diff --git a/.gitignore b/.gitignore index e9d114326b..2f02054dcb 100644 --- a/.gitignore +++ b/.gitignore @@ -26,3 +26,11 @@ tools/kconfig-frontends/kconfig-mconf packages cconfig.h GPUCache + +#cscope files +cscope.* +ncscope.* + +#ctag files +tags + diff --git a/.travis.yml b/.travis.yml index b191ae213c..dafebb91ea 100644 --- a/.travis.yml +++ b/.travis.yml @@ -12,7 +12,7 @@ before_script: # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && export RTT_EXEC_PATH=/usr/bin && arm-none-eabi-gcc --version || true" # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2014.05-28-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2014.05/bin && /opt/arm-2014.05/bin/arm-none-eabi-gcc --version || true" - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 && sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin && /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version || true" - - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/mips-sde-elf/mips-2012.09-98-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/mips-2012.09/bin && /opt/mips-2012.09/bin/mips-sde-elf-gcc --version || true" + - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/mips-sde-elf/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/mips-2016.05/bin && /opt/mips-2016.05/bin/mips-sde-elf-gcc --version || true" # - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true" # - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true" - export RTT_ROOT=`pwd` @@ -24,7 +24,7 @@ script: env: # - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build - RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm' -# - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm' @@ -33,6 +33,7 @@ env: # - RTT_BSP='bf533' # no scons - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm' @@ -58,8 +59,11 @@ env: - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='mini4020' # no scons # - RTT_BSP='nios_ii' # no scons + - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='pic32ethernet' # no scons - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='simulator' # x86 - RTT_BSP='stm32f0x' RTT_TOOL_CHAIN='sourcery-arm' @@ -76,6 +80,7 @@ env: - RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm' # - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc' # - RTT_BSP='upd70f3454' # iar # - RTT_BSP='x86' # x86 diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index d0cd0692fd..0000000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "C_Cpp.dimInactiveRegions": false, - "files.exclude": { - "**/.git": true, - "**/build": true, - "bsp" : true, - }, - "editor.renderWhitespace": "all" -} diff --git a/COPYING b/COPYING deleted file mode 100644 index d60c31a97a..0000000000 --- a/COPYING +++ /dev/null @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/ChangeLog.md b/ChangeLog.md index dbb58c957c..76bc6f80b2 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,3 +1,133 @@ +# RT-Thread v3.1.1 Change Log + +## Kernel + +* Support the configuration of the upward growth stack which is defined by the `ARCH_CPU_STACK_GROWS_UPWARD` macro. Because there are fewer ARCH for stacks growing upward, this configuration item does not display directly in menuconfig. When a CPU ARCH needs stacks growing upward, the configuration of `ARCH_CPU_STACK_GROWS_UPWARD` can be selected by BSP Kconfig file in default. +* Support for ARMCC V6 and later compiler (LLVM-based Compiler); currently it's mainly used in Keil MDK IDE. Please notes that the "Warnings" needs to use `Moderate Warnings` in project configuration in C/C++ (AC6) TAB; After using ARMCC v6, RT-Thread will add an additional `CLANG_ARM` macro definition; (liruncong, nongxiaoming, bernard) +* The `RT_USING_IDLE_HOOK` configuration in Kconfig becomes a separate configuration item, not limited to `RT_USING_HOOK`; (geniusgogo) + +## Components + +* Improve the PWM driver framework and add more interfaces. +* Fix the F_SETFL handling in ioctrl function; Fix the return value issue of fcntl function which is always 0 value. +* Fix the memheap object type issue when creating a ramfs object. +* Add power management framework for low power applications. +* Add multi-segment support for read and write operations in MC/SDIO driver framework (for stm32, you can choose a separate stm32_sdio package); (weety) +* Add ringblk_buf component for the block mode but in ringbuffer applications; +* Improve WLAN management framework with unified interfaces, management, commands, to provide more friendly support to developers and users; +* Add the conditional macro in the finsh when the MSH component is not enabled, even if the code files are compiled. +* Remove gdbstub and move to rt-thread packages. +* Upgrade and improve SAL and AT components: (linuxhan, eddylin83, slyant, luofanlu, Hubert Xie, Lawlieta, zhaojuntao, armink) + * Fix the none cleared issue when closing socket in SAL, which lead to the socket is always holding. + * Fix the `select()` issue for UDP communication in AT component. Add the receiving data handling to complete the clearing of received event; + * Add the errno value when receive data timeout in at_recvfrom function in the AT component. + * Add the receive data timeout handling in at_client_recv function in the AT component. +* Fix a possible issue in fputc function implementation when using microlib; +* Add gmtime_r implementation for ARMCC, IAR tool chain; +* Improve time function support in IAR and support 64bit time; (hichard) +* DHCPD's support for IPv6; +* Remove lwIP-1.3.2 porting and add lwIP-2.1.0 porting; lwIP-2.0.2 is still the default version. +* Add a lightweight ulog component and automatically replace the debug macro of the original rtdbg.h when it's enable. +* USB stack update + * HOST, optimize the USB HOST timeout mechanism; fix the un-alignment visit issue in F4xx-HAL USB host driver; + * Device: Add the check when class drivers are illegally registered; Fix the un-aligned access issue in some platforms; optimize CDC VCOM classes, add the timeout mechanism and ID definition. + +## BSP + +* Upgrade the wlan adaptor to the new version of Wi-Fi management framework in amebaz BSP. +* Add airkiss wifi configuration code to amebaz BSP. +* Update Apollo2 BSP with ADC, GPIO, I2C, PDM, SPI, UART and other drivers; (Haleyl) +* BeagleBone BSP is changed to main function mode, and adds Kconfig configuration file. +* DM365 BSP adds Kconfig configuration file; +* Update HiFive1 BSP and add more documentation. +* Update imx6sx BSP to main function mode, and add Kconfig configuration file. +* Change the old imxrt1052-evk BSP. The imxrt1052-related BSPs are classified into the `bsp/imxrt` directory; A touch framework is added to `bsp/imxrt`, and later will be moved into `components/drivers` directory; +* Improve stm32f4xx-HAL BSP with PWM, I2C, USB Host driver; (XuanZe, xuzhuoyi) +* Improve stm32f10x BSP with CAN driver and increase I2C driver; (wuhanstudio, AubrCool) +* Improve stm32f10x-HAL BSP with I2C, IWG, PWM, RTC and other drivers, improve UART driver; (XuanZe) +* Improve stm32f429-disco BSP and add I2C, LCD, Touch driver; (xuzhuoyi) +* Improve x86 BSP, support dlmodule function; (SASANO Takayoshi, parai) + +## Tool + +* Modify the building script to support Python 3; (Arda) +* Add `scons --pyconfig` mode, which has a TK UI configurator; (weety) +* Support for GNU GCC 7/8 version toolchains (The `-std=c99` is not added into C-compiler flags), but please note: PThreads component failed in 2.5 and new version of newlib. + +# RT-Thread 3.1.0 Change Log + +## Kernel + +* The main thread priority can be configured by Kconfig; +* Add the checking of kernel object type, which can effectively avoid the problem of continuing to use kernel objects after they are destroyed. +* Add the idle hook list to mount multiple idle hook, and can be configured by Kconfig. +* Add the device_ops operation set to reduce the footprint of device object. +* Remove the special memory operation in application module when using SLAB memory management algorithm. +* Move application module from the kernel to `libc/libdl`. +* Enhance the debug information output of `rtdbg.h` file. +* In Keil/IAR tool chain, the `RT_USED` is used to keep symbols and avoid to add more argument or section in link phrase. + +## Components + +* Remove all of external codes, which will be moved to packages in the future. +* Add initialization flag for shell, file system, network protocol stack etc to prevent repeated initialization; +* Enable the long file name feature of ELM FatFs in default. +* Change DFS FD to dynamic allocation mode. The maximum number of allocation is still DFS_FD_MAX. +* Add dfs_fdtable_get() function to get different fdtable; +* Add more DFS error messages, and provide easy to understand log when abnormal. +* Fix the disk format issue of FatFs file system when multiple FatFs file systems are mounted. +* Remove the folder enter feature in msh when input a folder name; +* Add `int finsh_set_prompt (const char * prompt);` routine for setting a custom prompt for msh; +* Add the VBUS configuration in Kconfig. +* Move the application module from kernel to `libc/libdl` component; +* Rewrite most of the management code for application module: replace the original object container with the object list; split the symbol resolution code into different processor architecture etc. +* Update the application module chapter in the programming guide, and change it into dynamic module chapter. +* Overwrite the exit() function of newlib to take over the processing of exit for a dlmodule. +* Add SAL (Socket Abstraction Layer) component for adapting different protocol stacks and network implementations, and update the relevant sections of the programming guide; +* Add AT component, including AT client, AT server and AT Socket function; +* Remove the poll/select API of DFS_NET and move them to SAL component. +* Remove the strong dependence of lwIP component for DFS_NET and replace it with Kconfig configuration in SAL. +* Add the DHCP server function with lwIP raw API; +* Fix the wait queue none-initialization issue in socket allocation of lwIP. +* When a thread is about to block on a wait queue, fix the wake up issue for `rt_wqueue_wakeup' is executed to wake up that thread; +* Add the PWM driver framework; +* Fix the sdio_irq_wakeup release issue in the MMC/SD framework. +* Fix the problem of DMA handling in the serial driver framework. +* Update SFUD to v1.0.6 version; + +## BSP + +* Fix the SP issue when hard fault occurs for ARM Cortex-M arch; +* Add C-Sky CK802 architecture porting; +* Add Realtek amebaz WiFi SOC (rtl8710bn) BSP; +* Update imxrt1052-evk firmware SDK to support B model chip. +* Fix the copying packets issue in the Godson 1C BSP when sending message. +* The Nuvoton m05x/m451 BSP are changed into the main() entry mode, and supports GCC compilation; +* Fix the inconsistency issue between touch range and LCD resolution in qemu-vexpress-a9. +* Add qemu-vexpress-gemini BSP for dual core A9 (RT-Thread + Linux) arch; +* Add the basic porting for Raspberry Pi 2B ; +* Add CAN and PWM drivers in stm32f4xx-HAL BSP; +* Optimize the GPIO driver in stm32f4xx-HAL BSP; +* Add UART3 driver in stm32f4xx-HAL BSP; +* Fix the I2C1 driver clock in stm32f10x BSP and WDG control interface. +* Add rt_hw_us_delay interface in stm32f10x-HAL BSP; +* Optimize the GPIO driver in stm32f10x-HAL BSP; +* Add GPIO driver and RTC driver in stm32f107 BSP; + +## Tool + +* ENV update to v1.0.0 final version. +* ENV added the China mirror for software package, which can speed up the software package download, update etc. +* Fix the ENV known bugs and enhance the interaction with users. +* Add building script to detect the version of GCC & newlib; +* Add building script to detect the version of armcc; +* Add `scons --dist` function to make distribution for a BSP. +* Add `scons - dist - strip' function to make a minimal files of distribution for a BSP. +* Add `ASFLAGS/LOCAL_ASFLAGS' parameters for defined a group and pass them to assembler; +* Fix some errors in building script under the Linux environment. +* Add the C-Sky CDK IDE project generation. +* Add `scons --target=vsc -s` to generate friendly configuration files for VSCode; + # RT-Thread 3.0.4 Change Log ## Kernel diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000000..261eeb9e9f --- /dev/null +++ b/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/README.md b/README.md index dd9112b59f..c83590872f 100644 --- a/README.md +++ b/README.md @@ -2,6 +2,7 @@ [中文页](README_zh.md) | +[![GitHub](https://img.shields.io/github/license/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases) [![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread) [![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) @@ -16,13 +17,13 @@ RT-Thread RTOS like a traditional real-time operating system. The kernel has rea * Device Driver; * Component; -* Application Module +* Dyanmic Module The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features. The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system). -The Appliation Module, or User Applicaion (UA) is a dyanmic loaded module, it can be compiled standalone without Kernel. Each UA has its own object container to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps). +The Dyanmic Module, formerly named as User Applicaion (UA) is a dyanmic loaded module or library, it can be compiled standalone without Kernel. Each Dyanmic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps). ## Board Support Package ## @@ -42,9 +43,19 @@ RT-Thread RTOS can support many architectures: ## License ## -RT-Thread RTOS is free software; you can redistribute it and/or modify it under terms of the GNU General Public License version 2 as published by the Free Software Foundation. RT-Thread RTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with RT-Thread; see file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. +RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v3.1.1. License and copyright information can be found within the code. -As a special exception, including RT-Thread RTOS header files in a file, instantiating RT-Thread RTOS generics or templates, or linking other files with RT-Thread RTOS objects to produce an executable application, does not by itself cause the resulting executable application to be covered by the GNU General Public License. This exception does not however invalidate any other reasons why the executable file might be covered by the GNU Public License. + /* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA). + +NOTE: + +RT-Thread using the Apache license v2.0 is only launched after the release of v3.1.1, and is still in preparation right now. ## Usage ## @@ -60,18 +71,18 @@ In SConstruct file: When you set these variables correctly, you can use command: - scons + scons under BSP directory to simplely compile RT-Thread RTOS. If you want to generate the IDE's project file, you can use command: - scons --target=mdk/mdk4/mdk5/iar/cb -s + scons --target=mdk/mdk4/mdk5/iar/cb -s -to generate the project file. +to generate the project file. -NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files. +NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files. ## Contribution ## -Please refer the contributors in the github. Thank all of RT-Thread Developers. +Please refer the contributors in the github. Thank all of RT-Thread Developers. diff --git a/README_zh.md b/README_zh.md index 61b157fc0b..56fe096963 100644 --- a/README_zh.md +++ b/README_zh.md @@ -31,7 +31,7 @@ RT-Thread包含了一个自有的、传统的硬实时内核：可抢占的多 更多的IoT软件包则以package方式被添加到RT-Thread系统中。 -应用模块，或者说用户应用（User Application，UA）是一个可动态加载的模块：它可以独立于RT-Thread固件而单独编译。一般的，每个UA都包含一个main函数入口；一个它自己的对象容器，用于管理这个应用的任务/信号量/消息队列等内核对象，创建、初始化、销毁等。更多关于UA的信息，请访问另外一个 [git 仓库](https://github.com/RT-Thread/rtthread-apps) 了解。 +应用模块，或者说用户应用（User Application，UA）是一个可动态加载的模块：它可以独立于RT-Thread固件而单独编译。一般的，每个UA都包含一个main函数入口；一个它自己的对象链表，用于管理这个应用的任务/信号量/消息队列等内核对象，创建、初始化、销毁等。更多关于UA的信息，请访问另外一个 [git 仓库](https://github.com/RT-Thread/rtthread-apps) 了解。 ## 支持的芯片架构 ## @@ -51,11 +51,19 @@ RT-Thread支持数种芯片体系架构，已经覆盖当前应用中的主流 ## 许可证 ## -RT-Thread is free software; you can redistribute it and/or modify it under terms of the GNU General Public License version 2 as published by the Free Software Foundation. RT-Thread RTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with RT-Thread; see file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. +RT-Thread从v3.1.1版本开始，是一个以Apache许可证2.0版本授权的开源软件，许可证信息以及版权信息一般的可以在代码首部看到： -As a special exception, including RT-Thread RTOS header files in a file, instantiating RT-Thread RTOS generics or templates, or linking other files with RT-Thread RTOS objects to produce an executable application, does not by itself cause the resulting executable application to be covered by the GNU General Public License. This exception does not however invalidate any other reasons why the executable file might be covered by the GNU Public License. + /* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ -RT-Thread始终以开源的方式发展，所有发布的代码都遵循GPLv2+许可证。注意，GPLv2+的意思是，它是GPLv2的一个修改版本，添加了一定的例外。简单的来说，当使用RT-Thread时，除了RT-Thread发布的源代码以外的代码，可以不用遵循GPLv2的方式开源代码。 +从2018/09/09开始，开发者提交PR需要签署贡献者许可协议（CLA）。 + +注意： + +以Apache许可协议v2.0版本授权仅在RT-Thread v3.1.1正式版发布之后才正式实施，当前依然在准备阶段（准备所有原有开发者签署CLA协议）。 ## 编译 ## diff --git a/bsp/allwinner_tina/drivers/drv_gpio.c b/bsp/allwinner_tina/drivers/drv_gpio.c index 70a4b3a3f1..2c3b6e1865 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.c +++ b/bsp/allwinner_tina/drivers/drv_gpio.c @@ -53,7 +53,7 @@ int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func) if (func & 0x8) { - dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__); + LOG_W("[line]:%d There is a warning with parameter input", __LINE__); return RT_EINVAL; } @@ -65,7 +65,7 @@ int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func) data |= func << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); return RT_EOK; } @@ -80,7 +80,7 @@ int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value) if (value & 0xE) { - dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__); + LOG_W("[line]:%d There is a warning with parameter input", __LINE__); return RT_EINVAL; } @@ -92,7 +92,7 @@ int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value) data |= value << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); return RT_EOK; } @@ -110,7 +110,7 @@ int gpio_get_value(enum gpio_port port, enum gpio_pin pin) data = readl(addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); return (data >> offset) & 0x01; } @@ -125,7 +125,7 @@ int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull p if (pull & 0xC) { - dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__); + LOG_W("[line]:%d There is a warning with parameter input", __LINE__); return RT_EINVAL; } @@ -138,7 +138,7 @@ int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull p data |= pull << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); return RT_EOK; } @@ -153,7 +153,7 @@ int gpio_set_drive_level(enum gpio_port port, enum gpio_pin pin, enum gpio_drv_l if (level & 0xC) { - dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__); + LOG_W("[line]:%d There is a warning with parameter input", __LINE__); return RT_EINVAL; } @@ -166,7 +166,7 @@ int gpio_set_drive_level(enum gpio_port port, enum gpio_pin pin, enum gpio_drv_l data |= level << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); return RT_EOK; } @@ -187,7 +187,7 @@ void gpio_direction_input(enum gpio_port port, enum gpio_pin pin) data |= IO_INPUT << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); } void gpio_direction_output(enum gpio_port port, enum gpio_pin pin, int value) @@ -208,7 +208,7 @@ void gpio_direction_output(enum gpio_port port, enum gpio_pin pin, int value) data |= IO_OUTPUT << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); } /********************************************************* ** IRQ @@ -237,7 +237,7 @@ void gpio_select_irq_clock(enum gpio_port port, enum gpio_irq_clock clock) data &= ~0x01; data |= clock; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d addr:%08x data:%08x\n", __LINE__, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d addr:%08x data:%08x", __LINE__, addr, *((rt_uint32_t *)addr)); } void gpio_set_debounce(enum gpio_port port, enum gpio_direction_type prescaler) @@ -253,7 +253,7 @@ void gpio_set_debounce(enum gpio_port port, enum gpio_direction_type prescaler) data &= ~(0x07 << 4); data |= prescaler << 4; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d addr:%08x data:%08x\n", __LINE__, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d addr:%08x data:%08x", __LINE__, addr, *((rt_uint32_t *)addr)); } void gpio_irq_enable(enum gpio_port port, enum gpio_pin pin) @@ -272,7 +272,7 @@ void gpio_irq_enable(enum gpio_port port, enum gpio_pin pin) data |= 0x1 << offset; writel(data, addr); gpio_select_irq_clock(port, GPIO_IRQ_HOSC_24MHZ); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); } void gpio_irq_disable(enum gpio_port port, enum gpio_pin pin) @@ -292,7 +292,7 @@ void gpio_irq_disable(enum gpio_port port, enum gpio_pin pin) data &= ~(0x1 << offset); writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); } void gpio_set_irq_type(enum gpio_port port, enum gpio_pin pin, enum gpio_irq_type irq_type) @@ -312,7 +312,7 @@ void gpio_set_irq_type(enum gpio_port port, enum gpio_pin pin, enum gpio_irq_ty data |= irq_type << offset; writel(data, addr); - dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr)); + LOG_D("[line]:%d offset:%d addr:%08x data:%08x", __LINE__, offset, addr, *((rt_uint32_t *)addr)); } static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_PORT_NUM]; @@ -353,7 +353,7 @@ static void gpio_irq_handler(int irq, void *param) { if ((pend & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) { - dbg_log(DBG_LOG, "do irq callback...\n", port, pin); + LOG_D("do irq callback...", port, pin); irq_def->irq_cb[pin](irq_def->irq_arg[pin]); } pin++; @@ -452,7 +452,7 @@ static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { - dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin); + LOG_E("pin:%d value wrongful", pin); return; } @@ -463,7 +463,7 @@ static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { - dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin); + LOG_E("pin:%d value wrongful", pin); return; } @@ -474,7 +474,7 @@ static int pin_read(struct rt_device *device, rt_base_t pin) { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { - dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin); + LOG_E("pin:%d value wrongful", pin); return 0; } @@ -485,7 +485,7 @@ static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { - dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin); + LOG_E("pin:%d value wrongful", pin); return RT_ERROR; } @@ -497,7 +497,7 @@ static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin) { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { - dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin); + LOG_E("pin:%d value wrongful", pin); return RT_ERROR; } @@ -510,7 +510,7 @@ rt_err_t pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t ena { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { - dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin); + LOG_E("pin:%d value wrongful", pin); return RT_ERROR; } diff --git a/bsp/allwinner_tina/drivers/drv_sdio.c b/bsp/allwinner_tina/drivers/drv_sdio.c index 08be4c1652..12cb437f42 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.c +++ b/bsp/allwinner_tina/drivers/drv_sdio.c @@ -99,7 +99,7 @@ static void mmc_delay_us(int us) static void mmc_dump_errinfo(unsigned int err) { - dbg_log(DBG_ERROR, "[err]:0x%08x, %s%s%s%s%s%s%s%s%s%s%s\n", + LOG_E("[err]:0x%08x, %s%s%s%s%s%s%s%s%s%s%s", err, err & SDXC_RespErr ? " RE" : "", err & SDXC_RespCRCErr ? " RCE" : "", @@ -130,7 +130,7 @@ static int mmc_update_clk(tina_mmc_t mmc) } if (!timeout) { - dbg_log(DBG_ERROR, "mmc update clk failed\n"); + LOG_E("mmc update clk failed"); return -RT_ERROR; } /* clean interrupt */ @@ -189,8 +189,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1]; } - dbg_log(DBG_LOG, "frag %d, remain %d, des[%d](%08x): " \ - "[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n", \ + LOG_D("frag %d, remain %d, des[%d](%08x): " \ + "[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x", \ i, remain, des_idx, (unsigned int)&pdes[des_idx], (unsigned int)((unsigned int*)&pdes[des_idx])[0], (unsigned int)((unsigned int*)&pdes[des_idx])[1], (unsigned int)((unsigned int*)&pdes[des_idx])[2], (unsigned int)((unsigned int*)&pdes[des_idx])[3]); @@ -243,7 +243,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) if (timeout <= 0) { - dbg_log(DBG_ERROR, "write data by cpu failed status:0x%08x\n", mmc->star_reg); + LOG_E("write data by cpu failed status:0x%08x", mmc->star_reg); return -RT_ERROR; } mmc->fifo_reg = buff[i]; @@ -258,7 +258,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) if (timeout <= 0) { - dbg_log(DBG_ERROR, "read data by cpu failed status:0x%08x\n", mmc->star_reg); + LOG_E("read data by cpu failed status:0x%08x", mmc->star_reg); return -RT_ERROR; } buff[i] = mmc->fifo_reg; @@ -279,7 +279,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) mmc->ckcr_reg = rval; if (mmc_update_clk(mmc) != RT_EOK) { - dbg_log(DBG_ERROR, "clk update fail line:%d\n", __LINE__); + LOG_E("clk update fail line:%d", __LINE__); return -RT_ERROR; } @@ -298,7 +298,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) mmc->ckcr_reg = rval; if(mmc_update_clk(mmc) != RT_EOK) { - dbg_log(DBG_ERROR, "clk update fail line:%d\n", __LINE__); + LOG_E("clk update fail line:%d", __LINE__); return -RT_ERROR; } @@ -307,12 +307,12 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) static rt_err_t mmc_set_ios(tina_mmc_t mmc, int clk, int bus_width) { - dbg_log(DBG_LOG, "mmc set io bus width:%d clock:%d\n", \ + LOG_D("mmc set io bus width:%d clock:%d", \ (bus_width == MMCSD_BUS_WIDTH_8 ? 8 : (bus_width == MMCSD_BUS_WIDTH_4 ? 4 : 1)), clk); /* change clock */ if (clk && (mmc_config_clock(mmc, clk) != RT_EOK)) { - dbg_log(DBG_ERROR, "update clock failed\n"); + LOG_E("update clock failed"); return -RT_ERROR; } @@ -349,13 +349,13 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) status = mmc->star_reg; while (status & (1 << 9)) { - dbg_log(DBG_LOG, "note: check card busy\n"); + LOG_D("note: check card busy"); status = mmc->star_reg; if (!timeout--) { err = -1; - dbg_log(DBG_ERROR, "mmc cmd12 busy timeout data:0x%08x\n", status); + LOG_E("mmc cmd12 busy timeout data:0x%08x", status); return err; } mmc_delay_us(1); @@ -397,7 +397,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) mmc->bycr_reg = bytecnt; } - dbg_log(DBG_LOG, "cmd %d(0x%08x), arg 0x%08x\n", cmd->cmd_code, cmdval | cmd->cmd_code, cmd->arg); + LOG_D("cmd %d(0x%08x), arg 0x%08x", cmd->cmd_code, cmdval | cmd->cmd_code, cmd->arg); mmc->cagr_reg = cmd->arg; if (!data) { @@ -412,7 +412,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) */ if (data) { - dbg_log(DBG_LOG, "mmc trans data %d bytes addr:0x%08x\n", bytecnt, data); + LOG_D("mmc trans data %d bytes addr:0x%08x", bytecnt, data); #ifdef CONFIG_MMC_USE_DMA if (bytecnt > 64) { @@ -478,13 +478,13 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) cmd->resp[2] = mmc->resp1_reg; cmd->resp[1] = mmc->resp2_reg; cmd->resp[0] = mmc->resp3_reg; - dbg_log(DBG_LOG, "mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + LOG_D("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x", cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); } else { cmd->resp[0] = mmc->resp0_reg; - dbg_log(DBG_LOG, "mmc resp 0x%08x\n", cmd->resp[0]); + LOG_D("mmc resp 0x%08x", cmd->resp[0]); } out: @@ -516,16 +516,16 @@ out: mmc->gctl_reg = mmc->gctl_reg | 0x80000000; mmc->dbgc_reg = 0xdeb; timeout = 1000; - dbg_log(DBG_LOG, "Read remain data\n"); + LOG_D("Read remain data"); while (mmc->bbcr_reg < 512) { unsigned int tmp = mmc->fifo_reg; tmp = tmp; - dbg_log(DBG_LOG, "Read data 0x%08x, bbcr 0x%04x\n", tmp, mmc->bbcr_reg); + LOG_D("Read data 0x%08x, bbcr 0x%04x", tmp, mmc->bbcr_reg); mmc_delay_us(1); if (!(timeout--)) { - dbg_log(DBG_ERROR, "Read remain data timeout\n"); + LOG_E("Read remain data timeout"); break; } } @@ -536,7 +536,7 @@ out: mmc_update_clk(mmc); cmd->err = -RT_ETIMEOUT; - dbg_log(DBG_ERROR, "mmc cmd %d err\n", cmd->cmd_code); + LOG_E("mmc cmd %d err", cmd->cmd_code); } mmc->gctl_reg &= ~(0x1 << 4); @@ -744,13 +744,13 @@ int tina_sdio_init(void) host = mmcsd_alloc_host(); if (!host) { - dbg_log(DBG_ERROR, "alloc host failed\n"); + LOG_E("alloc host failed"); goto err; } if (rt_sem_init(&_sdio_drv.rt_sem, "sdio_sem", RT_NULL, RT_IPC_FLAG_FIFO)) { - dbg_log(DBG_ERROR, "sem init failed\n"); + LOG_E("sem init failed"); goto err; } _sdio_drv.mmc_des = (tina_mmc_t)MMC0_BASE_ADDR; diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi.c b/bsp/allwinner_tina/drivers/spi/drv_spi.c index bf5da9de58..6e76cbec3e 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi.c +++ b/bsp/allwinner_tina/drivers/spi/drv_spi.c @@ -33,25 +33,22 @@ #define SPI_BUS_MAX_CLK (30 * 1000 * 1000) +//#define DEBUG + #define DBG_ENABLE #define DBG_SECTION_NAME "SPI" +#ifdef DEBUG +#define DBG_LEVEL DBG_LOG +#else #define DBG_LEVEL DBG_WARNING +#endif /* DEBUG */ #define DBG_COLOR #include #ifdef RT_USING_SPI -//#define DEBUG - #define ARR_LEN(__N) (sizeof(__N) / sizeof(__N[0])) -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - - #define __SPI_STATIC_INLINE__ rt_inline /* @@ -296,7 +293,7 @@ void SPI_DMA(SPI_T *spi, bool txEn, bool rxEn) * @brief */ __SPI_STATIC_INLINE__ -void SPI_SetTxFifoThreshold(SPI_T *spi, uint8_t threshold) +void SPI_SetTxFifoThreshold(SPI_T *spi, rt_uint8_t threshold) { HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_TX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_TX_TRIG_LEVEL_SHIFT); } @@ -305,7 +302,7 @@ void SPI_SetTxFifoThreshold(SPI_T *spi, uint8_t threshold) * @brief */ __SPI_STATIC_INLINE__ -void SPI_SetRxFifoThreshold(SPI_T *spi, uint8_t threshold) +void SPI_SetRxFifoThreshold(SPI_T *spi, rt_uint8_t threshold) { HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_RX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_RX_TRIG_LEVEL_SHIFT); } @@ -314,18 +311,18 @@ void SPI_SetRxFifoThreshold(SPI_T *spi, uint8_t threshold) * @brief */ __SPI_STATIC_INLINE__ -uint8_t SPI_GetTxFifoCounter(SPI_T *spi) +rt_uint8_t SPI_GetTxFifoCounter(SPI_T *spi) { - return (uint8_t)((spi->FST & SPI_FST_TF_CNT_MASK) >> SPI_FST_TF_CNT_SHIFT); + return (rt_uint8_t)((spi->FST & SPI_FST_TF_CNT_MASK) >> SPI_FST_TF_CNT_SHIFT); } /* * @brief */ __SPI_STATIC_INLINE__ -uint8_t SPI_GetRxFifoCounter(SPI_T *spi) +rt_uint8_t SPI_GetRxFifoCounter(SPI_T *spi) { - return (uint8_t)((spi->FST & SPI_FST_RF_CNT_MASK) >> SPI_FST_RF_CNT_SHIFT); + return (rt_uint8_t)((spi->FST & SPI_FST_RF_CNT_MASK) >> SPI_FST_RF_CNT_SHIFT); } /* @@ -350,7 +347,7 @@ void SPI_DisableDualMode(SPI_T *spi) * @brief */ __SPI_STATIC_INLINE__ -void SPI_SetInterval(SPI_T *spi, uint16_t nSCLK) +void SPI_SetInterval(SPI_T *spi, rt_uint16_t nSCLK) { HAL_MODIFY_REG(spi->WAIT, SPI_WAIT_WCC_MASK, nSCLK << SPI_WAIT_WCC_SHIFT); } @@ -358,9 +355,9 @@ void SPI_SetInterval(SPI_T *spi, uint16_t nSCLK) /* * @brief */ -static void SPI_SetClkDiv(SPI_T *spi, uint16_t div) +static void SPI_SetClkDiv(SPI_T *spi, rt_uint16_t div) { - uint8_t n = 0; + rt_uint8_t n = 0; if (div < 1) { return; @@ -401,7 +398,7 @@ void SPI_SetDataSize(SPI_T *spi, rt_uint32_t data_size, rt_uint32_t dummy_size) * @brief */ __SPI_STATIC_INLINE__ -void SPI_Write(SPI_T *spi, uint8_t *data) +void SPI_Write(SPI_T *spi, rt_uint8_t *data) { HAL_REG_8BIT(&spi->TXD) = *data; } @@ -410,7 +407,7 @@ void SPI_Write(SPI_T *spi, uint8_t *data) * @brief */ __SPI_STATIC_INLINE__ -void SPI_Read(SPI_T *spi, uint8_t *data) +void SPI_Read(SPI_T *spi, rt_uint8_t *data) { *data = HAL_REG_8BIT(&spi->RXD); } @@ -419,18 +416,18 @@ void SPI_Read(SPI_T *spi, uint8_t *data) * @brief */ __SPI_STATIC_INLINE__ -uint8_t *SPI_TxAddress(SPI_T *spi) +rt_uint8_t *SPI_TxAddress(SPI_T *spi) { - return (uint8_t *)&spi->TXD; + return (rt_uint8_t *)&spi->TXD; } /* * @brief */ __SPI_STATIC_INLINE__ -uint8_t *SPI_RxAddress(SPI_T *spi) +rt_uint8_t *SPI_RxAddress(SPI_T *spi) { - return (uint8_t *)&spi->RXD; + return (rt_uint8_t *)&spi->RXD; } /* private rt-thread spi ops function */ @@ -451,30 +448,30 @@ static rt_err_t configure(struct rt_spi_device *device, struct tina_spi *_spi_info = (struct tina_spi *)spi_bus->parent.user_data; SPI_T *spi = _spi_info->spi; - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); - DEBUG_PRINTF("spi address: %08X\n", (rt_uint32_t)spi); + LOG_D("spi address: %08X", (rt_uint32_t)spi); SPI_Disable(spi); SPI_Reset(spi); SPI_ResetRxFifo(spi); SPI_ResetTxFifo(spi); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); /* data_width */ if (configuration->data_width != 8) { - DEBUG_PRINTF("error: data_width is %d\n", configuration->data_width); + LOG_D("error: data_width is %d", configuration->data_width); return RT_EIO; } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); SPI_SetDuplex(spi, SPI_TCTRL_DHB_FULL_DUPLEX); SPI_SetMode(spi, SPI_CTRL_MODE_MASTER); @@ -510,7 +507,7 @@ static rt_err_t configure(struct rt_spi_device *device, rt_uint32_t max_hz; rt_uint32_t div; - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); max_hz = configuration->max_hz; @@ -520,14 +517,14 @@ static rt_err_t configure(struct rt_spi_device *device, } spi_clock = ahb_get_clk(); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); div = (spi_clock + max_hz - 1) / max_hz; - dbg_log(DBG_LOG, "configuration->max_hz: %d\n", configuration->max_hz); - dbg_log(DBG_LOG, "max freq: %d\n", max_hz); - dbg_log(DBG_LOG, "spi_clock: %d\n", spi_clock); - dbg_log(DBG_LOG, "div: %d\n", div); + LOG_D("configuration->max_hz: %d", configuration->max_hz); + LOG_D("max freq: %d", max_hz); + LOG_D("spi_clock: %d", spi_clock); + LOG_D("div: %d", div); SPI_SetClkDiv(spi, div / 2); } /* baudrate */ @@ -536,7 +533,7 @@ static rt_err_t configure(struct rt_spi_device *device, SPI_SetDataSize(spi, 0, 0); SPI_Enable(spi); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); return RT_EOK; }; @@ -552,19 +549,19 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *mes RT_ASSERT(device != NULL); RT_ASSERT(message != NULL); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); - DEBUG_PRINTF("spi_info: %08X\n", (rt_uint32_t)_spi_info); - DEBUG_PRINTF("spi address: %08X\n", (rt_uint32_t)spi); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); + LOG_D("spi_info: %08X", (rt_uint32_t)_spi_info); + LOG_D("spi address: %08X", (rt_uint32_t)spi); /* take CS */ if (message->cs_take) { SPI_ManualChipSelect(spi, tina_spi_cs->cs); SPI_SetCsLevel(spi, false); - DEBUG_PRINTF("spi take cs\n"); + LOG_D("spi take cs"); } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); { if ((config->data_width <= 8) && (message->length > 0)) @@ -574,7 +571,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *mes rt_uint32_t tx_size = message->length; rt_uint32_t rx_size = message->length; - DEBUG_PRINTF("spi poll transfer start: %d\n", tx_size); + LOG_D("spi poll transfer start: %d", tx_size); SPI_ResetTxFifo(spi); SPI_ResetRxFifo(spi); @@ -582,12 +579,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *mes SPI_StartTransmit(spi); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); while (tx_size > 0 || rx_size > 0) { - uint8_t tx_data = 0xFF; - uint8_t rx_data = 0xFF; + rt_uint8_t tx_data = 0xFF; + rt_uint8_t rx_data = 0xFF; while ((SPI_GetTxFifoCounter(spi) < SPI_FIFO_SIZE) && (tx_size > 0)) { @@ -611,25 +608,25 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *mes } } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); if ((tx_size != 0) || (rx_size != 0)) { - DEBUG_PRINTF("spi_tx_rx error with tx count = %d, rx count = %d.\n", tx_size, rx_size); + LOG_D("spi_tx_rx error with tx count = %d, rx count = %d.", tx_size, rx_size); return 0; } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); while (SPI_IntState(spi, SPI_INT_TRANSFER_COMPLETE) == 0); SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); - DEBUG_PRINTF("spi poll transfer finsh\n"); + LOG_D("spi poll transfer finsh"); } else if (config->data_width > 8) { - DEBUG_PRINTF("data width: %d\n", config->data_width); + LOG_D("data width: %d", config->data_width); RT_ASSERT(NULL); } } @@ -638,7 +635,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *mes if (message->cs_release) { SPI_SetCsLevel(spi, true); - DEBUG_PRINTF("spi release cs\n"); + LOG_D("spi release cs"); } return message->length; @@ -676,7 +673,7 @@ rt_err_t tina_spi_bus_register(SPI_T *spi, const char *spi_bus_name) { int i; - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); RT_ASSERT(spi_bus_name != RT_NULL); @@ -688,67 +685,67 @@ rt_err_t tina_spi_bus_register(SPI_T *spi, const char *spi_bus_name) bus_gate_clk_enalbe(spis[i].spi_gate); spis[i].spi_bus->parent.user_data = (void *)&spis[i]; - DEBUG_PRINTF("bus addr: %08X\n", (rt_uint32_t)spis[i].spi_bus); - DEBUG_PRINTF("user_data: %08X\n", (rt_uint32_t)spis[i].spi_bus->parent.user_data); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("bus addr: %08X", (rt_uint32_t)spis[i].spi_bus); + LOG_D("user_data: %08X", (rt_uint32_t)spis[i].spi_bus->parent.user_data); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &tina_spi_ops); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); return RT_EOK; } } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); return RT_ERROR; } int rt_hw_spi_init(void) { - DEBUG_PRINTF("register spi bus\n"); + LOG_D("register spi bus"); #ifdef TINA_USING_SPI0 /* register spi bus */ { rt_err_t result; - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); gpio_set_func(GPIO_PORT_C, GPIO_PIN_0, IO_FUN_1); gpio_set_func(GPIO_PORT_C, GPIO_PIN_2, IO_FUN_1); gpio_set_func(GPIO_PORT_C, GPIO_PIN_3, IO_FUN_1); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); result = tina_spi_bus_register((SPI_T *)SPI0_BASE_ADDR, "spi0"); if (result != RT_EOK) { - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); return result; } } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); /* attach cs */ { static struct rt_spi_device spi_device; static struct tina_spi_cs spi_cs; rt_err_t result; - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); spi_cs.cs = SPI_TCTRL_SS_SEL_SS0; - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); gpio_set_func(GPIO_PORT_C, GPIO_PIN_1, IO_FUN_1); - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); result = rt_spi_bus_attach_device(&spi_device, "spi00", "spi0", (void *)&spi_cs); if (result != RT_EOK) { - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); return result; } } - DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__); + LOG_D("%s -> %d", __FUNCTION__, __LINE__); #endif #ifdef TINA_USING_SPI1 @@ -763,12 +760,12 @@ int rt_hw_spi_init(void) result = tina_spi_bus_register((SPI_T *)SPI1_BASE_ADDR, "spi1"); if (result != RT_EOK) { - DEBUG_PRINTF("register spi bus faild: %d\n", result); + LOG_D("register spi bus faild: %d", result); return result; } } - DEBUG_PRINTF("attach cs\n"); + LOG_D("attach cs"); /* attach cs */ { static struct rt_spi_device spi_device; @@ -781,7 +778,7 @@ int rt_hw_spi_init(void) result = rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)&spi_cs); if (result != RT_EOK) { - DEBUG_PRINTF("attach cs faild: %d\n", result); + LOG_D("attach cs faild: %d", result); return result; } } diff --git a/bsp/amebaz/.config b/bsp/amebaz/.config index 7745397107..4a513007e7 100644 --- a/bsp/amebaz/.config +++ b/bsp/amebaz/.config @@ -13,15 +13,24 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_DEBUG=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -CONFIG_RT_DEBUG_THREAD=0 CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -53,13 +62,14 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="dbg" -# CONFIG_RT_USING_MODULE is not set # # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y -# CONFIG_RT_USING_USER_MAIN is not set +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -82,7 +92,7 @@ CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_USING_MSH_ONLY=y CONFIG_FINSH_ARG_MAX=10 # @@ -94,26 +104,49 @@ CONFIG_FINSH_ARG_MAX=10 # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PIN is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set -CONFIG_RT_USING_WIFI=y -CONFIG_RT_USING_WLAN_STA=y -CONFIG_RT_USING_WLAN_AP=y -CONFIG_WIFI_DEVICE_STA_NAME="w0" -CONFIG_WIFI_DEVICE_AP_NAME="ap" # CONFIG_RT_USING_AUDIO is not set +# +# Using WiFi +# +CONFIG_RT_USING_WIFI=y +CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0" +CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1" +CONFIG_RT_WLAN_DEFAULT_PROT="lwip" +CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 +CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 +CONFIG_RT_WLAN_SSID_MAX_LENGTH=32 +CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32 +CONFIG_RT_WLAN_SCAN_SORT=y +CONFIG_RT_WLAN_CFG_INFO_MAX=3 +CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan_job" +CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048 +CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=22 +CONFIG_RT_WLAN_DEV_EVENT_NUM=2 +# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set +CONFIG_RT_WLAN_DEBUG=y +CONFIG_RT_WLAN_CMD_DEBUG=y +# CONFIG_RT_WLAN_MGNT_DEBUG is not set +# CONFIG_RT_WLAN_DEV_DEBUG is not set +# CONFIG_RT_WLAN_PROT_DEBUG is not set +# CONFIG_RT_WLAN_CFG_DEBUG is not set +# CONFIG_RT_WLAN_LWIP_DEBUG is not set + # # Using USB # @@ -127,15 +160,21 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set # -# Network stack +# Network # +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + # # light weight TCP/IP stack # CONFIG_RT_USING_LWIP=y -CONFIG_RT_USING_LWIP141=y -# CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP_IPV6 is not set CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -178,12 +217,22 @@ CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set # # Modbus master and slave stack # # CONFIG_RT_USING_MODBUS is not set -# CONFIG_LWIP_USING_DHCPD is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +CONFIG_LWIP_USING_DHCPD=y +CONFIG_DHCPD_SERVER_IP="192.168.169.1" +CONFIG_DHCPD_USING_ROUTER=y +# CONFIG_LWIP_USING_CUSTOMER_DNS_SERVER is not set # # VBUS(Virtual Software BUS) @@ -212,7 +261,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set # # Wi-Fi @@ -230,7 +278,16 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# # CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set # # security packages @@ -242,6 +299,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set @@ -258,6 +316,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set # # system packages @@ -271,22 +330,29 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set CONFIG_PKG_USING_REALTEK_AMEBA=y CONFIG_PKG_REALTEK_AMEBA_PATH="/packages/peripherals/realtek_ameba" CONFIG_PKG_USING_REALTEK_AMEBA_LATEST_VERSION=y # CONFIG_PKG_USING_REALTEK_AMEBA_V100 is not set CONFIG_PKG_REALTEK_AMEBA_VER="latest" -# CONFIG_PKG_USING_CC3200_SDK is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set # # miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set @@ -298,17 +364,57 @@ CONFIG_PKG_REALTEK_AMEBA_VER="latest" # # sample package # -# CONFIG_PKG_USING_SAMPLES is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # # example package: hello # # CONFIG_PKG_USING_HELLO is not set +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set + +# +# Test Packages of RealThread +# +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set + # # Env config # # CONFIG_SYS_AUTO_UPDATE_PKGS is not set # CONFIG_SYS_CREATE_MDK_IAR_PROJECT is not set # CONFIG_SYS_PKGS_DOWNLOAD_ACCELERATE is not set -CONFIG_RT_USING_UART0=y + +# +# External Libraries +# +CONFIG_RT_USING_SMARTCONFIG_LIB=y +# CONFIG_BSP_USING_UART0 is not set +CONFIG_BSP_USING_WIFI=y diff --git a/bsp/amebaz/Kconfig b/bsp/amebaz/Kconfig index 7c35a1cc66..5e639f4e5f 100644 --- a/bsp/amebaz/Kconfig +++ b/bsp/amebaz/Kconfig @@ -26,10 +26,7 @@ config $ENV_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "$ENV_DIR/tools/scripts/cmds/Kconfig" - -config RT_USING_UART0 - bool "Using RT_USING_UART0" - default y +source "$BSP_DIR/libraries/Kconfig" +source "$BSP_DIR/drivers/Kconfig" select PKG_USING_REALTEK_AMEBA - diff --git a/bsp/amebaz/README.md b/bsp/amebaz/README.md index d2c0b4013e..5bc1d60426 100644 --- a/bsp/amebaz/README.md +++ b/bsp/amebaz/README.md @@ -1,9 +1,8 @@ # amebaz on RT-Thread -## 1. 简介 +## 1 简介 -amebaz 是由Realtek推出的Cortex-M4内核的WiFi SOC芯片rtl8710b系列 -包括如下硬件特性： +amebaz 是由Realtek推出的Cortex-M4内核的WiFi SOC芯片，属于rtl8710b系列。硬件特性如下： | 硬件 | 描述 | | -- | -- | @@ -11,25 +10,42 @@ amebaz 是由Realtek推出的Cortex-M4内核的WiFi SOC芯片rtl8710b系列 |CPU| Cortex-M4 | |主频| 125MHz | -## 2. 编译说明 - +## 2 编译说明 | 环境 | 说明 | | ------------ | ------------------------------------------------------------ | | PC操作系统 | Linux/MacOS/Windows | -| 编译器 | arm-none-eabi-gcc version 6.3.1 20170620 (release)/iar | -| 构建工具 | scons/iar | +| 编译器 | arm-none-eabi-gcc version 6.3.1 20170620 (release) | +| 构建工具 | scons | | 依赖软件环境 | Env工具/(IAR或arm-none-eabi-gcc)/git/调试器驱动 | -1) 下载源码 +## 3 下载源码 ```bash git clone https://github.com/RT-Thread/rt-thread.git ``` -2) 配置工程并准备env +## 4 环境准备 -（Linux/Mac） +### 4.1 Windows 环境准备 + +Windows环境下有两种开发环境，`GCC toolchain` 和 `IAR IDE`，根据不同的需求自行选择。 + +#### 4.1.1 IAR 发开环境 + +IAR 开发环境需要开发者自己安装软件，安装过程这里就不特别说明了。amebaz工程当前仅支持 `IAR 7.X` 的版本。 + +#### 4.4.2 GCC 开发环境 + +GCC开发使用 RT-Thread 官方提供的 env 工具，该工具集成 GCC 工具链，还具有编译构建环境、图形化系统配置及软件包管理功能。 + +下载地址：[点击下载env工具](https://www.rt-thread.org/page/download.html) + +第一次使用env工具的开发者可以去这里查看教程：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/rtthread-development-guide/rtthread-tool-manual/env/env-user-manual/)。 + +### 4.2 Linux/Mac 环境准备 + +Linux/Mac 仅支持 GCC 工具链。 ```bash cd rt-thread/bsp/amebaz @@ -38,11 +54,17 @@ amebaz 是由Realtek推出的Cortex-M4内核的WiFi SOC芯片rtl8710b系列 pkgs --upgrade ``` -（Windows） +## 5 配置工程（可选） ->在[RT-Thread官网][1]下载ENV工具包 +### 5.1 Windows 配置工程 -3) 配置芯片型号 +配置工程，需要在相应的工程目录下使用 `menuconfig` 命令打开图形界面，开发者根据自己的需求开关功能组件。 + +```bash + menuconfig +``` + +### 5.2 Linux/Mac 配置工程 （Linux/Mac） @@ -50,56 +72,44 @@ amebaz 是由Realtek推出的Cortex-M4内核的WiFi SOC芯片rtl8710b系列 scons --menuconfig ``` -（Windows(ENV环境中)） +## 6 更新软件包 -```bash - menuconfig -``` - -在menuconfig页面配置并选择对应的芯片型号，若开发环境为IAR，则需要生成工程 - -4) 下载package - -amebaz配套的驱动库以package形式提供，故需先下载对应的package(realtek-ameba)，请使用env下载package +amebaz 配套的驱动库以 package 形式提供，故需先下载对应的 package(realtek-ameba)，在工程目录下，使用下面命令下载软件包。 ```bash pkgs --update ``` -5) 生成工程(Mac/Linux下请跳过此步骤) +## 7 编译 -（Windows IAR） +### 7.1 Windows 编译工程 + +#### 7.1.1 IAR 编译工程 + +先打开工程目录下的IAR工程（project.eww），然后单击 Project 选项卡，单击 Rebuild All 选项，进行编译 + +![ ](figures/iar_build.png) + +#### 7.1.2 GCC 编译工程 + +可以使用env编译工程，无需设置GCC工具链路径，直接在 rt-thread/bsp/amebaz 工程目录下输入 `scons` 编译即可。编译完成后，在工程目录下生成 `image2_all_ota1.bin` 文件。 ```bash - SET RTT_CC=iar - scons --target=iar -s + scons ``` -*该板级支持包不支持生成mdk的工程 +### 7.2 Linux/Mac 编译工程 - -6) 编译 - -使用IAR请参见对应教程 - -（Windows arm-none-eabi-gcc） -使用以下指令设置gcc路径 - -```bash - SET RTT_EXEC_PATH=[GCC路径] -``` - -（Linux/Mac arm-none-eabi-gcc） -使用以下指令设置gcc路径 +如果没有配置GCC路径的环境变量，则需要使用以下指令设置gcc路径。 ```bash export RTT_EXEC_PATH=[GCC路径] ``` -编译（WindowsLinux/Mac arm-none-eabi-gcc） +设置 GCC 路径后，使用 `scons` 编译工程。 ```bash - scons -j4 + scons ``` 出现下列信息即为编译成功 @@ -128,35 +138,153 @@ Done... scons: done building targets. ``` -如果编译正确无误，会产生image2_all_ota1.bin文件。 +如果编译正确无误，会在工程目录下生成 image2_all_ota1.bin 文件。 -## 3. 烧写及执行 +## 8 烧写及执行 -烧写可以使用仿真器 串口等多种方式 此处不再赘述 +### 8.1 IAR下载 -### 3.1 运行结果 +下载程序分为两部分： -如果编译 & 烧写无误，会在专用日志串口*上看到RT-Thread的启动logo信息： +（a）先使用jlink工具正确连接A14(CLK),A15(TMS),GND,VCC引脚 + +（b）打开 IAR 工程并完成编译后，单击 Project 选项卡下 Download 选项，选择 Download active application 下载程序。 + +![IAR下载程序](figures/iar_download.png) + +（c）短按复位按钮，连接串口查看调试信息 + +### 8.2 串口下载 + +串口下载分为三个步骤 + +（a）板子进入下载模式 + +板子使用 `micros usb` 上电，然后按住 `FLASH` 键不放手，短按 `RST` 键，松开 `RST` 和 `FLASH` 键进入下载模式。 + +（b）配置下载工具 + +打开 Image Tool 下载工具配置使用，选择 `micros usb` 所对应的串口端口，选择波特率，默认波特率 1.5Mbps，然后打开串口端口，如下载工具图“①”所示 + +![串口下载程序](figures/image-tool_v2.2.0.png) + +boot选择工程提供的 `boot_all.bin`, OTA1 选择生成的 image2_all_ota1.bin 文件（通常在工程目录下），并且注意在这两个选项前面打勾确认，其他默认即可，如下载工具图“②”。 + +（c）下载程序 + +按下 Download（如下载工具图 “③”），即可开始下载程序，并且可以从日志窗口查看到下载信息。 + +## 9 运行 + +下载程序后，连接串口（默认使用板子上 `micro usb`），打开串口工具，配置串口波特率 115200，数据位 8 位，停止位 1 位，无校验，无流控；短按 `RST` 键复位，串口将输出调试信息，如下所示： ```bash \ | / - RT - Thread Operating System - / | \ 3.0.4 build May 15 2018 + / | \ 3.1.1 build Oct 25 2018 2006 - 2018 Copyright by rt-thread team -msh /> +lwIP-2.0.2 initialized! + +Initializing WIFI ... +LDO Mode, BD_Info: 0 + +LDO Mode, BD_Info: 0 + +WIFI initialized +[I/WIFI] amebaz_wifi_start success +build time: Oct 25 2018 10:52:02 +Hello RT-Thread! +[I/WLAN.dev] wlan init success +[I/WLAN.lwip] eth device init ok name:w0 +msh > ``` -*默认串口 +## 10 WIFI简单使用 +### wifi扫描命令 -## 4. 驱动支持情况及计划 +wifi 扫描命令格式如下 + +```bash + wifi scan +``` + +命令说明 + +| 字段 | 描述 | +| ---- | ------------------------ | +| wifi | 有关wifi命令都以wifi开头 | +| scan | wifi执行扫描动作 | + +在调试工具中输入该命令，即可进行 wifi 命令扫描，调试信息如下 + +```bash +scan ap down + SSID MAC security rssi chn Mbps +------------------------------- ----------------- -------------- ---- --- ---- +NEO-shanghai-ap2 58:66:ba:a1:ee:71 WPA2_TKIP_PSK -74 11 0 +WQ1 88:25:93:94:51:54 WPA2_AES_PSK -76 13 0 +shyc1 a0:40:a0:a3:e8:c9 WPA2_AES_PSK -77 13 0 +KVIP 70:65:82:3b:71:43 WPA2_AES_PSK -83 11 0 +YST2016 88:25:93:c6:67:d1 WPA2_TKIP_PSK -84 4 0 +``` + +> 注：wifi 有关的命令，均以wifi开头。 + +### wifi 接入 + +接入 wifi 之前，先介绍一下其接入的命令 ，如下 + +```bash + wifi join ssid 123456789 +``` + +命令说明 + +| 字段 | 描述 | +| --------- | ---------------------------------- | +| wifi | 有关wifi命令都以wifi开头 | +| join | wifi执行连接动作 | +| ssid | 热点的名字 | +| 123456789 | 热点的密码，没有密码可不输入这一项 | + +了解上述命令，并且成功完成前面步骤，在串口中输入 `wifi w0 join realthread_VIP 123456789` ，如下日志表示连接成功 + +```bash + +WIFI wlan0 Setting: +============================== + MODE => STATION + SSID => realthread_VIP + CHANNEL => 6 + SECURITY => AES + PASSWORD => 123456789 +[I/WLAN.mgnt] wifi connect success ssid:realthread_VIP + +``` + +另外，提供一个简单的测试使用命令，查询设备IP地址命令：ifconfig。 + +```bash +network interface: w0 (Default) +MTU: 1500 +MAC: 00 e0 4c d5 ac 46 +FLAGS: UP LINK_UP ETHARP BROADCAST +ip address: 172.16.200.110 +gw address: 172.16.200.1 +net mask : 255.255.255.0 +dns server #0: 172.16.200.1 +dns server #1: 223.5.5.5 +``` + +## 驱动支持情况及计划 | 驱动 | 支持情况 | 备注 | | ---------- | :------: | :--------------------------: | -| UART | 支持 | UART0 | +| UART | 支持 | UART0 | +| WLAN | 部分支持 | 仅支持STA模式 | - -## 5. 联系人信息 +## 联系人信息 维护人: [flyingcys][4] < [flyingcys@163.com][5] > diff --git a/bsp/amebaz/applications/main.c b/bsp/amebaz/applications/main.c index 2f304b9503..381b026867 100644 --- a/bsp/amebaz/applications/main.c +++ b/bsp/amebaz/applications/main.c @@ -15,19 +15,12 @@ #include #include - -/** - * @addtogroup ameba - */ - -/*@{*/ +#include int main(void) { rt_kprintf("build time: %s %s\n", __DATE__, __TIME__); rt_kprintf("Hello RT-Thread!\n"); - + rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); return 0; } - -/*@}*/ diff --git a/bsp/amebaz/applications/smartconfig_app.c b/bsp/amebaz/applications/smartconfig_app.c new file mode 100644 index 0000000000..4302fe7937 --- /dev/null +++ b/bsp/amebaz/applications/smartconfig_app.c @@ -0,0 +1,146 @@ +/* + * File : smartconfig_demo.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-09-13 Bernard the first version + */ +#include +#include + +#ifdef RT_USING_SMARTCONFIG_LIB + +#include +#include "smartconfig.h" + +#define NET_READY_TIME_OUT (rt_tick_from_millisecond(30 * 1000)) + +static int rt_wlan_device_connetct(char *ssid, char *passwd) +{ + int result = RT_EOK; + rt_uint8_t time_cnt = 0; + + result = rt_wlan_connect(ssid, passwd); + if (result != RT_EOK) + { + rt_kprintf("\nconnect ssid %s error:%d!\n", ssid, result); + return result; + }; + + do + { + rt_thread_mdelay(1000); + time_cnt ++; + if (rt_wlan_is_ready()) + { + break; + } + } + while (time_cnt <= (NET_READY_TIME_OUT / 1000)); + + if (time_cnt <= (NET_READY_TIME_OUT / 1000)) + { + rt_kprintf("networking ready!\n"); + } + else + { + rt_kprintf("wait ip got timeout!\n"); + result = -RT_ETIMEOUT; + } + + return result; +} + +static void airkiss_send_notification(uint8_t random) +{ + int sock = -1; + int udpbufsize = 2; + struct sockaddr_in UDPBCAddr, UDPBCServerAddr; + + sock = socket(AF_INET, SOCK_DGRAM, 0); + if (sock < 0) + { + rt_kprintf("notify create socket error!\n"); + goto _exit; + } + + UDPBCAddr.sin_family = AF_INET; + UDPBCAddr.sin_port = htons(10000); + UDPBCAddr.sin_addr.s_addr = htonl(0xffffffff); + rt_memset(&(UDPBCAddr.sin_zero), 0, sizeof(UDPBCAddr.sin_zero)); + + UDPBCServerAddr.sin_family = AF_INET; + UDPBCServerAddr.sin_port = htons(10000); + UDPBCServerAddr.sin_addr.s_addr = htonl(INADDR_ANY); + rt_memset(&(UDPBCServerAddr.sin_zero), 0, sizeof(UDPBCServerAddr.sin_zero)); + + if (setsockopt(sock, SOL_SOCKET, SO_BROADCAST, &udpbufsize, sizeof(int)) != 0) + { + rt_kprintf("notify socket setsockopt error\n"); + goto _exit; + } + + if (bind(sock, (struct sockaddr *)&UDPBCServerAddr, sizeof(UDPBCServerAddr)) != 0) + { + rt_kprintf("notify socket bind error\n"); + goto _exit; + } + + for (int i = 0; i <= 20; i++) + { + int ret = sendto(sock, (char *)&random, 1, 0, (struct sockaddr *)&UDPBCAddr, sizeof(UDPBCAddr)); + rt_thread_delay(10); + } + + rt_kprintf("airkiss notification thread exit!\n"); + +_exit: + if (sock >= 0) + { + closesocket(sock); + } +} + +static int smartconfig_result(rt_smartconfig_type result_type, char *ssid, char *passwd, void *userdata, rt_uint8_t userdata_len) +{ + rt_uint8_t random = *(rt_uint8_t *)userdata; + + rt_kprintf("type:%d\n", result_type); + rt_kprintf("ssid:%s\n", ssid); + rt_kprintf("passwd:%s\n", passwd); + rt_kprintf("user_data:0x%02x\n", random); + if (rt_wlan_device_connetct(ssid, passwd) == RT_EOK) + { + airkiss_send_notification(random); + } + + return 0; +} + +void smartconfig_demo(void) +{ + rt_smartconfig_start(SMARTCONFIG_TYPE_AIRKISS, SMARTCONFIG_ENCRYPT_NONE, RT_NULL, smartconfig_result); +} + +#ifdef RT_USING_FINSH +#include "finsh.h" +MSH_CMD_EXPORT(smartconfig_demo, smartconfig demo); +#endif + +#endif diff --git a/bsp/amebaz/drivers/Kconfig b/bsp/amebaz/drivers/Kconfig new file mode 100644 index 0000000000..19046fc40c --- /dev/null +++ b/bsp/amebaz/drivers/Kconfig @@ -0,0 +1,9 @@ +config BSP_USING_UART0 + bool "Using UART0" + select RT_USING_SERIAL + default y + +config BSP_USING_WIFI + bool "Using WIFI" + select RT_USING_WIFI + default y diff --git a/bsp/amebaz/drivers/SConscript b/bsp/amebaz/drivers/SConscript index aec108b678..dbaeb2a476 100644 --- a/bsp/amebaz/drivers/SConscript +++ b/bsp/amebaz/drivers/SConscript @@ -5,14 +5,9 @@ list = os.listdir(cwd) objs = [] src = Split(''' - board.c - drv_uart.c - ''') - -if GetDepend(['RT_USING_LWIP']): - src += Split(''' - drv_wifi.c - ''') + board.c + drv_uart.c + ''') CPPPATH = [cwd] diff --git a/bsp/amebaz/drivers/board.c b/bsp/amebaz/drivers/board.c index f343c31d5b..ffdc9fc680 100644 --- a/bsp/amebaz/drivers/board.c +++ b/bsp/amebaz/drivers/board.c @@ -12,10 +12,8 @@ * 2009-01-05 Bernard first implementation * 2018-03-15 flyingcys add amebaz */ +#include #include -#include -#include - #include "board.h" #include "drv_uart.h" @@ -87,7 +85,7 @@ void rt_hw_board_init(void) { extern uint32_t SystemCoreClock; SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); - + #ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif diff --git a/bsp/amebaz/drivers/board.h b/bsp/amebaz/drivers/board.h index aa915a67cf..3baf67a4d5 100644 --- a/bsp/amebaz/drivers/board.h +++ b/bsp/amebaz/drivers/board.h @@ -17,7 +17,17 @@ #ifndef __BOARD_H__ #define __BOARD_H__ -#include "rtl8710b.h" +#ifdef _LITTLE_ENDIAN +#undef _LITTLE_ENDIAN +#endif + +#ifdef SECTION +#undef SECTION +#endif + +#include +#include +#include void rt_hw_board_init(void); diff --git a/bsp/amebaz/drivers/drv_uart.c b/bsp/amebaz/drivers/drv_uart.c index da89095d30..1bf659e79f 100644 --- a/bsp/amebaz/drivers/drv_uart.c +++ b/bsp/amebaz/drivers/drv_uart.c @@ -22,11 +22,8 @@ * 2017-05-30 Bernard the first version * 2018-03-15 flyingcys add amebaz */ - -#include -#include -#include - +#include +#include #include "board.h" #include "drv_uart.h" @@ -37,7 +34,9 @@ struct device_uart rt_uint32_t irqno; }; -#ifdef RT_USING_UART0 +extern int LOGUART_SetBaud(u32 BaudRate); + +#ifdef BSP_USING_UART0 static struct rt_serial_device serial0; static struct device_uart uart0; #endif @@ -64,7 +63,6 @@ const struct rt_uart_ops _uart_ops = */ static rt_err_t ameba_uart_configure (struct rt_serial_device *serial, struct serial_configure *cfg) { - rt_uint32_t baud_div; struct device_uart * uart; RT_ASSERT(serial != RT_NULL); @@ -230,16 +228,16 @@ int rt_hw_uart_init(void) struct rt_serial_device *serial; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; -#ifdef RT_USING_UART0 +#ifdef BSP_USING_UART0 { struct device_uart *uart; serial = &serial0; uart = &uart0; - + /* Init UART Hardware */ serial_init(&uart->serial, UART_TX, UART_RX); - + serial->ops = &_uart_ops; serial->config = config; serial->config.baud_rate = 115200; diff --git a/bsp/amebaz/drivers/drv_uart.h b/bsp/amebaz/drivers/drv_uart.h index 8d2f1b6db5..a4d326da58 100644 --- a/bsp/amebaz/drivers/drv_uart.h +++ b/bsp/amebaz/drivers/drv_uart.h @@ -26,9 +26,6 @@ #ifndef __DRV_UART_H__ #define __DRV_UART_H__ -#include "ameba_soc.h" -#include "serial_api.h" - #if defined(CONFIG_PLATFORM_8711B) // 8710B #define UART_TX PA_23 diff --git a/bsp/amebaz/drivers/drv_wifi.c b/bsp/amebaz/drivers/drv_wifi.c deleted file mode 100644 index 7c0366d6aa..0000000000 --- a/bsp/amebaz/drivers/drv_wifi.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * File : drv_wifi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-5-30 Bernard the first version - * 2018-5-30 flyingcys add amebaz wifi driver - */ - -#include -#include -#include - -#include "amebaz_wlan.h" - -//#define ETH_RX_DUMP -//#define ETH_TX_DUMP -//#define MINI_DUMP - -struct sk_buff * rltk_wlan_get_recv_skb(int idx); -struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len); - -#define MAX_ADDR_LEN 6 - -struct ameba_wifi -{ - struct rt_wlan_device parent; - - rt_uint8_t dev_addr[MAX_ADDR_LEN]; - - int idx; - int connected; -}; - -#ifdef RT_USING_WLAN_STA -static struct ameba_wifi wifi_sta; -#endif - -#ifdef RT_USING_WLAN_AP -static struct ameba_wifi wifi_ap; -#endif - -#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) -static void packet_dump(const char *msg, const struct pbuf *p) -{ - const struct pbuf *q; - rt_uint32_t i, j; - rt_uint8_t *ptr; - - rt_kprintf("%s %d byte\n", msg, p->tot_len); - -#ifdef MINI_DUMP - return; -#endif - - i = 0; - for (q = p; q != RT_NULL; q = q->next) - { - ptr = q->payload; - - for (j = 0; j < q->len; j++) - { - if ((i % 8) == 0) - { - rt_kprintf(" "); - } - - if ((i % 16) == 0) - { - rt_kprintf("\r\n"); - } - rt_kprintf("%02x ", *ptr); - - i++; - ptr++; - } - } - - rt_kprintf("\n\n"); -} -#endif /* dump */ - -#define netifapi_netif_set_link_up(n) netifapi_netif_common(n, netif_set_link_up, NULL) -#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL) - -void netif_set_connected(int connected) -{ - wifi_sta.connected = connected; - if (connected) - { - netifapi_netif_set_link_up(wifi_sta.parent.parent.netif); - } - else - { - netifapi_netif_set_link_down(wifi_sta.parent.parent.netif); - } -} - -void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr) -{ - struct ameba_wifi *wifi; - - if(idx_wlan == 0) - wifi = &wifi_sta; - - rtw_memcpy(wifi->dev_addr, dev_addr, 6); - rt_hw_wifi_init(); -} - -void netif_rx(int idx, unsigned int len) -{ - struct ameba_wifi *wifi; - struct pbuf *p, *q; - int sg_len = 0; - struct sk_buff *skb = RT_NULL; - - if(idx == 0) - wifi = &wifi_sta; - -#if CONFIG_WLAN - if(!wifi->connected || !rltk_wlan_running(idx)) - return; -#endif - - skb = rltk_wlan_get_recv_skb(idx); - if(!skb) - { - rt_kprintf("netif_rx rltk_wlan_get_recv_skb NULL.\n"); - return; - } - - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - if (p != RT_NULL) - { - pbuf_take(p, skb->data, len); - skb_pull(skb, len); - -#ifdef ETH_RX_DUMP - packet_dump("RX dump", p); -#endif /* ETH_RX_DUMP */ - - if(wifi->parent.parent.netif->input(p, wifi->parent.parent.netif) != ERR_OK) - { - pbuf_free(p); - } - } - else - { - rt_kprintf("pbuf_alloc NULL for wifi RX.\n"); - } -} - -int netif_is_valid_IP(int idx, unsigned char *ip_dest) -{ - - struct netif * pnetif; - struct ip_addr addr = { 0 }; - u32_t *ip_dest_addr = (u32_t*)ip_dest; - - if(idx == 0) - pnetif = wifi_sta.parent.parent.netif; - - addr.addr = *ip_dest_addr; - - if(pnetif == RT_NULL) - return 0; - - if(pnetif->ip_addr.addr == 0) - return 1; - - if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)) - { - return 1; - } - - if(ip_addr_cmp(&(pnetif->ip_addr), &addr)) - return 1; - - return 0; -} - -void netif_post_sleep_processing(void) -{ - -} - -void netif_pre_sleep_processing(void) -{ - -} - -unsigned char *rltk_wlan_get_ip(int idx) -{ - struct ameba_wifi *wifi; - - if(idx == 0) - wifi = &wifi_sta; - - return (unsigned char *)&(wifi->parent.parent.netif->ip_addr); -} - -struct netif *rltk_wlan_get_netif(int idx) -{ - struct netif *netif; - - if(idx == 0) - netif = wifi_sta.parent.parent.netif; - else if(idx == 1) - netif = wifi_ap.parent.parent.netif; - - return netif; -} - - -rt_err_t rt_ameba_wifi_init(rt_device_t dev) -{ - return RT_EOK; -} - -rt_err_t rt_ameba_wifi_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -rt_err_t rt_ameba_wifi_close(rt_device_t dev) -{ - return RT_EOK; -} - -rt_size_t rt_ameba_wifi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -rt_size_t rt_ameba_wifi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -rt_err_t rt_ameba_wifi_control(rt_device_t dev, int cmd, void *args) -{ - switch(cmd) - { - case NIOCTL_GADDR: - { - struct ameba_wifi *wifi = (struct ameba_wifi *)dev; - if(args) - memcpy(args, wifi->dev_addr, MAX_ADDR_LEN); - else - return -RT_ERROR; - } - break; - - case WIFI_INIT: - { - rt_wlan_mode_t mode = *(rt_wlan_mode_t *)args; - rt_kprintf("mode:%d\n", mode); - } - break; - - case WIFI_SCAN: - { - struct rt_wlan_scan_result *dst = RT_NULL; - dst = (struct rt_wlan_scan_result *)rt_malloc(sizeof(struct rt_wlan_scan_result)); - if(dst == RT_NULL) - { - rt_kprintf("rt_malloc for scan result failed!\n"); - return -RT_ENOMEM; - } - - memset(dst, 0, sizeof(struct rt_wlan_scan_result)); - if(amebaz_wifi_scan(dst) != RT_EOK) - { - rt_kprintf("amebaz_wifi_scan failed...\n"); - return -RT_ERROR; - } - - *(struct rt_wlan_scan_result **)args = dst; - } - break; - - case WIFI_JOIN: - - break; - - case WIFI_EASYJOIN: - { - struct rt_wlan_device *wlan = (struct rt_wlan_device *)dev; - if(amebaz_wifi_connect(wlan->info->ssid, (char *)args) != RT_EOK) - { - rt_kprintf("amebaz_wifi_connect failed...\n"); - return -RT_ERROR; - } - } - break; - - case WIFI_SOFTAP: - { - struct rt_wlan_device *wlan = (struct rt_wlan_device *)dev; - if(amebaz_wifi_ap_start(wlan->info->ssid, (char *)args, wlan->info->channel) != RT_EOK) - { - rt_kprintf("amebaz_wifi_ap_start failed...\n"); - return -RT_ERROR; - } - } - break; - - case WIFI_DISCONNECT: - if(amebaz_wifi_disconnect() != RT_EOK) - { - rt_kprintf("amebaz_wifi_disconnect failed...\n"); - return -RT_ERROR; - } - break; - - case WIFI_GET_RSSI: - { - int *rssi = (int *)args; - - *rssi = amebaz_wifi_get_rssi(); - } - break; - - case WIFI_ENTER_POWERSAVE: - - break; - - case WIFI_CFG_MONITOR: - - break; - - case WIFI_SET_CHANNEL: - { - int channel = *(int *)args; - - amebaz_wifi_set_channel(channel); - } - break; - - case WIFI_GET_CHANNEL: - { - int *channel = (int *)args; - - *channel = amebaz_wifi_get_channel(); - } - break; - - case WIFI_SET_MONITOR_CALLBACK: - - break; - } - - return RT_EOK; -} - -rt_err_t rt_ameba_wifi_tx(rt_device_t dev, struct pbuf* p) -{ - rt_err_t result = RT_EOK; - struct ameba_wifi *wifi = (struct ameba_wifi *)dev; - int idx; - rt_base_t level; - struct sk_buff *skb = RT_NULL; - - idx = wifi->idx; - - level = rt_hw_interrupt_disable(); - if(wifi->connected && rltk_wlan_check_isup(idx)) - rltk_wlan_tx_inc(idx); - else - { - rt_hw_interrupt_enable(level); -// rt_kprintf("is not: connected && rltk_wlan_check_isup(idx)\n"); - - result = -RT_ERROR; - goto _exit; - } - - rt_hw_interrupt_enable(level); - -#ifdef ETH_TX_DUMP - packet_dump("TX dump", p); -#endif /* ETH_TX_DUMP */ - - skb = rltk_wlan_alloc_skb(p->tot_len); - if(skb != RT_NULL) - { - /* copy pbuf to a whole ETH frame */ - pbuf_copy_partial(p, skb->tail, p->tot_len, 0); - skb_put(skb, p->tot_len); - - rltk_wlan_send_skb(idx, skb); - } - else - { - rt_kprintf("rltk_wlan_alloc_skb NULL for WIFI TX.\n"); - result = -RT_ENOMEM; - } - -_exit: - level = rt_hw_interrupt_disable(); - rltk_wlan_tx_dec(idx); - rt_hw_interrupt_enable(level); - - return result; -} - -int rt_hw_wifi_init(void) -{ - rt_kprintf("%s %d\n", __FUNCTION__, __LINE__); - -#ifdef RT_USING_WLAN_STA - wifi_sta.parent.parent.parent.init = rt_ameba_wifi_init; - wifi_sta.parent.parent.parent.open = rt_ameba_wifi_open; - wifi_sta.parent.parent.parent.close = rt_ameba_wifi_close; - wifi_sta.parent.parent.parent.read = rt_ameba_wifi_read; - wifi_sta.parent.parent.parent.write = rt_ameba_wifi_write; - wifi_sta.parent.parent.parent.control = rt_ameba_wifi_control; - wifi_sta.parent.parent.parent.user_data = RT_NULL; - // - wifi_sta.idx = 0; - // - wifi_sta.parent.parent.eth_rx = RT_NULL; - wifi_sta.parent.parent.eth_tx = rt_ameba_wifi_tx; - - /* register wifi device */ - eth_device_init(&wifi_sta.parent.parent, WIFI_DEVICE_STA_NAME); -#endif - -#ifdef RT_USING_WLAN_AP - -#endif - - return RT_EOK; -} - diff --git a/bsp/amebaz/drivers/wlan/SConscript b/bsp/amebaz/drivers/wlan/SConscript index 9b4e410f5d..414abb50e6 100644 --- a/bsp/amebaz/drivers/wlan/SConscript +++ b/bsp/amebaz/drivers/wlan/SConscript @@ -6,10 +6,11 @@ CPPPATH = [cwd, str(Dir('#'))] src = [] if GetDepend(['RT_USING_LWIP']): - src += Split(''' - amebaz_wlan.c - ''') + src += Split(''' + drv_wifi.c + drv_wlan.c + ''') -group = DefineGroup('amebaz_wlan', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/amebaz/drivers/wlan/amebaz_wlan.c b/bsp/amebaz/drivers/wlan/amebaz_wlan.c deleted file mode 100644 index 855be37fc7..0000000000 --- a/bsp/amebaz/drivers/wlan/amebaz_wlan.c +++ /dev/null @@ -1,642 +0,0 @@ -/* - * File : amebaz_wlan.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-5-30 Bernard the first version - * 2018-6-12 flyingcys add amebaz wlan interface - */ -#include -#include - -#include "wifi_structures.h" -#include "wifi_constants.h" -#include -#include - - -#define PASSWD_LEN 65 -#define SCAN_WAIT_TIME 10000 - -typedef enum -{ - WIFI_NONE, - WIFI_STATION, - WIFI_AP, -} rt_wlan_mode_t; - -struct rt_wlan_info -{ - rt_wlan_mode_t mode; /* wifi mode */ - rtw_security_t security; - - char *ssid; - uint8_t bssid[6]; - - /* maximal data rate */ - uint32_t datarate; - /* radio channel */ - uint16_t channel; - /* signal strength */ - int16_t rssi; -}; - -typedef struct rt_wlan_scan_result -{ - char ap_num; - struct rt_wlan_info *ap_table; -} rt_wlan_scan_result_t; - - -static rtw_network_info_t wifi_info = {0}; -static rtw_ap_info_t ap_info = {0}; -static unsigned char wifi_password[65] = {0}; -static unsigned char ap_password[PASSWD_LEN] = {0}; -static rt_sem_t scan_done_sem = RT_NULL; -static char *scan_buf = RT_NULL; -static int ApNum = 0; - -extern struct netif *rltk_wlan_get_netif(int idx); - -static void LwIP_ReleaseIP(uint8_t idx) -{ - struct ip_addr ipaddr; - struct ip_addr netmask; - struct ip_addr gw; - struct netif *pnetif = rltk_wlan_get_netif(idx); - - IP4_ADDR(&ipaddr, 0, 0, 0, 0); - IP4_ADDR(&netmask, 255, 255, 255, 0); - IP4_ADDR(&gw, 0, 0, 0, 0); - - netif_set_addr(pnetif, &ipaddr , &netmask, &gw); -} - -static rtw_result_t amebaz_scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) -{ - if (malloced_scan_result->scan_complete != RTW_TRUE) { - rtw_scan_result_t* record = &malloced_scan_result->ap_details; - record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ - - ++ ApNum; - - if(malloced_scan_result->user_data) - memcpy((void *)((char *)malloced_scan_result->user_data+(ApNum-1)*sizeof(rtw_scan_result_t)), (char *)record, sizeof(rtw_scan_result_t)); - } - else - { - rt_kprintf("ap num:%d\n", ApNum); - - if(scan_done_sem) - { - rt_sem_release(scan_done_sem); - } - } - - return RTW_SUCCESS; -} - - -static int amebaz_wifi_do_scan(void) -{ - int ret = RTW_SUCCESS; - - rt_kprintf("wifi scan start...\n"); - - scan_buf = malloc(65*sizeof(rtw_scan_result_t)); - if(scan_buf == NULL){ - ret = RTW_BUFFER_UNAVAILABLE_TEMPORARY; - return -RT_ENOMEM; - } - - memset(scan_buf, 0, 65 * sizeof(rtw_scan_result_t)); - - if((ret = wifi_scan_networks(amebaz_scan_result_handler, scan_buf)) != RTW_SUCCESS){ - rt_kprintf("ERROR: wifi scan failed\n\r"); - - return -RT_ERROR; - } - - return RT_EOK; -} - -int amebaz_wifi_scan(struct rt_wlan_scan_result *dst) -{ - rt_uint32_t i; - rt_uint32_t j = 0; - - scan_done_sem = rt_sem_create("scandone", 0, RT_IPC_FLAG_FIFO); - if(scan_done_sem == RT_NULL) - return -RT_ENOMEM; - - if(amebaz_wifi_do_scan() != RT_EOK) - { - rt_kprintf("amebaz_wifi_do_scan failed...\n"); - return -RT_ERROR; - } - - if(rt_sem_take(scan_done_sem, rt_tick_from_millisecond(SCAN_WAIT_TIME)) != RT_EOK) - { - rt_kprintf("scan wait timeout...\n"); - return -RT_ETIMEOUT; - } - - if(scan_done_sem) - { - rt_sem_delete(scan_done_sem); - scan_done_sem = RT_NULL; - } - - rtw_scan_result_t *ptr = (rtw_scan_result_t *)scan_buf; - dst->ap_num = ApNum; - ApNum = 0; - - dst->ap_table = (struct rt_wlan_info *)rt_malloc(sizeof(struct rt_wlan_info) * dst->ap_num); - if(dst->ap_table == RT_NULL) - { - rt_kprintf("rt_malloc for ap table failed...\n"); - goto __exit; - } - - for(i = 0; i < dst->ap_num; i ++) - { - dst->ap_table[i].mode = 1; - dst->ap_table[i].security = ptr->security; - dst->ap_table[i].ssid = (char *)rt_malloc(33); - if(dst->ap_table[i].ssid == RT_NULL) - { - rt_kprintf("rt_malloc for ssid Failed! times:%d,total:%d\n",i,ApNum); - j = i; - goto __exit; - } - - memset(dst->ap_table[i].ssid, 0, 33); - memcpy(dst->ap_table[i].ssid, ptr->SSID.val, ptr->SSID.len); - memcpy(dst->ap_table[i].bssid, ptr->BSSID.octet, 6); - dst->ap_table[i].datarate = 0; - dst->ap_table[i].channel = ptr->channel; - dst->ap_table[i].rssi = ptr->signal_strength; - - ptr ++; - } - - if(scan_buf != RT_NULL) - { - rt_free(scan_buf); - scan_buf = RT_NULL; - } - - return RT_EOK; - -__exit: - - if(scan_buf != RT_NULL) - { - rt_free(scan_buf); - scan_buf = RT_NULL; - } - - if(dst->ap_table) - { - for(i = 0; i < j; i ++) - rt_free(dst->ap_table[i].ssid); - rt_free(dst->ap_table); - dst->ap_table = RT_NULL; - dst->ap_num = 0; - } - - return -RT_ERROR; -} - -void amebaz_wifi_info_init(void) -{ - memset(wifi_info.ssid.val, 0, sizeof(wifi_info.ssid.val)); - memset(wifi_info.bssid.octet, 0, 6); - memset(wifi_password, 0, sizeof(wifi_password)); - wifi_info.ssid.len = 0; - wifi_info.password = NULL; - wifi_info.password_len = 0; - wifi_info.key_id = -1; - - memset(ap_info.ssid.val, 0, sizeof(ap_info.ssid.val)); - ap_info.ssid.len = 0; - ap_info.security_type = RTW_SECURITY_UNKNOWN; - ap_info.password = NULL; - ap_info.password_len = 0; - ap_info.channel = 1; -} - -static int amebaz_wifi_set_sta_info(char *ssid, char *passwd) -{ - if(ssid == RT_NULL || strlen(ssid) > 32) - { - rt_kprintf("Invalid argument...\n"); - return -RT_EINVAL; - } - - strcpy(wifi_info.ssid.val, ssid); - wifi_info.ssid.len = strlen(ssid); - - if(passwd != NULL) - { - if(strlen(passwd) > 64) - { - rt_kprintf("Invalid argument...\n"); - return -RT_EINVAL; - } - strcpy(wifi_password, passwd); - wifi_info.password = wifi_password; - wifi_info.password_len = strlen(passwd); - } - else - wifi_info.password = RT_NULL; - - return RT_EOK; -} - -static int amebaz_wifi_set_ap_info(char *ssid, char *passwd, int channel) -{ - if(ssid == RT_NULL || strlen(ssid) > 32) - { - rt_kprintf("Invalid argument...\n"); - return -RT_EINVAL; - } - - strcpy(ap_info.ssid.val, ssid); - ap_info.ssid.len = strlen(ssid); - - if(passwd != NULL) - { - if(strlen(passwd) > 64) - { - rt_kprintf("Invalid argument...\n"); - return -RT_EINVAL; - } - strcpy(ap_password, passwd); - ap_info.password = ap_password; - ap_info.password_len = strlen(passwd); - } - else - ap_info.password = RT_NULL; - - ap_info.channel = channel; - return RT_EOK; -} - -static int amebaz_wifi_do_connect(void) -{ - int mode, ret; - char empty_bssid[6] = {0}; - char assoc_by_bssid = 0; - - rt_kprintf("amebaz wifi do connect start...\n"); - if(memcmp (wifi_info.bssid.octet, empty_bssid, 6)) - { - assoc_by_bssid = 1; - } - else if(wifi_info.ssid.val[0] == 0) - { - ret = RTW_BADARG; - return -RT_ERROR; - } - - if(wifi_info.password != RT_NULL) - { - if((wifi_info.key_id >= 0) && (wifi_info.key_id <= 3)) - { - wifi_info.security_type = RTW_SECURITY_WEP_PSK; - } - else - { - wifi_info.security_type = RTW_SECURITY_WPA2_AES_PSK; - } - } - else - { - wifi_info.security_type = RTW_SECURITY_OPEN; - } - - //Check if in AP mode - wext_get_mode(WLAN0_NAME, &mode); - if(mode == IW_MODE_MASTER) - { - #if 0 -#if CONFIG_LWIP_LAYER - dhcps_deinit(); -#endif - wifi_off(); - vTaskDelay(20); - if (wifi_on(RTW_MODE_STA) < 0){ - printf("\n\rERROR: Wifi on failed!"); - ret = RTW_ERROR; - goto EXIT; - } - #endif - } - - if(assoc_by_bssid) - { - rt_kprintf("Joining BSS by BSSID \"MAC_FMT\" ...\n", MAC_ARG(wifi_info.bssid.octet)); - ret = wifi_connect_bssid(wifi_info.bssid.octet, (char*)wifi_info.ssid.val, wifi_info.security_type, (char*)wifi_info.password, - ETH_ALEN, wifi_info.ssid.len, wifi_info.password_len, wifi_info.key_id, NULL); - } - else - { - rt_kprintf("\n\rJoining BSS by SSID %s...\n\r", (char*)wifi_info.ssid.val); - ret = wifi_connect((char*)wifi_info.ssid.val, wifi_info.security_type, - (char*)wifi_info.password, wifi_info.ssid.len, - wifi_info.password_len, wifi_info.key_id, NULL); - } - - if(ret!= RTW_SUCCESS) - { - if(ret == RTW_INVALID_KEY) - rt_kprintf("ERROR:Invalid Key\n"); - - rt_kprintf("ERROR: Can't connect to AP\n"); - return -RT_ERROR; - } - - rt_kprintf("now start dhcp...\n"); - netif_set_connected(1); - dhcp_start(netif_default); - rt_kprintf("dhcp success...\n"); - - return RT_EOK; -} - -int amebaz_wifi_connect(char *ssid, char *passwd) -{ - int ret; - - ret = amebaz_wifi_set_sta_info(ssid, passwd); - if(ret != RT_EOK) - { - amebaz_wifi_info_init(); - return ret; - } - - if(amebaz_wifi_do_connect() != RT_EOK) - { - amebaz_wifi_info_init(); - rt_kprintf("amebaz_wifi_do_connect failed...\n"); - return -RT_ERROR; - } - - amebaz_wifi_info_init(); - - return RT_EOK; -} - -static int amebaz_wifi_do_disconnect(void) -{ - int timeout = 20; - char essid[33]; - int ret = RTW_SUCCESS; - - if(wext_get_ssid(WLAN0_NAME, (unsigned char *) essid) < 0) - { - rt_kprintf("\nWIFI disconnected!\n"); - return -RT_ERROR; - } - - if((ret = wifi_disconnect()) < 0) - { - return -RT_ERROR; - } - - while(1) - { - if(wext_get_ssid(WLAN0_NAME, (unsigned char *) essid) < 0) - { - rt_kprintf("\nWIFI disconnected!\n"); - break; - } - - if(timeout == 0) - { - rt_kprintf("ERROR: Deassoc timeout!\n\r"); - ret = RTW_TIMEOUT; - break; - } - - vTaskDelay(10); - timeout --; - } - - LwIP_ReleaseIP(WLAN0_IDX); - - if(ret != RTW_SUCCESS) - return -RT_ERROR; - - rt_kprintf("amebaz wifi do disconnect success...\n"); - return RT_EOK; -} - -int amebaz_wifi_disconnect(void) -{ - int ret = RT_EOK; - - ret = amebaz_wifi_do_disconnect(); - if(ret != RT_EOK) - rt_kprintf("amebaz_wifi_do_disconnect failed...\n"); - - amebaz_wifi_info_init(); - - return ret; -} - -static int amebaz_wifi_do_ap_start(void) -{ - struct ip_addr ipaddr; - struct ip_addr netmask; - struct ip_addr gw; - struct netif *pnetif = rltk_wlan_get_netif(1); - - int timeout = 20; - int ret = RTW_SUCCESS; - - if(ap_info.ssid.val[0] == 0){ - rt_kprintf("ERROR: SSID can't be empty\n\r"); - return -RT_ERROR; - } - - if(ap_info.password == NULL) - { - ap_info.security_type = RTW_SECURITY_OPEN; - } - else - { - if(ap_info.password_len <= RTW_MAX_PSK_LEN && ap_info.password_len >= RTW_MIN_PSK_LEN) - { - ap_info.security_type = RTW_SECURITY_WPA2_AES_PSK; - } - else - { - rt_kprintf("ERROR: password length is between 8 to 64 \n"); - return -RT_ERROR; - } - } - -//#if CONFIG_LWIP_LAYER -// dhcps_deinit(); -// IP4_ADDR(&ipaddr, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); -// IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1 , NETMASK_ADDR2, NETMASK_ADDR3); -// IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); -// netif_set_addr(pnetif, &ipaddr, &netmask,&gw); -//#ifdef CONFIG_DONT_CARE_TP -// pnetif->flags |= NETIF_FLAG_IPSWITCH; -//#endif -//#endif - - wifi_off(); - vTaskDelay(20); - if (wifi_on(RTW_MODE_AP) < 0) - { - rt_kprintf("ERROR: Wifi on failed!\n"); - return -RT_ERROR; - } - rt_kprintf("Now start AP mode...\n"); - - if((ret = wifi_start_ap((char*)ap_info.ssid.val, ap_info.security_type, (char*)ap_info.password, ap_info.ssid.len, ap_info.password_len, ap_info.channel) ) < 0) - { - rt_kprintf("ERROR: Operation failed!"); - return -RT_ERROR; - } - - while(1) - { - char essid[33]; - - if(wext_get_ssid(WLAN0_NAME, (unsigned char *) essid) > 0) - { - if(strcmp((const char *) essid, (const char *)ap_info.ssid.val) == 0) - { - rt_kprintf("AP %s started...\n", ap_info.ssid.val); - ret = RTW_SUCCESS; - break; - } - } - - if(timeout == 0) - { - rt_kprintf("ERROR: Start AP timeout!"); - ret = RTW_TIMEOUT; - break; - } - - vTaskDelay(10); - timeout --; - } - - if(ret != RTW_SUCCESS) - return -RT_ERROR; - -//#if CONFIG_LWIP_LAYER - //LwIP_UseStaticIP(pnetif); -// dhcps_init(pnetif); -//#endif - - return RT_EOK; -} - -static int amebaz_wifi_do_ap_stop(void) -{ - return RT_EOK; -} - -int amebaz_wifi_ap_start(char *ssid, char *passwd, int channel) -{ - int ret; - - ret = amebaz_wifi_set_ap_info(ssid, passwd, channel); - if(ret != RT_EOK) - { - amebaz_wifi_info_init(); - return ret; - } - - if(amebaz_wifi_do_ap_start() != RT_EOK) - { - amebaz_wifi_info_init(); - rt_kprintf("amebaz_wifi_ap_start failed...\n"); - return -RT_ERROR; - } - - amebaz_wifi_info_init(); - return RT_EOK; -} - -int amebaz_wifi_ap_stop(void) -{ - int ret; - - if(amebaz_wifi_do_ap_stop() != RT_EOK) - { - amebaz_wifi_info_init(); - rt_kprintf("amebaz_wifi_ap_stop failed...\n"); - return -RT_ERROR; - } - - amebaz_wifi_info_init(); - return RT_EOK; -} - -int amebaz_wifi_get_rssi(void) -{ - int rssi = 0; - - wifi_get_rssi(&rssi); - - return rssi; -} - -void amebaz_wifi_set_channel(int channel) -{ - wifi_set_channel(channel); -} - -int amebaz_wifi_get_channel(void) -{ - int channel; - - wifi_get_channel(&channel); - - return channel; -} - -int amebaz_wifi_init(rt_wlan_mode_t mode) -{ - int ret; - rtw_mode_t rtw_mode; - - if(mode == WIFI_STATION) - rtw_mode = RTW_MODE_STA; - else if(mode == WIFI_AP) - rtw_mode = RTW_MODE_AP; - - if(wifi_on(mode) < 0) - return -RT_ERROR; - - if(wifi_set_autoreconnect(1) < 0) - return -RT_ERROR; - - return RT_EOK; -} - diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.c b/bsp/amebaz/drivers/wlan/drv_wifi.c new file mode 100644 index 0000000000..7e62ed1acf --- /dev/null +++ b/bsp/amebaz/drivers/wlan/drv_wifi.c @@ -0,0 +1,666 @@ +/* + * File : drv_wifi.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + * 2018-5-30 flyingcys add amebaz wifi driver + */ +#include +#include "board.h" +#include +#include "drv_wlan.h" +#include "drv_wifi.h" + +#define DBG_ENABLE +#define DBG_LEVEL DBG_INFO +#define DBG_SECTION_NAME "WIFI" +#define DBG_COLOR +#include + +#define MAX_ADDR_LEN (6) +#define RT_WLAN_SSID_MAX_LEN (32) + +#define WIFI_INIT_FLAG (0x1 << 0) +#define WIFI_MAC_FLAG (0x1 << 1) +#define WIFI_TYPE_STA (0) +#define WIFI_TYPE_AP (1) + +struct ameba_wifi +{ + struct rt_wlan_device *wlan; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + rt_uint8_t flag; + int connected; + int type; +}; + +extern unsigned char rltk_wlan_running(unsigned char idx); +extern struct sk_buff * rltk_wlan_get_recv_skb(int idx); +extern unsigned char rltk_wlan_check_isup(int idx); +extern void rltk_wlan_tx_inc(int idx); +extern struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len); +extern void rltk_wlan_send_skb(int idx, struct sk_buff *skb); +extern void rltk_wlan_tx_dec(int idx); +extern void rtw_event_register(int event, void (*fun)(char *buf, int len, int flags, void *user_data) , void *user_data); + +static const struct rt_wlan_dev_ops ops; + +static struct ameba_wifi wifi_sta; +static struct ameba_wifi wifi_ap; + +rt_inline struct ameba_wifi *rthw_wifi_get_dev(int idx) +{ + int mode = rthw_wifi_mode_get(); + + if (mode == 1) return &wifi_sta; + if (mode == 2) return &wifi_ap; + if (idx == 0) return &wifi_sta; + if (idx == 1) return &wifi_ap; + return RT_NULL; +} + +rt_inline int rthw_wifi_get_idx(struct ameba_wifi *wifi) +{ + int mode = rthw_wifi_mode_get(); + + if (mode == 1) return 0; + if (mode == 2) return 0; + return wifi->type; +} + +int rthw_wifi_register(struct ameba_wifi *wifi) +{ + struct rt_wlan_device *wlan = RT_NULL; + + if ((wifi->flag & WIFI_INIT_FLAG) == 0) + { + wlan = rt_malloc(sizeof(struct rt_wlan_device)); + RT_ASSERT(wlan != RT_NULL); + if (wifi->type == WIFI_TYPE_STA) + { + rt_wlan_dev_register(wlan, RT_WLAN_DEVICE_STA_NAME, &ops, 0, wifi); + } + if (wifi->type == WIFI_TYPE_AP) + { + rt_wlan_dev_register(wlan, RT_WLAN_DEVICE_AP_NAME, &ops, 0, wifi); + } + wifi->flag |= WIFI_INIT_FLAG; + wifi->wlan = wlan; + LOG_D("F:%s L:%d wifi:0x%08x wlan:0x%08x\n", __FUNCTION__, __LINE__, wifi, wlan); + } + return RT_EOK; +} + +void netif_post_sleep_processing(void) +{ +} + +void netif_pre_sleep_processing(void) +{ +} + +unsigned char *rltk_wlan_get_ip(int idx) +{ + struct ameba_wifi *wifi; + + wifi = rthw_wifi_get_dev(idx); + if (wifi == RT_NULL) + return RT_NULL; + + LOG_D("F:%s L:%d is run", __FUNCTION__, __LINE__); + + /* 这里留空了，会不会炸未知 */ + return RT_NULL; +} + +int netif_is_valid_IP(int idx, unsigned char *ip_dest) +{ + LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, + ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]); + return 1; +} + +void rltk_wlan_set_netif_info(int idx, void *dev, rt_uint8_t *dev_addr) +{ + struct ameba_wifi *wifi = RT_NULL; + + wifi = rthw_wifi_get_dev(idx); + if (wifi == RT_NULL) + return; + LOG_D("F:%s L:%d wifi:0x%08x type:0x%x", __FUNCTION__, __LINE__, wifi, wifi->flag); + rt_memcpy(wifi->dev_addr, dev_addr, 6); + wifi->flag |= WIFI_MAC_FLAG; + rthw_wifi_register(wifi); + LOG_D("wifi type:%d", wifi->type); + LOG_D("idx:%d MAC %02x:%02x:%02x:%02x:%02x:%02x", idx, dev_addr[0], dev_addr[1], dev_addr[2], dev_addr[3], dev_addr[4], dev_addr[5]); +} + +static void rtw_connect_callbackfn(char *buf, int len, int flags, void *user_data) +{ + struct ameba_wifi *wifi = user_data; + + LOG_D("L:%d wifi connect callback flags:%d user_data:%08x", __LINE__, flags, user_data); + if( wifi_is_connected_to_ap() == 0) + { + wifi->connected = 1; + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_CONNECT, RT_NULL); + } +} + +static void rtw_connect_fail_callbackfn(char *buf, int len, int flags, void *user_data) +{ + struct ameba_wifi *wifi = user_data; + + LOG_D("L:%d wifi connect callback flags:%d", __LINE__, flags); + wifi->connected = 0; + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_CONNECT_FAIL, RT_NULL); +} + +static void rtw_disconnect_callbackfn(char *buf, int len, int flags, void *user_data) +{ + struct ameba_wifi *wifi = user_data; + + LOG_D("L:%d wifi disconnect callback flags:%d", __LINE__, flags); + wifi->connected = 0; + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_DISCONNECT, RT_NULL); +} + +static void rtw_sta_assoc_callbackfn(char *buf, int len, int flags, void *user_data) +{ + LOG_D("L:%d wifi sta assoc callback flags:%d", __LINE__, flags); +} + +static void rtw_sta_disassoc_callbackfn(char *buf, int len, int flags, void *user_data) +{ + LOG_D("L:%d wifi sta assoc callback flags:%d buf:%08x %08x", __LINE__, flags, *((rt_uint32_t*)buf), *((rt_uint32_t*)buf + 4)); +} + +void netif_rx(int idx, unsigned int len) +{ + struct ameba_wifi *wifi = RT_NULL; + struct sk_buff *skb = RT_NULL; + + wifi = rthw_wifi_get_dev(idx); + if (wifi == RT_NULL) + return; + + LOG_D("F:%s L:%d idx:%d len:%d", __FUNCTION__, __LINE__, idx, len); + if((!wifi->connected) || (!rltk_wlan_running(idx))) + return; + + skb = (struct sk_buff *)rltk_wlan_get_recv_skb(idx); + if(!skb) + { + LOG_D("netif_rx rltk_wlan_get_recv_skb NULL."); + return; + } + rt_wlan_dev_report_data(wifi->wlan, skb->data, len); +} + +static rt_wlan_security_t security_map_from_ameba(rthw_security_t security) +{ + rt_wlan_security_t result = SECURITY_OPEN; + + switch (security) + { + case RTHW_SECURITY_OPEN: result = SECURITY_OPEN; break; + case RTHW_SECURITY_WEP_PSK: result = SECURITY_WEP_PSK; break; + case RTHW_SECURITY_WEP_SHARED: result = SECURITY_WEP_SHARED; break; + case RTHW_SECURITY_WPA_TKIP_PSK: result = SECURITY_WPA_TKIP_PSK; break; + case RTHW_SECURITY_WPA_AES_PSK: result = SECURITY_WPA_AES_PSK; break; + case RTHW_SECURITY_WPA2_AES_PSK: result = SECURITY_WPA2_AES_PSK; break; + case RTHW_SECURITY_WPA2_TKIP_PSK: result = SECURITY_WPA2_TKIP_PSK; break; + case RTHW_SECURITY_WPA2_MIXED_PSK: result = SECURITY_WPA2_MIXED_PSK; break; + case RTHW_SECURITY_WPA_WPA2_MIXED: result = SECURITY_WPA2_AES_PSK; break; + case RTHW_SECURITY_WPS_OPEN: result = SECURITY_WPS_OPEN; break; + case RTHW_SECURITY_WPS_SECURE: result = SECURITY_WPS_SECURE; break; + default: result = -1; break; + } + + return result; +} + +static rthw_security_t security_map_from_rtthread(rt_wlan_security_t security) +{ + rt_wlan_security_t result = RTHW_SECURITY_OPEN; + + switch (security) + { + case SECURITY_OPEN: result = RTHW_SECURITY_OPEN; break; + case SECURITY_WEP_PSK: result = RTHW_SECURITY_WEP_PSK; break; + case SECURITY_WEP_SHARED: result = RTHW_SECURITY_WEP_SHARED; break; + case SECURITY_WPA_TKIP_PSK: result = RTHW_SECURITY_WPA_TKIP_PSK; break; + case SECURITY_WPA_AES_PSK: result = RTHW_SECURITY_WPA_AES_PSK; break; + case SECURITY_WPA2_AES_PSK: result = RTHW_SECURITY_WPA2_AES_PSK; break; + case SECURITY_WPA2_TKIP_PSK: result = RTHW_SECURITY_WPA2_TKIP_PSK; break; + case SECURITY_WPA2_MIXED_PSK: result = RTHW_SECURITY_WPA2_MIXED_PSK; break; + case SECURITY_WPS_OPEN: result = RTHW_SECURITY_WPS_OPEN; break; + case SECURITY_WPS_SECURE: result = RTHW_SECURITY_WPS_SECURE; break; + default: result = -1; break; + } + + return result; +} + +static void rt_ameba_wifi_scan_callback(struct rthw_wlan_info *info, void *user_data) +{ + struct rt_wlan_info wlan_info = { 0 }; + struct rt_wlan_buff buff; + struct ameba_wifi *wifi = user_data; + + if (info == RT_NULL) + { + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_SCAN_DONE, RT_NULL); + return; + } + memcpy(&wlan_info.bssid[0], info->bssid, 6); + strncpy(&wlan_info.ssid.val[0], info->ssid, RT_WLAN_SSID_MAX_LEN); + wlan_info.ssid.len = strlen(&wlan_info.ssid.val[0]); + wlan_info.band = info->band == RTHW_802_11_BAND_2_4GHZ ? RTHW_802_11_BAND_2_4GHZ : RTHW_802_11_BAND_5GHZ; + wlan_info.channel = info->channel; + wlan_info.datarate = info->datarate * 1000; + wlan_info.security = security_map_from_ameba(info->security); + wlan_info.rssi = info->rssi; + + buff.data = &wlan_info; + buff.len = sizeof(wlan_info); + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_SCAN_REPORT, &buff); +} + +static void rthw_wlan_monitor_callback(rt_uint8_t *data, int len, void *user_data) +{ + rt_wlan_dev_promisc_handler(wifi_sta.wlan, data, len); +} + +static rt_err_t rthw_wlan_init (struct rt_wlan_device *wlan) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static rt_err_t rthw_wlan_mode (struct rt_wlan_device *wlan, rt_wlan_mode_t mode) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + + LOG_D("F:%s L:%d mode:%d", __FUNCTION__, __LINE__, mode); + + if (mode == RT_WLAN_STATION) + { + if (wifi->type != WIFI_TYPE_STA) + { + LOG_D("this wlan not support sta mode"); + return -RT_ERROR; + } + } + else if (mode == RT_WLAN_AP) + { + if (wifi->type != WIFI_TYPE_AP) + { + LOG_D("this wlan not support ap mode"); + return -RT_ERROR; + } + } + + return RT_EOK; +} + +static rt_err_t rthw_wlan_scan (struct rt_wlan_device *wlan, struct rt_scan_info *scan_info) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + LOG_D("F:%s L:%d wifi:0x%08x type:0x%x", __FUNCTION__, __LINE__, wifi, wifi->type); + + if (wifi->type != WIFI_TYPE_STA) + { + LOG_D("this wlan not support scan mode"); + return -RT_ERROR; + } + if (rthw_wifi_mode_get() == RTHW_MODE_NONE) + { + if(rthw_wifi_start(RTHW_MODE_STA_AP) != RT_EOK) + { + LOG_D("L:%d wifistart failed...", __LINE__); + return -1; + } + } + rthw_wifi_scan(rt_ameba_wifi_scan_callback, wifi); + return RT_EOK; +} + +static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, struct rt_sta_info *sta_info) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + int result = 0, i; + char *ssid = RT_NULL, *key = RT_NULL; + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + if (wifi->type != WIFI_TYPE_STA) + { + LOG_E("this wlan not support sta mode"); + return -RT_ERROR; + } + if ((rthw_wifi_mode_get() != RTHW_MODE_STA) && (rthw_wifi_mode_get() != RTHW_MODE_STA_AP)) + { + rthw_wifi_stop(); + rt_thread_delay(RT_TICK_PER_SECOND / 10); + if (rthw_wifi_start(RTHW_MODE_STA_AP) != RT_EOK) + { + LOG_E("wifi on failed, join fail"); + return -RT_ERROR; + } + } + for (i = 0; i < RT_WLAN_BSSID_MAX_LENGTH; i++) + { + if (sta_info->bssid[i] != 0xff || sta_info->bssid[i] != 0x00) + break; + } + if (i < RT_WLAN_BSSID_MAX_LENGTH) + { + if (sta_info->ssid.len > 0) + ssid = &sta_info->ssid.val[0]; + if (sta_info->key.len > 0) + key = &sta_info->key.val[0]; + LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", + sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5], + ssid, + sta_info->ssid.len, + key, + sta_info->key.len + ); + result = rthw_wifi_connect_bssid(sta_info->bssid, ssid, sta_info->ssid.len, key, sta_info->key.len, security_map_from_rtthread(sta_info->security)); + } + else + { + result = rthw_wifi_connect(sta_info->ssid.val, sta_info->ssid.len, sta_info->key.val, sta_info->key.len, security_map_from_rtthread(sta_info->security)); + } + if (result != 0) + { + LOG_E("amebaz_wifi_connect failed..."); + return -RT_ERROR; + } + // netif_set_connected((struct ameba_wifi *)wlan, 1); + LOG_D("amebaz_wifi_connect do"); + return RT_EOK; +} + +static rt_err_t rthw_wlan_softap (struct rt_wlan_device *wlan, struct rt_ap_info *ap_info) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + if (wifi->type != WIFI_TYPE_AP) + { + LOG_E("this wlan not support ap mode"); + return -RT_ERROR; + } + if (rthw_wifi_ap_start(&ap_info->ssid.val[0], &ap_info->key.val[0], ap_info->channel) != 0) + { + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_AP_STOP, RT_NULL); + wifi->connected = 0; + return -RT_ERROR; + } + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_AP_START, RT_NULL); + wifi->connected = 1; + return RT_EOK; +} + +static rt_err_t rthw_wlan_disconnect (struct rt_wlan_device *wlan) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + if (wifi->type != WIFI_TYPE_STA) + { + LOG_E("this wlan not support sta mode"); + return -RT_ERROR; + } + wifi->connected = 0; + rthw_wifi_sta_disconnect(); + rt_wlan_dev_indicate_event_handle(wifi->wlan, RT_WLAN_DEV_EVT_AP_STOP, RT_NULL); + return RT_EOK; +} + +static rt_err_t rthw_wlan_ap_stop (struct rt_wlan_device *wlan) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + if (wifi->type != WIFI_TYPE_AP) + { + LOG_E("this wlan not support ap mode"); + return -RT_ERROR; + } + + rthw_wifi_ap_disconnect(); + return RT_EOK; +} + +static rt_err_t rthw_wlan_ap_deauth (struct rt_wlan_device *wlan, rt_uint8_t mac[]) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static rt_err_t rthw_wlan_scan_stop (struct rt_wlan_device *wlan) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static int rthw_wlan_get_rssi (struct rt_wlan_device *wlan) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)(wlan->user_data); + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + if (wifi->type != WIFI_TYPE_STA) + { + LOG_E("this wlan not support sta mode"); + return -RT_ERROR; + } + + return rthw_wifi_rssi_get(); +} + +static rt_err_t rthw_wlan_set_powersave (struct rt_wlan_device *wlan, int level) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static int rthw_wlan_get_powersave (struct rt_wlan_device *wlan) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return 0; +} + +static rt_err_t rthw_wlan_cfg_promisc (struct rt_wlan_device *wlan, rt_bool_t start) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + if(start) + { + rthw_wifi_monitor_callback_set(rthw_wlan_monitor_callback); + rthw_wifi_monitor_enable(1); + } + else + { + rthw_wifi_monitor_callback_set(RT_NULL); + rthw_wifi_monitor_enable(0); + } + return RT_EOK; +} + +static rt_err_t rthw_wlan_cfg_filter (struct rt_wlan_device *wlan, struct rt_wlan_filter *filter) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static rt_err_t rthw_wlan_set_channel (struct rt_wlan_device *wlan, int channel) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + rthw_wifi_channel_set(channel); + + return RT_EOK; +} + +static int rthw_wlan_get_channel (struct rt_wlan_device *wlan) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + + return rthw_wifi_channel_get(); +} + +static rt_err_t rthw_wlan_set_country (struct rt_wlan_device *wlan, rt_country_code_t country_code) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static rt_country_code_t rthw_wlan_get_country (struct rt_wlan_device *wlan) +{ + LOG_D("F:%s L:%d\n", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static rt_err_t rthw_wlan_set_mac (struct rt_wlan_device *wlan, rt_uint8_t mac[]) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return -RT_ERROR; +} + +static rt_err_t rthw_wlan_get_mac (struct rt_wlan_device *wlan, rt_uint8_t mac[]) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)wlan->user_data; + + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + if(mac == RT_NULL) + { + return -RT_ERROR; + } + memcpy(mac, wifi->dev_addr, MAX_ADDR_LEN); + return RT_EOK; +} + +static int rthw_wlan_recv (struct rt_wlan_device *wlan, void *buff, int len) +{ + LOG_D("F:%s L:%d", __FUNCTION__, __LINE__); + return RT_EOK; +} + +static int rthw_wlan_send (struct rt_wlan_device *wlan, void *buff, int len) +{ + struct ameba_wifi *wifi = (struct ameba_wifi *)wlan->user_data; + int idx = rthw_wifi_get_idx(wifi); + rt_base_t level; + struct sk_buff *skb = RT_NULL; + + LOG_D("F:%s L:%d len:%d", __FUNCTION__, __LINE__, len); + + level = rt_hw_interrupt_disable(); + if(!wifi->connected || !rltk_wlan_check_isup(idx)) + { + rt_hw_interrupt_enable(level); + return -RT_ERROR; + } + rltk_wlan_tx_inc(idx); + rt_hw_interrupt_enable(level); + + skb = (struct sk_buff *)rltk_wlan_alloc_skb(len); + if (skb == RT_NULL) + { + LOG_W("rltk_wlan_alloc_skb NULL for WIFI TX."); + goto exit; + } + /* copy buff to a whole ETH frame */ + memcpy(skb->tail, buff, len); + skb_put(skb, len); + rltk_wlan_send_skb(idx, skb); + +exit: + level = rt_hw_interrupt_disable(); + rltk_wlan_tx_dec(idx); + rt_hw_interrupt_enable(level); + + LOG_D("F:%s L:%d end", __FUNCTION__, __LINE__); + + return RT_EOK; +} + +static const struct rt_wlan_dev_ops ops = +{ + .wlan_init = rthw_wlan_init , + .wlan_mode = rthw_wlan_mode , + .wlan_scan = rthw_wlan_scan , + .wlan_join = rthw_wlan_join , + .wlan_softap = rthw_wlan_softap , + .wlan_disconnect = rthw_wlan_disconnect , + .wlan_ap_stop = rthw_wlan_ap_stop , + .wlan_ap_deauth = rthw_wlan_ap_deauth , + .wlan_scan_stop = rthw_wlan_scan_stop , + .wlan_get_rssi = rthw_wlan_get_rssi , + .wlan_set_powersave = rthw_wlan_set_powersave , + .wlan_get_powersave = rthw_wlan_get_powersave , + .wlan_cfg_promisc = rthw_wlan_cfg_promisc , + .wlan_cfg_filter = rthw_wlan_cfg_filter , + .wlan_set_channel = rthw_wlan_set_channel , + .wlan_get_channel = rthw_wlan_get_channel , + .wlan_set_country = rthw_wlan_set_country , + .wlan_get_country = rthw_wlan_get_country , + .wlan_set_mac = rthw_wlan_set_mac , + .wlan_get_mac = rthw_wlan_get_mac , + .wlan_recv = rthw_wlan_recv , + .wlan_send = rthw_wlan_send , +}; + +int rthw_wifi_low_init(void) +{ + static rt_int8_t _init_flag = 0; + + if (_init_flag) + { + return 1; + } + rt_memset(&wifi_sta, 0, sizeof(wifi_sta)); + rt_memset(&wifi_ap, 0, sizeof(wifi_ap)); + wifi_sta.type = WIFI_TYPE_STA; + wifi_ap.type = WIFI_TYPE_AP; + if(rthw_wifi_start(RTHW_MODE_STA_AP) != RT_EOK) + { + LOG_E("amebaz_wifi_start failed..."); + return -1; + } + LOG_I("amebaz_wifi_start success"); + LOG_D("F:%s L:%d wifi_sta:0x%08x wifi_ap:0x%08x", __FUNCTION__, __LINE__, &wifi_sta, &wifi_ap); + + wifi_reg_event_handler(RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE, rtw_connect_callbackfn, &wifi_sta); + wifi_reg_event_handler(RTHW_WIFI_EVENT_DISCONNECT, rtw_disconnect_callbackfn, &wifi_sta); + + _init_flag = 1; + + return 0; +} +INIT_DEVICE_EXPORT(rthw_wifi_low_init); diff --git a/bsp/amebaz/drivers/drv_wifi.h b/bsp/amebaz/drivers/wlan/drv_wifi.h similarity index 97% rename from bsp/amebaz/drivers/drv_wifi.h rename to bsp/amebaz/drivers/wlan/drv_wifi.h index e2ca03cd1c..b92658d470 100644 --- a/bsp/amebaz/drivers/drv_wifi.h +++ b/bsp/amebaz/drivers/wlan/drv_wifi.h @@ -25,7 +25,7 @@ #ifndef __DRV_WIFI_H__ #define __DRV_WIFI_H__ -int rt_hw_wifi_init(void); - +int rthw_wifi_low_init(void); + #endif /* __DRV_WIFI_H__ */ diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.c b/bsp/amebaz/drivers/wlan/drv_wlan.c new file mode 100644 index 0000000000..c414470633 --- /dev/null +++ b/bsp/amebaz/drivers/wlan/drv_wlan.c @@ -0,0 +1,366 @@ +/* + * File : drv_wlan.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-7-10 tyx the first version + */ + +#include "wifi_structures.h" +#include "wifi_constants.h" +#include +#include +#include "board.h" +#include "drv_wlan.h" + +// #define SCAN_WAIT_TIME (10000) + +struct scan_user_data +{ + struct rt_completion done; + scan_callback_fn fun; + void *data; +}; + +extern rthw_mode_t wifi_mode; + +rthw_mode_t rthw_wifi_mode_get(void) +{ + return wifi_mode; +} + +int rthw_wifi_stop(void) +{ + return wifi_off(); +} + +int rthw_wifi_start(rthw_mode_t mode) +{ + if(wifi_on(mode) < 0) + { + rt_kprintf("ERROR: wifi_on failed\n"); + return -1; + } + return 0; +} + +int rthw_wifi_connect(char *ssid, int ssid_len, char *password, int pass_len, rthw_security_t security_type) +{ + int mode; + rtw_wifi_setting_t setting; + + mode = rthw_wifi_mode_get(); + if ((mode != RTHW_MODE_STA) && (mode != RTHW_MODE_STA_AP)) + { + return -1; + } + if(wext_get_mode(WLAN0_NAME, &mode) < 0) + { + rt_kprintf("L:%d wifi get mode err\n", __LINE__); + return -1; + } + if(wifi_connect(ssid, security_type, password, ssid_len, pass_len, -1, NULL) != RTW_SUCCESS) + { + rt_kprintf("wifi connect fail\n"); + return -1; + } + rt_kprintf("wifi connect success\n"); + rt_kprintf("Show Wi-Fi information\n"); + wifi_get_setting(WLAN0_NAME,&setting); + wifi_show_setting(WLAN0_NAME,&setting); + return 0; +} + +int rthw_wifi_connect_bssid(char *bssid, char *ssid, int ssid_len, char *password, int pass_len, rthw_security_t security_type) +{ + int mode; + rtw_wifi_setting_t setting; + + mode = rthw_wifi_mode_get(); + if ((mode != RTHW_MODE_STA) && (mode != RTHW_MODE_STA_AP)) + { + return -1; + } + if(wext_get_mode(WLAN0_NAME, &mode) < 0) + { + rt_kprintf("L:%d wifi get mode err\n", __LINE__); + return -1; + } + + if(wifi_connect_bssid(bssid, ssid, security_type, password, 6, ssid_len, pass_len, -1, NULL) != RTW_SUCCESS) + { + rt_kprintf("wifi connect fail\n"); + return -1; + } + rt_kprintf("wifi connect success\n"); + rt_kprintf("Show Wi-Fi information\n"); + wifi_get_setting(WLAN0_NAME,&setting); + wifi_show_setting(WLAN0_NAME,&setting); + return 0; +} + +int rthw_wifi_ap_start(char *ssid, char *password, int channel) +{ + int mode = 0, timeout = 20; + rtw_security_t security_type = RTW_SECURITY_WPA2_AES_PSK; + char *name = RT_NULL; + + mode = rthw_wifi_mode_get(); + if (mode == RTHW_MODE_AP) + { + name = WLAN0_NAME; + } + else if (mode == RTHW_MODE_STA_AP) + { + name = WLAN1_NAME; + } + else + { + return -1; + } + + if(wext_get_mode(name, &mode) < 0) + { + rt_kprintf("L:%d wifi get mode err\n", __LINE__); + return -1; + } + if (password == RT_NULL) + { + security_type = RTW_SECURITY_OPEN; + } + + if(wifi_start_ap(ssid, security_type, password, rt_strlen(ssid), rt_strlen(password), 6) != 0) + { + rt_kprintf("ERROR: wifi_start_ap failed\n"); + return -1; + } + + while(1) + { + char essid[33]; + if(wext_get_ssid(name, (unsigned char *) essid) > 0) + { + if(strcmp((const char *) essid, (const char *)ssid) == 0) + { + rt_kprintf("%s started\n", ssid); + break; + } + } + if(timeout == 0) + { + rt_kprintf("Start AP timeout\n"); + return -1; + } + rt_thread_delay(1 * RT_TICK_PER_SECOND); + timeout --; + } + + return 0; +} + +static int rthw_wifi_disconnect(char *name) +{ + char essid[33]; + int timeout = 20; + const rt_uint8_t null_bssid[ETH_ALEN + 2] = {0, 0, 0, 0, 0, 1, 0, 0}; + + if (name == RT_NULL) + return -1; + + if (wext_get_ssid(name, (unsigned char *) essid) < 0) + { + rt_kprintf("\nWIFI disconnected!\n"); + return -1; + } + + if (wext_set_bssid(name, null_bssid) < 0) + { + rt_kprintf("Failed to set bogus BSSID to disconnect"); + return -1; + } + + while (1) + { + if(wext_get_ssid(name, (unsigned char *) essid) < 0) + { + rt_kprintf("WIFI disconnected!\n"); + break; + } + + if(timeout == 0) + { + rt_kprintf("ERROR: Deassoc timeout!\n"); + return -1; + } + + rt_thread_delay(10); + timeout --; + } + return 0; +} + +int rthw_wifi_sta_disconnect(void) +{ + int mode = 0; + char *name = RT_NULL; + + mode = rthw_wifi_mode_get(); + if (mode == RTHW_MODE_STA) + { + name = WLAN0_NAME; + } + else if (mode == RTHW_MODE_STA_AP) + { + name = WLAN0_NAME; + } + else + { + return -1; + } + return rthw_wifi_disconnect(name); +} + +int rthw_wifi_ap_disconnect(void) +{ + int mode = 0; + char *name = RT_NULL; + + mode = rthw_wifi_mode_get(); + if (mode == RTHW_MODE_AP) + { + name = WLAN0_NAME; + } + else if (mode == RTHW_MODE_STA_AP) + { + name = WLAN1_NAME; + } + else + { + return -1; + } + return rthw_wifi_disconnect(name); +} + +int rthw_wifi_rssi_get(void) +{ + int rssi = 0; + wifi_get_rssi(&rssi); + return rssi; +} + +void rthw_wifi_channel_set(int channel) +{ + wifi_set_channel(channel); +} + +int rthw_wifi_channel_get(void) +{ + int channel; + wifi_get_channel(&channel); + return channel; +} + +static rtw_result_t rthw_wifi_scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result) +{ + struct scan_user_data* user_data = malloced_scan_result->user_data; + struct rthw_wlan_info info = { 0 }; + + if (malloced_scan_result->scan_complete != RTW_TRUE) + { + rtw_scan_result_t* record = &malloced_scan_result->ap_details; + + if (user_data->fun != RT_NULL) + { + record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ + info.ssid = record->SSID.val; + info.bssid = record->BSSID.octet; + info.band = record->band; + info.datarate = 0; + info.channel = record->channel; + info.rssi = record->signal_strength; + info.security = record->security; + user_data->fun(&info, user_data->data); + } + } + else + { + user_data->fun(RT_NULL, user_data->data); + rt_free(user_data); + rt_kprintf("scan ap down\n"); + } + + return RTW_SUCCESS; +} + +int rthw_wifi_scan(scan_callback_fn fun, void *data) +{ + struct scan_user_data *user_data; + + if (fun == RT_NULL) + { + rt_kprintf("scan callback fun is null\n"); + return -1; + } + user_data = rt_malloc(sizeof(struct scan_user_data)); + if (user_data == RT_NULL) + { + rt_kprintf("wifi scan malloc fail\n"); + return -1; + } + user_data->fun = fun; + user_data->data = data; + + if (wifi_scan_networks(rthw_wifi_scan_result_handler, user_data) != RTW_SUCCESS) + { + rt_kprintf("ERROR: wifi scan failed\n\r"); + return -1; + } + + return 0; +} + +static rthw_wlan_monitor_callback_t monitor_callback; + +static void rthw_wifi_promisc_callback(unsigned char *buf, unsigned int len, void* userdata) +{ + if (monitor_callback) + { + monitor_callback(userdata, len, RT_NULL); + } +} + +void rthw_wifi_monitor_callback_set(rthw_wlan_monitor_callback_t callback) +{ + monitor_callback = callback; +} + +void rthw_wifi_monitor_enable(int enable) +{ + if (enable) + { + wifi_enter_promisc_mode(); + wifi_set_promisc(RTW_PROMISC_ENABLE, rthw_wifi_promisc_callback, 1); + rt_kprintf("%s run \n", __FUNCTION__); + } + else + { + wifi_set_promisc(RTW_PROMISC_DISABLE, RT_NULL, 0); + rthw_wifi_stop(); + } +} diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.h b/bsp/amebaz/drivers/wlan/drv_wlan.h new file mode 100644 index 0000000000..03a8db01e8 --- /dev/null +++ b/bsp/amebaz/drivers/wlan/drv_wlan.h @@ -0,0 +1,119 @@ +/* + * File : drv_wlan.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-7-10 tyx the first version + */ + +#ifndef __DRV_WLAN_H__ +#define __DRV_WLAN_H__ + +typedef enum +{ + RTHW_MODE_NONE = 0, + RTHW_MODE_STA, + RTHW_MODE_AP, + RTHW_MODE_STA_AP, + RTHW_MODE_PROMISC, + RTHW_MODE_P2P +}rthw_mode_t; + +#define SHARED_ENABLED 0x00008000 +#define WPA_SECURITY 0x00200000 +#define WPA2_SECURITY 0x00400000 +#define WPS_ENABLED 0x10000000 +#define WEP_ENABLED 0x0001 +#define TKIP_ENABLED 0x0002 +#define AES_ENABLED 0x0004 +#define WSEC_SWFLAG 0x0008 + +typedef enum { + RTHW_SECURITY_OPEN = 0, /**< Open security */ + RTHW_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */ + RTHW_SECURITY_WEP_SHARED = ( WEP_ENABLED | SHARED_ENABLED ), /**< WEP Security with shared authentication */ + RTHW_SECURITY_WPA_TKIP_PSK = ( WPA_SECURITY | TKIP_ENABLED ), /**< WPA Security with TKIP */ + RTHW_SECURITY_WPA_AES_PSK = ( WPA_SECURITY | AES_ENABLED ), /**< WPA Security with AES */ + RTHW_SECURITY_WPA2_AES_PSK = ( WPA2_SECURITY | AES_ENABLED ), /**< WPA2 Security with AES */ + RTHW_SECURITY_WPA2_TKIP_PSK = ( WPA2_SECURITY | TKIP_ENABLED ), /**< WPA2 Security with TKIP */ + RTHW_SECURITY_WPA2_MIXED_PSK = ( WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED ), /**< WPA2 Security with AES & TKIP */ + RTHW_SECURITY_WPA_WPA2_MIXED = ( WPA_SECURITY | WPA2_SECURITY ), /**< WPA/WPA2 Security */ + + RTHW_SECURITY_WPS_OPEN = WPS_ENABLED, /**< WPS with open security */ + RTHW_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */ + + RTHW_SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */ + + RTHW_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force rtw_security_t type to 32 bits */ +} rthw_security_t; + +typedef enum { + RTHW_WIFI_EVENT_CONNECT = 0, + RTHW_WIFI_EVENT_DISCONNECT = 1, + RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, + RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3, + RTHW_WIFI_EVENT_SCAN_DONE = 4, + RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5, + RTHW_WIFI_EVENT_SEND_ACTION_DONE = 6, + RTHW_WIFI_EVENT_RX_MGNT = 7, + RTHW_WIFI_EVENT_STA_ASSOC = 8, + RTHW_WIFI_EVENT_STA_DISASSOC = 9, + RTHW_WIFI_EVENT_STA_WPS_START = 10, + RTHW_WIFI_EVENT_WPS_FINISH = 11, + RTHW_WIFI_EVENT_EAPOL_START = 12, + RTHW_WIFI_EVENT_EAPOL_RECVD = 13, + RTHW_WIFI_EVENT_NO_NETWORK = 14, + RTHW_WIFI_EVENT_BEACON_AFTER_DHCP = 15, + RTHW_WIFI_EVENT_MAX, +}rthw_event_indicate_t; + +typedef enum { + RTHW_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */ + RTHW_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */ +} rthw_802_11_band_t; + +struct rthw_wlan_info +{ + char *ssid; + rt_uint8_t *bssid; + rthw_802_11_band_t band; + rt_uint32_t datarate; + rt_uint16_t channel; + rt_int16_t rssi; + rthw_security_t security; +}; + +typedef void (*scan_callback_fn)(struct rthw_wlan_info *info, void *user_data); +typedef void (*rthw_wlan_monitor_callback_t)(rt_uint8_t *data, int len, void *user_data); + +rthw_mode_t rthw_wifi_mode_get(void); +int rthw_wifi_stop(void); +int rthw_wifi_start(rthw_mode_t mode); +int rthw_wifi_connect(char *ssid, int ssid_len, char *password, int pass_len, rthw_security_t security_type); +int rthw_wifi_connect_bssid(char *bssid, char *ssid, int ssid_len, char *password, int pass_len, rthw_security_t security_type); +int rthw_wifi_ap_start(char *ssid, char *password, int channel); +int rthw_wifi_rssi_get(void); +void rthw_wifi_channel_set(int channel); +int rthw_wifi_channel_get(void); +int rthw_wifi_sta_disconnect(void); +int rthw_wifi_ap_disconnect(void); +int rthw_wifi_scan(scan_callback_fn fun, void *data); +void rthw_wifi_monitor_enable(int enable); +void rthw_wifi_monitor_callback_set(rthw_wlan_monitor_callback_t callback); +#endif diff --git a/bsp/amebaz/figures/iar_build.png b/bsp/amebaz/figures/iar_build.png new file mode 100644 index 0000000000..ee373d785c Binary files /dev/null and b/bsp/amebaz/figures/iar_build.png differ diff --git a/bsp/amebaz/figures/iar_download.png b/bsp/amebaz/figures/iar_download.png new file mode 100644 index 0000000000..75ebf026c5 Binary files /dev/null and b/bsp/amebaz/figures/iar_download.png differ diff --git a/bsp/amebaz/figures/image-tool_v2.2.0.png b/bsp/amebaz/figures/image-tool_v2.2.0.png new file mode 100644 index 0000000000..fceb1b7f3e Binary files /dev/null and b/bsp/amebaz/figures/image-tool_v2.2.0.png differ diff --git a/bsp/amebaz/libraries/Kconfig b/bsp/amebaz/libraries/Kconfig new file mode 100644 index 0000000000..935bb1fef9 --- /dev/null +++ b/bsp/amebaz/libraries/Kconfig @@ -0,0 +1,7 @@ +menu "External Libraries" + + config RT_USING_SMARTCONFIG_LIB + bool "Using RT-Thrad SmartConfig Library" + default n + +endmenu diff --git a/bsp/amebaz/libraries/SConscript b/bsp/amebaz/libraries/SConscript new file mode 100644 index 0000000000..ca95be14e2 --- /dev/null +++ b/bsp/amebaz/libraries/SConscript @@ -0,0 +1,12 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/amebaz/libraries/smartconfig/SConscript b/bsp/amebaz/libraries/smartconfig/SConscript new file mode 100644 index 0000000000..4ae07e3815 --- /dev/null +++ b/bsp/amebaz/libraries/smartconfig/SConscript @@ -0,0 +1,18 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +path = [cwd + '/inc'] +libs = [''] +libpath = [cwd + '/libs'] + +if rtconfig.CROSS_TOOL == 'gcc': + libs += ['libsmartconfig_armcm4_gcc'] +elif rtconfig.CROSS_TOOL == 'iar': + libs += ['libsmartconfig_armcm4_iar'] + +group = DefineGroup('smartconfig', src, depend = ['RT_USING_SMARTCONFIG_LIB'], CPPPATH = path, LIBS = libs, LIBPATH = libpath) + +Return('group') + diff --git a/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h b/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h new file mode 100644 index 0000000000..b215e983c4 --- /dev/null +++ b/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h @@ -0,0 +1,62 @@ +/* + * File : smartconfig.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-09-13 Bernard the first version + */ +#ifndef __SMARTCONFIG_H__ +#define __SMARTCONFIG_H__ + +#define SMARTCONFIG_EVENT_CHANGE_CHANNEL (1 << 0) +#define SMARTCONFIG_EVENT_LOCKED_CHANNEL (1 << 1) +#define SMARTCONFIG_EVENT_COMPLETE (1 << 2) +#define SMARTCONFIG_EVENT_RESTART (1 << 3) +#define SMARTCONFIG_EVENT_STOP (1 << 4) + +typedef enum +{ + SMARTCONFIG_TYPE_AIRKISS = 0, + SMARTCONFIG_TYPE_JDSMART = 1, + SMARTCONFIG_TYPE_ESPTOUCH, + SMARTCONFIG_TYPE_REALTOUCH, + SMARTCONFIG_TYPE_ALL, + SMARTCONFIG_TYPE_MAX, +} rt_smartconfig_type; + +typedef enum +{ + SMARTCONFIG_ENCRYPT_NONE, + SMARTCONFIG_ENCRYPT_AES, +} rt_smartconfig_encrypt_type; + +typedef int (*rt_smartconfig_result_cb)(rt_smartconfig_type result_type, char *ssid, char *passwd, \ + void *userdata, rt_uint8_t userdata_len); +typedef void (*rt_smartconfig_event_handle)(rt_uint32_t event, void *userdata); + +int rt_smartconfig_start(rt_smartconfig_type config_type, rt_smartconfig_encrypt_type encrypt_type, char *encrypt, \ + rt_smartconfig_result_cb result_cb); + +int rt_smartconfig_stop(void); + +void rt_smartconfig_set_event_handle(rt_smartconfig_event_handle handle, void *userdata); + +char *rt_smartconfig_version(void); + +#endif diff --git a/bsp/amebaz/libraries/smartconfig/libs/libsmartconfig_armcm4_gcc.a b/bsp/amebaz/libraries/smartconfig/libs/libsmartconfig_armcm4_gcc.a new file mode 100644 index 0000000000..b7e261aa08 Binary files /dev/null and b/bsp/amebaz/libraries/smartconfig/libs/libsmartconfig_armcm4_gcc.a differ diff --git a/bsp/amebaz/libraries/smartconfig/libs/libsmartconfig_armcm4_iar.a b/bsp/amebaz/libraries/smartconfig/libs/libsmartconfig_armcm4_iar.a new file mode 100644 index 0000000000..f10f3ba8d0 Binary files /dev/null and b/bsp/amebaz/libraries/smartconfig/libs/libsmartconfig_armcm4_iar.a differ diff --git a/bsp/amebaz/project.ewd b/bsp/amebaz/project.ewd new file mode 100644 index 0000000000..9d0f67c974 --- /dev/null +++ b/bsp/amebaz/project.ewd @@ -0,0 +1,2697 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/amebaz/project.ewp b/bsp/amebaz/project.ewp index adb68dc096..aa4eec3342 100644 --- a/bsp/amebaz/project.ewp +++ b/bsp/amebaz/project.ewp @@ -10,7 +10,7 @@ General 3 - 24 + 22 1 1 + + + - - - - - - @@ -181,6 +168,14 @@ CCDefines CONFIG_PLATFORM_8711B + CONFIG_BUILD_ROM + PLATFORM_RTTHREAD + __IEEE_LITTLE_ENDIAN + RT_USING_DLIBC + _DLIB_FILE_DESCRIPTOR + _DLIB_THREAD_SUPPORT + CONFIG_PLATFORM_8711B + PLATFORM_RTTHREAD __IEEE_LITTLE_ENDIAN RT_USING_DLIBC @@ -312,39 +307,39 @@ @@ -1189,6 +1174,7 @@ CCDefines NDEBUG CONFIG_PLATFORM_8711B + PLATFORM_RTTHREAD __IEEE_LITTLE_ENDIAN RT_USING_DLIBC @@ -1320,39 +1306,39 @@ @@ -844,7 +840,7 @@ @@ -1566,7 +1444,7 @@ + + C-STAT + 260 + + 1 + + 0 + + 600 + 0 + 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tm4c129x-dk/template.eww b/bsp/amebaz/template.eww similarity index 100% rename from bsp/tm4c129x-dk/template.eww rename to bsp/amebaz/template.eww diff --git a/bsp/amebaz/tmp.board b/bsp/amebaz/tmp.board index f88776bc84..1bf54bd90e 100644 --- a/bsp/amebaz/tmp.board +++ b/bsp/amebaz/tmp.board @@ -12,10 +12,10 @@ 0xb020 - CODE 0x10005000 0x10005A6B + CODE 0x10005000 0x10005A9B $PROJ_DIR$\packages\realtek_ameba-latest\sdk-ameba-v4.0b_without_NDA_GCC_V1.0.0\component\soc\realtek\8711b\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash 0xb000 --concat - CODE 0x10005a6c 0x1003dfff + CODE 0x10005a9c 0x1003dfff diff --git a/bsp/apollo2/board/adc.c b/bsp/apollo2/board/adc.c index 13be618ecf..a0044bcc37 100644 --- a/bsp/apollo2/board/adc.c +++ b/bsp/apollo2/board/adc.c @@ -19,46 +19,57 @@ * * Change Logs: * Date Author Notes - * 2017-12-04 Haley the first version + * 2017-09-18 Haley the first version */ +#include #include #include "am_mcu_apollo.h" -#include "board.h" #ifdef RT_USING_ADC -/* sem define */ -rt_sem_t adcsem = RT_NULL; +/* messagequeue define */ +struct rt_messagequeue adcbat_mq; -#define BATTERY_GPIO 29 /* Battery */ -#define BATTERY_ADC_PIN AM_HAL_PIN_29_ADCSE1 -#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE1 /* BATTERY ADCɼͨ */ -#define BATTERY_ADC_CHANNELNUM 1 /* BATTERY ADCɼͨ */ +#define BATTERY_GPIO 35 /* Battery */ +#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 +#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADCɼͨ */ +#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADCɼͨ */ #define ADC_CTIMER_NUM 3 /* ADCʹöʱ */ +#define ADC_CTIMER_COUNT (2048/512 - 1) #define ADC_CHANNEL_NUM 1 /* ADCɼͨ */ -#define ADC_SAMPLE_NUM 8 /* ADC, NE_OF_OUTPUT */ +#define ADC_SAMPLE_NUM 8 /* ADC */ -rt_uint8_t bat_adc_cnt = (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM; -rt_int16_t am_adc_buffer_pool[64]; +rt_uint8_t bat_adc_cnt = 0; +static rt_uint8_t am_adcbat_buffer_pool[256]; +static rt_int16_t am_adcbat_buffertemp[32]; -rt_uint8_t am_adc_data_get(rt_int16_t *buff, rt_uint16_t size) +rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t size) { - /* wait adc interrupt release sem forever */ - rt_sem_take(adcsem, RT_WAITING_FOREVER); + rt_uint8_t adc_bufftemp[32]; + + if (channel == BATTERY_ADC_CHANNELNUM) + { + /* wait adc message forever */ + rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER); + } /* copy the data */ - rt_memcpy(buff, am_adc_buffer_pool, size*sizeof(rt_int16_t)); + rt_memcpy(buff, adc_bufftemp, size*sizeof(rt_int16_t)); return 0; } -void am_adc_start(void) +void am_adc_start(rt_uint8_t channel) { - /* adcsem create */ - adcsem = rt_sem_create("adcsem", 0, RT_IPC_FLAG_FIFO); + /* messagequeue init */ + rt_mq_init(&adcbat_mq, "mq_adcbat", + &am_adcbat_buffer_pool[0], + 32 - sizeof(void*), + sizeof(am_adcbat_buffer_pool), + RT_IPC_FLAG_FIFO); /* Start the ctimer */ am_hal_ctimer_start(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA); @@ -67,13 +78,16 @@ void am_adc_start(void) am_hal_adc_trigger(); } -void am_adc_stop(void) +void am_adc_stop(rt_uint8_t channel) { /* Stop the ctimer */ am_hal_ctimer_stop(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA); - /* adcsem delete */ - rt_sem_delete(adcsem); + /* messagequeue delete */ + rt_mq_delete(&adceeg_mq); + + /* messagequeue delete */ + rt_mq_delete(&adcbat_mq); } /** @@ -87,6 +101,9 @@ void am_adc_isr(void) { uint32_t ui32Status, ui32FifoData; + /* enter interrupt */ + rt_interrupt_enter(); + /* Read the interrupt status */ ui32Status = am_hal_adc_int_status_get(true); @@ -101,20 +118,23 @@ void am_adc_isr(void) /* Read the value from the FIFO into the circular buffer */ ui32FifoData = am_hal_adc_fifo_pop(); - if(AM_HAL_ADC_FIFO_SLOT(ui32FifoData) == BATTERY_ADC_CHANNELNUM) - am_adc_buffer_pool[bat_adc_cnt++] = AM_HAL_ADC_FIFO_SAMPLE(ui32FifoData); - - if(bat_adc_cnt > (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM - 1) + if (AM_HAL_ADC_FIFO_SLOT(ui32FifoData) == BATTERY_ADC_CHANNELNUM) { - /* shift data */ - rt_memmove(am_adc_buffer_pool, am_adc_buffer_pool + ADC_CHANNEL_NUM*ADC_SAMPLE_NUM, ADC_CHANNEL_NUM*ADC_SAMPLE_NUM*sizeof(rt_int16_t)); - bat_adc_cnt = (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM; + am_adcbat_buffertemp[bat_adc_cnt++] = AM_HAL_ADC_FIFO_SAMPLE(ui32FifoData); + } - /* release adcsem */ - rt_sem_release(adcsem); + if ((bat_adc_cnt > ADC_SAMPLE_NUM + 2 - 1)) + { + bat_adc_cnt = 0; + + /* send the message */ + rt_mq_send(&adcbat_mq, am_adcbat_buffertemp, ADC_SAMPLE_NUM*sizeof(rt_int16_t)); } } while (AM_HAL_ADC_FIFO_COUNT(ui32FifoData) > 0); } + + /* leave interrupt */ + rt_interrupt_leave(); } static void timerA3_for_adc_init(void) @@ -129,7 +149,7 @@ static void timerA3_for_adc_init(void) am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA3); /* Set 512 sample rate */ - am_hal_ctimer_period_set(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA, 3, 1); + am_hal_ctimer_period_set(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA, ADC_CTIMER_COUNT, 1); /* Enable the timer A3 to trigger the ADC directly */ am_hal_ctimer_adc_trigger_enable(); @@ -184,7 +204,10 @@ int rt_hw_adc_init(void) /* Enable the ADC */ am_hal_adc_enable(); - rt_kprintf("adc_init!\n"); + /* Trigger the ADC once */ + //am_hal_adc_trigger(); + + //rt_kprintf("adc_init!\n"); return 0; } diff --git a/bsp/apollo2/board/adc.h b/bsp/apollo2/board/adc.h index 7e1f1eebc4..4e4396bae3 100644 --- a/bsp/apollo2/board/adc.h +++ b/bsp/apollo2/board/adc.h @@ -32,8 +32,8 @@ * */ int rt_hw_adc_init(void); -rt_uint8_t am_adc_data_get(rt_int16_t *buff, rt_uint16_t size); -void am_adc_start(void); -void am_adc_stop(void); +rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t size); +void am_adc_start(rt_uint8_t channel); +void am_adc_stop(rt_uint8_t channel); #endif // __ADC_H_ diff --git a/bsp/apollo2/board/board.c b/bsp/apollo2/board/board.c index ed1ff52302..23bc332af4 100644 --- a/bsp/apollo2/board/board.c +++ b/bsp/apollo2/board/board.c @@ -104,15 +104,17 @@ void am_low_power_init(void) /* Turn off the voltage comparator as this is enabled on reset */ am_hal_vcomp_disable(); + #ifndef RT_USING_RTC /* Run the RTC off the LFRC */ am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC); /* Stop the XT and LFRC */ am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_XT); - am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC); + //am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC); /* Disable the RTC */ am_hal_rtc_osc_disable(); + #endif } /** @@ -159,7 +161,7 @@ void rt_hw_board_init(void) /* Turn off unused Flash & SRAM */ am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_FLASH512K); - am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K); + //am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K); #endif diff --git a/bsp/apollo2/board/flash.c b/bsp/apollo2/board/flash.c index cc8e4dd499..ae224e85a1 100644 --- a/bsp/apollo2/board/flash.c +++ b/bsp/apollo2/board/flash.c @@ -140,7 +140,7 @@ int rt_hw_rom_init(void) /* register the device */ rt_device_register(&device, "rom", RT_DEVICE_FLAG_RDWR); - rt_kprintf("register device rom!\r\n"); + //rt_kprintf("register device rom!\r\n"); return 0; } diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c index 3a422dd452..c2eb1be581 100644 --- a/bsp/apollo2/board/gpio.c +++ b/bsp/apollo2/board/gpio.c @@ -24,10 +24,14 @@ #include #include +#include #include "am_mcu_apollo.h" #ifdef RT_USING_PIN +#define APLLO2_PIN_NUMBERS 64 //[34, 64] +struct rt_pin_irq_hdr am_pin_irq_hdr_tab[64]; + void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { if (mode == PIN_MODE_OUTPUT) @@ -43,12 +47,17 @@ void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) else if (mode == PIN_MODE_INPUT_PULLUP) { /* input setting: pull up. */ + am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ am_hal_gpio_pin_config(pin, AM_HAL_GPIO_OPENDRAIN); } else { /* input setting:default. */ - am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT); + am_hal_gpio_pin_config(pin, AM_HAL_GPIO_3STATE); } } @@ -58,40 +67,159 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { am_hal_gpio_out_bit_clear(pin); } - else + else if (value == PIN_HIGH) { am_hal_gpio_out_bit_set(pin); - } + } } int am_pin_read(rt_device_t dev, rt_base_t pin) { int value = PIN_LOW; - if (am_hal_gpio_input_bit_read(pin) == 0) + if (am_hal_gpio_pin_config_read(pin) == AM_HAL_GPIO_OUTPUT) { - value = PIN_LOW; + if (am_hal_gpio_out_bit_read(pin) == 0) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } } else { - value = PIN_HIGH; + if (am_hal_gpio_input_bit_read(pin) == 0) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } } return value; } -const static struct rt_pin_ops _am_pin_ops = +rt_err_t am_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + irqindex = pin; + + level = rt_hw_interrupt_disable(); + if(am_pin_irq_hdr_tab[irqindex].pin == pin && + am_pin_irq_hdr_tab[irqindex].hdr == hdr && + am_pin_irq_hdr_tab[irqindex].mode == mode && + am_pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if(am_pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + am_pin_irq_hdr_tab[irqindex].pin = pin; + am_pin_irq_hdr_tab[irqindex].hdr = hdr; + am_pin_irq_hdr_tab[irqindex].mode = mode; + am_pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t am_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + irqindex = pin; + + level = rt_hw_interrupt_disable(); + if(am_pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + am_pin_irq_hdr_tab[irqindex].pin = -1; + am_pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + am_pin_irq_hdr_tab[irqindex].mode = 0; + am_pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t am_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + irqindex = pin; + + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + + /* Configure the GPIO/button interrupt polarity */ + if (am_pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING) + { + am_hal_gpio_int_polarity_bit_set(am_pin_irq_hdr_tab[irqindex].pin, AM_HAL_GPIO_RISING); + } + else if (am_pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING) + { + am_hal_gpio_int_polarity_bit_set(am_pin_irq_hdr_tab[irqindex].pin, AM_HAL_GPIO_FALLING); + } + + /* Clear the GPIO Interrupt (write to clear) */ + am_hal_gpio_int_clear(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)); + + /* Enable the GPIO/button interrupt */ + am_hal_gpio_int_enable(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + if (am_hal_gpio_int_enable_get() != AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)) + { + return RT_ENOSYS; + } + + /* Disable the GPIO/button interrupt */ + am_hal_gpio_int_disable(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)); + } + else + { + return RT_ENOSYS; + } + + return RT_EOK; +} + +const static struct rt_pin_ops am_pin_ops = { am_pin_mode, am_pin_write, am_pin_read, + am_pin_attach_irq, + am_pin_dettach_irq, + am_pin_irq_enable, }; int rt_hw_pin_init(void) { - rt_device_pin_register("pin", &_am_pin_ops, RT_NULL); + rt_device_pin_register("pin", &am_pin_ops, RT_NULL); - rt_kprintf("pin_init!\n"); + //rt_device_pin_irq_register("pin", &am_pin_ops, RT_NULL); + //rt_kprintf("pin_init!\n"); return 0; } diff --git a/bsp/apollo2/board/i2c.c b/bsp/apollo2/board/i2c.c index cb91cdd2e5..6d1bcdc0c0 100644 --- a/bsp/apollo2/board/i2c.c +++ b/bsp/apollo2/board/i2c.c @@ -25,7 +25,6 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" /* I2C0 */ #define AM_I2C0_IOM_INST 0 @@ -43,6 +42,14 @@ #define I2C2_GPIO_SDA 25 #define I2C2_GPIO_CFG_SDA AM_HAL_PIN_25_M2SDA +/* I2C3 */ +#define AM_I2C3_IOM_INST 3 + +#define I2C3_GPIO_SCL 42 +#define I2C3_GPIO_CFG_SCK AM_HAL_PIN_42_M3SCL +#define I2C3_GPIO_SDA 43 +#define I2C3_GPIO_CFG_SDA AM_HAL_PIN_43_M3SDA + /* I2C4 */ #define AM_I2C4_IOM_INST 4 @@ -76,7 +83,7 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus; struct rt_i2c_msg *msg; int i; - rt_int32_t ret = RT_EOK; + rt_uint32_t msg_len = 0; for (i = 0; i < num; i++) { @@ -84,16 +91,16 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, if (msg->flags == RT_I2C_RD) { am_hal_iom_i2c_read(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW); + msg_len += msg->len; } else if(msg->flags == RT_I2C_WR) { am_hal_iom_i2c_write(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW); + msg_len += (msg->len - 1); } - - ret++; } - return ret; + return msg_len; } rt_err_t rt_i2c_bus_control(struct rt_i2c_bus_device *bus, @@ -136,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_0 = #ifdef RT_USING_I2C1 static struct am_i2c_bus am_i2c_bus_1 = { - {0}, + {1}, AM_I2C1_IOM_INST }; #endif @@ -144,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_1 = #ifdef RT_USING_I2C2 static struct am_i2c_bus am_i2c_bus_2 = { - {1}, + {2}, AM_I2C2_IOM_INST }; #endif @@ -152,7 +159,7 @@ static struct am_i2c_bus am_i2c_bus_2 = #ifdef RT_USING_I2C3 static struct am_i2c_bus am_i2c_bus_3 = { - {2}, + {3}, AM_I2C3_IOM_INST }; #endif @@ -160,7 +167,7 @@ static struct am_i2c_bus am_i2c_bus_3 = #ifdef RT_USING_I2C4 static struct am_i2c_bus am_i2c_bus_4 = { - {3}, + {4}, AM_I2C4_IOM_INST }; #endif @@ -203,6 +210,23 @@ int rt_i2c_init(void) rt_i2c_bus_device_register(&am_i2c->parent, "i2c2"); #endif +#ifdef RT_USING_I2C3 + /* init i2c gpio */ + am_hal_gpio_pin_config(I2C3_GPIO_SCL, I2C3_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K); + am_hal_gpio_pin_config(I2C3_GPIO_SDA, I2C3_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K); + + /* Initialize IOM 3 in I2C mode at 400KHz */ + am_hal_iom_pwrctrl_enable(AM_I2C3_IOM_INST); + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ; + am_hal_iom_config(AM_I2C3_IOM_INST, &g_sIOMConfig); + am_hal_iom_enable(AM_I2C3_IOM_INST); + + /* init i2c bus device */ + am_i2c = &am_i2c_bus_3; + am_i2c->parent.ops = &am_i2c_ops; + rt_i2c_bus_device_register(&am_i2c->parent, "i2c3"); +#endif + #ifdef RT_USING_I2C4 /* init i2c gpio */ am_hal_gpio_pin_config(I2C4_GPIO_SCL, I2C4_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K); @@ -220,7 +244,7 @@ int rt_i2c_init(void) rt_i2c_bus_device_register(&am_i2c->parent, "i2c4"); #endif - rt_kprintf("i2c_init!\n"); + //rt_kprintf("i2c_init!\n"); return 0; } diff --git a/bsp/apollo2/board/pdm.c b/bsp/apollo2/board/pdm.c index e97d2fa530..3eb46f7411 100644 --- a/bsp/apollo2/board/pdm.c +++ b/bsp/apollo2/board/pdm.c @@ -25,15 +25,15 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" #ifdef RT_USING_PDM -/* sem define */ -rt_sem_t pdmsem = RT_NULL; +/* messagequeue define */ +struct rt_messagequeue pdm_mq; -#define NWA_FRAME_MS 10 -#define NWA_FRAME_SAMPLES (16*NWA_FRAME_MS) /* 16k, 16bit, mono audio data */ +static rt_uint8_t am_pdm_buffer_pool[1024]; + +#define NWA_FRAME_SAMPLES 160 /* 8k, 16bit, mono audio data */ #define PDM_FIFO_THRESHOLD NWA_FRAME_SAMPLES #define PDM_GPIO_CLK 22 @@ -41,23 +41,16 @@ rt_sem_t pdmsem = RT_NULL; #define PDM_GPIO_DATA 23 #define PDM_GPIO_CFG_DATA AM_HAL_PIN_23_PDM_DATA -#define PING_PONG_BUF_SIZE 8000*NWA_FRAME_MS -static rt_uint16_t am_pdm_buffer_pool[PING_PONG_BUF_SIZE]; -static rt_uint8_t pdm_flag = 0; -static rt_uint16_t pdm_cnt = 0; - - static am_hal_pdm_config_t g_sPDMConfig = { - AM_HAL_PDM_PCFG_LRSWAP_DISABLE | AM_HAL_PDM_PCFG_RIGHT_PGA_P105DB | AM_HAL_PDM_PCFG_LEFT_PGA_P105DB - | AM_HAL_PDM_PCFG_MCLKDIV_DIV1 | AM_HAL_PDM_PCFG_SINC_RATE(48) | AM_HAL_PDM_PCFG_ADCHPD_ENABLE - | AM_HAL_PDM_PCFG_HPCUTOFF(0xB) | AM_HAL_PDM_PCFG_CYCLES(0x1) | AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE - | AM_HAL_PDM_PCFG_PDMCORE_ENABLE, /* Set the PDM configuration */ - AM_REG_PDM_VCFG_IOCLKEN_EN | AM_HAL_PDM_VCFG_RSTB_NORMAL | AM_REG_PDM_VCFG_PDMCLKSEL_750KHz - | AM_HAL_PDM_VCFG_PDMCLK_ENABLE | AM_HAL_PDM_VCFG_I2SMODE_DISABLE | AM_HAL_PDM_VCFG_BCLKINV_DISABLE - | AM_HAL_PDM_VCFG_DMICDEL_DISABLE | AM_HAL_PDM_VCFG_SELAP_INTERNAL | AM_HAL_PDM_VCFG_PACK_DISABLE - | AM_HAL_PDM_VCFG_CHANNEL_RIGHT, /* Set the Voice Configuration */ - PDM_FIFO_THRESHOLD, /* Select the FIFO PCM sample threshold */ + AM_HAL_PDM_PCFG_LRSWAP_DISABLE | AM_HAL_PDM_PCFG_RIGHT_PGA_0DB | AM_HAL_PDM_PCFG_LEFT_PGA_0DB + | AM_HAL_PDM_PCFG_MCLKDIV_DIV1 | AM_HAL_PDM_PCFG_SINC_RATE(48) | AM_HAL_PDM_PCFG_ADCHPD_ENABLE + | AM_HAL_PDM_PCFG_HPCUTOFF(0x1) | AM_HAL_PDM_PCFG_CYCLES(0x1) | AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE + | AM_HAL_PDM_PCFG_PDMCORE_ENABLE, /* Set the PDM configuration */ + AM_HAL_PDM_IOCLK_750KHZ | AM_HAL_PDM_VCFG_RSTB_NORMAL | AM_HAL_PDM_VCFG_PDMCLK_ENABLE + | AM_HAL_PDM_VCFG_I2SMODE_DISABLE | AM_HAL_PDM_VCFG_BCLKINV_DISABLE | AM_HAL_PDM_VCFG_DMICDEL_DISABLE + | AM_HAL_PDM_VCFG_SELAP_INTERNAL | AM_HAL_PDM_VCFG_PACK_DISABLE | AM_HAL_PDM_VCFG_CHANNEL_LEFT, /* Set the Voice Configuration */ + PDM_FIFO_THRESHOLD, /* Select the FIFO PCM sample threshold 0~256 */ }; /** @@ -71,28 +64,13 @@ static am_hal_pdm_config_t g_sPDMConfig = */ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) { - uint8_t temp; - int i; + rt_uint8_t pdm_rbufftemp[340]; - /* wait adc interrupt release sem forever */ - rt_sem_take(pdmsem, RT_WAITING_FOREVER); + /* wait pdm message forever */ + rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER); - for(i = 0; i < PING_PONG_BUF_SIZE; i++) - { - temp = (uint8_t)(am_pdm_buffer_pool[i] & 0xFF); - /* lower byte */ - while ( AM_BFRn(UART, 0, FR, TXFF) ); - AM_REGn(UART, 0, DR) = temp; - - temp = (uint8_t)((am_pdm_buffer_pool[i] & 0xFF00)>>8); - /* higher byte */ - while ( AM_BFRn(UART, 0, FR, TXFF) ); - AM_REGn(UART, 0, DR) = temp; - } /* copy the data */ - //rt_memcpy(buff, am_pdm_buffer_pool, size*sizeof(rt_uint16_t)); - - pdm_flag = 0; + rt_memcpy(buff, (char *)pdm_rbufftemp, size); return 0; } @@ -108,12 +86,9 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) */ void am_pdm_start(void) { - /* adcsem create */ - pdmsem = rt_sem_create("pdmsem", 0, RT_IPC_FLAG_FIFO); - /* Enable PDM */ - am_hal_pdm_enable(); am_hal_interrupt_enable(AM_HAL_INTERRUPT_PDM); + am_hal_pdm_enable(); } /** @@ -128,11 +103,8 @@ void am_pdm_start(void) void am_pdm_stop(void) { /* Disable PDM */ - am_hal_pdm_disable(); am_hal_interrupt_disable(AM_HAL_INTERRUPT_PDM); - - /* adcsem delete */ - rt_sem_delete(pdmsem); + am_hal_pdm_disable(); } /** @@ -153,7 +125,7 @@ uint8_t am_pdm_left_gain_get(void) /** * @brief Set the pdm left gain. * - * @param None. + * @param gain_val. * * This function Set the pdm left gain. * @@ -183,7 +155,7 @@ uint8_t am_pdm_right_gain_get(void) /** * @brief Set the pdm right gain. * - * @param None. + * @param gain_val. * * This function Set the pdm right gain. * @@ -204,33 +176,19 @@ void am_pdm_right_gain_set(uint8_t gain_val) */ void am_pdm_isr (void) { - uint32_t ui32FifoData; int i; + rt_int16_t pdm_sbufftemp[160]; /* Clear the PDM interrupt */ am_hal_pdm_int_clear(AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF | AM_HAL_PDM_INT_FIFO); for (i = 0; i < PDM_FIFO_THRESHOLD; i++) /* adjust as needed */ { - ui32FifoData = am_hal_pdm_fifo_data_read(); - - if(pdm_flag == 0) - { - am_pdm_buffer_pool[pdm_cnt * PDM_FIFO_THRESHOLD + i] = (uint16_t)ui32FifoData; - } + pdm_sbufftemp[i] = (rt_int16_t)am_hal_pdm_fifo_data_read(); } - if(pdm_flag == 0) - pdm_cnt ++; - - if(pdm_cnt == PING_PONG_BUF_SIZE/PDM_FIFO_THRESHOLD) /* 500 means 10 second logging under 8k sampling rate */ - { - pdm_cnt = 0; - pdm_flag = 1; - - /* release pdmsem */ - rt_sem_release(pdmsem); - } + /* send the message */ + rt_mq_send(&pdm_mq, pdm_sbufftemp, PDM_FIFO_THRESHOLD*sizeof(rt_int16_t)); } /** @@ -258,7 +216,14 @@ int rt_hw_pdm_init(void) /* Clear PDM interrupts */ am_hal_pdm_int_clear(AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF | AM_HAL_PDM_INT_FIFO); - rt_kprintf("pdm_init!\n"); + /* messagequeue init */ + rt_mq_init(&pdm_mq, "mq_pdm", + &am_pdm_buffer_pool[0], + 340 - sizeof(void*), + sizeof(am_pdm_buffer_pool), + RT_IPC_FLAG_FIFO); + + //rt_kprintf("pdm_init!\n"); return 0; } diff --git a/bsp/apollo2/board/pdm.h b/bsp/apollo2/board/pdm.h index b0fae857c4..43ed075da8 100644 --- a/bsp/apollo2/board/pdm.h +++ b/bsp/apollo2/board/pdm.h @@ -31,7 +31,7 @@ * @brief External function definitions * */ -int rt_hw_pdm_init(void); +int rt_pdm_init(void); rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size); void am_pdm_start(void); void am_pdm_stop(void); diff --git a/bsp/apollo2/board/pwm.h b/bsp/apollo2/board/pwm.h index 2c22e38891..53a6571264 100644 --- a/bsp/apollo2/board/pwm.h +++ b/bsp/apollo2/board/pwm.h @@ -32,5 +32,7 @@ * */ int rt_hw_pwm_init(void); +void am_pwm_start(int led); +void am_pwm_stop(int led); #endif // __PWM_H_ diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index 4ac1869472..1bc4779257 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -118,7 +118,6 @@ int rt_hw_rtc_init(void) #if RTC_CLK_SRC == XT /* Enable the XT for the RTC */ - //am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_LFRC); am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT); /* Select XT for RTC clock source */ diff --git a/bsp/apollo2/board/smbus.c b/bsp/apollo2/board/smbus.c index d2d801994e..ae41f9fac6 100644 --- a/bsp/apollo2/board/smbus.c +++ b/bsp/apollo2/board/smbus.c @@ -25,23 +25,22 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" #ifdef RT_USING_SMBUS #define SMBUS_GPIO_SDA 5 #define SMBUS_GPIO_SCL 6 -#define mSDA_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SCL) /* Clear SDA line */ -#define mSDA_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SCL) /* Set SDA line */ -#define mSCL_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SDA) /* Clear SCL line */ -#define mSCL_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SDA) /* Set SCL line */ +#define mSDA_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SDA) /* Clear SDA line */ +#define mSDA_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SDA) /* Set SDA line */ +#define mSCL_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SCL) /* Clear SCL line */ +#define mSCL_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SCL) /* Set SCL line */ -#define mSDA_READ() am_hal_gpio_input_bit_read(SMBUS_GPIO_SCL) /* Read SCL line */ +#define mSDA_READ() am_hal_gpio_input_bit_read(SMBUS_GPIO_SDA) /* Read SDA line */ -#define mSDA_IN() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_INPUT | AM_HAL_GPIO_PULL6K) /* Set SDA as Input */ -#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ -#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ +#define mSDA_IN() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_INPUT | AM_HAL_GPIO_PULL6K) /* Set SDA as Input */ +#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ +#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ #define ACK 0 #define NACK 1 diff --git a/bsp/apollo2/board/spi.c b/bsp/apollo2/board/spi.c index 5267329684..783f359af0 100644 --- a/bsp/apollo2/board/spi.c +++ b/bsp/apollo2/board/spi.c @@ -25,10 +25,9 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" #include "spi.h" -/* SPI1 */ +/* SPI0 */ #define AM_SPI0_IOM_INST 0 #define SPI0_GPIO_SCK 5 @@ -38,17 +37,17 @@ #define SPI0_GPIO_MOSI 7 #define SPI0_GPIO_CFG_MOSI AM_HAL_PIN_7_M0MOSI -/* SPI2 */ +/* SPI1 */ #define AM_SPI1_IOM_INST 1 static am_hal_iom_config_t g_sIOMConfig = { AM_HAL_IOM_SPIMODE, // ui32InterfaceMode - AM_HAL_IOM_8MHZ, // ui32ClockFrequency + AM_HAL_IOM_400KHZ, // ui32ClockFrequency 0, // bSPHA 0, // bSPOL - 4, // ui8WriteThreshold - 60, // ui8ReadThreshold + 80, // ui8WriteThreshold + 80, // ui8ReadThreshold }; /* AM spi driver */ @@ -64,7 +63,19 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat struct am_spi_bus * am_spi_bus = (struct am_spi_bus *)device->bus; rt_uint32_t max_hz = configuration->max_hz; - if(max_hz >= 8000000) + if(max_hz >= 24000000) + { + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_24MHZ; + } + else if(max_hz >= 16000000) + { + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_16MHZ; + } + else if(max_hz >= 12000000) + { + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_12MHZ; + } + else if(max_hz >= 8000000) { g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_8MHZ; } @@ -147,7 +158,6 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat /* init SPI */ am_hal_iom_disable(am_spi_bus->u32Module); - am_hal_iom_pwrctrl_enable(am_spi_bus->u32Module); am_hal_iom_config(am_spi_bus->u32Module, &g_sIOMConfig); am_hal_iom_enable(am_spi_bus->u32Module); @@ -167,14 +177,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes /* take CS */ if (message->cs_take) { - ; + am_hal_gpio_out_bit_clear(am_spi_cs->chip_select); } // if (recv_ptr != RT_NULL) { - u32TransferSize = u32BytesRemaining; - while (u32BytesRemaining) { /* Set the transfer size to either 64, or the number of remaining @@ -182,22 +190,21 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes if (u32BytesRemaining > 64) { u32TransferSize = 64; + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_PULL6K); + am_hal_gpio_out_bit_set(SPI0_GPIO_MOSI); am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); + (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW); + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K); } else { u32TransferSize = u32BytesRemaining; - /* release CS */ - if(message->cs_release) { + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_PULL6K); + am_hal_gpio_out_bit_set(SPI0_GPIO_MOSI); am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW); - } - else - { - am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K); } } @@ -207,33 +214,26 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes } // д - else if (send_ptr != RT_NULL) + else { while (u32BytesRemaining) { /* Set the transfer size to either 32, or the number of remaining bytes, whichever is smaller */ - if (u32BytesRemaining > 32) + if (u32BytesRemaining > 64) { - u32TransferSize = 32; + u32TransferSize = 64; am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); + (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); } else { u32TransferSize = u32BytesRemaining; - /* release CS */ - if (message->cs_release) { am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); } - else - { - am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); - } } u32BytesRemaining -= u32TransferSize; @@ -241,6 +241,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes } } + /* release CS */ + if(message->cs_release) + { + am_hal_gpio_out_bit_set(am_spi_cs->chip_select); + } + return message->length; } @@ -250,31 +256,31 @@ static const struct rt_spi_ops am_spi_ops = xfer }; -#ifdef RT_USING_SPI1 -static struct am_spi_bus am_spi_bus_1 = +#ifdef RT_USING_SPI0 +static struct am_spi_bus am_spi_bus_0 = { {0}, AM_SPI0_IOM_INST }; -#endif /* #ifdef RT_USING_SPI1 */ +#endif /* #ifdef RT_USING_SPI0 */ -#ifdef RT_USING_SPI2 -static struct ambiq_spi_bus ambiq_spi_bus_2 = +#ifdef RT_USING_SPI1 +static struct am_spi_bus am_spi_bus_1 = { - {1}, + {0}, AM_SPI1_IOM_INST }; -#endif /* #ifdef RT_USING_SPI2 */ +#endif /* #ifdef RT_USING_SPI1 */ int yr_hw_spi_init(void) { struct am_spi_bus* am_spi; -#ifdef RT_USING_SPI1 +#ifdef RT_USING_SPI0 /* init spi gpio */ am_hal_gpio_pin_config(SPI0_GPIO_SCK, SPI0_GPIO_CFG_SCK); - am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO); - am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI); + am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO | AM_HAL_GPIO_PULL6K); + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K); /* Initialize IOM 0 in SPI mode at 100KHz */ am_hal_iom_pwrctrl_enable(AM_SPI0_IOM_INST); @@ -282,11 +288,11 @@ int yr_hw_spi_init(void) am_hal_iom_enable(AM_SPI0_IOM_INST); //init spi bus device - am_spi = &am_spi_bus_1; - rt_spi_bus_register(&am_spi->parent, "spi1", &am_spi_ops); + am_spi = &am_spi_bus_0; + rt_spi_bus_register(&am_spi->parent, "spi0", &am_spi_ops); #endif - rt_kprintf("spi init!\n"); + //rt_kprintf("spi init!\n"); return 0; } diff --git a/bsp/apollo2/board/uart.c b/bsp/apollo2/board/uart.c index 94a76299ba..fc3884bf2d 100644 --- a/bsp/apollo2/board/uart.c +++ b/bsp/apollo2/board/uart.c @@ -25,7 +25,6 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" /* USART0 */ #define AM_UART0_INST 0 @@ -165,8 +164,14 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf else if (cfg->stop_bits == STOP_BITS_2) uart_cfg.bTwoStopBits = true; - uart_cfg.ui32Parity = cfg->parity; - uart_cfg.ui32FlowCtrl = AM_HAL_UART_PARITY_NONE; + if (cfg->parity == PARITY_NONE) + uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE; + else if (cfg->parity == PARITY_ODD) + uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD; + else if (cfg->parity == PARITY_EVEN) + uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN; + + uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE; /* UART Config */ am_hal_uart_config(uart->uart_device, &uart_cfg); @@ -181,7 +186,7 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf am_hal_uart_enable(uart->uart_device); /* Enable interrupts */ - am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX | AM_HAL_UART_INT_TX); + am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX); /* Enable the uart interrupt in the NVIC */ am_hal_interrupt_enable(uart->uart_interrupt); @@ -231,7 +236,7 @@ static int am_putc(struct rt_serial_device *serial, char c) //if (txsize > 0) { am_hal_uart_char_transmit_buffered(uart->uart_device, c); - } + } /* Wait until busy bit clears to make sure UART fully transmitted last byte */ while ( am_hal_uart_flags_get(uart->uart_device) & AM_HAL_UART_FR_BUSY ); @@ -400,9 +405,6 @@ int rt_hw_uart_init(void) #if defined(RT_USING_UART0) uart = &uart0; config.baud_rate = BAUD_RATE_115200; - config.data_bits = DATA_BITS_8; - config.stop_bits = STOP_BITS_1; - config.parity = PARITY_NONE; RCC_Configuration(uart); @@ -418,9 +420,6 @@ int rt_hw_uart_init(void) #if defined(RT_USING_UART1) uart = &uart1; config.baud_rate = BAUD_RATE_115200; - config.data_bits = DATA_BITS_8; - config.stop_bits = STOP_BITS_1; - config.parity = PARITY_NONE; RCC_Configuration(uart); diff --git a/bsp/apollo2/libraries/drivers/SConscript b/bsp/apollo2/libraries/drivers/SConscript index 6e460fbc5f..da2298889c 100644 --- a/bsp/apollo2/libraries/drivers/SConscript +++ b/bsp/apollo2/libraries/drivers/SConscript @@ -10,6 +10,7 @@ hal/am_hal_clkgen.c hal/am_hal_debug.c hal/am_hal_cachectrl.c hal/am_hal_pwrctrl.c +hal/am_hal_mcuctrl.c hal/am_hal_sysctrl.c hal/am_hal_reset.c hal/am_hal_stimer.c diff --git a/bsp/apollo2/libraries/drivers/am_mcu_apollo.h b/bsp/apollo2/libraries/drivers/am_mcu_apollo.h index bf46aa61bb..ecd55de013 100644 --- a/bsp/apollo2/libraries/drivers/am_mcu_apollo.h +++ b/bsp/apollo2/libraries/drivers/am_mcu_apollo.h @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_MCU_APOLLO_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c index 957408d0e5..87a6c60483 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h index 86b48b162c..554e997441 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_ADC_H #define AM_HAL_ADC_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name Clock Selection @@ -309,6 +304,11 @@ am_hal_adc_config_t; (((value) & AM_REG_ADC_FIFO_COUNT_M) >> AM_REG_ADC_FIFO_COUNT_S) //! @} +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c index 26c41a22e3..49b879398e 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h index b8ce914b94..beb7104516 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h @@ -38,17 +38,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CACHECTRL_H #define AM_HAL_CACHECTRL_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Cache configuration structure @@ -186,6 +181,11 @@ extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults; AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE | \ AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c index d60d7e47b5..83ac822609 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -287,16 +287,20 @@ am_hal_clkgen_int_clear(uint32_t ui32Interrupt) //! AM_HAL_CLKGEN_OSC_LFRC //! AM_HAL_CLKGEN_OSC_XT //! -//! @return 0 None. +//! @return None. // //***************************************************************************** void am_hal_clkgen_osc_start(uint32_t ui32OscFlags) { - // - // Start the oscillator(s). - // - AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags; + if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) ) + { + // + // Start the oscillator(s). + // Note that these bits are cleared in order to enable the oscillator. + // + AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags; + } } //***************************************************************************** @@ -318,10 +322,14 @@ am_hal_clkgen_osc_start(uint32_t ui32OscFlags) void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags) { - // - // Stop the oscillator(s). - // - AM_REG(CLKGEN, OCTRL) |= ui32OscFlags; + if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) ) + { + // + // Stop the oscillator(s). + // Note that these bits are set in order to stop the oscillator. + // + AM_REG(CLKGEN, OCTRL) |= ui32OscFlags; + } } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h index fc50cb9b43..3ad31bbf7f 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h @@ -38,17 +38,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CLKGEN_H #define AM_HAL_CLKGEN_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name System Clock max frequency @@ -178,6 +173,11 @@ extern "C" (AM_REG_CLKGEN_UARTEN_UART0EN_##entype << \ AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c index 13fc3c07cc..f3d06b6a76 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -68,11 +68,12 @@ // still pass in the event of a timer rollover. // //***************************************************************************** +//! Timer read workaround: Do count values differ by one tick or less. #define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) //***************************************************************************** // -// Array of function pointers for handling CTimer interrupts. +//! Array of function pointers for handling CTimer interrupts. // //***************************************************************************** am_hal_ctimer_handler_t am_hal_ctimer_ppfnHandlers[16]; @@ -162,10 +163,10 @@ back2back_reads( uint32_t u32TimerAddr, uint32_t u32Data[]) //***************************************************************************** // -// @brief Check to see if the given CTimer is using the HFRC -// -// Note - Calls to this function should be from inside a critical section. -// +//! @brief Check to see if the given CTimer is using the HFRC +//! +//! @note Calls to this function should be from inside a critical section. +//! //! @return None. // //***************************************************************************** @@ -501,7 +502,7 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber, //! @param ui32TimerSegment specifies which segment of the timer should be //! enabled. //! -//! @param ui32Configval specifies the configuration options for the selected +//! @param ui32ConfigVal specifies the configuration options for the selected //! timer. //! //! This function should be used to perform the initial set-up of the @@ -823,7 +824,7 @@ uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) { volatile uint32_t ui32Value = 0; - uint32_t ui32Values[3] = {0}; + uint32_t ui32Values[4] = {0, }; uint32_t ui32TimerAddrTbl[4] = { REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR0_O, @@ -1023,7 +1024,7 @@ am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) //! //! @param ui32TimerSegment specifies which segment of the timer to use. //! -//! @param bInvertOutpt determines whether the output should be inverted. If +//! @param bInvertOutput determines whether the output should be inverted. If //! true, the timer output pin for the selected timer segment will be //! inverted. //! @@ -1131,7 +1132,7 @@ am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, pui32CmprRegA = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CMPRA0_O + (ui32TimerNumber * TIMER_OFFSET)); - pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET; + pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET / 4; // // Write the compare register with the selected value. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h index fa1ebe16c4..dbd4d8e198 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CTIMER_H #define AM_HAL_CTIMER_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! Number of timers @@ -114,7 +109,7 @@ extern "C" //! //! These options are to be used with the \e am_hal_ctimer_config_t structure //! used by \e am_hal_ctimer_config -//! @{ +//! @{ // //***************************************************************************** #define AM_HAL_CTIMER_CLK_PIN AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0) @@ -208,6 +203,11 @@ am_hal_ctimer_config_t; //***************************************************************************** typedef void (*am_hal_ctimer_handler_t)(void); +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c index 4078b5a5a0..4f79ca7b99 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h index a482799c4f..3cb28d9367 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_DEBUG_H #define AM_HAL_DEBUG_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Debug assert macros. @@ -73,6 +68,11 @@ extern "C" #endif // AM_DEBUG_ASSERT +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function prototypes. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c index cd38da812c..db9f000a78 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c @@ -54,7 +54,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -428,6 +428,47 @@ am_hal_flash_delay(uint32_t ui32Iterations) g_am_hal_flash.delay_cycles(ui32Iterations); } +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status change. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_change(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value) +{ + while ( ui32usMaxDelay-- ) + { + // + // Check the status + // + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return 1; + } + + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + + return 0; +} // am_hal_flash_delay_status_change() + //***************************************************************************** // //! @brief Static Helper Function to check customer info valid bits erasure. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h index 66d6f5059c..dad39a6d23 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_FLASH_H #define AM_HAL_FLASH_H -#ifdef __cplusplus -extern "C" -{ -#endif - #include #include @@ -94,13 +89,19 @@ extern "C" // #define AM_HAL_FLASH_ADDR2ABSPAGE(addr) ( addr >> 13 ) +//***************************************************************************** +// +// Given an integer number of microseconds, convert to a value representing the +// number of am_hal_flash_delay() cycles that will provide that amount of delay. +// This macro is designed to take into account some of the call overhead. // -// Given a number of microseconds, convert to a value representing the number of -// cycles that will give that delay. This macro is basically taking into account -// some of the call overhead. // e.g. To provide a 2us delay: // am_hal_flash_delay( FLASH_CYCLES_US(2) ); // +// IMPORTANT - Apollo2 is spec'ed for only 48MHz operation, so this macro +// assumes that. +// +//***************************************************************************** #define FLASH_CYCLES_US(n) ((n * (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3)) - 4) // @@ -223,6 +224,11 @@ extern g_am_hal_flash_t g_am_hal_flash; #define AM_HAL_FLASH_INFO_CHUNK2INST(n) ((n >> 5) & 1 #define AM_HAL_FLASH_INFO_ADDR2CHUNK(n) ((n) >> 14) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Function prototypes for the helper functions @@ -254,6 +260,10 @@ extern void am_hal_flash_recovery(uint32_t ui32RecoveryKey); extern uint32_t am_hal_flash_load_ui32(uint32_t ui32Address); extern void am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data); extern void am_hal_flash_delay(uint32_t ui32Iterations); +extern uint32_t am_hal_flash_delay_status_change(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value); // // These functions update security/protection bits in the customer INFO blOCK. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_global.c b/bsp/apollo2/libraries/drivers/hal/am_hal_global.c index 498eb1627a..e9a3e2f67a 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_global.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_global.c @@ -43,7 +43,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_global.h b/bsp/apollo2/libraries/drivers/hal/am_hal_global.h index bb437b198a..0edb0fa745 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_global.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_global.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_GLOBAL_H #define AM_HAL_GLOBAL_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Macro definitions @@ -107,6 +102,11 @@ extern "C" //***************************************************************************** extern volatile uint32_t g_ui32HALflags; +#ifdef __cplusplus +extern "C" +{ +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c index 480118da6b..6715890737 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -479,7 +479,7 @@ am_hal_gpio_int_register(uint32_t ui32GPIONumber, //! //! This function gets the state of one GPIO polarity bit. //! -//! @note When the bit is a one the interrupt polarity is rising edge. +//! @note When the bit is a zero the interrupt polarity is rising edge. //! //! @return the current polarity. // diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h index 60e5cf36d6..553569e5ed 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -119,7 +119,7 @@ //***************************************************************************** // -// Output options +// Output options (OUTCFG) // //***************************************************************************** #define AM_HAL_GPIO_OUT_DISABLE ((0x0 << 1) << CFGVAL_GPIOCFG_S) @@ -127,6 +127,15 @@ #define AM_HAL_GPIO_OUT_OPENDRAIN ((0x2 << 1) << CFGVAL_GPIOCFG_S) #define AM_HAL_GPIO_OUT_3STATE ((0x3 << 1) << CFGVAL_GPIOCFG_S) +//***************************************************************************** +// +// Special options for IOM0 and IOM4 clocks. +// For 24MHz operation, a special enable must be selected. The 24MHZ select is +// selected via bit0 of OUTCFG (which is, in a way,an alias of OUT_PUSHPULL). +// +//***************************************************************************** +#define AM_HAL_GPIO_24MHZ_ENABLE ((0x1 << 1) << CFGVAL_GPIOCFG_S) + //***************************************************************************** // // Pad configuration options. @@ -498,13 +507,13 @@ //! @return None. // //***************************************************************************** -#define am_hal_gpio_int_polarity_bit_set(ui32PinNumber, ui32Polarity) \ - if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS ) \ +#define am_hal_gpio_int_polarity_bit_set(ui32BitNum, ui32Polarity) \ + if ( (uint32_t)(ui32BitNum) < AM_HAL_GPIO_MAX_PADS ) \ { \ AM_CRITICAL_BEGIN_ASM \ \ AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \ - AM_HAL_GPIO_POL_W(ui32PinNumber, ui32Polarity); \ + AM_HAL_GPIO_POL_W(ui32BitNum, ui32Polarity); \ AM_REGn(GPIO, 0, PADKEY) = 0; \ \ AM_CRITICAL_END_ASM \ diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c index 18e61b98f6..8c8527d7f3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c @@ -41,7 +41,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -133,7 +133,7 @@ static am_hal_i2c_bit_bang_priv_t am_hal_i2c_bit_bang_priv; // Wait for any stretched clock to go high // If it times out - return failure // -static bool +static __inline bool i2c_pull_and_wait_scl_hi(void) { // Maximum time to wait for clock stretching @@ -165,7 +165,7 @@ i2c_pull_and_wait_scl_hi(void) //! returns None. // //***************************************************************************** -am_hal_i2c_bit_bang_enum_t +am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, uint32_t sda_gpio_number) { @@ -192,7 +192,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, // // Set up SCK GPIO configuration bi-direction, input // - am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN); + am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN); // // Set SDA GPIO data bit high so we aren't pulling down the data line @@ -201,7 +201,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, // // Set up SDA GPIO configuration bi-direction, input // - am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN); + am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN); // Now make sure we have control of the clock line // @@ -284,7 +284,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, //! returns the byte received // //***************************************************************************** -static am_hal_i2c_bit_bang_enum_t +static __inline am_hal_i2c_bit_bang_enum_e i2c_receive_byte(uint8_t *pRxByte, bool bNack) { int i; @@ -389,7 +389,7 @@ i2c_receive_byte(uint8_t *pRxByte, bool bNack) //! } // //***************************************************************************** -static am_hal_i2c_bit_bang_enum_t +static __inline am_hal_i2c_bit_bang_enum_e i2c_send_byte(uint8_t one_byte) { int i; @@ -478,13 +478,13 @@ i2c_send_byte(uint8_t one_byte) //! returns ENUM{AM_HAL_I2C_BIT_BANG_SUCCESS,AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED} // //***************************************************************************** -am_hal_i2c_bit_bang_enum_t +am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, bool bUseOffset, bool bNoStop) { uint32_t ui32I; - am_hal_i2c_bit_bang_enum_t status = AM_HAL_I2C_BIT_BANG_SUCCESS; + am_hal_i2c_bit_bang_enum_e status = AM_HAL_I2C_BIT_BANG_SUCCESS; if (i2c_pull_and_wait_scl_hi()) @@ -617,13 +617,13 @@ am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, //! AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED} // //***************************************************************************** -am_hal_i2c_bit_bang_enum_t +am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, bool bUseOffset, bool bNoStop) { uint32_t ui32I; - am_hal_i2c_bit_bang_enum_t status; + am_hal_i2c_bit_bang_enum_e status; bool data_naked = false; if (i2c_pull_and_wait_scl_hi()) diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h index a9571edbe5..bc2afa46fe 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h @@ -40,17 +40,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_I2C_BIT_BANG_H #define AM_HAL_I2C_BIT_BANG_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Enumerated return constants @@ -63,24 +58,30 @@ typedef enum AM_HAL_I2C_BIT_BANG_DATA_NAKED, AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT, AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT, -}am_hal_i2c_bit_bang_enum_t; + AM_HAL_I2C_BIT_BANG_STATUS_MAX, +}am_hal_i2c_bit_bang_enum_e; + +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions // //***************************************************************************** -extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, uint32_t sda_gpio_number); -extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_send(uint8_t address, +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, bool bUseOffset, bool bNoStop); -extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_receive(uint8_t address, +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c index 2f93b09cfc..5a404211e1 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -190,7 +190,7 @@ am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority) // // OR in the new priority. // - *pui32PriorityReg |= (ui32Priority << ui32Shift); + *pui32PriorityReg = ui32OldPriority | (ui32Priority << ui32Shift); } //***************************************************************************** @@ -210,7 +210,7 @@ void am_hal_interrupt_pend_set(uint32_t ui32Interrupt) // // Check to see if the specified interrupt is valid for this MCU // - if ( ui32Interrupt > 47 ) + if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX ) { return; } @@ -247,7 +247,7 @@ void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt) // // Check to see if the specified interrupt is valid for this MCU // - if ( ui32Interrupt > 47 ) + if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX ) { return; } diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h index a8523371eb..1ba1550271 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h @@ -44,16 +44,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_INTERRUPT_H #define AM_HAL_INTERRUPT_H -#ifdef __cplusplus -extern "C" -{ -#endif //***************************************************************************** // //! @name ISR number macros. @@ -66,6 +62,7 @@ extern "C" // // Hardware interrupts // +#define AM_HAL_INTERRUPT_MAX (47) //AM_HAL_INTERRUPT_SOFTWARE3 #define AM_HAL_INTERRUPT_RESET 1 #define AM_HAL_INTERRUPT_NMI 2 #define AM_HAL_INTERRUPT_HARDFAULT 3 @@ -130,6 +127,10 @@ extern "C" //***************************************************************************** #define AM_HAL_INTERRUPT_PRIORITY(n) (((uint32_t)(n) & 0x7) << 5) +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c index 95653b9fa5..222aca352a 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c @@ -42,14 +42,13 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #include #include #include "am_mcu_apollo.h" -//#include "am_util_delay.h" #ifdef __IAR_SYSTEMS_ICC__ #define AM_INSTR_CLZ(n) __CLZ(n) @@ -62,22 +61,6 @@ #define AM_ASSERT_INVALID_THRESHOLD (1) #endif -uint32_t am_util_wait_status_change(uint32_t ui32Iterations, uint32_t ui32Address, uint32_t ui32Mask, uint32_t ui32Value) -{ - int i; - for (i = 0; i < ui32Iterations; i++) - { - // Check the status - if (((*(uint32_t *)ui32Address) & ui32Mask) == ui32Value) - { - return 1; - } - // Call the BOOTROM cycle delay function to get about 1 usec @ 48MHz - am_hal_flash_delay(16); - } - return 0; -} - //***************************************************************************** // // Forcing optimizations @@ -111,6 +94,8 @@ internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation, uint32_t ui32ChipSelect, uint32_t ui32NumBytes, uint32_t ui32Options); +static am_hal_iom_status_e +internal_iom_wait_i2c_scl_hi(uint32_t ui32Module); //***************************************************************************** // @@ -126,11 +111,6 @@ internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation, // Global state variables // //***************************************************************************** -// -// Save error status from ISR, particularly for use in I2C queue mode. -// -uint32_t g_iom_error_status = 0; - // // Define a structure to map CE for IOM4 only. // @@ -149,6 +129,26 @@ const IOMPad_t g_IOMPads[] = {5, 47, 6}, {6, 35, 4}, {7, 38, 6} }; +typedef struct +{ + uint8_t module; // IOM module + uint8_t pad; // GPIO Pad + uint8_t funcsel; // FNCSEL value +} I2CPad_t; + +// Define the mapping between I2C SCL Pads, and FNCSEL values for all IOMs. +const I2CPad_t g_I2CPads[] = +{ + {0, 5, 0}, + {1, 8, 0}, + {2, 0, 7}, + {3, 42, 4}, + {4, 39, 4}, + {5, 48, 4}, + {2, 27, 4}, +}; + +// Defines for IOM 4 Workaround #define WORKAROUND_IOM 4 #define WORKAROUND_IOM_MOSI_PIN 44 #define WORKAROUND_IOM_MOSI_CFG AM_HAL_PIN_44_M4MOSI @@ -174,10 +174,15 @@ am_hal_iom_nb_buffer; // // Global State to keep track if there is an ongoing transaction // -volatile bool g_bIomBusy[AM_REG_IOMSTR_NUM_MODULES] = {0}; +volatile bool g_bIomBusy[AM_REG_IOMSTR_NUM_MODULES + 1] = {0}; am_hal_iom_nb_buffer g_psIOMBuffers[AM_REG_IOMSTR_NUM_MODULES]; +// +// Save error status from non-blocking calls +// +static am_hal_iom_status_e g_iom_error_status[AM_REG_IOMSTR_NUM_MODULES + 1]; + //***************************************************************************** // // Computed timeout. @@ -208,6 +213,19 @@ am_hal_iom_queue_flush_t am_hal_iom_queue_flush = am_hal_iom_sleeping_queue_flus //***************************************************************************** am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; +//***************************************************************************** +// +// I2C BitBang to IOM error mapping +// +//***************************************************************************** +const am_hal_iom_status_e i2c_bb_errmap[AM_HAL_I2C_BIT_BANG_STATUS_MAX] = + { + AM_HAL_IOM_SUCCESS, // AM_HAL_I2C_BIT_BANG_SUCCESS, + AM_HAL_IOM_ERR_I2C_NAK, // AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED, + AM_HAL_IOM_ERR_I2C_NAK, // AM_HAL_I2C_BIT_BANG_DATA_NAKED, + AM_HAL_IOM_ERR_TIMEOUT, // AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT, + AM_HAL_IOM_ERR_TIMEOUT, // AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT, + }; //***************************************************************************** // @@ -215,6 +233,50 @@ am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; // //***************************************************************************** +//***************************************************************************** +// +// Get the error interrupt staus +// +//***************************************************************************** +// +//! @brief Returns the error status based on interrupt bits +//! +//! @param ui32Module - IOM module +//! ui32Status - Currently accumulated error status +//! +//! The function looks at the supplied interrupt error status bits and the +//! the current INTSTAT and maps the same to the enum am_hal_iom_status_e. +//! +//! @return Returns the appropriate error status in the form of am_hal_iom_status_e +//! +//***************************************************************************** +static am_hal_iom_status_e +internal_iom_get_int_err(uint32_t ui32Module, uint32_t ui32IntStatus) +{ + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + // + // Let's accumulate the errors + // + ui32IntStatus |= am_hal_iom_int_status_get(ui32Module, false); + + if (ui32IntStatus & AM_HAL_IOM_INT_SWERR) + { + // Error in hardware command issued or illegal access by SW + ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_I2CARBERR) + { + // Loss of I2C multi-master arbitration + ui32Status = AM_HAL_IOM_ERR_I2C_ARB; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_NAK) + { + // I2C NAK + ui32Status = AM_HAL_IOM_ERR_I2C_NAK; + } + return ui32Status; +} + //***************************************************************************** // onebit() //***************************************************************************** @@ -315,6 +377,128 @@ isRevB0(void) } } +//***************************************************************************** +// +// Checks to see if this processor is a Rev B2 device. +// +// This is needed for the B2 I2C workaround. +// +//***************************************************************************** +static bool +isRevB2(void) +{ + // + // Check to make sure the major rev is B and the minor rev is zero. + // + if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == + (AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2) ) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// +// Checks and waits for the SCL line to be high +// This is to ensure clock hi time specs are not violated in case slave did +// clock stretching in previous transaction +// +//***************************************************************************** +static am_hal_iom_status_e +internal_iom_wait_i2c_scl_hi(uint32_t ui32Module) +{ + uint32_t ui32IOMGPIO = 0xDEADBEEF; + volatile uint32_t *pui32SCLPadreg; + uint32_t ui32SCLPadregVal; + uint32_t index; + uint8_t ui8PadRegVal; + uint8_t ui8FncSelVal; + uint32_t waitStatus; + + // Need to change the SCL pin as a GPIO and poll till it is set to hi + // For all the IOM's except for IOM2, there is a single designated pin for SCL + // IOM2 has two choices and we need to determine which one + + // + // Figure out which GPIO we are using for the SCL + // + for ( index = 0; index < (sizeof(g_I2CPads) / sizeof(I2CPad_t)); index++ ) + { + // + // Is this for the IOM that we are using? + // + if ( g_I2CPads[index].module == ui32Module ) + { + // + // Get the PAD register value + // + ui8PadRegVal = ((AM_REGVAL(AM_HAL_GPIO_PADREG(g_I2CPads[index].pad))) & + AM_HAL_GPIO_PADREG_M(g_I2CPads[index].pad)) >> + AM_HAL_GPIO_PADREG_S(g_I2CPads[index].pad); + + // + // Get the FNCSEL field value + // + ui8FncSelVal = (ui8PadRegVal & 0x38) >> 3; + + // + // Is the FNCSEL filed for this pad set to the expected value? + // + if ( ui8FncSelVal == g_I2CPads[index].funcsel ) + { + // This is the GPIO we need to use. + ui32IOMGPIO = g_I2CPads[index].pad; + break; + } + } + } + if (0xDEADBEEF == ui32IOMGPIO) + { + // SCL has not been configured + return AM_HAL_IOM_ERR_INVALID_CFG; + } + + // + // Save the locations and values of the SCL pin configuration + // information. + // + pui32SCLPadreg = (volatile uint32_t *)AM_HAL_GPIO_PADREG(ui32IOMGPIO); + ui32SCLPadregVal = *pui32SCLPadreg; + // + // Temporarily configure the override pin as an input. + // + am_hal_gpio_pin_config(ui32IOMGPIO, AM_HAL_PIN_INPUT); + + // + // Make sure SCL is high within standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_HAL_GPIO_RD_REG(ui32IOMGPIO), AM_HAL_GPIO_RD_M(ui32IOMGPIO), + AM_HAL_GPIO_RD_M(ui32IOMGPIO)); + + // + // Write the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; + // Revert back the original settings + *pui32SCLPadreg = ui32SCLPadregVal; + // + // Re-lock the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = 0; + + if (waitStatus != 1) + { + return AM_HAL_IOM_ERR_TIMEOUT; + } + + return AM_HAL_IOM_SUCCESS; +} + //***************************************************************************** // //! @brief Returns the proper settings for the CLKCFG register. @@ -475,6 +659,53 @@ uint64_t iom_get_interface_clock_cfg(uint32_t ui32FreqHz, uint32_t ui32Phase ) } //iom_get_interface_clock_cfg() +//***************************************************************************** +// +//! @brief Clock setting for the I2C Clock Stretch Workaround +//! +//! This restricts the frequencies that can be used for I2C devices on +//! +//! @param ui32FreqHz - The desired interface frequency in Hz. +//! +//! @return None. +// +//***************************************************************************** +static +uint64_t iom_get_i2c_workaround_clock_cfg(uint32_t ui32FreqHz) +{ + uint32_t ui32Fsel; + + // Only allow certain SCL frequencies for clock stretching devices. + if (ui32FreqHz == AM_HAL_IOM_800KHZ) + { + ui32Fsel = 2; + } + else if (ui32FreqHz == AM_HAL_IOM_400KHZ) + { + ui32Fsel = 3; + } + else if (ui32FreqHz == AM_HAL_IOM_200KHZ) + { + ui32Fsel = 4; + } + else if (ui32FreqHz == AM_HAL_IOM_100KHZ) + { + ui32Fsel = 5; + } + else // Default is 100KHz. + { + ui32Fsel = 5; + } + + // Return the resulting CLKCFG register settings. + return (AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel) | + AM_REG_IOMSTR_CLKCFG_DIV3(0) | + AM_REG_IOMSTR_CLKCFG_DIVEN(1) | + AM_REG_IOMSTR_CLKCFG_LOWPER(14) | + AM_REG_IOMSTR_CLKCFG_TOTPER(29)); + +} // iom_get_i2c_workaround_clock_cfg + //***************************************************************************** // //! @brief Enable the IOM in the power control block. @@ -777,27 +1008,42 @@ am_hal_iom_config(uint32_t ui32Module, const am_hal_iom_config_t *psConfig) #error AM_ASSERT_INVALID_THRESHOLD must be 0 or 1. #endif - // - // An exception occurs in the LOWPER computation when setting an interface - // frequency (such as a divide by 5 frequency) which results in a 60/40 - // duty cycle. The 60% cycle must occur in the appropriate half-period, - // as only one of the half-periods is active, depending on which phase - // is being selected. - // If SPHA=0 the low period must be 60%. If SPHA=1 high period must be 60%. - // Note that the predetermined frequency parameters use the formula - // lowper = (totper-1)/2, which results in a 60% low period. - // - ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency, - psConfig->bSPHA ); + // Apply I2C clock stretching workaround if B2 silicon and IOM 1,2,3, or 5 + // Note: Only I2C clock speeds of AM_HAL_IOM_800KHZ, AM_HAL_IOM_400KHZ, + // AM_HAL_IOM_200KHZ, and AM_HAL_IOM_100KHZ are allowed. Other values will + // result in the default of AM_HAL_IOM_100KHZ. + if ((0 != ui32Module) && (4 != ui32Module) && (6 != ui32Module) && + isRevB2() && (AM_HAL_IOM_I2CMODE == psConfig->ui32InterfaceMode)) + { + // Set SPHA field to 1 on B2 silicon to enable the feature; + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_SPHA_M; + ui32ClkCfg = iom_get_i2c_workaround_clock_cfg(psConfig->ui32ClockFrequency); + } + else + { + // + // An exception occurs in the LOWPER computation when setting an interface + // frequency (such as a divide by 5 frequency) which results in a 60/40 + // duty cycle. The 60% cycle must occur in the appropriate half-period, + // as only one of the half-periods is active, depending on which phase + // is being selected. + // If SPHA=0 the low period must be 60%. If SPHA=1 high period must be 60%. + // Note that the predetermined frequency parameters use the formula + // lowper = (totper-1)/2, which results in a 60% low period. + // + ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency, + psConfig->bSPHA ); + } + if ( ui32ClkCfg ) { AM_REGn(IOMSTR, ui32Module, CLKCFG) = (uint32_t)ui32ClkCfg; } - + // // Compute the status timeout value. // - ui32StatusTimeout[ui32Module] = MAX_IOM_BITS * AM_HAL_IOM_MAX_FIFO_SIZE * + ui32StatusTimeout[ui32Module] = MAX_IOM_BITS * AM_HAL_IOM_MAX_FIFO_SIZE * IOM_OVERHEAD_FACTOR * (am_hal_clkgen_sysclk_get() / psConfig->ui32ClockFrequency); } @@ -1101,6 +1347,10 @@ am_hal_iom_workaround_word_write(uint32_t ui32ChipSelect, pui32CSPadreg, ui32CSPadregVal, ui32DelayTime, ui32ClkCfg, ui32LowClkCfg, bRising); + // + // Re-lock the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = 0; // // Update the pointer and data counter. @@ -1122,7 +1372,7 @@ am_hal_iom_workaround_word_write(uint32_t ui32ChipSelect, //! @return None. // //***************************************************************************** -#if defined(__GNUC_STDC_INLINE__) +#if defined(__GNUC__) static void __attribute__((naked)) iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, bool bRising) @@ -1164,8 +1414,7 @@ iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, __asm(" str r0, [r1]"); __asm(" bx lr"); } -#endif -#ifdef keil +#elif defined(__CC_ARM) __asm static void iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, bool bRising) @@ -1208,8 +1457,7 @@ falling_check_mosi bx lr nop } -#endif -#ifdef iar +#elif defined(__ICCARM__) static void iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, bool bRising) @@ -1276,21 +1524,29 @@ iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui8Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -1301,27 +1557,32 @@ am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, we'll just do a polled transaction. // - am_hal_iom_spi_write_nq(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_write_nq(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; } //***************************************************************************** @@ -1343,26 +1604,38 @@ am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); - + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -1373,27 +1646,131 @@ am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_spi_read(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_queue_spi_read(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, just perform a polled transaction. // - am_hal_iom_spi_read_nq(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_read_nq(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex transaction to the SPI interface. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32TxData - Pointer to the bytes that will be sent. +//! @param pui32RxData - Pointer to the bytes that will be received. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Full-Duplex operation is only supported for Apollo2 B2 Silicon. + // + if (!isRevB2()) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // +#if 0 + + // To be implemented!!! + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { +#endif + // + // Otherwise, we'll just do a polled transaction. + // + ui32Status = am_hal_iom_spi_fullduplex_nq(ui32Module, ui32ChipSelect, + pui32TxData, pui32RxData, + ui32NumBytes, ui32Options); +#if 0 + } +#endif + + return ui32Status; } //***************************************************************************** @@ -1417,10 +1794,10 @@ am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui8Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -1429,34 +1806,47 @@ am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t ui32SpaceInFifo; uint32_t ui32IntConfig; uint32_t ui32MaxFifoSize; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); // - // Wait until any earlier transactions have completed. - // - am_hal_iom_poll_complete(ui32Module); - // // Disable interrupts so that we don't get any undesired interrupts. // ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // Clear CMDCMP status - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // If we're on a B0 part, and we're using IOM4, our first byte coule be @@ -1547,23 +1937,27 @@ am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Make sure CMDCMP was raised with standard timeout // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // - // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // Re-enable IOM interrupts. // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - - // - // Return the status (0 = timeout; 1 = success) - // return ui32Status; - } //***************************************************************************** @@ -1585,10 +1979,10 @@ am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -1596,26 +1990,36 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t ui32BytesInFifo; uint32_t ui32IntConfig; uint32_t bCmdCmp = false; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); - - // - // Wait until the bus is idle, then start the requested READ transfer on - // the physical interface. - // - am_hal_iom_poll_complete(ui32Module); + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Disable interrupts so that we don't get any undesired interrupts. @@ -1627,10 +2031,8 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // If we're on a B0 part, and we're using IOM4, our first byte coule be @@ -1656,11 +2058,22 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // Wait for the dummy word to go out over the bus. // // Make sure the command complete has also been raised - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); - - + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + // Clear CMDCMP status AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); } @@ -1708,21 +2121,230 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Make sure CMDCMP was raised, // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // // Re-enable IOM interrupts. Make sure CMDCMP is cleared // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - + return ui32Status; + +} + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex operation to the SPI interface (without queuing) +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param pui32Data - Pointer to the bytes that will be received. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options) +{ + uint32_t ui32TransferSize; + uint32_t ui32SpaceInFifo; + uint32_t bCmdCmp = false; + uint32_t ui32IntConfig; + uint32_t ui32MaxFifoSize; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + // - // Return the status (0 = timeout; 1 = success) + // Validate parameters // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Full-Duplex operation is only supported for Apollo2 B2 Silicon. + // + if (!isRevB2()) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + return ui32Status; + } + + // + // Put the IOM into Full-Duplex mode. + // + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP; + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + // + // write up to the maximum FIFO size into the fifo. + // + am_hal_iom_fifo_write(ui32Module, pui32TxData, ui32TransferSize); + + // + // Start the write on the bus. + // + am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + + // + // Update the pointer and data counter. + // + pui32TxData += ui32TransferSize >> 2; + + // + // Keep looping until we're out of bytes to receive or command complete (error). + // + while ( ui32NumBytes ) + { + // + // Wait for FIFO to empty. + // + while (am_hal_iom_fifo_full_slots(ui32Module) > 0); + + am_hal_iom_fifo_read(ui32Module, pui32RxData, ui32TransferSize); + ui32NumBytes -= ui32TransferSize; + pui32RxData += ui32TransferSize >> 2; + + // + // Get the number of bytes that can be written (always a multiple of 4). + // + ui32SpaceInFifo = am_hal_iom_fifo_empty_slots(ui32Module); + + if ( ui32NumBytes <= ui32SpaceInFifo ) + { + // + // If the entire message will fit in the fifo, prepare to copy + // everything. + // + ui32TransferSize = ui32NumBytes; + } + else + { + // + // If only a portion of the message will fit in the fifo, prepare + // to copy the largest number of 4-byte blocks possible. + // + ui32TransferSize = ui32SpaceInFifo & ~(0x3); + } + + // + // Write this chunk to the fifo. + // + am_hal_iom_fifo_write(ui32Module, pui32TxData, ui32TransferSize); + + // + // Update the data pointer and bytes-left count. + // + pui32TxData += ui32TransferSize >> 2; + + // + // Check for Command Complete condition. + if ( bCmdCmp == true ) + { + // + // No more data expected. Get out of the loop + // + break; + } + + bCmdCmp = AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP); + + } + + // + // Make sure CMDCMP was raised with standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + + // + // Take the IOM out of Full-Duplex mode. + // + AM_REGn(IOMSTR, ui32Module, CFG) &= ~AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP; + return ui32Status; } @@ -1756,15 +2378,19 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui8Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32TransferSize; uint32_t ui32MaxFifoSize; @@ -1773,24 +2399,32 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; } - - // - // Make sure the transfer isn't too long for the hardware to support. - // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); - - ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? - AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); - // // Wait until the bus is idle // am_hal_iom_poll_complete(ui32Module); + // Reset the error status for non-blocking transfer + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + // // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE @@ -1798,10 +2432,8 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // Check to see if we need to do the workaround. @@ -1865,6 +2497,7 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, ui32NumBytes, ui32Options); } } + return ui32Status; } //***************************************************************************** @@ -1894,51 +2527,62 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32IntConfig; - uint32_t ui32Status = 1; - + uint32_t waitStatus; + // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); - - // - // Make sure the transfer isn't too long for the hardware to support. - // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); - + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } // // Wait until the bus is idle // am_hal_iom_poll_complete(ui32Module); + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE // set is not a guarantee that the CMDCMP has been received // - g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // - // If we're on a B0 part, and we're using IOM4, our first byte coule be + // If we're on a B0 part, and we're using IOM4, our first byte could be // corrupted, so we need to send a dummy word with chip-select held high to // get that first byte out of the way. This is only true for spi reads with // OFFSET values. @@ -1970,9 +2614,15 @@ am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // Wait for the dummy word to go out over the bus. // // Make sure the command complete has also been raised - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + return ui32Status; + } // // Re-mark IOM as busy @@ -1983,7 +2633,7 @@ am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Re-enable IOM interrupts. Make sure CMDCMP is cleared // - AM_REGn(IOMSTR, 4, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, 4, INTEN) = ui32IntConfig; } @@ -2001,9 +2651,7 @@ am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // am_hal_iom_spi_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32ChipSelect, ui32NumBytes, ui32Options); - - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - + return ui32Status; } @@ -2099,10 +2747,10 @@ am_hal_iom_spi_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui32Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -2111,17 +2759,29 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32SpaceInFifo; uint32_t ui32IntConfig; uint32_t ui32MaxFifoSize; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return 0; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until any earlier transactions have completed. + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2131,13 +2791,13 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2145,34 +2805,32 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert BB retCode to proper retCode here // - return 0; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); - // - // Wait until any earlier transactions have completed. - // - am_hal_iom_poll_complete(ui32Module); - // // Disable interrupts so that we don't get any undesired interrupts. // ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // Figure out how many bytes we can write to the FIFO immediately. @@ -2185,9 +2843,20 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, // // Start the write on the bus. // - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status = ui32Status; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } // // Update the pointer and data counter. // @@ -2236,21 +2905,25 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, // // Make sure CMDCMP was raised, // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // - // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // Re-enable IOM interrupts. // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - - // - // Return the status (0 = timeout; 1 = success) - // return ui32Status; } @@ -2275,10 +2948,10 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -2286,17 +2959,29 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32BytesInFifo; uint32_t ui32IntConfig; uint32_t bCmdCmp = false; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return 0; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2306,13 +2991,13 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2320,20 +3005,20 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert i2c bb retCode // - return 0; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); - - // - // Wait until the bus is idle - // - am_hal_iom_poll_complete(ui32Module); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Disable interrupts so that we don't get any undesired interrupts. @@ -2341,14 +3026,24 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status = ui32Status; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + // // Start a loop to catch the Rx data. // @@ -2389,21 +3084,24 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, // // Make sure CMDCMP was raised, // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // - // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // Re-enable IOM interrupts. // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - - // - // Return the status (0 = timeout; 1 = success) - // return ui32Status; } @@ -2422,23 +3120,35 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, //! See the "Command Options" section for parameters that may be ORed together //! and used in the \b ui32Options parameter. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2448,13 +3158,13 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2462,15 +3172,20 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert i2c bb retCode // - return; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -2481,27 +3196,32 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_i2c_write(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_queue_i2c_write(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, we'll just do a polled transaction. // - am_hal_iom_i2c_write_nq(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_write_nq(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; } //***************************************************************************** @@ -2532,23 +3252,35 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2558,13 +3290,13 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2572,15 +3304,20 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert i2c bb retCode // - return; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -2591,27 +3328,32 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_i2c_read(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_queue_i2c_read(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, just perform a polled transaction. // - am_hal_iom_i2c_read_nq(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_read_nq(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; } //***************************************************************************** @@ -2644,27 +3386,42 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui32Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32TransferSize; uint32_t ui32MaxFifoSize; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2672,21 +3429,27 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) { + // Reset the error status for non-blocking transfer + g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, (ui32Options & AM_HAL_IOM_NO_STOP)); } + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; // // The I2C bit-bang interface is actually a blocking transfer, and it // doesn't trigger the interrupt handler, so we have to call the @@ -2696,16 +3459,17 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, { pfnCallback(); } - // - // Return. - // - return; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); @@ -2716,21 +3480,13 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : ui32MaxFifoSize); - // - // Wait until any earlier transactions have completed, and then write our - // first word to the fifo. - // - am_hal_iom_poll_complete(ui32Module); - // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE // set is not a guarantee that the CMDCMP has been received g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; if ( am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize) > 0 ) { @@ -2752,9 +3508,14 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // // Start the write on the bus. // - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } } + return ui32Status; } //***************************************************************************** @@ -2784,24 +3545,39 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2809,21 +3585,27 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) { + // Reset the error status for non-blocking transfer + g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, (ui32Options & AM_HAL_IOM_NO_STOP)); } + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; // // The I2C bit-bang interface is actually a blocking transfer, and it // doesn't trigger the interrupt handler, so we have to call the @@ -2834,33 +3616,26 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, pfnCallback(); } - // - // Return. - // - return; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } - // - // Wait until the bus is idle - // - am_hal_iom_poll_complete(ui32Module); - - // // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE // set is not a guarantee that the CMDCMP has been received // g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // Prepare the global IOM buffer structure. @@ -2873,8 +3648,13 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // // Start the read transaction on the bus. // - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + return ui32Status; } //***************************************************************************** @@ -2889,28 +3669,32 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, //! @param ui32Options - Additional I2C options to apply to this command. //! //! This function may be used along with am_hal_iom_fifo_write and -//! am_hal_iom_fifo_read to perform more complex I2C reads and writes. This -//! function +//! am_hal_iom_fifo_read to perform more complex I2C reads and writes. +//! This function has additional logic to make sure SCL is high before a new +//! transaction is initiated. //! -//! @return None. +//! @return 0 on success // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32NumBytes, uint32_t ui32Options) { uint32_t ui32Command; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + if (ui32NumBytes == 0) + { + return AM_HAL_IOM_ERR_INVALID_PARAM; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start building the command from the operation parameter. @@ -2935,9 +3719,20 @@ am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, ui32Command |= (ui32Options & 0x5C00FF00); // - // Write the complete command word to the IOM command register. + // Wait for SCL to be high before initiating a new transaction + // This is to ensure clock hi time specs are not violated in case slave did + // clock stretching in previous transaction // - AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command; + ui32Status = internal_iom_wait_i2c_scl_hi(ui32Module); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Write the complete command word to the IOM command register. + // + AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command; + } + return ui32Status; } //***************************************************************************** @@ -3101,9 +3896,13 @@ am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, // // Make sure we check the number of bytes we're reading from the FIFO. + // This doesn't make sense for Full-Duplex operations. // - am_hal_debug_assert_msg((am_hal_iom_fifo_full_slots(ui32Module) >= ui32NumBytes), + if ( AM_REG_IOMSTR_CFG_FULLDUP_NORMAL == (AM_REGn(IOMSTR, ui32Module, CFG) & AM_REG_IOMSTR_CFG_FULLDUP_M) ) + { + am_hal_debug_assert_msg((am_hal_iom_fifo_full_slots(ui32Module) >= ui32NumBytes), "The fifo doesn't contain the requested number of bytes."); + } // // Figure out how many whole words we're reading from the fifo, and how @@ -3272,35 +4071,20 @@ am_hal_iom_status_get(uint32_t ui32Module) //! @param ui32Module IOM instance to check the status of. //! //! This function returns status indicating whether the IOM has incurred any -//! errors or not. +//! errors or not for previous operation. +//! This function can be called when the callback is invoked to determine the +//! status of the transaction just completed. +//! This function can also be called after a blocking call, though it would +//! return the same status as returned from the call itself +//! This function should not be called for an ongoing transaction, and the +//! result of such operation is indeterministic //! -//! @return 0 if all is well. -//! Otherwise error status as a bitmask of: -//! AM_HAL_IOM_ERR_INVALID_MODULE -//! AM_HAL_IOM_INT_ARB Another master initiated an operation -//! simultaenously and the IOM lost. Or -//! the IOM started an operation but found -//! SDA already low. -//! AM_HAL_IOM_INT_START A START from another master detected. -//! SW must wait for STOP before continuing. -//! AM_HAL_IOM_INT_ICMD Attempt to issue a CMD while another -//! CMD was already in progress, or issue a -//! non-zero-len write CMD with empty FIFO. -//! AM_HAL_IOM_INT_IACC Attempt to read the FIFO on a write. Or -//! an attempt to write the FIFO on a read. -//! AM_HAL_IOM_INT_NAK Expected ACK from slave not received. -//! AM_HAL_IOM_INT_FOVFL Attempt to write the FIFO while full -//! (FIFOSIZ > 124). -//! AM_HAL_IOM_INT_FUNDFL Attempt to read FIFO when empty (that is -//! FIFOSIZ < 4). -//! Note - see the datasheet text for full explanations of the INT errs. +//! @return AM_HAL_IOM_SUCCESS if all is well. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module) { - uint32_t ui32intstat = 0; - // // Validate parameters // @@ -3312,27 +4096,7 @@ am_hal_iom_error_status_get(uint32_t ui32Module) return AM_HAL_IOM_ERR_INVALID_MODULE; } - if ( AM_REGn(IOMSTR, ui32Module, STATUS) & AM_REG_IOMSTR_STATUS_ERR_ERROR ) - { - // - // The IOM is currently indicating an error condition. - // Let's figure out what is going on. - // - ui32intstat = AM_REGn(IOMSTR, ui32Module, INTSTAT); - - // - // Filter out non-error bits. - // - ui32intstat &= AM_REG_IOMSTR_INTSTAT_ARB_M | - AM_REG_IOMSTR_INTSTAT_START_M | - AM_REG_IOMSTR_INTSTAT_ICMD_M | - AM_REG_IOMSTR_INTSTAT_IACC_M | - AM_REG_IOMSTR_INTSTAT_NAK_M | - AM_REG_IOMSTR_INTSTAT_FOVFL_M | - AM_REG_IOMSTR_INTSTAT_FUNDFL_M; - } - - return ui32intstat; + return (g_iom_error_status[ui32Module]); } //***************************************************************************** @@ -3368,6 +4132,9 @@ am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status) // psBuffer = &g_psIOMBuffers[ui32Module]; + // Keep accumulating any error indications + // This is to account for the case if the error indication comes before CMDCMP + g_iom_error_status[ui32Module] |= ui32Status; // // Figure out what type of interrupt this was. // @@ -3406,6 +4173,7 @@ am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status) // psBuffer->ui32State = BUFFER_IDLE; + g_iom_error_status[ui32Module] = internal_iom_get_int_err(ui32Module, g_iom_error_status[ui32Module]); // // If we have a callback, call it now. // @@ -3623,7 +4391,7 @@ am_hal_iom_queue_length_get(uint32_t ui32Module) void am_hal_iom_queue_start_next_msg(uint32_t ui32Module) { - am_hal_iom_queue_entry_t sIOMTransaction = {0}; + am_hal_iom_queue_entry_t sIOMTransaction = {0}; uint32_t ui32ChipSelect; uint32_t *pui32Data; @@ -3631,6 +4399,7 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) uint32_t ui32Options; am_hal_iom_callback_t pfnCallback; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; uint32_t ui32Critical; // @@ -3667,22 +4436,22 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) switch ( sIOMTransaction.ui32Operation ) { case AM_HAL_IOM_QUEUE_SPI_WRITE: - am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; case AM_HAL_IOM_QUEUE_SPI_READ: - am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; case AM_HAL_IOM_QUEUE_I2C_WRITE: - am_hal_iom_i2c_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_i2c_write_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; case AM_HAL_IOM_QUEUE_I2C_READ: - am_hal_iom_i2c_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_i2c_read_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; } @@ -3692,6 +4461,14 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + // Preserve the error + g_iom_error_status[ui32Module] = ui32Status; + // Call the respective callback + pfnCallback(); + } } //***************************************************************************** @@ -3728,22 +4505,28 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start a critical section. @@ -3763,7 +4546,7 @@ am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Send the packet. // - am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -3789,17 +4572,19 @@ am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, - "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -3836,22 +4621,28 @@ am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // Start a critical section. // @@ -3870,7 +4661,7 @@ am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Send the packet. // - am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -3896,17 +4687,19 @@ am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, - "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -3943,11 +4736,12 @@ am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32Critical; // @@ -3955,10 +4749,15 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start a critical section. @@ -3978,7 +4777,7 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // // Send the packet. // - am_hal_iom_i2c_write_nb(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_write_nb(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -4004,17 +4803,19 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, - "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -4051,22 +4852,28 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start a critical section. @@ -4086,7 +4893,7 @@ am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, // // Send the packet. // - am_hal_iom_i2c_read_nb(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_read_nb(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -4112,16 +4919,19 @@ am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -4224,16 +5034,17 @@ am_hal_iom_sleeping_queue_flush(uint32_t ui32Module) //! ui32Status = am_hal_iom_int_status(0, true); //! //! // +//! // Clear the interrupts. This should be done before calling service routine +//! // as otherwise we may lose re-triggered interrupts +//! // +//! am_hal_iom_int_clear(ui32Status); +//! +//! // //! // Fill or empty the FIFO, and either continue the current operation or //! // start the next one in the queue. If there was a callback, it will be //! // called here. //! // //! am_hal_iom_queue_service(0, ui32Status); -//! -//! // -//! // Clear the interrupts before leaving the ISR. -//! // -//! am_hal_iom_int_clear(ui32Status); //! } //! @endcode //! diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h index e5a450f15c..88cb34641e 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -79,11 +79,13 @@ #define AM_HAL_IOM_2MHZ 2000000 #define AM_HAL_IOM_1_5MHZ 1500000 #define AM_HAL_IOM_1MHZ 1000000 +#define AM_HAL_IOM_800KHZ 800000 #define AM_HAL_IOM_750KHZ 750000 #define AM_HAL_IOM_500KHZ 500000 #define AM_HAL_IOM_400KHZ 400000 #define AM_HAL_IOM_375KHZ 375000 #define AM_HAL_IOM_250KHZ 250000 +#define AM_HAL_IOM_200KHZ 200000 #define AM_HAL_IOM_125KHZ 125000 #define AM_HAL_IOM_100KHZ 100000 #define AM_HAL_IOM_50KHZ 50000 @@ -176,18 +178,30 @@ #define AM_HAL_IOM_INT_FUNDFL AM_REG_IOMSTR_INTEN_FUNDFL_M #define AM_HAL_IOM_INT_THR AM_REG_IOMSTR_INTEN_THR_M #define AM_HAL_IOM_INT_CMDCMP AM_REG_IOMSTR_INTEN_CMDCMP_M -//! @} -//***************************************************************************** -// -//! @name IOM function errors -//! @brief Return values for IOM HAL function errors, such as with the function -//! am_hal_iom_error_status_get(). -//! -//! @{ -// -//***************************************************************************** -#define AM_HAL_IOM_ERR_INVALID_MODULE (1 << 30) +#define AM_HAL_IOM_INT_ALL ( \ + AM_HAL_IOM_INT_ARB | \ + AM_HAL_IOM_INT_STOP | \ + AM_HAL_IOM_INT_START | \ + AM_HAL_IOM_INT_ICMD | \ + AM_HAL_IOM_INT_IACC | \ + AM_HAL_IOM_INT_WTLEN | \ + AM_HAL_IOM_INT_NAK | \ + AM_HAL_IOM_INT_FOVFL | \ + AM_HAL_IOM_INT_FUNDFL | \ + AM_HAL_IOM_INT_THR | \ + AM_HAL_IOM_INT_CMDCMP) + +#define AM_HAL_IOM_INT_SWERR ( \ + AM_HAL_IOM_INT_ICMD | \ + AM_HAL_IOM_INT_FOVFL | \ + AM_HAL_IOM_INT_FUNDFL | \ + AM_HAL_IOM_INT_IACC) + +#define AM_HAL_IOM_INT_I2CARBERR ( \ + AM_HAL_IOM_INT_ARB | \ + AM_HAL_IOM_INT_START | \ + AM_HAL_IOM_INT_STOP) //! @} //***************************************************************************** @@ -204,6 +218,31 @@ #define AM_HAL_IOM_I2CBB_MODULE AM_REG_IOMSTR_NUM_MODULES //! @} +//***************************************************************************** +// +//! @name IOM Return Codes +//! @brief Enum definitions for defining return values for IOM APIs +//! +//! This enum defines possible values for non-void IOM APIs +//! +//! @{ +// +//***************************************************************************** +typedef enum +{ + AM_HAL_IOM_SUCCESS = 0, + AM_HAL_IOM_ERR_TIMEOUT, + AM_HAL_IOM_ERR_INVALID_MODULE, + AM_HAL_IOM_ERR_INVALID_PARAM, + AM_HAL_IOM_ERR_INVALID_CFG, + AM_HAL_IOM_ERR_INVALID_OPER, + AM_HAL_IOM_ERR_I2C_NAK, + AM_HAL_IOM_ERR_I2C_ARB, + AM_HAL_IOM_ERR_RESOURCE_ERR, +} am_hal_iom_status_e ; + +//! @} + //***************************************************************************** // //! @brief Union type for a word-aligned, byte-addressable array. @@ -271,7 +310,7 @@ typedef struct //! Select the SPI clock polarity (unused in I2C mode). // bool bSPOL; - + // //! @brief Select the FIFO write threshold. //! @@ -404,7 +443,11 @@ am_hal_iom_pwrsave_t; // //***************************************************************************** extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; -extern uint32_t g_iom_error_status; + +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // @@ -420,23 +463,30 @@ extern void am_hal_iom_config(uint32_t ui32Module, extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module); extern void am_hal_iom_enable(uint32_t ui32Module); extern void am_hal_iom_disable(uint32_t ui32Module); -extern void am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options); + +extern am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern uint32_t am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); @@ -445,39 +495,39 @@ extern void am_hal_iom_spi_cmd_run(uint32_t ui32Operation, uint32_t ui32ChipSelect, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_i2c_write(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_i2c_read(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_i2c_write_nq(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_i2c_read_nq(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_i2c_write_nb(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_i2c_read_nb(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, +extern am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32NumBytes, @@ -485,7 +535,7 @@ extern void am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, extern void am_hal_iom_command_repeat_set(uint32_t ui32Module, uint32_t ui32CmdCount); extern uint32_t am_hal_iom_status_get(uint32_t ui32Module); -extern uint32_t am_hal_iom_error_status_get(uint32_t ui32Module); +extern am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module); extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, uint32_t ui32NumBytes); extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, @@ -505,19 +555,19 @@ extern void am_hal_iom_queue_init(uint32_t ui32ModuleNum, uint32_t ui32QueueMemSize); extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module); extern void am_hal_iom_sleeping_queue_flush(uint32_t ui32Module); -extern void am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, +extern am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, +extern am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); @@ -533,7 +583,6 @@ extern void am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Statu void am_iomaster##x##_isr(void) \ { \ uint32_t ui32IntStatus; \ - g_iom_error_status = am_hal_iom_error_status_get(x); \ ui32IntStatus = am_hal_iom_int_status_get(x, false); \ am_hal_iom_int_clear(x, ui32IntStatus); \ am_hal_iom_queue_service(x, ui32IntStatus); \ @@ -543,12 +592,15 @@ void am_iomaster##x##_isr(void) \ void am_iomaster##x##_isr(void) \ { \ uint32_t ui32IntStatus; \ - g_iom_error_status = am_hal_iom_error_status_get(x); \ ui32IntStatus = am_hal_iom_int_status_get(x, false); \ am_hal_iom_int_clear(x, ui32IntStatus); \ am_hal_iom_int_service(x, ui32IntStatus); \ } +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_IOM_H //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c index 0f34aa6efb..921d6eeade 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -61,6 +61,7 @@ typedef struct volatile uint32_t ui32WriteIndex; volatile uint32_t ui32ReadIndex; volatile uint32_t ui32Length; + uint32_t ui32FifoInc; uint32_t ui32Capacity; } am_hal_ios_buffer_t; @@ -103,6 +104,23 @@ uint8_t *g_pui8FIFOPtr = (uint8_t *) REG_IOSLAVE_BASEADDR; uint8_t g_ui32HwFifoSize = 0; uint32_t g_ui32FifoBaseOffset = 0; +//***************************************************************************** +// +// Checks to see if this processor is a Rev B2 device. +// +// This is needed to disable SHELBY-1654 workaround. +// +//***************************************************************************** +bool +isRevB2(void) +{ + // + // Check to make sure the major rev is B and the minor rev is 2. + // + return ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == \ + (AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | (AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 + 2)) ); +} + //***************************************************************************** // //! @brief Enable the IOS in the power control block. @@ -957,7 +975,10 @@ am_hal_ios_fifo_service(uint32_t ui32Status) } } } - resync_fifoSize(); + if (!isRevB2()) + { + resync_fifoSize(); + } // // Need to retake the FIFO space, after Threshold interrupt has been reenabled @@ -1041,7 +1062,10 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) ui32NumBytes -= ui32FIFOSpace; pui8Data += ui32FIFOSpace; }; - resync_fifoSize(); + if (!isRevB2()) + { + resync_fifoSize(); + } } // @@ -1102,6 +1126,8 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) } } + // Number of bytes written + g_sSRAMBuffer.ui32FifoInc += totalBytes - ui32NumBytes; return (totalBytes - ui32NumBytes); } @@ -1114,7 +1140,7 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) //! //! This function will write data from the caller-provided array to the IOS //! LRAM FIFO. This simple routine does not use SRAM buffering for large -//! messages. +//! messages. This function also updates the FIFOCTR. //! //! The maximum message size for the IO Slave is 128 bytes. //! @@ -1140,6 +1166,8 @@ am_hal_ios_fifo_write_simple(uint8_t *pui8Data, uint32_t ui32NumBytes) if ( ui32NumBytes <= ui32FIFOSpace ) { fifo_write(pui8Data, ui32NumBytes); + // Write FIFOINC + AM_BFW(IOSLAVE, FIFOINC, FIFOINC, ui32NumBytes); } else { @@ -1209,6 +1237,7 @@ am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray, psBuffer->ui32ReadIndex = 0; psBuffer->ui32Length = 0; psBuffer->ui32Capacity = ui32Bytes; + psBuffer->ui32FifoInc = 0; psBuffer->pui8Data = (uint8_t *)pvArray; } @@ -1273,12 +1302,19 @@ am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes) //! @brief Update the FIFOCTR to inform host of available data to read. //! //! This function allows the application to indicate to HAL when it is safe to -//! update the FIFOCTR. +//! update the FIFOCTR. This function needs to be used in conjunction with +//! am_hal_ios_fifo_write(), which itself does not update the FIFOCTR //! +//! CAUTION: //! Application needs to implement some sort of //! synchronization with the host to make sure host is not reading FIFOCTR while //! it is being updated by the MCU, since the FIFOCTR read over -//! IO is not an atomic operation. +//! IO is not an atomic operation. Otherwise, some other logic could be implemented +//! by the host to detect and disregard transient values of FIFOCTR (e.g. multiple +//! reads till it gets a stable value). +//! For Pre-B2 parts, it is necessary to have this synchronization guarantee that +//! Host is not doing any READ operation - be it for FIFOCTR or FIFO itself when +//! this call is made, as otherwise the FIFOCTR value may get corrupted. //! //! //! @return None. @@ -1287,11 +1323,9 @@ am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes) void am_hal_ios_update_fifoctr(void) { - uint32_t ui32Val; - // Determine the available data - ui32Val = am_hal_ios_fifo_space_used(); - // Update FIFOCTR - AM_BFW(IOSLAVE, FIFOCTR, FIFOCTR, ui32Val); + // Write FIFOINC + AM_BFW(IOSLAVE, FIFOINC, FIFOINC, g_sSRAMBuffer.ui32FifoInc); + g_sSRAMBuffer.ui32FifoInc = 0; return; } diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h index b166c9c6e5..20af148d97 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h @@ -42,16 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_IOS_H #define AM_HAL_IOS_H -#ifdef __cplusplus -extern "C" -{ -#endif //***************************************************************************** // @@ -300,6 +296,10 @@ typedef struct } am_hal_ios_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c index 0f57c0d417..8e7949edc7 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -56,30 +56,6 @@ // //***************************************************************************** -//***************************************************************************** -// -//! @brief Delays for a desired amount of microseconds. -//! -//! @note - This function is based on the similar function in am_util_delay.c, -//! please see that module for implementation details. It was necessary to -//! duplicate it here to avoid having to update every example to include the -//! am_util_delay.c module in its build. -//! -//! @returns None -// -//***************************************************************************** -void -am_hal_itm_delay_us(uint32_t ui32MicroSeconds) -{ - uint32_t ui32Iterations = ui32MicroSeconds * - (am_hal_clkgen_sysclk_get() / 3000000); - - // - // Call the BOOTROM cycle delay function - // - am_hal_flash_delay(ui32Iterations); -} - //***************************************************************************** // //! @brief Enables the ITM @@ -118,7 +94,7 @@ am_hal_itm_enable(void) AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff; // - // Write to the ITM control and status register (don't enable yet). + // Write to the ITM control and status register. // AM_REGVAL(AM_REG_ITM_TCR_O) = AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15) | @@ -129,6 +105,7 @@ am_hal_itm_enable(void) AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1); + } //***************************************************************************** @@ -203,7 +180,7 @@ am_hal_itm_not_busy(void) // // wait for 50us for the data to flush out // - am_hal_itm_delay_us(50); + am_hal_flash_delay(FLASH_CYCLES_US(50)); } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h index e747b0ab65..78f0b7a993 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h @@ -42,18 +42,13 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_ITM_H #define AM_HAL_ITM_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Sync Packet Defines @@ -71,12 +66,16 @@ extern "C" #define AM_HAL_ITM_PRINT_NUM_REGS 1 extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS]; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions // //***************************************************************************** -extern void am_hal_itm_delay_us(uint32_t ui32MicroSeconds); extern void am_hal_itm_enable(void); extern void am_hal_itm_disable(void); extern void am_hal_itm_not_busy(void); diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c index f7b60e3c1a..3e5eeb2c59 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h index 6811006fd6..b93515347d 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_MCUCTRL_H #define AM_HAL_MCUCTRL_H -#ifdef __cplusplus -extern "C" -{ -#endif - // // Deprecate the am_hal_mcuctrl_bucks_enable() and disable() functions. // This functionality is now handled in pwrctrl. @@ -188,6 +183,11 @@ typedef struct } am_hal_mcuctrl_fault_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c index 67d08448da..99ce2493b3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #include "am_mcu_apollo.h" diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h index d938e916fb..3ea13618d3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h @@ -38,17 +38,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_OTP_H #define AM_HAL_OTP_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Define some OTP values and macros. @@ -82,6 +77,11 @@ extern "C" #define AM_OTP_SRAM_LOCKOUT_S (2) #define AM_OTP_SRAM_LOCKOUT_M (0x1 << AM_OTP_SRAM_LOCKOUT_S) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Function prototypes diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c index 45acfab995..b8ca3dde5c 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h index a6e23d2698..77c0ad9488 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h @@ -42,13 +42,18 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_PDM_H #define AM_HAL_PDM_H +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Macro definitions @@ -655,6 +660,10 @@ extern void am_hal_pdm_disable(void); extern uint32_t am_hal_pdm_int_status_get(bool bEnabledOnly); +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_PDM_H //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h index 8a1068f882..0173881bae 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h @@ -41,7 +41,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -55,7 +55,7 @@ //***************************************************************************** #define AM_HAL_PIN_DIR_INPUT (AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_DIR_OUTPUT (AM_HAL_GPIO_OUT_PUSHPULL) -#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN) #define AM_HAL_PIN_DIR_3STATE (AM_HAL_GPIO_OUT_3STATE) //***************************************************************************** @@ -81,25 +81,25 @@ #define AM_HAL_PIN_0_MxSCKLB (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_0_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_0_MxSCLLB (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) -#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_1_SLMISO (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_1_UART0TX (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_1_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_1_MxMISOLB (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_1_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_1_MxSDALB (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) -#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_2_SLMOSI (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_2_UART0RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_2_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_2_MxMOSILB (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_2_M2MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_2_MxWIR3LB (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_3_UART0RTS (AM_HAL_GPIO_FUNC(0)) #define AM_HAL_PIN_3_SLnCE (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) @@ -109,7 +109,6 @@ #define AM_HAL_PIN_3_M2nCE0 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_3_TRIG1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_3_I2S_WCLK (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_3_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER) #define AM_HAL_PIN_4_UART0CTS (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_4_SLINT (AM_HAL_GPIO_FUNC(1)) @@ -119,17 +118,18 @@ #define AM_HAL_PIN_4_M2nCE5 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_4_CLKOUT (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_4_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) +// PSINK usage: GPIOWT=0 to activate the power switch, GPIOWT=1 to disable +#define AM_HAL_PIN_4_PSINK (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_POWER) -#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_5_M0SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_5_UART0RTS (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_5_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_5_M0SCKLB (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_5_EXTHFA (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_5_M0SCLLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_5_M1nCE2 (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_6_M0MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_6_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_6_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -138,7 +138,7 @@ #define AM_HAL_PIN_6_SLSDALB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_6_I2S_DAT (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_7_M0MOSI (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_7_CLKOUT (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_7_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -147,7 +147,7 @@ #define AM_HAL_PIN_7_SLWIR3LB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_7_M1nCE1 (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_8_M1SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_8_M0nCE4 (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_8_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -156,7 +156,7 @@ #define AM_HAL_PIN_8_UART1TX (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_8_M1SCLLB (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_9_M1MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_9_M0nCE5 (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_9_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -165,7 +165,7 @@ #define AM_HAL_PIN_9_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_9_SLSDALB (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_10_M1MOSI (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_10_M0nCE6 (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_10_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -182,7 +182,6 @@ #define AM_HAL_PIN_11_UART1CTS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_11_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_11_PDM_DATA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) -#define AM_HAL_PIN_11_PSINK (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_12_ADCD0NSE9 (AM_HAL_GPIO_FUNC(0)) #define AM_HAL_PIN_12_M1nCE0 (AM_HAL_GPIO_FUNC(1)) @@ -198,7 +197,6 @@ #define AM_HAL_PIN_13_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_13_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_13_M2nCE3 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_13_EXTHFB (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_13_UART0RTS (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_13_UART1RX (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) @@ -207,7 +205,6 @@ #define AM_HAL_PIN_14_UART1TX (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_14_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_14_M2nCE1 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_14_EXTHFS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_14_SWDCK (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_14_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) @@ -216,7 +213,6 @@ #define AM_HAL_PIN_15_UART1RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_15_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_15_M2nCE2 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_15_EXTXT (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_15_SWDIO (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_15_SWO (AM_HAL_GPIO_FUNC(7)) @@ -234,7 +230,6 @@ #define AM_HAL_PIN_17_TRIG1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_17_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_17_M4nCE3 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_17_EXTLF (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_17_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_17_UART1CTS (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) @@ -243,7 +238,6 @@ #define AM_HAL_PIN_18_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_18_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_18_M4nCE1 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_18_ANATEST2 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_18_UART1TX (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_18_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) @@ -252,7 +246,6 @@ #define AM_HAL_PIN_19_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_19_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_19_TCTA1 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) -#define AM_HAL_PIN_19_ANATEST1 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_19_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_19_I2S_BCLK (AM_HAL_GPIO_FUNC(7)) @@ -277,6 +270,7 @@ #define AM_HAL_PIN_22_PDM_CLK (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_22_TCTB1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_22_SWO (AM_HAL_GPIO_FUNC(7)) +// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable #define AM_HAL_PIN_22_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER) #define AM_HAL_PIN_23_UART0RX (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) @@ -299,17 +293,15 @@ #endif // defined (AM_PACKAGE_BGA) #if defined (AM_PACKAGE_BGA) -#define AM_HAL_PIN_25_EXTXT (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_25_M0nCE2 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_25_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_25_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_25_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_25_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_25_SLSDALB (AM_HAL_GPIO_FUNC(7)) #endif // defined (AM_PACKAGE_BGA) -#define AM_HAL_PIN_26_EXTLF (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_26_M0nCE3 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_26_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_26_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -319,11 +311,10 @@ #define AM_HAL_PIN_26_M3nCE0 (AM_HAL_GPIO_FUNC(7)) #if defined (AM_PACKAGE_BGA) -#define AM_HAL_PIN_27_EXTHF (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_27_M1nCE4 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_27_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_27_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_27_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_27_M2SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_27_M2SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -333,7 +324,7 @@ #define AM_HAL_PIN_28_M1nCE5 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_28_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_28_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_28_M2MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_28_M5nCE3 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_28_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -353,7 +344,6 @@ #define AM_HAL_PIN_30_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_30_UART0TX (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_30_UART1RTS (AM_HAL_GPIO_FUNC(5)) -#define AM_HAL_PIN_30_SWO (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_30_I2S_DAT (AM_HAL_GPIO_FUNC(7)) #endif // defined (AM_PACKAGE_BGA) @@ -433,7 +423,7 @@ #define AM_HAL_PIN_38_M1nCE3 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_38_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_38_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_38_M3MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_38_M4nCE7 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_38_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -443,7 +433,7 @@ #define AM_HAL_PIN_39_UART1TX (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_39_CLKOUT (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_39_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_39_M4SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_39_M4SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_39_M4SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -452,7 +442,7 @@ #define AM_HAL_PIN_40_UART1RX (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_40_TRIG0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_40_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_40_M4MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_40_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_40_SLSDALB (AM_HAL_GPIO_FUNC(7)) @@ -465,6 +455,7 @@ #define AM_HAL_PIN_41_M5nCE7 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_41_M4nCE2 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_41_UART0RTS (AM_HAL_GPIO_FUNC(7)) +// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable #define AM_HAL_PIN_41_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER) #if defined (AM_PACKAGE_BGA) @@ -472,7 +463,7 @@ #define AM_HAL_PIN_42_M0nCE0 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_42_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_42_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_42_M3SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_42_M3SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_42_M3SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -483,7 +474,7 @@ #define AM_HAL_PIN_43_M0nCE1 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_43_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_43_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_43_M3MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_43_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_43_SLSDALB (AM_HAL_GPIO_FUNC(7)) @@ -493,7 +484,7 @@ #define AM_HAL_PIN_44_M0nCE2 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_44_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_44_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_44_M4MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_44_M5nCE6 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_44_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -506,7 +497,7 @@ #define AM_HAL_PIN_45_M4nCE3 (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_45_M3nCE6 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_45_M5nCE5 (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_45_TCTA1 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_45_SWO (AM_HAL_GPIO_FUNC(7)) #endif // defined (AM_PACKAGE_BGA) #if defined (AM_PACKAGE_BGA) @@ -524,7 +515,7 @@ #define AM_HAL_PIN_47_M0nCE5 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_47_TCTB2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_47_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_47_M5MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_47_M4nCE5 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_47_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -533,7 +524,7 @@ #define AM_HAL_PIN_48_M0nCE6 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_48_TCTA3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_48_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_48_M5SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_48_M5SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_48_M5SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -542,7 +533,7 @@ #define AM_HAL_PIN_49_M0nCE7 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_49_TCTB3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_49_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_49_M5MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_49_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_49_SLSDALB (AM_HAL_GPIO_FUNC(7)) diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c index cc91eeb159..b16b909308 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h index bc9adabf84..8068253900 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -319,6 +319,11 @@ #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Function prototypes @@ -332,6 +337,10 @@ extern void am_hal_pwrctrl_bucks_enable(void); extern void am_hal_pwrctrl_bucks_disable(void); extern void am_hal_pwrctrl_low_power_init(void); +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_PWRCTRL_H //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c index 66a9846c29..f54b90a1e0 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h index 11e8ace90a..8cab7dd907 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_QUEUE_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c index 86d5cf10b7..19ef48dcd3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h index a3273dad10..5e914f4d18 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_RSTGEN_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c index 4630d5a117..44fccb49db 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h index 9304a6c67f..c49cdf25de 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_RTC_H #define AM_HAL_RTC_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name OSC Start and Stop @@ -149,6 +144,11 @@ typedef struct am_hal_rtc_time_struct uint32_t ui32Hundredths; }am_hal_rtc_time_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c index 0cdd706c9e..ed94beb5a1 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -136,11 +136,14 @@ am_hal_stimer_counter_clear(void) //! //! @param ui32CmprInstance is the compare register instance number (0-7). //! @param ui32Delta is the value to add to the STimer counter and load into -//! the comparator register. +//! the comparator register. It should be > 1 //! //! NOTE: There is no way to set an absolute value into a comparator register. //! Only deltas added to the STimer counter can be written to the compare //! registers. +//! CAUTION: The HAL implementation requires temporarily disabling the +//! comparison. To avoid the remote possibility of losing an interrupt +//! during that time, delta should always be set to a value greater than 1 //! //! @return None. // @@ -148,12 +151,32 @@ am_hal_stimer_counter_clear(void) void am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta) { + uint32_t cfgVal; + uint32_t ui32Critical = 0; if ( ui32CmprInstance > 7 ) { return; } + cfgVal = AM_REG(CTIMER, STCFG); + // We need to disable the compare temporarily while setting the delta value + // That leaves a corner case where we could miss the trigger if setting a very + // small delta. To avoid this, we take critical section, and we should ensure + // that delta value is at least > 1 + + // Disable the compare if already enabled, when setting the new value + AM_REG(CTIMER, STCFG) &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance)); + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; + // Restore Compare Enable bit + AM_REG(CTIMER, STCFG) |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance); + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h index bd4b09feae..5368c4af81 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_STIMER_H #define AM_HAL_STIMER_H -#ifdef __cplusplus -extern "C" -{ -#endif - // // Compute address of a given COMPARE or CAPTURE register. // Note - For Apollo2, the parameter n should be 0 (as only 1 stimer module @@ -204,6 +199,11 @@ am_hal_stimer_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c index 50e0b67915..57cd34b95d 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -731,8 +731,6 @@ am_hal_sysctrl_buck_update_complete(void) static void am_hal_sysctrl_buckA_ctimer_isr(void) { - volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1; - // // Begin critical section. // Although a relatively long time, the following 2us delay is critically @@ -792,8 +790,6 @@ am_hal_sysctrl_buckA_ctimer_isr(void) static void am_hal_sysctrl_buckB_ctimer_isr(void) { - volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1; - // // Begin critical section. // Although a relatively long time, the following 2us delay is critically diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h index 34c72b4173..17854f948b 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h @@ -42,16 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SYSCTRL_H #define AM_HAL_SYSCTRL_H -#ifdef __cplusplus -extern "C" -{ -#endif //***************************************************************************** // @@ -86,6 +82,10 @@ extern "C" // #define AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT 0x01000000 // No timer, apply a constant value +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c index 3654910495..b09ee47c83 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h index bd5e576938..8ecdf7fec2 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SYSTICK_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c index 722f22fa13..151b0ce21d 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -350,7 +350,7 @@ am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) // // Wait for 50us for the data to flush out. // - am_hal_itm_delay_us(50); + am_hal_flash_delay(FLASH_CYCLES_US(50)); } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h index 9739034a18..6ef6b1f542 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_TPIU_H @@ -50,11 +50,6 @@ #include -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // TPIU bit rate defines. @@ -165,6 +160,11 @@ typedef struct } am_hal_tpiu_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c index 77bde67b87..22de5e782b 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c @@ -39,7 +39,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #include "am_mcu_apollo.h" diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h index b254c957a7..8879e98c83 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h @@ -39,7 +39,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_TTP_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c index 1a7e5aca31..4582cbb4e9 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h index 4aab828582..b6209d112e 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_UART_H #define AM_HAL_UART_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name UART Interrupts @@ -270,6 +265,11 @@ am_hal_uart_pwrsave_t; //***************************************************************************** extern am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES]; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c index 31e28855e4..37539c1d04 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h index a6ca991aae..cd0d81ad53 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_VCOMP_H #define AM_HAL_VCOMP_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name Positive Input Selection @@ -145,6 +140,11 @@ typedef struct } am_hal_vcomp_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c index 4e80113fd1..9676f973ac 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h index 63766fa458..b719158b8a 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_WDT_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h b/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h index 54d2d8620f..90d3531f0f 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_ADC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h b/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h index 13a850d1c4..0a223b4a67 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h @@ -37,7 +37,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_BASE_ADDRESSES_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h index b933a08874..ac7e9d22d2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_CACHECTRL_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h b/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h index c769673d65..d9dae13622 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_CLKGEN_H @@ -66,7 +66,6 @@ #define AM_REG_CLKGEN_CCTRL_O 0x00000018 #define AM_REG_CLKGEN_STATUS_O 0x0000001C #define AM_REG_CLKGEN_HFADJ_O 0x00000020 -#define AM_REG_CLKGEN_HFVAL_O 0x00000024 #define AM_REG_CLKGEN_CLOCKEN_O 0x00000028 #define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C #define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030 @@ -390,16 +389,6 @@ #define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000 #define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001 -//***************************************************************************** -// -// CLKGEN_HFVAL - HFADJ readback -// -//***************************************************************************** -// Current HFTUNE value -#define AM_REG_CLKGEN_HFVAL_HFTUNERB_S 0 -#define AM_REG_CLKGEN_HFVAL_HFTUNERB_M 0x000007FF -#define AM_REG_CLKGEN_HFVAL_HFTUNERB(n) (((uint32_t)(n) << 0) & 0x000007FF) - //***************************************************************************** // // CLKGEN_CLOCKEN - Clock Enable Status diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h b/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h index 278849a74d..7bc30aa3f2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_CTIMER_H @@ -51,7 +51,7 @@ //***************************************************************************** #define AM_REG_CTIMER_NUM_MODULES 1 #define AM_REG_CTIMERn(n) \ - (REG_CTIMER_BASEADDR + 0x00000000 * n) + (REG_CTIMER_BASEADDR + 0x00000010 * n) //***************************************************************************** // diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h index 0b103ea6fb..53cc2fb6d1 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_FLASHCTRL_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h b/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h index 4690cd6111..1e3d424151 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_GPIO_H @@ -1348,7 +1348,7 @@ #define AM_REG_GPIO_PADREGB_PAD7FNCSEL_SLWIR3LB 0x30000000 #define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M1nCE1 0x38000000 -// Pad 7 drive strentgh +// Pad 7 drive strength #define AM_REG_GPIO_PADREGB_PAD7STRNG_S 26 #define AM_REG_GPIO_PADREGB_PAD7STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGB_PAD7STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1514,7 +1514,7 @@ #define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UART0RX 0x30000000 #define AM_REG_GPIO_PADREGC_PAD11FNCSEL_PDM_DATA 0x38000000 -// Pad 11 drive strentgh +// Pad 11 drive strength #define AM_REG_GPIO_PADREGC_PAD11STRNG_S 26 #define AM_REG_GPIO_PADREGC_PAD11STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGC_PAD11STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1673,7 +1673,7 @@ #define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWDIO 0x30000000 #define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWO 0x38000000 -// Pad 15 drive strentgh +// Pad 15 drive strength #define AM_REG_GPIO_PADREGD_PAD15STRNG_S 26 #define AM_REG_GPIO_PADREGD_PAD15STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGD_PAD15STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1814,7 +1814,7 @@ #define AM_REG_GPIO_PADREGE_PAD19FNCSEL_UART1RX 0x30000000 #define AM_REG_GPIO_PADREGE_PAD19FNCSEL_I2S_BCLK 0x38000000 -// Pad 19 drive strentgh +// Pad 19 drive strength #define AM_REG_GPIO_PADREGE_PAD19STRNG_S 26 #define AM_REG_GPIO_PADREGE_PAD19STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGE_PAD19STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1955,7 +1955,7 @@ #define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB1 0x30000000 #define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UNDEF7 0x38000000 -// Pad 23 drive strentgh +// Pad 23 drive strength #define AM_REG_GPIO_PADREGF_PAD23STRNG_S 26 #define AM_REG_GPIO_PADREGF_PAD23STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGF_PAD23STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2112,7 +2112,7 @@ #define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCKLB 0x30000000 #define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCLLB 0x38000000 -// Pad 27 drive strentgh +// Pad 27 drive strength #define AM_REG_GPIO_PADREGG_PAD27STRNG_S 26 #define AM_REG_GPIO_PADREGG_PAD27STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGG_PAD27STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2262,7 +2262,7 @@ #define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF6 0x30000000 #define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF7 0x38000000 -// Pad 31 drive strentgh +// Pad 31 drive strength #define AM_REG_GPIO_PADREGH_PAD31STRNG_S 26 #define AM_REG_GPIO_PADREGH_PAD31STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGH_PAD31STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2403,7 +2403,7 @@ #define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UA0RTS 0x30000000 #define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M3nCE2 0x38000000 -// Pad 35 drive strentgh +// Pad 35 drive strength #define AM_REG_GPIO_PADREGI_PAD35STRNG_S 26 #define AM_REG_GPIO_PADREGI_PAD35STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGI_PAD35STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2553,7 +2553,7 @@ #define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCKLB 0x30000000 #define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCLLB 0x38000000 -// Pad 39 drive strentgh +// Pad 39 drive strength #define AM_REG_GPIO_PADREGJ_PAD39STRNG_S 26 #define AM_REG_GPIO_PADREGJ_PAD39STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGJ_PAD39STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2703,7 +2703,7 @@ #define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLMISOLB 0x30000000 #define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLSDALB 0x38000000 -// Pad 43 drive strentgh +// Pad 43 drive strength #define AM_REG_GPIO_PADREGK_PAD43STRNG_S 26 #define AM_REG_GPIO_PADREGK_PAD43STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGK_PAD43STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2869,7 +2869,7 @@ #define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M4nCE5 0x30000000 #define AM_REG_GPIO_PADREGL_PAD47FNCSEL_SLWIR3LB 0x38000000 -// Pad 47 drive strentgh +// Pad 47 drive strength #define AM_REG_GPIO_PADREGL_PAD47STRNG_S 26 #define AM_REG_GPIO_PADREGL_PAD47STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGL_PAD47STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h b/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h index c04cd2c04a..b33ed9b666 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_IOMSTR_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h b/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h index 4a1c96ae3c..6e9f47b002 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_IOSLAVE_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h index c007aa629a..91554948b7 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_ITM_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h b/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h index 61560dc099..7f883a8333 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_JEDEC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h b/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h index e9662958c1..5378f1a858 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h @@ -1,6 +1,7 @@ //***************************************************************************** // -//! @file am_reg_macros.h +// am_reg_macros.h +//! @file //! //! @brief Helper macros for using hardware registers. // @@ -37,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -106,10 +107,15 @@ extern "C" // Register access macros for single-instance modules // AM_REG - Write a register of a module. // AM_BFW - Write a value to a bitfield of a register. -// AM_BFWe - Use a defined enum value to write a value to a bitfield. +// AM_BFWe - Use a defined enum value to write a value to a register bitfield. // AM_BFR - Read a bitfield value from a register. -// AM_BFM - Read and mask a bitfield, but leave the value in its bit position. -// (Useful for comparing with enums.) +// AM_BFM - Read and mask a bitfield from a register, but leave the value in +// its bit position. Useful for comparing with enums. +// +// AM_BFV - Move a value to a bitfield. This macro is used for creating a +// value, it does not modify any register. +// AM_BFX - Extract the value of a bitfield from a 32-bit value, such as that +// read from a register. Does not read or modify any register. // //***************************************************************************** #define AM_REG(module, reg) \ @@ -139,16 +145,19 @@ extern "C" //***************************************************************************** // // Register access macros for multi-instance modules +// AM_REGADDRn - Calc the register address inside a multiple instance module. // AM_REGn - Write a register of a multiple instance module. // AM_BFWn - Write a value to a bitfield of a register in a multiple instance. // AM_BFWen - Use a defined enum value to write a value to a bitfield of a // register in a multiple instance. // AM_BFRn - Read a bitfield value from a register in a multiple instance. -// AM_BFMn - Read a bitfield, but leave the value in its bitfield position. // AM_BFMn - Read and mask a bitfield, but leave the value in its bit position. // (Useful for comparing with enums.) // //***************************************************************************** +#define AM_REGADDRn(module, instance, reg) \ + (AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O) + #define AM_REGn(module, instance, reg) \ AM_REGVAL(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O) @@ -187,9 +196,9 @@ extern "C" // no operator to simply write the value atomically. // AM_REGa_SET - Set bits in a single instance module according to the mask. // AM_REGa_CLR - Clear bits in a single instance module according to the mask. -// AM_REGna - Multiple module version of AM_REGa. -// AM_REGna_SET - Multiple instance version of AM_REGa_SET. -// AM_REGna_CLR - Multiple instance version of AM_REGa_CLR. +// AM_REGan - Multiple module version of AM_REGa. +// AM_REGan_SET - Multiple instance version of AM_REGa_SET. +// AM_REGan_CLR - Multiple instance version of AM_REGa_CLR. // AM_BFWa - Write a value to a register bitfield. // AM_BFWae - Use a defined enum value to write a value to a bitfield. // AM_BFWan - Write a value to a bitfield of a register in a multiple instance. diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h index f02624d8e3..854019d911 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h index ae066bf85d..b4b1e54428 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_MCUCTRL_H @@ -143,6 +143,7 @@ #define AM_REG_MCUCTRL_CHIPREV_REVMIN_M 0x0000000F #define AM_REG_MCUCTRL_CHIPREV_REVMIN(n) (((uint32_t)(n) << 0) & 0x0000000F) #define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 0x00000000 +#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2 0x00000002 //***************************************************************************** // diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h b/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h index 349991e28f..c2657660f2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_NVIC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h index 6a7c6aa3cf..042dfd2ce3 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_PDM_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h index cac7cab36c..b4929ff39a 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_PWRCTRL_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h b/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h index 1e76519744..0554bdd465 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_RSTGEN_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h b/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h index 9da5bc816c..b830445c22 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_RTC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h index 4a00cc21d5..b82cd0dd70 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_SYSCTRL_H @@ -58,6 +58,8 @@ // Register offsets. // //***************************************************************************** +#define AM_REG_SYSCTRL_ICTR_O 0xE000E004 +#define AM_REG_SYSCTRL_ACTLR_O 0xE000E008 #define AM_REG_SYSCTRL_ICSR_O 0xE000ED04 #define AM_REG_SYSCTRL_VTOR_O 0xE000ED08 #define AM_REG_SYSCTRL_AIRCR_O 0xE000ED0C @@ -78,6 +80,47 @@ #define AM_REG_SYSCTRL_FPCAR_O 0xE000EF38 #define AM_REG_SYSCTRL_FPDSCR_O 0xE000EF3C +//***************************************************************************** +// +// SYSCTRL_ICTR - Interrupt Controller Type Register (NVIC) +// +//***************************************************************************** +// Total number of interrupt lines in groups of 32. +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_S 0 +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_M 0x0000000F +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// SYSCTRL_ACTLR - Auxilliary Control Register +// +//***************************************************************************** +// Disables lazy stacking of floating point context. +#define AM_REG_SYSCTRL_ACTLR_DISFPCA_S 9 +#define AM_REG_SYSCTRL_ACTLR_DISFPCA_M 0x00000200 +#define AM_REG_SYSCTRL_ACTLR_DISFPCA(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Disables floating point instructions completing out of order with respect to +// integer instructions. +#define AM_REG_SYSCTRL_ACTLR_DISOOFP_S 8 +#define AM_REG_SYSCTRL_ACTLR_DISOOFP_M 0x00000100 +#define AM_REG_SYSCTRL_ACTLR_DISOOFP(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Disables folding of IT instructions. +#define AM_REG_SYSCTRL_ACTLR_DISFOLD_S 2 +#define AM_REG_SYSCTRL_ACTLR_DISFOLD_M 0x00000004 +#define AM_REG_SYSCTRL_ACTLR_DISFOLD(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Disables write buffer use during default memory map accesses. +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_S 1 +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_M 0x00000002 +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Disables interruption of multi-cycle instructions. +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_S 0 +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_M 0x00000001 +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT(n) (((uint32_t)(n) << 0) & 0x00000001) + //***************************************************************************** // // SYSCTRL_ICSR - Interrupt Control and State Register diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h b/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h index d68a8c4063..0d427dabe2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_SYSTICK_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h b/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h index e3719b60f8..f1822a74d5 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_TPIU_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h b/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h index 493a947630..eabf749939 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_UART_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h b/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h index 93c610e123..2df6cc8479 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_VCOMP_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h b/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h index f95ddc1e8d..96fefd898f 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_WDT_H diff --git a/bsp/apollo2/libraries/startup/SConscript b/bsp/apollo2/libraries/startup/SConscript index e4758f1e2e..865befb6e9 100644 --- a/bsp/apollo2/libraries/startup/SConscript +++ b/bsp/apollo2/libraries/startup/SConscript @@ -11,15 +11,16 @@ src = Split(""" # add for startup script if rtconfig.CROSS_TOOL == 'gcc': - src = src + ['gcc_ride7/' + 'startup_gcc.c'] + src = src + ['gcc/' + 'startup_gcc.c'] elif rtconfig.CROSS_TOOL == 'keil': src = src + ['arm/' + 'startup_keil.s'] elif rtconfig.CROSS_TOOL == 'iar': src = src + ['iar/' + 'startup_iar.c'] path = [cwd] +path += [cwd + '/cmsis/include'] -CPPDEFINES = ['AM_PACKAGE_BGA', 'AM_PART_APOLLO2', 'keil'] +CPPDEFINES = ['AM_PACKAGE_BGA', 'AM_PART_APOLLO2'] group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) diff --git a/bsp/apollo2/project.uvoptx b/bsp/apollo2/project.uvoptx index a546ada74f..5578f1480e 100644 --- a/bsp/apollo2/project.uvoptx +++ b/bsp/apollo2/project.uvoptx @@ -161,4 +161,1228 @@ + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Board + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + board\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + board\flash.c + flash.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + board\gpio.c + gpio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + board\i2c.c + i2c.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + board\led.c + led.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + board\pdm.c + pdm.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + board\pwm.c + pwm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + board\rtc.c + rtc.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + board\smbus.c + smbus.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + board\spi.c + spi.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + board\uart.c + uart.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_clkgen.c + am_hal_clkgen.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_debug.c + am_hal_debug.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_cachectrl.c + am_hal_cachectrl.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_pwrctrl.c + am_hal_pwrctrl.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_mcuctrl.c + am_hal_mcuctrl.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_sysctrl.c + am_hal_sysctrl.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_reset.c + am_hal_reset.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_stimer.c + am_hal_stimer.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_ctimer.c + am_hal_ctimer.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_rtc.c + am_hal_rtc.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_interrupt.c + am_hal_interrupt.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_queue.c + am_hal_queue.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_iom.c + am_hal_iom.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_ios.c + am_hal_ios.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_vcomp.c + am_hal_vcomp.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_flash.c + am_hal_flash.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_gpio.c + am_hal_gpio.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_uart.c + am_hal_uart.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_adc.c + am_hal_adc.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_pdm.c + am_hal_pdm.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_i2c_bit_bang.c + am_hal_i2c_bit_bang.c + 0 + 0 + + + 3 + 35 + 2 + 0 + 0 + 0 + libraries\startup\arm\startup_keil.s + startup_keil.s + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 4 + 36 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 4 + 37 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + + + 4 + 38 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + 4 + 39 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 4 + 40 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 4 + 41 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 4 + 42 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 4 + 43 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 4 + 44 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + 4 + 45 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 4 + 46 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 4 + 47 + 1 + 0 + 0 + 0 + ..\..\src\signal.c + signal.c + 0 + 0 + + + 4 + 48 + 1 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + 0 + 0 + + + 4 + 49 + 1 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + 0 + 0 + + + + + CORTEX-M4 + 0 + 0 + 0 + 0 + + 5 + 50 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + 5 + 51 + 2 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 5 + 52 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 5 + 53 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 5 + 54 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 6 + 55 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\dfs.c + dfs.c + 0 + 0 + + + 6 + 56 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\dfs_file.c + dfs_file.c + 0 + 0 + + + 6 + 57 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 6 + 58 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + 6 + 59 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\poll.c + poll.c + 0 + 0 + + + 6 + 60 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\select.c + select.c + 0 + 0 + + + 6 + 61 + 1 + 0 + 0 + 0 + ..\..\components\dfs\filesystems\devfs\devfs.c + devfs.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\components\drivers\rtc\rtc.c + rtc_rtc.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 7 + 74 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 7 + 75 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 8 + 76 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\..\components\finsh\symbol.c + symbol.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh_cmd.c + msh_cmd.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_init.c + finsh_init.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 8 + 91 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 9 + 92 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 9 + 93 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 9 + 94 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stdio.c + stdio.c + 0 + 0 + + + 9 + 95 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stubs.c + stubs.c + 0 + 0 + + + 9 + 96 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\time.c + time.c + 0 + 0 + + + diff --git a/bsp/apollo2/project.uvprojx b/bsp/apollo2/project.uvprojx index 13c1c51fe6..4346b8d5e4 100644 --- a/bsp/apollo2/project.uvprojx +++ b/bsp/apollo2/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rtthread-apollo2 @@ -15,28 +18,28 @@ AmbiqMicro.Apollo_DFP.1.0.0 http://s3.asia.ambiqmicro.com/pack/ IROM(0x00000000,0x100000) IRAM(0x10000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD10000000 -FC4000 -FN1 -FF0Apollo2 -FS00 -FL010000 -FP0($$Device:AMAPH1KK-KBR$Flash\Apollo2.FLM)) 0 $$Device:AMAPH1KK-KBR$Device\Include\apollo2.h - - - - - - - - - + + + + + + + + + $$Device:AMAPH1KK-KBR$SVD\apollo2.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +61,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +71,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +82,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -100,8 +103,8 @@ 0 0 3 - - + + 1 @@ -149,18 +152,18 @@ 0 6 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -176,10 +179,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -212,7 +215,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -344,7 +347,7 @@ 0x0 - + 1 @@ -367,10 +370,10 @@ 1 1 - - AM_PART_APOLLO2, RT_USING_ARM_LIBC, AM_PACKAGE_BGA, keil - - board;libraries/drivers;libraries/startup;applications;.;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/spi;../../components/drivers/include;../../components/drivers/include;../../components/libc/compilers/armlibc;../../components/finsh;../../components/dfs/include;../../components/dfs/filesystems/devfs + + AM_PART_APOLLO2, RT_USING_ARM_LIBC, AM_PACKAGE_BGA + + applications;.;board;libraries\drivers;libraries\startup;libraries\startup\cmsis\include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc @@ -384,10 +387,10 @@ 0 0 - - - - + + + + @@ -399,101 +402,89 @@ 0 0x00000000 0x20000000 - + .\build\rtthread.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + + + Applications + + + main.c + 1 + applications\main.c + + + Board adc.c 1 - board/adc.c + board\adc.c - - board.c 1 - board/board.c + board\board.c - - flash.c 1 - board/flash.c + board\flash.c - - gpio.c 1 - board/gpio.c + board\gpio.c - - i2c.c 1 - board/i2c.c + board\i2c.c - - led.c 1 - board/led.c + board\led.c - - pdm.c 1 - board/pdm.c + board\pdm.c - - pwm.c 1 - board/pwm.c + board\pwm.c - - rtc.c 1 - board/rtc.c + board\rtc.c - - smbus.c 1 - board/smbus.c + board\smbus.c - - spi.c 1 - board/spi.c + board\spi.c - - uart.c 1 - board/uart.c + board\uart.c @@ -503,157 +494,112 @@ am_hal_clkgen.c 1 - libraries/drivers/hal/am_hal_clkgen.c + libraries\drivers\hal\am_hal_clkgen.c - - am_hal_debug.c 1 - libraries/drivers/hal/am_hal_debug.c + libraries\drivers\hal\am_hal_debug.c - - am_hal_cachectrl.c 1 - libraries/drivers/hal/am_hal_cachectrl.c + libraries\drivers\hal\am_hal_cachectrl.c - - am_hal_pwrctrl.c 1 - libraries/drivers/hal/am_hal_pwrctrl.c + libraries\drivers\hal\am_hal_pwrctrl.c + + + am_hal_mcuctrl.c + 1 + libraries\drivers\hal\am_hal_mcuctrl.c - - am_hal_sysctrl.c 1 - libraries/drivers/hal/am_hal_sysctrl.c + libraries\drivers\hal\am_hal_sysctrl.c - - am_hal_reset.c 1 - libraries/drivers/hal/am_hal_reset.c + libraries\drivers\hal\am_hal_reset.c - - am_hal_stimer.c 1 - libraries/drivers/hal/am_hal_stimer.c + libraries\drivers\hal\am_hal_stimer.c - - am_hal_ctimer.c 1 - libraries/drivers/hal/am_hal_ctimer.c + libraries\drivers\hal\am_hal_ctimer.c - - am_hal_rtc.c 1 - libraries/drivers/hal/am_hal_rtc.c + libraries\drivers\hal\am_hal_rtc.c - - am_hal_interrupt.c 1 - libraries/drivers/hal/am_hal_interrupt.c + libraries\drivers\hal\am_hal_interrupt.c - - am_hal_queue.c 1 - libraries/drivers/hal/am_hal_queue.c + libraries\drivers\hal\am_hal_queue.c - - am_hal_iom.c 1 - libraries/drivers/hal/am_hal_iom.c + libraries\drivers\hal\am_hal_iom.c - - am_hal_ios.c 1 - libraries/drivers/hal/am_hal_ios.c + libraries\drivers\hal\am_hal_ios.c - - am_hal_vcomp.c 1 - libraries/drivers/hal/am_hal_vcomp.c + libraries\drivers\hal\am_hal_vcomp.c - - am_hal_flash.c 1 - libraries/drivers/hal/am_hal_flash.c + libraries\drivers\hal\am_hal_flash.c - - am_hal_gpio.c 1 - libraries/drivers/hal/am_hal_gpio.c + libraries\drivers\hal\am_hal_gpio.c - - am_hal_uart.c 1 - libraries/drivers/hal/am_hal_uart.c + libraries\drivers\hal\am_hal_uart.c - - am_hal_adc.c 1 - libraries/drivers/hal/am_hal_adc.c + libraries\drivers\hal\am_hal_adc.c - - am_hal_pdm.c 1 - libraries/drivers/hal/am_hal_pdm.c + libraries\drivers\hal\am_hal_pdm.c - - am_hal_i2c_bit_bang.c 1 - libraries/drivers/hal/am_hal_i2c_bit_bang.c + libraries\drivers\hal\am_hal_i2c_bit_bang.c - - startup_keil.s 2 - libraries/startup/arm/startup_keil.s - - - - - Applications - - - main.c - 1 - applications/main.c + libraries\startup\arm\startup_keil.s @@ -663,98 +609,72 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c - - components.c 1 - ../../src/components.c + ..\..\src\components.c - - device.c 1 - ../../src/device.c + ..\..\src\device.c - - idle.c 1 - ../../src/idle.c + ..\..\src\idle.c - - ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c - - irq.c 1 - ../../src/irq.c + ..\..\src\irq.c - - kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c - - mem.c 1 - ../../src/mem.c + ..\..\src\mem.c - - mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c - - object.c 1 - ../../src/object.c + ..\..\src\object.c - - scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c - - signal.c 1 - ../../src/signal.c + ..\..\src\signal.c - - thread.c 1 - ../../src/thread.c + ..\..\src\thread.c - - timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -764,301 +684,27 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m4/cpuport.c + ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 - ../../libcpu/arm/cortex-m4/context_rvds.S + ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c - - showmem.c 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - pin.c - 1 - ../../components/drivers/misc/pin.c - - - - - i2c_core.c - 1 - ../../components/drivers/i2c/i2c_core.c - - - - - i2c_dev.c - 1 - ../../components/drivers/i2c/i2c_dev.c - - - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - - - rtc_rtc.c - 1 - ../../components/drivers/rtc/rtc.c - - - - - spi_core.c - 1 - ../../components/drivers/spi/spi_core.c - - - - - spi_dev.c - 1 - ../../components/drivers/spi/spi_dev.c - - - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - - - - - - - - - - - - - libc - - - libc.c - 1 - ../../components/libc/compilers/armlibc/libc.c - - - - - libc_syms.c - 1 - ../../components/libc/compilers/armlibc/libc_syms.c - - - - - mem_std.c - 1 - ../../components/libc/compilers/armlibc/mem_std.c - - - - - stdio.c - 1 - ../../components/libc/compilers/armlibc/stdio.c - - - - - stubs.c - 1 - ../../components/libc/compilers/armlibc/stubs.c - - - - - time.c - 1 - ../../components/libc/compilers/armlibc/time.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - - - msh.c - 1 - ../../components/finsh/msh.c - - - - - msh_cmd.c - 1 - ../../components/finsh/msh_cmd.c - - - - - msh_file.c - 1 - ../../components/finsh/msh_file.c - - - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c + ..\..\libcpu\arm\common\showmem.c @@ -1068,53 +714,296 @@ dfs.c 1 - ../../components/dfs/src/dfs.c + ..\..\components\dfs\src\dfs.c - - dfs_file.c 1 - ../../components/dfs/src/dfs_file.c + ..\..\components\dfs\src\dfs_file.c - - dfs_fs.c 1 - ../../components/dfs/src/dfs_fs.c + ..\..\components\dfs\src\dfs_fs.c - - dfs_posix.c 1 - ../../components/dfs/src/dfs_posix.c + ..\..\components\dfs\src\dfs_posix.c - - poll.c 1 - ../../components/dfs/src/poll.c + ..\..\components\dfs\src\poll.c - - select.c 1 - ../../components/dfs/src/select.c + ..\..\components\dfs\src\select.c - - devfs.c 1 - ../../components/dfs/filesystems/devfs/devfs.c + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 0 + 0 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + rtc_rtc.c + 1 + ..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c + diff --git a/bsp/apollo2/rtconfig.py b/bsp/apollo2/rtconfig.py index 90adde5435..506ee78eca 100644 --- a/bsp/apollo2/rtconfig.py +++ b/bsp/apollo2/rtconfig.py @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' CFLAGS = DEVICE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-apollo2.map,-cref,-u,Reset_Handler -T' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-apollo2.map,-cref,-u,am_reset_isr -T rtthread_link.ld' CPATH = '' LPATH = '' diff --git a/bsp/apollo2/rtthread.sct b/bsp/apollo2/rtthread.sct new file mode 100644 index 0000000000..507ebdca1a --- /dev/null +++ b/bsp/apollo2/rtthread.sct @@ -0,0 +1,14 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00006000 0x000FFFFF { ; load region size_region + ER_IROM1 0x00006000 0x000FFFFF { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10000000 0x00040000 { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/bsp/apollo2/rtthread_link.ld b/bsp/apollo2/rtthread_link.ld new file mode 100644 index 0000000000..9be7326368 --- /dev/null +++ b/bsp/apollo2/rtthread_link.ld @@ -0,0 +1,142 @@ +/* + * linker script for STM32F10x with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 1024k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x10000000, LENGTH = 256k /* 128K sram */ +} +ENTRY(am_reset_isr) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _init_data = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_init_data) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/at91sam9260/rtconfig.h b/bsp/at91sam9260/rtconfig.h index 53ca53359d..62ceba4914 100755 --- a/bsp/at91sam9260/rtconfig.h +++ b/bsp/at91sam9260/rtconfig.h @@ -69,7 +69,6 @@ /* Using Module System */ #define RT_USING_MODULE -#define RT_USING_LIBDL /* SECTION: Device System */ /* Using Device System */ @@ -147,7 +146,7 @@ #define RT_LWIP_DNS /* Trace LwIP protocol */ -// #define RT_LWIP_DEBUG +// #define RT_LWIP_DEBUG /* Enable ICMP protocol */ #define RT_LWIP_ICMP @@ -239,11 +238,11 @@ /* * Note on FTK: - * + * * FTK depends : * #define RT_USING_NEWLIB * #define DFS_USING_WORKDIR - * + * * And the maximal length must great than 64 * #define RT_DFS_ELM_MAX_LFN 128 */ diff --git a/bsp/at91sam9260/rtconfig.py b/bsp/at91sam9260/rtconfig.py index 2ebf071443..3aefb30fad 100755 --- a/bsp/at91sam9260/rtconfig.py +++ b/bsp/at91sam9260/rtconfig.py @@ -1,8 +1,8 @@ import os -ARCH = 'arm' -CPU = 'arm926' +ARCH = 'arm' +CPU = 'arm926' # toolchains options -CROSS_TOOL = 'gcc' +CROSS_TOOL = 'gcc' #------- toolchains path ------------------------------------------------------- if os.getenv('RTT_CC'): @@ -11,12 +11,6 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' EXEC_PATH = r'D:\arm-2013.11\bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -61,77 +55,3 @@ if PLATFORM == 'gcc': POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' POST_ACTION += SIZE + ' $TARGET\n' -#------- Keil settings --------------------------------------------------------- -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - EXEC_PATH += '/arm/armcc/bin/' - - DEVICE = ' --cpu=' + CORE - CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870' - AFLAGS = DEVICE + ' -Iplatform' - LFLAGS = DEVICE + ' --strict' - LFLAGS += ' --info sizes --info totals --info unused --info veneers' - LFLAGS += ' --list ' + MAP_FILE - LFLAGS += ' --scatter ' + LINK_FILE + '.scat' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n' - POST_ACTION += 'fromelf -z $TARGET\n' -#------- IAR settings ---------------------------------------------------------- -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = CORE - - CFLAGS = '--cpu=' + DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - - CFLAGS += ' --endian=little' - CFLAGS += ' -e' - CFLAGS += ' --fpu=none' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = '--cpu '+ DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --fpu none' - AFLAGS += ' -S' - AFLAGS += ' -Iplatform' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = '--config ' + LINK_FILE +'.icf' - LFLAGS += ' --entry __iar_program_start' - LFLAGS += ' --map ' + MAP_FILE - LFLAGS += ' --silent' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --silent --bin $TARGET ' + TARGET_NAME diff --git a/bsp/beaglebone/.config b/bsp/beaglebone/.config new file mode 100644 index 0000000000..0ff69f1164 --- /dev/null +++ b/bsp/beaglebone/.config @@ -0,0 +1,293 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_RT_USING_UART1=y diff --git a/bsp/beaglebone/Kconfig b/bsp/beaglebone/Kconfig new file mode 100644 index 0000000000..a3d9b2e519 --- /dev/null +++ b/bsp/beaglebone/Kconfig @@ -0,0 +1,32 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example: default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config $ENV_DIR + string + option env="ENV_ROOT" + default "/" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config RT_USING_UART1 + bool "Using RT_USING_UART1" + default y + diff --git a/bsp/beaglebone/SConstruct b/bsp/beaglebone/SConstruct index b7c9ef221e..6b19269c47 100644 --- a/bsp/beaglebone/SConstruct +++ b/bsp/beaglebone/SConstruct @@ -15,6 +15,7 @@ TARGET = 'rtthread-beaglebone.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/beaglebone/am335x_sk.ewp b/bsp/beaglebone/am335x_sk.ewp index c71c566b05..a898b36242 100644 --- a/bsp/beaglebone/am335x_sk.ewp +++ b/bsp/beaglebone/am335x_sk.ewp @@ -1099,9 +1099,6 @@ $PROJ_DIR$\..\..\src\mempool.c - - $PROJ_DIR$\..\..\src\module.c - $PROJ_DIR$\..\..\src\object.c diff --git a/bsp/beaglebone/applications/main.c b/bsp/beaglebone/applications/main.c new file mode 100644 index 0000000000..c9a2b6ca05 --- /dev/null +++ b/bsp/beaglebone/applications/main.c @@ -0,0 +1,10 @@ +#include +#include +#include + +int main(void) +{ + printf("hello rt-thread\n"); + return 0; +} + diff --git a/bsp/beaglebone/applications/startup.c b/bsp/beaglebone/applications/startup.c deleted file mode 100644 index c079240b63..0000000000 --- a/bsp/beaglebone/applications/startup.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2012-12-05 Bernard the first version - * 2015-11-11 zchong support iar compiler - */ - -#include -#include - -#include - -extern int rt_application_init(void); -#ifdef __ICCARM__ -#pragma section="HEAP" -#endif -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* initialzie hardware interrupt */ - rt_hw_interrupt_init(); - - /* initialize board */ - rt_hw_board_init(); - /* show RT-Thread version */ - rt_show_version(); - - /* initialize memory system */ -#ifdef RT_USING_HEAP -#ifdef __ICCARM__ -rt_system_heap_init(__segment_end("HEAP"), (void*)0x8FFFFFFF); -#else - rt_system_heap_init(HEAP_BEGIN, HEAP_END); -#endif -#endif - - /* initialize scheduler system */ - rt_system_scheduler_init(); - - /* initialize timer */ - rt_system_timer_init(); - - /* initialize soft timer thread */ - rt_system_timer_thread_init(); - - /* initialize application */ - rt_application_init(); - - /* initialize idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* invoke rtthread_startup */ - rtthread_startup(); - - return 0; -} diff --git a/bsp/beaglebone/rtconfig.h b/bsp/beaglebone/rtconfig.h index bdb79ef054..5bc7ab92db 100644 --- a/bsp/beaglebone/rtconfig.h +++ b/bsp/beaglebone/rtconfig.h @@ -1,167 +1,153 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -//
-//#define RT_USING_GDB -//#define RT_GDB_DEBUG -#define RT_GDB_ICACHE -//
+/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -// +/* RT-Thread Kernel */ -// -#define RT_NAME_MAX 6 -// -#define RT_ALIGN_SIZE 4 -// -// 8 -// 32 -// 256 -// -#define RT_THREAD_PRIORITY_MAX 32 -// -#define RT_TICK_PER_SECOND 1000 -// -#define IDLE_THREAD_STACK_SIZE 512 -//
-#define RT_DEBUG -//#define RT_DEBUG_SCHEDULER 1 -// -// #define RT_THREAD_DEBUG -// -//#define RT_USING_OVERFLOW_CHECK -//
- -// +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK -//
-// #define RT_USING_TIMER_SOFT -// -#define RT_TIMER_THREAD_PRIO 4 -// -#define RT_TIMER_THREAD_STACK_SIZE 512 -// -#define RT_TIMER_TICK_PER_SECOND 10 -//
+#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ -//
-// #define RT_USING_SEMAPHORE -// #define RT_USING_MUTEX -// #define RT_USING_EVENT -// #define RT_USING_MAILBOX -// #define RT_USING_MESSAGEQUEUE -//
-//
-// +/* Memory Management */ + #define RT_USING_MEMPOOL -// -// #define RT_USING_MEMHEAP -// -#define RT_USING_HEAP -// -// #define RT_USING_MEMHEAP_AS_HEAP -// #define RT_USING_SMALL_MEM -// -// #define RT_USING_SLAB -//
+#define RT_USING_HEAP + +/* Kernel Device Object */ -//
#define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL -// -#define RT_USING_UART0 -// -#define RT_USING_UART1 -// -#define RT_USING_UART2 -// -//#define RT_USING_UART3 -// -#define RT_USING_UART4 -// -#define RT_USING_UART5 -// -#define RT_USING_PIN -// -#define RT_UART_RX_BUFFER_SIZE 64 -// -#define RT_USING_INTERRUPT_INFO -//
- -//
#define RT_USING_CONSOLE -// -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart0" -//
+#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" + +/* RT-Thread Components */ -// #define RT_USING_COMPONENTS_INIT -//
+#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + #define RT_USING_FINSH -// -#define FINSH_USING_MSH -// -//#define FINSH_USING_MSH_DEFAULT -// +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -// #define FINSH_USING_DESCRIPTION -// -#define FINSH_THREAD_STACK_SIZE 4096 -//
+#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ -//
-// #define RT_USING_LIBC -// -//#define RT_USING_PTHREADS -//
-//
-// #define RT_USING_DFS -// -// #define DFS_USING_WORKDIR -// -#define DFS_FILESYSTEMS_MAX 2 -// -#define DFS_FD_MAX 4 -// -#define RT_USING_DFS_ELMFAT -// -// 1 -// 2 -// -#define RT_DFS_ELM_USE_LFN 1 -// -#define RT_DFS_ELM_MAX_LFN 64 -// -// #define RT_USING_DFS_YAFFS2 -// -// #define RT_USING_DFS_UFFS -// -// #define RT_USING_DFS_DEVFS -// -// #define RT_USING_DFS_NFS -// -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" -//
+/* Network */ -// +/* Socket abstraction layer */ -#define __rt_ffs __builtin_ffs + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + + +/* example package: hello */ + +#define RT_USING_UART1 #endif - diff --git a/bsp/bf533/rtconfig.h b/bsp/bf533/rtconfig.h index 10b5202811..788fa32299 100644 --- a/bsp/bf533/rtconfig.h +++ b/bsp/bf533/rtconfig.h @@ -68,7 +68,6 @@ /* Using Module System */ //#define RT_USING_MODULE -#define RT_USING_LIBDL /* SECTION: Console options */ #define RT_USING_CONSOLE @@ -231,11 +230,11 @@ /* * Note on FTK: - * + * * FTK depends : * #define RT_USING_NEWLIB * #define DFS_USING_WORKDIR - * + * * And the maximal length must great than 64 * #define RT_DFS_ELM_MAX_LFN 128 */ diff --git a/bsp/bf533/vdsp/bf533.dpj b/bsp/bf533/vdsp/bf533.dpj index 621aa26ddb..f8b61a5d78 100644 --- a/bsp/bf533/vdsp/bf533.dpj +++ b/bsp/bf533/vdsp/bf533.dpj @@ -453,24 +453,6 @@ - - - - - - .\Debug - .\Debug - - - - - .\Release - .\Release - - - - - diff --git a/bsp/bf533/vdsp/bf533.mak b/bsp/bf533/vdsp/bf533.mak index eeeefbf2ec..fbefd9858e 100644 --- a/bsp/bf533/vdsp/bf533.mak +++ b/bsp/bf533/vdsp/bf533.mak @@ -138,10 +138,6 @@ bf533_Debug : ./Debug/bf533.ldr @echo "..\..\..\src\mempool.c" $(VDSP)/ccblkfn.exe -c ..\..\..\src\mempool.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\mempool.doj -MM -./Debug/module.doj :../../../src/module.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rtm.h $(VDSP)/Blackfin/include/string.h - @echo "..\..\..\src\module.c" - $(VDSP)/ccblkfn.exe -c ..\..\..\src\module.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\module.doj -MM - ./Debug/object.doj :../../../src/object.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h @echo "..\..\..\src\object.c" $(VDSP)/ccblkfn.exe -c ..\..\..\src\object.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\object.doj -MM diff --git a/bsp/dm365/.config b/bsp/dm365/.config new file mode 100644 index 0000000000..30dc0871e5 --- /dev/null +++ b/bsp/dm365/.config @@ -0,0 +1,397 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=32 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +# CONFIG_RT_THREAD_PRIORITY_32 is not set +CONFIG_RT_THREAD_PRIORITY_256=y +CONFIG_RT_THREAD_PRIORITY_MAX=256 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=8 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=1024 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=936 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=128 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +CONFIG_RT_USING_DFS_NFS=y +CONFIG_RT_NFS_HOST_EXPORT="192.168.1.5:/" + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +CONFIG_RT_USING_PTHREADS=y +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_MODULE=y + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +# CONFIG_RT_LWIP_RAW is not set +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=8 +CONFIG_RT_LWIP_TCP_PCB_NUM=32 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=128 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=144 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set + +# +# BSP configure +# +CONFIG_RT_USING_GPIO_DEVICE=y +CONFIG_RT_USING_I2C_CONTROL=y +CONFIG_RT_USING_SDIO_CONTROL=y +CONFIG_RT_USING_SPI_CONTROL=y +CONFIG_RT_USING_EMAC=y +CONFIG_RT_MMU_PTE_SIZE=4096 diff --git a/bsp/dm365/Kconfig b/bsp/dm365/Kconfig new file mode 100644 index 0000000000..7c2d7799a9 --- /dev/null +++ b/bsp/dm365/Kconfig @@ -0,0 +1,50 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +comment "BSP configure" + +config RT_USING_GPIO_DEVICE + bool "Using GPIO" + default y + +config RT_USING_I2C_CONTROL + bool "Using I2C control" + select RT_USING_I2C + default y + +config RT_USING_SDIO_CONTROL + bool "Using SDIO control" + select RT_USING_SDIO + default y + +config RT_USING_SPI_CONTROL + bool "Using SPI control" + depends on RT_USING_SPI + default y + +config RT_USING_EMAC + bool "Using EMAC control" + depends on RT_USING_LWIP + default y + +config RT_MMU_PTE_SIZE + int "The first page table for MMU" + default 4096 + diff --git a/bsp/dm365/drivers/SConscript b/bsp/dm365/drivers/SConscript index 19f4c5c77c..287720aa96 100644 --- a/bsp/dm365/drivers/SConscript +++ b/bsp/dm365/drivers/SConscript @@ -11,19 +11,19 @@ src = Split(""" davinci_serial.c """) -if GetDepend('RT_USING_GPIO'): +if GetDepend('RT_USING_GPIO_DEVICE'): src += ['gpio.c'] -if GetDepend('RT_USING_I2C'): +if GetDepend('RT_USING_I2C_CONTROL'): src += ['i2c-davinci.c'] -if GetDepend('RT_USING_SDIO'): +if GetDepend('RT_USING_SDIO_CONTROL'): src += ['mmcsd.c'] -if GetDepend('RT_USING_SPI'): +if GetDepend('RT_USING_SPI_CONTROL'): src += ['spi-davinci.c'] -if GetDepend('RT_USING_LWIP'): +if GetDepend('RT_USING_EMAC'): src += ['davinci_emac.c'] group = DefineGroup('Startup', src, depend = [''], CPPPATH = path) diff --git a/bsp/dm365/rtconfig.h b/bsp/dm365/rtconfig.h index 2a8cbdb22a..ae16abdca6 100644 --- a/bsp/dm365/rtconfig.h +++ b/bsp/dm365/rtconfig.h @@ -1,264 +1,359 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 32 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 256 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define SCHEDULER_DEBUG -/* #define RT_THREAD_DEBUG */ +/* RT-Thread Kernel */ +#define RT_NAME_MAX 32 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +/* RT_THREAD_PRIORITY_32 is not set */ +#define RT_THREAD_PRIORITY_256 +#define RT_THREAD_PRIORITY_MAX 256 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ #define RT_USING_HOOK - -/* Using Software Timer */ +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 8 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ -#define IDLE_THREAD_STACK_SIZE 1024 +/* Inter-Thread communication */ - -/* SECTION: IPC */ -/* Using Semaphore */ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX - -/* Using Event */ #define RT_USING_EVENT - -/* Using MailBox */ #define RT_USING_MAILBOX - -/* Using Message Queue */ #define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ #define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ +/* RT_USING_SMALL_MEM is not set */ +#define RT_USING_SLAB #define RT_USING_HEAP -/* Using Small MM */ -/* #define RT_USING_SMALL_MEM */ +/* Kernel Device Object */ -/* Using SLAB Allocator */ -#define RT_USING_SLAB - -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE -#define RT_USING_DEVICE_IPC - -/* Using Module System */ -#define RT_USING_MODULE -#define RT_USING_LIBDL - -/* Interrupt debug */ +/* RT_USING_DEVICE_OPS is not set */ #define RT_USING_INTERRUPT_INFO - -#define RT_USING_SERIAL -/* SECTION: Console options */ #define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 1024 +#define RT_CONSOLEBUF_SIZE 1024 #define RT_CONSOLE_DEVICE_NAME "uart0" -/* SECTION: finsh, a C-Express shell */ -/* Using FinSH as Shell*/ -#define RT_USING_FINSH -/* Using symbol table */ -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY 1 -#define FINSH_USING_MSH - -/* SECTION: the runtime libc library */ -/* the runtime libc library */ -#define RT_USING_LIBC -#define RT_USING_PTHREADS - -/* SECTION: C++ support */ -/* Using C++ support */ -/* #define RT_USING_CPLUSPLUS */ - -/* SECTION: Device filesystem support */ -/* using DFS support */ -#define RT_USING_DFS -#define RT_USING_DFS_ELMFAT -/* use long file name feature */ -#define RT_DFS_ELM_USE_LFN 2 -#define RT_DFS_ELM_REENTRANT -/* define OEM code page */ -#define RT_DFS_ELM_CODE_PAGE 936 -/* Using OEM code page file */ -// #define RT_DFS_ELM_CODE_PAGE_FILE -/* the max number of file length */ -#define RT_DFS_ELM_MAX_LFN 128 -/* #define RT_USING_DFS_YAFFS2 */ -#define RT_USING_DFS_DEVFS - -#define RT_USING_DFS_NFS -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" - -#define DFS_USING_WORKDIR - -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 4 -/* the max number of opened files */ -#define DFS_FD_MAX 16 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 - -/* Enable freemodbus protocol stack*/ -/* #define RT_USING_MODBUS */ - -/* USING CPU FFS */ -#define RT_USING_CPU_FFS - -/* MMU pte item size defined */ -#define RT_MMU_PTE_SIZE 4096 - -#define RT_USING_GPIO - -#define RT_USING_I2C - -#define RT_USING_SPI - -#define RT_USING_SDIO -#define RT_MMCSD_DBG - -/* SECTION: lwip, a lightweight TCP/IP protocol stack */ -/* Using lightweight TCP/IP protocol stack */ -#define RT_USING_LWIP - -/* Trace LwIP protocol */ -/* #define RT_LWIP_DEBUG */ - -//#define RT_LWIP_REASSEMBLY_FRAG - -#define SO_REUSE 1 - -#define RT_LWIP_DNS - -/* Enable ICMP protocol */ -#define RT_LWIP_ICMP - -/* Enable IGMP protocol */ -#define RT_LWIP_IGMP - -/* Enable UDP protocol */ -#define RT_LWIP_UDP - -/* Enable TCP protocol */ -#define RT_LWIP_TCP - -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 32 - -/* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 1460*10 - -/* TCP receive window. */ -#define RT_LWIP_TCP_WND 1460*8 - -/* Enable SNMP protocol */ -/* #define RT_LWIP_SNMP */ - -/* Using DHCP */ -/* #define RT_LWIP_DHCP */ - -/* ip address of target */ -#define RT_LWIP_IPADDR "192.168.1.30" - -/* gateway address of target */ -#define RT_LWIP_GWADDR "192.168.1.1" - -/* mask address of target */ -#define RT_LWIP_MSKADDR "255.255.255.0" - -/* the number of blocks for pbuf */ -#define RT_LWIP_PBUF_NUM 16 - -/* the number of simultaneously queued TCP */ -#define RT_LWIP_TCP_SEG_NUM 40 - -/* thread priority of tcpip thread */ -#define RT_LWIP_TCPTHREAD_PRIORITY 128 - -/* mail box size of tcpip thread to wait for */ -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 - -/* thread stack size of tcpip thread */ -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 - -/* thread priority of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_PRIORITY 144 - -/* mail box size of ethnetif thread to wait for */ -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 - -/* thread stack size of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 - -/* SECTION: RTGUI support */ -/* using RTGUI support */ -/* #define RT_USING_RTGUI */ - -/* name length of RTGUI object */ -//#define RTGUI_NAME_MAX 16 -/* support 16 weight font */ -//#define RTGUI_USING_FONT16 -/* support 16 weight font */ -//#define RTGUI_USING_FONT12 -/* support Chinese font */ -//#define RTGUI_USING_FONTHZ -/* use DFS as file interface */ -//#define RTGUI_USING_DFS_FILERW -/* use font file as Chinese font */ -/* #define RTGUI_USING_HZ_FILE */ -/* use Chinese bitmap font */ -//#define RTGUI_USING_HZ_BMP -/* use small size in RTGUI */ -/* #define RTGUI_USING_SMALL_SIZE */ -/* use mouse cursor */ -/* #define RTGUI_USING_MOUSE_CURSOR */ - -/* SECTION: FTK support */ -/* using FTK support */ -/* #define RT_USING_FTK */ - -/* - * Note on FTK: - * - * FTK depends : - * #define RT_USING_NEWLIB - * #define DFS_USING_WORKDIR - * - * And the maximal length must great than 64 - * #define RT_DFS_ELM_MAX_LFN 128 - */ +/* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +/* FINSH_USING_MSH_ONLY is not set */ +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +/* RT_USING_DFS_MNTTABLE is not set */ +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 936 +#define RT_DFS_ELM_WORD_ACCESS +/* RT_DFS_ELM_USE_LFN_0 is not set */ +/* RT_DFS_ELM_USE_LFN_1 is not set */ +/* RT_DFS_ELM_USE_LFN_2 is not set */ +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 128 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +/* RT_DFS_ELM_USE_ERASE is not set */ +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS +/* RT_USING_DFS_ROMFS is not set */ +/* RT_USING_DFS_RAMFS is not set */ +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ +#define RT_USING_DFS_NFS +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_RTC is not set */ +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI +/* RT_USING_SPI_MSD is not set */ +/* RT_USING_SFUD is not set */ +/* RT_USING_W25QXX is not set */ +/* RT_USING_GD is not set */ +/* RT_USING_ENC28J60 is not set */ +/* RT_USING_SPI_WIFI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_WIFI is not set */ +/* RT_USING_AUDIO is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_PTHREADS +#define RT_USING_POSIX +/* RT_USING_POSIX_MMAP is not set */ +/* RT_USING_POSIX_TERMIOS is not set */ +/* RT_USING_POSIX_AIO is not set */ +#define RT_USING_MODULE + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +/* RT_USING_LWIP141 is not set */ +#define RT_USING_LWIP202 +/* RT_USING_LWIP_IPV6 is not set */ +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +/* RT_LWIP_SNMP is not set */ +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +/* RT_LWIP_RAW is not set */ +/* RT_LWIP_PPP is not set */ +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 8 +#define RT_LWIP_TCP_PCB_NUM 32 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 128 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +/* LWIP_NO_RX_THREAD is not set */ +/* LWIP_NO_TX_THREAD is not set */ +#define RT_LWIP_ETHTHREAD_PRIORITY 144 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 +/* RT_LWIP_REASSEMBLY_FRAG is not set */ +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +/* RT_LWIP_NETIF_LOOPBACK is not set */ +#define LWIP_NETIF_LOOPBACK 0 +/* RT_LWIP_STATS is not set */ +/* RT_LWIP_DEBUG is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ +/* LWIP_USING_DHCPD is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_LOGTRACE is not set */ +/* RT_USING_RYM is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_STM32F4_HAL is not set */ +/* PKG_USING_STM32F4_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_AHT10 is not set */ +/* PKG_USING_AP3216C is not set */ +/* PKG_USING_STM32_SDIO is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ + +/* sample package */ + +/* samples: kernel and components samples */ + +/* PKG_USING_KERNEL_SAMPLES is not set */ +/* PKG_USING_FILESYSTEM_SAMPLES is not set */ +/* PKG_USING_NETWORK_SAMPLES is not set */ +/* PKG_USING_PERIPHERAL_SAMPLES is not set */ + +/* example package: hello */ + +/* PKG_USING_HELLO is not set */ + +/* BSP configure */ + +#define RT_USING_GPIO_DEVICE +#define RT_USING_I2C_CONTROL +#define RT_USING_SDIO_CONTROL +#define RT_USING_SPI_CONTROL +#define RT_USING_EMAC +#define RT_MMU_PTE_SIZE 4096 #endif diff --git a/bsp/frdm-k64f/applications/application.c b/bsp/frdm-k64f/applications/application.c index 0b2f9cda6e..3d4448e2a5 100644 --- a/bsp/frdm-k64f/applications/application.c +++ b/bsp/frdm-k64f/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/applications/startup.c b/bsp/frdm-k64f/applications/startup.c index 430cf0f0bc..3627cb993b 100644 --- a/bsp/frdm-k64f/applications/startup.c +++ b/bsp/frdm-k64f/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/board.c b/bsp/frdm-k64f/board/board.c index a386d18520..334f571d69 100644 --- a/bsp/frdm-k64f/board/board.c +++ b/bsp/frdm-k64f/board/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/board.h b/bsp/frdm-k64f/board/board.h index fca6fd0ce2..7610ade1fe 100644 --- a/bsp/frdm-k64f/board/board.h +++ b/bsp/frdm-k64f/board/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/drv_emac.c b/bsp/frdm-k64f/board/drv_emac.c index b70fb1c310..606c141545 100644 --- a/bsp/frdm-k64f/board/drv_emac.c +++ b/bsp/frdm-k64f/board/drv_emac.c @@ -1,8 +1,7 @@ /* - * File : emac_drv.c - * i.MX6 EMAC Ethernet driver - * COPYRIGHT (C) 2015, Shanghai Real-Thread Electronic Technology Co.,Ltd - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version diff --git a/bsp/frdm-k64f/board/drv_emac.h b/bsp/frdm-k64f/board/drv_emac.h index c53b367647..e2d0ec8c8c 100644 --- a/bsp/frdm-k64f/board/drv_emac.h +++ b/bsp/frdm-k64f/board/drv_emac.h @@ -1,8 +1,7 @@ /* - * File : drv_emac.h - * i.MX6 EMAC Ethernet driver - * COPYRIGHT (C) 2015, Shanghai Real-Thread Electronic Technology Co.,Ltd - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version diff --git a/bsp/frdm-k64f/board/drv_uart.c b/bsp/frdm-k64f/board/drv_uart.c index 6481746fe0..c4a1da1013 100644 --- a/bsp/frdm-k64f/board/drv_uart.c +++ b/bsp/frdm-k64f/board/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/drv_uart.h b/bsp/frdm-k64f/board/drv_uart.h index 83580972d1..7fd78c9a4e 100644 --- a/bsp/frdm-k64f/board/drv_uart.h +++ b/bsp/frdm-k64f/board/drv_uart.h @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/led.c b/bsp/frdm-k64f/board/led.c index 3a13fef29b..aebea8bdce 100644 --- a/bsp/frdm-k64f/board/led.c +++ b/bsp/frdm-k64f/board/led.c @@ -1,11 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/board/led.h b/bsp/frdm-k64f/board/led.h index ca08d3f266..f1c62666d6 100644 --- a/bsp/frdm-k64f/board/led.h +++ b/bsp/frdm-k64f/board/led.h @@ -1,11 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/frdm-k64f/project.uvproj b/bsp/frdm-k64f/project.uvproj index 38dd4a8bda..9530fc5210 100644 --- a/bsp/frdm-k64f/project.uvproj +++ b/bsp/frdm-k64f/project.uvproj @@ -72,6 +72,8 @@ 0 0 + 0 + 0 0 @@ -80,6 +82,8 @@ 0 0 + 0 + 0 0 @@ -141,10 +145,9 @@ 1 1 1 - 0 0 - 6 + 3 @@ -224,6 +227,7 @@ 0 0 0 + 0 3 3 0 @@ -358,6 +362,13 @@ 0 1 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 CPU_MK64FN1M0VLL12 @@ -375,6 +386,7 @@ 0 0 0 + 0 diff --git a/bsp/frdm-k64f/project.uvprojx b/bsp/frdm-k64f/project.uvprojx index 7d8bef0d9c..0e5a4da425 100644 --- a/bsp/frdm-k64f/project.uvprojx +++ b/bsp/frdm-k64f/project.uvprojx @@ -1,41 +1,45 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ RT-Thread 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC MK64FN1M0xxx12 NXP - Keil.Kinetis_K60_DFP.1.5.0 - http://www.keil.com/pack/ + NXP.MK64F12_DFP.10.0.4 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x00030000) IRAM2(0x1FFF0000,0x00010000) IROM(0x00000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000 -FP0($$Device:MK64FN1M0xxx12$Flash\MK_P1M0.FLM)) 7425 $$Device:MK64FN1M0xxx12$Device\Include\MK64F12.h - - - - - - - - - + + + + + + + + + $$Device:MK64FN1M0xxx12$SVD\MK64F12.svd 0 0 - - - - - + + + + + 0 0 @@ -57,8 +61,8 @@ 0 0 - - + + 0 0 0 @@ -67,8 +71,8 @@ 0 0 - - + + 0 0 0 @@ -77,15 +81,15 @@ 0 0 - - + + 0 0 0 0 0 - + 0 @@ -99,17 +103,17 @@ 0 0 3 - - + + 1 SARMCM3.DLL - + DCM.DLL -pCM4 SARMCM3.DLL - + TCM.DLL -pCM4 @@ -133,11 +137,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -170,7 +174,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -203,8 +207,8 @@ 0 0 0 - 1 - 0 + 0 + 1 0 @@ -293,16 +297,16 @@ 0 - 0x20000000 - 0x30000 + 0x1fff0000 + 0x10000 0 - 0x1fff0000 - 0x10000 + 0x20000000 + 0x30000 - + 1 @@ -328,10 +332,10 @@ 0 0 - + CPU_MK64FN1M0VLL12 - - device;device/MK64F12;board;applications;.;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-2.0.2/src;../../components/net/lwip-2.0.2/src/include;../../components/net/lwip-2.0.2/src/include/ipv4;../../components/net/lwip-2.0.2/src/arch/include;../../components/net/lwip-2.0.2/src/include/netif;../../components/net/lwip-2.0.2/src/include/posix + + applications;.;board;device;device\MK64F12;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix @@ -346,10 +350,10 @@ 0 0 - - - - + + + + @@ -361,297 +365,29 @@ 0 0x00000000 0x1FFF0000 - - - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + - Device + Applications - fsl_adc16.c + application.c 1 - device/MK64F12/fsl_adc16.c + applications\application.c - - - fsl_clock.c + startup.c 1 - device/MK64F12/fsl_clock.c - - - - - fsl_cmp.c - 1 - device/MK64F12/fsl_cmp.c - - - - - fsl_cmt.c - 1 - device/MK64F12/fsl_cmt.c - - - - - fsl_common.c - 1 - device/MK64F12/fsl_common.c - - - - - fsl_crc.c - 1 - device/MK64F12/fsl_crc.c - - - - - fsl_dac.c - 1 - device/MK64F12/fsl_dac.c - - - - - fsl_dmamux.c - 1 - device/MK64F12/fsl_dmamux.c - - - - - fsl_dspi.c - 1 - device/MK64F12/fsl_dspi.c - - - - - fsl_dspi_edma.c - 1 - device/MK64F12/fsl_dspi_edma.c - - - - - fsl_edma.c - 1 - device/MK64F12/fsl_edma.c - - - - - fsl_enet.c - 1 - device/MK64F12/fsl_enet.c - - - - - fsl_ewm.c - 1 - device/MK64F12/fsl_ewm.c - - - - - fsl_flash.c - 1 - device/MK64F12/fsl_flash.c - - - - - fsl_flexbus.c - 1 - device/MK64F12/fsl_flexbus.c - - - - - fsl_flexcan.c - 1 - device/MK64F12/fsl_flexcan.c - - - - - fsl_ftm.c - 1 - device/MK64F12/fsl_ftm.c - - - - - fsl_gpio.c - 1 - device/MK64F12/fsl_gpio.c - - - - - fsl_i2c.c - 1 - device/MK64F12/fsl_i2c.c - - - - - fsl_i2c_edma.c - 1 - device/MK64F12/fsl_i2c_edma.c - - - - - fsl_llwu.c - 1 - device/MK64F12/fsl_llwu.c - - - - - fsl_lptmr.c - 1 - device/MK64F12/fsl_lptmr.c - - - - - fsl_pdb.c - 1 - device/MK64F12/fsl_pdb.c - - - - - fsl_pit.c - 1 - device/MK64F12/fsl_pit.c - - - - - fsl_pmc.c - 1 - device/MK64F12/fsl_pmc.c - - - - - fsl_rcm.c - 1 - device/MK64F12/fsl_rcm.c - - - - - fsl_rnga.c - 1 - device/MK64F12/fsl_rnga.c - - - - - fsl_rtc.c - 1 - device/MK64F12/fsl_rtc.c - - - - - fsl_sai.c - 1 - device/MK64F12/fsl_sai.c - - - - - fsl_sai_edma.c - 1 - device/MK64F12/fsl_sai_edma.c - - - - - fsl_sdhc.c - 1 - device/MK64F12/fsl_sdhc.c - - - - - fsl_sim.c - 1 - device/MK64F12/fsl_sim.c - - - - - fsl_smc.c - 1 - device/MK64F12/fsl_smc.c - - - - - fsl_sysmpu.c - 1 - device/MK64F12/fsl_sysmpu.c - - - - - fsl_uart.c - 1 - device/MK64F12/fsl_uart.c - - - - - fsl_uart_edma.c - 1 - device/MK64F12/fsl_uart_edma.c - - - - - fsl_vref.c - 1 - device/MK64F12/fsl_vref.c - - - - - fsl_wdog.c - 1 - device/MK64F12/fsl_wdog.c - - - - - system_MK64F12.c - 1 - device/system_MK64F12.c - - - - - startup_MK64F12.s - 2 - device/TOOLCHAIN_ARM_STD/startup_MK64F12.s + applications\startup.c @@ -661,59 +397,237 @@ board.c 1 - board/board.c + board\board.c - - clock_config.c 1 - board/clock_config.c + board\clock_config.c - - drv_uart.c 1 - board/drv_uart.c + board\drv_uart.c - - led.c 1 - board/led.c + board\led.c - - drv_emac.c 1 - board/drv_emac.c + board\drv_emac.c - - fsl_phy.c 1 - board/fsl_phy.c + board\fsl_phy.c - Applications + Device - application.c + fsl_adc16.c 1 - applications/application.c + device\MK64F12\fsl_adc16.c - - - startup.c + fsl_clock.c 1 - applications/startup.c + device\MK64F12\fsl_clock.c + + + fsl_cmp.c + 1 + device\MK64F12\fsl_cmp.c + + + fsl_cmt.c + 1 + device\MK64F12\fsl_cmt.c + + + fsl_common.c + 1 + device\MK64F12\fsl_common.c + + + fsl_crc.c + 1 + device\MK64F12\fsl_crc.c + + + fsl_dac.c + 1 + device\MK64F12\fsl_dac.c + + + fsl_dmamux.c + 1 + device\MK64F12\fsl_dmamux.c + + + fsl_dspi.c + 1 + device\MK64F12\fsl_dspi.c + + + fsl_dspi_edma.c + 1 + device\MK64F12\fsl_dspi_edma.c + + + fsl_edma.c + 1 + device\MK64F12\fsl_edma.c + + + fsl_enet.c + 1 + device\MK64F12\fsl_enet.c + + + fsl_ewm.c + 1 + device\MK64F12\fsl_ewm.c + + + fsl_flash.c + 1 + device\MK64F12\fsl_flash.c + + + fsl_flexbus.c + 1 + device\MK64F12\fsl_flexbus.c + + + fsl_flexcan.c + 1 + device\MK64F12\fsl_flexcan.c + + + fsl_ftm.c + 1 + device\MK64F12\fsl_ftm.c + + + fsl_gpio.c + 1 + device\MK64F12\fsl_gpio.c + + + fsl_i2c.c + 1 + device\MK64F12\fsl_i2c.c + + + fsl_i2c_edma.c + 1 + device\MK64F12\fsl_i2c_edma.c + + + fsl_llwu.c + 1 + device\MK64F12\fsl_llwu.c + + + fsl_lptmr.c + 1 + device\MK64F12\fsl_lptmr.c + + + fsl_pdb.c + 1 + device\MK64F12\fsl_pdb.c + + + fsl_pit.c + 1 + device\MK64F12\fsl_pit.c + + + fsl_pmc.c + 1 + device\MK64F12\fsl_pmc.c + + + fsl_rcm.c + 1 + device\MK64F12\fsl_rcm.c + + + fsl_rnga.c + 1 + device\MK64F12\fsl_rnga.c + + + fsl_rtc.c + 1 + device\MK64F12\fsl_rtc.c + + + fsl_sai.c + 1 + device\MK64F12\fsl_sai.c + + + fsl_sai_edma.c + 1 + device\MK64F12\fsl_sai_edma.c + + + fsl_sdhc.c + 1 + device\MK64F12\fsl_sdhc.c + + + fsl_sim.c + 1 + device\MK64F12\fsl_sim.c + + + fsl_smc.c + 1 + device\MK64F12\fsl_smc.c + + + fsl_sysmpu.c + 1 + device\MK64F12\fsl_sysmpu.c + + + fsl_uart.c + 1 + device\MK64F12\fsl_uart.c + + + fsl_uart_edma.c + 1 + device\MK64F12\fsl_uart_edma.c + + + fsl_vref.c + 1 + device\MK64F12\fsl_vref.c + + + fsl_wdog.c + 1 + device\MK64F12\fsl_wdog.c + + + system_MK64F12.c + 1 + device\system_MK64F12.c + + + startup_MK64F12.s + 2 + device\TOOLCHAIN_ARM_STD\startup_MK64F12.s @@ -723,98 +637,72 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c - - components.c 1 - ../../src/components.c + ..\..\src\components.c - - device.c 1 - ../../src/device.c + ..\..\src\device.c - - idle.c 1 - ../../src/idle.c + ..\..\src\idle.c - - ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c - - irq.c 1 - ../../src/irq.c + ..\..\src\irq.c - - kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c - - mem.c 1 - ../../src/mem.c + ..\..\src\mem.c - - mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c - - object.c 1 - ../../src/object.c + ..\..\src\object.c - - scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c - - signal.c 1 - ../../src/signal.c + ..\..\src\signal.c - - thread.c 1 - ../../src/thread.c + ..\..\src\thread.c - - timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -824,35 +712,27 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m4/cpuport.c + ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 - ../../libcpu/arm/cortex-m4/context_rvds.S + ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c - - showmem.c 1 - ../../libcpu/arm/common/showmem.c + ..\..\libcpu\arm\common\showmem.c @@ -862,49 +742,37 @@ serial.c 1 - ../../components/drivers/serial/serial.c + ..\..\components\drivers\serial\serial.c - - completion.c 1 - ../../components/drivers/src/completion.c + ..\..\components\drivers\src\completion.c - - dataqueue.c 1 - ../../components/drivers/src/dataqueue.c + ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 - ../../components/drivers/src/pipe.c + ..\..\components\drivers\src\pipe.c - - ringbuffer.c 1 - ../../components/drivers/src/ringbuffer.c + ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 - ../../components/drivers/src/waitqueue.c + ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 - ../../components/drivers/src/workqueue.c + ..\..\components\drivers\src\workqueue.c @@ -914,91 +782,67 @@ shell.c 1 - ../../components/finsh/shell.c + ..\..\components\finsh\shell.c - - symbol.c 1 - ../../components/finsh/symbol.c + ..\..\components\finsh\symbol.c - - cmd.c 1 - ../../components/finsh/cmd.c + ..\..\components\finsh\cmd.c - - finsh_compiler.c 1 - ../../components/finsh/finsh_compiler.c + ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 - ../../components/finsh/finsh_error.c + ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 - ../../components/finsh/finsh_heap.c + ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 - ../../components/finsh/finsh_init.c + ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 - ../../components/finsh/finsh_node.c + ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 - ../../components/finsh/finsh_ops.c + ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 - ../../components/finsh/finsh_parser.c + ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 - ../../components/finsh/finsh_var.c + ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 - ../../components/finsh/finsh_vm.c + ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 - ../../components/finsh/finsh_token.c + ..\..\components\finsh\finsh_token.c @@ -1008,268 +852,203 @@ sys_arch.c 1 - ../../components/net/lwip-2.0.2/src/arch/sys_arch.c + ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - api_lib.c 1 - ../../components/net/lwip-2.0.2/src/api/api_lib.c + ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - api_msg.c 1 - ../../components/net/lwip-2.0.2/src/api/api_msg.c + ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - err.c 1 - ../../components/net/lwip-2.0.2/src/api/err.c + ..\..\components\net\lwip-2.0.2\src\api\err.c - - netbuf.c 1 - ../../components/net/lwip-2.0.2/src/api/netbuf.c + ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - netdb.c 1 - ../../components/net/lwip-2.0.2/src/api/netdb.c + ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - netifapi.c 1 - ../../components/net/lwip-2.0.2/src/api/netifapi.c + ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - sockets.c 1 - ../../components/net/lwip-2.0.2/src/api/sockets.c + ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - tcpip.c 1 - ../../components/net/lwip-2.0.2/src/api/tcpip.c + ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - def.c 1 - ../../components/net/lwip-2.0.2/src/core/def.c + ..\..\components\net\lwip-2.0.2\src\core\def.c - - dns.c 1 - ../../components/net/lwip-2.0.2/src/core/dns.c + ..\..\components\net\lwip-2.0.2\src\core\dns.c - - inet_chksum.c 1 - ../../components/net/lwip-2.0.2/src/core/inet_chksum.c + ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - init.c 1 - ../../components/net/lwip-2.0.2/src/core/init.c + ..\..\components\net\lwip-2.0.2\src\core\init.c - - ip.c 1 - ../../components/net/lwip-2.0.2/src/core/ip.c + ..\..\components\net\lwip-2.0.2\src\core\ip.c - - memp.c 1 - ../../components/net/lwip-2.0.2/src/core/memp.c + ..\..\components\net\lwip-2.0.2\src\core\memp.c - - netif.c 1 - ../../components/net/lwip-2.0.2/src/core/netif.c + ..\..\components\net\lwip-2.0.2\src\core\netif.c - - pbuf.c 1 - ../../components/net/lwip-2.0.2/src/core/pbuf.c + ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - raw.c 1 - ../../components/net/lwip-2.0.2/src/core/raw.c + ..\..\components\net\lwip-2.0.2\src\core\raw.c - - stats.c 1 - ../../components/net/lwip-2.0.2/src/core/stats.c + ..\..\components\net\lwip-2.0.2\src\core\stats.c - - sys.c 1 - ../../components/net/lwip-2.0.2/src/core/sys.c + ..\..\components\net\lwip-2.0.2\src\core\sys.c - - tcp.c 1 - ../../components/net/lwip-2.0.2/src/core/tcp.c + ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - tcp_in.c 1 - ../../components/net/lwip-2.0.2/src/core/tcp_in.c + ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - tcp_out.c 1 - ../../components/net/lwip-2.0.2/src/core/tcp_out.c + ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - timeouts.c 1 - ../../components/net/lwip-2.0.2/src/core/timeouts.c + ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - udp.c 1 - ../../components/net/lwip-2.0.2/src/core/udp.c + ..\..\components\net\lwip-2.0.2\src\core\udp.c - - ethernet.c 1 - ../../components/net/lwip-2.0.2/src/netif/ethernet.c + ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - ethernetif.c 1 - ../../components/net/lwip-2.0.2/src/netif/ethernetif.c + ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - lowpan6.c 1 - ../../components/net/lwip-2.0.2/src/netif/lowpan6.c + ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - autoip.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/autoip.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - dhcp.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/dhcp.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - etharp.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/etharp.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - icmp.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/icmp.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - igmp.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/igmp.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - ip4.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/ip4.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - ip4_addr.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_addr.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - ip4_frag.c 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_frag.c + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + + ::CMSIS + + - + - + - + - + + diff --git a/bsp/frdm-k64f/rtconfig.py b/bsp/frdm-k64f/rtconfig.py index ff874e791e..1f4d8d246e 100644 --- a/bsp/frdm-k64f/rtconfig.py +++ b/bsp/frdm-k64f/rtconfig.py @@ -63,7 +63,7 @@ elif PLATFORM == 'armcc': LINK = 'armlink' TARGET_EXT = 'axf' - DEVICE = ' --device DARMSTM' + DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = DEVICE + ' --apcs=interwork' AFLAGS = DEVICE LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k64f.map --scatter MK64F.sct' diff --git a/bsp/frdm-k64f/template.uvprojx b/bsp/frdm-k64f/template.uvprojx index ac684902ab..cbc80c689e 100644 --- a/bsp/frdm-k64f/template.uvprojx +++ b/bsp/frdm-k64f/template.uvprojx @@ -14,8 +14,8 @@ MK64FN1M0xxx12 NXP - Keil.Kinetis_K60_DFP.1.5.0 - http://www.keil.com/pack/ + NXP.MK64F12_DFP.10.0.4 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x00030000) IRAM2(0x1FFF0000,0x00010000) IROM(0x00000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -206,8 +206,8 @@ 0 0 0 - 1 - 0 + 0 + 1 0 @@ -296,13 +296,13 @@ 0 - 0x20000000 - 0x30000 + 0x1fff0000 + 0x10000 0 - 0x1fff0000 - 0x10000 + 0x20000000 + 0x30000 diff --git a/bsp/gd32450z-eval/project.uvproj b/bsp/gd32450z-eval/project.uvproj index 86ebb419d7..7913c0ca08 100644 --- a/bsp/gd32450z-eval/project.uvproj +++ b/bsp/gd32450z-eval/project.uvproj @@ -10,7 +10,8 @@ rt-thread_gd32f4xx 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 GD32F450ZK @@ -148,7 +149,7 @@ 1 0 - 2 + 3 @@ -362,6 +363,7 @@ 0 0 1 + 0 0 1 1 @@ -374,7 +376,7 @@ GD32F4XX, RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - applications;.;drivers;Libraries\CMSIS\GD\GD32F4xx\Include;Libraries\CMSIS;Libraries\GD32F4xx_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + applications;.;drivers;Libraries\CMSIS\GD\GD32F4xx\Include;Libraries\CMSIS;Libraries\GD32F4xx_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket @@ -1133,16 +1135,16 @@ 1 ..\..\components\net\sal_socket\socket\net_netdb.c - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - af_inet_lwip.c 1 ..\..\components\net\sal_socket\impl\af_inet_lwip.c + + net_sockets.c + 1 + ..\..\components\net\sal_socket\socket\net_sockets.c + dfs_net.c 1 diff --git a/bsp/gd32450z-eval/project.uvprojx b/bsp/gd32450z-eval/project.uvprojx index 3bcefee67b..9937bd77c5 100644 --- a/bsp/gd32450z-eval/project.uvprojx +++ b/bsp/gd32450z-eval/project.uvprojx @@ -10,7 +10,8 @@ rt-thread_gd32f4xx 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 GD32F450ZK @@ -323,6 +324,7 @@ 0 0 1 + 0 0 1 1 @@ -335,7 +337,7 @@ GD32F4XX, RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - applications;.;drivers;Libraries\CMSIS\GD\GD32F4xx\Include;Libraries\CMSIS;Libraries\GD32F4xx_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + applications;.;drivers;Libraries\CMSIS\GD\GD32F4xx\Include;Libraries\CMSIS;Libraries\GD32F4xx_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket @@ -1094,16 +1096,16 @@ 1 ..\..\components\net\sal_socket\socket\net_netdb.c - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - af_inet_lwip.c 1 ..\..\components\net\sal_socket\impl\af_inet_lwip.c + + net_sockets.c + 1 + ..\..\components\net\sal_socket\socket\net_sockets.c + dfs_net.c 1 diff --git a/bsp/hifive1/Makefile b/bsp/hifive1/Makefile new file mode 100644 index 0000000000..fe67833df4 --- /dev/null +++ b/bsp/hifive1/Makefile @@ -0,0 +1,7 @@ +scons := python ${SCONS}\scons.py + +all: + @$(scons) + +clean: + @$(scons) -c diff --git a/bsp/hifive1/README.md b/bsp/hifive1/README.md index 2a9285931b..7c65c15b78 100644 --- a/bsp/hifive1/README.md +++ b/bsp/hifive1/README.md @@ -2,28 +2,148 @@ ## 简介 -[HIFIVE1](https://www.sifive.com/products/hifive1/)是SiFive提供的一款基于RISCV的开发板，搭载SiFive Freedom E310。 +[HIFIVE1](https://www.sifive.com/products/hifive1/) 是由 SiFive 公司推出的全球首款基于开源指令集 RISC-V 架构的商用 SoC Freedom E310 的开发板。 -板载主要资源如下： +![1538284005769](figures/board.png) + + + +### 板载资源： | 硬件 | 描述 | | -- | -- | -|CPU| SiFive E31 RISC-V Core | -|架构| 32-bit RV32IMAC | -|主频| 320+ MHz | +|Soc| SiFive Freedom E310 (FE310) | +| 内核 | SiFive E31 RISC-V Core | +| 架构 | 32-bit RV32IMAC | +| 主频 | 320+ MHz | +| 性能 | 1.61 DMIPs/MHz, 2.73 Coremark/MHz | |SRAM| 16KB | |Flash| 16MB QSPI + 16KB 指令Cache | ## 编译说明 -HIFIVE1可以自行编译工具链，或者使用SiFive提供的[二进制版本](https://www.sifive.com/products/tools/)。 +### 下载 Freedom Studio + +Freedom Studio 是 SiFive 公司推出的一个集成开发环境，用来编写和调试基于 SiFive 处理器的软件。内嵌了编译好的 RISC-V GCC 工具链、OpenOCD、以及一些示例和文档。 + +下载地址：[官网下载](https://www.sifive.com/products/tools/) + +![1538295358180](figures/dowmload.png) + +下载成功之后，解压到和 rt-thread 源码同一目录下 + +![1538295750998](figures/untar.png) + +### 配置工具链 + +工具链就在解压开的 IDE `F:\FreedomStudio\SiFive\riscv64-unknown-elf-gcc-20171231-x86_64-w64-mingw32\bin` 目录下。 + +在源码 `rt-thread/bsp/hifive1/` 目录下，运行 env 工具，输入下面的命令设置 gcc 工具链路径 + +``` +set RTT_EXEC_PATH=F:\FreedomStudio\SiFive\riscv64-unknown-elf-gcc-20171231-x86_64-w64-mingw32\bin +``` + +### 添加环境变量 + +将 **工具链**和**编译工具**的路径 添加到环境变量里，输入命令如下 + +``` +set path=%path%;工具链的路径;编译工具的路径; +``` + +例如： + +``` +set path=%path%;F:\FreedomStudio\SiFive\riscv64-unknown-elf-gcc-20171231-x86_64-w64-mingw32\bin;F:\FreedomStudio\build-tools\bin +``` + +![1538296570129](figures/env.png) + +### 从 env 工具打开 IDE + +利用 cd 命令，切换到解压开的 IDE 目录 + +![1538296766437](figures/cd.png) + +输入 Freedom Studio 按 Tab 键 自动补全，然后按回车运行 IDE。 + +![1538296878924](figures/open_ide.png) + +在弹出的窗口输入 workspace 创建工作空间，然后点击启动打开 IDE。 + +![1538296978929](figures/ide.png) + +### 导入工程 + +在菜单栏点击 `File->Import` + +![1538297215062](figures/import.png) + +按照下面的图片导入工程 + +![1538297303505](figures/import2.png) + +![1538297553367](figures/import3.png) + + + +### 编译 + +![1538297679868](figures/build.png) + +然后等待编译完成 + +![1538297922206](figures/builded.png) + + ## 烧写及执行 -供电方式：开发板使用 Micro USB 线连接电脑和开发板。 +### 安装驱动 -下载程序：参看[hifive1-getting-started](https://static.dev.sifive.com/dev.../hifive1/hifive1-getting-started-v1.0.2.pdf)完成开发环境的配置，运行bsp里的openocd.sh脚本就可以下载程序了。 +1. 使用 Micro USB 线连接电脑和开发板。 + +2. 然后双击安装 IDE 目录 `F:\FreedomStudio\SiFive\Drivers` 下的驱动文件 + +### 添加字符串定义 + +点击菜单栏 `Window->preferences` 按下图的步骤将 字符串 `cross_prefix` 定义为 `riscv64-unknown-elf-` + +![1538298633528](figures/string.png) + +### 配置 Debug 参数 + +选中生成的 `rtthread.elf` 文件,右键配置 Debug 参数，如下图所示 + +![1538298914673](figures/debug.png) + +按下图新建一个 Debug 选项 + +![1538299063801](figures/debug1.png) + +打开 `Debugger` 选项卡 添加如下参数 + +``` +-f openocd.cfg + +set mem inaccessible-by-default off +set arch riscv:rv32 +set remotetimeout 250 +``` + +如下图所示： + +![1538299273874](figures/debug2.png) + +打开 `startup` 选项卡，去掉**主机模式**和**复位命令** + +![1538299521246](figures/debug3.png) + +然后待程序停止在 main 函数处，然后点击继续运行程序就运行起来了。 + +![1538299736730](figures/run.png) ### 运行结果 @@ -41,10 +161,8 @@ msh > | 驱动 | 支持情况 | 备注 | | ------ | ---- | :------: | -| UART | 支持 | | -| GPIO | 未支持 | | -| SPI | 未支持 | | -| I2C | 未支持 | | +| UART | 支持 | UART0_RX/TX：GPIO 16/17 | + ### 4.1 IO在板级支持包中的映射情况 @@ -65,5 +183,3 @@ msh > * [HIFIVE1 Software Development Tools](https://www.sifive.com/products/tools/) * [hifive1-getting-started-guide](https://www.sifive.com/documentation/boards/hifive1/hifive1-getting-started-guide/) * [hifive1-schematics](https://www.sifive.com/documentation/boards/hifive1/hifive1-schematics/) - - diff --git a/bsp/hifive1/figures/board.png b/bsp/hifive1/figures/board.png new file mode 100644 index 0000000000..8565696a43 Binary files /dev/null and b/bsp/hifive1/figures/board.png differ diff --git a/bsp/hifive1/figures/build.png b/bsp/hifive1/figures/build.png new file mode 100644 index 0000000000..966546c752 Binary files /dev/null and b/bsp/hifive1/figures/build.png differ diff --git a/bsp/hifive1/figures/builded.png b/bsp/hifive1/figures/builded.png new file mode 100644 index 0000000000..ba39f7f254 Binary files /dev/null and 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a/bsp/hifive1/figures/string.png b/bsp/hifive1/figures/string.png new file mode 100644 index 0000000000..747ecbfe4e Binary files /dev/null and b/bsp/hifive1/figures/string.png differ diff --git a/bsp/hifive1/figures/untar.png b/bsp/hifive1/figures/untar.png new file mode 100644 index 0000000000..69667a4ec9 Binary files /dev/null and b/bsp/hifive1/figures/untar.png differ diff --git a/bsp/hifive1/rtconfig.py b/bsp/hifive1/rtconfig.py index 231a1ef858..a339f34064 100644 --- a/bsp/hifive1/rtconfig.py +++ b/bsp/hifive1/rtconfig.py @@ -16,8 +16,8 @@ if CROSS_TOOL == 'gcc': if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') -#BUILD = 'debug' -BUILD = 'release' +BUILD = 'debug' +#BUILD = 'release' CORE = 'risc-v' MAP_FILE = 'rtthread.map' @@ -37,7 +37,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -g -L. -nostartfiles -lc ' + DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L. -nostartfiles -lc ' CFLAGS = DEVICE CFLAGS += ' -save-temps=obj' AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp' @@ -51,8 +51,8 @@ if PLATFORM == 'gcc': LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3' else: CFLAGS += ' -O2' diff --git a/bsp/imx6sx/cortex-a9/.config b/bsp/imx6sx/cortex-a9/.config new file mode 100644 index 0000000000..cb857b4c0f --- /dev/null +++ b/bsp/imx6sx/cortex-a9/.config @@ -0,0 +1,354 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_POSIX is not set +CONFIG_SAL_SOCKETS_NUM=16 +CONFIG_SAL_PROTO_FAMILIES_NUM=4 + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +# CONFIG_RT_LWIP_RAW is not set +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_RT_USING_UART1=y diff --git a/bsp/imx6sx/cortex-a9/Kconfig b/bsp/imx6sx/cortex-a9/Kconfig new file mode 100644 index 0000000000..a54e2f40be --- /dev/null +++ b/bsp/imx6sx/cortex-a9/Kconfig @@ -0,0 +1,32 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example: default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config $ENV_DIR + string + option env="ENV_ROOT" + default "/" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config RT_USING_UART1 + bool "Using RT_USING_UART1" + default y + diff --git a/bsp/imx6sx/cortex-a9/applications/application.c b/bsp/imx6sx/cortex-a9/applications/application.c deleted file mode 100644 index 7b409b2b25..0000000000 --- a/bsp/imx6sx/cortex-a9/applications/application.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2012-11-20 Bernard the first version - */ - -#include - -#include -#include - -void show_freq(void) -{ - rt_kprintf("CPU: %d MHz\n", get_main_clock(CPU_CLK)/1000000); - rt_kprintf("DDR: %d MHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000000); - rt_kprintf("IPG: %d MHz\n", get_main_clock(IPG_CLK)/1000000); -} - -void init_thread(void* parameter) -{ - rt_kprintf("Freescale i.MX6 Platform SDK %s\n", SDK_VERSION_STRING); - show_freq(); - - rt_components_init(); -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", init_thread, RT_NULL, - 1024, RT_THREAD_PRIORITY_MAX/3, 10); - if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; -} diff --git a/bsp/imx6sx/cortex-a9/applications/main.c b/bsp/imx6sx/cortex-a9/applications/main.c new file mode 100644 index 0000000000..9b0847fc8f --- /dev/null +++ b/bsp/imx6sx/cortex-a9/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include +#include +#include + +int main(void) +{ + printf("hello rt-thread\n"); + return 0; +} + diff --git a/bsp/imx6sx/cortex-a9/cpu/context_gcc.S b/bsp/imx6sx/cortex-a9/cpu/context_gcc.S index 01593a7c0a..97b3dbc447 100644 --- a/bsp/imx6sx/cortex-a9/cpu/context_gcc.S +++ b/bsp/imx6sx/cortex-a9/cpu/context_gcc.S @@ -1,21 +1,7 @@ /* - * File : context.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/cp15_gcc.S b/bsp/imx6sx/cortex-a9/cpu/cp15_gcc.S index f1ed6492aa..0e3e60655c 100644 --- a/bsp/imx6sx/cortex-a9/cpu/cp15_gcc.S +++ b/bsp/imx6sx/cortex-a9/cpu/cp15_gcc.S @@ -1,22 +1,7 @@ /* - * File : cp15_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team - * http://www.rt-thread.org + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/cpu.c b/bsp/imx6sx/cortex-a9/cpu/cpu.c index 7dd426e4dd..2d78715011 100644 --- a/bsp/imx6sx/cortex-a9/cpu/cpu.c +++ b/bsp/imx6sx/cortex-a9/cpu/cpu.c @@ -1,11 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/interrupt.c b/bsp/imx6sx/cortex-a9/cpu/interrupt.c index 942c074721..3934c84aaf 100644 --- a/bsp/imx6sx/cortex-a9/cpu/interrupt.c +++ b/bsp/imx6sx/cortex-a9/cpu/interrupt.c @@ -1,11 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/mmu.c b/bsp/imx6sx/cortex-a9/cpu/mmu.c index b2503e4260..58acdd8145 100644 --- a/bsp/imx6sx/cortex-a9/cpu/mmu.c +++ b/bsp/imx6sx/cortex-a9/cpu/mmu.c @@ -1,11 +1,7 @@ /* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/pmu.c b/bsp/imx6sx/cortex-a9/cpu/pmu.c index 07911a2db7..8ffc1dede6 100644 --- a/bsp/imx6sx/cortex-a9/cpu/pmu.c +++ b/bsp/imx6sx/cortex-a9/cpu/pmu.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "pmu.h" diff --git a/bsp/imx6sx/cortex-a9/cpu/stack.c b/bsp/imx6sx/cortex-a9/cpu/stack.c index e653c5d111..2bd3c36915 100644 --- a/bsp/imx6sx/cortex-a9/cpu/stack.c +++ b/bsp/imx6sx/cortex-a9/cpu/stack.c @@ -1,11 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/start_gcc.S b/bsp/imx6sx/cortex-a9/cpu/start_gcc.S index ca8c1f930f..2f16d16807 100644 --- a/bsp/imx6sx/cortex-a9/cpu/start_gcc.S +++ b/bsp/imx6sx/cortex-a9/cpu/start_gcc.S @@ -1,21 +1,7 @@ /* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/trap.c b/bsp/imx6sx/cortex-a9/cpu/trap.c index 515f7cb544..f3b2c26e6d 100644 --- a/bsp/imx6sx/cortex-a9/cpu/trap.c +++ b/bsp/imx6sx/cortex-a9/cpu/trap.c @@ -1,11 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/cpu/vector_gcc.S b/bsp/imx6sx/cortex-a9/cpu/vector_gcc.S index 4a44a7395c..60d3c6cf1d 100644 --- a/bsp/imx6sx/cortex-a9/cpu/vector_gcc.S +++ b/bsp/imx6sx/cortex-a9/cpu/vector_gcc.S @@ -1,21 +1,7 @@ /* - * File : vector_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/drivers/board.c b/bsp/imx6sx/cortex-a9/drivers/board.c index 1ac040d7e4..7ff9d47a89 100644 --- a/bsp/imx6sx/cortex-a9/drivers/board.c +++ b/bsp/imx6sx/cortex-a9/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/drivers/board.h b/bsp/imx6sx/cortex-a9/drivers/board.h index f3fe347584..9ae9ae60c7 100644 --- a/bsp/imx6sx/cortex-a9/drivers/board.h +++ b/bsp/imx6sx/cortex-a9/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c index ae61d2601c..af5ca009cf 100644 --- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c +++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c @@ -1,8 +1,7 @@ /* - * File : emac_drv.c - * i.MX6 EMAC Ethernet driver - * COPYRIGHT (C) 2015, Shanghai Real-Thread Electronic Technology Co.,Ltd - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h index 4400219d8e..face875283 100644 --- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h +++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h @@ -1,8 +1,7 @@ /* - * File : drv_emac.h - * i.MX6 EMAC Ethernet driver - * COPYRIGHT (C) 2015, Shanghai Real-Thread Electronic Technology Co.,Ltd - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-07-15 Bernard The first version diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.c b/bsp/imx6sx/cortex-a9/drivers/serial.c index ff6b1ac32e..a2d4e2338a 100644 --- a/bsp/imx6sx/cortex-a9/drivers/serial.c +++ b/bsp/imx6sx/cortex-a9/drivers/serial.c @@ -1,27 +1,7 @@ /* - * serial.c UART driver - * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.h b/bsp/imx6sx/cortex-a9/drivers/serial.h index 52e6f07ea3..00d464bde0 100644 --- a/bsp/imx6sx/cortex-a9/drivers/serial.h +++ b/bsp/imx6sx/cortex-a9/drivers/serial.h @@ -1,27 +1,7 @@ /* - * UART driver - * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6sx/cortex-a9/rtconfig.h b/bsp/imx6sx/cortex-a9/rtconfig.h index 427c4894e0..71f7cf4d9b 100644 --- a/bsp/imx6sx/cortex-a9/rtconfig.h +++ b/bsp/imx6sx/cortex-a9/rtconfig.h @@ -1,194 +1,197 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -// +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -// -#define RT_NAME_MAX 6 -// -#define RT_ALIGN_SIZE 4 -// -// 8 -// 32 -// 256 -// -#define RT_THREAD_PRIORITY_MAX 32 -// -#define RT_TICK_PER_SECOND 1000 -// -#define IDLE_THREAD_STACK_SIZE 512 -//
-#define RT_DEBUG -// -// #define RT_DEBUG_SCHEDULER 1 -// +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK -//
- -// #define RT_USING_HOOK -//
-// #define RT_USING_TIMER_SOFT -// -#define RT_TIMER_THREAD_PRIO 4 -// -#define RT_TIMER_THREAD_STACK_SIZE 512 -// -#define RT_TIMER_TICK_PER_SECOND 10 -//
+#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ -//
-// #define RT_USING_SEMAPHORE -// #define RT_USING_MUTEX -// #define RT_USING_EVENT -// #define RT_USING_MAILBOX -// #define RT_USING_MESSAGEQUEUE -//
-//
-// +/* Memory Management */ + #define RT_USING_MEMPOOL -// -// #define RT_USING_MEMHEAP -// -#define RT_USING_HEAP -// -// #define RT_USING_MEMHEAP_AS_HEAP -// #define RT_USING_SMALL_MEM -// -// #define RT_USING_SLAB -//
+#define RT_USING_HEAP + +/* Kernel Device Object */ -//
#define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL -// -#define RT_UART_RX_BUFFER_SIZE 64 -// -#define RT_USING_INTERRUPT_INFO -// -// #define RT_USING_UART0 -// -#define RT_USING_UART1 -//
- -//
#define RT_USING_CONSOLE -// -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart1" -//
+#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" + +/* RT-Thread Components */ -// #define RT_USING_COMPONENTS_INIT -//
+#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + #define RT_USING_FINSH -// -#define FINSH_USING_MSH -// -#define FINSH_USING_MSH_DEFAULT -// +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -// #define FINSH_USING_DESCRIPTION -// -#define FINSH_THREAD_STACK_SIZE 4096 -//
+#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 -//
-// -#define RT_USING_LIBC -// -#define RT_USING_PTHREADS -//
+/* Device virtual file system */ -//
-// #define RT_USING_DFS -// +#define RT_USING_DFS #define DFS_USING_WORKDIR -// -#define DFS_FILESYSTEMS_MAX 2 -// -#define DFS_FD_MAX 4 -// -// #define RT_USING_DFS_ELMFAT -// -// 1 -// 2 -// -#define RT_DFS_ELM_USE_LFN 1 -// -#define RT_DFS_ELM_MAX_LFN 64 -// -// #define RT_USING_DFS_YAFFS2 -// -// #define RT_USING_DFS_UFFS -// +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 #define RT_USING_DFS_DEVFS -// -// #define RT_USING_DFS_NFS -// -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" -//
-//
+/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + +#define RT_USING_SAL + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_SOCKETS_NUM 16 +#define SAL_PROTO_FAMILIES_NUM 4 + +/* light weight TCP/IP stack */ + #define RT_USING_LWIP -// +#define RT_USING_LWIP202 +#define RT_LWIP_IGMP #define RT_LWIP_ICMP -// -// #define RT_LWIP_IGMP -// -#define RT_LWIP_UDP -// -#define RT_LWIP_TCP -// #define RT_LWIP_DNS -// -// #define RT_LWIP_SNMP -// #define RT_LWIP_DHCP -// -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -// -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -// -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 -// -#define RT_LWIP_ETHTHREAD_PRIORITY 14 -// -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -// -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 -// -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 -// -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 -// -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 -//
+#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 -#define RT_USING_LOGTRACE +/* Static IPv4 Address */ -// +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_NETIF_LOOPBACK 0 + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + + +/* example package: hello */ + +#define RT_USING_UART1 #endif diff --git a/bsp/imx6ul/applications/application.c b/bsp/imx6ul/applications/application.c index d9580cda23..98fcbfc883 100644 --- a/bsp/imx6ul/applications/application.c +++ b/bsp/imx6ul/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6ul/applications/startup.c b/bsp/imx6ul/applications/startup.c index be041e0c0f..4c1f83619e 100644 --- a/bsp/imx6ul/applications/startup.c +++ b/bsp/imx6ul/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6ul/drivers/board.c b/bsp/imx6ul/drivers/board.c index 75df035630..e53e2405b6 100644 --- a/bsp/imx6ul/drivers/board.c +++ b/bsp/imx6ul/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6ul/drivers/board.h b/bsp/imx6ul/drivers/board.h index b063e49879..3e98e302c2 100644 --- a/bsp/imx6ul/drivers/board.h +++ b/bsp/imx6ul/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/imx6ul/drivers/serial.c b/bsp/imx6ul/drivers/serial.c index dcb4e16e12..0f6943cfbd 100644 --- a/bsp/imx6ul/drivers/serial.c +++ b/bsp/imx6ul/drivers/serial.c @@ -1,27 +1,7 @@ /* - * serial.c UART driver - * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6ul/drivers/serial.h b/bsp/imx6ul/drivers/serial.h index 52e6f07ea3..00d464bde0 100644 --- a/bsp/imx6ul/drivers/serial.h +++ b/bsp/imx6ul/drivers/serial.h @@ -1,27 +1,7 @@ /* - * UART driver - * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_common_tables.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..dfea7460e9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_const_structs.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000..80a3e8bbe7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_math.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..ea9dd26aa8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_armcc.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..093d35b9e5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_armclang.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..5c4c20e877 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_compiler.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..94212eb87a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_gcc.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..5d0f07e8ac --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_iccarm.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..edcaee3d4a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_version.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_armv8mbl.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000..47a39893ac --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_armv8mml.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000..0951a1f781 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm0.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..a3f1b9ac33 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm0plus.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..f8f30c3496 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm23.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000..7d1d478af2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm3.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..a2c0d08057 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm33.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000..b1efbcae7c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm4.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..a11a3817a2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm4.h @@ -0,0 +1,2118 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm7.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..1fe53bf012 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_sc000.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..9aab5e5b3e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_sc300.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..a569ef2ace --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/mpu_armv7.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..aa180c9e59 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/mpu_armv8.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000..0ccfc74fe5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/tz_context.h b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/imxrt/Libraries/imxrt1050/CMSIS/LICENSE.txt b/bsp/imxrt/Libraries/imxrt1050/CMSIS/LICENSE.txt new file mode 100644 index 0000000000..8dada3edaf --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052.h + * @version 0.1 + * @date 2017-01-10 + * @brief CMSIS Peripheral Access Layer for MIMXRT1052 + * + * CMSIS Peripheral Access Layer for MIMXRT1052 + */ + +#ifndef _MIMXRT1052_H_ +#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0000U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 176 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ + DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ + DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ + DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ + DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ + DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ + DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ + DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ + DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ + DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ + DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ + DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ + DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ + DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ + DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ + DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ + DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ + CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ + CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ + CORE_IRQn = 19, /**< CorePlatform exception IRQ */ + LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ + LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ + LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ + LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ + LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ + LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ + LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ + LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ + LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ + LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ + LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ + LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ + LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ + LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ + LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ + LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ + CAN1_IRQn = 36, /**< CAN1 interrupt */ + CAN2_IRQn = 37, /**< CAN2 interrupt */ + FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ + KPP_IRQn = 39, /**< Keypad nterrupt */ + TSC_DIG_IRQn = 40, /**< TSC interrupt */ + GPR_IRQ_IRQn = 41, /**< GPR interrupt */ + LCDIF_IRQn = 42, /**< LCDIF interrupt */ + CSI_IRQn = 43, /**< CSI interrupt */ + PXP_IRQn = 44, /**< PXP interrupt */ + WDOG2_IRQn = 45, /**< WDOG2 interrupt */ + SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */ + SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */ + SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ + CSU_IRQn = 49, /**< CSU interrupt */ + DCP_IRQn = 50, /**< DCP_IRQ interrupt */ + DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */ + Reserved68_IRQn = 52, /**< Reserved interrupt */ + TRNG_IRQn = 53, /**< TRNG interrupt */ + SJC_IRQn = 54, /**< SJC interrupt */ + BEE_IRQn = 55, /**< BEE interrupt */ + SAI1_IRQn = 56, /**< SAI1 interrupt */ + SAI2_IRQn = 57, /**< SAI1 interrupt */ + SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ + SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ + SPDIF_IRQn = 60, /**< SPDIF interrupt */ + ANATOP_EVENT0_IRQn = 61, /**< ANATOP interrupt */ + ANATOP_EVENT1_IRQn = 62, /**< ANATOP interrupt */ + ANATOP_TAMP_LOW_HIGH_IRQn = 63, /**< ANATOP interrupt */ + ANATOP_TEMP_PANIC_IRQn = 64, /**< ANATOP interrupt */ + USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ + USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ + ADC1_IRQn = 67, /**< ADC1 interrupt */ + ADC2_IRQn = 68, /**< ADC2 interrupt */ + DCDC_IRQn = 69, /**< DCDC interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Reserved87_IRQn = 71, /**< Reserved interrupt */ + GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ + GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ + GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ + GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ + FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ + FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */ + WDOG1_IRQn = 92, /**< WDOG1 interrupt */ + RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ + EWM_IRQn = 94, /**< EWM interrupt */ + CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ + CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ + GPC_IRQn = 97, /**< GPC interrupt */ + SRC_IRQn = 98, /**< SRC interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + GPT1_IRQn = 100, /**< GPT1 interrupt */ + GPT2_IRQn = 101, /**< GPT2 interrupt */ + PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ + PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ + PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ + PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ + PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ + SEMC_IRQn = 109, /**< Reserved interrupt */ + USDHC1_IRQn = 110, /**< USDHC1 interrupt */ + USDHC2_IRQn = 111, /**< USDHC2 interrupt */ + USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ + ENET_IRQn = 114, /**< ENET interrupt */ + ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ + XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ + XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ + ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ + ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ + ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ + ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ + PIT_IRQn = 122, /**< PIT interrupt */ + ACMP1_IRQn = 123, /**< ACMP interrupt */ + ACMP2_IRQn = 124, /**< ACMP interrupt */ + ACMP3_IRQn = 125, /**< ACMP interrupt */ + ACMP4_IRQn = 126, /**< ACMP interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + ENC1_IRQn = 129, /**< ENC1 interrupt */ + ENC2_IRQn = 130, /**< ENC2 interrupt */ + ENC3_IRQn = 131, /**< ENC3 interrupt */ + ENC4_IRQn = 132, /**< ENC4 interrupt */ + TMR1_IRQn = 133, /**< TMR1 interrupt */ + TMR2_IRQn = 134, /**< TMR2 interrupt */ + TMR3_IRQn = 135, /**< TMR3 interrupt */ + TMR4_IRQn = 136, /**< TMR4 interrupt */ + PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ + PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ + PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ + PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ + PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */ + PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */ + PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */ + PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */ + PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */ + PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */ + PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */ + PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ + PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ + PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ + PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */ + Reserved168_IRQn = 152, /**< Reserved interrupt */ + Reserved169_IRQn = 153, /**< Reserved interrupt */ + Reserved170_IRQn = 154, /**< Reserved interrupt */ + Reserved171_IRQn = 155, /**< Reserved interrupt */ + Reserved172_IRQn = 156, /**< Reserved interrupt */ + Reserved173_IRQn = 157, /**< Reserved interrupt */ + SJC_ARM_DEBUG_IRQn = 158, /**< SJC ARM debug interrupt */ + NMI_WAKEUP_IRQn = 159 /**< NMI wake up */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M7 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ +#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ +#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm7.h" /* Core Peripheral Access Layer */ +#include "system_MIMXRT1052.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the DMA0 hardware request + * + * Defines the enumeration for the DMA0 hardware request collections. + */ +typedef enum _dma_request_source +{ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */ + kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ + kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ + kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ + kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ + kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ + kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ + kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ + kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ + kDmaRequestMuxCSI = 12|0x100U, /**< CSI */ + kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ + kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ + kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ + kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ + kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ + kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< Sai1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< Sai1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< Sai2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< Sai2 Transmit */ + kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ + kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ + kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ + kDmaRequestMuxACMP2 = 26|0x100U, /**< ACMP2 */ + kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ + kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ + kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ + kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ + kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ + kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ + kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ + kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ + kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ + kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ + kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ + kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ + kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */ + kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */ + kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */ + kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */ + kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */ + kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ + kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ + kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< QTIMER3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 57|0x100U, /**< QTIMER3 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 58|0x100U, /**< QTIMER3 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */ + kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ + kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ + kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ + kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ + kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ + kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ + kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ + kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ + kDmaRequestMuxPxp = 75|0x100U, /**< PXP */ + kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */ + kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ + kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ + kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ + kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ + kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ + kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< Sai3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< Sai3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< Spdif Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< Spdif Transmit */ + kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ + kDmaRequestMuxACMP3 = 89|0x100U, /**< ACMP3 */ + kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ + kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< Enet Timer0 */ + kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< Enet Timer1 */ + kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ + kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ + kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ + kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ + kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ + kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ + kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ + kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ + kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ + kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ + kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */ + kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */ + kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */ + kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */ + kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */ + kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ + kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ + kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ + kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< QTIMER2 Capture timer 0 */ + kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< QTIMER2 Capture timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< QTIMER2 Capture timer 2 */ + kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< QTIMER2 Capture timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< QTIMER2 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< QTIMER2 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< QTIMER2 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< QTIMER2 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< QTIMER4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 121|0x100U, /**< QTIMER4 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 122|0x100U, /**< QTIMER4 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ +} dma_request_source_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +typedef enum _xbar_input_signal +{ + kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ + kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ + kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ + kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ + kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ + kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ + kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ + kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ + kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ + kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ + kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ + kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ + kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ + kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ + kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ + kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ + kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ + kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ + kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ + kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ + kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ + kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ + kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ + kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ + kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ + kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ + kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */ + kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */ + kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */ + kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */ + kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */ + kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */ + kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ + kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ + kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ + kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ + kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ + kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ + kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ + kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ + kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ + kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ + kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ + kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ + kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ + kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ + kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ + kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ + kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ + kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ + kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ + kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ + kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ + kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ + kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ + kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ + kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ + kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ + kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ + kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ + kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ + kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ + kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ + kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ + kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */ + kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */ + kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */ + kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */ + kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */ + kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */ + kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */ + kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */ + kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */ + kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */ + kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */ + kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */ + kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */ + kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */ + kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */ + kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */ + kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ + kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ + kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ + kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ + kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ + kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ + kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ + kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ + kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ + kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */ + kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */ + kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */ + kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */ + kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */ + kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */ + kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */ + kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */ + kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */ + kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */ + kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ + kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ + kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ + kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ + kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ + kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ + kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ + kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ + kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ + kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ + kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ + kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ + kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ + kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ + kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ + kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ + kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ + kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ + kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ + kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ + kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ + kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ + kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ + kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ + kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ + kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ + kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ + kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ + kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ + kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ + kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ + kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ + kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ + kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ + kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ + kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ + kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ + kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ + kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */ + kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */ + kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */ + kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */ + kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */ + kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */ + kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */ + kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */ + kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ + kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ + kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */ + kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */ + kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */ + kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */ + kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */ + kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */ + kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */ + kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */ + kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */ + kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */ + kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ + kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ + kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ + kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ + kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ + kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ + kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ + kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ + kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ + kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ + kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ + kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ + kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ + kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ + kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ + kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ + kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ + kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ + kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ + kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ + kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ + kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ + kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ + kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ + kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ + kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ + kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ + kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ + kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ + kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ + kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ + kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ + kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ + kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ + kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ + kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ + kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ + kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ + kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */ + kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */ + kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */ + kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */ + kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */ + kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */ + kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */ + kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ + kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ + kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ + kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ + kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ + kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ + kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ + kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ + kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ + kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ + kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ + kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ + kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ + kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ + kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ + kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ + kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ + kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ + kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ + kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ + kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ + kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ + kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ + kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ + kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */ + kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */ + kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ + kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ + kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ + kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ + kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ + kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ + kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ + kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ + kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ + kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ + kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ + kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ + kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ + kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ + kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ + kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ + kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ + kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ + kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ + kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ + kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ + kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ + kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ + kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ + kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */ + kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */ + kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */ + kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */ + kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */ + kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */ + kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */ + kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */ + kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */ + kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */ + kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */ + kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */ + kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */ + kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */ + kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */ + kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */ + kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */ + kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */ + kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */ + kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */ + kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */ + kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */ + kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */ + kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */ + kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */ + kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */ + kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */ + kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */ + kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */ + kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */ + kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */ + kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */ + kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */ + kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */ + kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */ + kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */ + kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */ + kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ + kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ + kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ + kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ + kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ + kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ + kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ + kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ + kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */ + kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */ + kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */ + kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */ + kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */ + kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */ + kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */ + kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */ + kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */ + kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */ + kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */ + kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */ + kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */ + kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */ + kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */ + kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */ + kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ + kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ + kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ + kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ + kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ + kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ + kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ + kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */ + kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */ + kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */ + kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */ + kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */ + kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */ + kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */ + kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */ + kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */ + kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */ + kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */ + kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */ + kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */ + kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */ + kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */ + kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */ + kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */ + kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */ + kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */ + kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */ + kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */ + kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */ + kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */ + kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */ + kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */ + kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */ + kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */ + kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */ + kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ + __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ + __IO uint32_t GC; /**< General control register, offset: 0x48 */ + __IO uint32_t GS; /**< General status register, offset: 0x4C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +/*! @{ */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (8U) + +/*! @name HS - Status register for HW triggers */ +/*! @{ */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ + +/*! @name R - Data result register for HW triggers */ +/*! @{ */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ + +/* The count of ADC_R */ +#define ADC_R_COUNT (8U) + +/*! @name CFG - Configuration register */ +/*! @{ */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ + +/*! @name GC - General control register */ +/*! @{ */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ + +/*! @name GS - General status register */ +/*! @{ */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ + +/*! @name CV - Compare value register */ +/*! @{ */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ + +/*! @name OFS - Offset correction value register */ +/*! @{ */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ + +/*! @name CAL - Calibration value register */ +/*! @{ */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400C4000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400C8000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer + * @{ + */ + +/** ADC_ETC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ + __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ + __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ + __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ + } TRIG[8]; +} ADC_ETC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks + * @{ + */ + +/*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ +#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) +#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) +#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) +#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) +#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) +#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) +#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) +#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) +#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) +#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) +#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ + +/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ + +/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ + +/*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ + +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CTRL */ +#define ADC_ETC_TRIGn_CTRL_COUNT (8U) + +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_COUNTER */ +#define ADC_ETC_TRIGn_COUNTER_COUNT (8U) + +/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ +#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) + +/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ +#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) + +/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ +#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) + +/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ +#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) + +/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_1_0 */ +#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) + +/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_3_2 */ +#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) + +/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_5_4 */ +#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) + +/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_7_6 */ +#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) + + +/*! + * @} + */ /* end of group ADC_ETC_Register_Masks */ + + +/* ADC_ETC - Peripheral instance base addresses */ +/** Peripheral ADC_ETC base address */ +#define ADC_ETC_BASE (0x403B0000u) +/** Peripheral ADC_ETC base pointer */ +#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) +/** Array initializer of ADC_ETC peripheral base addresses */ +#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } +/** Array initializer of ADC_ETC peripheral base pointers */ +#define ADC_ETC_BASE_PTRS { ADC_ETC } +/** Interrupt vectors for the ADC_ETC peripheral type */ +#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } +#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } + +/*! + * @} + */ /* end of group ADC_ETC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +/*! @{ */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x4007C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x4017C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x4027C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Peripheral AIPSTZ4 base address */ +#define AIPSTZ4_BASE (0x4037C000u) +/** Peripheral AIPSTZ4 base pointer */ +#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x403B4000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Peripheral AOI2 base address */ +#define AOI2_BASE (0x403B8000u) +/** Peripheral AOI2 base pointer */ +#define AOI2 ((AOI_Type *)AOI2_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BEE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer + * @{ + */ + +/** BEE - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */ + __IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */ + __IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */ + __IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */ + __IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */ + __IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */ + __IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */ + __IO uint32_t STATUS; /**< , offset: 0x1C */ + __O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */ + __O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */ + __O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */ + __O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */ + __O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */ + __O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */ + __O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */ + __O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */ + __IO uint32_t REGION1_TOP; /**< , offset: 0x40 */ + __IO uint32_t REGION1_BOT; /**< , offset: 0x44 */ +} BEE_Type; + +/* ---------------------------------------------------------------------------- + -- BEE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Register_Masks BEE Register Masks + * @{ + */ + +/*! @name CTRL - BEE Control Register */ +/*! @{ */ +#define BEE_CTRL_BEE_ENABLE_MASK (0x1U) +#define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) +#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) +#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) +#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) +#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) +#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) +#define BEE_CTRL_KEY_VALID_MASK (0x10U) +#define BEE_CTRL_KEY_VALID_SHIFT (4U) +#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) +#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) +#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) +#define BEE_CTRL_AC_PROT_EN_MASK (0x40U) +#define BEE_CTRL_AC_PROT_EN_SHIFT (6U) +#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) +#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) +#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) +#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) +#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) +#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) +#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) +#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) +#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) +#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) +#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) +#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) +#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) +#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) +#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) +#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) +#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) +#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) +#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) +#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) +#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) +#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) +#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) +#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET0 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET1 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ + +/*! @name AES_KEY0_W0 - */ +/*! @{ */ +#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) +#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ + +/*! @name AES_KEY0_W1 - */ +/*! @{ */ +#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) +#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ + +/*! @name AES_KEY0_W2 - */ +/*! @{ */ +#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) +#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ + +/*! @name AES_KEY0_W3 - */ +/*! @{ */ +#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) +#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ + +/*! @name STATUS - */ +/*! @{ */ +#define BEE_STATUS_IRQ_VEC_MASK (0xFFU) +#define BEE_STATUS_IRQ_VEC_SHIFT (0U) +#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) +#define BEE_STATUS_BEE_IDLE_MASK (0x100U) +#define BEE_STATUS_BEE_IDLE_SHIFT (8U) +#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) +#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) +#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) +#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) +#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) +#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) +#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) +#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) +#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ + +/*! @name REGION1_TOP - */ +/*! @{ */ +#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) +#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) +#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ + +/*! @name REGION1_BOT - */ +/*! @{ */ +#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) +#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) +#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BEE_Register_Masks */ + + +/* BEE - Peripheral instance base addresses */ +/** Peripheral BEE base address */ +#define BEE_BASE (0x403EC000u) +/** Peripheral BEE base pointer */ +#define BEE ((BEE_Type *)BEE_BASE) +/** Array initializer of BEE peripheral base addresses */ +#define BEE_BASE_ADDRS { BEE_BASE } +/** Array initializer of BEE peripheral base pointers */ +#define BEE_BASE_PTRS { BEE } + +/*! + * @} + */ /* end of group BEE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +/*! @{ */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 Register */ +/*! @{ */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free Running Timer Register */ +/*! @{ */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +/*! @{ */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +/*! @{ */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter Register */ +/*! @{ */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 Register */ +/*! @{ */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +/*! @{ */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @{ */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +/*! @{ */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @{ */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 Register */ +/*! @{ */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - CRC Register */ +/*! @{ */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +/*! @{ */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +/*! @{ */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +/*! @{ */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x401D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x401D4000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_3[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_4[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +/*! @{ */ +#define CCM_CCR_OSCNT_MASK (0xFFU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ + +/*! @name CSR - CCM Status Register */ +/*! @{ */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_CAMP2_READY_MASK (0x8U) +#define CCM_CSR_CAMP2_READY_SHIFT (3U) +#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ + +/*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ + +/*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ +#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) +#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) +#define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) +#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) +#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ + +/*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ + +/*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) +#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) +#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) +#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +/*! @{ */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) +#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ +#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ + +/*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) +#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) +#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ + +/*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ + +/*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ + +/*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) +#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x400FC000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x400D8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ + +/*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ + +/*! @name FPR - CMP Filter Period Register */ +/*! @{ */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ + +/*! @name SCR - CMP Status and Control Register */ +/*! @{ */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ + +/*! @name DACCR - DAC Control Register */ +/*! @{ */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ + +/*! @name MUXCR - MUX Control Register */ +/*! @{ */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40094000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x40094008u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Peripheral CMP3 base address */ +#define CMP3_BASE (0x40094010u) +/** Peripheral CMP3 base pointer */ +#define CMP3 ((CMP_Type *)CMP3_BASE) +/** Peripheral CMP4 base address */ +#define CMP4_BASE (0x40094018u) +/** Peripheral CMP4 base pointer */ +#define CMP4 ((CMP_Type *)CMP4_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +/*! @{ */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U) +#define CSI_CSICR1_CCIR_MODE_SHIFT (27U) +#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) +/*! @} */ + +/*! @name CSICR2 - CSI Control Register 2 */ +/*! @{ */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +/*! @} */ + +/*! @name CSICR3 - CSI Control Register 3 */ +/*! @{ */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) +/*! @} */ + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +/*! @{ */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) +/*! @} */ + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +/*! @{ */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) +/*! @} */ + +/*! @name CSIRXCNT - CSI RX Count Register */ +/*! @{ */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) +/*! @} */ + +/*! @name CSISR - CSI Status Register */ +/*! @{ */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) +/*! @} */ + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +/*! @{ */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/*! @} */ + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +/*! @{ */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/*! @} */ + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @{ */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) +/*! @} */ + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +/*! @{ */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +/*! @} */ + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +/*! @{ */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) +/*! @} */ + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +/*! @{ */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) +/*! @} */ + +/*! @name CSICR18 - CSI Control Register 18 */ +/*! @{ */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) +/*! @} */ + +/*! @name CSICR19 - CSI Control Register 19 */ +/*! @{ */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x402BC000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer + * @{ + */ + +/** CSU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[384]; + __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ + uint8_t RESERVED_2[316]; + __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ +} CSU_Type; + +/* ---------------------------------------------------------------------------- + -- CSU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Register_Masks CSU Register Masks + * @{ + */ + +/*! @name CSL - Config security level register */ +/*! @{ */ +#define CSU_CSL_SUR_S2_MASK (0x1U) +#define CSU_CSL_SUR_S2_SHIFT (0U) +#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) +#define CSU_CSL_SSR_S2_MASK (0x2U) +#define CSU_CSL_SSR_S2_SHIFT (1U) +#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) +#define CSU_CSL_NUR_S2_MASK (0x4U) +#define CSU_CSL_NUR_S2_SHIFT (2U) +#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) +#define CSU_CSL_NSR_S2_MASK (0x8U) +#define CSU_CSL_NSR_S2_SHIFT (3U) +#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) +#define CSU_CSL_SUW_S2_MASK (0x10U) +#define CSU_CSL_SUW_S2_SHIFT (4U) +#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) +#define CSU_CSL_SSW_S2_MASK (0x20U) +#define CSU_CSL_SSW_S2_SHIFT (5U) +#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) +#define CSU_CSL_NUW_S2_MASK (0x40U) +#define CSU_CSL_NUW_S2_SHIFT (6U) +#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) +#define CSU_CSL_NSW_S2_MASK (0x80U) +#define CSU_CSL_NSW_S2_SHIFT (7U) +#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) +#define CSU_CSL_LOCK_S2_MASK (0x100U) +#define CSU_CSL_LOCK_S2_SHIFT (8U) +#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) +#define CSU_CSL_SUR_S1_MASK (0x10000U) +#define CSU_CSL_SUR_S1_SHIFT (16U) +#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) +#define CSU_CSL_SSR_S1_MASK (0x20000U) +#define CSU_CSL_SSR_S1_SHIFT (17U) +#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) +#define CSU_CSL_NUR_S1_MASK (0x40000U) +#define CSU_CSL_NUR_S1_SHIFT (18U) +#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) +#define CSU_CSL_NSR_S1_MASK (0x80000U) +#define CSU_CSL_NSR_S1_SHIFT (19U) +#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) +#define CSU_CSL_SUW_S1_MASK (0x100000U) +#define CSU_CSL_SUW_S1_SHIFT (20U) +#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) +#define CSU_CSL_SSW_S1_MASK (0x200000U) +#define CSU_CSL_SSW_S1_SHIFT (21U) +#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) +#define CSU_CSL_NUW_S1_MASK (0x400000U) +#define CSU_CSL_NUW_S1_SHIFT (22U) +#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) +#define CSU_CSL_NSW_S1_MASK (0x800000U) +#define CSU_CSL_NSW_S1_SHIFT (23U) +#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) +#define CSU_CSL_LOCK_S1_MASK (0x1000000U) +#define CSU_CSL_LOCK_S1_SHIFT (24U) +#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ + +/* The count of CSU_CSL */ +#define CSU_CSL_COUNT (32U) + +/*! @name HP0 - HP0 register */ +/*! @{ */ +#define CSU_HP0_HP_DMA_MASK (0x4U) +#define CSU_HP0_HP_DMA_SHIFT (2U) +#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) +#define CSU_HP0_L_DMA_MASK (0x8U) +#define CSU_HP0_L_DMA_SHIFT (3U) +#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) +#define CSU_HP0_HP_LCDIF_MASK (0x10U) +#define CSU_HP0_HP_LCDIF_SHIFT (4U) +#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) +#define CSU_HP0_L_LCDIF_MASK (0x20U) +#define CSU_HP0_L_LCDIF_SHIFT (5U) +#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) +#define CSU_HP0_HP_CSI_MASK (0x40U) +#define CSU_HP0_HP_CSI_SHIFT (6U) +#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) +#define CSU_HP0_L_CSI_MASK (0x80U) +#define CSU_HP0_L_CSI_SHIFT (7U) +#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) +#define CSU_HP0_HP_PXP_MASK (0x100U) +#define CSU_HP0_HP_PXP_SHIFT (8U) +#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) +#define CSU_HP0_L_PXP_MASK (0x200U) +#define CSU_HP0_L_PXP_SHIFT (9U) +#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) +#define CSU_HP0_HP_DCP_MASK (0x400U) +#define CSU_HP0_HP_DCP_SHIFT (10U) +#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) +#define CSU_HP0_L_DCP_MASK (0x800U) +#define CSU_HP0_L_DCP_SHIFT (11U) +#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) +#define CSU_HP0_HP_ENET_MASK (0x4000U) +#define CSU_HP0_HP_ENET_SHIFT (14U) +#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) +#define CSU_HP0_L_ENET_MASK (0x8000U) +#define CSU_HP0_L_ENET_SHIFT (15U) +#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) +#define CSU_HP0_HP_USDHC1_MASK (0x10000U) +#define CSU_HP0_HP_USDHC1_SHIFT (16U) +#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) +#define CSU_HP0_L_USDHC1_MASK (0x20000U) +#define CSU_HP0_L_USDHC1_SHIFT (17U) +#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) +#define CSU_HP0_HP_USDHC2_MASK (0x40000U) +#define CSU_HP0_HP_USDHC2_SHIFT (18U) +#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) +#define CSU_HP0_L_USDHC2_MASK (0x80000U) +#define CSU_HP0_L_USDHC2_SHIFT (19U) +#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) +#define CSU_HP0_HP_TPSMP_MASK (0x100000U) +#define CSU_HP0_HP_TPSMP_SHIFT (20U) +#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) +#define CSU_HP0_L_TPSMP_MASK (0x200000U) +#define CSU_HP0_L_TPSMP_SHIFT (21U) +#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) +#define CSU_HP0_HP_USB_MASK (0x400000U) +#define CSU_HP0_HP_USB_SHIFT (22U) +#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) +#define CSU_HP0_L_USB_MASK (0x800000U) +#define CSU_HP0_L_USB_SHIFT (23U) +#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ + +/*! @name SA - Secure access register */ +/*! @{ */ +#define CSU_SA_NSA_DMA_MASK (0x4U) +#define CSU_SA_NSA_DMA_SHIFT (2U) +#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) +#define CSU_SA_L_DMA_MASK (0x8U) +#define CSU_SA_L_DMA_SHIFT (3U) +#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) +#define CSU_SA_NSA_LCDIF_MASK (0x10U) +#define CSU_SA_NSA_LCDIF_SHIFT (4U) +#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) +#define CSU_SA_L_LCDIF_MASK (0x20U) +#define CSU_SA_L_LCDIF_SHIFT (5U) +#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) +#define CSU_SA_NSA_CSI_MASK (0x40U) +#define CSU_SA_NSA_CSI_SHIFT (6U) +#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) +#define CSU_SA_L_CSI_MASK (0x80U) +#define CSU_SA_L_CSI_SHIFT (7U) +#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) +#define CSU_SA_NSA_PXP_MASK (0x100U) +#define CSU_SA_NSA_PXP_SHIFT (8U) +#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) +#define CSU_SA_L_PXP_MASK (0x200U) +#define CSU_SA_L_PXP_SHIFT (9U) +#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) +#define CSU_SA_NSA_DCP_MASK (0x400U) +#define CSU_SA_NSA_DCP_SHIFT (10U) +#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) +#define CSU_SA_L_DCP_MASK (0x800U) +#define CSU_SA_L_DCP_SHIFT (11U) +#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) +#define CSU_SA_NSA_ENET_MASK (0x4000U) +#define CSU_SA_NSA_ENET_SHIFT (14U) +#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) +#define CSU_SA_L_ENET_MASK (0x8000U) +#define CSU_SA_L_ENET_SHIFT (15U) +#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) +#define CSU_SA_NSA_USDHC1_MASK (0x10000U) +#define CSU_SA_NSA_USDHC1_SHIFT (16U) +#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) +#define CSU_SA_L_USDHC1_MASK (0x20000U) +#define CSU_SA_L_USDHC1_SHIFT (17U) +#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) +#define CSU_SA_NSA_USDHC2_MASK (0x40000U) +#define CSU_SA_NSA_USDHC2_SHIFT (18U) +#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) +#define CSU_SA_L_USDHC2_MASK (0x80000U) +#define CSU_SA_L_USDHC2_SHIFT (19U) +#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) +#define CSU_SA_NSA_TPSMP_MASK (0x100000U) +#define CSU_SA_NSA_TPSMP_SHIFT (20U) +#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) +#define CSU_SA_L_TPSMP_MASK (0x200000U) +#define CSU_SA_L_TPSMP_SHIFT (21U) +#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) +#define CSU_SA_NSA_USB_MASK (0x400000U) +#define CSU_SA_NSA_USB_SHIFT (22U) +#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) +#define CSU_SA_L_USB_MASK (0x800000U) +#define CSU_SA_L_USB_SHIFT (23U) +#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ + +/*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ +#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) +#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) +#define CSU_HPCONTROL0_L_DMA_MASK (0x8U) +#define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) +#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) +#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) +#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) +#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) +#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) +#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) +#define CSU_HPCONTROL0_L_CSI_MASK (0x80U) +#define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) +#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) +#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) +#define CSU_HPCONTROL0_L_PXP_MASK (0x200U) +#define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) +#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) +#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) +#define CSU_HPCONTROL0_L_DCP_MASK (0x800U) +#define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) +#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) +#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) +#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) +#define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) +#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) +#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) +#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) +#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) +#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) +#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) +#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) +#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) +#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) +#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) +#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) +#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) +#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) +#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) +#define CSU_HPCONTROL0_L_USB_MASK (0x800000U) +#define CSU_HPCONTROL0_L_USB_SHIFT (23U) +#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSU_Register_Masks */ + + +/* CSU - Peripheral instance base addresses */ +/** Peripheral CSU base address */ +#define CSU_BASE (0x400DC000u) +/** Peripheral CSU base pointer */ +#define CSU ((CSU_Type *)CSU_BASE) +/** Array initializer of CSU peripheral base addresses */ +#define CSU_BASE_ADDRS { CSU_BASE } +/** Array initializer of CSU peripheral base pointers */ +#define CSU_BASE_PTRS { CSU } + +/*! + * @} + */ /* end of group CSU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ + __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ + __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ + __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name REG0 - DCDC Register 0 */ +/*! @{ */ +#define DCDC_REG0_PWD_ZCD_MASK (0x1U) +#define DCDC_REG0_PWD_ZCD_SHIFT (0U) +#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) +#define DCDC_REG0_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_SEL_CLK_SHIFT (2U) +#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) +#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) +#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) +#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) +#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) +#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) +#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) +#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) +#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) +#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) +#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) +#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) +#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) +#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) +#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) +#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) +#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) +#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) +#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) +#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) +#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) +#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) +#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) +#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) +#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) +#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) +#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) +#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) +#define DCDC_REG0_STS_DC_OK_SHIFT (31U) +#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ + +/*! @name REG1 - DCDC Register 1 */ +/*! @{ */ +#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) +#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) +#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) +#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) +#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) +#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) +#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) +#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) +#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) +#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) +#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) +#define DCDC_REG1_VBG_TRIM_SHIFT (24U) +#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ + +/*! @name REG2 - DCDC Register 2 */ +/*! @{ */ +#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) +#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) +#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) +#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) +#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) +#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) +#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) +#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) +#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) +#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) +#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) +#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) +#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) +#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) +#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ + +/*! @name REG3 - DCDC Register 3 */ +/*! @{ */ +#define DCDC_REG3_TRG_MASK (0x1FU) +#define DCDC_REG3_TRG_SHIFT (0U) +#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) +#define DCDC_REG3_TARGET_LP_MASK (0x700U) +#define DCDC_REG3_TARGET_LP_SHIFT (8U) +#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) +#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) +#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) +#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) +#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) +#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) +#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK) +#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) +#define DCDC_REG3_DISABLE_STEP_SHIFT (30U) +#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCDC_Register_Masks */ + + +/* DCDC - Peripheral instance base addresses */ +/** Peripheral DCDC base address */ +#define DCDC_BASE (0x40080000u) +/** Peripheral DCDC base pointer */ +#define DCDC ((DCDC_Type *)DCDC_BASE) +/** Array initializer of DCDC peripheral base addresses */ +#define DCDC_BASE_ADDRS { DCDC_BASE } +/** Array initializer of DCDC peripheral base pointers */ +#define DCDC_BASE_PTRS { DCDC } +/** Interrupt vectors for the DCDC peripheral type */ +#define DCDC_IRQS { DCDC_IRQn } + +/*! + * @} + */ /* end of group DCDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - DCP status register */ +/*! @{ */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ + +/*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ + +/*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ + +/*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ + +/*! @name KEY - DCP key index */ +/*! @{ */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ + +/*! @name KEYDATA - DCP key data */ +/*! @{ */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ + +/*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ + +/*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ + +/*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ + +/*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ + +/*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ + +/*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ + +/*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ + +/*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ + +/*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ + +/*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ + +/*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ + +/*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ + +/*! @name DBGDATA - DCP debug data register */ +/*! @{ */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ + +/*! @name PAGETABLE - DCP page table register */ +/*! @{ */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ + +/*! @name VERSION - DCP version register */ +/*! @{ */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x402FC000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ + __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ + __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ + __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ + __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ + __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ + __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ + __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ + __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ + __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ + __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ + __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ + __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ + __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ + __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ + __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ + uint8_t RESERVED_7[3808]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_ERGA_MASK (0x8U) +#define DMA_CR_ERGA_SHIFT (3U) +#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_GRP0PRI_MASK (0x100U) +#define DMA_CR_GRP0PRI_SHIFT (8U) +#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) +#define DMA_CR_GRP1PRI_MASK (0x400U) +#define DMA_CR_GRP1PRI_SHIFT (10U) +#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) +#define DMA_CR_ACTIVE_MASK (0x80000000U) +#define DMA_CR_ACTIVE_SHIFT (31U) +#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Error Status Register */ +/*! @{ */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0x1F00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_GPE_MASK (0x8000U) +#define DMA_ES_GPE_SHIFT (15U) +#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ + +/*! @name ERQ - Enable Request Register */ +/*! @{ */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) +#define DMA_ERQ_ERQ16_MASK (0x10000U) +#define DMA_ERQ_ERQ16_SHIFT (16U) +#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) +#define DMA_ERQ_ERQ17_MASK (0x20000U) +#define DMA_ERQ_ERQ17_SHIFT (17U) +#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) +#define DMA_ERQ_ERQ18_MASK (0x40000U) +#define DMA_ERQ_ERQ18_SHIFT (18U) +#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) +#define DMA_ERQ_ERQ19_MASK (0x80000U) +#define DMA_ERQ_ERQ19_SHIFT (19U) +#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) +#define DMA_ERQ_ERQ20_MASK (0x100000U) +#define DMA_ERQ_ERQ20_SHIFT (20U) +#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) +#define DMA_ERQ_ERQ21_MASK (0x200000U) +#define DMA_ERQ_ERQ21_SHIFT (21U) +#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) +#define DMA_ERQ_ERQ22_MASK (0x400000U) +#define DMA_ERQ_ERQ22_SHIFT (22U) +#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) +#define DMA_ERQ_ERQ23_MASK (0x800000U) +#define DMA_ERQ_ERQ23_SHIFT (23U) +#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) +#define DMA_ERQ_ERQ24_MASK (0x1000000U) +#define DMA_ERQ_ERQ24_SHIFT (24U) +#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) +#define DMA_ERQ_ERQ25_MASK (0x2000000U) +#define DMA_ERQ_ERQ25_SHIFT (25U) +#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) +#define DMA_ERQ_ERQ26_MASK (0x4000000U) +#define DMA_ERQ_ERQ26_SHIFT (26U) +#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) +#define DMA_ERQ_ERQ27_MASK (0x8000000U) +#define DMA_ERQ_ERQ27_SHIFT (27U) +#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) +#define DMA_ERQ_ERQ28_MASK (0x10000000U) +#define DMA_ERQ_ERQ28_SHIFT (28U) +#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) +#define DMA_ERQ_ERQ29_MASK (0x20000000U) +#define DMA_ERQ_ERQ29_SHIFT (29U) +#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) +#define DMA_ERQ_ERQ30_MASK (0x40000000U) +#define DMA_ERQ_ERQ30_SHIFT (30U) +#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) +#define DMA_ERQ_ERQ31_MASK (0x80000000U) +#define DMA_ERQ_ERQ31_SHIFT (31U) +#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ + +/*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) +#define DMA_EEI_EEI16_MASK (0x10000U) +#define DMA_EEI_EEI16_SHIFT (16U) +#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) +#define DMA_EEI_EEI17_MASK (0x20000U) +#define DMA_EEI_EEI17_SHIFT (17U) +#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) +#define DMA_EEI_EEI18_MASK (0x40000U) +#define DMA_EEI_EEI18_SHIFT (18U) +#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) +#define DMA_EEI_EEI19_MASK (0x80000U) +#define DMA_EEI_EEI19_SHIFT (19U) +#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) +#define DMA_EEI_EEI20_MASK (0x100000U) +#define DMA_EEI_EEI20_SHIFT (20U) +#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) +#define DMA_EEI_EEI21_MASK (0x200000U) +#define DMA_EEI_EEI21_SHIFT (21U) +#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) +#define DMA_EEI_EEI22_MASK (0x400000U) +#define DMA_EEI_EEI22_SHIFT (22U) +#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) +#define DMA_EEI_EEI23_MASK (0x800000U) +#define DMA_EEI_EEI23_SHIFT (23U) +#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) +#define DMA_EEI_EEI24_MASK (0x1000000U) +#define DMA_EEI_EEI24_SHIFT (24U) +#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) +#define DMA_EEI_EEI25_MASK (0x2000000U) +#define DMA_EEI_EEI25_SHIFT (25U) +#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) +#define DMA_EEI_EEI26_MASK (0x4000000U) +#define DMA_EEI_EEI26_SHIFT (26U) +#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) +#define DMA_EEI_EEI27_MASK (0x8000000U) +#define DMA_EEI_EEI27_SHIFT (27U) +#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) +#define DMA_EEI_EEI28_MASK (0x10000000U) +#define DMA_EEI_EEI28_SHIFT (28U) +#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) +#define DMA_EEI_EEI29_MASK (0x20000000U) +#define DMA_EEI_EEI29_SHIFT (29U) +#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) +#define DMA_EEI_EEI30_MASK (0x40000000U) +#define DMA_EEI_EEI30_SHIFT (30U) +#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) +#define DMA_EEI_EEI31_MASK (0x80000000U) +#define DMA_EEI_EEI31_SHIFT (31U) +#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_CEEI_CEEI_MASK (0x1FU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ + +/*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_SEEI_SEEI_MASK (0x1FU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ + +/*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ +#define DMA_CERQ_CERQ_MASK (0x1FU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ + +/*! @name SERQ - Set Enable Request Register */ +/*! @{ */ +#define DMA_SERQ_SERQ_MASK (0x1FU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ + +/*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ +#define DMA_CDNE_CDNE_MASK (0x1FU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ + +/*! @name SSRT - Set START Bit Register */ +/*! @{ */ +#define DMA_SSRT_SSRT_MASK (0x1FU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ + +/*! @name CERR - Clear Error Register */ +/*! @{ */ +#define DMA_CERR_CERR_MASK (0x1FU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ + +/*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ +#define DMA_CINT_CINT_MASK (0x1FU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ + +/*! @name INT - Interrupt Request Register */ +/*! @{ */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) +#define DMA_INT_INT16_MASK (0x10000U) +#define DMA_INT_INT16_SHIFT (16U) +#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) +#define DMA_INT_INT17_MASK (0x20000U) +#define DMA_INT_INT17_SHIFT (17U) +#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) +#define DMA_INT_INT18_MASK (0x40000U) +#define DMA_INT_INT18_SHIFT (18U) +#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) +#define DMA_INT_INT19_MASK (0x80000U) +#define DMA_INT_INT19_SHIFT (19U) +#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) +#define DMA_INT_INT20_MASK (0x100000U) +#define DMA_INT_INT20_SHIFT (20U) +#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) +#define DMA_INT_INT21_MASK (0x200000U) +#define DMA_INT_INT21_SHIFT (21U) +#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) +#define DMA_INT_INT22_MASK (0x400000U) +#define DMA_INT_INT22_SHIFT (22U) +#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) +#define DMA_INT_INT23_MASK (0x800000U) +#define DMA_INT_INT23_SHIFT (23U) +#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) +#define DMA_INT_INT24_MASK (0x1000000U) +#define DMA_INT_INT24_SHIFT (24U) +#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) +#define DMA_INT_INT25_MASK (0x2000000U) +#define DMA_INT_INT25_SHIFT (25U) +#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) +#define DMA_INT_INT26_MASK (0x4000000U) +#define DMA_INT_INT26_SHIFT (26U) +#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) +#define DMA_INT_INT27_MASK (0x8000000U) +#define DMA_INT_INT27_SHIFT (27U) +#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) +#define DMA_INT_INT28_MASK (0x10000000U) +#define DMA_INT_INT28_SHIFT (28U) +#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) +#define DMA_INT_INT29_MASK (0x20000000U) +#define DMA_INT_INT29_SHIFT (29U) +#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) +#define DMA_INT_INT30_MASK (0x40000000U) +#define DMA_INT_INT30_SHIFT (30U) +#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) +#define DMA_INT_INT31_MASK (0x80000000U) +#define DMA_INT_INT31_SHIFT (31U) +#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ + +/*! @name ERR - Error Register */ +/*! @{ */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) +#define DMA_ERR_ERR16_MASK (0x10000U) +#define DMA_ERR_ERR16_SHIFT (16U) +#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) +#define DMA_ERR_ERR17_MASK (0x20000U) +#define DMA_ERR_ERR17_SHIFT (17U) +#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) +#define DMA_ERR_ERR18_MASK (0x40000U) +#define DMA_ERR_ERR18_SHIFT (18U) +#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) +#define DMA_ERR_ERR19_MASK (0x80000U) +#define DMA_ERR_ERR19_SHIFT (19U) +#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) +#define DMA_ERR_ERR20_MASK (0x100000U) +#define DMA_ERR_ERR20_SHIFT (20U) +#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) +#define DMA_ERR_ERR21_MASK (0x200000U) +#define DMA_ERR_ERR21_SHIFT (21U) +#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) +#define DMA_ERR_ERR22_MASK (0x400000U) +#define DMA_ERR_ERR22_SHIFT (22U) +#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) +#define DMA_ERR_ERR23_MASK (0x800000U) +#define DMA_ERR_ERR23_SHIFT (23U) +#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) +#define DMA_ERR_ERR24_MASK (0x1000000U) +#define DMA_ERR_ERR24_SHIFT (24U) +#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) +#define DMA_ERR_ERR25_MASK (0x2000000U) +#define DMA_ERR_ERR25_SHIFT (25U) +#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) +#define DMA_ERR_ERR26_MASK (0x4000000U) +#define DMA_ERR_ERR26_SHIFT (26U) +#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) +#define DMA_ERR_ERR27_MASK (0x8000000U) +#define DMA_ERR_ERR27_SHIFT (27U) +#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) +#define DMA_ERR_ERR28_MASK (0x10000000U) +#define DMA_ERR_ERR28_SHIFT (28U) +#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) +#define DMA_ERR_ERR29_MASK (0x20000000U) +#define DMA_ERR_ERR29_SHIFT (29U) +#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) +#define DMA_ERR_ERR30_MASK (0x40000000U) +#define DMA_ERR_ERR30_SHIFT (30U) +#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) +#define DMA_ERR_ERR31_MASK (0x80000000U) +#define DMA_ERR_ERR31_SHIFT (31U) +#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ + +/*! @name HRS - Hardware Request Status Register */ +/*! @{ */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) +#define DMA_HRS_HRS16_MASK (0x10000U) +#define DMA_HRS_HRS16_SHIFT (16U) +#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) +#define DMA_HRS_HRS17_MASK (0x20000U) +#define DMA_HRS_HRS17_SHIFT (17U) +#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) +#define DMA_HRS_HRS18_MASK (0x40000U) +#define DMA_HRS_HRS18_SHIFT (18U) +#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) +#define DMA_HRS_HRS19_MASK (0x80000U) +#define DMA_HRS_HRS19_SHIFT (19U) +#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) +#define DMA_HRS_HRS20_MASK (0x100000U) +#define DMA_HRS_HRS20_SHIFT (20U) +#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) +#define DMA_HRS_HRS21_MASK (0x200000U) +#define DMA_HRS_HRS21_SHIFT (21U) +#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) +#define DMA_HRS_HRS22_MASK (0x400000U) +#define DMA_HRS_HRS22_SHIFT (22U) +#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) +#define DMA_HRS_HRS23_MASK (0x800000U) +#define DMA_HRS_HRS23_SHIFT (23U) +#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) +#define DMA_HRS_HRS24_MASK (0x1000000U) +#define DMA_HRS_HRS24_SHIFT (24U) +#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) +#define DMA_HRS_HRS25_MASK (0x2000000U) +#define DMA_HRS_HRS25_SHIFT (25U) +#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) +#define DMA_HRS_HRS26_MASK (0x4000000U) +#define DMA_HRS_HRS26_SHIFT (26U) +#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) +#define DMA_HRS_HRS27_MASK (0x8000000U) +#define DMA_HRS_HRS27_SHIFT (27U) +#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) +#define DMA_HRS_HRS28_MASK (0x10000000U) +#define DMA_HRS_HRS28_SHIFT (28U) +#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) +#define DMA_HRS_HRS29_MASK (0x20000000U) +#define DMA_HRS_HRS29_SHIFT (29U) +#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) +#define DMA_HRS_HRS30_MASK (0x40000000U) +#define DMA_HRS_HRS30_SHIFT (30U) +#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) +#define DMA_HRS_HRS31_MASK (0x80000000U) +#define DMA_HRS_HRS31_SHIFT (31U) +#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ + +/*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) +#define DMA_EARS_EDREQ_16_MASK (0x10000U) +#define DMA_EARS_EDREQ_16_SHIFT (16U) +#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) +#define DMA_EARS_EDREQ_17_MASK (0x20000U) +#define DMA_EARS_EDREQ_17_SHIFT (17U) +#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) +#define DMA_EARS_EDREQ_18_MASK (0x40000U) +#define DMA_EARS_EDREQ_18_SHIFT (18U) +#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) +#define DMA_EARS_EDREQ_19_MASK (0x80000U) +#define DMA_EARS_EDREQ_19_SHIFT (19U) +#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) +#define DMA_EARS_EDREQ_20_MASK (0x100000U) +#define DMA_EARS_EDREQ_20_SHIFT (20U) +#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) +#define DMA_EARS_EDREQ_21_MASK (0x200000U) +#define DMA_EARS_EDREQ_21_SHIFT (21U) +#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) +#define DMA_EARS_EDREQ_22_MASK (0x400000U) +#define DMA_EARS_EDREQ_22_SHIFT (22U) +#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) +#define DMA_EARS_EDREQ_23_MASK (0x800000U) +#define DMA_EARS_EDREQ_23_SHIFT (23U) +#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) +#define DMA_EARS_EDREQ_24_MASK (0x1000000U) +#define DMA_EARS_EDREQ_24_SHIFT (24U) +#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) +#define DMA_EARS_EDREQ_25_MASK (0x2000000U) +#define DMA_EARS_EDREQ_25_SHIFT (25U) +#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) +#define DMA_EARS_EDREQ_26_MASK (0x4000000U) +#define DMA_EARS_EDREQ_26_SHIFT (26U) +#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) +#define DMA_EARS_EDREQ_27_MASK (0x8000000U) +#define DMA_EARS_EDREQ_27_SHIFT (27U) +#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) +#define DMA_EARS_EDREQ_28_MASK (0x10000000U) +#define DMA_EARS_EDREQ_28_SHIFT (28U) +#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) +#define DMA_EARS_EDREQ_29_MASK (0x20000000U) +#define DMA_EARS_EDREQ_29_SHIFT (29U) +#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) +#define DMA_EARS_EDREQ_30_MASK (0x40000000U) +#define DMA_EARS_EDREQ_30_SHIFT (30U) +#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) +#define DMA_EARS_EDREQ_31_MASK (0x80000000U) +#define DMA_EARS_EDREQ_31_SHIFT (31U) +#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ + +/*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI19_CHPRI_MASK (0xFU) +#define DMA_DCHPRI19_CHPRI_SHIFT (0U) +#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) +#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) +#define DMA_DCHPRI19_DPA_MASK (0x40U) +#define DMA_DCHPRI19_DPA_SHIFT (6U) +#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) +#define DMA_DCHPRI19_ECP_MASK (0x80U) +#define DMA_DCHPRI19_ECP_SHIFT (7U) +#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI18_CHPRI_MASK (0xFU) +#define DMA_DCHPRI18_CHPRI_SHIFT (0U) +#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) +#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) +#define DMA_DCHPRI18_DPA_MASK (0x40U) +#define DMA_DCHPRI18_DPA_SHIFT (6U) +#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) +#define DMA_DCHPRI18_ECP_MASK (0x80U) +#define DMA_DCHPRI18_ECP_SHIFT (7U) +#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI17_CHPRI_MASK (0xFU) +#define DMA_DCHPRI17_CHPRI_SHIFT (0U) +#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) +#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) +#define DMA_DCHPRI17_DPA_MASK (0x40U) +#define DMA_DCHPRI17_DPA_SHIFT (6U) +#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) +#define DMA_DCHPRI17_ECP_MASK (0x80U) +#define DMA_DCHPRI17_ECP_SHIFT (7U) +#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI16_CHPRI_MASK (0xFU) +#define DMA_DCHPRI16_CHPRI_SHIFT (0U) +#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) +#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) +#define DMA_DCHPRI16_DPA_MASK (0x40U) +#define DMA_DCHPRI16_DPA_SHIFT (6U) +#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) +#define DMA_DCHPRI16_ECP_MASK (0x80U) +#define DMA_DCHPRI16_ECP_SHIFT (7U) +#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI23_CHPRI_MASK (0xFU) +#define DMA_DCHPRI23_CHPRI_SHIFT (0U) +#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) +#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) +#define DMA_DCHPRI23_DPA_MASK (0x40U) +#define DMA_DCHPRI23_DPA_SHIFT (6U) +#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) +#define DMA_DCHPRI23_ECP_MASK (0x80U) +#define DMA_DCHPRI23_ECP_SHIFT (7U) +#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI22_CHPRI_MASK (0xFU) +#define DMA_DCHPRI22_CHPRI_SHIFT (0U) +#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) +#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) +#define DMA_DCHPRI22_DPA_MASK (0x40U) +#define DMA_DCHPRI22_DPA_SHIFT (6U) +#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) +#define DMA_DCHPRI22_ECP_MASK (0x80U) +#define DMA_DCHPRI22_ECP_SHIFT (7U) +#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI21_CHPRI_MASK (0xFU) +#define DMA_DCHPRI21_CHPRI_SHIFT (0U) +#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) +#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) +#define DMA_DCHPRI21_DPA_MASK (0x40U) +#define DMA_DCHPRI21_DPA_SHIFT (6U) +#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) +#define DMA_DCHPRI21_ECP_MASK (0x80U) +#define DMA_DCHPRI21_ECP_SHIFT (7U) +#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI20_CHPRI_MASK (0xFU) +#define DMA_DCHPRI20_CHPRI_SHIFT (0U) +#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) +#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) +#define DMA_DCHPRI20_DPA_MASK (0x40U) +#define DMA_DCHPRI20_DPA_SHIFT (6U) +#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) +#define DMA_DCHPRI20_ECP_MASK (0x80U) +#define DMA_DCHPRI20_ECP_SHIFT (7U) +#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI27_CHPRI_MASK (0xFU) +#define DMA_DCHPRI27_CHPRI_SHIFT (0U) +#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) +#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) +#define DMA_DCHPRI27_DPA_MASK (0x40U) +#define DMA_DCHPRI27_DPA_SHIFT (6U) +#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) +#define DMA_DCHPRI27_ECP_MASK (0x80U) +#define DMA_DCHPRI27_ECP_SHIFT (7U) +#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI26_CHPRI_MASK (0xFU) +#define DMA_DCHPRI26_CHPRI_SHIFT (0U) +#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) +#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) +#define DMA_DCHPRI26_DPA_MASK (0x40U) +#define DMA_DCHPRI26_DPA_SHIFT (6U) +#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) +#define DMA_DCHPRI26_ECP_MASK (0x80U) +#define DMA_DCHPRI26_ECP_SHIFT (7U) +#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI25_CHPRI_MASK (0xFU) +#define DMA_DCHPRI25_CHPRI_SHIFT (0U) +#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) +#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) +#define DMA_DCHPRI25_DPA_MASK (0x40U) +#define DMA_DCHPRI25_DPA_SHIFT (6U) +#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) +#define DMA_DCHPRI25_ECP_MASK (0x80U) +#define DMA_DCHPRI25_ECP_SHIFT (7U) +#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI24_CHPRI_MASK (0xFU) +#define DMA_DCHPRI24_CHPRI_SHIFT (0U) +#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) +#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) +#define DMA_DCHPRI24_DPA_MASK (0x40U) +#define DMA_DCHPRI24_DPA_SHIFT (6U) +#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) +#define DMA_DCHPRI24_ECP_MASK (0x80U) +#define DMA_DCHPRI24_ECP_SHIFT (7U) +#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI31_CHPRI_MASK (0xFU) +#define DMA_DCHPRI31_CHPRI_SHIFT (0U) +#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) +#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) +#define DMA_DCHPRI31_DPA_MASK (0x40U) +#define DMA_DCHPRI31_DPA_SHIFT (6U) +#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) +#define DMA_DCHPRI31_ECP_MASK (0x80U) +#define DMA_DCHPRI31_ECP_SHIFT (7U) +#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI30_CHPRI_MASK (0xFU) +#define DMA_DCHPRI30_CHPRI_SHIFT (0U) +#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) +#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) +#define DMA_DCHPRI30_DPA_MASK (0x40U) +#define DMA_DCHPRI30_DPA_SHIFT (6U) +#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) +#define DMA_DCHPRI30_ECP_MASK (0x80U) +#define DMA_DCHPRI30_ECP_SHIFT (7U) +#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI29_CHPRI_MASK (0xFU) +#define DMA_DCHPRI29_CHPRI_SHIFT (0U) +#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) +#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) +#define DMA_DCHPRI29_DPA_MASK (0x40U) +#define DMA_DCHPRI29_DPA_SHIFT (6U) +#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) +#define DMA_DCHPRI29_ECP_MASK (0x80U) +#define DMA_DCHPRI29_ECP_SHIFT (7U) +#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI28_CHPRI_MASK (0xFU) +#define DMA_DCHPRI28_CHPRI_SHIFT (0U) +#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) +#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) +#define DMA_DCHPRI28_DPA_MASK (0x40U) +#define DMA_DCHPRI28_DPA_SHIFT (6U) +#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) +#define DMA_DCHPRI28_ECP_MASK (0x80U) +#define DMA_DCHPRI28_ECP_SHIFT (7U) +#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ + +/*! @name SADDR - TCD Source Address */ +/*! @{ */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (32U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (32U) + +/*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (32U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (32U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (32U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (32U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (32U) + +/*! @name DADDR - TCD Destination Address */ +/*! @{ */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (32U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (32U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (32U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (32U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (32U) + +/*! @name CSR - TCD Control and Status */ +/*! @{ */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (32U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (32U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (32U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x400E8000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } +#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) +#define DMAMUX_CHCFG_A_ON_SHIFT (29U) +#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) +#define DMAMUX_CHCFG_TRIG_SHIFT (30U) +#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) +#define DMAMUX_CHCFG_ENBL_SHIFT (31U) +#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (32U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x400EC000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer + * @{ + */ + +/** ENC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ + __IO uint16_t TST; /**< Test Register, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ +} ENC_Type; + +/* ---------------------------------------------------------------------------- + -- ENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Register_Masks ENC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define ENC_CTRL_CMPIE_MASK (0x1U) +#define ENC_CTRL_CMPIE_SHIFT (0U) +#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) +#define ENC_CTRL_CMPIRQ_MASK (0x2U) +#define ENC_CTRL_CMPIRQ_SHIFT (1U) +#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL_WDE_MASK (0x4U) +#define ENC_CTRL_WDE_SHIFT (2U) +#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) +#define ENC_CTRL_DIE_MASK (0x8U) +#define ENC_CTRL_DIE_SHIFT (3U) +#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) +#define ENC_CTRL_DIRQ_MASK (0x10U) +#define ENC_CTRL_DIRQ_SHIFT (4U) +#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) +#define ENC_CTRL_XNE_MASK (0x20U) +#define ENC_CTRL_XNE_SHIFT (5U) +#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) +#define ENC_CTRL_XIP_MASK (0x40U) +#define ENC_CTRL_XIP_SHIFT (6U) +#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) +#define ENC_CTRL_XIE_MASK (0x80U) +#define ENC_CTRL_XIE_SHIFT (7U) +#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) +#define ENC_CTRL_XIRQ_MASK (0x100U) +#define ENC_CTRL_XIRQ_SHIFT (8U) +#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) +#define ENC_CTRL_PH1_MASK (0x200U) +#define ENC_CTRL_PH1_SHIFT (9U) +#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) +#define ENC_CTRL_REV_MASK (0x400U) +#define ENC_CTRL_REV_SHIFT (10U) +#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) +#define ENC_CTRL_SWIP_MASK (0x800U) +#define ENC_CTRL_SWIP_SHIFT (11U) +#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) +#define ENC_CTRL_HNE_MASK (0x1000U) +#define ENC_CTRL_HNE_SHIFT (12U) +#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) +#define ENC_CTRL_HIP_MASK (0x2000U) +#define ENC_CTRL_HIP_SHIFT (13U) +#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) +#define ENC_CTRL_HIE_MASK (0x4000U) +#define ENC_CTRL_HIE_SHIFT (14U) +#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) +#define ENC_CTRL_HIRQ_MASK (0x8000U) +#define ENC_CTRL_HIRQ_SHIFT (15U) +#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ +#define ENC_FILT_FILT_PER_MASK (0xFFU) +#define ENC_FILT_FILT_PER_SHIFT (0U) +#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) +#define ENC_FILT_FILT_CNT_MASK (0x700U) +#define ENC_FILT_FILT_CNT_SHIFT (8U) +#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ +#define ENC_WTR_WDOG_MASK (0xFFFFU) +#define ENC_WTR_WDOG_SHIFT (0U) +#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ +#define ENC_POSD_POSD_MASK (0xFFFFU) +#define ENC_POSD_POSD_SHIFT (0U) +#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ +#define ENC_POSDH_POSDH_MASK (0xFFFFU) +#define ENC_POSDH_POSDH_SHIFT (0U) +#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ +#define ENC_REV_REV_MASK (0xFFFFU) +#define ENC_REV_REV_SHIFT (0U) +#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ +#define ENC_REVH_REVH_MASK (0xFFFFU) +#define ENC_REVH_REVH_SHIFT (0U) +#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ +#define ENC_UPOS_POS_MASK (0xFFFFU) +#define ENC_UPOS_POS_SHIFT (0U) +#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ +#define ENC_LPOS_POS_MASK (0xFFFFU) +#define ENC_LPOS_POS_SHIFT (0U) +#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ +#define ENC_UPOSH_POSH_MASK (0xFFFFU) +#define ENC_UPOSH_POSH_SHIFT (0U) +#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ +#define ENC_LPOSH_POSH_MASK (0xFFFFU) +#define ENC_LPOSH_POSH_SHIFT (0U) +#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ +#define ENC_UINIT_INIT_MASK (0xFFFFU) +#define ENC_UINIT_INIT_SHIFT (0U) +#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ +#define ENC_LINIT_INIT_MASK (0xFFFFU) +#define ENC_LINIT_INIT_SHIFT (0U) +#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ +#define ENC_IMR_HOME_MASK (0x1U) +#define ENC_IMR_HOME_SHIFT (0U) +#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) +#define ENC_IMR_INDEX_MASK (0x2U) +#define ENC_IMR_INDEX_SHIFT (1U) +#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) +#define ENC_IMR_PHB_MASK (0x4U) +#define ENC_IMR_PHB_SHIFT (2U) +#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) +#define ENC_IMR_PHA_MASK (0x8U) +#define ENC_IMR_PHA_SHIFT (3U) +#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) +#define ENC_IMR_FHOM_MASK (0x10U) +#define ENC_IMR_FHOM_SHIFT (4U) +#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) +#define ENC_IMR_FIND_MASK (0x20U) +#define ENC_IMR_FIND_SHIFT (5U) +#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) +#define ENC_IMR_FPHB_MASK (0x40U) +#define ENC_IMR_FPHB_SHIFT (6U) +#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) +#define ENC_IMR_FPHA_MASK (0x80U) +#define ENC_IMR_FPHA_SHIFT (7U) +#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ +#define ENC_TST_TEST_COUNT_MASK (0xFFU) +#define ENC_TST_TEST_COUNT_SHIFT (0U) +#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) +#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) +#define ENC_TST_TEST_PERIOD_SHIFT (8U) +#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) +#define ENC_TST_QDN_MASK (0x2000U) +#define ENC_TST_QDN_SHIFT (13U) +#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) +#define ENC_TST_TCE_MASK (0x4000U) +#define ENC_TST_TCE_SHIFT (14U) +#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) +#define ENC_TST_TEN_MASK (0x8000U) +#define ENC_TST_TEN_SHIFT (15U) +#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define ENC_CTRL2_UPDHLD_MASK (0x1U) +#define ENC_CTRL2_UPDHLD_SHIFT (0U) +#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) +#define ENC_CTRL2_UPDPOS_MASK (0x2U) +#define ENC_CTRL2_UPDPOS_SHIFT (1U) +#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) +#define ENC_CTRL2_MOD_MASK (0x4U) +#define ENC_CTRL2_MOD_SHIFT (2U) +#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) +#define ENC_CTRL2_DIR_MASK (0x8U) +#define ENC_CTRL2_DIR_SHIFT (3U) +#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) +#define ENC_CTRL2_RUIE_MASK (0x10U) +#define ENC_CTRL2_RUIE_SHIFT (4U) +#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) +#define ENC_CTRL2_RUIRQ_MASK (0x20U) +#define ENC_CTRL2_RUIRQ_SHIFT (5U) +#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) +#define ENC_CTRL2_ROIE_MASK (0x40U) +#define ENC_CTRL2_ROIE_SHIFT (6U) +#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) +#define ENC_CTRL2_ROIRQ_MASK (0x80U) +#define ENC_CTRL2_ROIRQ_SHIFT (7U) +#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) +#define ENC_CTRL2_REVMOD_MASK (0x100U) +#define ENC_CTRL2_REVMOD_SHIFT (8U) +#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) +#define ENC_CTRL2_OUTCTL_MASK (0x200U) +#define ENC_CTRL2_OUTCTL_SHIFT (9U) +#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) +#define ENC_CTRL2_SABIE_MASK (0x400U) +#define ENC_CTRL2_SABIE_SHIFT (10U) +#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) +#define ENC_CTRL2_SABIRQ_MASK (0x800U) +#define ENC_CTRL2_SABIRQ_SHIFT (11U) +#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ +#define ENC_UMOD_MOD_MASK (0xFFFFU) +#define ENC_UMOD_MOD_SHIFT (0U) +#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ +#define ENC_LMOD_MOD_MASK (0xFFFFU) +#define ENC_LMOD_MOD_SHIFT (0U) +#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ +#define ENC_UCOMP_COMP_MASK (0xFFFFU) +#define ENC_UCOMP_COMP_SHIFT (0U) +#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ +#define ENC_LCOMP_COMP_MASK (0xFFFFU) +#define ENC_LCOMP_COMP_SHIFT (0U) +#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ENC_Register_Masks */ + + +/* ENC - Peripheral instance base addresses */ +/** Peripheral ENC1 base address */ +#define ENC1_BASE (0x403C8000u) +/** Peripheral ENC1 base pointer */ +#define ENC1 ((ENC_Type *)ENC1_BASE) +/** Peripheral ENC2 base address */ +#define ENC2_BASE (0x403CC000u) +/** Peripheral ENC2 base pointer */ +#define ENC2 ((ENC_Type *)ENC2_BASE) +/** Peripheral ENC3 base address */ +#define ENC3_BASE (0x403D0000u) +/** Peripheral ENC3 base pointer */ +#define ENC3 ((ENC_Type *)ENC3_BASE) +/** Peripheral ENC4 base address */ +#define ENC4_BASE (0x403D4000u) +/** Peripheral ENC4 base pointer */ +#define ENC4 ((ENC_Type *)ENC4_BASE) +/** Array initializer of ENC peripheral base addresses */ +#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE } +/** Array initializer of ENC peripheral base pointers */ +#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 } +/** Interrupt vectors for the ENC peripheral type */ +#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } + +/*! + * @} + */ /* end of group ENC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x402D8000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn } +#define ENET_Error_IRQS { ENET_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service Register */ +/*! @{ */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low Register */ +/*! @{ */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High Register */ +/*! @{ */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x400B4000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_5[240]; + __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_12[368]; + __IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_14[112]; + __IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FlexIO Control Register */ +/*! @{ */ +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State Register */ +/*! @{ */ +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (4U) + +/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (4U) + +/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (4U) + +/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (4U) + +/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (4U) + +/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (4U) + +/*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (4U) + +/*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (4U) + +/*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (4U) + +/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (4U) + +/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (4U) + +/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (4U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x401AC000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Peripheral FLEXIO2 base address */ +#define FLEXIO2_BASE (0x401B0000u) +/** Peripheral FLEXIO2 base pointer */ +#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer + * @{ + */ + +/** FLEXRAM - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ + __IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */ + __IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */ + __IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */ + __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ + __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ +} FLEXRAM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks + * @{ + */ + +/*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) +#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) +#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) +#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) +/*! @} */ + +/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ +/*! @{ */ +#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) +#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) +#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) +#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU) +#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) +#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) +#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) +#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) +#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ + +/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ +/*! @{ */ +#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) +#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) +#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) +#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) +#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) +#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) +#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) +#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) +#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ + +/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ +/*! @{ */ +#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) +#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) +#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) +#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) +#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) +#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) +#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) +#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) +#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) +#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) +#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) +#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) +#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) +#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) +#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) +#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) +#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) +#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) +#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) +/*! @} */ + +/*! @name INT_STAT_EN - Interrupt Status Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) +#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) +#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) +#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) +#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) +#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) +#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) +#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) +#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) +#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) +#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) +#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) +#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) +#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) +#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) +#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) +#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXRAM_Register_Masks */ + + +/* FLEXRAM - Peripheral instance base addresses */ +/** Peripheral FLEXRAM base address */ +#define FLEXRAM_BASE (0x400B0000u) +/** Peripheral FLEXRAM base pointer */ +#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) +/** Array initializer of FLEXRAM peripheral base addresses */ +#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } +/** Array initializer of FLEXRAM peripheral base pointers */ +#define FLEXRAM_BASE_PTRS { FLEXRAM } +/** Interrupt vectors for the FLEXRAM peripheral type */ +#define FLEXRAM_IRQS { FLEXRAM_IRQn } + +/*! + * @} + */ /* end of group FLEXRAM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[48]; + __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + uint8_t RESERVED_4[4]; + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_6[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Register */ +/*! @{ */ +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control Register */ +/*! @{ */ +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) + +/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command Register */ +/*! @{ */ +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status Register 0 */ +/*! @{ */ +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ + +/*! @name STS1 - Status Register 1 */ +/*! @{ */ +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status Register 2 */ +/*! @{ */ +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI base address */ +#define FLEXSPI_BASE (0x402A8000u) +/** Peripheral FLEXSPI base pointer */ +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI_IRQn } +/* FlexSPI AMBA address. */ +#define FlexSPI_AMBA_BASE (0x60000000U) +/* FlexSPI ASFM address. */ +#define FlexSPI_ASFM_BASE (0x00000000U) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI_ARDF_BASE (0x7FC00000U) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI_ATDF_BASE (0x7F800000U) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */ + __I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +/*! @{ */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) +#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + +/*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ +#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) +#define GPC_IMR5_IMR5_SHIFT (0U) +#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ + +/*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ +#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR5_ISR4_SHIFT (0U) +#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x400F4000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x401B8000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x401BC000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x401C0000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x401C4000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x400C0000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +/*! @{ */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ + +/*! @name PR - GPT Prescaler Register */ +/*! @{ */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ + +/*! @name SR - GPT Status Register */ +/*! @{ */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ + +/*! @name IR - GPT Interrupt Register */ +/*! @{ */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +/*! @{ */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x401EC000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x401F0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ + __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[16]; + __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ + __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0xF0000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) +#define I2S_TCR3_CFR_MASK (0xF000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (4U) + +/*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (4U) + +/*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0xF0000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) +#define I2S_RCR3_CFR_MASK (0xF000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - SAI Receive Data Register */ +/*! @{ */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (4U) + +/*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (4U) + +/*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x40384000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x40388000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x4038C000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) + +/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (154U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x401F8000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ + __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ + __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ + uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ + __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ + __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ + uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ + __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ + __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ + __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ + __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ + __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ + __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ + __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ + __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ + __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ + +/*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +/*! @} */ + +/*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ + +/*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ + +/*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ + +/*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ + +/*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +/*! @} */ + +/*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) +#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) +#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) +#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) +#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ + +/*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ + +/*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) +#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) +#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) +#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) +/*! @} */ + +/*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ + +/*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ + +/*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ + +/*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ + +/*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ + +/*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ + +/*! @name GPR23 - GPR23 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ + +/*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK) +/*! @} */ + +/*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x400AC000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */ + __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */ + __IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */ + __IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */ + __IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x400A8000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ +} IOMUXC_SNVS_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks + * @{ + */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */ + + +/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS_GPR base address */ +#define IOMUXC_SNVS_GPR_BASE (0x400A4000u) +/** Peripheral IOMUXC_SNVS_GPR base pointer */ +#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) +/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */ +#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } +/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */ +#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +/*! @{ */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ + +/*! @name KPSR - Keypad Status Register */ +/*! @{ */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ + +/*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ + +/*! @name KPDR - Keypad Data Register */ +/*! @{ */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x401FC000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[28]; + __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_6[220]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_8[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_9[76]; + __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_10[380]; + __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ + __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ + __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */ + __IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */ + __IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */ + __IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */ + __IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */ + __IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */ + __IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */ + __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */ + __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */ + __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */ + uint8_t RESERVED_11[1104]; + struct { /* offset: 0x800, array step: 0x40 */ + __IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */ + uint8_t RESERVED_2[28]; + } PIGEON[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */ + uint8_t RESERVED_12[12]; + __IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */ + uint8_t RESERVED_13[12]; + __IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */ + uint8_t RESERVED_14[12]; + __IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */ + uint8_t RESERVED_15[12]; + __IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL1 - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_SET - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_CLR - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_TOG - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL2 - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_SET - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_CLR - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_TOG - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) +/*! @} */ + +/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @{ */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/*! @} */ + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +/*! @{ */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) +/*! @} */ + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +/*! @{ */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @{ */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/*! @} */ + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +/*! @{ */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/*! @} */ + +/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @{ */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) +/*! @} */ + +/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @{ */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/*! @} */ + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +/*! @{ */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) +/*! @} */ + +/*! @name CRC_STAT - CRC Status Register */ +/*! @{ */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) +/*! @} */ + +/*! @name STAT - LCD Interface Status Register */ +/*! @{ */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) +#define LCDIF_STAT_DMA_REQ_SHIFT (30U) +#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) +/*! @} */ + +/*! @name THRES - LCDIF Threshold Register */ +/*! @{ */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEON_0 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_0_EN_MASK (0x1U) +#define LCDIF_PIGEON_0_EN_SHIFT (0U) +#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) +#define LCDIF_PIGEON_0_POL_MASK (0x2U) +#define LCDIF_PIGEON_0_POL_SHIFT (1U) +#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) +#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) +#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) +#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) +#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) +#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) +#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) +#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) +#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) +#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) +#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) +#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) +#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_0 */ +#define LCDIF_PIGEON_0_COUNT (12U) + +/*! @name PIGEON_1 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) +#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) +#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) +#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) +#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) +#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_1 */ +#define LCDIF_PIGEON_1_COUNT (12U) + +/*! @name PIGEON_2 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) +#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) +#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) +#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) +#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) +#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) +#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) +#define LCDIF_PIGEON_2_RSVD_SHIFT (9U) +#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_2 */ +#define LCDIF_PIGEON_2_COUNT (12U) + +/*! @name LUT_CTRL - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) +#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) +#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) +/*! @} */ + +/*! @name LUT0_ADDR - Lookup Table Control Register. */ +/*! @{ */ +#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) +#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name LUT0_DATA - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) +#define LCDIF_LUT0_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) +/*! @} */ + +/*! @name LUT1_ADDR - Lookup Table Control Register. */ +/*! @{ */ +#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) +#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name LUT1_DATA - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) +#define LCDIF_LUT1_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x402B8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } +/** Interrupt vectors for the LCDIF peripheral type */ +#define LCDIF_IRQ0_IRQS { LCDIF_IRQn } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + uint8_t RESERVED_6[156]; + __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + uint8_t RESERVED_7[4]; + __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Master Control Register */ +/*! @{ */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Master Status Register */ +/*! @{ */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ + +/*! @name MDER - Master DMA Enable Register */ +/*! @{ */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ + +/*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Master Data Match Register */ +/*! @{ */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Master Receive Data Register */ +/*! @{ */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Slave Control Register */ +/*! @{ */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Slave Status Register */ +/*! @{ */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Slave Address Match Register */ +/*! @{ */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Slave Address Status Register */ +/*! @{ */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x403F0000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x403F4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x403F8000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base address */ +#define LPI2C4_BASE (0x403FC000u) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< Status Register, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ + uint8_t RESERVED_3[20]; + __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable Register */ +/*! @{ */ +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration Register */ +/*! @{ */ +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control Register */ +/*! @{ */ +#define LPSPI_FCR_TXWATER_MASK (0xFU) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) +#define LPSPI_FCR_RXWATER_MASK (0xF0000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status Register */ +/*! @{ */ +#define LPSPI_FSR_TXCOUNT_MASK (0x1FU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) +#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command Register */ +/*! @{ */ +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data Register */ +/*! @{ */ +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status Register */ +/*! @{ */ +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data Register */ +/*! @{ */ +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x40394000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x40398000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Peripheral LPSPI3 base address */ +#define LPSPI3_BASE (0x4039C000u) +/** Peripheral LPSPI3 base pointer */ +#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) +/** Peripheral LPSPI4 base address */ +#define LPSPI4_BASE (0x403A0000u) +/** Peripheral LPSPI4 base pointer */ +#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ + __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ + __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ + __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - LPUART Status Register */ +/*! @{ */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - LPUART Control Register */ +/*! @{ */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - LPUART Data Register */ +/*! @{ */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - LPUART Watermark Register */ +/*! @{ */ +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x40184000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x40188000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x4018C000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x40190000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x40194000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Peripheral LPUART6 base address */ +#define LPUART6_BASE (0x40198000u) +/** Peripheral LPUART6 base pointer */ +#define LPUART6 ((LPUART_Type *)LPUART6_BASE) +/** Peripheral LPUART7 base address */ +#define LPUART7_BASE (0x4019C000u) +/** Peripheral LPUART7 base pointer */ +#define LPUART7 ((LPUART_Type *)LPUART7_BASE) +/** Peripheral LPUART8 base address */ +#define LPUART8_BASE (0x401A0000u) +/** Peripheral LPUART8 base pointer */ +#define LPUART8 ((LPUART_Type *)LPUART8_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + uint8_t RESERVED_5[32]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_6[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_7[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_15[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ + uint8_t RESERVED_23[140]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_24[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_25[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_30[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_33[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_34[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_35[12]; + __IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ + uint8_t RESERVED_36[28]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_37[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ + +/*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ + +/*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ + +/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ + +/*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +/*! @} */ + +/*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ + +/*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ + +/*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_SRK_MASK (0x4000U) +#define OCOTP_LOCK_SRK_SHIFT (14U) +#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) +#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) +#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) +#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) +#define OCOTP_LOCK_SW_GP1_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP1_SHIFT (16U) +#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK) +#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U) +#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U) +#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U) +#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U) +#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U) +#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK) +#define OCOTP_LOCK_GP3_MASK (0xC000000U) +#define OCOTP_LOCK_GP3_SHIFT (26U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) +#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) +#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ + +/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ + +/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ + +/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ +#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_BITS_SHIFT (0U) +#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ + +/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ + +/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP20_BITS_SHIFT (0U) +#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ + +/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP21_BITS_SHIFT (0U) +#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ + +/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP22_BITS_SHIFT (0U) +#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ + +/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP23_BITS_SHIFT (0U) +#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF0_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF1_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x401F4000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[544]; + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */ + uint8_t RESERVED_1[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ + +/*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x400F4000u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[220]; + __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ + __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ + uint8_t RESERVED_1[24]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +/*! @{ */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ + +/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) +#define PIT_LTMR64H_LTH_SHIFT (0U) +#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ + +/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) +#define PIT_LTMR64L_LTL_SHIFT (0U) +#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ + +/*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +/*! @{ */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +/*! @{ */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +/*! @{ */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40084000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[272]; + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ + __IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */ + __IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */ + __IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */ + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ + __IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */ + __IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */ + __IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */ + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ + __IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */ + __IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */ + __IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */ + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ + __IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */ + __IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */ + __IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */ + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) +#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK) +#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK) +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK) +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK) +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) +#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK) +#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) +#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) +#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) +#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) +#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) +#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) +#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) +#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) +#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) +#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_OSC_I_MASK (0x6000U) +#define PMU_MISC0_OSC_I_SHIFT (13U) +#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) +#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK) +#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) +#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) +#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) +#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_SET_OSC_I_MASK (0x6000U) +#define PMU_MISC0_SET_OSC_I_SHIFT (13U) +#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) +#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) +#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) +#define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) +#define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) +#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK) +#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK) +#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK) +#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK) +#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) +#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK) +#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_REG2_OK_SHIFT (22U) +#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) +#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) +#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) +#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_VIDEO_DIV_SHIFT (30U) +#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_SET_REG2_OK_SHIFT (22U) +#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) +#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) +#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U) +#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) +#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U) +#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) +#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x400D8000u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + uint8_t RESERVED_1[8]; + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) +#define PWM_CTRL2_WAITEN_MASK (0x4000U) +#define PWM_CTRL2_WAITEN_SHIFT (14U) +#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) +#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) +#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) +#define PWM_DISMAP_DIS1A_MASK (0xFU) +#define PWM_DISMAP_DIS1A_SHIFT (0U) +#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) +#define PWM_DISMAP_DIS1B_MASK (0xF0U) +#define PWM_DISMAP_DIS1B_SHIFT (4U) +#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (2U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ +#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ +#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ +#define PWM_MCTRL2_MONPLL_MASK (0x3U) +#define PWM_MCTRL2_MONPLL_SHIFT (0U) +#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x403DC000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x403E0000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x403E4000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x403E8000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[348]; + __IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */ + uint8_t RESERVED_25[220]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_26[60]; + __IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_RSVD0_MASK (0xE0U) +#define PXP_CTRL_RSVD0_SHIFT (5U) +#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK) +#define PXP_CTRL_ROTATE_MASK (0x300U) +#define PXP_CTRL_ROTATE_SHIFT (8U) +#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) +#define PXP_CTRL_HFLIP_MASK (0x400U) +#define PXP_CTRL_HFLIP_SHIFT (10U) +#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK) +#define PXP_CTRL_VFLIP_MASK (0x800U) +#define PXP_CTRL_VFLIP_SHIFT (11U) +#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK) +#define PXP_CTRL_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_RSVD1_SHIFT (12U) +#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK) +#define PXP_CTRL_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_ROT_POS_SHIFT (22U) +#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_RSVD3_SHIFT (24U) +#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_RSVD4_SHIFT (29U) +#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_SET_RSVD0_MASK (0xE0U) +#define PXP_CTRL_SET_RSVD0_SHIFT (5U) +#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK) +#define PXP_CTRL_SET_ROTATE_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE_SHIFT (8U) +#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) +#define PXP_CTRL_SET_HFLIP_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK) +#define PXP_CTRL_SET_VFLIP_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK) +#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_SET_RSVD1_SHIFT (12U) +#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK) +#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_SET_ROT_POS_SHIFT (22U) +#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_SET_RSVD3_SHIFT (24U) +#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_SET_RSVD4_SHIFT (29U) +#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U) +#define PXP_CTRL_CLR_RSVD0_SHIFT (5U) +#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK) +#define PXP_CTRL_CLR_ROTATE_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE_SHIFT (8U) +#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) +#define PXP_CTRL_CLR_HFLIP_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK) +#define PXP_CTRL_CLR_VFLIP_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK) +#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_CLR_RSVD1_SHIFT (12U) +#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK) +#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U) +#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_CLR_RSVD3_SHIFT (24U) +#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_CLR_RSVD4_SHIFT (29U) +#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U) +#define PXP_CTRL_TOG_RSVD0_SHIFT (5U) +#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK) +#define PXP_CTRL_TOG_ROTATE_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE_SHIFT (8U) +#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) +#define PXP_CTRL_TOG_HFLIP_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK) +#define PXP_CTRL_TOG_VFLIP_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK) +#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_TOG_RSVD1_SHIFT (12U) +#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK) +#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U) +#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_TOG_RSVD3_SHIFT (24U) +#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_TOG_RSVD4_SHIFT (29U) +#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ +#define PXP_STAT_IRQ_MASK (0x1U) +#define PXP_STAT_IRQ_SHIFT (0U) +#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_RSVD2_MASK (0xFE00U) +#define PXP_STAT_RSVD2_SHIFT (9U) +#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_SET - Status Register */ +/*! @{ */ +#define PXP_STAT_SET_IRQ_MASK (0x1U) +#define PXP_STAT_SET_IRQ_SHIFT (0U) +#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_RSVD2_MASK (0xFE00U) +#define PXP_STAT_SET_RSVD2_SHIFT (9U) +#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_CLR - Status Register */ +/*! @{ */ +#define PXP_STAT_CLR_IRQ_MASK (0x1U) +#define PXP_STAT_CLR_IRQ_SHIFT (0U) +#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U) +#define PXP_STAT_CLR_RSVD2_SHIFT (9U) +#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_TOG - Status Register */ +/*! @{ */ +#define PXP_STAT_TOG_IRQ_MASK (0x1U) +#define PXP_STAT_TOG_IRQ_SHIFT (0U) +#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U) +#define PXP_STAT_TOG_RSVD2_SHIFT (9U) +#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) +/*! @} */ + +/*! @name OUT_CTRL - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +/*! @{ */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +/*! @{ */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) +/*! @} */ + +/*! @name OUT_PITCH - Output Buffer Pitch */ +/*! @{ */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) +#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_OUT_PITCH_RSVD_SHIFT (16U) +#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) +#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +/*! @{ */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U) +#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U) +#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) +#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) +#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) +#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +/*! @{ */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U) +#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U) +#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) +#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) +#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) +#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) +#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) +#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) +#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) +#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name PS_BUF - PS Input Buffer Address */ +/*! @{ */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +/*! @{ */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +/*! @{ */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_PITCH - Processed Surface Pitch */ +/*! @{ */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) +#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_PS_PITCH_RSVD_SHIFT (16U) +#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name PS_BACKGROUND - PS Background Color */ +/*! @{ */ +#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) +#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) +#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) +#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) +/*! @} */ + +/*! @name PS_SCALE - PS Scale Factor Register */ +/*! @{ */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_RSVD1_MASK (0x8000U) +#define PXP_PS_SCALE_RSVD1_SHIFT (15U) +#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) +#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) +#define PXP_PS_SCALE_RSVD2_SHIFT (31U) +#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) +/*! @} */ + +/*! @name PS_OFFSET - PS Scale Offset Register */ +/*! @{ */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U) +#define PXP_PS_OFFSET_RSVD1_SHIFT (12U) +#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) +#define PXP_PS_OFFSET_RSVD2_SHIFT (28U) +#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) +/*! @} */ + +/*! @name PS_CLRKEYLOW - PS Color Key Low */ +/*! @{ */ +#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) +#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CLRKEYHIGH - PS Color Key High */ +/*! @{ */ +#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) +#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CTRL - Alpha Surface Control */ +/*! @{ */ +#define PXP_AS_CTRL_RSVD0_MASK (0x1U) +#define PXP_AS_CTRL_RSVD0_SHIFT (0U) +#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK) +#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) +#define PXP_AS_CTRL_RSVD1_SHIFT (21U) +#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) +/*! @} */ + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +/*! @{ */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name AS_PITCH - Alpha Surface Pitch */ +/*! @{ */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) +#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_AS_PITCH_RSVD_SHIFT (16U) +#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name AS_CLRKEYLOW - Overlay Color Key Low */ +/*! @{ */ +#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) +#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CLRKEYHIGH - Overlay Color Key High */ +/*! @{ */ +#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) +#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U) +#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U) +#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) +/*! @} */ + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U) +#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U) +#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) +#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) +#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) +#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) +/*! @} */ + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U) +#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U) +#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) +#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) +#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) +#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) +/*! @} */ + +/*! @name POWER - PXP Power Control Register */ +/*! @{ */ +#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) +#define PXP_POWER_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_CTRL_SHIFT (12U) +#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) +/*! @} */ + +/*! @name NEXT - Next Frame Pointer */ +/*! @{ */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_RSVD_MASK (0x2U) +#define PXP_NEXT_RSVD_SHIFT (1U) +#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) +/*! @} */ + +/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ +/*! @{ */ +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x402B4000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ + +/*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x40180000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTWDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer + * @{ + */ + +/** RTWDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ + __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ + __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ +} RTWDOG_Type; + +/* ---------------------------------------------------------------------------- + -- RTWDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks + * @{ + */ + +/*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ +#define RTWDOG_CS_STOP_MASK (0x1U) +#define RTWDOG_CS_STOP_SHIFT (0U) +#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) +#define RTWDOG_CS_WAIT_MASK (0x2U) +#define RTWDOG_CS_WAIT_SHIFT (1U) +#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) +#define RTWDOG_CS_DBG_MASK (0x4U) +#define RTWDOG_CS_DBG_SHIFT (2U) +#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) +#define RTWDOG_CS_TST_MASK (0x18U) +#define RTWDOG_CS_TST_SHIFT (3U) +#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) +#define RTWDOG_CS_UPDATE_MASK (0x20U) +#define RTWDOG_CS_UPDATE_SHIFT (5U) +#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) +#define RTWDOG_CS_INT_MASK (0x40U) +#define RTWDOG_CS_INT_SHIFT (6U) +#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) +#define RTWDOG_CS_EN_MASK (0x80U) +#define RTWDOG_CS_EN_SHIFT (7U) +#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) +#define RTWDOG_CS_CLK_MASK (0x300U) +#define RTWDOG_CS_CLK_SHIFT (8U) +#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) +#define RTWDOG_CS_RCS_MASK (0x400U) +#define RTWDOG_CS_RCS_SHIFT (10U) +#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) +#define RTWDOG_CS_ULK_MASK (0x800U) +#define RTWDOG_CS_ULK_SHIFT (11U) +#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) +#define RTWDOG_CS_PRES_MASK (0x1000U) +#define RTWDOG_CS_PRES_SHIFT (12U) +#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) +#define RTWDOG_CS_CMD32EN_MASK (0x2000U) +#define RTWDOG_CS_CMD32EN_SHIFT (13U) +#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) +#define RTWDOG_CS_FLG_MASK (0x4000U) +#define RTWDOG_CS_FLG_SHIFT (14U) +#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) +#define RTWDOG_CS_WIN_MASK (0x8000U) +#define RTWDOG_CS_WIN_SHIFT (15U) +#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - Watchdog Counter Register */ +/*! @{ */ +#define RTWDOG_CNT_CNTLOW_MASK (0xFFU) +#define RTWDOG_CNT_CNTLOW_SHIFT (0U) +#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) +#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define RTWDOG_CNT_CNTHIGH_SHIFT (8U) +#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ +#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) +#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) +#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) +#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window Register */ +/*! @{ */ +#define RTWDOG_WIN_WINLOW_MASK (0xFFU) +#define RTWDOG_WIN_WINLOW_SHIFT (0U) +#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) +#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) +#define RTWDOG_WIN_WINHIGH_SHIFT (8U) +#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTWDOG_Register_Masks */ + + +/* RTWDOG - Peripheral instance base addresses */ +/** Peripheral RTWDOG base address */ +#define RTWDOG_BASE (0x400BC000u) +/** Peripheral RTWDOG base pointer */ +#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE) +/** Array initializer of RTWDOG peripheral base addresses */ +#define RTWDOG_BASE_ADDRS { RTWDOG_BASE } +/** Array initializer of RTWDOG peripheral base pointers */ +#define RTWDOG_BASE_PTRS { RTWDOG } +/** Interrupt vectors for the RTWDOG peripheral type */ +#define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group RTWDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer + * @{ + */ + +/** SEMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ + __IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */ + __IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */ + __IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */ + __IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */ + __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ + __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ + __IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */ + __IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */ + __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ + __IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */ + __IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */ + __IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */ + __IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */ + __IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */ + __IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */ + __IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */ + uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */ + __IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */ + __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ + __IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */ + uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */ + __IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */ + __IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */ + uint8_t RESERVED_1[8]; + __IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */ + __IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */ + __IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */ + __IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */ + __IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */ + uint8_t RESERVED_2[12]; + __I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */ + uint8_t RESERVED_3[12]; + __I uint32_t STS0; /**< Status register 0, offset: 0xC0 */ + uint32_t STS1; /**< Status register 1, offset: 0xC4 */ + __I uint32_t STS2; /**< Status register 2, offset: 0xC8 */ + uint32_t STS3; /**< Status register 3, offset: 0xCC */ + uint32_t STS4; /**< Status register 4, offset: 0xD0 */ + uint32_t STS5; /**< Status register 5, offset: 0xD4 */ + uint32_t STS6; /**< Status register 6, offset: 0xD8 */ + uint32_t STS7; /**< Status register 7, offset: 0xDC */ + uint32_t STS8; /**< Status register 8, offset: 0xE0 */ + uint32_t STS9; /**< Status register 9, offset: 0xE4 */ + uint32_t STS10; /**< Status register 10, offset: 0xE8 */ + uint32_t STS11; /**< Status register 11, offset: 0xEC */ + __I uint32_t STS12; /**< Status register 12, offset: 0xF0 */ + uint32_t STS13; /**< Status register 13, offset: 0xF4 */ + uint32_t STS14; /**< Status register 14, offset: 0xF8 */ + uint32_t STS15; /**< Status register 15, offset: 0xFC */ +} SEMC_Type; + +/* ---------------------------------------------------------------------------- + -- SEMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Register_Masks SEMC Register Masks + * @{ + */ + +/*! @name MCR - Module Control Register */ +/*! @{ */ +#define SEMC_MCR_SWRST_MASK (0x1U) +#define SEMC_MCR_SWRST_SHIFT (0U) +#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) +#define SEMC_MCR_MDIS_MASK (0x2U) +#define SEMC_MCR_MDIS_SHIFT (1U) +#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) +#define SEMC_MCR_DQSMD_MASK (0x4U) +#define SEMC_MCR_DQSMD_SHIFT (2U) +#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) +#define SEMC_MCR_WPOL0_MASK (0x40U) +#define SEMC_MCR_WPOL0_SHIFT (6U) +#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) +#define SEMC_MCR_WPOL1_MASK (0x80U) +#define SEMC_MCR_WPOL1_SHIFT (7U) +#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) +#define SEMC_MCR_CTO_MASK (0xFF0000U) +#define SEMC_MCR_CTO_SHIFT (16U) +#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) +#define SEMC_MCR_BTO_MASK (0x1F000000U) +#define SEMC_MCR_BTO_SHIFT (24U) +#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ + +/*! @name IOCR - IO Mux Control Register */ +/*! @{ */ +#define SEMC_IOCR_MUX_A8_MASK (0x7U) +#define SEMC_IOCR_MUX_A8_SHIFT (0U) +#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) +#define SEMC_IOCR_MUX_CSX0_MASK (0x38U) +#define SEMC_IOCR_MUX_CSX0_SHIFT (3U) +#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) +#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) +#define SEMC_IOCR_MUX_CSX1_SHIFT (6U) +#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) +#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) +#define SEMC_IOCR_MUX_CSX2_SHIFT (9U) +#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) +#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) +#define SEMC_IOCR_MUX_CSX3_SHIFT (12U) +#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) +#define SEMC_IOCR_MUX_RDY_MASK (0x38000U) +#define SEMC_IOCR_MUX_RDY_SHIFT (15U) +#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +/*! @} */ + +/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ +#define SEMC_BMCR0_WQOS_MASK (0xFU) +#define SEMC_BMCR0_WQOS_SHIFT (0U) +#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) +#define SEMC_BMCR0_WAGE_MASK (0xF0U) +#define SEMC_BMCR0_WAGE_SHIFT (4U) +#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) +#define SEMC_BMCR0_WSH_MASK (0xFF00U) +#define SEMC_BMCR0_WSH_SHIFT (8U) +#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) +#define SEMC_BMCR0_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR0_WRWS_SHIFT (16U) +#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ + +/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ +#define SEMC_BMCR1_WQOS_MASK (0xFU) +#define SEMC_BMCR1_WQOS_SHIFT (0U) +#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) +#define SEMC_BMCR1_WAGE_MASK (0xF0U) +#define SEMC_BMCR1_WAGE_SHIFT (4U) +#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) +#define SEMC_BMCR1_WPH_MASK (0xFF00U) +#define SEMC_BMCR1_WPH_SHIFT (8U) +#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) +#define SEMC_BMCR1_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR1_WRWS_SHIFT (16U) +#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) +#define SEMC_BMCR1_WBR_MASK (0xFF000000U) +#define SEMC_BMCR1_WBR_SHIFT (24U) +#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ + +/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ +#define SEMC_BR_VLD_MASK (0x1U) +#define SEMC_BR_VLD_SHIFT (0U) +#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) +#define SEMC_BR_MS_MASK (0x3EU) +#define SEMC_BR_MS_SHIFT (1U) +#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) +#define SEMC_BR_BA_MASK (0xFFFFF000U) +#define SEMC_BR_BA_SHIFT (12U) +#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ + +/* The count of SEMC_BR */ +#define SEMC_BR_COUNT (9U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) +#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) +#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) +#define SEMC_INTEN_IPCMDERREN_MASK (0x2U) +#define SEMC_INTEN_IPCMDERREN_SHIFT (1U) +#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) +#define SEMC_INTEN_AXICMDERREN_MASK (0x4U) +#define SEMC_INTEN_AXICMDERREN_SHIFT (2U) +#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) +#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U) +#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U) +#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) +#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) +#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) +#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) +#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) +#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) +#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTR_IPCMDDONE_MASK (0x1U) +#define SEMC_INTR_IPCMDDONE_SHIFT (0U) +#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) +#define SEMC_INTR_IPCMDERR_MASK (0x2U) +#define SEMC_INTR_IPCMDERR_SHIFT (1U) +#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) +#define SEMC_INTR_AXICMDERR_MASK (0x4U) +#define SEMC_INTR_AXICMDERR_SHIFT (2U) +#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) +#define SEMC_INTR_AXIBUSERR_MASK (0x8U) +#define SEMC_INTR_AXIBUSERR_SHIFT (3U) +#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) +#define SEMC_INTR_NDPAGEEND_MASK (0x10U) +#define SEMC_INTR_NDPAGEEND_SHIFT (4U) +#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) +#define SEMC_INTR_NDNOPEND_MASK (0x20U) +#define SEMC_INTR_NDNOPEND_SHIFT (5U) +#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ + +/*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ +#define SEMC_SDRAMCR0_PS_MASK (0x1U) +#define SEMC_SDRAMCR0_PS_SHIFT (0U) +#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) +#define SEMC_SDRAMCR0_BL_MASK (0x70U) +#define SEMC_SDRAMCR0_BL_SHIFT (4U) +#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) +#define SEMC_SDRAMCR0_COL_MASK (0x300U) +#define SEMC_SDRAMCR0_COL_SHIFT (8U) +#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) +#define SEMC_SDRAMCR0_CL_MASK (0xC00U) +#define SEMC_SDRAMCR0_CL_SHIFT (10U) +#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +/*! @} */ + +/*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ +#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) +#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) +#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) +#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) +#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) +#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) +#define SEMC_SDRAMCR1_RFRC_SHIFT (8U) +#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) +#define SEMC_SDRAMCR1_WRC_MASK (0xE000U) +#define SEMC_SDRAMCR1_WRC_SHIFT (13U) +#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) +#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) +#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) +#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) +#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) +#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ + +/*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ +#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) +#define SEMC_SDRAMCR2_SRRC_SHIFT (0U) +#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) +#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) +#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U) +#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) +#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) +#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) +#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) +#define SEMC_SDRAMCR2_ITO_SHIFT (24U) +#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ + +/*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ +#define SEMC_SDRAMCR3_REN_MASK (0x1U) +#define SEMC_SDRAMCR3_REN_SHIFT (0U) +#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) +#define SEMC_SDRAMCR3_REBL_MASK (0xEU) +#define SEMC_SDRAMCR3_REBL_SHIFT (1U) +#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) +#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) +#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) +#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) +#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) +#define SEMC_SDRAMCR3_RT_SHIFT (16U) +#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) +#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) +#define SEMC_SDRAMCR3_UT_SHIFT (24U) +#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ + +/*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ +#define SEMC_NANDCR0_PS_MASK (0x1U) +#define SEMC_NANDCR0_PS_SHIFT (0U) +#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) +#define SEMC_NANDCR0_BL_MASK (0x70U) +#define SEMC_NANDCR0_BL_SHIFT (4U) +#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) +#define SEMC_NANDCR0_EDO_MASK (0x80U) +#define SEMC_NANDCR0_EDO_SHIFT (7U) +#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) +#define SEMC_NANDCR0_COL_MASK (0x700U) +#define SEMC_NANDCR0_COL_SHIFT (8U) +#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ + +/*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ +#define SEMC_NANDCR1_CES_MASK (0xFU) +#define SEMC_NANDCR1_CES_SHIFT (0U) +#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) +#define SEMC_NANDCR1_CEH_MASK (0xF0U) +#define SEMC_NANDCR1_CEH_SHIFT (4U) +#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) +#define SEMC_NANDCR1_WEL_MASK (0xF00U) +#define SEMC_NANDCR1_WEL_SHIFT (8U) +#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) +#define SEMC_NANDCR1_WEH_MASK (0xF000U) +#define SEMC_NANDCR1_WEH_SHIFT (12U) +#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) +#define SEMC_NANDCR1_REL_MASK (0xF0000U) +#define SEMC_NANDCR1_REL_SHIFT (16U) +#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) +#define SEMC_NANDCR1_REH_MASK (0xF00000U) +#define SEMC_NANDCR1_REH_SHIFT (20U) +#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) +#define SEMC_NANDCR1_TA_MASK (0xF000000U) +#define SEMC_NANDCR1_TA_SHIFT (24U) +#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) +#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) +#define SEMC_NANDCR1_CEITV_SHIFT (28U) +#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ + +/*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ +#define SEMC_NANDCR2_TWHR_MASK (0x3FU) +#define SEMC_NANDCR2_TWHR_SHIFT (0U) +#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) +#define SEMC_NANDCR2_TRHW_MASK (0xFC0U) +#define SEMC_NANDCR2_TRHW_SHIFT (6U) +#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) +#define SEMC_NANDCR2_TADL_MASK (0x3F000U) +#define SEMC_NANDCR2_TADL_SHIFT (12U) +#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) +#define SEMC_NANDCR2_TRR_MASK (0xFC0000U) +#define SEMC_NANDCR2_TRR_SHIFT (18U) +#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) +#define SEMC_NANDCR2_TWB_MASK (0x3F000000U) +#define SEMC_NANDCR2_TWB_SHIFT (24U) +#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ + +/*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ +#define SEMC_NANDCR3_NDOPT1_MASK (0x1U) +#define SEMC_NANDCR3_NDOPT1_SHIFT (0U) +#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) +#define SEMC_NANDCR3_NDOPT2_MASK (0x2U) +#define SEMC_NANDCR3_NDOPT2_SHIFT (1U) +#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) +#define SEMC_NANDCR3_NDOPT3_MASK (0x4U) +#define SEMC_NANDCR3_NDOPT3_SHIFT (2U) +#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +/*! @} */ + +/*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ +#define SEMC_NORCR0_PS_MASK (0x1U) +#define SEMC_NORCR0_PS_SHIFT (0U) +#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) +#define SEMC_NORCR0_BL_MASK (0x70U) +#define SEMC_NORCR0_BL_SHIFT (4U) +#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) +#define SEMC_NORCR0_AM_MASK (0x300U) +#define SEMC_NORCR0_AM_SHIFT (8U) +#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) +#define SEMC_NORCR0_ADVP_MASK (0x400U) +#define SEMC_NORCR0_ADVP_SHIFT (10U) +#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) +#define SEMC_NORCR0_COL_MASK (0xF000U) +#define SEMC_NORCR0_COL_SHIFT (12U) +#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ + +/*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ +#define SEMC_NORCR1_CES_MASK (0xFU) +#define SEMC_NORCR1_CES_SHIFT (0U) +#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) +#define SEMC_NORCR1_CEH_MASK (0xF0U) +#define SEMC_NORCR1_CEH_SHIFT (4U) +#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) +#define SEMC_NORCR1_AS_MASK (0xF00U) +#define SEMC_NORCR1_AS_SHIFT (8U) +#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) +#define SEMC_NORCR1_AH_MASK (0xF000U) +#define SEMC_NORCR1_AH_SHIFT (12U) +#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) +#define SEMC_NORCR1_WEL_MASK (0xF0000U) +#define SEMC_NORCR1_WEL_SHIFT (16U) +#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) +#define SEMC_NORCR1_WEH_MASK (0xF00000U) +#define SEMC_NORCR1_WEH_SHIFT (20U) +#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) +#define SEMC_NORCR1_REL_MASK (0xF000000U) +#define SEMC_NORCR1_REL_SHIFT (24U) +#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) +#define SEMC_NORCR1_REH_MASK (0xF0000000U) +#define SEMC_NORCR1_REH_SHIFT (28U) +#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ + +/*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ +#define SEMC_NORCR2_WDS_MASK (0xFU) +#define SEMC_NORCR2_WDS_SHIFT (0U) +#define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) +#define SEMC_NORCR2_WDH_MASK (0xF0U) +#define SEMC_NORCR2_WDH_SHIFT (4U) +#define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK) +#define SEMC_NORCR2_TA_MASK (0xF00U) +#define SEMC_NORCR2_TA_SHIFT (8U) +#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) +#define SEMC_NORCR2_AWDH_MASK (0xF000U) +#define SEMC_NORCR2_AWDH_SHIFT (12U) +#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) +#define SEMC_NORCR2_LC_MASK (0xF0000U) +#define SEMC_NORCR2_LC_SHIFT (16U) +#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) +#define SEMC_NORCR2_RD_MASK (0xF00000U) +#define SEMC_NORCR2_RD_SHIFT (20U) +#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) +#define SEMC_NORCR2_CEITV_MASK (0xF000000U) +#define SEMC_NORCR2_CEITV_SHIFT (24U) +#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +/*! @} */ + +/*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ +#define SEMC_SRAMCR0_PS_MASK (0x1U) +#define SEMC_SRAMCR0_PS_SHIFT (0U) +#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) +#define SEMC_SRAMCR0_BL_MASK (0x70U) +#define SEMC_SRAMCR0_BL_SHIFT (4U) +#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) +#define SEMC_SRAMCR0_AM_MASK (0x300U) +#define SEMC_SRAMCR0_AM_SHIFT (8U) +#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) +#define SEMC_SRAMCR0_ADVP_MASK (0x400U) +#define SEMC_SRAMCR0_ADVP_SHIFT (10U) +#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) +#define SEMC_SRAMCR0_COL_MASK (0xF000U) +#define SEMC_SRAMCR0_COL_SHIFT (12U) +#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ + +/*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ +#define SEMC_SRAMCR1_CES_MASK (0xFU) +#define SEMC_SRAMCR1_CES_SHIFT (0U) +#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) +#define SEMC_SRAMCR1_CEH_MASK (0xF0U) +#define SEMC_SRAMCR1_CEH_SHIFT (4U) +#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) +#define SEMC_SRAMCR1_AS_MASK (0xF00U) +#define SEMC_SRAMCR1_AS_SHIFT (8U) +#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) +#define SEMC_SRAMCR1_AH_MASK (0xF000U) +#define SEMC_SRAMCR1_AH_SHIFT (12U) +#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) +#define SEMC_SRAMCR1_WEL_MASK (0xF0000U) +#define SEMC_SRAMCR1_WEL_SHIFT (16U) +#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) +#define SEMC_SRAMCR1_WEH_MASK (0xF00000U) +#define SEMC_SRAMCR1_WEH_SHIFT (20U) +#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) +#define SEMC_SRAMCR1_REL_MASK (0xF000000U) +#define SEMC_SRAMCR1_REL_SHIFT (24U) +#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) +#define SEMC_SRAMCR1_REH_MASK (0xF0000000U) +#define SEMC_SRAMCR1_REH_SHIFT (28U) +#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ + +/*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ +#define SEMC_SRAMCR2_WDS_MASK (0xFU) +#define SEMC_SRAMCR2_WDS_SHIFT (0U) +#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) +#define SEMC_SRAMCR2_WDH_MASK (0xF0U) +#define SEMC_SRAMCR2_WDH_SHIFT (4U) +#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) +#define SEMC_SRAMCR2_TA_MASK (0xF00U) +#define SEMC_SRAMCR2_TA_SHIFT (8U) +#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) +#define SEMC_SRAMCR2_AWDH_MASK (0xF000U) +#define SEMC_SRAMCR2_AWDH_SHIFT (12U) +#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) +#define SEMC_SRAMCR2_LC_MASK (0xF0000U) +#define SEMC_SRAMCR2_LC_SHIFT (16U) +#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) +#define SEMC_SRAMCR2_RD_MASK (0xF00000U) +#define SEMC_SRAMCR2_RD_SHIFT (20U) +#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) +#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) +#define SEMC_SRAMCR2_CEITV_SHIFT (24U) +#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +/*! @} */ + +/*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ +#define SEMC_DBICR0_PS_MASK (0x1U) +#define SEMC_DBICR0_PS_SHIFT (0U) +#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) +#define SEMC_DBICR0_BL_MASK (0x70U) +#define SEMC_DBICR0_BL_SHIFT (4U) +#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) +#define SEMC_DBICR0_COL_MASK (0xF000U) +#define SEMC_DBICR0_COL_SHIFT (12U) +#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ + +/*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ +#define SEMC_DBICR1_CES_MASK (0xFU) +#define SEMC_DBICR1_CES_SHIFT (0U) +#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) +#define SEMC_DBICR1_CEH_MASK (0xF0U) +#define SEMC_DBICR1_CEH_SHIFT (4U) +#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) +#define SEMC_DBICR1_WEL_MASK (0xF00U) +#define SEMC_DBICR1_WEL_SHIFT (8U) +#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) +#define SEMC_DBICR1_WEH_MASK (0xF000U) +#define SEMC_DBICR1_WEH_SHIFT (12U) +#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) +#define SEMC_DBICR1_REL_MASK (0xF0000U) +#define SEMC_DBICR1_REL_SHIFT (16U) +#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) +#define SEMC_DBICR1_REH_MASK (0xF00000U) +#define SEMC_DBICR1_REH_SHIFT (20U) +#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) +#define SEMC_DBICR1_CEITV_MASK (0xF000000U) +#define SEMC_DBICR1_CEITV_SHIFT (24U) +#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR1_REL2_MASK (0x30000000U) +#define SEMC_DBICR1_REL2_SHIFT (28U) +#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) +#define SEMC_DBICR1_REH2_MASK (0xC0000000U) +#define SEMC_DBICR1_REH2_SHIFT (30U) +#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ +#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) +#define SEMC_IPCR0_SA_SHIFT (0U) +#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ +#define SEMC_IPCR1_DATSZ_MASK (0x7U) +#define SEMC_IPCR1_DATSZ_SHIFT (0U) +#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +/*! @} */ + +/*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ +#define SEMC_IPCR2_BM0_MASK (0x1U) +#define SEMC_IPCR2_BM0_SHIFT (0U) +#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) +#define SEMC_IPCR2_BM1_MASK (0x2U) +#define SEMC_IPCR2_BM1_SHIFT (1U) +#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) +#define SEMC_IPCR2_BM2_MASK (0x4U) +#define SEMC_IPCR2_BM2_SHIFT (2U) +#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) +#define SEMC_IPCR2_BM3_MASK (0x8U) +#define SEMC_IPCR2_BM3_SHIFT (3U) +#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command register */ +/*! @{ */ +#define SEMC_IPCMD_CMD_MASK (0xFFFFU) +#define SEMC_IPCMD_CMD_SHIFT (0U) +#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) +#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) +#define SEMC_IPCMD_KEY_SHIFT (16U) +#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ + +/*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPTXDAT_DAT_SHIFT (0U) +#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ + +/*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPRXDAT_DAT_SHIFT (0U) +#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ + +/*! @name STS0 - Status register 0 */ +/*! @{ */ +#define SEMC_STS0_IDLE_MASK (0x1U) +#define SEMC_STS0_IDLE_SHIFT (0U) +#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) +#define SEMC_STS0_NARDY_MASK (0x2U) +#define SEMC_STS0_NARDY_SHIFT (1U) +#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ + +/*! @name STS2 - Status register 2 */ +/*! @{ */ +#define SEMC_STS2_NDWRPEND_MASK (0x8U) +#define SEMC_STS2_NDWRPEND_SHIFT (3U) +#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ + +/*! @name STS12 - Status register 12 */ +/*! @{ */ +#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) +#define SEMC_STS12_NDADDR_SHIFT (0U) +#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMC_Register_Masks */ + + +/* SEMC - Peripheral instance base addresses */ +/** Peripheral SEMC base address */ +#define SEMC_BASE (0x402F0000u) +/** Peripheral SEMC base pointer */ +#define SEMC ((SEMC_Type *)SEMC_BASE) +/** Array initializer of SEMC peripheral base addresses */ +#define SEMC_BASE_ADDRS { SEMC_BASE } +/** Array initializer of SEMC peripheral base pointers */ +#define SEMC_BASE_PTRS { SEMC } +/** Interrupt vectors for the SEMC peripheral type */ +#define SEMC_IRQS { SEMC_IRQn } + +/*! + * @} + */ /* end of group SEMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + uint8_t RESERVED_2[96]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) +#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) +#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ + +/*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ + +/*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ + +/*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) +#define SNVS_HPSR_LPDIS_MASK (0x10U) +#define SNVS_HPSR_LPDIS_SHIFT (4U) +#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ + +/*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) +#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) +#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ + +/*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ + +/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ +#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) +#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) +#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) +#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) +#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) +#define SNVS_LPTDCR_ET1P_MASK (0x800U) +#define SNVS_LPTDCR_ET1P_SHIFT (11U) +#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) +#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) +#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) +#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) +#define SNVS_LPTDCR_OSCB_SHIFT (28U) +#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ + +/*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) +#define SNVS_LPSR_ET1D_MASK (0x200U) +#define SNVS_LPSR_ET1D_SHIFT (9U) +#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) +#define SNVS_LPSR_SED_MASK (0x100000U) +#define SNVS_LPSR_SED_SHIFT (20U) +#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (8U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x400D4000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ + +/*! @name SRCD - CDText Control Register */ +/*! @{ */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ + +/*! @name SRPC - PhaseConfig Register */ +/*! @{ */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ + +/*! @name SIE - InterruptEn Register */ +/*! @{ */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ + +/*! @name SIC - InterruptClear Register */ +/*! @{ */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ + +/*! @name SIS - InterruptStat Register */ +/*! @{ */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ + +/*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ + +/*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ + +/*! @name SRU - UchannelRx Register */ +/*! @{ */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ + +/*! @name SRQ - QchannelRx Register */ +/*! @{ */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ + +/*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ + +/*! @name STR - SPDIFTxRight Register */ +/*! @{ */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ + +/*! @name SRFM - FreqMeas Register */ +/*! @{ */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ + +/*! @name STC - SPDIFTxClk Register */ +/*! @{ */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x40380000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[16]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +/*! @{ */ +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) +#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +/*! @{ */ +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x400F8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +/* Backward compatibility */ +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[384]; + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ + uint8_t RESERVED_1[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x400D8000u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer + * @{ + */ + +/** TMR - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */ + __IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */ + __IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */ + __IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */ + __IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */ + __IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */ + __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */ + __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */ + __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */ + __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */ + __IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */ + __IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */ + uint8_t RESERVED_0[4]; + __IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */ + } CHANNEL[4]; +} TMR_Type; + +/* ---------------------------------------------------------------------------- + -- TMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Register_Masks TMR Register Masks + * @{ + */ + +/*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ +#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) +#define TMR_COMP1_COMPARISON_1_SHIFT (0U) +#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ + +/* The count of TMR_COMP1 */ +#define TMR_COMP1_COUNT (4U) + +/*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ +#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) +#define TMR_COMP2_COMPARISON_2_SHIFT (0U) +#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ + +/* The count of TMR_COMP2 */ +#define TMR_COMP2_COUNT (4U) + +/*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ +#define TMR_CAPT_CAPTURE_MASK (0xFFFFU) +#define TMR_CAPT_CAPTURE_SHIFT (0U) +#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ + +/* The count of TMR_CAPT */ +#define TMR_CAPT_COUNT (4U) + +/*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ +#define TMR_LOAD_LOAD_MASK (0xFFFFU) +#define TMR_LOAD_LOAD_SHIFT (0U) +#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ + +/* The count of TMR_LOAD */ +#define TMR_LOAD_COUNT (4U) + +/*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ +#define TMR_HOLD_HOLD_MASK (0xFFFFU) +#define TMR_HOLD_HOLD_SHIFT (0U) +#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ + +/* The count of TMR_HOLD */ +#define TMR_HOLD_COUNT (4U) + +/*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ +#define TMR_CNTR_COUNTER_MASK (0xFFFFU) +#define TMR_CNTR_COUNTER_SHIFT (0U) +#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ + +/* The count of TMR_CNTR */ +#define TMR_CNTR_COUNT (4U) + +/*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ +#define TMR_CTRL_OUTMODE_MASK (0x7U) +#define TMR_CTRL_OUTMODE_SHIFT (0U) +#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) +#define TMR_CTRL_COINIT_MASK (0x8U) +#define TMR_CTRL_COINIT_SHIFT (3U) +#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) +#define TMR_CTRL_DIR_MASK (0x10U) +#define TMR_CTRL_DIR_SHIFT (4U) +#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) +#define TMR_CTRL_LENGTH_MASK (0x20U) +#define TMR_CTRL_LENGTH_SHIFT (5U) +#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) +#define TMR_CTRL_ONCE_MASK (0x40U) +#define TMR_CTRL_ONCE_SHIFT (6U) +#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) +#define TMR_CTRL_SCS_MASK (0x180U) +#define TMR_CTRL_SCS_SHIFT (7U) +#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) +#define TMR_CTRL_PCS_MASK (0x1E00U) +#define TMR_CTRL_PCS_SHIFT (9U) +#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) +#define TMR_CTRL_CM_MASK (0xE000U) +#define TMR_CTRL_CM_SHIFT (13U) +#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ + +/* The count of TMR_CTRL */ +#define TMR_CTRL_COUNT (4U) + +/*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ +#define TMR_SCTRL_OEN_MASK (0x1U) +#define TMR_SCTRL_OEN_SHIFT (0U) +#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) +#define TMR_SCTRL_OPS_MASK (0x2U) +#define TMR_SCTRL_OPS_SHIFT (1U) +#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) +#define TMR_SCTRL_FORCE_MASK (0x4U) +#define TMR_SCTRL_FORCE_SHIFT (2U) +#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) +#define TMR_SCTRL_VAL_MASK (0x8U) +#define TMR_SCTRL_VAL_SHIFT (3U) +#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) +#define TMR_SCTRL_EEOF_MASK (0x10U) +#define TMR_SCTRL_EEOF_SHIFT (4U) +#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) +#define TMR_SCTRL_MSTR_MASK (0x20U) +#define TMR_SCTRL_MSTR_SHIFT (5U) +#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) +#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) +#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) +#define TMR_SCTRL_INPUT_MASK (0x100U) +#define TMR_SCTRL_INPUT_SHIFT (8U) +#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) +#define TMR_SCTRL_IPS_MASK (0x200U) +#define TMR_SCTRL_IPS_SHIFT (9U) +#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) +#define TMR_SCTRL_IEFIE_MASK (0x400U) +#define TMR_SCTRL_IEFIE_SHIFT (10U) +#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) +#define TMR_SCTRL_IEF_MASK (0x800U) +#define TMR_SCTRL_IEF_SHIFT (11U) +#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) +#define TMR_SCTRL_TOFIE_MASK (0x1000U) +#define TMR_SCTRL_TOFIE_SHIFT (12U) +#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) +#define TMR_SCTRL_TOF_MASK (0x2000U) +#define TMR_SCTRL_TOF_SHIFT (13U) +#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) +#define TMR_SCTRL_TCFIE_MASK (0x4000U) +#define TMR_SCTRL_TCFIE_SHIFT (14U) +#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) +#define TMR_SCTRL_TCF_MASK (0x8000U) +#define TMR_SCTRL_TCF_SHIFT (15U) +#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ + +/* The count of TMR_SCTRL */ +#define TMR_SCTRL_COUNT (4U) + +/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ +#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) +#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) +#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ + +/* The count of TMR_CMPLD1 */ +#define TMR_CMPLD1_COUNT (4U) + +/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ +#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) +#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) +#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ + +/* The count of TMR_CMPLD2 */ +#define TMR_CMPLD2_COUNT (4U) + +/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ +#define TMR_CSCTRL_CL1_MASK (0x3U) +#define TMR_CSCTRL_CL1_SHIFT (0U) +#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) +#define TMR_CSCTRL_CL2_MASK (0xCU) +#define TMR_CSCTRL_CL2_SHIFT (2U) +#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) +#define TMR_CSCTRL_TCF1_MASK (0x10U) +#define TMR_CSCTRL_TCF1_SHIFT (4U) +#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) +#define TMR_CSCTRL_TCF2_MASK (0x20U) +#define TMR_CSCTRL_TCF2_SHIFT (5U) +#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) +#define TMR_CSCTRL_TCF1EN_MASK (0x40U) +#define TMR_CSCTRL_TCF1EN_SHIFT (6U) +#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) +#define TMR_CSCTRL_TCF2EN_MASK (0x80U) +#define TMR_CSCTRL_TCF2EN_SHIFT (7U) +#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) +#define TMR_CSCTRL_UP_MASK (0x200U) +#define TMR_CSCTRL_UP_SHIFT (9U) +#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) +#define TMR_CSCTRL_TCI_MASK (0x400U) +#define TMR_CSCTRL_TCI_SHIFT (10U) +#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) +#define TMR_CSCTRL_ROC_MASK (0x800U) +#define TMR_CSCTRL_ROC_SHIFT (11U) +#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) +#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) +#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) +#define TMR_CSCTRL_FAULT_MASK (0x2000U) +#define TMR_CSCTRL_FAULT_SHIFT (13U) +#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) +#define TMR_CSCTRL_DBG_EN_MASK (0xC000U) +#define TMR_CSCTRL_DBG_EN_SHIFT (14U) +#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ + +/* The count of TMR_CSCTRL */ +#define TMR_CSCTRL_COUNT (4U) + +/*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ +#define TMR_FILT_FILT_PER_MASK (0xFFU) +#define TMR_FILT_FILT_PER_SHIFT (0U) +#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) +#define TMR_FILT_FILT_CNT_MASK (0x700U) +#define TMR_FILT_FILT_CNT_SHIFT (8U) +#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of TMR_FILT */ +#define TMR_FILT_COUNT (4U) + +/*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ +#define TMR_DMA_IEFDE_MASK (0x1U) +#define TMR_DMA_IEFDE_SHIFT (0U) +#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) +#define TMR_DMA_CMPLD1DE_MASK (0x2U) +#define TMR_DMA_CMPLD1DE_SHIFT (1U) +#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) +#define TMR_DMA_CMPLD2DE_MASK (0x4U) +#define TMR_DMA_CMPLD2DE_SHIFT (2U) +#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ + +/* The count of TMR_DMA */ +#define TMR_DMA_COUNT (4U) + +/*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ +#define TMR_ENBL_ENBL_MASK (0xFU) +#define TMR_ENBL_ENBL_SHIFT (0U) +#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ + +/* The count of TMR_ENBL */ +#define TMR_ENBL_COUNT (4U) + + +/*! + * @} + */ /* end of group TMR_Register_Masks */ + + +/* TMR - Peripheral instance base addresses */ +/** Peripheral TMR1 base address */ +#define TMR1_BASE (0x401DC000u) +/** Peripheral TMR1 base pointer */ +#define TMR1 ((TMR_Type *)TMR1_BASE) +/** Peripheral TMR2 base address */ +#define TMR2_BASE (0x401E0000u) +/** Peripheral TMR2 base pointer */ +#define TMR2 ((TMR_Type *)TMR2_BASE) +/** Peripheral TMR3 base address */ +#define TMR3_BASE (0x401E4000u) +/** Peripheral TMR3 base pointer */ +#define TMR3 ((TMR_Type *)TMR3_BASE) +/** Peripheral TMR4 base address */ +#define TMR4_BASE (0x401E8000u) +/** Peripheral TMR4 base pointer */ +#define TMR4 ((TMR_Type *)TMR4_BASE) +/** Array initializer of TMR peripheral base addresses */ +#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE } +/** Array initializer of TMR peripheral base pointers */ +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 } +/** Interrupt vectors for the TMR peripheral type */ +#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn } + +/*! + * @} + */ /* end of group TMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @{ + */ + +/** TRNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ + __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ + __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ + __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ + }; + __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ + union { /* offset: 0x14 */ + __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ + __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ + }; + __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ + union { /* offset: 0x1C */ + __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ + __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ + }; + union { /* offset: 0x20 */ + __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ + __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ + }; + union { /* offset: 0x24 */ + __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ + __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ + }; + union { /* offset: 0x28 */ + __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ + __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ + }; + union { /* offset: 0x2C */ + __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ + __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ + }; + union { /* offset: 0x30 */ + __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ + __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ + }; + union { /* offset: 0x34 */ + __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ + __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ + }; + union { /* offset: 0x38 */ + __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ + __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ + }; + __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ + __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ + __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ + __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ + __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ + __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ + __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ + __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ + __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ + __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ + __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ + __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ + uint8_t RESERVED_0[64]; + __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ + __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ +} TRNG_Type; + +/* ---------------------------------------------------------------------------- + -- TRNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @{ + */ + +/*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ +#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) +#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) +#define TRNG_MCTL_OSC_DIV_MASK (0xCU) +#define TRNG_MCTL_OSC_DIV_SHIFT (2U) +#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRNG_MCTL_UNUSED4_MASK (0x10U) +#define TRNG_MCTL_UNUSED4_SHIFT (4U) +#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) +#define TRNG_MCTL_UNUSED5_MASK (0x20U) +#define TRNG_MCTL_UNUSED5_SHIFT (5U) +#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK) +#define TRNG_MCTL_RST_DEF_MASK (0x40U) +#define TRNG_MCTL_RST_DEF_SHIFT (6U) +#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) +#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) +#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) +#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) +#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) +#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) +#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) +#define TRNG_MCTL_FCT_VAL_MASK (0x200U) +#define TRNG_MCTL_FCT_VAL_SHIFT (9U) +#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) +#define TRNG_MCTL_ENT_VAL_MASK (0x400U) +#define TRNG_MCTL_ENT_VAL_SHIFT (10U) +#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) +#define TRNG_MCTL_TST_OUT_MASK (0x800U) +#define TRNG_MCTL_TST_OUT_SHIFT (11U) +#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) +#define TRNG_MCTL_ERR_MASK (0x1000U) +#define TRNG_MCTL_ERR_SHIFT (12U) +#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) +#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) +#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) +#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) +#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) +#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) +#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) +#define TRNG_MCTL_PRGM_MASK (0x10000U) +#define TRNG_MCTL_PRGM_SHIFT (16U) +#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ + +/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ +#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) +#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) +#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) +#define TRNG_SCMISC_RTY_CT_SHIFT (16U) +#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ + +/*! @name PKRRNG - Poker Range Register */ +/*! @{ */ +#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) +#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) +#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ + +/*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ +#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) +#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) +#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ + +/*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ +#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) +#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) +#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ + +/*! @name SDCTL - Seed Control Register */ +/*! @{ */ +#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) +#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) +#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) +#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) +#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) +#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ + +/*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ +#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) +#define TRNG_SBLIM_SB_LIM_SHIFT (0U) +#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ + +/*! @name TOTSAM - Total Samples Register */ +/*! @{ */ +#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) +#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) +#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ + +/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ +#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) +#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) +#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ + +/*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ +#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) +#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ +#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) +#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) +#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ + +/*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ +#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) +#define TRNG_SCMC_MONO_CT_SHIFT (0U) +#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ + +/*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ +#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) +#define TRNG_SCML_MONO_MAX_SHIFT (0U) +#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) +#define TRNG_SCML_MONO_RNG_SHIFT (16U) +#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ + +/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ +#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) +#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) +#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) +#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) +#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ + +/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ +#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) +#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) +#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) +#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) +#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ + +/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ +#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) +#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) +#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) +#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) +#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ + +/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ +#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) +#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) +#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) +#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) +#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) +#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ + +/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ +#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) +#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) +#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) +#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) +#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) +#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ + +/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ +#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) +#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) +#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) +#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) +#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) +#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ + +/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ +#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) +#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) +#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) +#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) +#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) +#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ + +/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ +#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) +#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) +#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) +#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) +#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) +#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ + +/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ +#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) +#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) +#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) +#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) +#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ + +/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ +#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) +#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) +#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) +#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) +#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) +#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ + +/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ +#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) +#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) +#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) +#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) +#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ + +/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ +#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) +#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) +#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) +#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) +#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) +#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ +#define TRNG_STATUS_TF1BR0_MASK (0x1U) +#define TRNG_STATUS_TF1BR0_SHIFT (0U) +#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) +#define TRNG_STATUS_TF1BR1_MASK (0x2U) +#define TRNG_STATUS_TF1BR1_SHIFT (1U) +#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) +#define TRNG_STATUS_TF2BR0_MASK (0x4U) +#define TRNG_STATUS_TF2BR0_SHIFT (2U) +#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) +#define TRNG_STATUS_TF2BR1_MASK (0x8U) +#define TRNG_STATUS_TF2BR1_SHIFT (3U) +#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) +#define TRNG_STATUS_TF3BR0_MASK (0x10U) +#define TRNG_STATUS_TF3BR0_SHIFT (4U) +#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) +#define TRNG_STATUS_TF3BR1_MASK (0x20U) +#define TRNG_STATUS_TF3BR1_SHIFT (5U) +#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) +#define TRNG_STATUS_TF4BR0_MASK (0x40U) +#define TRNG_STATUS_TF4BR0_SHIFT (6U) +#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) +#define TRNG_STATUS_TF4BR1_MASK (0x80U) +#define TRNG_STATUS_TF4BR1_SHIFT (7U) +#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) +#define TRNG_STATUS_TF5BR0_MASK (0x100U) +#define TRNG_STATUS_TF5BR0_SHIFT (8U) +#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) +#define TRNG_STATUS_TF5BR1_MASK (0x200U) +#define TRNG_STATUS_TF5BR1_SHIFT (9U) +#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) +#define TRNG_STATUS_TF6PBR0_MASK (0x400U) +#define TRNG_STATUS_TF6PBR0_SHIFT (10U) +#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) +#define TRNG_STATUS_TF6PBR1_MASK (0x800U) +#define TRNG_STATUS_TF6PBR1_SHIFT (11U) +#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) +#define TRNG_STATUS_TFSB_MASK (0x1000U) +#define TRNG_STATUS_TFSB_SHIFT (12U) +#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) +#define TRNG_STATUS_TFLR_MASK (0x2000U) +#define TRNG_STATUS_TFLR_SHIFT (13U) +#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) +#define TRNG_STATUS_TFP_MASK (0x4000U) +#define TRNG_STATUS_TFP_SHIFT (14U) +#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) +#define TRNG_STATUS_TFMB_MASK (0x8000U) +#define TRNG_STATUS_TFMB_SHIFT (15U) +#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) +#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) +#define TRNG_STATUS_RETRY_CT_SHIFT (16U) +#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ + +/*! @name ENT - Entropy Read Register */ +/*! @{ */ +#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) +#define TRNG_ENT_ENT_SHIFT (0U) +#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ + +/* The count of TRNG_ENT */ +#define TRNG_ENT_COUNT (16U) + +/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ +#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) +#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) +#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) +#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ + +/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ +#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) +#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) +#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) +#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ + +/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ +#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) +#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) +#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) +#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ + +/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ +#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) +#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) +#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) +#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ + +/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ +#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) +#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) +#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) +#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ + +/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ +#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) +#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) +#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) +#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ + +/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ +#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) +#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) +#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) +#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ + +/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ +#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) +#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) +#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) +#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ + +/*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ +#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) +#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) +#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) +#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) +#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) +#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) +#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) +#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ + +/*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ +#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) +#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) +#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) +#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) +#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) +#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) +#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ + +/*! @name INT_MASK - Mask Register */ +/*! @{ */ +#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) +#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) +#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) +#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) +#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) +#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) +#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) +#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ +#define TRNG_VID1_MIN_REV_MASK (0xFFU) +#define TRNG_VID1_MIN_REV_SHIFT (0U) +#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) +#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) +#define TRNG_VID1_MAJ_REV_SHIFT (8U) +#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) +#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) +#define TRNG_VID1_IP_ID_SHIFT (16U) +#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ + +/*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ +#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) +#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) +#define TRNG_VID2_ECO_REV_MASK (0xFF00U) +#define TRNG_VID2_ECO_REV_SHIFT (8U) +#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) +#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) +#define TRNG_VID2_INTG_OPT_SHIFT (16U) +#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) +#define TRNG_VID2_ERA_MASK (0xFF000000U) +#define TRNG_VID2_ERA_SHIFT (24U) +#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRNG_Register_Masks */ + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG base address */ +#define TRNG_BASE (0x400CC000u) +/** Peripheral TRNG base pointer */ +#define TRNG ((TRNG_Type *)TRNG_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG_IRQn } + +/*! + * @} + */ /* end of group TRNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - */ +/*! @{ */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U) +#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ + +/*! @name PRE_CHARGE_TIME - */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ + +/*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ + +/*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ + +/*! @name INT_EN - Interrupt Enable */ +/*! @{ */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ + +/*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ + +/*! @name DEBUG_MODE - */ +/*! @{ */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ + +/*! @name DEBUG_MODE2 - */ +/*! @{ */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x400E0000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_DIG_IRQn } +/* Backward compatibility */ +#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT +#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x) + + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command Register */ +/*! @{ */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status Register */ +/*! @{ */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x402E0000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x402E0200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } +#define USBHS_IRQHandler USB_OTG1_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */ + uint8_t RESERVED_1[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ + +/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x402E0000u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x402E0004u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ + +/*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x400D9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x400DA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[416]; + struct { /* offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x400D8000u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x402C0000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x402C4000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +/*! @{ */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ + +/*! @name WSR - Watchdog Service Register */ +/*! @{ */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ + +/*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ + +/*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x400B8000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x400D0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer + * @{ + */ + +/** XBARA - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */ + __IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */ + __IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */ + __IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */ + __IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */ + __IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */ + __IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */ + __IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */ + __IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */ + __IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */ + __IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */ + __IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */ + __IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */ + __IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */ + __IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */ + __IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */ + __IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */ + __IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */ + __IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */ + __IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */ + __IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */ + __IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */ + __IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */ + __IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */ + __IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */ + __IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */ + __IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */ + __IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */ + __IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */ + __IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */ + __IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */ + __IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */ + __IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */ + __IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */ + __IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */ + __IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */ + __IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */ + __IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */ + __IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */ + __IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */ + __IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */ + __IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */ + __IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */ + __IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */ + __IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */ + __IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */ + __IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */ + __IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */ + __IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */ + __IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */ + __IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */ + __IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */ + __IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */ + __IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */ + __IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */ + __IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */ + __IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */ + __IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */ + __IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */ + __IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */ + __IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */ +} XBARA_Type; + +/* ---------------------------------------------------------------------------- + -- XBARA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Register_Masks XBARA Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ +#define XBARA_SEL0_SEL0_MASK (0x7FU) +#define XBARA_SEL0_SEL0_SHIFT (0U) +#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) +#define XBARA_SEL0_SEL1_MASK (0x7F00U) +#define XBARA_SEL0_SEL1_SHIFT (8U) +#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ +#define XBARA_SEL1_SEL2_MASK (0x7FU) +#define XBARA_SEL1_SEL2_SHIFT (0U) +#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) +#define XBARA_SEL1_SEL3_MASK (0x7F00U) +#define XBARA_SEL1_SEL3_SHIFT (8U) +#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ +#define XBARA_SEL2_SEL4_MASK (0x7FU) +#define XBARA_SEL2_SEL4_SHIFT (0U) +#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) +#define XBARA_SEL2_SEL5_MASK (0x7F00U) +#define XBARA_SEL2_SEL5_SHIFT (8U) +#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ +#define XBARA_SEL3_SEL6_MASK (0x7FU) +#define XBARA_SEL3_SEL6_SHIFT (0U) +#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) +#define XBARA_SEL3_SEL7_MASK (0x7F00U) +#define XBARA_SEL3_SEL7_SHIFT (8U) +#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ +#define XBARA_SEL4_SEL8_MASK (0x7FU) +#define XBARA_SEL4_SEL8_SHIFT (0U) +#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) +#define XBARA_SEL4_SEL9_MASK (0x7F00U) +#define XBARA_SEL4_SEL9_SHIFT (8U) +#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ +#define XBARA_SEL5_SEL10_MASK (0x7FU) +#define XBARA_SEL5_SEL10_SHIFT (0U) +#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) +#define XBARA_SEL5_SEL11_MASK (0x7F00U) +#define XBARA_SEL5_SEL11_SHIFT (8U) +#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ +#define XBARA_SEL6_SEL12_MASK (0x7FU) +#define XBARA_SEL6_SEL12_SHIFT (0U) +#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) +#define XBARA_SEL6_SEL13_MASK (0x7F00U) +#define XBARA_SEL6_SEL13_SHIFT (8U) +#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ +#define XBARA_SEL7_SEL14_MASK (0x7FU) +#define XBARA_SEL7_SEL14_SHIFT (0U) +#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) +#define XBARA_SEL7_SEL15_MASK (0x7F00U) +#define XBARA_SEL7_SEL15_SHIFT (8U) +#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ + +/*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ +#define XBARA_SEL8_SEL16_MASK (0x7FU) +#define XBARA_SEL8_SEL16_SHIFT (0U) +#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) +#define XBARA_SEL8_SEL17_MASK (0x7F00U) +#define XBARA_SEL8_SEL17_SHIFT (8U) +#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ + +/*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ +#define XBARA_SEL9_SEL18_MASK (0x7FU) +#define XBARA_SEL9_SEL18_SHIFT (0U) +#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) +#define XBARA_SEL9_SEL19_MASK (0x7F00U) +#define XBARA_SEL9_SEL19_SHIFT (8U) +#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ + +/*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ +#define XBARA_SEL10_SEL20_MASK (0x7FU) +#define XBARA_SEL10_SEL20_SHIFT (0U) +#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) +#define XBARA_SEL10_SEL21_MASK (0x7F00U) +#define XBARA_SEL10_SEL21_SHIFT (8U) +#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ + +/*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ +#define XBARA_SEL11_SEL22_MASK (0x7FU) +#define XBARA_SEL11_SEL22_SHIFT (0U) +#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) +#define XBARA_SEL11_SEL23_MASK (0x7F00U) +#define XBARA_SEL11_SEL23_SHIFT (8U) +#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ + +/*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ +#define XBARA_SEL12_SEL24_MASK (0x7FU) +#define XBARA_SEL12_SEL24_SHIFT (0U) +#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) +#define XBARA_SEL12_SEL25_MASK (0x7F00U) +#define XBARA_SEL12_SEL25_SHIFT (8U) +#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ + +/*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ +#define XBARA_SEL13_SEL26_MASK (0x7FU) +#define XBARA_SEL13_SEL26_SHIFT (0U) +#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) +#define XBARA_SEL13_SEL27_MASK (0x7F00U) +#define XBARA_SEL13_SEL27_SHIFT (8U) +#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ + +/*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ +#define XBARA_SEL14_SEL28_MASK (0x7FU) +#define XBARA_SEL14_SEL28_SHIFT (0U) +#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) +#define XBARA_SEL14_SEL29_MASK (0x7F00U) +#define XBARA_SEL14_SEL29_SHIFT (8U) +#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ + +/*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ +#define XBARA_SEL15_SEL30_MASK (0x7FU) +#define XBARA_SEL15_SEL30_SHIFT (0U) +#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) +#define XBARA_SEL15_SEL31_MASK (0x7F00U) +#define XBARA_SEL15_SEL31_SHIFT (8U) +#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ + +/*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ +#define XBARA_SEL16_SEL32_MASK (0x7FU) +#define XBARA_SEL16_SEL32_SHIFT (0U) +#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) +#define XBARA_SEL16_SEL33_MASK (0x7F00U) +#define XBARA_SEL16_SEL33_SHIFT (8U) +#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ + +/*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ +#define XBARA_SEL17_SEL34_MASK (0x7FU) +#define XBARA_SEL17_SEL34_SHIFT (0U) +#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) +#define XBARA_SEL17_SEL35_MASK (0x7F00U) +#define XBARA_SEL17_SEL35_SHIFT (8U) +#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ + +/*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ +#define XBARA_SEL18_SEL36_MASK (0x7FU) +#define XBARA_SEL18_SEL36_SHIFT (0U) +#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) +#define XBARA_SEL18_SEL37_MASK (0x7F00U) +#define XBARA_SEL18_SEL37_SHIFT (8U) +#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ + +/*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ +#define XBARA_SEL19_SEL38_MASK (0x7FU) +#define XBARA_SEL19_SEL38_SHIFT (0U) +#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) +#define XBARA_SEL19_SEL39_MASK (0x7F00U) +#define XBARA_SEL19_SEL39_SHIFT (8U) +#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ + +/*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ +#define XBARA_SEL20_SEL40_MASK (0x7FU) +#define XBARA_SEL20_SEL40_SHIFT (0U) +#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) +#define XBARA_SEL20_SEL41_MASK (0x7F00U) +#define XBARA_SEL20_SEL41_SHIFT (8U) +#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ + +/*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ +#define XBARA_SEL21_SEL42_MASK (0x7FU) +#define XBARA_SEL21_SEL42_SHIFT (0U) +#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) +#define XBARA_SEL21_SEL43_MASK (0x7F00U) +#define XBARA_SEL21_SEL43_SHIFT (8U) +#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ + +/*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ +#define XBARA_SEL22_SEL44_MASK (0x7FU) +#define XBARA_SEL22_SEL44_SHIFT (0U) +#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) +#define XBARA_SEL22_SEL45_MASK (0x7F00U) +#define XBARA_SEL22_SEL45_SHIFT (8U) +#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ + +/*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ +#define XBARA_SEL23_SEL46_MASK (0x7FU) +#define XBARA_SEL23_SEL46_SHIFT (0U) +#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) +#define XBARA_SEL23_SEL47_MASK (0x7F00U) +#define XBARA_SEL23_SEL47_SHIFT (8U) +#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ + +/*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ +#define XBARA_SEL24_SEL48_MASK (0x7FU) +#define XBARA_SEL24_SEL48_SHIFT (0U) +#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) +#define XBARA_SEL24_SEL49_MASK (0x7F00U) +#define XBARA_SEL24_SEL49_SHIFT (8U) +#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ + +/*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ +#define XBARA_SEL25_SEL50_MASK (0x7FU) +#define XBARA_SEL25_SEL50_SHIFT (0U) +#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) +#define XBARA_SEL25_SEL51_MASK (0x7F00U) +#define XBARA_SEL25_SEL51_SHIFT (8U) +#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ + +/*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ +#define XBARA_SEL26_SEL52_MASK (0x7FU) +#define XBARA_SEL26_SEL52_SHIFT (0U) +#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) +#define XBARA_SEL26_SEL53_MASK (0x7F00U) +#define XBARA_SEL26_SEL53_SHIFT (8U) +#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ + +/*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ +#define XBARA_SEL27_SEL54_MASK (0x7FU) +#define XBARA_SEL27_SEL54_SHIFT (0U) +#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) +#define XBARA_SEL27_SEL55_MASK (0x7F00U) +#define XBARA_SEL27_SEL55_SHIFT (8U) +#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ + +/*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ +#define XBARA_SEL28_SEL56_MASK (0x7FU) +#define XBARA_SEL28_SEL56_SHIFT (0U) +#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) +#define XBARA_SEL28_SEL57_MASK (0x7F00U) +#define XBARA_SEL28_SEL57_SHIFT (8U) +#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ + +/*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ +#define XBARA_SEL29_SEL58_MASK (0x7FU) +#define XBARA_SEL29_SEL58_SHIFT (0U) +#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) +#define XBARA_SEL29_SEL59_MASK (0x7F00U) +#define XBARA_SEL29_SEL59_SHIFT (8U) +#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ + +/*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ +#define XBARA_SEL30_SEL60_MASK (0x7FU) +#define XBARA_SEL30_SEL60_SHIFT (0U) +#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) +#define XBARA_SEL30_SEL61_MASK (0x7F00U) +#define XBARA_SEL30_SEL61_SHIFT (8U) +#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ + +/*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ +#define XBARA_SEL31_SEL62_MASK (0x7FU) +#define XBARA_SEL31_SEL62_SHIFT (0U) +#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) +#define XBARA_SEL31_SEL63_MASK (0x7F00U) +#define XBARA_SEL31_SEL63_SHIFT (8U) +#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ + +/*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ +#define XBARA_SEL32_SEL64_MASK (0x7FU) +#define XBARA_SEL32_SEL64_SHIFT (0U) +#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) +#define XBARA_SEL32_SEL65_MASK (0x7F00U) +#define XBARA_SEL32_SEL65_SHIFT (8U) +#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ + +/*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ +#define XBARA_SEL33_SEL66_MASK (0x7FU) +#define XBARA_SEL33_SEL66_SHIFT (0U) +#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) +#define XBARA_SEL33_SEL67_MASK (0x7F00U) +#define XBARA_SEL33_SEL67_SHIFT (8U) +#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ + +/*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ +#define XBARA_SEL34_SEL68_MASK (0x7FU) +#define XBARA_SEL34_SEL68_SHIFT (0U) +#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) +#define XBARA_SEL34_SEL69_MASK (0x7F00U) +#define XBARA_SEL34_SEL69_SHIFT (8U) +#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ + +/*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ +#define XBARA_SEL35_SEL70_MASK (0x7FU) +#define XBARA_SEL35_SEL70_SHIFT (0U) +#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) +#define XBARA_SEL35_SEL71_MASK (0x7F00U) +#define XBARA_SEL35_SEL71_SHIFT (8U) +#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ + +/*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ +#define XBARA_SEL36_SEL72_MASK (0x7FU) +#define XBARA_SEL36_SEL72_SHIFT (0U) +#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) +#define XBARA_SEL36_SEL73_MASK (0x7F00U) +#define XBARA_SEL36_SEL73_SHIFT (8U) +#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ + +/*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ +#define XBARA_SEL37_SEL74_MASK (0x7FU) +#define XBARA_SEL37_SEL74_SHIFT (0U) +#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) +#define XBARA_SEL37_SEL75_MASK (0x7F00U) +#define XBARA_SEL37_SEL75_SHIFT (8U) +#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ + +/*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ +#define XBARA_SEL38_SEL76_MASK (0x7FU) +#define XBARA_SEL38_SEL76_SHIFT (0U) +#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) +#define XBARA_SEL38_SEL77_MASK (0x7F00U) +#define XBARA_SEL38_SEL77_SHIFT (8U) +#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ + +/*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ +#define XBARA_SEL39_SEL78_MASK (0x7FU) +#define XBARA_SEL39_SEL78_SHIFT (0U) +#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) +#define XBARA_SEL39_SEL79_MASK (0x7F00U) +#define XBARA_SEL39_SEL79_SHIFT (8U) +#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ + +/*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ +#define XBARA_SEL40_SEL80_MASK (0x7FU) +#define XBARA_SEL40_SEL80_SHIFT (0U) +#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) +#define XBARA_SEL40_SEL81_MASK (0x7F00U) +#define XBARA_SEL40_SEL81_SHIFT (8U) +#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ + +/*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ +#define XBARA_SEL41_SEL82_MASK (0x7FU) +#define XBARA_SEL41_SEL82_SHIFT (0U) +#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) +#define XBARA_SEL41_SEL83_MASK (0x7F00U) +#define XBARA_SEL41_SEL83_SHIFT (8U) +#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ + +/*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ +#define XBARA_SEL42_SEL84_MASK (0x7FU) +#define XBARA_SEL42_SEL84_SHIFT (0U) +#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) +#define XBARA_SEL42_SEL85_MASK (0x7F00U) +#define XBARA_SEL42_SEL85_SHIFT (8U) +#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ + +/*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ +#define XBARA_SEL43_SEL86_MASK (0x7FU) +#define XBARA_SEL43_SEL86_SHIFT (0U) +#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) +#define XBARA_SEL43_SEL87_MASK (0x7F00U) +#define XBARA_SEL43_SEL87_SHIFT (8U) +#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ + +/*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ +#define XBARA_SEL44_SEL88_MASK (0x7FU) +#define XBARA_SEL44_SEL88_SHIFT (0U) +#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) +#define XBARA_SEL44_SEL89_MASK (0x7F00U) +#define XBARA_SEL44_SEL89_SHIFT (8U) +#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ + +/*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ +#define XBARA_SEL45_SEL90_MASK (0x7FU) +#define XBARA_SEL45_SEL90_SHIFT (0U) +#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) +#define XBARA_SEL45_SEL91_MASK (0x7F00U) +#define XBARA_SEL45_SEL91_SHIFT (8U) +#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ + +/*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ +#define XBARA_SEL46_SEL92_MASK (0x7FU) +#define XBARA_SEL46_SEL92_SHIFT (0U) +#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) +#define XBARA_SEL46_SEL93_MASK (0x7F00U) +#define XBARA_SEL46_SEL93_SHIFT (8U) +#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ + +/*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ +#define XBARA_SEL47_SEL94_MASK (0x7FU) +#define XBARA_SEL47_SEL94_SHIFT (0U) +#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) +#define XBARA_SEL47_SEL95_MASK (0x7F00U) +#define XBARA_SEL47_SEL95_SHIFT (8U) +#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ + +/*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ +#define XBARA_SEL48_SEL96_MASK (0x7FU) +#define XBARA_SEL48_SEL96_SHIFT (0U) +#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) +#define XBARA_SEL48_SEL97_MASK (0x7F00U) +#define XBARA_SEL48_SEL97_SHIFT (8U) +#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ + +/*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ +#define XBARA_SEL49_SEL98_MASK (0x7FU) +#define XBARA_SEL49_SEL98_SHIFT (0U) +#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) +#define XBARA_SEL49_SEL99_MASK (0x7F00U) +#define XBARA_SEL49_SEL99_SHIFT (8U) +#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ + +/*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ +#define XBARA_SEL50_SEL100_MASK (0x7FU) +#define XBARA_SEL50_SEL100_SHIFT (0U) +#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) +#define XBARA_SEL50_SEL101_MASK (0x7F00U) +#define XBARA_SEL50_SEL101_SHIFT (8U) +#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ + +/*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ +#define XBARA_SEL51_SEL102_MASK (0x7FU) +#define XBARA_SEL51_SEL102_SHIFT (0U) +#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) +#define XBARA_SEL51_SEL103_MASK (0x7F00U) +#define XBARA_SEL51_SEL103_SHIFT (8U) +#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ + +/*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ +#define XBARA_SEL52_SEL104_MASK (0x7FU) +#define XBARA_SEL52_SEL104_SHIFT (0U) +#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) +#define XBARA_SEL52_SEL105_MASK (0x7F00U) +#define XBARA_SEL52_SEL105_SHIFT (8U) +#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ + +/*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ +#define XBARA_SEL53_SEL106_MASK (0x7FU) +#define XBARA_SEL53_SEL106_SHIFT (0U) +#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) +#define XBARA_SEL53_SEL107_MASK (0x7F00U) +#define XBARA_SEL53_SEL107_SHIFT (8U) +#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ + +/*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ +#define XBARA_SEL54_SEL108_MASK (0x7FU) +#define XBARA_SEL54_SEL108_SHIFT (0U) +#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) +#define XBARA_SEL54_SEL109_MASK (0x7F00U) +#define XBARA_SEL54_SEL109_SHIFT (8U) +#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ + +/*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ +#define XBARA_SEL55_SEL110_MASK (0x7FU) +#define XBARA_SEL55_SEL110_SHIFT (0U) +#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) +#define XBARA_SEL55_SEL111_MASK (0x7F00U) +#define XBARA_SEL55_SEL111_SHIFT (8U) +#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ + +/*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ +#define XBARA_SEL56_SEL112_MASK (0x7FU) +#define XBARA_SEL56_SEL112_SHIFT (0U) +#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) +#define XBARA_SEL56_SEL113_MASK (0x7F00U) +#define XBARA_SEL56_SEL113_SHIFT (8U) +#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ + +/*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ +#define XBARA_SEL57_SEL114_MASK (0x7FU) +#define XBARA_SEL57_SEL114_SHIFT (0U) +#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) +#define XBARA_SEL57_SEL115_MASK (0x7F00U) +#define XBARA_SEL57_SEL115_SHIFT (8U) +#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ + +/*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ +#define XBARA_SEL58_SEL116_MASK (0x7FU) +#define XBARA_SEL58_SEL116_SHIFT (0U) +#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) +#define XBARA_SEL58_SEL117_MASK (0x7F00U) +#define XBARA_SEL58_SEL117_SHIFT (8U) +#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ + +/*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ +#define XBARA_SEL59_SEL118_MASK (0x7FU) +#define XBARA_SEL59_SEL118_SHIFT (0U) +#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) +#define XBARA_SEL59_SEL119_MASK (0x7F00U) +#define XBARA_SEL59_SEL119_SHIFT (8U) +#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ + +/*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ +#define XBARA_SEL60_SEL120_MASK (0x7FU) +#define XBARA_SEL60_SEL120_SHIFT (0U) +#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) +#define XBARA_SEL60_SEL121_MASK (0x7F00U) +#define XBARA_SEL60_SEL121_SHIFT (8U) +#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ + +/*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ +#define XBARA_SEL61_SEL122_MASK (0x7FU) +#define XBARA_SEL61_SEL122_SHIFT (0U) +#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) +#define XBARA_SEL61_SEL123_MASK (0x7F00U) +#define XBARA_SEL61_SEL123_SHIFT (8U) +#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ + +/*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ +#define XBARA_SEL62_SEL124_MASK (0x7FU) +#define XBARA_SEL62_SEL124_SHIFT (0U) +#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) +#define XBARA_SEL62_SEL125_MASK (0x7F00U) +#define XBARA_SEL62_SEL125_SHIFT (8U) +#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ + +/*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ +#define XBARA_SEL63_SEL126_MASK (0x7FU) +#define XBARA_SEL63_SEL126_SHIFT (0U) +#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) +#define XBARA_SEL63_SEL127_MASK (0x7F00U) +#define XBARA_SEL63_SEL127_SHIFT (8U) +#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ + +/*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ +#define XBARA_SEL64_SEL128_MASK (0x7FU) +#define XBARA_SEL64_SEL128_SHIFT (0U) +#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) +#define XBARA_SEL64_SEL129_MASK (0x7F00U) +#define XBARA_SEL64_SEL129_SHIFT (8U) +#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ + +/*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ +#define XBARA_SEL65_SEL130_MASK (0x7FU) +#define XBARA_SEL65_SEL130_SHIFT (0U) +#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) +#define XBARA_SEL65_SEL131_MASK (0x7F00U) +#define XBARA_SEL65_SEL131_SHIFT (8U) +#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ + +/*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ +#define XBARA_CTRL0_DEN0_MASK (0x1U) +#define XBARA_CTRL0_DEN0_SHIFT (0U) +#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) +#define XBARA_CTRL0_IEN0_MASK (0x2U) +#define XBARA_CTRL0_IEN0_SHIFT (1U) +#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) +#define XBARA_CTRL0_EDGE0_MASK (0xCU) +#define XBARA_CTRL0_EDGE0_SHIFT (2U) +#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) +#define XBARA_CTRL0_STS0_MASK (0x10U) +#define XBARA_CTRL0_STS0_SHIFT (4U) +#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) +#define XBARA_CTRL0_DEN1_MASK (0x100U) +#define XBARA_CTRL0_DEN1_SHIFT (8U) +#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) +#define XBARA_CTRL0_IEN1_MASK (0x200U) +#define XBARA_CTRL0_IEN1_SHIFT (9U) +#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) +#define XBARA_CTRL0_EDGE1_MASK (0xC00U) +#define XBARA_CTRL0_EDGE1_SHIFT (10U) +#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) +#define XBARA_CTRL0_STS1_MASK (0x1000U) +#define XBARA_CTRL0_STS1_SHIFT (12U) +#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ + +/*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ +#define XBARA_CTRL1_DEN2_MASK (0x1U) +#define XBARA_CTRL1_DEN2_SHIFT (0U) +#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) +#define XBARA_CTRL1_IEN2_MASK (0x2U) +#define XBARA_CTRL1_IEN2_SHIFT (1U) +#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) +#define XBARA_CTRL1_EDGE2_MASK (0xCU) +#define XBARA_CTRL1_EDGE2_SHIFT (2U) +#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) +#define XBARA_CTRL1_STS2_MASK (0x10U) +#define XBARA_CTRL1_STS2_SHIFT (4U) +#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) +#define XBARA_CTRL1_DEN3_MASK (0x100U) +#define XBARA_CTRL1_DEN3_SHIFT (8U) +#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) +#define XBARA_CTRL1_IEN3_MASK (0x200U) +#define XBARA_CTRL1_IEN3_SHIFT (9U) +#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) +#define XBARA_CTRL1_EDGE3_MASK (0xC00U) +#define XBARA_CTRL1_EDGE3_SHIFT (10U) +#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) +#define XBARA_CTRL1_STS3_MASK (0x1000U) +#define XBARA_CTRL1_STS3_SHIFT (12U) +#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARA_Register_Masks */ + + +/* XBARA - Peripheral instance base addresses */ +/** Peripheral XBARA1 base address */ +#define XBARA1_BASE (0x403BC000u) +/** Peripheral XBARA1 base pointer */ +#define XBARA1 ((XBARA_Type *)XBARA1_BASE) +/** Array initializer of XBARA peripheral base addresses */ +#define XBARA_BASE_ADDRS { XBARA1_BASE } +/** Array initializer of XBARA peripheral base pointers */ +#define XBARA_BASE_PTRS { XBARA1 } + +/*! + * @} + */ /* end of group XBARA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer + * @{ + */ + +/** XBARB - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */ +} XBARB_Type; + +/* ---------------------------------------------------------------------------- + -- XBARB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Register_Masks XBARB Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ +#define XBARB_SEL0_SEL0_MASK (0x3FU) +#define XBARB_SEL0_SEL0_SHIFT (0U) +#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) +#define XBARB_SEL0_SEL1_MASK (0x3F00U) +#define XBARB_SEL0_SEL1_SHIFT (8U) +#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ +#define XBARB_SEL1_SEL2_MASK (0x3FU) +#define XBARB_SEL1_SEL2_SHIFT (0U) +#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) +#define XBARB_SEL1_SEL3_MASK (0x3F00U) +#define XBARB_SEL1_SEL3_SHIFT (8U) +#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ +#define XBARB_SEL2_SEL4_MASK (0x3FU) +#define XBARB_SEL2_SEL4_SHIFT (0U) +#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) +#define XBARB_SEL2_SEL5_MASK (0x3F00U) +#define XBARB_SEL2_SEL5_SHIFT (8U) +#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ +#define XBARB_SEL3_SEL6_MASK (0x3FU) +#define XBARB_SEL3_SEL6_SHIFT (0U) +#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) +#define XBARB_SEL3_SEL7_MASK (0x3F00U) +#define XBARB_SEL3_SEL7_SHIFT (8U) +#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ +#define XBARB_SEL4_SEL8_MASK (0x3FU) +#define XBARB_SEL4_SEL8_SHIFT (0U) +#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) +#define XBARB_SEL4_SEL9_MASK (0x3F00U) +#define XBARB_SEL4_SEL9_SHIFT (8U) +#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ +#define XBARB_SEL5_SEL10_MASK (0x3FU) +#define XBARB_SEL5_SEL10_SHIFT (0U) +#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) +#define XBARB_SEL5_SEL11_MASK (0x3F00U) +#define XBARB_SEL5_SEL11_SHIFT (8U) +#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ +#define XBARB_SEL6_SEL12_MASK (0x3FU) +#define XBARB_SEL6_SEL12_SHIFT (0U) +#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) +#define XBARB_SEL6_SEL13_MASK (0x3F00U) +#define XBARB_SEL6_SEL13_SHIFT (8U) +#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ +#define XBARB_SEL7_SEL14_MASK (0x3FU) +#define XBARB_SEL7_SEL14_SHIFT (0U) +#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) +#define XBARB_SEL7_SEL15_MASK (0x3F00U) +#define XBARB_SEL7_SEL15_SHIFT (8U) +#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARB_Register_Masks */ + + +/* XBARB - Peripheral instance base addresses */ +/** Peripheral XBARB2 base address */ +#define XBARB2_BASE (0x403C0000u) +/** Peripheral XBARB2 base pointer */ +#define XBARB2 ((XBARB_Type *)XBARB2_BASE) +/** Peripheral XBARB3 base address */ +#define XBARB3_BASE (0x403C4000u) +/** Peripheral XBARB3 base pointer */ +#define XBARB3 ((XBARB_Type *)XBARB3_BASE) +/** Array initializer of XBARB peripheral base addresses */ +#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE } +/** Array initializer of XBARB peripheral base pointers */ +#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 } + +/*! + * @} + */ /* end of group XBARB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + uint8_t RESERVED_1[272]; + __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ + uint8_t RESERVED_2[32]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x400D8000u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MIMXRT1052_H_ */ + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052.xml b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052.xml new file mode 100644 index 0000000000..6951ad8763 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052.xml @@ -0,0 +1,196945 @@ + + + nxp.com + MIMXRT1052 + 1.0 + MIMXRT1052DVL6B + +The Clear BSD License +Copyright 2016-2018 NXP +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted (subject to the limitations in the +disclaimer below) provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + + CM7 + r0p1 + little + true + true + true + 4 + false + + 8 + 32 + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + AIPSTZ + 0x4007C000 + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x77000000 + 0xFFFFFFFF + + + MPROT5 + Master 5 Priviledge, Buffer, Read, Write Control. + 8 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT3 + Master 3 Priviledge, Buffer, Read, Write Control. + 16 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT2 + Master 2 Priviledge, Buffer, Read, Write Control + 20 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT1 + Master 1 Priviledge, Buffer, Read, Write Control + 24 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT0 + Master 0 Priviledge, Buffer, Read, Write Control + 28 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + Off-platform Peripheral Access Control 7 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC6 + Off-platform Peripheral Access Control 6 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC5 + Off-platform Peripheral Access Control 5 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC4 + Off-platform Peripheral Access Control 4 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC3 + Off-platform Peripheral Access Control 3 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC2 + Off-platform Peripheral Access Control 2 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC1 + Off-platform Peripheral Access Control 1 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC0 + Off-platform Peripheral Access Control 0 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + Off-platform Peripheral Access Control 15 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC14 + Off-platform Peripheral Access Control 14 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC13 + Off-platform Peripheral Access Control 13 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC12 + Off-platform Peripheral Access Control 12 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC11 + Off-platform Peripheral Access Control 11 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC10 + Off-platform Peripheral Access Control 10 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC9 + Off-platform Peripheral Access Control 9 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC8 + Off-platform Peripheral Access Control 8 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + Off-platform Peripheral Access Control 23 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC22 + Off-platform Peripheral Access Control 22 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC21 + Off-platform Peripheral Access Control 21 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC20 + Off-platform Peripheral Access Control 20 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC19 + Off-platform Peripheral Access Control 19 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC18 + Off-platform Peripheral Access Control 18 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC17 + Off-platform Peripheral Access Control 17 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC16 + Off-platform Peripheral Access Control 16 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + Off-platform Peripheral Access Control 31 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC30 + Off-platform Peripheral Access Control 30 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC29 + Off-platform Peripheral Access Control 29 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC28 + Off-platform Peripheral Access Control 28 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC27 + Off-platform Peripheral Access Control 27 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC26 + Off-platform Peripheral Access Control 26 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC25 + Off-platform Peripheral Access Control 25 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC24 + Off-platform Peripheral Access Control 24 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC33 + Off-platform Peripheral Access Control 33 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC32 + Off-platform Peripheral Access Control 32 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x4017C000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ3_ + 0x4027C000 + + 0 + 0x54 + registers + + + + AIPSTZ4 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ4_ + 0x4037C000 + + 0 + 0x54 + registers + + + + DCDC + DCDC + DCDC + 0x40080000 + + 0 + 0x10 + registers + + + DCDC + 69 + + + + REG0 + DCDC Register 0 + 0 + 32 + read-write + 0x14030111 + 0xFFFFFFFF + + + PWD_ZCD + power down the zero cross detection function for discontinuous conductor mode + 0 + 1 + read-write + + + DISABLE_AUTO_CLK_SWITCH + Disable automatic clock switch from internal osc to xtal clock. + 1 + 1 + read-write + + + SEL_CLK + select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set. + 2 + 1 + read-write + + + PWD_OSC_INT + Power down internal osc. Only set this bit, when 24 MHz crystal osc is available + 3 + 1 + read-write + + + PWD_CUR_SNS_CMP + The power down signal of the current detector. + 4 + 1 + read-write + + + CUR_SNS_THRSH + Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert + 5 + 3 + read-write + + + PWD_OVERCUR_DET + power down overcurrent detection comparator + 8 + 1 + read-write + + + OVERCUR_TRIG_ADJ + The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0 + 9 + 2 + read-write + + + PWD_CMP_BATT_DET + set to "1" to power down the low voltage detection comparator + 11 + 1 + read-write + + + ADJ_POSLIMIT_BUCK + adjust value to poslimit_buck register + 12 + 4 + read-write + + + EN_LP_OVERLOAD_SNS + enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically + 16 + 1 + read-write + + + PWD_HIGH_VOLT_DET + power down overvoltage detection comparator + 17 + 1 + read-write + + + LP_OVERLOAD_THRSH + the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode + 18 + 2 + read-write + + + LP_OVERLOAD_FREQ_SEL + the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle + 20 + 1 + read-write + + + LP_HIGH_HYS + Adjust hysteretic value in low power from 12.5mV to 25mV + 21 + 1 + read-write + + + PWD_CMP_OFFSET + power down output range comparator + 26 + 1 + read-write + + + XTALOK_DISABLE + 1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit + 27 + 1 + read-write + + + CURRENT_ALERT_RESET + reset current alert signal + 28 + 1 + read-write + + + XTAL_24M_OK + set to 1 to switch internal ring osc to xtal 24M + 29 + 1 + read-write + + + STS_DC_OK + Status register to indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling + 31 + 1 + read-only + + + + + REG1 + DCDC Register 1 + 0x4 + 32 + read-write + 0x111BA29C + 0xFFFFFFFF + + + REG_FBK_SEL + select the feedback point of the internal regulator + 7 + 2 + read-write + + + REG_RLOAD_SW + control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor + 9 + 1 + read-write + + + LP_CMP_ISRC_SEL + set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA + 12 + 2 + read-write + + + LOOPCTRL_HST_THRESH + increase the threshold detection for common mode analog comparator + 21 + 1 + read-write + + + LOOPCTRL_EN_HYST + Enable hysteresis in switching converter common mode analog comparators + 23 + 1 + read-write + + + VBG_TRIM + trim bandgap voltage + 24 + 5 + read-write + + + + + REG2 + DCDC Register 2 + 0x8 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + LOOPCTRL_DC_C + Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response + 0 + 2 + read-write + + + LOOPCTRL_DC_R + Magnitude of proportional control parameter in the switching DC-DC converter control loop. + 2 + 4 + read-write + + + LOOPCTRL_DC_FF + Two's complement feed forward step in duty cycle in the switching DC-DC converter + 6 + 3 + read-write + + + LOOPCTRL_EN_RCSCALE + Enable analog circuit of DC-DC converter to respond faster under transient load conditions. + 9 + 3 + read-write + + + LOOPCTRL_RCSCALE_THRSH + Increase the threshold detection for RC scale circuit. + 12 + 1 + read-write + + + LOOPCTRL_HYST_SIGN + Invert the sign of the hysteresis in DC-DC analog comparators. + 13 + 1 + read-write + + + DISABLE_PULSE_SKIP + Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in + 27 + 1 + read-write + + + DCM_SET_CTRL + Set high to improve the transition from heavy load to light load + 28 + 1 + read-write + + + + + REG3 + DCDC Register 3 + 0xC + 32 + read-write + 0x10E + 0xFFFFFFFF + + + TRG + Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V + 0 + 5 + read-write + + + TARGET_LP + Target value of standby (low power) mode 0x0: 0 + 8 + 3 + read-write + + + MINPWR_DC_HALFCLK + Set DCDC clock to half freqeuncy for continuous mode + 24 + 1 + read-write + + + MISC_DELAY_TIMING + Ajust delay to reduce ground noise + 27 + 1 + read-write + + + MISC_DISABLEFET_LOGIC + Reserved + 28 + 1 + read-write + + + DISABLE_STEP + Disable stepping for the output VDD_SOC of DCDC + 30 + 1 + read-write + + + + + + + PIT + PIT + PIT + 0x40084000 + + 0 + 0x140 + registers + + + PIT + 122 + + + + MCR + PIT Module Control Register + 0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + FRZ + Freeze + 0 + 1 + read-write + + + FRZ_0 + Timers continue to run in Debug mode. + 0 + + + FRZ_1 + Timers are stopped in Debug mode. + 0x1 + + + + + MDIS + Module Disable - (PIT section) + 1 + 1 + read-write + + + MDIS_0 + Clock for standard PIT timers is enabled. + 0 + + + MDIS_1 + Clock for standard PIT timers is disabled. + 0x1 + + + + + + + LTMR64H + PIT Upper Lifetime Timer Register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTH + Life Timer value + 0 + 32 + read-only + + + + + LTMR64L + PIT Lower Lifetime Timer Register + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTL + Life Timer value + 0 + 32 + read-only + + + + + 4 + 0x10 + TIMER[%s] + no description available + 0x100 + + LDVAL + Timer Load Value Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSV + Timer Start Value + 0 + 32 + read-write + + + + + CVAL + Current Timer Value Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + TVL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL + Timer Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + TEN_0 + Timer n is disabled. + 0 + + + TEN_1 + Timer n is enabled. + 0x1 + + + + + TIE + Timer Interrupt Enable + 1 + 1 + read-write + + + TIE_0 + Interrupt requests from Timer n are disabled. + 0 + + + TIE_1 + Interrupt will be requested whenever TIF is set. + 0x1 + + + + + CHN + Chain Mode + 2 + 1 + read-write + + + CHN_0 + Timer is not chained. + 0 + + + CHN_1 + Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + 0x1 + + + + + + + TFLG + Timer Flag Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TIF + Timer Interrupt Flag + 0 + 1 + read-write + oneToClear + + + TIF_0 + Timeout has not yet occurred. + 0 + + + TIF_1 + Timeout has occurred. + 0x1 + + + + + + + + + + CMP1 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP1_ + ACMP + 0x40094000 + + 0 + 0x6 + registers + + + ACMP1 + 123 + + + + CR0 + CMP Control Register 0 + 0 + 8 + read-write + 0 + 0xFF + + + HYSTCTR + Comparator hard block hysteresis control + 0 + 2 + read-write + + + HYSTCTR_0 + Level 0 + 0 + + + HYSTCTR_1 + Level 1 + 0x1 + + + HYSTCTR_2 + Level 2 + 0x2 + + + HYSTCTR_3 + Level 3 + 0x3 + + + + + FILTER_CNT + Filter Sample Count + 4 + 3 + read-write + + + FILTER_CNT_0 + Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + 0 + + + FILTER_CNT_1 + One sample must agree. The comparator output is simply sampled. + 0x1 + + + FILTER_CNT_2 + 2 consecutive samples must agree. + 0x2 + + + FILTER_CNT_3 + 3 consecutive samples must agree. + 0x3 + + + FILTER_CNT_4 + 4 consecutive samples must agree. + 0x4 + + + FILTER_CNT_5 + 5 consecutive samples must agree. + 0x5 + + + FILTER_CNT_6 + 6 consecutive samples must agree. + 0x6 + + + FILTER_CNT_7 + 7 consecutive samples must agree. + 0x7 + + + + + + + CR1 + CMP Control Register 1 + 0x1 + 8 + read-write + 0 + 0xFF + + + EN + Comparator Module Enable + 0 + 1 + read-write + + + EN_0 + Analog Comparator is disabled. + 0 + + + EN_1 + Analog Comparator is enabled. + 0x1 + + + + + OPE + Comparator Output Pin Enable + 1 + 1 + read-write + + + OPE_0 + CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + 0 + + + OPE_1 + CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + 0x1 + + + + + COS + Comparator Output Select + 2 + 1 + read-write + + + COS_0 + Set the filtered comparator output (CMPO) to equal COUT. + 0 + + + COS_1 + Set the unfiltered comparator output (CMPO) to equal COUTA. + 0x1 + + + + + INV + Comparator INVERT + 3 + 1 + read-write + + + INV_0 + Does not invert the comparator output. + 0 + + + INV_1 + Inverts the comparator output. + 0x1 + + + + + PMODE + Power Mode Select + 4 + 1 + read-write + + + PMODE_0 + Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + 0 + + + PMODE_1 + High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + 0x1 + + + + + WE + Windowing Enable + 6 + 1 + read-write + + + WE_0 + Windowing mode is not selected. + 0 + + + WE_1 + Windowing mode is selected. + 0x1 + + + + + SE + Sample Enable + 7 + 1 + read-write + + + SE_0 + Sampling mode is not selected. + 0 + + + SE_1 + Sampling mode is selected. + 0x1 + + + + + + + FPR + CMP Filter Period Register + 0x2 + 8 + read-write + 0 + 0xFF + + + FILT_PER + Filter Sample Period + 0 + 8 + read-write + + + + + SCR + CMP Status and Control Register + 0x3 + 8 + read-write + 0 + 0xFF + + + COUT + Analog Comparator Output + 0 + 1 + read-only + + + CFF + Analog Comparator Flag Falling + 1 + 1 + read-write + oneToClear + + + CFF_0 + Falling-edge on COUT has not been detected. + 0 + + + CFF_1 + Falling-edge on COUT has occurred. + 0x1 + + + + + CFR + Analog Comparator Flag Rising + 2 + 1 + read-write + oneToClear + + + CFR_0 + Rising-edge on COUT has not been detected. + 0 + + + CFR_1 + Rising-edge on COUT has occurred. + 0x1 + + + + + IEF + Comparator Interrupt Enable Falling + 3 + 1 + read-write + + + IEF_0 + Interrupt is disabled. + 0 + + + IEF_1 + Interrupt is enabled. + 0x1 + + + + + IER + Comparator Interrupt Enable Rising + 4 + 1 + read-write + + + IER_0 + Interrupt is disabled. + 0 + + + IER_1 + Interrupt is enabled. + 0x1 + + + + + DMAEN + DMA Enable Control + 6 + 1 + read-write + + + DMAEN_0 + DMA is disabled. + 0 + + + DMAEN_1 + DMA is enabled. + 0x1 + + + + + + + DACCR + DAC Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + VOSEL + DAC Output Voltage Select + 0 + 6 + read-write + + + VRSEL + Supply Voltage Reference Source Select + 6 + 1 + read-write + + + VRSEL_0 + Vin1 is selected as resistor ladder network supply reference. + 0 + + + VRSEL_1 + Vin2 is selected as resistor ladder network supply reference. + 0x1 + + + + + DACEN + DAC Enable + 7 + 1 + read-write + + + DACEN_0 + DAC is disabled. + 0 + + + DACEN_1 + DAC is enabled. + 0x1 + + + + + + + MUXCR + MUX Control Register + 0x5 + 8 + read-write + 0 + 0xFF + + + MSEL + Minus Input Mux Control + 0 + 3 + read-write + + + MSEL_0 + IN0 + 0 + + + MSEL_1 + IN1 + 0x1 + + + MSEL_2 + IN2 + 0x2 + + + MSEL_3 + IN3 + 0x3 + + + MSEL_4 + IN4 + 0x4 + + + MSEL_5 + IN5 + 0x5 + + + MSEL_6 + IN6 + 0x6 + + + MSEL_7 + IN7 + 0x7 + + + + + PSEL + Plus Input Mux Control + 3 + 3 + read-write + + + PSEL_0 + IN0 + 0 + + + PSEL_1 + IN1 + 0x1 + + + PSEL_2 + IN2 + 0x2 + + + PSEL_3 + IN3 + 0x3 + + + PSEL_4 + IN4 + 0x4 + + + PSEL_5 + IN5 + 0x5 + + + PSEL_6 + IN6 + 0x6 + + + PSEL_7 + IN7 + 0x7 + + + + + + + + + CMP2 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP2_ + 0x40094008 + + 0 + 0x6 + registers + + + ACMP2 + 124 + + + + CMP3 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP3_ + 0x40094010 + + 0 + 0x6 + registers + + + ACMP3 + 125 + + + + CMP4 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP4_ + 0x40094018 + + 0 + 0x6 + registers + + + ACMP4 + 126 + + + + IOMUXC_SNVS_GPR + IOMUXC + IOMUXC_SNVS_GPR + IOMUXC_SNVS_GPR_ + 0x400A4000 + + 0 + 0x10 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + LPSR_MODE_ENABLE + Set to enable LPSR mode. + 0 + 1 + read-write + + + DCDC_STATUS_CAPT_CLR + DCDC captured status clear + 1 + 1 + read-write + + + POR_PULL_TYPE + POR_B pad control + 2 + 2 + read-write + + + DCDC_IN_LOW_VOL + DCDC_IN low voltage detect. + 16 + 1 + read-only + + + DCDC_OVER_CUR + DCDC output over current alert + 17 + 1 + read-only + + + DCDC_OVER_VOL + DCDC output over voltage alert + 18 + 1 + read-only + + + DCDC_STS_DC_OK + DCDC status OK + 19 + 1 + read-only + + + + + + + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS_ + 0x400A8000 + + 0 + 0x24 + registers + + + + SW_MUX_CTL_PAD_WAKEUP + SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register + 0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad WAKEUP + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_ON_REQ + SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_ON_REQ + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_STBY_REQ + SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_STBY_REQ + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0xC + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x10 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x14 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_WAKEUP + SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register + 0x18 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_ON_REQ + SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register + 0x1C + 32 + read-write + 0xB8A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_STBY_REQ + SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register + 0x20 + 32 + read-write + 0xA0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + + + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR_ + 0x400AC000 + + 0 + 0x68 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SAI1_MCLK1_SEL + SAI1 MCLK1 source select + 0 + 3 + read-write + + + SAI1_MCLK1_SEL_0 + ccm.ssi1_clk_root + 0 + + + SAI1_MCLK1_SEL_1 + ccm.ssi2_clk_root + 0x1 + + + SAI1_MCLK1_SEL_2 + ccm.ssi3_clk_root + 0x2 + + + SAI1_MCLK1_SEL_3 + iomux.sai1_ipg_clk_sai_mclk[2] + 0x3 + + + SAI1_MCLK1_SEL_4 + iomux.sai2_ipg_clk_sai_mclk[2] + 0x4 + + + SAI1_MCLK1_SEL_5 + iomux.sai3_ipg_clk_sai_mclk[2] + 0x5 + + + + + SAI1_MCLK2_SEL + SAI1 MCLK2 source select + 3 + 3 + read-write + + + SAI1_MCLK2_SEL_0 + ccm.ssi1_clk_root + 0 + + + SAI1_MCLK2_SEL_1 + ccm.ssi2_clk_root + 0x1 + + + SAI1_MCLK2_SEL_2 + ccm.ssi3_clk_root + 0x2 + + + SAI1_MCLK2_SEL_3 + iomux.sai1_ipg_clk_sai_mclk[2] + 0x3 + + + SAI1_MCLK2_SEL_4 + iomux.sai2_ipg_clk_sai_mclk[2] + 0x4 + + + SAI1_MCLK2_SEL_5 + iomux.sai3_ipg_clk_sai_mclk[2] + 0x5 + + + + + SAI1_MCLK3_SEL + SAI1 MCLK3 source select + 6 + 2 + read-write + + + SAI1_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI1_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI1_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI1_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI2_MCLK3_SEL + SAI2 MCLK3 source select + 8 + 2 + read-write + + + SAI2_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI2_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI2_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI2_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI3_MCLK3_SEL + SAI3 MCLK3 source select + 10 + 2 + read-write + + + SAI3_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI3_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI3_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI3_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + GINT + Global interrupt bit (connected to ARM M7 IRQ#41 and GPC) + 12 + 1 + read-write + + + GINT_0 + Global interrupt request is not asserted. + 0 + + + GINT_1 + Global interrupt request is asserted. + 0x1 + + + + + ENET1_CLK_SEL + ENET1 reference clock mode select. + 13 + 1 + read-write + + + ENET1_CLK_SEL_0 + ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + 0 + + + ENET1_CLK_SEL_1 + Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller. + 0x1 + + + + + USB_EXP_MODE + USB Exposure mode + 15 + 1 + read-write + + + USB_EXP_MODE_0 + Exposure mode is disabled. + 0 + + + USB_EXP_MODE_1 + Exposure mode is enabled. + 0x1 + + + + + ENET1_TX_CLK_DIR + ENET1_TX_CLK data direction control when ENET_REF_CLK1 ALT is selected. + 17 + 1 + read-write + + + ENET1_TX_CLK_DIR_0 + ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. + 0 + + + ENET1_TX_CLK_DIR_1 + ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. + 0x1 + + + + + SAI1_MCLK_DIR + sai1.MCLK signal direction control + 19 + 1 + read-write + + + SAI1_MCLK_DIR_0 + sai1.MCLK is input signal + 0 + + + SAI1_MCLK_DIR_1 + sai1.MCLK is output signal + 0x1 + + + + + SAI2_MCLK_DIR + sai2.MCLK signal direction control + 20 + 1 + read-write + + + SAI2_MCLK_DIR_0 + sai2.MCLK is input signal + 0 + + + SAI2_MCLK_DIR_1 + sai2.MCLK is output signal + 0x1 + + + + + SAI3_MCLK_DIR + sai3.MCLK signal direction control + 21 + 1 + read-write + + + SAI3_MCLK_DIR_0 + sai3.MCLK is input signal + 0 + + + SAI3_MCLK_DIR_1 + sai3.MCLK is output signal + 0x1 + + + + + EXC_MON + Exclusive monitor response select of illegal command + 22 + 1 + read-write + + + EXC_MON_0 + OKAY response + 0 + + + EXC_MON_1 + SLVError response + 0x1 + + + + + ENET_IPG_CLK_S_EN + ENET ipg_clk_s clock gating enable + 23 + 1 + read-write + + + ENET_IPG_CLK_S_EN_0 + ipg_clk_s is gated when there is no IPS access + 0 + + + ENET_IPG_CLK_S_EN_1 + ipg_clk_s is always on + 0x1 + + + + + CM7_FORCE_HCLK_EN + ARM CM7 platform AHB clock enable + 31 + 1 + read-write + + + CM7_FORCE_HCLK_EN_0 + AHB clock is not running (gated) + 0 + + + CM7_FORCE_HCLK_EN_1 + AHB clock is running (enabled) + 0x1 + + + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + L2_MEM_EN_POWERSAVING + enable power saving features on memory + 12 + 1 + read-write + + + L2_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + L2_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + L2_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 14 + 1 + read-write + + + L2_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + L2_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + MQS_CLK_DIV + Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + 16 + 8 + read-write + + + MQS_CLK_DIV_0 + mclk frequency = hmclk frequency + 0 + + + MQS_CLK_DIV_1 + mclk frequency = 1/2 * hmclk frequency + 0x1 + + + MQS_CLK_DIV_2 + mclk frequency = 1/3 * hmclk frequency + 0x2 + + + MQS_CLK_DIV_255 + mclk frequency = 1/256 * hmclk frequency + 0xFF + + + + + MQS_SW_RST + MQS software reset + 24 + 1 + read-write + + + MQS_SW_RST_0 + Exit software reset for MQS + 0 + + + MQS_SW_RST_1 + Enable software reset for MQS + 0x1 + + + + + MQS_EN + MQS enable. + 25 + 1 + read-write + + + MQS_EN_0 + Disable MQS + 0 + + + MQS_EN_1 + Enable MQS + 0x1 + + + + + MQS_OVERSAMPLE + Used to control the PWM oversampling rate compared with mclk. + 26 + 1 + read-write + + + MQS_OVERSAMPLE_0 + 32 + 0 + + + MQS_OVERSAMPLE_1 + 64 + 0x1 + + + + + QTIMER1_TMR_CNTS_FREEZE + QTIMER1 timer counter freeze + 28 + 1 + read-write + + + QTIMER1_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER1_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + QTIMER2_TMR_CNTS_FREEZE + QTIMER2 timer counter freeze + 29 + 1 + read-write + + + QTIMER2_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER2_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + QTIMER3_TMR_CNTS_FREEZE + QTIMER3 timer counter freeze + 30 + 1 + read-write + + + QTIMER3_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER3_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + QTIMER4_TMR_CNTS_FREEZE + QTIMER4 timer counter freeze + 31 + 1 + read-write + + + QTIMER4_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER4_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xFFF0 + 0xFFFFFFFF + + + OCRAM_CTL + OCRAM_CTL[3] - write address pipeline control bit + 0 + 4 + read-write + + + DCP_KEY_SEL + Select 128-bit dcp key from 256-bit key from snvs/ocotp + 4 + 1 + read-write + + + DCP_KEY_SEL_0 + Select [127:0] from snvs/ocotp key as dcp key + 0 + + + DCP_KEY_SEL_1 + Select [255:128] from snvs/ocotp key as dcp key + 0x1 + + + + + OCRAM_STATUS + This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL bits respectively + 16 + 4 + read-only + + + OCRAM_STATUS_0 + read data pipeline configuration valid + 0 + + + OCRAM_STATUS_1 + read data pipeline control bit changed + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDMA_STOP_REQ + EDMA stop request. + 0 + 1 + read-write + + + EDMA_STOP_REQ_0 + stop request off + 0 + + + EDMA_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN1_STOP_REQ + CAN1 stop request. + 1 + 1 + read-write + + + CAN1_STOP_REQ_0 + stop request off + 0 + + + CAN1_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN2_STOP_REQ + CAN2 stop request. + 2 + 1 + read-write + + + CAN2_STOP_REQ_0 + stop request off + 0 + + + CAN2_STOP_REQ_1 + stop request on + 0x1 + + + + + TRNG_STOP_REQ + TRNG stop request. + 3 + 1 + read-write + + + TRNG_STOP_REQ_0 + stop request off + 0 + + + TRNG_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET_STOP_REQ + ENET stop request. + 4 + 1 + read-write + + + ENET_STOP_REQ_0 + stop request off + 0 + + + ENET_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI1_STOP_REQ + SAI1 stop request. + 5 + 1 + read-write + + + SAI1_STOP_REQ_0 + stop request off + 0 + + + SAI1_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI2_STOP_REQ + SAI2 stop request. + 6 + 1 + read-write + + + SAI2_STOP_REQ_0 + stop request off + 0 + + + SAI2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI3_STOP_REQ + SAI3 stop request. + 7 + 1 + read-write + + + SAI3_STOP_REQ_0 + stop request off + 0 + + + SAI3_STOP_REQ_1 + stop request on + 0x1 + + + + + SEMC_STOP_REQ + SEMC stop request. + 9 + 1 + read-write + + + SEMC_STOP_REQ_0 + stop request off + 0 + + + SEMC_STOP_REQ_1 + stop request on + 0x1 + + + + + PIT_STOP_REQ + PIT stop request. + 10 + 1 + read-write + + + PIT_STOP_REQ_0 + stop request off + 0 + + + PIT_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXSPI_STOP_REQ + FlexSPI stop request. + 11 + 1 + read-write + + + FLEXSPI_STOP_REQ_0 + stop request off + 0 + + + FLEXSPI_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO1_STOP_REQ + FlexIO1 stop request. + 12 + 1 + read-write + + + FLEXIO1_STOP_REQ_0 + stop request off + 0 + + + FLEXIO1_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO2_STOP_REQ + FlexIO2 stop request. + 13 + 1 + read-write + + + FLEXIO2_STOP_REQ_0 + stop request off + 0 + + + FLEXIO2_STOP_REQ_1 + stop request on + 0x1 + + + + + EDMA_STOP_ACK + EDMA stop acknowledge. This is a status (read-only) bit + 16 + 1 + read-only + + + EDMA_STOP_ACK_0 + EDMA stop acknowledge is not asserted + 0 + + + EDMA_STOP_ACK_1 + EDMA stop acknowledge is asserted (EDMA is in STOP mode). + 0x1 + + + + + CAN1_STOP_ACK + CAN1 stop acknowledge. + 17 + 1 + read-only + + + CAN1_STOP_ACK_0 + CAN1 stop acknowledge is not asserted + 0 + + + CAN1_STOP_ACK_1 + CAN1 stop acknowledge is asserted + 0x1 + + + + + CAN2_STOP_ACK + CAN2 stop acknowledge. + 18 + 1 + read-only + + + CAN2_STOP_ACK_0 + CAN2 stop acknowledge is not asserted + 0 + + + CAN2_STOP_ACK_1 + CAN2 stop acknowledge is asserted + 0x1 + + + + + TRNG_STOP_ACK + TRNG stop acknowledge + 19 + 1 + read-only + + + TRNG_STOP_ACK_0 + TRNG stop acknowledge is not asserted + 0 + + + TRNG_STOP_ACK_1 + TRNG stop acknowledge is asserted + 0x1 + + + + + ENET_STOP_ACK + ENET stop acknowledge. + 20 + 1 + read-only + + + ENET_STOP_ACK_0 + ENET stop acknowledge is not asserted + 0 + + + ENET_STOP_ACK_1 + ENET stop acknowledge is asserted + 0x1 + + + + + SAI1_STOP_ACK + SAI1 stop acknowledge + 21 + 1 + read-only + + + SAI1_STOP_ACK_0 + SAI1 stop acknowledge is not asserted + 0 + + + SAI1_STOP_ACK_1 + SAI1 stop acknowledge is asserted + 0x1 + + + + + SAI2_STOP_ACK + SAI2 stop acknowledge + 22 + 1 + read-only + + + SAI2_STOP_ACK_0 + SAI2 stop acknowledge is not asserted + 0 + + + SAI2_STOP_ACK_1 + SAI2 stop acknowledge is asserted + 0x1 + + + + + SAI3_STOP_ACK + SAI3 stop acknowledge + 23 + 1 + read-only + + + SAI3_STOP_ACK_0 + SAI3 stop acknowledge is not asserted + 0 + + + SAI3_STOP_ACK_1 + SAI3 stop acknowledge is asserted + 0x1 + + + + + SEMC_STOP_ACK + SEMC stop acknowledge + 25 + 1 + read-only + + + SEMC_STOP_ACK_0 + SEMC stop acknowledge is not asserted + 0 + + + SEMC_STOP_ACK_1 + SEMC stop acknowledge is asserted + 0x1 + + + + + PIT_STOP_ACK + PIT stop acknowledge + 26 + 1 + read-only + + + PIT_STOP_ACK_0 + PIT stop acknowledge is not asserted + 0 + + + PIT_STOP_ACK_1 + PIT stop acknowledge is asserted + 0x1 + + + + + FLEXSPI_STOP_ACK + FLEXSPI stop acknowledge + 27 + 1 + read-only + + + FLEXSPI_STOP_ACK_0 + FLEXSPI stop acknowledge is not asserted + 0 + + + FLEXSPI_STOP_ACK_1 + FLEXSPI stop acknowledge is asserted + 0x1 + + + + + FLEXIO1_STOP_ACK + FLEXIO1 stop acknowledge + 28 + 1 + read-only + + + FLEXIO1_STOP_ACK_0 + FLEXIO1 stop acknowledge is not asserted + 0 + + + FLEXIO1_STOP_ACK_1 + FLEXIO1 stop acknowledge is asserted + 0x1 + + + + + FLEXIO2_STOP_ACK + FLEXIO2 stop acknowledge + 29 + 1 + read-only + + + FLEXIO2_STOP_ACK_0 + FLEXIO2 stop acknowledge is not asserted + 0 + + + FLEXIO2_STOP_ACK_1 + FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDOG1_MASK + WDOG1 Timeout Mask + 6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + GPT2_CAPIN1_SEL + GPT2 input capture channel 1 source select + 23 + 1 + read-write + + + GPT2_CAPIN1_SEL_0 + source from pad + 0 + + + GPT2_CAPIN1_SEL_1 + source from enet1.ipp_do_mac0_timer[3] + 0x1 + + + + + ENET_EVENT3IN_SEL + ENET input timer event3 source select + 25 + 1 + read-write + + + ENET_EVENT3IN_SEL_0 + event3 source input from pad + 0 + + + ENET_EVENT3IN_SEL_1 + event3 source input from gpt2.ipp_do_cmpout1 + 0x1 + + + + + VREF_1M_CLK_GPT1 + GPT1 1 MHz clock source select + 28 + 1 + read-write + + + VREF_1M_CLK_GPT1_0 + GPT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT1_1 + GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + VREF_1M_CLK_GPT2 + GPT2 1 MHz clock source select + 29 + 1 + read-write + + + VREF_1M_CLK_GPT2_0 + GPT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT2_1 + GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + + + GPR6 + GPR6 General Purpose Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + QTIMER1_TRM0_INPUT_SEL + QTIMER1 TMR0 input select + 0 + 1 + read-write + + + QTIMER1_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM1_INPUT_SEL + QTIMER1 TMR1 input select + 1 + 1 + read-write + + + QTIMER1_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM2_INPUT_SEL + QTIMER1 TMR2 input select + 2 + 1 + read-write + + + QTIMER1_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM3_INPUT_SEL + QTIMER1 TMR3 input select + 3 + 1 + read-write + + + QTIMER1_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM0_INPUT_SEL + QTIMER2 TMR0 input select + 4 + 1 + read-write + + + QTIMER2_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM1_INPUT_SEL + QTIMER2 TMR1 input select + 5 + 1 + read-write + + + QTIMER2_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM2_INPUT_SEL + QTIMER2 TMR2 input select + 6 + 1 + read-write + + + QTIMER2_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM3_INPUT_SEL + QTIMER2 TMR3 input select + 7 + 1 + read-write + + + QTIMER2_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM0_INPUT_SEL + QTIMER3 TMR0 input select + 8 + 1 + read-write + + + QTIMER3_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM1_INPUT_SEL + QTIMER3 TMR1 input select + 9 + 1 + read-write + + + QTIMER3_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM2_INPUT_SEL + QTIMER3 TMR2 input select + 10 + 1 + read-write + + + QTIMER3_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM3_INPUT_SEL + QTIMER3 TMR3 input select + 11 + 1 + read-write + + + QTIMER3_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM0_INPUT_SEL + QTIMER4 TMR0 input select + 12 + 1 + read-write + + + QTIMER4_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM1_INPUT_SEL + QTIMER4 TMR1 input select + 13 + 1 + read-write + + + QTIMER4_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM2_INPUT_SEL + QTIMER4 TMR2 input select + 14 + 1 + read-write + + + QTIMER4_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM3_INPUT_SEL + QTIMER4 TMR3 input select + 15 + 1 + read-write + + + QTIMER4_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_4 + IOMUXC XBAR_INOUT4 function direction select + 16 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_4_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_4_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_5 + IOMUXC XBAR_INOUT5 function direction select + 17 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_5_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_5_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_6 + IOMUXC XBAR_INOUT6 function direction select + 18 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_6_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_6_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_7 + IOMUXC XBAR_INOUT7 function direction select + 19 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_7_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_7_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_8 + IOMUXC XBAR_INOUT8 function direction select + 20 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_8_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_8_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_9 + IOMUXC XBAR_INOUT9 function direction select + 21 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_9_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_9_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_10 + IOMUXC XBAR_INOUT10 function direction select + 22 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_10_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_10_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_11 + IOMUXC XBAR_INOUT11 function direction select + 23 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_11_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_11_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_12 + IOMUXC XBAR_INOUT12 function direction select + 24 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_12_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_12_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_13 + IOMUXC XBAR_INOUT13 function direction select + 25 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_13_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_13_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_14 + IOMUXC XBAR_INOUT14 function direction select + 26 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_14_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_14_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_15 + IOMUXC XBAR_INOUT15 function direction select + 27 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_15_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_15_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_16 + IOMUXC XBAR_INOUT16 function direction select + 28 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_16_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_16_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_17 + IOMUXC XBAR_INOUT17 function direction select + 29 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_17_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_17_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_18 + IOMUXC XBAR_INOUT18 function direction select + 30 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_18_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_18_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_19 + IOMUXC XBAR_INOUT19 function direction select + 31 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_19_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_19_1 + XBAR_INOUT as output + 0x1 + + + + + + + GPR7 + GPR7 General Purpose Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_STOP_REQ + LPI2C1 stop request + 0 + 1 + read-write + + + LPI2C1_STOP_REQ_0 + stop request off + 0 + + + LPI2C1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C2_STOP_REQ + LPI2C2 stop request + 1 + 1 + read-write + + + LPI2C2_STOP_REQ_0 + stop request off + 0 + + + LPI2C2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C3_STOP_REQ + LPI2C3 stop request + 2 + 1 + read-write + + + LPI2C3_STOP_REQ_0 + stop request off + 0 + + + LPI2C3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C4_STOP_REQ + LPI2C4 stop request + 3 + 1 + read-write + + + LPI2C4_STOP_REQ_0 + stop request off + 0 + + + LPI2C4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI1_STOP_REQ + LPSPI1 stop request + 4 + 1 + read-write + + + LPSPI1_STOP_REQ_0 + stop request off + 0 + + + LPSPI1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI2_STOP_REQ + LPSPI2 stop request + 5 + 1 + read-write + + + LPSPI2_STOP_REQ_0 + stop request off + 0 + + + LPSPI2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI3_STOP_REQ + LPSPI3 stop request + 6 + 1 + read-write + + + LPSPI3_STOP_REQ_0 + stop request off + 0 + + + LPSPI3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI4_STOP_REQ + LPSPI4 stop request + 7 + 1 + read-write + + + LPSPI4_STOP_REQ_0 + stop request off + 0 + + + LPSPI4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART1_STOP_REQ + LPUART1 stop request + 8 + 1 + read-write + + + LPUART1_STOP_REQ_0 + stop request off + 0 + + + LPUART1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART2_STOP_REQ + LPUART1 stop request + 9 + 1 + read-write + + + LPUART2_STOP_REQ_0 + stop request off + 0 + + + LPUART2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART3_STOP_REQ + LPUART3 stop request + 10 + 1 + read-write + + + LPUART3_STOP_REQ_0 + stop request off + 0 + + + LPUART3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART4_STOP_REQ + LPUART4 stop request + 11 + 1 + read-write + + + LPUART4_STOP_REQ_0 + stop request off + 0 + + + LPUART4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART5_STOP_REQ + LPUART5 stop request + 12 + 1 + read-write + + + LPUART5_STOP_REQ_0 + stop request off + 0 + + + LPUART5_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART6_STOP_REQ + LPUART6 stop request + 13 + 1 + read-write + + + LPUART6_STOP_REQ_0 + stop request off + 0 + + + LPUART6_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART7_STOP_REQ + LPUART7 stop request + 14 + 1 + read-write + + + LPUART7_STOP_REQ_0 + stop request off + 0 + + + LPUART7_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART8_STOP_REQ + LPUART8 stop request + 15 + 1 + read-write + + + LPUART8_STOP_REQ_0 + stop request off + 0 + + + LPUART8_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C1_STOP_ACK + LPI2C1 stop acknowledge + 16 + 1 + read-only + + + LPI2C1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C1_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + LPI2C2_STOP_ACK + LPI2C2 stop acknowledge + 17 + 1 + read-only + + + LPI2C2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPI2C3_STOP_ACK + LPI2C3 stop acknowledge + 18 + 1 + read-only + + + LPI2C3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPI2C4_STOP_ACK + LPI2C4 stop acknowledge + 19 + 1 + read-only + + + LPI2C4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI1_STOP_ACK + LPSPI1 stop acknowledge + 20 + 1 + read-only + + + LPSPI1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI2_STOP_ACK + LPSPI2 stop acknowledge + 21 + 1 + read-only + + + LPSPI2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI3_STOP_ACK + LPSPI3 stop acknowledge + 22 + 1 + read-only + + + LPSPI3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI4_STOP_ACK + LPSPI4 stop acknowledge + 23 + 1 + read-only + + + LPSPI4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART1_STOP_ACK + LPUART1 stop acknowledge + 24 + 1 + read-only + + + LPUART1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART2_STOP_ACK + LPUART1 stop acknowledge + 25 + 1 + read-only + + + LPUART2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART3_STOP_ACK + LPUART3 stop acknowledge + 26 + 1 + read-only + + + LPUART3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART4_STOP_ACK + LPUART4 stop acknowledge + 27 + 1 + read-only + + + LPUART4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART5_STOP_ACK + LPUART5 stop acknowledge + 28 + 1 + read-only + + + LPUART5_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART5_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART6_STOP_ACK + LPUART6 stop acknowledge + 29 + 1 + read-only + + + LPUART6_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART6_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART7_STOP_ACK + LPUART7 stop acknowledge + 30 + 1 + read-only + + + LPUART7_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART7_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART8_STOP_ACK + LPUART8 stop acknowledge + 31 + 1 + read-only + + + LPUART8_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART8_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + + + GPR8 + GPR8 General Purpose Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_IPG_STOP_MODE + LPI2C1 stop mode selection, cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + LPI2C1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C1_IPG_DOZE + LPI2C1 ipg_doze mode + 1 + 1 + read-write + + + LPI2C1_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C2_IPG_STOP_MODE + LPI2C2 stop mode selection, cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + LPI2C2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C2_IPG_DOZE + LPI2C2 ipg_doze mode + 3 + 1 + read-write + + + LPI2C2_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C3_IPG_STOP_MODE + LPI2C3 stop mode selection, cannot change when ipg_stop is asserted. + 4 + 1 + read-write + + + LPI2C3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C3_IPG_DOZE + LPI2C3 ipg_doze mode + 5 + 1 + read-write + + + LPI2C3_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C4_IPG_STOP_MODE + LPI2C4 stop mode selection, cannot change when ipg_stop is asserted. + 6 + 1 + read-write + + + LPI2C4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C4_IPG_DOZE + LPI2C4 ipg_doze mode + 7 + 1 + read-write + + + LPI2C4_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI1_IPG_STOP_MODE + LPSPI1 stop mode selection, cannot change when ipg_stop is asserted. + 8 + 1 + read-write + + + LPSPI1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI1_IPG_DOZE + LPSPI1 ipg_doze mode + 9 + 1 + read-write + + + LPSPI1_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI2_IPG_STOP_MODE + LPSPI2 stop mode selection, cannot change when ipg_stop is asserted. + 10 + 1 + read-write + + + LPSPI2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI2_IPG_DOZE + LPSPI2 ipg_doze mode + 11 + 1 + read-write + + + LPSPI2_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI3_IPG_STOP_MODE + LPSPI3 stop mode selection, cannot change when ipg_stop is asserted. + 12 + 1 + read-write + + + LPSPI3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI3_IPG_DOZE + LPSPI3 ipg_doze mode + 13 + 1 + read-write + + + LPSPI3_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI4_IPG_STOP_MODE + LPSPI4 stop mode selection, cannot change when ipg_stop is asserted. + 14 + 1 + read-write + + + LPSPI4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI4_IPG_DOZE + LPSPI4 ipg_doze mode + 15 + 1 + read-write + + + LPSPI4_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART1_IPG_STOP_MODE + LPUART1 stop mode selection, cannot change when ipg_stop is asserted. + 16 + 1 + read-write + + + LPUART1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART1_IPG_DOZE + LPUART1 ipg_doze mode + 17 + 1 + read-write + + + LPUART1_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART2_IPG_STOP_MODE + LPUART2 stop mode selection, cannot change when ipg_stop is asserted. + 18 + 1 + read-write + + + LPUART2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART2_IPG_DOZE + LPUART2 ipg_doze mode + 19 + 1 + read-write + + + LPUART2_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART3_IPG_STOP_MODE + LPUART3 stop mode selection, cannot change when ipg_stop is asserted. + 20 + 1 + read-write + + + LPUART3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART3_IPG_DOZE + LPUART3 ipg_doze mode + 21 + 1 + read-write + + + LPUART3_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART4_IPG_STOP_MODE + LPUART4 stop mode selection, cannot change when ipg_stop is asserted. + 22 + 1 + read-write + + + LPUART4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART4_IPG_DOZE + LPUART4 ipg_doze mode + 23 + 1 + read-write + + + LPUART4_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART5_IPG_STOP_MODE + LPUART5 stop mode selection, cannot change when ipg_stop is asserted. + 24 + 1 + read-write + + + LPUART5_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART5_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART5_IPG_DOZE + LPUART5 ipg_doze mode + 25 + 1 + read-write + + + LPUART5_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART5_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART6_IPG_STOP_MODE + LPUART6 stop mode selection, cannot change when ipg_stop is asserted. + 26 + 1 + read-write + + + LPUART6_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART6_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART6_IPG_DOZE + LPUART6 ipg_doze mode + 27 + 1 + read-write + + + LPUART6_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART6_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART7_IPG_STOP_MODE + LPUART7 stop mode selection, cannot change when ipg_stop is asserted. + 28 + 1 + read-write + + + LPUART7_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART7_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART7_IPG_DOZE + LPUART7 ipg_doze mode + 29 + 1 + read-write + + + LPUART7_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART7_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART8_IPG_STOP_MODE + LPUART8 stop mode selection, cannot change when ipg_stop is asserted. + 30 + 1 + read-write + + + LPUART8_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART8_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART8_IPG_DOZE + LPUART8 ipg_doze mode + 31 + 1 + read-write + + + LPUART8_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART8_IPG_DOZE_1 + in doze mode + 0x1 + + + + + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + NIDEN + ARM non-secure (non-invasive) debug enable + 0 + 1 + read-write + + + NIDEN_0 + Debug turned off. + 0 + + + NIDEN_1 + Debug enabled (default). + 0x1 + + + + + DBG_EN + ARM invasive debug enable + 1 + 1 + read-write + + + DBG_EN_0 + Debug turned off. + 0 + + + DBG_EN_1 + Debug enabled (default). + 0x1 + + + + + SEC_ERR_RESP + Security error response enable for all security gaskets (on both AHB and AXI buses) + 2 + 1 + read-write + + + SEC_ERR_RESP_0 + OKEY response + 0 + + + SEC_ERR_RESP_1 + SLVError (default) + 0x1 + + + + + DCPKEY_OCOTP_OR_KEYMUX + DCP Key selection bit. + 4 + 1 + read-write + + + DCPKEY_OCOTP_OR_KEYMUX_0 + Select key from Key MUX (SNVS/OTPMK). + 0 + + + DCPKEY_OCOTP_OR_KEYMUX_1 + Select key from OCOTP (SW_GP2). + 0x1 + + + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable. + 8 + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 9 + 7 + read-write + + + LOCK_NIDEN + Lock NIDEN field for changes + 16 + 1 + read-write + + + LOCK_NIDEN_0 + Field is not locked + 0 + + + LOCK_NIDEN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DBG_EN + Lock DBG_EN field for changes + 17 + 1 + read-write + + + LOCK_DBG_EN_0 + Field is not locked + 0 + + + LOCK_DBG_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_SEC_ERR_RESP + Lock SEC_ERR_RESP field for changes + 18 + 1 + read-write + + + LOCK_SEC_ERR_RESP_0 + Field is not locked + 0 + + + LOCK_SEC_ERR_RESP_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX + Lock DCP Key OCOTP/Key MUX selection bit + 20 + 1 + read-write + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_0 + Field is not locked + 0 + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_EN + Lock OCRAM_TZ_EN field for changes + 24 + 1 + read-write + + + LOCK_OCRAM_TZ_EN_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_ADDR + Lock OCRAM_TZ_ADDR field for changes + 25 + 7 + read-write + + + LOCK_OCRAM_TZ_ADDR_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_ADDR_1 + Field is locked (read access only) + 0x1 + + + + + + + GPR11 + GPR11 General Purpose Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + M7_APC_AC_R0_CTRL + Access control of memory region-0 + 0 + 2 + read-write + + + M7_APC_AC_R0_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R0_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R0_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R0_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + M7_APC_AC_R1_CTRL + Access control of memory region-1 + 2 + 2 + read-write + + + M7_APC_AC_R1_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R1_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R1_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R1_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + M7_APC_AC_R2_CTRL + Access control of memory region-2 + 4 + 2 + read-write + + + M7_APC_AC_R2_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R2_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R2_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R2_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + M7_APC_AC_R3_CTRL + Access control of memory region-3 + 6 + 2 + read-write + + + M7_APC_AC_R3_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R3_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R3_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R3_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + BEE_DE_RX_EN + BEE data decryption of memory region-n (n = 3 to 0) + 8 + 4 + read-write + + + LOCK_M7_APC_AC_R0_CTRL + Lock M7_APC_AC_R0_CTRL field for changes + 16 + 2 + read-write + + + LOCK_M7_APC_AC_R1_CTRL + Lock M7_APC_AC_R1_CTRL field for changes + 18 + 2 + read-write + + + LOCK_M7_APC_AC_R2_CTRL + Lock M7_APC_AC_R2_CTRL field for changes + 20 + 2 + read-write + + + LOCK_M7_APC_AC_R3_CTRL + Lock M7_APC_AC_R3_CTRL field for changes + 22 + 2 + read-write + + + LOCK_BEE_DE_RX_EN + Lock BEE_DE_RX_EN[n] (n = 3 to 0) field for changes + 24 + 4 + read-write + + + + + GPR12 + GPR12 General Purpose Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXIO1_IPG_STOP_MODE + FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + FLEXIO1_IPG_STOP_MODE_0 + FlexIO1 is functional in Stop mode. + 0 + + + FLEXIO1_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + 0x1 + + + + + FLEXIO1_IPG_DOZE + FLEXIO1 ipg_doze mode + 1 + 1 + read-write + + + FLEXIO1_IPG_DOZE_0 + FLEXIO1 is not in doze mode + 0 + + + FLEXIO1_IPG_DOZE_1 + FLEXIO1 is in doze mode + 0x1 + + + + + FLEXIO2_IPG_STOP_MODE + FlexIO2 stop mode selection. Cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + FLEXIO2_IPG_STOP_MODE_0 + FlexIO2 is functional in Stop mode. + 0 + + + FLEXIO2_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + 0x1 + + + + + FLEXIO2_IPG_DOZE + FLEXIO2 ipg_doze mode + 3 + 1 + read-write + + + FLEXIO2_IPG_DOZE_0 + FLEXIO2 is not in doze mode + 0 + + + FLEXIO2_IPG_DOZE_1 + FLEXIO2 is in doze mode + 0x1 + + + + + ACMP_IPG_STOP_MODE + ACMP stop mode selection. Cannot change when ipg_stop is asserted. + 4 + 1 + read-write + + + ACMP_IPG_STOP_MODE_0 + ACMP is functional in Stop mode. + 0 + + + ACMP_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + 0x1 + + + + + + + GPR13 + GPR13 General Purpose Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARCACHE_USDHC + uSDHC block cacheable attribute value of AXI read transactions + 0 + 1 + read-write + + + ARCACHE_USDHC_0 + Cacheable attribute is off for read transactions. + 0 + + + ARCACHE_USDHC_1 + Cacheable attribute is on for read transactions. + 0x1 + + + + + AWCACHE_USDHC + uSDHC block cacheable attribute value of AXI write transactions + 1 + 1 + read-write + + + AWCACHE_USDHC_0 + Cacheable attribute is off for write transactions. + 0 + + + AWCACHE_USDHC_1 + Cacheable attribute is on for write transactions. + 0x1 + + + + + CACHE_ENET + ENET block cacheable attribute value of AXI transactions + 7 + 1 + read-write + + + CACHE_ENET_0 + Cacheable attribute is off for read/write transactions. + 0 + + + CACHE_ENET_1 + Cacheable attribute is on for read/write transactions. + 0x1 + + + + + CACHE_USB + USB block cacheable attribute value of AXI transactions + 13 + 1 + read-write + + + CACHE_USB_0 + Cacheable attribute is off for read/write transactions. + 0 + + + CACHE_USB_1 + Cacheable attribute is on for read/write transactions. + 0x1 + + + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACMP1_CMP_IGEN_TRIM_DN + reduces ACMP1 internal bias current by 30% + 0 + 1 + read-write + + + ACMP1_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP1_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP2_CMP_IGEN_TRIM_DN + reduces ACMP2 internal bias current by 30% + 1 + 1 + read-write + + + ACMP2_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP2_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP3_CMP_IGEN_TRIM_DN + reduces ACMP3 internal bias current by 30% + 2 + 1 + read-write + + + ACMP3_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP3_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP4_CMP_IGEN_TRIM_DN + reduces ACMP4 internal bias current by 30% + 3 + 1 + read-write + + + ACMP4_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP4_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP1_CMP_IGEN_TRIM_UP + increases ACMP1 internal bias current by 30% + 4 + 1 + read-write + + + ACMP1_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP1_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP2_CMP_IGEN_TRIM_UP + increases ACMP2 internal bias current by 30% + 5 + 1 + read-write + + + ACMP2_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP2_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP3_CMP_IGEN_TRIM_UP + increases ACMP3 internal bias current by 30% + 6 + 1 + read-write + + + ACMP3_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP3_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP4_CMP_IGEN_TRIM_UP + increases ACMP4 internal bias current by 30% + 7 + 1 + read-write + + + ACMP4_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP4_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP1_SAMPLE_SYNC_EN + ACMP1 sample_lv source select + 8 + 1 + read-write + + + ACMP1_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP1_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP2_SAMPLE_SYNC_EN + ACMP2 sample_lv source select + 9 + 1 + read-write + + + ACMP2_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP2_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP3_SAMPLE_SYNC_EN + ACMP3 sample_lv source select + 10 + 1 + read-write + + + ACMP3_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP3_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP4_SAMPLE_SYNC_EN + ACMP4 sample_lv source select + 11 + 1 + read-write + + + ACMP4_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP4_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + CM7_CFGITCMSZ + ITCM total size configuration + 16 + 4 + read-write + + + CM7_CFGITCMSZ_0 + 0 KB (No ITCM) + 0 + + + CM7_CFGITCMSZ_3 + 4 KB + 0x3 + + + CM7_CFGITCMSZ_4 + 8 KB + 0x4 + + + CM7_CFGITCMSZ_5 + 16 KB + 0x5 + + + CM7_CFGITCMSZ_6 + 32 KB + 0x6 + + + CM7_CFGITCMSZ_7 + 64 KB + 0x7 + + + CM7_CFGITCMSZ_8 + 128 KB + 0x8 + + + CM7_CFGITCMSZ_9 + 256 KB + 0x9 + + + CM7_CFGITCMSZ_10 + 512 KB + 0xA + + + + + CM7_CFGDTCMSZ + DTCM total size configuration + 20 + 4 + read-write + + + CM7_CFGDTCMSZ_0 + 0 KB (No DTCM) + 0 + + + CM7_CFGDTCMSZ_3 + 4 KB + 0x3 + + + CM7_CFGDTCMSZ_4 + 8 KB + 0x4 + + + CM7_CFGDTCMSZ_5 + 16 KB + 0x5 + + + CM7_CFGDTCMSZ_6 + 32 KB + 0x6 + + + CM7_CFGDTCMSZ_7 + 64 KB + 0x7 + + + CM7_CFGDTCMSZ_8 + 128 KB + 0x8 + + + CM7_CFGDTCMSZ_9 + 256 KB + 0x9 + + + CM7_CFGDTCMSZ_10 + 512 KB + 0xA + + + + + + + GPR15 + GPR15 General Purpose Register + 0x3C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + GPR16 + GPR16 General Purpose Register + 0x40 + 32 + read-write + 0x200003 + 0xFFFFFFFF + + + INIT_ITCM_EN + ITCM enable initialization out of reset + 0 + 1 + read-write + + + INIT_ITCM_EN_0 + ITCM is disabled + 0 + + + INIT_ITCM_EN_1 + ITCM is enabled + 0x1 + + + + + INIT_DTCM_EN + DTCM enable initialization out of reset + 1 + 1 + read-write + + + INIT_DTCM_EN_0 + DTCM is disabled + 0 + + + INIT_DTCM_EN_1 + DTCM is enabled + 0x1 + + + + + FLEXRAM_BANK_CFG_SEL + FlexRAM bank config source select + 2 + 1 + read-write + + + FLEXRAM_BANK_CFG_SEL_0 + use fuse value to config + 0 + + + FLEXRAM_BANK_CFG_SEL_1 + use FLEXRAM_BANK_CFG to config + 0x1 + + + + + CM7_INIT_VTOR + Vector table offset register out of reset + 7 + 25 + read-write + + + + + GPR17 + GPR17 General Purpose Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXRAM_BANK_CFG + FlexRAM bank config value + 0 + 32 + read-write + + + + + GPR18 + GPR18 General Purpose Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_BOT + lock M7_APC_AC_R0_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R0_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_BOT + APC end address of memory region-0 + 3 + 29 + read-write + + + + + GPR19 + GPR19 General Purpose Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_TOP + lock M7_APC_AC_R0_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R0_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_TOP + APC start address of memory region-0 + 3 + 29 + read-write + + + + + GPR20 + GPR20 General Purpose Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_BOT + lock M7_APC_AC_R1_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_BOT + APC end address of memory region-1 + 3 + 29 + read-write + + + + + GPR21 + GPR21 General Purpose Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_TOP + lock M7_APC_AC_R1_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_TOP + APC start address of memory region-1 + 3 + 29 + read-write + + + + + GPR22 + GPR22 General Purpose Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_BOT + lock M7_APC_AC_R2_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R2_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_BOT + APC end address of memory region-2 + 3 + 29 + read-write + + + + + GPR23 + GPR23 General Purpose Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_TOP + lock M7_APC_AC_R2_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_TOP + APC start address of memory region-2 + 3 + 29 + read-write + + + + + GPR24 + GPR24 General Purpose Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_BOT + lock M7_APC_AC_R3_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R3_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_BOT + APC end address of memory region-3 + 3 + 29 + read-write + + + + + GPR25 + GPR25 General Purpose Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_TOP + lock M7_APC_AC_R3_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R3_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_TOP + APC start address of memory region-3 + 3 + 29 + read-write + + + + + + + FLEXRAM + FLEXRAM + FLEXRAM + 0x400B0000 + + 0 + 0x1000 + registers + + + FLEXRAM + 38 + + + + TCM_CTRL + TCM CRTL Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCM_WWAIT_EN + TCM Write Wait Mode Enable + 0 + 1 + read-write + + + TCM_WWAIT_EN_0 + TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_WWAIT_EN_1 + TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + TCM_RWAIT_EN + TCM Read Wait Mode Enable + 1 + 1 + read-write + + + TCM_RWAIT_EN_0 + TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_RWAIT_EN_1 + TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + FORCE_CLK_ON + Force RAM Clock Always On + 2 + 1 + read-write + + + Reserved + Reserved + 3 + 29 + read-only + + + + + OCRAM_MAGIC_ADDR + OCRAM Magic Address Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + OCRAM_WR_RD_SEL + OCRAM Write Read Select + 0 + 1 + read-write + + + OCRAM_WR_RD_SEL_0 + When OCRAM read access hits magic address, it will generate interrupt. + 0 + + + OCRAM_WR_RD_SEL_1 + When OCRAM write access hits magic address, it will generate interrupt. + 0x1 + + + + + OCRAM_MAGIC_ADDR + OCRAM Magic Address + 1 + 16 + read-write + + + Reserved + Reserved + 17 + 15 + read-only + + + + + DTCM_MAGIC_ADDR + DTCM Magic Address Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTCM_WR_RD_SEL + DTCM Write Read Select + 0 + 1 + read-write + + + DTCM_WR_RD_SEL_0 + When DTCM read access hits magic address, it will generate interrupt. + 0 + + + DTCM_WR_RD_SEL_1 + When DTCM write access hits magic address, it will generate interrupt. + 0x1 + + + + + DTCM_MAGIC_ADDR + DTCM Magic Address + 1 + 16 + read-write + + + Reserved + Reserved + 17 + 15 + read-only + + + + + ITCM_MAGIC_ADDR + ITCM Magic Address Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_WR_RD_SEL + ITCM Write Read Select + 0 + 1 + read-write + + + ITCM_WR_RD_SEL_0 + When ITCM read access hits magic address, it will generate interrupt. + 0 + + + ITCM_WR_RD_SEL_1 + When ITCM write access hits magic address, it will generate interrupt. + 0x1 + + + + + ITCM_MAGIC_ADDR + ITCM Magic Address + 1 + 16 + read-write + + + Reserved + Reserved + 17 + 15 + read-only + + + + + INT_STATUS + Interrupt Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_MAM_STATUS + ITCM Magic Address Match Status + 0 + 1 + read-write + oneToClear + + + ITCM_MAM_STATUS_0 + ITCM did not access magic address. + 0 + + + ITCM_MAM_STATUS_1 + ITCM accessed magic address. + 0x1 + + + + + DTCM_MAM_STATUS + DTCM Magic Address Match Status + 1 + 1 + read-write + oneToClear + + + DTCM_MAM_STATUS_0 + DTCM did not access magic address. + 0 + + + DTCM_MAM_STATUS_1 + DTCM accessed magic address. + 0x1 + + + + + OCRAM_MAM_STATUS + OCRAM Magic Address Match Status + 2 + 1 + read-write + oneToClear + + + OCRAM_MAM_STATUS_0 + OCRAM did not access magic address. + 0 + + + OCRAM_MAM_STATUS_1 + OCRAM accessed magic address. + 0x1 + + + + + ITCM_ERR_STATUS + ITCM Access Error Status + 3 + 1 + read-write + oneToClear + + + ITCM_ERR_STATUS_0 + ITCM access error does not happen + 0 + + + ITCM_ERR_STATUS_1 + ITCM access error happens. + 0x1 + + + + + DTCM_ERR_STATUS + DTCM Access Error Status + 4 + 1 + read-write + oneToClear + + + DTCM_ERR_STATUS_0 + DTCM access error does not happen + 0 + + + DTCM_ERR_STATUS_1 + DTCM access error happens. + 0x1 + + + + + OCRAM_ERR_STATUS + OCRAM Access Error Status + 5 + 1 + read-write + oneToClear + + + OCRAM_ERR_STATUS_0 + OCRAM access error does not happen + 0 + + + OCRAM_ERR_STATUS_1 + OCRAM access error happens. + 0x1 + + + + + Reserved + Reserved + 6 + 26 + read-only + + + + + INT_STAT_EN + Interrupt Status Enable Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_MAM_STAT_EN + ITCM Magic Address Match Status Enable + 0 + 1 + read-write + + + ITCM_MAM_STAT_EN_0 + Masked + 0 + + + ITCM_MAM_STAT_EN_1 + Enabled + 0x1 + + + + + DTCM_MAM_STAT_EN + DTCM Magic Address Match Status Enable + 1 + 1 + read-write + + + DTCM_MAM_STAT_EN_0 + Masked + 0 + + + DTCM_MAM_STAT_EN_1 + Enabled + 0x1 + + + + + OCRAM_MAM_STAT_EN + OCRAM Magic Address Match Status Enable + 2 + 1 + read-write + + + OCRAM_MAM_STAT_EN_0 + Masked + 0 + + + OCRAM_MAM_STAT_EN_1 + Enabled + 0x1 + + + + + ITCM_ERR_STAT_EN + ITCM Access Error Status Enable + 3 + 1 + read-write + + + ITCM_ERR_STAT_EN_0 + Masked + 0 + + + ITCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_STAT_EN + DTCM Access Error Status Enable + 4 + 1 + read-write + + + DTCM_ERR_STAT_EN_0 + Masked + 0 + + + DTCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_STAT_EN + OCRAM Access Error Status Enable + 5 + 1 + read-write + + + OCRAM_ERR_STAT_EN_0 + Masked + 0 + + + OCRAM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + Reserved + Reserved + 6 + 26 + read-only + + + + + INT_SIG_EN + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_MAM_SIG_EN + ITCM Magic Address Match Interrupt Enable + 0 + 1 + read-write + + + ITCM_MAM_SIG_EN_0 + Masked + 0 + + + ITCM_MAM_SIG_EN_1 + Enabled + 0x1 + + + + + DTCM_MAM_SIG_EN + DTCM Magic Address Match Interrupt Enable + 1 + 1 + read-write + + + DTCM_MAM_SIG_EN_0 + Masked + 0 + + + DTCM_MAM_SIG_EN_1 + Enabled + 0x1 + + + + + OCRAM_MAM_SIG_EN + OCRAM Magic Address Match Interrupt Enable + 2 + 1 + read-write + + + OCRAM_MAM_SIG_EN_0 + Masked + 0 + + + OCRAM_MAM_SIG_EN_1 + Enabled + 0x1 + + + + + ITCM_ERR_SIG_EN + ITCM Access Error Interrupt Enable + 3 + 1 + read-write + + + ITCM_ERR_SIG_EN_0 + Masked + 0 + + + ITCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_SIG_EN + DTCM Access Error Interrupt Enable + 4 + 1 + read-write + + + DTCM_ERR_SIG_EN_0 + Masked + 0 + + + DTCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_SIG_EN + OCRAM Access Error Interrupt Enable + 5 + 1 + read-write + + + OCRAM_ERR_SIG_EN_0 + Masked + 0 + + + OCRAM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + Reserved + Reserved + 6 + 26 + read-only + + + + + + + EWM + EWM + EWM + 0x400B4000 + + 0 + 0x6 + registers + + + EWM + 94 + + + + CTRL + Control Register + 0 + 8 + read-write + 0 + 0xFF + + + EWMEN + EWM enable. + 0 + 1 + read-writeOnce + + + ASSIN + EWM_in's Assertion State Select. + 1 + 1 + read-writeOnce + + + INEN + Input Enable. + 2 + 1 + read-writeOnce + + + INTEN + Interrupt Enable. + 3 + 1 + read-write + + + + + SERV + Service Register + 0x1 + 8 + write-only + 0 + 0xFF + + + SERVICE + SERVICE + 0 + 8 + write-only + + + + + CMPL + Compare Low Register + 0x2 + 8 + read-writeOnce + 0 + 0xFF + + + COMPAREL + COMPAREL + 0 + 8 + read-writeOnce + + + + + CMPH + Compare High Register + 0x3 + 8 + read-writeOnce + 0xFF + 0xFF + + + COMPAREH + COMPAREH + 0 + 8 + read-writeOnce + + + + + CLKCTRL + Clock Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + CLKSEL + CLKSEL + 0 + 2 + read-writeOnce + + + + + CLKPRESCALER + Clock Prescaler Register + 0x5 + 8 + read-writeOnce + 0 + 0xFF + + + CLK_DIV + CLK_DIV + 0 + 8 + read-writeOnce + + + + + + + WDOG1 + WDOG + WDOG + WDOG + 0x400B8000 + + 0 + 0xA + registers + + + WDOG1 + 92 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + WDZST + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + WDBG + 1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + WDE + 2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDT + 3 + 1 + read-write + + + WDT_0 + no description available + 0 + + + WDT_1 + no description available + 0x1 + + + + + SRS + SRS + 4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDA + 5 + 1 + read-write + + + WDA_0 + no description available + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + software reset extension, an option way to generate software reset + 6 + 1 + read-write + + + SRE_0 + using original way to generate software reset (default) + 0 + + + SRE_1 + using new way to generate software reset. + 0x1 + + + + + WDW + WDW + 7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + WT + 8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + WSR + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + SFTW + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + TOUT + 1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + POR + 4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + WICT + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + WTIS + 14 + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + WIE + 15 + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + PDE + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + 0x400D0000 + + 0 + 0xA + registers + + + WDOG2 + 45 + + + + RTWDOG + WDOG + RTWDOG + 0x400BC000 + + 0 + 0x10 + registers + + + RTWDOG + 93 + + + + CS + Watchdog Control and Status Register + 0 + 32 + read-write + 0x2980 + 0xFFFFFFFF + + + STOP + Stop Enable + 0 + 1 + read-write + + + STOP_0 + Watchdog disabled in chip stop mode. + 0 + + + STOP_1 + Watchdog enabled in chip stop mode. + 0x1 + + + + + WAIT + Wait Enable + 1 + 1 + read-write + + + WAIT_0 + Watchdog disabled in chip wait mode. + 0 + + + WAIT_1 + Watchdog enabled in chip wait mode. + 0x1 + + + + + DBG + Debug Enable + 2 + 1 + read-write + + + DBG_0 + Watchdog disabled in chip debug mode. + 0 + + + DBG_1 + Watchdog enabled in chip debug mode. + 0x1 + + + + + TST + Watchdog Test + 3 + 2 + read-write + + + TST_0 + Watchdog test mode disabled. + 0 + + + TST_1 + Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + 0x1 + + + TST_2 + Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + 0x2 + + + TST_3 + Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + 0x3 + + + + + UPDATE + Allow updates + 5 + 1 + read-write + + + UPDATE_0 + Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + 0 + + + UPDATE_1 + Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + 0x1 + + + + + INT + Watchdog Interrupt + 6 + 1 + read-write + + + INT_0 + Watchdog interrupts are disabled. Watchdog resets are not delayed. + 0 + + + INT_1 + Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + 0x1 + + + + + EN + Watchdog Enable + 7 + 1 + read-write + + + EN_0 + Watchdog disabled. + 0 + + + EN_1 + Watchdog enabled. + 0x1 + + + + + CLK + Watchdog Clock + 8 + 2 + read-write + + + CLK_0 + Bus clock + 0 + + + CLK_1 + LPO clock + 0x1 + + + CLK_2 + INTCLK (internal clock) + 0x2 + + + CLK_3 + ERCLK (external reference clock) + 0x3 + + + + + RCS + Reconfiguration Success + 10 + 1 + read-only + + + RCS_0 + Reconfiguring WDOG. + 0 + + + RCS_1 + Reconfiguration is successful. + 0x1 + + + + + ULK + Unlock status + 11 + 1 + read-only + + + ULK_0 + WDOG is locked. + 0 + + + ULK_1 + WDOG is unlocked. + 0x1 + + + + + PRES + Watchdog prescaler + 12 + 1 + read-write + + + PRES_0 + 256 prescaler disabled. + 0 + + + PRES_1 + 256 prescaler enabled. + 0x1 + + + + + CMD32EN + Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + 13 + 1 + read-write + + + CMD32EN_0 + Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + 0 + + + CMD32EN_1 + Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + 0x1 + + + + + FLG + Watchdog Interrupt Flag + 14 + 1 + read-write + oneToClear + + + FLG_0 + No interrupt occurred. + 0 + + + FLG_1 + An interrupt occurred. + 0x1 + + + + + WIN + Watchdog Window + 15 + 1 + read-write + + + WIN_0 + Window mode disabled. + 0 + + + WIN_1 + Window mode enabled. + 0x1 + + + + + + + CNT + Watchdog Counter Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CNTLOW + Low byte of the Watchdog Counter + 0 + 8 + read-write + + + CNTHIGH + High byte of the Watchdog Counter + 8 + 8 + read-write + + + + + TOVAL + Watchdog Timeout Value Register + 0x8 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + TOVALLOW + Low byte of the timeout value + 0 + 8 + read-write + + + TOVALHIGH + High byte of the timeout value + 8 + 8 + read-write + + + + + WIN + Watchdog Window Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINLOW + Low byte of Watchdog Window + 0 + 8 + read-write + + + WINHIGH + High byte of Watchdog Window + 8 + 8 + read-write + + + + + + + ADC1 + Analog-to-Digital Converter + ADC + ADC1_ + ADC + 0x400C4000 + + 0 + 0x5C + registers + + + ADC1 + 67 + + + + HC0 + Control register for hardware triggers + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + HC%s + Control register for hardware triggers + 0x4 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register for HW triggers + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + + + R0 + Data result register for HW triggers + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + R%s + Data result register for HW triggers + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x44 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 10 + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 11 + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 13 + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + ADTRG_1 + Hardware trigger selected + 0x1 + + + + + AVGS + Hardware Average select + 14 + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 16 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 7 + 1 + read-write + + + + + GS + General status register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynchronous wake up interrupt occurred in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 16 + 12 + read-write + + + + + OFS + Offset correction value register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 12 + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + ADC2 + Analog-to-Digital Converter + ADC + ADC2_ + 0x400C8000 + + 0 + 0x5C + registers + + + ADC2 + 68 + + + + TRNG + TRNG + TRNG + 0x400CC000 + + 0 + 0xF8 + registers + + + TRNG + 53 + + + + MCTL + Miscellaneous Control Register + 0 + 32 + read-write + 0x12001 + 0xFFFFFFFF + + + SAMP_MODE + Sample Mode + 0 + 2 + read-write + + + SAMP_MODE_0 + use Von Neumann data into both Entropy shifter and Statistical Checker + 0 + + + SAMP_MODE_1 + use raw data into both Entropy shifter and Statistical Checker + 0x1 + + + SAMP_MODE_2 + use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + 0x2 + + + SAMP_MODE_3 + undefined/reserved. + 0x3 + + + + + OSC_DIV + Oscillator Divide + 2 + 2 + read-write + + + OSC_DIV_0 + use ring oscillator with no divide + 0 + + + OSC_DIV_1 + use ring oscillator divided-by-2 + 0x1 + + + OSC_DIV_2 + use ring oscillator divided-by-4 + 0x2 + + + OSC_DIV_3 + use ring oscillator divided-by-8 + 0x3 + + + + + UNUSED4 + This bit is unused. Always reads zero. + 4 + 1 + read-only + + + UNUSED5 + This bit is unused. Always reads zero. + 5 + 1 + read-only + + + RST_DEF + Reset Defaults + 6 + 1 + write-only + + + FOR_SCLK + Force System Clock + 7 + 1 + read-write + + + FCT_FAIL + Read only: Frequency Count Fail + 8 + 1 + read-only + + + FCT_VAL + Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. + 9 + 1 + read-only + + + ENT_VAL + Read only: Entropy Valid + 10 + 1 + read-only + + + TST_OUT + Read only: Test point inside ring oscillator. + 11 + 1 + read-only + + + ERR + Read: Error status + 12 + 1 + read-write + oneToClear + + + TSTOP_OK + TRNG_OK_TO_STOP + 13 + 1 + read-only + + + LRUN_CONT + Long run count continues between entropy generations + 14 + 1 + read-write + + + PRGM + Programming Mode Select + 16 + 1 + read-write + + + + + SCMISC + Statistical Check Miscellaneous Register + 0x4 + 32 + read-write + 0x10022 + 0xFFFFFFFF + + + LRUN_MAX + LONG RUN MAX LIMIT + 0 + 8 + read-write + + + RTY_CT + RETRY COUNT + 16 + 4 + read-write + + + + + PKRRNG + Poker Range Register + 0x8 + 32 + read-write + 0x9A3 + 0xFFFFFFFF + + + PKR_RNG + Poker Range + 0 + 16 + read-write + + + + + PKRMAX + Poker Maximum Limit Register + MAX_SQ + 0xC + 32 + read-write + 0x6920 + 0xFFFFFFFF + + + PKR_MAX + Poker Maximum Limit. + 0 + 24 + read-write + + + + + PKRSQ + Poker Square Calculation Result Register + MAX_SQ + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_SQ + Poker Square Calculation Result. + 0 + 24 + read-only + + + + + SDCTL + Seed Control Register + 0x10 + 32 + read-write + 0xC8009C4 + 0xFFFFFFFF + + + SAMP_SIZE + Sample Size + 0 + 16 + read-write + + + ENT_DLY + Entropy Delay + 16 + 16 + read-write + + + + + SBLIM + Sparse Bit Limit Register + SBLIM_TOTSAM + 0x14 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + SB_LIM + Sparse Bit Limit + 0 + 10 + read-write + + + + + TOTSAM + Total Samples Register + SBLIM_TOTSAM + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOT_SAM + Total Samples + 0 + 20 + read-only + + + + + FRQMIN + Frequency Count Minimum Limit Register + 0x18 + 32 + read-write + 0x640 + 0xFFFFFFFF + + + FRQ_MIN + Frequency Count Minimum Limit + 0 + 22 + read-write + + + + + FRQCNT + Frequency Count Register + MAX_CNT + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + FRQ_CT + Frequency Count + 0 + 22 + read-only + + + + + FRQMAX + Frequency Count Maximum Limit Register + MAX_CNT + 0x1C + 32 + read-write + 0x6400 + 0xFFFFFFFF + + + FRQ_MAX + Frequency Counter Maximum Limit + 0 + 22 + read-write + + + + + SCMC + Statistical Check Monobit Count Register + SCML_MC + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + MONO_CT + Monobit Count + 0 + 16 + read-only + + + + + SCML + Statistical Check Monobit Limit Register + SCML_MC + 0x20 + 32 + read-write + 0x10C0568 + 0xFFFFFFFF + + + MONO_MAX + Monobit Maximum Limit + 0 + 16 + read-write + + + MONO_RNG + Monobit Range + 16 + 16 + read-write + + + + + SCR1C + Statistical Check Run Length 1 Count Register + SCR1L_1C + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + R1_0_CT + Runs of Zero, Length 1 Count + 0 + 15 + read-only + + + R1_1_CT + Runs of One, Length 1 Count + 16 + 15 + read-only + + + + + SCR1L + Statistical Check Run Length 1 Limit Register + SCR1L_1C + 0x24 + 32 + read-write + 0xB20195 + 0xFFFFFFFF + + + RUN1_MAX + Run Length 1 Maximum Limit + 0 + 15 + read-write + + + RUN1_RNG + Run Length 1 Range + 16 + 15 + read-write + + + + + SCR2C + Statistical Check Run Length 2 Count Register + SCR2L_2C + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + R2_0_CT + Runs of Zero, Length 2 Count + 0 + 14 + read-only + + + R2_1_CT + Runs of One, Length 2 Count + 16 + 14 + read-only + + + + + SCR2L + Statistical Check Run Length 2 Limit Register + SCR2L_2C + 0x28 + 32 + read-write + 0x7A00DC + 0xFFFFFFFF + + + RUN2_MAX + Run Length 2 Maximum Limit + 0 + 14 + read-write + + + RUN2_RNG + Run Length 2 Range + 16 + 14 + read-write + + + + + SCR3C + Statistical Check Run Length 3 Count Register + SCR3L_3C + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + R3_0_CT + Runs of Zeroes, Length 3 Count + 0 + 13 + read-only + + + R3_1_CT + Runs of Ones, Length 3 Count + 16 + 13 + read-only + + + + + SCR3L + Statistical Check Run Length 3 Limit Register + SCR3L_3C + 0x2C + 32 + read-write + 0x58007D + 0xFFFFFFFF + + + RUN3_MAX + Run Length 3 Maximum Limit + 0 + 13 + read-write + + + RUN3_RNG + Run Length 3 Range + 16 + 13 + read-write + + + + + SCR4C + Statistical Check Run Length 4 Count Register + SCR4L_4C + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + R4_0_CT + Runs of Zero, Length 4 Count + 0 + 12 + read-only + + + R4_1_CT + Runs of One, Length 4 Count + 16 + 12 + read-only + + + + + SCR4L + Statistical Check Run Length 4 Limit Register + SCR4L_4C + 0x30 + 32 + read-write + 0x40004B + 0xFFFFFFFF + + + RUN4_MAX + Run Length 4 Maximum Limit + 0 + 12 + read-write + + + RUN4_RNG + Run Length 4 Range + 16 + 12 + read-write + + + + + SCR5C + Statistical Check Run Length 5 Count Register + SCR5L_5C + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + R5_0_CT + Runs of Zero, Length 5 Count + 0 + 11 + read-only + + + R5_1_CT + Runs of One, Length 5 Count + 16 + 11 + read-only + + + + + SCR5L + Statistical Check Run Length 5 Limit Register + SCR5L_5C + 0x34 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN5_MAX + Run Length 5 Maximum Limit + 0 + 11 + read-write + + + RUN5_RNG + Run Length 5 Range + 16 + 11 + read-write + + + + + SCR6PC + Statistical Check Run Length 6+ Count Register + SCR6PL_PC + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + R6P_0_CT + Runs of Zero, Length 6+ Count + 0 + 11 + read-only + + + R6P_1_CT + Runs of One, Length 6+ Count + 16 + 11 + read-only + + + + + SCR6PL + Statistical Check Run Length 6+ Limit Register + SCR6PL_PC + 0x38 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN6P_MAX + Run Length 6+ Maximum Limit + 0 + 11 + read-write + + + RUN6P_RNG + Run Length 6+ Range + 16 + 11 + read-write + + + + + STATUS + Status Register + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TF1BR0 + Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. + 0 + 1 + read-only + + + TF1BR1 + Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. + 1 + 1 + read-only + + + TF2BR0 + Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. + 2 + 1 + read-only + + + TF2BR1 + Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. + 3 + 1 + read-only + + + TF3BR0 + Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. + 4 + 1 + read-only + + + TF3BR1 + Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. + 5 + 1 + read-only + + + TF4BR0 + Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. + 6 + 1 + read-only + + + TF4BR1 + Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. + 7 + 1 + read-only + + + TF5BR0 + Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. + 8 + 1 + read-only + + + TF5BR1 + Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. + 9 + 1 + read-only + + + TF6PBR0 + Test Fail, 6 Plus Bit Run, Sampling 0s + 10 + 1 + read-only + + + TF6PBR1 + Test Fail, 6 Plus Bit Run, Sampling 1s + 11 + 1 + read-only + + + TFSB + Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. + 12 + 1 + read-only + + + TFLR + Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. + 13 + 1 + read-only + + + TFP + Test Fail, Poker. If TFP=1, the Poker Test has failed. + 14 + 1 + read-only + + + TFMB + Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. + 15 + 1 + read-only + + + RETRY_CT + RETRY COUNT + 16 + 4 + read-only + + + + + 16 + 0x4 + ENT[%s] + Entropy Read Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + PKRCNT10 + Statistical Check Poker Count 1 and 0 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_0_CT + Poker 0h Count + 0 + 16 + read-only + + + PKR_1_CT + Poker 1h Count + 16 + 16 + read-only + + + + + PKRCNT32 + Statistical Check Poker Count 3 and 2 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_2_CT + Poker 2h Count + 0 + 16 + read-only + + + PKR_3_CT + Poker 3h Count + 16 + 16 + read-only + + + + + PKRCNT54 + Statistical Check Poker Count 5 and 4 Register + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_4_CT + Poker 4h Count + 0 + 16 + read-only + + + PKR_5_CT + Poker 5h Count + 16 + 16 + read-only + + + + + PKRCNT76 + Statistical Check Poker Count 7 and 6 Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_6_CT + Poker 6h Count + 0 + 16 + read-only + + + PKR_7_CT + Poker 7h Count + 16 + 16 + read-only + + + + + PKRCNT98 + Statistical Check Poker Count 9 and 8 Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_8_CT + Poker 8h Count + 0 + 16 + read-only + + + PKR_9_CT + Poker 9h Count + 16 + 16 + read-only + + + + + PKRCNTBA + Statistical Check Poker Count B and A Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_A_CT + Poker Ah Count + 0 + 16 + read-only + + + PKR_B_CT + Poker Bh Count + 16 + 16 + read-only + + + + + PKRCNTDC + Statistical Check Poker Count D and C Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_C_CT + Poker Ch Count + 0 + 16 + read-only + + + PKR_D_CT + Poker Dh Count + 16 + 16 + read-only + + + + + PKRCNTFE + Statistical Check Poker Count F and E Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_E_CT + Poker Eh Count + 0 + 16 + read-only + + + PKR_F_CT + Poker Fh Count + 16 + 16 + read-only + + + + + SEC_CFG + Security Configuration Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + UNUSED0 + This bit is unused. Ignore. + 0 + 1 + read-write + + + NO_PRGM + If set, the TRNG registers cannot be programmed + 1 + 1 + read-write + + + NO_PRGM_0 + Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + 0 + + + NO_PRGM_1 + Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + 0x1 + + + + + UNUSED2 + This bit is unused. Ignore. + 2 + 1 + read-write + + + + + INT_CTRL + Interrupt Control Register + 0xA4 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding bit of INT_STATUS register cleared. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS register active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 of this register. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 of this register. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 of this register. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 of this register. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + + + INT_MASK + Mask Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding interrupt of INT_STATUS is masked. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS is active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 of this register. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 of this register. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 of this register. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 of this register. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + + + INT_STATUS + Interrupt Status Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_ERR + Read: Error status + 0 + 1 + read-only + + + HW_ERR_0 + no error + 0 + + + HW_ERR_1 + error detected. + 0x1 + + + + + ENT_VAL + Read only: Entropy Valid + 1 + 1 + read-only + + + ENT_VAL_0 + Busy generation entropy. Any value read is invalid. + 0 + + + ENT_VAL_1 + TRNG can be stopped and entropy is valid if read. + 0x1 + + + + + FRQ_CT_FAIL + Read only: Frequency Count Fail + 2 + 1 + read-only + + + FRQ_CT_FAIL_0 + No hardware nor self test frequency errors. + 0 + + + FRQ_CT_FAIL_1 + The frequency counter has detected a failure. + 0x1 + + + + + + + VID1 + Version ID Register (MS) + 0xF0 + 32 + read-only + 0x300301 + 0xFFFFFFFF + + + MIN_REV + Shows the IP's Minor revision of the TRNG. + 0 + 8 + read-only + + + MIN_REV_0 + Minor revision number for TRNG. + 0 + + + + + MAJ_REV + Shows the IP's Major revision of the TRNG. + 8 + 8 + read-only + + + MAJ_REV_1 + Major revision number for TRNG. + 0x1 + + + + + IP_ID + Shows the IP ID. + 16 + 16 + read-only + + + IP_ID_48 + ID for TRNG. + 0x30 + + + + + + + VID2 + Version ID Register (LS) + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CONFIG_OPT + Shows the IP's Configuaration options for the TRNG. + 0 + 8 + read-only + + + CONFIG_OPT_0 + TRNG_CONFIG_OPT for TRNG. + 0 + + + + + ECO_REV + Shows the IP's ECO revision of the TRNG. + 8 + 8 + read-only + + + ECO_REV_0 + TRNG_ECO_REV for TRNG. + 0 + + + + + INTG_OPT + Shows the integration options for the TRNG. + 16 + 8 + read-only + + + INTG_OPT_0 + INTG_OPT for TRNG. + 0 + + + + + ERA + Shows the compile options for the TRNG. + 24 + 8 + read-only + + + ERA_0 + COMPILE_OPT for TRNG. + 0 + + + + + + + + + SNVS + SNVS + SNVS + 0x400D4000 + + 0 + 0x10000 + registers + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + + HPLR + SNVS_HP Lock Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WSL + Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WSL_0 + Write access is allowed + 0 + + + ZMK_WSL_1 + Write access is not allowed + 0x1 + + + + + ZMK_RSL + Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RSL_0 + Read access is allowed (only in software Programming mode) + 0 + + + ZMK_RSL_1 + Read access is not allowed + 0x1 + + + + + SRTC_SL + Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_SL_0 + Write access is allowed + 0 + + + SRTC_SL_1 + Write access is not allowed + 0x1 + + + + + LPCALB_SL + LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_SL_0 + Write access is allowed + 0 + + + LPCALB_SL_1 + Write access is not allowed + 0x1 + + + + + MC_SL + Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_SL_0 + Write access (increment) is allowed + 0 + + + MC_SL_1 + Write access (increment) is not allowed + 0x1 + + + + + GPR_SL + General Purpose Register Soft Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_SL_0 + Write access is allowed + 0 + + + GPR_SL_1 + Write access is not allowed + 0x1 + + + + + LPSVCR_SL + LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_SL_0 + Write access is allowed + 0 + + + LPSVCR_SL_1 + Write access is not allowed + 0x1 + + + + + LPTDCR_SL + LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR + 8 + 1 + read-write + + + LPTDCR_SL_0 + Write access is allowed + 0 + + + LPTDCR_SL_1 + Write access is not allowed + 0x1 + + + + + MKS_SL + Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR + 9 + 1 + read-write + + + MKS_SL_0 + Write access is allowed + 0 + + + MKS_SL_1 + Write access is not allowed + 0x1 + + + + + HPSVCR_L + HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR + 16 + 1 + read-write + + + HPSVCR_L_0 + Write access is allowed + 0 + + + HPSVCR_L_1 + Write access is not allowed + 0x1 + + + + + HPSICR_L + HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR + 17 + 1 + read-write + + + HPSICR_L_0 + Write access is allowed + 0 + + + HPSICR_L_1 + Write access is not allowed + 0x1 + + + + + HAC_L + High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR + 18 + 1 + read-write + + + HAC_L_0 + Write access is allowed + 0 + + + HAC_L_1 + Write access is not allowed + 0x1 + + + + + + + HPCOMR + SNVS_HP Command Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSM_ST + SSM State Transition Transition state of the system security monitor + 0 + 1 + write-only + + + SSM_ST_DIS + SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state + 1 + 1 + read-write + + + SSM_ST_DIS_0 + Secure to Trusted State transition is enabled + 0 + + + SSM_ST_DIS_1 + Secure to Trusted State transition is disabled + 0x1 + + + + + SSM_SFNS_DIS + SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state + 2 + 1 + read-write + + + SSM_SFNS_DIS_0 + Soft Fail to Non-Secure State transition is enabled + 0 + + + SSM_SFNS_DIS_1 + Soft Fail to Non-Secure State transition is disabled + 0x1 + + + + + LP_SWR + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set + 4 + 1 + write-only + + + LP_SWR_0 + No Action + 0 + + + LP_SWR_1 + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, disables the LP software reset + 5 + 1 + read-write + + + LP_SWR_DIS_0 + LP software reset is enabled + 0 + + + LP_SWR_DIS_1 + LP software reset is disabled + 0x1 + + + + + SW_SV + Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation + 8 + 1 + read-write + + + SW_FSV + Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation + 9 + 1 + read-write + + + SW_LPSV + LP Software Security Violation When set, SNVS_LP treats this bit as a security violation + 10 + 1 + read-write + + + PROG_ZMK + Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism + 12 + 1 + write-only + + + PROG_ZMK_0 + No Action + 0 + + + PROG_ZMK_1 + Activate hardware key programming mechanism + 0x1 + + + + + MKS_EN + Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default + 13 + 1 + read-write + + + MKS_EN_0 + no description available + 0 + + + MKS_EN_1 + no description available + 0x1 + + + + + HAC_EN + High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state + 16 + 1 + read-write + + + HAC_EN_0 + High Assurance Counter is disabled + 0 + + + HAC_EN_1 + High Assurance Counter is enabled + 0x1 + + + + + HAC_LOAD + High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register + 17 + 1 + write-only + + + HAC_LOAD_0 + No Action + 0 + + + HAC_LOAD_1 + Load the HAC + 0x1 + + + + + HAC_CLEAR + High Assurance Counter Clear When set, it clears the High Assurance Counter Register + 18 + 1 + write-only + + + HAC_CLEAR_0 + No Action + 0 + + + HAC_CLEAR_1 + Clear the HAC + 0x1 + + + + + HAC_STOP + High Assurance Counter Stop This bit can be set only when SSM is in soft fail state + 19 + 1 + read-write + + + NPSWA_EN + Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only + 31 + 1 + read-write + + + + + HPCR + SNVS_HP Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real Time Counter Enable + 0 + 1 + read-write + + + RTC_EN_0 + RTC is disabled + 0 + + + RTC_EN_1 + RTC is enabled + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter + 1 + 1 + read-write + + + HPTA_EN_0 + HP Time Alarm Interrupt is disabled + 0 + + + HPTA_EN_1 + HP Time Alarm Interrupt is enabled + 0x1 + + + + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + DIS_PI_0 + Periodic interrupt will trigger a functional interrupt + 0 + + + DIS_PI_1 + Disable periodic interrupt in the function interrupt + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled + 3 + 1 + read-write + + + PI_EN_0 + HP Periodic Interrupt is disabled + 0 + + + PI_EN_1 + HP Periodic Interrupt is enabled + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines frequency of the periodic interrupt + 4 + 4 + read-write + + + PI_FREQ_0 + - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + 0 + + + PI_FREQ_1 + - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + 0x1 + + + PI_FREQ_2 + - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + 0x2 + + + PI_FREQ_3 + - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + 0x3 + + + PI_FREQ_4 + - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + 0x4 + + + PI_FREQ_5 + - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + 0x5 + + + PI_FREQ_6 + - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + 0x6 + + + PI_FREQ_7 + - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + 0x7 + + + PI_FREQ_8 + - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + 0x8 + + + PI_FREQ_9 + - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + 0x9 + + + PI_FREQ_10 + - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + 0xA + + + PI_FREQ_11 + - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + 0xB + + + PI_FREQ_12 + - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + 0xC + + + PI_FREQ_13 + - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + 0xD + + + PI_FREQ_14 + - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + 0xE + + + PI_FREQ_15 + - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + 0xF + + + + + HPCALB_EN + HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. + 8 + 1 + read-write + + + HPCALB_EN_0 + HP Timer calibration disabled + 0 + + + HPCALB_EN_1 + HP Timer calibration enabled + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines signed calibration value for the HP Real Time Counter + 10 + 5 + read-write + + + HPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter + 0 + + + HPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter + 0x1 + + + HPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter + 0x2 + + + HPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter + 0xF + + + HPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter + 0x10 + + + HPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter + 0x11 + + + HPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter + 0x1E + + + HPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + HP_TS + HP Time Synchronize + 16 + 1 + read-write + + + HP_TS_0 + No Action + 0 + + + HP_TS_1 + Synchronize the HP Time Counter to the LP Time Counter + 0x1 + + + + + BTN_CONFIG + Button Configuration + 24 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 27 + 1 + read-write + + + + + HPSICR + SNVS_HP Security Interrupt Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 Interrupt is Disabled + 0 + + + SV0_EN_1 + Security Violation 0 Interrupt is Enabled + 0x1 + + + + + SV1_EN + Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 Interrupt is Disabled + 0 + + + SV1_EN_1 + Security Violation 1 Interrupt is Enabled + 0x1 + + + + + SV2_EN + Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 Interrupt is Disabled + 0 + + + SV2_EN_1 + Security Violation 2 Interrupt is Enabled + 0x1 + + + + + SV3_EN + Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 Interrupt is Disabled + 0 + + + SV3_EN_1 + Security Violation 3 Interrupt is Enabled + 0x1 + + + + + SV4_EN + Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 Interrupt is Disabled + 0 + + + SV4_EN_1 + Security Violation 4 Interrupt is Enabled + 0x1 + + + + + SV5_EN + Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 Interrupt is Disabled + 0 + + + SV5_EN_1 + Security Violation 5 Interrupt is Enabled + 0x1 + + + + + LPSVI_EN + LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section + 31 + 1 + read-write + + + LPSVI_EN_0 + LP Security Violation Interrupt is Disabled + 0 + + + LPSVI_EN_1 + LP Security Violation Interrupt is Enabled + 0x1 + + + + + + + HPSVCR + SNVS_HP Security Violation Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_CFG + Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input + 0 + 1 + read-write + + + SV0_CFG_0 + Security Violation 0 is a non-fatal violation + 0 + + + SV0_CFG_1 + Security Violation 0 is a fatal violation + 0x1 + + + + + SV1_CFG + Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input + 1 + 1 + read-write + + + SV1_CFG_0 + Security Violation 1 is a non-fatal violation + 0 + + + SV1_CFG_1 + Security Violation 1 is a fatal violation + 0x1 + + + + + SV2_CFG + Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input + 2 + 1 + read-write + + + SV2_CFG_0 + Security Violation 2 is a non-fatal violation + 0 + + + SV2_CFG_1 + Security Violation 2 is a fatal violation + 0x1 + + + + + SV3_CFG + Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input + 3 + 1 + read-write + + + SV3_CFG_0 + Security Violation 3 is a non-fatal violation + 0 + + + SV3_CFG_1 + Security Violation 3 is a fatal violation + 0x1 + + + + + SV4_CFG + Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input + 4 + 1 + read-write + + + SV4_CFG_0 + Security Violation 4 is a non-fatal violation + 0 + + + SV4_CFG_1 + Security Violation 4 is a fatal violation + 0x1 + + + + + SV5_CFG + Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input + 5 + 2 + read-write + + + SV5_CFG_0 + Security Violation 5 is disabled + 0 + + + SV5_CFG_1 + Security Violation 5 is a non-fatal violation + 0x1 + + + SV5_CFG_2 + Security Violation 5 is a fatal violation + #1x + + + + + LPSV_CFG + LP Security Violation Configuration This field configures the LP security violation source. + 30 + 2 + read-write + + + LPSV_CFG_0 + LP security violation is disabled + 0 + + + LPSV_CFG_1 + LP security violation is a non-fatal violation + 0x1 + + + LPSV_CFG_2 + LP security violation is a fatal violation + #1x + + + + + + + HPSR + SNVS_HP Status Register + 0x14 + 32 + read-write + 0x80003000 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. + 0 + 1 + read-write + oneToClear + + + HPTA_0 + No time alarm interrupt occurred. + 0 + + + HPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + PI + Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. + 1 + 1 + read-write + oneToClear + + + PI_0 + No periodic interrupt occurred. + 0 + + + PI_1 + A periodic interrupt occurred. + 0x1 + + + + + LPDIS + Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS + 4 + 1 + read-only + + + BTN + Button Value of the BTN input + 6 + 1 + read-only + + + BI + Button Interrupt Signal ipi_snvs_btn_int_b was asserted. + 7 + 1 + read-write + oneToClear + + + SSM_STATE + System Security Monitor State This field contains the encoded state of the SSM's state machine + 8 + 4 + read-only + + + SSM_STATE_0 + Init + 0 + + + SSM_STATE_1 + Hard Fail + 0x1 + + + SSM_STATE_3 + Soft Fail + 0x3 + + + SSM_STATE_8 + Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + 0x8 + + + SSM_STATE_9 + Check + 0x9 + + + SSM_STATE_11 + Non-Secure + 0xB + + + SSM_STATE_13 + Trusted + 0xD + + + SSM_STATE_15 + Secure + 0xF + + + + + SECURITY_CONFIG + Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS + 12 + 4 + read-only + + + FAB_CONFIG + FAB configuration + 0 + + + OPEN_CONFIG + OPEN configuration + 0x1 + + + OPEN_CONFIG + OPEN configuration + 0x2 + + + OPEN_CONFIG + OPEN configuration + 0x3 + + + FIELD_RETURN_CONFIG + FIELD RETURN configuration + #x1xx + + + FAB_CONFIG + FAB configuration + 0x8 + + + CLOSED_CONFIG + CLOSED configuration + 0x9 + + + CLOSED_CONFIG + CLOSED configuration + 0xA + + + CLOSED_CONFIG + CLOSED configuration + 0xB + + + + + OTPMK_SYNDROME + One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location + 16 + 9 + read-only + + + OTPMK_ZERO + One Time Programmable Master Key is Equal to Zero + 27 + 1 + read-only + + + OTPMK_ZERO_0 + The OTPMK is not zero. + 0 + + + OTPMK_ZERO_1 + The OTPMK is zero. + 0x1 + + + + + ZMK_ZERO + Zeroizable Master Key is Equal to Zero + 31 + 1 + read-only + + + ZMK_ZERO_0 + The ZMK is not zero. + 0 + + + ZMK_ZERO_1 + The ZMK is zero. + 0x1 + + + + + + + HPSVSR + SNVS_HP Security Violation Status Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + SV0 + Security Violation 0 security violation was detected. + 0 + 1 + read-write + oneToClear + + + SV0_0 + No Security Violation 0 security violation was detected. + 0 + + + SV0_1 + Security Violation 0 security violation was detected. + 0x1 + + + + + SV1 + Security Violation 1 security violation was detected. + 1 + 1 + read-write + oneToClear + + + SV1_0 + No Security Violation 1 security violation was detected. + 0 + + + SV1_1 + Security Violation 1 security violation was detected. + 0x1 + + + + + SV2 + Security Violation 2 security violation was detected. + 2 + 1 + read-write + oneToClear + + + SV2_0 + No Security Violation 2 security violation was detected. + 0 + + + SV2_1 + Security Violation 2 security violation was detected. + 0x1 + + + + + SV3 + Security Violation 3 security violation was detected. + 3 + 1 + read-write + oneToClear + + + SV3_0 + No Security Violation 3 security violation was detected. + 0 + + + SV3_1 + Security Violation 3 security violation was detected. + 0x1 + + + + + SV4 + Security Violation 4 security violation was detected. + 4 + 1 + read-write + oneToClear + + + SV4_0 + No Security Violation 4 security violation was detected. + 0 + + + SV4_1 + Security Violation 4 security violation was detected. + 0x1 + + + + + SV5 + Security Violation 5 security violation was detected. + 5 + 1 + read-write + oneToClear + + + SV5_0 + No Security Violation 5 security violation was detected. + 0 + + + SV5_1 + Security Violation 5 security violation was detected. + 0x1 + + + + + SW_SV + Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register + 13 + 1 + read-only + + + SW_FSV + Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register + 14 + 1 + read-only + + + SW_LPSV + LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register + 15 + 1 + read-only + + + ZMK_SYNDROME + Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register + 16 + 9 + read-only + + + ZMK_ECC_FAIL + Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data + 27 + 1 + read-write + oneToClear + + + ZMK_ECC_FAIL_0 + ZMK ECC Failure was not detected. + 0 + + + ZMK_ECC_FAIL_1 + ZMK ECC Failure was detected. + 0x1 + + + + + LP_SEC_VIO + LP Security Violation A security volation was detected in the SNVS low power section. + 31 + 1 + read-only + + + + + HPHACIVR + SNVS_HP High Assurance Counter IV Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAC_COUNTER_IV + High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter + 0 + 32 + read-write + + + + + HPHACR + SNVS_HP High Assurance Counter Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + HAC_COUNTER + High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock + 0 + 32 + read-only + + + + + HPRTCMR + SNVS_HP Real Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter The most-significant 15 bits of the RTC + 0 + 15 + read-write + + + + + HPRTCLR + SNVS_HP Real Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter least-significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_MS + HP Time Alarm, most-significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_LS + HP Time Alarm, 32 least-significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WHL + Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WHL_0 + Write access is allowed. + 0 + + + ZMK_WHL_1 + Write access is not allowed. + 0x1 + + + + + ZMK_RHL + Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RHL_0 + Read access is allowed (only in software programming mode). + 0 + + + ZMK_RHL_1 + Read access is not allowed. + 0x1 + + + + + SRTC_HL + Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_HL_0 + Write access is allowed. + 0 + + + SRTC_HL_1 + Write access is not allowed. + 0x1 + + + + + LPCALB_HL + LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_HL_0 + Write access is allowed. + 0 + + + LPCALB_HL_1 + Write access is not allowed. + 0x1 + + + + + MC_HL + Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_HL_0 + Write access (increment) is allowed. + 0 + + + MC_HL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General Purpose Register Hard Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_HL_0 + Write access is allowed. + 0 + + + GPR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPSVCR_HL + LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_HL_0 + Write access is allowed. + 0 + + + LPSVCR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPTDCR_HL + LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR + 8 + 1 + read-write + + + LPTDCR_HL_0 + Write access is allowed. + 0 + + + LPTDCR_HL_1 + Write access is not allowed. + 0x1 + + + + + MKS_HL + Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register + 9 + 1 + read-write + + + MKS_HL_0 + Write access is allowed. + 0 + + + MKS_HL_1 + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + SRTC_ENV + Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational + 0 + 1 + read-write + + + SRTC_ENV_0 + SRTC is disabled or invalid. + 0 + + + SRTC_ENV_1 + SRTC is enabled and valid. + 0x1 + + + + + LPTA_EN + LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter + 1 + 1 + read-write + + + LPTA_EN_0 + LP time alarm interrupt is disabled. + 0 + + + LPTA_EN_1 + LP time alarm interrupt is enabled. + 0x1 + + + + + MC_ENV + Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) + 2 + 1 + read-write + + + MC_ENV_0 + MC is disabled or invalid. + 0 + + + MC_ENV_1 + MC is enabled and valid. + 0x1 + + + + + LPWUI_EN + LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm ) + 3 + 1 + read-write + + + SRTC_INV_EN + If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) + 4 + 1 + read-write + + + SRTC_INV_EN_0 + SRTC stays valid in the case of security violation. + 0 + + + SRTC_INV_EN_1 + SRTC is invalidated in the case of security violation. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, software can control the system power + 5 + 1 + read-write + + + DP_EN_0 + Smart PMIC enabled. + 0 + + + DP_EN_1 + Dumb PMIC enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power + 6 + 1 + read-write + + + TOP_0 + Leave system power on. + 0 + + + TOP_1 + Turn off system power. + 0x1 + + + + + PWR_GLITCH_EN + Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted + 7 + 1 + read-write + + + LPCALB_EN + LP Calibration Enable When set, enables the SRTC calibration mechanism + 8 + 1 + read-write + + + LPCALB_EN_0 + SRTC Time calibration is disabled. + 0 + + + LPCALB_EN_1 + SRTC Time calibration is enabled. + 0x1 + + + + + LPCALB_VAL + LP Calibration Value Defines signed calibration value for SRTC + 10 + 5 + read-write + + + LPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter clock + 0 + + + LPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter clock + 0x1 + + + LPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter clock + 0x2 + + + LPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter clock + 0xF + + + LPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter clock + 0x10 + + + LPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter clock + 0x11 + + + LPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter clock + 0x1E + + + LPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter clock + 0x1F + + + + + BTN_PRESS_TIME + This field configures the button press time out values for the PMIC Logic + 16 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 18 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power + 20 + 2 + read-write + + + PK_EN + PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en + 22 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override + 23 + 1 + read-write + + + GPR_Z_DIS + General Purpose Registers Zeroization Disable + 24 + 1 + read-write + + + + + LPMKCR + SNVS_LP Master Key Control Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER_KEY_SEL + Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR + 0 + 2 + read-write + + + MASTER_KEY_SEL_0 + Select one time programmable master key. + #0x + + + MASTER_KEY_SEL_2 + no description available + 0x2 + + + MASTER_KEY_SEL_3 + no description available + 0x3 + + + + + ZMK_HWP + Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it + 2 + 1 + read-write + + + ZMK_HWP_0 + ZMK is in the software programming mode. + 0 + + + ZMK_HWP_1 + ZMK is in the hardware programming mode. + 0x1 + + + + + ZMK_VAL + Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules + 3 + 1 + read-write + + + ZMK_VAL_0 + ZMK is not valid. + 0 + + + ZMK_VAL_1 + ZMK is valid. + 0x1 + + + + + ZMK_ECC_EN + Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register + 4 + 1 + read-write + + + ZMK_ECC_EN_0 + ZMK ECC check is disabled. + 0 + + + ZMK_ECC_EN_1 + ZMK ECC check is enabled. + 0x1 + + + + + ZMK_ECC_VALUE + Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register + 7 + 9 + read-only + + + + + LPSVCR + SNVS_LP Security Violation Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Enable This bit enables Security Violation 0 Input + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 is disabled in the LP domain. + 0 + + + SV0_EN_1 + Security Violation 0 is enabled in the LP domain. + 0x1 + + + + + SV1_EN + Security Violation 1 Enable This bit enables Security Violation 1 Input + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 is disabled in the LP domain. + 0 + + + SV1_EN_1 + Security Violation 1 is enabled in the LP domain. + 0x1 + + + + + SV2_EN + Security Violation 2 Enable This bit enables Security Violation 2 Input + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 is disabled in the LP domain. + 0 + + + SV2_EN_1 + Security Violation 2 is enabled in the LP domain. + 0x1 + + + + + SV3_EN + Security Violation 3 Enable This bit enables Security Violation 3 Input + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 is disabled in the LP domain. + 0 + + + SV3_EN_1 + Security Violation 3 is enabled in the LP domain. + 0x1 + + + + + SV4_EN + Security Violation 4 Enable This bit enables Security Violation 4 Input + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 is disabled in the LP domain. + 0 + + + SV4_EN_1 + Security Violation 4 is enabled in the LP domain. + 0x1 + + + + + SV5_EN + Security Violation 5 Enable This bit enables Security Violation 5 Input + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 is disabled in the LP domain. + 0 + + + SV5_EN_1 + Security Violation 5 is enabled in the LP domain. + 0x1 + + + + + + + LPTDCR + SNVS_LP Tamper Detectors Configuration Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTCR_EN + SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. + 1 + 1 + read-write + + + SRTCR_EN_0 + SRTC rollover is disabled. + 0 + + + SRTCR_EN_1 + SRTC rollover is enabled. + 0x1 + + + + + MCR_EN + MC Rollover Enable When set, an MC Rollover event generates an LP security violation. + 2 + 1 + read-write + + + MCR_EN_0 + MC rollover is disabled. + 0 + + + MCR_EN_1 + MC rollover is enabled. + 0x1 + + + + + ET1_EN + External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation + 9 + 1 + read-write + + + ET1_EN_0 + External tamper 1 is disabled. + 0 + + + ET1_EN_1 + External tamper 1 is enabled. + 0x1 + + + + + ET1P + External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1. + 11 + 1 + read-write + + + ET1P_0 + External tamper 1 is active low. + 0 + + + ET1P_1 + External tamper 1 is active high. + 0x1 + + + + + PFD_OBSERV + System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) + 14 + 1 + read-write + + + POR_OBSERV + Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS + 15 + 1 + read-write + + + OSCB + Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted + 28 + 1 + read-write + + + OSCB_0 + Normal SRTC clock oscillator not bypassed. + 0 + + + OSCB_1 + Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + 0x1 + + + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + LPTA + LP Time Alarm + 0 + 1 + read-write + oneToClear + + + LPTA_0 + No time alarm interrupt occurred. + 0 + + + LPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + SRTCR + Secure Real Time Counter Rollover + 1 + 1 + read-write + oneToClear + + + SRTCR_0 + SRTC has not reached its maximum value. + 0 + + + SRTCR_1 + SRTC has reached its maximum value. + 0x1 + + + + + MCR + Monotonic Counter Rollover + 2 + 1 + read-write + oneToClear + + + MCR_0 + MC has not reached its maximum value. + 0 + + + MCR_1 + MC has reached its maximum value. + 0x1 + + + + + PGD + Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected. + 3 + 1 + read-write + oneToClear + + + ET1D + External Tampering 1 Detected + 9 + 1 + read-write + oneToClear + + + ET1D_0 + External tampering 1 not detected. + 0 + + + ET1D_1 + External tampering 1 detected. + 0x1 + + + + + ESVD + External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports + 16 + 1 + read-write + oneToClear + + + ESVD_0 + No external security violation. + 0 + + + ESVD_1 + External security violation is detected. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 17 + 1 + read-write + oneToClear + + + EO_0 + Emergency off was not detected. + 0 + + + EO_1 + Emergency off was detected. + 0x1 + + + + + SPO + Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time + 18 + 1 + read-write + oneToClear + + + SPO_0 + Set Power Off was not detected. + 0 + + + SPO_1 + Set Power Off was detected. + 0x1 + + + + + SED + Scan Exit Detected + 20 + 1 + read-write + oneToClear + + + SED_0 + Scan exit was not detected. + 0 + + + SED_1 + Scan exit was detected. + 0x1 + + + + + LPNS + LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state + 30 + 1 + read-only + + + LPNS_0 + LP section was not programmed in the non-secure state. + 0 + + + LPNS_1 + LP section was programmed in the non-secure state. + 0x1 + + + + + LPS + LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state + 31 + 1 + read-only + + + LPS_0 + LP section was not programmed in secure or trusted state. + 0 + + + LPS_1 + LP section was programmed in secure or trusted state. + 0x1 + + + + + + + LPSRTCMR + SNVS_LP Secure Real Time Counter MSB Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter The most-significant 15 bits of the SRTC + 0 + 15 + read-write + + + + + LPSRTCLR + SNVS_LP Secure Real Time Counter LSB Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set + 0 + 32 + read-write + + + + + LPTAR + SNVS_LP Time Alarm Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPTA + LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) + 0 + 32 + read-write + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected + 0 + 16 + read-only + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses + 16 + 16 + read-only + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected + 0 + 32 + read-only + + + + + LPPGDR + SNVS_LP Power Glitch Detector Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + PGD + Power Glitch Detector Value + 0 + 32 + read-write + + + + + LPGPR0_legacy_alias + SNVS_LP General Purpose Register 0 (legacy alias) + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPZMKR[%s] + SNVS_LP Zeroizable Master Key Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK + Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR_alias[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPGPR[%s] + SNVS_LP General Purpose Registers 0 .. 7 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0104 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 8 + 8 + read-only + + + IP_ID + SNVS block ID + 16 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Options + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 8 + 8 + read-only + + + INTG_OPT + SNVS Integration Options + 16 + 8 + read-only + + + IP_ERA + IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 + 24 + 8 + read-only + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x400D8000 + + 0 + 0x180 + registers + + + + PLL_ARM + Analog ARM PLL control Register + 0 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_SET + Analog ARM PLL control Register + 0x4 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_CLR + Analog ARM PLL control Register + 0x8 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_TOG + Analog ARM PLL control Register + 0xC + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_SET + Analog USB1 480MHz PLL Control Register + 0x14 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_TOG + Analog USB1 480MHz PLL Control Register + 0x1C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2 + Analog USB2 480MHz PLL Control Register + 0x20 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_SET + Analog USB2 480MHz PLL Control Register + 0x24 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_CLR + Analog USB2 480MHz PLL Control Register + 0x28 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_TOG + Analog USB2 480MHz PLL Control Register + 0x2C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0 + 15 + read-write + + + ENABLE + Enable bit + 15 + 1 + read-write + + + ENABLE_0 + Spread spectrum modulation disabled + 0 + + + ENABLE_1 + Soread spectrum modulation enabled + 0x1 + + + + + STOP + Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 16 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + 30 bit numerator (A) of fractional loop divider (signed integer). + 0 + 30 + read-write + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + 30 bit Denominator (B) of fractional loop divider (unsigned integer). + 0 + 30 + read-write + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_VIDEO + Analog Video PLL control Register + 0xA0 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_SET + Analog Video PLL control Register + 0xA4 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_CLR + Analog Video PLL control Register + 0xA8 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_TOG + Analog Video PLL control Register + 0xAC + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_NUM + Numerator of Video PLL Fractional Loop Divider Register + 0xB0 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator + 0 + 30 + read-write + + + + + PLL_VIDEO_DENOM + Denominator of Video PLL Fractional Loop Divider Register + 0xC0 + 32 + read-write + 0x10A24447 + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the ethernet clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the ethernet clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the ethernet clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the ethernet clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 18 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PFD_480 + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528 + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_SET + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_CLR + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_TOG + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Register 2 + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Register 2 + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Register 2 + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Register 2 + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + PMU + PMU + CCM_ANALOG + PMU + PMU_ + 0x400D8000 + + 0 + 0x180 + registers + + + + REG_1P1 + Regulator 1P1 Register + 0x110 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_SET + Regulator 1P1 Register + 0x114 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_CLR + Regulator 1P1 Register + 0x118 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_TOG + Regulator 1P1 Register + 0x11C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_3P0 + Regulator 3P0 Register + 0x120 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_SET + Regulator 3P0 Register + 0x124 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_CLR + Regulator 3P0 Register + 0x128 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_TOG + Regulator 3P0 Register + 0x12C + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_2P5 + Regulator 2P5 Register + 0x130 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_SET + Regulator 2P5 Register + 0x134 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_CLR + Regulator 2P5 Register + 0x138 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_TOG + Regulator 2P5 Register + 0x13C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_CORE + Digital Regulator Core Register + 0x140 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_SET + Digital Regulator Core Register + 0x144 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_CLR + Digital Regulator Core Register + 0x148 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_TOG + Digital Regulator Core Register + 0x14C + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Control Register + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Control Register + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Control Register + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Control Register + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + TEMPMON + Temperature Monitor + CCM_ANALOG + TEMPMON + TEMPMON_ + 0x400D8000 + + 0 + 0x2A0 + registers + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0x180 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 20 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x184 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 20 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x188 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 20 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0x18C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 20 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x190 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x194 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x198 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x19C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE2 + Tempsensor Control Register 2 + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 16 + 12 + read-write + + + + + TEMPSENSE2_SET + Tempsensor Control Register 2 + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 16 + 12 + read-write + + + + + TEMPSENSE2_CLR + Tempsensor Control Register 2 + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 16 + 12 + read-write + + + + + TEMPSENSE2_TOG + Tempsensor Control Register 2 + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 16 + 12 + read-write + + + + + + + USB_ANALOG + USB Analog + CCM_ANALOG + USB_ANALOG + USB_ANALOG_ + 0x400D8000 + + 0 + 0x264 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0x1A0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x1A4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x1A8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x1AC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x1C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x1D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB1_MISC + USB Misc Register + 0x1F0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_SET + USB Misc Register + 0x1F4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_CLR + USB Misc Register + 0x1F8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_TOG + USB Misc Register + 0x1FC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_VBUS_DETECT + USB VBUS Detect Register + 0x200 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_SET + USB VBUS Detect Register + 0x204 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x208 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x20C + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_CHRG_DETECT + USB Charger Detect Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_SET + USB Charger Detect Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_CLR + USB Charger Detect Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_TOG + USB Charger Detect Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB2_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB2_MISC + USB Misc Register + 0x250 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_SET + USB Misc Register + 0x254 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_CLR + USB Misc Register + 0x258 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_TOG + USB Misc Register + 0x25C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + DIGPROG + Chip Silicon Version + 0x260 + 32 + read-only + 0x6A0001 + 0xFFFFFFFF + + + SILICON_REVISION + Chip silicon revision + 0 + 32 + read-only + + + SILICON_REVISION_6946817 + Silicon revision 1.1 + 0x6A0001 + + + + + + + + + XTALOSC24M + XTALOSC24M + CCM_ANALOG + XTALOSC24M + XTALOSC24M_ + 0x400D8000 + + 0 + 0x2D0 + registers + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + LOWPWR_CTRL + XTAL OSC (LP) Control Register + 0x270 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_SET + XTAL OSC (LP) Control Register + 0x274 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_CLR + XTAL OSC (LP) Control Register + 0x278 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_TOG + XTAL OSC (LP) Control Register + 0x27C + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + OSC_CONFIG0 + XTAL OSC Configuration 0 Register + 0x2A0 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_SET + XTAL OSC Configuration 0 Register + 0x2A4 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_CLR + XTAL OSC Configuration 0 Register + 0x2A8 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_TOG + XTAL OSC Configuration 0 Register + 0x2AC + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG1 + XTAL OSC Configuration 1 Register + 0x2B0 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_SET + XTAL OSC Configuration 1 Register + 0x2B4 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_CLR + XTAL OSC Configuration 1 Register + 0x2B8 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_TOG + XTAL OSC Configuration 1 Register + 0x2BC + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG2 + XTAL OSC Configuration 2 Register + 0x2C0 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_SET + XTAL OSC Configuration 2 Register + 0x2C4 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_CLR + XTAL OSC Configuration 2 Register + 0x2C8 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_TOG + XTAL OSC Configuration 2 Register + 0x2CC + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + + + USBPHY1 + USBPHY Register Reference Index + USBPHY + USBPHY1_ + USBPHY + 0x400D9000 + + 0 + 0x84 + registers + + + USB_PHY1 + 65 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates that the device has disconnected while in high-speed host mode. + 3 + 1 + read-only + + + RSVD1 + Reserved. + 4 + 2 + read-only + + + DEVPLUGIN_STATUS + Indicates that the device has been connected on the USB_DP and USB_DM lines. + 6 + 1 + read-only + + + RSVD2 + Reserved. + 7 + 1 + read-only + + + OTGID_STATUS + Indicates the results of ID pin on MiniAB plug + 8 + 1 + read-write + + + RSVD3 + Reserved. + 9 + 1 + read-only + + + RESUME_STATUS + Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. + 10 + 1 + read-only + + + RSVD4 + Reserved. + 11 + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + Running count of the failed pseudo-random generator loopback + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + Running count of the UTMI_RXERROR. + 16 + 10 + read-only + + + SQUELCH_COUNT + Running count of the squelch reset instead of normal end for HS RX. + 26 + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4030000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + + + USBPHY2 + USBPHY Register Reference Index + USBPHY + USBPHY2_ + 0x400DA000 + + 0 + 0x84 + registers + + + USB_PHY2 + 66 + + + + CSU + CSU registers + CSU + CSU_ + 0x400DC000 + + 0 + 0x35C + registers + + + CSU + 49 + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + CSL%s + Config security level register + 0 + 32 + read-write + 0x330033 + 0xFFFFFFFF + + + SUR_S2 + Secure user read access control for the second slave + 0 + 1 + read-write + + + SUR_S2_0 + The secure user read access is disabled for the second slave. + 0 + + + SUR_S2_1 + The secure user read access is enabled for the second slave. + 0x1 + + + + + SSR_S2 + Secure supervisor read access control for the second slave + 1 + 1 + read-write + + + SSR_S2_0 + The secure supervisor read access is disabled for the second slave. + 0 + + + SSR_S2_1 + The secure supervisor read access is enabled for the second slave. + 0x1 + + + + + NUR_S2 + Non-secure user read access control for the second slave + 2 + 1 + read-write + + + NUR_S2_0 + The non-secure user read access is disabled for the second slave. + 0 + + + NUR_S2_1 + The non-secure user read access is enabled for the second slave. + 0x1 + + + + + NSR_S2 + Non-secure supervisor read access control for the second slave + 3 + 1 + read-write + + + NSR_S2_0 + The non-secure supervisor read access is disabled for the second slave. + 0 + + + NSR_S2_1 + The non-secure supervisor read access is enabled for the second slave. + 0x1 + + + + + SUW_S2 + Secure user write access control for the second slave + 4 + 1 + read-write + + + SUW_S2_0 + The secure user write access is disabled for the second slave. + 0 + + + SUW_S2_1 + The secure user write access is enabled for the second slave. + 0x1 + + + + + SSW_S2 + Secure supervisor write access control for the second slave + 5 + 1 + read-write + + + SSW_S2_0 + The secure supervisor write access is disabled for the second slave. + 0 + + + SSW_S2_1 + The secure supervisor write access is enabled for the second slave. + 0x1 + + + + + NUW_S2 + Non-secure user write access control for the second slave + 6 + 1 + read-write + + + NUW_S2_0 + The non-secure user write access is disabled for the second slave. + 0 + + + NUW_S2_1 + The non-secure user write access is enabled for the second slave. + 0x1 + + + + + NSW_S2 + Non-secure supervisor write access control for the second slave + 7 + 1 + read-write + + + NSW_S2_0 + The non-secure supervisor write access is disabled for the second slave. + 0 + + + NSW_S2_1 + The non-secure supervisor write access is enabled for the second slave. + 0x1 + + + + + LOCK_S2 + The lock bit corresponding to the second slave. It is written by the secure software. + 8 + 1 + read-write + + + LOCK_S2_0 + Not locked. Bits 7-0 can be written by the software. + 0 + + + LOCK_S2_1 + Bits 7-0 are locked and cannot be written by the software + 0x1 + + + + + SUR_S1 + Secure user read access control for the first slave + 16 + 1 + read-write + + + SUR_S1_0 + The secure user read access is disabled for the first slave. + 0 + + + SUR_S1_1 + The secure user read access is enabled for the first slave. + 0x1 + + + + + SSR_S1 + Secure supervisor read access control for the first slave + 17 + 1 + read-write + + + SSR_S1_0 + The secure supervisor read access is disabled for the first slave. + 0 + + + SSR_S1_1 + The secure supervisor read access is enabled for the first slave. + 0x1 + + + + + NUR_S1 + Non-secure user read access control for the first slave + 18 + 1 + read-write + + + NUR_S1_0 + The non-secure user read access is disabled for the first slave. + 0 + + + NUR_S1_1 + The non-secure user read access is enabled for the first slave. + 0x1 + + + + + NSR_S1 + Non-secure supervisor read access control for the first slave + 19 + 1 + read-write + + + NSR_S1_0 + The non-secure supervisor read access is disabled for the first slave. + 0 + + + NSR_S1_1 + The non-secure supervisor read access is enabled for the first slave. + 0x1 + + + + + SUW_S1 + Secure user write access control for the first slave + 20 + 1 + read-write + + + SUW_S1_0 + The secure user write access is disabled for the first slave. + 0 + + + SUW_S1_1 + The secure user write access is enabled for the first slave. + 0x1 + + + + + SSW_S1 + Secure supervisor write access control for the first slave + 21 + 1 + read-write + + + SSW_S1_0 + The secure supervisor write access is disabled for the first slave. + 0 + + + SSW_S1_1 + The secure supervisor write access is enabled for the first slave. + 0x1 + + + + + NUW_S1 + Non-secure user write access control for the first slave + 22 + 1 + read-write + + + NUW_S1_0 + The non-secure user write access is disabled for the first slave. + 0 + + + NUW_S1_1 + The non-secure user write access is enabled for the first slave. + 0x1 + + + + + NSW_S1 + Non-secure supervisor write access control for the first slave + 23 + 1 + read-write + + + NSW_S1_0 + The non-secure supervisor write access is disabled for the first slave. + 0 + + + NSW_S1_1 + The non-secure supervisor write access is enabled for the first slave + 0x1 + + + + + LOCK_S1 + The lock bit corresponding to the first slave. It is written by the secure software. + 24 + 1 + read-write + + + LOCK_S1_0 + Not locked. The bits 16-23 can be written by the software. + 0 + + + LOCK_S1_1 + The bits 16-23 are locked and can't be written by the software. + 0x1 + + + + + + + HP0 + HP0 register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_DMA + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA + 2 + 1 + read-write + + + HP_DMA_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DMA_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_LCDIF + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF + 4 + 1 + read-write + + + HP_LCDIF_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_LCDIF_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_CSI + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI + 6 + 1 + read-write + + + HP_CSI_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_CSI_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_PXP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP + 8 + 1 + read-write + + + HP_PXP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_PXP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_DCP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP + 10 + 1 + read-write + + + HP_DCP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DCP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit cannot be written by the software. + 0x1 + + + + + HP_ENET + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET + 14 + 1 + read-write + + + HP_ENET_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_ENET_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC1 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1 + 16 + 1 + read-write + + + HP_USDHC1_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC1_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC2 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2 + 18 + 1 + read-write + + + HP_USDHC2_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC2_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_TPSMP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP + 20 + 1 + read-write + + + HP_TPSMP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_TPSMP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USB + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB + 22 + 1 + read-write + + + HP_USB_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USB_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + SA + Secure access register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSA_DMA + Non-secure access policy indicator bit + 2 + 1 + read-write + + + NSA_DMA_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DMA_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_LCDIF + Non-secure access policy indicator bit + 4 + 1 + read-write + + + NSA_LCDIF_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_LCDIF_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_CSI + Non-secure access policy indicator bit + 6 + 1 + read-write + + + NSA_CSI_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_CSI_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_PXP + Non-Secure Access Policy indicator bit + 8 + 1 + read-write + + + NSA_PXP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_PXP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_DCP + Non-secure access policy indicator bit + 10 + 1 + read-write + + + NSA_DCP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DCP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_ENET + Non-secure access policy indicator bit + 14 + 1 + read-write + + + NSA_ENET_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_ENET_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET1 and ENET2 + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC1 + Non-secure access policy indicator bit + 16 + 1 + read-write + + + NSA_USDHC1_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC1_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC2 + Non-secure access policy indicator bit + 18 + 1 + read-write + + + NSA_USDHC2_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC2_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_TPSMP + Non-secure access policy indicator bit + 20 + 1 + read-write + + + NSA_TPSMP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_TPSMP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USB + Non-secure access policy indicator bit + 22 + 1 + read-write + + + NSA_USB_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USB_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + HPCONTROL0 + HPCONTROL0 register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPC_DMA + Indicates the privilege/user mode for the eDMA + 2 + 1 + read-write + + + HPC_DMA_0 + User mode for the corresponding master + 0 + + + HPC_DMA_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_LCDIF + Indicates the privilege/user mode for the LCDIF + 4 + 1 + read-write + + + HPC_LCDIF_0 + User mode for the corresponding master + 0 + + + HPC_LCDIF_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_CSI + Indicates the privilege/user mode for the CSI + 6 + 1 + read-write + + + HPC_CSI_0 + User mode for the corresponding master + 0 + + + HPC_CSI_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_PXP + Indicates the privilege/user mode for the PXP + 8 + 1 + read-write + + + HPC_PXP_0 + User mode for the corresponding master + 0 + + + HPC_PXP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_DCP + Indicates the privilege/user mode for the DCP + 10 + 1 + read-write + + + HPC_DCP_0 + User mode for the corresponding master + 0 + + + HPC_DCP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_ENET + Indicates the privilege/user mode for the ENET + 14 + 1 + read-write + + + HPC_ENET_0 + User mode for the corresponding master + 0 + + + HPC_ENET_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC1 + Indicates the privilege/user mode for the USDHC1 + 16 + 1 + read-write + + + HPC_USDHC1_0 + User mode for the corresponding master + 0 + + + HPC_USDHC1_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC2 + Indicates the privilege/user mode for the USDHC2 + 18 + 1 + read-write + + + HPC_USDHC2_0 + User mode for the corresponding master + 0 + + + HPC_USDHC2_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2. + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_TPSMP + Indicates the privilege/user mode for the TPSMP + 20 + 1 + read-write + + + HPC_TPSMP_0 + User mode for the corresponding master + 0 + + + HPC_TPSMP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP. + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USB + Indicates the privilege/user mode for the USB + 22 + 1 + read-write + + + HPC_USB_0 + User mode for the corresponding master + 0 + + + HPC_USB_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB. + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + + + TSC + Touch Screen Controller + TSC + TSC_ + 0x400E0000 + + 0 + 0x84 + registers + + + TSC_DIG + 40 + + + + BASIC_SETTING + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTO_MEASURE + Auto Measure + 0 + 1 + read-write + + + AUTO_MEASURE_0 + Disable Auto Measure + 0 + + + AUTO_MEASURE_1 + Auto Measure + 0x1 + + + + + _4_5_WIRE + 4/5 Wire detection + 4 + 1 + read-write + + + 4_5_WIRE_0 + 4-Wire Detection Mode + 0 + + + 4_5_WIRE_1 + 5-Wire Detection Mode + 0x1 + + + + + MEASURE_DELAY_TIME + Measure Delay Time + 8 + 24 + read-write + + + + + PRE_CHARGE_TIME + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_CHARGE_TIME + Before detection, the top screen needs some time before being pulled up to a high voltage. + 0 + 32 + read-write + + + + + FLOW_CONTROL + Flow Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_RST + Soft Reset + 0 + 1 + read-write + + + START_MEASURE + Start Measure + 4 + 1 + read-write + + + START_MEASURE_0 + Do not start measure for now + 0 + + + START_MEASURE_1 + Start measure the X/Y coordinate value + 0x1 + + + + + DROP_MEASURE + Drop Measure + 8 + 1 + read-write + + + DROP_MEASURE_0 + Do not drop measure for now + 0 + + + DROP_MEASURE_1 + Drop the measure and controller return to idle status + 0x1 + + + + + START_SENSE + Start Sense + 12 + 1 + read-write + + + START_SENSE_0 + Stay at idle status + 0 + + + START_SENSE_1 + Start sense detection and (if auto_measure set to 1) measure after detect a touch + 0x1 + + + + + DISABLE + This bit is for SW disable registers + 16 + 1 + read-write + + + DISABLE_0 + Leave HW state machine control + 0 + + + DISABLE_1 + SW set to idle status + 0x1 + + + + + + + MEASEURE_VALUE + Measure Value + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + Y_VALUE + Y Value + 0 + 12 + read-only + + + X_VALUE + X Value + 16 + 12 + read-only + + + + + INT_EN + Interrupt Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_INT_EN + Measure Interrupt Enable + 0 + 1 + read-write + + + MEASURE_INT_EN_0 + Disable measure interrupt + 0 + + + MEASURE_INT_EN_1 + Enable measure interrupt + 0x1 + + + + + DETECT_INT_EN + Detect Interrupt Enable + 4 + 1 + read-write + + + DETECT_INT_EN_0 + Disable detect interrupt + 0 + + + DETECT_INT_EN_1 + Enable detect interrupt + 0x1 + + + + + IDLE_SW_INT_EN + Idle Software Interrupt Enable + 12 + 1 + read-write + + + IDLE_SW_INT_EN_0 + Disable idle software interrupt + 0 + + + IDLE_SW_INT_EN_1 + Enable idle software interrupt + 0x1 + + + + + + + INT_SIG_EN + Interrupt Signal Enable + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_SIG_EN + Measure Signal Enable + 0 + 1 + read-write + + + DETECT_SIG_EN + Detect Signal Enable + 4 + 1 + read-write + + + DETECT_SIG_EN_0 + Disable detect signal + 0 + + + DETECT_SIG_EN_1 + Enable detect signal + 0x1 + + + + + VALID_SIG_EN + Valid Signal Enable + 8 + 1 + read-write + + + VALID_SIG_EN_0 + Disable valid signal + 0 + + + VALID_SIG_EN_1 + Enable valid signal + 0x1 + + + + + IDLE_SW_SIG_EN + Idle Software Signal Enable + 12 + 1 + read-write + + + IDLE_SW_SIG_EN_0 + Disable idle software signal + 0 + + + IDLE_SW_SIG_EN_1 + Enable idle software signal + 0x1 + + + + + + + INT_STATUS + Intterrupt Status + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE + Measure Signal + 0 + 1 + read-write + + + MEASURE_0 + Does not exist a measure signal + 0 + + + MEASURE_1 + Exist a measure signal + 0x1 + + + + + DETECT + Detect Signal + 4 + 1 + read-write + + + DETECT_0 + Does not exist a detect signal + 0 + + + DETECT_1 + Exist detect signal + 0x1 + + + + + VALID + Valid Signal + 8 + 1 + read-write + + + VALID_0 + There is no touch detected after measurement, indicates that the measured value is not valid + 0 + + + VALID_1 + There is touch detection after measurement, indicates that the measure is valid + 0x1 + + + + + IDLE_SW + Idle Software + 12 + 1 + read-write + + + IDLE_SW_0 + Haven't return to idle status + 0 + + + IDLE_SW_1 + Already return to idle status + 0x1 + + + + + + + DEBUG_MODE + no description available + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_CONV_VALUE + ADC Conversion Value + 0 + 12 + read-only + + + ADC_COCO + ADC COCO Signal + 12 + 1 + read-only + + + EXT_HWTS + Hardware Trigger Select Signal + 16 + 5 + read-write + + + TRIGGER + Trigger + 24 + 1 + read-write + + + TRIGGER_0 + No hardware trigger signal + 0 + + + TRIGGER_1 + Hardware trigger signal, the signal must last at least 1 ips clock period + 0x1 + + + + + ADC_COCO_CLEAR + ADC Coco Clear + 25 + 1 + read-write + + + ADC_COCO_CLEAR_0 + No ADC COCO clear + 0 + + + ADC_COCO_CLEAR_1 + Set ADC COCO clear + 0x1 + + + + + ADC_COCO_CLEAR_DISABLE + ADC COCO Clear Disable + 26 + 1 + read-write + + + ADC_COCO_CLEAR_DISABLE_0 + Allow TSC hardware generates ADC COCO clear + 0 + + + ADC_COCO_CLEAR_DISABLE_1 + Prevent TSC from generate ADC COCO clear signal + 0x1 + + + + + DEBUG_EN + Debug Enable + 28 + 1 + read-write + + + DEBUG_EN_0 + Enable debug mode + 0 + + + DEBUG_EN_1 + Disable debug mode + 0x1 + + + + + + + DEBUG_MODE2 + no description available + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + XPUL_PULL_DOWN + XPUL Wire Pull Down Switch + 0 + 1 + read-write + + + XPUL_PULL_DOWN_0 + Close the switch + 0 + + + XPUL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XPUL_PULL_UP + XPUL Wire Pull Up Switch + 1 + 1 + read-write + + + XPUL_PULL_UP_0 + Close the switch + 0 + + + XPUL_PULL_UP_1 + Open up the switch + 0x1 + + + + + XPUL_200K_PULL_UP + XPUL Wire 200K Pull Up Switch + 2 + 1 + read-write + + + XPUL_200K_PULL_UP_0 + Close the switch + 0 + + + XPUL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_DOWN + XNUR Wire Pull Down Switch + 3 + 1 + read-write + + + XNUR_PULL_DOWN_0 + Close the switch + 0 + + + XNUR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_UP + XNUR Wire Pull Up Switch + 4 + 1 + read-write + + + XNUR_PULL_UP_0 + Close the switch + 0 + + + XNUR_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_200K_PULL_UP + XNUR Wire 200K Pull Up Switch + 5 + 1 + read-write + + + XNUR_200K_PULL_UP_0 + Close the switch + 0 + + + XNUR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_DOWN + YPLL Wire Pull Down Switch + 6 + 1 + read-write + + + YPLL_PULL_DOWN_0 + Close the switch + 0 + + + YPLL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_UP + YPLL Wire Pull Up Switch + 7 + 1 + read-write + + + YPLL_PULL_UP_0 + Close the switch + 0 + + + YPLL_PULL_UP_1 + Open the switch + 0x1 + + + + + YPLL_200K_PULL_UP + YPLL Wire 200K Pull Up Switch + 8 + 1 + read-write + + + YPLL_200K_PULL_UP_0 + Close the switch + 0 + + + YPLL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_DOWN + YNLR Wire Pull Down Switch + 9 + 1 + read-write + + + YNLR_PULL_DOWN_0 + Close the switch + 0 + + + YNLR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_UP + YNLR Wire Pull Up Switch + 10 + 1 + read-write + + + YNLR_PULL_UP_0 + Close the switch + 0 + + + YNLR_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_200K_PULL_UP + YNLR Wire 200K Pull Up Switch + 11 + 1 + read-write + + + YNLR_200K_PULL_UP_0 + Close the switch + 0 + + + YNLR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_DOWN + Wiper Wire Pull Down Switch + 12 + 1 + read-write + + + WIPER_PULL_DOWN_0 + Close the switch + 0 + + + WIPER_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_UP + Wiper Wire Pull Up Switch + 13 + 1 + read-write + + + WIPER_PULL_UP_0 + Close the switch + 0 + + + WIPER_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_200K_PULL_UP + Wiper Wire 200K Pull Up Switch + 14 + 1 + read-write + + + WIPER_200K_PULL_UP_0 + Close the switch + 0 + + + WIPER_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + DETECT_FOUR_WIRE + Detect Four Wire + 16 + 1 + read-only + + + DETECT_FOUR_WIRE_0 + No detect signal + 0 + + + DETECT_FOUR_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + DETECT_FIVE_WIRE + Detect Five Wire + 17 + 1 + read-only + + + DETECT_FIVE_WIRE_0 + No detect signal + 0 + + + DETECT_FIVE_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + STATE_MACHINE + State Machine + 20 + 3 + read-only + + + STATE_MACHINE_0 + Idle + 0 + + + STATE_MACHINE_1 + Pre-charge + 0x1 + + + STATE_MACHINE_2 + Detect + 0x2 + + + STATE_MACHINE_3 + X-measure + 0x3 + + + STATE_MACHINE_4 + Y-measure + 0x4 + + + STATE_MACHINE_5 + Pre-charge + 0x5 + + + STATE_MACHINE_6 + Detect + 0x6 + + + + + INTERMEDIATE + Intermediate State + 23 + 1 + read-only + + + INTERMEDIATE_0 + Not in intermedia + 0 + + + INTERMEDIATE_1 + Intermedia + 0x1 + + + + + DETECT_ENABLE_FOUR_WIRE + Detect Enable Four Wire + 24 + 1 + read-write + + + DETECT_ENABLE_FOUR_WIRE_0 + Do not read four wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FOUR_WIRE_1 + Read four wire detect status from analogue + 0x1 + + + + + DETECT_ENABLE_FIVE_WIRE + Detect Enable Five Wire + 28 + 1 + read-write + + + DETECT_ENABLE_FIVE_WIRE_0 + Do not read five wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FIVE_WIRE_1 + Read five wire detect status from analogue + 0x1 + + + + + DE_GLITCH + This field indicates glitch threshold + 29 + 2 + read-only + + + DE_GLITCH_0 + Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + 0 + + + DE_GLITCH_1 + Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + 0x1 + + + DE_GLITCH_2 + Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + 0x2 + + + DE_GLITCH_3 + Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + 0x3 + + + + + + + + + DMA0 + DMA + DMA + 0x400E8000 + + 0 + 0x1400 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + + CR + Control Register + 0 + 32 + read-write + 0x400 + 0x80FFFFFF + + + EDBG + Enable Debug + 1 + 1 + read-write + + + EDBG_0 + no description available + 0 + + + EDBG_1 + no description available + 0x1 + + + + + ERCA + Enable Round Robin Channel Arbitration + 2 + 1 + read-write + + + ERCA_0 + no description available + 0 + + + ERCA_1 + no description available + 0x1 + + + + + ERGA + Enable Round Robin Group Arbitration + 3 + 1 + read-write + + + ERGA_0 + Fixed priority arbitration is used for selection among the groups. + 0 + + + ERGA_1 + Round robin arbitration is used for selection among the groups. + 0x1 + + + + + HOE + Halt On Error + 4 + 1 + read-write + + + HOE_0 + Normal operation + 0 + + + HOE_1 + Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + 0x1 + + + + + HALT + Halt DMA Operations + 5 + 1 + read-write + + + HALT_0 + Normal operation + 0 + + + HALT_1 + Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + 0x1 + + + + + CLM + Continuous Link Mode + 6 + 1 + read-write + + + CLM_0 + A minor loop channel link made to itself goes through channel arbitration before being activated again. + 0 + + + CLM_1 + A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + 0x1 + + + + + EMLM + Enable Minor Loop Mapping + 7 + 1 + read-write + + + EMLM_0 + Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + 0 + + + EMLM_1 + Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + 0x1 + + + + + GRP0PRI + Channel Group 0 Priority + 8 + 1 + read-write + + + GRP1PRI + Channel Group 1 Priority + 10 + 1 + read-write + + + ECX + Error Cancel Transfer + 16 + 1 + read-write + + + ECX_0 + Normal operation + 0 + + + ECX_1 + Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + 0x1 + + + + + CX + Cancel Transfer + 17 + 1 + read-write + + + CX_0 + Normal operation + 0 + + + CX_1 + Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + 0x1 + + + + + ACTIVE + DMA Active Status + 31 + 1 + read-only + + + ACTIVE_0 + eDMA is idle. + 0 + + + ACTIVE_1 + eDMA is executing a channel. + 0x1 + + + + + + + ES + Error Status Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + DBE_0 + No destination bus error + 0 + + + DBE_1 + The last recorded error was a bus error on a destination write + 0x1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + SBE_0 + No source bus error + 0 + + + SBE_1 + The last recorded error was a bus error on a source read + 0x1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + SGE_0 + No scatter/gather configuration error + 0 + + + SGE_1 + The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + 0x1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + NCE_0 + No NBYTES/CITER configuration error + 0 + + + NCE_1 + no description available + 0x1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + DOE_0 + No destination offset configuration error + 0 + + + DOE_1 + The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + DAE_0 + No destination address configuration error + 0 + + + DAE_1 + The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + SOE_0 + No source offset configuration error + 0 + + + SOE_1 + The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + SAE_0 + No source address configuration error. + 0 + + + SAE_1 + The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + ERRCHN + Error Channel Number or Canceled Channel Number + 8 + 5 + read-only + + + CPE + Channel Priority Error + 14 + 1 + read-only + + + CPE_0 + No channel priority error + 0 + + + CPE_1 + no description available + 0x1 + + + + + GPE + Group Priority Error + 15 + 1 + read-only + + + GPE_0 + No group priority error + 0 + + + GPE_1 + The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + 0x1 + + + + + ECX + Transfer Canceled + 16 + 1 + read-only + + + ECX_0 + No canceled transfers + 0 + + + ECX_1 + The last recorded entry was a canceled transfer by the error cancel transfer input + 0x1 + + + + + VLD + VLD + 31 + 1 + read-only + + + VLD_0 + No ERR bits are set. + 0 + + + VLD_1 + At least one ERR bit is set indicating a valid error exists that has not been cleared. + 0x1 + + + + + + + ERQ + Enable Request Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERQ0 + Enable DMA Request 0 + 0 + 1 + read-write + + + ERQ0_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ0_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ1 + Enable DMA Request 1 + 1 + 1 + read-write + + + ERQ1_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ1_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ2 + Enable DMA Request 2 + 2 + 1 + read-write + + + ERQ2_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ2_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ3 + Enable DMA Request 3 + 3 + 1 + read-write + + + ERQ3_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ3_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ4 + Enable DMA Request 4 + 4 + 1 + read-write + + + ERQ4_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ4_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ5 + Enable DMA Request 5 + 5 + 1 + read-write + + + ERQ5_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ5_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ6 + Enable DMA Request 6 + 6 + 1 + read-write + + + ERQ6_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ6_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ7 + Enable DMA Request 7 + 7 + 1 + read-write + + + ERQ7_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ7_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ8 + Enable DMA Request 8 + 8 + 1 + read-write + + + ERQ8_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ8_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ9 + Enable DMA Request 9 + 9 + 1 + read-write + + + ERQ9_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ9_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ10 + Enable DMA Request 10 + 10 + 1 + read-write + + + ERQ10_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ10_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ11 + Enable DMA Request 11 + 11 + 1 + read-write + + + ERQ11_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ11_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ12 + Enable DMA Request 12 + 12 + 1 + read-write + + + ERQ12_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ12_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ13 + Enable DMA Request 13 + 13 + 1 + read-write + + + ERQ13_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ13_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ14 + Enable DMA Request 14 + 14 + 1 + read-write + + + ERQ14_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ14_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ15 + Enable DMA Request 15 + 15 + 1 + read-write + + + ERQ15_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ15_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ16 + Enable DMA Request 16 + 16 + 1 + read-write + + + ERQ16_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ16_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ17 + Enable DMA Request 17 + 17 + 1 + read-write + + + ERQ17_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ17_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ18 + Enable DMA Request 18 + 18 + 1 + read-write + + + ERQ18_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ18_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ19 + Enable DMA Request 19 + 19 + 1 + read-write + + + ERQ19_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ19_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ20 + Enable DMA Request 20 + 20 + 1 + read-write + + + ERQ20_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ20_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ21 + Enable DMA Request 21 + 21 + 1 + read-write + + + ERQ21_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ21_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ22 + Enable DMA Request 22 + 22 + 1 + read-write + + + ERQ22_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ22_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ23 + Enable DMA Request 23 + 23 + 1 + read-write + + + ERQ23_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ23_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ24 + Enable DMA Request 24 + 24 + 1 + read-write + + + ERQ24_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ24_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ25 + Enable DMA Request 25 + 25 + 1 + read-write + + + ERQ25_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ25_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ26 + Enable DMA Request 26 + 26 + 1 + read-write + + + ERQ26_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ26_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ27 + Enable DMA Request 27 + 27 + 1 + read-write + + + ERQ27_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ27_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ28 + Enable DMA Request 28 + 28 + 1 + read-write + + + ERQ28_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ28_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ29 + Enable DMA Request 29 + 29 + 1 + read-write + + + ERQ29_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ29_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ30 + Enable DMA Request 30 + 30 + 1 + read-write + + + ERQ30_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ30_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ31 + Enable DMA Request 31 + 31 + 1 + read-write + + + ERQ31_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ31_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + + + EEI + Enable Error Interrupt Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + EEI0 + Enable Error Interrupt 0 + 0 + 1 + read-write + + + EEI0_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI0_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI1 + Enable Error Interrupt 1 + 1 + 1 + read-write + + + EEI1_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI1_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI2 + Enable Error Interrupt 2 + 2 + 1 + read-write + + + EEI2_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI2_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI3 + Enable Error Interrupt 3 + 3 + 1 + read-write + + + EEI3_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI3_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI4 + Enable Error Interrupt 4 + 4 + 1 + read-write + + + EEI4_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI4_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI5 + Enable Error Interrupt 5 + 5 + 1 + read-write + + + EEI5_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI5_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI6 + Enable Error Interrupt 6 + 6 + 1 + read-write + + + EEI6_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI6_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI7 + Enable Error Interrupt 7 + 7 + 1 + read-write + + + EEI7_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI7_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI8 + Enable Error Interrupt 8 + 8 + 1 + read-write + + + EEI8_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI8_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI9 + Enable Error Interrupt 9 + 9 + 1 + read-write + + + EEI9_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI9_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI10 + Enable Error Interrupt 10 + 10 + 1 + read-write + + + EEI10_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI10_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI11 + Enable Error Interrupt 11 + 11 + 1 + read-write + + + EEI11_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI11_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI12 + Enable Error Interrupt 12 + 12 + 1 + read-write + + + EEI12_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI12_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI13 + Enable Error Interrupt 13 + 13 + 1 + read-write + + + EEI13_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI13_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI14 + Enable Error Interrupt 14 + 14 + 1 + read-write + + + EEI14_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI14_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI15 + Enable Error Interrupt 15 + 15 + 1 + read-write + + + EEI15_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI15_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI16 + Enable Error Interrupt 16 + 16 + 1 + read-write + + + EEI16_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI16_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI17 + Enable Error Interrupt 17 + 17 + 1 + read-write + + + EEI17_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI17_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI18 + Enable Error Interrupt 18 + 18 + 1 + read-write + + + EEI18_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI18_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI19 + Enable Error Interrupt 19 + 19 + 1 + read-write + + + EEI19_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI19_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI20 + Enable Error Interrupt 20 + 20 + 1 + read-write + + + EEI20_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI20_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI21 + Enable Error Interrupt 21 + 21 + 1 + read-write + + + EEI21_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI21_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI22 + Enable Error Interrupt 22 + 22 + 1 + read-write + + + EEI22_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI22_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI23 + Enable Error Interrupt 23 + 23 + 1 + read-write + + + EEI23_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI23_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI24 + Enable Error Interrupt 24 + 24 + 1 + read-write + + + EEI24_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI24_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI25 + Enable Error Interrupt 25 + 25 + 1 + read-write + + + EEI25_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI25_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI26 + Enable Error Interrupt 26 + 26 + 1 + read-write + + + EEI26_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI26_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI27 + Enable Error Interrupt 27 + 27 + 1 + read-write + + + EEI27_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI27_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI28 + Enable Error Interrupt 28 + 28 + 1 + read-write + + + EEI28_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI28_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI29 + Enable Error Interrupt 29 + 29 + 1 + read-write + + + EEI29_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI29_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI30 + Enable Error Interrupt 30 + 30 + 1 + read-write + + + EEI30_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI30_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI31 + Enable Error Interrupt 31 + 31 + 1 + read-write + + + EEI31_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI31_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + + + CEEI + Clear Enable Error Interrupt Register + 0x18 + 8 + write-only + 0 + 0xFF + + + CEEI + Clear Enable Error Interrupt + 0 + 5 + write-only + + + CAEE + Clear All Enable Error Interrupts + 6 + 1 + write-only + + + CAEE_0 + no description available + 0 + + + CAEE_1 + no description available + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SEEI + Set Enable Error Interrupt Register + 0x19 + 8 + write-only + 0 + 0xFF + + + SEEI + Set Enable Error Interrupt + 0 + 5 + write-only + + + SAEE + Sets All Enable Error Interrupts + 6 + 1 + write-only + + + SAEE_0 + no description available + 0 + + + SAEE_1 + no description available + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CERQ + Clear Enable Request Register + 0x1A + 8 + write-only + 0 + 0xFF + + + CERQ + Clear Enable Request + 0 + 5 + write-only + + + CAER + Clear All Enable Requests + 6 + 1 + write-only + + + CAER_0 + no description available + 0 + + + CAER_1 + no description available + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SERQ + Set Enable Request Register + 0x1B + 8 + write-only + 0 + 0xFF + + + SERQ + Set Enable Request + 0 + 5 + write-only + + + SAER + Set All Enable Requests + 6 + 1 + write-only + + + SAER_0 + no description available + 0 + + + SAER_1 + no description available + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CDNE + Clear DONE Status Bit Register + 0x1C + 8 + write-only + 0 + 0xFF + + + CDNE + Clear DONE Bit + 0 + 5 + write-only + + + CADN + Clears All DONE Bits + 6 + 1 + write-only + + + CADN_0 + Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + 0 + + + CADN_1 + Clears all bits in TCDn_CSR[DONE] + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SSRT + Set START Bit Register + 0x1D + 8 + write-only + 0 + 0xFF + + + SSRT + Set START Bit + 0 + 5 + write-only + + + SAST + Set All START Bits (activates all channels) + 6 + 1 + write-only + + + SAST_0 + Set only the TCDn_CSR[START] bit specified in the SSRT field + 0 + + + SAST_1 + Set all bits in TCDn_CSR[START] + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CERR + Clear Error Register + 0x1E + 8 + write-only + 0 + 0xFF + + + CERR + Clear Error Indicator + 0 + 5 + write-only + + + CAEI + Clear All Error Indicators + 6 + 1 + write-only + + + CAEI_0 + no description available + 0 + + + CAEI_1 + no description available + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CINT + Clear Interrupt Request Register + 0x1F + 8 + write-only + 0 + 0xFF + + + CINT + Clear Interrupt Request + 0 + 5 + write-only + + + CAIR + Clear All Interrupt Requests + 6 + 1 + write-only + + + CAIR_0 + no description available + 0 + + + CAIR_1 + no description available + 0x1 + + + + + NOP + No Op enable + 7 + 1 + write-only + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + INT + Interrupt Request Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT0 + Interrupt Request 0 + 0 + 1 + read-write + oneToClear + + + INT0_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT0_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT1 + Interrupt Request 1 + 1 + 1 + read-write + oneToClear + + + INT1_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT1_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT2 + Interrupt Request 2 + 2 + 1 + read-write + oneToClear + + + INT2_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT2_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT3 + Interrupt Request 3 + 3 + 1 + read-write + oneToClear + + + INT3_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT3_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT4 + Interrupt Request 4 + 4 + 1 + read-write + oneToClear + + + INT4_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT4_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT5 + Interrupt Request 5 + 5 + 1 + read-write + oneToClear + + + INT5_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT5_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT6 + Interrupt Request 6 + 6 + 1 + read-write + oneToClear + + + INT6_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT6_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT7 + Interrupt Request 7 + 7 + 1 + read-write + oneToClear + + + INT7_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT7_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT8 + Interrupt Request 8 + 8 + 1 + read-write + oneToClear + + + INT8_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT8_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT9 + Interrupt Request 9 + 9 + 1 + read-write + oneToClear + + + INT9_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT9_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT10 + Interrupt Request 10 + 10 + 1 + read-write + oneToClear + + + INT10_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT10_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT11 + Interrupt Request 11 + 11 + 1 + read-write + oneToClear + + + INT11_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT11_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT12 + Interrupt Request 12 + 12 + 1 + read-write + oneToClear + + + INT12_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT12_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT13 + Interrupt Request 13 + 13 + 1 + read-write + oneToClear + + + INT13_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT13_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT14 + Interrupt Request 14 + 14 + 1 + read-write + oneToClear + + + INT14_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT14_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT15 + Interrupt Request 15 + 15 + 1 + read-write + oneToClear + + + INT15_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT15_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT16 + Interrupt Request 16 + 16 + 1 + read-write + oneToClear + + + INT16_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT16_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT17 + Interrupt Request 17 + 17 + 1 + read-write + oneToClear + + + INT17_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT17_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT18 + Interrupt Request 18 + 18 + 1 + read-write + oneToClear + + + INT18_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT18_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT19 + Interrupt Request 19 + 19 + 1 + read-write + oneToClear + + + INT19_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT19_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT20 + Interrupt Request 20 + 20 + 1 + read-write + oneToClear + + + INT20_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT20_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT21 + Interrupt Request 21 + 21 + 1 + read-write + oneToClear + + + INT21_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT21_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT22 + Interrupt Request 22 + 22 + 1 + read-write + oneToClear + + + INT22_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT22_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT23 + Interrupt Request 23 + 23 + 1 + read-write + oneToClear + + + INT23_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT23_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT24 + Interrupt Request 24 + 24 + 1 + read-write + oneToClear + + + INT24_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT24_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT25 + Interrupt Request 25 + 25 + 1 + read-write + oneToClear + + + INT25_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT25_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT26 + Interrupt Request 26 + 26 + 1 + read-write + oneToClear + + + INT26_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT26_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT27 + Interrupt Request 27 + 27 + 1 + read-write + oneToClear + + + INT27_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT27_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT28 + Interrupt Request 28 + 28 + 1 + read-write + oneToClear + + + INT28_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT28_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT29 + Interrupt Request 29 + 29 + 1 + read-write + oneToClear + + + INT29_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT29_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT30 + Interrupt Request 30 + 30 + 1 + read-write + oneToClear + + + INT30_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT30_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT31 + Interrupt Request 31 + 31 + 1 + read-write + oneToClear + + + INT31_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT31_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + + + ERR + Error Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR0 + Error In Channel 0 + 0 + 1 + read-write + oneToClear + + + ERR0_0 + An error in this channel has not occurred + 0 + + + ERR0_1 + An error in this channel has occurred + 0x1 + + + + + ERR1 + Error In Channel 1 + 1 + 1 + read-write + oneToClear + + + ERR1_0 + An error in this channel has not occurred + 0 + + + ERR1_1 + An error in this channel has occurred + 0x1 + + + + + ERR2 + Error In Channel 2 + 2 + 1 + read-write + oneToClear + + + ERR2_0 + An error in this channel has not occurred + 0 + + + ERR2_1 + An error in this channel has occurred + 0x1 + + + + + ERR3 + Error In Channel 3 + 3 + 1 + read-write + oneToClear + + + ERR3_0 + An error in this channel has not occurred + 0 + + + ERR3_1 + An error in this channel has occurred + 0x1 + + + + + ERR4 + Error In Channel 4 + 4 + 1 + read-write + oneToClear + + + ERR4_0 + An error in this channel has not occurred + 0 + + + ERR4_1 + An error in this channel has occurred + 0x1 + + + + + ERR5 + Error In Channel 5 + 5 + 1 + read-write + oneToClear + + + ERR5_0 + An error in this channel has not occurred + 0 + + + ERR5_1 + An error in this channel has occurred + 0x1 + + + + + ERR6 + Error In Channel 6 + 6 + 1 + read-write + oneToClear + + + ERR6_0 + An error in this channel has not occurred + 0 + + + ERR6_1 + An error in this channel has occurred + 0x1 + + + + + ERR7 + Error In Channel 7 + 7 + 1 + read-write + oneToClear + + + ERR7_0 + An error in this channel has not occurred + 0 + + + ERR7_1 + An error in this channel has occurred + 0x1 + + + + + ERR8 + Error In Channel 8 + 8 + 1 + read-write + oneToClear + + + ERR8_0 + An error in this channel has not occurred + 0 + + + ERR8_1 + An error in this channel has occurred + 0x1 + + + + + ERR9 + Error In Channel 9 + 9 + 1 + read-write + oneToClear + + + ERR9_0 + An error in this channel has not occurred + 0 + + + ERR9_1 + An error in this channel has occurred + 0x1 + + + + + ERR10 + Error In Channel 10 + 10 + 1 + read-write + oneToClear + + + ERR10_0 + An error in this channel has not occurred + 0 + + + ERR10_1 + An error in this channel has occurred + 0x1 + + + + + ERR11 + Error In Channel 11 + 11 + 1 + read-write + oneToClear + + + ERR11_0 + An error in this channel has not occurred + 0 + + + ERR11_1 + An error in this channel has occurred + 0x1 + + + + + ERR12 + Error In Channel 12 + 12 + 1 + read-write + oneToClear + + + ERR12_0 + An error in this channel has not occurred + 0 + + + ERR12_1 + An error in this channel has occurred + 0x1 + + + + + ERR13 + Error In Channel 13 + 13 + 1 + read-write + oneToClear + + + ERR13_0 + An error in this channel has not occurred + 0 + + + ERR13_1 + An error in this channel has occurred + 0x1 + + + + + ERR14 + Error In Channel 14 + 14 + 1 + read-write + oneToClear + + + ERR14_0 + An error in this channel has not occurred + 0 + + + ERR14_1 + An error in this channel has occurred + 0x1 + + + + + ERR15 + Error In Channel 15 + 15 + 1 + read-write + oneToClear + + + ERR15_0 + An error in this channel has not occurred + 0 + + + ERR15_1 + An error in this channel has occurred + 0x1 + + + + + ERR16 + Error In Channel 16 + 16 + 1 + read-write + oneToClear + + + ERR16_0 + An error in this channel has not occurred + 0 + + + ERR16_1 + An error in this channel has occurred + 0x1 + + + + + ERR17 + Error In Channel 17 + 17 + 1 + read-write + oneToClear + + + ERR17_0 + An error in this channel has not occurred + 0 + + + ERR17_1 + An error in this channel has occurred + 0x1 + + + + + ERR18 + Error In Channel 18 + 18 + 1 + read-write + oneToClear + + + ERR18_0 + An error in this channel has not occurred + 0 + + + ERR18_1 + An error in this channel has occurred + 0x1 + + + + + ERR19 + Error In Channel 19 + 19 + 1 + read-write + oneToClear + + + ERR19_0 + An error in this channel has not occurred + 0 + + + ERR19_1 + An error in this channel has occurred + 0x1 + + + + + ERR20 + Error In Channel 20 + 20 + 1 + read-write + oneToClear + + + ERR20_0 + An error in this channel has not occurred + 0 + + + ERR20_1 + An error in this channel has occurred + 0x1 + + + + + ERR21 + Error In Channel 21 + 21 + 1 + read-write + oneToClear + + + ERR21_0 + An error in this channel has not occurred + 0 + + + ERR21_1 + An error in this channel has occurred + 0x1 + + + + + ERR22 + Error In Channel 22 + 22 + 1 + read-write + oneToClear + + + ERR22_0 + An error in this channel has not occurred + 0 + + + ERR22_1 + An error in this channel has occurred + 0x1 + + + + + ERR23 + Error In Channel 23 + 23 + 1 + read-write + oneToClear + + + ERR23_0 + An error in this channel has not occurred + 0 + + + ERR23_1 + An error in this channel has occurred + 0x1 + + + + + ERR24 + Error In Channel 24 + 24 + 1 + read-write + oneToClear + + + ERR24_0 + An error in this channel has not occurred + 0 + + + ERR24_1 + An error in this channel has occurred + 0x1 + + + + + ERR25 + Error In Channel 25 + 25 + 1 + read-write + oneToClear + + + ERR25_0 + An error in this channel has not occurred + 0 + + + ERR25_1 + An error in this channel has occurred + 0x1 + + + + + ERR26 + Error In Channel 26 + 26 + 1 + read-write + oneToClear + + + ERR26_0 + An error in this channel has not occurred + 0 + + + ERR26_1 + An error in this channel has occurred + 0x1 + + + + + ERR27 + Error In Channel 27 + 27 + 1 + read-write + oneToClear + + + ERR27_0 + An error in this channel has not occurred + 0 + + + ERR27_1 + An error in this channel has occurred + 0x1 + + + + + ERR28 + Error In Channel 28 + 28 + 1 + read-write + oneToClear + + + ERR28_0 + An error in this channel has not occurred + 0 + + + ERR28_1 + An error in this channel has occurred + 0x1 + + + + + ERR29 + Error In Channel 29 + 29 + 1 + read-write + oneToClear + + + ERR29_0 + An error in this channel has not occurred + 0 + + + ERR29_1 + An error in this channel has occurred + 0x1 + + + + + ERR30 + Error In Channel 30 + 30 + 1 + read-write + oneToClear + + + ERR30_0 + An error in this channel has not occurred + 0 + + + ERR30_1 + An error in this channel has occurred + 0x1 + + + + + ERR31 + Error In Channel 31 + 31 + 1 + read-write + oneToClear + + + ERR31_0 + An error in this channel has not occurred + 0 + + + ERR31_1 + An error in this channel has occurred + 0x1 + + + + + + + HRS + Hardware Request Status Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + HRS0 + Hardware Request Status Channel 0 + 0 + 1 + read-only + + + HRS0_0 + A hardware service request for channel 0 is not present + 0 + + + HRS0_1 + A hardware service request for channel 0 is present + 0x1 + + + + + HRS1 + Hardware Request Status Channel 1 + 1 + 1 + read-only + + + HRS1_0 + A hardware service request for channel 1 is not present + 0 + + + HRS1_1 + A hardware service request for channel 1 is present + 0x1 + + + + + HRS2 + Hardware Request Status Channel 2 + 2 + 1 + read-only + + + HRS2_0 + A hardware service request for channel 2 is not present + 0 + + + HRS2_1 + A hardware service request for channel 2 is present + 0x1 + + + + + HRS3 + Hardware Request Status Channel 3 + 3 + 1 + read-only + + + HRS3_0 + A hardware service request for channel 3 is not present + 0 + + + HRS3_1 + A hardware service request for channel 3 is present + 0x1 + + + + + HRS4 + Hardware Request Status Channel 4 + 4 + 1 + read-only + + + HRS4_0 + A hardware service request for channel 4 is not present + 0 + + + HRS4_1 + A hardware service request for channel 4 is present + 0x1 + + + + + HRS5 + Hardware Request Status Channel 5 + 5 + 1 + read-only + + + HRS5_0 + A hardware service request for channel 5 is not present + 0 + + + HRS5_1 + A hardware service request for channel 5 is present + 0x1 + + + + + HRS6 + Hardware Request Status Channel 6 + 6 + 1 + read-only + + + HRS6_0 + A hardware service request for channel 6 is not present + 0 + + + HRS6_1 + A hardware service request for channel 6 is present + 0x1 + + + + + HRS7 + Hardware Request Status Channel 7 + 7 + 1 + read-only + + + HRS7_0 + A hardware service request for channel 7 is not present + 0 + + + HRS7_1 + A hardware service request for channel 7 is present + 0x1 + + + + + HRS8 + Hardware Request Status Channel 8 + 8 + 1 + read-only + + + HRS8_0 + A hardware service request for channel 8 is not present + 0 + + + HRS8_1 + A hardware service request for channel 8 is present + 0x1 + + + + + HRS9 + Hardware Request Status Channel 9 + 9 + 1 + read-only + + + HRS9_0 + A hardware service request for channel 9 is not present + 0 + + + HRS9_1 + A hardware service request for channel 9 is present + 0x1 + + + + + HRS10 + Hardware Request Status Channel 10 + 10 + 1 + read-only + + + HRS10_0 + A hardware service request for channel 10 is not present + 0 + + + HRS10_1 + A hardware service request for channel 10 is present + 0x1 + + + + + HRS11 + Hardware Request Status Channel 11 + 11 + 1 + read-only + + + HRS11_0 + A hardware service request for channel 11 is not present + 0 + + + HRS11_1 + A hardware service request for channel 11 is present + 0x1 + + + + + HRS12 + Hardware Request Status Channel 12 + 12 + 1 + read-only + + + HRS12_0 + A hardware service request for channel 12 is not present + 0 + + + HRS12_1 + A hardware service request for channel 12 is present + 0x1 + + + + + HRS13 + Hardware Request Status Channel 13 + 13 + 1 + read-only + + + HRS13_0 + A hardware service request for channel 13 is not present + 0 + + + HRS13_1 + A hardware service request for channel 13 is present + 0x1 + + + + + HRS14 + Hardware Request Status Channel 14 + 14 + 1 + read-only + + + HRS14_0 + A hardware service request for channel 14 is not present + 0 + + + HRS14_1 + A hardware service request for channel 14 is present + 0x1 + + + + + HRS15 + Hardware Request Status Channel 15 + 15 + 1 + read-only + + + HRS15_0 + A hardware service request for channel 15 is not present + 0 + + + HRS15_1 + A hardware service request for channel 15 is present + 0x1 + + + + + HRS16 + Hardware Request Status Channel 16 + 16 + 1 + read-only + + + HRS16_0 + A hardware service request for channel 16 is not present + 0 + + + HRS16_1 + A hardware service request for channel 16 is present + 0x1 + + + + + HRS17 + Hardware Request Status Channel 17 + 17 + 1 + read-only + + + HRS17_0 + A hardware service request for channel 17 is not present + 0 + + + HRS17_1 + A hardware service request for channel 17 is present + 0x1 + + + + + HRS18 + Hardware Request Status Channel 18 + 18 + 1 + read-only + + + HRS18_0 + A hardware service request for channel 18 is not present + 0 + + + HRS18_1 + A hardware service request for channel 18 is present + 0x1 + + + + + HRS19 + Hardware Request Status Channel 19 + 19 + 1 + read-only + + + HRS19_0 + A hardware service request for channel 19 is not present + 0 + + + HRS19_1 + A hardware service request for channel 19 is present + 0x1 + + + + + HRS20 + Hardware Request Status Channel 20 + 20 + 1 + read-only + + + HRS20_0 + A hardware service request for channel 20 is not present + 0 + + + HRS20_1 + A hardware service request for channel 20 is present + 0x1 + + + + + HRS21 + Hardware Request Status Channel 21 + 21 + 1 + read-only + + + HRS21_0 + A hardware service request for channel 21 is not present + 0 + + + HRS21_1 + A hardware service request for channel 21 is present + 0x1 + + + + + HRS22 + Hardware Request Status Channel 22 + 22 + 1 + read-only + + + HRS22_0 + A hardware service request for channel 22 is not present + 0 + + + HRS22_1 + A hardware service request for channel 22 is present + 0x1 + + + + + HRS23 + Hardware Request Status Channel 23 + 23 + 1 + read-only + + + HRS23_0 + A hardware service request for channel 23 is not present + 0 + + + HRS23_1 + A hardware service request for channel 23 is present + 0x1 + + + + + HRS24 + Hardware Request Status Channel 24 + 24 + 1 + read-only + + + HRS24_0 + A hardware service request for channel 24 is not present + 0 + + + HRS24_1 + A hardware service request for channel 24 is present + 0x1 + + + + + HRS25 + Hardware Request Status Channel 25 + 25 + 1 + read-only + + + HRS25_0 + A hardware service request for channel 25 is not present + 0 + + + HRS25_1 + A hardware service request for channel 25 is present + 0x1 + + + + + HRS26 + Hardware Request Status Channel 26 + 26 + 1 + read-only + + + HRS26_0 + A hardware service request for channel 26 is not present + 0 + + + HRS26_1 + A hardware service request for channel 26 is present + 0x1 + + + + + HRS27 + Hardware Request Status Channel 27 + 27 + 1 + read-only + + + HRS27_0 + A hardware service request for channel 27 is not present + 0 + + + HRS27_1 + A hardware service request for channel 27 is present + 0x1 + + + + + HRS28 + Hardware Request Status Channel 28 + 28 + 1 + read-only + + + HRS28_0 + A hardware service request for channel 28 is not present + 0 + + + HRS28_1 + A hardware service request for channel 28 is present + 0x1 + + + + + HRS29 + Hardware Request Status Channel 29 + 29 + 1 + read-only + + + HRS29_0 + A hardware service request for channel 29 is not preset + 0 + + + HRS29_1 + A hardware service request for channel 29 is present + 0x1 + + + + + HRS30 + Hardware Request Status Channel 30 + 30 + 1 + read-only + + + HRS30_0 + A hardware service request for channel 30 is not present + 0 + + + HRS30_1 + A hardware service request for channel 30 is present + 0x1 + + + + + HRS31 + Hardware Request Status Channel 31 + 31 + 1 + read-only + + + HRS31_0 + A hardware service request for channel 31 is not present + 0 + + + HRS31_1 + A hardware service request for channel 31 is present + 0x1 + + + + + + + EARS + Enable Asynchronous Request in Stop Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDREQ_0 + Enable asynchronous DMA request in stop mode for channel 0. + 0 + 1 + read-write + + + EDREQ_0_0 + Disable asynchronous DMA request for channel 0. + 0 + + + EDREQ_0_1 + Enable asynchronous DMA request for channel 0. + 0x1 + + + + + EDREQ_1 + Enable asynchronous DMA request in stop mode for channel 1. + 1 + 1 + read-write + + + EDREQ_1_0 + Disable asynchronous DMA request for channel 1 + 0 + + + EDREQ_1_1 + Enable asynchronous DMA request for channel 1. + 0x1 + + + + + EDREQ_2 + Enable asynchronous DMA request in stop mode for channel 2. + 2 + 1 + read-write + + + EDREQ_2_0 + Disable asynchronous DMA request for channel 2. + 0 + + + EDREQ_2_1 + Enable asynchronous DMA request for channel 2. + 0x1 + + + + + EDREQ_3 + Enable asynchronous DMA request in stop mode for channel 3. + 3 + 1 + read-write + + + EDREQ_3_0 + Disable asynchronous DMA request for channel 3. + 0 + + + EDREQ_3_1 + Enable asynchronous DMA request for channel 3. + 0x1 + + + + + EDREQ_4 + Enable asynchronous DMA request in stop mode for channel 4 + 4 + 1 + read-write + + + EDREQ_4_0 + Disable asynchronous DMA request for channel 4. + 0 + + + EDREQ_4_1 + Enable asynchronous DMA request for channel 4. + 0x1 + + + + + EDREQ_5 + Enable asynchronous DMA request in stop mode for channel 5 + 5 + 1 + read-write + + + EDREQ_5_0 + Disable asynchronous DMA request for channel 5. + 0 + + + EDREQ_5_1 + Enable asynchronous DMA request for channel 5. + 0x1 + + + + + EDREQ_6 + Enable asynchronous DMA request in stop mode for channel 6 + 6 + 1 + read-write + + + EDREQ_6_0 + Disable asynchronous DMA request for channel 6. + 0 + + + EDREQ_6_1 + Enable asynchronous DMA request for channel 6. + 0x1 + + + + + EDREQ_7 + Enable asynchronous DMA request in stop mode for channel 7 + 7 + 1 + read-write + + + EDREQ_7_0 + Disable asynchronous DMA request for channel 7. + 0 + + + EDREQ_7_1 + Enable asynchronous DMA request for channel 7. + 0x1 + + + + + EDREQ_8 + Enable asynchronous DMA request in stop mode for channel 8 + 8 + 1 + read-write + + + EDREQ_8_0 + Disable asynchronous DMA request for channel 8. + 0 + + + EDREQ_8_1 + Enable asynchronous DMA request for channel 8. + 0x1 + + + + + EDREQ_9 + Enable asynchronous DMA request in stop mode for channel 9 + 9 + 1 + read-write + + + EDREQ_9_0 + Disable asynchronous DMA request for channel 9. + 0 + + + EDREQ_9_1 + Enable asynchronous DMA request for channel 9. + 0x1 + + + + + EDREQ_10 + Enable asynchronous DMA request in stop mode for channel 10 + 10 + 1 + read-write + + + EDREQ_10_0 + Disable asynchronous DMA request for channel 10. + 0 + + + EDREQ_10_1 + Enable asynchronous DMA request for channel 10. + 0x1 + + + + + EDREQ_11 + Enable asynchronous DMA request in stop mode for channel 11 + 11 + 1 + read-write + + + EDREQ_11_0 + Disable asynchronous DMA request for channel 11. + 0 + + + EDREQ_11_1 + Enable asynchronous DMA request for channel 11. + 0x1 + + + + + EDREQ_12 + Enable asynchronous DMA request in stop mode for channel 12 + 12 + 1 + read-write + + + EDREQ_12_0 + Disable asynchronous DMA request for channel 12. + 0 + + + EDREQ_12_1 + Enable asynchronous DMA request for channel 12. + 0x1 + + + + + EDREQ_13 + Enable asynchronous DMA request in stop mode for channel 13 + 13 + 1 + read-write + + + EDREQ_13_0 + Disable asynchronous DMA request for channel 13. + 0 + + + EDREQ_13_1 + Enable asynchronous DMA request for channel 13. + 0x1 + + + + + EDREQ_14 + Enable asynchronous DMA request in stop mode for channel 14 + 14 + 1 + read-write + + + EDREQ_14_0 + Disable asynchronous DMA request for channel 14. + 0 + + + EDREQ_14_1 + Enable asynchronous DMA request for channel 14. + 0x1 + + + + + EDREQ_15 + Enable asynchronous DMA request in stop mode for channel 15 + 15 + 1 + read-write + + + EDREQ_15_0 + Disable asynchronous DMA request for channel 15. + 0 + + + EDREQ_15_1 + Enable asynchronous DMA request for channel 15. + 0x1 + + + + + EDREQ_16 + Enable asynchronous DMA request in stop mode for channel 16 + 16 + 1 + read-write + + + EDREQ_16_0 + Disable asynchronous DMA request for channel 16 + 0 + + + EDREQ_16_1 + Enable asynchronous DMA request for channel 16 + 0x1 + + + + + EDREQ_17 + Enable asynchronous DMA request in stop mode for channel 17 + 17 + 1 + read-write + + + EDREQ_17_0 + Disable asynchronous DMA request for channel 17 + 0 + + + EDREQ_17_1 + Enable asynchronous DMA request for channel 17 + 0x1 + + + + + EDREQ_18 + Enable asynchronous DMA request in stop mode for channel 18 + 18 + 1 + read-write + + + EDREQ_18_0 + Disable asynchronous DMA request for channel 18 + 0 + + + EDREQ_18_1 + Enable asynchronous DMA request for channel 18 + 0x1 + + + + + EDREQ_19 + Enable asynchronous DMA request in stop mode for channel 19 + 19 + 1 + read-write + + + EDREQ_19_0 + Disable asynchronous DMA request for channel 19 + 0 + + + EDREQ_19_1 + Enable asynchronous DMA request for channel 19 + 0x1 + + + + + EDREQ_20 + Enable asynchronous DMA request in stop mode for channel 20 + 20 + 1 + read-write + + + EDREQ_20_0 + Disable asynchronous DMA request for channel 20 + 0 + + + EDREQ_20_1 + Enable asynchronous DMA request for channel 20 + 0x1 + + + + + EDREQ_21 + Enable asynchronous DMA request in stop mode for channel 21 + 21 + 1 + read-write + + + EDREQ_21_0 + Disable asynchronous DMA request for channel 21 + 0 + + + EDREQ_21_1 + Enable asynchronous DMA request for channel 21 + 0x1 + + + + + EDREQ_22 + Enable asynchronous DMA request in stop mode for channel 22 + 22 + 1 + read-write + + + EDREQ_22_0 + Disable asynchronous DMA request for channel 22 + 0 + + + EDREQ_22_1 + Enable asynchronous DMA request for channel 22 + 0x1 + + + + + EDREQ_23 + Enable asynchronous DMA request in stop mode for channel 23 + 23 + 1 + read-write + + + EDREQ_23_0 + Disable asynchronous DMA request for channel 23 + 0 + + + EDREQ_23_1 + Enable asynchronous DMA request for channel 23 + 0x1 + + + + + EDREQ_24 + Enable asynchronous DMA request in stop mode for channel 24 + 24 + 1 + read-write + + + EDREQ_24_0 + Disable asynchronous DMA request for channel 24 + 0 + + + EDREQ_24_1 + Enable asynchronous DMA request for channel 24 + 0x1 + + + + + EDREQ_25 + Enable asynchronous DMA request in stop mode for channel 25 + 25 + 1 + read-write + + + EDREQ_25_0 + Disable asynchronous DMA request for channel 25 + 0 + + + EDREQ_25_1 + Enable asynchronous DMA request for channel 25 + 0x1 + + + + + EDREQ_26 + Enable asynchronous DMA request in stop mode for channel 26 + 26 + 1 + read-write + + + EDREQ_26_0 + Disable asynchronous DMA request for channel 26 + 0 + + + EDREQ_26_1 + Enable asynchronous DMA request for channel 26 + 0x1 + + + + + EDREQ_27 + Enable asynchronous DMA request in stop mode for channel 27 + 27 + 1 + read-write + + + EDREQ_27_0 + Disable asynchronous DMA request for channel 27 + 0 + + + EDREQ_27_1 + Enable asynchronous DMA request for channel 27 + 0x1 + + + + + EDREQ_28 + Enable asynchronous DMA request in stop mode for channel 28 + 28 + 1 + read-write + + + EDREQ_28_0 + Disable asynchronous DMA request for channel 28 + 0 + + + EDREQ_28_1 + Enable asynchronous DMA request for channel 28 + 0x1 + + + + + EDREQ_29 + Enable asynchronous DMA request in stop mode for channel 29 + 29 + 1 + read-write + + + EDREQ_29_0 + Disable asynchronous DMA request for channel 29 + 0 + + + EDREQ_29_1 + Enable asynchronous DMA request for channel 29 + 0x1 + + + + + EDREQ_30 + Enable asynchronous DMA request in stop mode for channel 30 + 30 + 1 + read-write + + + EDREQ_30_0 + Disable asynchronous DMA request for channel 30 + 0 + + + EDREQ_30_1 + Enable asynchronous DMA request for channel 30 + 0x1 + + + + + EDREQ_31 + Enable asynchronous DMA request in stop mode for channel 31 + 31 + 1 + read-write + + + EDREQ_31_0 + Disable asynchronous DMA request for channel 31 + 0 + + + EDREQ_31_1 + Enable asynchronous DMA request for channel 31 + 0x1 + + + + + + + DCHPRI3 + Channel n Priority Register + 0x100 + 8 + read-write + 0x3 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI2 + Channel n Priority Register + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI1 + Channel n Priority Register + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI0 + Channel n Priority Register + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI7 + Channel n Priority Register + 0x104 + 8 + read-write + 0x7 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI6 + Channel n Priority Register + 0x105 + 8 + read-write + 0x6 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI5 + Channel n Priority Register + 0x106 + 8 + read-write + 0x5 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI4 + Channel n Priority Register + 0x107 + 8 + read-write + 0x4 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI11 + Channel n Priority Register + 0x108 + 8 + read-write + 0xB + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI10 + Channel n Priority Register + 0x109 + 8 + read-write + 0xA + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI9 + Channel n Priority Register + 0x10A + 8 + read-write + 0x9 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI8 + Channel n Priority Register + 0x10B + 8 + read-write + 0x8 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI15 + Channel n Priority Register + 0x10C + 8 + read-write + 0xF + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI14 + Channel n Priority Register + 0x10D + 8 + read-write + 0xE + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI13 + Channel n Priority Register + 0x10E + 8 + read-write + 0xD + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI12 + Channel n Priority Register + 0x10F + 8 + read-write + 0xC + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI19 + Channel n Priority Register + 0x110 + 8 + read-write + 0x13 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI18 + Channel n Priority Register + 0x111 + 8 + read-write + 0x12 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI17 + Channel n Priority Register + 0x112 + 8 + read-write + 0x11 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI16 + Channel n Priority Register + 0x113 + 8 + read-write + 0x10 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI23 + Channel n Priority Register + 0x114 + 8 + read-write + 0x17 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI22 + Channel n Priority Register + 0x115 + 8 + read-write + 0x16 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI21 + Channel n Priority Register + 0x116 + 8 + read-write + 0x15 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI20 + Channel n Priority Register + 0x117 + 8 + read-write + 0x14 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI27 + Channel n Priority Register + 0x118 + 8 + read-write + 0x1B + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI26 + Channel n Priority Register + 0x119 + 8 + read-write + 0x1A + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI25 + Channel n Priority Register + 0x11A + 8 + read-write + 0x19 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI24 + Channel n Priority Register + 0x11B + 8 + read-write + 0x18 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI31 + Channel n Priority Register + 0x11C + 8 + read-write + 0x1F + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI30 + Channel n Priority Register + 0x11D + 8 + read-write + 0x1E + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI29 + Channel n Priority Register + 0x11E + 8 + read-write + 0x1D + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI28 + Channel n Priority Register + 0x11F + 8 + read-write + 0x1C + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + TCD0_SADDR + TCD Source Address + 0x1000 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD0_SOFF + TCD Signed Source Address Offset + 0x1004 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD0_ATTR + TCD Transfer Attributes + 0x1006 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD0_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD0_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_SLAST + TCD Last Source Address Adjustment + 0x100C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD0_DADDR + TCD Destination Address + 0x1010 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD0_DOFF + TCD Signed Destination Address Offset + 0x1014 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD0_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1018 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD0_CSR + TCD Control and Status + 0x101C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD0_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_SADDR + TCD Source Address + 0x1020 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD1_SOFF + TCD Signed Source Address Offset + 0x1024 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD1_ATTR + TCD Transfer Attributes + 0x1026 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD1_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD1_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_SLAST + TCD Last Source Address Adjustment + 0x102C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD1_DADDR + TCD Destination Address + 0x1030 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD1_DOFF + TCD Signed Destination Address Offset + 0x1034 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD1_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1038 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD1_CSR + TCD Control and Status + 0x103C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD1_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_SADDR + TCD Source Address + 0x1040 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD2_SOFF + TCD Signed Source Address Offset + 0x1044 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD2_ATTR + TCD Transfer Attributes + 0x1046 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD2_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD2_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_SLAST + TCD Last Source Address Adjustment + 0x104C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD2_DADDR + TCD Destination Address + 0x1050 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD2_DOFF + TCD Signed Destination Address Offset + 0x1054 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD2_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1058 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD2_CSR + TCD Control and Status + 0x105C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD2_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_SADDR + TCD Source Address + 0x1060 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD3_SOFF + TCD Signed Source Address Offset + 0x1064 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD3_ATTR + TCD Transfer Attributes + 0x1066 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD3_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD3_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_SLAST + TCD Last Source Address Adjustment + 0x106C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD3_DADDR + TCD Destination Address + 0x1070 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD3_DOFF + TCD Signed Destination Address Offset + 0x1074 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD3_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1078 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD3_CSR + TCD Control and Status + 0x107C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD3_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_SADDR + TCD Source Address + 0x1080 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD4_SOFF + TCD Signed Source Address Offset + 0x1084 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD4_ATTR + TCD Transfer Attributes + 0x1086 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD4_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD4_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_SLAST + TCD Last Source Address Adjustment + 0x108C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD4_DADDR + TCD Destination Address + 0x1090 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD4_DOFF + TCD Signed Destination Address Offset + 0x1094 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD4_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1098 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD4_CSR + TCD Control and Status + 0x109C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD4_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_SADDR + TCD Source Address + 0x10A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD5_SOFF + TCD Signed Source Address Offset + 0x10A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD5_ATTR + TCD Transfer Attributes + 0x10A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD5_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD5_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_SLAST + TCD Last Source Address Adjustment + 0x10AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD5_DADDR + TCD Destination Address + 0x10B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD5_DOFF + TCD Signed Destination Address Offset + 0x10B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD5_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD5_CSR + TCD Control and Status + 0x10BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD5_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_SADDR + TCD Source Address + 0x10C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD6_SOFF + TCD Signed Source Address Offset + 0x10C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD6_ATTR + TCD Transfer Attributes + 0x10C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD6_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD6_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_SLAST + TCD Last Source Address Adjustment + 0x10CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD6_DADDR + TCD Destination Address + 0x10D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD6_DOFF + TCD Signed Destination Address Offset + 0x10D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD6_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD6_CSR + TCD Control and Status + 0x10DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD6_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_SADDR + TCD Source Address + 0x10E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD7_SOFF + TCD Signed Source Address Offset + 0x10E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD7_ATTR + TCD Transfer Attributes + 0x10E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD7_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD7_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_SLAST + TCD Last Source Address Adjustment + 0x10EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD7_DADDR + TCD Destination Address + 0x10F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD7_DOFF + TCD Signed Destination Address Offset + 0x10F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD7_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD7_CSR + TCD Control and Status + 0x10FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD7_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_SADDR + TCD Source Address + 0x1100 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD8_SOFF + TCD Signed Source Address Offset + 0x1104 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD8_ATTR + TCD Transfer Attributes + 0x1106 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD8_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD8_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_SLAST + TCD Last Source Address Adjustment + 0x110C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD8_DADDR + TCD Destination Address + 0x1110 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD8_DOFF + TCD Signed Destination Address Offset + 0x1114 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD8_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1118 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD8_CSR + TCD Control and Status + 0x111C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD8_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_SADDR + TCD Source Address + 0x1120 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD9_SOFF + TCD Signed Source Address Offset + 0x1124 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD9_ATTR + TCD Transfer Attributes + 0x1126 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD9_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD9_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_SLAST + TCD Last Source Address Adjustment + 0x112C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD9_DADDR + TCD Destination Address + 0x1130 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD9_DOFF + TCD Signed Destination Address Offset + 0x1134 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD9_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1138 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD9_CSR + TCD Control and Status + 0x113C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD9_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_SADDR + TCD Source Address + 0x1140 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD10_SOFF + TCD Signed Source Address Offset + 0x1144 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD10_ATTR + TCD Transfer Attributes + 0x1146 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD10_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD10_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_SLAST + TCD Last Source Address Adjustment + 0x114C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD10_DADDR + TCD Destination Address + 0x1150 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD10_DOFF + TCD Signed Destination Address Offset + 0x1154 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD10_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1158 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD10_CSR + TCD Control and Status + 0x115C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD10_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_SADDR + TCD Source Address + 0x1160 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD11_SOFF + TCD Signed Source Address Offset + 0x1164 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD11_ATTR + TCD Transfer Attributes + 0x1166 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD11_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD11_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_SLAST + TCD Last Source Address Adjustment + 0x116C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD11_DADDR + TCD Destination Address + 0x1170 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD11_DOFF + TCD Signed Destination Address Offset + 0x1174 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD11_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1178 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD11_CSR + TCD Control and Status + 0x117C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD11_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_SADDR + TCD Source Address + 0x1180 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD12_SOFF + TCD Signed Source Address Offset + 0x1184 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD12_ATTR + TCD Transfer Attributes + 0x1186 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD12_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD12_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_SLAST + TCD Last Source Address Adjustment + 0x118C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD12_DADDR + TCD Destination Address + 0x1190 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD12_DOFF + TCD Signed Destination Address Offset + 0x1194 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD12_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1198 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD12_CSR + TCD Control and Status + 0x119C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD12_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_SADDR + TCD Source Address + 0x11A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD13_SOFF + TCD Signed Source Address Offset + 0x11A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD13_ATTR + TCD Transfer Attributes + 0x11A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD13_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD13_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_SLAST + TCD Last Source Address Adjustment + 0x11AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD13_DADDR + TCD Destination Address + 0x11B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD13_DOFF + TCD Signed Destination Address Offset + 0x11B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD13_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD13_CSR + TCD Control and Status + 0x11BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD13_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_SADDR + TCD Source Address + 0x11C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD14_SOFF + TCD Signed Source Address Offset + 0x11C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD14_ATTR + TCD Transfer Attributes + 0x11C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD14_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD14_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_SLAST + TCD Last Source Address Adjustment + 0x11CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD14_DADDR + TCD Destination Address + 0x11D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD14_DOFF + TCD Signed Destination Address Offset + 0x11D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD14_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD14_CSR + TCD Control and Status + 0x11DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD14_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_SADDR + TCD Source Address + 0x11E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD15_SOFF + TCD Signed Source Address Offset + 0x11E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD15_ATTR + TCD Transfer Attributes + 0x11E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD15_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD15_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_SLAST + TCD Last Source Address Adjustment + 0x11EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD15_DADDR + TCD Destination Address + 0x11F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD15_DOFF + TCD Signed Destination Address Offset + 0x11F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD15_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD15_CSR + TCD Control and Status + 0x11FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD15_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_SADDR + TCD Source Address + 0x1200 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD16_SOFF + TCD Signed Source Address Offset + 0x1204 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD16_ATTR + TCD Transfer Attributes + 0x1206 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD16_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD16_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_SLAST + TCD Last Source Address Adjustment + 0x120C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD16_DADDR + TCD Destination Address + 0x1210 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD16_DOFF + TCD Signed Destination Address Offset + 0x1214 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD16_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1218 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD16_CSR + TCD Control and Status + 0x121C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD16_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_SADDR + TCD Source Address + 0x1220 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD17_SOFF + TCD Signed Source Address Offset + 0x1224 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD17_ATTR + TCD Transfer Attributes + 0x1226 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD17_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD17_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_SLAST + TCD Last Source Address Adjustment + 0x122C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD17_DADDR + TCD Destination Address + 0x1230 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD17_DOFF + TCD Signed Destination Address Offset + 0x1234 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD17_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1238 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD17_CSR + TCD Control and Status + 0x123C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD17_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_SADDR + TCD Source Address + 0x1240 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD18_SOFF + TCD Signed Source Address Offset + 0x1244 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD18_ATTR + TCD Transfer Attributes + 0x1246 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD18_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD18_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_SLAST + TCD Last Source Address Adjustment + 0x124C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD18_DADDR + TCD Destination Address + 0x1250 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD18_DOFF + TCD Signed Destination Address Offset + 0x1254 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD18_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1258 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD18_CSR + TCD Control and Status + 0x125C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD18_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_SADDR + TCD Source Address + 0x1260 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD19_SOFF + TCD Signed Source Address Offset + 0x1264 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD19_ATTR + TCD Transfer Attributes + 0x1266 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD19_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD19_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_SLAST + TCD Last Source Address Adjustment + 0x126C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD19_DADDR + TCD Destination Address + 0x1270 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD19_DOFF + TCD Signed Destination Address Offset + 0x1274 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD19_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1278 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD19_CSR + TCD Control and Status + 0x127C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD19_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_SADDR + TCD Source Address + 0x1280 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD20_SOFF + TCD Signed Source Address Offset + 0x1284 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD20_ATTR + TCD Transfer Attributes + 0x1286 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD20_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD20_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_SLAST + TCD Last Source Address Adjustment + 0x128C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD20_DADDR + TCD Destination Address + 0x1290 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD20_DOFF + TCD Signed Destination Address Offset + 0x1294 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD20_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1298 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD20_CSR + TCD Control and Status + 0x129C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD20_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_SADDR + TCD Source Address + 0x12A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD21_SOFF + TCD Signed Source Address Offset + 0x12A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD21_ATTR + TCD Transfer Attributes + 0x12A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD21_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD21_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_SLAST + TCD Last Source Address Adjustment + 0x12AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD21_DADDR + TCD Destination Address + 0x12B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD21_DOFF + TCD Signed Destination Address Offset + 0x12B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD21_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD21_CSR + TCD Control and Status + 0x12BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD21_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_SADDR + TCD Source Address + 0x12C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD22_SOFF + TCD Signed Source Address Offset + 0x12C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD22_ATTR + TCD Transfer Attributes + 0x12C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD22_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD22_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_SLAST + TCD Last Source Address Adjustment + 0x12CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD22_DADDR + TCD Destination Address + 0x12D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD22_DOFF + TCD Signed Destination Address Offset + 0x12D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD22_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD22_CSR + TCD Control and Status + 0x12DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD22_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_SADDR + TCD Source Address + 0x12E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD23_SOFF + TCD Signed Source Address Offset + 0x12E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD23_ATTR + TCD Transfer Attributes + 0x12E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD23_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD23_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_SLAST + TCD Last Source Address Adjustment + 0x12EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD23_DADDR + TCD Destination Address + 0x12F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD23_DOFF + TCD Signed Destination Address Offset + 0x12F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD23_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD23_CSR + TCD Control and Status + 0x12FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD23_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_SADDR + TCD Source Address + 0x1300 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD24_SOFF + TCD Signed Source Address Offset + 0x1304 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD24_ATTR + TCD Transfer Attributes + 0x1306 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD24_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD24_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_SLAST + TCD Last Source Address Adjustment + 0x130C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD24_DADDR + TCD Destination Address + 0x1310 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD24_DOFF + TCD Signed Destination Address Offset + 0x1314 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD24_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1318 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD24_CSR + TCD Control and Status + 0x131C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD24_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_SADDR + TCD Source Address + 0x1320 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD25_SOFF + TCD Signed Source Address Offset + 0x1324 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD25_ATTR + TCD Transfer Attributes + 0x1326 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD25_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD25_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_SLAST + TCD Last Source Address Adjustment + 0x132C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD25_DADDR + TCD Destination Address + 0x1330 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD25_DOFF + TCD Signed Destination Address Offset + 0x1334 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD25_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1338 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD25_CSR + TCD Control and Status + 0x133C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD25_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_SADDR + TCD Source Address + 0x1340 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD26_SOFF + TCD Signed Source Address Offset + 0x1344 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD26_ATTR + TCD Transfer Attributes + 0x1346 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD26_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD26_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_SLAST + TCD Last Source Address Adjustment + 0x134C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD26_DADDR + TCD Destination Address + 0x1350 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD26_DOFF + TCD Signed Destination Address Offset + 0x1354 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD26_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1358 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD26_CSR + TCD Control and Status + 0x135C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD26_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_SADDR + TCD Source Address + 0x1360 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD27_SOFF + TCD Signed Source Address Offset + 0x1364 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD27_ATTR + TCD Transfer Attributes + 0x1366 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD27_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD27_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_SLAST + TCD Last Source Address Adjustment + 0x136C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD27_DADDR + TCD Destination Address + 0x1370 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD27_DOFF + TCD Signed Destination Address Offset + 0x1374 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD27_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1378 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD27_CSR + TCD Control and Status + 0x137C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD27_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_SADDR + TCD Source Address + 0x1380 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD28_SOFF + TCD Signed Source Address Offset + 0x1384 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD28_ATTR + TCD Transfer Attributes + 0x1386 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD28_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD28_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_SLAST + TCD Last Source Address Adjustment + 0x138C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD28_DADDR + TCD Destination Address + 0x1390 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD28_DOFF + TCD Signed Destination Address Offset + 0x1394 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD28_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1398 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD28_CSR + TCD Control and Status + 0x139C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD28_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_SADDR + TCD Source Address + 0x13A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD29_SOFF + TCD Signed Source Address Offset + 0x13A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD29_ATTR + TCD Transfer Attributes + 0x13A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD29_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD29_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_SLAST + TCD Last Source Address Adjustment + 0x13AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD29_DADDR + TCD Destination Address + 0x13B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD29_DOFF + TCD Signed Destination Address Offset + 0x13B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD29_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD29_CSR + TCD Control and Status + 0x13BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD29_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_SADDR + TCD Source Address + 0x13C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD30_SOFF + TCD Signed Source Address Offset + 0x13C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD30_ATTR + TCD Transfer Attributes + 0x13C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD30_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD30_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_SLAST + TCD Last Source Address Adjustment + 0x13CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD30_DADDR + TCD Destination Address + 0x13D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD30_DOFF + TCD Signed Destination Address Offset + 0x13D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD30_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD30_CSR + TCD Control and Status + 0x13DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD30_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_SADDR + TCD Source Address + 0x13E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD31_SOFF + TCD Signed Source Address Offset + 0x13E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD31_ATTR + TCD Transfer Attributes + 0x13E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + no description available + 0x3 + + + SSIZE_5 + no description available + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD31_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD31_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_SLAST + TCD Last Source Address Adjustment + 0x13EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD31_DADDR + TCD Destination Address + 0x13F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD31_DOFF + TCD Signed Destination Address Offset + 0x13F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD31_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD31_CSR + TCD Control and Status + 0x13FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + no description available + 0 + + + DREQ_1 + no description available + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD31_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + + + DMAMUX + DMA_CH_MUX + DMAMUX + 0x400EC000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + CHCFG[%s] + Channel 0 Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + DMA Channel Source (Slot Number) + 0 + 7 + read-write + + + A_ON + DMA Channel Always Enable + 29 + 1 + read-write + + + A_ON_0 + DMA Channel Always ON function is disabled + 0 + + + A_ON_1 + DMA Channel Always ON function is enabled + 0x1 + + + + + TRIG + DMA Channel Trigger Enable + 30 + 1 + read-write + + + TRIG_0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + 0 + + + TRIG_1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + 0x1 + + + + + ENBL + DMA Mux Channel Enable + 31 + 1 + read-write + + + ENBL_0 + DMA Mux channel is disabled + 0 + + + ENBL_1 + DMA Mux channel is enabled + 0x1 + + + + + + + + + GPC + GPC + GPC + GPC_ + 0x400F4000 + + 0 + 0x3C + registers + + + GPC + 97 + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x520000 + 0xFFFFFFFF + + + MEGA_PDN_REQ + MEGA domain power down request + 2 + 1 + read-write + + + MEGA_PDN_REQ_0 + No Request + 0 + + + MEGA_PDN_REQ_1 + Request power down sequence + 0x1 + + + + + MEGA_PUP_REQ + MEGA domain power up request + 3 + 1 + read-write + + + MEGA_PUP_REQ_0 + No Request + 0 + + + MEGA_PUP_REQ_1 + Request power up sequence + 0x1 + + + + + PDRAM0_PGE + FlexRAM PDRAM0 Power Gate Enable + 22 + 1 + read-write + + + PDRAM0_PGE_0 + FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down. + 0 + + + PDRAM0_PGE_1 + FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down. + 0x1 + + + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + IRQ[31:0] status, read only + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + IRQ[63:32] status, read only + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + IRQ[95:64] status, read only + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[127:96] status, read only + 0 + 32 + read-only + + + + + IMR5 + IRQ masking register 5 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR5 + IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR5 + IRQ status resister 5 + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[159:128] status, read only + 0 + 32 + read-only + + + + + + + PGC + PGC + GPC + PGC + PGC_ + 0x400F4000 + + 0 + 0x2B0 + registers + + + + MEGA_CTRL + PGC Mega Control Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + MEGA_PUPSCR + PGC Mega Power Up Sequence Control Register + 0x224 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 8 + 6 + read-write + + + + + MEGA_PDNSCR + PGC Mega Pull Down Sequence Control Register + 0x228 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) + 8 + 6 + read-write + + + + + MEGA_SR + PGC Mega Power Gating Controller Status Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + CPU_CTRL + PGC CPU Control Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + CPU_PUPSCR + PGC CPU Power Up Sequence Control Register + 0x2A4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + There are two different silicon revisions: 1 + 0 + 6 + read-write + + + SW2ISO + There are two different silicon revisions: 1 + 8 + 6 + read-write + + + + + CPU_PDNSCR + PGC CPU Pull Down Sequence Control Register + 0x2A8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating + 8 + 6 + read-write + + + + + CPU_SR + PGC CPU Power Gating Controller Status Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + + + SRC + SRC + SRC + SRC_ + 0x400F8000 + + 0 + 0x48 + registers + + + SRC + 98 + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0xA0480520 + 0xFFFFFFFF + + + mask_wdog_rst + Mask wdog_rst_b source + 7 + 4 + read-write + + + mask_wdog_rst_5 + wdog_rst_b is masked + 0x5 + + + mask_wdog_rst_10 + wdog_rst_b is not masked (default) + 0xA + + + + + core0_rst + Software reset for core0 only + 13 + 1 + read-write + + + core0_rst_0 + do not assert core0 reset + 0 + + + core0_rst_1 + assert core0 reset + 0x1 + + + + + core0_dbg_rst + Software reset for core0 debug only + 17 + 1 + read-write + + + core0_dbg_rst_0 + do not assert core0 debug reset + 0 + + + core0_dbg_rst_1 + assert core0 debug reset + 0x1 + + + + + dbg_rst_msk_pg + Do not assert debug resets after power gating event of core + 25 + 1 + read-write + + + dbg_rst_msk_pg_0 + do not mask core debug resets (debug resets will be asserted after power gating event) + 0 + + + dbg_rst_msk_pg_1 + mask core debug resets (debug resets won't be asserted after power gating event) + 0x1 + + + + + mask_wdog3_rst + Mask wdog3_rst_b source + 28 + 4 + read-write + + + mask_wdog3_rst_5 + wdog3_rst_b is masked + 0x5 + + + mask_wdog3_rst_10 + wdog3_rst_b is not masked + 0xA + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + Refer to fusemap. + 0 + 8 + read-only + + + BOOT_CFG2 + Refer to fusemap. + 8 + 8 + read-only + + + BOOT_CFG3 + Refer to fusemap. + 16 + 8 + read-only + + + BOOT_CFG4 + Refer to fusemap. + 24 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) + 0 + 1 + read-write + oneToClear + + + ipp_reset_b_0 + Reset is not a result of ipp_reset_b pin. + 0 + + + ipp_reset_b_1 + Reset is a result of ipp_reset_b pin. + 0x1 + + + + + lockup_sysresetreq + Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core + 1 + 1 + read-write + oneToClear + + + lockup_sysresetreq_0 + Reset is not a result of the mentioned case. + 0 + + + lockup_sysresetreq_1 + Reset is a result of the mentioned case. + 0x1 + + + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input. + 2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog_rst_b + IC Watchdog Time-out reset + 4 + 1 + read-write + oneToClear + + + wdog_rst_b_0 + Reset is not a result of the watchdog time-out event. + 0 + + + wdog_rst_b_1 + Reset is a result of the watchdog time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. + 6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of software reset from JTAG. + 0 + + + jtag_sw_rst_1 + Reset is a result of software reset from JTAG. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 8 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + DIR_BT_DIS + DIR_BT_DIS shows the state of the DIR_BT_DIS fuse + 3 + 1 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 4 + 1 + read-only + + + BMOD + BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 24 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + + + CCM + CCM + CCM + CCM_ + 0x400FC000 + + 0 + 0x8C + registers + + + CCM_1 + 95 + + + CCM_2 + 96 + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x401107F + 0xFFFFFFFF + + + OSCNT + Oscillator ready counter value + 0 + 8 + read-write + + + OSCNT_0 + count 1 ckil + 0 + + + OSCNT_255 + count 256 ckil's + 0xFF + + + + + COSC_EN + On chip oscillator enable bit - this bit value is reflected on the output cosc_en + 12 + 1 + read-write + + + COSC_EN_0 + disable on chip oscillator + 0 + + + COSC_EN_1 + enable on chip oscillator + 0x1 + + + + + REG_BYPASS_COUNT + Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ + 21 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock periods delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 27 + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled. + 0x1 + + + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + Status of the value of CCM_REF_EN_B output of ccm + 0 + 1 + read-only + + + REF_EN_B_0 + value of CCM_REF_EN_B is '0' + 0 + + + REF_EN_B_1 + value of CCM_REF_EN_B is '1' + 0x1 + + + + + CAMP2_READY + Status indication of CAMP2. + 3 + 1 + read-only + + + CAMP2_READY_0 + CAMP2 is not ready. + 0 + + + CAMP2_READY_1 + CAMP2 is ready. + 0x1 + + + + + COSC_READY + Status indication of on board oscillator + 5 + 1 + read-only + + + COSC_READY_0 + on board oscillator is not ready. + 0 + + + COSC_READY_1 + on board oscillator is ready. + 0x1 + + + + + + + CCSR + CCM Clock Switcher Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + PLL3_SW_CLK_SEL + Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. + 0 + 1 + read-write + + + PLL3_SW_CLK_SEL_0 + pll3_main_clk + 0 + + + PLL3_SW_CLK_SEL_1 + pll3 bypass clock + 0x1 + + + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ARM_PODF + Divider for ARM clock root + 0 + 3 + read-write + + + ARM_PODF_0 + divide by 1 + 0 + + + ARM_PODF_1 + divide by 2 + 0x1 + + + ARM_PODF_2 + divide by 3 + 0x2 + + + ARM_PODF_3 + divide by 4 + 0x3 + + + ARM_PODF_4 + divide by 5 + 0x4 + + + ARM_PODF_5 + divide by 6 + 0x5 + + + ARM_PODF_6 + divide by 7 + 0x6 + + + ARM_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0xA8300 + 0xFFFFFFFF + + + SEMC_CLK_SEL + SEMC clock source select + 6 + 1 + read-write + + + SEMC_CLK_SEL_0 + Periph_clk output will be used as SEMC clock root + 0 + + + SEMC_CLK_SEL_1 + SEMC alternative clock will be used as SEMC clock root + 0x1 + + + + + SEMC_ALT_CLK_SEL + SEMC alternative clock select + 7 + 1 + read-write + + + SEMC_ALT_CLK_SEL_0 + PLL2 PFD2 will be selected as alternative clock for SEMC root clock + 0 + + + SEMC_ALT_CLK_SEL_1 + PLL3 PFD1 will be selected as alternative clock for SEMC root clock + 0x1 + + + + + IPG_PODF + Divider for ipg podf. + 8 + 2 + read-write + + + IPG_PODF_0 + divide by 1 + 0 + + + IPG_PODF_1 + divide by 2 + 0x1 + + + IPG_PODF_2 + divide by 3 + 0x2 + + + IPG_PODF_3 + divide by 4 + 0x3 + + + + + AHB_PODF + Divider for AHB PODF + 10 + 3 + read-write + + + AHB_PODF_0 + divide by 1 + 0 + + + AHB_PODF_1 + divide by 2 + 0x1 + + + AHB_PODF_2 + divide by 3 + 0x2 + + + AHB_PODF_3 + divide by 4 + 0x3 + + + AHB_PODF_4 + divide by 5 + 0x4 + + + AHB_PODF_5 + divide by 6 + 0x5 + + + AHB_PODF_6 + divide by 7 + 0x6 + + + AHB_PODF_7 + divide by 8 + 0x7 + + + + + SEMC_PODF + Post divider for SEMC clock + 16 + 3 + read-write + + + SEMC_PODF_0 + divide by 1 + 0 + + + SEMC_PODF_1 + divide by 2 + 0x1 + + + SEMC_PODF_2 + divide by 3 + 0x2 + + + SEMC_PODF_3 + divide by 4 + 0x3 + + + SEMC_PODF_4 + divide by 5 + 0x4 + + + SEMC_PODF_5 + divide by 6 + 0x5 + + + SEMC_PODF_6 + divide by 7 + 0x6 + + + SEMC_PODF_7 + divide by 8 + 0x7 + + + + + PERIPH_CLK_SEL + Selector for peripheral main clock + 25 + 1 + read-write + + + PERIPH_CLK_SEL_0 + derive clock from pre_periph_clk_sel + 0 + + + PERIPH_CLK_SEL_1 + derive clock from periph_clk2_clk_divided + 0x1 + + + + + PERIPH_CLK2_PODF + Divider for periph_clk2_podf. + 27 + 3 + read-write + + + PERIPH_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x2DAE8324 + 0xFFFFFFFF + + + LPSPI_CLK_SEL + Selector for lpspi clock multiplexer + 4 + 2 + read-write + + + LPSPI_CLK_SEL_0 + derive clock from PLL3 PFD1 clk + 0 + + + LPSPI_CLK_SEL_1 + derive clock from PLL3 PFD0 + 0x1 + + + LPSPI_CLK_SEL_2 + derive clock from PLL2 + 0x2 + + + LPSPI_CLK_SEL_3 + derive clock from PLL2 PFD2 + 0x3 + + + + + PERIPH_CLK2_SEL + Selector for peripheral clk2 clock multiplexer + 12 + 2 + read-write + + + PERIPH_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH_CLK2_SEL_1 + derive clock from osc_clk (pll1_ref_clk) + 0x1 + + + PERIPH_CLK2_SEL_2 + derive clock from pll2_bypass_clk + 0x2 + + + + + TRACE_CLK_SEL + Selector for Trace clock multiplexer + 14 + 2 + read-write + + + TRACE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + TRACE_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + TRACE_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + TRACE_CLK_SEL_3 + derive clock from PLL2 PFD1 + 0x3 + + + + + PRE_PERIPH_CLK_SEL + Selector for pre_periph clock multiplexer + 18 + 2 + read-write + + + PRE_PERIPH_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH_CLK_SEL_3 + derive clock from divided PLL1 + 0x3 + + + + + LCDIF_PODF + Post-divider for LCDIF clock. + 23 + 3 + read-write + + + LCDIF_PODF_0 + divide by 1 + 0 + + + LCDIF_PODF_1 + divide by 2 + 0x1 + + + LCDIF_PODF_2 + divide by 3 + 0x2 + + + LCDIF_PODF_3 + divide by 4 + 0x3 + + + LCDIF_PODF_4 + divide by 5 + 0x4 + + + LCDIF_PODF_5 + divide by 6 + 0x5 + + + LCDIF_PODF_6 + divide by 7 + 0x6 + + + LCDIF_PODF_7 + divide by 8 + 0x7 + + + + + LPSPI_PODF + Divider for LPSPI. Divider should be updated when output clock is gated. + 26 + 3 + read-write + + + LPSPI_PODF_0 + divide by 1 + 0 + + + LPSPI_PODF_1 + divide by 2 + 0x1 + + + LPSPI_PODF_2 + divide by 3 + 0x2 + + + LPSPI_PODF_3 + divide by 4 + 0x3 + + + LPSPI_PODF_4 + divide by 5 + 0x4 + + + LPSPI_PODF_5 + divide by 6 + 0x5 + + + LPSPI_PODF_6 + divide by 7 + 0x6 + + + LPSPI_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0x4900000 + 0xFFFFFFFF + + + PERCLK_PODF + Divider for perclk podf. + 0 + 6 + read-write + + + PERCLK_PODF_0 + divide by 1 + 0 + + + PERCLK_PODF_1 + divide by 2 + 0x1 + + + PERCLK_PODF_2 + divide by 3 + 0x2 + + + PERCLK_PODF_3 + divide by 4 + 0x3 + + + PERCLK_PODF_4 + divide by 5 + 0x4 + + + PERCLK_PODF_5 + divide by 6 + 0x5 + + + PERCLK_PODF_6 + divide by 7 + 0x6 + + + PERCLK_PODF_63 + divide by 64 + 0x3F + + + + + PERCLK_CLK_SEL + Selector for the perclk clock multiplexor + 6 + 1 + read-write + + + PERCLK_CLK_SEL_0 + derive clock from ipg clk root + 0 + + + PERCLK_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + SAI1_CLK_SEL + Selector for sai1 clock multiplexer + 10 + 2 + read-write + + + SAI1_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI1_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI1_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI2_CLK_SEL + Selector for sai2 clock multiplexer + 12 + 2 + read-write + + + SAI2_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI2_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI2_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI3_CLK_SEL + Selector for sai3 clock multiplexer + 14 + 2 + read-write + + + SAI3_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI3_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI3_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + USDHC1_CLK_SEL + Selector for usdhc1 clock multiplexer + 16 + 1 + read-write + + + USDHC1_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC1_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + USDHC2_CLK_SEL + Selector for usdhc2 clock multiplexer + 17 + 1 + read-write + + + USDHC2_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC2_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + FLEXSPI_PODF + Divider for flexspi clock root. + 23 + 3 + read-write + + + FLEXSPI_PODF_0 + divide by 1 + 0 + + + FLEXSPI_PODF_1 + divide by 2 + 0x1 + + + FLEXSPI_PODF_2 + divide by 3 + 0x2 + + + FLEXSPI_PODF_3 + divide by 4 + 0x3 + + + FLEXSPI_PODF_4 + divide by 5 + 0x4 + + + FLEXSPI_PODF_5 + divide by 6 + 0x5 + + + FLEXSPI_PODF_6 + divide by 7 + 0x6 + + + FLEXSPI_PODF_7 + divide by 8 + 0x7 + + + + + FLEXSPI_CLK_SEL + Selector for flexspi clock multiplexer + 29 + 2 + read-write + + + FLEXSPI_CLK_SEL_0 + derive clock from semc_clk_root_pre + 0 + + + FLEXSPI_CLK_SEL_1 + derive clock from pll3_sw_clk + 0x1 + + + FLEXSPI_CLK_SEL_2 + derive clock from PLL2 PFD2 + 0x2 + + + FLEXSPI_CLK_SEL_3 + derive clock from PLL3 PFD0 + 0x3 + + + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x13192F06 + 0xFFFFFFFF + + + CAN_CLK_PODF + Divider for CAN clock podf. + 2 + 6 + read-write + + + CAN_CLK_PODF_0 + divide by 1 + 0 + + + CAN_CLK_PODF_7 + divide by 8 + 0x7 + + + CAN_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + CAN_CLK_SEL + Selector for CAN clock multiplexer + 8 + 2 + read-write + + + CAN_CLK_SEL_0 + derive clock from pll3_sw_clk divided clock (60M) + 0 + + + CAN_CLK_SEL_1 + derive clock from osc_clk (24M) + 0x1 + + + CAN_CLK_SEL_2 + derive clock from pll3_sw_clk divided clock (80M) + 0x2 + + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + + + + + FLEXIO2_CLK_SEL + Selector for flexio2 clock multiplexer + 19 + 2 + read-write + + + FLEXIO2_CLK_SEL_0 + derive clock from PLL4 divided clock + 0 + + + FLEXIO2_CLK_SEL_1 + derive clock from PLL3 PFD2 clock + 0x1 + + + FLEXIO2_CLK_SEL_2 + derive clock from PLL5 clock + 0x2 + + + FLEXIO2_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x6490B00 + 0xFFFFFFFF + + + UART_CLK_PODF + Divider for uart clock podf. + 0 + 6 + read-write + + + UART_CLK_PODF_0 + divide by 1 + 0 + + + UART_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + UART_CLK_SEL + Selector for the UART clock multiplexor + 6 + 1 + read-write + + + UART_CLK_SEL_0 + derive clock from pll3_80m + 0 + + + UART_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + USDHC1_PODF + Divider for usdhc1 clock podf. Divider should be updated when output clock is gated. + 11 + 3 + read-write + + + USDHC1_PODF_0 + divide by 1 + 0 + + + USDHC1_PODF_1 + divide by 2 + 0x1 + + + USDHC1_PODF_2 + divide by 3 + 0x2 + + + USDHC1_PODF_3 + divide by 4 + 0x3 + + + USDHC1_PODF_4 + divide by 5 + 0x4 + + + USDHC1_PODF_5 + divide by 6 + 0x5 + + + USDHC1_PODF_6 + divide by 7 + 0x6 + + + USDHC1_PODF_7 + divide by 8 + 0x7 + + + + + USDHC2_PODF + Divider for usdhc2 clock. Divider should be updated when output clock is gated. + 16 + 3 + read-write + + + USDHC2_PODF_0 + divide by 1 + 0 + + + USDHC2_PODF_1 + divide by 2 + 0x1 + + + USDHC2_PODF_2 + divide by 3 + 0x2 + + + USDHC2_PODF_3 + divide by 4 + 0x3 + + + USDHC2_PODF_4 + divide by 5 + 0x4 + + + USDHC2_PODF_5 + divide by 6 + 0x5 + + + USDHC2_PODF_6 + divide by 7 + 0x6 + + + USDHC2_PODF_7 + divide by 8 + 0x7 + + + + + TRACE_PODF + Divider for trace clock. Divider should be updated when output clock is gated. + 25 + 2 + read-write + + + TRACE_PODF_0 + divide by 1 + 0 + + + TRACE_PODF_1 + divide by 2 + 0x1 + + + TRACE_PODF_2 + divide by 3 + 0x2 + + + TRACE_PODF_3 + divide by 4 + 0x3 + + + + + + + CS1CDR + CCM Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + SAI1_CLK_PODF + Divider for sai1 clock podf + 0 + 6 + read-write + + + SAI1_CLK_PODF_0 + divide by 1 + 0 + + + SAI1_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI1_CLK_PRED + Divider for sai1 clock pred. + 6 + 3 + read-write + + + SAI1_CLK_PRED_0 + divide by 1 + 0 + + + SAI1_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI1_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI1_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI1_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI1_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI1_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO2_CLK_PRED + Divider for flexio2 clock. + 9 + 3 + read-write + + + FLEXIO2_CLK_PRED_0 + divide by 1 + 0 + + + FLEXIO2_CLK_PRED_1 + divide by 2 + 0x1 + + + FLEXIO2_CLK_PRED_2 + divide by 3 + 0x2 + + + FLEXIO2_CLK_PRED_3 + divide by 4 + 0x3 + + + FLEXIO2_CLK_PRED_4 + divide by 5 + 0x4 + + + FLEXIO2_CLK_PRED_5 + divide by 6 + 0x5 + + + FLEXIO2_CLK_PRED_6 + divide by 7 + 0x6 + + + FLEXIO2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + SAI3_CLK_PODF + Divider for sai3 clock podf + 16 + 6 + read-write + + + SAI3_CLK_PODF_0 + divide by 1 + 0 + + + SAI3_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI3_CLK_PRED + Divider for sai3 clock pred. + 22 + 3 + read-write + + + SAI3_CLK_PRED_0 + divide by 1 + 0 + + + SAI3_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI3_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI3_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI3_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI3_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI3_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI3_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO2_CLK_PODF + Divider for flexio2 clock. + 25 + 3 + read-write + + + FLEXIO2_CLK_PODF_0 + divide by 1 + 0 + + + FLEXIO2_CLK_PODF_1 + divide by 2 + 0x1 + + + FLEXIO2_CLK_PODF_2 + divide by 3 + 0x2 + + + FLEXIO2_CLK_PODF_3 + divide by 4 + 0x3 + + + FLEXIO2_CLK_PODF_4 + divide by 5 + 0x4 + + + FLEXIO2_CLK_PODF_5 + divide by 6 + 0x5 + + + FLEXIO2_CLK_PODF_6 + divide by 7 + 0x6 + + + FLEXIO2_CLK_PODF_7 + divide by 8 + 0x7 + + + + + + + CS2CDR + CCM Clock Divider Register + 0x2C + 32 + read-write + 0x7336C1 + 0xFFFFFFFF + + + SAI2_CLK_PODF + Divider for sai2 clock podf + 0 + 6 + read-write + + + SAI2_CLK_PODF_0 + divide by 1 + 0 + + + SAI2_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI2_CLK_PRED + Divider for sai2 clock pred.Divider should be updated when output clock is gated. + 6 + 3 + read-write + + + SAI2_CLK_PRED_0 + divide by 1 + 0 + + + SAI2_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI2_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI2_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI2_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI2_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI2_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + FLEXIO1_CLK_SEL + Selector for flexio1 clock multiplexer + 7 + 2 + read-write + + + FLEXIO1_CLK_SEL_0 + derive clock from PLL4 + 0 + + + FLEXIO1_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + FLEXIO1_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + FLEXIO1_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + FLEXIO1_CLK_PODF + Divider for flexio1 clock podf. Divider should be updated when output clock is gated. + 9 + 3 + read-write + + + FLEXIO1_CLK_PODF_0 + divide by 1 + 0 + + + FLEXIO1_CLK_PODF_7 + divide by 8 + 0x7 + + + + + FLEXIO1_CLK_PRED + Divider for flexio1 clock pred. Divider should be updated when output clock is gated. + 12 + 3 + read-write + + + FLEXIO1_CLK_PRED_0 + divide by 1 (do not use with high input frequencies) + 0 + + + FLEXIO1_CLK_PRED_1 + divide by 2 + 0x1 + + + FLEXIO1_CLK_PRED_2 + divide by 3 + 0x2 + + + FLEXIO1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + SPDIF0_CLK_SEL + Selector for spdif0 clock multiplexer + 20 + 2 + read-write + + + SPDIF0_CLK_SEL_0 + derive clock from PLL4 + 0 + + + SPDIF0_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + SPDIF0_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + SPDIF0_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + SPDIF0_CLK_PODF + Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + 22 + 3 + read-write + + + SPDIF0_CLK_PODF_0 + divide by 1 + 0 + + + SPDIF0_CLK_PODF_7 + divide by 8 + 0x7 + + + + + SPDIF0_CLK_PRED + Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + SPDIF0_CLK_PRED_0 + divide by 1 (do not use with high input frequencies) + 0 + + + SPDIF0_CLK_PRED_1 + divide by 2 + 0x1 + + + SPDIF0_CLK_PRED_2 + divide by 3 + 0x2 + + + SPDIF0_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29150 + 0xFFFFFFFF + + + LCDIF_PRED + Pre-divider for lcdif clock. Divider should be updated when output clock is gated. + 12 + 3 + read-write + + + LCDIF_PRED_0 + divide by 1 + 0 + + + LCDIF_PRED_1 + divide by 2 + 0x1 + + + LCDIF_PRED_2 + divide by 3 + 0x2 + + + LCDIF_PRED_3 + divide by 4 + 0x3 + + + LCDIF_PRED_4 + divide by 5 + 0x4 + + + LCDIF_PRED_5 + divide by 6 + 0x5 + + + LCDIF_PRED_6 + divide by 7 + 0x6 + + + LCDIF_PRED_7 + divide by 8 + 0x7 + + + + + LCDIF_PRE_CLK_SEL + Selector for lcdif root clock pre-multiplexer + 15 + 3 + read-write + + + LCDIF_PRE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + LCDIF_PRE_CLK_SEL_1 + derive clock from PLL3 PFD3 + 0x1 + + + LCDIF_PRE_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + LCDIF_PRE_CLK_SEL_3 + derive clock from PLL2 PFD0 + 0x3 + + + LCDIF_PRE_CLK_SEL_4 + derive clock from PLL2 PFD1 + 0x4 + + + LCDIF_PRE_CLK_SEL_5 + derive clock from PLL3 PFD1 + 0x5 + + + + + LPI2C_CLK_SEL + Selector for the LPI2C clock multiplexor + 18 + 1 + read-write + + + LPI2C_CLK_SEL_0 + derive clock from pll3_60m + 0 + + + LPI2C_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + LPI2C_CLK_PODF + Divider for lpi2c clock podf + 19 + 6 + read-write + + + LPI2C_CLK_PODF_0 + divide by 1 + 0 + + + LPI2C_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-write + 0x30841 + 0xFFFFFFFF + + + CSI_CLK_SEL + Selector for csi_mclk multiplexer + 9 + 2 + read-write + + + CSI_CLK_SEL_0 + derive clock from osc_clk (24M) + 0 + + + CSI_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + CSI_CLK_SEL_2 + derive clock from pll3_120M + 0x2 + + + CSI_CLK_SEL_3 + derive clock from PLL3 PFD1 + 0x3 + + + + + CSI_PODF + Post divider for csi_mclk. Divider should be updated when output clock is gated. + 11 + 3 + read-write + + + CSI_PODF_0 + divide by 1 + 0 + + + CSI_PODF_1 + divide by 2 + 0x1 + + + CSI_PODF_2 + divide by 3 + 0x2 + + + CSI_PODF_3 + divide by 4 + 0x3 + + + CSI_PODF_4 + divide by 5 + 0x4 + + + CSI_PODF_5 + divide by 6 + 0x5 + + + CSI_PODF_6 + divide by 7 + 0x6 + + + CSI_PODF_7 + divide by 8 + 0x7 + + + + + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEMC_PODF_BUSY + Busy indicator for semc_podf. + 0 + 1 + read-only + + + SEMC_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + SEMC_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + 0x1 + + + + + AHB_PODF_BUSY + Busy indicator for ahb_podf. + 1 + 1 + read-only + + + AHB_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AHB_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + 0x1 + + + + + PERIPH2_CLK_SEL_BUSY + Busy indicator for periph2_clk_sel mux control. + 3 + 1 + read-only + + + PERIPH2_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH2_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + 0x1 + + + + + PERIPH_CLK_SEL_BUSY + Busy indicator for periph_clk_sel mux control. + 5 + 1 + read-only + + + PERIPH_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + 0x1 + + + + + ARM_PODF_BUSY + Busy indicator for arm_podf. + 16 + 1 + read-only + + + ARM_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + ARM_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + 0x1 + + + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM_0 + Remain in run mode + 0 + + + LPM_1 + Transfer to wait mode + 0x1 + + + LPM_2 + Transfer to stop mode + 0x2 + + + + + ARM_CLK_DIS_ON_LPM + Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode + 5 + 1 + read-write + + + ARM_CLK_DIS_ON_LPM_0 + ARM clock enabled on wait mode. + 0 + + + ARM_CLK_DIS_ON_LPM_1 + ARM clock disabled on wait mode. . + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 6 + 1 + read-write + + + SBYOS_0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + 0 + + + SBYOS_1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + 0x1 + + + + + DIS_REF_OSC + dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i + 7 + 1 + read-write + + + DIS_REF_OSC_0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + 0 + + + DIS_REF_OSC_1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + 0x1 + + + + + VSTBY + Voltage standby request bit + 8 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + 0x1 + + + + + STBY_COUNT + Standby counter definition + 9 + 2 + read-write + + + STBY_COUNT_0 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + 0 + + + STBY_COUNT_1 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + 0x3 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 11 + 1 + read-write + + + COSC_PWRDOWN_0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + 0 + + + COSC_PWRDOWN_1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + 0x1 + + + + + BYPASS_LPM_HS1 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 19 + 1 + read-write + + + BYPASS_LPM_HS0 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 21 + 1 + read-write + + + MASK_CORE0_WFI + Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 22 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI of core0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI of core0 is masked + 0x1 + + + + + MASK_SCU_IDLE + Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 26 + 1 + read-write + + + MASK_SCU_IDLE_0 + SCU IDLE is not masked + 0 + + + MASK_SCU_IDLE_1 + SCU IDLE is masked + 0x1 + + + + + MASK_L2CC_IDLE + Mask L2CC IDLE for entering low power mode + 27 + 1 + read-write + + + MASK_L2CC_IDLE_0 + L2CC IDLE is not masked + 0 + + + MASK_L2CC_IDLE_1 + L2CC IDLE is masked + 0x1 + + + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRF_PLL + CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs + 0 + 1 + read-write + oneToClear + + + LRF_PLL_0 + interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + 0 + + + LRF_PLL_1 + interrupt generated due to lock ready of all enabled and not bypaseed PLLs + 0x1 + + + + + COSC_READY + CCM interrupt request 2 generated due to on board oscillator ready, i + 6 + 1 + read-write + oneToClear + + + COSC_READY_0 + interrupt is not generated due to on board oscillator ready + 0 + + + COSC_READY_1 + interrupt generated due to on board oscillator ready + 0x1 + + + + + SEMC_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of semc_podf + 17 + 1 + read-write + oneToClear + + + SEMC_PODF_LOADED_0 + interrupt is not generated due to frequency change of semc_podf + 0 + + + SEMC_PODF_LOADED_1 + interrupt generated due to frequency change of semc_podf + 0x1 + + + + + PERIPH2_CLK_SEL_LOADED + CCM interrupt request 1 generated due to frequency change of periph2_clk_sel + 19 + 1 + read-write + oneToClear + + + PERIPH2_CLK_SEL_LOADED_0 + interrupt is not generated due to frequency change of periph2_clk_sel + 0 + + + PERIPH2_CLK_SEL_LOADED_1 + interrupt generated due to frequency change of periph2_clk_sel + 0x1 + + + + + AHB_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of ahb_podf + 20 + 1 + read-write + oneToClear + + + AHB_PODF_LOADED_0 + interrupt is not generated due to frequency change of ahb_podf + 0 + + + AHB_PODF_LOADED_1 + interrupt generated due to frequency change of ahb_podf + 0x1 + + + + + PERIPH_CLK_SEL_LOADED + CCM interrupt request 1 generated due to update of periph_clk_sel. + 22 + 1 + read-write + oneToClear + + + PERIPH_CLK_SEL_LOADED_0 + interrupt is not generated due to update of periph_clk_sel. + 0 + + + PERIPH_CLK_SEL_LOADED_1 + interrupt generated due to update of periph_clk_sel. + 0x1 + + + + + ARM_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of arm_podf + 26 + 1 + read-write + oneToClear + + + ARM_PODF_LOADED_0 + interrupt is not generated due to frequency change of arm_podf + 0 + + + ARM_PODF_LOADED_1 + interrupt generated due to frequency change of arm_podf + 0x1 + + + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MASK_LRF_PLL + mask interrupt generation due to lrf of PLLs + 0 + 1 + read-write + + + MASK_LRF_PLL_0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + 0 + + + MASK_LRF_PLL_1 + mask interrupt due to lrf of PLLs + 0x1 + + + + + MASK_COSC_READY + mask interrupt generation due to on board oscillator ready + 6 + 1 + read-write + + + MASK_COSC_READY_0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + 0 + + + MASK_COSC_READY_1 + mask interrupt due to on board oscillator ready + 0x1 + + + + + MASK_SEMC_PODF_LOADED + mask interrupt generation due to frequency change of semc_podf + 17 + 1 + read-write + + + MASK_SEMC_PODF_LOADED_0 + don't mask interrupt due to frequency change of semc_podf - interrupt will be created + 0 + + + MASK_SEMC_PODF_LOADED_1 + mask interrupt due to frequency change of semc_podf + 0x1 + + + + + MASK_PERIPH2_CLK_SEL_LOADED + mask interrupt generation due to update of periph2_clk_sel. + 19 + 1 + read-write + + + MASK_PERIPH2_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH2_CLK_SEL_LOADED_1 + mask interrupt due to update of periph2_clk_sel + 0x1 + + + + + MASK_AHB_PODF_LOADED + mask interrupt generation due to frequency change of ahb_podf + 20 + 1 + read-write + + + MASK_AHB_PODF_LOADED_0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + 0 + + + MASK_AHB_PODF_LOADED_1 + mask interrupt due to frequency change of ahb_podf + 0x1 + + + + + MASK_PERIPH_CLK_SEL_LOADED + mask interrupt generation due to update of periph_clk_sel. + 22 + 1 + read-write + + + MASK_PERIPH_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH_CLK_SEL_LOADED_1 + mask interrupt due to update of periph_clk_sel + 0x1 + + + + + ARM_PODF_LOADED + mask interrupt generation due to frequency change of arm_podf + 26 + 1 + read-write + + + ARM_PODF_LOADED_0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + 0 + + + ARM_PODF_LOADED_1 + mask interrupt due to frequency change of arm_podf + 0x1 + + + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO1_SEL + Selection of the clock to be generated on CCM_CLKO1 + 0 + 4 + read-write + + + CLKO1_SEL_0 + USB1 PLL clock (divided by 2) + 0 + + + CLKO1_SEL_1 + SYS PLL clock (divided by 2) + 0x1 + + + CLKO1_SEL_3 + VIDEO PLL clock (divided by 2) + 0x3 + + + CLKO1_SEL_5 + semc_clk_root + 0x5 + + + CLKO1_SEL_10 + lcdif_pix_clk_root + 0xA + + + CLKO1_SEL_11 + ahb_clk_root + 0xB + + + CLKO1_SEL_12 + ipg_clk_root + 0xC + + + CLKO1_SEL_13 + perclk_root + 0xD + + + CLKO1_SEL_14 + ckil_sync_clk_root + 0xE + + + CLKO1_SEL_15 + pll4_main_clk + 0xF + + + + + CLKO1_DIV + Setting the divider of CCM_CLKO1 + 4 + 3 + read-write + + + CLKO1_DIV_0 + divide by 1 + 0 + + + CLKO1_DIV_1 + divide by 2 + 0x1 + + + CLKO1_DIV_2 + divide by 3 + 0x2 + + + CLKO1_DIV_3 + divide by 4 + 0x3 + + + CLKO1_DIV_4 + divide by 5 + 0x4 + + + CLKO1_DIV_5 + divide by 6 + 0x5 + + + CLKO1_DIV_6 + divide by 7 + 0x6 + + + CLKO1_DIV_7 + divide by 8 + 0x7 + + + + + CLKO1_EN + Enable of CCM_CLKO1 clock + 7 + 1 + read-write + + + CLKO1_EN_0 + CCM_CLKO1 disabled. + 0 + + + CLKO1_EN_1 + CCM_CLKO1 enabled. + 0x1 + + + + + CLK_OUT_SEL + CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + 8 + 1 + read-write + + + CLK_OUT_SEL_0 + CCM_CLKO1 output drives CCM_CLKO1 clock + 0 + + + CLK_OUT_SEL_1 + CCM_CLKO1 output drives CCM_CLKO2 clock + 0x1 + + + + + CLKO2_SEL + Selection of the clock to be generated on CCM_CLKO2 + 16 + 5 + read-write + + + CLKO2_SEL_3 + usdhc1_clk_root + 0x3 + + + CLKO2_SEL_5 + wrck_clk_root + 0x5 + + + CLKO2_SEL_6 + lpi2c_clk_root + 0x6 + + + CLKO2_SEL_11 + csi_clk_root + 0xB + + + CLKO2_SEL_14 + osc_clk + 0xE + + + CLKO2_SEL_17 + usdhc2_clk_root + 0x11 + + + CLKO2_SEL_18 + sai1_clk_root + 0x12 + + + CLKO2_SEL_19 + sai2_clk_root + 0x13 + + + CLKO2_SEL_20 + sai3_clk_root + 0x14 + + + CLKO2_SEL_23 + can_clk_root + 0x17 + + + CLKO2_SEL_27 + flexspi_clk_root + 0x1B + + + CLKO2_SEL_28 + uart_clk_root + 0x1C + + + CLKO2_SEL_29 + spdif0_clk_root + 0x1D + + + + + CLKO2_DIV + Setting the divider of CCM_CLKO2 + 21 + 3 + read-write + + + CLKO2_DIV_0 + divide by 1 + 0 + + + CLKO2_DIV_1 + divide by 2 + 0x1 + + + CLKO2_DIV_2 + divide by 3 + 0x2 + + + CLKO2_DIV_3 + divide by 4 + 0x3 + + + CLKO2_DIV_4 + divide by 5 + 0x4 + + + CLKO2_DIV_5 + divide by 6 + 0x5 + + + CLKO2_DIV_6 + divide by 7 + 0x6 + + + CLKO2_DIV_7 + divide by 8 + 0x7 + + + + + CLKO2_EN + Enable of CCM_CLKO2 clock + 24 + 1 + read-write + + + CLKO2_EN_0 + CCM_CLKO2 disabled. + 0 + + + CLKO2_EN_1 + CCM_CLKO2 enabled. + 0x1 + + + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + PMIC_DELAY_SCALER + Defines clock dividion of clock for stby_count (pmic delay counter) + 0 + 1 + read-write + + + PMIC_DELAY_SCALER_0 + clock is not divided + 0 + + + PMIC_DELAY_SCALER_1 + clock is divided /8 + 0x1 + + + + + EFUSE_PROG_SUPPLY_GATE + Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + 4 + 1 + read-write + + + EFUSE_PROG_SUPPLY_GATE_0 + fuse programing supply voltage is gated off to the efuse module + 0 + + + EFUSE_PROG_SUPPLY_GATE_1 + allow fuse programing. + 0x1 + + + + + SYS_MEM_DS_CTRL + System memory DS control + 14 + 2 + read-write + + + SYS_MEM_DS_CTRL_0 + Disable memory DS mode always + 0 + + + SYS_MEM_DS_CTRL_1 + Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + 0x1 + + + SYS_MEM_DS_CTRL_2 + enable memory (outside ARM platform) DS mode when system is in STOP mode + #1x + + + + + FPL + Fast PLL enable. + 16 + 1 + read-write + + + FPL_0 + Engage PLL enable default way. + 0 + + + FPL_1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + 0x1 + + + + + INT_MEM_CLK_LPM + Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal + 17 + 1 + read-write + + + INT_MEM_CLK_LPM_0 + Disable the clock to the ARM platform memories when entering Low Power Mode + 0 + + + INT_MEM_CLK_LPM_1 + Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + 0x1 + + + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + aips_tz1 clocks (aips_tz1_clk_enable) + 0 + 2 + read-write + + + CG1 + aips_tz2 clocks (aips_tz2_clk_enable) + 2 + 2 + read-write + + + CG2 + mqs clock ( mqs_hmclk_clock_enable) + 4 + 2 + read-write + + + CG3 + flexspi_exsc clock (flexspi_exsc_clk_enable) + 6 + 2 + read-write + + + CG4 + sim_m or sim_main register access clock (sim_m_mainclk_r_enable) + 8 + 2 + read-write + + + CG5 + dcp clock (dcp_clk_enable) + 10 + 2 + read-write + + + CG6 + lpuart3 clock (lpuart3_clk_enable) + 12 + 2 + read-write + + + CG7 + can1 clock (can1_clk_enable) + 14 + 2 + read-write + + + CG8 + can1_serial clock (can1_serial_clk_enable) + 16 + 2 + read-write + + + CG9 + can2 clock (can2_clk_enable) + 18 + 2 + read-write + + + CG10 + can2_serial clock (can2_serial_clk_enable) + 20 + 2 + read-write + + + CG11 + trace clock (trace_clk_enable) + 22 + 2 + read-write + + + CG12 + gpt2 bus clocks (gpt2_bus_clk_enable) + 24 + 2 + read-write + + + CG13 + gpt2 serial clocks (gpt2_serial_clk_enable) + 26 + 2 + read-write + + + CG14 + lpuart2 clock (lpuart2_clk_enable) + 28 + 2 + read-write + + + CG15 + gpio2_clocks (gpio2_clk_enable) + 30 + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + lpspi1 clocks (lpspi1_clk_enable) + 0 + 2 + read-write + + + CG1 + lpspi2 clocks (lpspi2_clk_enable) + 2 + 2 + read-write + + + CG2 + lpspi3 clocks (lpspi3_clk_enable) + 4 + 2 + read-write + + + CG3 + lpspi4 clocks (lpspi4_clk_enable) + 6 + 2 + read-write + + + CG4 + adc2 clock (adc2_clk_enable) + 8 + 2 + read-write + + + CG5 + enet clock (enet_clk_enable) + 10 + 2 + read-write + + + CG6 + pit clocks (pit_clk_enable) + 12 + 2 + read-write + + + CG7 + aoi2 clocks (aoi2_clk_enable) + 14 + 2 + read-write + + + CG8 + adc1 clock (adc1_clk_enable) + 16 + 2 + read-write + + + CG9 + semc_exsc clock (semc_exsc_clk_enable) + 18 + 2 + read-write + + + CG10 + gpt1 bus clock (gpt_clk_enable) + 20 + 2 + read-write + + + CG11 + gpt1 serial clock (gpt_serial_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart4 clock (lpuart4_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio1 clock (gpio1_clk_enable) + 26 + 2 + read-write + + + CG14 + csu clock (csu_clk_enable) + 28 + 2 + read-write + + + CG15 + Reserved + 30 + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + ocram_exsc clock (ocram_exsc_clk_enable) + 0 + 2 + read-write + + + CG1 + csi clock (csi_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc_snvs clock (iomuxc_snvs_clk_enable) + 4 + 2 + read-write + + + CG3 + lpi2c1 clock (lpi2c1_clk_enable) + 6 + 2 + read-write + + + CG4 + lpi2c2 clock (lpi2c2_clk_enable) + 8 + 2 + read-write + + + CG5 + lpi2c3 clock (lpi2c3_clk_enable) + 10 + 2 + read-write + + + CG6 + OCOTP_CTRL clock (iim_clk_enable) + 12 + 2 + read-write + + + CG7 + xbar3 clock (xbar3_clk_enable) + 14 + 2 + read-write + + + CG8 + ipmux1 clock (ipmux1_clk_enable) + 16 + 2 + read-write + + + CG9 + ipmux2 clock (ipmux2_clk_enable) + 18 + 2 + read-write + + + CG10 + ipmux3 clock (ipmux3_clk_enable) + 20 + 2 + read-write + + + CG11 + xbar1 clock (xbar1_clk_enable) + 22 + 2 + read-write + + + CG12 + xbar2 clock (xbar2_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio3 clock (gpio3_clk_enable) + 26 + 2 + read-write + + + CG14 + lcd clocks (lcd_clk_enable) + 28 + 2 + read-write + + + CG15 + pxp clocks (pxp_clk_enable) + 30 + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFCF + 0xFFFFFFFF + + + CG0 + flexio2 clocks (flexio2_clk_enable) + 0 + 2 + read-write + + + CG1 + lpuart5 clock (lpuart5_clk_enable) + 2 + 2 + read-write + + + CG2 + semc clocks (semc_clk_enable) + 4 + 2 + read-write + + + CG3 + lpuart6 clock (lpuart6_clk_enable) + 6 + 2 + read-write + + + CG4 + aoi1 clock (aoi1_clk_enable) + 8 + 2 + read-write + + + CG5 + lcdif pix clock (lcdif_pix_clk_enable) + 10 + 2 + read-write + + + CG6 + gpio4 clock (gpio4_clk_enable) + 12 + 2 + read-write + + + CG7 + ewm clocks (ewm_clk_enable) + 14 + 2 + read-write + + + CG8 + wdog1 clock (wdog1_clk_enable) + 16 + 2 + read-write + + + CG9 + flexram clock (flexram_clk_enable) + 18 + 2 + read-write + + + CG10 + acmp1 clocks (acmp1_clk_enable) + 20 + 2 + read-write + + + CG11 + acmp2 clocks (acmp2_clk_enable) + 22 + 2 + read-write + + + CG12 + acmp3 clocks (acmp3_clk_enable) + 24 + 2 + read-write + + + CG13 + acmp4 clocks (acmp4_clk_enable) + 26 + 2 + read-write + + + CG14 + ocram clock (ocram_clk_enable) + 28 + 2 + read-write + + + CG15 + iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) + 30 + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + sim_m7 register access clock (sim_m7_mainclk_r_enable) + 0 + 2 + read-write + + + CG1 + iomuxc clock (iomuxc_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc gpr clock (iomuxc_gpr_clk_enable) + 4 + 2 + read-write + + + CG3 + bee clock(bee_clk_enable) + 6 + 2 + read-write + + + CG4 + sim_m7 clock (sim_m7_clk_enable) + 8 + 2 + read-write + + + CG5 + tsc_dig clock (tsc_clk_enable) + 10 + 2 + read-write + + + CG6 + sim_m clocks (sim_m_clk_enable) + 12 + 2 + read-write + + + CG7 + sim_ems clocks (sim_ems_clk_enable) + 14 + 2 + read-write + + + CG8 + pwm1 clocks (pwm1_clk_enable) + 16 + 2 + read-write + + + CG9 + pwm2 clocks (pwm2_clk_enable) + 18 + 2 + read-write + + + CG10 + pwm3 clocks (pwm3_clk_enable) + 20 + 2 + read-write + + + CG11 + pwm4 clocks (pwm4_clk_enable) + 22 + 2 + read-write + + + CG12 + enc1 clocks (enc1_clk_enable) + 24 + 2 + read-write + + + CG13 + enc2 clocks (enc2_clk_enable) + 26 + 2 + read-write + + + CG14 + enc3 clocks (enc3_clk_enable) + 28 + 2 + read-write + + + CG15 + enc4 clocks (enc4_clk_enable) + 30 + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + rom clock (rom_clk_enable) + 0 + 2 + read-write + + + CG1 + flexio1 clock (flexio1_clk_enable) + 2 + 2 + read-write + + + CG2 + wdog3 clock (wdog3_clk_enable) + 4 + 2 + read-write + + + CG3 + dma clock (dma_clk_enable) + 6 + 2 + read-write + + + CG4 + kpp clock (kpp_clk_enable) + 8 + 2 + read-write + + + CG5 + wdog2 clock (wdog2_clk_enable) + 10 + 2 + read-write + + + CG6 + aipstz4 clocks (aips_tz4_clk_enable) + 12 + 2 + read-write + + + CG7 + spdif clock (spdif_clk_enable) + 14 + 2 + read-write + + + CG8 + sim_main clock (sim_main_clk_enable) + 16 + 2 + read-write + + + CG9 + sai1 clock (sai1_clk_enable) + 18 + 2 + read-write + + + CG10 + sai2 clock (sai2_clk_enable) + 20 + 2 + read-write + + + CG11 + sai3 clock (sai3_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart1 clock (lpuart1_clk_enable) + 24 + 2 + read-write + + + CG13 + lpuart7 clock (lpuart7_clk_enable) + 26 + 2 + read-write + + + CG14 + snvs_hp clock (snvs_hp_clk_enable) + 28 + 2 + read-write + + + CG15 + snvs_lp clock (snvs_lp_clk_enable) + 30 + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + usboh3 clock (usboh3_clk_enable) + 0 + 2 + read-write + + + CG1 + usdhc1 clocks (usdhc1_clk_enable) + 2 + 2 + read-write + + + CG2 + usdhc2 clocks (usdhc2_clk_enable) + 4 + 2 + read-write + + + CG3 + dcdc clocks (dcdc_clk_enable) + 6 + 2 + read-write + + + CG4 + ipmux4 clock (ipmux4_clk_enable) + 8 + 2 + read-write + + + CG5 + flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared + 10 + 2 + read-write + + + CG6 + trng clock (trng_clk_enable) + 12 + 2 + read-write + + + CG7 + lpuart8 clocks (lpuart8_clk_enable) + 14 + 2 + read-write + + + CG8 + timer4 clocks (timer4_clk_enable) + 16 + 2 + read-write + + + CG9 + aips_tz3 clock (aips_tz3_clk_enable) + 18 + 2 + read-write + + + CG10 + sim_per clock (sim_per_clk_enable) + 20 + 2 + read-write + + + CG11 + anadig clocks (anadig_clk_enable) + 22 + 2 + read-write + + + CG12 + lpi2c4 serial clock (lpi2c4_serial_clk_enable) + 24 + 2 + read-write + + + CG13 + timer1 clocks (timer1_clk_enable) + 26 + 2 + read-write + + + CG14 + timer2 clocks (timer2_clk_enable) + 28 + 2 + read-write + + + CG15 + timer3 clocks (timer3_clk_enable) + 30 + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MOD_EN_OV_GPT + Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' + 5 + 1 + read-write + + + MOD_EN_OV_GPT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_GPT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_PIT + Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk' + 6 + 1 + read-write + + + MOD_EN_OV_PIT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_PIT_1 + override module enable signal + 0x1 + + + + + MOD_EN_USDHC + overide clock enable signal from USDHC. + 7 + 1 + read-write + + + MOD_EN_USDHC_0 + don't override module enable signal + 0 + + + MOD_EN_USDHC_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_TRNG + Overide clock enable signal from TRNG + 9 + 1 + read-write + + + MOD_EN_OV_TRNG_0 + don't override module enable signal + 0 + + + MOD_EN_OV_TRNG_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN2_CPI + Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 28 + 1 + read-write + + + MOD_EN_OV_CAN2_CPI_0 + don't override module enable signal + 0 + + + MOD_EN_OV_CAN2_CPI_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN1_CPI + Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 30 + 1 + read-write + + + MOD_EN_OV_CAN1_CPI_0 + don't overide module enable signal + 0 + + + MOD_EN_OV_CAN1_CPI_1 + overide module enable signal + 0x1 + + + + + + + + + ROMC + ROMC + ROMC + ROMC_ + 0x40180000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 29 + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch + 0 + 1 + read-write + + + THUMBX_0 + Arm patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 17 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + LPUART1 + LPUART + LPUART + LPUART + 0x40184000 + + 0 + 0x30 + registers + + + LPUART1 + 20 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x4010003 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + FEATURE_1 + Standard feature set. + 0x1 + + + FEATURE_3 + Standard feature set with MODEM/IrDA support. + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + + + GLOBAL + LPUART Global Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Module is not reset. + 0 + + + RST_1 + Module is reset. + 0x1 + + + + + + + PINCFG + LPUART Pin Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRGSEL + Trigger Select + 0 + 2 + read-write + + + TRGSEL_0 + Input trigger is disabled. + 0 + + + TRGSEL_1 + Input trigger is used instead of RXD pin input. + 0x1 + + + TRGSEL_2 + Input trigger is used instead of CTS_B pin input. + 0x2 + + + TRGSEL_3 + Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + 0x3 + + + + + + + BAUD + LPUART Baud Rate Register + 0x10 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor. + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + SBNS_0 + One stop bit. + 0 + + + SBNS_1 + Two stop bits. + 0x1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + RXEDGIE_0 + Hardware interrupts from STAT[RXEDGIF] are disabled. + 0 + + + RXEDGIE_1 + Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + 0x1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + LBKDIE_0 + Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + 0 + + + LBKDIE_1 + Hardware interrupt requested when STAT[LBKDIF] flag is 1. + 0x1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + RESYNCDIS_0 + Resynchronization during received data word is supported + 0 + + + RESYNCDIS_1 + Resynchronization during received data word is disabled + 0x1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + BOTHEDGE_0 + Receiver samples input data using the rising edge of the baud rate clock. + 0 + + + BOTHEDGE_1 + Receiver samples input data using the rising and falling edge of the baud rate clock. + 0x1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + MATCFG_0 + Address Match Wakeup + 0 + + + MATCFG_1 + Idle Match Wakeup + 0x1 + + + MATCFG_2 + Match On and Match Off + 0x2 + + + MATCFG_3 + no description available + 0x3 + + + + + RIDMAE + Receiver Idle DMA Enable + 20 + 1 + read-write + + + RIDMAE_0 + DMA request disabled. + 0 + + + RIDMAE_1 + DMA request enabled. + 0x1 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + RDMAE_0 + DMA request disabled. + 0 + + + RDMAE_1 + DMA request enabled. + 0x1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + TDMAE_0 + DMA request disabled. + 0 + + + TDMAE_1 + DMA request enabled. + 0x1 + + + + + OSR + Oversampling Ratio + 24 + 5 + read-write + + + OSR_0 + Writing 0 to this field will result in an oversampling ratio of 16 + 0 + + + OSR_3 + Oversampling ratio of 4, requires BOTHEDGE to be set. + 0x3 + + + OSR_4 + Oversampling ratio of 5, requires BOTHEDGE to be set. + 0x4 + + + OSR_5 + Oversampling ratio of 6, requires BOTHEDGE to be set. + 0x5 + + + OSR_6 + Oversampling ratio of 7, requires BOTHEDGE to be set. + 0x6 + + + OSR_7 + Oversampling ratio of 8. + 0x7 + + + OSR_8 + Oversampling ratio of 9. + 0x8 + + + OSR_9 + Oversampling ratio of 10. + 0x9 + + + OSR_10 + Oversampling ratio of 11. + 0xA + + + OSR_11 + Oversampling ratio of 12. + 0xB + + + OSR_12 + Oversampling ratio of 13. + 0xC + + + OSR_13 + Oversampling ratio of 14. + 0xD + + + OSR_14 + Oversampling ratio of 15. + 0xE + + + OSR_15 + Oversampling ratio of 16. + 0xF + + + OSR_16 + Oversampling ratio of 17. + 0x10 + + + OSR_17 + Oversampling ratio of 18. + 0x11 + + + OSR_18 + Oversampling ratio of 19. + 0x12 + + + OSR_19 + Oversampling ratio of 20. + 0x13 + + + OSR_20 + Oversampling ratio of 21. + 0x14 + + + OSR_21 + Oversampling ratio of 22. + 0x15 + + + OSR_22 + Oversampling ratio of 23. + 0x16 + + + OSR_23 + Oversampling ratio of 24. + 0x17 + + + OSR_24 + Oversampling ratio of 25. + 0x18 + + + OSR_25 + Oversampling ratio of 26. + 0x19 + + + OSR_26 + Oversampling ratio of 27. + 0x1A + + + OSR_27 + Oversampling ratio of 28. + 0x1B + + + OSR_28 + Oversampling ratio of 29. + 0x1C + + + OSR_29 + Oversampling ratio of 30. + 0x1D + + + OSR_30 + Oversampling ratio of 31. + 0x1E + + + OSR_31 + Oversampling ratio of 32. + 0x1F + + + + + M10 + 10-bit Mode select + 29 + 1 + read-write + + + M10_0 + Receiver and transmitter use 7-bit to 9-bit data characters. + 0 + + + M10_1 + Receiver and transmitter use 10-bit data characters. + 0x1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + MAEN2_0 + Normal operation. + 0 + + + MAEN2_1 + Enables automatic address matching or data matching mode for MATCH[MA2]. + 0x1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + MAEN1_0 + Normal operation. + 0 + + + MAEN1_1 + Enables automatic address matching or data matching mode for MATCH[MA1]. + 0x1 + + + + + + + STAT + LPUART Status Register + 0x14 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + MA2F + Match 2 Flag + 14 + 1 + read-write + oneToClear + + + MA2F_0 + Received data is not equal to MA2 + 0 + + + MA2F_1 + Received data is equal to MA2 + 0x1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + oneToClear + + + MA1F_0 + Received data is not equal to MA1 + 0 + + + MA1F_1 + Received data is equal to MA1 + 0x1 + + + + + PF + Parity Error Flag + 16 + 1 + read-write + oneToClear + + + PF_0 + No parity error. + 0 + + + PF_1 + Parity error. + 0x1 + + + + + FE + Framing Error Flag + 17 + 1 + read-write + oneToClear + + + FE_0 + No framing error detected. This does not guarantee the framing is correct. + 0 + + + FE_1 + Framing error. + 0x1 + + + + + NF + Noise Flag + 18 + 1 + read-write + oneToClear + + + NF_0 + No noise detected. + 0 + + + NF_1 + Noise detected in the received character in the DATA register. + 0x1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + oneToClear + + + OR_0 + No overrun. + 0 + + + OR_1 + Receive overrun (new LPUART data lost). + 0x1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + oneToClear + + + IDLE_0 + No idle line detected. + 0 + + + IDLE_1 + Idle line was detected. + 0x1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + RDRF_0 + Receive data buffer empty. + 0 + + + RDRF_1 + Receive data buffer full. + 0x1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + TC_0 + Transmitter active (sending data, a preamble, or a break). + 0 + + + TC_1 + Transmitter idle (transmission activity complete). + 0x1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + TDRE_0 + Transmit data buffer full. + 0 + + + TDRE_1 + Transmit data buffer empty. + 0x1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + RAF_0 + LPUART receiver idle waiting for a start bit. + 0 + + + RAF_1 + LPUART receiver active (RXD input not idle). + 0x1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + LBKDE_0 + LIN break detect is disabled, normal break character can be detected. + 0 + + + LBKDE_1 + LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + 0x1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + BRK13_0 + Break character is transmitted with length of 9 to 13 bit times. + 0 + + + BRK13_1 + Break character is transmitted with length of 12 to 15 bit times. + 0x1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + RWUID_0 + During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + 0 + + + RWUID_1 + During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + 0x1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + RXINV_0 + Receive data not inverted. + 0 + + + RXINV_1 + Receive data inverted. + 0x1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + MSBF_0 + LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + 0 + + + MSBF_1 + MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + 0x1 + + + + + RXEDGIF + RXD Pin Active Edge Interrupt Flag + 30 + 1 + read-write + oneToClear + + + RXEDGIF_0 + No active edge on the receive pin has occurred. + 0 + + + RXEDGIF_1 + An active edge on the receive pin has occurred. + 0x1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + oneToClear + + + LBKDIF_0 + No LIN break character has been detected. + 0 + + + LBKDIF_1 + LIN break character has been detected. + 0x1 + + + + + + + CTRL + LPUART Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + PT_0 + Even parity. + 0 + + + PT_1 + Odd parity. + 0x1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + PE_0 + No hardware parity generation or checking. + 0 + + + PE_1 + Parity enabled. + 0x1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + ILT_0 + Idle character bit count starts after start bit. + 0 + + + ILT_1 + Idle character bit count starts after stop bit. + 0x1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + WAKE_0 + Configures RWU for idle-line wakeup. + 0 + + + WAKE_1 + Configures RWU with address-mark wakeup. + 0x1 + + + + + M + 9-Bit or 8-Bit Mode Select + 4 + 1 + read-write + + + M_0 + Receiver and transmitter use 8-bit data characters. + 0 + + + M_1 + Receiver and transmitter use 9-bit data characters. + 0x1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + RSRC_0 + Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + 0 + + + RSRC_1 + Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + 0x1 + + + + + DOZEEN + Doze Enable + 6 + 1 + read-write + + + DOZEEN_0 + LPUART is enabled in Doze mode. + 0 + + + DOZEEN_1 + LPUART is disabled in Doze mode. + 0x1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + LOOPS_0 + Normal operation - RXD and TXD use separate pins. + 0 + + + LOOPS_1 + Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + 0x1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + IDLECFG_0 + 1 idle character + 0 + + + IDLECFG_1 + 2 idle characters + 0x1 + + + IDLECFG_2 + 4 idle characters + 0x2 + + + IDLECFG_3 + 8 idle characters + 0x3 + + + IDLECFG_4 + 16 idle characters + 0x4 + + + IDLECFG_5 + 32 idle characters + 0x5 + + + IDLECFG_6 + 64 idle characters + 0x6 + + + IDLECFG_7 + 128 idle characters + 0x7 + + + + + M7 + 7-Bit Mode Select + 11 + 1 + read-write + + + M7_0 + Receiver and transmitter use 8-bit to 10-bit data characters. + 0 + + + M7_1 + Receiver and transmitter use 7-bit data characters. + 0x1 + + + + + MA2IE + Match 2 Interrupt Enable + 14 + 1 + read-write + + + MA2IE_0 + MA2F interrupt disabled + 0 + + + MA2IE_1 + MA2F interrupt enabled + 0x1 + + + + + MA1IE + Match 1 Interrupt Enable + 15 + 1 + read-write + + + MA1IE_0 + MA1F interrupt disabled + 0 + + + MA1IE_1 + MA1F interrupt enabled + 0x1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + SBK_0 + Normal transmitter operation. + 0 + + + SBK_1 + Queue break character(s) to be sent. + 0x1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + RWU_0 + Normal receiver operation. + 0 + + + RWU_1 + LPUART receiver in standby waiting for wakeup condition. + 0x1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + RE_0 + Receiver disabled. + 0 + + + RE_1 + Receiver enabled. + 0x1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + TE_0 + Transmitter disabled. + 0 + + + TE_1 + Transmitter enabled. + 0x1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + ILIE_0 + Hardware interrupts from IDLE disabled; use polling. + 0 + + + ILIE_1 + Hardware interrupt requested when IDLE flag is 1. + 0x1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + RIE_0 + Hardware interrupts from RDRF disabled; use polling. + 0 + + + RIE_1 + Hardware interrupt requested when RDRF flag is 1. + 0x1 + + + + + TCIE + Transmission Complete Interrupt Enable for + 22 + 1 + read-write + + + TCIE_0 + Hardware interrupts from TC disabled; use polling. + 0 + + + TCIE_1 + Hardware interrupt requested when TC flag is 1. + 0x1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + TIE_0 + Hardware interrupts from TDRE disabled; use polling. + 0 + + + TIE_1 + Hardware interrupt requested when TDRE flag is 1. + 0x1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + PEIE_0 + PF interrupts disabled; use polling). + 0 + + + PEIE_1 + Hardware interrupt requested when PF is set. + 0x1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + FEIE_0 + FE interrupts disabled; use polling. + 0 + + + FEIE_1 + Hardware interrupt requested when FE is set. + 0x1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + NEIE_0 + NF interrupts disabled; use polling. + 0 + + + NEIE_1 + Hardware interrupt requested when NF is set. + 0x1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + ORIE_0 + OR interrupts disabled; use polling. + 0 + + + ORIE_1 + Hardware interrupt requested when OR is set. + 0x1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + TXINV_0 + Transmit data not inverted. + 0 + + + TXINV_1 + Transmit data inverted. + 0x1 + + + + + TXDIR + TXD Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + TXDIR_0 + TXD pin is an input in single-wire mode. + 0 + + + TXDIR_1 + TXD pin is an output in single-wire mode. + 0x1 + + + + + R9T8 + Receive Bit 9 / Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 / Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + LPUART Data Register + 0x1C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + R0T0 + 0 + 1 + read-write + + + R1T1 + R1T1 + 1 + 1 + read-write + + + R2T2 + R2T2 + 2 + 1 + read-write + + + R3T3 + R3T3 + 3 + 1 + read-write + + + R4T4 + R4T4 + 4 + 1 + read-write + + + R5T5 + R5T5 + 5 + 1 + read-write + + + R6T6 + R6T6 + 6 + 1 + read-write + + + R7T7 + R7T7 + 7 + 1 + read-write + + + R8T8 + R8T8 + 8 + 1 + read-write + + + R9T9 + R9T9 + 9 + 1 + read-write + + + IDLINE + Idle Line + 11 + 1 + read-only + + + IDLINE_0 + Receiver was not idle before receiving this character. + 0 + + + IDLINE_1 + Receiver was idle before receiving this character. + 0x1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + RXEMPT_0 + Receive buffer contains valid data. + 0 + + + RXEMPT_1 + Receive buffer is empty, data returned on read is not valid. + 0x1 + + + + + FRETSC + Frame Error / Transmit Special Character + 13 + 1 + read-write + + + FRETSC_0 + The dataword was received without a frame error on read, or transmit a normal character on write. + 0 + + + FRETSC_1 + The dataword was received with a frame error, or transmit an idle or break character on transmit. + 0x1 + + + + + PARITYE + PARITYE + 14 + 1 + read-only + + + PARITYE_0 + The dataword was received without a parity error. + 0 + + + PARITYE_1 + The dataword was received with a parity error. + 0x1 + + + + + NOISY + NOISY + 15 + 1 + read-only + + + NOISY_0 + The dataword was received without noise. + 0 + + + NOISY_1 + The data was received with noise. + 0x1 + + + + + + + MATCH + LPUART Match Address Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + LPUART Modem IrDA Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter clear-to-send enable + 0 + 1 + read-write + + + TXCTSE_0 + CTS has no effect on the transmitter. + 0 + + + TXCTSE_1 + Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + 0x1 + + + + + TXRTSE + Transmitter request-to-send enable + 1 + 1 + read-write + + + TXRTSE_0 + The transmitter has no effect on RTS. + 0 + + + TXRTSE_1 + When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + 0x1 + + + + + TXRTSPOL + Transmitter request-to-send polarity + 2 + 1 + read-write + + + TXRTSPOL_0 + Transmitter RTS is active low. + 0 + + + TXRTSPOL_1 + Transmitter RTS is active high. + 0x1 + + + + + RXRTSE + Receiver request-to-send enable + 3 + 1 + read-write + + + RXRTSE_0 + The receiver has no effect on RTS. + 0 + + + RXRTSE_1 + no description available + 0x1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + TXCTSC_0 + CTS input is sampled at the start of each character. + 0 + + + TXCTSC_1 + CTS input is sampled when the transmitter is idle. + 0x1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + TXCTSSRC_0 + CTS input is the CTS_B pin. + 0 + + + TXCTSSRC_1 + CTS input is the inverted Receiver Match result. + 0x1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 2 + read-write + + + TNP + Transmitter narrow pulse + 16 + 2 + read-write + + + TNP_0 + 1/OSR. + 0 + + + TNP_1 + 2/OSR. + 0x1 + + + TNP_2 + 3/OSR. + 0x2 + + + TNP_3 + 4/OSR. + 0x3 + + + + + IREN + Infrared enable + 18 + 1 + read-write + + + IREN_0 + IR disabled. + 0 + + + IREN_1 + IR enabled. + 0x1 + + + + + + + FIFO + LPUART FIFO Register + 0x28 + 32 + read-write + 0xC00011 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO Buffer Depth + 0 + 3 + read-only + + + RXFIFOSIZE_0 + Receive FIFO/Buffer depth = 1 dataword. + 0 + + + RXFIFOSIZE_1 + Receive FIFO/Buffer depth = 4 datawords. + 0x1 + + + RXFIFOSIZE_2 + Receive FIFO/Buffer depth = 8 datawords. + 0x2 + + + RXFIFOSIZE_3 + Receive FIFO/Buffer depth = 16 datawords. + 0x3 + + + RXFIFOSIZE_4 + Receive FIFO/Buffer depth = 32 datawords. + 0x4 + + + RXFIFOSIZE_5 + Receive FIFO/Buffer depth = 64 datawords. + 0x5 + + + RXFIFOSIZE_6 + Receive FIFO/Buffer depth = 128 datawords. + 0x6 + + + RXFIFOSIZE_7 + Receive FIFO/Buffer depth = 256 datawords. + 0x7 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + RXFE_0 + Receive FIFO is not enabled. Buffer is depth 1. + 0 + + + RXFE_1 + Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + 0x1 + + + + + TXFIFOSIZE + Transmit FIFO Buffer Depth + 4 + 3 + read-only + + + TXFIFOSIZE_0 + Transmit FIFO/Buffer depth = 1 dataword. + 0 + + + TXFIFOSIZE_1 + Transmit FIFO/Buffer depth = 4 datawords. + 0x1 + + + TXFIFOSIZE_2 + Transmit FIFO/Buffer depth = 8 datawords. + 0x2 + + + TXFIFOSIZE_3 + Transmit FIFO/Buffer depth = 16 datawords. + 0x3 + + + TXFIFOSIZE_4 + Transmit FIFO/Buffer depth = 32 datawords. + 0x4 + + + TXFIFOSIZE_5 + Transmit FIFO/Buffer depth = 64 datawords. + 0x5 + + + TXFIFOSIZE_6 + Transmit FIFO/Buffer depth = 128 datawords. + 0x6 + + + TXFIFOSIZE_7 + Transmit FIFO/Buffer depth = 256 datawords + 0x7 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + TXFE_0 + Transmit FIFO is not enabled. Buffer is depth 1. + 0 + + + TXFE_1 + Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + 0x1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + RXUFE_0 + RXUF flag does not generate an interrupt to the host. + 0 + + + RXUFE_1 + RXUF flag generates an interrupt to the host. + 0x1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + TXOFE_0 + TXOF flag does not generate an interrupt to the host. + 0 + + + TXOFE_1 + TXOF flag generates an interrupt to the host. + 0x1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + RXIDEN_0 + Disable RDRF assertion due to partially filled FIFO when receiver is idle. + 0 + + + RXIDEN_1 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + 0x1 + + + RXIDEN_2 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + 0x2 + + + RXIDEN_3 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + 0x3 + + + RXIDEN_4 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + 0x4 + + + RXIDEN_5 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + 0x5 + + + RXIDEN_6 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + 0x6 + + + RXIDEN_7 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + 0x7 + + + + + RXFLUSH + Receive FIFO/Buffer Flush + 14 + 1 + write-only + + + RXFLUSH_0 + No flush operation occurs. + 0 + + + RXFLUSH_1 + All data in the receive FIFO/buffer is cleared out. + 0x1 + + + + + TXFLUSH + Transmit FIFO/Buffer Flush + 15 + 1 + write-only + + + TXFLUSH_0 + No flush operation occurs. + 0 + + + TXFLUSH_1 + All data in the transmit FIFO/Buffer is cleared out. + 0x1 + + + + + RXUF + Receiver Buffer Underflow Flag + 16 + 1 + read-write + oneToClear + + + RXUF_0 + No receive buffer underflow has occurred since the last time the flag was cleared. + 0 + + + RXUF_1 + At least one receive buffer underflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TXOF + Transmitter Buffer Overflow Flag + 17 + 1 + read-write + oneToClear + + + TXOF_0 + No transmit buffer overflow has occurred since the last time the flag was cleared. + 0 + + + TXOF_1 + At least one transmit buffer overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RXEMPT + Receive Buffer/FIFO Empty + 22 + 1 + read-only + + + RXEMPT_0 + Receive buffer is not empty. + 0 + + + RXEMPT_1 + Receive buffer is empty. + 0x1 + + + + + TXEMPT + Transmit Buffer/FIFO Empty + 23 + 1 + read-only + + + TXEMPT_0 + Transmit buffer is not empty. + 0 + + + TXEMPT_1 + Transmit buffer is empty. + 0x1 + + + + + + + WATER + LPUART Watermark Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 2 + read-write + + + TXCOUNT + Transmit Counter + 8 + 3 + read-only + + + RXWATER + Receive Watermark + 16 + 2 + read-write + + + RXCOUNT + Receive Counter + 24 + 3 + read-only + + + + + + + LPUART2 + LPUART + LPUART + 0x40188000 + + 0 + 0x30 + registers + + + LPUART2 + 21 + + + + LPUART3 + LPUART + LPUART + 0x4018C000 + + 0 + 0x30 + registers + + + LPUART3 + 22 + + + + LPUART4 + LPUART + LPUART + 0x40190000 + + 0 + 0x30 + registers + + + LPUART4 + 23 + + + + LPUART5 + LPUART + LPUART + 0x40194000 + + 0 + 0x30 + registers + + + LPUART5 + 24 + + + + LPUART6 + LPUART + LPUART + 0x40198000 + + 0 + 0x30 + registers + + + LPUART6 + 25 + + + + LPUART7 + LPUART + LPUART + 0x4019C000 + + 0 + 0x30 + registers + + + LPUART7 + 26 + + + + LPUART8 + LPUART + LPUART + 0x401A0000 + + 0 + 0x30 + registers + + + LPUART8 + 27 + + + + FLEXIO1 + FLEXIO + FLEXIO + FLEXIO + 0x401AC000 + + 0 + 0x790 + registers + + + FLEXIO1 + 90 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard features implemented. + 0 + + + FEATURE_1 + Supports state, logic and parallel modes. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x2200404 + 0xFFFFFFFF + + + SHIFTER + Shifter Number + 0 + 8 + read-only + + + TIMER + Timer Number + 8 + 8 + read-only + + + PIN + Pin Number + 16 + 8 + read-only + + + TRIGGER + Trigger Number + 24 + 8 + read-only + + + + + CTRL + FlexIO Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXEN + FlexIO Enable + 0 + 1 + read-write + + + FLEXEN_0 + FlexIO module is disabled. + 0 + + + FLEXEN_1 + FlexIO module is enabled. + 0x1 + + + + + SWRST + Software Reset + 1 + 1 + read-write + + + SWRST_0 + Software reset is disabled + 0 + + + SWRST_1 + Software reset is enabled, all FlexIO registers except the Control Register are reset. + 0x1 + + + + + FASTACC + Fast Access + 2 + 1 + read-write + + + FASTACC_0 + Configures for normal register accesses to FlexIO + 0 + + + FASTACC_1 + Configures for fast register accesses to FlexIO + 0x1 + + + + + DBGE + Debug Enable + 30 + 1 + read-write + + + DBGE_0 + FlexIO is disabled in debug modes. + 0 + + + DBGE_1 + FlexIO is enabled in debug modes + 0x1 + + + + + DOZEN + Doze Enable + 31 + 1 + read-write + + + DOZEN_0 + FlexIO enabled in Doze modes. + 0 + + + DOZEN_1 + FlexIO disabled in Doze modes. + 0x1 + + + + + + + PIN + Pin State Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Pin Data Input + 0 + 32 + read-only + + + + + SHIFTSTAT + Shifter Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSF + Shifter Status Flag + 0 + 4 + read-write + oneToClear + + + + + SHIFTERR + Shifter Error Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEF + Shifter Error Flags + 0 + 4 + read-write + oneToClear + + + + + TIMSTAT + Timer Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSF + Timer Status Flags + 0 + 4 + read-write + oneToClear + + + + + SHIFTSIEN + Shifter Status Interrupt Enable + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIE + Shifter Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTEIEN + Shifter Error Interrupt Enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEIE + Shifter Error Interrupt Enable + 0 + 4 + read-write + + + + + TIMIEN + Timer Interrupt Enable Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIE + Timer Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTSDEN + Shifter Status DMA Enable + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSDE + Shifter Status DMA Enable + 0 + 4 + read-write + + + + + SHIFTSTATE + Shifter State Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STATE + Current State Pointer + 0 + 3 + read-write + + + + + 4 + 0x4 + SHIFTCTL[%s] + Shifter Control N Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMOD + Shifter Mode + 0 + 3 + read-write + + + SMOD_0 + Disabled. + 0 + + + SMOD_1 + Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + 0x1 + + + SMOD_2 + Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + 0x2 + + + SMOD_4 + Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + 0x4 + + + SMOD_5 + Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + 0x5 + + + SMOD_6 + no description available + 0x6 + + + SMOD_7 + no description available + 0x7 + + + + + PINPOL + Shifter Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Shifter Pin Select + 8 + 5 + read-write + + + PINCFG + Shifter Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Shifter pin output disabled + 0 + + + PINCFG_1 + Shifter pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Shifter pin bidirectional output data + 0x2 + + + PINCFG_3 + Shifter pin output + 0x3 + + + + + TIMPOL + Timer Polarity + 23 + 1 + read-write + + + TIMPOL_0 + Shift on posedge of Shift clock + 0 + + + TIMPOL_1 + Shift on negedge of Shift clock + 0x1 + + + + + TIMSEL + Timer Select + 24 + 2 + read-write + + + + + 4 + 0x4 + SHIFTCFG[%s] + Shifter Configuration N Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSTART + Shifter Start bit + 0 + 2 + read-write + + + SSTART_0 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + 0 + + + SSTART_1 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + 0x1 + + + SSTART_2 + Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + 0x2 + + + SSTART_3 + Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + 0x3 + + + + + SSTOP + Shifter Stop bit + 4 + 2 + read-write + + + SSTOP_0 + Stop bit disabled for transmitter/receiver/match store + 0 + + + SSTOP_2 + Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + 0x2 + + + SSTOP_3 + Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + 0x3 + + + + + INSRC + Input Source + 8 + 1 + read-write + + + INSRC_0 + Pin + 0 + + + INSRC_1 + Shifter N+1 Output + 0x1 + + + + + PWIDTH + Parallel Width + 16 + 5 + read-write + + + + + 4 + 0x4 + SHIFTBUF[%s] + Shifter Buffer N Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUF + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBIS[%s] + Shifter Buffer N Bit Swapped Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBIS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBYS[%s] + Shifter Buffer N Byte Swapped Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBYS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBBS[%s] + Shifter Buffer N Bit Byte Swapped Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + TIMCTL[%s] + Timer Control N Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMOD + Timer Mode + 0 + 2 + read-write + + + TIMOD_0 + Timer Disabled. + 0 + + + TIMOD_1 + Dual 8-bit counters baud mode. + 0x1 + + + TIMOD_2 + Dual 8-bit counters PWM high mode. + 0x2 + + + TIMOD_3 + Single 16-bit counter mode. + 0x3 + + + + + PINPOL + Timer Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Timer Pin Select + 8 + 5 + read-write + + + PINCFG + Timer Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Timer pin output disabled + 0 + + + PINCFG_1 + Timer pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Timer pin bidirectional output data + 0x2 + + + PINCFG_3 + Timer pin output + 0x3 + + + + + TRGSRC + Trigger Source + 22 + 1 + read-write + + + TRGSRC_0 + External trigger selected + 0 + + + TRGSRC_1 + Internal trigger selected + 0x1 + + + + + TRGPOL + Trigger Polarity + 23 + 1 + read-write + + + TRGPOL_0 + Trigger active high + 0 + + + TRGPOL_1 + Trigger active low + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 6 + read-write + + + + + 4 + 0x4 + TIMCFG[%s] + Timer Configuration N Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSTART + Timer Start Bit + 1 + 1 + read-write + + + TSTART_0 + Start bit disabled + 0 + + + TSTART_1 + Start bit enabled + 0x1 + + + + + TSTOP + Timer Stop Bit + 4 + 2 + read-write + + + TSTOP_0 + Stop bit disabled + 0 + + + TSTOP_1 + Stop bit is enabled on timer compare + 0x1 + + + TSTOP_2 + Stop bit is enabled on timer disable + 0x2 + + + TSTOP_3 + Stop bit is enabled on timer compare and timer disable + 0x3 + + + + + TIMENA + Timer Enable + 8 + 3 + read-write + + + TIMENA_0 + Timer always enabled + 0 + + + TIMENA_1 + Timer enabled on Timer N-1 enable + 0x1 + + + TIMENA_2 + Timer enabled on Trigger high + 0x2 + + + TIMENA_3 + Timer enabled on Trigger high and Pin high + 0x3 + + + TIMENA_4 + Timer enabled on Pin rising edge + 0x4 + + + TIMENA_5 + Timer enabled on Pin rising edge and Trigger high + 0x5 + + + TIMENA_6 + Timer enabled on Trigger rising edge + 0x6 + + + TIMENA_7 + Timer enabled on Trigger rising or falling edge + 0x7 + + + + + TIMDIS + Timer Disable + 12 + 3 + read-write + + + TIMDIS_0 + Timer never disabled + 0 + + + TIMDIS_1 + Timer disabled on Timer N-1 disable + 0x1 + + + TIMDIS_2 + Timer disabled on Timer compare (upper 8-bits match and decrement) + 0x2 + + + TIMDIS_3 + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + 0x3 + + + TIMDIS_4 + Timer disabled on Pin rising or falling edge + 0x4 + + + TIMDIS_5 + Timer disabled on Pin rising or falling edge provided Trigger is high + 0x5 + + + TIMDIS_6 + Timer disabled on Trigger falling edge + 0x6 + + + + + TIMRST + Timer Reset + 16 + 3 + read-write + + + TIMRST_0 + Timer never reset + 0 + + + TIMRST_2 + Timer reset on Timer Pin equal to Timer Output + 0x2 + + + TIMRST_3 + Timer reset on Timer Trigger equal to Timer Output + 0x3 + + + TIMRST_4 + Timer reset on Timer Pin rising edge + 0x4 + + + TIMRST_6 + Timer reset on Trigger rising edge + 0x6 + + + TIMRST_7 + Timer reset on Trigger rising or falling edge + 0x7 + + + + + TIMDEC + Timer Decrement + 20 + 2 + read-write + + + TIMDEC_0 + Decrement counter on FlexIO clock, Shift clock equals Timer output. + 0 + + + TIMDEC_1 + Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + 0x1 + + + TIMDEC_2 + Decrement counter on Pin input (both edges), Shift clock equals Pin input. + 0x2 + + + TIMDEC_3 + Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + 0x3 + + + + + TIMOUT + Timer Output + 24 + 2 + read-write + + + TIMOUT_0 + Timer output is logic one when enabled and is not affected by timer reset + 0 + + + TIMOUT_1 + Timer output is logic zero when enabled and is not affected by timer reset + 0x1 + + + TIMOUT_2 + Timer output is logic one when enabled and on timer reset + 0x2 + + + TIMOUT_3 + Timer output is logic zero when enabled and on timer reset + 0x3 + + + + + + + 4 + 0x4 + TIMCMP[%s] + Timer Compare N Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP + Timer Compare Value + 0 + 16 + read-write + + + + + 4 + 0x4 + SHIFTBUFNBS[%s] + Shifter Buffer N Nibble Byte Swapped Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFHWS[%s] + Shifter Buffer N Half Word Swapped Register + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHWS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFNIS[%s] + Shifter Buffer N Nibble Swapped Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNIS + Shift Buffer + 0 + 32 + read-write + + + + + + + FLEXIO2 + FLEXIO + FLEXIO + 0x401B0000 + + 0 + 0x790 + registers + + + FLEXIO2 + 91 + + + + GPIO1 + GPIO + GPIO + GPIO + 0x401B8000 + + 0 + 0x90 + registers + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + DR + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GDIR + 0 + 32 + read-write + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + PSR + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + ICR0 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + ICR1 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + ICR2 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + ICR3 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + ICR4 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + ICR5 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + ICR6 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + ICR7 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + ICR8 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + ICR9 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + ICR10 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + ICR11 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + ICR12 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + ICR13 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + ICR14 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + ICR15 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + ICR16 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + ICR17 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + ICR18 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + ICR19 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + ICR20 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + ICR21 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + ICR22 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + ICR23 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + ICR24 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + ICR25 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + ICR26 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + ICR27 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + ICR28 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + ICR29 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + ICR30 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + ICR31 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + IMR + 0 + 32 + read-write + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + ISR + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + GPIO_EDGE_SEL + 0 + 32 + read-write + + + + + DR_SET + GPIO data register SET + 0x84 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_SET + DR_SET + 0 + 32 + write-only + + + + + DR_CLEAR + GPIO data register CLEAR + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_CLEAR + DR_CLEAR + 0 + 32 + write-only + + + + + DR_TOGGLE + GPIO data register TOGGLE + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_TOGGLE + DR_TOGGLE + 0 + 32 + write-only + + + + + + + GPIO5 + GPIO + GPIO + 0x400C0000 + + 0 + 0x90 + registers + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + + GPIO2 + GPIO + GPIO + 0x401BC000 + + 0 + 0x90 + registers + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + + GPIO3 + GPIO + GPIO + 0x401C0000 + + 0 + 0x90 + registers + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + + GPIO4 + GPIO + GPIO + 0x401C4000 + + 0 + 0x90 + registers + + + GPIO4_Combined_0_15 + 86 + + + GPIO4_Combined_16_31 + 87 + + + + CAN1 + FLEXCAN + CAN + FLEXCAN1_ + CAN + 0x401D0000 + + 0 + 0x9E4 + registers + + + CAN1 + 36 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes + 0 + 7 + read-write + + + IDAM + This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below + 8 + 2 + read-write + + + IDAM_0 + Format A One full ID (standard or extended) per ID filter Table element. + 0 + + + IDAM_1 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + 0x1 + + + IDAM_2 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + 0x2 + + + IDAM_3 + Format D All frames rejected. + 0x3 + + + + + AEN + This bit is supplied for backwards compatibility reasons + 12 + 1 + read-write + + + AEN_0 + Abort disabled + 0 + + + AEN_1 + Abort enabled + 0x1 + + + + + LPRIOEN + This bit is provided for backwards compatibility reasons + 13 + 1 + read-write + + + LPRIOEN_0 + Local Priority disabled + 0 + + + LPRIOEN_1 + Local Priority enabled + 0x1 + + + + + IRMQ + This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK + 16 + 1 + read-write + + + IRMQ_0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + 0 + + + IRMQ_1 + Individual Rx masking and queue feature are enabled. + 0x1 + + + + + SRXDIS + This bit defines whether FlexCAN is allowed to receive frames transmitted by itself + 17 + 1 + read-write + + + SRXDIS_0 + Self reception enabled + 0 + + + SRXDIS_1 + Self reception disabled + 0x1 + + + + + WAKSRC + This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up + 19 + 1 + read-write + + + WAKSRC_0 + FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + 0 + + + WAKSRC_1 + FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + 0x1 + + + + + LPMACK + This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode + 20 + 1 + read-only + + + LPMACK_0 + FLEXCAN not in any of the low power modes + 0 + + + LPMACK_1 + FLEXCAN is either in Disable Mode, or Stop mode + 0x1 + + + + + WRNEN + When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register + 21 + 1 + read-write + + + WRNEN_0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + 0 + + + WRNEN_1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + 0x1 + + + + + SLFWAK + This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode + 22 + 1 + read-write + + + SLFWAK_0 + FLEXCAN Self Wake Up feature is disabled + 0 + + + SLFWAK_1 + FLEXCAN Self Wake Up feature is enabled + 0x1 + + + + + SUPV + This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode + 23 + 1 + read-write + + + SUPV_0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + 0 + + + SUPV_1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + 0x1 + + + + + FRZACK + This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped + 24 + 1 + read-only + + + FRZACK_0 + FLEXCAN not in Freeze Mode, prescaler running + 0 + + + FRZACK_1 + FLEXCAN in Freeze Mode, prescaler stopped + 0x1 + + + + + SOFTRST + When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers + 25 + 1 + read-write + + + SOFTRST_0 + No reset request + 0 + + + SOFTRST_1 + Reset the registers + 0x1 + + + + + WAKMSK + This bit enables the Wake Up Interrupt generation. + 26 + 1 + read-write + + + WAKMSK_0 + Wake Up Interrupt is disabled + 0 + + + WAKMSK_1 + Wake Up Interrupt is enabled + 0x1 + + + + + NOTRDY + This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode + 27 + 1 + read-only + + + NOTRDY_0 + FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + 0 + + + NOTRDY_1 + FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + 0x1 + + + + + HALT + Assertion of this bit puts the FLEXCAN module into Freeze Mode + 28 + 1 + read-write + + + HALT_0 + No Freeze Mode request. + 0 + + + HALT_1 + Enters Freeze Mode if the FRZ bit is asserted. + 0x1 + + + + + RFEN + This bit controls whether the Rx FIFO feature is enabled or not + 29 + 1 + read-write + + + RFEN_0 + FIFO not enabled + 0 + + + RFEN_1 + FIFO enabled + 0x1 + + + + + FRZ + The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level + 30 + 1 + read-write + + + FRZ_0 + Not enabled to enter Freeze Mode + 0 + + + FRZ_1 + Enabled to enter Freeze Mode + 0x1 + + + + + MDIS + This bit controls whether FLEXCAN is enabled or not + 31 + 1 + read-write + + + MDIS_0 + Enable the FLEXCAN module + 0 + + + MDIS_1 + Disable the FLEXCAN module + 0x1 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + This 3-bit field defines the length of the Propagation Segment in the bit time + 0 + 3 + read-write + + + LOM + This bit configures FLEXCAN to operate in Listen Only Mode + 3 + 1 + read-write + + + LOM_0 + Listen Only Mode is deactivated + 0 + + + LOM_1 + FLEXCAN module operates in Listen Only Mode + 0x1 + + + + + LBUF + This bit defines the ordering mechanism for Message Buffer transmission + 4 + 1 + read-write + + + LBUF_0 + Buffer with highest priority is transmitted first + 0 + + + LBUF_1 + Lowest number buffer is transmitted first + 0x1 + + + + + TSYN + This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0 + 5 + 1 + read-write + + + TSYN_0 + Timer Sync feature disabled + 0 + + + TSYN_1 + Timer Sync feature enabled + 0x1 + + + + + BOFFREC + This bit defines how FLEXCAN recovers from Bus Off state + 6 + 1 + read-write + + + BOFFREC_0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + 0 + + + BOFFREC_1 + Automatic recovering from Bus Off state disabled + 0x1 + + + + + SMP + This bit defines the sampling mode of CAN bits at the FLEXCAN_RX + 7 + 1 + read-write + + + SMP_0 + Just one sample is used to determine the bit value + 0 + + + SMP_1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + 0x1 + + + + + RWRNMSK + This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register + 10 + 1 + read-write + + + RWRNMSK_0 + Rx Warning Interrupt disabled + 0 + + + RWRNMSK_1 + Rx Warning Interrupt enabled + 0x1 + + + + + TWRNMSK + This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register + 11 + 1 + read-write + + + TWRNMSK_0 + Tx Warning Interrupt disabled + 0 + + + TWRNMSK_1 + Tx Warning Interrupt enabled + 0x1 + + + + + LPB + This bit configures FlexCAN to operate in Loop-Back Mode + 12 + 1 + read-write + + + LPB_0 + Loop Back disabled + 0 + + + LPB_1 + Loop Back enabled + 0x1 + + + + + ERRMSK + This bit provides a mask for the Error Interrupt. + 14 + 1 + read-write + + + ERRMSK_0 + Error interrupt disabled + 0 + + + ERRMSK_1 + Error interrupt enabled + 0x1 + + + + + BOFFMSK + This bit provides a mask for the Bus Off Interrupt. + 15 + 1 + read-write + + + BOFFMSK_0 + Bus Off interrupt disabled + 0 + + + BOFFMSK_1 + Bus Off interrupt enabled + 0x1 + + + + + PSEG2 + This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time + 16 + 3 + read-write + + + PSEG1 + This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time + 19 + 3 + read-write + + + RJW + This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period + 22 + 2 + read-write + + + PRESDIV + This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency + 24 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + TIMER + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG + These bits mask the Mailbox filter bits as shown in the figure above + 0 + 32 + read-write + + + MG_0 + the corresponding bit in the filter is "don't care" + 0 + + + MG_1 + The corresponding bit in the filter is checked against the one received + 0x1 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M + These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX14M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX14M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M + These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX15M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX15M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_ERR_COUNTER + Tx_Err_Counter + 0 + 8 + read-write + + + RX_ERR_COUNTER + Rx_Err_Counter + 8 + 8 + read-write + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm + 0 + 1 + read-write + + + WAKINT_0 + No such occurrence + 0 + + + WAKINT_1 + Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + 0x1 + + + + + ERRINT + This bit indicates that at least one of the Error Bits (bits 15-10) is set + 1 + 1 + read-write + + + ERRINT_0 + No such occurrence + 0 + + + ERRINT_1 + Indicates setting of any Error Bit in the Error and Status Register + 0x1 + + + + + BOFFINT + This bit is set when FLEXCAN enters 'Bus Off' state + 2 + 1 + read-write + + + BOFFINT_0 + No such occurrence + 0 + + + BOFFINT_1 + FLEXCAN module entered 'Bus Off' state + 0x1 + + + + + RX + This bit indicates if FlexCAN is receiving a message. Refer to . + 3 + 1 + read-only + + + RX_0 + FLEXCAN is receiving a message + 0 + + + RX_1 + FLEXCAN is transmitting a message + 0x1 + + + + + FLTCONF + If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive" + 4 + 2 + read-only + + + FLTCONF_0 + Error Active + 0 + + + FLTCONF_1 + Error Passive + 0x1 + + + FLTCONF_2 + Bus off + #1x + + + + + TX + This bit indicates if FLEXCAN is transmitting a message.Refer to . + 6 + 1 + read-only + + + TX_0 + FLEXCAN is receiving a message + 0 + + + TX_1 + FLEXCAN is transmitting a message + 0x1 + + + + + IDLE + This bit indicates when CAN bus is in IDLE state.Refer to . + 7 + 1 + read-only + + + IDLE_0 + No such occurrence + 0 + + + IDLE_1 + CAN bus is now IDLE + 0x1 + + + + + RXWRN + This bit indicates when repetitive errors are occurring during message reception. + 8 + 1 + read-only + + + RXWRN_0 + No such occurrence + 0 + + + RXWRN_1 + Rx_Err_Counter >= 96 + 0x1 + + + + + TXWRN + This bit indicates when repetitive errors are occurring during message transmission. + 9 + 1 + read-only + + + TXWRN_0 + No such occurrence + 0 + + + TXWRN_1 + TX_Err_Counter >= 96 + 0x1 + + + + + STFERR + This bit indicates that a Stuffing Error has been detected. + 10 + 1 + read-only + + + STFERR_0 + No such occurrence. + 0 + + + STFERR_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR + This bit indicates that a Form Error has been detected by the receiver node, i + 11 + 1 + read-only + + + FRMERR_0 + No such occurrence + 0 + + + FRMERR_1 + A Form Error occurred since last read of this register + 0x1 + + + + + CRCERR + This bit indicates that a CRC Error has been detected by the receiver node, i + 12 + 1 + read-only + + + CRCERR_0 + No such occurrence + 0 + + + CRCERR_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + ACKERR + This bit indicates that an Acknowledge Error has been detected by the transmitter node, i + 13 + 1 + read-only + + + ACKERR_0 + No such occurrence + 0 + + + ACKERR_1 + An ACK error occurred since last read of this register + 0x1 + + + + + BIT0ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 14 + 1 + read-only + + + BIT0ERR_0 + No such occurrence + 0 + + + BIT0ERR_1 + At least one bit sent as dominant is received as recessive + 0x1 + + + + + BIT1ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 15 + 1 + read-only + + + BIT1ERR_0 + No such occurrence + 0 + + + BIT1ERR_1 + At least one bit sent as recessive is received as dominant + 0x1 + + + + + RWRNINT + If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96 + 16 + 1 + read-write + + + RWRNINT_0 + No such occurrence + 0 + + + RWRNINT_1 + The Rx error counter transition from < 96 to >= 96 + 0x1 + + + + + TWRNINT + If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96 + 17 + 1 + read-write + + + TWRNINT_0 + No such occurrence + 0 + + + TWRNINT_1 + The Tx error counter transition from < 96 to >= 96 + 0x1 + + + + + SYNCH + This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process + 18 + 1 + read-only + + + SYNCH_0 + FlexCAN is not synchronized to the CAN bus + 0 + + + SYNCH_1 + FlexCAN is synchronized to the CAN bus + 0x1 + + + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHM + Each bit enables or disables the respective FLEXCAN Message Buffer (MB32 to MB63) Interrupt + 0 + 32 + read-write + + + BUFHM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFHM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFLM + Each bit enables or disables the respective FLEXCAN Message Buffer (MB0 to MB31) Interrupt + 0 + 32 + read-write + + + BUFLM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFLM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHI + Each bit flags the respective FLEXCAN Message Buffer (MB32 to MB63) interrupt. + 0 + 32 + read-write + + + BUFHI_0 + No such occurrence + 0 + + + BUFHI_1 + The corresponding buffer has successfully completed transmission or reception + 0x1 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4TO0I + If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 + 0 + 5 + read-write + + + BUF4TO0I_0 + No such occurrence + 0 + + + BUF4TO0I_1 + Corresponding MB completed transmission/reception + 0x1 + + + + + BUF5I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB5 + 5 + 1 + read-write + + + BUF5I_0 + No such occurrence + 0 + + + BUF5I_1 + MB5 completed transmission/reception or frames available in the FIFO + 0x1 + + + + + BUF6I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB6 + 6 + 1 + read-write + + + BUF6I_0 + No such occurrence + 0 + + + BUF6I_1 + MB6 completed transmission/reception or FIFO almost full + 0x1 + + + + + BUF7I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB7 + 7 + 1 + read-write + + + BUF7I_0 + No such occurrence + 0 + + + BUF7I_1 + MB7 completed transmission/reception or FIFO overflow + 0x1 + + + + + BUF31TO8I + Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt. + 8 + 24 + read-write + + + BUF31TO8I_0 + No such occurrence + 0 + + + BUF31TO8I_1 + The corresponding MB has successfully completed transmission or reception + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + EACEN + This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process + 16 + 1 + read-write + + + EACEN_0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + 0 + + + EACEN_1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + 0x1 + + + + + RRS + If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame + 17 + 1 + read-write + + + RRS_0 + Remote Response Frame is generated + 0 + + + RRS_1 + Remote Request Frame is stored + 0x1 + + + + + MRP + If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO + 18 + 1 + read-write + + + MRP_0 + Matching starts from Rx FIFO and continues on Mailboxes + 0 + + + MRP_1 + Matching starts from Mailboxes and continues on Rx FIFO + 0x1 + + + + + TASD + This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus + 19 + 5 + read-write + + + RFFN + This 4-bit field defines the number of Rx FIFO filters according to + 24 + 4 + read-write + + + WRMFRZ + Enable unrestricted write access to FlexCAN memory in Freeze mode + 28 + 1 + read-write + + + WRMFRZ_0 + Keep the write access restricted in some regions of FlexCAN memory + 0 + + + WRMFRZ_1 + Enable unrestricted write access to FlexCAN memory + 0x1 + + + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000) + 13 + 1 + read-only + + + IMB_0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + 0 + + + IMB_1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + 0x1 + + + + + VPS + This bit indicates whether IMB and LPTM contents are currently valid or not + 14 + 1 + read-only + + + VPS_0 + Contents of IMB and LPTM are invalid + 0 + + + VPS_1 + Contents of IMB and LPTM are valid + 0x1 + + + + + LPTM + If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description) + 16 + 7 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + This field indicates the CRC value of the last message transmitted + 0 + 15 + read-only + + + MBCRC + This field indicates the number of the Mailbox corresponding to the value in TXCRC field. + 16 + 7 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM + These bits mask the ID Filter Table elements bits in a perfect alignment + 0 + 32 + read-write + + + FGM_0 + The corresponding bit in the filter is "don't care" + 0 + + + FGM_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received message that is in the output of the Rx FIFO + 0 + 9 + read-only + + + + + CS0 + Message Buffer 0 CS Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID0 + Message Buffer 0 ID Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD00 + Message Buffer 0 WORD0 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD10 + Message Buffer 0 WORD1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS1 + Message Buffer 1 CS Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID1 + Message Buffer 1 ID Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD01 + Message Buffer 1 WORD0 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD11 + Message Buffer 1 WORD1 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS2 + Message Buffer 2 CS Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID2 + Message Buffer 2 ID Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD02 + Message Buffer 2 WORD0 Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD12 + Message Buffer 2 WORD1 Register + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS3 + Message Buffer 3 CS Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID3 + Message Buffer 3 ID Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD03 + Message Buffer 3 WORD0 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD13 + Message Buffer 3 WORD1 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS4 + Message Buffer 4 CS Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID4 + Message Buffer 4 ID Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD04 + Message Buffer 4 WORD0 Register + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD14 + Message Buffer 4 WORD1 Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS5 + Message Buffer 5 CS Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID5 + Message Buffer 5 ID Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD05 + Message Buffer 5 WORD0 Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD15 + Message Buffer 5 WORD1 Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS6 + Message Buffer 6 CS Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID6 + Message Buffer 6 ID Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD06 + Message Buffer 6 WORD0 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD16 + Message Buffer 6 WORD1 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS7 + Message Buffer 7 CS Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID7 + Message Buffer 7 ID Register + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD07 + Message Buffer 7 WORD0 Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD17 + Message Buffer 7 WORD1 Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS8 + Message Buffer 8 CS Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID8 + Message Buffer 8 ID Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD08 + Message Buffer 8 WORD0 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD18 + Message Buffer 8 WORD1 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS9 + Message Buffer 9 CS Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID9 + Message Buffer 9 ID Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD09 + Message Buffer 9 WORD0 Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD19 + Message Buffer 9 WORD1 Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS10 + Message Buffer 10 CS Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID10 + Message Buffer 10 ID Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD010 + Message Buffer 10 WORD0 Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD110 + Message Buffer 10 WORD1 Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS11 + Message Buffer 11 CS Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID11 + Message Buffer 11 ID Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD011 + Message Buffer 11 WORD0 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD111 + Message Buffer 11 WORD1 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS12 + Message Buffer 12 CS Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID12 + Message Buffer 12 ID Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD012 + Message Buffer 12 WORD0 Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD112 + Message Buffer 12 WORD1 Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS13 + Message Buffer 13 CS Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID13 + Message Buffer 13 ID Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD013 + Message Buffer 13 WORD0 Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD113 + Message Buffer 13 WORD1 Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS14 + Message Buffer 14 CS Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID14 + Message Buffer 14 ID Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD014 + Message Buffer 14 WORD0 Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD114 + Message Buffer 14 WORD1 Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS15 + Message Buffer 15 CS Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID15 + Message Buffer 15 ID Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD015 + Message Buffer 15 WORD0 Register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD115 + Message Buffer 15 WORD1 Register + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS16 + Message Buffer 16 CS Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID16 + Message Buffer 16 ID Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD016 + Message Buffer 16 WORD0 Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD116 + Message Buffer 16 WORD1 Register + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS17 + Message Buffer 17 CS Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID17 + Message Buffer 17 ID Register + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD017 + Message Buffer 17 WORD0 Register + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD117 + Message Buffer 17 WORD1 Register + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS18 + Message Buffer 18 CS Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID18 + Message Buffer 18 ID Register + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD018 + Message Buffer 18 WORD0 Register + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD118 + Message Buffer 18 WORD1 Register + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS19 + Message Buffer 19 CS Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID19 + Message Buffer 19 ID Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD019 + Message Buffer 19 WORD0 Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD119 + Message Buffer 19 WORD1 Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS20 + Message Buffer 20 CS Register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID20 + Message Buffer 20 ID Register + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD020 + Message Buffer 20 WORD0 Register + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD120 + Message Buffer 20 WORD1 Register + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS21 + Message Buffer 21 CS Register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID21 + Message Buffer 21 ID Register + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD021 + Message Buffer 21 WORD0 Register + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD121 + Message Buffer 21 WORD1 Register + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS22 + Message Buffer 22 CS Register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID22 + Message Buffer 22 ID Register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD022 + Message Buffer 22 WORD0 Register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD122 + Message Buffer 22 WORD1 Register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS23 + Message Buffer 23 CS Register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID23 + Message Buffer 23 ID Register + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD023 + Message Buffer 23 WORD0 Register + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD123 + Message Buffer 23 WORD1 Register + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS24 + Message Buffer 24 CS Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID24 + Message Buffer 24 ID Register + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD024 + Message Buffer 24 WORD0 Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD124 + Message Buffer 24 WORD1 Register + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS25 + Message Buffer 25 CS Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID25 + Message Buffer 25 ID Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD025 + Message Buffer 25 WORD0 Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD125 + Message Buffer 25 WORD1 Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS26 + Message Buffer 26 CS Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID26 + Message Buffer 26 ID Register + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD026 + Message Buffer 26 WORD0 Register + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD126 + Message Buffer 26 WORD1 Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS27 + Message Buffer 27 CS Register + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID27 + Message Buffer 27 ID Register + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD027 + Message Buffer 27 WORD0 Register + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD127 + Message Buffer 27 WORD1 Register + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS28 + Message Buffer 28 CS Register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID28 + Message Buffer 28 ID Register + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD028 + Message Buffer 28 WORD0 Register + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD128 + Message Buffer 28 WORD1 Register + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS29 + Message Buffer 29 CS Register + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID29 + Message Buffer 29 ID Register + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD029 + Message Buffer 29 WORD0 Register + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD129 + Message Buffer 29 WORD1 Register + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS30 + Message Buffer 30 CS Register + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID30 + Message Buffer 30 ID Register + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD030 + Message Buffer 30 WORD0 Register + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD130 + Message Buffer 30 WORD1 Register + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS31 + Message Buffer 31 CS Register + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID31 + Message Buffer 31 ID Register + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD031 + Message Buffer 31 WORD0 Register + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD131 + Message Buffer 31 WORD1 Register + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS32 + Message Buffer 32 CS Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID32 + Message Buffer 32 ID Register + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD032 + Message Buffer 32 WORD0 Register + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD132 + Message Buffer 32 WORD1 Register + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS33 + Message Buffer 33 CS Register + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID33 + Message Buffer 33 ID Register + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD033 + Message Buffer 33 WORD0 Register + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD133 + Message Buffer 33 WORD1 Register + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS34 + Message Buffer 34 CS Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID34 + Message Buffer 34 ID Register + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD034 + Message Buffer 34 WORD0 Register + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD134 + Message Buffer 34 WORD1 Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS35 + Message Buffer 35 CS Register + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID35 + Message Buffer 35 ID Register + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD035 + Message Buffer 35 WORD0 Register + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD135 + Message Buffer 35 WORD1 Register + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS36 + Message Buffer 36 CS Register + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID36 + Message Buffer 36 ID Register + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD036 + Message Buffer 36 WORD0 Register + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD136 + Message Buffer 36 WORD1 Register + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS37 + Message Buffer 37 CS Register + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID37 + Message Buffer 37 ID Register + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD037 + Message Buffer 37 WORD0 Register + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD137 + Message Buffer 37 WORD1 Register + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS38 + Message Buffer 38 CS Register + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID38 + Message Buffer 38 ID Register + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD038 + Message Buffer 38 WORD0 Register + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD138 + Message Buffer 38 WORD1 Register + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS39 + Message Buffer 39 CS Register + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID39 + Message Buffer 39 ID Register + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD039 + Message Buffer 39 WORD0 Register + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD139 + Message Buffer 39 WORD1 Register + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS40 + Message Buffer 40 CS Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID40 + Message Buffer 40 ID Register + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD040 + Message Buffer 40 WORD0 Register + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD140 + Message Buffer 40 WORD1 Register + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS41 + Message Buffer 41 CS Register + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID41 + Message Buffer 41 ID Register + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD041 + Message Buffer 41 WORD0 Register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD141 + Message Buffer 41 WORD1 Register + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS42 + Message Buffer 42 CS Register + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID42 + Message Buffer 42 ID Register + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD042 + Message Buffer 42 WORD0 Register + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD142 + Message Buffer 42 WORD1 Register + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS43 + Message Buffer 43 CS Register + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID43 + Message Buffer 43 ID Register + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD043 + Message Buffer 43 WORD0 Register + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD143 + Message Buffer 43 WORD1 Register + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS44 + Message Buffer 44 CS Register + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID44 + Message Buffer 44 ID Register + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD044 + Message Buffer 44 WORD0 Register + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD144 + Message Buffer 44 WORD1 Register + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS45 + Message Buffer 45 CS Register + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID45 + Message Buffer 45 ID Register + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD045 + Message Buffer 45 WORD0 Register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD145 + Message Buffer 45 WORD1 Register + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS46 + Message Buffer 46 CS Register + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID46 + Message Buffer 46 ID Register + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD046 + Message Buffer 46 WORD0 Register + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD146 + Message Buffer 46 WORD1 Register + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS47 + Message Buffer 47 CS Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID47 + Message Buffer 47 ID Register + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD047 + Message Buffer 47 WORD0 Register + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD147 + Message Buffer 47 WORD1 Register + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS48 + Message Buffer 48 CS Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID48 + Message Buffer 48 ID Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD048 + Message Buffer 48 WORD0 Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD148 + Message Buffer 48 WORD1 Register + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS49 + Message Buffer 49 CS Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID49 + Message Buffer 49 ID Register + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD049 + Message Buffer 49 WORD0 Register + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD149 + Message Buffer 49 WORD1 Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS50 + Message Buffer 50 CS Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID50 + Message Buffer 50 ID Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD050 + Message Buffer 50 WORD0 Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD150 + Message Buffer 50 WORD1 Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS51 + Message Buffer 51 CS Register + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID51 + Message Buffer 51 ID Register + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD051 + Message Buffer 51 WORD0 Register + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD151 + Message Buffer 51 WORD1 Register + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS52 + Message Buffer 52 CS Register + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID52 + Message Buffer 52 ID Register + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD052 + Message Buffer 52 WORD0 Register + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD152 + Message Buffer 52 WORD1 Register + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS53 + Message Buffer 53 CS Register + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID53 + Message Buffer 53 ID Register + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD053 + Message Buffer 53 WORD0 Register + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD153 + Message Buffer 53 WORD1 Register + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS54 + Message Buffer 54 CS Register + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID54 + Message Buffer 54 ID Register + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD054 + Message Buffer 54 WORD0 Register + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD154 + Message Buffer 54 WORD1 Register + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS55 + Message Buffer 55 CS Register + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID55 + Message Buffer 55 ID Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD055 + Message Buffer 55 WORD0 Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD155 + Message Buffer 55 WORD1 Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS56 + Message Buffer 56 CS Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID56 + Message Buffer 56 ID Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD056 + Message Buffer 56 WORD0 Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD156 + Message Buffer 56 WORD1 Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS57 + Message Buffer 57 CS Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID57 + Message Buffer 57 ID Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD057 + Message Buffer 57 WORD0 Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD157 + Message Buffer 57 WORD1 Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS58 + Message Buffer 58 CS Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID58 + Message Buffer 58 ID Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD058 + Message Buffer 58 WORD0 Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD158 + Message Buffer 58 WORD1 Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS59 + Message Buffer 59 CS Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID59 + Message Buffer 59 ID Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD059 + Message Buffer 59 WORD0 Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD159 + Message Buffer 59 WORD1 Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS60 + Message Buffer 60 CS Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID60 + Message Buffer 60 ID Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD060 + Message Buffer 60 WORD0 Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD160 + Message Buffer 60 WORD1 Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS61 + Message Buffer 61 CS Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID61 + Message Buffer 61 ID Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD061 + Message Buffer 61 WORD0 Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD161 + Message Buffer 61 WORD1 Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS62 + Message Buffer 62 CS Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID62 + Message Buffer 62 ID Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD062 + Message Buffer 62 WORD0 Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD162 + Message Buffer 62 WORD1 Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS63 + Message Buffer 63 CS Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Reserved + 24 + 4 + read-write + + + + + ID63 + Message Buffer 63 ID Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD063 + Message Buffer 63 WORD0 Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD163 + Message Buffer 63 WORD1 Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 24 + 8 + read-write + + + + + 64 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + RXIMR%s + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI + These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways + 0 + 32 + read-write + + + MI_0 + the corresponding bit in the filter is "don't care" + 0 + + + MI_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + It determines the Glitch Filter Width + 0 + 8 + read-write + + + + + + + CAN2 + FLEXCAN + CAN + FLEXCAN2_ + 0x401D4000 + + 0 + 0x9E4 + registers + + + CAN2 + 37 + + + + TMR1 + Quad Timer + TMR + TMR1_ + TMR + 0x401DC000 + + 0 + 0x7A + registers + + + TMR1 + 133 + + + + 4 + 0x20 + 0,1,2,3 + COMP1%s + Timer Channel Compare Register 1 + 0 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_1 + Comparison Value 1 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + COMP2%s + Timer Channel Compare Register 2 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_2 + Comparison Value 2 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CAPT%s + Timer Channel Capture Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CAPTURE + Capture Value + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + LOAD%s + Timer Channel Load Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + LOAD + Timer Load Register + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + HOLD%s + Timer Channel Hold Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + HOLD + This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CNTR%s + Timer Channel Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + COUNTER + This read/write register is the counter for the corresponding channel in a timer module. + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CTRL%s + Timer Channel Control Register + 0xC + 16 + read-write + 0 + 0xFFFF + + + OUTMODE + Output Mode + 0 + 3 + read-write + + + OUTMODE_0 + Asserted while counter is active + 0 + + + OUTMODE_1 + Clear OFLAG output on successful compare + 0x1 + + + OUTMODE_2 + Set OFLAG output on successful compare + 0x2 + + + OUTMODE_3 + Toggle OFLAG output on successful compare + 0x3 + + + OUTMODE_4 + Toggle OFLAG output using alternating compare registers + 0x4 + + + OUTMODE_5 + Set on compare, cleared on secondary source input edge + 0x5 + + + OUTMODE_6 + Set on compare, cleared on counter rollover + 0x6 + + + OUTMODE_7 + Enable gated clock output while counter is active + 0x7 + + + + + COINIT + Co-Channel Initialization + 3 + 1 + read-write + + + COINIT_0 + Co-channel counter/timers cannot force a re-initialization of this counter/timer + 0 + + + COINIT_1 + Co-channel counter/timers may force a re-initialization of this counter/timer + 0x1 + + + + + DIR + Count Direction + 4 + 1 + read-write + + + DIR_0 + Count up. + 0 + + + DIR_1 + Count down. + 0x1 + + + + + LENGTH + Count Length + 5 + 1 + read-write + + + LENGTH_0 + Count until roll over at $FFFF and continue from $0000. + 0 + + + LENGTH_1 + Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + 0x1 + + + + + ONCE + Count Once + 6 + 1 + read-write + + + ONCE_0 + Count repeatedly. + 0 + + + ONCE_1 + Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + 0x1 + + + + + SCS + Secondary Count Source + 7 + 2 + read-write + + + SCS_0 + Counter 0 input pin + 0 + + + SCS_1 + Counter 1 input pin + 0x1 + + + SCS_2 + Counter 2 input pin + 0x2 + + + SCS_3 + Counter 3 input pin + 0x3 + + + + + PCS + Primary Count Source + 9 + 4 + read-write + + + PCS_0 + Counter 0 input pin + 0 + + + PCS_1 + Counter 1 input pin + 0x1 + + + PCS_2 + Counter 2 input pin + 0x2 + + + PCS_3 + Counter 3 input pin + 0x3 + + + PCS_4 + Counter 0 output + 0x4 + + + PCS_5 + Counter 1 output + 0x5 + + + PCS_6 + Counter 2 output + 0x6 + + + PCS_7 + Counter 3 output + 0x7 + + + PCS_8 + IP bus clock divide by 1 prescaler + 0x8 + + + PCS_9 + IP bus clock divide by 2 prescaler + 0x9 + + + PCS_10 + IP bus clock divide by 4 prescaler + 0xA + + + PCS_11 + IP bus clock divide by 8 prescaler + 0xB + + + PCS_12 + IP bus clock divide by 16 prescaler + 0xC + + + PCS_13 + IP bus clock divide by 32 prescaler + 0xD + + + PCS_14 + IP bus clock divide by 64 prescaler + 0xE + + + PCS_15 + IP bus clock divide by 128 prescaler + 0xF + + + + + CM + Count Mode + 13 + 3 + read-write + + + CM_0 + No operation + 0 + + + CM_1 + Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + 0x1 + + + CM_2 + Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + 0x2 + + + CM_3 + Count rising edges of primary source while secondary input high active + 0x3 + + + CM_4 + Quadrature count mode, uses primary and secondary sources + 0x4 + + + CM_5 + Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + 0x5 + + + CM_6 + Edge of secondary source triggers primary count until compare + 0x6 + + + CM_7 + Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + 0x7 + + + + + + + 4 + 0x20 + 0,1,2,3 + SCTRL%s + Timer Channel Status and Control Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + OEN + Output Enable + 0 + 1 + read-write + + + OEN_0 + The external pin is configured as an input. + 0 + + + OEN_1 + The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + 0x1 + + + + + OPS + Output Polarity Select + 1 + 1 + read-write + + + OPS_0 + True polarity. + 0 + + + OPS_1 + Inverted polarity. + 0x1 + + + + + FORCE + Force OFLAG Output + 2 + 1 + write-only + + + VAL + Forced OFLAG Value + 3 + 1 + read-write + + + EEOF + Enable External OFLAG Force + 4 + 1 + read-write + + + MSTR + Master Mode + 5 + 1 + read-write + + + CAPTURE_MODE + Input Capture Mode + 6 + 2 + read-write + + + CAPTURE_MODE_0 + Capture function is disabled + 0 + + + CAPTURE_MODE_1 + Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + 0x1 + + + CAPTURE_MODE_2 + Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + 0x2 + + + CAPTURE_MODE_3 + Load capture register on both edges of input + 0x3 + + + + + INPUT + External Input Signal + 8 + 1 + read-only + + + IPS + Input Polarity Select + 9 + 1 + read-write + + + IEFIE + Input Edge Flag Interrupt Enable + 10 + 1 + read-write + + + IEF + Input Edge Flag + 11 + 1 + read-write + + + TOFIE + Timer Overflow Flag Interrupt Enable + 12 + 1 + read-write + + + TOF + Timer Overflow Flag + 13 + 1 + read-write + + + TCFIE + Timer Compare Flag Interrupt Enable + 14 + 1 + read-write + + + TCF + Timer Compare Flag + 15 + 1 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD1%s + Timer Channel Comparator Load Register 1 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_1 + This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD2%s + Timer Channel Comparator Load Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_2 + This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CSCTRL%s + Timer Channel Comparator Status and Control Register + 0x14 + 16 + read-write + 0 + 0xFFFF + + + CL1 + Compare Load Control 1 + 0 + 2 + read-write + + + CL1_0 + Never preload + 0 + + + CL1_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL1_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + CL2 + Compare Load Control 2 + 2 + 2 + read-write + + + CL2_0 + Never preload + 0 + + + CL2_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL2_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + TCF1 + Timer Compare 1 Interrupt Flag + 4 + 1 + read-write + + + TCF2 + Timer Compare 2 Interrupt Flag + 5 + 1 + read-write + + + TCF1EN + Timer Compare 1 Interrupt Enable + 6 + 1 + read-write + + + TCF2EN + Timer Compare 2 Interrupt Enable + 7 + 1 + read-write + + + UP + Counting Direction Indicator + 9 + 1 + read-only + + + UP_0 + The last count was in the DOWN direction. + 0 + + + UP_1 + The last count was in the UP direction. + 0x1 + + + + + TCI + Triggered Count Initialization Control + 10 + 1 + read-write + + + TCI_0 + Stop counter upon receiving a second trigger event while still counting from the first trigger event. + 0 + + + TCI_1 + Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + 0x1 + + + + + ROC + Reload on Capture + 11 + 1 + read-write + + + ROC_0 + Do not reload the counter on a capture event. + 0 + + + ROC_1 + Reload the counter on a capture event. + 0x1 + + + + + ALT_LOAD + Alternative Load Enable + 12 + 1 + read-write + + + ALT_LOAD_0 + Counter can be re-initialized only with the LOAD register. + 0 + + + ALT_LOAD_1 + Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + 0x1 + + + + + FAULT + Fault Enable + 13 + 1 + read-write + + + FAULT_0 + Fault function disabled. + 0 + + + FAULT_1 + Fault function enabled. + 0x1 + + + + + DBG_EN + Debug Actions Enable + 14 + 2 + read-write + + + DBG_EN_0 + Continue with normal operation during debug mode. (default) + 0 + + + DBG_EN_1 + Halt TMR counter during debug mode. + 0x1 + + + DBG_EN_2 + Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + 0x2 + + + DBG_EN_3 + Both halt counter and force output to 0 during debug mode. + 0x3 + + + + + + + 4 + 0x20 + 0,1,2,3 + FILT%s + Timer Channel Input Filter Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + DMA%s + Timer Channel DMA Enable Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + IEFDE + Input Edge Flag DMA Enable + 0 + 1 + read-write + + + CMPLD1DE + Comparator Preload Register 1 DMA Enable + 1 + 1 + read-write + + + CMPLD2DE + Comparator Preload Register 2 DMA Enable + 2 + 1 + read-write + + + + + ENBL + Timer Channel Enable Register + 0x1E + 16 + read-write + 0xF + 0xFFFF + + + ENBL + Timer Channel Enable + 0 + 4 + read-write + + + ENBL_0 + Timer channel is disabled. + 0 + + + ENBL_1 + Timer channel is enabled. (default) + 0x1 + + + + + + + + + TMR2 + Quad Timer + TMR + TMR2_ + 0x401E0000 + + 0 + 0x7A + registers + + + TMR2 + 134 + + + + TMR3 + Quad Timer + TMR + TMR3_ + 0x401E4000 + + 0 + 0x7A + registers + + + TMR3 + 135 + + + + TMR4 + Quad Timer + TMR + TMR4_ + 0x401E8000 + + 0 + 0x7A + registers + + + TMR4 + 136 + + + + GPT1 + GPT + GPT + GPT1_ + GPT + 0x401EC000 + + 0 + 0x28 + registers + + + GPT1 + 100 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 10 + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 15 + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 16 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 18 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 20 + 3 + read-write + + + OM2 + See OM3 + 23 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 26 + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + OM3_4 + Generate an active low pulse (that is one input clock wide) on the output pin. + #1xx + + + + + FO1 + See F03 + 29 + 1 + write-only + + + FO2 + See F03 + 30 + 1 + write-only + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 31 + 1 + write-only + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 12 + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x401F0000 + + 0 + 0x28 + registers + + + GPT2 + 101 + + + + OCOTP + no description available + OCOTP + 0x401F4000 + + 0 + 0x6F4 + registers + + + + HW_OCOTP_CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_OCOTP_CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_OCOTP_CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_OCOTP_CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_OCOTP_TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x60D9755 + 0xFFFFFFFF + + + STROBE_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX + This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd + 12 + 4 + read-write + + + STROBE_READ + This count value specifies the strobe period in one time read OTP + 16 + 6 + read-write + + + WAIT + This count value specifies time interval between auto read and write access in one time program + 22 + 6 + read-write + + + + + HW_OCOTP_DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Used to initiate a write to OTP + 0 + 32 + read-write + + + + + HW_OCOTP_READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + Used to initiate a read to OTP + 0 + 1 + read-write + + + + + HW_OCOTP_READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The data read from OTP + 0 + 32 + read-write + + + + + HW_OCOTP_SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLOCK_DTCP_KEY + Shadow register read and OTP read lock for DTCP_KEY region + 0 + 1 + read-write + + + SRK_REVOKE_LOCK + Shadow register write and OTP write lock for SRK_REVOKE region + 1 + 1 + read-write + + + FIELD_RETURN_LOCK + Shadow register write and OTP write lock for FIELD_RETURN region + 2 + 1 + read-write + + + BLOCK_ROM_PART + Set by ARM during Boot after DTCP is initialized and before test mode entry, if ROM_PART_LOCK=1 + 3 + 1 + read-write + + + JTAG_BLOCK_RELEASE + Set by ARM during Boot after DTCP is initialized and before test mode entry + 4 + 1 + read-write + + + + + HW_OCOTP_SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_OCOTP_SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_OCOTP_SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_OCOTP_SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_OCOTP_VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + HW_OCOTP_TIMING2 + OTP Controller Timing Register 2 + 0x100 + 32 + read-write + 0x1C30092 + 0xFFFFFFFF + + + RELAX_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX_READ + This count value specifies the strobe period in one time read OTP + 16 + 6 + read-write + + + RELAX1 + This count value specifies time interval between auto read and write access in one time program + 22 + 7 + read-write + + + + + HW_OCOTP_LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TESTER + Status of shadow register and OTP write lock for tester region + 0 + 2 + read-only + + + BOOT_CFG + Status of shadow register and OTP write lock for boot_cfg region + 2 + 2 + read-only + + + MEM_TRIM + Status of shadow register and OTP write lock for mem_trim region + 4 + 2 + read-only + + + SJC_RESP + Status of shadow register read and write, OTP read and write lock for sjc_resp region + 6 + 1 + read-only + + + MAC_ADDR + Status of shadow register and OTP write lock for mac_addr region + 8 + 2 + read-only + + + GP1 + Status of shadow register and OTP write lock for gp1 region + 10 + 2 + read-only + + + GP2 + Status of shadow register and OTP write lock for gp2 region + 12 + 2 + read-only + + + SRK + Status of shadow register and OTP write lock for srk region + 14 + 1 + read-only + + + OTPMK_MSB + Status of shadow register read and write, OTP read and write lock for otpmk region (MSB) + 15 + 1 + read-only + + + SW_GP1 + Status of shadow register and OTP write lock for sw_gp1 region + 16 + 1 + read-only + + + OTPMK_LSB + Status of shadow register read and write, OTP read and write lock for otpmk region (LSB) + 17 + 1 + read-only + + + ANALOG + Status of shadow register and OTP write lock for analog region + 18 + 2 + read-only + + + OTPMK_CRC + Status of shadow register and OTP write lock for otpmk_crc region + 20 + 1 + read-only + + + SW_GP2_LOCK + Status of shadow register and OTP write lock for sw_gp2 region + 21 + 1 + read-only + + + MISC_CONF + Status of shadow register and OTP write lock for misc_conf region + 22 + 1 + read-only + + + SW_GP2_RLOCK + Status of shadow register and OTP read lock for sw_gp2 region + 23 + 1 + read-only + + + GP3 + Status of shadow register and OTP write lock for gp3 region + 26 + 2 + read-only + + + FIELD_RETURN + Reserved + 28 + 4 + read-write + + + + + HW_OCOTP_CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + HW_OCOTP_CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + HW_OCOTP_CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 4 (ADDR = 0x04) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 5 (ADDR = 0x05) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 6 (ADDR = 0x06) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 7 (ADDR = 0x07) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 0 (ADDR = 0x08) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 1 (ADDR = 0x09) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 2 (ADDR = 0x0A) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 3 (ADDR = 0x0B) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM4 + Value of OTP Bank1 Word4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 4 (ADDR = 0x0C) + 0 + 32 + read-write + + + + + HW_OCOTP_ANA0 + Value of OTP Bank1 Word5 (Analog Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 5 (ADDR = 0x0D) + 0 + 32 + read-write + + + + + HW_OCOTP_ANA1 + Value of OTP Bank1 Word6 (Analog Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 6 (ADDR = 0x0E) + 0 + 32 + read-write + + + + + HW_OCOTP_ANA2 + Value of OTP Bank1 Word7 (Analog Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 7 (ADDR = 0x0F) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x1C)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x1D)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1E)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1F)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x20)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x21)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x22)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x23)) + 0 + 32 + read-write + + + + + HW_OCOTP_SJC_RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)) + 0 + 32 + read-write + + + + + HW_OCOTP_SJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)) + 0 + 32 + read-write + + + + + HW_OCOTP_MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). + 0 + 32 + read-write + + + + + HW_OCOTP_MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). + 0 + 32 + read-write + + + + + HW_OCOTP_GP3 + Value of OTP Bank4 Word4 (MAC Address) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). + 0 + 32 + read-write + + + + + HW_OCOTP_GP1 + Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). + 0 + 32 + read-write + + + + + HW_OCOTP_GP2 + Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP1 + Value of OTP Bank5 Word0 (SW GP1) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP20 + Value of OTP Bank5 Word1 (SW GP2) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP21 + Value of OTP Bank5 Word2 (SW GP2) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP22 + Value of OTP Bank5 Word3 (SW GP2) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP23 + Value of OTP Bank5 Word4 (SW GP2) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). + 0 + 32 + read-write + + + + + HW_OCOTP_MISC_CONF0 + Value of OTP Bank5 Word5 (Misc Conf) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). + 0 + 32 + read-write + + + + + HW_OCOTP_MISC_CONF1 + Value of OTP Bank5 Word6 (Misc Conf) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). + 0 + 32 + read-write + + + + + HW_OCOTP_SRK_REVOKE + Value of OTP Bank5 Word7 (SRK Revoke) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). + 0 + 32 + read-write + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x401F8000 + + 0 + 0x65C + registers + + + + SW_MUX_CTL_PAD_GPIO_EMC_00 + SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register + 0x14 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_01 + SW_MUX_CTL_PAD_GPIO_EMC_01 SW MUX Control Register + 0x18 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB00 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO01 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_02 + SW_MUX_CTL_PAD_GPIO_EMC_02 SW MUX Control Register + 0x1C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA02 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SDO of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO02 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_03 + SW_MUX_CTL_PAD_GPIO_EMC_03 SW MUX Control Register + 0x20 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA03 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB01 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SDI of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO03 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_04 + SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register + 0x24 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_05 + SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register + 0x28 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB02 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_06 + SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register + 0x2C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_07 + SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register + 0x30 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_08 + SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register + 0x34 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_09 + SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register + 0x38 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_10 + SW_MUX_CTL_PAD_GPIO_EMC_10 SW MUX Control Register + 0x3C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA02 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO10 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_11 + SW_MUX_CTL_PAD_GPIO_EMC_11 SW MUX Control Register + 0x40 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB02 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C4_SDA of instance: lpi2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO11 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_12 + SW_MUX_CTL_PAD_GPIO_EMC_12 SW MUX Control Register + 0x44 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C4_SCL of instance: lpi2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USDHC1_WP of instance: usdhc1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_13 + SW_MUX_CTL_PAD_GPIO_EMC_13 SW MUX Control Register + 0x48 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR04 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: MQS_RIGHT of instance: mqs + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_14 + SW_MUX_CTL_PAD_GPIO_EMC_14 SW MUX Control Register + 0x4C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR05 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT19 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: MQS_LEFT of instance: mqs + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS1 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_15 + SW_MUX_CTL_PAD_GPIO_EMC_15 SW MUX Control Register + 0x50 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR06 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN20 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER0 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_16 + SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register + 0x54 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR07 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN21 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER1 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_16 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_17 + SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register + 0x58 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR08 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_CTS_B of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER2 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_17 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_18 + SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register + 0x5C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_18 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_19 + SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RDATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER0 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_19 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_20 + SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR12 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RDATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER1 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_20 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_21 + SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_BA0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA03 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TDATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER2 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_21 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_22 + SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_BA1 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB03 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TDATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER3 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_22 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_23 + SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR10 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_TX of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_23 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_24 + SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CAS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_RX of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_24 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_25 + SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_RAS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_REF_CLK of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_25 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_26 + SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CLK of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO12 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_26 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_27 + SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CKE of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_RTS_B of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SCK of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO13 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_27 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_28 + SW_MUX_CTL_PAD_GPIO_EMC_28 SW MUX Control Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_WE of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_CTS_B of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SDO of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO14 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_28 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_29 + SW_MUX_CTL_PAD_GPIO_EMC_29 SW MUX Control Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CS0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA00 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RTS_B of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SDI of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO15 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO29 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_29 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_30 + SW_MUX_CTL_PAD_GPIO_EMC_30 SW MUX Control Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA08 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB00 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_CTS_B of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA23 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO30 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_30 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_31 + SW_MUX_CTL_PAD_GPIO_EMC_31 SW MUX Control Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA09 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA01 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_PCS1 of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA22 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO31 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_31 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_32 + SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA10 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB01 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA21 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_32 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_33 + SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA02 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA20 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_33 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_34 + SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA12 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB02 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA19 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_34 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_35 + SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA13 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT18 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA18 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_35 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_36 + SW_MUX_CTL_PAD_GPIO_EMC_36 SW MUX Control Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA14 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN22 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA17 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_36 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_37 + SW_MUX_CTL_PAD_GPIO_EMC_37 SW MUX Control Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA15 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN23 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA16 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_37 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_38 + SW_MUX_CTL_PAD_GPIO_EMC_38 SW MUX Control Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DM01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_FIELD of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_38 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_39 + SW_MUX_CTL_PAD_GPIO_EMC_39 SW MUX Control Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DQS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_39 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_40 + SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_RDY of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: lpspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_OC of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_MDC of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_40 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_41 + SW_MUX_CTL_PAD_GPIO_EMC_41 SW MUX Control Register + 0xB8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CSX00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI1_PCS3 of instance: lpspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_PWR of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_41 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_00 + SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register + 0xBC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: REF_CLK_32K of instance: xtalosc + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_ID of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPI2C1_SCLS of instance: lpi2c1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SCK of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_01 + SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register + 0xC0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: REF_CLK_24M of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_ID of instance: anatop + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPI2C1_SDAS of instance: lpi2c1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: EWM_OUT_B of instance: ewm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SDO of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_02 + SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register + 0xC4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXCAN2_TX of instance: flexcan2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX00 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: lpi2c1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SDI of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_03 + SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register + 0xC8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_04 + SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_05 + SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_06 + SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TMS of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_CLK of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT18 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS3 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_07 + SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TCK of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_ER of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT19 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT3_OUT of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_08 + SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MOD of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_DATA03 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN20 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT3_IN of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_09 + SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_DATA02 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN21 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: GPT2_CLK of instance: gpt2 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_10 + SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_CRS of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_MCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN22 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_11 + SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_COL of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN23 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_12 + SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_13 + SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX03 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_14 + SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_CTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_15 + SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_00 + SW_MUX_CTL_PAD_GPIO_AD_B1_00 SW MUX Control Register + 0xFC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: lpi2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_B of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW07 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_01 + SW_MUX_CTL_PAD_GPIO_AD_B1_01 SW MUX Control Register + 0x100 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_02 + SW_MUX_CTL_PAD_GPIO_AD_B1_02 SW MUX Control Register + 0x104 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_1588_EVENT2_OUT of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_03 + SW_MUX_CTL_PAD_GPIO_AD_B1_03 SW MUX Control Register + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_1588_EVENT2_IN of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL06 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_04 + SW_MUX_CTL_PAD_GPIO_AD_B1_04 SW MUX Control Register + 0x10C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA03 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET_MDC of instance: enet + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_SR_CLK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_PIXCLK of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW05 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_05 + SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register + 0x110 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA02 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET_MDIO of instance: enet + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_MCLK of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL05 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_06 + SW_MUX_CTL_PAD_GPIO_AD_B1_06 SW MUX Control Register + 0x114 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA01 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_LOCK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW04 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_07 + SW_MUX_CTL_PAD_GPIO_AD_B1_07 SW MUX Control Register + 0x118 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA00 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_EXT_CLK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL04 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_08 + SW_MUX_CTL_PAD_GPIO_AD_B1_08 SW MUX Control Register + 0x11C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_SS1_B of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_PMIC_READY of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CMD of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW03 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_09 + SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register + 0x120 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DQS of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CLK of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL03 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_10 + SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA03 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_B of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW02 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_11 + SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA02 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: EWM_OUT_B of instance: ewm + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL02 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_12 + SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA01 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT00 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_PCS0 of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW01 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_13 + SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA00 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT01 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SDI of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL01 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_14 + SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_SCLK of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT02 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SDO of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW00 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_15 + SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_SS0_B of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT03 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SCK of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL00 of instance: kpp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_00 + SW_MUX_CTL_PAD_GPIO_B0_00 SW MUX Control Register + 0x13C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_CLK of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER0 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: MQS_RIGHT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_PCS0 of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO00 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX01 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_01 + SW_MUX_CTL_PAD_GPIO_B0_01 SW MUX Control Register + 0x140 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_ENABLE of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER1 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: MQS_LEFT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SDI of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO01 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX02 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_02 + SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register + 0x144 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_HSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER2 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SDO of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO02 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX03 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_03 + SW_MUX_CTL_PAD_GPIO_B0_03 SW MUX Control Register + 0x148 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_VSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER0 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SCK of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO03 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: WDOG2_RESET_B_DEB of instance: wdog2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_04 + SW_MUX_CTL_PAD_GPIO_B0_04 SW MUX Control Register + 0x14C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA00 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER1 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE00 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO04 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG00 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_05 + SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register + 0x150 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA01 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER2 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE01 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO05 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG01 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_06 + SW_MUX_CTL_PAD_GPIO_B0_06 SW MUX Control Register + 0x154 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA02 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE02 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO06 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG02 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_07 + SW_MUX_CTL_PAD_GPIO_B0_07 SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA03 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_CM7_TRACE03 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO07 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG03 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_08 + SW_MUX_CTL_PAD_GPIO_B0_08 SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA04 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPUART3_TX of instance: lpuart3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO08 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG04 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_09 + SW_MUX_CTL_PAD_GPIO_B0_09 SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA05 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER0 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPUART3_RX of instance: lpuart3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO09 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG05 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_10 + SW_MUX_CTL_PAD_GPIO_B0_10 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA06 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER1 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA02 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO10 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG06 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_11 + SW_MUX_CTL_PAD_GPIO_B0_11 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA07 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER2 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB02 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO11 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG07 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_12 + SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA08 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO12 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG08 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_13 + SW_MUX_CTL_PAD_GPIO_B0_13 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA09 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TRACE_SWO of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO13 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG09 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_14 + SW_MUX_CTL_PAD_GPIO_B0_14 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA10 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT12 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO14 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG10 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_15 + SW_MUX_CTL_PAD_GPIO_B0_15 SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA11 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT13 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO15 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG11 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_00 + SW_MUX_CTL_PAD_GPIO_B1_00 SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA12 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO16 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_01 + SW_MUX_CTL_PAD_GPIO_B1_01 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA13 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO17 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_02 + SW_MUX_CTL_PAD_GPIO_B1_02 SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA14 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI4_PCS2 of instance: lpspi4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO18 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_03 + SW_MUX_CTL_PAD_GPIO_B1_03 SW MUX Control Register + 0x188 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA15 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI4_PCS1 of instance: lpspi4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO19 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_04 + SW_MUX_CTL_PAD_GPIO_B1_04 SW MUX Control Register + 0x18C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA16 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_PCS0 of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA15 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO20 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_05 + SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register + 0x190 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA17 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SDI of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA14 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO21 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_06 + SW_MUX_CTL_PAD_GPIO_B1_06 SW MUX Control Register + 0x194 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA18 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SDO of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA13 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO22 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_07 + SW_MUX_CTL_PAD_GPIO_B1_07 SW MUX Control Register + 0x198 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA19 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SCK of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA12 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO23 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_08 + SW_MUX_CTL_PAD_GPIO_B1_08 SW MUX Control Register + 0x19C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA20 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER3 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA11 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO24 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO24 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_09 + SW_MUX_CTL_PAD_GPIO_B1_09 SW MUX Control Register + 0x1A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA21 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER3 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA10 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO25 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO25 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_10 + SW_MUX_CTL_PAD_GPIO_B1_10 SW MUX Control Register + 0x1A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA22 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA00 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO26 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO26 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_REF_CLK of instance: enet + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_11 + SW_MUX_CTL_PAD_GPIO_B1_11 SW MUX Control Register + 0x1A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA23 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER3 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA01 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO27 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO27 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: LPSPI4_PCS3 of instance: lpspi4 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_12 + SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register + 0x1AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPUART5_TX of instance: lpuart5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_PIXCLK of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO28 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO28 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_13 + SW_MUX_CTL_PAD_GPIO_B1_13 SW MUX Control Register + 0x1B0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: WDOG1_B of instance: wdog1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPUART5_RX of instance: lpuart5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_VSYNC of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO29 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO29 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_14 + SW_MUX_CTL_PAD_GPIO_B1_14 SW MUX Control Register + 0x1B4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET_MDC of instance: enet + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_HSYNC of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN02 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO30 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO30 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_15 + SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register + 0x1B8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET_MDIO of instance: enet + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_MCLK of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO31 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO31 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_00 + SW_MUX_CTL_PAD_GPIO_SD_B0_00 SW MUX Control Register + 0x1BC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SCK of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXSPIA_SS1_B of instance: flexspi + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_01 + SW_MUX_CTL_PAD_GPIO_SD_B0_01 SW MUX Control Register + 0x1C0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXSPIB_SS1_B of instance: flexspi + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_02 + SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register + 0x1C4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_CTS_B of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SDO of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_03 + SW_MUX_CTL_PAD_GPIO_SD_B0_03 SW MUX Control Register + 0x1C8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RTS_B of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SDI of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_04 + SW_MUX_CTL_PAD_GPIO_SD_B0_04 SW MUX Control Register + 0x1CC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_05 + SW_MUX_CTL_PAD_GPIO_SD_B0_05 SW MUX Control Register + 0x1D0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIB_DQS of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_00 + SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register + 0x1D4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA03 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPUART4_TX of instance: lpuart4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_01 + SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register + 0x1D8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA02 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPUART4_RX of instance: lpuart4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_02 + SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register + 0x1DC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA01 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_03 + SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register + 0x1E0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA00 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_PMIC_READY of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_04 + SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register + 0x1E4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_SCLK of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C1_SCL of instance: lpi2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIA_SS1_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_05 + SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register + 0x1E8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_CMD of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DQS of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C1_SDA of instance: lpi2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_06 + SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register + 0x1EC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_SS0_B of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_CTS_B of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_07 + SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register + 0x1F0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_SCLK of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_08 + SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register + 0x1F4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA4 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA00 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SD0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX02 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_09 + SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register + 0x1F8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA01 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_10 + SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register + 0x1FC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA02 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_11 + SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register + 0x200 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA03 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_11 + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_00 + SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register + 0x204 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_01 + SW_PAD_CTL_PAD_GPIO_EMC_01 SW PAD Control Register + 0x208 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_02 + SW_PAD_CTL_PAD_GPIO_EMC_02 SW PAD Control Register + 0x20C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_03 + SW_PAD_CTL_PAD_GPIO_EMC_03 SW PAD Control Register + 0x210 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_04 + SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register + 0x214 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_05 + SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register + 0x218 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_06 + SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register + 0x21C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_07 + SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register + 0x220 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_08 + SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register + 0x224 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_09 + SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register + 0x228 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_10 + SW_PAD_CTL_PAD_GPIO_EMC_10 SW PAD Control Register + 0x22C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_11 + SW_PAD_CTL_PAD_GPIO_EMC_11 SW PAD Control Register + 0x230 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_12 + SW_PAD_CTL_PAD_GPIO_EMC_12 SW PAD Control Register + 0x234 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_13 + SW_PAD_CTL_PAD_GPIO_EMC_13 SW PAD Control Register + 0x238 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_14 + SW_PAD_CTL_PAD_GPIO_EMC_14 SW PAD Control Register + 0x23C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_15 + SW_PAD_CTL_PAD_GPIO_EMC_15 SW PAD Control Register + 0x240 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_16 + SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register + 0x244 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_17 + SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register + 0x248 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_18 + SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register + 0x24C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_19 + SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register + 0x250 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_20 + SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register + 0x254 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_21 + SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register + 0x258 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_22 + SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register + 0x25C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_23 + SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register + 0x260 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_24 + SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register + 0x264 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_25 + SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register + 0x268 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_26 + SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register + 0x26C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_27 + SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register + 0x270 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_28 + SW_PAD_CTL_PAD_GPIO_EMC_28 SW PAD Control Register + 0x274 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_29 + SW_PAD_CTL_PAD_GPIO_EMC_29 SW PAD Control Register + 0x278 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_30 + SW_PAD_CTL_PAD_GPIO_EMC_30 SW PAD Control Register + 0x27C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_31 + SW_PAD_CTL_PAD_GPIO_EMC_31 SW PAD Control Register + 0x280 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_32 + SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register + 0x284 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_33 + SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register + 0x288 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_34 + SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register + 0x28C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_35 + SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register + 0x290 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_36 + SW_PAD_CTL_PAD_GPIO_EMC_36 SW PAD Control Register + 0x294 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_37 + SW_PAD_CTL_PAD_GPIO_EMC_37 SW PAD Control Register + 0x298 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_38 + SW_PAD_CTL_PAD_GPIO_EMC_38 SW PAD Control Register + 0x29C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_39 + SW_PAD_CTL_PAD_GPIO_EMC_39 SW PAD Control Register + 0x2A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_40 + SW_PAD_CTL_PAD_GPIO_EMC_40 SW PAD Control Register + 0x2A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_41 + SW_PAD_CTL_PAD_GPIO_EMC_41 SW PAD Control Register + 0x2A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_00 + SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register + 0x2AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_01 + SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register + 0x2B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_02 + SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register + 0x2B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_03 + SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register + 0x2B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_04 + SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register + 0x2BC + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_05 + SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register + 0x2C0 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_06 + SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register + 0x2C4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_07 + SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register + 0x2C8 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_08 + SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register + 0x2CC + 32 + read-write + 0xB0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_09 + SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register + 0x2D0 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_10 + SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register + 0x2D4 + 32 + read-write + 0x90B1 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_11 + SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register + 0x2D8 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_12 + SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register + 0x2DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_13 + SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register + 0x2E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_14 + SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register + 0x2E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_15 + SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register + 0x2E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_00 + SW_PAD_CTL_PAD_GPIO_AD_B1_00 SW PAD Control Register + 0x2EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_01 + SW_PAD_CTL_PAD_GPIO_AD_B1_01 SW PAD Control Register + 0x2F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_02 + SW_PAD_CTL_PAD_GPIO_AD_B1_02 SW PAD Control Register + 0x2F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_03 + SW_PAD_CTL_PAD_GPIO_AD_B1_03 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_04 + SW_PAD_CTL_PAD_GPIO_AD_B1_04 SW PAD Control Register + 0x2FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_05 + SW_PAD_CTL_PAD_GPIO_AD_B1_05 SW PAD Control Register + 0x300 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_06 + SW_PAD_CTL_PAD_GPIO_AD_B1_06 SW PAD Control Register + 0x304 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_07 + SW_PAD_CTL_PAD_GPIO_AD_B1_07 SW PAD Control Register + 0x308 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_08 + SW_PAD_CTL_PAD_GPIO_AD_B1_08 SW PAD Control Register + 0x30C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_09 + SW_PAD_CTL_PAD_GPIO_AD_B1_09 SW PAD Control Register + 0x310 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_10 + SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register + 0x314 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_11 + SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register + 0x318 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_12 + SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register + 0x31C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_13 + SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register + 0x320 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_14 + SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register + 0x324 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_15 + SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register + 0x328 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_00 + SW_PAD_CTL_PAD_GPIO_B0_00 SW PAD Control Register + 0x32C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_01 + SW_PAD_CTL_PAD_GPIO_B0_01 SW PAD Control Register + 0x330 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_02 + SW_PAD_CTL_PAD_GPIO_B0_02 SW PAD Control Register + 0x334 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_03 + SW_PAD_CTL_PAD_GPIO_B0_03 SW PAD Control Register + 0x338 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_04 + SW_PAD_CTL_PAD_GPIO_B0_04 SW PAD Control Register + 0x33C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_05 + SW_PAD_CTL_PAD_GPIO_B0_05 SW PAD Control Register + 0x340 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_06 + SW_PAD_CTL_PAD_GPIO_B0_06 SW PAD Control Register + 0x344 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_07 + SW_PAD_CTL_PAD_GPIO_B0_07 SW PAD Control Register + 0x348 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_08 + SW_PAD_CTL_PAD_GPIO_B0_08 SW PAD Control Register + 0x34C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_09 + SW_PAD_CTL_PAD_GPIO_B0_09 SW PAD Control Register + 0x350 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_10 + SW_PAD_CTL_PAD_GPIO_B0_10 SW PAD Control Register + 0x354 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_11 + SW_PAD_CTL_PAD_GPIO_B0_11 SW PAD Control Register + 0x358 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_12 + SW_PAD_CTL_PAD_GPIO_B0_12 SW PAD Control Register + 0x35C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_13 + SW_PAD_CTL_PAD_GPIO_B0_13 SW PAD Control Register + 0x360 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_14 + SW_PAD_CTL_PAD_GPIO_B0_14 SW PAD Control Register + 0x364 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_15 + SW_PAD_CTL_PAD_GPIO_B0_15 SW PAD Control Register + 0x368 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_00 + SW_PAD_CTL_PAD_GPIO_B1_00 SW PAD Control Register + 0x36C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_01 + SW_PAD_CTL_PAD_GPIO_B1_01 SW PAD Control Register + 0x370 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_02 + SW_PAD_CTL_PAD_GPIO_B1_02 SW PAD Control Register + 0x374 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_03 + SW_PAD_CTL_PAD_GPIO_B1_03 SW PAD Control Register + 0x378 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_04 + SW_PAD_CTL_PAD_GPIO_B1_04 SW PAD Control Register + 0x37C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_05 + SW_PAD_CTL_PAD_GPIO_B1_05 SW PAD Control Register + 0x380 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_06 + SW_PAD_CTL_PAD_GPIO_B1_06 SW PAD Control Register + 0x384 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_07 + SW_PAD_CTL_PAD_GPIO_B1_07 SW PAD Control Register + 0x388 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_08 + SW_PAD_CTL_PAD_GPIO_B1_08 SW PAD Control Register + 0x38C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_09 + SW_PAD_CTL_PAD_GPIO_B1_09 SW PAD Control Register + 0x390 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_10 + SW_PAD_CTL_PAD_GPIO_B1_10 SW PAD Control Register + 0x394 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_11 + SW_PAD_CTL_PAD_GPIO_B1_11 SW PAD Control Register + 0x398 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_12 + SW_PAD_CTL_PAD_GPIO_B1_12 SW PAD Control Register + 0x39C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_13 + SW_PAD_CTL_PAD_GPIO_B1_13 SW PAD Control Register + 0x3A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_14 + SW_PAD_CTL_PAD_GPIO_B1_14 SW PAD Control Register + 0x3A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_15 + SW_PAD_CTL_PAD_GPIO_B1_15 SW PAD Control Register + 0x3A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_00 + SW_PAD_CTL_PAD_GPIO_SD_B0_00 SW PAD Control Register + 0x3AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_01 + SW_PAD_CTL_PAD_GPIO_SD_B0_01 SW PAD Control Register + 0x3B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_02 + SW_PAD_CTL_PAD_GPIO_SD_B0_02 SW PAD Control Register + 0x3B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_03 + SW_PAD_CTL_PAD_GPIO_SD_B0_03 SW PAD Control Register + 0x3B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_04 + SW_PAD_CTL_PAD_GPIO_SD_B0_04 SW PAD Control Register + 0x3BC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_05 + SW_PAD_CTL_PAD_GPIO_SD_B0_05 SW PAD Control Register + 0x3C0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_00 + SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register + 0x3C4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_01 + SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register + 0x3C8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_02 + SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register + 0x3CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_03 + SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register + 0x3D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_04 + SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register + 0x3D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_05 + SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register + 0x3D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_06 + SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register + 0x3DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_07 + SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register + 0x3E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_08 + SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register + 0x3E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_09 + SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register + 0x3E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_10 + SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register + 0x3EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_11 + SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register + 0x3F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + ANATOP_USB_OTG1_ID_SELECT_INPUT + ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT3 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3 + 0 + + + GPIO_AD_B1_02_ALT0 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0 + 0x1 + + + + + + + ANATOP_USB_OTG2_ID_SELECT_INPUT + ANATOP_USB_OTG2_ID_SELECT_INPUT DAISY Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT3 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT3 + 0 + + + GPIO_AD_B1_00_ALT0 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT0 + 0x1 + + + + + + + CCM_PMIC_READY_SELECT_INPUT + CCM_PMIC_READY_SELECT_INPUT DAISY Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_03_ALT6 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + 0 + + + GPIO_AD_B0_12_ALT1 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + 0x1 + + + GPIO_AD_B1_01_ALT4 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + 0x2 + + + GPIO_AD_B1_08_ALT3 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + 0x3 + + + GPIO_EMC_32_ALT3 + Selecting Pad: GPIO_EMC_32 for Mode: ALT3 + 0x4 + + + + + + + CSI_DATA02_SELECT_INPUT + CSI_DATA02_SELECT_INPUT DAISY Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_15_ALT4 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT4 + 0 + + + GPIO_AD_B0_11_ALT4 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA03_SELECT_INPUT + CSI_DATA03_SELECT_INPUT DAISY Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_14_ALT4 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT4 + 0 + + + GPIO_AD_B0_10_ALT4 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA04_SELECT_INPUT + CSI_DATA04_SELECT_INPUT DAISY Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_13_ALT4 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT4 + 0 + + + GPIO_AD_B0_09_ALT4 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA05_SELECT_INPUT + CSI_DATA05_SELECT_INPUT DAISY Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_12_ALT4 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT4 + 0 + + + GPIO_AD_B0_08_ALT4 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA06_SELECT_INPUT + CSI_DATA06_SELECT_INPUT DAISY Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_11_ALT4 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT4 + 0 + + + GPIO_AD_B0_07_ALT4 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA07_SELECT_INPUT + CSI_DATA07_SELECT_INPUT DAISY Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_10_ALT4 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT4 + 0 + + + GPIO_AD_B0_06_ALT4 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA08_SELECT_INPUT + CSI_DATA08_SELECT_INPUT DAISY Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_09_ALT4 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT4 + 0 + + + GPIO_AD_B0_05_ALT4 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA09_SELECT_INPUT + CSI_DATA09_SELECT_INPUT DAISY Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_08_ALT4 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT4 + 0 + + + GPIO_AD_B0_04_ALT4 + Selecting Pad: GPIO_AD_B0_04 for Mode: ALT4 + 0x1 + + + + + + + CSI_HSYNC_SELECT_INPUT + CSI_HSYNC_SELECT_INPUT DAISY Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_15_ALT4 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT4 + 0 + + + GPIO_AD_B1_07_ALT4 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT4 + 0x1 + + + GPIO_B1_14_ALT2 + Selecting Pad: GPIO_B1_14 for Mode: ALT2 + 0x2 + + + + + + + CSI_PIXCLK_SELECT_INPUT + CSI_PIXCLK_SELECT_INPUT DAISY Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_04_ALT4 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT4 + 0 + + + GPIO_B1_12_ALT2 + Selecting Pad: GPIO_B1_12 for Mode: ALT2 + 0x1 + + + + + + + CSI_VSYNC_SELECT_INPUT + CSI_VSYNC_SELECT_INPUT DAISY Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_14_ALT4 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT4 + 0 + + + GPIO_AD_B1_06_ALT4 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT4 + 0x1 + + + GPIO_B1_13_ALT2 + Selecting Pad: GPIO_B1_13 for Mode: ALT2 + 0x2 + + + + + + + ENET_IPG_CLK_RMII_SELECT_INPUT + ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT4 + Selecting Pad: GPIO_EMC_25 for Mode: ALT4 + 0 + + + GPIO_B1_10_ALT6 + Selecting Pad: GPIO_B1_10 for Mode: ALT6 + 0x1 + + + + + + + ENET_MDIO_SELECT_INPUT + ENET_MDIO_SELECT_INPUT DAISY Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_05_ALT1 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT1 + 0 + + + GPIO_EMC_41_ALT4 + Selecting Pad: GPIO_EMC_41 for Mode: ALT4 + 0x1 + + + GPIO_B1_15_ALT0 + Selecting Pad: GPIO_B1_15 for Mode: ALT0 + 0x2 + + + + + + + ENET0_RXDATA_SELECT_INPUT + ENET0_RXDATA_SELECT_INPUT DAISY Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT3 + Selecting Pad: GPIO_EMC_20 for Mode: ALT3 + 0 + + + GPIO_B1_04_ALT3 + Selecting Pad: GPIO_B1_04 for Mode: ALT3 + 0x1 + + + + + + + ENET1_RXDATA_SELECT_INPUT + ENET1_RXDATA_SELECT_INPUT DAISY Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT3 + Selecting Pad: GPIO_EMC_19 for Mode: ALT3 + 0 + + + GPIO_B1_05_ALT3 + Selecting Pad: GPIO_B1_05 for Mode: ALT3 + 0x1 + + + + + + + ENET_RXEN_SELECT_INPUT + ENET_RXEN_SELECT_INPUT DAISY Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT3 + Selecting Pad: GPIO_EMC_23 for Mode: ALT3 + 0 + + + GPIO_B1_06_ALT3 + Selecting Pad: GPIO_B1_06 for Mode: ALT3 + 0x1 + + + + + + + ENET_RXERR_SELECT_INPUT + ENET_RXERR_SELECT_INPUT DAISY Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT3 + Selecting Pad: GPIO_EMC_26 for Mode: ALT3 + 0 + + + GPIO_B1_11_ALT3 + Selecting Pad: GPIO_B1_11 for Mode: ALT3 + 0x1 + + + + + + + ENET0_TIMER_SELECT_INPUT + ENET0_TIMER_SELECT_INPUT DAISY Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_15_ALT3 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT3 + 0 + + + GPIO_AD_B0_11_ALT7 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT7 + 0x1 + + + GPIO_B1_12_ALT3 + Selecting Pad: GPIO_B1_12 for Mode: ALT3 + 0x2 + + + + + + + ENET_TXCLK_SELECT_INPUT + ENET_TXCLK_SELECT_INPUT DAISY Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT3 + Selecting Pad: GPIO_EMC_25 for Mode: ALT3 + 0 + + + GPIO_B1_10_ALT3 + Selecting Pad: GPIO_B1_10 for Mode: ALT3 + 0x1 + + + + + + + FLEXCAN1_RX_SELECT_INPUT + FLEXCAN1_RX_SELECT_INPUT DAISY Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT4 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT4 + 0 + + + GPIO_EMC_18_ALT3 + Selecting Pad: GPIO_EMC_18 for Mode: ALT3 + 0x1 + + + GPIO_AD_B1_09_ALT2 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT2 + 0x2 + + + GPIO_B0_03_ALT2 + Selecting Pad: GPIO_B0_03 for Mode: ALT2 + 0x3 + + + + + + + FLEXCAN2_RX_SELECT_INPUT + FLEXCAN2_RX_SELECT_INPUT DAISY Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_10_ALT3 + Selecting Pad: GPIO_EMC_10 for Mode: ALT3 + 0 + + + GPIO_AD_B0_03_ALT0 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT0 + 0x1 + + + GPIO_AD_B0_15_ALT6 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT6 + 0x2 + + + GPIO_B1_09_ALT6 + Selecting Pad: GPIO_B1_09 for Mode: ALT6 + 0x3 + + + + + + + FLEXPWM1_PWMA3_SELECT_INPUT + FLEXPWM1_PWMA3_SELECT_INPUT DAISY Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_00_ALT2 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT2 + 0 + + + GPIO_EMC_12_ALT4 + Selecting Pad: GPIO_EMC_12 for Mode: ALT4 + 0x1 + + + GPIO_EMC_38_ALT1 + Selecting Pad: GPIO_EMC_38 for Mode: ALT1 + 0x2 + + + GPIO_AD_B0_10_ALT1 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT1 + 0x3 + + + GPIO_B1_00_ALT6 + Selecting Pad: GPIO_B1_00 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM1_PWMA0_SELECT_INPUT + FLEXPWM1_PWMA0_SELECT_INPUT DAISY Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT1 + Selecting Pad: GPIO_EMC_23 for Mode: ALT1 + 0 + + + GPIO_SD_B0_00_ALT1 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMA1_SELECT_INPUT + FLEXPWM1_PWMA1_SELECT_INPUT DAISY Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT1 + Selecting Pad: GPIO_EMC_25 for Mode: ALT1 + 0 + + + GPIO_SD_B0_02_ALT1 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMA2_SELECT_INPUT + FLEXPWM1_PWMA2_SELECT_INPUT DAISY Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT1 + Selecting Pad: GPIO_EMC_27 for Mode: ALT1 + 0 + + + GPIO_SD_B0_04_ALT1 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB3_SELECT_INPUT + FLEXPWM1_PWMB3_SELECT_INPUT DAISY Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_01_ALT2 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT2 + 0 + + + GPIO_EMC_13_ALT4 + Selecting Pad: GPIO_EMC_13 for Mode: ALT4 + 0x1 + + + GPIO_EMC_39_ALT1 + Selecting Pad: GPIO_EMC_39 for Mode: ALT1 + 0x2 + + + GPIO_AD_B0_11_ALT1 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT1 + 0x3 + + + GPIO_B1_01_ALT6 + Selecting Pad: GPIO_B1_01 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM1_PWMB0_SELECT_INPUT + FLEXPWM1_PWMB0_SELECT_INPUT DAISY Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT1 + Selecting Pad: GPIO_EMC_24 for Mode: ALT1 + 0 + + + GPIO_SD_B0_01_ALT1 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB1_SELECT_INPUT + FLEXPWM1_PWMB1_SELECT_INPUT DAISY Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT1 + Selecting Pad: GPIO_EMC_26 for Mode: ALT1 + 0 + + + GPIO_SD_B0_03_ALT1 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB2_SELECT_INPUT + FLEXPWM1_PWMB2_SELECT_INPUT DAISY Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_28_ALT1 + Selecting Pad: GPIO_EMC_28 for Mode: ALT1 + 0 + + + GPIO_SD_B0_05_ALT1 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM2_PWMA3_SELECT_INPUT + FLEXPWM2_PWMA3_SELECT_INPUT DAISY Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_02_ALT2 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT2 + 0 + + + GPIO_EMC_19_ALT1 + Selecting Pad: GPIO_EMC_19 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_00_ALT0 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT0 + 0x2 + + + GPIO_AD_B0_09_ALT1 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT1 + 0x3 + + + GPIO_B1_02_ALT6 + Selecting Pad: GPIO_B1_02 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM2_PWMA0_SELECT_INPUT + FLEXPWM2_PWMA0_SELECT_INPUT DAISY Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT1 + Selecting Pad: GPIO_EMC_06 for Mode: ALT1 + 0 + + + GPIO_B0_06_ALT2 + Selecting Pad: GPIO_B0_06 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMA1_SELECT_INPUT + FLEXPWM2_PWMA1_SELECT_INPUT DAISY Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT1 + Selecting Pad: GPIO_EMC_08 for Mode: ALT1 + 0 + + + GPIO_B0_08_ALT2 + Selecting Pad: GPIO_B0_08 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMA2_SELECT_INPUT + FLEXPWM2_PWMA2_SELECT_INPUT DAISY Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_10_ALT1 + Selecting Pad: GPIO_EMC_10 for Mode: ALT1 + 0 + + + GPIO_B0_10_ALT2 + Selecting Pad: GPIO_B0_10 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB3_SELECT_INPUT + FLEXPWM2_PWMB3_SELECT_INPUT DAISY Register + 0x484 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT2 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT2 + 0 + + + GPIO_EMC_20_ALT1 + Selecting Pad: GPIO_EMC_20 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_01_ALT0 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT0 + 0x2 + + + GPIO_B1_03_ALT6 + Selecting Pad: GPIO_B1_03 for Mode: ALT6 + 0x3 + + + + + + + FLEXPWM2_PWMB0_SELECT_INPUT + FLEXPWM2_PWMB0_SELECT_INPUT DAISY Register + 0x488 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT1 + Selecting Pad: GPIO_EMC_07 for Mode: ALT1 + 0 + + + GPIO_B0_07_ALT2 + Selecting Pad: GPIO_B0_07 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB1_SELECT_INPUT + FLEXPWM2_PWMB1_SELECT_INPUT DAISY Register + 0x48C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT1 + Selecting Pad: GPIO_EMC_09 for Mode: ALT1 + 0 + + + GPIO_B0_09_ALT2 + Selecting Pad: GPIO_B0_09 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB2_SELECT_INPUT + FLEXPWM2_PWMB2_SELECT_INPUT DAISY Register + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_11_ALT1 + Selecting Pad: GPIO_EMC_11 for Mode: ALT1 + 0 + + + GPIO_B0_11_ALT2 + Selecting Pad: GPIO_B0_11 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM4_PWMA0_SELECT_INPUT + FLEXPWM4_PWMA0_SELECT_INPUT DAISY Register + 0x494 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_00_ALT1 + Selecting Pad: GPIO_EMC_00 for Mode: ALT1 + 0 + + + GPIO_AD_B1_08_ALT1 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA1_SELECT_INPUT + FLEXPWM4_PWMA1_SELECT_INPUT DAISY Register + 0x498 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_02_ALT1 + Selecting Pad: GPIO_EMC_02 for Mode: ALT1 + 0 + + + GPIO_AD_B1_09_ALT1 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA2_SELECT_INPUT + FLEXPWM4_PWMA2_SELECT_INPUT DAISY Register + 0x49C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT1 + Selecting Pad: GPIO_EMC_04 for Mode: ALT1 + 0 + + + GPIO_B1_14_ALT1 + Selecting Pad: GPIO_B1_14 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA3_SELECT_INPUT + FLEXPWM4_PWMA3_SELECT_INPUT DAISY Register + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_17_ALT1 + Selecting Pad: GPIO_EMC_17 for Mode: ALT1 + 0 + + + GPIO_B1_15_ALT1 + Selecting Pad: GPIO_B1_15 for Mode: ALT1 + 0x1 + + + + + + + FLEXSPIA_DQS_SELECT_INPUT + FLEXSPIA_DQS_SELECT_INPUT DAISY Register + 0x4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT1 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT1 + 0 + + + GPIO_AD_B1_09_ALT0 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA0_SELECT_INPUT + FLEXSPIA_DATA0_SELECT_INPUT DAISY Register + 0x4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT1 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT1 + 0 + + + GPIO_AD_B1_13_ALT0 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA1_SELECT_INPUT + FLEXSPIA_DATA1_SELECT_INPUT DAISY Register + 0x4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT1 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT1 + 0 + + + GPIO_AD_B1_12_ALT0 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA2_SELECT_INPUT + FLEXSPIA_DATA2_SELECT_INPUT DAISY Register + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT1 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT1 + 0 + + + GPIO_AD_B1_11_ALT0 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA3_SELECT_INPUT + FLEXSPIA_DATA3_SELECT_INPUT DAISY Register + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT1 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT1 + 0 + + + GPIO_AD_B1_10_ALT0 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA0_SELECT_INPUT + FLEXSPIB_DATA0_SELECT_INPUT DAISY Register + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_03_ALT1 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT1 + 0 + + + GPIO_AD_B1_07_ALT0 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA1_SELECT_INPUT + FLEXSPIB_DATA1_SELECT_INPUT DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT1 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT1 + 0 + + + GPIO_AD_B1_06_ALT0 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA2_SELECT_INPUT + FLEXSPIB_DATA2_SELECT_INPUT DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT1 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT1 + 0 + + + GPIO_AD_B1_05_ALT0 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA3_SELECT_INPUT + FLEXSPIB_DATA3_SELECT_INPUT DAISY Register + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT1 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT1 + 0 + + + GPIO_AD_B1_04_ALT0 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_SCK_SELECT_INPUT + FLEXSPIA_SCK_SELECT_INPUT DAISY Register + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT1 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT1 + 0 + + + GPIO_AD_B1_14_ALT0 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT0 + 0x1 + + + + + + + LPI2C1_SCL_SELECT_INPUT + LPI2C1_SCL_SELECT_INPUT DAISY Register + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_04_ALT2 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT2 + 0 + + + GPIO_AD_B1_00_ALT3 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT3 + 0x1 + + + + + + + LPI2C1_SDA_SELECT_INPUT + LPI2C1_SDA_SELECT_INPUT DAISY Register + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT2 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT2 + 0 + + + GPIO_AD_B1_01_ALT3 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT3 + 0x1 + + + + + + + LPI2C2_SCL_SELECT_INPUT + LPI2C2_SCL_SELECT_INPUT DAISY Register + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT3 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT3 + 0 + + + GPIO_B0_04_ALT2 + Selecting Pad: GPIO_B0_04 for Mode: ALT2 + 0x1 + + + + + + + LPI2C2_SDA_SELECT_INPUT + LPI2C2_SDA_SELECT_INPUT DAISY Register + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT3 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT3 + 0 + + + GPIO_B0_05_ALT2 + Selecting Pad: GPIO_B0_05 for Mode: ALT2 + 0x1 + + + + + + + LPI2C3_SCL_SELECT_INPUT + LPI2C3_SCL_SELECT_INPUT DAISY Register + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_22_ALT2 + Selecting Pad: GPIO_EMC_22 for Mode: ALT2 + 0 + + + GPIO_SD_B0_00_ALT2 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT2 + 0x1 + + + GPIO_AD_B1_07_ALT1 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT1 + 0x2 + + + + + + + LPI2C3_SDA_SELECT_INPUT + LPI2C3_SDA_SELECT_INPUT DAISY Register + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_21_ALT2 + Selecting Pad: GPIO_EMC_21 for Mode: ALT2 + 0 + + + GPIO_SD_B0_01_ALT2 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT2 + 0x1 + + + GPIO_AD_B1_06_ALT1 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT1 + 0x2 + + + + + + + LPI2C4_SCL_SELECT_INPUT + LPI2C4_SCL_SELECT_INPUT DAISY Register + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT2 + Selecting Pad: GPIO_EMC_12 for Mode: ALT2 + 0 + + + GPIO_AD_B0_12_ALT0 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT0 + 0x1 + + + + + + + LPI2C4_SDA_SELECT_INPUT + LPI2C4_SDA_SELECT_INPUT DAISY Register + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_11_ALT2 + Selecting Pad: GPIO_EMC_11 for Mode: ALT2 + 0 + + + GPIO_AD_B0_13_ALT0 + Selecting Pad: GPIO_AD_B0_13 for Mode: ALT0 + 0x1 + + + + + + + LPSPI1_PCS0_SELECT_INPUT + LPSPI1_PCS0_SELECT_INPUT DAISY Register + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B0_01_ALT4 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT4 + 0 + + + GPIO_EMC_30_ALT3 + Selecting Pad: GPIO_EMC_30 for Mode: ALT3 + 0x1 + + + + + + + LPSPI1_SCK_SELECT_INPUT + LPSPI1_SCK_SELECT_INPUT DAISY Register + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT3 + Selecting Pad: GPIO_EMC_27 for Mode: ALT3 + 0 + + + GPIO_SD_B0_00_ALT4 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT4 + 0x1 + + + + + + + LPSPI1_SDI_SELECT_INPUT + LPSPI1_SDI_SELECT_INPUT DAISY Register + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_29_ALT3 + Selecting Pad: GPIO_EMC_29 for Mode: ALT3 + 0 + + + GPIO_SD_B0_03_ALT4 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT4 + 0x1 + + + + + + + LPSPI1_SDO_SELECT_INPUT + LPSPI1_SDO_SELECT_INPUT DAISY Register + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_28_ALT3 + Selecting Pad: GPIO_EMC_28 for Mode: ALT3 + 0 + + + GPIO_SD_B0_02_ALT4 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT4 + 0x1 + + + + + + + LPSPI2_PCS0_SELECT_INPUT + LPSPI2_PCS0_SELECT_INPUT DAISY Register + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_06_ALT4 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT4 + 0 + + + GPIO_EMC_01_ALT2 + Selecting Pad: GPIO_EMC_01 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SCK_SELECT_INPUT + LPSPI2_SCK_SELECT_INPUT DAISY Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT4 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT4 + 0 + + + GPIO_EMC_00_ALT2 + Selecting Pad: GPIO_EMC_00 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SDI_SELECT_INPUT + LPSPI2_SDI_SELECT_INPUT DAISY Register + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT4 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT4 + 0 + + + GPIO_EMC_03_ALT2 + Selecting Pad: GPIO_EMC_03 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SDO_SELECT_INPUT + LPSPI2_SDO_SELECT_INPUT DAISY Register + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT4 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT4 + 0 + + + GPIO_EMC_02_ALT2 + Selecting Pad: GPIO_EMC_02 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_PCS0_SELECT_INPUT + LPSPI3_PCS0_SELECT_INPUT DAISY Register + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_03_ALT7 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT7 + 0 + + + GPIO_AD_B1_12_ALT2 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SCK_SELECT_INPUT + LPSPI3_SCK_SELECT_INPUT DAISY Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT7 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT7 + 0 + + + GPIO_AD_B1_15 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SDI_SELECT_INPUT + LPSPI3_SDI_SELECT_INPUT DAISY Register + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_02_ALT7 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT7 + 0 + + + GPIO_AD_B1_13_ALT2 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SDO_SELECT_INPUT + LPSPI3_SDO_SELECT_INPUT DAISY Register + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT7 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT7 + 0 + + + GPIO_AD_B1_14_ALT2 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT2 + 0x1 + + + + + + + LPSPI4_PCS0_SELECT_INPUT + LPSPI4_PCS0_SELECT_INPUT DAISY Register + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_00_ALT3 + Selecting Pad: GPIO_B0_00 for Mode: ALT3 + 0 + + + GPIO_B1_04_ALT1 + Selecting Pad:GPIO_B1_04 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SCK_SELECT_INPUT + LPSPI4_SCK_SELECT_INPUT DAISY Register + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_03_ALT3 + Selecting Pad: GPIO_B0_03 for Mode: ALT3 + 0 + + + GPIO_B1_07_ALT1 + Selecting Pad: GPIO_B1_07 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SDI_SELECT_INPUT + LPSPI4_SDI_SELECT_INPUT DAISY Register + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_01_ALT3 + Selecting Pad: GPIO_B0_01 for Mode: ALT3 + 0 + + + GPIO_B1_05_ALT1 + Selecting Pad: GPIO_B1_05 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SDO_SELECT_INPUT + LPSPI4_SDO_SELECT_INPUT DAISY Register + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_02_ALT3 + Selecting Pad: GPIO_B0_02 for Mode: ALT3 + 0 + + + GPIO_B1_06_ALT1 + Selecting Pad: GPIO_B1_06 for Mode: ALT1 + 0x1 + + + + + + + LPUART2_RX_SELECT_INPUT + LPUART2_RX_SELECT_INPUT DAISY Register + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT2 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT2 + 0 + + + GPIO_AD_B1_03_ALT2 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT2 + 0x1 + + + + + + + LPUART2_TX_SELECT_INPUT + LPUART2_TX_SELECT_INPUT DAISY Register + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT2 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT2 + 0 + + + GPIO_AD_B1_02_ALT2 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_CTS_B_SELECT_INPUT + LPUART3_CTS_B_SELECT_INPUT DAISY Register + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT2 + Selecting Pad: GPIO_EMC_15 for Mode: ALT2 + 0 + + + GPIO_AD_B1_04_ALT2 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_RX_SELECT_INPUT + LPUART3_RX_SELECT_INPUT DAISY Register + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_07_ALT2 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT2 + 0 + + + GPIO_EMC_14_ALT2 + Selecting Pad: GPIO_EMC_14 for Mode: ALT2 + 0x1 + + + GPIO_B0_09_ALT3 + Selecting Pad: GPIO_B0_09 for Mode: ALT3 + 0x2 + + + + + + + LPUART3_TX_SELECT_INPUT + LPUART3_TX_SELECT_INPUT DAISY Register + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_06_ALT2 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT2 + 0 + + + GPIO_EMC_13_ALT2 + Selecting Pad: GPIO_EMC_13 for Mode: ALT2 + 0x1 + + + GPIO_B0_08_ALT3 + Selecting Pad: GPIO_B0_08 for Mode: ALT3 + 0x2 + + + + + + + LPUART4_RX_SELECT_INPUT + LPUART4_RX_SELECT_INPUT DAISY Register + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_01_ALT4 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT4 + 0 + + + GPIO_EMC_20_ALT2 + Selecting Pad: GPIO_EMC_20 for Mode: ALT2 + 0x1 + + + GPIO_B1_01_ALT2 + Selecting Pad: GPIO_B1_01 for Mode: ALT2 + 0x2 + + + + + + + LPUART4_TX_SELECT_INPUT + LPUART4_TX_SELECT_INPUT DAISY Register + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_00_ALT4 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT4 + 0 + + + GPIO_EMC_19_ALT2 + Selecting Pad: GPIO_EMC_19 for Mode: ALT2 + 0x1 + + + GPIO_B1_00_ALT2 + Selecting Pad: GPIO_B1_00 for Mode: ALT2 + 0x2 + + + + + + + LPUART5_RX_SELECT_INPUT + LPUART5_RX_SELECT_INPUT DAISY Register + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT2 + Selecting Pad: GPIO_EMC_24 for Mode: ALT2 + 0 + + + GPIO_B1_13_ALT1 + Selecting Pad: GPIO_B1_13 for Mode: ALT1 + 0x1 + + + + + + + LPUART5_TX_SELECT_INPUT + LPUART5_TX_SELECT_INPUT DAISY Register + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT2 + Selecting Pad: GPIO_EMC_23 for Mode: ALT2 + 0 + + + GPIO_B1_12_ALT1 + Selecting Pad: GPIO_B1_12 for Mode: ALT1 + 0x1 + + + + + + + LPUART6_RX_SELECT_INPUT + LPUART6_RX_SELECT_INPUT DAISY Register + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT2 + Selecting Pad: GPIO_EMC_26 for Mode: ALT2 + 0 + + + GPIO_AD_B0_03_ALT2 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT2 + 0x1 + + + + + + + LPUART6_TX_SELECT_INPUT + LPUART6_TX_SELECT_INPUT DAISY Register + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT2 + Selecting Pad: GPIO_EMC_25 for Mode: ALT2 + 0 + + + GPIO_AD_B0_02_ALT2 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT2 + 0x1 + + + + + + + LPUART7_RX_SELECT_INPUT + LPUART7_RX_SELECT_INPUT DAISY Register + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT2 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT2 + 0 + + + GPIO_EMC_32_ALT2 + Selecting Pad: GPIO_EMC_32 for Mode: ALT2 + 0x1 + + + + + + + LPUART7_TX_SELECT_INPUT + LPUART7_TX_SELECT_INPUT DAISY Register + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT2 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT2 + 0 + + + GPIO_EMC_31_ALT2 + Selecting Pad:GPIO_EMC_31 for Mode: ALT2 + 0x1 + + + + + + + LPUART8_RX_SELECT_INPUT + LPUART8_RX_SELECT_INPUT DAISY Register + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_05_ALT2 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT2 + 0 + + + GPIO_AD_B1_11_ALT2 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT2 + 0x1 + + + GPIO_EMC_39_ALT2 + Selecting Pad: GPIO_EMC_39 for Mode: ALT2 + 0x2 + + + + + + + LPUART8_TX_SELECT_INPUT + LPUART8_TX_SELECT_INPUT DAISY Register + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_04_ALT2 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT2 + 0 + + + GPIO_AD_B1_10_ALT2 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT2 + 0x1 + + + GPIO_EMC_38_ALT2 + Selecting Pad: GPIO_EMC_38 for Mode: ALT2 + 0x2 + + + + + + + NMI_SELECT_INPUT + NMI_GLUE_NMI_SELECT_INPUT DAISY Register + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_12_ALT7 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT7 + 0 + + + WAKEUP_ALT7 + Selecting Pad: WAKEUP for Mode: ALT7 + 0x1 + + + + + + + QTIMER2_TIMER0_SELECT_INPUT + QTIMER2_TIMER0_SELECT_INPUT DAISY Register + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT4 + Selecting Pad: GPIO_EMC_19 for Mode: ALT4 + 0 + + + GPIO_B0_03_ALT1 + Selecting Pad: GPIO_B0_03 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER1_SELECT_INPUT + QTIMER2_TIMER1_SELECT_INPUT DAISY Register + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT4 + Selecting Pad: GPIO_EMC_20 for Mode: ALT4 + 0 + + + GPIO_B0_04_ALT1 + Selecting Pad: GPIO_B0_04 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER2_SELECT_INPUT + QTIMER2_TIMER2_SELECT_INPUT DAISY Register + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_21_ALT4 + Selecting Pad: GPIO_EMC_21 for Mode: ALT4 + 0 + + + GPIO_B0_05_ALT1 + Selecting Pad: GPIO_B0_05 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER3_SELECT_INPUT + QTIMER2_TIMER3_SELECT_INPUT DAISY Register + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_22_ALT4 + Selecting Pad: GPIO_EMC_22 for Mode: ALT4 + 0 + + + GPIO_B1_09_ALT1 + Selecting Pad: GPIO_B1_09 for Mode: ALT1 + 0x1 + + + + + + + QTIMER3_TIMER0_SELECT_INPUT + QTIMER3_TIMER0_SELECT_INPUT DAISY Register + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_15_ALT4 + Selecting Pad: GPIO_EMC_15 for Mode: ALT4 + 0 + + + GPIO_AD_B1_00_ALT1 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT1 + 0x1 + + + GPIO_B0_06_ALT1 + Selecting Pad: GPIO_B0_06 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER1_SELECT_INPUT + QTIMER3_TIMER1_SELECT_INPUT DAISY Register + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_01_ALT1 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT1 + 0 + + + GPIO_EMC_16_ALT4 + Selecting Pad: GPIO_EMC_16 for Mode: ALT4 + 0x1 + + + GPIO_B0_07_ALT1 + Selecting Pad: GPIO_B0_07 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER2_SELECT_INPUT + QTIMER3_TIMER2_SELECT_INPUT DAISY Register + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_17_ALT4 + Selecting Pad: GPIO_EMC_17 for Mode: ALT4 + 0 + + + GPIO_AD_B1_02_ALT1 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT1 + 0x1 + + + GPIO_B0_08_ALT1 + Selecting Pad: GPIO_B0_08 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER3_SELECT_INPUT + QTIMER3_TIMER3_SELECT_INPUT DAISY Register + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_18_ALT4 + Selecting Pad: GPIO_EMC_18 for Mode: ALT4 + 0 + + + GPIO_AD_B1_03_ALT1 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT1 + 0x1 + + + GPIO_B1_10_ALT1 + Selecting Pad: GPIO_B1_10 for Mode: ALT1 + 0x2 + + + + + + + SAI1_MCLK2_SELECT_INPUT + SAI1_MCLK2_SELECT_INPUT DAISY Register + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT3 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT3 + 0 + + + GPIO_AD_B1_09_ALT3 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT3 + 0x1 + + + GPIO_B0_13_ALT3 + Selecting Pad: GPIO_B0_13 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_BCLK_SELECT_INPUT + SAI1_RX_BCLK_SELECT_INPUT DAISY Register + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_05_ALT3 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT3 + 0 + + + GPIO_AD_B1_11_ALT3 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT3 + 0x1 + + + GPIO_B0_15_ALT3 + Selecting Pad: GPIO_B0_15 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_DATA0_SELECT_INPUT + SAI1_RX_DATA0_SELECT_INPUT DAISY Register + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_06_ALT3 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT3 + 0 + + + GPIO_AD_B1_12_ALT3 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT3 + 0x1 + + + GPIO_B1_00_ALT3 + Selecting Pad: GPIO_B1_00 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_DATA1_SELECT_INPUT + SAI1_RX_DATA1_SELECT_INPUT DAISY Register + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT3 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT3 + 0 + + + GPIO_B0_10_ALT3 + Selecting Pad: GPIO_B0_10 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_DATA2_SELECT_INPUT + SAI1_RX_DATA2_SELECT_INPUT DAISY Register + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT3 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT3 + 0 + + + GPIO_B0_11_ALT3 + Selecting Pad: GPIO_B0_11 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_DATA3_SELECT_INPUT + SAI1_RX_DATA3_SELECT_INPUT DAISY Register + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT3 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT3 + 0 + + + GPIO_B0_12_ALT3 + Selecting Pad: GPIO_B0_12 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_SYNC_SELECT_INPUT + SAI1_RX_SYNC_SELECT_INPUT DAISY Register + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_04_ALT3 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT3 + 0 + + + GPIO_AD_B1_10_ALT3 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT3 + 0x1 + + + GPIO_B0_14_ALT3 + Selecting Pad: GPIO_B0_14 for Mode: ALT3 + 0x2 + + + + + + + SAI1_TX_BCLK_SELECT_INPUT + SAI1_TX_BCLK_SELECT_INPUT DAISY Register + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_08_ALT3 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT3 + 0 + + + GPIO_AD_B1_14_ALT3 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT3 + 0x1 + + + GPIO_B1_02_ALT3 + Selecting Pad: GPIO_B1_02 for Mode: ALT3 + 0x2 + + + + + + + SAI1_TX_SYNC_SELECT_INPUT + SAI1_TX_SYNC_SELECT_INPUT DAISY Register + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_09_ALT3 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT3 + 0 + + + GPIO_AD_B1_15_ALT3 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT3 + 0x1 + + + GPIO_B1_03_ALT3 + Selecting Pad: GPIO_B1_03 for Mode: ALT3 + 0x2 + + + + + + + SAI2_MCLK2_SELECT_INPUT + SAI2_MCLK2_SELECT_INPUT DAISY Register + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT2 + Selecting Pad: GPIO_EMC_07 for Mode: ALT2 + 0 + + + GPIO_AD_B0_10_ALT3 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_BCLK_SELECT_INPUT + SAI2_RX_BCLK_SELECT_INPUT DAISY Register + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_10_ALT2 + Selecting Pad: GPIO_EMC_10 for Mode: ALT2 + 0 + + + GPIO_AD_B0_06_ALT3 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_DATA0_SELECT_INPUT + SAI2_RX_DATA0_SELECT_INPUT DAISY Register + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT2 + Selecting Pad: GPIO_EMC_08 for Mode: ALT2 + 0 + + + GPIO_AD_B0_08_ALT3 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_SYNC_SELECT_INPUT + SAI2_RX_SYNC_SELECT_INPUT DAISY Register + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT2 + Selecting Pad: GPIO_EMC_09 for Mode: ALT2 + 0 + + + GPIO_AD_B0_07_ALT3 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT3 + 0x1 + + + + + + + SAI2_TX_BCLK_SELECT_INPUT + SAI2_TX_BCLK_SELECT_INPUT DAISY Register + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT2 + Selecting Pad: GPIO_EMC_06 for Mode: ALT2 + 0 + + + GPIO_AD_B0_05_ALT3 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT3 + 0x1 + + + + + + + SAI2_TX_SYNC_SELECT_INPUT + SAI2_TX_SYNC_SELECT_INPUT DAISY Register + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT2 + Selecting Pad: GPIO_EMC_05 for Mode: ALT2 + 0 + + + GPIO_AD_B0_04_ALT3 + Selecting Pad: GPIO_AD_B0_04 for Mode: ALT3 + 0x1 + + + + + + + SPDIF_IN_SELECT_INPUT + SPDIF_IN_SELECT_INPUT DAISY Register + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_03_ALT3 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT3 + 0 + + + GPIO_EMC_16_ALT3 + Selecting Pad: GPIO_EMC_16 for Mode: ALT3 + 0x1 + + + + + + + USB_OTG2_OC_SELECT_INPUT + USB_OTG2_OC_SELECT_INPUT DAISY Register + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_14_ALT0 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT0 + 0 + + + GPIO_EMC_40_ALT3 + Selecting Pad: GPIO_EMC_40 for Mode: ALT3 + 0x1 + + + + + + + USB_OTG1_OC_SELECT_INPUT + USB_OTG1_OC_SELECT_INPUT DAISY Register + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_03_ALT3 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT3 + 0 + + + GPIO_AD_B1_03_ALT0 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT0 + 0x1 + + + + + + + USDHC1_CD_B_SELECT_INPUT + USDHC1_CD_B_SELECT_INPUT DAISY Register + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_35_ALT6 + Selecting Pad: GPIO_EMC_35 for Mode: ALT6 + 0 + + + GPIO_AD_B1_02_ALT6 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT6 + 0x1 + + + GPIO_B1_12_ALT6 + Selecting Pad: GPIO_B1_12 for Mode: ALT6 + 0x2 + + + + + + + USDHC1_WP_SELECT_INPUT + USDHC1_WP_SELECT_INPUT DAISY Register + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_12_ALT3 + Selecting Pad: GPIO_EMC_12 for Mode: ALT3 + 0 + + + GPIO_EMC_36_ALT6 + Selecting Pad: GPIO_EMC_36for Mode: ALT6 + 0x1 + + + GPIO_AD_B1_00_ALT6 + Selecting Pad:GPIO_AD_B1_00 for Mode: ALT6 + 0x2 + + + GPIO_B1_13_ALT6 + Selecting Pad: GPIO_B1_13 for Mode: ALT6 + 0x3 + + + + + + + USDHC2_CLK_SELECT_INPUT + USDHC2_CLK_SELECT_INPUT DAISY Register + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_04_ALT0 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT0 + 0 + + + GPIO_AD_B1_09_ALT6 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_CD_B_SELECT_INPUT + USDHC2_CD_B_SELECT_INPUT DAISY Register + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_03_ALT6 + Selecting Pad:GPIO_AD_B1_03 for Mode: ALT6 + 0 + + + GPIO_EMC_39_ALT6 + Selecting Pad: GPIO_EMC_39 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_CMD_SELECT_INPUT + USDHC2_CMD_SELECT_INPUT DAISY Register + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT0 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT0 + 0 + + + GPIO_AD_B1_08_ALT6 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA0_SELECT_INPUT + USDHC2_DATA0_SELECT_INPUT DAISY Register + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_03_ALT0 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT0 + 0 + + + GPIO_AD_B1_04_ALT6 + Selecting Pad:GPIO_AD_B1_04 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA1_SELECT_INPUT + USDHC2_DATA1_SELECT_INPUT DAISY Register + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT0 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT0 + 0 + + + GPIO_AD_B1_05_ALT6 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA2_SELECT_INPUT + USDHC2_DATA2_SELECT_INPUT DAISY Register + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT0 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT0 + 0 + + + GPIO_AD_B1_06_ALT6 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA3_SELECT_INPUT + USDHC2_DATA3_SELECT_INPUT DAISY Register + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT0 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT0 + 0 + + + GPIO_AD_B1_07_ALT6 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA4_SELECT_INPUT + USDHC2_DATA4_SELECT_INPUT DAISY Register + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT0 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT0 + 0 + + + GPIO_AD_B1_12_ALT6 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA5_SELECT_INPUT + USDHC2_DATA5_SELECT_INPUT DAISY Register + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT0 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT0 + 0 + + + GPIO_AD_B1_13_ALT6 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA6_SELECT_INPUT + USDHC2_DATA6_SELECT_INPUT DAISY Register + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT0 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT0 + 0 + + + GPIO_AD_B1_14_ALT6 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA7_SELECT_INPUT + USDHC2_DATA7_SELECT_INPUT DAISY Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT0 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT0 + 0 + + + GPIO_AD_B1_15_ALT6 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_WP_SELECT_INPUT + USDHC2_WP_SELECT_INPUT DAISY Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT6 + Selecting Pad: GPIO_EMC_37 for Mode: ALT6 + 0 + + + GPIO_AD_B1_10_ALT6 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN02_SELECT_INPUT + XBAR1_IN02_SELECT_INPUT DAISY Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_00_ALT3 + Selecting Pad: GPIO_EMC_00 for Mode: ALT3 + 0 + + + GPIO_B1_14_ALT3 + Selecting Pad: GPIO_B1_14 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN03_SELECT_INPUT + XBAR1_IN03_SELECT_INPUT DAISY Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_01_ALT3 + Selecting Pad: GPIO_EMC_01 for Mode: ALT3 + 0 + + + GPIO_B1_15_ALT3 + Selecting Pad: GPIO_B1_15 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN04_SELECT_INPUT + XBAR1_IN04_SELECT_INPUT DAISY Register + 0x614 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_02_ALT3 + Selecting Pad: GPIO_EMC_02 for Mode: ALT3 + 0 + + + GPIO_SD_B0_00_ALT3 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN05_SELECT_INPUT + XBAR1_IN05_SELECT_INPUT DAISY Register + 0x618 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_03_ALT3 + Selecting Pad: GPIO_EMC_03 for Mode: ALT3 + 0 + + + GPIO_SD_B0_01_ALT3 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN06_SELECT_INPUT + XBAR1_IN06_SELECT_INPUT DAISY Register + 0x61C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT3 + Selecting Pad: GPIO_EMC_04 for Mode: ALT3 + 0 + + + GPIO_SD_B0_02_ALT3 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN07_SELECT_INPUT + XBAR1_IN07_SELECT_INPUT DAISY Register + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT3 + Selecting Pad: GPIO_EMC_05 for Mode: ALT3 + 0 + + + GPIO_SD_B0_03_ALT3 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN08_SELECT_INPUT + XBAR1_IN08_SELECT_INPUT DAISY Register + 0x624 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT3 + Selecting Pad: GPIO_EMC_06 for Mode: ALT3 + 0 + + + GPIO_SD_B0_04_ALT3 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN09_SELECT_INPUT + XBAR1_IN09_SELECT_INPUT DAISY Register + 0x628 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT3 + Selecting Pad: GPIO_EMC_07 for Mode: ALT3 + 0 + + + GPIO_SD_B0_05_ALT3 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN17_SELECT_INPUT + XBAR1_IN17_SELECT_INPUT DAISY Register + 0x62C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_08_ALT3 + Selecting Pad: GPIO_EMC_08 for Mode: ALT3 + 0 + + + GPIO_AD_B0_03_ALT1 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_05_ALT6 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT6 + 0x2 + + + GPIO_B1_03_ALT1 + Selecting Pad: GPIO_B1_03 for Mode: ALT1 + 0x3 + + + + + + + XBAR1_IN18_SELECT_INPUT + XBAR1_IN18_SELECT_INPUT DAISY Register + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_35_ALT1 + Selecting Pad: GPIO_EMC_35 for Mode: ALT1 + 0 + + + GPIO_AD_B0_06_ALT6 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN20_SELECT_INPUT + XBAR1_IN20_SELECT_INPUT DAISY Register + 0x634 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT1 + Selecting Pad: GPIO_EMC_15 for Mode: ALT1 + 0 + + + GPIO_AD_B0_08_ALT6 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN22_SELECT_INPUT + XBAR1_IN22_SELECT_INPUT DAISY Register + 0x638 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_36_ALT1 + Selecting Pad: GPIO_EMC_36 for Mode: ALT1 + 0 + + + GPIO_AD_B0_10_ALT6 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN23_SELECT_INPUT + XBAR1_IN23_SELECT_INPUT DAISY Register + 0x63C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT1 + Selecting Pad: GPIO_EMC_37 for Mode: ALT1 + 0 + + + GPIO_AD_B0_11_ALT6 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN24_SELECT_INPUT + XBAR1_IN24_SELECT_INPUT DAISY Register + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT1 + Selecting Pad: GPIO_EMC_12 for Mode: ALT1 + 0 + + + GPIO_AD_B0_14_ALT1 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN14_SELECT_INPUT + XBAR1_IN14_SELECT_INPUT DAISY Register + 0x644 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT1 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT1 + 0 + + + GPIO_B1_00_ALT1 + Selecting Pad:GPIO_B1_00 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN15_SELECT_INPUT + XBAR1_IN15_SELECT_INPUT DAISY Register + 0x648 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT1 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT1 + 0 + + + GPIO_B1_01_ALT1 + Selecting Pad: GPIO_B1_01 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN16_SELECT_INPUT + XBAR1_IN16_SELECT_INPUT DAISY Register + 0x64C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_02_ALT1 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT1 + 0 + + + GPIO_B1_02_ALT1 + Selecting Pad: GPIO_B1_02 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN25_SELECT_INPUT + XBAR1_IN25_SELECT_INPUT DAISY Register + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_15_ALT1 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT1 + 0 + + + GPIO_EMC_13_ALT1 + Selecting Pad: GPIO_EMC_13 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN19_SELECT_INPUT + XBAR1_IN19_SELECT_INPUT DAISY Register + 0x654 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_14_ALT1 + Selecting Pad: GPIO_EMC_14 for Mode: ALT1 + 0 + + + GPIO_AD_B0_07_ALT6 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN21_SELECT_INPUT + XBAR1_IN23_SELECT_INPUT DAISY Register + 0x658 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_16_ALT1 + Selecting Pad: GPIO_EMC_16 for Mode: ALT1 + 0 + + + GPIO_AD_B0_09_ALT6 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT6 + 0x1 + + + + + + + + + KPP + KPP Registers + KPP + KPP_ + 0x401FC000 + + 0 + 0x8 + registers + + + KPP + 39 + + + + KPCR + Keypad Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + KRE + Keypad Row Enable + 0 + 8 + read-write + + + KRE_0 + Row is not included in the keypad key press detect. + 0 + + + KRE_1 + Row is included in the keypad key press detect. + 0x1 + + + + + KCO + Keypad Column Strobe Open-Drain Enable + 8 + 8 + read-write + + + TOTEM_POLE + Column strobe output is totem pole drive. + 0 + + + OPEN_DRAIN + Column strobe output is open drain. + 0x1 + + + + + + + KPSR + Keypad Status Register + 0x2 + 16 + read-write + 0x400 + 0xFFFF + + + KPKD + Keypad Key Depress + 0 + 1 + read-write + oneToClear + + + KPKD_0 + No key presses detected + 0 + + + KPKD_1 + A key has been depressed + 0x1 + + + + + KPKR + Keypad Key Release + 1 + 1 + read-write + oneToClear + + + KPKR_0 + No key release detected + 0 + + + KPKR_1 + All keys have been released + 0x1 + + + + + KDSC + Key Depress Synchronizer Clear + 2 + 1 + write-only + + + KDSC_0 + No effect + 0 + + + KDSC_1 + Set bits that clear the keypad depress synchronizer chain + 0x1 + + + + + KRSS + Key Release Synchronizer Set + 3 + 1 + write-only + + + KRSS_0 + No effect + 0 + + + KRSS_1 + Set bits which sets keypad release synchronizer chain + 0x1 + + + + + KDIE + Keypad Key Depress Interrupt Enable + 8 + 1 + read-write + + + KDIE_0 + No interrupt request is generated when KPKD is set. + 0 + + + KDIE_1 + An interrupt request is generated when KPKD is set. + 0x1 + + + + + KRIE + Keypad Release Interrupt Enable + 9 + 1 + read-write + + + KRIE_0 + No interrupt request is generated when KPKR is set. + 0 + + + KRIE_1 + An interrupt request is generated when KPKR is set. + 0x1 + + + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + Keypad Row Data Direction + 0 + 8 + read-write + + + INPUT + ROWn pin configured as an input. + 0 + + + OUTPUT + ROWn pin configured as an output. + 0x1 + + + + + KCDD + Keypad Column Data Direction Register + 8 + 8 + read-write + + + INPUT + COLn pin is configured as an input. + 0 + + + OUTPUT + COLn pin is configured as an output. + 0x1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + Keypad Row Data + 0 + 8 + read-write + + + KCD + Keypad Column Data + 8 + 8 + read-write + + + + + + + FLEXSPI + FlexSPI + FlexSPI + 0x402A8000 + + 0 + 0x400 + registers + + + FLEXSPI + 108 + + + + MCR0 + Module Control Register 0 + 0 + 32 + read-write + 0xFFFF80C2 + 0xFFFFFFFF + + + SWRESET + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + RXCLKSRC + Sample Clock source selection for Flash Reading + 4 + 2 + read-write + + + RXCLKSRC_0 + Dummy Read strobe generated by FlexSPI Controller and loopback internally. + 0 + + + RXCLKSRC_1 + Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + 0x1 + + + RXCLKSRC_3 + Flash provided Read strobe and input from DQS pad + 0x3 + + + + + ARDFEN + Enable AHB bus Read Access to IP RX FIFO. + 6 + 1 + read-write + + + ARDFEN_0 + IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + 0 + + + ARDFEN_1 + IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + 0x1 + + + + + ATDFEN + Enable AHB bus Write Access to IP TX FIFO. + 7 + 1 + read-write + + + ATDFEN_0 + IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + 0 + + + ATDFEN_1 + IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + 0x1 + + + + + HSEN + Half Speed Serial Flash access Enable. + 11 + 1 + read-write + + + HSEN_0 + Disable divide by 2 of serial flash clock for half speed commands. + 0 + + + HSEN_1 + Enable divide by 2 of serial flash clock for half speed commands. + 0x1 + + + + + DOZEEN + Doze mode enable bit + 12 + 1 + read-write + + + DOZEEN_0 + Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + 0 + + + DOZEEN_1 + Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + 0x1 + + + + + COMBINATIONEN + This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + 13 + 1 + read-write + + + COMBINATIONEN_0 + Disable. + 0 + + + COMBINATIONEN_1 + Enable. + 0x1 + + + + + SCKFREERUNEN + This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + 14 + 1 + read-write + + + SCKFREERUNEN_0 + Disable. + 0 + + + SCKFREERUNEN_1 + Enable. + 0x1 + + + + + IPGRANTWAIT + Time out wait cycle for IP command grant. + 16 + 8 + read-write + + + AHBGRANTWAIT + Timeout wait cycle for AHB command grant. + 24 + 8 + read-write + + + + + MCR1 + Module Control Register 1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + AHBBUSWAIT + AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmited after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response + 0 + 16 + read-write + + + SEQWAIT + Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles + 16 + 16 + read-write + + + + + MCR2 + Module Control Register 2 + 0x8 + 32 + read-write + 0x200081F7 + 0xFFFFFFFF + + + CLRAHBBUFOPT + This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + 11 + 1 + read-write + + + CLRAHBBUFOPT_0 + AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + 0 + + + CLRAHBBUFOPT_1 + AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + 0x1 + + + + + CLRLEARNPHASE + The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately. + 14 + 1 + read-write + + + SAMEDEVICEEN + All external devices are same devices (both in types and size) for A1/A2/B1/B2. + 15 + 1 + read-write + + + SAMEDEVICEEN_0 + In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + 0 + + + SAMEDEVICEEN_1 + FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + 0x1 + + + + + SCKBDIFFOPT + SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. + 19 + 1 + read-write + + + SCKBDIFFOPT_0 + SCKB pad is used as port B SCK clock output. Port B flash access is available. + 0 + + + SCKBDIFFOPT_1 + SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + 0x1 + + + + + RESUMEWAIT + Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. + 24 + 8 + read-write + + + + + AHBCR + AHB Bus Control Register + 0xC + 32 + read-write + 0x18 + 0xFFFFFFFF + + + APAREN + Parallel mode enabled for AHB triggered Command (both read and write) . + 0 + 1 + read-write + + + APAREN_0 + Flash will be accessed in Individual mode. + 0 + + + APAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + CACHABLEEN + Enable AHB bus cachable read access support. + 3 + 1 + read-write + + + CACHABLEEN_0 + Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + 0 + + + CACHABLEEN_1 + Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + 0x1 + + + + + BUFFERABLEEN + Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + 4 + 1 + read-write + + + BUFFERABLEEN_0 + Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + 0 + + + BUFFERABLEEN_1 + Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + 0x1 + + + + + PREFETCHEN + AHB Read Prefetch Enable. + 5 + 1 + read-write + + + READADDROPT + AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + 6 + 1 + read-write + + + READADDROPT_0 + There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + 0 + + + READADDROPT_1 + There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement. + 0x1 + + + + + + + INTEN + Interrupt Enable Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP triggered Command Sequences Execution finished interrupt enable. + 0 + 1 + read-write + + + IPCMDGEEN + IP triggered Command Sequences Grant Timeout interrupt enable. + 1 + 1 + read-write + + + AHBCMDGEEN + AHB triggered Command Sequences Grant Timeout interrupt enable. + 2 + 1 + read-write + + + IPCMDERREN + IP triggered Command Sequences Error Detected interrupt enable. + 3 + 1 + read-write + + + AHBCMDERREN + AHB triggered Command Sequences Error Detected interrupt enable. + 4 + 1 + read-write + + + IPRXWAEN + IP RX FIFO WaterMark available interrupt enable. + 5 + 1 + read-write + + + IPTXWEEN + IP TX FIFO WaterMark empty interrupt enable. + 6 + 1 + read-write + + + SCKSTOPBYRDEN + SCK is stopped during command sequence because Async RX FIFO full interrupt enable. + 8 + 1 + read-write + + + SCKSTOPBYWREN + SCK is stopped during command sequence because Async TX FIFO empty interrupt enable. + 9 + 1 + read-write + + + AHBBUSTIMEOUTEN + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + + + SEQTIMEOUTEN + Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. + 11 + 1 + read-write + + + + + INTR + Interrupt Register + 0x14 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + IPCMDDONE + IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated. + 0 + 1 + read-write + oneToClear + + + IPCMDGE + IP triggered Command Sequences Grant Timeout interrupt. + 1 + 1 + read-write + oneToClear + + + AHBCMDGE + AHB triggered Command Sequences Grant Timeout interrupt. + 2 + 1 + read-write + oneToClear + + + IPCMDERR + IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all. + 3 + 1 + read-write + oneToClear + + + AHBCMDERR + AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all. + 4 + 1 + read-write + oneToClear + + + IPRXWA + IP RX FIFO watermark available interrupt. + 5 + 1 + read-write + oneToClear + + + IPTXWE + IP TX FIFO watermark empty interrupt. + 6 + 1 + read-write + oneToClear + + + SCKSTOPBYRD + SCK is stopped during command sequence because Async RX FIFO full interrupt. + 8 + 1 + read-write + oneToClear + + + SCKSTOPBYWR + SCK is stopped during command sequence because Async TX FIFO empty interrupt. + 9 + 1 + read-write + oneToClear + + + AHBBUSTIMEOUT + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + oneToClear + + + SEQTIMEOUT + Sequence execution timeout interrupt. + 11 + 1 + read-write + oneToClear + + + + + LUTKEY + LUT Key Register + 0x18 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The Key to lock or unlock LUT. + 0 + 32 + read-write + + + + + LUTCR + LUT Control Register + 0x1C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Lock LUT + 0 + 1 + read-write + + + UNLOCK + Unlock LUT + 1 + 1 + read-write + + + + + AHBRXBUF0CR0 + AHB RX Buffer 0 Control Register 0 + 0x20 + 32 + read-write + 0x80000020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF1CR0 + AHB RX Buffer 1 Control Register 0 + 0x24 + 32 + read-write + 0x80010020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF2CR0 + AHB RX Buffer 2 Control Register 0 + 0x28 + 32 + read-write + 0x80020020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF3CR0 + AHB RX Buffer 3 Control Register 0 + 0x2C + 32 + read-write + 0x80030020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + FLSHA1CR0 + Flash A1 Control Register 0 + 0x60 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHA2CR0 + Flash A2 Control Register 0 + 0x64 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB1CR0 + Flash B1 Control Register 0 + 0x68 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB2CR0 + Flash B2 Control Register 0 + 0x6C + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR1%s + Flash A1 Control Register 1 + 0x70 + 32 + read-write + 0x63 + 0xFFFFFFFF + + + TCSS + Serial Flash CS setup time. + 0 + 5 + read-write + + + TCSH + Serial Flash CS Hold time. + 5 + 5 + read-write + + + WA + Word Addressable. + 10 + 1 + read-write + + + CAS + Column Address Size. + 11 + 4 + read-write + + + CSINTERVALUNIT + CS interval unit + 15 + 1 + read-write + + + CSINTERVALUNIT_0 + The CS interval unit is 1 serial clock cycle + 0 + + + CSINTERVALUNIT_1 + The CS interval unit is 256 serial clock cycle + 0x1 + + + + + CSINTERVAL + This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0. + 16 + 16 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR2%s + Flash A1 Control Register 2 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARDSEQID + Sequence Index for AHB Read triggered Command in LUT. + 0 + 4 + read-write + + + ARDSEQNUM + Sequence Number for AHB Read triggered Command in LUT. + 5 + 3 + read-write + + + AWRSEQID + Sequence Index for AHB Write triggered Command. + 8 + 4 + read-write + + + AWRSEQNUM + Sequence Number for AHB Write triggered Command. + 13 + 3 + read-write + + + AWRWAIT + For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface + 16 + 12 + read-write + + + AWRWAITUNIT + AWRWAIT unit + 28 + 3 + read-write + + + AWRWAITUNIT_0 + The AWRWAIT unit is 2 ahb clock cycle + 0 + + + AWRWAITUNIT_1 + The AWRWAIT unit is 8 ahb clock cycle + 0x1 + + + AWRWAITUNIT_2 + The AWRWAIT unit is 32 ahb clock cycle + 0x2 + + + AWRWAITUNIT_3 + The AWRWAIT unit is 128 ahb clock cycle + 0x3 + + + AWRWAITUNIT_4 + The AWRWAIT unit is 512 ahb clock cycle + 0x4 + + + AWRWAITUNIT_5 + The AWRWAIT unit is 2048 ahb clock cycle + 0x5 + + + AWRWAITUNIT_6 + The AWRWAIT unit is 8192 ahb clock cycle + 0x6 + + + AWRWAITUNIT_7 + The AWRWAIT unit is 32768 ahb clock cycle + 0x7 + + + + + CLRINSTRPTR + Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. + 31 + 1 + read-write + + + + + FLSHCR4 + Flash Control Register 4 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMOPT1 + Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + 0 + 1 + read-write + + + WMOPT1_0 + DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0 + + + WMOPT1_1 + DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0x1 + + + + + WMENA + Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + 2 + 1 + read-write + + + WMENA_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENA_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + WMENB + Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + 3 + 1 + read-write + + + WMENB_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENB_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + + + IPCR0 + IP Control Register 0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFAR + Serial Flash Address for IP command. + 0 + 32 + read-write + + + + + IPCR1 + IP Control Register 1 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + Flash Read/Program Data Size (in Bytes) for IP command. + 0 + 16 + read-write + + + ISEQID + Sequence Index in LUT for IP command. + 16 + 4 + read-write + + + ISEQNUM + Sequence Number for IP command: ISEQNUM+1. + 24 + 3 + read-write + + + IPAREN + Parallel mode Enabled for IP command. + 31 + 1 + read-write + + + IPAREN_0 + Flash will be accessed in Individual mode. + 0 + + + IPAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + + + IPCMD + IP Command Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRG + Setting this bit will trigger an IP Command. + 0 + 1 + read-write + + + + + IPRXFCR + IP RX FIFO Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPRXF + Clear all valid data entries in IP RX FIFO. + 0 + 1 + read-write + + + RXDMAEN + IP RX FIFO reading by DMA enabled. + 1 + 1 + read-write + + + RXDMAEN_0 + IP RX FIFO would be read by processor. + 0 + + + RXDMAEN_1 + IP RX FIFO would be read by DMA. + 0x1 + + + + + RXWMRK + Watermark level is (RXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + IPTXFCR + IP TX FIFO Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPTXF + Clear all valid data entries in IP TX FIFO. + 0 + 1 + read-write + + + TXDMAEN + IP TX FIFO filling by DMA enabled. + 1 + 1 + read-write + + + TXDMAEN_0 + IP TX FIFO would be filled by processor. + 0 + + + TXDMAEN_1 + IP TX FIFO would be filled by DMA. + 0x1 + + + + + TXWMRK + Watermark level is (TXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + 2 + 0x4 + A,B + DLLCR%s + DLL Control Register 0 + 0xC0 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DLLEN + DLL calibration enable. + 0 + 1 + read-write + + + DLLRESET + Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). + 1 + 1 + read-write + + + SLVDLYTARGET + The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock). + 3 + 4 + read-write + + + OVRDEN + Slave clock delay line delay cell number selection override enable. + 8 + 1 + read-write + + + OVRDVAL + Slave clock delay line delay cell number selection override value. + 9 + 6 + read-write + + + + + STS0 + Status Register 0 + 0xE0 + 32 + read-only + 0x3 + 0xFFFFFFFF + + + SEQIDLE + This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. + 0 + 1 + read-only + + + ARBIDLE + This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. + 1 + 1 + read-only + + + ARBCMDSRC + This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + 2 + 2 + read-only + + + ARBCMDSRC_0 + Triggered by AHB read command (triggered by AHB read). + 0 + + + ARBCMDSRC_1 + Triggered by AHB write command (triggered by AHB Write). + 0x1 + + + ARBCMDSRC_2 + Triggered by IP command (triggered by setting register bit IPCMD.TRG). + 0x2 + + + ARBCMDSRC_3 + Triggered by suspended command (resumed). + 0x3 + + + + + + + STS1 + Status Register 1 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHBCMDERRID + Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 0 + 4 + read-only + + + AHBCMDERRCODE + Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 8 + 4 + read-only + + + AHBCMDERRCODE_0 + No error. + 0 + + + AHBCMDERRCODE_2 + AHB Write command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + AHBCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + AHBCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + AHBCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + AHBCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + + + IPCMDERRID + Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 16 + 4 + read-only + + + IPCMDERRCODE + Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 24 + 4 + read-only + + + IPCMDERRCODE_0 + No error. + 0 + + + IPCMDERRCODE_2 + IP command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + IPCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + IPCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + IPCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + IPCMDERRCODE_6 + Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + 0x6 + + + IPCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + IPCMDERRCODE_15 + Flash boundary crossed. + 0xF + + + + + + + STS2 + Status Register 2 + 0xE8 + 32 + read-only + 0x1000100 + 0xFFFFFFFF + + + ASLVLOCK + Flash A sample clock slave delay line locked. + 0 + 1 + read-only + + + AREFLOCK + Flash A sample clock reference delay line locked. + 1 + 1 + read-only + + + ASLVSEL + Flash A sample clock slave delay line delay cell number selection . + 2 + 6 + read-only + + + AREFSEL + Flash A sample clock reference delay line delay cell number selection. + 8 + 6 + read-only + + + BSLVLOCK + Flash B sample clock slave delay line locked. + 16 + 1 + read-only + + + BREFLOCK + Flash B sample clock reference delay line locked. + 17 + 1 + read-only + + + BSLVSEL + Flash B sample clock slave delay line delay cell number selection. + 18 + 6 + read-only + + + BREFSEL + Flash B sample clock reference delay line delay cell number selection. + 24 + 6 + read-only + + + + + AHBSPNDSTS + AHB Suspend Status Register + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + ACTIVE + Indicates if an AHB read prefetch command sequence has been suspended. + 0 + 1 + read-only + + + BUFID + AHB RX BUF ID for suspended command sequence. + 1 + 3 + read-only + + + DATLFT + Left Data size for suspended command sequence (in byte). + 16 + 16 + read-only + + + + + IPRXFSTS + IP RX FIFO Status Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP RX FIFO. + 0 + 8 + read-only + + + RDCNTR + Total Read Data Counter: RDCNTR * 64 Bits. + 16 + 16 + read-only + + + + + IPTXFSTS + IP TX FIFO Status Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP TX FIFO. + 0 + 8 + read-only + + + WRCNTR + Total Write Data Counter: WRCNTR * 64 Bits. + 16 + 16 + read-only + + + + + 32 + 0x4 + RFDR[%s] + IP RX FIFO Data Register 0 + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-only + + + + + 32 + 0x4 + TFDR[%s] + IP TX FIFO Data Register 0 + 0x180 + 32 + write-only + 0 + 0xFFFFFFFF + + + TXDATA + TX Data + 0 + 32 + write-only + + + + + 64 + 0x4 + LUT[%s] + LUT 0 + 0x200 + 32 + read-write + 0 + 0 + + + OPERAND0 + OPERAND0 + 0 + 8 + read-write + + + NUM_PADS0 + NUM_PADS0 + 8 + 2 + read-write + + + OPCODE0 + OPCODE + 10 + 6 + read-write + + + OPERAND1 + OPERAND1 + 16 + 8 + read-write + + + NUM_PADS1 + NUM_PADS1 + 24 + 2 + read-write + + + OPCODE1 + OPCODE1 + 26 + 6 + read-write + + + + + + + PXP + PXP v2.0 Register Reference Index + PXP + PXP_ + 0x402B4000 + + 0 + 0x444 + registers + + + PXP + 44 + + + + CTRL + Control Register 0 + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + IRQ_ENABLE + Interrupt enable + 1 + 1 + read-write + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 12 + 10 + read-only + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 24 + 4 + read-only + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + RSVD4 + Reserved, always set to zero. + 29 + 1 + read-only + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal PXP operation + 31 + 1 + read-write + + + + + CTRL_SET + Control Register 0 + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + IRQ_ENABLE + Interrupt enable + 1 + 1 + read-write + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 12 + 10 + read-only + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 24 + 4 + read-only + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + RSVD4 + Reserved, always set to zero. + 29 + 1 + read-only + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal PXP operation + 31 + 1 + read-write + + + + + CTRL_CLR + Control Register 0 + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + IRQ_ENABLE + Interrupt enable + 1 + 1 + read-write + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 12 + 10 + read-only + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 24 + 4 + read-only + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + RSVD4 + Reserved, always set to zero. + 29 + 1 + read-only + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal PXP operation + 31 + 1 + read-write + + + + + CTRL_TOG + Control Register 0 + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + IRQ_ENABLE + Interrupt enable + 1 + 1 + read-write + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 2 + 1 + read-write + + + ENABLE_LCD_HANDSHAKE + Enable handshake with LCD controller + 4 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + ROTATE + Indicates the clockwise rotation to be applied at the output buffer + 8 + 2 + read-write + + + ROT_0 + ROT_0 + 0 + + + ROT_90 + ROT_90 + 0x1 + + + ROT_180 + ROT_180 + 0x2 + + + ROT_270 + ROT_270 + 0x3 + + + + + HFLIP + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 10 + 1 + read-write + + + VFLIP + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 11 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 12 + 10 + read-only + + + ROT_POS + This bit controls where rotation will occur in the PXP datapath + 22 + 1 + read-write + + + BLOCK_SIZE + Select the block size to process. + 23 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 24 + 4 + read-only + + + EN_REPEAT + Enable the PXP to run continuously + 28 + 1 + read-write + + + RSVD4 + Reserved, always set to zero. + 29 + 1 + read-only + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal PXP operation + 31 + 1 + read-write + + + + + STAT + Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 9 + 7 + read-only + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + STAT_SET + Status Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 9 + 7 + read-only + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + STAT_CLR + Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 9 + 7 + read-only + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + STAT_TOG + Status Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ + Indicates current PXP interrupt status + 0 + 1 + read-write + + + AXI_WRITE_ERROR + Indicates PXP encountered an AXI write error and processing has been terminated. + 1 + 1 + read-write + + + AXI_READ_ERROR + Indicates PXP encountered an AXI read error and processing has been terminated. + 2 + 1 + read-write + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 3 + 1 + read-write + + + AXI_ERROR_ID + Indicates the AXI ID of the failing bus operation. + 4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 8 + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 9 + 7 + read-only + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 16 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 24 + 8 + read-only + + + + + OUT_CTRL + Output Buffer Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 10 + 13 + read-only + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_CTRL_SET + Output Buffer Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 10 + 13 + read-only + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_CTRL_CLR + Output Buffer Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 10 + 13 + read-only + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_CTRL_TOG + Output Buffer Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + RSVD0 + Reserved, always set to zero. + 5 + 3 + read-only + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 10 + 13 + read-only + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL[ALPHA] + 23 + 1 + read-write + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 24 + 8 + read-write + + + + + OUT_BUF + Output Frame Buffer Pointer + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + OUT_BUF2 + Output Frame Buffer Pointer #2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + OUT_PITCH + Output Buffer Pitch + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 16 + 16 + read-only + + + + + OUT_LRC + Output Surface Lower Right Coordinate + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + Indicates the number of vertical PIXELS in the output surface (non-rotated) + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 14 + 2 + read-only + + + X + Indicates number of horizontal PIXELS in the output surface (non-rotated) + 16 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 30 + 2 + read-only + + + + + OUT_PS_ULC + Processed Surface Upper Left Coordinate + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 14 + 2 + read-only + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer + 16 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 30 + 2 + read-only + + + + + OUT_PS_LRC + Processed Surface Lower Right Coordinate + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 14 + 2 + read-only + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer + 16 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 30 + 2 + read-only + + + + + OUT_AS_ULC + Alpha Surface Upper Left Coordinate + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 14 + 2 + read-only + + + X + This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 16 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 30 + 2 + read-only + + + + + OUT_AS_LRC + Alpha Surface Lower Right Coordinate + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 14 + 2 + read-only + + + X + This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 16 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 30 + 2 + read-only + + + + + PS_CTRL + Processed Surface (PS) Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 5 + read-write + + + RGB888 + 32-bit pixels (unpacked 24-bit format) + 0x4 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 5 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 6 + 2 + read-only + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 12 + 20 + read-only + + + + + PS_CTRL_SET + Processed Surface (PS) Control Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 5 + read-write + + + RGB888 + 32-bit pixels (unpacked 24-bit format) + 0x4 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 5 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 6 + 2 + read-only + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 12 + 20 + read-only + + + + + PS_CTRL_CLR + Processed Surface (PS) Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 5 + read-write + + + RGB888 + 32-bit pixels (unpacked 24-bit format) + 0x4 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 5 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 6 + 2 + read-only + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 12 + 20 + read-only + + + + + PS_CTRL_TOG + Processed Surface (PS) Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 5 + read-write + + + RGB888 + 32-bit pixels (unpacked 24-bit format) + 0x4 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 5 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 6 + 2 + read-only + + + DECY + Verticle pre decimation filter control. + 8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 10 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 12 + 20 + read-only + + + + + PS_BUF + PS Input Buffer Address + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + PS_UBUF + PS U/Cb or 2 Plane UV Input Buffer Address + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer. + 0 + 32 + read-write + + + + + PS_VBUF + PS V/Cr Input Buffer Address + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS V/Cr Chroma input buffer. + 0 + 32 + read-write + + + + + PS_PITCH + Processed Surface Pitch + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 16 + 16 + read-only + + + + + PS_BACKGROUND + PS Background Color + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + COLOR + Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC + 0 + 24 + read-write + + + RSVD + Reserved, always set to zero. + 24 + 8 + read-only + + + + + PS_SCALE + PS Scale Factor Register + 0x110 + 32 + read-write + 0x10001000 + 0xFFFFFFFF + + + XSCALE + This is a two bit integer and 12 bit fractional representation (## + 0 + 15 + read-write + + + RSVD1 + Reserved, always set to zero. + 15 + 1 + read-only + + + YSCALE + This is a two bit integer and 12 bit fractional representation (## + 16 + 15 + read-write + + + RSVD2 + Reserved, always set to zero. + 31 + 1 + read-only + + + + + PS_OFFSET + PS Scale Offset Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + XOFFSET + This is a 12 bit fractional representation (0 + 0 + 12 + read-write + + + RSVD1 + Reserved, always set to zero. + 12 + 4 + read-only + + + YOFFSET + This is a 12 bit fractional representation (0 + 16 + 12 + read-write + + + RSVD2 + Reserved, always set to zero. + 28 + 4 + read-only + + + + + PS_CLRKEYLOW + PS Color Key Low + 0x130 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 24 + 8 + read-only + + + + + PS_CLRKEYHIGH + PS Color Key High + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 24 + 8 + read-only + + + + + AS_CTRL + Alpha Surface Control + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved, always set to zero. + 0 + 1 + read-only + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 1 + 2 + read-write + + + Embedded + Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + 0 + + + Override + Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + 0x1 + + + Multiply + Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. + 0x2 + + + ROPs + Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + 0x3 + + + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 3 + 1 + read-write + + + FORMAT + Indicates the input buffer format for AS. + 4 + 4 + read-write + + + ARGB8888 + 32-bit pixels with alpha + 0 + + + RGB888 + 32-bit pixels without alpha (unpacked 24-bit format) + 0x4 + + + ARGB1555 + 16-bit pixels with alpha + 0x8 + + + ARGB4444 + 16-bit pixels with alpha + 0x9 + + + RGB555 + 16-bit pixels without alpha + 0xC + + + RGB444 + 16-bit pixels without alpha + 0xD + + + RGB565 + 16-bit pixels without alpha + 0xE + + + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in PXP_AS_CTRL[ALPHA_CTRL] + 8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 16 + 4 + read-write + + + MASKAS + AS AND PS + 0 + + + MASKNOTAS + nAS AND PS + 0x1 + + + MASKASNOT + AS AND nPS + 0x2 + + + MERGEAS + AS OR PS + 0x3 + + + MERGENOTAS + nAS OR PS + 0x4 + + + MERGEASNOT + AS OR nPS + 0x5 + + + NOTCOPYAS + nAS + 0x6 + + + NOT + nPS + 0x7 + + + NOTMASKAS + AS NAND PS + 0x8 + + + NOTMERGEAS + AS NOR PS + 0x9 + + + XORAS + AS XOR PS + 0xA + + + NOTXORAS + AS XNOR PS + 0xB + + + + + ALPHA_INVERT + Setting this bit to logic 0 will not alter the alpha value + 20 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 21 + 11 + read-only + + + + + AS_BUF + Alpha Surface Buffer Pointer + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + AS_PITCH + Alpha Surface Pitch + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 16 + 16 + read-only + + + + + AS_CLRKEYLOW + Overlay Color Key Low + 0x180 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 24 + 8 + read-only + + + + + AS_CLRKEYHIGH + Overlay Color Key High + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 24 + 8 + read-only + + + + + CSC1_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1A0 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data + 0 + 9 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data + 9 + 9 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 29 + 1 + read-only + + + BYPASS + Bypass the CSC unit in the scaling engine + 30 + 1 + read-write + + + YCBCR_MODE + Set to 1 when performing YCbCr conversion to RGB + 31 + 1 + read-write + + + + + CSC1_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1B0 + 32 + read-write + 0x1230208 + 0xFFFFFFFF + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 11 + 5 + read-only + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) + 16 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 27 + 5 + read-only + + + + + CSC1_COEF2 + Color Space Conversion Coefficient Register 2 + 0x1C0 + 32 + read-write + 0x79B076C + 0xFFFFFFFF + + + C3 + Two's complement Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 11 + 5 + read-only + + + C2 + Two's complement Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) + 16 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 27 + 5 + read-only + + + + + POWER + PXP Power Control Register + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROT_MEM_LP_STATE + Select the low power state of the ROT memory. + 9 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + CTRL + Power control for the PXP. + 12 + 20 + read-write + + + + + NEXT + Next Frame Pointer + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLED + Indicates that the "next frame" functionality has been enabled + 0 + 1 + read-only + + + RSVD + Reserved, always set to zero. + 1 + 1 + read-only + + + POINTER + A pointer to a data structure containing register values to be used when processing the next frame + 2 + 30 + read-write + + + + + PORTER_DUFF_CTRL + PXP Alpha Engine A Control Register. + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + POTER_DUFF_ENABLE + poter_duff enable + 0 + 1 + read-write + + + S0_S1_FACTOR_MODE + s0 to s1 factor mode + 1 + 2 + read-write + + + S0_GLOBAL_ALPHA_MODE + s0 global alpha mode + 3 + 2 + read-write + + + S0_ALPHA_MODE + s0 alpha mode + 5 + 1 + read-write + + + S0_COLOR_MODE + s0 color mode + 6 + 1 + read-write + + + S1_S0_FACTOR_MODE + s1 to s0 factor mode + 8 + 2 + read-write + + + S1_GLOBAL_ALPHA_MODE + s1 global alpha mode + 10 + 2 + read-write + + + S1_ALPHA_MODE + s1 alpha mode + 12 + 1 + read-write + + + S1_COLOR_MODE + s1 color mode + 13 + 1 + read-write + + + S0_GLOBAL_ALPHA + s0 global alpha + 16 + 8 + read-write + + + S1_GLOBAL_ALPHA + s1 global alpha + 24 + 8 + read-write + + + + + + + LCDIF + LCDIF Register Reference Index + LCDIF + LCDIF_ + 0x402B8000 + + 0 + 0xB44 + registers + + + LCDIF + 42 + + + + CTRL + LCDIF General Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_SET + LCDIF General Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_CLR + LCDIF General Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL_TOG + LCDIF General Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 3 + 1 + read-write + + + MASTER + Set this bit to make the LCDIF act as a bus master + 5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on + 6 + 1 + read-write + + + WORD_LENGTH + Input data format. + 8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 10 + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 12 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 14 + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 17 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 19 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 21 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data. + 26 + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + CLKGATE + This bit must be set to zero for normal operation + 30 + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the LCDIF + 31 + 1 + read-write + + + + + CTRL1 + LCDIF General Control1 Register + 0x10 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL1_SET + LCDIF General Control1 Register + 0x14 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL1_CLR + LCDIF General Control1 Register + 0x18 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL1_TOG + LCDIF General Control1 Register + 0x1C + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 10 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 11 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 12 + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 13 + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 14 + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 15 + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 16 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 20 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 21 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 22 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field + 23 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 24 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the LCDIF block + 25 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the LCDIF master mode. + 26 + 1 + read-write + + + CS_OUT_SELECT + This bit is CS0/CS1 valid select signals + 30 + 1 + read-write + + + IMAGE_DATA_SELECT + Command Mode MIPI image data select bit + 31 + 1 + read-write + + + + + CTRL2 + LCDIF General Control2 Register + 0x20 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_SET + LCDIF General Control2 Register + 0x24 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_CLR + LCDIF General Control2 Register + 0x28 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + CTRL2_TOG + LCDIF General Control2 Register + 0x2C + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 12 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 16 + 3 + read-write + + + RGB + RGB + 0 + + + RBG + RBG + 0x1 + + + GBR + GBR + 0x2 + + + GRB + GRB + 0x3 + + + BRG + BRG + 0x4 + + + BGR + BGR + 0x5 + + + + + BURST_LEN_8 + By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 20 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master + 21 + 3 + read-write + + + REQ_1 + REQ_1 + 0 + + + REQ_2 + REQ_2 + 0x1 + + + REQ_4 + REQ_4 + 0x2 + + + REQ_8 + REQ_8 + 0x3 + + + REQ_16 + REQ_16 + 0x4 + + + + + + + TRANSFER_COUNT + LCDIF Horizontal and Vertical Valid Data Count Register + 0x30 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + H_COUNT + Total valid data (pixels) in each horizontal line + 0 + 16 + read-write + + + V_COUNT + Number of horizontal lines per frame which contain valid data + 16 + 16 + read-write + + + + + CUR_BUF + LCD Interface Current Buffer Address Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the current frame being transmitted by LCDIF. + 0 + 32 + read-write + + + + + NEXT_BUF + LCD Interface Next Buffer Address Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by LCDIF. + 0 + 32 + read-write + + + + + VDCTRL0 + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL0_SET + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL0_CLR + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL0_TOG + LCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 18 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 19 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 20 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 21 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 24 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 25 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 26 + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 27 + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 28 + 1 + read-write + + + + + VDCTRL1 + LCDIF VSYNC Mode and Dotclk Mode Control Register1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PERIOD + Total number of units between two positive or two negative edges of the VSYNC signal + 0 + 32 + read-write + + + + + VDCTRL2 + LCDIF VSYNC Mode and Dotclk Mode Control Register2 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSYNC_PERIOD + Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal + 0 + 18 + read-write + + + HSYNC_PULSE_WIDTH + Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active. + 18 + 14 + read-write + + + + + VDCTRL3 + LCDIF VSYNC Mode and Dotclk Mode Control Register3 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + VERTICAL_WAIT_CNT + In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set + 0 + 16 + read-write + + + HORIZONTAL_WAIT_CNT + In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins + 16 + 12 + read-write + + + VSYNC_ONLY + This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. + 28 + 1 + read-write + + + MUX_SYNC_SIGNALS + When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins + 29 + 1 + read-write + + + + + VDCTRL4 + LCDIF VSYNC Mode and Dotclk Mode Control Register4 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOTCLK_H_VALID_DATA_CNT + Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode + 0 + 18 + read-write + + + SYNC_SIGNALS_ON + Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end + 18 + 1 + read-write + + + DOTCLK_DLY_SEL + This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin + 29 + 3 + read-write + + + + + BM_ERROR_STAT + Bus Master Error Status Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Virtual address at which bus master error occurred. + 0 + 32 + read-write + + + + + CRC_STAT + CRC Status Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_VALUE + Calculated CRC value. + 0 + 32 + read-write + + + + + STAT + LCD Interface Status Register + 0x1B0 + 32 + read-only + 0x95000000 + 0xFFFFFFFF + + + LFIFO_COUNT + Read only view of the current count in Latency buffer (LFIFO). + 0 + 9 + read-only + + + TXFIFO_EMPTY + Read only view of the signals that indicates LCD TXFIFO is empty. + 26 + 1 + read-only + + + TXFIFO_FULL + Read only view of the signals that indicates LCD TXFIFO is full. + 27 + 1 + read-only + + + LFIFO_EMPTY + Read only view of the signals that indicates LCD LFIFO is empty. + 28 + 1 + read-only + + + LFIFO_FULL + Read only view of the signals that indicates LCD LFIFO is full. + 29 + 1 + read-only + + + DMA_REQ + Reflects the current state of the DMA Request line for the LCDIF + 30 + 1 + read-only + + + PRESENT + 0: LCDIF not present on this product 1: LCDIF is present. + 31 + 1 + read-only + + + + + THRES + LCDIF Threshold Register + 0x200 + 32 + read-write + 0x100000F + 0xFFFFFFFF + + + PANIC + This value should be set to a value of pixels from 0 to 511 + 0 + 9 + read-write + + + FASTCLOCK + This value should be set to a value of pixels, from 0 to 511 + 16 + 9 + read-write + + + + + PIGEONCTRL0 + LCDIF Pigeon Mode Control0 Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL0_SET + LCDIF Pigeon Mode Control0 Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL0_CLR + LCDIF Pigeon Mode Control0 Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL0_TOG + LCDIF Pigeon Mode Control0 Register + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + Period of line counter during FD phase + 0 + 12 + read-write + + + LD_PERIOD + Period of pclk counter during LD phase + 16 + 12 + read-write + + + + + PIGEONCTRL1 + LCDIF Pigeon Mode Control1 Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL1_SET + LCDIF Pigeon Mode Control1 Register + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL1_CLR + LCDIF Pigeon Mode Control1 Register + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL1_TOG + LCDIF Pigeon Mode Control1 Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + Period of frame counter + 0 + 12 + read-write + + + FRAME_CNT_CYCLES + Max cycles of frame counter + 16 + 12 + read-write + + + + + PIGEONCTRL2 + LCDIF Pigeon Mode Control2 Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEONCTRL2_SET + LCDIF Pigeon Mode Control2 Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEONCTRL2_CLR + LCDIF Pigeon Mode Control2 Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEONCTRL2_TOG + LCDIF Pigeon Mode Control2 Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PIGEON_DATA_EN + Pigeon mode data enable + 0 + 1 + read-write + + + PIGEON_CLK_GATE + Pigeon mode dot clock gate enable + 1 + 1 + read-write + + + + + PIGEON_0_0 + Panel Interface Signal Generator Register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_0_1 + Panel Interface Signal Generator Register + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_0_2 + Panel Interface Signal Generator Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_1_0 + Panel Interface Signal Generator Register + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_1_1 + Panel Interface Signal Generator Register + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_1_2 + Panel Interface Signal Generator Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_2_0 + Panel Interface Signal Generator Register + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_2_1 + Panel Interface Signal Generator Register + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_2_2 + Panel Interface Signal Generator Register + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_3_0 + Panel Interface Signal Generator Register + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_3_1 + Panel Interface Signal Generator Register + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_3_2 + Panel Interface Signal Generator Register + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_4_0 + Panel Interface Signal Generator Register + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_4_1 + Panel Interface Signal Generator Register + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_4_2 + Panel Interface Signal Generator Register + 0x920 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_5_0 + Panel Interface Signal Generator Register + 0x940 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_5_1 + Panel Interface Signal Generator Register + 0x950 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_5_2 + Panel Interface Signal Generator Register + 0x960 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_6_0 + Panel Interface Signal Generator Register + 0x980 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_6_1 + Panel Interface Signal Generator Register + 0x990 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_6_2 + Panel Interface Signal Generator Register + 0x9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_7_0 + Panel Interface Signal Generator Register + 0x9C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_7_1 + Panel Interface Signal Generator Register + 0x9D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_7_2 + Panel Interface Signal Generator Register + 0x9E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_8_0 + Panel Interface Signal Generator Register + 0xA00 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_8_1 + Panel Interface Signal Generator Register + 0xA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_8_2 + Panel Interface Signal Generator Register + 0xA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_9_0 + Panel Interface Signal Generator Register + 0xA40 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_9_1 + Panel Interface Signal Generator Register + 0xA50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_9_2 + Panel Interface Signal Generator Register + 0xA60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_10_0 + Panel Interface Signal Generator Register + 0xA80 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_10_1 + Panel Interface Signal Generator Register + 0xA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_10_2 + Panel Interface Signal Generator Register + 0xAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_11_0 + Panel Interface Signal Generator Register + 0xAC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable pigeon Mode on this signal + 0 + 1 + read-write + + + POL + Polarity of signal output + 1 + 1 + read-write + + + ACTIVE_HIGH + Normal Signal (Active high) + 0 + + + ACTIVE_LOW + Inverted signal (Active low) + 0x1 + + + + + INC_SEL + Event to incrment local counter + 2 + 2 + read-write + + + PCLK + pclk + 0 + + + LINE + Line start pulse + 0x1 + + + FRAME + Frame start pulse + 0x2 + + + SIG_ANOTHER + Use another signal as tick event + 0x3 + + + + + OFFSET + offset on pclk unit + 4 + 4 + read-write + + + MASK_CNT_SEL + select global counters as mask condition, use together with MASK_CNT + 8 + 4 + read-write + + + HSTATE_CNT + pclk counter within one hscan state + 0 + + + HSTATE_CYCLE + pclk cycle within one hscan state + 0x1 + + + VSTATE_CNT + line counter within one vscan state + 0x2 + + + VSTATE_CYCLE + line cycle within one vscan state + 0x3 + + + FRAME_CNT + frame counter + 0x4 + + + FRAME_CYCLE + frame cycle + 0x5 + + + HCNT + horizontal counter (pclk counter within one line ) + 0x6 + + + VCNT + vertical counter (line counter within one frame) + 0x7 + + + + + MASK_CNT + When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking + 12 + 12 + read-write + + + STATE_MASK + state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking + 24 + 8 + read-write + + + FS + FRAME SYNC + 0x1 + + + FB + FRAME BEGIN + 0x2 + + + FD + FRAME DATA + 0x4 + + + FE + FRAME END + 0x8 + + + LS + LINE SYNC + 0x10 + + + LB + LINE BEGIN + 0x20 + + + LD + LINE DATA + 0x40 + + + LE + LINE END + 0x80 + + + + + + + PIGEON_11_1 + Panel Interface Signal Generator Register + 0xAD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + Assert signal output when counter match this value + 0 + 16 + read-write + + + START_ACTIVE + Start as active + 0 + + + + + CLR_CNT + Deassert signal output when counter match this value + 16 + 16 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + PIGEON_11_2 + Panel Interface Signal Generator Register + 0xAE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + Logic operation with another signal: DIS/AND/OR/COND + 0 + 4 + read-write + + + DIS + No logic operation + 0 + + + AND + sigout = sig_another AND this_sig + 0x1 + + + OR + sigout = sig_another OR this_sig + 0x2 + + + MASK + mask = sig_another AND other_masks + 0x3 + + + + + SIG_ANOTHER + Select another signal for logic operation or as mask or counter tick event + 4 + 5 + read-write + + + CLEAR_USING_MASK + Keep active until mask off + 0 + + + + + + + LUT_CTRL + Lookup Table Data Register. + 0xB00 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + LUT_BYPASS + Setting this bit will bypass the LUT memory resource completely + 0 + 1 + read-write + + + + + LUT0_ADDR + Lookup Table Control Register. + 0xB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + LUT indexed address pointer + 0 + 8 + read-write + + + + + LUT0_DATA + Lookup Table Data Register. + 0xB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register + 0 + 32 + read-write + + + + + LUT1_ADDR + Lookup Table Control Register. + 0xB30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + LUT indexed address pointer + 0 + 8 + read-write + + + + + LUT1_DATA + Lookup Table Data Register. + 0xB40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register + 0 + 32 + read-write + + + + + + + CSI + CSI + CSI + CSI_ + 0x402BC000 + + 0 + 0x50 + registers + + + CSI + 43 + + + + CSICR1 + CSI Control Register 1 + 0 + 32 + read-write + 0x40000800 + 0xFFFFFFFF + + + PIXEL_BIT + Pixel Bit + 0 + 1 + read-write + + + PIXEL_BIT_0 + 8-bit data for each pixel + 0 + + + PIXEL_BIT_1 + 10-bit data for each pixel + 0x1 + + + + + REDGE + Valid Pixel Clock Edge Select + 1 + 1 + read-write + + + REDGE_0 + Pixel data is latched at the falling edge of CSI_PIXCLK + 0 + + + REDGE_1 + Pixel data is latched at the rising edge of CSI_PIXCLK + 0x1 + + + + + INV_PCLK + Invert Pixel Clock Input + 2 + 1 + read-write + + + INV_PCLK_0 + CSI_PIXCLK is directly applied to internal circuitry + 0 + + + INV_PCLK_1 + CSI_PIXCLK is inverted before applied to internal circuitry + 0x1 + + + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. + 3 + 1 + read-write + + + INV_DATA_0 + CSI_D[7:0] data lines are directly applied to internal circuitry + 0 + + + INV_DATA_1 + CSI_D[7:0] data lines are inverted before applied to internal circuitry + 0x1 + + + + + GCLK_MODE + Gated Clock Mode Enable + 4 + 1 + read-write + + + GCLK_MODE_0 + Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + 0 + + + GCLK_MODE_1 + Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + 0x1 + + + + + CLR_RXFIFO + Asynchronous RXFIFO Clear + 5 + 1 + read-write + + + CLR_STATFIFO + Asynchronous STATFIFO Clear + 6 + 1 + read-write + + + PACK_DIR + Data Packing Direction + 7 + 1 + read-write + + + PACK_DIR_0 + Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + 0 + + + PACK_DIR_1 + Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + 0x1 + + + + + FCC + FIFO Clear Control + 8 + 1 + read-write + + + FCC_0 + Asynchronous FIFO clear is selected. + 0 + + + FCC_1 + Synchronous FIFO clear is selected. + 0x1 + + + + + CCIR_EN + CCIR656 Interface Enable + 10 + 1 + read-write + + + CCIR_EN_0 + Traditional interface is selected. Timing interface logic is used to latch data. + 0 + + + CCIR_EN_1 + CCIR656 interface is selected. + 0x1 + + + + + HSYNC_POL + HSYNC Polarity Select + 11 + 1 + read-write + + + HSYNC_POL_0 + HSYNC is active low + 0 + + + HSYNC_POL_1 + HSYNC is active high + 0x1 + + + + + SOF_INTEN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. + 16 + 1 + read-write + + + SOF_INTEN_0 + SOF interrupt disable + 0 + + + SOF_INTEN_1 + SOF interrupt enable + 0x1 + + + + + SOF_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. + 17 + 1 + read-write + + + SOF_POL_0 + SOF interrupt is generated on SOF falling edge + 0 + + + SOF_POL_1 + SOF interrupt is generated on SOF rising edge + 0x1 + + + + + RXFF_INTEN + RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. + 18 + 1 + read-write + + + RXFF_INTEN_0 + RxFIFO full interrupt disable + 0 + + + RXFF_INTEN_1 + RxFIFO full interrupt enable + 0x1 + + + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable + 19 + 1 + read-write + + + FB1_DMA_DONE_INTEN_0 + Frame Buffer1 DMA Transfer Done interrupt disable + 0 + + + FB1_DMA_DONE_INTEN_1 + Frame Buffer1 DMA Transfer Done interrupt enable + 0x1 + + + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable + 20 + 1 + read-write + + + FB2_DMA_DONE_INTEN_0 + Frame Buffer2 DMA Transfer Done interrupt disable + 0 + + + FB2_DMA_DONE_INTEN_1 + Frame Buffer2 DMA Transfer Done interrupt enable + 0x1 + + + + + STATFF_INTEN + STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. + 21 + 1 + read-write + + + STATFF_INTEN_0 + STATFIFO full interrupt disable + 0 + + + STATFF_INTEN_1 + STATFIFO full interrupt enable + 0x1 + + + + + SFF_DMA_DONE_INTEN + STATFIFO DMA Transfer Done Interrupt Enable + 22 + 1 + read-write + + + SFF_DMA_DONE_INTEN_0 + STATFIFO DMA Transfer Done interrupt disable + 0 + + + SFF_DMA_DONE_INTEN_1 + STATFIFO DMA Transfer Done interrupt enable + 0x1 + + + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. + 24 + 1 + read-write + + + RF_OR_INTEN_0 + RxFIFO overrun interrupt is disabled + 0 + + + RF_OR_INTEN_1 + RxFIFO overrun interrupt is enabled + 0x1 + + + + + SF_OR_INTEN + STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. + 25 + 1 + read-write + + + SF_OR_INTEN_0 + STATFIFO overrun interrupt is disabled + 0 + + + SF_OR_INTEN_1 + STATFIFO overrun interrupt is enabled + 0x1 + + + + + COF_INT_EN + Change Of Image Field (COF) Interrupt Enable + 26 + 1 + read-write + + + COF_INT_EN_0 + COF interrupt is disabled + 0 + + + COF_INT_EN_1 + COF interrupt is enabled + 0x1 + + + + + CCIR_MODE + CCIR Mode Select + 27 + 1 + read-write + + + CCIR_MODE_0 + Progressive mode is selected + 0 + + + CCIR_MODE_1 + Interlace mode is selected + 0x1 + + + + + PrP_IF_EN + CSI-PrP Interface Enable + 28 + 1 + read-write + + + PrP_IF_EN_0 + CSI to PrP bus is disabled + 0 + + + PrP_IF_EN_1 + CSI to PrP bus is enabled + 0x1 + + + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. + 29 + 1 + read-write + + + EOF_INT_EN_0 + EOF interrupt is disabled. + 0 + + + EOF_INT_EN_1 + EOF interrupt is generated when RX count value is reached. + 0x1 + + + + + EXT_VSYNC + External VSYNC Enable + 30 + 1 + read-write + + + EXT_VSYNC_0 + Internal VSYNC mode + 0 + + + EXT_VSYNC_1 + External VSYNC mode + 0x1 + + + + + SWAP16_EN + SWAP 16-Bit Enable + 31 + 1 + read-write + + + SWAP16_EN_0 + Disable swapping + 0 + + + SWAP16_EN_1 + Enable swapping + 0x1 + + + + + + + CSICR2 + CSI Control Register 2 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSC + Horizontal Skip Count + 0 + 8 + read-write + + + VSC + Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored. + 8 + 8 + read-write + + + LVRM + Live View Resolution Mode. Selects the grid size used for live view resolution. + 16 + 3 + read-write + + + LVRM_0 + 512 x 384 + 0 + + + LVRM_1 + 448 x 336 + 0x1 + + + LVRM_2 + 384 x 288 + 0x2 + + + LVRM_3 + 384 x 256 + 0x3 + + + LVRM_4 + 320 x 240 + 0x4 + + + LVRM_5 + 288 x 216 + 0x5 + + + LVRM_6 + 400 x 300 + 0x6 + + + + + BTS + Bayer Tile Start. Controls the Bayer pattern starting point. + 19 + 2 + read-write + + + BTS_0 + GR + 0 + + + BTS_1 + RG + 0x1 + + + BTS_2 + BG + 0x2 + + + BTS_3 + GB + 0x3 + + + + + SCE + Skip Count Enable. Enables or disables the skip count feature. + 23 + 1 + read-write + + + SCE_0 + Skip count disable + 0 + + + SCE_1 + Skip count enable + 0x1 + + + + + AFS + Auto Focus Spread. Selects which green pixels are used for auto-focus. + 24 + 2 + read-write + + + AFS_0 + Abs Diff on consecutive green pixels + 0 + + + AFS_1 + Abs Diff on every third green pixels + 0x1 + + + AFS_2 + Abs Diff on every four green pixels + #1x + + + + + DRM + Double Resolution Mode. Controls size of statistics grid. + 26 + 1 + read-write + + + DRM_0 + Stats grid of 8 x 6 + 0 + + + DRM_1 + Stats grid of 8 x 12 + 0x1 + + + + + DMA_BURST_TYPE_SFF + Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO. + 28 + 2 + read-write + + + DMA_BURST_TYPE_SFF_0 + INCR8 + #x0 + + + DMA_BURST_TYPE_SFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_SFF_3 + INCR16 + 0x3 + + + + + DMA_BURST_TYPE_RFF + Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO. + 30 + 2 + read-write + + + DMA_BURST_TYPE_RFF_0 + INCR8 + #x0 + + + DMA_BURST_TYPE_RFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_RFF_3 + INCR16 + 0x3 + + + + + + + CSICR3 + CSI Control Register 3 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ECC_AUTO_EN + Automatic Error Correction Enable + 0 + 1 + read-write + + + ECC_AUTO_EN_0 + Auto Error correction is disabled. + 0 + + + ECC_AUTO_EN_1 + Auto Error correction is enabled. + 0x1 + + + + + ECC_INT_EN + Error Detection Interrupt Enable + 1 + 1 + read-write + + + ECC_INT_EN_0 + No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + 0 + + + ECC_INT_EN_1 + Interrupt is generated when error is detected. + 0x1 + + + + + ZERO_PACK_EN + Dummy Zero Packing Enable + 2 + 1 + read-write + + + ZERO_PACK_EN_0 + Zero packing disabled + 0 + + + ZERO_PACK_EN_1 + Zero packing enabled + 0x1 + + + + + TWO_8BIT_SENSOR + Two 8-bit Sensor Mode + 3 + 1 + read-write + + + TWO_8BIT_SENSOR_0 + Only one sensor is connected. + 0 + + + TWO_8BIT_SENSOR_1 + Two 8-bit sensors are connected or one 16-bit sensor is connected. + 0x1 + + + + + RxFF_LEVEL + RxFIFO Full Level + 4 + 3 + read-write + + + RxFF_LEVEL_0 + 4 Double words + 0 + + + RxFF_LEVEL_1 + 8 Double words + 0x1 + + + RxFF_LEVEL_2 + 16 Double words + 0x2 + + + RxFF_LEVEL_3 + 24 Double words + 0x3 + + + RxFF_LEVEL_4 + 32 Double words + 0x4 + + + RxFF_LEVEL_5 + 48 Double words + 0x5 + + + RxFF_LEVEL_6 + 64 Double words + 0x6 + + + RxFF_LEVEL_7 + 96 Double words + 0x7 + + + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse error interrupt. + 7 + 1 + read-write + + + HRESP_ERR_EN_0 + Disable hresponse error interrupt + 0 + + + HRESP_ERR_EN_1 + Enable hresponse error interrupt + 0x1 + + + + + STATFF_LEVEL + STATFIFO Full Level + 8 + 3 + read-write + + + STATFF_LEVEL_0 + 4 Double words + 0 + + + STATFF_LEVEL_1 + 8 Double words + 0x1 + + + STATFF_LEVEL_2 + 12 Double words + 0x2 + + + STATFF_LEVEL_3 + 16 Double words + 0x3 + + + STATFF_LEVEL_4 + 24 Double words + 0x4 + + + STATFF_LEVEL_5 + 32 Double words + 0x5 + + + STATFF_LEVEL_6 + 48 Double words + 0x6 + + + STATFF_LEVEL_7 + 64 Double words + 0x7 + + + + + DMA_REQ_EN_SFF + DMA Request Enable for STATFIFO + 11 + 1 + read-write + + + DMA_REQ_EN_SFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_SFF_1 + Enable the dma request + 0x1 + + + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO + 12 + 1 + read-write + + + DMA_REQ_EN_RFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_RFF_1 + Enable the dma request + 0x1 + + + + + DMA_REFLASH_SFF + Reflash DMA Controller for STATFIFO + 13 + 1 + read-write + + + DMA_REFLASH_SFF_0 + No reflashing + 0 + + + DMA_REFLASH_SFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + DMA_REFLASH_RFF + Reflash DMA Controller for RxFIFO + 14 + 1 + read-write + + + DMA_REFLASH_RFF_0 + No reflashing + 0 + + + DMA_REFLASH_RFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done) + 15 + 1 + read-write + + + FRMCNT_RST_0 + Do not reset + 0 + + + FRMCNT_RST_1 + Reset frame counter immediately + 0x1 + + + + + FRMCNT + Frame Counter + 16 + 16 + read-write + + + + + CSISTATFIFO + CSI Statistic FIFO Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT + Static data from sensor + 0 + 32 + read-only + + + + + CSIRFIFO + CSI RX FIFO Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMAGE + Received image data + 0 + 32 + read-only + + + + + CSIRXCNT + CSI RX Count Register + 0x14 + 32 + read-write + 0x9600 + 0xFFFFFFFF + + + RXCNT + RxFIFO Count + 0 + 22 + read-write + + + + + CSISR + CSI Status Register + 0x18 + 32 + read-write + 0x4000 + 0xFFFFFFFF + + + DRDY + RXFIFO Data Ready + 0 + 1 + read-write + + + DRDY_0 + No data (word) is ready + 0 + + + DRDY_1 + At least 1 datum (word) is ready in RXFIFO. + 0x1 + + + + + ECC_INT + CCIR Error Interrupt + 1 + 1 + read-write + + + ECC_INT_0 + No error detected + 0 + + + ECC_INT_1 + Error is detected in CCIR coding + 0x1 + + + + + HRESP_ERR_INT + Hresponse Error Interrupt Status + 7 + 1 + read-write + + + HRESP_ERR_INT_0 + No hresponse error. + 0 + + + HRESP_ERR_INT_1 + Hresponse error is detected. + 0x1 + + + + + COF_INT + Change Of Field Interrupt Status + 13 + 1 + read-write + + + COF_INT_0 + Video field has no change. + 0 + + + COF_INT_1 + Change of video field is detected. + 0x1 + + + + + F1_INT + CCIR Field 1 Interrupt Status + 14 + 1 + read-write + + + F1_INT_0 + Field 1 of video is not detected. + 0 + + + F1_INT_1 + Field 1 of video is about to start. + 0x1 + + + + + F2_INT + CCIR Field 2 Interrupt Status + 15 + 1 + read-write + + + F2_INT_0 + Field 2 of video is not detected + 0 + + + F2_INT_1 + Field 2 of video is about to start + 0x1 + + + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) + 16 + 1 + read-write + + + SOF_INT_0 + SOF is not detected. + 0 + + + SOF_INT_1 + SOF is detected. + 0x1 + + + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) + 17 + 1 + read-write + + + EOF_INT_0 + EOF is not detected. + 0 + + + EOF_INT_1 + EOF is detected. + 0x1 + + + + + RxFF_INT + RXFIFO Full Interrupt Status + 18 + 1 + read-write + + + RxFF_INT_0 + RxFIFO is not full. + 0 + + + RxFF_INT_1 + RxFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1 + 19 + 1 + read-write + + + DMA_TSF_DONE_FB1_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB1_1 + DMA transfer is completed. + 0x1 + + + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2 + 20 + 1 + read-write + + + DMA_TSF_DONE_FB2_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB2_1 + DMA transfer is completed. + 0x1 + + + + + STATFF_INT + STATFIFO Full Interrupt Status + 21 + 1 + read-write + + + STATFF_INT_0 + STATFIFO is not full. + 0 + + + STATFF_INT_1 + STATFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_SFF + DMA Transfer Done from StatFIFO + 22 + 1 + read-write + + + DMA_TSF_DONE_SFF_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_SFF_1 + DMA transfer is completed. + 0x1 + + + + + RF_OR_INT + RxFIFO Overrun Interrupt Status + 24 + 1 + read-write + + + RF_OR_INT_0 + RXFIFO has not overflowed. + 0 + + + RF_OR_INT_1 + RXFIFO has overflowed. + 0x1 + + + + + SF_OR_INT + STATFIFO Overrun Interrupt Status + 25 + 1 + read-write + + + SF_OR_INT_0 + STATFIFO has not overflowed. + 0 + + + SF_OR_INT_1 + STATFIFO has overflowed. + 0x1 + + + + + DMA_FIELD1_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 26 + 1 + read-write + + + DMA_FIELD0_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 27 + 1 + read-write + + + BASEADDR_CHHANGE_ERROR + When using base address switching enable, this bit will be 1 when switching occur before DMA complete + 28 + 1 + read-write + + + + + CSIDMASA_STATFIFO + CSI DMA Start Address Register - for STATFIFO + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_SFF + DMA Start Address for STATFIFO + 2 + 30 + read-write + + + + + CSIDMATS_STATFIFO + CSI DMA Transfer Size Register - for STATFIFO + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_TSF_SIZE_SFF + DMA Transfer Size for STATFIFO + 0 + 32 + read-write + + + + + CSIDMASA_FB1 + CSI DMA Start Address Register - for Frame Buffer1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB1 + DMA Start Address in Frame Buffer1 + 2 + 30 + read-write + + + + + CSIDMASA_FB2 + CSI DMA Transfer Size Register - for Frame Buffer2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB2 + DMA Start Address in Frame Buffer2 + 2 + 30 + read-write + + + + + CSIFBUF_PARA + CSI Frame Buffer Parameter Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBUF_STRIDE + Frame Buffer Parameter + 0 + 16 + read-write + + + DEINTERLACE_STRIDE + DEINTERLACE_STRIDE is only used in the deinterlace mode + 16 + 16 + read-write + + + + + CSIIMAG_PARA + CSI Image Parameter Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMAGE_HEIGHT + Image Height. Indicates how many pixels in a column of the image from the sensor. + 0 + 16 + read-write + + + IMAGE_WIDTH + Image Width + 16 + 16 + read-write + + + + + CSICR18 + CSI Control Register 18 + 0x48 + 32 + read-write + 0x2D000 + 0xFFFFFFFF + + + DEINTERLACE_EN + This bit is used to select the output method When input is standard CCIR656 video. + 2 + 1 + read-write + + + DEINTERLACE_EN_0 + Deinterlace disabled + 0 + + + DEINTERLACE_EN_1 + Deinterlace enabled + 0x1 + + + + + PARALLEL24_EN + When input is parallel rgb888/yuv444 24bit, this bit can be enabled. + 3 + 1 + read-write + + + BASEADDR_SWITCH_EN + When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed + 4 + 1 + read-write + + + BASEADDR_SWITCH_SEL + CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1. + 5 + 1 + read-write + + + BASEADDR_SWITCH_SEL_0 + Switching base address at the edge of the vsync + 0 + + + BASEADDR_SWITCH_SEL_1 + Switching base address at the edge of the first data of each frame + 0x1 + + + + + FIELD0_DONE_IE + In interlace mode, fileld 0 means interrupt enabled. + 6 + 1 + read-write + + + FIELD0_DONE_IE_0 + Interrupt disabled + 0 + + + FIELD0_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + DMA_FIELD1_DONE_IE + When in interlace mode, field 1 done interrupt enable. + 7 + 1 + read-write + + + DMA_FIELD1_DONE_IE_0 + Interrupt disabled + 0 + + + DMA_FIELD1_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + LAST_DMA_REQ_SEL + Choosing the last DMA request condition. + 8 + 1 + read-write + + + LAST_DMA_REQ_SEL_0 + fifo_full_level + 0 + + + LAST_DMA_REQ_SEL_1 + hburst_length + 0x1 + + + + + BASEADDR_CHANGE_ERROR_IE + Base address change error interrupt enable signal. + 9 + 1 + read-write + + + RGB888A_FORMAT_SEL + Output is 32-bit format. + 10 + 1 + read-write + + + RGB888A_FORMAT_SEL_0 + {8'h0, data[23:0]} + 0 + + + RGB888A_FORMAT_SEL_1 + {data[23:0], 8'h0} + 0x1 + + + + + AHB_HPROT + Hprot value in AHB bus protocol. + 12 + 4 + read-write + + + MASK_OPTION + These bits used to choose the method to mask the CSI input. + 18 + 2 + read-write + + + MASK_OPTION_0 + Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. + 0 + + + MASK_OPTION_1 + Writing to memory when CSI_ENABLE is 1. + 0x1 + + + MASK_OPTION_2 + Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + 0x2 + + + MASK_OPTION_3 + Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + 0x3 + + + + + CSI_ENABLE + CSI global enable signal + 31 + 1 + read-write + + + + + CSICR19 + CSI Control Register 19 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_RFIFO_HIGHEST_FIFO_LEVEL + This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it + 0 + 8 + read-write + + + + + + + USDHC1 + uSDHC + uSDHC + uSDHC + 0x402C0000 + + 0 + 0xD0 + registers + + + USDHC1 + 110 + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS_ADDR + DS_ADDR + 0 + 32 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + Block Size + 0 + 13 + read-write + + + BLKSIZE_0 + No data transfer + 0 + + + BLKSIZE_1 + 1 Byte + 0x1 + + + BLKSIZE_2 + 2 Bytes + 0x2 + + + BLKSIZE_3 + 3 Bytes + 0x3 + + + BLKSIZE_4 + 4 Bytes + 0x4 + + + BLKSIZE_511 + 511 Bytes + 0x1FF + + + BLKSIZE_512 + 512 Bytes + 0x200 + + + BLKSIZE_2048 + 2048 Bytes + 0x800 + + + BLKSIZE_4096 + 4096 Bytes + 0x1000 + + + + + BLKCNT + Block Count + 16 + 16 + read-write + + + BLKCNT_0 + Stop Count + 0 + + + BLKCNT_1 + 1 block + 0x1 + + + BLKCNT_2 + 2 blocks + 0x2 + + + BLKCNT_65535 + 65535 blocks + 0xFFFF + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + Command Argument + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RSPTYP + Response Type Select + 16 + 2 + read-write + + + RSPTYP_0 + No Response + 0 + + + RSPTYP_1 + Response Length 136 + 0x1 + + + RSPTYP_2 + Response Length 48 + 0x2 + + + RSPTYP_3 + Response Length 48, check Busy after response + 0x3 + + + + + CCCEN + Command CRC Check Enable + 19 + 1 + read-write + + + CCCEN_0 + Disable + 0 + + + CCCEN_1 + Enable + 0x1 + + + + + CICEN + Command Index Check Enable + 20 + 1 + read-write + + + CICEN_0 + Disable + 0 + + + CICEN_1 + Enable + 0x1 + + + + + DPSEL + Data Present Select + 21 + 1 + read-write + + + DPSEL_0 + No Data Present + 0 + + + DPSEL_1 + Data Present + 0x1 + + + + + CMDTYP + Command Type + 22 + 2 + read-write + + + CMDTYP_0 + Normal Other commands + 0 + + + CMDTYP_1 + Suspend CMD52 for writing Bus Suspend in CCCR + 0x1 + + + CMDTYP_2 + Resume CMD52 for writing Function Select in CCCR + 0x2 + + + CMDTYP_3 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDINX + Command Index + 24 + 6 + read-write + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + Command Response 0 + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + Command Response 1 + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + Command Response 2 + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + Command Response 3 + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + Data Content + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0x8080 + 0x72FFFF + + + CIHB + Command Inhibit (CMD) + 0 + 1 + read-only + + + CIHB_0 + Can issue command using only CMD line + 0 + + + CIHB_1 + Cannot issue command + 0x1 + + + + + CDIHB + Command Inhibit (DATA) + 1 + 1 + read-only + + + CDIHB_0 + Can issue command which uses the DATA line + 0 + + + CDIHB_1 + Cannot issue command which uses the DATA line + 0x1 + + + + + DLA + Data Line Active + 2 + 1 + read-only + + + DLA_0 + DATA Line Inactive + 0 + + + DLA_1 + DATA Line Active + 0x1 + + + + + SDSTB + SD Clock Stable + 3 + 1 + read-only + + + SDSTB_0 + Clock is changing frequency and not stable. + 0 + + + SDSTB_1 + Clock is stable. + 0x1 + + + + + IPGOFF + IPG_CLK Gated Off Internally + 4 + 1 + read-only + + + IPGOFF_0 + IPG_CLK is active. + 0 + + + IPGOFF_1 + IPG_CLK is gated off. + 0x1 + + + + + HCKOFF + HCLK Gated Off Internally + 5 + 1 + read-only + + + HCKOFF_0 + HCLK is active. + 0 + + + HCKOFF_1 + HCLK is gated off. + 0x1 + + + + + PEROFF + IPG_PERCLK Gated Off Internally + 6 + 1 + read-only + + + PEROFF_0 + IPG_PERCLK is active. + 0 + + + PEROFF_1 + IPG_PERCLK is gated off. + 0x1 + + + + + SDOFF + SD Clock Gated Off Internally + 7 + 1 + read-only + + + SDOFF_0 + SD Clock is active. + 0 + + + SDOFF_1 + SD Clock is gated off. + 0x1 + + + + + WTA + Write Transfer Active + 8 + 1 + read-only + + + WTA_0 + No valid data + 0 + + + WTA_1 + Transferring data + 0x1 + + + + + RTA + Read Transfer Active + 9 + 1 + read-only + + + RTA_0 + No valid data + 0 + + + RTA_1 + Transferring data + 0x1 + + + + + BWEN + Buffer Write Enable + 10 + 1 + read-only + + + BWEN_0 + Write disable + 0 + + + BWEN_1 + Write enable + 0x1 + + + + + BREN + Buffer Read Enable + 11 + 1 + read-only + + + BREN_0 + Read disable + 0 + + + BREN_1 + Read enable + 0x1 + + + + + RTR + Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 12 + 1 + read-only + + + RTR_0 + Fixed or well tuned sampling clock + 0 + + + RTR_1 + Sampling clock needs re-tuning + 0x1 + + + + + TSCD + Tape Select Change Done + 15 + 1 + read-only + + + TSCD_0 + Delay cell select change is not finished. + 0 + + + TSCD_1 + Delay cell select change is finished. + 0x1 + + + + + CINST + Card Inserted + 16 + 1 + read-only + + + CINST_0 + Power on Reset or No Card + 0 + + + CINST_1 + Card Inserted + 0x1 + + + + + CDPL + Card Detect Pin Level + 18 + 1 + read-only + + + CDPL_0 + No card present (CD_B = 1) + 0 + + + CDPL_1 + Card present (CD_B = 0) + 0x1 + + + + + WPSPL + Write Protect Switch Pin Level + 19 + 1 + read-only + + + WPSPL_0 + Write protected (WP = 1) + 0 + + + WPSPL_1 + Write enabled (WP = 0) + 0x1 + + + + + CLSL + CMD Line Signal Level + 23 + 1 + read-only + + + DLSL + DATA[7:0] Line Signal Level + 24 + 8 + read-only + + + DATA0 + Data 0 line signal level + 0 + + + DATA1 + Data 1 line signal level + 0x1 + + + DATA2 + Data 2 line signal level + 0x2 + + + DATA3 + Data 3 line signal level + 0x3 + + + DATA4 + Data 4 line signal level + 0x4 + + + DATA5 + Data 5 line signal level + 0x5 + + + DATA6 + Data 6 line signal level + 0x6 + + + DATA7 + Data 7 line signal level + 0x7 + + + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + LED Control + 0 + 1 + read-write + + + LCTL_0 + LED off + 0 + + + LCTL_1 + LED on + 0x1 + + + + + DTW + Data Transfer Width + 1 + 2 + read-write + + + DTW_0 + 1-bit mode + 0 + + + DTW_1 + 4-bit mode + 0x1 + + + DTW_2 + 8-bit mode + 0x2 + + + + + D3CD + DATA3 as Card Detection Pin + 3 + 1 + read-write + + + D3CD_0 + DATA3 does not monitor Card Insertion + 0 + + + D3CD_1 + DATA3 as Card Detection Pin + 0x1 + + + + + EMODE + Endian Mode + 4 + 2 + read-write + + + EMODE_0 + Big Endian Mode + 0 + + + EMODE_1 + Half Word Big Endian Mode + 0x1 + + + EMODE_2 + Little Endian Mode + 0x2 + + + + + CDTL + Card Detect Test Level + 6 + 1 + read-write + + + CDTL_0 + Card Detect Test Level is 0, no card inserted + 0 + + + CDTL_1 + Card Detect Test Level is 1, card inserted + 0x1 + + + + + CDSS + Card Detect Signal Selection + 7 + 1 + read-write + + + CDSS_0 + Card Detection Level is selected (for normal purpose). + 0 + + + CDSS_1 + Card Detection Test Level is selected (for test purpose). + 0x1 + + + + + DMASEL + DMA Select + 8 + 2 + read-write + + + DMASEL_0 + No DMA or Simple DMA is selected + 0 + + + DMASEL_1 + ADMA1 is selected + 0x1 + + + DMASEL_2 + ADMA2 is selected + 0x2 + + + + + SABGREQ + Stop At Block Gap Request + 16 + 1 + read-write + + + SABGREQ_0 + Transfer + 0 + + + SABGREQ_1 + Stop + 0x1 + + + + + CREQ + Continue Request + 17 + 1 + read-write + + + CREQ_0 + No effect + 0 + + + CREQ_1 + Restart + 0x1 + + + + + RWCTL + Read Wait Control + 18 + 1 + read-write + + + RWCTL_0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + 0 + + + RWCTL_1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + 0x1 + + + + + IABG + Interrupt At Block Gap + 19 + 1 + read-write + + + IABG_0 + Disabled + 0 + + + IABG_1 + Enabled + 0x1 + + + + + RD_DONE_NO_8CLK + RD_DONE_NO_8CLK + 20 + 1 + read-write + + + WECINT + Wakeup Event Enable On Card Interrupt + 24 + 1 + read-write + + + WECINT_0 + Disable + 0 + + + WECINT_1 + Enable + 0x1 + + + + + WECINS + Wakeup Event Enable On SD Card Insertion + 25 + 1 + read-write + + + WECINS_0 + Disable + 0 + + + WECINS_1 + Enable + 0x1 + + + + + WECRM + Wakeup Event Enable On SD Card Removal + 26 + 1 + read-write + + + WECRM_0 + Disable + 0 + + + WECRM_1 + Enable + 0x1 + + + + + BURST_LEN_EN + BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + 27 + 3 + read-write + + + BURST_LEN_EN_1 + Burst length is enabled for INCR + #xx1 + + + + + NON_EXACT_BLK_RD + NON_EXACT_BLK_RD + 30 + 1 + read-write + + + NON_EXACT_BLK_RD_0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + 0 + + + NON_EXACT_BLK_RD_1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + 0x1 + + + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + DVS + Divisor + 4 + 4 + read-write + + + DVS_0 + Divide-by-1 + 0 + + + DVS_1 + Divide-by-2 + 0x1 + + + DVS_14 + Divide-by-15 + 0xE + + + DVS_15 + Divide-by-16 + 0xF + + + + + SDCLKFS + SDCLK Frequency Select + 8 + 8 + read-write + + + DTOCV + Data Timeout Counter Value + 16 + 4 + read-write + + + DTOCV_0 + no description available + 0 + + + DTOCV_1 + no description available + 0x1 + + + DTOCV_13 + no description available + 0xD + + + DTOCV_14 + no description available + 0xE + + + DTOCV_15 + no description available + 0xF + + + + + IPP_RST_N + IPP_RST_N + 23 + 1 + read-write + + + RSTA + Software Reset For ALL + 24 + 1 + read-write + + + RSTA_0 + No Reset + 0 + + + RSTA_1 + Reset + 0x1 + + + + + RSTC + Software Reset For CMD Line + 25 + 1 + read-write + + + RSTC_0 + No Reset + 0 + + + RSTC_1 + Reset + 0x1 + + + + + RSTD + Software Reset For DATA Line + 26 + 1 + read-write + + + RSTD_0 + No Reset + 0 + + + RSTD_1 + Reset + 0x1 + + + + + INITA + Initialization Active + 27 + 1 + read-write + + + RSTT + Reset Tuning + 28 + 1 + read-write + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Command Complete + 0 + 1 + read-write + oneToClear + + + CC_0 + Command not complete + 0 + + + CC_1 + Command complete + 0x1 + + + + + TC + Transfer Complete + 1 + 1 + read-write + oneToClear + + + TC_0 + Transfer not complete + 0 + + + TC_1 + Transfer complete + 0x1 + + + + + BGE + Block Gap Event + 2 + 1 + read-write + oneToClear + + + BGE_0 + No block gap event + 0 + + + BGE_1 + Transaction stopped at block gap + 0x1 + + + + + DINT + DMA Interrupt + 3 + 1 + read-write + oneToClear + + + DINT_0 + No DMA Interrupt + 0 + + + DINT_1 + DMA Interrupt is generated + 0x1 + + + + + BWR + Buffer Write Ready + 4 + 1 + read-write + oneToClear + + + BWR_0 + Not ready to write buffer + 0 + + + BWR_1 + Ready to write buffer: + 0x1 + + + + + BRR + Buffer Read Ready + 5 + 1 + read-write + oneToClear + + + BRR_0 + Not ready to read buffer + 0 + + + BRR_1 + Ready to read buffer + 0x1 + + + + + CINS + Card Insertion + 6 + 1 + read-write + oneToClear + + + CINS_0 + Card state unstable or removed + 0 + + + CINS_1 + Card inserted + 0x1 + + + + + CRM + Card Removal + 7 + 1 + read-write + oneToClear + + + CRM_0 + Card state unstable or inserted + 0 + + + CRM_1 + Card removed + 0x1 + + + + + CINT + Card Interrupt + 8 + 1 + read-write + oneToClear + + + CINT_0 + No Card Interrupt + 0 + + + CINT_1 + Generate Card Interrupt + 0x1 + + + + + RTE + Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 12 + 1 + read-write + oneToClear + + + RTE_0 + Re-Tuning is not required + 0 + + + RTE_1 + Re-Tuning should be performed + 0x1 + + + + + TP + Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) + 14 + 1 + read-write + oneToClear + + + CTOE + Command Timeout Error + 16 + 1 + read-write + oneToClear + + + CTOE_0 + No Error + 0 + + + CTOE_1 + Time out + 0x1 + + + + + CCE + Command CRC Error + 17 + 1 + read-write + oneToClear + + + CCE_0 + No Error + 0 + + + CCE_1 + CRC Error Generated. + 0x1 + + + + + CEBE + Command End Bit Error + 18 + 1 + read-write + oneToClear + + + CEBE_0 + No Error + 0 + + + CEBE_1 + End Bit Error Generated + 0x1 + + + + + CIE + Command Index Error + 19 + 1 + read-write + oneToClear + + + CIE_0 + No Error + 0 + + + CIE_1 + Error + 0x1 + + + + + DTOE + Data Timeout Error + 20 + 1 + read-write + oneToClear + + + DTOE_0 + No Error + 0 + + + DTOE_1 + Time out + 0x1 + + + + + DCE + Data CRC Error + 21 + 1 + read-write + oneToClear + + + DCE_0 + No Error + 0 + + + DCE_1 + Error + 0x1 + + + + + DEBE + Data End Bit Error + 22 + 1 + read-write + oneToClear + + + DEBE_0 + No Error + 0 + + + DEBE_1 + Error + 0x1 + + + + + AC12E + Auto CMD12 Error + 24 + 1 + read-write + oneToClear + + + AC12E_0 + No Error + 0 + + + AC12E_1 + Error + 0x1 + + + + + TNE + Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 26 + 1 + read-write + oneToClear + + + DMAE + DMA Error + 28 + 1 + read-write + oneToClear + + + DMAE_0 + No Error + 0 + + + DMAE_1 + Error + 0x1 + + + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCSEN + Command Complete Status Enable + 0 + 1 + read-write + + + CCSEN_0 + Masked + 0 + + + CCSEN_1 + Enabled + 0x1 + + + + + TCSEN + Transfer Complete Status Enable + 1 + 1 + read-write + + + TCSEN_0 + Masked + 0 + + + TCSEN_1 + Enabled + 0x1 + + + + + BGESEN + Block Gap Event Status Enable + 2 + 1 + read-write + + + BGESEN_0 + Masked + 0 + + + BGESEN_1 + Enabled + 0x1 + + + + + DINTSEN + DMA Interrupt Status Enable + 3 + 1 + read-write + + + DINTSEN_0 + Masked + 0 + + + DINTSEN_1 + Enabled + 0x1 + + + + + BWRSEN + Buffer Write Ready Status Enable + 4 + 1 + read-write + + + BWRSEN_0 + Masked + 0 + + + BWRSEN_1 + Enabled + 0x1 + + + + + BRRSEN + Buffer Read Ready Status Enable + 5 + 1 + read-write + + + BRRSEN_0 + Masked + 0 + + + BRRSEN_1 + Enabled + 0x1 + + + + + CINSSEN + Card Insertion Status Enable + 6 + 1 + read-write + + + CINSSEN_0 + Masked + 0 + + + CINSSEN_1 + Enabled + 0x1 + + + + + CRMSEN + Card Removal Status Enable + 7 + 1 + read-write + + + CRMSEN_0 + Masked + 0 + + + CRMSEN_1 + Enabled + 0x1 + + + + + CINTSEN + Card Interrupt Status Enable + 8 + 1 + read-write + + + CINTSEN_0 + Masked + 0 + + + CINTSEN_1 + Enabled + 0x1 + + + + + RTESEN + Re-Tuning Event Status Enable + 12 + 1 + read-write + + + RTESEN_0 + Masked + 0 + + + RTESEN_1 + Enabled + 0x1 + + + + + TPSEN + Tuning Pass Status Enable + 14 + 1 + read-write + + + TPSEN_0 + Masked + 0 + + + TPSEN_1 + Enabled + 0x1 + + + + + CTOESEN + Command Timeout Error Status Enable + 16 + 1 + read-write + + + CTOESEN_0 + Masked + 0 + + + CTOESEN_1 + Enabled + 0x1 + + + + + CCESEN + Command CRC Error Status Enable + 17 + 1 + read-write + + + CCESEN_0 + Masked + 0 + + + CCESEN_1 + Enabled + 0x1 + + + + + CEBESEN + Command End Bit Error Status Enable + 18 + 1 + read-write + + + CEBESEN_0 + Masked + 0 + + + CEBESEN_1 + Enabled + 0x1 + + + + + CIESEN + Command Index Error Status Enable + 19 + 1 + read-write + + + CIESEN_0 + Masked + 0 + + + CIESEN_1 + Enabled + 0x1 + + + + + DTOESEN + Data Timeout Error Status Enable + 20 + 1 + read-write + + + DTOESEN_0 + Masked + 0 + + + DTOESEN_1 + Enabled + 0x1 + + + + + DCESEN + Data CRC Error Status Enable + 21 + 1 + read-write + + + DCESEN_0 + Masked + 0 + + + DCESEN_1 + Enabled + 0x1 + + + + + DEBESEN + Data End Bit Error Status Enable + 22 + 1 + read-write + + + DEBESEN_0 + Masked + 0 + + + DEBESEN_1 + Enabled + 0x1 + + + + + AC12ESEN + Auto CMD12 Error Status Enable + 24 + 1 + read-write + + + AC12ESEN_0 + Masked + 0 + + + AC12ESEN_1 + Enabled + 0x1 + + + + + TNESEN + Tuning Error Status Enable + 26 + 1 + read-write + + + TNESEN_0 + Masked + 0 + + + TNESEN_1 + Enabled + 0x1 + + + + + DMAESEN + DMA Error Status Enable + 28 + 1 + read-write + + + DMAESEN_0 + Masked + 0 + + + DMAESEN_1 + Enabled + 0x1 + + + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + Command Complete Interrupt Enable + 0 + 1 + read-write + + + CCIEN_0 + Masked + 0 + + + CCIEN_1 + Enabled + 0x1 + + + + + TCIEN + Transfer Complete Interrupt Enable + 1 + 1 + read-write + + + TCIEN_0 + Masked + 0 + + + TCIEN_1 + Enabled + 0x1 + + + + + BGEIEN + Block Gap Event Interrupt Enable + 2 + 1 + read-write + + + BGEIEN_0 + Masked + 0 + + + BGEIEN_1 + Enabled + 0x1 + + + + + DINTIEN + DMA Interrupt Enable + 3 + 1 + read-write + + + DINTIEN_0 + Masked + 0 + + + DINTIEN_1 + Enabled + 0x1 + + + + + BWRIEN + Buffer Write Ready Interrupt Enable + 4 + 1 + read-write + + + BWRIEN_0 + Masked + 0 + + + BWRIEN_1 + Enabled + 0x1 + + + + + BRRIEN + Buffer Read Ready Interrupt Enable + 5 + 1 + read-write + + + BRRIEN_0 + Masked + 0 + + + BRRIEN_1 + Enabled + 0x1 + + + + + CINSIEN + Card Insertion Interrupt Enable + 6 + 1 + read-write + + + CINSIEN_0 + Masked + 0 + + + CINSIEN_1 + Enabled + 0x1 + + + + + CRMIEN + Card Removal Interrupt Enable + 7 + 1 + read-write + + + CRMIEN_0 + Masked + 0 + + + CRMIEN_1 + Enabled + 0x1 + + + + + CINTIEN + Card Interrupt Interrupt Enable + 8 + 1 + read-write + + + CINTIEN_0 + Masked + 0 + + + CINTIEN_1 + Enabled + 0x1 + + + + + RTEIEN + Re-Tuning Event Interrupt Enable + 12 + 1 + read-write + + + RTEIEN_0 + Masked + 0 + + + RTEIEN_1 + Enabled + 0x1 + + + + + TPIEN + Tuning Pass Interrupt Enable + 14 + 1 + read-write + + + TPIEN_0 + Masked + 0 + + + TPIEN_1 + Enabled + 0x1 + + + + + CTOEIEN + Command Timeout Error Interrupt Enable + 16 + 1 + read-write + + + CTOEIEN_0 + Masked + 0 + + + CTOEIEN_1 + Enabled + 0x1 + + + + + CCEIEN + Command CRC Error Interrupt Enable + 17 + 1 + read-write + + + CCEIEN_0 + Masked + 0 + + + CCEIEN_1 + Enabled + 0x1 + + + + + CEBEIEN + Command End Bit Error Interrupt Enable + 18 + 1 + read-write + + + CEBEIEN_0 + Masked + 0 + + + CEBEIEN_1 + Enabled + 0x1 + + + + + CIEIEN + Command Index Error Interrupt Enable + 19 + 1 + read-write + + + CIEIEN_0 + Masked + 0 + + + CIEIEN_1 + Enabled + 0x1 + + + + + DTOEIEN + Data Timeout Error Interrupt Enable + 20 + 1 + read-write + + + DTOEIEN_0 + Masked + 0 + + + DTOEIEN_1 + Enabled + 0x1 + + + + + DCEIEN + Data CRC Error Interrupt Enable + 21 + 1 + read-write + + + DCEIEN_0 + Masked + 0 + + + DCEIEN_1 + Enabled + 0x1 + + + + + DEBEIEN + Data End Bit Error Interrupt Enable + 22 + 1 + read-write + + + DEBEIEN_0 + Masked + 0 + + + DEBEIEN_1 + Enabled + 0x1 + + + + + AC12EIEN + Auto CMD12 Error Interrupt Enable + 24 + 1 + read-write + + + AC12EIEN_0 + Masked + 0 + + + AC12EIEN_1 + Enabled + 0x1 + + + + + TNEIEN + Tuning Error Interrupt Enable + 26 + 1 + read-write + + + TNEIEN_0 + Masked + 0 + + + TNEIEN_1 + Enabled + 0x1 + + + + + DMAEIEN + DMA Error Interrupt Enable + 28 + 1 + read-write + + + DMAEIEN_0 + Masked + 0 + + + DMAEIEN_1 + Enable + 0x1 + + + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AC12NE + Auto CMD12 Not Executed + 0 + 1 + read-only + + + AC12NE_0 + Executed + 0 + + + AC12NE_1 + Not executed + 0x1 + + + + + AC12TOE + Auto CMD12 / 23 Timeout Error + 1 + 1 + read-only + + + AC12TOE_0 + No error + 0 + + + AC12TOE_1 + Time out + 0x1 + + + + + AC12EBE + Auto CMD12 / 23 End Bit Error + 2 + 1 + read-only + + + AC12EBE_0 + No error + 0 + + + AC12EBE_1 + End Bit Error Generated + 0x1 + + + + + AC12CE + Auto CMD12 / 23 CRC Error + 3 + 1 + read-only + + + AC12CE_0 + No CRC error + 0 + + + AC12CE_1 + CRC Error Met in Auto CMD12/23 Response + 0x1 + + + + + AC12IE + Auto CMD12 / 23 Index Error + 4 + 1 + read-only + + + AC12IE_0 + No error + 0 + + + AC12IE_1 + Error, the CMD index in response is not CMD12/23 + 0x1 + + + + + CNIBAC12E + Command Not Issued By Auto CMD12 Error + 7 + 1 + read-only + + + CNIBAC12E_0 + No error + 0 + + + CNIBAC12E_1 + Not Issued + 0x1 + + + + + EXECUTE_TUNING + Execute Tuning + 22 + 1 + read-write + + + SMP_CLK_SEL + Sample Clock Select + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data + 0x1 + + + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-write + 0x7F3B407 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 support + 0 + 1 + read-only + + + SDR104_SUPPORT + SDR104 support + 1 + 1 + read-only + + + DDR50_SUPPORT + DDR50 support + 2 + 1 + read-only + + + TIME_COUNT_RETUNING + Time Counter for Retuning + 8 + 4 + read-write + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 13 + 1 + read-write + + + USE_TUNING_SDR50_0 + SDR does not require tuning + 0 + + + USE_TUNING_SDR50_1 + SDR50 requires tuning + 0x1 + + + + + RETUNING_MODE + Retuning Mode + 14 + 2 + read-only + + + RETUNING_MODE_0 + Mode 1 + 0 + + + RETUNING_MODE_1 + Mode 2 + 0x1 + + + RETUNING_MODE_2 + Mode 3 + 0x2 + + + + + MBL + Max Block Length + 16 + 3 + read-only + + + MBL_0 + 512 bytes + 0 + + + MBL_1 + 1024 bytes + 0x1 + + + MBL_2 + 2048 bytes + 0x2 + + + MBL_3 + 4096 bytes + 0x3 + + + + + ADMAS + ADMA Support + 20 + 1 + read-only + + + ADMAS_0 + Advanced DMA Not supported + 0 + + + ADMAS_1 + Advanced DMA Supported + 0x1 + + + + + HSS + High Speed Support + 21 + 1 + read-only + + + HSS_0 + High Speed Not Supported + 0 + + + HSS_1 + High Speed Supported + 0x1 + + + + + DMAS + DMA Support + 22 + 1 + read-only + + + DMAS_0 + DMA not supported + 0 + + + DMAS_1 + DMA Supported + 0x1 + + + + + SRS + Suspend / Resume Support + 23 + 1 + read-only + + + SRS_0 + Not supported + 0 + + + SRS_1 + Supported + 0x1 + + + + + VS33 + Voltage Support 3.3V + 24 + 1 + read-only + + + VS33_0 + 3.3V not supported + 0 + + + VS33_1 + 3.3V supported + 0x1 + + + + + VS30 + Voltage Support 3.0 V + 25 + 1 + read-only + + + VS30_0 + 3.0V not supported + 0 + + + VS30_1 + 3.0V supported + 0x1 + + + + + VS18 + Voltage Support 1.8 V + 26 + 1 + read-only + + + VS18_0 + 1.8V not supported + 0 + + + VS18_1 + 1.8V supported + 0x1 + + + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + Read Watermark Level + 0 + 8 + read-write + + + RD_BRST_LEN + Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + 8 + 5 + read-write + + + WR_WML + Write Watermark Level + 16 + 8 + read-write + + + WR_BRST_LEN + Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + 24 + 5 + read-write + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + DMAEN_0 + Disable + 0 + + + DMAEN_1 + Enable + 0x1 + + + + + BCEN + Block Count Enable + 1 + 1 + read-write + + + BCEN_0 + Disable + 0 + + + BCEN_1 + Enable + 0x1 + + + + + AC12EN + Auto CMD12 Enable + 2 + 1 + read-write + + + AC12EN_0 + Disable + 0 + + + AC12EN_1 + Enable + 0x1 + + + + + DDR_EN + Dual Data Rate mode selection + 3 + 1 + read-write + + + DTDSEL + Data Transfer Direction Select + 4 + 1 + read-write + + + DTDSEL_0 + Write (Host to Card) + 0 + + + DTDSEL_1 + Read (Card to Host) + 0x1 + + + + + MSBSEL + Multi / Single Block Select + 5 + 1 + read-write + + + MSBSEL_0 + Single Block + 0 + + + MSBSEL_1 + Multiple Blocks + 0x1 + + + + + NIBBLE_POS + NIBBLE_POS + 6 + 1 + read-write + + + AC23EN + Auto CMD23 Enable + 7 + 1 + read-write + + + EXE_TUNE + Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + 22 + 1 + read-write + + + EXE_TUNE_0 + Not Tuned or Tuning Completed + 0 + + + EXE_TUNE_1 + Execute Tuning + 0x1 + + + + + SMP_CLK_SEL + SMP_CLK_SEL + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data / cmd + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data / cmd + 0x1 + + + + + AUTO_TUNE_EN + Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + 24 + 1 + read-write + + + AUTO_TUNE_EN_0 + Disable auto tuning + 0 + + + AUTO_TUNE_EN_1 + Enable auto tuning + 0x1 + + + + + FBCLK_SEL + Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + 25 + 1 + read-write + + + FBCLK_SEL_0 + Feedback clock comes from the loopback CLK + 0 + + + FBCLK_SEL_1 + Feedback clock comes from the ipp_card_clk_out + 0x1 + + + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + Force Event Auto Command 12 Not Executed + 0 + 1 + write-only + + + FEVTAC12TOE + Force Event Auto Command 12 Time Out Error + 1 + 1 + write-only + + + FEVTAC12CE + Force Event Auto Command 12 CRC Error + 2 + 1 + write-only + + + FEVTAC12EBE + Force Event Auto Command 12 End Bit Error + 3 + 1 + write-only + + + FEVTAC12IE + Force Event Auto Command 12 Index Error + 4 + 1 + write-only + + + FEVTCNIBAC12E + Force Event Command Not Executed By Auto Command 12 Error + 7 + 1 + write-only + + + FEVTCTOE + Force Event Command Time Out Error + 16 + 1 + write-only + + + FEVTCCE + Force Event Command CRC Error + 17 + 1 + write-only + + + FEVTCEBE + Force Event Command End Bit Error + 18 + 1 + write-only + + + FEVTCIE + Force Event Command Index Error + 19 + 1 + write-only + + + FEVTDTOE + Force Event Data Time Out Error + 20 + 1 + write-only + + + FEVTDCE + Force Event Data CRC Error + 21 + 1 + write-only + + + FEVTDEBE + Force Event Data End Bit Error + 22 + 1 + write-only + + + FEVTAC12E + Force Event Auto Command 12 Error + 24 + 1 + write-only + + + FEVTTNE + Force Tuning Error + 26 + 1 + write-only + + + FEVTDMAE + Force Event DMA Error + 28 + 1 + write-only + + + FEVTCINT + Force Event Card Interrupt + 31 + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + ADMA Error State (when ADMA Error is occurred) + 0 + 2 + read-only + + + ADMALME + ADMA Length Mismatch Error + 2 + 1 + read-only + + + ADMALME_0 + No Error + 0 + + + ADMALME_1 + Error + 0x1 + + + + + ADMADCE + ADMA Descriptor Error + 3 + 1 + read-only + + + ADMADCE_0 + No Error + 0 + + + ADMADCE_1 + Error + 0x1 + + + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADS_ADDR + ADMA System Address + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + DLL_CTRL_ENABLE + 0 + 1 + read-write + + + DLL_CTRL_RESET + DLL_CTRL_RESET + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + DLL_CTRL_SLV_FORCE_UPD + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + DLL_CTRL_SLV_DLY_TARGET0 + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + DLL_CTRL_GATE_UPDATE + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + DLL_CTRL_SLV_OVERRIDE + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + DLL_CTRL_SLV_OVERRIDE_VAL + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + DLL_CTRL_SLV_DLY_TARGET1 + 16 + 3 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + DLL_CTRL_SLV_UPDATE_INT + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + DLL_CTRL_REF_UPDATE_INT + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0x200 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + DLL_STS_SLV_LOCK + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + DLL_STS_REF_LOCK + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + DLL_STS_SLV_SEL + 2 + 7 + read-only + + + DLL_STS_REF_SEL + DLL_STS_REF_SEL + 9 + 7 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + DLY_CELL_SET_POST + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + DLY_CELL_SET_OUT + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + DLY_CELL_SET_PRE + 8 + 7 + read-write + + + NXT_ERR + NXT_ERR + 15 + 1 + read-only + + + TAP_SEL_POST + TAP_SEL_POST + 16 + 4 + read-only + + + TAP_SEL_OUT + TAP_SEL_OUT + 20 + 4 + read-only + + + TAP_SEL_PRE + TAP_SEL_PRE + 24 + 7 + read-only + + + PRE_ERR + PRE_ERR + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + VSELECT + Voltage Selection + 1 + 1 + read-write + + + VSELECT_0 + Change the voltage to high voltage range, around 3.0 V + 0 + + + VSELECT_1 + Change the voltage to low voltage range, around 1.8 V + 0x1 + + + + + CONFLICT_CHK_EN + Conflict check enable. + 2 + 1 + read-write + + + CONFLICT_CHK_EN_0 + Conflict check disable + 0 + + + CONFLICT_CHK_EN_1 + Conflict check enable + 0x1 + + + + + AC12_WR_CHKBUSY_EN + AC12_WR_CHKBUSY_EN + 3 + 1 + read-write + + + AC12_WR_CHKBUSY_EN_0 + Do not check busy after auto CMD12 for write data packet + 0 + + + AC12_WR_CHKBUSY_EN_1 + Check busy after auto CMD12 for write data packet + 0x1 + + + + + FRC_SDCLK_ON + FRC_SDCLK_ON + 8 + 1 + read-write + + + FRC_SDCLK_ON_0 + CLK active or inactive is fully controlled by the hardware. + 0 + + + FRC_SDCLK_ON_1 + Force CLK active. + 0x1 + + + + + CRC_CHK_DIS + CRC Check Disable + 15 + 1 + read-write + + + CRC_CHK_DIS_0 + Check CRC16 for every read data packet and check CRC bits for every write data packet + 0 + + + CRC_CHK_DIS_1 + Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + 0x1 + + + + + CMD_BYTE_EN + CMD_BYTE_EN + 31 + 1 + read-write + + + CMD_BYTE_EN_0 + Disable + 0 + + + CMD_BYTE_EN_1 + Enable + 0x1 + + + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + DTOCV_ACK + 0 + 4 + read-write + + + DTOCV_ACK_0 + SDCLK x 2^14 + 0 + + + DTOCV_ACK_1 + SDCLK x 2^15 + 0x1 + + + DTOCV_ACK_2 + SDCLK x 2^16 + 0x2 + + + DTOCV_ACK_3 + SDCLK x 2^17 + 0x3 + + + DTOCV_ACK_4 + SDCLK x 2^18 + 0x4 + + + DTOCV_ACK_5 + SDCLK x 2^19 + 0x5 + + + DTOCV_ACK_6 + SDCLK x 2^20 + 0x6 + + + DTOCV_ACK_7 + SDCLK x 2^21 + 0x7 + + + DTOCV_ACK_14 + SDCLK x 2^28 + 0xE + + + DTOCV_ACK_15 + SDCLK x 2^29 + 0xF + + + + + BOOT_ACK + BOOT_ACK + 4 + 1 + read-write + + + BOOT_ACK_0 + No ack + 0 + + + BOOT_ACK_1 + Ack + 0x1 + + + + + BOOT_MODE + BOOT_MODE + 5 + 1 + read-write + + + BOOT_MODE_0 + Normal boot + 0 + + + BOOT_MODE_1 + Alternative boot + 0x1 + + + + + BOOT_EN + BOOT_EN + 6 + 1 + read-write + + + BOOT_EN_0 + Fast boot disable + 0 + + + BOOT_EN_1 + Fast boot enable + 0x1 + + + + + AUTO_SABG_EN + AUTO_SABG_EN + 7 + 1 + read-write + + + DISABLE_TIME_OUT + Disable Time Out + 8 + 1 + read-write + + + DISABLE_TIME_OUT_0 + Enable time out + 0 + + + DISABLE_TIME_OUT_1 + Disable time out + 0x1 + + + + + BOOT_BLK_CNT + BOOT_BLK_CNT + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x1006 + 0xFFFFFFFF + + + CARD_INT_D3_TEST + Card Interrupt Detection Test + 3 + 1 + read-write + + + CARD_INT_D3_TEST_0 + Check the card interrupt only when DATA3 is high. + 0 + + + CARD_INT_D3_TEST_1 + Check the card interrupt by ignoring the status of DATA3. + 0x1 + + + + + TUNING_8bit_EN + TUNING_8bit_EN + 4 + 1 + read-write + + + TUNING_1bit_EN + TUNING_1bit_EN + 5 + 1 + read-write + + + TUNING_CMD_EN + TUNING_CMD_EN + 6 + 1 + read-write + + + TUNING_CMD_EN_0 + Auto tuning circuit does not check the CMD line. + 0 + + + TUNING_CMD_EN_1 + Auto tuning circuit checks the CMD line. + 0x1 + + + + + ACMD23_ARGU2_EN + Argument2 register enable for ACMD23 + 12 + 1 + read-write + + + ACMD23_ARGU2_EN_0 + Disable + 0 + + + ACMD23_ARGU2_EN_1 + Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + 0x1 + + + + + PART_DLL_DEBUG + debug for part dll + 13 + 1 + read-write + + + BUS_RST + BUS reset + 14 + 1 + read-write + + + + + TUNING_CTRL + Tuning Control Register + 0xCC + 32 + read-write + 0x212800 + 0xFFFFFFFF + + + TUNING_START_TAP + TUNING_START_TAP + 0 + 8 + read-write + + + TUNING_COUNTER + TUNING_COUNTER + 8 + 8 + read-write + + + TUNING_STEP + TUNING_STEP + 16 + 3 + read-write + + + TUNING_WINDOW + TUNING_WINDOW + 20 + 3 + read-write + + + STD_TUNING_EN + STD_TUNING_EN + 24 + 1 + read-write + + + + + + + USDHC2 + uSDHC + uSDHC + 0x402C4000 + + 0 + 0xD0 + registers + + + USDHC2 + 111 + + + + ENET + Ethernet MAC-NET Core + ENET + ENET_ + 0x402D8000 + + 0 + 0x628 + registers + + + ENET + 114 + + + ENET_1588_Timer + 115 + + + + EIR + Interrupt Event Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + Timestamp Timer + 15 + 1 + read-write + oneToClear + + + TS_AVAIL + Transmit Timestamp Available + 16 + 1 + read-write + oneToClear + + + WAKEUP + Node Wakeup Request Indication + 17 + 1 + read-write + oneToClear + + + PLR + Payload Receive Error + 18 + 1 + read-write + oneToClear + + + UN + Transmit FIFO Underrun + 19 + 1 + read-write + oneToClear + + + RL + Collision Retry Limit + 20 + 1 + read-write + oneToClear + + + LC + Late Collision + 21 + 1 + read-write + oneToClear + + + EBERR + Ethernet Bus Error + 22 + 1 + read-write + oneToClear + + + MII + MII Interrupt. + 23 + 1 + read-write + oneToClear + + + RXB + Receive Buffer Interrupt + 24 + 1 + read-write + oneToClear + + + RXF + Receive Frame Interrupt + 25 + 1 + read-write + oneToClear + + + TXB + Transmit Buffer Interrupt + 26 + 1 + read-write + oneToClear + + + TXF + Transmit Frame Interrupt + 27 + 1 + read-write + oneToClear + + + GRA + Graceful Stop Complete + 28 + 1 + read-write + oneToClear + + + BABT + Babbling Transmit Error + 29 + 1 + read-write + oneToClear + + + BABR + Babbling Receive Error + 30 + 1 + read-write + oneToClear + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + TS_TIMER Interrupt Mask + 15 + 1 + read-write + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 16 + 1 + read-write + + + WAKEUP + WAKEUP Interrupt Mask + 17 + 1 + read-write + + + PLR + PLR Interrupt Mask + 18 + 1 + read-write + + + UN + UN Interrupt Mask + 19 + 1 + read-write + + + RL + RL Interrupt Mask + 20 + 1 + read-write + + + LC + LC Interrupt Mask + 21 + 1 + read-write + + + EBERR + EBERR Interrupt Mask + 22 + 1 + read-write + + + MII + MII Interrupt Mask + 23 + 1 + read-write + + + RXB + RXB Interrupt Mask + 24 + 1 + read-write + + + RXF + RXF Interrupt Mask + 25 + 1 + read-write + + + TXB + TXB Interrupt Mask + 26 + 1 + read-write + + + TXB_0 + The corresponding interrupt source is masked. + 0 + + + TXB_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + TXF + TXF Interrupt Mask + 27 + 1 + read-write + + + TXF_0 + The corresponding interrupt source is masked. + 0 + + + TXF_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + GRA + GRA Interrupt Mask + 28 + 1 + read-write + + + GRA_0 + The corresponding interrupt source is masked. + 0 + + + GRA_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABT + BABT Interrupt Mask + 29 + 1 + read-write + + + BABT_0 + The corresponding interrupt source is masked. + 0 + + + BABT_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABR + BABR Interrupt Mask + 30 + 1 + read-write + + + BABR_0 + The corresponding interrupt source is masked. + 0 + + + BABR_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + + + RDAR + Receive Descriptor Active Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + + + TDAR + Transmit Descriptor Active Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0x70000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 1 + 1 + read-write + + + ETHEREN_0 + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + 0 + + + ETHEREN_1 + MAC is enabled, and reception and transmission are possible. + 0x1 + + + + + MAGICEN + Magic Packet Detection Enable + 2 + 1 + read-write + + + MAGICEN_0 + Magic detection logic disabled. + 0 + + + MAGICEN_1 + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + 0x1 + + + + + SLEEP + Sleep Mode Enable + 3 + 1 + read-write + + + SLEEP_0 + Normal operating mode. + 0 + + + SLEEP_1 + Sleep mode. + 0x1 + + + + + EN1588 + EN1588 Enable + 4 + 1 + read-write + + + EN1588_0 + Legacy FEC buffer descriptors and functions enabled. + 0 + + + EN1588_1 + Enhanced frame time-stamping functions enabled. + 0x1 + + + + + DBGEN + Debug Enable + 6 + 1 + read-write + + + DBGEN_0 + MAC continues operation in debug mode. + 0 + + + DBGEN_1 + MAC enters hardware freeze mode when the processor is in debug mode. + 0x1 + + + + + DBSWP + Descriptor Byte Swapping Enable + 8 + 1 + read-write + + + DBSWP_0 + The buffer descriptor bytes are not swapped to support big-endian devices. + 0 + + + DBSWP_1 + The buffer descriptor bytes are swapped to support little-endian devices. + 0x1 + + + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 16 + 2 + read-write + + + RA + Register Address + 18 + 5 + read-write + + + PA + PHY Address + 23 + 5 + read-write + + + OP + Operation Code + 28 + 2 + read-write + + + ST + Start Of Frame Delimiter + 30 + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MII_SPEED + MII Speed + 1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 7 + 1 + read-write + + + DIS_PRE_0 + Preamble enabled. + 0 + + + DIS_PRE_1 + Preamble (32 ones) is not prepended to the MII management frame. + 0x1 + + + + + HOLDTIME + Hold time On MDIO Output + 8 + 3 + read-write + + + HOLDTIME_0 + 1 internal module clock cycle + 0 + + + HOLDTIME_1 + 2 internal module clock cycles + 0x1 + + + HOLDTIME_2 + 3 internal module clock cycles + 0x2 + + + HOLDTIME_7 + 8 internal module clock cycles + 0x7 + + + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + MIB_CLEAR + MIB Clear + 29 + 1 + read-write + + + MIB_CLEAR_0 + See note above. + 0 + + + MIB_CLEAR_1 + All statistics counters are reset to 0. + 0x1 + + + + + MIB_IDLE + MIB Idle + 30 + 1 + read-only + + + MIB_IDLE_0 + The MIB block is updating MIB counters. + 0 + + + MIB_IDLE_1 + The MIB block is not currently updating any MIB counters. + 0x1 + + + + + MIB_DIS + Disable MIB Logic + 31 + 1 + read-write + + + MIB_DIS_0 + MIB logic is enabled. + 0 + + + MIB_DIS_1 + MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + 0x1 + + + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + LOOP_0 + Loopback disabled. + 0 + + + LOOP_1 + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + 0x1 + + + + + DRT + Disable Receive On Transmit + 1 + 1 + read-write + + + DRT_0 + Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + 0 + + + DRT_1 + Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + 0x1 + + + + + MII_MODE + Media Independent Interface Mode + 2 + 1 + read-write + + + MII_MODE_1 + MII or RMII mode, as indicated by the RMII_MODE field. + 0x1 + + + + + PROM + Promiscuous Mode + 3 + 1 + read-write + + + PROM_0 + Disabled. + 0 + + + PROM_1 + Enabled. + 0x1 + + + + + BC_REJ + Broadcast Frame Reject + 4 + 1 + read-write + + + FCE + Flow Control Enable + 5 + 1 + read-write + + + RMII_MODE + RMII Mode Enable + 8 + 1 + read-write + + + RMII_MODE_0 + MAC configured for MII mode. + 0 + + + RMII_MODE_1 + MAC configured for RMII operation. + 0x1 + + + + + RMII_10T + Enables 10-Mbit/s mode of the RMII . + 9 + 1 + read-write + + + RMII_10T_0 + 100-Mbit/s operation. + 0 + + + RMII_10T_1 + 10-Mbit/s operation. + 0x1 + + + + + PADEN + Enable Frame Padding Remove On Receive + 12 + 1 + read-write + + + PADEN_0 + No padding is removed on receive by the MAC. + 0 + + + PADEN_1 + Padding is removed from received frames. + 0x1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 13 + 1 + read-write + + + PAUFWD_0 + Pause frames are terminated and discarded in the MAC. + 0 + + + PAUFWD_1 + Pause frames are forwarded to the user application. + 0x1 + + + + + CRCFWD + Terminate/Forward Received CRC + 14 + 1 + read-write + + + CRCFWD_0 + The CRC field of received frames is transmitted to the user application. + 0 + + + CRCFWD_1 + The CRC field is stripped from the frame. + 0x1 + + + + + CFEN + MAC Control Frame Enable + 15 + 1 + read-write + + + CFEN_0 + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + 0 + + + CFEN_1 + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + 0x1 + + + + + MAX_FL + Maximum Frame Length + 16 + 14 + read-write + + + NLC + Payload Length Check Disable + 30 + 1 + read-write + + + NLC_0 + The payload length check is disabled. + 0 + + + NLC_1 + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + 0x1 + + + + + GRS + Graceful Receive Stopped + 31 + 1 + read-only + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + FDEN + Full-Duplex Enable + 2 + 1 + read-write + + + TFC_PAUSE + Transmit Frame Control Pause + 3 + 1 + read-write + + + TFC_PAUSE_0 + No PAUSE frame transmitted. + 0 + + + TFC_PAUSE_1 + The MAC stops transmission of data frames after the current transmission is complete. + 0x1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 5 + 3 + read-write + + + ADDSEL_0 + Node MAC address programmed on PADDR1/2 registers. + 0 + + + + + ADDINS + Set MAC Address On Transmit + 8 + 1 + read-write + + + ADDINS_0 + The source MAC address is not modified by the MAC. + 0 + + + ADDINS_1 + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + 0x1 + + + + + CRCFWD + Forward Frame From Application With CRC + 9 + 1 + read-write + + + CRCFWD_0 + TxBD[TC] controls whether the frame has a CRC from the application. + 0 + + + CRCFWD_1 + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + 0x1 + + + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames + 16 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 16 + 16 + read-only + + + + + TXIC + Transmit Interrupt Coalescing Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + RXIC + Receive Interrupt Coalescing Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + TFWR_0 + 64 bytes written. + 0 + + + TFWR_1 + 64 bytes written. + 0x1 + + + TFWR_2 + 128 bytes written. + 0x2 + + + TFWR_3 + 192 bytes written. + 0x3 + + + TFWR_31 + 1984 bytes written. + 0x1F + + + + + STRFWD + Store And Forward Enable + 8 + 1 + read-write + + + STRFWD_0 + Reset. The transmission start threshold is programmed in TFWR[TFWR]. + 0 + + + STRFWD_1 + Enabled. + 0x1 + + + + + + + RDSR + Receive Descriptor Ring Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue. + 3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of the transmit buffer descriptor queue. + 3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 4 + 10 + read-write + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 8 + read-write + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 8 + read-write + + + STAT_SECTION_EMPTY + RX Status FIFO Section Empty Threshold + 16 + 5 + read-write + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 8 + read-write + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value Of The Transmit FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + 0x1 + + + + + IPCHK + Enables insertion of IP header checksum. + 3 + 1 + read-write + + + IPCHK_0 + Checksum is not inserted. + 0 + + + IPCHK_1 + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + 0x1 + + + + + PROCHK + Enables insertion of protocol checksum. + 4 + 1 + read-write + + + PROCHK_0 + Checksum not inserted. + 0 + + + PROCHK_1 + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + 0x1 + + + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + PADREM_0 + Padding not removed. + 0 + + + PADREM_1 + Any bytes following the IP payload section of the frame are removed from the frame. + 0x1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 1 + 1 + read-write + + + IPDIS_0 + Frames with wrong IPv4 header checksum are not discarded. + 0 + + + IPDIS_1 + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 2 + 1 + read-write + + + PRODIS_0 + Frames with wrong checksum are not discarded. + 0 + + + PRODIS_1 + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 6 + 1 + read-write + + + LINEDIS_0 + Frames with errors are not discarded. + 0 + + + LINEDIS_1 + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + 0x1 + + + + + SHIFT16 + RX FIFO Shift-16 + 7 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + 0x1 + + + + + + + RMON_T_DROP + Reserved Statistic Register + 0x200 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_T_PACKETS + Tx Packet Count Statistic Register + 0x204 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packet count + 0 + 16 + read-only + + + + + RMON_T_BC_PKT + Tx Broadcast Packets Statistic Register + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Broadcast packets + 0 + 16 + read-only + + + + + RMON_T_MC_PKT + Tx Multicast Packets Statistic Register + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Multicast packets + 0 + 16 + read-only + + + + + RMON_T_CRC_ALIGN + Tx Packets with CRC/Align Error Statistic Register + 0x210 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packets with CRC/align error + 0 + 16 + read-only + + + + + RMON_T_UNDERSIZE + Tx Packets Less Than Bytes and Good CRC Statistic Register + 0x214 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets less than 64 bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_OVERSIZE + Tx Packets GT MAX_FL bytes and Good CRC Statistic Register + 0x218 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_FRAG + Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x21C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets less than 64 bytes with bad CRC + 0 + 16 + read-only + + + + + RMON_T_JAB + Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_T_COL + Tx Collision Count Statistic Register + 0x224 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit collisions + 0 + 16 + read-only + + + + + RMON_T_P64 + Tx 64-Byte Packets Statistic Register + 0x228 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 64-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P65TO127 + Tx 65- to 127-byte Packets Statistic Register + 0x22C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 65- to 127-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P128TO255 + Tx 128- to 255-byte Packets Statistic Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 128- to 255-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P256TO511 + Tx 256- to 511-byte Packets Statistic Register + 0x234 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 256- to 511-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P512TO1023 + Tx 512- to 1023-byte Packets Statistic Register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 512- to 1023-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P1024TO2047 + Tx 1024- to 2047-byte Packets Statistic Register + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 1024- to 2047-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P_GTE2048 + Tx Packets Greater Than 2048 Bytes Statistic Register + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than 2048 bytes + 0 + 16 + read-only + + + + + RMON_T_OCTETS + Tx Octets Statistic Register + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXOCTS + Number of transmit octets + 0 + 32 + read-only + + + + + IEEE_T_DROP + Reserved Statistic Register + 0x248 + 32 + read-only + 0 + 0xFFFFFFFF + + + IEEE_T_FRAME_OK + Frames Transmitted OK Statistic Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted OK + 0 + 16 + read-only + + + + + IEEE_T_1COL + Frames Transmitted with Single Collision Statistic Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with one collision + 0 + 16 + read-only + + + + + IEEE_T_MCOL + Frames Transmitted with Multiple Collisions Statistic Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with multiple collisions + 0 + 16 + read-only + + + + + IEEE_T_DEF + Frames Transmitted after Deferral Delay Statistic Register + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with deferral delay + 0 + 16 + read-only + + + + + IEEE_T_LCOL + Frames Transmitted with Late Collision Statistic Register + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with late collision + 0 + 16 + read-only + + + + + IEEE_T_EXCOL + Frames Transmitted with Excessive Collisions Statistic Register + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with excessive collisions + 0 + 16 + read-only + + + + + IEEE_T_MACERR + Frames Transmitted with Tx FIFO Underrun Statistic Register + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with transmit FIFO underrun + 0 + 16 + read-only + + + + + IEEE_T_CSERR + Frames Transmitted with Carrier Sense Error Statistic Register + 0x268 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with carrier sense error + 0 + 16 + read-only + + + + + IEEE_T_SQE + Reserved Statistic Register + 0x26C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + This read-only field is reserved and always has the value 0 + 0 + 16 + read-only + + + + + IEEE_T_FDXFC + Flow Control Pause Frames Transmitted Statistic Register + 0x270 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames transmitted + 0 + 16 + read-only + + + + + IEEE_T_OCTETS_OK + Octet Count for Frames Transmitted w/o Error Statistic Register + 0x274 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + 0 + 32 + read-only + + + + + RMON_R_PACKETS + Rx Packet Count Statistic Register + 0x284 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of packets received + 0 + 16 + read-only + + + + + RMON_R_BC_PKT + Rx Broadcast Packets Statistic Register + 0x288 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive broadcast packets + 0 + 16 + read-only + + + + + RMON_R_MC_PKT + Rx Multicast Packets Statistic Register + 0x28C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive multicast packets + 0 + 16 + read-only + + + + + RMON_R_CRC_ALIGN + Rx Packets with CRC/Align Error Statistic Register + 0x290 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with CRC or align error + 0 + 16 + read-only + + + + + RMON_R_UNDERSIZE + Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register + 0x294 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and good CRC + 0 + 16 + read-only + + + + + RMON_R_OVERSIZE + Rx Packets Greater Than MAX_FL and Good CRC Statistic Register + 0x298 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and good CRC + 0 + 16 + read-only + + + + + RMON_R_FRAG + Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x29C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_R_JAB + Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register + 0x2A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and bad CRC + 0 + 16 + read-only + + + + + RMON_R_RESVD_0 + Reserved Statistic Register + 0x2A4 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_R_P64 + Rx 64-Byte Packets Statistic Register + 0x2A8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 64-byte receive packets + 0 + 16 + read-only + + + + + RMON_R_P65TO127 + Rx 65- to 127-Byte Packets Statistic Register + 0x2AC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 65- to 127-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P128TO255 + Rx 128- to 255-Byte Packets Statistic Register + 0x2B0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 128- to 255-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P256TO511 + Rx 256- to 511-Byte Packets Statistic Register + 0x2B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 256- to 511-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P512TO1023 + Rx 512- to 1023-Byte Packets Statistic Register + 0x2B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 512- to 1023-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P1024TO2047 + Rx 1024- to 2047-Byte Packets Statistic Register + 0x2BC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 1024- to 2047-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P_GTE2048 + Rx Packets Greater than 2048 Bytes Statistic Register + 0x2C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of greater-than-2048-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_OCTETS + Rx Octets Statistic Register + 0x2C4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive octets + 0 + 32 + read-only + + + + + IEEE_R_DROP + Frames not Counted Correctly Statistic Register + 0x2C8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Frame count + 0 + 16 + read-only + + + + + IEEE_R_FRAME_OK + Frames Received OK Statistic Register + 0x2CC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received OK + 0 + 16 + read-only + + + + + IEEE_R_CRC + Frames Received with CRC Error Statistic Register + 0x2D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with CRC error + 0 + 16 + read-only + + + + + IEEE_R_ALIGN + Frames Received with Alignment Error Statistic Register + 0x2D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with alignment error + 0 + 16 + read-only + + + + + IEEE_R_MACERR + Receive FIFO Overflow Count Statistic Register + 0x2D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Receive FIFO overflow count + 0 + 16 + read-only + + + + + IEEE_R_FDXFC + Flow Control Pause Frames Received Statistic Register + 0x2DC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames received + 0 + 16 + read-only + + + + + IEEE_R_OCTETS_OK + Octet Count for Frames Received without Error Statistic Register + 0x2E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of octets for frames received without error + 0 + 32 + read-only + + + + + ATCR + Adjustable Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + EN_0 + The timer stops at the current value. + 0 + + + EN_1 + The timer starts incrementing. + 0x1 + + + + + OFFEN + Enable One-Shot Offset Event + 2 + 1 + read-write + + + OFFEN_0 + Disable. + 0 + + + OFFEN_1 + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + 0x1 + + + + + OFFRST + Reset Timer On Offset Event + 3 + 1 + read-write + + + OFFRST_0 + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + 0 + + + OFFRST_1 + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + 0x1 + + + + + PEREN + Enable Periodical Event + 4 + 1 + read-write + + + PEREN_0 + Disable. + 0 + + + PEREN_1 + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + 0x1 + + + + + PINPER + Enables event signal output assertion on period event + 7 + 1 + read-write + + + PINPER_0 + Disable. + 0 + + + PINPER_1 + Enable. + 0x1 + + + + + RESTART + Reset Timer + 9 + 1 + read-write + + + CAPTURE + Capture Timer Value + 11 + 1 + read-write + + + CAPTURE_0 + No effect. + 0 + + + CAPTURE_1 + The current time is captured and can be read from the ATVR register. + 0x1 + + + + + SLAVE + Enable Timer Slave Mode + 13 + 1 + read-write + + + SLAVE_0 + The timer is active and all configuration fields in this register are relevant. + 0 + + + SLAVE_1 + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + 0x1 + + + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + A write sets the timer + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + Offset value for one-shot event generation + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + Value for generating periodic events + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + INC_CORR + Correction Increment Value + 8 + 7 + read-write + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIMESTAMP + Timestamp of the last frame transmitted by the core that had TxBD[TS] set + 0 + 32 + read-only + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + oneToClear + + + TF0_0 + Timer Flag for Channel 0 is clear + 0 + + + TF0_1 + Timer Flag for Channel 0 is set + 0x1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 1 + 1 + read-write + oneToClear + + + TF1_0 + Timer Flag for Channel 1 is clear + 0 + + + TF1_1 + Timer Flag for Channel 1 is set + 0x1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 2 + 1 + read-write + oneToClear + + + TF2_0 + Timer Flag for Channel 2 is clear + 0 + + + TF2_1 + Timer Flag for Channel 2 is set + 0x1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 3 + 1 + read-write + oneToClear + + + TF3_0 + Timer Flag for Channel 3 is clear + 0 + + + TF3_1 + Timer Flag for Channel 3 is set + 0x1 + + + + + + + 4 + 0x8 + 0,1,2,3 + TCSR%s + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + TDRE_0 + DMA request is disabled + 0 + + + TDRE_1 + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMODE_0 + Timer Channel is disabled. + 0 + + + TMODE_1 + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMODE_2 + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMODE_3 + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMODE_4 + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMODE_5 + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMODE_6 + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMODE_7 + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMODE_9 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMODE_10 + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMODE_14 + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMODE_15 + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + TIE_0 + Interrupt is disabled + 0 + + + TIE_1 + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + TF_0 + Input Capture or Output Compare has not occurred. + 0 + + + TF_1 + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 11 + 5 + read-write + + + TPWC_0 + Pulse width is one 1588-clock cycle. + 0 + + + TPWC_1 + Pulse width is two 1588-clock cycles. + 0x1 + + + TPWC_2 + Pulse width is three 1588-clock cycles. + 0x2 + + + TPWC_3 + Pulse width is four 1588-clock cycles. + 0x3 + + + TPWC_31 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + 4 + 0x8 + 0,1,2,3 + TCCR%s + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + USB1 + USB + USB + USB_ + USB + 0x402E0000 + + 0 + 0x1E0 + registers + + + USB_OTG1 + 113 + + + + ID + Identification register + 0 + 32 + read-only + 0xE4A1FA05 + 0xFFFFFFFF + + + ID + Configuration number + 0 + 6 + read-only + + + NID + Complement version of ID + 8 + 6 + read-only + + + REVISION + Revision number of the controller core. + 16 + 8 + read-only + + + + + HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x35 + 0xFFFFFFFF + + + PHYW + Data width of the transciever connected to the controller core. PHYW bit reset value is + 4 + 2 + read-only + + + PHYW_0 + 8 bit wide data bus Software non-programmable + 0 + + + PHYW_1 + 16 bit wide data bus Software non-programmable + 0x1 + + + PHYW_2 + Reset to 8 bit wide data bus Software programmable + 0x2 + + + PHYW_3 + Reset to 16 bit wide data bus Software programmable + 0x3 + + + + + PHYM + Transciever type + 6 + 3 + read-only + + + PHYM_0 + UTMI/UMTI+ + 0 + + + PHYM_1 + ULPI DDR + 0x1 + + + PHYM_2 + ULPI + 0x2 + + + PHYM_3 + Serial Only + 0x3 + + + PHYM_4 + Software programmable - reset to UTMI/UTMI+ + 0x4 + + + PHYM_5 + Software programmable - reset to ULPI DDR + 0x5 + + + PHYM_6 + Software programmable - reset to ULPI + 0x6 + + + PHYM_7 + Software programmable - reset to Serial + 0x7 + + + + + SM + Serial interface mode capability + 9 + 2 + read-only + + + SM_0 + No Serial Engine, always use parallel signalling. + 0 + + + SM_1 + Serial Engine present, always use serial signalling for FS/LS. + 0x1 + + + SM_2 + Software programmable - Reset to use parallel signalling for FS/LS + 0x2 + + + SM_3 + Software programmable - Reset to use serial signalling for FS/LS + 0x3 + + + + + + + HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + Host Capable. Indicating whether host operation mode is supported or not. + 0 + 1 + read-only + + + HC_0 + Not supported + 0 + + + HC_1 + Supported + 0x1 + + + + + NPORT + The Nmber of downstream ports supported by the host controller is (NPORT+1) + 1 + 3 + read-only + + + + + HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + Device Capable. Indicating whether device operation mode is supported or not. + 0 + 1 + read-only + + + DC_0 + Not supported + 0 + + + DC_1 + Supported + 0x1 + + + + + DEVEP + Device Endpoint Number + 1 + 5 + read-only + + + + + HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + Default burst size for memory to TX buffer transfer + 0 + 8 + read-only + + + TXCHANADD + TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes + 16 + 8 + read-only + + + + + HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + Default burst size for memory to RX buffer transfer + 0 + 8 + read-only + + + RXADD + Buffer total size for all receive endpoints is (2^RXADD) + 8 + 8 + read-only + + + + + GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) + 0 + 3 + read-write + + + AHBBRST_0 + Incremental burst of unspecified length only + 0 + + + AHBBRST_1 + INCR4 burst, then single transfer + 0x1 + + + AHBBRST_2 + INCR8 burst, INCR4 burst, then single transfer + 0x2 + + + AHBBRST_3 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + 0x3 + + + AHBBRST_5 + INCR4 burst, then incremental burst of unspecified length + 0x5 + + + AHBBRST_6 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x6 + + + AHBBRST_7 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x7 + + + + + + + CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + These bits are used as an offset to add to register base to find the beginning of the Operational Register + 0 + 8 + read-only + + + + + HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. + 0 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + Number of downstream ports + 0 + 4 + read-only + + + PPC + Port Power Control This field indicates whether the host controller implementation includes port power control + 4 + 1 + read-only + + + N_PCC + Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller + 8 + 4 + read-only + + + N_CC + Number of Companion Controller (N_CC) + 12 + 4 + read-only + + + N_CC_0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + 0 + + + N_CC_1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + 0x1 + + + + + PI + Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control + 16 + 1 + read-only + + + N_PTT + Number of Ports per Transaction Translator (N_PTT) + 20 + 4 + read-only + + + N_TT + Number of Transaction Translators (N_TT) + 24 + 4 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported + 0 + 1 + read-only + + + PFL + Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller + 1 + 1 + read-only + + + ASP + Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule + 2 + 1 + read-only + + + IST + Isochronous Scheduling Threshold + 4 + 4 + read-only + + + EECP + EHCI Extended Capabilities Pointer + 8 + 8 + read-only + + + + + DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + Device Controller Interface Version Number Default value is '01h', which means rev0.1. + 0 + 16 + read-only + + + + + DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + Device Endpoint Number This field indicates the number of endpoints built into the device controller + 0 + 5 + read-only + + + DC + Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. + 7 + 1 + read-only + + + HC + Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 + 8 + 1 + read-only + + + + + USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + Run/Stop (RS) - Read/Write + 0 + 1 + read-write + + + RST + Controller Reset (RESET) - Read/Write + 1 + 1 + read-write + + + FS_1 + See description at bit 15 + 2 + 2 + read-write + + + PSE + Periodic Schedule Enable- Read/Write + 4 + 1 + read-write + + + PSE_0 + Do not process the Periodic Schedule + 0 + + + PSE_1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + 0x1 + + + + + ASE + Asynchronous Schedule Enable - Read/Write + 5 + 1 + read-write + + + ASE_0 + Do not process the Asynchronous Schedule. + 0 + + + ASE_1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 0x1 + + + + + IAA + Interrupt on Async Advance Doorbell - Read/Write + 6 + 1 + read-write + + + ASP + Asynchronous Schedule Park Mode Count - Read/Write + 8 + 2 + read-write + + + ASPE + Asynchronous Schedule Park Mode Enable - Read/Write + 11 + 1 + read-write + + + ATDTW + Add dTD TripWire - Read/Write + 12 + 1 + read-write + + + SUTW + Setup TripWire - Read/Write + 13 + 1 + read-write + + + FS_2 + See also bits 3-2 Frame List Size - (Read/Write or Read Only) + 15 + 1 + read-write + + + FS_2_0 + 1024 elements (4096 bytes) Default value + 0 + + + FS_2_1 + 512 elements (2048 bytes) + 0x1 + + + + + ITC + Interrupt Threshold Control -Read/Write + 16 + 8 + read-write + + + ITC_0 + Immediate (no threshold) + 0 + + + ITC_1 + 1 micro-frame + 0x1 + + + ITC_2 + 2 micro-frames + 0x2 + + + ITC_4 + 4 micro-frames + 0x4 + + + ITC_8 + 8 micro-frames + 0x8 + + + ITC_16 + 16 micro-frames + 0x10 + + + ITC_32 + 32 micro-frames + 0x20 + + + ITC_64 + 64 micro-frames + 0x40 + + + + + + + USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + USB Interrupt (USBINT) - R/WC + 0 + 1 + read-write + + + UEI + USB Error Interrupt (USBERRINT) - R/WC + 1 + 1 + read-write + + + PCI + Port Change Detect - R/WC + 2 + 1 + read-write + + + FRI + Frame List Rollover - R/WC + 3 + 1 + read-write + + + SEI + System Error- R/WC + 4 + 1 + read-write + + + AAI + Interrupt on Async Advance - R/WC + 5 + 1 + read-write + + + URI + USB Reset Received - R/WC + 6 + 1 + read-write + + + SRI + SOF Received - R/WC + 7 + 1 + read-write + + + SLI + DCSuspend - R/WC + 8 + 1 + read-write + + + ULPII + ULPI Interrupt - R/WC + 10 + 1 + read-write + + + HCH + HCHaIted - Read Only + 12 + 1 + read-write + + + RCL + Reclamation - Read Only + 13 + 1 + read-write + + + PS + Periodic Schedule Status - Read Only + 14 + 1 + read-write + + + AS + Asynchronous Schedule Status - Read Only + 15 + 1 + read-write + + + NAKI + NAK Interrupt Bit--RO + 16 + 1 + read-only + + + TI0 + General Purpose Timer Interrupt 0(GPTINT0)--R/WC + 24 + 1 + read-write + + + TI1 + General Purpose Timer Interrupt 1(GPTINT1)--R/WC + 25 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt + 0 + 1 + read-write + + + UEE + USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt + 1 + 1 + read-write + + + PCE + Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt + 2 + 1 + read-write + + + FRE + Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt + 3 + 1 + read-write + + + SEE + System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt + 4 + 1 + read-write + + + AAE + Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt + 5 + 1 + read-write + + + URE + USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt + 6 + 1 + read-write + + + SRE + SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt + 7 + 1 + read-write + + + SLE + Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt + 8 + 1 + read-write + + + ULPIE + ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt + 10 + 1 + read-write + + + NAKE + NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt + 16 + 1 + read-write + + + UAIE + USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 18 + 1 + read-write + + + UPIE + USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 19 + 1 + read-write + + + TIE0 + General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt + 24 + 1 + read-write + + + TIE1 + General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt + 25 + 1 + read-write + + + + + FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + Frame Index + 0 + 14 + read-write + + + FRINDEX_0 + (1024) 12 + 0 + + + FRINDEX_1 + (512) 11 + 0x1 + + + FRINDEX_2 + (256) 10 + 0x2 + + + FRINDEX_3 + (128) 9 + 0x3 + + + FRINDEX_4 + (64) 8 + 0x4 + + + FRINDEX_5 + (32) 7 + 0x5 + + + FRINDEX_6 + (16) 6 + 0x6 + + + FRINDEX_7 + (8) 5 + 0x7 + + + + + + + DEVICEADDR + Device Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBADRA + Device Address Advance + 24 + 1 + read-write + + + USBADR + Device Address. These bits correspond to the USB device address + 25 + 7 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASEADR + Base Address (Low) + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASYBASE + Link Pointer Low (LPL) + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPBASE + Endpoint List Pointer(Low) + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + RXPBURST + Programmable RX Burst Size + 0 + 8 + read-write + + + TXPBURST + Programmable TX Burst Size + 8 + 9 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXSCHOH + Scheduler Overhead + 0 + 8 + read-write + + + TXSCHHEALTH + Scheduler Health Counter + 8 + 5 + read-write + + + TXFIFOTHRES + FIFO Burst Threshold + 16 + 6 + read-write + + + + + ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + RX Endpoint NAK - R/WC + 0 + 8 + read-write + + + EPTN + TX Endpoint NAK - R/WC + 16 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + RX Endpoint NAK Enable - R/W + 0 + 8 + read-write + + + EPTNE + TX Endpoint NAK Enable - R/W + 16 + 8 + read-write + + + + + CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller + 0 + 1 + read-only + + + CF_0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + 0 + + + CF_1 + Port routing control logic default-routes all ports to this host controller. + 0x1 + + + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + Current Connect Status-Read Only + 0 + 1 + read-only + + + CSC + Connect Status Change-R/WC + 1 + 1 + read-write + + + PE + Port Enabled/Disabled-Read/Write + 2 + 1 + read-write + + + PEC + Port Enable/Disable Change-R/WC + 3 + 1 + read-write + + + OCA + Over-current Active-Read Only + 4 + 1 + read-only + + + OCA_0 + This port does not have an over-current condition. + 0 + + + OCA_1 + This port currently has an over-current condition + 0x1 + + + + + OCC + Over-current Change-R/WC + 5 + 1 + read-write + + + FPR + Force Port Resume -Read/Write + 6 + 1 + read-write + + + SUSP + Suspend - Read/Write or Read Only + 7 + 1 + read-write + + + PR + Port Reset - Read/Write or Read Only + 8 + 1 + read-write + + + HSP + High-Speed Port - Read Only + 9 + 1 + read-only + + + LS + Line Status-Read Only + 10 + 2 + read-write + + + LS_0 + SE0 + 0 + + + LS_1 + K-state + 0x1 + + + LS_2 + J-state + 0x2 + + + LS_3 + Undefined + 0x3 + + + + + PP + Port Power (PP)-Read/Write or Read Only + 12 + 1 + read-write + + + PO + Port Owner-Read/Write + 13 + 1 + read-write + + + PIC + Port Indicator Control - Read/Write + 14 + 2 + read-write + + + PIC_0 + Port indicators are off + 0 + + + PIC_1 + Amber + 0x1 + + + PIC_2 + Green + 0x2 + + + PIC_3 + Undefined + 0x3 + + + + + PTC + Port Test Control - Read/Write + 16 + 4 + read-write + + + PTC_0 + TEST_MODE_DISABLE + 0 + + + PTC_1 + J_STATE + 0x1 + + + PTC_2 + K_STATE + 0x2 + + + PTC_3 + SE0 (host) / NAK (device) + 0x3 + + + PTC_4 + Packet + 0x4 + + + PTC_5 + FORCE_ENABLE_HS + 0x5 + + + PTC_6 + FORCE_ENABLE_FS + 0x6 + + + PTC_7 + FORCE_ENABLE_LS + 0x7 + + + + + WKCN + Wake on Connect Enable (WKCNNT_E) - Read/Write + 20 + 1 + read-write + + + WKDC + Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write + 21 + 1 + read-write + + + WKOC + Wake on Over-current Enable (WKOC_E) - Read/Write + 22 + 1 + read-write + + + PHCD + PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write + 23 + 1 + read-write + + + PHCD_0 + Enable PHY clock + 0 + + + PHCD_1 + Disable PHY clock + 0x1 + + + + + PFSC + Port Force Full Speed Connect - Read/Write + 24 + 1 + read-write + + + PFSC_0 + Normal operation + 0 + + + PFSC_1 + Forced to full speed + 0x1 + + + + + PTS_2 + See description at bits 31-30 + 25 + 1 + read-write + + + PSPD + Port Speed - Read Only. This register field indicates the speed at which the port is operating. + 26 + 2 + read-write + + + PSPD_0 + Full Speed + 0 + + + PSPD_1 + Low Speed + 0x1 + + + PSPD_2 + High Speed + 0x2 + + + PSPD_3 + Undefined + 0x3 + + + + + PTW + Parallel Transceiver Width This bit has no effect if serial interface engine is used + 28 + 1 + read-write + + + PTW_0 + Select the 8-bit UTMI interface [60MHz] + 0 + + + PTW_1 + Select the 16-bit UTMI interface [30MHz] + 0x1 + + + + + STS + Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals + 29 + 1 + read-write + + + PTS_1 + All USB port interface modes are listed in this field description, but not all are supported + 30 + 2 + read-write + + + + + OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x1120 + 0xFFFFFFFF + + + VD + VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + VC + VBUS Charge - Read/Write + 1 + 1 + read-write + + + OT + OTG Termination - Read/Write + 3 + 1 + read-write + + + DP + Data Pulsing - Read/Write + 4 + 1 + read-write + + + IDPU + ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] + 5 + 1 + read-write + + + ID + USB ID - Read Only. 0 = A device, 1 = B device + 8 + 1 + read-only + + + AVV + A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ASV + A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + BSV + B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. + 11 + 1 + read-only + + + BSE + B Session End - Read Only. Indicates VBus is below the B session end threshold. + 12 + 1 + read-only + + + TOG_1MS + 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. + 13 + 1 + read-only + + + DPS + Data Bus Pulsing Status - Read Only + 14 + 1 + read-only + + + IDIS + USB ID Interrupt Status - Read/Write + 16 + 1 + read-write + + + AVVIS + A VBus Valid Interrupt Status - Read/Write to Clear + 17 + 1 + read-write + + + ASVIS + A Session Valid Interrupt Status - Read/Write to Clear + 18 + 1 + read-write + + + BSVIS + B Session Valid Interrupt Status - Read/Write to Clear + 19 + 1 + read-write + + + BSEIS + B Session End Interrupt Status - Read/Write to Clear + 20 + 1 + read-write + + + STATUS_1MS + 1 millisecond timer Interrupt Status - Read/Write to Clear + 21 + 1 + read-write + + + DPIS + Data Pulse Interrupt Status - Read/Write to Clear + 22 + 1 + read-write + + + IDIE + USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + AVVIE + A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + ASVIE + A Session Valid Interrupt Enable - Read/Write + 26 + 1 + read-write + + + BSVIE + B Session Valid Interrupt Enable - Read/Write + 27 + 1 + read-write + + + BSEIE + B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. + 28 + 1 + read-write + + + EN_1MS + 1 millisecond timer Interrupt Enable - Read/Write + 29 + 1 + read-write + + + DPIE + Data Pulse Interrupt Enable + 30 + 1 + read-write + + + + + USBMODE + USB Device Mode + 0x1A8 + 32 + read-write + 0x5000 + 0xFFFFFFFF + + + CM + Controller Mode - R/WO + 0 + 2 + read-write + + + CM_0 + Idle [Default for combination host/device] + 0 + + + CM_2 + Device Controller [Default for device only controller] + 0x2 + + + CM_3 + Host Controller [Default for host only controller] + 0x3 + + + + + ES + Endian Select - Read/Write + 2 + 1 + read-write + + + ES_0 + Little Endian [Default] + 0 + + + ES_1 + Big Endian + 0x1 + + + + + SLOM + Setup Lockout Mode + 3 + 1 + read-write + + + SLOM_0 + Setup Lockouts On (default); + 0 + + + SLOM_1 + Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + 0x1 + + + + + SDIS + Stream Disable Mode + 4 + 1 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENDPTSETUPSTAT + Setup Endpoint Status + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERB + Prime Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + PETB + Prime Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FERB + Flush Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + FETB + Flush Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status + 0x1B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERBR + Endpoint Receive Buffer Ready -- Read Only + 0 + 8 + read-only + + + ETBR + Endpoint Transmit Buffer Ready -- Read Only + 16 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERCE + Endpoint Receive Complete Event - RW/C + 0 + 8 + read-write + + + ETCE + Endpoint Transmit Complete Event - R/WC + 16 + 8 + read-write + + + + + ENDPTCTRL0 + Endpoint Control0 + 0x1C0 + 32 + read-write + 0x800080 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. + 2 + 2 + read-write + + + RXE + RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host + 16 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. + 18 + 2 + read-write + + + TXE + TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 23 + 1 + read-write + + + + + ENDPTCTRL1 + Endpoint Control 1 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL2 + Endpoint Control 2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL3 + Endpoint Control 3 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL4 + Endpoint Control 4 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL5 + Endpoint Control 5 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL6 + Endpoint Control 6 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL7 + Endpoint Control 7 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + + + USB2 + USB + USB + USB_ + 0x402E0200 + + 0 + 0x1E0 + registers + + + USB_OTG2 + 112 + + + + USBNC1 + USB + USB1 + USBNC + USBNC_ + USBNC + 0x402E0000 + + 0 + 0x81C + registers + + + + USB_OTG1_CTRL + USB OTG1 Control Register + 0x800 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTG1 Overcurrent Detection + 7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event + 8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity. + 9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt + 10 + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTG1 Software Wake-up Enable + 14 + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTG1 Software Wake-up + 15 + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTG1 Wake-up on ID change enable + 16 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTG1 wake-up on VBUS change enable + 17 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WKUP_DPDM_EN + Wake-up on DPDM change enable + 29 + 1 + read-write + + + WKUP_DPDM_EN_0 + DPDM changes wake-up to be disabled only when VBUS is 0. + 0 + + + WKUP_DPDM_EN_1 + (Default) DPDM changes wake-up to be enabled, it is for device only. + 0x1 + + + + + WIR + OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port + 31 + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTG1_PHY_CTRL_0 + OTG1 UTMI PHY Control 0 Register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTG1 UTMI PHY clock is valid + 31 + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + USBNC2 + USB + USBNC + USBNC_ + 0x402E0004 + + 0 + 0x81C + registers + + + + SEMC + SEMC + SEMC + 0x402F0000 + + 0 + 0x100 + registers + + + SEMC + 109 + + + + MCR + Module Control Register + 0 + 32 + read-write + 0x10000002 + 0xFFFFFFFF + + + SWRST + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + MDIS_0 + Module enabled + 0 + + + MDIS_1 + Module disabled. + 0x1 + + + + + DQSMD + DQS (read strobe) mode + 2 + 1 + read-write + + + DQSMD_0 + Dummy read strobe loopbacked internally + 0 + + + DQSMD_1 + Dummy read strobe loopbacked from DQS pad + 0x1 + + + + + WPOL0 + WAIT/RDY# polarity for NOR/PSRAM + 6 + 1 + read-write + + + WPOL0_0 + Low active + 0 + + + WPOL0_1 + High active + 0x1 + + + + + WPOL1 + WAIT/RDY# polarity for NAND + 7 + 1 + read-write + + + WPOL1_0 + Low active + 0 + + + WPOL1_1 + High active + 0x1 + + + + + CTO + Command Execution timeout cycles + 16 + 8 + read-write + + + BTO + Bus timeout cycles + 24 + 5 + read-write + + + BTO_0 + 255*1 + 0 + + + BTO_1 + 255*2 - 255*2^30 + 0x1 + + + BTO_2 + 255*2 - 255*2^30 + 0x2 + + + BTO_3 + 255*2 - 255*2^30 + 0x3 + + + BTO_4 + 255*2 - 255*2^30 + 0x4 + + + BTO_5 + 255*2 - 255*2^30 + 0x5 + + + BTO_6 + 255*2 - 255*2^30 + 0x6 + + + BTO_7 + 255*2 - 255*2^30 + 0x7 + + + BTO_8 + 255*2 - 255*2^30 + 0x8 + + + BTO_9 + 255*2 - 255*2^30 + 0x9 + + + BTO_31 + 255*2^31 + 0x1F + + + + + + + IOCR + IO Mux Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_A8 + SEMC_A8 output selection + 0 + 3 + read-write + + + MUX_A8_0 + SDRAM Address bit (A8) + 0 + + + MUX_A8_1 + NAND CE# + 0x1 + + + MUX_A8_2 + NOR CE# + 0x2 + + + MUX_A8_3 + PSRAM CE# + 0x3 + + + MUX_A8_4 + DBI CSX + 0x4 + + + MUX_A8_5 + SDRAM Address bit (A8) + 0x5 + + + MUX_A8_6 + SDRAM Address bit (A8) + 0x6 + + + MUX_A8_7 + SDRAM Address bit (A8) + 0x7 + + + + + MUX_CSX0 + SEMC_CSX0 output selection + 3 + 3 + read-write + + + MUX_CSX0_0 + NOR/PSRAM Address bit 24 (A24) + 0 + + + MUX_CSX0_1 + SDRAM CS1 + 0x1 + + + MUX_CSX0_2 + SDRAM CS2 + 0x2 + + + MUX_CSX0_3 + SDRAM CS3 + 0x3 + + + MUX_CSX0_4 + NAND CE# + 0x4 + + + MUX_CSX0_5 + NOR CE# + 0x5 + + + MUX_CSX0_6 + PSRAM CE# + 0x6 + + + MUX_CSX0_7 + DBI CSX + 0x7 + + + + + MUX_CSX1 + SEMC_CSX1 output selection + 6 + 3 + read-write + + + MUX_CSX1_0 + NOR/PSRAM Address bit 25 (A25) + 0 + + + MUX_CSX1_1 + SDRAM CS1 + 0x1 + + + MUX_CSX1_2 + SDRAM CS2 + 0x2 + + + MUX_CSX1_3 + SDRAM CS3 + 0x3 + + + MUX_CSX1_4 + NAND CE# + 0x4 + + + MUX_CSX1_5 + NOR CE# + 0x5 + + + MUX_CSX1_6 + PSRAM CE# + 0x6 + + + MUX_CSX1_7 + DBI CSX + 0x7 + + + + + MUX_CSX2 + SEMC_CSX2 output selection + 9 + 3 + read-write + + + MUX_CSX2_0 + NOR/PSRAM Address bit 26 (A26) + 0 + + + MUX_CSX2_1 + SDRAM CS1 + 0x1 + + + MUX_CSX2_2 + SDRAM CS2 + 0x2 + + + MUX_CSX2_3 + SDRAM CS3 + 0x3 + + + MUX_CSX2_4 + NAND CE# + 0x4 + + + MUX_CSX2_5 + NOR CE# + 0x5 + + + MUX_CSX2_6 + PSRAM CE# + 0x6 + + + MUX_CSX2_7 + DBI CSX + 0x7 + + + + + MUX_CSX3 + SEMC_CSX3 output selection + 12 + 3 + read-write + + + MUX_CSX3_0 + NOR/PSRAM Address bit 27 (A27) + 0 + + + MUX_CSX3_1 + SDRAM CS1 + 0x1 + + + MUX_CSX3_2 + SDRAM CS2 + 0x2 + + + MUX_CSX3_3 + SDRAM CS3 + 0x3 + + + MUX_CSX3_4 + NAND CE# + 0x4 + + + MUX_CSX3_5 + NOR CE# + 0x5 + + + MUX_CSX3_6 + PSRAM CE# + 0x6 + + + MUX_CSX3_7 + DBI CSX + 0x7 + + + + + MUX_RDY + SEMC_RDY function selection + 15 + 3 + read-write + + + MUX_RDY_0 + NAND Ready/Wait# input + 0 + + + MUX_RDY_1 + SDRAM CS1 + 0x1 + + + MUX_RDY_2 + SDRAM CS2 + 0x2 + + + MUX_RDY_3 + SDRAM CS3 + 0x3 + + + MUX_RDY_4 + NOR CE# + 0x4 + + + MUX_RDY_5 + PSRAM CE# + 0x5 + + + MUX_RDY_6 + DBI CSX + 0x6 + + + MUX_RDY_7 + NOR/PSRAM Address bit 27 + 0x7 + + + + + + + BMCR0 + Master Bus (AXI) Control Register 0 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WQOS + Weight of QoS + 0 + 4 + read-write + + + WAGE + Weight of Aging + 4 + 4 + read-write + + + WSH + Weight of Slave Hit (no read/write switch) + 8 + 8 + read-write + + + WRWS + Weight of Slave Hit (Read/Write switch) + 16 + 8 + read-write + + + + + BMCR1 + Master Bus (AXI) Control Register 1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WQOS + Weight of QoS + 0 + 4 + read-write + + + WAGE + Weight of Aging + 4 + 4 + read-write + + + WPH + Weight of Page Hit + 8 + 8 + read-write + + + WRWS + Weight of Read/Write switch + 16 + 8 + read-write + + + WBR + Weight of Bank Rotation + 24 + 8 + read-write + + + + + BR0 + Base Register 0 (For SDRAM CS0 device) + 0x10 + 32 + read-write + 0x8000001D + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR1 + Base Register 1 (For SDRAM CS1 device) + 0x14 + 32 + read-write + 0x8400001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR2 + Base Register 2 (For SDRAM CS2 device) + 0x18 + 32 + read-write + 0x8800001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR3 + Base Register 3 (For SDRAM CS3 device) + 0x1C + 32 + read-write + 0x8C00001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR4 + Base Register 4 (For NAND device) + 0x20 + 32 + read-write + 0x9E00001A + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR5 + Base Register 5 (For NOR device) + 0x24 + 32 + read-write + 0x90000018 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR6 + Base Register 6 (For PSRAM device) + 0x28 + 32 + read-write + 0x98000018 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR7 + Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device) + 0x2C + 32 + read-write + 0x9C00001A + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR8 + Base Register 8 (For NAND device) + 0x30 + 32 + read-write + 0x26 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP command done interrupt enable + 0 + 1 + read-write + + + IPCMDERREN + IP command error interrupt enable + 1 + 1 + read-write + + + AXICMDERREN + AXI command error interrupt enable + 2 + 1 + read-write + + + AXIBUSERREN + AXI bus error interrupt enable + 3 + 1 + read-write + + + NDPAGEENDEN + This bit enable/disable the NDPAGEEND interrupt generation. + 4 + 1 + read-write + + + NDPAGEENDEN_0 + Disable + 0 + + + NDPAGEENDEN_1 + Enable + 0x1 + + + + + NDNOPENDEN + This bit enable/disable the NDNOPEND interrupt generation. + 5 + 1 + read-write + + + NDNOPENDEN_0 + Disable + 0 + + + NDNOPENDEN_1 + Enable + 0x1 + + + + + + + INTR + Interrupt Enable Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + read-write + oneToClear + + + IPCMDERR + IP command error done interrupt + 1 + 1 + read-write + oneToClear + + + AXICMDERR + AXI command error interrupt + 2 + 1 + read-write + oneToClear + + + AXIBUSERR + AXI bus error interrupt + 3 + 1 + read-write + oneToClear + + + NDPAGEEND + This interrupt is generated when the last address of one page in NAND device is written by AXI command + 4 + 1 + read-write + oneToClear + + + NDNOPEND + This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface. + 5 + 1 + read-write + oneToClear + + + + + SDRAMCR0 + SDRAM control register 0 + 0x40 + 32 + read-write + 0xC26 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 8 + 0x4 + + + BL_5 + 8 + 0x5 + + + BL_6 + 8 + 0x6 + + + BL_7 + 8 + 0x7 + + + + + COL + Column address bit number + 8 + 2 + read-write + + + COL_0 + 12 bit + 0 + + + COL_1 + 11 bit + 0x1 + + + COL_2 + 10 bit + 0x2 + + + COL_3 + 9 bit + 0x3 + + + + + CL + CAS Latency + 10 + 2 + read-write + + + CL_0 + 1 + 0 + + + CL_1 + 1 + 0x1 + + + CL_2 + 2 + 0x2 + + + CL_3 + 3 + 0x3 + + + + + + + SDRAMCR1 + SDRAM control register 1 + 0x44 + 32 + read-write + 0x994934 + 0xFFFFFFFF + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time + 0 + 4 + read-write + + + ACT2RW + ACT to Read/Write wait time + 4 + 4 + read-write + + + RFRC + Refresh recovery time + 8 + 5 + read-write + + + WRC + Write recovery time + 13 + 3 + read-write + + + CKEOFF + CKE OFF minimum time + 16 + 4 + read-write + + + ACT2PRE + ACT to Precharge minimum time + 20 + 4 + read-write + + + + + SDRAMCR2 + SDRAM control register 2 + 0x48 + 32 + read-write + 0x80000EEE + 0xFFFFFFFF + + + SRRC + Self Refresh Recovery time + 0 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time + 8 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time + 16 + 8 + read-write + + + ITO + SDRAM Idle timeout + 24 + 8 + read-write + + + ITO_0 + IDLE timeout period is 256*Prescale period. + 0 + + + ITO_1 + IDLE timeout period is ITO*Prescale period. + 0x1 + + + ITO_2 + IDLE timeout period is ITO*Prescale period. + 0x2 + + + ITO_3 + IDLE timeout period is ITO*Prescale period. + 0x3 + + + ITO_4 + IDLE timeout period is ITO*Prescale period. + 0x4 + + + ITO_5 + IDLE timeout period is ITO*Prescale period. + 0x5 + + + ITO_6 + IDLE timeout period is ITO*Prescale period. + 0x6 + + + ITO_7 + IDLE timeout period is ITO*Prescale period. + 0x7 + + + ITO_8 + IDLE timeout period is ITO*Prescale period. + 0x8 + + + ITO_9 + IDLE timeout period is ITO*Prescale period. + 0x9 + + + + + + + SDRAMCR3 + SDRAM control register 3 + 0x4C + 32 + read-write + 0x40808000 + 0xFFFFFFFF + + + REN + Refresh enable + 0 + 1 + read-write + + + REBL + Refresh burst length + 1 + 3 + read-write + + + REBL_0 + 1 + 0 + + + REBL_1 + 2 + 0x1 + + + REBL_2 + 3 + 0x2 + + + REBL_3 + 4 + 0x3 + + + REBL_4 + 5 + 0x4 + + + REBL_5 + 6 + 0x5 + + + REBL_6 + 7 + 0x6 + + + REBL_7 + 8 + 0x7 + + + + + PRESCALE + Prescaler timer period + 8 + 8 + read-write + + + PRESCALE_0 + 256*16 cycle + 0 + + + PRESCALE_1 + PRESCALE*16 cycle + 0x1 + + + PRESCALE_2 + PRESCALE*16 cycle + 0x2 + + + PRESCALE_3 + PRESCALE*16 cycle + 0x3 + + + PRESCALE_4 + PRESCALE*16 cycle + 0x4 + + + PRESCALE_5 + PRESCALE*16 cycle + 0x5 + + + PRESCALE_6 + PRESCALE*16 cycle + 0x6 + + + PRESCALE_7 + PRESCALE*16 cycle + 0x7 + + + PRESCALE_8 + PRESCALE*16 cycle + 0x8 + + + PRESCALE_9 + PRESCALE*16 cycle + 0x9 + + + + + RT + Refresh timer period + 16 + 8 + read-write + + + RT_0 + 256*Prescaler period + 0 + + + RT_1 + RT*Prescaler period + 0x1 + + + RT_2 + RT*Prescaler period + 0x2 + + + RT_3 + RT*Prescaler period + 0x3 + + + RT_4 + RT*Prescaler period + 0x4 + + + RT_5 + RT*Prescaler period + 0x5 + + + RT_6 + RT*Prescaler period + 0x6 + + + RT_7 + RT*Prescaler period + 0x7 + + + RT_8 + RT*Prescaler period + 0x8 + + + RT_9 + RT*Prescaler period + 0x9 + + + + + UT + Refresh urgent threshold + 24 + 8 + read-write + + + UT_0 + 256*Prescaler period + 0 + + + UT_1 + UT*Prescaler period + 0x1 + + + UT_2 + UT*Prescaler period + 0x2 + + + UT_3 + UT*Prescaler period + 0x3 + + + UT_4 + UT*Prescaler period + 0x4 + + + UT_5 + UT*Prescaler period + 0x5 + + + UT_6 + UT*Prescaler period + 0x6 + + + UT_7 + UT*Prescaler period + 0x7 + + + UT_8 + UT*Prescaler period + 0x8 + + + UT_9 + UT*Prescaler period + 0x9 + + + + + + + NANDCR0 + NAND control register 0 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + EDO + EDO mode enabled + 7 + 1 + read-write + + + EDO_0 + EDO mode disabled + 0 + + + EDO_1 + EDO mode enabled + 0x1 + + + + + COL + Column address bit number + 8 + 3 + read-write + + + COL_0 + 16 + 0 + + + COL_1 + 15 + 0x1 + + + COL_2 + 14 + 0x2 + + + COL_3 + 13 + 0x3 + + + COL_4 + 12 + 0x4 + + + COL_5 + 11 + 0x5 + + + COL_6 + 10 + 0x6 + + + COL_7 + 9 + 0x7 + + + + + + + NANDCR1 + NAND control register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time + 0 + 4 + read-write + + + CEH + CE hold time + 4 + 4 + read-write + + + WEL + WE# LOW time + 8 + 4 + read-write + + + WEH + WE# HIGH time + 12 + 4 + read-write + + + REL + RE# LOW time + 16 + 4 + read-write + + + REH + RE# HIGH time + 20 + 4 + read-write + + + TA + Turnaround time + 24 + 4 + read-write + + + CEITV + CE# interval time + 28 + 4 + read-write + + + + + NANDCR2 + NAND control register 2 + 0x58 + 32 + read-write + 0x10410 + 0xFFFFFFFF + + + TWHR + WE# HIGH to RE# LOW wait time + 0 + 6 + read-write + + + TRHW + RE# HIGH to WE# LOW wait time + 6 + 6 + read-write + + + TADL + ALE to WRITE Data start wait time + 12 + 6 + read-write + + + TRR + Ready to RE# LOW min wait time + 18 + 6 + read-write + + + TWB + WE# HIGH to busy wait time + 24 + 6 + read-write + + + + + NANDCR3 + NAND control register 3 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + NDOPT1 + NAND option bit 1 + 0 + 1 + read-write + + + NDOPT2 + NAND option bit 2 + 1 + 1 + read-write + + + NDOPT3 + NAND option bit 3 + 2 + 1 + read-write + + + + + NORCR0 + NOR control register 0 + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + AM + Address Mode + 8 + 2 + read-write + + + AM_0 + Address/Data MUX mode + 0 + + + AM_1 + Advanced Address/Data MUX mode + 0x1 + + + AM_2 + Address/Data non-MUX mode + 0x2 + + + AM_3 + Address/Data non-MUX mode + 0x3 + + + + + ADVP + ADV# polarity + 10 + 1 + read-write + + + ADVP_0 + ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + 0 + + + ADVP_1 + ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + 0x1 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + NORCR1 + NOR control register 1 + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time cycle + 0 + 4 + read-write + + + CEH + CE hold min time (CEH+1) cycle + 4 + 4 + read-write + + + AS + Address setup time + 8 + 4 + read-write + + + AH + Address hold time + 12 + 4 + read-write + + + WEL + WE LOW time (WEL+1) cycle + 16 + 4 + read-write + + + WEH + WE HIGH time (WEH+1) cycle + 20 + 4 + read-write + + + REL + RE LOW time (REL+1) cycle + 24 + 4 + read-write + + + REH + RE HIGH time (REH+1) cycle + 28 + 4 + read-write + + + + + NORCR2 + NOR control register 2 + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDS + Write Data setup time (WDS+1) cycle + 0 + 4 + read-write + + + WDH + Write Data hold time (WDH+1) cycle + 4 + 4 + read-write + + + TA + Turnaround time cycle + 8 + 4 + read-write + + + AWDH + Address to write data hold time cycle + 12 + 4 + read-write + + + LC + Latency count + 16 + 4 + read-write + + + RD + Read cycle time + 20 + 4 + read-write + + + CEITV + CE# interval min time + 24 + 4 + read-write + + + + + NORCR3 + NOR control register 3 + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + SRAMCR0 + SRAM control register 0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + AM + Address Mode + 8 + 2 + read-write + + + AM_0 + Address/Data MUX mode + 0 + + + AM_1 + Advanced Address/Data MUX mode + 0x1 + + + AM_2 + Address/Data non-MUX mode + 0x2 + + + AM_3 + Address/Data non-MUX mode + 0x3 + + + + + ADVP + ADV# polarity + 10 + 1 + read-write + + + ADVP_0 + ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + 0 + + + ADVP_1 + ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + 0x1 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + SRAMCR1 + SRAM control register 1 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time cycle + 0 + 4 + read-write + + + CEH + CE hold min time (CEH+1) cycle + 4 + 4 + read-write + + + AS + Address setup time + 8 + 4 + read-write + + + AH + Address hold time + 12 + 4 + read-write + + + WEL + WE LOW time (WEL+1) cycle + 16 + 4 + read-write + + + WEH + WE HIGH time (WEH+1) cycle + 20 + 4 + read-write + + + REL + RE LOW time (REL+1) cycle + 24 + 4 + read-write + + + REH + RE HIGH time (REH+1) cycle + 28 + 4 + read-write + + + + + SRAMCR2 + SRAM control register 2 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDS + Write Data setup time (WDS+1) cycle + 0 + 4 + read-write + + + WDH + Write Data hold time (WDH+1) cycle + 4 + 4 + read-write + + + TA + Turnaround time cycle + 8 + 4 + read-write + + + AWDH + Address to write data hold time cycle + 12 + 4 + read-write + + + LC + Latency count + 16 + 4 + read-write + + + RD + Read cycle time + 20 + 4 + read-write + + + CEITV + CE# interval min time + 24 + 4 + read-write + + + + + SRAMCR3 + SRAM control register 3 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DBICR0 + DBI-B control register 0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + DBICR1 + DBI-B control register 1 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CSX Setup Time + 0 + 4 + read-write + + + CEH + CSX Hold Time + 4 + 4 + read-write + + + WEL + WRX Low Time + 8 + 4 + read-write + + + WEH + WRX High Time + 12 + 4 + read-write + + + REL + RDX Low Time bit [3:0] + 16 + 4 + read-write + + + REH + RDX High Time bit [3:0] + 20 + 4 + read-write + + + CEITV + CSX interval min time + 24 + 4 + read-write + + + REL2 + RDX Low Time bit [5:4] + 28 + 2 + read-write + + + REH2 + RDX High Time bit [5:4] + 30 + 2 + read-write + + + + + IPCR0 + IP Command control register 0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + IPCR1 + IP Command control register 1 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATSZ + Data Size in Byte + 0 + 3 + read-write + + + DATSZ_0 + 4 + 0 + + + DATSZ_1 + 1 + 0x1 + + + DATSZ_2 + 2 + 0x2 + + + DATSZ_3 + 3 + 0x3 + + + DATSZ_4 + 4 + 0x4 + + + DATSZ_5 + 4 + 0x5 + + + DATSZ_6 + 4 + 0x6 + + + DATSZ_7 + 4 + 0x7 + + + + + + + IPCR2 + IP Command control register 2 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) + 0 + 1 + read-write + + + BM0_0 + Byte Unmasked + 0 + + + BM0_1 + Byte Masked + 0x1 + + + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) + 1 + 1 + read-write + + + BM1_0 + Byte Unmasked + 0 + + + BM1_1 + Byte Masked + 0x1 + + + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) + 2 + 1 + read-write + + + BM2_0 + Byte Unmasked + 0 + + + BM2_1 + Byte Masked + 0x1 + + + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) + 3 + 1 + read-write + + + BM3_0 + Byte Unmasked + 0 + + + BM3_1 + Byte Masked + 0x1 + + + + + + + IPCMD + IP Command register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD + SDRAM Commands: 0x8: READ 0x9: WRITE 0xA: MODESET 0xB: ACTIVE 0xC: AUTO REFRESH 0xD: SELF REFRESH 0xE: PRECHARGE 0xF: PRECHARGE ALL Others: RSVD SELF REFRESH will be sent to all SDRAM devices because they shared same SEMC_CLK pin + 0 + 16 + read-write + + + KEY + This field should be written with 0xA55A when trigging an IP command. + 16 + 16 + write-only + + + + + IPTXDAT + TX DATA register (for IP Command) + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAT + no description available + 0 + 32 + read-write + + + + + IPRXDAT + RX DATA register (for IP Command) + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DAT + no description available + 0 + 32 + read-only + + + + + STS0 + Status register 0 + 0xC0 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + IDLE + Indicating whether SEMC is in IDLE state. + 0 + 1 + read-only + + + NARDY + Indicating NAND device Ready/WAIT# pin level. + 1 + 1 + read-only + + + NARDY_0 + NAND device is not ready + 0 + + + NARDY_1 + NAND device is ready + 0x1 + + + + + + + STS1 + Status register 1 + 0xC4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS2 + Status register 2 + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + NDWRPEND + This field indicating whether there is pending AXI command (write) to NAND device. + 3 + 1 + read-only + + + NDWRPEND_0 + No pending + 0 + + + NDWRPEND_1 + Pending + 0x1 + + + + + + + STS3 + Status register 3 + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS4 + Status register 4 + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS5 + Status register 5 + 0xD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS6 + Status register 6 + 0xD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS7 + Status register 7 + 0xDC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS8 + Status register 8 + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS9 + Status register 9 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS10 + Status register 10 + 0xE8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS11 + Status register 11 + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS12 + Status register 12 + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + NDADDR + This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). + 0 + 32 + read-only + + + + + STS13 + Status register 13 + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS14 + Status register 14 + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS15 + Status register 15 + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + + + DCP + DCP register reference index + DCP + DCP_ + 0x402FC000 + + 0 + 0x434 + registers + + + DCP + 50 + + + DCP_VMI + 51 + + + + CTRL + DCP control register 0 + 0 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + STAT + DCP status register + 0x10 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + CHANNELCTRL + DCP channel control register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CAPABILITY0 + DCP capability 0 register + 0x30 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + NUM_KEYS + Encoded value indicating the number of key-storage locations implemented in the design + 0 + 8 + read-only + + + NUM_CHANNELS + Encoded value indicating the number of channels implemented in the design + 8 + 4 + read-only + + + DISABLE_UNIQUE_KEY + Write to a 1 to disable the per-device unique key + 29 + 1 + read-write + + + DISABLE_DECRYPT + Write to 1 to disable the decryption + 31 + 1 + read-write + + + + + CAPABILITY1 + DCP capability 1 register + 0x40 + 32 + read-only + 0x70001 + 0xFFFFFFFF + + + CIPHER_ALGORITHMS + One-hot field indicating which cipher algorithms are available + 0 + 16 + read-only + + + AES128 + AES128 + 0x1 + + + + + HASH_ALGORITHMS + One-hot field indicating which hashing features are implemented in the hardware + 16 + 16 + read-only + + + SHA1 + SHA1 + 0x1 + + + CRC32 + CRC32 + 0x2 + + + SHA256 + SHA256 + 0x4 + + + + + + + CONTEXT + DCP context buffer pointer + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Context pointer address + 0 + 32 + read-write + + + + + KEY + DCP key index + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBWORD + Key subword pointer + 0 + 2 + read-write + + + INDEX + Key index pointer. The valid indices are 0-[number_keys]. + 4 + 2 + read-write + + + + + KEYDATA + DCP key data + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Word 0 data for the key. This is the least-significant word. + 0 + 32 + read-write + + + + + PACKET0 + DCP work packet 0 status register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Next pointer register + 0 + 32 + read-only + + + + + PACKET1 + DCP work packet 1 status register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTERRUPT + Reflects whether the channel must issue an interrupt upon the completion of the packet. + 0 + 1 + read-only + + + DECR_SEMAPHORE + Reflects whether the channel's semaphore must be decremented at the end of the current operation + 1 + 1 + read-only + + + CHAIN + Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer + 2 + 1 + read-only + + + CHAIN_CONTIGUOUS + Reflects whether the next packet's address is located following this packet's payload. + 3 + 1 + read-only + + + ENABLE_MEMCOPY + Reflects whether the selected hashing function should be enabled for this operation. + 4 + 1 + read-only + + + ENABLE_CIPHER + Reflects whether the selected cipher function must be enabled for this operation. + 5 + 1 + read-only + + + ENABLE_HASH + Reflects whether the selected hashing function must be enabled for this operation. + 6 + 1 + read-only + + + ENABLE_BLIT + Reflects whether the DCP must perform a blit operation + 7 + 1 + read-only + + + CIPHER_ENCRYPT + When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption + 8 + 1 + read-only + + + DECRYPT + DECRYPT + 0 + + + ENCRYPT + ENCRYPT + 0x1 + + + + + CIPHER_INIT + Reflects whether the cipher block must load the initialization vector from the payload for this operation + 9 + 1 + read-only + + + OTP_KEY + Reflects whether a hardware-based key must be used + 10 + 1 + read-only + + + PAYLOAD_KEY + When set, it indicates the payload contains the key + 11 + 1 + read-only + + + HASH_INIT + Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation + 12 + 1 + read-only + + + HASH_TERM + Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware + 13 + 1 + read-only + + + CHECK_HASH + Reflects whether the calculated hash value must be compared to the hash provided in the payload. + 14 + 1 + read-only + + + HASH_OUTPUT + When the hashing is enabled, this bit controls whether the input or output data is hashed. + 15 + 1 + read-only + + + INPUT + INPUT + 0 + + + OUTPUT + OUTPUT + 0x1 + + + + + CONSTANT_FILL + When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field + 16 + 1 + read-only + + + TEST_SEMA_IRQ + This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! + 17 + 1 + read-only + + + KEY_BYTESWAP + Reflects whether the DCP engine swaps the key bytes (big-endian key). + 18 + 1 + read-only + + + KEY_WORDSWAP + Reflects whether the DCP engine swaps the key words (big-endian key). + 19 + 1 + read-only + + + INPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the input data (big-endian data). + 20 + 1 + read-only + + + INPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the input data (big-endian data). + 21 + 1 + read-only + + + OUTPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the output data (big-endian data). + 22 + 1 + read-only + + + OUTPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the output data (big-endian data). + 23 + 1 + read-only + + + TAG + Packet Tag + 24 + 8 + read-only + + + + + PACKET2 + DCP work packet 2 status register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIPHER_SELECT + Cipher selection field + 0 + 4 + read-only + + + AES128 + AES128 + 0 + + + + + CIPHER_MODE + Cipher mode selection field. Reflects the mode of operation for the cipher operations. + 4 + 4 + read-only + + + ECB + ECB + 0 + + + CBC + CBC + 0x1 + + + + + KEY_SELECT + Key selection field + 8 + 8 + read-only + + + KEY0 + KEY0 + 0 + + + KEY1 + KEY1 + 0x1 + + + KEY2 + KEY2 + 0x2 + + + KEY3 + KEY3 + 0x3 + + + UNIQUE_KEY + UNIQUE_KEY + 0xFE + + + OTP_KEY + OTP_KEY + 0xFF + + + + + HASH_SELECT + Hash Selection Field + 16 + 4 + read-only + + + SHA1 + SHA1 + 0 + + + CRC32 + CRC32 + 0x1 + + + SHA256 + SHA256 + 0x2 + + + + + CIPHER_CFG + Cipher configuration bits. Optional configuration bits are required for the ciphers. + 24 + 8 + read-only + + + + + PACKET3 + DCP work packet 3 status register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Source buffer address pointer + 0 + 32 + read-only + + + + + PACKET4 + DCP work packet 4 status register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Destination buffer address pointer + 0 + 32 + read-only + + + + + PACKET5 + DCP work packet 5 status register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Byte count register. This value is the working value and updates as the operation proceeds. + 0 + 32 + read-only + + + + + PACKET6 + DCP work packet 6 status register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + This regiser reflects the payload pointer for the current control packet. + 0 + 32 + read-only + + + + + CH0CMDPTR + DCP channel 0 command pointer address register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 0. + 0 + 32 + read-write + + + + + CH0SEMA + DCP channel 0 semaphore register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH0STAT + DCP channel 0 status register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0OPTS + DCP channel 0 options register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1CMDPTR + DCP channel 1 command pointer address register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 1. + 0 + 32 + read-write + + + + + CH1SEMA + DCP channel 1 semaphore register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH1STAT + DCP channel 1 status register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1OPTS + DCP channel 1 options register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2CMDPTR + DCP channel 2 command pointer address register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 2. + 0 + 32 + read-write + + + + + CH2SEMA + DCP channel 2 semaphore register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH2STAT + DCP channel 2 status register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2OPTS + DCP channel 2 options register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3CMDPTR + DCP channel 3 command pointer address register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 3. + 0 + 32 + read-write + + + + + CH3SEMA + DCP channel 3 semaphore register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH3STAT + DCP channel 3 status register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3OPTS + DCP channel 3 options register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + DBGSELECT + DCP debug select register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + INDEX + Selects a value to read via the debug data register. + 0 + 8 + read-write + + + CONTROL + CONTROL + 0x1 + + + OTPKEY0 + OTPKEY0 + 0x10 + + + OTPKEY1 + OTPKEY1 + 0x11 + + + OTPKEY2 + OTPKEY2 + 0x12 + + + OTPKEY3 + OTPKEY3 + 0x13 + + + + + + + DBGDATA + DCP debug data register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Debug data + 0 + 32 + read-only + + + + + PAGETABLE + DCP page table register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Page table enable control + 0 + 1 + read-write + + + FLUSH + Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. + 1 + 1 + read-write + + + BASE + Page table base address + 2 + 30 + read-write + + + + + VERSION + DCP version register + 0x430 + 32 + read-only + 0x2010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the version of the design implementation. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR version of the design implementation. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR version of the design implementation. + 24 + 8 + read-only + + + + + + + SPDIF + SPDIF + SPDIF + SPDIF_ + 0x40380000 + + 0 + 0x54 + registers + + + SPDIF + 60 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 10 + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 12 + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 13 + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 15 + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 17 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 18 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 19 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 21 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 22 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 23 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. + 7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 8 + 3 + read-write + + + TxClk_Source_0 + REF_CLK_32K input (XTALOSC 32 kHz clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_3 + SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 11 + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + SAI1 + I2S + I2S + I2S + 0x40384000 + + 0 + 0xE4 + registers + + + SAI1 + 56 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard feature set. + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x50504 + 0xFFFFFFFF + + + DATALINE + Number of Datalines + 0 + 4 + read-only + + + FIFO + FIFO Size + 8 + 4 + read-only + + + FRAME + Frame Size + 16 + 4 + read-only + + + + + TCSR + SAI Transmit Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 31 + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + write-only + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + CHMOD + Channel Mode + 5 + 1 + read-write + + + CHMOD_0 + TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + 0 + + + CHMOD_1 + Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO reads (from transmit shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO writes (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + TDR[%s] + SAI Transmit Data Register + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + write-only + + + + + 4 + 0x4 + TFR[%s] + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + WCP + Write Channel Pointer + 31 + 1 + read-only + + + WCP_0 + No effect. + 0 + + + WCP_1 + FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + 0x1 + + + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 31 + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + write-only + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame Size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO writes (from receive shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO reads (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + RDR[%s] + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + 4 + 0x4 + RFR[%s] + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + RCP + Receive Channel Pointer + 15 + 1 + read-only + + + RCP_0 + No effect. + 0 + + + RCP_1 + FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + 0x1 + + + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + SAI2 + I2S + I2S + 0x40388000 + + 0 + 0xE4 + registers + + + SAI2 + 57 + + + + SAI3 + I2S + I2S + 0x4038C000 + + 0 + 0xE4 + registers + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + + LPSPI1 + LPSPI + LPSPI + LPSPI + 0x40394000 + + 0 + 0x78 + registers + + + LPSPI1 + 32 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1020004 + 0xFFFFFFFF + + + FEATURE + Module Identification Number + 0 + 16 + read-only + + + FEATURE_4 + Standard feature set supporting a 32-bit shift register. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x40404 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + PCSNUM + PCS Number + 16 + 8 + read-only + + + + + CR + Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Module Enable + 0 + 1 + read-write + + + MEN_0 + Module is disabled + 0 + + + MEN_1 + Module is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Module is not reset + 0 + + + RST_1 + Module is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Module is enabled in Doze mode + 0 + + + DOZEN_1 + Module is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Module is disabled in debug mode + 0 + + + DBGEN_1 + Module is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + SR + Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + WCF + Word Complete Flag + 8 + 1 + read-write + oneToClear + + + WCF_0 + Transfer of a received word has not yet completed + 0 + + + WCF_1 + Transfer of a received word has completed + 0x1 + + + + + FCF + Frame Complete Flag + 9 + 1 + read-write + oneToClear + + + FCF_0 + Frame transfer has not completed + 0 + + + FCF_1 + Frame transfer has completed + 0x1 + + + + + TCF + Transfer Complete Flag + 10 + 1 + read-write + oneToClear + + + TCF_0 + All transfers have not completed + 0 + + + TCF_1 + All transfers have completed + 0x1 + + + + + TEF + Transmit Error Flag + 11 + 1 + read-write + oneToClear + + + TEF_0 + Transmit FIFO underrun has not occurred + 0 + + + TEF_1 + Transmit FIFO underrun has occurred + 0x1 + + + + + REF + Receive Error Flag + 12 + 1 + read-write + oneToClear + + + REF_0 + Receive FIFO has not overflowed + 0 + + + REF_1 + Receive FIFO has overflowed + 0x1 + + + + + DMF + Data Match Flag + 13 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Module Busy Flag + 24 + 1 + read-only + + + MBF_0 + LPSPI is idle + 0 + + + MBF_1 + LPSPI is busy + 0x1 + + + + + + + IER + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + WCIE + Word Complete Interrupt Enable + 8 + 1 + read-write + + + WCIE_0 + Disabled + 0 + + + WCIE_1 + Enabled + 0x1 + + + + + FCIE + Frame Complete Interrupt Enable + 9 + 1 + read-write + + + FCIE_0 + Disabled + 0 + + + FCIE_1 + Enabled + 0x1 + + + + + TCIE + Transfer Complete Interrupt Enable + 10 + 1 + read-write + + + TCIE_0 + Disabled + 0 + + + TCIE_1 + Enabled + 0x1 + + + + + TEIE + Transmit Error Interrupt Enable + 11 + 1 + read-write + + + TEIE_0 + Disabled + 0 + + + TEIE_1 + Enabled + 0x1 + + + + + REIE + Receive Error Interrupt Enable + 12 + 1 + read-write + + + REIE_0 + Disabled + 0 + + + REIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 13 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + DER + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + CFGR0 + Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request is disabled + 0 + + + HREN_1 + Host request is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is the LPSPI_HREQ pin + 0 + + + HRSEL_1 + Host request input is the input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO as in normal operations + 0 + + + RDMO_1 + Received data is discarded unless the Data Match Flag (DMF) is set + 0x1 + + + + + + + CFGR1 + Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER + Master Mode + 0 + 1 + read-write + + + MASTER_0 + Slave mode + 0 + + + MASTER_1 + Master mode + 0x1 + + + + + SAMPLE + Sample Point + 1 + 1 + read-write + + + SAMPLE_0 + Input data is sampled on SCK edge + 0 + + + SAMPLE_1 + Input data is sampled on delayed SCK edge + 0x1 + + + + + AUTOPCS + Automatic PCS + 2 + 1 + read-write + + + AUTOPCS_0 + Automatic PCS generation is disabled + 0 + + + AUTOPCS_1 + Automatic PCS generation is enabled + 0x1 + + + + + NOSTALL + No Stall + 3 + 1 + read-write + + + NOSTALL_0 + Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + 0 + + + NOSTALL_1 + Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + 0x1 + + + + + PCSPOL + Peripheral Chip Select Polarity + 8 + 4 + read-write + + + PCSPOL_0 + The Peripheral Chip Select pin PCSx is active low + 0 + + + PCSPOL_1 + The Peripheral Chip Select pin PCSx is active high + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + 0x2 + + + MATCFG_3 + 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + 0x3 + + + MATCFG_4 + 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + 0x4 + + + MATCFG_5 + 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + 0x5 + + + MATCFG_6 + 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + 0x6 + + + MATCFG_7 + 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 2 + read-write + + + PINCFG_0 + SIN is used for input data and SOUT is used for output data + 0 + + + PINCFG_1 + SIN is used for both input and output data + 0x1 + + + PINCFG_2 + SOUT is used for both input and output data + 0x2 + + + PINCFG_3 + SOUT is used for input data and SIN is used for output data + 0x3 + + + + + OUTCFG + Output Config + 26 + 1 + read-write + + + OUTCFG_0 + Output data retains last value when chip select is negated + 0 + + + OUTCFG_1 + Output data is tristated when chip select is negated + 0x1 + + + + + PCSCFG + Peripheral Chip Select Configuration + 27 + 1 + read-write + + + PCSCFG_0 + PCS[3:2] are enabled + 0 + + + PCSCFG_1 + PCS[3:2] are disabled + 0x1 + + + + + + + DMR0 + Data Match Register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 32 + read-write + + + + + DMR1 + Data Match Register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH1 + Match 1 Value + 0 + 32 + read-write + + + + + CCR + Clock Configuration Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCKDIV + SCK Divider + 0 + 8 + read-write + + + DBT + Delay Between Transfers + 8 + 8 + read-write + + + PCSSCK + PCS-to-SCK Delay + 16 + 8 + read-write + + + SCKPCS + SCK-to-PCS Delay + 24 + 8 + read-write + + + + + FCR + FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 4 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 4 + read-write + + + + + FSR + FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 5 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 5 + read-only + + + + + TCR + Transmit Command Register + 0x60 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + FRAMESZ + Frame Size + 0 + 12 + read-write + + + WIDTH + Transfer Width + 16 + 2 + read-write + + + WIDTH_0 + 1 bit transfer + 0 + + + WIDTH_1 + 2 bit transfer + 0x1 + + + WIDTH_2 + 4 bit transfer + 0x2 + + + + + TXMSK + Transmit Data Mask + 18 + 1 + read-write + + + TXMSK_0 + Normal transfer + 0 + + + TXMSK_1 + Mask transmit data + 0x1 + + + + + RXMSK + Receive Data Mask + 19 + 1 + read-write + + + RXMSK_0 + Normal transfer + 0 + + + RXMSK_1 + Receive data is masked + 0x1 + + + + + CONTC + Continuing Command + 20 + 1 + read-write + + + CONTC_0 + Command word for start of new transfer + 0 + + + CONTC_1 + Command word for continuing transfer + 0x1 + + + + + CONT + Continuous Transfer + 21 + 1 + read-write + + + CONT_0 + Continuous transfer is disabled + 0 + + + CONT_1 + Continuous transfer is enabled + 0x1 + + + + + BYSW + Byte Swap + 22 + 1 + read-write + + + BYSW_0 + Byte swap is disabled + 0 + + + BYSW_1 + Byte swap is enabled + 0x1 + + + + + LSBF + LSB First + 23 + 1 + read-write + + + LSBF_0 + Data is transferred MSB first + 0 + + + LSBF_1 + Data is transferred LSB first + 0x1 + + + + + PCS + Peripheral Chip Select + 24 + 2 + read-write + + + PCS_0 + Transfer using LPSPI_PCS[0] + 0 + + + PCS_1 + Transfer using LPSPI_PCS[1] + 0x1 + + + PCS_2 + Transfer using LPSPI_PCS[2] + 0x2 + + + PCS_3 + Transfer using LPSPI_PCS[3] + 0x3 + + + + + PRESCALE + Prescaler Value + 27 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + CPHA + Clock Phase + 30 + 1 + read-write + + + CPHA_0 + Data is captured on the leading edge of SCK and changed on the following edge of SCK + 0 + + + CPHA_1 + Data is changed on the leading edge of SCK and captured on the following edge of SCK + 0x1 + + + + + CPOL + Clock Polarity + 31 + 1 + read-write + + + CPOL_0 + The inactive state value of SCK is low + 0 + + + CPOL_1 + The inactive state value of SCK is high + 0x1 + + + + + + + TDR + Transmit Data Register + 0x64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 32 + write-only + + + + + RSR + Receive Status Register + 0x70 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + SOF + Start Of Frame + 0 + 1 + read-only + + + SOF_0 + Subsequent data word received after LPSPI_PCS assertion + 0 + + + SOF_1 + First data word received after LPSPI_PCS assertion + 0x1 + + + + + RXEMPTY + RX FIFO Empty + 1 + 1 + read-only + + + RXEMPTY_0 + RX FIFO is not empty + 0 + + + RXEMPTY_1 + RX FIFO is empty + 0x1 + + + + + + + RDR + Receive Data Register + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 32 + read-only + + + + + + + LPSPI2 + LPSPI + LPSPI + 0x40398000 + + 0 + 0x78 + registers + + + LPSPI2 + 33 + + + + LPSPI3 + LPSPI + LPSPI + 0x4039C000 + + 0 + 0x78 + registers + + + LPSPI3 + 34 + + + + LPSPI4 + LPSPI + LPSPI + 0x403A0000 + + 0 + 0x78 + registers + + + LPSPI4 + 35 + + + + ADC_ETC + ADC_ETC + ADC_ETC + 0x403B0000 + + 0 + 0x150 + registers + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + + CTRL + ADC_ETC Global Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + TRIG_ENABLE + TRIG enable register + 0 + 8 + read-write + + + EXT0_TRIG_ENABLE + TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger. + 8 + 1 + read-write + + + EXT0_TRIG_PRIORITY + External TSC0 trigger priority, 7 is Highest, 0 is lowest . + 9 + 3 + read-write + + + EXT1_TRIG_ENABLE + TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger. + 12 + 1 + read-write + + + EXT1_TRIG_PRIORITY + External TSC1 trigger priority, 7 is Highest, 0 is lowest . + 13 + 3 + read-write + + + PRE_DIVIDER + Pre-divider for trig delay and interval . + 16 + 8 + read-write + + + DMA_MODE_SEL + 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared + 29 + 1 + read-write + + + TSC_BYPASS + 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared. + 30 + 1 + read-write + + + SOFTRST + Software reset, high active. When write 1 ,all logical will be reset. + 31 + 1 + read-write + + + + + DONE0_1_IRQ + ETC DONE0 and DONE1 IRQ State Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE0 + TRIG0 done0 interrupt detection + 0 + 1 + read-write + + + TRIG1_DONE0 + TRIG1 done0 interrupt detection + 1 + 1 + read-write + + + TRIG2_DONE0 + TRIG2 done0 interrupt detection + 2 + 1 + read-write + + + TRIG3_DONE0 + TRIG3 done0 interrupt detection + 3 + 1 + read-write + + + TRIG4_DONE0 + TRIG4 done0 interrupt detection + 4 + 1 + read-write + + + TRIG5_DONE0 + TRIG5 done0 interrupt detection + 5 + 1 + read-write + + + TRIG6_DONE0 + TRIG6 done0 interrupt detection + 6 + 1 + read-write + + + TRIG7_DONE0 + TRIG7 done0 interrupt detection + 7 + 1 + read-write + + + TRIG0_DONE1 + TRIG0 done1 interrupt detection + 16 + 1 + read-write + + + TRIG1_DONE1 + TRIG1 done1 interrupt detection + 17 + 1 + read-write + + + TRIG2_DONE1 + TRIG2 done1 interrupt detection + 18 + 1 + read-write + + + TRIG3_DONE1 + TRIG3 done1 interrupt detection + 19 + 1 + read-write + + + TRIG4_DONE1 + TRIG4 done1 interrupt detection + 20 + 1 + read-write + + + TRIG5_DONE1 + TRIG5 done1 interrupt detection + 21 + 1 + read-write + + + TRIG6_DONE1 + TRIG6 done1 interrupt detection + 22 + 1 + read-write + + + TRIG7_DONE1 + TRIG7 done1 interrupt detection + 23 + 1 + read-write + + + + + DONE2_ERR_IRQ + ETC DONE_2 and DONE_ERR IRQ State Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE2 + TRIG0 done2 interrupt detection + 0 + 1 + read-write + + + TRIG1_DONE2 + TRIG1 done2 interrupt detection + 1 + 1 + read-write + + + TRIG2_DONE2 + TRIG2 done2 interrupt detection + 2 + 1 + read-write + + + TRIG3_DONE2 + TRIG3 done2 interrupt detection + 3 + 1 + read-write + + + TRIG4_DONE2 + TRIG4 done2 interrupt detection + 4 + 1 + read-write + + + TRIG5_DONE2 + TRIG5 done2 interrupt detection + 5 + 1 + read-write + + + TRIG6_DONE2 + TRIG6 done2 interrupt detection + 6 + 1 + read-write + + + TRIG7_DONE2 + TRIG7 done2 interrupt detection + 7 + 1 + read-write + + + TRIG0_ERR + TRIG0 error interrupt detection + 16 + 1 + read-write + + + TRIG1_ERR + TRIG1 error interrupt detection + 17 + 1 + read-write + + + TRIG2_ERR + TRIG2 error interrupt detection + 18 + 1 + read-write + + + TRIG3_ERR + TRIG3 error interrupt detection + 19 + 1 + read-write + + + TRIG4_ERR + TRIG4 error interrupt detection + 20 + 1 + read-write + + + TRIG5_ERR + TRIG5 error interrupt detection + 21 + 1 + read-write + + + TRIG6_ERR + TRIG6 error interrupt detection + 22 + 1 + read-write + + + TRIG7_ERR + TRIG7 error interrupt detection + 23 + 1 + read-write + + + + + DMA_CTRL + ETC DMA control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_ENABLE + When TRIG0 done enable DMA request + 0 + 1 + read-write + + + TRIG1_ENABLE + When TRIG1 done enable DMA request + 1 + 1 + read-write + + + TRIG2_ENABLE + When TRIG2 done enable DMA request + 2 + 1 + read-write + + + TRIG3_ENABLE + When TRIG3 done enable DMA request + 3 + 1 + read-write + + + TRIG4_ENABLE + When TRIG4 done enable DMA request + 4 + 1 + read-write + + + TRIG5_ENABLE + When TRIG5 done enable DMA request + 5 + 1 + read-write + + + TRIG6_ENABLE + When TRIG6 done enable DMA request + 6 + 1 + read-write + + + TRIG7_ENABLE + When TRIG7 done enable DMA request + 7 + 1 + read-write + + + TRIG0_REQ + When TRIG0 done DMA request detection + 16 + 1 + read-write + + + TRIG1_REQ + When TRIG1 done DMA request detection + 17 + 1 + read-write + + + TRIG2_REQ + When TRIG2 done DMA request detection + 18 + 1 + read-write + + + TRIG3_REQ + When TRIG3 done DMA request detection + 19 + 1 + read-write + + + TRIG4_REQ + When TRIG4 done DMA request detection + 20 + 1 + read-write + + + TRIG5_REQ + When TRIG5 done DMA request detection + 21 + 1 + read-write + + + TRIG6_REQ + When TRIG6 done DMA request detection + 22 + 1 + read-write + + + TRIG7_REQ + When TRIG7 done DMA request detection + 23 + 1 + read-write + + + + + TRIG0_CTRL + ETC_TRIG0 Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG0_COUNTER + ETC_TRIG0 Counter Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG0_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG0_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG0_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG0_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG0_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG0_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG0_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG0_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG1_CTRL + ETC_TRIG1 Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG1_COUNTER + ETC_TRIG1 Counter Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG1_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG1_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG1_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG1_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG1_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG1_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG1_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG1_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG2_CTRL + ETC_TRIG2 Control Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG2_COUNTER + ETC_TRIG2 Counter Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG2_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG2_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG2_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG2_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG2_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG2_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG2_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG2_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG3_CTRL + ETC_TRIG3 Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG3_COUNTER + ETC_TRIG3 Counter Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG3_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG3_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG3_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG3_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG3_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG3_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG3_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xA8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG3_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG4_CTRL + ETC_TRIG4 Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG4_COUNTER + ETC_TRIG4 Counter Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG4_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG4_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG4_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG4_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG4_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG4_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG4_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG4_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG5_CTRL + ETC_TRIG5 Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG5_COUNTER + ETC_TRIG5 Counter Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG5_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG5_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG5_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG5_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG5_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG5_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG5_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG5_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG6_CTRL + ETC_TRIG6 Control Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG6_COUNTER + ETC_TRIG6 Counter Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG6_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG6_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG6_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG6_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG6_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x118 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG6_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG6_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG6_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG7_CTRL + ETC_TRIG7 Control Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG7_COUNTER + ETC_TRIG7 Counter Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG7_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG7_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG7_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG7_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG7_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG7_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG7_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG7_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + + + AOI1 + AND/OR/INVERT module + AOI + AOI1_ + AOI + 0x403B4000 + + 0 + 0x10 + registers + + + + 4 + 0x4 + 0,1,2,3 + BFCRT01%s + Boolean Function Term 0 and 1 Configuration Register for EVENTn + 0 + 16 + read-write + 0 + 0xFFFF + + + PT1_DC + Product term 1, D input configuration + 0 + 2 + read-write + + + PT1_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT1_DC_1 + Pass the D input in this product term + 0x1 + + + PT1_DC_2 + Complement the D input in this product term + 0x2 + + + PT1_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT1_CC + Product term 1, C input configuration + 2 + 2 + read-write + + + PT1_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT1_CC_1 + Pass the C input in this product term + 0x1 + + + PT1_CC_2 + Complement the C input in this product term + 0x2 + + + PT1_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT1_BC + Product term 1, B input configuration + 4 + 2 + read-write + + + PT1_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT1_BC_1 + Pass the B input in this product term + 0x1 + + + PT1_BC_2 + Complement the B input in this product term + 0x2 + + + PT1_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT1_AC + Product term 1, A input configuration + 6 + 2 + read-write + + + PT1_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT1_AC_1 + Pass the A input in this product term + 0x1 + + + PT1_AC_2 + Complement the A input in this product term + 0x2 + + + PT1_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT0_DC + Product term 0, D input configuration + 8 + 2 + read-write + + + PT0_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT0_DC_1 + Pass the D input in this product term + 0x1 + + + PT0_DC_2 + Complement the D input in this product term + 0x2 + + + PT0_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT0_CC + Product term 0, C input configuration + 10 + 2 + read-write + + + PT0_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT0_CC_1 + Pass the C input in this product term + 0x1 + + + PT0_CC_2 + Complement the C input in this product term + 0x2 + + + PT0_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT0_BC + Product term 0, B input configuration + 12 + 2 + read-write + + + PT0_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT0_BC_1 + Pass the B input in this product term + 0x1 + + + PT0_BC_2 + Complement the B input in this product term + 0x2 + + + PT0_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT0_AC + Product term 0, A input configuration + 14 + 2 + read-write + + + PT0_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT0_AC_1 + Pass the A input in this product term + 0x1 + + + PT0_AC_2 + Complement the A input in this product term + 0x2 + + + PT0_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + 4 + 0x4 + 0,1,2,3 + BFCRT23%s + Boolean Function Term 2 and 3 Configuration Register for EVENTn + 0x2 + 16 + read-write + 0 + 0xFFFF + + + PT3_DC + Product term 3, D input configuration + 0 + 2 + read-write + + + PT3_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT3_DC_1 + Pass the D input in this product term + 0x1 + + + PT3_DC_2 + Complement the D input in this product term + 0x2 + + + PT3_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT3_CC + Product term 3, C input configuration + 2 + 2 + read-write + + + PT3_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT3_CC_1 + Pass the C input in this product term + 0x1 + + + PT3_CC_2 + Complement the C input in this product term + 0x2 + + + PT3_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT3_BC + Product term 3, B input configuration + 4 + 2 + read-write + + + PT3_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT3_BC_1 + Pass the B input in this product term + 0x1 + + + PT3_BC_2 + Complement the B input in this product term + 0x2 + + + PT3_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT3_AC + Product term 3, A input configuration + 6 + 2 + read-write + + + PT3_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT3_AC_1 + Pass the A input in this product term + 0x1 + + + PT3_AC_2 + Complement the A input in this product term + 0x2 + + + PT3_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT2_DC + Product term 2, D input configuration + 8 + 2 + read-write + + + PT2_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT2_DC_1 + Pass the D input in this product term + 0x1 + + + PT2_DC_2 + Complement the D input in this product term + 0x2 + + + PT2_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT2_CC + Product term 2, C input configuration + 10 + 2 + read-write + + + PT2_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT2_CC_1 + Pass the C input in this product term + 0x1 + + + PT2_CC_2 + Complement the C input in this product term + 0x2 + + + PT2_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT2_BC + Product term 2, B input configuration + 12 + 2 + read-write + + + PT2_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT2_BC_1 + Pass the B input in this product term + 0x1 + + + PT2_BC_2 + Complement the B input in this product term + 0x2 + + + PT2_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT2_AC + Product term 2, A input configuration + 14 + 2 + read-write + + + PT2_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT2_AC_1 + Pass the A input in this product term + 0x1 + + + PT2_AC_2 + Complement the A input in this product term + 0x2 + + + PT2_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + + + AOI2 + AND/OR/INVERT module + AOI + AOI2_ + 0x403B8000 + + 0 + 0x10 + registers + + + + XBARA1 + Crossbar Switch + XBARA + XBARA1_ + 0x403BC000 + + 0 + 0x88 + registers + + + + SEL0 + Crossbar A Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL1 + Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL1 + Crossbar A Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL3 + Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL2 + Crossbar A Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL5 + Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL3 + Crossbar A Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL7 + Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL4 + Crossbar A Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL9 + Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL5 + Crossbar A Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL11 + Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL6 + Crossbar A Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL13 + Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL7 + Crossbar A Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL15 + Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL8 + Crossbar A Select Register 8 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + SEL16 + Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL17 + Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL9 + Crossbar A Select Register 9 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + SEL18 + Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL19 + Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL10 + Crossbar A Select Register 10 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + SEL20 + Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL21 + Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL11 + Crossbar A Select Register 11 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + SEL22 + Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL23 + Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL12 + Crossbar A Select Register 12 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + SEL24 + Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL25 + Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL13 + Crossbar A Select Register 13 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + SEL26 + Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL27 + Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL14 + Crossbar A Select Register 14 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + SEL28 + Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL29 + Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL15 + Crossbar A Select Register 15 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + SEL30 + Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL31 + Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL16 + Crossbar A Select Register 16 + 0x20 + 16 + read-write + 0 + 0xFFFF + + + SEL32 + Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL33 + Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL17 + Crossbar A Select Register 17 + 0x22 + 16 + read-write + 0 + 0xFFFF + + + SEL34 + Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL35 + Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL18 + Crossbar A Select Register 18 + 0x24 + 16 + read-write + 0 + 0xFFFF + + + SEL36 + Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL37 + Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL19 + Crossbar A Select Register 19 + 0x26 + 16 + read-write + 0 + 0xFFFF + + + SEL38 + Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL39 + Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL20 + Crossbar A Select Register 20 + 0x28 + 16 + read-write + 0 + 0xFFFF + + + SEL40 + Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL41 + Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL21 + Crossbar A Select Register 21 + 0x2A + 16 + read-write + 0 + 0xFFFF + + + SEL42 + Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL43 + Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL22 + Crossbar A Select Register 22 + 0x2C + 16 + read-write + 0 + 0xFFFF + + + SEL44 + Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL45 + Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL23 + Crossbar A Select Register 23 + 0x2E + 16 + read-write + 0 + 0xFFFF + + + SEL46 + Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL47 + Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL24 + Crossbar A Select Register 24 + 0x30 + 16 + read-write + 0 + 0xFFFF + + + SEL48 + Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL49 + Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL25 + Crossbar A Select Register 25 + 0x32 + 16 + read-write + 0 + 0xFFFF + + + SEL50 + Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL51 + Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL26 + Crossbar A Select Register 26 + 0x34 + 16 + read-write + 0 + 0xFFFF + + + SEL52 + Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL53 + Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL27 + Crossbar A Select Register 27 + 0x36 + 16 + read-write + 0 + 0xFFFF + + + SEL54 + Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL55 + Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL28 + Crossbar A Select Register 28 + 0x38 + 16 + read-write + 0 + 0xFFFF + + + SEL56 + Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL57 + Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL29 + Crossbar A Select Register 29 + 0x3A + 16 + read-write + 0 + 0xFFFF + + + SEL58 + Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL59 + Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL30 + Crossbar A Select Register 30 + 0x3C + 16 + read-write + 0 + 0xFFFF + + + SEL60 + Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL61 + Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL31 + Crossbar A Select Register 31 + 0x3E + 16 + read-write + 0 + 0xFFFF + + + SEL62 + Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL63 + Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL32 + Crossbar A Select Register 32 + 0x40 + 16 + read-write + 0 + 0xFFFF + + + SEL64 + Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL65 + Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL33 + Crossbar A Select Register 33 + 0x42 + 16 + read-write + 0 + 0xFFFF + + + SEL66 + Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL67 + Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL34 + Crossbar A Select Register 34 + 0x44 + 16 + read-write + 0 + 0xFFFF + + + SEL68 + Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL69 + Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL35 + Crossbar A Select Register 35 + 0x46 + 16 + read-write + 0 + 0xFFFF + + + SEL70 + Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL71 + Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL36 + Crossbar A Select Register 36 + 0x48 + 16 + read-write + 0 + 0xFFFF + + + SEL72 + Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL73 + Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL37 + Crossbar A Select Register 37 + 0x4A + 16 + read-write + 0 + 0xFFFF + + + SEL74 + Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL75 + Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL38 + Crossbar A Select Register 38 + 0x4C + 16 + read-write + 0 + 0xFFFF + + + SEL76 + Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL77 + Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL39 + Crossbar A Select Register 39 + 0x4E + 16 + read-write + 0 + 0xFFFF + + + SEL78 + Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL79 + Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL40 + Crossbar A Select Register 40 + 0x50 + 16 + read-write + 0 + 0xFFFF + + + SEL80 + Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL81 + Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL41 + Crossbar A Select Register 41 + 0x52 + 16 + read-write + 0 + 0xFFFF + + + SEL82 + Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL83 + Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL42 + Crossbar A Select Register 42 + 0x54 + 16 + read-write + 0 + 0xFFFF + + + SEL84 + Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL85 + Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL43 + Crossbar A Select Register 43 + 0x56 + 16 + read-write + 0 + 0xFFFF + + + SEL86 + Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL87 + Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL44 + Crossbar A Select Register 44 + 0x58 + 16 + read-write + 0 + 0xFFFF + + + SEL88 + Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL89 + Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL45 + Crossbar A Select Register 45 + 0x5A + 16 + read-write + 0 + 0xFFFF + + + SEL90 + Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL91 + Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL46 + Crossbar A Select Register 46 + 0x5C + 16 + read-write + 0 + 0xFFFF + + + SEL92 + Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL93 + Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL47 + Crossbar A Select Register 47 + 0x5E + 16 + read-write + 0 + 0xFFFF + + + SEL94 + Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL95 + Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL48 + Crossbar A Select Register 48 + 0x60 + 16 + read-write + 0 + 0xFFFF + + + SEL96 + Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL97 + Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL49 + Crossbar A Select Register 49 + 0x62 + 16 + read-write + 0 + 0xFFFF + + + SEL98 + Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL99 + Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL50 + Crossbar A Select Register 50 + 0x64 + 16 + read-write + 0 + 0xFFFF + + + SEL100 + Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL101 + Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL51 + Crossbar A Select Register 51 + 0x66 + 16 + read-write + 0 + 0xFFFF + + + SEL102 + Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL103 + Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL52 + Crossbar A Select Register 52 + 0x68 + 16 + read-write + 0 + 0xFFFF + + + SEL104 + Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL105 + Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL53 + Crossbar A Select Register 53 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + SEL106 + Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL107 + Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL54 + Crossbar A Select Register 54 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + SEL108 + Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL109 + Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL55 + Crossbar A Select Register 55 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + SEL110 + Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL111 + Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL56 + Crossbar A Select Register 56 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + SEL112 + Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL113 + Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL57 + Crossbar A Select Register 57 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + SEL114 + Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL115 + Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL58 + Crossbar A Select Register 58 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + SEL116 + Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL117 + Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL59 + Crossbar A Select Register 59 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + SEL118 + Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL119 + Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL60 + Crossbar A Select Register 60 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + SEL120 + Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL121 + Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL61 + Crossbar A Select Register 61 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + SEL122 + Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL123 + Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL62 + Crossbar A Select Register 62 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + SEL124 + Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL125 + Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL63 + Crossbar A Select Register 63 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + SEL126 + Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL127 + Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL64 + Crossbar A Select Register 64 + 0x80 + 16 + read-write + 0 + 0xFFFF + + + SEL128 + Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL129 + Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL65 + Crossbar A Select Register 65 + 0x82 + 16 + read-write + 0 + 0xFFFF + + + SEL130 + Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL131 + Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + CTRL0 + Crossbar A Control Register 0 + 0x84 + 16 + read-write + 0 + 0xFFFF + + + DEN0 + DMA Enable for XBAR_OUT0 + 0 + 1 + read-write + + + DEN0_0 + DMA disabled + 0 + + + DEN0_1 + DMA enabled + 0x1 + + + + + IEN0 + Interrupt Enable for XBAR_OUT0 + 1 + 1 + read-write + + + IEN0_0 + Interrupt disabled + 0 + + + IEN0_1 + Interrupt enabled + 0x1 + + + + + EDGE0 + Active edge for edge detection on XBAR_OUT0 + 2 + 2 + read-write + + + EDGE0_0 + STS0 never asserts + 0 + + + EDGE0_1 + STS0 asserts on rising edges of XBAR_OUT0 + 0x1 + + + EDGE0_2 + STS0 asserts on falling edges of XBAR_OUT0 + 0x2 + + + EDGE0_3 + STS0 asserts on rising and falling edges of XBAR_OUT0 + 0x3 + + + + + STS0 + Edge detection status for XBAR_OUT0 + 4 + 1 + read-write + oneToClear + + + STS0_0 + Active edge not yet detected on XBAR_OUT0 + 0 + + + STS0_1 + Active edge detected on XBAR_OUT0 + 0x1 + + + + + DEN1 + DMA Enable for XBAR_OUT1 + 8 + 1 + read-write + + + DEN1_0 + DMA disabled + 0 + + + DEN1_1 + DMA enabled + 0x1 + + + + + IEN1 + Interrupt Enable for XBAR_OUT1 + 9 + 1 + read-write + + + IEN1_0 + Interrupt disabled + 0 + + + IEN1_1 + Interrupt enabled + 0x1 + + + + + EDGE1 + Active edge for edge detection on XBAR_OUT1 + 10 + 2 + read-write + + + EDGE1_0 + STS1 never asserts + 0 + + + EDGE1_1 + STS1 asserts on rising edges of XBAR_OUT1 + 0x1 + + + EDGE1_2 + STS1 asserts on falling edges of XBAR_OUT1 + 0x2 + + + EDGE1_3 + STS1 asserts on rising and falling edges of XBAR_OUT1 + 0x3 + + + + + STS1 + Edge detection status for XBAR_OUT1 + 12 + 1 + read-write + oneToClear + + + STS1_0 + Active edge not yet detected on XBAR_OUT1 + 0 + + + STS1_1 + Active edge detected on XBAR_OUT1 + 0x1 + + + + + + + CTRL1 + Crossbar A Control Register 1 + 0x86 + 16 + read-write + 0 + 0xFFFF + + + DEN2 + DMA Enable for XBAR_OUT2 + 0 + 1 + read-write + + + DEN2_0 + DMA disabled + 0 + + + DEN2_1 + DMA enabled + 0x1 + + + + + IEN2 + Interrupt Enable for XBAR_OUT2 + 1 + 1 + read-write + + + IEN2_0 + Interrupt disabled + 0 + + + IEN2_1 + Interrupt enabled + 0x1 + + + + + EDGE2 + Active edge for edge detection on XBAR_OUT2 + 2 + 2 + read-write + + + EDGE2_0 + STS2 never asserts + 0 + + + EDGE2_1 + STS2 asserts on rising edges of XBAR_OUT2 + 0x1 + + + EDGE2_2 + STS2 asserts on falling edges of XBAR_OUT2 + 0x2 + + + EDGE2_3 + STS2 asserts on rising and falling edges of XBAR_OUT2 + 0x3 + + + + + STS2 + Edge detection status for XBAR_OUT2 + 4 + 1 + read-write + oneToClear + + + STS2_0 + Active edge not yet detected on XBAR_OUT2 + 0 + + + STS2_1 + Active edge detected on XBAR_OUT2 + 0x1 + + + + + DEN3 + DMA Enable for XBAR_OUT3 + 8 + 1 + read-write + + + DEN3_0 + DMA disabled + 0 + + + DEN3_1 + DMA enabled + 0x1 + + + + + IEN3 + Interrupt Enable for XBAR_OUT3 + 9 + 1 + read-write + + + IEN3_0 + Interrupt disabled + 0 + + + IEN3_1 + Interrupt enabled + 0x1 + + + + + EDGE3 + Active edge for edge detection on XBAR_OUT3 + 10 + 2 + read-write + + + EDGE3_0 + STS3 never asserts + 0 + + + EDGE3_1 + STS3 asserts on rising edges of XBAR_OUT3 + 0x1 + + + EDGE3_2 + STS3 asserts on falling edges of XBAR_OUT3 + 0x2 + + + EDGE3_3 + STS3 asserts on rising and falling edges of XBAR_OUT3 + 0x3 + + + + + STS3 + Edge detection status for XBAR_OUT3 + 12 + 1 + read-write + oneToClear + + + STS3_0 + Active edge not yet detected on XBAR_OUT3 + 0 + + + STS3_1 + Active edge detected on XBAR_OUT3 + 0x1 + + + + + + + + + XBARB2 + Crossbar Switch + XBARA + XBARB2_ + XBARA + 0x403C0000 + + 0 + 0x10 + registers + + + + SEL0 + Crossbar B Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL1 + Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL1 + Crossbar B Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL3 + Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL2 + Crossbar B Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL5 + Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL3 + Crossbar B Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL7 + Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL4 + Crossbar B Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL9 + Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL5 + Crossbar B Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL11 + Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL6 + Crossbar B Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL13 + Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL7 + Crossbar B Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL15 + Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + + + XBARB3 + Crossbar Switch + XBARA + XBARB3_ + 0x403C4000 + + 0 + 0x10 + registers + + + + ENC1 + Quadrature Decoder + ENC + ENC1_ + ENC + 0x403C8000 + + 0 + 0x28 + registers + + + ENC1 + 129 + + + + CTRL + Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enable + 0 + 1 + read-write + + + CMPIE_0 + Compare interrupt is disabled + 0 + + + CMPIE_1 + Compare interrupt is enabled + 0x1 + + + + + CMPIRQ + Compare Interrupt Request + 1 + 1 + read-write + oneToClear + + + CMPIRQ_0 + No match has occurred + 0 + + + CMPIRQ_1 + COMP match has occurred + 0x1 + + + + + WDE + Watchdog Enable + 2 + 1 + read-write + + + WDE_0 + Watchdog timer is disabled + 0 + + + WDE_1 + Watchdog timer is enabled + 0x1 + + + + + DIE + Watchdog Timeout Interrupt Enable + 3 + 1 + read-write + + + DIE_0 + Watchdog timer interrupt is disabled + 0 + + + DIE_1 + Watchdog timer interrupt is enabled + 0x1 + + + + + DIRQ + Watchdog Timeout Interrupt Request + 4 + 1 + read-write + oneToClear + + + DIRQ_0 + No interrupt has occurred + 0 + + + DIRQ_1 + Watchdog timeout interrupt has occurred + 0x1 + + + + + XNE + Use Negative Edge of INDEX Pulse + 5 + 1 + read-write + + + XNE_0 + Use positive transition edge of INDEX pulse + 0 + + + XNE_1 + Use negative transition edge of INDEX pulse + 0x1 + + + + + XIP + INDEX Triggered Initialization of Position Counters UPOS and LPOS + 6 + 1 + read-write + + + XIP_0 + No action + 0 + + + XIP_1 + INDEX pulse initializes the position counter + 0x1 + + + + + XIE + INDEX Pulse Interrupt Enable + 7 + 1 + read-write + + + XIE_0 + INDEX pulse interrupt is disabled + 0 + + + XIE_1 + INDEX pulse interrupt is enabled + 0x1 + + + + + XIRQ + INDEX Pulse Interrupt Request + 8 + 1 + read-write + oneToClear + + + XIRQ_0 + No interrupt has occurred + 0 + + + XIRQ_1 + INDEX pulse interrupt has occurred + 0x1 + + + + + PH1 + Enable Signal Phase Count Mode + 9 + 1 + read-write + + + PH1_0 + Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + 0 + + + PH1_1 + Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up + 0x1 + + + + + REV + Enable Reverse Direction Counting + 10 + 1 + read-write + + + REV_0 + Count normally + 0 + + + REV_1 + Count in the reverse direction + 0x1 + + + + + SWIP + Software Triggered Initialization of Position Counters UPOS and LPOS + 11 + 1 + write-only + + + SWIP_0 + No action + 0 + + + SWIP_1 + Initialize position counter + 0x1 + + + + + HNE + Use Negative Edge of HOME Input + 12 + 1 + read-write + + + HNE_0 + Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + 0 + + + HNE_1 + Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + 0x1 + + + + + HIP + Enable HOME to Initialize Position Counters UPOS and LPOS + 13 + 1 + read-write + + + HIP_0 + No action + 0 + + + HIP_1 + HOME signal initializes the position counter + 0x1 + + + + + HIE + HOME Interrupt Enable + 14 + 1 + read-write + + + HIE_0 + Disable HOME interrupts + 0 + + + HIE_1 + Enable HOME interrupts + 0x1 + + + + + HIRQ + HOME Signal Transition Interrupt Request + 15 + 1 + read-write + oneToClear + + + HIRQ_0 + No interrupt + 0 + + + HIRQ_1 + HOME signal transition interrupt request + 0x1 + + + + + + + FILT + Input Filter Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + WTR + Watchdog Timeout Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + WDOG + WDOG[15:0] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt + 0 + 16 + read-write + + + + + POSD + Position Difference Counter Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + POSD + This read/write register contains the position change in value occurring between each read of the position register + 0 + 16 + read-write + + + + + POSDH + Position Difference Hold Register + 0x8 + 16 + read-only + 0 + 0xFFFF + + + POSDH + This read-only register contains a snapshot of the value of the POSD register + 0 + 16 + read-only + + + + + REV + Revolution Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + REV + This read/write register contains the current value of the revolution counter. + 0 + 16 + read-write + + + + + REVH + Revolution Hold Register + 0xC + 16 + read-only + 0 + 0xFFFF + + + REVH + This read-only register contains a snapshot of the value of the REV register. + 0 + 16 + read-only + + + + + UPOS + Upper Position Counter Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + POS + This read/write register contains the upper (most significant) half of the position counter + 0 + 16 + read-write + + + + + LPOS + Lower Position Counter Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + POS + This read/write register contains the lower (least significant) half of the position counter + 0 + 16 + read-write + + + + + UPOSH + Upper Position Hold Register + 0x12 + 16 + read-only + 0 + 0xFFFF + + + POSH + This read-only register contains a snapshot of the UPOS register. + 0 + 16 + read-only + + + + + LPOSH + Lower Position Hold Register + 0x14 + 16 + read-only + 0 + 0xFFFF + + + POSH + This read-only register contains a snapshot of the LPOS register. + 0 + 16 + read-only + + + + + UINIT + Upper Initialization Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + INIT + This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS) + 0 + 16 + read-write + + + + + LINIT + Lower Initialization Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + INIT + This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS) + 0 + 16 + read-write + + + + + IMR + Input Monitor Register + 0x1A + 16 + read-only + 0 + 0xFFFF + + + HOME + This is the raw HOME input. + 0 + 1 + read-only + + + INDEX + This is the raw INDEX input. + 1 + 1 + read-only + + + PHB + This is the raw PHASEB input. + 2 + 1 + read-only + + + PHA + This is the raw PHASEA input. + 3 + 1 + read-only + + + FHOM + This is the filtered version of HOME input. + 4 + 1 + read-only + + + FIND + This is the filtered version of INDEX input. + 5 + 1 + read-only + + + FPHB + This is the filtered version of PHASEB input. + 6 + 1 + read-only + + + FPHA + This is the filtered version of PHASEA input. + 7 + 1 + read-only + + + + + TST + Test Register + 0x1C + 16 + read-write + 0 + 0xFFFF + + + TEST_COUNT + These bits hold the number of quadrature advances to generate. + 0 + 8 + read-write + + + TEST_PERIOD + These bits hold the period of quadrature phase in IPBus clock cycles. + 8 + 5 + read-write + + + QDN + Quadrature Decoder Negative Signal + 13 + 1 + read-write + + + QDN_0 + Leaves quadrature decoder signal in a positive direction + 0 + + + QDN_1 + Generates a negative quadrature decoder signal + 0x1 + + + + + TCE + Test Counter Enable + 14 + 1 + read-write + + + TCE_0 + Test count is not enabled + 0 + + + TCE_1 + Test count is enabled + 0x1 + + + + + TEN + Test Mode Enable + 15 + 1 + read-write + + + TEN_0 + Test module is not enabled + 0 + + + TEN_1 + Test module is enabled + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x1E + 16 + read-write + 0 + 0xFFFF + + + UPDHLD + Update Hold Registers + 0 + 1 + read-write + + + UPDHLD_0 + Disable updates of hold registers on rising edge of TRIGGER + 0 + + + UPDHLD_1 + Enable updates of hold registers on rising edge of TRIGGER + 0x1 + + + + + UPDPOS + Update Position Registers + 1 + 1 + read-write + + + UPDPOS_0 + No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + 0 + + + UPDPOS_1 + Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + 0x1 + + + + + MOD + Enable Modulo Counting + 2 + 1 + read-write + + + MOD_0 + Disable modulo counting + 0 + + + MOD_1 + Enable modulo counting + 0x1 + + + + + DIR + Count Direction Flag + 3 + 1 + read-only + + + DIR_0 + Last count was in the down direction + 0 + + + DIR_1 + Last count was in the up direction + 0x1 + + + + + RUIE + Roll-under Interrupt Enable + 4 + 1 + read-write + + + RUIE_0 + Roll-under interrupt is disabled + 0 + + + RUIE_1 + Roll-under interrupt is enabled + 0x1 + + + + + RUIRQ + Roll-under Interrupt Request + 5 + 1 + read-write + oneToClear + + + RUIRQ_0 + No roll-under has occurred + 0 + + + RUIRQ_1 + Roll-under has occurred + 0x1 + + + + + ROIE + Roll-over Interrupt Enable + 6 + 1 + read-write + + + ROIE_0 + Roll-over interrupt is disabled + 0 + + + ROIE_1 + Roll-over interrupt is enabled + 0x1 + + + + + ROIRQ + Roll-over Interrupt Request + 7 + 1 + read-write + oneToClear + + + ROIRQ_0 + No roll-over has occurred + 0 + + + ROIRQ_1 + Roll-over has occurred + 0x1 + + + + + REVMOD + Revolution Counter Modulus Enable + 8 + 1 + read-write + + + REVMOD_0 + Use INDEX pulse to increment/decrement revolution counter (REV). + 0 + + + REVMOD_1 + Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + 0x1 + + + + + OUTCTL + Output Control + 9 + 1 + read-write + + + OUTCTL_0 + POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + 0 + + + OUTCTL_1 + POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + 0x1 + + + + + SABIE + Simultaneous PHASEA and PHASEB Change Interrupt Enable + 10 + 1 + read-write + + + SABIE_0 + Simultaneous PHASEA and PHASEB change interrupt disabled. + 0 + + + SABIE_1 + Simultaneous PHASEA and PHASEB change interrupt enabled. + 0x1 + + + + + SABIRQ + Simultaneous PHASEA and PHASEB Change Interrupt Request + 11 + 1 + read-write + oneToClear + + + SABIRQ_0 + No simultaneous change of PHASEA and PHASEB has occurred. + 0 + + + SABIRQ_1 + A simultaneous change of PHASEA and PHASEB has occurred. + 0x1 + + + + + + + UMOD + Upper Modulus Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + MOD + This read/write register contains the upper (most significant) half of the modulus register + 0 + 16 + read-write + + + + + LMOD + Lower Modulus Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + MOD + This read/write register contains the lower (least significant) half of the modulus register + 0 + 16 + read-write + + + + + UCOMP + Upper Position Compare Register + 0x24 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + This read/write register contains the upper (most significant) half of the position compare register + 0 + 16 + read-write + + + + + LCOMP + Lower Position Compare Register + 0x26 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + This read/write register contains the lower (least significant) half of the position compare register + 0 + 16 + read-write + + + + + + + ENC2 + Quadrature Decoder + ENC + ENC2_ + 0x403CC000 + + 0 + 0x28 + registers + + + ENC2 + 130 + + + + ENC3 + Quadrature Decoder + ENC + ENC3_ + 0x403D0000 + + 0 + 0x28 + registers + + + ENC3 + 131 + + + + ENC4 + Quadrature Decoder + ENC + ENC4_ + 0x403D4000 + + 0 + 0x28 + registers + + + ENC4 + 132 + + + + PWM1 + PWM + PWM + PWM + 0x403DC000 + + 0 + 0x196 + registers + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + + SM0CNT + Counter Register + 0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM0INIT + Initial Count Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM0CTRL2 + Control 2 Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + write-only + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM0CTRL + Control Register + 0x6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + no description available + 0 + + + PRSC_1 + no description available + 0x1 + + + PRSC_2 + no description available + 0x2 + + + PRSC_3 + no description available + 0x3 + + + PRSC_4 + no description available + 0x4 + + + PRSC_5 + no description available + 0x5 + + + PRSC_6 + no description available + 0x6 + + + PRSC_7 + no description available + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM0VAL0 + Value Register 0 + 0xA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM0FRACVAL1 + Fractional Value Register 1 + 0xC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM0VAL1 + Value Register 1 + 0xE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM0FRACVAL2 + Fractional Value Register 2 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM0VAL2 + Value Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM0FRACVAL3 + Fractional Value Register 3 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM0VAL3 + Value Register 3 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM0FRACVAL4 + Fractional Value Register 4 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM0VAL4 + Value Register 4 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM0FRACVAL5 + Fractional Value Register 5 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM0VAL5 + Value Register 5 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM0FRCTRL + Fractional Control Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM0OCTRL + Output Control Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM0STS + Status Register + 0x24 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM0INTEN + Interrupt Enable Register + 0x26 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM0DMAEN + DMA Enable Register + 0x28 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + no description available + 0x1 + + + + + + + SM0TCTRL + Output Trigger Control Register + 0x2A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM0DISMAP0 + Fault Disable Mapping Register 0 + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM0DISMAP1 + Fault Disable Mapping Register 1 + 0x2E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM0DTCNT0 + Deadtime Count Register 0 + 0x30 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM0DTCNT1 + Deadtime Count Register 1 + 0x32 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM0CAPTCTRLA + Capture Control A Register + 0x34 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + no description available + 0 + + + ONESHOTA_1 + no description available + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + no description available + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPA + Capture Compare A Register + 0x36 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM0CAPTCTRLB + Capture Control B Register + 0x38 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + no description available + 0 + + + ONESHOTB_1 + no description available + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + no description available + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPB + Capture Compare B Register + 0x3A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM0CAPTCTRLX + Capture Control X Register + 0x3C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + no description available + 0 + + + ONESHOTX_1 + no description available + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + no description available + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPX + Capture Compare X Register + 0x3E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM0CVAL0 + Capture Value 0 Register + 0x40 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM0CVAL0CYC + Capture Value 0 Cycle Register + 0x42 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM0CVAL1 + Capture Value 1 Register + 0x44 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM0CVAL1CYC + Capture Value 1 Cycle Register + 0x46 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM0CVAL2 + Capture Value 2 Register + 0x48 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM0CVAL2CYC + Capture Value 2 Cycle Register + 0x4A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM0CVAL3 + Capture Value 3 Register + 0x4C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM0CVAL3CYC + Capture Value 3 Cycle Register + 0x4E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM0CVAL4 + Capture Value 4 Register + 0x50 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM0CVAL4CYC + Capture Value 4 Cycle Register + 0x52 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM0CVAL5 + Capture Value 5 Register + 0x54 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM0CVAL5CYC + Capture Value 5 Cycle Register + 0x56 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM1CNT + Counter Register + 0x60 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM1INIT + Initial Count Register + 0x62 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM1CTRL2 + Control 2 Register + 0x64 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + write-only + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM1CTRL + Control Register + 0x66 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + no description available + 0 + + + PRSC_1 + no description available + 0x1 + + + PRSC_2 + no description available + 0x2 + + + PRSC_3 + no description available + 0x3 + + + PRSC_4 + no description available + 0x4 + + + PRSC_5 + no description available + 0x5 + + + PRSC_6 + no description available + 0x6 + + + PRSC_7 + no description available + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM1VAL0 + Value Register 0 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM1FRACVAL1 + Fractional Value Register 1 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM1VAL1 + Value Register 1 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM1FRACVAL2 + Fractional Value Register 2 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM1VAL2 + Value Register 2 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM1FRACVAL3 + Fractional Value Register 3 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM1VAL3 + Value Register 3 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM1FRACVAL4 + Fractional Value Register 4 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM1VAL4 + Value Register 4 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM1FRACVAL5 + Fractional Value Register 5 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM1VAL5 + Value Register 5 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM1FRCTRL + Fractional Control Register + 0x80 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM1OCTRL + Output Control Register + 0x82 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM1STS + Status Register + 0x84 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM1INTEN + Interrupt Enable Register + 0x86 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM1DMAEN + DMA Enable Register + 0x88 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + no description available + 0x1 + + + + + + + SM1TCTRL + Output Trigger Control Register + 0x8A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM1DISMAP0 + Fault Disable Mapping Register 0 + 0x8C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM1DISMAP1 + Fault Disable Mapping Register 1 + 0x8E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM1DTCNT0 + Deadtime Count Register 0 + 0x90 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM1DTCNT1 + Deadtime Count Register 1 + 0x92 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM1CAPTCTRLA + Capture Control A Register + 0x94 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + no description available + 0 + + + ONESHOTA_1 + no description available + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + no description available + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPA + Capture Compare A Register + 0x96 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM1CAPTCTRLB + Capture Control B Register + 0x98 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + no description available + 0 + + + ONESHOTB_1 + no description available + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + no description available + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPB + Capture Compare B Register + 0x9A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM1CAPTCTRLX + Capture Control X Register + 0x9C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + no description available + 0 + + + ONESHOTX_1 + no description available + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + no description available + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPX + Capture Compare X Register + 0x9E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM1CVAL0 + Capture Value 0 Register + 0xA0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM1CVAL0CYC + Capture Value 0 Cycle Register + 0xA2 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM1CVAL1 + Capture Value 1 Register + 0xA4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM1CVAL1CYC + Capture Value 1 Cycle Register + 0xA6 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM1CVAL2 + Capture Value 2 Register + 0xA8 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM1CVAL2CYC + Capture Value 2 Cycle Register + 0xAA + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM1CVAL3 + Capture Value 3 Register + 0xAC + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM1CVAL3CYC + Capture Value 3 Cycle Register + 0xAE + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM1CVAL4 + Capture Value 4 Register + 0xB0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM1CVAL4CYC + Capture Value 4 Cycle Register + 0xB2 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM1CVAL5 + Capture Value 5 Register + 0xB4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM1CVAL5CYC + Capture Value 5 Cycle Register + 0xB6 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM2CNT + Counter Register + 0xC0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM2INIT + Initial Count Register + 0xC2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM2CTRL2 + Control 2 Register + 0xC4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + write-only + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM2CTRL + Control Register + 0xC6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + no description available + 0 + + + PRSC_1 + no description available + 0x1 + + + PRSC_2 + no description available + 0x2 + + + PRSC_3 + no description available + 0x3 + + + PRSC_4 + no description available + 0x4 + + + PRSC_5 + no description available + 0x5 + + + PRSC_6 + no description available + 0x6 + + + PRSC_7 + no description available + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM2VAL0 + Value Register 0 + 0xCA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM2FRACVAL1 + Fractional Value Register 1 + 0xCC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM2VAL1 + Value Register 1 + 0xCE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM2FRACVAL2 + Fractional Value Register 2 + 0xD0 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM2VAL2 + Value Register 2 + 0xD2 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM2FRACVAL3 + Fractional Value Register 3 + 0xD4 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM2VAL3 + Value Register 3 + 0xD6 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM2FRACVAL4 + Fractional Value Register 4 + 0xD8 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM2VAL4 + Value Register 4 + 0xDA + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM2FRACVAL5 + Fractional Value Register 5 + 0xDC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM2VAL5 + Value Register 5 + 0xDE + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM2FRCTRL + Fractional Control Register + 0xE0 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM2OCTRL + Output Control Register + 0xE2 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM2STS + Status Register + 0xE4 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM2INTEN + Interrupt Enable Register + 0xE6 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM2DMAEN + DMA Enable Register + 0xE8 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + no description available + 0x1 + + + + + + + SM2TCTRL + Output Trigger Control Register + 0xEA + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM2DISMAP0 + Fault Disable Mapping Register 0 + 0xEC + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM2DISMAP1 + Fault Disable Mapping Register 1 + 0xEE + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM2DTCNT0 + Deadtime Count Register 0 + 0xF0 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM2DTCNT1 + Deadtime Count Register 1 + 0xF2 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM2CAPTCTRLA + Capture Control A Register + 0xF4 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + no description available + 0 + + + ONESHOTA_1 + no description available + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + no description available + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPA + Capture Compare A Register + 0xF6 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM2CAPTCTRLB + Capture Control B Register + 0xF8 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + no description available + 0 + + + ONESHOTB_1 + no description available + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + no description available + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPB + Capture Compare B Register + 0xFA + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM2CAPTCTRLX + Capture Control X Register + 0xFC + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + no description available + 0 + + + ONESHOTX_1 + no description available + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + no description available + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPX + Capture Compare X Register + 0xFE + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM2CVAL0 + Capture Value 0 Register + 0x100 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM2CVAL0CYC + Capture Value 0 Cycle Register + 0x102 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM2CVAL1 + Capture Value 1 Register + 0x104 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM2CVAL1CYC + Capture Value 1 Cycle Register + 0x106 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM2CVAL2 + Capture Value 2 Register + 0x108 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM2CVAL2CYC + Capture Value 2 Cycle Register + 0x10A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM2CVAL3 + Capture Value 3 Register + 0x10C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM2CVAL3CYC + Capture Value 3 Cycle Register + 0x10E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM2CVAL4 + Capture Value 4 Register + 0x110 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM2CVAL4CYC + Capture Value 4 Cycle Register + 0x112 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM2CVAL5 + Capture Value 5 Register + 0x114 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM2CVAL5CYC + Capture Value 5 Cycle Register + 0x116 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM3CNT + Counter Register + 0x120 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM3INIT + Initial Count Register + 0x122 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM3CTRL2 + Control 2 Register + 0x124 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + write-only + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM3CTRL + Control Register + 0x126 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + no description available + 0 + + + PRSC_1 + no description available + 0x1 + + + PRSC_2 + no description available + 0x2 + + + PRSC_3 + no description available + 0x3 + + + PRSC_4 + no description available + 0x4 + + + PRSC_5 + no description available + 0x5 + + + PRSC_6 + no description available + 0x6 + + + PRSC_7 + no description available + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM3VAL0 + Value Register 0 + 0x12A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM3FRACVAL1 + Fractional Value Register 1 + 0x12C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM3VAL1 + Value Register 1 + 0x12E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM3FRACVAL2 + Fractional Value Register 2 + 0x130 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM3VAL2 + Value Register 2 + 0x132 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM3FRACVAL3 + Fractional Value Register 3 + 0x134 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM3VAL3 + Value Register 3 + 0x136 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM3FRACVAL4 + Fractional Value Register 4 + 0x138 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM3VAL4 + Value Register 4 + 0x13A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM3FRACVAL5 + Fractional Value Register 5 + 0x13C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM3VAL5 + Value Register 5 + 0x13E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM3FRCTRL + Fractional Control Register + 0x140 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM3OCTRL + Output Control Register + 0x142 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM3STS + Status Register + 0x144 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM3INTEN + Interrupt Enable Register + 0x146 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM3DMAEN + DMA Enable Register + 0x148 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + no description available + 0x1 + + + + + + + SM3TCTRL + Output Trigger Control Register + 0x14A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM3DISMAP0 + Fault Disable Mapping Register 0 + 0x14C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM3DISMAP1 + Fault Disable Mapping Register 1 + 0x14E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM3DTCNT0 + Deadtime Count Register 0 + 0x150 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM3DTCNT1 + Deadtime Count Register 1 + 0x152 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM3CAPTCTRLA + Capture Control A Register + 0x154 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + no description available + 0 + + + ONESHOTA_1 + no description available + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + no description available + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPA + Capture Compare A Register + 0x156 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM3CAPTCTRLB + Capture Control B Register + 0x158 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + no description available + 0 + + + ONESHOTB_1 + no description available + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + no description available + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPB + Capture Compare B Register + 0x15A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM3CAPTCTRLX + Capture Control X Register + 0x15C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + no description available + 0 + + + ONESHOTX_1 + no description available + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + no description available + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPX + Capture Compare X Register + 0x15E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM3CVAL0 + Capture Value 0 Register + 0x160 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM3CVAL0CYC + Capture Value 0 Cycle Register + 0x162 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM3CVAL1 + Capture Value 1 Register + 0x164 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM3CVAL1CYC + Capture Value 1 Cycle Register + 0x166 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM3CVAL2 + Capture Value 2 Register + 0x168 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM3CVAL2CYC + Capture Value 2 Cycle Register + 0x16A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM3CVAL3 + Capture Value 3 Register + 0x16C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM3CVAL3CYC + Capture Value 3 Cycle Register + 0x16E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM3CVAL4 + Capture Value 4 Register + 0x170 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM3CVAL4CYC + Capture Value 4 Cycle Register + 0x172 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM3CVAL5 + Capture Value 5 Register + 0x174 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM3CVAL5CYC + Capture Value 5 Cycle Register + 0x176 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + OUTEN + Output Enable Register + 0x180 + 16 + read-write + 0 + 0xFFFF + + + PWMX_EN + PWM_X Output Enables + 0 + 4 + read-write + + + PWMX_EN_0 + PWM_X output disabled. + 0 + + + PWMX_EN_1 + PWM_X output enabled. + 0x1 + + + + + PWMB_EN + PWM_B Output Enables + 4 + 4 + read-write + + + PWMB_EN_0 + PWM_B output disabled. + 0 + + + PWMB_EN_1 + PWM_B output enabled. + 0x1 + + + + + PWMA_EN + PWM_A Output Enables + 8 + 4 + read-write + + + PWMA_EN_0 + PWM_A output disabled. + 0 + + + PWMA_EN_1 + PWM_A output enabled. + 0x1 + + + + + + + MASK + Mask Register + 0x182 + 16 + read-write + 0 + 0xFFFF + + + MASKX + PWM_X Masks + 0 + 4 + read-write + + + MASKX_0 + PWM_X output normal. + 0 + + + MASKX_1 + PWM_X output masked. + 0x1 + + + + + MASKB + PWM_B Masks + 4 + 4 + read-write + + + MASKB_0 + PWM_B output normal. + 0 + + + MASKB_1 + PWM_B output masked. + 0x1 + + + + + MASKA + PWM_A Masks + 8 + 4 + read-write + + + MASKA_0 + PWM_A output normal. + 0 + + + MASKA_1 + PWM_A output masked. + 0x1 + + + + + UPDATE_MASK + Update Mask Bits Immediately + 12 + 4 + write-only + + + UPDATE_MASK_0 + Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + 0 + + + UPDATE_MASK_1 + Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + 0x1 + + + + + + + SWCOUT + Software Controlled Output Register + 0x184 + 16 + read-write + 0 + 0xFFFF + + + SM0OUT45 + Submodule 0 Software Controlled Output 45 + 0 + 1 + read-write + + + SM0OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0 + + + SM0OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0x1 + + + + + SM0OUT23 + Submodule 0 Software Controlled Output 23 + 1 + 1 + read-write + + + SM0OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0 + + + SM0OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0x1 + + + + + SM1OUT45 + Submodule 1 Software Controlled Output 45 + 2 + 1 + read-write + + + SM1OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0 + + + SM1OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0x1 + + + + + SM1OUT23 + Submodule 1 Software Controlled Output 23 + 3 + 1 + read-write + + + SM1OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0 + + + SM1OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0x1 + + + + + SM2OUT45 + Submodule 2 Software Controlled Output 45 + 4 + 1 + read-write + + + SM2OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0 + + + SM2OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0x1 + + + + + SM2OUT23 + Submodule 2 Software Controlled Output 23 + 5 + 1 + read-write + + + SM2OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0 + + + SM2OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0x1 + + + + + SM3OUT45 + Submodule 3 Software Controlled Output 45 + 6 + 1 + read-write + + + SM3OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0 + + + SM3OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0x1 + + + + + SM3OUT23 + Submodule 3 Software Controlled Output 23 + 7 + 1 + read-write + + + SM3OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0 + + + SM3OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0x1 + + + + + + + DTSRCSEL + PWM Source Select Register + 0x186 + 16 + read-write + 0 + 0xFFFF + + + SM0SEL45 + Submodule 0 PWM45 Control Select + 0 + 2 + read-write + + + SM0SEL45_0 + Generated SM0PWM45 signal is used by the deadtime logic. + 0 + + + SM0SEL45_1 + Inverted generated SM0PWM45 signal is used by the deadtime logic. + 0x1 + + + SM0SEL45_2 + SWCOUT[SM0OUT45] is used by the deadtime logic. + 0x2 + + + SM0SEL45_3 + PWM0_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM0SEL23 + Submodule 0 PWM23 Control Select + 2 + 2 + read-write + + + SM0SEL23_0 + Generated SM0PWM23 signal is used by the deadtime logic. + 0 + + + SM0SEL23_1 + Inverted generated SM0PWM23 signal is used by the deadtime logic. + 0x1 + + + SM0SEL23_2 + SWCOUT[SM0OUT23] is used by the deadtime logic. + 0x2 + + + SM0SEL23_3 + PWM0_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL45 + Submodule 1 PWM45 Control Select + 4 + 2 + read-write + + + SM1SEL45_0 + Generated SM1PWM45 signal is used by the deadtime logic. + 0 + + + SM1SEL45_1 + Inverted generated SM1PWM45 signal is used by the deadtime logic. + 0x1 + + + SM1SEL45_2 + SWCOUT[SM1OUT45] is used by the deadtime logic. + 0x2 + + + SM1SEL45_3 + PWM1_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL23 + Submodule 1 PWM23 Control Select + 6 + 2 + read-write + + + SM1SEL23_0 + Generated SM1PWM23 signal is used by the deadtime logic. + 0 + + + SM1SEL23_1 + Inverted generated SM1PWM23 signal is used by the deadtime logic. + 0x1 + + + SM1SEL23_2 + SWCOUT[SM1OUT23] is used by the deadtime logic. + 0x2 + + + SM1SEL23_3 + PWM1_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL45 + Submodule 2 PWM45 Control Select + 8 + 2 + read-write + + + SM2SEL45_0 + Generated SM2PWM45 signal is used by the deadtime logic. + 0 + + + SM2SEL45_1 + Inverted generated SM2PWM45 signal is used by the deadtime logic. + 0x1 + + + SM2SEL45_2 + SWCOUT[SM2OUT45] is used by the deadtime logic. + 0x2 + + + SM2SEL45_3 + PWM2_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL23 + Submodule 2 PWM23 Control Select + 10 + 2 + read-write + + + SM2SEL23_0 + Generated SM2PWM23 signal is used by the deadtime logic. + 0 + + + SM2SEL23_1 + Inverted generated SM2PWM23 signal is used by the deadtime logic. + 0x1 + + + SM2SEL23_2 + SWCOUT[SM2OUT23] is used by the deadtime logic. + 0x2 + + + SM2SEL23_3 + PWM2_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL45 + Submodule 3 PWM45 Control Select + 12 + 2 + read-write + + + SM3SEL45_0 + Generated SM3PWM45 signal is used by the deadtime logic. + 0 + + + SM3SEL45_1 + Inverted generated SM3PWM45 signal is used by the deadtime logic. + 0x1 + + + SM3SEL45_2 + SWCOUT[SM3OUT45] is used by the deadtime logic. + 0x2 + + + SM3SEL45_3 + PWM3_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL23 + Submodule 3 PWM23 Control Select + 14 + 2 + read-write + + + SM3SEL23_0 + Generated SM3PWM23 signal is used by the deadtime logic. + 0 + + + SM3SEL23_1 + Inverted generated SM3PWM23 signal is used by the deadtime logic. + 0x1 + + + SM3SEL23_2 + SWCOUT[SM3OUT23] is used by the deadtime logic. + 0x2 + + + SM3SEL23_3 + PWM3_EXTA signal is used by the deadtime logic. + 0x3 + + + + + + + MCTRL + Master Control Register + 0x188 + 16 + read-write + 0 + 0xFFFF + + + LDOK + Load Okay + 0 + 4 + read-write + + + LDOK_0 + Do not load new values. + 0 + + + LDOK_1 + Load prescaler, modulus, and PWM values of the corresponding submodule. + 0x1 + + + + + CLDOK + Clear Load Okay + 4 + 4 + write-only + + + RUN + Run + 8 + 4 + read-write + + + RUN_0 + PWM generator is disabled in the corresponding submodule. + 0 + + + RUN_1 + PWM generator is enabled in the corresponding submodule. + 0x1 + + + + + IPOL + Current Polarity + 12 + 4 + read-write + + + IPOL_0 + PWM23 is used to generate complementary PWM pair in the corresponding submodule. + 0 + + + IPOL_1 + PWM45 is used to generate complementary PWM pair in the corresponding submodule. + 0x1 + + + + + + + MCTRL2 + Master Control 2 Register + 0x18A + 16 + read-write + 0 + 0xFFFF + + + MONPLL + Monitor PLL State + 0 + 2 + read-write + + + MONPLL_0 + Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + 0 + + + MONPLL_1 + Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + 0x1 + + + MONPLL_2 + Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + 0x2 + + + MONPLL_3 + Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + 0x3 + + + + + + + FCTRL0 + Fault Control Register + 0x18C + 16 + read-write + 0 + 0xFFFF + + + FIE + Fault Interrupt Enables + 0 + 4 + read-write + + + FIE_0 + FAULTx CPU interrupt requests disabled. + 0 + + + FIE_1 + FAULTx CPU interrupt requests enabled. + 0x1 + + + + + FSAFE + Fault Safety Mode + 4 + 4 + read-write + + + FSAFE_0 + Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + 0 + + + FSAFE_1 + Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + 0x1 + + + + + FAUTO + Automatic Fault Clearing + 8 + 4 + read-write + + + FAUTO_0 + Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. + 0 + + + FAUTO_1 + Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. + 0x1 + + + + + FLVL + Fault Level + 12 + 4 + read-write + + + FLVL_0 + A logic 0 on the fault input indicates a fault condition. + 0 + + + FLVL_1 + A logic 1 on the fault input indicates a fault condition. + 0x1 + + + + + + + FSTS0 + Fault Status Register + 0x18E + 16 + read-write + 0 + 0xFFFF + + + FFLAG + Fault Flags + 0 + 4 + read-write + + + FFLAG_0 + No fault on the FAULTx pin. + 0 + + + FFLAG_1 + Fault on the FAULTx pin. + 0x1 + + + + + FFULL + Full Cycle + 4 + 4 + read-write + + + FFULL_0 + PWM outputs are not re-enabled at the start of a full cycle + 0 + + + FFULL_1 + PWM outputs are re-enabled at the start of a full cycle + 0x1 + + + + + FFPIN + Filtered Fault Pins + 8 + 4 + read-only + + + FHALF + Half Cycle Fault Recovery + 12 + 4 + read-write + + + FHALF_0 + PWM outputs are not re-enabled at the start of a half cycle. + 0 + + + FHALF_1 + PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + 0x1 + + + + + + + FFILT0 + Fault Filter Register + 0x190 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Fault Filter Period + 0 + 8 + read-write + + + FILT_CNT + Fault Filter Count + 8 + 3 + read-write + + + GSTR + Fault Glitch Stretch Enable + 15 + 1 + read-write + + + GSTR_0 + Fault input glitch stretching is disabled. + 0 + + + GSTR_1 + Input fault signals will be stretched to at least 2 IPBus clock cycles. + 0x1 + + + + + + + FTST0 + Fault Test Register + 0x192 + 16 + read-write + 0 + 0xFFFF + + + FTEST + Fault Test + 0 + 1 + read-write + + + FTEST_0 + No fault + 0 + + + FTEST_1 + Cause a simulated fault + 0x1 + + + + + + + FCTRL20 + Fault Control 2 Register + 0x194 + 16 + read-write + 0 + 0xFFFF + + + NOCOMB + No Combinational Path From Fault Input To PWM Output + 0 + 4 + read-write + + + NOCOMB_0 + There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + 0 + + + NOCOMB_1 + The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + 0x1 + + + + + + + + + PWM2 + PWM + PWM + 0x403E0000 + + 0 + 0x196 + registers + + + PWM2_0 + 137 + + + PWM2_1 + 138 + + + PWM2_2 + 139 + + + PWM2_3 + 140 + + + PWM2_FAULT + 141 + + + + PWM3 + PWM + PWM + 0x403E4000 + + 0 + 0x196 + registers + + + PWM3_0 + 142 + + + PWM3_1 + 143 + + + PWM3_2 + 144 + + + PWM3_3 + 145 + + + PWM3_FAULT + 146 + + + + PWM4 + PWM + PWM + 0x403E8000 + + 0 + 0x196 + registers + + + PWM4_0 + 147 + + + PWM4_1 + 148 + + + PWM4_2 + 149 + + + PWM4_3 + 150 + + + PWM4_FAULT + 151 + + + + BEE + Bus Encryption Engine + BEE + BEE_ + 0x403EC000 + + 0 + 0x48 + registers + + + BEE + 55 + + + + CTRL + BEE Control Register + 0 + 32 + read-write + 0x7700 + 0xFFFFFFFF + + + BEE_ENABLE + BEE enable bit + 0 + 1 + read-write + + + BEE_ENABLE_0 + Disable BEE + 0 + + + BEE_ENABLE_1 + Enable BEE + 0x1 + + + + + CTRL_CLK_EN + Clock enable input, low inactive + 1 + 1 + read-write + + + CTRL_SFTRST_N + Soft reset input, low active + 2 + 1 + read-write + + + KEY_VALID + AES-128 key is ready + 4 + 1 + read-write + + + KEY_REGION_SEL + AES key region select + 5 + 1 + read-write + + + KEY_REGION_SEL_0 + Load AES key for region0 + 0 + + + KEY_REGION_SEL_1 + Load AES key for region1 + 0x1 + + + + + AC_PROT_EN + Enable access permission control + 6 + 1 + read-write + + + LITTLE_ENDIAN + Endian swap control for the 16 bytes input and output data of AES core. + 7 + 1 + read-write + + + LITTLE_ENDIAN_0 + The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + 0 + + + LITTLE_ENDIAN_1 + The input and output data of AES core is not swapped. + 0x1 + + + + + SECURITY_LEVEL_R0 + Security level of the allowed access for memory region0 + 8 + 2 + read-write + + + CTRL_AES_MODE_R0 + AES mode of region0 + 10 + 1 + read-write + + + CTRL_AES_MODE_R0_0 + ECB + 0 + + + CTRL_AES_MODE_R0_1 + CTR + 0x1 + + + + + SECURITY_LEVEL_R1 + Security level of the allowed access for memory region1 + 12 + 2 + read-write + + + CTRL_AES_MODE_R1 + AES mode of region1 + 14 + 1 + read-write + + + CTRL_AES_MODE_R1_0 + ECB + 0 + + + CTRL_AES_MODE_R1_1 + CTR + 0x1 + + + + + BEE_ENABLE_LOCK + Lock bit for bee_enable + 16 + 1 + read-write + + + CTRL_CLK_EN_LOCK + Lock bit for ctrl_clk_en + 17 + 1 + read-write + + + CTRL_SFTRST_N_LOCK + Lock bit for ctrl_sftrst + 18 + 1 + read-write + + + REGION1_ADDR_LOCK + Lock bit for region1 address boundary + 19 + 1 + read-write + + + KEY_VALID_LOCK + Lock bit for key_valid + 20 + 1 + read-write + + + KEY_REGION_SEL_LOCK + Lock bit for key_region_sel + 21 + 1 + read-write + + + AC_PROT_EN_LOCK + Lock bit for ac_prot + 22 + 1 + read-write + + + LITTLE_ENDIAN_LOCK + Lock bit for little_endian + 23 + 1 + read-write + + + SECURITY_LEVEL_R0_LOCK + Lock bits for security_level_r0 + 24 + 2 + read-write + + + CTRL_AES_MODE_R0_LOCK + Lock bit for region0 ctrl_aes_mode + 26 + 1 + read-write + + + REGION0_KEY_LOCK + Lock bit for region0 AES key + 27 + 1 + read-write + + + SECURITY_LEVEL_R1_LOCK + Lock bits for security_level_r1 + 28 + 2 + read-write + + + CTRL_AES_MODE_R1_LOCK + Lock bit for region1 ctrl_aes_mode + 30 + 1 + read-write + + + REGION1_KEY_LOCK + Lock bit for region1 AES key + 31 + 1 + read-write + + + + + ADDR_OFFSET0 + no description available + 0x4 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET0 + Address offset used to remap received address to output address of memory region0 + 0 + 16 + read-write + + + ADDR_OFFSET0_LOCK + Lock bits for addr_offset0 + 16 + 16 + read-write + + + + + ADDR_OFFSET1 + no description available + 0x8 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET0 + Address offset used to remap received address to output address of memory region1 + 0 + 16 + read-write + + + ADDR_OFFSET0_LOCK + Lock bits for addr_offset1 + 16 + 16 + read-write + + + + + AES_KEY0_W0 + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY0 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W1 + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY1 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W2 + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY2 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W3 + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY3 + AES 128 key from software + 0 + 32 + read-write + + + + + STATUS + no description available + 0x1C + 32 + read-write + 0 + 0 + + + IRQ_VEC + bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 Read channel security violation bit 0: Disable abort + 0 + 8 + read-write + oneToClear + + + BEE_IDLE + Lock bits for addr_offset1 + 8 + 1 + read-only + + + + + CTR_NONCE0_W0 + no description available + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE00 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W1 + no description available + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE01 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W2 + no description available + 0x28 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE02 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W3 + no description available + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE03 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE1_W0 + no description available + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE10 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W1 + no description available + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE11 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W2 + no description available + 0x38 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE12 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W3 + no description available + 0x3C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE13 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + REGION1_TOP + no description available + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_TOP + Address upper limit of region1 + 0 + 32 + read-write + + + + + REGION1_BOT + no description available + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_BOT + Address lower limit of region1 + 0 + 32 + read-write + + + + + + + LPI2C1 + LPI2C + LPI2C + LPI2C + 0x403F0000 + + 0 + 0x174 + registers + + + LPI2C1 + 28 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1000003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_2 + Master only, with standard feature set + 0x2 + + + FEATURE_3 + Master and slave, with standard feature set + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + MTXFIFO + Master Transmit FIFO Size + 0 + 4 + read-only + + + MRXFIFO + Master Receive FIFO Size + 8 + 4 + read-only + + + + + MCR + Master Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Master Enable + 0 + 1 + read-write + + + MEN_0 + Master logic is disabled + 0 + + + MEN_1 + Master logic is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Master logic is not reset + 0 + + + RST_1 + Master logic is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Master is enabled in Doze mode + 0 + + + DOZEN_1 + Master is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Master is disabled in debug mode + 0 + + + DBGEN_1 + Master is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + MSR + Master Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data is not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + EPF + End Packet Flag + 8 + 1 + read-write + oneToClear + + + EPF_0 + Master has not generated a STOP or Repeated START condition + 0 + + + EPF_1 + Master has generated a STOP or Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Master has not generated a STOP condition + 0 + + + SDF_1 + Master has generated a STOP condition + 0x1 + + + + + NDF + NACK Detect Flag + 10 + 1 + read-write + oneToClear + + + NDF_0 + Unexpected NACK was not detected + 0 + + + NDF_1 + Unexpected NACK was detected + 0x1 + + + + + ALF + Arbitration Lost Flag + 11 + 1 + read-write + oneToClear + + + ALF_0 + Master has not lost arbitration + 0 + + + ALF_1 + Master has lost arbitration + 0x1 + + + + + FEF + FIFO Error Flag + 12 + 1 + read-write + oneToClear + + + FEF_0 + No error + 0 + + + FEF_1 + Master sending or receiving data without a START condition + 0x1 + + + + + PLTF + Pin Low Timeout Flag + 13 + 1 + read-write + oneToClear + + + PLTF_0 + Pin low timeout has not occurred or is disabled + 0 + + + PLTF_1 + Pin low timeout has occurred + 0x1 + + + + + DMF + Data Match Flag + 14 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Master Busy Flag + 24 + 1 + read-only + + + MBF_0 + I2C Master is idle + 0 + + + MBF_1 + I2C Master is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + MIER + Master Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + EPIE + End Packet Interrupt Enable + 8 + 1 + read-write + + + EPIE_0 + Disabled + 0 + + + EPIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + NDIE + NACK Detect Interrupt Enable + 10 + 1 + read-write + + + NDIE_0 + Disabled + 0 + + + NDIE_1 + Enabled + 0x1 + + + + + ALIE + Arbitration Lost Interrupt Enable + 11 + 1 + read-write + + + ALIE_0 + Disabled + 0 + + + ALIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 12 + 1 + read-write + + + FEIE_0 + Enabled + 0 + + + FEIE_1 + Disabled + 0x1 + + + + + PLTIE + Pin Low Timeout Interrupt Enable + 13 + 1 + read-write + + + PLTIE_0 + Disabled + 0 + + + PLTIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 14 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + MDER + Master DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + MCFGR0 + Master Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request input is disabled + 0 + + + HREN_1 + Host request input is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is pin HREQ + 0 + + + HRSEL_1 + Host request input is input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO + 0 + + + RDMO_1 + Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + 0x1 + + + + + + + MCFGR1 + Master Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALE + Prescaler + 0 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + AUTOSTOP + Automatic STOP Generation + 8 + 1 + read-write + + + AUTOSTOP_0 + No effect + 0 + + + AUTOSTOP_1 + STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + 0x1 + + + + + IGNACK + IGNACK + 9 + 1 + read-write + + + IGNACK_0 + LPI2C Master will receive ACK and NACK normally + 0 + + + IGNACK_1 + LPI2C Master will treat a received NACK as if it (NACK) was an ACK + 0x1 + + + + + TIMECFG + Timeout Configuration + 10 + 1 + read-write + + + TIMECFG_0 + Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + 0 + + + TIMECFG_1 + Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + Match is enabled (1st data word equals MATCH0 OR MATCH1) + 0x2 + + + MATCFG_3 + Match is enabled (any data word equals MATCH0 OR MATCH1) + 0x3 + + + MATCFG_4 + Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + 0x4 + + + MATCFG_5 + Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + 0x5 + + + MATCFG_6 + Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x6 + + + MATCFG_7 + Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 3 + read-write + + + PINCFG_0 + 2-pin open drain mode + 0 + + + PINCFG_1 + 2-pin output only mode (ultra-fast mode) + 0x1 + + + PINCFG_2 + 2-pin push-pull mode + 0x2 + + + PINCFG_3 + 4-pin push-pull mode + 0x3 + + + PINCFG_4 + 2-pin open drain mode with separate LPI2C slave + 0x4 + + + PINCFG_5 + 2-pin output only mode (ultra-fast mode) with separate LPI2C slave + 0x5 + + + PINCFG_6 + 2-pin push-pull mode with separate LPI2C slave + 0x6 + + + PINCFG_7 + 4-pin push-pull mode (inverted outputs) + 0x7 + + + + + + + MCFGR2 + Master Configuration Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUSIDLE + Bus Idle Timeout + 0 + 12 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + MCFGR3 + Master Configuration Register 3 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PINLOW + Pin Low Timeout + 8 + 12 + read-write + + + + + MDMR + Master Data Match Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 8 + read-write + + + MATCH1 + Match 1 Value + 16 + 8 + read-write + + + + + MCCR0 + Master Clock Configuration Register 0 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MCCR1 + Master Clock Configuration Register 1 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MFCR + Master FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 2 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 2 + read-write + + + + + MFSR + Master FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 3 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 3 + read-only + + + + + MTDR + Master Transmit Data Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + CMD + Command Data + 8 + 3 + write-only + + + CMD_0 + Transmit DATA[7:0] + 0 + + + CMD_1 + Receive (DATA[7:0] + 1) bytes + 0x1 + + + CMD_2 + Generate STOP condition + 0x2 + + + CMD_3 + Receive and discard (DATA[7:0] + 1) bytes + 0x3 + + + CMD_4 + Generate (repeated) START and transmit address in DATA[7:0] + 0x4 + + + CMD_5 + Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + 0x5 + + + CMD_6 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + 0x6 + + + CMD_7 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + 0x7 + + + + + + + MRDR + Master Receive Data Register + 0x70 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + Receive FIFO is not empty + 0 + + + RXEMPTY_1 + Receive FIFO is empty + 0x1 + + + + + + + SCR + Slave Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEN + Slave Enable + 0 + 1 + read-write + + + SEN_0 + I2C Slave mode is disabled + 0 + + + SEN_1 + I2C Slave mode is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Slave mode logic is not reset + 0 + + + RST_1 + Slave mode logic is reset + 0x1 + + + + + FILTEN + Filter Enable + 4 + 1 + read-write + + + FILTEN_0 + Disable digital filter and output delay counter for slave mode + 0 + + + FILTEN_1 + Enable digital filter and output delay counter for slave mode + 0x1 + + + + + FILTDZ + Filter Doze Enable + 5 + 1 + read-write + + + FILTDZ_0 + Filter remains enabled in Doze mode + 0 + + + FILTDZ_1 + Filter is disabled in Doze mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit Data Register is now empty + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive Data Register is now empty + 0x1 + + + + + + + SSR + Slave Status Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + AVF + Address Valid Flag + 2 + 1 + read-only + + + AVF_0 + Address Status Register is not valid + 0 + + + AVF_1 + Address Status Register is valid + 0x1 + + + + + TAF + Transmit ACK Flag + 3 + 1 + read-only + + + TAF_0 + Transmit ACK/NACK is not required + 0 + + + TAF_1 + Transmit ACK/NACK is required + 0x1 + + + + + RSF + Repeated Start Flag + 8 + 1 + read-write + oneToClear + + + RSF_0 + Slave has not detected a Repeated START condition + 0 + + + RSF_1 + Slave has detected a Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Slave has not detected a STOP condition + 0 + + + SDF_1 + Slave has detected a STOP condition + 0x1 + + + + + BEF + Bit Error Flag + 10 + 1 + read-write + oneToClear + + + BEF_0 + Slave has not detected a bit error + 0 + + + BEF_1 + Slave has detected a bit error + 0x1 + + + + + FEF + FIFO Error Flag + 11 + 1 + read-write + oneToClear + + + FEF_0 + FIFO underflow or overflow was not detected + 0 + + + FEF_1 + FIFO underflow or overflow was detected + 0x1 + + + + + AM0F + Address Match 0 Flag + 12 + 1 + read-only + + + AM0F_0 + Have not received an ADDR0 matching address + 0 + + + AM0F_1 + Have received an ADDR0 matching address + 0x1 + + + + + AM1F + Address Match 1 Flag + 13 + 1 + read-only + + + AM1F_0 + Have not received an ADDR1 or ADDR0/ADDR1 range matching address + 0 + + + AM1F_1 + Have received an ADDR1 or ADDR0/ADDR1 range matching address + 0x1 + + + + + GCF + General Call Flag + 14 + 1 + read-only + + + GCF_0 + Slave has not detected the General Call Address or the General Call Address is disabled + 0 + + + GCF_1 + Slave has detected the General Call Address + 0x1 + + + + + SARF + SMBus Alert Response Flag + 15 + 1 + read-only + + + SARF_0 + SMBus Alert Response is disabled or not detected + 0 + + + SARF_1 + SMBus Alert Response is enabled and detected + 0x1 + + + + + SBF + Slave Busy Flag + 24 + 1 + read-only + + + SBF_0 + I2C Slave is idle + 0 + + + SBF_1 + I2C Slave is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + SIER + Slave Interrupt Enable Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + AVIE + Address Valid Interrupt Enable + 2 + 1 + read-write + + + AVIE_0 + Disabled + 0 + + + AVIE_1 + Enabled + 0x1 + + + + + TAIE + Transmit ACK Interrupt Enable + 3 + 1 + read-write + + + TAIE_0 + Disabled + 0 + + + TAIE_1 + Enabled + 0x1 + + + + + RSIE + Repeated Start Interrupt Enable + 8 + 1 + read-write + + + RSIE_0 + Disabled + 0 + + + RSIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + BEIE + Bit Error Interrupt Enable + 10 + 1 + read-write + + + BEIE_0 + Disabled + 0 + + + BEIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 11 + 1 + read-write + + + FEIE_0 + Disabled + 0 + + + FEIE_1 + Enabled + 0x1 + + + + + AM0IE + Address Match 0 Interrupt Enable + 12 + 1 + read-write + + + AM0IE_0 + Enabled + 0 + + + AM0IE_1 + Disabled + 0x1 + + + + + AM1F + Address Match 1 Interrupt Enable + 13 + 1 + read-write + + + AM1F_0 + Disabled + 0 + + + AM1F_1 + Enabled + 0x1 + + + + + GCIE + General Call Interrupt Enable + 14 + 1 + read-write + + + GCIE_0 + Disabled + 0 + + + GCIE_1 + Enabled + 0x1 + + + + + SARIE + SMBus Alert Response Interrupt Enable + 15 + 1 + read-write + + + SARIE_0 + Disabled + 0 + + + SARIE_1 + Enabled + 0x1 + + + + + + + SDER + Slave DMA Enable Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + AVDE + Address Valid DMA Enable + 2 + 1 + read-write + + + AVDE_0 + DMA request is disabled + 0 + + + AVDE_1 + DMA request is enabled + 0x1 + + + + + + + SCFGR1 + Slave Configuration Register 1 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADRSTALL + Address SCL Stall + 0 + 1 + read-write + + + ADRSTALL_0 + Clock stretching is disabled + 0 + + + ADRSTALL_1 + Clock stretching is enabled + 0x1 + + + + + RXSTALL + RX SCL Stall + 1 + 1 + read-write + + + RXSTALL_0 + Clock stretching is disabled + 0 + + + RXSTALL_1 + Clock stretching is enabled + 0x1 + + + + + TXDSTALL + TX Data SCL Stall + 2 + 1 + read-write + + + TXDSTALL_0 + Clock stretching is disabled + 0 + + + TXDSTALL_1 + Clock stretching is enabled + 0x1 + + + + + ACKSTALL + ACK SCL Stall + 3 + 1 + read-write + + + ACKSTALL_0 + Clock stretching is disabled + 0 + + + ACKSTALL_1 + Clock stretching is enabled + 0x1 + + + + + GCEN + General Call Enable + 8 + 1 + read-write + + + GCEN_0 + General Call address is disabled + 0 + + + GCEN_1 + General Call address is enabled + 0x1 + + + + + SAEN + SMBus Alert Enable + 9 + 1 + read-write + + + SAEN_0 + Disables match on SMBus Alert + 0 + + + SAEN_1 + Enables match on SMBus Alert + 0x1 + + + + + TXCFG + Transmit Flag Configuration + 10 + 1 + read-write + + + TXCFG_0 + Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + 0 + + + TXCFG_1 + Transmit Data Flag will assert whenever the Transmit Data register is empty + 0x1 + + + + + RXCFG + Receive Data Configuration + 11 + 1 + read-write + + + RXCFG_0 + Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + 0 + + + RXCFG_1 + Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + 0x1 + + + + + IGNACK + Ignore NACK + 12 + 1 + read-write + + + IGNACK_0 + Slave will end transfer when NACK is detected + 0 + + + IGNACK_1 + Slave will not end transfer when NACK detected + 0x1 + + + + + HSMEN + High Speed Mode Enable + 13 + 1 + read-write + + + HSMEN_0 + Disables detection of HS-mode master code + 0 + + + HSMEN_1 + Enables detection of HS-mode master code + 0x1 + + + + + ADDRCFG + Address Configuration + 16 + 3 + read-write + + + ADDRCFG_0 + Address match 0 (7-bit) + 0 + + + ADDRCFG_1 + Address match 0 (10-bit) + 0x1 + + + ADDRCFG_2 + Address match 0 (7-bit) or Address match 1 (7-bit) + 0x2 + + + ADDRCFG_3 + Address match 0 (10-bit) or Address match 1 (10-bit) + 0x3 + + + ADDRCFG_4 + Address match 0 (7-bit) or Address match 1 (10-bit) + 0x4 + + + ADDRCFG_5 + Address match 0 (10-bit) or Address match 1 (7-bit) + 0x5 + + + ADDRCFG_6 + From Address match 0 (7-bit) to Address match 1 (7-bit) + 0x6 + + + ADDRCFG_7 + From Address match 0 (10-bit) to Address match 1 (10-bit) + 0x7 + + + + + + + SCFGR2 + Slave Configuration Register 2 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKHOLD + Clock Hold Time + 0 + 4 + read-write + + + DATAVD + Data Valid Delay + 8 + 6 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + SAMR + Slave Address Match Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0 + Address 0 Value + 1 + 10 + read-write + + + ADDR1 + Address 1 Value + 17 + 10 + read-write + + + + + SASR + Slave Address Status Register + 0x150 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + RADDR + Received Address + 0 + 11 + read-only + + + ANV + Address Not Valid + 14 + 1 + read-only + + + ANV_0 + Received Address (RADDR) is valid + 0 + + + ANV_1 + Received Address (RADDR) is not valid + 0x1 + + + + + + + STAR + Slave Transmit ACK Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXNACK + Transmit NACK + 0 + 1 + read-write + + + TXNACK_0 + Write a Transmit ACK for each received word + 0 + + + TXNACK_1 + Write a Transmit NACK for each received word + 0x1 + + + + + + + STDR + Slave Transmit Data Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + + + SRDR + Slave Receive Data Register + 0x170 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + The Receive Data Register is not empty + 0 + + + RXEMPTY_1 + The Receive Data Register is empty + 0x1 + + + + + SOF + Start Of Frame + 15 + 1 + read-only + + + SOF_0 + Indicates this is not the first data word since a (repeated) START or STOP condition + 0 + + + SOF_1 + Indicates this is the first data word since a (repeated) START or STOP condition + 0x1 + + + + + + + + + LPI2C2 + LPI2C + LPI2C + 0x403F4000 + + 0 + 0x174 + registers + + + LPI2C2 + 29 + + + + LPI2C3 + LPI2C + LPI2C + 0x403F8000 + + 0 + 0x174 + registers + + + LPI2C3 + 30 + + + + LPI2C4 + LPI2C + LPI2C + 0x403FC000 + + 0 + 0x174 + registers + + + LPI2C4 + 31 + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xFAC + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + DISFOLD_0 + Normal operation. + 0 + + + + + FPEXCODIS + Disables FPU exception outputs. + 10 + 1 + read-write + + + FPEXCODIS_0 + Normal operation. + 0 + + + FPEXCODIS_1 + FPU exception outputs are disabled. + 0x1 + + + + + DISRAMODE + Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. + 11 + 1 + read-write + + + DISRAMODE_0 + Normal operation. + 0 + + + DISRAMODE_1 + Dynamic disabled. + 0x1 + + + + + DISITMATBFLUSH + Disables ITM and DWT ATB flush. + 12 + 1 + read-write + + + DISITMATBFLUSH_1 + ITM and DWT ATB flush disabled, this bit is always 1. + 0x1 + + + + + DISBTACREAD + Disables BTAC read. + 13 + 1 + read-write + + + DISBTACREAD_0 + Normal operation. + 0 + + + DISBTACREAD_1 + BTAC is not used and only static branch prediction can occur. + 0x1 + + + + + DISBTACALLOC + Disables BTAC allocate. + 14 + 1 + read-write + + + DISBTACALLOC_0 + Normal operation. + 0 + + + DISBTACALLOC_1 + No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. + 0x1 + + + + + DISCRITAXIRUR + Disables critical AXI Read-Under-Read. + 15 + 1 + read-write + + + DISCRITAXIRUR_0 + Normal operation. + 0 + + + DISCRITAXIRUR_1 + An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. + 0x1 + + + + + DISDI + Disables dual-issued. + 16 + 5 + read-write + + + DISDI_0 + Normal operation. + 0 + + + DISDI_1 + Nothing can be dual-issued when this instruction type is in channel 0. + 0x1 + + + + + DISISSCH1 + Disables dual-issued. + 21 + 5 + read-write + + + DISISSCH1_0 + Normal operation. + 0 + + + DISISSCH1_1 + Nothing can be dual-issued when this instruction type is in channel 1. + 0x1 + + + + + DISDYNADD + Disables dynamic allocation of ADD and SUB instructions + 26 + 1 + read-write + + + DISDYNADD_0 + Normal operation. Some ADD and SUB instrctions are resolved in EX1. + 0 + + + DISDYNADD_1 + All ADD and SUB instructions are resolved in EX2. + 0x1 + + + + + DISCRITAXIRUW + Disables critical AXI read-under-write + 27 + 1 + read-write + + + DISCRITAXIRUW_0 + Normal operation. This is backwards compatible with r0. + 0 + + + DISCRITAXIRUW_1 + AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. + 0x1 + + + + + DISFPUISSOPT + Disables critical AXI read-under-write + 28 + 1 + read-write + + + DISFPUISSOPT_0 + Normal operation. + 0 + + + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + ARCHITECTURE + ARCHITECTURE + 16 + 4 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + Indicates whether there are preempted active exceptions + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + read-only + + + ISRPENDING + Interrupt pending flag, excluding NMI and Faults + 22 + 1 + read-only + + + ISRPENDING_0 + No external interrupt pending. + 0 + + + ISRPENDING_1 + External interrupt pending. + 0x1 + + + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + Writing 1 to this bit causes a local system reset + 0 + 1 + write-only + + + VECTRESET_0 + No change + 0 + + + VECTRESET_1 + Causes a local system reset + 0x1 + + + + + VECTCLRACTIVE + Writing 1 to this bit clears all active state information for fixed and configurable exceptions. + 1 + 1 + write-only + + + VECTCLRACTIVE_0 + No change + 0 + + + VECTCLRACTIVE_1 + Clears all active state information for fixed and configurable exceptions + 0x1 + + + + + SYSRESETREQ + System reset request + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + Data endianness + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + NONBASETHRDENA + Indicates how the processor enters Thread mode + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + DC + Enables L1 data cache. + 16 + 1 + read-write + + + DC_0 + L1 data cache disabled + 0 + + + DC_1 + L1 data cache enabled + 0x1 + + + + + IC + Enables L1 instruction cache. + 17 + 1 + read-write + + + IC_0 + L1 instruction cache disabled + 0 + + + IC_1 + L1 instruction cache enabled + 0x1 + + + + + BP + Always reads-as-one. It indicates branch prediction is enabled. + 18 + 1 + read-only + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active bit + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + UsageFault exception active bit + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + SVCall active bit + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + Debug monitor active bit + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + PendSV exception active bit + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + SVCall pending bit + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + MemManage enable bit + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + BusFault enable bit + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + UsageFault enable bit + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + Instruction access violation flag + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + Data access violation flag + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + MemManage fault on unstacking for a return from exception + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + MemManage fault on stacking for exception entry + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + MemManage fault occurred during floating-point lazy state preservation + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + MemManage Fault Address Register (MMFAR) valid flag + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + Instruction bus error + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + Precise data bus error + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + BusFault on unstacking for a return from exception + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + BusFault on stacking for exception entry + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + Bus fault occurred during floating-point lazy state preservation + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + BusFault Address Register (BFAR) valid flag + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + Invalid state UsageFault + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + No coprocessor UsageFault + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + Unaligned access UsageFault + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + Divide by zero UsageFault + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + Indicates a BusFault on a vector table read during exception processing. + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled. + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. + 31 + 1 + read-write + + + DEBUGEVT_0 + No Debug event has occurred. + 0 + + + DEBUGEVT_1 + Debug event has occurred. The Debug Fault Status Register has been updated. + 0x1 + + + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1. + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + Debug event generated by BKPT instruction execution or a breakpoint match in FPB + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + Debug event generated by the DWT + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + Indicates triggering of a Vector catch + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + Debug event generated because of the assertion of an external debug request + 4 + 1 + read-write + + + EXTERNAL_0 + No external debug request debug event + 0 + + + EXTERNAL_1 + External debug request debug event + 0x1 + + + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + ID_PFR0 + Processor Feature Register 0 + 0xD40 + 32 + read-only + 0 + 0xFFFFFFFF + + + STATE0 + ARM instruction set support + 0 + 4 + read-only + + + STATE0_0 + ARMv7-M unused + 0 + + + STATE0_1 + ARMv7-M unused + 0x1 + + + STATE0_2 + ARMv7-M unused + 0x2 + + + STATE0_3 + Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions. + 0x3 + + + + + STATE1 + Thumb instruction set support + 4 + 4 + read-only + + + STATE1_0 + The processor does not support the ARM instruction set. + 0 + + + STATE1_1 + ARMv7-M unused + 0x1 + + + + + STATE2 + ARMv7-M unused + 8 + 4 + read-only + + + STATE3 + ARMv7-M unused + 12 + 4 + read-only + + + + + ID_PFR1 + Processor Feature Register 1 + 0xD44 + 32 + read-only + 0 + 0xFFFFFFFF + + + PROGMODEL + M profile programmers' model + 8 + 4 + read-only + + + PROGMODEL_0 + ARMv7-M unused + 0 + + + PROGMODEL_2 + Two-stack programmers' model supported + 0x2 + + + + + + + ID_DFR0 + Debug Feature Register + 0xD48 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUGMODEL + Support for memory-mapped debug model for M profile processors + 20 + 4 + read-only + + + DEBUGMODEL_0 + Not supported + 0 + + + DEBUGMODEL_1 + Support for M profile Debug architecture, with memory-mapped access. + 0x1 + + + + + + + ID_AFR0 + Auxiliary Feature Register + 0xD4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IMPLEMENTATION_DEFINED0 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 0 + 4 + read-only + + + IMPLEMENTATION_DEFINED1 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 4 + 4 + read-only + + + IMPLEMENTATION_DEFINED2 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 8 + 4 + read-only + + + IMPLEMENTATION_DEFINED3 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 12 + 4 + read-only + + + + + ID_MMFR0 + Memory Model Feature Register 0 + 0xD50 + 32 + read-only + 0 + 0xFFFFFFFF + + + PMSASUPPORT + Indicates support for a PMSA + 4 + 4 + read-only + + + PMSASUPPORT_0 + Not supported + 0 + + + PMSASUPPORT_1 + ARMv7-M unused + 0x1 + + + PMSASUPPORT_2 + ARMv7-M unused + 0x2 + + + PMSASUPPORT_3 + PMSAv7, providing support for a base region and subregions. + 0x3 + + + + + OUTERMOST_SHAREABILITY + Indicates the outermost shareability domain implemented + 8 + 4 + read-only + + + OUTERMOST_SHAREABILITY_0 + Implemented as Non-cacheable + 0 + + + OUTERMOST_SHAREABILITY_1 + ARMv7-M unused + 0x1 + + + OUTERMOST_SHAREABILITY_2 + ARMv7-M unused + 0x2 + + + OUTERMOST_SHAREABILITY_3 + ARMv7-M unused + 0x3 + + + OUTERMOST_SHAREABILITY_4 + ARMv7-M unused + 0x4 + + + OUTERMOST_SHAREABILITY_5 + ARMv7-M unused + 0x5 + + + OUTERMOST_SHAREABILITY_6 + ARMv7-M unused + 0x6 + + + OUTERMOST_SHAREABILITY_7 + ARMv7-M unused + 0x7 + + + OUTERMOST_SHAREABILITY_8 + ARMv7-M unused + 0x8 + + + OUTERMOST_SHAREABILITY_9 + ARMv7-M unused + 0x9 + + + OUTERMOST_SHAREABILITY_10 + ARMv7-M unused + 0xA + + + OUTERMOST_SHAREABILITY_11 + ARMv7-M unused + 0xB + + + OUTERMOST_SHAREABILITY_12 + ARMv7-M unused + 0xC + + + OUTERMOST_SHAREABILITY_13 + ARMv7-M unused + 0xD + + + OUTERMOST_SHAREABILITY_14 + ARMv7-M unused + 0xE + + + OUTERMOST_SHAREABILITY_15 + Shareability ignored. + 0xF + + + + + SHAREABILITY_LEVELS + Indicates the number of shareability levels implemented + 12 + 4 + read-only + + + SHAREABILITY_LEVELS_0 + One level of shareability implemented + 0 + + + SHAREABILITY_LEVELS_1 + ARMv7-M unused + 0x1 + + + + + TCM_SUPPORT + Indicates the support for Tightly Coupled Memory + 16 + 4 + read-only + + + TCM_SUPPORT_0 + No tightly coupled memories implemented. + 0 + + + TCM_SUPPORT_1 + Tightly coupled memories implemented with IMPLEMENTATION DEFINED control. + 0x1 + + + TCM_SUPPORT_2 + ARMv7-M unused + 0x2 + + + + + AUXILIARY_REGISTERS + Indicates the support for Auxiliary registers + 20 + 4 + read-only + + + AUXILIARY_REGISTERS_0 + Not supported + 0 + + + AUXILIARY_REGISTERS_1 + Support for Auxiliary Control Register only. + 0x1 + + + AUXILIARY_REGISTERS_2 + ARMv7-M unused + 0x2 + + + + + + + ID_MMFR1 + Memory Model Feature Register 1 + 0xD54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR1 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_MMFR2 + Memory Model Feature Register 2 + 0xD58 + 32 + read-only + 0 + 0xFFFFFFFF + + + WFI_STALL + Indicates the support for Wait For Interrupt (WFI) stalling + 24 + 4 + read-only + + + WFI_STALL_0 + Not supported + 0 + + + WFI_STALL_1 + Support for WFI stalling + 0x1 + + + + + + + ID_MMFR3 + Memory Model Feature Register 3 + 0xD5C + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR3 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_ISAR0 + Instruction Set Attributes Register 0 + 0xD60 + 32 + read-only + 0 + 0xFFFFFFFF + + + BITCOUNT_INSTRS + Indicates the supported Bit Counting instructions + 4 + 4 + read-only + + + BITCOUNT_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITCOUNT_INSTRS_1 + Adds support for the CLZ instruction + 0x1 + + + + + BITFIELD_INSTRS + Indicates the supported BitField instructions + 8 + 4 + read-only + + + BITFIELD_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITFIELD_INSTRS_1 + Adds support for the BFC, BFI, SBFX, and UBFX instructions + 0x1 + + + + + CMPBRANCH_INSTRS + Indicates the supported combined Compare and Branch instructions + 12 + 4 + read-only + + + CMPBRANCH_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + CMPBRANCH_INSTRS_1 + Adds support for the CBNZ and CBZ instructions + 0x1 + + + + + COPROC_INSTRS + Indicates the supported Coprocessor instructions + 16 + 4 + read-only + + + COPROC_INSTRS_0 + None supported, except for separately attributed architectures, for example the Floating-point extension + 0 + + + COPROC_INSTRS_1 + Adds support for generic CDP, LDC, MCR, MRC, and STC instructions + 0x1 + + + COPROC_INSTRS_2 + As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions + 0x2 + + + COPROC_INSTRS_3 + As for 2, and adds support for generic MCRR and MRRC instructions + 0x3 + + + COPROC_INSTRS_4 + As for 3, and adds support for generic MCRR2 and MRRC2 instructions + 0x4 + + + + + DEBUG_INSTRS + Indicates the supported Debug instructions + 20 + 4 + read-only + + + DEBUG_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DEBUG_INSTRS_1 + Adds support for the BKPT instruction + 0x1 + + + + + DIVIDE_INSTRS + Indicates the supported Divide instructions + 24 + 4 + read-only + + + DIVIDE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DIVIDE_INSTRS_1 + Adds support for the SDIV and UDIV instructions + 0x1 + + + + + + + ID_ISAR1 + Instruction Set Attributes Register 1 + 0xD64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EXTEND_INSTRS + Indicates the supported Extend instructions + 12 + 4 + read-only + + + EXTEND_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + EXTEND_INSTRS_1 + Adds support for the SXTB, SXTH, UXTB, and UXTH instructions + 0x1 + + + EXTEND_INSTRS_2 + As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions + 0x2 + + + + + IFTHEN_INSTRS + Indicates the supported IfThen instructions + 16 + 4 + read-only + + + IFTHEN_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IFTHEN_INSTRS_1 + Adds support for the IT instructions, and for the IT bits in the PSRs + 0x1 + + + + + IMMEDIATE_INSTRS + Indicates the support for data-processing instructions with long immediate + 20 + 4 + read-only + + + IMMEDIATE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IMMEDIATE_INSTRS_1 + Adds support for the ADDW, MOVW, MOVT, and SUBW instructions + 0x1 + + + + + INTERWORK_INSTRS + Indicates the supported Interworking instructions + 24 + 4 + read-only + + + INTERWORK_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + INTERWORK_INSTRS_1 + Adds support for the BX instruction, and the T bit in the PSR + 0x1 + + + INTERWORK_INSTRS_2 + As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior + 0x2 + + + INTERWORK_INSTRS_3 + ARMv7-M unused + 0x3 + + + + + + + ID_ISAR2 + Instruction Set Attributes Register 2 + 0xD68 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOADSTORE_INSTRS + Indicates the supported additional load and store instructions + 0 + 4 + read-only + + + LOADSTORE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + LOADSTORE_INSTRS_1 + Adds support for the LDRD and STRD instructions + 0x1 + + + + + MEMHINT_INSTRS + Indicates the supported Memory Hint instructions + 4 + 4 + read-only + + + MEMHINT_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + MEMHINT_INSTRS_1 + Adds support for the PLD instruction, ARMv7-M unused. + 0x1 + + + MEMHINT_INSTRS_2 + As for 1, ARMv7-M unused. + 0x2 + + + MEMHINT_INSTRS_3 + As for 1 or 2, and adds support for the PLI instruction. + 0x3 + + + + + MULTIACCESSINT_INSTRS + Indicates the support for multi-access interruptible instructions + 8 + 4 + read-only + + + MULTIACCESSINT_INSTRS_0 + None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused. + 0 + + + MULTIACCESSINT_INSTRS_1 + LDM and STM instructions are restartable. + 0x1 + + + MULTIACCESSINT_INSTRS_2 + LDM and STM instructions are continuable. + 0x2 + + + + + MULT_INSTRS + Indicates the supported additional Multiply instructions + 12 + 4 + read-only + + + MULT_INSTRS_0 + None supported. This means only MUL is supported. ARMv7-M unused. + 0 + + + MULT_INSTRS_1 + Adds support for the MLA instruction, ARMv7-M unused. + 0x1 + + + MULT_INSTRS_2 + As for 1, and adds support for the MLS instruction. + 0x2 + + + + + MULTS_INSTRS + Indicates the supported advanced signed Multiply instructions + 16 + 4 + read-only + + + MULTS_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTS_INSTRS_1 + Adds support for the SMULL and SMLAL instructions + 0x1 + + + MULTS_INSTRS_2 + As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. + 0x2 + + + MULTS_INSTRS_3 + As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. + 0x3 + + + + + MULTU_INSTRS + Indicates the supported advanced unsigned Multiply instructions + 20 + 4 + read-only + + + MULTU_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTU_INSTRS_1 + Adds support for the UMULL and UMLAL instructions. + 0x1 + + + MULTU_INSTRS_2 + As for 1, and adds support for the UMAAL instruction. + 0x2 + + + + + REVERSAL_INSTRS + Indicates the supported Reversal instructions + 28 + 4 + read-only + + + REVERSAL_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + REVERSAL_INSTRS_1 + Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused. + 0x1 + + + REVERSAL_INSTRS_2 + As for 1, and adds support for the RBIT instruction. + 0x2 + + + + + + + ID_ISAR3 + Instruction Set Attributes Register 3 + 0xD6C + 32 + read-only + 0 + 0xFFFFFFFF + + + SATURATE_INSTRS + Indicates the supported Saturate instructions + 0 + 4 + read-only + + + SATURATE_INSTRS_0 + None supported + 0 + + + SATURATE_INSTRS_1 + Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. + 0x1 + + + + + SIMD_INSTRS + Indicates the supported SIMD instructions + 4 + 4 + read-only + + + SIMD_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SIMD_INSTRS_1 + Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. + 0x1 + + + SIMD_INSTRS_3 + As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. + 0x3 + + + + + SVC_INSTRS + Indicates the supported SVC instructions + 8 + 4 + read-only + + + SVC_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SVC_INSTRS_1 + Adds support for the SVC instruction. + 0x1 + + + + + SYNCHPRIM_INSTRS + Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives + 12 + 4 + read-only + + + TABBRANCH_INSTRS + Indicates the supported Table Branch instructions + 16 + 4 + read-only + + + TABBRANCH_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TABBRANCH_INSTRS_1 + Adds support for the TBB and TBH instructions. + 0x1 + + + + + THUMBCOPY_INSTRS + Indicates the supported non flag-setting MOV instructions + 20 + 4 + read-only + + + THUMBCOPY_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + THUMBCOPY_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + TRUENOP_INSTRS + Indicates the supported non flag-setting MOV instructions + 24 + 4 + read-only + + + TRUENOP_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TRUENOP_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + + + ID_ISAR4 + Instruction Set Attributes Register 4 + 0xD70 + 32 + read-only + 0 + 0xFFFFFFFF + + + UNPRIV_INSTRS + Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. + 0 + 4 + read-only + + + UNPRIV_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + UNPRIV_INSTRS_1 + Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. + 0x1 + + + UNPRIV_INSTRS_2 + As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. + 0x2 + + + + + WITHSHIFTS_INSTRS + Indicates the support for instructions with shifts + 4 + 4 + read-only + + + WITHSHIFTS_INSTRS_0 + Nonzero shifts supported only in MOV and shift instructions. + 0 + + + WITHSHIFTS_INSTRS_1 + Adds support for shifts of loads and stores over the range LSL 0-3. + 0x1 + + + WITHSHIFTS_INSTRS_3 + As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. + 0x3 + + + WITHSHIFTS_INSTRS_4 + ARMv7-M unused. + 0x4 + + + + + WRITEBACK_INSTRS + Indicates the support for Writeback addressing modes + 8 + 4 + read-only + + + WRITEBACK_INSTRS_0 + Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. + 0 + + + WRITEBACK_INSTRS_1 + Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. + 0x1 + + + + + BARRIER_INSTRS + Indicates the supported Barrier instructions + 16 + 4 + read-only + + + BARRIER_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + BARRIER_INSTRS_1 + Adds support for the DMB, DSB, and ISB barrier instructions. + 0x1 + + + + + SYNCHPRIM_INSTRS_FRAC + Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives + 20 + 4 + read-only + + + PSR_M_INSTRS + Indicates the supported M profile instructions to modify the PSRs + 24 + 4 + read-only + + + PSR_M_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + PSR_M_INSTRS_1 + Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. + 0x1 + + + + + + + CLIDR + Cache Level ID register + 0xD78 + 32 + read-only + 0 + 0xFFFFFFFF + + + CL1 + Indicate the type of cache implemented at level 1. + 0 + 3 + read-only + + + CL1_0 + No cache + 0 + + + CL1_1 + Instruction cache only + 0x1 + + + CL1_2 + Data cache only + 0x2 + + + CL1_3 + Separate instruction and data caches + 0x3 + + + CL1_4 + Unified cache + 0x4 + + + + + CL2 + Indicate the type of cache implemented at level 2. + 3 + 3 + read-only + + + CL2_0 + No cache + 0 + + + CL2_1 + Instruction cache only + 0x1 + + + CL2_2 + Data cache only + 0x2 + + + CL2_3 + Separate instruction and data caches + 0x3 + + + CL2_4 + Unified cache + 0x4 + + + + + CL3 + Indicate the type of cache implemented at level 3. + 6 + 3 + read-only + + + CL3_0 + No cache + 0 + + + CL3_1 + Instruction cache only + 0x1 + + + CL3_2 + Data cache only + 0x2 + + + CL3_3 + Separate instruction and data caches + 0x3 + + + CL3_4 + Unified cache + 0x4 + + + + + CL4 + Indicate the type of cache implemented at level 4. + 9 + 3 + read-only + + + CL4_0 + No cache + 0 + + + CL4_1 + Instruction cache only + 0x1 + + + CL4_2 + Data cache only + 0x2 + + + CL4_3 + Separate instruction and data caches + 0x3 + + + CL4_4 + Unified cache + 0x4 + + + + + CL5 + Indicate the type of cache implemented at level 5. + 12 + 3 + read-only + + + CL5_0 + No cache + 0 + + + CL5_1 + Instruction cache only + 0x1 + + + CL5_2 + Data cache only + 0x2 + + + CL5_3 + Separate instruction and data caches + 0x3 + + + CL5_4 + Unified cache + 0x4 + + + + + CL6 + Indicate the type of cache implemented at level 6. + 15 + 3 + read-only + + + CL6_0 + No cache + 0 + + + CL6_1 + Instruction cache only + 0x1 + + + CL6_2 + Data cache only + 0x2 + + + CL6_3 + Separate instruction and data caches + 0x3 + + + CL6_4 + Unified cache + 0x4 + + + + + CL7 + Indicate the type of cache implemented at level 7. + 18 + 3 + read-only + + + CL7_0 + No cache + 0 + + + CL7_1 + Instruction cache only + 0x1 + + + CL7_2 + Data cache only + 0x2 + + + CL7_3 + Separate instruction and data caches + 0x3 + + + CL7_4 + Unified cache + 0x4 + + + + + LOUIS + Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. + 21 + 3 + read-only + + + LOUIS_0 + 0 + 0 + + + LOUIS_1 + 1 + 0x1 + + + LOUIS_2 + 2 + 0x2 + + + LOUIS_3 + 3 + 0x3 + + + LOUIS_4 + 4 + 0x4 + + + LOUIS_5 + 5 + 0x5 + + + LOUIS_6 + 6 + 0x6 + + + LOUIS_7 + 7 + 0x7 + + + + + LOC + Level of Coherency for the cache hierarchy + 24 + 3 + read-only + + + LOC_0 + 0 + 0 + + + LOC_1 + 1 + 0x1 + + + LOC_2 + 2 + 0x2 + + + LOC_3 + 3 + 0x3 + + + LOC_4 + 4 + 0x4 + + + LOC_5 + 5 + 0x5 + + + LOC_6 + 6 + 0x6 + + + LOC_7 + 7 + 0x7 + + + + + LOU + Level of Unification for the cache hierarchy + 27 + 3 + read-only + + + LOU_0 + 0 + 0 + + + LOU_1 + 1 + 0x1 + + + LOU_2 + 2 + 0x2 + + + LOU_3 + 3 + 0x3 + + + LOU_4 + 4 + 0x4 + + + LOU_5 + 5 + 0x5 + + + LOU_6 + 6 + 0x6 + + + LOU_7 + 7 + 0x7 + + + + + + + CTR + Cache Type register + 0xD7C + 32 + read-only + 0x8000C000 + 0xFFFFFFFF + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. + 0 + 4 + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. + 16 + 4 + read-only + + + ERG + Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words. + 20 + 4 + read-only + + + CWG + Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words. + 24 + 4 + read-only + + + FORMAT + Indicates the implemented CTR format. + 29 + 3 + read-only + + + FORMAT_4 + ARMv7 format. + 0x4 + + + + + + + CCSIDR + Cache Size ID Register + 0xD80 + 32 + read-only + 0 + 0xFFFFFFFF + + + LINESIZE + (Log2(Number of words in cache line)) - 2. + 0 + 3 + read-only + + + LINESIZE_0 + The line length of 4 words. + 0 + + + LINESIZE_1 + The line length of 8 words. + 0x1 + + + LINESIZE_2 + The line length of 16 words. + 0x2 + + + LINESIZE_3 + The line length of 32 words. + 0x3 + + + LINESIZE_4 + The line length of 64 words. + 0x4 + + + LINESIZE_5 + The line length of 128 words. + 0x5 + + + LINESIZE_6 + The line length of 256 words. + 0x6 + + + LINESIZE_7 + The line length of 512 words. + 0x7 + + + + + ASSOCIATIVITY + (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. + 3 + 10 + read-only + + + NUMSETS + (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. + 13 + 15 + read-only + + + WA + Indicates whether the cache level supports write-allocation + 28 + 1 + read-only + + + WA_0 + Feature not supported + 0 + + + WA_1 + Feature supported + 0x1 + + + + + RA + Indicates whether the cache level supports read-allocation + 29 + 1 + read-only + + + RA_0 + Feature not supported + 0 + + + RA_1 + Feature supported + 0x1 + + + + + WB + Indicates whether the cache level supports write-back + 30 + 1 + read-only + + + WB_0 + Feature not supported + 0 + + + WB_1 + Feature supported + 0x1 + + + + + WT + Indicates whether the cache level supports write-through + 31 + 1 + read-only + + + WT_0 + Feature not supported + 0 + + + WT_1 + Feature supported + 0x1 + + + + + + + CSSELR + Cache Size Selection Register + 0xD84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IND + Instruction not data bit + 0 + 1 + read-write + + + IND_0 + Data or unified cache. + 0 + + + IND_1 + Instruction cache. + 0x1 + + + + + LEVEL + Cache level of required cache + 1 + 3 + read-write + + + LEVEL_0 + Level 1 cache. + 0 + + + LEVEL_1 + Level 2 cache. + 0x1 + + + LEVEL_2 + Level 3 cache. + 0x2 + + + LEVEL_3 + Level 4 cache. + 0x3 + + + LEVEL_4 + Level 5 cache. + 0x4 + + + LEVEL_5 + Level 6 cache. + 0x5 + + + LEVEL_6 + Level 7 cache. + 0x6 + + + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CP0 + Access privileges for coprocessor 0. + 0 + 2 + read-write + + + CP0_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP0_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP0_3 + Full access. + 0x3 + + + + + CP1 + Access privileges for coprocessor 1. + 2 + 2 + read-write + + + CP1_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP1_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP1_3 + Full access. + 0x3 + + + + + CP2 + Access privileges for coprocessor 2. + 4 + 2 + read-write + + + CP2_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP2_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP2_3 + Full access. + 0x3 + + + + + CP3 + Access privileges for coprocessor 3. + 6 + 2 + read-write + + + CP3_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP3_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP3_3 + Full access. + 0x3 + + + + + CP4 + Access privileges for coprocessor 4. + 8 + 2 + read-write + + + CP4_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP4_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP4_3 + Full access. + 0x3 + + + + + CP5 + Access privileges for coprocessor 5. + 10 + 2 + read-write + + + CP5_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP5_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP5_3 + Full access. + 0x3 + + + + + CP6 + Access privileges for coprocessor 6. + 12 + 2 + read-write + + + CP6_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP6_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP6_3 + Full access. + 0x3 + + + + + CP7 + Access privileges for coprocessor 7. + 14 + 2 + read-write + + + CP7_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP7_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP7_3 + Full access. + 0x3 + + + + + CP10 + Access privileges for coprocessor 10. + 20 + 2 + read-write + + + CP10_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP10_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP10_3 + Full access. + 0x3 + + + + + CP11 + Access privileges for coprocessor 11. + 22 + 2 + read-write + + + CP11_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP11_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP11_3 + Full access. + 0x3 + + + + + + + STIR + Instruction cache invalidate all to Point of Unification (PoU) + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Indicates the interrupt to be triggered + 0 + 9 + write-only + + + + + ICIALLU + Instruction cache invalidate all to Point of Unification (PoU) + 0xF50 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIALLU + I-cache invalidate all to PoU + 0 + 32 + write-only + + + + + ICIMVAU + Instruction cache invalidate by address to PoU + 0xF58 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIMVAU + I-cache invalidate by MVA to PoU + 0 + 32 + write-only + + + + + DCIMVAC + Data cache invalidate by address to Point of Coherency (PoC) + 0xF5C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCIMVAC + D-cache invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCISW + Data cache invalidate by set/way + 0xF60 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCISW + D-cache invalidate by set-way + 0 + 32 + write-only + + + + + DCCMVAU + Data cache by address to PoU + 0xF64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAU + D-cache clean by MVA to PoU + 0 + 32 + write-only + + + + + DCCMVAC + Data cache clean by address to PoC + 0xF68 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAC + D-cache clean by MVA to PoC + 0 + 32 + write-only + + + + + DCCSW + Data cache clean by set/way + 0xF6C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCSW + D-cache clean by set-way + 0 + 32 + write-only + + + + + DCCIMVAC + Data cache clean and invalidate by address to PoC + 0xF70 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCIMVAC + D-cache clean and invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCCISW + Data cache clean and invalidate by set/way + 0xF74 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCISW + D-cache clean and invalidate by set-way + 0 + 32 + write-only + + + + + CM7_ITCMCR + Instruction Tightly-Coupled Memory Control Register + 0xF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_DTCMCR + Data Tightly-Coupled Memory Control Register + 0xF94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_AHBPCR + AHBP Control Register + 0xF98 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + AHBP enable. + 0 + 1 + read-write + + + EN_0 + AHBP disabled. When disabled all accesses are made to the AXIM interface. + 0 + + + EN_1 + AHBP enabled. + 0x1 + + + + + SZ + AHBP size. + 1 + 3 + read-only + + + SZ_0 + 0MB. AHBP disabled. + 0 + + + SZ_1 + 64MB. + 0x1 + + + SZ_2 + 128MB. + 0x2 + + + SZ_3 + 256MB. + 0x3 + + + SZ_4 + 512MB. + 0x4 + + + + + + + CM7_CACR + L1 Cache Control Register + 0xF9C + 32 + read-write + 0 + 0xFFFFFFFF + + + SIWT + Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. + 0 + 1 + read-write + + + SIWT_0 + Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. + 0 + + + SIWT_1 + Normal Cacheable shared locations are treated as Write-Through. + 0x1 + + + + + ECCDIS + Enables ECC in the instruction and data cache. + 1 + 1 + read-write + + + ECCDIS_0 + Enables ECC in the instruction and data cache. + 0 + + + ECCDIS_1 + Disables ECC in the instruction and data cache. + 0x1 + + + + + FORCEWT + Enables Force Write-Through in the data cache. + 2 + 1 + read-write + + + FORCEWT_0 + Disables Force Write-Through. + 0 + + + FORCEWT_1 + Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. + 0x1 + + + + + + + CM7_AHBSCR + AHB Slave Control Register + 0xFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTL + AHBS prioritization control. + 0 + 2 + read-write + + + CTL_0 + AHBS access priority demoted. This is the reset value. + 0 + + + CTL_1 + Software access priority demoted. + 0x1 + + + CTL_2 + AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI]. + 0x2 + + + CTL_3 + AHBSPRI signal has control of access priority. + 0x3 + + + + + TPRI + Threshold execution priority for AHBS traffic demotion. + 2 + 9 + read-write + + + INITCOUNT + Fairness counter initialization value. + 11 + 5 + read-write + + + + + CM7_ABFSR + Auxiliary Bus Fault Status Register + 0xFA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM + Asynchronous fault on ITCM interface. + 0 + 1 + read-write + + + DTCM + Asynchronous fault on DTCM interface. + 1 + 1 + read-write + + + AHBP + Asynchronous fault on AHBP interface. + 2 + 1 + read-write + + + AXIM + Asynchronous fault on AXIM interface. + 3 + 1 + read-write + + + EPPB + Asynchronous fault on EPPB interface. + 4 + 1 + read-write + + + AXIMTYPE + Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1. + 8 + 2 + read-write + + + AXIMTYPE_0 + OKAY. + 0 + + + AXIMTYPE_1 + EXOKAY. + 0x1 + + + AXIMTYPE_2 + SLVERR. + 0x2 + + + AXIMTYPE_3 + DECERR. + 0x3 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + CTI0_ERROR + 17 + + + CTI1_ERROR + 18 + + + CORE + 19 + + + LPUART1 + 20 + + + LPUART2 + 21 + + + LPUART3 + 22 + + + LPUART4 + 23 + + + LPUART5 + 24 + + + LPUART6 + 25 + + + LPUART7 + 26 + + + LPUART8 + 27 + + + LPI2C1 + 28 + + + LPI2C2 + 29 + + + LPI2C3 + 30 + + + LPI2C4 + 31 + + + LPSPI1 + 32 + + + LPSPI2 + 33 + + + LPSPI3 + 34 + + + LPSPI4 + 35 + + + CAN1 + 36 + + + CAN2 + 37 + + + FLEXRAM + 38 + + + KPP + 39 + + + TSC_DIG + 40 + + + GPR_IRQ + 41 + + + LCDIF + 42 + + + CSI + 43 + + + PXP + 44 + + + WDOG2 + 45 + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + CSU + 49 + + + DCP + 50 + + + DCP_VMI + 51 + + + Reserved68 + 52 + + + TRNG + 53 + + + SJC + 54 + + + BEE + 55 + + + SAI1 + 56 + + + SAI2 + 57 + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + SPDIF + 60 + + + ANATOP_EVENT0 + 61 + + + ANATOP_EVENT1 + 62 + + + ANATOP_TAMP_LOW_HIGH + 63 + + + ANATOP_TEMP_PANIC + 64 + + + USB_PHY1 + 65 + + + USB_PHY2 + 66 + + + ADC1 + 67 + + + ADC2 + 68 + + + DCDC + 69 + + + Reserved86 + 70 + + + Reserved87 + 71 + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + GPIO4_Combined_0_15 + 86 + + + GPIO4_Combined_16_31 + 87 + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + FLEXIO1 + 90 + + + FLEXIO2 + 91 + + + WDOG1 + 92 + + + RTWDOG + 93 + + + EWM + 94 + + + CCM_1 + 95 + + + CCM_2 + 96 + + + GPC + 97 + + + SRC + 98 + + + Reserved115 + 99 + + + GPT1 + 100 + + + GPT2 + 101 + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + Reserved123 + 107 + + + SEMC + 109 + + + USDHC1 + 110 + + + USDHC2 + 111 + + + USB_OTG2 + 112 + + + USB_OTG1 + 113 + + + ENET + 114 + + + ENET_1588_Timer + 115 + + + XBAR1_IRQ_0_1 + 116 + + + XBAR1_IRQ_2_3 + 117 + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + PIT + 122 + + + ACMP1 + 123 + + + ACMP2 + 124 + + + ACMP3 + 125 + + + ACMP4 + 126 + + + Reserved143 + 127 + + + Reserved144 + 128 + + + ENC1 + 129 + + + ENC2 + 130 + + + ENC3 + 131 + + + ENC4 + 132 + + + TMR1 + 133 + + + TMR2 + 134 + + + TMR3 + 135 + + + TMR4 + 136 + + + PWM2_0 + 137 + + + PWM2_1 + 138 + + + PWM2_2 + 139 + + + PWM2_3 + 140 + + + PWM2_FAULT + 141 + + + PWM3_0 + 142 + + + PWM3_1 + 143 + + + PWM3_2 + 144 + + + PWM3_3 + 145 + + + PWM3_FAULT + 146 + + + PWM4_0 + 147 + + + PWM4_1 + 148 + + + PWM4_2 + 149 + + + PWM4_3 + 150 + + + PWM4_FAULT + 151 + + + Reserved168 + 152 + + + Reserved169 + 153 + + + Reserved170 + 154 + + + Reserved171 + 155 + + + Reserved172 + 156 + + + Reserved173 + 157 + + + SJC_ARM_DEBUG + 158 + + + NMI_WAKEUP + 159 + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER4 + Interrupt Set Enable Register n + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER4 + Interrupt Clear Enable Register n + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR4 + Interrupt Set Pending Register n + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR4 + Interrupt Clear Pending Register n + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR4 + Interrupt Active bit Register n + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register 0 + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of the INT_DMA0_DMA16 interrupt 0 + 4 + 4 + read-write + + + + + NVICIP1 + Interrupt Priority Register 1 + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of the INT_DMA1_DMA17 interrupt 1 + 4 + 4 + read-write + + + + + NVICIP2 + Interrupt Priority Register 2 + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of the INT_DMA2_DMA18 interrupt 2 + 4 + 4 + read-write + + + + + NVICIP3 + Interrupt Priority Register 3 + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of the INT_DMA3_DMA19 interrupt 3 + 4 + 4 + read-write + + + + + NVICIP4 + Interrupt Priority Register 4 + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of the INT_DMA4_DMA20 interrupt 4 + 4 + 4 + read-write + + + + + NVICIP5 + Interrupt Priority Register 5 + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of the INT_DMA5_DMA21 interrupt 5 + 4 + 4 + read-write + + + + + NVICIP6 + Interrupt Priority Register 6 + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of the INT_DMA6_DMA22 interrupt 6 + 4 + 4 + read-write + + + + + NVICIP7 + Interrupt Priority Register 7 + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of the INT_DMA7_DMA23 interrupt 7 + 4 + 4 + read-write + + + + + NVICIP8 + Interrupt Priority Register 8 + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of the INT_DMA8_DMA24 interrupt 8 + 4 + 4 + read-write + + + + + NVICIP9 + Interrupt Priority Register 9 + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of the INT_DMA9_DMA25 interrupt 9 + 4 + 4 + read-write + + + + + NVICIP10 + Interrupt Priority Register 10 + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of the INT_DMA10_DMA26 interrupt 10 + 4 + 4 + read-write + + + + + NVICIP11 + Interrupt Priority Register 11 + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of the INT_DMA11_DMA27 interrupt 11 + 4 + 4 + read-write + + + + + NVICIP12 + Interrupt Priority Register 12 + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of the INT_DMA12_DMA28 interrupt 12 + 4 + 4 + read-write + + + + + NVICIP13 + Interrupt Priority Register 13 + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of the INT_DMA13_DMA29 interrupt 13 + 4 + 4 + read-write + + + + + NVICIP14 + Interrupt Priority Register 14 + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of the INT_DMA14_DMA30 interrupt 14 + 4 + 4 + read-write + + + + + NVICIP15 + Interrupt Priority Register 15 + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of the INT_DMA15_DMA31 interrupt 15 + 4 + 4 + read-write + + + + + NVICIP16 + Interrupt Priority Register 16 + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of the INT_DMA_ERROR interrupt 16 + 4 + 4 + read-write + + + + + NVICIP17 + Interrupt Priority Register 17 + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of the INT_CTI0_ERROR interrupt 17 + 4 + 4 + read-write + + + + + NVICIP18 + Interrupt Priority Register 18 + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of the INT_CTI1_ERROR interrupt 18 + 4 + 4 + read-write + + + + + NVICIP19 + Interrupt Priority Register 19 + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of the INT_CORE interrupt 19 + 4 + 4 + read-write + + + + + NVICIP20 + Interrupt Priority Register 20 + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of the INT_LPUART1 interrupt 20 + 4 + 4 + read-write + + + + + NVICIP21 + Interrupt Priority Register 21 + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of the INT_LPUART2 interrupt 21 + 4 + 4 + read-write + + + + + NVICIP22 + Interrupt Priority Register 22 + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of the INT_LPUART3 interrupt 22 + 4 + 4 + read-write + + + + + NVICIP23 + Interrupt Priority Register 23 + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of the INT_LPUART4 interrupt 23 + 4 + 4 + read-write + + + + + NVICIP24 + Interrupt Priority Register 24 + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of the INT_LPUART5 interrupt 24 + 4 + 4 + read-write + + + + + NVICIP25 + Interrupt Priority Register 25 + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of the INT_LPUART6 interrupt 25 + 4 + 4 + read-write + + + + + NVICIP26 + Interrupt Priority Register 26 + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of the INT_LPUART7 interrupt 26 + 4 + 4 + read-write + + + + + NVICIP27 + Interrupt Priority Register 27 + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of the INT_LPUART8 interrupt 27 + 4 + 4 + read-write + + + + + NVICIP28 + Interrupt Priority Register 28 + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of the INT_LPI2C1 interrupt 28 + 4 + 4 + read-write + + + + + NVICIP29 + Interrupt Priority Register 29 + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of the INT_LPI2C2 interrupt 29 + 4 + 4 + read-write + + + + + NVICIP30 + Interrupt Priority Register 30 + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of the INT_LPI2C3 interrupt 30 + 4 + 4 + read-write + + + + + NVICIP31 + Interrupt Priority Register 31 + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of the INT_LPI2C4 interrupt 31 + 4 + 4 + read-write + + + + + NVICIP32 + Interrupt Priority Register 32 + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of the INT_LPSPI1 interrupt 32 + 4 + 4 + read-write + + + + + NVICIP33 + Interrupt Priority Register 33 + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of the INT_LPSPI2 interrupt 33 + 4 + 4 + read-write + + + + + NVICIP34 + Interrupt Priority Register 34 + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of the INT_LPSPI3 interrupt 34 + 4 + 4 + read-write + + + + + NVICIP35 + Interrupt Priority Register 35 + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of the INT_LPSPI4 interrupt 35 + 4 + 4 + read-write + + + + + NVICIP36 + Interrupt Priority Register 36 + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of the INT_CAN1 interrupt 36 + 4 + 4 + read-write + + + + + NVICIP37 + Interrupt Priority Register 37 + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of the INT_CAN2 interrupt 37 + 4 + 4 + read-write + + + + + NVICIP38 + Interrupt Priority Register 38 + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of the INT_FLEXRAM interrupt 38 + 4 + 4 + read-write + + + + + NVICIP39 + Interrupt Priority Register 39 + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of the INT_KPP interrupt 39 + 4 + 4 + read-write + + + + + NVICIP40 + Interrupt Priority Register 40 + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of the INT_TSC_DIG interrupt 40 + 4 + 4 + read-write + + + + + NVICIP41 + Interrupt Priority Register 41 + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of the INT_GPR_IRQ interrupt 41 + 4 + 4 + read-write + + + + + NVICIP42 + Interrupt Priority Register 42 + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of the INT_LCDIF interrupt 42 + 4 + 4 + read-write + + + + + NVICIP43 + Interrupt Priority Register 43 + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of the INT_CSI interrupt 43 + 4 + 4 + read-write + + + + + NVICIP44 + Interrupt Priority Register 44 + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of the INT_PXP interrupt 44 + 4 + 4 + read-write + + + + + NVICIP45 + Interrupt Priority Register 45 + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of the INT_WDOG2 interrupt 45 + 4 + 4 + read-write + + + + + NVICIP46 + Interrupt Priority Register 46 + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of the INT_SNVS_HP_WRAPPER interrupt 46 + 4 + 4 + read-write + + + + + NVICIP47 + Interrupt Priority Register 47 + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of the INT_SNVS_HP_WRAPPER_TZ interrupt 47 + 4 + 4 + read-write + + + + + NVICIP48 + Interrupt Priority Register 48 + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of the INT_SNVS_LP_WRAPPER interrupt 48 + 4 + 4 + read-write + + + + + NVICIP49 + Interrupt Priority Register 49 + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of the INT_CSU interrupt 49 + 4 + 4 + read-write + + + + + NVICIP50 + Interrupt Priority Register 50 + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of the INT_DCP interrupt 50 + 4 + 4 + read-write + + + + + NVICIP51 + Interrupt Priority Register 51 + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of the INT_DCP_VMI interrupt 51 + 4 + 4 + read-write + + + + + NVICIP52 + Interrupt Priority Register 52 + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of the INT_Reserved68 interrupt 52 + 4 + 4 + read-write + + + + + NVICIP53 + Interrupt Priority Register 53 + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of the INT_TRNG interrupt 53 + 4 + 4 + read-write + + + + + NVICIP54 + Interrupt Priority Register 54 + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of the INT_SJC interrupt 54 + 4 + 4 + read-write + + + + + NVICIP55 + Interrupt Priority Register 55 + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of the INT_BEE interrupt 55 + 4 + 4 + read-write + + + + + NVICIP56 + Interrupt Priority Register 56 + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of the INT_SAI1 interrupt 56 + 4 + 4 + read-write + + + + + NVICIP57 + Interrupt Priority Register 57 + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of the INT_SAI2 interrupt 57 + 4 + 4 + read-write + + + + + NVICIP58 + Interrupt Priority Register 58 + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of the INT_SAI3_RX interrupt 58 + 4 + 4 + read-write + + + + + NVICIP59 + Interrupt Priority Register 59 + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of the INT_SAI3_TX interrupt 59 + 4 + 4 + read-write + + + + + NVICIP60 + Interrupt Priority Register 60 + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of the INT_SPDIF interrupt 60 + 4 + 4 + read-write + + + + + NVICIP61 + Interrupt Priority Register 61 + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of the INT_ANATOP_EVENT0 interrupt 61 + 4 + 4 + read-write + + + + + NVICIP62 + Interrupt Priority Register 62 + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of the INT_ANATOP_EVENT1 interrupt 62 + 4 + 4 + read-write + + + + + NVICIP63 + Interrupt Priority Register 63 + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of the INT_ANATOP_TAMP_LOW_HIGH interrupt 63 + 4 + 4 + read-write + + + + + NVICIP64 + Interrupt Priority Register 64 + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of the INT_ANATOP_TEMP_PANIC interrupt 64 + 4 + 4 + read-write + + + + + NVICIP65 + Interrupt Priority Register 65 + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of the INT_USB_PHY1 interrupt 65 + 4 + 4 + read-write + + + + + NVICIP66 + Interrupt Priority Register 66 + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of the INT_USB_PHY2 interrupt 66 + 4 + 4 + read-write + + + + + NVICIP67 + Interrupt Priority Register 67 + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of the INT_ADC1 interrupt 67 + 4 + 4 + read-write + + + + + NVICIP68 + Interrupt Priority Register 68 + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of the INT_ADC2 interrupt 68 + 4 + 4 + read-write + + + + + NVICIP69 + Interrupt Priority Register 69 + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of the INT_DCDC interrupt 69 + 4 + 4 + read-write + + + + + NVICIP70 + Interrupt Priority Register 70 + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of the INT_Reserved86 interrupt 70 + 4 + 4 + read-write + + + + + NVICIP71 + Interrupt Priority Register 71 + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of the INT_Reserved87 interrupt 71 + 4 + 4 + read-write + + + + + NVICIP72 + Interrupt Priority Register 72 + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of the INT_GPIO1_INT0 interrupt 72 + 4 + 4 + read-write + + + + + NVICIP73 + Interrupt Priority Register 73 + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of the INT_GPIO1_INT1 interrupt 73 + 4 + 4 + read-write + + + + + NVICIP74 + Interrupt Priority Register 74 + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of the INT_GPIO1_INT2 interrupt 74 + 4 + 4 + read-write + + + + + NVICIP75 + Interrupt Priority Register 75 + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of the INT_GPIO1_INT3 interrupt 75 + 4 + 4 + read-write + + + + + NVICIP76 + Interrupt Priority Register 76 + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of the INT_GPIO1_INT4 interrupt 76 + 4 + 4 + read-write + + + + + NVICIP77 + Interrupt Priority Register 77 + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of the INT_GPIO1_INT5 interrupt 77 + 4 + 4 + read-write + + + + + NVICIP78 + Interrupt Priority Register 78 + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of the INT_GPIO1_INT6 interrupt 78 + 4 + 4 + read-write + + + + + NVICIP79 + Interrupt Priority Register 79 + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of the INT_GPIO1_INT7 interrupt 79 + 4 + 4 + read-write + + + + + NVICIP80 + Interrupt Priority Register 80 + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of the INT_GPIO1_Combined_0_15 interrupt 80 + 4 + 4 + read-write + + + + + NVICIP81 + Interrupt Priority Register 81 + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of the INT_GPIO1_Combined_16_31 interrupt 81 + 4 + 4 + read-write + + + + + NVICIP82 + Interrupt Priority Register 82 + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of the INT_GPIO2_Combined_0_15 interrupt 82 + 4 + 4 + read-write + + + + + NVICIP83 + Interrupt Priority Register 83 + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of the INT_GPIO2_Combined_16_31 interrupt 83 + 4 + 4 + read-write + + + + + NVICIP84 + Interrupt Priority Register 84 + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of the INT_GPIO3_Combined_0_15 interrupt 84 + 4 + 4 + read-write + + + + + NVICIP85 + Interrupt Priority Register 85 + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of the INT_GPIO3_Combined_16_31 interrupt 85 + 4 + 4 + read-write + + + + + NVICIP86 + Interrupt Priority Register 86 + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of the INT_GPIO4_Combined_0_15 interrupt 86 + 4 + 4 + read-write + + + + + NVICIP87 + Interrupt Priority Register 87 + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of the INT_GPIO4_Combined_16_31 interrupt 87 + 4 + 4 + read-write + + + + + NVICIP88 + Interrupt Priority Register 88 + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of the INT_GPIO5_Combined_0_15 interrupt 88 + 4 + 4 + read-write + + + + + NVICIP89 + Interrupt Priority Register 89 + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of the INT_GPIO5_Combined_16_31 interrupt 89 + 4 + 4 + read-write + + + + + NVICIP90 + Interrupt Priority Register 90 + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of the INT_FLEXIO1 interrupt 90 + 4 + 4 + read-write + + + + + NVICIP91 + Interrupt Priority Register 91 + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of the INT_FLEXIO2 interrupt 91 + 4 + 4 + read-write + + + + + NVICIP92 + Interrupt Priority Register 92 + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of the INT_WDOG1 interrupt 92 + 4 + 4 + read-write + + + + + NVICIP93 + Interrupt Priority Register 93 + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of the INT_RTWDOG interrupt 93 + 4 + 4 + read-write + + + + + NVICIP94 + Interrupt Priority Register 94 + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of the INT_EWM interrupt 94 + 4 + 4 + read-write + + + + + NVICIP95 + Interrupt Priority Register 95 + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of the INT_CCM_1 interrupt 95 + 4 + 4 + read-write + + + + + NVICIP96 + Interrupt Priority Register 96 + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of the INT_CCM_2 interrupt 96 + 4 + 4 + read-write + + + + + NVICIP97 + Interrupt Priority Register 97 + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of the INT_GPC interrupt 97 + 4 + 4 + read-write + + + + + NVICIP98 + Interrupt Priority Register 98 + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of the INT_SRC interrupt 98 + 4 + 4 + read-write + + + + + NVICIP99 + Interrupt Priority Register 99 + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of the INT_Reserved115 interrupt 99 + 4 + 4 + read-write + + + + + NVICIP100 + Interrupt Priority Register 100 + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of the INT_GPT1 interrupt 100 + 4 + 4 + read-write + + + + + NVICIP101 + Interrupt Priority Register 101 + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of the INT_GPT2 interrupt 101 + 4 + 4 + read-write + + + + + NVICIP102 + Interrupt Priority Register 102 + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of the INT_PWM1_0 interrupt 102 + 4 + 4 + read-write + + + + + NVICIP103 + Interrupt Priority Register 103 + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of the INT_PWM1_1 interrupt 103 + 4 + 4 + read-write + + + + + NVICIP104 + Interrupt Priority Register 104 + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of the INT_PWM1_2 interrupt 104 + 4 + 4 + read-write + + + + + NVICIP105 + Interrupt Priority Register 105 + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of the INT_PWM1_3 interrupt 105 + 4 + 4 + read-write + + + + + NVICIP106 + Interrupt Priority Register 106 + 0x36A + 8 + read-write + 0 + 0xFF + + + PRI106 + Priority of the INT_PWM1_FAULT interrupt 106 + 4 + 4 + read-write + + + + + NVICIP107 + Interrupt Priority Register 107 + 0x36B + 8 + read-write + 0 + 0xFF + + + PRI107 + Priority of the INT_Reserved123 interrupt 107 + 4 + 4 + read-write + + + + + NVICIP108 + Interrupt Priority Register 108 + 0x36C + 8 + read-write + 0 + 0xFF + + + PRI108 + Priority of interrupt 108 + 4 + 4 + read-write + + + + + NVICIP109 + Interrupt Priority Register 109 + 0x36D + 8 + read-write + 0 + 0xFF + + + PRI109 + Priority of the INT_SEMC interrupt 109 + 4 + 4 + read-write + + + + + NVICIP110 + Interrupt Priority Register 110 + 0x36E + 8 + read-write + 0 + 0xFF + + + PRI110 + Priority of the INT_USDHC1 interrupt 110 + 4 + 4 + read-write + + + + + NVICIP111 + Interrupt Priority Register 111 + 0x36F + 8 + read-write + 0 + 0xFF + + + PRI111 + Priority of the INT_USDHC2 interrupt 111 + 4 + 4 + read-write + + + + + NVICIP112 + Interrupt Priority Register 112 + 0x370 + 8 + read-write + 0 + 0xFF + + + PRI112 + Priority of the INT_USB_OTG2 interrupt 112 + 4 + 4 + read-write + + + + + NVICIP113 + Interrupt Priority Register 113 + 0x371 + 8 + read-write + 0 + 0xFF + + + PRI113 + Priority of the INT_USB_OTG1 interrupt 113 + 4 + 4 + read-write + + + + + NVICIP114 + Interrupt Priority Register 114 + 0x372 + 8 + read-write + 0 + 0xFF + + + PRI114 + Priority of the INT_ENET interrupt 114 + 4 + 4 + read-write + + + + + NVICIP115 + Interrupt Priority Register 115 + 0x373 + 8 + read-write + 0 + 0xFF + + + PRI115 + Priority of the INT_ENET_1588_Timer interrupt 115 + 4 + 4 + read-write + + + + + NVICIP116 + Interrupt Priority Register 116 + 0x374 + 8 + read-write + 0 + 0xFF + + + PRI116 + Priority of the INT_XBAR1_IRQ_0_1 interrupt 116 + 4 + 4 + read-write + + + + + NVICIP117 + Interrupt Priority Register 117 + 0x375 + 8 + read-write + 0 + 0xFF + + + PRI117 + Priority of the INT_XBAR1_IRQ_2_3 interrupt 117 + 4 + 4 + read-write + + + + + NVICIP118 + Interrupt Priority Register 118 + 0x376 + 8 + read-write + 0 + 0xFF + + + PRI118 + Priority of the INT_ADC_ETC_IRQ0 interrupt 118 + 4 + 4 + read-write + + + + + NVICIP119 + Interrupt Priority Register 119 + 0x377 + 8 + read-write + 0 + 0xFF + + + PRI119 + Priority of the INT_ADC_ETC_IRQ1 interrupt 119 + 4 + 4 + read-write + + + + + NVICIP120 + Interrupt Priority Register 120 + 0x378 + 8 + read-write + 0 + 0xFF + + + PRI120 + Priority of the INT_ADC_ETC_IRQ2 interrupt 120 + 4 + 4 + read-write + + + + + NVICIP121 + Interrupt Priority Register 121 + 0x379 + 8 + read-write + 0 + 0xFF + + + PRI121 + Priority of the INT_ADC_ETC_ERROR_IRQ interrupt 121 + 4 + 4 + read-write + + + + + NVICIP122 + Interrupt Priority Register 122 + 0x37A + 8 + read-write + 0 + 0xFF + + + PRI122 + Priority of the INT_PIT interrupt 122 + 4 + 4 + read-write + + + + + NVICIP123 + Interrupt Priority Register 123 + 0x37B + 8 + read-write + 0 + 0xFF + + + PRI123 + Priority of the INT_ACMP1 interrupt 123 + 4 + 4 + read-write + + + + + NVICIP124 + Interrupt Priority Register 124 + 0x37C + 8 + read-write + 0 + 0xFF + + + PRI124 + Priority of the INT_ACMP2 interrupt 124 + 4 + 4 + read-write + + + + + NVICIP125 + Interrupt Priority Register 125 + 0x37D + 8 + read-write + 0 + 0xFF + + + PRI125 + Priority of the INT_ACMP3 interrupt 125 + 4 + 4 + read-write + + + + + NVICIP126 + Interrupt Priority Register 126 + 0x37E + 8 + read-write + 0 + 0xFF + + + PRI126 + Priority of the INT_ACMP4 interrupt 126 + 4 + 4 + read-write + + + + + NVICIP127 + Interrupt Priority Register 127 + 0x37F + 8 + read-write + 0 + 0xFF + + + PRI127 + Priority of the INT_Reserved143 interrupt 127 + 4 + 4 + read-write + + + + + NVICIP128 + Interrupt Priority Register 128 + 0x380 + 8 + read-write + 0 + 0xFF + + + PRI128 + Priority of the INT_Reserved144 interrupt 128 + 4 + 4 + read-write + + + + + NVICIP129 + Interrupt Priority Register 129 + 0x381 + 8 + read-write + 0 + 0xFF + + + PRI129 + Priority of the INT_ENC1 interrupt 129 + 4 + 4 + read-write + + + + + NVICIP130 + Interrupt Priority Register 130 + 0x382 + 8 + read-write + 0 + 0xFF + + + PRI130 + Priority of the INT_ENC2 interrupt 130 + 4 + 4 + read-write + + + + + NVICIP131 + Interrupt Priority Register 131 + 0x383 + 8 + read-write + 0 + 0xFF + + + PRI131 + Priority of the INT_ENC3 interrupt 131 + 4 + 4 + read-write + + + + + NVICIP132 + Interrupt Priority Register 132 + 0x384 + 8 + read-write + 0 + 0xFF + + + PRI132 + Priority of the INT_ENC4 interrupt 132 + 4 + 4 + read-write + + + + + NVICIP133 + Interrupt Priority Register 133 + 0x385 + 8 + read-write + 0 + 0xFF + + + PRI133 + Priority of the INT_TMR1 interrupt 133 + 4 + 4 + read-write + + + + + NVICIP134 + Interrupt Priority Register 134 + 0x386 + 8 + read-write + 0 + 0xFF + + + PRI134 + Priority of the INT_TMR2 interrupt 134 + 4 + 4 + read-write + + + + + NVICIP135 + Interrupt Priority Register 135 + 0x387 + 8 + read-write + 0 + 0xFF + + + PRI135 + Priority of the INT_TMR3 interrupt 135 + 4 + 4 + read-write + + + + + NVICIP136 + Interrupt Priority Register 136 + 0x388 + 8 + read-write + 0 + 0xFF + + + PRI136 + Priority of the INT_TMR4 interrupt 136 + 4 + 4 + read-write + + + + + NVICIP137 + Interrupt Priority Register 137 + 0x389 + 8 + read-write + 0 + 0xFF + + + PRI137 + Priority of the INT_PWM2_0 interrupt 137 + 4 + 4 + read-write + + + + + NVICIP138 + Interrupt Priority Register 138 + 0x38A + 8 + read-write + 0 + 0xFF + + + PRI138 + Priority of the INT_PWM2_1 interrupt 138 + 4 + 4 + read-write + + + + + NVICIP139 + Interrupt Priority Register 139 + 0x38B + 8 + read-write + 0 + 0xFF + + + PRI139 + Priority of the INT_PWM2_2 interrupt 139 + 4 + 4 + read-write + + + + + NVICIP140 + Interrupt Priority Register 140 + 0x38C + 8 + read-write + 0 + 0xFF + + + PRI140 + Priority of the INT_PWM2_3 interrupt 140 + 4 + 4 + read-write + + + + + NVICIP141 + Interrupt Priority Register 141 + 0x38D + 8 + read-write + 0 + 0xFF + + + PRI141 + Priority of the INT_PWM2_FAULT interrupt 141 + 4 + 4 + read-write + + + + + NVICIP142 + Interrupt Priority Register 142 + 0x38E + 8 + read-write + 0 + 0xFF + + + PRI142 + Priority of the INT_PWM3_0 interrupt 142 + 4 + 4 + read-write + + + + + NVICIP143 + Interrupt Priority Register 143 + 0x38F + 8 + read-write + 0 + 0xFF + + + PRI143 + Priority of the INT_PWM3_1 interrupt 143 + 4 + 4 + read-write + + + + + NVICIP144 + Interrupt Priority Register 144 + 0x390 + 8 + read-write + 0 + 0xFF + + + PRI144 + Priority of the INT_PWM3_2 interrupt 144 + 4 + 4 + read-write + + + + + NVICIP145 + Interrupt Priority Register 145 + 0x391 + 8 + read-write + 0 + 0xFF + + + PRI145 + Priority of the INT_PWM3_3 interrupt 145 + 4 + 4 + read-write + + + + + NVICIP146 + Interrupt Priority Register 146 + 0x392 + 8 + read-write + 0 + 0xFF + + + PRI146 + Priority of the INT_PWM3_FAULT interrupt 146 + 4 + 4 + read-write + + + + + NVICIP147 + Interrupt Priority Register 147 + 0x393 + 8 + read-write + 0 + 0xFF + + + PRI147 + Priority of the INT_PWM4_0 interrupt 147 + 4 + 4 + read-write + + + + + NVICIP148 + Interrupt Priority Register 148 + 0x394 + 8 + read-write + 0 + 0xFF + + + PRI148 + Priority of the INT_PWM4_1 interrupt 148 + 4 + 4 + read-write + + + + + NVICIP149 + Interrupt Priority Register 149 + 0x395 + 8 + read-write + 0 + 0xFF + + + PRI149 + Priority of the INT_PWM4_2 interrupt 149 + 4 + 4 + read-write + + + + + NVICIP150 + Interrupt Priority Register 150 + 0x396 + 8 + read-write + 0 + 0xFF + + + PRI150 + Priority of the INT_PWM4_3 interrupt 150 + 4 + 4 + read-write + + + + + NVICIP151 + Interrupt Priority Register 151 + 0x397 + 8 + read-write + 0 + 0xFF + + + PRI151 + Priority of the INT_PWM4_FAULT interrupt 151 + 4 + 4 + read-write + + + + + NVICIP152 + Interrupt Priority Register 152 + 0x398 + 8 + read-write + 0 + 0xFF + + + PRI152 + Priority of the INT_Reserved168 interrupt 152 + 4 + 4 + read-write + + + + + NVICIP153 + Interrupt Priority Register 153 + 0x399 + 8 + read-write + 0 + 0xFF + + + PRI153 + Priority of the INT_Reserved169 interrupt 153 + 4 + 4 + read-write + + + + + NVICIP154 + Interrupt Priority Register 154 + 0x39A + 8 + read-write + 0 + 0xFF + + + PRI154 + Priority of the INT_Reserved170 interrupt 154 + 4 + 4 + read-write + + + + + NVICIP155 + Interrupt Priority Register 155 + 0x39B + 8 + read-write + 0 + 0xFF + + + PRI155 + Priority of the INT_Reserved171 interrupt 155 + 4 + 4 + read-write + + + + + NVICIP156 + Interrupt Priority Register 156 + 0x39C + 8 + read-write + 0 + 0xFF + + + PRI156 + Priority of the INT_Reserved172 interrupt 156 + 4 + 4 + read-write + + + + + NVICIP157 + Interrupt Priority Register 157 + 0x39D + 8 + read-write + 0 + 0xFF + + + PRI157 + Priority of the INT_Reserved173 interrupt 157 + 4 + 4 + read-write + + + + + NVICIP158 + Interrupt Priority Register 158 + 0x39E + 8 + read-write + 0 + 0xFF + + + PRI158 + Priority of the INT_SJC_ARM_DEBUG interrupt 158 + 4 + 4 + read-write + + + + + NVICIP159 + Interrupt Priority Register 159 + 0x39F + 8 + read-write + 0 + 0xFF + + + PRI159 + Priority of the INT_NMI_WAKEUP interrupt 159 + 4 + 4 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + + + \ No newline at end of file diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052_features.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052_features.h new file mode 100644 index 0000000000..765ebaddda --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052_features.h @@ -0,0 +1,615 @@ +/* +** ################################################################### +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Chip specific module features. +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MIMXRT1052_FEATURES_H_ +#define _MIMXRT1052_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (2) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (4) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (1) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (4) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (2) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (5) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (4) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (4) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (1) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief SEMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMC_COUNT (1) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (4) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (2) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (1) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (2) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) + +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief Has extra MB interrupt or common one. */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ +#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (1) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (0) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) + +/* FLEXRAM module features */ + +/* @brief Bank size */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024) +/* @brief Total Bank numbers */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) + +/* GPC module features */ + +/* @brief Has DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) +/* @brief Has GPC interrupt/event masking. */ +#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) +/* @brief Has L2 cache power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) +/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) +/* @brief Has VADC power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) +/* @brief Has Display power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) +/* @brief Supports IRQ 0-31. */ +#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) + +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + +/* LCDIF module features */ + +/* @brief LCDIF does not support alpha support. */ +#define FSL_FEATURE_LCDIF_HAS_NO_AS (1) +/* @brief LCDIF does not support output reset pin to LCD panel. */ +#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1) +/* @brief LCDIF supports LUT. */ +#define FSL_FEATURE_LCDIF_HAS_LUT (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159) + +/* OCOTP module features */ + +/* No feature definitions */ + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) + +/* PMU module features */ + +/* @brief PMU supports lower power control. */ +#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0) + +/* PWM module features */ + +/* @brief Number of each EflexPWM module channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U) +/* @brief Number of EflexPWM module A channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U) +/* @brief Number of EflexPWM module B channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U) +/* @brief Number of EflexPWM module X channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U) +/* @brief Number of each EflexPWM module compare channels interrupts. */ +#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module reload channels interrupts. */ +#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module capture channels interrupts. */ +#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module reload error channels interrupts. */ +#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module fault channels interrupts. */ +#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U) +/* @brief Number of submodules in each EflexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) + +/* PXP module features */ + +/* @brief PXP module has dither engine. */ +#define FSL_FEATURE_PXP_HAS_DITHER (0) +/* @brief PXP module supports repeat run */ +#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1) +/* @brief PXP doesn't have CSC */ +#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1) +/* @brief PXP doesn't have LUT */ +#define FSL_FEATURE_PXP_HAS_NO_LUT (1) + +/* RTWDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) +/* @brief RTWDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (4) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (1) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is LOCKUP_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is no WRBC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) +/* @brief There is no WRE bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (0) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) +/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) +/* @brief There is no WBI bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) + +/* SCB module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) + +/* TRNG module features */ + +/* @brief TRNG has no TRNG_ACC bitfield. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) + +/* XBARA module features */ + +/* @brief DMA_CH_MUX_REQ_30. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1) +/* @brief DMA_CH_MUX_REQ_31. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1) +/* @brief DMA_CH_MUX_REQ_94. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1) +/* @brief DMA_CH_MUX_REQ_95. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1) + +#endif /* _MIMXRT1052_FEATURES_H_ */ + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/SConscript b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/SConscript new file mode 100644 index 0000000000..41f5e4c419 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/SConscript @@ -0,0 +1,22 @@ +# RT-Thread building script for component + +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('drivers/*.c') + Glob('*.c') + +CPPPATH = [cwd, cwd + '/drivers', cwd + '/utilities'] +CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1'] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/gcc/startup_MIMXRT1052.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/arm/startup_MIMXRT1052.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/iar/startup_MIMXRT1052.s'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor.scf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor.scf new file mode 100644 index 0000000000..d3f3c58bea --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor.scf @@ -0,0 +1,127 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x1F7FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +/* #include "../../rtconfig.h" */ + +#if (defined(BOARD_USING_HYPERFLASH)) +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } +} + + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor_sdram.scf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor_sdram.scf new file mode 100644 index 0000000000..3d3dd020b8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor_sdram.scf @@ -0,0 +1,129 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_interrupts_start 0x60002000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x60002400 +#define m_text_size 0x03FFDC00 + +#define m_data_start 0x80000000 +#define m_data_size 0x01E00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x20200000 +#define m_data3_size 0x00040000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_rom_config m_flash_config_start m_flash_config_size { ; load region size_region + RW_m_config_text m_flash_config_start m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size { ; load region size_region + RW_m_ivt_text m_ivt_start m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_ram.scf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_ram.scf new file mode 100644 index 0000000000..7c95609d26 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_ram.scf @@ -0,0 +1,99 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0001FC00 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_data2_start 0x20200000 +#define m_data2_size 0x00040000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + * (NonCacheable.init) + * (NonCacheable) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram.scf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram.scf new file mode 100644 index 0000000000..c24777537e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram.scf @@ -0,0 +1,109 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0001FC00 + +#define m_data_start 0x80000000 +#define m_data_size 0x01E00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x20200000 +#define m_data3_size 0x00040000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram_txt.scf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram_txt.scf new file mode 100644 index 0000000000..e964fe1ce7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram_txt.scf @@ -0,0 +1,109 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x80000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x80000400 +#define m_text_size 0x001FFC00 + +#define m_data_start 0x20200000 +#define m_data_size 0x00040000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x80200000 +#define m_data3_size 0x01C00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/startup_MIMXRT1052.s b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/startup_MIMXRT1052.s new file mode 100644 index 0000000000..a40c03d6ac --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/startup_MIMXRT1052.s @@ -0,0 +1,1051 @@ +; * ------------------------------------------------------------------------- +; * @file: startup_MIMXRT1052.s +; * @purpose: CMSIS Cortex-M7 Core Device Startup File +; * MIMXRT1052 +; * @version: 0.1 +; * @date: 2017-1-10 +; * @build: b180509 +; * ------------------------------------------------------------------------- +; * +; * The Clear BSD License +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2018 NXP +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted (subject to the limitations in the +; * disclaimer below) provided that the following conditions are met: +; * +; * * Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. +; * +; * * Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. +; * +; * * Neither the name of the copyright holder nor the names of its +; * contributors may be used to endorse or promote products derived from +; * this software without specific prior written permission. +; * +; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +; * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +; * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +; * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +; * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +; * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +; * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete + DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete + DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete + DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete + DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete + DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete + DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete + DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete + DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete + DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete + DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete + DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete + DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete + DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete + DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete + DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete + DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31 + DCD CTI0_ERROR_IRQHandler ;CTI0_Error + DCD CTI1_ERROR_IRQHandler ;CTI1_Error + DCD CORE_IRQHandler ;CorePlatform exception IRQ + DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt + DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt + DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt + DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt + DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt + DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt + DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt + DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt + DCD LPI2C1_IRQHandler ;LPI2C1 interrupt + DCD LPI2C2_IRQHandler ;LPI2C2 interrupt + DCD LPI2C3_IRQHandler ;LPI2C3 interrupt + DCD LPI2C4_IRQHandler ;LPI2C4 interrupt + DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources + DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources + DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources + DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources + DCD CAN1_IRQHandler ;CAN1 interrupt + DCD CAN2_IRQHandler ;CAN2 interrupt + DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ + DCD KPP_IRQHandler ;Keypad nterrupt + DCD TSC_DIG_IRQHandler ;TSC interrupt + DCD GPR_IRQ_IRQHandler ;GPR interrupt + DCD LCDIF_IRQHandler ;LCDIF interrupt + DCD CSI_IRQHandler ;CSI interrupt + DCD PXP_IRQHandler ;PXP interrupt + DCD WDOG2_IRQHandler ;WDOG2 interrupt + DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ + DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ + DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event) + DCD CSU_IRQHandler ;CSU interrupt + DCD DCP_IRQHandler ;DCP_IRQ interrupt + DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt + DCD Reserved68_IRQHandler ;Reserved interrupt + DCD TRNG_IRQHandler ;TRNG interrupt + DCD SJC_IRQHandler ;SJC interrupt + DCD BEE_IRQHandler ;BEE interrupt + DCD SAI1_IRQHandler ;SAI1 interrupt + DCD SAI2_IRQHandler ;SAI1 interrupt + DCD SAI3_RX_IRQHandler ;SAI3 interrupt + DCD SAI3_TX_IRQHandler ;SAI3 interrupt + DCD SPDIF_IRQHandler ;SPDIF interrupt + DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt + DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt + DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt + DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt + DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt + DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD ADC2_IRQHandler ;ADC2 interrupt + DCD DCDC_IRQHandler ;DCDC interrupt + DCD Reserved86_IRQHandler ;Reserved interrupt + DCD Reserved87_IRQHandler ;Reserved interrupt + DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO + DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO + DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO + DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO + DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO + DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO + DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO + DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO + DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 + DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 + DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 + DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 + DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 + DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 + DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 + DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 + DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 + DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 + DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt + DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt + DCD WDOG1_IRQHandler ;WDOG1 interrupt + DCD RTWDOG_IRQHandler ;RTWDOG interrupt + DCD EWM_IRQHandler ;EWM interrupt + DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt + DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt + DCD GPC_IRQHandler ;GPC interrupt + DCD SRC_IRQHandler ;SRC interrupt + DCD Reserved115_IRQHandler ;Reserved interrupt + DCD GPT1_IRQHandler ;GPT1 interrupt + DCD GPT2_IRQHandler ;GPT2 interrupt + DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt + DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt + DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt + DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt + DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt + DCD Reserved123_IRQHandler ;Reserved interrupt + DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt + DCD SEMC_IRQHandler ;Reserved interrupt + DCD USDHC1_IRQHandler ;USDHC1 interrupt + DCD USDHC2_IRQHandler ;USDHC2 interrupt + DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 + DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1 + DCD ENET_IRQHandler ;ENET interrupt + DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt + DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt + DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt + DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt + DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt + DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt + DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt + DCD PIT_IRQHandler ;PIT interrupt + DCD ACMP1_IRQHandler ;ACMP interrupt + DCD ACMP2_IRQHandler ;ACMP interrupt + DCD ACMP3_IRQHandler ;ACMP interrupt + DCD ACMP4_IRQHandler ;ACMP interrupt + DCD Reserved143_IRQHandler ;Reserved interrupt + DCD Reserved144_IRQHandler ;Reserved interrupt + DCD ENC1_IRQHandler ;ENC1 interrupt + DCD ENC2_IRQHandler ;ENC2 interrupt + DCD ENC3_IRQHandler ;ENC3 interrupt + DCD ENC4_IRQHandler ;ENC4 interrupt + DCD TMR1_IRQHandler ;TMR1 interrupt + DCD TMR2_IRQHandler ;TMR2 interrupt + DCD TMR3_IRQHandler ;TMR3 interrupt + DCD TMR4_IRQHandler ;TMR4 interrupt + DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt + DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt + DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt + DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt + DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt + DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt + DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt + DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt + DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt + DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt + DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt + DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt + DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt + DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt + DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt + DCD Reserved168_IRQHandler ;Reserved interrupt + DCD Reserved169_IRQHandler ;Reserved interrupt + DCD Reserved170_IRQHandler ;Reserved interrupt + DCD Reserved171_IRQHandler ;Reserved interrupt + DCD Reserved172_IRQHandler ;Reserved interrupt + DCD Reserved173_IRQHandler ;Reserved interrupt + DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt + DCD NMI_WAKEUP_IRQHandler ;NMI wake up + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_DMA16_IRQHandler\ + PROC + EXPORT DMA0_DMA16_IRQHandler [WEAK] + LDR R0, =DMA0_DMA16_DriverIRQHandler + BX R0 + ENDP + +DMA1_DMA17_IRQHandler\ + PROC + EXPORT DMA1_DMA17_IRQHandler [WEAK] + LDR R0, =DMA1_DMA17_DriverIRQHandler + BX R0 + ENDP + +DMA2_DMA18_IRQHandler\ + PROC + EXPORT DMA2_DMA18_IRQHandler [WEAK] + LDR R0, =DMA2_DMA18_DriverIRQHandler + BX R0 + ENDP + +DMA3_DMA19_IRQHandler\ + PROC + EXPORT DMA3_DMA19_IRQHandler [WEAK] + LDR R0, =DMA3_DMA19_DriverIRQHandler + BX R0 + ENDP + +DMA4_DMA20_IRQHandler\ + PROC + EXPORT DMA4_DMA20_IRQHandler [WEAK] + LDR R0, =DMA4_DMA20_DriverIRQHandler + BX R0 + ENDP + +DMA5_DMA21_IRQHandler\ + PROC + EXPORT DMA5_DMA21_IRQHandler [WEAK] + LDR R0, =DMA5_DMA21_DriverIRQHandler + BX R0 + ENDP + +DMA6_DMA22_IRQHandler\ + PROC + EXPORT DMA6_DMA22_IRQHandler [WEAK] + LDR R0, =DMA6_DMA22_DriverIRQHandler + BX R0 + ENDP + +DMA7_DMA23_IRQHandler\ + PROC + EXPORT DMA7_DMA23_IRQHandler [WEAK] + LDR R0, =DMA7_DMA23_DriverIRQHandler + BX R0 + ENDP + +DMA8_DMA24_IRQHandler\ + PROC + EXPORT DMA8_DMA24_IRQHandler [WEAK] + LDR R0, =DMA8_DMA24_DriverIRQHandler + BX R0 + ENDP + +DMA9_DMA25_IRQHandler\ + PROC + EXPORT DMA9_DMA25_IRQHandler [WEAK] + LDR R0, =DMA9_DMA25_DriverIRQHandler + BX R0 + ENDP + +DMA10_DMA26_IRQHandler\ + PROC + EXPORT DMA10_DMA26_IRQHandler [WEAK] + LDR R0, =DMA10_DMA26_DriverIRQHandler + BX R0 + ENDP + +DMA11_DMA27_IRQHandler\ + PROC + EXPORT DMA11_DMA27_IRQHandler [WEAK] + LDR R0, =DMA11_DMA27_DriverIRQHandler + BX R0 + ENDP + +DMA12_DMA28_IRQHandler\ + PROC + EXPORT DMA12_DMA28_IRQHandler [WEAK] + LDR R0, =DMA12_DMA28_DriverIRQHandler + BX R0 + ENDP + +DMA13_DMA29_IRQHandler\ + PROC + EXPORT DMA13_DMA29_IRQHandler [WEAK] + LDR R0, =DMA13_DMA29_DriverIRQHandler + BX R0 + ENDP + +DMA14_DMA30_IRQHandler\ + PROC + EXPORT DMA14_DMA30_IRQHandler [WEAK] + LDR R0, =DMA14_DMA30_DriverIRQHandler + BX R0 + ENDP + +DMA15_DMA31_IRQHandler\ + PROC + EXPORT DMA15_DMA31_IRQHandler [WEAK] + LDR R0, =DMA15_DMA31_DriverIRQHandler + BX R0 + ENDP + +DMA_ERROR_IRQHandler\ + PROC + EXPORT DMA_ERROR_IRQHandler [WEAK] + LDR R0, =DMA_ERROR_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +LPUART2_IRQHandler\ + PROC + EXPORT LPUART2_IRQHandler [WEAK] + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + ENDP + +LPUART3_IRQHandler\ + PROC + EXPORT LPUART3_IRQHandler [WEAK] + LDR R0, =LPUART3_DriverIRQHandler + BX R0 + ENDP + +LPUART4_IRQHandler\ + PROC + EXPORT LPUART4_IRQHandler [WEAK] + LDR R0, =LPUART4_DriverIRQHandler + BX R0 + ENDP + +LPUART5_IRQHandler\ + PROC + EXPORT LPUART5_IRQHandler [WEAK] + LDR R0, =LPUART5_DriverIRQHandler + BX R0 + ENDP + +LPUART6_IRQHandler\ + PROC + EXPORT LPUART6_IRQHandler [WEAK] + LDR R0, =LPUART6_DriverIRQHandler + BX R0 + ENDP + +LPUART7_IRQHandler\ + PROC + EXPORT LPUART7_IRQHandler [WEAK] + LDR R0, =LPUART7_DriverIRQHandler + BX R0 + ENDP + +LPUART8_IRQHandler\ + PROC + EXPORT LPUART8_IRQHandler [WEAK] + LDR R0, =LPUART8_DriverIRQHandler + BX R0 + ENDP + +LPI2C1_IRQHandler\ + PROC + EXPORT LPI2C1_IRQHandler [WEAK] + LDR R0, =LPI2C1_DriverIRQHandler + BX R0 + ENDP + +LPI2C2_IRQHandler\ + PROC + EXPORT LPI2C2_IRQHandler [WEAK] + LDR R0, =LPI2C2_DriverIRQHandler + BX R0 + ENDP + +LPI2C3_IRQHandler\ + PROC + EXPORT LPI2C3_IRQHandler [WEAK] + LDR R0, =LPI2C3_DriverIRQHandler + BX R0 + ENDP + +LPI2C4_IRQHandler\ + PROC + EXPORT LPI2C4_IRQHandler [WEAK] + LDR R0, =LPI2C4_DriverIRQHandler + BX R0 + ENDP + +LPSPI1_IRQHandler\ + PROC + EXPORT LPSPI1_IRQHandler [WEAK] + LDR R0, =LPSPI1_DriverIRQHandler + BX R0 + ENDP + +LPSPI2_IRQHandler\ + PROC + EXPORT LPSPI2_IRQHandler [WEAK] + LDR R0, =LPSPI2_DriverIRQHandler + BX R0 + ENDP + +LPSPI3_IRQHandler\ + PROC + EXPORT LPSPI3_IRQHandler [WEAK] + LDR R0, =LPSPI3_DriverIRQHandler + BX R0 + ENDP + +LPSPI4_IRQHandler\ + PROC + EXPORT LPSPI4_IRQHandler [WEAK] + LDR R0, =LPSPI4_DriverIRQHandler + BX R0 + ENDP + +CAN1_IRQHandler\ + PROC + EXPORT CAN1_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN2_IRQHandler\ + PROC + EXPORT CAN2_IRQHandler [WEAK] + LDR R0, =CAN2_DriverIRQHandler + BX R0 + ENDP + +SAI1_IRQHandler\ + PROC + EXPORT SAI1_IRQHandler [WEAK] + LDR R0, =SAI1_DriverIRQHandler + BX R0 + ENDP + +SAI2_IRQHandler\ + PROC + EXPORT SAI2_IRQHandler [WEAK] + LDR R0, =SAI2_DriverIRQHandler + BX R0 + ENDP + +SAI3_RX_IRQHandler\ + PROC + EXPORT SAI3_RX_IRQHandler [WEAK] + LDR R0, =SAI3_RX_DriverIRQHandler + BX R0 + ENDP + +SAI3_TX_IRQHandler\ + PROC + EXPORT SAI3_TX_IRQHandler [WEAK] + LDR R0, =SAI3_TX_DriverIRQHandler + BX R0 + ENDP + +SPDIF_IRQHandler\ + PROC + EXPORT SPDIF_IRQHandler [WEAK] + LDR R0, =SPDIF_DriverIRQHandler + BX R0 + ENDP + +FLEXIO1_IRQHandler\ + PROC + EXPORT FLEXIO1_IRQHandler [WEAK] + LDR R0, =FLEXIO1_DriverIRQHandler + BX R0 + ENDP + +FLEXIO2_IRQHandler\ + PROC + EXPORT FLEXIO2_IRQHandler [WEAK] + LDR R0, =FLEXIO2_DriverIRQHandler + BX R0 + ENDP + +FLEXSPI_IRQHandler\ + PROC + EXPORT FLEXSPI_IRQHandler [WEAK] + LDR R0, =FLEXSPI_DriverIRQHandler + BX R0 + ENDP + +USDHC1_IRQHandler\ + PROC + EXPORT USDHC1_IRQHandler [WEAK] + LDR R0, =USDHC1_DriverIRQHandler + BX R0 + ENDP + +USDHC2_IRQHandler\ + PROC + EXPORT USDHC2_IRQHandler [WEAK] + LDR R0, =USDHC2_DriverIRQHandler + BX R0 + ENDP + +ENET_IRQHandler\ + PROC + EXPORT ENET_IRQHandler [WEAK] + LDR R0, =ENET_DriverIRQHandler + BX R0 + ENDP + +ENET_1588_Timer_IRQHandler\ + PROC + EXPORT ENET_1588_Timer_IRQHandler [WEAK] + LDR R0, =ENET_1588_Timer_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DMA16_DriverIRQHandler [WEAK] + EXPORT DMA1_DMA17_DriverIRQHandler [WEAK] + EXPORT DMA2_DMA18_DriverIRQHandler [WEAK] + EXPORT DMA3_DMA19_DriverIRQHandler [WEAK] + EXPORT DMA4_DMA20_DriverIRQHandler [WEAK] + EXPORT DMA5_DMA21_DriverIRQHandler [WEAK] + EXPORT DMA6_DMA22_DriverIRQHandler [WEAK] + EXPORT DMA7_DMA23_DriverIRQHandler [WEAK] + EXPORT DMA8_DMA24_DriverIRQHandler [WEAK] + EXPORT DMA9_DMA25_DriverIRQHandler [WEAK] + EXPORT DMA10_DMA26_DriverIRQHandler [WEAK] + EXPORT DMA11_DMA27_DriverIRQHandler [WEAK] + EXPORT DMA12_DMA28_DriverIRQHandler [WEAK] + EXPORT DMA13_DMA29_DriverIRQHandler [WEAK] + EXPORT DMA14_DMA30_DriverIRQHandler [WEAK] + EXPORT DMA15_DMA31_DriverIRQHandler [WEAK] + EXPORT DMA_ERROR_DriverIRQHandler [WEAK] + EXPORT CTI0_ERROR_IRQHandler [WEAK] + EXPORT CTI1_ERROR_IRQHandler [WEAK] + EXPORT CORE_IRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT LPUART2_DriverIRQHandler [WEAK] + EXPORT LPUART3_DriverIRQHandler [WEAK] + EXPORT LPUART4_DriverIRQHandler [WEAK] + EXPORT LPUART5_DriverIRQHandler [WEAK] + EXPORT LPUART6_DriverIRQHandler [WEAK] + EXPORT LPUART7_DriverIRQHandler [WEAK] + EXPORT LPUART8_DriverIRQHandler [WEAK] + EXPORT LPI2C1_DriverIRQHandler [WEAK] + EXPORT LPI2C2_DriverIRQHandler [WEAK] + EXPORT LPI2C3_DriverIRQHandler [WEAK] + EXPORT LPI2C4_DriverIRQHandler [WEAK] + EXPORT LPSPI1_DriverIRQHandler [WEAK] + EXPORT LPSPI2_DriverIRQHandler [WEAK] + EXPORT LPSPI3_DriverIRQHandler [WEAK] + EXPORT LPSPI4_DriverIRQHandler [WEAK] + EXPORT CAN1_DriverIRQHandler [WEAK] + EXPORT CAN2_DriverIRQHandler [WEAK] + EXPORT FLEXRAM_IRQHandler [WEAK] + EXPORT KPP_IRQHandler [WEAK] + EXPORT TSC_DIG_IRQHandler [WEAK] + EXPORT GPR_IRQ_IRQHandler [WEAK] + EXPORT LCDIF_IRQHandler [WEAK] + EXPORT CSI_IRQHandler [WEAK] + EXPORT PXP_IRQHandler [WEAK] + EXPORT WDOG2_IRQHandler [WEAK] + EXPORT SNVS_HP_WRAPPER_IRQHandler [WEAK] + EXPORT SNVS_HP_WRAPPER_TZ_IRQHandler [WEAK] + EXPORT SNVS_LP_WRAPPER_IRQHandler [WEAK] + EXPORT CSU_IRQHandler [WEAK] + EXPORT DCP_IRQHandler [WEAK] + EXPORT DCP_VMI_IRQHandler [WEAK] + EXPORT Reserved68_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT SJC_IRQHandler [WEAK] + EXPORT BEE_IRQHandler [WEAK] + EXPORT SAI1_DriverIRQHandler [WEAK] + EXPORT SAI2_DriverIRQHandler [WEAK] + EXPORT SAI3_RX_DriverIRQHandler [WEAK] + EXPORT SAI3_TX_DriverIRQHandler [WEAK] + EXPORT SPDIF_DriverIRQHandler [WEAK] + EXPORT ANATOP_EVENT0_IRQHandler [WEAK] + EXPORT ANATOP_EVENT1_IRQHandler [WEAK] + EXPORT ANATOP_TAMP_LOW_HIGH_IRQHandler [WEAK] + EXPORT ANATOP_TEMP_PANIC_IRQHandler [WEAK] + EXPORT USB_PHY1_IRQHandler [WEAK] + EXPORT USB_PHY2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT DCDC_IRQHandler [WEAK] + EXPORT Reserved86_IRQHandler [WEAK] + EXPORT Reserved87_IRQHandler [WEAK] + EXPORT GPIO1_INT0_IRQHandler [WEAK] + EXPORT GPIO1_INT1_IRQHandler [WEAK] + EXPORT GPIO1_INT2_IRQHandler [WEAK] + EXPORT GPIO1_INT3_IRQHandler [WEAK] + EXPORT GPIO1_INT4_IRQHandler [WEAK] + EXPORT GPIO1_INT5_IRQHandler [WEAK] + EXPORT GPIO1_INT6_IRQHandler [WEAK] + EXPORT GPIO1_INT7_IRQHandler [WEAK] + EXPORT GPIO1_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO1_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO2_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO2_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO3_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO3_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO4_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO4_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO5_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO5_Combined_16_31_IRQHandler [WEAK] + EXPORT FLEXIO1_DriverIRQHandler [WEAK] + EXPORT FLEXIO2_DriverIRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT RTWDOG_IRQHandler [WEAK] + EXPORT EWM_IRQHandler [WEAK] + EXPORT CCM_1_IRQHandler [WEAK] + EXPORT CCM_2_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT SRC_IRQHandler [WEAK] + EXPORT Reserved115_IRQHandler [WEAK] + EXPORT GPT1_IRQHandler [WEAK] + EXPORT GPT2_IRQHandler [WEAK] + EXPORT PWM1_0_IRQHandler [WEAK] + EXPORT PWM1_1_IRQHandler [WEAK] + EXPORT PWM1_2_IRQHandler [WEAK] + EXPORT PWM1_3_IRQHandler [WEAK] + EXPORT PWM1_FAULT_IRQHandler [WEAK] + EXPORT Reserved123_IRQHandler [WEAK] + EXPORT FLEXSPI_DriverIRQHandler [WEAK] + EXPORT SEMC_IRQHandler [WEAK] + EXPORT USDHC1_DriverIRQHandler [WEAK] + EXPORT USDHC2_DriverIRQHandler [WEAK] + EXPORT USB_OTG2_IRQHandler [WEAK] + EXPORT USB_OTG1_IRQHandler [WEAK] + EXPORT ENET_DriverIRQHandler [WEAK] + EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK] + EXPORT XBAR1_IRQ_0_1_IRQHandler [WEAK] + EXPORT XBAR1_IRQ_2_3_IRQHandler [WEAK] + EXPORT ADC_ETC_IRQ0_IRQHandler [WEAK] + EXPORT ADC_ETC_IRQ1_IRQHandler [WEAK] + EXPORT ADC_ETC_IRQ2_IRQHandler [WEAK] + EXPORT ADC_ETC_ERROR_IRQ_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT ACMP1_IRQHandler [WEAK] + EXPORT ACMP2_IRQHandler [WEAK] + EXPORT ACMP3_IRQHandler [WEAK] + EXPORT ACMP4_IRQHandler [WEAK] + EXPORT Reserved143_IRQHandler [WEAK] + EXPORT Reserved144_IRQHandler [WEAK] + EXPORT ENC1_IRQHandler [WEAK] + EXPORT ENC2_IRQHandler [WEAK] + EXPORT ENC3_IRQHandler [WEAK] + EXPORT ENC4_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT PWM2_0_IRQHandler [WEAK] + EXPORT PWM2_1_IRQHandler [WEAK] + EXPORT PWM2_2_IRQHandler [WEAK] + EXPORT PWM2_3_IRQHandler [WEAK] + EXPORT PWM2_FAULT_IRQHandler [WEAK] + EXPORT PWM3_0_IRQHandler [WEAK] + EXPORT PWM3_1_IRQHandler [WEAK] + EXPORT PWM3_2_IRQHandler [WEAK] + EXPORT PWM3_3_IRQHandler [WEAK] + EXPORT PWM3_FAULT_IRQHandler [WEAK] + EXPORT PWM4_0_IRQHandler [WEAK] + EXPORT PWM4_1_IRQHandler [WEAK] + EXPORT PWM4_2_IRQHandler [WEAK] + EXPORT PWM4_3_IRQHandler [WEAK] + EXPORT PWM4_FAULT_IRQHandler [WEAK] + EXPORT Reserved168_IRQHandler [WEAK] + EXPORT Reserved169_IRQHandler [WEAK] + EXPORT Reserved170_IRQHandler [WEAK] + EXPORT Reserved171_IRQHandler [WEAK] + EXPORT Reserved172_IRQHandler [WEAK] + EXPORT Reserved173_IRQHandler [WEAK] + EXPORT SJC_ARM_DEBUG_IRQHandler [WEAK] + EXPORT NMI_WAKEUP_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DMA16_DriverIRQHandler +DMA1_DMA17_DriverIRQHandler +DMA2_DMA18_DriverIRQHandler +DMA3_DMA19_DriverIRQHandler +DMA4_DMA20_DriverIRQHandler +DMA5_DMA21_DriverIRQHandler +DMA6_DMA22_DriverIRQHandler +DMA7_DMA23_DriverIRQHandler +DMA8_DMA24_DriverIRQHandler +DMA9_DMA25_DriverIRQHandler +DMA10_DMA26_DriverIRQHandler +DMA11_DMA27_DriverIRQHandler +DMA12_DMA28_DriverIRQHandler +DMA13_DMA29_DriverIRQHandler +DMA14_DMA30_DriverIRQHandler +DMA15_DMA31_DriverIRQHandler +DMA_ERROR_DriverIRQHandler +CTI0_ERROR_IRQHandler +CTI1_ERROR_IRQHandler +CORE_IRQHandler +LPUART1_DriverIRQHandler +LPUART2_DriverIRQHandler +LPUART3_DriverIRQHandler +LPUART4_DriverIRQHandler +LPUART5_DriverIRQHandler +LPUART6_DriverIRQHandler +LPUART7_DriverIRQHandler +LPUART8_DriverIRQHandler +LPI2C1_DriverIRQHandler +LPI2C2_DriverIRQHandler +LPI2C3_DriverIRQHandler +LPI2C4_DriverIRQHandler +LPSPI1_DriverIRQHandler +LPSPI2_DriverIRQHandler +LPSPI3_DriverIRQHandler +LPSPI4_DriverIRQHandler +CAN1_DriverIRQHandler +CAN2_DriverIRQHandler +FLEXRAM_IRQHandler +KPP_IRQHandler +TSC_DIG_IRQHandler +GPR_IRQ_IRQHandler +LCDIF_IRQHandler +CSI_IRQHandler +PXP_IRQHandler +WDOG2_IRQHandler +SNVS_HP_WRAPPER_IRQHandler +SNVS_HP_WRAPPER_TZ_IRQHandler +SNVS_LP_WRAPPER_IRQHandler +CSU_IRQHandler +DCP_IRQHandler +DCP_VMI_IRQHandler +Reserved68_IRQHandler +TRNG_IRQHandler +SJC_IRQHandler +BEE_IRQHandler +SAI1_DriverIRQHandler +SAI2_DriverIRQHandler +SAI3_RX_DriverIRQHandler +SAI3_TX_DriverIRQHandler +SPDIF_DriverIRQHandler +ANATOP_EVENT0_IRQHandler +ANATOP_EVENT1_IRQHandler +ANATOP_TAMP_LOW_HIGH_IRQHandler +ANATOP_TEMP_PANIC_IRQHandler +USB_PHY1_IRQHandler +USB_PHY2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +DCDC_IRQHandler +Reserved86_IRQHandler +Reserved87_IRQHandler +GPIO1_INT0_IRQHandler +GPIO1_INT1_IRQHandler +GPIO1_INT2_IRQHandler +GPIO1_INT3_IRQHandler +GPIO1_INT4_IRQHandler +GPIO1_INT5_IRQHandler +GPIO1_INT6_IRQHandler +GPIO1_INT7_IRQHandler +GPIO1_Combined_0_15_IRQHandler +GPIO1_Combined_16_31_IRQHandler +GPIO2_Combined_0_15_IRQHandler +GPIO2_Combined_16_31_IRQHandler +GPIO3_Combined_0_15_IRQHandler +GPIO3_Combined_16_31_IRQHandler +GPIO4_Combined_0_15_IRQHandler +GPIO4_Combined_16_31_IRQHandler +GPIO5_Combined_0_15_IRQHandler +GPIO5_Combined_16_31_IRQHandler +FLEXIO1_DriverIRQHandler +FLEXIO2_DriverIRQHandler +WDOG1_IRQHandler +RTWDOG_IRQHandler +EWM_IRQHandler +CCM_1_IRQHandler +CCM_2_IRQHandler +GPC_IRQHandler +SRC_IRQHandler +Reserved115_IRQHandler +GPT1_IRQHandler +GPT2_IRQHandler +PWM1_0_IRQHandler +PWM1_1_IRQHandler +PWM1_2_IRQHandler +PWM1_3_IRQHandler +PWM1_FAULT_IRQHandler +Reserved123_IRQHandler +FLEXSPI_DriverIRQHandler +SEMC_IRQHandler +USDHC1_DriverIRQHandler +USDHC2_DriverIRQHandler +USB_OTG2_IRQHandler +USB_OTG1_IRQHandler +ENET_DriverIRQHandler +ENET_1588_Timer_DriverIRQHandler +XBAR1_IRQ_0_1_IRQHandler +XBAR1_IRQ_2_3_IRQHandler +ADC_ETC_IRQ0_IRQHandler +ADC_ETC_IRQ1_IRQHandler +ADC_ETC_IRQ2_IRQHandler +ADC_ETC_ERROR_IRQ_IRQHandler +PIT_IRQHandler +ACMP1_IRQHandler +ACMP2_IRQHandler +ACMP3_IRQHandler +ACMP4_IRQHandler +Reserved143_IRQHandler +Reserved144_IRQHandler +ENC1_IRQHandler +ENC2_IRQHandler +ENC3_IRQHandler +ENC4_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +PWM2_0_IRQHandler +PWM2_1_IRQHandler +PWM2_2_IRQHandler +PWM2_3_IRQHandler +PWM2_FAULT_IRQHandler +PWM3_0_IRQHandler +PWM3_1_IRQHandler +PWM3_2_IRQHandler +PWM3_3_IRQHandler +PWM3_FAULT_IRQHandler +PWM4_0_IRQHandler +PWM4_1_IRQHandler +PWM4_2_IRQHandler +PWM4_3_IRQHandler +PWM4_FAULT_IRQHandler +Reserved168_IRQHandler +Reserved169_IRQHandler +Reserved170_IRQHandler +Reserved171_IRQHandler +Reserved172_IRQHandler +Reserved173_IRQHandler +SJC_ARM_DEBUG_IRQHandler +NMI_WAKEUP_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c new file mode 100644 index 0000000000..56173ee6fb --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c @@ -0,0 +1,2059 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_lpi2c_cmsis.h" + +#if ((RTE_I2C0 && defined(LPI2C0)) || (RTE_I2C1 && defined(LPI2C1)) || (RTE_I2C2 && defined(LPI2C2)) || \ + (RTE_I2C3 && defined(LPI2C3)) || (RTE_I2C4 && defined(LPI2C4)) || (RTE_I2C5 && defined(LPI2C5)) || \ + (RTE_I2C6 && defined(LPI2C6))) + +#define ARM_LPI2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c_cmsis" +#endif + +/*! @brief Common sets of flags used by the driver. */ +enum _lpi2c_flag_constants +{ + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + +}; + +typedef const struct _cmsis_lpi2c_resource +{ + LPI2C_Type *base; /*!< LPI2C peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ + +} cmsis_lpi2c_resource_t; + +typedef union _cmsis_i2c_handle +{ + lpi2c_master_handle_t master_handle; + lpi2c_slave_handle_t slave_handle; +} cmsis_i2c_handle_t; + +typedef struct _cmsis_lpi2c_interrupt_driver_state +{ + cmsis_lpi2c_resource_t *resource; /*!< Basic LPI2C resource. */ + cmsis_i2c_handle_t *handle; + uint8_t *slave_data; /*!< slave Transfer buffer */ + size_t slave_dataSize; /*!< slave Transfer size */ + ARM_I2C_SignalEvent_t cb_event; /*!< call back function */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpi2c_interrupt_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +typedef const struct _cmsis_lpi2c_edma_resource +{ + DMA_Type *txEdmaBase; /*!< EDMA peripheral base address for Tx. */ + uint32_t txEdmaChannel; /*!< EDMA channel for Tx */ + uint16_t txDmaRequest; /*!< Tx EDMA request source. */ + + DMA_Type *rxEdmaBase; /*!< EDMA peripheral base address for Rx. */ + uint32_t rxEdmaChannel; /*!< EDMA channel for Rx */ + uint16_t rxDmaRequest; /*!< Rx EDMA request source. */ +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for Tx */ + DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for Rx */ +#endif +} cmsis_lpi2c_edma_resource_t; + +typedef struct _cmsis_lpi2c_edma_driver_state +{ + cmsis_lpi2c_resource_t *resource; /*!< lpi2c basic resource. */ + cmsis_lpi2c_edma_resource_t *edmaResource; /*!< lpi2c EDMA resource. */ + lpi2c_master_edma_handle_t *master_edma_handle; /*!< lpi2c EDMA transfer handle. */ + edma_handle_t *edmaTxHandle; /*!< EDMA lpi2c Tx handle. */ + edma_handle_t *edmaRxHandle; /*!< EDMA lpi2c Rx handle. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpi2c_edma_driver_state_t; +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static const ARM_DRIVER_VERSION s_lpi2cDriverVersion = {ARM_I2C_API_VERSION, ARM_LPI2C_DRV_VERSION}; +static const ARM_I2C_CAPABILITIES s_lpi2cDriverCapabilities = { + 0, /* Do not support 10-bit addressing.*/ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Returns version information */ +static ARM_DRIVER_VERSION LPI2Cx_GetVersion(void) +{ + return s_lpi2cDriverVersion; +} + +/* Returns information about capabilities of this driver implementation */ +static ARM_I2C_CAPABILITIES LPI2Cx_GetCapabilities(void) +{ + return s_lpi2cDriverCapabilities; +} + +#endif + +#if (RTE_I2C0_DMA_EN || RTE_I2C1_DMA_EN || RTE_I2C2_DMA_EN || RTE_I2C3_DMA_EN || RTE_I2C4_DMA_EN || RTE_I2C5_DMA_EN || \ + RTE_I2C6_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +void KSDK_LPI2C_MASTER_EdmaCallback(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0; + + /* Signal transfer success when received success status. */ + if (status == kStatus_Success) + { + event = ARM_I2C_EVENT_TRANSFER_DONE; + } + + if (userData) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t LPI2C_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + if (!(lpi2c->flags & I2C_FLAG_INIT)) + { +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + /* TxDMAMUX init */ + DMAMUX_SetSource(lpi2c->edmaResource->txDmamuxBase, lpi2c->edmaResource->txEdmaChannel, + (uint8_t)lpi2c->edmaResource->txDmaRequest); + DMAMUX_EnableChannel(lpi2c->edmaResource->txDmamuxBase, lpi2c->edmaResource->txEdmaChannel); + /* RxDMAMUX init */ + DMAMUX_SetSource(lpi2c->edmaResource->rxDmamuxBase, lpi2c->edmaResource->rxEdmaChannel, + (uint8_t)lpi2c->edmaResource->rxDmaRequest); + DMAMUX_EnableChannel(lpi2c->edmaResource->rxDmamuxBase, lpi2c->edmaResource->rxEdmaChannel); +#endif + /* Create edmaTxHandle */ + EDMA_CreateHandle(lpi2c->edmaTxHandle, lpi2c->edmaResource->txEdmaBase, lpi2c->edmaResource->txEdmaChannel); + + /* Create edmaRxHandle */ + EDMA_CreateHandle(lpi2c->edmaRxHandle, lpi2c->edmaResource->rxEdmaBase, lpi2c->edmaResource->rxEdmaChannel); + + /* Create master_edma_handle */ + LPI2C_MasterCreateEDMAHandle(lpi2c->resource->base, lpi2c->master_edma_handle, lpi2c->edmaRxHandle, + lpi2c->edmaTxHandle, KSDK_LPI2C_MASTER_EdmaCallback, (void *)cb_event); + + lpi2c->flags = I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +int32_t LPI2C_Master_EdmaUninitialize(cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + lpi2c->flags = I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +int32_t LPI2C_Master_EdmaTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + int32_t status; + int32_t ret; + lpi2c_master_transfer_t masterXfer; + + /* Setup the master transfer */ + masterXfer.slaveAddress = addr; + masterXfer.direction = kLPI2C_Write; + masterXfer.subaddress = 0; + masterXfer.subaddressSize = 0; + masterXfer.data = (uint8_t *)data; + masterXfer.dataSize = num; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + + if (xfer_pending) + { + /* Do not transfer stop */ + masterXfer.flags |= kLPI2C_TransferNoStopFlag; + } + + /* Send master non-blocking data to slave */ + status = LPI2C_MasterTransferEDMA(lpi2c->resource->base, lpi2c->master_edma_handle, &masterXfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_LPI2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t LPI2C_Master_EdmaReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + int32_t status; + int32_t ret; + lpi2c_master_transfer_t masterXfer; + + /* Setup the master transfer */ + masterXfer.slaveAddress = addr; + masterXfer.direction = kLPI2C_Read; + masterXfer.subaddress = 0; + masterXfer.subaddressSize = 0; + masterXfer.data = data; + masterXfer.dataSize = num; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + + if (xfer_pending) + { + masterXfer.flags |= kLPI2C_TransferNoStopFlag; + } + + /* Receive non-blocking data from slave */ + status = LPI2C_MasterTransferEDMA(lpi2c->resource->base, lpi2c->master_edma_handle, &masterXfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_LPI2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t LPI2C_Master_EdmaGetDataCount(cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + size_t cnt; + + LPI2C_MasterTransferGetCountEDMA(lpi2c->resource->base, lpi2c->master_edma_handle, &cnt); + + return cnt; +} + +int32_t LPI2C_Master_EdmaControl(uint32_t control, uint32_t arg, cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + uint32_t baudRate_Bps; + + switch (control) + { + /* Set Own Slave Address */ + case ARM_I2C_OWN_ADDRESS: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + /* Set Bus Speed; arg = bus speed */ + case ARM_I2C_BUS_SPEED: + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + LPI2C_MasterSetBaudRate(lpi2c->resource->base, lpi2c->resource->GetFreq(), baudRate_Bps); + + return ARM_DRIVER_OK; + + /* Not supported. */ + case ARM_I2C_BUS_CLEAR: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + /* Only support aborting data transfer when master transmit in master mode */ + case ARM_I2C_ABORT_TRANSFER: + + if ((lpi2c->resource->base->MDER & 0x3) == 0x3) + { + if (lpi2c->master_edma_handle->transfer.direction == kLPI2C_Write) + { + LPI2C_MasterTransferAbortEDMA(lpi2c->resource->base, lpi2c->master_edma_handle); + + lpi2c->master_edma_handle->transfer.data = NULL; + lpi2c->master_edma_handle->transfer.dataSize = 0; + } + } + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +int32_t LPI2C_Master_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + lpi2c_master_config_t masterConfig; + + switch (state) + { + case ARM_POWER_OFF: + if (lpi2c->flags & I2C_FLAG_POWER) + { + /* Terminates any pending data transfers */ + LPI2C_Master_EdmaControl(ARM_I2C_ABORT_TRANSFER, 0, lpi2c); + + /* Disables peripheral */ + LPI2C_MasterDeinit(lpi2c->resource->base); +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + /* Disable DMAMUX channel */ + DMAMUX_DisableChannel(lpi2c->edmaResource->txDmamuxBase, lpi2c->edmaResource->txEdmaChannel); + DMAMUX_DisableChannel(lpi2c->edmaResource->rxDmamuxBase, lpi2c->edmaResource->rxEdmaChannel); +#endif + lpi2c->flags = I2C_FLAG_INIT; + } + return ARM_DRIVER_OK; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if (lpi2c->flags == I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpi2c->flags & I2C_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + /* + * masterConfig.debugEnable = false; + * masterConfig.ignoreAck = false; + * masterConfig.pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig.baudRate_Hz = 100000U; + * masterConfig.busIdleTimeout_ns = 0; + * masterConfig.pinLowTimeout_ns = 0; + * masterConfig.sdaGlitchFilterWidth_ns = 0; + * masterConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&masterConfig); + + /* Initialize the LPI2C master peripheral */ + LPI2C_MasterInit(lpi2c->resource->base, &masterConfig, lpi2c->resource->GetFreq()); + + lpi2c->flags |= I2C_FLAG_POWER; + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +ARM_I2C_STATUS LPI2C_Master_EdmaGetStatus(cmsis_lpi2c_edma_driver_state_t *lpi2c) +{ + ARM_I2C_STATUS stat = {0}; + uint32_t ksdk_lpi2c_master_status = LPI2C_MasterGetStatusFlags(lpi2c->resource->base); + + stat.busy = !(!(ksdk_lpi2c_master_status & kLPI2C_MasterBusyFlag)); /* Busy flag */ + stat.mode = 1; /* Mode: 0=Slave, 1=Master */ + stat.direction = lpi2c->master_edma_handle->transfer.direction; /* Direction: 0=Transmitter, 1=Receiver */ + stat.arbitration_lost = + !(!(ksdk_lpi2c_master_status & kLPI2C_MasterArbitrationLostFlag)); /* Master lost arbitration */ + + return stat; +} +#endif + +#endif + +#if ((RTE_I2C0 && !RTE_I2C0_DMA_EN) || (RTE_I2C1 && !RTE_I2C1_DMA_EN) || (RTE_I2C2 && !RTE_I2C2_DMA_EN) || \ + (RTE_I2C3 && !RTE_I2C3_DMA_EN) || (RTE_I2C4 && !RTE_I2C4_DMA_EN) || (RTE_I2C5 && !RTE_I2C5_DMA_EN) || \ + (RTE_I2C6 && !RTE_I2C6_DMA_EN)) + +static void KSDK_LPI2C_SLAVE_InterruptCallback(LPI2C_Type *base, + lpi2c_slave_transfer_t *xfer, + void *userData, + cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + uint32_t event = 0; + + switch (xfer->event) + { + /* Transfer done */ + case kLPI2C_SlaveCompletionEvent: + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + + /* Setup the slave receive buffer */ + case kLPI2C_SlaveReceiveEvent: + xfer->data = lpi2c->slave_data; + xfer->dataSize = lpi2c->slave_dataSize; + break; + + /* Setup the slave transmit buffer */ + case kLPI2C_SlaveTransmitEvent: + xfer->data = lpi2c->slave_data; + xfer->dataSize = lpi2c->slave_dataSize; + break; + + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + if (userData) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static void KSDK_LPI2C_MASTER_InterruptCallback(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0; + + /* Signal transfer success when received success status. */ + switch (status) + { + /* Transfer done */ + case kStatus_Success: + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + + /* Occurs in master mode when arbitration is lost */ + case kStatus_LPI2C_ArbitrationLost: + event = ARM_I2C_EVENT_ARBITRATION_LOST; + break; + + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + if (userData) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t LPI2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + if (!(lpi2c->flags & I2C_FLAG_INIT)) + { + lpi2c->cb_event = cb_event; /* Call back function */ + lpi2c->flags = I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPI2C_InterruptUninitialize(cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + lpi2c->flags = I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +int32_t LPI2C_Master_InterruptTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + int32_t status; + int32_t ret; + lpi2c_master_transfer_t masterXfer; + + if (lpi2c->handle->master_handle.state != 0) + { + return ARM_DRIVER_ERROR_BUSY; /* Master is busy */ + } + + /* Create master_handle */ + LPI2C_MasterTransferCreateHandle(lpi2c->resource->base, &(lpi2c->handle->master_handle), + KSDK_LPI2C_MASTER_InterruptCallback, (void *)lpi2c->cb_event); + + /* Setup the master transfer */ + masterXfer.slaveAddress = addr; + masterXfer.direction = kLPI2C_Write; + masterXfer.subaddress = (uint32_t)NULL; + masterXfer.subaddressSize = 0; + masterXfer.data = (uint8_t *)data; + masterXfer.dataSize = num; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + + if (xfer_pending) + { + /* Stop condition will not be generated */ + masterXfer.flags |= kLPI2C_TransferNoStopFlag; + } + + /* Send master non-blocking data to slave */ + status = LPI2C_MasterTransferNonBlocking(lpi2c->resource->base, &(lpi2c->handle->master_handle), &masterXfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_LPI2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t LPI2C_Master_InterruptReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + int32_t status; + int32_t ret; + lpi2c_master_transfer_t masterXfer; + + if (lpi2c->handle->master_handle.state != 0) + { + /* Master is busy */ + return ARM_DRIVER_ERROR_BUSY; + } + + /* Create master_handle */ + LPI2C_MasterTransferCreateHandle(lpi2c->resource->base, &(lpi2c->handle->master_handle), + KSDK_LPI2C_MASTER_InterruptCallback, (void *)lpi2c->cb_event); + + /* Setup the master transfer */ + masterXfer.slaveAddress = addr; + masterXfer.direction = kLPI2C_Read; + masterXfer.subaddress = (uint32_t)NULL; + masterXfer.subaddressSize = 0; + masterXfer.data = data; + masterXfer.dataSize = num; + masterXfer.flags = kLPI2C_TransferDefaultFlag; + + if (xfer_pending) + { + /* Stop condition will not be generated */ + masterXfer.flags |= kLPI2C_TransferNoStopFlag; + } + + /* Receive non-blocking data from slave */ + status = LPI2C_MasterTransferNonBlocking(lpi2c->resource->base, &(lpi2c->handle->master_handle), &masterXfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_LPI2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t LPI2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + int32_t status; + int32_t ret; + + /* Create slave_handle */ + LPI2C_SlaveTransferCreateHandle(lpi2c->resource->base, &(lpi2c->handle->slave_handle), + lpi2c->handle->slave_handle.callback, (void *)lpi2c->cb_event); + + /* Slave send Nonblocking data to master */ + status = LPI2C_SlaveTransferNonBlocking(lpi2c->resource->base, &(lpi2c->handle->slave_handle), + kLPI2C_SlaveCompletionEvent); + + lpi2c->slave_data = (uint8_t *)data; /*!< slave Transfer buffer */ + lpi2c->slave_dataSize = num; /*!< slave Transfer data size */ + lpi2c->handle->slave_handle.transferredCount = 0; /*!< slave Transfered data count */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_LPI2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t LPI2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + int32_t status; + int32_t ret; + + /* Create slave_handle */ + LPI2C_SlaveTransferCreateHandle(lpi2c->resource->base, &(lpi2c->handle->slave_handle), + lpi2c->handle->slave_handle.callback, (void *)lpi2c->cb_event); + + /* Slave receive Nonblocking data from master */ + status = LPI2C_SlaveTransferNonBlocking(lpi2c->resource->base, &(lpi2c->handle->slave_handle), + kLPI2C_SlaveCompletionEvent); + + lpi2c->slave_data = data; /*!< slave Transfer buffer */ + lpi2c->slave_dataSize = num; /*!< slave Transfer data size */ + lpi2c->handle->slave_handle.transferredCount = 0; /*!< slave Transfered data count */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + + case kStatus_LPI2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t LPI2C_InterruptGetDataCount(cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + size_t cnt; + + if ((lpi2c->resource->base->SIER & kSlaveIrqFlags) == kSlaveIrqFlags) + { + /* In slave mode */ + LPI2C_SlaveTransferGetCount(lpi2c->resource->base, &lpi2c->handle->slave_handle, &cnt); + } + else + { + /* In master mode */ + LPI2C_MasterTransferGetCount(lpi2c->resource->base, &lpi2c->handle->master_handle, &cnt); + } + return cnt; +} + +int32_t LPI2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + uint32_t baudRate_Bps; + + switch (control) + { + case ARM_I2C_OWN_ADDRESS: + /* Set Own Slave Address */ + lpi2c->resource->base->SAMR = (arg << 1U); + return ARM_DRIVER_OK; + + case ARM_I2C_BUS_SPEED: + /* Set Bus Speed */ + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + LPI2C_MasterSetBaudRate(lpi2c->resource->base, lpi2c->resource->GetFreq(), baudRate_Bps); + + return ARM_DRIVER_OK; + + /* Not supported. */ + case ARM_I2C_BUS_CLEAR: + + return ARM_DRIVER_ERROR_UNSUPPORTED; + + /* Only support aborting data transfer when master transmit(in master mode) or slave receive(in slave mode) */ + case ARM_I2C_ABORT_TRANSFER: + /* Abort data transfer when slave receive(in slave mode) */ + if ((lpi2c->resource->base->SIER & kSlaveIrqFlags) == kSlaveIrqFlags) + { + /* Disable slave mode */ + lpi2c->resource->base->SCR = 0; + + /* Diable slave interrupt */ + LPI2C_SlaveTransferAbort(lpi2c->resource->base, &(lpi2c->handle->slave_handle)); + + /* Enable slave mode */ + lpi2c->resource->base->SCR = 0x31; + } + + /* Bort data transfer when master transmit abort(in master mode) */ + if ((lpi2c->resource->base->MIER & kMasterIrqFlags) == kMasterIrqFlags) + { + /* Disable master interrupt and send stop */ + LPI2C_MasterTransferAbort(lpi2c->resource->base, &(lpi2c->handle->master_handle)); + + lpi2c->handle->master_handle.remainingBytes = 0; + lpi2c->handle->master_handle.transfer.data = NULL; + lpi2c->handle->master_handle.transfer.dataSize = 0; + } + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +static int32_t LPI2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + switch (state) + { + lpi2c_slave_config_t slaveConfig; + lpi2c_master_config_t masterConfig; + + case ARM_POWER_OFF: + if (lpi2c->flags & I2C_FLAG_POWER) + { + /* Terminates any pending data transfers */ + LPI2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, lpi2c); + + /* Disables peripheral */ + LPI2C_MasterDeinit(lpi2c->resource->base); + lpi2c->flags = I2C_FLAG_INIT; + } + return ARM_DRIVER_OK; + + case ARM_POWER_LOW: + + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + + if (lpi2c->flags == I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpi2c->flags & I2C_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + /* + * slaveConfig.address0 = 0U; + * slaveConfig.address1 = 0U; + * slaveConfig.addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig.filterDozeEnable = true; + * slaveConfig.filterEnable = true; + * slaveConfig.enableGeneralCall = false; + * slaveConfig.ignoreAck = false; + * slaveConfig.enableReceivedAddressRead = false; + * slaveConfig.sdaGlitchFilterWidth_ns = 0; + * slaveConfig.sclGlitchFilterWidth_ns = 0; + * slaveConfig.dataValidDelay_ns = 0; + * slaveConfig.clockHoldTime_ns = 0; + */ + LPI2C_SlaveGetDefaultConfig(&slaveConfig); + + /* Initialize the LPI2C slave peripheral */ + LPI2C_SlaveInit(lpi2c->resource->base, &slaveConfig, lpi2c->resource->GetFreq()); + + /* + * masterConfig.debugEnable = false; + * masterConfig.ignoreAck = false; + * masterConfig.pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig.baudRate_Hz = 100000U; + * masterConfig.busIdleTimeout_ns = 0; + * masterConfig.pinLowTimeout_ns = 0; + * masterConfig.sdaGlitchFilterWidth_ns = 0; + * masterConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&masterConfig); + + /* Initialize the LPI2C master peripheral */ + LPI2C_MasterInit(lpi2c->resource->base, &masterConfig, lpi2c->resource->GetFreq()); + + lpi2c->flags |= I2C_FLAG_POWER; + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +ARM_I2C_STATUS LPI2C_InterruptGetStatus(cmsis_lpi2c_interrupt_driver_state_t *lpi2c) +{ + ARM_I2C_STATUS stat = {0}; + uint32_t ksdk_lpi2c_master_status = LPI2C_MasterGetStatusFlags(lpi2c->resource->base); + uint32_t ksdk_lpi2c_slave_status = LPI2C_SlaveGetStatusFlags(lpi2c->resource->base); + + /* Busy flag */ + stat.busy = + !(!((ksdk_lpi2c_master_status & kLPI2C_MasterBusyFlag) | (ksdk_lpi2c_slave_status & kLPI2C_SlaveBusyFlag))); + + /* Mode: 0=Slave, 1=Master */ + if ((lpi2c->resource->base->SIER & kSlaveIrqFlags) == kSlaveIrqFlags) + { + stat.mode = 0; + } + else + { + stat.mode = 1; + } + + /* Direction: 0=Transmitter, 1=Receiver */ + stat.direction = lpi2c->handle->master_handle.transfer.direction; + + /* Master lost arbitration */ + stat.arbitration_lost = !(!(ksdk_lpi2c_master_status & kLPI2C_MasterArbitrationLostFlag)); + + return stat; +} + +#endif + +#if defined(LPI2C0) && RTE_I2C0 +/* User needs to provide the implementation for LPI2C0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C0_GetFreq(void); +extern void LPI2C0_InitPins(void); +extern void LPI2C0_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C0_Resource = {LPI2C0, LPI2C0_GetFreq}; + +#if RTE_I2C0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C0_EdmaResource = { + RTE_I2C0_DMA_TX_DMA_BASE, RTE_I2C0_DMA_TX_CH, RTE_I2C0_DMA_TX_PERI_SEL, + RTE_I2C0_DMA_RX_DMA_BASE, RTE_I2C0_DMA_RX_CH, RTE_I2C0_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C0_DMA_TX_DMAMUX_BASE, RTE_I2C0_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C0_EdmaHandle); +edma_handle_t LPI2C0_EdmaTxHandle; +edma_handle_t LPI2C0_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c0_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C0_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C0_EdmaDriverState = { +#endif + &LPI2C0_Resource, &LPI2C0_EdmaResource, &LPI2C0_EdmaHandle, &LPI2C0_EdmaTxHandle, &LPI2C0_EdmaRxHandle, +}; + +static int32_t LPI2C0_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C0_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C0_EdmaDriverState); +} + +int32_t LPI2C0_Master_EdmaUninitialize(void) +{ + LPI2C0_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C0_EdmaDriverState); +} + +int32_t LPI2C0_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C0_EdmaDriverState); +} + +int32_t LPI2C0_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C0_EdmaDriverState); +} + +int32_t LPI2C0_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C0_EdmaDriverState); +} + +int32_t LPI2C0_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C0_EdmaDriverState); +} + +int32_t LPI2C0_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C0_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C0_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C0_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C0_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c0_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C0_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C0_InterruptDriverState = { +#endif + &LPI2C0_Resource, &LPI2C0_Handle, + +}; + +static void KSDK_LPI2C0_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C0_InterruptDriverState); +} + +static int32_t LPI2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C0_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C0_InterruptDriverState); +} + +static int32_t LPI2C0_InterruptUninitialize(void) +{ + LPI2C0_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C0_InterruptDriverState); +} + +static int32_t LPI2C0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C0_InterruptDriverState); +} + +int32_t LPI2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C0_InterruptDriverState); +} + +int32_t LPI2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C0_InterruptDriverState); +} + +int32_t LPI2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C0_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C0_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C0_InterruptDriverState); +} + +int32_t LPI2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C0_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C0_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C0_InterruptDriverState); +} + +int32_t LPI2C0_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C0_InterruptDriverState); +} + +int32_t LPI2C0_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C0_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C0_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C0_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C0 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C0_DMA_EN + LPI2C0_Master_EdmaInitialize, LPI2C0_Master_EdmaUninitialize, + LPI2C0_Master_EdmaPowerControl, LPI2C0_Master_EdmaTransmit, LPI2C0_Master_EdmaReceive, + NULL, NULL, LPI2C0_Master_EdmaGetDataCount, LPI2C0_Master_EdmaControl, + LPI2C0_Master_EdmaGetStatus +#else + LPI2C0_InterruptInitialize, LPI2C0_InterruptUninitialize, LPI2C0_InterruptPowerControl, + LPI2C0_Master_InterruptTransmit, LPI2C0_Master_InterruptReceive, + LPI2C0_Slave_InterruptTransmit, LPI2C0_Slave_InterruptReceive, + LPI2C0_InterruptGetDataCount, LPI2C0_InterruptControl, LPI2C0_InterruptGetStatus +#endif +}; + +#endif + +#if defined(LPI2C1) && RTE_I2C1 +/* User needs to provide the implementation for LPI2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C1_GetFreq(void); +extern void LPI2C1_InitPins(void); +extern void LPI2C1_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C1_Resource = {LPI2C1, LPI2C1_GetFreq}; + +#if RTE_I2C1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C1_EdmaResource = { + RTE_I2C1_DMA_TX_DMA_BASE, RTE_I2C1_DMA_TX_CH, RTE_I2C1_DMA_TX_PERI_SEL, + RTE_I2C1_DMA_RX_DMA_BASE, RTE_I2C1_DMA_RX_CH, RTE_I2C1_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C1_DMA_TX_DMAMUX_BASE, RTE_I2C1_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C1_EdmaHandle); +edma_handle_t LPI2C1_EdmaTxHandle; +edma_handle_t LPI2C1_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c1_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C1_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C1_EdmaDriverState = { +#endif + &LPI2C1_Resource, &LPI2C1_EdmaResource, &LPI2C1_EdmaHandle, &LPI2C1_EdmaTxHandle, &LPI2C1_EdmaRxHandle, +}; + +static int32_t LPI2C1_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C1_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C1_EdmaDriverState); +} + +int32_t LPI2C1_Master_EdmaUninitialize(void) +{ + LPI2C1_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C1_EdmaDriverState); +} + +int32_t LPI2C1_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C1_EdmaDriverState); +} + +int32_t LPI2C1_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C1_EdmaDriverState); +} + +int32_t LPI2C1_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C1_EdmaDriverState); +} + +int32_t LPI2C1_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C1_EdmaDriverState); +} + +int32_t LPI2C1_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C1_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C1_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C1_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C1_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c1_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C1_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C1_InterruptDriverState = { +#endif + &LPI2C1_Resource, &LPI2C1_Handle, +}; + +static void KSDK_LPI2C1_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C1_InterruptDriverState); +} + +static int32_t LPI2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C1_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C1_InterruptDriverState); +} + +static int32_t LPI2C1_InterruptUninitialize(void) +{ + LPI2C1_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C1_InterruptDriverState); +} + +static int32_t LPI2C1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C1_InterruptDriverState); +} + +int32_t LPI2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C1_InterruptDriverState); +} + +int32_t LPI2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C1_InterruptDriverState); +} + +int32_t LPI2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C1_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C1_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C1_InterruptDriverState); +} + +int32_t LPI2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C1_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C1_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C1_InterruptDriverState); +} + +int32_t LPI2C1_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C1_InterruptDriverState); +} + +int32_t LPI2C1_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C1_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C1_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C1 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C1_DMA_EN + LPI2C1_Master_EdmaInitialize, LPI2C1_Master_EdmaUninitialize, + LPI2C1_Master_EdmaPowerControl, LPI2C1_Master_EdmaTransmit, LPI2C1_Master_EdmaReceive, + NULL, NULL, LPI2C1_Master_EdmaGetDataCount, LPI2C1_Master_EdmaControl, + LPI2C1_Master_EdmaGetStatus +#else + LPI2C1_InterruptInitialize, LPI2C1_InterruptUninitialize, LPI2C1_InterruptPowerControl, + LPI2C1_Master_InterruptTransmit, LPI2C1_Master_InterruptReceive, + LPI2C1_Slave_InterruptTransmit, LPI2C1_Slave_InterruptReceive, + LPI2C1_InterruptGetDataCount, LPI2C1_InterruptControl, LPI2C1_InterruptGetStatus +#endif +}; + +#endif + +#if defined(LPI2C2) && RTE_I2C2 +/* User needs to provide the implementation for LPI2C2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C2_GetFreq(void); +extern void LPI2C2_InitPins(void); +extern void LPI2C2_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C2_Resource = {LPI2C2, LPI2C2_GetFreq}; + +#if RTE_I2C2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C2_EdmaResource = { + RTE_I2C2_DMA_TX_DMA_BASE, RTE_I2C2_DMA_TX_CH, RTE_I2C2_DMA_TX_PERI_SEL, + RTE_I2C2_DMA_RX_DMA_BASE, RTE_I2C2_DMA_RX_CH, RTE_I2C2_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C2_DMA_TX_DMAMUX_BASE, RTE_I2C2_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C2_EdmaHandle); +edma_handle_t LPI2C2_EdmaTxHandle; +edma_handle_t LPI2C2_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c2_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C2_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C2_EdmaDriverState = { +#endif + &LPI2C2_Resource, &LPI2C2_EdmaResource, &LPI2C2_EdmaHandle, &LPI2C2_EdmaTxHandle, &LPI2C2_EdmaRxHandle, +}; + +static int32_t LPI2C2_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C2_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C2_EdmaDriverState); +} + +int32_t LPI2C2_Master_EdmaUninitialize(void) +{ + LPI2C2_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C2_EdmaDriverState); +} + +int32_t LPI2C2_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C2_EdmaDriverState); +} + +int32_t LPI2C2_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C2_EdmaDriverState); +} + +int32_t LPI2C2_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C2_EdmaDriverState); +} + +int32_t LPI2C2_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C2_EdmaDriverState); +} + +int32_t LPI2C2_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C2_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C2_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C2_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C2_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c2_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C2_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C2_InterruptDriverState = { +#endif + &LPI2C2_Resource, &LPI2C2_Handle, + +}; + +static void KSDK_LPI2C2_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C2_InterruptDriverState); +} + +static int32_t LPI2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C2_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C2_InterruptDriverState); +} + +static int32_t LPI2C2_InterruptUninitialize(void) +{ + LPI2C2_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C2_InterruptDriverState); +} + +static int32_t LPI2C2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C2_InterruptDriverState); +} + +int32_t LPI2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C2_InterruptDriverState); +} + +int32_t LPI2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C2_InterruptDriverState); +} + +int32_t LPI2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C2_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C2_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C2_InterruptDriverState); +} + +int32_t LPI2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C2_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C2_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C2_InterruptDriverState); +} + +int32_t LPI2C2_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C2_InterruptDriverState); +} + +int32_t LPI2C2_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C2_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C2_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C2 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C2_DMA_EN + LPI2C2_Master_EdmaInitialize, LPI2C2_Master_EdmaUninitialize, + LPI2C2_Master_EdmaPowerControl, LPI2C2_Master_EdmaTransmit, LPI2C2_Master_EdmaReceive, + NULL, NULL, LPI2C2_Master_EdmaGetDataCount, LPI2C2_Master_EdmaControl, + LPI2C2_Master_EdmaGetStatus +#else + LPI2C2_InterruptInitialize, LPI2C2_InterruptUninitialize, LPI2C2_InterruptPowerControl, + LPI2C2_Master_InterruptTransmit, LPI2C2_Master_InterruptReceive, + LPI2C2_Slave_InterruptTransmit, LPI2C2_Slave_InterruptReceive, + LPI2C2_InterruptGetDataCount, LPI2C2_InterruptControl, LPI2C2_InterruptGetStatus +#endif +}; + +#endif + +#if defined(LPI2C3) && RTE_I2C3 +/* User needs to provide the implementation for LPI2C3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C3_GetFreq(void); +extern void LPI2C3_InitPins(void); +extern void LPI2C3_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C3_Resource = {LPI2C3, LPI2C3_GetFreq}; + +#if RTE_I2C3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C3_EdmaResource = { + RTE_I2C3_DMA_TX_DMA_BASE, RTE_I2C3_DMA_TX_CH, RTE_I2C3_DMA_TX_PERI_SEL, + RTE_I2C3_DMA_RX_DMA_BASE, RTE_I2C3_DMA_RX_CH, RTE_I2C3_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C3_DMA_TX_DMAMUX_BASE, RTE_I2C3_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C3_EdmaHandle); +edma_handle_t LPI2C3_EdmaTxHandle; +edma_handle_t LPI2C3_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c3_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C3_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C3_EdmaDriverState = { +#endif + &LPI2C3_Resource, &LPI2C3_EdmaResource, &LPI2C3_EdmaHandle, &LPI2C3_EdmaTxHandle, &LPI2C3_EdmaRxHandle, +}; + +static int32_t LPI2C3_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C3_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C3_EdmaDriverState); +} + +int32_t LPI2C3_Master_EdmaUninitialize(void) +{ + LPI2C3_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C3_EdmaDriverState); +} + +int32_t LPI2C3_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C3_EdmaDriverState); +} + +int32_t LPI2C3_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C3_EdmaDriverState); +} + +int32_t LPI2C3_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C3_EdmaDriverState); +} + +int32_t LPI2C3_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C3_EdmaDriverState); +} + +int32_t LPI2C3_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C3_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C3_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C3_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C3_Handle; +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c3_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C3_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C3_InterruptDriverState = { +#endif + &LPI2C3_Resource, &LPI2C3_Handle, +}; + +static void KSDK_LPI2C3_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C3_InterruptDriverState); +} + +static int32_t LPI2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C3_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C3_InterruptDriverState); +} + +static int32_t LPI2C3_InterruptUninitialize(void) +{ + LPI2C3_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C3_InterruptDriverState); +} + +static int32_t LPI2C3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C3_InterruptDriverState); +} + +int32_t LPI2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C3_InterruptDriverState); +} + +int32_t LPI2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C3_InterruptDriverState); +} + +int32_t LPI2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C3_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C3_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C3_InterruptDriverState); +} + +int32_t LPI2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C3_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C3_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C3_InterruptDriverState); +} + +int32_t LPI2C3_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C3_InterruptDriverState); +} + +int32_t LPI2C3_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C3_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C3_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C3_InterruptDriverState); +} + +#endif /* RTE_I2C3_DMA_EN */ + +ARM_DRIVER_I2C Driver_I2C3 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C3_DMA_EN + LPI2C3_Master_EdmaInitialize, LPI2C3_Master_EdmaUninitialize, + LPI2C3_Master_EdmaPowerControl, LPI2C3_Master_EdmaTransmit, LPI2C3_Master_EdmaReceive, + NULL, NULL, LPI2C3_Master_EdmaGetDataCount, LPI2C3_Master_EdmaControl, + LPI2C3_Master_EdmaGetStatus +#else + LPI2C3_InterruptInitialize, LPI2C3_InterruptUninitialize, LPI2C3_InterruptPowerControl, + LPI2C3_Master_InterruptTransmit, LPI2C3_Master_InterruptReceive, + LPI2C3_Slave_InterruptTransmit, LPI2C3_Slave_InterruptReceive, + LPI2C3_InterruptGetDataCount, LPI2C3_InterruptControl, LPI2C3_InterruptGetStatus +#endif /* RTE_I2C3_DMA_EN */ +}; + +#endif + +#if defined(LPI2C4) && RTE_I2C4 +/* User needs to provide the implementation for LPI2C4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C4_GetFreq(void); +extern void LPI2C4_InitPins(void); +extern void LPI2C4_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C4_Resource = {LPI2C4, LPI2C4_GetFreq}; + +#if RTE_I2C4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C4_EdmaResource = { + RTE_I2C4_DMA_TX_DMA_BASE, RTE_I2C4_DMA_TX_CH, RTE_I2C4_DMA_TX_PERI_SEL, + RTE_I2C4_DMA_RX_DMA_BASE, RTE_I2C4_DMA_RX_CH, RTE_I2C4_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C4_DMA_TX_DMAMUX_BASE, RTE_I2C4_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C4_EdmaHandle); +edma_handle_t LPI2C4_EdmaTxHandle; +edma_handle_t LPI2C4_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c4_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C4_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C4_EdmaDriverState = { +#endif + &LPI2C4_Resource, &LPI2C4_EdmaResource, &LPI2C4_EdmaHandle, &LPI2C4_EdmaTxHandle, &LPI2C4_EdmaRxHandle, +}; + +static int32_t LPI2C4_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C4_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C4_EdmaDriverState); +} + +int32_t LPI2C4_Master_EdmaUninitialize(void) +{ + LPI2C4_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C4_EdmaDriverState); +} + +int32_t LPI2C4_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C4_EdmaDriverState); +} + +int32_t LPI2C4_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C4_EdmaDriverState); +} + +int32_t LPI2C4_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C4_EdmaDriverState); +} + +int32_t LPI2C4_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C4_EdmaDriverState); +} + +int32_t LPI2C4_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C4_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C4_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C4_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C4_Handle; +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c4_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C4_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C4_InterruptDriverState = { +#endif + &LPI2C4_Resource, &LPI2C4_Handle, +}; + +static void KSDK_LPI2C4_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C4_InterruptDriverState); +} + +static int32_t LPI2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C4_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C4_InterruptDriverState); +} + +static int32_t LPI2C4_InterruptUninitialize(void) +{ + LPI2C4_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C4_InterruptDriverState); +} + +static int32_t LPI2C4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C4_InterruptDriverState); +} + +int32_t LPI2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C4_InterruptDriverState); +} + +int32_t LPI2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C4_InterruptDriverState); +} + +int32_t LPI2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C4_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C4_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C4_InterruptDriverState); +} + +int32_t LPI2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C4_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C4_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C4_InterruptDriverState); +} + +int32_t LPI2C4_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C4_InterruptDriverState); +} + +int32_t LPI2C4_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C4_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C4_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C4_InterruptDriverState); +} + +#endif /* RTE_I2C4_DMA_EN */ + +ARM_DRIVER_I2C Driver_I2C4 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C4_DMA_EN + LPI2C4_Master_EdmaInitialize, LPI2C4_Master_EdmaUninitialize, + LPI2C4_Master_EdmaPowerControl, LPI2C4_Master_EdmaTransmit, LPI2C4_Master_EdmaReceive, + NULL, NULL, LPI2C4_Master_EdmaGetDataCount, LPI2C4_Master_EdmaControl, + LPI2C4_Master_EdmaGetStatus +#else + LPI2C4_InterruptInitialize, LPI2C4_InterruptUninitialize, LPI2C4_InterruptPowerControl, + LPI2C4_Master_InterruptTransmit, LPI2C4_Master_InterruptReceive, + LPI2C4_Slave_InterruptTransmit, LPI2C4_Slave_InterruptReceive, + LPI2C4_InterruptGetDataCount, LPI2C4_InterruptControl, LPI2C4_InterruptGetStatus +#endif /* RTE_I2C4_DMA_EN */ +}; + +#endif + +#if defined(LPI2C5) && RTE_I2C5 +/* User needs to provide the implementation for LPI2C5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C5_GetFreq(void); +extern void LPI2C5_InitPins(void); +extern void LPI2C5_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C5_Resource = {LPI2C5, LPI2C5_GetFreq}; + +#if RTE_I2C5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C5_EdmaResource = { + RTE_I2C5_DMA_TX_DMA_BASE, RTE_I2C5_DMA_TX_CH, RTE_I2C5_DMA_TX_PERI_SEL, + RTE_I2C5_DMA_RX_DMA_BASE, RTE_I2C5_DMA_RX_CH, RTE_I2C5_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C5_DMA_TX_DMAMUX_BASE, RTE_I2C5_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C5_EdmaHandle); +edma_handle_t LPI2C5_EdmaTxHandle; +edma_handle_t LPI2C5_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c5_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C5_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C5_EdmaDriverState = { +#endif + &LPI2C5_Resource, &LPI2C5_EdmaResource, &LPI2C5_EdmaHandle, &LPI2C5_EdmaTxHandle, &LPI2C5_EdmaRxHandle, +}; + +static int32_t LPI2C5_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C5_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C5_EdmaDriverState); +} + +int32_t LPI2C5_Master_EdmaUninitialize(void) +{ + LPI2C5_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C5_EdmaDriverState); +} + +int32_t LPI2C5_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C5_EdmaDriverState); +} + +int32_t LPI2C5_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C5_EdmaDriverState); +} + +int32_t LPI2C5_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C5_EdmaDriverState); +} + +int32_t LPI2C5_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C5_EdmaDriverState); +} + +int32_t LPI2C5_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C5_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C5_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C5_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C5_Handle; +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c5_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C5_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C5_InterruptDriverState = { +#endif + &LPI2C5_Resource, &LPI2C5_Handle, +}; + +static void KSDK_LPI2C5_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C5_InterruptDriverState); +} + +static int32_t LPI2C5_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C5_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C5_InterruptDriverState); +} + +static int32_t LPI2C5_InterruptUninitialize(void) +{ + LPI2C5_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C5_InterruptDriverState); +} + +static int32_t LPI2C5_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C5_InterruptDriverState); +} + +int32_t LPI2C5_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C5_InterruptDriverState); +} + +int32_t LPI2C5_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C5_InterruptDriverState); +} + +int32_t LPI2C5_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C5_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C5_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C5_InterruptDriverState); +} + +int32_t LPI2C5_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C5_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C5_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C5_InterruptDriverState); +} + +int32_t LPI2C5_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C5_InterruptDriverState); +} + +int32_t LPI2C5_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C5_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C5_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C5_InterruptDriverState); +} + +#endif /* RTE_I2C5_DMA_EN */ + +ARM_DRIVER_I2C Driver_I2C5 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C5_DMA_EN + LPI2C5_Master_EdmaInitialize, LPI2C5_Master_EdmaUninitialize, + LPI2C5_Master_EdmaPowerControl, LPI2C5_Master_EdmaTransmit, LPI2C5_Master_EdmaReceive, + NULL, NULL, LPI2C5_Master_EdmaGetDataCount, LPI2C5_Master_EdmaControl, + LPI2C5_Master_EdmaGetStatus +#else + LPI2C5_InterruptInitialize, LPI2C5_InterruptUninitialize, LPI2C5_InterruptPowerControl, + LPI2C5_Master_InterruptTransmit, LPI2C5_Master_InterruptReceive, + LPI2C5_Slave_InterruptTransmit, LPI2C5_Slave_InterruptReceive, + LPI2C5_InterruptGetDataCount, LPI2C5_InterruptControl, LPI2C5_InterruptGetStatus +#endif /* RTE_I2C5_DMA_EN */ +}; + +#endif /* LPI2C5 */ + +#if defined(LPI2C6) && RTE_I2C6 +/* User needs to provide the implementation for LPI2C6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPI2C6_GetFreq(void); +extern void LPI2C6_InitPins(void); +extern void LPI2C6_DeinitPins(void); + +cmsis_lpi2c_resource_t LPI2C6_Resource = {LPI2C6, LPI2C6_GetFreq}; + +#if RTE_I2C6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpi2c_edma_resource_t LPI2C6_EdmaResource = { + RTE_I2C6_DMA_TX_DMA_BASE, RTE_I2C6_DMA_TX_CH, RTE_I2C6_DMA_TX_PERI_SEL, + RTE_I2C6_DMA_RX_DMA_BASE, RTE_I2C6_DMA_RX_CH, RTE_I2C6_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_I2C6_DMA_TX_DMAMUX_BASE, RTE_I2C6_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C6_EdmaHandle); +edma_handle_t LPI2C6_EdmaTxHandle; +edma_handle_t LPI2C6_EdmaRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c6_edma_driver_state") +cmsis_lpi2c_edma_driver_state_t LPI2C6_EdmaDriverState = { +#else +cmsis_lpi2c_edma_driver_state_t LPI2C6_EdmaDriverState = { +#endif + &LPI2C6_Resource, &LPI2C6_EdmaResource, &LPI2C6_EdmaHandle, &LPI2C6_EdmaTxHandle, &LPI2C6_EdmaRxHandle, +}; + +static int32_t LPI2C6_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C6_InitPins(); + return LPI2C_Master_EdmaInitialize(cb_event, &LPI2C6_EdmaDriverState); +} + +int32_t LPI2C6_Master_EdmaUninitialize(void) +{ + LPI2C6_DeinitPins(); + return LPI2C_Master_EdmaUninitialize(&LPI2C6_EdmaDriverState); +} + +int32_t LPI2C6_Master_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_Master_EdmaPowerControl(state, &LPI2C6_EdmaDriverState); +} + +int32_t LPI2C6_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &LPI2C6_EdmaDriverState); +} + +int32_t LPI2C6_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_EdmaReceive(addr, data, num, xfer_pending, &LPI2C6_EdmaDriverState); +} + +int32_t LPI2C6_Master_EdmaGetDataCount(void) +{ + return LPI2C_Master_EdmaGetDataCount(&LPI2C6_EdmaDriverState); +} + +int32_t LPI2C6_Master_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPI2C_Master_EdmaControl(control, arg, &LPI2C6_EdmaDriverState); +} + +ARM_I2C_STATUS LPI2C6_Master_EdmaGetStatus(void) +{ + return LPI2C_Master_EdmaGetStatus(&LPI2C6_EdmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t LPI2C6_Handle; +#if defined(__CC_ARM) +ARMCC_SECTION("lpi2c6_interrupt_driver_state") +cmsis_lpi2c_interrupt_driver_state_t LPI2C6_InterruptDriverState = { +#else +cmsis_lpi2c_interrupt_driver_state_t LPI2C6_InterruptDriverState = { +#endif + &LPI2C6_Resource, &LPI2C6_Handle, +}; + +static void KSDK_LPI2C6_SLAVE_InterruptCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *userData) +{ + KSDK_LPI2C_SLAVE_InterruptCallback(base, xfer, userData, &LPI2C6_InterruptDriverState); +} + +static int32_t LPI2C6_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + LPI2C6_InitPins(); + return LPI2C_InterruptInitialize(cb_event, &LPI2C6_InterruptDriverState); +} + +static int32_t LPI2C6_InterruptUninitialize(void) +{ + LPI2C6_DeinitPins(); + return LPI2C_InterruptUninitialize(&LPI2C6_InterruptDriverState); +} + +static int32_t LPI2C6_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPI2C_InterruptPowerControl(state, &LPI2C6_InterruptDriverState); +} + +int32_t LPI2C6_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &LPI2C6_InterruptDriverState); +} + +int32_t LPI2C6_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return LPI2C_Master_InterruptReceive(addr, data, num, xfer_pending, &LPI2C6_InterruptDriverState); +} + +int32_t LPI2C6_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + LPI2C6_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C6_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptTransmit(data, num, &LPI2C6_InterruptDriverState); +} + +int32_t LPI2C6_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + LPI2C6_InterruptDriverState.handle->slave_handle.callback = KSDK_LPI2C6_SLAVE_InterruptCallback; + return LPI2C_Slave_InterruptReceive(data, num, &LPI2C6_InterruptDriverState); +} + +int32_t LPI2C6_InterruptGetDataCount(void) +{ + return LPI2C_InterruptGetDataCount(&LPI2C6_InterruptDriverState); +} + +int32_t LPI2C6_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPI2C_InterruptControl(control, arg, &LPI2C6_InterruptDriverState); +} + +ARM_I2C_STATUS LPI2C6_InterruptGetStatus(void) +{ + return LPI2C_InterruptGetStatus(&LPI2C6_InterruptDriverState); +} + +#endif /* RTE_I2C6_DMA_EN */ + +ARM_DRIVER_I2C Driver_I2C6 = {LPI2Cx_GetVersion, LPI2Cx_GetCapabilities, +#if RTE_I2C6_DMA_EN + LPI2C6_Master_EdmaInitialize, LPI2C6_Master_EdmaUninitialize, + LPI2C6_Master_EdmaPowerControl, LPI2C6_Master_EdmaTransmit, LPI2C6_Master_EdmaReceive, + NULL, NULL, LPI2C6_Master_EdmaGetDataCount, LPI2C6_Master_EdmaControl, + LPI2C6_Master_EdmaGetStatus +#else + LPI2C6_InterruptInitialize, LPI2C6_InterruptUninitialize, LPI2C6_InterruptPowerControl, + LPI2C6_Master_InterruptTransmit, LPI2C6_Master_InterruptReceive, + LPI2C6_Slave_InterruptTransmit, LPI2C6_Slave_InterruptReceive, + LPI2C6_InterruptGetDataCount, LPI2C6_InterruptControl, LPI2C6_InterruptGetStatus +#endif /* RTE_I2C6_DMA_EN */ +}; + +#endif /* LPI2C6 */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.h new file mode 100644 index 0000000000..9db2c51777 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FSL_LPI2C_CMSIS_H_ +#define _FSL_LPI2C_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_I2C.h" +#include "RTE_Device.h" +#include "fsl_lpi2c.h" +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) +#include "fsl_dmamux.h" +#endif +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_lpi2c_dma.h" +#endif +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +#include "fsl_lpi2c_edma.h" +#endif + +#if defined(LPI2C0) +extern ARM_DRIVER_I2C Driver_I2C0; +#endif /* LPI2C0 */ + +#if defined(LPI2C1) +extern ARM_DRIVER_I2C Driver_I2C1; +#endif /* LPI2C1 */ + +#if defined(LPI2C2) +extern ARM_DRIVER_I2C Driver_I2C2; +#endif /* LPI2C2 */ + +#if defined(LPI2C3) +extern ARM_DRIVER_I2C Driver_I2C3; +#endif /* LPI2C3 */ + +#if defined(LPI2C4) +extern ARM_DRIVER_I2C Driver_I2C4; +#endif /* LPI2C4 */ + +#if defined(LPI2C5) +extern ARM_DRIVER_I2C Driver_I2C5; +#endif /* LPI2C5*/ + +#if defined(LPI2C6) +extern ARM_DRIVER_I2C Driver_I2C6; +#endif /* LPI2C6 */ + +/* I2C Driver state flags */ +#define I2C_FLAG_UNINIT (0) +#define I2C_FLAG_INIT (1 << 0) +#define I2C_FLAG_POWER (1 << 1) + +#endif /* _FSL_LPI2C_CMSIS_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.c new file mode 100644 index 0000000000..09608a7623 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.c @@ -0,0 +1,2183 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "fsl_lpspi_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi_cmsis" +#endif + + +#if ((RTE_SPI0 && defined(LPSPI0)) || (RTE_SPI1 && defined(LPSPI1)) || (RTE_SPI2 && defined(LPSPI2)) || \ + (RTE_SPI3 && defined(LPSPI3)) || (RTE_SPI4 && defined(LPSPI4)) || (RTE_SPI5 && defined(LPSPI5))) + +#define ARM_LPSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 1) /* driver version */ + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +static clock_ip_name_t const s_lpspiClock[] = LPSPI_CLOCKS; + +typedef const struct _cmsis_lpspi_resource +{ + LPSPI_Type *base; + uint32_t instance; + uint32_t (*GetFreq)(void); +} cmsis_lpspi_resource_t; + +typedef union _cmsis_lpspi_handle +{ + lpspi_master_handle_t masterHandle; + lpspi_slave_handle_t slaveHandle; +} cmsis_lpspi_handle_t; + +typedef struct _cmsis_lpspi_interrupt_driver_state +{ + cmsis_lpspi_resource_t *resource; + cmsis_lpspi_handle_t *handle; + ARM_SPI_SignalEvent_t cb_event; + uint32_t baudRate_Bps; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpspi_interrupt_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +typedef const struct _cmsis_lpspi_edma_resource +{ + DMA_Type *txEdmaBase; + uint32_t txEdmaChannel; + uint8_t txDmaRequest; + + DMA_Type *rxEdmaBase; + uint32_t rxEdmaChannel; + uint8_t rxDmaRequest; + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_Type *txDmamuxBase; + DMAMUX_Type *rxDmamuxBase; +#endif +} cmsis_lpspi_edma_resource_t; + +typedef union _cmsis_lpspi_edma_handle +{ + lpspi_master_edma_handle_t masterHandle; + lpspi_slave_edma_handle_t slaveHandle; +} cmsis_lpspi_edma_handle_t; + +typedef struct _cmsis_lpspi_edma_driver_state +{ + cmsis_lpspi_resource_t *resource; + cmsis_lpspi_edma_resource_t *dmaResource; + cmsis_lpspi_edma_handle_t *handle; + edma_handle_t *edmaRxRegToRxDataHandle; + edma_handle_t *edmaTxDataToTxRegHandle; + ARM_SPI_SignalEvent_t cb_event; + uint32_t baudRate_Bps; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpspi_edma_driver_state_t; +#endif + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_lpspiDriverVersion = {ARM_SPI_API_VERSION, ARM_LPSPI_DRV_VERSION}; + +/* Driver Capabilities */ +static const ARM_SPI_CAPABILITIES s_lpspiDriverCapabilities = { + 1, /* Simplex Mode (Master and Slave) */ + 0, /* TI Synchronous Serial Interface */ + 0, /* Microwire Interface */ + 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ +}; + +/* + *Common Control function used by LPSPI_InterruptControl / LPSPI_EdmaControl. + */ +static int32_t LPSPI_CommonControl(uint32_t control, + uint32_t arg, + cmsis_lpspi_resource_t *resource, + uint8_t *isConfigured) +{ + lpspi_master_config_t masterConfig; + LPSPI_MasterGetDefaultConfig(&masterConfig); + lpspi_slave_config_t slaveConfig; + LPSPI_SlaveGetDefaultConfig(&slaveConfig); + masterConfig.baudRate = arg; + + if (ARM_SPI_MODE_MASTER_SIMPLEX == (control & ARM_SPI_CONTROL_Msk)) + { + masterConfig.pinCfg = kLPSPI_SdoInSdoOut; + } + if (ARM_SPI_MODE_SLAVE_SIMPLEX == (control & ARM_SPI_CONTROL_Msk)) + { + slaveConfig.pinCfg = kLPSPI_SdiInSdiOut; + } + +#if (defined(RTE_SPI0_PCS_TO_SCK_DELAY) && defined(RTE_SPI0_SCK_TO_PSC_DELAY) && \ + defined(RTE_SPI0_BETWEEN_TRANSFER_DELAY)) + if (0U == resource->instance) + { + masterConfig.pcsToSckDelayInNanoSec = RTE_SPI0_PCS_TO_SCK_DELAY; + masterConfig.lastSckToPcsDelayInNanoSec = RTE_SPI0_SCK_TO_PSC_DELAY; + masterConfig.betweenTransferDelayInNanoSec = RTE_SPI0_BETWEEN_TRANSFER_DELAY; + } +#endif /*RTE LPSPI0 trnafer delay time configure */ + +#if (defined(RTE_SPI1_PCS_TO_SCK_DELAY) && defined(RTE_SPI1_SCK_TO_PSC_DELAY) && \ + defined(RTE_SPI1_BETWEEN_TRANSFER_DELAY)) + if (1U == resource->instance) + { + masterConfig.pcsToSckDelayInNanoSec = RTE_SPI1_PCS_TO_SCK_DELAY; + masterConfig.lastSckToPcsDelayInNanoSec = RTE_SPI1_SCK_TO_PSC_DELAY; + masterConfig.betweenTransferDelayInNanoSec = RTE_SPI1_BETWEEN_TRANSFER_DELAY; + } +#endif /*RTE LPSPI1 trnafer delay time configure */ + +#if (defined(RTE_SPI2_PCS_TO_SCK_DELAY) && defined(RTE_SPI2_SCK_TO_PSC_DELAY) && \ + defined(RTE_SPI2_BETWEEN_TRANSFER_DELAY)) + if (2U == resource->instance) + { + masterConfig.pcsToSckDelayInNanoSec = RTE_SPI2_PCS_TO_SCK_DELAY; + masterConfig.lastSckToPcsDelayInNanoSec = RTE_SPI2_SCK_TO_PSC_DELAY; + masterConfig.betweenTransferDelayInNanoSec = RTE_SPI2_BETWEEN_TRANSFER_DELAY; + } +#endif /*RTE LPSPI2 trnafer delay time configure */ +#if (defined(RTE_SPI3_PCS_TO_SCK_DELAY) && defined(RTE_SPI3_SCK_TO_PSC_DELAY) && \ + defined(RTE_SPI3_BETWEEN_TRANSFER_DELAY)) + if (3U == resource->instance) + { + masterConfig.pcsToSckDelayInNanoSec = RTE_SPI3_PCS_TO_SCK_DELAY; + masterConfig.lastSckToPcsDelayInNanoSec = RTE_SPI3_SCK_TO_PSC_DELAY; + masterConfig.betweenTransferDelayInNanoSec = RTE_SPI3_BETWEEN_TRANSFER_DELAY; + } +#endif /*RTE LPSPI3 trnafer delay time configure */ + +#if (defined(RTE_SPI4_PCS_TO_SCK_DELAY) && defined(RTE_SPI4_SCK_TO_PSC_DELAY) && \ + defined(RTE_SPI4_BETWEEN_TRANSFER_DELAY)) + if (4U == resource->instance) + { + masterConfig.pcsToSckDelayInNanoSec = RTE_SPI4_PCS_TO_SCK_DELAY; + masterConfig.lastSckToPcsDelayInNanoSec = RTE_SPI4_SCK_TO_PSC_DELAY; + masterConfig.betweenTransferDelayInNanoSec = RTE_SPI4_BETWEEN_TRANSFER_DELAY; + } +#endif /*RTE LPSPI4 trnafer delay time configure */ + +#if (defined(RTE_SPI5_PCS_TO_SCK_DELAY) && defined(RTE_SPI5_SCK_TO_PSC_DELAY) && \ + defined(RTE_SPI5_BETWEEN_TRANSFER_DELAY)) + if (5U == resource->instance) + { + masterConfig.pcsToSckDelayInNanoSec = RTE_SPI5_PCS_TO_SCK_DELAY; + masterConfig.lastSckToPcsDelayInNanoSec = RTE_SPI5_SCK_TO_PSC_DELAY; + masterConfig.betweenTransferDelayInNanoSec = RTE_SPI5_BETWEEN_TRANSFER_DELAY; + } +#endif /*RTE LPSPI5 trnafer delay time configure */ + + switch (control & ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: /* Clock Polarity 0, Clock Phase 0*/ + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + } + else + { + slaveConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + slaveConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + } + break; + case ARM_SPI_CPOL0_CPHA1: /* Clock Polarity 0, Clock Phase 1*/ + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + } + else + { + slaveConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + slaveConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + } + break; + case ARM_SPI_CPOL1_CPHA0: /* Clock Polarity 1, Clock Phase 0*/ + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; + masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + } + else + { + slaveConfig.cpol = kLPSPI_ClockPolarityActiveLow; + slaveConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + } + break; + case ARM_SPI_CPOL1_CPHA1: /* Clock Polarity 1, Clock Phase 1*/ + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; + masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + } + else + { + slaveConfig.cpol = kLPSPI_ClockPolarityActiveLow; + slaveConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + } + break; + default: + break; + } + + if (control & ARM_SPI_DATA_BITS_Msk) /* Number of Data bits */ + { + if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 8)) + { + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); + } + else + { + slaveConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); + } + } + else + { + return ARM_SPI_ERROR_DATA_BITS; + } + } + + switch (control & ARM_SPI_BIT_ORDER_Msk) + { + case ARM_SPI_LSB_MSB: /* SPI Bit order from LSB to MSB */ + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.direction = kLPSPI_LsbFirst; + } + else + { + slaveConfig.direction = kLPSPI_LsbFirst; + } + break; + case ARM_SPI_MSB_LSB: /* SPI Bit order from MSB to LSB */ + if (LPSPI_IsMaster(resource->base)) + { + masterConfig.direction = kLPSPI_MsbFirst; + } + else + { + slaveConfig.direction = kLPSPI_MsbFirst; + } + break; + default: + break; + } + + if (LPSPI_IsMaster(resource->base)) + { + /* The SPI slave select is controlled by hardware, the other mode is not supported by current driver. */ + switch (control & ARM_SPI_SS_MASTER_MODE_Msk) + { + case ARM_SPI_SS_MASTER_UNUSED: + break; + case ARM_SPI_SS_MASTER_SW: + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: + break; + case ARM_SPI_SS_MASTER_HW_INPUT: + break; + default: + break; + } + } + else + { + /* The SPI slave select is controlled by hardware, the other mode is not supported by current driver. */ + switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + break; + case ARM_SPI_SS_SLAVE_SW: + break; + default: + break; + } + } + + /* LPSPI Init*/ + if (LPSPI_IsMaster(resource->base)) + { + if ((*isConfigured) & SPI_FLAG_CONFIGURED) + { + LPSPI_Deinit(resource->base); + } + LPSPI_MasterInit(resource->base, &masterConfig, resource->GetFreq()); + *isConfigured |= SPI_FLAG_CONFIGURED; + } + else + { + if ((*isConfigured) & SPI_FLAG_CONFIGURED) + { + LPSPI_Deinit(resource->base); + } + LPSPI_SlaveInit(resource->base, &slaveConfig); + *isConfigured |= SPI_FLAG_CONFIGURED; + } + + return ARM_DRIVER_OK; +} + +static void LPSPI_SetTransferConfigFlags(bool isMaster, uint32_t instance, lpspi_transfer_t *xfer) +{ + if (isMaster) + { + /* Set default config flag */ + xfer->configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; +#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) + if (0U == instance) + { + xfer->configFlags = RTE_SPI0_MASTER_PCS_PIN_SEL | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; + } +#endif /* LPSPI0 PCS pin configuration */ +#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) + if (1U == instance) + { + xfer->configFlags = RTE_SPI1_MASTER_PCS_PIN_SEL | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; + } +#endif /* LPSPI1 PCS pin configuration */ +#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) + if (2U == instance) + { + xfer->configFlags = RTE_SPI2_MASTER_PCS_PIN_SEL | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; + } +#endif /* LPSPI2 PCS pin configuration */ +#if (defined(RTE_SPI3_MASTER_PCS_PIN_SEL)) + if (3U == instance) + { + xfer->configFlags = RTE_SPI3_MASTER_PCS_PIN_SEL | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; + } +#endif /* LPSPI3 PCS pin configuration */ +#if (defined(RTE_SPI4_MASTER_PCS_PIN_SEL)) + if (4U == instance) + { + xfer->configFlags = RTE_SPI4_MASTER_PCS_PIN_SEL | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; + } +#endif /* LPSPI4 PCS pin configuration */ +#if (defined(RTE_SPI5_MASTER_PCS_PIN_SEL)) + if (5U == instance) + { + xfer->configFlags = RTE_SPI5_MASTER_PCS_PIN_SEL | kLPSPI_MasterByteSwap | kLPSPI_MasterPcsContinuous; + } +#endif /* LPSPI5 PCS pin configuration */ + } + else + { + /* Set default config flag */ + xfer->configFlags = kLPSPI_SlavePcs0 | kLPSPI_SlaveByteSwap; +#if (defined(RTE_SPI0_SLAVE_PCS_PIN_SEL)) + if (0U == instance) + { + xfer->configFlags = RTE_SPI0_SLAVE_PCS_PIN_SEL | kLPSPI_SlaveByteSwap; + } +#endif /* LPSPI0 PCS pin configuration */ +#if (defined(RTE_SPI1_SLAVE_PCS_PIN_SEL)) + if (1U == instance) + { + xfer->configFlags = RTE_SPI1_SLAVE_PCS_PIN_SEL | kLPSPI_SlaveByteSwap; + } +#endif /* LPSPI1 PCS pin configuration */ +#if (defined(RTE_SPI2_SLAVE_PCS_PIN_SEL)) + if (2U == instance) + { + xfer->configFlags = RTE_SPI2_SLAVE_PCS_PIN_SEL | kLPSPI_SlaveByteSwap; + } +#endif /* LPSPI2 PCS pin configuration */ +#if (defined(RTE_SPI3_SLAVE_PCS_PIN_SEL)) + if (3U == instance) + { + xfer->configFlags = RTE_SPI3_SLAVE_PCS_PIN_SEL | kLPSPI_SlaveByteSwap; + } +#endif /* LPSPI3 PCS pin configuration */ +#if (defined(RTE_SPI4_SLAVE_PCS_PIN_SEL)) + if (4U == instance) + { + xfer->configFlags = RTE_SPI4_SLAVE_PCS_PIN_SEL | kLPSPI_SlaveByteSwap; + } +#endif /* LPSPI4 PCS pin configuration */ +#if (defined(RTE_SPI5_SLAVE_PCS_PIN_SEL)) + if (5U == instance) + { + xfer->configFlags = RTE_SPI5_SLAVE_PCS_PIN_SEL | kLPSPI_SlaveByteSwap; + } +#endif /* LPSPI5 PCS pin configuration */ + } +} + +static ARM_DRIVER_VERSION LPSPIx_GetVersion(void) +{ + return s_lpspiDriverVersion; +} + +static ARM_SPI_CAPABILITIES LPSPIx_GetCapabilities(void) +{ + return s_lpspiDriverCapabilities; +} + +#endif + +#if (RTE_SPI0_DMA_EN || RTE_SPI1_DMA_EN || RTE_SPI2_DMA_EN || RTE_SPI3_DMA_EN || RTE_SPI4_DMA_EN || RTE_SPI5_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +void KSDK_LPSPI_MasterEdmaCallback(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + else if (kStatus_LPSPI_OutOfRange == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + else + { + __NOP(); + } + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} +void KSDK_LPSPI_SlaveEdmaCallback(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + else if (kStatus_LPSPI_OutOfRange == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + else + { + __NOP(); + } + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t LPSPI_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_lpspi_edma_driver_state_t *lpspi) +{ + if (!(lpspi->flags & SPI_FLAG_INIT)) + { + lpspi->cb_event = cb_event; + lpspi->flags = SPI_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +static int32_t LPSPI_EdmaUninitialize(cmsis_lpspi_edma_driver_state_t *lpspi) +{ + lpspi->flags = SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t LPSPI_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpspi_edma_driver_state_t *lpspi) +{ + cmsis_lpspi_edma_resource_t *dmaResource = lpspi->dmaResource; + + switch (state) + { + case ARM_POWER_OFF: + if (lpspi->flags & SPI_FLAG_POWER) + { + LPSPI_Deinit(lpspi->resource->base); +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_DisableChannel(lpspi->dmaResource->rxDmamuxBase, lpspi->dmaResource->rxEdmaChannel); + DMAMUX_DisableChannel(lpspi->dmaResource->txDmamuxBase, lpspi->dmaResource->txEdmaChannel); +#endif + lpspi->flags = SPI_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + { + if (lpspi->flags == SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpspi->flags & SPI_FLAG_POWER) + { + /* Driver already powered */ + break; + } + /* Enable Clock gate */ + CLOCK_EnableClock(s_lpspiClock[lpspi->resource->instance]); + + memset(lpspi->edmaRxRegToRxDataHandle, 0, sizeof(edma_handle_t)); + memset(lpspi->edmaTxDataToTxRegHandle, 0, sizeof(edma_handle_t)); + + EDMA_CreateHandle(lpspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel); + EDMA_CreateHandle(lpspi->edmaTxDataToTxRegHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel); + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest); + DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel); + + DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, dmaResource->txDmaRequest); + DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel); +#endif + lpspi->flags |= SPI_FLAG_POWER; + break; + } + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPSPI_EdmaSend(const void *data, uint32_t num, cmsis_lpspi_edma_driver_state_t *lpspi) +{ + int32_t ret; + status_t status; + lpspi_transfer_t xfer = {0}; + + xfer.rxData = NULL; + xfer.txData = (uint8_t *)data; + xfer.dataSize = num; + + LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer); + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + status = LPSPI_MasterTransferEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer); + } + else + { + status = LPSPI_SlaveTransferEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPSPI_EdmaReceive(void *data, uint32_t num, cmsis_lpspi_edma_driver_state_t *lpspi) +{ + int32_t ret; + status_t status; + lpspi_transfer_t xfer = {0}; + + xfer.txData = NULL; + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num; + + LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer); + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + status = LPSPI_MasterTransferEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer); + } + else + { + status = LPSPI_SlaveTransferEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPSPI_EdmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_lpspi_edma_driver_state_t *lpspi) +{ + int32_t ret; + status_t status; + lpspi_transfer_t xfer = {0}; + + xfer.txData = (uint8_t *)data_out; + xfer.rxData = (uint8_t *)data_in; + xfer.dataSize = num; + + LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer); + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + status = LPSPI_MasterTransferEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer); + } + else + { + status = LPSPI_SlaveTransferEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t LPSPI_EdmaGetCount(cmsis_lpspi_edma_driver_state_t *lpspi) +{ + uint32_t cnt; + size_t bytes; + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + bytes = (uint32_t)lpspi->handle->masterHandle.nbytes * + EDMA_GetRemainingMajorLoopCount(lpspi->dmaResource->rxEdmaBase, lpspi->dmaResource->rxEdmaChannel); + cnt = lpspi->handle->masterHandle.totalByteCount - bytes; + } + else + { + bytes = (uint32_t)lpspi->handle->masterHandle.nbytes * + EDMA_GetRemainingMajorLoopCount(lpspi->dmaResource->rxEdmaBase, lpspi->dmaResource->rxEdmaChannel); + cnt = lpspi->handle->slaveHandle.totalByteCount - bytes; + } + return cnt; +} + +static int32_t LPSPI_EdmaControl(uint32_t control, uint32_t arg, cmsis_lpspi_edma_driver_state_t *lpspi) +{ + if (!(lpspi->flags & SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: + LPSPI_Enable(lpspi->resource->base, false); + return ARM_DRIVER_OK; + case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Master); + LPSPI_MasterTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), + KSDK_LPSPI_MasterEdmaCallback, (void *)lpspi->cb_event, + lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle); + + lpspi->baudRate_Bps = arg; + break; + } + case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Slave); + LPSPI_SlaveTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), + KSDK_LPSPI_SlaveEdmaCallback, (void *)lpspi->cb_event, + lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle); + break; + } + case ARM_SPI_SET_BUS_SPEED: /* Get Bus Speed in bps */ + { + uint32_t tcrPrescaleValue = 0; + LPSPI_Enable(lpspi->resource->base, false); + + if (!LPSPI_IsMaster(lpspi->resource->base)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + if (0 == LPSPI_MasterSetBaudRate(lpspi->resource->base, arg, lpspi->resource->GetFreq(), &tcrPrescaleValue)) + { + return ARM_DRIVER_ERROR; + } + + LPSPI_Enable(lpspi->resource->base, true); + lpspi->baudRate_Bps = arg; + return ARM_DRIVER_OK; + } + + case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ + if (!LPSPI_IsMaster(lpspi->resource->base)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return lpspi->baudRate_Bps; + case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ + if (LPSPI_IsMaster(lpspi->resource->base)) + { + LPSPI_MasterTransferAbortEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle)); + } + else + { + LPSPI_SlaveTransferAbortEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle)); + } + return ARM_DRIVER_OK; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + LPSPI_SetDummyData(lpspi->resource->base, (uint8_t)arg); + return ARM_DRIVER_OK; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on SOUT); arg = Bus Speed in bps */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Master); + LPSPI_MasterTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), + KSDK_LPSPI_MasterEdmaCallback, (void *)lpspi->cb_event, + lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle); + + lpspi->baudRate_Bps = arg; + break; + } + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on SIN) */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Slave); + LPSPI_SlaveTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), + KSDK_LPSPI_SlaveEdmaCallback, (void *)lpspi->cb_event, + lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle); + break; + } + + default: + break; + } + + return LPSPI_CommonControl(control, arg, lpspi->resource, &lpspi->flags); +} + +ARM_SPI_STATUS LPSPI_EdmaGetStatus(cmsis_lpspi_edma_driver_state_t *lpspi) +{ + ARM_SPI_STATUS stat; + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + stat.busy = (kLPSPI_Busy == lpspi->handle->masterHandle.state) ? (1U) : (0U); + stat.data_lost = (kLPSPI_Error == lpspi->handle->masterHandle.state) ? (1U) : (0U); + } + else + { + stat.busy = (kLPSPI_Busy == lpspi->handle->slaveHandle.state) ? (1U) : (0U); + stat.data_lost = (kLPSPI_Error == lpspi->handle->slaveHandle.state) ? (1U) : (0U); + } + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} +#endif /* defined(FSL_FEATURE_SOC_EDMA_COUNT) */ + +#endif + +#if ((RTE_SPI0 && !RTE_SPI0_DMA_EN) || (RTE_SPI1 && !RTE_SPI1_DMA_EN) || (RTE_SPI2 && !RTE_SPI2_DMA_EN) || \ + (RTE_SPI3 && !RTE_SPI3_DMA_EN) || (RTE_SPI4 && !RTE_SPI4_DMA_EN) || (RTE_SPI5 && !RTE_SPI5_DMA_EN)) + +void KSDK_LPSPI_MasterInterruptCallback(LPSPI_Type *base, + lpspi_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + else if (kStatus_LPSPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + else + { + __NOP(); + } + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +void KSDK_LPSPI_SlaveInterruptCallback(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + if (kStatus_LPSPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + else + { + __NOP(); + } + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t LPSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + if (!(lpspi->flags & SPI_FLAG_INIT)) + { + lpspi->cb_event = cb_event; + lpspi->flags = SPI_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPSPI_InterruptUninitialize(cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + lpspi->flags = SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t LPSPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + switch (state) + { + case ARM_POWER_OFF: + if (lpspi->flags & SPI_FLAG_POWER) + { + LPSPI_Deinit(lpspi->resource->base); + lpspi->flags = SPI_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + if (lpspi->flags == SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpspi->flags & SPI_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + CLOCK_EnableClock(s_lpspiClock[lpspi->resource->instance]); + lpspi->flags |= SPI_FLAG_POWER; + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPSPI_InterruptSend(const void *data, uint32_t num, cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + int32_t ret; + status_t status; + lpspi_transfer_t xfer = {0}; + + xfer.rxData = NULL; + xfer.txData = (uint8_t *)data; + xfer.dataSize = num; + + LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer); + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + status = LPSPI_MasterTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer); + } + else + { + status = LPSPI_SlaveTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPSPI_InterruptReceive(void *data, uint32_t num, cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + int32_t ret; + status_t status; + lpspi_transfer_t xfer = {0}; + + xfer.txData = NULL; + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num; + + LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer); + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + status = LPSPI_MasterTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer); + } + else + { + status = LPSPI_SlaveTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPSPI_InterruptTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + int32_t ret; + status_t status; + lpspi_transfer_t xfer = {0}; + + xfer.txData = (uint8_t *)data_out; + xfer.rxData = (uint8_t *)data_in; + xfer.dataSize = num; + + LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer); + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + status = LPSPI_MasterTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer); + } + else + { + status = LPSPI_SlaveTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPSPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t LPSPI_InterruptGetCount(cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + if (LPSPI_IsMaster(lpspi->resource->base)) + { + return lpspi->handle->masterHandle.totalByteCount - lpspi->handle->masterHandle.rxRemainingByteCount; + } + else + { + return lpspi->handle->slaveHandle.totalByteCount - lpspi->handle->slaveHandle.rxRemainingByteCount; + } +} + +static int32_t LPSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + if (!(lpspi->flags & SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: + LPSPI_Enable(lpspi->resource->base, false); + return ARM_DRIVER_OK; + case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Master); + LPSPI_MasterTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->masterHandle), + KSDK_LPSPI_MasterInterruptCallback, (void *)lpspi->cb_event); + lpspi->baudRate_Bps = arg; + break; + } + case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Slave); + LPSPI_SlaveTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->slaveHandle), + KSDK_LPSPI_SlaveInterruptCallback, (void *)lpspi->cb_event); + break; + } + case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ + { + uint32_t tcrPrescaleValue = 0; + LPSPI_Enable(lpspi->resource->base, false); + + if (!LPSPI_IsMaster(lpspi->resource->base)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + if (0 == LPSPI_MasterSetBaudRate(lpspi->resource->base, arg, lpspi->resource->GetFreq(), &tcrPrescaleValue)) + { + return ARM_DRIVER_ERROR; + } + + LPSPI_Enable(lpspi->resource->base, true); + lpspi->baudRate_Bps = arg; + return ARM_DRIVER_OK; + } + case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ + if (!LPSPI_IsMaster(lpspi->resource->base)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return (lpspi->baudRate_Bps); + case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + LPSPI_MasterTransferAbort(lpspi->resource->base, &(lpspi->handle->masterHandle)); + } + else + { + LPSPI_SlaveTransferAbort(lpspi->resource->base, &(lpspi->handle->slaveHandle)); + } + return ARM_DRIVER_OK; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + if (LPSPI_IsMaster(lpspi->resource->base)) + { + LPSPI_SetDummyData(lpspi->resource->base, (uint8_t)arg); + return ARM_DRIVER_OK; + } + else + { + /* Mode is not supported by current driver. + * In slave mode, if the tx buffer is NULL, the output pin will keep tristated. + */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on SOUT); arg = Bus Speed in bps */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Master); + LPSPI_MasterTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->masterHandle), + KSDK_LPSPI_MasterInterruptCallback, (void *)lpspi->cb_event); + lpspi->baudRate_Bps = arg; + break; + } + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on SIN) */ + { + LPSPI_SetMasterSlaveMode(lpspi->resource->base, kLPSPI_Slave); + LPSPI_SlaveTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->slaveHandle), + KSDK_LPSPI_SlaveInterruptCallback, (void *)lpspi->cb_event); + break; + } + + default: + break; + } + return LPSPI_CommonControl(control, lpspi->baudRate_Bps, lpspi->resource, &lpspi->flags); +} + +ARM_SPI_STATUS LPSPI_InterruptGetStatus(cmsis_lpspi_interrupt_driver_state_t *lpspi) +{ + ARM_SPI_STATUS stat; + + if (LPSPI_IsMaster(lpspi->resource->base)) + { + stat.busy = ((lpspi->handle->masterHandle.rxRemainingByteCount > 0) || + (lpspi->handle->masterHandle.txRemainingByteCount > 0)) ? + (1U) : + (0U); + stat.data_lost = (kLPSPI_Error == lpspi->handle->masterHandle.state) ? (1U) : (0U); + } + else + { + stat.busy = ((lpspi->handle->slaveHandle.rxRemainingByteCount > 0) || + (lpspi->handle->slaveHandle.txRemainingByteCount > 0)) ? + (1U) : + (0U); + stat.data_lost = (kLPSPI_Error == lpspi->handle->slaveHandle.state) ? (1U) : (0U); + } + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(LPSPI0) && RTE_SPI0 + +/* User needs to provide the implementation for LPSPI0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPSPI0_GetFreq(void); +extern void LPSPI0_InitPins(void); +extern void LPSPI0_DeinitPins(void); + +cmsis_lpspi_resource_t LPSPI0_Resource = {LPSPI0, 0, LPSPI0_GetFreq}; + +#if RTE_SPI0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpspi_edma_resource_t LPSPI0_EdmaResource = { + RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_TX_PERI_SEL, + RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH, RTE_SPI0_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_SPI0_DMA_TX_DMAMUX_BASE, RTE_SPI0_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI0_EdmaHandle); +edma_handle_t LPSPI0_EdmaTxDataToTxRegHandle; +edma_handle_t LPSPI0_EdmaRxRegToRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi0_edma_driver_state") +cmsis_lpspi_edma_driver_state_t LPSPI0_EdmaDriverState = { +#else +cmsis_lpspi_edma_driver_state_t LPSPI0_EdmaDriverState = { +#endif + &LPSPI0_Resource, + &LPSPI0_EdmaResource, + &LPSPI0_EdmaHandle, + &LPSPI0_EdmaRxRegToRxDataHandle, + &LPSPI0_EdmaTxDataToTxRegHandle, +}; + +static int32_t LPSPI0_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI0_InitPins(); + return LPSPI_EdmaInitialize(cb_event, &LPSPI0_EdmaDriverState); +} + +static int32_t LPSPI0_EdmaUninitialize(void) +{ + LPSPI0_DeinitPins(); + return LPSPI_EdmaUninitialize(&LPSPI0_EdmaDriverState); +} + +static int32_t LPSPI0_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_EdmaPowerControl(state, &LPSPI0_EdmaDriverState); +} + +static int32_t LPSPI0_EdmaSend(const void *data, uint32_t num) +{ + return LPSPI_EdmaSend(data, num, &LPSPI0_EdmaDriverState); +} + +static int32_t LPSPI0_EdmaReceive(void *data, uint32_t num) +{ + return LPSPI_EdmaReceive(data, num, &LPSPI0_EdmaDriverState); +} + +static int32_t LPSPI0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI0_EdmaDriverState); +} + +static uint32_t LPSPI0_EdmaGetCount(void) +{ + return LPSPI_EdmaGetCount(&LPSPI0_EdmaDriverState); +} + +static int32_t LPSPI0_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPSPI_EdmaControl(control, arg, &LPSPI0_EdmaDriverState); +} + +static ARM_SPI_STATUS LPSPI0_EdmaGetStatus(void) +{ + return LPSPI_EdmaGetStatus(&LPSPI0_EdmaDriverState); +} + +#endif + +#else + +cmsis_lpspi_handle_t LPSPI0_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi0_interrupt_driver_state") +cmsis_lpspi_interrupt_driver_state_t LPSPI0_InterruptDriverState = { +#else +cmsis_lpspi_interrupt_driver_state_t LPSPI0_InterruptDriverState = { +#endif + &LPSPI0_Resource, &LPSPI0_Handle, +}; + +static int32_t LPSPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI0_InitPins(); + return LPSPI_InterruptInitialize(cb_event, &LPSPI0_InterruptDriverState); +} + +static int32_t LPSPI0_InterruptUninitialize(void) +{ + LPSPI0_DeinitPins(); + return LPSPI_InterruptUninitialize(&LPSPI0_InterruptDriverState); +} + +static int32_t LPSPI0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_InterruptPowerControl(state, &LPSPI0_InterruptDriverState); +} + +static int32_t LPSPI0_InterruptSend(const void *data, uint32_t num) +{ + return LPSPI_InterruptSend(data, num, &LPSPI0_InterruptDriverState); +} + +static int32_t LPSPI0_InterruptReceive(void *data, uint32_t num) +{ + return LPSPI_InterruptReceive(data, num, &LPSPI0_InterruptDriverState); +} + +static int32_t LPSPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI0_InterruptDriverState); +} + +static uint32_t LPSPI0_InterruptGetCount(void) +{ + return LPSPI_InterruptGetCount(&LPSPI0_InterruptDriverState); +} + +static int32_t LPSPI0_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPSPI_InterruptControl(control, arg, &LPSPI0_InterruptDriverState); +} + +static ARM_SPI_STATUS LPSPI0_InterruptGetStatus(void) +{ + return LPSPI_InterruptGetStatus(&LPSPI0_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI0 = { + LPSPIx_GetVersion, LPSPIx_GetCapabilities, +#if RTE_SPI0_DMA_EN + LPSPI0_EdmaInitialize, LPSPI0_EdmaUninitialize, LPSPI0_EdmaPowerControl, LPSPI0_EdmaSend, LPSPI0_EdmaReceive, + LPSPI0_EdmaTransfer, LPSPI0_EdmaGetCount, LPSPI0_EdmaControl, LPSPI0_EdmaGetStatus +#else + LPSPI0_InterruptInitialize, LPSPI0_InterruptUninitialize, LPSPI0_InterruptPowerControl, LPSPI0_InterruptSend, + LPSPI0_InterruptReceive, LPSPI0_InterruptTransfer, LPSPI0_InterruptGetCount, LPSPI0_InterruptControl, + LPSPI0_InterruptGetStatus +#endif +}; + +#endif /* LPSPI0 */ + +#if defined(LPSPI1) && RTE_SPI1 + +/* User needs to provide the implementation for LPSPI1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPSPI1_GetFreq(void); +extern void LPSPI1_InitPins(void); +extern void LPSPI1_DeinitPins(void); + +cmsis_lpspi_resource_t LPSPI1_Resource = {LPSPI1, 1, LPSPI1_GetFreq}; + +#if RTE_SPI1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpspi_edma_resource_t LPSPI1_EdmaResource = { + RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_PERI_SEL, + RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_SPI1_DMA_TX_DMAMUX_BASE, RTE_SPI1_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI1_EdmaHandle); +edma_handle_t LPSPI1_EdmaTxDataToTxRegHandle; +edma_handle_t LPSPI1_EdmaRxRegToRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi1_edma_driver_state") +cmsis_lpspi_edma_driver_state_t LPSPI1_EdmaDriverState = { +#else +cmsis_lpspi_edma_driver_state_t LPSPI1_EdmaDriverState = { +#endif + &LPSPI1_Resource, + &LPSPI1_EdmaResource, + &LPSPI1_EdmaHandle, + &LPSPI1_EdmaRxRegToRxDataHandle, + &LPSPI1_EdmaTxDataToTxRegHandle, +}; + +static int32_t LPSPI1_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI1_InitPins(); + return LPSPI_EdmaInitialize(cb_event, &LPSPI1_EdmaDriverState); +} + +static int32_t LPSPI1_EdmaUninitialize(void) +{ + LPSPI1_DeinitPins(); + return LPSPI_EdmaUninitialize(&LPSPI1_EdmaDriverState); +} + +static int32_t LPSPI1_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_EdmaPowerControl(state, &LPSPI1_EdmaDriverState); +} + +static int32_t LPSPI1_EdmaSend(const void *data, uint32_t num) +{ + return LPSPI_EdmaSend(data, num, &LPSPI1_EdmaDriverState); +} + +static int32_t LPSPI1_EdmaReceive(void *data, uint32_t num) +{ + return LPSPI_EdmaReceive(data, num, &LPSPI1_EdmaDriverState); +} + +static int32_t LPSPI1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI1_EdmaDriverState); +} + +static uint32_t LPSPI1_EdmaGetCount(void) +{ + return LPSPI_EdmaGetCount(&LPSPI1_EdmaDriverState); +} + +static int32_t LPSPI1_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPSPI_EdmaControl(control, arg, &LPSPI1_EdmaDriverState); +} + +static ARM_SPI_STATUS LPSPI1_EdmaGetStatus(void) +{ + return LPSPI_EdmaGetStatus(&LPSPI1_EdmaDriverState); +} + +#endif + +#else + +cmsis_lpspi_handle_t LPSPI1_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi1_interrupt_driver_state") +cmsis_lpspi_interrupt_driver_state_t LPSPI1_InterruptDriverState = { +#else +cmsis_lpspi_interrupt_driver_state_t LPSPI1_InterruptDriverState = { +#endif + &LPSPI1_Resource, &LPSPI1_Handle, +}; + +static int32_t LPSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI1_InitPins(); + return LPSPI_InterruptInitialize(cb_event, &LPSPI1_InterruptDriverState); +} + +static int32_t LPSPI1_InterruptUninitialize(void) +{ + LPSPI1_DeinitPins(); + return LPSPI_InterruptUninitialize(&LPSPI1_InterruptDriverState); +} + +static int32_t LPSPI1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_InterruptPowerControl(state, &LPSPI1_InterruptDriverState); +} + +static int32_t LPSPI1_InterruptSend(const void *data, uint32_t num) +{ + return LPSPI_InterruptSend(data, num, &LPSPI1_InterruptDriverState); +} + +static int32_t LPSPI1_InterruptReceive(void *data, uint32_t num) +{ + return LPSPI_InterruptReceive(data, num, &LPSPI1_InterruptDriverState); +} + +static int32_t LPSPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI1_InterruptDriverState); +} + +static uint32_t LPSPI1_InterruptGetCount(void) +{ + return LPSPI_InterruptGetCount(&LPSPI1_InterruptDriverState); +} + +static int32_t LPSPI1_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPSPI_InterruptControl(control, arg, &LPSPI1_InterruptDriverState); +} + +static ARM_SPI_STATUS LPSPI1_InterruptGetStatus(void) +{ + return LPSPI_InterruptGetStatus(&LPSPI1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI1 = { + LPSPIx_GetVersion, LPSPIx_GetCapabilities, +#if RTE_SPI1_DMA_EN + LPSPI1_EdmaInitialize, LPSPI1_EdmaUninitialize, LPSPI1_EdmaPowerControl, LPSPI1_EdmaSend, LPSPI1_EdmaReceive, + LPSPI1_EdmaTransfer, LPSPI1_EdmaGetCount, LPSPI1_EdmaControl, LPSPI1_EdmaGetStatus +#else + LPSPI1_InterruptInitialize, LPSPI1_InterruptUninitialize, LPSPI1_InterruptPowerControl, LPSPI1_InterruptSend, + LPSPI1_InterruptReceive, LPSPI1_InterruptTransfer, LPSPI1_InterruptGetCount, LPSPI1_InterruptControl, + LPSPI1_InterruptGetStatus +#endif +}; + +#endif /* LPSPI1 */ + +#if defined(LPSPI2) && RTE_SPI2 + +/* User needs to provide the implementation for LPSPI2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPSPI2_GetFreq(void); +extern void LPSPI2_InitPins(void); +extern void LPSPI2_DeinitPins(void); + +cmsis_lpspi_resource_t LPSPI2_Resource = {LPSPI2, 2, LPSPI2_GetFreq}; + +#if RTE_SPI2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpspi_edma_resource_t LPSPI2_EdmaResource = { + RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_TX_PERI_SEL, + RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, RTE_SPI2_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_SPI2_DMA_TX_DMAMUX_BASE, RTE_SPI2_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI2_EdmaHandle); +edma_handle_t LPSPI2_EdmaTxDataToTxRegHandle; +edma_handle_t LPSPI2_EdmaRxRegToRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi2_edma_driver_state") +cmsis_lpspi_edma_driver_state_t LPSPI2_EdmaDriverState = { +#else +cmsis_lpspi_edma_driver_state_t LPSPI2_EdmaDriverState = { +#endif + &LPSPI2_Resource, + &LPSPI2_EdmaResource, + &LPSPI2_EdmaHandle, + &LPSPI2_EdmaRxRegToRxDataHandle, + &LPSPI2_EdmaTxDataToTxRegHandle, +}; + +static int32_t LPSPI2_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI2_InitPins(); + return LPSPI_EdmaInitialize(cb_event, &LPSPI2_EdmaDriverState); +} + +static int32_t LPSPI2_EdmaUninitialize(void) +{ + LPSPI2_DeinitPins(); + return LPSPI_EdmaUninitialize(&LPSPI2_EdmaDriverState); +} + +static int32_t LPSPI2_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_EdmaPowerControl(state, &LPSPI2_EdmaDriverState); +} + +static int32_t LPSPI2_EdmaSend(const void *data, uint32_t num) +{ + return LPSPI_EdmaSend(data, num, &LPSPI2_EdmaDriverState); +} + +static int32_t LPSPI2_EdmaReceive(void *data, uint32_t num) +{ + return LPSPI_EdmaReceive(data, num, &LPSPI2_EdmaDriverState); +} + +static int32_t LPSPI2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI2_EdmaDriverState); +} + +static uint32_t LPSPI2_EdmaGetCount(void) +{ + return LPSPI_EdmaGetCount(&LPSPI2_EdmaDriverState); +} + +static int32_t LPSPI2_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPSPI_EdmaControl(control, arg, &LPSPI2_EdmaDriverState); +} + +static ARM_SPI_STATUS LPSPI2_EdmaGetStatus(void) +{ + return LPSPI_EdmaGetStatus(&LPSPI2_EdmaDriverState); +} + +#endif + +#else + +cmsis_lpspi_handle_t LPSPI2_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi2_interrupt_driver_state") +cmsis_lpspi_interrupt_driver_state_t LPSPI2_InterruptDriverState = { +#else +cmsis_lpspi_interrupt_driver_state_t LPSPI2_InterruptDriverState = { +#endif + &LPSPI2_Resource, &LPSPI2_Handle, +}; + +static int32_t LPSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI2_InitPins(); + return LPSPI_InterruptInitialize(cb_event, &LPSPI2_InterruptDriverState); +} + +static int32_t LPSPI2_InterruptUninitialize(void) +{ + LPSPI2_DeinitPins(); + return LPSPI_InterruptUninitialize(&LPSPI2_InterruptDriverState); +} + +static int32_t LPSPI2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_InterruptPowerControl(state, &LPSPI2_InterruptDriverState); +} + +static int32_t LPSPI2_InterruptSend(const void *data, uint32_t num) +{ + return LPSPI_InterruptSend(data, num, &LPSPI2_InterruptDriverState); +} + +static int32_t LPSPI2_InterruptReceive(void *data, uint32_t num) +{ + return LPSPI_InterruptReceive(data, num, &LPSPI2_InterruptDriverState); +} + +static int32_t LPSPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI2_InterruptDriverState); +} + +static uint32_t LPSPI2_InterruptGetCount(void) +{ + return LPSPI_InterruptGetCount(&LPSPI2_InterruptDriverState); +} + +static int32_t LPSPI2_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPSPI_InterruptControl(control, arg, &LPSPI2_InterruptDriverState); +} + +static ARM_SPI_STATUS LPSPI2_InterruptGetStatus(void) +{ + return LPSPI_InterruptGetStatus(&LPSPI2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI2 = { + LPSPIx_GetVersion, LPSPIx_GetCapabilities, +#if RTE_SPI2_DMA_EN + LPSPI2_EdmaInitialize, LPSPI2_EdmaUninitialize, LPSPI2_EdmaPowerControl, LPSPI2_EdmaSend, LPSPI2_EdmaReceive, + LPSPI2_EdmaTransfer, LPSPI2_EdmaGetCount, LPSPI2_EdmaControl, LPSPI2_EdmaGetStatus +#else + LPSPI2_InterruptInitialize, LPSPI2_InterruptUninitialize, LPSPI2_InterruptPowerControl, LPSPI2_InterruptSend, + LPSPI2_InterruptReceive, LPSPI2_InterruptTransfer, LPSPI2_InterruptGetCount, LPSPI2_InterruptControl, + LPSPI2_InterruptGetStatus +#endif +}; + +#endif /* LPSPI2 */ + +#if defined(LPSPI3) && RTE_SPI3 + +/* User needs to provide the implementation for LPSPI3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPSPI3_GetFreq(void); +extern void LPSPI3_InitPins(void); +extern void LPSPI3_DeinitPins(void); + +cmsis_lpspi_resource_t LPSPI3_Resource = {LPSPI3, 3, LPSPI3_GetFreq}; + +#if RTE_SPI3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpspi_edma_resource_t LPSPI3_EdmaResource = { + RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_TX_PERI_SEL, + RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH, RTE_SPI3_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_SPI3_DMA_TX_DMAMUX_BASE, RTE_SPI3_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI3_EdmaHandle); +edma_handle_t LPSPI3_EdmaTxDataToTxRegHandle; +edma_handle_t LPSPI3_EdmaRxRegToRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi3_edma_driver_state") +cmsis_lpspi_edma_driver_state_t LPSPI3_EdmaDriverState = { +#else +cmsis_lpspi_edma_driver_state_t LPSPI3_EdmaDriverState = { +#endif + &LPSPI3_Resource, + &LPSPI3_EdmaResource, + &LPSPI3_EdmaHandle, + &LPSPI3_EdmaRxRegToRxDataHandle, + &LPSPI3_EdmaTxDataToTxRegHandle, +}; + +static int32_t LPSPI3_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI3_InitPins(); + return LPSPI_EdmaInitialize(cb_event, &LPSPI3_EdmaDriverState); +} + +static int32_t LPSPI3_EdmaUninitialize(void) +{ + LPSPI3_DeinitPins(); + return LPSPI_EdmaUninitialize(&LPSPI3_EdmaDriverState); +} + +static int32_t LPSPI3_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_EdmaPowerControl(state, &LPSPI3_EdmaDriverState); +} + +static int32_t LPSPI3_EdmaSend(const void *data, uint32_t num) +{ + return LPSPI_EdmaSend(data, num, &LPSPI3_EdmaDriverState); +} + +static int32_t LPSPI3_EdmaReceive(void *data, uint32_t num) +{ + return LPSPI_EdmaReceive(data, num, &LPSPI3_EdmaDriverState); +} + +static int32_t LPSPI3_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI3_EdmaDriverState); +} + +static uint32_t LPSPI3_EdmaGetCount(void) +{ + return LPSPI_EdmaGetCount(&LPSPI3_EdmaDriverState); +} + +static int32_t LPSPI3_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPSPI_EdmaControl(control, arg, &LPSPI3_EdmaDriverState); +} + +static ARM_SPI_STATUS LPSPI3_EdmaGetStatus(void) +{ + return LPSPI_EdmaGetStatus(&LPSPI3_EdmaDriverState); +} + +#endif + +#else + +cmsis_lpspi_handle_t LPSPI3_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi3_interrupt_driver_state") +cmsis_lpspi_interrupt_driver_state_t LPSPI3_InterruptDriverState = { +#else +cmsis_lpspi_interrupt_driver_state_t LPSPI3_InterruptDriverState = { +#endif + &LPSPI3_Resource, &LPSPI3_Handle, +}; + +static int32_t LPSPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI3_InitPins(); + return LPSPI_InterruptInitialize(cb_event, &LPSPI3_InterruptDriverState); +} + +static int32_t LPSPI3_InterruptUninitialize(void) +{ + LPSPI3_DeinitPins(); + return LPSPI_InterruptUninitialize(&LPSPI3_InterruptDriverState); +} + +static int32_t LPSPI3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_InterruptPowerControl(state, &LPSPI3_InterruptDriverState); +} + +static int32_t LPSPI3_InterruptSend(const void *data, uint32_t num) +{ + return LPSPI_InterruptSend(data, num, &LPSPI3_InterruptDriverState); +} + +static int32_t LPSPI3_InterruptReceive(void *data, uint32_t num) +{ + return LPSPI_InterruptReceive(data, num, &LPSPI3_InterruptDriverState); +} + +static int32_t LPSPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI3_InterruptDriverState); +} + +static uint32_t LPSPI3_InterruptGetCount(void) +{ + return LPSPI_InterruptGetCount(&LPSPI3_InterruptDriverState); +} + +static int32_t LPSPI3_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPSPI_InterruptControl(control, arg, &LPSPI3_InterruptDriverState); +} + +static ARM_SPI_STATUS LPSPI3_InterruptGetStatus(void) +{ + return LPSPI_InterruptGetStatus(&LPSPI3_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI3 = { + LPSPIx_GetVersion, LPSPIx_GetCapabilities, +#if RTE_SPI3_DMA_EN + LPSPI3_EdmaInitialize, LPSPI3_EdmaUninitialize, LPSPI3_EdmaPowerControl, LPSPI3_EdmaSend, LPSPI3_EdmaReceive, + LPSPI3_EdmaTransfer, LPSPI3_EdmaGetCount, LPSPI3_EdmaControl, LPSPI3_EdmaGetStatus +#else + LPSPI3_InterruptInitialize, LPSPI3_InterruptUninitialize, LPSPI3_InterruptPowerControl, LPSPI3_InterruptSend, + LPSPI3_InterruptReceive, LPSPI3_InterruptTransfer, LPSPI3_InterruptGetCount, LPSPI3_InterruptControl, + LPSPI3_InterruptGetStatus +#endif +}; + +#endif /* LPSPI3 */ + +#if defined(LPSPI4) && RTE_SPI4 + +/* User needs to provide the implementation for LPSPI4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPSPI4_GetFreq(void); +extern void LPSPI4_InitPins(void); +extern void LPSPI4_DeinitPins(void); + +cmsis_lpspi_resource_t LPSPI4_Resource = {LPSPI4, 4, LPSPI4_GetFreq}; + +#if RTE_SPI4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpspi_edma_resource_t LPSPI4_EdmaResource = { + RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, RTE_SPI4_DMA_TX_PERI_SEL, + RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH, RTE_SPI4_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_SPI4_DMA_TX_DMAMUX_BASE, RTE_SPI4_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI4_EdmaHandle); +edma_handle_t LPSPI4_EdmaTxDataToTxRegHandle; +edma_handle_t LPSPI4_EdmaRxRegToRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi4_edma_driver_state") +cmsis_lpspi_edma_driver_state_t LPSPI4_EdmaDriverState = { +#else +cmsis_lpspi_edma_driver_state_t LPSPI4_EdmaDriverState = { +#endif + &LPSPI4_Resource, + &LPSPI4_EdmaResource, + &LPSPI4_EdmaHandle, + &LPSPI4_EdmaRxRegToRxDataHandle, + &LPSPI4_EdmaTxDataToTxRegHandle, +}; + +static int32_t LPSPI4_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI4_InitPins(); + return LPSPI_EdmaInitialize(cb_event, &LPSPI4_EdmaDriverState); +} + +static int32_t LPSPI4_EdmaUninitialize(void) +{ + LPSPI4_DeinitPins(); + return LPSPI_EdmaUninitialize(&LPSPI4_EdmaDriverState); +} + +static int32_t LPSPI4_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_EdmaPowerControl(state, &LPSPI4_EdmaDriverState); +} + +static int32_t LPSPI4_EdmaSend(const void *data, uint32_t num) +{ + return LPSPI_EdmaSend(data, num, &LPSPI4_EdmaDriverState); +} + +static int32_t LPSPI4_EdmaReceive(void *data, uint32_t num) +{ + return LPSPI_EdmaReceive(data, num, &LPSPI4_EdmaDriverState); +} + +static int32_t LPSPI4_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI4_EdmaDriverState); +} + +static uint32_t LPSPI4_EdmaGetCount(void) +{ + return LPSPI_EdmaGetCount(&LPSPI4_EdmaDriverState); +} + +static int32_t LPSPI4_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPSPI_EdmaControl(control, arg, &LPSPI4_EdmaDriverState); +} + +static ARM_SPI_STATUS LPSPI4_EdmaGetStatus(void) +{ + return LPSPI_EdmaGetStatus(&LPSPI4_EdmaDriverState); +} + +#endif + +#else + +cmsis_lpspi_handle_t LPSPI4_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi4_interrupt_driver_state") +cmsis_lpspi_interrupt_driver_state_t LPSPI4_InterruptDriverState = { +#else +cmsis_lpspi_interrupt_driver_state_t LPSPI4_InterruptDriverState = { +#endif + &LPSPI4_Resource, &LPSPI4_Handle, +}; + +static int32_t LPSPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI4_InitPins(); + return LPSPI_InterruptInitialize(cb_event, &LPSPI4_InterruptDriverState); +} + +static int32_t LPSPI4_InterruptUninitialize(void) +{ + LPSPI4_DeinitPins(); + return LPSPI_InterruptUninitialize(&LPSPI4_InterruptDriverState); +} + +static int32_t LPSPI4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_InterruptPowerControl(state, &LPSPI4_InterruptDriverState); +} + +static int32_t LPSPI4_InterruptSend(const void *data, uint32_t num) +{ + return LPSPI_InterruptSend(data, num, &LPSPI4_InterruptDriverState); +} + +static int32_t LPSPI4_InterruptReceive(void *data, uint32_t num) +{ + return LPSPI_InterruptReceive(data, num, &LPSPI4_InterruptDriverState); +} + +static int32_t LPSPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI4_InterruptDriverState); +} + +static uint32_t LPSPI4_InterruptGetCount(void) +{ + return LPSPI_InterruptGetCount(&LPSPI4_InterruptDriverState); +} + +static int32_t LPSPI4_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPSPI_InterruptControl(control, arg, &LPSPI4_InterruptDriverState); +} + +static ARM_SPI_STATUS LPSPI4_InterruptGetStatus(void) +{ + return LPSPI_InterruptGetStatus(&LPSPI4_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI4 = { + LPSPIx_GetVersion, LPSPIx_GetCapabilities, +#if RTE_SPI4_DMA_EN + LPSPI4_EdmaInitialize, LPSPI4_EdmaUninitialize, LPSPI4_EdmaPowerControl, LPSPI4_EdmaSend, LPSPI4_EdmaReceive, + LPSPI4_EdmaTransfer, LPSPI4_EdmaGetCount, LPSPI4_EdmaControl, LPSPI4_EdmaGetStatus +#else + LPSPI4_InterruptInitialize, LPSPI4_InterruptUninitialize, LPSPI4_InterruptPowerControl, LPSPI4_InterruptSend, + LPSPI4_InterruptReceive, LPSPI4_InterruptTransfer, LPSPI4_InterruptGetCount, LPSPI4_InterruptControl, + LPSPI4_InterruptGetStatus +#endif +}; + +#endif /* LPSPI4 */ + +#if defined(LPSPI5) && RTE_SPI5 + +/* User needs to provide the implementation for LPSPI5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPSPI5_GetFreq(void); +extern void LPSPI5_InitPins(void); +extern void LPSPI5_DeinitPins(void); + +cmsis_lpspi_resource_t LPSPI5_Resource = {LPSPI5, 5, LPSPI5_GetFreq}; + +#if RTE_SPI5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +cmsis_lpspi_edma_resource_t LPSPI5_EdmaResource = { + RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, RTE_SPI5_DMA_TX_PERI_SEL, + RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH, RTE_SPI5_DMA_RX_PERI_SEL, +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_SPI5_DMA_TX_DMAMUX_BASE, RTE_SPI5_DMA_RX_DMAMUX_BASE, +#endif +}; + +AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI5_EdmaHandle); +edma_handle_t LPSPI5_EdmaTxDataToTxRegHandle; +edma_handle_t LPSPI5_EdmaRxRegToRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi5_edma_driver_state") +cmsis_lpspi_edma_driver_state_t LPSPI5_EdmaDriverState = { +#else +cmsis_lpspi_edma_driver_state_t LPSPI5_EdmaDriverState = { +#endif + &LPSPI5_Resource, + &LPSPI5_EdmaResource, + &LPSPI5_EdmaHandle, + &LPSPI5_EdmaRxRegToRxDataHandle, + &LPSPI5_EdmaTxDataToTxRegHandle, +}; + +static int32_t LPSPI5_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI5_InitPins(); + return LPSPI_EdmaInitialize(cb_event, &LPSPI5_EdmaDriverState); +} + +static int32_t LPSPI5_EdmaUninitialize(void) +{ + LPSPI5_DeinitPins(); + return LPSPI_EdmaUninitialize(&LPSPI5_EdmaDriverState); +} + +static int32_t LPSPI5_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_EdmaPowerControl(state, &LPSPI5_EdmaDriverState); +} + +static int32_t LPSPI5_EdmaSend(const void *data, uint32_t num) +{ + return LPSPI_EdmaSend(data, num, &LPSPI5_EdmaDriverState); +} + +static int32_t LPSPI5_EdmaReceive(void *data, uint32_t num) +{ + return LPSPI_EdmaReceive(data, num, &LPSPI5_EdmaDriverState); +} + +static int32_t LPSPI5_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI5_EdmaDriverState); +} + +static uint32_t LPSPI5_EdmaGetCount(void) +{ + return LPSPI_EdmaGetCount(&LPSPI5_EdmaDriverState); +} + +static int32_t LPSPI5_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPSPI_EdmaControl(control, arg, &LPSPI5_EdmaDriverState); +} + +static ARM_SPI_STATUS LPSPI5_EdmaGetStatus(void) +{ + return LPSPI_EdmaGetStatus(&LPSPI5_EdmaDriverState); +} + +#endif + +#else + +cmsis_lpspi_handle_t LPSPI5_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpspi5_interrupt_driver_state") +cmsis_lpspi_interrupt_driver_state_t LPSPI5_InterruptDriverState = { +#else +cmsis_lpspi_interrupt_driver_state_t LPSPI5_InterruptDriverState = { +#endif + &LPSPI5_Resource, &LPSPI5_Handle, +}; + +static int32_t LPSPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + LPSPI5_InitPins(); + return LPSPI_InterruptInitialize(cb_event, &LPSPI5_InterruptDriverState); +} + +static int32_t LPSPI5_InterruptUninitialize(void) +{ + LPSPI5_DeinitPins(); + return LPSPI_InterruptUninitialize(&LPSPI5_InterruptDriverState); +} + +static int32_t LPSPI5_InterruptPowerControl(ARM_POWER_STATE state) +{ + return LPSPI_InterruptPowerControl(state, &LPSPI5_InterruptDriverState); +} + +static int32_t LPSPI5_InterruptSend(const void *data, uint32_t num) +{ + return LPSPI_InterruptSend(data, num, &LPSPI5_InterruptDriverState); +} + +static int32_t LPSPI5_InterruptReceive(void *data, uint32_t num) +{ + return LPSPI_InterruptReceive(data, num, &LPSPI5_InterruptDriverState); +} + +static int32_t LPSPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI5_InterruptDriverState); +} + +static uint32_t LPSPI5_InterruptGetCount(void) +{ + return LPSPI_InterruptGetCount(&LPSPI5_InterruptDriverState); +} + +static int32_t LPSPI5_InterruptControl(uint32_t control, uint32_t arg) +{ + return LPSPI_InterruptControl(control, arg, &LPSPI5_InterruptDriverState); +} + +static ARM_SPI_STATUS LPSPI5_InterruptGetStatus(void) +{ + return LPSPI_InterruptGetStatus(&LPSPI5_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI5 = { + LPSPIx_GetVersion, LPSPIx_GetCapabilities, +#if RTE_SPI5_DMA_EN + LPSPI5_EdmaInitialize, LPSPI5_EdmaUninitialize, LPSPI5_EdmaPowerControl, LPSPI5_EdmaSend, LPSPI5_EdmaReceive, + LPSPI5_EdmaTransfer, LPSPI5_EdmaGetCount, LPSPI5_EdmaControl, LPSPI5_EdmaGetStatus +#else + LPSPI5_InterruptInitialize, LPSPI5_InterruptUninitialize, LPSPI5_InterruptPowerControl, LPSPI5_InterruptSend, + LPSPI5_InterruptReceive, LPSPI5_InterruptTransfer, LPSPI5_InterruptGetCount, LPSPI5_InterruptControl, + LPSPI5_InterruptGetStatus +#endif +}; + +#endif /* LPSPI5 */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.h new file mode 100644 index 0000000000..cdf106ff29 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FSL_LPSPI_CMSISI_H_ +#define _FSL_LPSPI_CMSISI_H_ + +#include "fsl_common.h" +#include "RTE_Device.h" +#include "Driver_SPI.h" +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +#include "fsl_lpspi_edma.h" +#endif +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) +#include "fsl_dmamux.h" +#endif + +#if defined(LPSPI0) +extern ARM_DRIVER_SPI Driver_SPI0; +#endif /* LPSPI0 */ + +#if defined(LPSPI1) +extern ARM_DRIVER_SPI Driver_SPI1; +#endif /* LPSPI1 */ + +#if defined(LPSPI2) +extern ARM_DRIVER_SPI Driver_SPI2; +#endif /* LPSPI2 */ + +#if defined(LPSPI3) +extern ARM_DRIVER_SPI Driver_SPI3; +#endif /* LPSPI3 */ + +#if defined(LPSPI4) +extern ARM_DRIVER_SPI Driver_SPI4; +#endif /* LPSPI4 */ + +#if defined(LPSPI5) +extern ARM_DRIVER_SPI Driver_SPI5; +#endif /* LPSPI5 */ + +/* SPI Driver state flags */ +#define SPI_FLAG_UNINIT (0) +#define SPI_FLAG_INIT (1 << 0) +#define SPI_FLAG_POWER (1 << 1) +#define SPI_FLAG_CONFIGURED (1 << 2) + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.c new file mode 100644 index 0000000000..75a9840b4b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.c @@ -0,0 +1,3309 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "fsl_lpuart_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_cmsis" +#endif + + +/* Re-mapping for LPUART & UART indexing. */ +#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && FSL_FEATURE_SOC_UART_COUNT + +#ifdef RTE_USART0 +#undef RTE_USART0 +#endif +#ifdef RTE_USART0_DMA_EN +#undef RTE_USART0_DMA_EN +#endif +#ifdef RTE_USART0_DMA_TX_CH +#undef RTE_USART0_DMA_TX_CH +#endif +#ifdef RTE_USART0_DMA_TX_PERI_SEL +#undef RTE_USART0_DMA_TX_PERI_SEL +#endif +#ifdef RTE_USART0_DMA_TX_DMAMUX_BASE +#undef RTE_USART0_DMA_TX_DMAMUX_BASE +#endif +#ifdef RTE_USART0_DMA_TX_DMA_BASE +#undef RTE_USART0_DMA_TX_DMA_BASE +#endif +#ifdef RTE_USART0_DMA_RX_CH +#undef RTE_USART0_DMA_RX_CH +#endif +#ifdef RTE_USART0_DMA_RX_PERI_SEL +#undef RTE_USART0_DMA_RX_PERI_SEL +#endif +#ifdef RTE_USART0_DMA_RX_DMAMUX_BASE +#undef RTE_USART0_DMA_RX_DMAMUX_BASE +#endif +#ifdef RTE_USART0_DMA_RX_DMA_BASE +#undef RTE_USART0_DMA_RX_DMA_BASE +#endif +#ifdef USART0_RX_BUFFER_ENABLE +#undef USART0_RX_BUFFER_ENABLE +#endif + +#if (FSL_FEATURE_SOC_UART_COUNT == 3) + +#ifdef RTE_USART3 +#define RTE_USART0 RTE_USART3 +#endif +#ifdef RTE_USART3_DMA_EN +#define RTE_USART0_DMA_EN RTE_USART3_DMA_EN +#endif +#ifdef RTE_USART3_DMA_TX_CH +#define RTE_USART0_DMA_TX_CH RTE_USART3_DMA_TX_CH +#endif +#ifdef RTE_USART3_DMA_TX_PERI_SEL +#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART3_DMA_TX_PERI_SEL +#endif +#ifdef RTE_USART3_DMA_TX_DMAMUX_BASE +#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART3_DMA_TX_DMAMUX_BASE +#endif +#ifdef RTE_USART3_DMA_TX_DMA_BASE +#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART3_DMA_TX_DMA_BASE +#endif +#ifdef RTE_USART3_DMA_RX_CH +#define RTE_USART0_DMA_RX_CH RTE_USART3_DMA_RX_CH +#endif +#ifdef RTE_USART3_DMA_RX_PERI_SEL +#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART3_DMA_RX_PERI_SEL +#endif +#ifdef RTE_USART3_DMA_RX_DMAMUX_BASE +#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART3_DMA_RX_DMAMUX_BASE +#endif +#ifdef RTE_USART3_DMA_RX_DMA_BASE +#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART3_DMA_RX_DMA_BASE +#endif +#ifdef USART3_RX_BUFFER_ENABLE +#define USART0_RX_BUFFER_ENABLE USART3_RX_BUFFER_ENABLE +#endif + +#endif + +#if (FSL_FEATURE_SOC_UART_COUNT == 4) + +#ifdef RTE_USART4 +#define RTE_USART0 RTE_USART4 +#endif +#ifdef RTE_USART4_DMA_EN +#define RTE_USART0_DMA_EN RTE_USART4_DMA_EN +#endif +#ifdef RTE_USART4_DMA_TX_CH +#define RTE_USART0_DMA_TX_CH RTE_USART4_DMA_TX_CH +#endif +#ifdef RTE_USART4_DMA_TX_PERI_SEL +#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART4_DMA_TX_PERI_SEL +#endif +#ifdef RTE_USART4_DMA_TX_DMAMUX_BASE +#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART4_DMA_TX_DMAMUX_BASE +#endif +#ifdef RTE_USART4_DMA_TX_DMA_BASE +#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART4_DMA_TX_DMA_BASE +#endif +#ifdef RTE_USART4_DMA_RX_CH +#define RTE_USART0_DMA_RX_CH RTE_USART4_DMA_RX_CH +#endif +#ifdef RTE_USART4_DMA_RX_PERI_SEL +#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART4_DMA_RX_PERI_SEL +#endif +#ifdef RTE_USART4_DMA_RX_DMAMUX_BASE +#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART4_DMA_RX_DMAMUX_BASE +#endif +#ifdef RTE_USART4_DMA_RX_DMA_BASE +#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART4_DMA_RX_DMA_BASE +#endif +#ifdef USART4_RX_BUFFER_ENABLE +#define USART0_RX_BUFFER_ENABLE USART4_RX_BUFFER_ENABLE +#endif + +#endif + +#if (FSL_FEATURE_SOC_UART_COUNT == 5) + +#ifdef RTE_USART5 +#define RTE_USART0 RTE_USART5 +#endif +#ifdef RTE_USART5_DMA_EN +#define RTE_USART0_DMA_EN RTE_USART5_DMA_EN +#endif +#ifdef RTE_USART5_DMA_TX_CH +#define RTE_USART0_DMA_TX_CH RTE_USART5_DMA_TX_CH +#endif +#ifdef RTE_USART5_DMA_TX_PERI_SEL +#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART5_DMA_TX_PERI_SEL +#endif +#ifdef RTE_USART5_DMA_TX_DMAMUX_BASE +#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART5_DMA_TX_DMAMUX_BASE +#endif +#ifdef RTE_USART5_DMA_TX_DMA_BASE +#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART5_DMA_TX_DMA_BASE +#endif +#ifdef RTE_USART5_DMA_RX_CH +#define RTE_USART0_DMA_RX_CH RTE_USART5_DMA_RX_CH +#endif +#ifdef RTE_USART5_DMA_RX_PERI_SEL +#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART5_DMA_RX_PERI_SEL +#endif +#ifdef RTE_USART5_DMA_RX_DMAMUX_BASE +#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART5_DMA_RX_DMAMUX_BASE +#endif +#ifdef RTE_USART5_DMA_RX_DMA_BASE +#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART5_DMA_RX_DMA_BASE +#endif +#ifdef USART5_RX_BUFFER_ENABLE +#define USART0_RX_BUFFER_ENABLE USART5_RX_BUFFER_ENABLE +#endif + +#endif + +#endif + +#if ((RTE_USART0 && defined(LPUART0)) || (RTE_USART1 && defined(LPUART1)) || (RTE_USART2 && defined(LPUART2)) || \ + (RTE_USART3 && defined(LPUART3)) || (RTE_USART4 && defined(LPUART4)) || (RTE_USART5 && defined(LPUART5)) || \ + (RTE_USART6 && defined(LPUART6))) + +#define ARM_LPUART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_lpuart_resource +{ + LPUART_Type *base; /*!< LPUART peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ +} cmsis_lpuart_resource_t; + +typedef struct _cmsis_lpuart_non_blocking_driver_state +{ + cmsis_lpuart_resource_t *resource; /*!< Basic LPUART resource. */ + lpuart_handle_t *handle; /*!< Interupt transfer handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpuart_non_blocking_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +typedef struct _cmsis_lpuart_dma_resource +{ + DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ + uint32_t txDmaChannel; /*!< DMA channel for LPUART TX. */ + uint8_t txDmaRequest; /*!< TX DMA request source. */ + + DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ + uint32_t rxDmaChannel; /*!< DMA channel for LPUART RX. */ + uint8_t rxDmaRequest; /*!< RX DMA request source. */ + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */ + DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */ +#endif +} cmsis_lpuart_dma_resource_t; + +typedef struct _cmsis_lpuart_dma_driver_state +{ + cmsis_lpuart_resource_t *resource; /*!< LPUART basic resource. */ + cmsis_lpuart_dma_resource_t *dmaResource; /*!< LPUART DMA resource. */ + lpuart_dma_handle_t *handle; /*!< LPUART DMA transfer handle. */ + dma_handle_t *rxHandle; /*!< DMA RX handle. */ + dma_handle_t *txHandle; /*!< DMA TX handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpuart_dma_driver_state_t; +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +typedef struct _cmsis_lpuart_edma_resource +{ + DMA_Type *txEdmaBase; /*!< EDMA peripheral base address for TX. */ + uint32_t txEdmaChannel; /*!< EDMA channel for LPUART TX. */ + uint8_t txDmaRequest; /*!< TX EDMA request source. */ + + DMA_Type *rxEdmaBase; /*!< EDMA peripheral base address for RX. */ + uint32_t rxEdmaChannel; /*!< EDMA channel for LPUART RX. */ + uint8_t rxDmaRequest; /*!< RX EDMA request source. */ + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */ + DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */ +#endif +} cmsis_lpuart_edma_resource_t; + +typedef struct _cmsis_lpuart_edma_driver_state +{ + cmsis_lpuart_resource_t *resource; /*!< LPUART basic resource. */ + cmsis_lpuart_edma_resource_t *dmaResource; /*!< LPUART EDMA resource. */ + lpuart_edma_handle_t *handle; /*!< LPUART EDMA transfer handle. */ + edma_handle_t *rxHandle; /*!< EDMA RX handle. */ + edma_handle_t *txHandle; /*!< EDMA TX handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_lpuart_edma_driver_state_t; +#endif + +enum _lpuart_transfer_states +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_lpuartDriverVersion = {ARM_USART_API_VERSION, ARM_LPUART_DRV_VERSION}; + +static const ARM_USART_CAPABILITIES s_lpuartDriverCapabilities = { + 1, /* supports LPUART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports LPUART Single-wire mode */ + 0, /* supports LPUART IrDA mode */ + 0, /* supports LPUART Smart Card mode */ + 0, /* Smart Card Clock generator */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +/* + * Common control function used by LPUART_NonBlockingControl/LPUART_DmaControl/LPUART_EdmaControl + */ +static int32_t LPUART_CommonControl(uint32_t control, + uint32_t arg, + cmsis_lpuart_resource_t *resource, + uint8_t *isConfigured) +{ + lpuart_config_t config; + + LPUART_GetDefaultConfig(&config); + + switch (control & ARM_USART_CONTROL_Msk) + { + case ARM_USART_MODE_ASYNCHRONOUS: + /* USART Baudrate */ + config.baudRate_Bps = arg; + break; + + /* TX/RX IO is controlled in application layer. */ + case ARM_USART_CONTROL_TX: + if (arg) + { + LPUART_EnableTx(resource->base, true); + } + else + { + LPUART_EnableTx(resource->base, false); + } + return ARM_DRIVER_OK; + + case ARM_USART_CONTROL_RX: + if (arg) + { + LPUART_EnableRx(resource->base, true); + } + else + { + LPUART_EnableRx(resource->base, false); + } + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_DATA_BITS_Msk) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + case ARM_USART_DATA_BITS_7: + config.dataBitsCount = kLPUART_SevenDataBits; + break; +#endif + case ARM_USART_DATA_BITS_8: + config.dataBitsCount = kLPUART_EightDataBits; + break; + + default: + return ARM_USART_ERROR_DATA_BITS; + } + + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + config.parityMode = kLPUART_ParityDisabled; + break; + case ARM_USART_PARITY_EVEN: + config.parityMode = kLPUART_ParityEven; + break; + case ARM_USART_PARITY_ODD: + config.parityMode = kLPUART_ParityOdd; + break; + default: + return ARM_USART_ERROR_PARITY; + } + + switch (control & ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + /* The GetDefaultConfig has already set for this case. */ + break; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + case ARM_USART_STOP_BITS_2: + config.stopBitCount = kLPUART_TwoStopBit; + break; +#endif + default: + return ARM_USART_ERROR_STOP_BITS; + } + + /* If LPUART is already configured, deinit it first. */ + if ((*isConfigured) & USART_FLAG_CONFIGURED) + { + LPUART_Deinit(resource->base); + *isConfigured &= ~USART_FLAG_CONFIGURED; + } + + config.enableTx = true; + config.enableRx = true; + + if (kStatus_LPUART_BaudrateNotSupport == LPUART_Init(resource->base, &config, resource->GetFreq())) + { + return ARM_USART_ERROR_BAUDRATE; + } + + *isConfigured |= USART_FLAG_CONFIGURED; + + return ARM_DRIVER_OK; +} + +static ARM_DRIVER_VERSION LPUARTx_GetVersion(void) +{ + return s_lpuartDriverVersion; +} + +static ARM_USART_CAPABILITIES LPUARTx_GetCapabilities(void) +{ + return s_lpuartDriverCapabilities; +} + +static int32_t LPUARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS LPUARTx_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status; + + modem_status.cts = 0U; + modem_status.dsr = 0U; + modem_status.ri = 0U; + modem_status.dcd = 0U; + modem_status.reserved = 0U; + + return modem_status; +} + +#endif + +#if ((RTE_USART0_DMA_EN && defined(LPUART0)) || (RTE_USART1_DMA_EN && defined(LPUART1)) || \ + (RTE_USART2_DMA_EN && defined(LPUART2)) || (RTE_USART3_DMA_EN && defined(LPUART3)) || \ + (RTE_USART4_DMA_EN && defined(LPUART4)) || (RTE_USART5_DMA_EN && defined(LPUART5)) || \ + (RTE_USART6_DMA_EN && defined(LPUART6))) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +void KSDK_LPUART_DmaCallback(LPUART_Type *base, lpuart_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_LPUART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + else if (kStatus_LPUART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t LPUART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_lpuart_dma_driver_state_t *lpuart) +{ + if (!(lpuart->flags & USART_FLAG_INIT)) + { + lpuart->cb_event = cb_event; + lpuart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPUART_DmaUninitialize(cmsis_lpuart_dma_driver_state_t *lpuart) +{ + lpuart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t LPUART_DmaPowerControl(ARM_POWER_STATE state, cmsis_lpuart_dma_driver_state_t *lpuart) +{ + lpuart_config_t config; + cmsis_lpuart_dma_resource_t *dmaResource; + + switch (state) + { + case ARM_POWER_OFF: + if (lpuart->flags & USART_FLAG_POWER) + { + LPUART_Deinit(lpuart->resource->base); +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxDmaChannel); + DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txDmaChannel); +#endif + lpuart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (lpuart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpuart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + LPUART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + dmaResource = lpuart->dmaResource; + + /* Set up DMA setting. */ + DMA_CreateHandle(lpuart->rxHandle, dmaResource->rxDmaBase, dmaResource->rxDmaChannel); + + DMA_CreateHandle(lpuart->txHandle, dmaResource->txDmaBase, dmaResource->txDmaChannel); +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel, dmaResource->rxDmaRequest); + DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel); + + DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txDmaChannel, dmaResource->txDmaRequest); + DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txDmaChannel); +#endif + /* Setup the LPUART. */ + LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq()); + LPUART_TransferCreateHandleDMA(lpuart->resource->base, lpuart->handle, KSDK_LPUART_DmaCallback, + (void *)lpuart->cb_event, lpuart->txHandle, lpuart->rxHandle); + + lpuart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPUART_DmaSend(const void *data, uint32_t num, cmsis_lpuart_dma_driver_state_t *lpuart) +{ + int32_t ret; + status_t status; + lpuart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = LPUART_TransferSendDMA(lpuart->resource->base, lpuart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPUART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPUART_DmaReceive(void *data, uint32_t num, cmsis_lpuart_dma_driver_state_t *lpuart) +{ + int32_t ret; + status_t status; + lpuart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = LPUART_TransferReceiveDMA(lpuart->resource->base, lpuart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPUART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPUART_DmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_lpuart_dma_driver_state_t *lpuart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t LPUART_DmaGetTxCount(cmsis_lpuart_dma_driver_state_t *lpuart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCountDMA(lpuart->resource->base, lpuart->handle, &cnt)) + { + cnt = lpuart->handle->txDataSizeAll; + } + + return cnt; +} + +static uint32_t LPUART_DmaGetRxCount(cmsis_lpuart_dma_driver_state_t *lpuart) +{ + uint32_t cnt; + + if (kStatus_NoTransferInProgress == LPUART_TransferGetReceiveCountDMA(lpuart->resource->base, lpuart->handle, &cnt)) + { + cnt = lpuart->handle->rxDataSizeAll; + } + + return cnt; +} + +static int32_t LPUART_DmaControl(uint32_t control, uint32_t arg, cmsis_lpuart_dma_driver_state_t *lpuart) +{ + /* Must be power on. */ + if (!(lpuart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + LPUART_TransferAbortSendDMA(lpuart->resource->base, lpuart->handle); + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + LPUART_TransferAbortReceiveDMA(lpuart->resource->base, lpuart->handle); + return ARM_DRIVER_OK; + + default: + break; + } + + return LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->flags); +} + +static ARM_USART_STATUS LPUART_DmaGetStatus(cmsis_lpuart_dma_driver_state_t *lpuart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base); + + stat.tx_busy = ((kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag))); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag))); +#else + stat.rx_break = 0U; +#endif + stat.rx_framing_error = (!(!(ksdk_lpuart_status & kLPUART_FramingErrorFlag))); + stat.rx_parity_error = (!(!(ksdk_lpuart_status & kLPUART_ParityErrorFlag))); + stat.reserved = 0U; + + return stat; +} +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +void KSDK_LPUART_EdmaCallback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_LPUART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + if (kStatus_LPUART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t LPUART_EdmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_lpuart_edma_driver_state_t *lpuart) +{ + if (!(lpuart->flags & USART_FLAG_INIT)) + { + lpuart->cb_event = cb_event; + lpuart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPUART_EdmaUninitialize(cmsis_lpuart_edma_driver_state_t *lpuart) +{ + lpuart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t LPUART_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpuart_edma_driver_state_t *lpuart) +{ + lpuart_config_t config; + cmsis_lpuart_edma_resource_t *dmaResource; + + switch (state) + { + case ARM_POWER_OFF: + if (lpuart->flags & USART_FLAG_POWER) + { + LPUART_Deinit(lpuart->resource->base); + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxEdmaChannel); + DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txEdmaChannel); +#endif + lpuart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (lpuart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpuart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + LPUART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + dmaResource = lpuart->dmaResource; + + /* Set up EDMA setting. */ + EDMA_CreateHandle(lpuart->rxHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel); + EDMA_CreateHandle(lpuart->txHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel); + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest); + DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel); + + DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, dmaResource->txDmaRequest); + DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel); +#endif + /* Setup the LPUART. */ + LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq()); + LPUART_TransferCreateHandleEDMA(lpuart->resource->base, lpuart->handle, KSDK_LPUART_EdmaCallback, + (void *)lpuart->cb_event, lpuart->txHandle, lpuart->rxHandle); + + lpuart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPUART_EdmaSend(const void *data, uint32_t num, cmsis_lpuart_edma_driver_state_t *lpuart) +{ + int32_t ret; + status_t status; + lpuart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = LPUART_SendEDMA(lpuart->resource->base, lpuart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPUART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPUART_EdmaReceive(void *data, uint32_t num, cmsis_lpuart_edma_driver_state_t *lpuart) +{ + int32_t ret; + status_t status; + lpuart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = LPUART_ReceiveEDMA(lpuart->resource->base, lpuart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPUART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPUART_EdmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_lpuart_edma_driver_state_t *lpuart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t LPUART_EdmaGetTxCount(cmsis_lpuart_edma_driver_state_t *lpuart) +{ + uint32_t cnt; + + if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCountEDMA(lpuart->resource->base, lpuart->handle, &cnt)) + { + cnt = lpuart->handle->txDataSizeAll; + } + + return cnt; +} + +static uint32_t LPUART_EdmaGetRxCount(cmsis_lpuart_edma_driver_state_t *lpuart) +{ + uint32_t cnt; + + if (kStatus_NoTransferInProgress == + LPUART_TransferGetReceiveCountEDMA(lpuart->resource->base, lpuart->handle, &cnt)) + { + cnt = lpuart->handle->rxDataSizeAll; + } + + return cnt; +} + +static int32_t LPUART_EdmaControl(uint32_t control, uint32_t arg, cmsis_lpuart_edma_driver_state_t *lpuart) +{ + /* Must be power on. */ + if (!(lpuart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + LPUART_TransferAbortSendEDMA(lpuart->resource->base, lpuart->handle); + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + LPUART_TransferAbortReceiveEDMA(lpuart->resource->base, lpuart->handle); + return ARM_DRIVER_OK; + + default: + break; + } + + return LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->flags); +} + +static ARM_USART_STATUS LPUART_EdmaGetStatus(cmsis_lpuart_edma_driver_state_t *lpuart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base); + + stat.tx_busy = ((kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag))); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag))); +#else + stat.rx_break = 0U; +#endif + stat.rx_framing_error = (!(!(ksdk_lpuart_status & kLPUART_FramingErrorFlag))); + stat.rx_parity_error = (!(!(ksdk_lpuart_status & kLPUART_ParityErrorFlag))); + stat.reserved = 0U; + + return stat; +} +#endif + +#endif + +#if (((RTE_USART0 && !RTE_USART0_DMA_EN) && defined(LPUART0)) || \ + ((RTE_USART1 && !RTE_USART1_DMA_EN) && defined(LPUART1)) || \ + ((RTE_USART2 && !RTE_USART2_DMA_EN) && defined(LPUART2)) || \ + ((RTE_USART3 && !RTE_USART3_DMA_EN) && defined(LPUART3)) || \ + ((RTE_USART4 && !RTE_USART4_DMA_EN) && defined(LPUART4)) || \ + ((RTE_USART5 && !RTE_USART5_DMA_EN) && defined(LPUART5)) || \ + ((RTE_USART6 && !RTE_USART6_DMA_EN) && defined(LPUART6))) + +void KSDK_LPUART_NonBlockingCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_LPUART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + if (kStatus_LPUART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + if (kStatus_LPUART_RxHardwareOverrun == status) + { + event = ARM_USART_EVENT_RX_OVERFLOW; + } + + /* User data is actually CMSIS driver callback. */ + if ((0U != event) && (userData)) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t LPUART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, + cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + if (!(lpuart->flags & USART_FLAG_INIT)) + { + lpuart->cb_event = cb_event; + lpuart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPUART_NonBlockingUninitialize(cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + lpuart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t LPUART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + lpuart_config_t config; + + switch (state) + { + case ARM_POWER_OFF: + if (lpuart->flags & USART_FLAG_POWER) + { + LPUART_Deinit(lpuart->resource->base); + lpuart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (lpuart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (lpuart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + LPUART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq()); + LPUART_TransferCreateHandle(lpuart->resource->base, lpuart->handle, KSDK_LPUART_NonBlockingCallback, + (void *)lpuart->cb_event); + lpuart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t LPUART_NonBlockingSend(const void *data, uint32_t num, cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + int32_t ret; + status_t status; + lpuart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = LPUART_TransferSendNonBlocking(lpuart->resource->base, lpuart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPUART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPUART_NonBlockingReceive(void *data, uint32_t num, cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + int32_t ret; + status_t status; + lpuart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = LPUART_TransferReceiveNonBlocking(lpuart->resource->base, lpuart->handle, &xfer, NULL); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_LPUART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t LPUART_NonBlockingTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t LPUART_NonBlockingGetTxCount(cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCount(lpuart->resource->base, lpuart->handle, &cnt)) + { + cnt = lpuart->handle->txDataSizeAll; + } + + return cnt; +} + +static uint32_t LPUART_NonBlockingGetRxCount(cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + uint32_t cnt; + + if (kStatus_NoTransferInProgress == LPUART_TransferGetReceiveCount(lpuart->resource->base, lpuart->handle, &cnt)) + { + cnt = lpuart->handle->rxDataSizeAll; + } + + return cnt; +} + +static int32_t LPUART_NonBlockingControl(uint32_t control, + uint32_t arg, + cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + /* Must be power on. */ + if (!(lpuart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + LPUART_TransferAbortSend(lpuart->resource->base, lpuart->handle); + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + LPUART_TransferAbortReceive(lpuart->resource->base, lpuart->handle); + return ARM_DRIVER_OK; + + default: + break; + } + + return LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->flags); +} + +static ARM_USART_STATUS LPUART_NonBlockingGetStatus(cmsis_lpuart_non_blocking_driver_state_t *lpuart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base); + + stat.tx_busy = ((kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag))); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag))); +#else + stat.rx_break = 0U; +#endif + stat.rx_framing_error = (!(!(ksdk_lpuart_status & kLPUART_FramingErrorFlag))); + stat.rx_parity_error = (!(!(ksdk_lpuart_status & kLPUART_ParityErrorFlag))); + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(LPUART0) && RTE_USART0 + +/* User needs to provide the implementation for LPUART0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART0_GetFreq(void); +extern void LPUART0_InitPins(void); +extern void LPUART0_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART0_Resource = {LPUART0, LPUART0_GetFreq}; + +#if RTE_USART0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART0_DmaResource = { + RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_PERI_SEL, + RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART0_DmaHandle; +dma_handle_t LPUART0_DmaRxHandle; +dma_handle_t LPUART0_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart0_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = { +#endif + &LPUART0_Resource, &LPUART0_DmaResource, &LPUART0_DmaHandle, &LPUART0_DmaRxHandle, &LPUART0_DmaTxHandle, +}; + +static int32_t LPUART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART0_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART0_DmaDriverState); +} + +static int32_t LPUART0_DmaUninitialize(void) +{ + LPUART0_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART0_DmaDriverState); +} + +static int32_t LPUART0_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART0_DmaDriverState); +} + +static int32_t LPUART0_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART0_DmaDriverState); +} + +static int32_t LPUART0_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART0_DmaDriverState); +} + +static int32_t LPUART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART0_DmaDriverState); +} + +static uint32_t LPUART0_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART0_DmaDriverState); +} + +static uint32_t LPUART0_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART0_DmaDriverState); +} + +static int32_t LPUART0_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART0_DmaDriverState); +} + +static ARM_USART_STATUS LPUART0_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART0_DmaDriverState); +} + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART0_EdmaResource = { + RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_PERI_SEL, + + RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART0_EdmaHandle; +edma_handle_t LPUART0_EdmaRxHandle; +edma_handle_t LPUART0_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart0_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = { +#endif + &LPUART0_Resource, &LPUART0_EdmaResource, &LPUART0_EdmaHandle, &LPUART0_EdmaRxHandle, &LPUART0_EdmaTxHandle, +}; + +static int32_t LPUART0_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART0_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART0_EdmaDriverState); +} + +static int32_t LPUART0_EdmaUninitialize(void) +{ + LPUART0_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART0_EdmaDriverState); +} + +static int32_t LPUART0_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART0_EdmaDriverState); +} + +static int32_t LPUART0_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART0_EdmaDriverState); +} + +static int32_t LPUART0_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART0_EdmaDriverState); +} + +static int32_t LPUART0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART0_EdmaDriverState); +} + +static uint32_t LPUART0_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART0_EdmaDriverState); +} + +static uint32_t LPUART0_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART0_EdmaDriverState); +} + +static int32_t LPUART0_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART0_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART0_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART0_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART0_Handle; + +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart0_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart0_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = { +#endif + &LPUART0_Resource, &LPUART0_Handle, +}; + +static int32_t LPUART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART0_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART0_NonBlockingDriverState); +} + +static int32_t LPUART0_NonBlockingUninitialize(void) +{ + LPUART0_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART0_NonBlockingDriverState); +} + +static int32_t LPUART0_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART0_NonBlockingDriverState); + +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART0_NonBlockingDriverState.resource->base, + LPUART0_NonBlockingDriverState.handle, lpuart0_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART0_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART0_NonBlockingDriverState); +} + +static int32_t LPUART0_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART0_NonBlockingDriverState); +} + +static int32_t LPUART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART0_NonBlockingDriverState); +} + +static uint32_t LPUART0_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART0_NonBlockingDriverState); +} + +static uint32_t LPUART0_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART0_NonBlockingDriverState); +} + +static int32_t LPUART0_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART0_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART0_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART0_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART0_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART0_NonBlockingDriverState); +} + +#endif + +#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) +#if (FSL_FEATURE_SOC_UART_COUNT == 3) +ARM_DRIVER_USART Driver_USART3 = { +#elif(FSL_FEATURE_SOC_UART_COUNT == 4) +ARM_DRIVER_USART Driver_USART4 = { +#elif(FSL_FEATURE_SOC_UART_COUNT == 5) +ARM_DRIVER_USART Driver_USART5 = { +#else +ARM_DRIVER_USART Driver_USART0 = { +#endif +#else +ARM_DRIVER_USART Driver_USART0 = { +#endif + + LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART0_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART0_EdmaInitialize, LPUART0_EdmaUninitialize, LPUART0_EdmaPowerControl, LPUART0_EdmaSend, + LPUART0_EdmaReceive, LPUART0_EdmaTransfer, LPUART0_EdmaGetTxCount, LPUART0_EdmaGetRxCount, + LPUART0_EdmaControl, LPUART0_EdmaGetStatus, +#else + LPUART0_DmaInitialize, LPUART0_DmaUninitialize, LPUART0_DmaPowerControl, LPUART0_DmaSend, LPUART0_DmaReceive, + LPUART0_DmaTransfer, LPUART0_DmaGetTxCount, LPUART0_DmaGetRxCount, LPUART0_DmaControl, LPUART0_DmaGetStatus, +#endif +#else + LPUART0_NonBlockingInitialize, + LPUART0_NonBlockingUninitialize, + LPUART0_NonBlockingPowerControl, + LPUART0_NonBlockingSend, + LPUART0_NonBlockingReceive, + LPUART0_NonBlockingTransfer, + LPUART0_NonBlockingGetTxCount, + LPUART0_NonBlockingGetRxCount, + LPUART0_NonBlockingControl, + LPUART0_NonBlockingGetStatus, +#endif + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART0 */ + +#if defined(LPUART1) && RTE_USART1 + +/* User needs to provide the implementation for LPUART1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART1_GetFreq(void); +extern void LPUART1_InitPins(void); +extern void LPUART1_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART1_Resource = {LPUART1, LPUART1_GetFreq}; + +#if RTE_USART1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART1_DmaResource = { + RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_PERI_SEL, + RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART1_DmaHandle; +dma_handle_t LPUART1_DmaRxHandle; +dma_handle_t LPUART1_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart1_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = { +#endif + &LPUART1_Resource, &LPUART1_DmaResource, &LPUART1_DmaHandle, &LPUART1_DmaRxHandle, &LPUART1_DmaTxHandle, +}; + +static int32_t LPUART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART1_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART1_DmaDriverState); +} + +static int32_t LPUART1_DmaUninitialize(void) +{ + LPUART1_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART1_DmaDriverState); +} + +static int32_t LPUART1_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART1_DmaDriverState); +} + +static int32_t LPUART1_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART1_DmaDriverState); +} + +static int32_t LPUART1_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART1_DmaDriverState); +} + +static int32_t LPUART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART1_DmaDriverState); +} + +static uint32_t LPUART1_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART1_DmaDriverState); +} + +static uint32_t LPUART1_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART1_DmaDriverState); +} + +static int32_t LPUART1_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART1_DmaDriverState); +} + +static ARM_USART_STATUS LPUART1_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART1_DmaDriverState); +} + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART1_EdmaResource = { + RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_PERI_SEL, + RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART1_EdmaHandle; +edma_handle_t LPUART1_EdmaRxHandle; +edma_handle_t LPUART1_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart1_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = { +#endif + &LPUART1_Resource, &LPUART1_EdmaResource, &LPUART1_EdmaHandle, &LPUART1_EdmaRxHandle, &LPUART1_EdmaTxHandle, +}; + +static int32_t LPUART1_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART1_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART1_EdmaDriverState); +} + +static int32_t LPUART1_EdmaUninitialize(void) +{ + LPUART1_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART1_EdmaDriverState); +} + +static int32_t LPUART1_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART1_EdmaDriverState); +} + +static int32_t LPUART1_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART1_EdmaDriverState); +} + +static int32_t LPUART1_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART1_EdmaDriverState); +} + +static int32_t LPUART1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART1_EdmaDriverState); +} + +static uint32_t LPUART1_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART1_EdmaDriverState); +} + +static uint32_t LPUART1_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART1_EdmaDriverState); +} + +static int32_t LPUART1_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART1_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART1_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART1_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART1_Handle; + +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart1_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = { +#endif + &LPUART1_Resource, &LPUART1_Handle, +}; + +static int32_t LPUART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART1_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART1_NonBlockingDriverState); +} + +static int32_t LPUART1_NonBlockingUninitialize(void) +{ + LPUART1_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART1_NonBlockingDriverState); +} + +static int32_t LPUART1_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART1_NonBlockingDriverState); + +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART1_NonBlockingDriverState.resource->base, + LPUART1_NonBlockingDriverState.handle, lpuart1_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART1_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART1_NonBlockingDriverState); +} + +static int32_t LPUART1_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART1_NonBlockingDriverState); +} + +static int32_t LPUART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART1_NonBlockingDriverState); +} + +static uint32_t LPUART1_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART1_NonBlockingDriverState); +} + +static uint32_t LPUART1_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART1_NonBlockingDriverState); +} + +static int32_t LPUART1_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART1_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART1_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART1_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART1_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART1_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART1 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART1_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART1_EdmaInitialize, LPUART1_EdmaUninitialize, LPUART1_EdmaPowerControl, + LPUART1_EdmaSend, LPUART1_EdmaReceive, LPUART1_EdmaTransfer, + LPUART1_EdmaGetTxCount, LPUART1_EdmaGetRxCount, LPUART1_EdmaControl, + LPUART1_EdmaGetStatus, +#else + LPUART1_DmaInitialize, LPUART1_DmaUninitialize, LPUART1_DmaPowerControl, + LPUART1_DmaSend, LPUART1_DmaReceive, LPUART1_DmaTransfer, + LPUART1_DmaGetTxCount, LPUART1_DmaGetRxCount, LPUART1_DmaControl, + LPUART1_DmaGetStatus, +#endif +#else + LPUART1_NonBlockingInitialize, + LPUART1_NonBlockingUninitialize, + LPUART1_NonBlockingPowerControl, + LPUART1_NonBlockingSend, + LPUART1_NonBlockingReceive, + LPUART1_NonBlockingTransfer, + LPUART1_NonBlockingGetTxCount, + LPUART1_NonBlockingGetRxCount, + LPUART1_NonBlockingControl, + LPUART1_NonBlockingGetStatus, +#endif + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART1 */ + +#if defined(LPUART2) && RTE_USART2 + +/* User needs to provide the implementation for LPUART2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART2_GetFreq(void); +extern void LPUART2_InitPins(void); +extern void LPUART2_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART2_Resource = {LPUART2, LPUART2_GetFreq}; + +#if RTE_USART2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART2_DmaResource = { + RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_PERI_SEL, + RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART2_DmaHandle; +dma_handle_t LPUART2_DmaRxHandle; +dma_handle_t LPUART2_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart2_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = { +#endif + &LPUART2_Resource, &LPUART2_DmaResource, &LPUART2_DmaHandle, &LPUART2_DmaRxHandle, &LPUART2_DmaTxHandle, +}; + +static int32_t LPUART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART2_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART2_DmaDriverState); +} + +static int32_t LPUART2_DmaUninitialize(void) +{ + LPUART2_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART2_DmaDriverState); +} + +static int32_t LPUART2_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART2_DmaDriverState); +} + +static int32_t LPUART2_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART2_DmaDriverState); +} + +static int32_t LPUART2_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART2_DmaDriverState); +} + +static int32_t LPUART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART2_DmaDriverState); +} + +static uint32_t LPUART2_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART2_DmaDriverState); +} + +static uint32_t LPUART2_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART2_DmaDriverState); +} + +static int32_t LPUART2_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART2_DmaDriverState); +} + +static ARM_USART_STATUS LPUART2_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART2_DmaDriverState); +} + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART2_EdmaResource = { + RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_PERI_SEL, + RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART2_EdmaHandle; +edma_handle_t LPUART2_EdmaRxHandle; +edma_handle_t LPUART2_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart2_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = { +#endif + &LPUART2_Resource, &LPUART2_EdmaResource, &LPUART2_EdmaHandle, &LPUART2_EdmaRxHandle, &LPUART2_EdmaTxHandle, +}; + +static int32_t LPUART2_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART2_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART2_EdmaDriverState); +} + +static int32_t LPUART2_EdmaUninitialize(void) +{ + LPUART2_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART2_EdmaDriverState); +} + +static int32_t LPUART2_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART2_EdmaDriverState); +} + +static int32_t LPUART2_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART2_EdmaDriverState); +} + +static int32_t LPUART2_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART2_EdmaDriverState); +} + +static int32_t LPUART2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART2_EdmaDriverState); +} + +static uint32_t LPUART2_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART2_EdmaDriverState); +} + +static uint32_t LPUART2_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART2_EdmaDriverState); +} + +static int32_t LPUART2_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART2_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART2_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART2_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART2_Handle; + +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart2_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = { +#endif + &LPUART2_Resource, &LPUART2_Handle, +}; + +static int32_t LPUART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART2_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART2_NonBlockingDriverState); +} + +static int32_t LPUART2_NonBlockingUninitialize(void) +{ + LPUART2_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART2_NonBlockingDriverState); +} + +static int32_t LPUART2_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART2_NonBlockingDriverState); + +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART2_NonBlockingDriverState.resource->base, + LPUART2_NonBlockingDriverState.handle, lpuart2_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART2_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART2_NonBlockingDriverState); +} + +static int32_t LPUART2_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART2_NonBlockingDriverState); +} + +static int32_t LPUART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART2_NonBlockingDriverState); +} + +static uint32_t LPUART2_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART2_NonBlockingDriverState); +} + +static uint32_t LPUART2_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART2_NonBlockingDriverState); +} + +static int32_t LPUART2_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART2_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART2_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART2_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART2_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART2_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART2 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART2_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART2_EdmaInitialize, LPUART2_EdmaUninitialize, LPUART2_EdmaPowerControl, + LPUART2_EdmaSend, LPUART2_EdmaReceive, LPUART2_EdmaTransfer, + LPUART2_EdmaGetTxCount, LPUART2_EdmaGetRxCount, LPUART2_EdmaControl, + LPUART2_EdmaGetStatus, +#else + LPUART2_DmaInitialize, LPUART2_DmaUninitialize, LPUART2_DmaPowerControl, + LPUART2_DmaSend, LPUART2_DmaReceive, LPUART2_DmaTransfer, + LPUART2_DmaGetTxCount, LPUART2_DmaGetRxCount, LPUART2_DmaControl, + LPUART2_DmaGetStatus, +#endif +#else + LPUART2_NonBlockingInitialize, + LPUART2_NonBlockingUninitialize, + LPUART2_NonBlockingPowerControl, + LPUART2_NonBlockingSend, + LPUART2_NonBlockingReceive, + LPUART2_NonBlockingTransfer, + LPUART2_NonBlockingGetTxCount, + LPUART2_NonBlockingGetRxCount, + LPUART2_NonBlockingControl, + LPUART2_NonBlockingGetStatus, +#endif + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART2 */ + +#if defined(LPUART3) && RTE_USART3 + +/* User needs to provide the implementation for LPUART3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART3_GetFreq(void); +extern void LPUART3_InitPins(void); +extern void LPUART3_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART3_Resource = {LPUART3, LPUART3_GetFreq}; + +#if RTE_USART3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART3_DmaResource = { + RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_PERI_SEL, + RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART3_DmaHandle; +dma_handle_t LPUART3_DmaRxHandle; +dma_handle_t LPUART3_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart3_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = { +#endif + &LPUART3_Resource, &LPUART3_DmaResource, &LPUART3_DmaHandle, &LPUART3_DmaRxHandle, &LPUART3_DmaTxHandle, +}; + +static int32_t LPUART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART3_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART3_DmaDriverState); +} + +static int32_t LPUART3_DmaUninitialize(void) +{ + LPUART3_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART3_DmaDriverState); +} + +static int32_t LPUART3_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART3_DmaDriverState); +} + +static int32_t LPUART3_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART3_DmaDriverState); +} + +static int32_t LPUART3_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART3_DmaDriverState); +} + +static int32_t LPUART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART3_DmaDriverState); +} + +static uint32_t LPUART3_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART3_DmaDriverState); +} + +static uint32_t LPUART3_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART3_DmaDriverState); +} + +static int32_t LPUART3_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART3_DmaDriverState); +} + +static ARM_USART_STATUS LPUART3_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART3_DmaDriverState); +} + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART3_EdmaResource = { + RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_PERI_SEL, + RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART3_EdmaHandle; +edma_handle_t LPUART3_EdmaRxHandle; +edma_handle_t LPUART3_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart3_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = { +#endif + &LPUART3_Resource, &LPUART3_EdmaResource, &LPUART3_EdmaHandle, &LPUART3_EdmaRxHandle, &LPUART3_EdmaTxHandle, +}; + +static int32_t LPUART3_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART3_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART3_EdmaDriverState); +} + +static int32_t LPUART3_EdmaUninitialize(void) +{ + LPUART3_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART3_EdmaDriverState); +} + +static int32_t LPUART3_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART3_EdmaDriverState); +} + +static int32_t LPUART3_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART3_EdmaDriverState); +} + +static int32_t LPUART3_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART3_EdmaDriverState); +} + +static int32_t LPUART3_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART3_EdmaDriverState); +} + +static uint32_t LPUART3_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART3_EdmaDriverState); +} + +static uint32_t LPUART3_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART3_EdmaDriverState); +} + +static int32_t LPUART3_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART3_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART3_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART3_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART3_Handle; + +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart3_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = { +#endif + &LPUART3_Resource, &LPUART3_Handle, +}; + +static int32_t LPUART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART3_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART3_NonBlockingDriverState); +} + +static int32_t LPUART3_NonBlockingUninitialize(void) +{ + LPUART3_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART3_NonBlockingDriverState); +} + +static int32_t LPUART3_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART3_NonBlockingDriverState); + +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART3_NonBlockingDriverState.resource->base, + LPUART3_NonBlockingDriverState.handle, lpuart3_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART3_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART3_NonBlockingDriverState); +} + +static int32_t LPUART3_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART3_NonBlockingDriverState); +} + +static int32_t LPUART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART3_NonBlockingDriverState); +} + +static uint32_t LPUART3_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART3_NonBlockingDriverState); +} + +static uint32_t LPUART3_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART3_NonBlockingDriverState); +} + +static int32_t LPUART3_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART3_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART3_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART3_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART3_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART3_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART3 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART3_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART3_EdmaInitialize, LPUART3_EdmaUninitialize, LPUART3_EdmaPowerControl, + LPUART3_EdmaSend, LPUART3_EdmaReceive, LPUART3_EdmaTransfer, + LPUART3_EdmaGetTxCount, LPUART3_EdmaGetRxCount, LPUART3_EdmaControl, + LPUART3_EdmaGetStatus, +#else + LPUART3_DmaInitialize, LPUART3_DmaUninitialize, LPUART3_DmaPowerControl, + LPUART3_DmaSend, LPUART3_DmaReceive, LPUART3_DmaTransfer, + LPUART3_DmaGetTxCount, LPUART3_DmaGetRxCount, LPUART3_DmaControl, + LPUART3_DmaGetStatus, +#endif +#else + LPUART3_NonBlockingInitialize, + LPUART3_NonBlockingUninitialize, + LPUART3_NonBlockingPowerControl, + LPUART3_NonBlockingSend, + LPUART3_NonBlockingReceive, + LPUART3_NonBlockingTransfer, + LPUART3_NonBlockingGetTxCount, + LPUART3_NonBlockingGetRxCount, + LPUART3_NonBlockingControl, + LPUART3_NonBlockingGetStatus, +#endif + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART3 */ + +#if defined(LPUART4) && RTE_USART4 + +/* User needs to provide the implementation for LPUART4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART4_GetFreq(void); +extern void LPUART4_InitPins(void); +extern void LPUART4_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART4_Resource = {LPUART4, LPUART4_GetFreq}; + +#if RTE_USART4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART4_DmaResource = { + RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_PERI_SEL, + RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART4_DmaHandle; +dma_handle_t LPUART4_DmaRxHandle; +dma_handle_t LPUART4_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart4_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = { +#endif + &LPUART4_Resource, &LPUART4_DmaResource, &LPUART4_DmaHandle, &LPUART4_DmaRxHandle, &LPUART4_DmaTxHandle}; + +static int32_t LPUART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART4_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART4_DmaDriverState); +} + +static int32_t LPUART4_DmaUninitialize(void) +{ + LPUART4_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART4_DmaDriverState); +} + +static int32_t LPUART4_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART4_DmaDriverState); +} + +static int32_t LPUART4_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART4_DmaDriverState); +} + +static int32_t LPUART4_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART4_DmaDriverState); +} + +static int32_t LPUART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART4_DmaDriverState); +} + +static uint32_t LPUART4_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART4_DmaDriverState); +} + +static uint32_t LPUART4_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART4_DmaDriverState); +} + +static int32_t LPUART4_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART4_DmaDriverState); +} + +static ARM_USART_STATUS LPUART4_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART4_DmaDriverState); +} + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART4_EdmaResource = { + RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_PERI_SEL, + RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART4_EdmaHandle; +edma_handle_t LPUART4_EdmaRxHandle; +edma_handle_t LPUART4_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart4_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = { +#endif + &LPUART4_Resource, &LPUART4_EdmaResource, &LPUART4_EdmaHandle, &LPUART4_EdmaRxHandle, &LPUART4_EdmaTxHandle}; + +static int32_t LPUART4_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART4_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART4_EdmaDriverState); +} + +static int32_t LPUART4_EdmaUninitialize(void) +{ + LPUART4_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART4_EdmaDriverState); +} + +static int32_t LPUART4_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART4_EdmaDriverState); +} + +static int32_t LPUART4_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART4_EdmaDriverState); +} + +static int32_t LPUART4_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART4_EdmaDriverState); +} + +static int32_t LPUART4_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART4_EdmaDriverState); +} + +static uint32_t LPUART4_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART4_EdmaDriverState); +} + +static uint32_t LPUART4_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART4_EdmaDriverState); +} + +static int32_t LPUART4_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART4_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART4_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART4_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART4_Handle; + +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart4_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = { +#endif + &LPUART4_Resource, &LPUART4_Handle, +}; + +static int32_t LPUART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART4_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART4_NonBlockingDriverState); +} + +static int32_t LPUART4_NonBlockingUninitialize(void) +{ + LPUART4_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART4_NonBlockingDriverState); +} + +static int32_t LPUART4_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART4_NonBlockingDriverState); + +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART4_NonBlockingDriverState.resource->base, + LPUART4_NonBlockingDriverState.handle, lpuart4_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART4_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART4_NonBlockingDriverState); +} + +static int32_t LPUART4_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART4_NonBlockingDriverState); +} + +static int32_t LPUART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART4_NonBlockingDriverState); +} + +static uint32_t LPUART4_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART4_NonBlockingDriverState); +} + +static uint32_t LPUART4_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART4_NonBlockingDriverState); +} + +static int32_t LPUART4_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART4_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART4_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART4_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART4_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART4_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART4 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART4_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART4_EdmaInitialize, LPUART4_EdmaUninitialize, LPUART4_EdmaPowerControl, + LPUART4_EdmaSend, LPUART4_EdmaReceive, LPUART4_EdmaTransfer, + LPUART4_EdmaGetTxCount, LPUART4_EdmaGetRxCount, LPUART4_EdmaControl, + LPUART4_EdmaGetStatus, +#else + LPUART4_DmaInitialize, LPUART4_DmaUninitialize, LPUART4_DmaPowerControl, + LPUART4_DmaSend, LPUART4_DmaReceive, LPUART4_DmaTransfer, + LPUART4_DmaGetTxCount, LPUART4_DmaGetRxCount, LPUART4_DmaControl, + LPUART4_DmaGetStatus, +#endif +#else + LPUART4_NonBlockingInitialize, + LPUART4_NonBlockingUninitialize, + LPUART4_NonBlockingPowerControl, + LPUART4_NonBlockingSend, + LPUART4_NonBlockingReceive, + LPUART4_NonBlockingTransfer, + LPUART4_NonBlockingGetTxCount, + LPUART4_NonBlockingGetRxCount, + LPUART4_NonBlockingControl, + LPUART4_NonBlockingGetStatus, +#endif + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART4 */ + +#if defined(LPUART5) && RTE_USART5 + +/* User needs to provide the implementation for LPUART5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART5_GetFreq(void); +extern void LPUART5_InitPins(void); +extern void LPUART5_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART5_Resource = {LPUART5, LPUART5_GetFreq}; + +#if RTE_USART5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART5_DmaResource = { + RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_PERI_SEL, + RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART5_DmaHandle; +dma_handle_t LPUART5_DmaRxHandle; +dma_handle_t LPUART5_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart5_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = { +#endif + &LPUART5_Resource, &LPUART5_DmaResource, &LPUART5_DmaHandle, &LPUART5_DmaRxHandle, &LPUART5_DmaTxHandle, +}; + +static int32_t LPUART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART5_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART5_DmaDriverState); +} + +static int32_t LPUART5_DmaUninitialize(void) +{ + LPUART5_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART5_DmaDriverState); +} + +static int32_t LPUART5_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART5_DmaDriverState); +} + +static int32_t LPUART5_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART5_DmaDriverState); +} + +static int32_t LPUART5_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART5_DmaDriverState); +} + +static int32_t LPUART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART5_DmaDriverState); +} + +static uint32_t LPUART5_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART5_DmaDriverState); +} + +static uint32_t LPUART5_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART5_DmaDriverState); +} + +static int32_t LPUART5_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART5_DmaDriverState); +} + +static ARM_USART_STATUS LPUART5_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART5_DmaDriverState); +} + +/* LPUART5 Driver Control Block */ + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART5_EdmaResource = { + RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_PERI_SEL, + RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART5_EdmaHandle; +edma_handle_t LPUART5_EdmaRxHandle; +edma_handle_t LPUART5_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart5_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = { +#endif + &LPUART5_Resource, &LPUART5_EdmaResource, &LPUART5_EdmaHandle, &LPUART5_EdmaRxHandle, &LPUART5_EdmaTxHandle, +}; + +static int32_t LPUART5_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART5_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART5_EdmaDriverState); +} + +static int32_t LPUART5_EdmaUninitialize(void) +{ + LPUART5_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART5_EdmaDriverState); +} + +static int32_t LPUART5_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART5_EdmaDriverState); +} + +static int32_t LPUART5_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART5_EdmaDriverState); +} + +static int32_t LPUART5_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART5_EdmaDriverState); +} + +static int32_t LPUART5_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART5_EdmaDriverState); +} + +static uint32_t LPUART5_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART5_EdmaDriverState); +} + +static uint32_t LPUART5_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART5_EdmaDriverState); +} + +static int32_t LPUART5_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART5_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART5_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART5_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART5_Handle; + +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart5_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = { +#endif + &LPUART5_Resource, &LPUART5_Handle, +}; + +static int32_t LPUART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART5_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART5_NonBlockingDriverState); +} + +static int32_t LPUART5_NonBlockingUninitialize(void) +{ + LPUART5_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART5_NonBlockingDriverState); +} + +static int32_t LPUART5_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART5_NonBlockingDriverState); + +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART5_NonBlockingDriverState.resource->base, + LPUART5_NonBlockingDriverState.handle, lpuart5_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART5_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART5_NonBlockingDriverState); +} + +static int32_t LPUART5_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART5_NonBlockingDriverState); +} + +static int32_t LPUART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART5_NonBlockingDriverState); +} + +static uint32_t LPUART5_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART5_NonBlockingDriverState); +} + +static uint32_t LPUART5_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART5_NonBlockingDriverState); +} + +static int32_t LPUART5_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART5_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART5_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART5_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART5_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART5_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART5 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART5_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART5_EdmaInitialize, LPUART5_EdmaUninitialize, LPUART5_EdmaPowerControl, + LPUART5_EdmaSend, LPUART5_EdmaReceive, LPUART5_EdmaTransfer, + LPUART5_EdmaGetTxCount, LPUART5_EdmaGetRxCount, LPUART5_EdmaControl, + LPUART5_EdmaGetStatus, +#else + LPUART5_DmaInitialize, LPUART5_DmaUninitialize, LPUART5_DmaPowerControl, + LPUART5_DmaSend, LPUART5_DmaReceive, LPUART5_DmaTransfer, + LPUART5_DmaGetTxCount, LPUART5_DmaGetRxCount, LPUART5_DmaControl, + LPUART5_DmaGetStatus, +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ +#else + LPUART5_NonBlockingInitialize, + LPUART5_NonBlockingUninitialize, + LPUART5_NonBlockingPowerControl, + LPUART5_NonBlockingSend, + LPUART5_NonBlockingReceive, + LPUART5_NonBlockingTransfer, + LPUART5_NonBlockingGetTxCount, + LPUART5_NonBlockingGetRxCount, + LPUART5_NonBlockingControl, + LPUART5_NonBlockingGetStatus, +#endif /* RTE_USART5_DMA_EN */ + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART5 */ + +#if defined(LPUART6) && RTE_USART6 + +/* User needs to provide the implementation for LPUART5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t LPUART6_GetFreq(void); +extern void LPUART6_InitPins(void); +extern void LPUART6_DeinitPins(void); + +cmsis_lpuart_resource_t LPUART6_Resource = {LPUART6, LPUART6_GetFreq}; + +#if RTE_USART6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_lpuart_dma_resource_t LPUART6_DmaResource = { + RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_TX_PERI_SEL, + RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, RTE_USART6_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART6_DMA_TX_DMAMUX_BASE, RTE_USART6_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_dma_handle_t LPUART6_DmaHandle; +dma_handle_t LPUART6_DmaRxHandle; +dma_handle_t LPUART6_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart5_dma_driver_state") +cmsis_lpuart_dma_driver_state_t LPUART6_DmaDriverState = { +#else +cmsis_lpuart_dma_driver_state_t LPUART6_DmaDriverState = { +#endif + &LPUART6_Resource, &LPUART6_DmaResource, &LPUART6_DmaHandle, &LPUART6_DmaRxHandle, &LPUART6_DmaTxHandle, +}; + +static int32_t LPUART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART6_InitPins(); + return LPUART_DmaInitialize(cb_event, &LPUART6_DmaDriverState); +} + +static int32_t LPUART6_DmaUninitialize(void) +{ + LPUART6_DeinitPins(); + return LPUART_DmaUninitialize(&LPUART6_DmaDriverState); +} + +static int32_t LPUART6_DmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_DmaPowerControl(state, &LPUART6_DmaDriverState); +} + +static int32_t LPUART6_DmaSend(const void *data, uint32_t num) +{ + return LPUART_DmaSend(data, num, &LPUART6_DmaDriverState); +} + +static int32_t LPUART6_DmaReceive(void *data, uint32_t num) +{ + return LPUART_DmaReceive(data, num, &LPUART6_DmaDriverState); +} + +static int32_t LPUART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_DmaTransfer(data_out, data_in, num, &LPUART6_DmaDriverState); +} + +static uint32_t LPUART6_DmaGetTxCount(void) +{ + return LPUART_DmaGetTxCount(&LPUART6_DmaDriverState); +} + +static uint32_t LPUART6_DmaGetRxCount(void) +{ + return LPUART_DmaGetRxCount(&LPUART6_DmaDriverState); +} + +static int32_t LPUART6_DmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_DmaControl(control, arg, &LPUART6_DmaDriverState); +} + +static ARM_USART_STATUS LPUART6_DmaGetStatus(void) +{ + return LPUART_DmaGetStatus(&LPUART6_DmaDriverState); +} + +/* LPUART6 Driver Control Block */ + +#endif + +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + +cmsis_lpuart_edma_resource_t LPUART6_EdmaResource = { + RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_TX_PERI_SEL, + RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, RTE_USART6_DMA_RX_PERI_SEL, + +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) + RTE_USART6_DMA_TX_DMAMUX_BASE, RTE_USART6_DMA_RX_DMAMUX_BASE, +#endif +}; + +lpuart_edma_handle_t LPUART6_EdmaHandle; +edma_handle_t LPUART6_EdmaRxHandle; +edma_handle_t LPUART6_EdmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart6_edma_driver_state") +cmsis_lpuart_edma_driver_state_t LPUART6_EdmaDriverState = { +#else +cmsis_lpuart_edma_driver_state_t LPUART6_EdmaDriverState = { +#endif + &LPUART6_Resource, &LPUART6_EdmaResource, &LPUART6_EdmaHandle, &LPUART6_EdmaRxHandle, &LPUART6_EdmaTxHandle, +}; + +static int32_t LPUART6_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART6_InitPins(); + return LPUART_EdmaInitialize(cb_event, &LPUART6_EdmaDriverState); +} + +static int32_t LPUART6_EdmaUninitialize(void) +{ + LPUART6_DeinitPins(); + return LPUART_EdmaUninitialize(&LPUART6_EdmaDriverState); +} + +static int32_t LPUART6_EdmaPowerControl(ARM_POWER_STATE state) +{ + return LPUART_EdmaPowerControl(state, &LPUART6_EdmaDriverState); +} + +static int32_t LPUART6_EdmaSend(const void *data, uint32_t num) +{ + return LPUART_EdmaSend(data, num, &LPUART6_EdmaDriverState); +} + +static int32_t LPUART6_EdmaReceive(void *data, uint32_t num) +{ + return LPUART_EdmaReceive(data, num, &LPUART6_EdmaDriverState); +} + +static int32_t LPUART6_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART6_EdmaDriverState); +} + +static uint32_t LPUART6_EdmaGetTxCount(void) +{ + return LPUART_EdmaGetTxCount(&LPUART6_EdmaDriverState); +} + +static uint32_t LPUART6_EdmaGetRxCount(void) +{ + return LPUART_EdmaGetRxCount(&LPUART6_EdmaDriverState); +} + +static int32_t LPUART6_EdmaControl(uint32_t control, uint32_t arg) +{ + return LPUART_EdmaControl(control, arg, &LPUART6_EdmaDriverState); +} + +static ARM_USART_STATUS LPUART6_EdmaGetStatus(void) +{ + return LPUART_EdmaGetStatus(&LPUART6_EdmaDriverState); +} + +#endif + +#else + +lpuart_handle_t LPUART6_Handle; + +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) +static uint8_t lpuart6_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("lpuart6_non_blocking_driver_state") +cmsis_lpuart_non_blocking_driver_state_t LPUART6_NonBlockingDriverState = { +#else +cmsis_lpuart_non_blocking_driver_state_t LPUART6_NonBlockingDriverState = { +#endif + &LPUART6_Resource, &LPUART6_Handle, +}; + +static int32_t LPUART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + LPUART6_InitPins(); + return LPUART_NonBlockingInitialize(cb_event, &LPUART6_NonBlockingDriverState); +} + +static int32_t LPUART6_NonBlockingUninitialize(void) +{ + LPUART6_DeinitPins(); + return LPUART_NonBlockingUninitialize(&LPUART6_NonBlockingDriverState); +} + +static int32_t LPUART6_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = LPUART_NonBlockingPowerControl(state, &LPUART6_NonBlockingDriverState); + +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (LPUART6_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + LPUART_TransferStartRingBuffer(LPUART6_NonBlockingDriverState.resource->base, + LPUART6_NonBlockingDriverState.handle, lpuart6_rxRingBuffer, + USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t LPUART6_NonBlockingSend(const void *data, uint32_t num) +{ + return LPUART_NonBlockingSend(data, num, &LPUART6_NonBlockingDriverState); +} + +static int32_t LPUART6_NonBlockingReceive(void *data, uint32_t num) +{ + return LPUART_NonBlockingReceive(data, num, &LPUART6_NonBlockingDriverState); +} + +static int32_t LPUART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART6_NonBlockingDriverState); +} + +static uint32_t LPUART6_NonBlockingGetTxCount(void) +{ + return LPUART_NonBlockingGetTxCount(&LPUART6_NonBlockingDriverState); +} + +static uint32_t LPUART6_NonBlockingGetRxCount(void) +{ + return LPUART_NonBlockingGetRxCount(&LPUART6_NonBlockingDriverState); +} + +static int32_t LPUART6_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = LPUART_NonBlockingControl(control, arg, &LPUART6_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } + + /* Enable the receive interrupts if ring buffer is used */ + if (LPUART6_NonBlockingDriverState.handle->rxRingBuffer != NULL) + { + LPUART_EnableInterrupts(LPUART6_NonBlockingDriverState.resource->base, + kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS LPUART6_NonBlockingGetStatus(void) +{ + return LPUART_NonBlockingGetStatus(&LPUART6_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART6 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, +#if RTE_USART6_DMA_EN +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) + LPUART6_EdmaInitialize, LPUART6_EdmaUninitialize, LPUART6_EdmaPowerControl, + LPUART6_EdmaSend, LPUART6_EdmaReceive, LPUART6_EdmaTransfer, + LPUART6_EdmaGetTxCount, LPUART6_EdmaGetRxCount, LPUART6_EdmaControl, + LPUART6_EdmaGetStatus, +#else + LPUART6_DmaInitialize, LPUART6_DmaUninitialize, LPUART6_DmaPowerControl, + LPUART6_DmaSend, LPUART6_DmaReceive, LPUART6_DmaTransfer, + LPUART6_DmaGetTxCount, LPUART6_DmaGetRxCount, LPUART6_DmaControl, + LPUART6_DmaGetStatus, +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ +#else + LPUART6_NonBlockingInitialize, + LPUART6_NonBlockingUninitialize, + LPUART6_NonBlockingPowerControl, + LPUART6_NonBlockingSend, + LPUART6_NonBlockingReceive, + LPUART6_NonBlockingTransfer, + LPUART6_NonBlockingGetTxCount, + LPUART6_NonBlockingGetRxCount, + LPUART6_NonBlockingControl, + LPUART6_NonBlockingGetStatus, +#endif /* RTE_USART6_DMA_EN */ + LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; + +#endif /* LPUART6 */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.h new file mode 100644 index 0000000000..5d3a8530ed --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FSL_LPUART_CMSIS_H_ +#define _FSL_LPUART_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "fsl_lpuart.h" +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) +#include "fsl_dmamux.h" +#endif +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_lpuart_dma.h" +#endif +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +#include "fsl_lpuart_edma.h" +#endif + +#if defined(LPUART0) +extern ARM_DRIVER_USART Driver_USART0; +#endif /* LPUART0 */ + +#if defined(LPUART1) +extern ARM_DRIVER_USART Driver_USART1; +#endif /* LPUART1 */ + +#if defined(LPUART2) +extern ARM_DRIVER_USART Driver_USART2; +#endif /* LPUART2 */ + +#if defined(LPUART3) +extern ARM_DRIVER_USART Driver_USART3; +#endif /* LPUART3 */ + +#if defined(LPUART4) +extern ARM_DRIVER_USART Driver_USART4; +#endif /* LPUART4 */ + +#if defined(LPUART5) +extern ARM_DRIVER_USART Driver_USART5; +#endif /* LPUART5 */ + +#if defined(LPUART6) +extern ARM_DRIVER_USART Driver_USART6; +#endif /* LPUART6 */ + +#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 3) + +extern ARM_DRIVER_USART Driver_USART3; + +#endif + +#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 4) + +extern ARM_DRIVER_USART Driver_USART4; + +#endif + +#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 5) +extern ARM_DRIVER_USART Driver_USART5; + +#endif + +/* USART Driver state flags */ +#define USART_FLAG_UNINIT (0) +#define USART_FLAG_INIT (1 << 0) +#define USART_FLAG_POWER (1 << 1) +#define USART_FLAG_CONFIGURED (1 << 2) + +#endif /* _FSL_LPUART_CMSIS_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.c new file mode 100644 index 0000000000..d3cdb6f645 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.c @@ -0,0 +1,306 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC module. + * + * @param base ADC peripheral base address + */ +static uint32_t ADC_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC bases for each instance. */ +static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; + +/*! @brief Pointers to ADC clocks for each instance. */ +static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) + { + if (s_adcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_adcBases)); + + return instance; +} + +void ADC_Init(ADC_Type *base, const adc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Enable the clock. */ + CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); + /* ADCx_CFG */ + tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ + tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) | + ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution); + if (config->enableOverWrite) + { + tmp32 |= ADC_CFG_OVWREN_MASK; + } + if (config->enableLongSample) + { + tmp32 |= ADC_CFG_ADLSMP_MASK; + } + if (config->enableLowPower) + { + tmp32 |= ADC_CFG_ADLPC_MASK; + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG_ADHSC_MASK; + } + base->CFG = tmp32; + + /* ADCx_GC */ + tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK); + if (config->enableContinuousConversion) + { + tmp32 |= ADC_GC_ADCO_MASK; + } + if (config->enableAsynchronousClockOutput) + { + tmp32 |= ADC_GC_ADACKEN_MASK; + } + base->GC = tmp32; +} + +void ADC_Deinit(ADC_Type *base) +{ + /* Disable the clock. */ + CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); +} + +void ADC_GetDefaultConfig(adc_config_t *config) +{ + assert(NULL != config); + + config->enableAsynchronousClockOutput = true; + config->enableOverWrite = false; + config->enableContinuousConversion = false; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableLongSample = false; + config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + config->clockSource = kADC_ClockSourceAD; + config->clockDriver = kADC_ClockDriver1; + config->resolution = kADC_Resolution12Bit; +} + +void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config) +{ + assert(NULL != config); + assert(channelGroup < ADC_HC_COUNT); + + uint32_t tmp32; + + tmp32 = ADC_HC_ADCH(config->channelNumber); + if (config->enableInterruptOnConversionCompleted) + { + tmp32 |= ADC_HC_AIEN_MASK; + } + base->HC[channelGroup] = tmp32; +} + +/* + *To complete calibration, the user must follow the below procedure: + * 1. Configure ADC_CFG with actual operating values for maximum accuracy. + * 2. Configure the ADC_GC values along with CAL bit. + * 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. + * 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. + */ +status_t ADC_DoAutoCalibration(ADC_Type *base) +{ + status_t status = kStatus_Success; +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + bool bHWTrigger = false; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) + { + bHWTrigger = true; + ADC_EnableHardwareTrigger(base, false); + } +#endif + + /* Clear the CALF and launch the calibration. */ + base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */ + base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */ + + /* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */ + while (0U != (base->GC & ADC_GC_CAL_MASK)) + { + /* Check the CALF when the calibration is active. */ + if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) + { + status = kStatus_Fail; + break; + } + } + + /* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */ + if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */ + { + status = kStatus_Fail; + } + if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */ + { + status = kStatus_Fail; + } + + /* Clear conversion done flag. */ + ADC_GetChannelConversionValue(base, 0U); + +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + /* Restore original trigger mode. */ + if (true == bHWTrigger) + { + ADC_EnableHardwareTrigger(base, true); + } +#endif + + return status; +} + +void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = ADC_OFS_OFS(config->offsetValue); + if (config->enableSigned) + { + tmp32 |= ADC_OFS_SIGN_MASK; + } + base->OFS = tmp32; +} + +void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config) +{ + uint32_t tmp32; + + tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + base->GC = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_GC_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC_HardwareCompareMode0: + break; + case kADC_HardwareCompareMode1: + tmp32 |= ADC_GC_ACFGT_MASK; + break; + case kADC_HardwareCompareMode2: + tmp32 |= ADC_GC_ACREN_MASK; + break; + case kADC_HardwareCompareMode3: + tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK; + break; + default: + break; + } + base->GC = tmp32; + + /* Load the compare values. */ + tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2); + base->CV = tmp32; +} + +void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode) +{ + uint32_t tmp32; + + if (mode == kADC_HardwareAverageDiasable) + { + base->GC &= ~ADC_GC_AVGE_MASK; + } + else + { + tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK; + tmp32 |= ADC_CFG_AVGS(mode); + base->CFG = tmp32; + base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */ + } +} + +void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + uint32_t tmp32 = 0; + + if (0U != (mask & kADC_CalibrationFailedFlag)) + { + tmp32 |= ADC_GS_CALF_MASK; + } + if (0U != (mask & kADC_ConversionActiveFlag)) + { + tmp32 |= ADC_GS_ADACT_MASK; + } + base->GS = tmp32; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.h new file mode 100644 index 0000000000..8b46fb1ba5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.h @@ -0,0 +1,446 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC_H_ +#define _FSL_ADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc_12b1msps_sar + * @{ + */ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! @brief ADC driver version */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! + * @brief Converter's status flags. + */ +typedef enum _adc_status_flags +{ + kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ + kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ + kADC_AsynchronousWakeupInterruptFlag = + ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */ +} adc_status_flags_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc_reference_voltage_source +{ + kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */ +} adc_reference_voltage_source_t; + +/*! + * @brief Sample time duration. + */ +typedef enum _adc_sample_period_mode +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */ + kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */ + kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */ + kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */ + /* This group of enumeration is for a public user. */ + /* For long sample mode. */ + kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */ + kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */ + kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */ + kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */ + /* For short sample mode. */ + kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */ + kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */ + kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */ + kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */ +} adc_sample_period_mode_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc_clock_source +{ + kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */ + kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */ +#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) + kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */ +#endif + kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */ +} adc_clock_source_t; + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc_clock_drvier +{ + kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc_clock_driver_t; + +/*! + * @brief Converter's resolution. + */ +typedef enum _adc_resolution +{ + kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */ + kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */ + kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */ +} adc_resolution_t; + +/*! + * @brief Converter hardware compare mode. + */ +typedef enum _adc_hardware_compare_mode +{ + kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */ + kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */ + kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or + the result is Greater than value2. + Value1 > Value2, compare true if the result is less than value1 And the + result is greater than value2*/ + kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal + to value1 And the result is less than or equal to value2. + Value1 > Value2, compare true if the result is greater than or equal to + value1 Or the result is less than or equal to value2. */ +} adc_hardware_compare_mode_t; + +/*! + * @brief Converter hardware average mode. + */ +typedef enum _adc_hardware_average_mode +{ + kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */ +} adc_hardware_average_mode_t; + +/*! + * @brief Converter configuration. + */ +typedef struct _adc_config +{ + bool enableOverWrite; /*!< Enable the overwriting. */ + bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable the low power mode. */ + bool enableLongSample; /*!< Enable the long sample mode. */ + bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */ + adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */ + adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */ + adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */ + adc_resolution_t resolution; /*!< Select the ADC resolution mode. */ +} adc_config_t; + +/*! + * @brief Converter Offset configuration. + */ +typedef struct _adc_offest_config +{ + bool enableSigned; /*!< if false,The offset value is added with the raw result. + if true,The offset value is subtracted from the raw converted value. */ + uint32_t offsetValue; /*!< User configurable offset value(0-4095). */ +} adc_offest_config_t; + +/*! + * @brief ADC hardware compare configuration. + * + * In kADC_HardwareCompareMode0, compare true if the result is less than the value1. + * In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1. + * In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is + * Greater than value2. + * Value1 > Value2, compare true if the result is less than value1 And the result is + * Greater than value2. + * In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the + * result is less than or equal to value2. + * Value1 > Value2, compare true if the result is greater than or equal to value1 Or the + * result is less than or equal to value2. + */ +typedef struct _adc_hardware_compare_config +{ + adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc_hardware_compare_mode_t". */ + uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */ + uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */ +} adc_hardware_compare_config_t; + +/*! + * @brief ADC channel conversion configuration. + */ +typedef struct _adc_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ +} adc_channel_config_t; +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize the ADC module. + * + * @param base ADC peripheral base address. + * @param config Pointer to "adc_config_t" structure. + */ +void ADC_Init(ADC_Type *base, const adc_config_t *config); + +/*! + * @brief De-initializes the ADC module. + * + * @param base ADC peripheral base address. + */ +void ADC_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are: + * @code + * config->enableAsynchronousClockOutput = true; + * config->enableOverWrite = false; + * config->enableContinuousConversion = false; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableLongSample = false; + * config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + * config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + * config->clockSource = kADC_ClockSourceAD; + * config->clockDriver = kADC_ClockDriver1; + * config->resolution = kADC_Resolution12Bit; + * @endcode + * @param base ADC peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ADC_GetDefaultConfig(adc_config_t *config); + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B + * registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and + * hardware + * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual + * about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to the "adc_channel_config_t" structure for the conversion channel. + */ +void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * A conversion is completed when the result of the conversion is transferred into the data + * result registers. (provided the compare function & hardware averaging is disabled), this is + * indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only, + * if the last of the selected number of conversions is complete. If the compare function is + * enabled, COCOn sets and conversion result data is transferred only if the compare + * condition is true. If both hardware averaging and compare functions are enabled, then + * COCOn sets only if the last of the selected number of conversions is complete and the + * compare condition is true. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * + * @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1. + */ +static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_HC_COUNT); + + /* If flag is set,return 1,otherwise, return 0. */ + return (((base->HS) & (1U << channelGroup)) >> channelGroup); +} + +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the software trigger should be used + * during calibration. + * + * @param base ADC peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration has failed. + */ +status_t ADC_DoAutoCalibration(ADC_Type *base); + +/*! + * @brief Set user defined offset. + * + * @param base ADC peripheral base address. + * @param config Pointer to "adc_offest_config_t" structure. + */ +void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config); + +/*! + * @brief Enables generating the DMA trigger when the conversion is complete. + * + * @param base ADC peripheral base address. + * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->GC |= ADC_GC_DMAEN_MASK; + } + else + { + base->GC &= ~ADC_GC_DMAEN_MASK; + } +} + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC peripheral base address. + * @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode. + */ +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) +static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= ADC_CFG_ADTRG_MASK; + } + else + { + base->CFG &= ~ADC_CFG_ADTRG_MASK; + } +} +#endif + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the + * result + * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate + * reference + * manual for more information. + * + * @param base ADC peripheral base address. + * @param Pointer to "adc_hardware_compare_config_t" structure. + * + */ +void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config); + +/*! + * @brief Configures the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The + * multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * @param base ADC peripheral base address. + * @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t". + */ +void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode); + +/*! + * @brief Gets the converter's status flags. + * + * @param base ADC peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t". + */ +static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) +{ + return base->GS; +} + +/*! + * @brief Clears the converter's status falgs. + * + * @param base ADC peripheral base address. + * @param mask Mask value for the cleared flags. See "adc_status_flags_t". + */ +void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_ADC_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.c new file mode 100644 index 0000000000..f17dcc3ba7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.c @@ -0,0 +1,365 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc_etc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_etc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(ADC_ETC_CLOCKS) +/*! + * @brief Get instance number for ADC_ETC module. + * + * @param base ADC_ETC peripheral base address + */ +static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC_ETC bases for each instance. */ +static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS; + +/*! @brief Pointers to ADC_ETC clocks for each instance. */ +static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base) +{ + uint32_t instance = 0U; + uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < adcetcArrayCount; instance++) + { + if (s_adcetcBases[instance] == base) + { + break; + } + } + + return instance; +} +#endif /* ADC_ETC_CLOCKS */ + +void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(ADC_ETC_CLOCKS) + /* Open clock gate. */ + CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]); +#endif /* ADC_ETC_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable software reset. */ + ADC_ETC_DoSoftwareReset(base, false); + + /* Set ADC_ETC_CTRL register. */ + tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) | + ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) | + ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask) +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode) +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + ; + if (config->enableTSCBypass) + { + tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK; + } + if (config->enableTSC0Trigger) + { + tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK; + } + if (config->enableTSC1Trigger) + { + tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK; + } + base->CTRL = tmp32; +} + +void ADC_ETC_Deinit(ADC_ETC_Type *base) +{ + /* Do software reset to clear all logical. */ + ADC_ETC_DoSoftwareReset(base, true); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(ADC_ETC_CLOCKS) + /* Close clock gate. */ + CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]); +#endif /* ADC_ETC_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) +{ + config->enableTSCBypass = true; + config->enableTSC0Trigger = false; + config->enableTSC1Trigger = false; +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal; +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + config->TSC0triggerPriority = 0U; + config->TSC1triggerPriority = 0U; + config->clockPreDivider = 0U; + config->XBARtriggerMask = 0U; +} + +void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config) +{ + assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); + assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup); + + uint32_t tmp32; + + /* Set ADC_ETC_TRGn_CTRL register. */ + tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) | + ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority); + if (config->enableSyncMode) + { + tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK; + } + if (config->enableSWTriggerMode) + { + tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK; + } + base->TRIG[triggerGroup].TRIGn_CTRL = tmp32; + + /* Set ADC_ETC_TRGn_COUNTER register. */ + tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) | + ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay); + base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32; +} + +void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, + uint32_t triggerGroup, + uint32_t chainGroup, + const adc_etc_trigger_chain_config_t *config) +{ + assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); + + uint32_t tmp; + uint32_t tmp32; + uint8_t mRemainder = chainGroup % 2U; + + /* Set ADC_ETC_TRIGn_CHAINm register. */ + tmp = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) | + ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) | + ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable); + if (config->enableB2BMode) + { + tmp |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK; + } + switch (chainGroup / 2U) + { + case 0U: /* Configurate trigger chain0 and chain 1. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0; + if (mRemainder == 0U) /* Chain 0. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK | + ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK); + tmp32 |= tmp; + } + else /* Chain 1. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK | + ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmp32; + break; + case 1U: /* Configurate trigger chain2 and chain 3. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2; + if (mRemainder == 0U) /* Chain 2. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK | + ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK); + tmp32 |= tmp; + } + else /* Chain 3. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK | + ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmp32; + break; + case 2U: /* Configurate trigger chain4 and chain 5. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4; + if (mRemainder == 0U) /* Chain 4. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK | + ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK); + tmp32 |= tmp; + } + else /* Chain 5. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK | + ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmp32; + break; + case 3U: /* Configurate trigger chain6 and chain 7. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6; + if (mRemainder == 0U) /* Chain 6. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK | + ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK); + tmp32 |= tmp; + } + else /* Chain 7. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK | + ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmp32; + break; + default: + break; + } +} + +uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex) +{ + uint32_t tmp32 = 0U; + + if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + return tmp32; +} + +void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask) +{ + if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */ + { + base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex); + } + if (0U != (mask & kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */ + { + base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex); + } + if (0U != (mask & kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */ + { + base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex); + } + if (0U != (mask & kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */ + { + base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex); + } +} + +uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup) +{ + assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT); + + uint32_t mADCResult; + uint8_t mRemainder = chainGroup % 2U; + + switch (chainGroup / 2U) + { + case 0U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT; + } + break; + case 1U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT; + } + break; + case 2U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT; + } + break; + case 3U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT; + } + break; + default: + return 0U; + } + return mADCResult; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.h new file mode 100644 index 0000000000..06cb5675b0 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.h @@ -0,0 +1,342 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC_ETC_H_ +#define _FSL_ADC_ETC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc_etc + * @{ + */ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! @brief ADC_ETC driver version */ +#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*! @brief The mask of status flags cleared by writing 1. */ +#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U + +/*! +* @brief ADC_ETC customized status flags mask. +*/ +enum _adc_etc_status_flag_mask +{ + kADC_ETC_Done0StatusFlagMask = 1U, + kADC_ETC_Done1StatusFlagMask = 2U, + kADC_ETC_Done2StatusFlagMask = 4U, + kADC_ETC_ErrorStatusFlagMask = 8U, +}; + +/*! +* @brief External triggers sources. +*/ +typedef enum _adc_etc_external_trigger_source +{ + /* External XBAR sources. Support HW or SW mode. */ + kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */ + kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */ + kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */ + kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */ + kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */ + kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */ + kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */ + kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */ + /* External TSC sources. Only support HW mode. */ + kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */ + kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */ +} adc_etc_external_trigger_source_t; + +/*! +* @brief Interrupt enable/disable mask. +*/ +typedef enum _adc_etc_interrupt_enable +{ + kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */ + kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */ + kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */ + kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */ +} adc_etc_interrupt_enable_t; + +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL +/*! +* @brief DMA mode selection. +*/ +typedef enum _adc_etc_dma_mode_selection +{ + kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */ + kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */ +} adc_etc_dma_mode_selection_t; +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + +/*! + * @brief ADC_ETC configuration. + */ +typedef struct _adc_etc_config +{ + bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly. + Otherwise TSC would trigger ADC through ADC_ETC. */ + bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */ + bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/ +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */ + uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */ + uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255. + Clock would be divided by (clockPreDivider+1). */ + uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to + trigger7:0x80 + For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is + enabled. */ +} adc_etc_config_t; + +/*! +* @brief ADC_ETC trigger chain configuration. +*/ +typedef struct _adc_etc_trigger_chain_config +{ + bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode, + wait until interval delay is reached. */ + uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */ + uint32_t ADCChannelSelect; /* Select ADC sample channel. */ + adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */ +} adc_etc_trigger_chain_config_t; + +/*! +* @brief ADC_ETC trigger configuration. +*/ +typedef struct _adc_etc_trigger_config +{ + bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source. + In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */ + bool enableSWTriggerMode; /* Enable the sofware trigger mode. */ + uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */ + uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */ + uint32_t sampleIntervalDelay; /* Set sampling interval delay. */ + uint32_t initialDelay; /* Set trigger initial delay. */ +} adc_etc_trigger_config_t; + +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! +* @brief Initialize the ADC_ETC module. +* +* @param base ADC_ETC peripheral base address. +* @param config Pointer to "adc_etc_config_t" structure. +*/ +void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config); + +/*! +* @brief De-Initialize the ADC_ETC module. +* +* @param base ADC_ETC peripheral base address. +*/ +void ADC_ETC_Deinit(ADC_ETC_Type *base); + +/*! +* @brief Gets an available pre-defined settings for the ADC_ETC's configuration. +* This function initializes the ADC_ETC's configuration structure with available settings. The default values are: +* @code +* config->enableTSCBypass = true; +* config->enableTSC0Trigger = false; +* config->enableTSC1Trigger = false; +* config->TSC0triggerPriority = 0U; +* config->TSC1triggerPriority = 0U; +* config->clockPreDivider = 0U; +* config->XBARtriggerMask = 0U; +* @endCode +* +* @param config Pointer to "adc_etc_config_t" structure. +*/ +void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config); + +/*! +* @brief Set the external XBAR trigger configuration. +* +* @param base ADC_ETC peripheral base address. +* @param triggerGroup Trigger group index. +* @param config Pointer to "adc_etc_trigger_config_t" structure. +*/ +void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config); + +/*! +* @brief Set the external XBAR trigger chain configuration. +* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be +* configurated. +* +* @param base ADC_ETC peripheral base address. +* @param triggerGroup Trigger group index. Available number is 0~7. +* @param chainGroup Trigger chain group index. Available number is 0~7. +* @param config Pointer to "adc_etc_trigger_chain_config_t" structure. +*/ +void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, + uint32_t triggerGroup, + uint32_t chainGroup, + const adc_etc_trigger_chain_config_t *config); + +/*! +* @brief Gets the interrupt status flags of external XBAR and TSC triggers. +* +* @param base ADC_ETC peripheral base address. +* @param sourceIndex trigger source index. +* +* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". +*/ +uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex); + +/*! +* @brief Clears the ADC_ETC's interrupt status falgs. +* +* @param base ADC_ETC peripheral base address. +* @param sourceIndex trigger source index. +* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". +*/ +void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, + adc_etc_external_trigger_source_t sourceIndex, + uint32_t mask); + +/*! +* @brief Enable the DMA corresponding to each trigger source. +* +* @param base ADC_ETC peripheral base address. +* @param triggerGroup Trigger group index. Available number is 0~7. +*/ +static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) +{ + /* Avoid clearing status flags at the same time. */ + base->DMA_CTRL = + (base->DMA_CTRL | (ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK; +} + +/*! +* @brief Disable the DMA corresponding to each trigger sources. +* +* @param base ADC_ETC peripheral base address. +* @param triggerGroup Trigger group index. Available number is 0~7. +*/ +static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) +{ + /* Avoid clearing status flags at the same time. */ + base->DMA_CTRL = + (base->DMA_CTRL & ~(ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK; +} + +/*! + * @brief Get the DMA request status falgs. Only external XBAR sources support DMA request. + * + * @param base ADC_ETC peripheral base address. + * @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to + * trigger7:0x80. + */ +static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base) +{ + return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT); +} + +/*! + * @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request. + * + * @param base ADC_ETC peripheral base address. + * @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to + * trigger7:0x80. + */ +static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask) +{ + base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT); +} + +/*! +* @brief When enable ,all logical will be reset. +* +* @param base ADC_ETC peripheral base address. +* @param enable Enable/Disable the software reset. +*/ +static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK; + } + else + { + base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK; + } +} + +/*! +* @brief Do software trigger corresponding to each XBAR trigger sources. +* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode, +* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources +* can only work in hardware trigger mode. +* +* @param base ADC_ETC peripheral base address. +* @param triggerGroup Trigger group index. Available number is 0~7. +*/ +static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup) +{ + assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); + + base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK; +} + +/*! +* @brief Get ADC conversion result from external XBAR sources. +* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would +* return Trigger0 source's chain1 conversion result. +* +* @param base ADC_ETC peripheral base address. +* @param triggerGroup Trigger group index. Available number is 0~7. +* @param chainGroup Trigger chain group index. Available number is 0~7. +* @return ADC conversion result value. +*/ +uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_ADC_ETC_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.c new file mode 100644 index 0000000000..91c091c75e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.c @@ -0,0 +1,66 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_aipstz.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aipstz" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig) +{ + uint32_t mask = ((uint32_t)master >> 8) - 1; + uint32_t shift = (uint32_t)master & 0xFF; + base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); +} + +void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl) +{ + volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16)); + uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1; + uint32_t shift = (uint32_t)peripheral & 0xFF; + + *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift); +} + + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.h new file mode 100644 index 0000000000..9d46f2e6a5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aipstz.h @@ -0,0 +1,155 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_AIPSTZ_H_ +#define _FSL_AIPSTZ_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup aipstz + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of AIPSTZ privilege configuration.*/ +typedef enum _aipstz_master_privilege_level { + kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */ + kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */ + kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */ + kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */ +} aipstz_master_privilege_level_t; + +/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/ +typedef enum _aipstz_master { + kAIPSTZ_Master0 = (0x400U | 28U), + kAIPSTZ_Master1 = (0x400U | 24U), + kAIPSTZ_Master2 = (0x400U | 20U), + kAIPSTZ_Master3 = (0x400U | 16U), + kAIPSTZ_Master5 = (0x400U | 8U) +} aipstz_master_t; + +/*! @brief List of AIPSTZ peripheral access control configuration.*/ +typedef enum _aipstz_peripheral_access_control { + kAIPSTZ_PeripheralAllowUntrustedMaster = 1U, + kAIPSTZ_PeripheralWriteProtected = (1U << 1), + kAIPSTZ_PeripheralRequireSupervisor = (1U << 2), + kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3) +} aipstz_peripheral_access_control_t; + +/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/ +typedef enum _aipstz_peripheral { + kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24) +} aipstz_peripheral_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Configure the privilege level for master. + * + * @param base AIPSTZ peripheral base pointer + * @param master Masters for AIPSTZ. + * @param privilegeConfig Configuration is ORed from @aipstz_master_privilege_level_t. + */ +void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig); + +/*! + * @brief Configure the access for peripheral. + * + * @param base AIPSTZ peripheral base pointer + * @param master Peripheral for AIPSTZ. + * @param accessControl Configuration is ORed from @aipstz_peripheral_access_control_t. + */ +void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_AIPSTZ_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.c new file mode 100644 index 0000000000..c20f13c928 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.c @@ -0,0 +1,157 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_aoi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aoi" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to aoi bases for each instance. */ +static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to aoi clocks for each instance. */ +static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for AOI module. + * + * @param base AOI peripheral base address + * + * @return The AOI instance + */ +static uint32_t AOI_GetInstance(AOI_Type *base); +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t AOI_GetInstance(AOI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++) + { + if (s_aoiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_aoiBases)); + + return instance; +} + +void AOI_Init(AOI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock gate from clock manager. */ + CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void AOI_Deinit(AOI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock gate from clock manager */ + CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config) +{ + assert(event < FSL_FEATURE_AOI_EVENT_COUNT); + assert(config != NULL); + + uint16_t value = 0; + /* Read BFCRT01 register at event index. */ + value = base->BFCRT[event].BFCRT01; + + config->PT0AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT); + config->PT0BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT); + config->PT0CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT); + config->PT0DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT); + + config->PT1AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT); + config->PT1BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT); + config->PT1CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT); + config->PT1DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT); + + /* Read BFCRT23 register at event index. */ + value = 0; + value = base->BFCRT[event].BFCRT23; + + config->PT2AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT); + config->PT2BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT); + config->PT2CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT); + config->PT2DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT); + + config->PT3AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT); + config->PT3BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT); + config->PT3CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT); + config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT); +} + +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) +{ + assert(eventConfig != NULL); + assert(event < FSL_FEATURE_AOI_EVENT_COUNT); + + uint16_t value = 0; + /* Calculate value to configure product term 0, 1 */ + value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) | + AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) | + AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) | + AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC); + /* Write value to register */ + base->BFCRT[event].BFCRT01 = value; + + /* Reset and calculate value to configure product term 2, 3 */ + value = 0; + value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) | + AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) | + AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) | + AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC); + /* Write value to register */ + base->BFCRT[event].BFCRT23 = value; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.h new file mode 100644 index 0000000000..47dbd9b9ca --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.h @@ -0,0 +1,213 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_AOI_H_ +#define _FSL_AOI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup aoi + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef AOI +#define AOI AOI0 /*!< AOI peripheral address */ +#endif + +/*! @name Driver version */ +/*@{*/ +#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! + * @brief AOI input configurations. + * + * The selection item represents the Boolean evaluations. +*/ +typedef enum _aoi_input_config +{ + kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ + kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ + kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ + kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ +} aoi_input_config_t; + +/*! + * @brief AOI event indexes, where an event is the collection of the four product + * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). + */ +typedef enum _aoi_event +{ + kAOI_Event0 = 0x0U, /*!< Event 0 index */ + kAOI_Event1 = 0x1U, /*!< Event 1 index */ + kAOI_Event2 = 0x2U, /*!< Event 2 index */ + kAOI_Event3 = 0x3U /*!< Event 3 index */ +} aoi_event_t; + +/*! + * @brief AOI event configuration structure + * + * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make + * whole event configuration. + */ +typedef struct _aoi_event_config +{ + aoi_input_config_t PT0AC; /*!< Product term 0 input A */ + aoi_input_config_t PT0BC; /*!< Product term 0 input B */ + aoi_input_config_t PT0CC; /*!< Product term 0 input C */ + aoi_input_config_t PT0DC; /*!< Product term 0 input D */ + aoi_input_config_t PT1AC; /*!< Product term 1 input A */ + aoi_input_config_t PT1BC; /*!< Product term 1 input B */ + aoi_input_config_t PT1CC; /*!< Product term 1 input C */ + aoi_input_config_t PT1DC; /*!< Product term 1 input D */ + aoi_input_config_t PT2AC; /*!< Product term 2 input A */ + aoi_input_config_t PT2BC; /*!< Product term 2 input B */ + aoi_input_config_t PT2CC; /*!< Product term 2 input C */ + aoi_input_config_t PT2DC; /*!< Product term 2 input D */ + aoi_input_config_t PT3AC; /*!< Product term 3 input A */ + aoi_input_config_t PT3BC; /*!< Product term 3 input B */ + aoi_input_config_t PT3CC; /*!< Product term 3 input C */ + aoi_input_config_t PT3DC; /*!< Product term 3 input D */ +} aoi_event_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name AOI Initialization + * @{ + */ + +/*! + * @brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * @param base AOI peripheral address. + */ +void AOI_Init(AOI_Type *base); + +/*! + * @brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * @param base AOI peripheral address. + */ +void AOI_Deinit(AOI_Type *base); + +/*@}*/ + +/*! + * @name AOI Get Set Operation + * @{ + */ + +/*! + * @brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Index of the event which will be set of type aoi_event_t. + * @param config Selected input configuration . + */ +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config); + +/*! + * @brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Event which will be configured of type aoi_event_t. + * @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*@}*/ + +/*!* @} */ + +#endif /* _FSL_AOI_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_bee.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_bee.c new file mode 100644 index 0000000000..15a804b0c5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_bee.c @@ -0,0 +1,244 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_bee.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.bee" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void aligned_memcpy(void *dst, const void *src, size_t size) +{ + register uint32_t *to32 = (uint32_t *)(uintptr_t)dst; + register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src; + + while (size >= sizeof(uint32_t)) + { + *to32 = *from32; + size -= sizeof(uint32_t); + to32++; + from32++; + } +} + +void BEE_Init(BEE_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Bee); +#endif + + base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK; +} + +void BEE_Deinit(BEE_Type *base) +{ + base->CTRL &= + ~(BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK | BEE_CTRL_KEY_VALID_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Bee); +#endif +} + +void BEE_GetDefaultConfig(bee_region_config_t *config) +{ + assert(config); + + config->mode = kBEE_AesEcbMode; + config->regionBot = 0U; + config->regionTop = 0U; + config->addrOffset = 0xF0000000U; + config->regionEn = kBEE_RegionDisabled; +} + +status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config) +{ + IOMUXC_GPR_Type *iomuxc = IOMUXC_GPR; + bool reenable = false; + + /* Wait until BEE is in idle state */ + while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) + { + } + + /* Disable BEE before region configuration in case it is enabled. */ + if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1) + { + BEE_Disable(base); + reenable = true; + } + + if (region == kBEE_Region0) + { + /* Region 0 config */ + iomuxc->GPR18 = config->regionBot; + iomuxc->GPR19 = config->regionTop; + + base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R0(config->mode); + base->ADDR_OFFSET0 = BEE_ADDR_OFFSET0_ADDR_OFFSET0(config->addrOffset); + } + + else if (region == kBEE_Region1) + { + /* Region 1 config */ + iomuxc->GPR20 = config->regionBot; + iomuxc->GPR21 = config->regionTop; + + base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R1(config->mode); + base->ADDR_OFFSET1 = BEE_ADDR_OFFSET1_ADDR_OFFSET0(config->addrOffset); + base->REGION1_BOT = BEE_REGION1_BOT_REGION1_BOT(config->regionBot); + base->REGION1_TOP = BEE_REGION1_TOP_REGION1_TOP(config->regionTop); + } + + else + { + return kStatus_InvalidArgument; + } + + /* Enable/disable region if desired */ + if (config->regionEn == kBEE_RegionEnabled) + { + iomuxc->GPR11 |= IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region); + } + else + { + iomuxc->GPR11 &= ~IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region); + } + + /* Reenable BEE if it was enabled before. */ + if (reenable) + { + BEE_Enable(base); + } + + return kStatus_Success; +} + +status_t BEE_SetRegionKey( + BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize) +{ + bool reenable = false; + + /* Key must be 32-bit aligned */ + if (((uintptr_t)key & 0x3u) || (keySize != 16)) + { + return kStatus_InvalidArgument; + } + + /* Wait until BEE is in idle state */ + while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) + { + } + + /* Disable BEE before region configuration in case it is enabled. */ + if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1) + { + BEE_Disable(base); + reenable = true; + } + + if (region == kBEE_Region0) + { + base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK; + + if (nonce) + { + if (nonceSize != 16) + { + return kStatus_InvalidArgument; + } + memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize); + } + } + + else if (region == kBEE_Region1) + { + base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK; + + if (nonce) + { + if (nonceSize != 16) + { + return kStatus_InvalidArgument; + } + memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize); + } + } + + else + { + return kStatus_InvalidArgument; + } + + /* Try to load key. If BEE key selection fuse is programmed to use OTMP key on this device, this operation should + * fail. */ + aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize); + if (memcmp((uint32_t *)&base->AES_KEY0_W0, key, keySize) != 0) + { + return kStatus_Fail; + } + + /* Reenable BEE if it was enabled before. */ + if (reenable) + { + BEE_Enable(base); + } + + return kStatus_Success; +} + +uint32_t BEE_GetStatusFlags(BEE_Type *base) +{ + return base->STATUS; +} + +void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask) +{ + /* w1c */ + base->STATUS |= mask; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_bee.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_bee.h new file mode 100644 index 0000000000..1eb6ae1ed6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_bee.h @@ -0,0 +1,228 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_BEE_H_ +#define _FSL_BEE_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief BEE driver version. Version 2.0.0. + * + * Current version: 2.0.0 + * + * Change log: + * - Version 2.0.0 + * - Initial version + */ +#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +typedef enum _bee_aes_mode +{ + kBEE_AesEcbMode = 0U, /*!< AES ECB Mode */ + kBEE_AesCtrMode = 1U /*!< AES CTR Mode */ +} bee_aes_mode_t; + +typedef enum _bee_region +{ + kBEE_Region0 = 0U, /*!< BEE region 0 */ + kBEE_Region1 = 1U /*!< BEE region 1 */ +} bee_region_t; + +typedef enum _bee_region_enable +{ + kBEE_RegionDisabled = 0U, /*!< BEE region disabled */ + kBEE_RegionEnabled = 1U /*!< BEE region enabled */ +} bee_region_enable_t; + +typedef enum _bee_status_flags +{ + kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */ + kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */ + kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */ + kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */ + kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */ + kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */ + kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */ +} bee_status_flags_t; + +/*! @brief BEE region configuration structure. */ +typedef struct _bee_region_config +{ + bee_aes_mode_t mode; /*!< AES mode used for encryption/decryption */ + uint32_t regionBot; /*!< Region bottom address */ + uint32_t regionTop; /*!< Region top address */ + uint32_t addrOffset; /*!< Region address offset */ + bee_region_enable_t regionEn; /*!< Region enable/disable */ +} bee_region_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Resets BEE module to factory default values. + * + * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared. + * + * @param base BEE peripheral address. + */ +void BEE_Init(BEE_Type *base); + +/*! + * @brief Resets BEE module, clears keys for both regions and disables clock to the BEE. + * + * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both + * regions are cleared. + * + * @param base BEE peripheral address. + */ +void BEE_Deinit(BEE_Type *base); + +/*! + * @brief Enables BEE decryption. + * + * This function enables decryption using BEE. + * + * @param base BEE peripheral address. + */ +static inline void BEE_Enable(BEE_Type *base) +{ + base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK; +} + +/*! + * @brief Disables BEE decryption. + * + * This function disables decryption using BEE. + * + * @param base BEE peripheral address. + */ +static inline void BEE_Disable(BEE_Type *base) +{ + base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK; +} + +/*! + * @brief Loads default values to the BEE region configuration structure. + * + * Loads default values to the BEE region configuration structure. The default values are as follows: + * @code + * config->mode = kBEE_AesCbcMode; + * config->regionBot = 0U; + * config->regionTop = 0U; + * config->addrOffset = 0xF0000000U; + * config->regionEn = kBEE_RegionDisabled; + * @endcode + * + * @param config Configuration structure for BEE region. + */ +void BEE_GetDefaultConfig(bee_region_config_t *config); + +/*! + * @brief Sets BEE region configuration. + * + * This function sets BEE region settings accorging to given configuration structure. + * + * @param base BEE peripheral address. + * @param region Selection of the BEE region to be configured. + * @param config Configuration structure for BEE region. + */ +status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config); + +/*! + * @brief Loads the AES key and nonce for selected region into BEE key registers. + * + * This function loads given AES key and nonce(only AES CTR mode) to BEE register for the given region. + * + * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers. + * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2. + * + * @param base BEE peripheral address. + * @param region Selection of the BEE region to be configured. + * @param key AES key. + * @param keySize Size of AES key. + * @param nonce AES nonce. + * @param nonceSize Size of AES nonce. + */ +status_t BEE_SetRegionKey( + BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize); + +/*! + * @brief Gets the BEE status flags. + * + * This function returns status of BEE peripheral. + * + * @param base BEE peripheral address. + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::bee_status_flags_t + */ +uint32_t BEE_GetStatusFlags(BEE_Type *base); + +/*! + * @brief Clears the BEE status flags. + * + * @param base BEE peripheral base address. + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::bee_status_flags_t + */ +void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask); + +/*! + * @brief Computes offset to be set for specifed memory location. + * + * This function calculates offset that must be set for BEE region to access physical memory location. + * + * @param addressMemory Address of physical memory location. + */ +static inline uint32_t BEE_GetOffset(uint32_t addressMemory) +{ + return (addressMemory >> 16); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_BEE_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.c new file mode 100644 index 0000000000..595fefe733 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.c @@ -0,0 +1,470 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7" +#endif + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU +#define L2CACHE_8WAYS_MASK 0xFFU +#define L2CACHE_16WAYS_MASK 0xFFFFU +#define L2CACHE_SMALLWAYS_NUM 8U +#define L2CACHE_1KBCOVERTOB 1024U +#define L2CACHE_SAMLLWAYS_SIZE 16U +#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! + * @brief Set for all ways and waiting for the operation finished. + * This is provided for all the background operations. + * + * @param auxCtlReg The auxiliary control register. + * @param regAddr The register address to be operated. + */ +static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr); + +/*! + * @brief Invalidates the Level 2 cache line by physical address. + * This function invalidates a cache line by physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address); + +/*! + * @brief Cleans the Level 2 cache line based on the physical address. + * This function cleans a cache line based on a physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_CleanLineByAddr(uint32_t address); + +/*! + * @brief Cleans and invalidates the Level 2 cache line based on the physical address. + * This function cleans and invalidates a cache line based on a physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address); + +/*! + * @brief Gets the number of the Level 2 cache and the way size. + * This function cleans and invalidates a cache line based on a physcial address. + * + * @param num_ways The number of the cache way. + * @param size_way The way size. + */ +static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way); +/******************************************************************************* + * Code + ******************************************************************************/ +static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr) +{ + uint16_t mask = L2CACHE_8WAYS_MASK; + uint32_t timeout = L2CACHE_OPERATION_TIMEOUT; + + /* Check the ways used at first. */ + if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) + { + mask = L2CACHE_16WAYS_MASK; + } + + /* Set the opeartion for all ways/entries of the cache. */ + *(uint32_t *)regAddr = mask; + /* Waiting for until the operation is complete. */ + while ((*(volatile uint32_t *)regAddr & mask) && timeout) + { + __ASM("nop"); + timeout--; + } +} + +static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Invalidate the cache line by physical address. */ + L2CACHEC->REG7_INV_PA = address; + + return address; +} + +static uint32_t L2CACHE_CleanLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Invalidate the cache line by physical address. */ + L2CACHEC->REG7_CLEAN_PA = address; + + return address; +} + +static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Clean and invalidate the cache line by physical address. */ + L2CACHEC->REG7_CLEAN_INV_PA = address; + + return address; +} + +static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way) +{ + assert(num_ways); + assert(size_way); + + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; + + *num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM; + if (!size) + { + /* 0 internally mapped to the same size as 1 - 16KB.*/ + size += 1; + } + *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB; +} + +void L2CACHE_Init(l2cache_config_t *config) +{ + assert (config); + + uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */ + uint8_t count; + uint32_t auxReg = 0; + + /*The aux register must be configured when the cachec is disabled + * So disable first if the cache controller is enabled. + */ + if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK) + { + L2CACHE_Disable(); + } + + /* Unlock all entries. */ + if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) + { + waysNum = 0xFFFFU; + } + + for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++) + { + L2CACHE_LockdownByWayEnable(count, waysNum, false); + } + + /* Set the ways and way-size etc. */ + auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) | + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | + L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | + L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) | + L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | + L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc); + L2CACHEC->REG1_AUX_CONTROL = auxReg; + + /* Set the tag/data ram latency. */ + if (config->lateConfig) + { + uint32_t data = 0; + /* Tag latency. */ + data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)| + L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)| + L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)| + L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + L2CACHEC->REG1_TAG_RAM_CONTROL = data; + /* Data latency. */ + data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)| + L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)| + L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)| + L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + L2CACHEC->REG1_DATA_RAM_CONTROL = data; + } +} + +void L2CACHE_GetDefaultConfig(l2cache_config_t *config) +{ + assert(config); + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; + + /* Get the default value */ + config->wayNum = (l2cache_way_num_t)number; + config->waySize = (l2cache_way_size)size; + config->repacePolicy = kL2CACHE_Roundrobin; + config->lateConfig = NULL; + config->istrPrefetchEnable = false; + config->dataPrefetchEnable = false; + config->nsLockdownEnable = false; + config->writeAlloc = kL2CACHE_UseAwcache; +} + +void L2CACHE_Enable(void) +{ + /* Invalidate first. */ + L2CACHE_Invalidate(); + /* Enable the level 2 cache controller. */ + L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK; +} + +void L2CACHE_Disable(void) +{ + /* First CleanInvalidate all enties in the cache. */ + L2CACHE_CleanInvalidate(); + /* Disable the level 2 cache controller. */ + L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK; + /* DSB - data sync barrier.*/ + __DSB(); +} + +void L2CACHE_Invalidate(void) +{ + /* Invalidate all entries in cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +void L2CACHE_Clean(void) +{ + /* Clean all entries of the cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +void L2CACHE_CleanInvalidate(void) +{ + /* Clean all entries of the cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + + /* Invalidate addresses in the range. */ + while (address < endAddr) + { + address = L2CACHE_InvalidateLineByAddr(address); + /* Update the size. */ + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t num_ways = 0; + uint32_t size_way = 0; + uint32_t endAddr = address + size_byte; + + /* Get the number and size of the cache way. */ + L2CACHE_GetWayNumSize(&num_ways, &size_way); + + /* Check if the clean size is over the cache size. */ + if ((endAddr - address) > num_ways * size_way) + { + L2CACHE_Clean(); + return; + } + + /* Clean addresses in the range. */ + while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) + { + /* Clean the address in the range. */ + address = L2CACHE_CleanLineByAddr(address); + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t num_ways = 0; + uint32_t size_way = 0; + uint32_t endAddr = address + size_byte; + + /* Get the number and size of the cache way. */ + L2CACHE_GetWayNumSize(&num_ways, &size_way); + + /* Check if the clean size is over the cache size. */ + if ((endAddr - address) > num_ways * size_way) + { + L2CACHE_CleanInvalidate(); + return; + } + + /* Clean addresses in the range. */ + while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) + { + /* Clean the address in the range. */ + address = L2CACHE_CleanInvalidateLineByAddr(address); + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) +{ + uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM; + + assert(mask < (1U << num_ways)); + assert(masterId < L2CACHE_LOCKDOWN_REGNUM); + + uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; + uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; + + if (enable) + { + /* Data lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; + /* Instruction lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; + } + else + { + /* Data lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; + /* Instruction lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; + } +} +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); + int32_t size = size_byte + address - addr; + uint32_t linesize = 32U; + + __DSB(); + while (size > 0) + { + SCB->ICIMVAU = addr; + addr += linesize; + size -= linesize; + } + __DSB(); + __ISB(); +#endif +} + +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_InvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_InvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_CleanByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +} + +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_CleanInvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.h new file mode 100644 index 0000000000..a041ea2a34 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.h @@ -0,0 +1,494 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.1. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT +#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 +#endif +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT + +/*! @brief Number of level 2 cache controller ways. */ +typedef enum _l2cache_way_num +{ + kL2CACHE_8ways = 0, /*!< 8 ways. */ +#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY + kL2CACHE_16ways /*!< 16 ways. */ +#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ +} l2cache_way_num_t; + +/*! @brief Level 2 cache controller way size. */ +typedef enum _l2cache_way_size +{ + kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ + kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ + kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ + kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ + kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ + kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ +} l2cache_way_size; + +/*! @brief Level 2 cache controller replacement policy. */ +typedef enum _l2cache_replacement +{ + kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ + kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ +} l2cache_replacement_t; + +/*! @brief Level 2 cache controller force write allocate options. */ +typedef enum _l2cache_writealloc +{ + kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ + kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ + kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ +} l2cache_writealloc_t; + +/*! @brief Level 2 cache controller tag/data ram latency. */ +typedef enum _l2cache_latency +{ + kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ + kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ + kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ + kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ + kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ + kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ + kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ + kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ +} l2cache_latency_t; + +/*! @brief Level 2 cache controller tag/data ram latency configure structure. */ +typedef struct _l2cache_latency_config +{ + l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ + l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ + l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ + l2cache_latency_t dataWriteLate; /*!< Data write latency. */ + l2cache_latency_t dataReadLate; /*!< Data Read latency. */ + l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ +} L2cache_latency_config_t; + +/*! @brief Level 2 cache controller configure structure. */ +typedef struct _l2cache_config +{ + /* ------------------------ l2 cachec basic settings ---------------------------- */ + l2cache_way_num_t wayNum; /*!< The number of ways. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */ + /* ------------------------ tag/data ram latency settings ----------------------- */ + L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ + /* ------------------------ Prefetch enable settings ---------------------------- */ + bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ + bool dataPrefetchEnable; /*!< Data prefetch enable. */ + /* ------------------------ Non-secure access settings -------------------------- */ + bool nsLockdownEnable; /*!< None-secure lockdown enable. */ + /* ------------------------ other settings -------------------------------------- */ + l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ +} l2cache_config_t; +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Control for cortex-m7 L1 cache + *@{ + */ + +/*! + * @brief Enables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_EnableICache(void) +{ + SCB_EnableICache(); +} + +/*! + * @brief Disables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_DisableICache(void) +{ + SCB_DisableICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_InvalidateICache(void) +{ + SCB_InvalidateICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_EnableDCache(void) +{ + SCB_EnableDCache(); +} + +/*! + * @brief Disables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_DisableDCache(void) +{ + SCB_DisableDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_InvalidateDCache(void) +{ + SCB_InvalidateDCache(); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanDCache(void) +{ + SCB_CleanDCache(); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanInvalidateDCache(void) +{ + SCB_CleanInvalidateDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size); +} +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +/*! + * @name Control for L2 pl310 cache + *@{ + */ + +/*! + * @brief Initializes the level 2 cache controller module. + * + * @param config Pointer to configuration structure. See "l2cache_config_t". + */ +void L2CACHE_Init(l2cache_config_t *config); + +/*! + * @brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * @code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * @endcode + * @param config Pointer to the configuration structure. + */ +void L2CACHE_GetDefaultConfig(l2cache_config_t *config); + +/*! + * @brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Enable(void); + +/*! + * @brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Disable(void); + +/*! + * @brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ +void L2CACHE_Invalidate(void); + +/*! + * @brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ +void L2CACHE_Clean(void); + +/*! + * @brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ +void L2CACHE_CleanInvalidate(void); + +/*! + * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * @param masterId The master id, range from 0 ~ 7. + * @param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * @param enable True enable the lockdown, false to disable the lockdown. + */ +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); + +/*@}*/ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +/*! + * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) + * Mainly used for many drivers for easy cache operation. + *@{ + */ + +/*! + * @brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned and invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*@}*/ + + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.c new file mode 100644 index 0000000000..fba76beac2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.c @@ -0,0 +1,917 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + else + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; +} + +void CLOCK_InitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +void CLOCK_DeinitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + /* Periph_clk ---> AHB Clock */ + case kCLOCK_AhbClk: + /* Periph_clk ---> AHB Clock */ + freq = + CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + break; + + case kCLOCK_SemcClk: + /* SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + break; + + case kCLOCK_IpgClk: + /* Periph_clk ---> AHB Clock ---> IPG Clock */ + freq = + CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; +} + +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; +} + +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; +} + +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; +} + +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; +} + +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + } + + if (config->enableClkOutput25M) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; +} + +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + uint64_t freqTmp; + + const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); + break; + case kCLOCK_PllSys: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = + ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = + ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllVideo: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = + ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1): + freq >>= 1U; + break; + + default: + break; + } + break; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & + ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); +} + +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & + ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); +} + +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} + +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.h new file mode 100644 index 0000000000..52fd227e2e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.h @@ -0,0 +1,1466 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could contol the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.2. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \ + ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U)->reg) & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief Clock ip name array for LCDIF PIXEL. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ + } \ + , {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + + kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xDU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xEU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0xFU, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */ + + kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x15U, /*!< Video PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + + /* CCM CCGR3 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE( + CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE( + CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE( + CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE( + CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE( + CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = + CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE( + CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_CanDiv = CCM_TUPLE( + CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_TraceDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE( + CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE( + CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE( + CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE( + CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ + + kCLOCK_CsiDiv = + CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ +} clock_div_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 6); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.c new file mode 100644 index 0000000000..98039cd6f9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.c @@ -0,0 +1,295 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmp.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cmp" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for CMP module. + * + * @param base CMP peripheral base address + */ +static uint32_t CMP_GetInstance(CMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CMP bases for each instance. */ +static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to CMP clocks for each instance. */ +static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t CMP_GetInstance(CMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++) + { + if (s_cmpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_cmpBases)); + + return instance; +} + +void CMP_Init(CMP_Type *base, const cmp_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure. */ + CMP_Enable(base, false); /* Disable the CMP module during configuring. */ + /* CMPx_CR1. */ + tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); + if (config->enableHighSpeed) + { + tmp8 |= CMP_CR1_PMODE_MASK; + } + if (config->enableInvertOutput) + { + tmp8 |= CMP_CR1_INV_MASK; + } + if (config->useUnfilteredOutput) + { + tmp8 |= CMP_CR1_COS_MASK; + } + if (config->enablePinOut) + { + tmp8 |= CMP_CR1_OPE_MASK; + } +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + if (config->enableTriggerMode) + { + tmp8 |= CMP_CR1_TRIGM_MASK; + } + else + { + tmp8 &= ~CMP_CR1_TRIGM_MASK; + } +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + base->CR1 = tmp8; + + /* CMPx_CR0. */ + tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; + tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); + base->CR0 = tmp8; + + CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ +} + +void CMP_Deinit(CMP_Type *base) +{ + /* Disable the CMP module. */ + CMP_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + assert(NULL != config); + + config->enableCmp = true; /* Enable the CMP module after initialization. */ + config->hysteresisMode = kCMP_HysteresisLevel0; + config->enableHighSpeed = false; + config->enableInvertOutput = false; + config->useUnfilteredOutput = false; + config->enablePinOut = false; +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} + +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) +{ + uint8_t tmp8 = base->MUXCR; + + tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); + tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); + base->MUXCR = tmp8; +} + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +void CMP_EnableDMA(CMP_Type *base, bool enable) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (enable) + { + tmp8 |= CMP_SCR_DMAEN_MASK; + } + else + { + tmp8 &= ~CMP_SCR_DMAEN_MASK; + } + base->SCR = tmp8; +} +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + /* Choose the clock source for sampling. */ + if (config->enableSample) + { + base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ + } + else + { + base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ + } +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + /* Set the filter count. */ + tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; + tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); + base->CR0 = tmp8; + /* Set the filter period. It is used as the divider to bus clock. */ + base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); +} + +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) +{ + uint8_t tmp8 = 0U; + + if (NULL == config) + { + /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ + base->DACCR = 0U; + return; + } + /* CMPx_DACCR. */ + tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ + if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) + { + tmp8 |= CMP_DACCR_VRSEL_MASK; + } + tmp8 |= CMP_DACCR_VOSEL(config->DACValue); + + base->DACCR = tmp8; +} + +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +uint32_t CMP_GetStatusFlags(CMP_Type *base) +{ + uint32_t ret32 = 0U; + + if (0U != (CMP_SCR_CFR_MASK & base->SCR)) + { + ret32 |= kCMP_OutputRisingEventFlag; + } + if (0U != (CMP_SCR_CFF_MASK & base->SCR)) + { + ret32 |= kCMP_OutputFallingEventFlag; + } + if (0U != (CMP_SCR_COUT_MASK & base->SCR)) + { + ret32 |= kCMP_OutputAssertEventFlag; + } + return ret32; +} + +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFR_MASK; + } + if (0U != (kCMP_OutputFallingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFF_MASK; + } + base->SCR = tmp8; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.h new file mode 100644 index 0000000000..e228413f0c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.h @@ -0,0 +1,347 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CMP_H_ +#define _FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMP driver version 2.0.0. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! +* @brief Interrupt enable/disable mask. +*/ +enum _cmp_interrupt_enable +{ + kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ + kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ +}; + +/*! + * @brief Status flags' mask. + */ +enum _cmp_status_flags +{ + kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ + kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ +}; + +/*! + * @brief CMP Hysteresis mode. + */ +typedef enum _cmp_hysteresis_mode +{ + kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ + kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ + kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ + kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ +} cmp_hysteresis_mode_t; + +/*! + * @brief CMP Voltage Reference source. + */ +typedef enum _cmp_reference_voltage_source +{ + kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */ + kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */ +} cmp_reference_voltage_source_t; + +/*! + * @brief Configures the comparator. + */ +typedef struct _cmp_config +{ + bool enableCmp; /*!< Enable the CMP module. */ + cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ + bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */ + bool enableInvertOutput; /*!< Enable the inverted comparator output. */ + bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */ + bool enablePinOut; /*!< The comparator output is available on the associated pin. */ +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool enableTriggerMode; /*!< Enable the trigger mode. */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} cmp_config_t; + +/*! + * @brief Configures the filter. + */ +typedef struct _cmp_filter_config +{ +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */ +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/ + uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */ +} cmp_filter_config_t; + +/*! + * @brief Configures the internal DAC. + */ +typedef struct _cmp_dac_config +{ + cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ +} cmp_dac_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are as follows. + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for + * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config); + +/*! + * @brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are as follows. + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * @param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base); + +/*! + * @brief Enables/disables the CMP module. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the module. + */ +static inline void CMP_Enable(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_EN_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_EN_MASK; + } +} + +/*! +* @brief Initializes the CMP user configuration structure. +* +* This function initializes the user configuration structure to these default values. +* @code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* @endcode +* @param config Pointer to the configuration structure. +*/ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/*! + * @brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set the same way in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * @param base CMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP + * if the DMA is disabled. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable); +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE +/*! + * @brief Enables/disables the window mode. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_WE_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_WE_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ + +#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE +/*! + * @brief Enables/disables the pass through mode. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->MUXCR |= CMP_MUXCR_PSTM_MASK; + } + else + { + base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ + +/*! + * @brief Configures the filter. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); + +/*! + * @brief Configures the internal DAC. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. "NULL" disables the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); + +/*! + * @brief Enables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Results + * @{ + */ + +/*! + * @brief Gets the status flags. + * + * @param base CMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base); + +/*! + * @brief Clears the status flags. + * + * @param base CMP peripheral base address. + * @param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_CMP_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_common.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_common.c new file mode 100644 index 0000000000..903faf52b6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_common.c @@ -0,0 +1,192 @@ +/* +* The Clear BSD License +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP +* All rights reserved. +* +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted (subject to the limitations in the disclaimer below) provided +* that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned adress to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#ifndef QN908XC_SERIES +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + +#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) + { + SYSCON->STARTERP1 = 1u << intNumber; + } +#else + { + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + } +#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ +#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) + { + SYSCON->STARTERP1 &= ~(1u << intNumber); + } +#else + { + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; + } +#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ +} +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#endif /* QN908XC_SERIES */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_common.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_common.h new file mode 100644 index 0000000000..a53dbc2713 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_common.h @@ -0,0 +1,576 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.0. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__ARMCC_VERSION)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __align(alignbytes) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif + } + + /*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.c new file mode 100644 index 0000000000..df993d29dc --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.c @@ -0,0 +1,694 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_csi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.csi" +#endif + + +/* Two frame buffer loaded to CSI register at most. */ +#define CSI_MAX_ACTIVE_FRAME_NUM 2 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base CSI peripheral base address + * + * @return The CSI module instance + */ +static uint32_t CSI_GetInstance(CSI_Type *base); + +/*! + * @brief Get the delta value of two index in queue. + * + * @param startIdx Start index. + * @param endIdx End index. + * + * @return The delta between startIdx and endIdx in queue. + */ +static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx); + +/*! + * @brief Increase a index value in queue. + * + * This function increases the index value in the queue, if the index is out of + * the queue range, it is reset to 0. + * + * @param idx The index value to increase. + * + * @return The index value after increase. + */ +static uint32_t CSI_TransferIncreaseQueueIdx(uint32_t idx); + +/*! + * @brief Get the empty frame buffer count in queue. + * + * @param base CSI peripheral base address + * @param handle Pointer to CSI driver handle. + * + * @return Number of the empty frame buffer count in queue. + */ +static uint32_t CSI_TransferGetEmptyBufferCount(CSI_Type *base, csi_handle_t *handle); + +/*! + * @brief Load one empty frame buffer in queue to CSI module. + * + * Load one empty frame in queue to CSI module, this function could only be called + * when there is empty frame buffer in queue. + * + * @param base CSI peripheral base address + * @param handle Pointer to CSI driver handle. + */ +static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle); + +/* Typedef for interrupt handler. */ +typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CSI bases for each instance. */ +static CSI_Type *const s_csiBases[] = CSI_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to CSI clocks for each CSI submodule. */ +static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* Array for the CSI driver handle. */ +static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)]; + +/* Array of CSI IRQ number. */ +static const IRQn_Type s_csiIRQ[] = CSI_IRQS; + +/* CSI ISR for transactional APIs. */ +static csi_isr_t s_csiIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CSI_GetInstance(CSI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_csiBases); instance++) + { + if (s_csiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_csiBases)); + + return instance; +} + +static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx) +{ + if (endIdx >= startIdx) + { + return endIdx - startIdx; + } + else + { + return startIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - endIdx; + } +} + +static uint32_t CSI_TransferIncreaseQueueIdx(uint32_t idx) +{ + uint32_t ret; + + /* + * Here not use the method: + * ret = (idx+1) % CSI_DRIVER_ACTUAL_QUEUE_SIZE; + * + * Because the mod function might be slow. + */ + + ret = idx + 1; + + if (ret >= CSI_DRIVER_ACTUAL_QUEUE_SIZE) + { + ret = 0; + } + + return ret; +} + +static uint32_t CSI_TransferGetEmptyBufferCount(CSI_Type *base, csi_handle_t *handle) +{ + return CSI_TransferGetQueueDelta(handle->queueDrvReadIdx, handle->queueUserWriteIdx); +} + +static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle) +{ + /* Load the frame buffer address to CSI register. */ + CSI_SetRxBufferAddr(base, handle->nextBufferIdx, handle->frameBufferQueue[handle->queueDrvReadIdx]); + + handle->queueDrvReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueDrvReadIdx); + handle->activeBufferNum++; + + /* There are two CSI buffers, so could use XOR to get the next index. */ + handle->nextBufferIdx ^= 1U; +} + +status_t CSI_Init(CSI_Type *base, const csi_config_t *config) +{ + assert(config); + uint32_t reg; + uint32_t imgWidth_Bytes; + + imgWidth_Bytes = config->width * config->bytesPerPixel; + + /* The image width and frame buffer pitch should be multiple of 8-bytes. */ + if ((imgWidth_Bytes & 0x07) | ((uint32_t)config->linePitch_Bytes & 0x07)) + { + return kStatus_InvalidArgument; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = CSI_GetInstance(base); + CLOCK_EnableClock(s_csiClocks[instance]); +#endif + + CSI_Reset(base); + + /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */ + reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK; + + if (config->useExtVsync) + { + reg |= CSI_CSICR1_EXT_VSYNC_MASK; + } + + base->CSICR1 = reg; + + /* + * Generally, CSIIMAG_PARA[IMAGE_WIDTH] indicates how many data bus cycles per line. + * One special case is when receiving 24-bit pixels through 8-bit data bus, and + * CSICR3[ZERO_PACK_EN] is enabled, in this case, the CSIIMAG_PARA[IMAGE_WIDTH] + * should be set to the pixel number per line. + * + * Currently the CSI driver only support 8-bit data bus, so generally the + * CSIIMAG_PARA[IMAGE_WIDTH] is bytes number per line. When the CSICR3[ZERO_PACK_EN] + * is enabled, CSIIMAG_PARA[IMAGE_WIDTH] is pixel number per line. + * + * NOTE: The CSIIMAG_PARA[IMAGE_WIDTH] setting code should be updated if the + * driver is upgraded to support other data bus width. + */ + if (4U == config->bytesPerPixel) + { + /* Enable zero pack. */ + base->CSICR3 |= CSI_CSICR3_ZERO_PACK_EN_MASK; + /* Image parameter. */ + base->CSIIMAG_PARA = ((uint32_t)(config->width) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) | + ((uint32_t)(config->height) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT); + } + else + { + /* Image parameter. */ + base->CSIIMAG_PARA = ((uint32_t)(imgWidth_Bytes) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) | + ((uint32_t)(config->height) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT); + } + + /* The CSI frame buffer bus is 8-byte width. */ + base->CSIFBUF_PARA = (uint32_t)((config->linePitch_Bytes - imgWidth_Bytes) / 8U) + << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT; + + /* Enable auto ECC. */ + base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK; + + /* + * For better performance. + * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte, + * choose the best burst size based on bytes per line. + */ + if (!(imgWidth_Bytes % (8 * 16))) + { + base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U); + base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); + } + else if (!(imgWidth_Bytes % (8 * 8))) + { + base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U); + base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); + } + else + { + base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U); + base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); + } + + CSI_ReflashFifoDma(base, kCSI_RxFifo); + + return kStatus_Success; +} + +void CSI_Deinit(CSI_Type *base) +{ + /* Disable transfer first. */ + CSI_Stop(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = CSI_GetInstance(base); + CLOCK_DisableClock(s_csiClocks[instance]); +#endif +} + +void CSI_Reset(CSI_Type *base) +{ + uint32_t csisr; + + /* Disable transfer first. */ + CSI_Stop(base); + + /* Disable DMA request. */ + base->CSICR3 = 0U; + + /* Reset the fame count. */ + base->CSICR3 |= CSI_CSICR3_FRMCNT_RST_MASK; + while (base->CSICR3 & CSI_CSICR3_FRMCNT_RST_MASK) + { + } + + /* Clear the RX FIFO. */ + CSI_ClearFifo(base, kCSI_AllFifo); + + /* Reflash DMA. */ + CSI_ReflashFifoDma(base, kCSI_AllFifo); + + /* Clear the status. */ + csisr = base->CSISR; + base->CSISR = csisr; + + /* Set the control registers to default value. */ + base->CSICR1 = CSI_CSICR1_HSYNC_POL_MASK | CSI_CSICR1_EXT_VSYNC_MASK; + base->CSICR2 = 0U; + base->CSICR3 = 0U; +#if defined(CSI_CSICR18_CSI_LCDIF_BUFFER_LINES) + base->CSICR18 = CSI_CSICR18_AHB_HPROT(0x0DU) | CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(0x02U); +#else + base->CSICR18 = CSI_CSICR18_AHB_HPROT(0x0DU); +#endif + base->CSIFBUF_PARA = 0U; + base->CSIIMAG_PARA = 0U; +} + +void CSI_GetDefaultConfig(csi_config_t *config) +{ + assert(config); + + config->width = 320U; + config->height = 240U; + config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge; + config->bytesPerPixel = 2U; + config->linePitch_Bytes = 320U * 2U; + config->workMode = kCSI_GatedClockMode; + config->dataBus = kCSI_DataBus8Bit; + config->useExtVsync = true; +} + +void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr) +{ + if (index) + { + base->CSIDMASA_FB2 = addr; + } + else + { + base->CSIDMASA_FB1 = addr; + } +} + +void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo) +{ + uint32_t cr1; + uint32_t mask = 0U; + + /* The FIFO could only be cleared when CSICR1[FCC] = 0, so first clear the FCC. */ + cr1 = base->CSICR1; + base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK); + + if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo) + { + mask |= CSI_CSICR1_CLR_RXFIFO_MASK; + } + + if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo) + { + mask |= CSI_CSICR1_CLR_STATFIFO_MASK; + } + + base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK) | mask; + + /* Wait clear completed. */ + while (base->CSICR1 & mask) + { + } + + /* Recover the FCC. */ + base->CSICR1 = cr1; +} + +void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo) +{ + uint32_t cr3 = 0U; + + if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo) + { + cr3 |= CSI_CSICR3_DMA_REFLASH_RFF_MASK; + } + + if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo) + { + cr3 |= CSI_CSICR3_DMA_REFLASH_SFF_MASK; + } + + base->CSICR3 |= cr3; + + /* Wait clear completed. */ + while (base->CSICR3 & cr3) + { + } +} + +void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable) +{ + uint32_t cr3 = 0U; + + if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo) + { + cr3 |= CSI_CSICR3_DMA_REQ_EN_RFF_MASK; + } + + if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo) + { + cr3 |= CSI_CSICR3_DMA_REQ_EN_SFF_MASK; + } + + if (enable) + { + base->CSICR3 |= cr3; + } + else + { + base->CSICR3 &= ~cr3; + } +} + +void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask) +{ + base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK); + base->CSICR3 |= (mask & CSI_CSICR3_INT_EN_MASK); + base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U); +} + +void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask) +{ + base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK); + base->CSICR3 &= ~(mask & CSI_CSICR3_INT_EN_MASK); + base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U); +} + +status_t CSI_TransferCreateHandle(CSI_Type *base, + csi_handle_t *handle, + csi_transfer_callback_t callback, + void *userData) +{ + assert(handle); + uint32_t instance; + + memset(handle, 0, sizeof(*handle)); + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Get instance from peripheral base address. */ + instance = CSI_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_csiHandle[instance] = handle; + + s_csiIsr = CSI_TransferHandleIRQ; + + /* Enable interrupt. */ + EnableIRQ(s_csiIRQ[instance]); + + return kStatus_Success; +} + +status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle) +{ + assert(handle); + + uint32_t emptyBufferCount; + + emptyBufferCount = CSI_TransferGetEmptyBufferCount(base, handle); + + if (emptyBufferCount < 2U) + { + return kStatus_CSI_NoEmptyBuffer; + } + + handle->nextBufferIdx = 0U; + handle->activeBufferNum = 0U; + + /* Write to memory from second completed frame. */ + base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(2); + + /* Load the frame buffer to CSI register, there are at least two empty buffers. */ + CSI_TransferLoadBufferToDevice(base, handle); + CSI_TransferLoadBufferToDevice(base, handle); + + /* After reflash DMA, the CSI saves frame to frame buffer 0. */ + CSI_ReflashFifoDma(base, kCSI_RxFifo); + + handle->transferStarted = true; + handle->transferOnGoing = true; + + CSI_EnableInterrupts(base, kCSI_RxBuffer1DmaDoneInterruptEnable | kCSI_RxBuffer0DmaDoneInterruptEnable); + + CSI_Start(base); + + return kStatus_Success; +} + +status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle) +{ + assert(handle); + + CSI_Stop(base); + CSI_DisableInterrupts(base, kCSI_RxBuffer1DmaDoneInterruptEnable | kCSI_RxBuffer0DmaDoneInterruptEnable); + + handle->transferStarted = false; + handle->transferOnGoing = false; + + /* Stoped, reset the state flags. */ + handle->queueDrvReadIdx = handle->queueDrvWriteIdx; + handle->activeBufferNum = 0U; + + return kStatus_Success; +} + +status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer) +{ + uint32_t csicr1; + + if (CSI_DRIVER_QUEUE_SIZE == CSI_TransferGetQueueDelta(handle->queueUserReadIdx, handle->queueUserWriteIdx)) + { + return kStatus_CSI_QueueFull; + } + + /* Disable the interrupt to protect the index information in handle. */ + csicr1 = base->CSICR1; + + base->CSICR1 = (csicr1 & ~(CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)); + + /* Save the empty frame buffer address to queue. */ + handle->frameBufferQueue[handle->queueUserWriteIdx] = frameBuffer; + handle->queueUserWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx); + + base->CSICR1 = csicr1; + + if (handle->transferStarted) + { + /* + * If user has started transfer using @ref CSI_TransferStart, and the CSI is + * stopped due to no empty frame buffer in queue, then start the CSI. + */ + if ((!handle->transferOnGoing) && (CSI_TransferGetEmptyBufferCount(base, handle) >= 2U)) + { + handle->transferOnGoing = true; + handle->nextBufferIdx = 0U; + + /* Load the frame buffers to CSI module. */ + CSI_TransferLoadBufferToDevice(base, handle); + CSI_TransferLoadBufferToDevice(base, handle); + CSI_ReflashFifoDma(base, kCSI_RxFifo); + CSI_Start(base); + } + } + + return kStatus_Success; +} + +status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer) +{ + uint32_t csicr1; + + /* No full frame buffer. */ + if (handle->queueUserReadIdx == handle->queueDrvWriteIdx) + { + return kStatus_CSI_NoFullBuffer; + } + + /* Disable the interrupt to protect the index information in handle. */ + csicr1 = base->CSICR1; + + base->CSICR1 = (csicr1 & ~(CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)); + + *frameBuffer = handle->frameBufferQueue[handle->queueUserReadIdx]; + + handle->queueUserReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserReadIdx); + + base->CSICR1 = csicr1; + + return kStatus_Success; +} + +void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle) +{ + uint32_t queueDrvWriteIdx; + uint32_t csisr = base->CSISR; + + /* Clear the error flags. */ + base->CSISR = csisr; + + /* + * If both frame buffer 0 and frame buffer 1 flags assert, driver does not + * know which frame buffer ready just now, so reset the CSI transfer to + * start from frame buffer 0. + */ + if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) == + (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) + { + CSI_Stop(base); + + /* Reset the active buffers. */ + if (1 <= handle->activeBufferNum) + { + queueDrvWriteIdx = handle->queueDrvWriteIdx; + + base->CSIDMASA_FB1 = handle->frameBufferQueue[queueDrvWriteIdx]; + + if (2U == handle->activeBufferNum) + { + queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx); + base->CSIDMASA_FB2 = handle->frameBufferQueue[queueDrvWriteIdx]; + handle->nextBufferIdx = 0U; + } + else + { + handle->nextBufferIdx = 1U; + } + } + CSI_ReflashFifoDma(base, kCSI_RxFifo); + CSI_Start(base); + } + else if (csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) + { + handle->queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueDrvWriteIdx); + + handle->activeBufferNum--; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData); + } + + /* No frame buffer to save incoming data, then stop the CSI module. */ + if (!(handle->activeBufferNum)) + { + CSI_Stop(base); + handle->transferOnGoing = false; + } + else + { + if (CSI_TransferGetEmptyBufferCount(base, handle)) + { + CSI_TransferLoadBufferToDevice(base, handle); + } + } + } + else + { + } +} + +#if defined(CSI) +void CSI_DriverIRQHandler(void) +{ + s_csiIsr(CSI, s_csiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CSI0) +void CSI0_DriverIRQHandler(void) +{ + s_csiIsr(CSI, s_csiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.h new file mode 100644 index 0000000000..96230c8318 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.h @@ -0,0 +1,562 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CSI_H_ +#define _FSL_CSI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup csi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Size of the frame buffer queue used in CSI transactional function. */ +#ifndef CSI_DRIVER_QUEUE_SIZE +#define CSI_DRIVER_QUEUE_SIZE 4U +#endif + +/* + * There is one empty room in queue, used to distinguish whether the queue + * is full or empty. When header equals tail, the queue is empty; when header + * equals tail + 1, the queue is full. + */ +#define CSI_DRIVER_ACTUAL_QUEUE_SIZE (CSI_DRIVER_QUEUE_SIZE + 1U) + +/* + * The interrupt enable bits are in registers CSICR1[16:31], CSICR3[0:7], + * and CSICR18[2:9]. So merge them into an uint32_t value, place CSICR18 control + * bits to [8:15]. + */ +#define CSI_CSICR1_INT_EN_MASK 0xFFFF0000U +#define CSI_CSICR3_INT_EN_MASK 0x000000FFU +#define CSI_CSICR18_INT_EN_MASK 0x0000FF00U + +#if ((~CSI_CSICR1_INT_EN_MASK) & \ + (CSI_CSICR1_EOF_INT_EN_MASK | CSI_CSICR1_COF_INT_EN_MASK | CSI_CSICR1_SF_OR_INTEN_MASK | \ + CSI_CSICR1_RF_OR_INTEN_MASK | CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK | CSI_CSICR1_STATFF_INTEN_MASK | \ + CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK | CSI_CSICR1_RXFF_INTEN_MASK | \ + CSI_CSICR1_SOF_INTEN_MASK)) +#error CSI_CSICR1_INT_EN_MASK could not cover all interrupt bits in CSICR1. +#endif + +#if ((~CSI_CSICR3_INT_EN_MASK) & (CSI_CSICR3_ECC_INT_EN_MASK | CSI_CSICR3_HRESP_ERR_EN_MASK)) +#error CSI_CSICR3_INT_EN_MASK could not cover all interrupt bits in CSICR3. +#endif + +#if ((~CSI_CSICR18_INT_EN_MASK) & ((CSI_CSICR18_FIELD0_DONE_IE_MASK | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) << 6U)) +#error CSI_CSICR18_INT_EN_MASK could not cover all interrupt bits in CSICR18. +#endif + +/*! @brief Error codes for the CSI driver. */ +enum _csi_status +{ + kStatus_CSI_NoEmptyBuffer = MAKE_STATUS(kStatusGroup_CSI, 0), /*!< No empty frame buffer in queue to load to CSI. */ + kStatus_CSI_NoFullBuffer = MAKE_STATUS(kStatusGroup_CSI, 1), /*!< No full frame buffer in queue to read out. */ + kStatus_CSI_QueueFull = MAKE_STATUS(kStatusGroup_CSI, 2), /*!< Queue is full, no room to save new empty buffer. */ + kStatus_CSI_FrameDone = MAKE_STATUS(kStatusGroup_CSI, 3), /*!< New frame received and saved to queue. */ +}; + +/*! + * @brief CSI work mode. + * + * The CCIR656 interlace mode is not supported currently. + */ +typedef enum _csi_work_mode +{ + kCSI_GatedClockMode = CSI_CSICR1_GCLK_MODE(1U), /*!< HSYNC, VSYNC, and PIXCLK signals are used. */ + kCSI_NonGatedClockMode = 0U, /*!< VSYNC, and PIXCLK signals are used. */ + kCSI_CCIR656ProgressiveMode = CSI_CSICR1_CCIR_EN(1U), /*!< CCIR656 progressive mode. */ +} csi_work_mode_t; + +/*! + * @brief CSI data bus witdh. + * + * Currently only support 8-bit width. + */ +typedef enum _csi_data_bus +{ + kCSI_DataBus8Bit, /*!< 8-bit data bus. */ +} csi_data_bus_t; + +/*! @brief CSI signal polarity. */ +enum _csi_polarity_flags +{ + kCSI_HsyncActiveLow = 0U, /*!< HSYNC is active low. */ + kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */ + kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */ + kCSI_DataLatchOnFallingEdge = 0U, /*!< Pixel data latched at falling edge of pixel clock. */ + kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */ + kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */ +}; + +/*! @brief Configuration to initialize the CSI module. */ +typedef struct _csi_config +{ + uint16_t width; /*!< Pixels of the input frame. */ + uint16_t height; /*!< Lines of the input frame. */ + uint32_t polarityFlags; /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */ + uint8_t bytesPerPixel; /*!< Bytes per pixel, valid values are: + - 2: Used for RGB565, YUV422, and so on. + - 3: Used for packed RGB888, packed YUV444, and so on. + - 4: Used for XRGB8888, XYUV444, and so on. + */ + uint16_t linePitch_Bytes; /*!< Frame buffer line pitch, must be 8-byte aligned. */ + csi_work_mode_t workMode; /*!< CSI work mode. */ + csi_data_bus_t dataBus; /*!< Data bus width. */ + bool useExtVsync; /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false + to use internal VSYNC signal decoded from SOF. */ +} csi_config_t; + +/*! @brief The CSI FIFO, used for FIFO operation. */ +typedef enum _csi_fifo +{ + kCSI_RxFifo = (1U << 0U), /*!< RXFIFO. */ + kCSI_StatFifo = (1U << 1U), /*!< STAT FIFO. */ + kCSI_AllFifo = 0x01 | 0x02, /*!< Both RXFIFO and STAT FIFO. */ +} csi_fifo_t; + +/*! @brief CSI feature interrupt source. */ +enum _csi_interrupt_enable +{ + kCSI_EndOfFrameInterruptEnable = CSI_CSICR1_EOF_INT_EN_MASK, /*!< End of frame interrupt enable. */ + kCSI_ChangeOfFieldInterruptEnable = CSI_CSICR1_COF_INT_EN_MASK, /*!< Change of field interrupt enable. */ + kCSI_StatFifoOverrunInterruptEnable = CSI_CSICR1_SF_OR_INTEN_MASK, /*!< STAT FIFO overrun interrupt enable. */ + kCSI_RxFifoOverrunInterruptEnable = CSI_CSICR1_RF_OR_INTEN_MASK, /*!< RXFIFO overrun interrupt enable. */ + kCSI_StatFifoDmaDoneInterruptEnable = + CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK, /*!< STAT FIFO DMA done interrupt enable. */ + kCSI_StatFifoFullInterruptEnable = CSI_CSICR1_STATFF_INTEN_MASK, /*!< STAT FIFO full interrupt enable. */ + kCSI_RxBuffer1DmaDoneInterruptEnable = + CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 1 DMA transfer done. */ + kCSI_RxBuffer0DmaDoneInterruptEnable = + CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 0 DMA transfer done. */ + kCSI_RxFifoFullInterruptEnable = CSI_CSICR1_RXFF_INTEN_MASK, /*!< RXFIFO full interrupt enable. */ + kCSI_StartOfFrameInterruptEnable = CSI_CSICR1_SOF_INTEN_MASK, /*!< Start of frame (SOF) interrupt enable. */ + + kCSI_EccErrorInterruptEnable = CSI_CSICR3_ECC_INT_EN_MASK, /*!< ECC error detection interrupt enable. */ + kCSI_AhbResErrorInterruptEnable = CSI_CSICR3_HRESP_ERR_EN_MASK, /*!< AHB response Error interrupt enable. */ + + kCSI_BaseAddrChangeErrorInterruptEnable = CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK << 6U, /*!< The DMA output buffer base address + changes before DMA completed. */ + kCSI_Field0DoneInterruptEnable = CSI_CSICR18_FIELD0_DONE_IE_MASK << 6U, /*!< Field 0 done interrupt enable. */ + kCSI_Field1DoneInterruptEnable = CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK << 6U, /*!< Field 1 done interrupt enable. */ +}; + +/*! + * @brief CSI status flags. + * + * The following status register flags can be cleared: + * - kCSI_EccErrorFlag + * - kCSI_AhbResErrorFlag + * - kCSI_ChangeOfFieldFlag + * - kCSI_StartOfFrameFlag + * - kCSI_EndOfFrameFlag + * - kCSI_RxBuffer1DmaDoneFlag + * - kCSI_RxBuffer0DmaDoneFlag + * - kCSI_StatFifoDmaDoneFlag + * - kCSI_StatFifoOverrunFlag + * - kCSI_RxFifoOverrunFlag + * - kCSI_Field0DoneFlag + * - kCSI_Field1DoneFlag + * - kCSI_BaseAddrChangeErrorFlag + */ +enum _csi_flags +{ + kCSI_RxFifoDataReadyFlag = CSI_CSISR_DRDY_MASK, /*!< RXFIFO data ready. */ + kCSI_EccErrorFlag = CSI_CSISR_ECC_INT_MASK, /*!< ECC error detected. */ + kCSI_AhbResErrorFlag = CSI_CSISR_HRESP_ERR_INT_MASK, /*!< Hresponse (AHB bus response) Error. */ + kCSI_ChangeOfFieldFlag = CSI_CSISR_COF_INT_MASK, /*!< Change of field. */ + kCSI_Field0PresentFlag = CSI_CSISR_F1_INT_MASK, /*!< Field 0 present in CCIR mode. */ + kCSI_Field1PresentFlag = CSI_CSISR_F2_INT_MASK, /*!< Field 1 present in CCIR mode. */ + kCSI_StartOfFrameFlag = CSI_CSISR_SOF_INT_MASK, /*!< Start of frame (SOF) detected. */ + kCSI_EndOfFrameFlag = CSI_CSISR_EOF_INT_MASK, /*!< End of frame (EOF) detected. */ + kCSI_RxFifoFullFlag = CSI_CSISR_RxFF_INT_MASK, /*!< RXFIFO full (Number of data reaches trigger level). */ + kCSI_RxBuffer1DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB2_MASK, /*!< RX frame buffer 1 DMA transfer done. */ + kCSI_RxBuffer0DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB1_MASK, /*!< RX frame buffer 0 DMA transfer done. */ + kCSI_StatFifoFullFlag = CSI_CSISR_STATFF_INT_MASK, /*!< STAT FIFO full (Reach trigger level). */ + kCSI_StatFifoDmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_SFF_MASK, /*!< STAT FIFO DMA transfer done. */ + kCSI_StatFifoOverrunFlag = CSI_CSISR_SF_OR_INT_MASK, /*!< STAT FIFO overrun. */ + kCSI_RxFifoOverrunFlag = CSI_CSISR_RF_OR_INT_MASK, /*!< RXFIFO overrun. */ + kCSI_Field0DoneFlag = CSI_CSISR_DMA_FIELD0_DONE_MASK, /*!< Field 0 transfer done. */ + kCSI_Field1DoneFlag = CSI_CSISR_DMA_FIELD1_DONE_MASK, /*!< Field 1 transfer done. */ + kCSI_BaseAddrChangeErrorFlag = CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK, /*!< The DMA output buffer base address + changes before DMA completed. */ +}; + +/* Forward declaration of the handle typedef. */ +typedef struct _csi_handle csi_handle_t; + +/*! + * @brief CSI transfer callback function. + * + * When a new frame is received and saved to the frame buffer queue, the callback + * is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer. + */ +typedef void (*csi_transfer_callback_t)(CSI_Type *base, csi_handle_t *handle, status_t status, void *userData); + +/*! + * @brief CSI handle structure. + * + * Please see the user guide for the details of the CSI driver queue mechanism. + */ +struct _csi_handle +{ + uint32_t frameBufferQueue[CSI_DRIVER_ACTUAL_QUEUE_SIZE]; /*!< Frame buffer queue. */ + + volatile uint8_t queueUserReadIdx; /*!< Application gets full-filled frame buffer from this index. */ + volatile uint8_t queueUserWriteIdx; /*!< Application puts empty frame buffer to this index. */ + volatile uint8_t queueDrvReadIdx; /*!< Driver gets empty frame buffer from this index. */ + volatile uint8_t queueDrvWriteIdx; /*!< Driver puts the full-filled frame buffer to this index. */ + + volatile uint8_t activeBufferNum; /*!< How many frame buffers are in progres currently. */ + volatile uint8_t nextBufferIdx; /*!< The CSI frame buffer index to use for next frame. */ + + volatile bool transferStarted; /*!< User has called @ref CSI_TransferStart to start frame receiving. */ + volatile bool transferOnGoing; /*!< CSI is working and receiving incoming frames. */ + + csi_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< CSI callback function parameter.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize the CSI. + * + * This function enables the CSI peripheral clock, and resets the CSI registers. + * + * @param base CSI peripheral base address. + * @param config Pointer to the configuration structure. + * + * @retval kStatus_Success Initialize successfully. + * @retval kStatus_InvalidArgument Initialize failed because of invalid argument. + */ +status_t CSI_Init(CSI_Type *base, const csi_config_t *config); + +/*! + * @brief De-initialize the CSI. + * + * This function disables the CSI peripheral clock. + * + * @param base CSI peripheral base address. + */ +void CSI_Deinit(CSI_Type *base); + +/*! + * @brief Reset the CSI. + * + * This function resets the CSI peripheral registers to default status. + * + * @param base CSI peripheral base address. + */ +void CSI_Reset(CSI_Type *base); + +/*! + * @brief Get the default configuration for to initialize the CSI. + * + * The default configuration value is: + * + * @code + config->width = 320U; + config->height = 240U; + config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge; + config->bytesPerPixel = 2U; + config->linePitch_Bytes = 320U * 2U; + config->workMode = kCSI_GatedClockMode; + config->dataBus = kCSI_DataBus8Bit; + config->useExtVsync = true; + @endcode + * + * @param config Pointer to the CSI configuration. + */ +void CSI_GetDefaultConfig(csi_config_t *config); + +/* @} */ + +/*! + * @name Module operation + * @{ + */ + +/*! + * @brief Clear the CSI FIFO. + * + * This function clears the CSI FIFO. + * + * @param base CSI peripheral base address. + * @param fifo The FIFO to clear. + */ +void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo); + +/*! + * @brief Reflash the CSI FIFO DMA. + * + * This function reflashes the CSI FIFO DMA. + * + * For RXFIFO, there are two frame buffers. When the CSI module started, it saves + * the frames to frame buffer 0 then frame buffer 1, the two buffers will be + * written by turns. After reflash DMA using this function, the CSI is reset to + * save frame to buffer 0. + * + * @param base CSI peripheral base address. + * @param fifo The FIFO DMA to reflash. + */ +void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo); + +/*! + * @brief Enable or disable the CSI FIFO DMA request. + * + * @param base CSI peripheral base address. + * @param fifo The FIFO DMA reques to enable or disable. + * @param enable True to enable, false to disable. + */ +void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable); + +/*! + * @brief Start to receive data. + * + * @param base CSI peripheral base address. + */ +static inline void CSI_Start(CSI_Type *base) +{ + CSI_EnableFifoDmaRequest(base, kCSI_RxFifo, true); + base->CSICR18 |= CSI_CSICR18_CSI_ENABLE_MASK; +} + +/*! + * @brief Stop to receiving data. + * + * @param base CSI peripheral base address. + */ +static inline void CSI_Stop(CSI_Type *base) +{ + base->CSICR18 &= ~CSI_CSICR18_CSI_ENABLE_MASK; + CSI_EnableFifoDmaRequest(base, kCSI_RxFifo, false); +} + +/*! + * @brief Set the RX frame buffer address. + * + * @param base CSI peripheral base address. + * @param index Buffer index. + * @param addr Frame buffer address to set. + */ +void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr); +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables CSI interrupt requests. + * + * @param base CSI peripheral base address. + * @param mask The interrupts to enable, pass in as OR'ed value of @ref _csi_interrupt_enable. + */ +void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask); + +/*! + * @brief Disable CSI interrupt requests. + * + * @param base CSI peripheral base address. + * @param mask The interrupts to disable, pass in as OR'ed value of @ref _csi_interrupt_enable. + */ +void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the CSI status flags. + * + * @param base CSI peripheral base address. + * @return status flag, it is OR'ed value of @ref _csi_flags. + */ +static inline uint32_t CSI_GetStatusFlags(CSI_Type *base) +{ + return base->CSISR; +} + +/*! + * @brief Clears the CSI status flag. + * + * The flags to clear are passed in as OR'ed value of @ref _csi_flags. The following + * flags are cleared automatically by hardware: + * + * - @ref kCSI_RxFifoFullFlag, + * - @ref kCSI_StatFifoFullFlag, + * - @ref kCSI_Field0PresentFlag, + * - @ref kCSI_Field1PresentFlag, + * - @ref kCSI_RxFifoDataReadyFlag, + * + * @param base CSI peripheral base address. + * @param statusMask The status flags mask, OR'ed value of @ref _csi_flags. + */ +static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask) +{ + base->CSISR = statusMask; +} +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the CSI handle. + * + * This function initializes CSI handle, it should be called before any other + * CSI transactional functions. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the handle structure. + * @param callback Callback function for CSI transfer. + * @param userData Callback function parameter. + * + * @retval kStatus_Success Handle created successfully. + */ +status_t CSI_TransferCreateHandle(CSI_Type *base, + csi_handle_t *handle, + csi_transfer_callback_t callback, + void *userData); + +/*! + * @brief Start the transfer using transactional functions. + * + * When the empty frame buffers have been submit to CSI driver using function + * @ref CSI_TransferSubmitEmptyBuffer, user could call this function to start + * the transfer. The incoming frame will be saved to the empty frame buffer, + * and user could be optionally notified through callback function. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the handle structure. + * + * @retval kStatus_Success Started successfully. + * @retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue. + */ +status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle); + +/*! + * @brief Stop the transfer using transactional functions. + * + * The driver does not clean the full frame buffers in queue. In other words, after + * calling this function, user still could get the full frame buffers in queue + * using function @ref CSI_TransferGetFullBuffer. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the handle structure. + * + * @retval kStatus_Success Stoped successfully. + */ +status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle); + +/*! + * @brief Submit empty frame buffer to queue. + * + * This function could be called before @ref CSI_TransferStart or after @ref + * CSI_TransferStart. If there is no room in queue to store the empty frame + * buffer, this function returns error. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the handle structure. + * @param frameBuffer Empty frame buffer to submit. + * + * @retval kStatus_Success Started successfully. + * @retval kStatus_CSI_QueueFull Could not submit because there is no room in queue. + */ +status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer); + +/*! + * @brief Get one full frame buffer from queue. + * + * After the transfer started using function @ref CSI_TransferStart, the incoming + * frames will be saved to the empty frame buffers in queue. This function gets + * the full-filled frame buffer from the queue. If there is no full frame buffer + * in queue, this function returns error. + * + * @param base CSI peripheral base address. + * @param handle Pointer to the handle structure. + * @param frameBuffer Full frame buffer. + * + * @retval kStatus_Success Started successfully. + * @retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue. + */ +status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer); + +/*! + * @brief CSI IRQ handle function. + * + * This function handles the CSI IRQ request to work with CSI driver transactional + * APIs. + * + * @param base CSI peripheral base address. + * @param handle CSI handle pointer. + */ +void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CSI_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.c new file mode 100644 index 0000000000..5e0e3a97b4 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.c @@ -0,0 +1,351 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dcdc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcdc_1" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DCDC module. + * + * @param base DCDC peripheral base address + */ +static uint32_t DCDC_GetInstance(DCDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DCDC bases for each instance. */ +static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to DCDC clocks for each instance. */ +static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DCDC_GetInstance(DCDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++) + { + if (s_dcdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dcdcBases)); + + return instance; +} + +void DCDC_Init(DCDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void DCDC_Deinit(DCDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) +{ + uint32_t tmp32; + + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & + ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | + DCDC_REG0_PWD_OSC_INT_MASK); + switch (clockSource) + { + case kDCDC_ClockInternalOsc: + tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; + break; + case kDCDC_ClockExternalOsc: + /* Choose the external clock and disable the internal clock. */ + tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK; + break; + case kDCDC_ClockAutoSwitch: + /* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */ + tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; + break; + default: + break; + } + base->REG0 = tmp32; +} + +void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) +{ + assert(NULL != config); + + config->enableXtalokDetection = false; + config->powerDownOverVoltageDetection = true; + config->powerDownLowVlotageDetection = false; + config->powerDownOverCurrentDetection = true; + config->powerDownPeakCurrentDetection = true; + config->powerDownZeroCrossDetection = true; + config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; +} + +void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & + ~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK | DCDC_REG0_PWD_CMP_BATT_DET_MASK | + DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | DCDC_REG0_PWD_ZCD_MASK | + DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK); + + tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) | + DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold); + if (false == config->enableXtalokDetection) + { + tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; + } + if (config->powerDownOverVoltageDetection) + { + tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK; + } + if (config->powerDownLowVlotageDetection) + { + tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK; + } + if (config->powerDownOverCurrentDetection) + { + tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK; + } + if (config->powerDownPeakCurrentDetection) + { + tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK; + } + if (config->powerDownZeroCrossDetection) + { + tmp32 |= DCDC_REG0_PWD_ZCD_MASK; + } + base->REG0 = tmp32; +} + +void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) +{ + assert(NULL != config); + + config->enableOverloadDetection = true; + config->enableAdjustHystereticValue = false; + config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; +} + +void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & + ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | + DCDC_REG0_LP_OVERLOAD_THRSH_MASK); + tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) | + DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold); + if (config->enableOverloadDetection) + { + tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK; + } + if (config->enableAdjustHystereticValue) + { + tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK; + } + base->REG0 = tmp32; +} + +uint32_t DCDC_GetstatusFlags(DCDC_Type *base) +{ + uint32_t tmp32 = 0U; + + if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + tmp32 |= kDCDC_LockedOKStatus; + } + + return tmp32; +} + +void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK; + } + else + { + base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK; + } +} + +void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) +{ + assert(NULL != config); + + config->enableCommonHysteresis = false; + config->enableCommonThresholdDetection = false; + config->enableInvertHysteresisSign = false; + config->enableRCThresholdDetection = false; + config->enableRCScaleCircuit = 0U; + config->complementFeedForwardStep = 0U; + config->controlParameterMagnitude = 2U; + config->integralProportionalRatio = 2U; +} + +void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Configure the DCDC_REG1 register. */ + tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK); + if (config->enableCommonHysteresis) + { + tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK; + } + if (config->enableCommonThresholdDetection) + { + tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK; + } + base->REG1 = tmp32; + + /* configure the DCDC_REG2 register. */ + tmp32 = base->REG2 & + ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK | + DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | DCDC_REG2_LOOPCTRL_DC_R_MASK | + DCDC_REG2_LOOPCTRL_DC_C_MASK); + tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) | + DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) | + DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) | + DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit); + if (config->enableInvertHysteresisSign) + { + tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK; + } + if (config->enableRCThresholdDetection) + { + tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK; + } + base->REG2 = tmp32; +} + +void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK; + if (config->enableUseHalfFreqForContinuous) + { + tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK; + } + base->REG3 = tmp32; +} + +void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby) +{ + uint32_t tmp32; + + /* Unlock the step for the output. */ + base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK; + + /* Configure the DCDC_REG3 register. */ + tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK); + + tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun); + base->REG3 = tmp32; + + /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage settling to new + * target value, DCDC_STS_DC_OK will be asserted. */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + } +} + +void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Configure the DCDC_REG1 register. */ + tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK); + tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint); + if (config->enableLoadResistor) + { + tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK; + } + base->REG1 = tmp32; +} + +void DCDC_BootIntoDCM(DCDC_Type *base) +{ + base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) | + DCDC_REG2_DCM_SET_CTRL_MASK; +} + +void DCDC_BootIntoCCM(DCDC_Type *base) +{ + base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U); +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.h new file mode 100644 index 0000000000..647d3a8589 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.h @@ -0,0 +1,490 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DCDC_H__ +#define __FSL_DCDC_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup dcdc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief DCDC driver version. */ +#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*! + * @brief DCDC status flags. + */ +enum _dcdc_status_flags_t +{ + kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */ +}; + +/*! +* @brief The current bias of low power comparator. +*/ +typedef enum _dcdc_comparator_current_bias +{ + kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */ + kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */ + kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */ + kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */ +} dcdc_comparator_current_bias_t; + +/*! +* @brief The threshold of over current detection. +*/ +typedef enum _dcdc_over_current_threshold +{ + kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */ + kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */ + kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */ + kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */ +} dcdc_over_current_threshold_t; + +/*! +* @brief The threshold if peak current detection. +*/ +typedef enum _dcdc_peak_current_threshold +{ + kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */ +} dcdc_peak_current_threshold_t; + +/*! +* @brief The period of counting the charging times in power save mode. +*/ +typedef enum _dcdc_count_charging_time_period +{ + kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */ + kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */ +} dcdc_count_charging_time_period_t; + +/*! +* @brief The threshold of the counting number of charging times +*/ +typedef enum _dcdc_count_charging_time_threshold +{ + kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */ + kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */ + kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */ + kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */ +} dcdc_count_charging_time_threshold_t; + +/*! + * @brief Oscillator clock option. + */ +typedef enum _dcdc_clock_source +{ + kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */ + kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */ + kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */ +} dcdc_clock_source_t; + +/*! +* @brief Configuration for DCDC detection. +*/ +typedef struct _dcdc_detection_config +{ + bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */ + bool powerDownOverVoltageDetection; /*!< Power down over-voltage detection comparator. */ + bool powerDownLowVlotageDetection; /*!< Power down low-voltage detection comparator. */ + bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */ + bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */ + bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor + mode. */ + dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */ + dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */ +} dcdc_detection_config_t; + +/*! +* @brief Configuration for the loop control. +*/ +typedef struct _dcdc_loop_control_config +{ + bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators. + This feature will improve transient supply ripple and efficiency. */ + bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */ + bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */ + bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */ + uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond + faster under transient load conditions. */ + uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in + the switching DC-DC converter. Each time this field makes a transition from + 0x0, the loop filter of the DC-DC converter is stepped once by a value + proportional to the change. This can be used to force a certain control loop + behavior, such as improving response under known heavy load transients. */ + uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the + switching DC-DC converter control loop. */ + uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional + control parameter in the switching DC-DC converter, and can be used to + optimize efficiency and loop response. */ +} dcdc_loop_control_config_t; +/*! +* @brief Configuration for DCDC low power. +*/ +typedef struct _dcdc_low_power_config +{ + bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the + overloading threshold (typical value is 50 mA), DCDC will switch to the run mode + automatically. */ + bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */ + dcdc_count_charging_time_period_t + countChargingTimePeriod; /*!< The period of counting the charging times in power save mode. */ + dcdc_count_charging_time_threshold_t + countChargingTimeThreshold; /*!< the threshold of the counting number of charging times during + the period that lp_overload_freq_sel sets in power save mode. */ +} dcdc_low_power_config_t; + +/*! +* @brief Configuration for DCDC internal regulator. +*/ +typedef struct _dcdc_internal_regulator_config +{ + bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is + connected as default "true", and need set to "false" to disconnect the load + resistor. */ + uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */ +} dcdc_internal_regulator_config_t; + +/*! + * @brief Configuration for min power setting. + */ +typedef struct _dcdc_min_power_config +{ + bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */ +} dcdc_min_power_config_t; +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! +* @brief Enable the access to DCDC registers. +* +* @param base DCDC peripheral base address. +*/ +void DCDC_Init(DCDC_Type *base); + +/*! +* @brief Disable the access to DCDC registers. +* +* @param base DCDC peripheral base address. +*/ +void DCDC_Deinit(DCDC_Type *base); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! +* @brief Get DCDC status flags. +* +* @param base peripheral base address. +* @return Mask of asserted status flags. See to "_dcdc_status_flags_t". +*/ +uint32_t DCDC_GetstatusFlags(DCDC_Type *base); + +/* @} */ + +/*! + * @name Misc control. + * @{ + */ + +/*! + * @brief Enable the output range comparator. + * + * The output range comparator is disabled by default. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; + } + else + { + base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; + } +} + +/*! +* @brief Configure the DCDC clock source. +* +* @param base DCDC peripheral base address. +* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". +*/ +void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource); + +/*! +* @brief Get the default setting for detection configuration. +* +* The default configuration are set according to responding registers' setting when powered on. +* They are: +* @code +* config->enableXtalokDetection = false; +* config->powerDownOverVoltageDetection = true; +* config->powerDownLowVlotageDetection = false; +* config->powerDownOverCurrentDetection = true; +* config->powerDownPeakCurrentDetection = true; +* config->powerDownZeroCrossDetection = true; +* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; +* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; +* @endcode +* +* @param config Pointer to configuration structure. See to "dcdc_detection_config_t" +*/ +void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config); + +/*! +* @breif Configure the DCDC detection. +* +* @param base DCDC peripheral base address. +* @param config Pointer to configuration structure. See to "dcdc_detection_config_t" +*/ +void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config); + +/*! +* @brief Get the default setting for low power configuration. +* +* The default configuration are set according to responding registers' setting when powered on. +* They are: +* @code +* config->enableOverloadDetection = true; +* config->enableAdjustHystereticValue = false; +* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; +* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; +* @endcode +* +* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t" +*/ +void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config); + +/*! +* @brief Configure the DCDC low power. +* +* @param base DCDC peripheral base address. +* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t". +*/ +void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config); + +/*! +* @brief Reset current alert signal. Alert signal is generate by peak current detection. +* +* @param base DCDC peripheral base address. +* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal. +*/ +void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable); + +/*! +* @brief Set the bangap trim value to trim bandgap voltage. +* +* @param base DCDC peripheral base address. +* @param TrimValue The bangap trim value. Available range is 0U-31U. +*/ +static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue) +{ + base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; + base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); +} + +/*! +* @brief Get the default setting for loop control configuration. +* +* The default configuration are set according to responding registers' setting when powered on. +* They are: +* @code +* config->enableCommonHysteresis = false; +* config->enableCommonThresholdDetection = false; +* config->enableInvertHysteresisSign = false; +* config->enableRCThresholdDetection = false; +* config->enableRCScaleCircuit = 0U; +* config->complementFeedForwardStep = 0U; +* config->controlParameterMagnitude = 2U; +* config->integralProportionalRatio = 2U; +* @endcode +* +* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" +*/ +void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config); + +/*! +* @brief Configure the DCDC loop control. +* +* @param base DCDC peripheral base address. +* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". +*/ +void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config); + +/*! + * @brief Configure for the min power. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_min_power_config_t". + */ +void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config); + +/*! +* @brief Set the current bias of low power comparator. +* +* @param base DCDC peripheral base address. +* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t". +*/ +static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule) +{ + base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; + base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule); +} + +static inline void DCDC_LockTargetVoltage(DCDC_Type *base) +{ + base->REG3 |= DCDC_REG3_DISABLE_STEP_MASK; +} + +/*! +* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode. +* +* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is +* stabled. +* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch +* back to run mode if it detects the current loading is larger than about 50 mA(typical value). +* +* @param base DCDC peripheral base address. +* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. +* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. +*/ +void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby); + +/*! +* @brief Configure the DCDC internal regulator. +* +* @param base DCDC peripheral base address. +* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". +*/ +void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config); + +/*! +* @brief Ajust delay to reduce ground noise. +* +* @param base DCDC peripheral base address. +* @param enable Enable the feature or not. +*/ +static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK; + } + else + { + base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK; + } +} + +/*! +* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero +* cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM. +* +* @param base DCDC peripheral base address. +* @param enable Enable the feature or not. +*/ +static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK; + } + else + { + base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK; + } +} + +/* @} */ + +/*! + * @name Application guideline. + * @{ + */ + +/*! +* @brief Boot DCDC into DCM(discontinous conduction mode). +* +* pwd_zcd=0x0; +* pwd_cmp_offset=0x0; +* dcdc_loopctrl_en_rcscale=0x3 or 0x5; +* DCM_set_ctrl=1'b1; +* +* @param base DCDC peripheral base address. +*/ +void DCDC_BootIntoDCM(DCDC_Type *base); + +/*! +* @brief Boot DCDC into CCM(continous conduction mode). +* +* pwd_zcd=0x1; +* pwd_cmp_offset=0x0; +* dcdc_loopctrl_en_rcscale=0x3; +* +* @param base DCDC peripheral base address. +*/ +void DCDC_BootIntoCCM(DCDC_Type *base); + +#if defined(__cplusplus) +} +#endif + +#endif /* __FSL_DCDC_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcp.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcp.c new file mode 100644 index 0000000000..fdc13fa0fc --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcp.c @@ -0,0 +1,1129 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dcp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcp" +#endif + + +/*! Compile time sizeof() check */ +#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) + +#define dcp_memcpy memcpy + +/*! Internal states of the HASH creation process */ +typedef enum _dcp_hash_algo_state +{ + kDCP_StateHashInit = 1u, /*!< Init state. */ + kDCP_StateHashUpdate, /*!< Update state. */ +} dcp_hash_algo_state_t; + +/*! multiple of 64-byte block represented as byte array of 32-bit words */ +typedef union _dcp_hash_block +{ + uint32_t w[DCP_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ + uint8_t b[DCP_HASH_BLOCK_SIZE]; /*!< byte array */ +} dcp_hash_block_t; + +/*! internal dcp_hash context structure */ +typedef struct _dcp_hash_ctx_internal +{ + dcp_hash_block_t blk; /*!< memory buffer. only full blocks are written to DCP during hash updates */ + size_t blksz; /*!< number of valid bytes in memory buffer */ + dcp_hash_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ + dcp_hash_algo_state_t state; /*!< finite machine state of the hash software process */ + uint32_t fullMessageSize; /*!< track message size */ + uint32_t ctrl0; /*!< HASH_INIT and HASH_TERM flags */ + uint32_t runningHash[9]; /*!< running hash. up to SHA-256 plus size, that is 36 bytes. */ + dcp_handle_t *handle; +} dcp_hash_ctx_internal_t; + +/*!< SHA-1/SHA-2 digest length in bytes */ +enum _dcp_hash_digest_len +{ + kDCP_OutLenSha1 = 20u, + kDCP_OutLenSha256 = 32u, + kDCP_OutLenCrc32 = 4u, +}; + +enum _dcp_work_packet_bit_definitions +{ + kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */ + kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */ + kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */ + kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */ + kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16, + kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16, + kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16, +}; + +/*! 64-byte block represented as byte array of 16 32-bit words */ +typedef union _dcp_sha_block +{ + uint32_t w[64 / 4]; /*!< array of 32-bit words */ + uint8_t b[64]; /*!< byte array */ +} dcp_sha_block_t; + +#if defined(DCP_HASH_CAVP_COMPATIBLE) +/* result of sha1 hash for message with zero size */ +static uint8_t s_nullSha1[] = {0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 0x32, 0x55, + 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 0xaf, 0xd8, 0x07, 0x09}; +/* result of sha256 hash for message with zero size */ +static uint8_t s_nullSha256[] = {0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, 0xf4, + 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, + 0x93, 0x4c, 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55}; +#endif /* DCP_HASH_CAVP_COMPATIBLE */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static dcp_context_t s_dcpContextSwitchingBuffer; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len) +{ + for (int i = 0; i < src_len; i++) + { + dest[i] = src[src_len - 1 - i]; + } +} + +static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel) +{ + uint32_t statReg = 0; + uint32_t semaReg = 0; + status_t status = kStatus_Fail; + + switch (channel) + { + case kDCP_Channel0: + statReg = base->CH0STAT; + semaReg = base->CH0SEMA; + break; + + case kDCP_Channel1: + statReg = base->CH1STAT; + semaReg = base->CH1SEMA; + break; + + case kDCP_Channel2: + statReg = base->CH2STAT; + semaReg = base->CH2SEMA; + break; + + case kDCP_Channel3: + statReg = base->CH3STAT; + semaReg = base->CH3SEMA; + break; + + default: + break; + } + + if (!((semaReg & DCP_CH0SEMA_VALUE_MASK) || (statReg & DCP_CH0STAT_ERROR_CODE_MASK))) + { + status = kStatus_Success; + } + + return status; +} + +static void dcp_clear_status(DCP_Type *base) +{ + volatile uint32_t *dcpStatClrPtr = &base->STAT + 2u; + *dcpStatClrPtr = 0xFFu; +} + +static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask) +{ + volatile uint32_t *chStatClrPtr; + + if (mask & kDCP_Channel0) + { + chStatClrPtr = &base->CH0STAT + 2u; + *chStatClrPtr = 0xFFu; + } + if (mask & kDCP_Channel1) + { + chStatClrPtr = &base->CH1STAT + 2u; + *chStatClrPtr = 0xFFu; + } + if (mask & kDCP_Channel2) + { + chStatClrPtr = &base->CH2STAT + 2u; + *chStatClrPtr = 0xFFu; + } + if (mask & kDCP_Channel3) + { + chStatClrPtr = &base->CH3STAT + 2u; + *chStatClrPtr = 0xFFu; + } +} + +static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key) +{ + base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0); + /* move the key by 32-bit words */ + int i = 0; + size_t keySize = 16u; + while (keySize) + { + keySize -= sizeof(uint32_t); + base->KEYDATA = ((uint32_t *)(uintptr_t)key)[i]; + i++; + } + return kStatus_Success; +} + +static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket) +{ + status_t status; + + /* check if our channel is active */ + if ((base->STAT & (uint32_t)handle->channel) != handle->channel) + { + /* disable global interrupt */ + uint32_t currPriMask = DisableGlobalIRQ(); + + /* re-check if our channel is still available */ + if ((base->STAT & (uint32_t)handle->channel) == 0) + { + volatile uint32_t *cmdptr = NULL; + volatile uint32_t *chsema = NULL; + + switch (handle->channel) + { + case kDCP_Channel0: + cmdptr = &base->CH0CMDPTR; + chsema = &base->CH0SEMA; + break; + + case kDCP_Channel1: + cmdptr = &base->CH1CMDPTR; + chsema = &base->CH1SEMA; + break; + + case kDCP_Channel2: + cmdptr = &base->CH2CMDPTR; + chsema = &base->CH2SEMA; + break; + + case kDCP_Channel3: + cmdptr = &base->CH3CMDPTR; + chsema = &base->CH3SEMA; + break; + + default: + break; + } + + if (cmdptr && chsema) + { + /* set out packet to DCP CMDPTR */ + *cmdptr = (uint32_t)dcpPacket; + + /* set the channel semaphore */ + *chsema = 1u; + } + + status = kStatus_Success; + } + + else + { + status = kStatus_DCP_Again; + } + /* global interrupt enable */ + EnableGlobalIRQ(currPriMask); + } + + else + { + return kStatus_DCP_Again; + } + + return status; +} + +status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize) +{ + status_t status = kStatus_Fail; + + if ((kDCP_OtpKey == handle->keySlot) || (kDCP_OtpUniqueKey == handle->keySlot)) + { + /* for AES OTP and unique key, check and return read from fuses status */ + if ((base->STAT & DCP_STAT_OTP_KEY_READY_MASK) == DCP_STAT_OTP_KEY_READY_MASK) + { + status = kStatus_Success; + } + } + else + { + /* only work with aligned key[] */ + if (0x3U & (uintptr_t)key) + { + return kStatus_InvalidArgument; + } + + /* keySize must be 16. */ + if (keySize != 16U) + { + return kStatus_InvalidArgument; + } + + /* move the key by 32-bit words */ + int i = 0; + while (keySize) + { + keySize -= sizeof(uint32_t); + handle->keyWord[i] = ((uint32_t *)(uintptr_t)key)[i]; + i++; + } + + if (kDCP_PayloadKey != handle->keySlot) + { + /* move the key by 32-bit words to DCP SRAM-based key storage */ + status = dcp_aes_set_sram_based_key(base, handle, key); + } + else + { + /* for PAYLOAD_KEY, just return Ok status now */ + status = kStatus_Success; + } + } + + return status; +} + +status_t DCP_AES_EncryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_EncryptEcbNonBlocking(base, handle, &dcpWork, plaintext, ciphertext, size); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = 0x122u; /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->sourceBufferAddress = (uint32_t)plaintext; + dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */ + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->control1 = (handle->keySlot << 8); /* KEY_SELECT = keySlot */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +status_t DCP_AES_DecryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_DecryptEcbNonBlocking(base, handle, &dcpWork, ciphertext, plaintext, size); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = 0x22u; /* ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; + dcpPacket->destinationBufferAddress = (uint32_t)plaintext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */ + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->control1 = (handle->keySlot << 8); /* KEY_SELECT = keySlot */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +status_t DCP_AES_EncryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_EncryptCbcNonBlocking(base, handle, &dcpWork, plaintext, ciphertext, size, iv); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t *iv) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = 0x322u; /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->sourceBufferAddress = (uint32_t)plaintext; + dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* In this case payload must contain key & iv in one array. */ + /* Copy iv into handle right behind the keyWord[] so we can point payload to keyWord[]. */ + dcp_memcpy(handle->iv, iv, 16); + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT = keySlot */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +status_t DCP_AES_DecryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_DecryptCbcNonBlocking(base, handle, &dcpWork, ciphertext, plaintext, size, iv); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t *iv) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = 0x222u; /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; + dcpPacket->destinationBufferAddress = (uint32_t)plaintext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFFu << 8); /* OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFEu << 8); /* UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* in this case payload must contain KEY + IV together */ + /* copy iv into handle struct so we can point payload directly to keyWord[]. */ + dcp_memcpy(handle->iv, iv, 16); + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +void DCP_GetDefaultConfig(dcp_config_t *config) +{ + /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses + * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support + * Hash context switch (different messages interleaved) on the same channel. + */ + dcp_config_t userConfig = { + true, false, true, kDCP_chEnableAll, kDCP_chIntDisable, + }; + + *config = userConfig; +} + +void DCP_Init(DCP_Type *base, const dcp_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Dcp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CTRL = 0xF0800000u; /* reset value */ + base->CTRL = 0x30800000u; /* default value */ + + dcp_clear_status(base); + dcp_clear_channel_status(base, kDCP_Channel0 | kDCP_Channel1 | kDCP_Channel2 | kDCP_Channel3); + + base->CTRL = DCP_CTRL_GATHER_RESIDUAL_WRITES(config->gatherResidualWrites) | + DCP_CTRL_ENABLE_CONTEXT_CACHING(config->enableContextCaching) | + DCP_CTRL_ENABLE_CONTEXT_SWITCHING(config->enableContextSwitching) | + DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(config->enableChannelInterrupt); + + /* enable DCP channels */ + base->CHANNELCTRL = DCP_CHANNELCTRL_ENABLE_CHANNEL(config->enableChannel); + + /* use context switching buffer */ + base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer; +} + +void DCP_Deinit(DCP_Type *base) +{ + base->CTRL = 0xF0800000u; /* reset value */ + memset(&s_dcpContextSwitchingBuffer, 0, sizeof(s_dcpContextSwitchingBuffer)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Dcp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle) +{ + /* wait if our channel is still active */ + while ((base->STAT & (uint32_t)handle->channel) == handle->channel) + { + } + + if (dcp_get_channel_status(base, handle->channel) != kStatus_Success) + { + dcp_clear_status(base); + dcp_clear_channel_status(base, handle->channel); + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * @brief Check validity of algoritm. + * + * This function checks the validity of input argument. + * + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t dcp_hash_check_input_alg(dcp_hash_algo_t algo) +{ + if ((algo != kDCP_Sha256) && (algo != kDCP_Sha1) && (algo != kDCP_Crc32)) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Check validity of input arguments. + * + * This function checks the validity of input arguments. + * + * @param base DCP peripheral base address. + * @param ctx Memory buffer given by user application where the DCP_HASH_Init/DCP_HASH_Update/DCP_HASH_Finish store + * context. + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t dcp_hash_check_input_args(DCP_Type *base, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) +{ + /* Check validity of input algorithm */ + if (kStatus_Success != dcp_hash_check_input_alg(algo)) + { + return kStatus_InvalidArgument; + } + + if ((NULL == ctx) || (NULL == base)) + { + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * @brief Check validity of internal software context. + * + * This function checks if the internal context structure looks correct. + * + * @param ctxInternal Internal context. + * @param message Input message address. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t dcp_hash_check_context(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message) +{ + if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != dcp_hash_check_input_alg(ctxInternal->algo))) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Initialize the SHA engine for new hash. + * + * This function sets kDCP_CONTROL0_HASH_INIT for control0 in work packet to start a new hash. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + */ +static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal) +{ + status_t status; + + status = kStatus_InvalidArgument; + + if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo)) + { + ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT; + status = kStatus_Success; + } + + return status; +} + +static status_t dcp_hash_update_non_blocking( + DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size) +{ + dcpPacket->control0 = ctxInternal->ctrl0 | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR; + if (ctxInternal->algo == kDCP_Sha256) + { + dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256; + } + else if (ctxInternal->algo == kDCP_Sha1) + { + dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA1; + } + else if (ctxInternal->algo == kDCP_Crc32) + { + dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_CRC32; + } + else + { + return kStatus_Fail; + } + dcpPacket->sourceBufferAddress = (uint32_t)msg; + dcpPacket->destinationBufferAddress = 0; + dcpPacket->bufferSize = size; + dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash; + + return dcp_schedule_work(base, ctxInternal->handle, dcpPacket); +} + +static status_t dcp_hash_update(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = dcp_hash_update_non_blocking(base, ctxInternal, &dcpWork, msg, size); + } while (completionStatus == kStatus_DCP_Again); + + completionStatus = DCP_WaitForChannelComplete(base, ctxInternal->handle); + + ctxInternal->ctrl0 = 0; /* clear kDCP_CONTROL0_HASH_INIT and kDCP_CONTROL0_HASH_TERM flags */ + return (completionStatus); +} + +/*! + * @brief Adds message to current hash. + * + * This function merges the message to fill the internal buffer, empties the internal buffer if + * it becomes full, then process all remaining message data. + * + * + * @param base DCP peripheral base address. + * @param ctxInternal Internal context. + * @param message Input message. + * @param messageSize Size of input message in bytes. + * @return kStatus_Success. + */ +static status_t dcp_hash_process_message_data(DCP_Type *base, + dcp_hash_ctx_internal_t *ctxInternal, + const uint8_t *message, + size_t messageSize) +{ + status_t status = kStatus_Fail; + + /* if there is partially filled internal buffer, fill it to full block */ + if (ctxInternal->blksz > 0) + { + size_t toCopy = DCP_HASH_BLOCK_SIZE - ctxInternal->blksz; + dcp_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); + message += toCopy; + messageSize -= toCopy; + + /* process full internal block */ + status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], DCP_HASH_BLOCK_SIZE); + if (kStatus_Success != status) + { + return status; + } + } + + /* process all full blocks in message[] */ + uint32_t fullBlocksSize = ((messageSize >> 6) << 6); /* (X / 64) * 64 */ + if (fullBlocksSize > 0) + { + status = dcp_hash_update(base, ctxInternal, message, fullBlocksSize); + if (kStatus_Success != status) + { + return status; + } + message += fullBlocksSize; + messageSize -= fullBlocksSize; + } + + /* copy last incomplete message bytes into internal block */ + dcp_memcpy(&ctxInternal->blk.b[0], message, messageSize); + ctxInternal->blksz = messageSize; + + return status; +} + +/*! + * @brief Finalize the running hash to make digest. + * + * This function empties the internal buffer, adds padding bits, and generates final digest. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @return kStatus_Success. + */ +static status_t dcp_hash_finalize(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal) +{ + status_t status; + + ctxInternal->ctrl0 |= kDCP_CONTROL0_HASH_TERM; + status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], ctxInternal->blksz); + + return status; +} + +static void dcp_hash_save_running_hash(dcp_hash_ctx_internal_t *ctxInternal) +{ + uint32_t *srcAddr = NULL; + + switch (ctxInternal->handle->channel) + { + case kDCP_Channel0: + srcAddr = &s_dcpContextSwitchingBuffer.x[43]; + break; + + case kDCP_Channel1: + srcAddr = &s_dcpContextSwitchingBuffer.x[30]; + break; + + case kDCP_Channel2: + srcAddr = &s_dcpContextSwitchingBuffer.x[17]; + break; + + case kDCP_Channel3: + srcAddr = &s_dcpContextSwitchingBuffer.x[4]; + break; + + default: + break; + } + if (srcAddr) + { + dcp_memcpy(ctxInternal->runningHash, srcAddr, sizeof(ctxInternal->runningHash)); + } +} + +static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal) +{ + uint32_t *destAddr = NULL; + + switch (ctxInternal->handle->channel) + { + case kDCP_Channel0: + destAddr = &s_dcpContextSwitchingBuffer.x[43]; + break; + + case kDCP_Channel1: + destAddr = &s_dcpContextSwitchingBuffer.x[30]; + break; + + case kDCP_Channel2: + destAddr = &s_dcpContextSwitchingBuffer.x[17]; + break; + + case kDCP_Channel3: + destAddr = &s_dcpContextSwitchingBuffer.x[4]; + break; + + default: + break; + } + if (destAddr) + { + dcp_memcpy(destAddr, ctxInternal->runningHash, sizeof(ctxInternal->runningHash)); + } +} + +status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) +{ + status_t status; + + dcp_hash_ctx_internal_t *ctxInternal; + /* compile time check for the correct structure size */ + BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= sizeof(dcp_hash_ctx_internal_t), dcp_hash_ctx_t_size); + uint32_t i; + + status = dcp_hash_check_input_args(base, ctx, algo); + if (status != kStatus_Success) + { + return status; + } + + /* set algorithm in context struct for later use */ + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + ctxInternal->algo = algo; + ctxInternal->blksz = 0u; + for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) + { + ctxInternal->blk.w[0] = 0u; + } + ctxInternal->state = kDCP_StateHashInit; + ctxInternal->fullMessageSize = 0; + ctxInternal->handle = handle; + return status; +} + +status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) +{ + bool isUpdateState; + status_t status; + dcp_hash_ctx_internal_t *ctxInternal; + size_t blockSize; + + if (inputSize == 0) + { + return kStatus_Success; + } + + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + status = dcp_hash_check_context(ctxInternal, input); + if (kStatus_Success != status) + { + return status; + } + + ctxInternal->fullMessageSize += inputSize; + blockSize = DCP_HASH_BLOCK_SIZE; + /* if we are still less than DCP_HASH_BLOCK_SIZE bytes, keep only in context */ + if ((ctxInternal->blksz + inputSize) <= blockSize) + { + dcp_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); + ctxInternal->blksz += inputSize; + return status; + } + else + { + isUpdateState = ctxInternal->state == kDCP_StateHashUpdate; + if (!isUpdateState) + { + /* start NEW hash */ + status = dcp_hash_engine_init(base, ctxInternal); + if (status != kStatus_Success) + { + return status; + } + ctxInternal->state = kDCP_StateHashUpdate; + } + else + { + dcp_hash_restore_running_hash(ctxInternal); + } + } + + /* process input data */ + status = dcp_hash_process_message_data(base, ctxInternal, input, inputSize); + dcp_hash_save_running_hash(ctxInternal); + return status; +} + +status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) +{ + size_t algOutSize = 0; + status_t status; + dcp_hash_ctx_internal_t *ctxInternal; + + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + status = dcp_hash_check_context(ctxInternal, output); + if (kStatus_Success != status) + { + return status; + } + + if (ctxInternal->state == kDCP_StateHashInit) + { + status = dcp_hash_engine_init(base, ctxInternal); + if (status != kStatus_Success) + { + return status; + } + } + else + { + dcp_hash_restore_running_hash(ctxInternal); + } + + size_t outSize = 0u; + + /* compute algorithm output length */ + switch (ctxInternal->algo) + { + case kDCP_Sha256: + outSize = kDCP_OutLenSha256; + break; + case kDCP_Sha1: + outSize = kDCP_OutLenSha1; + break; + case kDCP_Crc32: + outSize = kDCP_OutLenCrc32; + break; + default: + break; + } + algOutSize = outSize; + +#if defined(DCP_HASH_CAVP_COMPATIBLE) + if (ctxInternal->fullMessageSize == 0) + { + switch (ctxInternal->algo) + { + case kDCP_Sha256: + dcp_memcpy(&output[0], &s_nullSha256, 32); + break; + case kDCP_Sha1: + dcp_memcpy(&output[0], &s_nullSha1, 20); + break; + default: + break; + } + + return kStatus_Success; + } +#endif /* DCP_HASH_CAVP_COMPATIBLE */ + + /* flush message last incomplete block, if there is any, and add padding bits */ + status = dcp_hash_finalize(base, ctxInternal); + + if (outputSize) + { + if (algOutSize < *outputSize) + { + *outputSize = algOutSize; + } + else + { + algOutSize = *outputSize; + } + } + + /* Reverse and copy result to output[] */ + dcp_reverse_and_copy((uint8_t *)ctxInternal->runningHash, &output[0], algOutSize); + + memset(ctx, 0, sizeof(dcp_hash_ctx_t)); + return status; +} + +status_t DCP_HASH(DCP_Type *base, + dcp_handle_t *handle, + dcp_hash_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize) +{ + dcp_hash_ctx_t hashCtx; + status_t status; + + status = DCP_HASH_Init(base, handle, &hashCtx, algo); + if (status != kStatus_Success) + { + return status; + } + + status = DCP_HASH_Update(base, &hashCtx, input, inputSize); + if (status != kStatus_Success) + { + return status; + } + + status = DCP_HASH_Finish(base, &hashCtx, output, outputSize); + + return status; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcp.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcp.h new file mode 100644 index 0000000000..15694703a6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcp.h @@ -0,0 +1,557 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DCP_H_ +#define _FSL_DCP_H_ + +#include "fsl_common.h" + +/*! @brief DCP status return codes. */ +enum _dcp_status +{ + kStatus_DCP_Again = MAKE_STATUS(kStatusGroup_DCP, 0), /*!< Non-blocking function shall be called again. */ +}; + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup dcp_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief DCP driver version. Version 2.0.0. + * + * Current version: 2.0.0 + * + * Change log: + * - Version 2.0.0 + * - Initial version + */ +#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief DCP channel enable. + * + */ +typedef enum _dcp_ch_enable +{ + kDCP_chDisable = 0U, /*!< DCP channel disable */ + kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */ + kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */ + kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */ + kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */ + kDCP_chEnableAll = 15U, /*!< DCP channel enable all */ +} _dcp_ch_enable_t; + +/*! @brief DCP interrupt enable. + * + */ +typedef enum _dcp_ch_int_enable +{ + kDCP_chIntDisable = 0U, /*!< DCP interrupts disable */ + kDCP_ch0IntEnable = 1U, /*!< DCP channel 0 interrupt enable */ + kDCP_ch1IntEnable = 2U, /*!< DCP channel 1 interrupt enable */ + kDCP_ch2IntEnable = 4U, /*!< DCP channel 2 interrupt enable */ + kDCP_ch3IntEnable = 8U, /*!< DCP channel 3 interrupt enable */ +} _dcp_ch_int_enable_t; + +/*! @brief DCP channel selection. + * + */ +typedef enum _dcp_channel +{ + kDCP_Channel0 = (1u << 16), /*!< DCP channel 0. */ + kDCP_Channel1 = (1u << 17), /*!< DCP channel 1. */ + kDCP_Channel2 = (1u << 18), /*!< DCP channel 2. */ + kDCP_Channel3 = (1u << 19), /*!< DCP channel 3. */ +} dcp_channel_t; + +/*! @brief DCP key slot selection. + * + */ +typedef enum _dcp_key_slot +{ + kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */ + kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */ + kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/ + kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */ + kDCP_OtpKey = 4U, /*!< DCP OTP key. */ + kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */ + kDCP_PayloadKey = 6U, /*!< DCP payload key. */ +} dcp_key_slot_t; + +/*! @brief DCP's work packet. */ +typedef struct _dcp_work_packet +{ + uint32_t nextCmdAddress; + uint32_t control0; + uint32_t control1; + uint32_t sourceBufferAddress; + uint32_t destinationBufferAddress; + uint32_t bufferSize; + uint32_t payloadPointer; + uint32_t status; +} dcp_work_packet_t; + +/*! @brief Specify DCP's key resource and DCP channel. */ +typedef struct _dcp_handle +{ + dcp_channel_t channel; /*!< Specify DCP channel. */ + dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */ + uint32_t keyWord[4]; + uint32_t iv[4]; +} dcp_handle_t; + +/*! @brief DCP's context buffer, used by DCP for context switching between channels. */ +typedef struct _dcp_context +{ + uint32_t x[208 / sizeof(uint32_t)]; +} dcp_context_t; + +/*! @brief DCP's configuration structure. */ +typedef struct _dcp_config +{ + bool gatherResidualWrites; /*!< Enable the ragged writes to the unaligned buffers. */ + bool enableContextCaching; /*!< Enable the caching of contexts between the operations. */ + bool enableContextSwitching; /*!< Enable automatic context switching for the channels. */ + uint8_t enableChannel; /*!< DCP channel enable. */ + uint8_t enableChannelInterrupt; /*!< Per-channel interrupt enable. */ +} dcp_config_t; + +/*! @} */ + +/******************************************************************************* + * AES Definitions + *******************************************************************************/ + +/*! + * @addtogroup dcp_driver_aes + * @{ + */ + +/*! AES block size in bytes */ +#define DCP_AES_BLOCK_SIZE 16 + +/*! + *@} + */ /* end of dcp_driver_aes */ + +/******************************************************************************* + * HASH Definitions + ******************************************************************************/ +/*! + * @addtogroup dcp_driver_hash + * @{ + */ + +/* DCP cannot correctly compute hash for message with zero size. When enabled, driver bypases DCP and returns correct + * hash value. If you are sure, that the driver will never be called with zero sized message, you can disable this + * feature to reduce code size */ +#define DCP_HASH_CAVP_COMPATIBLE + +/*! @brief Supported cryptographic block cipher functions for HASH creation */ +typedef enum _dcp_hash_algo_t +{ + kDCP_Sha1, /*!< SHA_1 */ + kDCP_Sha256, /*!< SHA_256 */ + kDCP_Crc32, /*!< CRC_32 */ +} dcp_hash_algo_t; + +/*! @brief DCP HASH Context size. */ +#define DCP_SHA_BLOCK_SIZE 128 /*!< internal buffer block size */ +#define DCP_HASH_BLOCK_SIZE DCP_SHA_BLOCK_SIZE /*!< DCP hash block size */ + +/*! @brief DCP HASH Context size. */ +#define DCP_HASH_CTX_SIZE 58 + +/*! @brief Storage type used to save hash context. */ +typedef struct _dcp_hash_ctx_t +{ + uint32_t x[DCP_HASH_CTX_SIZE]; +} dcp_hash_ctx_t; + +/*! + *@} + */ /* end of dcp_driver_hash */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup dcp_driver + * @{ + */ + +/*! + * @brief Enables clock to and enables DCP + * + * Enable DCP clock and configure DCP. + * + * @param base DCP base address + * @param config Pointer to configuration structure. + */ +void DCP_Init(DCP_Type *base, const dcp_config_t *config); + +/*! + * @brief Disable DCP clock + * + * Reset DCP and Disable DCP clock. + * + * @param base DCP base address + */ +void DCP_Deinit(DCP_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the DCP configuration structure to a default value. The default + * values are as follows. + * dcpConfig->gatherResidualWrites = true; + * dcpConfig->enableContextCaching = true; + * dcpConfig->enableContextSwitching = true; + * dcpConfig->enableChannnel = kDCP_chEnableAll; + * dcpConfig->enableChannelInterrupt = kDCP_chIntDisable; + * + * @param[out] config Pointer to configuration structure. + */ +void DCP_GetDefaultConfig(dcp_config_t *config); + +/*! + * @brief Poll and wait on DCP channel. + * + * Polls the specified DCP channel until current it completes activity. + * + * @param base DCP peripheral base address. + * @param handle Specifies DCP channel. + * @return kStatus_Success When data processing completes without error. + * @return kStatus_Fail When error occurs. + */ +status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle); + +/*! + *@} + */ /* end of dcp_driver */ + +/******************************************************************************* + * AES API + ******************************************************************************/ + +/*! + * @addtogroup dcp_driver_aes + * @{ + */ + +/*! + * @brief Set AES key to dcp_handle_t struct and optionally to DCP. + * + * Sets the AES key for encryption/decryption with the dcp_handle_t structure. + * The dcp_handle_t input argument specifies keySlot. + * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use + * status. + * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct. + * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2, + * kDCP_KeySlot3), + * this function will also load the supplied key to the specified keySlot in DCP. + * + * @param base DCP peripheral base address. + * @param handle Handle used for the request. + * @param key 0-mod-4 aligned pointer to AES key. + * @param keySize AES key size in bytes. Shall equal 16. + * @return status from set key operation + */ +status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize); + +/*! + * @brief Encrypts AES on one or multiple 128-bit block(s). + * + * Encrypts AES. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from encrypt operation + */ +status_t DCP_AES_EncryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); + +/*! + * @brief Decrypts AES on one or multiple 128-bit block(s). + * + * Decrypts AES. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input plain text to encrypt + * @param[out] plaintext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from decrypt operation + */ +status_t DCP_AES_DecryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); + +/*! + * @brief Encrypts AES using CBC block mode. + * + * Encrypts AES using CBC block mode. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ +status_t DCP_AES_EncryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Decrypts AES using CBC block mode. + * + * Decrypts AES using CBC block mode. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from decrypt operation + */ +status_t DCP_AES_DecryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]); + +/*! + *@} + */ /* end of dcp_driver_aes */ + +/*! + * @addtogroup dcp_nonblocking_driver_aes + * @{ + */ +/*! +* @brief Encrypts AES using the ECB block mode. +* +* Puts AES ECB encrypt work packet to DCP channel. +* +* @param base DCP peripheral base address +* @param handle Handle used for this request. +* @param[out] dcpPacket Memory for the DCP work packet. +* @param plaintext Input plain text to encrypt. +* @param[out] ciphertext Output cipher text +* @param size Size of input and output data in bytes. Must be multiple of 16 bytes. +* @return kStatus_Success The work packet has been scheduled at DCP channel. +* @return kStatus_DCP_Again The DCP channel is busy processing previous request. +*/ +status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size); + +/*! + * @brief Decrypts AES using ECB block mode. + * + * Puts AES ECB decrypt dcpPacket to DCP input job ring. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size); + +/*! + * @brief Encrypts AES using CBC block mode. + * + * Puts AES CBC encrypt dcpPacket to DCP input job ring. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. Specifies jobRing. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t *iv); + +/*! + * @brief Decrypts AES using CBC block mode. + * + * Puts AES CBC decrypt dcpPacket to DCP input job ring. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. Specifies jobRing. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t *iv); + +/*! + *@} + */ /* end of dcp_nonblocking_driver_aes */ + +/******************************************************************************* + * HASH API + ******************************************************************************/ + +/*! + * @addtogroup dcp_driver_hash + * @{ + */ +/*! + * @brief Initialize HASH context + * + * This function initializes the HASH. + * + * @param base DCP peripheral base address + * @param handle Specifies the DCP channel used for hashing. + * @param[out] ctx Output hash context + * @param algo Underlaying algorithm to use for hash computation. + * @return Status of initialization + */ +status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo); + +/*! + * @brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. The functions blocks. If it returns kStatus_Success, the running hash + * has been updated (DCP has processed the input data), so the memory at @ref input pointer + * can be released back to system. The DCP context buffer is updated with the running hash + * and with all necessary information to support possible context switch. + * + * @param base DCP peripheral base address + * @param[in,out] ctx HASH context + * @param input Input data + * @param inputSize Size of input data in bytes + * @return Status of the hash update operation + */ +status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); + +/*! + * @brief Finalize hashing + * + * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context. + * + * @param[in,out] ctx Input hash context + * @param[out] output Output hash data + * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of + * output[] buffer. On function return, it stores the number of updated output bytes. + * @return Status of the hash finish operation + */ +status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); + +/*! + * @brief Create HASH on given data + * + * Perform the full SHA or CRC32 in one function call. The function is blocking. + * + * @param base DCP peripheral base address + * @param handle Handle used for the request. + * @param algo Underlaying algorithm to use for hash computation. + * @param input Input data + * @param inputSize Size of input data in bytes + * @param[out] output Output hash data + * @param[out] outputSize Output parameter storing the size of the output hash in bytes + * @return Status of the one call hash operation. + */ +status_t DCP_HASH(DCP_Type *base, + dcp_handle_t *handle, + dcp_hash_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize); + +/*! + *@} + */ /* end of dcp_driver_hash */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_DCP_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.c new file mode 100644 index 0000000000..155531de5a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.c @@ -0,0 +1,103 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmamux" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMAMUX. + * + * @param base DMAMUX peripheral base address. + */ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMAMUX instance number to base pointer. */ +static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMAMUX instance number to clock name. */ +static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++) + { + if (s_dmamuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dmamuxBases)); + + return instance; +} + +void DMAMUX_Init(DMAMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void DMAMUX_Deinit(DMAMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.h new file mode 100644 index 0000000000..17f32ee2e8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.h @@ -0,0 +1,204 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMAMUX_H_ +#define _FSL_DMAMUX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmamux + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMAMUX driver version 2.0.2. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMAMUX Initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the DMAMUX peripheral. + * + * This function ungates the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base); + +/*! + * @brief Deinitializes the DMAMUX peripheral. + * + * This function gates the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base); + +/* @} */ +/*! + * @name DMAMUX Channel Operation + * @{ + */ + +/*! + * @brief Enables the DMAMUX channel. + * + * This function enables the DMAMUX channel. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Disables the DMAMUX channel. + * + * This function disables the DMAMUX channel. + * + * @note The user must disable the DMAMUX channel before configuring it. + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Configures the DMAMUX channel source. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param source Channel source, which is used to trigger the DMA transfer. + */ +static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); +} + +#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U +/*! + * @brief Enables the DMAMUX period trigger. + * + * This function enables the DMAMUX period trigger feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; +} + +/*! + * @brief Disables the DMAMUX period trigger. + * + * This function disables the DMAMUX period trigger. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; +} +#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ + +#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) +/*! + * @brief Enables the DMA channel to be always ON. + * + * This function enables the DMAMUX channel always ON feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. + */ +static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + if (enable) + { + base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; + } + else + { + base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; + } +} +#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /* _FSL_DMAMUX_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_edma.c new file mode 100644 index 0000000000..96b0f80022 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_edma.c @@ -0,0 +1,2299 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma" +#endif + + +#define EDMA_TRANSFER_ENABLED_MASK 0x80U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for EDMA. + * + * @param base EDMA peripheral base address. + */ +static uint32_t EDMA_GetInstance(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map EDMA instance number to base pointer. */ +static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map EDMA instance number to clock name. */ +static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Array to map EDMA instance number to IRQ number. */ +static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; + +/*! @brief Pointers to transfer handle for each EDMA channel. */ +static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t EDMA_GetInstance(DMA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) + { + if (s_edmaBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_edmaBases)); + + return instance; +} + +void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + /* Push tcd into hardware TCD register */ + base->TCD[channel].SADDR = tcd->SADDR; + base->TCD[channel].SOFF = tcd->SOFF; + base->TCD[channel].ATTR = tcd->ATTR; + base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; + base->TCD[channel].SLAST = tcd->SLAST; + base->TCD[channel].DADDR = tcd->DADDR; + base->TCD[channel].DOFF = tcd->DOFF; + base->TCD[channel].CITER_ELINKNO = tcd->CITER; + base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; + /* Clear DONE bit first, otherwise ESG cannot be set */ + base->TCD[channel].CSR = 0; + base->TCD[channel].CSR = tcd->CSR; + base->TCD[channel].BITER_ELINKNO = tcd->BITER; +} + +void EDMA_Init(DMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + + uint32_t tmpreg; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EDMA periphral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = base->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); + base->CR = tmpreg; +} + +void EDMA_Deinit(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate EDMA periphral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + config->enableRoundRobinArbitration = false; + config->enableHaltOnError = true; + config->enableContinuousLinkMode = false; + config->enableDebugMode = false; +} + +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); +} + +void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); +} + +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].NBYTES_MLOFFYES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + base->TCD[channel].NBYTES_MLOFFYES = tmpreg; +} + +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); +} + +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Enable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI |= (0x1U << channel); + } + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Disable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI &= ~(0x1U << channel); + } + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(true); + tcd->BITER = 0U; +} + +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + /* source address */ + tcd->SADDR = config->srcAddr; + /* destination address */ + tcd->DADDR = config->destAddr; + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); + /* Source address signed offset */ + tcd->SOFF = config->srcOffset; + /* Destination address signed offset */ + tcd->DOFF = config->destOffset; + /* Minor byte transfer count */ + tcd->NBYTES = config->minorLoopBytes; + /* Current major iteration count */ + tcd->CITER = config->majorLoopCounts; + /* Starting major iteration count */ + tcd->BITER = config->majorLoopCounts; + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = (uint32_t)nextTcd; + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + } +} + +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint32_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set likned channel */ + tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint32_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; + } +} + +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t remainingCount = 0; + + if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) + { + remainingCount = 0; + } + else + { + /* Calculate the unfinished bytes */ + if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) + { + remainingCount = + (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; + } + else + { + remainingCount = + (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; + } + } + + return remainingCount; +} + +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + /* Get ERROR bit flag */ + retval |= (((base->ERR >> channel) & 0x1U) << 1U); + /* Get INT bit flag */ + retval |= (((base->INT >> channel) & 0x1U) << 2U); + + return retval; +} + +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Clear DONE bit flag */ + if (mask & kEDMA_DoneFlag) + { + base->CDNE = channel; + } + /* Clear ERROR bit flag */ + if (mask & kEDMA_ErrorFlag) + { + base->CERR = channel; + } + /* Clear INT bit flag */ + if (mask & kEDMA_InterruptFlag) + { + base->CINT = channel; + } +} + +static uint8_t Get_StartInstance(void) +{ + static uint8_t StartInstanceNum; + +#if defined(DMA0) + StartInstanceNum = EDMA_GetInstance(DMA0); +#elif defined(DMA1) + StartInstanceNum = EDMA_GetInstance(DMA1); +#elif defined(DMA2) + StartInstanceNum = EDMA_GetInstance(DMA2); +#elif defined(DMA3) + StartInstanceNum = EDMA_GetInstance(DMA3); +#endif + + return StartInstanceNum; +} + +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t edmaInstance; + uint32_t channelIndex; + uint8_t StartInstance; + edma_tcd_t *tcdRegs; + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + handle->base = base; + handle->channel = channel; + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + StartInstance = Get_StartInstance(); + channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; + s_EDMAHandle[channelIndex] = handle; + + /* Enable NVIC interrupt */ + EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0); + + /* Initialize tcd queue attibute. */ + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + handle->tcdSize = tcdSize; + handle->flags = 0; + handle->tcdPool = tcdPool; +} + +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); + assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); + assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); + assert(transferBytes % bytesEachRequest == 0); + + config->destAddr = (uint32_t)destAddr; + config->srcAddr = (uint32_t)srcAddr; + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + switch (srcWidth) + { + case 1U: + config->srcTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->srcTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->srcTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->srcTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->srcTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (destWidth) + { + case 1U: + config->destTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->destTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->destTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->destTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->destTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (type) + { + case kEDMA_MemoryToMemory: + config->destOffset = destWidth; + config->srcOffset = srcWidth; + break; + case kEDMA_MemoryToPeripheral: + config->destOffset = 0U; + config->srcOffset = srcWidth; + break; + case kEDMA_PeripheralToMemory: + config->destOffset = destWidth; + config->srcOffset = 0U; + break; + default: + break; + } +} + +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + if (handle->tcdPool == NULL) + { + /* + Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because + if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit + this check mechanism, EDMA_CreatHandle will clear CSR register. + */ + if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); + /* Enable auto disable request feature */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint32_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + if (handle->tcdUsed >= handle->tcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1U; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0U; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + link succeed. + */ + if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + { + tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; + } +} + +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + handle->flags |= EDMA_TRANSFER_ENABLED_MASK; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & (1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +} + +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +} + +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + handle->base->TCD[handle->channel].CSR = 0; + /* Cancel all next TCD transfer. */ + handle->base->TCD[handle->channel].DLAST_SGA = 0; + + /* Handle the tcd */ + if (handle->tcdPool != NULL) + { + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + } +} + +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Clear EDMA interrupt flag */ + handle->base->CINT = handle->channel; + if ((handle->tcdPool == NULL) && (handle->callback != NULL)) + { + (handle->callback)(handle, handle->userData, true, 0); + } + else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ + { + uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool transfer_done; + + /* Check if transfer is already finished. */ + transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); + /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ + sga -= (uint32_t)handle->tcdPool; + /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD to be loaded (current one is already finished) */ + new_header = sga_index; + } + else + { + /* New header shall point to this descriptor currently loaded (not finished yet) */ + new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == handle->header) + { + if (handle->tcdUsed == handle->tcdSize) + { + tcds_done = handle->tcdUsed; + } + else + { + /* No TCD in the memory are going to be loaded or internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = new_header - handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + } + /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ + handle->header = new_header; + /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ + handle->tcdUsed -= tcds_done; + /* Invoke callback function. */ + if (handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + } +} + +/* 8 channels (Shared): kl28 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U + +#if defined(DMA0) +void DMA0_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA1) + +#if defined(DMA0) +void DMA1_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#else +void DMA1_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#endif /* 8 channels (Shared) */ + +/* 16 channels (Shared): K32H844P */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U + +void DMA0_08_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_210_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_311_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_412_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_513_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_614_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_715_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(DMA1) +void DMA1_08_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_210_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_311_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_412_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_513_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_614_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_715_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif /* 16 channels (Shared) */ + +/* 32 channels (Shared): k80 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_DMA16_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_DMA17_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA2_DMA18_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA3_DMA19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA4_DMA20_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA5_DMA21_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA6_DMA22_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA7_DMA23_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA8_DMA24_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA9_DMA25_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA10_DMA26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA11_DMA27_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA12_DMA28_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA13_DMA29_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA14_DMA30_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA15_DMA31_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* 32 channels (Shared) */ + +/* 32 channels (Shared): MCIMX7U5_M4 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_0_4_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_1_5_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_2_6_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_3_7_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_8_12_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_9_13_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_10_14_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_11_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_16_20_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_17_21_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_18_22_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_19_23_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_24_28_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_25_29_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_26_30_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_27_31_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* 32 channels (Shared): MCIMX7U5 */ + +/* 4 channels (No Shared): kv10 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 + +void DMA0_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA2_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[2]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA3_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[3]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* 8 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U + +void DMA4_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[4]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA5_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[5]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA6_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[6]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA7_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[7]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ + +/* 16 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U + +void DMA8_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[8]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA9_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[9]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA10_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[10]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA11_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[11]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA12_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[12]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA13_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[13]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA14_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[14]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA15_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[15]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ + +/* 32 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U + +void DMA16_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[16]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA17_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[17]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA18_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[18]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA19_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[19]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA20_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[20]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA21_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[21]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA22_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[22]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA23_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[23]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA24_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[24]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA25_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[25]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA26_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[26]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA27_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[27]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA28_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[28]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA29_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[29]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA30_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[30]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA31_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[31]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ + +#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_edma.h new file mode 100644 index 0000000000..03bc8db16d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_edma.h @@ -0,0 +1,957 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_EDMA_H_ +#define _FSL_EDMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */ +/*@}*/ + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) + +/*! @brief Get the pointer of DCHPRIn */ +#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ +} edma_modulo_t; + +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief eDMA channel status flags. */ +enum _edma_channel_status_flags +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief eDMA channel error status flags. */ +enum _edma_error_status_flags +{ + kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ + kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ + kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 + kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ +}; + +/*! @brief eDMA interrupt source */ +typedef enum _edma_interrupt_enable +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +} edma_interrupt_enable_t; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA transfer status */ +enum _edma_transfer_status +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority + arbitration is used for channel selection */ + bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of + a new channel. Executing channels are allowed to complete. */ +} edma_config_t; + +/*! + * @brief eDMA transfer configuration + * + * This structure configures the source/destination transfer attribute. + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to + form the next-state value as each source read is completed. */ + int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to + form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ + uint32_t majorLoopCounts; /*!< Major loop iteration count. */ +} edma_transfer_config_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ +} edma_minor_offset_config_t; + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure the scatter/gather feature as a next hardware TCD. + */ +typedef struct _edma_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_tcd_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + DMA_Type *base; /*!< eDMA peripheral base address. */ + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint8_t channel; /*!< eDMA channel number. */ + volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ + volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in + the memory. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ + uint8_t flags; /*!< The status of the current channel. */ +} edma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config A pointer to the configuration structure, see "edma_config_t". + * @note This function enables the minor loop map feature. + */ +void EDMA_Init(DMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(DMA_Type *base); + +/*! + * @brief Push content of TCD structure into hardware TCD register. + * + * @param base EDMA peripheral base address. + * @param channel EDMA channel number. + * @param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +/*! + * @brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * @note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(DMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config A pointer to the channel preemption configuration structure. + */ +static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, + uint32_t channel, + const edma_channel_Preemption_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + DMA_DCHPRIn(base, channel) = + (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | + DMA_DCHPRI0_CHPRI(config->channelPriority)); +} + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type A channel link type, which can be one of the following: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); +} +#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The STCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SERQ = DMA_SERQ_SERQ(channel); +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CERQ = DMA_CERQ_CERQ(channel); +} + +/*! + * @brief Starts the eDMA transfer by using the software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SSRT = DMA_SSRT_SSRT(channel); +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Major loop count which has not been transferred yet for the current TCD. + * @note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. Users need to use the +* _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) +{ + return base->ES; +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * @param handle eDMA handle pointer. + * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief Get unused TCD slot number. + * + * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. + * + * @param handle DMA handle pointer. + * @return The unused tcd slot number. + */ +static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) +{ + return (handle->tcdSize - handle->tcdUsed); +} + +/*! + * @brief Get the next tcd address. + * + * This function gets the next tcd address. If this is last TCD, return 0. + * + * @param handle DMA handle pointer. + * @return The next TCD address. + */ +static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) +{ + return (handle->base->TCD[handle->channel].DLAST_SGA); +} + +/*! + * @brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_EDMA_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.c new file mode 100644 index 0000000000..51aabe3b88 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.c @@ -0,0 +1,303 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_elcdif.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.elcdif" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for ELCDIF module. + * + * @param base ELCDIF peripheral base address + */ +static uint32_t ELCDIF_GetInstance(LCDIF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to ELCDIF bases for each instance. */ +static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to eLCDIF apb_clk for each instance. */ +static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS; +#if defined(LCDIF_PERIPH_CLOCKS) +/*! @brief Pointers to eLCDIF pix_clk for each instance. */ +static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief The control register value to select different pixel format. */ +elcdif_pixel_format_reg_t s_pixelFormatReg[] = { + /* kELCDIF_PixelFormatRAW8 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, + /* kELCDIF_PixelFormatRGB565 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(0U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, + /* kELCDIF_PixelFormatRGB666 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, + /* kELCDIF_PixelFormatXRGB8888 */ + {/* Register CTRL. 24-bit. */ + LCDIF_CTRL_WORD_LENGTH(3U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, + /* kELCDIF_PixelFormatRGB888 */ + {/* Register CTRL. 24-bit. */ + LCDIF_CTRL_WORD_LENGTH(3U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, +}; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t ELCDIF_GetInstance(LCDIF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++) + { + if (s_elcdifBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_elcdifBases)); + + return instance; +} + +void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config) +{ + assert(config); + assert(config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ELCDIF_GetInstance(base); + /* Enable the clock. */ + CLOCK_EnableClock(s_elcdifApbClocks[instance]); +#if defined(LCDIF_PERIPH_CLOCKS) + CLOCK_EnableClock(s_elcdifPixClocks[instance]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset. */ + ELCDIF_Reset(base); + + base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) | + LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */ + LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */ + LCDIF_CTRL_MASTER_MASK; + + base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1; + + base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) | + ((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT); + + base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */ + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */ + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */ + (uint32_t)config->polarityFlags | (uint32_t)config->vsw; + + base->VDCTRL1 = config->vsw + config->panelHeight + config->vfp + config->vbp; + base->VDCTRL2 = ((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) | + ((uint32_t)(config->hfp + config->hbp + config->panelWidth + config->hsw)) + << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT; + + base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) | + (((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT); + + base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK | + ((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT); + + base->CUR_BUF = config->bufferAddr; + base->NEXT_BUF = config->bufferAddr; +} + +void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config) +{ + assert(config); + + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; +} + +void ELCDIF_Deinit(LCDIF_Type *base) +{ + ELCDIF_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ELCDIF_GetInstance(base); +/* Disable the clock. */ +#if defined(LCDIF_PERIPH_CLOCKS) + CLOCK_DisableClock(s_elcdifPixClocks[instance]); +#endif + CLOCK_DisableClock(s_elcdifApbClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ELCDIF_RgbModeStop(LCDIF_Type *base) +{ + base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK; + + /* Wait for data transfer finished. */ + while (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK) + { + } +} + +void ELCDIF_Reset(LCDIF_Type *base) +{ + volatile uint32_t i = 0x100; + + /* Disable the clock gate. */ + base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; + /* Confirm the clock gate is disabled. */ + while (base->CTRL & LCDIF_CTRL_CLKGATE_MASK) + { + } + + /* Reset the block. */ + base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK; + /* Confirm the reset bit is set. */ + while (!(base->CTRL & LCDIF_CTRL_SFTRST_MASK)) + { + } + + /* Delay for the reset. */ + while (i--) + { + } + + /* Bring the module out of reset. */ + base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK; + /* Disable the clock gate. */ + base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; +} + +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) +void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config) +{ + assert(config); + + base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat); + base->AS_BUF = config->bufferAddr; + base->AS_NEXT_BUF = config->bufferAddr; +} + +void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config) +{ + assert(config); + uint32_t reg; + + reg = base->AS_CTRL; + reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK | + LCDIF_AS_CTRL_ALPHA_CTRL_MASK); + reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) | + LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode)); + + if (config->invertAlpha) + { + reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK; + } + + base->AS_CTRL = reg; +} +#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */ + +#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT) +status_t ELCDIF_UpdateLut( + LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count) +{ + volatile uint32_t *regLutAddr; + volatile uint32_t *regLutData; + uint32_t i; + + /* Only has 256 entries. */ + if (startIndex + count > ELCDIF_LUT_ENTRY_NUM) + { + return kStatus_InvalidArgument; + } + + if (kELCDIF_Lut0 == lut) + { + regLutAddr = &(base->LUT0_ADDR); + regLutData = &(base->LUT0_DATA); + } + else + { + regLutAddr = &(base->LUT1_ADDR); + regLutData = &(base->LUT1_DATA); + } + + *regLutAddr = startIndex; + + for (i = 0; i < count; i++) + { + *regLutData = lutData[i]; + } + + return kStatus_Success; +} +#endif /* FSL_FEATURE_LCDIF_HAS_LUT */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.h new file mode 100644 index 0000000000..2183c84f7d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.h @@ -0,0 +1,768 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ELCDIF_H_ +#define _FSL_ELCDIF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup elcdif + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eLCDIF driver version */ +#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/* All IRQ flags in CTRL1 register. */ +#define ELCDIF_CTRL1_IRQ_MASK \ + (LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \ + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) + +/* All IRQ enable control bits in CTRL1 register. */ +#define ELCDIF_CTRL1_IRQ_EN_MASK \ + (LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \ + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) + +/* All IRQ flags in AS_CTRL register. */ +#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) +#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) +#else +#define ELCDIF_AS_CTRL_IRQ_MASK 0U +#endif + +/* All IRQ enable control bits in AS_CTRL register. */ +#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) +#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) +#else +#define ELCDIF_AS_CTRL_IRQ_EN_MASK 0U +#endif + +#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK)) +#error Interrupt bits overlap, need to update the interrupt functions. +#endif + +/* LUT memory entery number. */ +#define ELCDIF_LUT_ENTRY_NUM 256 + +/*! + * @brief eLCDIF signal polarity flags + */ +enum _elcdif_polarity_flags +{ + kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */ + kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */ + kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */ + kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */ + kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */ + kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */ + kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data + on rising clock edge. */ + kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling + clock edge, capture data + on rising clock edge. */ +}; + +/*! + * @brief The eLCDIF interrupts to enable. + */ +enum _elcdif_interrupt_enable +{ + kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */ + kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */ + kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */ + kELCDIF_CurFrameDoneInterruptEnable = + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ + kELCDIF_VsyncEdgeInterruptEnable = + LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ +#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) + kELCDIF_SciSyncOnInterruptEnable = + LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ +#endif +}; + +/*! + * @brief The eLCDIF interrupt status flags. + */ +enum _elcdif_interrupt_flags +{ + kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */ + kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */ + kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */ + kELCDIF_CurFrameDone = + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ + kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ +#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) + kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ +#endif +}; + +/*! + * @brief eLCDIF status flags + */ +enum _elcdif_status_flags +{ + kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */ + kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */ + kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */ + kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */ +#if defined(LCDIF_STAT_BUSY_MASK) + kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */ +#endif +#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK) + kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2, + otherwise current filed is 1. */ +#endif +}; + +/*! + * @brief The pixel format. + * + * This enumerator should be defined together with the array s_pixelFormatReg. + * To support new pixel format, enhance this enumerator and s_pixelFormatReg. + */ +typedef enum _elcdif_pixel_format +{ + kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */ + kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */ + kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused, + upper 2 bits of other bytes unused. */ + kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */ + kELCDIF_PixelFormatRGB888 = 4, /*!< RGB888 packed, one pixel uses 24 bits. */ +} elcdif_pixel_format_t; + +/*! @brief The LCD data bus type. */ +typedef enum _elcdif_lcd_data_bus +{ + kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */ + kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */ + kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */ + kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */ +} elcdif_lcd_data_bus_t; + +/*! + * @brief The register value when using different pixel format. + * + * These register bits control the pixel format: + * - CTRL[DATA_FORMAT_24_BIT] + * - CTRL[DATA_FORMAT_18_BIT] + * - CTRL[DATA_FORMAT_16_BIT] + * - CTRL[WORD_LENGTH] + * - CTRL1[BYTE_PACKING_FORMAT] + */ +typedef struct _elcdif_pixel_format_reg +{ + uint32_t regCtrl; /*!< Value of register CTRL. */ + uint32_t regCtrl1; /*!< Value of register CTRL1. */ +} elcdif_pixel_format_reg_t; + +/*! + * @brief eLCDIF configure structure for RGB mode (DOTCLK mode). + */ +typedef struct _elcdif_rgb_mode_config +{ + uint16_t panelWidth; /*!< Display panel width, pixels per line. */ + uint16_t panelHeight; /*!< Display panel height, how many lines per panel. */ + uint8_t hsw; /*!< HSYNC pulse width. */ + uint8_t hfp; /*!< Horizontal front porch. */ + uint8_t hbp; /*!< Horizontal back porch. */ + uint8_t vsw; /*!< VSYNC pulse width. */ + uint8_t vfp; /*!< Vrtical front porch. */ + uint8_t vbp; /*!< Vertical back porch. */ + uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */ + uint32_t bufferAddr; /*!< Frame buffer address. */ + elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */ + elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */ +} elcdif_rgb_mode_config_t; + +/*! + * @brief eLCDIF alpha surface pixel format. + */ +typedef enum _elcdif_as_pixel_format +{ + kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ + kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ + kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ + kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ + kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ + kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ + kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ +} elcdif_as_pixel_format_t; + +/*! + * @brief eLCDIF alpha surface buffer configuration. + */ +typedef struct _elcdif_as_buffer_config +{ + uint32_t bufferAddr; /*!< Buffer address. */ + elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */ +} elcdif_as_buffer_config_t; + +/*! + * @brief eLCDIF alpha mode during blending. + */ +typedef enum _elcdif_alpha_mode +{ + kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ + kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ + kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined + alpha value will be used for blend, for example, pixel alpha set + set to 200, user defined alpha set to 100, then the reault alpha + is 200 * 100 / 255. */ + kELCDIF_AlphaRop /*!< Raster operation. */ +} elcdif_alpha_mode_t; + +/*! + * @brief eLCDIF ROP mode during blending. + * + * Explanation: + * - AS: Alpha surface + * - PS: Process surface + * - nAS: Alpha surface NOT value + * - nPS: Process surface NOT value + */ +typedef enum _elcdif_rop_mode +{ + kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */ + kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ + kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ + kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */ + kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ + kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ + kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */ + kELCDIF_RopNot = 0x7, /*!< nPS. */ + kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ + kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ + kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */ + kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */ +} elcdif_rop_mode_t; + +/*! + * @brief eLCDIF alpha surface blending configuration. + */ +typedef struct _elcdif_as_blend_config +{ + uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref + kELCDIF_AlphaRop. */ + bool invertAlpha; /*!< Set true to invert the alpha. */ + elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */ + elcdif_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */ +} elcdif_as_blend_config_t; + +/*! + * @brief eLCDIF LUT + * + * The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel + * before output to external displayer. + * + * There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address + * determins which memory to use. + */ +typedef enum _elcdif_lut +{ + kELCDIF_Lut0 = 0, /*!< LUT 0. */ + kELCDIF_Lut1, /*!< LUT 1. */ +} elcdif_lut_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eLCDIF initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode). + * + * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according + * to the configuration structure. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config); + +/*! + * @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | + kELCDIF_HsyncActiveLow | + kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; + @code + * + * @param config Pointer to the eLCDIF configuration structure. + */ +void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config); + +/*! + * @brief Deinitializes the eLCDIF peripheral. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_Deinit(LCDIF_Type *base); + +/* @} */ + +/*! + * @name Module operation + * @{ + */ + +/*! + * @brief Start to display in RGB (DOTCLK) mode. + * + * @param base eLCDIF peripheral base address. + */ +static inline void ELCDIF_RgbModeStart(LCDIF_Type *base) +{ + base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK; +} + +/*! + * @brief Stop display in RGB (DOTCLK) mode and wait until finished. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_RgbModeStop(LCDIF_Type *base); + +/*! + * @brief Set the next frame buffer address to display. + * + * @param base eLCDIF peripheral base address. + * @param bufferAddr The frame buffer address to set. + */ +static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) +{ + base->NEXT_BUF = bufferAddr; +} + +/*! + * @brief Reset the eLCDIF peripheral. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_Reset(LCDIF_Type *base); + +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) && FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) +/*! + * @brief Pull up or down the reset pin for the externel LCD controller. + * + * @param base eLCDIF peripheral base address. + * @param pullUp True to pull up reset pin, false to pull down. + */ +static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp) +{ + if (pullUp) + { + base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK; + } + else + { + base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK; + } +} +#endif + +/*! + * @brief Enable or disable the hand shake with PXP. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; + } + else + { + base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get the CRC value of the frame sent out. + * + * When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function + * can be used to get the CRC value of the frame sent. + * + * @param base eLCDIF peripheral base address. + * @return The CRC value. + * + * @note The CRC value is dependent on the LCD_DATABUS_WIDTH. + */ +static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base) +{ + return base->CRC_STAT; +} + +/*! + * @brief Get the bus master error virtual address. + * + * When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function + * can get the virtual address at which the AXI master received an error + * response from the slave. + * + * @param base eLCDIF peripheral base address. + * @return The error virtual address. + */ +static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base) +{ + return base->BM_ERROR_STAT; +} + +/*! + * @brief Get the eLCDIF status. + * + * The status flags are returned as a mask value, application could check the + * corresponding bit. Example: + * + * @code + uint32_t statusFlags; + statusFlags = ELCDIF_GetStatus(LCDIF); + + // If LFIFO is full. + if (kELCDIF_LFifoFull & statusFlags) + { + // ...; + } + // If TXFIFO is empty. + if (kELCDIF_TxFifoEmpty & statusFlags) + { + // ...; + } + @endcode + * + * @param base eLCDIF peripheral base address. + * @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags. + */ +static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base) +{ + return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK | + LCDIF_STAT_TXFIFO_EMPTY_MASK +#if defined(LCDIF_STAT_BUSY_MASK) + | LCDIF_STAT_BUSY_MASK +#endif +#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK) + | LCDIF_STAT_DVI_CURRENT_FIELD_MASK +#endif + ); +} + +/*! + * @brief Get current count in Latency buffer (LFIFO). + * + * @param base eLCDIF peripheral base address. + * @return The LFIFO current count + */ +static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base) +{ + return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables eLCDIF interrupt requests. + * + * @param base eLCDIF peripheral base address. + * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. + */ +static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) + base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); +#endif +} + +/*! + * @brief Disables eLCDIF interrupt requests. + * + * @param base eLCDIF peripheral base address. + * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. + */ +static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) + base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); +#endif +} + +/*! + * @brief Get eLCDIF interrupt peding status. + * + * @param base eLCDIF peripheral base address. + * @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags. + */ +static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base) +{ + uint32_t flags; + + flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK); +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) + flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK); +#endif + + return flags; +} + +/*! + * @brief Clear eLCDIF interrupt peding status. + * + * @param base eLCDIF peripheral base address. + * @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags. + */ +static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK); +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) + base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK); +#endif +} + +/* @} */ + +#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) +/*! + * @name Alpha surface + * @{ + */ + +/*! + * @brief Set the configuration for alpha surface buffer. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config); + +/*! + * @brief Set the alpha surface blending configuration. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config); + +/*! + * @brief Set the next alpha surface buffer address. + * + * @param base eLCDIF peripheral base address. + * @param bufferAddr Alpha surface buffer address. + */ +static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) +{ + base->AS_NEXT_BUF = bufferAddr; +} + +/*! + * @brief Set the overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface + * pixel value for that location. + * + * @param base eLCDIF peripheral base address. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + * + * @note Colorkey operations are higher priority than alpha or ROP operations + */ +static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + base->AS_CLRKEYLOW = colorKeyLow; + base->AS_CLRKEYHIGH = colorKeyHigh; +} + +/*! + * @brief Enable or disable the color key. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; + } + else + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; + } +} + +/*! + * @brief Enable or disable the alpha surface. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK; + } + else + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK; + } +} + +/*! + * @brief Enable or disable the process surface. + * + * Process surface is the normal frame buffer. The process surface content + * is controlled by @ref ELCDIF_SetNextBufferAddr. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK; + } + else + { + base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */ + +#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT) +/*! + * @name LUT + * + * The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel + * before output to external displayer. + * + * There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address + * determins which memory to use. + * + * @{ + */ + +/*! + * @brief Enable or disable the LUT. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableLut(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->LUT_CTRL &= ~LCDIF_LUT_CTRL_LUT_BYPASS_MASK; + } + else + { + base->LUT_CTRL |= LCDIF_LUT_CTRL_LUT_BYPASS_MASK; + } +} + +/*! + * @brief Load the LUT value. + * + * This function loads the LUT value to the specific LUT memory, user can + * specify the start entry index. + * + * @param base eLCDIF peripheral base address. + * @param lut Which LUT to load. + * @param startIndex The start index of the LUT entry to update. + * @param lutData The LUT data to load. + * @param count Count of @p lutData. + * @retval kStatus_Success Initialization success. + * @retval kStatus_InvalidArgument Wrong argument. + */ +status_t ELCDIF_UpdateLut( + LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count); + +/* @} */ +#endif /* FSL_FEATURE_LCDIF_HAS_LUT */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_ELCDIF_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enc.c new file mode 100644 index 0000000000..76db836d06 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enc.c @@ -0,0 +1,489 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_enc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enc" +#endif + +#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ENC module. + * + * @param base ENC peripheral base address + */ +static uint32_t ENC_GetInstance(ENC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ENC bases for each instance. */ +static ENC_Type *const s_encBases[] = ENC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ENC clocks for each instance. */ +static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ENC_GetInstance(ENC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++) + { + if (s_encBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_encBases)); + + return instance; +} + +void ENC_Init(ENC_Type *base, const enc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp16; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* ENC_CTRL. */ + tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK | + ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK)); + /* For HOME trigger. */ + if (kENC_HOMETriggerDisabled != config->HOMETriggerMode) + { + tmp16 |= ENC_CTRL_HIP_MASK; + if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) + { + tmp16 |= ENC_CTRL_HNE_MASK; + } + } + /* For encoder work mode. */ + if (config->enableReverseDirection) + { + tmp16 |= ENC_CTRL_REV_MASK; + } + if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) + { + tmp16 |= ENC_CTRL_PH1_MASK; + } + /* For INDEX trigger. */ + if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode) + { + tmp16 |= ENC_CTRL_XIP_MASK; + if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) + { + tmp16 |= ENC_CTRL_XNE_MASK; + } + } + /* Watchdog. */ + if (config->enableWatchdog) + { + tmp16 |= ENC_CTRL_WDE_MASK; + base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ + } + base->CTRL = tmp16; + + /* ENC_FILT. */ + base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod); + + /* ENC_CTRL2. */ + tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK | + ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK)); + if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) + { + tmp16 |= ENC_CTRL2_OUTCTL_MASK; + } + if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) + { + tmp16 |= ENC_CTRL2_REVMOD_MASK; + } + if (config->enableModuloCountMode) + { + tmp16 |= ENC_CTRL2_MOD_MASK; + /* Set modulus value. */ + base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ + base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ + } + if (config->enableTRIGGERClearPositionCounter) + { + tmp16 |= ENC_CTRL2_UPDPOS_MASK; + } + if (config->enableTRIGGERClearHoldPositionCounter) + { + tmp16 |= ENC_CTRL2_UPDHLD_MASK; + } + base->CTRL2 = tmp16; + + /* ENC_UCOMP & ENC_LCOMP. */ + base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ + base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ + + /* ENC_UINIT & ENC_LINIT. */ + base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ + base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ +} + +void ENC_Deinit(ENC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ENC_GetDefaultConfig(enc_config_t *config) +{ + assert(NULL != config); + + config->enableReverseDirection = false; + config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kENC_HOMETriggerDisabled; + config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; + config->enableTRIGGERClearHoldPositionCounter = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; +} + +void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); + + tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ + base->CTRL = tmp16; +} + +void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) +{ + uint16_t tmp16 = 0U; + + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + base->TST = 0U; + return; + } + tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) | + ENC_TST_TEST_COUNT(config->signalCount); + if (kENC_SelfTestDirectionNegative == config->signalDirection) + { + tmp16 |= ENC_TST_QDN_MASK; + } + base->TST = tmp16; +} + +void ENC_EnableWatchdog(ENC_Type *base, bool enable) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); + + if (enable) + { + tmp16 |= ENC_CTRL_WDE_MASK; + } + base->CTRL = tmp16; +} + +uint32_t ENC_GetStatusFlags(ENC_Type *base) +{ + uint32_t ret32 = 0U; + + /* ENC_CTRL. */ + if (ENC_CTRL_HIRQ_MASK == (ENC_CTRL_HIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_HOMETransitionFlag; + } + if (ENC_CTRL_XIRQ_MASK == (ENC_CTRL_XIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_INDEXPulseFlag; + } + if (ENC_CTRL_DIRQ_MASK == (ENC_CTRL_DIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_WatchdogTimeoutFlag; + } + if (ENC_CTRL_CMPIRQ_MASK == (ENC_CTRL_CMPIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_PositionCompareFlag; + } + + /* ENC_CTRL2. */ + if (ENC_CTRL2_SABIRQ_MASK == (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) + { + ret32 |= kENC_SimultBothPhaseChangeFlag; + } + if (ENC_CTRL2_ROIRQ_MASK == (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollOverFlag; + } + if (ENC_CTRL2_RUIRQ_MASK == (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollUnderFlag; + } + if (ENC_CTRL2_DIR_MASK == (ENC_CTRL2_DIR_MASK & base->CTRL2)) + { + ret32 |= kENC_LastCountDirectionFlag; + } + + return ret32; +} + +void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (kENC_HOMETransitionFlag == (kENC_HOMETransitionFlag & mask)) + { + tmp16 |= ENC_CTRL_HIRQ_MASK; + } + if (kENC_INDEXPulseFlag == (kENC_INDEXPulseFlag & mask)) + { + tmp16 |= ENC_CTRL_XIRQ_MASK; + } + if (kENC_WatchdogTimeoutFlag == (kENC_WatchdogTimeoutFlag & mask)) + { + tmp16 |= ENC_CTRL_DIRQ_MASK; + } + if (kENC_PositionCompareFlag == (kENC_PositionCompareFlag & mask)) + { + tmp16 |= ENC_CTRL_CMPIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL = (base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) | tmp16; + } + + /* ENC_CTRL2. */ + tmp16 = 0U; + if (kENC_SimultBothPhaseChangeFlag == (kENC_SimultBothPhaseChangeFlag & mask)) + { + tmp16 |= ENC_CTRL2_SABIRQ_MASK; + } + if (kENC_PositionRollOverFlag == (kENC_PositionRollOverFlag & mask)) + { + tmp16 |= ENC_CTRL2_ROIRQ_MASK; + } + if (kENC_PositionRollUnderFlag == (kENC_PositionRollUnderFlag & mask)) + { + tmp16 |= ENC_CTRL2_RUIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL2 = (base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) | tmp16; + } +} + +void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (kENC_HOMETransitionInterruptEnable == (kENC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_HIE_MASK; + } + if (kENC_INDEXPulseInterruptEnable == (kENC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_XIE_MASK; + } + if (kENC_WatchdogTimeoutInterruptEnable == (kENC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_DIE_MASK; + } + if (kENC_PositionCompareInerruptEnable == (kENC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= ENC_CTRL_CMPIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL = (base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) | tmp16; + } + /* ENC_CTRL2. */ + tmp16 = 0U; + if (kENC_SimultBothPhaseChangeInterruptEnable == (kENC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_SABIE_MASK; + } + if (kENC_PositionRollOverInterruptEnable == (kENC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_ROIE_MASK; + } + if (kENC_PositionRollUnderInterruptEnable == (kENC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) | tmp16; + } +} + +void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) +{ + uint16_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (kENC_HOMETransitionInterruptEnable == (kENC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_HIE_MASK; + } + if (kENC_INDEXPulseInterruptEnable == (kENC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_XIE_MASK; + } + if (kENC_WatchdogTimeoutInterruptEnable == (kENC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_DIE_MASK; + } + if (kENC_PositionCompareInerruptEnable == (kENC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= ENC_CTRL_CMPIE_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); + } + /* ENC_CTRL2. */ + tmp16 = 0U; + if (kENC_SimultBothPhaseChangeInterruptEnable == (kENC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_SABIE_MASK; + } + if (kENC_PositionRollOverInterruptEnable == (kENC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_ROIE_MASK; + } + if (kENC_PositionRollUnderInterruptEnable == (kENC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); + } +} + +uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) +{ + uint32_t ret32 = 0U; + + /* ENC_CTRL. */ + if (ENC_CTRL_HIE_MASK == (ENC_CTRL_HIE_MASK & base->CTRL)) + { + ret32 |= kENC_HOMETransitionInterruptEnable; + } + if (ENC_CTRL_XIE_MASK == (ENC_CTRL_XIE_MASK & base->CTRL)) + { + ret32 |= kENC_INDEXPulseInterruptEnable; + } + if (ENC_CTRL_DIE_MASK == (ENC_CTRL_DIE_MASK & base->CTRL)) + { + ret32 |= kENC_WatchdogTimeoutInterruptEnable; + } + if (ENC_CTRL_CMPIE_MASK == (ENC_CTRL_CMPIE_MASK & base->CTRL)) + { + ret32 |= kENC_PositionCompareInerruptEnable; + } + /* ENC_CTRL2. */ + if (ENC_CTRL2_SABIE_MASK == (ENC_CTRL2_SABIE_MASK & base->CTRL2)) + { + ret32 |= kENC_SimultBothPhaseChangeInterruptEnable; + } + if (ENC_CTRL2_ROIE_MASK == (ENC_CTRL2_ROIE_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollOverInterruptEnable; + } + if (ENC_CTRL2_RUIE_MASK == (ENC_CTRL2_RUIE_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollUnderInterruptEnable; + } + return ret32; +} + +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) +{ + base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ + base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ +} + +uint32_t ENC_GetPositionValue(ENC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} + +uint32_t ENC_GetHoldPositionValue(ENC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enc.h new file mode 100644 index 0000000000..64c4f402da --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enc.h @@ -0,0 +1,484 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ENC_H_ +#define _FSL_ENC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup enc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FSL_ENC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! + * @brief Interrupt enable/disable mask. + */ +enum _enc_interrupt_enable +{ + kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ + kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ + kENC_SimultBothPhaseChangeInterruptEnable = + (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ + kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ +}; + +/*! + * @brief Status flag mask. + * + * These flags indicate the counter's events. + */ +enum _enc_status_flags +{ + kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ + kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ + kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ +}; + +/*! + * @brief Signal status flag mask. + * + * These flags indicate the counter's signal. + */ +enum _enc_signal_status_flags +{ + kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ +}; + +/*! + * @brief Define HOME signal's trigger mode. + * + * The ENC would count the trigger from HOME signal line. + */ +typedef enum _enc_home_trigger_mode +{ + kENC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ + kENC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kENC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} enc_home_trigger_mode_t; + +/*! + * @brief Define INDEX signal's trigger mode. + * + * The ENC would count the trigger from INDEX signal line. + */ +typedef enum _enc_index_trigger_mode +{ + kENC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ + kENC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kENC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} enc_index_trigger_mode_t; + +/*! + * @brief Define type for decoder work mode. + * + * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, + * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction + * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 + * means counting down. Otherwise, the direction is reversed. + */ +typedef enum _enc_decoder_work_mode +{ + kENC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ + kENC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the + direction. */ +} enc_decoder_work_mode_t; + +/*! + * @brief Define type for the condition of POSMATCH pulses. + */ +typedef enum _enc_position_match_mode +{ + kENC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the + position counters (POS) and the compare value (COMP). */ + kENC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ +} enc_position_match_mode_t; + +/*! + * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. + */ +typedef enum _enc_revolution_count_condition +{ + kENC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kENC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + counter. */ +} enc_revolution_count_condition_t; + +/*! + * @brief Define type for direction of self test generated signal. + */ +typedef enum _enc_self_test_direction +{ + kENC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ + kENC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ +} enc_self_test_direction_t; + +/*! + * @brief Define user configuration structure for ENC module. + */ +typedef struct _enc_config +{ + /* Basic counter. */ + bool enableReverseDirection; /*!< Enable reverse direction counting. */ + enc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ + + /* Signal detection. */ + enc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ + enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ + bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ + bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. + */ + + /* Watchdog. */ + bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ + uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature + decoder module watchdog timer. This field is only available when + "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ + + /* Filter for PHASEA, PHASEB, INDEX and HOME. */ + uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of + noisy samples causing an incorrect transition to be recognized. The value represent the + number of consecutive samples that must agree prior to the input filter accepting an + input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 + samples. The Available range is 0 - 7.*/ + uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period + is larger than the period of the expected noise. This value represents the + sampling period (in IPBus clock cycles) of the decoder input signals. + The available range is 0 - 255. */ + + /* Position compare. */ + enc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ + uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ + + /* Modulus counting. */ + enc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ + bool enableModuloCountMode; /*!< Enable Modulo Counting. */ + uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when + "enableModuloCountMode" = true. The available value is a 32-bit number. */ + uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ +} enc_config_t; + +/*! + * @brief Define configuration structure for self test module. + * + * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. + * This is a factory test feature. It is also useful to customers' software development and testing. + */ +typedef struct _enc_self_test_config +{ + enc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ + uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ + uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. + The available range is 0 - 31. */ +} enc_self_test_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initialization for the ENC module. + * + * This function is to make the initialization for the ENC module. It should be called firstly before any operation to + * the ENC with the operations like: + * - Enable the clock for ENC module. + * - Configure the ENC's working attributes. + * + * @param base ENC peripheral base address. + * @param config Pointer to configuration structure. See to "enc_config_t". + */ +void ENC_Init(ENC_Type *base, const enc_config_t *config); + +/*! + * @brief De-initialization for the ENC module. + * + * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * the operations like: + * - Disable the clock for ENC module. + * + * @param base ENC peripheral base address. + */ +void ENC_Deinit(ENC_Type *base); + +/*! + * @brief Get an available pre-defined settings for ENC's configuration. + * + * This function initializes the ENC configuration structure with an available settings, the default value are: + * @code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kENC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * @endcode + * @param config Pointer to a variable of configuration structure. See to "enc_config_t". + */ +void ENC_GetDefaultConfig(enc_config_t *config); + +/*! + * @brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * @param base ENC peripheral base address. + */ +void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); + +/*! + * @brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * @param base ENC peripheral base address. + * @param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + */ +void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); + +/*! + * @brief Enable watchdog for ENC module. + * + * @param base ENC peripheral base address + * @param enable Enables or disables the watchdog + */ +void ENC_EnableWatchdog(ENC_Type *base, bool enable); + +/*! + * @brief Set initial position value for ENC module. + * + * @param base ENC peripheral base address + * @param value Positive initial value + */ +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the status flags. + * + * @param base ENC peripheral base address. + * + * @return Mask value of status flags. For available mask, see to "_enc_status_flags". + */ +uint32_t ENC_GetStatusFlags(ENC_Type *base); + +/*! + * @brief Clear the status flags. + * + * @param base ENC peripheral base address. + * @param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + */ +void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask); + +/*! + * @brief Get the signals' real-time status. + * + * @param base ENC peripheral base address. + * + * @return Mask value of signals' real-time status. For available mask, see to "_enc_signal_status_flags" + */ +static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) +{ + return base->IMR; +} +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base ENC peripheral base address. + * @param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask); + +/*! + * @brief Disable the interrupts. + * + * @param base ENC peripheral base address. + * @param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask); + +/*! + * @brief Get the enabled interrupts' flags. + * + * @param base ENC peripheral base address. + * + * @return Mask value of enabled interrupts. + */ +uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); + +/* @} */ + +/*! + * @name Value Operation + * @{ + */ + +/*! + * @brief Get the current position counter's value. + * + * @param base ENC peripheral base address. + * + * @return Current position counter's value. + */ +uint32_t ENC_GetPositionValue(ENC_Type *base); + +/*! + * @brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position counter's value. + */ +uint32_t ENC_GetHoldPositionValue(ENC_Type *base); + +/*! + * @brief Get the position difference counter's value. + * + * @param base ENC peripheral base address. + * + * @return The position difference counter's value. + */ +static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) +{ + return base->POSD; +} + +/*! + * @brief Get the hold position difference counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position difference counter's value. + */ +static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) +{ + return base->POSDH; +} + +/*! + * @brief Get the position revolution counter's value. + * + * @param base ENC peripheral base address. + * + * @return The position revolution counter's value. + */ +static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) +{ + return base->REV; +} +/*! + * @brief Get the hold position revolution counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position revolution counter's value. + */ +static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base) +{ + return base->REVH; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/* + * @} + */ +#endif /* _FSL_ENC_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enet.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enet.c new file mode 100644 index 0000000000..d44b73eb94 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enet.c @@ -0,0 +1,2975 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_enet.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enet" +#endif + +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U +/*! @brief Ethernet mac address length. */ +#define ENET_FRAME_MACLEN 6U +/*! @brief Ethernet VLAN header length. */ +#define ENET_FRAME_VLAN_TAGLEN 4U +/*! @brief MDC frequency. */ +#define ENET_MDC_FREQUENCY 2500000U +/*! @brief NanoSecond in one second. */ +#define ENET_NANOSECOND_ONE_SECOND 1000000000U +/*! @brief Define a common clock cycle delays used for time stamp capture. */ +#ifndef ENET_1588TIME_DELAY_COUNT +#define ENET_1588TIME_DELAY_COUNT 10U +#endif + +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/*! @brief Define the ENET ring/class bumber . */ +enum _enet_ring_number +{ + kENET_Ring0 = 0U, /*!< ENET ring/class 0. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + kENET_Ring1 = 1U, /*!< ENET ring/class 1. */ + kENET_Ring2 = 2U /*!< ENET ring/class 2. */ +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +}; + +/*! @brief Define interrupt IRQ handler. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET Mac configuration. + * @param bufferConfig ENET buffer configuration. + * @param macAddr ENET six-byte mac address. + * @param srcClock_Hz ENET module clock source, normally it's system clock. + */ +static void ENET_SetMacController(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Set ENET handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET configuration stucture pointer. + * @param bufferConfig ENET buffer configuration. + */ +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); +/*! + * @brief Set ENET MAC transmit buffer descriptors. + * + * @param handle The ENET handle pointer. + * @param config The ENET configuration structure. + * @param bufferConfig The ENET buffer configuration. + */ +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); + +/*! + * @brief Set ENET MAC receive buffer descriptors. + * + * @param handle The ENET handle pointer. + * @param config The ENET configuration structure. + * @param bufferConfig The ENET buffer configuration. + */ +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); + +/*! + * @brief Updates the ENET read buffer descriptors. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + */ +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief Activates ENET send for multiple tx rings. + * + * @param base ENET peripheral base address. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * this should be called when the ENET receive required. + */ +static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. + * + * @param data The ENET read data for frame parse. + * @param ptpTsData The ENET PTP message and time-stamp data pointer. + * @param isFastEnabled The fast parse flag. + * - true , Fast processing, only check if this is a PTP message. + * - false, Store the PTP message data after check the PTP message. + */ +static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); + +/*! + * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The new PTP 1588 time-stamp data pointer. + */ +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. + */ +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); + +/*! + * @brief Store the transmit time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + */ +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ptpTimeData The PTP 1588 time-stamp data pointer. + */ +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_AVB +/*! + * @brief Gets the ring index for transmission. + * + * @param base ENET peripheral base address. + * @param data The ENET transmit data. + * @param handle The ENET handle pointer. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * this should be called when the ENET receive required. + */ +static uint8_t ENET_GetTxRingId(ENET_Type *base, uint8_t *data, enet_handle_t *handle); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL}; + +/*! @brief Pointers to enet clocks for each instance. */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to enet transmit IRQ number for each instance. */ +static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS; +/*! @brief Pointers to enet receive IRQ number for each instance. */ +static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Pointers to enet timestamp IRQ number for each instance. */ +static const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! @brief Pointers to enet error IRQ number for each instance. */ +static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS; + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/* ENET ISR for transactional APIs. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +static enet_isr_ring_t s_enetTxIsr; +static enet_isr_ring_t s_enetRxIsr; +#else +static enet_isr_t s_enetTxIsr; +static enet_isr_t s_enetRxIsr; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +static enet_isr_t s_enetErrIsr; +static enet_isr_t s_enetTsIsr; +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_enetBases)); + + return instance; +} + +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + assert(config); + + /* Initializes the MAC configure structure to zero. */ + memset(config, 0, sizeof(enet_config_t)); + + /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + config->miiMode = kENET_RgmiiMode; +#else + config->miiMode = kENET_RmiiMode; +#endif + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + config->ringNum = 1; + + /* Sets the maximum receive frame length. */ + config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +} + +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + /* Checks input parameters. */ + assert(handle); + assert(config); + assert(bufferConfig); + assert(macAddr); + assert(config->ringNum <= FSL_FEATURE_ENET_QUEUE); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ENET_GetInstance(base); + + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset ENET module. */ + ENET_Reset(base); + + /* Initializes the ENET transmit buffer descriptors. */ + ENET_SetTxBufferDescriptors(handle, config, bufferConfig); + + /* Initializes the ENET receive buffer descriptors. */ + ENET_SetRxBufferDescriptors(handle, config, bufferConfig); + + /* Initializes the ENET MAC controller with basic function. */ + ENET_SetMacController(base, handle, config, bufferConfig, macAddr, srcClock_Hz); + + /* Set all buffers or data in handler for data transmit/receive process. */ + ENET_SetHandler(base, handle, config, bufferConfig); +} + +void ENET_Deinit(ENET_Type *base) +{ + /* Disable interrupt. */ + base->EIMR = 0; + + /* Disable ENET. */ + base->ECR &= ~ENET_ECR_ETHEREN_MASK; + + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disables the clock source. */ + CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) +{ + assert(handle); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; +} + +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + uint8_t count; + uint32_t instance = ENET_GetInstance(base); + const enet_buffer_config_t *buffCfg = bufferConfig; + + /* Store transfer parameters in handle pointer. */ + memset(handle, 0, sizeof(enet_handle_t)); + + handle->ringNum = (config->ringNum > FSL_FEATURE_ENET_QUEUE) ? FSL_FEATURE_ENET_QUEUE : config->ringNum; + for (count = 0; count < handle->ringNum; count++) + { + assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); + + handle->rxBdBase[count] = buffCfg->rxBdStartAddrAlign; + handle->rxBdCurrent[count] = buffCfg->rxBdStartAddrAlign; + handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; + handle->txBdBase[count] = buffCfg->txBdStartAddrAlign; + handle->txBdCurrent[count] = buffCfg->txBdStartAddrAlign; + handle->txBuffSizeAlign[count] = buffCfg->txBuffSizeAlign; + buffCfg++; + } + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[instance] = handle; + + /* Set the IRQ handler when the interrupt is enabled. */ + if (config->interrupt & ENET_TX_INTERRUPT) + { + s_enetTxIsr = ENET_TransmitIRQHandler; + EnableIRQ(s_enetTxIrqId[instance]); + } + if (config->interrupt & ENET_RX_INTERRUPT) + { + s_enetRxIsr = ENET_ReceiveIRQHandler; + EnableIRQ(s_enetRxIrqId[instance]); + } + if (config->interrupt & ENET_ERR_INTERRUPT) + { + s_enetErrIsr = ENET_ErrorIRQHandler; + EnableIRQ(s_enetErrIrqId[instance]); + } +} + +static void ENET_SetMacController(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + /* Check the MII mode/speed/duplex setting. */ + if (config->miiSpeed == kENET_MiiSpeed1000M) + { + /* Only RGMII mode has the 1000M bit/s. The 1000M only support full duplex. */ + assert(config->miiMode == kENET_RgmiiMode); + assert(config->miiDuplex == kENET_MiiFullDuplex); + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + uint32_t rcr = 0; + uint32_t tcr = 0; + uint32_t ecr = base->ECR; + uint32_t macSpecialConfig = config->macSpecialConfig; + uint32_t maxFrameLen = config->rxMaxFrameLen; + + /* Maximum frame length check. */ + if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN)) + { + maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN); +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (macSpecialConfig & kENET_ControlSVLANEnable) + { + /* Double vlan tag (SVLAN) supported. */ + maxFrameLen += ENET_FRAME_VLAN_TAGLEN; + } + ecr |= ((macSpecialConfig & kENET_ControlSVLANEnable) ? (ENET_ECR_SVLANEN_MASK | ENET_ECR_SVLANDBL_MASK) : 0) | + ((macSpecialConfig & kENET_ControlVLANUseSecondTag) ? ENET_ECR_VLANUSE2ND_MASK : 0); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + } + + /* Configures MAC receive controller with user configure structure. */ + rcr = ((macSpecialConfig & kENET_ControlRxPayloadCheckEnable) ? ENET_RCR_NLC_MASK : 0) | + ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_CFEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_FCE_MASK : 0) | + ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | + ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; + +/* Set the RGMII or RMII, MII mode and control register. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (config->miiMode == kENET_RgmiiMode) + { + rcr |= ENET_RCR_RGMII_EN_MASK; + rcr &= ~ENET_RCR_MII_MODE_MASK; + } + else + { + rcr &= ~ENET_RCR_RGMII_EN_MASK; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + rcr |= ENET_RCR_MII_MODE_MASK; + if (config->miiMode == kENET_RmiiMode) + { + rcr |= ENET_RCR_RMII_MODE_MASK; + } +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + /* Speed. */ + if (config->miiSpeed == kENET_MiiSpeed10M) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (config->miiSpeed == kENET_MiiSpeed1000M) + { + ecr |= ENET_ECR_SPEED_MASK; + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Receive setting for half duplex. */ + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + } + /* Sets internal loop only for MII mode. */ + if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode != kENET_RmiiMode)) + { + rcr |= ENET_RCR_LOOP_MASK; + rcr &= ~ENET_RCR_DRT_MASK; + } + base->RCR = rcr; + + /* Configures MAC transmit controller: duplex mode, mac address insertion. */ + tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); + tcr |= (config->miiDuplex ? ENET_TCR_FDEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlMacAddrInsert) ? ENET_TCR_ADDINS_MASK : 0); + base->TCR = tcr; + + /* Configures receive and transmit accelerator. */ + base->TACC = config->txAccelerConfig; + base->RACC = config->rxAccelerConfig; + + /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ + if (macSpecialConfig & kENET_ControlFlowControlEnable) + { + uint32_t reemReg; + base->OPD = config->pauseDuration; + reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); +#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + base->RSEM = reemReg; + } + + /* FIFO threshold setting for store and forward enable/disable case. */ + if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) + { + /* Transmit fifo watermark settings. */ + base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; + /* Receive fifo full threshold settings. */ + base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; + } + else + { + /* Transmit fifo watermark settings. */ + base->TFWR = ENET_TFWR_STRFWD_MASK; + base->RSFL = 0; + } + + /* Enable store and forward when accelerator is enabled */ + if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) + { + base->TFWR = ENET_TFWR_STRFWD_MASK; + } + if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) + { + base->RSFL = 0; + } + + /* Initializes the ring 0. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; + base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; +#endif + base->MRBR = bufferConfig->rxBuffSizeAlign; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + const enet_buffer_config_t *buffCfg = bufferConfig; + + if (config->ringNum > 1) + { + /* Initializes the ring 1. */ + buffCfg++; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; + base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; +#endif + base->MRBR1 = buffCfg->rxBuffSizeAlign; + /* Enable the DMAC for ring 1 and with no rx classification set. */ + base->DMACFG[0] = ENET_DMACFG_DMA_CLASS_EN_MASK; + } + if (config->ringNum > 2) + { + /* Initializes the ring 2. */ + buffCfg++; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR2 = (uint32_t)buffCfg->txBdStartAddrAlign; + base->RDSR2 = (uint32_t)buffCfg->rxBdStartAddrAlign; +#endif + base->MRBR2 = buffCfg->rxBuffSizeAlign; + /* Enable the DMAC for ring 2 and with no rx classification set. */ + base->DMACFG[1] = ENET_DMACFG_DMA_CLASS_EN_MASK; + } + + /* Default the class/ring 1 and 2 are not enabled and the receive classification is disabled + * so we set the default transmit scheme with the round-robin mode. beacuse the legacy bd mode + * only support the round-robin mode. if the avb feature is required, just call the setup avb + * feature API. */ + base->QOS |= ENET_QOS_TX_SCHEME(1); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Configures the Mac address. */ + ENET_SetMacAddr(base, macAddr); + + /* Initialize the SMI if uninitialized. */ + if (!ENET_GetSMI(base)) + { + ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); + } + +/* Enables Ethernet interrupt, enables the interrupt coalsecing if it is required. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + if (config->intCoalesceCfg) + { + uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK); + +#if FSL_FEATURE_ENET_QUEUE > 1 + uint8_t queue = 0; + intMask |= ENET_EIMR_TXB2_MASK | ENET_EIMR_RXB2_MASK | ENET_EIMR_TXB1_MASK | ENET_EIMR_RXB1_MASK; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + /* Clear all buffer interrupts. */ + base->EIMR &= ~intMask; + +/* Set the interrupt coalescence. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + for (queue = 0; queue < FSL_FEATURE_ENET_QUEUE; queue++) + { + base->TXIC[queue] = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[queue]) | + config->intCoalesceCfg->txCoalesceTimeCount[queue] | ENET_TXIC_ICCS_MASK | + ENET_TXIC_ICEN_MASK; + base->RXIC[queue] = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[queue]) | + config->intCoalesceCfg->rxCoalesceTimeCount[queue] | ENET_RXIC_ICCS_MASK | + ENET_RXIC_ICEN_MASK; + } +#else + base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) | + config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK; + base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) | + config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + ENET_EnableInterrupts(base, config->interrupt); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Sets the 1588 enhanced feature. */ + ecr |= ENET_ECR_EN1588_MASK; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Enables Ethernet module after all configuration except the buffer descriptor active. */ + ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; + base->ECR = ecr; +} + +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + /* Default single ring is supported. */ + uint8_t ringNum; + uint32_t count; + uint32_t txBuffSizeAlign; + uint8_t *txBuffer; + const enet_buffer_config_t *buffCfg = bufferConfig; + + /* Check the input parameters. */ + for (ringNum = 0; ringNum < config->ringNum; ringNum++) + { + if ((buffCfg->txBdStartAddrAlign > 0) && (buffCfg->txBufferAlign > 0)) + { + volatile enet_tx_bd_struct_t *curBuffDescrip = buffCfg->txBdStartAddrAlign; + txBuffSizeAlign = buffCfg->txBuffSizeAlign; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + txBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBufferAlign, kMEMORY_Local2DMA); +#else + txBuffer = buffCfg->txBufferAlign; +#endif + for (count = 0; count < buffCfg->txBdNumber; count++) + { + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffer[count * txBuffSizeAlign]); + /* Initializes data length. */ + curBuffDescrip->length = 0; + /* Sets the crc. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == buffCfg->txBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Enable transmit interrupt for store the transmit timestamp. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK; +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + /* Set the type of the frame when the credit-based scheme is used. */ + curBuffDescrip->controlExtend1 |= ENET_BD_FTYPE(ringNum); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } + } + buffCfg++; + } +} + +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + /* Default single ring is supported. */ + uint8_t ringNum; + uint32_t count; + uint32_t rxBuffSizeAlign; + uint8_t *rxBuffer; + const enet_buffer_config_t *buffCfg = bufferConfig; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t mask = (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Check the input parameters. */ + for (ringNum = 0; ringNum < config->ringNum; ringNum++) + { + assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#if FSL_FEATURE_ENET_QUEUE > 1 + if (ringNum == 1) + { + mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); + } + else if (ringNum == 2) + { + mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); + } +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + if ((buffCfg->rxBdStartAddrAlign > 0) && (buffCfg->rxBufferAlign > 0)) + { + volatile enet_rx_bd_struct_t *curBuffDescrip = buffCfg->rxBdStartAddrAlign; + rxBuffSizeAlign = buffCfg->rxBuffSizeAlign; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + rxBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBufferAlign, kMEMORY_Local2DMA); +#else + rxBuffer = buffCfg->rxBufferAlign; +#endif + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Invalidate rx buffers before DMA transfer data into them. */ + DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + + for (count = 0; count < buffCfg->rxBdNumber; count++) + { + /* Set data buffer and the length. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffer[count * rxBuffSizeAlign]); + curBuffDescrip->length = 0; + + /* Initializes the buffer descriptors with empty bit. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == buffCfg->rxBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (config->interrupt & mask) + { + /* Enable receive interrupt. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK; + } + else + { + curBuffDescrip->controlExtend1 = 0; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } + } + buffCfg++; + } +} + +static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId) +{ + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + switch (ringId) + { + case kENET_Ring0: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->TDAR1 = ENET_TDAR1_TDAR_MASK; + break; + case kENET_Ring2: + base->TDAR2 = ENET_TDAR2_TDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; + } +} + +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t rcr = base->RCR; + uint32_t tcr = base->TCR; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + uint32_t ecr = base->ECR; + + if (kENET_MiiSpeed1000M == speed) + { + assert(duplex == kENET_MiiFullDuplex); + ecr |= ENET_ECR_SPEED_MASK; + } + else + { + ecr &= ~ENET_ECR_SPEED_MASK; + } + + base->ECR = ecr; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Sets speed mode. */ + if (kENET_MiiSpeed10M == speed) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } + else + { + rcr &= ~ENET_RCR_RMII_10T_MASK; + } + /* Set duplex mode. */ + if (duplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + tcr &= ~ENET_TCR_FDEN_MASK; + } + else + { + rcr &= ~ENET_RCR_DRT_MASK; + tcr |= ENET_TCR_FDEN_MASK; + } + + base->RCR = rcr; + base->TCR = tcr; +} + +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + uint32_t address; + + /* Set physical address lower register. */ + address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | + (uint32_t)macAddr[3]); + base->PALR = address; + /* Set physical address high register. */ + address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); + base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; +} + +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + assert(macAddr); + + uint32_t address; + + /* Get from physical address lower register. */ + address = base->PALR; + macAddr[0] = 0xFFU & (address >> 24U); + macAddr[1] = 0xFFU & (address >> 16U); + macAddr[2] = 0xFFU & (address >> 8U); + macAddr[3] = 0xFFU & address; + + /* Get from physical address high register. */ + address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; +} + +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) +{ + assert(srcClock_Hz); + + uint32_t clkCycle = 0; + uint32_t speed = 0; + uint32_t mscr = 0; + + /* Calculate the MII speed which controls the frequency of the MDC. */ + speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); + /* Calculate the hold time on the MDIO output. */ + clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; + /* Build the configuration for MDC/MDIO control. */ + mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); + base->MSCR = mscr; +} + +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | + (data & 0xFFFF); + base->MMFR = mmfr; +} + +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) +{ + uint32_t mmfr = 0; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); + base->MMFR = mmfr; +} + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); + base->MMFR = mmfr; +} + +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2); + base->MMFR = mmfr; +} +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + assert(eErrorStatic); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[0]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[0]); +} + +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + assert(length); + + /* Reset the length to zero. */ + *length = 0; + + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Add check for abnormal case. */ + if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) + { + return kStatus_ENET_RxFrameError; + } + + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[0]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[0]); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + + uint32_t len = 0; + uint32_t offset = 0; + uint16_t control; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + status_t result = kStatus_Success; + uint32_t address; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Update the control flag. */ + control = handle->rxBdCurrent[0]->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + break; + } + + } while (handle->rxBdCurrent[0] != curBuffDescrip); + + return result; + } + else + { + /* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, (void *)address, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + return result; + } + else + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + } + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + break; + } + + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]); + offset += handle->rxBuffSizeAlign[0]; + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + } + + /* Get the current buffer descriptor. */ + curBuffDescrip = handle->rxBdCurrent[0]; + /* Add the cache invalidate maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + } + } + + return kStatus_ENET_RxFrameFail; +} + +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +{ + assert(handle); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Clears status. */ + handle->rxBdCurrent[ringId]->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + /* Sets the receive buffer descriptor with the empty flag. */ + handle->rxBdCurrent[ringId]->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + + /* Increase current buffer descriptor to the next one. */ + if (handle->rxBdCurrent[ringId]->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent[ringId] = handle->rxBdBase[ringId]; + } + else + { + handle->rxBdCurrent[ringId]++; + } + + /* Actives the receive buffer descriptor. */ + switch (ringId) + { + case kENET_Ring0: + base->RDAR = ENET_RDAR_RDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->RDAR1 = ENET_RDAR1_RDAR_MASK; + break; + case kENET_Ring2: + base->RDAR2 = ENET_RDAR2_RDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->RDAR = ENET_RDAR_RDAR_MASK; + break; + } +} + +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) +{ + assert(handle); + assert(data); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[0]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[0] >= length) + { + /* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (sizeleft > handle->txBuffSizeAlign[0]) + { + /* Data copy. */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[0]; + len += handle->txBuffSizeAlign[0]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + /* Active the transmit buffer descriptor*/ + ENET_ActiveSend(base, 0); + } + else + { + + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[0]; + + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) +{ + assert(handle); + assert(eErrorStatic); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[ringId]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[ringId]); +} + +status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId) +{ + assert(handle); + assert(length); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Reset the length to zero. */ + *length = 0; + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip; + + curBuffDescrip = handle->rxBdCurrent[ringId]; + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Add check for abnormal case. */ + if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) + { + return kStatus_ENET_RxFrameError; + } + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[ringId]; + } + else + { + curBuffDescrip++; + } + } while (curBuffDescrip != handle->rxBdCurrent[ringId]); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +status_t ENET_ReadFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) +{ + assert(handle); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint32_t len = 0; + uint32_t offset = 0; + uint16_t control; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; + status_t result = kStatus_Success; + uint32_t address; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Update the control flag. */ + control = handle->rxBdCurrent[ringId]->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + break; + } + + } while (handle->rxBdCurrent[ringId] != curBuffDescrip); + + return result; + } + else + { + /* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, (void *)address, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + return result; + } + else + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + } + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + break; + } + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); + offset += handle->rxBuffSizeAlign[ringId]; + + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + } + + /* Get the current buffer descriptor. */ + + curBuffDescrip = handle->rxBdCurrent[ringId]; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + } + } + + return kStatus_ENET_RxFrameFail; +} + + +status_t ENET_SendFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) +{ + assert(handle); + assert(data); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[ringId]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[ringId] >= length) + { + /* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data, length); + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdCurrent[ringId]++; + } + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, ringId); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdCurrent[ringId]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (sizeleft > handle->txBuffSizeAlign[ringId]) + { + /* Data copy. */ + memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[ringId]; + len += handle->txBuffSizeAlign[ringId]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + + /* Active the transmit buffer descriptor*/ + ENET_ActiveSend(base, ringId); + } + else + { + + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, ringId); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[ringId]; + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Enable a multicast group address. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } + else + { + base->GAUR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } +} + +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Set the hash table. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } + else + { + base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(eErrorStatic); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic[0]->control; + controlExt = handle->txBdDirtyStatic[0]->controlExtend0; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic[0]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic[0] = handle->txBdBase[0]; + } + else + { + handle->txBdDirtyStatic[0]++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic[0] != handle->txBdCurrent[0]); + + return kStatus_ENET_TxFrameFail; +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) +{ + assert(handle); + assert(eErrorStatic); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic[ringId]->control; + controlExt = handle->txBdDirtyStatic[ringId]->controlExtend0; + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyStatic[ringId]++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic[ringId] != handle->txBdCurrent[ringId]); + + return kStatus_ENET_TxFrameFail; +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) +{ + assert(data); + if (!isFastEnabled) + { + assert(ptpTsData); + } + + bool isPtpMsg = false; + const uint8_t *buffer = data; + uint16_t ptpType; + + /* Check for VLAN frame. + * Add Double vlan tag check for receiving extended QIN vlan frame. */ + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == (ENET_HTONS(ENET_8021QVLAN) +#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB + || ENET_HTONS(ENET_8021QSVLAN) +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + )) + { + buffer += ENET_FRAME_VLAN_TAGLEN; +#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) + { + buffer += ENET_FRAME_VLAN_TAGLEN; + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + } + + ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); + switch (ENET_HTONS(ptpType)) + { /* Ethernet layer 2. */ + case ENET_ETHERNETL2: + if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType) + { + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a ptpv2 message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), + kENET_PtpSrcPortIdLen); + } + } + break; + /* IPV4. */ + case ENET_IPV4: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV4 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + /* IPV6. */ + case ENET_IPV6: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV6 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + default: + break; + } + return isPtpMsg; +} + +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) +{ + assert(handle); + assert(ptpConfig); + uint8_t count; + + uint32_t instance = ENET_GetInstance(base); + uint32_t mask = kENET_TxBufferInterrupt; +#if FSL_FEATURE_ENET_QUEUE > 1 + mask |= kENET_TxBuffer1Interrupt | kENET_TxBuffer2Interrupt; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + /* Start the 1588 timer. */ + ENET_Ptp1588StartTimer(base, ptpConfig->ptp1588ClockSrc_Hz); + + for (count = 0; count < handle->ringNum; count++) + { + handle->txBdDirtyTime[count] = handle->txBdBase[count]; + handle->txBdDirtyStatic[count] = handle->txBdBase[count]; + } + + /* Setting the receive and transmit state for transaction. */ + handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData; + handle->rxPtpTsDataRing.size = ptpConfig->ptpTsRxBuffNum; + handle->rxPtpTsDataRing.front = 0; + handle->rxPtpTsDataRing.end = 0; + handle->txPtpTsDataRing.ptpTsData = ptpConfig->txPtpTsData; + handle->txPtpTsDataRing.size = ptpConfig->ptpTsTxBuffNum; + handle->txPtpTsDataRing.front = 0; + handle->txPtpTsDataRing.end = 0; + handle->msTimerSecond = 0; + + /* Set the IRQ handler when the interrupt is enabled. */ + s_enetTxIsr = ENET_TransmitIRQHandler; + s_enetTsIsr = ENET_Ptp1588TimerIRQHandler; + + /* Enables the time stamp interrupt and transmit frame interrupt to + * handle the time-stamp . */ + ENET_EnableInterrupts(base, (ENET_TS_INTERRUPT | ENET_TX_INTERRUPT)); + ENET_DisableInterrupts(base, mask); + + EnableIRQ(s_enetTsIrqId[instance]); + EnableIRQ(s_enetTxIrqId[instance]); +} + +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) +{ + /* Restart PTP 1588 timer, master clock. */ + base->ATCR = ENET_ATCR_RESTART_MASK; + + /* Initializes PTP 1588 timer. */ + base->ATINC = ENET_ATINC_INC(ENET_NANOSECOND_ONE_SECOND / ptpClkSrc); + base->ATPER = ENET_NANOSECOND_ONE_SECOND; + /* Sets periodical event and the event signal output assertion and Actives PTP 1588 timer. */ + base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; +} + +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + uint16_t count = ENET_1588TIME_DELAY_COUNT; + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get the current PTP time. */ + ptpTime->second = handle->msTimerSecond; + /* Get the nanosecond from the master timer. */ + base->ATCR |= ENET_ATCR_CAPTURE_MASK; + /* Add at least six clock cycle delay to get accurate time. + It's the requirement when the 1588 clock source is slower + than the register clock. + */ + while (count--) + { + __NOP(); + } + /* Get the captured time. */ + ptpTime->nanosecond = base->ATVR; + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Sets PTP timer. */ + handle->msTimerSecond = ptpTime->second; + base->ATVR = ptpTime->nanosecond; + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) +{ + /* Set correction for PTP timer increment. */ + base->ATINC = (base->ATINC & ~ENET_ATINC_INC_CORR_MASK) | (corrIncrease << ENET_ATINC_INC_CORR_SHIFT); + /* Set correction for PTP timer period. */ + base->ATCOR = (base->ATCOR & ~ENET_ATCOR_COR_MASK) | (corrPeriod << ENET_ATCOR_COR_SHIFT); +} + +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimeData); + + uint16_t usedBuffer = 0; + + /* Check if the buffers ring is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == ptpTsDataRing->size) + { + return kStatus_ENET_PtpTsRingFull; + } + + /* Copy the new data into the buffer. */ + memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); + + /* Increase the buffer pointer to the next empty one. */ + ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; + + return kStatus_Success; +} + +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimedata); + + uint32_t index; + uint32_t size; + uint16_t usedBuffer = 0; + + /* Check the PTP 1588 timestamp ring. */ + if (ptpTsDataRing->front == ptpTsDataRing->end) + { + return kStatus_ENET_PtpTsRingEmpty; + } + + /* Search the element in the ring buffer */ + index = ptpTsDataRing->front; + size = ptpTsDataRing->size; + while (index != ptpTsDataRing->end) + { + if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && + (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && + ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && + ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) + { + break; + } + + /* Increase the ptp ring index. */ + index = (index + 1) % size; + } + + if (index == ptpTsDataRing->end) + { + /* Check if buffers is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == ptpTsDataRing->size) + { /* Drop one in the front. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; + } + return kStatus_ENET_PtpTsRingFull; + } + + /* Get the right timestamp of the required ptp messag. */ + ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; + ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; + + /* Increase the index. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; + + return kStatus_Success; +} + +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + bool ptpTimerWrap = false; + enet_ptp_time_t ptpTimer; + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimer); + + /* Get PTP timer wrap event. */ + ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt; + + /* Get transmit time stamp second. */ + if ((ptpTimer.nanosecond > ptpTimeData->timeStamp.nanosecond) || + ((ptpTimer.nanosecond < ptpTimeData->timeStamp.nanosecond) && ptpTimerWrap)) + { + ptpTimeData->timeStamp.second = handle->msTimerSecond; + } + else + { + ptpTimeData->timeStamp.second = handle->msTimerSecond - 1; + } + /* Enable the interrupt. */ + EnableGlobalIRQ(primask); + + /* Store the timestamp to the receive time stamp ring. */ + /* Check if the buffers ring is full. */ + return ENET_Ptp1588UpdateTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +{ + assert(handle); + + uint32_t primask; + bool ptpTimerWrap; + bool isPtpEventMessage = false; + enet_ptp_time_data_t ptpTimeData; + volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdDirtyTime[ringId]; + uint32_t address; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + + /* Parse the PTP message. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); + if (isPtpEventMessage) + { + /* Only store tx timestamp for ptp event message. */ + do + { + /* Increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + + /* Do time stamp check on the last buffer descriptor of the frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimeData.timeStamp); + + /* Get PTP timer wrap event. */ + ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt; + + /* Get transmit time stamp second. */ + if ((ptpTimeData.timeStamp.nanosecond > curBuffDescrip->timestamp) || + ((ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp) && ptpTimerWrap)) + { + ptpTimeData.timeStamp.second = handle->msTimerSecond; + } + else + { + ptpTimeData.timeStamp.second = handle->msTimerSecond - 1; + } + + /* Save transmit time stamp nanosecond. */ + ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp; + + /* Enable the interrupt. */ + EnableGlobalIRQ(primask); + + /* Store the timestamp to the transmit timestamp ring. */ + return ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData); + } + + /* Get the current transmit buffer descriptor. */ + curBuffDescrip = handle->txBdDirtyTime[ringId]; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + } while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]); + return kStatus_ENET_TxFrameFail; + } + else + { + /* Only increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + } + return kStatus_Success; +} + +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); +} + +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config) +{ + assert(config); + + uint8_t count = 0; + + for (count = 0; count < FSL_FEATURE_ENET_QUEUE - 1; count++) + { + /* Set the AVB receive ring classification match when the match is not 0. */ + if (config->rxClassifyMatch[count]) + { + base->RCMR[count] = (config->rxClassifyMatch[count] & 0xFFFF) | ENET_RCMR_MATCHEN_MASK; + } + /* Set the dma controller for the extended ring. */ + base->DMACFG[count] |= ENET_DMACFG_IDLE_SLOPE(config->idleSlope[count]); + } + + /* Shall use the credit-based scheme for avb. */ + base->QOS &= ~ENET_QOS_TX_SCHEME_MASK; + base->QOS |= ENET_QOS_RX_FLUSH0_MASK; +} +#endif /* FSL_FETAURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if FSL_FEATURE_ENET_QUEUE > 1 +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +#else +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +{ + assert(handle); + uint32_t mask = kENET_TxBufferInterrupt | kENET_TxFrameInterrupt; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) || (FSL_FEATURE_ENET_QUEUE > 1) + uint32_t index = 0; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTORMODE || (FSL_FEATURE_ENET_QUEUE > 1) */ + +/* Check if the transmit interrupt happen. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + switch (ringId) + { + case kENET_Ring1: + mask = (kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt); + break; + case kENET_Ring2: + mask = (kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt); + break; + default: + break; + } + index = ringId; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + while (mask & base->EIR) + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (base->EIR & kENET_TxFrameInterrupt) + { + /* Store the transmit timestamp from the buffer descriptor should be done here. */ + ENET_StoreTxFrameTime(base, handle, index); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Clear the transmit interrupt event. */ + base->EIR = mask; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, index, kENET_TxEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TxEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +#else +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +{ + assert(handle); + uint32_t mask = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt; + +/* Check if the receive interrupt happen. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + switch (ringId) + { + case kENET_Ring1: + mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); + break; + case kENET_Ring2: + mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); + break; + default: + break; + } +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + while (mask & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = mask; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, ringId, kENET_RxEvent, handle->userData); +#else + handle->callback(base, handle, kENET_RxEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +} + +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; + + /* Check if the error interrupt happen. */ + if (kENET_WakeupInterrupt & base->EIR) + { + /* Clear the wakeup interrupt. */ + base->EIR = kENET_WakeupInterrupt; + /* wake up and enter the normal mode. */ + ENET_EnableSleepMode(base, false); + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_WakeUpEvent, handle->userData); +#else + handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + else + { + /* Clear the error interrupt event status. */ + errMask &= base->EIR; + base->EIR = errMask; + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_ErrEvent, handle->userData); +#else + handle->callback(base, handle, kENET_ErrEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + /* Check if the PTP time stamp interrupt happen. */ + if (kENET_TsTimerInterrupt & base->EIR) + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsTimerInterrupt; + + /* Increase timer second counter. */ + handle->msTimerSecond++; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_TimeStampEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TimeStampEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + else + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsAvailInterrupt; + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_TimeStampAvailEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TimeStampAvailEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +void ENET_CommonFrame0IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBufferInterrupt | kENET_TxFrameInterrupt)) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + s_enetTxIsr(base, s_ENETHandle[instance], 0); +#else + s_enetTxIsr(base, s_ENETHandle[instance]); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + + if (event & (kENET_RxBufferInterrupt | kENET_RxFrameInterrupt)) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + s_enetRxIsr(base, s_ENETHandle[instance], 0); +#else + s_enetRxIsr(base, s_ENETHandle[instance]); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + + if (event & ENET_TS_INTERRUPT) + { + s_enetTsIsr(base, s_ENETHandle[instance]); + } + if (event & ENET_ERR_INTERRUPT) + { + s_enetErrIsr(base, s_ENETHandle[instance]); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +void ENET_CommonFrame1IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBuffer1Interrupt | kENET_TxFrame1Interrupt)) + { + s_enetTxIsr(base, s_ENETHandle[instance], 1); + } + + if (event & (kENET_RxBuffer1Interrupt | kENET_RxFrame1Interrupt)) + { + s_enetRxIsr(base, s_ENETHandle[instance], 1); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_CommonFrame2IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBuffer2Interrupt | kENET_TxFrame2Interrupt)) + { + s_enetTxIsr(base, s_ENETHandle[instance], 2); + } + + if (event & (kENET_RxBuffer2Interrupt | kENET_RxFrame2Interrupt)) + { + s_enetRxIsr(base, s_ENETHandle[instance], 2); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +#if defined(ENET) +void ENET_Transmit_IRQHandler(void) +{ + s_enetTxIsr(ENET, s_ENETHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_Receive_IRQHandler(void) +{ + s_enetRxIsr(ENET, s_ENETHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_Error_IRQHandler(void) +{ + s_enetErrIsr(ENET, s_ENETHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_1588_Timer_IRQHandler(void) +{ + s_enetTsIsr(ENET, s_ENETHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif + + +#if defined(ENET1) +void ENET1_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ENET2) +void ENET2_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET2); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + + +#if defined(CONNECTIVITY__ENET0) +void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#if FSL_FEATURE_ENET_QUEUE > 1 +void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#if defined(CONNECTIVITY__ENET1) +void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#if FSL_FEATURE_ENET_QUEUE > 1 +void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enet.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enet.h new file mode 100644 index 0000000000..3538bca2f2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_enet.h @@ -0,0 +1,1635 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#include "fsl_memory.h" +#endif +/*! + * @addtogroup enet + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */ +/*@}*/ + +/*! @name ENET DESCRIPTOR QUEUE */ +/*@{*/ +/*! @brief Defines the queue number. */ +#ifndef FSL_FEATURE_ENET_QUEUE +#define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */ +#endif +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ +#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ +#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ +#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ +/*@}*/ + +/* Extended control regions for enhanced buffer descriptors. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @name First extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ +/*@}*/ + +/*! @name First extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +#define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U /*!< Use the transmit launch time. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U /*!< Frame type mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U /*!< Frame type shift. */ +#define ENET_BD_FTYPE(n) ((n << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK) +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +/*@}*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive error status flag mask. */ +#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ + ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) +#endif + +/*! @name Defines some Ethernet parameters. */ +/*@{*/ +#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size. */ + +#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ +#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ +#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) +#if FSL_FEATURE_ENET_QUEUE > 1 +#define ENET_TX_INTERRUPT \ + (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt | kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt | \ + kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt) +#define ENET_RX_INTERRUPT \ + (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt | kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt | \ + kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt) +#else +#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt) +#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt) +#define ENET_ERR_INTERRUPT \ + (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ + kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) +#define ENET_ERR_INTERRUPT \ + (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ + kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) +/*@}*/ + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Tx frame over length. */ + kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Tx buffer descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit frame fail. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/*! @brief Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode +{ + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode = 1U, /*!< RMII mode for data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_RgmiiMode = 2U /*!< RGMII mode for data interface. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_mii_mode_t; + +/*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. + * + * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". + */ +typedef enum _enet_mii_speed +{ + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_MiiSpeed1000M = 2U /*!< Speed 1000M bps. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex +{ + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ +typedef enum _enet_mii_write +{ + kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ + kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ +} enet_mii_write_t; + +/*! @brief Defines the read operation for the MII management frame. */ +typedef enum _enet_mii_read +{ + kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ + kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ +} enet_mii_read_t; + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ +typedef enum _enet_mii_extend_opcode +{ + kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ + kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ + kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ +} enet_mii_extend_opcode; +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! @brief Defines a special configuration for ENET MAC controller. + * + * These control flags are provided for special user requirements. + * Normally, these control flags are unused for ENET initialization. + * For special requirements, set the flags to + * macSpecialConfig in the enet_config_t. + * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store + * and forward. FIFO store and forward means that the FIFO read/send is started + * when a complete frame is stored in TX/RX FIFO. If this flag is set, + * configure rxFifoFullThreshold and txFifoWatermark + * in the enet_config_t. + */ +typedef enum _enet_special_control_flag +{ + kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ + kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ + kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ + kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ + kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ + kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ + kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ + kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ + kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ + kENET_ControlVLANTagEnable = 0x0200U, /*!< Enable normal VLAN (single vlan tag). */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_ControlSVLANEnable = 0x0400U, /*!< Enable S-VLAN. */ + kENET_ControlVLANUseSecondTag = 0x0800U /*!< Enable extracting the second vlan tag for further processing. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_special_control_flag_t; + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _enet_interrupt_enable +{ + kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ + kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ + kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ + kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ + kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ + kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ + kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ + kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ + kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ + kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ + kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ + kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ + kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive error interrupt source */ + kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ +#if FSL_FEATURE_ENET_QUEUE > 1 + kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK, /*!< Rx DMA ring2 flush indication. */ + kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK, /*!< Rx DMA ring1 flush indication. */ + kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK, /*!< RX DMA ring0 flush indication. */ + kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK, /*!< Tx frame interrupt for Tx ring/class 2. */ + kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK, /*!< Tx buffer interrupt for Tx ring/class 2. */ + kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK, /*!< Rx frame interrupt for Rx ring/class 2. */ + kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK, /*!< Rx buffer interrupt for Rx ring/class 2. */ + kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK, /*!< Tx frame interrupt for Tx ring/class 1. */ + kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK, /*!< Tx buffer interrupt for Tx ring/class 1. */ + kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK, /*!< Rx frame interrupt for Rx ring/class 1. */ + kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK, /*!< Rx buffer interrupt for Rx ring/class 1. */ +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ + kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ +} enet_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event +{ + kENET_RxEvent, /*!< Receive event. */ + kENET_TxEvent, /*!< Transmit event. */ + kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ + kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ + kENET_TimeStampEvent, /*!< Time stamp event. */ + kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ +} enet_event_t; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! @brief Defines certain idle slope for bandwidth fraction. */ +typedef enum _enet_idle_slope +{ + kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ + kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ + kENET_IdleSlope4 = 4U, /*!< The bandwidth fraction is about 0.008. */ + kENET_IdleSlope8 = 8U, /*!< The bandwidth fraction is about 0.02. */ + kENET_IdleSlope16 = 16U, /*!< The bandwidth fraction is about 0.03. */ + kENET_IdleSlope32 = 32U, /*!< The bandwidth fraction is about 0.06. */ + kENET_IdleSlope64 = 64U, /*!< The bandwidth fraction is about 0.11. */ + kENET_IdleSlope128 = 128U, /*!< The bandwidth fraction is about 0.20. */ + kENET_IdleSlope256 = 256U, /*!< The bandwidth fraction is about 0.33. */ + kENET_IdleSlope384 = 384U, /*!< The bandwidth fraction is about 0.43. */ + kENET_IdleSlope512 = 512U, /*!< The bandwidth fraction is about 0.50. */ + kENET_IdleSlope640 = 640U, /*!< The bandwidth fraction is about 0.56. */ + kENET_IdleSlope768 = 768U, /*!< The bandwidth fraction is about 0.60. */ + kENET_IdleSlope896 = 896U, /*!< The bandwidth fraction is about 0.64. */ + kENET_IdleSlope1024 = 1024U, /*!< The bandwidth fraction is about 0.67. */ + kENET_IdleSlope1152 = 1152U, /*!< The bandwidth fraction is about 0.69. */ + kENET_IdleSlope1280 = 1280U, /*!< The bandwidth fraction is about 0.71. */ + kENET_IdleSlope1408 = 1408U, /*!< The bandwidth fraction is about 0.73. */ + kENET_IdleSlope1536 = 1536U /*!< The bandwidth fraction is about 0.75. */ +} enet_idle_slope_t; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + +/*! @brief Defines the transmit accelerator configuration. */ +typedef enum _enet_tx_accelerator +{ + kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ + kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ + kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ +} enet_tx_accelerator_t; + +/*! @brief Defines the receive accelerator configuration. */ +typedef enum _enet_rx_accelerator +{ + kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ + kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ + kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ + kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ + kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ +} enet_rx_accelerator_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type +{ + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ +typedef enum _enet_ptp_timer_channel +{ + kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ + kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ + kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ + kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ +} enet_ptp_timer_channel_t; + +/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ +typedef enum _enet_ptp_timer_channel_mode +{ + kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ + kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ + kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ + kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ + kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ + kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ + kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ + kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ + kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ + kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ + kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ + kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ +} enet_ptp_timer_channel_mode_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ +typedef struct _enet_rx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t payloadCheckSum; /*!< Internal payload checksum. */ + uint8_t headerLength; /*!< Header length. */ + uint8_t protocolTyte; /*!< Protocol type. */ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ +typedef struct _enet_tx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + int8_t *txLaunchTime; /*!< Transmit launch time. */ +#else + uint16_t reserved0; + uint16_t reserved1; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + uint16_t reserved2; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved3; + uint16_t reserved4; + uint16_t reserved5; + uint16_t reserved6; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_tx_bd_struct_t; + +/*! @brief Defines the ENET data error statistic structure. */ +typedef struct _enet_data_error_stats +{ + uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ + uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ + uint32_t statsRxFcsErr; /*!< Receive CRC error. */ + uint32_t statsRxOverRunErr; /*!< Receive over run. */ + uint32_t statsRxTruncateErr; /*!< Receive truncate. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ + uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ + uint32_t statsRxMacErr; /*!< Receive Mac error. */ + uint32_t statsRxPhyErr; /*!< Receive PHY error. */ + uint32_t statsRxCollisionErr; /*!< Receive collision. */ + uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ + uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ + uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ + uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ + uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ + uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ + uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_data_error_stats_t; + +/*! @brief Defines the receive buffer descriptor configuration structure. + * + * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. + * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + * 2. The aligned transmit and receive buffer descriptor start address must be at + * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. + * buffer descriptors should be put in non-cacheable region when cache is enabled. + * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. + * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". + * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + */ +typedef struct _enet_buffer_config +{ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t + *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ + volatile enet_tx_bd_struct_t + *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ +} enet_buffer_config_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configuration structure. */ +typedef struct _enet_ptp_config +{ + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ + enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ + uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ +} enet_ptp_config_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE +/*! @brief Defines the interrupt coalescing configure structure. */ +typedef struct _enet_intcoalesce_config +{ + uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ + uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ + uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ + uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ +} enet_intcoalesce_config_t; +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! @brief Defines the ENET AVB Configure structure. + * + * This is used for to configure the extended ring 1 and ring 2. + * 1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. + * composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel. + * + * If CMP1,2,3 are not unused, please set them to the same value as CMP0. + * 2. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). + * For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75. + */ +typedef struct _enet_avb_config +{ + uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The classification match value for the ring. */ + enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The idle slope for certian bandwidth fraction. */ +} enet_avb_config_t; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. macSpecialConfig is used for a special control configuration, A logical OR of + * "enet_special_control_flag_t". For a special configuration for MAC, + * set this parameter to 0. + * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: + * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. + * 2 - 128 bytes written to TX FIFO .... + * 3 - 192 bytes written to TX FIFO .... + * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... + * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 + * or for larger bus access latency 3 or larger due to contention for the system bus. + * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. + * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. + * If the end of the frame is stored in FIFO and the frame size if smaller than the + * txWatermark, the frame is still transmitted. The rule is the + * same for rxFifoFullThreshold in the receive direction. + * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure + * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold + * are set for flow control enabled case. + * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure + * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. + * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator + * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are + * recommended to be used to enable the transmit and receive accelerator. + * After the accelerators are enabled, the store and forward feature should be enabled. + * As a result, kENET_ControlStoreAndFwdDisabled should not be set. + * 7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading. + */ +typedef struct _enet_config +{ + uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ + uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ + uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, + it makes MAC generate XOFF pause frame. */ +#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, + independent of size, that can be accept. If the limit is reached, reception + continues and a pause frame is triggered. */ +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify + the MAC receive ready status. */ + uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO + before a frame transmit start. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + enet_intcoalesce_config_t + *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set + to NULL. */ +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +typedef void (*enet_callback_t)( + ENET_Type *base, enet_handle_t *handle, uint32_t ringId, enet_event_t event, void *userData); +#else +typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + volatile enet_rx_bd_struct_t + *rxBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer descriptor base address pointer. */ + volatile enet_rx_bd_struct_t + *rxBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available receive buffer descriptor pointer. */ + volatile enet_tx_bd_struct_t + *txBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer descriptor base address pointer. */ + volatile enet_tx_bd_struct_t + *txBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available transmit buffer descriptor pointer. */ + uint32_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ + uint32_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer size alignment. */ + uint8_t ringNum; /*!< Number of used rings. */ + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + volatile enet_tx_bd_struct_t + *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for error static update. */ + volatile enet_tx_bd_struct_t + *txBdDirtyTime[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for time stamp update. */ + uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * @param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * @param srcClock_Hz The internal module clock source for MII clock. + * + * @note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Resets the ENET module. + * + * This function restores the ENET module to reset state. + * Note that this function sets all registers to + * reset state. As a result, the ENET module can't work after calling this function. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Reset(ENET_Type *base) +{ + base->ECR |= ENET_ECR_RESET_MASK; +} + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); + +/*! + * @brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * @param base ENET peripheral base address. + * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * @param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); + +/*! + * @brief Gets the ENET SMI- MII management interface configuration. + * + * This API is used to get the SMI configuration to check whether the MII management + * interface has been set. + * + * @param base ENET peripheral base address. + * @return The SMI setup status true or false. + */ +static inline bool ENET_GetSMI(ENET_Type *base) +{ + return (0 != (base->MSCR & 0x7E)); +} + +/*! + * @brief Reads data from the PHY register through an SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); +} + +/*! + * @brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. Range from 0 ~ 31. + * @param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. Range from 0 ~ 31. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); + +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * @param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * @brief Control the usage of the delayed tx/rx RGMII clock. + * + * @param base ENET peripheral base address. + * @param txEnabled Enable or disable to generate the delayed version of RGMII_TXC. + * @param rxEnabled Enable or disable to use the delayed version of RGMII_RXC. + */ + +static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled) +{ + uint32_t ecrReg = base->ECR; + + /* Set for transmit clock delay. */ + if (txEnabled) + { + ecrReg |= ENET_ECR_TXC_DLY_MASK; + } + else + { + ecrReg &= ~ENET_ECR_TXC_DLY_MASK; + } + + /* Set for receive clock delay. */ + if (rxEnabled) + { + ecrReg |= ENET_ECR_RXC_DLY_MASK; + } + else + { + ecrReg &= ~ENET_ECR_RXC_DLY_MASK; + } +} +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + /* @} */ + +/*! + * @name MAC Address Filter + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Adds the ENET device to a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); + +/*! + * @brief Moves the ENET device from a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); + +/* @} */ + +/*! + * @name Other basic operation + * @{ + */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * @brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config The ENET AVB feature configuration structure. + */ +void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Activates ENET read or receive. + * + * This function is to active the enet read process. It is + * used for single descriptor ring/queue. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveRead(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * @brief Activates ENET read or receive for multiple-queue/ring. + * + * This function is to active the enet read process. It is + * used for extended multiple descriptor rings/queues. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveReadMultiRing(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; + base->RDAR1 = ENET_RDAR1_RDAR_MASK; + base->RDAR2 = ENET_RDAR2_RDAR_MASK; +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * @brief Enables/disables the MAC to enter sleep mode. + * This function is used to set the MAC enter sleep mode. + * When entering sleep mode, the magic frame wakeup interrupt should be enabled + * to wake up MAC from the sleep mode and reset it to normal mode. + * + * @param base ENET peripheral base address. + * @param enable True enable sleep mode, false disable sleep mode. + */ +static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) +{ + if (enable) + { + /* When this field is set, MAC enters sleep mode. */ + base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; + } + else + { /* MAC exits sleep mode. */ + base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); + } +} + +/*! + * @brief Gets ENET transmit and receive accelerator functions from MAC controller. + * + * @param base ENET peripheral base address. + * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + */ +static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) +{ + assert(txAccelOption); + assert(txAccelOption); + + *txAccelOption = base->TACC; + *rxAccelOption = base->RACC; +} + +/* @} */ + +/*! + * @name Interrupts. + * @{ + */ + +/*! + * @brief Enables the ENET interrupt. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR |= mask; +} + +/*! + * @brief Disables the ENET interrupt. + * + * This function disables the ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR &= ~mask; +} + +/*! + * @brief Gets the ENET interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_interrupt_enable_t. + */ +static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) +{ + return base->EIR; +} + +/*! + * @brief Clears the ENET interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) +{ + base->EIR = mask; +} +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * @param handle ENET handler pointer. Should be provided by application. + * @param callback The ENET callback function. + * @param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); + +/*! + * @brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * @code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! +* @brief Gets the size of the read frame for single ring. +* +* This function gets a received frame size from the ENET buffer descriptors. +* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". +* +* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* @param length The length of the valid frame received. +* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. +* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data +* and NULL length to update the receive buffers. +* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); + +/*! + * @brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * @code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); + +/*! + * @brief Transmits an ENET frame for single ring. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length); + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * @brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ +void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId); + +/*! + * @brief Transmits an ENET frame for extended multi-ring. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @param ringId The ring index for transmission. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @param ringId The ring index. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! +* @brief Gets the size of the read frame for extended mutli-ring. +* +* This function gets a received frame size from the ENET buffer descriptors. +* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is +* the same to the single ring, refer to ENET_GetRxFrameSize. +* +* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* @param length The length of the valid frame received. +* @param ringId The ring index or ring number; +* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. +* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data +* and NULL length to update the receive buffers. +* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ +status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId); + +/*! + * @brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @param ringId The ring index or ring number; + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); + +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + * @param ringId The ring id or ring number. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + * @param ringId The ring id or ring number. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame1IRQHandler(ENET_Type *base); + +/*! + * @brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame2IRQHandler(ENET_Type *base); +#else +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * @brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base); +/* @} */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @name ENET PTP 1588 function operation + * @{ + */ + +/*! + * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Stops the ENET PTP 1588 Timer. + * This function is used to stops the ENET PTP timer. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Ptp1588StopTimer(ENET_Type *base) +{ + /* Disable PTP timer and reset the timer. */ + base->ATCR &= ~ENET_ATCR_EN_MASK; + base->ATCR |= ENET_ATCR_RESTART_MASK; +} + +/*! + * @brief Adjusts the ENET PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); + +/*! + * @brief Sets the ENET PTP 1588 timer channel mode. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, + enet_ptp_timer_channel_t channel, + enet_ptp_timer_channel_mode_t mode, + bool intEnable) +{ + uint32_t tcrReg = 0; + + tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0); + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} + +#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL +/*! + * @brief Sets ENET PTP 1588 timer channel mode pulse width. + * + * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare + * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. + * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. + * so call this function if you need to set the timer channel mode for + * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare + * with pulse width more than one 1588 clock, + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param isOutputLow True --- timer channel is configured for output compare + * pulse output low. + * false --- timer channel is configured for output compare + * pulse output high. + * @param pulseWidth The pulse width control value, range from 0 ~ 31. + * 0 --- pulse width is one 1588 clock cycle. + * 31 --- pulse width is thirty two 1588 clock cycles. + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelOutputPulseWidth( + ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable) +{ + uint32_t tcrReg; + + tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); + + if (isOutputLow) + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); + } + else + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); + } + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} +#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ + +/*! + * @brief Sets the ENET PTP 1588 timer channel comparison value. + * + * @param base ENET peripheral base address. + * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". + * @param cmpValue The compare value for the compare setting. + */ +static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) +{ + base->CHANNEL[channel].TCCR = cmpValue; +} + +/*! + * @brief Gets the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + * @return True or false, Compare or capture operation status + */ +static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); +} + +/*! + * @brief Clears the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + */ +static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; + base->TGSR = (1U << channel); +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief Sets the ENET PTP 1588 timer to the assigned time. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief The IEEE 1588 PTP time stamp interrupt handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_ewm.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_ewm.c new file mode 100644 index 0000000000..bbc49d62e7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_ewm.c @@ -0,0 +1,112 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ewm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ewm" +#endif + + +/******************************************************************************* + * Code + ******************************************************************************/ + +void EWM_Init(EWM_Type *base, const ewm_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif + value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | + EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + base->CLKPRESCALER = config->prescaler; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + base->CLKCTRL = config->clockSource; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ + + base->CMPL = config->compareLowValue; + base->CMPH = config->compareHighValue; + base->CTRL = value; +} + +void EWM_Deinit(EWM_Type *base) +{ + EWM_DisableInterrupts(base, kEWM_InterruptEnable); +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ +} + +void EWM_GetDefaultConfig(ewm_config_t *config) +{ + assert(config); + + config->enableEwm = true; + config->enableEwmInput = false; + config->setInputAssertLogic = false; + config->enableInterrupt = false; +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + config->clockSource = kEWM_LpoClockSource0; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + config->prescaler = 0U; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + config->compareLowValue = 0U; + config->compareHighValue = 0xFEU; +} + +void EWM_Refresh(EWM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; + EnableGlobalIRQ(primaskValue); +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_ewm.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_ewm.h new file mode 100644 index 0000000000..55ab66af95 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_ewm.h @@ -0,0 +1,245 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_EWM_H_ +#define _FSL_EWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ewm + * @{ + */ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EWM driver version 2.0.1. */ +#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Describes EWM clock source. */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT +typedef enum _ewm_lpo_clock_source +{ + kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ + kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ + kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ + kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ +} ewm_lpo_clock_source_t; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ + +/*! +* @brief Data structure for EWM configuration. +* +* This structure is used to configure the EWM. +*/ +typedef struct _ewm_config +{ + bool enableEwm; /*!< Enable EWM module */ + bool enableEwmInput; /*!< Enable EWM_in input */ + bool setInputAssertLogic; /*!< EWM_in signal assertion state */ + bool enableInterrupt; /*!< Enable EWM interrupt */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t prescaler; /*!< Clock prescaler value */ +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + uint8_t compareLowValue; /*!< Compare low-register value */ + uint8_t compareHighValue; /*!< Compare high-register value */ +} ewm_config_t; + +/*! + * @brief EWM interrupt configuration structure with default settings all disabled. + * + * This structure contains the settings for all of EWM interrupt configurations. + */ +enum _ewm_interrupt_enable_t +{ + kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/ +}; + +/*! + * @brief EWM status flags. + * + * This structure contains the constants for the EWM status flags for use in the EWM functions. + */ +enum _ewm_status_flags_t +{ + kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name EWM initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * @code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * @endcode + * + * @param base EWM peripheral base address + * @param config The configuration of the EWM +*/ +void EWM_Init(EWM_Type *base, const ewm_config_t *config); + +/*! + * @brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * @param base EWM peripheral base address +*/ +void EWM_Deinit(EWM_Type *base); + +/*! + * @brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * @code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * @endcode + * + * @param config Pointer to the EWM configuration structure. + * @see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config); + +/* @} */ + +/*! + * @name EWM functional Operation + * @{ + */ + +/*! + * @brief Enables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL |= mask; +} + +/*! + * @brief Disables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL &= ~mask; +} + +/*! + * @brief Gets all status flags. + * + * This function gets all status flags. + * + * This is an example for getting the running flag. + * @code + * uint32_t status; + * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; + * @endcode + * @param base EWM peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t + * - True: a related status flag has been set. + * - False: a related status flag is not set. + */ +static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) +{ + return (base->CTRL & EWM_CTRL_EWMEN_MASK); +} + +/*! + * @brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * @param base EWM peripheral base address +*/ +void EWM_Refresh(EWM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_EWM_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexcan.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexcan.c new file mode 100644 index 0000000000..132dbfb702 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexcan.c @@ -0,0 +1,2127 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ + /*! The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */ + /*! an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); + +#if !defined(NDEBUG) +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif + +/*! + * @brief Check if Message Buffer interrupt is enabled. + * + * This function check if Message Buffer interrupt is enabled. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. +*/ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Set Baud Rate of FlexCAN. + * + * This function set the baud rate of FlexCAN. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRate_Bps Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. + */ +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Set Baud Rate of FlexCAN FD frame. + * + * This function set the baud rate of FlexCAN FD frame. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRateFD_Bps FD frame Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. + */ +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig); + +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +#if defined(FLEXCAN_PERIPH_CLOCKS) +/* Array of FlexCAN serial clock name. */ +static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexcanBases)); + + return instance; +} + +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + + /* Wait until the FlexCAN Module enter freeze mode. */ + while (!(base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) +{ + /* Clear Freeze, Halt bits. */ + base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (base->MCR & CAN_MCR_FRZACK_MASK) + { + } +} + +#if !defined(NDEBUG) +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + + /* Is Rx FIFO enabled? */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Get RFFN value. */ + lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (mbIdx <= (lastOccupiedMb + 1)) +#else + if (mbIdx <= lastOccupiedMb) +#endif + { + return true; + } + else + { + return false; + } + } + else + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (0 == mbIdx) + { + return true; + } + else + { + return false; + } +#else + return false; +#endif + } +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif + +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) +{ + /* Assertion. */ + assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)); + +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + if (mbIdx < 32) + { +#endif + if (base->IMASK1 & ((uint32_t)(1 << mbIdx))) + { + return true; + } + else + { + return false; + } +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + } + else + { + if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32)))) + { + return true; + } + else + { + return false; + } + } +#endif +} + +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(!(base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0) + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (base->MCR & CAN_MCR_LPMACK_MASK) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (base->MCR & CAN_MCR_SOFTRST_MASK) + { + } + +/* Reset MCR rigister. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#else + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#endif + + /* Reset CTRL1 and CTRL2 rigister. */ + base->CTRL1 = CAN_CTRL1_SMP_MASK; + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; + + /* Clean all Message Buffer CS fields. */ + for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->MB[i].CS = 0x0; + } +} + +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig) +{ + /* FlexCAN timing setting formula: + * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); + */ + uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1); + uint32_t priDiv = baudRate_Bps * quantum; + + /* Assertion: Desired baud rate is too high. */ + assert(baudRate_Bps <= 1000000U); + /* Assertion: Source clock should greater than baud rate * quantum. */ + assert(priDiv <= sourceClock_Hz); + + if (0 == priDiv) + { + priDiv = 1; + } + + priDiv = (sourceClock_Hz / priDiv) - 1; + + /* Desired baud rate is too low. */ + if (priDiv > 0xFF) + { + priDiv = 0xFF; + } + + timingConfig.preDivider = priDiv; + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, &timingConfig); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig) +{ + /* FlexCAN FD timing setting formula: + * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG; + */ + uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg; + uint32_t priDiv = baudRateFD_Bps * quantum; + + /* Assertion: Desired baud rate is too high. */ + assert(baudRateFD_Bps <= 8000000U); + /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ + assert(priDiv <= sourceClock_Hz); + + if (0 == priDiv) + { + priDiv = 1; + } + + priDiv = (sourceClock_Hz / priDiv) - 1; + + /* Desired baud rate is too low. */ + if (priDiv > 0xFF) + { + priDiv = 0xFF; + } + + timingConfig.fpreDivider = priDiv; + + /* Update actual timing characteristic. */ + FLEXCAN_SetFDTimingConfig(base, &timingConfig); +} +#endif + +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) +{ + uint32_t mcrTemp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + + /* Assertion. */ + assert(config); + assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); + /* Enable FlexCAN clock. */ + CLOCK_EnableClock(s_flexcanClock[instance]); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Enable FlexCAN serial clock. */ + CLOCK_EnableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : + base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + + /* Enable FlexCAN Module for configuartion. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ + mcrTemp = base->MCR; + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1); + + /* Enable Loop Back Mode? */ + base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK; + + /* Enable Self Wake Up Mode? */ + mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; + + /* Enable Individual Rx Masking? */ + mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + /* Enable Doze Mode? */ + mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; +#endif + + /* Save MCR Configuation. */ + base->MCR = mcrTemp; + + /* Baud Rate Configuration.*/ + FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig); +#endif +} + +void FLEXCAN_Deinit(CAN_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Disable FlexCAN serial clock. */ + CLOCK_DisableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ + /* Disable FlexCAN clock. */ + CLOCK_DisableClock(s_flexcanClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Initialize FlexCAN Module config struct with default value. */ +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + config->clkSrc = kFLEXCAN_ClkSrcOsc; +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + config->baudRate = 1000000U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + config->baudRateFD = 1000000U; +#endif + config->maxMbNum = 16; + config->enableLoopBack = false; + config->enableSelfWakeup = false; + config->enableIndividMask = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + config->enableDoze = false; +#endif + /* Default protocol timing configuration, time quantum is 10. */ + config->timingConfig.phaseSeg1 = 3; + config->timingConfig.phaseSeg2 = 2; + config->timingConfig.propSeg = 1; + config->timingConfig.rJumpwidth = 1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + config->timingConfig.fphaseSeg1 = 3; + config->timingConfig.fphaseSeg2 = 3; + config->timingConfig.fpropSeg = 1; + config->timingConfig.frJumpwidth = 1; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs) +{ + if (brs) + { + base->FDCTRL &= CAN_FDCTRL_FDRATE_MASK; + } + else + { + base->FDCTRL &= ~CAN_FDCTRL_FDRATE_MASK; + } + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + base->MCR |= CAN_MCR_FDEN_MASK; + base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize); +#endif + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + /* Cleaning previous Timing Setting. */ + base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_EPROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CBT |= + (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | CAN_CBT_EPSEG1(config->phaseSeg1) | + CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); +#else + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= + (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); +#endif + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + base->CBT |= CAN_CBT_BTF(1); + /* Cleaning previous Timing Setting. */ + base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | + CAN_FDCBT_FPROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) | + CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(config->fpropSeg)); + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t dataSize; + uint32_t offset = 0; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + switch (dataSize) + { + case kFLEXCAN_8BperMB: + offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16; + break; + case kFLEXCAN_16BperMB: + offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24; + break; + case kFLEXCAN_32BperMB: + offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40; + break; + case kFLEXCAN_64BperMB: + offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72; + break; + default: + break; + } + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4; + return offset; +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + uint8_t cnt = 0; + uint8_t payload_dword = 1; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + mbAddr[offset] = 0x0; + } + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) + { + payload_dword *= 2; + } + + /* Clean ID. */ + mbAddr[offset + 1] = 0x0; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2 + cnt] = 0x0; + } + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif +} +#endif + +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = config->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == config->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == config->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + /* Inactivate all mailboxes first, clean ID and Message Buffer content. */ + for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++) + { + base->MB[cnt].CS = 0; + base->MB[cnt].ID = 0; + base->MB[cnt].WORD0 = 0; + base->MB[cnt].WORD1 = 0; + } + + if (enable) + { + /* Setup Message Buffer ID. */ + mbAddr[offset + 1] = config->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == config->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + mbAddr[offset] = cs_temp; + } +} +#endif + +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +{ + /* Assertion. */ + assert((config) || (false == enable)); + + volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); + uint8_t setup_mb, i, rffn = 0; + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + assert(config->idFilterNum <= 128); + + /* Get the setup_mb value. */ + setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT; + setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xF; i++) + { + if ((8 * (i + 1)) >= config->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8) - (2 * rffn)) > 0); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + } + else + { + rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; + } + + /* Clean ID filter table occuyied Message Buffer Region. */ + rffn = (rffn + 1) * 8; + for (i = 0; i < rffn; i++) + { + idFilterRegion[i] = 0x0; + } + + if (enable) + { + /* Disable unused Rx FIFO Filter. */ + for (i = config->idFilterNum; i < rffn; i++) + { + idFilterRegion[i] = 0xFFFFFFFFU; + } + + /* Copy ID filter table to Message Buffer Region. */ + for (i = 0; i < config->idFilterNum; i++) + { + idFilterRegion[i] = config->idFilterTable[i]; + } + + /* Setup ID Fitlter Type. */ + switch (config->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK : + base->CTRL2 | CAN_CTRL2_MRP_MASK; + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5. */ + FLEXCAN_SetRxMbConfig(base, 0, NULL, false); + FLEXCAN_SetRxMbConfig(base, 1, NULL, false); + FLEXCAN_SetRxMbConfig(base, 2, NULL, false); + FLEXCAN_SetRxMbConfig(base, 3, NULL, false); + FLEXCAN_SetRxMbConfig(base, 4, NULL, false); + FLEXCAN_SetRxMbConfig(base, 5, NULL, false); + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } + else + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(txFrame); + assert(txFrame->length <= 8); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = txFrame->id; + + /* Fill Message Format field. */ + if (kFLEXCAN_FrameFormatExtend == txFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if (kFLEXCAN_FrameTypeRemote == txFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = txFrame->dataWord0; + base->MB[mbIdx].WORD1 = txFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + return kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + return kStatus_Fail; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(txFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + uint32_t can_cs = 0; + uint8_t payload_dword = 1; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + can_cs = mbAddr[0]; + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) + { + /* Inactive Tx Message Buffer and Fill Message ID field. */ + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1] = txFrame->id; + + /* Fill Message Format field. */ + if (kFLEXCAN_FrameFormatExtend == txFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) + { + payload_dword *= 2; + } + + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + return kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + return kStatus_Fail; + } +} +#endif + +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp; + uint8_t rx_code; + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[mbIdx].WORD0; + rxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if (kFLEXCAN_RxMbFull == rx_code) + { + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Fail; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp; + uint8_t rx_code; + uint8_t cnt = 0; + uint32_t can_id = 0; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1]; + + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + rxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < dataSize + 1; cnt++) + { + payload_dword *= 2; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt]; + } + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if (kFLEXCAN_RxMbFull == rx_code) + { + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Fail; + } +} +#endif + +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(rxFrame); + + uint32_t cs_temp; + + /* Check if Rx FIFO is Enabled. */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[0].WORD0; + rxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +{ + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) + { + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) +#else + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) +#endif + { + } + + /* Clean Tx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); +#endif + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) +#else + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) +#endif + { + } + + /* Clean Rx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame) +{ + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, txFrame)) + { + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) +#else + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) +#endif + { + } + + /* Clean Tx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); +#endif + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) +{ + /* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) +#else + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) +#endif + { + } + + /* Clean Rx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadFDRxMb(base, mbIdx, rxFrame); +} +#endif + +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Rx FIFO non-empty. */ + while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* */ + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | + kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | + kFLEXCAN_WakeUpInterruptEnable); + } + else + { + FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | + kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | + kFLEXCAN_WakeUpInterruptEnable); + } + + /* Enable interrupts in NVIC. */ + EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + /* Distinguish transmit type. */ + if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; + + /* Register user Frame buffer to receive remote Frame. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; + } + + if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) + { + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; + return kStatus_Fail; + } + } + else + { + return kStatus_FLEXCAN_TxBusy; + } +} + +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxBusy; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + /* Distinguish transmit type. */ + if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; + + /* Register user Frame buffer to receive remote Frame. */ + handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; + } + + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, xfer->framefd)) + { + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; + return kStatus_Fail; + } + } + else + { + return kStatus_FLEXCAN_TxBusy; + } +} + +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; + + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxBusy; + } +} +#endif + +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = xfer->frame; + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts( + base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxFifoBusy; + } +} + +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = 0x0; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = 0x0; + + /* Clean Message Buffer. */ + FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = 0x0; + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} +#endif + +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = 0x0; + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(handle); + + /* Check if Rx FIFO is enabled. */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts( + base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = 0x0; + } + + handle->rxFifoState = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(handle); + + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result; + + /* Store Current FlexCAN Module Error and Status. */ + result = base->ESR1; + + do + { + /* Solve FlexCAN Error and Status Interrupt. */ + if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)) + { + status = kStatus_FLEXCAN_ErrorStatus; + + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | + kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag); + } + /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ + else + { + /* For this implementation, we solve the Message with lowest MB index first. */ + for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { + /* Get the lowest unhandled Message Buffer */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + if ((FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) +#else + if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) +#endif + { + break; + } + } + + /* Does not find Message to deal with. */ + if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + break; + } + + /* Solve Rx FIFO interrupt. */ + if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag)) + { + switch (1 << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + status = kStatus_FLEXCAN_RxFifoWarning; + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxFifoIdle; + } + FLEXCAN_TransferAbortReceiveFifo(base, handle); + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + else + { + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case kFLEXCAN_StateRxData: +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + status = FLEXCAN_ReadFDRxMb(base, result, handle->mbFDFrameBuf[result]); +#else + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); +#endif + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + FLEXCAN_TransferFDAbortReceive(base, handle, result); +#else + FLEXCAN_TransferAbortReceive(base, handle, result); +#endif + break; + + /* Solve Rx Remote Frame. */ + case kFLEXCAN_StateRxRemote: + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + FLEXCAN_TransferAbortReceive(base, handle, result); + break; + + /* Solve Tx Data Frame. */ + case kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + FLEXCAN_TransferFDAbortSend(base, handle, result); +#else + FLEXCAN_TransferAbortSend(base, handle, result); +#endif + break; + + /* Solve Tx Remote Frame. */ + case kFLEXCAN_StateTxRemote: + handle->mbState[result] = kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + + /* Clear resolved Message Buffer IRQ. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << result); +#else + FLEXCAN_ClearMbStatusFlags(base, 1 << result); +#endif + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + + /* Reset return status */ + status = kStatus_FLEXCAN_UnHandled; + + /* Store Current FlexCAN Module Error and Status. */ + result = base->ESR1; + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) || + (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); +#else + while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) || + (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); +#endif +} + +#if defined(CAN0) +void CAN0_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[0]); + + s_flexcanIsr(CAN0, s_flexcanHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN1) +void CAN1_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[1]); + + s_flexcanIsr(CAN1, s_flexcanHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN2) +void CAN2_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[2]); + + s_flexcanIsr(CAN2, s_flexcanHandle[2]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN3) +void CAN3_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[3]); + + s_flexcanIsr(CAN3, s_flexcanHandle[3]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN4) +void CAN4_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[4]); + + s_flexcanIsr(CAN4, s_flexcanHandle[4]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__CAN0) +void DMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + + s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__CAN1) +void DMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + + s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__CAN2) +void DMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + + s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexcan.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexcan.h new file mode 100644 index 0000000000..78ec2c4293 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexcan.h @@ -0,0 +1,1327 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXCAN_H_ +#define _FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN driver version 2.2.0. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \ + */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \ + */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN transfer status. */ +enum _flexcan_status +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */ +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE +/*! @brief FlexCAN clock source. */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ +} flexcan_clock_source_t; +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief FlexCAN Message Buffer Data Size. + */ +typedef enum _flexcan_mb_size +{ + kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ + kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ + kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ + kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */ +} flexcan_mb_size_t; +#endif + +/*! + * @brief FlexCAN Rx FIFO priority. + * + * The matching process starts from the Rx MB(or Rx FIFO) with higher priority. + * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with + * the Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the FlexCAN Module interrupt configurations. + * Note: FlexCAN Message Buffers and Rx FIFO have their own interrupts. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */ +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to + * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Error Overrun Status. */ +#endif + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = /*!< All FlexCAN Error Status. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK | + CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | +#endif + CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | + CAN_ESR1_STFERR_MASK, +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ + kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ +#endif + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Rx FIFO status flags. + * + * The FlexCAN Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum _flexcan_rx_fifo_flags +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t : 1; /*!< Reserved. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! @brief CAN FDmessage frame structure. */ +typedef struct _flexcan_fd_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t srr : 1; /*!< Substitute Remote request. */ + uint32_t : 1; + uint32_t code : 4; /*!< Message Buffer Code. */ + uint32_t : 1; + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_fd_frame_t; +#endif + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Phase Segment 1. */ + uint8_t phaseSeg2; /*!< Phase Segment 2. */ + uint8_t propSeg; /*!< Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */ + uint8_t frJumpwidth; /*!< Fast Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< Fast Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< Fast Phase Segment 2. */ + uint8_t fpropSeg; /*!< Fast Propagation Segment. */ +#endif +} flexcan_timing_config_t; + +/*! @brief FlexCAN module configuration structure. */ +typedef struct _flexcan_config +{ + uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ +#endif +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ +} flexcan_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +/*! @brief FlexCAN Rx FIFO configuration structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The quantity of filter elements. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *framefd; +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; +#endif + /*!< The buffer for received data from Message Buffers. */ + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz); + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 1000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * + * @param config Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Sets the FlexCAN FD protocol characteristic. + * + * This function gives user settings to CAN FD characteristic. + * + * @param base FlexCAN peripheral base address. + * @param dataSize Quantity of data bytes allocated for the message payload. + * @param brs Enable/Disable the effect of bit rate switch during data phase of Tx messages. + */ +void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs); +#endif + +/* @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Sets the FlexCAN FD protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); +#endif + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); +#endif + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param config Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param config Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); +#endif + +/*! + * @brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the FlexCAN Rx FIFO configuration structure. + * @param enable Enable/disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} + +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + return ((((uint64_t)base->IFLAG1) & mask) | ((((uint64_t)base->IFLAG2) << 32) & mask)); +#else + return (base->IFLAG1 & mask); +#endif +} + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to the provided mask. + * + * This function enables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if (mask & kFLEXCAN_WakeUpInterruptEnable) + { + base->MCR |= CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 |= (mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Disables FlexCAN interrupts according to the provided mask. + * + * This function disables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if (mask & kFLEXCAN_WakeUpInterruptEnable) + { + base->MCR &= ~CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 &= ~(mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif +} + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif +} + +/* @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uint32_t) & (base->MB[0].CS); +} + +/* @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (base->MCR & CAN_MCR_LPMACK_MASK) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (!(base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param txFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame); + +/*! + * @brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param rxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame); +#endif + +/*! + * @brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param txFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param rxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); +#endif + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +/*! + * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio.c new file mode 100644 index 0000000000..e6c256c3ee --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio.c @@ -0,0 +1,320 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio" +#endif + + +/*< @brief user configurable flexio handle count. */ +#define FLEXIO_HANDLE_COUNT 2 + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*< @brief pointer to array of FLEXIO handle. */ +static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO IP types. */ +static void *s_flexioType[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO Isr. */ +static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++) + { + if (s_flexioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexioBases)); + + return instance; +} + +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) +{ + uint32_t ctrlReg = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + FLEXIO_Reset(base); + + ctrlReg = base->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->CTRL = ctrlReg; +} + +void FLEXIO_Deinit(FLEXIO_Type *base) +{ + FLEXIO_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) +{ + assert(userConfig); + + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; +} + +void FLEXIO_Reset(FLEXIO_Type *base) +{ + /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ + base->CTRL |= FLEXIO_CTRL_SWRST_MASK; + base->CTRL = 0; +} + +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) +{ + assert(index < FLEXIO_SHIFTBUF_COUNT); + + uint32_t address = 0; + + switch (type) + { + case kFLEXIO_ShifterBuffer: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + + case kFLEXIO_ShifterBufferBitSwapped: + address = (uint32_t) & (base->SHIFTBUFBIS[index]); + break; + + case kFLEXIO_ShifterBufferByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBYS[index]); + break; + + case kFLEXIO_ShifterBufferBitByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBBS[index]); + break; + +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + case kFLEXIO_ShifterBufferNibbleByteSwapped: + address = (uint32_t) & (base->SHIFTBUFNBS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + case kFLEXIO_ShifterBufferHalfWordSwapped: + address = (uint32_t) & (base->SHIFTBUFHWS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + case kFLEXIO_ShifterBufferNibbleSwapped: + address = (uint32_t) & (base->SHIFTBUFNIS[index]); + break; + +#endif + default: + break; + } + return address; +} + +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) +{ + base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | + FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); + + base->SHIFTCTL[index] = + FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | + FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | + FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); +} + +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) +{ + base->TIMCFG[index] = + FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | + FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | + FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | + FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); + + base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); + + base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | + FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | + FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | + FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | + FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); +} + +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) +{ + assert(base); + assert(handle); + assert(isr); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] == NULL) + { + /* Register FLEXIO simulated driver base, handle and isr. */ + s_flexioType[index] = base; + s_flexioHandle[index] = handle; + s_flexioIsr[index] = isr; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +status_t FLEXIO_UnregisterHandleIRQ(void *base) +{ + assert(base); + + uint8_t index = 0; + + /* Find the index from base address mappings. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioType[index] == base) + { + /* Unregister FLEXIO simulated driver handle and isr. */ + s_flexioType[index] = NULL; + s_flexioHandle[index] = NULL; + s_flexioIsr[index] = NULL; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +void FLEXIO_CommonIRQHandler(void) +{ + uint8_t index; + + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index]) + { + s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO0_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO1_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void UART2_FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO2_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio.h new file mode 100644 index 0000000000..bebca939ec --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio.h @@ -0,0 +1,726 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_H_ +#define _FSL_FLEXIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO driver version 2.0.2. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief Calculate FlexIO timer trigger.*/ +#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) +#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) +#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) + +/*! @brief Define time of timer trigger polarity.*/ +typedef enum _flexio_timer_trigger_polarity +{ + kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! @brief Define type of timer trigger source.*/ +typedef enum _flexio_timer_trigger_source +{ + kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ + kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! @brief Define type of timer/shifter pin configuration.*/ +typedef enum _flexio_pin_config +{ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ +} flexio_pin_config_t; + +/*! @brief Definition of pin polarity.*/ +typedef enum _flexio_pin_polarity +{ + kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! @brief Define type of timer work mode.*/ +typedef enum _flexio_timer_mode +{ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! @brief Define type of timer initial output or timer reset condition.*/ +typedef enum _flexio_timer_output +{ + kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! @brief Define type of timer decrement.*/ +typedef enum _flexio_timer_decrement_source +{ + kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock + equals Timer output. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U, /*!< Decrement counter on Pin input (both edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Trigger input. */ +} flexio_timer_decrement_source_t; + +/*! @brief Define type of timer reset condition.*/ +typedef enum _flexio_timer_reset_condition +{ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to + Timer Output. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! @brief Define type of timer disable condition.*/ +typedef enum _flexio_timer_disable_condition +{ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided + Trigger is high. */ + kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! @brief Define type of timer enable condition.*/ +typedef enum _flexio_timer_enable_condition +{ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! @brief Define type of timer stop bit generate condition.*/ +typedef enum _flexio_timer_stop_bit_condition +{ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer + disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! @brief Define type of timer start bit generate condition.*/ +typedef enum _flexio_timer_start_bit_condition +{ + kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @brief Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */ +} flexio_shifter_timer_polarity_t; + +/*! @brief Define type of shifter working mode.*/ +typedef enum _flexio_shifter_mode +{ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE + kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing + programmable state attributes. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE + kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing + programmable logic look up table. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ +} flexio_shifter_mode_t; + +/*! @brief Define type of shifter input source.*/ +typedef enum _flexio_shifter_input_source +{ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! @brief Define of STOP bit configuration.*/ +typedef enum _flexio_shifter_stop_bit +{ + kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! @brief Define type of START bit configuration.*/ +typedef enum _flexio_shifter_start_bit +{ + kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads + data on enable. */ + kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads + data on first shift. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ +} flexio_shifter_start_bit_t; + +/*! @brief Define FlexIO shifter buffer type*/ +typedef enum _flexio_shifter_buffer_type +{ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ +#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ +#endif +} flexio_shifter_buffer_type_t; + +/*! @brief Define FlexIO user configuration structure. */ +typedef struct _flexio_config_ +{ + bool enableFlexio; /*!< Enable/disable FlexIO module */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ +} flexio_config_t; + +/*! @brief Define FlexIO timer configuration structure. */ +typedef struct _flexio_timer_config +{ + /* Trigger. */ + uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ + uint32_t pinSelect; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ + flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and + whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the + source of the Shift clock. */ + flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter + (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be + disabled and stop decrementing. */ + flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be + enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ + uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +/*! @brief Define FlexIO shifter configuration structure. */ +typedef struct _flexio_shifter_config +{ + /* Timer. */ + uint32_t timerSelect; /*!< Selects which Timer is used for controlling the + logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ + uint32_t pinSelect; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ +typedef void (*flexio_isr_t)(void *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +extern FLEXIO_Type *const s_flexioBases[]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +extern const clock_ip_name_t s_flexioClocks[]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + @code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + @endcode + * + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); + +/*! + * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + @code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); + +/*! + * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * @note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * @param base FlexIO peripheral base address +*/ +void FLEXIO_Deinit(FLEXIO_Type *base); + +/*! + * @brief Get instance number for FLEXIO module. + * + * @param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); + +/* @} */ + +/*! + * @name FlexIO Basic Operation + * @{ + */ + +/*! + * @brief Resets the FlexIO module. + * + * @param base FlexIO peripheral base address +*/ +void FLEXIO_Reset(FLEXIO_Type *base); + +/*! + * @brief Enables the FlexIO module operation. + * + * @param base FlexIO peripheral base address + * @param enable true to enable, false to disable. +*/ +static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Reads the input data on each of the FlexIO pins. + * + * @param base FlexIO peripheral base address + * @return FlexIO pin input data +*/ +static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) +{ + return base->PIN; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +/*! + * @brief Gets the current state pointer for state mode use. + * + * @param base FlexIO peripheral base address + * @return current State pointer +*/ +static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) +{ + return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); +} +#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ + +/*! + * @brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + @code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Shifter index + * @param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); +/*! + * @brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + @code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Timer index + * @param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); + +/* @} */ + +/*! + * @name FlexIO Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN |= mask; +} + +/*! + * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN &= ~mask; +} + +/*! + * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN |= mask; +} + +/*! + * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN &= ~mask; +} + +/*! + * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) +*/ +static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN |= mask; +} + +/*! + * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) +*/ +static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN &= ~mask; +} + +/* @} */ + +/*! + * @name FlexIO Status Operation + * @{ + */ + +/*! + * @brief Gets the shifter status flags. + * + * @param base FlexIO peripheral base address + * @return Shifter status flags +*/ +static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); +} + +/*! + * @brief Clears the shifter status flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSTAT = mask; +} + +/*! + * @brief Gets the shifter error flags. + * + * @param base FlexIO peripheral base address + * @return Shifter error flags +*/ +static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); +} + +/*! + * @brief Clears the shifter error flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTERR = mask; +} + +/*! + * @brief Gets the timer status flags. + * + * @param base FlexIO peripheral base address + * @return Timer status flags +*/ +static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) +{ + return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); +} + +/*! + * @brief Clears the timer status flags. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) +*/ +static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMSTAT = mask; +} + +/* @} */ + +/*! + * @name FlexIO DMA Operation + * @{ + */ + +/*! + * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. + * + * @note For multiple shifter status DMA enables, for example, calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @param enable True to enable, false to disable. +*/ +static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SHIFTSDEN |= mask; + } + else + { + base->SHIFTSDEN &= ~mask; + } +} + +/*! + * @brief Gets the shifter buffer address for the DMA transfer usage. + * + * @param base FlexIO peripheral base address + * @param type Shifter type of flexio_shifter_buffer_type_t + * @param index Shifter index + * @return Corresponding shifter buffer index +*/ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); + +/*! + * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param handle Pointer to the handler for FlexIO simulated peripheral. + * @param isr FlexIO simulated peripheral interrupt handler. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. +*/ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); + +/*! + * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. +*/ +status_t FLEXIO_UnregisterHandleIRQ(void *base); +/* @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.c new file mode 100644 index 0000000000..3d3ca0d657 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.c @@ -0,0 +1,818 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_i2c_master.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master" +#endif + + +/*! @brief FLEXIO I2C transfer state */ +enum _flexio_i2c_master_transfer_states +{ + kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ + kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ + kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ + kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ + kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ + kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param transfer pointer to flexio_i2c_master_transfer_t structure + */ +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * @retval kStatus_Success Successfully run state machine + * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer + */ +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief Complete transfer, disable interrupt and call callback. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param status flexio transfer status + */ +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status); + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + bool needRestart; + uint32_t byteCount; + + /* Init the handle member. */ + handle->transfer.slaveAddress = xfer->slaveAddress; + handle->transfer.direction = xfer->direction; + handle->transfer.subaddress = xfer->subaddress; + handle->transfer.subaddressSize = xfer->subaddressSize; + handle->transfer.data = xfer->data; + handle->transfer.dataSize = xfer->dataSize; + handle->transfer.flags = xfer->flags; + handle->transferSize = xfer->dataSize; + + /* Initial state, i2c check address state. */ + handle->state = kFLEXIO_I2C_CheckAddress; + + /* Clear all status before transfer. */ + FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag); + + /* Calculate whether need to send re-start. */ + needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read); + + /* Calculate total byte count in a frame. */ + byteCount = 1; + + if (!needRestart) + { + byteCount += handle->transfer.dataSize; + } + + if (handle->transfer.subaddressSize != 0) + { + byteCount += handle->transfer.subaddressSize; + /* Next state, send command byte. */ + handle->state = kFLEXIO_I2C_SendCommand; + } + + /* Configure data count. */ + if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success) + { + return kStatus_InvalidArgument; + } + + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + + /* Send address byte first. */ + if (needRestart) + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); + } + else + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); + } + + return kStatus_Success; +} + +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag) + { + /* Clear receive nak flag. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + + if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && + (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) && + (handle->transfer.dataSize == 1U)))) + { + FLEXIO_I2C_MasterReadByte(base); + + FLEXIO_I2C_MasterAbortStop(base); + + handle->state = kFLEXIO_I2C_Idle; + + return kStatus_FLEXIO_I2C_Nak; + } + } + + if (handle->state == kFLEXIO_I2C_CheckAddress) + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = kFLEXIO_I2C_SendData; + } + else + { + /* Next state, receive data begin. */ + handle->state = kFLEXIO_I2C_ReceiveDataBegin; + } + } + + if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData)) + { + FLEXIO_I2C_MasterReadByte(base); + } + + switch (handle->state) + { + case kFLEXIO_I2C_SendCommand: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + if (handle->transfer.subaddressSize > 0) + { + handle->transfer.subaddressSize--; + FLEXIO_I2C_MasterWriteByte( + base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize))); + + if (handle->transfer.subaddressSize == 0) + { + /* Load re-start in advance. */ + if (handle->transfer.direction == kFLEXIO_I2C_Read) + { + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterRepeatedStart(base); + } + } + } + else + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = kFLEXIO_I2C_SendData; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1)); + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); + + /* Next state, receive data begin. */ + handle->state = kFLEXIO_I2C_ReceiveDataBegin; + } + } + } + break; + + /* Send command byte. */ + case kFLEXIO_I2C_SendData: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + + while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) + { + } + FLEXIO_I2C_MasterReadByte(base); + + handle->state = kFLEXIO_I2C_Idle; + } + } + break; + + case kFLEXIO_I2C_ReceiveDataBegin: + if (statusFlags & kFLEXIO_I2C_RxFullFlag) + { + handle->state = kFLEXIO_I2C_ReceiveData; + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + FLEXIO_I2C_MasterEnableAck(base, false); + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterStop(base); + } + else + { + FLEXIO_I2C_MasterEnableAck(base, true); + } + } + else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + /* Read one byte of data. */ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + else + { + } + break; + + case kFLEXIO_I2C_ReceiveData: + if (statusFlags & kFLEXIO_I2C_RxFullFlag) + { + *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); + handle->transfer.data++; + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable); + handle->state = kFLEXIO_I2C_Idle; + } + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + FLEXIO_I2C_MasterEnableAck(base, false); + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterStop(base); + } + } + } + else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + if (handle->transfer.dataSize > 1) + { + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + } + else + { + } + break; + + default: + break; + } + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status) +{ + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + if (handle->completionCallback) + { + handle->completionCallback(base, handle, status, handle->userData); + } +} + +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base && masterConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t controlVal = 0; + uint16_t timerDiv = 0; + status_t result = kStatus_Success; + + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for generating bit clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */ + timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1; + + if (timerDiv > 0xFFU) + { + result = kStatus_InvalidArgument; + return result; + } + + timerConfig.timerCompare = timerDiv; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for controlling shifters. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ + timerConfig.timerCompare = 8 * 2 - 1; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + /* Configure FLEXIO I2C Master. */ + controlVal = base->flexioBase->CTRL; + controlVal &= + ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + controlVal |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = controlVal; + return result; +} + +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); +} + +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; +} + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) +{ + uint32_t status = 0; + + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + + return status; +} + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + + if (mask & kFLEXIO_I2C_RxFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } + + if (mask & kFLEXIO_I2C_ReceiveNakFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_I2C_RxFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_I2C_RxFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = srcClock_Hz / baudRate_Bps; + timerDiv = timerDiv / 2 - 1U; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0xFF00; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) +{ + if (count > 14U) + { + return kStatus_InvalidArgument; + } + + uint16_t timerCmp = 0; + uint32_t timerConfig = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0x00FFU; + timerCmp |= (count * 18 + 1U) << 8U; + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; + timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; + timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; + + return kStatus_Success; +} + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) +{ + uint32_t data; + + data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); + + FLEXIO_I2C_MasterWriteByte(base, data); +} + +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) +{ + /* Prepare for RESTART condition, no stop.*/ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); +} + +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) +{ + /* Prepare normal stop. */ + FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); + FLEXIO_I2C_MasterWriteByte(base, 0x0U); +} + +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) +{ + uint32_t tmpConfig; + + /* Prepare abort stop. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; +} + +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) +{ + uint32_t tmpConfig = 0; + + tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; + tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; + if (enable) + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); + } + else + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); + } + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; +} + +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) +{ + assert(txBuff); + assert(txSize); + + uint32_t status; + + while (txSize--) + { + FLEXIO_I2C_MasterWriteByte(base, *txBuff++); + + /* Wait until data transfer complete. */ + while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag)) + { + } + + if (status & kFLEXIO_I2C_ReceiveNakFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + return kStatus_FLEXIO_I2C_Nak; + } + } + return kStatus_Success; +} + +void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) +{ + assert(rxBuff); + assert(rxSize); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) + { + } + + *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); + } +} + +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) +{ + assert(xfer); + + flexio_i2c_master_handle_t tmpHandle; + uint32_t statusFlags; + uint32_t result = kStatus_Success; + + /* Zero the handle. */ + memset(&tmpHandle, 0, sizeof(tmpHandle)); + + /* Set up transfer machine. */ + FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer); + + do + { + /* Wait either tx empty or rx full flag is asserted. */ + while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & + (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag))) + { + } + + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); + + } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success)); + + return result; +} + +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); +} + +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + if (handle->state != kFLEXIO_I2C_Idle) + { + return kStatus_FLEXIO_I2C_Busy; + } + else + { + /* Set up transfer machine. */ + FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); + + /* Enable both tx empty and rxfull interrupt. */ + FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + return kStatus_Success; + } +} + +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupts. */ + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + /* Reset to idle state. */ + handle->state = kFLEXIO_I2C_Idle; +} + +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) +{ + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) +{ + FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; + flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; + uint32_t statusFlags; + status_t result; + + statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); + + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); + + if (handle->state == kFLEXIO_I2C_Idle) + { + FLEXIO_I2C_MasterTransferComplete(base, handle, result); + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.h new file mode 100644 index 0000000000..5e6ee2b9bf --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2c_master.h @@ -0,0 +1,487 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_I2C_MASTER_H_ +#define _FSL_FLEXIO_I2C_MASTER_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2c_master + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2C master driver version 2.1.5. */ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + +/*! @brief FlexIO I2C transfer status*/ +enum _flexio_i2c_status +{ + kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ +}; + +/*! @brief Define FlexIO I2C master interrupt mask. */ +enum _flexio_i2c_master_interrupt +{ + kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ + kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO I2C master status mask. */ +enum _flexio_i2c_master_status_flags +{ + kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ + kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ + kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ +}; + +/*! @brief Direction of master transfer.*/ +typedef enum _flexio_i2c_direction +{ + kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ + kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ +} flexio_i2c_direction_t; + +/*! @brief Define FlexIO I2C master access structure typedef. */ +typedef struct _flexio_i2c_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ + uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO I2C. */ +} FLEXIO_I2C_Type; + +/*! @brief Define FlexIO I2C master user configuration structure. */ +typedef struct _flexio_i2c_master_config +{ + bool enableMaster; /*!< Enables the FlexIO I2C peripheral at initialization time. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ +} flexio_i2c_master_config_t; + +/*! @brief Define FlexIO I2C master transfer structure. */ +typedef struct _flexio_i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t volatile *data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} flexio_i2c_master_transfer_t; + +/*! @brief FlexIO I2C master handle typedef. */ +typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; + +/*! @brief FlexIO I2C master transfer callback typedef. */ +typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2C master handle structure. */ +struct _flexio_i2c_master_handle +{ + flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ + /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + @code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization successful + * @retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + @code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + @endcode + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); + +/*! + * @brief Enables/disables the FlexIO module operation. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable Pass true to enable module, false does not have any effect. +*/ +static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. +*/ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); + +/*! + * @brief Clears the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_I2C_RxFullFlag + * @arg kFLEXIO_I2C_ReceiveNakFlag +*/ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO i2c master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + * Currently only one interrupt request source: + * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2C master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the FlexIO I2C master transfer baudrate. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param baudRate_Bps the baud rate value in HZ + * @param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends START + 7-bit address to the bus. + * + * @note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param address 7-bit address. + * @param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * @arg kFLEXIO_I2C_Write: Transmit + * @arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); + +/*! + * @brief Sends the stop signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the repeated start signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the stop signal when transfer is still on-going. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Configures the sent ACK/NAK for the following byte. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); + +/*! + * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * @note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * @retval kStatus_Success Successfully configured the count. + * @retval kStatus_InvalidArgument Input argument is invalid. +*/ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count); + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param data a byte of data. + */ +static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; +} + +/*! + * @brief Reads one byte of data from the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the data is ready in the register. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @return data byte read. + */ +static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) +{ + return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; +} + +/*! + * @brief Sends a buffer of data in bytes. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param txBuff The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_Success Successfully write data. + * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param rxBuff The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + */ +void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param xfer pointer to flexio_i2c_master_transfer_t structure. + * @return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); +/*@}*/ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * @param callback Pointer to user callback function. + * @param userData User param passed to the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2c_master_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param i2cType Pointer to FLEXIO_I2C_Type structure + * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s.c new file mode 100644 index 0000000000..5e7bc43773 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s.c @@ -0,0 +1,668 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_i2s.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s" +#endif + + +/******************************************************************************* +* Definitations +******************************************************************************/ +enum _sai_transfer_state +{ + kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */ + kFLEXIO_I2S_Idle, /*!< Transfer is done. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base FLEXIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base FLEXIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*txData); + data |= (temp << (8U * j)); + txData++; + } + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); + data = 0; + } +} + +static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth)); + for (j = 0; j < bytesPerWord; j++) + { + *rxData = (data >> (8U * j)) & 0xFF; + rxData++; + } + } +} + +void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) +{ + assert(base && config); + + flexio_shifter_config_t shifterConfig = {0}; + flexio_timer_config_t timerConfig = {0}; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Set shifter for I2S Tx data */ + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->txPinIndex; + shifterConfig.timerPolarity = config->txTimerPolarity; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinPolarity = config->txPinPolarity; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (config->masterSlave == kFLEXIO_I2S_Master) + { + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + else + { + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig); + + /* Set shifter for I2S Rx Data */ + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->rxPinIndex; + shifterConfig.timerPolarity = config->rxTimerPolarity; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinPolarity = config->rxPinPolarity; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig); + + /* Set Timer to I2S frame sync */ + if (config->masterSlave == kFLEXIO_I2S_Master) + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = config->fsPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + else + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = config->fsPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig); + + /* Set Timer to I2S bit clock */ + if (config->masterSlave == kFLEXIO_I2S_Master) + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinPolarity = config->bclkPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + else + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinPolarity = config->bclkPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig); + + /* If enable flexio I2S */ + if (config->enableI2S) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) +{ + config->masterSlave = kFLEXIO_I2S_Master; + config->enableI2S = true; + config->txPinPolarity = kFLEXIO_PinActiveHigh; + config->rxPinPolarity = kFLEXIO_PinActiveHigh; + config->bclkPinPolarity = kFLEXIO_PinActiveHigh; + config->fsPinPolarity = kFLEXIO_PinActiveLow; + config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; +} + +void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) +{ + base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0; + base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0; + base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0; + base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0; + base->flexioBase->TIMCFG[base->fsTimerIndex] = 0; + base->flexioBase->TIMCMP[base->fsTimerIndex] = 0; + base->flexioBase->TIMCTL[base->fsTimerIndex] = 0; + base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0; +} + +void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); + } + if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); + } +} + +uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) +{ + uint32_t status = 0; + status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex)) + << 1U); + return status; +} + +void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); + } + if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); + } +} + +void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz) +{ + uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U); + uint32_t bclkDiv = 0; + + /* Shall keep bclk and fs div an integer */ + if (timDiv % 2) + { + timDiv += 1U; + } + /* Set Frame sync timer cmp */ + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U); + + /* Set bit clock timer cmp */ + bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U)); + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv); +} + +void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format) +{ + /* Set Frame sync timer cmp */ + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U); + + /* Set bit clock timer cmp */ + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U); +} + +void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size / bytesPerWord; i++) + { + /* Wait until it can write data */ + while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) + { + } + + FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord); + txData += bytesPerWord; + } + + /* Wait until the last data is sent */ + while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) + { + } +} + +void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size / bytesPerWord; i++) + { + /* Wait until data is received */ + while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex))) + { + } + + FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord); + rxData += bytesPerWord; + } +} + +void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Store callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ); + + /* Set the TX/RX state. */ + handle->state = kFLEXIO_I2S_Idle; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); +} + +void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Store callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ); + + /* Set the TX/RX state. */ + handle->state = kFLEXIO_I2S_Idle; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); +} + +void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz) +{ + assert(handle && format); + + /* Set the bitWidth to handle */ + handle->bitWidth = format->bitWidth; + + /* Set sample rate */ + if (srcClock_Hz != 0) + { + /* It is master */ + FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); + } + else + { + FLEXIO_I2S_SlaveSetFormat(base, format); + } +} + +status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + if ((xfer->dataSize == 0) || (xfer->data == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Add into queue */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kFLEXIO_I2S_Busy; + + FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); + + /* Enable Tx transfer */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + if ((xfer->dataSize == 0) || (xfer->data == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Add into queue */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kFLEXIO_I2S_Busy; + + /* Enable interrupt */ + FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); + + /* Enable Rx transfer */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); + handle->state = kFLEXIO_I2S_Idle; + + /* Clear the queue */ + memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) +{ + assert(handle); + + /* Stop rx transfer and disable interrupt */ + FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); + handle->state = kFLEXIO_I2S_Idle; + + /* Clear the queue */ + memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); + } + + return status; +} + +void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) +{ + assert(i2sHandle); + + flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle error */ + if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex)) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex)); + } + /* Handle transfer */ + if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) && + (handle->queue[handle->queueDriver].data != NULL)) + { + FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize); + + /* Update internal counter */ + handle->queue[handle->queueDriver].dataSize -= dataSize; + handle->queue[handle->queueDriver].data += dataSize; + } + + /* If finished a blcok, call the callback function */ + if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) + { + memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->queue[handle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortSend(base, handle); + } +} + +void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) +{ + assert(i2sHandle); + + flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle transfer */ + if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) && + (handle->queue[handle->queueDriver].data != NULL)) + { + FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize); + + /* Update internal state */ + handle->queue[handle->queueDriver].dataSize -= dataSize; + handle->queue[handle->queueDriver].data += dataSize; + } + + /* If finished a blcok, call the callback function */ + if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) + { + memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->queue[handle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortReceive(base, handle); + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s.h new file mode 100644 index 0000000000..2d7326c37e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s.h @@ -0,0 +1,574 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_I2S_H_ +#define _FSL_FLEXIO_I2S_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2s + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2S driver version 2.1.4. */ +#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/*! @brief FlexIO I2S transfer status */ +enum _flexio_i2s_status +{ + kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */ + kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */ + kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */ +}; + +/*! @brief Define FlexIO I2S access structure typedef */ +typedef struct _flexio_i2s_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer */ + uint8_t txPinIndex; /*!< Tx data pin index in FlexIO pins */ + uint8_t rxPinIndex; /*!< Rx data pin index */ + uint8_t bclkPinIndex; /*!< Bit clock pin index */ + uint8_t fsPinIndex; /*!< Frame sync pin index */ + uint8_t txShifterIndex; /*!< Tx data shifter index */ + uint8_t rxShifterIndex; /*!< Rx data shifter index */ + uint8_t bclkTimerIndex; /*!< Bit clock timer index */ + uint8_t fsTimerIndex; /*!< Frame sync timer index */ +} FLEXIO_I2S_Type; + +/*! @brief Master or slave mode */ +typedef enum _flexio_i2s_master_slave +{ + kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */ + kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */ +} flexio_i2s_master_slave_t; + +/*! @brief Define FlexIO FlexIO I2S interrupt mask. */ +enum _flexio_i2s_interrupt_enable +{ + kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO FlexIO I2S status mask. */ +enum _flexio_i2s_status_flags +{ + kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief FlexIO I2S configure structure */ +typedef struct _flexio_i2s_config +{ + bool enableI2S; /*!< Enable FlexIO I2S */ + flexio_i2s_master_slave_t masterSlave; /*!< Master or slave */ + flexio_pin_polarity_t txPinPolarity; /*!< Tx data pin polarity, active high or low */ + flexio_pin_polarity_t rxPinPolarity; /*!< Rx data pin polarity */ + flexio_pin_polarity_t bclkPinPolarity; /*!< Bit clock pin polarity */ + flexio_pin_polarity_t fsPinPolarity; /*!< Frame sync pin polarity */ + flexio_shifter_timer_polarity_t txTimerPolarity; /*!< Tx data valid on bclk rising or falling edge */ + flexio_shifter_timer_polarity_t rxTimerPolarity; /*!< Rx data valid on bclk rising or falling edge */ +} flexio_i2s_config_t; + +/*! @brief FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx */ +typedef struct _flexio_i2s_format +{ + uint8_t bitWidth; /*!< Bit width of audio data, always 8/16/24/32 bits */ + uint32_t sampleRate_Hz; /*!< Sample rate of the audio data */ +} flexio_i2s_format_t; + +/*!@brief FlexIO I2S transfer queue size, user can refine it according to use case. */ +#define FLEXIO_I2S_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _flexio_i2s_sample_rate +{ + kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ + kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ + kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ + kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ + kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ + kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ + kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ + kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ + kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ + kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ +} flexio_i2s_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _flexio_i2s_word_width +{ + kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kFLEXIO_I2S_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} flexio_i2s_word_width_t; + +/*! @brief Define FlexIO I2S transfer structure. */ +typedef struct _flexio_i2s_transfer +{ + uint8_t *data; /*!< Data buffer start pointer */ + size_t dataSize; /*!< Bytes to be transferred. */ +} flexio_i2s_transfer_t; + +typedef struct _flexio_i2s_handle flexio_i2s_handle_t; + +/*! @brief FlexIO I2S xfer callback prototype */ +typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2S handle structure. */ +struct _flexio_i2s_handle +{ + uint32_t state; /*!< Internal state */ + flexio_i2s_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32bits */ + flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S. + * + * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. + * The configuration structure can be filled by the user, or be set with default values by + * FLEXIO_I2S_GetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault + * because the clock is not enabled. + * + * @param base FlexIO I2S base pointer + * @param config FlexIO I2S configure structure. +*/ +void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config); + +/*! + * @brief Sets the FlexIO I2S configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). + * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify + * some fields of the structure before calling FLEXIO_I2S_Init(). + * + * @param config pointer to master configuration structure + */ +void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config); + +/*! + * @brief De-initializes the FlexIO I2S. + * + * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, + * call the FLEXO_I2S_Init to use the FlexIO I2S module. + * + * @param base FlexIO I2S base pointer +*/ +void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base); + +/*! + * @brief Enables/disables the FlexIO I2S module operation. + * + * @param base Pointer to FLEXIO_I2S_Type + * @param enable True to enable, false dose not have any effect. +*/ +static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2S status flags. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. +*/ +uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param mask interrupt source + */ +void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param mask interrupt source + */ +void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO I2S Tx DMA requests. + * + * @param base FlexIO I2S base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->txShifterIndex, enable); +} + +/*! + * @brief Enables/disables the FlexIO I2S Rx DMA requests. + * + * @param base FlexIO I2S base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->rxShifterIndex, enable); +} + +/*! + * @brief Gets the FlexIO I2S send data register address. + * + * This function returns the I2S data register address, mainly used by DMA/eDMA. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @return FlexIO i2s send data register address. + */ +static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->txShifterIndex); +} + +/*! + * @brief Gets the FlexIO I2S receive data register address. + * + * This function returns the I2S data register address, mainly used by DMA/eDMA. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @return FlexIO i2s receive data register address. + */ +static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->rxShifterIndex); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the FlexIO I2S audio format in master mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param format Pointer to FlexIO I2S audio data format structure. + * @param srcClock_Hz I2S master clock source frequency in Hz. +*/ +void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz); + +/*! + * @brief Configures the FlexIO I2S audio format in slave mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param format Pointer to FlexIO I2S audio data format structure. +*/ +void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks via polling until data is ready to be sent. + * + * @param base FlexIO I2S base pointer. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param txData Pointer to the data to be written. + * @param size Bytes to be written. + */ +void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); + +/*! + * @brief Writes data into a data register. + * + * @param base FlexIO I2S base pointer. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param data Data to be written. + */ +static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data) +{ + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); +} + +/*! + * @brief Receives a piece of data using a blocking method. + * + * @note This function blocks via polling until data is ready to be sent. + * + * @param base FlexIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param rxData Pointer to the data to be read. + * @param size Bytes to be read. + */ +void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); + +/*! + * @brief Reads a data from the data register. + * + * @param base FlexIO I2S base pointer + * @return Data read from data register. + */ +static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base) +{ + return base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * @param callback FlexIO I2S callback function, which is called while finished a block. + * @param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData); + +/*! + * @brief Configures the FlexIO I2S audio format. + * + * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle FlexIO I2S handle pointer. + * @param format Pointer to audio data format structure. + * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. +*/ +void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz); + +/*! + * @brief Initializes the FlexIO I2S receive handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * @param callback FlexIO I2S callback function, which is called while finished a block. + * @param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData); + +/*! + * @brief Performs an interrupt non-blocking send transfer on FlexIO I2S. + * + * @note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param xfer Pointer to flexio_i2s_transfer_t structure + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on FlexIO I2S. + * + * @note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param xfer Pointer to flexio_i2s_transfer_t structure + * @retval kStatus_Success Successfully start the data receive. + * @retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); + +/*! + * @brief Aborts the current receive. + * + * @note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be sent. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param count Bytes sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); + +/*! + * @brief Gets the remaining bytes to be received. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @return count Bytes received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); + +/*! + * @brief Tx interrupt handler. + * + * @param i2sBase Pointer to FLEXIO_I2S_Type structure. + * @param i2sHandle Pointer to flexio_i2s_handle_t structure + */ +void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle); + +/*! + * @brief Rx interrupt handler. + * + * @param i2sBase Pointer to FLEXIO_I2S_Type structure. + * @param i2sHandle Pointer to flexio_i2s_handle_t structure. + */ +void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_FLEXIO_I2S_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.c new file mode 100644 index 0000000000..223d71d759 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.c @@ -0,0 +1,377 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_i2s_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma" +#endif + + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (flexio_i2sHandle->callback) + { + (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortSendEDMA(privHandle->base, flexio_i2sHandle); + } +} + +static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData; + flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (flexio_i2sHandle->callback) + { + (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortReceiveEDMA(privHandle->base, flexio_i2sHandle); + } +} + +void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set flexio_i2s base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set FLEXIO I2S state to idle */ + handle->state = kFLEXIO_I2S_Idle; + + s_edmaPrivateHandle[0].base = base; + s_edmaPrivateHandle[0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]); +} + +void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set flexio_i2s base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set FLEXIO I2S state to idle */ + handle->state = kFLEXIO_I2S_Idle; + + s_edmaPrivateHandle[1].base = base; + s_edmaPrivateHandle[1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]); +} + +void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz) +{ + assert(handle && format); + + /* Configure the audio format to FLEXIO I2S registers */ + if (srcClock_Hz != 0) + { + /* It is master */ + FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); + } + else + { + FLEXIO_I2S_SlaveSetFormat(base, format); + } + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; +} + +status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + /* Change the state of handle */ + handle->state = kFLEXIO_I2S_Busy; + + /* Update the queue state */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */ + handle->nbytes = handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + FLEXIO_I2S_TxEnableDMA(base, true); + + /* Enable FLEXIO I2S Tx clock */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + /* Change the state of handle */ + handle->state = kFLEXIO_I2S_Busy; + + /* Update queue state */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */ + handle->nbytes = handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + FLEXIO_I2S_RxEnableDMA(base, true); + + /* Enable FLEXIO I2S Rx clock */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + FLEXIO_I2S_TxEnableDMA(base, false); + + /* Set the handle state */ + handle->state = kFLEXIO_I2S_Idle; +} + +void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + FLEXIO_I2S_RxEnableDMA(base, false); + + /* Set the handle state */ + handle->state = kFLEXIO_I2S_Idle; +} + +status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel); + } + + return status; +} + +status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel); + } + + return status; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.h new file mode 100644 index 0000000000..e529fe23f7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_i2s_edma.h @@ -0,0 +1,229 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_I2S_EDMA_H_ +#define _FSL_FLEXIO_I2S_EDMA_H_ + +#include "fsl_flexio_i2s.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_i2s + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2S EDMA driver version 2.1.4. */ +#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t; + +/*! @brief FlexIO I2S eDMA transfer callback function for finish and error */ +typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO I2S DMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_i2s_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for FlexIO I2S send */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint32_t state; /*!< Internal state for FlexIO I2S eDMA transfer */ + flexio_i2s_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ + void *userData; /*!< User callback parameter */ + edma_tcd_t tcd[FLEXIO_I2S_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S eDMA handle. + * + * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master + * transactional APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S eDMA handle pointer. + * @param callback FlexIO I2S eDMA callback function called while finished a block. + * @param userData User parameter for callback. + * @param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ +void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the FlexIO I2S Rx eDMA handle. + * + * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional + * APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S eDMA handle pointer. + * @param callback FlexIO I2S eDMA callback function called while finished a block. + * @param userData User parameter for callback. + * @param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ +void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle); + +/*! + * @brief Configures the FlexIO I2S Tx audio format. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to format. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S eDMA handle pointer + * @param format Pointer to FlexIO I2S audio data format structure. + * @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. +*/ +void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz); + +/*! + * @brief Performs a non-blocking FlexIO I2S transfer using DMA. + * + * @note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a FlexIO I2S eDMA send successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + * @retval kStatus_TxBusy FlexIO I2S is busy sending data. + */ +status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking FlexIO I2S receive using eDMA. + * + * @note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is + * finished. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a FlexIO I2S eDMA receive successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + * @retval kStatus_RxBusy FlexIO I2S is busy receiving data. + */ +status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO I2S transfer using eDMA. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle); + +/*! + * @brief Aborts a FlexIO I2S receive using eDMA. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be sent. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param count Bytes sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count); + +/*! + * @brief Get the remaining bytes to be received. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param count Bytes received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi.c new file mode 100644 index 0000000000..5cae486ae8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi.c @@ -0,0 +1,1005 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_spi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi" +#endif + + +/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ +enum _flexio_spi_transfer_states +{ + kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ + kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Send a piece of data for SPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for SPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = *(handle->txData); + handle->txData++; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += handle->txData[0]; + } + handle->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes -= handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + if (!handle->txRemainingBytes) + { + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + } +} + +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint16_t tmpData; + + tmpData = FLEXIO_SPI_ReadData(base, handle->direction); + + if (handle->rxData != NULL) + { + if (handle->bytePerFrame == 1U) + { + *handle->rxData = tmpData; + handle->rxData++; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + *((uint16_t *)(handle->rxData)) = tmpData; + } + else + { + *((uint16_t *)(handle->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); + } + handle->rxData += 2U; + } + } + handle->rxRemainingBytes -= handle->bytePerFrame; +} + +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base); + assert(masterConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Master */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for SCK. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = srcClock_Hz / masterConfig->baudRate_Bps; + timerDiv = timerDiv / 2 - 1; + + timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for CSn. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->CSnPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + timerConfig.timerCompare = 0xFFFFU; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); +} + +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; +} + +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) +{ + assert(masterConfig); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + /* Default baud rate 500kbps. */ + masterConfig->baudRate_Bps = 500000U; + /* Default CPHA = 0. */ + masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + masterConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) +{ + assert(base && slaveConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Slave */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); + if (!slaveConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for shift clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous + PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + } + else + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + } + + timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); +} + +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) +{ + FLEXIO_SPI_MasterDeinit(base); +} + +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + slaveConfig->enableSlave = true; + slaveConfig->enableInDoze = false; + slaveConfig->enableInDebug = true; + slaveConfig->enableFastAccess = false; + /* Default CPHA = 0. */ + slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); + } +} + +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); + } +} + +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) +{ + if (mask & kFLEXIO_SPI_TxDmaEnable) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable); + } + + if (mask & kFLEXIO_SPI_RxDmaEnable) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable); + } +} + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) +{ + uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); + uint32_t status = 0; + + status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); + + return status; +} + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxBufferEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxBufferFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = srcClockHz / baudRate_Bps; + timerDiv = timerDiv / 2 - 1U; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0xFF00U; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size) +{ + assert(buffer); + assert(size); + + while (size--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) + { + } + FLEXIO_SPI_WriteData(base, direction, *buffer++); + } +} + +void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size) +{ + assert(buffer); + assert(size); + + while (size--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) + { + } + *buffer++ = FLEXIO_SPI_ReadData(base, direction); + } +} + +void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) +{ + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + timerCmp &= 0x00FFU; + /* Configure the values in handle. */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case kFLEXIO_SPI_8bitLsb: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case kFLEXIO_SPI_16bitMsb: + dataMode = (16 * 2 - 1U) << 8U; + bytesPerFrame = 2; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case kFLEXIO_SPI_16bitLsb: + dataMode = (16 * 2 - 1U) << 8U; + bytesPerFrame = 2; + direction = kFLEXIO_SPI_LsbFirst; + break; + + default: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + while (xfer->dataSize) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) + { + } + if (xfer->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (bytesPerFrame == 1U) + { + tmpData = *(xfer->txData); + xfer->txData++; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 8U; + tmpData += xfer->txData[1]; + } + else + { + tmpData = (uint32_t)(xfer->txData[1]) << 8U; + tmpData += xfer->txData[0]; + } + xfer->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + xfer->dataSize -= bytesPerFrame; + + FLEXIO_SPI_WriteData(base, direction, tmpData); + + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) + { + } + tmpData = FLEXIO_SPI_ReadData(base, direction); + + if (xfer->rxData != NULL) + { + if (bytesPerFrame == 1U) + { + *xfer->rxData = tmpData; + xfer->rxData++; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + *((uint16_t *)(xfer->rxData)) = tmpData; + } + else + { + *((uint16_t *)(xfer->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); + } + xfer->rxData += 2U; + } + } + } +} + +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); +} + +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + timerCmp &= 0x00FFU; + + /* Check if SPI is busy. */ + if (handle->state == kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Configure the values in handle */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + dataMode = (16 * 2 - 1U) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + dataMode = (16 * 2 - 1U) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Send first byte of data to trigger the rx interrupt. */ + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = *(handle->txData); + handle->txData++; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += handle->txData[0]; + } + handle->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + /* Enable transmit and receive interrupt to handle rx. */ + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Return remaing bytes in different cases. */ + if (handle->rxData) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + + return kStatus_Success; +} + +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + assert(handle); + + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + + /* Transfer finished, set the state to idle. */ + handle->state = kFLEXIO_SPI_Idle; + + /* Clear the internal state. */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle rx. */ + if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* Handle tx. */ + if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_MasterTransferAbort(base, handle); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); +} + +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + + /* Check if SPI is busy. */ + if (handle->state == kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Configure the values in handle */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + dataMode = 16 * 2 - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + dataMode = 16 * 2 - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Enable transmit and receive interrupt to handle tx and rx. */ + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle tx. */ + if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* Handle rx. */ + if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_SlaveTransferAbort(base, handle); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi.h new file mode 100644 index 0000000000..e72f6e09cd --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi.h @@ -0,0 +1,707 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXIO_SPI_H_ +#define _FSL_FLEXIO_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI driver version 2.1.3. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*@}*/ + +#ifndef FLEXIO_SPI_DUMMYDATA +/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ +#define FLEXIO_SPI_DUMMYDATA (0xFFFFU) +#endif + +/*! @brief Error codes for the FlexIO SPI driver. */ +enum _flexio_spi_status +{ + kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ + kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ + kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ +}; + +/*! @brief FlexIO SPI clock phase configuration. */ +typedef enum _flexio_spi_clock_phase +{ + kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. */ + kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer. */ +} flexio_spi_clock_phase_t; + +/*! @brief FlexIO SPI data shifter direction options. */ +typedef enum _flexio_spi_shift_direction +{ + kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ + kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ +} flexio_spi_shift_direction_t; + +/*! @brief FlexIO SPI data length mode options. */ +typedef enum _flexio_spi_data_bitcount_mode +{ + kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ + kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ +} flexio_spi_data_bitcount_mode_t; + +/*! @brief Define FlexIO SPI interrupt mask. */ +enum _flexio_spi_interrupt_enable +{ + kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO SPI status mask. */ +enum _flexio_spi_status_flags +{ + kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO SPI DMA mask. */ +enum _flexio_spi_dma_enable +{ + kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ + kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ +}; + +/*! @brief Define FlexIO SPI transfer flags. */ +enum _flexio_spi_transfer_flags +{ + kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ + kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ +}; + +/*! @brief Define FlexIO SPI access structure typedef. */ +typedef struct _flexio_spi_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDOPinIndex; /*!< Pin select for data output. */ + uint8_t SDIPinIndex; /*!< Pin select for data input. */ + uint8_t SCKPinIndex; /*!< Pin select for clock. */ + uint8_t CSnPinIndex; /*!< Pin select for enable. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ +} FLEXIO_SPI_Type; + +/*! @brief Define FlexIO SPI master configuration structure. */ +typedef struct _flexio_spi_master_config +{ + bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_master_config_t; + +/*! @brief Define FlexIO SPI slave configuration structure. */ +typedef struct _flexio_spi_slave_config +{ + bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_slave_config_t; + +/*! @brief Define FlexIO SPI transfer structure. */ +typedef struct _flexio_spi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t dataSize; /*!< Transfer bytes. */ + uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ +} flexio_spi_transfer_t; + +/*! @brief typedef for flexio_spi_master_handle_t in advance. */ +typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO SPI handle structure. */ +struct _flexio_spi_master_handle +{ + uint8_t *txData; /*!< Transfer buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ + volatile uint32_t state; /*!< FlexIO SPI internal state. */ + uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ + flexio_spi_shift_direction_t direction; /*!< Shift direction. */ + flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO SPI Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO SPI timer and shifter config. + * + * @param base Pointer to the FLEXIO_SPI_Type. +*/ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + @code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + @endcode + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + @endcode + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); + +/*! + * @brief Gates the FlexIO clock. + * + * @param base Pointer to the FLEXIO_SPI_Type. +*/ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + @code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + @endcode + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @return status flag; Use the status flag to AND the following flag mask and get the status. + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag +*/ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); + +/*! + * @brief Clears FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask status flag + * The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag +*/ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source. The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask SPI DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI transmit data register address. + */ +static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, + base->shifterIndex[0]) + + 3U; + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); + } +} + +/*! + * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI receive data register address. + */ +static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U; + } +} + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI module operation. + * + * @param base Pointer to the FLEXIO_SPI_Type. + * @param enable True to enable, false does not have any effect. +*/ +static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param baudRate_Bps Baud Rate needed in Hz. + * @param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); + +/*! + * @brief Writes one byte of data, which is sent using the MSB method. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param data 8 bit/16 bit data. + */ +static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; + } + else + { + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; + } +} + +/*! + * @brief Reads 8 bit/16 bit data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return 8 bit/16 bit data received. + */ +static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; + } + else + { + return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + } +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The data bytes to send. + * @param size The number of data bytes to send. + */ +void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The buffer to store the received bytes. + * @param size The number of data bytes to be received. + * @param direction Shift direction of MSB first or LSB first. + */ +void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + */ +void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the master data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO SPI master IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); + +/*! + * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the slave data transfer which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbort(base, handle); +} +/*! + * @brief Gets the data transfer status which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief FlexIO SPI slave IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_SPI_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.c new file mode 100644 index 0000000000..2c6aeda82b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.c @@ -0,0 +1,442 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_spi_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma" +#endif + +/*base, kFLEXIO_SPI_TxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; + + if (transferDone) + { + /* Disable Rx dma */ + FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_RxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + edma_transfer_config_t xferConfig; + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + + /* Configure the values in handle. */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + bytesPerFrame = 2; + direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + bytesPerFrame = 2; + direction = kFLEXIO_SPI_LsbFirst; + break; + default: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Configure tx transfer EDMA. */ + xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); + xferConfig.destOffset = 0; + if (bytesPerFrame == 1U) + { + xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.minorLoopBytes = 1; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 1U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.minorLoopBytes = 2; + } + + /* Configure DMA channel. */ + if (xfer->txData) + { + xferConfig.srcOffset = bytesPerFrame; + xferConfig.srcAddr = (uint32_t)(xfer->txData); + } + else + { + /* Disable the source increasement and source set to dummyData. */ + xferConfig.srcOffset = 0; + xferConfig.srcAddr = (uint32_t)(&s_dummyData); + } + + xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */ + handle->nbytes = xferConfig.minorLoopBytes; + + if (handle->txHandle) + { + EDMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + + /* Configure tx transfer EDMA. */ + if (xfer->rxData) + { + xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); + if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 1U; + } + } + xferConfig.srcOffset = 0; + xferConfig.destAddr = (uint32_t)(xfer->rxData); + xferConfig.destOffset = bytesPerFrame; + EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true); + EDMA_StartTransfer(handle->rxHandle); + } + + /* Always start Tx transfer. */ + if (handle->txHandle) + { + handle->txInProgress = true; + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true); + EDMA_StartTransfer(handle->txHandle); + } +} + +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + assert(handle); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_SPI_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_SPI_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + /* Set spi base to handle. */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle. */ + handle->txInProgress = false; + handle->rxInProgress = false; + + /* Install callback for Tx/Rx dma channel. */ + if (handle->txHandle) + { + EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]); + } + if (handle->rxHandle) + { + EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]); + } + + return kStatus_Success; +} + +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + + timerCmp &= 0x00FFU; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) + { + dataMode = (8 * 2 - 1U) << 8U; + } + else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) + { + dataMode = (16 * 2 - 1U) << 8U; + } + else + { + dataMode = 8 * 2 - 1U; + } + + dataMode |= timerCmp; + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + FLEXIO_SPI_EDMAConfig(base, handle, xfer); + + return kStatus_Success; +} + +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->rxInProgress) + { + *count = (handle->transferSize - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel)); + } + else + { + *count = (handle->transferSize - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel)); + } + + return kStatus_Success; +} + +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma. */ + EDMA_StopTransfer(handle->txHandle); + EDMA_StopTransfer(handle->rxHandle); + + /* Disable DMA enable bit. */ + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_DmaAllEnable, false); + + /* Set the handle state. */ + handle->txInProgress = false; + handle->rxInProgress = false; +} + +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) + { + dataMode = 8 * 2 - 1U; + } + else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) + { + dataMode = 16 * 2 - 1U; + } + else + { + dataMode = 8 * 2 - 1U; + } + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + FLEXIO_SPI_EDMAConfig(base, handle, xfer); + + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.h new file mode 100644 index 0000000000..5dba8de5a1 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_spi_edma.h @@ -0,0 +1,233 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_SPI_EDMA_H_ +#define _FSL_FLEXIO_SPI_EDMA_H_ + +#include "fsl_flexio_spi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI EDMA driver version 2.1.3. */ +#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*@}*/ + +/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ +typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_spi_master_edma_handle +{ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + bool txInProgress; /*!< Send transfer in progress */ + bool rxInProgress; /*!< Receive transfer in progress */ + edma_handle_t *txHandle; /*!< DMA handler for SPI send */ + edma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle); + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO SPI eDMA transfer. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count); + +/*! + * @brief Initializes the FlexIO SPI slave eDMA handle. + * + * This function initializes the FlexIO SPI slave eDMA handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + */ +static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbortEDMA(base, handle); +} + +/*! + * @brief Gets the remaining bytes to be transferred for FlexIO SPI eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart.c new file mode 100644 index 0000000000..fd7d550ad4 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart.c @@ -0,0 +1,730 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart" +#endif + + +/*flexioBase); +} + +static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) +{ + bool full; + + if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) +{ + assert(base && userConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + status_t result = kStatus_Success; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO UART */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->TxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /*2. Configure the timer 0 for tx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->TxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = srcClock_Hz / userConfig->baudRate_Bps; + timerDiv = timerDiv / 2 - 1; + + if (timerDiv > 0xFFU) + { + result = kStatus_InvalidArgument; + } + + timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 3. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->RxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /* 4. Configure the timer 1 for rx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->RxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + return result; +} + +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); +} + +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) +{ + assert(userConfig); + + userConfig->enableUart = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; + /* Default baud rate 115200. */ + userConfig->baudRate_Bps = 115200U; + /* Default bit count at 8. */ + userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; +} + +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) +{ + uint32_t status = 0; + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + return status; +} + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } + if (mask & kFLEXIO_UART_RxOverRunFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) +{ + assert(txData); + assert(txSize); + + while (txSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))) + { + } + + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; + } +} + +void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) +{ + assert(rxData); + assert(rxSize); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag)) + { + } + + *rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + } +} + +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kFLEXIO_UART_RxIdle; + handle->txState = kFLEXIO_UART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); +} + +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ringbuffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } +} + +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kFLEXIO_UART_RxIdle) + { + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kFLEXIO_UART_TxBusy; + + /* Enable transmiter interrupt. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Disable the transmitter and disable the interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kFLEXIO_UART_TxIdle; +} + +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle); + assert(count); + + if (kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kFLEXIO_UART_RxBusy; + } + + /* Enable FLEXIO_UART RX IRQ if previously enabled. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kFLEXIO_UART_RxBusy; + + /* Enable RX interrupt. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kFLEXIO_UART_RxIdle; +} + +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle); + assert(count); + + if (kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) +{ + uint8_t count = 1; + FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; + flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; + + /* Read the status back. */ + uint8_t status = FLEXIO_UART_GetStatusFlags(base); + + /* If RX overrun. */ + if (kFLEXIO_UART_RxOverRunFlag & status) + { + /* Clear Overrun flag. */ + FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1]))) + { + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + if (handle->rxDataSize) + { + /* Using non block API to read the data from the registers. */ + FLEXIO_UART_ReadByte(base, handle->rxData); + handle->rxDataSize--; + handle->rxData++; + count--; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kFLEXIO_UART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + + if (handle->rxRingBuffer) + { + if (count) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0]))) + { + if (handle->txDataSize) + { + /* Using non block API to write the data to the registers. */ + FLEXIO_UART_WriteByte(base, handle->txData); + handle->txData++; + handle->txDataSize--; + count--; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kFLEXIO_UART_TxIdle; + + /* Disable TX register empty interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); + } + } + } + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart.h new file mode 100644 index 0000000000..356752a14a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart.h @@ -0,0 +1,586 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXIO_UART_H_ +#define _FSL_FLEXIO_UART_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART driver version 2.1.4. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _flexio_uart_status +{ + kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ + kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ + kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ + kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ + kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ + kStatus_FLEXIO_UART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ + kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */ +}; + +/*! @brief FlexIO UART bit count per char. */ +typedef enum _flexio_uart_bit_count_per_char +{ + kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ + kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ + kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ +} flexio_uart_bit_count_per_char_t; + +/*! @brief Define FlexIO UART interrupt mask. */ +enum _flexio_uart_interrupt_enable +{ + kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO UART status mask. */ +enum _flexio_uart_status_flags +{ + kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ +}; + +/*! @brief Define FlexIO UART access structure typedef. */ +typedef struct _flexio_uart_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ + uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ +} FLEXIO_UART_Type; + +/*! @brief Define FlexIO UART user configuration structure. */ +typedef struct _flexio_uart_config +{ + bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ +} flexio_uart_config_t; + +/*! @brief Define FlexIO UART transfer structure. */ +typedef struct _flexio_uart_transfer +{ + uint8_t *data; /*!< Transfer buffer*/ + size_t dataSize; /*!< Transfer size*/ +} flexio_uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_handle flexio_uart_handle_t; + +/*! @brief FlexIO UART transfer callback function. */ +typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FLEXIO UART handle structure*/ +struct _flexio_uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + flexio_uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + @code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param userConfig Pointer to the flexio_uart_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Configuration success + * @retval kStatus_InvalidArgument Buadrate configuration out of range +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO UART shifter and timer config. + * + * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * @param base Pointer to FLEXIO_UART_Type structure +*/ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + @code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + @endcode + * @param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART status flags. +*/ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_UART_TxDataRegEmptyFlag + * @arg kFLEXIO_UART_RxEmptyFlag + * @arg kFLEXIO_UART_RxOverRunFlag +*/ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the FlexIO UARt transmit data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART transmit data register address. + */ +static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); +} + +/*! + * @brief Gets the FlexIO UART receive data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART receive data register address. + */ +static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); +} + +/*! + * @brief Enables/disables the FlexIO UART transmit DMA. + * This function enables/disables the FlexIO UART Tx DMA, + * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[0], enable); +} + +/*! + * @brief Enables/disables the FlexIO UART receive DMA. + * This function enables/disables the FlexIO UART Rx DMA, + * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[1], enable); +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO UART module operation. + * + * @param base Pointer to the FLEXIO_UART_Type. + * @param enable True to enable, false does not have any effect. +*/ +static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Writes one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register. Ensure that the TxEmptyFlag is asserted before calling + * this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The data bytes to send. + */ +static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) +{ + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; +} + +/*! + * @brief Reads one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The buffer to store the received bytes. + */ +static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) +{ + *buffer = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param txData The data bytes to send. + * @param txSize The number of data bytes to send. + */ +void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param rxData The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + */ +void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base to FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * @retval kStatus_Success Successfully starts the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer UART transfer structure. See #flexio_uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * @param uartType Pointer to the FLEXIO_UART_Type structure. + * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_UART_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.c new file mode 100644 index 0000000000..3b008e620f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.c @@ -0,0 +1,360 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_uart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" +#endif + + +/*handle); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); + } + } +} + +static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, + void *param, + bool transferDone, + uint32_t tcds) +{ + flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param; + + assert(uartPrivateHandle->handle); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); + } + } +} + +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_UART_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kFLEXIO_UART_RxIdle; + handle->txState = kFLEXIO_UART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle); + } + + return kStatus_Success; +} + +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txState = kFLEXIO_UART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + handle->rxState = kFLEXIO_UART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle); + + /* Disable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->txEdmaHandle); + + handle->txState = kFLEXIO_UART_TxIdle; +} + +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle); + + /* Disable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->rxEdmaHandle); + + handle->rxState = kFLEXIO_UART_RxIdle; +} + +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count) +{ + assert(handle); + assert(handle->rxEdmaHandle); + assert(count); + + if (kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) +{ + assert(handle); + assert(handle->txEdmaHandle); + assert(count); + + if (kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.h new file mode 100644 index 0000000000..153525abf3 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexio_uart_edma.h @@ -0,0 +1,204 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_UART_EDMA_H_ +#define _FSL_FLEXIO_UART_EDMA_H_ + +#include "fsl_flexio_uart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART EDMA driver version 2.1.4. */ +#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART eDMA handle +*/ +struct _flexio_uart_edma_handle +{ + flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_UART_Type. + * @param handle Pointer to flexio_uart_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_EDMA_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexram.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexram.c new file mode 100644 index 0000000000..45e3f62be2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexram.c @@ -0,0 +1,233 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexram.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexram" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base FLEXRAM base address + * + * @return The FLEXRAM instance + */ +static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base); + +/*! + * @brief FLEXRAM map TCM size to register value + * + * @param tcmBankNum tcm banknumber + * @retval register value correspond to the tcm size + */ +static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum); + +/*! + * @brief FLEXRAM configure TCM size + * This function is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will + * raised by core. + * @param itcmBankNum itcm bank number to allocate + * @param dtcmBankNum dtcm bank number to allocate + */ +static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to FLEXRAM bases for each instance. */ +static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FLEXRAM clocks for each instance. */ +static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++) + { + if (s_flexramBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexramBases)); + + return instance; +} + +void FLEXRAM_Init(FLEXRAM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* enable all the interrupt status */ + base->INT_STAT_EN |= kFLEXRAM_InterruptStatusAll; + /* clear all the interrupt status */ + base->INT_STATUS |= kFLEXRAM_InterruptStatusAll; + /* disable all the interrpt */ + base->INT_SIG_EN = 0U; +} + +void FLEXRAN_Deinit(FLEXRAM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum) +{ + uint8_t tcmSizeConfig = 0U; + + switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE) + { + case kFLEXRAM_TCMSize32KB: + tcmSizeConfig = 6U; + break; + + case kFLEXRAM_TCMSize64KB: + tcmSizeConfig = 7U; + break; + + case kFLEXRAM_TCMSize128KB: + tcmSizeConfig = 8U; + break; + + case kFLEXRAM_TCMSize256KB: + tcmSizeConfig = 9U; + break; + + case kFLEXRAM_TCMSize512KB: + tcmSizeConfig = 10U; + break; + + default: + break; + } + + return tcmSizeConfig; +} + +static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) +{ + /* dtcm configuration */ + if (dtcmBankNum != 0U) + { + IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK; + IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum)); + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; + } + else + { + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; + } + /* itcm configuration */ + if (itcmBankNum != 0U) + { + IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK; + IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum)); + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; + } + else + { + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; + } + + return kStatus_Success; +} + +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) +{ + uint8_t dtcmBankNum = config->dtcmBankNum; + uint8_t itcmBankNum = config->itcmBankNum; + uint8_t ocramBankNum = config->ocramBankNum; + uint32_t bankCfg = 0U, i = 0U; + + /* check the arguments */ + if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) || + ((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) || + ((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U))) + { + return kStatus_InvalidArgument; + } + /* flexram bank config value */ + for (i = 0U; i < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++) + { + if (i < ocramBankNum) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum + itcmBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2); + continue; + } + } + IOMUXC_GPR->GPR17 = bankCfg; + /* set TCM size */ + FLEXRAM_SetTCMSize(itcmBankNum, dtcmBankNum); + /* select ram allocate source from FLEXRAM_BANK_CFG */ + FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg); + + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexram.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexram.h new file mode 100644 index 0000000000..b84e8daec9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexram.h @@ -0,0 +1,323 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXRAM_H_ +#define _FSL_FLEXRAM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexram + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.2. */ +#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) +/*@}*/ + +/*! @brief flexram write read sel */ +enum _flexram_wr_rd_sel +{ + kFLEXRAM_Read = 0U, /*!< read */ + kFLEXRAM_Write = 1U, /*!< write */ +}; + +/*! @brief Interrupt status flag mask */ +enum _flexram_interrupt_status +{ + kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */ + kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ + kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ + kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */ + kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< dtcm maigc address match */ + kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< itcm maigc address match */ + + kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */ +}; + +/*! @brief FLEXRAM TCM access mode +* Fast access mode expected to be finished in 1-cycle +* Wait access mode expected to be finished in 2-cycle +* Wait access mode is a feature of the flexram and it should be used when +* the cpu clock too fast to finish tcm access in 1-cycle. +* Normally, fast mode is the default mode, the efficiency of the tcm access will better. +*/ +typedef enum _flexram_tcm_access_mode +{ + kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */ + kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */ +} flexram_tcm_access_mode_t; + +/*! @brief FLEXRAM bank type */ +enum _flexram_bank_type +{ + kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */ + kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ + kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ + kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ +}; + +/*! @brief FLEXRAM tcm support size */ +enum _flexram_tcm_size +{ + kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */ + kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */ + kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */ + kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */ + kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */ +}; + +/*! @brief FLEXRAM bank allocate source */ +typedef enum _flexram_bank_allocate_src +{ + kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */ + kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ +} flexram_bank_allocate_src_t; + +/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */ +typedef struct _flexram_allocate_ram +{ + const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */ + const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */ + const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */ +} flexram_allocate_ram_t; +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief FLEXRAM module initialization function. + * + * @param base FLEXRAM base address. + */ +void FLEXRAM_Init(FLEXRAM_Type *base); + +/*! + * @brief Deinitializes the FLEXRAM. + * + */ +void FLEXRAN_Deinit(FLEXRAM_Type *base); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief FLEXRAM module get interrupt status. + * + * @param base FLEXRAM base address. + */ +static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base) +{ + return base->INT_STATUS & kFLEXRAM_InterruptStatusAll; +} + +/*! + * @brief FLEXRAM module clear interrupt status. + * + * @param base FLEXRAM base address. + * @param status status to clear. + */ +static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STATUS |= status; +} + +/*! + * @brief FLEXRAM module enable interrupt status. + * + * @param base FLEXRAM base address. + * @param status status to enable. + */ +static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STAT_EN |= status; +} + +/*! + * @brief FLEXRAM module disable interrupt status. + * + * @param base FLEXRAM base address. + * @param status status to disable. + */ +static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STAT_EN &= ~status; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief FLEXRAM module enable interrupt. + * + * @param base FLEXRAM base address. + * @param status status interrupt to enable. + */ +static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_SIG_EN |= status; +} + +/*! + * @brief FLEXRAM module disable interrupt. + * + * @param base FLEXRAM base address. + * @param status status interrupt to disable. + */ +static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_SIG_EN &= ~status; +} +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief FLEXRAM module set TCM read access mode + * + * @param base FLEXRAM base address. + * @param mode access mode. + */ +static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) +{ + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK; + base->TCM_CTRL |= mode; +} + +/*! + * @brief FLEXRAM module set TCM write access mode + * + * @param base FLEXRAM base address. + * @param mode access mode. + */ +static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) +{ + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK; + base->TCM_CTRL |= mode; +} + +/*! + * @brief FLEXRAM module force ram clock on + * + * @param base FLEXRAM base address. + * @param enable enable or disable clock force on. + */ +static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable) +{ + if (enable) + { + base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; + } + else + { + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; + } +} + +/*! + * @brief FLEXRAM OCRAM magic addr configuration + * When read/write access hit magic address, it will generate interrupt + * @param magicAddr magic address. + * @param rwsel read write select, 0 read access , 1 write access + */ +static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) +{ + base->OCRAM_MAGIC_ADDR = + FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U); +} + +/*! + * @brief FLEXRAM DTCM magic addr configuration + * When read/write access hit magic address, it will generate interrupt + * @param magicAddr magic address. + * @param rwsel read write select, 0 read access , 1 write access + */ +static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) +{ + base->DTCM_MAGIC_ADDR = + FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U); +} + +/*! + * @brief FLEXRAM ITCM magic addr configuration + * When read/write access hit magic address, it will generate interrupt + * @param magicAddr magic address. + * @param rwsel read write select, 0 read access , 1 write access + */ +static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) +{ + base->ITCM_MAGIC_ADDR = + FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U); +} + +/*! + * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * @param config allocate configuration. + * @retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); + +/*! + * @brief FLEXRAM set allocate on-chip ram source + * @param src bank config source select value. + */ +static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src) +{ + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK; + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src); +} + +/*! @}*/ + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c new file mode 100644 index 0000000000..d74ab47e23 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c @@ -0,0 +1,868 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexspi" +#endif + + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +#define FREQ_1MHz (1000000UL) +#define FLEXSPI_DLLCR_DEFAULT (0x100UL) +#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul) + +enum +{ + kFLEXSPI_DelayCellUnitMin = 75, /* 75ps. */ + kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _flexspi_flag_constants +{ + /*! IRQ sources enabled by the non-blocking transactional API. */ + kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag, + + /*! Errors to check for. */ + kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag, +}; + +enum _flexspi_transfer_state +{ + kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ + kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ + kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, void *flexspiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! +* @brief Get the instance number for FLEXSPI. +* +* @param base FLEXSPI base pointer. +*/ +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); + +/*! +* @brief Configure flash A/B sample clock DLL. +* +* @param base FLEXSPI base pointer. +* @param config Flash configuration parameters. +*/ +static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config); + +/*! +* @brief Check and clear IP command execution errors. +* +* @param base FLEXSPI base pointer. +* @param status interrupt status. +*/ +status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +/*! @brief Pointers to flexspi handles for each instance. */ +static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT]; +#endif + +/*! @brief Pointers to flexspi bases for each instance. */ +static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; + +/*! @brief Pointers to flexspi IRQ number for each instance. */ +static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FLEXSPI_COUNT; instance++) + { + if (s_flexspiBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FLEXSPI_COUNT); + + return instance; +} + +static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) +{ + bool isUnifiedConfig = true; + uint32_t flexspiDllValue; + uint32_t dllValue; + uint32_t temp; + + uint8_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT; + switch (rxSampleClock) + { + case kFLEXSPI_ReadSampleClkLoopbackInternally: + case kFLEXSPI_ReadSampleClkLoopbackFromDqsPad: + case kFLEXSPI_ReadSampleClkLoopbackFromSckPad: + isUnifiedConfig = true; + break; + case kFLEXSPI_ReadSampleClkExternalInputFromDqsPad: + if (config->isSck2Enabled) + { + isUnifiedConfig = true; + } + else + { + isUnifiedConfig = false; + } + break; + default: + break; + } + + if (isUnifiedConfig) + { + flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */ + } + else + { + if (config->flexspiRootClk >= 100 * FREQ_1MHz) + { + /* DLLEN = 1, SLVDLYTARGET = 0xF, */ + flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F); + } + else + { + temp = config->dataValidTime * 1000; /* Convert data valid time in ns to ps. */ + dllValue = temp / kFLEXSPI_DelayCellUnitMin; + if (dllValue * kFLEXSPI_DelayCellUnitMin < temp) + { + dllValue++; + } + flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue); + } + } + return flexspiDllValue; +} + +status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. */ + status &= kErrorFlags; + if (status) + { + /* Select the correct error code.. */ + if (status & kFLEXSPI_SequenceExecutionTimeoutFlag) + { + result = kStatus_FLEXSPI_SequenceExecutionTimeout; + } + else if (status & kFLEXSPI_IpCommandSequenceErrorFlag) + { + result = kStatus_FLEXSPI_IpCommandSequenceError; + } + else if (status & kFLEXSPI_IpCommandGrantTimeoutFlag) + { + result = kStatus_FLEXSPI_IpCommandGrantTimeout; + } + else + { + assert(false); + } + + /* Clear the flags. */ + FLEXSPI_ClearInterruptStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + } + + return result; +} + +void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) +{ + uint32_t configValue = 0; + uint8_t i = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the flexspi clock */ + CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]); + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset peripheral before configuring it. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + FLEXSPI_SoftwareReset(base); + + /* Configure MCR0 configuration items. */ + configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) | + FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) | + FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) | + FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) | + FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) | + FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) | + FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) | + FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK; + base->MCR0 = configValue; + + /* Configure MCR1 configurations. */ + configValue = + FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle); + base->MCR1 = configValue; + + /* Configure MCR2 configurations. */ + configValue = base->MCR2; + configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK | + FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); + configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | + FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | + FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | + FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); + + base->MCR2 = configValue; + + /* Configure AHB control items. */ + configValue = base->AHBCR; + configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | + FLEXSPI_AHBCR_CACHABLEEN_MASK); + configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | + FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | + FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | + FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); + base->AHBCR = configValue; + + /* Configure AHB rx buffers. */ + for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + configValue = base->AHBRXBUFCR0[i]; + + configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | + FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); + configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) | + FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | + FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | + FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize * 8); + base->AHBRXBUFCR0[i] = configValue; + } + + /* Configure IP Fifo watermarks. */ + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1); + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1); +} + +void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) +{ + config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; + config->enableSckFreeRunning = false; + config->enableCombination = false; + config->enableDoze = true; + config->enableHalfSpeedAccess = false; + config->enableSckBDiffOpt = false; + config->enableSameConfigForAll = false; + config->seqTimeoutCycle = 0xFFFFU; + config->ipGrantTimeoutCycle = 0xFFU; + config->txWatermark = 8; + config->rxWatermark = 8; + config->ahbConfig.enableAHBWriteIpTxFifo = false; + config->ahbConfig.enableAHBWriteIpRxFifo = false; + config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; + config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; + config->ahbConfig.resumeWaitCycle = 0x20U; + memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); + for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/ + } + config->ahbConfig.enableClearAHBBufferOpt = false; + config->ahbConfig.enableReadAddressOpt = false; + config->ahbConfig.enableAHBPrefetch = false; + config->ahbConfig.enableAHBBufferable = false; + config->ahbConfig.enableAHBCachable = false; +} + +void FLEXSPI_Deinit(FLEXSPI_Type *base) +{ + /* Reset peripheral. */ + FLEXSPI_SoftwareReset(base); +} + +void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) +{ + uint32_t configValue = 0; + uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */ + + /* Wait for bus idle before change flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Configure flash size. */ + base->FLSHCR0[index] = 0; + base->FLSHCR0[port] = config->flashSize; + + /* Configure flash parameters. */ + base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) | + FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) | + FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) | + FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress); + + /* Configure AHB operation items. */ + configValue = base->FLSHCR2[port]; + + configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK | + FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_AWRSEQID_MASK); + + configValue |= + FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval); + + if (config->AWRSeqNumber > 0U) + { + configValue |= + FLEXSPI_FLSHCR2_AWRSEQID(config->AWRSeqIndex) | FLEXSPI_FLSHCR2_AWRSEQNUM(config->AWRSeqNumber - 1U); + } + + if (config->ARDSeqNumber > 0U) + { + configValue |= + FLEXSPI_FLSHCR2_ARDSEQID(config->ARDSeqIndex) | FLEXSPI_FLSHCR2_ARDSEQNUM(config->ARDSeqNumber - 1U); + } + + base->FLSHCR2[port] = configValue; + + /* Configure DLL. */ + base->DLLCR[index] = FLEXSPI_ConfigureDll(base, config); + + /* Configure write mask. */ + if (config->enableWriteMask) + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + else + { + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + + if (index == 0) /*PortA*/ + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask); + } + else + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK; + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask); + } + + /* Exit stop mode. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; +} + +void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) +{ + assert(index < 64U); + + uint8_t i = 0; + volatile uint32_t *lutBase; + + /* Wait for bus idle before change flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Unlock LUT for update. */ + base->LUTKEY = FLEXSPI_LUT_KEY_VAL; + base->LUTCR = 0x02; + + lutBase = &base->LUT[index]; + for (i = index; i < count; i++) + { + *lutBase++ = *cmd++; + } + + /* Lock LUT. */ + base->LUTKEY = FLEXSPI_LUT_KEY_VAL; + base->LUTCR = 0x01; +} + +status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; + uint32_t status; + status_t result = kStatus_Success; + uint32_t i = 0; + + /* Send data buffer */ + while (size) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + while (!((status = base->INTR) & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag)) + { + } + + result = FLEXSPI_CheckAndClearError(base, status); + + if (result) + { + return result; + } + + /* Write watermark level data into tx fifo . */ + if (size >= 8 * txWatermark) + { + for (i = 0; i < 2 * txWatermark; i++) + { + base->TFDR[i] = *buffer++; + } + + size = size - 8 * txWatermark; + } + else + { + for (i = 0; i < (size / 4 + 1); i++) + { + base->TFDR[i] = *buffer++; + } + size = 0; + } + + /* Push a watermark level datas into IP TX FIFO. */ + base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag; + } + + return result; +} + +status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; + uint32_t status; + status_t result = kStatus_Success; + uint32_t i = 0; + + /* Send data buffer */ + while (size) + { + if (size >= 8 * rxWatermark) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + while (!((status = base->INTR) & kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) + { + result = FLEXSPI_CheckAndClearError(base, status); + + if (result) + { + return result; + } + } + } + else + { + /* Wait fill level. This also checks for errors. */ + while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U)) + { + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + if (result) + { + return result; + } + } + } + + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + if (result) + { + return result; + } + + /* Read watermark level data from rx fifo . */ + if (size >= 8 * rxWatermark) + { + for (i = 0; i < 2 * rxWatermark; i++) + { + *buffer++ = base->RFDR[i]; + } + + size = size - 8 * rxWatermark; + } + else + { + for (i = 0; i < (size / 4 + 1); i++) + { + *buffer++ = base->RFDR[i]; + } + size = 0; + } + + /* Pop out a watermark level datas from IP RX FIFO. */ + base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + } + + return result; +} + +status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this tranfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base addresss. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1); + base->IPCR1 = configValue; + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + result = FLEXSPI_WriteBlocking(base, xfer->data, xfer->dataSize); + } + else if (xfer->cmdType == kFLEXSPI_Read) + { + result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize); + } + else + { + } + + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + if (xfer->cmdType == kFLEXSPI_Command) + { + result = FLEXSPI_CheckAndClearError(base, base->INTR); + } + + return result; +} + +void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, + flexspi_handle_t *handle, + flexspi_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = FLEXSPI_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ + /* Save the context in global variables to support the double weak mechanism. */ + s_flexspiHandle[instance] = handle; +#endif + + /* Enable NVIC interrupt. */ + EnableIRQ(s_flexspiIrqs[instance]); +} + +status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + assert(handle); + assert(xfer); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kFLEXSPI_Idle) + { + result = kStatus_FLEXSPI_Busy; + } + else + { + handle->data = xfer->data; + handle->dataSize = xfer->dataSize; + handle->transferTotalSize = xfer->dataSize; + handle->state = (xfer->cmdType == kFLEXSPI_Read) ? kFLEXSPI_BusyRead : kFLEXSPI_BusyWrite; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this tranfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base addresss. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1); + base->IPCR1 = configValue; + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + if (handle->state == kFLEXSPI_BusyRead) + { + FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpRxFifoWatermarkAvailableFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | + kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag); + } + else + { + FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | + kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag); + } + } + + return result; +} + +status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t result = kStatus_Success; + + if (handle->state == kFLEXSPI_Idle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferTotalSize - handle->dataSize; + } + + return result; +} + +void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) +{ + assert(handle); + + FLEXSPI_DisableInterrupts(base, kIrqFlags); + handle->state = kFLEXSPI_Idle; +} + +void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) +{ + uint8_t status; + status_t result; + uint8_t txWatermark; + uint8_t rxWatermark; + uint8_t i = 0; + + status = base->INTR; + + result = FLEXSPI_CheckAndClearError(base, status); + + if ((result != kStatus_Success) && (handle->completionCallback != NULL)) + { + FLEXSPI_TransferAbort(base, handle); + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + return; + } + + if ((status & kFLEXSPI_IpRxFifoWatermarkAvailableFlag) && (handle->state == kFLEXSPI_BusyRead)) + { + rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; + + /* Read watermark level data from rx fifo . */ + if (handle->dataSize >= 8 * rxWatermark) + { + /* Read watermark level data from rx fifo . */ + for (i = 0; i < 2 * rxWatermark; i++) + { + *handle->data++ = base->RFDR[i]; + } + + handle->dataSize = handle->dataSize - 8 * rxWatermark; + } + else + { + for (i = 0; i < (handle->dataSize / 4 + 1); i++) + { + *handle->data++ = base->RFDR[i]; + } + handle->dataSize = 0; + } + /* Pop out a watermark level datas from IP RX FIFO. */ + base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + } + + if (status & kFLEXSPI_IpCommandExcutionDoneFlag) + { + base->INTR |= kFLEXSPI_IpCommandExcutionDoneFlag; + + FLEXSPI_TransferAbort(base, handle); + + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + } + + /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */ + if ((status & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag) && (handle->state == kFLEXSPI_BusyWrite)) + { + if (handle->dataSize) + { + txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; + /* Write watermark level data into tx fifo . */ + if (handle->dataSize >= 8 * txWatermark) + { + for (i = 0; i < 2 * txWatermark; i++) + { + base->TFDR[i] = *handle->data++; + } + + handle->dataSize = handle->dataSize - 8 * txWatermark; + } + else + { + for (i = 0; i < (handle->dataSize / 4 + 1); i++) + { + base->TFDR[i] = *handle->data++; + } + handle->dataSize = 0; + } + + /* Push a watermark level datas into IP TX FIFO. */ + base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag; + } + } + else + { + } +} + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#if defined(FLEXSPI) +void FLEXSPI_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXSPI0) +void FLEXSPI0_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(FLEXSPI1) +void FLEXSPI1_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h new file mode 100644 index 0000000000..e2f00393b3 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h @@ -0,0 +1,844 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FLEXSPI_H_ +#define __FSL_FLEXSPI_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/*! + * @addtogroup flexspi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLEXSPI driver version 2.0.2. */ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) + +/*! @breif Formula to form FLEXSPI instructions in LUT table. */ +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/*! @brief Status structure of FLEXSPI.*/ +enum _flexspi_status +{ + kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ + kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout + error occurred during FLEXSPI transfer. */ + kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution + timeout error occurred during FLEXSPI transfer. */ + kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error + occurred during FLEXSPI transfer. */ +}; + +/*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */ +enum _flexspi_command +{ + kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ + kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ + kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ + kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ + kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ + kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ + kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ + kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, + dummy cycles decided by RWDS. */ + kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ + kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ + kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ + kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ + kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ + kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ + kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, + dummy cycles decided by RWDS. */ + kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the + instruction start pointer for next sequence */ +}; + +/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */ +enum _flexspi_pad +{ + kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */ + kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */ + kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */ + kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */ +}; + +/*! @brief FLEXSPI interrupt status flags.*/ +typedef enum _flexspi_flags +{ + kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ + kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ + kFLEXSPI_SckStoppedBecauseTxEmptyFlag = + FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command + sequence because Async TX FIFO empty. */ + kFLEXSPI_SckStoppedBecauseRxFullFlag = + FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command + sequence because Async RX FIFO full. */ +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) + kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ +#endif + kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ + kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ + kFLEXSPI_AhbCommandSequenceErrorFlag = + FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ + kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */ + kFLEXSPI_AhbCommandGrantTimeoutFlag = + FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */ + kFLEXSPI_IpCommandGrantTimeoutFlag = + FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */ + kFLEXSPI_IpCommandExcutionDoneFlag = + FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */ + kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */ +} flexspi_flags_t; + +/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/ +typedef enum _flexspi_read_sample_clock +{ + kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller + and loopback internally. */ + kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller + and loopback from DQS pad. */ + kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ + kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ +} flexspi_read_sample_clock_t; + +/*! @brief FLEXSPI interval unit for flash device select.*/ +typedef enum _flexspi_cs_interval_cycle_unit +{ + kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ + kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ +} flexspi_cs_interval_cycle_unit_t; + +/*! @brief FLEXSPI AHB wait interval unit for writting.*/ +typedef enum _flexspi_ahb_write_wait_unit +{ + kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ +} flexspi_ahb_write_wait_unit_t; + +/*! @brief Error Code when IP command Error detected.*/ +typedef enum _flexspi_ip_error_code +{ + kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ + kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR + used in DDR sequence. */ + kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR + used in SDR sequence. */ + kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole + flash address range (A1/A2/B1/B2). */ + kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ + kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ +} flexspi_ip_error_code_t; + +/*! @brief Error Code when AHB command Error detected.*/ +typedef enum _flexspi_ahb_error_code +{ + kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction + used in the sequence. */ + kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used + in DDR sequence. */ + kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR + used in SDR sequence. */ + kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */ +} flexspi_ahb_error_code_t; + +/*! @brief FLEXSPI operation port select.*/ +typedef enum _flexspi_port +{ + kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ + kFLEXSPI_PortA2 = 0x1U, /*!< Access flash on A2 port. */ + kFLEXSPI_PortB1 = 0x2U, /*!< Access flash on B1 port. */ + kFLEXSPI_PortB2 = 0x3U, /*!< Access flash on B2 port. */ +} flexspi_port_t; + +/*! @brief Trigger source of current command sequence granted by arbitrator.*/ +typedef enum _flexspi_arb_command_source +{ + kFLEXSPI_AhbReadCommand = 0x0U, + kFLEXSPI_AhbWriteCommand = 0x1U, + kFLEXSPI_IpCommand = 0x2U, + kFLEXSPI_SuspendedCommand = 0x3U, +} flexspi_arb_command_source_t; + +typedef enum _flexspi_command_type +{ + kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */ + kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */ + kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */ +} flexspi_command_type_t; + +typedef struct _flexspi_ahbBuffer_config +{ + uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ + uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ + uint16_t bufferSize; /*!< AHB buffer size in byte. */ + bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows + prefetch disable/enable seperately for each master. */ +} flexspi_ahbBuffer_config_t; + +/*! @brief FLEXSPI configuration structure. */ +typedef struct _flexspi_config +{ + flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */ + bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */ + bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins + (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ + bool enableDoze; /*!< Enable/disable doze mode support. */ + bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half + speed commands. */ + bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock + output, when enable, Port B flash access is not available. */ + bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices + when enabled, same configuration in FLASHA1CRx is applied to all. */ + uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, + timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */ + uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after + ipGrantTimeoutCycle*1024 AHB clock cycles. */ + uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */ + uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */ + struct + { + bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */ + bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */ + uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant, + timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */ + uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access, + timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ + uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence + resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ + flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ + bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer + when FLEXSPI returns STOP mode ACK. */ + bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. + when eanble, there is no AHB read burst start address alignment limitation. */ + bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI + will fetch more data than current AHB burst. */ + bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, + FLEXSPI return before waiting for command excution finished. */ + bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */ + } ahbConfig; +} flexspi_config_t; + +/*! @brief External device configuration items. */ +typedef struct _flexspi_device_config +{ + uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */ + bool isSck2Enabled; /*!< FLEXSPI use SCK2. */ + uint32_t flashSize; /*!< Flash size in KByte. */ + flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */ + uint16_t CSInterval; /*!< CS line assert interval, mutiply CS interval unit to + get the CS line assert interval cycles. */ + uint8_t CSHoldTime; /*!< CS line hold time. */ + uint8_t CSSetupTime; /*!< CS line setup time. */ + uint8_t dataValidTime; /*!< Data valid time for external device. */ + uint8_t columnspace; /*!< Column space size. */ + bool enableWordAddress; /*!< If enable word address.*/ + uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */ + uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */ + uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */ + uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */ + flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */ + uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, mutiply AHB write interval + unit to get the AHB write wait cycles. */ + bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask + when writing to external device. */ +} flexspi_device_config_t; + +/*! @brief Transfer structure for FLEXSPI. */ +typedef struct _flexspi_transfer +{ + uint32_t deviceAddress; /*!< Operation device address. */ + flexspi_port_t port; /*!< Operation port. */ + flexspi_command_type_t cmdType; /*!< Execution command type. */ + uint8_t seqIndex; /*!< Sequence ID for command. */ + uint8_t SeqNumber; /*!< Sequence number for command. */ + uint32_t *data; /*!< Data buffer. */ + size_t dataSize; /*!< Data size in bytes. */ +} flexspi_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexspi_handle flexspi_handle_t; + +/*! @brief FLEXSPI transfer callback function. */ +typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, + flexspi_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Transfer handle structure for FLEXSPI. */ +struct _flexspi_handle +{ + uint32_t state; /*!< Internal state for FLEXSPI transfer */ + uint32_t *data; /*!< Data buffer. */ + size_t dataSize; /*!< Remaining Data size in bytes. */ + size_t transferTotalSize; /*!< Total Data size in bytes. */ + flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */ + void *userData; /*!< FLEXSPI callback function parameter.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ +/*! + * @brief Initializes the FLEXSPI module and internal state. + * + * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the + * input configure parameters. Users should call this function before any FLEXSPI operations. + * + * @param base FLEXSPI peripheral base address. + * @param config FLEXSPI configure structure. + */ +void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); + +/*! + * @brief Gets default settings for FLEXSPI. + * + * @param config FLEXSPI configuration structure. + */ +void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); + +/*! + * @brief Deinitializes the FLEXSPI module. + * + * Clears the FLEXSPI state and FLEXSPI module registers. + * @param base FLEXSPI peripheral base address. + */ +void FLEXSPI_Deinit(FLEXSPI_Type *base); + +/*! + * @brief Configures the connected device parameter. + * + * This function configures the connected device relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * connected device. + * + * @param base FLEXSPI peripheral base address. + * @param config Flash configuration parameters. + * @param port FLEXSPI Operation port. + */ +void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); + +/*! + * @brief Software reset for the FLEXSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * @param base FLEXSPI peripheral base address. + */ +static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) +{ + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } +} + +/*! + * @brief Enables or disables the FLEXSPI module. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable FLEXSPI, false means disable. + */ +static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + } + else + { + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ +/*! + * @brief Enables the FLEXSPI interrupts. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disable the FLEXSPI interrupts. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/* @} */ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. + * + * @param base FLEXSPI peripheral base address. + * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. + */ +static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; + } + else + { + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; + } +} + +/*! + * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests. + * + * @param base FLEXSPI peripheral base address. + * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; + } + else + { + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; + } +} + +/*! + * @brief Gets FLEXSPI IP tx fifo address for DMA transfer. + * + * @param base FLEXSPI peripheral base address. + * @retval The tx fifo address. + */ +static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) +{ + return (uint32_t)&base->TFDR[0]; +} + +/*! + * @brief Gets FLEXSPI IP rx fifo address for DMA transfer. + * + * @param base FLEXSPI peripheral base address. + * @retval The rx fifo address. + */ +static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) +{ + return (uint32_t)&base->RFDR[0]; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! @brief Clears the FLEXSPI IP FIFO logic. + * + * @param base FLEXSPI peripheral base address. + * @param txFifo Pass true to reset TX FIFO. + * @param rxFifo Pass true to reset RX FIFO. + */ +static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) +{ + if (txFifo) + { + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + } + if (rxFifo) + { + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + } +} + +/*! + * @brief Gets the valid data entries in the FLEXSPI FIFOs. + * + * @param base FLEXSPI peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) +{ + if (txCount) + { + *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U; + } + if (rxCount) + { + *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; + } +} + +/*@}*/ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the FLEXSPI interrupt status flags. + * + * @param base FLEXSPI peripheral base address. + * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. + */ +static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Get the FLEXSPI interrupt status flags. + * + * @param base FLEXSPI peripheral base address. + * @param interrupt status flag. + */ +static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) +/*! @brief Gets the sampling clock phase selection after Data Learning. + * + * @param base FLEXSPI peripheral base address. + * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA. + * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB. + */ +static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase) +{ + if (portAPhase) + { + *portAPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT; + } + + if (portBPhase) + { + *portBPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT; + } +} +#endif + +/*! @brief Gets the trigger source of current command sequence granted by arbitrator. + * + * @param base FLEXSPI peripheral base address. + * @retval trigger source of current command sequence. + */ +static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) +{ + return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT); +} + +/*! @brief Gets the error code when IP command error detected. + * + * @param base FLEXSPI peripheral base address. + * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. + * @retval error code when IP command error detected. + */ +static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +{ + *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT; + return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT); +} + +/*! @brief Gets the error code when AHB command error detected. + * + * @param base FLEXSPI peripheral base address. + * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. + * @retval error code when AHB command error detected. + */ +static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +{ + *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; + return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> + FLEXSPI_STS1_AHBCMDERRCODE_SHIFT); +} + +/*! @brief Returns whether the bus is idle. + * + * @param base FLEXSPI peripheral base address. + * @retval true Bus is idle. + * @retval false Bus is busy. + */ +static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) +{ + return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK); +} +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! @brief Enables/disables the FLEXSPI IP command parallel mode. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; + } + else + { + base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; + } +} + +/*! @brief Enables/disables the FLEXSPI AHB command parallel mode. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK; + } + else + { + base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; + } +} + +/*! @brief Updates the LUT table. +* +* @param base FLEXSPI peripheral base address. +* @param index From which index start to update. It could be any index of the LUT table, which +* also allows user to update command content inside a command. Each command consists of up to +* 8 instructions and occupy 4*32-bit memory. +* @param cmd Command sequence array. +* @param count Number of sequences. +*/ +void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); + +/*! + * @brief Writes data into FIFO. + * + * @param base FLEXSPI peripheral base address + * @param data The data bytes to send + * @param fifoIndex Destination fifo index. + */ +static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) +{ + base->TFDR[fifoIndex] = data; +} + +/*! + * @brief Receives data from data FIFO. + * + * @param base FLEXSPI peripheral base address + * @param fifoIndex Source fifo index. + * @return The data in the FIFO. + */ +static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) +{ + return base->RFDR[fifoIndex]; +} + +/*! + * @brief Sends a buffer of data bytes using blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base FLEXSPI peripheral base address + * @param buffer The data bytes to send + * @param size The number of data bytes to send + * @retval kStatus_Success write success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receives a buffer of data bytes using a blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base FLEXSPI peripheral base address + * @param buffer The data bytes to send + * @param size The number of data bytes to receive + * @retval kStatus_Success read success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Execute command to transfer a buffer data bytes using a blocking method. + * @param base FLEXSPI peripheral base address + * @param xfer pointer to the transfer structure. + * @retval kStatus_Success command transfer success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected +*/ +status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXSPI handle which is used in transactional functions. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, + flexspi_handle_t *handle, + flexspi_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer + * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or + * FLEXSPI could not read data properly. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state. + * @param xfer pointer to flexspi_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished. + */ +status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state + */ +void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure. + */ +void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* __FSL_FLEXSPI_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpc.c new file mode 100644 index 0000000000..90b7eb1542 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpc.c @@ -0,0 +1,111 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpc_1" +#endif + + +void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + + assert(irqRegNum > 0U); + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + base->IMR5 &= ~(1U << irqRegShiftNum); + } + else + { + base->IMR[irqRegNum] &= ~(1U << irqRegShiftNum); + } +#else + base->IMR[irqRegNum - 1U] &= ~(1U << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ +} + +void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + + assert(irqRegNum > 0U); + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + base->IMR5 |= (1U << irqRegShiftNum); + } + else + { + base->IMR[irqRegNum] |= (1U << irqRegShiftNum); + } +#else + base->IMR[irqRegNum - 1U] |= (1U << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ +} + +bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + uint32_t ret; + + assert(irqRegNum > 0U); + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + ret = base->ISR5 & (1U << irqRegShiftNum); + } + else + { + ret = base->ISR[irqRegNum] & (1U << irqRegShiftNum); + } +#else + ret = base->ISR[irqRegNum - 1U] & (1U << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ + + return (1U << irqRegShiftNum) == ret; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpc.h new file mode 100644 index 0000000000..5ba31ecf65 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpc.h @@ -0,0 +1,257 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPC_H_ +#define _FSL_GPC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPC driver version 2.1.0. */ +#define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) +/*! + * @brief Allow all the IRQ/Events within the charge of GPC. + * + * @param base GPC peripheral base address. + */ +static inline void GPC_AllowIRQs(GPC_Type *base) +{ + base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */ +} + +/*! + * @brief Disallow all the IRQ/Events within the charge of GPC. + * + * @param base GPC peripheral base address. + */ +static inline void GPC_DisallowIRQs(GPC_Type *base) +{ + base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */ +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */ + +/*! + * @brief Enable the IRQ. + * + * @param base GPC peripheral base address. + * @param irqId ID number of IRQ to be enabled, available range is 32-159. + */ +void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId); + +/*! + * @brief Disable the IRQ. + * + * @param base GPC peripheral base address. + * @param irqId ID number of IRQ to be disabled, available range is 32-159. + */ +void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId); + +/*! + * @brief Get the IRQ/Event flag. + * + * @param base GPC peripheral base address. + * @param irqId ID number of IRQ to be enabled, available range is 32-159. + * @return Indicated IRQ/Event is asserted or not. + */ +bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId); + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE) +/*! + * @brief L2 Cache Power Gate Enable + * + * This function configures the L2 cache if it will keep power when in low power mode. + * When the L2 cache power is OFF, L2 cache will be power down once when CPU core is power down + * and will be hardware invalidated automatically when CPU core is re-power up. + * When the L2 cache power is ON, L2 cache will keep power on even if CPU core is power down and + * will not be hardware invalidated. + * When CPU core is re-power up, the default setting is OFF. + * + * @param base GPC peripheral base address. + * @param enable Enable the request or not. + */ +static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */ + } + else + { + base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */ + } +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) +/*! + * @brief FLEXRAM PDRAM0 Power Gate Enable + * + * This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down. + * When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down. + * When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down. + * When CPU core is re-power up, the default setting is 1. + * + * @param base GPC peripheral base address. + * @param enable Enable the request or not. + */ +static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */ + } + else + { + base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */ + } +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC) +/*! + * @brief VADC power down. + * + * This function requests the VADC power down. + * + * @param base GPC peripheral base address. + * @param enable Enable the request or not. + */ +static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */ + } + else + { + base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */ + } +} + +/*! + * @brief Checks if the VADC is power off. + * + * @param base GPC peripheral base address. + * @return Whether the VADC is power off or not. + */ +static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base) +{ + return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR)); +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) +/*! + * @brief Checks if the DVFS0 is requesting for frequency/voltage update. + * + * @param base GPC peripheral base address. + * @return Whether the DVFS0 is requesting for frequency/voltage update. + */ +static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base) +{ + return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR)); +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) +/*! + * @brief Requests the display power switch sequence. + * + * @param base GPC peripheral base address. + * @param enable Enable the power on sequence, or the power down sequence. + */ +static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */ + } + else + { + base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */ + } +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */ + +/*! + * @brief Requests the MEGA power switch sequence. + * + * @param base GPC peripheral base address. + * @param enable Enable the power on sequence, or the power down sequence. + */ +static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */ + } + else + { + base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */ + } +} + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_GPC_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpio.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpio.c new file mode 100644 index 0000000000..f4714aa53e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpio.c @@ -0,0 +1,166 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.igpio" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of GPIO clock name. */ +static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable GPIO clock. */ + CLOCK_EnableClock(s_gpioClock[GPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Register reset to default value */ + base->IMR &= ~(1U << pin); + + /* Configure GPIO pin direction */ + if (Config->direction == kGPIO_DigitalInput) + { + base->GDIR &= ~(1U << pin); + } + else + { + GPIO_PinWrite(base, pin, Config->outputLogic); + base->GDIR |= (1U << pin); + } + + /* Configure GPIO pin interrupt mode */ + GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); +} + +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + assert(pin < 32); + if (output == 0U) + { + base->DR &= ~(1U << pin); /* Set pin output to low level.*/ + } + else + { + base->DR |= (1U << pin); /* Set pin output to high level.*/ + } +} + +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + /* Register reset to default value */ + base->EDGE_SEL &= ~(1U << pin); + + if (pin < 16) + { + icr = &(base->ICR1); + } + else + { + icr = &(base->ICR2); + icrShift -= 16; + } + switch (pinInterruptMode) + { + case (kGPIO_IntLowLevel): + *icr &= ~(3U << (2 * icrShift)); + break; + case (kGPIO_IntHighLevel): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); + break; + case (kGPIO_IntRisingEdge): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); + break; + case (kGPIO_IntFallingEdge): + *icr |= (3U << (2 * icrShift)); + break; + case (kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1U << pin); + break; + default: + break; + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpio.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpio.h new file mode 100644 index 0000000000..834a9c981a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpio.h @@ -0,0 +1,368 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.0.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param initConfig pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + GPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else + base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else + base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32); + + return (((base->DR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current input value of the GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinRead(base, pin); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + +/*! +* @brief Reads the current GPIO pin pad status. +* +* @param base GPIO base pointer. +* @param pin GPIO port pin number. +* @retval GPIO pin pad status value. +*/ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} + +/*! +* @brief Reads the current GPIO pin pad status. +* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. +*/ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinReadPadStatus(base, pin); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Sets the current pin interrupt mode. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortEnableInterrupts(base, mask); +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortDisableInterrupts(base, mask); +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + return base->ISR; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + return GPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISR = mask; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClearInterruptFlags(base, mask); +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpt.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpt.c new file mode 100644 index 0000000000..39b0e89fb5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpt.c @@ -0,0 +1,124 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpt" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GPT bases for each instance. */ +static GPT_Type *const s_gptBases[] = GPT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to GPT clocks for each instance. */ +static const clock_ip_name_t s_gptClocks[] = GPT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t GPT_GetInstance(GPT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_gptBases); instance++) + { + if (s_gptBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gptBases)); + + return instance; +} + +void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig) +{ + assert(initConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the GPT clock*/ + CLOCK_EnableClock(s_gptClocks[GPT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + base->CR = 0U; + + GPT_SoftwareReset(base); + + base->CR = + (initConfig->enableFreeRun ? GPT_CR_FRR_MASK : 0U) | (initConfig->enableRunInWait ? GPT_CR_WAITEN_MASK : 0U) | + (initConfig->enableRunInStop ? GPT_CR_STOPEN_MASK : 0U) | + (initConfig->enableRunInDoze ? GPT_CR_DOZEEN_MASK : 0U) | + (initConfig->enableRunInDbg ? GPT_CR_DBGEN_MASK : 0U) | (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0U); + + GPT_SetClockSource(base, initConfig->clockSource); + GPT_SetClockDivider(base, initConfig->divider); +} + +void GPT_Deinit(GPT_Type *base) +{ + /* Disable GPT timers */ + base->CR = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the GPT clock*/ + CLOCK_DisableClock(s_gptClocks[GPT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void GPT_GetDefaultConfig(gpt_config_t *config) +{ + assert(config); + + config->clockSource = kGPT_ClockSource_Periph; + config->divider = 1U; + config->enableRunInStop = true; + config->enableRunInWait = true; + config->enableRunInDoze = false; + config->enableRunInDbg = false; + config->enableFreeRun = false; + config->enableMode = true; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpt.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpt.h new file mode 100644 index 0000000000..1cea054557 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_gpt.h @@ -0,0 +1,533 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPT_H_ +#define _FSL_GPT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpt + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ + /*@}*/ + +/*! + * @brief List of clock sources + * @note Actual number of clock sources is SoC dependent + */ +typedef enum _gpt_clock_source +{ + kGPT_ClockSource_Off = 0U, /*!< GPT Clock Source Off.*/ + kGPT_ClockSource_Periph = 1U, /*!< GPT Clock Source from Peripheral Clock.*/ + kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/ + kGPT_ClockSource_Ext = 3U, /*!< GPT Clock Source from external pin.*/ + kGPT_ClockSource_LowFreq = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/ + kGPT_ClockSource_Osc = 5U, /*!< GPT Clock Source from Crystal oscillator.*/ +} gpt_clock_source_t; + +/*! @brief List of input capture channel number. */ +typedef enum _gpt_input_capture_channel +{ + kGPT_InputCapture_Channel1 = 0U, /*!< GPT Input Capture Channel1.*/ + kGPT_InputCapture_Channel2 = 1U, /*!< GPT Input Capture Channel2.*/ +} gpt_input_capture_channel_t; + +/*! @brief List of input capture operation mode. */ +typedef enum _gpt_input_operation_mode +{ + kGPT_InputOperation_Disabled = 0U, /*!< Don't capture.*/ + kGPT_InputOperation_RiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ + kGPT_InputOperation_FallEdge = 2U, /*!< Capture on falling edge of input pin.*/ + kGPT_InputOperation_BothEdge = 3U, /*!< Capture on both edges of input pin.*/ +} gpt_input_operation_mode_t; + +/*! @brief List of output compare channel number. */ +typedef enum _gpt_output_compare_channel +{ + kGPT_OutputCompare_Channel1 = 0U, /*!< Output Compare Channel1.*/ + kGPT_OutputCompare_Channel2 = 1U, /*!< Output Compare Channel2.*/ + kGPT_OutputCompare_Channel3 = 2U, /*!< Output Compare Channel3.*/ +} gpt_output_compare_channel_t; + +/*! @brief List of output compare operation mode. */ +typedef enum _gpt_output_operation_mode +{ + kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/ + kGPT_OutputOperation_Toggle = 1U, /*!< Toggle output pin.*/ + kGPT_OutputOperation_Clear = 2U, /*!< Set output pin low.*/ + kGPT_OutputOperation_Set = 3U, /*!< Set output pin high.*/ + kGPT_OutputOperation_Activelow = 4U, /*!< Generate a active low pulse on output pin.*/ +} gpt_output_operation_mode_t; + +/*! @brief List of GPT interrupts */ +typedef enum _gpt_interrupt_enable +{ + kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/ + kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/ + kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/ + kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/ +} gpt_interrupt_enable_t; + +/*! @brief Status flag. */ +typedef enum _gpt_status_flag +{ + kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/ + kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/ + kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/ + kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/ + kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/ + kGPT_RollOverFlag = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/ +} gpt_status_flag_t; + +/*! @brief Structure to configure the running mode. */ +typedef struct _gpt_init_config +{ + gpt_clock_source_t clockSource; /*!< clock source for GPT module. */ + uint32_t divider; /*!< clock divider (prescaler+1) from clock source to counter. */ + bool enableFreeRun; /*!< true: FreeRun mode, false: Restart mode. */ + bool enableRunInWait; /*!< GPT enabled in wait mode. */ + bool enableRunInStop; /*!< GPT enabled in stop mode. */ + bool enableRunInDoze; /*!< GPT enabled in doze mode. */ + bool enableRunInDbg; /*!< GPT enabled in debug mode. */ + bool enableMode; /*!< true: counter reset to 0 when enabled; + false: counter retain its value when enabled. */ +} gpt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize GPT to reset state and initialize running mode. + * + * @param base GPT peripheral base address. + * @param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig); + +/*! + * @brief Disables the module and gates the GPT clock. + * + * @param base GPT peripheral base address. + */ +void GPT_Deinit(GPT_Type *base); + +/*! + * @brief Fills in the GPT configuration structure with default settings. + * + * The default values are: + * @code + * config->clockSource = kGPT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDoze = false; + * config->enableRunInDbg = false; + * config->enableFreeRun = true; + * config->enableMode = true; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void GPT_GetDefaultConfig(gpt_config_t *config); + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset of GPT module. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_SoftwareReset(GPT_Type *base) +{ + base->CR |= GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while ((base->CR & GPT_CR_SWR_MASK) == GPT_CR_SWR_MASK) + { + } +} + +/*! + * @name Clock source and frequency control + * @{ + */ + +/*! + * @brief Set clock source of GPT. + * + * @param base GPT peripheral base address. + * @param source Clock source (see @ref gpt_clock_source_t typedef enumeration). + */ +static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t source) +{ + if (source == kGPT_ClockSource_Osc) + { + base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); + } + else + { + base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); + } +} + +/*! + * @brief Get clock source of GPT. + * + * @param base GPT peripheral base address. + * @return clock source (see @ref gpt_clock_source_t typedef enumeration). + */ +static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base) +{ + return (gpt_clock_source_t)((base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT); +} + +/*! + * @brief Set pre scaler of GPT. + * + * @param base GPT peripheral base address. + * @param divider Divider of GPT (1-4096). + */ +static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider) +{ + assert(divider - 1 <= GPT_PR_PRESCALER_MASK); + + base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(divider - 1); +} + +/*! + * @brief Get clock divider in GPT module. + * + * @param base GPT peripheral base address. + * @return clock divider in GPT module (1-4096). + */ +static inline uint32_t GPT_GetClockDivider(GPT_Type *base) +{ + return ((base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT) + 1; +} + +/*! + * @brief OSC 24M pre-scaler before selected by clock source. + * + * @param base GPT peripheral base address. + * @param divider OSC Divider(1-16). + */ +static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider) +{ + assert(divider - 1 <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); + + base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(divider - 1); +} + +/*! + * @brief Get OSC 24M clock divider in GPT module. + * + * @param base GPT peripheral base address. + * @return OSC clock divider in GPT module (1-16). + */ +static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base) +{ + return ((base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT) + 1; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ +/*! + * @brief Start GPT timer. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_StartTimer(GPT_Type *base) +{ + base->CR |= GPT_CR_EN_MASK; +} + +/*! + * @brief Stop GPT timer. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_StopTimer(GPT_Type *base) +{ + base->CR &= ~GPT_CR_EN_MASK; +} + +/*! + * @name Read the timer period + * @{ + */ + +/*! + * @brief Reads the current GPT counting value. + * + * @param base GPT peripheral base address. + * @return Current GPT counter value. + */ +static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base) +{ + return base->CNT; +} + +/*@}*/ + +/*! + * @name GPT Input/Output Signal Control + * @{ + */ + +/*! + * @brief Set GPT operation mode of input capture channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @param mode GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). + */ +static inline void GPT_SetInputOperationMode(GPT_Type *base, + gpt_input_capture_channel_t channel, + gpt_input_operation_mode_t mode) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + base->CR = (base->CR & ~(GPT_CR_IM1_MASK << (channel * 2))) | (GPT_CR_IM1(mode) << (channel * 2)); +} + +/*! + * @brief Get GPT operation mode of input capture channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @return GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). + */ +static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + return (gpt_input_operation_mode_t)((base->CR >> (GPT_CR_IM1_SHIFT + channel * 2)) & + (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT)); +} + +/*! + * @brief Get GPT input capture value of certain channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @return GPT input capture value. + */ +static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + return *(&base->ICR[0] + channel); +} + +/*! + * @brief Set GPT operation mode of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @param mode GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). + */ +static inline void GPT_SetOutputOperationMode(GPT_Type *base, + gpt_output_compare_channel_t channel, + gpt_output_operation_mode_t mode) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->CR = (base->CR & ~(GPT_CR_OM1_MASK << (channel * 3))) | (GPT_CR_OM1(mode) << (channel * 3)); +} + +/*! + * @brief Get GPT operation mode of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @return GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). + */ +static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, + gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + return (gpt_output_operation_mode_t)((base->CR >> (GPT_CR_OM1_SHIFT + channel * 3)) & + (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT)); +} + +/*! + * @brief Set GPT output compare value of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @param value GPT output compare value. + */ +static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + *(&base->OCR[0] + channel) = value; +} + +/*! + * @brief Get GPT output compare value of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @return GPT output compare value. + */ +static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + return *(&base->OCR[0] + channel); +} + +/*! + * @brief Force GPT output action on output compare channel, ignoring comparator. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + */ +static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->CR |= (GPT_CR_FO1_MASK << channel); +} + +/*@}*/ + +/*! + * @name GPT Interrupt and Status Interface + * @{ + */ + +/*! + * @brief Enables the selected GPT interrupts. + * + * @param base GPT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask) +{ + base->IR |= mask; +} + +/*! + * @brief Disables the selected GPT interrupts. + * + * @param base GPT peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask) +{ + base->IR &= ~mask; +} + +/*! + * @brief Gets the enabled GPT interrupts. + * + * @param base GPT peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base) +{ + return (base->IR & (GPT_IR_OF1IE_MASK | GPT_IR_OF2IE_MASK | GPT_IR_OF3IE_MASK | GPT_IR_IF1IE_MASK | + GPT_IR_IF2IE_MASK | GPT_IR_ROVIE_MASK)); +} + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get GPT status flags. + * + * @param base GPT peripheral base address. + * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). + * @return GPT status, each bit represents one status flag. + */ +static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags) +{ + return base->SR & flags; +} + +/*! + * @brief Clears the GPT status flags. + * + * @param base GPT peripheral base address. + * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). + */ +static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags) +{ + base->SR = flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_GPT_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_iomuxc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_iomuxc.h new file mode 100644 index 0000000000..2a7dabb802 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_iomuxc.h @@ -0,0 +1,1272 @@ +/* + * The Clear BSD License + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U + +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U +#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U + +#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U + +#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU + +#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U + +#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U + +#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U + +#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU + +#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U + +#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U + +#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU + +#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U + +#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U + +#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U + +#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U + +#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU + +#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U + +#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U + +#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U + +#define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU + +#define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U + +#define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U + +#define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U + +#define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU + +#define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U + +#define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U + +#define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U + +#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U + +#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U + +#define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU + +#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U + +#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U + +#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U + +#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU + +#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U + +#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U + +#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U + +#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U + +#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U + +#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU + +#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U + +#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U + +#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU + +#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U + +#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U + +#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U + +#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU + +#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U + +#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U + +#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U + +#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU + +#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U + +#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U + +#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U + +#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU +#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU + +#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U +#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U + +#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U + +#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U + +#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU + +#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U + +#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U + +#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U + +#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU + +#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U + +#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U + +#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U + +#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU +#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU + +#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U +#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U + +#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U +#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U + +#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U + +#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU + +#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U + +#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U + +#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U + +#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU + +#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U + +#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U + +#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U +#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U + +#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU + +#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U + +#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U + +#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U + +#define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU + +#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U + +#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U + +#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U + +#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU + +#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U + +#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U + +#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U + +#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU + +#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U + +#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U + +#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U + +#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU + +#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U + +#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U + +#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U + +#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU + +#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U + +#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U + +#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U + +#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU + +#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, + kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, + kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_kpp.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_kpp.c new file mode 100644 index 0000000000..f83fd25705 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_kpp.c @@ -0,0 +1,202 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_kpp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.kpp" +#endif + +#define KPP_KEYPAD_SCAN_TIMES (3U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SEMC clocks for each instance. */ +static const clock_ip_name_t s_kppClock[FSL_FEATURE_SOC_KPP_COUNT] = KPP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to SEMC bases for each instance. */ +static KPP_Type *const s_kppBases[] = KPP_BASE_PTRS; + +/*! @brief Pointers to KPP IRQ number for each instance. */ +static const IRQn_Type s_kppIrqs[] = KPP_IRQS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t KPP_GetInstance(KPP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_kppBases); instance++) + { + if (s_kppBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_kppBases)); + + return instance; +} +static void KPP_Mdelay(uint64_t tickets) +{ + while (tickets--) + { + __NOP(); + } +} + +void KPP_Init(KPP_Type *base, kpp_config_t *configure) +{ + assert(configure); + + uint32_t instance = KPP_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate sdram controller clock. */ + CLOCK_EnableClock(s_kppClock[KPP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Clear all. */ + base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); + + /* Enable the keypad row and set the column strobe output to open drain. */ + base->KPCR = KPP_KPCR_KRE(configure->activeRow); + base->KPDR = KPP_KPDR_KCD((uint8_t)~(configure->activeColumn)); + base->KPCR |= KPP_KPCR_KCO(configure->activeColumn); + + /* Set the input direction for row and output direction for column. */ + base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t)~(configure->activeRow)); + + /* Clear the status flag and enable the interrupt. */ + base->KPSR = + KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt; + + if (configure->interrupt) + { + /* Enable at the Interrupt */ + EnableIRQ(s_kppIrqs[instance]); + } +} + +void KPP_Deinit(KPP_Type *base) +{ + /* Disable interrupts and disable all rows. */ + base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); + base->KPCR = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable KPP clock. */ + CLOCK_DisableClock(s_kppClock[KPP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) +{ + assert(data); + + uint16_t kppKCO = base->KPCR & KPP_KPCR_KCO_MASK; + uint8_t columIndex = 0; + uint8_t activeColumn = (base->KPCR & KPP_KPCR_KCO_MASK) >> KPP_KPCR_KCO_SHIFT; + uint8_t times; + uint8_t rowData[KPP_KEYPAD_SCAN_TIMES][KPP_KEYPAD_COLUMNNUM_MAX]; + bool press = false; + uint8_t column; + + /* Initialize row data to zero. */ + memset(&rowData[0][0], 0, sizeof(rowData)); + + /* Scanning. */ + /* Configure the column data to 1 according to column numbers. */ + base->KPDR = KPP_KPDR_KCD_MASK; + /* Configure column to totem pole for quick discharge of keypad capacitance. */ + base->KPCR &= (uint16_t)(((uint16_t)~kppKCO) | KPP_KPCR_KRE_MASK); + /* Recover. */ + base->KPCR |= kppKCO; + /* Three times scanning. */ + for (times = 0; times < KPP_KEYPAD_SCAN_TIMES; times++) + { + for (columIndex = 0; columIndex < KPP_KEYPAD_COLUMNNUM_MAX; columIndex++) + { + column = activeColumn & (1U << columIndex); + if (column) + { + /* Set the single column line to 0. */ + base->KPDR = KPP_KPDR_KCD(~(uint16_t)column); + /* Take 100us delays. */ + KPP_Mdelay(clockSrc_Hz / 10000000); + /* Read row data. */ + rowData[times][columIndex] = ~(base->KPDR & KPP_KPDR_KRD_MASK); + } + else + { + /* Read row data. */ + rowData[times][columIndex] = 0; + } + } + } + + /* Return all columns to 0 in preparation for standby mode. */ + base->KPDR &= ~KPP_KPDR_KCD_MASK; + + /* Check if three time scan data is the same. */ + for (columIndex = 0; columIndex < KPP_KEYPAD_COLUMNNUM_MAX; columIndex++) + { + if ((uint8_t)(rowData[0][columIndex] & rowData[1][columIndex]) & rowData[2][columIndex]) + { + press = true; + } + } + + if (press) + { + memcpy((void *)data, &rowData[0][0], sizeof(rowData[0])); + } + else + { + memset((void *)data, 0, sizeof(rowData[0])); + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_kpp.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_kpp.h new file mode 100644 index 0000000000..46eb3aab57 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_kpp.h @@ -0,0 +1,203 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_KPP_H_ +#define _FSL_KPP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kpp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief KPP driver version 2.0.0. */ +#define FSL_KPP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define KPP_KEYPAD_COLUMNNUM_MAX (8U) +#define KPP_KEYPAD_ROWNUM_MAX (8U) + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _kpp_interrupt_enable { + kKPP_keyDepressInterrupt = KPP_KPSR_KDIE_MASK, /*!< Keypad depress interrupt source */ + kKPP_keyReleaseInterrupt = KPP_KPSR_KRIE_MASK /*!< Keypad release interrupt source */ +} kpp_interrupt_enable_t; + +/*! @brief Lists of KPP synchronize chain operation. */ +typedef enum _kpp_sync_operation { + kKPP_ClearKeyDepressSyncChain = KPP_KPSR_KDSC_MASK, /*!< Keypad depress interrupt status. */ + kKPP_SetKeyReleasesSyncChain = KPP_KPSR_KRSS_MASK, /*!< Keypad release interrupt status. */ +} kpp_sync_operation_t; + +/*! @brief Lists of KPP status. */ +typedef struct _kpp_config +{ + uint8_t activeRow; /*!< The row number: bit 7 ~ 0 represents the row 7 ~ 0. */ + uint8_t activeColumn; /*!< The column number: bit 7 ~ 0 represents the column 7 ~ 0. */ + uint16_t interrupt; /*!< KPP interrupt source. A logical OR of "kpp_interrupt_enable_t". */ +} kpp_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief KPP initialize. + * This function ungates the KPP clock and initializes KPP. + * This function must be called before calling any other KPP driver functions. + * + * @param base KPP peripheral base address. + * @param configure The KPP configuration structure pointer. + */ +void KPP_Init(KPP_Type *base, kpp_config_t *configure); + +/*! + * @brief Deinitializes the KPP module and gates the clock. + * This function gates the KPP clock. As a result, the KPP + * module doesn't work after calling this function. + * + * @param base KPP peripheral base address. + */ +void KPP_Deinit(KPP_Type *base); + +/* @} */ + +/*! + * @name KPP Basic Operation + * @{ + */ + +/*! + * @brief Enable the interrupt. + * + * @param base KPP peripheral base address. + * @param mask KPP interrupts to enable. This is a logical OR of the + * enumeration :: kpp_interrupt_enable_t. + */ +static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask) +{ + uint16_t data = base->KPSR & ~(KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); + base->KPSR = data | mask; +} + +/*! + * @brief Disable the interrupt. + * + * @param base KPP peripheral base address. + * @param mask KPP interrupts to disable. This is a logical OR of the + * enumeration :: kpp_interrupt_enable_t. + */ +static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask) +{ + base->KPSR &= ~(mask | KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); +} + +/*! + * @brief Gets the KPP interrupt event status. + * + * @param base KPP peripheral base address. + * @return The status of the KPP. Application can use the enum type in the "kpp_interrupt_enable_t" + * to get the right status of the related event. + */ +static inline uint16_t KPP_GetStatusFlag(KPP_Type *base) +{ + return (base->KPSR & (KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK)) << KPP_KPSR_KDIE_SHIFT; +} + +/*! + * @brief Clears KPP status flag. + * + * @param base KPP peripheral base address. + * @param mask KPP mask to be cleared. This is a logical OR of the + * enumeration :: kpp_interrupt_enable_t. + */ +static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask) +{ + base->KPSR |= (uint16_t)((mask) >> KPP_KPSR_KDIE_SHIFT); +} + +/*! + * @brief Set KPP synchronization chain. + * + * @param base KPP peripheral base address. + * @param mask KPP mask to be cleared. This is a logical OR of the + * enumeration :: kpp_sync_operation_t. + */ +static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask) +{ + uint16_t data = base->KPSR & (KPP_KPSR_KRSS_MASK | KPP_KPSR_KDSC_MASK | KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); + base->KPSR = data | mask; +} + +/*! + * @brief Keypad press scanning. + * + * This function will scanning all columns and rows. so + * all scanning data will be stored in the data pointer. + * + * @param base KPP peripheral base address. + * @param data KPP key press scanning data. The data buffer should be prepared with + * length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. + * the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. + * for example the data[2] = 4, that means in column 1 row 2 has a key press event. + */ +void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_KPP_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c.c new file mode 100644 index 0000000000..7ce2c37213 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c.c @@ -0,0 +1,1927 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpi2c.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c" +#endif + +/*! @brief Common sets of flags used by the driver. */ +enum _lpi2c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterDataMatchFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag, + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, +}; + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpi2c_default_watermarks +{ + kDefaultTxWatermark = 0, + kDefaultRxWatermark = 0, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpi2c_slave_isr_t)(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base); + +static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, + uint32_t width_ns, + uint32_t maxCycles, + uint32_t prescaler); + +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); + +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); + +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); + +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); + +static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/*! @brief Array to map LPI2C instance number to IRQ number. */ +static IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map LPI2C instance number to clock gate enum. */ +static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; + +#if defined(LPI2C_PERIPH_CLOCKS) +/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ +static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointers to master handles for each instance. */ +static lpi2c_master_handle_t *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The LPI2C peripheral base address. + * @return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base) +{ + uint32_t instance; + for (instance = 0; instance < ARRAY_SIZE(kLpi2cBases); ++instance) + { + if (kLpi2cBases[instance] == base) + { + return instance; + } + } + + assert(false); + return 0; +} + +/*! + * @brief Computes a cycle count for a given time in nanoseconds. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param width_ns Desired with in nanoseconds. + * @param maxCycles Maximum cycle count, determined by the number of bits wide the cycle count field is. + * @param prescaler LPI2C prescaler setting. Pass 1 if the prescaler should not be used, as for slave glitch widths. + */ +static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, + uint32_t width_ns, + uint32_t maxCycles, + uint32_t prescaler) +{ + assert(sourceClock_Hz > 0); + assert(prescaler > 0); + + uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000); + uint32_t cycles = 0; + + /* Search for the cycle count just below the desired glitch width. */ + while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles)) + { + ++cycles; + } + + /* If we end up with zero cycles, then set the filter to a single cycle unless the */ + /* bus clock is greater than 10x the desired glitch width. */ + if ((cycles == 0) && (busCycle_ns <= (width_ns * 10))) + { + cycles = 1; + } + + return cycles; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= kMasterErrorFlags; + if (status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (status & kLPI2C_MasterPinLowTimeoutFlag) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (status & kLPI2C_MasterArbitrationLostFlag) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (status & kLPI2C_MasterNackDetectFlag) + { + result = kStatus_LPI2C_Nak; + } + else if (status & kLPI2C_MasterFifoErrFlag) + { + result = kStatus_LPI2C_FifoError; + } + else + { + assert(false); + } + + /* Clear the flags. */ + LPI2C_MasterClearStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } + + return result; +} + +/*! + * @brief Wait until there is room in the tx fifo. + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) +{ + uint32_t status; + size_t txCount; + size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + do + { + status_t result; + + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (result) + { + return result; + } +#if LPI2C_WAIT_TIMEOUT + } while ((!txCount) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while (!txCount); +#endif + + return kStatus_Success; +} + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Busy + */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) +{ + uint32_t status = LPI2C_MasterGetStatusFlags(base); + if ((status & kLPI2C_MasterBusBusyFlag) && (!(status & kLPI2C_MasterBusyFlag))) + { + return kStatus_LPI2C_Busy; + } + + return kStatus_Success; +} + +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) +{ + masterConfig->enableMaster = true; + masterConfig->debugEnable = false; + masterConfig->enableDoze = true; + masterConfig->ignoreAck = false; + masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + masterConfig->baudRate_Hz = 100000U; + masterConfig->busIdleTimeout_ns = 0; + masterConfig->pinLowTimeout_ns = 0; + masterConfig->sdaGlitchFilterWidth_ns = 0; + masterConfig->sclGlitchFilterWidth_ns = 0; + masterConfig->hostRequest.enable = false; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; +} + +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t prescaler; + uint32_t cycles; + uint32_t cfgr2; + uint32_t value; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Ungate the clock. */ + CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset peripheral before configuring it. */ + LPI2C_MasterReset(base); + + /* Doze bit: 0 is enable, 1 is disable */ + base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); + + /* host request */ + value = base->MCFGR0; + value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); + value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | + LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | + LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); + base->MCFGR0 = value; + + /* pin config and ignore ack */ + value = base->MCFGR1; + value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); + value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); + base->MCFGR1 = value; + + LPI2C_MasterSetWatermarks(base, kDefaultTxWatermark, kDefaultRxWatermark); + + LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); + + /* Configure glitch filters and bus idle and pin low timeouts. */ + prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; + cfgr2 = base->MCFGR2; + if (masterConfig->busIdleTimeout_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK; + cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles); + } + if (masterConfig->sdaGlitchFilterWidth_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, + (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 1); + cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); + } + if (masterConfig->sclGlitchFilterWidth_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, + (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 1); + cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); + } + base->MCFGR2 = cfgr2; + if (masterConfig->pinLowTimeout_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); + } + + LPI2C_MasterEnable(base, masterConfig->enableMaster); +} + +void LPI2C_MasterDeinit(LPI2C_Type *base) +{ + /* Restore to reset state. */ + LPI2C_MasterReset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Gate clock. */ + CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config) +{ + /* Disable master mode. */ + bool wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; + LPI2C_MasterEnable(base, false); + + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); + base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly); + base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) +{ + uint32_t prescale = 0; + uint32_t bestPre = 0; + uint32_t bestClkHi = 0; + uint32_t absError = 0; + uint32_t bestError = 0xffffffffu; + uint32_t value; + uint32_t clkHiCycle; + uint32_t computedRate; + int i; + bool wasEnabled; + + /* Disable master mode. */ + wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; + LPI2C_MasterEnable(base, false); + + /* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */ + /* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */ + for (prescale = 1; (prescale <= 128) && (bestError != 0); prescale = 2 * prescale) + { + for (clkHiCycle = 1; clkHiCycle < 32; clkHiCycle++) + { + if (clkHiCycle == 1) + { + computedRate = (sourceClock_Hz / prescale) / (1 + 3 + 2 + 2 / prescale); + } + else + { + computedRate = (sourceClock_Hz / prescale) / (3 * clkHiCycle + 2 + 2 / prescale); + } + + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + + if (absError < bestError) + { + bestPre = prescale; + bestClkHi = clkHiCycle; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Standard, fast, fast mode plus and ultra-fast transfers. */ + value = LPI2C_MCCR0_CLKHI(bestClkHi); + + if (bestClkHi < 2) + { + value |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1); + } + else + { + value |= LPI2C_MCCR0_CLKLO(2 * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2); + } + + base->MCCR0 = value; + + for (i = 0; i < 8; i++) + { + if (bestPre == (1U << i)) + { + bestPre = i; + break; + } + } + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + /* Return an error if the bus is already in use not by us. */ + status_t result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Wait until there is room in the fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Issue start command. */ + base->MTDR = kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); + + return kStatus_Success; +} + +status_t LPI2C_MasterStop(LPI2C_Type *base) +{ + /* Wait until there is room in the fifo. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Send the STOP signal */ + base->MTDR = kStopCmd; + +/* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ +/* Also check for errors while waiting. */ +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + +#if LPI2C_WAIT_TIMEOUT + while ((result == kStatus_Success) && (--waitTimes)) +#else + while (result == kStatus_Success) +#endif + { + uint32_t status = LPI2C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + result = LPI2C_MasterCheckAndClearError(base, status); + + /* Check if the stop was sent successfully. */ + if (status & kLPI2C_MasterStopDetectFlag) + { + LPI2C_MasterClearStatusFlags(base, kLPI2C_MasterStopDetectFlag); + break; + } + } + +#if LPI2C_WAIT_TIMEOUT + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#endif + + return result; +} + +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) +{ + status_t result; + uint8_t *buf; + + assert(rxBuff); + + /* Handle empty read. */ + if (!rxSize) + { + return kStatus_Success; + } + + /* Wait until there is room in the command fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Issue command to receive data. */ + base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(rxSize - 1); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (rxSize--) + { + /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ + /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ + /* using a single register read. */ + uint32_t value; + do + { + /* Check for errors. */ + result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); + if (result) + { + return result; + } + + value = base->MRDR; +#if LPI2C_WAIT_TIMEOUT + } while ((value & LPI2C_MRDR_RXEMPTY_MASK) && (--waitTimes)); + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while (value & LPI2C_MRDR_RXEMPTY_MASK); +#endif + + *buf++ = value & LPI2C_MRDR_DATA_MASK; + } + + return kStatus_Success; +} + +status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize) +{ + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + + assert(txBuff); + + /* Send data buffer */ + while (txSize--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = *buf++; + } + + return kStatus_Success; +} + +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) +{ + status_t result = kStatus_Success; + uint16_t commandBuffer[7]; + uint32_t cmdCount = 0; + + assert(transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + lpi2c_direction_t direction = transfer->subaddressSize ? kLPI2C_Write : transfer->direction; + if (!(transfer->flags & kLPI2C_TransferNoStartFlag)) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); + } + + /* Subaddress, MSB first. */ + if (transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (subaddressRemaining--) + { + uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + commandBuffer[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((transfer->dataSize) && (transfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Send command buffer */ + uint32_t index = 0; + while (cmdCount--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = commandBuffer[index]; + index++; + } + + /* Transmit data. */ + if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0)) + { + /* Send Data. */ + result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize); + } + + /* Receive Data. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0)) + { + result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize); + } + + if (result) + { + return result; + } + + if ((transfer->flags & kLPI2C_TransferNoStopFlag) == 0) + { + result = LPI2C_MasterStop(base); + } + + return result; +} + +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + EnableIRQ(kLpi2cIrqs[instance]); +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + status_t result = kStatus_Success; + lpi2c_master_transfer_t *xfer; + size_t txCount; + size_t rxCount; + size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + bool state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (result) + { + return result; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + /* Get fifo counts and compute room in tx fifo. */ + LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount); + txCount = txFifoSize - txCount; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case kSendCommandState: + { + /* Make sure there is room in the tx fifo for the next command. */ + if (!txCount--) + { + state_complete = true; + break; + } + + /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ + base->MTDR = *(uint16_t *)handle->buf; + handle->buf += sizeof(uint16_t); + + /* Count down until all commands are sent. */ + if (--handle->remainingBytes == 0) + { + /* Choose next state and set up buffer pointer and count. */ + if (xfer->dataSize) + { + /* Either a send or receive transfer is next. */ + handle->state = kTransferDataState; + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = xfer->dataSize; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); + } + } + else + { + /* No transfer, so move to stop state. */ + handle->state = kStopState; + } + } + break; + } + + case kIssueReadCommandState: + /* Make sure there is room in the tx fifo for the read command. */ + if (!txCount--) + { + state_complete = true; + break; + } + + base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + + /* Move to transfer state. */ + handle->state = kTransferDataState; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); + } + break; + + case kTransferDataState: + if (xfer->direction == kLPI2C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (!txCount--) + { + state_complete = true; + break; + } + + /* Put byte to send in fifo. */ + base->MTDR = *(handle->buf)++; + } + else + { + /* XXX handle receive sizes > 256, use kIssueReadCommandState */ + /* Make sure there is data in the rx fifo. */ + if (!rxCount--) + { + state_complete = true; + break; + } + + /* Read byte from fifo. */ + *(handle->buf)++ = base->MRDR & LPI2C_MRDR_DATA_MASK; + } + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0) + { + handle->state = kStopState; + } + break; + + case kStopState: + /* Only issue a stop transition if the caller requested it. */ + if ((xfer->flags & kLPI2C_TransferNoStopFlag) == 0) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (!txCount--) + { + state_complete = true; + break; + } + + base->MTDR = kStopCmd; + } + else + { + /* Caller doesn't want to send a stop, so we're done now. */ + *isDone = true; + state_complete = true; + break; + } + handle->state = kWaitForCompletionState; + break; + + case kWaitForCompletionState: + /* We stay in this state until the stop state is detected. */ + if (status & kLPI2C_MasterStopDetectFlag) + { + *isDone = true; + } + state_complete = true; + break; + default: + assert(false); + break; + } + } + return result; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + + /* Handle no start option. */ + if (xfer->flags & kLPI2C_TransferNoStartFlag) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + handle->state = kIssueReadCommandState; + } + else + { + /* Start immediately in the data transfer state. */ + handle->state = kTransferDataState; + } + + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = xfer->dataSize; + } + else + { + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Initial direction depends on whether a subaddress was provided, and of course the actual */ + /* data transfer direction. */ + lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (subaddressRemaining--) + { + uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. */ + cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + } + + /* Set up state machine for transferring the commands. */ + handle->state = kSendCommandState; + handle->remainingBytes = cmdCount; + handle->buf = (uint8_t *)&handle->commandBuffer; + } +} + +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle); + assert(transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != kIdleState) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + LPI2C_InitTransferStateMachine(handle); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_MasterEnableInterrupts(base, kMasterIrqFlags); + + return result; +} + +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint8_t state; + uint16_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); + LPI2C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + LPI2C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case kIdleState: + case kSendCommandState: + case kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ + *count = 0; + break; + + case kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case kStopState: + case kWaitForCompletionState: + default: + *count = dataSize; + break; + } + + return kStatus_Success; +} + +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + if (handle->state != kIdleState) + { + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Send a stop command to finalize the transfer. */ + base->MTDR = kStopCmd; + + /* Reset handle. */ + handle->state = kIdleState; + } +} + +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + if (handle->state == kIdleState) + { + return; + } + + result = LPI2C_RunTransferStateMachine(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Set handle to idle state. */ + handle->state = kIdleState; + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) +{ + slaveConfig->enableSlave = true; + slaveConfig->address0 = 0U; + slaveConfig->address1 = 0U; + slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + slaveConfig->filterDozeEnable = true; + slaveConfig->filterEnable = true; + slaveConfig->enableGeneralCall = false; + slaveConfig->sclStall.enableAck = false; + slaveConfig->sclStall.enableTx = true; + slaveConfig->sclStall.enableRx = true; + slaveConfig->sclStall.enableAddress = false; + slaveConfig->ignoreAck = false; + slaveConfig->enableReceivedAddressRead = false; + slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */ + slaveConfig->sclGlitchFilterWidth_ns = 0; + slaveConfig->dataValidDelay_ns = 0; + slaveConfig->clockHoldTime_ns = 0; +} + +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Ungate the clock. */ + CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Restore to reset conditions. */ + LPI2C_SlaveReset(base); + + /* Configure peripheral. */ + base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); + + base->SCFGR1 = + LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | + LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | + LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | + LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | + LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); + + base->SCFGR2 = + LPI2C_SCFGR2_FILTSDA(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, + (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT), 1)) | + LPI2C_SCFGR2_FILTSCL(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, + (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT), 1)) | + LPI2C_SCFGR2_DATAVD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, + (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 1)) | + LPI2C_SCFGR2_CLKHOLD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, + (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT), 1)); + + /* Save SCR to last so we don't enable slave until it is configured */ + base->SCR = LPI2C_SCR_FILTDZ(slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | + LPI2C_SCR_SEN(slaveConfig->enableSlave); +} + +void LPI2C_SlaveDeinit(LPI2C_Type *base) +{ + LPI2C_SlaveReset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Gate the clock. */ + CLOCK_DisableClock(kLpi2cClocks[instance]); + +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_BitError + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) +{ + status_t result = kStatus_Success; + + flags &= kSlaveErrorFlags; + if (flags) + { + if (flags & kLPI2C_SlaveBitErrFlag) + { + result = kStatus_LPI2C_BitError; + } + else if (flags & kLPI2C_SlaveFifoErrFlag) + { + result = kStatus_LPI2C_FifoError; + } + else + { + assert(false); + } + + /* Clear the errors. */ + LPI2C_SlaveClearStatusFlags(base, flags); + } + + return result; +} + +status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize) +{ + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + size_t remaining = txSize; + + assert(txBuff); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + + while (remaining) + { + uint32_t flags; + status_t result; + + /* Wait until we can transmit. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (result) + { + if (actualTxSize) + { + *actualTxSize = txSize - remaining; + } + return result; + } +#if LPI2C_WAIT_TIMEOUT + } while ( + (!(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) && + (--waitTimes)); + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while ( + !(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + /* Send a byte. */ + if (flags & kLPI2C_SlaveTxReadyFlag) + { + base->STDR = *buf++; + --remaining; + } + + /* Exit loop if we see a stop or restart */ + if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) + { + LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (actualTxSize) + { + *actualTxSize = txSize - remaining; + } + + return kStatus_Success; +} + +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) +{ + uint8_t *buf = (uint8_t *)rxBuff; + size_t remaining = rxSize; + + assert(rxBuff); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + + while (remaining) + { + uint32_t flags; + status_t result; + + /* Wait until we can receive. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (result) + { + if (actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + return result; + } +#if LPI2C_WAIT_TIMEOUT + } while ( + (!(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) && + (--waitTimes)); + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while ( + !(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + /* Receive a byte. */ + if (flags & kLPI2C_SlaveRxReadyFlag) + { + *buf++ = base->SRDR & LPI2C_SRDR_DATA_MASK; + --remaining; + } + + /* Exit loop if we see a stop or restart */ + if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) + { + LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + + return kStatus_Success; +} + +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); + EnableIRQ(kLpi2cIrqs[instance]); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; +} + +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) +{ + uint32_t status; + + assert(handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + status = LPI2C_SlaveGetStatusFlags(base); + if ((status & kLPI2C_SlaveBusBusyFlag) && (!(status & kLPI2C_SlaveBusyFlag))) + { + return kStatus_LPI2C_Busy; + } + + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent; + + /* Ack by default. */ + base->STAR = 0; + + /* Clear all flags. */ + LPI2C_SlaveClearStatusFlags(base, kSlaveClearFlags); + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(base, kSlaveIrqFlags); + + return kStatus_Success; +} + +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transferredCount; + + return kStatus_Success; +} + +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + assert(handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable LPI2C IRQ sources. */ + LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + uint32_t flags; + lpi2c_slave_transfer_t *xfer; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (!handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = LPI2C_SlaveGetStatusFlags(base); + + if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag)) + { + xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); + + if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + if (flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)) + { + xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent : + kLPI2C_SlaveCompletionEvent; + xfer->receivedAddress = 0; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + + if (xfer->event == kLPI2C_SlaveCompletionEvent) + { + handle->isBusy = false; + } + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = false; + } + + /* Clear the flag. */ + LPI2C_SlaveClearStatusFlags(base, flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)); + + /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ + base->STAR = 0; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clean up transfer info on completion, after the callback has been invoked. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + if (flags & kLPI2C_SlaveAddressValidFlag) + { + xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK; + + if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + if (flags & kLPI2C_SlaveTransmitAckFlag) + { + xfer->event = kLPI2C_SlaveTransmitAckEvent; + + if ((handle->eventMask & kLPI2C_SlaveTransmitAckEvent) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + /* Handle transmit and receive. */ + if (flags & kLPI2C_SlaveTxReadyFlag) + { + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveTransmitEvent; + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + /* Transmit a byte. */ + if ((xfer->data) && (xfer->dataSize)) + { + base->STDR = *xfer->data++; + --xfer->dataSize; + ++handle->transferredCount; + } + } + if (flags & kLPI2C_SlaveRxReadyFlag) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveReceiveEvent; + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + /* Receive a byte. */ + if ((xfer->data) && (xfer->dataSize)) + { + *xfer->data++ = base->SRDR; + --xfer->dataSize; + ++handle->transferredCount; + } + else + { + /* We don't have any room to receive more data, so send a nack. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + } + } +} + +/*! + * @brief Shared IRQ handler that can call both master and slave ISRs. + * + * The master and slave ISRs are called through function pointers in order to decouple + * this code from the ISR functions. Without this, the linker would always pull in both + * ISRs and every function they call, even if only the functional API was used. + * + * @param base The LPI2C peripheral base address. + * @param instance The LPI2C peripheral instance number. + */ +static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((base->MCR & LPI2C_MCR_MEN_MASK) && s_lpi2cMasterIsr) + { + /* Master mode. */ + s_lpi2cMasterIsr(base, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((base->SCR & LPI2C_SCR_SEN_MASK) && s_lpi2cSlaveIsr) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(base, s_lpi2cSlaveHandle[instance]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(LPI2C0) +/* Implementation of LPI2C0 handler named in startup code. */ +void LPI2C0_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C0, 0); +} +#endif + +#if defined(LPI2C1) +/* Implementation of LPI2C1 handler named in startup code. */ +void LPI2C1_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C1, 1); +} +#endif + +#if defined(LPI2C2) +/* Implementation of LPI2C2 handler named in startup code. */ +void LPI2C2_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C2, 2); +} +#endif + +#if defined(LPI2C3) +/* Implementation of LPI2C3 handler named in startup code. */ +void LPI2C3_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C3, 3); +} +#endif + +#if defined(LPI2C4) +/* Implementation of LPI2C4 handler named in startup code. */ +void LPI2C4_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C4, 4); +} +#endif + +#if defined(CM4_0__LPI2C) +/* Implementation of CM4_0__LPI2C handler named in startup code. */ +void M4_0_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C)); +} +#endif + +#if defined(CM4__LPI2C) +/* Implementation of CM4__LPI2C handler named in startup code. */ +void M4_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C)); +} +#endif + +#if defined(CM4_1__LPI2C) +/* Implementation of CM4_1__LPI2C handler named in startup code. */ +void M4_1_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C)); +} +#endif + +#if defined(DMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void DMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0)); +} +#endif + +#if defined(DMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void DMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1)); +} +#endif + +#if defined(DMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void DMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2)); +} +#endif + +#if defined(DMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3)); +} +#endif + +#if defined(DMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4)); +} +#endif + +#if defined(ADMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void ADMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0)); +} +#endif + +#if defined(ADMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void ADMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1)); +} +#endif + +#if defined(ADMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void ADMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2)); +} +#endif + +#if defined(ADMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3)); +} +#endif + +#if defined(ADMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4)); +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c.h new file mode 100644 index 0000000000..1706a548ef --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c.h @@ -0,0 +1,1293 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPI2C_H_ +#define _FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C driver version 2.1.5. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef LPI2C_WAIT_TIMEOUT +#define LPI2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum _lpi2c_status +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t + flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for available + options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! +* @brief Deinitializes the LPI2C master peripheral. +* + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param config Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MRDR; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return (base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval #kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! +* @brief Deinitializes the LPI2C slave peripheral. +* + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/*@}*/ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} + +/*@}*/ + +/*! @name Slave interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/*@}*/ + +/*! @name Slave DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/*@}*/ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return (base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_LPI2C_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.c new file mode 100644 index 0000000000..b79dea63a1 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.c @@ -0,0 +1,486 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpi2c_edma.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma" +#endif + +/* @brief Mask to align an address to 32 bytes. */ +#define ALIGN_32_MASK (0x1fU) + +/*! @brief Common sets of flags used by the driver. */ +enum _lpi2c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterDataMatchFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag, + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, +}; + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); + +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); + +/******************************************************************************* + * Code + ******************************************************************************/ + +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData) +{ + assert(handle); + assert(rxDmaHandle); + assert(txDmaHandle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ + /* in order to make the transfer API code simpler. */ + handle->base = base; + handle->completionCallback = callback; + handle->userData = userData; + handle->rx = rxDmaHandle; + handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle; + + /* Set DMA channel completion callbacks. */ + EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); + } +} + +/*! + * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. + * @param handle Master DMA driver handle. + * @return Number of command words. + */ +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Handle no start option. */ + if (xfer->flags & kLPI2C_TransferNoStartFlag) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + } + } + else + { + /* + * Initial direction depends on whether a subaddress was provided, and of course the actual + * data transfer direction. + */ + lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (subaddressRemaining--) + { + uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ + if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. */ + cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + } + } + + return cmdCount; +} + +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle); + assert(transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* We're now busy. */ + handle->isBusy = true; + + /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + LPI2C_MasterEnableDMA(base, false, false); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + uint32_t commandCount = LPI2C_GenerateCommands(handle); + + /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ + if ((!commandCount) && (transfer->dataSize == 0)) + { + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + return kStatus_Success; + } + + /* Reset DMA channels. */ + EDMA_ResetChannel(handle->rx->base, handle->rx->channel); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_ResetChannel(handle->tx->base, handle->tx->channel); + } + + /* Get a 32-byte aligned TCD pointer. */ + edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); + + bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize); + bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize); + + edma_transfer_config_t transferConfig; + edma_tcd_t *linkTcd = NULL; + + /* Set up data transmit. */ + if (hasSendData) + { + transferConfig.srcAddr = (uint32_t)transfer->data; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = sizeof(uint8_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = transferConfig.minorLoopBytes; + + if (commandCount) + { + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); + linkTcd = tcd; + } + else + { + /* User is only transmitting data with no required commands, so this transfer can stand alone. */ + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); + } + } + else if (hasReceiveData) + { + /* Set up data receive. */ + transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); + transferConfig.destAddr = (uint32_t)transfer->data; + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = transferConfig.minorLoopBytes; + + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) || (!commandCount)) + { + /* We can put this receive transfer on its own DMA channel. */ + EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, kEDMA_MajorInterruptEnable); + } + else + { + /* For shared rx/tx DMA requests when there are commands, create a software TCD which will be */ + /* chained onto the commands transfer, notice that in this situation assume tx/rx uses same channel */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); + linkTcd = tcd; + } + } + else + { + /* No data to send */ + } + + /* Set up commands transfer. */ + if (commandCount) + { + transferConfig.srcAddr = (uint32_t)handle->commandBuffer; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.srcOffset = sizeof(uint16_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = commandCount; + + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); + } + + /* Start DMA transfer. */ + if (hasReceiveData || !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_StartTransfer(handle->rx); + } + + if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); + } + + if ((hasSendData || commandCount) && FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_StartTransfer(handle->tx); + } + + /* Enable DMA in both directions. This actually kicks of the transfer. */ + LPI2C_MasterEnableDMA(base, true, true); + + return result; +} + +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint32_t remaining = handle->transfer.dataSize; + + /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ + /* we do nothing and return the number of transferred bytes as zero. */ + if (EDMA_GetNextTCDAddress(handle->tx) == 0) + { + if (handle->transfer.direction == kLPI2C_Write) + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); + } + else + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); + } + } + + *count = handle->transfer.dataSize - remaining; + + return kStatus_Success; +} + +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) +{ + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + return kStatus_LPI2C_Idle; + } + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Send a stop command to finalize the transfer. */ + base->MTDR = kStopCmd; + + /* Reset handle. */ + handle->isBusy = false; + + return kStatus_Success; +} + +/*! + * @brief DMA completion callback. + * @param dmaHandle DMA channel handle for the channel that completed. + * @param userData User data associated with the channel handle. For this callback, the user data is the + * LPI2C DMA driver handle. + * @param isTransferDone Whether the DMA transfer has completed. + * @param tcds Number of TCDs that completed. + */ +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) +{ + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; + bool hasReceiveData; + + if (!handle) + { + return; + } + + hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize); + + if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (EDMA_GetNextTCDAddress(handle->tx) != 0) + { + LPI2C_MasterEnableDMA(handle->base, false, true); + } + } + + /* Check for errors. */ + status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); + + /* Done with this transaction. */ + handle->isBusy = false; + + if (!(handle->transfer.flags & kLPI2C_TransferNoStopFlag)) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = kStopCmd; + } + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(handle->base, handle, result, handle->userData); + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.h new file mode 100644 index 0000000000..b66edbfd4b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpi2c_edma.h @@ -0,0 +1,183 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPI2C_EDMA_H_ +#define _FSL_LPI2C_EDMA_H_ + +#include "fsl_lpi2c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C EDMA driver version 2.1.5. */ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; + +/*! + * @brief Master DMA completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterCreateEDMAHandle(). + * + * @param base The LPI2C peripheral base address. + * @param handle Handle associated with the completed transfer. + * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Driver handle for master DMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_edma_handle +{ + LPI2C_Type *base; /*!< LPI2C base pointer. */ + bool isBusy; /*!< Transfer state machine current state. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rx; /*!< Handle for receive DMA channel. */ + edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ + edma_tcd_t tcds[2]; /*!< Software TCD. Two are allocated to provide enough room to align to 32-bytes. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*@{*/ + +/*! + * @brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_LPI2C_EDMA_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi.c new file mode 100644 index 0000000000..3a515e1739 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi.c @@ -0,0 +1,1851 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpspi.h" + +/******************************************************************************* +* Definitions +******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi" +#endif + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpspi_default_watermarks +{ + kLpspiDefaultTxWatermark = 0, + kLpspiDefaultRxWatermark = 0, +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*lpspi_master_isr_t)(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Configures the LPSPI peripheral chip select polarity. +* +* This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and +* configures the Pcs signal to operate with the desired characteristic. +* +* @param base LPSPI peripheral address. +* @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to +* apply the active high or active low characteristic. +* @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of +* type lpspi_pcs_polarity_config_t. +*/ +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh); + +/*! +* @brief Combine the write data for 1 byte to 4 bytes. +* This is not a public API. +*/ +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap); + +/*! +* @brief Separate the read data for 1 byte to 4 bytes. +* This is not a public API. +*/ +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*! +* @brief Master fill up the TX FIFO with data. +* This is not a public API. +*/ +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! +* @brief Master finish up a transfer. +* It would call back if there is callback function and set the state to idle. +* This is not a public API. +*/ +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! +* @brief Slave fill up the TX FIFO with data. +* This is not a public API. +*/ +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! +* @brief Slave finish up a transfer. +* It would call back if there is callback function and set the state to idle. +* This is not a public API. +*/ +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! +* @brief LPSPI common interrupt handler. +* +* @param handle pointer to s_lpspiHandle which stores the transfer state. +*/ +static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param); + +/******************************************************************************* +* Variables +******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; + +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi IRQ number for each instance. */ +static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to lpspi clocks for each instance. */ +static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; + +#if defined(LPSPI_PERIPH_CLOCKS) +static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to lpspi handles for each instance. */ +static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)] = {NULL}; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpspi_master_isr_t s_lpspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpspi_slave_isr_t s_lpspiSlaveIsr; +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; +/********************************************************************************************************************** +* Code +*********************************************************************************************************************/ +uint32_t LPSPI_GetInstance(LPSPI_Type *base) +{ + uint8_t instance = 0; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) + { + if (s_lpspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpspiBases)); + + return instance; +} + +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = LPSPI_GetInstance(base); + g_lpspiDummyData[instance] = dummyData; +} + +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig); + + uint32_t tcrPrescaleValue = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset to known status */ + LPSPI_Reset(base); + + /* Set LPSPI to master */ + LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); + + /* Set specific PCS to active high or low */ + LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + /* Set Configuration Register 1 related setting.*/ + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) | + LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | + LPSPI_CFGR1_NOSTALL(0); + + /* Set baudrate and delay times*/ + LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); + + /* Set default watermarks */ + LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); + + /* Set Transmit Command Register*/ + base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | + LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1) | + LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); + + LPSPI_Enable(base, true); + + LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); + LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); + LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, srcClock_Hz); + + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); +} + +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) +{ + assert(masterConfig); + + masterConfig->baudRate = 500000; + masterConfig->bitsPerFrame = 8; + masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig->direction = kLPSPI_MsbFirst; + + masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + + masterConfig->whichPcs = kLPSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + + masterConfig->pinCfg = kLPSPI_SdiInSdoOut; + masterConfig->dataOutConfig = kLpspiDataOutRetained; +} + +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset to known status */ + LPSPI_Reset(base); + + LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); + + LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); + + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | + LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); + + LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); + + base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | + LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1); + + /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); + + LPSPI_Enable(base, true); +} + +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ + slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ + slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ + slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ + + slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ + slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ + + slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; + slaveConfig->dataOutConfig = kLpspiDataOutRetained; +} + +void LPSPI_Reset(LPSPI_Type *base) +{ + /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ + base->CR |= LPSPI_CR_RST_MASK; + + /* Software reset doesn't reset the CR, so manual reset the FIFOs */ + base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; + + /* Master logic is not reset and module is disabled.*/ + base->CR = 0x00U; +} + +void LPSPI_Deinit(LPSPI_Type *base) +{ + /* Reset to default value */ + LPSPI_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + CLOCK_DisableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t cfgr1Value = 0; + /* Clear the PCS polarity bit */ + cfgr1Value = base->CFGR1 & ~(1U << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); + + /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ + base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); +} + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue) +{ + assert(tcrPrescaleValue); + + /* For master mode configuration only, if slave mode detected, return 0. + * Also, the LPSPI module needs to be disabled first, if enabled, return 0 + */ + if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK)) + { + return 0; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t desiredBaudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + + /* Set to maximum divisor value bit settings so that if baud rate passed in is less + * than the minimum possible baud rate, then the SPI will be configured to the lowest + * possible baud rate + */ + bestPrescaler = 7; + bestScaler = 255; + + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 256) && min_diff; scaler++) + { + realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); + + /* calculate the baud rate difference based on the conditional statement + * that states that the calculated baud rate must not exceed the desired baud rate + */ + if (desiredBaudrate >= realBaudrate) + { + diff = desiredBaudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + } + } + } + } + + /* Write the best baud rate scalar to the CCR. + * Note, no need to check for error since we've already checked to make sure the module is + * disabled and in master mode. Also, there is a limit on the maximum divider so we will not + * exceed this. + */ + base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); + + /* return the best prescaler value for user to use later */ + *tcrPrescaleValue = bestPrescaler; + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) +{ + /*These settings are only relevant in master mode */ + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); + + break; + default: + assert(false); + break; + } +} + +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz) +{ + uint64_t realDelay, bestDelay; + uint32_t scaler, bestScaler; + uint32_t diff, min_diff; + uint64_t initialDelayNanoSec; + uint32_t clockDividedPrescaler; + + /* For delay between transfer, an additional scaler value is needed */ + uint32_t additionalScaler = 0; + + /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between + * transfers.*/ + clockDividedPrescaler = + srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; + + /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ + min_diff = 0xFFFFFFFFU; + + /* Initialize scaler to max value to generate the max delay */ + bestScaler = 0xFFU; + + /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as + * the delay divisors are slightly different based on which delay we are configuring. + */ + if (whichDelay == kLPSPI_BetweenTransfer) + { + /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of + calculated values (uint64_t), we need to break up the calculation into several steps to ensure + accurate calculated results + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec *= 2U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated + values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated + results. + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 0; + } + + /* If the initial, default delay is already greater than the desired delay, then + * set the delay to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + LPSPI_MasterSetDelayScaler(base, 0, whichDelay); + return initialDelayNanoSec; + } + + /* If min_diff = 0, the exit for loop */ + for (scaler = 0; (scaler < 256U) && min_diff; scaler++) + { + /* Calculate the real delay value as we cycle through the scaler values. + Due to large size of calculated values (uint64_t), we need to break up the + calculation into several steps to ensure accurate calculated results + */ + realDelay = 1000000000U; + realDelay *= (scaler + 1 + additionalScaler); + realDelay /= clockDividedPrescaler; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = realDelay - delayTimeInNanoSec; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + + /* write the best scaler value for the delay */ + LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + + /* return the actual calculated delay value (in ns) */ + return bestDelay; +} + +/*Transactional APIs -- Master*/ + +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + s_lpspiHandle[LPSPI_GetInstance(base)] = handle; + + /* Set irq handler. */ + s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; + + handle->callback = callback; + handle->userData = userData; +} + +bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) +{ + assert(transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return false; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return false; + } + + /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . + *For bytesPerFrame greater than 4 situation: + *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , + *otherwise , the transfer data size can be integer multiples of bytesPerFrame. + */ + if (bytesPerFrame <= 4) + { + if ((transfer->dataSize % bytesPerFrame) != 0) + { + return false; + } + } + else + { + if ((bytesPerFrame % 4U) != 0) + { + if (transfer->dataSize != bytesPerFrame) + { + return false; + } + } + else + { + if ((transfer->dataSize % bytesPerFrame) != 0) + { + return false; + } + } + } + + return true; +} + +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) +{ + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /* Check that LPSPI is not busy.*/ + if (LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag) + { + return kStatus_LPSPI_Busy; + } + + uint8_t *txData = transfer->txData; + uint8_t *rxData = transfer->rxData; + uint32_t txRemainingByteCount = transfer->dataSize; + uint32_t rxRemainingByteCount = transfer->dataSize; + + uint8_t bytesEachWrite; + uint8_t bytesEachRead; + + uint32_t readData = 0; + uint32_t wordToSend = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + uint32_t fifoSize = LPSPI_GetRxFifoSize(base); + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); + bool isRxMask = false; + bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + + if (!rxData) + { + isRxMask = true; + } + + LPSPI_Enable(base, false); + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((txData) && (rxData)) + { + return kStatus_InvalidArgument; + } + } + LPSPI_Enable(base, true); + + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_PCS(whichPcs); + + if (bytesPerFrame <= 4) + { + bytesEachWrite = bytesPerFrame; + bytesEachRead = bytesPerFrame; + } + else + { + bytesEachWrite = 4; + bytesEachRead = 4; + } + + /*Write the TX data until txRemainingByteCount is equal to 0 */ + while (txRemainingByteCount > 0) + { + if (txRemainingByteCount < bytesEachWrite) + { + bytesEachWrite = txRemainingByteCount; + } + + /*Wait until TX FIFO is not full*/ + while (LPSPI_GetTxFifoCount(base) == fifoSize) + { + } + + if (txData) + { + wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); + txData += bytesEachWrite; + } + + LPSPI_WriteData(base, wordToSend); + txRemainingByteCount -= bytesEachWrite; + + /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/ + if (rxData) + { + while (LPSPI_GetRxFifoCount(base)) + { + readData = LPSPI_ReadData(base); + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } + } + } + + /* After write all the data in TX FIFO , should write the TCR_CONTC to 0 to de-assert the PCS. Note that TCR + * register also use the TX FIFO. + */ + while ((LPSPI_GetTxFifoCount(base) == fifoSize)) + { + } + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + + /*Read out the RX data in FIFO*/ + if (rxData) + { + while (rxRemainingByteCount > 0) + { + while (LPSPI_GetRxFifoCount(base)) + { + readData = LPSPI_ReadData(base); + + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } + } + } + else + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag)) + { + } + } + + return kStatus_Success; +} + +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + handle->state = kLPSPI_Busy; + + bool isRxMask = false; + + uint8_t txWatermark; + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeTcrInIsr = false; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (handle->fifoSize > 1) + { + txWatermark = 1; + handle->rxWatermark = handle->fifoSize - 2; + } + else + { + txWatermark = 0; + handle->rxWatermark = 0; + } + + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + LPSPI_Enable(base, false); + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + LPSPI_Enable(base, true); + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /* If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO). + * For master transfer , we'd better not masked the transmit data in TCR since the transfer flow is hard to + * controlled by software.*/ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | + LPSPI_TCR_PCS(whichPcs); + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + } + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + while (LPSPI_GetTxFifoCount(base) != 0) + { + } + /*Fill up the TX data in FIFO */ + LPSPI_MasterTransferFillUpTxFifo(base, handle); + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); + } + + LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + uint32_t wordToSend = 0; + + /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth + * and that the number of TX FIFO entries does not exceed the FIFO depth. + * But no need to make the protection if there is no rxData. + */ + while ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) && + (((handle->readRegRemainingTimes - handle->writeRegRemainingTimes) < handle->fifoSize) || + (handle->rxData == NULL))) + { + if (handle->txRemainingByteCount < handle->bytesEachWrite) + { + handle->bytesEachWrite = handle->txRemainingByteCount; + } + + if (handle->txData) + { + wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); + handle->txData += handle->bytesEachWrite; + } + else + { + wordToSend = handle->txBuffIfNull; + } + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + /*Decrease the write TX register times.*/ + --handle->writeRegRemainingTimes; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= handle->bytesEachWrite; + + if (handle->txRemainingByteCount == 0) + { + /* If PCS is continuous, update TCR to de-assert PCS */ + if (handle->isPcsContinuous) + { + /* Only write to the TCR if the FIFO has room */ + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + /* Else, set a global flag to tell the ISR to do write to the TCR */ + else + { + handle->writeTcrInIsr = true; + } + } + break; + } + } +} + +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + handle->state = kLPSPI_Idle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_Success, handle->userData); + } +} + +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + LPSPI_Reset(base); + + handle->state = kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + uint32_t readData; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts based on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable); + + while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < handle->bytesEachRead) + { + handle->bytesEachRead = handle->rxRemainingByteCount; + } + + LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); + handle->rxData += handle->bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= handle->bytesEachRead; + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (handle->rxRemainingByteCount) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) + { + base->FCR = + (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); + } + } + + if (handle->txRemainingByteCount) + { + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + else + { + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + if ((handle->isPcsContinuous) && (handle->writeTcrInIsr)) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + } + } + + if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0) && (!handle->writeTcrInIsr)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + if (handle->rxData == NULL) + { + if (LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag) + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + else + { + LPSPI_EnableInterrupts(base, kLPSPI_TransferCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + } +} + +/*Transactional APIs -- Slave*/ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + s_lpspiHandle[LPSPI_GetInstance(base)] = handle; + + /* Set irq handler. */ + s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; + + handle->callback = callback; + handle->userData = userData; +} + +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + handle->state = kLPSPI_Busy; + + bool isRxMask = false; + bool isTxMask = false; + + uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_SlaveByteSwap); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + uint8_t txWatermark; + if (handle->fifoSize > 1) + { + txWatermark = 1; + handle->rxWatermark = handle->fifoSize - 2; + } + else + { + txWatermark = 0; + handle->rxWatermark = 0; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + LPSPI_Enable(base, false); + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + LPSPI_Enable(base, true); + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + /*If there is not txData , can mask the transmit data (no data is loaded from transmit FIFO and output pin + * is tristated). + */ + if (handle->txData == NULL) + { + isTxMask = true; + handle->txRemainingByteCount = 0; + } + + base->TCR = (base->TCR & + ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK | + LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | + LPSPI_TCR_PCS(whichPcs); + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + } + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + while (LPSPI_GetTxFifoCount(base) != 0) + { + } + + /*Fill up the TX data in FIFO */ + if (handle->txData) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); + } + + LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); + } + + if (handle->rxData) + { + /* RX FIFO overflow request enable */ + LPSPI_EnableInterrupts(base, kLPSPI_ReceiveErrorInterruptEnable); + } + if (handle->txData) + { + /* TX FIFO underflow request enable */ + LPSPI_EnableInterrupts(base, kLPSPI_TransmitErrorInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + uint32_t wordToSend = 0; + + while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) + { + if (handle->txRemainingByteCount < handle->bytesEachWrite) + { + handle->bytesEachWrite = handle->txRemainingByteCount; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); + handle->txData += handle->bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= handle->bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + if (handle->txRemainingByteCount == 0) + { + break; + } + } +} + +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + status_t status = 0; + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + if (handle->state == kLPSPI_Error) + { + status = kStatus_LPSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = kLPSPI_Idle; + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } +} + +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); + + LPSPI_Reset(base); + + handle->state = kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + uint32_t readData; /* variable to store word read from RX FIFO */ + uint32_t wordToSend; /* variable to store word to write to TX FIFO */ + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount > 0) + { + while (LPSPI_GetRxFifoCount(base)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < handle->bytesEachRead) + { + handle->bytesEachRead = handle->rxRemainingByteCount; + } + + LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); + handle->rxData += handle->bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= handle->bytesEachRead; + + if ((handle->txRemainingByteCount > 0) && (handle->txData != NULL)) + { + if (handle->txRemainingByteCount < handle->bytesEachWrite) + { + handle->bytesEachWrite = handle->txRemainingByteCount; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); + handle->txData += handle->bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= handle->bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + } + + if (handle->rxRemainingByteCount == 0) + { + break; + } + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) + { + base->FCR = + (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); + } + } + else if ((handle->txRemainingByteCount) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + else + { + __NOP(); + } + + if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ + if (handle->rxData == NULL) + { + if ((LPSPI_GetStatusFlags(base) & kLPSPI_FrameCompleteFlag) && (LPSPI_GetTxFifoCount(base) == 0)) + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + else + { + LPSPI_ClearStatusFlags(base, kLPSPI_FrameCompleteFlag); + LPSPI_EnableInterrupts(base, kLPSPI_FrameCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if ((LPSPI_GetStatusFlags(base) & kLPSPI_TransmitErrorFlag) && (base->IER & LPSPI_IER_TEIE_MASK)) + { + LPSPI_ClearStatusFlags(base, kLPSPI_TransmitErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kLPSPI_Error; + } + handle->errorCount++; + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if ((LPSPI_GetStatusFlags(base) & kLPSPI_ReceiveErrorFlag) && (base->IER & LPSPI_IER_REIE_MASK)) + { + LPSPI_ClearStatusFlags(base, kLPSPI_ReceiveErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kLPSPI_Error; + } + handle->errorCount++; + } +} + +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap) +{ + assert(txData); + + uint32_t wordToSend = 0; + + switch (bytesEachWrite) + { + case 1: + wordToSend = *txData; + ++txData; + break; + + case 2: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + + break; + + case 3: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + case 4: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 24U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 24U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + default: + assert(false); + break; + } + return wordToSend; +} + +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData); + + switch (bytesEachRead) + { + case 1: + *rxData = readData; + ++rxData; + break; + + case 2: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + } + else + { + *rxData = readData >> 8; + ++rxData; + *rxData = readData; + ++rxData; + } + break; + + case 3: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData >> 16; + ++rxData; + } + else + { + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData; + ++rxData; + } + break; + + case 4: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 24; + ++rxData; + } + else + { + *rxData = readData >> 24; + ++rxData; + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData; + ++rxData; + } + break; + + default: + assert(false); + break; + } +} + +static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param) +{ + if (LPSPI_IsMaster(base)) + { + s_lpspiMasterIsr(base, (lpspi_master_handle_t *)param); + } + else + { + s_lpspiSlaveIsr(base, (lpspi_slave_handle_t *)param); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(LPSPI0) +void LPSPI0_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[0]); + LPSPI_CommonIRQHandler(LPSPI0, s_lpspiHandle[0]); +} +#endif + +#if defined(LPSPI1) +void LPSPI1_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[1]); + LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]); +} +#endif + +#if defined(LPSPI2) +void LPSPI2_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[2]); + LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]); +} +#endif + +#if defined(LPSPI3) +void LPSPI3_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[3]); + LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]); +} +#endif + +#if defined(LPSPI4) +void LPSPI4_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[4]); + LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]); +} +#endif + +#if defined(LPSPI5) +void LPSPI5_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[5]); + LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]); +} +#endif + +#if defined(DMA__LPSPI0) +void DMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); + LPSPI_CommonIRQHandler(DMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); +} +#endif + +#if defined(DMA__LPSPI1) +void DMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); + LPSPI_CommonIRQHandler(DMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); +} +#endif +#if defined(DMA__LPSPI2) +void DMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); + LPSPI_CommonIRQHandler(DMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); +} +#endif + +#if defined(DMA__LPSPI3) +void DMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); + LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); +} +#endif + +#if defined(ADMA__LPSPI0) +void ADMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); +} +#endif + +#if defined(ADMA__LPSPI1) +void ADMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); +} +#endif +#if defined(ADMA__LPSPI2) +void ADMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); +} +#endif + +#if defined(ADMA__LPSPI3) +void ADMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi.h new file mode 100644 index 0000000000..72895a225b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi.h @@ -0,0 +1,1145 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPSPI_H_ +#define _FSL_LPSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpspi_driver + * @{ + */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI driver version 2.0.1. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#ifndef LPSPI_DUMMY_DATA +/*! @brief LPSPI dummy data if no Tx data.*/ +#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ +#endif + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_lpspiDummyData[]; + +/*! @brief Status for the LPSPI driver.*/ +enum _lpspi_status +{ + kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ + kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ + kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ + kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */ +}; + +/*! @brief LPSPI status flags in SPIx_SR register.*/ +enum _lpspi_flags +{ + kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ + kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ + kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ + kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ + kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ + kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ + kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ + kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ + kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ + kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | + LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | + LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ +}; + +/*! @brief LPSPI interrupt source.*/ +enum _lpspi_interrupt_enable +{ + kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ + kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ + kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ + kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ + kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ + kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ + kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ + kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ + kLPSPI_AllInterruptEnable = + (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | + LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ +}; + +/*! @brief LPSPI DMA source.*/ +enum _lpspi_dma_enable +{ + kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ + kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ +}; + +/*! @brief LPSPI master or slave mode configuration.*/ +typedef enum _lpspi_master_slave_mode +{ + kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ + kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ +} lpspi_master_slave_mode_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ +typedef enum _lpspi_which_pcs_config +{ + kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ + kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ + kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ + kLPSPI_Pcs3 = 3U /*!< PCS[3] */ +} lpspi_which_pcs_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ +typedef enum _lpspi_pcs_polarity_config +{ + kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ + kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ +} lpspi_pcs_polarity_config_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ +enum _lpspi_pcs_polarity +{ + kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief LPSPI clock polarity configuration.*/ +typedef enum _lpspi_clock_polarity +{ + kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ + kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ +} lpspi_clock_polarity_t; + +/*! @brief LPSPI clock phase configuration.*/ +typedef enum _lpspi_clock_phase +{ + kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} lpspi_clock_phase_t; + +/*! @brief LPSPI data shifter direction options.*/ +typedef enum _lpspi_shift_direction +{ + kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} lpspi_shift_direction_t; + +/*! @brief LPSPI Host Request select configuration. */ +typedef enum _lpspi_host_request_select +{ + kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ + kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ +} lpspi_host_request_select_t; + +/*! @brief LPSPI Match configuration options. */ +typedef enum _lpspi_match_config +{ + kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ + kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ +} lpspi_match_config_t; + +/*! @brief LPSPI pin (SDO and SDI) configuration. */ +typedef enum _lpspi_pin_config +{ + kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ + kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ + kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ + kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ +} lpspi_pin_config_t; + +/*! @brief LPSPI data output configuration. */ +typedef enum _lpspi_data_out_config +{ + kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ + kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ +} lpspi_data_out_config_t; + +/*! @brief LPSPI transfer width configuration. */ +typedef enum _lpspi_transfer_width +{ + kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} lpspi_transfer_width_t; + +/*! @brief LPSPI delay type selection.*/ +typedef enum _lpspi_delay_type +{ + kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ + kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ + kLPSPI_BetweenTransfer /*!< Delay between transfers. */ +} lpspi_delay_type_t; + +#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ +#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_master +{ + kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ + kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ + kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ + kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ + + kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ + + kLPSPI_MasterByteSwap = + 1U << 22 /*!< Is master swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ +}; + +#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ +#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_slave +{ + kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ + kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ + kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ + kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ + + kLPSPI_SlaveByteSwap = + 1U << 22 /*!< Is slave swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ +}; + +/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ +enum _lpspi_transfer_state +{ + kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kLPSPI_Busy, /*!< Transfer queue is not finished. */ + kLPSPI_Error /*!< Transfer error. */ +}; + +/*! @brief LPSPI master configuration structure.*/ +typedef struct _lpspi_master_config +{ + uint32_t baudRate; /*!< Baud Rate for LPSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. + It sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum + delay. It sets the boundary value if out of range.*/ + uint32_t + betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the minimum + delay. It sets the boundary value if out of range.*/ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_master_config_t; + +/*! @brief LPSPI slave configuration structure.*/ +typedef struct _lpspi_slave_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_slave_config_t; + +/*! +* @brief Forward declaration of the _lpspi_master_handle typedefs. +*/ +typedef struct _lpspi_master_handle lpspi_master_handle_t; + +/*! +* @brief Forward declaration of the _lpspi_slave_handle typedefs. +*/ +typedef struct _lpspi_slave_handle lpspi_slave_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Slave completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master/slave transfer structure.*/ +typedef struct _lpspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t + configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the + transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer + is used for slave.*/ +} lpspi_transfer_t; + +/*! @brief LPSPI master transfer handle structure used for transactional API. */ +struct _lpspi_master_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief LPSPI slave transfer handle structure used for transactional API. */ +struct _lpspi_slave_handle +{ + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the LPSPI master. + * + * @param base LPSPI peripheral address. + * @param masterConfig Pointer to structure lpspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * @code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); + +/*! + * @brief LPSPI slave configuration. + * + * @param base LPSPI peripheral address. + * @param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * @code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * @param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base); + +/*! + * @brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * @param base LPSPI peripheral address. +*/ +void LPSPI_Reset(LPSPI_Type *base); + +/*! + * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. + * + * @param base LPSPI peripheral address. + * @param enable Pass true to enable module, false to disable module. + */ +static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) +{ + if (enable) + { + base->CR |= LPSPI_CR_MEN_MASK; + } + else + { + base->CR &= ~LPSPI_CR_MEN_MASK; + } +} + +/*! + *@} +*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the LPSPI status flag state. + * @param base LPSPI peripheral address. + * @return The LPSPI status(in SR register). + */ +static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Gets the LPSPI Tx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Tx FIFO size. + */ +static inline uint32_t LPSPI_GetTxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Rx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Rx FIFO size. + */ +static inline uint32_t LPSPI_GetRxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Tx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the transmit FIFO. + */ +static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); +} + +/*! + * @brief Gets the LPSPI Rx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the receive FIFO. + */ +static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); +} + +/*! + * @brief Clears the LPSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. + * Example usage: + * @code + * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); + * @endcode + * + * @param base LPSPI peripheral address. + * @param statusFlags The status flag used from type _lpspi_flags. + */ +static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} +*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the LPSPI interrupts. + * + * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. + * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. + * + * @code + * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the LPSPI interrupts. + * + * @code + * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + *@} +*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER |= mask; +} + +/*! + * @brief Disables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER &= ~mask; +} + +/*! + * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. + * + * This function gets the LPSPI Transmit Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Transmit Data Register address. + */ +static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->TDR); +} + +/*! + * @brief Gets the LPSPI Receive Data Register address for a DMA operation. + * + * This function gets the LPSPI Receive Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Receive Data Register address. + */ +static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->RDR); +} + +/*! + *@} +*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! +* @brief Get instance number for LPSPI module. +* +* @param base LPSPI peripheral base address. +* @return Return the value of LPSPI instance. +*/ +uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! +* @brief Check the argument for transfer . +* +* @param transfer the transfer struct to be used. +* @param bitPerFrame The bit size of one frame. +* @param bytePerFrame The byte size of one frame. +* @return Return true for right and false for wrong. +*/ +bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); + +/*! + * @brief Configures the LPSPI for either master or slave. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * @param base LPSPI peripheral address. + * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. + */ +static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) +{ + base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); +} + +/*! + * @brief Returns whether the LPSPI module is in master mode. + * + * @param base LPSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool LPSPI_IsMaster(LPSPI_Type *base) +{ + return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); +} + +/*! + * @brief Flushes the LPSPI FIFOs. + * + * @param base LPSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. + */ +static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); +} + +/*! + * @brief Sets the transmit and receive FIFO watermark values. + * + * This function allows the user to set the receive and transmit FIFO watermarks. The function + * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be + * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. + * + * @param base LPSPI peripheral address. + * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + */ +static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) +{ + base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); +} + +/*! + * @brief Configures all LPSPI peripheral chip select polarities simultaneously. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of + * PCS is device-specific. + * @code + * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. + */ +static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) +{ + base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); +} + +/*! + * @brief Configures the frame size. + * + * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal + * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word + * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not + * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. + * + * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although + * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command + * register + * should only be changed if the LPSPI is idle. + * + * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That + * means the TCR register should be written to when the Tx FIFO is not full. + * + * @param base LPSPI peripheral address. + * @param frameSize The frame size in number of bits. + */ +static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) +{ + base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1); +} + +/*! + * @brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param baudRate_Bps The desired baud rate in bits per second. + * @param srcClock_Hz Module source input clock in Hertz. + * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * @return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue); + +/*! + * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param scaler The 8-bit delay value 0x00 to 0xFF (255). + * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * @param base LPSPI peripheral address. + * @param delayTimeInNanoSec The desired delay value in nano-seconds. + * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * @param srcClock_Hz Module source input clock in Hertz. + * @return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz); + +/*! + * @brief Writes data into the transmit data buffer. + * + * This function writes data passed in by the user to the Transmit Data Register (TDR). + * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, + * the user has to manage sending the data one 32-bit word at a time. + * Any writes to the TDR result in an immediate push to the transmit FIFO. + * This function can be used for either master or slave modes. + * + * @param base LPSPI peripheral address. + * @param data The data word to be sent. + */ +static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) +{ + base->TDR = data; +} + +/*! + * @brief Reads data from the data buffer. + * + * This function reads the data from the Receive Data Register (RDR). + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The data read from the data buffer. + */ +static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) +{ + return (base->RDR); +} + +/*! + * @brief Set up the dummy data. + * + * @param base LPSPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); + +/*! + *@} +*/ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_master_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); + +/*! + * @brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_slave_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + *@} +*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + /*! + *@} + */ + +#endif /*_FSL_LPSPI_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi_edma.c new file mode 100644 index 0000000000..cbc7af7e76 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi_edma.c @@ -0,0 +1,1056 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpspi_edma.h" + +/*********************************************************************************************************************** +* Definitions +***********************************************************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi_edma" +#endif + +/*! +* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. +*/ +typedef struct _lpspi_master_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ +} lpspi_master_edma_private_handle_t; + +/*! +* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. +*/ +typedef struct _lpspi_slave_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ +} lpspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** +* Prototypes +***********************************************************************************************************************/ +/*! +* @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. +* This is not a public API. +*/ +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! +* @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. +* This is not a public API. +*/ +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*********************************************************************************************************************** +* Variables +***********************************************************************************************************************/ + +/*! @brief Pointers to lpspi edma handles for each instance. */ +static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; +static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; + +/*********************************************************************************************************************** +* Code +***********************************************************************************************************************/ +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData); + + switch (bytesEachRead) + { + case 1: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + } + else + { + *rxData = readData >> 24; + ++rxData; + } + break; + + case 2: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + } + else + { + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 24; + ++rxData; + } + break; + + case 4: + + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 24; + ++rxData; + + break; + + default: + assert(false); + break; + } +} + +void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + lpspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + assert(edmaRxRegToRxDataHandle); + assert(edmaTxDataToTxRegHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiMasterEdmaPrivateHandle[instance].base = base; + s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /*And since the dma transfer can not support 3 bytes .*/ + if ((bytesPerFrame % 4U) == 3) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + handle->state = kLPSPI_Busy; + + uint32_t instance = LPSPI_GetInstance(base); + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + uint8_t txWatermark = 0; + uint8_t rxWatermark = 0; + + /*Used for byte swap*/ + uint32_t dif = 0; + + uint8_t bytesLastWrite = 0; + + bool isThereExtraTxBytes = false; + + uint8_t dummyData = g_lpspiDummyData[instance]; + + edma_transfer_config_t transferConfigRx; + edma_transfer_config_t transferConfigTx; + + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + LPSPI_Enable(base, false); + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. + */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | + LPSPI_TCR_PCS(whichPcs); + + isThereExtraTxBytes = false; + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + + handle->bytesLastRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + + handle->bytesLastRead = 4; + + if ((transfer->dataSize % 4) != 0) + { + bytesLastWrite = transfer->dataSize % 4; + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + + --handle->writeRegRemainingTimes; + + --handle->readRegRemainingTimes; + handle->isThereExtraRxBytes = true; + } + } + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, + &s_lpspiMasterEdmaPrivateHandle[instance]); + + /*Rx*/ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ + handle->nbytes = transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + + /*Tx*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + } + + if (handle->isPcsContinuous) + { + handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); + + transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); + transferConfigTx.srcOffset = 0; + + transferConfigTx.destAddr = (uint32_t) & (base->TCR); + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); + } + + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else if (handle->isPcsContinuous) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + LPSPI_Enable(base, true); + + return kStatus_Success; +} + +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle); + assert(g_lpspiEdmaPrivateHandle); + + uint32_t readData; + + lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData) + { + LPSPI_SeparateEdmaReadData( + &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - + lpspiEdmaPrivateHandle->handle->bytesLastRead]), + readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) +{ + assert(handle); + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kLPSPI_Idle; +} + +status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + lpspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + assert(edmaRxRegToRxDataHandle); + assert(edmaTxDataToTxRegHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiSlaveEdmaPrivateHandle[instance].base = base; + s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /*And since the dma transfer can not support 3 bytes .*/ + if ((bytesPerFrame % 4U) == 3) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + handle->state = kLPSPI_Busy; + + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + uint8_t txWatermark = 0; + uint8_t rxWatermark = 0; + + /*Used for byte swap*/ + uint32_t dif = 0; + + uint8_t bytesLastWrite = 0; + + uint32_t instance = LPSPI_GetInstance(base); + + edma_transfer_config_t transferConfigRx; + edma_transfer_config_t transferConfigTx; + + bool isThereExtraTxBytes = false; + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + LPSPI_Enable(base, false); + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. + */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | + LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs); + + isThereExtraTxBytes = false; + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + + handle->bytesLastRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + + handle->bytesLastRead = 4; + + if ((transfer->dataSize % 4) != 0) + { + bytesLastWrite = transfer->dataSize % 4; + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + --handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = true; + --handle->readRegRemainingTimes; + } + } + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, + &s_lpspiSlaveEdmaPrivateHandle[instance]); + + /*Rx*/ + if (handle->readRegRemainingTimes > 0) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + } + + /*Tx*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + LPSPI_Enable(base, true); + + return kStatus_Success; +} + +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle); + assert(g_lpspiEdmaPrivateHandle); + + uint32_t readData; + + lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData) + { + LPSPI_SeparateEdmaReadData( + &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - + lpspiEdmaPrivateHandle->handle->bytesLastRead]), + readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) +{ + assert(handle); + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kLPSPI_Idle; +} + +status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi_edma.h new file mode 100644 index 0000000000..54b71bed43 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpspi_edma.h @@ -0,0 +1,328 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPSPI_EDMA_H_ +#define _FSL_LPSPI_EDMA_H_ + +#include "fsl_lpspi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpspi_edma_driver + * @{ + */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI EDMA driver version 2.0.2. */ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! +* @brief Forward declaration of the _lpspi_master_edma_handle typedefs. +*/ +typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; + +/*! +* @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. +*/ +typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ +struct _lpspi_master_edma_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ + volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + + uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (base->DATA & 0x7F); + } + else + { + data[i] = base->DATA; + } +#else + data[i] = base->DATA; +#endif + } +} + +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); + assert(config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + uint32_t temp; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4; osrTemp <= 32; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0) + { + sbrTemp = 1; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - config->baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + { + tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100) * 3)) + { + /* Unacceptable baud rate difference of more than 3%*/ + return kStatus_LPUART_BaudrateNotSupport; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPUART_GetInstance(base); + + /* Enable lpuart clock */ + CLOCK_EnableClock(s_lpuartClock[instance]); +#if defined(LPUART_PERIPH_CLOCKS) + CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3) && (osr < 8)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & + ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= + (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; + + return kStatus_Success; +} +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = LPUART_GetInstance(base); + + /* Disable lpuart clock */ + CLOCK_DisableClock(s_lpuartClock[instance]); + +#if defined(LPUART_PERIPH_CLOCKS) + CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 0; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +} + +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(baudRate_Bps); + + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4; osrTemp <= 32; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0) + { + sbrTemp = 1; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + { + tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < ((baudRate_Bps / 100) * 3)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3) && (osr < 8)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + + return kStatus_Success; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + return kStatus_LPUART_BaudrateNotSupport; + } +} + +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL |= mask; +} + +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL &= ~mask; +} + +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + uint32_t temp; + temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; +#endif + temp |= (base->CTRL & 0xFF0C000); + + return temp; +} + +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16; +#endif + return temp; +} + +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; +#endif + temp = (uint32_t)base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK)); + temp |= mask & LPUART_STAT_LBKDIF_MASK; +#endif + temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK)); + temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK)); + temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK); +#endif + base->STAT = temp; + /* If some flags still pending. */ + if (mask & LPUART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, + kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, + kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ + status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ + } + else + { + status = kStatus_Success; + } + + return status; +} + +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->STAT & LPUART_STAT_TDRE_MASK)) + { + } + base->DATA = *(data++); + } +} + +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + uint32_t statusFlag; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); +#endif + + while (length--) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (!(base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { + statusFlag = LPUART_GetStatusFlags(base); + + if (statusFlag & kLPUART_RxOverrunFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); + return kStatus_LPUART_RxHardwareOverrun; + } + + if (statusFlag & kLPUART_NoiseErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); + return kStatus_LPUART_NoiseError; + } + + if (statusFlag & kLPUART_FramingErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); + return kStatus_LPUART_FramingError; + } + + if (statusFlag & kLPUART_ParityErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); + return kStatus_LPUART_ParityError; + } + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(data++) = (base->DATA & 0x7F); + } + else + { + *(data++) = base->DATA; + } +#else + *(data++) = base->DATA; +#endif + } + + return kStatus_Success; +} + +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); +#endif + + /* Zero the handle. */ + memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = kLPUART_RxIdle; + handle->txState = kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr = LPUART_TransferHandleIRQ; + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + EnableIRQ(s_lpuartRxIRQ[instance]); + EnableIRQ(s_lpuartTxIRQ[instance]); +#else + EnableIRQ(s_lpuartIRQ[instance]); +#endif +} + +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle); + assert(ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); +} + +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kLPUART_RxIdle) + { + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if (kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kLPUART_TxBusy; + + /* Enable transmiter interrupt. */ + LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kLPUART_TxIdle; +} + +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(handle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable LPUART RX IRQ, protect ring buffer. */ + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kLPUART_RxBusy; + } + /* Enable LPUART RX IRQ if previously enabled. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kLPUART_RxBusy; + + /* Enable RX interrupt. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | + kLPUART_IdleLineInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | + kLPUART_IdleLineInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kLPUART_RxIdle; +} + +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + uint8_t count; + uint8_t tempCount; + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & base->STAT) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((count) && (handle->rxDataSize)) + { + tempCount = MIN(handle->rxDataSize, count); + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (!(handle->rxDataSize)) + { + handle->rxState = kLPUART_RxIdle; + + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT |= LPUART_STAT_IDLE_MASK; + + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (!(handle->rxDataSize)) + { + LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable); + } + /* If callback is not NULL and rxDataSize is not 0. */ + if ((handle->callback) && (handle->rxDataSize)) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + } + /* Receive data register full */ + if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kLPUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + +/* Read data. */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F); + } + else + { + handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; + } +#else + handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; +#endif + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kLPUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } + } + } +} + +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* To be implemented by User. */ +} +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void) +{ + if (CLOCK_isEnabledClock(s_lpuartClock[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL))) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + } + if (CLOCK_isEnabledClock(s_lpuartClock[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL))) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART0_LPUART1_TX_DriverIRQHandler(void) +{ + if (CLOCK_isEnabledClock(s_lpuartClock[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + } + if (CLOCK_isEnabledClock(s_lpuartClock[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART0_LPUART1_DriverIRQHandler(void) +{ + if (CLOCK_isEnabledClock(s_lpuartClock[0])) + { + if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) || + ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + } + if (CLOCK_isEnabledClock(s_lpuartClock[1])) + { + if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || + ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) || + ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART0_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART1_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART2_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART3_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART4_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART5_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART6_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART6_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART7_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART7_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART8_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART8_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart.h new file mode 100644 index 0000000000..395c27a68d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart.h @@ -0,0 +1,880 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version 2.2.5. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) +/*@}*/ + +/*! @brief Error codes for the LPUART driver. */ +enum _lpuart_status +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start conuting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char + detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/* @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || + ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); + + if (isSevenDataBits) + { + return (base->DATA & 0x7F); + } + else + { + return base->DATA; + } +#else + return base->DATA; +#endif +} + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room, and writes data to the transmitter buffer. + * + * @note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! +* @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @userData handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been written to the LPUART transmitter register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart_edma.c new file mode 100644 index 0000000000..add9488179 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart_edma.c @@ -0,0 +1,380 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpuart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" +#endif + +/*base, lpuartPrivateHandle->handle); + + if (lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint32_t instance = LPUART_GetInstance(base); + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kLPUART_RxIdle; + handle->txState = kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); + } +} + +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle); + assert(handle->txEdmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if (kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle); + assert(handle->rxEdmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if (kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(handle); + assert(handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = kLPUART_TxIdle; +} + +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(handle); + assert(handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = kLPUART_RxIdle; +} + +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->rxEdmaHandle); + assert(count); + + if (kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->txEdmaHandle); + assert(count); + + if (kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart_edma.h new file mode 100644 index 0000000000..a6f240147a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_lpuart_edma.h @@ -0,0 +1,199 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPUART_EDMA_H_ +#define _FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART EDMA driver version 2.2.5. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief LPUART eDMA handle +*/ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_EDMA_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pit.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pit.c new file mode 100644 index 0000000000..e6ff9c8745 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pit.c @@ -0,0 +1,138 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pit.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pit" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base PIT peripheral base address + * + * @return The PIT instance + */ +static uint32_t PIT_GetInstance(PIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PIT bases for each instance. */ +static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PIT clocks for each instance. */ +static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PIT_GetInstance(PIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++) + { + if (s_pitBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pitBases)); + + return instance; +} + +void PIT_Init(PIT_Type *base, const pit_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PIT clock*/ + CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS + /* Enable PIT timers */ + base->MCR &= ~PIT_MCR_MDIS_MASK; +#endif + /* Config timer operation when in debug mode */ + if (config->enableRunInDebug) + { + base->MCR &= ~PIT_MCR_FRZ_MASK; + } + else + { + base->MCR |= PIT_MCR_FRZ_MASK; + } +} + +void PIT_Deinit(PIT_Type *base) +{ +#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS + /* Disable PIT timers */ + base->MCR |= PIT_MCR_MDIS_MASK; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PIT clock*/ + CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) +{ + uint32_t valueH = 0U; + uint32_t valueL = 0U; + + /* LTMR64H should be read before LTMR64L */ + valueH = base->LTMR64H; + valueL = base->LTMR64L; + + return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); +} + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pit.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pit.h new file mode 100644 index 0000000000..55abdd5db8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pit.h @@ -0,0 +1,358 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PIT_H_ +#define _FSL_PIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pit + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of PIT channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pit_chnl +{ + kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ + kPIT_Chnl_1, /*!< PIT channel number 1 */ + kPIT_Chnl_2, /*!< PIT channel number 2 */ + kPIT_Chnl_3, /*!< PIT channel number 3 */ +} pit_chnl_t; + +/*! @brief List of PIT interrupts */ +typedef enum _pit_interrupt_enable +{ + kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ +} pit_interrupt_enable_t; + +/*! @brief List of PIT status flags */ +typedef enum _pit_status_flags +{ + kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ +} pit_status_flags_t; + +/*! + * @brief PIT configuration structure + * + * This structure holds the configuration settings for the PIT peripheral. To initialize this + * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _pit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ +} pit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. + * + * @note This API should be called at the beginning of the application using the PIT driver. + * + * @param base PIT peripheral base address + * @param config Pointer to the user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config); + +/*! + * @brief Gates the PIT clock and disables the PIT module. + * + * @param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base); + +/*! + * @brief Fills in the PIT configuration structure with the default settings. + * + * The default values are as follows. + * @code + * config->enableRunInDebug = false; + * @endcode + * @param config Pointer to the onfiguration structure. + */ +static inline void PIT_GetDefaultConfig(pit_config_t *config) +{ + assert(config); + + /* Timers are stopped in Debug mode */ + config->enableRunInDebug = false; +} + +#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE + +/*! + * @brief Enables or disables chaining a timer with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. Each timer is 32-bits, which allows the developers + * to chain timers together and form a longer timer (64-bits and larger). The first timer + * (timer 0) can't be chained to any other timer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number which is chained with the previous timer + * @param enable Enable or disable chain. + * true: Current timer is chained with the previous timer. + * false: Timer doesn't chain with other timers. + */ +static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; + } + else + { + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; + } +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL &= ~mask; +} + +/*! + * @brief Gets the enabled PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); +} + +/*! + * @brief Clears the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TFLG = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function until it reaches 0, + * then it generates an interrupt and load this register value again. + * Writing a new value to this register does not restart the timer. Instead, the value + * is loaded after the timer expires. + * + * @note Users can call the utility macros provided in fsl_common.h to convert to ticks. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + */ +static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) +{ + base->CHANNEL[channel].LDVAL = count; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, count down to 0 and + * then load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops every timer counting. Timers reload their periods + * respectively after the next time they call the PIT_DRV_StartTimer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * @param base PIT peripheral base address + * + * @return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PIT_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pmu.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pmu.c new file mode 100644 index 0000000000..717f5f8a69 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pmu.c @@ -0,0 +1,77 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_pmu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pmu" +#endif + + +uint32_t PMU_GetStatusFlags(PMU_Type *base) +{ + uint32_t ret = 0U; + + /* For 1P1. */ + if (PMU_REG_1P1_OK_VDD1P1_MASK == (PMU_REG_1P1_OK_VDD1P1_MASK & base->REG_1P1)) + { + ret |= kPMU_1P1RegulatorOutputOK; + } + if (PMU_REG_1P1_BO_VDD1P1_MASK == (PMU_REG_1P1_BO_VDD1P1_MASK & base->REG_1P1)) + { + ret |= kPMU_1P1BrownoutOnOutput; + } + + /* For 3P0. */ + if (PMU_REG_3P0_OK_VDD3P0_MASK == (PMU_REG_3P0_OK_VDD3P0_MASK & base->REG_3P0)) + { + ret |= kPMU_3P0RegulatorOutputOK; + } + if (PMU_REG_3P0_BO_VDD3P0_MASK == (PMU_REG_3P0_BO_VDD3P0_MASK & base->REG_3P0)) + { + ret |= kPMU_3P0BrownoutOnOutput; + } + + /* For 2P5. */ + if (PMU_REG_2P5_OK_VDD2P5_MASK == (PMU_REG_2P5_OK_VDD2P5_MASK & base->REG_2P5)) + { + ret |= kPMU_2P5RegulatorOutputOK; + } + if (PMU_REG_2P5_BO_VDD2P5_MASK == (PMU_REG_2P5_BO_VDD2P5_MASK & base->REG_2P5)) + { + ret |= kPMU_2P5BrownoutOnOutput; + } + + return ret; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pmu.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pmu.h new file mode 100644 index 0000000000..b7108941de --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pmu.h @@ -0,0 +1,690 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PMU_H_ +#define _FSL_PMU_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmu */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMU driver version */ +#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*@}*/ + +/*! + * @brief Status flags. + */ +enum _pmu_status_flags +{ + kPMU_1P1RegulatorOutputOK = (1U << 0U), /*!< Status bit that signals when the 1p1 regulator output + is ok. 1 = regulator output > brownout target. */ + kPMU_1P1BrownoutOnOutput = (1U << 1U), /*!< Status bit that signals when a 1p1 brownout is detected + on the regulator output. */ + kPMU_3P0RegulatorOutputOK = (1U << 2U), /*!< Status bit that signals when the 3p0 regulator output + is ok. 1 = regulator output > brownout target. */ + kPMU_3P0BrownoutOnOutput = (1U << 3U), /*!< Status bit that signals when a 3p0 brownout is detected + on the regulator output. */ + kPMU_2P5RegulatorOutputOK = (1U << 4U), /*!< Status bit that signals when the 2p5 regulator output + is ok. 1 = regulator output > brownout target. */ + kPMU_2P5BrownoutOnOutput = (1U << 5U), /*!< Status bit that signals when a 2p5 brownout is detected + on the regulator output. */ +}; + +/*! + * @brief The source for the reference voltage of the weak 1P1 regulator. + */ +typedef enum _pmu_1p1_weak_reference_source +{ + kPMU_1P1WeakReferenceSourceAlt0 = 0U, /*!< Weak-linreg output tracks low-power-bandgap voltage. */ + kPMU_1P1WeakReferenceSourceAlt1 = 1U, /*!< Weak-linreg output tracks VDD_SOC_CAP voltage. */ +} pmu_1p1_weak_reference_source_t; + +/*! + * @brief Input voltage source for LDO_3P0 from USB VBus. + */ +typedef enum _pmu_3p0_vbus_voltage_source +{ + kPMU_3P0VBusVoltageSourceAlt0 = 0U, /*!< USB_OTG1_VBUS - Utilize VBUS OTG1 for power. */ + kPMU_3P0VBusVoltageSourceAlt1 = 1U, /*!< USB_OTG2_VBUS - Utilize VBUS OTG2 for power. */ +} pmu_3p0_vbus_voltage_source_t; + +/*! + * @brief Regulator voltage ramp rate. + */ +typedef enum _pmu_core_reg_voltage_ramp_rate +{ + kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */ + kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */ + kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */ + kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */ +} pmu_core_reg_voltage_ramp_rate_t; + +#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL +/*! + * @brief Mask values of power gate. + */ +enum _pmu_power_gate +{ + kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */ + kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */ + kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */ + kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */ + kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */ +}; +#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ + +/*! + * @brief Bandgap select. + */ +typedef enum _pmu_power_bandgap +{ + kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */ + kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */ +} pmu_power_bandgap_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name Status. + * @{ + */ + +uint32_t PMU_GetStatusFlags(PMU_Type *base); + +/*@}*/ + +/*! + * @name 1P1 Regular + * @{ + */ + +/*! + * @brief Selects the source for the reference voltage of the weak 1P1 regulator. + * + * @param base PMU peripheral base address. + * @param option The option for reference voltage source, see to #pmu_1p1_weak_reference_source_t. + */ +static inline void PMU_1P1SetWeakReferenceSource(PMU_Type *base, pmu_1p1_weak_reference_source_t option) +{ + base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) | PMU_REG_1P1_SELREF_WEAK_LINREG(option); +} + +/*! + * @brief Enables the weak 1P1 regulator. + * + * This regulator can be used when the main 1P1 regulator is disabled, under low-power conditions. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableWeakRegulator(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; + } +} + +/*! + * @brief Adjust the 1P1 regulator output voltage. + * + * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages + * may be interpolated from these examples. Choices must be in this range: + * - 0x1b(1.375V) >= output_trg >= 0x04(0.8V) + * - 0x04 : 0.8V + * - 0x10 : 1.1V (typical) + * - 0x1b : 1.375V + * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range. + * + * @param base PMU peripheral base address. + * @param value Setting value for the output. + */ +static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value); +} + +/*! + * @brief Adjust the 1P1 regulator brownout offset voltage. + * + * Control bits to adjust the regulator brownout offset voltage in 25mV steps. The reset + * brown-offset is 175mV below the programmed target code. + * Brownout target = OUTPUT_TRG - BO_OFFSET. + * Some steps may be irrelevant because of input supply limitations or load operation. + * + * @param base PMU peripheral base address. + * @param value Setting value for the brownout offset. The available range is in 3-bit. + */ +static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value); +} + +/*! + * @brief Enable the pull-down circuitry in the regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnablePullDown(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_PULLDOWN_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_PULLDOWN_MASK; + } +} + +/*! + * @brief Enable the current-limit circuitry in the regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableCurrentLimit(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK; + } +} + +/*! + * @brief Enable the brownout circuitry in the regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableBrownout(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_BO_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_BO_MASK; + } +} + +/*! + * @brief Enable the regulator output. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableOutput(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_LINREG_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK; + } +} + +/*@}*/ + +/*! + * @name 3P0 Regular + * @{ + */ + +/*! + * @brief Adjust the 3P0 regulator output voltage. + * + * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages + * may be interpolated from these examples. Choices must be in this range: + * - 0x00(2.625V) >= output_trg >= 0x1f(3.4V) + * - 0x00 : 2.625V + * - 0x0f : 3.0V (typical) + * - 0x1f : 3.4V + * + * @param base PMU peripheral base address. + * @param value Setting value for the output. + */ +static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value); +} + +/*! + * @brief Select input voltage source for LDO_3P0. + * + * Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS. If only + * one of the two VBUS voltages is present, it is automatically selected. + * + * @param base PMU peripheral base address. + * @param option User-defined input voltage source for LDO_3P0. + */ +static inline void PMU_3P0SetVBusVoltageSource(PMU_Type *base, pmu_3p0_vbus_voltage_source_t option) +{ + base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option); +} + +/*! + * @brief Adjust the 3P0 regulator brownout offset voltage. + * + * Control bits to adjust the 3P0 regulator brownout offset voltage in 25mV steps. The reset + * brown-offset is 175mV below the programmed target code. + * Brownout target = OUTPUT_TRG - BO_OFFSET. + * Some steps may be irrelevant because of input supply limitations or load operation. + * + * @param base PMU peripheral base address. + * @param value Setting value for the brownout offset. The available range is in 3-bit. + */ +static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value); +} + +/*! + * @brief Enable the current-limit circuitry in the 3P0 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_3P0EnableCurrentLimit(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK; + } + else + { + base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK; + } +} + +/*! + * @brief Enable the brownout circuitry in the 3P0 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_3P0EnableBrownout(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK; + } + else + { + base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK; + } +} + +/*! + * @brief Enable the 3P0 regulator output. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_3P0EnableOutput(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK; + } + else + { + base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK; + } +} + +/* @} */ + +/*! + * @name 2P5 Regulator + * @{ + */ + +/*! + * @brief Enables the weak 2P5 regulator. + * + * This low power regulator is used when the main 2P5 regulator is disabled + * to keep the 2.5V output roughly at 2.5V. Scales directly with the value of VDDHIGH_IN. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnableWeakRegulator(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; + } +} + +/*! + * @brief Adjust the 1P1 regulator output voltage. + * + * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages + * may be interpolated from these examples. Choices must be in this range: + * - 0x00(2.1V) >= output_trg >= 0x1f(2.875V) + * - 0x00 : 2.1V + * - 0x10 : 2.5V (typical) + * - 0x1f : 2.875V + * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range. + * + * @param base PMU peripheral base address. + * @param value Setting value for the output. + */ +static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value); +} + +/*! + * @brief Adjust the 2P5 regulator brownout offset voltage. + * + * Adjust the regulator brownout offset voltage in 25mV steps. The reset + * brown-offset is 175mV below the programmed target code. + * Brownout target = OUTPUT_TRG - BO_OFFSET. + * Some steps may be irrelevant because of input supply limitations or load operation. + * + * @param base PMU peripheral base address. + * @param value Setting value for the brownout offset. The available range is in 3-bit. + */ +static inline void PMU_2P5SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value); +} + +/*! + * @brief Enable the pull-down circuitry in the 2P5 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnablePullDown(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } +} + +/*! + * @brief Enable the pull-down circuitry in the 2P5 regulator. + * @deprecated Do not use this function. It has been superceded by @ref PMU_2P5EnablePullDown. + */ +static inline void PMU_2P1EnablePullDown(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } +} + +/*! + * @brief Enable the current-limit circuitry in the 2P5 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnableCurrentLimit(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK; + } +} + +/*! + * @brief Enable the brownout circuitry in the 2P5 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5nableBrownout(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_BO_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_BO_MASK; + } +} + +/*! + * @brief Enable the 2P5 regulator output. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnableOutput(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_LINREG_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK; + } +} + +/* @} */ + +/*! + * @name Core Regulator + * @{ + */ + +/*! + * @brief Increase the gate drive on power gating FETs. + * + * If set, increases the gate drive on power gating FETs to reduce leakage in the off state. + * Care must be taken to apply this bit only when the input supply voltage to the power FET + * is less than 1.1V. + * NOTE: This bit should only be used in low-power modes where the external input supply voltage + * is nominally 0.9V. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_CoreEnableIncreaseGateDrive(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_CORE |= PMU_REG_CORE_FET_ODRIVE_MASK; + } + else + { + base->REG_CORE &= ~PMU_REG_CORE_FET_ODRIVE_MASK; + } +} + +/*! + * @brief Set the CORE regulator voltage ramp rate. + * + * @param base PMU peripheral base address. + * @param option User-defined option for voltage ramp rate, see to #pmu_core_reg_voltage_ramp_rate_t. + */ +static inline void PMU_CoreSetRegulatorVoltageRampRate(PMU_Type *base, pmu_core_reg_voltage_ramp_rate_t option) +{ + base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_RAMP_RATE_MASK) | PMU_REG_CORE_RAMP_RATE(option); +} + +/*! + * @brief Define the target voltage for the SOC power domain. + * + * Define the target voltage for the SOC power domain. Single-bit increments reflect 25mV core + * voltage steps. Some steps may not be relevant because of input supply limitations or load operation. + * - 0x00 : Power gated off. + * - 0x01 : Target core voltage = 0.725V + * - 0x02 : Target core voltage = 0.750V + * - ... + * - 0x10 : Target core voltage = 1.100V + * - ... + * - 0x1e : Target core voltage = 1.450V + * - 0x1F : Power FET switched full on. No regulation. + * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the + * datasheet Operating Ranges table for the allowed voltages. + * + * @param base PMU peripheral base address. + * @param value Setting value for target voltage. 5-bit available + */ +static inline void PMU_CoreSetSOCDomainVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG2_TARG_MASK) | PMU_REG_CORE_REG2_TARG(value); +} + +/*! + * @brief Define the target voltage for the ARM Core power domain. + * + * Define the target voltage for the ARM Core power domain. Single-bit increments reflect 25mV core + * voltage steps. Some steps may not be relevant because of input supply limitations or load operation. + * - 0x00 : Power gated off. + * - 0x01 : Target core voltage = 0.725V + * - 0x02 : Target core voltage = 0.750V + * - ... + * - 0x10 : Target core voltage = 1.100V + * - ... + * - 0x1e : Target core voltage = 1.450V + * - 0x1F : Power FET switched full on. No regulation. + * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the + * datasheet Operating Ranges table for the allowed voltages. + * + * @param base PMU peripheral base address. + * @param value Setting value for target voltage. 5-bit available + */ +static inline void PMU_CoreSetARMCoreDomainVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG0_TARG_MASK) | PMU_REG_CORE_REG0_TARG(value); +} + +/* @} */ + +#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL +/*! + * @name Power Gate Controller & other + * @{ + */ + +/*! + * @brief Gate the power to modules. + * + * @param base PMU peripheral base address. + * @param gates Mask value for the module to be gated. See to #_pmu_power_gate. + */ +static inline void PMU_GatePower(PMU_Type *base, uint32_t gates) +{ + base->LOWPWR_CTRL_SET = gates; +} + +/*! + * @brief Ungate the power to modules. + * + * @param base PMU peripheral base address. + * @param gates Mask value for the module to be gated. See to #_pmu_power_gate. + */ +static inline void PMU_UngatePower(PMU_Type *base, uint32_t gates) +{ + base->LOWPWR_CTRL_CLR = gates; +} + +/*! + * @brief Enable the low power bandgap. + * + * @param base PMU peripheral base address. + * @param enable Enable the low power bandgap or use the normal power bandgap. + * @ + */ +static inline void PMU_EnableLowPowerBandgap(PMU_Type *base, bool enable) +{ + if (enable) + { + base->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the low power bandgap. */ + } + else + { + base->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the normal power bandgap. */ + } +} +#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMU_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pwm.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pwm.c new file mode 100644 index 0000000000..a244750f80 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pwm.c @@ -0,0 +1,693 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pwm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pwm" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t PWM_GetInstance(PWM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PWM clocks for each PWM submodule. */ +static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PWM_GetInstance(PWM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pwmBases)); + + return instance; +} + +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) +{ + assert(config); + + uint16_t reg; + + /* Source clock for submodule 0 cannot be itself */ + if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + + /* Reload source select clock for submodule 0 cannot be master reload */ + if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PWM submodule clock*/ + CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Clear the fault status flags */ + base->FSTS |= PWM_FSTS_FFLAG_MASK; + + reg = base->SM[subModule].CTRL2; + + /* Setup the submodule clock-source, control source of the INIT signal, + * source of the force output signal, operation in debug & wait modes and reload source select + */ + reg &= ~(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL2_INDEP_MASK | + PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); + reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | + PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | + PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); + + /* Setup PWM A & B to be independent or a complementary-pair */ + switch (config->pairOperation) + { + case kPWM_Independent: + reg |= PWM_CTRL2_INDEP_MASK; + break; + case kPWM_ComplementaryPwmA: + base->MCTRL &= ~(1U << (PWM_MCTRL_IPOL_SHIFT + subModule)); + break; + case kPWM_ComplementaryPwmB: + base->MCTRL |= (1U << (PWM_MCTRL_IPOL_SHIFT + subModule)); + break; + default: + break; + } + base->SM[subModule].CTRL2 = reg; + + reg = base->SM[subModule].CTRL; + + /* Setup the clock prescale, load mode and frequency */ + reg &= ~(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); + reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); + + /* Setup register reload logic */ + switch (config->reloadLogic) + { + case kPWM_ReloadImmediate: + reg |= PWM_CTRL_LDMOD_MASK; + break; + case kPWM_ReloadPwmHalfCycle: + reg |= PWM_CTRL_HALF_MASK; + reg &= ~PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmFullCycle: + reg &= ~PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmHalfAndFullCycle: + reg |= PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + default: + break; + } + base->SM[subModule].CTRL = reg; + + /* Setup the fault filter */ + if (base->FFILT & PWM_FFILT_FILT_PER_MASK) + { + /* When changing values for fault period from a non-zero value, first write a value of 0 + * to clear the filter + */ + base->FFILT &= ~(PWM_FFILT_FILT_PER_MASK); + } + + base->FFILT = (PWM_FFILT_FILT_CNT(config->faultFilterCount) | PWM_FFILT_FILT_PER(config->faultFilterPeriod)); + + /* Issue a Force trigger event when configured to trigger locally */ + if (config->forceTrigger == kPWM_Force_Local) + { + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); + } + + return kStatus_Success; +} + +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) +{ + /* Stop the submodule */ + base->MCTRL &= ~(1U << (PWM_MCTRL_RUN_SHIFT + subModule)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM submodule clock*/ + CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void PWM_GetDefaultConfig(pwm_config_t *config) +{ + assert(config); + + /* PWM is paused in debug mode */ + config->enableDebugMode = false; + /* PWM is paused in wait mode */ + config->enableWait = false; + /* PWM module uses the local reload signal to reload registers */ + config->reloadSelect = kPWM_LocalReload; + /* Fault filter count is set to 0 */ + config->faultFilterCount = 0; + /* Fault filter period is set to 0 which disables the fault filter */ + config->faultFilterPeriod = 0; + /* Use the IP Bus clock as source clock for the PWM submodule */ + config->clockSource = kPWM_BusClock; + /* Clock source prescale is set to divide by 1*/ + config->prescale = kPWM_Prescale_Divide_1; + /* Local sync causes initialization */ + config->initializationControl = kPWM_Initialize_LocalSync; + /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + config->forceTrigger = kPWM_Force_Local; + /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. + * This field is not used in Immediate reload mode + */ + config->reloadFrequency = kPWM_LoadEveryOportunity; + /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ + config->reloadLogic = kPWM_ReloadImmediate; + /* PWM A & PWM B operate as 2 independent channels */ + config->pairOperation = kPWM_Independent; +} + +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(pwmFreq_Hz); + assert(numOfChnls); + assert(srcClock_Hz); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + int16_t modulo = 0; + uint8_t i, polarityShift = 0, outputEnableShift = 0; + + if (numOfChnls > 2) + { + /* Each submodule has 2 signals; PWM A & PWM B */ + return kStatus_Fail; + } + + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (pwmClock / pwmFreq_Hz); + + /* Setup each PWM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100; + + /* Setup the different match registers to generate the PWM signal */ + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + modulo = pulseCnt >> 1; + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = (-modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = modulo; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL3 = (pwmHighPulse / 2); + } + else + { + base->SM[subModule].VAL4 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL5 = (pwmHighPulse / 2); + } + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2); + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = pulseCnt; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2); + } + else + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2); + } + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + modulo = pulseCnt >> 1; + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = (-modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = modulo; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-modulo); + base->SM[subModule].VAL3 = (-modulo + pwmHighPulse); + } + else + { + base->SM[subModule].VAL4 = (-modulo); + base->SM[subModule].VAL5 = (-modulo + pwmHighPulse); + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2); + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = pulseCnt; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + break; + default: + break; + } + /* Setup register shift values based on the channel being configured. + * Also setup the deadtime value + */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + polarityShift = PWM_OCTRL_POLA_SHIFT; + outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; + base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); + } + else + { + polarityShift = PWM_OCTRL_POLB_SHIFT; + outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; + base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); + } + + /* Setup signal active level */ + if (chnlParams->level == kPWM_HighTrue) + { + base->SM[subModule].OCTRL &= ~(1U << polarityShift); + } + else + { + base->SM[subModule].OCTRL |= (1U << polarityShift); + } + /* Enable PWM output */ + base->OUTEN |= (1U << (outputEnableShift + subModule)); + + /* Get the next channel parameters */ + chnlParams++; + } + + return kStatus_Success; +} + +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent) +{ + assert(dutyCyclePercent <= 100); + assert(pwmSignal < 2); + uint16_t pulseCnt = 0, pwmHighPulse = 0; + int16_t modulo = 0; + + switch (currPwmMode) + { + case kPWM_SignedCenterAligned: + modulo = base->SM[subModule].VAL1; + pulseCnt = modulo * 2; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL3 = (pwmHighPulse / 2); + } + else + { + base->SM[subModule].VAL4 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL5 = (pwmHighPulse / 2); + } + break; + case kPWM_CenterAligned: + pulseCnt = base->SM[subModule].VAL1; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2); + } + else + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2); + } + break; + case kPWM_SignedEdgeAligned: + modulo = base->SM[subModule].VAL1; + pulseCnt = modulo * 2; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-modulo); + base->SM[subModule].VAL3 = (-modulo + pwmHighPulse); + } + else + { + base->SM[subModule].VAL4 = (-modulo); + base->SM[subModule].VAL5 = (-modulo + pwmHighPulse); + } + break; + case kPWM_EdgeAligned: + pulseCnt = base->SM[subModule].VAL1; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + break; + default: + break; + } +} + +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams) +{ + uint32_t reg = 0; + switch (pwmChannel) + { + case kPWM_PwmA: + /* Setup the capture paramters for PWM A pin */ + reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | + PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLA_ARMA_MASK; + + base->SM[subModule].CAPTCTRLA = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); + /* Setup PWM A pin for input capture */ + base->OUTEN &= ~(1U << (PWM_OUTEN_PWMA_EN_SHIFT + subModule)); + + break; + case kPWM_PwmB: + /* Setup the capture paramters for PWM B pin */ + reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | + PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLB_ARMB_MASK; + + base->SM[subModule].CAPTCTRLB = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); + /* Setup PWM B pin for input capture */ + base->OUTEN &= ~(1U << (PWM_OUTEN_PWMB_EN_SHIFT + subModule)); + break; + case kPWM_PwmX: + reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | + PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLX_ARMX_MASK; + + base->SM[subModule].CAPTCTRLX = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); + /* Setup PWM X pin for input capture */ + base->OUTEN &= ~(1U << (PWM_OUTEN_PWMX_EN_SHIFT + subModule)); + break; + default: + break; + } +} + +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) +{ + assert(faultParams); + uint16_t reg; + + reg = base->FCTRL; + /* Set the faults level-settting */ + if (faultParams->faultLevel) + { + reg |= (1U << (PWM_FCTRL_FLVL_SHIFT + faultNum)); + } + else + { + reg &= ~(1U << (PWM_FCTRL_FLVL_SHIFT + faultNum)); + } + /* Set the fault clearing mode */ + if (faultParams->faultClearingMode) + { + /* Use manual fault clearing */ + reg &= ~(1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum)); + if (faultParams->faultClearingMode == kPWM_ManualSafety) + { + /* Use manual fault clearing with safety mode enabled */ + reg |= (1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum)); + } + else + { + /* Use manual fault clearing with safety mode disabled */ + reg &= ~(1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum)); + } + } + else + { + /* Use automatic fault clearing */ + reg |= (1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum)); + } + base->FCTRL = reg; + + /* Set the combinational path option */ + if (faultParams->enableCombinationalPath) + { + /* Combinational path from the fault input to the PWM output is available */ + base->FCTRL2 &= ~(1U << faultNum); + } + else + { + /* No combinational path available, only fault filter & latch signal can disable PWM output */ + base->FCTRL2 |= (1U << faultNum); + } + + /* Initially clear both recovery modes */ + reg = base->FSTS; + reg &= ~((1U << (PWM_FSTS_FFULL_SHIFT + faultNum)) | (1U << (PWM_FSTS_FHALF_SHIFT + faultNum))); + /* Setup fault recovery */ + switch (faultParams->recoverMode) + { + case kPWM_NoRecovery: + break; + case kPWM_RecoverHalfCycle: + reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)); + break; + case kPWM_RecoverFullCycle: + reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum)); + break; + case kPWM_RecoverHalfAndFullCycle: + reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)); + reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum)); + break; + default: + break; + } + base->FSTS = reg; +} + +void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) + +{ + uint16_t shift; + uint16_t reg; + + /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ + shift = subModule * 4 + pwmChannel * 2; + + /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ + reg = base->DTSRCSEL; + reg &= ~(0x3U << shift); + reg |= (uint16_t)((uint16_t)mode << shift); + base->DTSRCSEL = reg; +} + +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + /* Upper 16 bits are for related to the submodule */ + base->SM[subModule].INTEN |= (mask & 0xFFFFU); + /* Fault related interrupts */ + base->FCTRL |= ((mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + base->SM[subModule].INTEN &= ~(mask & 0xFFFF); + base->FCTRL &= ~((mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t enabledInterrupts; + + enabledInterrupts = base->SM[subModule].INTEN; + enabledInterrupts |= ((uint32_t)(base->FCTRL & PWM_FCTRL_FIE_MASK) << 16U); + return enabledInterrupts; +} + +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t statusFlags; + + statusFlags = base->SM[subModule].STS; + statusFlags |= ((uint32_t)(base->FSTS & PWM_FSTS_FFLAG_MASK) << 16U); + + return statusFlags; +} + +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + uint16_t reg; + + base->SM[subModule].STS = (mask & 0xFFFFU); + reg = base->FSTS; + /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared + * by writing a login one + */ + reg &= ~(PWM_FSTS_FFLAG_MASK); + reg |= ((mask >> 16U) & PWM_FSTS_FFLAG_MASK); + base->FSTS = reg; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pwm.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pwm.h new file mode 100644 index 0000000000..26619202d9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pwm.h @@ -0,0 +1,696 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PWM_H_ +#define _FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! Number of bits per submodule for software output control */ +#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 + +/*! @brief List of PWM submodules */ +typedef enum _pwm_submodule +{ + kPWM_Module_0 = 0U, /*!< Submodule 0 */ + kPWM_Module_1, /*!< Submodule 1 */ + kPWM_Module_2, /*!< Submodule 2 */ + kPWM_Module_3 /*!< Submodule 3 */ +} pwm_submodule_t; + +/*! @brief List of PWM channels in each module */ +typedef enum _pwm_channels +{ + kPWM_PwmB = 0U, + kPWM_PwmA, + kPWM_PwmX +} pwm_channels_t; + +/*! @brief List of PWM value registers */ +typedef enum _pwm_value_register +{ + kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ + kPWM_ValueRegister_1, /*!< PWM Value1 register */ + kPWM_ValueRegister_2, /*!< PWM Value2 register */ + kPWM_ValueRegister_3, /*!< PWM Value3 register */ + kPWM_ValueRegister_4, /*!< PWM Value4 register */ + kPWM_ValueRegister_5 /*!< PWM Value5 register */ +} pwm_value_register_t; + +/*! @brief PWM clock source selection.*/ +typedef enum _pwm_clock_source +{ + kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ + kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ + kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ +} pwm_clock_source_t; + +/*! @brief PWM prescaler factor selection for clock source*/ +typedef enum _pwm_clock_prescale +{ + kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ + kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ + kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ + kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ + kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ + kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ + kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ + kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ +} pwm_clock_prescale_t; + +/*! @brief Options that can trigger a PWM FORCE_OUT */ +typedef enum _pwm_force_output_trigger +{ + kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ + kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to + the state of LDOK */ + kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ + kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ + kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ + kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ + kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ +} pwm_force_output_trigger_t; + +/*! @brief PWM counter initialization options */ +typedef enum _pwm_init_source +{ + kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ + kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ + kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ + kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ +} pwm_init_source_t; + +/*! @brief PWM load frequency selection */ +typedef enum _pwm_load_frequency +{ + kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ + kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ + kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ + kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ + kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ + kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ + kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ + kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ + kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ + kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ + kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ + kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ + kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ + kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ + kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ + kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ +} pwm_load_frequency_t; + +/*! @brief List of PWM fault selections */ +typedef enum _pwm_fault_input +{ + kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ + kPWM_Fault_1, /*!< Fault 1 input pin */ + kPWM_Fault_2, /*!< Fault 2 input pin */ + kPWM_Fault_3 /*!< Fault 3 input pin */ +} pwm_fault_input_t; + +/*! @brief PWM capture edge select */ +typedef enum _pwm_input_capture_edge +{ + kPWM_Disable = 0U, /*!< Disabled */ + kPWM_FallingEdge, /*!< Capture on falling edge only */ + kPWM_RisingEdge, /*!< Capture on rising edge only */ + kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ +} pwm_input_capture_edge_t; + +/*! @brief PWM output options when a FORCE_OUT signal is asserted */ +typedef enum _pwm_force_signal +{ + kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ + kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ + kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ + kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ +} pwm_force_signal_t; + +/*! @brief Options available for the PWM A & B pair operation */ +typedef enum _pwm_chnl_pair_operation +{ + kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ + kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ + kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ +} pwm_chnl_pair_operation_t; + +/*! @brief Options available on how to load the buffered-registers with new values */ +typedef enum _pwm_register_reload +{ + kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ + kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ + kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ + kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ +} pwm_register_reload_t; + +/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ +typedef enum _pwm_fault_recovery_mode +{ + kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ + kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ + kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ + kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ +} pwm_fault_recovery_mode_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ + kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ + kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ + kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ + kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ + kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ + kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ + kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ + kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ + kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ + kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ + kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ + kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ + kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ + kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ + kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ + kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ + kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ + kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ + kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ + kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ + kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ + kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ + kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ + kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ + kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ + kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ + kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ + kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ + kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ + kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ + kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ + kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ + kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ + kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ + kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ +} pwm_status_flags_t; + +/*! @brief PWM operation mode */ +typedef enum _pwm_mode +{ + kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ + kPWM_CenterAligned, /*!< Unsigned cente-aligned */ + kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ + kPWM_EdgeAligned /*!< Unsigned edge-aligned */ +} pwm_mode_t; + +/*! @brief PWM output pulse mode, high-true or low-true */ +typedef enum _pwm_level_select +{ + kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ + kPWM_LowTrue /*!< Low level represents "on" or "active" state */ +} pwm_level_select_t; + +/*! @brief PWM reload source select */ +typedef enum _pwm_reload_source_select +{ + kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ + kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ +} pwm_reload_source_select_t; + +/*! @brief PWM fault clearing options */ +typedef enum _pwm_fault_clear +{ + kPWM_Automatic = 0U, /*!< Automatic fault clearing */ + kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ + kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ +} pwm_fault_clear_t; + +/*! @brief Options for submodule master control operation */ +typedef enum _pwm_module_control +{ + kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ + kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ + kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ + kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ +} pwm_module_control_t; + +/*! @brief Structure for the user to define the PWM signal characteristics */ +typedef struct _pwm_signal_param +{ + pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ + pwm_level_select_t level; /*!< PWM output active level select */ + uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ +} pwm_signal_param_t; + +/*! + * @brief PWM config structure + * + * This structure holds the configuration settings for the PWM peripheral. To initialize this + * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pwm_config +{ + bool enableDebugMode; /*!< true: PWM continues to run in debug mode; + false: PWM is paused in debug mode */ + bool enableWait; /*!< true: PWM continues to run in WAIT mode; + false: PWM is paused in WAIT mode */ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ + pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ + pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ + pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ + pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice + is not immediate reload */ + pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ +} pwm_config_t; + +/*! @brief Structure is used to hold the parameters to configure a PWM fault */ +typedef struct _pwm_fault_param +{ + pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ + bool faultLevel; /*!< true: Logic 1 indicates fault; + false: Logic 0 indicates fault */ + bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; + false: No combination path is available */ + pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ +} pwm_fault_param_t; + +/*! + * @brief Structure is used to hold parameters to configure the capture capability of a signal pin + */ +typedef struct _pwm_input_capture_param +{ + bool captureInputSel; /*!< true: Use the edge counter signal as source + false: Use the raw input signal from the pin as source */ + uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ + pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ + pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ + bool enableOneShotCapture; /*!< true: Use one-shot capture mode; + false: Use free-running capture mode */ + uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in + the status register will set if the word count in the FIFO + is greater than this watermark level */ +} pwm_input_capture_param_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name Module PWM output + * @{ + */ +/*! + * @brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM main counter clock in Hz. + * + * @return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel in the submodule to setup + * @param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams); + +/*! + * @brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * @param base PWM peripheral base address + * @param faultNum PWM fault to configure. + * @param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); + +/*! + * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_force_signal_t mode); + +/*! + * @name Interrupts Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Disables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Gets the enabled PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Clears the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the PWM counter for a single or multiple submodules. + * + * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) +{ + base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); +} + +/*! + * @brief Stops the PWM counter for a single or multiple submodules. + * + * Clears the Run bit which resets the submodule's counter. This function can stop multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) +{ + base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); +} + +/*! @}*/ + +/*! + * @brief Enables or disables the PWM output trigger. + * + * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 + * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated + * when the counter matches VAL 1, VAL 3, or VAL 5 register. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister Value register that will activate the trigger + * @param activate true: Enable the trigger; false: Disable the trigger + */ +static inline void PWM_OutputTriggerEnable(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + bool activate) +{ + if (activate) + { + base->SM[subModule].TCTRL |= (1U << valueRegister); + } + else + { + base->SM[subModule].TCTRL &= ~(1U << valueRegister); + } +} + +/*! + * @brief Sets the software control output for a pin to high or low. + * + * The user specifies which channel to modify by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param value true: Supply a logic 1, false: Supply a logic 0. + */ +static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) +{ + if (value) + { + base->SWCOUT |= (1U << ((subModule * PWM_SUBMODULE_SWCONTROL_WIDTH) + pwmChannel)); + } + else + { + base->SWCOUT &= ~(1U << ((subModule * PWM_SUBMODULE_SWCONTROL_WIDTH) + pwmChannel)); + } +} + +/*! + * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules + * + * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The + * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the + * values are loaded at the next PWM reload point. + * This function can issue the load command to multiple submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of + * members of the enumeration ::pwm_module_control_t + * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit + */ +static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) +{ + if (value) + { + base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); + } + else + { + base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PWM_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pxp.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pxp.c new file mode 100644 index 0000000000..4bc424c967 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pxp.c @@ -0,0 +1,533 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pxp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pxp" +#endif + +/* The CSC2 coefficient is ###.####_#### */ +#define PXP_CSC2_COEF_INT_WIDTH 2 +#define PXP_CSC2_COEF_FRAC_WIDTH 8 + +/* Compatibility map macro. */ +#if defined(PXP_PS_CLRKEYLOW_0_PIXEL_MASK) && (!defined(PXP_PS_CLRKEYLOW_PIXEL_MASK)) +#define PS_CLRKEYLOW PS_CLRKEYLOW_0 +#define PS_CLRKEYHIGH PS_CLRKEYHIGH_0 +#endif +#if defined(PXP_AS_CLRKEYLOW_0_PIXEL_MASK) && (!defined(PXP_AS_CLRKEYLOW_PIXEL_MASK)) +#define AS_CLRKEYLOW AS_CLRKEYLOW_0 +#define AS_CLRKEYHIGH AS_CLRKEYHIGH_0 +#endif + +typedef union _u32_f32 +{ + float f32; + uint32_t u32; +} u32_f32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PXP peripheral base address + * + * @return The PXP module instance + */ +static uint32_t PXP_GetInstance(PXP_Type *base); + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) +/*! + * @brief Convert IEEE 754 float value to the value could be written to registers. + * + * This function converts the float value to integer value to set the scaler + * and CSC parameters. + * + * This function is an alternative implemention of the following code with no + * MISRA 2004 rule 10.4 error: + * + * @code + return (uint32_t)(floatValue * (float)(1 << fracBits)); + @endcode + * + * @param floatValue The float value to convert. + * @param intBits Bits number of integer part in result. + * @param fracBits Bits number of fractional part in result. + * @return The value to set to register. + */ +static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits); +#endif + +/*! + * @brief Convert the desired scale fact to DEC and PS_SCALE. + * + * @param inputDimension Input dimension. + * @param outputDimension Output dimension. + * @param dec The decimation filter contr0l value. + * @param scale The scale value set to register PS_SCALE. + */ +static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension, uint8_t *dec, uint32_t *scale); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PXP bases for each instance. */ +static PXP_Type *const s_pxpBases[] = PXP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PXP clocks for each PXP submodule. */ +static const clock_ip_name_t s_pxpClocks[] = PXP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PXP_GetInstance(PXP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pxpBases); instance++) + { + if (s_pxpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pxpBases)); + + return instance; +} + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) +static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits) +{ + /* One bit reserved for sign bit. */ + assert(intBits + fracBits < 32); + + u32_f32_t u32_f32; + uint32_t ret; + + u32_f32.f32 = floatValue; + uint32_t floatBits = u32_f32.u32; + int32_t expValue = (int32_t)((floatBits & 0x7F800000U) >> 23U) - 127; + + ret = (floatBits & 0x007FFFFFU) | 0x00800000U; + expValue += fracBits; + + if (expValue < 0) + { + return 0U; + } + else if (expValue > 23) + { + /* should not exceed 31-bit when left shift. */ + assert((expValue - 23) <= 7); + ret <<= (expValue - 23); + } + else + { + ret >>= (23 - expValue); + } + + /* Set the sign bit. */ + if (floatBits & 0x80000000U) + { + ret = ((~ret) + 1U) & ~(((uint32_t)-1) << (intBits + fracBits + 1)); + } + + return ret; +} +#endif + +static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension, uint8_t *dec, uint32_t *scale) +{ + uint32_t scaleFact = ((uint32_t)inputDimension << 12U) / outputDimension; + + if (scaleFact >= (16U << 12U)) + { + /* Desired fact is two large, use the largest support value. */ + *dec = 3U; + *scale = 0x2000U; + } + else + { + if (scaleFact > (8U << 12U)) + { + *dec = 3U; + } + else if (scaleFact > (4U << 12U)) + { + *dec = 2U; + } + else if (scaleFact > (2U << 12U)) + { + *dec = 1U; + } + else + { + *dec = 0U; + } + + *scale = scaleFact >> (*dec); + + if (0U == *scale) + { + *scale = 1U; + } + } +} + +void PXP_Init(PXP_Type *base) +{ + uint32_t ctrl = 0U; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = PXP_GetInstance(base); + CLOCK_EnableClock(s_pxpClocks[instance]); +#endif + + PXP_Reset(base); + +/* Enable the process engine in primary processing flow. */ +#if defined(PXP_CTRL_ENABLE_ROTATE0_MASK) + ctrl |= PXP_CTRL_ENABLE_ROTATE0_MASK; +#endif +#if defined(PXP_CTRL_ENABLE_ROTATE1_MASK) + ctrl |= PXP_CTRL_ENABLE_ROTATE1_MASK; +#endif +#if defined(PXP_CTRL_ENABLE_CSC2_MASK) + ctrl |= PXP_CTRL_ENABLE_CSC2_MASK; +#endif +#if defined(PXP_CTRL_ENABLE_LUT_MASK) + ctrl |= PXP_CTRL_ENABLE_LUT_MASK; +#endif +#if defined(PXP_CTRL_ENABLE_PS_AS_OUT_MASK) + ctrl |= PXP_CTRL_ENABLE_PS_AS_OUT_MASK; +#endif + + base->CTRL = ctrl; +} + +void PXP_Deinit(PXP_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = PXP_GetInstance(base); + CLOCK_DisableClock(s_pxpClocks[instance]); +#endif +} + +void PXP_Reset(PXP_Type *base) +{ + base->CTRL_SET = PXP_CTRL_SFTRST_MASK; + base->CTRL_CLR = (PXP_CTRL_SFTRST_MASK | PXP_CTRL_CLKGATE_MASK); +} + +void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config) +{ + assert(config); + + base->AS_CTRL = (base->AS_CTRL & ~PXP_AS_CTRL_FORMAT_MASK) | PXP_AS_CTRL_FORMAT(config->pixelFormat); + + base->AS_BUF = config->bufferAddr; + base->AS_PITCH = config->pitchBytes; +} + +void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config) +{ + assert(config); + uint32_t reg; + + reg = base->AS_CTRL; + reg &= + ~(PXP_AS_CTRL_ALPHA0_INVERT_MASK | PXP_AS_CTRL_ROP_MASK | PXP_AS_CTRL_ALPHA_MASK | PXP_AS_CTRL_ALPHA_CTRL_MASK); + reg |= (PXP_AS_CTRL_ROP(config->ropMode) | PXP_AS_CTRL_ALPHA(config->alpha) | + PXP_AS_CTRL_ALPHA_CTRL(config->alphaMode)); + + if (config->invertAlpha) + { + reg |= PXP_AS_CTRL_ALPHA0_INVERT_MASK; + } + + base->AS_CTRL = reg; +} + +void PXP_SetAlphaSurfacePosition( + PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY) +{ + base->OUT_AS_ULC = PXP_OUT_AS_ULC_Y(upperLeftY) | PXP_OUT_AS_ULC_X(upperLeftX); + base->OUT_AS_LRC = PXP_OUT_AS_LRC_Y(lowerRightY) | PXP_OUT_AS_LRC_X(lowerRightX); +} + +void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + base->AS_CLRKEYLOW = colorKeyLow; + base->AS_CLRKEYHIGH = colorKeyHigh; +} + +void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config) +{ + assert(config); + + base->PS_CTRL = ((base->PS_CTRL & ~(PXP_PS_CTRL_FORMAT_MASK | PXP_PS_CTRL_WB_SWAP_MASK)) | + PXP_PS_CTRL_FORMAT(config->pixelFormat) | PXP_PS_CTRL_WB_SWAP(config->swapByte)); + + base->PS_BUF = config->bufferAddr; + base->PS_UBUF = config->bufferAddrU; + base->PS_VBUF = config->bufferAddrV; + base->PS_PITCH = config->pitchBytes; +} + +void PXP_SetProcessSurfaceScaler( + PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight) +{ + uint8_t decX, decY; + uint32_t scaleX, scaleY; + + PXP_GetScalerParam(inputWidth, outputWidth, &decX, &scaleX); + PXP_GetScalerParam(inputHeight, outputHeight, &decY, &scaleY); + + base->PS_CTRL = (base->PS_CTRL & ~(PXP_PS_CTRL_DECX_MASK | PXP_PS_CTRL_DECY_MASK)) | PXP_PS_CTRL_DECX(decX) | + PXP_PS_CTRL_DECY(decY); + + base->PS_SCALE = PXP_PS_SCALE_XSCALE(scaleX) | PXP_PS_SCALE_YSCALE(scaleY); +} + +void PXP_SetProcessSurfacePosition( + PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY) +{ + base->OUT_PS_ULC = PXP_OUT_PS_ULC_Y(upperLeftY) | PXP_OUT_PS_ULC_X(upperLeftX); + base->OUT_PS_LRC = PXP_OUT_PS_LRC_Y(lowerRightY) | PXP_OUT_PS_LRC_X(lowerRightX); +} + +void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + base->PS_CLRKEYLOW = colorKeyLow; + base->PS_CLRKEYHIGH = colorKeyHigh; +} + +void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config) +{ + assert(config); + + base->OUT_CTRL = (base->OUT_CTRL & ~(PXP_OUT_CTRL_FORMAT_MASK | PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)) | + PXP_OUT_CTRL_FORMAT(config->pixelFormat) | PXP_OUT_CTRL_INTERLACED_OUTPUT(config->interlacedMode); + + base->OUT_BUF = config->buffer0Addr; + base->OUT_BUF2 = config->buffer1Addr; + + base->OUT_PITCH = config->pitchBytes; + base->OUT_LRC = PXP_OUT_LRC_Y(config->height - 1U) | PXP_OUT_LRC_X(config->width - 1U); + +/* + * The dither store size must be set to the same with the output buffer size, + * otherwise the dither engine could not work. + */ +#if defined(PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) + base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(config->width - 1U) | + PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(config->height - 1U); +#endif +} + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) +void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config) +{ + assert(config); + + base->CSC2_CTRL = (base->CSC2_CTRL & ~PXP_CSC2_CTRL_CSC_MODE_MASK) | PXP_CSC2_CTRL_CSC_MODE(config->mode); + + base->CSC2_COEF0 = + (PXP_ConvertFloat(config->A1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A1_SHIFT) | + (PXP_ConvertFloat(config->A2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A2_SHIFT); + + base->CSC2_COEF1 = + (PXP_ConvertFloat(config->A3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_A3_SHIFT) | + (PXP_ConvertFloat(config->B1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_B1_SHIFT); + + base->CSC2_COEF2 = + (PXP_ConvertFloat(config->B2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B2_SHIFT) | + (PXP_ConvertFloat(config->B3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B3_SHIFT); + + base->CSC2_COEF3 = + (PXP_ConvertFloat(config->C1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C1_SHIFT) | + (PXP_ConvertFloat(config->C2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C2_SHIFT); + + base->CSC2_COEF4 = + (PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4_C3_SHIFT) | + PXP_CSC2_COEF4_D1(config->D1); + + base->CSC2_COEF5 = PXP_CSC2_COEF5_D2(config->D2) | PXP_CSC2_COEF5_D3(config->D3); +} +#endif + +void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode) +{ + /* + * The equations used for Colorspace conversion are: + * + * R = C0*(Y+Y_OFFSET) + C1(V+UV_OFFSET) + * G = C0*(Y+Y_OFFSET) + C3(U+UV_OFFSET) + C2(V+UV_OFFSET) + * B = C0*(Y+Y_OFFSET) + C4(U+UV_OFFSET) + */ + + if (kPXP_Csc1YUV2RGB == mode) + { + base->CSC1_COEF0 = (base->CSC1_COEF0 & + ~(PXP_CSC1_COEF0_C0_MASK | PXP_CSC1_COEF0_Y_OFFSET_MASK | PXP_CSC1_COEF0_UV_OFFSET_MASK | + PXP_CSC1_COEF0_YCBCR_MODE_MASK)) | + PXP_CSC1_COEF0_C0(0x100U) /* 1.00. */ + | PXP_CSC1_COEF0_Y_OFFSET(0x0U) /* 0. */ + | PXP_CSC1_COEF0_UV_OFFSET(0x0U); /* 0. */ + base->CSC1_COEF1 = PXP_CSC1_COEF1_C1(0x0123U) /* 1.140. */ + | PXP_CSC1_COEF1_C4(0x0208U); /* 2.032. */ + base->CSC1_COEF2 = PXP_CSC1_COEF2_C2(0x076BU) /* -0.851. */ + | PXP_CSC1_COEF2_C3(0x079BU); /* -0.394. */ + } + else + { + base->CSC1_COEF0 = (base->CSC1_COEF0 & + ~(PXP_CSC1_COEF0_C0_MASK | PXP_CSC1_COEF0_Y_OFFSET_MASK | PXP_CSC1_COEF0_UV_OFFSET_MASK)) | + PXP_CSC1_COEF0_YCBCR_MODE_MASK | PXP_CSC1_COEF0_C0(0x12AU) /* 1.164. */ + | PXP_CSC1_COEF0_Y_OFFSET(0x1F0U) /* -16. */ + | PXP_CSC1_COEF0_UV_OFFSET(0x180U); /* -128. */ + base->CSC1_COEF1 = PXP_CSC1_COEF1_C1(0x0198U) /* 1.596. */ + | PXP_CSC1_COEF1_C4(0x0204U); /* 2.017. */ + base->CSC1_COEF2 = PXP_CSC1_COEF2_C2(0x0730U) /* -0.813. */ + | PXP_CSC1_COEF2_C3(0x079CU); /* -0.392. */ + } +} + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) +void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config) +{ + base->LUT_CTRL = (base->LUT_CTRL & ~(PXP_LUT_CTRL_OUT_MODE_MASK | PXP_LUT_CTRL_LOOKUP_MODE_MASK)) | + PXP_LUT_CTRL_LRU_UPD_MASK | /* Use Least Recently Used Policy Update Control. */ + PXP_LUT_CTRL_OUT_MODE(config->outMode) | PXP_LUT_CTRL_LOOKUP_MODE(config->lookupMode); + + if (kPXP_LutOutRGBW4444CFA == config->outMode) + { + base->CFA = config->cfaValue; + } +} + +status_t PXP_LoadLutTable( + PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr) +{ + if (kPXP_LutCacheRGB565 == lookupMode) + { + /* Make sure the previous memory write is finished, especially the LUT data memory. */ + __DSB(); + + base->LUT_EXTMEM = memAddr; + /* Invalid cache. */ + base->LUT_CTRL |= PXP_LUT_CTRL_INVALID_MASK; + } + else + { + /* Number of bytes must be divisable by 8. */ + if ((bytesNum & 0x07U) || (bytesNum < 8U) || (lutStartAddr & 0x07U) || + (bytesNum + lutStartAddr > PXP_LUT_TABLE_BYTE)) + { + return kStatus_InvalidArgument; + } + + base->LUT_EXTMEM = memAddr; + base->LUT_ADDR = PXP_LUT_ADDR_ADDR(lutStartAddr) | PXP_LUT_ADDR_NUM_BYTES(bytesNum); + + base->STAT_CLR = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK; + + /* Start DMA transfer. */ + base->LUT_CTRL |= PXP_LUT_CTRL_DMA_START_MASK; + + __DSB(); + + /* Wait for transfer completed. */ + while (!(base->STAT & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)) + { + } + } + + return kStatus_Success; +} +#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ + +#if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER) +void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr) +{ + assert((memStartAddr + bytesNum) <= PXP_INTERNAL_RAM_LUT_BYTE); + + base->INIT_MEM_CTRL = + PXP_INIT_MEM_CTRL_ADDR(memStartAddr) | PXP_INIT_MEM_CTRL_SELECT(ram) | PXP_INIT_MEM_CTRL_START_MASK; + + while (bytesNum--) + { + base->INIT_MEM_DATA = (uint32_t)(*data); + data++; + } + + base->INIT_MEM_CTRL = 0U; +} + +void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data) +{ + base->DITHER_FINAL_LUT_DATA0 = data->data_3_0; + base->DITHER_FINAL_LUT_DATA1 = data->data_7_4; + base->DITHER_FINAL_LUT_DATA2 = data->data_11_8; + base->DITHER_FINAL_LUT_DATA3 = data->data_15_12; +} + +void PXP_EnableDither(PXP_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_SET = PXP_CTRL_ENABLE_DITHER_MASK; + /* Route dither output to output buffer. */ + base->DATA_PATH_CTRL0 &= ~PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK; + } + else + { + base->CTRL_CLR = PXP_CTRL_ENABLE_DITHER_MASK; + /* Route MUX 12 output to output buffer. */ + base->DATA_PATH_CTRL0 |= PXP_DATA_PATH_CTRL0_MUX14_SEL(1U); + } +} +#endif /* FSL_FEATURE_PXP_HAS_DITHER */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pxp.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pxp.h new file mode 100644 index 0000000000..98f9d22cb8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_pxp.h @@ -0,0 +1,1235 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PXP_H_ +#define _FSL_PXP_H_ + +#include "fsl_common.h" + +/* Compatibility macro map. */ +#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK)) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK +#endif + +#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK)) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK +#endif + +#if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK)) +#define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK +#endif + +#if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK)) +#define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK +#endif + +#if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK)) +#define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK +#endif + +/*! + * @addtogroup pxp_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* PXP global LUT table is 16K. */ +#define PXP_LUT_TABLE_BYTE (16 * 1024) +/* Intenral memory for LUT, the size is 256 bytes. */ +#define PXP_INTERNAL_RAM_LUT_BYTE (256) + +/*! @name Driver version */ +/*@{*/ +#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */ +#if defined(PXP_CTRL_ROT_POS_MASK) +#define PXP_SHARE_ROTATE 1 +#else +#define PXP_SHARE_ROTATE 0 +#endif + +/*! @brief PXP interrupts to enable. */ +enum _pxp_interrupt_enable +{ + kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set + by @ref PXP_SetNextCommand has been loaded. */ + kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. */ +#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) + kPXP_LutDmaLoadInterruptEnable = PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. */ +#endif +}; + +/*! + * @brief PXP status flags. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _pxp_flags +{ + kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand + has been loaded, could set new command. */ + kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. */ +#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) + kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. */ +#endif + kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error + and processing has been terminated. */ + kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error + and processing has been terminated. */ +#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) + kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error + and processing has been terminated. */ + kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error + and processing has been terminated. */ +#endif +}; + +/*! @brief PXP output flip mode. */ +typedef enum _pxp_flip_mode +{ + kPXP_FlipDisable = 0U, /*!< Flip disable. */ + kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */ + kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */ + kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */ +} pxp_flip_mode_t; + +/*! @brief PXP rotate mode. */ +typedef enum _pxp_rotate_position +{ + kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */ + kPXP_RotateProcessSurface, /*!< Rotate the process surface. */ +} pxp_rotate_position_t; + +/*! @brief PXP rotate degree. */ +typedef enum _pxp_rotate_degree +{ + kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */ + kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */ + kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */ + kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */ +} pxp_rotate_degree_t; + +/*! @brief PXP interlaced output mode. */ +typedef enum _pxp_interlaced_output_mode +{ + kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */ + kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */ + kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */ + kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */ +} pxp_interlaced_output_mode_t; + +/*! @brief PXP output buffer format. */ +typedef enum _pxp_output_pixel_format +{ + kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ + kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ + kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */ + kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ + kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ + kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ + kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ + kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ + kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */ + kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ + kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ + kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */ + kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */ + kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */ + kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */ + kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */ + kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */ +} pxp_output_pixel_format_t; + +/*! @brief PXP output buffer configuration. */ +typedef struct _pxp_output_buffer_config +{ + pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */ + pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */ + uint32_t buffer0Addr; /*!< Output buffer 0 address. */ + uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or + field 1 in output interlaced mode. */ + uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ + uint16_t width; /*!< Pixels per line. */ + uint16_t height; /*!< How many lines in output buffer. */ +} pxp_output_buffer_config_t; + +/*! @brief PXP process surface buffer pixel format. */ +typedef enum _pxp_ps_pixel_format +{ + kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ + kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ + kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ + kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ + kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */ + kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ + kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ + kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */ + kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */ + kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */ + kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */ + kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */ + kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */ + kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */ + kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */ +} pxp_ps_pixel_format_t; + +/*! @brief PXP process surface buffer configuration. */ +typedef struct _pxp_ps_buffer_config +{ + pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */ + bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */ + uint32_t bufferAddr; /*!< Input buffer address for the first panel. */ + uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */ + uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */ + uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ +} pxp_ps_buffer_config_t; + +/*! @brief PXP alpha surface buffer pixel format. */ +typedef enum _pxp_as_pixel_format +{ + kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ + kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ + kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ + kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ + kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ + kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ + kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ +} pxp_as_pixel_format_t; + +/*! @brief PXP alphs surface buffer configuration. */ +typedef struct _pxp_as_buffer_config +{ + pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */ + uint32_t bufferAddr; /*!< Input buffer address. */ + uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ +} pxp_as_buffer_config_t; + +/*! + * @brief PXP alpha mode during blending. + */ +typedef enum _pxp_alpha_mode +{ + kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ + kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ + kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined + alpha value will be used for blend, for example, pixel alpha set + set to 200, user defined alpha set to 100, then the reault alpha + is 200 * 100 / 255. */ + kPXP_AlphaRop /*!< Raster operation. */ +} pxp_alpha_mode_t; + +/*! + * @brief PXP ROP mode during blending. + * + * Explanation: + * - AS: Alpha surface + * - PS: Process surface + * - nAS: Alpha surface NOT value + * - nPS: Process surface NOT value + */ +typedef enum _pxp_rop_mode +{ + kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */ + kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ + kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ + kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */ + kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ + kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ + kPXP_RopNotCopyAs = 0x6, /*!< nAS. */ + kPXP_RopNot = 0x7, /*!< nPS. */ + kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ + kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ + kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */ + kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */ +} pxp_rop_mode_t; + +/*! + * @brief PXP alpha surface blending configuration. + */ +typedef struct _pxp_as_blend_config +{ + uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref + kPXP_AlphaRop. */ + bool invertAlpha; /*!< Set true to invert the alpha. */ + pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */ + pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */ +} pxp_as_blend_config_t; + +/*! @brief PXP process block size. */ +typedef enum _pxp_block_size +{ + kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */ + kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */ +} pxp_block_size_t; + +/*! @brief PXP CSC1 mode. */ +typedef enum _pxp_csc1_mode +{ + kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */ + kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */ +} pxp_csc1_mode_t; + +/*! @brief PXP CSC2 mode. */ +typedef enum _pxp_csc2_mode +{ + kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */ + kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */ + kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */ + kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */ +} pxp_csc2_mode_t; + +/*! + * @brief PXP CSC2 configuration. + * + * Converting from YUV/YCbCr color spaces to the RGB color space uses the + * following equation structure: + * + * R = A1(Y+D1) + A2(U+D2) + A3(V+D3) + * G = B1(Y+D1) + B2(U+D2) + B3(V+D3) + * B = C1(Y+D1) + C2(U+D2) + C3(V+D3) + * + * Converting from the RGB color space to YUV/YCbCr color spaces uses the + * following equation structure: + * + * Y = A1*R + A2*G + A3*B + D1 + * U = B1*R + B2*G + B3*B + D2 + * V = C1*R + C2*G + C3*B + D3 + */ +typedef struct _pxp_csc2_config +{ + pxp_csc2_mode_t mode; /*!< Convertion mode. */ + float A1; /*!< A1. */ + float A2; /*!< A2. */ + float A3; /*!< A3. */ + float B1; /*!< B1. */ + float B2; /*!< B2. */ + float B3; /*!< B3. */ + float C1; /*!< C1. */ + float C2; /*!< C2. */ + float C3; /*!< C3. */ + int16_t D1; /*!< D1. */ + int16_t D2; /*!< D2. */ + int16_t D3; /*!< D3. */ +} pxp_csc2_config_t; + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) +/*! @brief PXP LUT lookup mode. */ +typedef enum _pxp_lut_lookup_mode +{ + kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT + for indirect cached 128KB lookup. */ + kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT. + Only third data path byte is tranformed. */ + kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT + selected by @ref PXP_Select8kLutBank. */ + kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */ +} pxp_lut_lookup_mode_t; + +/*! @brief PXP LUT output mode. */ +typedef enum _pxp_lut_out_mode +{ + kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */ + kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */ + kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */ +} pxp_lut_out_mode_t; + +/*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */ +typedef enum _pxp_lut_8k_bank +{ + kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */ + kPXP_Lut8kBank1, /*!< The second 8K bank used. */ +} pxp_lut_8k_bank_t; + +/*! @brief PXP LUT configuration. */ +typedef struct _pxp_lut_config +{ + pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */ + pxp_lut_out_mode_t outMode; /*!< Out mode. */ + uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */ +} pxp_lut_config_t; +#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ + +/*! @brief PXP internal memory. */ +typedef enum _pxp_ram +{ + kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */ + kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */ + kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */ +} pxp_ram_t; + +/*! @brief PXP dither mode. */ +enum _pxp_dither_mode +{ + kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */ + kPXP_DitherOrdered = 3U, /*!< Ordered dither. */ + kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */ +}; + +/*! @brief PXP dither LUT mode. */ +enum _pxp_dither_lut_mode +{ + kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */ + kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode + or Atkinson mode, which are not supported by current PXP module. */ + kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */ +}; + +/*! @brief PXP dither matrix size. */ +enum _pxp_dither_matrix_size +{ + kPXP_DitherMatrix8 = 1, /*!< The dither index matrix is 8x8. */ + kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */ +}; + +/*! @brief PXP dither final LUT data. */ +typedef struct _pxp_dither_final_lut_data +{ + uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */ + uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */ + uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */ + uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */ +} pxp_dither_final_lut_data_t; + +/*! @brief PXP dither configuration. */ +typedef struct _pxp_dither_config +{ + uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */ + uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */ + uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */ + uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */ + uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */ + uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */ + uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */ + uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref + kPXP_DitherLutOff + if any dither engine uses @ref kPXP_DitherOrdered mode. */ + uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref + _pxp_dither_matrix_size. */ + uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref + _pxp_dither_matrix_size. */ + uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref + _pxp_dither_matrix_size. */ + uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */ + uint32_t : 8; +} pxp_dither_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize the PXP. + * + * This function enables the PXP peripheral clock, and resets the PXP registers + * to default status. + * + * @param base PXP peripheral base address. + */ +void PXP_Init(PXP_Type *base); + +/*! + * @brief De-initialize the PXP. + * + * This function disables the PXP peripheral clock. + * + * @param base PXP peripheral base address. + */ +void PXP_Deinit(PXP_Type *base); + +/*! + * @brief Reset the PXP. + * + * This function resets the PXP peripheral registers to default status. + * + * @param base PXP peripheral base address. + */ +void PXP_Reset(PXP_Type *base); +/* @} */ + +/*! + * @name Global operations + * @{ + */ + +/*! + * @brief Start process. + * + * Start PXP process using current configuration. + * + * @param base PXP peripheral base address. + */ +static inline void PXP_Start(PXP_Type *base) +{ + base->CTRL_SET = PXP_CTRL_ENABLE_MASK; +} + +/*! + * @brief Enable or disable LCD hand shake. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable) +{ +#if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) + if (enable) + { + base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK; + } + else + { + base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK; + } +#else + if (enable) + { + base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK; + } + else + { + base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK; + } +#endif +} + +#if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT) +/*! + * @brief Enable or disable continous run. + * + * If continous run not enabled, @ref PXP_Start starts the PXP process. When completed, + * PXP enters idle mode and flag @ref kPXP_CompleteFlag asserts. + * + * If continous run enabled, the PXP will repeat based on the current configuration register + * settings. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK; + } + else + { + base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK; + } +} +#endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */ + +/*! + * @brief Set the PXP processing block size + * + * This function chooses the pixel block size that PXP using during process. + * Larger block size means better performace, but be careful that when PXP is + * rotating, the output must be divisible by the block size selected. + * + * @param base PXP peripheral base address. + * @param size The pixel block size. + */ +static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size) +{ + base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size); +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets PXP status flags. + * + * This function gets all PXP status flags. The flags are returned as the logical + * OR value of the enumerators @ref _pxp_flags. To check a specific status, + * compare the return value with enumerators in @ref _pxp_flags. + * For example, to check whether the PXP has completed process, use like this: + * @code + if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP)) + { + ... + } + @endcode + * + * @param base PXP peripheral base address. + * @return PXP status flags which are OR'ed by the enumerators in the _pxp_flags. + */ +static inline uint32_t PXP_GetStatusFlags(PXP_Type *base) +{ +#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) + return base->STAT & + (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | + PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | PXP_STAT_AXI_WRITE_ERROR_1_MASK); +#else + return base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | + PXP_STAT_AXI_WRITE_ERROR_0_MASK); +#endif +} + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears PXP status flags with a provided mask. + * + * @param base PXP peripheral base address. + * @param statusMask The status flags to be cleared; it is logical OR value of @ref _pxp_flags. + */ +static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask) +{ + base->STAT_CLR = statusMask; +} + +/*! + * @brief Gets the AXI ID of the failing bus operation. + * + * @param base PXP peripheral base address. + * @param axiIndex Whitch AXI to get + * - 0: AXI0 + * - 1: AXI1 + * @return The AXI ID of the failing bus operation. + */ +static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex) +{ +#if defined(PXP_STAT_AXI_ERROR_ID_1_MASK) + if (0 == axiIndex) + { + return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT); + } + else + { + return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT); + } +#else + return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT); +#endif +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables PXP interrupts according to the provided mask. + * + * This function enables the PXP interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable. + * For example, to enable PXP process complete interrupt and command loaded + * interrupt, do the following. + * @code + PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable); + @endcode + * + * @param base PXP peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _pxp_interrupt_enable. + */ +static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask) +{ + base->CTRL_SET = mask; +} + +/*! + * @brief Disables PXP interrupts according to the provided mask. + * + * This function disables the PXP interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable. + * + * @param base PXP peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _pxp_interrupt_enable. + */ +static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask) +{ + base->CTRL_CLR = mask; +} + +/* @} */ + +/*! + * @name Alpha surface + * @{ + */ + +/*! + * @brief Set the alpha surface input buffer configuration. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration. + */ +void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config); + +/*! + * @brief Set the alpha surface blending configuration. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config); + +/*! + * @brief Set the alpha surface overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface + * pixel value for that location. If no PS image is present or if the PS image also + * matches its colorkey range, the PS background color is used. + * + * @param base PXP peripheral base address. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + * + * @note Colorkey operations are higher priority than alpha or ROP operations + */ +void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); + +/*! + * @brief Enable or disable the alpha surface color key. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK; + } + { + base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK; + } +} + +/*! + * @brief Set the alpha surface position in output buffer. + * + * @param base PXP peripheral base address. + * @param upperLeftX X of the upper left corner. + * @param upperLeftY Y of the upper left corner. + * @param lowerRightX X of the lower right corner. + * @param lowerRightY Y of the lower right corner. + */ +void PXP_SetAlphaSurfacePosition( + PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); +/* @} */ + +/*! + * @name Process surface + * @{ + */ + +/*! + * @brief Set the back ground color of PS. + * + * @param base PXP peripheral base address. + * @param backGroundColor Pixel value of the background color. + */ +static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor) +{ +#if defined(PXP_PS_BACKGROUND_0_COLOR_MASK) + base->PS_BACKGROUND_0 = backGroundColor; +#else + base->PS_BACKGROUND = backGroundColor; +#endif +} + +/*! + * @brief Set the process surface input buffer configuration. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration. + */ +void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config); + +/*! + * @brief Set the process surface scaler configuration. + * + * The valid down scale fact is 1/(2^12) ~ 16. + * + * @param base PXP peripheral base address. + * @param inputWidth Input image width. + * @param inputHeight Input image height. + * @param outputWidth Output image width. + * @param outputHeight Output image height. + */ +void PXP_SetProcessSurfaceScaler( + PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight); + +/*! + * @brief Set the process surface position in output buffer. + * + * @param base PXP peripheral base address. + * @param upperLeftX X of the upper left corner. + * @param upperLeftY Y of the upper left corner. + * @param lowerRightX X of the lower right corner. + * @param lowerRightY Y of the lower right corner. + */ +void PXP_SetProcessSurfacePosition( + PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); + +/*! + * @brief Set the process surface color key. + * + * If the PS image matches colorkey range, the PS background color is output. Set + * @p colorKeyLow to 0xFFFFFFFF and @p colorKeyHigh to 0 will disable the colorkeying. + * + * @param base PXP peripheral base address. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + */ +void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); +/* @} */ + +/*! + * @name Output buffer + * @{ + */ + +/*! + * @brief Set the PXP outpt buffer configuration. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration. + */ +void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config); + +/*! + * @brief Set the global overwritten alpha value. + * + * If global overwritten alpha is enabled, the alpha component in output buffer pixels + * will be overwritten, otherwise the computed alpha value is used. + * + * @param base PXP peripheral base address. + * @param alpha The alpha value. + */ +static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha) +{ + base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha); +} + +/*! + * @brief Enable or disable the global overwritten alpha value. + * + * If global overwritten alpha is enabled, the alpha component in output buffer pixels + * will be overwritten, otherwise the computed alpha value is used. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable) +{ + if (enable) + { + base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK; + } + else + { + base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK; + } +} + +/*! + * @brief Set the rotation configuration. + * + * The PXP could rotate the process surface or the output buffer. There are + * two PXP versions: + * - Version 1: Only has one rotate sub module, the output buffer and process + * surface share the same rotate sub module, which means the process surface + * and output buffer could not be rotate at the same time. When pass in + * @ref kPXP_RotateOutputBuffer, the process surface could not use the rotate, + * Also when pass in @ref kPXP_RotateProcessSurface, output buffer could not + * use the rotate. + * - Version 2: Has two seperate rotate sub modules, the output buffer and + * process surface could configure the rotation independently. + * + * Upper layer could use the macro PXP_SHARE_ROTATE to check which version is. + * PXP_SHARE_ROTATE=1 means version 1. + * + * @param base PXP peripheral base address. + * @param position Rotate process surface or output buffer. + * @param degree Rotate degree. + * @param flipMode Flip mode. + * + * @note This function is different depends on the macro PXP_SHARE_ROTATE. + */ +static inline void PXP_SetRotateConfig(PXP_Type *base, + pxp_rotate_position_t position, + pxp_rotate_degree_t degree, + pxp_flip_mode_t flipMode) +{ +#if PXP_SHARE_ROTATE + base->CTRL = + (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) | + PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT); +#else + uint32_t ctrl = base->CTRL; + + if (kPXP_RotateOutputBuffer == position) + { + ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK); + ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT)); + } + else + { + ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK); + ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT)); + } + + base->CTRL = ctrl; +#endif +} +/* @} */ + +/*! + * @name Command queue + * @{ + */ + +/*! + * @brief Set the next command. + * + * The PXP supports a primitive ability to queue up one operation while the current + * operation is running. Workflow: + * + * 1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory + * in the order they appear in the register map. + * 2. Call this function sets the new operation to PXP. + * 3. There are two methods to check whether the PXP has loaded the new operation. + * The first method is using @ref PXP_IsNextCommandPending. If there is new operation + * not loaded by the PXP, this function returns true. The second method is checking + * the flag @ref kPXP_CommandLoadFlag, if command loaded, this flag asserts. User + * could enable interrupt @ref kPXP_CommandLoadInterruptEnable to get the loaded + * signal in interrupt way. + * 4. When command loaded by PXP, a new command could be set using this function. + * + * @code + uint32_t pxp_command1[48]; + uint32_t pxp_command2[48]; + + // Prepare the register values. + pxp_command1[0] = ...; + pxp_command1[1] = ...; + // ... + pxp_command2[0] = ...; + pxp_command2[1] = ...; + // ... + + // Make sure no new command pending. + while (PXP_IsNextCommandPending(PXP)) + { + } + + // Set new operation. + PXP_SetNextCommand(PXP, pxp_command1); + + // Wait for new command loaded. Here could check @ref kPXP_CommandLoadFlag too. + while (PXP_IsNextCommandPending(PXP)) + { + } + + PXP_SetNextCommand(PXP, pxp_command2); + @endcode + * + * @param base PXP peripheral base address. + * @param commandAddr Address of the new command. + */ +static inline void PXP_SetNextCommand(PXP_Type *base, void *commandAddr) +{ + /* Make sure commands have been saved to memory. */ + __DSB(); + + base->NEXT = (uint32_t)commandAddr & PXP_NEXT_POINTER_MASK; +} + +/*! + * @brief Check whether the next command is pending. + * + * @param base UART peripheral base address. + * @return True is pending, false is not. + */ +static inline bool PXP_IsNextCommandPending(PXP_Type *base) +{ + return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK); +} + +/*! + * @brief Cancel command set by @ref PXP_SetNextCommand + * + * @param base UART peripheral base address. + */ +static inline void PXP_CancelNextCommand(PXP_Type *base) +{ + /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */ + *((volatile uint32_t *)(&(base->NEXT)) + 2U) = PXP_NEXT_ENABLED_MASK; +} + +/* @} */ + +/*! + * @name Color space conversion + * @{ + */ + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) +/*! + * @brief Set the CSC2 configuration. + * + * The CSC2 module receives pixels in any color space and can convert the pixels + * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed + * onto the LUT and rotation engine for further processing + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration. + */ +void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config); + +/*! + * @brief Enable or disable the CSC2. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableCsc2(PXP_Type *base, bool enable) +{ + if (enable) + { + base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK; + } + else + { + base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK; + } +} +#endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */ + +/*! + * @brief Set the CSC1 mode. + * + * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and + * converts the pixels to the RGB888 color space. It could only be used by process + * surface. + * + * @param base PXP peripheral base address. + * @param mode The conversion mode. + */ +void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode); + +/*! + * @brief Enable or disable the CSC1. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableCsc1(PXP_Type *base, bool enable) +{ + if (enable) + { + base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK; + } + else + { + base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK; + } +} +/* @} */ + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) +/*! + * @name LUT operations + * @{ + */ + +/*! + * @brief Set the LUT configuration. + * + * The lookup table (LUT) is used to modify pixels in a manner that is not linear + * and that cannot be achieved by the color space conversion modules. To setup + * the LUT, the complete workflow is: + * 1. Use @ref PXP_SetLutConfig to set the configuration, such as the lookup mode. + * 2. Use @ref PXP_LoadLutTable to load the lookup table to PXP. + * 3. Use @ref PXP_EnableLut to enable the function. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration. + */ +void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config); + +/*! + * @brief Set the look up table to PXP. + * + * If lookup mode is DIRECT mode, this function loads @p bytesNum of values + * from the address @p memAddr into PXP LUT address @p lutStartAddr. So this + * function allows only update part of the PXP LUT. + * + * If lookup mode is CACHE mode, this function sets the new address to @p memAddr + * and invalid the PXP LUT cache. + * + * @param base PXP peripheral base address. + * @param lookupMode Which lookup mode is used. Note that this parameter is only + * used to distinguish DIRECT mode and CACHE mode, it does not change the register + * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function @ref PXP_SetLutConfig. + * @param bytesNum How many bytes to set. This value must be divisable by 8. + * @param memAddr Address of look up table to set. + * @param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should + * be 8 bytes aligned. + * + * @retval kStatus_Success Load successfully. + * @retval kStatus_InvalidArgument Failed because of invalid argument. + */ +status_t PXP_LoadLutTable( + PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr); + +/*! + * @brief Enable or disable the LUT. + * + * @param base PXP peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableLut(PXP_Type *base, bool enable) +{ + if (enable) + { + base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK; + } + else + { + base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK; + } +} + +/*! + * @brief Select the 8kB LUT bank in DIRECT_RGB444 mode. + * + * @param base PXP peripheral base address. + * @param bank The bank to select. + */ +static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank) +{ + base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank); +} +/* @} */ +#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ + +#if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER) +/*! + * @name Dither + * @{ + */ + +/*! + * @brief Write data to the PXP internal memory. + * + * @param base PXP peripheral base address. + * @param ram Which internal memory to write. + * @param bytesNum How many bytes to write. + * @param data Pointer to the data to write. + * @param memStartAddr The start address in the internal memory to write the data. + */ +void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr); + +/*! + * @brief Set the dither final LUT data. + * + * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4] + * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate + * the final output pixel to the next process module. + * + * @param base PXP peripheral base address. + * @param data Pointer to the LUT data to set. + */ +void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data); + +/*! + * @brief Set the configuration for the dither block. + * + * If the pre-dither LUT, post-dither LUT or ordered dither is used, please call + * @ref PXP_SetInternalRamData to set the LUT data to internal memory. + * + * If the final LUT is used, please call @ref PXP_SetDitherFinalLutData to set + * the LUT data. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration. + * + * @note When using ordered dithering, please set the PXP process block size same + * with the ordered dithering matrix size using function @ref PXP_SetProcessBlockSize. + */ +static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config) +{ + base->DITHER_CTRL = *((const uint32_t *)config) & 0x00FFFFFFU; +} + +/*! + * @brief Enable or disable dither engine in the PXP process path. + * + * After the initialize function @ref PXP_Init, the dither engine is disabled and not + * use in the PXP processing path. This function enables the dither engine and + * routes the dither engine output to the output buffer. When the dither engine + * is enabled using this function, @ref PXP_SetDitherConfig must be called to + * configure dither engine correctly, otherwise there is not output to the output + * buffer. + * + * @param base PXP peripheral base address. + * @param enable Pass in true to enable, false to disable. + */ +void PXP_EnableDither(PXP_Type *base, bool enable); + +/* @} */ + +#endif /* FSL_FEATURE_PXP_HAS_DITHER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PXP_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_qtmr.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_qtmr.c new file mode 100644 index 0000000000..8373fa0359 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_qtmr.c @@ -0,0 +1,477 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_qtmr.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.qtmr" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base Quad Timer peripheral base address + * + * @return The Quad Timer instance + */ +static uint32_t QTMR_GetInstance(TMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Quad Timer bases for each instance. */ +static TMR_Type *const s_qtmrBases[] = TMR_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Quad Timer clocks for each instance. */ +static const clock_ip_name_t s_qtmrClocks[] = TMR_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t QTMR_GetInstance(TMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_qtmrBases); instance++) + { + if (s_qtmrBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_qtmrBases)); + + return instance; +} + +void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the module clock */ + CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Setup the counter sources */ + base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource)); + + /* Setup the master mode operation */ + base->CHANNEL[channel].SCTRL = (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode)); + + /* Setup debug mode */ + base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode); + + base->CHANNEL[channel].FILT &= ~( TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK); + /* Setup input filter */ + base->CHANNEL[channel].FILT = (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod)); +} + +void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel) +{ + /* Stop the counter */ + base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the module clock */ + CLOCK_DisableClock(s_qtmrClocks[QTMR_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void QTMR_GetDefaultConfig(qtmr_config_t *config) +{ + assert(config); + + /* Halt counter during debug mode */ + config->debugMode = kQTMR_RunNormalInDebug; + /* Another counter cannot force state of OFLAG signal */ + config->enableExternalForce = false; + /* Compare function's output from this counter is not broadcast to other counters */ + config->enableMasterMode = false; + /* Fault filter count is set to 0 */ + config->faultFilterCount = 0; + /* Fault filter period is set to 0 which disables the fault filter */ + config->faultFilterPeriod = 0; + /* Primary count source is IP bus clock divide by 2 */ + config->primarySource = kQTMR_ClockDivide_2; + /* Secondary count source is counter 0 input pin */ + config->secondarySource = kQTMR_Counter0InputPin; +} + +status_t QTMR_SetupPwm( + TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz) +{ + uint32_t periodCount, highCount, lowCount, reg; + + if (dutyCyclePercent > 100) + { + /* Invalid dutycycle */ + return kStatus_Fail; + } + + /* Set OFLAG pin for output mode and force out a low on the pin */ + base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); + + /* Counter values to generate a PWM signal */ + periodCount = (srcClock_Hz / pwmFreqHz); + highCount = (periodCount * dutyCyclePercent) / 100; + lowCount = periodCount - highCount; + + /* Setup the compare registers for PWM output */ + base->CHANNEL[channel].COMP1 = lowCount; + base->CHANNEL[channel].COMP2 = highCount; + + /* Setup the pre-load registers for PWM output */ + base->CHANNEL[channel].CMPLD1 = lowCount; + base->CHANNEL[channel].CMPLD2 = highCount; + + reg = base->CHANNEL[channel].CSCTRL; + /* Setup the compare load control for COMP1 and COMP2. + * Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted + */ + reg &= ~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK); + reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1)); + base->CHANNEL[channel].CSCTRL = reg; + + if (outputPolarity) + { + /* Invert the polarity */ + base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OPS_MASK; + } + else + { + /* True polarity, no inversion */ + base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_OPS_MASK; + } + + reg = base->CHANNEL[channel].CTRL; + reg &= ~(TMR_CTRL_OUTMODE_MASK); + /* Count until compare value is reached and re-initialize the counter, toggle OFLAG output + * using alternating compare register + */ + reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); + base->CHANNEL[channel].CTRL = reg; + + return kStatus_Success; +} + +void QTMR_SetupInputCapture(TMR_Type *base, + qtmr_channel_selection_t channel, + qtmr_input_source_t capturePin, + bool inputPolarity, + bool reloadOnCapture, + qtmr_input_capture_edge_t captureMode) +{ + uint16_t reg; + + /* Clear the prior value for the input source for capture */ + reg = base->CHANNEL[channel].CTRL & (~TMR_CTRL_SCS_MASK); + + /* Set the new input source */ + reg |= TMR_CTRL_SCS(capturePin); + base->CHANNEL[channel].CTRL = reg; + + /* Clear the prior values for input polarity, capture mode. Set the external pin as input */ + reg = base->CHANNEL[channel].SCTRL & (~(TMR_SCTRL_IPS_MASK | TMR_SCTRL_CAPTURE_MODE_MASK | TMR_SCTRL_OEN_MASK)); + /* Set the new values */ + reg |= (TMR_SCTRL_IPS(inputPolarity) | TMR_SCTRL_CAPTURE_MODE(captureMode)); + base->CHANNEL[channel].SCTRL = reg; + + /* Setup if counter should reload when a capture occurs */ + if (reloadOnCapture) + { + base->CHANNEL[channel].CSCTRL |= TMR_CSCTRL_ROC_MASK; + } + else + { + base->CHANNEL[channel].CSCTRL &= ~TMR_CSCTRL_ROC_MASK; + } +} + +void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Compare interrupt */ + if (mask & kQTMR_CompareInterruptEnable) + { + reg |= TMR_SCTRL_TCFIE_MASK; + } + /* Overflow interrupt */ + if (mask & kQTMR_OverflowInterruptEnable) + { + reg |= TMR_SCTRL_TOFIE_MASK; + } + /* Input edge interrupt */ + if (mask & kQTMR_EdgeInterruptEnable) + { + /* Restriction: Do not set both SCTRL[IEFIE] and DMA[IEFDE] */ + base->CHANNEL[channel].DMA &= ~TMR_DMA_IEFDE_MASK; + reg |= TMR_SCTRL_IEFIE_MASK; + } + base->CHANNEL[channel].SCTRL = reg; + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 interrupt */ + if (mask & kQTMR_Compare1InterruptEnable) + { + reg |= TMR_CSCTRL_TCF1EN_MASK; + } + /* Compare 2 interrupt */ + if (mask & kQTMR_Compare2InterruptEnable) + { + reg |= TMR_CSCTRL_TCF2EN_MASK; + } + base->CHANNEL[channel].CSCTRL = reg; +} + +void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Compare interrupt */ + if (mask & kQTMR_CompareInterruptEnable) + { + reg &= ~TMR_SCTRL_TCFIE_MASK; + } + /* Overflow interrupt */ + if (mask & kQTMR_OverflowInterruptEnable) + { + reg &= ~TMR_SCTRL_TOFIE_MASK; + } + /* Input edge interrupt */ + if (mask & kQTMR_EdgeInterruptEnable) + { + reg &= ~TMR_SCTRL_IEFIE_MASK; + } + base->CHANNEL[channel].SCTRL = reg; + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 interrupt */ + if (mask & kQTMR_Compare1InterruptEnable) + { + reg &= ~TMR_CSCTRL_TCF1EN_MASK; + } + /* Compare 2 interrupt */ + if (mask & kQTMR_Compare2InterruptEnable) + { + reg &= ~TMR_CSCTRL_TCF2EN_MASK; + } + base->CHANNEL[channel].CSCTRL = reg; +} + +uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel) +{ + uint32_t enabledInterrupts = 0; + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Compare interrupt */ + if (reg & TMR_SCTRL_TCFIE_MASK) + { + enabledInterrupts |= kQTMR_CompareFlag; + } + /* Overflow interrupt */ + if (reg & TMR_SCTRL_TOFIE_MASK) + { + enabledInterrupts |= kQTMR_OverflowInterruptEnable; + } + /* Input edge interrupt */ + if (reg & TMR_SCTRL_IEFIE_MASK) + { + enabledInterrupts |= kQTMR_EdgeInterruptEnable; + } + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 interrupt */ + if (reg & TMR_CSCTRL_TCF1EN_MASK) + { + enabledInterrupts |= kQTMR_Compare1InterruptEnable; + } + /* Compare 2 interrupt */ + if (reg & TMR_CSCTRL_TCF2EN_MASK) + { + enabledInterrupts |= kQTMR_Compare2InterruptEnable; + } + + return enabledInterrupts; +} + +uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) +{ + uint32_t statusFlags = 0; + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Timer compare flag */ + if (reg & TMR_SCTRL_TCF_MASK) + { + statusFlags |= kQTMR_CompareFlag; + } + /* Timer overflow flag */ + if (reg & TMR_SCTRL_TOF_MASK) + { + statusFlags |= kQTMR_OverflowFlag; + } + /* Input edge flag */ + if (reg & TMR_SCTRL_IEF_MASK) + { + statusFlags |= kQTMR_EdgeFlag; + } + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 flag */ + if (reg & TMR_CSCTRL_TCF1_MASK) + { + statusFlags |= kQTMR_Compare1Flag; + } + /* Compare 2 flag */ + if (reg & TMR_CSCTRL_TCF2_MASK) + { + statusFlags |= kQTMR_Compare2Flag; + } + + return statusFlags; +} + +void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Timer compare flag */ + if (mask & kQTMR_CompareFlag) + { + reg &= ~TMR_SCTRL_TCF_MASK; + } + /* Timer overflow flag */ + if (mask & kQTMR_OverflowFlag) + { + reg &= ~TMR_SCTRL_TOF_MASK; + } + /* Input edge flag */ + if (mask & kQTMR_EdgeFlag) + { + reg &= ~TMR_SCTRL_IEF_MASK; + } + base->CHANNEL[channel].SCTRL = reg; + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 flag */ + if (mask & kQTMR_Compare1Flag) + { + reg &= ~TMR_CSCTRL_TCF1_MASK; + } + /* Compare 2 flag */ + if (mask & kQTMR_Compare2Flag) + { + reg &= ~TMR_CSCTRL_TCF2_MASK; + } + base->CHANNEL[channel].CSCTRL = reg; +} + +void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) +{ + /* Set the length bit to reinitialize the counters on a match */ + base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; + + if (base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) + { + /* Counting down */ + base->CHANNEL[channel].COMP2 = ticks; + } + else + { + /* Counting up */ + base->CHANNEL[channel].COMP1 = ticks; + } +} + +void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].DMA; + /* Input Edge Flag DMA Enable */ + if (mask & kQTMR_InputEdgeFlagDmaEnable) + { + /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */ + base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_IEFIE_MASK; + reg |= TMR_DMA_IEFDE_MASK; + } + /* Comparator Preload Register 1 DMA Enable */ + if (mask & kQTMR_ComparatorPreload1DmaEnable) + { + reg |= TMR_DMA_CMPLD1DE_MASK; + } + /* Comparator Preload Register 2 DMA Enable */ + if (mask & kQTMR_ComparatorPreload2DmaEnable) + { + reg |= TMR_DMA_CMPLD2DE_MASK; + } + base->CHANNEL[channel].DMA = reg; +} + +void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].DMA; + /* Input Edge Flag DMA Enable */ + if (mask & kQTMR_InputEdgeFlagDmaEnable) + { + reg &= ~TMR_DMA_IEFDE_MASK; + } + /* Comparator Preload Register 1 DMA Enable */ + if (mask & kQTMR_ComparatorPreload1DmaEnable) + { + reg &= ~TMR_DMA_CMPLD1DE_MASK; + } + /* Comparator Preload Register 2 DMA Enable */ + if (mask & kQTMR_ComparatorPreload2DmaEnable) + { + reg &= ~TMR_DMA_CMPLD2DE_MASK; + } + base->CHANNEL[channel].DMA = reg; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_qtmr.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_qtmr.h new file mode 100644 index 0000000000..ee23b4cca8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_qtmr.h @@ -0,0 +1,461 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_QTMR_H_ +#define _FSL_QTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup qtmr + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief Quad Timer primary clock source selection*/ +typedef enum _qtmr_primary_count_source +{ + kQTMR_ClockCounter0InputPin = 0, /*!< Use counter 0 input pin */ + kQTMR_ClockCounter1InputPin, /*!< Use counter 1 input pin */ + kQTMR_ClockCounter2InputPin, /*!< Use counter 2 input pin */ + kQTMR_ClockCounter3InputPin, /*!< Use counter 3 input pin */ + kQTMR_ClockCounter0Output, /*!< Use counter 0 output */ + kQTMR_ClockCounter1Output, /*!< Use counter 1 output */ + kQTMR_ClockCounter2Output, /*!< Use counter 2 output */ + kQTMR_ClockCounter3Output, /*!< Use counter 3 output */ + kQTMR_ClockDivide_1, /*!< IP bus clock divide by 1 prescaler */ + kQTMR_ClockDivide_2, /*!< IP bus clock divide by 2 prescaler */ + kQTMR_ClockDivide_4, /*!< IP bus clock divide by 4 prescaler */ + kQTMR_ClockDivide_8, /*!< IP bus clock divide by 8 prescaler */ + kQTMR_ClockDivide_16, /*!< IP bus clock divide by 16 prescaler */ + kQTMR_ClockDivide_32, /*!< IP bus clock divide by 32 prescaler */ + kQTMR_ClockDivide_64, /*!< IP bus clock divide by 64 prescaler */ + kQTMR_ClockDivide_128 /*!< IP bus clock divide by 128 prescaler */ +} qtmr_primary_count_source_t; + +/*! @brief Quad Timer input sources selection*/ +typedef enum _qtmr_input_source +{ + kQTMR_Counter0InputPin = 0, /*!< Use counter 0 input pin */ + kQTMR_Counter1InputPin, /*!< Use counter 1 input pin */ + kQTMR_Counter2InputPin, /*!< Use counter 2 input pin */ + kQTMR_Counter3InputPin /*!< Use counter 3 input pin */ +} qtmr_input_source_t; + +/*! @brief Quad Timer counting mode selection */ +typedef enum _qtmr_counting_mode +{ + kQTMR_NoOperation = 0, /*!< No operation */ + kQTMR_PriSrcRiseEdge, /*!< Count rising edges or primary source */ + kQTMR_PriSrcRiseAndFallEdge, /*!< Count rising and falling edges of primary source */ + kQTMR_PriSrcRiseEdgeSecInpHigh, /*!< Count rise edges of pri SRC while sec inp high active */ + kQTMR_QuadCountMode, /*!< Quadrature count mode, uses pri and sec sources */ + kQTMR_PriSrcRiseEdgeSecDir, /*!< Count rising edges of pri SRC; sec SRC specifies dir */ + kQTMR_SecSrcTrigPriCnt, /*!< Edge of sec SRC trigger primary count until compare*/ + kQTMR_CascadeCount /*!< Cascaded count mode (up/down) */ +} qtmr_counting_mode_t; + +/*! @brief Quad Timer output mode selection*/ +typedef enum _qtmr_output_mode +{ + kQTMR_AssertWhenCountActive = 0, /*!< Assert OFLAG while counter is active*/ + kQTMR_ClearOnCompare, /*!< Clear OFLAG on successful compare */ + kQTMR_SetOnCompare, /*!< Set OFLAG on successful compare */ + kQTMR_ToggleOnCompare, /*!< Toggle OFLAG on successful compare */ + kQTMR_ToggleOnAltCompareReg, /*!< Toggle OFLAG using alternating compare registers */ + kQTMR_SetOnCompareClearOnSecSrcInp, /*!< Set OFLAG on compare, clear on sec SRC input edge */ + kQTMR_SetOnCompareClearOnCountRoll, /*!< Set OFLAG on compare, clear on counter rollover */ + kQTMR_EnableGateClock /*!< Enable gated clock output while count is active */ +} qtmr_output_mode_t; + +/*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */ +typedef enum _qtmr_input_capture_edge +{ + kQTMR_NoCapture = 0, /*!< Capture is disabled */ + kQTMR_RisingEdge, /*!< Capture on rising edge (IPS=0) or falling edge (IPS=1)*/ + kQTMR_FallingEdge, /*!< Capture on falling edge (IPS=0) or rising edge (IPS=1)*/ + kQTMR_RisingAndFallingEdge /*!< Capture on both edges */ +} qtmr_input_capture_edge_t; + +/*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */ +typedef enum _qtmr_preload_control +{ + kQTMR_NoPreload = 0, /*!< Never preload */ + kQTMR_LoadOnComp1, /*!< Load upon successful compare with value in COMP1 */ + kQTMR_LoadOnComp2 /*!< Load upon successful compare with value in COMP2*/ +} qtmr_preload_control_t; + +/*! @brief List of Quad Timer run options when in Debug mode */ +typedef enum _qtmr_debug_action +{ + kQTMR_RunNormalInDebug = 0U, /*!< Continue with normal operation */ + kQTMR_HaltCounter, /*!< Halt counter */ + kQTMR_ForceOutToZero, /*!< Force output to logic 0 */ + kQTMR_HaltCountForceOutZero /*!< Halt counter and force output to logic 0 */ +} qtmr_debug_action_t; + +/*! @brief List of Quad Timer interrupts */ +typedef enum _qtmr_interrupt_enable +{ + kQTMR_CompareInterruptEnable = (1U << 0), /*!< Compare interrupt.*/ + kQTMR_Compare1InterruptEnable = (1U << 1), /*!< Compare 1 interrupt.*/ + kQTMR_Compare2InterruptEnable = (1U << 2), /*!< Compare 2 interrupt.*/ + kQTMR_OverflowInterruptEnable = (1U << 3), /*!< Timer overflow interrupt.*/ + kQTMR_EdgeInterruptEnable = (1U << 4) /*!< Input edge interrupt.*/ +} qtmr_interrupt_enable_t; + +/*! @brief List of Quad Timer flags */ +typedef enum _qtmr_status_flags +{ + kQTMR_CompareFlag = (1U << 0), /*!< Compare flag */ + kQTMR_Compare1Flag = (1U << 1), /*!< Compare 1 flag */ + kQTMR_Compare2Flag = (1U << 2), /*!< Compare 2 flag */ + kQTMR_OverflowFlag = (1U << 3), /*!< Timer overflow flag */ + kQTMR_EdgeFlag = (1U << 4) /*!< Input edge flag */ +} qtmr_status_flags_t; + +/*! @brief List of channel selection */ +typedef enum _qtmr_channel_selection +{ + kQTMR_Channel_0 = 0U, /*!< TMR Channel 0 */ + kQTMR_Channel_1, /*!< TMR Channel 1 */ + kQTMR_Channel_2, /*!< TMR Channel 2 */ + kQTMR_Channel_3, /*!< TMR Channel 3 */ +} qtmr_channel_selection_t; + +/*! @brief List of Quad Timer DMA enable */ +typedef enum _qtmr_dma_enable +{ + kQTMR_InputEdgeFlagDmaEnable = (1U << 0), /*!< Input Edge Flag DMA Enable.*/ + kQTMR_ComparatorPreload1DmaEnable = (1U << 1), /*!< Comparator Preload Register 1 DMA Enable.*/ + kQTMR_ComparatorPreload2DmaEnable = (1U << 2), /*!< Comparator Preload Register 2 DMA Enable.*/ +} qtmr_dma_enable_t; + +/*! + * @brief Quad Timer config structure + * + * This structure holds the configuration settings for the Quad Timer peripheral. To initialize this + * structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _qtmr_config +{ + qtmr_primary_count_source_t primarySource; /*!< Specify the primary count source */ + qtmr_input_source_t secondarySource; /*!< Specify the secondary count source */ + bool enableMasterMode; /*!< true: Broadcast compare function output to other counters; + false no broadcast */ + bool enableExternalForce; /*!< true: Compare from another counter force state of OFLAG signal + false: OFLAG controlled by local counter */ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + qtmr_debug_action_t debugMode; /*!< Operation in Debug mode */ +} qtmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the Quad Timer clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the Quad Timer driver. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param config Pointer to user's Quad Timer config structure + */ +void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config); + +/*! + * @brief Stops the counter and gates the Quad Timer clock + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + */ +void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel); + +/*! + * @brief Fill in the Quad Timer config struct with the default settings + * + * The default values are: + * @code + * config->debugMode = kQTMR_RunNormalInDebug; + * config->enableExternalForce = false; + * config->enableMasterMode = false; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->primarySource = kQTMR_ClockDivide_2; + * config->secondarySource = kQTMR_Counter0InputPin; + * @endcode + * @param config Pointer to user's Quad Timer config structure. + */ +void QTMR_GetDefaultConfig(qtmr_config_t *config); + +/*! @}*/ + +/*! + * @brief Sets up Quad timer module for PWM signal output. + * + * The function initializes the timer module according to the parameters passed in by the user. The + * function also sets up the value compare registers to match the PWM signal requirements. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param pwmFreqHz PWM signal frequency in Hz + * @param dutyCyclePercent PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + * @param outputPolarity true: invert polarity of the output signal, false: no inversion + * @param srcClock_Hz Main counter clock in Hz. + * + * @return Returns an error if there was error setting up the signal. + */ +status_t QTMR_SetupPwm( + TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz); + +/*! + * @brief Allows the user to count the source clock cycles until a capture event arrives. + * + * The count is stored in the capture register. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param capturePin Pin through which we receive the input signal to trigger the capture + * @param inputPolarity true: invert polarity of the input signal, false: no inversion + * @param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload + * @param captureMode Specifies which edge of the input signal triggers a capture + */ +void QTMR_SetupInputCapture(TMR_Type *base, + qtmr_channel_selection_t channel, + qtmr_input_source_t capturePin, + bool inputPolarity, + bool reloadOnCapture, + qtmr_input_capture_edge_t captureMode); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Quad Timer interrupts + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! + * @brief Disables the selected Quad Timer interrupts + * + * @param base Quad Timer peripheral base addres + * @param channel Quad Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! + * @brief Gets the enabled Quad Timer interrupts + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Quad Timer status flags + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ +uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel); + +/*! + * @brief Clears the Quad Timer status flags. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ +void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in ticks. + * + * Timers counts from initial value till it equals the count value set here. The counter + * will then reinitialize to the value specified in the Load register. + * + * @note + * 1. This function will write the time period in ticks to COMP1 or COMP2 register + * depending on the count direction + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * 3. This function supports cases, providing only primary source clock without secondary source clock. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param ticks Timer period in units of ticks + */ +void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * + * @return Current counter value in ticks + */ +static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel) +{ + return base->CHANNEL[channel].CNTR; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the Quad Timer counter. + * + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param clockSource Quad Timer clock source + */ +static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource) +{ + uint16_t reg = base->CHANNEL[channel].CTRL; + + reg &= ~(TMR_CTRL_CM_MASK); + reg |= TMR_CTRL_CM(clockSource); + base->CHANNEL[channel].CTRL = reg; +} + +/*! + * @brief Stops the Quad Timer counter. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + */ +static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel) +{ + base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; +} + +/*! @}*/ + +/*! + * @name Enable and Disable the Quad Timer DMA + * @{ + */ + +/*! + * @brief Enable the Quad Timer DMA. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ +void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! + * @brief Disable the Quad Timer DMA. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ +void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_QTMR_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_rtwdog.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_rtwdog.c new file mode 100644 index 0000000000..54f2717a6f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_rtwdog.c @@ -0,0 +1,105 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rtwdog.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rtwdog" +#endif + + +/******************************************************************************* + * Code + ******************************************************************************/ + +void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask) +{ + if (mask & kRTWDOG_InterruptFlag) + { + base->CS |= RTWDOG_CS_FLG_MASK; + } +} + +void RTWDOG_GetDefaultConfig(rtwdog_config_t *config) +{ + assert(config); + + config->enableRtwdog = true; + config->clockSource = kRTWDOG_ClockSource1; + config->prescaler = kRTWDOG_ClockPrescalerDivide1; + config->workMode.enableWait = true; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->testMode = kRTWDOG_TestModeDisabled; + config->enableUpdate = true; + config->enableInterrupt = false; + config->enableWindowMode = false; + config->windowValue = 0U; + config->timeoutValue = 0xFFFFU; +} + +void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | RTWDOG_CS_INT(config->enableInterrupt) | + RTWDOG_CS_WIN(config->enableWindowMode) | RTWDOG_CS_UPDATE(config->enableUpdate) | + RTWDOG_CS_DBG(config->workMode.enableDebug) | RTWDOG_CS_STOP(config->workMode.enableStop) | + RTWDOG_CS_WAIT(config->workMode.enableWait) | RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | + RTWDOG_CS_TST(config->testMode); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + RTWDOG_Unlock(base); + base->WIN = config->windowValue; + base->TOVAL = config->timeoutValue; + base->CS = value; + EnableGlobalIRQ(primaskValue); +} + +void RTWDOG_Deinit(RTWDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupts */ + primaskValue = DisableGlobalIRQ(); + RTWDOG_Unlock(base); + RTWDOG_Disable(base); + EnableGlobalIRQ(primaskValue); +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_rtwdog.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_rtwdog.h new file mode 100644 index 0000000000..76ba5b3b03 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_rtwdog.h @@ -0,0 +1,404 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RTWDOG_H_ +#define _FSL_RTWDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtwdog + * @{ + */ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Unlock sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U)& 0xFFFFU) /*!< Second word of unlock sequence */ +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U)& 0xFFFFU) /*!< Second word of refresh sequence */ +/*@}*/ +/*! @name Driver version */ +/*@{*/ +/*! @brief RTWDOG driver version 2.0.0. */ +#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Describes RTWDOG clock source. */ +typedef enum _rtwdog_clock_source +{ + kRTWDOG_ClockSource0 = 0U, /*!< Clock source 0 */ + kRTWDOG_ClockSource1 = 1U, /*!< Clock source 1 */ + kRTWDOG_ClockSource2 = 2U, /*!< Clock source 2 */ + kRTWDOG_ClockSource3 = 3U, /*!< Clock source 3 */ +} rtwdog_clock_source_t; + +/*! @brief Describes the selection of the clock prescaler. */ +typedef enum _rtwdog_clock_prescaler +{ + kRTWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kRTWDOG_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */ +} rtwdog_clock_prescaler_t; + +/*! @brief Defines RTWDOG work mode. */ +typedef struct _rtwdog_work_mode +{ + bool enableWait; /*!< Enables or disables RTWDOG in wait mode */ + bool enableStop; /*!< Enables or disables RTWDOG in stop mode */ + bool enableDebug; /*!< Enables or disables RTWDOG in debug mode */ +} rtwdog_work_mode_t; + +/*! @brief Describes RTWDOG test mode. */ +typedef enum _rtwdog_test_mode +{ + kRTWDOG_TestModeDisabled = 0U, /*!< Test Mode disabled */ + kRTWDOG_UserModeEnabled = 1U, /*!< User Mode enabled */ + kRTWDOG_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ + kRTWDOG_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ +} rtwdog_test_mode_t; + +/*! @brief Describes RTWDOG configuration structure. */ +typedef struct _rtwdog_config +{ + bool enableRtwdog; /*!< Enables or disables RTWDOG */ + rtwdog_clock_source_t clockSource; /*!< Clock source select */ + rtwdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ + rtwdog_work_mode_t workMode; /*!< Configures RTWDOG work mode in debug stop and wait mode */ + rtwdog_test_mode_t testMode; /*!< Configures RTWDOG test mode */ + bool enableUpdate; /*!< Update write-once register enable */ + bool enableInterrupt; /*!< Enables or disables RTWDOG interrupt */ + bool enableWindowMode; /*!< Enables or disables RTWDOG window mode */ + uint16_t windowValue; /*!< Window value */ + uint16_t timeoutValue; /*!< Timeout value */ +} rtwdog_config_t; + +/*! + * @brief RTWDOG interrupt configuration structure. + * + * This structure contains the settings for all of the RTWDOG interrupt configurations. + */ +enum _rtwdog_interrupt_enable_t +{ + kRTWDOG_InterruptEnable = RTWDOG_CS_INT_MASK, /*!< Interrupt is generated before forcing a reset */ +}; + +/*! + * @brief RTWDOG status flags. + * + * This structure contains the RTWDOG status flags for use in the RTWDOG functions. + */ +enum _rtwdog_status_flags_t +{ + kRTWDOG_RunningFlag = RTWDOG_CS_EN_MASK, /*!< Running flag, set when RTWDOG is enabled */ + kRTWDOG_InterruptFlag = RTWDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name RTWDOG Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the RTWDOG configuration structure. + * + * This function initializes the RTWDOG configuration structure to default values. The default + * values are: + * @code + * rtwdogConfig->enableRtwdog = true; + * rtwdogConfig->clockSource = kRTWDOG_ClockSource1; + * rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1; + * rtwdogConfig->workMode.enableWait = true; + * rtwdogConfig->workMode.enableStop = false; + * rtwdogConfig->workMode.enableDebug = false; + * rtwdogConfig->testMode = kRTWDOG_TestModeDisabled; + * rtwdogConfig->enableUpdate = true; + * rtwdogConfig->enableInterrupt = false; + * rtwdogConfig->enableWindowMode = false; + * rtwdogConfig->windowValue = 0U; + * rtwdogConfig->timeoutValue = 0xFFFFU; + * @endcode + * + * @param config Pointer to the RTWDOG configuration structure. + * @see rtwdog_config_t + */ +void RTWDOG_GetDefaultConfig(rtwdog_config_t *config); + +/*! + * @brief Initializes the RTWDOG module. + * + * This function initializes the RTWDOG. + * To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * Example: + * @code + * rtwdog_config_t config; + * RTWDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * RTWDOG_Init(wdog_base,&config); + * @endcode + * + * @param base RTWDOG peripheral base address. + * @param config The configuration of the RTWDOG. + */ +void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config); + +/*! + * @brief De-initializes the RTWDOG module. + * + * This function shuts down the RTWDOG. + * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. + * + * @param base RTWDOG peripheral base address. + */ +void RTWDOG_Deinit(RTWDOG_Type *base); + +/* @} */ + +/*! + * @name RTWDOG functional Operation + * @{ + */ + +/*! + * @brief Enables the RTWDOG module. + * + * This function writes a value into the WDOG_CS register to enable the RTWDOG. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + */ +static inline void RTWDOG_Enable(RTWDOG_Type *base) +{ + base->CS |= RTWDOG_CS_EN_MASK; +} + +/*! + * @brief Disables the RTWDOG module. + * + * This function writes a value into the WDOG_CS register to disable the RTWDOG. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address + */ +static inline void RTWDOG_Disable(RTWDOG_Type *base) +{ + base->CS &= ~RTWDOG_CS_EN_MASK; +} + +/*! + * @brief Enables the RTWDOG interrupt. + * + * This function writes a value into the WDOG_CS register to enable the RTWDOG interrupt. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + * @param mask The interrupts to enable. + * The parameter can be a combination of the following source if defined: + * @arg kRTWDOG_InterruptEnable + */ +static inline void RTWDOG_EnableInterrupts(RTWDOG_Type *base, uint32_t mask) +{ + base->CS |= mask; +} + +/*! + * @brief Disables the RTWDOG interrupt. + * + * This function writes a value into the WDOG_CS register to disable the RTWDOG interrupt. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + * @param mask The interrupts to disabled. + * The parameter can be a combination of the following source if defined: + * @arg kRTWDOG_InterruptEnable + */ +static inline void RTWDOG_DisableInterrupts(RTWDOG_Type *base, uint32_t mask) +{ + base->CS &= ~mask; +} + +/*! + * @brief Gets the RTWDOG all status flags. + * + * This function gets all status flags. + * + * Example to get the running flag: + * @code + * uint32_t status; + * status = RTWDOG_GetStatusFlags(wdog_base) & kRTWDOG_RunningFlag; + * @endcode + * @param base RTWDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false). @see _rtwdog_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base) +{ + return (base->CS & (RTWDOG_CS_EN_MASK | RTWDOG_CS_FLG_MASK)); +} + +/*! + * @brief Clears the RTWDOG flag. + * + * This function clears the RTWDOG status flag. + * + * Example to clear an interrupt flag: + * @code + * RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag); + * @endcode + * @param base RTWDOG peripheral base address. + * @param mask The status flags to clear. + * The parameter can be any combination of the following values: + * @arg kRTWDOG_InterruptFlag + */ +void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask); + +/*! + * @brief Sets the RTWDOG timeout value. + * + * This function writes a timeout value into the WDOG_TOVAL register. + * The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address + * @param timeoutCount RTWDOG timeout value, count of RTWDOG clock ticks. + */ +static inline void RTWDOG_SetTimeoutValue(RTWDOG_Type *base, uint16_t timeoutCount) +{ + base->TOVAL = timeoutCount; +} + +/*! + * @brief Sets the RTWDOG window value. + * + * This function writes a window value into the WDOG_WIN register. + * The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + * @param windowValue RTWDOG window value. + */ +static inline void RTWDOG_SetWindowValue(RTWDOG_Type *base, uint16_t windowValue) +{ + base->WIN = windowValue; +} + +/*! + * @brief Unlocks the RTWDOG register written. + * + * This function unlocks the RTWDOG register written. + * + * Before starting the unlock sequence and following the configuration, disable the global interrupts. + * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. + * After the configuration finishes, re-enable the global interrupts. + * + * @param base RTWDOG peripheral base address + */ +static inline void RTWDOG_Unlock(RTWDOG_Type *base) +{ + if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) + { + base->CNT = RTWDOG_UPDATE_KEY; + } + else + { + base->CNT = WDOG_FIRST_WORD_OF_UNLOCK; + base->CNT = WDOG_SECOND_WORD_OF_UNLOCK; + } +} + +/*! + * @brief Refreshes the RTWDOG timer. + * + * This function feeds the RTWDOG. + * This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted. + * + * @param base RTWDOG peripheral base address + */ +static inline void RTWDOG_Refresh(RTWDOG_Type *base) +{ + if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) + { + base->CNT = RTWDOG_REFRESH_KEY; + } + else + { + base->CNT = WDOG_FIRST_WORD_OF_REFRESH; + base->CNT = WDOG_SECOND_WORD_OF_REFRESH; + } +} + +/*! + * @brief Gets the RTWDOG counter value. + * + * This function gets the RTWDOG counter value. + * + * @param base RTWDOG peripheral base address. + * @return Current RTWDOG counter value. + */ +static inline uint16_t RTWDOG_GetCounterValue(RTWDOG_Type *base) +{ + return base->CNT; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_RTWDOG_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai.c new file mode 100644 index 0000000000..db5d26a263 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai.c @@ -0,0 +1,2104 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _sai_transfer_state +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occured. */ +}; + +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +static uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/*!@brief SAI handle pointer */ +static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + uint32_t freq = mclkSrcClock_Hz; + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /*In order to prevent overflow */ + freq /= 100; + mclk_Hz /= 100; + + /* Compute the max fract number */ + max_fract = mclk_Hz * 4096 / freq + 1; + if (max_fract > 256) + { + max_fract = 256; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = freq * fract; + remaind = mul_freq % mclk_Hz; + divide = mul_freq / mclk_Hz; + + /* Find the exactly frequency */ + if (remaind == 0) + { + current_fract = fract; + current_divide = mul_freq / mclk_Hz; + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2) + { + remaind = mclk_Hz - remaind; + divide += 1; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); + + /* Waiting for the divider updated */ + while (base->MCR & I2S_MCR_DUF_MASK) + { + } +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +static uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_saiBases)); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * j)); + buffer++; + } + base->TDR[channel] = data; + data = 0; + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = base->RDR[channel]; + for (j = 0; j < bytesPerWord; j++) + { + *buffer = (data >> (8U * j)) & 0xFF; + buffer++; + } + } +} + +void SAI_TxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + SAI_TxReset(base); + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + base->TCR4 |= I2S_TCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; + default: + break; + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_TxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ +} + +void SAI_RxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SAI clock first. */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + SAI_RxReset(base); + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + base->RCR4 |= I2S_RCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; + default: + break; + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_RxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ +} + +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SAI_TxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeAsync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_RxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeSync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* If RE not sync with TE, than disable TE, otherwise, shall not disable TE */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) != 0x1U) + { + /* Should not close RE even sync with Rx */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } + } +} + +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* While TX is not sync with RX, close RX */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) != 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } + } +} + +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +{ + base->TCSR |= (uint32_t)type; + + /* Clear the software reset */ + base->TCSR &= ~I2S_TCSR_SR_MASK; +} + +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +{ + base->RCSR |= (uint32_t)type; + + /* Clear the software reset */ + base->RCSR &= ~I2S_RCSR_SR_MASK; +} + +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(mask); +} + +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(mask); +} + +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); + + val |= I2S_TCR4_MF(order); + base->TCR4 = val; +} + +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); + + val |= I2S_RCR4_MF(order); + base->RCR4 = val; +} + +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); + + val |= I2S_TCR2_BCP(polarity); + base->TCR2 = val; +} + +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); + + val |= I2S_RCR2_BCP(polarity); + base->RCR2 = val; +} + +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); + + val |= I2S_TCR4_FSP(polarity); + base->TCR4 = val; +} + +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); + + val |= I2S_RCR4_FSP(polarity); + base->RCR4 = val; +} + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->TCR4; + + val &= ~I2S_TCR4_FPACK_MASK; + val |= I2S_TCR4_FPACK(pack); + base->TCR4 = val; +} + +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->RCR4; + + val &= ~I2S_RCR4_FPACK_MASK; + val |= I2S_RCR4_FPACK(pack); + base->RCR4 = val; +} +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = 0; + uint32_t val = 0; + uint32_t channels = 2U; + + if (format->stereo != kSAI_Stereo) + { + channels = 1U; + } + + if (format->isFrameSyncCompact) + { + bclk = format->sampleRate_Hz * format->bitWidth * channels; + val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); + val |= I2S_TCR4_SYWD(format->bitWidth - 1U); + base->TCR4 = val; + } + else + { + bclk = format->sampleRate_Hz * 32U * 2U; + } + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->TCR2 & I2S_TCR2_BCD_MASK) + { + base->TCR2 &= ~I2S_TCR2_DIV_MASK; + base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U; + if (format->protocol == kSAI_BusRightJustified) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val); + } + else + { + if (base->TCR4 & I2S_TCR4_MF_MASK) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); + } + else + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); + } + } + + /* Set mono or stereo */ + base->TMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->TCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = 0; + uint32_t val = 0; + uint32_t channels = 2U; + + if (format->stereo != kSAI_Stereo) + { + channels = 1U; + } + + if (format->isFrameSyncCompact) + { + bclk = format->sampleRate_Hz * format->bitWidth * channels; + val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); + val |= I2S_RCR4_SYWD(format->bitWidth - 1U); + base->RCR4 = val; + } + else + { + bclk = format->sampleRate_Hz * 32U * 2U; + } + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->RCR2 & I2S_RCR2_BCD_MASK) + { + base->RCR2 &= ~I2S_RCR2_DIV_MASK; + base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U; + if (format->protocol == kSAI_BusRightJustified) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val); + } + else + { + if (base->RCR4 & I2S_RCR4_MF_MASK) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); + } + else + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0); + } + } + + /* Set mono or stereo */ + base->RMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->RCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + while (i < size) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + i += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + while (i < size) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + i += bytesPerWord; + } +} + +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + + /* Enable Tx irq */ + EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + + /* Enable Rx irq */ + EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortSend(base, handle); + + /* Clear all the internal information */ + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortReceive(base, handle); + + /* Clear all the internal information */ + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->TCSR & I2S_TCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Reset FIFO for safety */ + SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->TCSR & I2S_TCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->TCSR & I2S_TCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->RCSR & I2S_RCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Reset FIFO for safety */ + SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->RCSR & I2S_RCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->RCSR & I2S_RCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +void I2S0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S1*/ + +#if defined(I2S2) +void I2S2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S2_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][0]); + s_saiTxIsr(I2S2, s_saiHandle[2][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S2_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][1]); + s_saiRxIsr(I2S2, s_saiHandle[2][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S2*/ + +#if defined(I2S3) +void I2S3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(I2S3, s_saiHandle[3][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(I2S3, s_saiHandle[3][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S3*/ + +#if defined(AUDIO__SAI0) +void AUDIO_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && + ((AUDIO__SAI0->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && + ((AUDIO__SAI0->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && + ((AUDIO__SAI0->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && + ((AUDIO__SAI0->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI0 */ + +#if defined(AUDIO__SAI1) +void AUDIO_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && + ((AUDIO__SAI1->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && + ((AUDIO__SAI1->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && + ((AUDIO__SAI1->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && + ((AUDIO__SAI1->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI1 */ + +#if defined(AUDIO__SAI2) +void AUDIO_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && + ((AUDIO__SAI2->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && + ((AUDIO__SAI2->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && + ((AUDIO__SAI2->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && + ((AUDIO__SAI2->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI2, s_saiHandle[2][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI2 */ + +#if defined(AUDIO__SAI3) +void AUDIO_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && + ((AUDIO__SAI3->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && + ((AUDIO__SAI3->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && + ((AUDIO__SAI3->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && + ((AUDIO__SAI3->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI3, s_saiHandle[3][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(AUDIO__SAI6) +void AUDIO_SAI6_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1]) && + ((AUDIO__SAI6->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][1]) && + ((AUDIO__SAI6->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0]) && + ((AUDIO__SAI6->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][0]) && + ((AUDIO__SAI6->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI6, s_saiHandle[6][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI6 */ + +#if defined(AUDIO__SAI7) +void AUDIO_SAI7_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[7][1]) && + ((AUDIO__SAI7->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[7][1]) && + ((AUDIO__SAI7->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI7, s_saiHandle[7][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[7][0]) && + ((AUDIO__SAI7->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[7][0]) && + ((AUDIO__SAI7->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI7, s_saiHandle[7][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI7 */ + +#if defined(ADMA__SAI0) +void ADMA_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI0 */ + +#if defined(ADMA__SAI1) +void ADMA_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI1 */ + +#if defined(ADMA__SAI2) +void ADMA_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI2 */ + +#if defined(ADMA__SAI3) +void ADMA_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI3 */ + +#if defined(ADMA__SAI4) +void ADMA_SAI4_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI4 */ + +#if defined(ADMA__SAI5) +void ADMA_SAI5_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI5 */ + +#if defined(SAI0) +void SAI0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && ((SAI0->RCSR & kSAI_FIFORequestFlag) || (SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && ((SAI0->RCSR & kSAI_FIFOWarningFlag) || (SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && ((SAI0->TCSR & kSAI_FIFORequestFlag) || (SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && ((SAI0->TCSR & kSAI_FIFOWarningFlag) || (SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI0 */ + +#if defined(SAI1) +void SAI1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((SAI1->RCSR & kSAI_FIFORequestFlag) || (SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((SAI1->RCSR & kSAI_FIFOWarningFlag) || (SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((SAI1->TCSR & kSAI_FIFORequestFlag) || (SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((SAI1->TCSR & kSAI_FIFOWarningFlag) || (SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI1 */ + +#if defined(SAI2) +void SAI2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && ((SAI2->RCSR & kSAI_FIFORequestFlag) || (SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && ((SAI2->RCSR & kSAI_FIFOWarningFlag) || (SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && ((SAI2->TCSR & kSAI_FIFORequestFlag) || (SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && ((SAI2->TCSR & kSAI_FIFOWarningFlag) || (SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI2, s_saiHandle[2][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI2 */ + +#if defined(SAI3) +void SAI3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && ((SAI3->RCSR & kSAI_FIFORequestFlag) || (SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && ((SAI3->RCSR & kSAI_FIFOWarningFlag) || (SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && ((SAI3->TCSR & kSAI_FIFORequestFlag) || (SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && ((SAI3->TCSR & kSAI_FIFOWarningFlag) || (SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI3, s_saiHandle[3][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void SAI3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(SAI3, s_saiHandle[3][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void SAI3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(SAI3, s_saiHandle[3][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI3 */ + +#if defined(SAI4) +void SAI4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][1]) && ((SAI4->RCSR & kSAI_FIFORequestFlag) || (SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][1]) && ((SAI4->RCSR & kSAI_FIFOWarningFlag) || (SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI4, s_saiHandle[4][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][0]) && ((SAI4->TCSR & kSAI_FIFORequestFlag) || (SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][0]) && ((SAI4->TCSR & kSAI_FIFOWarningFlag) || (SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI4, s_saiHandle[4][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI4 */ + +#if defined(SAI5) +void SAI5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1]) && ((SAI5->RCSR & kSAI_FIFORequestFlag) || (SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][1]) && ((SAI5->RCSR & kSAI_FIFOWarningFlag) || (SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0]) && ((SAI5->TCSR & kSAI_FIFORequestFlag) || (SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][0]) && ((SAI5->TCSR & kSAI_FIFOWarningFlag) || (SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI5, s_saiHandle[5][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI5 */ + +#if defined(SAI6) +void SAI6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1]) && ((SAI6->RCSR & kSAI_FIFORequestFlag) || (SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][1]) && ((SAI6->RCSR & kSAI_FIFOWarningFlag) || (SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0]) && ((SAI6->TCSR & kSAI_FIFORequestFlag) || (SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][0]) && ((SAI6->TCSR & kSAI_FIFOWarningFlag) || (SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI6, s_saiHandle[6][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI6 */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai.h new file mode 100644 index 0000000000..82dd26bfa6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai.h @@ -0,0 +1,1043 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SAI_H_ +#define _FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ +/*@}*/ + +/*! @brief SAI return status*/ +enum _sai_status_t +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode */ + kSAI_Slave = 0x1U /*!< Slave mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoRight, /*!< Only Right channel have sound. */ + kSAI_MonoLeft /*!< Only left channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief SAI data order, MSB or LSB */ +typedef enum _sai_data_order +{ + kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ + kSAI_DataMSB /*!< MSB bit transferred first */ +} sai_data_order_t; + +/*! @brief SAI clock polarity, active high or low */ +typedef enum _sai_clock_polarity +{ + kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */ + kSAI_PolarityActiveLow /*!< Clock active low */ +} sai_clock_polarity_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +} sai_sync_mode_t; + +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief The SAI interrupt enable flag */ +enum _sai_interrupt_enable_t +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The DMA request sources */ +enum _sai_dma_enable_t +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The SAI status flag */ +enum _sai_flags +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configuration structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + sai_mclk_source_t mclkSource; /*!< Master Clock source */ + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000 Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + uint8_t channel; /*!< Data channel used in transfer.*/ + sai_protocol_t protocol; /*!< Which audio protocol used */ + bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame + sync length is 64 times of bit clock. */ +} sai_transfer_format_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + uint8_t channel; /*!< Transfer channel */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI Tx peripheral. + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. +*/ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Initializes the SAI Rx peripheral. + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Sets the SAI Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Sets the SAI Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer +*/ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables the SAI Tx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables the SAI Rx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following sources if defined. + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param type Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param type Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type); + +/*! + * @brief Set the Tx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Rx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Set Tx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); + +/*! +* @brief Set Rx FIFO packing feature. +* +* @param base SAI base pointer. +* @param pack FIFO pack type. It is element of sai_fifo_packing_t. +*/ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! +* @brief Set Tx FIFO error continue. +* +* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature +* not enabled, SAI will hang and users need to clear FEF flag in TCSR register. +* +* @param base SAI base pointer. +* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. +*/ +static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->TCR4 |= I2S_TCR4_FCONT_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FCONT_MASK; + } +} + +/*! +* @brief Set Rx FIFO error continue. +* +* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature +* not enabled, SAI will hang and users need to clear FEF flag in RCSR register. +* +* @param base SAI base pointer. +* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. +*/ +static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->RCR4 |= I2S_RCR4_FCONT_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FCONT_MASK; + } +} +#endif +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables the SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is the status_t. +*/ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is one of status_t. +*/ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SAI_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai_edma.c new file mode 100644 index 0000000000..11bdae301b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai_edma.c @@ -0,0 +1,509 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai_edma" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + /* Disable DMA enable bit */ + SAI_TxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); + EDMA_AbortTransfer(handle); + } +} + +static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; + sai_edma_handle_t *saiHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + /* Disable DMA enable bit */ + SAI_RxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); + EDMA_AbortTransfer(handle); + } +} + +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, (edma_tcd_t *)(STCD_ADDR(handle->tcd)), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + if (format->bitWidth == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = format->bitWidth / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = format->channel; + + /* Clear the channel enable bits unitl do a send/receive */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + if (format->bitWidth == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = format->bitWidth / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = format->channel; + + /* Clear the channel enable bits unitl do a send/receive */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + /* Enable the channel FIFO */ + base->TCR3 |= I2S_TCR3_TCE(1U << handle->channel); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable the channel FIFO */ + base->RCR3 |= I2S_RCR3_RCE(1U << handle->channel); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable the channel FIFO */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + + /* Disable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Tx */ + SAI_TxEnable(base, false); + + /* Reset the FIFO pointer, at the same time clear all error flags if set */ + base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK); + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Handle the queue index */ + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable the channel FIFO */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + + /* Disable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Rx */ + SAI_RxEnable(base, false); + + /* Reset the FIFO pointer, at the same time clear all error flags if set */ + base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK); + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Handle the queue index */ + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortSendEDMA(base, handle); + + /* Clear all the internal information */ + memset(handle->tcd, 0U, sizeof(handle->tcd)); + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortReceiveEDMA(base, handle); + + /* Clear all the internal information */ + memset(handle->tcd, 0U, sizeof(handle->tcd)); + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai_edma.h new file mode 100644 index 0000000000..0b806d246b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_sai_edma.h @@ -0,0 +1,268 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SAI_EDMA_H_ +#define _FSL_SAI_EDMA_H_ + +#include "fsl_sai.h" +#include "fsl_edma.h" + +/*! + * @addtogroup sai_edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ +/*@}*/ + +typedef struct _sai_edma_handle sai_edma_handle_t; + +/*! @brief SAI eDMA transfer callback function for finish and error */ +typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ +struct _sai_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs a non-blocking SAI transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SAI. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param count Bytes count sent by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SAI. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param count Bytes count received by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_semc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_semc.c new file mode 100644 index 0000000000..31dbe76495 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_semc.c @@ -0,0 +1,986 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_semc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.semc" +#endif + + +/*! @brief Define macros for SEMC driver. */ +#define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U) +#define SEMC_IPCOMMANDMAGICKEY (0xA55A) +#define SEMC_IOCR_PINMUXBITWIDTH (0x3U) +#define SEMC_IOCR_NAND_CE (4U) +#define SEMC_IOCR_NOR_CE (5U) +#define SEMC_IOCR_NOR_CE_A8 (2U) +#define SEMC_IOCR_PSRAM_CE (6U) +#define SEMC_IOCR_PSRAM_CE_A8 (3U) +#define SEMC_IOCR_DBI_CSX (7U) +#define SEMC_IOCR_DBI_CSX_A8 (4U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX (28U) +#define SEMC_BMCR0_TYPICAL_WQOS (5U) +#define SEMC_BMCR0_TYPICAL_WAGE (8U) +#define SEMC_BMCR0_TYPICAL_WSH (0x40U) +#define SEMC_BMCR0_TYPICAL_WRWS (0x10U) +#define SEMC_BMCR1_TYPICAL_WQOS (5U) +#define SEMC_BMCR1_TYPICAL_WAGE (8U) +#define SEMC_BMCR1_TYPICAL_WPH (0x60U) +#define SEMC_BMCR1_TYPICAL_WBR (0x40U) +#define SEMC_BMCR1_TYPICAL_WRWS (0x24U) +#define SEMC_STARTADDRESS (0x80000000U) +#define SEMC_ENDADDRESS (0xDFFFFFFFU) +#define SEMC_BR_MEMSIZE_MIN (4) +#define SEMC_BR_MEMSIZE_OFFSET (2) +#define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024) +#define SEMC_SDRAM_MODESETCAL_OFFSET (4) +#define SEMC_BR_REG_NUM (9) +#define SEMC_BYTE_NUMBIT (8) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for SEMC module. + * + * @param base SEMC peripheral base address + */ +static uint32_t SEMC_GetInstance(SEMC_Type *base); + +/*! + * @brief Covert the input memory size to internal register set value. + * + * @param base SEMC peripheral base address + * @param size_kbytes SEMC memory size in unit of kbytes. + * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F. + * @return Execution status. + */ +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted); + +/*! + * @brief Covert the external timing nanosecond to internal clock cycle. + * + * @param time_ns SEMC external time interval in unit of nanosecond. + * @param clkSrc_Hz SEMC clock source frequency. + * @return The changed internal clock cycle. + */ +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz); + +/*! + * @brief Configure IP command. + * + * @param base SEMC peripheral base address. + * @param size_bytes SEMC IP command data size. + * @return Execution status. + */ +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes); + +/*! + * @brief Check if the IP command has finished. + * + * @param base SEMC peripheral base address. + * @return Execution status. + */ +static status_t SEMC_IsIPCommandDone(SEMC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SEMC clocks for each instance. */ +static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS; +static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to SEMC bases for each instance. */ +static SEMC_Type *const s_semcBases[] = SEMC_BASE_PTRS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SEMC_GetInstance(SEMC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_semcBases); instance++) + { + if (s_semcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_semcBases)); + + return instance; +} + +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted) +{ + assert(sizeConverted); + uint32_t memsize; + + if ((size_kbytes < SEMC_BR_MEMSIZE_MIN) || (size_kbytes > SEMC_BR_MEMSIZE_MAX)) + { + return kStatus_SEMC_InvalidMemorySize; + } + + *sizeConverted = 0; + memsize = size_kbytes / 8; + while (memsize) + { + memsize >>= 1; + (*sizeConverted)++; + } + return kStatus_Success; +} + +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz) +{ + assert(clkSrc_Hz); + + uint8_t clockCycles = 0; + uint32_t tClk_us; + + clkSrc_Hz /= 1000000; + tClk_us = 1000000 / clkSrc_Hz; + + while (tClk_us * clockCycles < (time_ns * 1000)) + { + clockCycles++; + } + + return clockCycles; +} + +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes) +{ + if ((size_bytes > SEMC_IPCOMMANDDATASIZEBYTEMAX) || (!size_bytes)) + { + return kStatus_SEMC_InvalidIpcmdDataSize; + } + + /* Set data size. */ + /* Note: It is better to set data size as the device data port width when transfering + * device command data. but for device memory data transfer, it can be set freely. + * Note: If the data size is greater than data port width, for example, datsz = 4, data port = 16bit, + * then the 4-byte data transfer will be split into two 2-byte transfer, the slave address + * will be switched automatically according to connected device type*/ + base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); + /* Clear data size. */ + base->IPCR2 = 0; + /* Set data size. */ + if (size_bytes < 4) + { + base->IPCR2 |= SEMC_IPCR2_BM3_MASK; + } + if (size_bytes < 3) + { + base->IPCR2 |= SEMC_IPCR2_BM2_MASK; + } + if (size_bytes < 2) + { + base->IPCR2 |= SEMC_IPCR2_BM1_MASK; + } + return kStatus_Success; +} + +static status_t SEMC_IsIPCommandDone(SEMC_Type *base) +{ + /* Poll status bit till command is done*/ + while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK)) + { + }; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + + /* Check error status */ + if (base->INTR & SEMC_INTR_IPCMDERR_MASK) + { + base->INTR |= SEMC_INTR_IPCMDERR_MASK; + return kStatus_SEMC_IpCommandExecutionError; + } + + return kStatus_Success; +} + +void SEMC_GetDefaultConfig(semc_config_t *config) +{ + assert(config); + + semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ + semc_queuea_weight_t queueaWeight; + semc_queueb_weight_t queuebWeight; + + /* Get default settings. */ + config->dqsMode = kSEMC_Loopbackinternal; + config->cmdTimeoutCycles = 0; + config->busTimeoutCycles = 0x1F; + + /* Set a typical weight settings. */ + memset((void *)&queueWeight, 0, sizeof(semc_axi_queueweight_t)); + + queueaWeight.qos = SEMC_BMCR0_TYPICAL_WQOS; + queueaWeight.aging = SEMC_BMCR0_TYPICAL_WAGE; + queueaWeight.slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH; + queueaWeight.slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS; + queuebWeight.qos = SEMC_BMCR1_TYPICAL_WQOS; + queuebWeight.aging = SEMC_BMCR1_TYPICAL_WAGE; + queuebWeight.slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS; + queuebWeight.weightPagehit = SEMC_BMCR1_TYPICAL_WPH; + queuebWeight.bankRotation = SEMC_BMCR1_TYPICAL_WBR; + + config->queueWeight.queueaWeight = &queueaWeight; + config->queueWeight.queuebWeight = &queuebWeight; +} + +void SEMC_Init(SEMC_Type *base, semc_config_t *configure) +{ + assert(configure); + + uint8_t index = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate sdram controller clock. */ + CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Initialize all BR to zero due to the default base address set. */ + for (index = 0; index < SEMC_BR_REG_NUM; index++) + { + base->BR[index] = 0; + } + + /* Software reset for SEMC internal logical . */ + base->MCR = SEMC_MCR_SWRST_MASK; + while (base->MCR & SEMC_MCR_SWRST_MASK) + { + } + + /* Configure, disable module first. */ + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_BTO(configure->busTimeoutCycles) | + SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode); + + /* Configure Queue 0/1 for AXI bus. */ + if (configure->queueWeight.queueaWeight) + { + base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight); + } + if (configure->queueWeight.queuebWeight) + { + base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight); + } + /* Enable SEMC. */ + base->MCR &= ~SEMC_MCR_MDIS_MASK; +} + +void SEMC_Deinit(SEMC_Type *base) +{ + /* Disable module. Check there is no pending command before disable module. */ + while (!(base->STS0 & SEMC_STS0_IDLE_MASK)) + { + ; + } + + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SDRAM clock. */ + CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(clkSrc_Hz); + assert(config->refreshBurstLen); + + uint8_t memsize; + status_t result = kStatus_Success; + uint16_t prescale = config->tPrescalePeriod_Ns / 16 / (1000000000 / clkSrc_Hz); + uint16_t refresh; + uint16_t urgentRef; + uint16_t idle; + uint16_t mode; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->csxPinMux == kSEMC_MUXA8) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (prescale > 256) + { + return kStatus_SEMC_InvalidTimerSetting; + } + + refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns; + urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns; + idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns; + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + + base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | + SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency); + /* IOMUX setting. */ + if (cs) + { + base->IOCR = iocReg | (cs << config->csxPinMux); + } + + base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK; + + /* Timing setting. */ + base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1); + base->SDRAMCR2 = + SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR2_REF2REF( + SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ITO(idle); + base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) | + /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */ + SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef); + + SEMC->IPCR1 = 0x2; + SEMC->IPCR2 = 0; + + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Prechargeall, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Mode setting value. */ + mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET); + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Enables refresh */ + base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; + + return kStatus_Success; +} + +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(config->timingConfig); + + uint8_t memsize; + status_t result; + + if ((config->axiAddress < SEMC_STARTADDRESS) || (config->axiAddress > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->cePinMux == kSEMC_MUXRDY) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + uint32_t iocReg = base->IOCR & ~((SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux) | SEMC_IOCR_MUX_RDY_MASK); + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL1_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL1_MASK; + } + result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + /* IOMUX setting. */ + if (config->cePinMux) + { + base->IOCR = iocReg | (SEMC_IOCR_NAND_CE << config->cePinMux); + } + else + { + base->IOCR = iocReg | (1U << config->cePinMux); + } + + base->NANDCR0 = SEMC_NANDCR0_PS(config->portSize) | SEMC_NANDCR0_BL(config->burstLen) | + SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1); + base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1); + base->NANDCR3 = config->arrayAddrOption; + return kStatus_Success; +} + +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_NOR_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL0_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL0_MASK; + } + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) | + SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) | + SEMC_NORCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NORCR1 = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + base->NORCR2 = SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | + SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) | + SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result = kStatus_Success; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_PSRAM_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[6] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SRAMCR0 = SEMC_SRAMCR0_PS(config->portSize) | SEMC_SRAMCR0_BL(config->burstLen) | + SEMC_SRAMCR0_AM(config->addrMode) | SEMC_SRAMCR0_ADVP(config->advActivePolarity) | + SEMC_SRAMCR0_COL_MASK; + + /* Timing setting. */ + base->SRAMCR1 = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + + base->SRAMCR2 = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD(config->readCycle) | + SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return result; +} + +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_DBI_CSX - 1 : + ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCsx << config->csxPinMux); + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->DBICR0 = + SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz)) | + SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz)) | + SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz)) | + SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz)) | + SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz)) | + SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz)) | + SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz)); + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) +{ + uint32_t cmdMode; + bool readCmd = 0; + bool writeCmd = 0; + status_t result; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + /* Set address. */ + base->IPCR0 = address; + + /* Check command mode. */ + cmdMode = command & 0xFU; + switch (type) + { + case kSEMC_MemType_NAND: + readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || + (cmdMode == kSEMC_NANDCM_CommandRead) || (cmdMode == kSEMC_NANDCM_Read); + writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || + (cmdMode == kSEMC_NANDCM_CommandWrite) || (cmdMode == kSEMC_NANDCM_Write); + break; + case kSEMC_MemType_NOR: + case kSEMC_MemType_8080: + readCmd = (cmdMode == kSEMC_NORDBICM_Read); + writeCmd = (cmdMode == kSEMC_NORDBICM_Write); + break; + case kSEMC_MemType_SRAM: + readCmd = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead); + writeCmd = (cmdMode == kSEMC_SRAMCM_ArrayWrite) || (cmdMode == kSEMC_SRAMCM_RegWrite); + break; + case kSEMC_MemType_SDRAM: + readCmd = (cmdMode == kSEMC_SDRAMCM_Read); + writeCmd = (cmdMode == kSEMC_SDRAMCM_Write) || (cmdMode == kSEMC_SDRAMCM_Modeset); + break; + default: + break; + } + + if (writeCmd) + { + /* Set data. */ + base->IPTXDAT = write; + } + + /* Set command code. */ + base->IPCMD = command | SEMC_IPCMD_KEY(SEMC_IPCOMMANDMAGICKEY); + /* Wait for command done. */ + result = SEMC_IsIPCommandDone(base); + if (result != kStatus_Success) + { + return result; + } + + if (readCmd) + { + /* Get the read data */ + *read = base->IPRXDAT; + } + + return kStatus_Success; +} + +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Write command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Write); + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL); + } + + return result; +} + +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + /* Read command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Read); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, &tempData); + + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + return result; +} + +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData); + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + SEMC_ConfigureIPCommand(base, dataSize); + return result; +} + +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Write command built */ + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, tempData, NULL); + } + SEMC_ConfigureIPCommand(base, dataSize); + + return result; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_semc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_semc.h new file mode 100644 index 0000000000..a6937e12ee --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_semc.h @@ -0,0 +1,807 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SEMC_H_ +#define _FSL_SEMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup semc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMC driver version 2.0.1. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief SEMC status. */ +enum _semc_status +{ + kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), + kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), + kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), + kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), + kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), + kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), + kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), + kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), + kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), + kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), + kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), + kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), +}; + +/*! @brief SEMC memory device type. */ +typedef enum _semc_mem_type { + kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ + kSEMC_MemType_SRAM, /*!< SRAM */ + kSEMC_MemType_NOR, /*!< NOR */ + kSEMC_MemType_NAND, /*!< NAND */ + kSEMC_MemType_8080 /*!< 8080. */ +} semc_mem_type_t; + +/*! @brief SEMC WAIT/RDY polarity. */ +typedef enum _semc_waitready_polarity { + kSEMC_LowActive = 0, /*!< Low active. */ + kSEMC_HighActive, /*!< High active. */ +} semc_waitready_polarity_t; + +/*! @brief SEMC SDRAM Chip selection . */ +typedef enum _semc_sdram_cs { + kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ + kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ + kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ + kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ +} semc_sdram_cs_t; + +/*! @brief SEMC NAND device type. */ +typedef enum _semc_nand_access_type { + kSEMC_NAND_ACCESS_BY_AXI = 0, + kSEMC_NAND_ACCESS_BY_IPCMD, +} semc_nand_access_type_t; + +/*! @brief SEMC interrupts . */ +typedef enum _semc_interrupt_enable { + kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ + kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ + kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ + kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ +} semc_interrupt_enable_t; + +/*! @brief SEMC IP command data size in bytes. */ +typedef enum _semc_ipcmd_datasize { + kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ + kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ + kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ + kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ +} semc_ipcmd_datasize_t; + +/*! @brief SEMC auto-refresh timing. */ +typedef enum _semc_refresh_time { + kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ + kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ + kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ +} semc_refresh_time_t; + +/*! @brief CAS latency */ +typedef enum _semc_caslatency { + kSEMC_LatencyOne = 1, /*!< Latency 1. */ + kSEMC_LatencyTwo, /*!< Latency 2. */ + kSEMC_LatencyThree, /*!< Latency 3. */ +} semc_caslatency_t; + +/*! @brief SEMC sdram column address bit number. */ +typedef enum _semc_sdram_column_bit_num { + kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_SdramColunm_11bit, /*!< 11 bit. */ + kSEMC_SdramColunm_10bit, /*!< 10 bit. */ + kSEMC_SdramColunm_9bit, /*!< 9 bit. */ +} semc_sdram_column_bit_num_t; + +/*! @brief SEMC sdram burst length. */ +typedef enum _semc_sdram_burst_len { + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ + kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ + kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ +} sem_sdram_burst_len_t; + +/*! @brief SEMC nand column address bit number. */ +typedef enum _semc_nand_column_bit_num { + kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ + kSEMC_NandColum_15bit, /*!< 15 bit. */ + kSEMC_NandColum_14bit, /*!< 14 bit. */ + kSEMC_NandColum_13bit, /*!< 13 bit. */ + kSEMC_NandColum_12bit, /*!< 12 bit. */ + kSEMC_NandColum_11bit, /*!< 11 bit. */ + kSEMC_NandColum_10bit, /*!< 10 bit. */ + kSEMC_NandColum_9bit, /*!< 9 bit. */ +} semc_nand_column_bit_num_t; + +/*! @brief SEMC nand burst length. */ +typedef enum _semc_nand_burst_len { + kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ +} sem_nand_burst_len_t; + +/*! @brief SEMC nor/sram column address bit number. */ +typedef enum _semc_norsram_column_bit_num { + kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_NorColum_11bit, /*!< 11 bit. */ + kSEMC_NorColum_10bit, /*!< 10 bit. */ + kSEMC_NorColum_9bit, /*!< 9 bit. */ + kSEMC_NorColum_8bit, /*!< 8 bit. */ + kSEMC_NorColum_7bit, /*!< 7 bit. */ + kSEMC_NorColum_6bit, /*!< 6 bit. */ + kSEMC_NorColum_5bit, /*!< 5 bit. */ + kSEMC_NorColum_4bit, /*!< 4 bit. */ + kSEMC_NorColum_3bit, /*!< 3 bit. */ + kSEMC_NorColum_2bit /*!< 2 bit. */ +} semc_norsram_column_bit_num_t; + +/*! @brief SEMC nor/sram burst length. */ +typedef enum _semc_norsram_burst_len { + kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ +} sem_norsram_burst_len_t; + +/*! @brief SEMC dbi column address bit number. */ +typedef enum _semc_dbi_column_bit_num { + kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ + kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ + kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ + kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ + kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ + kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ + kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ + kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ + kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ + kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ +} semc_dbi_column_bit_num_t; + +/*! @brief SEMC dbi burst length. */ +typedef enum _semc_dbi_burst_len { + kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ + kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ + kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ + kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ + kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ + kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ +} sem_dbi_burst_len_t; + +/*! @brief SEMC IOMUXC. */ +typedef enum _semc_iomux_pin { + kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ + kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ + kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ + kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ + kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_pin; + +/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ +typedef enum _semc_iomux_nora27_pin { + kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ + kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_nora27_pin; + +/*! @brief SEMC port size. */ +typedef enum _semc_port_size { + kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ + kSEMC_PortSize16Bit /*!< 16-Bit port size. */ +} smec_port_size_t; + +/*! @brief SEMC address mode. */ +typedef enum _semc_addr_mode { + kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ + kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ + kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ +} semc_addr_mode_t; + +/*! @brief SEMC DQS read strobe mode. */ +typedef enum _semc_dqs_mode { + kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ + kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ +} semc_dqs_mode_t; + +/*! @brief SEMC ADV signal active polarity. */ +typedef enum _semc_adv_polarity { + kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ + kSEMC_AdvActivehigh, /*!< Adv active low. */ +} semc_adv_polarity_t; + +/*! @brief SEMC RDY signal active polarity. */ +typedef enum _semc_rdy_polarity { + kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ + kSEMC_RdyActivehigh, /*!< Adv active low. */ +} semc_rdy_polarity_t; + +/*! @brief SEMC IP command for NAND: address mode. */ +typedef enum _semc_ipcmd_nand_addrmode { + kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ + kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ + kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ + kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ + kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ + kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ +} semc_ipcmd_nand_addrmode_t; + +/*! @brief SEMC IP command for NAND： command mode. */ +typedef enum _semc_ipcmd_nand_cmdmode { + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ + kSEMC_NANDCM_CommandHold, /*!< Command hold. */ + kSEMC_NANDCM_CommandAddress, /*!< Command address. */ + kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ + kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ + kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ + kSEMC_NANDCM_CommandRead, /*!< Command read. */ + kSEMC_NANDCM_CommandWrite, /*!< Command write. */ + kSEMC_NANDCM_Read, /*!< Read. */ + kSEMC_NANDCM_Write /*!< Write. */ +} semc_ipcmd_nand_cmdmode_t; + +/*! @brief SEMC NAND address option. */ +typedef enum _semc_nand_address_option { + kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ + kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ + kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ + kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ +} semc_nand_address_option_t; + +/*! @brief SEMC IP command for NOR. */ +typedef enum _semc_ipcmd_nor_dbi { + kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ + kSEMC_NORDBICM_Write /*!< NOR write. */ +} semc_ipcmd_nor_dbi_t; + +/*! @brief SEMC IP command for SRAM. */ +typedef enum _semc_ipcmd_sram { + kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ + kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ + kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ + kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ +} semc_ipcmd_sram_t; + +/*! @brief SEMC IP command for SDARM. */ +typedef enum _semc_ipcmd_sdram { + kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ + kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ + kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ + kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ + kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ + kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ + kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ + kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ +} semc_ipcmd_sdram_t; + +/*! @brief SEMC SDRAM configuration structure. + * + * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes + * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. + * Take refer to BR0~BR3 register in RM for details. + * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, + * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, + * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. + * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are + * similar to prescalePeriod_N16Cycle. + * + */ +typedef struct _semc_sdram_config +{ + semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + smec_port_size_t portSize; /*!< Port size. */ + sem_sdram_burst_len_t burstLen; /*!< Burst length. */ + semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_caslatency_t casLatency; /*!< CAS latency. */ + uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ + uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ + uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ + uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ + uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ + uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ + uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ + uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ + uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ + uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ + uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ + uint8_t refreshBurstLen; /*!< Refresh burst length. */ +} semc_sdram_config_t; + + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + + +/*! @brief SEMC NAND configuration structure. */ +typedef struct _semc_nand_config +{ + semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ + uint32_t axiAddress; /*!< The base address for AXI nand. */ + uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ + uint32_t ipgAddress; /*!< The base address for IPG nand . */ + uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + bool edoModeEnabled; /*!< EDO mode enabled. */ + semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ + sem_nand_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ +} semc_nand_config_t; + +/*! @brief SEMC NOR configuration structure. */ +typedef struct _semc_nor_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ + semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_nor_config_t; + +/*! @brief SEMC SRAM configuration structure. */ +typedef struct _semc_sram_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_sram_config_t; + +/*! @brief SEMC DBI configuration structure. */ +typedef struct _semc_dbi_config +{ + semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ + semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + sem_dbi_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ + uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ + uint8_t tWexLow_Ns; /*!< WEX low time. */ + uint8_t tWexHigh_Ns; /*!< WEX high time. */ + uint8_t tRdxLow_Ns; /*!< RDX low time. */ + uint8_t tRdxHigh_Ns; /*!< RDX high time. */ + uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ +} semc_dbi_config_t; + +/*! @brief SEMC AXI queue a weight setting. */ +typedef struct _semc_queuea_weight +{ + uint32_t qos : 4; /*!< weight of qos for queue 0 . */ + uint32_t aging : 4; /*!< weight of aging for queue 0.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ + uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ +} semc_queuea_weight_t; + +/*! @brief SEMC AXI queue b weight setting. */ +typedef struct _semc_queueb_weight +{ + uint32_t qos : 4; /*!< weight of qos for queue 1. */ + uint32_t aging : 4; /*!< weight of aging for queue 1.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ + uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ + uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ +} semc_queueb_weight_t; + +/*! @brief SEMC AXI queue weight setting. */ +typedef struct _semc_axi_queueweight +{ + semc_queuea_weight_t *queueaWeight; /*!< Weight settings for queue a. */ + semc_queueb_weight_t *queuebWeight; /*!< Weight settings for queue b. */ +} semc_axi_queueweight_t; + +/*! + * @brief SEMC configuration structure. + * + * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is + * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. + * cmdTimeoutCycles: is used for command execution timeout cycles. it's + * similar to the busTimeoutCycles. + */ +typedef struct _semc_config_t +{ + semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ + uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ + uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ + semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ +} semc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMC Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + @code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + @endcode + * @param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config); + +/*! + * @brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * @param base SEMC peripheral base address. + * @param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure); + +/*! + * @brief Deinitializes the SEMC module and gates the clock. + * This function gates the SEMC clock. As a result, the SEMC + * module doesn't work after calling this function. + * + * @param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base); + +/* @} */ + +/*! + * @name SEMC Configuration Operation For Each Memory Type + * @{ + */ + +/*! + * @brief Configures SDRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param cs The chip selection. + * @param config The sdram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NAND controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nand configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NOR controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nor configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures SRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The sram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures DBI controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The dbi configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); + +/* @} */ + +/*! + * @name SEMC Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the SEMC interrupt. + * + * This function enables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to enable the IP command done and error interrupt, do the following. + * @code + * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to enable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disables the SEMC interrupt. + * + * This function disables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to disable the IP command done and error interrupt, do the following. + * @code + * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to disable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/*! + * @brief Gets the SEMC status. + * + * This function gets the SEMC interrupts event status. + * User can use the a logical OR of enumeration member as a mask. + * See @ref semc_interrupt_enable_t. + * + * @param base SEMC peripheral base address. + * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. + */ +static inline bool SEMC_GetStatusFlag(SEMC_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Clears the SEMC status flag state. + * + * The following status register flags can be cleared SEMC interrupt status. + * + * @param base SEMC base pointer + * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. + */ +static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +/* @} */ + +/*! + * @name SEMC Memory Access Operation + * @{ + */ + +/*! + * @brief Check if SEMC is in idle. + * + * @param base SEMC peripheral base address. + * @return True SEMC is in idle, false is not in idle. + */ +static inline bool SEMC_IsInIdle(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false; +} + +/*! + * @brief SEMC IP command access. + * + * @param base SEMC peripheral base address. + * @param type SEMC memory type. refer to "semc_mem_type_t" + * @param address SEMC device address. + * @param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * @param write Data for write access. + * @param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read); + +/*! + * @brief Build SEMC IP command for NAND. + * + * This function build SEMC NAND IP command. The command is build of user command code, + * SEMC address mode and SEMC command mode. + * + * @param userCommand NAND device normal command. + * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". + * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". + */ +static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, + semc_ipcmd_nand_addrmode_t addrMode, + semc_ipcmd_nand_cmdmode_t cmdMode) +{ + return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu); +} + +/*! + * @brief Check if the NAND device is ready. + * + * @param base SEMC peripheral base address. + * @return True NAND is ready, false NAND is not ready. + */ +static inline bool SEMC_IsNandReady(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false; +} + +/*! + * @brief SEMC NAND device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NAND device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SEMC_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_hp.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_hp.c new file mode 100644 index 0000000000..0e6efab131 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_hp.c @@ -0,0 +1,463 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_snvs_hp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.snvs_hp" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +#if !(defined(SNVS_HPCOMR_SW_SV_MASK)) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#endif +#if !(defined(SNVS_HPSR_PI_MASK)) +#define SNVS_HPSR_PI_MASK (0x2U) +#endif +#if !(defined(SNVS_HPSR_HPTA_MASK)) +#define SNVS_HPSR_HPTA_MASK (0x1U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Returns RTC time in seconds. + * + * This function is used internally to get actual RTC time in seconds. + * + * @param base SNVS peripheral base address + * + * @return RTC time in seconds + */ +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! + * @brief Get the SNVS instance from peripheral base address. + * + * @param base SNVS peripheral base address. + * + * @return SNVS instance. + */ +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! @brief Pointer to snvs_hp clock. */ +const clock_ip_name_t s_snvsHpClock[] = SNVS_HP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base) +{ + return 0U; +} +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) +{ + assert(config); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_EnableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK | SNVS_HPCOMR_SW_SV_MASK; + + base->HPCR = SNVS_HPCR_PI_FREQ(config->periodicInterruptFreq); + + if (config->rtcCalEnable) + { + base->HPCR = SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT); + base->HPCR |= SNVS_HPCR_HPCALB_EN_MASK; + } +} + +void SNVS_HP_RTC_Deinit(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_DisableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) +{ + assert(config); + + config->rtcCalEnable = false; + config->rtcCalValue = 0U; + config->periodicInterruptFreq = 0U; +} + +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) +{ + uint32_t seconds = 0; + uint32_t tmp = 0; + + /* Do consecutive reads until value is correct */ + do + { + seconds = tmp; + tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); + } while (tmp != seconds); + + return seconds; +} + +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0U; + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + /* Return error if the time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + seconds = SNVS_HP_ConvertDatetimeToSeconds(datetime); + + base->HPRTCMR = (uint32_t)(seconds >> 17U); + base->HPRTCLR = (uint32_t)(seconds << 15U); + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } + + return kStatus_Success; +} + +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime); +} + +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0U; + uint32_t currSeconds = 0U; + uint32_t tmp = base->HPCR; + + /* Return error if the alarm time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime); + currSeconds = SNVS_HP_RTC_GetSeconds(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* disable RTC alarm interrupt */ + base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; + while (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + } + + /* Set alarm in seconds*/ + base->HPTAMR = (uint32_t)(alarmSeconds >> 17U); + base->HPTALR = (uint32_t)(alarmSeconds << 15U); + + /* reenable RTC alarm interrupt in case that it was enabled before */ + base->HPCR = tmp; + + return kStatus_Success; +} + +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0U; + + /* Get alarm in seconds */ + alarmSeconds = (base->HPTAMR << 17U) | (base->HPTALR >> 15U); + + SNVS_HP_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) +{ + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + base->HPCR |= SNVS_HPCR_HP_TS_MASK; + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } +} +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) +{ + uint32_t flags = 0U; + + if (base->HPSR & SNVS_HPSR_PI_MASK) + { + flags |= kSNVS_RTC_PeriodicInterruptFlag; + } + + if (base->HPSR & SNVS_HPSR_HPTA_MASK) + { + flags |= kSNVS_RTC_AlarmInterruptFlag; + } + + return flags; +} + +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) +{ + uint32_t val = 0U; + + if (base->HPCR & SNVS_HPCR_PI_EN_MASK) + { + val |= kSNVS_RTC_PeriodicInterrupt; + } + + if (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + val |= kSNVS_RTC_AlarmInterrupt; + } + + return val; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_hp.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_hp.h new file mode 100644 index 0000000000..27bf7e6625 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_hp.h @@ -0,0 +1,309 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SNVS_HP_H_ +#define _FSL_SNVS_HP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup snvs_hp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of SNVS interrupts */ +typedef enum _snvs_hp_interrupts +{ + kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */ + kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */ +} snvs_hp_interrupts_t; + +/*! @brief List of SNVS flags */ +typedef enum _snvs_hp_status_flags +{ + kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ + kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ +} snvs_hp_status_flags_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _snvs_hp_rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} snvs_hp_rtc_datetime_t; + +/*! + * @brief SNVS config structure + * + * This structure holds the configuration settings for the SNVS peripheral. To initialize this + * structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _snvs_hp_rtc_config +{ + bool rtcCalEnable; /*!< true: RTC calibration mechanism is enabled; + false:No calibration is used */ + uint32_t rtcCalValue; /*!< Defines signed calibration value for nonsecure RTC; + This is a 5-bit 2's complement value, range from -16 to +15 */ + uint32_t periodicInterruptFreq; /*!< Defines frequency of the periodic interrupt; + Range from 0 to 15 */ +} snvs_hp_rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config); + +/*! + * @brief Stops the RTC and SRTC timers. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_Deinit(SNVS_Type *base); + +/*! + * @brief Fills in the SNVS config struct with the default settings. + * + * The default values are as follows. + * @code + * config->rtccalenable = false; + * config->rtccalvalue = 0U; + * config->PIFreq = 0U; + * @endcode + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Non secure RTC current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the SNVS RTC date and time according to the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the SNVS RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Gets the SNVS RTC time and stores it in the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Sets the SNVS RTC alarm time. + * + * The function sets the RTC alarm. It also checks whether the specified alarm time + * is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * + * @param base SNVS peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the SNVS RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the SNVS RTC alarm time. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +/*! + * @brief The function synchronizes RTC counter value with SRTC. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base); +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->HPCR |= mask; +} + +/*! + * @brief Disables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->HPCR &= ~mask; +} + +/*! + * @brief Gets the enabled SNVS interrupts. + * + * @param base SNVS peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SNVS status flags. + * + * @param base SNVS peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base); + +/*! + * @brief Clears the SNVS status flags. + * + * @param base SNVS peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +static inline void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->HPSR |= mask; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base) +{ + base->HPCR |= SNVS_HPCR_RTC_EN_MASK; + while (!(base->HPCR & SNVS_HPCR_RTC_EN_MASK)) + { + } +} + +/*! + * @brief Stops the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + while (base->HPCR & SNVS_HPCR_RTC_EN_MASK) + { + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SNVS_HP_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_lp.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_lp.c new file mode 100644 index 0000000000..c9f539630e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_lp.c @@ -0,0 +1,609 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_snvs_lp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.snvs_lp" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool SNVS_LP_CheckDatetimeFormat(const snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t SNVS_LP_ConvertDatetimeToSeconds(const snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Returns SRTC time in seconds. + * + * This function is used internally to get actual SRTC time in seconds. + * + * @param base SNVS peripheral base address + * + * @return SRTC time in seconds + */ +static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) +/*! + * @brief Get the SNVS instance from peripheral base address. + * + * @param base SNVS peripheral base address. + * + * @return SNVS instance. + */ +static uint32_t SNVS_LP_GetInstance(SNVS_Type *base); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) +/*! @brief Pointer to snvs_lp clock. */ +const clock_ip_name_t s_snvsLpClock[] = SNVS_LP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SNVS_LP_CheckDatetimeFormat(const snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t SNVS_LP_ConvertDatetimeToSeconds(const snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) +static uint32_t SNVS_LP_GetInstance(SNVS_Type *base) +{ + return 0U; +} +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config) +{ + assert(config); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) + uint32_t instance = SNVS_LP_GetInstance(base); + CLOCK_EnableClock(s_snvsLpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + int pin; + + if (config->srtcCalEnable) + { + base->LPCR = SNVS_LPCR_LPCALB_VAL_MASK & (config->srtcCalValue << SNVS_LPCR_LPCALB_VAL_SHIFT); + base->LPCR |= SNVS_LPCR_LPCALB_EN_MASK; + } + + for (pin = kSNVS_ExternalTamper1; pin <= SNVS_LP_MAX_TAMPER; pin++) + { + SNVS_LP_DisableExternalTamper(SNVS, (snvs_lp_external_tamper_t)pin); + SNVS_LP_ClearExternalTamperStatus(SNVS, (snvs_lp_external_tamper_t)pin); + } +} + +void SNVS_LP_SRTC_Deinit(SNVS_Type *base) +{ + base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) + uint32_t instance = SNVS_LP_GetInstance(base); + CLOCK_DisableClock(s_snvsLpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config) +{ + assert(config); + + config->srtcCalEnable = false; + config->srtcCalValue = 0U; +} + +static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base) +{ + uint32_t seconds = 0; + uint32_t tmp = 0; + + /* Do consecutive reads until value is correct */ + do + { + seconds = tmp; + tmp = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U); + } while (tmp != seconds); + + return seconds; +} + +status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0U; + uint32_t tmp = base->LPCR; + + /* disable RTC */ + SNVS_LP_SRTC_StopTimer(base); + + /* Return error if the time provided is not valid */ + if (!(SNVS_LP_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + seconds = SNVS_LP_ConvertDatetimeToSeconds(datetime); + + base->LPSRTCMR = (uint32_t)(seconds >> 17U); + base->LPSRTCLR = (uint32_t)(seconds << 15U); + + /* reenable SRTC in case that it was enabled before */ + if (tmp & SNVS_LPCR_SRTC_ENV_MASK) + { + SNVS_LP_SRTC_StartTimer(base); + } + + return kStatus_Success; +} + +void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + SNVS_LP_ConvertSecondsToDatetime(SNVS_LP_SRTC_GetSeconds(base), datetime); +} + +status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0U; + uint32_t currSeconds = 0U; + uint32_t tmp = base->LPCR; + + /* Return error if the alarm time provided is not valid */ + if (!(SNVS_LP_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = SNVS_LP_ConvertDatetimeToSeconds(alarmTime); + currSeconds = SNVS_LP_SRTC_GetSeconds(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds <= currSeconds) + { + return kStatus_Fail; + } + + /* disable SRTC alarm interrupt */ + base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK; + while (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) + { + } + + /* Set alarm in seconds*/ + base->LPTAR = alarmSeconds; + + /* reenable SRTC alarm interrupt in case that it was enabled before */ + base->LPCR = tmp; + + return kStatus_Success; +} + +void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0U; + + /* Get alarm in seconds */ + alarmSeconds = base->LPTAR; + + SNVS_LP_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base) +{ + uint32_t flags = 0U; + + if (base->LPSR & SNVS_LPSR_LPTA_MASK) + { + flags |= kSNVS_SRTC_AlarmInterruptFlag; + } + + return flags; +} + +uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base) +{ + uint32_t val = 0U; + + if (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) + { + val |= kSNVS_SRTC_AlarmInterrupt; + } + + return val; +} + +void SNVS_LP_EnableExternalTamper(SNVS_Type *base, + snvs_lp_external_tamper_t pin, + snvs_lp_external_tamper_polarity_t polarity) +{ + switch (pin) + { + case (kSNVS_ExternalTamper1): + base->LPTDCR = (base->LPTDCR & ~(1U << SNVS_LPTDCR_ET1P_SHIFT)) | (polarity << SNVS_LPTDCR_ET1P_SHIFT); + base->LPTDCR |= SNVS_LPTDCR_ET1_EN_MASK; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + base->LPTDCR = (base->LPTDCR & ~(1U << SNVS_LPTDCR_ET2P_SHIFT)) | (polarity << SNVS_LPTDCR_ET2P_SHIFT); + base->LPTDCR |= SNVS_LPTDCR_ET2_EN_MASK; + break; + case (kSNVS_ExternalTamper3): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET3P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET3P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET3_EN_MASK; + break; + case (kSNVS_ExternalTamper4): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET4P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET4P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET4_EN_MASK; + break; + case (kSNVS_ExternalTamper5): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET5P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET5P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET5_EN_MASK; + break; + case (kSNVS_ExternalTamper6): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET6P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET6P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET6_EN_MASK; + break; + case (kSNVS_ExternalTamper7): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET7P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET7P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET7_EN_MASK; + break; + case (kSNVS_ExternalTamper8): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET8P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET8P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET8_EN_MASK; + break; + case (kSNVS_ExternalTamper9): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET9P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET9P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET9_EN_MASK; + break; + case (kSNVS_ExternalTamper10): + base->LPTDC2R = + (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET10P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET10P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET10_EN_MASK; + break; +#endif + default: + break; + } +} + +void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin) +{ + switch (pin) + { + case (kSNVS_ExternalTamper1): + base->LPTDCR &= ~SNVS_LPTDCR_ET1_EN_MASK; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + base->LPTDCR &= ~SNVS_LPTDCR_ET2_EN_MASK; + break; + case (kSNVS_ExternalTamper3): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET3_EN_MASK; + break; + case (kSNVS_ExternalTamper4): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET4_EN_MASK; + break; + case (kSNVS_ExternalTamper5): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET5_EN_MASK; + break; + case (kSNVS_ExternalTamper6): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET6_EN_MASK; + break; + case (kSNVS_ExternalTamper7): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET7_EN_MASK; + break; + case (kSNVS_ExternalTamper8): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET8_EN_MASK; + break; + case (kSNVS_ExternalTamper9): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET9_EN_MASK; + break; + case (kSNVS_ExternalTamper10): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET10_EN_MASK; + break; +#endif + default: + break; + } +} + +snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) +{ + snvs_lp_external_tamper_status_t status = kSNVS_TamperNotDetected; + + switch (pin) + { + case (kSNVS_ExternalTamper1): + status = (base->LPSR & SNVS_LPSR_ET1D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + status = (base->LPSR & SNVS_LPSR_ET2D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper3): + status = (base->LPTDSR & SNVS_LPTDSR_ET3D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper4): + status = (base->LPTDSR & SNVS_LPTDSR_ET4D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper5): + status = (base->LPTDSR & SNVS_LPTDSR_ET5D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper6): + status = (base->LPTDSR & SNVS_LPTDSR_ET6D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper7): + status = (base->LPTDSR & SNVS_LPTDSR_ET7D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper8): + status = (base->LPTDSR & SNVS_LPTDSR_ET8D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper9): + status = (base->LPTDSR & SNVS_LPTDSR_ET9D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper10): + status = (base->LPTDSR & SNVS_LPTDSR_ET10D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; +#endif + default: + break; + } + return status; +} + +void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) +{ + base->LPSR |= SNVS_LPSR_ET1D_MASK; + + switch (pin) + { + case (kSNVS_ExternalTamper1): + base->LPSR |= SNVS_LPSR_ET1D_MASK; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + base->LPSR |= SNVS_LPSR_ET2D_MASK; + break; + case (kSNVS_ExternalTamper3): + base->LPTDSR |= SNVS_LPTDSR_ET3D_MASK; + break; + case (kSNVS_ExternalTamper4): + base->LPTDSR |= SNVS_LPTDSR_ET4D_MASK; + break; + case (kSNVS_ExternalTamper5): + base->LPTDSR |= SNVS_LPTDSR_ET5D_MASK; + break; + case (kSNVS_ExternalTamper6): + base->LPTDSR |= SNVS_LPTDSR_ET6D_MASK; + break; + case (kSNVS_ExternalTamper7): + base->LPTDSR |= SNVS_LPTDSR_ET7D_MASK; + break; + case (kSNVS_ExternalTamper8): + base->LPTDSR |= SNVS_LPTDSR_ET8D_MASK; + break; + case (kSNVS_ExternalTamper9): + base->LPTDSR |= SNVS_LPTDSR_ET9D_MASK; + break; + case (kSNVS_ExternalTamper10): + base->LPTDSR |= SNVS_LPTDSR_ET10D_MASK; + break; +#endif + default: + break; + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_lp.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_lp.h new file mode 100644 index 0000000000..bd61d52ddb --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_snvs_lp.h @@ -0,0 +1,381 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SNVS_LP_H_ +#define _FSL_SNVS_LP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup snvs_lp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of SNVS_LP interrupts */ +typedef enum _snvs_lp_srtc_interrupts +{ + kSNVS_SRTC_AlarmInterrupt = SNVS_LPCR_LPTA_EN_MASK, /*!< SRTC time alarm.*/ +} snvs_lp_srtc_interrupts_t; + +/*! @brief List of SNVS_LP flags */ +typedef enum _snvs_lp_srtc_status_flags +{ + kSNVS_SRTC_AlarmInterruptFlag = SNVS_LPSR_LPTA_MASK, /*!< SRTC time alarm flag */ +} snvs_lp_srtc_status_flags_t; + +/*! @brief List of SNVS_LP external tampers */ +typedef enum _snvs_lp_external_tamper +{ + kSNVS_ExternalTamper1 = 1U, +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + kSNVS_ExternalTamper2 = 2U, + kSNVS_ExternalTamper3 = 3U, + kSNVS_ExternalTamper4 = 4U, + kSNVS_ExternalTamper5 = 5U, + kSNVS_ExternalTamper6 = 6U, + kSNVS_ExternalTamper7 = 7U, + kSNVS_ExternalTamper8 = 8U, + kSNVS_ExternalTamper9 = 9U, + kSNVS_ExternalTamper10 = 10U +#endif +} snvs_lp_external_tamper_t; + +/* define max possible tamper present */ +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) +#define SNVS_LP_MAX_TAMPER kSNVS_ExternalTamper10 +#else +#define SNVS_LP_MAX_TAMPER kSNVS_ExternalTamper1 +#endif + +/*! @brief List of SNVS_LP external tampers status */ +typedef enum _snvs_lp_external_tamper_status +{ + kSNVS_TamperNotDetected = 0U, + kSNVS_TamperDetected = 1U +} snvs_lp_external_tamper_status_t; + +/*! @brief SNVS_LP external tamper polarity */ +typedef enum _snvs_lp_external_tamper_polarity +{ + kSNVS_ExternalTamperActiveLow = 0U, + kSNVS_ExternalTamperActiveHigh = 1U +} snvs_lp_external_tamper_polarity_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _snvs_lp_srtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} snvs_lp_srtc_datetime_t; + +/*! + * @brief SNVS_LP config structure + * + * This structure holds the configuration settings for the SNVS_LP peripheral. To initialize this + * structure to reasonable defaults, call the SNVS_LP_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _snvs_lp_srtc_config +{ + bool srtcCalEnable; /*!< true: SRTC calibration mechanism is enabled; + false: No calibration is used */ + uint32_t srtcCalValue; /*!< Defines signed calibration value for SRTC; + This is a 5-bit 2's complement value, range from -16 to +15 */ +} snvs_lp_srtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config); + +/*! + * @brief Stops the SRTC timer. + * + * @param base SNVS peripheral base address + */ +void SNVS_LP_SRTC_Deinit(SNVS_Type *base); + +/*! + * @brief Fills in the SNVS_LP config struct with the default settings. + * + * The default values are as follows. + * @code + * config->srtccalenable = false; + * config->srtccalvalue = 0U; + * @endcode + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config); + +/*! @}*/ + +/*! + * @name Secure RTC (SRTC) current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the SNVS SRTC date and time according to the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the SNVS SRTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Gets the SNVS SRTC time and stores it in the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Sets the SNVS SRTC alarm time. + * + * The function sets the SRTC alarm. It also checks whether the specified alarm + * time is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * Please note, that SRTC alarm has limited resolution because only 32 most + * significant bits of SRTC counter are compared to SRTC Alarm register. + * If the alarm time is beyond SRTC resolution, the function does not set the alarm + * and returns an error. + * + * @param base SNVS peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the SNVS SRTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed or is beyond resolution + */ +status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime); + +/*! + * @brief Returns the SNVS SRTC alarm time. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->LPCR |= mask; +} + +/*! + * @brief Disables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->LPCR &= ~mask; +} + +/*! + * @brief Gets the enabled SNVS interrupts. + * + * @param base SNVS peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SNVS status flags. + * + * @param base SNVS peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base); + +/*! + * @brief Clears the SNVS status flags. + * + * @param base SNVS peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +static inline void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->LPSR |= mask; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the SNVS SRTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_LP_SRTC_StartTimer(SNVS_Type *base) +{ + base->LPCR |= SNVS_LPCR_SRTC_ENV_MASK; + while (!(base->LPCR & SNVS_LPCR_SRTC_ENV_MASK)) + { + } +} + +/*! + * @brief Stops the SNVS SRTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_LP_SRTC_StopTimer(SNVS_Type *base) +{ + base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; + while (base->LPCR & SNVS_LPCR_SRTC_ENV_MASK) + { + } +} + +/*! @}*/ + +/*! + * @name External tampering + * @{ + */ + +/*! + * @brief Enables the specified SNVS external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + * @param polarity Polarity of external tamper + */ +void SNVS_LP_EnableExternalTamper(SNVS_Type *base, + snvs_lp_external_tamper_t pin, + snvs_lp_external_tamper_polarity_t polarity); + +/*! + * @brief Disables the specified SNVS external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + */ +void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin); + +/*! + * @brief Returns status of the specified external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + * + * @return The status flag. This is the enumeration ::snvs_external_tamper_status_t + */ +snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin); + +/*! + * @brief Clears status of the specified external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + */ +void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SNVS_LP_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif.c new file mode 100644 index 0000000000..80b3229e20 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif.c @@ -0,0 +1,678 @@ +/* + * The Clear BSD License + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spdif.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.spdif" +#endif + + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _spdif_transfer_state +{ + kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */ + kSPDIF_Idle, /*!< Transfer is done. */ + kSPDIF_Error /*!< Transfer error occured. */ +}; + +/*! @brief Typedef for spdif tx interrupt handler. */ +typedef void (*spdif_isr_t)(SPDIF_Type *base, spdif_handle_t *handle); +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the instance number for SPDIF. + * + * @param base SPDIF base pointer. + */ +uint32_t SPDIF_GetInstance(SPDIF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static SPDIF_Type *const s_spdifBases[] = SPDIF_BASE_PTRS; +/*! @brief SPDIF handle pointer */ +spdif_handle_t *s_spdifHandle[ARRAY_SIZE(s_spdifBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_spdifIRQ[] = SPDIF_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_spdifClock[] = SPDIF_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to IRQ handler for each instance. */ +static spdif_isr_t s_spdifTxIsr; +/*! @brief Pointer to IRQ handler for each instance. */ +static spdif_isr_t s_spdifRxIsr; +/*! @brief Used for spdif gain */ +static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U}; +static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4}; +static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16}; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t SPDIF_GetInstance(SPDIF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_spdifBases); instance++) + { + if (s_spdifBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_spdifBases)); + + return instance; +} + +void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SPDIF clock */ + CLOCK_EnableClock(s_spdifClock[SPDIF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the internal logic */ + base->SCR |= SPDIF_SCR_SOFT_RESET_MASK; + + /* Waiting for reset finish */ + while (base->SCR & SPDIF_SCR_SOFT_RESET_MASK) + { + } + + /* Setting the SPDIF settings */ + base->SCR = SPDIF_SCR_RXFIFOFULL_SEL(config->rxFullSelect) | SPDIF_SCR_RXAUTOSYNC(config->isRxAutoSync) | + SPDIF_SCR_TXAUTOSYNC(config->isRxAutoSync) | SPDIF_SCR_TXFIFOEMPTY_SEL(config->txFullSelect) | + SPDIF_SCR_TXFIFO_CTRL(1U) | SPDIF_SCR_VALCTRL(config->validityConfig) | + SPDIF_SCR_TXSEL(config->txSource) | SPDIF_SCR_USRC_SEL(config->uChannelSrc); + + /* Set DPLL clock source */ + base->SRPC = SPDIF_SRPC_CLKSRC_SEL(config->DPLLClkSource) | SPDIF_SRPC_GAINSEL(config->gain); + + /* Set SPDIF tx clock source */ + val = base->STC & ~SPDIF_STC_TXCLK_SOURCE_MASK; + val |= SPDIF_STC_TXCLK_SOURCE(config->txClkSource); + base->STC = val; +} + +void SPDIF_Deinit(SPDIF_Type *base) +{ + SPDIF_TxEnable(base, false); + SPDIF_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_spdifClock[SPDIF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SPDIF_GetDefaultConfig(spdif_config_t *config) +{ + config->isTxAutoSync = true; + config->isRxAutoSync = true; + config->DPLLClkSource = 1; + config->txClkSource = 1; + config->rxFullSelect = kSPDIF_RxFull8Samples; + config->txFullSelect = kSPDIF_TxEmpty8Samples; + config->uChannelSrc = kSPDIF_UChannelFromTx; + config->txSource = kSPDIF_txNormal; + config->validityConfig = kSPDIF_validityFlagAlwaysClear; + config->gain = kSPDIF_GAIN_8; +} + +void SPDIF_TxEnable(SPDIF_Type *base, bool enable) +{ + uint32_t val = 0; + + if (enable) + { + /* Open Tx FIFO */ + val = base->SCR & (~SPDIF_SCR_TXFIFO_CTRL_MASK); + val |= SPDIF_SCR_TXFIFO_CTRL(1U); + base->SCR = val; + /* Enable transfer clock */ + base->STC |= SPDIF_STC_TX_ALL_CLK_EN_MASK; + } + else + { + base->SCR &= ~(SPDIF_SCR_TXFIFO_CTRL_MASK | SPDIF_SCR_TXSEL_MASK); + /* Disable transfer clock */ + base->STC &= ~SPDIF_STC_TX_ALL_CLK_EN_MASK; + } +} + +void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz) +{ + uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64); + uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64); + uint32_t val = 0; + uint8_t clockSource = (((base->STC) & SPDIF_STC_TXCLK_SOURCE_MASK) >> SPDIF_STC_TXCLK_SOURCE_SHIFT); + + /* Compute the nearest divider */ + if (mod > ((sampleRate_Hz * 64) / 2)) + { + clkDiv += 1U; + } + + /* If use divided systeme clock */ + if (clockSource == 5U) + { + if (clkDiv > 256) + { + val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); + val |= SPDIF_STC_SYSCLK_DF(clkDiv / 128U - 1U) | SPDIF_STC_TXCLK_DF(127U); + base->STC = val; + } + else + { + val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); + val |= SPDIF_STC_SYSCLK_DF(1U) | SPDIF_STC_TXCLK_DF(clkDiv - 1U); + base->STC = val; + } + } + else + { + /* Other clock only uses txclk div */ + val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); + val |= SPDIF_STC_TXCLK_DF(clkDiv - 1U); + base->STC = val; + } +} + +uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) +{ + uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)]; + uint32_t measure = 0, sampleRate = 0; + uint64_t temp = 0; + + /* Wait the DPLL locked */ + while ((base->SRPC & SPDIF_SRPC_LOCK_MASK) == 0U) + { + } + + /* Get the measure value */ + measure = base->SRFM; + temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz; + temp /= (uint64_t)(1024 * 1024 * 128 * gain); + sampleRate = (uint32_t)temp; + + return sampleRate; +} + +void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) +{ + assert(buffer); + assert(size / 6U == 0U); + + uint32_t i = 0, j = 0, data = 0; + + while (i < size) + { + /* Wait until it can write data */ + while ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) == 0U) + { + } + + /* Write left channel data */ + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteLeftData(base, data); + + /* Write right channel data */ + data = 0; + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteRightData(base, data); + + i += 6U; + } +} + +void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) +{ + assert(buffer); + assert(size / 6U == 0U); + + uint32_t i = 0, j = 0, data = 0; + + while (i < size) + { + /* Wait until it can write data */ + while ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) == 0U) + { + } + + /* Write left channel data */ + data = SPDIF_ReadLeftData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + /* Write right channel data */ + data = SPDIF_ReadRightData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + i += 6U; + } +} + +void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_spdifHandle[SPDIF_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->watermark = + s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; + + /* Set the isr pointer */ + s_spdifTxIsr = SPDIF_TransferTxHandleIRQ; + + /* Enable Tx irq */ + EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); +} + +void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_spdifHandle[SPDIF_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->watermark = + s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; + + /* Set the isr pointer */ + s_spdifRxIsr = SPDIF_TransferRxHandleIRQ; + + /* Enable Rx irq */ + EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); +} + +status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->spdifQueue[handle->queueUser].data) + { + return kStatus_SPDIF_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].data = xfer->data; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSPDIF_Busy; + + /* Enable interrupt */ + SPDIF_EnableInterrupts(base, kSPDIF_TxFIFOEmpty); + + /* Enable Tx transfer */ + SPDIF_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->spdifQueue[handle->queueUser].data) + { + return kStatus_SPDIF_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].data = xfer->data; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->spdifQueue[handle->queueUser].udata = xfer->udata; + handle->spdifQueue[handle->queueUser].qdata = xfer->qdata; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSPDIF_Busy; + + /* Enable interrupt */ + SPDIF_EnableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull | + kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange); + + /* Enable Rx transfer */ + SPDIF_RxEnable(base, true); + + return kStatus_Success; +} + +status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize); + } + + return status; +} + +void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + /* Use FIFO request interrupt and fifo error */ + SPDIF_DisableInterrupts(base, kSPDIF_TxFIFOEmpty); + + handle->state = kSPDIF_Idle; + + /* Clear the queue */ + memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt */ + SPDIF_DisableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull | + kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange); + + handle->state = kSPDIF_Idle; + + /* Clear the queue */ + memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data; + uint8_t dataSize = 0; + uint32_t i = 0, j = 0, data = 0; + + /* Do Transfer */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) && (base->SIE & kSPDIF_TxFIFOEmpty)) + { + dataSize = handle->watermark; + while (i < dataSize) + { + data = 0; + /* Write left channel data */ + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteLeftData(base, data); + + /* Write right channel data */ + data = 0; + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteRightData(base, data); + + i++; + } + handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; + handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; + + /* If finished a blcok, call the callback function */ + if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->spdifQueue[handle->queueDriver].data == NULL) + { + SPDIF_TransferAbortSend(base, handle); + } + } +} + +void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = NULL; + uint8_t dataSize = 0; + uint32_t i = 0, j = 0, data = 0; + + /* Handle Cnew flag */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxControlChannelChange) + { + /* Clear the interrupt flag */ + SPDIF_ClearStatusFlags(base, SPDIF_SIE_CNEW_MASK); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxCnew, handle->userData); + } + } + + /* Handle illegal symbol */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxIllegalSymbol) + { + SPDIF_ClearStatusFlags(base, kSPDIF_RxIllegalSymbol); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxIllegalSymbol, handle->userData); + } + } + + /* Handle Parity Bit Error */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxParityBitError) + { + SPDIF_ClearStatusFlags(base, kSPDIF_RxParityBitError); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxParityBitError, handle->userData); + } + } + + /* Handle DPlocked */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxDPLLLocked) + { + SPDIF_ClearStatusFlags(base, kSPDIF_RxDPLLLocked); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxDPLLLocked, handle->userData); + } + } + + /* Handle Q channel full flag */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_QChannelReceiveRegisterFull) && + (base->SIE & kSPDIF_QChannelReceiveRegisterFull)) + { + buffer = handle->spdifQueue[handle->queueDriver].qdata; + data = SPDIF_ReadQChannel(base); + buffer[0] = data & 0xFFU; + buffer[1] = (data >> 8U) & 0xFFU; + buffer[2] = (data >> 16U) & 0xFFU; + } + + /* Handle U channel full flag */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_UChannelReceiveRegisterFull) && + (base->SIE & kSPDIF_UChannelReceiveRegisterFull)) + { + buffer = handle->spdifQueue[handle->queueDriver].udata; + data = SPDIF_ReadUChannel(base); + buffer[0] = data & 0xFFU; + buffer[1] = (data >> 8U) & 0xFFU; + buffer[2] = (data >> 16U) & 0xFFU; + } + + /* Handle audio data transfer */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) && (base->SIE & kSPDIF_RxFIFOFull)) + { + dataSize = handle->watermark; + buffer = handle->spdifQueue[handle->queueDriver].data; + while (i < dataSize) + { + /* Read left channel data */ + data = SPDIF_ReadLeftData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + /* Read right channel data */ + data = SPDIF_ReadRightData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + i++; + } + handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; + handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; + + /* If finished a blcok, call the callback function */ + if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->spdifQueue[handle->queueDriver].data == NULL) + { + SPDIF_TransferAbortReceive(base, handle); + } + } +} + +#if defined(SPDIF) +void SPDIF_DriverIRQHandler(void) +{ + if ((s_spdifHandle[0][0]) && s_spdifTxIsr) + { + s_spdifTxIsr(SPDIF, s_spdifHandle[0][0]); + } + + if ((s_spdifHandle[0][1]) && s_spdifRxIsr) + { + s_spdifRxIsr(SPDIF, s_spdifHandle[0][1]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif.h new file mode 100644 index 0000000000..ce852af544 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif.h @@ -0,0 +1,767 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SPDIF_H_ +#define _FSL_SPDIF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup spdif + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SPDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief SPDIF return status*/ +enum _spdif_status_t +{ + kStatus_SPDIF_RxDPLLLocked = MAKE_STATUS(kStatusGroup_SPDIF, 0), /*!< SPDIF Rx PLL locked. */ + kStatus_SPDIF_TxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 1), /*!< SPDIF Tx FIFO error. */ + kStatus_SPDIF_TxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 2), /*!< SPDIF Tx left and right FIFO resync. */ + kStatus_SPDIF_RxCnew = MAKE_STATUS(kStatusGroup_SPDIF, 3), /*!< SPDIF Rx status channel value updated. */ + kStatus_SPDIF_ValidatyNoGood = MAKE_STATUS(kStatusGroup_SPDIF, 4), /*!< SPDIF validaty flag not good. */ + kStatus_SPDIF_RxIllegalSymbol = MAKE_STATUS(kStatusGroup_SPDIF, 5), /*!< SPDIF Rx receive illegal symbol. */ + kStatus_SPDIF_RxParityBitError = MAKE_STATUS(kStatusGroup_SPDIF, 6), /*!< SPDIF Rx parity bit error. */ + kStatus_SPDIF_UChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 7), /*!< SPDIF receive U channel overrun. */ + kStatus_SPDIF_QChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 8), /*!< SPDIF receive Q channel overrun. */ + kStatus_SPDIF_UQChannelSync = MAKE_STATUS(kStatusGroup_SPDIF, 9), /*!< SPDIF U/Q channel sync found. */ + kStatus_SPDIF_UQChannelFrameError = MAKE_STATUS(kStatusGroup_SPDIF, 10), /*!< SPDIF U/Q channel frame error. */ + kStatus_SPDIF_RxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 11), /*!< SPDIF Rx FIFO error. */ + kStatus_SPDIF_RxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 12), /*!< SPDIF Rx left and right FIFO resync. */ + kStatus_SPDIF_LockLoss = MAKE_STATUS(kStatusGroup_SPDIF, 13), /*!< SPDIF Rx PLL clock lock loss. */ + kStatus_SPDIF_TxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 14), /*!< SPDIF Tx is idle */ + kStatus_SPDIF_RxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 15), /*!< SPDIF Rx is idle */ + kStatus_SPDIF_QueueFull = MAKE_STATUS(kStatusGroup_SPDIF, 16) /*!< SPDIF queue full */ +}; + +/*! @brief SPDIF Rx FIFO full falg select, it decides when assert the rx full flag */ +typedef enum _spdif_rxfull_select +{ + kSPDIF_RxFull1Sample = 0x0u, /*!< Rx full at least 1 sample in left and right FIFO */ + kSPDIF_RxFull4Samples, /*!< Rx full at least 4 sample in left and right FIFO*/ + kSPDIF_RxFull8Samples, /*!< Rx full at least 8 sample in left and right FIFO*/ + kSPDIF_RxFull16Samples, /*!< Rx full at least 16 sample in left and right FIFO*/ +} spdif_rxfull_select_t; + +/*! @brief SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag */ +typedef enum _spdif_txempty_select +{ + kSPDIF_TxEmpty0Sample = 0x0u, /*!< Tx empty at most 0 sample in left and right FIFO */ + kSPDIF_TxEmpty4Samples, /*!< Tx empty at most 4 sample in left and right FIFO*/ + kSPDIF_TxEmpty8Samples, /*!< Tx empty at most 8 sample in left and right FIFO*/ + kSPDIF_TxEmpty12Samples, /*!< Tx empty at most 12 sample in left and right FIFO*/ +} spdif_txempty_select_t; + +/*! @brief SPDIF U channel source */ +typedef enum _spdif_uchannel_source +{ + kSPDIF_NoUChannel = 0x0U, /*!< No embedded U channel */ + kSPDIF_UChannelFromRx = 0x1U, /*!< U channel from receiver, it is CD mode */ + kSPDIF_UChannelFromTx = 0x3U, /*!< U channel from on chip tx */ +} spdif_uchannel_source_t; + +/*! @brief SPDIF clock gain*/ +typedef enum _spdif_gain_select +{ + kSPDIF_GAIN_24 = 0x0U, /*!< Gain select is 24 */ + kSPDIF_GAIN_16, /*!< Gain select is 16 */ + kSPDIF_GAIN_12, /*!< Gain select is 12 */ + kSPDIF_GAIN_8, /*!< Gain select is 8 */ + kSPDIF_GAIN_6, /*!< Gain select is 6 */ + kSPDIF_GAIN_4, /*!< Gain select is 4 */ + kSPDIF_GAIN_3, /*!< Gain select is 3 */ +} spdif_gain_select_t; + +/*! @brief SPDIF tx data source */ +typedef enum _spdif_tx_source +{ + kSPDIF_txFromReceiver = 0x1U, /*!< Tx data directly through SPDIF receiver */ + kSPDIF_txNormal = 0x5U, /*!< Normal operation, data from processor */ +} spdif_tx_source_t; + +/*! @brief SPDIF tx data source */ +typedef enum _spdif_validity_config +{ + kSPDIF_validityFlagAlwaysSet = 0x0U, /*!< Outgoing validity flags always set */ + kSPDIF_validityFlagAlwaysClear, /*!< Outgoing validity flags always clear */ +} spdif_validity_config_t; + +/*! @brief The SPDIF interrupt enable flag */ +enum _spdif_interrupt_enable_t +{ + kSPDIF_RxDPLLLocked = SPDIF_SIE_LOCK_MASK, /*!< SPDIF DPLL locked */ + kSPDIF_TxFIFOError = SPDIF_SIE_TXUNOV_MASK, /*!< Tx FIFO underrun or overrun */ + kSPDIF_TxFIFOResync = SPDIF_SIE_TXRESYN_MASK, /*!< Tx FIFO left and right channel resync */ + kSPDIF_RxControlChannelChange = SPDIF_SIE_CNEW_MASK, /*!< SPDIF Rx control channel value changed */ + kSPDIF_ValidityFlagNoGood = SPDIF_SIE_VALNOGOOD_MASK, /*!< SPDIF validity flag no good */ + kSPDIF_RxIllegalSymbol = SPDIF_SIE_SYMERR_MASK, /*!< SPDIF receiver found illegal symbol */ + kSPDIF_RxParityBitError = SPDIF_SIE_BITERR_MASK, /*!< SPDIF receiver found parity bit error */ + kSPDIF_UChannelReceiveRegisterFull = SPDIF_SIE_URXFUL_MASK, /*!< SPDIF U channel revceive register full */ + kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK, /*!< SPDIF U channel receive register overrun */ + kSPDIF_QChannelReceiveRegisterFull = SPDIF_SIE_QRXFUL_MASK, /*!< SPDIF Q channel receive reigster full */ + kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK, /*!< SPDIF Q channel receive register overrun */ + kSPDIF_UQChannelSync = SPDIF_SIE_UQSYNC_MASK, /*!< SPDIF U/Q channel sync found */ + kSPDIF_UQChannelFrameError = SPDIF_SIE_UQERR_MASK, /*!< SPDIF U/Q channel frame error */ + kSPDIF_RxFIFOError = SPDIF_SIE_RXFIFOUNOV_MASK, /*!< SPDIF Rx FIFO underrun/overrun */ + kSPDIF_RxFIFOResync = SPDIF_SIE_RXFIFORESYN_MASK, /*!< SPDIF Rx left and right FIFO resync */ + kSPDIF_LockLoss = SPDIF_SIE_LOCKLOSS_MASK, /*!< SPDIF receiver loss of lock */ + kSPDIF_TxFIFOEmpty = SPDIF_SIE_TXEM_MASK, /*!< SPDIF Tx FIFO empty */ + kSPDIF_RxFIFOFull = SPDIF_SIE_RXFIFOFUL_MASK /*!< SPDIF Rx FIFO full */ +}; + +/*! @brief The DMA request sources */ +enum _spdif_dma_enable_t +{ + kSPDIF_RxDMAEnable = SPDIF_SCR_DMA_RX_EN_MASK, /*!< Rx FIFO full */ + kSPDIF_TxDMAEnable = SPDIF_SCR_DMA_TX_EN_MASK, /*!< Tx FIFO empty */ +}; + +/*! @brief SPDIF user configuration structure */ +typedef struct _spdif_config +{ + bool isTxAutoSync; /*!< If auto sync mechanism open */ + bool isRxAutoSync; /*!< If auto sync mechanism open */ + uint8_t DPLLClkSource; /*!< SPDIF DPLL clock source, range from 0~15, meaning is chip-specific */ + uint8_t txClkSource; /*!< SPDIF tx clock source, range from 0~7, meaning is chip-specific */ + spdif_rxfull_select_t rxFullSelect; /*!< SPDIF rx buffer full select */ + spdif_txempty_select_t txFullSelect; /*!< SPDIF tx buffer empty select */ + spdif_uchannel_source_t uChannelSrc; /*!< U channel source */ + spdif_tx_source_t txSource; /*!< SPDIF tx data source */ + spdif_validity_config_t validityConfig; /*!< Validity flag config */ + spdif_gain_select_t gain; /*!< Rx receive clock measure gain parameter. */ +} spdif_config_t; + +/*!@brief SPDIF transfer queue size, user can refine it according to use case. */ +#define SPDIF_XFER_QUEUE_SIZE (4) + +/*! @brief SPDIF transfer structure */ +typedef struct _spdif_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + uint8_t *qdata; /*!< Data buffer for Q channel */ + uint8_t *udata; /*!< Data buffer for C channel */ + size_t dataSize; /*!< Transfer size. */ +} spdif_transfer_t; + +typedef struct _spdif_handle spdif_handle_t; + +/*! @brief SPDIF transfer callback prototype */ +typedef void (*spdif_transfer_callback_t)(SPDIF_Type *base, spdif_handle_t *handle, status_t status, void *userData); + +/*! @brief SPDIF handle structure */ +struct _spdif_handle +{ + uint32_t state; /*!< Transfer status */ + spdif_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + spdif_transfer_t spdifQueue[SPDIF_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SPDIF_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ + uint8_t watermark; /*!< Watermark value */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SPDIF peripheral. + * + * Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SPDIF_GetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault + * because the clock is not enabled. + * + * @param base SPDIF base pointer + * @param config SPDIF configuration structure. +*/ +void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config); + +/*! + * @brief Sets the SPDIF configuration structure to default values. + * + * This API initializes the configuration structure for use in SPDIF_Init. + * The initialized structure can remain unchanged in SPDIF_Init, or it can be modified + * before calling SPDIF_Init. + * This is an example. + @code + spdif_config_t config; + SPDIF_GetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SPDIF_GetDefaultConfig(spdif_config_t *config); + +/*! + * @brief De-initializes the SPDIF peripheral. + * + * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. + * + * @param base SPDIF base pointer +*/ +void SPDIF_Deinit(SPDIF_Type *base); + +/*! + * @brief Resets the SPDIF Tx. + * + * This function makes Tx FIFO in reset mode. + * + * @param base SPDIF base pointer + */ +static inline void SPDIF_TxFIFOReset(SPDIF_Type *base) +{ + base->SCR |= SPDIF_SCR_RXFIFO_RST_MASK; +} + +/*! + * @brief Resets the SPDIF Rx. + * + * This function enables the software reset and FIFO reset of SPDIF Rx. After reset, clear the reset bit. + * + * @param base SPDIF base pointer + */ +static inline void SPDIF_RxFIFOReset(SPDIF_Type *base) +{ + base->SCR |= SPDIF_SCR_RXFIFO_RST_MASK; +} + +/*! + * @brief Enables/disables the SPDIF Tx. + * + * @param base SPDIF base pointer + * @param enable True means enable SPDIF Tx, false means disable. + */ +void SPDIF_TxEnable(SPDIF_Type *base, bool enable); + +/*! + * @brief Enables/disables the SPDIF Rx. + * + * @param base SPDIF base pointer + * @param enable True means enable SPDIF Rx, false means disable. + */ +static inline void SPDIF_RxEnable(SPDIF_Type *base, bool enable) +{ + if (enable) + { + /* Open Rx FIFO */ + base->SCR &= ~(SPDIF_SCR_RXFIFO_CTRL_MASK | SPDIF_SCR_RXFIFO_OFF_ON_MASK); + } + else + { + base->SCR |= SPDIF_SCR_RXFIFO_OFF_ON_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SPDIF status flag state. + * + * @param base SPDIF base pointer + * @return SPDIF status flag value. Use the _spdif_interrupt_enable_t to get the status value needed. + */ +static inline uint32_t SPDIF_GetStatusFlag(SPDIF_Type *base) +{ + return base->SIS; +} + +/*! + * @brief Clears the SPDIF status flag state. + * + * @param base SPDIF base pointer + * @param mask State mask. It can be a combination of the _spdif_interrupt_enable_t member. Notice these members + * cannot be included, as these flags cannot be cleared by writing 1 to these bits: + * @arg kSPDIF_UChannelReceiveRegisterFull + * @arg kSPDIF_QChannelReceiveRegisterFull + * @arg kSPDIF_TxFIFOEmpty + * @arg kSPDIF_RxFIFOFull + */ +static inline void SPDIF_ClearStatusFlags(SPDIF_Type *base, uint32_t mask) +{ + base->SIC = mask; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SPDIF Tx interrupt requests. + * + * @param base SPDIF base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSPDIF_WordStartInterruptEnable + * @arg kSPDIF_SyncErrorInterruptEnable + * @arg kSPDIF_FIFOWarningInterruptEnable + * @arg kSPDIF_FIFORequestInterruptEnable + * @arg kSPDIF_FIFOErrorInterruptEnable + */ +static inline void SPDIF_EnableInterrupts(SPDIF_Type *base, uint32_t mask) +{ + base->SIE |= mask; +} + +/*! + * @brief Disables the SPDIF Tx interrupt requests. + * + * @param base SPDIF base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSPDIF_WordStartInterruptEnable + * @arg kSPDIF_SyncErrorInterruptEnable + * @arg kSPDIF_FIFOWarningInterruptEnable + * @arg kSPDIF_FIFORequestInterruptEnable + * @arg kSPDIF_FIFOErrorInterruptEnable + */ +static inline void SPDIF_DisableInterrupts(SPDIF_Type *base, uint32_t mask) +{ + base->SIE &= ~mask; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SPDIF DMA requests. + * @param base SPDIF base pointer + * @param mask SPDIF DMA enable mask, The parameter can be a combination of the following sources if defined + * @arg kSPDIF_RxDMAEnable + * @arg kSPDIF_TxDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SPDIF_EnableDMA(SPDIF_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SCR |= mask; + } + else + { + base->SCR &= ~mask; + } +} + +/*! + * @brief Gets the SPDIF Tx left data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_TxGetLeftDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->STL)); +} + +/*! + * @brief Gets the SPDIF Tx right data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_TxGetRightDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->STR)); +} + +/*! + * @brief Gets the SPDIF Rx left data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_RxGetLeftDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->SRL)); +} + +/*! + * @brief Gets the SPDIF Rx right data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->SRR)); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SPDIF Tx sample rate. + * + * The audio format can be changed at run-time. This function configures the sample rate. + * + * @param base SPDIF base pointer. + * @param sampleRate_Hz SPDIF sample rate frequency in Hz. + * @param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. +*/ +void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz); + +/*! + * @brief Configures the SPDIF Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SPDIF base pointer. + * @param clockSourceFreq_Hz SPDIF system clock frequency in hz. + */ +uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SPDIF base pointer. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteLeftData(SPDIF_Type *base, uint32_t data) +{ + base->STL = data; +} + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteRightData(SPDIF_Type *base, uint32_t data) +{ + base->STR = data; +} + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteChannelStatusHigh(SPDIF_Type *base, uint32_t data) +{ + base->STCSCH = data; +} + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteChannelStatusLow(SPDIF_Type *base, uint32_t data) +{ + base->STCSCL = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SPDIF base pointer. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadLeftData(SPDIF_Type *base) +{ + return base->SRL; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + *. + + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadRightData(SPDIF_Type *base) +{ + return base->SRR; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadChannelStatusHigh(SPDIF_Type *base) +{ + return base->SRCSH; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + *. + + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadChannelStatusLow(SPDIF_Type *base) +{ + return base->SRCSL; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadQChannel(SPDIF_Type *base) +{ + return base->SRQ; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + *. + + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadUChannel(SPDIF_Type *base) +{ + return base->SRU; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPDIF Tx handle. + * + * This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SPDIF base pointer + * @param handle SPDIF handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData); + +/*! + * @brief Initializes the SPDIF Rx handle. + * + * This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SPDIF base pointer. + * @param handle SPDIF handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SPDIF. + * + * @note This API returns immediately after the transfer initiates. + * Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param xfer Pointer to the spdif_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SPDIF_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SPDIF. + * + * @note This API returns immediately after the transfer initiates. + * Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * @param base SPDIF base pointer + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param xfer Pointer to the spdif_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SPDIF_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ +void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SPDIF base pointer + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ +void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure. + */ +void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure. + */ +void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SPDIF_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif_edma.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif_edma.c new file mode 100644 index 0000000000..79cc2ff05d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif_edma.c @@ -0,0 +1,521 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spdif_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.spdif_edma" +#endif + + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); + spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (spdifHandle->callback) + { + (spdifHandle->callback)(privHandle->base, spdifHandle, kStatus_SPDIF_TxIdle, spdifHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (spdifHandle->spdifQueue[spdifHandle->queueDriver].rightData == NULL) + { + SPDIF_TransferAbortSendEDMA(privHandle->base, spdifHandle); + } +} + +static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData; + spdif_edma_handle_t *spdifHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); + spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (spdifHandle->callback) + { + (spdifHandle->callback)(privHandle->base, spdifHandle, kStatus_SPDIF_RxIdle, spdifHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (spdifHandle->spdifQueue[spdifHandle->queueDriver].rightData == NULL) + { + SPDIF_TransferAbortReceiveEDMA(privHandle->base, spdifHandle); + } +} + +static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config, uint32_t rightChannel) +{ + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + uint32_t primask; + uint32_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + if (handle->tcdUsed >= handle->tcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1U; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0U; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Set channel link */ + EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MinorLink, rightChannel); + EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MajorLink, rightChannel); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Enable scatter/gather also in the TCD registers. */ + csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + link succeed. + */ + if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + { + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (handle->flags & 0x80) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; +} + +void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle) +{ + assert(handle && dmaLeftHandle && dmaRightHandle); + + uint32_t instance = SPDIF_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set spdif base to handle */ + handle->dmaLeftHandle = dmaLeftHandle; + handle->dmaRightHandle = dmaRightHandle; + handle->callback = callback; + handle->userData = userData; + handle->count = + s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; + + /* Set SPDIF state to idle */ + handle->state = kSPDIF_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaLeftHandle, STCD_ADDR(handle->leftTcd), SPDIF_XFER_QUEUE_SIZE); + EDMA_InstallTCDMemory(dmaRightHandle, STCD_ADDR(handle->rightTcd), SPDIF_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel, only right channel finished, a transfer finished */ + EDMA_SetCallback(dmaRightHandle, SPDIF_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle) +{ + assert(handle && dmaLeftHandle && dmaRightHandle); + + uint32_t instance = SPDIF_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set spdif base to handle */ + handle->dmaLeftHandle = dmaLeftHandle; + handle->dmaRightHandle = dmaRightHandle; + handle->callback = callback; + handle->userData = userData; + handle->count = s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; + + /* Set SPDIF state to idle */ + handle->state = kSPDIF_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaLeftHandle, STCD_ADDR(handle->leftTcd), SPDIF_XFER_QUEUE_SIZE); + EDMA_InstallTCDMemory(dmaRightHandle, STCD_ADDR(handle->rightTcd), SPDIF_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaRightHandle, SPDIF_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SPDIF_TxGetLeftDataRegisterAddress(base); + + /* Check if input parameter invalid */ + if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) + { + return kStatus_InvalidArgument; + } + + if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData)) + { + return kStatus_SPDIF_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSPDIF_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ + handle->nbytes = handle->count * 8U; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->leftData, 4U, (void *)destAddr, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_MemoryToPeripheral); + SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel); + + /* Prepare right channel */ + destAddr = SPDIF_TxGetRightDataRegisterAddress(base); + EDMA_PrepareTransfer(&config, xfer->rightData, 4U, (void *)destAddr, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_MemoryToPeripheral); + EDMA_SubmitTransfer(handle->dmaRightHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaLeftHandle); + EDMA_StartTransfer(handle->dmaRightHandle); + + /* Enable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_TxDMAEnable, true); + + /* Enable SPDIF Tx clock */ + SPDIF_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base); + + /* Check if input parameter invalid */ + if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) + { + return kStatus_InvalidArgument; + } + + if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData)) + { + return kStatus_SPDIF_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSPDIF_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ + handle->nbytes = handle->count * 8U; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->leftData, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_PeripheralToMemory); + /* Use specific submit function to enable channel link */ + SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel); + + /* Prepare right channel */ + srcAddr = SPDIF_RxGetRightDataRegisterAddress(base); + EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->rightData, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_PeripheralToMemory); + EDMA_SubmitTransfer(handle->dmaRightHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaLeftHandle); + EDMA_StartTransfer(handle->dmaRightHandle); + + /* Enable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, true); + + /* Enable SPDIF Rx clock */ + SPDIF_RxEnable(base, true); + + return kStatus_Success; +} + +void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaLeftHandle); + EDMA_AbortTransfer(handle->dmaRightHandle); + + /* Disable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_TxDMAEnable, false); + + /* Set internal state */ + memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; + + /* Set the handle state */ + handle->state = kSPDIF_Idle; +} + +void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaLeftHandle); + EDMA_AbortTransfer(handle->dmaRightHandle); + + /* Disable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, false); + + /* Set internal state */ + memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; + + /* Set the handle state */ + handle->state = kSPDIF_Idle; +} + +status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaRightHandle->base, handle->dmaRightHandle->channel)); + } + + return status; +} + +status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaRightHandle->base, handle->dmaRightHandle->channel)); + } + + return status; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif_edma.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif_edma.h new file mode 100644 index 0000000000..2815616f26 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_spdif_edma.h @@ -0,0 +1,217 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPDIF_EDMA_H_ +#define _FSL_SPDIF_EDMA_H_ + +#include "fsl_spdif.h" +#include "fsl_edma.h" + +/*! + * @addtogroup spdif_edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SPDIF_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +typedef struct _spdif_edma_handle spdif_edma_handle_t; + +/*! @brief SPDIF eDMA transfer callback function for finish and error */ +typedef void (*spdif_edma_callback_t)(SPDIF_Type *base, spdif_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPDIF transfer structure */ +typedef struct _spdif_edma_transfer +{ + uint8_t *leftData; /*!< Data start address to transfer. */ + uint8_t *rightData; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} spdif_edma_transfer_t; + +/*! @brief SPDIF DMA transfer handle, users should not touch the content of the handle.*/ +struct _spdif_edma_handle +{ + edma_handle_t *dmaLeftHandle; /*!< DMA handler for SPDIF left channel */ + edma_handle_t *dmaRightHandle; /*!< DMA handler for SPDIF right channel */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SPDIF eDMA transfer */ + spdif_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + edma_tcd_t leftTcd[SPDIF_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + edma_tcd_t rightTcd[SPDIF_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + spdif_edma_transfer_t spdifQueue[SPDIF_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SPDIF_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer, left and right are the same, so use + one */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SPDIF eDMA handle. + * + * This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param base SPDIF peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * @param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ +void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle); + +/*! + * @brief Initializes the SPDIF Rx eDMA handle. + * + * This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param base SPDIF peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * @param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ +void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle); + +/*! + * @brief Performs a non-blocking SPDIF transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SPDIF eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SPDIF is busy sending data. + */ +status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPDIF receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished. + * + * @param base SPDIF base pointer + * @param handle SPDIF eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SPDIF eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SPDIF is busy receiving data. + */ +status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer); + +/*! + * @brief Aborts a SPDIF transfer using eDMA. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + */ +void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle); + +/*! + * @brief Aborts a SPDIF receive using eDMA. + * + * @param base SPDIF base pointer + * @param handle SPDIF eDMA handle pointer. + */ +void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SPDIF. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param count Bytes count sent by SPDIF. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SPDIF. + * + * @param base SPDIF base pointer + * @param handle SPDIF eDMA handle pointer. + * @param count Bytes count received by SPDIF. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_src.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_src.c new file mode 100644 index 0000000000..7672586d32 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_src.c @@ -0,0 +1,70 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_src.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.src" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags) +{ + uint32_t tmp32 = base->SRSR; + + if (0U != (SRC_SRSR_TSR_MASK & flags)) + { + tmp32 &= ~SRC_SRSR_TSR_MASK; /* Write 0 to clear. */ + } + + if (0U != (SRC_SRSR_W1C_BITS_MASK & flags)) + { + tmp32 |= (SRC_SRSR_W1C_BITS_MASK & flags); /* Write 1 to clear. */ + } + + base->SRSR = tmp32; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_src.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_src.h new file mode 100644 index 0000000000..bf25582051 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_src.h @@ -0,0 +1,623 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SRC_H_ +#define _FSL_SRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup src + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SRC driver version 2.0.0. */ +#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief SRC reset status flags. + */ +enum _src_reset_status_flags +{ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) && FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) + kSRC_ResetOutputEnableFlag = SRC_SRSR_RESET_OUT_MASK, /*!< This bit indicates if RESET status is + driven out on PTE0 pin. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */ +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) + kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot + was initiated by software. */ +#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ + kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the + result of software reset from on-chip + Temperature Sensor. Temperature Sensor + Interrupt need be served before this + bit can be cleaned.*/ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) + kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates + whether the reset was the result of the + watchdog3 time-out event. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW) + kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software + setting of SYSRESETREQ bit in Application + Interrupt and Reset Control Register in the + ARM core. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_SW */ + kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK, /*!< Indicates whether the reset was the result of + setting SJC_GPCCR bit 31. */ + kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG + selection of certain IR codes: EXTEST or + HIGHZ. */ + kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK, /*!< Indicates a reset has been caused by the + watchdog timer timing out. This reset source + can be blocked by disabling the watchdog. */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) + kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK, /*!< Indicates whether the reset was the + result of the ipp_user_reset_b + qualified reset. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS) + kSRC_SNVSFailResetFlag = SRC_SRSR_SNVS_MASK, /*!< SNVS hardware failure will always cause a cold + reset. This flag indicates whether the reset + is a result of SNVS hardware failure. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_SNVS */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) + kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK, /*!< Indicates whether the reset was the result + of the csu_reset_b input. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) + kSRC_CoreLockupResetFlag = SRC_SRSR_LOCKUP_MASK, /*!< Indicates a reset has been caused by the + ARM core indication of a LOCKUP event. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR) + kSRC_PowerOnResetFlag = SRC_SRSR_POR_MASK, /*!< Indicates a reset has been caused by the + power-on detection logic. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) + kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software + setting of SYSRESETREQ bit in Application Interrupt and + Reset Control Register of the ARM core. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) + kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of + ipp_reset_b pin (Power-up sequence). */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B */ +}; + +#if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR) +/*! + * @brief SRC interrupt status flag. + */ +enum _src_status_flags +{ + kSRC_Core0WdogResetReqFlag = + SRC_SISR_CORE0_WDOG_RST_REQ_MASK, /*!< WDOG reset request from core0. Read-only status bit. */ +}; +#endif /* FSL_FEATURE_SRC_HAS_SISR */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) +/*! + * @brief Selection of SoC mix power reset stretch. + * + * This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset + * stretch mix reset width with the optional count of cycles + */ +typedef enum _src_mix_reset_stretch_cycles +{ + kSRC_MixResetStretchCycleAlt0 = 0U, /*!< mix reset width is 1 x 88 ipg_cycle cycles. */ + kSRC_MixResetStretchCycleAlt1 = 1U, /*!< mix reset width is 2 x 88 ipg_cycle cycles. */ + kSRC_MixResetStretchCycleAlt2 = 2U, /*!< mix reset width is 3 x 88 ipg_cycle cycles. */ + kSRC_MixResetStretchCycleAlt3 = 3U, /*!< mix reset width is 4 x 88 ipg_cycle cycles. */ +} src_mix_reset_stretch_cycles_t; +#endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) +/*! + * @brief Selection of WDOG3 reset option. + */ +typedef enum _src_wdog3_reset_option +{ + kSRC_Wdog3ResetOptionAlt0 = 0U, /*!< Wdog3_rst_b asserts M4 reset (default). */ + kSRC_Wdog3ResetOptionAlt1 = 1U, /*!< Wdog3_rst_b asserts global reset. */ +} src_wdog3_reset_option_t; +#endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */ + +/*! + * @brief Selection of WARM reset bypass count. + * + * This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM + * reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will + * be initiated. + */ +typedef enum _src_warm_reset_bypass_count +{ + kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */ + kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */ +} src_warm_reset_bypass_count_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) && FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) +/*! + * @brief Enable the WDOG3 reset. + * + * The WDOG3 reset is enabled by default. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableWDOG3Reset(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA); + } + else + { + base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5); + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) +/*! + * @brief Set the mix power up reset stretch mix reset width. + * + * @param base SRC peripheral base address. + * @param option Setting option, see to #src_mix_reset_stretch_cycles_t. + */ +static inline void SRC_SetMixResetStretchCycles(SRC_Type *base, src_mix_reset_stretch_cycles_t option) +{ + base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) && FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) +/*! + * @brief Debug reset would be asserted after power gating event. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableCoreDebugResetAfterPowerGate(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK; + } + else + { + base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) +/*! + * @brief Set the Wdog3_rst_b option. + * + * @param base SRC peripheral base address. + * @param option Setting option, see to #src_wdog3_reset_option_t. + */ +static inline void SRC_SetWdog3ResetOption(SRC_Type *base, src_wdog3_reset_option_t option) +{ + base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) && FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) +/*! + * @brief Software reset for debug of arm platform only. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoSoftwareResetARMCoreDebug(SRC_Type *base) +{ + base->SCR |= SRC_SCR_CORES_DBG_RST_MASK; +} + +/*! + * @brief Check if the software reset for debug of arm platform only is done. + * + * @param base SRC peripheral base address. + */ +static inline bool SRC_GetSoftwareResetARMCoreDebugDone(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK)); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MTSR) && FSL_FEATURE_SRC_HAS_SCR_MTSR) +/*! + * @brief Enable the temperature sensor reset. + * + * The temperature sersor reset is enabled by default. When the sensor reset happens, an flag bit + * would be asserted. This flag bit can be cleared only by the hardware reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableTemperatureSensorReset(SRC_Type *base, bool enable) +{ + if (enable) /* Temperature sensor reset is not masked. (default) */ + { + base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2); + } + else /* The on-chip temperature sensor interrupt will not create a reset to the chip. */ + { + base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5); + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_MTSR */ + +#if (defined(FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) && FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) +/*! + * @brief Do assert the core0 debug reset. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoAssertCore0DebugReset(SRC_Type *base) +{ + base->SCR |= SRC_SCR_CORE0_DBG_RST_MASK; +} + +/*! + * @brief Check if the core0 debug reset is done. + * + * @param base SRC peripheral base address. + */ +static inline bool SRC_GetAssertCore0DebugResetDone(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_CORE0_DBG_RST_MASK)); +} +#endif /* FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) && FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) +/*! + * @brief Do software reset the ARM core0 only. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoSoftwareResetARMCore0(SRC_Type *base) +{ + base->SCR |= SRC_SCR_CORE0_RST_MASK; +} + +/*! + * @brief Check if the software for ARM core0 is done. + * + * @param base SRC peripheral base address. + * @return If the reset is done. + */ +static inline bool SRC_GetSoftwareResetARMCore0Done(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_CORE0_RST_MASK)); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_CORE0_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_SWRC) && FSL_FEATURE_SRC_HAS_SCR_SWRC) +/*! + * @brief Do software reset for ARM core. + * + * This function can be used to assert the ARM core reset. Once it is called, the reset process will + * begin. After the reset process is finished, the command bit would be self cleared. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoSoftwareResetARMCore(SRC_Type *base) +{ + base->SCR |= SRC_SCR_SWRC_MASK; +} + +/*! + * @brief Check if the software for ARM core is done. + * + * @param base SRC peripheral base address. + * @return If the reset is done. + */ +static inline bool SRC_GetSoftwareResetARMCoreDone(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_SWRC_MASK)); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_SWRC */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_EIM_RST) && FSL_FEATURE_SRC_HAS_SCR_EIM_RST) +/*! + * @brief Assert the EIM reset. + * + * EIM reset is needed in order to reconfigure the EIM chip select. + * The software reset bit must de-asserted since this is not self-refresh. + * + * @param base SRC peripheral base address. + * @param enable Make the assertion or not. + */ +static inline void SRC_AssertEIMReset(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR |= SRC_SCR_EIM_RST_MASK; + } + else + { + base->SCR &= ~SRC_SCR_EIM_RST_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_EIM_RST */ + +/*! + * @brief Enable the WDOG Reset in SRC. + * + * WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create + * a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is + * asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear + * that bit is the hardware reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableWDOGReset(SRC_Type *base, bool enable) +{ + if (enable) /* WDOG Reset is not masked in SRC (default). */ + { + base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0xA); + } + else /* WDOG Reset is masked in SRC. */ + { + base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0x5); + } +} + +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) && FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) +/*! + * @brief Set the delay count of waiting MMDC's acknowledge. + * + * This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge + * for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD + * reset will be initiated. + * + * @param base SRC peripheral base address. + * @param option The option of setting mode, see to #src_warm_reset_bypass_count_t. + */ +static inline void SRC_SetWarmResetBypassCount(SRC_Type *base, src_warm_reset_bypass_count_t option) +{ + base->SCR = (base->SCR & ~SRC_SCR_WRBC_MASK) | SRC_SCR_WRBC(option); +} +#endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRBC */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) +/*! + * @brief Enable the lockup reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableLockupReset(SRC_Type *base, bool enable) +{ + if (enable) /* Enable lockup reset. */ + { + base->SCR |= SRC_SCR_LOCKUP_RST_MASK; + } + else /* Disable lockup reset. */ + { + base->SCR &= ~SRC_SCR_LOCKUP_RST_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_LUEN) && FSL_FEATURE_SRC_HAS_SCR_LUEN) +/*! + * @brief Enable the core lockup reset. + * + * When enable the core luckup reset, the system would be reset when core luckup event happens. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableCoreLockupReset(SRC_Type *base, bool enable) +{ + if (enable) /* Core lockup will cause system reset. */ + { + base->SCR |= SRC_SCR_LUEN_MASK; + } + else /* Core lockup will not cause system reset. */ + { + base->SCR &= ~SRC_SCR_LUEN_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_LUEN */ + +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRE) && FSL_FEATURE_SRC_HAS_NO_SCR_WRE) +/*! + * @brief Enable the WARM reset. + * + * Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset. + * Otherwise, all the WARM reset sources would generate COLD reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the WARM reset or not. + */ +static inline void SRC_EnableWarmReset(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR |= SRC_SCR_WRE_MASK; + } + else + { + base->SCR &= ~SRC_SCR_WRE_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRE */ + +#if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR) +/*! + * @brief Get interrupt status flags. + * + * @param base SRC peripheral base address. + * @return Mask value of status flags. See to $_src_status_flags. + */ +static inline uint32_t SRC_GetStatusFlags(SRC_Type *base) +{ + return base->SISR; +} +#endif /* FSL_FEATURE_SRC_HAS_SISR */ + +/*! + * @brief Get the boot mode register 1 value. + * + * The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. + * See to chip-specific document for detail information about value. + * + * @param base SRC peripheral base address. + * @return status of BOOT_CFGx pins of the chip. + */ +static inline uint32_t SRC_GetBootModeWord1(SRC_Type *base) +{ + return base->SBMR1; +} + +/*! + * @brief Get the boot mode register 2 value. + * + * The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values + * that controls boot of the chip. See to chip-specific document for detail information about value. + * + * @param base SRC peripheral base address. + * @return status of BOOT_MODEx Pins and fuse values that controls boot of the chip. + */ +static inline uint32_t SRC_GetBootModeWord2(SRC_Type *base) +{ + return base->SBMR2; +} + +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) +/*! + * @brief Set the warm boot indication flag. + * + * WARM boot indication shows that WARM boot was initiated by software. This indicates to the + * software that it saved the needed information in the memory before initiating the WARM reset. + * In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot + * bit should be used as indication only after a warm_reset sequence. Software should clear this bit + * after warm_reset to indicate that the next warm_reset is not performed with warm_boot. + * + * @param base SRC peripheral base address. + * @param enable Assert the flag or not. + */ +static inline void SRC_SetWarmBootIndication(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) | SRC_SRSR_WBI_MASK; + } + else + { + base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) & ~SRC_SRSR_WBI_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ + +/*! + * @brief Get the status flags of SRC. + * + * @param base SRC peripheral base address. + * @return Mask value of status flags, see to #_src_reset_status_flags. + */ +static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base) +{ + return base->SRSR; +} + +/*! + * @brief Clear the status flags of SRC. + * + * @param base SRC peripheral base address. + * @param Mask value of status flags to be cleared, see to #_src_reset_status_flags. + */ +void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags); + +/*! + * @brief Set value to general purpose registers. + * + * General purpose registers (GPRx) would hold the value during reset process. Wakeup function could + * be kept in these register. For example, the GPR1 holds the entry function for waking-up from + * Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the + * arbitray values. + * + * @param base SRC peripheral base address. + * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register. + * @param value Setting value for GPRx register. + */ +static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, uint32_t index, uint32_t value) +{ + assert(index < SRC_GPR_COUNT); + + base->GPR[index] = value; +} + +/*! + * @brief Get the value from general purpose registers. + * + * @param base SRC peripheral base address. + * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register. + * @return The setting value for GPRx register. + */ +static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, uint32_t index) +{ + assert(index < SRC_GPR_COUNT); + + return base->GPR[index]; +} + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_SRC_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_trng.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_trng.c new file mode 100644 index 0000000000..68864316fe --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_trng.c @@ -0,0 +1,1664 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_trng.h" + +#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trng" +#endif + +/* Default values for user configuration structure.*/ +#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ + defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES)) +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 +#elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ + defined(KL82Z7_SERIES)) +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 +#elif defined(K81F25615_SERIES) +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 +#else +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0 +#endif + +#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 +#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 +#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500 +#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 +#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 +#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34 + +#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384 +#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46) +#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912 +#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467) +#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 25600 +#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600 + +/*! @brief TRNG work mode */ +typedef enum _trng_work_mode +{ + kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ + kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ +} trng_work_mode_t; + +/*! @brief TRNG statistical check type*/ +typedef enum _trng_statistical_check +{ + kTRNG_StatisticalCheckMonobit = + 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */ + kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during + entropy generation. */ + kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */ + kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */ +} trng_statistical_check_t; + +/******************************************************************************* + * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register + ******************************************************************************/ +/*! + * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW) + * + * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation, + * the RTY_CT value indicates the number of times a retry should occur before + * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This + * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing + * the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */ +#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT) + +/*! @brief Set the RTY_CT field to a new value. */ +#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCML - RNG Statistical Check Monobit Limit Register + ******************************************************************************/ +/*! + * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW) + * + * Reset value: 0x010C0568U + * + * The RNG Statistical Check Monobit Limit Register defines the allowable + * maximum and minimum number of ones/zero detected during entropy generation. To pass + * the test, the number of ones/zeroes generated must be less than the programmed + * maximum value, and the number of ones/zeroes generated must be greater than + * (maximum - range). If this test fails, the Retry Counter in SCMISC will be + * decremented, and a retry will occur if the Retry Count has not reached zero. If + * the Retry Count has reached zero, an error will be generated. Note that this + * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, + * this offset is used as SCMC readback register. + */ +/*! + * @name Constants and macros for entire TRNG_SCML register + */ +/*@{*/ +#define TRNG_SCML_REG(base) ((base)->SCML) +#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) +#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) +#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value))) +/*@}*/ +/*! + * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW) + * + * Monobit Maximum Limit. Defines the maximum allowable count taken during + * entropy generation. The number of ones/zeroes detected during entropy generation + * must be less than MONO_MAX, else a retry or error will occur. This register is + * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */ +#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT) + +/*! @brief Set the MONO_MAX field to a new value. */ +#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value))) +/*@}*/ +/*! + * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW) + * + * Monobit Range. The number of ones/zeroes detected during entropy generation + * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur. + * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF] + * bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */ +#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT) + +/*! @brief Set the MONO_RNG field to a new value. */ +#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW) + * + * Reset value: 0x00B20195U + * + * The RNG Statistical Check Run Length 1 Limit Register defines the allowable + * maximum and minimum number of runs of length 1 detected during entropy + * generation. To pass the test, the number of runs of length 1 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 1 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR1L register + */ +/*@{*/ +#define TRNG_SCR1L_REG(base) ((base)->SCR1L) +#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base)) +#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) +#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW) + * + * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 1 detected during entropy generation must be less than RUN1_MAX, else a + * retry or error will occur. This register is cleared to 01E5h (decimal 485) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */ +#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT) + +/*! @brief Set the RUN1_MAX field to a new value. */ +#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW) + * + * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1) + * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a + * retry or error will occur. This register is cleared to 0102h (decimal 258) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */ +#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT) + +/*! @brief Set the RUN1_RNG field to a new value. */ +#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW) + * + * Reset value: 0x007A00DCU + * + * The RNG Statistical Check Run Length 2 Limit Register defines the allowable + * maximum and minimum number of runs of length 2 detected during entropy + * generation. To pass the test, the number of runs of length 2 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 2 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR2L register + */ +/*@{*/ +#define TRNG_SCR2L_REG(base) ((base)->SCR2L) +#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base)) +#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) +#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR2L bitfields + */ + +/*! + * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW) + * + * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 2 detected during entropy generation must be less than RUN2_MAX, else a + * retry or error will occur. This register is cleared to 00DCh (decimal 220) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */ +#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT) + +/*! @brief Set the RUN2_MAX field to a new value. */ +#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW) + * + * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1) + * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a + * retry or error will occur. This register is cleared to 007Ah (decimal 122) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */ +#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT) + +/*! @brief Set the RUN2_RNG field to a new value. */ +#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW) + * + * Reset value: 0x0058007DU + * + * The RNG Statistical Check Run Length 3 Limit Register defines the allowable + * maximum and minimum number of runs of length 3 detected during entropy + * generation. To pass the test, the number of runs of length 3 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 3 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR3L register + */ +/*@{*/ +#define TRNG_SCR3L_REG(base) ((base)->SCR3L) +#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base)) +#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) +#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR3L bitfields + */ + +/*! + * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW) + * + * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 3 detected during entropy generation must be less than RUN3_MAX, else a + * retry or error will occur. This register is cleared to 007Dh (decimal 125) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */ +#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT) + +/*! @brief Set the RUN3_MAX field to a new value. */ +#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW) + * + * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1) + * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a + * retry or error will occur. This register is cleared to 0058h (decimal 88) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */ +#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT) + +/*! @brief Set the RUN3_RNG field to a new value. */ +#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW) + * + * Reset value: 0x0040004BU + * + * The RNG Statistical Check Run Length 4 Limit Register defines the allowable + * maximum and minimum number of runs of length 4 detected during entropy + * generation. To pass the test, the number of runs of length 4 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 4 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR4L register + */ +/*@{*/ +#define TRNG_SCR4L_REG(base) ((base)->SCR4L) +#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base)) +#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) +#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR4L bitfields + */ + +/*! + * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW) + * + * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 4 detected during entropy generation must be less than RUN4_MAX, else a + * retry or error will occur. This register is cleared to 004Bh (decimal 75) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */ +#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT) + +/*! @brief Set the RUN4_MAX field to a new value. */ +#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW) + * + * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1) + * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a + * retry or error will occur. This register is cleared to 0040h (decimal 64) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */ +#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT) + +/*! @brief Set the RUN4_RNG field to a new value. */ +#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW) + * + * Reset value: 0x002E002FU + * + * The RNG Statistical Check Run Length 5 Limit Register defines the allowable + * maximum and minimum number of runs of length 5 detected during entropy + * generation. To pass the test, the number of runs of length 5 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 5 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR5L register + */ +/*@{*/ +#define TRNG_SCR5L_REG(base) ((base)->SCR5L) +#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base)) +#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) +#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR5L bitfields + */ + +/*! + * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW) + * + * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 5 detected during entropy generation must be less than RUN5_MAX, else a + * retry or error will occur. This register is cleared to 002Fh (decimal 47) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */ +#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT) + +/*! @brief Set the RUN5_MAX field to a new value. */ +#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW) + * + * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1) + * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a + * retry or error will occur. This register is cleared to 002Eh (decimal 46) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */ +#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT) + +/*! @brief Set the RUN5_RNG field to a new value. */ +#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW) + * + * Reset value: 0x002E002FU + * + * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable + * maximum and minimum number of runs of length 6 or more detected during entropy + * generation. To pass the test, the number of runs of length 6 or more (for + * samples of both 0 and 1) must be less than the programmed maximum value, and the + * number of runs of length 6 or more must be greater than (maximum - range). If + * this test fails, the Retry Counter in SCMISC will be decremented, and a retry + * will occur if the Retry Count has not reached zero. If the Retry Count has + * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is + * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is + * used as SCR6PC readback register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR6PL register + */ +/*@{*/ +#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) +#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base)) +#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) +#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR6PL bitfields + */ + +/*! + * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW) + * + * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6 + * or more (for both 0 and 1) detected during entropy generation. The number of + * runs of length 6 or more detected during entropy generation must be less than + * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh + * (decimal 47) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */ +#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \ + ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT) + +/*! @brief Set the RUN6P_MAX field to a new value. */ +#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \ + (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW) + * + * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and + * 1) detected during entropy generation must be greater than RUN6P_MAX - + * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh + * (decimal 46) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */ +#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \ + ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT) + +/*! @brief Set the RUN6P_RNG field to a new value. */ +#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \ + (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_PKRMAX - RNG Poker Maximum Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW) + * + * Reset value: 0x00006920U + * + * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during + * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is + * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used + * as the PKRSQ readback register. + */ +/*! + * @name Constants and macros for entire TRNG_PKRMAX register + */ +/*@{*/ +#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX) +#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base)) +#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) +#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_PKRMAX bitfields + */ + +/*! + * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW) + * + * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is + * run which requires a maximum and minimum limit. The maximum allowable result is + * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if + * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by + * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers + * combined are used to define the minimum allowable Poker result, which is PKR_MAX - + * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used + * to read the Poker Test Square Calculation result in register PKRSQ, as defined + * in the following section. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */ +#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT) + +/*! @brief Set the PKR_MAX field to a new value. */ +#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \ + (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_PKRRNG - RNG Poker Range Register + ******************************************************************************/ + +/*! + * @brief TRNG_PKRRNG - RNG Poker Range Register (RW) + * + * Reset value: 0x000009A3U + * + * The RNG Poker Range Register defines the difference between the TRNG Poker + * Maximum Limit and the minimum limit. These limits are used during the TRNG + * Statistical Check Poker Test. + */ +/*! + * @name Constants and macros for entire TRNG_PKRRNG register + */ +/*@{*/ +#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG) +#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base)) +#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value)) +#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_PKRRNG bitfields + */ + +/*! + * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW) + * + * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which + * requires a maximum and minimum limit. The maximum is programmed in the + * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG + * value from the programmed maximum value. This field is writable only if + * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is + * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that + * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */ +#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT) + +/*! @brief Set the PKR_RNG field to a new value. */ +#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \ + (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW) + * + * Reset value: 0x00006400U + * + * The RNG Frequency Count Maximum Limit Register defines the maximum allowable + * count taken by the Entropy sample counter during each Entropy sample. During + * any sample period, if the count is greater than this programmed maximum, a + * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note + * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If + * MCTL[PRGM] is 0, this address is used as FRQCNT readback register. + */ +/*! + * @name Constants and macros for entire TRNG_FRQMAX register + */ +/*@{*/ +#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX) +#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base)) +#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value)) +#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_FRQMAX bitfields + */ + +/*! + * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW) + * + * Frequency Counter Maximum Limit. Defines the maximum allowable count taken + * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. + * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1. + * Note that if MCTL[PRGM] bit is 0, this register address is used to read the + * Frequency Count result in register FRQCNT, as defined in the following section. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */ +#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT) + +/*! @brief Set the FRQ_MAX field to a new value. */ +#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \ + (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW) + * + * Reset value: 0x00000640U + * + * The RNG Frequency Count Minimum Limit Register defines the minimum allowable + * count taken by the Entropy sample counter during each Entropy sample. During + * any sample period, if the count is less than this programmed minimum, a + * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. + */ +/*! + * @name Constants and macros for entire TRNG_FRQMIN register + */ +/*@{*/ +#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN) +#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base)) +#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value)) +#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_FRQMIN bitfields + */ + +/*! + * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW) + * + * Frequency Count Minimum Limit. Defines the minimum allowable count taken + * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. + * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64 + * by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */ +#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT) + +/*! @brief Set the FRQ_MIN field to a new value. */ +#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \ + (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_MCTL - RNG Miscellaneous Control Register + ******************************************************************************/ + +/*! + * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW) + * + * Reset value: 0x00012001U + * + * This register is intended to be used for programming, configuring and testing + * the RNG. It is the main register to read/write, in order to enable Entropy + * generation, to stop entropy generation and to block access to entropy registers. + * This is done via the special TRNG_ACC and PRGM bits below. The RNG + * Miscellaneous Control Register is a read/write register used to control the RNG's True + * Random Number Generator (TRNG) access, operation and test. Note that in many + * cases two RNG registers share the same address, and a particular register at the + * shared address is selected based upon the value in the PRGM field of the MCTL + * register. + */ +/*! + * @name Constants and macros for entire TRNG_MCTL register + */ +/*@{*/ +#define TRNG_MCTL_REG(base) ((base)->MCTL) +#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base)) +#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) +#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW) + * + * Force System Clock. If set, the system clock is used to operate the TRNG, + * instead of the ring oscillator. This is for test use only, and indeterminate + * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is + * being written to 1 simultaneously to writing this bit. This bit is cleared by + * writing the RST_DEF bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */ +#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT) + +/*! @brief Set the FOR_SCLK field to a new value. */ +#define TRNG_WR_MCTL_FOR_SCLK(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW) + * + * Oscillator Divide. Determines the amount of dividing done to the ring + * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is + * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This + * field is cleared to 00 by writing the RST_DEF bit to 1. + * + * Values: + * - 0b00 - use ring oscillator with no divide + * - 0b01 - use ring oscillator divided-by-2 + * - 0b10 - use ring oscillator divided-by-4 + * - 0b11 - use ring oscillator divided-by-8 + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */ +#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT) + +/*! @brief Set the OSC_DIV field to a new value. */ +#define TRNG_WR_MCTL_OSC_DIV(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW) + * + * Sample Mode. Determines the method of sampling the ring oscillator while + * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM + * bit is being written to 1 simultaneously with writing this field. This field + * is cleared to 01 by writing the RST_DEF bit to 1. + * + * Values: + * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical + * Checker + * - 0b01 - use raw data into both Entropy shifter and Statistical Checker + * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into + * Statistical Checker + * - 0b11 - reserved. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */ +#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT) + +/*! @brief Set the SAMP_MODE field to a new value. */ +#define TRNG_WR_MCTL_SAMP_MODE(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field PRGM[16] (RW) + * + * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode, + * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is + * in Program Mode. Note that different RNG registers are accessible at the same + * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG + * register descriptions. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_PRGM field. */ +#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT) + +/*! @brief Set the PRGM field to a new value. */ +#define TRNG_WR_MCTL_PRGM(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field RST_DEF[6] (WO) + * + * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and + * bits within registers, to their default state. This bit is writable only if PRGM + * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this + * bit. Reading this bit always produces a 0. + */ +/*@{*/ +/*! @brief Set the RST_DEF field to a new value. */ +#define TRNG_WR_MCTL_RST_DEF(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value))) +/*@}*/ + +#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) +/*! + * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW) + * + * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy + * value that can be read via the ENT0-ENT15 registers. The Entropy value may be + * read once the ENT VAL bit is asserted. Also see ENTa register descriptions + * (For a = 0 to 15). + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */ +#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT) + +/*! @brief Set the TRNG_ACC field to a new value. */ +#define TRNG_WR_MCTL_TRNG_ACC(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value))) +/*@}*/ +#endif + +/*! + * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO) + * + * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before + * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG + * free-running ring oscillator whenever new entropy is being generated and turns off the + * ring oscillator when entropy generation is complete. If the RNG clock is + * stopped while the TRNG ring oscillator is running, the oscillator will continue + * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG + * ring oscillator is not running. and therefore it is ok to stop the RNG clock. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */ +#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field ENT_VAL[10] (RO) + * + * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then + * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0 + * through ENT14 should be read before reading ENT15). + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */ +#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field ERR[12] (W1C) + * + * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear + * errors. Writing 0 has no effect. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_ERR field. */ +#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT) + +/*! @brief Set the ERR field to a new value. */ +#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SDCTL - RNG Seed Control Register + ******************************************************************************/ + +/*! + * @brief TRNG_SDCTL - RNG Seed Control Register (RW) + * + * Reset value: 0x0C8009C4U + * + * The RNG Seed Control Register contains two fields. One field defines the + * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field + * indicates the number of samples that will taken during each TRNG Entropy + * generation (SAMP_SIZE). + */ +/*! + * @name Constants and macros for entire TRNG_SDCTL register + */ +/*@{*/ +#define TRNG_SDCTL_REG(base) ((base)->SDCTL) +#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base)) +#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) +#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SDCTL bitfields + */ + +/*! + * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW) + * + * Sample Size. Defines the total number of Entropy samples that will be taken + * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1. + * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h + * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */ +#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT) + +/*! @brief Set the SAMP_SIZE field to a new value. */ +#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \ + (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value))) +/*@}*/ + +/*! + * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW) + * + * Entropy Delay. Defines the length (in system clocks) of each Entropy sample + * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read + * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */ +#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT) + +/*! @brief Set the ENT_DLY field to a new value. */ +#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SBLIM - RNG Sparse Bit Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW) + * + * Reset value: 0x0000003FU + * + * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is + * selected during Entropy Generation. It defines the maximum number of consecutive Von + * Neumann samples which may be discarded before an error is generated. Note + * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If + * MCTL[PRGM] is 0, this address is used as TOTSAM readback register. + */ +/*! + * @name Constants and macros for entire TRNG_SBLIM register + */ +/*@{*/ +#define TRNG_SBLIM_REG(base) ((base)->SBLIM) +#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base)) +#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value)) +#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SBLIM bitfields + */ + +/*! + * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW) + * + * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE], + * samples are discarded if two consecutive raw samples are both 0 or both 1. If + * this discarding occurs for a long period of time, it indicates that there is + * insufficient Entropy. The Sparse Bit Limit defines the maximum number of + * consecutive samples that may be discarded before an error is generated. This field + * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by + * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this + * register address is used to read the Total Samples count in register TOTSAM, as + * defined in the following section. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */ +#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT) + +/*! @brief Set the SB_LIM field to a new value. */ +#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW) + * + * Reset value: 0x0001001FU + * + * The RNG Statistical Check Miscellaneous Register contains the Long Run + * Maximum Limit value and the Retry Count value. This register is accessible only when + * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot + * be written. + */ +/*! + * @name Constants and macros for entire TRNG_SCMISC register + */ +/*@{*/ +#define TRNG_SCMISC_REG(base) ((base)->SCMISC) +#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base)) +#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value)) +#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCMISC bitfields + */ + +/*! + * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW) + * + * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive + * samples of all 1, or all 0, that is allowed during the Entropy generation. + * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes + * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF] + * bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */ +#define TRNG_RD_SCMISC_LRUN_MAX(base) \ + ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT) + +/*! @brief Set the LRUN_MAX field to a new value. */ +#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \ + (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_ENT - RNG TRNG Entropy Read Register + ******************************************************************************/ + +/*! + * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO) + * + * Reset value: 0x00000000U + * + * The RNG TRNG can be programmed to generate an entropy value that is readable + * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the + * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this + * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value. + * Note that once ENT15 is read, the entropy value will be cleared and a new + * value will begin generation, so it is important that ENT15 be read last. These + * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1 + * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read. + */ +/*! + * @name Constants and macros for entire TRNG_ENT register + */ +/*@{*/ +#define TRNG_ENT_REG(base, index) ((base)->ENT[index]) +#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index)) +/*@}*/ + +/******************************************************************************* + * TRNG_SEC_CFG - RNG Security Configuration Register + ******************************************************************************/ + +/*! + * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW) + * + * Reset value: 0x00000000U + * + * The RNG Security Configuration Register is a read/write register used to + * control the test mode, programmability and state modes of the RNG. Many bits are + * place holders for this version. More configurability will be added here. Clears + * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0 + * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use + * these registers, if hard coded. + */ +/*! + * @name Constants and macros for entire TRNG_SEC_CFG register + */ +/*@{*/ +#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG) +#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base)) +#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value)) +#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW) + * + * If set the TRNG registers cannot be programmed. That is, regardless of the + * TRNG access mode in the SA-TRNG Miscellaneous Control Register. + * + * Values: + * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous + * Control Register's access mode bit. + * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents + * TRNG register programming. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */ +#define TRNG_RD_SEC_CFG_NO_PRGM(base) \ + ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT) + +/*! @brief Set the NO_PRGM field to a new value. */ +#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \ + (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value))) +/*@}*/ + +/*! @brief Array to map TRNG instance number to base pointer. */ +static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clock array name */ +static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ +static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig); +static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count); +static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, + trng_statistical_check_t statistical_check, + const trng_statistical_check_limit_t *limit); +static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index); +static uint32_t trng_GetInstance(TRNG_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t trng_GetInstance(TRNG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++) + { + if (s_trngBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_trngBases)); + + return instance; +} + +/*FUNCTION********************************************************************* + * + * Function Name : TRNG_InitUserConfigDefault + * Description : Initializes user configuration structure to default settings. + * + *END*************************************************************************/ +status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) +{ + status_t result; + + if (userConfig != NULL) + { + userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK; + userConfig->clockMode = kTRNG_ClockModeRingOscillator; + userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; + userConfig->sampleMode = kTRNG_SampleModeRaw; + userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; + userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; + userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; + + /* Statistical Check Parameters.*/ + userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; + userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; + + userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; + userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; + userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; + userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; + userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; + userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; + userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; + userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; + userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; + userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; + userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; + userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; + userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; + userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; + userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; + userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; + userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; + userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; + + result = kStatus_Success; + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +/*! + * @brief Sets the TRNG retry count. + * + * This function sets the retry counter which defines the number of times a + * statistical check may fails during the TRNG Entropy Generation before + * generating an error. +*/ +static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) +{ + status_t status; + + if ((retry_count >= 1u) && (retry_count <= 15u)) + { + /* Set retry count.*/ + TRNG_WR_SCMISC_RTY_CT(base, retry_count); + status = kStatus_Success; + } + else + { + status = kStatus_InvalidArgument; + } + return status; +} + +/*! + * @brief Sets statistical check limits. + * + * This function is used to set minimum and maximum limits of statistical checks. + * + */ +static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, + trng_statistical_check_t statistical_check, + const trng_statistical_check_limit_t *limit) +{ + uint32_t range; + status_t status = kStatus_Success; + + if (limit && (limit->maximum > limit->minimum)) + { + range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ + + switch (statistical_check) + { + case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during + entropy generation. */ + if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) + { + TRNG_WR_SCML_MONO_MAX(base, limit->maximum); + TRNG_WR_SCML_MONO_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected + during entropy generation. */ + if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) + { + TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); + TRNG_WR_SCR1L_RUN1_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected + during entropy generation. */ + if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) + { + TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); + TRNG_WR_SCR2L_RUN2_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected + during entropy generation. */ + if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) + { + TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); + TRNG_WR_SCR3L_RUN3_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected + during entropy generation. */ + if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) + { + TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); + TRNG_WR_SCR4L_RUN4_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected + during entropy generation. */ + if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) + { + TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); + TRNG_WR_SCR5L_RUN5_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected + during entropy generation */ + if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) + { + TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); + TRNG_WR_SCR6PL_RUN6P_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during + entropy generation . */ + if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) + { + TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); + TRNG_WR_PKRRNG_PKR_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + break; + case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency + count during entropy generation . */ + if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) + { + TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); + TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); + } + else + { + status = kStatus_InvalidArgument; + } + break; + default: + status = kStatus_InvalidArgument; + break; + } + } + + return status; +} + +/*FUNCTION********************************************************************* + * + * Function Name : trng_ApplyUserConfig + * Description : Apply user configuration settings to TRNG module. + * + *END*************************************************************************/ +static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig) +{ + status_t status; + + if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, + &userConfig->runBit6PlusLimit)) == kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) == + kStatus_Success) && + ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, + &userConfig->frequencyCountLimit)) == kStatus_Success)) + { + TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); + TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); + TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); + TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); + TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); + TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); + TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); + } + + return status; +} + +/*! + * @brief Gets a entry data from the TRNG. + * + * This function gets an entropy data from TRNG. + * Entropy data is spread over TRNG_ENT_COUNT registers. + * Read register number is defined by index parameter. +*/ +static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) +{ + uint32_t data; + + index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/ + + data = TRNG_RD_ENT(base, index); + + if (index == (TRNG_ENT_COUNT - 1)) + { + /* Dummy read. Defect workaround. + * TRNG could not clear ENT_VAL flag automatically, application + * had to do a dummy reading operation for anyone TRNG register + * to clear it firstly, then to read the RTENT0 to RTENT15 again */ + index = TRNG_RD_ENT(base, 0); + } + + return data; +} + +status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) +{ + status_t result; + + /* Check input parameters.*/ + if ((base != NULL) && (userConfig != NULL)) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock gate. */ + CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the registers of TRNG module to reset state. */ + /* Must be in program mode.*/ + TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); + /* Reset Defaults.*/ + TRNG_WR_MCTL_RST_DEF(base, 1); + + /* Set configuration.*/ + if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success) + { + /* Start entropy generation.*/ + /* Set to Run mode.*/ + TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); +#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) + /* Enable TRNG Access Mode. To generate an Entropy + * value that can be read via the true0-true15 registers.*/ + TRNG_WR_MCTL_TRNG_ACC(base, 1); +#endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ + + if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */ + { + TRNG_WR_SEC_CFG_NO_PRGM(base, 1); + } + + result = kStatus_Success; + } + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +void TRNG_Deinit(TRNG_Type *base) +{ + /* Check input parameters.*/ + if (base) + { + /* Move to program mode. Stop entropy generation.*/ + TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); + + /* Check before clock stop. + TRNG turns on the TRNG free-running ring oscillator whenever new entropy + is being generated and turns off the ring oscillator when entropy generation + is complete. If the TRNG clock is stopped while the TRNG ring oscillator + is running, the oscillator continues running though the RNG clock. + is stopped. */ + while (TRNG_RD_MCTL_TSTOP_OK(base) == 0) + { + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable Clock*/ + CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +} + +status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) +{ + status_t result = kStatus_Success; + uint32_t random_32; + uint8_t *random_p; + uint32_t random_size; + uint8_t *data_p = (uint8_t *)data; + uint32_t i; + int index = 0; + + /* Check input parameters.*/ + if (base && data && dataSize) + { + do + { + /* Wait for Valid or Error flag*/ + while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0)) + { + } + + /* Check HW error.*/ + if (TRNG_RD_MCTL_ERR(base)) + { + result = kStatus_Fail; /* TRNG module error occurred */ + /* Clear error.*/ + TRNG_WR_MCTL_ERR(base, 1); + break; /* No sense stay here.*/ + } + + /* Read Entropy.*/ + random_32 = trng_ReadEntropy(base, index++); + + random_p = (uint8_t *)&random_32; + + if (dataSize < sizeof(random_32)) + { + random_size = dataSize; + } + else + { + random_size = sizeof(random_32); + } + + for (i = 0U; i < random_size; i++) + { + *data_p++ = *random_p++; + } + + dataSize -= random_size; + } while (dataSize > 0); + + /* Start a new entropy generation. + It is done by reading of the last entropy register.*/ + if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1)) + { + trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); + } + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_trng.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_trng.h new file mode 100644 index 0000000000..de844e892e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_trng.h @@ -0,0 +1,245 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_TRNG_DRIVER_H_ +#define _FSL_TRNG_DRIVER_H_ + +#include "fsl_common.h" + +#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT + +/*! + * @addtogroup trng + * @{ + */ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief TRNG driver version 2.0.2. + * + * Current version: 2.0.2 + * + * Change log: + * - Version 2.0.2 + * - fix MISRA issues + * - Version 2.0.1 + * - add support for KL8x and KL28Z + * - update default OSCDIV for K81 to divide by 2 + */ +#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief TRNG sample mode. Used by trng_config_t. */ +typedef enum _trng_sample_mode +{ + kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ + kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ + kTRNG_SampleModeVonNeumannRaw = + 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ +} trng_sample_mode_t; + +/*! @brief TRNG clock mode. Used by trng_config_t. */ +typedef enum _trng_clock_mode +{ + kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ + kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and + indeterminate results may occur. */ +} trng_clock_mode_t; + +/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */ +typedef enum _trng_ring_osc_div +{ + kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */ + kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */ + kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */ + kTRNG_RingOscDiv8 = 3U /*!< Ring oscillator divided-by-8. */ +} trng_ring_osc_div_t; + +/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */ +typedef struct _trng_statistical_check_limit +{ + uint32_t maximum; /*!< Maximum limit.*/ + uint32_t minimum; /*!< Minimum limit.*/ +} trng_statistical_check_limit_t; + +/*! + * @brief Data structure for the TRNG initialization + * + * This structure initializes the TRNG by calling the TRNG_Init() function. + * It contains all TRNG configurations. + */ +typedef struct _trng_user_config +{ + bool lock; /*!< @brief Disable programmability of TRNG registers. */ + trng_clock_mode_t clockMode; /*!< @brief Clock mode used to operate TRNG.*/ + trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */ + trng_sample_mode_t sampleMode; /*!< @brief Sample mode of the TRNG ring oscillator. */ + /* Seed Control*/ + uint16_t + entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ + uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during + Entropy generation. */ + uint16_t + sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of + * consecutive samples that may be discarded before an error is generated. + * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()). + * Samples are discarded if two consecutive raw samples are both 0 or both 1. If + * this discarding occurs for a long period of time, it indicates that there is + * insufficient Entropy. */ + /* Statistical Check Parameters.*/ + uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails + * during the TRNG Entropy Generation before generating an error. */ + uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, + * that is allowed during the Entropy generation. */ + trng_statistical_check_limit_t + monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected + during entropy generation. */ + trng_statistical_check_limit_t + runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1 + detected during entropy generation. */ + trng_statistical_check_limit_t + runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2 + detected during entropy generation. */ + trng_statistical_check_limit_t + runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3 + detected during entropy generation. */ + trng_statistical_check_limit_t + runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4 + detected during entropy generation. */ + trng_statistical_check_limit_t + runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5 + detected during entropy generation. */ + trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of + number of runs of length 6 or more detected during entropy + generation. */ + trng_statistical_check_limit_t + pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ + trng_statistical_check_limit_t + frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency + count. */ +} trng_config_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the user configuration structure to default values. + * + * This function initializes the configuration structure to default values. The default + * values are as follows. + * @code + * user_config->lock = 0; + * user_config->clockMode = kTRNG_ClockModeRingOscillator; + * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. + * user_config->sampleMode = kTRNG_SampleModeRaw; + * user_config->entropyDelay = 3200; + * user_config->sampleSize = 2500; + * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; + * user_config->retryCount = 63; + * user_config->longRunMaxLimit = 34; + * user_config->monobitLimit.maximum = 1384; + * user_config->monobitLimit.minimum = 1116; + * user_config->runBit1Limit.maximum = 405; + * user_config->runBit1Limit.minimum = 227; + * user_config->runBit2Limit.maximum = 220; + * user_config->runBit2Limit.minimum = 98; + * user_config->runBit3Limit.maximum = 125; + * user_config->runBit3Limit.minimum = 37; + * user_config->runBit4Limit.maximum = 75; + * user_config->runBit4Limit.minimum = 11; + * user_config->runBit5Limit.maximum = 47; + * user_config->runBit5Limit.minimum = 1; + * user_config->runBit6PlusLimit.maximum = 47; + * user_config->runBit6PlusLimit.minimum = 1; + * user_config->pokerLimit.maximum = 26912; + * user_config->pokerLimit.minimum = 24445; + * user_config->frequencyCountLimit.maximum = 25600; + * user_config->frequencyCountLimit.minimum = 1600; + * @endcode + * + * @param user_config User configuration structure. + * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ +status_t TRNG_GetDefaultConfig(trng_config_t *userConfig); + +/*! + * @brief Initializes the TRNG. + * + * This function initializes the TRNG. + * When called, the TRNG entropy generation starts immediately. + * + * @param base TRNG base address + * @param userConfig Pointer to the initialization configuration structure. + * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ +status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig); + +/*! + * @brief Shuts down the TRNG. + * + * This function shuts down the TRNG. + * + * @param base TRNG base address. + */ +void TRNG_Deinit(TRNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the TRNG. + * + * @param base TRNG base address. + * @param data Pointer address used to store random data. + * @param dataSize Size of the buffer pointed by the data parameter. + * @return random data + */ +status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ +#endif /*_FSL_TRNG_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_tsc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_tsc.c new file mode 100644 index 0000000000..75f5c62d21 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_tsc.c @@ -0,0 +1,221 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_tsc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tsc" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for TSC module. + * + * @param base TSC peripheral base address + */ +static uint32_t TSC_GetInstance(TSC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to TSC bases for each instance. */ +static TSC_Type *const s_tscBases[] = TSC_BASE_PTRS; + +/*! @brief Pointers to ADC clocks for each instance. */ +static const clock_ip_name_t s_tscClocks[] = TSC_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t TSC_GetInstance(TSC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_tscBases); instance++) + { + if (s_tscBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_tscBases)); + + return instance; +} + +void TSC_Init(TSC_Type *base, const tsc_config_t *config) +{ + assert(NULL != config); + assert(config->measureDelayTime <= 0xFFFFFFU); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the TSC clock. */ + CLOCK_EnableClock(s_tscClocks[TSC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Configure TSC_BASIC_SETTING register. */ + tmp32 = TSC_BASIC_SETTING_MEASURE_DELAY_TIME(config->measureDelayTime) | + TSC_BASIC_SETTING__4_5_WIRE(config->detectionMode); + if (config->enableAutoMeasure) + { + tmp32 |= TSC_BASIC_SETTING_AUTO_MEASURE_MASK; + } + base->BASIC_SETTING = tmp32; + /* Configure TSC_PS_INPUT_BUFFER_ADDR register. */ + base->PRE_CHARGE_TIME = TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(config->prechargeTime); +} + +void TSC_Deinit(TSC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the TSC clcok. */ + CLOCK_DisableClock(s_tscClocks[TSC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void TSC_GetDefaultConfig(tsc_config_t *config) +{ + config->enableAutoMeasure = false; + config->measureDelayTime = 0xFFFFU; + config->prechargeTime = 0xFFFFU; + config->detectionMode = kTSC_Detection4WireMode; +} + +uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection) +{ + uint32_t tmp32 = 0; + + if (selection == kTSC_XCoordinateValueSelection) + { + tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_X_VALUE_MASK) >> TSC_MEASEURE_VALUE_X_VALUE_SHIFT; + } + else if (selection == kTSC_YCoordinateValueSelection) + { + tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) >> TSC_MEASEURE_VALUE_Y_VALUE_SHIFT; + } + else + { + } + return tmp32; +} + +void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable) +{ + if (enable) + { + /* TSC_DEBUG_MODE_EXT_HWTS field should be writed before writing TSC_DEBUG_MODE_TRIGGER field. + If the two fields are writed at the same time, the trigger couldn't work as expect. */ + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_EXT_HWTS_MASK; + base->DEBUG_MODE |= TSC_DEBUG_MODE_EXT_HWTS(hwts); + base->DEBUG_MODE |= TSC_DEBUG_MODE_TRIGGER_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_TRIGGER_MASK; + } +} + +void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable) +{ + if (detectionMode == kTSC_Detection4WireMode) + { + if (enable) + { + base->DEBUG_MODE2 |= TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK; + } + else + { + base->DEBUG_MODE2 &= ~TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK; + } + } + else if (detectionMode == kTSC_Detection5WireMode) + { + if (enable) + { + base->DEBUG_MODE2 |= TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK; + } + else + { + base->DEBUG_MODE2 &= ~TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK; + } + } + else + { + } +} + +void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode) +{ + uint32_t tmp32; + + tmp32 = base->DEBUG_MODE2; + switch (port) + { + case kTSC_WiperPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK | + TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT); + break; + case kTSC_YnlrPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK | + TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT); + break; + case kTSC_YpllPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK | + TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT); + break; + case kTSC_XnurPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK | + TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT); + break; + case kTSC_XpulPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK | + TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT); + break; + default: + break; + } + base->DEBUG_MODE2 = tmp32; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_tsc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_tsc.h new file mode 100644 index 0000000000..84ea320633 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_tsc.h @@ -0,0 +1,548 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_TSC_H_ +#define _FSL_TSC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup tsc + * @{ + */ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! @brief TSC driver version */ +#define FSL_TSC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! +* @ Controller detection mode. +*/ +typedef enum _tsc_detection_mode +{ + kTSC_Detection4WireMode = 0U, /*!< 4-Wire Detection Mode. */ + kTSC_Detection5WireMode = 1U, /*!< 5-Wire Detection Mode. */ +} tsc_detection_mode_t; + +/*! +* @ Coordinate value mask. +*/ +typedef enum _tsc_corrdinate_value_selection +{ + kTSC_XCoordinateValueSelection = 0U, /*!< X coordinate value is selected. */ + kTSC_YCoordinateValueSelection = 1U, /*!< Y coordinate value is selected. */ +} tsc_corrdinate_value_selection_t; + +/*! +* @ Interrupt signal enable/disable mask. +*/ +enum _tsc_interrupt_signal_mask +{ + kTSC_IdleSoftwareSignalEnable = TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK, /*!< Enable the interrupt signal when the + controller has return to idle status. + The signal is only valid after using + TSC_ReturnToIdleStatus API. */ + kTSC_ValidSignalEnable = + TSC_INT_SIG_EN_VALID_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal + after measurement. */ + kTSC_DetectSignalEnable = + TSC_INT_SIG_EN_DETECT_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal. */ + kTSC_MeasureSignalEnable = TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK, /*!< Enable the interrupt signal after the touch + detection which follows measurement. */ +}; + +/*! +* @ Interrupt enable/disable mask. +*/ +enum _tsc_interrupt_mask +{ + kTSC_IdleSoftwareInterruptEnable = + TSC_INT_EN_IDLE_SW_INT_EN_MASK, /*!< Enable the interrupt when the controller has return to idle status. + The interrupt is only valid after using TSC_ReturnToIdleStatus API. */ + kTSC_DetectInterruptEnable = + TSC_INT_EN_DETECT_INT_EN_MASK, /*!< Enable the interrupt when controller receive a detect signal. */ + kTSC_MeasureInterruptEnable = TSC_INT_EN_MEASURE_INT_EN_MASK, /*!< Enable the interrupt after the touch detection + which follows measurement. */ +}; + +/*! +* @ Interrupt Status flag mask. +*/ +enum _tsc_interrupt_status_flag_mask +{ + kTSC_IdleSoftwareFlag = + TSC_INT_STATUS_IDLE_SW_MASK, /*!< This flag is set if the controller has return to idle status. + The flag is only valid after using TSC_ReturnToIdleStatus API. */ + kTSC_ValidSignalFlag = + TSC_INT_STATUS_VALID_MASK, /*!< This flag is set if controller receives a detect signal after measurement. */ + kTSC_DetectSignalFlag = TSC_INT_STATUS_DETECT_MASK, /*!< This flag is set if controller receives a detect signal. */ + kTSC_MeasureSignalFlag = + TSC_INT_STATUS_MEASURE_MASK, /*!< This flag is set after the touch detection which follows measurement. + Note: Valid signal falg will be cleared along with measure signal flag. */ +}; + +/*! +* @ ADC status flag mask. +*/ +enum _tsc_adc_status_flag_mask +{ + kTSC_ADCCOCOSignalFlag = + TSC_DEBUG_MODE_ADC_COCO_MASK, /*!< This signal is generated by ADC when a conversion is completed. */ + kTSC_ADCConversionValueFlag = + TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK, /*!< This signal is generated by ADC and indicates the result of an ADC + conversion. */ +}; + +/*! +* @ TSC status flag mask. +*/ +enum _tsc_status_flag_mask +{ + kTSC_IntermediateStateFlag = TSC_DEBUG_MODE2_INTERMEDIATE_MASK, /*!< This flag is set if TSC is in intermediate + state, between two state machine states. */ + kTSC_DetectFiveWireFlag = TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK, /*!< This flag is set if TSC receives a 5-wire + detect signal. It is only valid when the TSC in + detect state and DETECT_ENABLE_FIVE_WIRE bit is + set. */ + kTSC_DetectFourWireFlag = TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK, /*!< This flag is set if TSC receives a 4-wire + detect signal. It is only valid when the TSC in + detect state and DETECT_ENABLE_FOUR_WIRE bit is + set. */ + kTSC_GlitchThresholdFlag = TSC_DEBUG_MODE2_DE_GLITCH_MASK, /*!< This field indicates glitch threshold.The threshold + is defined by number of clock cycles. See + "tsc_glitch_threshold_t". + If value = 00, Normal function: 0x1fff ipg clock + cycles, Low power mode: 0x9 low power clock cycles. + If value = 01, Normal function: 0xfff ipg clock + cycles, Low power mode: :0x7 low power clock cycles. + If value = 10, Normal function: 0x7ff ipg clock + cycles, Low power mode:0x5 low power clock cycles. + If value = 11, Normal function: 0x3 ipg clock + cycles, Low power mode:0x3 low power clock cycles. */ + kTSC_StateMachineFlag = + TSC_DEBUG_MODE2_STATE_MACHINE_MASK, /*!< This field indicates the state of TSC. See "tsc_state_machine_t"; + if value = 000, Controller is in idle state. + if value = 001, Controller is in 1st-Pre-charge state. + if value = 010, Controller is in 1st-detect state. + if value = 011, Controller is in x-measure state. + if value = 100, Controller is in y-measure state. + if value = 101, Controller is in 2nd-Pre-charge state. + if value = 110, Controller is in 2nd-detect state. */ +}; + +/*! +* @brief TSC state machine. These seven states are TSC complete workflow. +*/ +typedef enum _tsc_state_machine +{ + kTSC_IdleState = 0U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in idle state. */ + kTSC_1stPreChargeState = 1U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-Pre-charge state. */ + kTSC_1stDetectState = 2U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-detect state. */ + kTSC_XMeasureState = 3U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in x-measure state. */ + kTSC_YMeasureState = 4U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in y-measure state. */ + kTSC_2ndPreChargeState = 5U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-Pre-charge state. */ + kTSC_2ndDetectState = 6U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-detect state. */ +} tsc_state_machine_t; + +/*! +* @brief TSC glitch threshold. +*/ +typedef enum _tsc_glitch_threshold +{ + kTSC_glitchThresholdALT0 = + 0U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x1fff ipg clock cycles, Low power mode: 0x9 low + power clock cycles. */ + kTSC_glitchThresholdALT1 = + 1U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0xfff ipg clock cycles, Low power mode: :0x7 low + power clock cycles. */ + kTSC_glitchThresholdALT2 = + 2U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x7ff ipg clock cycles, Low power mode: :0x5 low + power clock cycles. */ + kTSC_glitchThresholdALT3 = + 3U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x3 ipg clock cycles, Low + power mode: :0x3 low power clock cycles. */ +} tsc_glitch_threshold_t; + +/*! +* @ Hardware trigger select signal, select which ADC channel to start conversion. +*/ +typedef enum _tsc_trigger_signal +{ + kTSC_TriggerToChannel0 = 1U << 0U, /*!< Trigger to ADC channel0. ADC_HC0 register will be used to conversion. */ + kTSC_TriggerToChannel1 = 1U << 1U, /*!< Trigger to ADC channel1. ADC_HC1 register will be used to conversion. */ + kTSC_TriggerToChannel2 = 1U << 2U, /*!< Trigger to ADC channel2. ADC_HC2 register will be used to conversion. */ + kTSC_TriggerToChannel3 = 1U << 3U, /*!< Trigger to ADC channel3. ADC_HC3 register will be used to conversion. */ + kTSC_TriggerToChannel4 = 1U << 4U, /*!< Trigger to ADC channel4. ADC_HC4 register will be used to conversion. */ +} tsc_trigger_signal_t; + +/*! +* @ TSC controller ports. +*/ +typedef enum _tsc_port_source +{ + kTSC_WiperPortSource = 0U, /*!< TSC controller wiper port. */ + kTSC_YnlrPortSource = 1U, /*!< TSC controller ynlr port. */ + kTSC_YpllPortSource = 2U, /*!< TSC controller ypll port. */ + kTSC_XnurPortSource = 3U, /*!< TSC controller xnur port. */ + kTSC_XpulPortSource = 4U, /*!< TSC controller xpul port. */ +} tsc_port_source_t; + +/*! +* @ TSC port mode. +*/ +typedef enum _tsc_port_mode +{ + kTSC_PortOffMode = 0U, /*!< Disable pull up/down mode. */ + kTSC_Port200k_PullUpMode = 1U << 2U, /*!< 200k-pull up mode. */ + kTSC_PortPullUpMode = 1U << 1U, /*!< Pull up mode. */ + kTSC_PortPullDownMode = 1U << 0U, /*!< Pull down mode. */ +} tsc_port_mode_t; + +/*! +* @ Controller configuration. +*/ +typedef struct _tsc_config +{ + bool enableAutoMeasure; /*!< Enable the auto-measure. It indicates after detect touch, whether automatic start + measurement */ + uint32_t measureDelayTime; /*!< Set delay time(0U~0xFFFFFFU) to even potential distribution ready.It is a + preparation for measure stage. If measure dalay time is too short, maybe it would + have an undesired effect on measure value. */ + uint32_t prechargeTime; /*!< Set pre-charge time(1U~0xFFFFFFFFU) to make the upper layer of + screen to charge to positive high. It is a preparation for detection stage. + Pre-charge time must is greater than 0U, otherwise TSC could not work normally. + If pre-charge dalay time is too short, maybe it would have an undesired effect on + generation of valid signal(kTSC_ValidSignalFlag).*/ + tsc_detection_mode_t detectionMode; /*!< Select the detection mode. See "tsc_detection_mode_t". */ +} tsc_config_t; + +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! +* @brief Initialize the TSC module. +* +* @param base TSC peripheral base address. +* @param config Pointer to "tsc_config_t" structure. +*/ +void TSC_Init(TSC_Type *base, const tsc_config_t *config); + +/*! +* @brief De-initializes the TSC module. +* +* @param base TSC peripheral base address. +*/ +void TSC_Deinit(TSC_Type *base); + +/*! +* @brief Gets an available pre-defined settings for the controller's configuration. +* +* This function initializes the converter configuration structure with available settings. +* The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally. +* The default values are: +* @code +* config->enableAutoMeausre = false; +* config->measureDelayTime = 0xFFFFU; +* config->prechargeTime = 0xFFFFU; +* config->detectionMode = kTSC_4WireDetectionMode; +* @endCode +* @param config Pointer to "tsc_config_t" structure. +*/ +void TSC_GetDefaultConfig(tsc_config_t *config); + +/*! +* @brief Make the TSC module return to idle status after finish the current state operation. +* Application could check TSC status to confirm that the controller has return to idle status. +* +* @param base TSC peripheral base address. +*/ +static inline void TSC_ReturnToIdleStatus(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_DISABLE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_DISABLE_MASK; +} + +/*! +* @brief Start sense detection and (if work in auto-measure mode) measure after detect a touch. +* +* @param base TSC peripheral base address. +*/ +static inline void TSC_StartSenseDetection(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_START_SENSE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_START_SENSE_MASK; +} + +/*! +* @brief start measure X/Y coordinate value after detect a touch. +* +* @param base TSC peripheral base address. +*/ +static inline void TSC_StartMeasure(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_START_MEASURE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_START_MEASURE_MASK; +} + +/*! +* @brief Drop measure X/Y coordinate value after detect a touch and controller return to idle status. +* +* @param base TSC peripheral base address. +*/ +static inline void TSC_DropMeasure(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_DROP_MEASURE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_DROP_MEASURE_MASK; +} + +/*! +* @brief This is a synchronization reset, which resets every register except IPS directly access ones. +* +* @param base TSC peripheral base address. +*/ +static inline void TSC_SoftwareReset(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_SW_RST_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_SW_RST_MASK; +} + +/*! +* @brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value. +* +* @param base TSC peripheral base address. +* @param selection Select alternative measure value which is Y coordinate value or X coordinate value. +* See "tsc_corrdinate_value_selection_t". +* @return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue. +* If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue. +*/ +uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection); + +/*! +* @brief Enable the interrupt signals. Interrupt signal will be set when corresponding event happens. +* Specific events point to "_tsc_interrupt_signal_mask" . +* Specific interrupt signal point to "_tsc_interrupt_status_flag_mask"; +* +* @param base TSC peripheral base address. +* @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask". +*/ +static inline void TSC_EnableInterruptSignals(TSC_Type *base, uint32_t mask) +{ + base->INT_SIG_EN |= mask; +} + +/*! +* @brief Disable the interrupt signals. Interrupt signal will be set when corresponding event happens. +* Specific events point to "_tsc_interrupt_signal_mask". +* Specific interrupt signal point to "_tsc_interrupt_status_flag_mask"; +* +* @param base TSC peripheral base address. +* @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask". +*/ +static inline void TSC_DisableInterruptSignals(TSC_Type *base, uint32_t mask) +{ + base->INT_SIG_EN &= ~mask; +} + +/*! +* @brief Enable the interrupts. Notice: Only interrupts and signals are all enabled, interrupts +* could work normally. +* +* @param base TSC peripheral base address. +* @param mask Interrupts mask. See "_tsc_interrupt_mask". +*/ +static inline void TSC_EnableInterrupts(TSC_Type *base, uint32_t mask) +{ + base->INT_EN |= mask; +} + +/*! +* @brief Disable the interrupts. +* +* @param base TSC peripheral base address. +* @param mask Interrupts mask. See "_tsc_interrupt_mask". +*/ +static inline void TSC_DisableInterrupts(TSC_Type *base, uint32_t mask) +{ + base->INT_EN &= ~mask; +} + +/*! +* @brief Get interrupt status flags. Interrupt status falgs are valid when corresponding +* interrupt signals are enabled. +* +* @param base TSC peripheral base address. +* @return Status flags asserted mask. See "_tsc_interrupt_status_flag_mask". +*/ +static inline uint32_t TSC_GetInterruptStatusFlags(TSC_Type *base) +{ + return base->INT_STATUS; +} + +/*! +* @brief Clear interrupt status flags. Interrupt status falgs are valid when corresponding +* interrupt signals are enabled. +* +* @param base TSC peripheral base address. +* @param mask Status flags mask. See "_tsc_interrupt_status_flag_mask". +*/ +static inline void TSC_ClearInterruptStatusFlags(TSC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! +* @brief Get the status flags of ADC working with TSC. +* +* @param base TSC peripheral base address. +* @return Status flags asserted mask. See "_tsc_adc_status_flag_mask". +*/ +static inline uint32_t TSC_GetADCStatusFlags(TSC_Type *base) +{ + return base->DEBUG_MODE; +} + +/*! +* @brief Get the status flags of TSC. +* +* @param base TSC peripheral base address. +* @return Status flags asserted mask. See "_tsc_status_flag_mask". +*/ +static inline uint32_t TSC_GetStatusFlags(TSC_Type *base) +{ + return base->DEBUG_MODE2; +} + +/*! + *@} + */ + +/******************************************************************************* + * Debug API + ******************************************************************************/ + +/*! +* @brief Enable/Disable debug mode. Once work in debug mode, then all +* TSC outputs will be controlled by software. Software can also observe all TSC inputs +* through debug interface. Furthermore, the debug registers also provides current state +* machine states. Software can always check the current hardware state. +* +* @param base TSC peripheral base address. +* @param enable Switcher of the debug mode. "true" means debug mode,"false" means non-debug mode. +*/ +static inline void TSC_EnableDebugMode(TSC_Type *base, bool enable) +{ + if (enable) + { + base->DEBUG_MODE |= TSC_DEBUG_MODE_DEBUG_EN_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_DEBUG_EN_MASK; + } +} + +/*! +* @brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period. +* +* @param base TSC peripheral base address. +* @param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t". +* On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion. +* @param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate +* trigger signal. +*/ +void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable); + +/*! +* @brief Enable/Disable hardware generates an ADC COCO clear signal in debug mode. +* +* @param base TSC peripheral base address. +* @param enable Switcher of the function of hardware generating an ADC COCO clear signal. +* "true" means prevent TSC from generate ADC COCO clear signal. +* "false" means allow TSC hardware generates ADC COCO clear. +*/ +static inline void TSC_DebugDisableHWClear(TSC_Type *base, bool enable) +{ + if (enable) + { + base->DEBUG_MODE |= TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK; + } +} + +/*! +* @brief Send clear ADC COCO signal to ADC in debug mode. The signal must hold a while. +* +* @param base TSC peripheral base address. +* @param enable Switcher of the clear signal."true" means generate clear signal, "false" means don't generate +* clear signal. +*/ +static inline void TSC_DebugClearSignalToADC(TSC_Type *base, bool enable) +{ + if (enable) + { + base->DEBUG_MODE |= TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK; + } +} + +/*! +* @brief Enable/Disable detection in debug mode. +* +* @param base TSC peripheral base address. +* @param detectionMode Set detect mode. See "tsc_detection_mode_t" +* @param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection. +*/ +void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable); + +/*! +* @brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up) +* +* @param base TSC peripheral base address. +* @param port TSC controller ports. +* @param mode TSC port mode.(pull down, pull up and 200k-pull up) +*/ +void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode); +#endif /* _FSL_TSC_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_usdhc.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_usdhc.c new file mode 100644 index 0000000000..d5145ff5cf --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_usdhc.c @@ -0,0 +1,1796 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_usdhc.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.usdhc" +#endif + +/*! @brief Clock setting */ +/* Max SD clock divisor from base clock */ +#define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) +#define USDHC_MAX_CLKFS ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U) +#define USDHC_PREV_DVS(x) ((x) -= 1U) +#define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) + +/* Typedef for interrupt handler. */ +typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); +/*! @brief Dummy data buffer for mmc boot mode */ +AT_NONCACHEABLE_SECTION_ALIGN(uint32_t s_usdhcBootDummy, USDHC_ADMA2_ADDRESS_ALIGN); +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base USDHC peripheral base address. + * @return Instance number. + */ +static uint32_t USDHC_GetInstance(USDHC_Type *base); + +/*! + * @brief Set transfer interrupt. + * + * @param base USDHC peripheral base address. + * @param usingInterruptSignal True to use IRQ signal. + */ +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal); + +/*! + * @brief Start transfer according to current transfer state + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @param flag data present flag + */ +static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag); + +/*! + * @brief Receive command response + * + * @param base USDHC peripheral base address. + * @param command Command to be sent. + */ +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Read DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time transaction. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Read data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @retval kStatus_Fail Read DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Write DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Write data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Write DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Transfer data by polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @param use DMA flag. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA); + +/*! + * @brief Handle card detect interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Card detect related interrupt flags. + */ +static void USDHC_TransferHandleCardDetect(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle command interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Command related interrupt flags. + */ +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle data interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Data related interrupt flags. + */ +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle SDIO card interrupt signal. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *handle); + +/*! + * @brief Handle SDIO block gap event. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle); + +/*! +* @brief Handle retuning +* +* @param base USDHC peripheral base address. +* @param handle USDHC handle. +* @param interrupt flags +*/ +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! +* @brief wait command done +* +* @param base USDHC peripheral base address. +* @param command configuration +* @param pollingCmdDone polling command done flag +*/ +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USDHC base pointer array */ +static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS; + +/*! @brief USDHC internal handle pointer array */ +static usdhc_handle_t *s_usdhcHandle[ARRAY_SIZE(s_usdhcBase)] = {NULL}; + +/*! @brief USDHC IRQ name array */ +static const IRQn_Type s_usdhcIRQ[] = USDHC_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief USDHC clock array name */ +static const clock_ip_name_t s_usdhcClock[] = USDHC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* USDHC ISR for transactional APIs. */ +static usdhc_isr_t s_usdhcIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t USDHC_GetInstance(USDHC_Type *base) +{ + uint8_t instance = 0; + + while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_usdhcBase)); + + return instance; +} + +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal) +{ + uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ + + /* Disable all interrupts */ + USDHC_DisableInterruptStatus(base, (uint32_t)kUSDHC_AllInterruptFlags); + USDHC_DisableInterruptSignal(base, (uint32_t)kUSDHC_AllInterruptFlags); + DisableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); + + interruptEnabled = (kUSDHC_CommandFlag | kUSDHC_CardInsertionFlag | kUSDHC_DataFlag | kUSDHC_CardRemovalFlag | + kUSDHC_SDR104TuningFlag | kUSDHC_BlockGapEventFlag); + + USDHC_EnableInterruptStatus(base, interruptEnabled); + + if (usingInterruptSignal) + { + USDHC_EnableInterruptSignal(base, interruptEnabled); + } +} + +static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag) +{ + uint32_t mixCtrl = base->MIX_CTRL; + + if (data != NULL) + { + /* if transfer boot continous, only need set the CREQ bit, leave others as it is */ + if (data->dataType == kUSDHC_TransferDataBootcontinous) + { + /* clear stop at block gap request */ + base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; + /* continous transfer data */ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; + return kStatus_Success; + } + + /* check data inhibit flag */ + if (base->PRES_STATE & kUSDHC_DataInhibitFlag) + { + return kStatus_USDHC_BusyTransferring; + } + /* check transfer block count */ + if ((data->blockCount > USDHC_MAX_BLOCK_COUNT) || ((data->txData == NULL) && (data->rxData == NULL))) + { + return kStatus_InvalidArgument; + } + + /* config mix parameter */ + mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK); + + if (data->rxData) + { + mixCtrl |= USDHC_MIX_CTRL_DTDSEL_MASK; + } + if (data->blockCount > 1U) + { + mixCtrl |= USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK; + /* auto command 12 */ + if (data->enableAutoCommand12) + { + mixCtrl |= USDHC_MIX_CTRL_AC12EN_MASK; + } + } + + /* auto command 23, auto send set block count cmd before multiple read/write */ + if ((data->enableAutoCommand23)) + { + mixCtrl |= USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + /* config the block count to DS_ADDR */ + base->DS_ADDR = data->blockCount; + } + else + { + mixCtrl &= ~USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + } + + /* if transfer boot data, leave the block count to USDHC_SetMmcBootConfig function */ + if (data->dataType != kUSDHC_TransferDataBoot) + { + /* config data block size/block count */ + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(data->blockSize) | USDHC_BLK_ATT_BLKCNT(data->blockCount))); + } + else + { + mixCtrl |= USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK; + base->PROT_CTRL |= USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK; + } + + /* data present flag */ + *dataPresentFlag |= kUSDHC_DataPresentFlag; + } + else + { + /* clear data flags */ + mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK); + + if (base->PRES_STATE & kUSDHC_CommandInhibitFlag) + { + return kStatus_USDHC_BusyTransferring; + } + } + + /* config the mix parameter */ + base->MIX_CTRL = mixCtrl; + + return kStatus_Success; +} + +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command) +{ + uint32_t i; + + if (command->responseType != kCARD_ResponseTypeNone) + { + command->response[0U] = base->CMD_RSP0; + if (command->responseType == kCARD_ResponseTypeR2) + { + command->response[1U] = base->CMD_RSP1; + command->response[2U] = base->CMD_RSP2; + command->response[3U] = base->CMD_RSP3; + + i = 4U; + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + do + { + command->response[i - 1U] <<= 8U; + if (i > 1U) + { + command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); + } + } while (i--); + } + } + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && + ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || + (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return kStatus_USDHC_SendCommandFailed; + } + } + + return kStatus_Success; +} + +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >> USDHC_WTMK_LVL_RD_WML_SHIFT); + + /* If DMA is enable, do not need to polling data port */ + if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U) + { + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers + left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = USDHC_ReadData(base); + i++; + } + } + + return transferredWords; +} + +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(interruptStatus & (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + /* during std tuning process, software do not need to read data, but wait BRR is enough */ + if ((data->dataType == kUSDHC_TransferDataTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); + + return kStatus_Success; + } + else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_ReadDataPort(base, data, transferredWords); + /* clear buffer read ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); + interruptStatus = 0U; + } + } + + /* Clear data complete flag after the last read operation. */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataCompleteFlag); + + return error; +} + +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ + uint32_t writeWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >> USDHC_WTMK_LVL_WR_WML_SHIFT); + + /* If DMA is enable, do not need to polling data port */ + if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U) + { + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ + if (writeWatermark >= totalWords) + { + wordsCanBeWrote = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrote = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left + words. */ + else + { + wordsCanBeWrote = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrote) + { + USDHC_WriteData(base, data->txData[transferredWords++]); + i++; + } + } + + return transferredWords; +} + +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(interruptStatus & (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + return kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_WriteDataPort(base, data, transferredWords); + /* clear buffer write ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); + interruptStatus = 0U; + } + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while (!(interruptStatus & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag)); + + return error; +} + +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) +{ + assert(NULL != command); + + uint32_t xferType = base->CMD_XFR_TYP, flags = command->flags; + + if (((base->PRES_STATE & kUSDHC_CommandInhibitFlag) == 0U) && (command->type != kCARD_CommandTypeEmpty)) + { + /* Define the flag corresponding to each response type. */ + switch (command->responseType) + { + case kCARD_ResponseTypeNone: + break; + case kCARD_ResponseTypeR1: /* Response 1 */ + case kCARD_ResponseTypeR5: /* Response 5 */ + case kCARD_ResponseTypeR6: /* Response 6 */ + case kCARD_ResponseTypeR7: /* Response 7 */ + flags |= (kUSDHC_ResponseLength48Flag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR1b: /* Response 1 with busy */ + case kCARD_ResponseTypeR5b: /* Response 5 with busy */ + flags |= (kUSDHC_ResponseLength48BusyFlag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR2: /* Response 2 */ + flags |= (kUSDHC_ResponseLength136Flag | kUSDHC_EnableCrcCheckFlag); + break; + + case kCARD_ResponseTypeR3: /* Response 3 */ + case kCARD_ResponseTypeR4: /* Response 4 */ + flags |= (kUSDHC_ResponseLength48Flag); + break; + + default: + break; + } + + if (command->type == kCARD_CommandTypeAbort) + { + flags |= kUSDHC_CommandTypeAbortFlag; + } + + /* config cmd index */ + xferType &= ~(USDHC_CMD_XFR_TYP_CMDINX_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | + USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK); + + xferType |= + (((command->index << USDHC_CMD_XFR_TYP_CMDINX_SHIFT) & USDHC_CMD_XFR_TYP_CMDINX_MASK) | + ((flags) & (USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | USDHC_CMD_XFR_TYP_CCCEN_MASK | + USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK))); + + /* config the command xfertype and argument */ + base->CMD_ARG = command->argument; + base->CMD_XFR_TYP = xferType; + } + + if (command->type == kCARD_CommandTypeEmpty) + { + /* disable CMD done interrupt for empty command */ + base->INT_SIGNAL_EN &= ~USDHC_INT_SIGNAL_EN_CCIEN_MASK; + } +} + +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone) +{ + assert(NULL != command); + + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + /* check if need polling command done or not */ + if (pollingCmdDone) + { + /* Wait command complete or USDHC encounters error. */ + while (!(interruptStatus & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_CommandErrorFlag) != 0U) + { + error = kStatus_Fail; + } + else + { + } + /* Receive response when command completes successfully. */ + if (error == kStatus_Success) + { + error = USDHC_ReceiveCommandResponse(base, command); + } + + USDHC_ClearInterruptStatusFlags( + base, (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag | kUSDHC_TuningErrorFlag)); + } + + return error; +} + +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA) +{ + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + + if (enDMA) + { + /* Wait data complete or USDHC encounters error. */ + while (!((interruptStatus & + (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag)))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if (((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U)) + { + if ((!(data->enableIgnoreError)) || (interruptStatus & kUSDHC_DataTimeoutFlag)) + { + error = kStatus_Fail; + } + } + else + { + } + /* load dummy data */ + if ((data->dataType == kUSDHC_TransferDataBootcontinous) && (error == kStatus_Success)) + { + *(data->rxData) = s_usdhcBootDummy; + } + + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | + kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); + } + else + { + if (data->rxData) + { + error = USDHC_ReadByDataPortBlocking(base, data); + } + else + { + error = USDHC_WriteByDataPortBlocking(base, data); + } + } + + return error; +} + +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) +{ + assert(config); + assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); + assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); + assert(config->writeBurstLen <= 16U); + + uint32_t proctl, sysctl, wml; + + /* Enable USDHC clock. */ + CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]); + + /* Reset USDHC. */ + USDHC_Reset(base, kUSDHC_ResetAll, 100U); + + proctl = base->PROT_CTRL; + wml = base->WTMK_LVL; + sysctl = base->SYS_CTRL; + + proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK); + /* Endian mode*/ + proctl |= USDHC_PROT_CTRL_EMODE(config->endianMode); + + /* Watermark level */ + wml &= ~(USDHC_WTMK_LVL_RD_WML_MASK | USDHC_WTMK_LVL_WR_WML_MASK | USDHC_WTMK_LVL_RD_BRST_LEN_MASK | + USDHC_WTMK_LVL_WR_BRST_LEN_MASK); + wml |= (USDHC_WTMK_LVL_RD_WML(config->readWatermarkLevel) | USDHC_WTMK_LVL_WR_WML(config->writeWatermarkLevel) | + USDHC_WTMK_LVL_RD_BRST_LEN(config->readBurstLen) | USDHC_WTMK_LVL_WR_BRST_LEN(config->writeBurstLen)); + + /* config the data timeout value */ + sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK; + sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout); + + base->SYS_CTRL = sysctl; + base->WTMK_LVL = wml; + base->PROT_CTRL = proctl; + +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable external DMA */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + /* disable internal DMA and DDR mode */ + base->MIX_CTRL &= ~(USDHC_MIX_CTRL_DMAEN_MASK | USDHC_MIX_CTRL_DDR_EN_MASK); + /* Enable interrupt status but doesn't enable interrupt signal. */ + USDHC_SetTransferInterrupt(base, false); +} + +void USDHC_Deinit(USDHC_Type *base) +{ + /* Disable clock. */ + CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]); +} + +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) +{ + base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); + /* Delay some time to wait reset success. */ + while ((base->SYS_CTRL & mask) != 0U) + { + if (timeout == 0U) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) +{ + assert(capability); + + uint32_t htCapability; + uint32_t maxBlockLength; + + htCapability = base->HOST_CTRL_CAP; + + /* Get the capability of USDHC. */ + maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT); + capability->maxBlockLength = (512U << maxBlockLength); + /* Other attributes not in HTCAPBLT register. */ + capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT; + capability->flags = (htCapability & (kUSDHC_SupportAdmaFlag | kUSDHC_SupportHighSpeedFlag | kUSDHC_SupportDmaFlag | + kUSDHC_SupportSuspendResumeFlag | kUSDHC_SupportV330Flag)); + capability->flags |= (htCapability & kUSDHC_SupportV300Flag); + capability->flags |= (htCapability & kUSDHC_SupportV180Flag); + capability->flags |= + (htCapability & (kUSDHC_SupportDDR50Flag | kUSDHC_SupportSDR104Flag | kUSDHC_SupportSDR50Flag)); + /* USDHC support 4/8 bit data bus width. */ + capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); +} + +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) +{ + assert(srcClock_Hz != 0U); + assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); + + uint32_t totalDiv = 0U; + uint32_t divisor = 0U; + uint32_t prescaler = 0U; + uint32_t sysctl = 0U; + uint32_t nearestFrequency = 0U; + + /* calucate total divisor first */ + if ((totalDiv = srcClock_Hz / busClock_Hz) > (USDHC_MAX_CLKFS * USDHC_MAX_DVS)) + { + return 0U; + } + + if (totalDiv != 0U) + { + /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ + if ((srcClock_Hz / totalDiv) > busClock_Hz) + { + totalDiv++; + } + + /* divide the total divisor to div and prescaler */ + if (totalDiv > USDHC_MAX_DVS) + { + prescaler = totalDiv / USDHC_MAX_DVS; + /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ + while (((USDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U)) + { + prescaler++; + } + /* calucate the divisor */ + divisor = totalDiv / prescaler; + /* fine tuning the divisor until divisor * prescaler >= totalDiv */ + while ((divisor * prescaler) < totalDiv) + { + divisor++; + } + + nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler; + } + else + { + /* in this situation , divsior and SDCLKFS can generate same clock + use SDCLKFS*/ + if ((USDHC_MAX_DVS % totalDiv) == 0U) + { + divisor = 0U; + prescaler = totalDiv; + } + else + { + divisor = (totalDiv / 2U) + 1U; /* make sure the output frequency not bigger than target value */ + prescaler = 2U; + } + nearestFrequency = srcClock_Hz / totalDiv; + } + } + /* in this condition , srcClock_Hz = busClock_Hz, */ + else + { + /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the + totoal divider = 2U */ + divisor = 0U; + prescaler = 0U; + nearestFrequency = srcClock_Hz; + } + + /* calucate the value write to register */ + if (divisor != 0U) + { + USDHC_PREV_DVS(divisor); + } + /* calucate the value write to register */ + if (prescaler != 0U) + { + USDHC_PREV_CLKFS(prescaler, 1U); + } + + /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ + sysctl = base->SYS_CTRL; + sysctl &= ~(USDHC_SYS_CTRL_DVS_MASK | USDHC_SYS_CTRL_SDCLKFS_MASK); + sysctl |= (USDHC_SYS_CTRL_DVS(divisor) | USDHC_SYS_CTRL_SDCLKFS(prescaler)); + base->SYS_CTRL = sysctl; + + /* Wait until the SD clock is stable. */ + while (!(base->PRES_STATE & USDHC_PRES_STATE_SDSTB_MASK)) + { + } + + return nearestFrequency; +} + +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) +{ + base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; + /* Delay some time to wait card become active state. */ + while ((base->SYS_CTRL & USDHC_SYS_CTRL_INITA_MASK) == USDHC_SYS_CTRL_INITA_MASK) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) +{ + uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >> USDHC_SYS_CTRL_SDCLKFS_SHIFT; + + if (enable) + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; + base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); + prescaler >>= 1U; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; + + if (prescaler == 0U) + { + prescaler += 1U; + } + else + { + prescaler <<= 1U; + } + } + + base->SYS_CTRL = (base->SYS_CTRL & (~USDHC_SYS_CTRL_SDCLKFS_MASK)) | USDHC_SYS_CTRL_SDCLKFS(prescaler); +} + +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) +{ + assert(config); + assert(config->ackTimeoutCount <= (USDHC_MMC_BOOT_DTOCV_ACK_MASK >> USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)); + assert(config->blockCount <= (USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK >> USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)); + + uint32_t mmcboot = base->MMC_BOOT; + + mmcboot &= ~(USDHC_MMC_BOOT_DTOCV_ACK_MASK | USDHC_MMC_BOOT_BOOT_MODE_MASK | USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK); + mmcboot |= USDHC_MMC_BOOT_DTOCV_ACK(config->ackTimeoutCount) | USDHC_MMC_BOOT_BOOT_MODE(config->bootMode); + + if (config->enableBootAck) + { + mmcboot |= USDHC_MMC_BOOT_BOOT_ACK_MASK; + } + if (config->enableAutoStopAtBlockGap) + { + mmcboot |= + USDHC_MMC_BOOT_AUTO_SABG_EN_MASK | USDHC_MMC_BOOT_BOOT_BLK_CNT(USDHC_MAX_BLOCK_COUNT - config->blockCount); + /* always set the block count to USDHC_MAX_BLOCK_COUNT to use auto stop at block gap feature */ + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(config->blockSize) | USDHC_BLK_ATT_BLKCNT(USDHC_MAX_BLOCK_COUNT))); + } + else + { + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(config->blockSize) | USDHC_BLK_ATT_BLKCNT(config->blockCount))); + } + + base->MMC_BOOT = mmcboot; +} + +status_t USDHC_SetADMA1Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) +{ + assert(NULL != admaTable); + assert(NULL != dataBufferAddr); + + uint32_t miniEntries, startEntries = 0U, + maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t); + usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(admaTable); + uint32_t i, dmaBufferLen = 0U; + const uint32_t *data = dataBufferAddr; + + if (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0U) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + return kStatus_USDHC_NotSupport; + } + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + /* make the data length as word-aligned */ + dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); + } + + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + miniEntries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + miniEntries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + + /* ADMA1 needs two descriptors to finish a transfer */ + miniEntries <<= 1U; + + if (miniEntries + startEntries > maxEntries) + { + return kStatus_OutOfRange; + } + + for (i = startEntries; i < (miniEntries + startEntries); i += 2U) + { + if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + dmaBufferLen = dataBytes; + } + + adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = (uint32_t)(data); + adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; + data += dmaBufferLen / sizeof(uint32_t); + dataBytes -= dmaBufferLen; + } + /* the end of the descriptor */ + adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; + + return kStatus_Success; +} + +status_t USDHC_SetADMA2Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) +{ + assert(NULL != admaTable); + assert(NULL != dataBufferAddr); + + uint32_t miniEntries, startEntries = 0U, + maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t); + usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(admaTable); + uint32_t i, dmaBufferLen = 0U; + const uint32_t *data = dataBufferAddr; + + if (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + /* make the data length as word-aligned */ + dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); + } + + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + miniEntries = dataBytes / USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + miniEntries = ((dataBytes / USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + /* calucate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor + data adress and data size is enough */ + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + for (i = 0U; i < maxEntries; i++) + { + if ((adma2EntryAddress[i].attribute & kUSDHC_Adma2DescriptorValidFlag) == 0U) + { + break; + } + } + startEntries = i; + /* add one entry for dummy entry */ + miniEntries += 1U; + } + + if ((miniEntries + startEntries) > maxEntries) + { + return kStatus_OutOfRange; + } + + for (i = startEntries; i < (miniEntries + startEntries); i++) + { + if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + dmaBufferLen = (dataBytes == 0U ? sizeof(uint32_t) : + dataBytes); /* adma don't support 0 data length transfer descriptor */ + } + + /* Each descriptor for ADMA2 is 64-bit in length */ + adma2EntryAddress[i].address = (dataBytes == 0U) ? &s_usdhcBootDummy : data; + adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= + (dataBytes == 0U) ? 0U : (kUSDHC_Adma2DescriptorTypeTransfer | kUSDHC_Adma2DescriptorInterruptFlag); + data += (dmaBufferLen / sizeof(uint32_t)); + + if (dataBytes != 0U) + { + dataBytes -= dmaBufferLen; + } + } + + /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA + engine + will not stop at block gap */ + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + adma2EntryAddress[startEntries + 1U].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; + } + else + { + /* set the end bit */ + adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; + } + + return kStatus_Success; +} + +status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + const uint32_t *dataAddr, + bool enAutoCmd23) +{ + assert(dmaConfig); + assert(dataAddr); + +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable the external DMA if support */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + + if (dmaConfig->dmaMode == kUSDHC_DmaModeSimple) + { + /* check DMA data buffer address align or not */ + if (((uint32_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, + and block count should load to DS_ADDR*/ + if (enAutoCmd23) + { + base->ADMA_SYS_ADDR = (uint32_t)dataAddr; + } + else + { + base->DS_ADDR = (uint32_t)dataAddr; + } + } + else + { + /* When use ADMA, disable simple DMA */ + base->DS_ADDR = 0U; + base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); + } + + /* select DMA mode and config the burst length */ + base->PROT_CTRL &= ~(USDHC_PROT_CTRL_DMASEL_MASK | USDHC_PROT_CTRL_BURST_LEN_EN_MASK); + base->PROT_CTRL |= USDHC_PROT_CTRL_DMASEL(dmaConfig->dmaMode) | USDHC_PROT_CTRL_BURST_LEN_EN(dmaConfig->burstLen); + /* enable DMA */ + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + + return kStatus_Success; +} + +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags) +{ + assert(NULL != dmaConfig); + assert(NULL != dmaConfig->admaTable); + assert(NULL != dataConfig); + + status_t error = kStatus_Fail; + uint32_t bootDummyOffset = dataConfig->dataType == kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0U; + const uint32_t *data = + (const uint32_t *)((uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + + bootDummyOffset); + uint32_t blockSize = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset; + + switch (dmaConfig->dmaMode) + { +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + case kUSDHC_ExternalDMA: + /* enable the external DMA */ + base->VEND_SPEC |= USDHC_VEND_SPEC_EXT_DMA_EN_MASK; + break; +#endif + case kUSDHC_DmaModeSimple: + error = kStatus_Success; + break; + + case kUSDHC_DmaModeAdma1: + error = USDHC_SetADMA1Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); + break; + + case kUSDHC_DmaModeAdma2: + error = USDHC_SetADMA2Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); + break; + default: + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + + /* for internal dma, internal DMA configurations should not update the configurations when continous transfer the + * boot data, only the DMA descriptor need update */ + if ((dmaConfig->dmaMode != kUSDHC_ExternalDMA) && (error == kStatus_Success) && + (dataConfig->dataType != kUSDHC_TransferDataBootcontinous)) + { + error = USDHC_SetInternalDmaConfig(base, dmaConfig, data, dataConfig->enableAutoCommand23); + } + + return error; +} + +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) +{ + assert(transfer); + + status_t error = kStatus_Fail; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + bool enDMA = true; + bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); + + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) + { + error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, (data->dataType & kUSDHC_TransferDataBoot) ? + kUSDHC_AdmaDescriptorMultipleFlag : + kUSDHC_AdmaDescriptorSingleFlag); + } + + /* if the DMA desciptor configure fail or not needed , disable it */ + if (error != kStatus_Success) + { + enDMA = false; + /* disable DMA, using polling mode in this situation */ + USDHC_EnableInternalDMA(base, false); + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + else + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + /* config the data transfer parameter */ + error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); + if (kStatus_Success != error) + { + return error; + } + /* send command first */ + USDHC_SendCommand(base, command); + /* wait command done */ + error = USDHC_WaitCommandDone(base, command, (data == NULL) || (data->dataType == kUSDHC_TransferDataNormal)); + + /* wait transfer data finsih */ + if ((data != NULL) && (error == kStatus_Success)) + { + return USDHC_TransferDataBlocking(base, data, enDMA); + } + + return error; +} + +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + status_t error = kStatus_Fail; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); + + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + + /* Save command and data into handle before transferring. */ + handle->command = command; + handle->data = data; + handle->interruptFlags = 0U; + /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ + handle->transferredWords = 0U; + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) + { + error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, (data->dataType & kUSDHC_TransferDataBoot) ? + kUSDHC_AdmaDescriptorMultipleFlag : + kUSDHC_AdmaDescriptorSingleFlag); + } + + /* if the DMA desciptor configure fail or not needed , disable it */ + if (error != kStatus_Success) + { + /* disable DMA, using polling mode in this situation */ + USDHC_EnableInternalDMA(base, false); + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + else + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); + if (kStatus_Success != error) + { + return error; + } + + /* send command first */ + USDHC_SendCommand(base, command); + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + /* make sure std_tun_en bit is clear */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* disable auto tuning here */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + /* execute tuning for SDR104 mode */ + base->MIX_CTRL |= + USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK | USDHC_MIX_CTRL_FBCLK_SEL_MASK; + } + else + { /* abort the tuning */ + base->MIX_CTRL &= ~(USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK); + } +} + +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) +{ + uint32_t clkTuneCtrl = 0U; + + clkTuneCtrl = base->CLK_TUNE_CTRL_STATUS; + + clkTuneCtrl &= ~USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK; + + clkTuneCtrl |= USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(delay); + + /* load the delay setting */ + base->CLK_TUNE_CTRL_STATUS = clkTuneCtrl; + /* check delat setting error */ + if (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) +{ + uint32_t tuningCtrl = 0U; + + if (enable) + { + /* feedback clock */ + base->MIX_CTRL |= USDHC_MIX_CTRL_FBCLK_SEL_MASK; + /* config tuning start and step */ + tuningCtrl = base->TUNING_CTRL; + tuningCtrl &= ~(USDHC_TUNING_CTRL_TUNING_START_TAP_MASK | USDHC_TUNING_CTRL_TUNING_STEP_MASK); + tuningCtrl |= (USDHC_TUNING_CTRL_TUNING_START_TAP(tuningStartTap) | USDHC_TUNING_CTRL_TUNING_STEP(step) | + USDHC_TUNING_CTRL_STD_TUNING_EN_MASK); + base->TUNING_CTRL = tuningCtrl; + + /* excute tuning */ + base->AUTOCMD12_ERR_STATUS |= + (USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } + else + { + /* disable the standard tuning */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* clear excute tuning */ + base->AUTOCMD12_ERR_STATUS &= + ~(USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } +} + +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) +{ + uint32_t busWidth = 0U; + + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; + busWidth = (base->PROT_CTRL & USDHC_PROT_CTRL_DTW_MASK) >> USDHC_PROT_CTRL_DTW_SHIFT; + if (busWidth == kUSDHC_DataBusWidth1Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth4Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth8Bit) + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else + { + } +} +#endif /* FSL_FEATURE_USDHC_HAS_SDR50_MODE */ + +static void USDHC_TransferHandleCardDetect(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + if (interruptFlags & kUSDHC_CardInsertionFlag) + { + if (handle->callback.CardInserted) + { + handle->callback.CardInserted(base, handle->userData); + } + } + else + { + if (handle->callback.CardRemoved) + { + handle->callback.CardRemoved(base, handle->userData); + } + } +} + +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->command); + + if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data))) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + } + else + { + /* Receive response */ + if (kStatus_Success != USDHC_ReceiveCommandResponse(base, handle->command)) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + } + else if ((!(handle->data)) && (handle->callback.TransferComplete)) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + else + { + } + } +} + +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + + if ((!(handle->data->enableIgnoreError)) && ((interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)))) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_TransferDataFailed, handle->userData); + } + } + else + { + if (interruptFlags & kUSDHC_BufferReadReadyFlag) + { + /* std tuning process only need to wait BRR */ + if (handle->data->dataType == kUSDHC_TransferDataTuning) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + else + { + handle->transferredWords = USDHC_ReadDataPort(base, handle->data, handle->transferredWords); + } + } + else if (interruptFlags & kUSDHC_BufferWriteReadyFlag) + { + handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); + } + else + { + if ((interruptFlags & kUSDHC_DmaCompleteFlag) && + (handle->data->dataType == kUSDHC_TransferDataBootcontinous)) + { + *(handle->data->rxData) = s_usdhcBootDummy; + } + + if ((handle->callback.TransferComplete) && (interruptFlags & kUSDHC_DataCompleteFlag)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + } +} + +static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *handle) +{ + if (handle->callback.SdioInterrupt) + { + handle->callback.SdioInterrupt(base, handle->userData); + } +} + +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->callback.ReTuning); + /* retuning request */ + if ((interruptFlags & kUSDHC_TuningErrorFlag) == kUSDHC_TuningErrorFlag) + { + handle->callback.ReTuning(base, handle->userData); /* retuning fail */ + } +} + +static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle) +{ + if (handle->callback.BlockGap) + { + handle->callback.BlockGap(base, handle->userData); + } +} + +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.CardInserted = callback->CardInserted; + handle->callback.CardRemoved = callback->CardRemoved; + handle->callback.SdioInterrupt = callback->SdioInterrupt; + handle->callback.BlockGap = callback->BlockGap; + handle->callback.TransferComplete = callback->TransferComplete; + handle->callback.ReTuning = callback->ReTuning; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_usdhcHandle[USDHC_GetInstance(base)] = handle; + + /* Enable interrupt in NVIC. */ + USDHC_SetTransferInterrupt(base, true); + /* disable the tuning pass interrupt */ + USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag); + /* save IRQ handler */ + s_usdhcIsr = USDHC_TransferHandleIRQ; + + EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); +} + +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags; + + interruptFlags = USDHC_GetInterruptStatusFlags(base); + handle->interruptFlags = interruptFlags; + + if (interruptFlags & kUSDHC_CardDetectFlag) + { + USDHC_TransferHandleCardDetect(base, handle, (interruptFlags & kUSDHC_CardDetectFlag)); + } + if (interruptFlags & kUSDHC_CommandFlag) + { + USDHC_TransferHandleCommand(base, handle, (interruptFlags & kUSDHC_CommandFlag)); + } + if (interruptFlags & kUSDHC_DataFlag) + { + USDHC_TransferHandleData(base, handle, (interruptFlags & kUSDHC_DataFlag)); + } + if (interruptFlags & kUSDHC_CardInterruptFlag) + { + USDHC_TransferHandleSdioInterrupt(base, handle); + } + if (interruptFlags & kUSDHC_BlockGapEventFlag) + { + USDHC_TransferHandleBlockGap(base, handle); + } + if (interruptFlags & kUSDHC_SDR104TuningFlag) + { + USDHC_TransferHandleReTuning(base, handle, (interruptFlags & kUSDHC_SDR104TuningFlag)); + } + USDHC_ClearInterruptStatusFlags(base, interruptFlags); +} + +#ifdef USDHC0 +void USDHC0_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[0U], s_usdhcHandle[0U]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#ifdef USDHC1 +void USDHC1_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[1U], s_usdhcHandle[1U]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#ifdef USDHC2 +void USDHC2_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[2U], s_usdhcHandle[2U]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_usdhc.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_usdhc.h new file mode 100644 index 0000000000..4139dfd8bd --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_usdhc.h @@ -0,0 +1,1505 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_USDHC_H_ +#define _FSL_USDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usdhc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.2.3. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 3U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) + +/*! @brief USDHC status */ +enum _usdhc_status +{ + kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ + kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ + kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ + kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ + kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ + kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ + kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */ +}; + +/*! @brief Host controller capabilities flag mask */ +enum _usdhc_capability_flag +{ + kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ + kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ + kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ + kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ + kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ + kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ + kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ + /* sd version 3.0 new feature */ + kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) + kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ +#else + kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ +#endif +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ +#else + kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ +#endif +}; + +/*! @brief Wakeup event mask */ +enum _usdhc_wakeup_event +{ + kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ + kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ + + kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | + kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _usdhc_reset +{ + kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ + kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ + kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ +#else + kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ +#endif + + kUSDHC_ResetsAll = + (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _usdhc_transfer_flag +{ + kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ + + kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ + kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ + kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ + + kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ + kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ + kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ + kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ + kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ + + kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ + kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ + kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ + kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ + kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _usdhc_present_status_flag +{ + kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ + kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ + kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ + kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ + kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ + kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ + kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ + kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ + kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ +#else + kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ + kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ +#endif + + kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ + kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ + + kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */ + kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */ + kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */ + kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */ + kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */ + kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */ + kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */ + kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _usdhc_interrupt_status_flag +{ + kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ + kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ + kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ + kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ + kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ + kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ + kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ + kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ + kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ +#else + kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ +#endif + + kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ + kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ + kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ + kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ + kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ + kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ + kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ + kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ + + kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | + kUSDHC_CommandIndexErrorFlag), /*!< Command error */ + kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | + kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ + kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | + kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ + kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), + + kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | + kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _usdhc_auto_command12_error_status_flag +{ + kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ + kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ + kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ + kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ + kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ + kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief standard tuning flag */ +enum _usdhc_standard_tuning +{ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ExecuteTuning = 0U, /*!< not support */ + kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ +#else + kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ + kUSDHC_TuningSampleClockSel = + USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this bit is used + select sampleing clock */ +#endif +}; + +/*! @brief ADMA error status flag mask */ +enum _usdhc_adma_error_status_flag +{ + kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ + kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +enum _usdhc_adma_error_state +{ + kUSDHC_AdmaErrorStateStopDma = + 0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateFetchDescriptor = + 0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occured */ + kUSDHC_AdmaErrorStateTransferData = + 0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateInvalidLength = 0x04U, /*!< Invalid length in ADMA descriptor */ + kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */ + + kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor | + kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */ +}; + +/*! @brief Force event mask */ +enum _usdhc_force_event +{ + kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ + kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ + kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ + kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ + kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ + kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ + kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ + kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ + kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ + kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ + kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ + kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ForceEventTuningError = 0U, /*!< not support */ +#else + kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ +#endif + kUSDHC_ForceEventsAll = + (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout | + kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError | + kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued | + kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError | + kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError | + kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt | + kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _usdhc_data_bus_width +{ + kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} usdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _usdhc_endian_mode +{ + kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} usdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _usdhc_dma_mode +{ + kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ + kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ + kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ +} usdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _usdhc_sdio_control_flag +{ + kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ + kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ + kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ + kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ + kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _usdhc_boot_mode +{ + kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} usdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _usdhc_card_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ + kCARD_CommandTypeEmpty = 4U, /*!< Empty command */ +} usdhc_card_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _usdhc_card_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} usdhc_card_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define USDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define USDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _usdhc_adma1_descriptor_flag +{ + kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma1DescriptorTypeTransfer = + (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | + kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kUSDHC_Adma1DescriptorTypeSetLength = + (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _usdhc_adma2_descriptor_flag +{ + kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma2DescriptorTypeReserved = + (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kUSDHC_Adma2DescriptorTypeTransfer = + (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | + kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief ADMA descriptor configuration flag */ +enum _usdhc_adma_flag +{ + kUSDHC_AdmaDescriptorSingleFlag = + 0U, /*!< try to finish the transfer in a single ADMA descriptor, if transfer size is bigger than one + ADMA descriptor's ability, new another descriptor for data transfer */ + kUSDHC_AdmaDescriptorMultipleFlag = 1U, /*!< create multiple ADMA descriptor within the ADMA table, this is used for + mmc boot mode specifically, which need + to modify the ADMA descriptor on the fly, so the flag should be used + combine with stop at block gap feature */ +}; + +/*! @brief dma transfer burst len config. */ +typedef enum _usdhc_burst_len +{ + kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ + kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ + kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ +} usdhc_burst_len_t; + +/*! @brief transfer data type definition. */ +enum _usdhc_transfer_data_type +{ + kUSDHC_TransferDataNormal = 0U, /*!< transfer normal read/write data */ + kUSDHC_TransferDataTuning = 1U, /*!< transfer tuning data */ + kUSDHC_TransferDataBoot = 2U, /*!< transfer boot data */ + kUSDHC_TransferDataBootcontinous = 3U, /*!< transfer boot data continous */ +}; + +/*! @brief Defines the adma1 descriptor structure. */ +typedef uint32_t usdhc_adma1_descriptor_t; + +/*! @brief Defines the ADMA2 descriptor structure. */ +typedef struct _usdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} usdhc_adma2_descriptor_t; + +/*! + * @brief USDHC capability information. + * + * Defines a structure to save the capability information of USDHC. + */ +typedef struct _usdhc_capability +{ + uint32_t sdVersion; /*!< support SD card/sdio version */ + uint32_t mmcVersion; /*!< support emmc card version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ +} usdhc_capability_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _usdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ + usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ + size_t blockSize; /*!< Block size */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} usdhc_boot_config_t; + +/*! @brief Data structure to initialize the USDHC */ +typedef struct _usdhc_config +{ + uint32_t dataTimeout; /*!< Data timeout value */ + usdhc_endian_mode_t endianMode; /*!< Endian mode */ + uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ + uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ + uint8_t readBurstLen; /*!< Read burst len */ + uint8_t writeBurstLen; /*!< Write burst len */ +} usdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _usdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableAutoCommand23; /*!< Enable auto CMD23 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + uint8_t dataType; /*!< this is used to distinguish the normal/tuning/boot data */ + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} usdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _usdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + usdhc_card_command_type_t type; /*!< Command type */ + usdhc_card_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ + uint32_t flags; /*!< Cmd flags */ +} usdhc_command_t; + +/*! @brief ADMA configuration */ +typedef struct _usdhc_adma_config +{ + usdhc_dma_mode_t dmaMode; /*!< DMA mode */ + + usdhc_burst_len_t burstLen; /*!< burst len config */ + + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} usdhc_adma_config_t; + +/*! @brief Transfer state */ +typedef struct _usdhc_transfer +{ + usdhc_data_t *data; /*!< Data to transfer */ + usdhc_command_t *command; /*!< Command to send */ +} usdhc_transfer_t; + +/*! @brief USDHC handle typedef */ +typedef struct _usdhc_handle usdhc_handle_t; + +/*! @brief USDHC callback functions. */ +typedef struct _usdhc_transfer_callback +{ + void (*CardInserted)(USDHC_Type *base, + void *userData); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(USDHC_Type *base, void *userData); /*!< Card removed occurs */ + void (*SdioInterrupt)(USDHC_Type *base, void *userData); /*!< SDIO card interrupt occurs */ + void (*BlockGap)(USDHC_Type *base, void *userData); /*!< stopped at block gap event */ + void (*TransferComplete)(USDHC_Type *base, + usdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ + void (*ReTuning)(USDHC_Type *base, void *userData); /*!< handle the re-tuning */ +} usdhc_transfer_callback_t; + +/*! + * @brief USDHC handle + * + * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when + * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in + * usdhc_interrupt_flag_t. + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _usdhc_handle +{ + /* Transfer parameter */ + usdhc_data_t *volatile data; /*!< Data to transfer */ + usdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + usdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief USDHC transfer function. */ +typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); + +/*! @brief USDHC host descriptor */ +typedef struct _usdhc_host +{ + USDHC_Type *base; /*!< USDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ + usdhc_config_t config; /*!< USDHC configuration */ + usdhc_capability_t capability; /*!< USDHC capability information */ + usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ +} usdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + @code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config USDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); + +/*! + * @brief Deinitializes the USDHC. + * + * @param base USDHC peripheral base address. + */ +void USDHC_Deinit(USDHC_Type *base); + +/*! + * @brief Resets the USDHC. + * + * @param base USDHC peripheral base address. + * @param mask The reset type mask(_usdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Sets the DMA descriptor table configuration. + * A high level DMA descriptor configuration function. + * @param base USDHC peripheral base address. + * @param adma configuration + * @param data Data descriptor + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags); + +/*! + * @brief Internal DMA configuration. + * This function is used to config the USDHC DMA related registers. + * @param base USDHC peripheral base address. + * @param adma configuration + * @param dataAddr tranfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. + * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to + * false. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + const uint32_t *dataAddr, + bool enAutoCmd23); + +/*! + * @brief Sets the ADMA2 descriptor table configuration. + * + * @param admaTable Adma table address. + * @param admaTableWords Adma table length. + * @param dataBufferAddr Data buffer address. + * @param dataBytes Data Data length. + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA2Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); + +/*! + * @brief Sets the ADMA1 descriptor table configuration. + * + * @param admaTable Adma table address. + * @param admaTableWords Adma table length. + * @param dataBufferAddr Data buffer address. + * @param dataBytes Data length. + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA1Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); + +/*! + * @brief enable internal DMA. + * + * @param base USDHC peripheral base address. + * @param enable enable or disable flag + */ +static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN |= mask; +} + +/*! + * @brief Disables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN &= ~mask; +} + +/*! + * @brief Enables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN |= mask; +} + +/*! + * @brief Disables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the current interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) +{ + return base->INT_STATUS; +} + +/*! + * @brief Clears a specified interrupt status. + * write 1 clears + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! + * @brief Gets the status of auto command 12 error. + * + * @param base USDHC peripheral base address. + * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). + */ +static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) +{ + return base->AUTOCMD12_ERR_STATUS; +} + +/*! + * @brief Gets the status of the ADMA error. + * + * @param base USDHC peripheral base address. + * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). + */ +static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) +{ + return base->ADMA_ERR_STATUS & 0xFU; +} + +/*! + * @brief Gets a present status. + * + * This function gets the present USDHC's status except for an interrupt status and an error status. + * + * @param base USDHC peripheral base address. + * @return Present USDHC's status flags mask(_usdhc_present_status_flag). + */ +static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) +{ + return base->PRES_STATE; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the capability information. + * + * @param base USDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); + +/*! + * @brief force the card clock on. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag. + */ +static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } +} + +/*! + * @brief Sets the SD bus clock frequency. + * + * @param base USDHC peripheral base address. + * @param srcClock_Hz USDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * @param base USDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); + +/*! + * @brief trigger a hardware reset. + * + * @param base USDHC peripheral base address. + * @param 1 or 0 level + */ +static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) +{ + if (high) + { + base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; + } + else + { + base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; + } +} + +/*! + * @brief Sets the data transfer width. + * + * @param base USDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) +{ + base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); +} + +/*! + * @brief Fills the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) +{ + base->DATA_BUFF_ACC_PORT = data; +} + +/*! + * @brief Retrieves the data from the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t USDHC_ReadData(USDHC_Type *base) +{ + return base->DATA_BUFF_ACC_PORT; +} + +/*! +* @brief send command function +* +* @param base USDHC peripheral base address. +* @param command configuration +*/ +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Enables or disables a wakeup event in low-power mode. + * + * @param base USDHC peripheral base address. + * @param mask Wakeup events mask(_usdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_DetectCardInsert(USDHC_Type *base) +{ + return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; +} + +/*! + * @brief Enables or disables the SDIO card control. + * + * @param base USDHC peripheral base address. + * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_SetContinueRequest(USDHC_Type *base) +{ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; +} + +/*! + * @brief Request stop at block gap function. + * + * @param base USDHC peripheral base address. + * @param enable true to stop at block gap, false to normal transfer + */ +static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_SABGREQ_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; + } +} + +/*! + * @brief Configures the MMC boot feature. + * + * Example: + @code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); + +/*! + * @brief Enables or disables the mmc boot mode. + * + * @param base USDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MMC_BOOT |= USDHC_MMC_BOOT_BOOT_EN_MASK; + } + else + { + base->MMC_BOOT &= ~USDHC_MMC_BOOT_BOOT_EN_MASK; + } +} + +/*! + * @brief Forces generating events according to the given mask. + * + * @param base USDHC peripheral base address. + * @param mask The force events mask(_usdhc_force_event). + */ +static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) +{ + base->FORCE_EVENT = mask; +} + +/*! + * @brief select the usdhc output voltage + * + * @param base USDHC peripheral base address. + * @param true 1.8V, false 3.0V + */ +static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) +{ + if (en18v) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; + } +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) +/*! +* @brief check the SDR50 mode request tuning bit +* When this bit set, user should call USDHC_StandardTuning function +* @param base USDHC peripheral base address. +*/ +static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) +{ + return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; +} + +/*! + * @brief check the request re-tuning bit + * When this bit is set, user should do manual tuning or standard tuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestReTuning(USDHC_Type *base) +{ + return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; +} + +/*! + * @brief the SDR104 mode auto tuning enable and disable + * This function should call after tuning function execute pass, auto tuning will handle + * by hardware + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } +} + +/*! + * @brief the config the re-tuning timer for mode 1 and mode 3 + * This timer is used for standard tuning auto re-tuning, + * @param base USDHC peripheral base address. + * @param timer counter value + */ +static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) +{ + base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; + base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); +} + +/*! + * @brief the auto tuning enbale for CMD/DATA line + * + * @param base USDHC peripheral base address. + */ +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); + +/*! + * @brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * @param base USDHC peripheral base address. + * @param tuning enable flag + */ +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); + +/*! + * @brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * @param base USDHC peripheral base address. + * @param delay setting configuration + * @retval kStatus_Fail config the delay setting fail + * @retval kStatus_Success config the delay setting success + */ +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); + +/*! + * @brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * @param base USDHC peripheral base address. + * @param tuning start tap + * @param tuning step + * @param enable/disable flag + */ +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); + +/*! + * @brief Get execute std tuning status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); +} + +/*! + * @brief check std tuning result + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); +} + +/*! + * @brief check tuning error + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) +{ + return (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); +} + +#endif +/*! + * @brief the enable/disable DDR mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + * @param nibble position + */ +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos); + +/*! + * @brief the enable/disable HS400 mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; + } +} + +/*! + * @brief reset the strobe DLL + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) +{ + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; +} + +/*! + * @brief enable/disable the strobe DLL + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } + else + { + base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } +} + +/*! + * @brief config the strobe DLL delay target and update interval + * + * @param base USDHC peripheral base address. + * @param delay target + * @param update interval + */ +static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) +{ + base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); + + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); +} + +/*! + * @brief get the strobe DLL status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) +{ + return base->STROBE_DLL_STATUS; +} + +#endif + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_USDHC_SendCommandFailed Send command failed. + * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); + +/*! + * @brief Creates the USDHC handle. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param adma configuration. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_BusyTransferring Busy transferring. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_USDHC_H_*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_wdog.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_wdog.c new file mode 100644 index 0000000000..b1cc4eb1fb --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_wdog.c @@ -0,0 +1,141 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wdog.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wdog01" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ +static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of WDOG clock name. */ +static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WDOG_GetInstance(WDOG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++) + { + if (s_wdogBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_wdogBases)); + + return instance; +} + +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + config->enableWdog = true; + config->workMode.enableWait = false; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableInterrupt = false; + config->softwareResetExtension = false; + config->enablePowerDown = false; + config->softwareAssertion= true; + config->softwareResetSignal = true; + config->timeoutValue = 0xffu; + config->interruptTimeValue = 0x04u; +} + +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint16_t value = 0u; + + value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | + WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | + WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | + WDOG_WCR_WDA(config->softwareAssertion) | WDOG_WCR_SRS(config->softwareResetSignal); + + /* Set configruation */ + CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); + base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); + base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); + base->WCR = value; +} + +void WDOG_Deinit(WDOG_Type *base) +{ + if (base->WCR & WDOG_WCR_WDBG_MASK) + { + WDOG_Disable(base); + } +} + +uint16_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint16_t status_flag = 0U; + + status_flag |= (base->WCR & WDOG_WCR_WDE_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK); + status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK); + + return status_flag; +} + +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) +{ + if (mask & kWDOG_InterruptFlag) + { + base->WICR |= WDOG_WICR_WTIS_MASK; + } +} + +void WDOG_Refresh(WDOG_Type *base) +{ + base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; + base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_wdog.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_wdog.h new file mode 100644 index 0000000000..508714bbe1 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_wdog.h @@ -0,0 +1,303 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_REFRESH_KEY (0xAAAA5555U) +/*@}*/ + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ + bool enableWait; /*!< continue or suspend WDOG in wait mode */ + bool enableStop; /*!< continue or suspend WDOG in stop mode */ + bool enableDebug; /*!< continue or suspend WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + uint16_t timeoutValue; /*!< Timeout value */ + uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ + bool softwareResetExtension; /*!< software reset extension */ + bool enablePowerDown; /*!< power down enable bit */ + bool softwareAssertion; /*!< software assertion bit*/ + bool softwareResetSignal; /*!< software reset signalbit*/ +} wdog_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable +{ + kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags +{ + kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ + kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ + kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ + kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization. + * @{ + */ + +/*! + * @brief Initializes the WDOG configuration sturcture. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * @endcode + * + * @param config Pointer to the WDOG configuration structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Enables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to enable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write, + * once the bit is set. only debug mode exception. + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->WCR |= WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to disable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. + * only debug mode exception + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Enables the WDOG interrupt. + * + *This bit is a write once only bit. Once the software does a write access to this bit, it will get + *locked and cannot be reprogrammed until the next system reset assertion + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask) +{ + base->WICR |= mask; +} + +/*! + * @brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * @code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * @code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask); + +/*! + * @brief Sets the WDOG timeout value. + * + * This function sets the timeout value. + * This function writes a value into WCR registers. + * The time-out value can be written at any point of time but it is loaded to the counter at the time + * when WDOG is enabled or after the service routine has been performed. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WCR = (base->WCR & ~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount); +} + +/*! + * @brief Sets the WDOG interrupt count timeout value. + * + * This function sets the interrupt count timeout value. + * This function writes a value into WIC registers which are wirte-once. + * This field is write once only. Once the software does a write access to this field, it will get locked + * and cannot be reprogrammed until the next system reset assertion. + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WICR = (base->WICR & ~WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount); +} + +/*! + * @brief Disable the WDOG power down enable bit. + * + * This function disable the WDOG power down enable(PDE). + * This function writes a value into WMCR registers which are wirte-once. + * This field is write once only. Once software sets this bit it cannot be reset until the next system reset. + * @param base WDOG peripheral base address + */ +static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) +{ + base->WMCR &= ~WDOG_WMCR_PDE_MASK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbara.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbara.c new file mode 100644 index 0000000000..3a8d903565 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbara.c @@ -0,0 +1,222 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xbara.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xbara" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the XBARA instance from peripheral base address. + * + * @param base XBARA peripheral base address. + * @return XBARA instance. + */ +static uint32_t XBARA_GetInstance(XBARA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of XBARA peripheral base address. */ +static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of XBARA clock name. */ +static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t XBARA_GetInstance(XBARA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++) + { + if (s_xbaraBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_xbaraBases)); + + return instance; +} + +void XBARA_Init(XBARA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable XBARA module clock. */ + CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void XBARA_Deinit(XBARA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable XBARA module clock. */ + CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) +{ + XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); +} + +uint32_t XBARA_GetStatusFlags(XBARA_Type *base) +{ + uint32_t status_flag; + + status_flag = ((base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)) | + ((base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U)); + + return status_flag; +} + +void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask) +{ + uint16_t regVal; + + /* Assign regVal to CTRL0 register's value */ + regVal = (base->CTRL0); + /* Perform this command to avoid writing 1 into interrupt flag bits */ + regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); + /* Write 1 to interrupt flag bits corresponding to mask */ + regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); + /* Write regVal value into CTRL0 register */ + base->CTRL0 = regVal; + + /* Assign regVal to CTRL1 register's value */ + regVal = (base->CTRL1); + /* Perform this command to avoid writing 1 into interrupt flag bits */ + regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)); + /* Write 1 to interrupt flag bits corresponding to mask */ + regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)); + /* Write regVal value into CTRL1 register */ + base->CTRL1 = regVal; +} + +void XBARA_SetOutputSignalConfig(XBARA_Type *base, + xbar_output_signal_t output, + const xbara_control_config_t *controlConfig) +{ + uint16_t regVal; + /* Set active edge for edge detection, set interrupt or DMA function. */ + switch ((uint16_t)output) + { +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 + case kXBARA1_OutputDmaChMuxReq30: +#else + case kXBARA_OutputDmamux18: +#endif + /* Assign regVal to CTRL0 register's value */ + regVal = (base->CTRL0); + /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN0, IEN0 */ + regVal &= (uint16_t)( + ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK)); + /* Configure edge and request type */ + regVal |= (uint16_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) | + ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT)); + /* Write regVal value into CTRL0 register */ + base->CTRL0 = regVal; + break; +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 + case kXBARA1_OutputDmaChMuxReq31: +#else + case kXBARA_OutputDmamux19: +#endif + /* Assign regVal to CTRL0 register's value */ + regVal = (base->CTRL0); + /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN1, IEN1 */ + regVal &= (uint16_t)( + ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN1_MASK | XBARA_CTRL0_IEN1_MASK)); + /* Configure edge and request type */ + regVal |= (uint16_t)(XBARA_CTRL0_EDGE1(controlConfig->activeEdge) | + ((controlConfig->requestType) << XBARA_CTRL0_DEN1_SHIFT)); + /* Write regVal value into CTRL0 register */ + base->CTRL0 = regVal; + break; +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 + case kXBARA1_OutputDmaChMuxReq94: +#else + case kXBARA_OutputDmamux20: +#endif + /* Assign regVal to CTRL1 register's value */ + regVal = (base->CTRL1); + /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN2, IEN2 */ + regVal &= (uint16_t)( + ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN2_MASK | XBARA_CTRL1_IEN2_MASK)); + /* Configure edge and request type */ + regVal |= (uint16_t)(XBARA_CTRL1_EDGE2(controlConfig->activeEdge) | + ((controlConfig->requestType) << XBARA_CTRL1_DEN2_SHIFT)); + /* Write regVal value into CTRL1 register */ + base->CTRL1 = regVal; + break; +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 + case kXBARA1_OutputDmaChMuxReq95: +#else + case kXBARA_OutputDmamux21: +#endif + /* Assign regVal to CTRL1 register's value */ + regVal = (base->CTRL1); + /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN3, IEN3 */ + regVal &= (uint16_t)( + ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN3_MASK | XBARA_CTRL1_IEN3_MASK)); + /* Configure edge and request type */ + regVal |= (uint16_t)(XBARA_CTRL1_EDGE3(controlConfig->activeEdge) | + ((controlConfig->requestType) << XBARA_CTRL1_DEN3_SHIFT)); + /* Write regVal value into CTRL1 register */ + base->CTRL1 = regVal; + break; + default: + break; + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbara.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbara.h new file mode 100644 index 0000000000..98410a198b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbara.h @@ -0,0 +1,211 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_XBARA_H_ +#define _FSL_XBARA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup xbara + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FSL_XBARA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ + +/* Macros for entire XBARA_SELx register. */ +#define XBARA_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U)) +/* Set the XBARA_SELx_SELx field to a new value. */ +#define XBARA_WR_SELx_SELx(base, input, output) \ + (XBARA_SELx((base), (output)) = \ + ((XBARA_SELx((base), (output)) & ~(0xFFU << (XBARA_SEL0_SEL1_SHIFT * ((output) % 2U)))) | \ + ((input) << (XBARA_SEL0_SEL1_SHIFT * ((output) % 2U))))) + +/*! + * @brief XBARA active edge for detection + */ +typedef enum _xbara_active_edge +{ + kXBARA_EdgeNone = 0U, /*!< Edge detection status bit never asserts. */ + kXBARA_EdgeRising = 1U, /*!< Edge detection status bit asserts on rising edges. */ + kXBARA_EdgeFalling = 2U, /*!< Edge detection status bit asserts on falling edges. */ + kXBARA_EdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */ +} xbara_active_edge_t; + +/*! + * @brief Defines the XBARA DMA and interrupt configurations. + */ +typedef enum _xbar_request +{ + kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */ + kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */ + kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */ +} xbara_request_t; + +/*! + * @brief XBARA status flags. + * + * This provides constants for the XBARA status flags for use in the XBARA functions. + */ +typedef enum _xbara_status_flag_t +{ + kXBARA_EdgeDetectionOut0 = + (XBARA_CTRL0_STS0_MASK), /*!< XBAR_OUT0 active edge interrupt flag, sets when active edge detected. */ + kXBARA_EdgeDetectionOut1 = + (XBARA_CTRL0_STS1_MASK), /*!< XBAR_OUT1 active edge interrupt flag, sets when active edge detected. */ + kXBARA_EdgeDetectionOut2 = + (XBARA_CTRL1_STS2_MASK << 16U), /*!< XBAR_OUT2 active edge interrupt flag, sets when active edge detected. */ + kXBARA_EdgeDetectionOut3 = + (XBARA_CTRL1_STS3_MASK << 16U), /*!< XBAR_OUT3 active edge interrupt flag, sets when active edge detected. */ +} xbara_status_flag_t; + +/*! + * @brief Defines the configuration structure of the XBARA control register. + * + * This structure keeps the configuration of XBARA control register for one output. + * Control registers are available only for a few outputs. Not every XBARA module has + * control registers. + */ +typedef struct XBARAControlConfig +{ + xbara_active_edge_t activeEdge; /*!< Active edge to be detected. */ + xbara_request_t requestType; /*!< Selects DMA/Interrupt request. */ +} xbara_control_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name XBARA functional Operation. + * @{ + */ + +/*! + * @brief Initializes the XBARA module. + * + * This function un-gates the XBARA clock. + * + * @param base XBARA peripheral address. + */ +void XBARA_Init(XBARA_Type *base); + +/*! + * @brief Shuts down the XBARA module. + * + * This function disables XBARA clock. + * + * @param base XBARA peripheral address. + */ +void XBARA_Deinit(XBARA_Type *base); + +/*! + * @brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal. + * + * This function connects the XBARA input to the selected XBARA output. + * If more than one XBARA module is available, only the inputs and outputs from the same module + * can be connected. + * + * Example: + @code + XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18); + @endcode + * + * @param base XBARA peripheral address. + * @param input XBARA input signal. + * @param output XBARA output signal. + */ +void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output); + +/*! + * @brief Gets the active edge detection status. + * + * This function gets the active edge detect status of all XBARA_OUTs. If the + * active edge occurs, the return value is asserted. When the interrupt or the DMA + * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt + * or DMA request is asserted and 0 when the interrupt or DMA request has been + * cleared. + * + * @param base XBARA peripheral address. + * @return the mask of these status flag bits. + */ +uint32_t XBARA_GetStatusFlags(XBARA_Type *base); + +/*! + * @brief Clears the edge detection status flags of relative mask. + * + * @param base XBARA peripheral address. + * @param mask the status flags to clear. + */ +void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask); + +/*! + * @brief Configures the XBARA control register. + * + * This function configures an XBARA control register. The active edge detection + * and the DMA/IRQ function on the corresponding XBARA output can be set. + * + * Example: + @code + xbara_control_config_t userConfig; + userConfig.activeEdge = kXBARA_EdgeRising; + userConfig.requestType = kXBARA_RequestInterruptEnalbe; + XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig); + @endcode + * + * @param base XBARA peripheral address. + * @param output XBARA output number. + * @param controlConfig Pointer to structure that keeps configuration of control register. + */ +void XBARA_SetOutputSignalConfig(XBARA_Type *base, + xbar_output_signal_t output, + const xbara_control_config_t *controlConfig); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +/*!* @} */ + +#endif /* _FSL_XBARA_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbarb.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbarb.c new file mode 100644 index 0000000000..627b0ab91f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbarb.c @@ -0,0 +1,112 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xbarb.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xbarb" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the XBARB instance from peripheral base address. + * + * @param base XBARB peripheral base address. + * @return XBARB instance. + */ +static uint32_t XBARB_GetInstance(XBARB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of XBARB peripheral base address. */ +static XBARB_Type *const s_xbarbBases[] = XBARB_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of XBARB clock name. */ +static const clock_ip_name_t s_xbarbClock[] = XBARB_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t XBARB_GetInstance(XBARB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_xbarbBases); instance++) + { + if (s_xbarbBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_xbarbBases)); + + return instance; +} + +void XBARB_Init(XBARB_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable XBARB module clock. */ + CLOCK_EnableClock(s_xbarbClock[XBARB_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void XBARB_Deinit(XBARB_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable XBARB module clock. */ + CLOCK_DisableClock(s_xbarbClock[XBARB_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) +{ + XBARB_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbarb.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbarb.h new file mode 100644 index 0000000000..38e687fb06 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_xbarb.h @@ -0,0 +1,111 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_XBARB_H_ +#define _FSL_XBARB_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup xbarb + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FSL_XBARB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ + +/* Macros for entire XBARB_SELx register. */ +#define XBARB_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U)) +/* Set the SELx field to a new value. */ +#define XBARB_WR_SELx_SELx(base, input, output) \ + (XBARB_SELx((base), (output)) = \ + ((XBARB_SELx((base), (output)) & ~(0xFFU << (XBARB_SEL0_SEL1_SHIFT * ((output) % 2U)))) | \ + ((input) << (XBARB_SEL0_SEL1_SHIFT * ((output) % 2U))))) + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name XBARB functional Operation. + * @{ + */ + +/*! + * @brief Initializes the XBARB module. + * + * This function un-gates the XBARB clock. + * + * @param base XBARB peripheral address. + */ +void XBARB_Init(XBARB_Type *base); + +/*! + * @brief Shuts down the XBARB module. + * + * This function disables XBARB clock. + * + * @param base XBARB peripheral address. + */ +void XBARB_Deinit(XBARB_Type *base); + +/*! + * @brief Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal. + * + * This function configures which XBARB input is connected to the selected XBARB output. + * If more than one XBARB module is available, only the inputs and outputs from the same module + * can be connected. + * + * @param base XBARB peripheral address. + * @param input XBARB input signal. + * @param output XBARB output signal. + */ +void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +/*!* @} */ + +#endif /* _FSL_XBARB_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/fsl_device_registers.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/fsl_device_registers.h new file mode 100644 index 0000000000..f546a9df0e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/fsl_device_registers.h @@ -0,0 +1,64 @@ +/* + * The Clear BSD License + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ + defined(CPU_MIMXRT1052DVL6B)) + +#define MIMXRT1052_SERIES + +/* CMSIS-style register definitions */ +#include "MIMXRT1052.h" +/* CPU specific feature definitions */ +#include "MIMXRT1052_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld new file mode 100644 index 0000000000..ae0c12c31a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld @@ -0,0 +1,271 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor_sdram.ld b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor_sdram.ld new file mode 100644 index 0000000000..2d6bfec347 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor_sdram.ld @@ -0,0 +1,273 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld new file mode 100644 index 0000000000..2cdf7cf6db --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld @@ -0,0 +1,250 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld new file mode 100644 index 0000000000..b873025a4f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld @@ -0,0 +1,252 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram_txt.ld b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram_txt.ld new file mode 100644 index 0000000000..ad35525e31 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram_txt.ld @@ -0,0 +1,252 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x80000400, LENGTH = 0x001FFC00 + m_data (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x80200000, LENGTH = 0x01C00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/startup_MIMXRT1052.S b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/startup_MIMXRT1052.S new file mode 100644 index 0000000000..a35793b80b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/gcc/startup_MIMXRT1052.S @@ -0,0 +1,1093 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MIMXRT1052.s */ +/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ +/* MIMXRT1052 */ +/* @version: 0.1 */ +/* @date: 2017-1-10 */ +/* @build: b180509 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* The Clear BSD License */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2018 NXP */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted (subject to the limitations in the */ +/* disclaimer below) provided that the following conditions are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE */ +/* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT */ +/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED */ +/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ +/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ +/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ +/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */ +/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */ +/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN */ +/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/ + .long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/ + .long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/ + .long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/ + .long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/ + .long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/ + .long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/ + .long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/ + .long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/ + .long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/ + .long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/ + .long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/ + .long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/ + .long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/ + .long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/ + .long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/ + .long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/ + .long CTI0_ERROR_IRQHandler /* CTI0_Error*/ + .long CTI1_ERROR_IRQHandler /* CTI1_Error*/ + .long CORE_IRQHandler /* CorePlatform exception IRQ*/ + .long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/ + .long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/ + .long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/ + .long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/ + .long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/ + .long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/ + .long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/ + .long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/ + .long LPI2C1_IRQHandler /* LPI2C1 interrupt*/ + .long LPI2C2_IRQHandler /* LPI2C2 interrupt*/ + .long LPI2C3_IRQHandler /* LPI2C3 interrupt*/ + .long LPI2C4_IRQHandler /* LPI2C4 interrupt*/ + .long LPSPI1_IRQHandler /* LPSPI1 single interrupt vector for all sources*/ + .long LPSPI2_IRQHandler /* LPSPI2 single interrupt vector for all sources*/ + .long LPSPI3_IRQHandler /* LPSPI3 single interrupt vector for all sources*/ + .long LPSPI4_IRQHandler /* LPSPI4 single interrupt vector for all sources*/ + .long CAN1_IRQHandler /* CAN1 interrupt*/ + .long CAN2_IRQHandler /* CAN2 interrupt*/ + .long FLEXRAM_IRQHandler /* FlexRAM address out of range Or access hit IRQ*/ + .long KPP_IRQHandler /* Keypad nterrupt*/ + .long TSC_DIG_IRQHandler /* TSC interrupt*/ + .long GPR_IRQ_IRQHandler /* GPR interrupt*/ + .long LCDIF_IRQHandler /* LCDIF interrupt*/ + .long CSI_IRQHandler /* CSI interrupt*/ + .long PXP_IRQHandler /* PXP interrupt*/ + .long WDOG2_IRQHandler /* WDOG2 interrupt*/ + .long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/ + .long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/ + .long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/ + .long CSU_IRQHandler /* CSU interrupt*/ + .long DCP_IRQHandler /* DCP_IRQ interrupt*/ + .long DCP_VMI_IRQHandler /* DCP_VMI_IRQ interrupt*/ + .long Reserved68_IRQHandler /* Reserved interrupt*/ + .long TRNG_IRQHandler /* TRNG interrupt*/ + .long SJC_IRQHandler /* SJC interrupt*/ + .long BEE_IRQHandler /* BEE interrupt*/ + .long SAI1_IRQHandler /* SAI1 interrupt*/ + .long SAI2_IRQHandler /* SAI1 interrupt*/ + .long SAI3_RX_IRQHandler /* SAI3 interrupt*/ + .long SAI3_TX_IRQHandler /* SAI3 interrupt*/ + .long SPDIF_IRQHandler /* SPDIF interrupt*/ + .long ANATOP_EVENT0_IRQHandler /* ANATOP interrupt*/ + .long ANATOP_EVENT1_IRQHandler /* ANATOP interrupt*/ + .long ANATOP_TAMP_LOW_HIGH_IRQHandler /* ANATOP interrupt*/ + .long ANATOP_TEMP_PANIC_IRQHandler /* ANATOP interrupt*/ + .long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/ + .long USB_PHY2_IRQHandler /* USBPHY (UTMI0), Interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long ADC2_IRQHandler /* ADC2 interrupt*/ + .long DCDC_IRQHandler /* DCDC interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long Reserved87_IRQHandler /* Reserved interrupt*/ + .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ + .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ + .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ + .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ + .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ + .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ + .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ + .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ + .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ + .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ + .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ + .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ + .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ + .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ + .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ + .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ + .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ + .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ + .long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/ + .long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/ + .long WDOG1_IRQHandler /* WDOG1 interrupt*/ + .long RTWDOG_IRQHandler /* RTWDOG interrupt*/ + .long EWM_IRQHandler /* EWM interrupt*/ + .long CCM_1_IRQHandler /* CCM IRQ1 interrupt*/ + .long CCM_2_IRQHandler /* CCM IRQ2 interrupt*/ + .long GPC_IRQHandler /* GPC interrupt*/ + .long SRC_IRQHandler /* SRC interrupt*/ + .long Reserved115_IRQHandler /* Reserved interrupt*/ + .long GPT1_IRQHandler /* GPT1 interrupt*/ + .long GPT2_IRQHandler /* GPT2 interrupt*/ + .long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/ + .long Reserved123_IRQHandler /* Reserved interrupt*/ + .long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/ + .long SEMC_IRQHandler /* Reserved interrupt*/ + .long USDHC1_IRQHandler /* USDHC1 interrupt*/ + .long USDHC2_IRQHandler /* USDHC2 interrupt*/ + .long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/ + .long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/ + .long ENET_IRQHandler /* ENET interrupt*/ + .long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/ + .long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/ + .long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/ + .long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/ + .long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/ + .long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/ + .long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/ + .long PIT_IRQHandler /* PIT interrupt*/ + .long ACMP1_IRQHandler /* ACMP interrupt*/ + .long ACMP2_IRQHandler /* ACMP interrupt*/ + .long ACMP3_IRQHandler /* ACMP interrupt*/ + .long ACMP4_IRQHandler /* ACMP interrupt*/ + .long Reserved143_IRQHandler /* Reserved interrupt*/ + .long Reserved144_IRQHandler /* Reserved interrupt*/ + .long ENC1_IRQHandler /* ENC1 interrupt*/ + .long ENC2_IRQHandler /* ENC2 interrupt*/ + .long ENC3_IRQHandler /* ENC3 interrupt*/ + .long ENC4_IRQHandler /* ENC4 interrupt*/ + .long TMR1_IRQHandler /* TMR1 interrupt*/ + .long TMR2_IRQHandler /* TMR2 interrupt*/ + .long TMR3_IRQHandler /* TMR3 interrupt*/ + .long TMR4_IRQHandler /* TMR4 interrupt*/ + .long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/ + .long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/ + .long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/ + .long Reserved168_IRQHandler /* Reserved interrupt*/ + .long Reserved169_IRQHandler /* Reserved interrupt*/ + .long Reserved170_IRQHandler /* Reserved interrupt*/ + .long Reserved171_IRQHandler /* Reserved interrupt*/ + .long Reserved172_IRQHandler /* Reserved interrupt*/ + .long Reserved173_IRQHandler /* Reserved interrupt*/ + .long SJC_ARM_DEBUG_IRQHandler /* SJC ARM debug interrupt*/ + .long NMI_WAKEUP_IRQHandler /* NMI wake up*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * __noncachedata_start__/__noncachedata_end__ : none cachable region + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif +#ifdef __STARTUP_INITIALIZE_NONCACHEDATA + ldr r2, =__noncachedata_start__ + ldr r3, =__noncachedata_init_end__ +#if 1 +.LC2: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC2 +#else + subs r3, r2 + ble .LC3 +.LC2: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC2 +.LC3: +#endif +/* zero inited ncache section initialization */ + ldr r3, =__noncachedata_end__ + movs r0,0 +.LC4: + cmp r2,r3 + itt lt + strlt r0,[r2],#4 + blt .LC4 +#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC5: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC5 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak NMI_WAKEUP_IRQHandler + .type NMI_WAKEUP_IRQHandler, %function +NMI_WAKEUP_IRQHandler: + ldr r0,=NMI_WAKEUP_IRQHandler + bx r0 + .size NMI_WAKEUP_IRQHandler, . - NMI_WAKEUP_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_DMA16_IRQHandler + .type DMA0_DMA16_IRQHandler, %function +DMA0_DMA16_IRQHandler: + ldr r0,=DMA0_DMA16_DriverIRQHandler + bx r0 + .size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_DMA17_IRQHandler + .type DMA1_DMA17_IRQHandler, %function +DMA1_DMA17_IRQHandler: + ldr r0,=DMA1_DMA17_DriverIRQHandler + bx r0 + .size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_DMA18_IRQHandler + .type DMA2_DMA18_IRQHandler, %function +DMA2_DMA18_IRQHandler: + ldr r0,=DMA2_DMA18_DriverIRQHandler + bx r0 + .size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_DMA19_IRQHandler + .type DMA3_DMA19_IRQHandler, %function +DMA3_DMA19_IRQHandler: + ldr r0,=DMA3_DMA19_DriverIRQHandler + bx r0 + .size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_DMA20_IRQHandler + .type DMA4_DMA20_IRQHandler, %function +DMA4_DMA20_IRQHandler: + ldr r0,=DMA4_DMA20_DriverIRQHandler + bx r0 + .size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_DMA21_IRQHandler + .type DMA5_DMA21_IRQHandler, %function +DMA5_DMA21_IRQHandler: + ldr r0,=DMA5_DMA21_DriverIRQHandler + bx r0 + .size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_DMA22_IRQHandler + .type DMA6_DMA22_IRQHandler, %function +DMA6_DMA22_IRQHandler: + ldr r0,=DMA6_DMA22_DriverIRQHandler + bx r0 + .size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_DMA23_IRQHandler + .type DMA7_DMA23_IRQHandler, %function +DMA7_DMA23_IRQHandler: + ldr r0,=DMA7_DMA23_DriverIRQHandler + bx r0 + .size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_DMA24_IRQHandler + .type DMA8_DMA24_IRQHandler, %function +DMA8_DMA24_IRQHandler: + ldr r0,=DMA8_DMA24_DriverIRQHandler + bx r0 + .size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_DMA25_IRQHandler + .type DMA9_DMA25_IRQHandler, %function +DMA9_DMA25_IRQHandler: + ldr r0,=DMA9_DMA25_DriverIRQHandler + bx r0 + .size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_DMA26_IRQHandler + .type DMA10_DMA26_IRQHandler, %function +DMA10_DMA26_IRQHandler: + ldr r0,=DMA10_DMA26_DriverIRQHandler + bx r0 + .size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_DMA27_IRQHandler + .type DMA11_DMA27_IRQHandler, %function +DMA11_DMA27_IRQHandler: + ldr r0,=DMA11_DMA27_DriverIRQHandler + bx r0 + .size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_DMA28_IRQHandler + .type DMA12_DMA28_IRQHandler, %function +DMA12_DMA28_IRQHandler: + ldr r0,=DMA12_DMA28_DriverIRQHandler + bx r0 + .size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_DMA29_IRQHandler + .type DMA13_DMA29_IRQHandler, %function +DMA13_DMA29_IRQHandler: + ldr r0,=DMA13_DMA29_DriverIRQHandler + bx r0 + .size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_DMA30_IRQHandler + .type DMA14_DMA30_IRQHandler, %function +DMA14_DMA30_IRQHandler: + ldr r0,=DMA14_DMA30_DriverIRQHandler + bx r0 + .size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_DMA31_IRQHandler + .type DMA15_DMA31_IRQHandler, %function +DMA15_DMA31_IRQHandler: + ldr r0,=DMA15_DMA31_DriverIRQHandler + bx r0 + .size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler + + .align 1 + .thumb_func + .weak DMA_ERROR_IRQHandler + .type DMA_ERROR_IRQHandler, %function +DMA_ERROR_IRQHandler: + ldr r0,=DMA_ERROR_DriverIRQHandler + bx r0 + .size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak LPUART1_IRQHandler + .type LPUART1_IRQHandler, %function +LPUART1_IRQHandler: + ldr r0,=LPUART1_DriverIRQHandler + bx r0 + .size LPUART1_IRQHandler, . - LPUART1_IRQHandler + + .align 1 + .thumb_func + .weak LPUART2_IRQHandler + .type LPUART2_IRQHandler, %function +LPUART2_IRQHandler: + ldr r0,=LPUART2_DriverIRQHandler + bx r0 + .size LPUART2_IRQHandler, . - LPUART2_IRQHandler + + .align 1 + .thumb_func + .weak LPUART3_IRQHandler + .type LPUART3_IRQHandler, %function +LPUART3_IRQHandler: + ldr r0,=LPUART3_DriverIRQHandler + bx r0 + .size LPUART3_IRQHandler, . - LPUART3_IRQHandler + + .align 1 + .thumb_func + .weak LPUART4_IRQHandler + .type LPUART4_IRQHandler, %function +LPUART4_IRQHandler: + ldr r0,=LPUART4_DriverIRQHandler + bx r0 + .size LPUART4_IRQHandler, . - LPUART4_IRQHandler + + .align 1 + .thumb_func + .weak LPUART5_IRQHandler + .type LPUART5_IRQHandler, %function +LPUART5_IRQHandler: + ldr r0,=LPUART5_DriverIRQHandler + bx r0 + .size LPUART5_IRQHandler, . - LPUART5_IRQHandler + + .align 1 + .thumb_func + .weak LPUART6_IRQHandler + .type LPUART6_IRQHandler, %function +LPUART6_IRQHandler: + ldr r0,=LPUART6_DriverIRQHandler + bx r0 + .size LPUART6_IRQHandler, . - LPUART6_IRQHandler + + .align 1 + .thumb_func + .weak LPUART7_IRQHandler + .type LPUART7_IRQHandler, %function +LPUART7_IRQHandler: + ldr r0,=LPUART7_DriverIRQHandler + bx r0 + .size LPUART7_IRQHandler, . - LPUART7_IRQHandler + + .align 1 + .thumb_func + .weak LPUART8_IRQHandler + .type LPUART8_IRQHandler, %function +LPUART8_IRQHandler: + ldr r0,=LPUART8_DriverIRQHandler + bx r0 + .size LPUART8_IRQHandler, . - LPUART8_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C1_IRQHandler + .type LPI2C1_IRQHandler, %function +LPI2C1_IRQHandler: + ldr r0,=LPI2C1_DriverIRQHandler + bx r0 + .size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C2_IRQHandler + .type LPI2C2_IRQHandler, %function +LPI2C2_IRQHandler: + ldr r0,=LPI2C2_DriverIRQHandler + bx r0 + .size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C3_IRQHandler + .type LPI2C3_IRQHandler, %function +LPI2C3_IRQHandler: + ldr r0,=LPI2C3_DriverIRQHandler + bx r0 + .size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C4_IRQHandler + .type LPI2C4_IRQHandler, %function +LPI2C4_IRQHandler: + ldr r0,=LPI2C4_DriverIRQHandler + bx r0 + .size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI1_IRQHandler + .type LPSPI1_IRQHandler, %function +LPSPI1_IRQHandler: + ldr r0,=LPSPI1_DriverIRQHandler + bx r0 + .size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI2_IRQHandler + .type LPSPI2_IRQHandler, %function +LPSPI2_IRQHandler: + ldr r0,=LPSPI2_DriverIRQHandler + bx r0 + .size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI3_IRQHandler + .type LPSPI3_IRQHandler, %function +LPSPI3_IRQHandler: + ldr r0,=LPSPI3_DriverIRQHandler + bx r0 + .size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI4_IRQHandler + .type LPSPI4_IRQHandler, %function +LPSPI4_IRQHandler: + ldr r0,=LPSPI4_DriverIRQHandler + bx r0 + .size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQHandler + .type CAN1_IRQHandler, %function +CAN1_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_IRQHandler, . - CAN1_IRQHandler + + .align 1 + .thumb_func + .weak CAN2_IRQHandler + .type CAN2_IRQHandler, %function +CAN2_IRQHandler: + ldr r0,=CAN2_DriverIRQHandler + bx r0 + .size CAN2_IRQHandler, . - CAN2_IRQHandler + + .align 1 + .thumb_func + .weak SAI1_IRQHandler + .type SAI1_IRQHandler, %function +SAI1_IRQHandler: + ldr r0,=SAI1_DriverIRQHandler + bx r0 + .size SAI1_IRQHandler, . - SAI1_IRQHandler + + .align 1 + .thumb_func + .weak SAI2_IRQHandler + .type SAI2_IRQHandler, %function +SAI2_IRQHandler: + ldr r0,=SAI2_DriverIRQHandler + bx r0 + .size SAI2_IRQHandler, . - SAI2_IRQHandler + + .align 1 + .thumb_func + .weak SAI3_RX_IRQHandler + .type SAI3_RX_IRQHandler, %function +SAI3_RX_IRQHandler: + ldr r0,=SAI3_RX_DriverIRQHandler + bx r0 + .size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler + + .align 1 + .thumb_func + .weak SAI3_TX_IRQHandler + .type SAI3_TX_IRQHandler, %function +SAI3_TX_IRQHandler: + ldr r0,=SAI3_TX_DriverIRQHandler + bx r0 + .size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler + + .align 1 + .thumb_func + .weak SPDIF_IRQHandler + .type SPDIF_IRQHandler, %function +SPDIF_IRQHandler: + ldr r0,=SPDIF_DriverIRQHandler + bx r0 + .size SPDIF_IRQHandler, . - SPDIF_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO1_IRQHandler + .type FLEXIO1_IRQHandler, %function +FLEXIO1_IRQHandler: + ldr r0,=FLEXIO1_DriverIRQHandler + bx r0 + .size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO2_IRQHandler + .type FLEXIO2_IRQHandler, %function +FLEXIO2_IRQHandler: + ldr r0,=FLEXIO2_DriverIRQHandler + bx r0 + .size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXSPI_IRQHandler + .type FLEXSPI_IRQHandler, %function +FLEXSPI_IRQHandler: + ldr r0,=FLEXSPI_DriverIRQHandler + bx r0 + .size FLEXSPI_IRQHandler, . - FLEXSPI_IRQHandler + + .align 1 + .thumb_func + .weak USDHC1_IRQHandler + .type USDHC1_IRQHandler, %function +USDHC1_IRQHandler: + ldr r0,=USDHC1_DriverIRQHandler + bx r0 + .size USDHC1_IRQHandler, . - USDHC1_IRQHandler + + .align 1 + .thumb_func + .weak USDHC2_IRQHandler + .type USDHC2_IRQHandler, %function +USDHC2_IRQHandler: + ldr r0,=USDHC2_DriverIRQHandler + bx r0 + .size USDHC2_IRQHandler, . - USDHC2_IRQHandler + + .align 1 + .thumb_func + .weak ENET_IRQHandler + .type ENET_IRQHandler, %function +ENET_IRQHandler: + ldr r0,=ENET_DriverIRQHandler + bx r0 + .size ENET_IRQHandler, . - ENET_IRQHandler + + .align 1 + .thumb_func + .weak ENET_1588_Timer_IRQHandler + .type ENET_1588_Timer_IRQHandler, %function +ENET_1588_Timer_IRQHandler: + ldr r0,=ENET_1588_Timer_DriverIRQHandler + bx r0 + .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DMA16_DriverIRQHandler + def_irq_handler DMA1_DMA17_DriverIRQHandler + def_irq_handler DMA2_DMA18_DriverIRQHandler + def_irq_handler DMA3_DMA19_DriverIRQHandler + def_irq_handler DMA4_DMA20_DriverIRQHandler + def_irq_handler DMA5_DMA21_DriverIRQHandler + def_irq_handler DMA6_DMA22_DriverIRQHandler + def_irq_handler DMA7_DMA23_DriverIRQHandler + def_irq_handler DMA8_DMA24_DriverIRQHandler + def_irq_handler DMA9_DMA25_DriverIRQHandler + def_irq_handler DMA10_DMA26_DriverIRQHandler + def_irq_handler DMA11_DMA27_DriverIRQHandler + def_irq_handler DMA12_DMA28_DriverIRQHandler + def_irq_handler DMA13_DMA29_DriverIRQHandler + def_irq_handler DMA14_DMA30_DriverIRQHandler + def_irq_handler DMA15_DMA31_DriverIRQHandler + def_irq_handler DMA_ERROR_DriverIRQHandler + def_irq_handler CTI0_ERROR_IRQHandler + def_irq_handler CTI1_ERROR_IRQHandler + def_irq_handler CORE_IRQHandler + def_irq_handler LPUART1_DriverIRQHandler + def_irq_handler LPUART2_DriverIRQHandler + def_irq_handler LPUART3_DriverIRQHandler + def_irq_handler LPUART4_DriverIRQHandler + def_irq_handler LPUART5_DriverIRQHandler + def_irq_handler LPUART6_DriverIRQHandler + def_irq_handler LPUART7_DriverIRQHandler + def_irq_handler LPUART8_DriverIRQHandler + def_irq_handler LPI2C1_DriverIRQHandler + def_irq_handler LPI2C2_DriverIRQHandler + def_irq_handler LPI2C3_DriverIRQHandler + def_irq_handler LPI2C4_DriverIRQHandler + def_irq_handler LPSPI1_DriverIRQHandler + def_irq_handler LPSPI2_DriverIRQHandler + def_irq_handler LPSPI3_DriverIRQHandler + def_irq_handler LPSPI4_DriverIRQHandler + def_irq_handler CAN1_DriverIRQHandler + def_irq_handler CAN2_DriverIRQHandler + def_irq_handler FLEXRAM_IRQHandler + def_irq_handler KPP_IRQHandler + def_irq_handler TSC_DIG_IRQHandler + def_irq_handler GPR_IRQ_IRQHandler + def_irq_handler LCDIF_IRQHandler + def_irq_handler CSI_IRQHandler + def_irq_handler PXP_IRQHandler + def_irq_handler WDOG2_IRQHandler + def_irq_handler SNVS_HP_WRAPPER_IRQHandler + def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler + def_irq_handler SNVS_LP_WRAPPER_IRQHandler + def_irq_handler CSU_IRQHandler + def_irq_handler DCP_IRQHandler + def_irq_handler DCP_VMI_IRQHandler + def_irq_handler Reserved68_IRQHandler + def_irq_handler TRNG_IRQHandler + def_irq_handler SJC_IRQHandler + def_irq_handler BEE_IRQHandler + def_irq_handler SAI1_DriverIRQHandler + def_irq_handler SAI2_DriverIRQHandler + def_irq_handler SAI3_RX_DriverIRQHandler + def_irq_handler SAI3_TX_DriverIRQHandler + def_irq_handler SPDIF_DriverIRQHandler + def_irq_handler ANATOP_EVENT0_IRQHandler + def_irq_handler ANATOP_EVENT1_IRQHandler + def_irq_handler ANATOP_TAMP_LOW_HIGH_IRQHandler + def_irq_handler ANATOP_TEMP_PANIC_IRQHandler + def_irq_handler USB_PHY1_IRQHandler + def_irq_handler USB_PHY2_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler ADC2_IRQHandler + def_irq_handler DCDC_IRQHandler + def_irq_handler Reserved86_IRQHandler + def_irq_handler Reserved87_IRQHandler + def_irq_handler GPIO1_INT0_IRQHandler + def_irq_handler GPIO1_INT1_IRQHandler + def_irq_handler GPIO1_INT2_IRQHandler + def_irq_handler GPIO1_INT3_IRQHandler + def_irq_handler GPIO1_INT4_IRQHandler + def_irq_handler GPIO1_INT5_IRQHandler + def_irq_handler GPIO1_INT6_IRQHandler + def_irq_handler GPIO1_INT7_IRQHandler + def_irq_handler GPIO1_Combined_0_15_IRQHandler + def_irq_handler GPIO1_Combined_16_31_IRQHandler + def_irq_handler GPIO2_Combined_0_15_IRQHandler + def_irq_handler GPIO2_Combined_16_31_IRQHandler + def_irq_handler GPIO3_Combined_0_15_IRQHandler + def_irq_handler GPIO3_Combined_16_31_IRQHandler + def_irq_handler GPIO4_Combined_0_15_IRQHandler + def_irq_handler GPIO4_Combined_16_31_IRQHandler + def_irq_handler GPIO5_Combined_0_15_IRQHandler + def_irq_handler GPIO5_Combined_16_31_IRQHandler + def_irq_handler FLEXIO1_DriverIRQHandler + def_irq_handler FLEXIO2_DriverIRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler RTWDOG_IRQHandler + def_irq_handler EWM_IRQHandler + def_irq_handler CCM_1_IRQHandler + def_irq_handler CCM_2_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler SRC_IRQHandler + def_irq_handler Reserved115_IRQHandler + def_irq_handler GPT1_IRQHandler + def_irq_handler GPT2_IRQHandler + def_irq_handler PWM1_0_IRQHandler + def_irq_handler PWM1_1_IRQHandler + def_irq_handler PWM1_2_IRQHandler + def_irq_handler PWM1_3_IRQHandler + def_irq_handler PWM1_FAULT_IRQHandler + def_irq_handler Reserved123_IRQHandler + def_irq_handler FLEXSPI_DriverIRQHandler + def_irq_handler SEMC_IRQHandler + def_irq_handler USDHC1_DriverIRQHandler + def_irq_handler USDHC2_DriverIRQHandler + def_irq_handler USB_OTG2_IRQHandler + def_irq_handler USB_OTG1_IRQHandler + def_irq_handler ENET_DriverIRQHandler + def_irq_handler ENET_1588_Timer_DriverIRQHandler + def_irq_handler XBAR1_IRQ_0_1_IRQHandler + def_irq_handler XBAR1_IRQ_2_3_IRQHandler + def_irq_handler ADC_ETC_IRQ0_IRQHandler + def_irq_handler ADC_ETC_IRQ1_IRQHandler + def_irq_handler ADC_ETC_IRQ2_IRQHandler + def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler + def_irq_handler PIT_IRQHandler + def_irq_handler ACMP1_IRQHandler + def_irq_handler ACMP2_IRQHandler + def_irq_handler ACMP3_IRQHandler + def_irq_handler ACMP4_IRQHandler + def_irq_handler Reserved143_IRQHandler + def_irq_handler Reserved144_IRQHandler + def_irq_handler ENC1_IRQHandler + def_irq_handler ENC2_IRQHandler + def_irq_handler ENC3_IRQHandler + def_irq_handler ENC4_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler TMR4_IRQHandler + def_irq_handler PWM2_0_IRQHandler + def_irq_handler PWM2_1_IRQHandler + def_irq_handler PWM2_2_IRQHandler + def_irq_handler PWM2_3_IRQHandler + def_irq_handler PWM2_FAULT_IRQHandler + def_irq_handler PWM3_0_IRQHandler + def_irq_handler PWM3_1_IRQHandler + def_irq_handler PWM3_2_IRQHandler + def_irq_handler PWM3_3_IRQHandler + def_irq_handler PWM3_FAULT_IRQHandler + def_irq_handler PWM4_0_IRQHandler + def_irq_handler PWM4_1_IRQHandler + def_irq_handler PWM4_2_IRQHandler + def_irq_handler PWM4_3_IRQHandler + def_irq_handler PWM4_FAULT_IRQHandler + def_irq_handler Reserved168_IRQHandler + def_irq_handler Reserved169_IRQHandler + def_irq_handler Reserved170_IRQHandler + def_irq_handler Reserved171_IRQHandler + def_irq_handler Reserved172_IRQHandler + def_irq_handler Reserved173_IRQHandler + def_irq_handler SJC_ARM_DEBUG_IRQHandler + + .end diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_flexspi_nor.icf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_flexspi_nor.icf new file mode 100644 index 0000000000..278e9d531b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_flexspi_nor.icf @@ -0,0 +1,122 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x63FFFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2023FFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_flexspi_nor_sdram.icf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_flexspi_nor_sdram.icf new file mode 100644 index 0000000000..ea4c46c563 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_flexspi_nor_sdram.icf @@ -0,0 +1,130 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x63FFFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2023FFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_ram.icf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_ram.icf new file mode 100644 index 0000000000..0719f0365a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_ram.icf @@ -0,0 +1,110 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0001FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2023FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_sdram.icf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_sdram.icf new file mode 100644 index 0000000000..e116185bc4 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_sdram.icf @@ -0,0 +1,118 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0001FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2023FFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_sdram_txt.icf b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_sdram_txt.icf new file mode 100644 index 0000000000..e980d3d60d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/MIMXRT1052xxxxx_sdram_txt.icf @@ -0,0 +1,118 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x80000000; +define symbol m_interrupts_end = 0x800003FF; + +define symbol m_text_start = 0x80000400; +define symbol m_text_end = 0x801FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2023FFFF; + +define symbol m_data3_start = 0x80200000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end]; +define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA2_region { block RW }; +place in DATA2_region { block ZI }; +place in DATA2_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/startup_MIMXRT1052.s b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/startup_MIMXRT1052.s new file mode 100644 index 0000000000..620c96ee70 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/iar/startup_MIMXRT1052.s @@ -0,0 +1,1016 @@ +; ------------------------------------------------------------------------- +; @file: startup_MIMXRT1052.s +; @purpose: CMSIS Cortex-M7 Core Device Startup File +; MIMXRT1052 +; @version: 0.1 +; @date: 2017-1-10 +; @build: b180509 +; ------------------------------------------------------------------------- +; +; The Clear BSD License +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2018 NXP +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted (subject to the limitations in the +; disclaimer below) provided that the following conditions are met: +; +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; * Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +; GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +; HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +; BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +; IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete + DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete + DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete + DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete + DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete + DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete + DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete + DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete + DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete + DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete + DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete + DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete + DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete + DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete + DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete + DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete + DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31 + DCD CTI0_ERROR_IRQHandler ;CTI0_Error + DCD CTI1_ERROR_IRQHandler ;CTI1_Error + DCD CORE_IRQHandler ;CorePlatform exception IRQ + DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt + DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt + DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt + DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt + DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt + DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt + DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt + DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt + DCD LPI2C1_IRQHandler ;LPI2C1 interrupt + DCD LPI2C2_IRQHandler ;LPI2C2 interrupt + DCD LPI2C3_IRQHandler ;LPI2C3 interrupt + DCD LPI2C4_IRQHandler ;LPI2C4 interrupt + DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources + DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources + DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources + DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources + DCD CAN1_IRQHandler ;CAN1 interrupt + DCD CAN2_IRQHandler ;CAN2 interrupt + DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ + DCD KPP_IRQHandler ;Keypad nterrupt + DCD TSC_DIG_IRQHandler ;TSC interrupt + DCD GPR_IRQ_IRQHandler ;GPR interrupt + DCD LCDIF_IRQHandler ;LCDIF interrupt + DCD CSI_IRQHandler ;CSI interrupt + DCD PXP_IRQHandler ;PXP interrupt + DCD WDOG2_IRQHandler ;WDOG2 interrupt + DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ + DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ + DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event) + DCD CSU_IRQHandler ;CSU interrupt + DCD DCP_IRQHandler ;DCP_IRQ interrupt + DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt + DCD Reserved68_IRQHandler ;Reserved interrupt + DCD TRNG_IRQHandler ;TRNG interrupt + DCD SJC_IRQHandler ;SJC interrupt + DCD BEE_IRQHandler ;BEE interrupt + DCD SAI1_IRQHandler ;SAI1 interrupt + DCD SAI2_IRQHandler ;SAI1 interrupt + DCD SAI3_RX_IRQHandler ;SAI3 interrupt + DCD SAI3_TX_IRQHandler ;SAI3 interrupt + DCD SPDIF_IRQHandler ;SPDIF interrupt + DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt + DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt + DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt + DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt + DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt + DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD ADC2_IRQHandler ;ADC2 interrupt + DCD DCDC_IRQHandler ;DCDC interrupt + DCD Reserved86_IRQHandler ;Reserved interrupt + DCD Reserved87_IRQHandler ;Reserved interrupt + DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO + DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO + DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO + DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO + DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO + DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO + DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO + DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO + DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 + DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 + DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 + DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 + DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 + DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 + DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 + DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 + DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 + DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 + DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt + DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt + DCD WDOG1_IRQHandler ;WDOG1 interrupt + DCD RTWDOG_IRQHandler ;RTWDOG interrupt + DCD EWM_IRQHandler ;EWM interrupt + DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt + DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt + DCD GPC_IRQHandler ;GPC interrupt + DCD SRC_IRQHandler ;SRC interrupt + DCD Reserved115_IRQHandler ;Reserved interrupt + DCD GPT1_IRQHandler ;GPT1 interrupt + DCD GPT2_IRQHandler ;GPT2 interrupt + DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt + DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt + DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt + DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt + DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt + DCD Reserved123_IRQHandler ;Reserved interrupt + DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt + DCD SEMC_IRQHandler ;Reserved interrupt + DCD USDHC1_IRQHandler ;USDHC1 interrupt + DCD USDHC2_IRQHandler ;USDHC2 interrupt + DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 + DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1 + DCD ENET_IRQHandler ;ENET interrupt + DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt + DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt + DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt + DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt + DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt + DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt + DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt + DCD PIT_IRQHandler ;PIT interrupt + DCD ACMP1_IRQHandler ;ACMP interrupt + DCD ACMP2_IRQHandler ;ACMP interrupt + DCD ACMP3_IRQHandler ;ACMP interrupt + DCD ACMP4_IRQHandler ;ACMP interrupt + DCD Reserved143_IRQHandler ;Reserved interrupt + DCD Reserved144_IRQHandler ;Reserved interrupt + DCD ENC1_IRQHandler ;ENC1 interrupt + DCD ENC2_IRQHandler ;ENC2 interrupt + DCD ENC3_IRQHandler ;ENC3 interrupt + DCD ENC4_IRQHandler ;ENC4 interrupt + DCD TMR1_IRQHandler ;TMR1 interrupt + DCD TMR2_IRQHandler ;TMR2 interrupt + DCD TMR3_IRQHandler ;TMR3 interrupt + DCD TMR4_IRQHandler ;TMR4 interrupt + DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt + DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt + DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt + DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt + DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt + DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt + DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt + DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt + DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt + DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt + DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt + DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt + DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt + DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt + DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt + DCD Reserved168_IRQHandler ;Reserved interrupt + DCD Reserved169_IRQHandler ;Reserved interrupt + DCD Reserved170_IRQHandler ;Reserved interrupt + DCD Reserved171_IRQHandler ;Reserved interrupt + DCD Reserved172_IRQHandler ;Reserved interrupt + DCD Reserved173_IRQHandler ;Reserved interrupt + DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt + DCD NMI_WAKEUP_IRQHandler ;NMI wake up + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_DMA16_IRQHandler + PUBWEAK DMA0_DMA16_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DMA16_IRQHandler + LDR R0, =DMA0_DMA16_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_DMA17_IRQHandler + PUBWEAK DMA1_DMA17_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_DMA17_IRQHandler + LDR R0, =DMA1_DMA17_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_DMA18_IRQHandler + PUBWEAK DMA2_DMA18_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_DMA18_IRQHandler + LDR R0, =DMA2_DMA18_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_DMA19_IRQHandler + PUBWEAK DMA3_DMA19_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_DMA19_IRQHandler + LDR R0, =DMA3_DMA19_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_DMA20_IRQHandler + PUBWEAK DMA4_DMA20_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_DMA20_IRQHandler + LDR R0, =DMA4_DMA20_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_DMA21_IRQHandler + PUBWEAK DMA5_DMA21_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_DMA21_IRQHandler + LDR R0, =DMA5_DMA21_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_DMA22_IRQHandler + PUBWEAK DMA6_DMA22_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_DMA22_IRQHandler + LDR R0, =DMA6_DMA22_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_DMA23_IRQHandler + PUBWEAK DMA7_DMA23_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_DMA23_IRQHandler + LDR R0, =DMA7_DMA23_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_DMA24_IRQHandler + PUBWEAK DMA8_DMA24_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_DMA24_IRQHandler + LDR R0, =DMA8_DMA24_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_DMA25_IRQHandler + PUBWEAK DMA9_DMA25_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_DMA25_IRQHandler + LDR R0, =DMA9_DMA25_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_DMA26_IRQHandler + PUBWEAK DMA10_DMA26_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_DMA26_IRQHandler + LDR R0, =DMA10_DMA26_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_DMA27_IRQHandler + PUBWEAK DMA11_DMA27_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_DMA27_IRQHandler + LDR R0, =DMA11_DMA27_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_DMA28_IRQHandler + PUBWEAK DMA12_DMA28_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_DMA28_IRQHandler + LDR R0, =DMA12_DMA28_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_DMA29_IRQHandler + PUBWEAK DMA13_DMA29_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_DMA29_IRQHandler + LDR R0, =DMA13_DMA29_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_DMA30_IRQHandler + PUBWEAK DMA14_DMA30_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_DMA30_IRQHandler + LDR R0, =DMA14_DMA30_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_DMA31_IRQHandler + PUBWEAK DMA15_DMA31_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_DMA31_IRQHandler + LDR R0, =DMA15_DMA31_DriverIRQHandler + BX R0 + + PUBWEAK DMA_ERROR_IRQHandler + PUBWEAK DMA_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_ERROR_IRQHandler + LDR R0, =DMA_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK CTI0_ERROR_IRQHandler + PUBWEAK CTI1_ERROR_IRQHandler + PUBWEAK CORE_IRQHandler + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART2_IRQHandler + PUBWEAK LPUART2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART2_IRQHandler + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + + PUBWEAK LPUART3_IRQHandler + PUBWEAK LPUART3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART3_IRQHandler + LDR R0, =LPUART3_DriverIRQHandler + BX R0 + + PUBWEAK LPUART4_IRQHandler + PUBWEAK LPUART4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART4_IRQHandler + LDR R0, =LPUART4_DriverIRQHandler + BX R0 + + PUBWEAK LPUART5_IRQHandler + PUBWEAK LPUART5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART5_IRQHandler + LDR R0, =LPUART5_DriverIRQHandler + BX R0 + + PUBWEAK LPUART6_IRQHandler + PUBWEAK LPUART6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART6_IRQHandler + LDR R0, =LPUART6_DriverIRQHandler + BX R0 + + PUBWEAK LPUART7_IRQHandler + PUBWEAK LPUART7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART7_IRQHandler + LDR R0, =LPUART7_DriverIRQHandler + BX R0 + + PUBWEAK LPUART8_IRQHandler + PUBWEAK LPUART8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART8_IRQHandler + LDR R0, =LPUART8_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C1_IRQHandler + PUBWEAK LPI2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C1_IRQHandler + LDR R0, =LPI2C1_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C2_IRQHandler + PUBWEAK LPI2C2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C2_IRQHandler + LDR R0, =LPI2C2_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C3_IRQHandler + PUBWEAK LPI2C3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C3_IRQHandler + LDR R0, =LPI2C3_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C4_IRQHandler + PUBWEAK LPI2C4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C4_IRQHandler + LDR R0, =LPI2C4_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI1_IRQHandler + PUBWEAK LPSPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI1_IRQHandler + LDR R0, =LPSPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI2_IRQHandler + PUBWEAK LPSPI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI2_IRQHandler + LDR R0, =LPSPI2_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI3_IRQHandler + PUBWEAK LPSPI3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI3_IRQHandler + LDR R0, =LPSPI3_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI4_IRQHandler + PUBWEAK LPSPI4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI4_IRQHandler + LDR R0, =LPSPI4_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQHandler + PUBWEAK CAN1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQHandler + LDR R0, =CAN1_DriverIRQHandler + BX R0 + + PUBWEAK CAN2_IRQHandler + PUBWEAK CAN2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN2_IRQHandler + LDR R0, =CAN2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXRAM_IRQHandler + PUBWEAK KPP_IRQHandler + PUBWEAK TSC_DIG_IRQHandler + PUBWEAK GPR_IRQ_IRQHandler + PUBWEAK LCDIF_IRQHandler + PUBWEAK CSI_IRQHandler + PUBWEAK PXP_IRQHandler + PUBWEAK WDOG2_IRQHandler + PUBWEAK SNVS_HP_WRAPPER_IRQHandler + PUBWEAK SNVS_HP_WRAPPER_TZ_IRQHandler + PUBWEAK SNVS_LP_WRAPPER_IRQHandler + PUBWEAK CSU_IRQHandler + PUBWEAK DCP_IRQHandler + PUBWEAK DCP_VMI_IRQHandler + PUBWEAK Reserved68_IRQHandler + PUBWEAK TRNG_IRQHandler + PUBWEAK SJC_IRQHandler + PUBWEAK BEE_IRQHandler + PUBWEAK SAI1_IRQHandler + PUBWEAK SAI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI1_IRQHandler + LDR R0, =SAI1_DriverIRQHandler + BX R0 + + PUBWEAK SAI2_IRQHandler + PUBWEAK SAI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI2_IRQHandler + LDR R0, =SAI2_DriverIRQHandler + BX R0 + + PUBWEAK SAI3_RX_IRQHandler + PUBWEAK SAI3_RX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI3_RX_IRQHandler + LDR R0, =SAI3_RX_DriverIRQHandler + BX R0 + + PUBWEAK SAI3_TX_IRQHandler + PUBWEAK SAI3_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI3_TX_IRQHandler + LDR R0, =SAI3_TX_DriverIRQHandler + BX R0 + + PUBWEAK SPDIF_IRQHandler + PUBWEAK SPDIF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPDIF_IRQHandler + LDR R0, =SPDIF_DriverIRQHandler + BX R0 + + PUBWEAK ANATOP_EVENT0_IRQHandler + PUBWEAK ANATOP_EVENT1_IRQHandler + PUBWEAK ANATOP_TAMP_LOW_HIGH_IRQHandler + PUBWEAK ANATOP_TEMP_PANIC_IRQHandler + PUBWEAK USB_PHY1_IRQHandler + PUBWEAK USB_PHY2_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK ADC2_IRQHandler + PUBWEAK DCDC_IRQHandler + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved87_IRQHandler + PUBWEAK GPIO1_INT0_IRQHandler + PUBWEAK GPIO1_INT1_IRQHandler + PUBWEAK GPIO1_INT2_IRQHandler + PUBWEAK GPIO1_INT3_IRQHandler + PUBWEAK GPIO1_INT4_IRQHandler + PUBWEAK GPIO1_INT5_IRQHandler + PUBWEAK GPIO1_INT6_IRQHandler + PUBWEAK GPIO1_INT7_IRQHandler + PUBWEAK GPIO1_Combined_0_15_IRQHandler + PUBWEAK GPIO1_Combined_16_31_IRQHandler + PUBWEAK GPIO2_Combined_0_15_IRQHandler + PUBWEAK GPIO2_Combined_16_31_IRQHandler + PUBWEAK GPIO3_Combined_0_15_IRQHandler + PUBWEAK GPIO3_Combined_16_31_IRQHandler + PUBWEAK GPIO4_Combined_0_15_IRQHandler + PUBWEAK GPIO4_Combined_16_31_IRQHandler + PUBWEAK GPIO5_Combined_0_15_IRQHandler + PUBWEAK GPIO5_Combined_16_31_IRQHandler + PUBWEAK FLEXIO1_IRQHandler + PUBWEAK FLEXIO1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO1_IRQHandler + LDR R0, =FLEXIO1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXIO2_IRQHandler + PUBWEAK FLEXIO2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO2_IRQHandler + LDR R0, =FLEXIO2_DriverIRQHandler + BX R0 + + PUBWEAK WDOG1_IRQHandler + PUBWEAK RTWDOG_IRQHandler + PUBWEAK EWM_IRQHandler + PUBWEAK CCM_1_IRQHandler + PUBWEAK CCM_2_IRQHandler + PUBWEAK GPC_IRQHandler + PUBWEAK SRC_IRQHandler + PUBWEAK Reserved115_IRQHandler + PUBWEAK GPT1_IRQHandler + PUBWEAK GPT2_IRQHandler + PUBWEAK PWM1_0_IRQHandler + PUBWEAK PWM1_1_IRQHandler + PUBWEAK PWM1_2_IRQHandler + PUBWEAK PWM1_3_IRQHandler + PUBWEAK PWM1_FAULT_IRQHandler + PUBWEAK Reserved123_IRQHandler + PUBWEAK FLEXSPI_IRQHandler + PUBWEAK FLEXSPI_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXSPI_IRQHandler + LDR R0, =FLEXSPI_DriverIRQHandler + BX R0 + + PUBWEAK SEMC_IRQHandler + PUBWEAK USDHC1_IRQHandler + PUBWEAK USDHC1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USDHC1_IRQHandler + LDR R0, =USDHC1_DriverIRQHandler + BX R0 + + PUBWEAK USDHC2_IRQHandler + PUBWEAK USDHC2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USDHC2_IRQHandler + LDR R0, =USDHC2_DriverIRQHandler + BX R0 + + PUBWEAK USB_OTG2_IRQHandler + PUBWEAK USB_OTG1_IRQHandler + PUBWEAK ENET_IRQHandler + PUBWEAK ENET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_IRQHandler + LDR R0, =ENET_DriverIRQHandler + BX R0 + + PUBWEAK ENET_1588_Timer_IRQHandler + PUBWEAK ENET_1588_Timer_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_1588_Timer_IRQHandler + LDR R0, =ENET_1588_Timer_DriverIRQHandler + BX R0 + + PUBWEAK XBAR1_IRQ_0_1_IRQHandler + PUBWEAK XBAR1_IRQ_2_3_IRQHandler + PUBWEAK ADC_ETC_IRQ0_IRQHandler + PUBWEAK ADC_ETC_IRQ1_IRQHandler + PUBWEAK ADC_ETC_IRQ2_IRQHandler + PUBWEAK ADC_ETC_ERROR_IRQ_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK ACMP1_IRQHandler + PUBWEAK ACMP2_IRQHandler + PUBWEAK ACMP3_IRQHandler + PUBWEAK ACMP4_IRQHandler + PUBWEAK Reserved143_IRQHandler + PUBWEAK Reserved144_IRQHandler + PUBWEAK ENC1_IRQHandler + PUBWEAK ENC2_IRQHandler + PUBWEAK ENC3_IRQHandler + PUBWEAK ENC4_IRQHandler + PUBWEAK TMR1_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK TMR4_IRQHandler + PUBWEAK PWM2_0_IRQHandler + PUBWEAK PWM2_1_IRQHandler + PUBWEAK PWM2_2_IRQHandler + PUBWEAK PWM2_3_IRQHandler + PUBWEAK PWM2_FAULT_IRQHandler + PUBWEAK PWM3_0_IRQHandler + PUBWEAK PWM3_1_IRQHandler + PUBWEAK PWM3_2_IRQHandler + PUBWEAK PWM3_3_IRQHandler + PUBWEAK PWM3_FAULT_IRQHandler + PUBWEAK PWM4_0_IRQHandler + PUBWEAK PWM4_1_IRQHandler + PUBWEAK PWM4_2_IRQHandler + PUBWEAK PWM4_3_IRQHandler + PUBWEAK PWM4_FAULT_IRQHandler + PUBWEAK Reserved168_IRQHandler + PUBWEAK Reserved169_IRQHandler + PUBWEAK Reserved170_IRQHandler + PUBWEAK Reserved171_IRQHandler + PUBWEAK Reserved172_IRQHandler + PUBWEAK Reserved173_IRQHandler + PUBWEAK SJC_ARM_DEBUG_IRQHandler + PUBWEAK NMI_WAKEUP_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DMA16_DriverIRQHandler +DMA1_DMA17_DriverIRQHandler +DMA2_DMA18_DriverIRQHandler +DMA3_DMA19_DriverIRQHandler +DMA4_DMA20_DriverIRQHandler +DMA5_DMA21_DriverIRQHandler +DMA6_DMA22_DriverIRQHandler +DMA7_DMA23_DriverIRQHandler +DMA8_DMA24_DriverIRQHandler +DMA9_DMA25_DriverIRQHandler +DMA10_DMA26_DriverIRQHandler +DMA11_DMA27_DriverIRQHandler +DMA12_DMA28_DriverIRQHandler +DMA13_DMA29_DriverIRQHandler +DMA14_DMA30_DriverIRQHandler +DMA15_DMA31_DriverIRQHandler +DMA_ERROR_DriverIRQHandler +CTI0_ERROR_IRQHandler +CTI1_ERROR_IRQHandler +CORE_IRQHandler +LPUART1_DriverIRQHandler +LPUART2_DriverIRQHandler +LPUART3_DriverIRQHandler +LPUART4_DriverIRQHandler +LPUART5_DriverIRQHandler +LPUART6_DriverIRQHandler +LPUART7_DriverIRQHandler +LPUART8_DriverIRQHandler +LPI2C1_DriverIRQHandler +LPI2C2_DriverIRQHandler +LPI2C3_DriverIRQHandler +LPI2C4_DriverIRQHandler +LPSPI1_DriverIRQHandler +LPSPI2_DriverIRQHandler +LPSPI3_DriverIRQHandler +LPSPI4_DriverIRQHandler +CAN1_DriverIRQHandler +CAN2_DriverIRQHandler +FLEXRAM_IRQHandler +KPP_IRQHandler +TSC_DIG_IRQHandler +GPR_IRQ_IRQHandler +LCDIF_IRQHandler +CSI_IRQHandler +PXP_IRQHandler +WDOG2_IRQHandler +SNVS_HP_WRAPPER_IRQHandler +SNVS_HP_WRAPPER_TZ_IRQHandler +SNVS_LP_WRAPPER_IRQHandler +CSU_IRQHandler +DCP_IRQHandler +DCP_VMI_IRQHandler +Reserved68_IRQHandler +TRNG_IRQHandler +SJC_IRQHandler +BEE_IRQHandler +SAI1_DriverIRQHandler +SAI2_DriverIRQHandler +SAI3_RX_DriverIRQHandler +SAI3_TX_DriverIRQHandler +SPDIF_DriverIRQHandler +ANATOP_EVENT0_IRQHandler +ANATOP_EVENT1_IRQHandler +ANATOP_TAMP_LOW_HIGH_IRQHandler +ANATOP_TEMP_PANIC_IRQHandler +USB_PHY1_IRQHandler +USB_PHY2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +DCDC_IRQHandler +Reserved86_IRQHandler +Reserved87_IRQHandler +GPIO1_INT0_IRQHandler +GPIO1_INT1_IRQHandler +GPIO1_INT2_IRQHandler +GPIO1_INT3_IRQHandler +GPIO1_INT4_IRQHandler +GPIO1_INT5_IRQHandler +GPIO1_INT6_IRQHandler +GPIO1_INT7_IRQHandler +GPIO1_Combined_0_15_IRQHandler +GPIO1_Combined_16_31_IRQHandler +GPIO2_Combined_0_15_IRQHandler +GPIO2_Combined_16_31_IRQHandler +GPIO3_Combined_0_15_IRQHandler +GPIO3_Combined_16_31_IRQHandler +GPIO4_Combined_0_15_IRQHandler +GPIO4_Combined_16_31_IRQHandler +GPIO5_Combined_0_15_IRQHandler +GPIO5_Combined_16_31_IRQHandler +FLEXIO1_DriverIRQHandler +FLEXIO2_DriverIRQHandler +WDOG1_IRQHandler +RTWDOG_IRQHandler +EWM_IRQHandler +CCM_1_IRQHandler +CCM_2_IRQHandler +GPC_IRQHandler +SRC_IRQHandler +Reserved115_IRQHandler +GPT1_IRQHandler +GPT2_IRQHandler +PWM1_0_IRQHandler +PWM1_1_IRQHandler +PWM1_2_IRQHandler +PWM1_3_IRQHandler +PWM1_FAULT_IRQHandler +Reserved123_IRQHandler +FLEXSPI_DriverIRQHandler +SEMC_IRQHandler +USDHC1_DriverIRQHandler +USDHC2_DriverIRQHandler +USB_OTG2_IRQHandler +USB_OTG1_IRQHandler +ENET_DriverIRQHandler +ENET_1588_Timer_DriverIRQHandler +XBAR1_IRQ_0_1_IRQHandler +XBAR1_IRQ_2_3_IRQHandler +ADC_ETC_IRQ0_IRQHandler +ADC_ETC_IRQ1_IRQHandler +ADC_ETC_IRQ2_IRQHandler +ADC_ETC_ERROR_IRQ_IRQHandler +PIT_IRQHandler +ACMP1_IRQHandler +ACMP2_IRQHandler +ACMP3_IRQHandler +ACMP4_IRQHandler +Reserved143_IRQHandler +Reserved144_IRQHandler +ENC1_IRQHandler +ENC2_IRQHandler +ENC3_IRQHandler +ENC4_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +PWM2_0_IRQHandler +PWM2_1_IRQHandler +PWM2_2_IRQHandler +PWM2_3_IRQHandler +PWM2_FAULT_IRQHandler +PWM3_0_IRQHandler +PWM3_1_IRQHandler +PWM3_2_IRQHandler +PWM3_3_IRQHandler +PWM3_FAULT_IRQHandler +PWM4_0_IRQHandler +PWM4_1_IRQHandler +PWM4_2_IRQHandler +PWM4_3_IRQHandler +PWM4_FAULT_IRQHandler +Reserved168_IRQHandler +Reserved169_IRQHandler +Reserved170_IRQHandler +Reserved171_IRQHandler +Reserved172_IRQHandler +Reserved173_IRQHandler +SJC_ARM_DEBUG_IRQHandler +NMI_WAKEUP_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/mcuxpresso/startup_mimxrt1052.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/mcuxpresso/startup_mimxrt1052.c new file mode 100644 index 0000000000..c8290e5bb4 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/mcuxpresso/startup_mimxrt1052.c @@ -0,0 +1,1447 @@ +//***************************************************************************** +// MIMXRT1052 startup code for use with MCUXpresso IDE +// +// Version : 090518 +//***************************************************************************** +// +// The Clear BSD License +// Copyright 2016-2018 NXP +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted (subject to the limitations in the +// disclaimer below) provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +// GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +// OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +// IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void); +WEAK void DMA1_DMA17_IRQHandler(void); +WEAK void DMA2_DMA18_IRQHandler(void); +WEAK void DMA3_DMA19_IRQHandler(void); +WEAK void DMA4_DMA20_IRQHandler(void); +WEAK void DMA5_DMA21_IRQHandler(void); +WEAK void DMA6_DMA22_IRQHandler(void); +WEAK void DMA7_DMA23_IRQHandler(void); +WEAK void DMA8_DMA24_IRQHandler(void); +WEAK void DMA9_DMA25_IRQHandler(void); +WEAK void DMA10_DMA26_IRQHandler(void); +WEAK void DMA11_DMA27_IRQHandler(void); +WEAK void DMA12_DMA28_IRQHandler(void); +WEAK void DMA13_DMA29_IRQHandler(void); +WEAK void DMA14_DMA30_IRQHandler(void); +WEAK void DMA15_DMA31_IRQHandler(void); +WEAK void DMA_ERROR_IRQHandler(void); +WEAK void CTI0_ERROR_IRQHandler(void); +WEAK void CTI1_ERROR_IRQHandler(void); +WEAK void CORE_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void LPUART6_IRQHandler(void); +WEAK void LPUART7_IRQHandler(void); +WEAK void LPUART8_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void LPI2C4_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void LPSPI2_IRQHandler(void); +WEAK void LPSPI3_IRQHandler(void); +WEAK void LPSPI4_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void CAN2_IRQHandler(void); +WEAK void FLEXRAM_IRQHandler(void); +WEAK void KPP_IRQHandler(void); +WEAK void TSC_DIG_IRQHandler(void); +WEAK void GPR_IRQ_IRQHandler(void); +WEAK void LCDIF_IRQHandler(void); +WEAK void CSI_IRQHandler(void); +WEAK void PXP_IRQHandler(void); +WEAK void WDOG2_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void); +WEAK void SNVS_LP_WRAPPER_IRQHandler(void); +WEAK void CSU_IRQHandler(void); +WEAK void DCP_IRQHandler(void); +WEAK void DCP_VMI_IRQHandler(void); +WEAK void Reserved68_IRQHandler(void); +WEAK void TRNG_IRQHandler(void); +WEAK void SJC_IRQHandler(void); +WEAK void BEE_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void SAI2_IRQHandler(void); +WEAK void SAI3_RX_IRQHandler(void); +WEAK void SAI3_TX_IRQHandler(void); +WEAK void SPDIF_IRQHandler(void); +WEAK void ANATOP_EVENT0_IRQHandler(void); +WEAK void ANATOP_EVENT1_IRQHandler(void); +WEAK void ANATOP_TAMP_LOW_HIGH_IRQHandler(void); +WEAK void ANATOP_TEMP_PANIC_IRQHandler(void); +WEAK void USB_PHY1_IRQHandler(void); +WEAK void USB_PHY2_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void DCDC_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Reserved87_IRQHandler(void); +WEAK void GPIO1_INT0_IRQHandler(void); +WEAK void GPIO1_INT1_IRQHandler(void); +WEAK void GPIO1_INT2_IRQHandler(void); +WEAK void GPIO1_INT3_IRQHandler(void); +WEAK void GPIO1_INT4_IRQHandler(void); +WEAK void GPIO1_INT5_IRQHandler(void); +WEAK void GPIO1_INT6_IRQHandler(void); +WEAK void GPIO1_INT7_IRQHandler(void); +WEAK void GPIO1_Combined_0_15_IRQHandler(void); +WEAK void GPIO1_Combined_16_31_IRQHandler(void); +WEAK void GPIO2_Combined_0_15_IRQHandler(void); +WEAK void GPIO2_Combined_16_31_IRQHandler(void); +WEAK void GPIO3_Combined_0_15_IRQHandler(void); +WEAK void GPIO3_Combined_16_31_IRQHandler(void); +WEAK void GPIO4_Combined_0_15_IRQHandler(void); +WEAK void GPIO4_Combined_16_31_IRQHandler(void); +WEAK void GPIO5_Combined_0_15_IRQHandler(void); +WEAK void GPIO5_Combined_16_31_IRQHandler(void); +WEAK void FLEXIO1_IRQHandler(void); +WEAK void FLEXIO2_IRQHandler(void); +WEAK void WDOG1_IRQHandler(void); +WEAK void RTWDOG_IRQHandler(void); +WEAK void EWM_IRQHandler(void); +WEAK void CCM_1_IRQHandler(void); +WEAK void CCM_2_IRQHandler(void); +WEAK void GPC_IRQHandler(void); +WEAK void SRC_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void GPT1_IRQHandler(void); +WEAK void GPT2_IRQHandler(void); +WEAK void PWM1_0_IRQHandler(void); +WEAK void PWM1_1_IRQHandler(void); +WEAK void PWM1_2_IRQHandler(void); +WEAK void PWM1_3_IRQHandler(void); +WEAK void PWM1_FAULT_IRQHandler(void); +WEAK void Reserved123_IRQHandler(void); +WEAK void FLEXSPI_IRQHandler(void); +WEAK void SEMC_IRQHandler(void); +WEAK void USDHC1_IRQHandler(void); +WEAK void USDHC2_IRQHandler(void); +WEAK void USB_OTG2_IRQHandler(void); +WEAK void USB_OTG1_IRQHandler(void); +WEAK void ENET_IRQHandler(void); +WEAK void ENET_1588_Timer_IRQHandler(void); +WEAK void XBAR1_IRQ_0_1_IRQHandler(void); +WEAK void XBAR1_IRQ_2_3_IRQHandler(void); +WEAK void ADC_ETC_IRQ0_IRQHandler(void); +WEAK void ADC_ETC_IRQ1_IRQHandler(void); +WEAK void ADC_ETC_IRQ2_IRQHandler(void); +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void); +WEAK void PIT_IRQHandler(void); +WEAK void ACMP1_IRQHandler(void); +WEAK void ACMP2_IRQHandler(void); +WEAK void ACMP3_IRQHandler(void); +WEAK void ACMP4_IRQHandler(void); +WEAK void Reserved143_IRQHandler(void); +WEAK void Reserved144_IRQHandler(void); +WEAK void ENC1_IRQHandler(void); +WEAK void ENC2_IRQHandler(void); +WEAK void ENC3_IRQHandler(void); +WEAK void ENC4_IRQHandler(void); +WEAK void TMR1_IRQHandler(void); +WEAK void TMR2_IRQHandler(void); +WEAK void TMR3_IRQHandler(void); +WEAK void TMR4_IRQHandler(void); +WEAK void PWM2_0_IRQHandler(void); +WEAK void PWM2_1_IRQHandler(void); +WEAK void PWM2_2_IRQHandler(void); +WEAK void PWM2_3_IRQHandler(void); +WEAK void PWM2_FAULT_IRQHandler(void); +WEAK void PWM3_0_IRQHandler(void); +WEAK void PWM3_1_IRQHandler(void); +WEAK void PWM3_2_IRQHandler(void); +WEAK void PWM3_3_IRQHandler(void); +WEAK void PWM3_FAULT_IRQHandler(void); +WEAK void PWM4_0_IRQHandler(void); +WEAK void PWM4_1_IRQHandler(void); +WEAK void PWM4_2_IRQHandler(void); +WEAK void PWM4_3_IRQHandler(void); +WEAK void PWM4_FAULT_IRQHandler(void); +WEAK void Reserved168_IRQHandler(void); +WEAK void Reserved169_IRQHandler(void); +WEAK void Reserved170_IRQHandler(void); +WEAK void Reserved171_IRQHandler(void); +WEAK void Reserved172_IRQHandler(void); +WEAK void Reserved173_IRQHandler(void); +WEAK void SJC_ARM_DEBUG_IRQHandler(void); +WEAK void NMI_WAKEUP_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void DMA0_DMA16_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DMA17_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA2_DMA18_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA3_DMA19_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA4_DMA20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA5_DMA21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA6_DMA22_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA7_DMA23_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA8_DMA24_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA9_DMA25_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA10_DMA26_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA11_DMA27_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA12_DMA28_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA13_DMA29_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA14_DMA30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA15_DMA31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TSC_DIG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LCDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CSI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PXP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SJC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void BEE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_EVENT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_EVENT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_TAMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved87_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved115_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved123_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEMC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_1588_Timer_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_0_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved143_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved144_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved168_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved169_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved170_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved171_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved172_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved173_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SJC_ARM_DEBUG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void NMI_WAKEUP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM7 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + 0, // Reserved + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - MIMXRT1052 + DMA0_DMA16_IRQHandler, // 16 : DMA channel 0/16 transfer complete + DMA1_DMA17_IRQHandler, // 17 : DMA channel 1/17 transfer complete + DMA2_DMA18_IRQHandler, // 18 : DMA channel 2/18 transfer complete + DMA3_DMA19_IRQHandler, // 19 : DMA channel 3/19 transfer complete + DMA4_DMA20_IRQHandler, // 20 : DMA channel 4/20 transfer complete + DMA5_DMA21_IRQHandler, // 21 : DMA channel 5/21 transfer complete + DMA6_DMA22_IRQHandler, // 22 : DMA channel 6/22 transfer complete + DMA7_DMA23_IRQHandler, // 23 : DMA channel 7/23 transfer complete + DMA8_DMA24_IRQHandler, // 24 : DMA channel 8/24 transfer complete + DMA9_DMA25_IRQHandler, // 25 : DMA channel 9/25 transfer complete + DMA10_DMA26_IRQHandler, // 26 : DMA channel 10/26 transfer complete + DMA11_DMA27_IRQHandler, // 27 : DMA channel 11/27 transfer complete + DMA12_DMA28_IRQHandler, // 28 : DMA channel 12/28 transfer complete + DMA13_DMA29_IRQHandler, // 29 : DMA channel 13/29 transfer complete + DMA14_DMA30_IRQHandler, // 30 : DMA channel 14/30 transfer complete + DMA15_DMA31_IRQHandler, // 31 : DMA channel 15/31 transfer complete + DMA_ERROR_IRQHandler, // 32 : DMA error interrupt channels 0-15 / 16-31 + CTI0_ERROR_IRQHandler, // 33 : CTI0_Error + CTI1_ERROR_IRQHandler, // 34 : CTI1_Error + CORE_IRQHandler, // 35 : CorePlatform exception IRQ + LPUART1_IRQHandler, // 36 : LPUART1 TX interrupt and RX interrupt + LPUART2_IRQHandler, // 37 : LPUART2 TX interrupt and RX interrupt + LPUART3_IRQHandler, // 38 : LPUART3 TX interrupt and RX interrupt + LPUART4_IRQHandler, // 39 : LPUART4 TX interrupt and RX interrupt + LPUART5_IRQHandler, // 40 : LPUART5 TX interrupt and RX interrupt + LPUART6_IRQHandler, // 41 : LPUART6 TX interrupt and RX interrupt + LPUART7_IRQHandler, // 42 : LPUART7 TX interrupt and RX interrupt + LPUART8_IRQHandler, // 43 : LPUART8 TX interrupt and RX interrupt + LPI2C1_IRQHandler, // 44 : LPI2C1 interrupt + LPI2C2_IRQHandler, // 45 : LPI2C2 interrupt + LPI2C3_IRQHandler, // 46 : LPI2C3 interrupt + LPI2C4_IRQHandler, // 47 : LPI2C4 interrupt + LPSPI1_IRQHandler, // 48 : LPSPI1 single interrupt vector for all sources + LPSPI2_IRQHandler, // 49 : LPSPI2 single interrupt vector for all sources + LPSPI3_IRQHandler, // 50 : LPSPI3 single interrupt vector for all sources + LPSPI4_IRQHandler, // 51 : LPSPI4 single interrupt vector for all sources + CAN1_IRQHandler, // 52 : CAN1 interrupt + CAN2_IRQHandler, // 53 : CAN2 interrupt + FLEXRAM_IRQHandler, // 54 : FlexRAM address out of range Or access hit IRQ + KPP_IRQHandler, // 55 : Keypad nterrupt + TSC_DIG_IRQHandler, // 56 : TSC interrupt + GPR_IRQ_IRQHandler, // 57 : GPR interrupt + LCDIF_IRQHandler, // 58 : LCDIF interrupt + CSI_IRQHandler, // 59 : CSI interrupt + PXP_IRQHandler, // 60 : PXP interrupt + WDOG2_IRQHandler, // 61 : WDOG2 interrupt + SNVS_HP_WRAPPER_IRQHandler, // 62 : SRTC Consolidated Interrupt. Non TZ + SNVS_HP_WRAPPER_TZ_IRQHandler, // 63 : SRTC Security Interrupt. TZ + SNVS_LP_WRAPPER_IRQHandler, // 64 : ON-OFF button press shorter than 5 secs (pulse event) + CSU_IRQHandler, // 65 : CSU interrupt + DCP_IRQHandler, // 66 : DCP_IRQ interrupt + DCP_VMI_IRQHandler, // 67 : DCP_VMI_IRQ interrupt + Reserved68_IRQHandler, // 68 : Reserved interrupt + TRNG_IRQHandler, // 69 : TRNG interrupt + SJC_IRQHandler, // 70 : SJC interrupt + BEE_IRQHandler, // 71 : BEE interrupt + SAI1_IRQHandler, // 72 : SAI1 interrupt + SAI2_IRQHandler, // 73 : SAI1 interrupt + SAI3_RX_IRQHandler, // 74 : SAI3 interrupt + SAI3_TX_IRQHandler, // 75 : SAI3 interrupt + SPDIF_IRQHandler, // 76 : SPDIF interrupt + ANATOP_EVENT0_IRQHandler, // 77 : ANATOP interrupt + ANATOP_EVENT1_IRQHandler, // 78 : ANATOP interrupt + ANATOP_TAMP_LOW_HIGH_IRQHandler, // 79 : ANATOP interrupt + ANATOP_TEMP_PANIC_IRQHandler, // 80 : ANATOP interrupt + USB_PHY1_IRQHandler, // 81 : USBPHY (UTMI0), Interrupt + USB_PHY2_IRQHandler, // 82 : USBPHY (UTMI0), Interrupt + ADC1_IRQHandler, // 83 : ADC1 interrupt + ADC2_IRQHandler, // 84 : ADC2 interrupt + DCDC_IRQHandler, // 85 : DCDC interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Reserved87_IRQHandler, // 87 : Reserved interrupt + GPIO1_INT0_IRQHandler, // 88 : Active HIGH Interrupt from INT0 from GPIO + GPIO1_INT1_IRQHandler, // 89 : Active HIGH Interrupt from INT1 from GPIO + GPIO1_INT2_IRQHandler, // 90 : Active HIGH Interrupt from INT2 from GPIO + GPIO1_INT3_IRQHandler, // 91 : Active HIGH Interrupt from INT3 from GPIO + GPIO1_INT4_IRQHandler, // 92 : Active HIGH Interrupt from INT4 from GPIO + GPIO1_INT5_IRQHandler, // 93 : Active HIGH Interrupt from INT5 from GPIO + GPIO1_INT6_IRQHandler, // 94 : Active HIGH Interrupt from INT6 from GPIO + GPIO1_INT7_IRQHandler, // 95 : Active HIGH Interrupt from INT7 from GPIO + GPIO1_Combined_0_15_IRQHandler, // 96 : Combined interrupt indication for GPIO1 signal 0 throughout 15 + GPIO1_Combined_16_31_IRQHandler, // 97 : Combined interrupt indication for GPIO1 signal 16 throughout 31 + GPIO2_Combined_0_15_IRQHandler, // 98 : Combined interrupt indication for GPIO2 signal 0 throughout 15 + GPIO2_Combined_16_31_IRQHandler, // 99 : Combined interrupt indication for GPIO2 signal 16 throughout 31 + GPIO3_Combined_0_15_IRQHandler, // 100: Combined interrupt indication for GPIO3 signal 0 throughout 15 + GPIO3_Combined_16_31_IRQHandler, // 101: Combined interrupt indication for GPIO3 signal 16 throughout 31 + GPIO4_Combined_0_15_IRQHandler, // 102: Combined interrupt indication for GPIO4 signal 0 throughout 15 + GPIO4_Combined_16_31_IRQHandler, // 103: Combined interrupt indication for GPIO4 signal 16 throughout 31 + GPIO5_Combined_0_15_IRQHandler, // 104: Combined interrupt indication for GPIO5 signal 0 throughout 15 + GPIO5_Combined_16_31_IRQHandler, // 105: Combined interrupt indication for GPIO5 signal 16 throughout 31 + FLEXIO1_IRQHandler, // 106: FLEXIO1 interrupt + FLEXIO2_IRQHandler, // 107: FLEXIO2 interrupt + WDOG1_IRQHandler, // 108: WDOG1 interrupt + RTWDOG_IRQHandler, // 109: RTWDOG interrupt + EWM_IRQHandler, // 110: EWM interrupt + CCM_1_IRQHandler, // 111: CCM IRQ1 interrupt + CCM_2_IRQHandler, // 112: CCM IRQ2 interrupt + GPC_IRQHandler, // 113: GPC interrupt + SRC_IRQHandler, // 114: SRC interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + GPT1_IRQHandler, // 116: GPT1 interrupt + GPT2_IRQHandler, // 117: GPT2 interrupt + PWM1_0_IRQHandler, // 118: PWM1 capture 0, compare 0, or reload 0 interrupt + PWM1_1_IRQHandler, // 119: PWM1 capture 1, compare 1, or reload 0 interrupt + PWM1_2_IRQHandler, // 120: PWM1 capture 2, compare 2, or reload 0 interrupt + PWM1_3_IRQHandler, // 121: PWM1 capture 3, compare 3, or reload 0 interrupt + PWM1_FAULT_IRQHandler, // 122: PWM1 fault or reload error interrupt + Reserved123_IRQHandler, // 123: Reserved interrupt + FLEXSPI_IRQHandler, // 124: FlexSPI0 interrupt + SEMC_IRQHandler, // 125: Reserved interrupt + USDHC1_IRQHandler, // 126: USDHC1 interrupt + USDHC2_IRQHandler, // 127: USDHC2 interrupt + USB_OTG2_IRQHandler, // 128: USBO2 USB OTG2 + USB_OTG1_IRQHandler, // 129: USBO2 USB OTG1 + ENET_IRQHandler, // 130: ENET interrupt + ENET_1588_Timer_IRQHandler, // 131: ENET_1588_Timer interrupt + XBAR1_IRQ_0_1_IRQHandler, // 132: XBAR1 interrupt + XBAR1_IRQ_2_3_IRQHandler, // 133: XBAR1 interrupt + ADC_ETC_IRQ0_IRQHandler, // 134: ADCETC IRQ0 interrupt + ADC_ETC_IRQ1_IRQHandler, // 135: ADCETC IRQ1 interrupt + ADC_ETC_IRQ2_IRQHandler, // 136: ADCETC IRQ2 interrupt + ADC_ETC_ERROR_IRQ_IRQHandler, // 137: ADCETC Error IRQ interrupt + PIT_IRQHandler, // 138: PIT interrupt + ACMP1_IRQHandler, // 139: ACMP interrupt + ACMP2_IRQHandler, // 140: ACMP interrupt + ACMP3_IRQHandler, // 141: ACMP interrupt + ACMP4_IRQHandler, // 142: ACMP interrupt + Reserved143_IRQHandler, // 143: Reserved interrupt + Reserved144_IRQHandler, // 144: Reserved interrupt + ENC1_IRQHandler, // 145: ENC1 interrupt + ENC2_IRQHandler, // 146: ENC2 interrupt + ENC3_IRQHandler, // 147: ENC3 interrupt + ENC4_IRQHandler, // 148: ENC4 interrupt + TMR1_IRQHandler, // 149: TMR1 interrupt + TMR2_IRQHandler, // 150: TMR2 interrupt + TMR3_IRQHandler, // 151: TMR3 interrupt + TMR4_IRQHandler, // 152: TMR4 interrupt + PWM2_0_IRQHandler, // 153: PWM2 capture 0, compare 0, or reload 0 interrupt + PWM2_1_IRQHandler, // 154: PWM2 capture 1, compare 1, or reload 0 interrupt + PWM2_2_IRQHandler, // 155: PWM2 capture 2, compare 2, or reload 0 interrupt + PWM2_3_IRQHandler, // 156: PWM2 capture 3, compare 3, or reload 0 interrupt + PWM2_FAULT_IRQHandler, // 157: PWM2 fault or reload error interrupt + PWM3_0_IRQHandler, // 158: PWM3 capture 0, compare 0, or reload 0 interrupt + PWM3_1_IRQHandler, // 159: PWM3 capture 1, compare 1, or reload 0 interrupt + PWM3_2_IRQHandler, // 160: PWM3 capture 2, compare 2, or reload 0 interrupt + PWM3_3_IRQHandler, // 161: PWM3 capture 3, compare 3, or reload 0 interrupt + PWM3_FAULT_IRQHandler, // 162: PWM3 fault or reload error interrupt + PWM4_0_IRQHandler, // 163: PWM4 capture 0, compare 0, or reload 0 interrupt + PWM4_1_IRQHandler, // 164: PWM4 capture 1, compare 1, or reload 0 interrupt + PWM4_2_IRQHandler, // 165: PWM4 capture 2, compare 2, or reload 0 interrupt + PWM4_3_IRQHandler, // 166: PWM4 capture 3, compare 3, or reload 0 interrupt + PWM4_FAULT_IRQHandler, // 167: PWM4 fault or reload error interrupt + Reserved168_IRQHandler, // 168: Reserved interrupt + Reserved169_IRQHandler, // 169: Reserved interrupt + Reserved170_IRQHandler, // 170: Reserved interrupt + Reserved171_IRQHandler, // 171: Reserved interrupt + Reserved172_IRQHandler, // 172: Reserved interrupt + Reserved173_IRQHandler, // 173: Reserved interrupt + SJC_ARM_DEBUG_IRQHandler, // 174: SJC ARM debug interrupt + NMI_WAKEUP_IRQHandler, // 175: NMI wake up +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); +#else + // Disable Watchdog + volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000; + *WDOG1_WCR = *WDOG1_WCR & ~(1 << 2); + volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000; + *WDOG2_WCR = *WDOG2_WCR & ~(1 << 2); + // Write watchdog update key to unlock + *((volatile unsigned int *)0x400BC004) = 0xD928C520; + // Set timeout value + *((volatile unsigned int *)0x400BC008) = 0xFFFF; + // Now disable watchdog via control register + volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000; + *RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) + +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void) +{ DMA0_DMA16_DriverIRQHandler(); +} + +WEAK void DMA1_DMA17_IRQHandler(void) +{ DMA1_DMA17_DriverIRQHandler(); +} + +WEAK void DMA2_DMA18_IRQHandler(void) +{ DMA2_DMA18_DriverIRQHandler(); +} + +WEAK void DMA3_DMA19_IRQHandler(void) +{ DMA3_DMA19_DriverIRQHandler(); +} + +WEAK void DMA4_DMA20_IRQHandler(void) +{ DMA4_DMA20_DriverIRQHandler(); +} + +WEAK void DMA5_DMA21_IRQHandler(void) +{ DMA5_DMA21_DriverIRQHandler(); +} + +WEAK void DMA6_DMA22_IRQHandler(void) +{ DMA6_DMA22_DriverIRQHandler(); +} + +WEAK void DMA7_DMA23_IRQHandler(void) +{ DMA7_DMA23_DriverIRQHandler(); +} + +WEAK void DMA8_DMA24_IRQHandler(void) +{ DMA8_DMA24_DriverIRQHandler(); +} + +WEAK void DMA9_DMA25_IRQHandler(void) +{ DMA9_DMA25_DriverIRQHandler(); +} + +WEAK void DMA10_DMA26_IRQHandler(void) +{ DMA10_DMA26_DriverIRQHandler(); +} + +WEAK void DMA11_DMA27_IRQHandler(void) +{ DMA11_DMA27_DriverIRQHandler(); +} + +WEAK void DMA12_DMA28_IRQHandler(void) +{ DMA12_DMA28_DriverIRQHandler(); +} + +WEAK void DMA13_DMA29_IRQHandler(void) +{ DMA13_DMA29_DriverIRQHandler(); +} + +WEAK void DMA14_DMA30_IRQHandler(void) +{ DMA14_DMA30_DriverIRQHandler(); +} + +WEAK void DMA15_DMA31_IRQHandler(void) +{ DMA15_DMA31_DriverIRQHandler(); +} + +WEAK void DMA_ERROR_IRQHandler(void) +{ DMA_ERROR_DriverIRQHandler(); +} + +WEAK void CTI0_ERROR_IRQHandler(void) +{ CTI0_ERROR_DriverIRQHandler(); +} + +WEAK void CTI1_ERROR_IRQHandler(void) +{ CTI1_ERROR_DriverIRQHandler(); +} + +WEAK void CORE_IRQHandler(void) +{ CORE_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ LPUART4_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ LPUART5_DriverIRQHandler(); +} + +WEAK void LPUART6_IRQHandler(void) +{ LPUART6_DriverIRQHandler(); +} + +WEAK void LPUART7_IRQHandler(void) +{ LPUART7_DriverIRQHandler(); +} + +WEAK void LPUART8_IRQHandler(void) +{ LPUART8_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ LPI2C1_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ LPI2C3_DriverIRQHandler(); +} + +WEAK void LPI2C4_IRQHandler(void) +{ LPI2C4_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ LPSPI1_DriverIRQHandler(); +} + +WEAK void LPSPI2_IRQHandler(void) +{ LPSPI2_DriverIRQHandler(); +} + +WEAK void LPSPI3_IRQHandler(void) +{ LPSPI3_DriverIRQHandler(); +} + +WEAK void LPSPI4_IRQHandler(void) +{ LPSPI4_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ CAN1_DriverIRQHandler(); +} + +WEAK void CAN2_IRQHandler(void) +{ CAN2_DriverIRQHandler(); +} + +WEAK void FLEXRAM_IRQHandler(void) +{ FLEXRAM_DriverIRQHandler(); +} + +WEAK void KPP_IRQHandler(void) +{ KPP_DriverIRQHandler(); +} + +WEAK void TSC_DIG_IRQHandler(void) +{ TSC_DIG_DriverIRQHandler(); +} + +WEAK void GPR_IRQ_IRQHandler(void) +{ GPR_IRQ_DriverIRQHandler(); +} + +WEAK void LCDIF_IRQHandler(void) +{ LCDIF_DriverIRQHandler(); +} + +WEAK void CSI_IRQHandler(void) +{ CSI_DriverIRQHandler(); +} + +WEAK void PXP_IRQHandler(void) +{ PXP_DriverIRQHandler(); +} + +WEAK void WDOG2_IRQHandler(void) +{ WDOG2_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_IRQHandler(void) +{ SNVS_HP_WRAPPER_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void) +{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler(); +} + +WEAK void SNVS_LP_WRAPPER_IRQHandler(void) +{ SNVS_LP_WRAPPER_DriverIRQHandler(); +} + +WEAK void CSU_IRQHandler(void) +{ CSU_DriverIRQHandler(); +} + +WEAK void DCP_IRQHandler(void) +{ DCP_DriverIRQHandler(); +} + +WEAK void DCP_VMI_IRQHandler(void) +{ DCP_VMI_DriverIRQHandler(); +} + +WEAK void Reserved68_IRQHandler(void) +{ Reserved68_DriverIRQHandler(); +} + +WEAK void TRNG_IRQHandler(void) +{ TRNG_DriverIRQHandler(); +} + +WEAK void SJC_IRQHandler(void) +{ SJC_DriverIRQHandler(); +} + +WEAK void BEE_IRQHandler(void) +{ BEE_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void SAI2_IRQHandler(void) +{ SAI2_DriverIRQHandler(); +} + +WEAK void SAI3_RX_IRQHandler(void) +{ SAI3_RX_DriverIRQHandler(); +} + +WEAK void SAI3_TX_IRQHandler(void) +{ SAI3_TX_DriverIRQHandler(); +} + +WEAK void SPDIF_IRQHandler(void) +{ SPDIF_DriverIRQHandler(); +} + +WEAK void ANATOP_EVENT0_IRQHandler(void) +{ ANATOP_EVENT0_DriverIRQHandler(); +} + +WEAK void ANATOP_EVENT1_IRQHandler(void) +{ ANATOP_EVENT1_DriverIRQHandler(); +} + +WEAK void ANATOP_TAMP_LOW_HIGH_IRQHandler(void) +{ ANATOP_TAMP_LOW_HIGH_DriverIRQHandler(); +} + +WEAK void ANATOP_TEMP_PANIC_IRQHandler(void) +{ ANATOP_TEMP_PANIC_DriverIRQHandler(); +} + +WEAK void USB_PHY1_IRQHandler(void) +{ USB_PHY1_DriverIRQHandler(); +} + +WEAK void USB_PHY2_IRQHandler(void) +{ USB_PHY2_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ ADC2_DriverIRQHandler(); +} + +WEAK void DCDC_IRQHandler(void) +{ DCDC_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Reserved87_IRQHandler(void) +{ Reserved87_DriverIRQHandler(); +} + +WEAK void GPIO1_INT0_IRQHandler(void) +{ GPIO1_INT0_DriverIRQHandler(); +} + +WEAK void GPIO1_INT1_IRQHandler(void) +{ GPIO1_INT1_DriverIRQHandler(); +} + +WEAK void GPIO1_INT2_IRQHandler(void) +{ GPIO1_INT2_DriverIRQHandler(); +} + +WEAK void GPIO1_INT3_IRQHandler(void) +{ GPIO1_INT3_DriverIRQHandler(); +} + +WEAK void GPIO1_INT4_IRQHandler(void) +{ GPIO1_INT4_DriverIRQHandler(); +} + +WEAK void GPIO1_INT5_IRQHandler(void) +{ GPIO1_INT5_DriverIRQHandler(); +} + +WEAK void GPIO1_INT6_IRQHandler(void) +{ GPIO1_INT6_DriverIRQHandler(); +} + +WEAK void GPIO1_INT7_IRQHandler(void) +{ GPIO1_INT7_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_0_15_IRQHandler(void) +{ GPIO1_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_16_31_IRQHandler(void) +{ GPIO1_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_0_15_IRQHandler(void) +{ GPIO2_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_16_31_IRQHandler(void) +{ GPIO2_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_0_15_IRQHandler(void) +{ GPIO3_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_16_31_IRQHandler(void) +{ GPIO3_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_0_15_IRQHandler(void) +{ GPIO4_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_16_31_IRQHandler(void) +{ GPIO4_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_0_15_IRQHandler(void) +{ GPIO5_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_16_31_IRQHandler(void) +{ GPIO5_Combined_16_31_DriverIRQHandler(); +} + +WEAK void FLEXIO1_IRQHandler(void) +{ FLEXIO1_DriverIRQHandler(); +} + +WEAK void FLEXIO2_IRQHandler(void) +{ FLEXIO2_DriverIRQHandler(); +} + +WEAK void WDOG1_IRQHandler(void) +{ WDOG1_DriverIRQHandler(); +} + +WEAK void RTWDOG_IRQHandler(void) +{ RTWDOG_DriverIRQHandler(); +} + +WEAK void EWM_IRQHandler(void) +{ EWM_DriverIRQHandler(); +} + +WEAK void CCM_1_IRQHandler(void) +{ CCM_1_DriverIRQHandler(); +} + +WEAK void CCM_2_IRQHandler(void) +{ CCM_2_DriverIRQHandler(); +} + +WEAK void GPC_IRQHandler(void) +{ GPC_DriverIRQHandler(); +} + +WEAK void SRC_IRQHandler(void) +{ SRC_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ Reserved115_DriverIRQHandler(); +} + +WEAK void GPT1_IRQHandler(void) +{ GPT1_DriverIRQHandler(); +} + +WEAK void GPT2_IRQHandler(void) +{ GPT2_DriverIRQHandler(); +} + +WEAK void PWM1_0_IRQHandler(void) +{ PWM1_0_DriverIRQHandler(); +} + +WEAK void PWM1_1_IRQHandler(void) +{ PWM1_1_DriverIRQHandler(); +} + +WEAK void PWM1_2_IRQHandler(void) +{ PWM1_2_DriverIRQHandler(); +} + +WEAK void PWM1_3_IRQHandler(void) +{ PWM1_3_DriverIRQHandler(); +} + +WEAK void PWM1_FAULT_IRQHandler(void) +{ PWM1_FAULT_DriverIRQHandler(); +} + +WEAK void Reserved123_IRQHandler(void) +{ Reserved123_DriverIRQHandler(); +} + +WEAK void FLEXSPI_IRQHandler(void) +{ FLEXSPI_DriverIRQHandler(); +} + +WEAK void SEMC_IRQHandler(void) +{ SEMC_DriverIRQHandler(); +} + +WEAK void USDHC1_IRQHandler(void) +{ USDHC1_DriverIRQHandler(); +} + +WEAK void USDHC2_IRQHandler(void) +{ USDHC2_DriverIRQHandler(); +} + +WEAK void USB_OTG2_IRQHandler(void) +{ USB_OTG2_DriverIRQHandler(); +} + +WEAK void USB_OTG1_IRQHandler(void) +{ USB_OTG1_DriverIRQHandler(); +} + +WEAK void ENET_IRQHandler(void) +{ ENET_DriverIRQHandler(); +} + +WEAK void ENET_1588_Timer_IRQHandler(void) +{ ENET_1588_Timer_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_0_1_IRQHandler(void) +{ XBAR1_IRQ_0_1_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_2_3_IRQHandler(void) +{ XBAR1_IRQ_2_3_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ0_IRQHandler(void) +{ ADC_ETC_IRQ0_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ1_IRQHandler(void) +{ ADC_ETC_IRQ1_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ2_IRQHandler(void) +{ ADC_ETC_IRQ2_DriverIRQHandler(); +} + +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void) +{ ADC_ETC_ERROR_IRQ_DriverIRQHandler(); +} + +WEAK void PIT_IRQHandler(void) +{ PIT_DriverIRQHandler(); +} + +WEAK void ACMP1_IRQHandler(void) +{ ACMP1_DriverIRQHandler(); +} + +WEAK void ACMP2_IRQHandler(void) +{ ACMP2_DriverIRQHandler(); +} + +WEAK void ACMP3_IRQHandler(void) +{ ACMP3_DriverIRQHandler(); +} + +WEAK void ACMP4_IRQHandler(void) +{ ACMP4_DriverIRQHandler(); +} + +WEAK void Reserved143_IRQHandler(void) +{ Reserved143_DriverIRQHandler(); +} + +WEAK void Reserved144_IRQHandler(void) +{ Reserved144_DriverIRQHandler(); +} + +WEAK void ENC1_IRQHandler(void) +{ ENC1_DriverIRQHandler(); +} + +WEAK void ENC2_IRQHandler(void) +{ ENC2_DriverIRQHandler(); +} + +WEAK void ENC3_IRQHandler(void) +{ ENC3_DriverIRQHandler(); +} + +WEAK void ENC4_IRQHandler(void) +{ ENC4_DriverIRQHandler(); +} + +WEAK void TMR1_IRQHandler(void) +{ TMR1_DriverIRQHandler(); +} + +WEAK void TMR2_IRQHandler(void) +{ TMR2_DriverIRQHandler(); +} + +WEAK void TMR3_IRQHandler(void) +{ TMR3_DriverIRQHandler(); +} + +WEAK void TMR4_IRQHandler(void) +{ TMR4_DriverIRQHandler(); +} + +WEAK void PWM2_0_IRQHandler(void) +{ PWM2_0_DriverIRQHandler(); +} + +WEAK void PWM2_1_IRQHandler(void) +{ PWM2_1_DriverIRQHandler(); +} + +WEAK void PWM2_2_IRQHandler(void) +{ PWM2_2_DriverIRQHandler(); +} + +WEAK void PWM2_3_IRQHandler(void) +{ PWM2_3_DriverIRQHandler(); +} + +WEAK void PWM2_FAULT_IRQHandler(void) +{ PWM2_FAULT_DriverIRQHandler(); +} + +WEAK void PWM3_0_IRQHandler(void) +{ PWM3_0_DriverIRQHandler(); +} + +WEAK void PWM3_1_IRQHandler(void) +{ PWM3_1_DriverIRQHandler(); +} + +WEAK void PWM3_2_IRQHandler(void) +{ PWM3_2_DriverIRQHandler(); +} + +WEAK void PWM3_3_IRQHandler(void) +{ PWM3_3_DriverIRQHandler(); +} + +WEAK void PWM3_FAULT_IRQHandler(void) +{ PWM3_FAULT_DriverIRQHandler(); +} + +WEAK void PWM4_0_IRQHandler(void) +{ PWM4_0_DriverIRQHandler(); +} + +WEAK void PWM4_1_IRQHandler(void) +{ PWM4_1_DriverIRQHandler(); +} + +WEAK void PWM4_2_IRQHandler(void) +{ PWM4_2_DriverIRQHandler(); +} + +WEAK void PWM4_3_IRQHandler(void) +{ PWM4_3_DriverIRQHandler(); +} + +WEAK void PWM4_FAULT_IRQHandler(void) +{ PWM4_FAULT_DriverIRQHandler(); +} + +WEAK void Reserved168_IRQHandler(void) +{ Reserved168_DriverIRQHandler(); +} + +WEAK void Reserved169_IRQHandler(void) +{ Reserved169_DriverIRQHandler(); +} + +WEAK void Reserved170_IRQHandler(void) +{ Reserved170_DriverIRQHandler(); +} + +WEAK void Reserved171_IRQHandler(void) +{ Reserved171_DriverIRQHandler(); +} + +WEAK void Reserved172_IRQHandler(void) +{ Reserved172_DriverIRQHandler(); +} + +WEAK void Reserved173_IRQHandler(void) +{ Reserved173_DriverIRQHandler(); +} + +WEAK void SJC_ARM_DEBUG_IRQHandler(void) +{ SJC_ARM_DEBUG_DriverIRQHandler(); +} + +WEAK void NMI_WAKEUP_IRQHandler(void) +{ NMI_WAKEUP_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/mcuxpresso/startup_mimxrt1052.cpp b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/mcuxpresso/startup_mimxrt1052.cpp new file mode 100644 index 0000000000..c8290e5bb4 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/mcuxpresso/startup_mimxrt1052.cpp @@ -0,0 +1,1447 @@ +//***************************************************************************** +// MIMXRT1052 startup code for use with MCUXpresso IDE +// +// Version : 090518 +//***************************************************************************** +// +// The Clear BSD License +// Copyright 2016-2018 NXP +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted (subject to the limitations in the +// disclaimer below) provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +// GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +// OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +// IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void); +WEAK void DMA1_DMA17_IRQHandler(void); +WEAK void DMA2_DMA18_IRQHandler(void); +WEAK void DMA3_DMA19_IRQHandler(void); +WEAK void DMA4_DMA20_IRQHandler(void); +WEAK void DMA5_DMA21_IRQHandler(void); +WEAK void DMA6_DMA22_IRQHandler(void); +WEAK void DMA7_DMA23_IRQHandler(void); +WEAK void DMA8_DMA24_IRQHandler(void); +WEAK void DMA9_DMA25_IRQHandler(void); +WEAK void DMA10_DMA26_IRQHandler(void); +WEAK void DMA11_DMA27_IRQHandler(void); +WEAK void DMA12_DMA28_IRQHandler(void); +WEAK void DMA13_DMA29_IRQHandler(void); +WEAK void DMA14_DMA30_IRQHandler(void); +WEAK void DMA15_DMA31_IRQHandler(void); +WEAK void DMA_ERROR_IRQHandler(void); +WEAK void CTI0_ERROR_IRQHandler(void); +WEAK void CTI1_ERROR_IRQHandler(void); +WEAK void CORE_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void LPUART6_IRQHandler(void); +WEAK void LPUART7_IRQHandler(void); +WEAK void LPUART8_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void LPI2C4_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void LPSPI2_IRQHandler(void); +WEAK void LPSPI3_IRQHandler(void); +WEAK void LPSPI4_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void CAN2_IRQHandler(void); +WEAK void FLEXRAM_IRQHandler(void); +WEAK void KPP_IRQHandler(void); +WEAK void TSC_DIG_IRQHandler(void); +WEAK void GPR_IRQ_IRQHandler(void); +WEAK void LCDIF_IRQHandler(void); +WEAK void CSI_IRQHandler(void); +WEAK void PXP_IRQHandler(void); +WEAK void WDOG2_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void); +WEAK void SNVS_LP_WRAPPER_IRQHandler(void); +WEAK void CSU_IRQHandler(void); +WEAK void DCP_IRQHandler(void); +WEAK void DCP_VMI_IRQHandler(void); +WEAK void Reserved68_IRQHandler(void); +WEAK void TRNG_IRQHandler(void); +WEAK void SJC_IRQHandler(void); +WEAK void BEE_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void SAI2_IRQHandler(void); +WEAK void SAI3_RX_IRQHandler(void); +WEAK void SAI3_TX_IRQHandler(void); +WEAK void SPDIF_IRQHandler(void); +WEAK void ANATOP_EVENT0_IRQHandler(void); +WEAK void ANATOP_EVENT1_IRQHandler(void); +WEAK void ANATOP_TAMP_LOW_HIGH_IRQHandler(void); +WEAK void ANATOP_TEMP_PANIC_IRQHandler(void); +WEAK void USB_PHY1_IRQHandler(void); +WEAK void USB_PHY2_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void DCDC_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Reserved87_IRQHandler(void); +WEAK void GPIO1_INT0_IRQHandler(void); +WEAK void GPIO1_INT1_IRQHandler(void); +WEAK void GPIO1_INT2_IRQHandler(void); +WEAK void GPIO1_INT3_IRQHandler(void); +WEAK void GPIO1_INT4_IRQHandler(void); +WEAK void GPIO1_INT5_IRQHandler(void); +WEAK void GPIO1_INT6_IRQHandler(void); +WEAK void GPIO1_INT7_IRQHandler(void); +WEAK void GPIO1_Combined_0_15_IRQHandler(void); +WEAK void GPIO1_Combined_16_31_IRQHandler(void); +WEAK void GPIO2_Combined_0_15_IRQHandler(void); +WEAK void GPIO2_Combined_16_31_IRQHandler(void); +WEAK void GPIO3_Combined_0_15_IRQHandler(void); +WEAK void GPIO3_Combined_16_31_IRQHandler(void); +WEAK void GPIO4_Combined_0_15_IRQHandler(void); +WEAK void GPIO4_Combined_16_31_IRQHandler(void); +WEAK void GPIO5_Combined_0_15_IRQHandler(void); +WEAK void GPIO5_Combined_16_31_IRQHandler(void); +WEAK void FLEXIO1_IRQHandler(void); +WEAK void FLEXIO2_IRQHandler(void); +WEAK void WDOG1_IRQHandler(void); +WEAK void RTWDOG_IRQHandler(void); +WEAK void EWM_IRQHandler(void); +WEAK void CCM_1_IRQHandler(void); +WEAK void CCM_2_IRQHandler(void); +WEAK void GPC_IRQHandler(void); +WEAK void SRC_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void GPT1_IRQHandler(void); +WEAK void GPT2_IRQHandler(void); +WEAK void PWM1_0_IRQHandler(void); +WEAK void PWM1_1_IRQHandler(void); +WEAK void PWM1_2_IRQHandler(void); +WEAK void PWM1_3_IRQHandler(void); +WEAK void PWM1_FAULT_IRQHandler(void); +WEAK void Reserved123_IRQHandler(void); +WEAK void FLEXSPI_IRQHandler(void); +WEAK void SEMC_IRQHandler(void); +WEAK void USDHC1_IRQHandler(void); +WEAK void USDHC2_IRQHandler(void); +WEAK void USB_OTG2_IRQHandler(void); +WEAK void USB_OTG1_IRQHandler(void); +WEAK void ENET_IRQHandler(void); +WEAK void ENET_1588_Timer_IRQHandler(void); +WEAK void XBAR1_IRQ_0_1_IRQHandler(void); +WEAK void XBAR1_IRQ_2_3_IRQHandler(void); +WEAK void ADC_ETC_IRQ0_IRQHandler(void); +WEAK void ADC_ETC_IRQ1_IRQHandler(void); +WEAK void ADC_ETC_IRQ2_IRQHandler(void); +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void); +WEAK void PIT_IRQHandler(void); +WEAK void ACMP1_IRQHandler(void); +WEAK void ACMP2_IRQHandler(void); +WEAK void ACMP3_IRQHandler(void); +WEAK void ACMP4_IRQHandler(void); +WEAK void Reserved143_IRQHandler(void); +WEAK void Reserved144_IRQHandler(void); +WEAK void ENC1_IRQHandler(void); +WEAK void ENC2_IRQHandler(void); +WEAK void ENC3_IRQHandler(void); +WEAK void ENC4_IRQHandler(void); +WEAK void TMR1_IRQHandler(void); +WEAK void TMR2_IRQHandler(void); +WEAK void TMR3_IRQHandler(void); +WEAK void TMR4_IRQHandler(void); +WEAK void PWM2_0_IRQHandler(void); +WEAK void PWM2_1_IRQHandler(void); +WEAK void PWM2_2_IRQHandler(void); +WEAK void PWM2_3_IRQHandler(void); +WEAK void PWM2_FAULT_IRQHandler(void); +WEAK void PWM3_0_IRQHandler(void); +WEAK void PWM3_1_IRQHandler(void); +WEAK void PWM3_2_IRQHandler(void); +WEAK void PWM3_3_IRQHandler(void); +WEAK void PWM3_FAULT_IRQHandler(void); +WEAK void PWM4_0_IRQHandler(void); +WEAK void PWM4_1_IRQHandler(void); +WEAK void PWM4_2_IRQHandler(void); +WEAK void PWM4_3_IRQHandler(void); +WEAK void PWM4_FAULT_IRQHandler(void); +WEAK void Reserved168_IRQHandler(void); +WEAK void Reserved169_IRQHandler(void); +WEAK void Reserved170_IRQHandler(void); +WEAK void Reserved171_IRQHandler(void); +WEAK void Reserved172_IRQHandler(void); +WEAK void Reserved173_IRQHandler(void); +WEAK void SJC_ARM_DEBUG_IRQHandler(void); +WEAK void NMI_WAKEUP_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void DMA0_DMA16_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DMA17_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA2_DMA18_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA3_DMA19_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA4_DMA20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA5_DMA21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA6_DMA22_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA7_DMA23_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA8_DMA24_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA9_DMA25_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA10_DMA26_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA11_DMA27_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA12_DMA28_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA13_DMA29_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA14_DMA30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA15_DMA31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TSC_DIG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LCDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CSI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PXP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SJC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void BEE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_EVENT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_EVENT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_TAMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ANATOP_TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved87_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved115_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved123_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEMC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_1588_Timer_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_0_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved143_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved144_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved168_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved169_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved170_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved171_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved172_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved173_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SJC_ARM_DEBUG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void NMI_WAKEUP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM7 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + 0, // Reserved + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - MIMXRT1052 + DMA0_DMA16_IRQHandler, // 16 : DMA channel 0/16 transfer complete + DMA1_DMA17_IRQHandler, // 17 : DMA channel 1/17 transfer complete + DMA2_DMA18_IRQHandler, // 18 : DMA channel 2/18 transfer complete + DMA3_DMA19_IRQHandler, // 19 : DMA channel 3/19 transfer complete + DMA4_DMA20_IRQHandler, // 20 : DMA channel 4/20 transfer complete + DMA5_DMA21_IRQHandler, // 21 : DMA channel 5/21 transfer complete + DMA6_DMA22_IRQHandler, // 22 : DMA channel 6/22 transfer complete + DMA7_DMA23_IRQHandler, // 23 : DMA channel 7/23 transfer complete + DMA8_DMA24_IRQHandler, // 24 : DMA channel 8/24 transfer complete + DMA9_DMA25_IRQHandler, // 25 : DMA channel 9/25 transfer complete + DMA10_DMA26_IRQHandler, // 26 : DMA channel 10/26 transfer complete + DMA11_DMA27_IRQHandler, // 27 : DMA channel 11/27 transfer complete + DMA12_DMA28_IRQHandler, // 28 : DMA channel 12/28 transfer complete + DMA13_DMA29_IRQHandler, // 29 : DMA channel 13/29 transfer complete + DMA14_DMA30_IRQHandler, // 30 : DMA channel 14/30 transfer complete + DMA15_DMA31_IRQHandler, // 31 : DMA channel 15/31 transfer complete + DMA_ERROR_IRQHandler, // 32 : DMA error interrupt channels 0-15 / 16-31 + CTI0_ERROR_IRQHandler, // 33 : CTI0_Error + CTI1_ERROR_IRQHandler, // 34 : CTI1_Error + CORE_IRQHandler, // 35 : CorePlatform exception IRQ + LPUART1_IRQHandler, // 36 : LPUART1 TX interrupt and RX interrupt + LPUART2_IRQHandler, // 37 : LPUART2 TX interrupt and RX interrupt + LPUART3_IRQHandler, // 38 : LPUART3 TX interrupt and RX interrupt + LPUART4_IRQHandler, // 39 : LPUART4 TX interrupt and RX interrupt + LPUART5_IRQHandler, // 40 : LPUART5 TX interrupt and RX interrupt + LPUART6_IRQHandler, // 41 : LPUART6 TX interrupt and RX interrupt + LPUART7_IRQHandler, // 42 : LPUART7 TX interrupt and RX interrupt + LPUART8_IRQHandler, // 43 : LPUART8 TX interrupt and RX interrupt + LPI2C1_IRQHandler, // 44 : LPI2C1 interrupt + LPI2C2_IRQHandler, // 45 : LPI2C2 interrupt + LPI2C3_IRQHandler, // 46 : LPI2C3 interrupt + LPI2C4_IRQHandler, // 47 : LPI2C4 interrupt + LPSPI1_IRQHandler, // 48 : LPSPI1 single interrupt vector for all sources + LPSPI2_IRQHandler, // 49 : LPSPI2 single interrupt vector for all sources + LPSPI3_IRQHandler, // 50 : LPSPI3 single interrupt vector for all sources + LPSPI4_IRQHandler, // 51 : LPSPI4 single interrupt vector for all sources + CAN1_IRQHandler, // 52 : CAN1 interrupt + CAN2_IRQHandler, // 53 : CAN2 interrupt + FLEXRAM_IRQHandler, // 54 : FlexRAM address out of range Or access hit IRQ + KPP_IRQHandler, // 55 : Keypad nterrupt + TSC_DIG_IRQHandler, // 56 : TSC interrupt + GPR_IRQ_IRQHandler, // 57 : GPR interrupt + LCDIF_IRQHandler, // 58 : LCDIF interrupt + CSI_IRQHandler, // 59 : CSI interrupt + PXP_IRQHandler, // 60 : PXP interrupt + WDOG2_IRQHandler, // 61 : WDOG2 interrupt + SNVS_HP_WRAPPER_IRQHandler, // 62 : SRTC Consolidated Interrupt. Non TZ + SNVS_HP_WRAPPER_TZ_IRQHandler, // 63 : SRTC Security Interrupt. TZ + SNVS_LP_WRAPPER_IRQHandler, // 64 : ON-OFF button press shorter than 5 secs (pulse event) + CSU_IRQHandler, // 65 : CSU interrupt + DCP_IRQHandler, // 66 : DCP_IRQ interrupt + DCP_VMI_IRQHandler, // 67 : DCP_VMI_IRQ interrupt + Reserved68_IRQHandler, // 68 : Reserved interrupt + TRNG_IRQHandler, // 69 : TRNG interrupt + SJC_IRQHandler, // 70 : SJC interrupt + BEE_IRQHandler, // 71 : BEE interrupt + SAI1_IRQHandler, // 72 : SAI1 interrupt + SAI2_IRQHandler, // 73 : SAI1 interrupt + SAI3_RX_IRQHandler, // 74 : SAI3 interrupt + SAI3_TX_IRQHandler, // 75 : SAI3 interrupt + SPDIF_IRQHandler, // 76 : SPDIF interrupt + ANATOP_EVENT0_IRQHandler, // 77 : ANATOP interrupt + ANATOP_EVENT1_IRQHandler, // 78 : ANATOP interrupt + ANATOP_TAMP_LOW_HIGH_IRQHandler, // 79 : ANATOP interrupt + ANATOP_TEMP_PANIC_IRQHandler, // 80 : ANATOP interrupt + USB_PHY1_IRQHandler, // 81 : USBPHY (UTMI0), Interrupt + USB_PHY2_IRQHandler, // 82 : USBPHY (UTMI0), Interrupt + ADC1_IRQHandler, // 83 : ADC1 interrupt + ADC2_IRQHandler, // 84 : ADC2 interrupt + DCDC_IRQHandler, // 85 : DCDC interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Reserved87_IRQHandler, // 87 : Reserved interrupt + GPIO1_INT0_IRQHandler, // 88 : Active HIGH Interrupt from INT0 from GPIO + GPIO1_INT1_IRQHandler, // 89 : Active HIGH Interrupt from INT1 from GPIO + GPIO1_INT2_IRQHandler, // 90 : Active HIGH Interrupt from INT2 from GPIO + GPIO1_INT3_IRQHandler, // 91 : Active HIGH Interrupt from INT3 from GPIO + GPIO1_INT4_IRQHandler, // 92 : Active HIGH Interrupt from INT4 from GPIO + GPIO1_INT5_IRQHandler, // 93 : Active HIGH Interrupt from INT5 from GPIO + GPIO1_INT6_IRQHandler, // 94 : Active HIGH Interrupt from INT6 from GPIO + GPIO1_INT7_IRQHandler, // 95 : Active HIGH Interrupt from INT7 from GPIO + GPIO1_Combined_0_15_IRQHandler, // 96 : Combined interrupt indication for GPIO1 signal 0 throughout 15 + GPIO1_Combined_16_31_IRQHandler, // 97 : Combined interrupt indication for GPIO1 signal 16 throughout 31 + GPIO2_Combined_0_15_IRQHandler, // 98 : Combined interrupt indication for GPIO2 signal 0 throughout 15 + GPIO2_Combined_16_31_IRQHandler, // 99 : Combined interrupt indication for GPIO2 signal 16 throughout 31 + GPIO3_Combined_0_15_IRQHandler, // 100: Combined interrupt indication for GPIO3 signal 0 throughout 15 + GPIO3_Combined_16_31_IRQHandler, // 101: Combined interrupt indication for GPIO3 signal 16 throughout 31 + GPIO4_Combined_0_15_IRQHandler, // 102: Combined interrupt indication for GPIO4 signal 0 throughout 15 + GPIO4_Combined_16_31_IRQHandler, // 103: Combined interrupt indication for GPIO4 signal 16 throughout 31 + GPIO5_Combined_0_15_IRQHandler, // 104: Combined interrupt indication for GPIO5 signal 0 throughout 15 + GPIO5_Combined_16_31_IRQHandler, // 105: Combined interrupt indication for GPIO5 signal 16 throughout 31 + FLEXIO1_IRQHandler, // 106: FLEXIO1 interrupt + FLEXIO2_IRQHandler, // 107: FLEXIO2 interrupt + WDOG1_IRQHandler, // 108: WDOG1 interrupt + RTWDOG_IRQHandler, // 109: RTWDOG interrupt + EWM_IRQHandler, // 110: EWM interrupt + CCM_1_IRQHandler, // 111: CCM IRQ1 interrupt + CCM_2_IRQHandler, // 112: CCM IRQ2 interrupt + GPC_IRQHandler, // 113: GPC interrupt + SRC_IRQHandler, // 114: SRC interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + GPT1_IRQHandler, // 116: GPT1 interrupt + GPT2_IRQHandler, // 117: GPT2 interrupt + PWM1_0_IRQHandler, // 118: PWM1 capture 0, compare 0, or reload 0 interrupt + PWM1_1_IRQHandler, // 119: PWM1 capture 1, compare 1, or reload 0 interrupt + PWM1_2_IRQHandler, // 120: PWM1 capture 2, compare 2, or reload 0 interrupt + PWM1_3_IRQHandler, // 121: PWM1 capture 3, compare 3, or reload 0 interrupt + PWM1_FAULT_IRQHandler, // 122: PWM1 fault or reload error interrupt + Reserved123_IRQHandler, // 123: Reserved interrupt + FLEXSPI_IRQHandler, // 124: FlexSPI0 interrupt + SEMC_IRQHandler, // 125: Reserved interrupt + USDHC1_IRQHandler, // 126: USDHC1 interrupt + USDHC2_IRQHandler, // 127: USDHC2 interrupt + USB_OTG2_IRQHandler, // 128: USBO2 USB OTG2 + USB_OTG1_IRQHandler, // 129: USBO2 USB OTG1 + ENET_IRQHandler, // 130: ENET interrupt + ENET_1588_Timer_IRQHandler, // 131: ENET_1588_Timer interrupt + XBAR1_IRQ_0_1_IRQHandler, // 132: XBAR1 interrupt + XBAR1_IRQ_2_3_IRQHandler, // 133: XBAR1 interrupt + ADC_ETC_IRQ0_IRQHandler, // 134: ADCETC IRQ0 interrupt + ADC_ETC_IRQ1_IRQHandler, // 135: ADCETC IRQ1 interrupt + ADC_ETC_IRQ2_IRQHandler, // 136: ADCETC IRQ2 interrupt + ADC_ETC_ERROR_IRQ_IRQHandler, // 137: ADCETC Error IRQ interrupt + PIT_IRQHandler, // 138: PIT interrupt + ACMP1_IRQHandler, // 139: ACMP interrupt + ACMP2_IRQHandler, // 140: ACMP interrupt + ACMP3_IRQHandler, // 141: ACMP interrupt + ACMP4_IRQHandler, // 142: ACMP interrupt + Reserved143_IRQHandler, // 143: Reserved interrupt + Reserved144_IRQHandler, // 144: Reserved interrupt + ENC1_IRQHandler, // 145: ENC1 interrupt + ENC2_IRQHandler, // 146: ENC2 interrupt + ENC3_IRQHandler, // 147: ENC3 interrupt + ENC4_IRQHandler, // 148: ENC4 interrupt + TMR1_IRQHandler, // 149: TMR1 interrupt + TMR2_IRQHandler, // 150: TMR2 interrupt + TMR3_IRQHandler, // 151: TMR3 interrupt + TMR4_IRQHandler, // 152: TMR4 interrupt + PWM2_0_IRQHandler, // 153: PWM2 capture 0, compare 0, or reload 0 interrupt + PWM2_1_IRQHandler, // 154: PWM2 capture 1, compare 1, or reload 0 interrupt + PWM2_2_IRQHandler, // 155: PWM2 capture 2, compare 2, or reload 0 interrupt + PWM2_3_IRQHandler, // 156: PWM2 capture 3, compare 3, or reload 0 interrupt + PWM2_FAULT_IRQHandler, // 157: PWM2 fault or reload error interrupt + PWM3_0_IRQHandler, // 158: PWM3 capture 0, compare 0, or reload 0 interrupt + PWM3_1_IRQHandler, // 159: PWM3 capture 1, compare 1, or reload 0 interrupt + PWM3_2_IRQHandler, // 160: PWM3 capture 2, compare 2, or reload 0 interrupt + PWM3_3_IRQHandler, // 161: PWM3 capture 3, compare 3, or reload 0 interrupt + PWM3_FAULT_IRQHandler, // 162: PWM3 fault or reload error interrupt + PWM4_0_IRQHandler, // 163: PWM4 capture 0, compare 0, or reload 0 interrupt + PWM4_1_IRQHandler, // 164: PWM4 capture 1, compare 1, or reload 0 interrupt + PWM4_2_IRQHandler, // 165: PWM4 capture 2, compare 2, or reload 0 interrupt + PWM4_3_IRQHandler, // 166: PWM4 capture 3, compare 3, or reload 0 interrupt + PWM4_FAULT_IRQHandler, // 167: PWM4 fault or reload error interrupt + Reserved168_IRQHandler, // 168: Reserved interrupt + Reserved169_IRQHandler, // 169: Reserved interrupt + Reserved170_IRQHandler, // 170: Reserved interrupt + Reserved171_IRQHandler, // 171: Reserved interrupt + Reserved172_IRQHandler, // 172: Reserved interrupt + Reserved173_IRQHandler, // 173: Reserved interrupt + SJC_ARM_DEBUG_IRQHandler, // 174: SJC ARM debug interrupt + NMI_WAKEUP_IRQHandler, // 175: NMI wake up +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); +#else + // Disable Watchdog + volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000; + *WDOG1_WCR = *WDOG1_WCR & ~(1 << 2); + volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000; + *WDOG2_WCR = *WDOG2_WCR & ~(1 << 2); + // Write watchdog update key to unlock + *((volatile unsigned int *)0x400BC004) = 0xD928C520; + // Set timeout value + *((volatile unsigned int *)0x400BC008) = 0xFFFF; + // Now disable watchdog via control register + volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000; + *RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) + +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void) +{ DMA0_DMA16_DriverIRQHandler(); +} + +WEAK void DMA1_DMA17_IRQHandler(void) +{ DMA1_DMA17_DriverIRQHandler(); +} + +WEAK void DMA2_DMA18_IRQHandler(void) +{ DMA2_DMA18_DriverIRQHandler(); +} + +WEAK void DMA3_DMA19_IRQHandler(void) +{ DMA3_DMA19_DriverIRQHandler(); +} + +WEAK void DMA4_DMA20_IRQHandler(void) +{ DMA4_DMA20_DriverIRQHandler(); +} + +WEAK void DMA5_DMA21_IRQHandler(void) +{ DMA5_DMA21_DriverIRQHandler(); +} + +WEAK void DMA6_DMA22_IRQHandler(void) +{ DMA6_DMA22_DriverIRQHandler(); +} + +WEAK void DMA7_DMA23_IRQHandler(void) +{ DMA7_DMA23_DriverIRQHandler(); +} + +WEAK void DMA8_DMA24_IRQHandler(void) +{ DMA8_DMA24_DriverIRQHandler(); +} + +WEAK void DMA9_DMA25_IRQHandler(void) +{ DMA9_DMA25_DriverIRQHandler(); +} + +WEAK void DMA10_DMA26_IRQHandler(void) +{ DMA10_DMA26_DriverIRQHandler(); +} + +WEAK void DMA11_DMA27_IRQHandler(void) +{ DMA11_DMA27_DriverIRQHandler(); +} + +WEAK void DMA12_DMA28_IRQHandler(void) +{ DMA12_DMA28_DriverIRQHandler(); +} + +WEAK void DMA13_DMA29_IRQHandler(void) +{ DMA13_DMA29_DriverIRQHandler(); +} + +WEAK void DMA14_DMA30_IRQHandler(void) +{ DMA14_DMA30_DriverIRQHandler(); +} + +WEAK void DMA15_DMA31_IRQHandler(void) +{ DMA15_DMA31_DriverIRQHandler(); +} + +WEAK void DMA_ERROR_IRQHandler(void) +{ DMA_ERROR_DriverIRQHandler(); +} + +WEAK void CTI0_ERROR_IRQHandler(void) +{ CTI0_ERROR_DriverIRQHandler(); +} + +WEAK void CTI1_ERROR_IRQHandler(void) +{ CTI1_ERROR_DriverIRQHandler(); +} + +WEAK void CORE_IRQHandler(void) +{ CORE_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ LPUART4_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ LPUART5_DriverIRQHandler(); +} + +WEAK void LPUART6_IRQHandler(void) +{ LPUART6_DriverIRQHandler(); +} + +WEAK void LPUART7_IRQHandler(void) +{ LPUART7_DriverIRQHandler(); +} + +WEAK void LPUART8_IRQHandler(void) +{ LPUART8_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ LPI2C1_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ LPI2C3_DriverIRQHandler(); +} + +WEAK void LPI2C4_IRQHandler(void) +{ LPI2C4_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ LPSPI1_DriverIRQHandler(); +} + +WEAK void LPSPI2_IRQHandler(void) +{ LPSPI2_DriverIRQHandler(); +} + +WEAK void LPSPI3_IRQHandler(void) +{ LPSPI3_DriverIRQHandler(); +} + +WEAK void LPSPI4_IRQHandler(void) +{ LPSPI4_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ CAN1_DriverIRQHandler(); +} + +WEAK void CAN2_IRQHandler(void) +{ CAN2_DriverIRQHandler(); +} + +WEAK void FLEXRAM_IRQHandler(void) +{ FLEXRAM_DriverIRQHandler(); +} + +WEAK void KPP_IRQHandler(void) +{ KPP_DriverIRQHandler(); +} + +WEAK void TSC_DIG_IRQHandler(void) +{ TSC_DIG_DriverIRQHandler(); +} + +WEAK void GPR_IRQ_IRQHandler(void) +{ GPR_IRQ_DriverIRQHandler(); +} + +WEAK void LCDIF_IRQHandler(void) +{ LCDIF_DriverIRQHandler(); +} + +WEAK void CSI_IRQHandler(void) +{ CSI_DriverIRQHandler(); +} + +WEAK void PXP_IRQHandler(void) +{ PXP_DriverIRQHandler(); +} + +WEAK void WDOG2_IRQHandler(void) +{ WDOG2_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_IRQHandler(void) +{ SNVS_HP_WRAPPER_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void) +{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler(); +} + +WEAK void SNVS_LP_WRAPPER_IRQHandler(void) +{ SNVS_LP_WRAPPER_DriverIRQHandler(); +} + +WEAK void CSU_IRQHandler(void) +{ CSU_DriverIRQHandler(); +} + +WEAK void DCP_IRQHandler(void) +{ DCP_DriverIRQHandler(); +} + +WEAK void DCP_VMI_IRQHandler(void) +{ DCP_VMI_DriverIRQHandler(); +} + +WEAK void Reserved68_IRQHandler(void) +{ Reserved68_DriverIRQHandler(); +} + +WEAK void TRNG_IRQHandler(void) +{ TRNG_DriverIRQHandler(); +} + +WEAK void SJC_IRQHandler(void) +{ SJC_DriverIRQHandler(); +} + +WEAK void BEE_IRQHandler(void) +{ BEE_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void SAI2_IRQHandler(void) +{ SAI2_DriverIRQHandler(); +} + +WEAK void SAI3_RX_IRQHandler(void) +{ SAI3_RX_DriverIRQHandler(); +} + +WEAK void SAI3_TX_IRQHandler(void) +{ SAI3_TX_DriverIRQHandler(); +} + +WEAK void SPDIF_IRQHandler(void) +{ SPDIF_DriverIRQHandler(); +} + +WEAK void ANATOP_EVENT0_IRQHandler(void) +{ ANATOP_EVENT0_DriverIRQHandler(); +} + +WEAK void ANATOP_EVENT1_IRQHandler(void) +{ ANATOP_EVENT1_DriverIRQHandler(); +} + +WEAK void ANATOP_TAMP_LOW_HIGH_IRQHandler(void) +{ ANATOP_TAMP_LOW_HIGH_DriverIRQHandler(); +} + +WEAK void ANATOP_TEMP_PANIC_IRQHandler(void) +{ ANATOP_TEMP_PANIC_DriverIRQHandler(); +} + +WEAK void USB_PHY1_IRQHandler(void) +{ USB_PHY1_DriverIRQHandler(); +} + +WEAK void USB_PHY2_IRQHandler(void) +{ USB_PHY2_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ ADC2_DriverIRQHandler(); +} + +WEAK void DCDC_IRQHandler(void) +{ DCDC_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Reserved87_IRQHandler(void) +{ Reserved87_DriverIRQHandler(); +} + +WEAK void GPIO1_INT0_IRQHandler(void) +{ GPIO1_INT0_DriverIRQHandler(); +} + +WEAK void GPIO1_INT1_IRQHandler(void) +{ GPIO1_INT1_DriverIRQHandler(); +} + +WEAK void GPIO1_INT2_IRQHandler(void) +{ GPIO1_INT2_DriverIRQHandler(); +} + +WEAK void GPIO1_INT3_IRQHandler(void) +{ GPIO1_INT3_DriverIRQHandler(); +} + +WEAK void GPIO1_INT4_IRQHandler(void) +{ GPIO1_INT4_DriverIRQHandler(); +} + +WEAK void GPIO1_INT5_IRQHandler(void) +{ GPIO1_INT5_DriverIRQHandler(); +} + +WEAK void GPIO1_INT6_IRQHandler(void) +{ GPIO1_INT6_DriverIRQHandler(); +} + +WEAK void GPIO1_INT7_IRQHandler(void) +{ GPIO1_INT7_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_0_15_IRQHandler(void) +{ GPIO1_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_16_31_IRQHandler(void) +{ GPIO1_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_0_15_IRQHandler(void) +{ GPIO2_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_16_31_IRQHandler(void) +{ GPIO2_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_0_15_IRQHandler(void) +{ GPIO3_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_16_31_IRQHandler(void) +{ GPIO3_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_0_15_IRQHandler(void) +{ GPIO4_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_16_31_IRQHandler(void) +{ GPIO4_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_0_15_IRQHandler(void) +{ GPIO5_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_16_31_IRQHandler(void) +{ GPIO5_Combined_16_31_DriverIRQHandler(); +} + +WEAK void FLEXIO1_IRQHandler(void) +{ FLEXIO1_DriverIRQHandler(); +} + +WEAK void FLEXIO2_IRQHandler(void) +{ FLEXIO2_DriverIRQHandler(); +} + +WEAK void WDOG1_IRQHandler(void) +{ WDOG1_DriverIRQHandler(); +} + +WEAK void RTWDOG_IRQHandler(void) +{ RTWDOG_DriverIRQHandler(); +} + +WEAK void EWM_IRQHandler(void) +{ EWM_DriverIRQHandler(); +} + +WEAK void CCM_1_IRQHandler(void) +{ CCM_1_DriverIRQHandler(); +} + +WEAK void CCM_2_IRQHandler(void) +{ CCM_2_DriverIRQHandler(); +} + +WEAK void GPC_IRQHandler(void) +{ GPC_DriverIRQHandler(); +} + +WEAK void SRC_IRQHandler(void) +{ SRC_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ Reserved115_DriverIRQHandler(); +} + +WEAK void GPT1_IRQHandler(void) +{ GPT1_DriverIRQHandler(); +} + +WEAK void GPT2_IRQHandler(void) +{ GPT2_DriverIRQHandler(); +} + +WEAK void PWM1_0_IRQHandler(void) +{ PWM1_0_DriverIRQHandler(); +} + +WEAK void PWM1_1_IRQHandler(void) +{ PWM1_1_DriverIRQHandler(); +} + +WEAK void PWM1_2_IRQHandler(void) +{ PWM1_2_DriverIRQHandler(); +} + +WEAK void PWM1_3_IRQHandler(void) +{ PWM1_3_DriverIRQHandler(); +} + +WEAK void PWM1_FAULT_IRQHandler(void) +{ PWM1_FAULT_DriverIRQHandler(); +} + +WEAK void Reserved123_IRQHandler(void) +{ Reserved123_DriverIRQHandler(); +} + +WEAK void FLEXSPI_IRQHandler(void) +{ FLEXSPI_DriverIRQHandler(); +} + +WEAK void SEMC_IRQHandler(void) +{ SEMC_DriverIRQHandler(); +} + +WEAK void USDHC1_IRQHandler(void) +{ USDHC1_DriverIRQHandler(); +} + +WEAK void USDHC2_IRQHandler(void) +{ USDHC2_DriverIRQHandler(); +} + +WEAK void USB_OTG2_IRQHandler(void) +{ USB_OTG2_DriverIRQHandler(); +} + +WEAK void USB_OTG1_IRQHandler(void) +{ USB_OTG1_DriverIRQHandler(); +} + +WEAK void ENET_IRQHandler(void) +{ ENET_DriverIRQHandler(); +} + +WEAK void ENET_1588_Timer_IRQHandler(void) +{ ENET_1588_Timer_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_0_1_IRQHandler(void) +{ XBAR1_IRQ_0_1_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_2_3_IRQHandler(void) +{ XBAR1_IRQ_2_3_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ0_IRQHandler(void) +{ ADC_ETC_IRQ0_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ1_IRQHandler(void) +{ ADC_ETC_IRQ1_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ2_IRQHandler(void) +{ ADC_ETC_IRQ2_DriverIRQHandler(); +} + +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void) +{ ADC_ETC_ERROR_IRQ_DriverIRQHandler(); +} + +WEAK void PIT_IRQHandler(void) +{ PIT_DriverIRQHandler(); +} + +WEAK void ACMP1_IRQHandler(void) +{ ACMP1_DriverIRQHandler(); +} + +WEAK void ACMP2_IRQHandler(void) +{ ACMP2_DriverIRQHandler(); +} + +WEAK void ACMP3_IRQHandler(void) +{ ACMP3_DriverIRQHandler(); +} + +WEAK void ACMP4_IRQHandler(void) +{ ACMP4_DriverIRQHandler(); +} + +WEAK void Reserved143_IRQHandler(void) +{ Reserved143_DriverIRQHandler(); +} + +WEAK void Reserved144_IRQHandler(void) +{ Reserved144_DriverIRQHandler(); +} + +WEAK void ENC1_IRQHandler(void) +{ ENC1_DriverIRQHandler(); +} + +WEAK void ENC2_IRQHandler(void) +{ ENC2_DriverIRQHandler(); +} + +WEAK void ENC3_IRQHandler(void) +{ ENC3_DriverIRQHandler(); +} + +WEAK void ENC4_IRQHandler(void) +{ ENC4_DriverIRQHandler(); +} + +WEAK void TMR1_IRQHandler(void) +{ TMR1_DriverIRQHandler(); +} + +WEAK void TMR2_IRQHandler(void) +{ TMR2_DriverIRQHandler(); +} + +WEAK void TMR3_IRQHandler(void) +{ TMR3_DriverIRQHandler(); +} + +WEAK void TMR4_IRQHandler(void) +{ TMR4_DriverIRQHandler(); +} + +WEAK void PWM2_0_IRQHandler(void) +{ PWM2_0_DriverIRQHandler(); +} + +WEAK void PWM2_1_IRQHandler(void) +{ PWM2_1_DriverIRQHandler(); +} + +WEAK void PWM2_2_IRQHandler(void) +{ PWM2_2_DriverIRQHandler(); +} + +WEAK void PWM2_3_IRQHandler(void) +{ PWM2_3_DriverIRQHandler(); +} + +WEAK void PWM2_FAULT_IRQHandler(void) +{ PWM2_FAULT_DriverIRQHandler(); +} + +WEAK void PWM3_0_IRQHandler(void) +{ PWM3_0_DriverIRQHandler(); +} + +WEAK void PWM3_1_IRQHandler(void) +{ PWM3_1_DriverIRQHandler(); +} + +WEAK void PWM3_2_IRQHandler(void) +{ PWM3_2_DriverIRQHandler(); +} + +WEAK void PWM3_3_IRQHandler(void) +{ PWM3_3_DriverIRQHandler(); +} + +WEAK void PWM3_FAULT_IRQHandler(void) +{ PWM3_FAULT_DriverIRQHandler(); +} + +WEAK void PWM4_0_IRQHandler(void) +{ PWM4_0_DriverIRQHandler(); +} + +WEAK void PWM4_1_IRQHandler(void) +{ PWM4_1_DriverIRQHandler(); +} + +WEAK void PWM4_2_IRQHandler(void) +{ PWM4_2_DriverIRQHandler(); +} + +WEAK void PWM4_3_IRQHandler(void) +{ PWM4_3_DriverIRQHandler(); +} + +WEAK void PWM4_FAULT_IRQHandler(void) +{ PWM4_FAULT_DriverIRQHandler(); +} + +WEAK void Reserved168_IRQHandler(void) +{ Reserved168_DriverIRQHandler(); +} + +WEAK void Reserved169_IRQHandler(void) +{ Reserved169_DriverIRQHandler(); +} + +WEAK void Reserved170_IRQHandler(void) +{ Reserved170_DriverIRQHandler(); +} + +WEAK void Reserved171_IRQHandler(void) +{ Reserved171_DriverIRQHandler(); +} + +WEAK void Reserved172_IRQHandler(void) +{ Reserved172_DriverIRQHandler(); +} + +WEAK void Reserved173_IRQHandler(void) +{ Reserved173_DriverIRQHandler(); +} + +WEAK void SJC_ARM_DEBUG_IRQHandler(void) +{ SJC_ARM_DEBUG_DriverIRQHandler(); +} + +WEAK void NMI_WAKEUP_IRQHandler(void) +{ NMI_WAKEUP_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/system_MIMXRT1052.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/system_MIMXRT1052.c new file mode 100644 index 0000000000..c9e37381b8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/system_MIMXRT1052.c @@ -0,0 +1,255 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052 + * @version 0.1 + * @date 2017-01-10 + * @brief Device specific configuration file for MIMXRT1052 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ +WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; +WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; + +/* Watchdog disable */ + +#if (DISABLE_WDOG) + if (WDOG1->WCR & WDOG_WCR_WDE_MASK) + { + WDOG1->WCR &= ~WDOG_WCR_WDE_MASK; + } + if (WDOG2->WCR & WDOG_WCR_WDE_MASK) + { + WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; + } + RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ + RTWDOG->TOVAL = 0xFFFF; + RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; +#endif /* (DISABLE_WDOG) */ + + /* Disable Systick which might be enabled by bootrom */ + if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) + { + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + +/* Enable instruction and data caches */ +#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } +#endif +#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } +#endif + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t freq; + uint32_t PLL1MainClock; + uint32_t PLL2MainClock; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) + { + freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + } + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CPU_XTAL_CLK_HZ; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) + { + PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + } + + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) + { + PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); + } + PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = PLL2MainClock; + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U; + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U; + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/system_MIMXRT1052.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/system_MIMXRT1052.h new file mode 100644 index 0000000000..8d9f2073d8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/system_MIMXRT1052.h @@ -0,0 +1,147 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052 + * @version 0.1 + * @date 2017-01-10 + * @brief Device specific configuration file for MIMXRT1052 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMXRT1052_H_ +#define _SYSTEM_MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ + +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + +#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMXRT1052_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_assert.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_assert.c new file mode 100644 index 0000000000..a249b64561 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_assert.c @@ -0,0 +1,59 @@ +/* +* The Clear BSD License +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted (subject to the limitations in the disclaimer below) provided +* that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console.c new file mode 100644 index 0000000000..30c762f5e7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console.c @@ -0,0 +1,366 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#if defined(__CC_ARM) +#include +#endif + +#include "fsl_debug_console.h" +#include "fsl_debug_console_conf.h" +#include "fsl_log.h" +#include "fsl_str.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq) +{ + assert(device != DEBUG_CONSOLE_DEVICE_TYPE_NONE); + + return LOG_Init(baseAddr, device, baudRate, clkSrcFreq); +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + /* LOG deinit */ + LOG_Deinit(); + + return kStatus_Success; +} + +status_t DbgConsole_Flush(void) +{ + /* wait log and io idle */ + return LOG_WaitIdle(); +} + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int logLength = 0U, result = 0U; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U}; + + va_start(ap, fmt_s); + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog); + /* print log */ + result = LOG_Push((uint8_t *)printBuf, logLength); + + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return LOG_Push((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_ptr, ...) +{ + va_list ap; + int result; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U}; + + /* scanf log */ + LOG_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, fmt_ptr); + /* format scanf log */ + result = StrFormatScanf(scanfBuf, fmt_ptr, ap); + + va_end(ap); + + return result; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ + if (NULL != ch) + { + return LOG_TryReadCharacter((uint8_t *)ch); + } + + return kStatus_Fail; +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + uint8_t ch; + + /* Get char */ + LOG_ReadCharacter(&ch); + + return ch; +} + +static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + LOG_Push((uint8_t *)buf, *indicator); + *indicator = 0U; + } + + buf[*indicator] = val; + (*indicator)++; + } +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + return 0; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return ((size_t)-1); + } + + /* Send data. */ + LOG_Push((uint8_t *)buffer, 1U); + + return size; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return ((size_t)-1); + } + + /* Receive data.*/ + LOG_ReadLine(buffer, size); + + return size; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif(defined(__REDLIB__)) + +#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (buffer == 0) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + LOG_Push((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + LOG_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif(defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) + +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (buffer == 0) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + LOG_Push((uint8_t *)buffer, size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + return LOG_ReadLine((uint8_t *)buffer, size); +} +#endif + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) +#if defined(SDK_DEBUGCONSOLE_UART) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return LOG_Push((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + LOG_ReadCharacter((uint8_t *)&ch); + + return ch; +} +#endif /* SDK_DEBUGCONSOLE_UART */ +#endif /* __ICCARM__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console.h new file mode 100644 index 0000000000..14dd3a0c2d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console.h @@ -0,0 +1,207 @@ +/* + * The Clear BSD License + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Definition to select sdk or toolchain printf, scanf. */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE 1U +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */ +#ifndef SDK_DEBUGCONSOLE_UART +/* mcux will handle this macro, not define it here */ +#if (!defined(__MCUXPRESSO)) +#define SDK_DEBUGCONSOLE_UART +#endif +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#endif + +#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#else /* Select printf, scanf, putchar, getchar of toolchain. */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral, + * frequency of peripheral source clock, and base address at the specified baud rate. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param baseAddr Indicates the address of the peripheral used to send debug messages. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg DEBUG_CONSOLE_DEVICE_TYPE_UART, + * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART, + * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI, + * @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC. + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + * @retval kStatus_Fail Execution failure + * @retval kStatus_InvalidArgument Invalid argument existed + */ +status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * base address and at the specified baud rate. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @param fmt_ptr Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_ptr, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Debug console flush log. + * + * Call this function to wait the buffer empty and io idle before. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provide a api which will not block current task, if character is + * avaliable return it , otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console_conf.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console_conf.h new file mode 100644 index 0000000000..7dfad4207d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_debug_console_conf.h @@ -0,0 +1,160 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, +* otherwise blocking mode is the default transfer mode. +* Warning: If you want to use non-blocking transfer,please make sure the corresponding +* IO interrupt is enable, otherwise there is no output. +* And non-blocking is combine with buffer, no matter bare-metal or rtos. +*/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically +* when +* non-blocking transfer is using, +* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. +* If it is configured too small, log maybe missed , because the log will not be +* buffered if the buffer is full, and the print will return immediately with -1. +* And this value should be multiple of 4 to meet memory alignment. +* +*/ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when +* non-blocking transfer is using, +* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. +* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. +* And this value should be multiple of 4 to meet memory alignment. +* +*/ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log +* length can not bigger than this value. +* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if +* the buffer is too big and current task stack size not big enough. +*/ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log +* length can not bigger than this value. +* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. +*/ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization +* User should not change these macro for synchronization mode, but add the +* corresponding synchronization mechanism per different software environment. +* Such as, if another RTOS is used, +* add: +* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 +* in this configuration file and implement the synchronization in fsl.log.c. +*/ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable +* If not defined, default is enable, to avoid multitask log print mess. +* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c +* If synchronization is disabled, log maybe messed on terminal. +*/ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef FSL_RTOS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* FSL_RTOS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support +* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO +* at your project setting. +*/ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_notifier.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_notifier.c new file mode 100644 index 0000000000..10cb9bece7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_notifier.c @@ -0,0 +1,186 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_notifier.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData) +{ + /* Check input parameter - at least one configuration is required and userFunction must exist */ + if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL)) + { + return kStatus_Fail; + } + /* Initialize handle structure */ + memset(notifierHandle, 0, sizeof(notifier_handle_t)); + /* Store references to user-defined configurations */ + notifierHandle->configsTable = configs; + notifierHandle->configsNumber = configsNumber; + /* Store references to user-defined callback configurations */ + if (callbacks != NULL) + { + notifierHandle->callbacksTable = callbacks; + notifierHandle->callbacksNumber = callbacksNumber; + /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */ + notifierHandle->errorCallbackIndex = callbacksNumber; + } + notifierHandle->userFunction = userFunction; + notifierHandle->userData = userData; + + return kStatus_Success; +} + +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy) +{ + uint8_t currentStaticCallback = 0U; /* Index to array of statically registered call-backs */ + status_t returnCode = kStatus_Success; /* Function return */ + + notifier_notification_block_t notifyBlock; /* Callback notification block */ + notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */ + + /* Set errorcallbackindex as callbacksNumber, which means no callback error now */ + notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber; + + /* Requested configuration availability check */ + if (configIndex >= notifierHandle->configsNumber) + { + return kStatus_OutOfRange; + } + + /* Initialization of local variables from the Notifier handle structure */ + + notifyBlock.policy = policy; + notifyBlock.targetConfig = notifierHandle->configsTable[configIndex]; + notifyBlock.notifyType = kNOTIFIER_NotifyBefore; + + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called before the configuration switch */ + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) + { + /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel + * the configuration switch */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = kStatus_NOTIFIER_ErrorNotificationBefore; + notifierHandle->errorCallbackIndex = currentStaticCallback; + /* If not forcing configuration switch, call all already notified call-backs to revert their state + * as the switch is canceled */ + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + + /* Set configuration */ + + /* In case that any call-back returned error code and policy doesn't force the configuration set, go to after + * switch call-backs */ + if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success)) + { + returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData); + if (returnCode != kStatus_Success) + { + return returnCode; + } + /* Update current configuration index */ + notifierHandle->currentConfigIndex = configIndex; + notifyBlock.notifyType = kNOTIFIER_NotifyAfter; + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; + currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called after the configruation switch */ + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackAfter) + { + /* In case that call-back returned error code mark it and store the call-back handle */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = kStatus_NOTIFIER_ErrorNotificationAfter; + notifierHandle->errorCallbackIndex = currentStaticCallback; + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + } + else + { + /* End of unsuccessful switch */ + notifyBlock.notifyType = kNOTIFIER_NotifyRecover; + while (currentStaticCallback--) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) + { + callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData); + } + } + } + + return returnCode; +} + +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle) +{ + return notifierHandle->errorCallbackIndex; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_notifier.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_notifier.h new file mode 100644 index 0000000000..5c930d9812 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_notifier.h @@ -0,0 +1,263 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_NOTIFIER_H_ +#define _FSL_NOTIFIER_H_ + +#include "fsl_common.h" +/*! + * @addtogroup notifier + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Notifier error codes. + * + * Used as return value of Notifier functions. + */ +enum _notifier_status +{ + kStatus_NOTIFIER_ErrorNotificationBefore = + MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */ + kStatus_NOTIFIER_ErrorNotificationAfter = + MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */ +}; + +/*! + * @brief Notifier policies. + * + * Defines whether the user function execution is forced or not. + * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results, + * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig() + * when any of the callbacks returns error code. + * See also NOTIFIER_SwitchConfig() description. + */ +typedef enum _notifier_policy +{ + kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error + code. */ + kNOTIFIER_PolicyForcible, /*!< The user function is executed regardless of the results. */ +} notifier_policy_t; + +/*! @brief Notification type. Used to notify registered callbacks */ +typedef enum _notifier_notification_type +{ + kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */ + kNOTIFIER_NotifyBefore = 0x01U, /*!< Notify IP that configuration setting is going to change. */ + kNOTIFIER_NotifyAfter = 0x02U, /*!< Notify IP that configuration setting has been changed. */ +} notifier_notification_type_t; + +/*! + * @brief The callback type, which indicates kinds of notification the callback handles. + * + * Used in the callback configuration structure (notifier_callback_config_t) + * to specify when the registered callback is called during configuration switch initiated by the + * NOTIFIER_SwitchConfig(). + * Callback can be invoked in following situations. + * - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig() + * execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation). + * - After an unsuccessful attempt to switch configuration + * - After a successful configuration switch + */ +typedef enum _notifier_callback_type +{ + kNOTIFIER_CallbackBefore = 0x01U, /*!< Callback handles BEFORE notification. */ + kNOTIFIER_CallbackAfter = 0x02U, /*!< Callback handles AFTER notification. */ + kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */ +} notifier_callback_type_t; + +/*! @brief Notifier user configuration type. + * + * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations + * based on this array. + */ +typedef void notifier_user_config_t; + +/*! @brief Notifier user function prototype + * Use this function to execute specific operations in configuration switch. + * Before and after this function execution, different notification is sent to registered callbacks. + * If this function returns any error code, NOTIFIER_SwitchConfig() exits. + * + * @param targetConfig target Configuration. + * @param userData Refers to other specific data passed to user function. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData); + +/*! @brief notification block passed to the registered callback function. */ +typedef struct _notifier_notification_block +{ + notifier_user_config_t *targetConfig; /*!< Pointer to target configuration. */ + notifier_policy_t policy; /*!< Configure transition policy. */ + notifier_notification_type_t notifyType; /*!< Configure notification type. */ +} notifier_notification_block_t; + +/*! + * @brief Callback prototype. + * + * Declaration of a callback. It is common for registered callbacks. + * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure. + * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig()) + * before configuration switch, after it or in both use cases to notify about + * the switch progress (see notifier_callback_type_t). When called, the type of the notification + * is passed as a parameter along with the reference to the target configuration structure (see notifier_notification_block_t) + * and any data passed during the callback registration. + * When notified before the configuration switch, depending on the configuration switch policy (see + * notifier_policy_t), the callback may deny the execution of the user function by returning an error code different + * than kStatus_Success (see NOTIFIER_SwitchConfig()). + * + * @param notify Notification block. + * @param data Callback data. Refers to the data passed during callback registration. Intended to + * pass any driver or application data such as internal state information. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data); + +/*! + * @brief Callback configuration structure. + * + * This structure holds the configuration of callbacks. + * Callbacks of this type are expected to be statically allocated. + * This structure contains the following application-defined data. + * callback - pointer to the callback function + * callbackType - specifies when the callback is called + * callbackData - pointer to the data passed to the callback. + */ +typedef struct _notifier_callback_config +{ + notifier_callback_t callback; /*!< Pointer to the callback function. */ + notifier_callback_type_t callbackType; /*!< Callback type. */ + void *callbackData; /*!< Pointer to the data passed to the callback. */ +} notifier_callback_config_t; + +/*! + * @brief Notifier handle structure. + * + * Notifier handle structure. Contains data necessary for the Notifier proper function. + * Stores references to registered configurations, callbacks, information about their numbers, + * user function, user data, and other internal data. + * NOTIFIER_CreateHandle() must be called to initialize this handle. + */ +typedef struct _notifier_handle +{ + notifier_user_config_t **configsTable; /*!< Pointer to configure table. */ + uint8_t configsNumber; /*!< Number of configurations. */ + notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */ + uint8_t callbacksNumber; /*!< Maximum number of callback configurations. */ + uint8_t errorCallbackIndex; /*!< Index of callback returns error. */ + uint8_t currentConfigIndex; /*!< Index of current configuration. */ + notifier_user_function_t userFunction; /*!< User function. */ + void *userData; /*!< User data passed to user function. */ +} notifier_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Creates a Notifier handle. + * + * @param notifierHandle A pointer to the notifier handle. + * @param configs A pointer to an array with references to all configurations which is handled by the Notifier. + * @param configsNumber Number of configurations. Size of the configuration array. + * @param callbacks A pointer to an array of callback configurations. + * If there are no callbacks to register during Notifier initialization, use NULL value. + * @param callbacksNumber Number of registered callbacks. Size of the callbacks array. + * @param userFunction User function. + * @param userData User data passed to user function. + * @return An error Code or kStatus_Success. + */ +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData); + +/*! + * @brief Switches the configuration according to a pre-defined structure. + * + * This function sets the system to the target configuration. Before transition, + * the Notifier sends notifications to all callbacks registered to the callback table. + * Callbacks are invoked in the following order: All registered callbacks are notified + * ordered by index in the callbacks array. The same order is used for before and after switch notifications. + * The notifications before the configuration switch can be used to obtain confirmation about + * the change from registered callbacks. If any registered callback denies the + * configuration change, further execution of this function depends on the notifier policy: the + * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). + * When configuration change is forced, the result of the before switch notifications are ignored. If an + * agreement is required, if any callback returns an error code, further notifications + * before switch notifications are cancelled and all already notified callbacks are re-invoked. + * The index of the callback which returned error code during pre-switch notifications is stored + * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. + * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase + * the error occurred is returned when NOTIFIER_SwitchConfig() exits. + * @param notifierHandle pointer to notifier handle + * @param configIndex Index of the target configuration. + * @param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. + * + * @return An error code or kStatus_Success. + * + */ +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy); + +/*! + * @brief This function returns the last failed notification callback. + * + * This function returns an index of the last callback that failed during the configuration switch while + * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully + * value equal to callbacks number is returned. The returned value represents an index in the array of + * static call-backs. + * + * @param notifierHandle Pointer to the notifier handle + * @return Callback Index of the last failed callback or value equal to callbacks count. + */ +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_NOTIFIER_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_sbrk.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_sbrk.c new file mode 100644 index 0000000000..0bb3802dd5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_sbrk.c @@ -0,0 +1,70 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if defined(__GNUC__) +#include +#include +#endif + +#if defined(__GNUC__) +/*! + * @brief Function to override ARMGCC default function _sbrk + * + * _sbrk is called by malloc. ARMGCC default _sbrk compares "SP" register and + * heap end, if heap end is larger than "SP", then _sbrk returns error and + * memory allocation failed. This function changes to compare __HeapLimit with + * heap end. + */ +caddr_t _sbrk(int incr) +{ + extern char end __asm("end"); + extern char heap_limit __asm("__HeapLimit"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == NULL) + heap_end = &end; + + prev_heap_end = heap_end; + + if ((unsigned int)heap_end + incr > (unsigned int)(&heap_limit)) + { + errno = ENOMEM; + return (caddr_t)-1; + } + + heap_end = (char *)((unsigned int)heap_end + incr); + + return (caddr_t)prev_heap_end; +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_shell.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_shell.c new file mode 100644 index 0000000000..e8030ea68b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_shell.c @@ -0,0 +1,651 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * POSIX getopt for Windows + * Code given out at the 1985 UNIFORUM conference in Dallas. + * + * From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985 + * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET + * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP + * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix + * From: std-unix@ut-sally.UUCP (Moderator, John Quarterman) + * Newsgroups: mod.std.unix + * Subject: public domain AT&T getopt source + * Message-ID: <3352@ut-sally.UUCP> + * Date: 3 Nov 85 19:34:15 GMT + * Date-Received: 4 Nov 85 12:25:09 GMT + * Organization: IEEE/P1003 Portable Operating System Environment Committee + * Lines: 91 + * Approved: jsq@ut-sally.UUC + * Here's something you've all been waiting for: the AT&T public domain + * source for getopt(3). It is the code which was given out at the 1985 + * UNIFORUM conference in Dallas. I obtained it by electronic mail + * directly from AT&T. The people there assure me that it is indeed + * in the public domain + * There is no manual page. That is because the one they gave out at + * UNIFORUM was slightly different from the current System V Release 2 + * manual page. The difference apparently involved a note about the + * famous rules 5 and 6, recommending using white space between an option + * and its first argument, and not grouping options that have arguments. + * Getopt itself is currently lenient about both of these things White + * space is allowed, but not mandatory, and the last option in a group can + * have an argument. That particular version of the man page evidently + * has no official existence, and my source at AT&T did not send a copy. + * The current SVR2 man page reflects the actual behavor of this getopt. + * However, I am not about to post a copy of anything licensed by AT&T. + */ + +#include +#include "fsl_shell.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define KEY_ESC (0x1BU) +#define KET_DEL (0x7FU) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static int32_t HelpCommand(p_shell_context_t context, int32_t argc, char **argv); /*!< help command */ + +static int32_t ExitCommand(p_shell_context_t context, int32_t argc, char **argv); /*!< exit command */ + +static int32_t ParseLine(const char *cmd, uint32_t len, char *argv[SHELL_MAX_ARGS]); /*!< parse line command */ + +static int32_t StrCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */ + +static void ProcessCommand(p_shell_context_t context, const char *cmd); /*!< process a command */ + +static void GetHistoryCommand(p_shell_context_t context, uint8_t hist_pos); /*!< get commands history */ + +static void AutoComplete(p_shell_context_t context); /*!< auto complete command */ + +static uint8_t GetChar(p_shell_context_t context); /*!< get a char from communication interface */ + +static int32_t StrLen(const char *str); /*!< get string length */ + +static char *StrCopy(char *dest, const char *src, int32_t count); /*!< string copy */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static const shell_command_context_t xHelpCommand = {"help", "\r\n\"help\": Lists all the registered commands\r\n", + HelpCommand, 0}; + +static const shell_command_context_t xExitCommand = {"exit", "\r\n\"exit\": Exit program\r\n", ExitCommand, 0}; + +static shell_command_context_list_t g_RegisteredCommands; + +static char g_paramBuffer[SHELL_BUFFER_SIZE]; + +/******************************************************************************* + * Code + ******************************************************************************/ +void SHELL_Init( + p_shell_context_t context, send_data_cb_t send_cb, recv_data_cb_t recv_cb, printf_data_t shell_printf, char *prompt) +{ + assert(send_cb != NULL); + assert(recv_cb != NULL); + assert(prompt != NULL); + assert(shell_printf != NULL); + + /* Memset for context */ + memset(context, 0, sizeof(shell_context_struct)); + context->send_data_func = send_cb; + context->recv_data_func = recv_cb; + context->printf_data_func = shell_printf; + context->prompt = prompt; + + SHELL_RegisterCommand(&xHelpCommand); + SHELL_RegisterCommand(&xExitCommand); +} + +int32_t SHELL_Main(p_shell_context_t context) +{ + uint8_t ch; + int32_t i; + + if (!context) + { + return -1; + } + + context->exit = false; + context->printf_data_func("\r\nSHELL (build: %s)\r\n", __DATE__); + context->printf_data_func("Copyright (c) 2017 NXP Semiconductor\r\n"); + context->printf_data_func(context->prompt); + + while (1) + { + if (context->exit) + { + break; + } + ch = GetChar(context); + /* If error occured when getting a char, continue to receive a new char. */ + if ((uint8_t)(-1) == ch) + { + continue; + } + /* Special key */ + if (ch == KEY_ESC) + { + context->stat = kSHELL_Special; + continue; + } + else if (context->stat == kSHELL_Special) + { + /* Function key */ + if (ch == '[') + { + context->stat = kSHELL_Function; + continue; + } + context->stat = kSHELL_Normal; + } + else if (context->stat == kSHELL_Function) + { + context->stat = kSHELL_Normal; + + switch ((uint8_t)ch) + { + /* History operation here */ + case 'A': /* Up key */ + GetHistoryCommand(context, context->hist_current); + if (context->hist_current < (context->hist_count - 1)) + { + context->hist_current++; + } + break; + case 'B': /* Down key */ + GetHistoryCommand(context, context->hist_current); + if (context->hist_current > 0) + { + context->hist_current--; + } + break; + case 'D': /* Left key */ + if (context->c_pos) + { + context->printf_data_func("\b"); + context->c_pos--; + } + break; + case 'C': /* Right key */ + if (context->c_pos < context->l_pos) + { + context->printf_data_func("%c", context->line[context->c_pos]); + context->c_pos++; + } + break; + default: + break; + } + continue; + } + /* Handle tab key */ + else if (ch == '\t') + { +#if SHELL_AUTO_COMPLETE + /* Move the cursor to the beginning of line */ + for (i = 0; i < context->c_pos; i++) + { + context->printf_data_func("\b"); + } + /* Do auto complete */ + AutoComplete(context); + /* Move position to end */ + context->c_pos = context->l_pos = StrLen(context->line); +#endif + continue; + } +#if SHELL_SEARCH_IN_HIST + /* Search command in history */ + else if ((ch == '`') && (context->l_pos == 0) && (context->line[0] == 0x00)) + { + } +#endif + /* Handle backspace key */ + else if ((ch == KET_DEL) || (ch == '\b')) + { + /* There must be at last one char */ + if (context->c_pos == 0) + { + continue; + } + + context->l_pos--; + context->c_pos--; + + if (context->l_pos > context->c_pos) + { + memmove(&context->line[context->c_pos], &context->line[context->c_pos + 1], + context->l_pos - context->c_pos); + context->line[context->l_pos] = 0; + context->printf_data_func("\b%s \b", &context->line[context->c_pos]); + + /* Reset position */ + for (i = context->c_pos; i <= context->l_pos; i++) + { + context->printf_data_func("\b"); + } + } + else /* Normal backspace operation */ + { + context->printf_data_func("\b \b"); + context->line[context->l_pos] = 0; + } + continue; + } + else + { + } + + /* Input too long */ + if (context->l_pos >= (SHELL_BUFFER_SIZE - 1)) + { + context->l_pos = 0; + } + + /* Handle end of line, break */ + if ((ch == '\r') || (ch == '\n')) + { + static char endoflinechar = 0U; + + if ((endoflinechar != 0U) && (endoflinechar != ch)) + { + continue; + } + else + { + endoflinechar = ch; + context->printf_data_func("\r\n"); + /* If command line is NULL, will start a new transfer */ + if (0U == StrLen(context->line)) + { + context->printf_data_func(context->prompt); + continue; + } + ProcessCommand(context, context->line); + /* Reset all params */ + context->c_pos = context->l_pos = 0; + context->hist_current = 0; + context->printf_data_func(context->prompt); + memset(context->line, 0, sizeof(context->line)); + continue; + } + } + + /* Normal character */ + if (context->c_pos < context->l_pos) + { + memmove(&context->line[context->c_pos + 1], &context->line[context->c_pos], + context->l_pos - context->c_pos); + context->line[context->c_pos] = ch; + context->printf_data_func("%s", &context->line[context->c_pos]); + /* Move the cursor to new position */ + for (i = context->c_pos; i < context->l_pos; i++) + { + context->printf_data_func("\b"); + } + } + else + { + context->line[context->l_pos] = ch; + context->printf_data_func("%c", ch); + } + + ch = 0; + context->l_pos++; + context->c_pos++; + } + return 0; +} + +static int32_t HelpCommand(p_shell_context_t context, int32_t argc, char **argv) +{ + uint8_t i = 0; + + for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) + { + context->printf_data_func(g_RegisteredCommands.CommandList[i]->pcHelpString); + } + return 0; +} + +static int32_t ExitCommand(p_shell_context_t context, int32_t argc, char **argv) +{ + /* Skip warning */ + context->printf_data_func("\r\nSHELL exited\r\n"); + context->exit = true; + return 0; +} + +static void ProcessCommand(p_shell_context_t context, const char *cmd) +{ + static const shell_command_context_t *tmpCommand = NULL; + static const char *tmpCommandString; + int32_t argc; + char *argv[SHELL_BUFFER_SIZE]; + uint8_t flag = 1; + uint8_t tmpCommandLen; + uint8_t tmpLen; + uint8_t i = 0; + + tmpLen = StrLen(cmd); + argc = ParseLine(cmd, tmpLen, argv); + + if ((tmpCommand == NULL) && (argc > 0)) + { + for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) + { + tmpCommand = g_RegisteredCommands.CommandList[i]; + tmpCommandString = tmpCommand->pcCommand; + tmpCommandLen = StrLen(tmpCommandString); + /* Compare with space or end of string */ + if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == 0x00)) + { + if (StrCompare(tmpCommandString, argv[0], tmpCommandLen) == 0) + { + /* support commands with optional number of parameters */ + if (tmpCommand->cExpectedNumberOfParameters == SHELL_OPTIONAL_PARAMS) + { + flag = 0; + } + else if ((tmpCommand->cExpectedNumberOfParameters == 0) && (argc == 1)) + { + flag = 0; + } + else if (tmpCommand->cExpectedNumberOfParameters > 0) + { + if ((argc - 1) == tmpCommand->cExpectedNumberOfParameters) + { + flag = 0; + } + } + else + { + flag = 1; + } + break; + } + } + } + } + + if ((tmpCommand != NULL) && (flag == 1U)) + { + context->printf_data_func( + "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n"); + tmpCommand = NULL; + } + else if (tmpCommand != NULL) + { + tmpLen = StrLen(cmd); + /* Compare with last command. Push back to history buffer if different */ + if (tmpLen != StrCompare(cmd, context->hist_buf[0], StrLen(cmd))) + { + for (i = SHELL_HIST_MAX - 1; i > 0; i--) + { + memset(context->hist_buf[i], '\0', SHELL_BUFFER_SIZE); + tmpLen = StrLen(context->hist_buf[i - 1]); + StrCopy(context->hist_buf[i], context->hist_buf[i - 1], tmpLen); + } + memset(context->hist_buf[0], '\0', SHELL_BUFFER_SIZE); + tmpLen = StrLen(cmd); + StrCopy(context->hist_buf[0], cmd, tmpLen); + if (context->hist_count < SHELL_HIST_MAX) + { + context->hist_count++; + } + } + tmpCommand->pFuncCallBack(context, argc, argv); + tmpCommand = NULL; + } + else + { + context->printf_data_func( + "\r\nCommand not recognised. Enter 'help' to view a list of available commands.\r\n\r\n"); + tmpCommand = NULL; + } +} + +static void GetHistoryCommand(p_shell_context_t context, uint8_t hist_pos) +{ + uint8_t i; + uint32_t tmp; + + if (context->hist_buf[0][0] == '\0') + { + context->hist_current = 0; + return; + } + if (hist_pos >= SHELL_HIST_MAX) + { + hist_pos = SHELL_HIST_MAX - 1; + } + tmp = StrLen(context->line); + /* Clear current if have */ + if (tmp > 0) + { + memset(context->line, '\0', tmp); + for (i = 0; i < tmp; i++) + { + context->printf_data_func("\b \b"); + } + } + + context->l_pos = StrLen(context->hist_buf[hist_pos]); + context->c_pos = context->l_pos; + StrCopy(context->line, context->hist_buf[hist_pos], context->l_pos); + context->printf_data_func(context->hist_buf[hist_pos]); +} + +static void AutoComplete(p_shell_context_t context) +{ + int32_t len; + int32_t minLen; + uint8_t i = 0; + const shell_command_context_t *tmpCommand = NULL; + const char *namePtr; + const char *cmdName; + + minLen = 0; + namePtr = NULL; + + if (!StrLen(context->line)) + { + return; + } + context->printf_data_func("\r\n"); + /* Empty tab, list all commands */ + if (context->line[0] == '\0') + { + HelpCommand(context, 0, NULL); + return; + } + /* Do auto complete */ + for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) + { + tmpCommand = g_RegisteredCommands.CommandList[i]; + cmdName = tmpCommand->pcCommand; + if (StrCompare(context->line, cmdName, StrLen(context->line)) == 0) + { + if (minLen == 0) + { + namePtr = cmdName; + minLen = StrLen(namePtr); + /* Show possible matches */ + context->printf_data_func("%s\r\n", cmdName); + continue; + } + len = StrCompare(namePtr, cmdName, StrLen(namePtr)); + if (len < 0) + { + len = len * (-1); + } + if (len < minLen) + { + minLen = len; + } + } + } + /* Auto complete string */ + if (namePtr) + { + StrCopy(context->line, namePtr, minLen); + } + context->printf_data_func("%s%s", context->prompt, context->line); + return; +} + +static char *StrCopy(char *dest, const char *src, int32_t count) +{ + char *ret = dest; + int32_t i = 0; + + for (i = 0; i < count; i++) + { + dest[i] = src[i]; + } + + return ret; +} + +static int32_t StrLen(const char *str) +{ + int32_t i = 0; + + while (*str) + { + str++; + i++; + } + return i; +} + +static int32_t StrCompare(const char *str1, const char *str2, int32_t count) +{ + while (count--) + { + if (*str1++ != *str2++) + { + return *(unsigned char *)(str1 - 1) - *(unsigned char *)(str2 - 1); + } + } + return 0; +} + +static int32_t ParseLine(const char *cmd, uint32_t len, char *argv[SHELL_MAX_ARGS]) +{ + uint32_t argc; + char *p; + uint32_t position; + + /* Init params */ + memset(g_paramBuffer, '\0', len + 1); + StrCopy(g_paramBuffer, cmd, len); + + p = g_paramBuffer; + position = 0; + argc = 0; + + while (position < len) + { + /* Skip all blanks */ + while (((char)(*p) == ' ') && (position < len)) + { + *p = '\0'; + p++; + position++; + } + /* Process begin of a string */ + if (*p == '"') + { + p++; + position++; + argv[argc] = p; + argc++; + /* Skip this string */ + while ((*p != '"') && (position < len)) + { + p++; + position++; + } + /* Skip '"' */ + *p = '\0'; + p++; + position++; + } + else /* Normal char */ + { + argv[argc] = p; + argc++; + while (((char)*p != ' ') && ((char)*p != '\t') && (position < len)) + { + p++; + position++; + } + } + } + return argc; +} + +int32_t SHELL_RegisterCommand(const shell_command_context_t *command_context) +{ + int32_t result = 0; + + /* If have room in command list */ + if (g_RegisteredCommands.numberOfCommandInList < SHELL_MAX_CMD) + { + g_RegisteredCommands.CommandList[g_RegisteredCommands.numberOfCommandInList++] = command_context; + } + else + { + result = -1; + } + return result; +} + +static uint8_t GetChar(p_shell_context_t context) +{ + uint8_t ch; + +#if SHELL_USE_FILE_STREAM + ch = fgetc(context->STDIN); +#else + context->recv_data_func(&ch, 1U); +#endif + return ch; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_shell.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_shell.h new file mode 100644 index 0000000000..c1cc6225b6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/fsl_shell.h @@ -0,0 +1,211 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SHELL_H_ +#define _FSL_SHELL_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup SHELL + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Macro to set on/off history feature. */ +#ifndef SHELL_USE_HISTORY +#define SHELL_USE_HISTORY (0U) +#endif + +/*! @brief Macro to set on/off history feature. */ +#ifndef SHELL_SEARCH_IN_HIST +#define SHELL_SEARCH_IN_HIST (1U) +#endif + +/*! @brief Macro to select method stream. */ +#ifndef SHELL_USE_FILE_STREAM +#define SHELL_USE_FILE_STREAM (0U) +#endif + +/*! @brief Macro to set on/off auto-complete feature. */ +#ifndef SHELL_AUTO_COMPLETE +#define SHELL_AUTO_COMPLETE (1U) +#endif + +/*! @brief Macro to set console buffer size. */ +#ifndef SHELL_BUFFER_SIZE +#define SHELL_BUFFER_SIZE (64U) +#endif + +/*! @brief Macro to set maximum arguments in command. */ +#ifndef SHELL_MAX_ARGS +#define SHELL_MAX_ARGS (8U) +#endif + +/*! @brief Macro to set maximum count of history commands. */ +#ifndef SHELL_HIST_MAX +#define SHELL_HIST_MAX (3U) +#endif + +/*! @brief Macro to set maximum count of commands. */ +#ifndef SHELL_MAX_CMD +#define SHELL_MAX_CMD (20U) +#endif + +/*! @brief Macro to bypass arguments check */ +#define SHELL_OPTIONAL_PARAMS (0xFF) + +/*! @brief Shell user send data callback prototype.*/ +typedef void (*send_data_cb_t)(uint8_t *buf, uint32_t len); + +/*! @brief Shell user receiver data callback prototype.*/ +typedef void (*recv_data_cb_t)(uint8_t *buf, uint32_t len); + +/*! @brief Shell user printf data prototype.*/ +typedef int (*printf_data_t)(const char *format, ...); + +/*! @brief A type for the handle special key. */ +typedef enum _fun_key_status +{ + kSHELL_Normal = 0U, /*!< Normal key */ + kSHELL_Special = 1U, /*!< Special key */ + kSHELL_Function = 2U, /*!< Function key */ +} fun_key_status_t; + +/*! @brief Data structure for Shell environment. */ +typedef struct _shell_context_struct +{ + char *prompt; /*!< Prompt string */ + enum _fun_key_status stat; /*!< Special key status */ + char line[SHELL_BUFFER_SIZE]; /*!< Consult buffer */ + uint8_t cmd_num; /*!< Number of user commands */ + uint8_t l_pos; /*!< Total line position */ + uint8_t c_pos; /*!< Current line position */ +#if SHELL_USE_FILE_STREAM + FILE *STDOUT, *STDIN, *STDERR; +#else + send_data_cb_t send_data_func; /*!< Send data interface operation */ + recv_data_cb_t recv_data_func; /*!< Receive data interface operation */ + printf_data_t printf_data_func; +#endif + uint16_t hist_current; /*!< Current history command in hist buff*/ + uint16_t hist_count; /*!< Total history command in hist buff*/ + char hist_buf[SHELL_HIST_MAX][SHELL_BUFFER_SIZE]; /*!< History buffer*/ + bool exit; /*!< Exit Flag*/ +} shell_context_struct, *p_shell_context_t; + +/*! @brief User command function prototype. */ +typedef int32_t (*cmd_function_t)(p_shell_context_t context, int32_t argc, char **argv); + +/*! @brief User command data structure. */ +typedef struct _shell_command_context +{ + const char *pcCommand; /*!< The command that is executed. For example "help". It must be all lower case. */ + char *pcHelpString; /*!< String that describes how to use the command. It should start with the command itself, + and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */ + const cmd_function_t + pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */ + uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */ +} shell_command_context_t; + +/*! @brief Structure list command. */ +typedef struct _shell_command_context_list +{ + const shell_command_context_t *CommandList[SHELL_MAX_CMD]; /*!< The command table list */ + uint8_t numberOfCommandInList; /*!< The total command in list */ +} shell_command_context_list_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Shell functional operation + * @{ + */ + +/*! +* @brief Enables the clock gate and configures the Shell module according to the configuration structure. +* +* This function must be called before calling all other Shell functions. +* Call operation the Shell commands with user-defined settings. +* The example below shows how to set up the middleware Shell and +* how to call the SHELL_Init function by passing in these parameters. +* This is an example. +* @code +* shell_context_struct user_context; +* SHELL_Init(&user_context, SendDataFunc, ReceiveDataFunc, "SHELL>> "); +* @endcode +* @param context The pointer to the Shell environment and runtime states. +* @param send_cb The pointer to call back send data function. +* @param recv_cb The pointer to call back receive data function. +* @param prompt The string prompt of Shell +*/ +void SHELL_Init(p_shell_context_t context, + send_data_cb_t send_cb, + recv_data_cb_t recv_cb, + printf_data_t shell_printf, + char *prompt); + +/*! + * @brief Shell register command. + * @param command_context The pointer to the command data structure. + * @return -1 if error or 0 if success + */ +int32_t SHELL_RegisterCommand(const shell_command_context_t *command_context); + +/*! + * @brief Main loop for Shell. + * Main loop for Shell; After this function is called, Shell begins to initialize the basic variables and starts to + * work. + * @param context The pointer to the Shell environment and runtime states. + * @return This function does not return until Shell command exit was called. + */ +int32_t SHELL_Main(p_shell_context_t context); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SHELL_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/fsl_io.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/fsl_io.c new file mode 100644 index 0000000000..434564150d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/fsl_io.c @@ -0,0 +1,815 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "fsl_io.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* check avaliable device */ +#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT != 0)) +#define DEBUG_CONSOLE_IO_UART +#endif + +#if (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT != 0)) +#define DEBUG_CONSOLE_IO_IUART +#endif + +#if (defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT != 0)) +#define DEBUG_CONSOLE_IO_LPUART +#endif + +#if (defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT != 0)) +#define DEBUG_CONSOLE_IO_LPSCI +#endif + +#if ((defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT != 0)) && \ + (defined(BOARD_USE_VIRTUALCOM) && (BOARD_USE_VIRTUALCOM != 0))) +#define DEBUG_CONSOLE_IO_USBCDC +#endif + +#if (defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT != 0)) +#define DEBUG_CONSOLE_IO_FLEXCOMM +#endif + +#if (defined(FSL_FEATURE_SOC_VFIFO_COUNT) && (FSL_FEATURE_SOC_VFIFO_COUNT != 0)) +#define DEBUG_CONSOLE_IO_VUSART +#endif + +/* If none of above io is supported, enable the swo for debug console, or swo can be enabled by define + * DEBUG_CONSOLE_IO_SWO directly */ +#if (!defined(DEBUG_CONSOLE_IO_SWO) && !defined(DEBUG_CONSOLE_IO_UART) && !defined(DEBUG_CONSOLE_IO_IUART) && \ +!defined(DEBUG_CONSOLE_IO_LPUART) && \ + !defined(DEBUG_CONSOLE_IO_LPSCI) && !defined(DEBUG_CONSOLE_IO_USBCDC) && \ +!defined(DEBUG_CONSOLE_IO_FLEXCOMM) && \ + !defined(DEBUG_CONSOLE_IO_VUSART)) +#define DEBUG_CONSOLE_IO_SWO +#endif + +/* configuration for debug console device */ +/* If new device is required as the low level device for debug console, + * Add the #elif branch and add the preprocessor macro to judge whether + * this kind of device exist in this SOC. */ +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) +#include "fsl_uart.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static uart_handle_t s_ioUartHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */ + +#if defined DEBUG_CONSOLE_IO_LPUART +#include "fsl_lpuart.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static lpuart_handle_t s_ioLpuartHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_IO_LPUART */ + +#if defined DEBUG_CONSOLE_IO_LPSCI +#include "fsl_lpsci.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static lpsci_handle_t s_ioLpsciHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_IO_LPSCI */ + +#if defined DEBUG_CONSOLE_IO_USBCDC +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device_cdc_acm.h" +#include "usb_device_ch9.h" +#include "virtual_com.h" +#endif /* DEBUG_CONSOLE_IO_USBCDC */ + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) +#include "fsl_usart.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static usart_handle_t s_ioUsartHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */ + +#if defined DEBUG_CONSOLE_IO_SWO +#include "fsl_swo.h" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console IO state information. */ +static io_state_t s_debugConsoleIO = { + .ioBase = NULL, + .ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE, +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + .callBack = NULL, +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) +static void UART_Callback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_UART_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_UART_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */ + +#if defined DEBUG_CONSOLE_IO_LPSCI +static void LPSCI_Callback(UART0_Type *base, lpsci_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_LPSCI_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_LPSCI_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* DEBUG_CONSOLE_IO_LPSCI */ + +#if defined DEBUG_CONSOLE_IO_LPUART +static void LPUART_Callback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_LPUART_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_LPUART_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* DEBUG_CONSOLE_IO_LPUART */ + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) +static void USART_Callback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_USART_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_USART_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */ +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer) +{ + assert(NULL != io); + + /* record device type/base */ + s_debugConsoleIO.ioType = io->ioType; + s_debugConsoleIO.ioBase = (void *)(io->ioBase); + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + uart_config_t uart_config; + UART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + UART_Init((UART_Type *)s_debugConsoleIO.ioBase, &uart_config, clkSrcFreq); + UART_EnableTx(s_debugConsoleIO.ioBase, true); + UART_EnableRx(s_debugConsoleIO.ioBase, true); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + UART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUartHandler, UART_Callback, NULL); + /* start ring buffer */ + UART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + lpuart_config_t lpuart_config; + LPUART_GetDefaultConfig(&lpuart_config); + lpuart_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + LPUART_Init((LPUART_Type *)s_debugConsoleIO.ioBase, &lpuart_config, clkSrcFreq); + LPUART_EnableTx(s_debugConsoleIO.ioBase, true); + LPUART_EnableRx(s_debugConsoleIO.ioBase, true); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + LPUART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, LPUART_Callback, NULL); + /* start ring buffer */ + LPUART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + lpsci_config_t lpsci_config; + LPSCI_GetDefaultConfig(&lpsci_config); + lpsci_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + LPSCI_Init((UART0_Type *)s_debugConsoleIO.ioBase, &lpsci_config, clkSrcFreq); + LPSCI_EnableTx(s_debugConsoleIO.ioBase, true); + LPSCI_EnableRx(s_debugConsoleIO.ioBase, true); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + LPSCI_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, LPSCI_Callback, NULL); + /* start ring buffer */ + LPSCI_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + { + s_debugConsoleIO.ioBase = USB_VcomInit(); + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_FLEXCOMM + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + { + usart_config_t usart_config; + USART_GetDefaultConfig(&usart_config); + usart_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL); + /* start ring buffer */ + USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_VUSART + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + usart_config_t usart_config; + USART_GetDefaultConfig(&usart_config); + usart_config.baudRate_Bps = baudRate; + usart_config.enableRx = true; + usart_config.enableTx = true; + /* Enable rx fifo for user's continously input */ + usart_config.fifoConfig.enableRxFifo = true; + usart_config.fifoConfig.rxFifoSize = 8; + /* Enable clock and initial UART module follow user configure structure. */ + USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL); + /* start ring buffer */ + USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + SWO_Init((uint32_t)s_debugConsoleIO.ioBase, baudRate, clkSrcFreq); + break; +#endif + default: + break; + } +} + +status_t IO_Deinit(void) +{ + if (s_debugConsoleIO.ioType == DEBUG_CONSOLE_DEVICE_TYPE_NONE) + { + return kStatus_Success; + } + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + UART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler); +#endif + /* Disable UART module. */ + UART_Deinit((UART_Type *)s_debugConsoleIO.ioBase); + + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + LPSCI_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler); +#endif + /* Disable LPSCI module. */ + LPSCI_Deinit((UART0_Type *)s_debugConsoleIO.ioBase); + + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + LPUART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler); +#endif + /* Disable LPUART module. */ + LPUART_Deinit((LPUART_Type *)s_debugConsoleIO.ioBase); + + break; +#endif +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + /* Disable USBCDC module. */ + USB_VcomDeinit(s_debugConsoleIO.ioBase); + break; +#endif +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + USART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler); +#endif + /* deinit IO */ + USART_Deinit((USART_Type *)s_debugConsoleIO.ioBase); + + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + SWO_Deinit((uint32_t)s_debugConsoleIO.ioBase); + break; +#endif + default: + s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE; + break; + } + + s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE; + + return kStatus_Success; +} + +status_t IO_WaitIdle(void) +{ + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + /* wait transfer complete flag */ + while (!(UART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUART_TransmissionCompleteFlag)) + { + } + + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + /* wait transfer complete flag */ + while (!(UART_GetStatusFlag(s_debugConsoleIO.ioBase, kUART_TxCompleteFlag))) + { + } + + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + /* wait transfer complete flag */ + while (!(LPSCI_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPSCI_TransmissionCompleteFlag)) + { + } + + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + /* wait transfer complete flag */ + while (!(LPUART_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPUART_TransmissionCompleteFlag)) + { + } + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + /* wait transfer complete flag */ + while (!(USART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUSART_TxFifoEmptyFlag)) + { + } + break; +#endif + default: + break; + } + + return kStatus_Success; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + +status_t IO_Transfer(uint8_t *ch, size_t size, bool tx) +{ + status_t status = kStatus_Fail; + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + uart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = UART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer); + } + else + { + status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL); + } + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + lpsci_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = LPSCI_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer); + } + else + { + status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + lpuart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = LPUART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer); + } + else + { + status = + LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + { + if (tx) + { + USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + usart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = USART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer); + } + else + { + status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + status = SWO_SendBlocking((uint32_t)s_debugConsoleIO.ioBase, ch, size); + break; +#endif + default: + break; + } + + return status; +} + +status_t IO_TryReceiveCharacter(uint8_t *ch) +{ + status_t status = kStatus_Fail; + uint32_t size = 1U; + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + uart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (UART_TransferGetRxRingBufferLength(&s_ioUartHandler) >= size) + { + /* transfer data */ + status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL); + } + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + lpsci_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (LPSCI_TransferGetRxRingBufferLength(&s_ioLpsciHandler) >= size) + { + /* transfer data */ + status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + lpuart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (LPUART_TransferGetRxRingBufferLength(s_debugConsoleIO.ioBase, &s_ioLpuartHandler) >= size) + { + /* transfer data */ + status = + LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + usart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (USART_TransferGetRxRingBufferLength(&s_ioUsartHandler) >= size) + { + /* transfer data */ + status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL); + } + } + break; +#endif + default: + break; + } + + return status; +} + +#else + +status_t IO_Transfer(uint8_t *ch, size_t size, bool tx) +{ + status_t status = kStatus_Success; + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + if (tx) + { + UART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = UART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + if (tx) + { + LPSCI_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = LPSCI_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + if (tx) + { + LPUART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = LPUART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + { + if (tx) + { + USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + if (tx) + { + USART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = USART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + status = SWO_SendBlocking((uint32_t)s_debugConsoleIO.ioBase, ch, size); + break; +#endif + default: + status = kStatus_Fail; + break; + } + + return status; +} + +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/fsl_io.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/fsl_io.h new file mode 100644 index 0000000000..396f66c70f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/fsl_io.h @@ -0,0 +1,140 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_IO_H +#define _FSL_IO_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief define a notify callback for IO +* @param size , transfer data size. +* @param rx, indicate a rx transfer is success. +* @param tx, indicate a tx transfer is success. +*/ +typedef void (*notify)(size_t *size, bool rx, bool tx); + +/*! @brief State structure storing io. */ +typedef struct io_State +{ + void *ioBase; /*!< Base of the IP register. */ + uint8_t ioType; /*!< device type */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + notify callBack; /*!< define the callback function for buffer */ +#endif + +} io_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief io init function. + * + * Call this function to init IO. + * + * @param io configuration pointer + * @param baudRate baud rate + * @param clkSrcFreq clock freq + * @param ringbuffer used to receive character + */ +void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer); + +/*! + * @brief Deinit IO. + * + * Call this function to Deinit IO. + * + * @return deinit status + */ +status_t IO_Deinit(void); + +/*! + * @brief io transfer function. + * + * Call this function to transfer log. + * Print log: + * @code + * IO_Transfer(ch, size, true); + * @endcode + * Scanf log: + * @code + * IO_Transfer(ch, size, false); + * @endcode + * + * @param ch transfer buffer pointer + * @param size transfer size + * @param tx indicate the transfer is TX or RX + */ +status_t IO_Transfer(uint8_t *ch, size_t size, bool tx); + +/*! + * @brief io wait idle. + * + * Call this function to wait the io idle + * + * @return Indicates whether wait idle was successful or not. + */ +status_t IO_WaitIdle(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief io try to receive one character. + * + * Call this function try to receive character + * @param ch the address of char to receive + * @return Indicates try getchar was successful or not. + */ +status_t IO_TryReceiveCharacter(uint8_t *ch); +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_IO_H */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/swo/fsl_swo.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/swo/fsl_swo.c new file mode 100644 index 0000000000..c1360a2c9f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/swo/fsl_swo.c @@ -0,0 +1,121 @@ +/* + * The Clear BSD License + * Copyright 2018 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "fsl_swo.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* SWO encoding protocol definition */ +#ifndef FSL_DEBUG_CONSOLE_SWO_PROTOCOL +#define FSL_DEBUG_CONSOLE_SWO_PROTOCOL kSWO_ProtocolNrz +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq) +{ + assert(baudRate <= clkSrcFreq); + assert((clkSrcFreq / baudRate) <= TPI_ACPR_PRESCALER_Msk); + assert((TPI->DEVID & (kSWO_ProtocolNrz | kSWO_ProtocolManchester)) != 0U); + + uint32_t prescaler = clkSrcFreq / baudRate - 1U; + + /* enable the ITM and DWT units */ + CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; + + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) == 0U) + { + return kStatus_Fail; + } + /* Lock access */ + ITM->LAR = 0xC5ACCE55U; + /* Disable ITM */ + ITM->TER &= ~(1U << port); + ITM->TCR = 0U; + /* select SWO encoding protocol */ + TPI->SPPR = FSL_DEBUG_CONSOLE_SWO_PROTOCOL; + /* select asynchronous clock prescaler */ + TPI->ACPR = prescaler & 0xFFFFU; + /* allow unprivilege access */ + ITM->TPR = 0U; + /* enable ITM */ + ITM->TCR = + ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_DWTENA_Msk; + /* enable the port bits */ + ITM->TER = 1U << port; + + return kStatus_Success; +} + +void SWO_Deinit(uint32_t port) +{ + /* disable ITM */ + ITM->TER &= ~(1U << port); +} + +status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size) +{ + assert(ch != NULL); + assert((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0U); + assert((ITM->TER & (1U << port)) != 0U); + + uint16_t *strAddr = (uint16_t *)ch; + + while (size) + { + /* wait FIFO ready */ + while (ITM->PORT[port].u32 == 0U) + { + } + + if (size >= 2U) + { + size -= 2U; + ITM->PORT[port].u16 = *strAddr; + } + else + { + size -= 1U; + ITM->PORT[port].u8 = *((uint8_t *)strAddr); + } + strAddr++; + } + + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/swo/fsl_swo.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/swo/fsl_swo.h new file mode 100644 index 0000000000..94cd651682 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/io/swo/fsl_swo.h @@ -0,0 +1,101 @@ +/* + * The Clear BSD License + * Copyright 2018 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_SWO_H_ +#define _FSL_SWO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* swo protocol */ +enum _swo_protocol +{ + kSWO_ProtocolManchester = 1U, /*!< SWO manchester protocol */ + kSWO_ProtocolNrz = 2U, /*!< SWO UART/NRZ protocol */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief io init function. + * + * Call this function to init SWO. + * + * @param port port used to transfer data + * @param baudRate SWO clock + * @param clkSrcFreq core clock frequency + */ +status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq); + +/*! + * @brief Deinit IO. + * + * Call this function to Deinit SWO. + * + * @param port port to deinit. + * @return deinit status + */ +void SWO_Deinit(uint32_t port); + +/*! + * @brief io transfer function. + * + * Call this function to print log. + * + * @param port port used to transfer data + * @param ch transfer buffer pointer + * @param size transfer size + */ +status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_SWO_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/log/fsl_log.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/log/fsl_log.c new file mode 100644 index 0000000000..e36832d36d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/log/fsl_log.c @@ -0,0 +1,587 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "fsl_log.h" +#include "fsl_debug_console_conf.h" +#include "fsl_io.h" +#ifdef FSL_RTOS_FREE_RTOS +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef BACKSPACE +/*! @brief character backspace ASCII value */ +#define BACKSPACE 127 +#endif + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief increase pop member */ +#define LOG_CHECK_BUFFER_INDEX_OVERFLOW(index) \ + { \ + if (index >= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN) \ + { \ + index -= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; \ + } \ + \ +\ +} + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +#else +#define IS_RUNNING_IN_ISR() (0U) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* define for rtos */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +/* metex semaphore */ +#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) (mutex = xSemaphoreCreateMutex()) + +#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) \ + \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + xSemaphoreGive(mutex); \ + } \ + \ +} + +#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ + \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ + \ +} + +#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ + \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ + \ +} + +/* Binary semaphore */ +#define LOG_CREATE_BINARY_SEMAPHORE(binary) (binary = xSemaphoreCreateBinary()) +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (xSemaphoreTake(binary, portMAX_DELAY)) +#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (xSemaphoreGiveFromISR(binary, NULL)) + +#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) +#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) +#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) +#define LOG_CREATE_BINARY_SEMAPHORE(binary) +#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + \ +{ \ + while (!binary) \ + ; \ + binary = false; \ + \ +\ +} +#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true) +#else +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) +#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* add other implementation here +*such as : +* #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_xxx) +*/ + +#else + +#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) +#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) +#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) +#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) +#define LOG_CREATE_BINARY_SEMAPHORE(binary) +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief Define the buffer +* The total buffer size should be calucate as (BUFFER_SUPPORT_LOG_LENGTH + 1) * BUFFER_SUPPORT_LOG_NUM * 4 +*/ +typedef struct _log_buffer +{ + volatile uint16_t totalIndex; /*!< indicate the total usage of the buffer */ + volatile uint16_t pushIndex; /*!< indicate the next push index */ + volatile uint16_t popIndex; /*!< indicate the pop index */ + uint8_t txBuf[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; /*!< buffer to store printf log */ + + uint8_t rxBuf[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; /*!< buffer to store scanf log */ +} log_buffer_t; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* A global log buffer */ +static log_buffer_t s_log_buffer; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static SemaphoreHandle_t s_logPushSemaphore = NULL; +static SemaphoreHandle_t s_logReadSemaphore = NULL; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +static SemaphoreHandle_t s_logPopSemaphore = NULL; +static SemaphoreHandle_t s_logReadWaitSemaphore = NULL; + +#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + +static volatile bool s_logReadWaitSemaphore = false; /* transferred event from ISR for bare-metal + interrupt */ + +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +#else +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/******************************************************************************* +* Prototypes +******************************************************************************/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief callback function for IO layer to notify LOG + * + * @param size last transfer data size + * @param receive indicate a RX transfer + * @param transmit indicate a TX transfer + * + */ +static void LOG_Transferred(size_t *size, bool receive, bool transmit); + +/*! + * @brief log push function + * + * @param buf target buffer + * @param size log size + * + */ +static int LOG_BufPush(uint8_t *buf, size_t size); + +/*! + * @brief Get next avaliable log + * + * @param next avaliable size + * @return next avaliable address + */ +static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size); + +/*! + * @brief buf pop + * + * @param size log size popped and next available log size + * @return next avaliable address + */ +static uint8_t *LOG_BufPop(size_t *size); + +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*! + * @brief read one character + * + * @param ch character address + * @return indicate the read status + * + */ +static status_t LOG_ReadOneCharacter(uint8_t *ch); + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +/*! + * @brief echo one character + * + * @param ch character address + * @param isGetchar flag to distinguish getchar from scanf + * @param index special for scanf to support backspace + * @return indicate the read status + * + */ +static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index); +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq) +{ + io_state_t io; + /* init io */ + io.ioBase = (void *)baseAddr; + io.ioType = device; + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* memset the global queue */ + memset(&s_log_buffer, 0U, sizeof(s_log_buffer)); + /* init callback for NON-BLOCKING */ + io.callBack = LOG_Transferred; + /* io init function */ + IO_Init(&io, baudRate, clkSrcFreq, s_log_buffer.rxBuf); + /* Debug console buffer push lock create */ + LOG_CREATE_MUTEX_SEMAPHORE(s_logPushSemaphore); + /* Debug console get/scanf mutex lock create */ + LOG_CREATE_MUTEX_SEMAPHORE(s_logReadSemaphore); +#else + IO_Init(&io, baudRate, clkSrcFreq, NULL); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + /* Debug console lock create */ + LOG_CREATE_MUTEX_SEMAPHORE(s_logPopSemaphore); + LOG_CREATE_BINARY_SEMAPHORE(s_logReadWaitSemaphore); + + return kStatus_Success; +} + +void LOG_Deinit(void) +{ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* memset the global queue */ + memset(&s_log_buffer, 0U, sizeof(s_log_buffer)); +#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/ + /* Deinit IO */ + IO_Deinit(); +} + +status_t LOG_WaitIdle(void) +{ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* wait buffer empty */ + while (!(s_log_buffer.totalIndex == 0U)) + ; +#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/ + /* wait IO idle */ + IO_WaitIdle(); + + return kStatus_Success; +} + +int LOG_Push(uint8_t *buf, size_t size) +{ + assert(buf != NULL); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* push to buffer */ + LOG_BufPush(buf, size); + buf = LOG_BufGetNextAvaliableLog(&size); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + /* pop log */ + return LOG_Pop(buf, size); +} + +int LOG_Pop(uint8_t *buf, size_t size) +{ + uint8_t getLock = 0U; + + if ((0 != size) && (NULL != buf)) + { + /* take POP lock, should be non-blocking */ + LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(s_logPopSemaphore, getLock); + + if (getLock) + { + /* call IO transfer function */ + if (IO_Transfer(buf, size, true) != kStatus_Success) + { + size = 0U; + } + /* release POP lock */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logPopSemaphore); + } + } + + return size; +} + +int LOG_ReadLine(uint8_t *buf, size_t size) +{ + assert(buf != NULL); + + int i = 0; + + /* take mutex lock function */ + LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logReadSemaphore); + + for (i = 0; i < size; i++) + { + /* recieve one char every time */ + if (LOG_ReadOneCharacter(&buf[i]) != kStatus_Success) + { + return -1; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + LOG_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if ((buf[i] == '\r') || (buf[i] == '\n')) + { + /* End of Line. */ + if (i == 0) + { + buf[i] = '\0'; + i = -1; + } + else + { + break; + } + } + } + /* get char should not add '\0'*/ + if (i == size) + { + buf[i] = '\0'; + } + else + { + buf[i + 1] = '\0'; + } + + /* release mutex lock function */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logReadSemaphore); + + return i; +} + +int LOG_ReadCharacter(uint8_t *ch) +{ + assert(ch != NULL); + int ret = 0; + + /* take mutex lock function */ + LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logReadSemaphore); + /* read one character */ + if (LOG_ReadOneCharacter(ch) == kStatus_Success) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + LOG_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logReadSemaphore); + + return ret; +} + +static status_t LOG_ReadOneCharacter(uint8_t *ch) +{ + /* recieve one char every time */ + if (IO_Transfer(ch, 1U, false) != kStatus_Success) + { + return kStatus_Fail; + } + + /* wait release from ISR */ + LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(s_logReadWaitSemaphore); + + return kStatus_Success; +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != '\r') && (*ch != '\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (IO_Transfer(ch, 1U, true) != kStatus_Success) + { + return kStatus_Fail; + } + } + + if (!isGetChar) + { + if ((*index > 0) && (*ch == BACKSPACE)) + { + *index -= 2; + } + } + + return kStatus_Success; +} +#endif + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static int LOG_BufPush(uint8_t *buf, size_t size) +{ + uint32_t pushIndex = 0U, i = 0U; + bool pushAvaliable = false; + + /* take mutex lock function */ + LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore); + if (size <= (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - s_log_buffer.totalIndex)) + { + /* get push index */ + pushIndex = s_log_buffer.pushIndex; + s_log_buffer.pushIndex += size; + /* check index overflow */ + LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.pushIndex); + /* update push/total index value */ + s_log_buffer.totalIndex += size; + pushAvaliable = true; + } + /* release mutex lock function */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore); + + /* check the buffer if have enough space to store the log */ + if (pushAvaliable) + { + for (i = size; i > 0; i--) + { + /* copy log to buffer, the buffer only support a fixed length argument, if the log argument + is longer than the fixed length, the left argument will be losed */ + s_log_buffer.txBuf[pushIndex] = *buf++; + /* increase index */ + pushIndex++; + /* check index overflow */ + LOG_CHECK_BUFFER_INDEX_OVERFLOW(pushIndex); + } + } + else + { + size = 0U; + } + + return size; +} + +static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size) +{ + uint16_t popIndex = s_log_buffer.popIndex; + + /* get avaliable size */ + if (s_log_buffer.totalIndex > (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex)) + { + *size = (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex); + } + else + { + *size = s_log_buffer.totalIndex; + } + + /* return address */ + return (&(s_log_buffer.txBuf[popIndex])); +} + +static uint8_t *LOG_BufPop(size_t *size) +{ + if (s_log_buffer.totalIndex >= *size) + { + /* decrease the log total member */ + s_log_buffer.totalIndex -= *size; + /* there is more log in the queue to be pushed */ + if (s_log_buffer.totalIndex > 0U) + { + /* update the pop index */ + s_log_buffer.popIndex += *size; + /* check index overflow */ + LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.popIndex); + + return LOG_BufGetNextAvaliableLog(size); + } + else + { + /* reset push and pop */ + s_log_buffer.popIndex = 0U; + s_log_buffer.pushIndex = 0U; + *size = 0U; + } + } + + return NULL; +} + +static void LOG_Transferred(size_t *size, bool receive, bool transmit) +{ + uint8_t *addr = NULL; + + if (transmit) + { + addr = LOG_BufPop(size); + /* continue pop log from buffer */ + LOG_Pop(addr, *size); + } + + if (receive) + { + /* release from ISR */ + LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_logReadWaitSemaphore); + } +} +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t LOG_TryReadCharacter(uint8_t *ch) +{ + if (NULL != ch) + { + return IO_TryReceiveCharacter(ch); + } + return kStatus_Fail; +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/log/fsl_log.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/log/fsl_log.h new file mode 100644 index 0000000000..87f4c8a7b8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/log/fsl_log.h @@ -0,0 +1,146 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_LOG_H +#define _FSL_LOG_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/************************************************************************************************* + * Prototypes + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Initializes + * + * Call this function to init the buffer + * @param baseAddr, device base address + * @param device, device type + * @param baudRate, device communicate baudrate + * @param clkSrcFreq, device source clock freq + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + * @retval kStatus_Fail Execution failure + */ +status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq); + +/*! + * @brief De-Initializes + * + * Call this function to deinit the buffer + * + * @return Indicates whether Deinit was successful or not. + */ +void LOG_Deinit(void); + +/*! + * @brief log push interface + * + * Call this function to print log + * @param fmt, buffer pointer + * @param size, avaliable size + * @return indicate the push size + * @retval-1 indicate buffer is full or transfer fail. + * @retval size return the push log size. + */ +int LOG_Push(uint8_t *buf, size_t size); + +/*! + * @brief log read one line function + * + * Call this function to print log + * @param fmt, buffer pointer + * @param size, avaliable size + * @reutrn the number of the recieved character + */ +int LOG_ReadLine(uint8_t *buf, size_t size); + +/*! + * @brief log read one character function + * + * Call this function to GETCHAR + * @param ch receive address + * @reutrn the number of the recieved character + */ +int LOG_ReadCharacter(uint8_t *ch); + +/*! + * @brief wait log and io idle + * + * Call this function to wait log buffer empty and io idle before enter low power mode. + * @return Indicates whether wait idle was successful or not. + */ +status_t LOG_WaitIdle(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief log try read one character + * Call this function to check character avaliable or not, if not return fail, otherwise return it. + * @param ch the address of char to receive + * @return Indicates try getchar was successful or not. + */ +status_t LOG_TryReadCharacter(uint8_t *ch); +#endif + +/*! + * @brief log pop function + * + * Call this function to pop log from buffer. + * @param buf buffer address to pop + * @param size log size to pop + * @return pop log size. + */ +int LOG_Pop(uint8_t *buf, size_t size); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/str/fsl_str.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/str/fsl_str.c new file mode 100644 index 0000000000..d34e41a3ad --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/str/fsl_str.c @@ -0,0 +1,1327 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include +#include +#include +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#if SCANF_FLOAT_ENABLE +static double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if PRINTF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! +* + */ +double modf(double input_dbl, double *intpart_ptr); + +/*************Code for process formatted data*******************************/ + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint8_t count = 0; + uint8_t c; + + c = **s; + while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + int64_t a; + int64_t b; + int64_t c; + + uint64_t ua; + uint64_t ub; + uint64_t uc; +#else + int32_t a; + int32_t b; + int32_t c; + + uint32_t ua; + uint32_t ub; + uint32_t uc; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + + if (neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(int64_t *)nump; +#else + a = *(int32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (int64_t)a / (int64_t)radix; + c = (int64_t)a - ((int64_t)b * (int64_t)radix); + if (c < 0) + { + uc = (uint64_t)c; + c = (int64_t)(~uc) + 1 + '0'; + } +#else + b = a / radix; + c = a - (b * radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (uint32_t)(~uc) + 1 + '0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else + { +#if PRINTF_ADVANCED_ENABLE + ua = *(uint64_t *)nump; +#else + ua = *(uint32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0) + { +#if PRINTF_ADVANCED_ENABLE + ub = (uint64_t)ua / (uint64_t)radix; + uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); +#else + ub = ua / (uint32_t)radix; + uc = ua - (ub * (uint32_t)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10) + { + uc = uc + '0'; + } + else + { + uc = uc - 10 + (use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (!r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < precision_width; i++) + { + fractpart *= radix; + } + if (r >= 0) + { + fa = fractpart + (double)0.5; + if (fa >= pow(10, precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow(10, precision_width)) + { + intpart--; + } + } + for (i = 0; i < precision_width; i++) + { + fb = fa / (int32_t)radix; + dc = (fa - (int64_t)fb * (int32_t)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + char *p; + int32_t c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t done; + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + int32_t schar, dschar; + int64_t ival; + uint64_t uval = 0; + bool valid_precision_width; +#else + int32_t ival; + uint32_t uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + for (p = (char *)fmt; (c = *p) != 0; p++) + { + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = 0; + done = false; + while (!done) + { + switch (*++p) + { + case '-': + flags_used |= kPRINTF_Minus; + break; + case '+': + flags_used |= kPRINTF_Plus; + break; + case ' ': + flags_used |= kPRINTF_Space; + break; + case '0': + flags_used |= kPRINTF_Zero; + break; + case '#': + flags_used |= kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + field_width = (field_width * 10) + (c - '0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + field_width = (uint32_t)va_arg(ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + /* Next check for the width and precision field separator. */ + precision_width = 6; +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = false; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10) + (c - '0'); +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = true; +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(ap, uint32_t); + valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } +#if PRINTF_ADVANCED_ENABLE + /* + * Check for the length modifier. + */ + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + /* Now we're ready to examine the format. */ + c = *++p; + { + if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || + (c == 'b') || (c == 'p') || (c == 'u')) + { + if ((c == 'd') || (c == 'i')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + ival = (int64_t)va_arg(ap, int64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int32_t)va_arg(ap, int32_t); + } + vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (ival < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + /* Do the ZERO pad. */ + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + /* The string was built in reverse order, now display in correct order. */ + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + +#if PRINTF_FLOAT_ENABLE + if ((c == 'f') || (c == 'F')) + { + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + if (fval < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#endif /* PRINTF_FLOAT_ENABLE */ + if ((c == 'X') || (c == 'x')) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + if (flags_used & kPRINTF_Pound) + { + vlen += 2; + } + cb(buf, &count, ' ', field_width - vlen); + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + } + } + + if ((flags_used & kPRINTF_Pound) && (!dschar)) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + vlen += 2; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + + if (c == 'o') + { + radix = 8; + } + else if (c == 'b') + { + radix = 2; + } + else if (c == 'p') + { + radix = 16; + } + else + { + radix = 10; + } + + vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Zero) + { + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if !PRINTF_ADVANCED_ENABLE + cb(buf, &count, ' ', field_width - vlen); +#endif /* !PRINTF_ADVANCED_ENABLE */ + if (vstrp != NULL) + { + while (*vstrp) + { + cb(buf, &count, *vstrp--, 1); + } + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + else if (c == 'c') + { + cval = (char)va_arg(ap, uint32_t); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = precision_width; + } + else + { + vlen = strlen(sval); + } +#else + vlen = strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (!(flags_used & kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', field_width - vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while ((*sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while (*sval) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + } + + return count; +} + +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char temp; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + const char *s; + /* Identifier for the input string. */ + const char *p = line_ptr; + + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while ((*c) && (*p)) + { + /* Ignore all white-spaces in the format strings. */ + if (ScanIgnoreWhiteSpace((const char **)&c)) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = 0; + base = 0; + + /* Loop to get full conversion specification. */ + while ((*c) && (!(flag & kSCANF_DestMask))) + { + switch (*c) + { +#if SCANF_ADVANCED_ENABLE + case '*': + if (flag & kSCANF_Suppress) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_Suppress; + c++; + break; + case 'h': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'h') + { + flag |= kSCANF_LengthChar; + c++; + } + else + { + flag |= kSCANF_LengthShortInt; + } + c++; + break; + case 'l': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'l') + { + flag |= kSCANF_LengthLongLongInt; + c++; + } + else + { + flag |= kSCANF_LengthLongInt; + } + c++; + break; +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + case 'L': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_LengthLongLongDouble; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (field_width) + { + /* Match failure. */ + return nassigned; + } + do + { + field_width = field_width * 10 + *c - '0'; + c++; + } while ((*c >= '0') && (*c <= '9')); + break; + case 'd': + base = 10; + flag |= kSCANF_TypeSinged; + flag |= kSCANF_DestInt; + c++; + break; + case 'u': + base = 10; + flag |= kSCANF_DestInt; + c++; + break; + case 'o': + base = 8; + flag |= kSCANF_DestInt; + c++; + break; + case 'x': + case 'X': + base = 16; + flag |= kSCANF_DestInt; + c++; + break; + case 'i': + base = 0; + flag |= kSCANF_DestInt; + c++; + break; +#if SCANF_FLOAT_ENABLE + case 'a': + case 'A': + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + flag |= kSCANF_DestFloat; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case 'c': + flag |= kSCANF_DestChar; + if (!field_width) + { + field_width = 1; + } + c++; + break; + case 's': + flag |= kSCANF_DestString; + c++; + break; + default: + return nassigned; + } + } + + if (!(flag & kSCANF_DestMask)) + { + /* Format strings are exhausted. */ + return nassigned; + } + + if (!field_width) + { + /* Large than length of a line. */ + field_width = 99; + } + + /* Matching strings in input streams and assign to argument. */ + switch (flag & kSCANF_DestMask) + { + case kSCANF_DestChar: + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p)) + { + if (!(flag & kSCANF_Suppress)) + { + *buf++ = *p++; + } + else + { + p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + nassigned++; + } + break; + case kSCANF_DestString: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && + (*p != '\r') && (*p != '\v') && (*p != '\f')) + { + if (flag & kSCANF_Suppress) + { + p++; + } + else + { + *buf++ = *p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + break; + case kSCANF_DestInt: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + if ((base == 0) || (base == 16)) + { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) + { + base = 16; + if (field_width >= 1) + { + p += 2; + n_decode += 2; + field_width -= 2; + } + } + } + + if (base == 0) + { + if (s[0] == '0') + { + base = 8; + } + else + { + base = 10; + } + } + + neg = 1; + switch (*p) + { + case '-': + neg = -1; + n_decode++; + p++; + field_width--; + break; + case '+': + neg = 1; + n_decode++; + p++; + field_width--; + break; + default: + break; + } + + while ((*p) && (field_width--)) + { + if ((*p <= '9') && (*p >= '0')) + { + temp = *p - '0'; + } + else if ((*p <= 'f') && (*p >= 'a')) + { + temp = *p - 'a' + 10; + } + else if ((*p <= 'F') && (*p >= 'A')) + { + temp = *p - 'A' + 10; + } + else + { + temp = base; + } + + if (temp >= base) + { + break; + } + else + { + val = base * val + temp; + } + p++; + n_decode++; + } + val *= neg; + if (!(flag & kSCANF_Suppress)) + { +#if SCANF_ADVANCED_ENABLE + switch (flag & kSCANF_LengthMask) + { + case kSCANF_LengthChar: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case kSCANF_LengthShortInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case kSCANF_LengthLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case kSCANF_LengthLongLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + nassigned++; + } + break; +#if SCANF_FLOAT_ENABLE + case kSCANF_DestFloat: + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = strtod(p, (char **)&s); + + if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) + { + break; + } + + n_decode += (int)(s) - (int)(p); + p = s; + if (!(flag & kSCANF_Suppress)) + { + if (flag & kSCANF_LengthLongLongDouble) + { + *va_arg(args_ptr, double *) = fnum; + } + else + { + *va_arg(args_ptr, float *) = (float)fnum; + } + nassigned++; + } + break; +#endif /* SCANF_FLOAT_ENABLE */ + default: + return nassigned; + } + } + } + return nassigned; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/str/fsl_str.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/str/fsl_str.h new file mode 100644 index 0000000000..47d835edf9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/str/fsl_str.h @@ -0,0 +1,92 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt_ptr Format string for printf. + * @param[in] args_ptr Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_cdc_acm.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_cdc_acm.c new file mode 100644 index 0000000000..f669248848 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_cdc_acm.c @@ -0,0 +1,42 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device.h" + +#if USB_DEVICE_CONFIG_CDC_ACM +#include "usb_device_cdc_acm.h" + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_cdc_acm.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_cdc_acm.h new file mode 100644 index 0000000000..20f1faff86 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_cdc_acm.h @@ -0,0 +1,112 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CDC_ACM_H_ +#define _USB_DEVICE_CDC_ACM_H_ 1 +/******************************************************************************* +* Definitions +******************************************************************************/ + +#define USB_DEVICE_CONFIG_CDC_ACM_MAX_INSTANCE (1) + +#define USB_DEVICE_CONFIG_CDC_COMM_CLASS_CODE (0x02) +#define USB_DEVICE_CONFIG_CDC_DATA_CLASS_CODE (0x0A) + +/* Class specific request Codes */ +#define USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND (0x00) +#define USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE (0x01) +#define USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE (0x02) +#define USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE (0x03) +#define USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE (0x04) +#define USB_DEVICE_CDC_REQUEST_SET_AUX_LINE_STATE (0x10) +#define USB_DEVICE_CDC_REQUEST_SET_HOOK_STATE (0x11) +#define USB_DEVICE_CDC_REQUEST_PULSE_SETUP (0x12) +#define USB_DEVICE_CDC_REQUEST_SEND_PULSE (0x13) +#define USB_DEVICE_CDC_REQUEST_SET_PULSE_TIME (0x14) +#define USB_DEVICE_CDC_REQUEST_RING_AUX_JACK (0x15) +#define USB_DEVICE_CDC_REQUEST_SET_LINE_CODING (0x20) +#define USB_DEVICE_CDC_REQUEST_GET_LINE_CODING (0x21) +#define USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE (0x22) +#define USB_DEVICE_CDC_REQUEST_SEND_BREAK (0x23) +#define USB_DEVICE_CDC_REQUEST_SET_RINGER_PARAMS (0x30) +#define USB_DEVICE_CDC_REQUEST_GET_RINGER_PARAMS (0x31) +#define USB_DEVICE_CDC_REQUEST_SET_OPERATION_PARAM (0x32) +#define USB_DEVICE_CDC_REQUEST_GET_OPERATION_PARAM (0x33) +#define USB_DEVICE_CDC_REQUEST_SET_LINE_PARAMS (0x34) +#define USB_DEVICE_CDC_REQUEST_GET_LINE_PARAMS (0x35) +#define USB_DEVICE_CDC_REQUEST_DIAL_DIGITS (0x36) +#define USB_DEVICE_CDC_REQUEST_SET_UNIT_PARAMETER (0x37) +#define USB_DEVICE_CDC_REQUEST_GET_UNIT_PARAMETER (0x38) +#define USB_DEVICE_CDC_REQUEST_CLEAR_UNIT_PARAMETER (0x39) +#define USB_DEVICE_CDC_REQUEST_GET_PROFILE (0x3A) +#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS (0x40) +#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_POW_PATTER_FILTER (0x41) +#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_POW_PATTER_FILTER (0x42) +#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_PACKET_FILTER (0x43) +#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_STATISTIC (0x44) +#define USB_DEVICE_CDC_REQUEST_SET_ATM_DATA_FORMAT (0x50) +#define USB_DEVICE_CDC_REQUEST_GET_ATM_DEVICE_STATISTICS (0x51) +#define USB_DEVICE_CDC_REQUEST_SET_ATM_DEFAULT_VC (0x52) +#define USB_DEVICE_CDC_REQUEST_GET_ATM_VC_STATISTICS (0x53) +#define USB_DEVICE_CDC_REQUEST_MDLM_SPECIFIC_REQUESTS_MASK (0x7F) + +#define USB_DEVICE_CDC_REQUEST_GET_ABSTRACT_STATE (0x23) +#define USB_DEVICE_CDC_REQUEST_GET_COUNTRY_SETTING (0x24) +#define USB_DEVICE_CDC_REQUEST_SET_ABSTRACT_STATE (0x25) +#define USB_DEVICE_CDC_REQUEST_SET_COUNTRY_SETTING (0x26) +/* Class Specific Notification Codes */ +#define USB_DEVICE_CDC_REQUEST_NETWORK_CONNECTION_NOTIF (0x00) +#define USB_DEVICE_CDC_REQUEST_RESPONSE_AVAIL_NOTIF (0x01) +#define USB_DEVICE_CDC_REQUEST_AUX_JACK_HOOK_STATE_NOTIF (0x08) +#define USB_DEVICE_CDC_REQUEST_RING_DETECT_NOTIF (0x09) +#define USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF (0x20) +#define USB_DEVICE_CDC_REQUEST_CALL_STATE_CHANGE_NOTIF (0x28) +#define USB_DEVICE_CDC_REQUEST_LINE_STATE_CHANGE_NOTIF (0x29) +#define USB_DEVICE_CDC_REQUEST_CONNECTION_SPEED_CHANGE_NOTIF (0x2A) +/* Communications Feature Selector Codes */ +#define USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE (0x01) +#define USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING (0x02) +/* Control Signal Bitmap Values */ +#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION (0x02) +#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE (0x01) +/* UART State Bitmap Values */ +#define USB_DEVICE_CDC_UART_STATE_RX_CARRIER (0x01) +#define USB_DEVICE_CDC_UART_STATE_TX_CARRIER (0x02) +#define USB_DEVICE_CDC_UART_STATE_BREAK (0x04) +#define USB_DEVICE_CDC_UART_STATE_RING_SIGNAL (0x08) +#define USB_DEVICE_CDC_UART_STATE_FRAMING (0x10) +#define USB_DEVICE_CDC_UART_STATE_PARITY (0x20) +#define USB_DEVICE_CDC_UART_STATE_OVERRUN (0x40) + +#endif /* _USB_DEVICE_CDC_ACM_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_ch9.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_ch9.c new file mode 100644 index 0000000000..b8ee92b9e8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_ch9.c @@ -0,0 +1,947 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "usb_device_config.h" +#include "usb.h" + +#include "usb_device.h" +#include "usb_device_dci.h" +#include "usb_device_ch9.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Standard request callback function typedef. + * + * This function is used to handle the standard request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_standard_request_callback_t)(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); + +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! + * @brief Get the setup packet buffer. + * + * The function is used to get the setup packet buffer to save the setup packet data. + * + * @param handle The device handle. + * @param setupBuffer It is an OUT parameter, return the setup buffer address to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer); + +/*! + * @brief Handle the class request. + * + * The function is used to handle the class request. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length It is an OUT parameter, return the data length need to be sent to host. + * @param buffer It is an OUT parameter, return the data buffer address. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer); + +/*! + * @brief Get the buffer to save the class specific data sent from host. + * + * The function is used to get the buffer to save the class specific data sent from host. + * The function will be called when the device receives a setup pakcet, and the host needs to send data to the device in + * the data stage. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length Pass the length the host needs to sent. + * @param buffer It is an OUT parameter, return the data buffer address to save the host's data. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer); + +/* standard request */ +/*! + * @brief Get the descritpor. + * + * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string + * descriptor, etc. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length It is an OUT parameter, return the data length need to be sent to host. + * @param buffer It is an OUT parameter, return the data buffer address. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer); + +/*! + * @brief Set the device configuration. + * + * The function is used to set the device configuration. + * + * @param handle The device handle. + * @param configure The configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure); + +/*! + * @brief Get the device configuration. + * + * The function is used to get the device configuration. + * + * @param handle The device handle. + * @param configure It is an OUT parameter, save the current configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure); + +/*! + * @brief Set an interface alternate setting. + * + * The function is used to set an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting The new alternate setting value. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting); + +/*! + * @brief Get an interface alternate setting. + * + * The function is used to get an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting); + +/*! + * @brief Configure a specified endpoint status. + * + * The function is used to configure a specified endpoint status, idle or halt. + * + * @param handle The device handle. + * @param endpointAddress The endpoint address, the BIT7 is the direction, 0 - USB_OUT, 1 - USB_IN. + * @param status The new status of the endpoint, 0 - idle, 1 - halt. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t status); + +/*! + * @brief Configure the device remote wakeup feature. + * + * The function is used to configure the device remote wakeup feature, enable or disbale the remote wakeup feature. + * + * @param handle The device handle. + * @param enable The new feature value of the device remote wakeup, 0 - disable, 1 - enable. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable); + +static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* The function list to handle the standard request. */ +static const usb_standard_request_callback_t s_UsbDeviceStandardRequest[] = { + USB_DeviceCh9GetStatus, + USB_DeviceCh9SetClearFeature, + (usb_standard_request_callback_t)NULL, + USB_DeviceCh9SetClearFeature, + (usb_standard_request_callback_t)NULL, + USB_DeviceCh9SetAddress, + USB_DeviceCh9GetDescriptor, + (usb_standard_request_callback_t)NULL, /* USB_DeviceCh9SetDescriptor */ + USB_DeviceCh9GetConfiguration, + USB_DeviceCh9SetConfiguration, + USB_DeviceCh9GetInterface, + USB_DeviceCh9SetInterface, + USB_DeviceCh9SynchFrame, +}; + +/* + * The internal global variable. + * This variable is used in: + * get status request + * get configuration request + * get interface request + * set interface request + * get sync frame request + */ +static uint16_t s_UsbDeviceStandardRx; + +/******************************************************************************* +* Code +******************************************************************************/ +/*! + * @brief Handle get status request. + * + * This function is used to handle get status request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) + { + return error; + } + + if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) + { + /* Get the device status */ + error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusDevice, &s_UsbDeviceStandardRx); + s_UsbDeviceStandardRx = s_UsbDeviceStandardRx & USB_GET_STATUS_DEVICE_MASK; + s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx); + /* The device status length must be USB_DEVICE_STATUS_SIZE. */ + *length = USB_DEVICE_STATUS_SIZE; + } + else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE) + { + /* Get the interface status */ + error = kStatus_USB_Success; + s_UsbDeviceStandardRx = 0U; + /* The interface status length must be USB_INTERFACE_STATUS_SIZE. */ + *length = USB_INTERFACE_STATUS_SIZE; + } + else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) + { + /* Get the endpoint status */ + usb_device_endpoint_status_struct_t endpointStatus; + endpointStatus.endpointAddress = (uint8_t)setup->wIndex; + endpointStatus.endpointStatus = kUSB_DeviceEndpointStateIdle; + error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusEndpoint, &endpointStatus); + s_UsbDeviceStandardRx = endpointStatus.endpointStatus & USB_GET_STATUS_ENDPOINT_MASK; + s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx); + /* The endpoint status length must be USB_INTERFACE_STATUS_SIZE. */ + *length = USB_ENDPOINT_STATUS_SIZE; + } + else + { + } + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + + return error; +} + +/*! + * @brief Handle set or clear device feature request. + * + * This function is used to handle set or clear device feature request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + uint8_t isSet = 0U; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) + { + return error; + } + + /* Identify the request is set or clear the feature. */ + if (USB_REQUEST_STANDARD_SET_FEATURE == setup->bRequest) + { + isSet = 1U; + } + + if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) + { + /* Set or Clear the device featrue. */ + if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP == setup->wValue) + { + /* Set or Clear the device remote wakeup featrue. */ + error = USB_DeviceConfigureRemoteWakeup(handle, isSet); + } +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \ + (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U)) + else if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE == setup->wValue) + { + state = kUSB_DeviceStateTestMode; + error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state); + } +#endif + else + { + } + } + else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) + { + /* Set or Clear the endpoint featrue. */ + if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT == setup->wValue) + { + if (USB_CONTROL_ENDPOINT == (setup->wIndex & USB_ENDPOINT_NUMBER_MASK)) + { + /* Set or Clear the control endpoint status(halt or not). */ + if (isSet) + { + USB_DeviceStallEndpoint(handle, (uint8_t)setup->wIndex); + } + else + { + USB_DeviceUnstallEndpoint(handle, (uint8_t)setup->wIndex); + } + } + + /* Set or Clear the endpoint status featrue. */ + error = USB_DeviceConfigureEndpointStatus(handle, setup->wIndex, isSet); + } + else + { + } + } + else + { + } + + return error; +} + +/*! + * @brief Handle set address request. + * + * This function is used to handle set address request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state. + */ +static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddressing != state) && (kUSB_DeviceStateAddress != state) && + (kUSB_DeviceStateDefault != state)) + { + return error; + } + + if (kUSB_DeviceStateAddressing != state) + { + /* If the device address is not setting, pass the address and the device state will change to + * kUSB_DeviceStateAddressing internally. */ + state = setup->wValue & 0xFFU; + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, &state); + } + else + { + /* If the device address is setting, set device address and the address will be write into the controller + * internally. */ + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL); + /* And then change the device state to kUSB_DeviceStateAddress. */ + if (kStatus_USB_Success == error) + { + state = kUSB_DeviceStateAddress; + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + + return error; +} + +/*! + * @brief Handle get descriptor request. + * + * This function is used to handle get descriptor request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state) && + (kUSB_DeviceStateDefault != state)) + { + return kStatus_USB_InvalidRequest; + } + + return USB_DeviceGetDescriptor(handle, setup, length, buffer); +} + +/*! + * @brief Handle get current configuration request. + * + * This function is used to handle get current configuration request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && ((kUSB_DeviceStateConfigured != state))) + { + return kStatus_USB_InvalidRequest; + } + + *length = USB_CONFIGURE_SIZE; + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + return USB_DeviceGetConfigure(handle, (uint8_t *)&s_UsbDeviceStandardRx); +} + +/*! + * @brief Handle set current configuration request. + * + * This function is used to handle set current configuration request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) + { + return kStatus_USB_InvalidRequest; + } + + /* The device state is changed to kUSB_DeviceStateConfigured */ + state = kUSB_DeviceStateConfigured; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if (!setup->wValue) + { + /* If the new configuration is zero, the device state is changed to kUSB_DeviceStateAddress */ + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + + return USB_DeviceSetConfigure(handle, setup->wValue); +} + +/*! + * @brief Handle get the alternate setting of a interface request. + * + * This function is used to handle get the alternate setting of a interface request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (state != kUSB_DeviceStateConfigured) + { + return error; + } + *length = USB_INTERFACE_SIZE; + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + + return USB_DeviceGetInterface(handle, setup->wIndex & 0xFFU, (uint8_t *)&s_UsbDeviceStandardRx); +} + +/*! + * @brief Handle set the alternate setting of a interface request. + * + * This function is used to handle set the alternate setting of a interface request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (state != kUSB_DeviceStateConfigured) + { + return kStatus_USB_InvalidRequest; + } + + return USB_DeviceSetInterface(handle, (setup->wIndex & 0xFFU), (setup->wValue & 0xFFU)); +} + +/*! + * @brief Handle get sync frame request. + * + * This function is used to handle get sync frame request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (state != kUSB_DeviceStateConfigured) + { + return error; + } + + s_UsbDeviceStandardRx = setup->wIndex; + /* Get the sync frame value */ + error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusSynchFrame, &s_UsbDeviceStandardRx); + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + *length = sizeof(s_UsbDeviceStandardRx); + + return error; +} + +/*! + * @brief Send the reponse to the host. + * + * This function is used to send the reponse to the host. + * + * There are two cases this function will be called. + * Case one when a setup packet is received in control endpoint callback function: + * 1. If there is not data phase in the setup transfer, the function will prime an IN transfer with the data + * length is zero for status phase. + * 2. If there is an IN data phase, the function will prime an OUT transfer with the actual length to need to + * send for data phase. And then prime an IN transfer with the data length is zero for status phase. + * 3. If there is an OUT data phase, the function will prime an IN transfer with the actual length to want to + * receive for data phase. + * + * Case two when is not a setup packet received in control endpoint callback function: + * 1. The function will prime an IN transfer with data length is zero for status phase. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param error The error code returned from the standard request fucntion. + * @param stage The stage of the control transfer. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceControlCallbackFeedback(usb_device_handle handle, + usb_setup_struct_t *setup, + usb_status_t error, + usb_device_control_read_write_sequence_t stage, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t errorCode = kStatus_USB_Error; + uint8_t direction = USB_IN; + + if (kStatus_USB_InvalidRequest == error) + { + /* Stall the control pipe when the request is unsupported. */ + if ((!((setup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD)) && + ((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT) && (setup->wLength) && + (kUSB_DeviceControlPipeSetupStage == stage)) + { + direction = USB_OUT; + } + errorCode = USB_DeviceStallEndpoint( + handle, + (USB_CONTROL_ENDPOINT) | (uint8_t)((uint32_t)direction << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + } + else + { + if (*length > setup->wLength) + { + *length = setup->wLength; + } + errorCode = USB_DeviceSendRequest(handle, (USB_CONTROL_ENDPOINT), *buffer, *length); + + if ((kStatus_USB_Success == errorCode) && + (USB_REQUEST_TYPE_DIR_IN == (setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK))) + { + errorCode = USB_DeviceRecvRequest(handle, (USB_CONTROL_ENDPOINT), (uint8_t *)NULL, 0U); + } + } + return errorCode; +} + +/*! + * @brief Control endpoint callback function. + * + * This callback function is used to notify uplayer the tranfser result of a transfer. + * This callback pointer is passed when a sepcified endpoint initialied by calling API USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The result of a transfer, includes transfer buffer, transfer length and whether is in setup + * phase for control pipe. + * @param callbackParam The paramter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceControlCallback(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_setup_struct_t *deviceSetup; + uint8_t *setupOutBuffer; + uint8_t *buffer = (uint8_t *)NULL; + uint32_t length = 0U; + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + if (USB_UNINITIALIZED_VAL_32 == message->length) + { + return error; + } + + USB_DeviceGetSetupBuffer(handle, &deviceSetup); + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (message->isSetup) + { + if ((USB_SETUP_PACKET_SIZE != message->length) || (NULL == message->buffer)) + { + /* If a invalid setup is received, the control pipes should be de-init and init again. + * Due to the IP can not meet this require, it is revesed for feature. + */ + /* + USB_DeviceDeinitEndpoint(handle, + USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + USB_DeviceDeinitEndpoint(handle, + USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + USB_DeviceControlPipeInit(handle); + */ + return error; + } + /* Receive a setup request */ + usb_setup_struct_t *setup = (usb_setup_struct_t *)(message->buffer); + /* Copy the setup packet to the application buffer */ + deviceSetup->wValue = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wValue); + deviceSetup->wIndex = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wIndex); + deviceSetup->wLength = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wLength); + deviceSetup->bRequest = setup->bRequest; + deviceSetup->bmRequestType = setup->bmRequestType; + + if ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD) + { + /* Handle the standard request */ + if (s_UsbDeviceStandardRequest[deviceSetup->bRequest] != (usb_standard_request_callback_t)NULL) + { + error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length); + } + } + else + { + if ((deviceSetup->wLength) && + ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT)) + { + /* Class or vendor request with the OUT data phase. */ + if ((deviceSetup->wLength) && + ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) + { + /* Get data buffer to receive the data from the host. */ + length = deviceSetup->wLength; + error = USB_DeviceGetClassReceiveBuffer(handle, deviceSetup, &length, &setupOutBuffer); + length = 0U; + } + else + { + } + if (kStatus_USB_Success == error) + { + /* Prime an OUT transfer */ + error = USB_DeviceRecvRequest(handle, USB_CONTROL_ENDPOINT, setupOutBuffer, deviceSetup->wLength); + return error; + } + } + else + { + /* Class or vendor request with the IN data phase. */ + if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) + { + /* Get data buffer to response the host. */ + error = USB_DeviceProcessClassRequest(handle, deviceSetup, &length, &buffer); + } + else + { + } + } + } + /* Send the reponse to the host. */ + error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeSetupStage, &buffer, + &length); + } + else if (kUSB_DeviceStateAddressing == state) + { + /* Set the device address to controller. */ + error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length); + } +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \ + (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U)) + else if (kUSB_DeviceStateTestMode == state) + { + uint8_t portTestControl = (uint8_t)(deviceSetup->wIndex >> 8); + /* Set the controller.into test mode. */ + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusTestMode, &portTestControl); + } +#endif + else if ((message->length) && (deviceSetup->wLength) && + ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT)) + { + if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) + { + /* Data received in OUT phase, and notify the class driver. */ + error = USB_DeviceProcessClassRequest(handle, deviceSetup, &message->length, &message->buffer); + } + else + { + } + /* Send the reponse to the host. */ + error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeDataStage, &buffer, + &length); + } + else + { + } + return error; +} + +/*! + * @brief Control endpoint initialization function. + * + * This callback function is used to initialize the control pipes. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param param The up layer handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle) +{ + usb_device_endpoint_init_struct_t epInitStruct; + usb_device_endpoint_callback_struct_t endpointCallback; + usb_status_t error; + + endpointCallback.callbackFn = USB_DeviceControlCallback; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 1U; + epInitStruct.transferType = USB_ENDPOINT_CONTROL; + epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + epInitStruct.maxPacketSize = USB_CONTROL_MAX_PACKET_SIZE; + /* Initialize the control IN pipe */ + error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback); + + if (kStatus_USB_Success != error) + { + return error; + } + epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + /* Initialize the control OUT pipe */ + error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback); + + if (kStatus_USB_Success != error) + { + USB_DeviceDeinitEndpoint(handle, + USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + return error; + } + + return kStatus_USB_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_ch9.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_ch9.h new file mode 100644 index 0000000000..0d964c800f --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_ch9.h @@ -0,0 +1,112 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_CH9_H__ +#define __USB_DEVICE_CH9_H__ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @addtogroup usb_device_ch9 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines USB device status size when the host request to get device status */ +#define USB_DEVICE_STATUS_SIZE (0x02U) + +/*! @brief Defines USB device interface status size when the host request to get interface status */ +#define USB_INTERFACE_STATUS_SIZE (0x02U) + +/*! @brief Defines USB device endpoint status size when the host request to get endpoint status */ +#define USB_ENDPOINT_STATUS_SIZE (0x02U) + +/*! @brief Defines USB device configuration size when the host request to get current configuration */ +#define USB_CONFIGURE_SIZE (0X01U) + +/*! @brief Defines USB device interface alternate setting size when the host request to get interface alternate setting + */ +#define USB_INTERFACE_SIZE (0X01U) + +/*! @brief Defines USB device status mask */ +#define USB_GET_STATUS_DEVICE_MASK (0x03U) + +/*! @brief Defines USB device interface status mask */ +#define USB_GET_STATUS_INTERFACE_MASK (0x03U) + +/*! @brief Defines USB device endpoint status mask */ +#define USB_GET_STATUS_ENDPOINT_MASK (0x03U) + +/*! @brief Control read and write sequence */ +typedef enum _usb_device_control_read_write_sequence +{ + kUSB_DeviceControlPipeSetupStage = 0U, /*!< Setup stage */ + kUSB_DeviceControlPipeDataStage, /*!< Data stage */ + kUSB_DeviceControlPipeStatusStage, /*!< status stage */ +} usb_device_control_read_write_sequence_t; + +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initialize the control pipes. + * + * The function is used to initialize the control pipes. This function should be called when event + * kUSB_DeviceEventBusReset is received. + * + * @param handle The device handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __USB_DEVICE_CH9_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_config.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_config.h new file mode 100644 index 0000000000..5d7bb7c9fa --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_config.h @@ -0,0 +1,183 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2018 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CONFIG_H_ +#define _USB_DEVICE_CONFIG_H_ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @name Hardware instance define + * @{ + */ + +/*! @brief KHCI instance count */ +#define USB_DEVICE_CONFIG_KHCI (0U) + +/*! @brief EHCI instance count */ +#define USB_DEVICE_CONFIG_EHCI (1U) + +/*! @brief LPC USB IP3511 FS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511FS (0U) + +/*! @brief LPC USB IP3511 HS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) + +/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ +#define USB_DEVICE_CONFIG_NUM \ + (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) + +/* @} */ + +/*! + * @addtogroup usb_device_configuration + * @{ + */ + +/*! + * @name class instance define + * @{ + */ + +/*! @brief HID instance count */ +#define USB_DEVICE_CONFIG_HID (0U) + +/*! @brief CDC ACM instance count */ +#define USB_DEVICE_CONFIG_CDC_ACM (1U) + +/*! @brief MSC instance count */ +#define USB_DEVICE_CONFIG_MSC (0U) + +/*! @brief Audio instance count */ +#define USB_DEVICE_CONFIG_AUDIO (0U) + +/*! @brief PHDC instance count */ +#define USB_DEVICE_CONFIG_PHDC (0U) + +/*! @brief Video instance count */ +#define USB_DEVICE_CONFIG_VIDEO (0U) + +/*! @brief CCID instance count */ +#define USB_DEVICE_CONFIG_CCID (0U) + +/*! @brief Printer instance count */ +#define USB_DEVICE_CONFIG_PRINTER (0U) + +/*! @brief DFU instance count */ +#define USB_DEVICE_CONFIG_DFU (0U) + +/* @} */ + +/*! @brief Whether device is self power. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_SELF_POWER (1U) + +/*! @brief How many endpoints are supported in the stack. */ +#define USB_DEVICE_CONFIG_ENDPOINTS (4U) + +/*! @brief Whether the device task is enabled. */ +#define USB_DEVICE_CONFIG_USE_TASK (0U) + +/*! @brief How many the notification message are supported when the device task is enabled. */ +#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) + +/*! @brief Whether test mode enabled. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) + +/*! @brief Whether device CV test is enabled. */ +#define USB_DEVICE_CONFIG_CV_TEST (0U) + +/*! @brief Whether device compliance test is enabled. If the macro is enabled, + the test mode and CV test macroes will be set.*/ +#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) + +#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) + +/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ +#undef USB_DEVICE_CONFIG_USB20_TEST_MODE +/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ +#undef USB_DEVICE_CONFIG_CV_TEST + +/*! @brief enable the test mode. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) + +/*! @brief enable the CV test */ +#define USB_DEVICE_CONFIG_CV_TEST (1U) + +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + +/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ +#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! @brief How many the DTD are supported. */ +#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) + +/*! @brief Whether the EHCI ID pin detect feature enabled. */ +#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) +#endif + +/*! @brief Whether the keep alive feature enabled. */ +#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) + +/*! @brief Whether the transfer buffer is cache-enabled or not. */ +#ifndef USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE +#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U) +#endif +/*! @brief Whether the low power mode is enabled or not. */ +#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) + +/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_LPM_L1 (0U) +#else +/*! @brief The device remote wakeup is unsupported. */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) +#endif + +/*! @brief Whether the device detached feature is enabled or not. */ +#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) + +/*! @brief Whether handle the USB bus error. */ +#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) + +/* @} */ + +#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_descriptor.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_descriptor.c new file mode 100644 index 0000000000..8271e58a8b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_descriptor.c @@ -0,0 +1,482 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device.h" + +#include "usb_device_cdc_acm.h" + +#include "usb_device_descriptor.h" + +/******************************************************************************* +* Variables +******************************************************************************/ +uint8_t g_currentConfigure = 0; +uint8_t g_interface[USB_CDC_VCOM_INTERFACE_COUNT]; + +/* Define device descriptor */ +uint8_t g_UsbDeviceDescriptor[USB_DESCRIPTOR_LENGTH_DEVICE] = { + /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_LENGTH_DEVICE, + /* DEVICE Descriptor Type */ + USB_DESCRIPTOR_TYPE_DEVICE, + /* USB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). */ + USB_SHORT_GET_LOW(USB_DEVICE_SPECIFIC_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_SPECIFIC_BCD_VERSION), + /* Class code (assigned by the USB-IF). */ + USB_DEVICE_CLASS, + /* Subclass code (assigned by the USB-IF). */ + USB_DEVICE_SUBCLASS, + /* Protocol code (assigned by the USB-IF). */ + USB_DEVICE_PROTOCOL, + /* Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid) */ + USB_CONTROL_MAX_PACKET_SIZE, + /* Vendor ID (assigned by the USB-IF) */ + 0xC9U, 0x1FU, + /* Product ID (assigned by the manufacturer) */ + 0x94, 0x00, + /* Device release number in binary-coded decimal */ + USB_SHORT_GET_LOW(USB_DEVICE_DEMO_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_DEMO_BCD_VERSION), + /* Index of string descriptor describing manufacturer */ + 0x01, + /* Index of string descriptor describing product */ + 0x02, + /* Index of string descriptor describing the device's serial number */ + 0x00, + /* Number of possible configurations */ + USB_DEVICE_CONFIGURATION_COUNT, +}; + +/* Define configuration descriptor */ +uint8_t g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL] = { + /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_LENGTH_CONFIGURE, + /* CONFIGURATION Descriptor Type */ + USB_DESCRIPTOR_TYPE_CONFIGURE, + /* Total length of data returned for this configuration. */ + USB_SHORT_GET_LOW(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL), + USB_SHORT_GET_HIGH(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL), + /* Number of interfaces supported by this configuration */ + USB_CDC_VCOM_INTERFACE_COUNT, + /* Value to use as an argument to the SetConfiguration() request to select this configuration */ + USB_CDC_VCOM_CONFIGURE_INDEX, + /* Index of string descriptor describing this configuration */ + 0, + /* Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote Wakeup D4...0: Reserved + (reset to zero) */ + (USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK) | + (USB_DEVICE_CONFIG_SELF_POWER << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT) | + (USB_DEVICE_CONFIG_REMOTE_WAKEUP << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT), + /* Maximum power consumption of the USB * device from the bus in this specific * configuration when the device is + fully * operational. Expressed in 2 mA units * (i.e., 50 = 100 mA). */ + USB_DEVICE_MAX_POWER, + + /* Communication Interface Descriptor */ + USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_COMM_INTERFACE_INDEX, 0x00, + USB_CDC_VCOM_ENDPOINT_CIC_COUNT, USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL, + 0x00, /* Interface Description String Index*/ + + /* CDC Class-Specific descriptor */ + USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_HEADER_FUNC_DESC, 0x10, + 0x01, /* USB Class Definitions for Communications the Communication specification version 1.10 */ + + USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_CALL_MANAGEMENT_FUNC_DESC, + 0x01, /*Bit 0: Whether device handle call management itself 1, Bit 1: Whether device can send/receive call + management information over a Data Class Interface 0 */ + 0x01, /* Indicates multiplexed commands are handled via data interface */ + + USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_ABSTRACT_CONTROL_FUNC_DESC, + 0x06, /* Bit 0: Whether device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and + Get_Comm_Feature 0, Bit 1: Whether device supports the request combination of Set_Line_Coding, + Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State 1, Bit ... */ + + USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_UNION_FUNC_DESC, 0x00, /* The interface number of the Communications or Data Class interface */ + 0x01, /* Interface number of subordinate interface in the Union */ + + /*Notification Endpoint descriptor */ + USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | (USB_IN << 7U), + USB_ENDPOINT_INTERRUPT, USB_SHORT_GET_LOW(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), + USB_SHORT_GET_HIGH(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), FS_CDC_VCOM_INTERRUPT_IN_INTERVAL, + + /* Data Interface Descriptor */ + USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_DATA_INTERFACE_INDEX, 0x00, + USB_CDC_VCOM_ENDPOINT_DIC_COUNT, USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL, + 0x00, /* Interface Description String Index*/ + + /*Bulk IN Endpoint descriptor */ + USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << 7U), + USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), + USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */ + + /*Bulk OUT Endpoint descriptor */ + USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << 7U), + USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), + USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */ +}; + +/* Define string descriptor */ +uint8_t g_UsbDeviceString0[USB_DESCRIPTOR_LENGTH_STRING0] = {sizeof(g_UsbDeviceString0), USB_DESCRIPTOR_TYPE_STRING, + 0x09, 0x04}; + +uint8_t g_UsbDeviceString1[USB_DESCRIPTOR_LENGTH_STRING1] = { + sizeof(g_UsbDeviceString1), + USB_DESCRIPTOR_TYPE_STRING, + 'N', + 0x00U, + 'X', + 0x00U, + 'P', + 0x00U, + ' ', + 0x00U, + 'S', + 0x00U, + 'E', + 0x00U, + 'M', + 0x00U, + 'I', + 0x00U, + 'C', + 0x00U, + 'O', + 0x00U, + 'N', + 0x00U, + 'D', + 0x00U, + 'U', + 0x00U, + 'C', + 0x00U, + 'T', + 0x00U, + 'O', + 0x00U, + 'R', + 0x00U, + 'S', + 0x00U, +}; + +uint8_t g_UsbDeviceString2[USB_DESCRIPTOR_LENGTH_STRING2] = {sizeof(g_UsbDeviceString2), + USB_DESCRIPTOR_TYPE_STRING, + 'M', + 0, + 'C', + 0, + 'U', + 0, + ' ', + 0, + 'V', + 0, + 'I', + 0, + 'R', + 0, + 'T', + 0, + 'U', + 0, + 'A', + 0, + 'L', + 0, + ' ', + 0, + 'C', + 0, + 'O', + 0, + 'M', + 0, + ' ', + 0, + 'D', + 0, + 'E', + 0, + 'M', + 0, + 'O', + 0}; + +uint8_t *g_UsbDeviceStringDescriptorArray[USB_DEVICE_STRING_COUNT] = {g_UsbDeviceString0, g_UsbDeviceString1, + g_UsbDeviceString2}; + +/* Define string descriptor size */ +uint32_t g_UsbDeviceStringDescriptorLength[USB_DEVICE_STRING_COUNT] = { + sizeof(g_UsbDeviceString0), sizeof(g_UsbDeviceString1), sizeof(g_UsbDeviceString2)}; +usb_language_t g_UsbDeviceLanguage[USB_DEVICE_LANGUAGE_COUNT] = {{ + g_UsbDeviceStringDescriptorArray, g_UsbDeviceStringDescriptorLength, (uint16_t)0x0409, +}}; + +usb_language_list_t g_UsbDeviceLanguageList = { + g_UsbDeviceString0, sizeof(g_UsbDeviceString0), g_UsbDeviceLanguage, USB_DEVICE_LANGUAGE_COUNT, +}; + +/******************************************************************************* +* Code +******************************************************************************/ +/*! + * @brief Get the descritpor. + * + * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string + * descriptor, etc. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length It is an OUT parameter, return the data length need to be sent to host. + * @param buffer It is an OUT parameter, return the data buffer address. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer) +{ + uint8_t descriptorType = (uint8_t)((setup->wValue & 0xFF00U) >> 8U); + uint8_t descriptorIndex = (uint8_t)((setup->wValue & 0x00FFU)); + usb_status_t ret = kStatus_USB_Success; + if (USB_REQUEST_STANDARD_GET_DESCRIPTOR != setup->bRequest) + { + return kStatus_USB_InvalidRequest; + } + switch (descriptorType) + { + case USB_DESCRIPTOR_TYPE_STRING: + { + if (descriptorIndex == 0) + { + *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageString; + *length = g_UsbDeviceLanguageList.stringLength; + } + else + { + uint8_t langId = 0; + uint8_t langIndex = USB_DEVICE_STRING_COUNT; + + for (; langId < USB_DEVICE_LANGUAGE_COUNT; langId++) + { + if (setup->wIndex == g_UsbDeviceLanguageList.languageList[langId].languageId) + { + if (descriptorIndex < USB_DEVICE_STRING_COUNT) + { + langIndex = descriptorIndex; + } + break; + } + } + + if (USB_DEVICE_STRING_COUNT == langIndex) + { + langId = 0; + } + *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageList[langId].string[langIndex]; + *length = g_UsbDeviceLanguageList.languageList[langId].length[langIndex]; + } + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE: + { + *buffer = g_UsbDeviceDescriptor; + *length = USB_DESCRIPTOR_LENGTH_DEVICE; + } + break; + case USB_DESCRIPTOR_TYPE_CONFIGURE: + { + *buffer = g_UsbDeviceConfigurationDescriptor; + *length = USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL; + } + break; + default: + ret = kStatus_USB_InvalidRequest; + break; + } /* End Switch */ + return ret; +} + +/*! + * @brief Set the device configuration. + * + * The function is used to set the device configuration. + * + * @param handle The device handle. + * @param configure The configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure) +{ + if (!configure) + { + return kStatus_USB_Error; + } + g_currentConfigure = configure; + return USB_DeviceCallback(handle, kUSB_DeviceEventSetConfiguration, &configure); +} + +/*! + * @brief Get the device configuration. + * + * The function is used to get the device configuration. + * + * @param handle The device handle. + * @param configure It is an OUT parameter, save the current configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure) +{ + *configure = g_currentConfigure; + return kStatus_USB_Success; +} + +/*! + * @brief Set an interface alternate setting. + * + * The function is used to set an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting The new alternate setting value. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting) +{ + g_interface[interface] = alternateSetting; + return USB_DeviceCallback(handle, kUSB_DeviceEventSetInterface, &interface); +} + +/*! + * @brief Get an interface alternate setting. + * + * The function is used to get an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting) +{ + *alternateSetting = g_interface[interface]; + return kStatus_USB_Success; +} + +/*! + * @brief USB device set speed function. + * + * This function sets the speed of the USB device. + * + * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match + * current speed. + * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and + * KHCI. + * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed. + * The updated information includes endpoint max packet size, endpoint interval, etc. + * + * @param handle The USB device handle. + * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed) +{ + usb_descriptor_union_t *ptr1; + usb_descriptor_union_t *ptr2; + + ptr1 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[0]); + ptr2 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL - 1]); + + while (ptr1 < ptr2) + { + if (ptr1->common.bDescriptorType == USB_DESCRIPTOR_TYPE_ENDPOINT) + { + if (USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) + { + if (USB_SPEED_HIGH == speed) + { + ptr1->endpoint.bInterval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL; + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE, + ptr1->endpoint.wMaxPacketSize); + } + else + { + ptr1->endpoint.bInterval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL; + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE, + ptr1->endpoint.wMaxPacketSize); + } + } + else if (USB_CDC_VCOM_BULK_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) + { + if (USB_SPEED_HIGH == speed) + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + else + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + } + else if (USB_CDC_VCOM_BULK_OUT_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) + { + if (USB_SPEED_HIGH == speed) + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + else + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + } + else + { + } + } + ptr1 = (usb_descriptor_union_t *)((uint8_t *)ptr1 + ptr1->common.bLength); + } + return kStatus_USB_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_descriptor.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_descriptor.h new file mode 100644 index 0000000000..5b8c8084a2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/usb_device_descriptor.h @@ -0,0 +1,203 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _USB_DEVICE_DESCRIPTOR_H_ +#define _USB_DEVICE_DESCRIPTOR_H_ 1 + +/******************************************************************************* +* Definitions +******************************************************************************/ +#define USB_DEVICE_SPECIFIC_BCD_VERSION (0x0200) +#define USB_DEVICE_DEMO_BCD_VERSION (0x0101U) + +/* Communication Class Codes */ +#define CDC_COMM_CLASS (0x02) +/* Data Class Codes */ +#define CDC_DATA_CLASS (0x0A) + +/* Communication Class SubClass Codes */ +#define USB_CDC_DIRECT_LINE_CONTROL_MODEL (0x01) +#define USB_CDC_ABSTRACT_CONTROL_MODEL (0x02) +#define USB_CDC_TELEPHONE_CONTROL_MODEL (0x03) +#define USB_CDC_MULTI_CHANNEL_CONTROL_MODEL (0x04) +#define USB_CDC_CAPI_CONTROL_MOPDEL (0x05) +#define USB_CDC_ETHERNET_NETWORKING_CONTROL_MODEL (0x06) +#define USB_CDC_ATM_NETWORKING_CONTROL_MODEL (0x07) +#define USB_CDC_WIRELESS_HANDSET_CONTROL_MODEL (0x08) +#define USB_CDC_DEVICE_MANAGEMENT (0x09) +#define USB_CDC_MOBILE_DIRECT_LINE_MODEL (0x0A) +#define USB_CDC_OBEX (0x0B) +#define USB_CDC_ETHERNET_EMULATION_MODEL (0x0C) + +/* Communication Class Protocol Codes */ +#define USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL (0x00) /*also for Data Class Protocol Code */ +#define USB_CDC_AT_250_PROTOCOL (0x01) +#define USB_CDC_AT_PCCA_101_PROTOCOL (0x02) +#define USB_CDC_AT_PCCA_101_ANNEX_O (0x03) +#define USB_CDC_AT_GSM_7_07 (0x04) +#define USB_CDC_AT_3GPP_27_007 (0x05) +#define USB_CDC_AT_TIA_CDMA (0x06) +#define USB_CDC_ETHERNET_EMULATION_PROTOCOL (0x07) +#define USB_CDC_EXTERNAL_PROTOCOL (0xFE) +#define USB_CDC_VENDOR_SPECIFIC (0xFF) /*also for Data Class Protocol Code */ + +/* Data Class Protocol Codes */ +#define USB_CDC_PYHSICAL_INTERFACE_PROTOCOL (0x30) +#define USB_CDC_HDLC_PROTOCOL (0x31) +#define USB_CDC_TRANSPARENT_PROTOCOL (0x32) +#define USB_CDC_MANAGEMENT_PROTOCOL (0x50) +#define USB_CDC_DATA_LINK_Q931_PROTOCOL (0x51) +#define USB_CDC_DATA_LINK_Q921_PROTOCOL (0x52) +#define USB_CDC_DATA_COMPRESSION_V42BIS (0x90) +#define USB_CDC_EURO_ISDN_PROTOCOL (0x91) +#define USB_CDC_RATE_ADAPTION_ISDN_V24 (0x92) +#define USB_CDC_CAPI_COMMANDS (0x93) +#define USB_CDC_HOST_BASED_DRIVER (0xFD) +#define USB_CDC_UNIT_FUNCTIONAL (0xFE) + +/* Descriptor SubType in Communications Class Functional Descriptors */ +#define USB_CDC_HEADER_FUNC_DESC (0x00) +#define USB_CDC_CALL_MANAGEMENT_FUNC_DESC (0x01) +#define USB_CDC_ABSTRACT_CONTROL_FUNC_DESC (0x02) +#define USB_CDC_DIRECT_LINE_FUNC_DESC (0x03) +#define USB_CDC_TELEPHONE_RINGER_FUNC_DESC (0x04) +#define USB_CDC_TELEPHONE_REPORT_FUNC_DESC (0x05) +#define USB_CDC_UNION_FUNC_DESC (0x06) +#define USB_CDC_COUNTRY_SELECT_FUNC_DESC (0x07) +#define USB_CDC_TELEPHONE_MODES_FUNC_DESC (0x08) +#define USB_CDC_TERMINAL_FUNC_DESC (0x09) +#define USB_CDC_NETWORK_CHANNEL_FUNC_DESC (0x0A) +#define USB_CDC_PROTOCOL_UNIT_FUNC_DESC (0x0B) +#define USB_CDC_EXTENSION_UNIT_FUNC_DESC (0x0C) +#define USB_CDC_MULTI_CHANNEL_FUNC_DESC (0x0D) +#define USB_CDC_CAPI_CONTROL_FUNC_DESC (0x0E) +#define USB_CDC_ETHERNET_NETWORKING_FUNC_DESC (0x0F) +#define USB_CDC_ATM_NETWORKING_FUNC_DESC (0x10) +#define USB_CDC_WIRELESS_CONTROL_FUNC_DESC (0x11) +#define USB_CDC_MOBILE_DIRECT_LINE_FUNC_DESC (0x12) +#define USB_CDC_MDLM_DETAIL_FUNC_DESC (0x13) +#define USB_CDC_DEVICE_MANAGEMENT_FUNC_DESC (0x14) +#define USB_CDC_OBEX_FUNC_DESC (0x15) +#define USB_CDC_COMMAND_SET_FUNC_DESC (0x16) +#define USB_CDC_COMMAND_SET_DETAIL_FUNC_DESC (0x17) +#define USB_CDC_TELEPHONE_CONTROL_FUNC_DESC (0x18) +#define USB_CDC_OBEX_SERVICE_ID_FUNC_DESC (0x19) + +/* usb descritpor length */ +#define USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL (67) +#define USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC (5) +#define USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG (5) +#define USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT (4) +#define USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC (5) + +#define USB_DEVICE_CONFIGURATION_COUNT (1) +#define USB_DEVICE_STRING_COUNT (3) +#define USB_DEVICE_LANGUAGE_COUNT (1) + +#define USB_CDC_VCOM_CONFIGURE_INDEX (1) + +#define USB_CDC_VCOM_ENDPOINT_CIC_COUNT (1) +#define USB_CDC_VCOM_ENDPOINT_DIC_COUNT (2) +#define USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT (1) +#define USB_CDC_VCOM_BULK_IN_ENDPOINT (2) +#define USB_CDC_VCOM_BULK_OUT_ENDPOINT (3) +#define USB_CDC_VCOM_INTERFACE_COUNT (2) +#define USB_CDC_VCOM_COMM_INTERFACE_INDEX (0) +#define USB_CDC_VCOM_DATA_INTERFACE_INDEX (1) + +#define HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16) +#define FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16) +#define HS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x07) /* 2^(7-1) = 8ms */ +#define FS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x08) +#define HS_CDC_VCOM_BULK_IN_PACKET_SIZE (512) +#define FS_CDC_VCOM_BULK_IN_PACKET_SIZE (64) +#define HS_CDC_VCOM_BULK_OUT_PACKET_SIZE (512) +#define FS_CDC_VCOM_BULK_OUT_PACKET_SIZE (64) + +#define USB_DESCRIPTOR_LENGTH_STRING0 (4) +#define USB_DESCRIPTOR_LENGTH_STRING1 (38) +#define USB_DESCRIPTOR_LENGTH_STRING2 (42) + +#define USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE (0x24) +#define USB_DESCRIPTOR_TYPE_CDC_CS_ENDPOINT (0x25) + +#define USB_DEVICE_CLASS (0x02) +#define USB_DEVICE_SUBCLASS (0x00) +#define USB_DEVICE_PROTOCOL (0x00) + +#define USB_DEVICE_MAX_POWER (0x32) + +#define USB_CDC_VCOM_CIC_CLASS (CDC_COMM_CLASS) +#define USB_CDC_VCOM_CIC_SUBCLASS (USB_CDC_ABSTRACT_CONTROL_MODEL) +#define USB_CDC_VCOM_CIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL) + +#define USB_CDC_VCOM_DIC_CLASS (CDC_DATA_CLASS) +#define USB_CDC_VCOM_DIC_SUBCLASS (0x00) +#define USB_CDC_VCOM_DIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL) + +/******************************************************************************* +* API +******************************************************************************/ +/*! + * @brief USB device callback function. + * + * This function handles the usb device specific requests. + * + * @param handle The USB device handle. + * @param event The USB device event type. + * @param param The parameter of the device specific request. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param); + +/*! + * @brief USB device set speed function. + * + * This function sets the speed of the USB device. + * + * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match + * current speed. + * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and + * KHCI. + * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed. + * The updated information includes endpoint max packet size, endpoint interval, etc. + * + * @param handle The USB device handle. + * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed); + +#endif /* _USB_DEVICE_DESCRIPTOR_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/virtual_com.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/virtual_com.c new file mode 100644 index 0000000000..d9e507fbc6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/virtual_com.c @@ -0,0 +1,693 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_device_registers.h" +#include "clock_config.h" +#include "board.h" + +#include +#include + +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device.h" + +#include "usb_device_cdc_acm.h" +#include "usb_device_ch9.h" + +#include "usb_device_descriptor.h" +#include "virtual_com.h" +#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U)) +#include "fsl_sysmpu.h" +#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) +#include "usb_phy.h" +#endif + +/* Provided by users. */ +extern void USB_DeviceClockInit(void); +extern void USB_DeviceIsrEnable(void); +/******************************************************************************* +* Definitions +******************************************************************************/ + +/******************************************************************************* +* Variables +******************************************************************************/ +/* Data structure of virtual com device */ +usb_cdc_vcom_struct_t s_cdcVcom; + +/* Line codinig of cdc device */ +static uint8_t s_lineCoding[LINE_CODING_SIZE] = { + /* E.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */ + (LINE_CODING_DTERATE >> 0U) & 0x000000FFU, + (LINE_CODING_DTERATE >> 8U) & 0x000000FFU, + (LINE_CODING_DTERATE >> 16U) & 0x000000FFU, + (LINE_CODING_DTERATE >> 24U) & 0x000000FFU, + LINE_CODING_CHARFORMAT, + LINE_CODING_PARITYTYPE, + LINE_CODING_DATABITS}; + +/* Abstract state of cdc device */ +static uint8_t s_abstractState[COMM_FEATURE_DATA_SIZE] = {(STATUS_ABSTRACT_STATE >> 0U) & 0x00FFU, + (STATUS_ABSTRACT_STATE >> 8U) & 0x00FFU}; + +/* Country code of cdc device */ +static uint8_t s_countryCode[COMM_FEATURE_DATA_SIZE] = {(COUNTRY_SETTING >> 0U) & 0x00FFU, + (COUNTRY_SETTING >> 8U) & 0x00FFU}; + +/* CDC ACM information */ +static usb_cdc_acm_info_t s_usbCdcAcmInfo = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0}; + +/* Data buffer for receiving and sending*/ +static uint8_t s_currRecvBuf[DATA_BUFF_SIZE]; +volatile static uint32_t s_recvSize = 0; +volatile static uint32_t s_sendSize = 0; +volatile static uint8_t s_sendComplete = 0; +volatile static uint8_t s_currRecvIndex = 0; +static uint32_t s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/******************************************************************************* +* Code +******************************************************************************/ +/*! + * @brief Interrupt in pipe callback function. + * + * This function serves as the callback function for interrupt in pipe. + * + * @param handle The USB device handle. + * @param message The endpoint callback message + * @param callbackParam The parameter of the callback. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCdcAcmInterruptIn(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_status_t error = kStatus_USB_Error; + + return error; +} + +/*! + * @brief Bulk in pipe callback function. + * + * This function serves as the callback function for bulk in pipe. + * + * @param handle The USB device handle. + * @param message The endpoint callback message + * @param callbackParam The parameter of the callback. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCdcAcmBulkIn(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_status_t error = kStatus_USB_Error; + + if ((message->length != 0) && (!(message->length % s_usbBulkMaxPacketSize))) + { + /* If the last packet is the size of endpoint, then send also zero-ended packet, + ** meaning that we want to inform the host that we do not have any additional + ** data, so it can flush the output. + */ + USB_DeviceSendRequest(handle, USB_CDC_VCOM_BULK_IN_ENDPOINT, NULL, 0); + } + else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions)) + { + if ((message->buffer != NULL) || ((message->buffer == NULL) && (message->length == 0))) + { + /* User: add your own code for send complete event */ + s_sendComplete = 1; +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; +#endif + } + } + else if ((0 == s_sendComplete) && (1 == s_cdcVcom.attach) && (0 == s_cdcVcom.startTransactions)) + { + s_sendComplete = 1; + } + else + { + } + return error; +} + +/*! + * @brief Bulk out pipe callback function. + * + * This function serves as the callback function for bulk out pipe. + * + * @param handle The USB device handle. + * @param message The endpoint callback message + * @param callbackParam The parameter of the callback. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCdcAcmBulkOut(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_status_t error = kStatus_USB_Error; + if (USB_UNINITIALIZED_VAL_32 == message->length) + { + s_recvSize = 0xFFFFFFFFU; + } + else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions)) + { + s_recvSize = message->length; +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN |= USB_INTEN_SOFTOKEN_MASK; +#endif + if (!s_recvSize) + { +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; +#endif + } + } + else + { + } + return error; +} + +/*! + * @brief Get the setup packet buffer. + * + * This function provides the buffer for setup packet. + * + * @param handle The USB device handle. + * @param setupBuffer The pointer to the address of setup packet buffer. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer) +{ + static uint32_t cdcVcomSetup[2]; + if (NULL == setupBuffer) + { + return kStatus_USB_InvalidParameter; + } + *setupBuffer = (usb_setup_struct_t *)&cdcVcomSetup; + return kStatus_USB_Success; +} + +/*! + * @brief Get the setup packet data buffer. + * + * This function gets the data buffer for setup packet. + * + * @param handle The USB device handle. + * @param setup The pointer to the setup packet. + * @param length The pointer to the length of the data buffer. + * @param buffer The pointer to the address of setup packet data buffer. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer) +{ + static uint8_t setupOut[8]; + if ((NULL == buffer) || ((*length) > sizeof(setupOut))) + { + return kStatus_USB_InvalidRequest; + } + *buffer = setupOut; + return kStatus_USB_Success; +} + +/*! + * @brief Configure remote wakeup feature. + * + * This function configures the remote wakeup feature. + * + * @param handle The USB device handle. + * @param enable 1: enable, 0: disable. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable) +{ + return kStatus_USB_InvalidRequest; +} + +/*! + * @brief CDC class specific callback function. + * + * This function handles the CDC class specific requests. + * + * @param handle The USB device handle. + * @param setup The pointer to the setup packet. + * @param length The pointer to the length of the data buffer. + * @param buffer The pointer to the address of setup packet data buffer. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + + usb_cdc_acm_info_t *acmInfo = &s_usbCdcAcmInfo; + uint32_t len; + uint16_t *uartBitmap; + if (setup->wIndex != USB_CDC_VCOM_COMM_INTERFACE_INDEX) + { + return error; + } + + switch (setup->bRequest) + { + case USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND: + break; + case USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE: + break; + case USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE: + if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue) + { + *buffer = s_abstractState; + } + else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue) + { + *buffer = s_countryCode; + } + else + { + } + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE: + if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue) + { + *buffer = s_abstractState; + *length = COMM_FEATURE_DATA_SIZE; + } + else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue) + { + *buffer = s_countryCode; + *length = COMM_FEATURE_DATA_SIZE; + } + else + { + } + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE: + break; + case USB_DEVICE_CDC_REQUEST_GET_LINE_CODING: + *buffer = s_lineCoding; + *length = LINE_CODING_SIZE; + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_SET_LINE_CODING: + *buffer = s_lineCoding; + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE: + { + acmInfo->dteStatus = setup->wValue; + /* activate/deactivate Tx carrier */ + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION) + { + acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_TX_CARRIER; + } + else + { + acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_TX_CARRIER; + } + + /* activate carrier and DTE */ + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) + { + acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_RX_CARRIER; + } + else + { + acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_RX_CARRIER; + } + + /* Indicates to DCE if DTE is present or not */ + acmInfo->dtePresent = (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) ? true : false; + + /* Initialize the serial state buffer */ + acmInfo->serialStateBuf[0] = NOTIF_REQUEST_TYPE; /* bmRequestType */ + acmInfo->serialStateBuf[1] = USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF; /* bNotification */ + acmInfo->serialStateBuf[2] = 0x00; /* wValue */ + acmInfo->serialStateBuf[3] = 0x00; + acmInfo->serialStateBuf[4] = 0x00; /* wIndex */ + acmInfo->serialStateBuf[5] = 0x00; + acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */ + acmInfo->serialStateBuf[7] = 0x00; + /* Notifiy to host the line state */ + acmInfo->serialStateBuf[4] = setup->wIndex; + /* Lower byte of UART BITMAP */ + uartBitmap = (uint16_t *)&acmInfo->serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE - 2]; + *uartBitmap = acmInfo->uartState; + len = (uint32_t)(NOTIF_PACKET_SIZE + UART_BITMAP_SIZE); + error = USB_DeviceSendRequest(handle, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT, acmInfo->serialStateBuf, len); + + /* Update status */ + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION) + { + /* To do: CARRIER_ACTIVATED */ + } + else + { + /* To do: CARRIER_DEACTIVATED */ + } + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) + { + /* DTE_ACTIVATED */ + if (1 == s_cdcVcom.attach) + { + s_cdcVcom.startTransactions = 1; +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; +#endif + } + } + else + { + /* DTE_DEACTIVATED */ + if (1 == s_cdcVcom.attach) + { + s_cdcVcom.startTransactions = 0; + } + } + } + break; + case USB_DEVICE_CDC_REQUEST_SEND_BREAK: + break; + default: + break; + } + + return error; +} + +/*! + * @brief USB device callback function. + * + * This function handles the usb device specific requests. + * + * @param handle The USB device handle. + * @param event The USB device event type. + * @param param The parameter of the device specific request. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param) +{ + usb_status_t error = kStatus_USB_Error; + uint8_t *temp8 = (uint8_t *)param; + + switch (event) + { + case kUSB_DeviceEventBusReset: + { + USB_DeviceControlPipeInit(s_cdcVcom.deviceHandle); + s_cdcVcom.attach = 0; +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)) || \ + (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + if (kStatus_USB_Success == + USB_DeviceGetStatus(s_cdcVcom.deviceHandle, kUSB_DeviceStatusSpeed, &s_cdcVcom.speed)) + { + USB_DeviceSetSpeed(handle, s_cdcVcom.speed); + } +#endif + } + break; + case kUSB_DeviceEventSetConfiguration: + if (param) + { + s_cdcVcom.attach = 1; + s_cdcVcom.currentConfiguration = *temp8; + if (USB_CDC_VCOM_CONFIGURE_INDEX == (*temp8)) + { + usb_device_endpoint_init_struct_t epInitStruct; + usb_device_endpoint_callback_struct_t endpointCallback; + + /* Initiailize endpoint for interrupt pipe */ + endpointCallback.callbackFn = USB_DeviceCdcAcmInterruptIn; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 0; + epInitStruct.transferType = USB_ENDPOINT_INTERRUPT; + epInitStruct.endpointAddress = USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | + (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + epInitStruct.maxPacketSize = HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE; + } + else + { + epInitStruct.maxPacketSize = FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE; + } + + USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); + + /* Initiailize endpoints for bulk pipe */ + endpointCallback.callbackFn = USB_DeviceCdcAcmBulkIn; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 0; + epInitStruct.transferType = USB_ENDPOINT_BULK; + epInitStruct.endpointAddress = + USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_IN_PACKET_SIZE; + } + else + { + epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_IN_PACKET_SIZE; + } + + USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); + + endpointCallback.callbackFn = USB_DeviceCdcAcmBulkOut; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 0; + epInitStruct.transferType = USB_ENDPOINT_BULK; + epInitStruct.endpointAddress = + USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + else + { + epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + + USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); + + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + s_usbBulkMaxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + else + { + s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + } + } + break; + default: + break; + } + + return error; +} + +/*! + * @brief USB configure endpoint function. + * + * This function configure endpoint status. + * + * @param handle The USB device handle. + * @param ep Endpoint address. + * @param status A flag to indicate whether to stall the endpoint. 1: stall, 0: unstall. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, uint8_t ep, uint8_t status) +{ + if (status) + { + return USB_DeviceStallEndpoint(handle, ep); + } + else + { + return USB_DeviceUnstallEndpoint(handle, ep); + } +} + +/* See virtual_com.h for documentation of this function. */ +void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count) +{ + while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) + { + __NOP(); + }; + USB_DeviceSendRequest((usb_device_handle)baseAddr, USB_CDC_VCOM_BULK_IN_ENDPOINT, (uint8_t *)buf, count); + while (!s_sendComplete) + { + __NOP(); + }; + s_sendComplete = 0; +} + +/* See virtual_com.h for documentation of this function. */ +status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count) +{ + status_t error = kStatus_Success; + size_t bufIndex = 0U, bytesToReceive = 0U; + assert(count != 0U); + + /* Waiting for the USB ready. */ + while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) + { + __NOP(); + }; + + do + { + /* If no receive request. */ + if (s_recvSize <= 0) + { + if (kStatus_USB_Success != + USB_DeviceRecvRequest(baseAddr, USB_CDC_VCOM_BULK_OUT_ENDPOINT, s_currRecvBuf, s_usbBulkMaxPacketSize)) + { + return kStatus_Fail; + } + s_currRecvIndex = 0; + } + /* Waiting for data received by virtual com. */ + while (s_recvSize <= 0) + { + __NOP(); + }; + + /* When receive request is error. */ + if (0xFFFFFFFFU == s_recvSize) + { + /* Waiting for the USB ready and transfer started. */ + while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) + { + __NOP(); + }; + s_recvSize = 0; + } + else + { + bytesToReceive = MIN(count, s_recvSize); + memcpy((void *)&buf[bufIndex], s_currRecvBuf + s_currRecvIndex, bytesToReceive); + count -= bytesToReceive; + s_recvSize -= bytesToReceive; + bufIndex += bytesToReceive; + s_currRecvIndex += bytesToReceive; + } + } while (0U != count); + return error; +} + +/* See virtual_com.h for documentation of this function. */ +usb_device_handle USB_VcomInit(void) +{ + usb_device_handle deviceHandle = NULL; + + USB_DeviceClockInit(); + +#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U)) + SYSMPU_Enable(SYSMPU, 0); +#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ + + s_cdcVcom.speed = USB_SPEED_FULL; + s_cdcVcom.attach = 0; + s_cdcVcom.deviceHandle = NULL; + + if (kStatus_USB_Success != USB_DeviceInit(CONTROLLER_ID, USB_DeviceCallback, &s_cdcVcom.deviceHandle)) + { + deviceHandle = NULL; + } + else + { + deviceHandle = s_cdcVcom.deviceHandle; + USB_DeviceIsrEnable(); + USB_DeviceRun(s_cdcVcom.deviceHandle); + } + return deviceHandle; +} + +/* See virtual_com.h for documentation of this function. */ +void USB_VcomDeinit(usb_device_handle deviceHandle) +{ + USB_DeviceStop(deviceHandle); + USB_DeviceDeinit(deviceHandle); + s_cdcVcom.deviceHandle = NULL; +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) + USB_EhciPhyDeinit(CONTROLLER_ID); +#endif +#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0) + CLOCK_DisableUsbfs0Clock(); +#endif +#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) + /* enable USB IP clock, user code. */ + CLOCK_DisableClock(kCLOCK_Usbd0); +#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +/* enable USB IP clock,user code. */ +#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */ +} diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/virtual_com.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/virtual_com.h new file mode 100644 index 0000000000..37ea3051f8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/utilities/virtual_com.h @@ -0,0 +1,175 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _USB_CDC_VCOM_H_ +#define _USB_CDC_VCOM_H_ 1 + +#include "usb_device_descriptor.h" +#include "fsl_common.h" + +/******************************************************************************* +* Definitions +******************************************************************************/ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) +#define CONTROLLER_ID kUSB_ControllerEhci0 +#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_EHCI */ + +#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0) +#define CONTROLLER_ID kUSB_ControllerKhci0 +#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_KHCI */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 +#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 +#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 +#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE + +#endif + +#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 +#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif + +#define USB_DEVICE_INTERRUPT_PRIORITY (3U) + +/* Currently configured line coding */ +#define LINE_CODING_SIZE (0x07) +#define LINE_CODING_DTERATE (115200) +#define LINE_CODING_CHARFORMAT (0x00) +#define LINE_CODING_PARITYTYPE (0x00) +#define LINE_CODING_DATABITS (0x08) + +/* Communications feature */ +#define COMM_FEATURE_DATA_SIZE (0x02) +#define STATUS_ABSTRACT_STATE (0x0000) +#define COUNTRY_SETTING (0x0000) + +/* Notification of serial state */ +#define NOTIF_PACKET_SIZE (0x08) +#define UART_BITMAP_SIZE (0x02) +#define NOTIF_REQUEST_TYPE (0xA1) + +/* Define the types for application */ +typedef struct _usb_cdc_vcom_struct +{ + usb_device_handle deviceHandle; /* USB device handle. */ + volatile uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */ + uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */ + volatile uint8_t + startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */ + uint8_t currentConfiguration; /* Current configuration value. */ + uint8_t currentInterfaceAlternateSetting + [USB_CDC_VCOM_INTERFACE_COUNT]; /* Current alternate setting value for each interface. */ +} usb_cdc_vcom_struct_t; + +/* Define the infomation relates to abstract control model */ +typedef struct _usb_cdc_acm_info +{ + uint8_t serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE]; /* Serial state buffer of the CDC device to notify the + serial state to host. */ + bool dtePresent; /* A flag to indicate whether DTE is present. */ + uint16_t breakDuration; /* Length of time in milliseconds of the break signal */ + uint8_t dteStatus; /* Status of data terminal equipment */ + uint8_t currentInterface; /* Current interface index. */ + uint16_t uartState; /* UART state of the CDC device. */ +} usb_cdc_acm_info_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Application initialization function. + * + * This function initializes the application. + * + * @return pointer to USB device handle. + */ +usb_device_handle USB_VcomInit(void); + +/*! + * @brief Application initialization function. + * + * This function initializes the application. + * + * @return pointer to USB device handle. + */ +void USB_VcomDeinit(usb_device_handle deviceHandle); + +/*! + * @brief USB recive data from host using a blocking method. + * + * This function recives data from host by usb cdc protocol + * @param baseAddr pointer to USB device handle. + * @param buf pointer to the data. + * @param count size of the transfer. + * + * @return A USB error code or kStatus_USB_Success. + */ +status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count); + +/*! + * @brief USB recive 'count' number of data from host using a blocking method. + * + * This function recives data from host by usb cdc protocol + * @param baseAddr pointer to USB device handle. + * @param buf pointer to the data. + * @param count size of the transfer. + * + * @return A USB error code or kStatus_USB_Success. + */ +status_t USB_VcomReadPolling(usb_device_handle baseAddr, uint8_t *buf, size_t count); + +/*! + * @brief USB send data to host using a blocking method. + * + * This function sends data to host by usb cdc protocol + * @param baseAddr pointer to USB device handle. + * @param buf pointer to the data. + * @param count size of the transfer. + * + * @return None. + */ +void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count); + +#endif /* _USB_CDC_VCOM_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_flexspi_nor_config.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_flexspi_nor_config.c new file mode 100644 index 0000000000..24fe770b11 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_flexspi_nor_config.c @@ -0,0 +1,76 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "evkbimxrt1050_flexspi_nor_config.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t hyperflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_flexspi_nor_config.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_flexspi_nor_config.h new file mode 100644 index 0000000000..67e93b3920 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_flexspi_nor_config.h @@ -0,0 +1,296 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ +#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.c new file mode 100644 index 0000000000..452e76e503 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.c @@ -0,0 +1,1126 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "evkbimxrt1050_sdram_ini_dcd.h" + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = { + /*0000*/ DCD_TAG_HEADER, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x09, +}; +#else +/************************************* + * DCD Data + *************************************/ +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.h new file mode 100644 index 0000000000..51fa34e599 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.h @@ -0,0 +1,47 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__ +#define __EVKBIMXRT1050_DCD_SDRAM_INIT__ + +#include + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000000..d52cfa3572 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,72 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; +#endif + + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000000..2d21242e0c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,131 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include +#include "board.h" + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +/* IVT header */ +#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) + +/* Set resume entry */ +#if defined(__CC_ARM) + extern uint32_t __Vectors[]; + extern uint32_t Image$$RW_m_config_text$$Base[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#elif defined(__MCUXPRESSO) + extern uint32_t __Vectors[]; + extern uint32_t __boot_hdr_start__[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)__boot_hdr_start__) +#elif defined(__ICCARM__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t m_boot_hdr_conf_start[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __FLASH_BASE[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#endif + +#define DCD_ADDRESS dcd_data +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define IVT_RSVD (uint32_t)(0x00000000) + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + +#define FLASH_SIZE BOARD_FLASH_SIZE +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +const BOOT_DATA_T boot_data; +extern const uint8_t dcd_data[]; + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ + diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/SConscript b/bsp/imxrt/Libraries/imxrt1050/devices/SConscript new file mode 100644 index 0000000000..744d8d7821 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/devices/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript new file mode 100644 index 0000000000..fa1b4693f5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript @@ -0,0 +1,74 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +drv_uart.c +drv_cache.c +""") + +CPPPATH = [cwd] +CPPDEFINES = [] + +# add sdram driver code +if GetDepend('RT_USING_SDRAM'): + src = src + ['drv_sdram.c'] + +# add pin driver code +if GetDepend('RT_USING_PIN'): + src += ['drv_pin.c'] + +# add rtc driver code +if GetDepend('RT_USING_RTC_HP'): + src = src + ['drv_rtc.c'] + +# add spibus driver code +if GetDepend('RT_USING_SPI'): + src += ['drv_spi_bus.c'] + +# add spi flash driver code +if GetDepend('RT_USING_SPI_FLASH'): + src += ['drv_spi_flash.c'] + +# add i2cbus driver code +if GetDepend('RT_USING_I2C'): + src += ['drv_i2c.c'] + +# add lcd driver code +if GetDepend('RT_USING_LCD'): + src += ['drv_lcd.c'] + +# add sdio driver code +if GetDepend('RT_USING_SDIO'): + src += ['drv_sdio.c'] + +# add usb device driver code +if GetDepend('RT_USING_USB_DEVICE'): + src += ['drv_usbd.c'] + src += Glob('usb/device/*.c') +# add usb phy driver code +if GetDepend('RT_USING_USB_DEVICE'): + src += Glob('usb/phy/*.c') + CPPDEFINES += ['ENDIANNESS'] + +if GetDepend('BOARD_RT1050_EVK'): + if GetDepend('RT_USING_LWIP'): + src += ['drv_eth.c', 'fsl_phy.c'] + CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE'] + +if GetDepend('BOARD_RT1050_FIRE') and GetDepend('RT_USING_LWIP'): + src += ['drv_eth.c', 'fsl_phy.c'] + +if GetDepend('BOARD_RT1050_ATK') and GetDepend('RT_USING_LWIP'): + src += ['drv_eth.c', 'fsl_phy.c', 'drv_pcf8574.c'] + +if GetDepend('RT_USING_AUDIO'): + src += ['drv_codec.c', 'fsl_wm8960.c'] + +if GetDepend('PKG_USING_GUIENGINE'): + src += Glob('touch/*.c') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c new file mode 100644 index 0000000000..4f88e769c4 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-02 tanek first implementation + */ + +#include +#include +#include + +void rt_hw_cpu_icache_enable(void) +{ + SCB_EnableICache(); +} + +void rt_hw_cpu_icache_disable(void) +{ + SCB_DisableICache(); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +void rt_hw_cpu_icache_ops(int ops, void* addr, int size) +{ + if (ops & RT_HW_CACHE_INVALIDATE) + { + ICACHE_InvalidateByRange((uint32_t)addr, size); + } +} + +void rt_hw_cpu_dcache_enable(void) +{ + SCB_EnableDCache(); +} + +void rt_hw_cpu_dcache_disable(void) +{ + SCB_DisableDCache(); +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) +{ + if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) + { + DCACHE_CleanInvalidateByRange((uint32_t)addr, size); + } + else if (ops & RT_HW_CACHE_FLUSH) + { + DCACHE_CleanByRange((uint32_t)addr, size); + } + else if (ops & RT_HW_CACHE_INVALIDATE) + { + DCACHE_InvalidateByRange((uint32_t)addr, size); + } + else + { + RT_ASSERT(0); + } +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_codec.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_codec.c new file mode 100644 index 0000000000..8d5d657f18 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_codec.c @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include +#include +#include + +#include "board.h" +#include "drv_codec.h" +#include "fsl_wm8960.h" + +#include +#include +#include +#include + +#define DEMO_CODEC_WM8960 +#define DEMO_SAI SAI1 +#define DEMO_SAI_IRQ SAI1_IRQn +#define SAI_TxIRQHandler SAI1_IRQHandler + +/* Select Audio/Video PLL (786.48 MHz) as sai1 clock source */ +#define DEMO_SAI1_CLOCK_SOURCE_SELECT (2U) +/* Clock pre divider for sai1 clock source */ +#define DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER (1U) +/* Clock divider for sai1 clock source */ +#define DEMO_SAI1_CLOCK_SOURCE_DIVIDER (63U) +/* Get frequency of sai1 clock */ +#define DEMO_SAI_CLK_FREQ (CLOCK_GetFreq(kCLOCK_AudioPllClk) / (DEMO_SAI1_CLOCK_SOURCE_DIVIDER + 1U) / (DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER + 1U)) + +/* I2C instance and clock */ +#define DEMO_I2C LPI2C1 + +/* Select USB1 PLL (480 MHz) as master lpi2c clock source */ +#define DEMO_LPI2C_CLOCK_SOURCE_SELECT (0U) +/* Clock divider for master lpi2c clock source */ +#define DEMO_LPI2C_CLOCK_SOURCE_DIVIDER (5U) +/* Get frequency of lpi2c clock */ +#define DEMO_I2C_CLK_FREQ ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (DEMO_LPI2C_CLOCK_SOURCE_DIVIDER + 1U)) + +/* DMA */ +#define DMAMUX0 DMAMUX +#define EXAMPLE_DMA DMA0 +#define EXAMPLE_CHANNEL (0U) +#define EXAMPLE_SAI_TX_SOURCE kDmaRequestMuxSai1Tx + +struct imxcodec +{ + I2S_Type *sai; + sai_edma_handle_t txHandle; + wm8960_handle_t codecHandle; + edma_handle_t dmaHandle; + lpi2c_master_handle_t i2cHandle; + sai_transfer_format_t format; +}; + +static void _InitPins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1); + + IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0u); + IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0u); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u); +} + +static void BOARD_EnableSaiMclkOutput(bool enable) +{ + if (enable) + { + IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK; + } + else + { + IOMUXC_GPR->GPR1 &= (~IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK); + } +} + +static void saidma_callback(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData) +{ + int ind = 0; + rt_uint8_t *saddr; + + ind = handle->queueDriver; + saddr = (rt_uint8_t*)handle->saiQueue[ind].data; + rt_audio_tx_complete(userData, saddr); +} + +/********************************************************************************************************* +** Audio device +*********************************************************************************************************/ + +static rt_err_t icodec_getcaps(struct rt_audio_device *audio,struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct imxcodec *icodec = (struct imxcodec *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */ + { + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } + + break; + } + case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (audio->replay == NULL) + { + result = -RT_ERROR; + break; + } + caps->udata.config.channels = 1; + caps->udata.config.samplefmt = 1; + caps->udata.config.samplerate = 1; + caps->udata.config.samplefmts = 1; + break; + default: + result = -RT_ERROR; + break; + } + break; + case AUDIO_TYPE_MIXER: /* report the Mixer Units */ + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_DIGITAL | AUDIO_MIXER_LINE; + break; + case AUDIO_MIXER_VOLUME: + caps->udata.value = WM8960_GetVolume(&icodec->codecHandle, kWM8960_ModuleDAC); + break; + case AUDIO_MIXER_DIGITAL: + + break; + case AUDIO_MIXER_LINE: + + break; + default: + result = -RT_ERROR; + break; + } + break; + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t icodec_configure(struct rt_audio_device *audio,struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct imxcodec *icodec = (struct imxcodec *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + { + switch (caps->sub_type) + { + case AUDIO_MIXER_VOLUME: + { + WM8960_SetVolume(&icodec->codecHandle, kWM8960_ModuleDAC, + caps->udata.value); + } + break; + default: + { + result = -RT_ERROR; + } + break; + } + } + break; + case AUDIO_TYPE_OUTPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + + } break; + case AUDIO_DSP_SAMPLERATE: + { + int rate = caps->udata.value; + + icodec->format.sampleRate_Hz = rate; + SAI_TxSetFormat(icodec->sai, &icodec->format, icodec->format.masterClockHz, icodec->format.masterClockHz); + } + break; + default: + { + result = -RT_ERROR; + } + break; + } + } + break; + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t icodec_init(struct rt_audio_device *audio) +{ + sai_config_t config; + uint32_t mclkSourceClockHz = 0U; + edma_config_t dmaConfig = {0}; + lpi2c_master_config_t i2cConfig = {0}; + uint32_t i2cSourceClock; + clock_audio_pll_config_t audioPllConfig = {32, 1, 77, 100}; + struct imxcodec *icodec = audio->parent.user_data; + sai_transfer_format_t *format; + + icodec->sai = DEMO_SAI; + format = &icodec->format; + + _InitPins(); + CLOCK_InitAudioPll(&audioPllConfig); + + /*Clock setting for LPI2C*/ + CLOCK_SetMux(kCLOCK_Lpi2cMux, DEMO_LPI2C_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, DEMO_LPI2C_CLOCK_SOURCE_DIVIDER); + + /*Clock setting for SAI1*/ + CLOCK_SetMux(kCLOCK_Sai1Mux, DEMO_SAI1_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER); + CLOCK_SetDiv(kCLOCK_Sai1Div, DEMO_SAI1_CLOCK_SOURCE_DIVIDER); + + /*Enable MCLK clock*/ + BOARD_EnableSaiMclkOutput(true); + + /* Create EDMA handle */ + EDMA_GetDefaultConfig(&dmaConfig); + EDMA_Init(EXAMPLE_DMA, &dmaConfig); + EDMA_CreateHandle(&icodec->dmaHandle, EXAMPLE_DMA, EXAMPLE_CHANNEL); + + DMAMUX_Init(DMAMUX0); + DMAMUX_SetSource(DMAMUX0, EXAMPLE_CHANNEL, EXAMPLE_SAI_TX_SOURCE); + DMAMUX_EnableChannel(DMAMUX0, EXAMPLE_CHANNEL); + + /* Init SAI module */ + SAI_TxGetDefaultConfig(&config); + config.protocol = kSAI_BusLeftJustified; + SAI_TxInit(DEMO_SAI, &config); + + /* Configure the audio format */ + format->bitWidth = kSAI_WordWidth16bits; + format->channel = 0U; + format->sampleRate_Hz = kSAI_SampleRate48KHz; + format->masterClockHz = DEMO_SAI_CLK_FREQ; + format->protocol = config.protocol; + format->stereo = kSAI_Stereo; + format->isFrameSyncCompact = 0; + format->watermark = FSL_FEATURE_SAI_FIFO_COUNT / 2U; + + /* Configure Sgtl5000 I2C */ + icodec->codecHandle.base = DEMO_I2C; + icodec->codecHandle.i2cHandle = &icodec->i2cHandle; + i2cSourceClock = DEMO_I2C_CLK_FREQ; + + LPI2C_MasterGetDefaultConfig(&i2cConfig); + LPI2C_MasterInit(DEMO_I2C, &i2cConfig, i2cSourceClock); + LPI2C_MasterTransferCreateHandle(DEMO_I2C, &icodec->i2cHandle, NULL, NULL); + + WM8960_Init(&icodec->codecHandle, NULL); + WM8960_ConfigDataFormat(&icodec->codecHandle, format->masterClockHz, format->sampleRate_Hz, format->bitWidth); + + SAI_TransferTxCreateHandleEDMA(icodec->sai, &icodec->txHandle, saidma_callback, audio, &icodec->dmaHandle); + + mclkSourceClockHz = DEMO_SAI_CLK_FREQ; + SAI_TransferTxSetFormatEDMA(icodec->sai, &icodec->txHandle, format, mclkSourceClockHz, format->masterClockHz); + + return RT_EOK; +} + +static rt_err_t icodec_shutdown(struct rt_audio_device *audio) +{ + return RT_EOK; +} + +rt_err_t icodec_start(struct rt_audio_device *audio,int stream) +{ + return RT_EOK; +} + +rt_err_t icodec_stop(struct rt_audio_device *audio,int stream) +{ + return RT_EOK; +} + +static rt_err_t icodec_suspend(struct rt_audio_device *audio,int stream) +{ + return RT_EOK; +} + +static rt_err_t icodec_resume(struct rt_audio_device *audio,int stream) +{ + return RT_EOK; +} + +static rt_err_t icodec_control (struct rt_audio_device *audio, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + switch (cmd) + { + case AUDIO_CTL_HWRESET: + + break; + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_size_t icodec_transmit(struct rt_audio_device *audio, const void *writeBuf, void *readBuf, rt_size_t size) +{ + struct imxcodec *icodec = (struct imxcodec *)audio->parent.user_data; + + if(writeBuf != RT_NULL) + { + sai_transfer_t xfer; + + xfer.data = (uint8_t *)writeBuf; + xfer.dataSize = size; + if (size%32 == 0) + icodec->txHandle.count = 16; + else + icodec->txHandle.count = 1; + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)writeBuf, size); + if (SAI_TransferSendEDMA(icodec->sai, &icodec->txHandle, &xfer) != kStatus_Success) + return 0; + + return size; + } + + return 0; +} + +static struct imxcodec _g_imxcodec; +static struct rt_audio_device _g_audio_device; +const struct rt_audio_ops _g_audio_ops = +{ + .getcaps = icodec_getcaps, + .configure = icodec_configure, + + .init = icodec_init, + .shutdown = icodec_shutdown, + .start = icodec_start, + .stop = icodec_stop, + .suspend = icodec_suspend, + .resume = icodec_resume, + .control = icodec_control, + + .transmit = icodec_transmit, +}; + +int rt_hw_codec_init(void) +{ + int result; + struct rt_audio_device *audio = &_g_audio_device; + + audio->ops = (struct rt_audio_ops*)&_g_audio_ops; + _g_imxcodec.sai = DEMO_SAI; + result = rt_audio_register(audio,"sound0", RT_DEVICE_FLAG_WRONLY, &_g_imxcodec); + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_codec_init); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_codec.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_codec.h new file mode 100644 index 0000000000..4fd3869e53 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_codec.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#ifndef __DRV_CODEC_H__ +#define __DRV_CODEC_H__ + +#define SUNXI_DAC_DPC 0x00 +#define SUNXI_DAC_FIFOC 0x04 +#define SUNXI_DAC_FIFOS 0x08 +#define SUNXI_DAC_TXDATA 0x0c +#define SUNXI_ADC_FIFOC 0x10 +#define SUNXI_ADC_FIFOS 0x14 +#define SUNXI_ADC_RXDATA 0x18 +#define DAC_MIXER_CTRL 0x20 +#define ADC_MIXER_CTRL 0x24 +#define ADDA_TUNE 0x28 +#define BIAS_DA16_CAL_CTRL0 0x2C +#define BIAS_DA16_CAL_CTRL1 0x34 + +#define SUNXI_DAC_CNT 0x40 +#define SUNXI_ADC_CNT 0x44 +#define SUNXI_DAC_DG 0x48 +#define SUNXI_ADC_DG 0x4c + +#define AC_PR_CFG 0x400 + +/*AC_DAC_DPC:0x00*/ +#define EN_DAC 31 +#define MODQU 25 +#define DWA 24 +#define HPF_EN 18 +#define DVOL 12 +/*#define HUB_EN 0 */ + +/*AC_DAC_FIFOC:0x04*/ +#define DAC_FS 29 +#define FIR_VER 28 +#define SEND_LASAT 26 +#define FIFO_MODE 24 +#define DAC_DRQ_CLR_CNT 21 +#define TX_TRIG_LEVEL 8 +#define ADDA_LOOP_EN 7 +#define DAC_MONO_EN 6 +#define TX_SAMPLE_BITS 5 +#define DAC_DRQ_EN 4 +#define DAC_IRQ_EN 3 +#define FIFO_UNDERRUN_IRQ_EN 2 +#define FIFO_OVERRUN_IRQ_EN 1 +#define FIFO_FLUSH 0 + +/*AC_ADC_FIFOC:0x10*/ +#define ADFS 29 +#define EN_AD 28 +#define RX_FIFO_MODE 24 +#define ADCDFEN 16 +#define RX_FIFO_TRG_LEVEL 8 +#define ADC_MONO_EN 7 +#define RX_SAMPLE_BITS 6 +#define ADC_DRQ_EN 4 +#define ADC_IRQ_EN 3 +#define ADC_OVERRUN_IRQ_EN 1 +#define ADC_FIFO_FLUSH 0 + +/*DAC_MIXER_CTRL: 0x20*/ +#define DAC_AG_R_EN 31 /* dac right enable bit */ +#define DAC_AG_L_EN 30 /* dac left enable bit */ +#define R_MIXER_EN 29 /* right output mixer */ +#define L_MIXER_EN 28 /* left output mixer */ +#define PH_R_MUTE 27 /* headphone right mute */ +#define PH_L_MUTE 26 /* headphone left mute */ +#define PH_R_PWR_SLT 25 +#define PH_L_PWR_SLT 24 +#define PH_COM_FC 22 +#define PH_COM_PROTEC 21 +#define R_MIXER_MUTE_MIC 20 +#define R_MIXER_MUTE_LINEIN 19 +#define R_MIXER_MUTE_FM 18 +#define R_MIXER_MUTE_R_DAC 17 +#define R_MIXER_MUTE_L_DAC 16 +#define R_MIXER_MUTE 16 +#define HP_POWER_EN 15 +#define L_MIXER_MUTE_MIC 12 +#define L_MIXER_MUTE_LINEIN 11 +#define L_MIXER_MUTE_FM 10 +#define L_MIXER_MUTE_R_DAC 9 +#define L_MIXER_MUTE_L_DAC 8 +#define L_MIXER_MUTE 8 +#define L_HP_TO_R_HP_MUTE 7 +#define R_HP_TO_L_HP_MUTE 6 +#define HP_VOL 0 + +/*ADC_MIXER_CTRL: 0x24*/ +#define ADC_EN 31 /* adc enable bit */ +/* mic in boost stage to L or R output mixer gain control */ +#define MIC_GAIN_CTL 24 +#define LINEIN_VOL 21 /* right output mixer */ +#define ADC_IN_GAIN_CTL 16 /* adc input gain control */ +#define COS_SLOP_TM 14 /* COS slop time control for Anti-pop */ +#define ADC_MIX_MUTE_MIC 13 +#define ADC_MIX_MUTE_FML 12 +#define ADC_MIX_MUTE_FMR 11 +#define ADC_MIX_MUTE_LINEIN 10 +#define ADC_MIX_MUTE_L 9 +#define ADC_MIX_MUTE_R 8 +#define ADC_MIX_MUTE 8 /* ADC mixer mute control */ +#define PA_SPEED_SLT 7 /* PA speed select->0: normal 1: fast */ +#define FM_TO_MIX_GAIN 4 /* FMin to mixer gain control */ +#define MIC_BST_AMP_EN 3 /* MIC boost AMP enable */ +#define MIC_BOST_GAIN 0 /* MIC boast AMP gain control */ + +/*AC_ADC_TXDATA:0x20*/ +#define TX_DATA 0 + +/*AC_DAC_CNT:0x40*/ +#define TX_CNT 0 + +/*AC_ADC_CNT:0x44*/ +#define RX_CNT 0 + +/*AC_DAC_DG:0x48*/ +/* +* DAC Modulator Debug +* 0:DAC Modulator Normal Mode +* 1:DAC Modulator Debug Mode +*/ +#define DAC_MODU_SELECT 11 +/* +* DAC Pattern Select +* 00:Normal(Audio sample from TX fifo) +* 01: -6 dB sin wave +* 10: -60 dB sin wave +* 11: silent wave +*/ +#define DAC_PATTERN_SELECT 9 +/* +* CODEC Clock Source Select +* 0:codec clock from PLL +* 1:codec clock from OSC(for debug) +*/ +#define CODEC_CLK_SELECT 8 +/* +* DAC output channel swap enable +* 0:disable +* 1:enable +*/ +#define DA_SWP 6 + +/*AC_ADC_DG:0x4c*/ +#define AD_SWP 24 + +/*AC_PR_CFG:0x400*/ +#define AC_PR_RST 28 +#define AC_PR_RW 24 +#define AC_PR_ADDR 16 +#define ADDA_PR_WDAT 8 +#define ADDA_PR_RDAT 0 + + +#define R6_REG_CCU_BASE 0x01c20000 +#define R6_REG_PLL_AUDIO_CTRL (R6_REG_CCU_BASE + 0x008) +#define R6_REG_BUS_CLK_GATING_0 (R6_REG_CCU_BASE + 0x060) +#define R6_REG_BUS_CLK_GATING_1 (R6_REG_CCU_BASE + 0x064) +#define R6_REG_BUS_CLK_GATING_2 (R6_REG_CCU_BASE + 0x068) +#define R6_REG_AUDIO_CODEC_CLK (R6_REG_CCU_BASE + 0x140) +#define R6_REG_BUS_SOFT_RST_0 (R6_REG_CCU_BASE + 0x02C0) +#define R6_REG_BUS_SOFT_RST_1 (R6_REG_CCU_BASE + 0x02C4) +#define R6_REG_BUS_SOFT_RST_2 (R6_REG_CCU_BASE + 0x02D0) + +#define R6_REG_PIO_BASE 0x01c20800 +#define R6_REG_PD_CFG0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X00)) +#define R6_REG_PD_CFG1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X04)) +#define R6_REG_PD_CFG2 (R6_REG_PIO_BASE + (3 * 0x24 + 0X08)) +#define R6_REG_PD_CFG3 (R6_REG_PIO_BASE + (3 * 0x24 + 0X0c)) +#define R6_REG_PD_DATA (R6_REG_PIO_BASE + (3 * 0x24 + 0X10)) +#define R6_REG_PD_DRV0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X14)) +#define R6_REG_PD_DRV1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X18)) +#define R6_REG_PD_PUL0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X1c)) +#define R6_REG_PD_PUL1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X20)) + +#define R6_REG_AC_BASE 0x01c23c00 +#define R6_REG_AC_DAC_DPC (R6_REG_AC_BASE + 0x00) +#define R6_REG_AC_DAC_FIFOC (R6_REG_AC_BASE + 0x04) +#define R6_REG_AC_DAC_FIFOS (R6_REG_AC_BASE + 0x08) +#define R6_REG_AC_DAC_TXDADA (R6_REG_AC_BASE + 0x0c) +#define R6_REG_AC_ADC_FIFOC (R6_REG_AC_BASE + 0x10) +#define R6_REG_AC_ADC_FIFOS (R6_REG_AC_BASE + 0x14) +#define R6_REG_AC_ADC_RXDADA (R6_REG_AC_BASE + 0x18) +#define R6_REG_DAC_MIXER_CTRL (R6_REG_AC_BASE + 0x20) +#define R6_REG_ADC_MIXER_CTRL (R6_REG_AC_BASE + 0x24) +#define R6_REG_AC_DAC_CNT (R6_REG_AC_BASE + 0x40) + +#define R6_REG_NDMA_0_BASE (0x01c02000 + 0x100 + 0 * 0x20) + +#define R6_REG_DMA_INT_CTRL (0x01c02000 + 0x00) +#define R6_REG_DMA_INT_STA (0x01c02000 + 0x04) +#define R6_REG_DMA_PTY_CFG (0x01c02000 + 0x08) +#define REG_NDMA_CFG (0x0) +#define REG_NDMA_SRC_ADR (0x4) +#define REG_NDMA_DES_ADR (0x8) +#define REG_NDMA_BYTE_CNT (0xc) + +#define NDMA_CFG_SRC_DRQ_IR_RX (0x00 << 0) +#define NDMA_CFG_SRC_DRQ_NONE (0x01 << 0) +#define NDMA_CFG_SRC_DRQ_SDRAM (0x11 << 0) + +#define NDMA_CFG_DST_LINEAR (0x00 << 21) + +#define NDMA_CFG_DST_DRQ_IR_RX (0x00 << 16) +#define NDMA_CFG_DST_DRQ_NONE (0x01 << 16) +#define NDMA_CFG_DST_DRQ_SRAM (0x10 << 16) +#define NDMA_CFG_DST_DRQ_SDRAM (0x11 << 16) + +#define NDMA_CFG_SRC_DRQ_SRAM (0x10 << 0) +#define NDMA_CFG_SRC_LINEAR (0x00 << 5) +#define NDMA_CFG_SRC_BST4_WIDTH32 ((0x1 << 7) | (0x2 << 8)) +#define NDMA_CFG_DST_DRQ_CODEC (0x0c << 16) +#define NDMA_CFG_DST_IO (0x1 << 21) +#define NDMA_CFG_DST_BST4_WIDTH32 ((0x1 << 23) | (0x2 << 24)) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c new file mode 100644 index 0000000000..54666a7b1c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c @@ -0,0 +1,1426 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-06-08 tanek first implementation + */ +#include +#include "board.h" +#include + +#ifdef RT_USING_FINSH + #include +#endif + +#include "fsl_enet.h" +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" +#include "fsl_phy.h" +#include "fsl_cache.h" + +#ifdef RT_USING_LWIP + +#include +#include "lwipopts.h" + +#ifdef BOARD_RT1050_ATK + #include "drv_pcf8574.h" +#endif + +#define ENET_RXBD_NUM (4) +#define ENET_TXBD_NUM (4) +#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) +#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) + +#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) + #define PHY_ADDRESS 0x00u +#endif + +#if defined(BOARD_RT1050_EVK) + #define PHY_ADDRESS 0x02u +#endif +/* debug option */ +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP + +#define DBG_ENABLE +#define DBG_SECTION_NAME "ETH" +#define DBG_COLOR +#define DBG_LEVEL DBG_INFO +#include + +#define MAX_ADDR_LEN 6 + +struct rt_imxrt_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; + + enet_handle_t enet_handle; + ENET_Type *enet_base; + enet_data_error_stats_t error_statistic; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + + rt_bool_t tx_is_waiting; + struct rt_semaphore tx_wait; + + enet_mii_speed_t speed; + enet_mii_duplex_t duplex; +}; + +ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable"); +ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; + +ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable"); +ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; + +static struct rt_imxrt_eth imxrt_eth_device; + +void _enet_rx_callback(struct rt_imxrt_eth *eth) +{ + rt_err_t result; + + ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt); + + result = eth_device_ready(&(eth->parent)); + if (result != RT_EOK) + rt_kprintf("RX err =%d\n", result); +} + +void _enet_tx_callback(struct rt_imxrt_eth *eth) +{ + if (eth->tx_is_waiting == RT_TRUE) + { + eth->tx_is_waiting = RT_FALSE; + rt_sem_release(ð->tx_wait); + } +} + +void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) +{ + switch (event) + { + case kENET_RxEvent: + + _enet_rx_callback((struct rt_imxrt_eth *)userData); + break; + + case kENET_TxEvent: + _enet_tx_callback((struct rt_imxrt_eth *)userData); + break; + + case kENET_ErrEvent: + //rt_kprintf("kENET_ErrEvent\n"); + break; + + case kENET_WakeUpEvent: + //rt_kprintf("kENET_WakeUpEvent\n"); + break; + + case kENET_TimeStampEvent: + //rt_kprintf("kENET_TimeStampEvent\n"); + break; + + case kENET_TimeStampAvailEvent: + //rt_kprintf("kENET_TimeStampAvailEvent \n"); + break; + + default: + //rt_kprintf("unknow error\n"); + break; + } +} +#if defined(BOARD_RT1050_EVK) +static void evk_enet_io_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +} +#endif + +#ifdef BOARD_RT1050_ATK +static void atk_enet_io_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_14_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0); /* Software Input On Field: Input Path is determined by functionality */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_14_ENET_MDC, + 0x110F9); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_15_ENET_MDIO, + 0x110F9); + + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); + IOMUXC_GPR->GPR1 |= 1 << 23; + +} +#endif + +#ifdef BOARD_RT1050_FIRE +static void fire_enet_io_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_04_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); + /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_04_ENET_MDC, + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_15_ENET_MDIO, + 0xB829u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +} +#endif +static void _enet_clk_init(void) +{ + const clock_enet_pll_config_t config = {true, false, 1}; + CLOCK_InitEnetPll(&config); + + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); +} + +static void _delay(void) +{ + volatile int i = 1000000; + + while (i--) + i = i; +} + +static void _enet_phy_reset_by_gpio(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + +#ifndef BOARD_RT1050_ATK + GPIO_PinInit(GPIO1, 9, &gpio_config); +#endif + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + +#ifdef BOARD_RT1050_ATK + pcf8574_write_bit(7, 1); + _delay(); + pcf8574_write_bit(7, 0); +#else + GPIO_WritePinOutput(GPIO1, 9, 0); + _delay(); + GPIO_WritePinOutput(GPIO1, 9, 1); +#endif +} + +static void _enet_config(void) +{ + enet_config_t config; + uint32_t sysClock; + + /* prepare the buffer configuration. */ + enet_buffer_config_t buffConfig = + { + ENET_RXBD_NUM, + ENET_TXBD_NUM, + SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), + SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT), + &g_rxBuffDescrip[0], + &g_txBuffDescrip[0], + &g_rxDataBuff[0][0], + &g_txDataBuff[0][0], + }; + + /* Get default configuration. */ + /* + * config.miiMode = kENET_RmiiMode; + * config.miiSpeed = kENET_MiiSpeed100M; + * config.miiDuplex = kENET_MiiFullDuplex; + * config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; + */ + ENET_GetDefaultConfig(&config); + config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; + //config.interrupt = 0xFFFFFFFF; + config.miiSpeed = imxrt_eth_device.speed; + config.miiDuplex = imxrt_eth_device.duplex; + + /* Set SMI to get PHY link status. */ + sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); + + LOG_D("deinit"); + ENET_Deinit(imxrt_eth_device.enet_base); + LOG_D("init"); + ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); + LOG_D("set call back"); + ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); + LOG_D("active read"); + ENET_ActiveRead(imxrt_eth_device.enet_base); +} + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +static void packet_dump(const char *msg, const struct pbuf *p) +{ + const struct pbuf *q; + rt_uint32_t i, j; + rt_uint8_t *ptr; + + rt_kprintf("%s %d byte\n", msg, p->tot_len); + + i = 0; + for (q = p; q != RT_NULL; q = q->next) + { + ptr = q->payload; + + for (j = 0; j < q->len; j++) + { + if ((i % 8) == 0) + { + rt_kprintf(" "); + } + if ((i % 16) == 0) + { + rt_kprintf("\r\n"); + } + rt_kprintf("%02x ", *ptr); + + i++; + ptr++; + } + } + + rt_kprintf("\n\n"); +} +#else +#define packet_dump(...) +#endif /* dump */ + +/* initialize the interface */ +static rt_err_t rt_imxrt_eth_init(rt_device_t dev) +{ + LOG_D("rt_imxrt_eth_init..."); + _enet_config(); + + return RT_EOK; +} + +static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("rt_imxrt_eth_open..."); + return RT_EOK; +} + +static rt_err_t rt_imxrt_eth_close(rt_device_t dev) +{ + LOG_D("rt_imxrt_eth_close..."); + return RT_EOK; +} + +static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("rt_imxrt_eth_read..."); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("rt_imxrt_eth_write..."); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) +{ + LOG_D("rt_imxrt_eth_control..."); + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId) +{ + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + switch (ringId) + { + case 0: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->TDAR1 = ENET_TDAR1_TDAR_MASK; + break; + case kENET_Ring2: + base->TDAR2 = ENET_TDAR2_TDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; + } +} + +static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) +{ + assert(handle); + assert(data); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[0]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[0] >= length) + { + /* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + + pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0); + + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ + _ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; + if (sizeleft > handle->txBuffSizeAlign[0]) + { + /* Data copy. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[0]; + len += handle->txBuffSizeAlign[0]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + /* Active the transmit buffer descriptor*/ + _ENET_ActiveSend(base, 0); + } + else + { +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data + len, sizeleft); + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ + _ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[0]; + + } + while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} + +/* ethernet device interface */ +/* transmit packet. */ +rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t result = RT_EOK; + enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; + + RT_ASSERT(p != NULL); + RT_ASSERT(enet_handle != RT_NULL); + + LOG_D("rt_imxrt_eth_tx: %d", p->len); + +#ifdef ETH_TX_DUMP + packet_dump("send", p); +#endif + + do + { + result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len); + + if (result == kStatus_ENET_TxFrameBusy) + { + imxrt_eth_device.tx_is_waiting = RT_TRUE; + rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); + } + + } + while (result == kStatus_ENET_TxFrameBusy); + + return RT_EOK; +} + +/* reception packet. */ +struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) +{ + uint32_t length = 0; + status_t status; + + struct pbuf *p = RT_NULL; + enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle; + ENET_Type *enet_base = imxrt_eth_device.enet_base; + enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; + + /* Get the Frame size */ + status = ENET_GetRxFrameSize(enet_handle, &length); + + /* Call ENET_ReadFrame when there is a received frame. */ + if (length != 0) + { + /* Received valid frame. Deliver the rx buffer with the size equal to length. */ + p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); + + if (p != NULL) + { + status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); + if (status == kStatus_Success) + { +#ifdef ETH_RX_DUMP + packet_dump("recv", p); +#endif + return p; + } + else + { + LOG_D(" A frame read failed"); + pbuf_free(p); + } + } + else + { + LOG_D(" pbuf_alloc faild"); + } + } + else if (status == kStatus_ENET_RxFrameError) + { + LOG_W("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError"); + /* Update the received buffer when error happened. */ + /* Get the error information of the received g_frame. */ + ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); + /* update the receive buffer. */ + ENET_ReadFrame(enet_base, enet_handle, NULL, 0); + } + + ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); + return NULL; +} + +static void phy_monitor_thread_entry(void *parameter) +{ + phy_speed_t speed; + phy_duplex_t duplex; + bool link = false; + + _enet_phy_reset_by_gpio(); + + PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + + while (1) + { + bool new_link = false; + status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); + + if ((status == kStatus_Success) && (link != new_link)) + { + link = new_link; + + if (link) // link up + { + PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, + PHY_ADDRESS, &speed, &duplex); + + if (kPHY_Speed10M == speed) + { + LOG_D("10M"); + } + else + { + LOG_D("100M"); + } + + if (kPHY_HalfDuplex == duplex) + { + LOG_D("half dumplex"); + } + else + { + LOG_D("full dumplex"); + } + + if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) + || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) + { + imxrt_eth_device.speed = (enet_mii_speed_t)speed; + imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; + + LOG_D("link up, and update eth mode."); + rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); + } + else + { + LOG_D("link up, eth not need re-config."); + } + LOG_D("link up."); + eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE); + } + else // link down + { + LOG_D("link down."); + eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); + } + } + + rt_thread_delay(RT_TICK_PER_SECOND * 2); + } +} + +static int rt_hw_imxrt_eth_init(void) +{ + rt_err_t state; + +#ifdef BOARD_RT1050_ATK + atk_enet_io_init(); +#endif + +#ifdef BOARD_RT1050_FIRE + fire_enet_io_init(); +#endif + +#if defined(BOARD_RT1050_EVK) + evk_enet_io_init(); +#endif + _enet_clk_init(); + /* OUI 00-80-E1 STMICROELECTRONICS. */ + imxrt_eth_device.dev_addr[0] = 0x00; + imxrt_eth_device.dev_addr[1] = 0x04; + imxrt_eth_device.dev_addr[2] = 0x9F; + /* generate MAC addr from 96bit unique ID (only for test). */ + imxrt_eth_device.dev_addr[3] = 0x08; + imxrt_eth_device.dev_addr[4] = 0x43; + imxrt_eth_device.dev_addr[5] = 0x75; + + imxrt_eth_device.speed = kENET_MiiSpeed100M; + imxrt_eth_device.duplex = kENET_MiiFullDuplex; + + imxrt_eth_device.enet_base = ENET; + + imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init; + imxrt_eth_device.parent.parent.open = rt_imxrt_eth_open; + imxrt_eth_device.parent.parent.close = rt_imxrt_eth_close; + imxrt_eth_device.parent.parent.read = rt_imxrt_eth_read; + imxrt_eth_device.parent.parent.write = rt_imxrt_eth_write; + imxrt_eth_device.parent.parent.control = rt_imxrt_eth_control; + imxrt_eth_device.parent.parent.user_data = RT_NULL; + + imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx; + imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx; + + LOG_D("sem init: tx_wait\r"); + /* init tx semaphore */ + rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); + + /* register eth device */ + LOG_D("eth_device_init start\r"); + state = eth_device_init(&(imxrt_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("eth_device_init success\r"); + } + else + { + LOG_D("eth_device_init faild: %d\r", state); + } + + eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); + + /* start phy monitor */ + { + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + rt_thread_startup(tid); + } + + return state; +} +#ifdef BOARD_RT1050_ATK + INIT_ENV_EXPORT(rt_hw_imxrt_eth_init); +#else + INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); +#endif +#endif + +#ifdef RT_USING_FINSH +#include + +void phy_read(uint32_t phyReg) +{ + uint32_t data; + status_t status; + + status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data); + if (kStatus_Success == status) + { + rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data); + } + else + { + rt_kprintf("PHY_Read: %02X --> faild", phyReg); + } +} + +void phy_write(uint32_t phyReg, uint32_t data) +{ + status_t status; + + status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data); + if (kStatus_Success == status) + { + rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data); + } + else + { + rt_kprintf("PHY_Write: %02X --> faild\n", phyReg); + } +} + +void phy_dump(void) +{ + uint32_t data; + status_t status; + + int i; + for (i = 0; i < 32; i++) + { + status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data); + if (kStatus_Success != status) + { + rt_kprintf("phy_dump: %02X --> faild", i); + break; + } + + if (i % 8 == 7) + { + rt_kprintf("%02X --> %08X ", i, data); + } + else + { + rt_kprintf("%02X --> %08X\n", i, data); + } + + } +} + +void enet_reg_dump(void) +{ + ENET_Type *enet_base = imxrt_eth_device.enet_base; + +#define DUMP_REG(__REG) \ + rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG) + + DUMP_REG(EIR); + DUMP_REG(EIMR); + DUMP_REG(RDAR); + DUMP_REG(TDAR); + DUMP_REG(ECR); + DUMP_REG(MMFR); + DUMP_REG(MSCR); + DUMP_REG(MIBC); + DUMP_REG(RCR); + DUMP_REG(TCR); + DUMP_REG(PALR); + DUMP_REG(PAUR); + DUMP_REG(OPD); + DUMP_REG(TXIC); + DUMP_REG(RXIC); + DUMP_REG(IAUR); + DUMP_REG(IALR); + DUMP_REG(GAUR); + DUMP_REG(GALR); + DUMP_REG(TFWR); + DUMP_REG(RDSR); + DUMP_REG(TDSR); + DUMP_REG(MRBR); + DUMP_REG(RSFL); + DUMP_REG(RSEM); + DUMP_REG(RAEM); + DUMP_REG(RAFL); + DUMP_REG(TSEM); + DUMP_REG(TAEM); + DUMP_REG(TAFL); + DUMP_REG(TIPG); + DUMP_REG(FTRL); + DUMP_REG(TACC); + DUMP_REG(RACC); + DUMP_REG(RMON_T_DROP); + DUMP_REG(RMON_T_PACKETS); + DUMP_REG(RMON_T_BC_PKT); + DUMP_REG(RMON_T_MC_PKT); + DUMP_REG(RMON_T_CRC_ALIGN); + DUMP_REG(RMON_T_UNDERSIZE); + DUMP_REG(RMON_T_OVERSIZE); + DUMP_REG(RMON_T_FRAG); + DUMP_REG(RMON_T_JAB); + DUMP_REG(RMON_T_COL); + DUMP_REG(RMON_T_P64); + DUMP_REG(RMON_T_P65TO127); + DUMP_REG(RMON_T_P128TO255); + DUMP_REG(RMON_T_P256TO511); + DUMP_REG(RMON_T_P512TO1023); + DUMP_REG(RMON_T_P1024TO2047); + DUMP_REG(RMON_T_P_GTE2048); + DUMP_REG(RMON_T_OCTETS); + DUMP_REG(IEEE_T_DROP); + DUMP_REG(IEEE_T_FRAME_OK); + DUMP_REG(IEEE_T_1COL); + DUMP_REG(IEEE_T_MCOL); + DUMP_REG(IEEE_T_DEF); + DUMP_REG(IEEE_T_LCOL); + DUMP_REG(IEEE_T_EXCOL); + DUMP_REG(IEEE_T_MACERR); + DUMP_REG(IEEE_T_CSERR); + DUMP_REG(IEEE_T_SQE); + DUMP_REG(IEEE_T_FDXFC); + DUMP_REG(IEEE_T_OCTETS_OK); + DUMP_REG(RMON_R_PACKETS); + DUMP_REG(RMON_R_BC_PKT); + DUMP_REG(RMON_R_MC_PKT); + DUMP_REG(RMON_R_CRC_ALIGN); + DUMP_REG(RMON_R_UNDERSIZE); + DUMP_REG(RMON_R_OVERSIZE); + DUMP_REG(RMON_R_FRAG); + DUMP_REG(RMON_R_JAB); + DUMP_REG(RMON_R_RESVD_0); + DUMP_REG(RMON_R_P64); + DUMP_REG(RMON_R_P65TO127); + DUMP_REG(RMON_R_P128TO255); + DUMP_REG(RMON_R_P256TO511); + DUMP_REG(RMON_R_P512TO1023); + DUMP_REG(RMON_R_P1024TO2047); + DUMP_REG(RMON_R_P_GTE2048); + DUMP_REG(RMON_R_OCTETS); + DUMP_REG(IEEE_R_DROP); + DUMP_REG(IEEE_R_FRAME_OK); + DUMP_REG(IEEE_R_CRC); + DUMP_REG(IEEE_R_ALIGN); + DUMP_REG(IEEE_R_MACERR); + DUMP_REG(IEEE_R_FDXFC); + DUMP_REG(IEEE_R_OCTETS_OK); + DUMP_REG(ATCR); + DUMP_REG(ATVR); + DUMP_REG(ATOFF); + DUMP_REG(ATPER); + DUMP_REG(ATCOR); + DUMP_REG(ATINC); + DUMP_REG(ATSTMP); + DUMP_REG(TGSR); +} + +void enet_nvic_tog(void) +{ + NVIC_SetPendingIRQ(ENET_IRQn); +} + +void enet_rx_stat(void) +{ + enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; + +#define DUMP_STAT(__VAR) \ + rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR); + + DUMP_STAT(statsRxLenGreaterErr); + DUMP_STAT(statsRxAlignErr); + DUMP_STAT(statsRxFcsErr); + DUMP_STAT(statsRxOverRunErr); + DUMP_STAT(statsRxTruncateErr); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + DUMP_STAT(statsRxProtocolChecksumErr); + DUMP_STAT(statsRxIpHeadChecksumErr); + DUMP_STAT(statsRxMacErr); + DUMP_STAT(statsRxPhyErr); + DUMP_STAT(statsRxCollisionErr); + DUMP_STAT(statsTxErr); + DUMP_STAT(statsTxFrameErr); + DUMP_STAT(statsTxOverFlowErr); + DUMP_STAT(statsTxLateCollisionErr); + DUMP_STAT(statsTxExcessCollisionErr); + DUMP_STAT(statsTxUnderFlowErr); + DUMP_STAT(statsTxTsErr); +#endif + +} + +void enet_buf_info(void) +{ + int i = 0; + for (i = 0; i < ENET_RXBD_NUM; i++) + { + rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", + i, + g_rxBuffDescrip[i].length, + g_rxBuffDescrip[i].control, + g_rxBuffDescrip[i].buffer); + } + + for (i = 0; i < ENET_TXBD_NUM; i++) + { + rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", + i, + g_txBuffDescrip[i].length, + g_txBuffDescrip[i].control, + g_txBuffDescrip[i].buffer); + } +} + +FINSH_FUNCTION_EXPORT(phy_read, read phy register); +FINSH_FUNCTION_EXPORT(phy_write, write phy register); +FINSH_FUNCTION_EXPORT(phy_dump, dump phy registers); +FINSH_FUNCTION_EXPORT(enet_reg_dump, dump enet registers); +FINSH_FUNCTION_EXPORT(enet_nvic_tog, toggle enet nvic pendding bit); +FINSH_FUNCTION_EXPORT(enet_rx_stat, dump enet rx statistic); +FINSH_FUNCTION_EXPORT(enet_buf_info, dump enet tx and tx buffer descripter); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth_fire.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth_fire.c new file mode 100644 index 0000000000..30b9e13306 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth_fire.c @@ -0,0 +1,1116 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-06-08 tanek first implementation + */ +#include +#include "board.h" +#include + +#ifdef RT_USING_FINSH + #include +#endif + +#include "fsl_enet.h" +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" +#include "fsl_phy_fire.h" +#include "fsl_cache.h" + +#ifdef RT_USING_LWIP + +#include +#include "lwipopts.h" + +#define ENET_RXBD_NUM (4) +#define ENET_TXBD_NUM (4) +#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) +#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) + +#define PHY_ADDRESS 0x00u + +/* debug option */ +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP + +#define DBG_ENABLE +#define DBG_SECTION_NAME "ETH" +#define DBG_COLOR +#define DBG_LEVEL DBG_LOG +#include + +#define MAX_ADDR_LEN 6 + +struct rt_imxrt_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; + + enet_handle_t enet_handle; + ENET_Type *enet_base; + enet_data_error_stats_t error_statistic; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + + rt_bool_t tx_is_waiting; + struct rt_semaphore tx_wait; + + enet_mii_speed_t speed; + enet_mii_duplex_t duplex; +}; + +ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable"); +ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; + +ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable"); +ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; + +static struct rt_imxrt_eth imxrt_eth_device; + +void _enet_rx_callback(struct rt_imxrt_eth *eth) +{ + rt_err_t result; + + ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt); + + result = eth_device_ready(&(eth->parent)); + if (result != RT_EOK) + rt_kprintf("RX err =%d\n", result); +} + +void _enet_tx_callback(struct rt_imxrt_eth *eth) +{ + if (eth->tx_is_waiting == RT_TRUE) + { + eth->tx_is_waiting = RT_FALSE; + rt_sem_release(ð->tx_wait); + } +} + +void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) +{ + switch (event) + { + case kENET_RxEvent: + + _enet_rx_callback((struct rt_imxrt_eth *)userData); + break; + + case kENET_TxEvent: + _enet_tx_callback((struct rt_imxrt_eth *)userData); + break; + + case kENET_ErrEvent: + //rt_kprintf("kENET_ErrEvent\n"); + break; + + case kENET_WakeUpEvent: + //rt_kprintf("kENET_WakeUpEvent\n"); + break; + + case kENET_TimeStampEvent: + //rt_kprintf("kENET_TimeStampEvent\n"); + break; + + case kENET_TimeStampAvailEvent: + //rt_kprintf("kENET_TimeStampAvailEvent \n"); + break; + + default: + //rt_kprintf("unknow error\n"); + break; + } +} + +static void _enet_io_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_04_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_04_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +} + +static void _enet_clk_init(void) +{ + const clock_enet_pll_config_t config = {true, false, 1}; + CLOCK_InitEnetPll(&config); + + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); +} + +static void _delay(void) +{ + volatile int i = 1000000; + + while (i--) + i = i; +} + +static void _enet_phy_reset_by_gpio(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + GPIO_PinInit(GPIO1, 9, &gpio_config); + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + GPIO_WritePinOutput(GPIO1, 9, 0); + _delay(); + GPIO_WritePinOutput(GPIO1, 9, 1); +} + +static void _enet_config(void) +{ + enet_config_t config; + uint32_t sysClock; + + /* prepare the buffer configuration. */ + enet_buffer_config_t buffConfig = + { + ENET_RXBD_NUM, + ENET_TXBD_NUM, + SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), + SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT), + &g_rxBuffDescrip[0], + &g_txBuffDescrip[0], + &g_rxDataBuff[0][0], + &g_txDataBuff[0][0], + }; + + /* Get default configuration. */ + /* + * config.miiMode = kENET_RmiiMode; + * config.miiSpeed = kENET_MiiSpeed100M; + * config.miiDuplex = kENET_MiiFullDuplex; + * config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; + */ + ENET_GetDefaultConfig(&config); + config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; + //config.interrupt = 0xFFFFFFFF; + config.miiSpeed = imxrt_eth_device.speed; + config.miiDuplex = imxrt_eth_device.duplex; + + /* Set SMI to get PHY link status. */ + sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); + + LOG_D("deinit"); + ENET_Deinit(imxrt_eth_device.enet_base); + LOG_D("init"); + ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); + LOG_D("set call back"); + ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); + LOG_D("active read"); + ENET_ActiveRead(imxrt_eth_device.enet_base); +} + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +static void packet_dump(const char *msg, const struct pbuf *p) +{ + const struct pbuf *q; + rt_uint32_t i, j; + rt_uint8_t *ptr; + + rt_kprintf("%s %d byte\n", msg, p->tot_len); + + i = 0; + for (q = p; q != RT_NULL; q = q->next) + { + ptr = q->payload; + + for (j = 0; j < q->len; j++) + { + if ((i % 8) == 0) + { + rt_kprintf(" "); + } + if ((i % 16) == 0) + { + rt_kprintf("\r\n"); + } + rt_kprintf("%02x ", *ptr); + + i++; + ptr++; + } + } + + rt_kprintf("\n\n"); +} +#else +#define packet_dump(...) +#endif /* dump */ + +/* initialize the interface */ +static rt_err_t rt_imxrt_eth_init(rt_device_t dev) +{ + LOG_D("rt_imxrt_eth_init..."); + _enet_config(); + + return RT_EOK; +} + +static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("rt_imxrt_eth_open..."); + return RT_EOK; +} + +static rt_err_t rt_imxrt_eth_close(rt_device_t dev) +{ + LOG_D("rt_imxrt_eth_close..."); + return RT_EOK; +} + +static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("rt_imxrt_eth_read..."); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("rt_imxrt_eth_write..."); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) +{ + LOG_D("rt_imxrt_eth_control..."); + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId) +{ + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + switch (ringId) + { + case 0: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->TDAR1 = ENET_TDAR1_TDAR_MASK; + break; + case kENET_Ring2: + base->TDAR2 = ENET_TDAR2_TDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; + } +} + +static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) +{ + assert(handle); + assert(data); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[0]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[0] >= length) + { + /* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + + pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0); + + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ + _ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; + if (sizeleft > handle->txBuffSizeAlign[0]) + { + /* Data copy. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[0]; + len += handle->txBuffSizeAlign[0]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + /* Active the transmit buffer descriptor*/ + _ENET_ActiveSend(base, 0); + } + else + { +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data + len, sizeleft); + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Active the transmit buffer descriptor. */ + _ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[0]; + + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} + +/* ethernet device interface */ +/* transmit packet. */ +rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t result = RT_EOK; + enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; + + RT_ASSERT(p != NULL); + RT_ASSERT(enet_handle != RT_NULL); + + LOG_D("rt_imxrt_eth_tx: %d", p->len); + +#ifdef ETH_TX_DUMP + packet_dump("send", p); +#endif + + do + { + result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len); + + if (result == kStatus_ENET_TxFrameBusy) + { + imxrt_eth_device.tx_is_waiting = RT_TRUE; + rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); + } + + } + while (result == kStatus_ENET_TxFrameBusy); + + return RT_EOK; +} + +/* reception packet. */ +struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) +{ + uint32_t length = 0; + status_t status; + + struct pbuf *p = RT_NULL; + enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle; + ENET_Type *enet_base = imxrt_eth_device.enet_base; + enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; + + /* Get the Frame size */ + status = ENET_GetRxFrameSize(enet_handle, &length); + + /* Call ENET_ReadFrame when there is a received frame. */ + if (length != 0) + { + /* Received valid frame. Deliver the rx buffer with the size equal to length. */ + p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); + + if (p != NULL) + { + status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); + if (status == kStatus_Success) + { +#ifdef ETH_RX_DUMP + packet_dump("recv", p); +#endif + return p; + } + else + { + LOG_D(" A frame read failed"); + pbuf_free(p); + } + } + else + { + LOG_D(" pbuf_alloc faild"); + } + } + else if (status == kStatus_ENET_RxFrameError) + { + LOG_W("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError"); + /* Update the received buffer when error happened. */ + /* Get the error information of the received g_frame. */ + ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); + /* update the receive buffer. */ + ENET_ReadFrame(enet_base, enet_handle, NULL, 0); + } + + ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); + return NULL; +} + +static void phy_monitor_thread_entry(void *parameter) +{ + phy_speed_t speed; + phy_duplex_t duplex; + bool link = false; + + _enet_phy_reset_by_gpio(); + + PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + + while (1) + { + bool new_link = false; + status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); + + if ((status == kStatus_Success) && (link != new_link)) + { + link = new_link; + + if (link) // link up + { + PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, + PHY_ADDRESS, &speed, &duplex); + + if (kPHY_Speed10M == speed) + { + LOG_D("10M"); + } + else + { + LOG_D("100M"); + } + + if (kPHY_HalfDuplex == duplex) + { + LOG_D("half dumplex"); + } + else + { + LOG_D("full dumplex"); + } + + if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) + || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) + { + imxrt_eth_device.speed = (enet_mii_speed_t)speed; + imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; + + LOG_D("link up, and update eth mode."); + rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); + } + else + { + LOG_D("link up, eth not need re-config."); + } + LOG_D("link up."); + eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE); + } + else // link down + { + LOG_D("link down."); + eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); + } + } + + rt_thread_delay(RT_TICK_PER_SECOND * 2); + } +} + +static int rt_hw_imxrt_eth_init(void) +{ + rt_err_t state; + + _enet_io_init(); + _enet_clk_init(); + + /* OUI 00-80-E1 STMICROELECTRONICS. */ + imxrt_eth_device.dev_addr[0] = 0x00; + imxrt_eth_device.dev_addr[1] = 0x04; + imxrt_eth_device.dev_addr[2] = 0x9F; + /* generate MAC addr from 96bit unique ID (only for test). */ + imxrt_eth_device.dev_addr[3] = 0x05; + imxrt_eth_device.dev_addr[4] = 0x44; + imxrt_eth_device.dev_addr[5] = 0xE5; + + imxrt_eth_device.speed = kENET_MiiSpeed100M; + imxrt_eth_device.duplex = kENET_MiiFullDuplex; + + imxrt_eth_device.enet_base = ENET; + + imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init; + imxrt_eth_device.parent.parent.open = rt_imxrt_eth_open; + imxrt_eth_device.parent.parent.close = rt_imxrt_eth_close; + imxrt_eth_device.parent.parent.read = rt_imxrt_eth_read; + imxrt_eth_device.parent.parent.write = rt_imxrt_eth_write; + imxrt_eth_device.parent.parent.control = rt_imxrt_eth_control; + imxrt_eth_device.parent.parent.user_data = RT_NULL; + + imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx; + imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx; + + LOG_D("sem init: tx_wait\r"); + /* init tx semaphore */ + rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); + + /* register eth device */ + LOG_D("eth_device_init start\r"); + state = eth_device_init(&(imxrt_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("eth_device_init success\r"); + } + else + { + LOG_D("eth_device_init faild: %d\r", state); + } + + eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); + + /* start phy monitor */ + { + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + rt_thread_startup(tid); + } + + return state; +} +INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); +#endif + +#ifdef RT_USING_FINSH +#include + +void phy_read(uint32_t phyReg) +{ + uint32_t data; + status_t status; + + status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data); + if (kStatus_Success == status) + { + rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data); + } + else + { + rt_kprintf("PHY_Read: %02X --> faild", phyReg); + } +} + +void phy_write(uint32_t phyReg, uint32_t data) +{ + status_t status; + + status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data); + if (kStatus_Success == status) + { + rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data); + } + else + { + rt_kprintf("PHY_Write: %02X --> faild\n", phyReg); + } +} + +void phy_dump(void) +{ + uint32_t data; + status_t status; + + int i; + for (i = 0; i < 32; i++) + { + status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data); + if (kStatus_Success != status) + { + rt_kprintf("phy_dump: %02X --> faild", i); + break; + } + + if (i % 8 == 7) + { + rt_kprintf("%02X --> %08X ", i, data); + } + else + { + rt_kprintf("%02X --> %08X\n", i, data); + } + + } +} + +void enet_reg_dump(void) +{ + ENET_Type *enet_base = imxrt_eth_device.enet_base; + +#define DUMP_REG(__REG) \ + rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG) + + DUMP_REG(EIR); + DUMP_REG(EIMR); + DUMP_REG(RDAR); + DUMP_REG(TDAR); + DUMP_REG(ECR); + DUMP_REG(MMFR); + DUMP_REG(MSCR); + DUMP_REG(MIBC); + DUMP_REG(RCR); + DUMP_REG(TCR); + DUMP_REG(PALR); + DUMP_REG(PAUR); + DUMP_REG(OPD); + DUMP_REG(TXIC); + DUMP_REG(RXIC); + DUMP_REG(IAUR); + DUMP_REG(IALR); + DUMP_REG(GAUR); + DUMP_REG(GALR); + DUMP_REG(TFWR); + DUMP_REG(RDSR); + DUMP_REG(TDSR); + DUMP_REG(MRBR); + DUMP_REG(RSFL); + DUMP_REG(RSEM); + DUMP_REG(RAEM); + DUMP_REG(RAFL); + DUMP_REG(TSEM); + DUMP_REG(TAEM); + DUMP_REG(TAFL); + DUMP_REG(TIPG); + DUMP_REG(FTRL); + DUMP_REG(TACC); + DUMP_REG(RACC); + DUMP_REG(RMON_T_DROP); + DUMP_REG(RMON_T_PACKETS); + DUMP_REG(RMON_T_BC_PKT); + DUMP_REG(RMON_T_MC_PKT); + DUMP_REG(RMON_T_CRC_ALIGN); + DUMP_REG(RMON_T_UNDERSIZE); + DUMP_REG(RMON_T_OVERSIZE); + DUMP_REG(RMON_T_FRAG); + DUMP_REG(RMON_T_JAB); + DUMP_REG(RMON_T_COL); + DUMP_REG(RMON_T_P64); + DUMP_REG(RMON_T_P65TO127); + DUMP_REG(RMON_T_P128TO255); + DUMP_REG(RMON_T_P256TO511); + DUMP_REG(RMON_T_P512TO1023); + DUMP_REG(RMON_T_P1024TO2047); + DUMP_REG(RMON_T_P_GTE2048); + DUMP_REG(RMON_T_OCTETS); + DUMP_REG(IEEE_T_DROP); + DUMP_REG(IEEE_T_FRAME_OK); + DUMP_REG(IEEE_T_1COL); + DUMP_REG(IEEE_T_MCOL); + DUMP_REG(IEEE_T_DEF); + DUMP_REG(IEEE_T_LCOL); + DUMP_REG(IEEE_T_EXCOL); + DUMP_REG(IEEE_T_MACERR); + DUMP_REG(IEEE_T_CSERR); + DUMP_REG(IEEE_T_SQE); + DUMP_REG(IEEE_T_FDXFC); + DUMP_REG(IEEE_T_OCTETS_OK); + DUMP_REG(RMON_R_PACKETS); + DUMP_REG(RMON_R_BC_PKT); + DUMP_REG(RMON_R_MC_PKT); + DUMP_REG(RMON_R_CRC_ALIGN); + DUMP_REG(RMON_R_UNDERSIZE); + DUMP_REG(RMON_R_OVERSIZE); + DUMP_REG(RMON_R_FRAG); + DUMP_REG(RMON_R_JAB); + DUMP_REG(RMON_R_RESVD_0); + DUMP_REG(RMON_R_P64); + DUMP_REG(RMON_R_P65TO127); + DUMP_REG(RMON_R_P128TO255); + DUMP_REG(RMON_R_P256TO511); + DUMP_REG(RMON_R_P512TO1023); + DUMP_REG(RMON_R_P1024TO2047); + DUMP_REG(RMON_R_P_GTE2048); + DUMP_REG(RMON_R_OCTETS); + DUMP_REG(IEEE_R_DROP); + DUMP_REG(IEEE_R_FRAME_OK); + DUMP_REG(IEEE_R_CRC); + DUMP_REG(IEEE_R_ALIGN); + DUMP_REG(IEEE_R_MACERR); + DUMP_REG(IEEE_R_FDXFC); + DUMP_REG(IEEE_R_OCTETS_OK); + DUMP_REG(ATCR); + DUMP_REG(ATVR); + DUMP_REG(ATOFF); + DUMP_REG(ATPER); + DUMP_REG(ATCOR); + DUMP_REG(ATINC); + DUMP_REG(ATSTMP); + DUMP_REG(TGSR); +} + +void enet_nvic_tog(void) +{ + NVIC_SetPendingIRQ(ENET_IRQn); +} + +void enet_rx_stat(void) +{ + enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; + +#define DUMP_STAT(__VAR) \ + rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR); + + DUMP_STAT(statsRxLenGreaterErr); + DUMP_STAT(statsRxAlignErr); + DUMP_STAT(statsRxFcsErr); + DUMP_STAT(statsRxOverRunErr); + DUMP_STAT(statsRxTruncateErr); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + DUMP_STAT(statsRxProtocolChecksumErr); + DUMP_STAT(statsRxIpHeadChecksumErr); + DUMP_STAT(statsRxMacErr); + DUMP_STAT(statsRxPhyErr); + DUMP_STAT(statsRxCollisionErr); + DUMP_STAT(statsTxErr); + DUMP_STAT(statsTxFrameErr); + DUMP_STAT(statsTxOverFlowErr); + DUMP_STAT(statsTxLateCollisionErr); + DUMP_STAT(statsTxExcessCollisionErr); + DUMP_STAT(statsTxUnderFlowErr); + DUMP_STAT(statsTxTsErr); +#endif + +} + +void enet_buf_info(void) +{ + int i = 0; + for (i = 0; i < ENET_RXBD_NUM; i++) + { + rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", + i, + g_rxBuffDescrip[i].length, + g_rxBuffDescrip[i].control, + g_rxBuffDescrip[i].buffer); + } + + for (i = 0; i < ENET_TXBD_NUM; i++) + { + rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", + i, + g_txBuffDescrip[i].length, + g_txBuffDescrip[i].control, + g_txBuffDescrip[i].buffer); + } +} + +FINSH_FUNCTION_EXPORT(phy_read, read phy register); +FINSH_FUNCTION_EXPORT(phy_write, write phy register); +FINSH_FUNCTION_EXPORT(phy_dump, dump phy registers); +FINSH_FUNCTION_EXPORT(enet_reg_dump, dump enet registers); +FINSH_FUNCTION_EXPORT(enet_nvic_tog, toggle enet nvic pendding bit); +FINSH_FUNCTION_EXPORT(enet_rx_stat, dump enet rx statistic); +FINSH_FUNCTION_EXPORT(enet_buf_info, dump enet tx and tx buffer descripter); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_hwtimer.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_hwtimer.c new file mode 100644 index 0000000000..b7e5412c2c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_hwtimer.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * +* Change Logs: +* Date Author Notes +* 2018-04-17 WangBing the first version. +*/ + +#include +#include +#include "drv_hwtimer.h" + +#include "fsl_common.h" +#include "fsl_gpt.h" + +#ifdef RT_USING_HWTIMER + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +/* Select IPG Clock as PERCLK_CLK clock source */ +#define EXAMPLE_GPT_CLOCK_SOURCE_SELECT (0U) +/* Clock divider for PERCLK_CLK clock source */ +#define EXAMPLE_GPT_CLOCK_DIVIDER_SELECT (5U) +/* Get source clock for GPT driver (GPT prescaler = 6) */ +#define EXAMPLE_GPT_CLK_FREQ (CLOCK_GetFreq(kCLOCK_IpgClk) / (EXAMPLE_GPT_CLOCK_DIVIDER_SELECT + 1U)) + +static void NVIC_Configuration(void) +{ + EnableIRQ(GPT1_IRQn); +} + +static rt_err_t rt1052_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t err = RT_EOK; + GPT_Type *hwtimer_dev; + hwtimer_dev = (GPT_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + uint32_t clk; + uint32_t pre; + clk = EXAMPLE_GPT_CLK_FREQ; + pre = clk / *((uint32_t *)args) - 1; + GPT_SetClockDivider(hwtimer_dev, pre); + } + break; + default: + err = -RT_ENOSYS; + break; + } + return err; +} + +static rt_uint32_t rt1052_hwtimer_count_get(rt_hwtimer_t *timer) +{ + rt_uint32_t CurrentTimer_Count; + GPT_Type *hwtimer_dev; + hwtimer_dev = (GPT_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + CurrentTimer_Count = GPT_GetCurrentTimerCount(hwtimer_dev); + + return CurrentTimer_Count; +} + +static void rt1052_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + GPT_Type *hwtimer_dev; + gpt_config_t gptConfig; + hwtimer_dev = (GPT_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + GPT_Deinit(hwtimer_dev); + + if (state == 1) + { + /*Clock setting for GPT*/ + CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); + + /* Initialize GPT module by default config */ + GPT_GetDefaultConfig(&gptConfig); + GPT_Init(hwtimer_dev, &gptConfig); + } +} + +static rt_err_t rt1052_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + GPT_Type *hwtimer_dev; + hwtimer_dev = (GPT_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + hwtimer_dev->CR |= (mode == HWTIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U; + + GPT_SetOutputCompareValue(hwtimer_dev, kGPT_OutputCompare_Channel1, cnt); + + GPT_EnableInterrupts(hwtimer_dev, kGPT_OutputCompare1InterruptEnable); + + NVIC_Configuration(); + + GPT_StartTimer(hwtimer_dev); + + return RT_EOK; +} + +static void rt1052_hwtimer_stop(rt_hwtimer_t *timer) +{ + GPT_Type *hwtimer_dev; + hwtimer_dev = (GPT_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + GPT_StopTimer(hwtimer_dev); +} + +static const struct rt_hwtimer_ops rt1052_hwtimer_ops = +{ + rt1052_hwtimer_init, + rt1052_hwtimer_start, + rt1052_hwtimer_stop, + rt1052_hwtimer_count_get, + rt1052_hwtimer_control, +}; + +static const struct rt_hwtimer_info rt1052_hwtimer_info = +{ + 25000000, /* the maximum count frequency can be set */ + 6103, /* the minimum count frequency can be set */ + 0xFFFFFFFF, + HWTIMER_CNTMODE_UP, +}; + +static rt_hwtimer_t GPT_timer1; + +int rt1052_hw_hwtimer_init(void) +{ + int ret = RT_EOK; + + GPT_timer1.info = &rt1052_hwtimer_info; + GPT_timer1.ops = &rt1052_hwtimer_ops; + + rt_device_hwtimer_register(&GPT_timer1, "_timer", GPT1); + + return ret; +} + +void GPT1_IRQHandler(void) +{ + if (GPT_GetStatusFlags(GPT1, kGPT_OutputCompare1Flag) != 0) + { + GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag); + rt_device_hwtimer_isr(&GPT_timer1); + } + + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U) + __DSB(); +#endif +} + +INIT_DEVICE_EXPORT(rt1052_hw_hwtimer_init); + +#endif /*RT_USING_HWTIMER*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_hwtimer.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_hwtimer.h new file mode 100644 index 0000000000..6e157c2332 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_hwtimer.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * +* Change Logs: +* Date Author Notes +* 2018-04-17 WangBing the first version. +*/ + +#ifndef __DRV_HWTIMER_H__ +#define __DRV_HWTIMER_H__ + +#include +#include + +int rt1052_hw_hwtimer_init(void); + +#endif + diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_i2c.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_i2c.c new file mode 100644 index 0000000000..3a428b0644 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_i2c.c @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-08 Yang the first version + * 2018-03-24 LaiYiKeTang add hardware iic + */ + +#include +#include +#include "board.h" +#include "fsl_gpio.h" +#include "fsl_lpi2c.h" +#include "drv_i2c.h" + +//#define DRV_I2C_DEBUG + +#ifdef RT_USING_I2C + +#define I2C1BUS_NAME "i2c1" +#define I2C2BUS_NAME "i2c2" +#define I2C3BUS_NAME "i2c3" +#define I2C4BUS_NAME "i2c4" + +#define LPI2C_CLOCK_SOURCE_DIVIDER 4 + +/* Get frequency of lpi2c clock */ +#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER)) + +#ifdef RT_USING_HW_I2C1 +static struct rt1052_i2c_bus lpi2c1 = +{ + .I2C = LPI2C1, + .device_name = I2C1BUS_NAME, +}; +#endif /* RT_USING_HW_I2C1 */ + +#ifdef RT_USING_HW_I2C2 +static struct rt1052_i2c_bus lpi2c2 = +{ + .I2C = LPI2C2, + .device_name = I2C2BUS_NAME, +}; +#endif /* RT_USING_HW_I2C2 */ + +#ifdef RT_USING_HW_I2C3 +static struct rt1052_i2c_bus lpi2c3 = +{ + .I2C = LPI2C3, + .device_name = I2C3BUS_NAME, +}; +#endif /* RT_USING_HW_I2C3 */ + +#ifdef RT_USING_HW_I2C4 +static struct rt1052_i2c_bus lpi2c4 = +{ + .I2C = LPI2C4, + .device_name = I2C4BUS_NAME, +}; +#endif /* RT_USING_HW_I2C4 */ + +#if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4)) + +static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t, + rt_uint32_t); + +static const struct rt_i2c_bus_device_ops imxrt_i2c_ops = +{ + imxrt_i2c_mst_xfer, + imxrt_i2c_slv_xfer, + imxrt_i2c_bus_control, +}; + +void imxrt_lpi2c_gpio_init(struct rt1052_i2c_bus *bus) +{ + if (bus->I2C == LPI2C1) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, + 0xD8B0u); + } + else if (bus->I2C == LPI2C2) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_04_LPI2C2_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B0_05_LPI2C2_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_04_LPI2C2_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B0_05_LPI2C2_SDA, + 0xD8B0u); + } + else if (bus->I2C == LPI2C3) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, + 0xD8B0u); + } + else if (bus->I2C == LPI2C4) + { + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_12_LPI2C4_SCL, + 1U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_11_LPI2C4_SDA, + 1U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_12_LPI2C4_SCL, + 0xD8B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_11_LPI2C4_SDA, + 0xD8B0u); + } + else + { + RT_ASSERT(RT_NULL); + } +} + +static rt_err_t imxrt_lpi2c_configure(struct rt1052_i2c_bus *bus, lpi2c_master_config_t *cfg) +{ + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + imxrt_lpi2c_gpio_init(bus); + bus->parent.ops = &imxrt_i2c_ops; + LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY); + return RT_EOK; +} + +status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= 0x3c00; + if (status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (status & kLPI2C_MasterPinLowTimeoutFlag) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (status & kLPI2C_MasterArbitrationLostFlag) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (status & kLPI2C_MasterNackDetectFlag) + { + result = kStatus_LPI2C_Nak; + } + else if (status & kLPI2C_MasterFifoErrFlag) + { + result = kStatus_LPI2C_FifoError; + } + else + { + assert(false); + } + + /* Clear the flags. */ + LPI2C_MasterClearStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } + + return result; +} + +/*! + * @brief Wait until the tx fifo all empty. + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base) +{ + uint32_t status; + size_t txCount; + do + { + status_t result; + + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheck(base, status); + if (result) + { + return result; + } + } + while (txCount); + return kStatus_Success; +} + +static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt1052_i2c_bus *rt1052_i2c; + rt_size_t i; + RT_ASSERT(bus != RT_NULL); + rt1052_i2c = (struct rt1052_i2c_bus *) bus; + + rt1052_i2c->msg = msgs; + rt1052_i2c->msg_ptr = 0; + rt1052_i2c->msg_cnt = num; + rt1052_i2c->dptr = 0; + + for (i = 0; i < num; i++) + { + if (rt1052_i2c->msg[i].flags & RT_I2C_RD) + { + if (LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success) + { + i = 0; + break; + } + if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) + { + i = 0; + break; + } + if (LPI2C_MasterReceive(rt1052_i2c->I2C, rt1052_i2c->msg[i].buf, rt1052_i2c->msg[i].len) != kStatus_Success) + { + i = 0; + break; + } + if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) + { + i = 0; + break; + } + } + else + { + if (LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success) + { + i = 0; + break; + } + if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) + { + i = 0; + break; + } + if (LPI2C_MasterSend(rt1052_i2c->I2C, rt1052_i2c->msg[i].buf, rt1052_i2c->msg[i].len) != kStatus_Success) + { + i = 0; + break; + } + if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) + { + i = 0; + break; + } + } + } + i2c_dbg("send stop condition\n"); + if (LPI2C_MasterStop(rt1052_i2c->I2C) != kStatus_Success) + { + i = 0; + } + + rt1052_i2c->msg = RT_NULL; + rt1052_i2c->msg_ptr = 0; + rt1052_i2c->msg_cnt = 0; + rt1052_i2c->dptr = 0; + return i; +} + +static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + return 0; +} +static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t cmd, + rt_uint32_t arg) +{ + return RT_ERROR; +} + +#endif + +int rt_hw_i2c_init(void) +{ +#if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4)) + + lpi2c_master_config_t masterConfig = {0}; + + /*Clock setting for LPI2C*/ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER - 1); + +#endif + +#if defined(RT_USING_HW_I2C1) + LPI2C_MasterGetDefaultConfig(&masterConfig); +#if defined(HW_I2C1_BADURATE_400kHZ) + masterConfig.baudRate_Hz = 400000U; +#elif defined(HW_I2C1_BADURATE_100kHZ) + masterConfig.baudRate_Hz = 100000U; +#endif + imxrt_lpi2c_configure(&lpi2c1, &masterConfig); + rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name); +#endif + +#if defined(RT_USING_HW_I2C2) + LPI2C_MasterGetDefaultConfig(&masterConfig); +#if defined(HW_I2C2_BADURATE_400kHZ) + masterConfig.baudRate_Hz = 400000U; +#elif defined(HW_I2C2_BADURATE_100kHZ) + masterConfig.baudRate_Hz = 100000U; +#endif + imxrt_lpi2c_configure(&lpi2c2, &masterConfig); + rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name); +#endif + +#if defined(RT_USING_HW_I2C3) + LPI2C_MasterGetDefaultConfig(&masterConfig); +#if defined(HW_I2C3_BADURATE_400kHZ) + masterConfig.baudRate_Hz = 400000U; +#elif defined(HW_I2C3_BADURATE_100kHZ) + masterConfig.baudRate_Hz = 100000U; +#endif + imxrt_lpi2c_configure(&lpi2c3, &masterConfig); + rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name); +#endif + +#if defined(RT_USING_HW_I2C4) + LPI2C_MasterGetDefaultConfig(&masterConfig); +#if defined(HW_I2C4_BADURATE_400kHZ) + masterConfig.baudRate_Hz = 400000U; +#elif defined(HW_I2C4_BADURATE_100kHZ) + masterConfig.baudRate_Hz = 100000U; +#endif + imxrt_lpi2c_configure(&lpi2c4, &masterConfig); + rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name); +#endif + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#if defined(RT_USING_FINSH) && defined(DRV_I2C_DEBUG) +#include + +static rt_device_t _i2c_find(const char *name) +{ + rt_device_t dev; + + dev = rt_device_find(name); + if (!dev) + { + rt_kprintf("search device failed: %s\n", name); + return RT_NULL; + } + + if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + rt_kprintf("open device failed: %s\n", name); + return RT_NULL; + } + + rt_kprintf("open i2c bus: %s\n", name); + + return dev; +} + +static void _search_i2c_device(rt_device_t dev, uint8_t cmd) +{ + int count = 0; + struct rt_i2c_msg msgs[2]; + uint8_t buf = 0; + + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = &cmd; + msgs[0].len = sizeof(cmd); + + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = &buf; + msgs[1].len = 1; + + for (int i = 0; i <= 0x7f; i++) + { + int len; + + msgs[0].addr = i; + msgs[1].addr = i; + len = rt_i2c_transfer((struct rt_i2c_bus_device *)dev, msgs, 2); + if (len == 2) + { + count++; + rt_kprintf("add:%02X transfer success, id: %02X\n", i, buf); + } + } + + rt_kprintf("i2c device: %d\n", count); +} + +static int i2c_test(const char *name, uint8_t cmd) +{ + rt_device_t dev = _i2c_find(name); + + if (dev == RT_NULL) + { + rt_kprintf("search i2c device faild\n"); + return -1; + } + + _search_i2c_device(dev, cmd); + rt_device_close(dev); + + return 0; +} +FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c1", 0xA3)); + +#endif + +#endif /* RT_USING_I2C */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_i2c.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_i2c.h new file mode 100644 index 0000000000..53e77e2ce7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_i2c.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-24 LaiYiKeTang the first version + */ + +#ifndef __DRVI2C_H__ +#define __DRVI2C_H__ + +#include +#include +#include +#include "board.h" +struct rt1052_i2c_bus +{ + struct rt_i2c_bus_device parent; + LPI2C_Type *I2C; + struct rt_i2c_msg *msg; + rt_uint32_t msg_cnt; + volatile rt_uint32_t msg_ptr; + volatile rt_uint32_t dptr; + char *device_name; +}; + +#endif + diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_lcd.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_lcd.c new file mode 100644 index 0000000000..06f95acadf --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_lcd.c @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-30 Tanek the first version + * 2018-04-05 Liu2guang export LCD config parameters. + */ + +#include "drv_lcd.h" + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_elcdif.h" + +#if !defined(LCD_WIDTH) || !defined(LCD_HEIGHT) +#error "Please config lcd pixel parameters." +#endif + +#if !defined(LCD_HFP) || !defined(LCD_HBP) || !defined(LCD_HSW) || \ + !defined(LCD_VFP) || !defined(LCD_VBP) || !defined(LCD_VSW) +#error "Please config lcd timing parameters." +#endif + +#if !defined(LCD_BL_PIN) || !defined(LCD_RST_PIN) +#error "Please config lcd backlight or reset pin." +#endif + +struct rt1050_lcd +{ + struct rt_device device; + struct rt_device_graphic_info info; +}; + +static struct rt1050_lcd lcd; + +static volatile int fb_index = 0; +static volatile rt_bool_t fb_modified = RT_TRUE; + +ALIGN(64) static uint16_t frame_buffer0[LCD_HEIGHT][LCD_WIDTH] SECTION("NonCacheable"); +ALIGN(64) static uint16_t frame_buffer1[LCD_HEIGHT][LCD_WIDTH] SECTION("NonCacheable"); + +static rt_err_t rt1050_lcd_init(rt_device_t device) +{ + RT_ASSERT(device != RT_NULL); + + memset(frame_buffer0, 0x00, sizeof(frame_buffer0)); + memset(frame_buffer1, 0x00, sizeof(frame_buffer1)); + + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + + /* + * Initialize the Video PLL. + * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz. + */ + clock_video_pll_config_t config = + { + .loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 1, + }; + + CLOCK_InitVideoPll(&config); + + /* + * 000 derive clock from PLL2 + * 001 derive clock from PLL3 PFD3 + * 010 derive clock from PLL5 + * 011 derive clock from PLL2 PFD0 + * 100 derive clock from PLL2 PFD1 + * 101 derive clock from PLL3 PFD1 + */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); + + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4); + + CLOCK_SetDiv(kCLOCK_LcdifDiv, 1); + + /* GPIO */ + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U); /* LCD_B3 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U); /* LCD_B4 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U); /* LCD_B5 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U); /* LCD_B6 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U); /* LCD_B7 */ + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U); /* LCD_G2 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U); /* LCD_G3 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U); /* LCD_G4 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U); /* LCD_G5 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U); /* LCD_G6 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U); /* LCD_G7 */ + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U); /* LCD_R3 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U); /* LCD_R4 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U); /* LCD_R5 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U); /* LCD_R6 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U); /* LCD_R7 */ + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0u); /* LCD_CLK */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0u); /* LCD_HSYNC */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0u); /* LCD_VSYNC */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u); /* LCD_ENABLE */ + + rt_pin_mode(LCD_RST_PIN, PIN_MODE_OUTPUT); /* LCD_RESET */ + rt_pin_write(LCD_RST_PIN, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND / 100); + rt_pin_write(LCD_RST_PIN, PIN_HIGH); + + rt_pin_mode(LCD_BL_PIN, PIN_MODE_OUTPUT); /* LCD_BL */ + rt_pin_write(LCD_BL_PIN, PIN_HIGH); + + /* LCD */ + elcdif_rgb_mode_config_t lcd_config; + + lcd_config.hfp = LCD_HFP; + lcd_config.vfp = LCD_VFP; + lcd_config.hbp = LCD_HBP; + lcd_config.vbp = LCD_VBP; + lcd_config.hsw = LCD_HSW; + lcd_config.vsw = LCD_VSW; + + lcd_config.polarityFlags = kELCDIF_DataEnableActiveHigh | + kELCDIF_VsyncActiveHigh | + kELCDIF_HsyncActiveLow | + kELCDIF_DriveDataOnRisingClkEdge; + + lcd_config.panelWidth = LCD_WIDTH; + lcd_config.panelHeight = LCD_HEIGHT; + lcd_config.pixelFormat = kELCDIF_PixelFormatRGB565; + lcd_config.dataBus = kELCDIF_DataBus16Bit; + lcd_config.bufferAddr = (uint32_t)frame_buffer0; + + ELCDIF_RgbModeInit(LCDIF, &lcd_config); + ELCDIF_RgbModeStart(LCDIF); + + /* LCD DEVICE */ + lcd.info.width = LCD_WIDTH; + lcd.info.height = LCD_HEIGHT; + lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + lcd.info.bits_per_pixel = 16; + lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * 2, 32); + + return RT_EOK; +} + +void LCDIF_IRQHandler(void) +{ + uint32_t intStatus; + + intStatus = ELCDIF_GetInterruptStatus(LCDIF); + + ELCDIF_ClearInterruptStatus(LCDIF, intStatus); + if (intStatus & kELCDIF_CurFrameDone) + { + fb_modified = RT_TRUE; + } +} + +static rt_err_t rt1050_lcd_control(rt_device_t device, int cmd, void *args) +{ + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + uint8_t *ptr; + + if (fb_index == 0) + { + ptr = (uint8_t *)&frame_buffer1[0]; + } + else + { + ptr = (uint8_t *)&frame_buffer0[0]; + } + + while(LCDIF->CUR_BUF != LCDIF->NEXT_BUF); + + memcpy(ptr, lcd.info.framebuffer, LCD_WIDTH * LCD_HEIGHT * 2); + + if (fb_index == 0) + { + /* use fb1 */ + ELCDIF_SetNextBufferAddr(LCDIF, (uint32_t)&frame_buffer1[0]); + fb_index = 1; + } + else + { + /* use fb0 */ + ELCDIF_SetNextBufferAddr(LCDIF, (uint32_t)&frame_buffer0[0]); + fb_index = 0; + } + } + break; + + case RTGRAPHIC_CTRL_POWERON: + rt_pin_write(LCD_BL_PIN, PIN_HIGH); + break; + + case RTGRAPHIC_CTRL_POWEROFF: + rt_pin_write(LCD_BL_PIN, PIN_LOW); + break; + + case RTGRAPHIC_CTRL_GET_INFO: + memcpy(args, &lcd.info, sizeof(lcd.info)); + break; + + case RTGRAPHIC_CTRL_SET_MODE: + break; + } + + return RT_EOK; +} + +int rt_hw_lcd_init(void) +{ + rt_err_t ret; + + lcd.device.type = RT_Device_Class_Graphic; + lcd.device.init = rt1050_lcd_init; + lcd.device.open = RT_NULL; + lcd.device.close = RT_NULL; + lcd.device.read = RT_NULL; + lcd.device.write = RT_NULL; + lcd.device.control = rt1050_lcd_control; + + lcd.device.user_data = (void *)&lcd.info; + + ret = rt_device_register(&lcd.device, "lcd", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_lcd_init); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_lcd.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_lcd.h new file mode 100644 index 0000000000..a465909935 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_lcd.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-05 Liuguang the first version. + */ + +#ifndef __DRV_LCD_H__ +#define __DRV_LCD_H__ + +#include +#include + +int rt_hw_lcd_init(void); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pcf8574.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pcf8574.c new file mode 100644 index 0000000000..398013ea6a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pcf8574.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-06-12 zylx the first version. + */ +#include "drv_pcf8574.h" + +#define PCF8574_I2CBUS_NAME "i2c1" +static struct rt_i2c_bus_device *pcf8574_i2c_bus; + +int pcf8574_Init(void) +{ + rt_uint8_t value = 0x01; + + pcf8574_i2c_bus = rt_i2c_bus_device_find(PCF8574_I2CBUS_NAME); + + if (pcf8574_i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device\r\n"); + return -RT_ERROR; + } + + if (!rt_i2c_master_send(pcf8574_i2c_bus, PCF8574_ADDR, 0, &value, 1)) + { + rt_kprintf("can't find pcf8574\r\n"); + return -RT_ERROR; + } + + return 0; +} +INIT_COMPONENT_EXPORT(pcf8574_Init); + +rt_uint8_t pcf8574_read_byte(void) +{ + rt_uint8_t temp = 0; + rt_i2c_master_recv(pcf8574_i2c_bus, PCF8574_ADDR, 0, &temp, 1); + return temp; +} + +void pcf8574_write_byte(rt_uint8_t data) +{ + rt_i2c_master_send(pcf8574_i2c_bus, PCF8574_ADDR, 0, &data, 1); +} + +void pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t sta) +{ + rt_uint8_t data; + data = pcf8574_read_byte(); + if (sta == 0)data &= ~(1 << bit); + else data |= 1 << bit; + pcf8574_write_byte(data); +} + +rt_uint8_t pcf8574_read_bit(rt_uint8_t bit) +{ + rt_uint8_t data; + data = pcf8574_read_byte(); + if (data & (1 << bit))return 1; + else return 0; +} + diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pcf8574.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pcf8574.h new file mode 100644 index 0000000000..266ce0239a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pcf8574.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-06-12 zylx the first version. + */ +#ifndef __PCF8574_H +#define __PCF8574_H + +#include +#include "rtdevice.h" + +#define PCF8574_ADDR 0X20 + +rt_uint8_t pcf8574_read_byte(void); +void pcf8574_write_byte(rt_uint8_t data); +void pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t sta); +rt_uint8_t pcf8574_read_bit(rt_uint8_t bit); + +#endif + diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.c new file mode 100644 index 0000000000..f1a63fd120 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.c @@ -0,0 +1,691 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-13 Liuguang the first version. + * 2018-03-19 Liuguang add GPIO interrupt mode support. + */ +#include "drv_pin.h" + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" + +#ifdef RT_USING_PIN + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +struct rt1052_pin +{ + rt_uint16_t pin; + GPIO_Type *gpio; + rt_uint32_t gpio_pin; +}; + +struct rt1052_irq +{ + rt_uint16_t enable; + struct rt_pin_irq_hdr irq_info; +}; + +#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0])) +#define __RT1052_PIN_DEFAULT {0, 0, 0} +#define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN} + +static struct rt_pin_ops rt1052_pin_ops; + +static struct rt1052_pin rt1052_pin_map[] = +{ + __RT1052_PIN_DEFAULT, + + /* GPIO4 */ + __RT1052_PIN( 1, GPIO4, 0), /* GPIO_EMC_00 */ + __RT1052_PIN( 2, GPIO4, 1), /* GPIO_EMC_01 */ + __RT1052_PIN( 3, GPIO4, 2), /* GPIO_EMC_02 */ + __RT1052_PIN( 4, GPIO4, 3), /* GPIO_EMC_03 */ + __RT1052_PIN( 5, GPIO4, 4), /* GPIO_EMC_04 */ + __RT1052_PIN( 6, GPIO4, 5), /* GPIO_EMC_05 */ + __RT1052_PIN( 7, GPIO4, 6), /* GPIO_EMC_06 */ + __RT1052_PIN( 8, GPIO4, 7), /* GPIO_EMC_07 */ + __RT1052_PIN( 9, GPIO4, 8), /* GPIO_EMC_08 */ + __RT1052_PIN(10, GPIO4, 9), /* GPIO_EMC_09 */ + __RT1052_PIN(11, GPIO4, 10), /* GPIO_EMC_10 */ + __RT1052_PIN(12, GPIO4, 11), /* GPIO_EMC_11 */ + __RT1052_PIN(13, GPIO4, 12), /* GPIO_EMC_12 */ + __RT1052_PIN(14, GPIO4, 13), /* GPIO_EMC_13 */ + __RT1052_PIN(15, GPIO4, 14), /* GPIO_EMC_14 */ + __RT1052_PIN(16, GPIO4, 15), /* GPIO_EMC_15 */ + __RT1052_PIN(17, GPIO4, 16), /* GPIO_EMC_16 */ + __RT1052_PIN(18, GPIO4, 17), /* GPIO_EMC_17 */ + __RT1052_PIN(19, GPIO4, 18), /* GPIO_EMC_18 */ + __RT1052_PIN(20, GPIO4, 19), /* GPIO_EMC_19 */ + __RT1052_PIN(21, GPIO4, 20), /* GPIO_EMC_20 */ + __RT1052_PIN(22, GPIO4, 21), /* GPIO_EMC_21 */ + __RT1052_PIN(23, GPIO4, 22), /* GPIO_EMC_22 */ + __RT1052_PIN(24, GPIO4, 23), /* GPIO_EMC_23 */ + __RT1052_PIN(25, GPIO4, 24), /* GPIO_EMC_24 */ + __RT1052_PIN(26, GPIO4, 25), /* GPIO_EMC_25 */ + __RT1052_PIN(27, GPIO4, 26), /* GPIO_EMC_26 */ + __RT1052_PIN(28, GPIO4, 27), /* GPIO_EMC_27 */ + __RT1052_PIN(29, GPIO4, 28), /* GPIO_EMC_28 */ + __RT1052_PIN(30, GPIO4, 29), /* GPIO_EMC_29 */ + __RT1052_PIN(31, GPIO4, 30), /* GPIO_EMC_30 */ + __RT1052_PIN(32, GPIO4, 31), /* GPIO_EMC_31 */ + + __RT1052_PIN(33, GPIO3, 18), /* GPIO_EMC_32 */ + __RT1052_PIN(34, GPIO3, 19), /* GPIO_EMC_33 */ + __RT1052_PIN(35, GPIO3, 20), /* GPIO_EMC_34 */ + __RT1052_PIN(36, GPIO3, 21), /* GPIO_EMC_35 */ + __RT1052_PIN(37, GPIO3, 22), /* GPIO_EMC_36 */ + __RT1052_PIN(38, GPIO3, 23), /* GPIO_EMC_37 */ + __RT1052_PIN(39, GPIO3, 24), /* GPIO_EMC_38 */ + __RT1052_PIN(40, GPIO3, 25), /* GPIO_EMC_39 */ + __RT1052_PIN(41, GPIO3, 26), /* GPIO_EMC_40 */ + __RT1052_PIN(42, GPIO3, 27), /* GPIO_EMC_41 */ + + /* GPIO1 */ + __RT1052_PIN(43, GPIO1, 0), /* GPIO_AD_B0_00 */ + __RT1052_PIN(44, GPIO1, 1), /* GPIO_AD_B0_01 */ + __RT1052_PIN(45, GPIO1, 2), /* GPIO_AD_B0_02 */ + __RT1052_PIN(46, GPIO1, 3), /* GPIO_AD_B0_03 */ + __RT1052_PIN(47, GPIO1, 4), /* GPIO_AD_B0_04 */ + __RT1052_PIN(48, GPIO1, 5), /* GPIO_AD_B0_05 */ + __RT1052_PIN(49, GPIO1, 6), /* GPIO_AD_B0_06 */ + __RT1052_PIN(50, GPIO1, 7), /* GPIO_AD_B0_07 */ + __RT1052_PIN(51, GPIO1, 8), /* GPIO_AD_B0_08 */ + __RT1052_PIN(52, GPIO1, 9), /* GPIO_AD_B0_09 */ + __RT1052_PIN(53, GPIO1, 10), /* GPIO_AD_B0_10 */ + __RT1052_PIN(54, GPIO1, 11), /* GPIO_AD_B0_11 */ + __RT1052_PIN(55, GPIO1, 12), /* GPIO_AD_B0_12 */ + __RT1052_PIN(56, GPIO1, 13), /* GPIO_AD_B0_13 */ + __RT1052_PIN(57, GPIO1, 14), /* GPIO_AD_B0_14 */ + __RT1052_PIN(58, GPIO1, 15), /* GPIO_AD_B0_15 */ + __RT1052_PIN(59, GPIO1, 16), /* GPIO_AD_B1_00 */ + __RT1052_PIN(60, GPIO1, 17), /* GPIO_AD_B1_01 */ + __RT1052_PIN(61, GPIO1, 18), /* GPIO_AD_B1_02 */ + __RT1052_PIN(62, GPIO1, 19), /* GPIO_AD_B1_03 */ + __RT1052_PIN(63, GPIO1, 20), /* GPIO_AD_B1_04 */ + __RT1052_PIN(64, GPIO1, 21), /* GPIO_AD_B1_05 */ + __RT1052_PIN(65, GPIO1, 22), /* GPIO_AD_B1_06 */ + __RT1052_PIN(66, GPIO1, 23), /* GPIO_AD_B1_07 */ + __RT1052_PIN(67, GPIO1, 24), /* GPIO_AD_B1_08 */ + __RT1052_PIN(68, GPIO1, 25), /* GPIO_AD_B1_09 */ + __RT1052_PIN(69, GPIO1, 26), /* GPIO_AD_B1_10 */ + __RT1052_PIN(70, GPIO1, 27), /* GPIO_AD_B1_11 */ + __RT1052_PIN(71, GPIO1, 28), /* GPIO_AD_B1_12 */ + __RT1052_PIN(72, GPIO1, 29), /* GPIO_AD_B1_13 */ + __RT1052_PIN(73, GPIO1, 30), /* GPIO_AD_B1_14 */ + __RT1052_PIN(74, GPIO1, 31), /* GPIO_AD_B1_15 */ + + /* GPIO2 */ + __RT1052_PIN( 75, GPIO2, 0), /* GPIO_B0_00 */ + __RT1052_PIN( 76, GPIO2, 1), /* GPIO_B0_01 */ + __RT1052_PIN( 77, GPIO2, 2), /* GPIO_B0_02 */ + __RT1052_PIN( 78, GPIO2, 3), /* GPIO_B0_03 */ + __RT1052_PIN( 79, GPIO2, 4), /* GPIO_B0_04 */ + __RT1052_PIN( 80, GPIO2, 5), /* GPIO_B0_05 */ + __RT1052_PIN( 81, GPIO2, 6), /* GPIO_B0_06 */ + __RT1052_PIN( 82, GPIO2, 7), /* GPIO_B0_07 */ + __RT1052_PIN( 83, GPIO2, 8), /* GPIO_B0_08 */ + __RT1052_PIN( 84, GPIO2, 9), /* GPIO_B0_09 */ + __RT1052_PIN( 85, GPIO2, 10), /* GPIO_B0_10 */ + __RT1052_PIN( 86, GPIO2, 11), /* GPIO_B0_11 */ + __RT1052_PIN( 87, GPIO2, 12), /* GPIO_B0_12 */ + __RT1052_PIN( 88, GPIO2, 13), /* GPIO_B0_13 */ + __RT1052_PIN( 89, GPIO2, 14), /* GPIO_B0_14 */ + __RT1052_PIN( 90, GPIO2, 15), /* GPIO_B0_15 */ + __RT1052_PIN( 91, GPIO2, 16), /* GPIO_B1_00 */ + __RT1052_PIN( 92, GPIO2, 17), /* GPIO_B1_01 */ + __RT1052_PIN( 93, GPIO2, 18), /* GPIO_B1_02 */ + __RT1052_PIN( 94, GPIO2, 19), /* GPIO_B1_03 */ + __RT1052_PIN( 95, GPIO2, 20), /* GPIO_B1_04 */ + __RT1052_PIN( 96, GPIO2, 21), /* GPIO_B1_05 */ + __RT1052_PIN( 97, GPIO2, 22), /* GPIO_B1_06 */ + __RT1052_PIN( 98, GPIO2, 23), /* GPIO_B1_07 */ + __RT1052_PIN( 99, GPIO2, 24), /* GPIO_B1_08 */ + __RT1052_PIN(100, GPIO2, 25), /* GPIO_B1_09 */ + __RT1052_PIN(101, GPIO2, 26), /* GPIO_B1_10 */ + __RT1052_PIN(102, GPIO2, 27), /* GPIO_B1_11 */ + __RT1052_PIN(103, GPIO2, 28), /* GPIO_B1_12 */ + __RT1052_PIN(104, GPIO2, 29), /* GPIO_B1_13 */ + __RT1052_PIN(105, GPIO2, 30), /* GPIO_B1_14 */ + __RT1052_PIN(106, GPIO2, 31), /* GPIO_B1_15 */ + + /* GPIO3 */ + __RT1052_PIN(107, GPIO3, 0), /* GPIO_SD_B1_00 */ + __RT1052_PIN(108, GPIO3, 1), /* GPIO_SD_B1_01 */ + __RT1052_PIN(109, GPIO3, 2), /* GPIO_SD_B1_02 */ + __RT1052_PIN(110, GPIO3, 3), /* GPIO_SD_B1_03 */ + __RT1052_PIN(111, GPIO3, 4), /* GPIO_SD_B1_04 */ + __RT1052_PIN(112, GPIO3, 5), /* GPIO_SD_B1_05 */ + __RT1052_PIN(113, GPIO3, 6), /* GPIO_SD_B1_06 */ + __RT1052_PIN(114, GPIO3, 7), /* GPIO_SD_B1_07 */ + __RT1052_PIN(115, GPIO3, 8), /* GPIO_SD_B1_08 */ + __RT1052_PIN(116, GPIO3, 9), /* GPIO_SD_B1_09 */ + __RT1052_PIN(117, GPIO3, 10), /* GPIO_SD_B1_10 */ + __RT1052_PIN(118, GPIO3, 11), /* GPIO_SD_B1_11 */ + __RT1052_PIN(119, GPIO3, 12), /* GPIO_SD_B0_00 */ + __RT1052_PIN(120, GPIO3, 13), /* GPIO_SD_B0_01 */ + __RT1052_PIN(121, GPIO3, 14), /* GPIO_SD_B0_02 */ + __RT1052_PIN(122, GPIO3, 15), /* GPIO_SD_B0_03 */ + __RT1052_PIN(123, GPIO3, 16), /* GPIO_SD_B0_04 */ + __RT1052_PIN(124, GPIO3, 17), /* GPIO_SD_B0_05 */ + + /* GPIO5 */ + __RT1052_PIN(125, GPIO5, 0), /* WAKEUP */ + __RT1052_PIN(126, GPIO5, 1), /* PMIC_ON_REQ */ + __RT1052_PIN(127, GPIO5, 2) /* PMIC_STBY_REQ */ +}; + +static struct rt1052_irq rt1052_irq_map[] = +{ + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, + {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} } +}; + +void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin) +{ + if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0) + { + GPIO_PortClearInterruptFlags(base, gpio_pin); + + if(rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL) + { + rt1052_irq_map[gpio_pin].irq_info.hdr(rt1052_irq_map[gpio_pin].irq_info.args); + } + } +} + +void GPIO1_Combined_0_15_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) + { + gpio_isr(GPIO1, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO1_Combined_16_31_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) + { + gpio_isr(GPIO1, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO2_Combined_0_15_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) + { + gpio_isr(GPIO2, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO2_Combined_16_31_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) + { + gpio_isr(GPIO2, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO3_Combined_0_15_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) + { + gpio_isr(GPIO3, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO3_Combined_16_31_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) + { + gpio_isr(GPIO3, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO4_Combined_0_15_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) + { + gpio_isr(GPIO4, gpio_pin); + } + + rt_interrupt_leave(); +} +void GPIO4_Combined_16_31_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) + { + gpio_isr(GPIO4, gpio_pin); + } + + rt_interrupt_leave(); +} + +void GPIO5_Combined_0_15_IRQHandler(void) +{ + rt_uint8_t gpio_pin; + + rt_interrupt_enter(); + + for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++) + { + gpio_isr(GPIO5, gpio_pin); + } + + rt_interrupt_leave(); +} + +static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin) +{ + IRQn_Type irq_num = NotAvail_IRQn; /* Invalid interrupt number */ + + if(gpio == GPIO1) + { + if(gpio_pin <= 15) + { + irq_num = GPIO1_Combined_0_15_IRQn; + } + else + { + irq_num = GPIO1_Combined_16_31_IRQn; + } + } + else if(gpio == GPIO2) + { + if(gpio_pin <= 15) + { + irq_num = GPIO2_Combined_0_15_IRQn; + } + else + { + irq_num = GPIO2_Combined_16_31_IRQn; + } + } + else if(gpio == GPIO3) + { + if(gpio_pin <= 15) + { + irq_num = GPIO3_Combined_0_15_IRQn; + } + else + { + irq_num = GPIO3_Combined_16_31_IRQn; + } + } + else if(gpio == GPIO4) + { + if(gpio_pin <= 15) + { + irq_num = GPIO4_Combined_0_15_IRQn; + } + else + { + irq_num = GPIO4_Combined_16_31_IRQn; + } + } + else if(gpio == GPIO5) + { + if(gpio_pin <= 15) + { + irq_num = GPIO5_Combined_0_15_IRQn; + } + else + { + irq_num = GPIO5_Combined_16_31_IRQn; + } + } + + return irq_num; +} + +static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + gpio_pin_config_t gpio; + rt_uint32_t config_value = 0; + + if((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0)) + { + return; + } + + if(rt1052_pin_map[pin].gpio != GPIO5) + { + CLOCK_EnableClock(kCLOCK_Iomuxc); + IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1); + } + else + { + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1); + } + + gpio.outputLogic = 0; + gpio.interruptMode = kGPIO_NoIntmode; + + switch(mode) + { + case PIN_MODE_OUTPUT: + { + config_value = 0x1030U; + gpio.direction = kGPIO_DigitalOutput; + } + break; + + case PIN_MODE_INPUT: + { + config_value = 0x1030U; + gpio.direction = kGPIO_DigitalInput; + } + break; + + case PIN_MODE_INPUT_PULLDOWN: + { + config_value = 0x1030U; + gpio.direction = kGPIO_DigitalInput; + } + break; + + case PIN_MODE_INPUT_PULLUP: + { + config_value = 0x5030U; + gpio.direction = kGPIO_DigitalInput; + } + break; + + case PIN_MODE_OUTPUT_OD: + { + config_value = 0x1830U; + gpio.direction = kGPIO_DigitalOutput; + } + break; + } + + if(rt1052_pin_map[pin].gpio != GPIO5) + { + IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); + } + else + { + IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); + } + + GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); +} + +static int rt1052_pin_read(rt_device_t dev, rt_base_t pin) +{ + return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); +} + +static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + GPIO_PinWrite(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, value); +} + +static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + struct rt1052_pin* pin_map = RT_NULL; + struct rt1052_irq* irq_map = RT_NULL; + + pin_map = &rt1052_pin_map[pin]; + irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; + + if(pin_map == RT_NULL || irq_map == RT_NULL) + { + return RT_ENOSYS; + } + + if(irq_map->enable == PIN_IRQ_ENABLE) + { + return RT_EBUSY; + } + + irq_map->irq_info.pin = pin; + irq_map->irq_info.hdr = hdr; + irq_map->irq_info.mode = mode; + irq_map->irq_info.args = args; + + return RT_EOK; +} + +static rt_err_t rt1052_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + struct rt1052_pin* pin_map = RT_NULL; + struct rt1052_irq* irq_map = RT_NULL; + + pin_map = &rt1052_pin_map[pin]; + irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; + + if(pin_map == RT_NULL || irq_map == RT_NULL) + { + return RT_ENOSYS; + } + + if(irq_map->enable == PIN_IRQ_DISABLE) + { + return RT_EOK; + } + + irq_map->irq_info.pin = PIN_IRQ_PIN_NONE; + irq_map->irq_info.hdr = RT_NULL; + irq_map->irq_info.mode = PIN_IRQ_MODE_RISING; + irq_map->irq_info.args = RT_NULL; + + return RT_EOK; +} + +static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + gpio_pin_config_t gpio; + IRQn_Type irq_num; + rt_uint32_t config_value = 0x1b0a0; + + struct rt1052_pin* pin_map = RT_NULL; + struct rt1052_irq* irq_map = RT_NULL; + + pin_map = &rt1052_pin_map[pin]; + irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; + + if(pin_map == RT_NULL || irq_map == RT_NULL) + { + return RT_ENOSYS; + } + + if(enabled == PIN_IRQ_ENABLE) + { + if(irq_map->enable == PIN_IRQ_ENABLE) + { + return RT_EBUSY; + } + + if(irq_map->irq_info.pin != pin) + { + return RT_EIO; + } + + irq_map->enable = PIN_IRQ_ENABLE; + + if(rt1052_pin_map[pin].gpio != GPIO5) + { + CLOCK_EnableClock(kCLOCK_Iomuxc); + IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); + } + else + { + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); + } + + gpio.direction = kGPIO_DigitalInput; + gpio.outputLogic = 0; + + switch(irq_map->irq_info.mode) + { + case PIN_IRQ_MODE_RISING: + { + gpio.interruptMode = kGPIO_IntRisingEdge; + } + break; + + case PIN_IRQ_MODE_FALLING: + { + gpio.interruptMode = kGPIO_IntFallingEdge; + } + break; + + case PIN_IRQ_MODE_RISING_FALLING: + { + gpio.interruptMode = kGPIO_IntRisingOrFallingEdge; + } + break; + + case PIN_IRQ_MODE_HIGH_LEVEL: + { + gpio.interruptMode = kGPIO_IntHighLevel; + } + break; + + case PIN_IRQ_MODE_LOW_LEVEL: + { + gpio.interruptMode = kGPIO_IntLowLevel; + } + break; + } + + if(rt1052_pin_map[pin].gpio != GPIO5) + { + IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); + } + else + { + IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); + } + + irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); + + NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0)); + EnableIRQ(irq_num); + + GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); + GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin); + } + else if(enabled == PIN_IRQ_DISABLE) + { + if(irq_map->enable == PIN_IRQ_DISABLE) + { + return RT_EOK; + } + + irq_map->enable = PIN_IRQ_DISABLE; + irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); + + NVIC_DisableIRQ(irq_num); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} + +int rt_hw_pin_init(void) +{ + int ret = RT_EOK; + + rt1052_pin_ops.pin_mode = rt1052_pin_mode; + rt1052_pin_ops.pin_read = rt1052_pin_read; + rt1052_pin_ops.pin_write = rt1052_pin_write; + rt1052_pin_ops.pin_attach_irq = rt1052_pin_attach_irq; + rt1052_pin_ops.pin_detach_irq = rt1052_pin_detach_irq; + rt1052_pin_ops.pin_irq_enable = rt1052_pin_irq_enable; + + ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL); + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /*RT_USING_PIN */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.h new file mode 100644 index 0000000000..55e09ebc10 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-13 Liuguang the first version. + * 2018-03-19 Liuguang add GPIO interrupt mode support. + */ + +#ifndef __DRV_PIN_H__ +#define __DRV_PIN_H__ + +#include +#include + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_rtc.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_rtc.c new file mode 100644 index 0000000000..06cb2e9094 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_rtc.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-15 Liuguang the first version. + */ +#include "drv_rtc.h" + +#include "fsl_common.h" +#include "fsl_snvs_hp.h" +#include "fsl_snvs_lp.h" +#include + +#ifdef RT_USING_RTC + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +static time_t get_timestamp(void) +{ + struct tm tm_new = {0}; + snvs_hp_rtc_datetime_t rtcDate; + + SNVS_HP_RTC_GetDatetime(SNVS, &rtcDate); + + tm_new.tm_sec = rtcDate.second; + tm_new.tm_min = rtcDate.minute; + tm_new.tm_hour = rtcDate.hour; + + tm_new.tm_mday = rtcDate.day; + tm_new.tm_mon = rtcDate.month - 1; + tm_new.tm_year = rtcDate.year - 1900; + + return mktime(&tm_new); +} + +static int set_timestamp(time_t timestamp) +{ + struct tm *p_tm; + snvs_hp_rtc_datetime_t rtcDate; + + p_tm = localtime(×tamp); + + rtcDate.second = p_tm->tm_sec ; + rtcDate.minute = p_tm->tm_min ; + rtcDate.hour = p_tm->tm_hour; + + rtcDate.day = p_tm->tm_mday; + rtcDate.month = p_tm->tm_mon + 1; + rtcDate.year = p_tm->tm_year + 1900; + + SNVS_HP_RTC_SetDatetime(SNVS, &rtcDate); + + return RT_EOK; +} + +static rt_err_t rt1052_hp_rtc_init(rt_device_t dev) +{ + snvs_hp_rtc_config_t snvsRtcConfig; + + SNVS_HP_RTC_GetDefaultConfig(&snvsRtcConfig); + SNVS_HP_RTC_Init(SNVS, &snvsRtcConfig); + + SNVS_HP_RTC_StartTimer(SNVS); + + return RT_EOK; +} + +static rt_err_t rt1052_hp_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt1052_hp_rtc_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt1052_hp_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_size_t rt1052_hp_rtc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt1052_hp_rtc_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch(cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + { + *(uint32_t *)args = get_timestamp(); + } + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + set_timestamp(*(time_t *)args); + } + break; + + default: + return RT_EINVAL; + } + + return RT_EOK; +} + +static struct rt_device device = +{ + .type = RT_Device_Class_RTC, + .init = rt1052_hp_rtc_init, + .open = rt1052_hp_rtc_open, + .close = rt1052_hp_rtc_close, + .read = rt1052_hp_rtc_read, + .write = rt1052_hp_rtc_write, + .control = rt1052_hp_rtc_control, +}; + +int rt_hw_hp_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + + ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); + if(ret != RT_EOK) + { + return ret; + } + + rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_hp_rtc_init); + +#endif /*RT_USING_RTC */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_rtc.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_rtc.h new file mode 100644 index 0000000000..c31cd80687 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_rtc.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-15 Liuguang the first version. + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include +#include + +int rt_hw_hp_rtc_init(void); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_sdio.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_sdio.c new file mode 100644 index 0000000000..27f58643f5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_sdio.c @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek first version + */ + +#include +#include +#include + +#include +#include +#include + +#include + +#define RT_USING_SDIO1 +#define RT_USING_SDIO2 + +//#define DEBUG + +#ifdef DEBUG +static int enable_log = 1; + +#define MMCSD_DGB(fmt, ...) \ + do \ + { \ + if (enable_log) \ + { \ + rt_kprintf(fmt, ##__VA_ARGS__); \ + } \ + } while (0) +#else +#define MMCSD_DGB(fmt, ...) +#endif + +#define CACHE_LINESIZE (32) + +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL) + +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ +#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ +#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define USDHC_READ_WATERMARK_LEVEL (0x80U) +#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* DMA mode */ +#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 + +/* Endian mode. */ +#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle + +ALIGN(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable"); + +struct imxrt_mmcsd +{ + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + + struct rt_timer timer; + + rt_uint32_t *buf; + + //USDHC_Type *base; + usdhc_host_t usdhc_host; + clock_div_t usdhc_div; + clock_ip_name_t ip_clock; + + uint32_t *usdhc_adma2_table; +}; + +static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd) +{ + gpio_pin_config_t sw_config; + + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + +#ifdef RT_USING_SDIO1 + if (mmcsd->usdhc_host.base == USDHC1) + { + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0); + + /* voltage select PIN */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0); + + /* card detect PIN */ + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0); + /* power reset pin */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + + /*voltage select pin*/ + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(4)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_GPIO2_IO28, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); + + sw_config.direction = kGPIO_DigitalOutput; + sw_config.outputLogic = 0; + sw_config.interruptMode = kGPIO_NoIntmode; + + GPIO_PinInit(GPIO1, 5U, &sw_config); + GPIO_PinWrite(GPIO1, 5U, true); + } + else +#endif + +#ifdef RT_USING_SDIO2 + if (mmcsd->usdhc_host.base == USDHC2) + { + // todo + } +#endif + +} + +static void SDMMCHOST_ErrorRecovery(USDHC_Type *base) +{ + uint32_t status = 0U; + /* get host present status */ + status = USDHC_GetPresentStatusFlags(base); + /* check command inhibit status flag */ + if ((status & kUSDHC_CommandInhibitFlag) != 0U) + { + /* reset command line */ + USDHC_Reset(base, kUSDHC_ResetCommand, 1000U); + } + /* check data inhibit status flag */ + if ((status & kUSDHC_DataInhibitFlag) != 0U) + { + /* reset data line */ + USDHC_Reset(base, kUSDHC_ResetData, 1000U); + } +} + +static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd) +{ + usdhc_host_t *usdhc_host = &mmcsd->usdhc_host; + + /* Initializes SDHC. */ + usdhc_host->config.dataTimeout = USDHC_DATA_TIMEOUT; + usdhc_host->config.endianMode = USDHC_ENDIAN_MODE; + usdhc_host->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL; + usdhc_host->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL; + usdhc_host->config.readBurstLen = USDHC_READ_BURST_LEN; + usdhc_host->config.writeBurstLen = USDHC_WRITE_BURST_LEN; + + USDHC_Init(usdhc_host->base, &(usdhc_host->config)); +} + +static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd) +{ + CLOCK_EnableClock(mmcsd->ip_clock); + CLOCK_SetDiv(mmcsd->usdhc_div, 5U); +} + +static void _mmcsd_isr_init(struct imxrt_mmcsd *mmcsd) +{ + //NVIC_SetPriority(USDHC1_IRQn, 5U); +} + +static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct imxrt_mmcsd *mmcsd; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + status_t error; + usdhc_adma_config_t dmaConfig; + usdhc_transfer_t fsl_content = {0}; + usdhc_command_t fsl_command = {0}; + usdhc_data_t fsl_data = {0}; + rt_uint32_t *buf = NULL; + + RT_ASSERT(host != RT_NULL); + RT_ASSERT(req != RT_NULL); + + mmcsd = (struct imxrt_mmcsd *)host->private_data; + RT_ASSERT(mmcsd != RT_NULL); + + cmd = req->cmd; + RT_ASSERT(cmd != RT_NULL); + + MMCSD_DGB("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags); + + data = cmd->data; + + memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t)); + /* config adma */ + dmaConfig.dmaMode = USDHC_DMA_MODE; + dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR; + dmaConfig.admaTable = mmcsd->usdhc_adma2_table; + dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS; + + fsl_command.index = cmd->cmd_code; + fsl_command.argument = cmd->arg; + + if (cmd->cmd_code == STOP_TRANSMISSION) + fsl_command.type = kCARD_CommandTypeAbort; + else + fsl_command.type = kCARD_CommandTypeNormal; + + switch (cmd->flags & RESP_MASK) + { + case RESP_NONE: + fsl_command.responseType = kCARD_ResponseTypeNone; + break; + case RESP_R1: + fsl_command.responseType = kCARD_ResponseTypeR1; + break; + case RESP_R1B: + fsl_command.responseType = kCARD_ResponseTypeR1b; + break; + case RESP_R2: + fsl_command.responseType = kCARD_ResponseTypeR2; + break; + case RESP_R3: + fsl_command.responseType = kCARD_ResponseTypeR3; + break; + case RESP_R4: + fsl_command.responseType = kCARD_ResponseTypeR4; + break; + case RESP_R6: + fsl_command.responseType = kCARD_ResponseTypeR6; + break; + case RESP_R7: + fsl_command.responseType = kCARD_ResponseTypeR7; + break; + case RESP_R5: + fsl_command.responseType = kCARD_ResponseTypeR5; + break; + /* + case RESP_R5B: + fsl_command.responseType = kCARD_ResponseTypeR5b; + break; + */ + default: + RT_ASSERT(NULL); + } + + // command type + /* + switch (cmd->flags & CMD_MASK) + { + case CMD_AC: + break; + case CMD_ADTC: + break; + case CMD_BC: + break; + case CMD_BCR: + break; + } + */ + + fsl_command.flags = 0; + //fsl_command.response + //fsl_command.responseErrorFlags + + fsl_content.command = &fsl_command; + + if (data) + { + if (req->stop != NULL) + fsl_data.enableAutoCommand12 = true; + else + fsl_data.enableAutoCommand12 = false; + + fsl_data.enableAutoCommand23 = false; + + fsl_data.enableIgnoreError = false; + fsl_data.dataType = kUSDHC_TransferDataNormal; //todo : update data type + fsl_data.blockSize = data->blksize; + fsl_data.blockCount = data->blks; + + MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount); + + if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte) + ((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM + ((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM + { + + buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE); + RT_ASSERT(buf != RT_NULL); + + MMCSD_DGB(" malloc buf: %p, data->buf:%p, %d ", buf, data->buf, fsl_data.blockSize * fsl_data.blockCount); + } + + + if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK)) + { + if (buf) + { + MMCSD_DGB(" write(data->buf to buf) "); + rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount); + fsl_data.txData = (uint32_t const *)buf; + } + else + { + fsl_data.txData = (uint32_t const *)data->buf; + } + + fsl_data.rxData = NULL; + } + else + { + if (buf) + { + fsl_data.rxData = (uint32_t *)buf; + } + else + { + fsl_data.rxData = (uint32_t *)data->buf; + } + + fsl_data.txData = NULL; + } + + fsl_content.data = &fsl_data; + } + else + { + fsl_content.data = NULL; + } + + error = USDHC_TransferBlocking(mmcsd->usdhc_host.base, &dmaConfig, &fsl_content); + if (error == kStatus_Fail) + { + SDMMCHOST_ErrorRecovery(mmcsd->usdhc_host.base); + MMCSD_DGB(" ***USDHC_TransferBlocking error: %d*** --> \n", error); + cmd->err = -RT_ERROR; + } + + if (buf) + { + if (fsl_data.rxData) + { + MMCSD_DGB("read copy buf to data->buf "); + rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount); + } + + rt_free_align(buf); + } + + if ((cmd->flags & RESP_MASK) == RESP_R2) + { + cmd->resp[3] = fsl_command.response[0]; + cmd->resp[2] = fsl_command.response[1]; + cmd->resp[1] = fsl_command.response[2]; + cmd->resp[0] = fsl_command.response[3]; + MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + cmd->resp[0] = fsl_command.response[0]; + MMCSD_DGB(" resp 0x%08X\n", cmd->resp[0]); + } + + mmcsd_req_complete(host); + + return; +} + +static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + + struct imxrt_mmcsd *mmcsd; + unsigned int usdhc_clk; + unsigned int bus_width; + uint32_t src_clk; + + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(io_cfg != RT_NULL); + + mmcsd = (struct imxrt_mmcsd *)host->private_data; + usdhc_clk = io_cfg->clock; + bus_width = io_cfg->bus_width; + + if (usdhc_clk > IMXRT_MAX_FREQ) + usdhc_clk = IMXRT_MAX_FREQ; + src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U)); + + MMCSD_DGB("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width); + + if (usdhc_clk) + { + USDHC_SetSdClock(mmcsd->usdhc_host.base, src_clk, usdhc_clk); + //CLOCK_EnableClock(mmcsd->ip_clock); + + /* Change bus width */ + if (bus_width == MMCSD_BUS_WIDTH_8) + USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth8Bit); + else if (bus_width == MMCSD_BUS_WIDTH_4) + USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth4Bit); + else if (bus_width == MMCSD_BUS_WIDTH_1) + USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth1Bit); + else + RT_ASSERT(RT_NULL); + } + else + { + //CLOCK_DisableClock(mmcsd->ip_clock); + } + +} + +#ifdef DEBUG +static void log_toggle(int en) +{ + enable_log = en; +} +FINSH_FUNCTION_EXPORT(log_toggle, toglle log dumple); +#endif + +//static rt_int32_t _mmc_get_card_status(struct rt_mmcsd_host *host) +//{ +// MMCSD_DGB("%s, start\n", __func__); +// MMCSD_DGB("%s, end\n", __func__); +// +// return 0; +//} +// +//static void _mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) +//{ +// +//} + +static const struct rt_mmcsd_host_ops ops = +{ + _mmc_request, + _mmc_set_iocfg, + RT_NULL,//_mmc_get_card_status, + RT_NULL,//_mmc_enable_sdio_irq, +}; + +rt_int32_t _imxrt_mci_init(void) +{ + struct rt_mmcsd_host *host; + struct imxrt_mmcsd *mmcsd; + + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } + + mmcsd = rt_malloc(sizeof(struct imxrt_mmcsd)); + if (!mmcsd) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } + + rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd)); + mmcsd->usdhc_host.base = USDHC1; + mmcsd->usdhc_div = kCLOCK_Usdhc1Div; + mmcsd->usdhc_adma2_table = g_usdhcAdma2Table; + + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + mmcsd->host = host; + + _mmcsd_clk_init(mmcsd); + _mmcsd_isr_init(mmcsd); + _mmcsd_gpio_init(mmcsd); + _mmcsd_host_init(mmcsd); + + host->private_data = mmcsd; + + mmcsd_change(host); + + return 0; + +err: + mmcsd_free_host(host); + + return -RT_ENOMEM; +} + +int imxrt_mci_init(void) +{ + /* initilize sd card */ + _imxrt_mci_init(); + + return 0; +} +INIT_DEVICE_EXPORT(imxrt_mci_init); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_sdram.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_sdram.c new file mode 100644 index 0000000000..f54b448779 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_sdram.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-12-04 Tanek first implementation + */ +#include +#include +#include + +static uint32_t _RDWORD(uint32_t address) +{ + return *((uint32_t *)address); +} + +static void _WDWORD(uint32_t address, uint32_t value) +{ + *((uint32_t *)address) = value; +} + +static void SDRAM_WaitIpCmdDone(void) +{ + unsigned long reg; + do + { + reg = _RDWORD(0x402F003C); + }while((reg & 0x3) == 0); +} + +static void _clock_init(void) +{ + // Enable all clocks + _WDWORD(0x400FC068,0xffffffff); + _WDWORD(0x400FC06C,0xffffffff); + _WDWORD(0x400FC070,0xffffffff); + _WDWORD(0x400FC074,0xffffffff); + _WDWORD(0x400FC078,0xffffffff); + _WDWORD(0x400FC07C,0xffffffff); + _WDWORD(0x400FC080,0xffffffff); + + _WDWORD(0x400D8030,0x00002001); + _WDWORD(0x400D8100,0x001d0000); + _WDWORD(0x400FC014,0x00010D40); +} + +static void _sdr_Init(void) +{ + // Config IOMUX + _WDWORD(0x401F8014, 0x00000000); + _WDWORD(0x401F8018, 0x00000000); + _WDWORD(0x401F801C, 0x00000000); + _WDWORD(0x401F8020, 0x00000000); + _WDWORD(0x401F8024, 0x00000000); + _WDWORD(0x401F8028, 0x00000000); + _WDWORD(0x401F802C, 0x00000000); + _WDWORD(0x401F8030, 0x00000000); + _WDWORD(0x401F8034, 0x00000000); + _WDWORD(0x401F8038, 0x00000000); + _WDWORD(0x401F803C, 0x00000000); + _WDWORD(0x401F8040, 0x00000000); + _WDWORD(0x401F8044, 0x00000000); + _WDWORD(0x401F8048, 0x00000000); + _WDWORD(0x401F804C, 0x00000000); + _WDWORD(0x401F8050, 0x00000000); + _WDWORD(0x401F8054, 0x00000000); + _WDWORD(0x401F8058, 0x00000000); + _WDWORD(0x401F805C, 0x00000000); + _WDWORD(0x401F8060, 0x00000000); + _WDWORD(0x401F8064, 0x00000000); + _WDWORD(0x401F8068, 0x00000000); + _WDWORD(0x401F806C, 0x00000000); + _WDWORD(0x401F8070, 0x00000000); + _WDWORD(0x401F8074, 0x00000000); + _WDWORD(0x401F8078, 0x00000000); + _WDWORD(0x401F807C, 0x00000000); + _WDWORD(0x401F8080, 0x00000000); + _WDWORD(0x401F8084, 0x00000000); + _WDWORD(0x401F8088, 0x00000000); + _WDWORD(0x401F808C, 0x00000000); + _WDWORD(0x401F8090, 0x00000000); + _WDWORD(0x401F8094, 0x00000000); + _WDWORD(0x401F8098, 0x00000000); + _WDWORD(0x401F809C, 0x00000000); + _WDWORD(0x401F80A0, 0x00000000); + _WDWORD(0x401F80A4, 0x00000000); + _WDWORD(0x401F80A8, 0x00000000); + _WDWORD(0x401F80AC, 0x00000000); + _WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION + _WDWORD(0x401F80B4, 0x00000000); + _WDWORD(0x401F80B8, 0x00000000); + + // PAD ctrl + // drive strength = 0x7 to increase drive strength + // otherwise the data7 bit may fail. + _WDWORD(0x401F8204, 0x000110F9); + _WDWORD(0x401F8208, 0x000110F9); + _WDWORD(0x401F820C, 0x000110F9); + _WDWORD(0x401F8210, 0x000110F9); + _WDWORD(0x401F8214, 0x000110F9); + _WDWORD(0x401F8218, 0x000110F9); + _WDWORD(0x401F821C, 0x000110F9); + _WDWORD(0x401F8220, 0x000110F9); + _WDWORD(0x401F8224, 0x000110F9); + _WDWORD(0x401F8228, 0x000110F9); + _WDWORD(0x401F822C, 0x000110F9); + _WDWORD(0x401F8230, 0x000110F9); + _WDWORD(0x401F8234, 0x000110F9); + _WDWORD(0x401F8238, 0x000110F9); + _WDWORD(0x401F823C, 0x000110F9); + _WDWORD(0x401F8240, 0x000110F9); + _WDWORD(0x401F8244, 0x000110F9); + _WDWORD(0x401F8248, 0x000110F9); + _WDWORD(0x401F824C, 0x000110F9); + _WDWORD(0x401F8250, 0x000110F9); + _WDWORD(0x401F8254, 0x000110F9); + _WDWORD(0x401F8258, 0x000110F9); + _WDWORD(0x401F825C, 0x000110F9); + _WDWORD(0x401F8260, 0x000110F9); + _WDWORD(0x401F8264, 0x000110F9); + _WDWORD(0x401F8268, 0x000110F9); + _WDWORD(0x401F826C, 0x000110F9); + _WDWORD(0x401F8270, 0x000110F9); + _WDWORD(0x401F8274, 0x000110F9); + _WDWORD(0x401F8278, 0x000110F9); + _WDWORD(0x401F827C, 0x000110F9); + _WDWORD(0x401F8280, 0x000110F9); + _WDWORD(0x401F8284, 0x000110F9); + _WDWORD(0x401F8288, 0x000110F9); + _WDWORD(0x401F828C, 0x000110F9); + _WDWORD(0x401F8290, 0x000110F9); + _WDWORD(0x401F8294, 0x000110F9); + _WDWORD(0x401F8298, 0x000110F9); + _WDWORD(0x401F829C, 0x000110F9); + _WDWORD(0x401F82A0, 0x000110F9); + _WDWORD(0x401F82A4, 0x000110F9); + _WDWORD(0x401F82A8, 0x000110F9); + + // Config SDR Controller Registers/ + _WDWORD(0x402F0000,0x10000004); // MCR + _WDWORD(0x402F0008,0x00030524); // BMCR0 + _WDWORD(0x402F000C,0x06030524); // BMCR1 + _WDWORD(0x402F0010,0x8000001B); // BR0, 32MB + _WDWORD(0x402F0014,0x8200001B); // BR1, 32MB + _WDWORD(0x402F0018,0x8400001B); // BR2, 32MB + _WDWORD(0x402F001C,0x8600001B); // BR3, 32MB + _WDWORD(0x402F0020,0x90000021); // BR4, + _WDWORD(0x402F0024,0xA0000019); // BR5, + _WDWORD(0x402F0028,0xA8000017); // BR6, + _WDWORD(0x402F002C,0xA900001B); // BR7, + _WDWORD(0x402F0030,0x00000021); // BR8, + _WDWORD(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE. + + // _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1 + _WDWORD(0x402F0040,0x00000F31); // SDRAMCR0 + _WDWORD(0x402F0044,0x00652922); // SDRAMCR1 + _WDWORD(0x402F0048,0x00010920); // SDRAMCR2 + _WDWORD(0x402F004C,0x50210A08); // SDRAMCR3 + + _WDWORD(0x402F0080,0x00000021); // DBICR0 + _WDWORD(0x402F0084,0x00888888); // DBICR1 + _WDWORD(0x402F0094,0x00000002); // IPCR1 + _WDWORD(0x402F0098,0x00000000); // IPCR2 + + _WDWORD(0x402F0090,0x80000000); // IPCR0 + _WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F0090,0x80000000); // IPCR0 + _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F0090,0x80000000); // IPCR0 + _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F00A0,0x00000033); // IPTXDAT + _WDWORD(0x402F0090,0x80000000); // IPCR0 + _WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS + SDRAM_WaitIpCmdDone(); + _WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done. +} + +int imxrt_sdram_init(void) +{ + _clock_init(); + _sdr_Init(); + + return 0; +} + +/*@}*/ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_bus.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_bus.c new file mode 100644 index 0000000000..eb7e39dcf2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_bus.c @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-27 Liuguang the first version. + */ + +#include "drv_spi_bus.h" + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_lpspi.h" + +#if defined(RT_USING_SPIBUS1) || defined(RT_USING_SPIBUS2) || \ + defined(RT_USING_SPIBUS3) || defined(RT_USING_SPIBUS4) + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +#if !defined(LPSPI_CLK_SOURCE) +#define LPSPI_CLK_SOURCE (1U) /* PLL3 PFD0 */ +#endif +#if !defined(LPSPI_CLK_SOURCE_DIVIDER) +#define LPSPI_CLK_SOURCE_DIVIDER (8U) /* 8div */ +#endif + +/* LPSPI1 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI1_SCK_GPIO_1) +#define LPSPI1_SCK_GPIO IOMUXC_GPIO_EMC_27_LPSPI1_SCK +#elif defined(LPSPI1_SCK_GPIO_2) +#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK +#else +#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK +#endif + +#if defined(LPSPI1_SDO_GPIO_1) +#define LPSPI1_SDO_GPIO IOMUXC_GPIO_EMC_28_LPSPI1_SDO +#elif defined(LPSPI1_SDO_GPIO_2) +#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO +#else +#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO +#endif + +#if defined(LPSPI1_SDI_GPIO_1) +#define LPSPI1_SDI_GPIO IOMUXC_GPIO_EMC_29_LPSPI1_SDI +#elif defined(LPSPI1_SDI_GPIO_2) +#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI +#else +#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI +#endif + +/* LPSPI2 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI2_SCK_GPIO_1) +#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK +#elif defined(LPSPI2_SCK_GPIO_2) +#define LPSPI2_SCK_GPIO IOMUXC_GPIO_EMC_00_LPSPI2_SCK +#else +#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK +#endif + +#if defined(LPSPI2_SDO_GPIO_1) +#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 +#elif defined(LPSPI2_SDO_GPIO_2) +#define LPSPI2_SDO_GPIO IOMUXC_GPIO_EMC_02_LPSPI2_SDO +#else +#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 +#endif + +#if defined(LPSPI2_SDI_GPIO_1) +#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI +#elif defined(LPSPI2_SDI_GPIO_2) +#define LPSPI2_SDI_GPIO IOMUXC_GPIO_EMC_03_LPSPI2_SDI +#else +#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI +#endif + +/* LPSPI3 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI3_SCK_GPIO_1) +#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK +#elif defined(LPSPI3_SCK_GPIO_2) +#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK +#else +#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK +#endif + +#if defined(LPSPI3_SDO_GPIO_1) +#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO +#elif defined(LPSPI3_SDO_GPIO_2) +#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO +#else +#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO +#endif + +#if defined(LPSPI3_SDI_GPIO_1) +#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI +#elif defined(LPSPI3_SDI_GPIO_2) +#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI +#else +#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI +#endif + +/* LPSPI4 SCK SDO SDI IOMUX Config */ +#if defined(LPSPI4_SCK_GPIO_1) +#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK +#elif defined(LPSPI4_SCK_GPIO_2) +#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B1_07_LPSPI4_SCK +#else +#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK +#endif + +#if defined(LPSPI4_SDO_GPIO_1) +#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO +#elif defined(LPSPI4_SDO_GPIO_2) +#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B1_06_LPSPI4_SDO +#else +#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO +#endif + +#if defined(LPSPI4_SDI_GPIO_1) +#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI +#elif defined(LPSPI4_SDI_GPIO_2) +#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B1_05_LPSPI4_SDI +#else +#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI +#endif + +struct rt1050_spi +{ + LPSPI_Type *base; + struct rt_spi_configuration *cfg; +}; + +struct rt1050_sw_spi_cs +{ + rt_uint32_t pin; +}; + +static uint32_t rt1050_get_lpspi_freq(void) +{ + uint32_t freq = 0; + + /* CLOCK_GetMux(kCLOCK_LpspiMux): + 00b: derive clock from PLL3 PFD1 720M + 01b: derive clock from PLL3 PFD0 720M + 10b: derive clock from PLL2 528M + 11b: derive clock from PLL2 PFD2 396M + */ + switch(CLOCK_GetMux(kCLOCK_LpspiMux)) + { + case 0: + freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); + break; + + case 1: + freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); + break; + + case 2: + freq = CLOCK_GetFreq(kCLOCK_SysPllClk); + break; + + case 3: + freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk); + break; + } + + freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); + + return freq; +} + +static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *cfg) +{ + lpspi_master_config_t masterConfig; + + RT_ASSERT(cfg != RT_NULL); + + if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) + { + return RT_EINVAL; + } + +#if defined(RT_USING_SPIBUS1) + if(base == LPSPI1) + { + IOMUXC_SetPinMux (LPSPI1_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI1_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI1_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI1_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI1_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI1_SDI_GPIO, 0x10B0u); + } +#endif + +#if defined(RT_USING_SPIBUS2) + if(base == LPSPI2) + { + IOMUXC_SetPinMux (LPSPI2_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI2_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI2_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI2_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI2_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI2_SDI_GPIO, 0x10B0u); + } +#endif + +#if defined(RT_USING_SPIBUS3) + if(base == LPSPI3) + { + IOMUXC_SetPinMux (LPSPI3_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI3_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI3_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI3_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI3_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI3_SDI_GPIO, 0x10B0u); + } +#endif + +#if defined(RT_USING_SPIBUS4) + if(base == LPSPI4) + { + IOMUXC_SetPinMux (LPSPI4_SCK_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI4_SCK_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI4_SDO_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI4_SDO_GPIO, 0x10B0u); + IOMUXC_SetPinMux (LPSPI4_SDI_GPIO, 0U); + IOMUXC_SetPinConfig(LPSPI4_SDI_GPIO, 0x10B0u); + } +#endif + + LPSPI_MasterGetDefaultConfig(&masterConfig); + + if(cfg->max_hz > 40*1000*1000) + { + cfg->max_hz = 40*1000*1000; + } + masterConfig.baudRate = cfg->max_hz; + masterConfig.bitsPerFrame = cfg->data_width; + + if(cfg->mode & RT_SPI_MSB) + { + masterConfig.direction = kLPSPI_MsbFirst; + } + else + { + masterConfig.direction = kLPSPI_LsbFirst; + } + + if(cfg->mode & RT_SPI_CPHA) + { + masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; + } + else + { + masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; + } + + if(cfg->mode & RT_SPI_CPOL) + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; + } + else + { + masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; + } + + masterConfig.pinCfg = kLPSPI_SdiInSdoOut; + masterConfig.dataOutConfig = kLpspiDataOutTristate; + masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; + masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; + + LPSPI_MasterInit(base, &masterConfig, rt1050_get_lpspi_freq()); + base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; + + return RT_EOK; +} + +rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct rt1050_sw_spi_cs *cs_pin = (struct rt1050_sw_spi_cs *)rt_malloc(sizeof(struct rt1050_sw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + rt_err_t ret = RT_EOK; + struct rt1050_spi *spi = RT_NULL; + + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + + spi = (struct rt1050_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = rt1050_spi_init(spi->base, cfg); + + return ret; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + lpspi_transfer_t transfer; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data); + struct rt1050_sw_spi_cs *cs = device->parent.user_data; + + if(message->cs_take) + { + rt_pin_write(cs->pin, PIN_LOW); + } + + transfer.dataSize = message->length; + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); + + LPSPI_MasterTransferBlocking(spi->base, &transfer); + + if(message->cs_release) + { + rt_pin_write(cs->pin, PIN_HIGH); + } + + return message->length; +} + +#if defined(RT_USING_SPIBUS1) +static struct rt1050_spi spi1 = +{ + .base = LPSPI1 +}; +static struct rt_spi_bus spi1_bus = +{ + .parent.user_data = &spi1 +}; +#endif + +#if defined(RT_USING_SPIBUS2) +static struct rt1050_spi spi2 = +{ + .base = LPSPI2 +}; +static struct rt_spi_bus spi2_bus = +{ + .parent.user_data = &spi2 +}; +#endif + +#if defined(RT_USING_SPIBUS3) +static struct rt1050_spi spi3 = +{ + .base = LPSPI3 +}; +static struct rt_spi_bus spi3_bus = +{ + .parent.user_data = &spi3 +}; +#endif + +#if defined(RT_USING_SPIBUS4) +static struct rt1050_spi spi4 = +{ + .base = LPSPI4 +}; +static struct rt_spi_bus spi4_bus = +{ + .parent.user_data = &spi4 +}; +#endif + +static struct rt_spi_ops rt1050_spi_ops = +{ + .configure = spi_configure, + .xfer = spixfer +}; + +int rt_hw_spi_bus_init(void) +{ + CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI_CLK_SOURCE); + CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLK_SOURCE_DIVIDER-1); + + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if defined(RT_USING_SPIBUS1) + rt_spi_bus_register(&spi1_bus, "spi1", &rt1050_spi_ops); +#endif + +#if defined(RT_USING_SPIBUS2) + rt_spi_bus_register(&spi2_bus, "spi2", &rt1050_spi_ops); +#endif + +#if defined(RT_USING_SPIBUS3) + rt_spi_bus_register(&spi3_bus, "spi3", &rt1050_spi_ops); +#endif + +#if defined(RT_USING_SPIBUS4) + rt_spi_bus_register(&spi4_bus, "spi4", &rt1050_spi_ops); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_spi_bus_init); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_bus.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_bus.h new file mode 100644 index 0000000000..f9068893c3 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_bus.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-27 Liuguang the first version. + */ + +#ifndef __DRV_SPI_BUS_H__ +#define __DRV_SPI_BUS_H__ + +#include +#include + +int rt_hw_spi_bus_init(void); +rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_flash.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_flash.c new file mode 100644 index 0000000000..65d5bb3e22 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_flash.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-02 Liuguang the first version. + */ + +#include "drv_spi_flash.h" + +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +#ifndef SPI_FLASH_USING_SPIBUS_NAME +#define SPI_FLASH_USING_SPIBUS_NAME "spi4" +#endif +#ifndef SPI_FLASH_NAME +#define SPI_FLASH_NAME "flash0" +#endif +#ifndef SPI_FLASH_USING_CS_PIN +#define SPI_FLASH_USING_CS_PIN (79) +#endif + +int rt_hw_spi_flash_init(void) +{ + rt_err_t ret; + + extern rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, + const char *device_name, rt_uint32_t pin); + + ret = rt1050_spi_bus_attach_device(SPI_FLASH_USING_SPIBUS_NAME, + SPI_FLASH_USING_SPIBUS_NAME "0", SPI_FLASH_USING_CS_PIN); + if(ret != RT_EOK) + { + return ret; + } + + if(rt_sfud_flash_probe(SPI_FLASH_NAME, SPI_FLASH_USING_SPIBUS_NAME "0") == RT_NULL) + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_flash_init); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_flash.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_flash.h new file mode 100644 index 0000000000..3cf2837063 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_spi_flash.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-02 Liuguang the first version. + */ + +#ifndef __DRV_SPI_FLASH_H_ +#define __DRV_SPI_FLASH_H_ + +#include +#include + +int rt_hw_spi_flash_init(void); + +#endif /* __DRV_SPI_FLASH_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_uart.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_uart.c new file mode 100644 index 0000000000..c56c33d0af --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_uart.c @@ -0,0 +1,561 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek the first version + * 2018-03-17 laiyiketang Add other uart. + */ +#include +#include "drv_uart.h" + +#include "fsl_common.h" +#include "fsl_lpuart.h" +#include "fsl_iomuxc.h" + +#ifdef RT_USING_SERIAL + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +#if !defined(RT_USING_UART1) && !defined(RT_USING_UART2) && \ + !defined(RT_USING_UART3) && !defined(RT_USING_UART4) && \ + !defined(RT_USING_UART5) && !defined(RT_USING_UART6) && \ + !defined(RT_USING_UART7) && !defined(RT_USING_UART8) +#error "Please define at least one UARTx" +#endif + +#include + +/* imxrt uart driver */ +struct imxrt_uart +{ + LPUART_Type *uart_base; + IRQn_Type irqn; + + struct rt_serial_device *serial; + char *device_name; +}; + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(RT_USING_UART1) +struct rt_serial_device serial1; + +void LPUART1_IRQHandler(void) +{ + uart_isr(&serial1); +} + +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_UART2) +struct rt_serial_device serial2; + +void LPUART2_IRQHandler(void) +{ + uart_isr(&serial2); +} + +#endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) +struct rt_serial_device serial3; + +void LPUART3_IRQHandler(void) +{ + uart_isr(&serial3); +} + +#endif /* RT_USING_UART3 */ + +#if defined(RT_USING_UART4) +struct rt_serial_device serial4; + +void LPUART4_IRQHandler(void) +{ + uart_isr(&serial4); +} +#endif /* RT_USING_UART4 */ + +#if defined(RT_USING_UART5) +struct rt_serial_device serial5; + +void LPUART5_IRQHandler(void) +{ + uart_isr(&serial5); +} + +#endif /* RT_USING_UART5 */ + +#if defined(RT_USING_UART6) +struct rt_serial_device serial6; + +void LPUART6_IRQHandler(void) +{ + uart_isr(&serial6); +} + +#endif /* RT_USING_UART6 */ + +#if defined(RT_USING_UART7) +struct rt_serial_device serial7; + +void LPUART7_IRQHandler(void) +{ + uart_isr(&serial7); +} + +#endif /* RT_USING_UART7 */ + +#if defined(RT_USING_UART8) +struct rt_serial_device serial8; + +void LPUART8_IRQHandler(void) +{ + uart_isr(&serial8); +} + +#endif /* RT_USING_UART8 */ + +static const struct imxrt_uart uarts[] = +{ +#ifdef RT_USING_UART1 + { + LPUART1, + LPUART1_IRQn, + &serial1, + "uart1", + }, +#endif +#ifdef RT_USING_UART2 + { + LPUART2, + LPUART2_IRQn, + &serial2, + "uart2", + }, +#endif +#ifdef RT_USING_UART3 + { + LPUART3, + LPUART3_IRQn, + &serial3, + "uart3", + }, +#endif +#ifdef RT_USING_UART4 + { + LPUART4, + LPUART4_IRQn, + &serial4, + "uart4", + }, +#endif +#ifdef RT_USING_UART5 + { + LPUART5, + LPUART5_IRQn, + &serial5, + "uart5", + }, +#endif +#ifdef RT_USING_UART6 + { + LPUART6, + LPUART6_IRQn, + &serial6, + "uart6", + }, +#endif +#ifdef RT_USING_UART7 + { + LPUART7, + LPUART7_IRQn, + &serial7, + "uart7", + }, +#endif +#ifdef RT_USING_UART8 + { + LPUART8, + LPUART8_IRQn, + &serial8, + "uart8", + }, +#endif + +}; + +/* Get debug console frequency. */ +uint32_t GetUartSrcFreq(void) +{ + uint32_t freq; + + /* To make it simple, we assume default PLL and divider settings, and the only variable + from application is use PLL3 source or OSC source */ + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + + return freq; +} + + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example: +* - Peripheral's clock enable +* - Peripheral's GPIO Configuration +* - NVIC configuration for UART interrupt request enable +* @param huart: UART handle pointer +* @retval None +*/ +void imxrt_uart_gpio_init(struct imxrt_uart *uart) +{ + if (uart->uart_base != RT_NULL) + { +#ifdef RT_USING_UART1 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +#endif +#ifdef RT_USING_UART2 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0x10B0u); + +#endif +#ifdef RT_USING_UART3 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0x10B0u); +#endif +#ifdef RT_USING_UART4 +#ifdef BOARD_RT1050_ATK + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_00_LPUART4_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_01_LPUART4_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_00_LPUART4_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_01_LPUART4_RX, + 0x10B0u); +#else + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0x10B0u); +#endif +#endif +#ifdef RT_USING_UART5 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0x10B0u); +#endif +#ifdef RT_USING_UART6 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0x10B0u); +#endif +#ifdef RT_USING_UART7 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0x10B0u); +#endif +#ifdef RT_USING_UART8 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0x10B0u); +#endif + } + else + { + RT_ASSERT(RT_NULL); + } +} + +static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct imxrt_uart *uart; + lpuart_config_t config; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct imxrt_uart *)serial->parent.user_data; + + imxrt_uart_gpio_init(uart); + + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = cfg->baud_rate; + + switch (cfg->data_bits) + { + case DATA_BITS_7: + config.dataBitsCount = kLPUART_SevenDataBits; + break; + + default: + config.dataBitsCount = kLPUART_EightDataBits; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + config.stopBitCount = kLPUART_TwoStopBit; + break; + default: + config.stopBitCount = kLPUART_OneStopBit; + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + config.parityMode = kLPUART_ParityOdd; + break; + case PARITY_EVEN: + config.parityMode = kLPUART_ParityEven; + break; + default: + config.parityMode = kLPUART_ParityDisabled; + break; + } + + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(uart->uart_base, &config, GetUartSrcFreq()); + LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); + + return RT_EOK; +} + +static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct imxrt_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct imxrt_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + DisableIRQ(uart->irqn); + + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + EnableIRQ(uart->irqn); + break; + } + + return RT_EOK; +} + +static int imxrt_putc(struct rt_serial_device *serial, char ch) +{ + struct imxrt_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct imxrt_uart *)serial->parent.user_data; + + LPUART_WriteByte(uart->uart_base, ch); + while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)); + + return 1; +} + +static int imxrt_getc(struct rt_serial_device *serial) +{ + int ch; + struct imxrt_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct imxrt_uart *)serial->parent.user_data; + + ch = -1; + if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag) + ch = LPUART_ReadByte(uart->uart_base); + return ch; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct imxrt_uart *uart; + LPUART_Type *base; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct imxrt_uart *) serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + base = uart->uart_base; + RT_ASSERT(base != RT_NULL); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver -------------------------------------------------*/ + if (LPUART_GetStatusFlags(base) & kLPUART_RxDataRegFullFlag) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & base->STAT) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static const struct rt_uart_ops imxrt_uart_ops = +{ + imxrt_configure, + imxrt_control, + imxrt_putc, + imxrt_getc, +}; + +int imxrt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i].serial->ops = &imxrt_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&uarts[i]); + } + + return 0; +} +INIT_BOARD_EXPORT(imxrt_hw_uart_init); + +#endif /*RT_USING_SERIAL */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_uart.h b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_uart.h new file mode 100644 index 0000000000..edfb1084f0 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek the first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +int imxrt_hw_uart_init(void); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_usbd.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_usbd.c new file mode 100644 index 0000000000..3482130ed2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_usbd.c @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-12-04 ZYH first implementation + */ +#include +#include +#include +#include +#include +#include +#include +#ifdef RT_USING_EHCI0_AS_DEVICE +#ifdef RT_USING_EHCI1_AS_DEVICE +#error Can not using 2 controller as usb device +#endif +#endif +#define FSL_USB_HS + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#define BOARD_XTAL0_CLK_HZ 24000000U + +#ifdef RT_USING_EHCI0_AS_DEVICE +static usb_device_handle ehci0_handle; +static struct udcd _fsl_udc_0; +#endif +#ifdef RT_USING_EHCI1_AS_DEVICE +static usb_device_handle ehci1_handle; +static struct udcd _fsl_udc_1; +#endif + + + +static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); +static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam); +void USB_DeviceIsrEnable(uint8_t controllerId) +{ + uint8_t irqNumber; +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + uint8_t usbDeviceEhciIrq[] = USBHS_IRQS; + irqNumber = usbDeviceEhciIrq[controllerId - kUSB_ControllerEhci0]; +#endif +/* Install isr, set priority, and enable IRQ. */ +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority((IRQn_Type)irqNumber, 3); +#else + NVIC_SetPriority((IRQn_Type)irqNumber, 3); +#endif + EnableIRQ((IRQn_Type)irqNumber); +} +void USB_DeviceClockInit(uint8_t controllerId) +{ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; +#endif +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + if (controllerId == kUSB_ControllerEhci0) + { + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); + } + else + { + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); + } + USB_EhciPhyInit(controllerId, BOARD_XTAL0_CLK_HZ, &phyConfig); +#endif +} +#ifdef RT_USING_EHCI0_AS_DEVICE +#ifdef FSL_USB_HS +static struct ep_id _ehci0_ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; +#else +static struct ep_id _ehci0_ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; +#endif +void USB_OTG1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + USB_DeviceEhciIsrFunction(ehci0_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +static rt_err_t _ehci0_ep_set_stall(rt_uint8_t address) +{ + USB_DeviceStallEndpoint(ehci0_handle, address); + return RT_EOK; +} +static rt_err_t _ehci0_ep_clear_stall(rt_uint8_t address) +{ + USB_DeviceUnstallEndpoint(ehci0_handle, address); + return RT_EOK; +} + +static rt_err_t _ehci0_set_address(rt_uint8_t address) +{ + USB_DeviceSetStatus(ehci0_handle, kUSB_DeviceStatusAddress, &address); + return RT_EOK; +} +static rt_err_t _ehci0_set_config(rt_uint8_t address) +{ + return RT_EOK; +} +static rt_err_t _ehci0_ep_enable(uep_t ep) +{ + usb_device_endpoint_init_struct_t ep_init; + usb_device_endpoint_callback_struct_t ep_callback; + rt_uint32_t param = ep->ep_desc->bEndpointAddress; + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize; + ep_init.endpointAddress = ep->ep_desc->bEndpointAddress; + ep_init.transferType = ep->ep_desc->bmAttributes; + ep_init.zlt = 0; + ep_callback.callbackFn = usb_device_endpoint_callback; + ep_callback.callbackParam = (void *)param; + ep_callback.isBusy = 0; + USB_DeviceInitEndpoint(ehci0_handle,&ep_init,&ep_callback); + return RT_EOK; +} +static rt_err_t _ehci0_ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + USB_DeviceDeinitEndpoint(ehci0_handle, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} +static rt_size_t _ehci0_ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + + RT_ASSERT(buffer != RT_NULL); + + return size; +} +static rt_size_t _ehci0_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceRecvRequest(ehci0_handle, address, buffer, size); + return size; +} +static rt_size_t _ehci0_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceSendRequest(ehci0_handle, address, buffer, size); + return size; +} +static rt_err_t _ehci0_ep0_send_status(void) +{ + _ehci0_ep_write(0x00, NULL, 0); + return RT_EOK; +} +static rt_err_t _ehci0_suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _ehci0_wakeup(void) +{ + return RT_EOK; +} +const static struct udcd_ops _ehci0_udc_ops = +{ + _ehci0_set_address, + _ehci0_set_config, + _ehci0_ep_set_stall, + _ehci0_ep_clear_stall, + _ehci0_ep_enable, + _ehci0_ep_disable, + _ehci0_ep_read_prepare, + _ehci0_ep_read, + _ehci0_ep_write, + _ehci0_ep0_send_status, + _ehci0_suspend, + _ehci0_wakeup, +}; +static rt_err_t drv_ehci0_usbd_init(rt_device_t device) +{ + usb_status_t result; + USB_DeviceClockInit(kUSB_ControllerEhci0); + + result = USB_DeviceInit(kUSB_ControllerEhci0,usb_device_callback,&ehci0_handle); + RT_ASSERT(ehci0_handle); + if(result == kStatus_USB_Success) + { + USB_DeviceIsrEnable(kUSB_ControllerEhci0); + USB_DeviceRun(ehci0_handle); + } + else + { + rt_kprintf("USB_DeviceInit ehci0 error\r\n"); + return RT_ERROR; + } + return RT_EOK; +} +#endif +#ifdef RT_USING_EHCI1_AS_DEVICE +#ifdef FSL_USB_HS +static struct ep_id _ehci1_ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; +#else +static struct ep_id _ehci1_ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; +#endif +void USB_OTG2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + USB_DeviceEhciIsrFunction(ehci1_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +static rt_err_t _ehci1_ep_set_stall(rt_uint8_t address) +{ + USB_DeviceStallEndpoint(ehci1_handle, address); + return RT_EOK; +} +static rt_err_t _ehci1_ep_clear_stall(rt_uint8_t address) +{ + USB_DeviceUnstallEndpoint(ehci1_handle, address); + return RT_EOK; +} + +static rt_err_t _ehci1_set_address(rt_uint8_t address) +{ + USB_DeviceSetStatus(ehci1_handle, kUSB_DeviceStatusAddress, &address); + return RT_EOK; +} +static rt_err_t _ehci1_set_config(rt_uint8_t address) +{ + return RT_EOK; +} +static rt_err_t _ehci1_ep_enable(uep_t ep) +{ + usb_device_endpoint_init_struct_t ep_init; + usb_device_endpoint_callback_struct_t ep_callback; + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize; + ep_init.endpointAddress = ep->ep_desc->bEndpointAddress; + ep_init.transferType = ep->ep_desc->bmAttributes; + ep_init.zlt = 0; + ep_callback.callbackFn = usb_device_endpoint_callback; + ep_callback.callbackParam = (void *)ep_init.endpointAddress; + ep_callback.isBusy = 0; + USB_DeviceInitEndpoint(ehci1_handle,&ep_init,&ep_callback); + return RT_EOK; +} +static rt_err_t _ehci1_ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + USB_DeviceDeinitEndpoint(ehci1_handle, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} +static rt_size_t _ehci1_ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + + RT_ASSERT(buffer != RT_NULL); + + return size; +} +static rt_size_t _ehci1_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceRecvRequest(ehci1_handle, address, buffer, size); + return size; +} +static rt_size_t _ehci1_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceSendRequest(ehci1_handle, address, buffer, size); + return size; +} +static rt_err_t _ehci1_ep0_send_status(void) +{ + _ehci1_ep_write(0x00, NULL, 0); + return RT_EOK; +} +static rt_err_t _ehci1_suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _ehci1_wakeup(void) +{ + return RT_EOK; +} +const static struct udcd_ops _ehci1_udc_ops = +{ + _ehci1_set_address, + _ehci1_set_config, + _ehci1_ep_set_stall, + _ehci1_ep_clear_stall, + _ehci1_ep_enable, + _ehci1_ep_disable, + _ehci1_ep_read_prepare, + _ehci1_ep_read, + _ehci1_ep_write, + _ehci1_ep0_send_status, + _ehci1_suspend, + _ehci1_wakeup, +}; +static rt_err_t drv_ehci1_usbd_init(rt_device_t device) +{ + usb_status_t result; + USB_DeviceClockInit(kUSB_ControllerEhci1); + + result = USB_DeviceInit(kUSB_ControllerEhci1,usb_device_callback,&ehci1_handle); + RT_ASSERT(ehci1_handle); + if(result == kStatus_USB_Success) + { + USB_DeviceIsrEnable(kUSB_ControllerEhci1); + USB_DeviceRun(ehci1_handle); + } + else + { + rt_kprintf("USB_DeviceInit ehci1 error\r\n"); + return RT_ERROR; + } + return RT_EOK; +} +#endif + + + +#if defined(RT_USING_EHCI0_AS_DEVICE) && defined(RT_USING_EHCI1_AS_DEVICE) +#error Can not using both now +#endif +static int rt_usbd_init(void) +{ + #ifdef RT_USING_EHCI0_AS_DEVICE + rt_memset((void *)&_fsl_udc_0, 0, sizeof(struct udcd)); + _fsl_udc_0.parent.type = RT_Device_Class_USBDevice; + _fsl_udc_0.parent.init = drv_ehci0_usbd_init; + _fsl_udc_0.ops = &_ehci0_udc_ops; + /* Register endpoint infomation */ + _fsl_udc_0.ep_pool = _ehci0_ep_pool; + _fsl_udc_0.ep0.id = &_ehci0_ep_pool[0]; + #ifdef FSL_USB_HS + _fsl_udc_0.device_is_hs = RT_TRUE; + #else + _fsl_udc_0.device_is_hs = RT_FALSE; + #endif + rt_device_register((rt_device_t)&_fsl_udc_0, "usbd", 0); + rt_usb_device_init(); + #endif + #ifdef RT_USING_EHCI1_AS_DEVICE + rt_memset((void *)&_fsl_udc_1, 0, sizeof(struct udcd)); + _fsl_udc_1.parent.type = RT_Device_Class_USBDevice; + _fsl_udc_1.parent.init = drv_ehci1_usbd_init; + _fsl_udc_1.ops = &_ehci1_udc_ops; + /* Register endpoint infomation */ + _fsl_udc_1.ep_pool = _ehci1_ep_pool; + _fsl_udc_1.ep0.id = &_ehci1_ep_pool[0]; + #ifdef FSL_USB_HS + _fsl_udc_1.device_is_hs = RT_TRUE; + #else + _fsl_udc_1.device_is_hs = RT_FALSE; + #endif + rt_device_register((rt_device_t)&_fsl_udc_1, "usbd", 0); + rt_usb_device_init(); + #endif + return 0; +} +INIT_DEVICE_EXPORT(rt_usbd_init); +static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam) +{ + rt_uint32_t ep_addr = (rt_uint32_t)callbackParam; + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + udcd_t udcd = RT_NULL; + uint8_t state; + if(deviceHandle->controllerId == kUSB_ControllerEhci0) + { + #ifdef RT_USING_EHCI0_AS_DEVICE + udcd = &_fsl_udc_0; + #endif + } + else + { + #ifdef RT_USING_EHCI1_AS_DEVICE + udcd = &_fsl_udc_1; + #endif + } + if(message->isSetup) + { + //rt_kprintf("1udcd:%#08X\n",udcd); + rt_usbd_ep0_setup_handler(udcd, (struct urequest*)message->buffer); + } + else if(ep_addr == 0x00) + { + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if(state == kUSB_DeviceStateAddressing) + { + if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) + { + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + //rt_kprintf("2udcd:%#08X\n",udcd); + rt_usbd_ep0_out_handler(udcd,message->length); + } + else if(ep_addr == 0x80) + { + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if(state == kUSB_DeviceStateAddressing) + { + if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) + { + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + //rt_kprintf("3udcd:%#08X\n",udcd); + rt_usbd_ep0_in_handler(udcd); + } + else if(ep_addr&0x80) + { + rt_usbd_ep_in_handler(udcd, ep_addr, message->length); + } + else + { + rt_usbd_ep_out_handler(udcd, ep_addr, message->length); + } + return kStatus_USB_Success; +} +static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam) +{ + usb_status_t error = kStatus_USB_Error; + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_device_endpoint_init_struct_t ep0_init = + { + 0x40, + 0x00, + USB_EP_ATTR_CONTROL, + 0 + }; + usb_device_endpoint_callback_struct_t ep0_callback = + { + usb_device_endpoint_callback, + 0, + 0 + }; + udcd_t udcd = RT_NULL; + if(deviceHandle->controllerId == kUSB_ControllerEhci0) + { + #ifdef RT_USING_EHCI0_AS_DEVICE + udcd = &_fsl_udc_0; + #endif + } + else + { + #ifdef RT_USING_EHCI1_AS_DEVICE + udcd = &_fsl_udc_1; + #endif + } + switch (callbackEvent) + { + case kUSB_DeviceEventBusReset: + ep0_init.endpointAddress = 0x00; + ep0_callback.callbackParam = (void *)0x00; + USB_DeviceInitEndpoint(deviceHandle,&ep0_init,&ep0_callback); + ep0_init.endpointAddress = 0x80; + ep0_callback.callbackParam = (void *)0x80; + USB_DeviceInitEndpoint(deviceHandle,&ep0_init,&ep0_callback); + rt_usbd_reset_handler(udcd); + break; + case kUSB_DeviceEventAttach: + rt_usbd_connect_handler(udcd); + break; + case kUSB_DeviceEventDetach: + rt_usbd_disconnect_handler(udcd); + break; + } + return error; +} + + + diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c new file mode 100644 index 0000000000..a8f3d2f3b2 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_phy.h" +#include +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0xFFFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) +{ + uint32_t bssReg; + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; + uint32_t instance = ENET_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI(base, srcClock_Hz, false); + + /* Initialization after PHY stars to work. */ + while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) + { + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + counter --; + } + + if (!counter) + { + return kStatus_Fail; + } + + /* Reset PHY. */ + counter = 6; + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { +#if defined(BOARD_RT1050_FIRE) + for (uint32_t i = 0x10000; i > 0; i--) + { + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg); + if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK)) + { + break; + } + } +#endif +#if defined(BOARD_RT1050_ATK) + rt_thread_delay(RT_TICK_PER_SECOND); +#endif +#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + uint32_t data = 0; + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if ( result != kStatus_Success) + { + return result; + } + result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); + if (result != kStatus_Success) + { + return result; + } +#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter --) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { +#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) + if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)) +#else + uint32_t ctlReg = 0; + PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); + if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) +#endif + { + rt_kprintf("auto negotiation complete success\n"); + break; + } + else + { + /* Wait a moment for Phy status stable. */ + __ASM("nop"); + } + } + + rt_kprintf("[PHY] wait autonegotiation complete...\n"); + rt_thread_delay(RT_TICK_PER_SECOND); + + if (!counter) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + } + + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + assert(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + if (speed == kPHY_Speed100M) + { + data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + data &= ~PHY_BCTL_LOOP_MASK; + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + assert(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ +#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg); +#endif +#if defined(BOARD_RT1050_EVK) + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); +#endif + if (result == kStatus_Success) + { + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = kPHY_FullDuplex; + } + else + { + /* Half duplex. */ + *duplex = kPHY_HalfDuplex; + } + + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = kPHY_Speed100M; + } + else + { /* 10M speed. */ + *speed = kPHY_Speed10M; + } + } + + return result; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h new file mode 100644 index 0000000000..8de59535d6 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ +#include "rtconfig.h" +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) +#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/ +#endif +#if defined(BOARD_RT1050_EVK) +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ +#endif +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ +#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ +#define PHY_BCTL_POWER_DOWN_MASK 0x800U /*!< The PHY Power Down mask. */ + + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) +#endif +#if defined(BOARD_RT1050_EVK) +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) +#endif +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the PHY status. */ +enum _phy_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_wm8960.c b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_wm8960.c new file mode 100644 index 0000000000..11c21742ec --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_wm8960.c @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_wm8960.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* + * wm8960 register cache + * We can't read the WM8960 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const uint16_t wm8960_reg[WM8960_CACHEREGNUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +static uint16_t reg_cache[WM8960_CACHEREGNUM]; +/******************************************************************************* + * Code + ******************************************************************************/ + +void WM8960_Init(wm8960_handle_t *handle, wm8960_config_t *config) +{ + uint32_t i = 4000000; + + memcpy(reg_cache, wm8960_reg, sizeof(wm8960_reg)); + + /* Set WM8960 I2C address */ + handle->xfer.slaveAddress = WM8960_I2C_ADDR; + + /* NULL pointer means default setting. */ + if (config == NULL) + { + /* + * Reset all registers + */ + WM8960_WriteReg(handle, WM8960_RESET, 0x00); + + WM8960_WriteReg(handle, WM8960_IFACE2, 0x40); + /* + * VMID=50K, Enable VREF, AINL, AINR, ADCL and ADCR + * I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5), ADC (bit 6) are powered on + */ + WM8960_WriteReg(handle, WM8960_POWER1, 0xCA); + + /* + * Enable DACL, DACR, LOUT1, ROUT1, PLL down + */ + WM8960_WriteReg(handle, WM8960_POWER2, 0x1E0); + + /* + * Enable left and right channel input PGA, left and right output mixer + */ + WM8960_WriteReg(handle, WM8960_POWER3, 0xC); + + /* Configure SYS_FS clock to 44.1kHz, MCLK_FREQ to 256*Fs, SYSCLK derived from MCLK input */ + WM8960_WriteReg(handle, WM8960_CLOCK1, 0x00); + + /* + * Audio data length = 32bit, Left justified data format + */ + WM8960_WriteReg(handle, WM8960_IFACE1, 0x0D); + + /* + * LMICBOOST = 0dB, Connect left and right PGA to left and right Input Boost Mixer + */ + WM8960_WriteReg(handle, WM8960_LINPATH, 0x18); + WM8960_WriteReg(handle, WM8960_RINPATH, 0x18); + + /* + * Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB + */ + WM8960_WriteReg(handle, WM8960_INBMIX1, 0x70); + WM8960_WriteReg(handle, WM8960_INBMIX2, 0x70); + + /* + * Left DAC and LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100); + + /* + * Right DAC and RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100); + + WM8960_WriteReg(handle, WM8960_BYPASS1, 0x0); + + WM8960_WriteReg(handle, WM8960_BYPASS2, 0x0); + + WM8960_WriteReg(handle, WM8960_MONOMIX1, 0x00); + WM8960_WriteReg(handle, WM8960_MONOMIX2, 0x00); + } + else + { + WM8960_SetDataRoute(handle, config->route); + WM8960_SetProtocol(handle, config->bus); + WM8960_SetMasterSlave(handle, config->master_slave); + } + WM8960_WriteReg(handle, WM8960_ADDCTL1, 0x0C4); + WM8960_WriteReg(handle, WM8960_ADDCTL4, 0x40); + + /* + * ADC volume, 0dB + */ + WM8960_WriteReg(handle, WM8960_LADC, 0x1F3); + WM8960_WriteReg(handle, WM8960_RADC, 0x1F3); + + /* + * Digital DAC volume, 0dB + */ + WM8960_WriteReg(handle, WM8960_LDAC, 0x1E0); + WM8960_WriteReg(handle, WM8960_RDAC, 0x1E0); + + /* + * Headphone volume, LOUT1 and ROUT1, 0dB + */ + WM8960_WriteReg(handle, WM8960_LOUT1, 0x16F); + WM8960_WriteReg(handle, WM8960_ROUT1, 0x16F); + + /* Delay for some while */ + while (i) + { + __ASM("nop"); + i--; + } + + /* Unmute DAC. */ + WM8960_WriteReg(handle, WM8960_DACCTL1, 0x0000); +} + +void WM8960_Deinit(wm8960_handle_t *handle) +{ + WM8960_SetModule(handle, kWM8960_ModuleADC, false); + WM8960_SetModule(handle, kWM8960_ModuleDAC, false); + WM8960_SetModule(handle, kWM8960_ModuleVREF, false); + WM8960_SetModule(handle, kWM8960_ModuleLineIn, false); + WM8960_SetModule(handle, kWM8960_ModuleLineOut, false); + WM8960_SetModule(handle, kWM8960_ModuleSpeaker, false); +} + +void WM8960_SetMasterSlave(wm8960_handle_t *handle, bool master) +{ + if (master == 1) + { + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS(WM8960_IFACE1_MASTER)); + } + else + { + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS(WM8960_IFACE1_SLAVE)); + } +} + +status_t WM8960_SetModule(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled) +{ + status_t ret = kStatus_Success; + switch (module) + { + case kWM8960_ModuleADC: + WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, + ((uint16_t)isEnabled << WM8960_POWER1_ADCL_SHIFT)); + WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, + ((uint16_t)isEnabled << WM8960_POWER1_ADCR_SHIFT)); + break; + case kWM8960_ModuleDAC: + WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_DACL_MASK, + ((uint16_t)isEnabled << WM8960_POWER2_DACL_SHIFT)); + WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_DACR_MASK, + ((uint16_t)isEnabled << WM8960_POWER2_DACR_SHIFT)); + break; + case kWM8960_ModuleVREF: + WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_VREF_MASK, + ((uint16_t)isEnabled << WM8960_POWER1_VREF_SHIFT)); + break; + case kWM8960_ModuleLineIn: + WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_AINL_MASK, + ((uint16_t)isEnabled << WM8960_POWER1_AINL_SHIFT)); + WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_AINR_MASK, + ((uint16_t)isEnabled << WM8960_POWER1_AINR_SHIFT)); + break; + case kWM8960_ModuleLineOut: + WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, + ((uint16_t)isEnabled << WM8960_POWER2_LOUT1_SHIFT)); + WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, + ((uint16_t)isEnabled << WM8960_POWER2_ROUT1_SHIFT)); + break; + case kWM8960_ModuleSpeaker: + WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, + ((uint16_t)isEnabled << WM8960_POWER2_SPKL_SHIFT)); + WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, + ((uint16_t)isEnabled << WM8960_POWER2_SPKR_SHIFT)); + WM8960_WriteReg(handle, WM8960_CLASSD1, 0xF7); + break; + default: + ret = kStatus_InvalidArgument; + break; + } + return ret; +} + +status_t WM8960_SetDataRoute(wm8960_handle_t *handle, wm8960_route_t route) +{ + status_t ret = kStatus_Success; + switch (route) + { + case kWM8960_RouteBypass: + /* Bypass means from line-in to HP*/ + /* + * Left LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x80); + + /* + * Right RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x80); + break; + case kWM8960_RoutePlayback: + /* Data route I2S_IN-> DAC-> HP */ + /* + * Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100); + + /* + * Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100); + break; + case kWM8960_RoutePlaybackandRecord: + /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ + /* + * Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB + */ + WM8960_WriteReg(handle, WM8960_INBMIX1, 0x50); + WM8960_WriteReg(handle, WM8960_INBMIX2, 0x50); + /* + * Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100); + + /* + * Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB + */ + WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100); + break; + case kWM8960_RoutePlaybackwithDAP: + /* I2S_IN->DAP->DAC->HP */ + break; + case kWM8960_RoutePlaybackwithDAPandRecord: + /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ + break; + case kWM8960_RouteRecord: + /* LINE_IN->ADC->I2S_OUT */ + /* + * Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB + */ + WM8960_WriteReg(handle, WM8960_INBMIX1, 0x50); + WM8960_WriteReg(handle, WM8960_INBMIX2, 0x50); + break; + default: + ret = kStatus_InvalidArgument; + break; + } + return ret; +} + +status_t WM8960_SetProtocol(wm8960_handle_t *handle, wm8960_protocol_t protocol) +{ + status_t ret = kStatus_Success; + switch (protocol) + { + case kWM8960_BusI2S: + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, + WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_I2S)); + break; + case kWM8960_BusLeftJustified: + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, + WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_LJ)); + break; + case kWM8960_BusRightJustified: + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, + WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_RJ)); + break; + case kWM8960_BusPCMA: + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, + WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_DSP)); + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP(WM8960_IFACE1_DSP_MODEA)); + break; + case kWM8960_BusPCMB: + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, + WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_DSP)); + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP(WM8960_IFACE1_DSP_MODEB)); + break; + default: + ret = kStatus_InvalidArgument; + break; + } + WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL(WM8960_IFACE1_WL_32BITS)); + return ret; +} + +status_t WM8960_SetVolume(wm8960_handle_t *handle, wm8960_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + status_t ret = kStatus_Success; + switch (module) + { + case kWM8960_ModuleADC: + vol = 0x100 | volume; + ret = WM8960_WriteReg(handle, WM8960_LADC, vol); + ret = WM8960_WriteReg(handle, WM8960_RADC, vol); + break; + case kWM8960_ModuleDAC: + vol = 0x100 | volume; + ret = WM8960_WriteReg(handle, WM8960_LDAC, vol); + ret = WM8960_WriteReg(handle, WM8960_RDAC, vol); + break; + case kWM8960_ModuleHP: + vol = 0x100 | volume; + ret = WM8960_WriteReg(handle, WM8960_LOUT1, vol); + ret = WM8960_WriteReg(handle, WM8960_ROUT1, vol); + break; + case kWM8960_ModuleLineIn: + vol = 0x100 | volume; + ret = WM8960_WriteReg(handle, WM8960_LINVOL, vol); + ret = WM8960_WriteReg(handle, WM8960_RINVOL, vol); + break; + case kWM8960_ModuleSpeaker: + vol = 0x100 | volume; + ret = WM8960_WriteReg(handle, WM8960_LOUT2, vol); + ret = WM8960_WriteReg(handle, WM8960_ROUT2, vol); + break; + default: + ret = kStatus_InvalidArgument; + break; + } + return ret; +} + +uint32_t WM8960_GetVolume(wm8960_handle_t *handle, wm8960_module_t module) +{ + uint16_t vol = 0; + switch (module) + { + case kWM8960_ModuleADC: + WM8960_ReadReg(WM8960_LADC, &vol); + vol &= 0xFF; + break; + case kWM8960_ModuleDAC: + WM8960_ReadReg(WM8960_LDAC, &vol); + vol &= 0xFF; + break; + case kWM8960_ModuleHP: + WM8960_ReadReg(WM8960_LOUT1, &vol); + vol &= 0x7F; + break; + case kWM8960_ModuleLineOut: + WM8960_ReadReg(WM8960_LINVOL, &vol); + vol &= 0x3F; + break; + default: + vol = 0; + break; + } + return vol; +} + +status_t WM8960_SetMute(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled) +{ + status_t ret = kStatus_Success; + switch (module) + { + case kWM8960_ModuleADC: + /* + * Digital Mute + */ + if (isEnabled) + { + ret = WM8960_WriteReg(handle, WM8960_LADC, 0x100); + ret = WM8960_WriteReg(handle, WM8960_RADC, 0x100); + } + else + { + ret = WM8960_WriteReg(handle, WM8960_LADC, 0x1C3); + ret = WM8960_WriteReg(handle, WM8960_RADC, 0x1C3); + } + break; + case kWM8960_ModuleDAC: + /* + * Digital mute + */ + if (isEnabled) + { + ret = WM8960_WriteReg(handle, WM8960_LDAC, 0x100); + ret = WM8960_WriteReg(handle, WM8960_RDAC, 0x100); + } + else + { + ret = WM8960_WriteReg(handle, WM8960_LDAC, 0x1FF); + ret = WM8960_WriteReg(handle, WM8960_RDAC, 0x1FF); + } + break; + case kWM8960_ModuleHP: + /* + * Analog mute + */ + if (isEnabled) + { + ret = WM8960_WriteReg(handle, WM8960_LOUT1, 0x100); + ret = WM8960_WriteReg(handle, WM8960_ROUT1, 0x100); + } + else + { + ret = WM8960_WriteReg(handle, WM8960_LOUT1, 0x179); + ret = WM8960_WriteReg(handle, WM8960_ROUT1, 0x179); + } + break; + case kWM8960_ModuleLineOut: + break; + default: + ret = kStatus_InvalidArgument; + break; + } + return ret; +} + +status_t WM8960_ConfigDataFormat(wm8960_handle_t *handle, uint32_t mclk, uint32_t sample_rate, uint8_t bits) +{ + status_t retval = kStatus_Success; + + switch (sample_rate) + { + case 8000: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x1B0); + break; + case 11025: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); + break; + case 12000: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x120); + break; + case 16000: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); + break; + case 22050: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); + break; + case 24000: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x90); + break; + case 32000: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x48); + break; + case 44100: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); + break; + case 48000: + retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x00); + break; + default: + retval = kStatus_InvalidArgument; + break; + } + + /* + * Slave mode (MS = 0), LRP = 0, 32bit WL, left justified (FORMAT[1:0]=0b01) + */ + switch (bits) + { + case 16: + retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, + WM8960_IFACE1_WL(WM8960_IFACE1_WL_16BITS)); + break; + case 20: + retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, + WM8960_IFACE1_WL(WM8960_IFACE1_WL_20BITS)); + break; + case 24: + retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, + WM8960_IFACE1_WL(WM8960_IFACE1_WL_24BITS)); + break; + case 32: + retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, + WM8960_IFACE1_WL(WM8960_IFACE1_WL_32BITS)); + break; + default: + retval = kStatus_InvalidArgument; + break; + } + + return retval; +} + +status_t WM8960_SetJackDetect(wm8960_handle_t *handle, bool isEnabled) +{ + uint8_t retval = 0; + uint16_t val = 0; + + WM8960_ReadReg(WM8960_ADDCTL2, &val); + + if (isEnabled) + { + val |= 0x40U; + } + else + { + val &= 0xCF; + } + + retval = WM8960_WriteReg(handle, WM8960_ADDCTL2, val); + + return retval; +} + +status_t WM8960_WriteReg(wm8960_handle_t *handle, uint8_t reg, uint16_t val) +{ + uint8_t cmd, buff; + uint8_t retval = 0; + + /* The register address */ + cmd = (reg << 1) | ((val >> 8U) & 0x0001U); + /* Data */ + buff = val & 0xFF; + + /* Copy data to cache */ + reg_cache[reg] = val; + +#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT) + uint8_t data[2]; + data[0] = cmd; + data[1] = buff; + retval = LPI2C_MasterStart(handle->base, WM8960_I2C_ADDR, kLPI2C_Write); + retval = LPI2C_MasterSend(handle->base, data, 2); + retval = LPI2C_MasterStop(handle->base); +#else + /* Config the I2C xfer */ + handle->xfer.direction = kI2C_Write; + handle->xfer.subaddress = cmd; + handle->xfer.subaddressSize = 1U; + handle->xfer.data = &buff; + handle->xfer.dataSize = 1U; + + retval = I2C_MasterTransferBlocking(handle->base, &handle->xfer); +#endif + + if (retval != kStatus_Success) + { + return kStatus_Fail; + } + return kStatus_Success; +} + +status_t WM8960_ReadReg(uint8_t reg, uint16_t *val) +{ + if (reg >= WM8960_CACHEREGNUM) + { + return kStatus_InvalidArgument; + } + + *val = reg_cache[reg]; + + return kStatus_Success; +} + +status_t WM8960_ModifyReg(wm8960_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t val) +{ + uint8_t retval = 0; + uint16_t reg_val = 0; + retval = WM8960_ReadReg(reg, ®_val); + if (retval != kStatus_Success) + { + return kStatus_Fail; + } + reg_val &= (uint16_t)~mask; + reg_val |= val; + retval = WM8960_WriteReg(handle, reg, reg_val); + if (retval != kStatus_Success) + { + return kStatus_Fail; + } + return kStatus_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_wm8960.h b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_wm8960.h new file mode 100644 index 0000000000..848e0332f9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_wm8960.h @@ -0,0 +1,426 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_WM8960_H_ +#define _FSL_WM8960_H_ + +#include "fsl_common.h" +#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT) +#include "fsl_lpi2c.h" +#else +#include "fsl_i2c.h" +#endif + +/*! + * @addtogroup wm8960 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define the register address of WM8960. */ +#define WM8960_LINVOL 0x0 +#define WM8960_RINVOL 0x1 +#define WM8960_LOUT1 0x2 +#define WM8960_ROUT1 0x3 +#define WM8960_CLOCK1 0x4 +#define WM8960_DACCTL1 0x5 +#define WM8960_DACCTL2 0x6 +#define WM8960_IFACE1 0x7 +#define WM8960_CLOCK2 0x8 +#define WM8960_IFACE2 0x9 +#define WM8960_LDAC 0xa +#define WM8960_RDAC 0xb + +#define WM8960_RESET 0xf +#define WM8960_3D 0x10 +#define WM8960_ALC1 0x11 +#define WM8960_ALC2 0x12 +#define WM8960_ALC3 0x13 +#define WM8960_NOISEG 0x14 +#define WM8960_LADC 0x15 +#define WM8960_RADC 0x16 +#define WM8960_ADDCTL1 0x17 +#define WM8960_ADDCTL2 0x18 +#define WM8960_POWER1 0x19 +#define WM8960_POWER2 0x1a +#define WM8960_ADDCTL3 0x1b +#define WM8960_APOP1 0x1c +#define WM8960_APOP2 0x1d + +#define WM8960_LINPATH 0x20 +#define WM8960_RINPATH 0x21 +#define WM8960_LOUTMIX 0x22 + +#define WM8960_ROUTMIX 0x25 +#define WM8960_MONOMIX1 0x26 +#define WM8960_MONOMIX2 0x27 +#define WM8960_LOUT2 0x28 +#define WM8960_ROUT2 0x29 +#define WM8960_MONO 0x2a +#define WM8960_INBMIX1 0x2b +#define WM8960_INBMIX2 0x2c +#define WM8960_BYPASS1 0x2d +#define WM8960_BYPASS2 0x2e +#define WM8960_POWER3 0x2f +#define WM8960_ADDCTL4 0x30 +#define WM8960_CLASSD1 0x31 + +#define WM8960_CLASSD3 0x33 +#define WM8960_PLL1 0x34 +#define WM8960_PLL2 0x35 +#define WM8960_PLL3 0x36 +#define WM8960_PLL4 0x37 + +/*! @brief Cache register number */ +#define WM8960_CACHEREGNUM 56 + +/*! @brief WM8960_IFACE1 FORMAT bits */ +#define WM8960_IFACE1_FORMAT_MASK 0x03 +#define WM8960_IFACE1_FORMAT_SHIFT 0x00 +#define WM8960_IFACE1_FORMAT_RJ 0x00 +#define WM8960_IFACE1_FORMAT_LJ 0x01 +#define WM8960_IFACE1_FORMAT_I2S 0x02 +#define WM8960_IFACE1_FORMAT_DSP 0x03 +#define WM8960_IFACE1_FORMAT(x) ((x << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) + +/*! @brief WM8960_IFACE1 WL bits */ +#define WM8960_IFACE1_WL_MASK 0x0C +#define WM8960_IFACE1_WL_SHIFT 0x02 +#define WM8960_IFACE1_WL_16BITS 0x00 +#define WM8960_IFACE1_WL_20BITS 0x01 +#define WM8960_IFACE1_WL_24BITS 0x02 +#define WM8960_IFACE1_WL_32BITS 0x03 +#define WM8960_IFACE1_WL(x) ((x << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) + +/*! @brief WM8960_IFACE1 LRP bit */ +#define WM8960_IFACE1_LRP_MASK 0x10 +#define WM8960_IFACE1_LRP_SHIFT 0x04 +#define WM8960_IFACE1_LRCLK_NORMAL_POL 0x00 +#define WM8960_IFACE1_LRCLK_INVERT_POL 0x01 +#define WM8960_IFACE1_DSP_MODEA 0x00 +#define WM8960_IFACE1_DSP_MODEB 0x01 +#define WM8960_IFACE1_LRP(x) ((x << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) + +/*! @brief WM8960_IFACE1 DLRSWAP bit */ +#define WM8960_IFACE1_DLRSWAP_MASK 0x20 +#define WM8960_IFACE1_DLRSWAP_SHIFT 0x05 +#define WM8960_IFACE1_DACCH_NORMAL 0x00 +#define WM8960_IFACE1_DACCH_SWAP 0x01 +#define WM8960_IFACE1_DLRSWAP(x) ((x << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) + +/*! @brief WM8960_IFACE1 MS bit */ +#define WM8960_IFACE1_MS_MASK 0x40 +#define WM8960_IFACE1_MS_SHIFT 0x06 +#define WM8960_IFACE1_SLAVE 0x00 +#define WM8960_IFACE1_MASTER 0x01 +#define WM8960_IFACE1_MS(x) ((x << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) + +/*! @brief WM8960_IFACE1 BCLKINV bit */ +#define WM8960_IFACE1_BCLKINV_MASK 0x80 +#define WM8960_IFACE1_BCLKINV_SHIFT 0x07 +#define WM8960_IFACE1_BCLK_NONINVERT 0x00 +#define WM8960_IFACE1_BCLK_INVERT 0x01 +#define WM8960_IFACE1_BCLKINV(x) ((x << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) + +/*! @brief WM8960_IFACE1 ALRSWAP bit */ +#define WM8960_IFACE1_ALRSWAP_MASK 0x100 +#define WM8960_IFACE1_ALRSWAP_SHIFT 0x08 +#define WM8960_IFACE1_ADCCH_NORMAL 0x00 +#define WM8960_IFACE1_ADCCH_SWAP 0x01 +#define WM8960_IFACE1_ALRSWAP(x) ((x << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) + +/*! @brief WM8960_POWER1 */ +#define WM8960_POWER1_VREF_MASK 0x40 +#define WM8960_POWER1_VREF_SHIFT 0x06 + +#define WM8960_POWER1_AINL_MASK 0x20 +#define WM8960_POWER1_AINL_SHIFT 0x05 + +#define WM8960_POWER1_AINR_MASK 0x10 +#define WM8960_POWER1_AINR_SHIFT 0x04 + +#define WM8960_POWER1_ADCL_MASK 0x08 +#define WM8960_POWER1_ADCL_SHIFT 0x03 + +#define WM8960_POWER1_ADCR_MASK 0x04 +#define WM8960_POWER1_ADCR_SHIFT 0x02 + +/*! @brief WM8960_POWER2 */ +#define WM8960_POWER2_DACL_MASK 0x100 +#define WM8960_POWER2_DACL_SHIFT 0x08 + +#define WM8960_POWER2_DACR_MASK 0x80 +#define WM8960_POWER2_DACR_SHIFT 0x07 + +#define WM8960_POWER2_LOUT1_MASK 0x40 +#define WM8960_POWER2_LOUT1_SHIFT 0x06 + +#define WM8960_POWER2_ROUT1_MASK 0x20 +#define WM8960_POWER2_ROUT1_SHIFT 0x05 + +#define WM8960_POWER2_SPKL_MASK 0x10 +#define WM8960_POWER2_SPKL_SHIFT 0x04 + +#define WM8960_POWER2_SPKR_MASK 0x08 +#define WM8960_POWER2_SPKR_SHIFT 0x03 + +/*! @brief WM8960 I2C address. */ +#define WM8960_I2C_ADDR 0x1A + +/*! @brief Modules in WM8960 board. */ +typedef enum _WM8960_module +{ + kWM8960_ModuleADC = 0x0, /*!< ADC module in WM8960 */ + kWM8960_ModuleDAC = 0x1, /*!< DAC module in WM8960 */ + kWM8960_ModuleVREF = 0x2, /*!< VREF module */ + kWM8960_ModuleHP = 0x03, /*!< Headphone module */ + kWM8960_ModuleLineIn = 0x6, /*!< Line-in module */ + kWM8960_ModuleLineOut = 0x7, /*!< Line out module */ + kWM8960_ModuleSpeaker = 0x8 /*!< Speaker module */ +} wm8960_module_t; + +/*! +* @brief WM8960 data route. +* Only provide some typical data route, not all route listed. +* Note: Users cannot combine any routes, once a new route is set, the previous one would be replaced. +*/ +typedef enum _wm8960_route +{ + kWM8960_RouteBypass = 0x0, /*!< LINEIN->Headphone. */ + kWM8960_RoutePlayback = 0x1, /*!< I2SIN->DAC->Headphone. */ + kWM8960_RoutePlaybackandRecord = 0x2, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ + kWM8960_RoutePlaybackwithDAP = 0x3, /*!< I2SIN->DAP->DAC->Headphone. */ + kWM8960_RoutePlaybackwithDAPandRecord = 0x4, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */ + kWM8960_RouteRecord = 0x5 /*!< LINEIN->ADC->I2SOUT. */ +} wm8960_route_t; + +/*! +* @brief The audio data transfer protocol choice. +* WM8960 only supports I2S format and PCM format. +*/ +typedef enum _wm8960_protocol +{ + kWM8960_BusI2S = 0x0, /*!< I2S type */ + kWM8960_BusLeftJustified = 0x1, /*!< Left justified mode */ + kWM8960_BusRightJustified = 0x2, /*!< Right justified mode */ + kWM8960_BusPCMA = 0x3, /*!< PCM A mode */ + kWM8960_BusPCMB = 0x4 /*!< PCM B mode */ +} wm8960_protocol_t; + +/*! @brief WM8960 configure definition. */ +typedef struct wm8960_handle +{ +#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT) + LPI2C_Type *base; + lpi2c_master_transfer_t xfer; + lpi2c_master_handle_t *i2cHandle; +#else + /* I2C relevant definition. */ + I2C_Type *base; /*!< I2C instance. */ + i2c_master_transfer_t xfer; /*!< I2C device setting */ + i2c_master_handle_t *i2cHandle; /*!< I2C internal state space. */ +#endif +} wm8960_handle_t; + +/*! @brief Initialize structure of WM8960 */ +typedef struct wm8960_config +{ + wm8960_route_t route; /*!< Audio data route.*/ + wm8960_protocol_t bus; /*!< Audio transfer protocol */ + bool master_slave; /*!< Master or slave. */ +} wm8960_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief WM8960 initialize function. + * + * The second parameter is NULL to WM8960 in this version. If users want + * to change the settings, they have to use wm8960_write_reg() or wm8960_modify_reg() + * to set the register value of WM8960. + * Note: If the codec_config is NULL, it would initialize WM8960 using default settings. + * The default setting: + * codec_config->route = kWM8960_RoutePlaybackandRecord + * codec_config->bus = kWM8960_BusI2S + * codec_config->master = slave + * + * @param handle WM8960 handle structure. + * @param codec_config WM8960 configuration structure. + */ +void WM8960_Init(wm8960_handle_t *handle, wm8960_config_t *config); + +/*! + * @brief Deinit the WM8960 codec. + * + * This function close all modules in WM8960 to save power. + * + * @param handle WM8960 handle structure pointer. + */ +void WM8960_Deinit(wm8960_handle_t *handle); + +/*! + * @brief Set audio data route in WM8960. + * + * This function would set the data route according to route. The route cannot be combined, + * as all route would enable different modules. + * Note: If a new route is set, the previous route would not work. + * + * @param handle WM8960 handle structure. + * @param route Audio data route in WM8960. + */ +status_t WM8960_SetDataRoute(wm8960_handle_t *handle, wm8960_route_t route); + +/*! + * @brief Set the audio transfer protocol. + * + * WM8960 only supports I2S, left justified, right justified, PCM A, PCM B format. + * + * @param handle WM8960 handle structure. + * @param bus Audio data transfer protocol. + */ +status_t WM8960_SetProtocol(wm8960_handle_t *handle, wm8960_protocol_t protocol); + +/*! + * @brief Set WM8960 as master or slave. + * + * @param handle WM8960 handle structure. + * @param master 1 represent master, 0 represent slave. + */ +void WM8960_SetMasterSlave(wm8960_handle_t *handle, bool master); + +/*! + * @brief Set the volume of different modules in WM8960. + * + * This function would set the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * @param handle WM8960 handle structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @param volume Volume value need to be set. + */ +status_t WM8960_SetVolume(wm8960_handle_t *handle, wm8960_module_t module, uint32_t volume); + +/*! + * @brief Get the volume of different modules in WM8960. + * + * This function gets the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * @param handle WM8960 handle structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @return Volume value of the module. + */ +uint32_t WM8960_GetVolume(wm8960_handle_t *handle, wm8960_module_t module); + +/*! + * @brief Mute modules in WM8960. + * + * @param handle WM8960 handle structure. + * @param module Modules need to be mute. + * @param isEnabled Mute or unmute, 1 represent mute. + */ +status_t WM8960_SetMute(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled); + +/*! + * @brief Enable/disable expected devices. + * + * @param handle WM8960 handle structure. + * @param module Module expected to enable. + * @param isEnabled Enable or disable moudles. + */ +status_t WM8960_SetModule(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled); + +/*! + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * + * @param handle WM8960 handle structure pointer. + * @param mclk Master clock frequency of I2S. + * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +status_t WM8960_ConfigDataFormat(wm8960_handle_t *handle, uint32_t mclk, uint32_t sample_rate, uint8_t bits); + +/*! + * @brief Enable/disable jack detect feature. + * + * @param handle WM8960 handle structure. + * @param isEnabled Enable or disable moudles. + */ +status_t WM8960_SetJackDetect(wm8960_handle_t *handle, bool isEnabled); + +/*! + * @brief Write register to WM8960 using I2C. + * + * @param handle WM8960 handle structure. + * @param reg The register address in WM8960. + * @param val Value needs to write into the register. + */ +status_t WM8960_WriteReg(wm8960_handle_t *handle, uint8_t reg, uint16_t val); + +/*! + * @brief Read register from WM8960 using I2C. + * @param handle WM8960 handle structure. + * @param reg The register address in WM8960. + * @param val Value written to. + */ +status_t WM8960_ReadReg(uint8_t reg, uint16_t *val); + +/*! + * @brief Modify some bits in the register using I2C. + * @param handle WM8960 handle structure. + * @param reg The register address in WM8960. + * @param mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +status_t WM8960_ModifyReg(wm8960_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t val); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_WM8960_H_ */ + +/******************************************************************************* + * API + ******************************************************************************/ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch.c b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch.c new file mode 100644 index 0000000000..721752ef4c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + * 2018-10-29 XY + */ +#include "drv_touch.h" + + +#define TOUCH_I2C_NAME "i2c1" + +#ifndef TOUCH_SAMPLE_HZ +#define TOUCH_SAMPLE_HZ (50) +#endif + +#ifndef TOUCH_I2C_NAME +#error "Please define touch i2c name!" +#endif + +#ifdef PKG_USING_GUIENGINE +#include +#include +#endif + +#if 0 +#define TPDEBUG rt_kprintf +#else +#define TPDEBUG(...) +#endif + +static rt_slist_t _driver_list; +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; + +static void post_down_event(rt_uint16_t x, rt_uint16_t y, rt_uint32_t id) +{ +#ifdef PKG_USING_GUIENGINE + rt_err_t result; + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; + emouse.x = x; + emouse.y = y; + emouse.ts = rt_tick_get(); + emouse.id = id; + + do + { + result = rtgui_server_post_event(&emouse.parent, sizeof(emouse)); + if (result != RT_EOK) + { + rt_thread_delay(RT_TICK_PER_SECOND / TOUCH_SAMPLE_HZ); + } + } + while (result != RT_EOK); + + TPDEBUG("[TP] touch down [%d, %d]\n", emouse.x, emouse.y); +#endif +} + +static void post_motion_event(rt_uint16_t x, rt_uint16_t y, rt_uint32_t id) +{ +#ifdef PKG_USING_GUIENGINE + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; + emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; + emouse.x = x; + emouse.y = y; + emouse.ts = rt_tick_get(); + emouse.id = id; + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); + TPDEBUG("[TP] touch motion [%d, %d]\n", emouse.x, emouse.y); +#endif +} + +static void post_up_event(rt_uint16_t x, rt_uint16_t y, rt_uint32_t id) +{ +#ifdef PKG_USING_GUIENGINE + rt_err_t result; + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP; + emouse.x = x; + emouse.y = y; + emouse.ts = rt_tick_get(); + emouse.id = id; + + do + { + result = rtgui_server_post_event(&emouse.parent, sizeof(emouse)); + if (result != RT_EOK) + { + rt_thread_delay(RT_TICK_PER_SECOND / TOUCH_SAMPLE_HZ); + } + } + while (result != RT_EOK); + + TPDEBUG("[TP] touch up [%d, %d]\n", emouse.x, emouse.y); +#endif +} + +static void touch_run(void* parameter) +{ + rt_tick_t emouse_id = 0; + struct touch_message msg; + rt_slist_t *driver_list = NULL; + struct touch_driver *current_driver = RT_NULL; + + i2c_bus = rt_i2c_bus_device_find(TOUCH_I2C_NAME); + RT_ASSERT(i2c_bus); + + if(rt_device_open(&i2c_bus->parent, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + return; + } + + rt_slist_for_each(driver_list, &_driver_list) + { + current_driver = (struct touch_driver *)driver_list; + if(current_driver->probe(i2c_bus) == RT_TRUE) + { + break; + } + current_driver = RT_NULL; + } + + if(current_driver == RT_NULL) + { + rt_kprintf("[TP] No touch pad or driver.\n"); + rt_device_close((rt_device_t)i2c_bus); + + return; + } + + current_driver->ops->init(i2c_bus); + + while (1) + { + if (rt_sem_take(current_driver->isr_sem, RT_WAITING_FOREVER) != RT_EOK) + { + continue; + } + + if (current_driver->ops->read_point(&msg) != RT_EOK) + { + continue; + } + + switch (msg.event) + { + case TOUCH_EVENT_MOVE: + post_motion_event(msg.x, msg.y, emouse_id); + break; + + case TOUCH_EVENT_DOWN: + emouse_id = rt_tick_get(); + post_down_event(msg.x, msg.y, emouse_id); + break; + + case TOUCH_EVENT_UP: + post_up_event(msg.x, msg.y, emouse_id); + break; + + default: + break; + } + + rt_thread_delay(RT_TICK_PER_SECOND / TOUCH_SAMPLE_HZ); + } +} + +rt_err_t rt_touch_drivers_register(touch_driver_t drv) +{ + RT_ASSERT(drv != RT_NULL); + RT_ASSERT(drv->ops != RT_NULL); + RT_ASSERT(drv->probe != RT_NULL); + + rt_slist_append(&_driver_list, &drv->list); + + return RT_EOK; +} + +static int rt_touch_list_init(void) +{ + rt_slist_init(&_driver_list); + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_touch_list_init); + +static int rt_touch_init(void) +{ + rt_thread_t thread = RT_NULL; + + thread = rt_thread_create("touch", touch_run, RT_NULL, 2048, 28, 20); + if(thread) + { + return rt_thread_startup(thread); + } + + return RT_ERROR; +} +INIT_APP_EXPORT(rt_touch_init); + +int rt_touch_read(rt_uint16_t addr, void *cmd_buf, size_t cmd_len, void *data_buf, size_t data_len) +{ + struct rt_i2c_msg msgs[2]; + + msgs[0].addr = addr; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = cmd_buf; + msgs[0].len = cmd_len; + + msgs[1].addr = addr; + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = data_buf; + msgs[1].len = data_len; + + if (rt_i2c_transfer(i2c_bus, msgs, 2) == 2) + return 0; + else + return -1; +} + +int rt_touch_write(rt_uint16_t addr, void *data_buf, size_t data_len) +{ + struct rt_i2c_msg msgs[1]; + + msgs[0].addr = addr; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = data_buf; + msgs[0].len = data_len; + + if (rt_i2c_transfer(i2c_bus, msgs, 1) == 1) + return 0; + else + return -1; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch.h b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch.h new file mode 100644 index 0000000000..b12b19d606 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + * 2018-10-29 XY + */ +#ifndef __DRV_TOUCH_H__ +#define __DRV_TOUCH_H__ + +#include "rtthread.h" +#include "rtdevice.h" + +#define TOUCH_EVENT_UP (0x01) +#define TOUCH_EVENT_DOWN (0x02) +#define TOUCH_EVENT_MOVE (0x03) +#define TOUCH_EVENT_NONE (0x80) + +struct touch_message +{ + rt_uint16_t x; + rt_uint16_t y; + rt_uint8_t event; +}; +typedef struct touch_message *touch_message_t; + +struct touch_ops +{ + void (*init)(struct rt_i2c_bus_device *); + void (*deinit)(void); + rt_err_t (*read_point)(touch_message_t); +}; +typedef struct touch_ops *touch_ops_t; + +struct touch_driver +{ + rt_slist_t list; + rt_bool_t (*probe)(struct rt_i2c_bus_device *i2c_bus); + rt_sem_t isr_sem; + touch_ops_t ops; + void *user_data; +}; +typedef struct touch_driver *touch_driver_t; + +rt_err_t rt_touch_drivers_register(touch_driver_t drv); + +int rt_touch_read(rt_uint16_t addr, void *cmd_buf, size_t cmd_len, void *data_buf, size_t data_len); +int rt_touch_write(rt_uint16_t addr, void *data_buf, size_t data_len); + +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch_ft5x06.c b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch_ft5x06.c new file mode 100644 index 0000000000..bbe71b3b1c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch_ft5x06.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-08 Yang the first version + * 2018-10-29 XY + */ + +#include +#include +#include +#include "drv_touch.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" + + +#define TP_INT_PIN 54 /* GPIO_AD_B0_11 */ +#define TP_RST_PIN 45 /* GPIO_AD_B0_02 */ + +#define FT5x06_TS_ADDR (0x38) + +#if 0 +#define TPDEBUG rt_kprintf +#else +#define TPDEBUG(...) +#endif + +static struct touch_driver ft5x06_driver; + +typedef enum _touch_event +{ + kTouch_Down = 0, /*!< The state changed to touched. */ + kTouch_Up = 1, /*!< The state changed to not touched. */ + kTouch_Contact = 2, /*!< There is a continuous touch being detected. */ + kTouch_Reserved = 3 /*!< No touch information available. */ +} touch_event_t; + +typedef struct _touch_point +{ + touch_event_t TOUCH_EVENT; /*!< Indicates the state or event of the touch point. */ + uint8_t TOUCH_ID; /*!< Id of the touch point. This numeric value stays constant between down and up event. */ + uint16_t TOUCH_X; /*!< X coordinate of the touch point */ + uint16_t TOUCH_Y; /*!< Y coordinate of the touch point */ +} touch_point_t; + +typedef struct _ft5406_touch_point +{ + uint8_t XH; + uint8_t XL; + uint8_t YH; + uint8_t YL; + uint8_t RESERVED[2]; +} ft5406_touch_point_t; + +typedef struct _ft5406_touch_data +{ + uint8_t DEVIDE_MODE; + uint8_t GEST_ID; + uint8_t TD_STATUS; + ft5406_touch_point_t TOUCH; +} ft5406_touch_data_t; + +#define TOUCH_POINT_GET_EVENT(T) ((touch_event_t)((T).XH >> 6)) +#define TOUCH_POINT_GET_ID(T) ((T).YH >> 4) +#define TOUCH_POINT_GET_X(T) ((((T).XH & 0x0f) << 8) | (T).XL) +#define TOUCH_POINT_GET_Y(T) ((((T).YH & 0x0f) << 8) | (T).YL) + +static int ft5406_read_touch(touch_point_t *dp) +{ + rt_uint8_t cmd = 0; + ft5406_touch_data_t touch_data; + + if (rt_touch_read(FT5x06_TS_ADDR, &cmd, 1, &touch_data, sizeof(ft5406_touch_data_t)) != 0) + return -1; + + dp->TOUCH_X = TOUCH_POINT_GET_Y(touch_data.TOUCH); + dp->TOUCH_Y = TOUCH_POINT_GET_X(touch_data.TOUCH); + dp->TOUCH_EVENT = TOUCH_POINT_GET_EVENT(touch_data.TOUCH); + dp->TOUCH_ID = TOUCH_POINT_GET_ID(touch_data.TOUCH); + + if (dp->TOUCH_EVENT == 3) return -1; + + if (touch_data.TD_STATUS != 0) + return 0; + else + return -1; +} + +static void ft5x06_isr_enable(rt_bool_t enable) +{ + if(enable == RT_TRUE) + { + rt_pin_irq_enable(TP_INT_PIN, PIN_IRQ_ENABLE); + } + else + { + rt_pin_irq_enable(TP_INT_PIN, PIN_IRQ_DISABLE); + } +} + +static void ft5x06_touch_isr(void *parameter) +{ + TPDEBUG("[TP] ft5x06_touch_isr\n"); + + ft5x06_isr_enable(RT_FALSE); + rt_sem_release(ft5x06_driver.isr_sem); +} + +static rt_err_t ft5x06_read_point(touch_message_t msg) +{ + touch_point_t dp; + + if (ft5406_read_touch(&dp) != 0) + { + msg->event = TOUCH_EVENT_UP; + } + else + { + if (dp.TOUCH_EVENT == kTouch_Up) + { + msg->event = TOUCH_EVENT_UP; + } + else if (dp.TOUCH_EVENT == kTouch_Down) + { + msg->event = TOUCH_EVENT_DOWN; + } + else if (dp.TOUCH_EVENT == kTouch_Contact) + { + msg->event = TOUCH_EVENT_MOVE; + } + else + { + msg->event = TOUCH_EVENT_UP; + } + } + + msg->x = dp.TOUCH_X; + msg->y = dp.TOUCH_Y; + + TPDEBUG("[TP] [%d, %d] %s\n", msg->x, msg->y, + msg->event == TOUCH_EVENT_DOWN ? "DOWN" : (msg->event == TOUCH_EVENT_MOVE ? "MOVE" : (msg->event == TOUCH_EVENT_UP ? "UP" : "NONE"))); + + if (msg->event != TOUCH_EVENT_UP) + { + rt_sem_release(ft5x06_driver.isr_sem); + } + else + { + ft5x06_isr_enable(RT_TRUE); + } + + return RT_EOK; +} + +static void ft5x06_init(struct rt_i2c_bus_device *i2c_bus) +{ + ft5x06_driver.isr_sem = rt_sem_create("ft5x06", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(ft5x06_driver.isr_sem); + + rt_pin_attach_irq(TP_INT_PIN, PIN_IRQ_MODE_LOW_LEVEL, ft5x06_touch_isr, &ft5x06_driver); + rt_pin_irq_enable(TP_INT_PIN, PIN_IRQ_ENABLE); + rt_thread_delay(RT_TICK_PER_SECOND / 5); +} + +static void ft5x06_deinit(void) +{ + if (ft5x06_driver.isr_sem) + { + rt_sem_delete(ft5x06_driver.isr_sem); + ft5x06_driver.isr_sem = RT_NULL; + } +} + +struct touch_ops ft5x06_ops = +{ + ft5x06_init, + ft5x06_deinit, + ft5x06_read_point, +}; + +static void ft5406_hw_reset(void) +{ + gpio_pin_config_t pin_config = + { + kGPIO_DigitalOutput, 0, + }; + + CLOCK_EnableClock(kCLOCK_Gpio1); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0x10B0u); + + /* Enable touch panel controller */ + GPIO_PinInit(GPIO1, 2, &pin_config); + GPIO_WritePinOutput(GPIO1, 2, 1); + rt_thread_delay(RT_TICK_PER_SECOND / 20); + GPIO_WritePinOutput(GPIO1, 2, 0); + rt_thread_delay(RT_TICK_PER_SECOND / 20); + GPIO_WritePinOutput(GPIO1, 2, 1); +} + +static rt_bool_t ft5x06_probe(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint16_t cmd = 0x000c; + rt_uint16_t tmp[2]; + rt_uint16_t CurVersion; + + ft5406_hw_reset(); + + if (rt_touch_read(FT5x06_TS_ADDR, &cmd, 2, tmp, 2) != 0) + { + TPDEBUG("[TP] %s failed!\n", __func__); + return RT_FALSE; + } + + CurVersion = (tmp[0]<<8) | tmp[1]; + rt_kprintf("[TP] FT5X06 Touch Version : %d\n", CurVersion); + + return RT_TRUE; +} + +int ft5x06_driver_register(void) +{ + ft5x06_driver.probe = ft5x06_probe; + ft5x06_driver.ops = &ft5x06_ops; + ft5x06_driver.user_data = RT_NULL; + + rt_touch_drivers_register(&ft5x06_driver); + + return 0; +} +INIT_ENV_EXPORT(ft5x06_driver_register); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch_gt9xx.c b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch_gt9xx.c new file mode 100644 index 0000000000..15fb73b119 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/touch/drv_touch_gt9xx.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + * 2018-04-03 XY gt9xx for 1024 * 600 + * 2018-04-14 liu2guang optimize int and rst to pin framework + * 2018-10-29 XY + */ + +#include "drv_touch.h" +#include "string.h" +#include "drv_pin.h" + + +#define TP_INT_PIN 54 /* GPIO_AD_B0_11 */ +#define TP_RST_PIN 45 /* GPIO_AD_B0_02 */ + +#ifndef TP_INT_PIN +#error "Please config touch panel INT pin." +#endif +#ifndef TP_RST_PIN +#error "Please config touch panel RST pin." +#endif + +#ifndef IIC_RETRY_NUM +#define IIC_RETRY_NUM 2 +#endif + +#define GT9xx_TS_ADDR (0x5D) + +#define gt9xx_READ_XY_REG (0x814E) /* 坐标寄存器 */ +#define gt9xx_CLEARBUF_REG (0x814E) /* 清除坐标寄存器 */ +#define gt9xx_CONFIG_REG (0x8047) /* 配置参数寄存器 */ +#define gt9xx_COMMAND_REG (0x8040) /* 实时命令 */ +#define gt9xx_PRODUCT_ID_REG (0x8140) /* 产品ID */ +#define gt9xx_VENDOR_ID_REG (0x814A) /* 当前模组选项信息 */ +#define gt9xx_CONFIG_VERSION_REG (0x8047) /* 配置文件版本号 */ +#define gt9xx_CONFIG_CHECKSUM_REG (0x80FF) /* 配置文件校验码 */ +#define gt9xx_FIRMWARE_VERSION_REG (0x8144) /* 固件版本号 */ + +#if 0 +#define TPDEBUG rt_kprintf +#else +#define TPDEBUG(...) +#endif + +static struct touch_driver gt9xx_driver; + +static void gt9xx_hw_reset(rt_uint8_t address) +{ + rt_pin_mode(TP_INT_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(TP_RST_PIN, PIN_MODE_OUTPUT); + + if(address == 0x5D) + { + rt_pin_write(TP_INT_PIN, PIN_LOW); + rt_pin_write(TP_RST_PIN, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND / 50); + + rt_pin_write(TP_RST_PIN, PIN_HIGH); + rt_pin_write(TP_INT_PIN, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND / 50); + } + else + { + rt_pin_write(TP_INT_PIN, PIN_LOW); + rt_pin_write(TP_RST_PIN, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND / 50); + + rt_pin_write(TP_RST_PIN, PIN_LOW); + rt_pin_write(TP_INT_PIN, PIN_HIGH); + rt_thread_delay(RT_TICK_PER_SECOND / 50); + + rt_pin_write(TP_RST_PIN, PIN_HIGH); + rt_thread_delay(RT_TICK_PER_SECOND / 50); + } +} + +static void gt9xx_soft_reset(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint8_t buf[3]; + + buf[0] = (rt_uint8_t)((gt9xx_COMMAND_REG >> 8) & 0xFF); + buf[1] = (rt_uint8_t)(gt9xx_COMMAND_REG & 0xFF); + buf[2] = 0x02; + rt_touch_write(GT9xx_TS_ADDR, buf, 3); +} + +static rt_bool_t gt9xx_probe(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint8_t cmd[2]; + rt_uint8_t buffer[5] = {0}; + + gt9xx_hw_reset(GT9xx_TS_ADDR); + //gt9xx_soft_reset(i2c_bus); + rt_thread_delay(RT_TICK_PER_SECOND / 5); + + cmd[0] = (rt_uint8_t)((gt9xx_PRODUCT_ID_REG >> 8) & 0xFF); + cmd[1] = (rt_uint8_t)(gt9xx_PRODUCT_ID_REG & 0xFF); + if (rt_touch_read(GT9xx_TS_ADDR, &cmd, 2, buffer, 4) != 0) + return RT_FALSE; + + buffer[4] = '\0'; + + TPDEBUG("%#X %#X %#X %#X %#X\n", buffer[0], buffer[1], buffer[2], buffer[3], buffer[4]); + + if(!rt_strcmp((const char*)buffer, "911")) + { + rt_kprintf("[TP] Found chip gt911\r\n"); + return RT_TRUE; + } + else if(!rt_strcmp((const char*)buffer, "9147")) + { + rt_kprintf("[TP] Found chip gt9147\r\n"); + return RT_TRUE; + } + else if(!rt_strcmp((const char*)buffer, "9157")) + { + rt_kprintf("[TP] Found chip gt9157\r\n"); + return RT_TRUE; + } + else + { + TPDEBUG("[TP] Uknow chip gt9xx device: [%s]\r\n", buffer); + } + + return RT_FALSE; +} + +static void gt9xx_init(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint8_t buf = 0; + rt_uint8_t cmd[2]; + + gt9xx_driver.isr_sem = rt_sem_create("gt9xx", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(gt9xx_driver.isr_sem); + + cmd[0] = (rt_uint8_t)((gt9xx_CONFIG_VERSION_REG >> 8) & 0xFF); + cmd[1] = (rt_uint8_t)(gt9xx_CONFIG_VERSION_REG & 0xFF); + rt_touch_read(GT9xx_TS_ADDR, &cmd, 2, &buf, 1); + rt_kprintf("[TP] GT9xx Config version: 0x%02X\n", buf); + + cmd[0] = (rt_uint8_t)((gt9xx_VENDOR_ID_REG >> 8) & 0xFF); + cmd[1] = (rt_uint8_t)(gt9xx_VENDOR_ID_REG & 0xFF); + rt_touch_read(GT9xx_TS_ADDR, &cmd, 2, &buf, 1); + rt_kprintf("[TP] GT9xx Sensor id: 0x%02X\n", buf); + + rt_sem_release(gt9xx_driver.isr_sem); +} + +static void gt9xx_deinit(void) +{ + rt_sem_delete(gt9xx_driver.isr_sem); +} + +static rt_err_t gt9xx_read_point(touch_message_t msg) +{ + rt_uint8_t cmd[2]; + rt_uint8_t buf[8] = {0}; + static rt_uint8_t s_tp_down = 0; + + cmd[0] = (rt_uint8_t)((gt9xx_READ_XY_REG >> 8) & 0xFF); + cmd[1] = (rt_uint8_t)(gt9xx_READ_XY_REG & 0xFF); + rt_touch_read(GT9xx_TS_ADDR, &cmd, 2, buf, 8); + + if((buf[0] & 0x01) == 0) + { + if(s_tp_down) + { + s_tp_down = 0; + msg->event = TOUCH_EVENT_UP; + } + else + { + msg->event = TOUCH_EVENT_NONE; + } + } + else + { + msg->x = ((rt_uint16_t)buf[3] << 8) | buf[2]; + msg->y = ((rt_uint16_t)buf[5] << 8) | buf[4]; + + if(s_tp_down) + { + msg->event = TOUCH_EVENT_MOVE; + } + else + { + msg->event = TOUCH_EVENT_DOWN; + s_tp_down = 1; + } + } + + buf[0] = ((gt9xx_CLEARBUF_REG >> 8) & 0xFF); + buf[1] = (gt9xx_CLEARBUF_REG & 0xFF); + buf[2] = 0x00; + rt_touch_write(GT9xx_TS_ADDR, buf, 3); + + rt_sem_release(gt9xx_driver.isr_sem); + + return RT_EOK; +} + +struct touch_ops gt9xx_ops = +{ + .init = gt9xx_init, + .deinit = gt9xx_deinit, + .read_point = gt9xx_read_point, +}; + +static int gt9xx_driver_register(void) +{ + gt9xx_driver.probe = gt9xx_probe; + gt9xx_driver.ops = >9xx_ops; + gt9xx_driver.user_data = RT_NULL; + + rt_touch_drivers_register(>9xx_driver); + + return RT_EOK; +} +INIT_ENV_EXPORT(gt9xx_driver_register); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device.h new file mode 100644 index 0000000000..99e8a879f8 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device.h @@ -0,0 +1,644 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_USB_DEVICE_H__ +#define __FSL_USB_DEVICE_H__ + +/*! + * @addtogroup usb_device_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines Get/Set status Types */ +typedef enum _usb_device_status +{ + kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */ + kUSB_DeviceStatusSpeed, /*!< Current speed */ + kUSB_DeviceStatusOtg, /*!< OTG status */ + kUSB_DeviceStatusDevice, /*!< Device status */ + kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */ + kUSB_DeviceStatusDeviceState, /*!< Device state */ + kUSB_DeviceStatusAddress, /*!< Device address */ + kUSB_DeviceStatusSynchFrame, /*!< Current frame */ + kUSB_DeviceStatusBus, /*!< Bus status */ + kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */ + kUSB_DeviceStatusBusSleep, /*!< Bus suspend */ + kUSB_DeviceStatusBusResume, /*!< Bus resume */ + kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */ + kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */ +} usb_device_status_t; + +/*! @brief Defines USB 2.0 device state */ +typedef enum _usb_device_state +{ + kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/ + kUSB_DeviceStateAddress, /*!< Device state, Address*/ + kUSB_DeviceStateDefault, /*!< Device state, Default*/ + kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/ + kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/ +} usb_device_state_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +typedef enum _usb_dcd_detection_sequence_status +{ + kUSB_DcdDetectionNotEnabled = 0x0U, + kUSB_DcdDataPinDetectionCompleted = 0x01U, + kUSB_DcdChargingPortDetectionCompleted = 0x02U, + kUSB_DcdChargerTypeDetectionCompleted = 0x03U, +} usb_dcd_detection_sequence_status_t; + +typedef enum _usb_dcd_detection_sequence_results +{ + kUSB_DcdDetectionNoResults = 0x0U, + kUSB_DcdDetectionStandardHost = 0x01U, + kUSB_DcdDetectionChargingPort = 0x02U, + kUSB_DcdDetectionDedicatedCharger = 0x03U, +} usb_dcd_detection_sequence_results_t; +#endif + +/*! @brief Defines endpoint state */ +typedef enum _usb_endpoint_status +{ + kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/ + kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/ +} usb_device_endpoint_status_t; + +/*! @brief Control endpoint index */ +#define USB_CONTROL_ENDPOINT (0U) +/*! @brief Control endpoint maxPacketSize */ +#define USB_CONTROL_MAX_PACKET_SIZE (64U) + +#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U))) +#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!! +#endif + +/*! @brief The setup packet size of USB control transfer. */ +#define USB_SETUP_PACKET_SIZE (8U) +/*! @brief USB endpoint mask */ +#define USB_ENDPOINT_NUMBER_MASK (0x0FU) + +/*! @brief Default invalid value or the endpoint callback length of cancelled transfer */ +#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU) + +/*! @brief Available common EVENT types in device callback */ +typedef enum _usb_device_event +{ + kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */ + kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */ + kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */ + kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */ + kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host + */ + kUSB_DeviceEventError, /*!< An error is happened in the bus. */ + kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */ + kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */ + kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */ + kUSB_DeviceEventSetInterface, /*!< Set interface. */ + + kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */ + kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */ + kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */ + kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */ + kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */ + kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */ + kUSB_DeviceEventVendorRequest, /*!< Vendor request. */ + kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */ + kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */ + kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */ + kUSB_DeviceEventSetBHNPEnable, +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceEventDcdTimeOut, /*!< Dcd detect result is timeout */ + kUSB_DeviceEventDcdUnknownType, /*!< Dcd detect result is unknown type */ + kUSB_DeviceEventSDPDetected, /*!< The SDP facility is detected */ + kUSB_DeviceEventChargingPortDetected, /*!< The charging port is detected */ + kUSB_DeviceEventChargingHostDetected, /*!< The CDP facility is detected */ + kUSB_DeviceEventDedicatedChargerDetected, /*!< The DCP facility is detected */ +#endif +} usb_device_event_t; + +/*! @brief Endpoint callback message structure */ +typedef struct _usb_device_endpoint_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_endpoint_callback_message_struct_t; + +/*! + * @brief Endpoint callback function typedef. + * + * This callback function is used to notify the upper layer what the transfer result is. + * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals to the value returned from #USB_DeviceInit. + * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a + * setup phase. + * phase for control pipe. + * @param callbackParam The parameter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam); + +/*! + * @brief Device callback function typedef. + * + * This callback function is used to notify the upper layer that the device status has changed. + * This callback pointer is passed by calling API #USB_DeviceInit. + * + * @param handle The device handle. It equals the value returned from #USB_DeviceInit. + * @param callbackEvent The callback event type. See enumeration #usb_device_event_t. + * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); + +/*! @brief Endpoint callback structure */ +typedef struct _usb_device_endpoint_callback_struct +{ + usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/ + void *callbackParam; /*!< Parameter for callback function*/ + uint8_t isBusy; +} usb_device_endpoint_callback_struct_t; + +/*! @brief Endpoint initialization structure */ +typedef struct _usb_device_endpoint_init_struct +{ + uint16_t maxPacketSize; /*!< Endpoint maximum packet size */ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t transferType; /*!< Endpoint transfer type*/ + uint8_t zlt; /*!< ZLT flag*/ +} usb_device_endpoint_init_struct_t; + +/*! @brief Endpoint status structure */ +typedef struct _usb_device_endpoint_status_struct +{ + uint8_t endpointAddress; /*!< Endpoint address */ + uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */ +} usb_device_endpoint_status_struct_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! @brief USB DCD charge timing specification structure */ +typedef struct _usb_device_dcd_charging_time +{ + uint16_t dcdSeqInitTime; /*!< The dcd sequence init time */ + uint16_t dcdDbncTime; /*!< The debounce time period on DP signal */ + uint16_t dcdDpSrcOnTime; /*!< The time period comparator enabled */ + uint16_t dcdTimeWaitAfterPrD; /*!< The time period between primary and secondary detection */ + uint8_t dcdTimeDMSrcOn; /*!< The amount of time that the modules enable the Vdm_src */ +} usb_device_dcd_charging_time_t; +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name USB device APIs + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t. + * @param[in] deviceCallback Function pointer of the device callback. + * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number. + * Or, the device has been initialized. + * Or, the mutex or message queue is created failed. + */ +extern usb_status_t USB_DeviceInit(uint8_t controllerId, + usb_device_callback_t deviceCallback, + usb_device_handle *handle); + +/*! + * @brief Enables the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceRun(usb_device_handle handle); + +/*! + * @brief Disables the device functionality. + * + * The function disables the device functionality. After this function called, even if the device is detached to the + * host, + * it can't work. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceStop(usb_device_handle handle); + +/*! + * @brief De-initializes the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDeinit(usb_device_handle handle); + +/*! + * @brief Sends data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant. + * @param[in] length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receives data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. The function is not reentrant. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Initializes a specified endpoint. + * + * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t. + * @param[in] epCallback Endpoint callback structure. See the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback); + +/*! + * @brief Deinitializes a specified endpoint. + * + * The function is used to deinitializes a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Stalls a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Unstalls a specified endpoint. + * + * The function is used to unstall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is unstalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Gets the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[out] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +/*! + * @brief Sets the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[in] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer. + */ +extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Initializes the device dcd module. + * + * The function initializes the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] time_param The time parameter used to config the dcd timing registers. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param); + +/*! + * @brief De-initializes the device dcd module. + * + * The function de-initializes the device dcd module specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle); +#endif +/*! + * @brief Device task function. + * + * The function is used to handle the controller message. + * This function should not be called in the application directly. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceTaskFunction(void *deviceHandle); + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI task function. + * + * The function is used to handle the KHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI task function. + * + * The function is used to handle the EHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Device EHCI DCD ISR function. + * + * The function is the EHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdHSIsrFunction(void *deviceHandle); +#endif +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC ip3511 controller task function. + * + * The function is used to handle the LPC ip3511 controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI ISR function. + * + * The function is the KHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceKhciIsrFunction(void *deviceHandle); +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Device KHCI DCD ISR function. + * + * The function is the KHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdIsrFunction(void *deviceHandle); +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI ISR function. + * + * The function is the EHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC USB ISR function. + * + * The function is the LPC USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle); +#endif + +/*! + * @brief Gets the device stack version function. + * + * The function is used to get the device stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +extern void USB_DeviceGetVersion(uint32_t *version); + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick); +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* __USB_DEVICE_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_dci.c b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_dci.c new file mode 100644 index 0000000000..dd28bdcbe3 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_dci.c @@ -0,0 +1,1459 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "usb_device.h" +#include "usb_device_dci.h" + +#include "fsl_device_registers.h" + +#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U)) + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#include "usb_device_khci.h" +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#include "usb_device_ehci.h" +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#include "usb_device_lpcip3511.h" +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) +#include "fsl_cache.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle); +static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle); +static usb_status_t USB_DeviceGetControllerInterface( + uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface); +static usb_status_t USB_DeviceTransfer(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); +static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param); +static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); + +#endif +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) +static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#endif +static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +USB_GLOBAL static usb_device_struct_t s_UsbDevice[USB_DEVICE_CONFIG_NUM]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Allocate a device handle. + * + * This function allocates a device handle. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param handle It is out parameter, is used to return pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_Error The device has been initialized. + */ +static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle) +{ + uint32_t count; + USB_OSA_SR_ALLOC(); + + USB_OSA_ENTER_CRITICAL(); + /* Check the controller is initialized or not. */ + for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++) + { + if ((NULL != s_UsbDevice[count].controllerHandle) && (controllerId == s_UsbDevice[count].controllerId)) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Error; + } + } + /* Get a free device handle. */ + for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++) + { + if (NULL == s_UsbDevice[count].controllerHandle) + { + s_UsbDevice[count].controllerId = controllerId; + *handle = &s_UsbDevice[count]; + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } + } + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Busy; +} + +/*! + * @brief Free a device handle. + * + * This function frees a device handle. + * + * @param handle The device handle. + * + * @retval kStatus_USB_Success Free device handle successfully. + */ +static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle) +{ + USB_OSA_SR_ALLOC(); + + USB_OSA_ENTER_CRITICAL(); + handle->controllerHandle = NULL; + handle->controllerId = 0U; + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/* KHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceKhciInterface = { + USB_DeviceKhciInit, USB_DeviceKhciDeinit, USB_DeviceKhciSend, + USB_DeviceKhciRecv, USB_DeviceKhciCancel, USB_DeviceKhciControl}; +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/* EHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceEhciInterface = { + USB_DeviceEhciInit, USB_DeviceEhciDeinit, USB_DeviceEhciSend, + USB_DeviceEhciRecv, USB_DeviceEhciCancel, USB_DeviceEhciControl}; +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/* EHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceLpc3511IpInterface = { + USB_DeviceLpc3511IpInit, USB_DeviceLpc3511IpDeinit, USB_DeviceLpc3511IpSend, + USB_DeviceLpc3511IpRecv, USB_DeviceLpc3511IpCancel, USB_DeviceLpc3511IpControl}; +#endif + +/*! + * @brief Get the controller interface handle. + * + * This function is used to get the controller interface handle. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param controllerInterface It is out parameter, is used to return pointer of the device controller handle to the + * caller. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_ControllerNotFound The controller id is invalided. + */ +static usb_status_t USB_DeviceGetControllerInterface( + uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface) +{ + usb_status_t error = kStatus_USB_ControllerNotFound; + switch (controllerId) + { +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + /* Get the KHCI controller driver interface */ + case kUSB_ControllerKhci0: + case kUSB_ControllerKhci1: + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceKhciInterface; + error = kStatus_USB_Success; + break; +#endif +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + /* Get the EHCI controller driver interface */ + case kUSB_ControllerEhci0: + case kUSB_ControllerEhci1: + error = kStatus_USB_Success; + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceEhciInterface; + break; +#endif +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) + /* Get the EHCI controller driver interface */ + case kUSB_ControllerLpcIp3511Fs0: + case kUSB_ControllerLpcIp3511Fs1: + case kUSB_ControllerLpcIp3511Hs0: + case kUSB_ControllerLpcIp3511Hs1: + error = kStatus_USB_Success; + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceLpc3511IpInterface; + break; +#endif + default: + break; + } + return error; +} + +/*! + * @brief Start a new transfer. + * + * This function is used to start a new transfer. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param endpointAddress Endpoint address. Bit7 is direction, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address to be transferred, or the memory address to hold the data need to be + * sent. + * @param length The length of the data. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_InvalidHandle The device handle is invalided. + * @retval kStatus_USB_ControllerNotFound The controller interface is not found. + * @retval kStatus_USB_Error The device is doing reset. + */ +static usb_status_t USB_DeviceTransfer(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + USB_OSA_SR_ALLOC(); + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + if (deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy) + { + return kStatus_USB_Busy; + } + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 1U; + USB_OSA_EXIT_CRITICAL(); + if (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) + { +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + if (length) + { + DCACHE_CleanByRange((uint32_t)buffer, length); + } +#endif + /* Call the controller send interface. */ + error = deviceHandle->controllerInterface->deviceSend(deviceHandle->controllerHandle, endpointAddress, + buffer, length); + } + else + { +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + if (length) + { + DCACHE_CleanInvalidateByRange((uint32_t)buffer, length); + } +#endif + /* Call the controller receive interface. */ + error = deviceHandle->controllerInterface->deviceRecv(deviceHandle->controllerHandle, endpointAddress, + buffer, length); + } + if (kStatus_USB_Success != error) + { + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + USB_OSA_EXIT_CRITICAL(); + } + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Control the status of the selected item. + * + * This function is used to control the status of the selected item.. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param type The control type, please refer to the enumeration usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_InvalidHandle The device handle is invalided. + * @retval kStatus_USB_ControllerNotFound The controller interface is not found. + * @retval kStatus_USB_Error Unsupport type. + * Or, the param is NULL pointer. + */ +static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + /* Call the controller control interface. */ + error = deviceHandle->controllerInterface->deviceControl(deviceHandle->controllerHandle, type, param); + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Handle the reset notification. + * + * This function is used to handle the reset notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @retval kStatus_USB_Success Get a device handle successfully. + */ +static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_SR_ALLOC(); +#endif + + handle->isResetting = 1U; + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + /* Clear remote wakeup feature */ + handle->remotewakeup = 0U; +#endif + +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + handle->epCallbackDirectly = 1; + USB_OSA_EXIT_CRITICAL(); +#endif + /* Set the controller to default status. */ + USB_DeviceControl(handle, kUSB_DeviceControlSetDefaultStatus, NULL); +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + handle->epCallbackDirectly = 0; + USB_OSA_EXIT_CRITICAL(); +#endif + + handle->state = kUSB_DeviceStateDefault; + handle->deviceAddress = 0U; + + for (uint32_t count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) + { + handle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; + handle->epCallback[count].callbackParam = NULL; + handle->epCallback[count].isBusy = 0U; + } + + /* Call device callback to notify the application that the USB bus reset signal detected. */ + handle->deviceCallback(handle, kUSB_DeviceEventBusReset, NULL); + + handle->isResetting = 0U; + return kStatus_USB_Success; +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend notification. + * + * This function is used to handle the suspend notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSuspend, NULL); +} + +/*! + * @brief Handle the resume notification. + * + * This function is used to handle the resume notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus resume signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventResume, NULL); +} +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Handle the suspend notification. + * + * This function is used to handle the suspend notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSleeped, NULL); +} +#endif +/*! + * @brief Handle the remotewakeup notification. + * + * This function is used to handle the remotewakeup notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param flag The buffer pointer to store remotewakeup flag. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetRemoteWakeUp(usb_device_struct_t *handle, uint8_t **flag) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return USB_DeviceControl(handle, kUSB_DeviceControlGetRemoteWakeUp, flag); +} + +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) +usb_status_t USB_DeviceErrorNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus error signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventError, NULL); +} +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) +/*! + * @brief Handle the detach notification. + * + * This function is used to handle the detach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device is disconnected from a host. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDetach, NULL); +} + +/*! + * @brief Handle the attach notification. + * + * This function is used to handle the attach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device is connected to a host. */ + return handle->deviceCallback(handle, kUSB_DeviceEventAttach, NULL); +} +#endif + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +/*! + * @brief Handle the dcd module timeout notification. + * + * This function is used to handle the dcd module timeout notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdTimeOutNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device charger detect timeout happened. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDcdTimeOut, NULL); +} + +/*! + * @brief Handle the dcd module unknown port type notification. + * + * This function is used to handle the dcd module unknown port type notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdUnknownPortTypeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device charger detect unknown port type happened. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDcdUnknownType, NULL); +} + +/*! + * @brief Handle the SDP facility is detected notification. + * + * This function is used to handle the SDP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdSDPDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the SDP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSDPDetected, NULL); +} + +/*! + * @brief Handle the charging port is detected notification. + * + * This function is used to handle the charging port is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdChargingPortDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the charing port is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventChargingPortDetected, NULL); +} + +/*! + * @brief Handle the CDP facility is detected notification. + * + * This function is used to handle the CDP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdChargingHostDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the CDP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventChargingHostDetected, NULL); +} + +/*! + * @brief Handle the DCP facility is detected notification. + * + * This function is used to handle the DCP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ + +static usb_status_t USB_DeviceDcdDedicatedChargerDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the DCP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDedicatedChargerDetected, NULL); +} +#endif + +/*! + * @brief Handle the attach notification. + * + * This function is used to handle the attach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) +{ + uint8_t endpoint = message->code & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (message->code & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + usb_status_t error = kStatus_USB_Error; + + switch (message->code) + { + case kUSB_DeviceNotifyBusReset: + error = USB_DeviceResetNotification(handle, message); + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + case kUSB_DeviceNotifySuspend: + error = USB_DeviceSuspendNotification(handle, message); + break; + case kUSB_DeviceNotifyResume: + error = USB_DeviceResumeNotification(handle, message); + break; +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + case kUSB_DeviceNotifyLPMSleep: + error = USB_DeviceSleepNotification(handle, message); + break; +#endif +#endif + +#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) + case kUSB_DeviceNotifyError: + error = USB_DeviceErrorNotification(handle, message); + break; +#endif + +#if USB_DEVICE_CONFIG_DETACH_ENABLE + case kUSB_DeviceNotifyDetach: + error = USB_DeviceDetachNotification(handle, message); + break; + case kUSB_DeviceNotifyAttach: + error = USB_DeviceAttachNotification(handle, message); + break; +#endif +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) + case kUSB_DeviceNotifyDcdTimeOut: + error = USB_DeviceDcdTimeOutNotification(handle, message); + break; + case kUSB_DeviceNotifyDcdUnknownPortType: + error = USB_DeviceDcdUnknownPortTypeNotification(handle, message); + break; + case kUSB_DeviceNotifySDPDetected: + error = USB_DeviceDcdSDPDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyChargingPortDetected: + error = USB_DeviceDcdChargingPortDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyChargingHostDetected: + error = USB_DeviceDcdChargingHostDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyDedicatedChargerDetected: + error = USB_DeviceDcdDedicatedChargerDetectNotification(handle, message); + break; +#endif + + default: + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn) + { + usb_device_endpoint_callback_message_struct_t endpointCallbackMessage; + endpointCallbackMessage.buffer = message->buffer; + endpointCallbackMessage.length = message->length; + endpointCallbackMessage.isSetup = message->isSetup; + if (message->isSetup) + { + handle->epCallback[0].isBusy = 0U; + handle->epCallback[1].isBusy = 0U; + } + else + { + handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + /* Call endpoint callback */ + error = handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn( + handle, &endpointCallbackMessage, + handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam); + } + } + break; + } + return error; +} + +/*! + * @brief Notify the device that the controller status changed. + * + * This function is used to notify the device that the controller status changed. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_device_callback_message_struct_t *message = (usb_device_callback_message_struct_t *)msg; + + if ((NULL == msg) || (NULL == handle)) + { + return kStatus_USB_InvalidHandle; + } + + /* The device callback is invalid or not. */ + if (!deviceHandle->deviceCallback) + { + return kStatus_USB_Error; + } + +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + if (deviceHandle->epCallbackDirectly) + { + if ((message->code & USB_ENDPOINT_NUMBER_MASK) && (!(message->code & 0x70U))) + { + return USB_DeviceNotification(deviceHandle, message); + } + } + + /* Add the message to message queue when the device task is enabled. */ + if (kStatus_USB_OSA_Success != USB_OsaMsgqSend(deviceHandle->notificationQueue, (void *)message)) + { + return kStatus_USB_Busy; + } + return kStatus_USB_Success; +#else + /* Handle the notification by calling USB_DeviceNotification. */ + return USB_DeviceNotification(deviceHandle, message); +#endif +} + +/*! + * @brief Initialize the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param deviceCallback Function pointer of the device callback. + * @param handle It is out parameter, is used to return pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invaild, There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than IP's endpoint number. + * Or, the device has been initialized. + * Or, the message queue is created failed. + */ +usb_status_t USB_DeviceInit(uint8_t controllerId, usb_device_callback_t deviceCallback, usb_device_handle *handle) +{ + usb_device_struct_t *deviceHandle = NULL; + usb_status_t error; + uint32_t count; + + if (NULL == handle) + { + return kStatus_USB_InvalidHandle; + } + + /* Allocate a device handle by using the controller id. */ + error = USB_DeviceAllocateHandle(controllerId, &deviceHandle); + + if (kStatus_USB_Success != error) + { + return error; + } + + /* Save the device callback */ + deviceHandle->deviceCallback = deviceCallback; + /* Save the controller id */ + deviceHandle->controllerId = controllerId; + /* Clear the device address */ + deviceHandle->deviceAddress = 0U; + /* Clear the device reset state */ + deviceHandle->isResetting = 0U; + + /* Initialize the enpoints */ + for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) + { + deviceHandle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; + deviceHandle->epCallback[count].callbackParam = NULL; + deviceHandle->epCallback[count].isBusy = 0U; + } + + /* Get the controller interface according to the controller id */ + error = USB_DeviceGetControllerInterface(controllerId, &deviceHandle->controllerInterface); + if (kStatus_USB_Success != error) + { + USB_DeviceFreeHandle(deviceHandle); + return error; + } + if (NULL == deviceHandle->controllerInterface) + { + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_ControllerNotFound; + } + if (((usb_device_controller_init_t)NULL == deviceHandle->controllerInterface->deviceInit) || + ((usb_device_controller_deinit_t)NULL == deviceHandle->controllerInterface->deviceDeinit) || + ((usb_device_controller_send_t)NULL == deviceHandle->controllerInterface->deviceSend) || + ((usb_device_controller_recv_t)NULL == deviceHandle->controllerInterface->deviceRecv) || + ((usb_device_controller_cancel_t)NULL == deviceHandle->controllerInterface->deviceCancel) || + ((usb_device_controller_control_t)NULL == deviceHandle->controllerInterface->deviceControl)) + { + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_InvalidControllerInterface; + } + +#if USB_DEVICE_CONFIG_USE_TASK + /* Create a message queue when the device handle is enabled. */ + if (kStatus_USB_OSA_Success != + USB_OsaMsgqCreate(&deviceHandle->notificationQueue, USB_DEVICE_CONFIG_MAX_MESSAGES, + (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t)))) + { + USB_DeviceDeinit(deviceHandle); + return kStatus_USB_Error; + } +#endif + + *handle = deviceHandle; + + /* Initialize the controller */ + error = deviceHandle->controllerInterface->deviceInit(controllerId, deviceHandle, &deviceHandle->controllerHandle); + if (kStatus_USB_Success != error) + { + USB_DeviceDeinit(deviceHandle); + *handle = NULL; + return error; + } + /* Set the device to deafult state */ + deviceHandle->state = kUSB_DeviceStateDefault; + + return error; +} + +/*! + * @brief Enable the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceRun(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlRun, NULL); +} +/*! + * @brief Disable the device functionality. + * + * The function disables the device functionality, after this function called, even the device is detached to the host, + * and the device can't work. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + */ +usb_status_t USB_DeviceStop(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlStop, NULL); +} +/*! + * @brief De-initialize the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + */ +usb_status_t USB_DeviceDeinit(usb_device_handle handle) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + /* De-initialize the controller */ + if (NULL != deviceHandle->controllerInterface) + { + deviceHandle->controllerInterface->deviceDeinit(deviceHandle->controllerHandle); + deviceHandle->controllerInterface = (usb_device_controller_interface_struct_t *)NULL; + } + +#if USB_DEVICE_CONFIG_USE_TASK + /* Destroy the message queue. */ + if (NULL != deviceHandle->notificationQueue) + { + USB_OsaMsgqDestroy(deviceHandle->notificationQueue); + deviceHandle->notificationQueue = NULL; + } +#endif + + /* Free the device handle. */ + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceSendRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) +{ + return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | + (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) +{ + return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | + (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + error = deviceHandle->controllerInterface->deviceCancel(deviceHandle->controllerHandle, endpointAddress); + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint and the corresponding endpoint callback is also initialized. + * + * @param handle The device handle got from USB_DeviceInit. + * @param epInit Endpoint initizlization structure. Please refer to the structure usb_device_endpoint_init_struct_t. + * @param epCallback Endpoint callback structure. Please refer to the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + uint8_t endpoint; + uint8_t direction; + + if (!deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if ((!epInit) || (!epCallback)) + { + return kStatus_USB_InvalidParameter; + } + + endpoint = epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK; + direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = epCallback->callbackFn; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = + epCallback->callbackParam; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + else + { + return kStatus_USB_InvalidParameter; + } + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointInit, epInit); +} + +/*! + * @brief De-initizlize a specified endpoint. + * + * The function is used to de-initizlize a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + usb_status_t error = kStatus_USB_Error; +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_SR_ALLOC(); +#endif + + if (!deviceHandle) + { + return kStatus_USB_InvalidHandle; + } +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallbackDirectly = 1; + USB_OSA_EXIT_CRITICAL(); +#endif + error = USB_DeviceControl(handle, kUSB_DeviceControlEndpointDeinit, &endpointAddress); +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallbackDirectly = 0; + USB_OSA_EXIT_CRITICAL(); +#endif + + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = + (usb_device_endpoint_callback_t)NULL; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = NULL; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + else + { + return kStatus_USB_InvalidParameter; + } + return error; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) + { + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointStall, &endpointAddress); + } + else + { + return kStatus_USB_InvalidParameter; + } +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is un-stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) + { + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointUnstall, &endpointAddress); + } + else + { + return kStatus_USB_InvalidParameter; + } +} + +/*! + * @brief Get the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param handle The device handle got from USB_DeviceInit. + * @param type The selected item. Please refer to the structure usb_device_status_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The param is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param) +{ + uint8_t *temp8; + usb_status_t error = kStatus_USB_Error; + + if (NULL == param) + { + return kStatus_USB_InvalidParameter; + } + switch (type) + { + case kUSB_DeviceStatusSpeed: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetSpeed, param); + break; + case kUSB_DeviceStatusOtg: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetOtgStatus, param); + break; + case kUSB_DeviceStatusDeviceState: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->state; + break; + case kUSB_DeviceStatusAddress: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->deviceAddress; + break; + case kUSB_DeviceStatusDevice: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetDeviceStatus, param); + break; + case kUSB_DeviceStatusEndpoint: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetEndpointStatus, param); + break; + case kUSB_DeviceStatusSynchFrame: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetSynchFrame, param); + break; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + case kUSB_DeviceStatusRemoteWakeup: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->remotewakeup; + break; +#endif + default: + break; + } + return error; +} + +/*! + * @brief Set the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param handle The device handle got from USB_DeviceInit. + * @param type The selected item. Please refer to the structure usb_device_status_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type, or the param is NULL pointer. + */ +usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param) +{ + usb_status_t error = kStatus_USB_Error; + switch (type) + { +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) || \ + (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \ + (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceStatusTestMode: + error = USB_DeviceControl(handle, kUSB_DeviceControlSetTestMode, param); + break; +#endif + case kUSB_DeviceStatusOtg: + error = USB_DeviceControl(handle, kUSB_DeviceControlSetOtgStatus, param); + break; + case kUSB_DeviceStatusDeviceState: + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->state = (uint8_t)(*(uint8_t *)param); + } + break; + case kUSB_DeviceStatusAddress: + if (kUSB_DeviceStateAddressing != ((usb_device_struct_t *)handle)->state) + { + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->deviceAddress = (uint8_t)(*(uint8_t *)param); + ((usb_device_struct_t *)handle)->state = kUSB_DeviceStateAddressing; + } + } + else + { + error = USB_DeviceControl(handle, kUSB_DeviceControlSetDeviceAddress, + &((usb_device_struct_t *)handle)->deviceAddress); + } + break; + case kUSB_DeviceStatusBusResume: + error = USB_DeviceControl(handle, kUSB_DeviceControlResume, param); + break; + case kUSB_DeviceStatusBusSleepResume: + error = USB_DeviceControl(handle, kUSB_DeviceControlSleepResume, param); + break; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + case kUSB_DeviceStatusRemoteWakeup: + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->remotewakeup = (uint8_t)(*(uint8_t *)param); + } + break; +#endif + case kUSB_DeviceStatusBusSuspend: + error = USB_DeviceControl(handle, kUSB_DeviceControlSuspend, param); + break; + case kUSB_DeviceStatusBusSleep: + error = USB_DeviceControl(handle, kUSB_DeviceControlSleep, param); + break; + default: + break; + } + return error; +} + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +/*! + * @brief Initializes the device dcd module. + * + * The function initializes the device dcd module. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlDcdInitModule, time_param); +} + +/*! + * @brief De-initializes the device dcd module. + * + * The function de-intializes the device dcd module. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlDcdDeinitModule, NULL); +} +#endif + +#if USB_DEVICE_CONFIG_USE_TASK +/*! + * @brief Device task function. + * + * The function is used to handle controller message. + * This function should not be called in applicartion directly. + * + * @param handle The device handle got from USB_DeviceInit. + */ +void USB_DeviceTaskFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + static usb_device_callback_message_struct_t message; + + if (deviceHandle) + { + /* Get the message from the queue */ + if (kStatus_USB_OSA_Success == USB_OsaMsgqRecv(handle->notificationQueue, (uint32_t *)&message, 0U)) + { + /* Handle the message */ + USB_DeviceNotification(handle, &message); + } + } +} +#endif + +/*! + * @brief Get dvice stack version function. + * + * The function is used to get dvice stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +void USB_DeviceGetVersion(uint32_t *version) +{ + if (version) + { + *version = + (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); + } +} + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick. + * + */ +usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick) +{ + usb_device_struct_t *deviceHandle; + usb_status_t status = kStatus_USB_Success; + + if (handle == NULL) + { + return kStatus_USB_InvalidHandle; + } + deviceHandle = (usb_device_struct_t *)handle; + + deviceHandle->hwTick = tick; + + return status; +} +#endif +#endif /* USB_DEVICE_CONFIG_NUM */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_dci.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_dci.h new file mode 100644 index 0000000000..fd4fdceb04 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_dci.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_DCI_H__ +#define __USB_DEVICE_DCI_H__ + +/*! + * @addtogroup usb_device_controller_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Macro to define controller handle */ +#define usb_device_controller_handle usb_device_handle + +/*! @brief Available notify types for device notification */ +typedef enum _usb_device_notification +{ + kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */ + kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */ + kUSB_DeviceNotifyResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */ + kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyError, /*!< Errors happened in bus */ + kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */ + kUSB_DeviceNotifyAttach, /*!< Device connected to a host */ +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceNotifyDcdTimeOut, /*!< Device charger detection timeout */ + kUSB_DeviceNotifyDcdUnknownPortType, /*!< Device charger detection unknown port type */ + kUSB_DeviceNotifySDPDetected, /*!< The SDP facility is detected */ + kUSB_DeviceNotifyChargingPortDetected, /*!< The charging port is detected */ + kUSB_DeviceNotifyChargingHostDetected, /*!< The CDP facility is detected */ + kUSB_DeviceNotifyDedicatedChargerDetected, /*!< The DCP facility is detected */ +#endif +} usb_device_notification_t; + +/*! @brief Device notification message structure */ +typedef struct _usb_device_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t code; /*!< Notification code */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_callback_message_struct_t; + +/*! @brief Control type for controller */ +typedef enum _usb_device_control_type +{ + kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */ + kUSB_DeviceControlStop, /*!< Disable the device functionality */ + kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */ + kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */ + kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */ + kUSB_DeviceControlEndpointUnstall, /*!< Unstall a specified endpoint */ + kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */ + kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */ + kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */ + kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */ + kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */ + kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */ + kUSB_DeviceControlSuspend, /*!< Drive controller to enetr into suspend mode */ + kUSB_DeviceControlSleep, /*!< Drive controller to enetr into sleep mode */ + kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */ + kUSB_DeviceControlGetSpeed, /*!< Get current speed */ + kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */ + kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */ + kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */ + kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */ +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceControlDcdInitModule, + kUSB_DeviceControlDcdDeinitModule, +#endif +} usb_device_control_type_t; + +/*! @brief USB device controller initialization function typedef */ +typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle); + +/*! @brief USB device controller de-initialization function typedef */ +typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle); + +/*! @brief USB device controller send data function typedef */ +typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller receive data function typedef */ +typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */ +typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress); + +/*! @brief USB device controller control function typedef */ +typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle, + usb_device_control_type_t command, + void *param); + +/*! @brief USB device controller interface structure */ +typedef struct _usb_device_controller_interface_struct +{ + usb_device_controller_init_t deviceInit; /*!< Controller initialization */ + usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */ + usb_device_controller_send_t deviceSend; /*!< Controller send data */ + usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */ + usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */ + usb_device_controller_control_t deviceControl; /*!< Controller control */ +} usb_device_controller_interface_struct_t; + +/*! @brief USB device status structure */ +typedef struct _usb_device_struct +{ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ +#endif + usb_device_controller_handle controllerHandle; /*!< Controller handle */ + const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */ +#if USB_DEVICE_CONFIG_USE_TASK + usb_osa_msgq_handle notificationQueue; /*!< Message queue */ +#endif + usb_device_callback_t deviceCallback; /*!< Device callback function pointer */ + usb_device_endpoint_callback_struct_t + epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */ + uint8_t deviceAddress; /*!< Current device address */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t state; /*!< Current device state */ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */ +#endif + uint8_t isResetting; /*!< Is doing device reset or not */ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */ +#endif +} usb_device_struct_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @}*/ + +#endif /* __USB_DEVICE_DCI_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_ehci.c b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_ehci.c new file mode 100644 index 0000000000..7bb202143d --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_ehci.c @@ -0,0 +1,1807 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_device_registers.h" +#include +#include "usb_device.h" +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + +#include "usb_device_dci.h" + +#include "usb_device_ehci.h" +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#include "usb_phy.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState); +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit); +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction); +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState); +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +extern usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Apply for QH buffer, 2048-byte alignment */ +USB_RAM_ADDRESS_ALIGNMENT(2048) +USB_CONTROLLER_DATA static uint8_t qh_buffer[(USB_DEVICE_CONFIG_EHCI - 1) * 2048 + + USB_DEVICE_CONFIG_ENDPOINTS * 2 * sizeof(usb_device_ehci_qh_struct_t)]; + +/* Apply for DTD buffer, 32-byte alignment */ +USB_RAM_ADDRESS_ALIGNMENT(32) +USB_CONTROLLER_DATA static usb_device_ehci_dtd_struct_t + s_UsbDeviceEhciDtd[USB_DEVICE_CONFIG_EHCI][USB_DEVICE_CONFIG_EHCI_MAX_DTD]; + +/* Apply for ehci device state structure */ +static usb_device_ehci_state_struct_t g_UsbDeviceEhciSate[USB_DEVICE_CONFIG_EHCI]; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/* Apply for device dcd state structure */ +static usb_device_dcd_state_struct_t s_UsbDeviceDcdHSState[USB_DEVICE_CONFIG_EHCI]; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief EHCI NC get USB NC bass address. + * + * This function is used to get USB NC bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB NC bass address. + */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +void *USB_EhciNCGetBase(uint8_t controllerId) +{ + void *usbNCBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) + { + if (usbnc_base_temp[instance]) + { + usbnc_base[newinstance++] = usbnc_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbNCBase = (void *)usbnc_base[controllerId]; +#endif + return usbNCBase; +} +#endif +#endif + +/*! + * @brief Set device controller state to default state. + * + * The function is used to set device controller state to default state. + * The function will be called when USB_DeviceEhciInit called or the control type kUSB_DeviceControlGetEndpointStatus + * received in USB_DeviceEhciControl. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_ehci_dtd_struct_t *p; + + /* Initialize the dtd free queue */ + ehciState->dtdFree = ehciState->dtd; + p = ehciState->dtdFree; + for (uint32_t i = 1U; i < USB_DEVICE_CONFIG_EHCI_MAX_DTD; i++) + { + p->nextDtdPointer = (uint32_t)&ehciState->dtd[i]; + p = (usb_device_ehci_dtd_struct_t *)p->nextDtdPointer; + } + p->nextDtdPointer = 0U; + ehciState->dtdCount = USB_DEVICE_CONFIG_EHCI_MAX_DTD; + + /* Not use interrupt threshold. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ITC_MASK; + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ITC(0U); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ehciState->registerBase->USBMODE |= USBHS_USBMODE_SLOM_MASK; + +/* Set the endian by using CPU's endian */ +#if (ENDIANNESS == USB_BIG_ENDIAN) + ehciState->registerBase->USBMODE |= USBHS_USBMODE_ES_MASK; +#else + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_ES_MASK; +#endif + /* Initialize the QHs of endpoint. */ + for (uint32_t i = 0U; i < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); i++) + { + ehciState->qh[i].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[i].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + USB_CONTROL_MAX_PACKET_SIZE; + ehciState->dtdHard[i] = NULL; + ehciState->dtdTail[i] = NULL; + ehciState->qh[i].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + } + + /* Add QH buffer address to USBHS_EPLISTADDR_REG */ + ehciState->registerBase->EPLISTADDR = (uint32_t)ehciState->qh; + + /* Clear device address */ + ehciState->registerBase->DEVICEADDR = 0U; + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + ehciState->registerBase->OTGSC = ehciState->registerBase->OTGSC & 0x0000FFFF; + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIE_MASK; +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + /* Enable reset, sof, token, stall interrupt */ + ehciState->registerBase->USBINTR = + (USBHS_USBINTR_UE_MASK | USBHS_USBINTR_UEE_MASK | USBHS_USBINTR_PCE_MASK | USBHS_USBINTR_URE_MASK +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + | USBHS_USBINTR_SLE_MASK +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + ); + + /* Clear reset flag */ + ehciState->isResetting = 0U; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param epInit The endpoint initialization structure pointer. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit) +{ + uint32_t primeBit = 1U << ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint16_t maxPacketSize = epInit->maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK; + uint8_t endpoint = (epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + uint8_t transferType = epInit->transferType & USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK; + + /* Cancel pending transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, epInit->endpointAddress); + + if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) + { + return kStatus_USB_Busy; + } + + /* Make the endpoint max packet size align with USB Specification 2.0. */ + if (USB_ENDPOINT_ISOCHRONOUS == transferType) + { + if (maxPacketSize > USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE) + { + maxPacketSize = USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE; + } + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = + 1U + ((maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK) >> + USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = 0U; + } + + /* Save the max packet size of the endpoint */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + maxPacketSize; + /* Set ZLT bit. */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = !epInit->zlt; + + /* Enable the endpoint. */ + if (USB_ENDPOINT_CONTROL == transferType) + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 1U; + ehciState->registerBase->EPCR0 |= + (direction ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 0U; + ehciState->registerBase->EPCR[endpoint - 1U] |= + (direction ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 1U; + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize a specified endpoint. + * + * The function is used to de-initialize a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be disabled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint32_t primeBit = + 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t endpoint = (ep & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + + /* Cancel the transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, ep); + + if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) + { + return kStatus_USB_Busy; + } + + /* Clear endpoint state */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristics = 0U; + /* Disable the endpoint */ + if (!endpoint) + { + ehciState->registerBase->EPCR0 &= + ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= + ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + /* Cancel the transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, ep); + + /* Set endpoint stall flag. */ + if (ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios) + { + if (!endpoint) + { + ehciState->registerBase->EPCR0 |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + } + else + { + if (!endpoint) + { + ehciState->registerBase->EPCR0 |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + } + + return kStatus_USB_Success; +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be un-stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + /* Clear the endpoint stall state */ + if (!endpoint) + { + ehciState->registerBase->EPCR0 &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXR_MASK : USBHS_EPCR_RXR_MASK); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Get setup packet data. + * + * The function is used to get setup packet data and copy to a backup buffer. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint number. + * + */ +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t waitingSafelyAccess = 1U; + uint8_t index = (ep * 2U) | USB_OUT; + + /* Write 1U to clear corresponding bit in EPSETUPSR. */ + ehciState->registerBase->EPSETUPSR = 1U << ep; + + while (waitingSafelyAccess) + { + /* Set the setup tripwire bit. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_SUTW_MASK; + + /* Copy setup packet data to backup buffer */ + ehciState->qh[index].setupBufferBack[0] = ehciState->qh[index].setupBuffer[0]; + ehciState->qh[index].setupBufferBack[1] = ehciState->qh[index].setupBuffer[1]; + + /* Read the USBCMD[SUTW] bit. If set, jump out from the while loop; if cleared continue */ + if (ehciState->registerBase->USBCMD & USBHS_USBCMD_SUTW_MASK) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the setup tripwire bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_SUTW_MASK; + + /* Poll until the EPSETUPSR bit clearred */ + while (ehciState->registerBase->EPSETUPSR & (1U << ep)) + { + } +} + +/*! + * @brief Cancel the transfer of the control pipe. + * + * The function is used to cancel the transfer of the control pipe. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpoint The endpoint number. + * @param direction The direction of the endpoint. + * + */ +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction) +{ + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t index = ((uint32_t)endpoint << 1U) + (uint32_t)direction; + usb_device_callback_message_struct_t message; + + message.buffer = NULL; + message.length = 0U; + /* Get the dtd of the control pipe */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + /* Pass the transfer buffer address */ + if (NULL == message.buffer) + { + uint32_t bufferAddress = currentDtd->bufferPointerPage[0]; + message.buffer = (uint8_t *)((bufferAddress & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* If the dtd is active, set the message length to USB_UNINITIALIZED_VAL_32. Or set the length by using finished + * length. */ + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + message.length = USB_UNINITIALIZED_VAL_32; + } + else + { + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + } + + /* Move the dtd head pointer to next. */ + /* If the pointer of the head equals to the tail, set the dtd queue to null. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + + /* Clear the token field of the dtd. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Add the dtd to the free dtd queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + + /* Get the next in-used dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } +} + +/*! + * @brief Handle the endpoint token done interrupt. + * + * The function is used to handle the endpoint token done interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status; + uint32_t primeBit; + usb_device_ehci_dtd_struct_t *currentDtd; + usb_device_callback_message_struct_t message; + uint8_t endpoint; + uint8_t direction; + uint8_t count; + uint8_t index; + + /* Get the EPSETUPSR to check the setup packect received in which one endpoint. */ + status = ehciState->registerBase->EPSETUPSR; + + if (status) + { + for (endpoint = 0U; endpoint < USB_DEVICE_CONFIG_ENDPOINTS; endpoint++) + { + /* Check the endpoint receive the setup packet. */ + if (status & (1U << endpoint)) + { + /* Get last setup packet */ + usb_setup_struct_t *deviceSetup = + (usb_setup_struct_t *)&ehciState->qh[(uint8_t)((uint32_t)endpoint << 1U) + USB_OUT].setupBufferBack; + + /* Check the direction of the data phase. */ + direction = (deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_IN) >> USB_REQUEST_TYPE_DIR_SHIFT; + /* Cancel the data phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, direction); + /* Cancel the status phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, 1U ^ direction); + message.code = (endpoint) | (USB_OUT << 0x07U); + message.buffer = (uint8_t *)deviceSetup; + message.length = USB_SETUP_PACKET_SIZE; + message.isSetup = 1U; + /* Fill the setup packet to the backup buffer */ + USB_DeviceEhciFillSetupBuffer(ehciState, endpoint); + /* Notify the up layer the EHCI status changed. */ + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } + } + /* Read the USBHS_EPCOMPLETE_REG to get the endpoint transfer done status */ + status = ehciState->registerBase->EPCOMPLETE; + /* Clear the endpoint transfer done status */ + ehciState->registerBase->EPCOMPLETE = status; + + if (status) + { + for (count = 0U; count < 32U; count++) + { + /* Check the transfer is done or not in the specified endpoint. */ + if (status & ((uint32_t)(1U << count))) + { + if (count > 15U) + { + endpoint = count - 16U; + direction = USB_IN; + } + else + { + endpoint = count; + direction = USB_OUT; + } + if (endpoint >= USB_DEVICE_CONFIG_ENDPOINTS) + { + continue; + } + index = (endpoint << 1U) + direction; + message.buffer = NULL; + message.length = 0U; + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + uint8_t isTokenDone = 0; + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (currentDtd) + { + /* Don't handle the active dtd. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) || + (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + if ((!(currentDtd->dtdTokenUnion.dtdTokenBitmap.status & + USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) && + (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + isTokenDone = 1U; + } + break; + } + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + if ((0 == isTokenDone) && (currentDtd)) + { + break; + } + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + /* Don't handle the active dtd. */ + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + break; + } + + /* Save the transfer buffer address */ + if (NULL == message.buffer) + { + message.buffer = + (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* Save the transferred data length */ + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + + /* Move the dtd queue head pointer to next */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = + (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + /* Clear the token field of the dtd */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + /* Get the next in-used dtd */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + if ((NULL != currentDtd) && + (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) + { + primeBit = 1U << (endpoint + 16U * direction); + + /* Try to prime the next dtd. */ + ehciState->registerBase->EPPRIME = primeBit; + + /* Whether the endpoint transmit/receive buffer is ready or not. If not, wait for prime bit + * cleared and prime the next dtd. */ + if (!(ehciState->registerBase->EPSR & primeBit)) + { + /* Wait for the endpoint prime bit cleared by HW */ + while (ehciState->registerBase->EPPRIME & primeBit) + { + } + + /* If the endpoint transmit/receive buffer is not ready */ + if (!(ehciState->registerBase->EPSR & primeBit)) + { + /* Prime next dtd and prime the transfer */ + ehciState->qh[index].nextDtdPointer = (uint32_t)currentDtd; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + } + } + } + } + } +} + +/*! + * @brief Handle the port status change interrupt. + * + * The function is used to handle the port status change interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + /* Whether the port is doing reset. */ + if (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)) + { + /* If not, update the USB speed. */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_HSP_MASK) + { + ehciState->speed = USB_SPEED_HIGH; + } + else + { + ehciState->speed = USB_SPEED_FULL; + } + + /* If the device reset flag is non-zero, notify the up layer the device reset finished. */ + if (ehciState->isResetting) + { + message.code = kUSB_DeviceNotifyBusReset; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + ehciState->isResetting = 0U; + } + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if ((ehciState->isSuspending) && (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK))) + { + /* Set the resume flag */ + ehciState->isSuspending = 0U; + + message.code = kUSB_DeviceNotifyResume; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +} + +/*! + * @brief Handle the reset interrupt. + * + * The function is used to handle the reset interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status = 0U; + + /* Clear the setup flag */ + status = ehciState->registerBase->EPSETUPSR; + ehciState->registerBase->EPSETUPSR = status; + /* Clear the endpoint complete flag */ + status = ehciState->registerBase->EPCOMPLETE; + ehciState->registerBase->EPCOMPLETE = status; + + do + { + /* Flush the pending transfers */ + ehciState->registerBase->EPFLUSH = USBHS_EPFLUSH_FERB_MASK | USBHS_EPFLUSH_FETB_MASK; + } while (ehciState->registerBase->EPPRIME & (USBHS_EPPRIME_PERB_MASK | USBHS_EPPRIME_PETB_MASK)); + + /* Whether is the port reset. If yes, set the isResetting flag. Or, notify the up layer. */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + ehciState->isResetting = 1U; + } + else + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.code = kUSB_DeviceNotifyBusReset; + message.length = 0U; + message.isSetup = 0U; + + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +} + +/*! + * @brief Handle the sof interrupt. + * + * The function is used to handle the sof interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState) +{ +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend interrupt. + * + * The function is used to handle the suspend interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState) +{ + /* If the port is in suspend state, notify the up layer */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK) + { +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#else + if (ehciState->registerPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) +#endif + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + message.code = kUSB_DeviceNotifySuspend; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +} +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +/*! + * @brief Get dtds and link to QH. + * + * The function is used to get dtds and link to QH. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpointAddress The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address needed to be transferred. + * @param length Data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_ehci_dtd_struct_t *dtd; + usb_device_ehci_dtd_struct_t *dtdHard; + uint32_t index = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + uint32_t primeBit = 1U << ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t epStatus = primeBit; + uint32_t sendLength; + uint32_t currentIndex = 0U; + uint32_t dtdRequestCount = (length + USB_DEVICE_ECHI_DTD_TOTAL_BYTES - 1U) / USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + uint8_t qhIdle = 0U; + uint8_t waitingSafelyAccess = 1U; + USB_OSA_SR_ALLOC(); + + if (!ehciState) + { + return kStatus_USB_InvalidHandle; + } + + if (0U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened) + { + return kStatus_USB_Error; + } + /* Return error when ehci is doing reset */ + if (ehciState->isResetting) + { + return kStatus_USB_Error; + } + + if (!dtdRequestCount) + { + dtdRequestCount = 1U; + } + + USB_OSA_ENTER_CRITICAL(); + /* The free dtd count need to not less than the transfer requests. */ + if (dtdRequestCount > (uint32_t)ehciState->dtdCount) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Busy; + } + + do + { + /* The transfer length need to not more than USB_DEVICE_ECHI_DTD_TOTAL_BYTES for each dtd. */ + if (length > USB_DEVICE_ECHI_DTD_TOTAL_BYTES) + { + sendLength = USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + } + else + { + sendLength = length; + } + length -= sendLength; + + /* Get a free dtd */ + dtd = ehciState->dtdFree; + + ehciState->dtdFree = (usb_device_ehci_dtd_struct_t *)dtd->nextDtdPointer; + ehciState->dtdCount--; + + /* Save the dtd head when current active buffer offset is zero. */ + if (!currentIndex) + { + dtdHard = dtd; + } + + /* Set the dtd field */ + dtd->nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + dtd->dtdTokenUnion.dtdToken = 0U; + dtd->bufferPointerPage[0] = (uint32_t)(buffer + currentIndex); + dtd->bufferPointerPage[1] = + (dtd->bufferPointerPage[0] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK) & USB_DEVICE_ECHI_DTD_PAGE_MASK; + dtd->bufferPointerPage[2] = dtd->bufferPointerPage[1] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[3] = dtd->bufferPointerPage[2] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[4] = dtd->bufferPointerPage[3] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + + dtd->dtdTokenUnion.dtdTokenBitmap.totalBytes = sendLength; + + /* Save the data length needed to be transferred. */ + dtd->reservedUnion.originalBufferInfo.originalBufferLength = sendLength; + /* Save the original buffer address */ + dtd->reservedUnion.originalBufferInfo.originalBufferOffest = + dtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK; + dtd->reservedUnion.originalBufferInfo.dtdInvalid = 0U; + + /* Set the IOC field in last dtd. */ + if (!length) + { + dtd->dtdTokenUnion.dtdTokenBitmap.ioc = 1U; + } + + /* Set dtd active */ + dtd->dtdTokenUnion.dtdTokenBitmap.status = USB_DEVICE_ECHI_DTD_STATUS_ACTIVE; + + /* Move the buffer offset index */ + currentIndex += sendLength; + + /* Add dtd to the in-used dtd queue */ + if (ehciState->dtdTail[index]) + { + ehciState->dtdTail[index]->nextDtdPointer = (uint32_t)dtd; + ehciState->dtdTail[index] = dtd; + } + else + { + ehciState->dtdHard[index] = dtd; + ehciState->dtdTail[index] = dtd; + qhIdle = 1U; + } + } while (length); + + /* If the QH is not empty */ + if (!qhIdle) + { + /* If the prime bit is set, nothing need to do. */ + if (ehciState->registerBase->EPPRIME & primeBit) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } + + /* To safely a dtd */ + while (waitingSafelyAccess) + { + /* set the ATDTW flag to USBHS_USBCMD_REG. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ATDTW_MASK; + /* Read EPSR */ + epStatus = ehciState->registerBase->EPSR; + /* Wait the ATDTW bit set */ + if (ehciState->registerBase->USBCMD & USBHS_USBCMD_ATDTW_MASK) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the ATDTW bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ATDTW_MASK; + } + + /* If QH is empty or the endpoint is not primed, need to link current dtd head to the QH. */ + /* When the endpoint is not primed if qhIdle is zero, it means the QH is empty. */ + if ((qhIdle) || (!(epStatus & primeBit))) + { + ehciState->qh[index].nextDtdPointer = (uint32_t)dtdHard; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + ehciState->registerBase->EPPRIME = primeBit; + while (!(ehciState->registerBase->EPSR & primeBit)) + { + if (ehciState->registerBase->EPCOMPLETE & primeBit) + { + break; + } + else + { + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Initialize the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to enumeration type usb_controller_index_t. + * @param handle Pointer of the device handle, used to identify the device object is belonged to. + * @param ehciHandle It is out parameter, is used to return pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState; + uint32_t ehci_base[] = USBHS_BASE_ADDRS; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + usb_device_dcd_state_struct_t *dcdHSState; + uint32_t dcd_base[] = USBHSDCD_BASE_ADDRS; + usb_device_callback_message_struct_t message; +#endif + + if ((controllerId < kUSB_ControllerEhci0) || + ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= USB_DEVICE_CONFIG_EHCI) || + ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(ehci_base) / sizeof(uint32_t)))) + { + return kStatus_USB_ControllerNotFound; + } + + ehciState = &g_UsbDeviceEhciSate[controllerId - kUSB_ControllerEhci0]; + + ehciState->dtd = s_UsbDeviceEhciDtd[controllerId - kUSB_ControllerEhci0]; + ehciState->qh = (usb_device_ehci_qh_struct_t *)&qh_buffer[(controllerId - kUSB_ControllerEhci0) * 2048]; + + ehciState->controllerId = controllerId; + + ehciState->registerBase = (USBHS_Type *)ehci_base[controllerId - kUSB_ControllerEhci0]; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + ehciState->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); +#endif + +#endif + + /* Get the HW's endpoint count */ + ehciState->endpointCount = + (uint8_t)((ehciState->registerBase->DCCPARAMS & USBHS_DCCPARAMS_DEN_MASK) >> USBHS_DCCPARAMS_DEN_SHIFT); + + if (ehciState->endpointCount < USB_DEVICE_CONFIG_ENDPOINTS) + { + return kStatus_USB_Error; + } + ehciState->deviceHandle = (usb_device_struct_t *)handle; + + /* Clear the controller mode field and set to device mode. */ + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_CM_MASK; + ehciState->registerBase->USBMODE |= USBHS_USBMODE_CM(0x02U); + + /* Set the EHCI to default status. */ + USB_DeviceEhciSetDefaultState(ehciState); + *ehciHandle = (usb_device_controller_handle)ehciState; +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + dcdHSState = &s_UsbDeviceDcdHSState[controllerId - kUSB_ControllerEhci0]; + + dcdHSState->controllerId = controllerId; + + dcdHSState->dcdRegisterBase = (USBHSDCD_Type *)dcd_base[controllerId - kUSB_ControllerEhci0]; + + dcdHSState->deviceHandle = (usb_device_struct_t *)handle; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) + { + /* Device is connected to a host. */ + message.code = kUSB_DeviceNotifyAttach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize the USB device EHCI instance. + * + * This function de-initializes the USB device EHCI module. + * + * @param ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + /* Disable all interrupt. */ + ehciState->registerBase->USBINTR = 0U; + /* Stop the device functionality. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + /* Reset the controller. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RST_MASK; + + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_device_callback_message_struct_t message; + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t primeBit = + 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t index = + ((ep & USB_ENDPOINT_NUMBER_MASK) << 1U) | ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x07U); + + USB_OSA_SR_ALLOC(); + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + USB_OSA_ENTER_CRITICAL(); + + message.buffer = NULL; + message.length = USB_UNINITIALIZED_VAL_32; + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (currentDtd) + { + currentDtd->reservedUnion.originalBufferInfo.dtdInvalid = 1U; + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + if (!currentDtd->reservedUnion.originalBufferInfo.dtdInvalid) + { + break; + } + else + { + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + /* Flush the endpoint to stop a transfer. */ + do + { + /* Set the corresponding bit(s) in the EPFLUSH register */ + ehciState->registerBase->EPFLUSH |= primeBit; + + /* Wait until all bits in the EPFLUSH register are cleared. */ + while (ehciState->registerBase->EPFLUSH & primeBit) + { + } + /* + * Read the EPSR register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (ehciState->registerBase->EPSR & primeBit); + } + + /* Save the original buffer address. */ + if (NULL == message.buffer) + { + message.buffer = (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + + /* Remove the dtd from the dtd in-used queue. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = ep; + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + } + /* Clear the token field. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Save the dtd to the free queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + } + /* Get the next dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + if (!currentDtd) + { + /* Set the QH to empty. */ + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Control the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param type The selected item. Please refer to enumeration type usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, usb_device_control_type_t type, void *param) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_status_t error = kStatus_USB_Error; + uint16_t *temp16; + uint8_t *temp8; +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + usb_device_dcd_state_struct_t *dcdHSState; + dcdHSState = + &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; /*The hard code should be replaced*/ + usb_device_dcd_charging_time_t *deviceDcdTimingConfig = (usb_device_dcd_charging_time_t *)param; +#endif +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + usb_device_struct_t *deviceHandle; + uint64_t startTick; +#endif + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + deviceHandle = (usb_device_struct_t *)ehciState->deviceHandle; +#endif + + switch (type) + { + case kUSB_DeviceControlRun: + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlStop: + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlEndpointInit: + if (param) + { + error = USB_DeviceEhciEndpointInit(ehciState, (usb_device_endpoint_init_struct_t *)param); + } + break; + case kUSB_DeviceControlEndpointDeinit: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointDeinit(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointStall: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointStall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointUnstall: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointUnstall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlGetDeviceStatus: + if (param) + { + temp16 = (uint16_t *)param; + *temp16 = (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT)) +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + | (deviceHandle->remotewakeup << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)) +#endif + ; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetEndpointStatus: + if (param) + { + usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param; + uint8_t ep = (endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + ((endpointStatus->endpointAddress) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (ep < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (ep) + { + endpointStatus->endpointStatus = (ehciState->registerBase->EPCR[ep - 1U] & + (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? + kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle; + } + else + { + endpointStatus->endpointStatus = + (ehciState->registerBase->EPCR0 & (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? + kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle; + } + error = kStatus_USB_Success; + } + } + break; + case kUSB_DeviceControlSetDeviceAddress: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->DEVICEADDR = (((uint32_t)(*temp8)) << USBHS_DEVICEADDR_USBADR_SHIFT); + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetSynchFrame: + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U) + case kUSB_DeviceControlResume: +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; + startTick = deviceHandle->hwTick; + while ((deviceHandle->hwTick - startTick) < 10) + { + __ASM("nop"); + } + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_FPR_MASK; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */ + case kUSB_DeviceControlSuspend: + ehciState->registerBase->OTGSC |= 0x007F0000U; + ehciState->registerPhyBase->PWD = 0xFFFFFFFF; + /* ehciState->registerBase->OTGCTL |= ((1U<<10) | (1U<<17) | (1U<<16)); */ + while (ehciState->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) + { + __ASM("nop"); + } + /* ehciState->registerPhyBase->CTRL |= ((1U << 21) | (1U << 22) | (1U << 23)); */ + ehciState->registerBase->USBSTS |= USBHS_USBSTS_SRI_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK | USBPHY_CTRL_ENIDCHG_WKUP_MASK | + USBPHY_CTRL_ENDPDMCHG_WKUP_MASK | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + ehciState->isSuspending = 1U; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + case kUSB_DeviceControlSetDefaultStatus: + for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++) + { + USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_IN << 0x07U))); + USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_OUT << 0x07U))); + } + USB_DeviceEhciSetDefaultState(ehciState); + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlGetSpeed: + if (param) + { + temp8 = (uint8_t *)param; + *temp8 = ehciState->speed; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetOtgStatus: + break; + case kUSB_DeviceControlSetOtgStatus: + break; +#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceControlSetTestMode: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->PORTSC1 |= ((uint32_t)(*temp8) << 16U); + error = kStatus_USB_Success; + } + break; +#endif +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + case kUSB_DeviceControlDcdInitModule: + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + dcdHSState->dcdRegisterBase->TIMER0 = USBDCD_TIMER0_TSEQ_INIT(deviceDcdTimingConfig->dcdSeqInitTime); + dcdHSState->dcdRegisterBase->TIMER1 = USBDCD_TIMER1_TDCD_DBNC(deviceDcdTimingConfig->dcdDbncTime); + dcdHSState->dcdRegisterBase->TIMER1 |= USBDCD_TIMER1_TVDPSRC_ON(deviceDcdTimingConfig->dcdDpSrcOnTime); + dcdHSState->dcdRegisterBase->TIMER2_BC12 = + USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(deviceDcdTimingConfig->dcdTimeWaitAfterPrD); + dcdHSState->dcdRegisterBase->TIMER2_BC12 |= + USBDCD_TIMER2_BC12_TVDMSRC_ON(deviceDcdTimingConfig->dcdTimeDMSrcOn); + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IE_MASK; + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_BC12_MASK; + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_START_MASK; + break; + case kUSB_DeviceControlDcdDeinitModule: + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + break; +#endif + + default: + break; + } + + return error; +} + +/*! + * @brief Handle the EHCI device interrupt. + * + * The function is used to handle the EHCI device interrupt. + * + * @param deviceHandle The device handle got from USB_DeviceInit. + * + */ +void USB_DeviceEhciIsrFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + uint32_t status; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + + if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) + { + if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIR_MASK) + { + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + } + } + else + { + } + +#else + if (ehciState->registerBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) + { + if (ehciState->registerBase->USBGENCTRL & (1U << 8)) + { + ehciState->registerBase->USBGENCTRL &= ~(1U << 8); + ehciState->registerBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + } + } + else + { + } +#endif + +#endif + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSVIS_MASK) + { + usb_device_callback_message_struct_t message; + + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIS_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) + { + /* Device is connected to a host. */ + message.code = kUSB_DeviceNotifyAttach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + else + { + /* Device is disconnected from a host. */ + message.code = kUSB_DeviceNotifyDetach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + status = ehciState->registerBase->USBSTS; + status &= ehciState->registerBase->USBINTR; + + ehciState->registerBase->USBSTS = status; + +#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U) + if (status & USBHS_USBSTS_UEI_MASK) + { + /* Error interrupt */ + USB_DeviceEhciInterruptError(ehciState); + } +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + + if (status & USBHS_USBSTS_URI_MASK) + { + /* Reset interrupt */ + USB_DeviceEhciInterruptReset(ehciState); + } + + if (status & USBHS_USBSTS_UI_MASK) + { + /* Token done interrupt */ + USB_DeviceEhciInterruptTokenDone(ehciState); + } + + if (status & USBHS_USBSTS_PCI_MASK) + { + /* Port status change interrupt */ + USB_DeviceEhciInterruptPortChange(ehciState); + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if (status & USBHS_USBSTS_SLI_MASK) + { + /* Suspend interrupt */ + USB_DeviceEhciInterruptSuspend(ehciState); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + + if (status & USBHS_USBSTS_SRI_MASK) + { + /* Sof interrupt */ + USB_DeviceEhciInterruptSof(ehciState); + } +} + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +void USB_DeviceDcdHSIsrFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + usb_device_dcd_state_struct_t *dcdHSState; + uint32_t status; + uint32_t chargerType; + usb_device_callback_message_struct_t message; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + + dcdHSState = &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; + + status = dcdHSState->dcdRegisterBase->STATUS; + + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IACK_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + if (status & USBDCD_STATUS_ERR_MASK) + { + if (status & USBDCD_STATUS_TO_MASK) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDcdTimeOut; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDcdUnknownPortType; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + } + else + { + switch (status & USBDCD_STATUS_SEQ_STAT_MASK) + { + case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargingPortDetectionCompleted): + chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; + if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionStandardHost)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifySDPDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) + { + message.code = kUSB_DeviceNotifyChargingPortDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + break; + case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargerTypeDetectionCompleted): + chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; + if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyChargingHostDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionDedicatedCharger)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDedicatedChargerDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + break; + + default: + break; + } + } +} +#endif + +#endif /* USB_DEVICE_CONFIG_EHCI */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_ehci.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_ehci.h new file mode 100644 index 0000000000..869e063263 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/device/usb_device_ehci.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_EHCI_H__ +#define __USB_DEVICE_EHCI_H__ + +#include + +/*! + * @addtogroup usb_device_controller_ehci_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The maximum value of ISO type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of interrupt type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_INTERUPT_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of bulk type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_BULK_MAX_PACKET_SIZE (512U) + +/*! @brief The maximum value of control type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_CONTROL_MAX_PACKET_SIZE (64U) + +/*! @brief EHCI state structure */ +typedef struct _usb_device_ehci_state_struct +{ + usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object is belonged to */ + USBHS_Type *registerBase; /*!< The base address of the register */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif +#endif + usb_device_ehci_qh_struct_t *qh; /*!< The QH structure base address */ + usb_device_ehci_dtd_struct_t *dtd; /*!< The DTD structure base address */ + usb_device_ehci_dtd_struct_t *dtdFree; /*!< The idle DTD list head */ + usb_device_ehci_dtd_struct_t + *dtdHard[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list head for each endpoint */ + usb_device_ehci_dtd_struct_t + *dtdTail[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list tail for each endpoint */ + int8_t dtdCount; /*!< The idle DTD node count */ + uint8_t endpointCount; /*!< The endpoint number of EHCI */ + uint8_t isResetting; /*!< Whether a PORT reset is occurring or not */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t speed; /*!< Current speed of EHCI */ + uint8_t isSuspending; /*!< Is suspending of the PORT */ +} usb_device_ehci_state_struct_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +typedef struct _usb_device_dcd_state_struct +{ + usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object belongs to */ + USBHSDCD_Type *dcdRegisterBase; /*!< The base address of the dcd module */ + uint8_t controllerId; /*!< Controller ID */ +} usb_device_dcd_state_struct_t; +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name USB device EHCI functions + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t. + * @param[in] handle Pointer of the device handle used to identify the device object is belonged to. + * @param[out] ehciHandle An out parameter used to return the pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle); + +/*! + * @brief Deinitializes the USB device EHCI instance. + * + * This function deinitializes the USB device EHCI module. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle); + +/*! + * @brief Sends data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. + * @param[in] length The data length to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value means whether the sending request is successful or not. The transfer completion is indicated + * by the + * corresponding callback function. + * Currently, only one transfer request can be supported for a specific endpoint. + * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer can begin only when the previous transfer is done (a notification is received through the + * endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep); + +/*! + * @brief Controls the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] type The selected item. See enumeration type usb_device_control_type_t. + * @param[in,out] param The parameter type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, + usb_device_control_type_t type, + void *param); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __USB_DEVICE_EHCI_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host.h new file mode 100644 index 0000000000..53be402cd3 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host.h @@ -0,0 +1,726 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_H_ +#define _USB_HOST_H_ + +#include +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +struct _usb_host_transfer; /* for cross reference */ + +/*! + * @addtogroup usb_host_drv + * @{ + */ + +/*! @brief USB host class handle type define */ +typedef void *usb_host_class_handle; + +/*! @brief USB host controller handle type define */ +typedef void *usb_host_controller_handle; + +/*! @brief USB host configuration handle type define */ +typedef void *usb_host_configuration_handle; + +/*! @brief USB host interface handle type define */ +typedef void *usb_host_interface_handle; + +/*! @brief USB host pipe handle type define */ +typedef void *usb_host_pipe_handle; + +/*! @brief Event codes for device attach/detach */ +typedef enum _usb_host_event +{ + kUSB_HostEventAttach = 1U, /*!< Device is attached */ + kUSB_HostEventDetach, /*!< Device is detached */ + kUSB_HostEventEnumerationDone, /*!< Device's enumeration is done and the device is supported */ + kUSB_HostEventNotSupported, /*!< Device's enumeration is done and the device is not supported */ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + kUSB_HostEventNotSuspended, /*!< Suspend failed */ + kUSB_HostEventSuspended, /*!< Suspend successful */ + kUSB_HostEventNotResumed, /*!< Resume failed */ + kUSB_HostEventDetectResume, /*!< Detect resume signal */ + kUSB_HostEventResumed, /*!< Resume successful */ + kUSB_HostEventL1Sleeped, /*!< L1 Sleep successful,state transition was successful (ACK) */ + kUSB_HostEventL1SleepNYET, /*!< Device was unable to enter the L1 state at this time (NYET) */ + kUSB_HostEventL1SleepNotSupport, /*!< Device does not support the L1 state (STALL) */ + kUSB_HostEventL1SleepError, /*!< Device failed to respond or an error occurred */ + kUSB_HostEventL1NotResumed, /*!< Resume failed */ + kUSB_HostEventL1DetectResume, /*!< Detect resume signal */ + kUSB_HostEventL1Resumed, /*!< Resume successful */ +#endif +} usb_host_event_t; + +/*! @brief USB host device information code */ +typedef enum _usb_host_dev_info +{ + kUSB_HostGetDeviceAddress = 1U, /*!< Device's address */ + kUSB_HostGetDeviceHubNumber, /*!< Device's first hub address */ + kUSB_HostGetDevicePortNumber, /*!< Device's first hub port number */ + kUSB_HostGetDeviceSpeed, /*!< Device's speed */ + kUSB_HostGetDeviceHSHubNumber, /*!< Device's first high-speed hub address */ + kUSB_HostGetDeviceHSHubPort, /*!< Device's first high-speed hub number */ + kUSB_HostGetDeviceLevel, /*!< Device's hub level */ + kUSB_HostGetHostHandle, /*!< Device's host handle */ + kUSB_HostGetDeviceControlPipe, /*!< Device's control pipe handle */ + kUSB_HostGetDevicePID, /*!< Device's PID */ + kUSB_HostGetDeviceVID, /*!< Device's VID */ + kUSB_HostGetHubThinkTime, /*!< Device's hub total think time */ + kUSB_HostGetDeviceConfigIndex, /*!< Device's running zero-based config index */ + kUSB_HostGetConfigurationDes, /*!< Device's configuration descriptor pointer */ + kUSB_HostGetConfigurationLength, /*!< Device's configuration descriptor pointer */ +} usb_host_dev_info_t; + +/*! + * @brief Host callback function typedef. + * + * This callback function is used to notify application device attach/detach event. + * This callback pointer is passed when initializing the host. + * + * @param deviceHandle The device handle, which indicates the attached device. + * @param configurationHandle The configuration handle contains the attached device's configuration information. + * @param event_code The callback event code; See the enumeration host_event_t. + * + * @return A USB error code or kStatus_USB_Success. + * @retval kStatus_USB_Success Application handles the attached device successfully. + * @retval kStatus_USB_NotSupported Application don't support the attached device. + * @retval kStatus_USB_Error Application handles the attached device falsely. + */ +typedef usb_status_t (*host_callback_t)(usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode); + +/*! + * @brief Transfer callback function typedef. + * + * This callback function is used to notify the upper layer the result of the transfer. + * This callback pointer is passed when calling the send/receive APIs. + * + * @param param The parameter pointer, which is passed when calling the send/receive APIs. + * @param data The data buffer pointer. + * @param data_len The result data length. + * @param status A USB error code or kStatus_USB_Success. + */ +typedef void (*transfer_callback_t)(void *param, uint8_t *data, uint32_t dataLen, usb_status_t status); + +/*! + * @brief Host stack inner transfer callback function typedef. + * + * This callback function is used to notify the upper layer the result of a transfer. + * This callback pointer is passed when initializing the structure usb_host_transfer_t. + * + * @param param The parameter pointer, which is passed when calling the send/receive APIs. + * @param transfer The transfer information; See the structure usb_host_transfer_t. + * @param status A USB error code or kStatus_USB_Success. + */ +typedef void (*host_inner_transfer_callback_t)(void *param, struct _usb_host_transfer *transfer, usb_status_t status); + +/*! @brief USB host endpoint information structure */ +typedef struct _usb_host_ep +{ + usb_descriptor_endpoint_t *epDesc; /*!< Endpoint descriptor pointer*/ + uint8_t *epExtension; /*!< Endpoint extended descriptor pointer*/ + uint16_t epExtensionLength; /*!< Extended descriptor length*/ +} usb_host_ep_t; + +/*! @brief USB host interface information structure */ +typedef struct _usb_host_interface +{ + usb_host_ep_t epList[USB_HOST_CONFIG_INTERFACE_MAX_EP]; /*!< Endpoint array*/ + usb_descriptor_interface_t *interfaceDesc; /*!< Interface descriptor pointer*/ + uint8_t *interfaceExtension; /*!< Interface extended descriptor pointer*/ + uint16_t interfaceExtensionLength; /*!< Extended descriptor length*/ + uint8_t interfaceIndex; /*!< The interface index*/ + uint8_t alternateSettingNumber; /*!< The interface alternate setting value*/ + uint8_t epCount; /*!< Interface's endpoint number*/ +} usb_host_interface_t; + +/*! @brief USB host configuration information structure */ +typedef struct _usb_host_configuration +{ + usb_host_interface_t interfaceList[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interface array*/ + usb_descriptor_configuration_t *configurationDesc; /*!< Configuration descriptor pointer*/ + uint8_t *configurationExtension; /*!< Configuration extended descriptor pointer*/ + uint16_t configurationExtensionLength; /*!< Extended descriptor length*/ + uint8_t interfaceCount; /*!< The configuration's interface number*/ +} usb_host_configuration_t; + +/*! @brief USB host pipe common structure */ +typedef struct _usb_host_pipe +{ + struct _usb_host_pipe *next; /*!< Link the idle pipes*/ + usb_device_handle deviceHandle; /*!< This pipe's device's handle*/ + uint16_t currentCount; /*!< For KHCI transfer*/ + uint16_t nakCount; /*!< Maximum NAK count*/ + uint16_t maxPacketSize; /*!< Maximum packet size*/ + uint16_t interval; /*!< FS/LS: frame unit; HS: micro-frame unit*/ + uint8_t open; /*!< 0 - closed, 1 - open*/ + uint8_t nextdata01; /*!< Data toggle*/ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t direction; /*!< Pipe direction*/ + uint8_t pipeType; /*!< Pipe type, for example USB_ENDPOINT_BULK*/ + uint8_t numberPerUframe; /*!< Transaction number per micro-frame*/ +} usb_host_pipe_t; + +/*! @brief USB host transfer structure */ +typedef struct _usb_host_transfer +{ + struct _usb_host_transfer *next; /*!< The next transfer structure*/ + uint8_t *transferBuffer; /*!< Transfer data buffer*/ + uint32_t transferLength; /*!< Transfer data length*/ + uint32_t transferSofar; /*!< Length transferred so far*/ + host_inner_transfer_callback_t callbackFn; /*!< Transfer callback function*/ + void *callbackParam; /*!< Transfer callback parameter*/ + usb_host_pipe_t *transferPipe; /*!< Transfer pipe pointer*/ + usb_setup_struct_t *setupPacket; /*!< Set up packet buffer*/ + uint8_t direction; /*!< Transfer direction; it's values are USB_OUT or USB_IN*/ + uint8_t setupStatus; /*!< Set up the transfer status*/ + union + { + uint32_t unitHead; /*!< xTD head for this transfer*/ + int32_t transferResult; /*!< KHCI transfer result */ + } union1; + + union + { + uint32_t unitTail; /*! 0U)) +/*! + * @brief Send a bus or device suspend request. + * + * This function is used to send a bus or device suspend request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief Send a bus or device resume request. + * + * This function is used to send a bus or device resume request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); +#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Send a bus or device suspend request. + * + * This function is used to send a bus or device suspend request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + *@param[in] sleeptype Bus suspend or single device suspend. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleeptype); + +/*! + * @brief Send a bus or device resume request. + * + * This function is used to send a bus or device resume request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * *@param[in] sleeptype Bus suspend or single device suspend. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType); +/*! + * @brief Update the lpm param. + * + * The function is used to configuure the lpm token. + * + * @param[in] hostHandle The host handle. + * @param[in] lpmParam HIRD vaule and whether enable remotewakeup. + * + */ +extern usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam); +#endif +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] hostHandle The host handle. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick); + +#endif + +/*! @}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _USB_HOST_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_devices.c b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_devices.c new file mode 100644 index 0000000000..42b16e071e --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_devices.c @@ -0,0 +1,1414 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +#include "usb_host_hub.h" +#endif /* USB_HOST_CONFIG_HUB */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief enumeration transfer callback function. + * + * @param param callback parameter. + * @param transfer the transfer. + * @param status transfer result status. + */ +static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status); + +/*! + * @brief process the new step state. + * + * @param deviceInstance device instance pointer. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance); + +/*! + * @brief process the previous step transfer result. + * + * @param deviceInstance device instance pointer. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance); + +/*! + * @brief notify the application event, the callback is registered when initializing host. + * + * @param deviceInstance device instance pointer. + * @param eventCode event code. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode); + +/*! + * @brief allocate one address. + * + * @param hostInstance host instance pointer. + * + * @return address, 0 is invalid. + */ +static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance); + +/*! + * @brief release one address. + * + * @param hostInstance host instance pointer. + * @param address releasing address. + */ +static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address); + +/*! + * @brief release device resource. + * + * @param hostInstance host instance pointer. + * @param deviceInstance device instance pointer. + */ +static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, + usb_host_device_instance_t *deviceInstance); + +/*! + * @brief parse device configuration descriptor. + * + * @param deviceHandle device handle. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle); + +/*! + * @brief remove device instance from host device list. + * + * @param hostHandle host instance handle. + * @param deviceHandle device handle. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief control the bus. + * + * This function control the host bus. + * + * @param[in] hostHandle the host handle. + * @param[in] controlType the control code, please reference to bus_event_t. + * + * @retval kStatus_USB_Success control successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. + */ +static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType); + +extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +extern usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +extern usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + uint8_t *buffer, + uint32_t bufferLen); + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + +extern usb_status_t USB_HostHubDeviceEvent(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode); + +extern uint32_t USB_HostHubGetHsHubNumber(usb_host_handle hostHandle, uint8_t parentHubNo); + +extern uint32_t USB_HostHubGetHsHubPort(usb_host_handle hostHandle, uint8_t parentHubNo, uint8_t parentPortNo); + +extern usb_status_t USB_HostHubRemovePort(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); + +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +extern usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; + +/*! @brief enumeration step process array */ +static const usb_host_enum_process_entry_t s_EnumEntries[] = \ +{ + /* kStatus_dev_initial */ + { + 0, 0, NULL, + }, + /* kStatus_DEV_GetDes8 */ + { + kStatus_DEV_SetAddress, kStatus_DEV_GetDes8, USB_HostProcessCallback, + }, + /* kStatus_DEV_SetAddress */ + { + kStatus_DEV_GetDes, kStatus_DEV_SetAddress, USB_HostProcessCallback, + }, + /* kStatus_DEV_GetDes */ + { + kStatus_DEV_GetCfg9, kStatus_DEV_GetDes, NULL, + }, + /* kStatus_DEV_GetCfg9 */ + { + kStatus_DEV_GetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, + }, + /* kStatus_DEV_GetCfg */ + { + kStatus_DEV_SetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, + }, + /* kStatus_DEV_SetCfg */ + { + kStatus_DEV_EnumDone, kStatus_DEV_SetCfg, NULL, + }, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) +{ + uint8_t nextStep = 0; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)param; + + USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */ + + if (status == kStatus_USB_Success) + { + nextStep = 1; + } + else if (status == kStatus_USB_TransferStall) + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("no response from device\r\n"); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ + if (deviceInstance->stallRetries > 0) /* retry same transfer when stall */ + { + deviceInstance->stallRetries--; + } + else /* process next state when all retries stall */ + { + nextStep = 1; + } + } + else if (status == kStatus_USB_TransferCancel) + { + return; + } + else + { + if (deviceInstance->enumRetries > 0) /* next whole retry */ + { + deviceInstance->enumRetries--; + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + deviceInstance->configurationValue = 0; + deviceInstance->state = kStatus_DEV_GetDes8; + } + else + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("Device No Response\r\n"); +#endif + return; + } + } + + if (nextStep == 1) + { + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + if (s_EnumEntries[deviceInstance->state - 1].process == NULL) + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; /* next state */ + } + else + { + status = s_EnumEntries[deviceInstance->state - 1].process( + deviceInstance); /* process the previous state result */ + if (status == kStatus_USB_Success) /* process success */ + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; + } + else if (status == kStatus_USB_Retry) /* need retry */ + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].retryState; + } + else if (status == kStatus_USB_NotSupported) /* device don't suport by the application */ + { + return; /* unrecoverable fail */ + } + else /* process error, next retry */ + { + if (deviceInstance->enumRetries > 0) /* next whole retry */ + { + deviceInstance->enumRetries--; + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + deviceInstance->configurationValue = 0; + deviceInstance->state = kStatus_DEV_GetDes8; + } + else + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("Device No Response\r\n"); +#endif + return; /* unrecoverable fail */ + } + } + } + } + + if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success) /* process the new state */ + { +#ifdef HOST_ECHO + usb_echo("enumation setup error\r\n"); +#endif + return; + } +} + +static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_process_descriptor_param_t getDescriptorParam; + usb_host_transfer_t *transfer; + + /* malloc transfer */ + if (deviceInstance->state != kStatus_DEV_EnumDone) + { + if (USB_HostMallocTransfer(deviceInstance->hostHandle, &transfer) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("error to get transfer\r\n"); +#endif + return kStatus_USB_Error; + } + transfer->callbackFn = USB_HostEnumerationTransferCallback; + transfer->callbackParam = deviceInstance; + + /* reset transfer fields */ + transfer->setupPacket->bmRequestType = 0x00; + transfer->setupPacket->wIndex = 0; + transfer->setupPacket->wLength = 0; + transfer->setupPacket->wValue = 0; + } + + switch (deviceInstance->state) + { + case kStatus_DEV_GetDes8: + case kStatus_DEV_GetDes: /* get descriptor state */ + getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); + if (deviceInstance->state == kStatus_DEV_GetDes8) + { + getDescriptorParam.descriptorLength = 8; + } + getDescriptorParam.descriptorBuffer = (uint8_t *)deviceInstance->deviceDescriptor; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; + getDescriptorParam.descriptorIndex = 0; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + case kStatus_DEV_SetAddress: /* set address state */ + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_ADDRESS; + status = USB_HostStandardSetAddress(deviceInstance, transfer, &deviceInstance->allocatedAddress); + break; + + case kStatus_DEV_GetCfg9: /* get 9 bytes configuration state */ + getDescriptorParam.descriptorBuffer = deviceInstance->enumBuffer; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; + getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; + getDescriptorParam.descriptorLength = 9; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + + case kStatus_DEV_GetCfg: /* get configuration state */ + getDescriptorParam.descriptorBuffer = deviceInstance->configurationDesc; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; + getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; + getDescriptorParam.descriptorLength = deviceInstance->configurationLen; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + + case kStatus_DEV_SetCfg: /* set configuration state */ + transfer->setupPacket->wValue = + USB_SHORT_TO_LITTLE_ENDIAN(deviceInstance->configuration.configurationDesc->bConfigurationValue); + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_CONFIGURATION; + status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0); + break; + + case kStatus_DEV_EnumDone: /* enumeration done state */ + status = USB_HostNotifyDevice(deviceInstance, + kUSB_HostEventEnumerationDone); /* notify device enumeration done */ + if (status == kStatus_USB_Success) + { + deviceInstance->state = kStatus_DEV_AppUsed; + } + break; + + default: + break; + } + + return status; +} + +static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance) +{ + usb_host_pipe_t *pipe = (usb_host_pipe_t *)deviceInstance->controlPipe; + usb_status_t status = kStatus_USB_Success; + usb_descriptor_configuration_t *configureDesc; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + + switch (deviceInstance->state) + { + case kStatus_DEV_GetDes8: /* process get 8 bytes descriptor result */ + pipe->maxPacketSize = deviceInstance->deviceDescriptor->bMaxPacketSize0; + hostInstance->controllerTable->controllerIoctl( + hostInstance->controllerHandle, kUSB_HostUpdateControlPacketSize, deviceInstance->controlPipe); + break; + + case kStatus_DEV_SetAddress: /* process set address result */ + deviceInstance->setAddress = deviceInstance->allocatedAddress; + hostInstance->controllerTable->controllerIoctl( + hostInstance->controllerHandle, kUSB_HostUpdateControlEndpointAddress, deviceInstance->controlPipe); + break; + + case kStatus_DEV_GetDes: /* process set address result */ + /* NULL */ + break; + + case kStatus_DEV_GetCfg9: /* process get 9 bytes configuration result */ + configureDesc = (usb_descriptor_configuration_t *)&deviceInstance->enumBuffer[0]; + + deviceInstance->configurationLen = USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(configureDesc->wTotalLength); + if (deviceInstance->configurationDesc != NULL) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->configurationDesc); +#else + USB_OsaMemoryFree(deviceInstance->configurationDesc); +#endif + deviceInstance->configurationDesc = NULL; + } + /* for KHCI, the start address and the length should be 4 byte align */ + if ((deviceInstance->configurationLen & 0x03) != 0) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + deviceInstance->configurationDesc = + (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4, USB_CACHE_LINESIZE); +#else + deviceInstance->configurationDesc = + (uint8_t *)USB_OsaMemoryAllocate((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4); +#endif + } + else + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + deviceInstance->configurationDesc = + (uint8_t *)SDK_Malloc(deviceInstance->configurationLen, USB_CACHE_LINESIZE); +#else + deviceInstance->configurationDesc = (uint8_t *)USB_OsaMemoryAllocate(deviceInstance->configurationLen); +#endif + } + if (deviceInstance->configurationDesc == NULL) + { + return kStatus_USB_Error; + } + break; + + case kStatus_DEV_GetCfg: /* process get cofiguration result */ + if (((usb_descriptor_configuration_t *)deviceInstance->configurationDesc)->bMaxPower > + USB_HOST_CONFIG_MAX_POWER) + { + return kStatus_USB_Error; + } + deviceInstance->configurationValue++; + if (USB_HostParseDeviceConfigurationDescriptor(deviceInstance) != + kStatus_USB_Success) /* parse configuration descriptor */ + { + return kStatus_USB_Error; + } + + status = USB_HostNotifyDevice(deviceInstance, kUSB_HostEventAttach); + + if (status != kStatus_USB_Success) + { + /* next configuration */ + if (deviceInstance->configurationValue < deviceInstance->deviceDescriptor->bNumConfigurations) + { + return kStatus_USB_Retry; + } + else + { + USB_HostNotifyDevice(deviceInstance, + kUSB_HostEventNotSupported); /* notify application device is not supported */ + return kStatus_USB_NotSupported; + } + } + break; + + case kStatus_DEV_SetCfg: + /* NULL */ + break; + + default: + break; + } + + return status; +} + +static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode) +{ + usb_host_instance_t *hostInstance; + usb_status_t status1 = kStatus_USB_Error; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + usb_status_t status2 = kStatus_USB_Error; + uint8_t haveHub; + uint8_t haveNoHub; + uint8_t interfaceIndex; +#endif /* USB_HOST_CONFIG_HUB */ + + if (deviceInstance == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + haveHub = 0; + haveNoHub = 0; + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (((usb_descriptor_interface_t *)deviceInstance->configuration.interfaceList[interfaceIndex].interfaceDesc) + ->bInterfaceClass == USB_HOST_HUB_CLASS_CODE) + { + haveHub = 1; + } + else + { + haveNoHub = 1; + } + } + + if ((haveNoHub == 1) && (hostInstance->deviceCallback != NULL)) + { + status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, + eventCode); /* notify application event */ + } + if (haveHub) + { + status2 = USB_HostHubDeviceEvent(hostInstance, deviceInstance, &deviceInstance->configuration, + eventCode); /* notify hub event */ + } + + if ((status1 == kStatus_USB_Success) || (status2 == kStatus_USB_Success)) /* the device is supported */ + { + return kStatus_USB_Success; + } + else if (eventCode == kUSB_HostEventAttach) /* attach event */ + { + status1 = kStatus_USB_NotSupported; + } + else + { + status1 = kStatus_USB_Error; + } +#else + if (hostInstance->deviceCallback != NULL) + { + status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, + eventCode); /* call host callback function */ + } +#endif + return status1; +} + +static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance) +{ + uint8_t address = 0; + uint8_t addressIndex; + uint8_t addressBitIndex; + for (addressIndex = 0; addressIndex < 8; ++addressIndex) /* find the idle address postion byte */ + { + if (hostInstance->addressBitMap[addressIndex] != 0xFF) + { + break; + } + } + if (addressIndex < 8) + { + for (addressBitIndex = 0; addressBitIndex < 8; ++addressBitIndex) /* find the idle address position bit */ + { + if (!(hostInstance->addressBitMap[addressIndex] & (0x01u << addressBitIndex))) + { + hostInstance->addressBitMap[addressIndex] |= (0x01u << addressBitIndex); /* set the allocated bit */ + address = addressIndex * 8 + addressBitIndex + 1; /* the address minimum is 1 */ + break; + } + } + } + return address; +} + +static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address) +{ + USB_HostLock(); + hostInstance->addressBitMap[(uint32_t)(address - 1) >> 3] &= + (~(0x01u << (((uint32_t)address - 1) & 0x07U))); /* reset the allocated bit */ + USB_HostUnlock(); +} + +static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *currentInstance; + usb_host_device_instance_t *prevInstance; + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* search and remove device instance */ + prevInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + if (prevInstance == deviceHandle) + { + hostInstance->deviceList = prevInstance->next; + return kStatus_USB_Success; + } + else + { + currentInstance = prevInstance->next; + } + + while (currentInstance != NULL) + { + if (currentInstance == deviceHandle) + { + prevInstance->next = currentInstance->next; + return kStatus_USB_Success; + } + prevInstance = currentInstance; + currentInstance = currentInstance->next; + } + + return kStatus_USB_Success; +} + +static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb_host_device_instance_t *deviceInstance) +{ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + uint8_t level = 0; +#endif + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (deviceInstance == hostInstance->suspendedDevice) + { + hostInstance->suspendedDevice = NULL; + } +#endif + /* release device's address */ + if (deviceInstance->setAddress != 0) + { + USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->setAddress); + } + else + { + if (deviceInstance->allocatedAddress != 0) + { + USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->allocatedAddress); + } + } + + /* close control pipe */ + if (deviceInstance->controlPipe != NULL) + { + USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); + if (USB_HostClosePipe(hostInstance, deviceInstance->controlPipe) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("error when close pipe\r\n"); +#endif + } + deviceInstance->controlPipe = NULL; + } + + /* free configuration buffer */ + if (deviceInstance->configurationDesc != NULL) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->configurationDesc); +#else + USB_OsaMemoryFree(deviceInstance->configurationDesc); +#endif + } + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + level = deviceInstance->level; +#endif +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(deviceInstance->deviceDescriptor); +#endif + /* free device instance buffer */ + USB_OsaMemoryFree(deviceInstance); + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + /* enable controller attach if root hub */ + if (level == 1) + { + USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); + } +#else + /* enable controller attach */ + USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); +#endif +} + +static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + uint32_t endPos; + usb_descriptor_union_t *unionDes; + usb_host_interface_t *interfaceParse = NULL; + usb_host_ep_t *epParse; + uint8_t *buffer; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidParameter; + } + + buffer = (uint8_t *)&deviceInstance->configuration; + /* clear the previous parse result, note: end_pos means buffer index here*/ + for (endPos = 0; endPos < sizeof(usb_host_configuration_t); endPos++) + { + buffer[endPos] = 0; + } + for (endPos = 0; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos) + { + deviceInstance->interfaceStatus[endPos] = 0; + } + + /* parse configuration descriptor */ + unionDes = (usb_descriptor_union_t *)deviceInstance->configurationDesc; + endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen); + + if ((unionDes->common.bLength == USB_DESCRIPTOR_LENGTH_CONFIGURE) && + (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_CONFIGURE)) + { + /* configuration descriptor */ + deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)unionDes; + deviceInstance->configuration.configurationExtensionLength = 0; + deviceInstance->configuration.configurationExtension = NULL; + deviceInstance->configuration.interfaceCount = 0; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (deviceInstance->configuration.configurationExtension == NULL) + { + deviceInstance->configuration.configurationExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + deviceInstance->configuration.configurationExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* interface descriptor */ + deviceInstance->configuration.interfaceCount = 0; + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (unionDes->interface.bAlternateSetting == 0x00) + { + if (deviceInstance->configuration.interfaceCount >= USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE) + { +#ifdef HOST_ECHO + usb_echo( + "Unsupported Device attached\r\n too many interfaces in one configuration, please increase " + "the USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE value\n"); +#endif + return kStatus_USB_Error; + } + interfaceParse = + &deviceInstance->configuration.interfaceList[deviceInstance->configuration.interfaceCount]; + deviceInstance->configuration.interfaceCount++; + interfaceParse->alternateSettingNumber = 0; + interfaceParse->epCount = 0; + interfaceParse->interfaceDesc = &unionDes->interface; + interfaceParse->interfaceExtensionLength = 0; + interfaceParse->interfaceExtension = NULL; + interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber; + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { + if (interfaceParse->interfaceExtension == NULL) + { + interfaceParse->interfaceExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* endpoint descriptor */ + if (interfaceParse->interfaceDesc->bNumEndpoints != 0) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || + (interfaceParse->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) + { +#ifdef HOST_ECHO + usb_echo("interface descriptor error\n"); +#endif + return kStatus_USB_Error; + } + for (; interfaceParse->epCount < interfaceParse->interfaceDesc->bNumEndpoints; + (interfaceParse->epCount)++) + { + if (((uint32_t)unionDes >= endPos) || + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { +#ifdef HOST_ECHO + usb_echo("endpoint descriptor error\n"); +#endif + return kStatus_USB_Error; + } + epParse = (usb_host_ep_t *)&interfaceParse->epList[interfaceParse->epCount]; + epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; + epParse->epExtensionLength = 0; + epParse->epExtension = NULL; + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) + { + if (epParse->epExtension == NULL) + { + epParse->epExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + epParse->epExtensionLength += unionDes->common.bLength; + unionDes = + (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + } + else + { + if (interfaceParse == NULL) + { + return kStatus_USB_Error; /* in normal situation this cannot reach */ + } + interfaceParse->alternateSettingNumber++; + if (interfaceParse->interfaceExtension == NULL) + { + interfaceParse->interfaceExtension = (uint8_t *)unionDes; + } + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) + { + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + else + { + return kStatus_USB_Error; + } + } + } + + for (endPos = 0; endPos < deviceInstance->configuration.interfaceCount; ++endPos) + { + deviceInstance->interfaceStatus[endPos] = kStatus_interface_Attached; + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, + uint8_t speed, + uint8_t hubNumber, + uint8_t portNumber, + uint8_t level, + usb_device_handle *deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *newInstance; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + usb_host_device_instance_t *currentInstance; +#endif + uint8_t address; + usb_host_pipe_init_t pipeInit; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + +/* check whether is the device attached? */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + currentInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (currentInstance != NULL) + { + if ((currentInstance->hubNumber == hubNumber) && (currentInstance->portNumber == portNumber)) + { + *deviceHandle = NULL; +#ifdef HOST_ECHO + usb_echo("device has attached\r\n"); +#endif + return kStatus_USB_Busy; + } + else + { + currentInstance = currentInstance->next; + } + } +#else + if (hostInstance->deviceList != NULL) + { + *deviceHandle = NULL; + usb_echo("device has attached\r\n"); + return kStatus_USB_Busy; + } +#endif + + /* Allocate new device instance */ + newInstance = (usb_host_device_instance_t *)USB_OsaMemoryAllocate(sizeof(usb_host_device_instance_t)); + if (newInstance == NULL) + { +#ifdef HOST_ECHO + usb_echo("allocate dev instance fail\r\n"); +#endif + return kStatus_USB_AllocFail; + } + + /* new instance fields init */ + newInstance->hostHandle = hostHandle; + newInstance->speed = speed; + newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES; + newInstance->setAddress = 0; + newInstance->deviceAttachState = kStatus_device_Attached; +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + newInstance->deviceDescriptor = + (usb_descriptor_device_t *)SDK_Malloc(sizeof(usb_descriptor_device_t) + 9, USB_CACHE_LINESIZE); +#else + newInstance->deviceDescriptor = + (usb_descriptor_device_t *)USB_OsaMemoryAllocate(sizeof(usb_descriptor_device_t) + 9); +#endif + if (newInstance->deviceDescriptor == NULL) + { +#ifdef HOST_ECHO + usb_echo("allocate newInstance->deviceDescriptor fail\r\n"); +#endif +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_AllocFail; + } + newInstance->enumBuffer = (uint8_t *)((uint8_t *)newInstance->deviceDescriptor + sizeof(usb_descriptor_device_t)); +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + newInstance->hubNumber = hubNumber; + newInstance->portNumber = portNumber; + newInstance->level = level; + + if ((speed != USB_SPEED_HIGH) && (level > 1)) + { + newInstance->hsHubNumber = USB_HostHubGetHsHubNumber(hostHandle, hubNumber); + newInstance->hsHubPort = USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber); + } + else + { + newInstance->hsHubNumber = hubNumber; + newInstance->hsHubPort = portNumber; + } +#endif /* USB_HOST_CONFIG_HUB */ + + USB_HostLock(); + /* allocate address && insert to the dev list */ + address = USB_HostAllocateDeviceAddress(hostInstance); + if (address == 0) + { +#ifdef HOST_ECHO + usb_echo("allocate address fail\r\n"); +#endif + USB_HostUnlock(); +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_Error; + } + newInstance->allocatedAddress = address; + + newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList; + hostInstance->deviceList = newInstance; + newInstance->state = kStatus_DEV_Initial; + USB_HostUnlock(); + + /* open control pipe */ + pipeInit.devInstance = newInstance; + pipeInit.pipeType = USB_ENDPOINT_CONTROL; + pipeInit.direction = 0; + pipeInit.endpointAddress = 0; + pipeInit.interval = 0; + pipeInit.maxPacketSize = 8; + pipeInit.numberPerUframe = 0; + pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK; + if (USB_HostOpenPipe(hostHandle, &newInstance->controlPipe, &pipeInit) != kStatus_USB_Success) + { + /* don't need release resource, resource is released when detach */ + *deviceHandle = newInstance; +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_Error; + } + + /* start enumeration */ + newInstance->state = kStatus_DEV_GetDes8; + USB_HostProcessState(newInstance); /* process enumeration state machine */ + + *deviceHandle = newInstance; + return kStatus_USB_Success; +} + +usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber) +{ + usb_host_device_instance_t *deviceInstance; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + USB_HostLock(); +/* search for device instance handle */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (deviceInstance != NULL) + { + if ((deviceInstance->hubNumber == hubNumber) && (deviceInstance->portNumber == portNumber)) + { + break; + } + deviceInstance = deviceInstance->next; + } +#else + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; +#endif + USB_HostUnlock(); + if (deviceInstance != NULL) + { + return USB_HostDetachDeviceInternal(hostHandle, deviceInstance); /* device instance detach */ + } + return kStatus_USB_Success; +} + +usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + deviceInstance->deviceAttachState = kStatus_device_Detached; /* mark the device is detached from host */ + + if (deviceInstance->state >= kStatus_DEV_Initial) /* device instance is valid */ + { + /* detach internally */ + if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeration is not done */ + { + if (deviceInstance->controlPipe != NULL) + { + USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); + } + + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + USB_HostReleaseDeviceResource(hostInstance, deviceInstance); + } + else /* enumeration has be done and notifed application */ + { + USB_HostNotifyDevice(deviceInstance, kUSB_HostEventDetach); /* notify application device detach */ + } + } + + return kStatus_USB_Success; +} + +uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle) +{ + return deviceHandle ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0; +} + +usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *searchDev; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidParameter; + } + /* search for the device */ + searchDev = (usb_host_device_instance_t *)((usb_host_instance_t *)hostHandle)->deviceList; + while ((searchDev != NULL) && ((usb_device_handle)searchDev != deviceHandle)) + { + searchDev = searchDev->next; + } + + if (searchDev) + { + return kStatus_USB_Success; + } + return kStatus_USB_Error; +} + +static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &controlType); + + return status; +} + +usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = NULL; + uint8_t interfaceIndex; + uint8_t index = 0; + + if ((deviceHandle == NULL) || (interfaceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + USB_HostLock(); + /* check host_instance valid? */ + for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) + { + if ((g_UsbHostInstance[index].occupied == 1) && + ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) + { + break; + } + } + if (index >= USB_HOST_CONFIG_MAX_HOST) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* check deviceHandle valid? */ + if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* search interface and set the interface as opened */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) + { + deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Opened; + break; + } + } + USB_HostUnlock(); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = NULL; + uint8_t interfaceIndex; + uint8_t removeLabel = 1; + uint8_t index = 0; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + USB_HostLock(); + /* check host_instance valid? */ + for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) + { + if ((g_UsbHostInstance[index].occupied == 1) && + ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) + { + break; + } + } + if (index >= USB_HOST_CONFIG_MAX_HOST) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* check deviceHandle valid? */ + if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + if (interfaceHandle != NULL) + { + /* search interface and set the interface as detached */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) + { + deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Detached; + break; + } + } + } + + if (deviceInstance->deviceAttachState == kStatus_device_Detached) /* device is removed from host */ + { + removeLabel = 1; + /* check all the interfaces of the device are not opened */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) + { + removeLabel = 0; + break; + } + } + if (removeLabel == 1) + { + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + } + USB_HostUnlock(); + + if (removeLabel == 1) + { + USB_HostReleaseDeviceResource((usb_host_instance_t *)deviceInstance->hostHandle, + deviceInstance); /* release device resource */ + } + } + else + { + USB_HostUnlock(); + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + uint8_t interfaceIndex = 0; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + uint8_t level = 0; + uint8_t devHubNo; + uint8_t devPortNo; +#endif + + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + if (deviceInstance->hostHandle != hostHandle) + { + return kStatus_USB_InvalidParameter; + } + + if (USB_HostValidateDevice(hostInstance, deviceInstance) == kStatus_USB_Success) /* device is valid */ + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + devHubNo = deviceInstance->hubNumber; + devPortNo = deviceInstance->portNumber; + level = deviceInstance->level; +#endif + + deviceInstance->deviceAttachState = kStatus_device_Detached; + if (deviceInstance->state >= kStatus_DEV_Initial) /* device is valid */ + { + if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeraion is not done or application don't use */ + { + /* detach internally */ + USB_HostDetachDeviceInternal(hostHandle, deviceHandle); + } + else /* application use the device */ + { + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; + ++interfaceIndex) + { + if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) + { +#ifdef HOST_ECHO + usb_echo("error: there is class instance that is not deinited\r\n"); +#endif + break; + } + } + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + USB_HostReleaseDeviceResource(hostInstance, deviceInstance); /* release resource */ + } + } + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + if (level == 1) + { + USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ + USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ + } + else + { + USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */ + } +#else + USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ + USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ +#endif /* USB_HOST_CONFIG_HUB */ + } + + return kStatus_USB_Success; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_devices.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_devices.h new file mode 100644 index 0000000000..422e876a12 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_devices.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_DEV_MNG_H_ +#define _USB_HOST_DEV_MNG_H_ + +#include "usb_host.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @addtogroup usb_host_drv + * @{ + */ +/*! @brief States of device instances enumeration */ +typedef enum _usb_host_device_enumeration_status +{ + kStatus_DEV_Notinit = 0, /*!< Device is invalid */ + kStatus_DEV_Initial, /*!< Device has been processed by host driver */ + kStatus_DEV_GetDes8, /*!< Enumeration process: get 8 bytes' device descriptor */ + kStatus_DEV_SetAddress, /*!< Enumeration process: set device address */ + kStatus_DEV_GetDes, /*!< Enumeration process: get device descriptor */ + kStatus_DEV_GetCfg9, /*!< Enumeration process: get 9 bytes' configuration descriptor */ + kStatus_DEV_GetCfg, /*!< Enumeration process: get configuration descriptor */ + kStatus_DEV_SetCfg, /*!< Enumeration process: set configuration */ + kStatus_DEV_EnumDone, /*!< Enumeration is done */ + kStatus_DEV_AppUsed, /*!< This device has been used by application */ +} usb_host_device_enumeration_status_t; + +/*! @brief States of device's interface */ +typedef enum _usb_host_interface_state +{ + kStatus_interface_Attached = 1, /*!< Interface's default status */ + kStatus_interface_Opened, /*!< Interface is used by application */ + kStatus_interface_Detached, /*!< Interface is not used by application */ +} usb_host_interface_state_t; + +/*! @brief States of device */ +typedef enum _usb_host_device_state +{ + kStatus_device_Detached = 0, /*!< Device is used by application */ + kStatus_device_Attached, /*!< Device's default status */ +} usb_host_device_state_t; + +/*! @brief Device instance */ +typedef struct _usb_host_device_instance +{ + struct _usb_host_device_instance *next; /*!< Next device, or NULL */ + usb_host_handle hostHandle; /*!< Host handle */ + usb_host_configuration_t configuration; /*!< Parsed configuration information for the device */ + usb_descriptor_device_t *deviceDescriptor; /*!< Standard device descriptor */ + usb_host_pipe_handle controlPipe; /*!< Device's control pipe */ + uint8_t *configurationDesc; /*!< Configuration descriptor pointer */ + uint16_t configurationLen; /*!< Configuration descriptor length */ + uint16_t configurationValue; /*!< Configuration index */ + uint8_t interfaceStatus[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interfaces' status, please reference to + #usb_host_interface_state_t */ + uint8_t *enumBuffer; /*!< Buffer for enumeration */ + uint8_t state; /*!< Device state for enumeration */ + uint8_t enumRetries; /*!< Re-enumeration when error in control transfer */ + uint8_t stallRetries; /*!< Re-transfer when stall */ + uint8_t speed; /*!< Device speed */ + uint8_t allocatedAddress; /*!< Temporary address for the device. When set address request succeeds, setAddress is + a value, 1 - 127 */ + uint8_t setAddress; /*!< The address has been set to the device successfully, 1 - 127 */ + uint8_t deviceAttachState; /*!< See the usb_host_device_state_t */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + /* hub related */ + uint8_t hubNumber; /*!< Device's first connected hub address (root hub = 0) */ + uint8_t portNumber; /*!< Device's first connected hub's port no (1 - 8) */ + uint8_t hsHubNumber; /*!< Device's first connected high-speed hub's address (1 - 8) */ + uint8_t hsHubPort; /*!< Device's first connected high-speed hub's port no (1 - 8) */ + uint8_t level; /*!< Device's level (root device = 0) */ +#endif +} usb_host_device_instance_t; + +typedef struct _usb_host_enum_process_entry +{ + uint8_t successState; /*!< When the last step is successful, the next state value */ + uint8_t retryState; /*!< When the last step need retry, the next state value */ + usb_status_t (*process)(usb_host_device_instance_t *deviceInstance); /*!< When the last step transfer is done, the + function is used to process the transfer + data */ +} usb_host_enum_process_entry_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Calls this function when device attach. + * + * @param hostHandle Host instance handle. + * @param speed Device speed. + * @param hubNumber Device hub no. root device's hub no. is 0. + * @param portNumber Device port no. root device's port no. is 0. + * @param level Device level. root device's level is 1. + * @param deviceHandle Return device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, + uint8_t speed, + uint8_t hubNumber, + uint8_t portNumber, + uint8_t level, + usb_device_handle *deviceHandle); + +/*! + * @brief Call this function when device detaches. + * + * @param hostHandle Host instance handle. + * @param hubNumber Device hub no. root device's hub no. is 0. + * @param portNumber Device port no. root device's port no. is 0. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); + +/*! + * @brief Call this function when device detaches. + * + * @param hostHandle Host instance handle. + * @param deviceHandle Device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief Gets the device attach/detach state. + * + * @param deviceHandle Device handle. + * + * @return 0x01 - attached; 0x00 - detached. + */ +extern uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle); + +/*! + * @brief Determine whether the device is attached. + * + * @param hostHandle Host instance pointer. + * @param deviceHandle Device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! @}*/ +#endif /* _USB_HOST_DEV_MNG_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_ehci.c b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_ehci.c new file mode 100644 index 0000000000..8a31514b3a --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_ehci.c @@ -0,0 +1,4747 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U)) +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" +#include "fsl_device_registers.h" +#include "usb_host_ehci.h" +#include "usb_phy.h" +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#include "usb_host.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +#define USB_HOST_EHCI_BANDWIDTH_DELAY (3500U) +#define USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP (333U) +#define USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME (900U) + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#define USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH (18U) +#define USB_HOST_EHCI_PORTSC_PTC_J_STATE (0x01U) +#define USB_HOST_EHCI_PORTSC_PTC_K_STATE (0x02U) +#define USB_HOST_EHCI_PORTSC_PTC_SE0_NAK (0x03U) +#define USB_HOST_EHCI_PORTSC_PTC_PACKET (0x04U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS (0x05U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_FS (0x06U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_LS (0x07U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief compute data bandwidth time. + * + * @param speed data speed. + * @param pipeType data type. + * @param direction data direction. + * @param dataLength data length. + * + *@return time value. + */ +static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength); + +/*! + * @brief compute current allocated bandwidth when ehci work as full-speed or low-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint16_t *frameBandwidth); + +/*! + * @brief compute current hub's allocated FS/LS bandwidth when ehci work as hi-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param hubNumber hub address. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, + uint32_t hubNumber, + uint16_t frameIndex, + uint8_t frameBandwidths[8]); + +/*! + * @brief compute current allocated HS bandwidth when ehci work as hi-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint8_t frameBandwidths[8]); + +/*! + * @brief allocate HS bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param uframeInterval micro-frame interval. + * @param timeData time for allocating. + * @param uframe_index_out return start uframe index. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, + uint16_t uframeInterval, + uint16_t timeData, + uint16_t *uframeIndexOut); + +/*! + * @brief allocate HS interrupt bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief allocate bandwidth when host work as full-speed or low-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief get the 2 power value of uint8_t. + * + * @param value input uint8_t value. + */ +static uint8_t USB_HostEhciGet2PowerValue(uint8_t value); + +/*! + * @brief memory zero. + * + * @param buffer buffer pointer. + * @param length buffer length. + */ +static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length); + +/*! + * @brief host ehci delay. + * + * @param ehciIpBase ehci ip base address. + * @param ms millisecond. + */ +static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms); + +/*! + * @brief host ehci start async schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci stop async schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci start periodic schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci stop periodic schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief initialize the qtd for one transfer. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release the qtd list. + * + * @param ehciInstance ehci instance pointer. + * @param ehciQtdStart qtd list start pointer. + * @param ehciQtdEnd qtd list end pointer. + * + *@return the transfer's length. + */ +static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_qtd_t *ehciQtdStart, + usb_host_ehci_qtd_t *ehciQtdEnd); + +/*! + * @brief de-initialize qh's linking qtd list. + * 1. remove qtd from qh; 2. remove transfer from qh; 3. release qtd; 4. transfer callback. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief de-initialize transfer's linking qtd list. + * 1. stop this qh schedule; 2. remove qtd from qh; 3. remove transfer from qh; 4. release qtd; 5. transfer callback; 6. + *start this qh schedule. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief initialize QH when opening one control, bulk or interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief de-initialize QH when closing one control, bulk or interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief add qh to one frame entry. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param framePos frame index. + * @param uframeInterval micro-frame interval. + */ +static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos, + uint16_t uframeInterval); + +/*! + * @brief remove entry from frame list. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param framePos frame index. + */ +static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos); + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) +/*! + * @brief add sitd array to the frame list. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param startEntryPointer sitd entry pointer. + */ +static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + void *startEntryPointer); + +/*! + * @brief initialize sitd array for one transfer. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + */ +static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release sitd list. + * + * @param ehciInstance ehci instance pointer. + * @param startSitdPointer start sitd pointer. + * @param endSitdPointer end sitd pointer. + * + * @return transfer's result length. + */ +static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_sitd_t *startSitdPointer, + usb_host_ehci_sitd_t *endSitdPointer); + +/*! + * @brief de-initialize sitd list. + * 1. remove transfer; 2. remove sitd from frame list and release sitd; 3. transfer callback + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) +/*! + * @brief compute the frame index when inserting itd. + * + * @param ehciInstance ehci instance pointer. + * @param lastLinkUframe last inserted micro-frame. + * @param startUframe start micro-frame. + * @param uframeInterval micro-frame interval. + * + * @return frame index + */ +static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t lastLinkUframe, + uint16_t startUframe, + uint16_t uframeInterval); + +/*! + * @brief initialize itd list for one transfer. + * 1. initialize itd list; 2. insert itd to frame list. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release itd list. + * + * @param ehciInstance ehci instance pointer. + * @param startItdPointer start itd pointer. + * @param endItdPointer end itd pointer. + * + * @return transfer's result length. + */ +static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_itd_t *startItdPointer, + usb_host_ehci_itd_t *endItdPointer); + +/*! + * @brief de-initialize itd list. + * 1. remove transfer; 2. remove itd from frame list and release itd; 3. transfer callback + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +/*! + * @brief open control or bulk pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close control or bulk pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief open interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) +/*! + * @brief open iso pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close iso pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief allocate HS iso bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +#endif + +/*! + * @brief reset ehci ip. + * + * @param ehciInstance ehci instance pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief start ehci ip. + * + * @param ehciInstance ehci instance pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief cancel pipe's transfers. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer the canceling transfer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief control ehci bus. + * + * @param ehciInstance ehci instance pointer. + * @param bus_control control code. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl); + +/*! + * @brief ehci transaction done process function. + * + * @param ehciInstance ehci instance pointer. + */ +void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief ehci port change interrupt process function. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief ehci timer0 interrupt process function. + * cancel control/bulk transfer that time out. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance); + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief ehci timer1 interrupt process function. + * cancel control/bulk transfer that time out. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance); +#endif + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +/*! + * @brief suspend bus. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief resume bus. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance); + +extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* EHCI controller driver instances. */ +#if (USB_HOST_CONFIG_EHCI == 1U) +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; + +#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ + { \ + &s_UsbHostEhciFrameList1[0] \ + } + +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; +#define USB_HOST_EHCI_DATA_ARRAY \ + { \ + &s_UsbHostEhciData1 \ + } +#elif(USB_HOST_CONFIG_EHCI == 2U) +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList2[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; +#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ + { \ + &s_UsbHostEhciFrameList1[0], &s_UsbHostEhciFrameList2[0] \ + } + +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData2; +#define USB_HOST_EHCI_DATA_ARRAY \ + { \ + &s_UsbHostEhciData1, &s_UsbHostEhciData2 \ + } +#else +#error "Please increase the instance count." +#endif + +static uint8_t s_SlotMaxBandwidth[8] = {125, 125, 125, 125, 125, 125, 50, 0}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! +* @brief EHCI NC get USB NC bass address. +* +* This function is used to get USB NC bass address. +* +* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. +* +* @retval USB NC bass address. +*/ +#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +void *USB_EhciNCGetBase(uint8_t controllerId) +{ + void *usbNCBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) + { + if (usbnc_base_temp[instance]) + { + usbnc_base[newinstance++] = usbnc_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbNCBase = (void *)usbnc_base[controllerId]; +#endif + return usbNCBase; +} +#endif +#endif + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + +usb_status_t USB_HostEhciTestSetMode(usb_host_ehci_instance_t *ehciInstance, uint32_t testMode) +{ + uint32_t ehciPortSC; + + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + ehciPortSC &= ~((uint32_t)USBHS_PORTSC1_PTC_MASK); /* clear test mode bits */ + ehciPortSC |= (testMode << USBHS_PORTSC1_PTC_SHIFT); /* set test mode bits */ + ehciInstance->ehciIpBase->PORTSC1 = ehciPortSC; + return kStatus_USB_Success; +} + +static void USB_HostEhciTestSuspendResume(usb_host_ehci_instance_t *ehciInstance) +{ + uint8_t timeCount; + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + USB_HostEhciSuspendBus(ehciInstance); + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + USB_HostEhciResumeBus(ehciInstance); +} + +static void USB_HostEhciTestCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) +{ + USB_HostFreeTransfer(param, transfer); +} + +static void USB_HostEhciTestSingleStepGetDeviceDesc(usb_host_ehci_instance_t *ehciInstance, + usb_device_handle deviceHandle) +{ + usb_host_process_descriptor_param_t getDescriptorParam; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_transfer_t *transfer; + uint8_t timeCount; + + /* disable periodic shedule */ + USB_HostEhciStopPeriodic(ehciInstance); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + /* malloc one transfer */ + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("allocate transfer error\r\n"); +#endif + return; + } + + getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); + getDescriptorParam.descriptorLength = 18; + getDescriptorParam.descriptorBuffer = (uint8_t *)&deviceInstance->deviceDescriptor; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; + getDescriptorParam.descriptorIndex = 0; + getDescriptorParam.languageId = 0; + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + transfer->setupPacket->wIndex = 0; + transfer->setupPacket->wLength = 0; + transfer->setupPacket->wValue = 0; + USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); +} + +static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer, + uint8_t setupPhase) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_ehci_qtd_t *qtdPointer = NULL; + volatile uint32_t *entryPointer; + uint32_t qtdNumber; + uint32_t dataLength; + uint32_t dataAddress; + uint8_t index; + + /* compute the qtd number */ + qtdNumber = 1; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* get qtd list */ + USB_HostEhciLock(); + if (qtdNumber <= ehciInstance->ehciQtdNumber) + { + ehciInstance->ehciQtdNumber -= qtdNumber; + qtdPointer = NULL; + do + { + if (qtdPointer != NULL) + { + qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; + } + qtdPointer = ehciInstance->ehciQtdHead; + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + qtdPointer->nextQtdPointer = 0; + } while (--qtdNumber); + } + else + { + USB_HostEhciUnlock(); + return kStatus_USB_Error; + } + USB_HostEhciUnlock(); + + /* int qTD */ + if (setupPhase == 1) /* setup transaction qtd init */ + { + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + qtdPointer->transferResults[0] = + ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + dataAddress = (uint32_t)(transfer->setupPacket); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); + } + } + else if (setupPhase == 2) /* data transaction qtd */ + { + dataLength = transfer->transferLength; + if (dataLength != 0) + { + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + + dataAddress = (uint32_t)(transfer->transferBuffer); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); + } + } + } + else if (setupPhase == 3) + { + /* status transaction qtd */ + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + } + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* set IOC */ + + /* save qtd to transfer */ + transfer->union1.unitHead = (uint32_t)qtdPointer; + transfer->union2.unitTail = (uint32_t)qtdPointer; + /* link transfer to qh */ + transfer->next = NULL; + if (vltQhPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + vltQhPointer->ehciTransferTail->next = transfer; + vltQhPointer->ehciTransferTail = transfer; + } + + USB_HostEhciLock(); + /* link qtd to qh (link to end) */ + entryPointer = &(vltQhPointer->nextQtdPointer); + dataAddress = *entryPointer; /* dataAddress variable means entry value here */ + while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) + { + entryPointer = (volatile uint32_t *)dataAddress; + dataAddress = *entryPointer; + } + *entryPointer = (uint32_t)qtdPointer; + USB_HostEhciUnlock(); + USB_HostEhciStartAsync(ehciInstance); + + return kStatus_USB_Success; +} + +static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t *ehciInstance, + usb_device_handle deviceHandle) +{ + static uint8_t buffer[USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH]; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_transfer_t *transfer; + uint8_t timeCount; + + USB_HostEhciStopPeriodic(ehciInstance); + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH); + transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN((uint16_t)((uint16_t)USB_DESCRIPTOR_TYPE_DEVICE << 8)); + transfer->setupPacket->wIndex = 0; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 1); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->transferBuffer = buffer; + transfer->transferLength = USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 2); + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->transferBuffer = NULL; + transfer->transferLength = 0; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 3); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + usb_echo("test_single_step_get_dev_desc_data finished\r\n"); + + return; +} + +void USB_HostEhciTestModeInit(usb_device_handle deviceHandle) +{ + uint32_t productId; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_ehci_instance_t *ehciInstance = + (usb_host_ehci_instance_t *)(((usb_host_instance_t *)(deviceInstance->hostHandle))->controllerHandle); + + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); + + usb_echo("usb host ehci test mode init product id:0x%x\r\n", productId); + + switch (productId) + { + case 0x0101U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_SE0_NAK); + break; + case 0x0102U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_J_STATE); + break; + case 0x0103U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_K_STATE); + break; + case 0x0104U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_PACKET); + break; + case 0x0105U: + usb_echo("set test mode FORCE_ENALBE_HS\r\n"); + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS); + break; + case 0x0106U: + USB_HostEhciTestSuspendResume(ehciInstance); + break; + case 0x0107U: + usb_echo("start test SINGLE_STEP_GET_DEV_DESC\r\n"); + USB_HostEhciTestSingleStepGetDeviceDesc(ehciInstance, deviceHandle); + break; + case 0x0108U: + usb_echo("start test SINGLE_STEP_GET_DEV_DESC_DATA\r\n"); + USB_HostEhciTestSingleStepGetDeviceDescData(ehciInstance, deviceHandle); + break; + default: + break; + } + + return; +} + +static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t ehciPortSC; + + USB_HostEhciLock(); + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + if (ehciPortSC & USBHS_PORTSC1_PE_MASK) + { + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_SUSP_MASK); + } + USB_HostEhciUnlock(); +} + +static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t ehciPortSC; + + USB_HostEhciLock(); + /* Resume port */ + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + if (ehciPortSC & USBHS_PORTSC1_PE_MASK) + { + ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_FPR_MASK); + } + USB_HostEhciUnlock(); +} +#endif + +static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength) +{ + uint32_t result = (3167 + ((1000 * dataLength) * 7U * 8U / 6U)) / 1000; + + if (pipeType == USB_ENDPOINT_ISOCHRONOUS) /* iso */ + { + if (speed == USB_SPEED_HIGH) + { + result = 38 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_FULL) + { + if (direction == USB_IN) + { + result = 7268000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else + { + result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + } + else + { + } + } + else /* interrupt */ + { + if (speed == USB_SPEED_HIGH) + { + result = 55 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_FULL) + { + result = 9107000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_LOW) + { + if (direction == USB_IN) + { + result = 64060000 + 2000 * USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP + 676670 * result + + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else + { + result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + } + else + { + } + } + + result /= 1000000; + if (result == 0) + { + result = 1; + } + + return result; +} + +static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint16_t *frameBandwidth) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + + /* clear the bandwidth */ + *frameBandwidth = 0; + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & + (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) + { + *frameBandwidth += ehciPipePointer->dataTime; + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, + uint32_t hubNumber, + uint16_t frameIndex, + uint8_t frameBandwidths[8]) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + uint8_t index; + uint32_t deviceInfo; + + for (index = 0; index < 8; ++index) + { + frameBandwidths[index] = 0; + } + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + /* compute FS/LS bandwidth that blong to same high-speed hub, because FS/LS bandwidth is allocated from + * first parent high-speed hub */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, + kUSB_HostGetDeviceHSHubNumber, &deviceInfo); + if (deviceInfo != hubNumber) + { + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + continue; + } + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + if (deviceInfo == USB_SPEED_HIGH) + { + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + continue; + } + + /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & + (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) + { + if (ehciPipePointer->pipeCommon.pipeType == + USB_ENDPOINT_ISOCHRONOUS) /* iso bandwidth is allocated once */ + { + frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; + } + else /* iso bandwidth is allocated three times */ + { + frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; + frameBandwidths[ehciPipePointer->startUframe + 2] += ehciPipePointer->dataTime; + frameBandwidths[ehciPipePointer->startUframe + 3] += ehciPipePointer->dataTime; + } + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + + for (index = 0; index < 7; ++index) /* */ + { + if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) + { + frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); + frameBandwidths[index] = s_SlotMaxBandwidth[index]; + } + } +} + +static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint8_t frameBandwidths[8]) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + uint8_t index; + uint32_t deviceInfo; + uint16_t frameInterval; + + for (index = 0; index < 8; ++index) + { + frameBandwidths[index] = 0; + } + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + frameInterval = ehciPipePointer->pipeCommon.interval; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + if (deviceInfo == USB_SPEED_HIGH) /* high-speed data bandwidth */ + { + /* frameInterval means micro-frame here */ + if (frameIndex >= ehciPipePointer->startFrame) + { + if ((frameInterval > 8) && + (frameIndex * 8 - ehciPipePointer->startFrame * 8 >= ehciPipePointer->startUframe)) + { + if (!((uint32_t)(frameIndex * 8 - ehciPipePointer->startFrame * 8 - + ehciPipePointer->startUframe) & + (uint32_t)(frameInterval - 1))) + { + frameBandwidths[ehciPipePointer->startUframe] += ehciPipePointer->dataTime; + } + } + else + { + for (index = ehciPipePointer->startUframe; index < 8; index += frameInterval) + { + frameBandwidths[index] += ehciPipePointer->dataTime; + } + } + } + } + else /* full-speed split bandwidth */ + { + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & (uint32_t)(frameInterval - 1)))) + { + for (index = 0; index < 8; ++index) + { + if ((uint32_t)(ehciPipePointer->uframeSmask) & + (uint32_t)(0x01 << index)) /* start-split micro-frames */ + { + frameBandwidths[index] += ehciPipePointer->startSplitTime; + } + if ((uint32_t)(ehciPipePointer->uframeCmask) & + (uint32_t)(0x01 << index)) /* complete-split micro-frames */ + { + frameBandwidths[index] += ehciPipePointer->completeSplitTime; + } + } + } + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + + for (index = 0; index < 7; ++index) /* */ + { + if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) + { + frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); + frameBandwidths[index] = s_SlotMaxBandwidth[index]; + } + } +} + +/*! + * @brief allocate HS bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param uframeInterval micro-frame interval. + * @param timeData time for allocating. + * @param uframeIndexOut return start uframe index. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, + uint16_t uframeInterval, + uint16_t timeData, + uint16_t *uframeIndexOut) +{ + uint16_t uframeIntervalIndex; + uint16_t uframeIndex; + uint16_t frameIndex; + uint8_t frameTimes[8]; + + frameIndex = 0; + USB_HostBandwidthHsHostComputeCurrentHsAll( + ehciInstance, frameIndex, frameTimes); /* compute the allocated bandwidths in the frameIndex frame */ + for (uframeIntervalIndex = 0; (uframeIntervalIndex < uframeInterval); ++uframeIntervalIndex) /* start micro-frame */ + { + /* for all the micro-frame in interval uframeInterval */ + for (uframeIndex = uframeIntervalIndex; uframeIndex < (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8); + uframeIndex += uframeInterval) + { + if (frameIndex != (uframeIndex >> 3)) + { + frameIndex = (uframeIndex >> 3); + USB_HostBandwidthHsHostComputeCurrentHsAll( + ehciInstance, frameIndex, + frameTimes); /* compute the allocated bandwidths in the new frameIndex frame */ + } + if (frameTimes[uframeIndex & 0x0007] + timeData > + s_SlotMaxBandwidth[(uframeIndex & 0x0007)]) /* micro-frame has enough idle bandwidth? */ + { + break; /* fail */ + } + } + if (uframeIndex >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8)) /* success? */ + { + break; + } + } + + if (uframeIntervalIndex < uframeInterval) + { + *uframeIndexOut = (uframeIntervalIndex); + return kStatus_USB_Success; + } + else + { + return kStatus_USB_Error; + } +} + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + +static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status; + uint32_t deviceInfo; + uint32_t hubNumber; + uint16_t uframeIntervalIndex = 0; + uint16_t frameIntervalIndex = 0; + uint16_t frameIndex; + uint16_t timeCompleteSplit; + uint16_t timeStartSplit; + uint32_t timeData; + uint8_t SsCsNumber = 0; + uint16_t frameInterval; + uint8_t frameTimes[8]; + uint8_t allocateOk = 1; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + + timeData = USB_HostBandwidthComputeTime( + deviceInfo, USB_ENDPOINT_ISOCHRONOUS, ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); + /* pipe is high-speed */ + if (deviceInfo == USB_SPEED_HIGH) + { + uframeIntervalIndex = 0; + status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, + &uframeIntervalIndex); + if (status == kStatus_USB_Success) + { + ehciPipePointer->startFrame = (uframeIntervalIndex / 8); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + ehciPipePointer->dataTime = timeData; + + return kStatus_USB_Success; + } + } + else /* pipe is full-speed or low-speed */ + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &deviceInfo); /* deviceInfo variable means hub think time */ + timeData += (deviceInfo * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + frameInterval = ehciPipePointer->pipeCommon.interval; + + /* compute start-split and complete-split bandwidth */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_OUT, + ehciPipePointer->pipeCommon.maxPacketSize); + timeCompleteSplit = 0; + } + else + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, + ehciPipePointer->pipeCommon.maxPacketSize); + } + /* note: bandwidth must put in one frame */ + for (uframeIntervalIndex = 0; uframeIntervalIndex <= 5; ++uframeIntervalIndex) /* uframe interval */ + { + for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ + { + allocateOk = 1; + for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) /* check all the frames */ + { + /* compute start-split and complete-split number */ + SsCsNumber = (ehciPipePointer->pipeCommon.maxPacketSize + 187) / + 188; /* ss number for iso out; cs number for iso in */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ + { + if (uframeIntervalIndex + SsCsNumber > 8) + { + allocateOk = 0; + } + } + else + { + if (uframeIntervalIndex + 2 + SsCsNumber > + 8) /* ISO IN: there are two micro-frame interval between start-split and complete-split */ + { + allocateOk = 0; + } + } + if (allocateOk) + { + /* allocate start-split and complete-split bandwidth */ + USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); + if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ + { + index = uframeIntervalIndex; + for (; index < (uframeIntervalIndex + SsCsNumber); ++index) + { + if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + else /* ISO IN */ + { + index = uframeIntervalIndex; + if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + } + if (allocateOk) + { + index = + uframeIntervalIndex + + 2; /* there are two micro-frames interval between start-split and complete-split */ + for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) + { + if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + } + } + + /* allocate data bandwidth */ + if (allocateOk) + { + USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); + index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ + /* iso must occupy all the uframe bandwidth */ + { + deviceInfo = timeData; /* note: deviceInfo variable means bandwidth here */ + while ((index < 8) && (deviceInfo > s_SlotMaxBandwidth[index])) + { + if (frameTimes[index] > 0) + { + allocateOk = 0; + break; + } + else + { + deviceInfo -= s_SlotMaxBandwidth[index]; + } + ++index; + } + } + } + if (allocateOk) + { + /* data bandwidth can be put in the frame? */ + index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ + frameTimes[index] += timeData; + for (; index < 7; ++index) + { + if (frameTimes[index] > s_SlotMaxBandwidth[index]) + { + frameTimes[index + 1] += (frameTimes[index] - s_SlotMaxBandwidth[index]); + frameTimes[index] = s_SlotMaxBandwidth[index]; + } + else + { + break; + } + } + if (frameTimes[index] > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + } + } + + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + + if (allocateOk) + { + ehciPipePointer->startFrame = frameIntervalIndex; + ehciPipePointer->startUframe = uframeIntervalIndex; + ehciPipePointer->dataTime = timeData; + ehciPipePointer->startSplitTime = timeStartSplit; + ehciPipePointer->completeSplitTime = timeCompleteSplit; + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + index = uframeIntervalIndex; + for (; index < (uframeIntervalIndex + SsCsNumber); ++index) + { + ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); + } + } + else + { + index = uframeIntervalIndex; + ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); + index = uframeIntervalIndex + 2; + for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) + { + ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); + } + } + + return kStatus_USB_Success; + } + } + + return kStatus_USB_Error; +} + +#endif + +static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status; + uint32_t deviceInfo; + uint32_t hubNumber; + uint16_t uframeIntervalIndex = 0; + uint16_t frameIntervalIndex = 0; + uint16_t frameIndex; + uint16_t timeCompleteSplit; + uint16_t timeStartSplit; + uint32_t timeData; + uint8_t SsCsNumber; + uint16_t frameInterval; + uint8_t frameTimes[8]; + uint8_t allocateOk = 1; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + + timeData = USB_HostBandwidthComputeTime( + deviceInfo, USB_ENDPOINT_INTERRUPT, ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); + /* pipe is high-speed */ + if (deviceInfo == USB_SPEED_HIGH) + { + uframeIntervalIndex = 0; + status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, + &uframeIntervalIndex); + if (status == kStatus_USB_Success) + { + ehciPipePointer->startFrame = (uframeIntervalIndex / 8); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + /* for HS interrupt start transaction position */ + if (ehciPipePointer->uframeInterval >= 8) + { + ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); + } + else + { + ehciPipePointer->uframeSmask = 0x00u; + for (index = ehciPipePointer->startUframe; index < 8; index += ehciPipePointer->uframeInterval) + { + ehciPipePointer->uframeSmask |= (0x01U << index); + } + } + ehciPipePointer->dataTime = timeData; + + return kStatus_USB_Success; + } + } + else /* pipe is full-speed or low-speed */ + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &deviceInfo); + timeData += (deviceInfo * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + frameInterval = ehciPipePointer->pipeCommon.interval; + SsCsNumber = 3; /* complete split number */ + + /* compute start-split and complete-split bandwidth */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, + ehciPipePointer->pipeCommon.maxPacketSize) + + USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 0); + } + else + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, + ehciPipePointer->pipeCommon.maxPacketSize) + + USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 0); + } + /* note: bandwidth must put in one frame */ + for (uframeIntervalIndex = 0; uframeIntervalIndex <= 4; ++uframeIntervalIndex) /* uframe interval */ + { + for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ + { + allocateOk = 1; + for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) /* check all the frames */ + { + /* allocate data bandwidth */ + USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); + index = uframeIntervalIndex + 1; + for (; index <= (uframeIntervalIndex + 3); ++index) /* data bandwidth number is 3. + uframeIntervalIndex don't exceed 4, so + index cannot exceed 7 */ + { + if (frameTimes[index] + timeData > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + + if (allocateOk) + { + USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); + /* allocate start_split bandwidth */ + if (frameTimes[uframeIntervalIndex] + timeStartSplit > s_SlotMaxBandwidth[uframeIntervalIndex]) + { + allocateOk = 0; + } + if (allocateOk) + { + /* allocate complete_split bandwidth */ + index = uframeIntervalIndex + 2; + /* complete-split number is normal 3. When uframeIntervalIndex is 4, complete-split number + * is 2. */ + for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) + { + if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + } + + if (!allocateOk) + { + break; /* allocate fail */ + } + } + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + + if (allocateOk) + { + ehciPipePointer->startFrame = frameIntervalIndex; + ehciPipePointer->startUframe = uframeIntervalIndex; + ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); + ehciPipePointer->uframeCmask = 0; + index = uframeIntervalIndex + 2; + for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) + { + ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); + } + ehciPipePointer->dataTime = timeData; + ehciPipePointer->startSplitTime = timeStartSplit; + ehciPipePointer->completeSplitTime = timeCompleteSplit; + + return kStatus_USB_Success; + } + } + + return kStatus_USB_BandwidthFail; +} + +static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + uint32_t FslsTime = 0; + uint32_t speed = 0; + uint16_t uframeIntervalIndex; + uint16_t frameIndex; + uint16_t frameInterval; + uint16_t frameTime; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &FslsTime); + FslsTime += (FslsTime * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + FslsTime = FslsTime + USB_HostBandwidthComputeTime(speed, ehciPipePointer->pipeCommon.pipeType, + ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize); + + frameInterval = ehciPipePointer->pipeCommon.interval; + for (uframeIntervalIndex = 0; uframeIntervalIndex < ehciPipePointer->uframeInterval; + ++uframeIntervalIndex) /* uframeIntervalIndex can exceed 8 */ + { + for (frameIndex = (uframeIntervalIndex >> 3); frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) + { + USB_HostBandwidthFslsHostComputeCurrent(ehciInstance, frameIndex, &frameTime); + if (frameTime + FslsTime > USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME) + { + break; + } + } + if (frameIndex >= USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) + { + break; + } + } + if (uframeIntervalIndex < ehciPipePointer->uframeInterval) + { + ehciPipePointer->startFrame = (uframeIntervalIndex >> 3); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + ehciPipePointer->uframeSmask = 0; /* useless */ + ehciPipePointer->uframeCmask = 0; + ehciPipePointer->dataTime = FslsTime; + + return kStatus_USB_Success; + } + + return kStatus_USB_BandwidthFail; +} + +static uint8_t USB_HostEhciGet2PowerValue(uint8_t value) +{ + if ((value == 0) || (value == 1)) + { + return value; + } + if (value & 0xf0) + { + if (value & 0x80) + { + return 128; + } + else if (value & 0x40) + { + return 64; + } + else if (value & 0x20) + { + return 32; + } + else + { + return 16; + } + } + else + { + if (value & 0x08) + { + return 8; + } + else if (value & 0x04) + { + return 4; + } + else if (value & 0x02) + { + return 2; + } + else + { + return 1; + } + } +} + +static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length) +{ + /* note: the zero unit is uint32_t */ + while (length--) + { + *buffer = 0; + buffer++; + } +} + +static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms) +{ + /* note: the max delay time cannot exceed half of max value (0x4000) */ + int32_t sofStart; + int32_t SofEnd; + uint32_t distance; + + sofStart = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + + do + { + SofEnd = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + distance = (uint32_t)(SofEnd - sofStart + EHCI_MAX_UFRAME_VALUE + 1); + } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8)); /* compute the distance between sofStart and SofEnd */ +} + +static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) + { + /* the status must be same when change USBCMD->ASE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); + } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); + + ehciInstance->ehciIpBase->ASYNCLISTADDR = (uint32_t)(ehciInstance->shedFirstQh); + ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_ASE_MASK; + while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) + { + } + } +} + +static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + /* the status must be same when change USBCMD->ASE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); + } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); + + ehciInstance->ehciIpBase->USBCMD &= (uint32_t)(~(uint32_t)USBHS_USBCMD_ASE_MASK); /* disable async schedule */ + while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) + { + } +} + +static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) + { + /* the status must be same when change USBCMD->PSE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); + } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); + ehciInstance->ehciIpBase->PERIODICLISTBASE = (uint32_t)(ehciInstance->ehciFrameList); + if (!(ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)) + { + ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_PSE_MASK; /* start periodic schedule */ + } + while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) + { + } + } + return; +} + +static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + /* the status must be same when change USBCMD->PSE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); + } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); + + ehciInstance->ehciIpBase->USBCMD &= (~USBHS_USBCMD_PSE_MASK); /* stop periodic schedule */ + while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) + { + } +} + +static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_ehci_qtd_t *qtdPointer = NULL; + usb_host_ehci_qtd_t *BaseQtdPointer = NULL; + volatile uint32_t *entryPointer; + uint32_t qtdNumber; + uint32_t dataLength; + uint32_t dataAddress; + uint32_t endAddress; + uint8_t index; + + /* compute the qtd number */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + /* assume setup data don't exceed one qtd data size, one qtd can transfer least 16k data */ + if (transfer->transferLength == 0) + { + qtdNumber = 2; + } + else + { + qtdNumber = 3; + } + } + else + { + qtdNumber = + (((transfer->transferLength) & 0xFFFFC000U) >> 14) + (((transfer->transferLength) & 0x00003FFF) ? 1 : 0); + } + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* get qtd list */ + USB_HostEhciLock(); + if (qtdNumber <= ehciInstance->ehciQtdNumber) + { + ehciInstance->ehciQtdNumber -= qtdNumber; + BaseQtdPointer = ehciInstance->ehciQtdHead; + qtdPointer = NULL; + do + { + if (qtdPointer != NULL) + { + qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; + } + qtdPointer = ehciInstance->ehciQtdHead; + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + qtdPointer->nextQtdPointer = 0; + } while (--qtdNumber); + if (ehciInstance->ehciQtdNumber == 0) + { + ehciInstance->ehciQtdTail = NULL; + } + } + else + { + USB_HostEhciUnlock(); + return kStatus_USB_Error; + } + USB_HostEhciUnlock(); + + /* int qTD list */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + /* setup transaction qtd */ + qtdPointer = BaseQtdPointer; + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + qtdPointer->transferResults[0] = + ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + dataAddress = ((uint32_t)transfer->setupPacket); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + + /* data transaction qtd */ + dataLength = transfer->transferLength; + if (dataLength != 0) + { + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if (transfer->direction == USB_OUT) + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + + dataAddress = (uint32_t)transfer->transferBuffer; + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + } + + /* status transaction qtd */ + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if ((dataLength == 0) || (transfer->direction == USB_OUT)) + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + } + else + { + dataLength = transfer->transferLength; + dataAddress = (uint32_t)transfer->transferBuffer; + qtdPointer = BaseQtdPointer; + while (1) + { + endAddress = dataAddress + (16 * 1024); + if (endAddress > (uint32_t)(transfer->transferBuffer + transfer->transferLength)) + { + endAddress = (uint32_t)(transfer->transferBuffer + transfer->transferLength); + } + + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if (transfer->direction == USB_OUT) + { + qtdPointer->transferResults[0] = + (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | + (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | + (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | + (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + dataAddress = endAddress; /* for next qtd */ + + if (qtdPointer->nextQtdPointer == 0) + { + break; + } + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + } + + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* last one set IOC */ + } + + /* save qtd to transfer */ + transfer->union1.unitHead = (uint32_t)BaseQtdPointer; + transfer->union2.unitTail = (uint32_t)qtdPointer; + /* link transfer to qh */ + transfer->next = NULL; + if (vltQhPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + vltQhPointer->ehciTransferTail->next = transfer; + vltQhPointer->ehciTransferTail = transfer; + } + + USB_HostEhciLock(); + /* link qtd to qh (link to end) */ + entryPointer = &(vltQhPointer->nextQtdPointer); + dataAddress = *entryPointer; /* dataAddress variable means entry value here */ + while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) + { + entryPointer = (volatile uint32_t *)dataAddress; + dataAddress = *entryPointer; + } + *entryPointer = (uint32_t)BaseQtdPointer; + USB_HostEhciUnlock(); + USB_HostEhciStartAsync(ehciInstance); + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_qtd_t *ehciQtdStart, + usb_host_ehci_qtd_t *ehciQtdEnd) +{ + uint32_t length = 0; + usb_host_ehci_qtd_t *qtdPointer; + + ehciQtdEnd->nextQtdPointer = 0; + + /* compute remaining length */ + qtdPointer = ehciQtdStart; + while (qtdPointer != ehciQtdEnd) + { + length += + ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); + qtdPointer = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + } + qtdPointer = ehciQtdEnd; + length += ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); + + /* put releasing qtd to idle qtd list */ + USB_HostEhciLock(); + if (ehciInstance->ehciQtdNumber == 0) + { + ehciInstance->ehciQtdHead = ehciQtdStart; + ehciInstance->ehciQtdTail = ehciQtdEnd; + } + else + { + ehciInstance->ehciQtdTail->nextQtdPointer = (uint32_t)ehciQtdStart; + ehciInstance->ehciQtdTail = ehciQtdEnd; + } + + while (ehciQtdStart != ehciQtdEnd) + { + ehciInstance->ehciQtdNumber++; + ehciQtdStart = (usb_host_ehci_qtd_t *)ehciQtdStart->nextQtdPointer; + } + ehciInstance->ehciQtdNumber++; + USB_HostEhciUnlock(); + + return length; +} + +static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint8_t needStop = 0; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ + /* remove qtd from qh */ + if ((!((uint32_t)vltQhPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)) || + (!((uint32_t)vltQhPointer->currentQtdPointer & EHCI_HOST_T_INVALID_VALUE))) + { + /* need stop async schedule */ + if ((!(vltQhPointer->horizontalLinkPointer & EHCI_HOST_T_INVALID_VALUE)) && + (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT)) + { + needStop = 1; + } + if (needStop) + { + USB_HostEhciStopAsync(ehciInstance); + } + vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if (needStop) + { + USB_HostEhciStartAsync(ehciInstance); + } + } + + /* remove transfer from the QH transfer list */ + transfer = vltQhPointer->ehciTransferHead; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + /* release qtd and transfer callback*/ + while (transfer != NULL) + { + nextTransfer = transfer->next; /* the transfer is released when call back */ + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_transfer_t *preSearchTransfer; + uint32_t qhNextQtdValue; + uint32_t qtdPointerEntry; + uint32_t *searchQtdEntryPointer; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ + /* remove qtd from qh */ + qhNextQtdValue = (uint32_t)vltQhPointer->currentQtdPointer; + qtdPointerEntry = *((uint32_t *)qhNextQtdValue + 2); /* note: qtdPointerEntry means qtd status */ + if ((qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE) || (!(qtdPointerEntry & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) + { + qhNextQtdValue = (uint32_t)vltQhPointer->nextQtdPointer; + } + if (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) /* there is pending qtd in the qh */ + { + /* this qh don't schedule temporarily */ + if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) + { + USB_HostEhciStopAsync(ehciInstance); + } + vltQhPointer->currentQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ + vltQhPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) + { + USB_HostEhciStartAsync(ehciInstance); + } + + /* remove qtd from qh one by one */ + qtdPointerEntry = transfer->union1.unitHead; + while (1) + { + /* search qh's qtd list for qtdPointerEntry */ + searchQtdEntryPointer = &qhNextQtdValue; + while (!((*searchQtdEntryPointer) & EHCI_HOST_T_INVALID_VALUE)) + { + if ((*searchQtdEntryPointer) == qtdPointerEntry) + { + *searchQtdEntryPointer = *((uint32_t *)qtdPointerEntry); /* remove the qtd from qh */ + break; + } + else + { + searchQtdEntryPointer = (uint32_t *)(*searchQtdEntryPointer); + } + } + if (qtdPointerEntry == transfer->union2.unitTail) + { + break; + } + qtdPointerEntry = *((uint32_t *)qtdPointerEntry); + } + } + + /* remove transfer from the QH transfer list */ + preSearchTransfer = vltQhPointer->ehciTransferHead; + if (preSearchTransfer == transfer) + { + vltQhPointer->ehciTransferHead = preSearchTransfer->next; + } + else + { + while (preSearchTransfer != NULL) + { + if (preSearchTransfer->next == transfer) + { + preSearchTransfer->next = transfer->next; + break; + } + else + { + preSearchTransfer = preSearchTransfer->next; + } + } + } + USB_HostEhciUnlock(); + + /* release qtd and callback */ + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = + (transfer->transferLength < transfer->transferSofar) ? 0 : (transfer->transferLength - transfer->transferSofar); + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + + /* start this qh schedule */ + vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if ((qhNextQtdValue != 0) && (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE))) + { + vltQhPointer->nextQtdPointer = qhNextQtdValue; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer = NULL; + uint32_t address, speed, portNumber, hubNumber; + uint32_t controlBits1 = 0; + uint32_t controlBits2 = 0; + /* get qh */ + USB_HostEhciLock(); + if (ehciInstance->ehciQhList != NULL) + { + qhPointer = (usb_host_ehci_qh_t *)ehciInstance->ehciQhList; + ehciInstance->ehciQhList = + (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); + } + USB_HostEhciUnlock(); + if (qhPointer == NULL) + { +#ifdef HOST_EHCO + usb_echo("get qh error\r\n"); +#endif + return kStatus_USB_Error; + } + ehciPipePointer->ehciQh = (void *)qhPointer; + + /* initialize qh */ + USB_HostEhciZeroMem((uint32_t *)qhPointer, sizeof(usb_host_ehci_qh_t) / 4); + qhPointer->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->ehciPipePointer = ehciPipePointer; + qhPointer->timeOutLabel = 0; + qhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + /* initialize staticEndpointStates[0] */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) + { + /* Software should set the RL field to zero if the queue head is an interrupt endpoint. */ + controlBits1 |= ((0U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + else + { + if (ehciPipePointer->pipeCommon.nakCount >= 16) + { + controlBits1 |= ((15U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + else + { + controlBits1 |= + (((uint32_t)ehciPipePointer->pipeCommon.nakCount << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + } + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + if (speed != USB_SPEED_HIGH) + { + controlBits1 |= (1 << EHCI_HOST_QH_C_SHIFT); + } + controlBits1 |= (1 << EHCI_HOST_QH_DTC_SHIFT); + } + controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT); + controlBits1 |= (speed << EHCI_HOST_QH_EPS_SHIFT); + controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_QH_ENDPT_SHIFT); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + controlBits1 |= (address << EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT); + qhPointer->staticEndpointStates[0] = controlBits1; + if (speed == USB_SPEED_HIGH) + { + controlBits2 |= ((uint32_t)ehciPipePointer->pipeCommon.numberPerUframe << EHCI_HOST_QH_MULT_SHIFT); + } + else + { + controlBits2 |= (0x00000001U << EHCI_HOST_QH_MULT_SHIFT); + } + /*initialize staticEndpointStates[1] */ + if (speed != USB_SPEED_HIGH) + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubPort, + &portNumber); + } + else + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, + &portNumber); + } + controlBits2 |= (portNumber << EHCI_HOST_QH_PORT_NUMBER_SHIFT); + controlBits2 |= (hubNumber << EHCI_HOST_QH_HUB_ADDR_SHIFT); + controlBits2 |= ((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_QH_UFRAME_CMASK_SHIFT); + controlBits2 |= ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_QH_UFRAME_SMASK_SHIFT); + qhPointer->staticEndpointStates[1] = controlBits2; + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer; + + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* de-initialize qtd from qh */ + USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); + + /* release QH */ + USB_HostEhciLock(); + qhPointer->horizontalLinkPointer = (uint32_t)ehciInstance->ehciQhList; + ehciInstance->ehciQhList = qhPointer; + USB_HostEhciUnlock(); + + return kStatus_USB_Success; +} + +static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos, + uint16_t uframeInterval) +{ + volatile uint32_t *frameEntryPointer; + uint32_t frameEntryValue; + + /* search for the inserting point by interval */ + frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); + while (frameEntryPointer) + { + frameEntryValue = *frameEntryPointer; + if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) + { + /* insert into the end */ + *((uint32_t *)entryPointerValue) = EHCI_HOST_T_INVALID_VALUE; + *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); + break; + } + + if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) + { + return; /* has inserted */ + } + if (((frameEntryValue & EHCI_HOST_POINTER_TYPE_MASK) == EHCI_HOST_POINTER_TYPE_QH) && + (((usb_host_ehci_qh_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK)) + ->ehciPipePointer->uframeInterval <= uframeInterval)) + { + /* insert into this point */ + *((uint32_t *)entryPointerValue) = frameEntryValue; + *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); + return; + } + else + { + frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + } +} + +static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos) +{ + volatile uint32_t *frameEntryPointer; + uint32_t frameEntryValue; + + /* search for the qh/itd/sitd entry */ + frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); + + while (frameEntryPointer) + { + frameEntryValue = *frameEntryPointer; + if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) + { + return; + } + + if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) + { + /* remove the entry */ + *frameEntryPointer = *((uint32_t *)entryPointerValue); + break; + } + else + { + frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + } +} + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) +static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + void *startEntryPointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_ehci_sitd_t *sitdPointer; + uint32_t distance; + uint32_t frameInterval; + int32_t shouldLinkFrame; + int32_t currentFrame; + + frameInterval = (ehciPipePointer->uframeInterval >> 3); + + if (isoPointer->lastLinkFrame == 0xFFFF) /* first link */ + { + currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + currentFrame = ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & + (EHCI_MAX_UFRAME_VALUE >> 3)); /* add USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER */ + /* frame should align with interval */ + currentFrame -= ehciPipePointer->startFrame; + currentFrame = + ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); /* frameInterval is power of 2 */ + currentFrame += ehciPipePointer->startFrame; + } + else + { + shouldLinkFrame = isoPointer->lastLinkFrame + frameInterval; /* continuous next should link frame */ + if (shouldLinkFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + shouldLinkFrame = shouldLinkFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + distance = ((shouldLinkFrame - currentFrame + (EHCI_MAX_UFRAME_VALUE >> 3) + 1) & + (EHCI_MAX_UFRAME_VALUE >> 3)); /* get the distance from shouldLinkFrame to currentFrame */ + /* shouldLinkFrame has add frameInterval, think about the align with interval, so here add (frameInterval * + * 2) */ + if ((distance <= (USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER + frameInterval * 2)) && (distance > 0)) + { + currentFrame = shouldLinkFrame; + } + else /* re-link */ + { + currentFrame = + ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & (EHCI_MAX_UFRAME_VALUE >> 3)); + if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + /* frame should align with interval */ + currentFrame -= ehciPipePointer->startFrame; + currentFrame = ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); + currentFrame += ehciPipePointer->startFrame; + } + } + if (currentFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) /* frame turn around */ + { + shouldLinkFrame = + (currentFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); /* shouldLinkFrame means inserted frame position */ + } + else + { + shouldLinkFrame = currentFrame; /* shouldLinkFrame means inserted frame position */ + } + + sitdPointer = (usb_host_ehci_sitd_t *)startEntryPointer; + while (sitdPointer) + { + sitdPointer->frameEntryIndex = shouldLinkFrame; + /* add to frame list head */ + sitdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame]; + ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame] = + ((uint32_t)sitdPointer | EHCI_HOST_POINTER_TYPE_SITD); + if (sitdPointer->nextSitdIndex == 0xFF) /* 0xFF is invalid value */ + { + break; + } + sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); /* next sitd */ + + shouldLinkFrame += frameInterval; + currentFrame += frameInterval; + if (shouldLinkFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) + { + shouldLinkFrame = (shouldLinkFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); + } + } + + if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + isoPointer->lastLinkFrame = currentFrame; /* save the last link frame value */ +} + +static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_iso_t *isoPointer; + uint32_t sitdNumber = 0; + usb_host_ehci_sitd_t *sitdPointer; + uint32_t dataLength = 0; + uint32_t sitdLength = 0; + uint32_t dataBufferValue; + uint32_t hubNumber; + uint32_t portNumber; + uint32_t address; + uint32_t tmp; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + + sitdNumber = ((transfer->transferLength - 1 + (ehciPipePointer->pipeCommon.maxPacketSize)) / + (ehciPipePointer->pipeCommon.maxPacketSize)); + /* get sitd array */ + tmp = ehciPipePointer - ehciInstance->ehciPipeIndexBase; /* pipe index */ + /* USB_HostEhciLock(); */ + if (ehciInstance->ehciSitdNumber >= sitdNumber) + { + sitdPointer = ehciInstance->ehciSitdList; + transfer->union1.unitHead = (uint32_t)sitdPointer; + for (index = 1; index < sitdNumber; ++index) + { + sitdPointer->nextSitdIndex = + (((usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer) - ehciInstance->ehciSitdIndexBase); + sitdPointer = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; + } + sitdPointer->nextSitdIndex = 0xFF; + ehciInstance->ehciSitdList = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; + ehciInstance->ehciSitdNumber -= sitdNumber; + } + else + { + /* USB_HostEhciUnlock(); */ + return kStatus_USB_Error; + } + /* USB_HostEhciUnlock(); */ + transfer->union2.unitTail = (uint32_t)sitdPointer; + /* initialize sitd array */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, + &portNumber); + sitdPointer = (usb_host_ehci_sitd_t *)transfer->union1.unitHead; + dataLength = transfer->transferLength; + while (sitdNumber--) + { + USB_HostEhciZeroMem((uint32_t *)sitdPointer, 7); + sitdLength = dataLength; + if (sitdLength > ehciPipePointer->pipeCommon.maxPacketSize) + { + sitdLength = ehciPipePointer->pipeCommon.maxPacketSize; + } + dataBufferValue = (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); + dataLength -= sitdLength; /* update left data length */ + sitdPointer->transferResults[1] = dataBufferValue; + sitdPointer->transferResults[2] = ((dataBufferValue + 4 * 1024) & 0xFFFFF000U); + sitdPointer->endpointStates[0] = + (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_SITD_DIRECTION_SHIFT) | + (portNumber << EHCI_HOST_SITD_PORT_NUMBER_SHIFT) | (hubNumber << EHCI_HOST_SITD_HUB_ADDR_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_SITD_ENDPT_SHIFT) | + (address << EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT)); + sitdPointer->transferResults[0] = + ((sitdLength << EHCI_HOST_SITD_TOTAL_BYTES_SHIFT) | (EHCI_HOST_SITD_STATUS_ACTIVE_MASK)); + + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + sitdPointer->endpointStates[1] = (((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_SITD_CMASK_SHIFT) | + ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_SITD_SMASK_SHIFT)); + + tmp = (sitdLength + 187) / 188; + if (tmp > 1) + { + sitdPointer->transferResults[2] |= (0x01 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ + } + else + { + sitdPointer->transferResults[2] |= (0x00 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ + } + sitdPointer->transferResults[2] |= (tmp << EHCI_HOST_SITD_TCOUNT_SHIFT); /* for iso split */ + } + + sitdPointer->backPointer = EHCI_HOST_T_INVALID_VALUE; + + sitdPointer = (ehciInstance->ehciSitdIndexBase + sitdPointer->nextSitdIndex); + } + sitdPointer = (usb_host_ehci_sitd_t *)transfer->union2.unitTail; + sitdPointer->transferResults[0] |= (1U << EHCI_HOST_SITD_IOC_SHIFT); /* last set IOC */ + + /* link transfer to usb_host_ehci_iso_t transfer list */ + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + USB_HostEhciLock(); + if (isoPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + isoPointer->ehciTransferTail->next = transfer; + isoPointer->ehciTransferTail = transfer; + } + USB_HostEhciUnlock(); + + /* link itd to frame list (note: initialize frameEntryIndex)*/ + USB_HostEhciLinkSitd(ehciInstance, ehciPipePointer, (void *)transfer->union1.unitHead); + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_sitd_t *startSitdPointer, + usb_host_ehci_sitd_t *endSitdPointer) +{ + usb_host_ehci_sitd_t *sitdPointer = startSitdPointer; + uint32_t leftLength = 0; + /* remove itd from frame list */ + while (1) + { + /* record the transfer's result length */ + leftLength += + ((sitdPointer->transferResults[0] & EHCI_HOST_SITD_TOTAL_BYTES_MASK) >> EHCI_HOST_SITD_TOTAL_BYTES_SHIFT); + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)sitdPointer, + sitdPointer->frameEntryIndex); /* remove from the inserted frame list */ + + /* release itd */ + /* USB_HostEhciLock(); */ + sitdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciSitdList; + ehciInstance->ehciSitdList = sitdPointer; + ehciInstance->ehciSitdNumber++; + /* USB_HostEhciUnlock(); */ + + if (sitdPointer == endSitdPointer) + { + break; + } + + sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); + } + + return leftLength; +} + +static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + + /* firstly remove the transfer (because host task may occupy to access the resource) */ + USB_HostEhciLock(); + transfer = isoPointer->ehciTransferHead; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + while (transfer != NULL) + { + nextTransfer = transfer->next; + /* remove sitd from frame list and release itd */ + transfer->transferSofar = + transfer->transferLength - USB_HostEhciSitdArrayRelease(ehciInstance, + (usb_host_ehci_sitd_t *)transfer->union1.unitHead, + (usb_host_ehci_sitd_t *)transfer->union2.unitTail); + /* transfer callback */ + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + /* next transfer */ + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) +static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t lastLinkUframe, + uint16_t startUframe, + uint16_t uframeInterval) +{ + int32_t shouldLinkUframe; + int32_t currentUframe; + int32_t distance; + + if (lastLinkUframe != 0xFFFF) + { + shouldLinkUframe = lastLinkUframe + uframeInterval; + if (shouldLinkUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) + { + shouldLinkUframe = shouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + distance = ((shouldLinkUframe - currentUframe + EHCI_MAX_UFRAME_VALUE + 1) & + EHCI_MAX_UFRAME_VALUE); /* get the distance */ + /* shouldLinkUframe has add uframeInterval, think about the align with interval, so here add (uframeInterval + * * 2) */ + if ((distance <= (int32_t)(USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER + (uframeInterval * 2))) && (distance > 2)) + { + currentUframe = shouldLinkUframe; + } + else /* re-link */ + { + currentUframe = + ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); + if (currentUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) + { + currentUframe = currentUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + /* uframe should align with interval */ + currentUframe -= startUframe; + currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & + (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ + currentUframe += startUframe; + } + } + else + { + currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + currentUframe = ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); + /* uframe should align with interval */ + currentUframe -= startUframe; + currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & + (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ + currentUframe += startUframe; + } + + return currentUframe; +} + +static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_iso_t *isoPointer; + usb_host_ehci_itd_t *itdPointer = NULL; + usb_host_ehci_itd_t *tmpItdPointer; + uint32_t dataLength; /* the remaining data for sending */ + uint32_t transactionLength; /* the initializing transaction descriptor data length */ + uint32_t itdBufferValue; + uint32_t itdBufferBaseValue; /* for calculating PG value */ + uint32_t address; + uint32_t lastShouldLinkUframe; + uint32_t linkUframe; + uint32_t minDataPerItd = ehciPipePointer->pipeCommon.numberPerUframe * ehciPipePointer->pipeCommon.maxPacketSize; + uint8_t maxItdNumber; + uint8_t index = 0; + + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + + /* max needed itd number, the actual needed number may be less because micro-frame interval may be less than 8 */ + maxItdNumber = ((transfer->transferLength - 1 + minDataPerItd) / minDataPerItd); + if (ehciPipePointer->uframeInterval < 8) + { + maxItdNumber = ((maxItdNumber * ehciPipePointer->uframeInterval + 7) / 8) + 1; + } + if (maxItdNumber > ehciInstance->ehciItdNumber) + { + return kStatus_USB_Error; + } + + /* link transfer to usb_host_ehci_iso_t transfer list */ + transfer->next = NULL; + /* USB_HostEhciLock(); */ + if (isoPointer->ehciTransferHead == NULL) + { + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; + } + else + { + isoPointer->ehciTransferTail->next = transfer; + isoPointer->ehciTransferTail = transfer; + } + /* USB_HostEhciUnlock(); */ + + dataLength = transfer->transferLength; + transfer->union1.unitHead = (uint32_t)NULL; + /* get the link micro-frame */ + lastShouldLinkUframe = USB_HostEhciGetItdLinkFrame( + ehciInstance, isoPointer->lastLinkFrame, + (uint16_t)((ehciPipePointer->startFrame << 3) + ehciPipePointer->startUframe), ehciPipePointer->uframeInterval); + if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) + { + linkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + else + { + linkUframe = lastShouldLinkUframe; + } + while (dataLength) + { + /* get one idle itd */ + tmpItdPointer = ehciInstance->ehciItdList; + ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)tmpItdPointer->nextLinkPointer; + ehciInstance->ehciItdNumber -= 1; + if (tmpItdPointer == NULL) + { + return kStatus_USB_Error; /* this should not reach */ + } + tmpItdPointer->nextItdPointer = NULL; + + /* use the itd */ + if (transfer->union1.unitHead == (uint32_t)NULL) /* first itd */ + { + transfer->union1.unitHead = (uint32_t)tmpItdPointer; + } + else /* link itd list */ + { + itdPointer->nextItdPointer = tmpItdPointer; + } + itdPointer = tmpItdPointer; + + /* itd has been set to all zero when releasing */ + itdBufferBaseValue = itdBufferValue = + (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); + for (index = 0; index < 7; ++index) + { + itdPointer->bufferPointers[index] = ((itdBufferBaseValue + (index * 4 * 1024)) & 0xFFFFF000U); + } + /* initialize iTD common fields */ + itdPointer->bufferPointers[0] |= + (((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_ITD_ENDPT_SHIFT) | + (address << EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT)); + itdPointer->bufferPointers[1] |= + (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_ITD_DIRECTION_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT)); + itdPointer->bufferPointers[2] |= (ehciPipePointer->pipeCommon.numberPerUframe); + /* initialize transaction descriptors */ + for (index = (linkUframe & 0x0007); index < 8; index += ehciPipePointer->uframeInterval) + { + transactionLength = ((dataLength > minDataPerItd) ? minDataPerItd : dataLength); + /* initialize the uframeIndex's transaction descriptor in itd */ + itdPointer->transactions[index] = + ((EHCI_HOST_ITD_STATUS_ACTIVE_MASK) | (transactionLength << EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT) | + ((((itdBufferValue & 0xFFFFF000U) - (itdBufferBaseValue & 0xFFFFF000U)) >> + EHCI_HOST_ITD_BUFFER_POINTER_SHIFT) + << EHCI_HOST_ITD_PG_SHIFT) | + (itdBufferValue & EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK)); + dataLength -= transactionLength; + itdBufferValue += transactionLength; + if (dataLength <= 0) + { + break; + } + } + } + + transfer->union2.unitTail = (uint32_t)itdPointer; + itdPointer->transactions[index] |= (1 << EHCI_HOST_ITD_IOC_SHIFT); /* last set IOC */ + + /* link itd to frame list (note: initialize frameEntryIndex)*/ + while (itdPointer) + { + itdPointer->frameEntryIndex = linkUframe; + /* add to frame head */ + itdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3]; + *(uint32_t *)((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3] = + ((uint32_t)itdPointer | EHCI_HOST_POINTER_TYPE_ITD); + itdPointer = itdPointer->nextItdPointer; + if (itdPointer == NULL) + { + break; + } + + linkUframe += ehciPipePointer->uframeInterval; + lastShouldLinkUframe += ehciPipePointer->uframeInterval; + if (linkUframe >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)) + { + linkUframe = (linkUframe - (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)); + } + } + + if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) + { + lastShouldLinkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + isoPointer->lastLinkFrame = lastShouldLinkUframe; + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_itd_t *startItdPointer, + usb_host_ehci_itd_t *endItdPointer) +{ + usb_host_ehci_itd_t *itdPointer = startItdPointer; + uint8_t index; + uint32_t doneLength = 0; + + /* remove itd from frame list */ + while (1) + { + /* record the transfer's result length */ + for (index = 0; index < 8; ++index) + { + doneLength += ((itdPointer->transactions[index] & EHCI_HOST_ITD_TRANSACTION_LEN_MASK) >> + EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT); + } + + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)itdPointer, + itdPointer->frameEntryIndex); /* remove from the inserted frame list */ + + /* release itd */ + /* USB_HostEhciLock(); */ + USB_HostEhciZeroMem((uint32_t *)itdPointer, sizeof(usb_host_ehci_itd_t) >> 2); + itdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciItdList; + ehciInstance->ehciItdList = itdPointer; + ehciInstance->ehciItdNumber++; + /* USB_HostEhciUnlock(); */ + + if (itdPointer == endItdPointer) + { + break; + } + itdPointer = itdPointer->nextItdPointer; + } + + return doneLength; +} + +static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint32_t doneLength = 0; + + /* firstly remove the transfer (because host task may occupy to access the resource) */ + USB_HostEhciLock(); + transfer = isoPointer->ehciTransferHead; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + while (transfer != NULL) + { + nextTransfer = transfer->next; + doneLength = 0; + /* remove itd from frame list and release itd */ + doneLength = USB_HostEhciItdArrayRelease(ehciInstance, (usb_host_ehci_itd_t *)transfer->union1.unitHead, + (usb_host_ehci_itd_t *)transfer->union2.unitTail); + + /* transfer callback */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + doneLength = transfer->transferLength; + } + transfer->transferSofar = doneLength; + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + + /* next transfer */ + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer; + + if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) /* initialize control/bulk qh */ + { + return kStatus_USB_Error; + } + + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + /* add qh to async */ + qhPointer->horizontalLinkPointer = ehciInstance->shedFirstQh->horizontalLinkPointer; + ehciInstance->shedFirstQh->horizontalLinkPointer = ((uint32_t)qhPointer | EHCI_HOST_POINTER_TYPE_QH); + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + volatile usb_host_ehci_qh_t *vltPrevQhPointer; + uint32_t horizontalLinkValue; + + /* remove qh from async schedule */ + if ((ehciInstance->shedFirstQh->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK) == + (uint32_t)ehciPipePointer->ehciQh) /* the removing qh is the first qh in the async list */ + { + USB_HostEhciStopAsync(ehciInstance); + ehciInstance->shedFirstQh->horizontalLinkPointer = + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; + USB_HostEhciStartAsync(ehciInstance); + } + else + { + /* search for the removing qh from the async list */ + vltPrevQhPointer = ehciInstance->shedFirstQh; + while (vltPrevQhPointer != NULL) + { + horizontalLinkValue = vltPrevQhPointer->horizontalLinkPointer; + if ((horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE) || + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh) || + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciInstance->shedFirstQh)) + { + break; + } + + vltPrevQhPointer = (volatile usb_host_ehci_qh_t *)(horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + + /* remove the qh from async list */ + if ((vltPrevQhPointer != NULL) && (!(horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) && + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh)) + { + USB_HostEhciStopAsync(ehciInstance); + vltPrevQhPointer->horizontalLinkPointer = + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; + USB_HostEhciStartAsync(ehciInstance); + } + } + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer = + EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ + return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initialize qh and release qh */ +} + +static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status = kStatus_USB_Success; + uint32_t frameIndex; + + /* allocate bandwidth */ + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + status = USB_HostBandwidthHsHostAllocateInterrupt(ehciInstance, ehciPipePointer); /* host works as high-speed */ + } + else + { + status = USB_HostBandwidthFslsHostAllocate(ehciInstance, + ehciPipePointer); /* host works as full-speed or low-speed */ + } + + if (status != kStatus_USB_Success) + { + return status; + } + if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) + { + return kStatus_USB_Error; + } + + /* insert QH to frame list */ + for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += (ehciPipePointer->uframeInterval / 8)) + { + USB_HostEhciAddQhToFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex, + ehciPipePointer->uframeInterval); + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + uint32_t frameIndex; + + /* remove from frame list */ + for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += (ehciPipePointer->uframeInterval / 8)) + { + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex); + } + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer |= + EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ + + return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initilaze qh and release qh */ +} + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + +static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer; + usb_status_t status = kStatus_USB_Success; + + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + status = USB_HostBandwidthHsHostAllocateIso( + ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as high-speed */ + } + else + { + status = USB_HostBandwidthFslsHostAllocate( + ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as full-speed or low-speed */ + } + + if (status != kStatus_USB_Success) + { + return status; + } + + /* get usb_host_ehci_iso_t */ + if (ehciInstance->ehciIsoList == NULL) + { + return kStatus_USB_Error; + } + USB_HostEhciLock(); + isoPointer = ehciInstance->ehciIsoList; + ehciInstance->ehciIsoList = ehciInstance->ehciIsoList->next; + USB_HostEhciUnlock(); + isoPointer->lastLinkFrame = 0xFFFF; + ehciPipePointer->ehciQh = isoPointer; + + return status; +} + +static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer; + uint32_t speed; + + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + + if (isoPointer->ehciTransferHead != NULL) + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd list and free them */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd list and free them */ +#endif + } + } + + /* release usb_host_ehci_iso_t */ + USB_HostEhciLock(); + isoPointer->next = ehciInstance->ehciIsoList; + ehciInstance->ehciIsoList = isoPointer; + USB_HostEhciUnlock(); + return kStatus_USB_Success; +} + +#endif + +static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance) +{ + /* reset controller */ + ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RST_MASK; + while (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_RST_MASK) + { + } +/* set host mode */ +#if (ENDIANNESS == USB_LITTLE_ENDIAN) + ehciInstance->ehciIpBase->USBMODE |= 0x03; +#else + ehciInstance->ehciIpBase->USBMODE |= (0x03 | (0x01 << USBHS_USBMODE_ES_SHIFT)); +#endif + /* check frame list size */ + if (!(ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK)) + { +#if ((USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE < 8) || (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE > 1024)) + return kStatus_USB_Error; +#endif +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE & (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE - 1)) + return kStatus_USB_Error; /* frame size must be 1024/512/256/128/64/32/16/8 */ +#endif + } + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t tmp = 0; + + if (ehciInstance->ehciIpBase->HCSPARAMS & USBHS_HCSPARAMS_PPC_MASK) /* Ports have power port switches */ + { + /* only has one port */ + tmp = ehciInstance->ehciIpBase->PORTSC1; + tmp &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (tmp | USBHS_PORTSC1_PP_MASK); /* turn on port power */ + } + + /* set frame list size */ + if (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK) + { +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE <= 64) + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_FS2_MASK); +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 64) + ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 32) + ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 16) + ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 8) + ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); +#endif +#else +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 1024) + ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 512) + ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 256) + ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 128) + ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); +#endif +#endif + } + + /* start the controller */ + ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RS_MASK; + + /* set timer0 */ + ehciInstance->ehciIpBase->GPTIMER0LD = (300 * 1000 - 1); /* 100ms */ + + /* enable interrupt (USB interrupt enable + USB error interrupt enable + port change detect enable + system error + * enable + interrupt on async advance enable) + general purpos Timer 0 Interrupt enable */ + ehciInstance->ehciIpBase->USBINTR |= (0x1000037); + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_qh_t *qhPointer; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + usb_host_ehci_iso_t *isoPointer; + uint32_t speed; +#endif + uint8_t cancelPipe = 0; + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_INTERRUPT: + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + if (qhPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ + { + return kStatus_USB_Success; + } + if (transfer != NULL) + { + if ((qhPointer->ehciTransferHead == transfer) && + (qhPointer->ehciTransferHead == qhPointer->ehciTransferTail)) /* only has this one transfer */ + { + cancelPipe = 1; + } + else + { + cancelPipe = 0; + } + } + else + { + cancelPipe = 1; + } + if (cancelPipe == 1) /* cancel all pipe */ + { + USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); /* release all the qtd */ + } + else /* cancel one transfer */ + { + USB_HostEhciTransferQtdListDeinit(ehciInstance, ehciPipePointer, transfer); + } + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + if (isoPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ + { + return kStatus_USB_Success; + } + /* cancel all pipe, don't implement canceling transfer for iso */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd */ +#endif + } + break; +#endif + + default: + break; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl) +{ + usb_status_t status = kStatus_USB_Success; + uint32_t portScRegister; + + switch (busControl) + { + case kUSB_HostBusReset: + /* reset port */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); + while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + } + break; + + case kUSB_HostBusRestart: + ehciInstance->deviceAttached = kEHCIDeviceDetached; + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ + break; + + case kUSB_HostBusEnableAttach: /* enable device attach */ + if (ehciInstance->deviceAttached == kEHCIDeviceDetached) + { + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ + } + break; + + case kUSB_HostBusDisableAttach: /* disable device attach */ + ehciInstance->ehciIpBase->USBINTR &= (~USBHS_USBINTR_PCE_MASK); /* disable ehci port change interrupt */ + break; +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + case kUSB_HostBusSuspend: + if (ehciInstance->ehciIpBase->PORTSC1 && USBHS_PORTSC1_CCS_MASK) + { + /* set timer1 */ + ehciInstance->ehciIpBase->GPTIMER1LD = (1 * 1000); /* 1ms */ + ehciInstance->ehciIpBase->GPTIMER1CTL |= + (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); + + USB_HostEhciStopAsync(ehciInstance); + USB_HostEhciStopPeriodic(ehciInstance); + while (ehciInstance->ehciIpBase->USBSTS & (USBHS_USBSTS_PS_MASK | USBHS_USBSTS_AS_MASK)) + { + __ASM("nop"); + } + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKCN_MASK; + ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_WKDS_MASK; + ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_SUSP_MASK); /* Suspend the device */ + + ehciInstance->matchTick = 0U; + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_TIE1_MASK); + ehciInstance->busSuspendStatus = kBus_EhciStartSuspend; + } + else + { + status = kStatus_USB_Error; + } + break; + case kUSB_HostBusResume: + ehciInstance->ehciIpBase->PORTSC1 &= ~(USBHS_PORTSC1_SUSP_MASK); /* Clear Suspend bit */ + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + if (ehciInstance->deviceAttached != kEHCIDeviceDetached) + { + ehciInstance->busSuspendStatus = kBus_EhciStartResume; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_FPR_MASK); /* Resume the device */ + } + else + { + status = kStatus_USB_Error; + } + break; +#endif + default: + status = kStatus_USB_Error; + break; + } + return status; +} + +void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) +{ + /* process async QH */ + usb_host_ehci_pipe_t *ehciPipePointer; + usb_host_ehci_pipe_t *ehciClearPipePointer = NULL; + volatile usb_host_ehci_qh_t *vltQhPointer; + volatile usb_host_ehci_qtd_t *vltQtdPointer; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint32_t qtdStatus = 0; +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + volatile usb_host_ehci_itd_t *vltItdPointer; + uint8_t index = 0; +#endif +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + volatile usb_host_ehci_sitd_t *vltSitdPointer; +#endif +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + usb_host_ehci_iso_t *isoPointer; + uint32_t dataLength; + uint32_t speed; +#endif + + ehciPipePointer = ehciInstance->ehciRunningPipeList; /* check all the running pipes */ + while (ehciPipePointer != NULL) + { + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_INTERRUPT: + case USB_ENDPOINT_CONTROL: + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ + transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ + while (transfer != NULL) + { + nextTransfer = transfer->next; + /* normal case */ + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + if ((vltQtdPointer->transferResults[0] & (EHCI_HOST_QTD_IOC_MASK)) && + (!(vltQtdPointer->transferResults[0] & + EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) /* transfer is done */ + { + qtdStatus = (vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_STATUS_ERROR_MASK); + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutLabel = 0; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + if (qtdStatus) /* has errors */ + { + if (!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) + { + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + } + if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferFailed); /* transfer fail */ + } + else + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferStall); /* transfer stall */ + } + } + else + { + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) && + (transfer->setupPacket->bRequest == USB_REQUEST_STANDARD_CLEAR_FEATURE) && + (transfer->setupPacket->bmRequestType == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) && + ((USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wValue) & 0x00FFu) == + USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT)) + { + ehciClearPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciClearPipePointer != NULL) + { + /* only compute bulk and interrupt pipe */ + if (((ehciClearPipePointer->pipeCommon.endpointAddress | + (ehciClearPipePointer->pipeCommon.direction + << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) == + (uint8_t)(USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wIndex))) && + (ehciClearPipePointer->pipeCommon.deviceHandle == + ehciPipePointer->pipeCommon.deviceHandle)) + { + break; + } + ehciClearPipePointer = + (usb_host_ehci_pipe_t *)ehciClearPipePointer->pipeCommon.next; + } + + if ((ehciClearPipePointer != NULL) && + ((ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) || + (ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_BULK))) + { + ((volatile usb_host_ehci_qh_t *)(ehciClearPipePointer->ehciQh)) + ->transferOverlayResults[0] &= (~EHCI_HOST_QTD_DT_MASK); + } + } + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer success */ + } + } + else if ((!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) && + (vltQhPointer->transferOverlayResults[0] & + EHCI_HOST_QH_STATUS_ERROR_MASK)) /* there is error and transfer is done */ + { + qtdStatus = (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QH_STATUS_ERROR_MASK); + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)(vltQhPointer->currentQtdPointer); + + if (((uint32_t)vltQtdPointer & EHCI_HOST_T_INVALID_VALUE) || + (vltQtdPointer == NULL)) /* the error status is unreasonable */ + { + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + } + else + { + /* remove qtd from qh */ + while ((vltQtdPointer != NULL) && (!(vltQtdPointer->transferResults[0] & + EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */ + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; + } + + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if (vltQtdPointer != NULL) + { + vltQhPointer->nextQtdPointer = vltQtdPointer->nextQtdPointer; + } + + transfer->transferSofar = USB_HostEhciQtdListRelease( + ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutLabel = 0; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferFailed); /* transfer fail */ + } + else + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferStall); /* transfer stall */ + } + } + } + else + { + break; + } + transfer = nextTransfer; + } + break; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + qtdStatus = 0; /* qtdStatus means break here, because there is only one break in while for misra */ + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; /* pipe's usb_host_ehci_iso_t */ + transfer = isoPointer->ehciTransferHead; /* usb_host_ehci_iso_t's transfer */ + while (transfer != NULL) + { + nextTransfer = transfer->next; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, + kUSB_HostGetDeviceSpeed, &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + vltItdPointer = + (volatile usb_host_ehci_itd_t *)(transfer->union2.unitTail); /* transfer's last itd */ + for (index = 0; index < 8; ++index) + { + if (vltItdPointer->transactions[index] & EHCI_HOST_ITD_STATUS_ACTIVE_MASK) + { + break; + } + } + if (index == 8) /* transfer is done */ + { + /* remove itd from frame list and release itd */ + dataLength = USB_HostEhciItdArrayRelease(ehciInstance, + (usb_host_ehci_itd_t *)transfer->union1.unitHead, + (usb_host_ehci_itd_t *)transfer->union2.unitTail); + transfer->transferSofar = dataLength; + isoPointer->ehciTransferHead = transfer->next; + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer callback success */ + /* TODO: iso callback error */ + } + else + { + qtdStatus = 1; /* break */ + } +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + vltSitdPointer = + (volatile usb_host_ehci_sitd_t *)(transfer->union2.unitTail); /* transfer's last sitd */ + if (!(vltSitdPointer->transferResults[0] & + EHCI_HOST_SITD_STATUS_ACTIVE_MASK)) /* transfer is done */ + { + /* remove sitd from frame list and release itd */ + dataLength = USB_HostEhciSitdArrayRelease( + ehciInstance, (usb_host_ehci_sitd_t *)transfer->union1.unitHead, + (usb_host_ehci_sitd_t *)transfer->union2.unitTail); + transfer->transferSofar = dataLength; + isoPointer->ehciTransferHead = transfer->next; + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer callback success */ + /* TODO: iso callback error */ + } + else + { + qtdStatus = 1; /* break */ + } +#endif + } + if (qtdStatus == 1) + { + break; + } + transfer = nextTransfer; + } + break; +#endif + + default: + break; + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) +{ + /* note: only has one port */ + uint32_t portScRegister = ehciInstance->ehciIpBase->PORTSC1; + int32_t sofStart = 0; + int32_t sofCount = 0; + uint32_t index; + + if (portScRegister & USBHS_PORTSC1_CSC_MASK) /* connection status change */ + { + sofStart = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + + /* process CSC bit */ + while (1) + { + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + if (portScRegister & USBHS_PORTSC1_CSC_MASK) + { + /* clear csc bit */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_CSC_MASK); + } + sofCount = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + if (((sofCount - sofStart + EHCI_MAX_UFRAME_VALUE + 1) & EHCI_MAX_UFRAME_VALUE) > + (1 * 8)) /* delay 1ms to clear CSC */ + { + break; + } + } + } + + /* process CCS bit */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + if (portScRegister & USBHS_PORTSC1_CCS_MASK) /* process attach */ + { + if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || + (ehciInstance->deviceAttached == kEHCIDeviceAttached)) + { + return; + } +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); +#endif + for (index = 0; index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY; ++index) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1); + if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)) + { + break; + } + } + if (index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY) /* CCS is cleared */ + { + ehciInstance->deviceAttached = kEHCIDeviceDetached; + return; + } + /* reset port */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); + while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + } + ehciInstance->firstDeviceSpeed = + ((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT); + /* enable ehci phy disconnection */ + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 1); + } + + /* wait for reset */ + USB_HostEhciDelay(ehciInstance->ehciIpBase, USB_HOST_EHCI_PORT_RESET_DELAY); + /* process attach */ + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_ATTACH); + /* gpt timer start */ + ehciInstance->ehciIpBase->GPTIMER0CTL |= + (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); + ehciInstance->deviceAttached = kEHCIDevicePhyAttached; + } + else + { + if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || + (ehciInstance->deviceAttached == kEHCIDeviceAttached)) + { +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); +#endif + /* disable ehci phy disconnection */ + USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 0); + /* disable async and periodic */ + USB_HostEhciStopAsync(ehciInstance); + USB_HostEhciStopPeriodic(ehciInstance); + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_DETACH); + } + } +} + +static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + volatile usb_host_ehci_qtd_t *vltQtdPointer; + usb_host_transfer_t *transfer; + uint32_t backValue; + volatile uint32_t *totalBytesAddress = NULL; + usb_host_ehci_pipe_t *ehciPipePointer = ehciInstance->ehciRunningPipeList; + uint8_t timeoutLabel; + + while (ehciPipePointer != NULL) + { + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ + transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ + if ((transfer != NULL)) /* there is transfering data */ + { + timeoutLabel = 0; + if (ehciInstance->deviceAttached != kEHCIDeviceAttached) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + timeoutLabel = 1; + } + else + { + if (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQhPointer->currentQtdPointer; + totalBytesAddress = &(vltQhPointer->transferOverlayResults[0]); + } + else + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + totalBytesAddress = ((uint32_t *)vltQtdPointer + 2); + } + + backValue = + (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> + EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); /* backValue is used for total bytes to transfer */ + if (vltQhPointer->timeOutLabel != backValue) /* use total bytes to reflect the time out */ + { + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + vltQhPointer->timeOutLabel = backValue; + } + else + { + /* time out when the total bytes don't change for the duration + * USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE + */ + (vltQhPointer->timeOutValue)--; + if (vltQhPointer->timeOutValue == 0) + { + /* stop the qh schedule */ + USB_HostEhciStopAsync(ehciInstance); + if (backValue != (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> + EHCI_HOST_QTD_TOTAL_BYTES_SHIFT)) + { + USB_HostEhciStartAsync(ehciInstance); + } + else + { + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + USB_HostEhciStartAsync(ehciInstance); + timeoutLabel = 1; + } + } + } + } + + if (timeoutLabel == 1) + { + /* remove qtd from qh */ + while ((vltQtdPointer != NULL) && + (!(vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_IOC_MASK)) && + (vltQtdPointer != (usb_host_ehci_qtd_t *)vltQhPointer->ehciTransferTail)) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; + } + if ((vltQtdPointer != NULL) && (!(vltQtdPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE))) + { + vltQhPointer->nextQtdPointer = + vltQtdPointer->nextQtdPointer; /* start qh if there are other qtd that don't belong to + the transfer */ + } + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferFailed); + } + } + break; + default: + break; + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance) +{ + if (ehciInstance->deviceAttached != kEHCIDeviceDetached) + { + if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + + if (0 == ehciInstance->matchTick) + { + ehciInstance->matchTick = hostPointer->hwTick; + } + else + { + if ((hostPointer->hwTick - ehciInstance->matchTick) >= 5) + { + ehciInstance->ehciIpBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + ehciInstance->ehciIpBase->USBSTS |= USBHS_USBSTS_SRI_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#if 0 + ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK + | USBPHY_CTRL_ENIDCHG_WKUP_MASK + | USBPHY_CTRL_ENDPDMCHG_WKUP_MASK + | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK + ; +#endif +#endif + ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; + + ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU; + + while (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) + { + __ASM("nop"); + } + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventSuspended); /* call host callback function */ + ehciInstance->busSuspendStatus = kBus_EhciSuspended; + } + } + } + else if (kBus_EhciStartResume == ehciInstance->busSuspendStatus) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK)) + { + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKDS_MASK; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventResumed); /* call host callback function */ + hostPointer->suspendedDevice = NULL; + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } + } + else + { + } + } + else + { + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } +} +#endif + +usb_status_t USB_HostEhciCreate(uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle) +{ + uint32_t index = 0; + usb_osa_status_t osaStatus; + usb_host_ehci_instance_t *ehciInstance; + uint32_t usbhsBaseAddrs[] = USBHS_BASE_ADDRS; + usb_host_ehci_data_t *usbHostEhciData[] = USB_HOST_EHCI_DATA_ARRAY; + uint8_t *usbHostEhciFrameList[] = USB_HOST_EHCI_FRAME_LIST_ARRAY; + uint32_t *framePointer; + + if ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(usbhsBaseAddrs) / sizeof(usbhsBaseAddrs[0]))) + { + return kStatus_USB_ControllerNotFound; + } + + *controllerHandle = NULL; + ehciInstance = (usb_host_ehci_instance_t *)USB_OsaMemoryAllocate( + sizeof(usb_host_ehci_instance_t)); /* malloc host ehci instance */ + if (ehciInstance == NULL) + { + return kStatus_USB_AllocFail; + } + ehciInstance->controllerId = controllerId; + ehciInstance->hostHandle = upperLayerHandle; + ehciInstance->deviceAttached = kEHCIDeviceDetached; + ehciInstance->ehciIpBase = (USBHS_Type *) + usbhsBaseAddrs[controllerId - kUSB_ControllerEhci0]; /* operate ehci ip through the base address */ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + +#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); +#endif + +#endif + +#endif + + if (USB_HostEhciResetIP(ehciInstance) != kStatus_USB_Success) /* reset ehci ip */ + { + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + + /* initialize ehci frame list */ + ehciInstance->ehciFrameList = usbHostEhciFrameList[ehciInstance->controllerId - kUSB_ControllerEhci0]; + + /* initialize ehci units */ + ehciInstance->ehciUnitBase = (uint32_t *)(usbHostEhciData[ehciInstance->controllerId - kUSB_ControllerEhci0]); + /* initialize qh/qtd/itd/sitd/iso list */ + ehciInstance->ehciQhList = (usb_host_ehci_qh_t *)((uint32_t)(ehciInstance->ehciUnitBase)); + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)((uint32_t)ehciInstance->ehciQhList + + (sizeof(usb_host_ehci_qh_t) * USB_HOST_CONFIG_EHCI_MAX_QH)); + ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)((uint32_t)ehciInstance->ehciQtdHead + + (sizeof(usb_host_ehci_qtd_t) * USB_HOST_CONFIG_EHCI_MAX_QTD)); + ehciInstance->ehciSitdList = ehciInstance->ehciSitdIndexBase = + (usb_host_ehci_sitd_t *)((uint32_t)ehciInstance->ehciItdList + + (sizeof(usb_host_ehci_itd_t) * USB_HOST_CONFIG_EHCI_MAX_ITD)); + ehciInstance->ehciIsoList = (usb_host_ehci_iso_t *)((uint32_t)ehciInstance->ehciSitdList + + (sizeof(usb_host_ehci_sitd_t) * USB_HOST_CONFIG_EHCI_MAX_SITD)); + ehciInstance->ehciPipeIndexBase = + (usb_host_ehci_pipe_t *)((uint32_t)ehciInstance->ehciIsoList + + (sizeof(usb_host_ehci_iso_t) * USB_HOST_EHCI_ISO_NUMBER)); + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QH; ++index) + { + ehciInstance->ehciQhList[index - 1].horizontalLinkPointer = (uint32_t)(&ehciInstance->ehciQhList[index]); + } + ehciInstance->ehciQhList[USB_HOST_CONFIG_EHCI_MAX_QH - 1].horizontalLinkPointer = (uint32_t)NULL; + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QTD; ++index) + { + ehciInstance->ehciQtdHead[index - 1].nextQtdPointer = (uint32_t)(&ehciInstance->ehciQtdHead[index]); + } + ehciInstance->ehciQtdNumber = USB_HOST_CONFIG_EHCI_MAX_QTD; + ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1].nextQtdPointer = (uint32_t)NULL; + ehciInstance->ehciQtdTail = &ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1]; + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_ITD; ++index) + { + ehciInstance->ehciItdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciItdList[index]); + } + ehciInstance->ehciItdNumber = USB_HOST_CONFIG_EHCI_MAX_ITD; + ehciInstance->ehciItdList[USB_HOST_CONFIG_EHCI_MAX_ITD - 1].nextLinkPointer = (uint32_t)NULL; +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_SITD; ++index) + { + ehciInstance->ehciSitdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciSitdList[index]); + } + ehciInstance->ehciSitdNumber = USB_HOST_CONFIG_EHCI_MAX_SITD; + ehciInstance->ehciSitdList[USB_HOST_CONFIG_EHCI_MAX_SITD - 1].nextLinkPointer = (uint32_t)NULL; +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + for (index = 1; index < USB_HOST_EHCI_ISO_NUMBER; ++index) + { + ehciInstance->ehciIsoList[index - 1].next = &ehciInstance->ehciIsoList[index]; + } + ehciInstance->ehciIsoList[USB_HOST_EHCI_ISO_NUMBER - 1].next = NULL; +#endif + + /* initialize pipes */ + ehciInstance->ehciPipeList = ehciInstance->ehciPipeIndexBase; + for (index = 1; index < USB_HOST_CONFIG_MAX_PIPES; ++index) + { + ehciInstance->ehciPipeList[index - 1].pipeCommon.next = (usb_host_pipe_t *)&ehciInstance->ehciPipeList[index]; + } + /* initialize mutext */ + osaStatus = USB_OsaMutexCreate(&ehciInstance->ehciMutex); + if (osaStatus != kStatus_USB_OSA_Success) + { +#ifdef HOST_ECHO + usb_echo("ehci mutex init fail\r\n"); +#endif + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + /* initialize task event */ + osaStatus = USB_OsaEventCreate(&ehciInstance->taskEventHandle, 1); + if (osaStatus != kStatus_USB_OSA_Success) + { +#ifdef HOST_ECHO + usb_echo("ehci event init fail\r\n"); +#endif + USB_OsaMutexDestroy(ehciInstance->ehciMutex); + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + + /* initialize first qh */ + ehciInstance->shedFirstQh = ehciInstance->ehciQhList; + ehciInstance->ehciQhList = + (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); + ehciInstance->shedFirstQh->staticEndpointStates[0] |= (1 << EHCI_HOST_QH_H_SHIFT); /* first qh */ + ehciInstance->shedFirstQh->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->horizontalLinkPointer = + (uint32_t)((uint32_t)(ehciInstance->shedFirstQh) | EHCI_HOST_POINTER_TYPE_QH); + + /* initialize periodic list */ + framePointer = (uint32_t *)ehciInstance->ehciFrameList; + for (index = 0; index < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; ++index) + { + framePointer[index] = EHCI_HOST_T_INVALID_VALUE; + } + + USB_HostEhciStartIP(ehciInstance); /* start ehci ip */ + + *controllerHandle = ehciInstance; + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + + /* disable all interrupts */ + ehciInstance->ehciIpBase->USBINTR = 0; + /* stop the controller */ + ehciInstance->ehciIpBase->USBCMD = 0; + /* free memory */ + USB_OsaMutexDestroy(ehciInstance->ehciMutex); + USB_OsaEventDestroy(ehciInstance->taskEventHandle); + USB_OsaMemoryFree(ehciInstance); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit) +{ + usb_host_ehci_pipe_t *ehciPipePointer = NULL; + usb_status_t status; + uint32_t speed; + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + + /* get one pipe */ + USB_HostEhciLock(); + if (ehciInstance->ehciPipeList != NULL) + { + ehciPipePointer = ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + USB_HostEhciUnlock(); + if (ehciPipePointer == NULL) + { +#ifdef HOST_ECHO + usb_echo("ehci open pipe failed\r\n"); +#endif + return kStatus_USB_Busy; + } + + /* initialize pipe informations */ + USB_HostEhciZeroMem((uint32_t *)ehciPipePointer, sizeof(usb_host_ehci_pipe_t) / 4); + ehciPipePointer->pipeCommon.deviceHandle = pipeInit->devInstance; + ehciPipePointer->pipeCommon.endpointAddress = pipeInit->endpointAddress; + ehciPipePointer->pipeCommon.direction = pipeInit->direction; + ehciPipePointer->pipeCommon.interval = pipeInit->interval; + ehciPipePointer->pipeCommon.maxPacketSize = pipeInit->maxPacketSize; + ehciPipePointer->pipeCommon.pipeType = pipeInit->pipeType; + ehciPipePointer->pipeCommon.numberPerUframe = pipeInit->numberPerUframe; + if (ehciPipePointer->pipeCommon.numberPerUframe == 0) + { + ehciPipePointer->pipeCommon.numberPerUframe = 1; + } + ehciPipePointer->pipeCommon.nakCount = pipeInit->nakCount; + ehciPipePointer->pipeCommon.nextdata01 = 0; + ehciPipePointer->ehciQh = NULL; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) + { + ehciPipePointer->pipeCommon.interval = + (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* iso interval is the power of 2 */ + } + else if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) + { + if (speed == USB_SPEED_HIGH) + { + ehciPipePointer->pipeCommon.interval = + (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* HS interrupt interval is the power of 2 */ + } + else + { + ehciPipePointer->pipeCommon.interval = USB_HostEhciGet2PowerValue( + ehciPipePointer->pipeCommon + .interval); /* FS/LS interrupt interval should be the power of 2, it is used for ehci bandwidth */ + } + } + else + { + } + + /* save the micro-frame interval, it is convenient for the interval process */ + if (speed == USB_SPEED_HIGH) + { + ehciPipePointer->uframeInterval = ehciPipePointer->pipeCommon.interval; + } + else + { + ehciPipePointer->uframeInterval = 8 * ehciPipePointer->pipeCommon.interval; + } + + /* open pipe */ + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_BULK: + status = USB_HostEhciOpenControlBulk(ehciInstance, ehciPipePointer); + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + status = USB_HostEhciOpenIso(ehciInstance, ehciPipePointer); + break; +#endif + + case USB_ENDPOINT_INTERRUPT: + status = USB_HostEhciOpenInterrupt(ehciInstance, ehciPipePointer); + break; + + default: + status = kStatus_USB_Error; + break; + } + + if (status != kStatus_USB_Success) + { + /* release pipe */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + return status; + } + + /* add pipe to run pipe list */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; + ehciInstance->ehciRunningPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + + *pipeHandle = ehciPipePointer; + return status; +} + +usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; + usb_host_pipe_t *prevPointer = NULL; + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + USB_HostEhciCloseControlBulk(ehciInstance, ehciPipePointer); + break; + + case USB_ENDPOINT_INTERRUPT: + USB_HostEhciCloseInterrupt(ehciInstance, ehciPipePointer); + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + USB_HostEhciCloseIso(ehciInstance, ehciPipePointer); + break; +#endif + + default: + break; + } + + /* delete pipe from run pipe list */ + USB_HostEhciLock(); + prevPointer = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; + if (prevPointer == (usb_host_pipe_t *)ehciPipePointer) + { + ehciInstance->ehciRunningPipeList = (usb_host_ehci_pipe_t *)(prevPointer->next); + } + else + { + while (prevPointer != NULL) + { + if (prevPointer->next == (usb_host_pipe_t *)ehciPipePointer) + { + prevPointer->next = ehciPipePointer->pipeCommon.next; + break; + } + else + { + prevPointer = prevPointer->next; + } + } + } + USB_HostEhciUnlock(); + + /* release pipe */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; + usb_status_t status = kStatus_USB_Success; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + uint32_t speed; +#endif + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_INTERRUPT: + status = USB_HostEhciQhQtdListInit(ehciInstance, ehciPipePointer, + transfer); /* initialize qtd for control/bulk transfer */ + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + status = USB_HostEhciItdArrayInit(ehciInstance, ehciPipePointer, + transfer); /* initialize itd for iso transfer */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + status = USB_HostEhciSitdArrayInit(ehciInstance, ehciPipePointer, + transfer); /* initialize sitd for iso transfer */ +#endif + } + break; +#endif + + default: + break; + } + return status; +} + +usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + return USB_HostEhciWritePipe(controllerHandle, pipeHandle, transfer); /* same as write */ +} + +usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint32_t ioctlEvent, void *ioctlParam) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_cancel_param_t *param; + usb_host_ehci_pipe_t *ehciPipePointer; + volatile usb_host_ehci_qh_t *vltQhPointer; + uint32_t deviceAddress; + + if (controllerHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + switch (ioctlEvent) + { + case kUSB_HostCancelTransfer: /* cancel pipe or one transfer */ + param = (usb_host_cancel_param_t *)ioctlParam; + status = USB_HostEhciCancelPipe(ehciInstance, (usb_host_ehci_pipe_t *)param->pipeHandle, param->transfer); + break; + + case kUSB_HostBusControl: /* bus control */ + status = USB_HostEhciControlBus(ehciInstance, *((uint8_t *)ioctlParam)); + break; + + case kUSB_HostGetFrameNumber: /* get frame number */ + *((uint32_t *)ioctlParam) = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + break; + + case kUSB_HostUpdateControlEndpointAddress: + ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* update address */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &deviceAddress); + vltQhPointer->staticEndpointStates[0] |= deviceAddress; + break; + + case kUSB_HostUpdateControlPacketSize: + ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + USB_HostEhciLock(); + if (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) + { + USB_HostEhciStopAsync(ehciInstance); + /* update max packet size */ + vltQhPointer->staticEndpointStates[0] = + (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); + USB_HostEhciStartAsync(ehciInstance); + } + else + { + /* update max packet size */ + vltQhPointer->staticEndpointStates[0] = + (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); + } + USB_HostEhciUnlock(); + break; + + default: + break; + } + return status; +} + +void USB_HostEhciTaskFunction(void *hostHandle) +{ + usb_host_ehci_instance_t *ehciInstance; + uint32_t bitSet; + usb_device_handle deviceHandle; + + if (hostHandle == NULL) + { + return; + } + ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; + + if (USB_OsaEventWait(ehciInstance->taskEventHandle, 0xFF, 0, 0, &bitSet) == + kStatus_USB_OSA_Success) /* wait all event */ + { + if (bitSet & EHCI_TASK_EVENT_PORT_CHANGE) /* port change */ + { + USB_HostEhciPortChange(ehciInstance); + } + + if (bitSet & EHCI_TASK_EVENT_TIMER0) /* timer0 */ + { + USB_HostEhciTimer0(ehciInstance); + } + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (bitSet & EHCI_TASK_EVENT_TIMER1) /* timer1 */ + { + USB_HostEhciTimer1(ehciInstance); + } +#endif + + if (ehciInstance->deviceAttached == kEHCIDeviceAttached) + { + if (bitSet & EHCI_TASK_EVENT_TRANSACTION_DONE) /* transaction done */ + { + USB_HostEhciTransactionDone(ehciInstance); + } + + if (bitSet & EHCI_TASK_EVENT_DEVICE_DETACH) /* device detach */ + { + ehciInstance->ehciIpBase->USBINTR &= + (~USBHS_USBINTR_PCE_MASK); /* disable attach, enable when the detach process is done */ + ehciInstance->deviceAttached = kEHCIDeviceDetached; + USB_HostDetachDevice(ehciInstance->hostHandle, 0, 0); + } + } + else if (ehciInstance->deviceAttached != kEHCIDeviceAttached) + { + if (bitSet & EHCI_TASK_EVENT_DEVICE_ATTACH) /* device is attached */ + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + + if (USB_HostAttachDevice(ehciInstance->hostHandle, ehciInstance->firstDeviceSpeed, 0, 0, 1, + &deviceHandle) == kStatus_USB_Success) + { + ehciInstance->deviceAttached = kEHCIDeviceAttached; + } + } + } + else + { + } + } +} + +void USB_HostEhciIsrFunction(void *hostHandle) +{ + usb_host_ehci_instance_t *ehciInstance; + static uint32_t interruptStatus = 0; + + if (hostHandle == NULL) + { + return; + } + + ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + if (ehciInstance->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventDetectResume); /* call host callback function */ + + while (!(ehciInstance->registerNcBase->USB_OTGn_PHY_CTRL_0 & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)) + { + } + + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) + { + /* ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ + ehciInstance->busSuspendStatus = kBus_EhciStartResume; + } + else + { + } + } + else + { + } +#else + if (ehciInstance->ehciIpBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventDetectResume); /* call host callback function */ + + while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + ehciInstance->ehciIpBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) + { + ehciInstance->busSuspendStatus = kBus_EhciStartResume; + /*ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ + } + else + { + } + } + else + { + } +#endif /* FSL_FEATURE_SOC_USBNC_COUNT */ + +#endif /* USB_HOST_CONFIG_LOW_POWER_MODE */ + + interruptStatus = ehciInstance->ehciIpBase->USBSTS; + interruptStatus &= ehciInstance->ehciIpBase->USBINTR; + while (interruptStatus) /* there are usb interrupts */ + { + ehciInstance->ehciIpBase->USBSTS = interruptStatus; /* clear interrupt */ + + if (interruptStatus & USBHS_USBSTS_SRI_MASK) /* SOF interrupt */ + { + } + + if (interruptStatus & USBHS_USBSTS_SEI_MASK) /* system error interrupt */ + { + } + + if ((interruptStatus & USBHS_USBSTS_UI_MASK) || + (interruptStatus & USBHS_USBSTS_UEI_MASK)) /* USB interrupt or USB error interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TRANSACTION_DONE); + } + + if (interruptStatus & USBHS_USBSTS_PCI_MASK) /* port change detect interrupt */ + { +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK) + { + if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) + { + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventNotSuspended); /* call host callback function */ + hostPointer->suspendedDevice = NULL; + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } + else + { + } + } +#endif + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_PORT_CHANGE); + } + + if (interruptStatus & USBHS_USBSTS_TI0_MASK) /* timer 0 interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER0); + } + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (interruptStatus & USBHS_USBSTS_TI1_MASK) /* timer 1 interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER1); + } +#endif + + interruptStatus = ehciInstance->ehciIpBase->USBSTS; + interruptStatus &= ehciInstance->ehciIpBase->USBINTR; + } +} + +#endif /* USB_HOST_CONFIG_EHCI */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_ehci.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_ehci.h new file mode 100644 index 0000000000..162d6576cd --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_ehci.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_CONTROLLER_EHCI_H_ +#define _USB_HOST_CONTROLLER_EHCI_H_ + +/******************************************************************************* + * KHCI private public structures, enumerations, macros, functions + ******************************************************************************/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* EHCI host macros */ +#define EHCI_HOST_T_INVALID_VALUE (1U) +#define EHCI_HOST_POINTER_TYPE_ITD (0x00U) +#define EHCI_HOST_POINTER_TYPE_QH (0x00000002U) +#define EHCI_HOST_POINTER_TYPE_SITD (0x00000004U) +#define EHCI_HOST_POINTER_TYPE_FSTN (0x00000006U) +#define EHCI_HOST_POINTER_TYPE_MASK (0x00000006U) +#define EHCI_HOST_POINTER_ADDRESS_MASK (0xFFFFFFE0U) +#define EHCI_HOST_PID_OUT (0U) +#define EHCI_HOST_PID_IN (1U) +#define EHCI_HOST_PID_SETUP (2U) + +#define EHCI_HOST_QH_RL_SHIFT (28U) +#define EHCI_HOST_QH_RL_MASK (0xF0000000U) +#define EHCI_HOST_QH_C_SHIFT (27U) +#define EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT (16U) +#define EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK (0x07FF0000U) +#define EHCI_HOST_QH_H_SHIFT (15U) +#define EHCI_HOST_QH_DTC_SHIFT (14U) +#define EHCI_HOST_QH_EPS_SHIFT (12U) +#define EHCI_HOST_QH_ENDPT_SHIFT (8U) +#define EHCI_HOST_QH_I_SHIFT (7U) +#define EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_QH_MULT_SHIFT (30U) +#define EHCI_HOST_QH_PORT_NUMBER_SHIFT (23U) +#define EHCI_HOST_QH_HUB_ADDR_SHIFT (16U) +#define EHCI_HOST_QH_UFRAME_CMASK_SHIFT (8U) +#define EHCI_HOST_QH_UFRAME_SMASK_SHIFT (0U) +#define EHCI_HOST_QH_STATUS_ERROR_MASK (0x0000007EU) +#define EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK (0x0000003EU) + +#define EHCI_HOST_QTD_DT_SHIFT (31U) +#define EHCI_HOST_QTD_DT_MASK (0x80000000U) +#define EHCI_HOST_QTD_TOTAL_BYTES_SHIFT (16U) +#define EHCI_HOST_QTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define EHCI_HOST_QTD_IOC_MASK (0x00008000U) +#define EHCI_HOST_QTD_C_PAGE_SHIFT (12U) +#define EHCI_HOST_QTD_CERR_SHIFT (10U) +#define EHCI_HOST_QTD_CERR_MAX_VALUE (0x00000003U) +#define EHCI_HOST_QTD_PID_CODE_SHIFT (8U) +#define EHCI_HOST_QTD_STATUS_SHIFT (0U) +#define EHCI_HOST_QTD_CURRENT_OFFSET_MASK (0x00000FFFU) +#define EHCI_HOST_QTD_BUFFER_POINTER_SHIFT (12U) +#define EHCI_HOST_QTD_STATUS_ACTIVE_MASK (0x00000080U) +#define EHCI_HOST_QTD_STATUS_MASK (0x000000ffU) +#define EHCI_HOST_QTD_STATUS_ERROR_MASK (0x0000007EU) +#define EHCI_HOST_QTD_STATUS_STALL_ERROR_MASK (0x00000040U) + +#define EHCI_HOST_ITD_STATUS_ACTIVE_MASK (0x80000000U) +#define EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT (16U) +#define EHCI_HOST_ITD_TRANSACTION_LEN_MASK (0x0FFF0000U) +#define EHCI_HOST_ITD_IOC_SHIFT (15U) +#define EHCI_HOST_ITD_PG_SHIFT (12U) +#define EHCI_HOST_ITD_TRANSACTION_OFFSET_SHIFT (0U) +#define EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK (0x00000FFFU) +#define EHCI_HOST_ITD_BUFFER_POINTER_SHIFT (12U) +#define EHCI_HOST_ITD_ENDPT_SHIFT (8U) +#define EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT (0U) +#define EHCI_HOST_ITD_MULT_SHIFT (0U) +#define EHCI_HOST_ITD_DIRECTION_SHIFT (11U) + +#define EHCI_HOST_SITD_STATUS_ACTIVE_MASK (0x00000080U) +#define EHCI_HOST_SITD_DIRECTION_SHIFT (31U) +#define EHCI_HOST_SITD_PORT_NUMBER_SHIFT (24U) +#define EHCI_HOST_SITD_HUB_ADDR_SHIFT (16U) +#define EHCI_HOST_SITD_ENDPT_SHIFT (8U) +#define EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_SITD_CMASK_SHIFT (8U) +#define EHCI_HOST_SITD_SMASK_SHIFT (0U) +#define EHCI_HOST_SITD_TOTAL_BYTES_SHIFT (16U) +#define EHCI_HOST_SITD_TOTAL_BYTES_MASK (0x03FF0000U) +#define EHCI_HOST_SITD_TP_SHIFT (3U) +#define EHCI_HOST_SITD_TCOUNT_SHIFT (0U) +#define EHCI_HOST_SITD_IOC_SHIFT (31U) + +/* register related MACROs */ +#define EHCI_PORTSC1_W1_BITS (0x0000002AU) +#define EHCI_MAX_UFRAME_VALUE (0x00003FFFU) + +/* task event */ +#define EHCI_TASK_EVENT_DEVICE_ATTACH (0x01U) +#define EHCI_TASK_EVENT_TRANSACTION_DONE (0x02U) +#define EHCI_TASK_EVENT_DEVICE_DETACH (0x04U) +#define EHCI_TASK_EVENT_PORT_CHANGE (0x08U) +#define EHCI_TASK_EVENT_TIMER0 (0x10U) +#define EHCI_TASK_EVENT_TIMER1 (0x20U) + +#define USB_HostEhciLock() USB_OsaMutexLock(ehciInstance->ehciMutex) +#define USB_HostEhciUnlock() USB_OsaMutexUnlock(ehciInstance->ehciMutex) + +/******************************************************************************* + * KHCI driver public structures, enumerations, macros, functions + ******************************************************************************/ + +/*! + * @addtogroup usb_host_controller_ehci + * @{ + */ + +/*! @brief The maximum supported ISO pipe number */ +#define USB_HOST_EHCI_ISO_NUMBER USB_HOST_CONFIG_EHCI_MAX_ITD +/*! @brief Check the port connect state delay if the state is unstable */ +#define USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY (101U) +/*! @brief Delay for port reset */ +#define USB_HOST_EHCI_PORT_RESET_DELAY (11U) +/*! @brief The SITD inserts a frame interval for putting more SITD continuously. + * There is an interval when an application sends two FS/LS ISO transfers. + * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two + * transfers + * are not continuous. + * For example: + * - Use case 1: when inserting the SITD first, the inserted frame = the current frame value + this MACRO value. + * - Use case 2: when inserting SITD is not first, choose between the last inserted frame value and the + * current frame value according to the following criteria: + * If the interval is less than the MACRO value, the new SITD is continuous with the last SITD. + * If not, the new SITD inserting frame = the current frame value + this MACRO value. + */ +#define USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER (2U) +/*! @brief The ITD inserts a micro-frame interval for putting more ITD continuously. + * There is an interval when an application sends two HS ISO transfers. + * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two + * transfers + * are not continuous. + * For example: + * - Use case 1: when inserting ITD first, the inserted micro-frame = the current micro-frame value + this MACRO value. + * - Use case 2: when inserting ITD is not first, choose between the last inserted micro-frame value and the + * current micro-frame value according to the following criteria: + * If the interval is less than this MACRO value, the new ITD is continuous with the last ITD. + * If not, the new ITD inserting micro-frame = the current micro-frame value + this MACRO value. + */ +#define USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER (16U) +/*! @brief Control or bulk transaction timeout value (unit: 100 ms) */ +#define USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE (20U) + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +typedef enum _bus_ehci_suspend_request_state +{ + kBus_EhciIdle = 0U, + kBus_EhciStartSuspend, + kBus_EhciSuspended, + kBus_EhciStartResume, +} bus_ehci_suspend_request_state_t; +#endif + +/*! @brief EHCI state for device attachment/detachment. */ +typedef enum _host_ehci_device_state_ +{ + kEHCIDevicePhyAttached = 1, /*!< Device is physically attached */ + kEHCIDeviceAttached, /*!< Device is attached and initialized */ + kEHCIDeviceDetached, /*!< Device is detached and de-initialized */ +} host_ehci_device_state_t; + +/*! @brief EHCI pipe structure */ +typedef struct _usb_host_ehci_pipe +{ + usb_host_pipe_t pipeCommon; /*!< Common pipe information */ + void *ehciQh; /*!< Control/bulk/interrupt: QH; ISO: usb_host_ehci_iso_t*/ + + /* bandwidth */ + uint16_t uframeInterval; /*!< Micro-frame interval value */ + uint16_t startFrame; /*!< + Bandwidth start frame: its value is from 0 to frame_list. + */ + uint16_t dataTime; /*!< + Bandwidth time value: + - When the host works as HS: it's the data bandwidth value. + - When the host works as FS/LS: + - For FS/LS device, it's the data bandwidth value when transferring the data by FS/LS. + - For HS device, it's the data bandwidth value when transferring the data by HS. + */ + uint16_t startSplitTime; /*!< + Start splitting the bandwidth time value: + - When the host works as HS, it is the start split bandwidth value. + */ + uint16_t completeSplitTime; /*!< + Complete splitting the bandwidth time value: + - When host works as HS, it is the complete split bandwidth value. + */ + uint8_t startUframe; /*!< + Bandwidth start micro-frame: its value is from 0 to 7. + */ + uint8_t uframeSmask; /*!< + Start micro-frame. + - When host works as an HS: + - For FS/LS device, it's the interrupt or ISO transfer start-split mask. + - For HS device, it's the interrupt transfer start micro-frame mask. + - When host works as FS/LS, it's the interrupt and ISO start micro-frame mask + */ + uint8_t uframeCmask; /*!< + Complete micro-frame + - When host works as HS: + - For FS/LS device, it's the interrupt or ISO transfer complete-split mask. + */ +} usb_host_ehci_pipe_t; + +/*! @brief EHCI QH structure. See the USB EHCI specification */ +typedef struct _usb_host_ehci_qh +{ + uint32_t horizontalLinkPointer; /*!< QH specification filed, queue head a horizontal link pointer */ + uint32_t + staticEndpointStates[2]; /*!< QH specification filed, static endpoint state and configuration information */ + uint32_t currentQtdPointer; /*!< QH specification filed, current qTD pointer */ + uint32_t nextQtdPointer; /*!< QH specification filed, next qTD pointer */ + uint32_t alternateNextQtdPointer; /*!< QH specification filed, alternate next qTD pointer */ + uint32_t + transferOverlayResults[6]; /*!< QH specification filed, transfer overlay configuration and transfer results */ + + /* reserved space */ + usb_host_ehci_pipe_t *ehciPipePointer; /*!< EHCI pipe pointer */ + usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this QH */ + usb_host_transfer_t *ehciTransferTail; /*!< Transfer list tail on this QH */ + uint16_t timeOutValue; /*!< Its maximum value is USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE. When the value is + zero, the transfer times out. */ + uint16_t timeOutLabel; /*!< It's used to judge the transfer timeout. The EHCI driver maintain the value */ +} usb_host_ehci_qh_t; + +/*! @brief EHCI QTD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_qtd +{ + uint32_t nextQtdPointer; /*!< QTD specification filed, the next QTD pointer */ + uint32_t alternateNextQtdPointer; /*!< QTD specification filed, alternate next QTD pointer */ + uint32_t transferResults[2]; /*!< QTD specification filed, transfer results fields */ + uint32_t bufferPointers[4]; /*!< QTD specification filed, transfer buffer fields */ +} usb_host_ehci_qtd_t; + +/*! @brief EHCI ITD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_itd +{ + uint32_t nextLinkPointer; /*!< ITD specification filed, the next linker pointer */ + uint32_t transactions[8]; /*!< ITD specification filed, transactions information */ + uint32_t bufferPointers[7]; /*!< ITD specification filed, transfer buffer fields */ + + /* add space */ + struct _usb_host_ehci_itd *nextItdPointer; /*!< Next ITD pointer */ + uint32_t frameEntryIndex; /*!< The ITD inserted frame value */ + uint32_t reserved[6]; /*!< Reserved fields for 32 bytes align */ +} usb_host_ehci_itd_t; + +/*! @brief EHCI SITD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_sitd +{ + uint32_t nextLinkPointer; /*!< SITD specification filed, the next linker pointer */ + uint32_t endpointStates[2]; /*!< SITD specification filed, endpoint configuration information */ + uint32_t transferResults[3]; /*!< SITD specification filed, transfer result fields */ + uint32_t backPointer; /*!< SITD specification filed, back pointer */ + + /* reserved space */ + uint16_t frameEntryIndex; /*!< The SITD inserted frame value */ + uint8_t nextSitdIndex; /*!< The next SITD index; Get the next SITD pointer through adding base address with the + index. 0xFF means invalid. */ + uint8_t reserved; /*!< Reserved fields for 32 bytes align */ +} usb_host_ehci_sitd_t; + +/*! @brief EHCI ISO structure; An ISO pipe has an instance of this structure to keep the ISO pipe-specific information. + */ +typedef struct _usb_host_ehci_iso +{ + struct _usb_host_ehci_iso *next; /*!< Next instance pointer */ + usb_host_pipe_t *ehciPipePointer; /*!< This ISO's EHCI pipe pointer */ + usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this ISO pipe */ + usb_host_transfer_t *ehciTransferTail; /*!< Transfer list head on this ISO pipe */ + + uint16_t lastLinkFrame; /*!< It means that the inserted frame for ISO ITD/SITD. 0xFFFF is invalid. For ITD, it is a + micro-frame value. For SITD, it is a frame value */ +} usb_host_ehci_iso_t; + +/*! @brief EHCI instance structure */ +typedef struct _usb_host_ehci_instance +{ + usb_host_handle hostHandle; /*!< Related host handle*/ + uint32_t *ehciUnitBase; /*!< Keep the QH/QTD/ITD/SITD buffer pointer for release*/ + uint8_t *ehciFrameList; /*!< The frame list of the current ehci instance*/ + usb_host_ehci_qh_t *ehciQhList; /*!< Idle QH list pointer */ + usb_host_ehci_qtd_t *ehciQtdHead; /*!< Idle QTD list pointer head */ + usb_host_ehci_qtd_t *ehciQtdTail; /*!< Idle QTD list pointer tail (recently used qTD will be used)*/ + usb_host_ehci_itd_t *ehciItdList; /*!< Idle ITD list pointer*/ + usb_host_ehci_sitd_t *ehciSitdIndexBase; /*!< SITD buffer's start pointer*/ + usb_host_ehci_sitd_t *ehciSitdList; /*!< Idle SITD list pointer*/ + usb_host_ehci_iso_t *ehciIsoList; /*!< Idle ISO list pointer*/ + USBHS_Type *ehciIpBase; /*!< EHCI IP base address*/ + usb_host_ehci_qh_t *shedFirstQh; /*!< First async QH*/ + usb_host_ehci_pipe_t *ehciPipeIndexBase; /*!< Pipe buffer's start pointer*/ + usb_host_ehci_pipe_t *ehciPipeList; /*!< Idle pipe list pointer*/ + usb_host_ehci_pipe_t *ehciRunningPipeList; /*!< Running pipe list pointer*/ + usb_osa_mutex_handle ehciMutex; /*!< EHCI mutex*/ + usb_osa_event_handle taskEventHandle; /*!< EHCI task event*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + uint64_t matchTick; + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif + +#endif + uint8_t controllerId; /*!< EHCI controller ID*/ + uint8_t deviceAttached; /*!< Device attach/detach state, see #host_ehci_device_state_t */ + uint8_t firstDeviceSpeed; /*!< The first device's speed, the controller's work speed*/ + uint8_t ehciItdNumber; /*!< Idle ITD number*/ + uint8_t ehciSitdNumber; /*!< Idle SITD number*/ + uint8_t ehciQtdNumber; /*!< Idle QTD number*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + bus_ehci_suspend_request_state_t busSuspendStatus; /*!< Bus Suspend Status*/ +#endif +} usb_host_ehci_instance_t; + +/*! @brief EHCI data structure */ +typedef struct _usb_host_ehci_data +{ +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QH)) && (USB_HOST_CONFIG_EHCI_MAX_QH > 0U)) + usb_host_ehci_qh_t ehciQh[USB_HOST_CONFIG_EHCI_MAX_QH]; /*!< Idle QH list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QTD)) && (USB_HOST_CONFIG_EHCI_MAX_QTD > 0U)) + usb_host_ehci_qtd_t ehciQtd[USB_HOST_CONFIG_EHCI_MAX_QTD]; /*!< Idle QTD list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_ITD)) && (USB_HOST_CONFIG_EHCI_MAX_ITD > 0U)) + usb_host_ehci_itd_t ehciItd[USB_HOST_CONFIG_EHCI_MAX_ITD]; /*!< Idle ITD list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_SITD)) && (USB_HOST_CONFIG_EHCI_MAX_SITD > 0U)) + usb_host_ehci_sitd_t ehciSitd[USB_HOST_CONFIG_EHCI_MAX_SITD]; /*!< Idle SITD list array*/ +#endif +#if ((defined(USB_HOST_EHCI_ISO_NUMBER)) && (USB_HOST_EHCI_ISO_NUMBER > 0U)) + usb_host_ehci_iso_t ehciIso[USB_HOST_EHCI_ISO_NUMBER]; /*!< Idle ISO list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_MAX_PIPES)) && (USB_HOST_CONFIG_MAX_PIPES > 0U)) + usb_host_ehci_pipe_t ehciPipe[USB_HOST_CONFIG_MAX_PIPES]; /*!< Idle pipe list array*/ +#endif +} usb_host_ehci_data_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +/*! + * @name USB host EHCI APIs + * @{ + */ + +/*! + * @brief Creates the USB host EHCI instance. + * + * This function initializes the USB host EHCI controller driver. + * + * @param[in] controllerId The controller ID of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param[in] upperLayerHandle The host level handle. + * @param[out] controllerHandle return the controller instance handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + * @retval kStatus_USB_AllocFail Allocating memory failed. + * @retval kStatus_USB_Error Host mutex create fail, KHCI/EHCI mutex or KHCI/EHCI event create fail. + * Or, KHCI/EHCI IP initialize fail. + */ +extern usb_status_t USB_HostEhciCreate(uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle); + +/*! + * @brief Destroys the USB host EHCI instance. + * + * This function de-initializes The USB host EHCI controller driver. + * + * @param[in] controllerHandle The controller handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + */ +extern usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle); + +/*! + * @brief Opens the USB host pipe. + * + * This function opens a pipe according to the pipe_init_ptr parameter. + * + * @param[in] controllerHandle The controller handle. + * @param[out] pipeHandle The pipe handle pointer, it is used to return the pipe handle. + * @param[in] pipeInit It is used to initialize the pipe. + * + * @retval kStatus_USB_Success The host is initialized successfully. + * @retval kStatus_USB_Error There is no idle pipe. + * Or, there is no idle QH for EHCI. + * Or, bandwidth allocate fail for EHCI. + */ +extern usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit); + +/*! + * @brief Closes the USB host pipe. + * + * This function closes a pipe and releases related resources. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The closing pipe handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + */ +extern usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle); + +/*! + * @brief Sends data to the pipe. + * + * This function requests to send the transfer to the specified pipe. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The sending pipe handle. + * @param[in] transfer The transfer information. + * + * @retval kStatus_USB_Success Sent successfully. + * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. + * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. + */ +extern usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); + +/*! + * @brief Receives data from the pipe. + * + * This function requests to receive the transfer from the specified pipe. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The receiving pipe handle. + * @param[in] transfer The transfer information. + + * @retval kStatus_USB_Success Send successfully. + * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. + * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. + */ +extern usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); + +/*! + * @brief Controls the EHCI. + * + * This function controls the EHCI. + * + * @param[in] controllerHandle The controller handle. + * @param[in] ioctlEvent See enumeration host_bus_control_t. + * @param[in] ioctlParam The control parameter. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_InvalidHandle The controllerHandle is a NULL pointer. + */ +extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, + uint32_t ioctlEvent, + void *ioctlParam); + +/*! @}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _USB_HOST_CONTROLLER_EHCI_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_hci.c b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_hci.c new file mode 100644 index 0000000000..927bf8bd9c --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_hci.c @@ -0,0 +1,1052 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_common.h" +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" +#include "fsl_device_registers.h" +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#include "fsl_cache.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + +extern uint32_t USB_HostHubGetTotalThinkTime(usb_host_handle hostHandle, uint8_t parentHubNo); + +extern usb_status_t USB_HostHubSuspendDevice(usb_host_handle hostHandle); + +extern usb_status_t USB_HostHubResumeDevice(usb_host_handle hostHandle); +#endif + +/*! + * @brief get the idle host instance. + * + * @return host instance pointer. + */ +static usb_host_instance_t *USB_HostGetInstance(void); + +/*! + * @brief release host instance. + * + * @param hostInstance host instance pointer. + */ +static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance); + +/*! + * @brief get the khci/ehci interface. + * + * @param controllerId controller id. + * @param controllerTable return controller interface structure. + */ +static void USB_HostGetControllerInterface(uint8_t controllerId, + const usb_host_controller_interface_t **controllerTable); + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) +extern void USB_HostEhciTestModeInit(usb_device_handle devHandle); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) +extern void USB_HostIp3516HsTestModeInit(usb_device_handle devHandle); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ +#endif /* USB_HOST_CONFIG_EHCI */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USB host instance resource */ +usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; + +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) +#include "usb_host_ehci.h" +static const usb_host_controller_interface_t s_EhciInterface = \ +{ + USB_HostEhciCreate, USB_HostEhciDestory, USB_HostEhciOpenPipe, USB_HostEhciClosePipe, + USB_HostEhciWritePipe, USB_HostEhciReadpipe, USB_HostEhciIoctl, +}; +#endif /* USB_HOST_CONFIG_EHCI */ + +#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) +#include "usb_host_khci.h" +static const usb_host_controller_interface_t s_KhciInterface = \ +{ + USB_HostKhciCreate, USB_HostKhciDestory, USB_HostKhciOpenPipe, USB_HostKhciClosePipe, + USB_HostKhciWritePipe, USB_HostKhciReadpipe, USB_HostKciIoctl, +}; +#endif /* USB_HOST_CONFIG_KHCI */ + +#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) +#include "usb_host_ohci.h" +static const usb_host_controller_interface_t s_OhciInterface = \ +{ + USB_HostOhciCreate, USB_HostOhciDestory, USB_HostOhciOpenPipe, USB_HostOhciClosePipe, + USB_HostOhciWritePipe, USB_HostOhciReadPipe, USB_HostOhciIoctl, +}; +#endif /* USB_HOST_CONFIG_OHCI */ + +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) +#include "usb_host_ip3516hs.h" +static const usb_host_controller_interface_t s_Ip3516HsInterface = \ +{ + USB_HostIp3516HsCreate, USB_HostIp3516HsDestory, USB_HostIp3516HsOpenPipe, USB_HostIp3516HsClosePipe, + USB_HostIp3516HsWritePipe, USB_HostIp3516HsReadPipe, USB_HostIp3516HsIoctl, +}; +#endif /* USB_HOST_CONFIG_IP3516HS */ + +USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE) static uint8_t s_Setupbuffer[USB_HOST_CONFIG_MAX_HOST][USB_HOST_CONFIG_MAX_TRANSFERS][USB_DATA_ALIGN_SIZE_MULTIPLE(8)]; +/******************************************************************************* +* Code +******************************************************************************/ + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : usb_test_mode_init +* Returned Value : None +* Comments : +* This function is called by common class to initialize the class driver. It +* is called in response to a select interface call by application +* +*END*--------------------------------------------------------------------*/ +usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle) +{ +#if (((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) || \ + ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))) + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; +#endif + uint32_t productId; + uint32_t vendorId; + + usb_echo("usb host test init\r\n"); + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceVID, &vendorId); + usb_echo(" vendor id :0x%x product id:0x%x \r\n", vendorId, productId); + + if ((productId != 0x0200U) && (productId != 0x0101) && (productId != 0x0102) && (productId != 0x0103) && + (productId != 0x0104) && (productId != 0x0105) && (productId != 0x0106) && (productId != 0x0107) && + (productId != 0x0108)) + { + usb_echo("Unsupported Device\r\n"); + } + + if (productId == 0x0200U) + { + usb_echo("PET test device attached\r\n"); + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) + if (hostInstance->controllerTable == &s_EhciInterface) + { + USB_HostEhciTestModeInit(deviceHandle); + } +#elif((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) + if (hostInstance->controllerTable == &s_Ip3516HsInterface) + { + USB_HostIp3516HsTestModeInit(deviceHandle); + } +#endif + } + + return kStatus_USB_Success; +} +#endif + +static usb_host_instance_t *USB_HostGetInstance(void) +{ + uint8_t i = 0; + uint32_t index = 0; + USB_OSA_SR_ALLOC(); + USB_OSA_ENTER_CRITICAL(); + for (; i < USB_HOST_CONFIG_MAX_HOST; i++) + { + if (g_UsbHostInstance[i].occupied != 1) + { + uint8_t *buffer = (uint8_t *)&g_UsbHostInstance[i]; + for (uint32_t j = 0U; j < sizeof(usb_host_instance_t); j++) + { + buffer[j] = 0x00U; + } + g_UsbHostInstance[i].occupied = 1; + USB_OSA_EXIT_CRITICAL(); + for (index = 0; index < USB_HOST_CONFIG_MAX_TRANSFERS; ++index) + { + g_UsbHostInstance[i].transferList[index].setupPacket = + (usb_setup_struct_t *)&(s_Setupbuffer[i][index][0]); + } + return &g_UsbHostInstance[i]; + } + } + USB_OSA_EXIT_CRITICAL(); + return NULL; +} + +static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance) +{ + USB_OSA_SR_ALLOC(); + USB_OSA_ENTER_CRITICAL(); + hostInstance->occupied = 0; + USB_OSA_EXIT_CRITICAL(); +} + +static void USB_HostGetControllerInterface(uint8_t controllerId, + const usb_host_controller_interface_t **controllerTable) +{ +#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) + if (controllerId == kUSB_ControllerKhci0) + { + *controllerTable = &s_KhciInterface; + } +#endif /* USB_HOST_CONFIG_KHCI */ + +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) + if ((controllerId == kUSB_ControllerEhci0) || (controllerId == kUSB_ControllerEhci1)) + { + *controllerTable = &s_EhciInterface; + } +#endif /* USB_HOST_CONFIG_EHCI */ + +#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) + if (controllerId == kUSB_ControllerOhci0) + { + *controllerTable = &s_OhciInterface; + } +#endif /* USB_HOST_CONFIG_OHCI */ + +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) + if (controllerId == kUSB_ControllerIp3516Hs0) + { + *controllerTable = &s_Ip3516HsInterface; + } +#endif /* USB_HOST_CONFIG_IP3516HS */ +} + +usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, host_callback_t callbackFn) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = NULL; + usb_host_transfer_t *transferPrev = NULL; + uint8_t i = 0; + + hostInstance = USB_HostGetInstance(); /* get one host instance */ + if (hostInstance == NULL) + { + return kStatus_USB_InvalidHandle; + } + + /* get khci/ehci API table */ + USB_HostGetControllerInterface(controllerId, &hostInstance->controllerTable); + if (hostInstance->controllerTable == NULL) + { + USB_HostReleaseInstance(hostInstance); + return kStatus_USB_ControllerNotFound; + } + + /* judge the controller interface one time at here */ + if ((hostInstance->controllerTable->controllerCreate == NULL) || + (hostInstance->controllerTable->controllerDestory == NULL) || + (hostInstance->controllerTable->controllerOpenPipe == NULL) || + (hostInstance->controllerTable->controllerClosePipe == NULL) || + (hostInstance->controllerTable->controllerWritePipe == NULL) || + (hostInstance->controllerTable->controllerReadPipe == NULL) || + (hostInstance->controllerTable->controllerIoctl == NULL)) + { + return kStatus_USB_Error; + } + + /* HOST instance init*/ + hostInstance->controllerId = controllerId; + hostInstance->deviceCallback = callbackFn; + hostInstance->deviceList = NULL; + if (kStatus_USB_OSA_Success != USB_OsaMutexCreate(&hostInstance->hostMutex)) + { + USB_HostReleaseInstance(hostInstance); +#ifdef HOST_ECHO + usb_echo("host init: create host mutex fail\r\n"); +#endif + return kStatus_USB_Error; + } + + /* initialize transfer list */ + + hostInstance->transferHead = &hostInstance->transferList[0]; + transferPrev = hostInstance->transferHead; + for (i = 1; i < USB_HOST_CONFIG_MAX_TRANSFERS; ++i) + { + transferPrev->next = &hostInstance->transferList[i]; + transferPrev = transferPrev->next; + } + + /* controller create */ + status = + hostInstance->controllerTable->controllerCreate(controllerId, hostInstance, &(hostInstance->controllerHandle)); + if ((status != kStatus_USB_Success) || (hostInstance->controllerHandle == NULL)) + { + USB_OsaMutexDestroy(hostInstance->hostMutex); + USB_HostReleaseInstance(hostInstance); +#ifdef HOST_ECHO + usb_echo("host init: controller init fail\r\n"); +#endif + return kStatus_USB_Error; + } + + *hostHandle = hostInstance; + return kStatus_USB_Success; +} + +usb_status_t USB_HostDeinit(usb_host_handle hostHandle) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *deviceInstance = NULL; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + /* device list detach */ + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (deviceInstance != NULL) + { + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + USB_HostDetachDeviceInternal(hostHandle, deviceInstance); + } + + /* controller instance destory */ + status = hostInstance->controllerTable->controllerDestory(hostInstance->controllerHandle); + hostInstance->controllerHandle = NULL; + if (status != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("host controller destory fail\r\n"); +#endif + } + + /* resource release */ + if (hostInstance->hostMutex) + { + USB_OsaMutexDestroy(hostInstance->hostMutex); + hostInstance->hostMutex = NULL; + } + USB_HostReleaseInstance(hostInstance); + + return status; +} + +usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeInit == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* call controller open pipe interface */ + status = hostInstance->controllerTable->controllerOpenPipe(hostInstance->controllerHandle, pipeHandle, pipeInit); + + return status; +} + +usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* call controller close pipe interface */ + status = hostInstance->controllerTable->controllerClosePipe(hostInstance->controllerHandle, pipeHandle); + + return status; +} + +usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->direction = USB_OUT; + + USB_HostLock(); /* This api can be called by host task and app task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif +/* call controller write pipe interface */ +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + if (transfer->transferLength > 0) + { + DCACHE_CleanByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostSendSetup(usb_host_handle hostHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->next = NULL; + transfer->setupStatus = 0; + if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN) + { + transfer->direction = USB_IN; + } + else + { + transfer->direction = USB_OUT; + } + + USB_HostLock(); /* This API can be called by host task and application task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif +/* call controller write pipe interface */ +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + DCACHE_CleanByRange((uint32_t)&transfer->setupPacket->bmRequestType, sizeof(usb_setup_struct_t)); + if (transfer->transferLength > 0) + { + DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->direction = USB_IN; + + USB_HostLock(); /* This API can be called by host task and application task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif + +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + if (transfer->transferLength > 0) + { + DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerReadPipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_cancel_param_t cancelParam; + + if ((hostHandle == NULL) || (pipeHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize cancel parameter */ + cancelParam.pipeHandle = pipeHandle; + cancelParam.transfer = transfer; + + /* USB_HostLock(); This api can be called by host task and app task */ + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostCancelTransfer, + &cancelParam); + /* USB_HostUnlock(); */ + + return status; +} + +usb_status_t USB_HostMallocTransfer(usb_host_handle hostHandle, usb_host_transfer_t **transfer) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* get one from the transfer_head */ + USB_HostLock(); + if (hostInstance->transferHead != NULL) + { + *transfer = hostInstance->transferHead; + hostInstance->transferHead = hostInstance->transferHead->next; + USB_HostUnlock(); + return kStatus_USB_Success; + } + else + { + *transfer = NULL; + USB_HostUnlock(); + return kStatus_USB_Error; + } +} + +usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_transfer_t *transfer) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + if (transfer == NULL) + { + return kStatus_USB_Success; + } + + /* release one to the transfer_head */ + USB_HostLock(); + transfer->next = hostInstance->transferHead; + hostInstance->transferHead = transfer; + USB_HostUnlock(); + return kStatus_USB_Success; +} + +usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHandle, + uint32_t infoCode, + uint32_t *infoValue) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if ((deviceHandle == NULL) || (infoValue == NULL)) + { + return kStatus_USB_InvalidParameter; + } + + switch (infoCode) + { + case kUSB_HostGetDeviceAddress: /* device address */ + *infoValue = (uint32_t)deviceInstance->setAddress; + break; + + case kUSB_HostGetDeviceControlPipe: /* device control pipe */ + *infoValue = (uint32_t)deviceInstance->controlPipe; + break; + + case kUSB_HostGetHostHandle: /* device host handle */ + *infoValue = (uint32_t)deviceInstance->hostHandle; + break; + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + case kUSB_HostGetDeviceHubNumber: /* device hub address */ + *infoValue = (uint32_t)deviceInstance->hubNumber; + break; + + case kUSB_HostGetDevicePortNumber: /* device port no */ + *infoValue = (uint32_t)deviceInstance->portNumber; + break; + + case kUSB_HostGetDeviceLevel: /* device level */ + *infoValue = (uint32_t)deviceInstance->level; + break; + + case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ + *infoValue = (uint32_t)deviceInstance->hsHubNumber; + break; + + case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ + *infoValue = (uint32_t)deviceInstance->hsHubPort; + break; + + case kUSB_HostGetHubThinkTime: /* device hub think time */ + *infoValue = USB_HostHubGetTotalThinkTime(deviceInstance->hostHandle, deviceInstance->hubNumber); + break; +#else + case kUSB_HostGetDeviceHubNumber: /* device hub address */ + case kUSB_HostGetDevicePortNumber: /* device port no */ + case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ + case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ + case kUSB_HostGetHubThinkTime: /* device hub think time */ + *infoValue = 0; + break; + case kUSB_HostGetDeviceLevel: /* device level */ + *infoValue = 1; + break; +#endif /* USB_HOST_CONFIG_HUB */ + + case kUSB_HostGetDeviceSpeed: /* device speed */ + *infoValue = (uint32_t)deviceInstance->speed; + break; + + case kUSB_HostGetDevicePID: /* device pid */ + *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idProduct); + break; + + case kUSB_HostGetDeviceVID: /* device vid */ + *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idVendor); + break; + + case kUSB_HostGetDeviceConfigIndex: /* device config index */ + *infoValue = (uint32_t)deviceInstance->configurationValue - 1U; + break; + + case kUSB_HostGetConfigurationDes: /* configuration descriptor pointer */ + *infoValue = (uint32_t)deviceInstance->configurationDesc; + break; + + case kUSB_HostGetConfigurationLength: /* configuration descriptor length */ + *infoValue = (uint32_t)deviceInstance->configurationLen; + break; + + default: + return kStatus_USB_Error; + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle interfaceHandle, + uint8_t alternateSetting, + usb_host_interface_t *interface) +{ + uint32_t endPosition; + usb_descriptor_union_t *unionDes; + usb_host_ep_t *epParse; + + if (interfaceHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + if (alternateSetting == 0) + { + return kStatus_USB_InvalidParameter; + } + + /* parse configuration descriptor */ + unionDes = (usb_descriptor_union_t *)((usb_host_interface_t *)interfaceHandle) + ->interfaceDesc; /* interface extend descriptor start */ + endPosition = + (uint32_t)unionDes + + ((usb_host_interface_t *)interfaceHandle)->interfaceExtensionLength; /* interface extend descriptor end */ + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + + /* search for the alternate setting interface descritpor */ + while ((uint32_t)unionDes < endPosition) + { + if (unionDes->interface.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (unionDes->interface.bAlternateSetting == alternateSetting) + { + break; + } + else + { + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + } + else + { + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + } + if ((uint32_t)unionDes >= endPosition) + { + return kStatus_USB_Error; + } + + /* initialize interface handle structure instance */ + interface->interfaceDesc = &unionDes->interface; + interface->alternateSettingNumber = 0; + interface->epCount = 0; + interface->interfaceExtension = NULL; + interface->interfaceExtensionLength = 0; + interface->interfaceIndex = unionDes->interface.bInterfaceNumber; + + /* search for endpoint descriptor start position */ + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPosition) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { + if (interface->interfaceExtension == NULL) + { + interface->interfaceExtension = (uint8_t *)unionDes; + } + interface->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* parse endpoint descriptor */ + if (interface->interfaceDesc->bNumEndpoints != 0) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || + (interface->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) + { +#ifdef HOST_ECHO + usb_echo("interface descriptor error\n"); +#endif + return kStatus_USB_Error; + } + for (; interface->epCount < interface->interfaceDesc->bNumEndpoints; (interface->epCount)++) + { + if (((uint32_t)unionDes >= endPosition) || + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { +#ifdef HOST_ECHO + usb_echo("endpoint descriptor error\n"); +#endif + return kStatus_USB_Error; + } + epParse = (usb_host_ep_t *)&interface->epList[interface->epCount]; + epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; + epParse->epExtensionLength = 0; + epParse->epExtension = NULL; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPosition) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) + { + if (epParse->epExtension == NULL) + { + epParse->epExtension = (uint8_t *)unionDes; + } + epParse->epExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + + return kStatus_USB_Success; +} + +void USB_HostGetVersion(uint32_t *version) +{ + if (version) + { + *version = + (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); + } +} + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance; + usb_host_device_instance_t *deviceInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusSuspend; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (NULL == deviceHandle) + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + status = USB_HostHubSuspendDevice(hostInstance); +#else + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if (0 == deviceInstance->hubNumber) + { +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, + kUSB_HostBusControl, &type); + } +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + } + else + { + if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) + { + status = USB_HostHubSuspendDevice(hostInstance); + } + } +#endif + } + if (kStatus_USB_Error == status) + { + hostInstance->suspendedDevice = NULL; + } + return status; +} + +/* Send BUS or specific device resume request */ +usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance; + usb_host_device_instance_t *deviceInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusResume; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostInstance->suspendedDevice != deviceHandle) + { + return kStatus_USB_InvalidParameter; + } + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (NULL == deviceHandle) + { + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if (0 == deviceInstance->hubNumber) + { +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, + kUSB_HostBusControl, &type); + } +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + } + else + { + if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) + { + status = USB_HostHubResumeDevice(hostInstance); + } + } +#endif + } + + return status; +} +#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusL1Sleep; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (1U == sleepType) + { + /*#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))*/ + /*To do, implete hub L1 suspend device*/ + /*#else*/ + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + /*#endif*/ + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &type); + } + } + if (kStatus_USB_Error == status) + { + hostInstance->suspendedDevice = NULL; + } + return status; +} +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Error; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostL1Config, lpmParam); + + return status; +} + +/* Send BUS or specific device resume request */ +usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType) +{ + usb_host_instance_t *hostInstance; + + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusL1Resume; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + if (1U == sleepType) + { + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ + +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &type); + } + } + + return status; +} +#endif +/* Update HW tick(unit is ms) */ +usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Success; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->hwTick = tick; + + return status; +} +#endif diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_hci.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_hci.h new file mode 100644 index 0000000000..26b6d4a9c5 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/host/usb_host_hci.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_HCI_H_ +#define _USB_HOST_HCI_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief USB host lock */ +#define USB_HostLock() USB_OsaMutexLock(hostInstance->hostMutex) +/*! @brief USB host unlock */ +#define USB_HostUnlock() USB_OsaMutexUnlock(hostInstance->hostMutex) + +/*! + * @addtogroup usb_host_controller_driver + * @{ + */ + +/*! @brief USB host controller control code */ +typedef enum _usb_host_controller_control +{ + kUSB_HostCancelTransfer = 1U, /*!< Cancel transfer code */ + kUSB_HostBusControl, /*!< Bus control code */ + kUSB_HostGetFrameNumber, /*!< Get frame number code */ + kUSB_HostUpdateControlEndpointAddress, /*!< Update control endpoint address */ + kUSB_HostUpdateControlPacketSize, /*!< Update control endpoint maximum packet size */ + kUSB_HostPortAttachDisable, /*!< Disable the port attach event */ + kUSB_HostPortAttachEnable, /*!< Enable the port attach event */ + kUSB_HostL1Config, /*!< L1 suspend Bus control code */ +} usb_host_controller_control_t; + +/*! @brief USB host controller bus control code */ +typedef enum _usb_host_bus_control +{ + kUSB_HostBusReset = 1U, /*!< Reset bus */ + kUSB_HostBusRestart, /*!< Restart bus */ + kUSB_HostBusEnableAttach, /*!< Enable attach */ + kUSB_HostBusDisableAttach, /*!< Disable attach */ + kUSB_HostBusSuspend, /*!< Suspend BUS */ + kUSB_HostBusResume, /*!< Resume BUS */ + kUSB_HostBusL1SuspendInit, /*!< L1 Suspend BUS */ + kUSB_HostBusL1Sleep, /*!< L1 Suspend BUS */ + kUSB_HostBusL1Resume, /*!< L1 Resume BUS */ +} usb_host_bus_control_t; + +/*! @brief USB host controller interface structure */ +typedef struct _usb_host_controller_interface +{ + usb_status_t (*controllerCreate)( + uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle); /*!< Create a controller instance function prototype*/ + usb_status_t (*controllerDestory)( + usb_host_controller_handle controllerHandle); /*!< Destroy a controller instance function prototype*/ + usb_status_t (*controllerOpenPipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit); /*!< Open a controller pipe function prototype*/ + usb_status_t (*controllerClosePipe)( + usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle); /*!< Close a controller pipe function prototype*/ + usb_status_t (*controllerWritePipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); /*!< Write data to a pipe function prototype*/ + usb_status_t (*controllerReadPipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); /*!< Read data from a pipe function prototype*/ + usb_status_t (*controllerIoctl)(usb_host_controller_handle controllerHandle, + uint32_t ioctlEvent, + void *ioctlParam); /*!< Control a controller function prototype*/ +} usb_host_controller_interface_t; + +/*! @}*/ + +/*! + * @addtogroup usb_host_drv + * @{ + */ + +/*! @brief USB host instance structure */ +typedef struct _usb_host_instance +{ + void *controllerHandle; /*!< The low level controller handle*/ + host_callback_t deviceCallback; /*!< Device attach/detach callback*/ + usb_osa_mutex_handle hostMutex; /*!< Host layer mutex*/ + usb_host_transfer_t transferList[USB_HOST_CONFIG_MAX_TRANSFERS]; /*!< Transfer resource*/ + usb_host_transfer_t *transferHead; /*!< Idle transfer head*/ + const usb_host_controller_interface_t *controllerTable; /*!< KHCI/EHCI interface*/ + void *deviceList; /*!< Device list*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + void *suspendedDevice; /*!< Suspended device handle*/ + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ + uint8_t sleepType; /*!< L1 LPM device handle*/ +#endif + uint8_t addressBitMap[16]; /*!< Used for address allocation. The first bit is the address 1, second bit is the + address 2*/ + uint8_t occupied; /*!< 0 - the instance is not occupied; 1 - the instance is occupied*/ + uint8_t controllerId; /*!< The controller ID*/ +} usb_host_instance_t; + +/*! @}*/ + +#endif /* _USB_HOST_HCI_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb.h new file mode 100644 index 0000000000..256896b472 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_H__ +#define __USB_H__ + +#include +#include +#include +#include "usb_misc.h" +#include "usb_spec.h" + +/*! + * @addtogroup usb_drv + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines USB stack major version */ +#define USB_STACK_VERSION_MAJOR (1U) +/*! @brief Defines USB stack minor version */ +#define USB_STACK_VERSION_MINOR (6U) +/*! @brief Defines USB stack bugfix version */ +#define USB_STACK_VERSION_BUGFIX (3U) + +/*! @brief USB stack version definition */ +#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @brief USB error code */ +typedef enum _usb_status +{ + kStatus_USB_Success = 0x00U, /*!< Success */ + kStatus_USB_Error, /*!< Failed */ + + kStatus_USB_Busy, /*!< Busy */ + kStatus_USB_InvalidHandle, /*!< Invalid handle */ + kStatus_USB_InvalidParameter, /*!< Invalid parameter */ + kStatus_USB_InvalidRequest, /*!< Invalid request */ + kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ + kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ + + kStatus_USB_NotSupported, /*!< Configuration is not supported */ + kStatus_USB_Retry, /*!< Enumeration get configuration retry */ + kStatus_USB_TransferStall, /*!< Transfer stalled */ + kStatus_USB_TransferFailed, /*!< Transfer failed */ + kStatus_USB_AllocFail, /*!< Allocation failed */ + kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ + kStatus_USB_TransferCancel, /*!< The transfer cancelled */ + kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ + kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ + kStatus_USB_EHCIAttached, + kStatus_USB_EHCIDetached, +} usb_status_t; + +/*! @brief USB host handle type define */ +typedef void *usb_host_handle; + +/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the + * attached device instance handle*/ +typedef void *usb_device_handle; + +/*! @brief USB OTG handle type define */ +typedef void *usb_otg_handle; + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = + 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = + 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = + 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, this is reserved + to be used in the future. */ +} usb_controller_index_t; + +/** +* @brief USB stack version fields +*/ +typedef struct _usb_version +{ + uint8_t major; /*!< Major */ + uint8_t minor; /*!< Minor */ + uint8_t bugfix; /*!< Bug fix */ +} usb_version_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @} */ + +#endif /* __USB_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_device_config.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_device_config.h new file mode 100644 index 0000000000..551d92edc7 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_device_config.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CONFIG_H_ +#define _USB_DEVICE_CONFIG_H_ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @addtogroup usb_device_configuration + * @{ + */ + +/*! + * @name Hardware instance define + * @{ + */ + +/*! @brief KHCI instance count */ +#define USB_DEVICE_CONFIG_KHCI (0U) + +/*! @brief EHCI instance count */ +#define USB_DEVICE_CONFIG_EHCI (2U) + +/*! @brief LPC USB IP3511 FS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511FS (0U) + +/*! @brief LPC USB IP3511 HS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) + +/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ +#define USB_DEVICE_CONFIG_NUM \ + (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) + +/* @} */ + +/*! + * @name class instance define + * @{ + */ + +/*! @brief HID instance count */ +#define USB_DEVICE_CONFIG_HID (0U) + +/*! @brief CDC ACM instance count */ +#define USB_DEVICE_CONFIG_CDC_ACM (1U) + +/*! @brief MSC instance count */ +#define USB_DEVICE_CONFIG_MSC (0U) + +/*! @brief Audio instance count */ +#define USB_DEVICE_CONFIG_AUDIO (0U) + +/*! @brief PHDC instance count */ +#define USB_DEVICE_CONFIG_PHDC (0U) + +/*! @brief Video instance count */ +#define USB_DEVICE_CONFIG_VIDEO (0U) + +/*! @brief CCID instance count */ +#define USB_DEVICE_CONFIG_CCID (0U) + +/*! @brief Printer instance count */ +#define USB_DEVICE_CONFIG_PRINTER (0U) + +/*! @brief DFU instance count */ +#define USB_DEVICE_CONFIG_DFU (0U) + +/* @} */ + +/*! @brief Whether device is self power. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_SELF_POWER (1U) + +/*! @brief How many endpoints are supported in the stack. */ +#define USB_DEVICE_CONFIG_ENDPOINTS (4U) + +/*! @brief Whether the device task is enabled. */ +#define USB_DEVICE_CONFIG_USE_TASK (0U) + +/*! @brief How many the notification message are supported when the device task is enabled. */ +#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) + +/*! @brief Whether test mode enabled. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) + +/*! @brief Whether device CV test is enabled. */ +#define USB_DEVICE_CONFIG_CV_TEST (0U) + +/*! @brief Whether device compliance test is enabled. If the macro is enabled, + the test mode and CV test macroes will be set.*/ +#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) + +#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) + +/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ +#undef USB_DEVICE_CONFIG_USB20_TEST_MODE +/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ +#undef USB_DEVICE_CONFIG_CV_TEST + +/*! @brief enable the test mode. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) + +/*! @brief enable the CV test */ +#define USB_DEVICE_CONFIG_CV_TEST (1U) + +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + +/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ +#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! @brief How many the DTD are supported. */ +#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) + +/*! @brief Whether the EHCI ID pin detect feature enabled. */ +#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) +#endif + +/*! @brief Whether the keep alive feature enabled. */ +#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) + +/*! @brief Whether the transfer buffer is cache-enabled or not. */ +#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (1U) + +/*! @brief Whether the low power mode is enabled or not. */ +#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) + +/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_LPM_L1 (0U) +#else +/*! @brief The device remote wakeup is unsupported. */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) +#endif + +/*! @brief Whether the device detached feature is enabled or not. */ +#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) + +/*! @brief Whether handle the USB bus error. */ +#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) + +/* @} */ +/*! @brief rt-thread port alloc */ +#include +#define USB_OSA_SR_ALLOC(...) +/*! @brief rt-thread port enter critical */ +#define USB_OSA_ENTER_CRITICAL rt_enter_critical +/*! @brief rt-thread port exit critical */ +#define USB_OSA_EXIT_CRITICAL rt_exit_critical + +#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_ehci.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_ehci.h new file mode 100644 index 0000000000..edc3496643 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_ehci.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_EHCI_H__ +#define __USB_EHCI_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Device QH */ +#define USB_DEVICE_EHCI_QH_POINTER_MASK (0xFFFFFFC0U) +#define USB_DEVICE_EHCI_QH_MULT_MASK (0xC0000000U) +#define USB_DEVICE_EHCI_QH_ZLT_MASK (0x20000000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE_MASK (0x07FF0000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE (0x00000800U) +#define USB_DEVICE_EHCI_QH_IOS_MASK (0x00008000U) + +/* Device DTD */ +#define USB_DEVICE_ECHI_DTD_POINTER_MASK (0xFFFFFFE0U) +#define USB_DEVICE_ECHI_DTD_TERMINATE_MASK (0x00000001U) +#define USB_DEVICE_ECHI_DTD_PAGE_MASK (0xFFFFF000U) +#define USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK (0x00000FFFU) +#define USB_DEVICE_ECHI_DTD_PAGE_BLOCK (0x00001000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES (0x00004000U) +#define USB_DEVICE_ECHI_DTD_IOC_MASK (0x00008000U) +#define USB_DEVICE_ECHI_DTD_MULTIO_MASK (0x00000C00U) +#define USB_DEVICE_ECHI_DTD_STATUS_MASK (0x000000FFU) +#define USB_DEVICE_EHCI_DTD_STATUS_ERROR_MASK (0x00000068U) +#define USB_DEVICE_ECHI_DTD_STATUS_ACTIVE (0x00000080U) +#define USB_DEVICE_ECHI_DTD_STATUS_HALTED (0x00000040U) +#define USB_DEVICE_ECHI_DTD_STATUS_DATA_BUFFER_ERROR (0x00000020U) +#define USB_DEVICE_ECHI_DTD_STATUS_TRANSACTION_ERROR (0x00000008U) + +typedef struct _usb_device_ehci_qh_struct +{ + union + { + volatile uint32_t capabilttiesCharacteristics; + struct + { + volatile uint32_t reserved1 : 15; + volatile uint32_t ios : 1; + volatile uint32_t maxPacketSize : 11; + volatile uint32_t reserved2 : 2; + volatile uint32_t zlt : 1; + volatile uint32_t mult : 2; + } capabilttiesCharacteristicsBitmap; + } capabilttiesCharacteristicsUnion; + volatile uint32_t currentDtdPointer; + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + volatile uint32_t reserved1; + uint32_t setupBuffer[2]; + uint32_t setupBufferBack[2]; + union + { + uint32_t endpointStatus; + struct + { + uint32_t isOpened : 1; + uint32_t : 31; + } endpointStatusBitmap; + } endpointStatusUnion; + uint32_t reserved2; +} usb_device_ehci_qh_struct_t; + +typedef struct _usb_device_ehci_dtd_struct +{ + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + union + { + volatile uint32_t reserved; + struct + { + uint32_t originalBufferOffest : 12; + uint32_t originalBufferLength : 19; + uint32_t dtdInvalid : 1; + } originalBufferInfo; + } reservedUnion; +} usb_device_ehci_dtd_struct_t; + +#endif /* __USB_EHCI_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_misc.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_misc.h new file mode 100644 index 0000000000..4e65cfa94b --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_misc.h @@ -0,0 +1,452 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_MISC_H__ +#define __USB_MISC_H__ + +#ifndef ENDIANNESS + +#error ENDIANNESS should be defined, and then rebulid the project. + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define USB printf */ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern int DbgConsole_Printf(const char *fmt_s, ...); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1) +#define usb_echo printf +#else +#define usb_echo DbgConsole_Printf +#endif + +#if defined(__ICCARM__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED __packed +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED +#endif + +#elif defined(__GNUC__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED __attribute__((__packed__)) +#endif + +#elif defined(__CC_ARM) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED _Pragma("pack(1U)") +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED _Pragma("pack()") +#endif + +#endif + +#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU) +#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU) + +#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU) +#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU) +#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU) +#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU) + +#define USB_MEM4_ALIGN_MASK (0x03U) + +/* accessory macro */ +#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu)) +#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u)) +#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u)) + +/* big/little endian */ +#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U)) +#define SWAP4BYTE_CONST(n) \ + ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U)) + +#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \ + *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \ + } + +#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \ + *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + } + +#if (ENDIANNESS == USB_BIG_ENDIAN) + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) (n) +#define USB_LONG_TO_BIG_ENDIAN(n) (n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) (n) +#define USB_LONG_FROM_BIG_ENDIAN(n) (n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = ((n >> 24U) & 0xFFU); \ + m[2] = ((n >> 16U) & 0xFFU); \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ + (((uint8_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 24U) & 0xFFU); \ + m[1] = ((n >> 16U) & 0xFFU); \ + m[2] = ((n >> 8U) & 0xFFU); \ + m[3] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ + (((uint8_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 8U) & 0xFFU); \ + m[1] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ + ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((n)&0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) + +#else + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) (n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = ((n >> 24U) & 0xFFU); \ + m[2] = ((n >> 16U) & 0xFFU); \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ + (((uint8_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 24U) & 0xFFU); \ + m[1] = ((n >> 16U) & 0xFFU); \ + m[2] = ((n >> 8U) & 0xFFU); \ + m[3] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ + (((uint8_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 8U) & 0xFFU); \ + m[1] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ + ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((n)&0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) + +#endif + +/* + * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack. + * The USB device global variables are put into the section m_usb_global and m_usb_bdt or the section + * .bss.m_usb_global and .bss.m_usb_bdt by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device + * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM. + * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of + * the marco can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and + * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM + * is not less than 2K Bytes. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put + * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs, + * the USB dedicated RAM size is not more than 512 Bytes. + */ +#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1 +#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2 + +#if defined(__ICCARM__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#define USB_ALIGN_PRAGMA(x) _Pragma(#x) + _Pragma("diag_default=Pm120") + +#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n) + _Pragma("diag_suppress=Pm120") +#define USB_LINK_SECTION_PART(str) _Pragma(#str) +#define USB_LINK_SECTION_SUB(sec) USB_LINK_SECTION_PART(location = #sec) +#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"") +#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"") +#define USB_LINK_USB_GLOBAL_BSS _Pragma("location = \".bss.m_usb_global\"") +#define USB_LINK_USB_BDT_BSS _Pragma("location = \".bss.m_usb_bdt\"") + _Pragma("diag_default=Pm120") +#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"") +#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"") +#elif defined(__CC_ARM) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __weak +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init)) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init)) +#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global"))) __attribute__((zero_init)) +#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt"))) __attribute__((zero_init)) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init)) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init)) + +#elif defined(__GNUC__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @"))) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @"))) + +#else +#error The tool-chain is not supported. +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#elif(defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0) +#elif(defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#else +#define USB_CACHE_LINESIZE 4 +#endif + +#else +#define USB_CACHE_LINESIZE 4 +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#define USB_DATA_ALIGN 64 +#else +#define USB_DATA_ALIGN 4 +#endif + +#define USB_DATA_ALIGN_SIZE MAX(USB_CACHE_LINESIZE, USB_DATA_ALIGN) + +#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) ((n + USB_DATA_ALIGN_SIZE - 1) & (~(USB_DATA_ALIGN_SIZE - 1))) + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL) + +#define USB_GLOBAL USB_LINK_USB_GLOBAL +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL +#endif + +#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT) + +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#else + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_BDT USB_LINK_USB_BDT_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#endif + +#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_DMA_DATA_NONCACHEABLE +#endif + +#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL + +/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */ +/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */ + +#endif /* __USB_MISC_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_spec.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_spec.h new file mode 100644 index 0000000000..d77b7d3598 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/include/usb_spec.h @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_SPEC_H__ +#define __USB_SPEC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ +#define USB_SPEED_FULL (0x00U) +#define USB_SPEED_LOW (0x01U) +#define USB_SPEED_HIGH (0x02U) + +/* Set up packet structure */ +typedef struct _usb_setup_struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_setup_struct_t; + +/* USB standard descriptor endpoint type */ +#define USB_ENDPOINT_CONTROL (0x00U) +#define USB_ENDPOINT_ISOCHRONOUS (0x01U) +#define USB_ENDPOINT_BULK (0x02U) +#define USB_ENDPOINT_INTERRUPT (0x03U) + +/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ +#define USB_OUT (0U) +#define USB_IN (1U) + +/* USB standard descriptor length */ +#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) +#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) +#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) +#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) + +/* USB Device Capability Type Codes */ +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) + +/* USB standard descriptor type */ +#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) +#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) +#define USB_DESCRIPTOR_TYPE_STRING (0x03U) +#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) +#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) +#define USB_DESCRIPTOR_TYPE_OTG (0x09U) +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) +#define USB_DESCRIPTOR_TYPE_BOS (0x0F) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) + +#define USB_DESCRIPTOR_TYPE_HID (0x21U) +#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) +#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) + +/* USB standard request type */ +#define USB_REQUEST_TYPE_DIR_MASK (0x80U) +#define USB_REQUEST_TYPE_DIR_SHIFT (7U) +#define USB_REQUEST_TYPE_DIR_OUT (0x00U) +#define USB_REQUEST_TYPE_DIR_IN (0x80U) + +#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) +#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) +#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) +#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) +#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) + +#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) +#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) +#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) +#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) +#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) + +/* USB standard request */ +#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) +#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) +#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) +#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) +#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) +#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) +#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) +#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) +#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) +#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) +#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) + +/* USB standard request GET Status */ +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) + +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) + +#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) + +/* USB standard request CLEAR/SET feature */ +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) + +/* USB standard descriptor configure bmAttributes */ +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) + +/* USB standard descriptor endpoint bmAttributes */ +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) + +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) + +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) + +/* USB standard descriptor otg bmAttributes */ +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) + +/* USB standard descriptor device capability usb20 extension bmAttributes */ +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) + + +/* Language structure */ +typedef struct _usb_language +{ + uint8_t **string; /* The Strings descriptor array */ + uint32_t *length; /* The strings descriptor length array */ + uint16_t languageId; /* The language id of current language */ +} usb_language_t; + +typedef struct _usb_language_list +{ + uint8_t *languageString; /* The String 0U pointer */ + uint32_t stringLength; /* The String 0U Length */ + usb_language_t *languageList; /* The language list */ + uint8_t count; /* The language count */ +} usb_language_list_t; + +typedef struct _usb_descriptor_common +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bData[1]; /* Data */ +} usb_descriptor_common_t; + +typedef struct _usb_descriptor_device +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ + uint8_t bDeviceClass; /* Class code */ + uint8_t bDeviceSubClass; /* Sub-Class code */ + uint8_t bDeviceProtocol; /* Protocol code */ + uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ + uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ + uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ + uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_descriptor_device_t; + +typedef struct _usb_descriptor_configuration +{ + uint8_t bLength; /* Descriptor size in bytes = 9U */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ + uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ + uint8_t bConfigurationValue; /* Value to set this configuration. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Configuration characteristics */ + uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ +} usb_descriptor_configuration_t; + +typedef struct _usb_descriptor_interface +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_descriptor_interface_t; + +typedef struct _usb_descriptor_endpoint +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSize[2]; + uint8_t bInterval; +} usb_descriptor_endpoint_t; + +typedef struct _usb_descriptor_binary_device_object_store +{ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ +} usb_descriptor_bos_t; + +typedef struct _usb_descriptor_usb20_extension +{ + uint8_t bLength; /* Descriptor size in bytes = 7U */ + uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ +} usb_descriptor_usb20_extension_t; + +typedef union _usb_descriptor_union +{ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ +} usb_descriptor_union_t; + +#endif /* __USB_SPEC_H__ */ diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/phy/usb_phy.c b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/phy/usb_phy.c new file mode 100644 index 0000000000..85258c63af --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/phy/usb_phy.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_device_registers.h" + +#include + +void *USB_EhciPhyGetBase(uint8_t controllerId) +{ + void *usbPhyBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; + uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) + { + if (usbphy_base_temp[instance]) + { + usbphy_base[newinstance++] = usbphy_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbPhyBase = (void *)usbphy_base[controllerId]; +#endif + return usbPhyBase; +} + +/*! + * @brief ehci phy initialization. + * + * This function initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return kStatus_USB_Error; + } + +#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) + ANATOP->HW_ANADIG_REG_3P0.RW = + (ANATOP->HW_ANADIG_REG_3P0.RW & + (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | + ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; + ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = + ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; +#endif + +#if (defined USB_ANALOG) + USB_ANALOG->INSTANCE[controllerId - kUSB_ControllerEhci0].CHRG_DETECT_SET = USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); +#endif + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; + + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return kStatus_USB_Error; + } + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + +#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) + usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK; +#else + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD + * pfd clock = 480MHz*18/N, where N=18~35 + * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode + */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ + + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; + while (!(usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) + { + } +#endif + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief ehci phy de-initialization. + * + * This function de-initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + */ +void USB_EhciPhyDeinit(uint8_t controllerId) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ +#endif +} + +/*! + * @brief ehci phy disconnect detection enable or disable. + * + * This function enable/disable host ehci disconnect detection. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (enable) + { + usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + else + { + usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); + } +#endif +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/usb/phy/usb_phy.h b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/phy/usb_phy.h new file mode 100644 index 0000000000..0409f9c8b9 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/usb/phy/usb_phy.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __USB_PHY_H__ +#define __USB_PHY_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ + uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ + uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ +} usb_phy_config_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief EHCI PHY get USB phy bass address. + * + * This function is used to get USB phy bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB phy bass address. + */ +extern void *USB_EhciPhyGetBase(uint8_t controllerId); + +/*! + * @brief EHCI PHY initialization. + * + * This function initializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] freq The external input clock. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_Error The freq value is incorrect. + */ +extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief EHCI PHY deinitialization. + * + * This function deinitializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + */ +extern void USB_EhciPhyDeinit(uint8_t controllerId); + +/*! + * @brief EHCI PHY disconnect detection enable or disable. + * + * This function enable/disable the host EHCI disconnect detection. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); + +#if defined(__cplusplus) +} +#endif + +#endif /* __USB_PHY_H__ */ diff --git a/bsp/imxrt/imxrt1050-ArchMix/.config b/bsp/imxrt/imxrt1050-ArchMix/.config new file mode 100644 index 0000000000..3406bd3ee8 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/.config @@ -0,0 +1,420 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RTC_SYNC_USING_NTP is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_BEEPPLAYER is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_IMXRT1052=y +CONFIG_BOARD_RT1050_ArchMix=y +# CONFIG_BOARD_USING_HYPERFLASH is not set +CONFIG_BOARD_USING_QSPIFLASH=y + +# +# RT1050 Bsp Config +# + +# +# Select uart drivers +# +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART8 is not set + +# +# Select spi bus and dev drivers +# +CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set +CONFIG_LPSPI_CLK_SOURCE=0 +CONFIG_LPSPI_CLK_SOURCE_DIVIDER=8 +# CONFIG_RT_USING_SPIBUS3 is not set +CONFIG_RT_USING_SPIBUS4=y +CONFIG_LPSPI4_SCK_GPIO_2=y +CONFIG_LPSPI4_SDO_GPIO_2=y +CONFIG_LPSPI4_SDI_GPIO_2=y +# CONFIG_RT_USING_SPI_FLASH is not set + +# +# Select iic bus drivers +# +CONFIG_RT_USING_HW_I2C1=y +CONFIG_HW_I2C1_BADURATE_100kHZ=y +# CONFIG_HW_I2C1_BADURATE_400kHZ is not set +# CONFIG_RT_USING_HW_I2C3 is not set +# CONFIG_RT_USING_HW_I2C4 is not set + +# +# Select lcd driver +# + +# +# Notice: Arch Mix Board para: 480*272 4 4 8 2 40 10 127 45 +# +CONFIG_RT_USING_LCD=y +CONFIG_LCD_WIDTH=480 +CONFIG_LCD_HEIGHT=272 +CONFIG_LCD_HFP=4 +CONFIG_LCD_VFP=4 +CONFIG_LCD_HBP=8 +CONFIG_LCD_VBP=2 +CONFIG_LCD_HSW=40 +CONFIG_LCD_VSW=10 +CONFIG_LCD_BL_PIN=127 +CONFIG_LCD_RST_PIN=45 +CONFIG_RT_USING_SDRAM=y +CONFIG_RT_USING_RTC_HP=y diff --git a/bsp/imxrt/imxrt1050-ArchMix/Kconfig b/bsp/imxrt/imxrt1050-ArchMix/Kconfig new file mode 100644 index 0000000000..6aa07d476d --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/Kconfig @@ -0,0 +1,302 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMXRT1052 + bool + select ARCH_ARM_CORTEX_M7 + select ARCH_ARM_CORTEX_FPU + default y + +# RT1050 board config! +config BOARD_RT1050_ArchMix + bool + default y + +# RT1050 flash select! +config BOARD_USING_QSPIFLASH + bool + default y + +menu "RT1050 Bsp Config" + +menu "Select uart drivers" + config RT_USING_UART1 + bool "Using uart1" + select RT_USING_SERIAL + default y + config RT_USING_UART2 + bool "Using uart2" + select RT_USING_SERIAL + default n + config RT_USING_UART3 + bool "Using uart3" + select RT_USING_SERIAL + default n + config RT_USING_UART8 + bool "Using uart8" + select RT_USING_SERIAL + default n +endmenu + +menu "Select spi bus and dev drivers" + choice + prompt "SPI bus clock source" + default LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + + config LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + bool "PLL3PFD1" + config LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + bool "PLL3PFD0" + config LPSPI_CLK_SOURCE_FROM_PLL2 + bool "PLL2" + config LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + bool "PLL2PFD2" + endchoice + config LPSPI_CLK_SOURCE + int + default 0 if LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + default 1 if LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + default 2 if LPSPI_CLK_SOURCE_FROM_PLL2 + default 3 if LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + + config LPSPI_CLK_SOURCE_DIVIDER + int "SPI bus clock source divider" + range 1 8 + default 8 + + config RT_USING_SPIBUS3 + bool "Using spi3 bus" + select RT_USING_SPI + default n + choice + prompt "spi3 bus sck io choice" + default LPSPI3_SCK_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SCK_GPIO_1 + bool "GPIO_AD_B1_15" + endchoice + choice + prompt "spi3 bus sdo io choice" + default LPSPI3_SDO_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDO_GPIO_1 + bool "GPIO_AD_B1_14" + endchoice + choice + prompt "spi3 bus sdi io choice" + default LPSPI3_SDI_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDI_GPIO_1 + bool "GPIO_AD_B1_13" + endchoice + + config RT_USING_SPIBUS4 + bool "Using spi4 bus" + select RT_USING_SPI + default y + choice + prompt "spi4 bus sck io choice" + default LPSPI4_SCK_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SCK_GPIO_2 + bool "GPIO_B1_07" + endchoice + choice + prompt "spi4 bus sdo io choice" + default LPSPI4_SDO_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDO_GPIO_2 + bool "GPIO_B1_06" + endchoice + choice + prompt "spi4 bus sdi io choice" + default LPSPI4_SDI_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDI_GPIO_2 + bool "GPIO_B1_05" + endchoice + + config RT_USING_SPI_FLASH + bool "Using spi flash with sfud" + default n + select RT_USING_SPI + select RT_USING_SFUD + select RT_USING_PIN + choice + prompt "SPI flash using spibus" + default SPI_FLASH_USING_SPIBUS4 + depends on RT_USING_SPI_FLASH + + config SPI_FLASH_USING_SPIBUS1 + bool "spi1" + select RT_USING_SPIBUS1 + config SPI_FLASH_USING_SPIBUS2 + bool "spi2" + select RT_USING_SPIBUS2 + config SPI_FLASH_USING_SPIBUS3 + bool "spi3" + select RT_USING_SPIBUS3 + config SPI_FLASH_USING_SPIBUS4 + bool "spi4" + select RT_USING_SPIBUS4 + endchoice + config SPI_FLASH_USING_SPIBUS_NAME + string + default "spi1" if SPI_FLASH_USING_SPIBUS1 + default "spi2" if SPI_FLASH_USING_SPIBUS2 + default "spi3" if SPI_FLASH_USING_SPIBUS3 + default "spi4" if SPI_FLASH_USING_SPIBUS4 + + config SPI_FLASH_NAME + string "SPI flash device name" + default "flash0" + depends on RT_USING_SPI_FLASH + + config SPI_FLASH_USING_CS_PIN + int "SPI flash cs pin index" + default 79 + range 1 127 + depends on RT_USING_SPI_FLASH +endmenu + +menu "Select iic bus drivers" + + config RT_USING_HW_I2C1 + bool "using hardware i2c1" + select RT_USING_I2C + default y + choice + prompt "i2c1 bus badurate choice" + default HW_I2C1_BADURATE_100kHZ + depends on RT_USING_HW_I2C1 + config HW_I2C1_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C1_BADURATE_400kHZ + bool "400kHZ" + endchoice + + config RT_USING_HW_I2C3 + bool "using hardware i2c3" + select RT_USING_I2C + default n + choice + prompt "i2c3 bus badurate choice" + default HW_I2C3_BADURATE_100kHZ + depends on RT_USING_HW_I2C3 + config HW_I2C3_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C3_BADURATE_400kHZ + bool "400kHZ" + endchoice + + config RT_USING_HW_I2C4 + bool "using hardware i2c4" + select RT_USING_I2C + default n + choice + prompt "i2c4 bus badurate choice" + default HW_I2C4_BADURATE_100kHZ + depends on RT_USING_HW_I2C4 + config HW_I2C4_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C4_BADURATE_400kHZ + bool "400kHZ" + endchoice + +endmenu + +menu "Select lcd driver" + + if RT_USING_LCD + comment "Notice: Arch Mix Board para: 480*272 4 4 8 2 40 10 127 45" + endif + + config RT_USING_LCD + bool "Using lcd" + default n + + config LCD_WIDTH + int "Width pixel num" + default 480 + depends on RT_USING_LCD + config LCD_HEIGHT + int "Height pixel num" + default 272 + depends on RT_USING_LCD + config LCD_HFP + int "HFP" + default 4 + depends on RT_USING_LCD + config LCD_VFP + int "VFP" + default 4 + depends on RT_USING_LCD + config LCD_HBP + int "HBP" + default 8 + depends on RT_USING_LCD + config LCD_VBP + int "VBP" + default 2 + depends on RT_USING_LCD + config LCD_HSW + int "HSW" + default 40 + depends on RT_USING_LCD + config LCD_VSW + int "VSW" + default 10 + depends on RT_USING_LCD + config LCD_BL_PIN + int "Backlight pin index" + default 127 + depends on RT_USING_LCD + config LCD_RST_PIN + int "Reset pin index" + default 45 + depends on RT_USING_LCD +endmenu + +#menu "Select SDRAM driver" + config RT_USING_SDRAM + bool "Using sdram" + default y +#endmenu + +#menu "Select RTC driver" + config RT_USING_RTC_HP + bool "Using hp rtc" + select RT_USING_RTC + default n +#endmenu + +if RT_USING_USB_DEVICE + choice + prompt "select usb device controller" + default RT_USING_EHCI0_AS_DEVICE + + config RT_USING_EHCI0_AS_DEVICE + bool "set EHCI0 as device" + config RT_USING_EHCI1_AS_DEVICE + bool "set EHCI1 as device" + endchoice +endif + +endmenu diff --git a/bsp/imxrt/imxrt1050-ArchMix/README.md b/bsp/imxrt/imxrt1050-ArchMix/README.md new file mode 100644 index 0000000000..4d6de05fd2 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/README.md @@ -0,0 +1,79 @@ +# i.MX RT1050 Arch Mix + +## 1. 简介 + +![Arch_Mix](figures/Arch_Mix.jpg) + +Arch Mix 是 [Seeed Studio](https://www.seeedstudio.com/) 推出的一款基于 i.MX RT 1050 系列芯片的开发板，板载一颗 RGB 灯和一个用户按键，外扩 32M SDRAM，板载资源丰富，运行速度快（主频可达 600MHZ），并且支持外接 LCD 屏幕。Seeed Studio 是一家致力于促进开源硬件发展的服务型企业。目前，已经与众多设计者建立了紧密的合作关系，并且合作推出了涉及新媒体艺术、嵌入式平台、物联网、智能家居、便携式仪器等领域的一系列明星产品和方案。 + +### 板载资源： + +| 硬件 | 描述 | +| ---- | ---- | +| 芯片 | i.MX RT 1052 | +| 架构 | ARM Cortex-M7 | +| 最高频率 | 600MHz | +| 内部存储器 | 512KB SRAM | +| 外部存储器 | 32M SDRAM、8M QSPI FLASH（存储代码） | + +## 2. 编译说明 + +Arch Mix 板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | --------- | +| MDK5 | MDK525 | +| IAR | IAR 8.11.3.13984 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 3.BSP使用 + +### 3.1 配置工程 + +- 在 bsp 下打开 env 工具 +- 输入`menuconfig`命令配置工程，配置好之后保存退出。 +- 输入`scons --target=mdk5 -s`或`scons --target=iar`来生成需要的工程 + +### 3.2 下载和仿真 + +开发板支持 SWD 调试接口，连接外置仿真器后，就可以进行下载和仿真。 + +> 注意：下载算法默认使用 [iMXRT1052_W25Q256JV_By_Fire.FLM](http://www.firebbs.cn/thread-22513-1-4.html)，将此文件拷贝到 Keil5安装目录下 `ARM\Flash` 目录下即可。 +> +> 下载失败时：先按下 `Reset 按键`，再按下 `Boot Mode 按键`，先松开 `Reset 按键`，再松开 `Boot Mode 按键`，即可进入`下载模式`。 + +### 3.3 运行结果 + +下载程序之后，使用 TTL 转串口工具连接开发板上 RXD/TXD ，在终端工具里打开相应的串口(115200-N-8-1)。如果编译 & 烧写无误，当复位设备后，可以看到RT-Thread的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Oct 9 2018 + 2006 - 2018 Copyright by rt-thread team +using armcc, version: 5060750 +build time: Oct 9 2018 14:21:49 +msh />[I/[SDIO]] SD card capacity 123904 KB. +[I/[SDIO]] probe mmcsd block device! +found part[0], begin: 67584, size: 120.958MB +File System initialized! +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | ------ | +| UART | 支持 | UART 1~3/8 | +| GPIO | 支持 | | +| IIC | 支持 | IIC 1/3/4 | +| SPI | 支持 | SPI 3/4 | +| LCD | 支持 | | +| RTC | 支持 | | +| SDIO | 支持 | 暂时仅仅支持一个SDIO，还不支持中断方式 | +| SDRAM | 支持 | 32M SDRAM，后面 2M 作为 Non Cache 区域 | + +## 5. 联系人信息 + +维护人： + +- [guozhanxin](https://github.com/Guozhanxin) diff --git a/bsp/tm4c129x-dk/SConscript b/bsp/imxrt/imxrt1050-ArchMix/SConscript similarity index 100% rename from bsp/tm4c129x-dk/SConscript rename to bsp/imxrt/imxrt1050-ArchMix/SConscript diff --git a/bsp/imxrt/imxrt1050-ArchMix/SConstruct b/bsp/imxrt/imxrt1050-ArchMix/SConstruct new file mode 100644 index 0000000000..ea53aac131 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/SConstruct @@ -0,0 +1,72 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-imxrt.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +objs = objs + SConscript('../Libraries/imxrt1050/SConscript') + +# make a building +DoBuilding(TARGET, objs) + +def Update_MDKFlashProgrammingAlgorithm(flash_dict): + import xml.etree.ElementTree as etree + from utils import xml_indent + + project_tree = etree.parse('project.uvoptx') + root = project_tree.getroot() + out = file('project.uvoptx', 'wb') + + for elem in project_tree.iterfind('.//Target/TargetOption/TargetDriverDllRegistry/SetRegEntry'): + Key = elem.find('Key') + if Key.text in flash_dict.keys(): + elem.find('Name').text = flash_dict[Key.text] + + xml_indent(root) + out.write(etree.tostring(root, encoding='utf-8')) + out.close() + +if GetOption('target') and GetDepend('BOARD_USING_QSPIFLASH'): + Update_MDKFlashProgrammingAlgorithm({ + "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', + "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', + }) diff --git a/bsp/imxrt/imxrt1050-ArchMix/applications/SConscript b/bsp/imxrt/imxrt1050-ArchMix/applications/SConscript new file mode 100644 index 0000000000..0a4d797abe --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/applications/SConscript @@ -0,0 +1,16 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/applications/lcd_init.c b/bsp/imxrt/imxrt1050-ArchMix/applications/lcd_init.c new file mode 100644 index 0000000000..1fdebfd260 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/applications/lcd_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-06-12 Tanek first version + */ + +#include + +#if defined(PKG_USING_GUIENGINE) + +#include +int lcd_init(void) +{ + struct rt_device *device; + device = rt_device_find("lcd"); + if (device) + { + rtgui_graphic_set_device(device); + } + + return 0; +} +INIT_APP_EXPORT(lcd_init); +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/applications/main.c b/bsp/imxrt/imxrt1050-ArchMix/applications/main.c new file mode 100644 index 0000000000..559c07bd09 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/applications/main.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek first version + */ + +#include +#include +#include + +#ifdef RT_USING_DFS +#include +#endif + +#ifdef RT_USING_DEVICE +#include +#endif + +#include + +void dump_clock(void) +{ + rt_kprintf("OSC clock : %d\n", CLOCK_GetFreq(kCLOCK_OscClk)); + rt_kprintf("RTC clock : %d\n", CLOCK_GetFreq(kCLOCK_RtcClk)); + rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk)); + rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk)); + rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk)); + rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk)); + rt_kprintf("ARMPLLCLK(PLL1) : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); + rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); + rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); + rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); + rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); + rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); + rt_kprintf("USB1PLLCLK(PLL3) : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); + rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); + rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); + rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); + rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); + rt_kprintf("Audio PLLCLK(PLL4) : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); + rt_kprintf("Video PLLCLK(PLL5) : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); + rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); + rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); + rt_kprintf("USB2PLLCLK(PLL7) : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); +} + +void dump_cc_info(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif +} + +void dump_link_info(void) +{ +#if defined(__CC_ARM) + +#elif defined(__ICCARM__) + +#elif defined(__GNUC__) + #define DUMP_SYMBOL(__SYM) \ + extern int __SYM; \ + rt_kprintf("%s: %p\n", #__SYM, &__SYM) + + DUMP_SYMBOL(__fsymtab_start); + DUMP_SYMBOL(__fsymtab_end); + DUMP_SYMBOL(__vsymtab_start); + DUMP_SYMBOL(__vsymtab_end); + DUMP_SYMBOL(__rt_init_start); + DUMP_SYMBOL(__rt_init_end); + + DUMP_SYMBOL(__exidx_start); + DUMP_SYMBOL(__exidx_end); + + DUMP_SYMBOL(__etext); + + DUMP_SYMBOL(__data_start__); + DUMP_SYMBOL(__data_end__); + + DUMP_SYMBOL(__noncachedata_start__); + DUMP_SYMBOL(__noncachedata_init_end__); + + DUMP_SYMBOL(__noncachedata_end__); + + DUMP_SYMBOL(__bss_start__); + DUMP_SYMBOL(__bss_end__); + + DUMP_SYMBOL(stack_start); + DUMP_SYMBOL(stack_end); + + DUMP_SYMBOL(heap_start); +#endif +} + +int main(void) +{ + rt_uint32_t result; + //dump_clock(); + dump_cc_info(); + dump_link_info(); + + rt_kprintf("build time: %s %s\n", __DATE__, __TIME__); + +#if defined(RT_USING_DFS) && defined(RT_USING_SDIO) + result = mmcsd_wait_cd_changed(RT_TICK_PER_SECOND); + if (result == MMCSD_HOST_PLUGED) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } + else + { + rt_kprintf("sdcard init fail or timeout: %d!\n", result); + } +#endif +} + +/*@}*/ diff --git a/bsp/tm4c129x-dk/drivers/SConscript b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript similarity index 55% rename from bsp/tm4c129x-dk/drivers/SConscript rename to bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript index e5f4cd4945..a7090a02d3 100644 --- a/bsp/tm4c129x-dk/drivers/SConscript +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript @@ -1,14 +1,15 @@ from building import * cwd = GetCurrentDir() -src = Glob('*.c') -# remove no need file. -if GetDepend('RT_USING_LWIP') == False: - SrcRemove(src, 'drv_emac.c') +# add the general drivers. +src = Split(""" +board.c +""") CPPPATH = [cwd] +CPPDEFINES = [] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/board.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.c new file mode 100644 index 0000000000..68b20e2546 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + */ +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) +static struct rt_memheap system_heap; +#endif + +/* ARM PLL configuration for RUN mode */ +const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U }; + +/* SYS PLL configuration for RUN mode */ +const clock_sys_pll_config_t sysPllConfig = { .loopDivider = 1U }; + +/* USB1 PLL configuration for RUN mode */ +const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U }; + +static void BOARD_BootClockGate(void) +{ +// /* Disable all unused peripheral clock */ +// CCM->CCGR0 = 0x00C0000FU; +// CCM->CCGR1 = 0x30000000U; +// CCM->CCGR2 = 0x003F0030U; +// CCM->CCGR3 = 0xF0000330U; +// CCM->CCGR4 = 0x0000FF3CU; +// CCM->CCGR5 = 0xF000330FU; +// CCM->CCGR6 = 0x00FC0300U; +} + +static void BOARD_BootClockRUN(void) +{ + /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(24000000U); + CLOCK_SetRtcXtalFreq(32768U); + + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + + /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + + CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ +#ifndef SKIP_SYSCLK_INIT + CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */ +#endif +#ifndef SKIP_USB_PLL_INIT + CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ +#endif + CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ + + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ + + /* Disable unused clock */ + BOARD_BootClockGate(); + + /* Power down all unused PLL */ + CLOCK_DeinitAudioPll(); + CLOCK_DeinitVideoPll(); + CLOCK_DeinitEnetPll(); + CLOCK_DeinitUsb2Pll(); + + /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* Update core clock */ + SystemCoreClockUpdate(); +} + + +/* MPU configuration. */ +static void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + SCB_DisableICache(); + SCB_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Region 0 setting */ + MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 2 setting */ + // spi flash: normal type, cacheable, no bufferable, no shareable + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +#if defined(SDRAM_MPU_INIT) + /* Region 7 setting */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + /* Region 8 setting */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void SystemInitHook(void) +{ + BOARD_ConfigMPU(); + +#if defined(RT_USING_SDRAM) + extern int imxrt_sdram_init(void); + imxrt_sdram_init(); +#endif +} + +/** + * This function will initial rt1050 board. + */ +void rt_hw_board_init() +{ + BOARD_BootClockRUN(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); + rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END); + + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#else + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#endif +} + +/*@}*/ diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/board.h b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.h new file mode 100644 index 0000000000..c02e150258 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include + +#ifdef __CC_ARM +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) + +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +#define SDRAM_MPU_INIT +#define SDRAM_BEGIN (0x80000000u) +#define SDRAM_END (0x81E00000u) + +void rt_hw_board_init(void); + +#endif + +//*** <<< end of configuration section >>> *** diff --git a/bsp/imxrt/imxrt1050-ArchMix/figures/Arch_Mix.jpg b/bsp/imxrt/imxrt1050-ArchMix/figures/Arch_Mix.jpg new file mode 100644 index 0000000000..d430d0e19a Binary files /dev/null and b/bsp/imxrt/imxrt1050-ArchMix/figures/Arch_Mix.jpg differ diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ini b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ini new file mode 100644 index 0000000000..1e21d31013 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ini @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +FUNC void Setup (void) { + + SP = _RDWORD(0x60002000); // Setup Stack Pointer + PC = _RDWORD(0x60002004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + Setup(); // Setup for Running +} + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ld b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ld new file mode 100644 index 0000000000..b8c229ae3c --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ld @@ -0,0 +1,276 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 + + m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + PROVIDE(__ctors_start__ = .); + /* __CTOR_LIST__ = .; */ + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* __CTOR_END__ = .; */ + PROVIDE(__ctors_end__ = .); + } > m_text + + .dtors : + { + PROVIDE(__dtors_start__ = .); + /* __DTOR_LIST__ = .; */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* __DTOR_END__ = .; */ + PROVIDE(__dtors_end__ = .); + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_dtcm + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_dtcm + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_dtcm + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_dtcm + + PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf new file mode 100644 index 0000000000..5e0834cd48 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf @@ -0,0 +1,125 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x1F7FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#include "rtconfig.h" + +#if (defined(BOARD_USING_HYPERFLASH)) +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.ewd b/bsp/imxrt/imxrt1050-ArchMix/project.ewd new file mode 100644 index 0000000000..60c31a48ee --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + 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$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 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+ + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/tm4c129x-dk/project.ewp b/bsp/imxrt/imxrt1050-ArchMix/project.ewp similarity index 72% rename from bsp/tm4c129x-dk/project.ewp rename to bsp/imxrt/imxrt1050-ArchMix/project.ewp index aa39574c29..9ad86219cf 100644 --- a/bsp/tm4c129x-dk/project.ewp +++ b/bsp/imxrt/imxrt1050-ArchMix/project.ewp @@ -10,25 +10,25 @@ General 3 - 22 + 21 1 1 - ICCARM 2 - 31 + 28 1 1 - - - - AARM 2 - 9 + 8 1 1 - @@ -600,15 +589,15 @@ @@ -645,9 +634,13 @@ ILINK 0 - 16 + 14 1 1 + + - - - @@ -968,7 +951,7 @@ General 3 - 22 + 21 1 0 - ICCARM 2 - 31 + 28 1 0 - - - - AARM 2 - 9 + 8 1 0 - @@ -1603,7 +1575,7 @@ ILINK 0 - 16 + 14 1 0 + - - - @@ -1917,360 +1879,600 @@ - Libraries + Applications - $PROJ_DIR$\libraries/driverlib/adc.c + $PROJ_DIR$\applications\device_test.c - $PROJ_DIR$\libraries/driverlib/aes.c + $PROJ_DIR$\applications\main.c - $PROJ_DIR$\libraries/driverlib/can.c + $PROJ_DIR$\applications\mem_dump.c - $PROJ_DIR$\libraries/driverlib/comp.c - - - $PROJ_DIR$\libraries/driverlib/cpu.c - - - $PROJ_DIR$\libraries/driverlib/crc.c - - - $PROJ_DIR$\libraries/driverlib/des.c - - - $PROJ_DIR$\libraries/driverlib/eeprom.c - - - $PROJ_DIR$\libraries/driverlib/emac.c - - - $PROJ_DIR$\libraries/driverlib/epi.c - - - $PROJ_DIR$\libraries/driverlib/flash.c - - - $PROJ_DIR$\libraries/driverlib/fpu.c - - - $PROJ_DIR$\libraries/driverlib/gpio.c - - - $PROJ_DIR$\libraries/driverlib/hibernate.c - - - $PROJ_DIR$\libraries/driverlib/i2c.c - - - $PROJ_DIR$\libraries/driverlib/interrupt.c - - - $PROJ_DIR$\libraries/driverlib/lcd.c - - - $PROJ_DIR$\libraries/driverlib/mpu.c - - - $PROJ_DIR$\libraries/driverlib/pwm.c - - - $PROJ_DIR$\libraries/driverlib/qei.c - - - $PROJ_DIR$\libraries/driverlib/shamd5.c - - - $PROJ_DIR$\libraries/driverlib/ssi.c - - - $PROJ_DIR$\libraries/driverlib/sw_crc.c - - - $PROJ_DIR$\libraries/driverlib/sysctl.c - - - $PROJ_DIR$\libraries/driverlib/sysexc.c - - - $PROJ_DIR$\libraries/driverlib/systick.c - - - $PROJ_DIR$\libraries/driverlib/tiva_timer.c - - - $PROJ_DIR$\libraries/driverlib/uart.c - - - $PROJ_DIR$\libraries/driverlib/udma.c - - - $PROJ_DIR$\libraries/driverlib/usb.c - - - $PROJ_DIR$\libraries/driverlib/watchdog.c - - - $PROJ_DIR$\libraries/startup/startup_ewarm.c + $PROJ_DIR$\applications\mem_test.c Drivers - $PROJ_DIR$\drivers/drv_eth.c + $PROJ_DIR$\drivers\board.c - $PROJ_DIR$\drivers/drv_uart.c + $PROJ_DIR$\drivers\drv_uart.c + + + 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+ + + $PROJ_DIR$\Libraries\drivers\fsl_dmamux.c + + + $PROJ_DIR$\Libraries\drivers\fsl_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_elcdif.c + + + $PROJ_DIR$\Libraries\drivers\fsl_enc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_enet.c + + + $PROJ_DIR$\Libraries\drivers\fsl_ewm.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexcan.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_i2c_master.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_i2s.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_i2s_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_spi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_spi_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_uart.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_uart_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexram.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexspi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_gpc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_gpio.c + + + $PROJ_DIR$\Libraries\drivers\fsl_gpt.c + + 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$PROJ_DIR$\../../src/memheap.c + $PROJ_DIR$\..\..\src\object.c - $PROJ_DIR$\../../src/mempool.c + $PROJ_DIR$\..\..\src\scheduler.c - $PROJ_DIR$\../../src/object.c + $PROJ_DIR$\..\..\src\signal.c - $PROJ_DIR$\../../src/scheduler.c + $PROJ_DIR$\..\..\src\thread.c - $PROJ_DIR$\../../src/signal.c - - - $PROJ_DIR$\../../src/thread.c - - - $PROJ_DIR$\../../src/timer.c + $PROJ_DIR$\..\..\src\timer.c - CORTEX-M4 + CORTEX-M7 - $PROJ_DIR$\../../libcpu/arm/cortex-m4/cpuport.c + $PROJ_DIR$\..\..\libcpu\arm\cortex-m7\cpuport.c - $PROJ_DIR$\../../libcpu/arm/cortex-m4/context_iar.S + $PROJ_DIR$\..\..\libcpu\arm\cortex-m7\context_iar.S - $PROJ_DIR$\../../libcpu/arm/common/backtrace.c + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c - $PROJ_DIR$\../../libcpu/arm/common/div0.c + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\../../libcpu/arm/common/showmem.c + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + + Filesystem + + $PROJ_DIR$\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c DeviceDrivers - $PROJ_DIR$\../../components/drivers/serial/serial.c + $PROJ_DIR$\..\..\components\drivers\i2c\i2c_core.c - $PROJ_DIR$\../../components/drivers/src/completion.c + $PROJ_DIR$\..\..\components\drivers\i2c\i2c_dev.c - $PROJ_DIR$\../../components/drivers/src/dataqueue.c + $PROJ_DIR$\..\..\components\drivers\i2c\i2c-bit-ops.c - $PROJ_DIR$\../../components/drivers/src/pipe.c + $PROJ_DIR$\..\..\components\drivers\misc\pin.c - $PROJ_DIR$\../../components/drivers/src/ringbuffer.c + $PROJ_DIR$\..\..\components\drivers\rtc\rtc.c - $PROJ_DIR$\../../components/drivers/src/waitqueue.c + $PROJ_DIR$\..\..\components\drivers\sdio\block_dev.c - $PROJ_DIR$\../../components/drivers/src/workqueue.c + $PROJ_DIR$\..\..\components\drivers\sdio\mmcsd_core.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\sd.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\sdio.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\mmc.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\components\drivers\spi\spi_dev.c + + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c finsh - $PROJ_DIR$\../../components/finsh/shell.c + $PROJ_DIR$\..\..\components\finsh\shell.c - $PROJ_DIR$\../../components/finsh/symbol.c + $PROJ_DIR$\..\..\components\finsh\symbol.c - $PROJ_DIR$\../../components/finsh/cmd.c + $PROJ_DIR$\..\..\components\finsh\cmd.c - $PROJ_DIR$\../../components/finsh/finsh_compiler.c + $PROJ_DIR$\..\..\components\finsh\msh.c - $PROJ_DIR$\../../components/finsh/finsh_error.c + $PROJ_DIR$\..\..\components\finsh\msh_cmd.c - $PROJ_DIR$\../../components/finsh/finsh_heap.c + $PROJ_DIR$\..\..\components\finsh\msh_file.c - $PROJ_DIR$\../../components/finsh/finsh_init.c + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c - $PROJ_DIR$\../../components/finsh/finsh_node.c + $PROJ_DIR$\..\..\components\finsh\finsh_error.c - $PROJ_DIR$\../../components/finsh/finsh_ops.c + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c - $PROJ_DIR$\../../components/finsh/finsh_parser.c + $PROJ_DIR$\..\..\components\finsh\finsh_init.c - $PROJ_DIR$\../../components/finsh/finsh_var.c + $PROJ_DIR$\..\..\components\finsh\finsh_node.c - $PROJ_DIR$\../../components/finsh/finsh_vm.c + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c - $PROJ_DIR$\../../components/finsh/finsh_token.c + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c - LwIP + dlib - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/api_lib.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/api_msg.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\libc.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/err.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\rmtx.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/netbuf.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\stdio.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/netdb.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/netifapi.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/sockets.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/api/tcpip.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/arch/sys_arch.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/def.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/dhcp.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/dns.c + $PROJ_DIR$\..\..\components\libc\compilers\dlib\time.c + + + + lwIP + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/init.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_lib.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/memp.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_msg.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/netif.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\err.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/pbuf.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netbuf.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/raw.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netdb.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/stats.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netifapi.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/sys.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\sockets.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/tcp.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\tcpip.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/tcp_in.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\def.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/tcp_out.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\dns.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/timers.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/udp.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\init.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ip.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\memp.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\netif.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\pbuf.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\raw.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\stats.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\sys.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/netif/etharp.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/netif/ethernetif.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - $PROJ_DIR$\../../components/net/lwip-1.4.1/src/netif/slipif.c + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\udp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c diff --git a/bsp/tm4c129x-dk/project.eww b/bsp/imxrt/imxrt1050-ArchMix/project.eww similarity index 100% rename from bsp/tm4c129x-dk/project.eww rename to bsp/imxrt/imxrt1050-ArchMix/project.eww diff --git a/bsp/tm4c129x-dk/project.uvoptx b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx similarity index 53% rename from bsp/tm4c129x-dk/project.uvoptx rename to bsp/imxrt/imxrt1050-ArchMix/project.uvoptx index e93d27b151..0a3c8c8bc0 100644 --- a/bsp/tm4c129x-dk/project.uvoptx +++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx @@ -8,7 +8,7 @@ *.c *.s*; *.src; *.a* - *.obj + *.obj; *.o *.lib *.txt; *.h; *.inc *.plm @@ -22,7 +22,7 @@ - RT-Thread TM4C129X + RT-Thread IMXRT1052 0x4 ARM-ADS @@ -45,7 +45,7 @@ 79 66 8 - .\ + .\build\ 1 @@ -77,19 +77,7 @@ 0 1 - 4 - - - 0 - Tiva C Series TM4C1294 Connected LaunchPad Web Page (EK-TM4C1294XL) - http://http://www.ti.com/tool/ek-tm4c1294xl - - - 1 - DK-TM4C129X Connected Development Kit Web Page (DK-TM4C129x) - http://www.ti.com/tool/DK-TM4C129X - - + 8 0 1 @@ -112,7 +100,10 @@ 1 0 0 - 0 + 1 + 0 + 0 + 4 @@ -122,14 +113,24 @@ - - BIN\UL2CM3.DLL + .\flexspi_nor.ini + Segger\JL2CM3.dll + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000 + 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0TM4C129_1024 -FL0100000 -FS00 -FP0($$Device:TM4C129XNCZAD$Flash\TM4C129_1024.FLM) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) @@ -165,14 +166,21 @@ 0 - - - 0 + 0 + 0 + + + + + + + + - Libraries + Applications 0 0 0 @@ -184,8 +192,8 @@ 0 0 0 - libraries/driverlib/adc.c - adc.c + applications\lcd_init.c + lcd_init.c 0 0 @@ -196,368 +204,8 @@ 0 0 0 - libraries/driverlib/aes.c - aes.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - libraries/driverlib/can.c - can.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - libraries/driverlib/comp.c - comp.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - libraries/driverlib/cpu.c - cpu.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - libraries/driverlib/crc.c - crc.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - libraries/driverlib/des.c - des.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - libraries/driverlib/eeprom.c - eeprom.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - libraries/driverlib/emac.c - emac.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - libraries/driverlib/epi.c - epi.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - libraries/driverlib/flash.c - flash.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - libraries/driverlib/fpu.c - fpu.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - libraries/driverlib/gpio.c - gpio.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - libraries/driverlib/hibernate.c - hibernate.c - 0 - 0 - - - 1 - 15 - 1 - 0 - 0 - 0 - libraries/driverlib/i2c.c - i2c.c - 0 - 0 - - - 1 - 16 - 1 - 0 - 0 - 0 - libraries/driverlib/interrupt.c - interrupt.c - 0 - 0 - - - 1 - 17 - 1 - 0 - 0 - 0 - libraries/driverlib/lcd.c - lcd.c - 0 - 0 - - - 1 - 18 - 1 - 0 - 0 - 0 - libraries/driverlib/mpu.c - mpu.c - 0 - 0 - - - 1 - 19 - 1 - 0 - 0 - 0 - libraries/driverlib/pwm.c - pwm.c - 0 - 0 - - - 1 - 20 - 1 - 0 - 0 - 0 - libraries/driverlib/qei.c - qei.c - 0 - 0 - - - 1 - 21 - 1 - 0 - 0 - 0 - libraries/driverlib/shamd5.c - shamd5.c - 0 - 0 - - - 1 - 22 - 1 - 0 - 0 - 0 - libraries/driverlib/ssi.c - ssi.c - 0 - 0 - - - 1 - 23 - 1 - 0 - 0 - 0 - libraries/driverlib/sw_crc.c - sw_crc.c - 0 - 0 - - - 1 - 24 - 1 - 0 - 0 - 0 - libraries/driverlib/sysctl.c - sysctl.c - 0 - 0 - - - 1 - 25 - 1 - 0 - 0 - 0 - libraries/driverlib/sysexc.c - sysexc.c - 0 - 0 - - - 1 - 26 - 1 - 0 - 0 - 0 - libraries/driverlib/systick.c - systick.c - 0 - 0 - - - 1 - 27 - 1 - 0 - 0 - 0 - libraries/driverlib/tiva_timer.c - tiva_timer.c - 0 - 0 - - - 1 - 28 - 1 - 0 - 0 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../../src/kservice.c + ..\..\..\src\kservice.c kservice.c 0 0 - 4 - 44 + 3 + 20 1 0 0 0 - ../../src/mem.c - mem.c - 0 - 0 - - - 4 - 45 - 1 - 0 - 0 - 0 - ../../src/memheap.c + ..\..\..\src\memheap.c memheap.c 0 0 - 4 - 46 + 3 + 21 1 0 0 0 - ../../src/mempool.c + ..\..\..\src\mempool.c mempool.c 0 0 - 4 - 47 + 3 + 22 1 0 0 0 - ../../src/object.c + ..\..\..\src\object.c object.c 0 0 - 4 - 48 + 3 + 23 1 0 0 0 - ../../src/scheduler.c + ..\..\..\src\scheduler.c scheduler.c 0 0 - 4 - 49 + 3 + 24 1 0 0 0 - ../../src/signal.c + ..\..\..\src\signal.c signal.c 0 0 - 4 - 50 + 3 + 25 1 0 0 0 - ../../src/thread.c + ..\..\..\src\thread.c thread.c 0 0 - 4 - 51 + 3 + 26 1 0 0 0 - ../../src/timer.c + ..\..\..\src\timer.c timer.c 0 0 @@ -816,68 +516,172 @@ - CORTEX-M4 + CORTEX-M7 + 0 + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + cpuport.c + 0 + 0 + + + 4 + 28 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + context_rvds.S + 0 + 0 + + + 4 + 29 + 1 + 0 + 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..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + fsl_wdog.c + 0 + 0 + + + 9 + 130 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + fsl_xbara.c + 0 + 0 + + + 9 + 131 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + fsl_xbarb.c + 0 + 0 + + + 9 + 132 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + system_MIMXRT1052.c + 0 + 0 + + + 9 + 133 + 2 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\arm\startup_MIMXRT1052.s + startup_MIMXRT1052.s + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx new file mode 100644 index 0000000000..5efaa5332e --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx @@ -0,0 +1,1180 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + MIMXRT1052:M7 + NXP + NXP.iMXRT_DFP.1.0.2 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) + 0 + $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h + + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-imxrt + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread-mdk.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + SKIP_SYSCLK_INIT, EVK_MCIMXRM, CPU_MIMXRT1052DVL6B, RT_USING_ARM_LIBC, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 + + applications;.;drivers;..\Libraries\imxrt1050\drivers;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\flexspi_nor.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + lcd_init.c + 1 + applications\lcd_init.c + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_uart.c + 1 + ..\Libraries\imxrt1050\drivers\drv_uart.c + + + drv_cache.c + 1 + ..\Libraries\imxrt1050\drivers\drv_cache.c + + + drv_sdram.c + 1 + ..\Libraries\imxrt1050\drivers\drv_sdram.c + + + drv_pin.c + 1 + ..\Libraries\imxrt1050\drivers\drv_pin.c + + + drv_rtc.c + 1 + ..\Libraries\imxrt1050\drivers\drv_rtc.c + + + drv_spi_bus.c + 1 + ..\Libraries\imxrt1050\drivers\drv_spi_bus.c + + + drv_i2c.c + 1 + ..\Libraries\imxrt1050\drivers\drv_i2c.c + + + drv_lcd.c + 1 + ..\Libraries\imxrt1050\drivers\drv_lcd.c + + + drv_sdio.c + 1 + ..\Libraries\imxrt1050\drivers\drv_sdio.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M7 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + 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..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + libc + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\..\components\libc\compilers\armlibc\time.c + + + + + Libraries + + + fsl_adc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc.c + + + fsl_adc_etc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc_etc.c + + + fsl_aipstz.c + 1 + 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fsl_elcdif.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_elcdif.c + + + fsl_enc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enc.c + + + fsl_enet.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enet.c + + + fsl_ewm.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_ewm.c + + + fsl_flexcan.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexcan.c + + + fsl_flexio.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio.c + + + fsl_flexio_i2c_master.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2c_master.c + + + fsl_flexio_i2s.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s.c + + + fsl_flexio_i2s_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s_edma.c + + + fsl_flexio_spi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c + + + fsl_flexio_spi_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c + + + fsl_flexio_uart.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c + + + fsl_flexio_uart_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c + + + fsl_flexram.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c + + + fsl_flexspi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c + + + fsl_gpc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c + + + fsl_gpio.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c + + + fsl_gpt.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c + + + fsl_kpp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c + + + fsl_lpi2c.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + + + fsl_lpi2c_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + + + fsl_lpspi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + + + fsl_lpspi_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + + + fsl_lpuart.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + + + fsl_lpuart_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + + + fsl_pit.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + + + fsl_pmu.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + + + fsl_pwm.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + + + fsl_pxp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + + + fsl_qtmr.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + + + fsl_rtwdog.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + + + fsl_sai.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + + + fsl_sai_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + + + fsl_semc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + + + fsl_snvs_hp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + + + fsl_snvs_lp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + + + fsl_spdif.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + + + fsl_spdif_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + + fsl_src.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + + fsl_trng.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + + fsl_tsc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + + fsl_usdhc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + + fsl_wdog.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + + fsl_xbara.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + + fsl_xbarb.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + + system_MIMXRT1052.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + + startup_MIMXRT1052.s + 2 + ..\Libraries\imxrt1050\devices\MIMXRT1052\arm\startup_MIMXRT1052.s + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h new file mode 100644 index 0000000000..525013e73e --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h @@ -0,0 +1,232 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + +#define SOC_IMXRT1052 +#define BOARD_RT1050_ArchMix +#define BOARD_USING_QSPIFLASH + +/* RT1050 Bsp Config */ + +/* Select uart drivers */ + +#define RT_USING_UART1 + +/* Select spi bus and dev drivers */ + +#define LPSPI_CLK_SOURCE_FROM_PLL3PFD1 +#define LPSPI_CLK_SOURCE 0 +#define LPSPI_CLK_SOURCE_DIVIDER 8 +#define RT_USING_SPIBUS4 +#define LPSPI4_SCK_GPIO_2 +#define LPSPI4_SDO_GPIO_2 +#define LPSPI4_SDI_GPIO_2 + +/* Select iic bus drivers */ + +#define RT_USING_HW_I2C1 +#define HW_I2C1_BADURATE_100kHZ + +/* Select lcd driver */ + +/* Notice: Arch Mix Board para: 480*272 4 4 8 2 40 10 127 45 */ + +#define RT_USING_LCD +#define LCD_WIDTH 480 +#define LCD_HEIGHT 272 +#define LCD_HFP 4 +#define LCD_VFP 4 +#define LCD_HBP 8 +#define LCD_VBP 2 +#define LCD_HSW 40 +#define LCD_VSW 10 +#define LCD_BL_PIN 127 +#define LCD_RST_PIN 45 +#define RT_USING_SDRAM +#define RT_USING_RTC_HP + +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.py b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.py new file mode 100644 index 0000000000..1b4257884f --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.py @@ -0,0 +1,144 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/usr/local/Cellar/arm-none-eabi-gcc/7-2017-q4-major/gcc/bin/' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99 -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T flexspi_nor.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf' + + CFLAGS += ' --diag_suppress=66,1296,186' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + CXXFLAGS = CFLAGS + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config flexspi_nor.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/tm4c129x-dk/template.ewp b/bsp/imxrt/imxrt1050-ArchMix/template.ewp similarity index 90% rename from bsp/tm4c129x-dk/template.ewp rename to bsp/imxrt/imxrt1050-ArchMix/template.ewp index 97696050b6..cf4216d8b3 100644 --- a/bsp/tm4c129x-dk/template.ewp +++ b/bsp/imxrt/imxrt1050-ArchMix/template.ewp @@ -12,25 +12,25 @@ General 3 - 22 + 21 1 1 - ICCARM 2 - 31 + 28 1 1 - - - - AARM 2 - 9 + 8 1 1 - @@ -585,15 +560,15 @@ @@ -630,9 +605,13 @@ ILINK 0 - 16 + 14 1 1 + + - - - @@ -953,7 +922,7 @@ General 3 - 22 + 21 1 0 - ICCARM 2 - 31 + 28 1 0 - - - - AARM 2 - 9 + 8 1 0 - @@ -1571,7 +1515,7 @@ ILINK 0 - 16 + 14 1 0 + - - - diff --git a/bsp/imxrt/imxrt1050-ArchMix/template.uvoptx b/bsp/imxrt/imxrt1050-ArchMix/template.uvoptx new file mode 100644 index 0000000000..38055496d3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + .\flexspi_nor.ini + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) + + + 0 + CMSIS_AGDI + -X"" -O974 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/template.uvprojx b/bsp/imxrt/imxrt1050-ArchMix/template.uvprojx new file mode 100644 index 0000000000..f6b254976b --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/template.uvprojx @@ -0,0 +1,399 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + + + MIMXRT1052:M7 + NXP + NXP.iMXRT_DFP.1.0.2 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) + 0 + $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h + + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-imxrt + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread-mdk.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\flexspi_nor.scf + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/SConscript b/bsp/imxrt/imxrt1050-ArchMix/xip/SConscript new file mode 100644 index 0000000000..1b69f9e2e5 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/SConscript @@ -0,0 +1,23 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BOARD_USING_HYPERFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + + if rtconfig.CROSS_TOOL == 'keil': + LINKFLAGS = '--keep=*(.boot_hdr.ivt)' + LINKFLAGS += '--keep=*(.boot_hdr.boot_data)' + LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)' + LINKFLAGS += '--keep=*(.boot_hdr.conf)' + else: + LINKFLAGS = '' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') + +if GetDepend('BOARD_USING_QSPIFLASH'): + group = [] + Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000000..5addfdbfaf --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,139 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif +const uint8_t dcd_sdram[1072] = { +/*0000*/ 0xD2, 0x04, 0x30, 0x41, 0xCC, 0x03, 0xAC, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, +/*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, +/*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, +/*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, +/*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, +/*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, +/*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, +/*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, +/*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, +/*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, +/*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, +/*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, +/*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, +/*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, +/*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, +/*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, +/*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, +/*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, +/*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, +/*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, +/*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, +/*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, +/*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, +/*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, +/*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, +/*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, +/*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, +/*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, +/*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, +/*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, +/*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, +/*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, +/*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, +/*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, +/*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, +/*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, +/*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, +/*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, +/*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, +/*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, +/*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, +/*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, +/*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, +/*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, +/*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, +/*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, +/*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, +/*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, +/*0300*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, +/*0310*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, +/*0320*/ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, +/*0330*/ 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, +/*0340*/ 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, +/*0350*/ 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, +/*0360*/ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, +/*0370*/ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, +/*0380*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, +/*0390*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, +/*03a0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, +/*03b0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +/*03c0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +/*03d0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +/*03e0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +/*03f0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, +/*0400*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, +/*0410*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, +/*0420*/ 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09, +}; diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000000..073bf5229b --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,118 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.c b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 0000000000..67076dd62f --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,76 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t hyperflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) | + (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | + (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.h b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 0000000000..6d3b5269cd --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,299 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__ diff --git a/bsp/imxrt/imxrt1050-evk/.config b/bsp/imxrt/imxrt1050-evk/.config new file mode 100644 index 0000000000..ba6c3d19ad --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/.config @@ -0,0 +1,484 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=4 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RTC_SYNC_USING_NTP is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +CONFIG_RT_USING_PTHREADS=y +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP_IPV6 is not set +# CONFIG_RT_LWIP_IGMP is not set +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +# CONFIG_RT_LWIP_RAW is not set +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_CMSIS_LATEST_VERSION is not set +# CONFIG_PKG_USING_CMSIS_V500 is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_IMXRT1052=y +CONFIG_BOARD_USING_HYPERFLASH=y +# CONFIG_BOARD_USING_QSPIFLASH is not set +CONFIG_BOARD_RT1050_EVK=y +# CONFIG_BOARD_RT1050_FIRE is not set +# CONFIG_BOARD_RT1050_ShareBoard is not set +# CONFIG_BOARD_RT1050_ATK is not set +# CONFIG_BOARD_RT1050_SeeedStudio is not set + +# +# RT1050 Bsp Config +# + +# +# Select uart drivers +# +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART4 is not set +# CONFIG_RT_USING_UART5 is not set +# CONFIG_RT_USING_UART6 is not set +# CONFIG_RT_USING_UART7 is not set +# CONFIG_RT_USING_UART8 is not set + +# +# Select spi bus and dev drivers +# +CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set +CONFIG_LPSPI_CLK_SOURCE=0 +CONFIG_LPSPI_CLK_SOURCE_DIVIDER=8 +# CONFIG_RT_USING_SPIBUS1 is not set +# CONFIG_RT_USING_SPIBUS2 is not set +# CONFIG_RT_USING_SPIBUS3 is not set +CONFIG_RT_USING_SPIBUS4=y +CONFIG_LPSPI4_SCK_GPIO_1=y +# CONFIG_LPSPI4_SCK_GPIO_2 is not set +CONFIG_LPSPI4_SDO_GPIO_1=y +# CONFIG_LPSPI4_SDO_GPIO_2 is not set +CONFIG_LPSPI4_SDI_GPIO_1=y +# CONFIG_LPSPI4_SDI_GPIO_2 is not set +# CONFIG_RT_USING_SPI_FLASH is not set + +# +# Select iic bus drivers +# +CONFIG_RT_USING_HW_I2C1=y +CONFIG_HW_I2C1_BADURATE_100kHZ=y +# CONFIG_HW_I2C1_BADURATE_400kHZ is not set +# CONFIG_RT_USING_HW_I2C2 is not set +# CONFIG_RT_USING_HW_I2C3 is not set +# CONFIG_RT_USING_HW_I2C4 is not set + +# +# Select lcd driver +# + +# +# Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45 +# +CONFIG_RT_USING_LCD=y +CONFIG_LCD_WIDTH=480 +CONFIG_LCD_HEIGHT=272 +CONFIG_LCD_HFP=4 +CONFIG_LCD_VFP=4 +CONFIG_LCD_HBP=8 +CONFIG_LCD_VBP=2 +CONFIG_LCD_HSW=40 +CONFIG_LCD_VSW=10 +CONFIG_LCD_BL_PIN=106 +CONFIG_LCD_RST_PIN=45 +CONFIG_RT_USING_SDRAM=y +CONFIG_RT_USING_RTC_HP=y diff --git a/bsp/imxrt/imxrt1050-evk/Kconfig b/bsp/imxrt/imxrt1050-evk/Kconfig new file mode 100644 index 0000000000..6a9e202469 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/Kconfig @@ -0,0 +1,463 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMXRT1052 + bool + select ARCH_ARM_CORTEX_M7 + select ARCH_ARM_CORTEX_FPU + default y + +config BOARD_USING_HYPERFLASH + bool + default n +config BOARD_USING_QSPIFLASH + bool + default n + +# RT1050 board select! +choice + prompt "RT1050 Board select" + default BOARD_RT1050_EVK + config BOARD_RT1050_EVK + bool "RT1050_EVK" + select BOARD_USING_HYPERFLASH + config BOARD_RT1050_FIRE + bool "RT1050_FIRE" + select BOARD_USING_QSPIFLASH + config BOARD_RT1050_ShareBoard + bool "RT1050_ShareBoard" + select BOARD_USING_QSPIFLASH + config BOARD_RT1050_ATK + bool "RT1050_ATK" + select BOARD_USING_QSPIFLASH + config BOARD_RT1050_SeeedStudio + bool "RT1050_SeeedStudio" + select BOARD_USING_HYPERFLASH +endchoice + +menu "RT1050 Bsp Config" + +menu "Select uart drivers" + config RT_USING_UART1 + bool "Using uart1" + select RT_USING_SERIAL + default y + config RT_USING_UART2 + bool "Using uart2" + select RT_USING_SERIAL + default n + config RT_USING_UART3 + bool "Using uart3" + select RT_USING_SERIAL + default n +if !BOARD_RT1050_SeeedStudio + config RT_USING_UART4 + bool "Using uart4" + select RT_USING_SERIAL + default n + config RT_USING_UART5 + bool "Using uart5" + select RT_USING_SERIAL + default n + config RT_USING_UART6 + bool "Using uart6" + select RT_USING_SERIAL + default n +endif +if !BOARD_RT1050_ATK && !BOARD_RT1050_SeeedStudio + config RT_USING_UART7 + bool "Using uart7" + select RT_USING_SERIAL + default n +endif + config RT_USING_UART8 + bool "Using uart8" + select RT_USING_SERIAL + default n +endmenu + +menu "Select spi bus and dev drivers" + choice + prompt "SPI bus clock source" + default LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + + config LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + bool "PLL3PFD1" + config LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + bool "PLL3PFD0" + config LPSPI_CLK_SOURCE_FROM_PLL2 + bool "PLL2" + config LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + bool "PLL2PFD2" + endchoice + config LPSPI_CLK_SOURCE + int + default 0 if LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + default 1 if LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + default 2 if LPSPI_CLK_SOURCE_FROM_PLL2 + default 3 if LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + + config LPSPI_CLK_SOURCE_DIVIDER + int "SPI bus clock source divider" + range 1 8 + default 8 +if !BOARD_RT1050_SeeedStudio + config RT_USING_SPIBUS1 + bool "Using spi1 bus" + select RT_USING_SPI + default n + choice + prompt "spi1 bus sck io choice" + default LPSPI1_SCK_GPIO_1 + depends on RT_USING_SPIBUS1 + config LPSPI1_SCK_GPIO_1 + bool "GPIO_EMC_27" + config LPSPI1_SCK_GPIO_2 + bool "GPIO_SD_B0_00" + endchoice + choice + prompt "spi1 bus sdo io choice" + default LPSPI1_SDO_GPIO_1 + depends on RT_USING_SPIBUS1 + config LPSPI1_SDO_GPIO_1 + bool "GPIO_EMC_28" + config LPSPI1_SDO_GPIO_2 + bool "GPIO_SD_B0_02" + endchoice + choice + prompt "spi1 bus sdi io choice" + default LPSPI1_SDI_GPIO_1 + depends on RT_USING_SPIBUS1 + config LPSPI1_SDI_GPIO_1 + bool "GPIO_EMC_29" + config LPSPI1_SDI_GPIO_2 + bool "GPIO_SD_B0_03" + endchoice + + config RT_USING_SPIBUS2 + bool "Using spi2 bus" + select RT_USING_SPI + default n + choice + prompt "spi2 bus sck io choice" + default LPSPI2_SCK_GPIO_1 + depends on RT_USING_SPIBUS2 + config LPSPI2_SCK_GPIO_1 + bool "GPIO_SD_B1_07" + config LPSPI2_SCK_GPIO_2 + bool "GPIO_EMC_00" + endchoice + choice + prompt "spi2 bus sdo io choice" + default LPSPI2_SDO_GPIO_1 + depends on RT_USING_SPIBUS2 + config LPSPI2_SDO_GPIO_1 + bool "GPIO_SD_B1_08" + config LPSPI2_SDO_GPIO_2 + bool "GPIO_EMC_02" + endchoice + choice + prompt "spi2 bus sdi io choice" + default LPSPI2_SDI_GPIO_1 + depends on RT_USING_SPIBUS2 + config LPSPI2_SDI_GPIO_1 + bool "GPIO_SD_B1_09" + config LPSPI2_SDI_GPIO_2 + bool "GPIO_EMC_03" + endchoice +endif + config RT_USING_SPIBUS3 + bool "Using spi3 bus" + select RT_USING_SPI + default n + choice + prompt "spi3 bus sck io choice" + default LPSPI3_SCK_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SCK_GPIO_1 + bool "GPIO_AD_B1_15" + config LPSPI3_SCK_GPIO_2 + bool "GPIO_AD_B0_00" + depends on !BOARD_RT1050_SeeedStudio + endchoice + choice + prompt "spi3 bus sdo io choice" + default LPSPI3_SDO_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDO_GPIO_1 + bool "GPIO_AD_B1_14" + config LPSPI3_SDO_GPIO_2 + bool "GPIO_AD_B0_01" + depends on !BOARD_RT1050_SeeedStudio + endchoice + choice + prompt "spi3 bus sdi io choice" + default LPSPI3_SDI_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDI_GPIO_1 + bool "GPIO_AD_B1_13" + config LPSPI3_SDI_GPIO_2 + bool "GPIO_AD_B0_02" + depends on !BOARD_RT1050_SeeedStudio + endchoice + + config RT_USING_SPIBUS4 + bool "Using spi4 bus" + select RT_USING_SPI + default y + choice + prompt "spi4 bus sck io choice" + default LPSPI4_SCK_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SCK_GPIO_1 + bool "GPIO_B0_03" + depends on !BOARD_RT1050_SeeedStudio + config LPSPI4_SCK_GPIO_2 + bool "GPIO_B1_07" + endchoice + choice + prompt "spi4 bus sdo io choice" + default LPSPI4_SDO_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDO_GPIO_1 + bool "GPIO_B0_02" + depends on !BOARD_RT1050_SeeedStudio + config LPSPI4_SDO_GPIO_2 + bool "GPIO_B1_06" + endchoice + choice + prompt "spi4 bus sdi io choice" + default LPSPI4_SDI_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDI_GPIO_1 + bool "GPIO_B0_01" + depends on !BOARD_RT1050_SeeedStudio + config LPSPI4_SDI_GPIO_2 + bool "GPIO_B1_05" + endchoice + + config RT_USING_SPI_FLASH + bool "Using spi flash with sfud" + default n + select RT_USING_SPI + select RT_USING_SFUD + select RT_USING_PIN + choice + prompt "SPI flash using spibus" + default SPI_FLASH_USING_SPIBUS4 + depends on RT_USING_SPI_FLASH + + config SPI_FLASH_USING_SPIBUS1 + bool "spi1" + select RT_USING_SPIBUS1 + config SPI_FLASH_USING_SPIBUS2 + bool "spi2" + select RT_USING_SPIBUS2 + config SPI_FLASH_USING_SPIBUS3 + bool "spi3" + select RT_USING_SPIBUS3 + config SPI_FLASH_USING_SPIBUS4 + bool "spi4" + select RT_USING_SPIBUS4 + endchoice + config SPI_FLASH_USING_SPIBUS_NAME + string + default "spi1" if SPI_FLASH_USING_SPIBUS1 + default "spi2" if SPI_FLASH_USING_SPIBUS2 + default "spi3" if SPI_FLASH_USING_SPIBUS3 + default "spi4" if SPI_FLASH_USING_SPIBUS4 + + config SPI_FLASH_NAME + string "SPI flash device name" + default "flash0" + depends on RT_USING_SPI_FLASH + + config SPI_FLASH_USING_CS_PIN + int "SPI flash cs pin index" + default 79 + range 1 127 + depends on RT_USING_SPI_FLASH +endmenu + +menu "Select iic bus drivers" + + config RT_USING_HW_I2C1 + bool "using hardware i2c1" + select RT_USING_I2C + default y + choice + prompt "i2c1 bus badurate choice" + default HW_I2C1_BADURATE_100kHZ + depends on RT_USING_HW_I2C1 + config HW_I2C1_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C1_BADURATE_400kHZ + bool "400kHZ" + endchoice +if !BOARD_RT1050_SeeedStudio + config RT_USING_HW_I2C2 + bool "using hardware i2c2" + select RT_USING_I2C + default n + choice + prompt "i2c2 bus badurate choice" + default HW_I2C2_BADURATE_100kHZ + depends on RT_USING_HW_I2C2 + config HW_I2C2_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C2_BADURATE_400kHZ + bool "400kHZ" + endchoice +endif + config RT_USING_HW_I2C3 + bool "using hardware i2c3" + select RT_USING_I2C + default n + choice + prompt "i2c3 bus badurate choice" + default HW_I2C3_BADURATE_100kHZ + depends on RT_USING_HW_I2C3 + config HW_I2C3_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C3_BADURATE_400kHZ + bool "400kHZ" + endchoice + + config RT_USING_HW_I2C4 + bool "using hardware i2c4" + select RT_USING_I2C + default n + choice + prompt "i2c4 bus badurate choice" + default HW_I2C4_BADURATE_100kHZ + depends on RT_USING_HW_I2C4 + config HW_I2C4_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C4_BADURATE_400kHZ + bool "400kHZ" + endchoice + +endmenu + +menu "Select lcd driver" + if RT_USING_LCD && BOARD_RT1050_EVK + comment "Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45" + endif + + if RT_USING_LCD && BOARD_RT1050_ShareBoard + comment "Notice: ShareBoard Board para: 800*480 4 4 8 2 40 10 58 45" + endif + + if RT_USING_LCD && BOARD_RT1050_FIRE + comment "Notice: Fire Board para: 800*480 4 4 8 2 40 10 58 45" + endif + + if RT_USING_LCD && BOARD_RT1050_ATK + comment "Notice: ATK Board para: 480*272 4 4 8 2 40 10 109 45" + endif + + if RT_USING_LCD && BOARD_RT1050_SeeedStudio + comment "Notice: SeeedStudio Board para: 480*272 4 4 8 2 40 10 127 45" + endif + + config RT_USING_LCD + bool "Using lcd" + default n + + config LCD_WIDTH + int "Width pixel num" + default 480 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 800 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_HEIGHT + int "Height pixel num" + default 272 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 480 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_HFP + int "HFP" + default 4 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 4 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_VFP + int "VFP" + default 4 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 4 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_HBP + int "HBP" + default 8 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 8 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_VBP + int "VBP" + default 2 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 2 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_HSW + int "HSW" + default 40 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 40 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_VSW + int "VSW" + default 10 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 10 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_BL_PIN + int "Backlight pin index" + default 127 if BOARD_RT1050_SeeedStudio + default 109 if BOARD_RT1050_ATK + default 106 if BOARD_RT1050_EVK + default 58 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD + config LCD_RST_PIN + int "Reset pin index" + default 45 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) + default 45 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) + depends on RT_USING_LCD +endmenu + +#menu "Select SDRAM driver" + config RT_USING_SDRAM + bool "Using sdram" + default y +#endmenu + +#menu "Select RTC driver" + config RT_USING_RTC_HP + bool "Using hp rtc" + select RT_USING_RTC + default n +#endmenu + +if RT_USING_USB_DEVICE + choice + prompt "select usb device controller" + default RT_USING_EHCI0_AS_DEVICE + + config RT_USING_EHCI0_AS_DEVICE + bool "set EHCI0 as device" + config RT_USING_EHCI1_AS_DEVICE + bool "set EHCI1 as device" + endchoice +endif + +endmenu diff --git a/bsp/imxrt/imxrt1050-evk/README.md b/bsp/imxrt/imxrt1050-evk/README.md new file mode 100644 index 0000000000..8f90f6f119 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/README.md @@ -0,0 +1,105 @@ +# i.MX RT1050 + +## 1. 简介 + +i.MX RT 1050系列芯片，是由 NXP 半导体公司推出的跨界处理器芯片。它基于应用处理器的芯片架构，采用了微控制器的内核Cortex-M7，从而具有应用处理器的高性能及丰富的功能，又具备传统微控制器的易用、实时及低功耗的特性。 + +BSP默认支持的i.MX RT1052处理器具备以下简要的特性： + +| 介绍 | 描述 | +| ---- | ---- | +| 主CPU平台 | ARM Cortex-M7 | +| 最高频率 | 600MHz | +| 内部存储器 | 512KB SRAM | +| 外部存储器接口 | NAND、eMMC、QuadSPI NOR Flash 和 Parallel NOR Flash | + +## 2. 编译说明 + +i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | --------- | +| MDK5 | MDK525 | +| IAR | IAR 8.11.3.13984 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 3.BSP使用 + +### 3.1 配置工程 + +i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野火的i.MX RT1052开发板等。如果不是基于官方开发板，那么需要重新配置并生成工程： + +- 在bsp下打开env工具 +- 输入`menuconfig`命令，`RT1052 Board select (***)-->`选择正确的开发板。 +- 输入`scons --target=mdk5 -s`或`scons --target=iar`来生成需要的工程 + +### 3.2 下载和仿真 + +#### 3.2.1 MIMXRT1050-EVK + +EVK开发板有板载OpenSDA仿真器，仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28)，就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口。 + +#### 3.2.2 野火开发板 +连接外置仿真器（野火DAP仿真器或者Jlink）后，就可以进行下载和仿真。使用USB线连接开发板底板的USB转串口，在终端工具里打开相应的串口。 + +#### 3.2.3 ShareBoard开发板 + +连接外置仿真器Jlink后，就可以进行下载和仿真。使用USB线连接开发板底板的USB转串口，在终端工具里打开相应的串口。 + +#### 3.2.4 正点原子开发板 + +连接外置仿真器（正点原子DAP仿真器或者Jlink）后，就可以进行下载和仿真。使用USB线连接开发板底板的USB_232，在终端工具里打开相应的串口。 + +#### 3.2.5 SeeedStudio开发板 + +连接外置仿真器Jlink后，就可以进行下载和仿真。使用TTL转串口工具连接开发板上J3的17/18引脚，在终端工具里打开相应的串口。(17接RX，18接TX) + +### 3.3 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +``` + + \ | / +- RT - Thread Operating System + / | \ 3.0.4 build May 2 2018 + 2006 - 2018 Copyright by rt-thread team +lwIP-2.0.2 initialized! +using armcc, version: 5060750 +build time: May 2 2018 21:52:40 +msh />[PHY] wait autonegotiation complete... +SD card capacity 123904 KB +probe mmcsd block device! +found part[0], begin: 32256, size: 120.992MB +File System initialized! +[PHY] wait autonegotiation complete... +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | ------ | +| UART | 支持 | UART 1~8 | +| GPIO | 支持 | | +| IIC | 支持 | IIC 1~4 | +| SPI | 支持 | SPI 1~4 | +| ETH | 支持 | 暂时仅支持官方的ETH | +| LCD | 支持 | | +| RTC | 支持 | | +| SDIO | 支持 | 暂时仅仅支持一个SDIO，还不支持中断方式 | +| SDRAM | 支持 | 32M SDRAM，后面2M作为Non Cache区域 | + +## 5. 联系人信息 + +维护人： + +- [tanek](https://github.com/TanekLiang) +- [liu2guang](https://github.com/liu2guang) + +## 6. 参考 + +- [MIMXRT1050-EVK: i.MX RT1050评估套件概述](https://www.nxp.com/cn/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK) +- [MIMXRT1050 EVK Board Hardware User’s Guide ](https://www.nxp.com/docs/en/user-guide/MIMXRT1050EVKHUG.pdf) +- [i.MX RT Series Crossover Processor Quick Start Guide](https://www.nxp.com/docs/en/user-guide/IMXRT1050EVKQSG.pdf) +- [i.MX RT Series Crossover Processor Fact Sheet](https://www.nxp.com/docs/en/fact-sheet/IMXRTSERIESFS.pdf) +- [Evaluation Kit Based on i.MX RT1050 Crossover Processors](https://www.nxp.com/docs/en/fact-sheet/IMXRT1050EVKFS.pdf) diff --git a/bsp/imxrt/imxrt1050-evk/SConscript b/bsp/imxrt/imxrt1050-evk/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imxrt/imxrt1050-evk/SConstruct b/bsp/imxrt/imxrt1050-evk/SConstruct new file mode 100644 index 0000000000..5f99b4eed1 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/SConstruct @@ -0,0 +1,49 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-imxrt.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +objs = objs + SConscript('../Libraries/imxrt1050/SConscript') + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1050-evk/applications/SConscript b/bsp/imxrt/imxrt1050-evk/applications/SConscript new file mode 100644 index 0000000000..0a4d797abe --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/applications/SConscript @@ -0,0 +1,16 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/imxrt1050-evk/applications/lcd_init.c b/bsp/imxrt/imxrt1050-evk/applications/lcd_init.c new file mode 100644 index 0000000000..1fdebfd260 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/applications/lcd_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-06-12 Tanek first version + */ + +#include + +#if defined(PKG_USING_GUIENGINE) + +#include +int lcd_init(void) +{ + struct rt_device *device; + device = rt_device_find("lcd"); + if (device) + { + rtgui_graphic_set_device(device); + } + + return 0; +} +INIT_APP_EXPORT(lcd_init); +#endif diff --git a/bsp/imxrt/imxrt1050-evk/applications/main.c b/bsp/imxrt/imxrt1050-evk/applications/main.c new file mode 100644 index 0000000000..559c07bd09 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/applications/main.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek first version + */ + +#include +#include +#include + +#ifdef RT_USING_DFS +#include +#endif + +#ifdef RT_USING_DEVICE +#include +#endif + +#include + +void dump_clock(void) +{ + rt_kprintf("OSC clock : %d\n", CLOCK_GetFreq(kCLOCK_OscClk)); + rt_kprintf("RTC clock : %d\n", CLOCK_GetFreq(kCLOCK_RtcClk)); + rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk)); + rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk)); + rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk)); + rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk)); + rt_kprintf("ARMPLLCLK(PLL1) : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); + rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); + rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); + rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); + rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); + rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); + rt_kprintf("USB1PLLCLK(PLL3) : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); + rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); + rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); + rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); + rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); + rt_kprintf("Audio PLLCLK(PLL4) : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); + rt_kprintf("Video PLLCLK(PLL5) : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); + rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); + rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); + rt_kprintf("USB2PLLCLK(PLL7) : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); +} + +void dump_cc_info(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif +} + +void dump_link_info(void) +{ +#if defined(__CC_ARM) + +#elif defined(__ICCARM__) + +#elif defined(__GNUC__) + #define DUMP_SYMBOL(__SYM) \ + extern int __SYM; \ + rt_kprintf("%s: %p\n", #__SYM, &__SYM) + + DUMP_SYMBOL(__fsymtab_start); + DUMP_SYMBOL(__fsymtab_end); + DUMP_SYMBOL(__vsymtab_start); + DUMP_SYMBOL(__vsymtab_end); + DUMP_SYMBOL(__rt_init_start); + DUMP_SYMBOL(__rt_init_end); + + DUMP_SYMBOL(__exidx_start); + DUMP_SYMBOL(__exidx_end); + + DUMP_SYMBOL(__etext); + + DUMP_SYMBOL(__data_start__); + DUMP_SYMBOL(__data_end__); + + DUMP_SYMBOL(__noncachedata_start__); + DUMP_SYMBOL(__noncachedata_init_end__); + + DUMP_SYMBOL(__noncachedata_end__); + + DUMP_SYMBOL(__bss_start__); + DUMP_SYMBOL(__bss_end__); + + DUMP_SYMBOL(stack_start); + DUMP_SYMBOL(stack_end); + + DUMP_SYMBOL(heap_start); +#endif +} + +int main(void) +{ + rt_uint32_t result; + //dump_clock(); + dump_cc_info(); + dump_link_info(); + + rt_kprintf("build time: %s %s\n", __DATE__, __TIME__); + +#if defined(RT_USING_DFS) && defined(RT_USING_SDIO) + result = mmcsd_wait_cd_changed(RT_TICK_PER_SECOND); + if (result == MMCSD_HOST_PLUGED) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } + else + { + rt_kprintf("sdcard init fail or timeout: %d!\n", result); + } +#endif +} + +/*@}*/ diff --git a/bsp/imxrt/imxrt1050-evk/drivers/SConscript b/bsp/imxrt/imxrt1050-evk/drivers/SConscript new file mode 100644 index 0000000000..a7090a02d3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/drivers/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +CPPPATH = [cwd] +CPPDEFINES = [] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/imxrt1050-evk/drivers/board.c b/bsp/imxrt/imxrt1050-evk/drivers/board.c new file mode 100644 index 0000000000..68b20e2546 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/drivers/board.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + */ +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) +static struct rt_memheap system_heap; +#endif + +/* ARM PLL configuration for RUN mode */ +const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U }; + +/* SYS PLL configuration for RUN mode */ +const clock_sys_pll_config_t sysPllConfig = { .loopDivider = 1U }; + +/* USB1 PLL configuration for RUN mode */ +const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U }; + +static void BOARD_BootClockGate(void) +{ +// /* Disable all unused peripheral clock */ +// CCM->CCGR0 = 0x00C0000FU; +// CCM->CCGR1 = 0x30000000U; +// CCM->CCGR2 = 0x003F0030U; +// CCM->CCGR3 = 0xF0000330U; +// CCM->CCGR4 = 0x0000FF3CU; +// CCM->CCGR5 = 0xF000330FU; +// CCM->CCGR6 = 0x00FC0300U; +} + +static void BOARD_BootClockRUN(void) +{ + /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(24000000U); + CLOCK_SetRtcXtalFreq(32768U); + + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + + /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + + CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ +#ifndef SKIP_SYSCLK_INIT + CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */ +#endif +#ifndef SKIP_USB_PLL_INIT + CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ +#endif + CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ + + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ + + /* Disable unused clock */ + BOARD_BootClockGate(); + + /* Power down all unused PLL */ + CLOCK_DeinitAudioPll(); + CLOCK_DeinitVideoPll(); + CLOCK_DeinitEnetPll(); + CLOCK_DeinitUsb2Pll(); + + /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* Update core clock */ + SystemCoreClockUpdate(); +} + + +/* MPU configuration. */ +static void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + SCB_DisableICache(); + SCB_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Region 0 setting */ + MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 2 setting */ + // spi flash: normal type, cacheable, no bufferable, no shareable + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +#if defined(SDRAM_MPU_INIT) + /* Region 7 setting */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + /* Region 8 setting */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void SystemInitHook(void) +{ + BOARD_ConfigMPU(); + +#if defined(RT_USING_SDRAM) + extern int imxrt_sdram_init(void); + imxrt_sdram_init(); +#endif +} + +/** + * This function will initial rt1050 board. + */ +void rt_hw_board_init() +{ + BOARD_BootClockRUN(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); + rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END); + + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#else + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#endif +} + +/*@}*/ diff --git a/bsp/imxrt/imxrt1050-evk/drivers/board.h b/bsp/imxrt/imxrt1050-evk/drivers/board.h new file mode 100644 index 0000000000..c02e150258 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/drivers/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include + +#ifdef __CC_ARM +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) + +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +#define SDRAM_MPU_INIT +#define SDRAM_BEGIN (0x80000000u) +#define SDRAM_END (0x81E00000u) + +void rt_hw_board_init(void); + +#endif + +//*** <<< end of configuration section >>> *** diff --git a/bsp/imxrt/imxrt1050-evk/flexspi_nor.ini b/bsp/imxrt/imxrt1050-evk/flexspi_nor.ini new file mode 100644 index 0000000000..1e21d31013 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/flexspi_nor.ini @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +FUNC void Setup (void) { + + SP = _RDWORD(0x60002000); // Setup Stack Pointer + PC = _RDWORD(0x60002004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + Setup(); // Setup for Running +} + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/imxrt/imxrt1050-evk/flexspi_nor.ld b/bsp/imxrt/imxrt1050-evk/flexspi_nor.ld new file mode 100644 index 0000000000..b8c229ae3c --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/flexspi_nor.ld @@ -0,0 +1,276 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 + + m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + PROVIDE(__ctors_start__ = .); + /* __CTOR_LIST__ = .; */ + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* __CTOR_END__ = .; */ + PROVIDE(__ctors_end__ = .); + } > m_text + + .dtors : + { + PROVIDE(__dtors_start__ = .); + /* __DTOR_LIST__ = .; */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* __DTOR_END__ = .; */ + PROVIDE(__dtors_end__ = .); + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_dtcm + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_dtcm + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_dtcm + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_dtcm + + PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf b/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf new file mode 100644 index 0000000000..5e0834cd48 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf @@ -0,0 +1,125 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x1F7FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#include "rtconfig.h" + +#if (defined(BOARD_USING_HYPERFLASH)) +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/imxrt1050-evk/project.ewd b/bsp/imxrt/imxrt1050-evk/project.ewd new file mode 100644 index 0000000000..60c31a48ee --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + 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### uVision Project, (C) Keil Software
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4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + SKIP_SYSCLK_INIT, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, CPU_MIMXRT1052DVL6B, RT_USING_ARM_LIBC + + applications;.;drivers;..\Libraries\imxrt1050\drivers;xip;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\pthreads;..\..\..\components\libc\time;..\..\..\components\net\lwip-2.0.2\src;..\..\..\components\net\lwip-2.0.2\src\include;..\..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\..\components\net\lwip-2.0.2\src\arch\include;..\..\..\components\net\lwip-2.0.2\src\include\netif;..\..\..\components\net\lwip-2.0.2\src\include\posix;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities 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fsl_lpi2c.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + + + fsl_lpi2c_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + + + fsl_lpspi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + + + fsl_lpspi_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + + + fsl_lpuart.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + + + fsl_lpuart_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + + + fsl_pit.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + + + fsl_pmu.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + + + fsl_pwm.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + + + fsl_pxp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + + + fsl_qtmr.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + + + fsl_rtwdog.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + + + fsl_sai.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + + + fsl_sai_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + + + fsl_semc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + + + fsl_snvs_hp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + + + fsl_snvs_lp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + + + fsl_spdif.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + + + fsl_spdif_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + + fsl_src.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + + fsl_trng.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + + fsl_tsc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + + fsl_usdhc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + + fsl_wdog.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + + fsl_xbara.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + + fsl_xbarb.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + + system_MIMXRT1052.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + + startup_MIMXRT1052.s + 2 + ..\Libraries\imxrt1050\devices\MIMXRT1052\arm\startup_MIMXRT1052.s + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1050-evk/rtconfig.h b/bsp/imxrt/imxrt1050-evk/rtconfig.h new file mode 100644 index 0000000000..b5e68cdab9 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/rtconfig.h @@ -0,0 +1,269 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_PTHREADS +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP202 +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_NETIF_LOOPBACK 0 + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + +#define SOC_IMXRT1052 +#define BOARD_USING_HYPERFLASH +#define BOARD_RT1050_EVK + +/* RT1050 Bsp Config */ + +/* Select uart drivers */ + +#define RT_USING_UART1 + +/* Select spi bus and dev drivers */ + +#define LPSPI_CLK_SOURCE_FROM_PLL3PFD1 +#define LPSPI_CLK_SOURCE 0 +#define LPSPI_CLK_SOURCE_DIVIDER 8 +#define RT_USING_SPIBUS4 +#define LPSPI4_SCK_GPIO_1 +#define LPSPI4_SDO_GPIO_1 +#define LPSPI4_SDI_GPIO_1 + +/* Select iic bus drivers */ + +#define RT_USING_HW_I2C1 +#define HW_I2C1_BADURATE_100kHZ + +/* Select lcd driver */ + +/* Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45 */ + +#define RT_USING_LCD +#define LCD_WIDTH 480 +#define LCD_HEIGHT 272 +#define LCD_HFP 4 +#define LCD_VFP 4 +#define LCD_HBP 8 +#define LCD_VBP 2 +#define LCD_HSW 40 +#define LCD_VSW 10 +#define LCD_BL_PIN 106 +#define LCD_RST_PIN 45 +#define RT_USING_SDRAM +#define RT_USING_RTC_HP + +#endif diff --git a/bsp/imxrt/imxrt1050-evk/rtconfig.py b/bsp/imxrt/imxrt1050-evk/rtconfig.py new file mode 100644 index 0000000000..1b4257884f --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/rtconfig.py @@ -0,0 +1,144 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/usr/local/Cellar/arm-none-eabi-gcc/7-2017-q4-major/gcc/bin/' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99 -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T flexspi_nor.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf' + + CFLAGS += ' --diag_suppress=66,1296,186' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + CXXFLAGS = CFLAGS + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config flexspi_nor.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/imxrt/imxrt1050-evk/template.ewp b/bsp/imxrt/imxrt1050-evk/template.ewp new file mode 100644 index 0000000000..cf4216d8b3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/template.ewp @@ -0,0 +1,1823 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/imxrt/imxrt1050-evk/template.uvoptx b/bsp/imxrt/imxrt1050-evk/template.uvoptx new file mode 100644 index 0000000000..38055496d3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + .\flexspi_nor.ini + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) + + + 0 + CMSIS_AGDI + -X"" -O974 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/imxrt/imxrt1050-evk/template.uvprojx b/bsp/imxrt/imxrt1050-evk/template.uvprojx new file mode 100644 index 0000000000..f6b254976b --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/template.uvprojx @@ -0,0 +1,399 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + + + MIMXRT1052:M7 + NXP + NXP.iMXRT_DFP.1.0.2 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) + 0 + $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h + + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-imxrt + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread-mdk.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\flexspi_nor.scf + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1050-evk/xip/SConscript b/bsp/imxrt/imxrt1050-evk/xip/SConscript new file mode 100644 index 0000000000..1b69f9e2e5 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/xip/SConscript @@ -0,0 +1,23 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BOARD_USING_HYPERFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + + if rtconfig.CROSS_TOOL == 'keil': + LINKFLAGS = '--keep=*(.boot_hdr.ivt)' + LINKFLAGS += '--keep=*(.boot_hdr.boot_data)' + LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)' + LINKFLAGS += '--keep=*(.boot_hdr.conf)' + else: + LINKFLAGS = '' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') + +if GetDepend('BOARD_USING_QSPIFLASH'): + group = [] + Return('group') diff --git a/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000000..5addfdbfaf --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,139 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif +const uint8_t dcd_sdram[1072] = { +/*0000*/ 0xD2, 0x04, 0x30, 0x41, 0xCC, 0x03, 0xAC, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, +/*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, +/*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, +/*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, +/*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, +/*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, +/*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, +/*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, +/*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, +/*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, +/*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, +/*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, +/*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, +/*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, +/*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, +/*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, +/*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, +/*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, +/*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, +/*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, +/*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, +/*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, +/*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, +/*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, +/*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, +/*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, +/*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, +/*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, +/*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, +/*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, +/*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, +/*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, +/*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, +/*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, +/*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, +/*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, +/*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, +/*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, +/*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, +/*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, +/*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, +/*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, +/*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, +/*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, +/*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, +/*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, +/*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, +/*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, +/*0300*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, +/*0310*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, +/*0320*/ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, +/*0330*/ 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, +/*0340*/ 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, +/*0350*/ 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, +/*0360*/ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, +/*0370*/ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, +/*0380*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, +/*0390*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, +/*03a0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, +/*03b0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +/*03c0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +/*03d0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +/*03e0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +/*03f0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, +/*0400*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, +/*0410*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, +/*0420*/ 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09, +}; diff --git a/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000000..073bf5229b --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,118 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_flash.c b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 0000000000..67076dd62f --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,76 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t hyperflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) | + (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | + (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; diff --git a/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_flash.h b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 0000000000..6d3b5269cd --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,299 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__ diff --git a/bsp/imxrt1052-evk/drivers/drv_eth.c b/bsp/imxrt1052-evk/drivers/drv_eth.c index a884d8d065..2ffe06c8d2 100644 --- a/bsp/imxrt1052-evk/drivers/drv_eth.c +++ b/bsp/imxrt1052-evk/drivers/drv_eth.c @@ -676,13 +676,13 @@ static void _enet_config(void) /* Set SMI to get PHY link status. */ sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); - dbg_log(DBG_LOG, "deinit\n"); + LOG_D("deinit"); ENET_Deinit(imxrt_eth_device.enet_base); - dbg_log(DBG_LOG, "init\n"); + LOG_D("init"); ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); - dbg_log(DBG_LOG, "set call back\n"); + LOG_D("set call back"); ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); - dbg_log(DBG_LOG, "active read\n"); + LOG_D("active read"); ENET_ActiveRead(imxrt_eth_device.enet_base); } @@ -726,7 +726,7 @@ static void packet_dump(const char *msg, const struct pbuf *p) /* initialize the interface */ static rt_err_t rt_imxrt_eth_init(rt_device_t dev) { - dbg_log(DBG_LOG, "rt_imxrt_eth_init...\n"); + LOG_D("rt_imxrt_eth_init..."); _enet_config(); return RT_EOK; @@ -734,33 +734,33 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev) static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) { - dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n"); + LOG_D("rt_imxrt_eth_open..."); return RT_EOK; } static rt_err_t rt_imxrt_eth_close(rt_device_t dev) { - dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n"); + LOG_D("rt_imxrt_eth_close..."); return RT_EOK; } static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) { - dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n"); + LOG_D("rt_imxrt_eth_read..."); rt_set_errno(-RT_ENOSYS); return 0; } static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n"); + LOG_D("rt_imxrt_eth_write..."); rt_set_errno(-RT_ENOSYS); return 0; } static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) { - dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n"); + LOG_D("rt_imxrt_eth_control..."); switch (cmd) { case NIOCTL_GADDR: @@ -969,7 +969,7 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) RT_ASSERT(p != NULL); RT_ASSERT(enet_handle != RT_NULL); - dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len); + LOG_D("rt_imxrt_eth_tx: %d", p->len); #ifdef ETH_TX_DUMP packet_dump("send", p); @@ -1023,18 +1023,18 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) } else { - dbg_log(DBG_LOG, " A frame read failed\n"); + LOG_D(" A frame read failed"); pbuf_free(p); } } else { - dbg_log(DBG_LOG, " pbuf_alloc faild\n"); + LOG_D(" pbuf_alloc faild"); } } else if (status == kStatus_ENET_RxFrameError) { - dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); + LOG_W("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError"); /* Update the received buffer when error happened. */ /* Get the error information of the received g_frame. */ ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); @@ -1072,20 +1072,20 @@ static void phy_monitor_thread_entry(void *parameter) if (kPHY_Speed10M == speed) { - dbg_log(DBG_LOG, "10M\n"); + LOG_D("10M"); } else { - dbg_log(DBG_LOG, "100M\n"); + LOG_D("100M"); } if (kPHY_HalfDuplex == duplex) { - dbg_log(DBG_LOG, "half dumplex\n"); + LOG_D("half dumplex"); } else { - dbg_log(DBG_LOG, "full dumplex\n"); + LOG_D("full dumplex"); } if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) @@ -1094,19 +1094,19 @@ static void phy_monitor_thread_entry(void *parameter) imxrt_eth_device.speed = (enet_mii_speed_t)speed; imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; - dbg_log(DBG_LOG, "link up, and update eth mode.\n"); + LOG_D("link up, and update eth mode."); rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); } else { - dbg_log(DBG_LOG, "link up, eth not need re-config.\n"); + LOG_D("link up, eth not need re-config."); } - dbg_log(DBG_LOG, "link up.\n"); + LOG_D("link up."); eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE); } else // link down { - dbg_log(DBG_LOG, "link down.\n"); + LOG_D("link down."); eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); } } @@ -1156,20 +1156,20 @@ static int rt_hw_imxrt_eth_init(void) imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx; imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx; - dbg_log(DBG_LOG, "sem init: tx_wait\r\n"); + LOG_D("sem init: tx_wait\r"); /* init tx semaphore */ rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); /* register eth device */ - dbg_log(DBG_LOG, "eth_device_init start\r\n"); + LOG_D("eth_device_init start\r"); state = eth_device_init(&(imxrt_eth_device.parent), "e0"); if (RT_EOK == state) { - dbg_log(DBG_LOG, "eth_device_init success\r\n"); + LOG_D("eth_device_init success\r"); } else { - dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state); + LOG_D("eth_device_init faild: %d\r", state); } eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); diff --git a/bsp/imxrt1052-evk/drivers/drv_eth_fire.c b/bsp/imxrt1052-evk/drivers/drv_eth_fire.c index 673f0061b8..7e337b9d66 100644 --- a/bsp/imxrt1052-evk/drivers/drv_eth_fire.c +++ b/bsp/imxrt1052-evk/drivers/drv_eth_fire.c @@ -380,13 +380,13 @@ static void _enet_config(void) /* Set SMI to get PHY link status. */ sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); - dbg_log(DBG_LOG, "deinit\n"); + LOG_D("deinit"); ENET_Deinit(imxrt_eth_device.enet_base); - dbg_log(DBG_LOG, "init\n"); + LOG_D("init"); ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); - dbg_log(DBG_LOG, "set call back\n"); + LOG_D("set call back"); ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); - dbg_log(DBG_LOG, "active read\n"); + LOG_D("active read"); ENET_ActiveRead(imxrt_eth_device.enet_base); } @@ -430,7 +430,7 @@ static void packet_dump(const char *msg, const struct pbuf *p) /* initialize the interface */ static rt_err_t rt_imxrt_eth_init(rt_device_t dev) { - dbg_log(DBG_LOG, "rt_imxrt_eth_init...\n"); + LOG_D("rt_imxrt_eth_init..."); _enet_config(); return RT_EOK; @@ -438,33 +438,33 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev) static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) { - dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n"); + LOG_D("rt_imxrt_eth_open..."); return RT_EOK; } static rt_err_t rt_imxrt_eth_close(rt_device_t dev) { - dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n"); + LOG_D("rt_imxrt_eth_close..."); return RT_EOK; } static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) { - dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n"); + LOG_D("rt_imxrt_eth_read..."); rt_set_errno(-RT_ENOSYS); return 0; } static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n"); + LOG_D("rt_imxrt_eth_write..."); rt_set_errno(-RT_ENOSYS); return 0; } static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) { - dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n"); + LOG_D("rt_imxrt_eth_control..."); switch (cmd) { case NIOCTL_GADDR: @@ -672,7 +672,7 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) RT_ASSERT(p != NULL); RT_ASSERT(enet_handle != RT_NULL); - dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len); + LOG_D("rt_imxrt_eth_tx: %d", p->len); #ifdef ETH_TX_DUMP packet_dump("send", p); @@ -726,18 +726,18 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) } else { - dbg_log(DBG_LOG, " A frame read failed\n"); + LOG_D(" A frame read failed"); pbuf_free(p); } } else { - dbg_log(DBG_LOG, " pbuf_alloc faild\n"); + LOG_D(" pbuf_alloc faild"); } } else if (status == kStatus_ENET_RxFrameError) { - dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); + LOG_W("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError"); /* Update the received buffer when error happened. */ /* Get the error information of the received g_frame. */ ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); @@ -775,20 +775,20 @@ static void phy_monitor_thread_entry(void *parameter) if (kPHY_Speed10M == speed) { - dbg_log(DBG_LOG, "10M\n"); + LOG_D("10M"); } else { - dbg_log(DBG_LOG, "100M\n"); + LOG_D("100M"); } if (kPHY_HalfDuplex == duplex) { - dbg_log(DBG_LOG, "half dumplex\n"); + LOG_D("half dumplex"); } else { - dbg_log(DBG_LOG, "full dumplex\n"); + LOG_D("full dumplex"); } if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) @@ -797,19 +797,19 @@ static void phy_monitor_thread_entry(void *parameter) imxrt_eth_device.speed = (enet_mii_speed_t)speed; imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; - dbg_log(DBG_LOG, "link up, and update eth mode.\n"); + LOG_D("link up, and update eth mode."); rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); } else { - dbg_log(DBG_LOG, "link up, eth not need re-config.\n"); + LOG_D("link up, eth not need re-config."); } - dbg_log(DBG_LOG, "link up.\n"); + LOG_D("link up."); eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE); } else // link down { - dbg_log(DBG_LOG, "link down.\n"); + LOG_D("link down."); eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); } } @@ -850,20 +850,20 @@ static int rt_hw_imxrt_eth_init(void) imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx; imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx; - dbg_log(DBG_LOG, "sem init: tx_wait\r\n"); + LOG_D("sem init: tx_wait\r"); /* init tx semaphore */ rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); /* register eth device */ - dbg_log(DBG_LOG, "eth_device_init start\r\n"); + LOG_D("eth_device_init start\r"); state = eth_device_init(&(imxrt_eth_device.parent), "e0"); if (RT_EOK == state) { - dbg_log(DBG_LOG, "eth_device_init success\r\n"); + LOG_D("eth_device_init success\r"); } else { - dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state); + LOG_D("eth_device_init faild: %d\r", state); } eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); diff --git a/bsp/imxrt1052-evk/drivers/drv_pin.c b/bsp/imxrt1052-evk/drivers/drv_pin.c index 2a9af1ea64..e834c1265f 100644 --- a/bsp/imxrt1052-evk/drivers/drv_pin.c +++ b/bsp/imxrt1052-evk/drivers/drv_pin.c @@ -362,7 +362,7 @@ void GPIO5_Combined_0_15_IRQHandler(void) static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin) { - IRQn_Type irq_num; + IRQn_Type irq_num = -100; /* Invalid interrupt number */ if(gpio == GPIO1) { diff --git a/bsp/lpc176x/applications/application.c b/bsp/lpc176x/applications/application.c index acc6b300ea..9facb30aa8 100644 --- a/bsp/lpc176x/applications/application.c +++ b/bsp/lpc176x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc176x/applications/platform.c b/bsp/lpc176x/applications/platform.c index 05e3b0d5e0..4bab858aa4 100644 --- a/bsp/lpc176x/applications/platform.c +++ b/bsp/lpc176x/applications/platform.c @@ -1,11 +1,7 @@ /* - * File : platform.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc176x/applications/platform.h b/bsp/lpc176x/applications/platform.h index 6b5ebf3f88..e52e4066c2 100644 --- a/bsp/lpc176x/applications/platform.h +++ b/bsp/lpc176x/applications/platform.h @@ -1,11 +1,7 @@ /* - * File : platform.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc176x/applications/startup.c b/bsp/lpc176x/applications/startup.c index abc08f1852..63d5b0f9a5 100644 --- a/bsp/lpc176x/applications/startup.c +++ b/bsp/lpc176x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc176x/drivers/board.c b/bsp/lpc176x/drivers/board.c index a66194b64c..c636462a2e 100644 --- a/bsp/lpc176x/drivers/board.c +++ b/bsp/lpc176x/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc176x/drivers/board.h b/bsp/lpc176x/drivers/board.h index 389e36e6c3..951a2c4cda 100644 --- a/bsp/lpc176x/drivers/board.h +++ b/bsp/lpc176x/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc176x/drivers/emac.c b/bsp/lpc176x/drivers/emac.c index fd2df23ec0..27fc55397a 100644 --- a/bsp/lpc176x/drivers/emac.c +++ b/bsp/lpc176x/drivers/emac.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "emac.h" #include "lwipopts.h" diff --git a/bsp/lpc176x/drivers/led.h b/bsp/lpc176x/drivers/led.h index 928c91e6e8..658ed16d1c 100644 --- a/bsp/lpc176x/drivers/led.h +++ b/bsp/lpc176x/drivers/led.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __LED_H__ #define __LED_H__ diff --git a/bsp/lpc176x/drivers/sd.c b/bsp/lpc176x/drivers/sd.c index 6c6c4ef4b6..27f3707da9 100644 --- a/bsp/lpc176x/drivers/sd.c +++ b/bsp/lpc176x/drivers/sd.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/bsp/lpc176x/drivers/uart.c b/bsp/lpc176x/drivers/uart.c index 29f11ebecd..231eccb10a 100644 --- a/bsp/lpc176x/drivers/uart.c +++ b/bsp/lpc176x/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc178x/applications/application.c b/bsp/lpc178x/applications/application.c index 29352f857b..9780d42154 100644 --- a/bsp/lpc178x/applications/application.c +++ b/bsp/lpc178x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc178x/applications/startup.c b/bsp/lpc178x/applications/startup.c index 4da4991523..07698574b5 100644 --- a/bsp/lpc178x/applications/startup.c +++ b/bsp/lpc178x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c index 42cc85912a..df06d7f2f8 100644 --- a/bsp/lpc178x/drivers/board.c +++ b/bsp/lpc178x/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h index 1cd02ccfb0..1a6d82e4b7 100644 --- a/bsp/lpc178x/drivers/board.h +++ b/bsp/lpc178x/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc178x/drivers/emac.c b/bsp/lpc178x/drivers/emac.c index 283b00243c..a16dc49770 100644 --- a/bsp/lpc178x/drivers/emac.c +++ b/bsp/lpc178x/drivers/emac.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "LPC177x_8x.h" #include "lpc177x_8x_pinsel.h" #include "emac.h" diff --git a/bsp/lpc178x/drivers/lpc17xx_lcd.c b/bsp/lpc178x/drivers/lpc17xx_lcd.c index 09208e893e..cc488dfebb 100644 --- a/bsp/lpc178x/drivers/lpc17xx_lcd.c +++ b/bsp/lpc178x/drivers/lpc17xx_lcd.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "LPC177x_8x.h" diff --git a/bsp/lpc178x/drivers/sdram.c b/bsp/lpc178x/drivers/sdram.c index 59a04e53df..c2fcbcc9ab 100644 --- a/bsp/lpc178x/drivers/sdram.c +++ b/bsp/lpc178x/drivers/sdram.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c index cfc97f4430..0d92eb1fca 100644 --- a/bsp/lpc178x/drivers/uart.c +++ b/bsp/lpc178x/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2148/applications/application.c b/bsp/lpc2148/applications/application.c index 5ceb371837..fd07f22f05 100644 --- a/bsp/lpc2148/applications/application.c +++ b/bsp/lpc2148/applications/application.c @@ -1,11 +1,7 @@ /* - * File : app.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2148/applications/startup.c b/bsp/lpc2148/applications/startup.c index 4a2db19c95..5b699a8613 100644 --- a/bsp/lpc2148/applications/startup.c +++ b/bsp/lpc2148/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2148/drivers/board.c b/bsp/lpc2148/drivers/board.c index 10f25e079a..96a4aa62f4 100644 --- a/bsp/lpc2148/drivers/board.c +++ b/bsp/lpc2148/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2148/drivers/board.h b/bsp/lpc2148/drivers/board.h index 7c2dcee6da..346f10182f 100644 --- a/bsp/lpc2148/drivers/board.h +++ b/bsp/lpc2148/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2148/drivers/dm9000.c b/bsp/lpc2148/drivers/dm9000.c index 478de46df3..169be59f12 100644 --- a/bsp/lpc2148/drivers/dm9000.c +++ b/bsp/lpc2148/drivers/dm9000.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "dm9000.h" diff --git a/bsp/lpc2148/drivers/sd.c b/bsp/lpc2148/drivers/sd.c index 95be32631b..d7b6769621 100644 --- a/bsp/lpc2148/drivers/sd.c +++ b/bsp/lpc2148/drivers/sd.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include #include diff --git a/bsp/lpc2148/drivers/serial.c b/bsp/lpc2148/drivers/serial.c index 5ad31af34a..0c78ecc026 100644 --- a/bsp/lpc2148/drivers/serial.c +++ b/bsp/lpc2148/drivers/serial.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2478/applications/application.c b/bsp/lpc2478/applications/application.c index ea8d1d68a1..64dbf3c807 100644 --- a/bsp/lpc2478/applications/application.c +++ b/bsp/lpc2478/applications/application.c @@ -1,11 +1,7 @@ /* - * File : app.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2478/applications/startup.c b/bsp/lpc2478/applications/startup.c index c262e57149..270312f7ae 100644 --- a/bsp/lpc2478/applications/startup.c +++ b/bsp/lpc2478/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2478/drivers/board.c b/bsp/lpc2478/drivers/board.c index ac17305062..65ff918711 100644 --- a/bsp/lpc2478/drivers/board.c +++ b/bsp/lpc2478/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2478/drivers/board.h b/bsp/lpc2478/drivers/board.h index 6271d45140..6386c19ba8 100644 --- a/bsp/lpc2478/drivers/board.h +++ b/bsp/lpc2478/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc2478/drivers/serial.c b/bsp/lpc2478/drivers/serial.c index 37c0d0c2ce..dff575c7cc 100644 --- a/bsp/lpc2478/drivers/serial.c +++ b/bsp/lpc2478/drivers/serial.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/applications/application.c b/bsp/lpc408x/applications/application.c index d8045587a6..29f7c36bba 100644 --- a/bsp/lpc408x/applications/application.c +++ b/bsp/lpc408x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/applications/board.c b/bsp/lpc408x/applications/board.c index a2bb22bfe4..2deb02d930 100644 --- a/bsp/lpc408x/applications/board.c +++ b/bsp/lpc408x/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/applications/board.h b/bsp/lpc408x/applications/board.h index 392dcf2031..654a5bea9e 100644 --- a/bsp/lpc408x/applications/board.h +++ b/bsp/lpc408x/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/applications/canapp.c b/bsp/lpc408x/applications/canapp.c index 59250380f8..96a0ceeb39 100644 --- a/bsp/lpc408x/applications/canapp.c +++ b/bsp/lpc408x/applications/canapp.c @@ -1,11 +1,7 @@ /* - * File : canapp.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/applications/sram.c b/bsp/lpc408x/applications/sram.c index e7ac0fe158..633d3eb6d4 100644 --- a/bsp/lpc408x/applications/sram.c +++ b/bsp/lpc408x/applications/sram.c @@ -1,12 +1,8 @@ /* -* File : sram.c -* This file is part of RT-Thread RTOS -* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rt-thread.org/license/LICENSE -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-05-19 Bernard The first version for LPC40xx diff --git a/bsp/lpc408x/applications/sram.h b/bsp/lpc408x/applications/sram.h index 902337aafc..3aee2aab0b 100644 --- a/bsp/lpc408x/applications/sram.h +++ b/bsp/lpc408x/applications/sram.h @@ -1,11 +1,7 @@ /* - * File : sram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/applications/startup.c b/bsp/lpc408x/applications/startup.c index bcab985a62..cb99fc16ff 100644 --- a/bsp/lpc408x/applications/startup.c +++ b/bsp/lpc408x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_emac.c b/bsp/lpc408x/drivers/drv_emac.c index 9f1e9920cb..7e38830f2c 100644 --- a/bsp/lpc408x/drivers/drv_emac.c +++ b/bsp/lpc408x/drivers/drv_emac.c @@ -1,11 +1,7 @@ /* - * File : drv_emac.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_emac.h b/bsp/lpc408x/drivers/drv_emac.h index abadc18520..efaa0ac8e3 100644 --- a/bsp/lpc408x/drivers/drv_emac.h +++ b/bsp/lpc408x/drivers/drv_emac.h @@ -1,11 +1,7 @@ /* - * File : drv_emac.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_hwtimer.c b/bsp/lpc408x/drivers/drv_hwtimer.c index 163c91fcd1..7946a7058a 100644 --- a/bsp/lpc408x/drivers/drv_hwtimer.c +++ b/bsp/lpc408x/drivers/drv_hwtimer.c @@ -1,11 +1,7 @@ /* - * File : drv_hwtimer.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_led.c b/bsp/lpc408x/drivers/drv_led.c index 2103e934fb..dcbe76a7b8 100644 --- a/bsp/lpc408x/drivers/drv_led.c +++ b/bsp/lpc408x/drivers/drv_led.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "board.h" diff --git a/bsp/lpc408x/drivers/drv_lpccan.c b/bsp/lpc408x/drivers/drv_lpccan.c index 037a4cf2ae..85d6511284 100644 --- a/bsp/lpc408x/drivers/drv_lpccan.c +++ b/bsp/lpc408x/drivers/drv_lpccan.c @@ -1,11 +1,7 @@ /* - * File : drv_lpccan.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_lpccan.h b/bsp/lpc408x/drivers/drv_lpccan.h index 1d81912dc9..9dda61a1f6 100644 --- a/bsp/lpc408x/drivers/drv_lpccan.h +++ b/bsp/lpc408x/drivers/drv_lpccan.h @@ -1,11 +1,7 @@ /* - * File : drv_lpccan.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_sdram.c b/bsp/lpc408x/drivers/drv_sdram.c index b648ed079c..515659f244 100644 --- a/bsp/lpc408x/drivers/drv_sdram.c +++ b/bsp/lpc408x/drivers/drv_sdram.c @@ -1,11 +1,7 @@ /* - * File : drv_sdram.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_sdram.h b/bsp/lpc408x/drivers/drv_sdram.h index a689f1ed98..21c0791f32 100644 --- a/bsp/lpc408x/drivers/drv_sdram.h +++ b/bsp/lpc408x/drivers/drv_sdram.h @@ -1,11 +1,7 @@ /* - * File : drv_sdram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_uart.c b/bsp/lpc408x/drivers/drv_uart.c index ef50f3a4d8..8360ca17c6 100644 --- a/bsp/lpc408x/drivers/drv_uart.c +++ b/bsp/lpc408x/drivers/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/drivers/drv_uart.h b/bsp/lpc408x/drivers/drv_uart.h index d93995b96e..aee8a379ed 100644 --- a/bsp/lpc408x/drivers/drv_uart.h +++ b/bsp/lpc408x/drivers/drv_uart.h @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc408x/project.uvprojx b/bsp/lpc408x/project.uvprojx index 14f721caf2..c9a4fc4fbf 100644 --- a/bsp/lpc408x/project.uvprojx +++ b/bsp/lpc408x/project.uvprojx @@ -7,21 +7,22 @@ - RT-Thread LPC408x + RT-Thread LPC408X 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC - LPC4088FBD208 - NXP - Keil.LPC4000_DFP.1.1.0 + ARMCM4 + ARM + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ - IROM(0x00000000,0x80000) IRAM(0x10000000,0x10000) IRAM2(0x20000000,0x8000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE - UL2CM3(-S0 -C0 -P0 -FD10000000 -FCFE0 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000 -FP0($$Device:LPC4088FBD208$Flash\LPC_IAP_512.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) 0 - $$Device:LPC4088FBD208$Device\Include\LPC407x_8x_177x_8x.h + $$Device:ARMCM4$Device\ARM\ARMCM4\Include\ARMCM4.h @@ -31,7 +32,7 @@ - $$Device:LPC4088FBD208$SVD\LPC408x_7x.svd + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd 0 0 @@ -47,12 +48,12 @@ 1 .\build\ - rtthread-lpc + rtthread 1 0 0 1 - 1 + 0 .\build\ 1 0 @@ -78,9 +79,9 @@ 0 - 0 + 1 0 - + fromelf --bin !L --output rtthread-mdk.bin 0 0 @@ -124,47 +125,6 @@ 0 16 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - @@ -173,10 +133,10 @@ 0 1 1 - 4099 + 4096 1 - Segger\JL2CM3.dll + BIN\UL2CM3.DLL "" () @@ -222,13 +182,14 @@ 1 0 0 - 2 - 1 + 0 + 0 0 8 0 - 0 + 1 0 + 0 3 3 0 @@ -281,13 +242,13 @@ 0 - 0x10000000 - 0x10000 + 0x20000000 + 0x20000 1 0x0 - 0x80000 + 0x40000 0 @@ -341,18 +302,18 @@ 0 - 0x20000000 - 0x8000 + 0x0 + 0x0 1 - 1 + 3 0 0 - 0 + 1 0 0 0 @@ -361,15 +322,20 @@ 0 0 0 - 0 + 1 0 - 0 - 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 - + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 CORE_M4, RT_USING_ARM_LIBC - Libraries/Device/NXP/LPC407x_8x_177x_8x/Include;Libraries/CMSIS/Include;Libraries/Drivers/include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;..\..\components\libc\pthreads;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/finsh + applications;.;drivers;Libraries\Device\NXP\LPC407x_8x_177x_8x\Include;Libraries\CMSIS\Include;Libraries\Drivers\include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\pthreads;..\..\components\libc\time @@ -382,6 +348,7 @@ 0 0 0 + 0 @@ -390,7 +357,7 @@ - 1 + 0 0 0 0 @@ -399,193 +366,43 @@ 0x00000000 0x10000000 - + .\rtthread-lpc408x.sct - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + --keep *.o(FSymTab) --keep *.o(VSymTab) - - CMSIS - - - system_LPC407x_8x_177x_8x.c - 1 - Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c - - - startup_LPC407x_8x_177x_8x.s - 2 - Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s - - - - - Libraries - - - lpc_adc.c - 1 - Libraries/Drivers/source/lpc_adc.c - - - lpc_bod.c - 1 - Libraries/Drivers/source/lpc_bod.c - - - lpc_can.c - 1 - Libraries/Drivers/source/lpc_can.c - - - lpc_clkpwr.c - 1 - Libraries/Drivers/source/lpc_clkpwr.c - - - lpc_crc.c - 1 - Libraries/Drivers/source/lpc_crc.c - - - lpc_dac.c - 1 - Libraries/Drivers/source/lpc_dac.c - - - lpc_eeprom.c - 1 - Libraries/Drivers/source/lpc_eeprom.c - - - lpc_emc.c - 1 - Libraries/Drivers/source/lpc_emc.c - - - lpc_exti.c - 1 - Libraries/Drivers/source/lpc_exti.c - - - lpc_gpdma.c - 1 - Libraries/Drivers/source/lpc_gpdma.c - - - lpc_gpio.c - 1 - Libraries/Drivers/source/lpc_gpio.c - - - lpc_i2c.c - 1 - Libraries/Drivers/source/lpc_i2c.c - - - lpc_i2s.c - 1 - Libraries/Drivers/source/lpc_i2s.c - - - lpc_iap.c - 1 - Libraries/Drivers/source/lpc_iap.c - - - lpc_lcd.c - 1 - Libraries/Drivers/source/lpc_lcd.c - - - lpc_mcpwm.c - 1 - Libraries/Drivers/source/lpc_mcpwm.c - - - lpc_nvic.c - 1 - Libraries/Drivers/source/lpc_nvic.c - - - lpc_pinsel.c - 1 - Libraries/Drivers/source/lpc_pinsel.c - - - lpc_pwm.c - 1 - Libraries/Drivers/source/lpc_pwm.c - - - lpc_qei.c - 1 - Libraries/Drivers/source/lpc_qei.c - - - lpc_rtc.c - 1 - Libraries/Drivers/source/lpc_rtc.c - - - lpc_ssp.c - 1 - Libraries/Drivers/source/lpc_ssp.c - - - lpc_systick.c - 1 - Libraries/Drivers/source/lpc_systick.c - - - lpc_timer.c - 1 - Libraries/Drivers/source/lpc_timer.c - - - lpc_uart.c - 1 - Libraries/Drivers/source/lpc_uart.c - - - lpc_wwdt.c - 1 - Libraries/Drivers/source/lpc_wwdt.c - - - Applications application.c 1 - applications/application.c + applications\application.c board.c 1 - applications/board.c - - - sram.c - 1 - applications/sram.c - - - startup.c - 1 - applications/startup.c + applications\board.c canapp.c 1 - .\applications\canapp.c + applications\canapp.c + + + sram.c + 1 + applications\sram.c + + + startup.c + 1 + applications\startup.c @@ -593,24 +410,174 @@ Drivers - drv_led.c + drv_hwtimer.c 1 - drivers/drv_led.c + drivers\drv_hwtimer.c - drv_uart.c + drv_led.c 1 - drivers/drv_uart.c + drivers\drv_led.c drv_lpccan.c 1 - .\drivers\drv_lpccan.c + drivers\drv_lpccan.c drv_sdram.c 1 - .\drivers\drv_sdram.c + drivers\drv_sdram.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + system_LPC407x_8x_177x_8x.c + 1 + Libraries\Device\NXP\LPC407x_8x_177x_8x\Source\Templates\system_LPC407x_8x_177x_8x.c + + + startup_LPC407x_8x_177x_8x.s + 2 + Libraries\Device\NXP\LPC407x_8x_177x_8x\Source\Templates\ARM\startup_LPC407x_8x_177x_8x.s + + + lpc_adc.c + 1 + Libraries\Drivers\source\lpc_adc.c + + + lpc_bod.c + 1 + Libraries\Drivers\source\lpc_bod.c + + + lpc_can.c + 1 + Libraries\Drivers\source\lpc_can.c + + + lpc_clkpwr.c + 1 + Libraries\Drivers\source\lpc_clkpwr.c + + + lpc_crc.c + 1 + Libraries\Drivers\source\lpc_crc.c + + + lpc_dac.c + 1 + Libraries\Drivers\source\lpc_dac.c + + + lpc_eeprom.c + 1 + Libraries\Drivers\source\lpc_eeprom.c + + + lpc_emc.c + 1 + Libraries\Drivers\source\lpc_emc.c + + + lpc_exti.c + 1 + Libraries\Drivers\source\lpc_exti.c + + + lpc_gpdma.c + 1 + Libraries\Drivers\source\lpc_gpdma.c + + + lpc_gpio.c + 1 + Libraries\Drivers\source\lpc_gpio.c + + + lpc_i2c.c + 1 + Libraries\Drivers\source\lpc_i2c.c + + + lpc_i2s.c + 1 + Libraries\Drivers\source\lpc_i2s.c + + + lpc_iap.c + 1 + Libraries\Drivers\source\lpc_iap.c + + + lpc_lcd.c + 1 + Libraries\Drivers\source\lpc_lcd.c + + + lpc_mcpwm.c + 1 + Libraries\Drivers\source\lpc_mcpwm.c + + + lpc_nvic.c + 1 + Libraries\Drivers\source\lpc_nvic.c + + + lpc_pinsel.c + 1 + Libraries\Drivers\source\lpc_pinsel.c + + + lpc_pwm.c + 1 + Libraries\Drivers\source\lpc_pwm.c + + + lpc_qei.c + 1 + Libraries\Drivers\source\lpc_qei.c + + + lpc_rtc.c + 1 + Libraries\Drivers\source\lpc_rtc.c + + + lpc_ssp.c + 1 + Libraries\Drivers\source\lpc_ssp.c + + + lpc_systick.c + 1 + Libraries\Drivers\source\lpc_systick.c + + + lpc_timer.c + 1 + Libraries\Drivers\source\lpc_timer.c + + + lpc_uart.c + 1 + Libraries\Drivers\source\lpc_uart.c + + + lpc_wwdt.c + 1 + Libraries\Drivers\source\lpc_wwdt.c @@ -620,72 +587,72 @@ clock.c 1 - ../../src/clock.c - - - components.c - 1 - ../../src/components.c + ..\..\src\clock.c device.c 1 - ../../src/device.c + ..\..\src\device.c idle.c 1 - ../../src/idle.c + ..\..\src\idle.c ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c irq.c 1 - ../../src/irq.c + ..\..\src\irq.c kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c mem.c 1 - ../../src/mem.c + ..\..\src\mem.c memheap.c 1 - ../../src/memheap.c + ..\..\src\memheap.c mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c object.c 1 - ../../src/object.c + ..\..\src\object.c scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c + + + signal.c + 1 + ..\..\src\signal.c thread.c 1 - ../../src/thread.c + ..\..\src\thread.c timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -695,38 +662,248 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m4/cpuport.c + ..\..\libcpu\arm\cortex-m4\cpuport.c context_rvds.S 2 - ../../libcpu/arm/cortex-m4/context_rvds.S + ..\..\libcpu\arm\cortex-m4\context_rvds.S backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c showmem.c 1 - ../../libcpu/arm/common/showmem.c + ..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + dfs_elm.c + 1 + ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + ff.c + 1 + ..\..\components\dfs\filesystems\elmfat\ff.c + + + + + DeviceDrivers + + + can.c + 1 + ..\..\components\drivers\can\can.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c pthreads - - clock_time.c - 1 - ..\..\components\libc\pthreads\clock_time.c - mqueue.c 1 @@ -782,151 +959,18 @@ 1 ..\..\components\libc\pthreads\semaphore.c - - - - libc - - mem_std.c + clock_time.c 1 - ../../components/libc/armlibc/mem_std.c + ..\..\components\libc\time\clock_time.c - stubs.c + posix_sleep.c 1 - ../../components/libc/armlibc/stubs.c + ..\..\components\libc\time\posix_sleep.c - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - portal.c - 1 - ../../components/drivers/src/portal.c - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - can.c - 1 - ..\..\components\drivers\can\can.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - msh_cmd.c - 1 - ..\..\components\finsh\msh_cmd.c - - - - - ::CMSIS - @@ -934,10 +978,10 @@ - - + + - + diff --git a/bsp/lpc408x/template.uvprojx b/bsp/lpc408x/template.uvprojx new file mode 100644 index 0000000000..b985d37e18 --- /dev/null +++ b/bsp/lpc408x/template.uvprojx @@ -0,0 +1,394 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread LPC408X + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + + + ARMCM4 + ARM + ARM.CMSIS.5.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4$Device\ARM\ARMCM4\Include\ARMCM4.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread-mdk.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\rtthread-lpc408x.sct + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/lpc43xx/M0/applications/application.c b/bsp/lpc43xx/M0/applications/application.c index 8e861873c8..397f934777 100644 --- a/bsp/lpc43xx/M0/applications/application.c +++ b/bsp/lpc43xx/M0/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/board.c b/bsp/lpc43xx/M0/applications/board.c index 000bd52f40..cd1cf62df0 100644 --- a/bsp/lpc43xx/M0/applications/board.c +++ b/bsp/lpc43xx/M0/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/board.h b/bsp/lpc43xx/M0/applications/board.h index ee300eb739..24dfee67d4 100644 --- a/bsp/lpc43xx/M0/applications/board.h +++ b/bsp/lpc43xx/M0/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/startup.c b/bsp/lpc43xx/M0/applications/startup.c index f6cf534b03..df9cb7a211 100644 --- a/bsp/lpc43xx/M0/applications/startup.c +++ b/bsp/lpc43xx/M0/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/vbus_drv.c b/bsp/lpc43xx/M0/applications/vbus_drv.c index 24d7f19b58..88d5321b30 100644 --- a/bsp/lpc43xx/M0/applications/vbus_drv.c +++ b/bsp/lpc43xx/M0/applications/vbus_drv.c @@ -1,27 +1,7 @@ /* - * VMM Bus Driver - * - * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd - * http://www.rt-thread.com - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-01-07 Grissiom add comment diff --git a/bsp/lpc43xx/M0/applications/vbus_hw.h b/bsp/lpc43xx/M0/applications/vbus_hw.h index b88586a112..cceee706b4 100644 --- a/bsp/lpc43xx/M0/applications/vbus_hw.h +++ b/bsp/lpc43xx/M0/applications/vbus_hw.h @@ -1,26 +1,7 @@ /* - * VMM Bus - * - * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-01-07 Grissiom init commit diff --git a/bsp/lpc43xx/M4/applications/application.c b/bsp/lpc43xx/M4/applications/application.c index 6575991895..b08a158400 100644 --- a/bsp/lpc43xx/M4/applications/application.c +++ b/bsp/lpc43xx/M4/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/board.c b/bsp/lpc43xx/M4/applications/board.c index dc0859f666..c6bfa10574 100644 --- a/bsp/lpc43xx/M4/applications/board.c +++ b/bsp/lpc43xx/M4/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/board.h b/bsp/lpc43xx/M4/applications/board.h index 299404a368..0450724e53 100644 --- a/bsp/lpc43xx/M4/applications/board.h +++ b/bsp/lpc43xx/M4/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/startup.c b/bsp/lpc43xx/M4/applications/startup.c index f6cf534b03..df9cb7a211 100644 --- a/bsp/lpc43xx/M4/applications/startup.c +++ b/bsp/lpc43xx/M4/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/vbus_drv.c b/bsp/lpc43xx/M4/applications/vbus_drv.c index 872de86504..bd3ae03adb 100644 --- a/bsp/lpc43xx/M4/applications/vbus_drv.c +++ b/bsp/lpc43xx/M4/applications/vbus_drv.c @@ -1,27 +1,7 @@ /* - * VMM Bus Driver - * - * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd - * http://www.rt-thread.com - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-01-07 Grissiom add comment diff --git a/bsp/lpc43xx/M4/applications/vbus_hw.h b/bsp/lpc43xx/M4/applications/vbus_hw.h index b88586a112..cceee706b4 100644 --- a/bsp/lpc43xx/M4/applications/vbus_hw.h +++ b/bsp/lpc43xx/M4/applications/vbus_hw.h @@ -1,26 +1,7 @@ /* - * VMM Bus - * - * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes * 2015-01-07 Grissiom init commit diff --git a/bsp/lpc43xx/drivers/drv_emac.c b/bsp/lpc43xx/drivers/drv_emac.c index a339bdb361..d1f02af768 100644 --- a/bsp/lpc43xx/drivers/drv_emac.c +++ b/bsp/lpc43xx/drivers/drv_emac.c @@ -1,11 +1,7 @@ /* - * File : drv_emac.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/drivers/drv_emac.h b/bsp/lpc43xx/drivers/drv_emac.h index abadc18520..efaa0ac8e3 100644 --- a/bsp/lpc43xx/drivers/drv_emac.h +++ b/bsp/lpc43xx/drivers/drv_emac.h @@ -1,11 +1,7 @@ /* - * File : drv_emac.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/drivers/drv_led.c b/bsp/lpc43xx/drivers/drv_led.c index d67344e54e..73128c243c 100644 --- a/bsp/lpc43xx/drivers/drv_led.c +++ b/bsp/lpc43xx/drivers/drv_led.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "board.h" #include "drv_led.h" diff --git a/bsp/lpc43xx/drivers/drv_uart.c b/bsp/lpc43xx/drivers/drv_uart.c index 70f4a880e1..e1b203a359 100644 --- a/bsp/lpc43xx/drivers/drv_uart.c +++ b/bsp/lpc43xx/drivers/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc5410x/applications/application.c b/bsp/lpc5410x/applications/application.c index 627e97c860..bad0922693 100644 --- a/bsp/lpc5410x/applications/application.c +++ b/bsp/lpc5410x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc5410x/applications/board.c b/bsp/lpc5410x/applications/board.c index c47e02c0c1..0fb09e6574 100644 --- a/bsp/lpc5410x/applications/board.c +++ b/bsp/lpc5410x/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc5410x/applications/board.h b/bsp/lpc5410x/applications/board.h index 29c8514136..5bbf8bc235 100644 --- a/bsp/lpc5410x/applications/board.h +++ b/bsp/lpc5410x/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc5410x/applications/demo_thread.c b/bsp/lpc5410x/applications/demo_thread.c index f4bcea9773..6acb8ae0ef 100644 --- a/bsp/lpc5410x/applications/demo_thread.c +++ b/bsp/lpc5410x/applications/demo_thread.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "drv_led.h" #include "drv_uart.h" diff --git a/bsp/lpc5410x/applications/startup.c b/bsp/lpc5410x/applications/startup.c index 4008c3dcde..6589dc6b46 100644 --- a/bsp/lpc5410x/applications/startup.c +++ b/bsp/lpc5410x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc5410x/drivers/drv_led.c b/bsp/lpc5410x/drivers/drv_led.c index d2b778a7dd..8923e3fda4 100644 --- a/bsp/lpc5410x/drivers/drv_led.c +++ b/bsp/lpc5410x/drivers/drv_led.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "board.h" diff --git a/bsp/lpc5410x/drivers/drv_uart.c b/bsp/lpc5410x/drivers/drv_uart.c index 59f4ef183f..d348921740 100644 --- a/bsp/lpc5410x/drivers/drv_uart.c +++ b/bsp/lpc5410x/drivers/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/applications/application.c b/bsp/lpc54608-LPCXpresso/applications/application.c index c282a290e9..b85de95df6 100644 --- a/bsp/lpc54608-LPCXpresso/applications/application.c +++ b/bsp/lpc54608-LPCXpresso/applications/application.c @@ -1,20 +1,7 @@ /* - * File : application.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/applications/mnt.c b/bsp/lpc54608-LPCXpresso/applications/mnt.c index 4f87859b59..dd1f862ea5 100644 --- a/bsp/lpc54608-LPCXpresso/applications/mnt.c +++ b/bsp/lpc54608-LPCXpresso/applications/mnt.c @@ -1,20 +1,7 @@ /* - * File : mnt.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/applications/startup.c b/bsp/lpc54608-LPCXpresso/applications/startup.c index 1015c5ae27..687cc0f864 100644 --- a/bsp/lpc54608-LPCXpresso/applications/startup.c +++ b/bsp/lpc54608-LPCXpresso/applications/startup.c @@ -1,20 +1,7 @@ /* - * File : startup.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.c b/bsp/lpc54608-LPCXpresso/drivers/board.c index d2cec9a4fa..51c72ec3f5 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/board.c +++ b/bsp/lpc54608-LPCXpresso/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.h b/bsp/lpc54608-LPCXpresso/drivers/board.h index d733e9e407..679f33682f 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/board.h +++ b/bsp/lpc54608-LPCXpresso/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c index e587948ca2..c6c5d114e4 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c @@ -1,20 +1,7 @@ /* - * File : application.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h index 5f38ae2eb6..ff34c225e7 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h @@ -1,20 +1,7 @@ /* - * File : application.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c index 1f38471fca..b432aea70e 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c @@ -1,20 +1,7 @@ /* - * File : drv_emac.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h index abadc18520..efaa0ac8e3 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h @@ -1,11 +1,7 @@ /* - * File : drv_emac.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c index 92ab3592bd..fd46a199c0 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c @@ -1,21 +1,7 @@ /* - * File : drv_ft5406.c - * FT5406 touch driver - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c index 27013feaf6..2d9a3c4d17 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c @@ -1,20 +1,7 @@ /* - * File : drv_i2c.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c index 4b6b805f6c..c1a6660819 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c @@ -1,20 +1,7 @@ /* - * File : drv_lcd.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c index 9400671301..e1239b7899 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c @@ -1,20 +1,7 @@ /* - * File : drv_sd.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h index 952d6a6048..d36134eaa4 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h @@ -1,12 +1,7 @@ /* - * File : drv_sd.h - * SPI mode SD Card Driver - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c index f01d815cc4..9b6438c4d2 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c @@ -1,20 +1,7 @@ /* - * File : drv_sdram.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h index 956498f929..4de79410b0 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h @@ -1,11 +1,7 @@ /* - * File : drv_sdram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c index fb3266b2c3..81f4ba6e9c 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c @@ -1,12 +1,8 @@ /* -* File : sram.c -* This file is part of RT-Thread RTOS -* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rt-thread.org/license/LICENSE -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-05-19 Bernard The first version for LPC40xx diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h index b5db6209db..14c87054ff 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h @@ -1,11 +1,7 @@ /* - * File : sram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c index d08d192617..7c9bd9fc7f 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc54608-LPCXpresso/project.ewp b/bsp/lpc54608-LPCXpresso/project.ewp index 5e297ee1ab..22154af07d 100644 --- a/bsp/lpc54608-LPCXpresso/project.ewp +++ b/bsp/lpc54608-LPCXpresso/project.ewp @@ -2111,9 +2111,6 @@ $PROJ_DIR$\../../src/mempool.c - - $PROJ_DIR$\../../src/module.c - $PROJ_DIR$\../../src/object.c diff --git a/bsp/lpc54608-LPCXpresso/project.uvoptx b/bsp/lpc54608-LPCXpresso/project.uvoptx index 568861960e..ea669a615e 100644 --- a/bsp/lpc54608-LPCXpresso/project.uvoptx +++ b/bsp/lpc54608-LPCXpresso/project.uvoptx @@ -1082,18 +1082,6 @@ 0 0 - - 5 - 73 - 1 - 0 - 0 - 0 - ../../src/module.c - module.c - 0 - 0 - 5 74 diff --git a/bsp/lpc54608-LPCXpresso/project.uvprojx b/bsp/lpc54608-LPCXpresso/project.uvprojx index d20f677e9e..f94c0c5065 100644 --- a/bsp/lpc54608-LPCXpresso/project.uvprojx +++ b/bsp/lpc54608-LPCXpresso/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rtthread-lpc546xx @@ -15,28 +18,28 @@ Keil.LPC54000_DFP.2.5.0 http://www.keil.com/pack/ IROM(0x00000000,0x00080000) IRAM(0x20000000,0x00028000) IRAM2(0x04000000,0x00008000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0LPC5460x_512 -FS00 -FL080000 -FP0($$Device:LPC54608J512ET180$Flash\LPC5460x_512.FLM)) 0 $$Device:LPC54608J512ET180$Device\Include\LPC54608.h - - - - - - - - - + + + + + + + + + $$Device:LPC54608J512ET180$SVD\LPC54608.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +61,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +71,8 @@ 0 0 - - + + 0 0 0 @@ -78,15 +81,15 @@ 0 0 - - + + 0 0 0 0 0 - + 0 @@ -100,8 +103,8 @@ 0 0 3 - - + + 1 @@ -135,10 +138,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -171,7 +174,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -303,7 +306,7 @@ 0x8000 - + 1 @@ -320,6 +323,7 @@ 0 0 1 + 0 0 0 0 @@ -331,8 +335,8 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 CPU_LPC54608J512ET180=1, CPU_LPC54608, CORE_M4, SDK_DEBUGCONSOLE=0, RT_USING_ARM_LIBC - - applications;.;drivers;SDK_2.2_LPCXpresso54608\CMSIS\Include;SDK_2.2_LPCXpresso54608\devices\LPC54608;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\cplusplus;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + + applications;.;drivers;SDK_2.2_LPCXpresso54608\CMSIS\Include;SDK_2.2_LPCXpresso54608\devices\LPC54608;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\cplusplus;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket @@ -347,10 +351,10 @@ 0 0 - - - - + + + + @@ -362,13 +366,13 @@ 0 0x00000000 0x02000000 - + .\LPC54608J512_flash.scf - - - --keep *.o(RTMSymTab) --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + @@ -381,15 +385,11 @@ 1 applications\application.c - - mnt.c 1 applications\mnt.c - - startup.c 1 @@ -405,78 +405,56 @@ 1 drivers\board.c - - clock_config.c 1 drivers\clock_config.c - - drt_mpu.c 1 drivers\drt_mpu.c - - drv_emac.c 1 drivers\drv_emac.c - - drv_ft5406.c 1 drivers\drv_ft5406.c - - drv_i2c.c 1 drivers\drv_i2c.c - - drv_lcd.c 1 drivers\drv_lcd.c - - drv_sd.c 1 drivers\drv_sd.c - - drv_sdram.c 1 drivers\drv_sdram.c - - drv_sram.c 1 drivers\drv_sram.c - - drv_uart.c 1 drivers\drv_uart.c - - fsl_phy.c 1 @@ -492,15 +470,11 @@ 2 SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\startup_LPC54608.s - - system_LPC54608.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\system_LPC54608.c - - keil_lib_power.lib 4 @@ -516,302 +490,216 @@ 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_adc.c - - fsl_clock.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_clock.c - - fsl_common.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_common.c - - fsl_crc.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_crc.c - - fsl_ctimer.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_ctimer.c - - fsl_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dma.c - - fsl_dmic.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic.c - - fsl_dmic_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic_dma.c - - fsl_eeprom.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_eeprom.c - - fsl_emc.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_emc.c - - fsl_enet.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_enet.c - - fsl_flashiap.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flashiap.c - - fsl_flexcomm.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flexcomm.c - - fsl_fmc.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmc.c - - fsl_fmeas.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmeas.c - - fsl_gint.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gint.c - - fsl_gpio.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gpio.c - - fsl_i2c.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c.c - - fsl_i2c_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c_dma.c - - fsl_i2s.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s.c - - fsl_i2s_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s_dma.c - - fsl_inputmux.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_inputmux.c - - fsl_lcdc.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_lcdc.c - - fsl_mcan.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mcan.c - - fsl_mrt.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mrt.c - - fsl_pint.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_pint.c - - fsl_power.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_power.c - - fsl_reset.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_reset.c - - fsl_rit.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rit.c - - fsl_rtc.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rtc.c - - fsl_sctimer.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sctimer.c - - fsl_sdif.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sdif.c - - fsl_spi.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi.c - - fsl_spi_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi_dma.c - - fsl_spifi.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi.c - - fsl_spifi_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi_dma.c - - fsl_usart.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart.c - - fsl_usart_dma.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart_dma.c - - fsl_utick.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_utick.c - - fsl_wwdt.c 1 SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_wwdt.c - - fsl_sd.c 1 SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd.c - - fsl_sdmmc.c 1 SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sdmmc.c - - fsl_host.c 1 SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_host.c - - fsl_sd_event.c 1 @@ -827,106 +715,71 @@ 1 ..\..\src\clock.c - - components.c 1 ..\..\src\components.c - - device.c 1 ..\..\src\device.c - - idle.c 1 ..\..\src\idle.c - - ipc.c 1 ..\..\src\ipc.c - - irq.c 1 ..\..\src\irq.c - - kservice.c 1 ..\..\src\kservice.c - - mem.c 1 ..\..\src\mem.c - - memheap.c 1 ..\..\src\memheap.c - - mempool.c 1 ..\..\src\mempool.c - - - - module.c - 1 - ..\..\src\module.c - - - object.c 1 ..\..\src\object.c - - scheduler.c 1 ..\..\src\scheduler.c - - signal.c 1 ..\..\src\signal.c - - thread.c 1 ..\..\src\thread.c - - timer.c 1 @@ -942,29 +795,21 @@ 1 ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\libcpu\arm\common\div0.c - - showmem.c 1 @@ -980,29 +825,21 @@ 8 ..\..\components\cplusplus\Mutex.cpp - - Semaphore.cpp 8 ..\..\components\cplusplus\Semaphore.cpp - - Thread.cpp 8 ..\..\components\cplusplus\Thread.cpp - - crt.cpp 8 ..\..\components\cplusplus\crt.cpp - - crt_init.c 1 @@ -1018,57 +855,41 @@ 1 ..\..\components\dfs\src\dfs.c - - dfs_file.c 1 ..\..\components\dfs\src\dfs_file.c - - dfs_fs.c 1 ..\..\components\dfs\src\dfs_fs.c - - dfs_posix.c 1 ..\..\components\dfs\src\dfs_posix.c - - poll.c 1 ..\..\components\dfs\src\poll.c - - select.c 1 ..\..\components\dfs\src\select.c - - devfs.c 1 ..\..\components\dfs\filesystems\devfs\devfs.c - - dfs_elm.c 1 ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - ff.c 1 @@ -1078,158 +899,177 @@ DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + i2c_core.c 1 ..\..\components\drivers\i2c\i2c_core.c - - i2c_dev.c 1 ..\..\components\drivers\i2c\i2c_dev.c - - i2c-bit-ops.c 1 ..\..\components\drivers\i2c\i2c-bit-ops.c - - pin.c 1 ..\..\components\drivers\misc\pin.c - - mtd_nand.c 1 ..\..\components\drivers\mtd\mtd_nand.c - - rtc.c 1 ..\..\components\drivers\rtc\rtc.c - - block_dev.c 1 ..\..\components\drivers\sdio\block_dev.c - - mmcsd_core.c 1 ..\..\components\drivers\sdio\mmcsd_core.c - - sd.c 1 ..\..\components\drivers\sdio\sd.c - - sdio.c 1 ..\..\components\drivers\sdio\sdio.c - - mmc.c 1 ..\..\components\drivers\sdio\mmc.c - - serial.c 1 ..\..\components\drivers\serial\serial.c - - spi_core.c 1 ..\..\components\drivers\spi\spi_core.c - - spi_dev.c 1 ..\..\components\drivers\spi\spi_dev.c - - completion.c 1 ..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\components\drivers\src\pipe.c - - ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 ..\..\components\drivers\src\workqueue.c - - - - - - - - - - - - finsh @@ -1239,106 +1079,76 @@ 1 ..\..\components\finsh\shell.c - - symbol.c 1 ..\..\components\finsh\symbol.c - - cmd.c 1 ..\..\components\finsh\cmd.c - - msh.c 1 ..\..\components\finsh\msh.c - - msh_cmd.c 1 ..\..\components\finsh\msh_cmd.c - - msh_file.c 1 ..\..\components\finsh\msh_file.c - - finsh_compiler.c 1 ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 @@ -1354,36 +1164,21 @@ 1 ..\..\components\libc\compilers\armlibc\libc.c - - - - libc_syms.c - 1 - ..\..\components\libc\compilers\armlibc\libc_syms.c - - - mem_std.c 1 ..\..\components\libc\compilers\armlibc\mem_std.c - - stdio.c 1 ..\..\components\libc\compilers\armlibc\stdio.c - - stubs.c 1 ..\..\components\libc\compilers\armlibc\stubs.c - - time.c 1 @@ -1399,85 +1194,61 @@ 1 ..\..\components\libc\pthreads\mqueue.c - - pthread.c 1 ..\..\components\libc\pthreads\pthread.c - - pthread_attr.c 1 ..\..\components\libc\pthreads\pthread_attr.c - - pthread_barrier.c 1 ..\..\components\libc\pthreads\pthread_barrier.c - - pthread_cond.c 1 ..\..\components\libc\pthreads\pthread_cond.c - - pthread_mutex.c 1 ..\..\components\libc\pthreads\pthread_mutex.c - - pthread_rwlock.c 1 ..\..\components\libc\pthreads\pthread_rwlock.c - - pthread_spin.c 1 ..\..\components\libc\pthreads\pthread_spin.c - - pthread_tls.c 1 ..\..\components\libc\pthreads\pthread_tls.c - - sched.c 1 ..\..\components\libc\pthreads\sched.c - - semaphore.c 1 ..\..\components\libc\pthreads\semaphore.c - - clock_time.c 1 ..\..\components\libc\time\clock_time.c - - posix_sleep.c 1 @@ -1493,246 +1264,176 @@ 1 ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - api_lib.c 1 ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - api_msg.c 1 ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - err.c 1 ..\..\components\net\lwip-2.0.2\src\api\err.c - - netbuf.c 1 ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - netdb.c 1 ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - netifapi.c 1 ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - sockets.c 1 ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - tcpip.c 1 ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - def.c 1 ..\..\components\net\lwip-2.0.2\src\core\def.c - - dns.c 1 ..\..\components\net\lwip-2.0.2\src\core\dns.c - - inet_chksum.c 1 ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - init.c 1 ..\..\components\net\lwip-2.0.2\src\core\init.c - - ip.c 1 ..\..\components\net\lwip-2.0.2\src\core\ip.c - - memp.c 1 ..\..\components\net\lwip-2.0.2\src\core\memp.c - - netif.c 1 ..\..\components\net\lwip-2.0.2\src\core\netif.c - - pbuf.c 1 ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - raw.c 1 ..\..\components\net\lwip-2.0.2\src\core\raw.c - - stats.c 1 ..\..\components\net\lwip-2.0.2\src\core\stats.c - - sys.c 1 ..\..\components\net\lwip-2.0.2\src\core\sys.c - - tcp.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - tcp_in.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - tcp_out.c 1 ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - timeouts.c 1 ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - udp.c 1 ..\..\components\net\lwip-2.0.2\src\core\udp.c - - ethernet.c 1 ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - ethernetif.c 1 ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - lowpan6.c 1 ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - autoip.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - dhcp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - etharp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - icmp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - igmp.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - ip4.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - ip4_addr.c 1 ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - ip4_frag.c 1 @@ -1748,36 +1449,26 @@ 1 ..\..\components\net\sal_socket\src\sal_ipaddr.c - - sal_socket.c 1 ..\..\components\net\sal_socket\src\sal_socket.c - - net_netdb.c 1 ..\..\components\net\sal_socket\socket\net_netdb.c - - - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - - - af_inet_lwip.c 1 ..\..\components\net\sal_socket\impl\af_inet_lwip.c - - + + net_sockets.c + 1 + ..\..\components\net\sal_socket\socket\net_sockets.c + dfs_net.c 1 @@ -1788,9 +1479,11 @@ + - - - + + + + diff --git a/bsp/lpc54608-LPCXpresso/rtconfig.h b/bsp/lpc54608-LPCXpresso/rtconfig.h index 540ba96030..7738810b58 100644 --- a/bsp/lpc54608-LPCXpresso/rtconfig.h +++ b/bsp/lpc54608-LPCXpresso/rtconfig.h @@ -41,7 +41,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_USING_MODULE +// #define RT_USING_MODULE #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 diff --git a/bsp/lpc824/applications/application.c b/bsp/lpc824/applications/application.c index 8d408d717b..f8ef7f40e3 100644 --- a/bsp/lpc824/applications/application.c +++ b/bsp/lpc824/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc824/applications/startup.c b/bsp/lpc824/applications/startup.c index 15c949df7e..5e95382ba0 100644 --- a/bsp/lpc824/applications/startup.c +++ b/bsp/lpc824/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc824/drivers/board.c b/bsp/lpc824/drivers/board.c index ea941abc64..51656718b8 100644 --- a/bsp/lpc824/drivers/board.c +++ b/bsp/lpc824/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc824/drivers/board.h b/bsp/lpc824/drivers/board.h index b89e518128..c8d21d94b5 100644 --- a/bsp/lpc824/drivers/board.h +++ b/bsp/lpc824/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc824/drivers/usart.c b/bsp/lpc824/drivers/usart.c index b36a2080d6..5109164a9a 100644 --- a/bsp/lpc824/drivers/usart.c +++ b/bsp/lpc824/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/lpc824/drivers/usart.h b/bsp/lpc824/drivers/usart.h index abd7631fee..1db28e9385 100644 --- a/bsp/lpc824/drivers/usart.h +++ b/bsp/lpc824/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1bdev/rtconfig.h b/bsp/ls1bdev/rtconfig.h index bb73a21f82..67bba7fc68 100644 --- a/bsp/ls1bdev/rtconfig.h +++ b/bsp/ls1bdev/rtconfig.h @@ -185,8 +185,6 @@ //
// #define RT_USING_MODULE -// -// #define RT_USING_LIBDL //
//
diff --git a/bsp/ls1cdev/.config b/bsp/ls1cdev/.config index 91f9c2f0c3..e51b00e78e 100644 --- a/bsp/ls1cdev/.config +++ b/bsp/ls1cdev/.config @@ -13,13 +13,22 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_DEBUG=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -CONFIG_RT_DEBUG_THREAD=0 CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -47,11 +56,11 @@ CONFIG_RT_USING_HEAP=y # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -# CONFIG_RT_USING_MODULE is not set # # RT-Thread Components @@ -59,6 +68,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -92,6 +102,7 @@ CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FILESYSTEMS_MAX=2 CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 CONFIG_DFS_FD_MAX=4 +# CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y # @@ -110,7 +121,6 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y # CONFIG_RT_USING_DFS_DEVFS is not set -# CONFIG_RT_USING_DFS_NET is not set # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set @@ -121,9 +131,10 @@ CONFIG_RT_DFS_ELM_REENTRANT=y # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_CAN=y -CONFIG_RT_CAN_USING_HDR=y +# CONFIG_RT_CAN_USING_HDR is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y @@ -132,6 +143,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y @@ -142,9 +155,13 @@ CONFIG_RT_USING_SPI_MSD=y # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_AUDIO is not set +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + # # Using USB # @@ -157,17 +174,24 @@ CONFIG_RT_USING_SPI_MSD=y CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_PTHREADS=y # CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set # -# Network stack +# Network # +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + # # light weight TCP/IP stack # CONFIG_RT_USING_LWIP=y CONFIG_RT_USING_LWIP141=y # CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP210 is not set CONFIG_RT_LWIP_IGMP=y CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -210,11 +234,18 @@ CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set # # Modbus master and slave stack # # CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set # CONFIG_LWIP_USING_DHCPD is not set # @@ -227,6 +258,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set # # RT-Thread online packages @@ -318,8 +350,8 @@ CONFIG_RT_USING_UART2=y CONFIG_RT_UART_RX_BUFFER_SIZE=64 CONFIG_RT_USING_GMAC_INT_MODE=y # CONFIG_RT_USING_FPU is not set -CONFIG_RT_USING_SPI0=y -CONFIG_RT_USING_SPI1=y +# CONFIG_RT_USING_SPI0 is not set +# CONFIG_RT_USING_SPI1 is not set CONFIG_RT_USING_I2C1=y CONFIG_RT_USING_I2C2=y CONFIG_USING_BXCAN0=y diff --git a/bsp/ls1cdev/drivers/net/synopGMAC.c b/bsp/ls1cdev/drivers/net/synopGMAC.c index 6aff98d22b..3ddc1af583 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC.c @@ -35,38 +35,38 @@ #define RMII -#define Gmac_base 0xbfe10000 +#define Gmac_base 0xbfe10000 #define Buffer_Size 2048 -#define MAX_ADDR_LEN 6 -#define NAMESIZE 16 +#define MAX_ADDR_LEN 6 +#define NAMESIZE 16 -#define LS1B_GMAC0_IRQ 34 +#define LS1B_GMAC0_IRQ 34 #define BUS_SIZE_ALIGN(x) ((x+15)&~15) #define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} -u32 regbase = 0xbfe10000; +u32 regbase = 0xbfe10000; static u32 GMAC_Power_down; extern void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) ; -extern s32 synopGMAC_check_phy_init (synopGMACPciNetworkAdapter *adapter) ; +extern s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter) ; extern int init_phy(synopGMACdevice *gmacdev); -dma_addr_t plat_dma_map_single(void *hwdev, void *ptr,u32 size); +dma_addr_t plat_dma_map_single(void *hwdev, void *ptr, u32 size); -void eth_rx_irq(int irqno,void *param); +void eth_rx_irq(int irqno, void *param); static char Rx_Buffer[Buffer_Size]; static char Tx_Buffer[Buffer_Size]; struct rt_eth_dev { - struct eth_device parent; - rt_uint8_t dev_addr[MAX_ADDR_LEN]; - char *name; - int iobase; - int state; - int index; - struct rt_timer link_timer; - struct rt_timer rx_poll_timer; - void *priv; + struct eth_device parent; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + char *name; + int iobase; + int state; + int index; + struct rt_timer link_timer; + struct rt_timer rx_poll_timer; + void *priv; }; static struct rt_eth_dev eth_dev; static struct rt_semaphore sem_ack, sem_lock; @@ -98,50 +98,52 @@ static struct rt_semaphore sem_ack, sem_lock; * continue further * only if the number of descriptors in the chain meets the requirements */ -s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode) +s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice *gmacdev, u32 no_of_desc, u32 desc_mode) { - s32 i; - DmaDesc * bf1; + s32 i; + DmaDesc *bf1; - DmaDesc *first_desc = NULL; + DmaDesc *first_desc = NULL; - dma_addr_t dma_addr; - gmacdev->TxDescCount = 0; + dma_addr_t dma_addr; + gmacdev->TxDescCount = 0; - first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory (gmacdev, sizeof(DmaDesc) * no_of_desc,&dma_addr); - if(first_desc == NULL){ - rt_kprintf("Error in Tx Descriptors memory allocation\n"); - return -ESYNOPGMACNOMEM; - } + first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory(gmacdev, sizeof(DmaDesc) * no_of_desc, &dma_addr); + if (first_desc == NULL) + { + rt_kprintf("Error in Tx Descriptors memory allocation\n"); + return -ESYNOPGMACNOMEM; + } - DEBUG_MES("tx_first_desc_addr = %p\n", first_desc); - DEBUG_MES("dmaadr = %p\n", dma_addr); - gmacdev->TxDescCount = no_of_desc; - gmacdev->TxDesc = first_desc; - gmacdev->TxDescDma = dma_addr; + DEBUG_MES("tx_first_desc_addr = %p\n", first_desc); + DEBUG_MES("dmaadr = %p\n", dma_addr); + gmacdev->TxDescCount = no_of_desc; + gmacdev->TxDesc = first_desc; + gmacdev->TxDescDma = dma_addr; - for(i =0; i < gmacdev->TxDescCount; i++){ - synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1); + for (i = 0; i < gmacdev->TxDescCount; i++) + { + synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount - 1); #if SYNOP_TOP_DEBUG - rt_kprintf("\n%02d %08x \n",i,(unsigned int)(gmacdev->TxDesc + i)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i))->status); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->length)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->buffer1)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->buffer2)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->data1)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->data2)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->dummy1)); - rt_kprintf("%08x ",(unsigned int)((gmacdev->TxDesc + i)->dummy2)); + rt_kprintf("\n%02d %08x \n", i, (unsigned int)(gmacdev->TxDesc + i)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i))->status); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->length)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->buffer1)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->buffer2)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->data1)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->data2)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->dummy1)); + rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->dummy2)); #endif - } + } - gmacdev->TxNext = 0; - gmacdev->TxBusy = 0; - gmacdev->TxNextDesc = gmacdev->TxDesc; - gmacdev->TxBusyDesc = gmacdev->TxDesc; - gmacdev->BusyTxDesc = 0; + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->TxNextDesc = gmacdev->TxDesc; + gmacdev->TxBusyDesc = gmacdev->TxDesc; + gmacdev->BusyTxDesc = 0; - return -ESYNOPGMACNOERR; + return -ESYNOPGMACNOERR; } /** @@ -169,778 +171,815 @@ s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 * this function * user should for gmacdev->RxDescCount to see how many descriptors are there in the chain. Should * continue further - * only if the number of descriptors in the chain meets the requirements - */ -s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode) + * only if the number of descriptors in the chain meets the requirements + */ +s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice *gmacdev, u32 no_of_desc, u32 desc_mode) { - s32 i; - DmaDesc * bf1; - DmaDesc *first_desc = NULL; + s32 i; + DmaDesc *bf1; + DmaDesc *first_desc = NULL; - dma_addr_t dma_addr; + dma_addr_t dma_addr; - gmacdev->RxDescCount = 0; - first_desc =(DmaDesc *)plat_alloc_consistent_dmaable_memory (gmacdev, sizeof(DmaDesc) * no_of_desc, &dma_addr); - if(first_desc == NULL){ - rt_kprintf("Error in Rx Descriptor Memory allocation in Ring mode\n"); - return -ESYNOPGMACNOMEM; - } + gmacdev->RxDescCount = 0; + first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory(gmacdev, sizeof(DmaDesc) * no_of_desc, &dma_addr); + if (first_desc == NULL) + { + rt_kprintf("Error in Rx Descriptor Memory allocation in Ring mode\n"); + return -ESYNOPGMACNOMEM; + } - DEBUG_MES("rx_first_desc_addr = %p\n", first_desc); - DEBUG_MES("dmaadr = %p\n", dma_addr); - gmacdev->RxDescCount = no_of_desc; - gmacdev->RxDesc = (DmaDesc *)first_desc; - gmacdev->RxDescDma = dma_addr; + DEBUG_MES("rx_first_desc_addr = %p\n", first_desc); + DEBUG_MES("dmaadr = %p\n", dma_addr); + gmacdev->RxDescCount = no_of_desc; + gmacdev->RxDesc = (DmaDesc *)first_desc; + gmacdev->RxDescDma = dma_addr; - for(i =0; i < gmacdev->RxDescCount; i++){ - synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1); + for (i = 0; i < gmacdev->RxDescCount; i++) + { + synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount - 1); - } + } - gmacdev->RxNext = 0; - gmacdev->RxBusy = 0; - gmacdev->RxNextDesc = gmacdev->RxDesc; - gmacdev->RxBusyDesc = gmacdev->RxDesc; + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + gmacdev->RxNextDesc = gmacdev->RxDesc; + gmacdev->RxBusyDesc = gmacdev->RxDesc; - gmacdev->BusyRxDesc = 0; + gmacdev->BusyRxDesc = 0; - return -ESYNOPGMACNOERR; + return -ESYNOPGMACNOERR; } void synopGMAC_linux_cable_unplug_function(void *adaptr) { - s32 data; - synopGMACPciNetworkAdapter *adapter = (synopGMACPciNetworkAdapter *)adaptr; - synopGMACdevice *gmacdev = adapter->synopGMACdev; - struct ethtool_cmd cmd; + s32 data; + synopGMACPciNetworkAdapter *adapter = (synopGMACPciNetworkAdapter *)adaptr; + synopGMACdevice *gmacdev = adapter->synopGMACdev; + struct ethtool_cmd cmd; - //rt_kprintf("%s\n",__FUNCTION__); - if(!mii_link_ok(&adapter->mii)){ - if(gmacdev->LinkState) - rt_kprintf("\r\nNo Link\r\n"); - gmacdev->DuplexMode = 0; - gmacdev->Speed = 0; - gmacdev->LoopBackMode = 0; - gmacdev->LinkState = 0; - } - else{ - data = synopGMAC_check_phy_init(adapter); + //rt_kprintf("%s\n",__FUNCTION__); + if (!mii_link_ok(&adapter->mii)) + { + if (gmacdev->LinkState) + rt_kprintf("\r\nNo Link\r\n"); + gmacdev->DuplexMode = 0; + gmacdev->Speed = 0; + gmacdev->LoopBackMode = 0; + gmacdev->LinkState = 0; + } + else + { + data = synopGMAC_check_phy_init(adapter); - if(gmacdev->LinkState != data){ - gmacdev->LinkState = data; - synopGMAC_mac_init(gmacdev); - rt_kprintf("Link is up in %s mode\n",(gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX": "HALF DUPLEX"); - if(gmacdev->Speed == SPEED1000) - rt_kprintf("Link is with 1000M Speed \r\n"); - if(gmacdev->Speed == SPEED100) - rt_kprintf("Link is with 100M Speed \n"); - if(gmacdev->Speed == SPEED10) - rt_kprintf("Link is with 10M Speed \n"); - } - } + if (gmacdev->LinkState != data) + { + gmacdev->LinkState = data; + synopGMAC_mac_init(gmacdev); + rt_kprintf("Link is up in %s mode\n", (gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX" : "HALF DUPLEX"); + if (gmacdev->Speed == SPEED1000) + rt_kprintf("Link is with 1000M Speed \r\n"); + if (gmacdev->Speed == SPEED100) + rt_kprintf("Link is with 100M Speed \n"); + if (gmacdev->Speed == SPEED10) + rt_kprintf("Link is with 10M Speed \n"); + } + } } -s32 synopGMAC_check_phy_init (synopGMACPciNetworkAdapter *adapter) -{ - struct ethtool_cmd cmd; - synopGMACdevice *gmacdev = adapter->synopGMACdev; +s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter) +{ + struct ethtool_cmd cmd; + synopGMACdevice *gmacdev = adapter->synopGMACdev; - if(!mii_link_ok(&adapter->mii)) - { - gmacdev->DuplexMode = FULLDUPLEX; - gmacdev->Speed = SPEED100; + if (!mii_link_ok(&adapter->mii)) + { + gmacdev->DuplexMode = FULLDUPLEX; + gmacdev->Speed = SPEED100; - return 0; - } - else - { - mii_ethtool_gset(&adapter->mii, &cmd); + return 0; + } + else + { + mii_ethtool_gset(&adapter->mii, &cmd); - gmacdev->DuplexMode = (cmd.duplex == DUPLEX_FULL) ? FULLDUPLEX: HALFDUPLEX ; - if(cmd.speed == SPEED_1000) - gmacdev->Speed = SPEED1000; - else if(cmd.speed == SPEED_100) - gmacdev->Speed = SPEED100; - else - gmacdev->Speed = SPEED10; - } + gmacdev->DuplexMode = (cmd.duplex == DUPLEX_FULL) ? FULLDUPLEX : HALFDUPLEX ; + if (cmd.speed == SPEED_1000) + gmacdev->Speed = SPEED1000; + else if (cmd.speed == SPEED_100) + gmacdev->Speed = SPEED100; + else + gmacdev->Speed = SPEED10; + } - return gmacdev->Speed|(gmacdev->DuplexMode<<4); + return gmacdev->Speed | (gmacdev->DuplexMode << 4); } static int Mac_change_check(u8 *macaddr0, u8 *macaddr1) { - int i; - for(i = 0; i < 6; i++){ - if(macaddr0[i] != macaddr1[i]) - return 1; - } - return 0; + int i; + for (i = 0; i < 6; i++) + { + if (macaddr0[i] != macaddr1[i]) + return 1; + } + return 0; } -static rt_err_t eth_init(rt_device_t device ) +static rt_err_t eth_init(rt_device_t device) { - struct eth_device *eth_device = (struct eth_device *)device; - RT_ASSERT(eth_device != RT_NULL); + struct eth_device *eth_device = (struct eth_device *)device; + RT_ASSERT(eth_device != RT_NULL); - s32 ijk; - s32 status = 0; - u64 dma_addr; - u32 Mac_changed = 0; - struct pbuf *pbuf; - u8 macaddr[6] = DEFAULT_MAC_ADDRESS; - struct rt_eth_dev *dev = ð_dev; - struct synopGMACNetworkAdapter *adapter = dev->priv; - synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev; + s32 ijk; + s32 status = 0; + u64 dma_addr; + u32 Mac_changed = 0; + struct pbuf *pbuf; + u8 macaddr[6] = DEFAULT_MAC_ADDRESS; + struct rt_eth_dev *dev = ð_dev; + struct synopGMACNetworkAdapter *adapter = dev->priv; + synopGMACdevice *gmacdev = (synopGMACdevice *)adapter->synopGMACdev; - synopGMAC_reset(gmacdev); - synopGMAC_attach(gmacdev,(regbase + MACBASE),(regbase + DMABASE), DEFAULT_PHY_BASE, macaddr); + synopGMAC_reset(gmacdev); + synopGMAC_attach(gmacdev, (regbase + MACBASE), (regbase + DMABASE), DEFAULT_PHY_BASE, macaddr); - synopGMAC_read_version(gmacdev); + synopGMAC_read_version(gmacdev); - synopGMAC_set_mdc_clk_div(gmacdev,GmiiCsrClk3); + synopGMAC_set_mdc_clk_div(gmacdev, GmiiCsrClk3); gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev); - init_phy(adapter->synopGMACdev); + init_phy(adapter->synopGMACdev); - rt_kprintf("tx desc_queue\n"); - synopGMAC_setup_tx_desc_queue(gmacdev,TRANSMIT_DESC_SIZE, RINGMODE); - synopGMAC_init_tx_desc_base(gmacdev); + DEBUG_MES("tx desc_queue\n"); + synopGMAC_setup_tx_desc_queue(gmacdev, TRANSMIT_DESC_SIZE, RINGMODE); + synopGMAC_init_tx_desc_base(gmacdev); - rt_kprintf("rx desc_queue\n"); - synopGMAC_setup_rx_desc_queue(gmacdev,RECEIVE_DESC_SIZE, RINGMODE); - synopGMAC_init_rx_desc_base(gmacdev); - DEBUG_MES("DmaRxBaseAddr = %08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr)); + DEBUG_MES("rx desc_queue\n"); + synopGMAC_setup_rx_desc_queue(gmacdev, RECEIVE_DESC_SIZE, RINGMODE); + synopGMAC_init_rx_desc_base(gmacdev); + DEBUG_MES("DmaRxBaseAddr = %08x\n", synopGMACReadReg(gmacdev->DmaBase, DmaRxBaseAddr)); -// u32 dmaRx_Base_addr = synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr); -// rt_kprintf("first_desc_addr = 0x%x\n", dmaRx_Base_addr); +// u32 dmaRx_Base_addr = synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr); +// rt_kprintf("first_desc_addr = 0x%x\n", dmaRx_Base_addr); #ifdef ENH_DESC_8W - synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words ); + synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words); #else - //synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip1); - synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip2); + //synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip1); + synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip2); #endif - synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128); + synopGMAC_dma_control_init(gmacdev, DmaStoreAndForward | DmaTxSecondFrame | DmaRxThreshCtrl128); - status = synopGMAC_check_phy_init(adapter); - synopGMAC_mac_init(gmacdev); + status = synopGMAC_check_phy_init(adapter); + synopGMAC_mac_init(gmacdev); - synopGMAC_pause_control(gmacdev); + synopGMAC_pause_control(gmacdev); #ifdef IPC_OFFLOAD - synopGMAC_enable_rx_chksum_offload(gmacdev); - synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); + synopGMAC_enable_rx_chksum_offload(gmacdev); + synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); #endif - u32 skb; - do{ - skb = (u32)plat_alloc_memory(RX_BUF_SIZE); //should skb aligned here? - if(skb == RT_NULL){ - rt_kprintf("ERROR in skb buffer allocation\n"); - break; - } + u32 skb; + do + { + skb = (u32)plat_alloc_memory(RX_BUF_SIZE); //should skb aligned here? + if (skb == RT_NULL) + { + rt_kprintf("ERROR in skb buffer allocation\n"); + break; + } - dma_addr = plat_dma_map_single(gmacdev,(void *)skb,RX_BUF_SIZE); //获取 skb 的 dma 地址 + dma_addr = plat_dma_map_single(gmacdev, (void *)skb, RX_BUF_SIZE); //获取 skb 的 dma 地址 - status = synopGMAC_set_rx_qptr(gmacdev,dma_addr,RX_BUF_SIZE,(u32)skb,0,0,0); - if(status < 0) - { - rt_kprintf("status < 0!!\n"); - plat_free_memory((void *)skb); - } - }while(status >= 0 && (status < (RECEIVE_DESC_SIZE - 1))); - - synopGMAC_clear_interrupt(gmacdev); + status = synopGMAC_set_rx_qptr(gmacdev, dma_addr, RX_BUF_SIZE, (u32)skb, 0, 0, 0); + if (status < 0) + { + rt_kprintf("status < 0!!\n"); + plat_free_memory((void *)skb); + } + } + while (status >= 0 && (status < (RECEIVE_DESC_SIZE - 1))); - synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF); - synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF); - synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF); + synopGMAC_clear_interrupt(gmacdev); -// synopGMAC_disable_interrupt_all(gmacdev); - synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); - synopGMAC_enable_dma_rx(gmacdev); - synopGMAC_enable_dma_tx(gmacdev); + synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF); + synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF); + synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF); - plat_delay(DEFAULT_LOOP_VARIABLE); - synopGMAC_check_phy_init(adapter); - synopGMAC_mac_init(gmacdev); +// synopGMAC_disable_interrupt_all(gmacdev); + synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); - rt_timer_init(&dev->link_timer, "link_timer", - synopGMAC_linux_cable_unplug_function, - (void *)adapter, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + plat_delay(DEFAULT_LOOP_VARIABLE); + synopGMAC_check_phy_init(adapter); + synopGMAC_mac_init(gmacdev); - rt_timer_start(&dev->link_timer); + rt_timer_init(&dev->link_timer, "link_timer", + synopGMAC_linux_cable_unplug_function, + (void *)adapter, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&dev->link_timer); #ifdef RT_USING_GMAC_INT_MODE - /* installl isr */ - DEBUG_MES("%s\n", __FUNCTION__); - rt_hw_interrupt_install(LS1C_MAC_IRQ, eth_rx_irq, RT_NULL, "e0_isr"); - rt_hw_interrupt_umask(LS1C_MAC_IRQ); + /* installl isr */ + DEBUG_MES("%s\n", __FUNCTION__); + rt_hw_interrupt_install(LS1C_MAC_IRQ, eth_rx_irq, RT_NULL, "e0_isr"); + rt_hw_interrupt_umask(LS1C_MAC_IRQ); #else - rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", - eth_rx_irq, - (void *)adapter, - 1, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", + eth_rx_irq, + (void *)adapter, + 1, + RT_TIMER_FLAG_PERIODIC); - rt_timer_start(&dev->rx_poll_timer); -#endif /*RT_USING_GMAC_INT_MODE*/ + rt_timer_start(&dev->rx_poll_timer); +#endif /*RT_USING_GMAC_INT_MODE*/ - rt_kprintf("eth_inited!\n"); + rt_kprintf("eth_inited!\n"); - return RT_EOK; + return RT_EOK; } static rt_err_t eth_open(rt_device_t dev, rt_uint16_t oflag) { - rt_kprintf("eth_open!!\n"); + rt_kprintf("eth_open!!\n"); - return RT_EOK; + return RT_EOK; } static rt_err_t eth_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } -static rt_size_t eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +static rt_size_t eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } -static rt_size_t eth_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +static rt_size_t eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t eth_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - if(args) rt_memcpy(args, eth_dev.dev_addr, 6); - else return -RT_ERROR; - break; + switch (cmd) + { + case NIOCTL_GADDR: + if (args) rt_memcpy(args, eth_dev.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } - return RT_EOK; + default : + break; + } + return RT_EOK; } -rt_err_t rt_eth_tx(rt_device_t device, struct pbuf* p) +rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) { - /* lock eth device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock eth device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - DEBUG_MES("in %s\n", __FUNCTION__); + DEBUG_MES("in %s\n", __FUNCTION__); - s32 status; - u32 pbuf; - u64 dma_addr; - u32 offload_needed = 0; - u32 index; - DmaDesc * dpr; - struct rt_eth_dev *dev = (struct rt_eth_dev *) device; - struct synopGMACNetworkAdapter *adapter; - synopGMACdevice * gmacdev; - adapter = (struct synopGMACNetworkAdapter *) dev->priv; - if(adapter == NULL) - return -1; + s32 status; + u32 pbuf; + u64 dma_addr; + u32 offload_needed = 0; + u32 index; + DmaDesc *dpr; + struct rt_eth_dev *dev = (struct rt_eth_dev *) device; + struct synopGMACNetworkAdapter *adapter; + synopGMACdevice *gmacdev; + adapter = (struct synopGMACNetworkAdapter *) dev->priv; + if (adapter == NULL) + return -1; - gmacdev = (synopGMACdevice *) adapter->synopGMACdev; - if(gmacdev == NULL) - return -1; + gmacdev = (synopGMACdevice *) adapter->synopGMACdev; + if (gmacdev == NULL) + return -1; - if(!synopGMAC_is_desc_owned_by_dma(gmacdev->TxNextDesc)) - { + if (!synopGMAC_is_desc_owned_by_dma(gmacdev->TxNextDesc)) + { - pbuf = (u32)plat_alloc_memory(p->len); - //pbuf = (u32)pbuf_alloc(PBUF_LINK, p->len, PBUF_RAM); - if(pbuf == 0) - { - rt_kprintf("===error in alloc bf1\n"); - return -1; - } + pbuf = (u32)plat_alloc_memory(p->tot_len); + //pbuf = (u32)pbuf_alloc(PBUF_LINK, p->len, PBUF_RAM); + if (pbuf == 0) + { + rt_kprintf("===error in alloc bf1\n"); + return -1; + } - DEBUG_MES("p->len = %d\n", p->len); - memcpy((void *)pbuf, p->payload, p->len); - dma_addr = plat_dma_map_single(gmacdev,(void*)pbuf,p->len); + DEBUG_MES("p->len = %d\n", p->len); + pbuf_copy_partial(p, (void *)pbuf, p->tot_len, 0); + dma_addr = plat_dma_map_single(gmacdev, (void *)pbuf, p->tot_len); - status = synopGMAC_set_tx_qptr(gmacdev,dma_addr,p->len,pbuf,0,0,0,offload_needed,&index,dpr); - if(status < 0){ - rt_kprintf("%s No More Free Tx Descriptors\n",__FUNCTION__); + status = synopGMAC_set_tx_qptr(gmacdev, dma_addr, p->tot_len, pbuf, 0, 0, 0, offload_needed, &index, dpr); + if (status < 0) + { + rt_kprintf("%s No More Free Tx Descriptors\n", __FUNCTION__); - plat_free_memory((void *)pbuf); - return -16; - } - } - synopGMAC_resume_dma_tx(gmacdev); + plat_free_memory((void *)pbuf); + return -16; + } + } + synopGMAC_resume_dma_tx(gmacdev); - s32 desc_index; - u32 data1, data2; - u32 dma_addr1, dma_addr2; - u32 length1, length2; + s32 desc_index; + u32 data1, data2; + u32 dma_addr1, dma_addr2; + u32 length1, length2; #ifdef ENH_DESC_8W - u32 ext_status; - u16 time_stamp_higher; - u32 time_stamp_high; - u32 time_stamp_low; + u32 ext_status; + u16 time_stamp_higher; + u32 time_stamp_high; + u32 time_stamp_low; #endif - do { + do + { #ifdef ENH_DESC_8W - desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2,&ext_status,&time_stamp_high,&time_stamp_low); - synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher); + desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2, &ext_status, &time_stamp_high, &time_stamp_low); + synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher); #else - desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2); + desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2); #endif - if(desc_index >= 0 && data1 != 0){ + if (desc_index >= 0 && data1 != 0) + { #ifdef IPC_OFFLOAD - if(synopGMAC_is_tx_ipv4header_checksum_error(gmacdev, status)){ - rt_kprintf("Harware Failed to Insert IPV4 Header Checksum\n"); - } - if(synopGMAC_is_tx_payload_checksum_error(gmacdev, status)){ - rt_kprintf("Harware Failed to Insert Payload Checksum\n"); - } + if (synopGMAC_is_tx_ipv4header_checksum_error(gmacdev, status)) + { + rt_kprintf("Harware Failed to Insert IPV4 Header Checksum\n"); + } + if (synopGMAC_is_tx_payload_checksum_error(gmacdev, status)) + { + rt_kprintf("Harware Failed to Insert Payload Checksum\n"); + } #endif - plat_free_memory((void *)(data1)); //sw: data1 = buffer1 + plat_free_memory((void *)(data1)); //sw: data1 = buffer1 - if(synopGMAC_is_desc_valid(status)){ - adapter->synopGMACNetStats.tx_bytes += length1; - adapter->synopGMACNetStats.tx_packets++; - } - else { - adapter->synopGMACNetStats.tx_errors++; - adapter->synopGMACNetStats.tx_aborted_errors += synopGMAC_is_tx_aborted(status); - adapter->synopGMACNetStats.tx_carrier_errors += synopGMAC_is_tx_carrier_error(status); - } - } adapter->synopGMACNetStats.collisions += synopGMAC_get_tx_collision_count(status); - } while(desc_index >= 0); + if (synopGMAC_is_desc_valid(status)) + { + adapter->synopGMACNetStats.tx_bytes += length1; + adapter->synopGMACNetStats.tx_packets++; + } + else + { + adapter->synopGMACNetStats.tx_errors++; + adapter->synopGMACNetStats.tx_aborted_errors += synopGMAC_is_tx_aborted(status); + adapter->synopGMACNetStats.tx_carrier_errors += synopGMAC_is_tx_carrier_error(status); + } + } + adapter->synopGMACNetStats.collisions += synopGMAC_get_tx_collision_count(status); + } + while (desc_index >= 0); - /* unlock eth device */ - rt_sem_release(&sem_lock); -// rt_kprintf("output %d bytes\n", p->len); - u32 test_data; - test_data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - return RT_EOK; + /* unlock eth device */ + rt_sem_release(&sem_lock); +// rt_kprintf("output %d bytes\n", p->len); + u32 test_data; + test_data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + return RT_EOK; } struct pbuf *rt_eth_rx(rt_device_t device) { - DEBUG_MES("%s : \n", __FUNCTION__); - struct rt_eth_dev *dev = ð_dev; - struct synopGMACNetworkAdapter *adapter; - synopGMACdevice * gmacdev; -// struct PmonInet * pinetdev; - s32 desc_index; - int i; - char * ptr; - u32 bf1; - u32 data1; - u32 data2; - u32 len; - u32 status; - u32 dma_addr1; - u32 dma_addr2; - struct pbuf *pbuf = RT_NULL; - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + DEBUG_MES("%s : \n", __FUNCTION__); + struct rt_eth_dev *dev = ð_dev; + struct synopGMACNetworkAdapter *adapter; + synopGMACdevice *gmacdev; +// struct PmonInet * pinetdev; + s32 desc_index; + int i; + char *ptr; + u32 bf1; + u32 data1; + u32 data2; + u32 len; + u32 status; + u32 dma_addr1; + u32 dma_addr2; + struct pbuf *pbuf = RT_NULL; + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - adapter = (struct synopGMACNetworkAdapter *) dev->priv; - if(adapter == NULL){ - rt_kprintf("%S : Unknown Device !!\n", __FUNCTION__); - return NULL; - } + adapter = (struct synopGMACNetworkAdapter *) dev->priv; + if (adapter == NULL) + { + rt_kprintf("%S : Unknown Device !!\n", __FUNCTION__); + return NULL; + } - gmacdev = (synopGMACdevice *) adapter->synopGMACdev; - if(gmacdev == NULL){ - rt_kprintf("%s : GMAC device structure is missing\n", __FUNCTION__); - return NULL; - } + gmacdev = (synopGMACdevice *) adapter->synopGMACdev; + if (gmacdev == NULL) + { + rt_kprintf("%s : GMAC device structure is missing\n", __FUNCTION__); + return NULL; + } - /*Handle the Receive Descriptors*/ - // do{ - desc_index = synopGMAC_get_rx_qptr(gmacdev, &status,&dma_addr1,NULL, &data1,&dma_addr2,NULL,&data2); + /*Handle the Receive Descriptors*/ + // do{ + desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, &dma_addr1, NULL, &data1, &dma_addr2, NULL, &data2); - if(desc_index >= 0 && data1 != 0){ - DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n",desc_index,dma_addr1,status); + if (desc_index >= 0 && data1 != 0) + { + DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n", desc_index, dma_addr1, status); - if(synopGMAC_is_rx_desc_valid(status)||SYNOP_PHY_LOOPBACK) - { - pbuf = pbuf_alloc(PBUF_LINK, MAX_ETHERNET_PAYLOAD, PBUF_RAM); - if(pbuf == 0) rt_kprintf("===error in pbuf_alloc\n"); + if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK) + { + pbuf = pbuf_alloc(PBUF_LINK, MAX_ETHERNET_PAYLOAD, PBUF_RAM); + if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n"); - dma_addr1 = plat_dma_map_single(gmacdev,(void*)data1,RX_BUF_SIZE); - len = synopGMAC_get_rx_desc_frame_length(status); //Not interested in Ethernet CRC bytes - rt_memcpy( pbuf->payload, (char *)data1, len); - DEBUG_MES("==get pkg len: %d\n",len); - } - else - { - rt_kprintf("s: %08x\n",status); - adapter->synopGMACNetStats.rx_errors++; - adapter->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status); - adapter->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status); - adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status); - adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status); - } + dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE); + len = synopGMAC_get_rx_desc_frame_length(status); //Not interested in Ethernet CRC bytes + rt_memcpy(pbuf->payload, (char *)data1, len); + DEBUG_MES("==get pkg len: %d\n", len); + } + else + { + rt_kprintf("s: %08x\n", status); + adapter->synopGMACNetStats.rx_errors++; + adapter->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status); + adapter->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status); + adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status); + adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status); + } - desc_index = synopGMAC_set_rx_qptr(gmacdev,dma_addr1, RX_BUF_SIZE, (u32)data1,0,0,0); + desc_index = synopGMAC_set_rx_qptr(gmacdev, dma_addr1, RX_BUF_SIZE, (u32)data1, 0, 0, 0); - if(desc_index < 0){ + if (desc_index < 0) + { #if SYNOP_RX_DEBUG - rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n",(u32)data1); + rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n", (u32)data1); #endif - plat_free_memory((void *)data1); - } + plat_free_memory((void *)data1); + } - } + } - // }while(desc_index >= 0); - rt_sem_release(&sem_lock); - DEBUG_MES("%s : before return \n", __FUNCTION__); - return pbuf; + // }while(desc_index >= 0); + rt_sem_release(&sem_lock); + DEBUG_MES("%s : before return \n", __FUNCTION__); + return pbuf; } static int rtl88e1111_config_init(synopGMACdevice *gmacdev) { - int retval, err; - u16 data; + int retval, err; + u16 data; - DEBUG_MES("in %s\n", __FUNCTION__); - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,&data); - data = data | 0x82; - err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,data); - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,&data); - data = data | 0x8000; - err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,data); + DEBUG_MES("in %s\n", __FUNCTION__); + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, &data); + data = data | 0x82; + err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, data); + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, &data); + data = data | 0x8000; + err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, data); #if SYNOP_PHY_LOOPBACK - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,&data); - data = data | 0x70; - data = data & 0xffdf; - err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x14,data); - data = 0x8000; - err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,data); - data = 0x5140; - err = synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x00,data); + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, &data); + data = data | 0x70; + data = data & 0xffdf; + err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, data); + data = 0x8000; + err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, data); + data = 0x5140; + err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, data); #endif - if (err < 0) - return err; - return 0; + if (err < 0) + return err; + return 0; } int init_phy(synopGMACdevice *gmacdev) { - u16 data; + u16 data; - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,2,&data); - /*set 88e1111 clock phase delay*/ - if(data == 0x141) - rtl88e1111_config_init(gmacdev); + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 2, &data); + /*set 88e1111 clock phase delay*/ + if (data == 0x141) + rtl88e1111_config_init(gmacdev); #if defined (RMII) - else if(data == 0x8201) - { - //RTL8201 - data = 0x400; // set RMII mode - synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x19,data); - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x19,&data); - TR("phy reg25 is %0x \n",data); + else if (data == 0x8201) + { + //RTL8201 + data = 0x400; // set RMII mode + synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x19, data); + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x19, &data); + TR("phy reg25 is %0x \n", data); - data = 0x3100; //set 100M speed - synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,data); - } - else if(data == 0x0180 || data == 0x0181) - { - //DM9161 - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x10,&data); - data |= (1 << 8); //set RMII mode - synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x10,data); //set RMII mode - synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x10,&data); - TR("phy reg16 is 0x%0x \n",data); + data = 0x3100; //set 100M speed + synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x0, data); + } + else if (data == 0x0180 || data == 0x0181) + { + //DM9161 + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x10, &data); + data |= (1 << 8); //set RMII mode + synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x10, data); //set RMII mode + synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x10, &data); + TR("phy reg16 is 0x%0x \n", data); - // synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,&data); - // data &= ~(1<<10); - data = 0x3100; //set auto- - //data = 0x0100; //set 10M speed - synopGMAC_write_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,data); - } + // synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,&data); + // data &= ~(1<<10); + data = 0x3100; //set auto- + //data = 0x0100; //set 10M speed + synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x0, data); + } #endif - return 0; + return 0; } -u32 synopGMAC_wakeup_filter_config3[] = { - 0x00000000, - 0x000000FF, - 0x00000000, - 0x00000000, - 0x00000100, - 0x00003200, - 0x7eED0000, - 0x00000000 +u32 synopGMAC_wakeup_filter_config3[] = +{ + 0x00000000, + 0x000000FF, + 0x00000000, + 0x00000000, + 0x00000100, + 0x00003200, + 0x7eED0000, + 0x00000000 }; static void synopGMAC_linux_powerdown_mac(synopGMACdevice *gmacdev) { - rt_kprintf("Put the GMAC to power down mode..\n"); + rt_kprintf("Put the GMAC to power down mode..\n"); - GMAC_Power_down = 1; + GMAC_Power_down = 1; - synopGMAC_disable_dma_tx(gmacdev); - plat_delay(10000); + synopGMAC_disable_dma_tx(gmacdev); + plat_delay(10000); - synopGMAC_tx_disable(gmacdev); - synopGMAC_rx_disable(gmacdev); - plat_delay(10000); + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); + plat_delay(10000); - synopGMAC_disable_dma_rx(gmacdev); + synopGMAC_disable_dma_rx(gmacdev); - synopGMAC_magic_packet_enable(gmacdev); - synopGMAC_write_wakeup_frame_register(gmacdev, synopGMAC_wakeup_filter_config3); + synopGMAC_magic_packet_enable(gmacdev); + synopGMAC_write_wakeup_frame_register(gmacdev, synopGMAC_wakeup_filter_config3); - synopGMAC_wakeup_frame_enable(gmacdev); + synopGMAC_wakeup_frame_enable(gmacdev); - synopGMAC_rx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); - synopGMAC_pmt_int_enable(gmacdev); + synopGMAC_pmt_int_enable(gmacdev); - synopGMAC_power_down_enable(gmacdev); - return; + synopGMAC_power_down_enable(gmacdev); + return; } static void synopGMAC_linux_powerup_mac(synopGMACdevice *gmacdev) { - GMAC_Power_down = 0; - if( synopGMAC_is_magic_packet_received(gmacdev)) - rt_kprintf("GMAC wokeup due to Magic Pkt Received\n"); - if(synopGMAC_is_wakeup_frame_received(gmacdev)) - rt_kprintf("GMAC wokeup due to Wakeup Frame Received\n"); + GMAC_Power_down = 0; + if (synopGMAC_is_magic_packet_received(gmacdev)) + rt_kprintf("GMAC wokeup due to Magic Pkt Received\n"); + if (synopGMAC_is_wakeup_frame_received(gmacdev)) + rt_kprintf("GMAC wokeup due to Wakeup Frame Received\n"); - synopGMAC_pmt_int_disable(gmacdev); + synopGMAC_pmt_int_disable(gmacdev); - synopGMAC_rx_enable(gmacdev); - synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_rx_enable(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); - synopGMAC_tx_enable(gmacdev); - synopGMAC_enable_dma_tx(gmacdev); - return; + synopGMAC_tx_enable(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + return; } -static int mdio_read(synopGMACPciNetworkAdapter *adapter, int addr, int reg) +static int mdio_read(synopGMACPciNetworkAdapter *adapter, int addr, int reg) { - synopGMACdevice * gmacdev; - u16 data; - gmacdev = adapter->synopGMACdev; + synopGMACdevice *gmacdev; + u16 data; + gmacdev = adapter->synopGMACdev; - synopGMAC_read_phy_reg(gmacdev->MacBase,addr,reg, &data); - return data; + synopGMAC_read_phy_reg(gmacdev->MacBase, addr, reg, &data); + return data; } static void mdio_write(synopGMACPciNetworkAdapter *adapter, int addr, int reg, int data) { - synopGMACdevice * gmacdev; - gmacdev = adapter->synopGMACdev; - synopGMAC_write_phy_reg(gmacdev->MacBase,addr,reg,data); + synopGMACdevice *gmacdev; + gmacdev = adapter->synopGMACdev; + synopGMAC_write_phy_reg(gmacdev->MacBase, addr, reg, data); } -void eth_rx_irq(int irqno,void *param) +void eth_rx_irq(int irqno, void *param) { - struct rt_eth_dev *dev = ð_dev; - struct synopGMACNetworkAdapter *adapter = dev->priv; - //DEBUG_MES("in irq!!\n"); + struct rt_eth_dev *dev = ð_dev; + struct synopGMACNetworkAdapter *adapter = dev->priv; + //DEBUG_MES("in irq!!\n"); #ifdef RT_USING_GMAC_INT_MODE - int i ; - for(i = 0; i < 7200; i++) - ; -#endif /*RT_USING_GMAC_INT_MODE*/ - synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev; + int i ; + for (i = 0; i < 7200; i++) + ; +#endif /*RT_USING_GMAC_INT_MODE*/ + synopGMACdevice *gmacdev = (synopGMACdevice *)adapter->synopGMACdev; - u32 interrupt,dma_status_reg; - s32 status; - u32 dma_addr; + u32 interrupt, dma_status_reg; + s32 status; + u32 dma_addr; - //rt_kprintf("irq i = %d\n", i++); - dma_status_reg = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - if(dma_status_reg == 0) - { - rt_kprintf("dma_status ==0 \n"); - return; - } + //rt_kprintf("irq i = %d\n", i++); + dma_status_reg = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + if (dma_status_reg == 0) + { + rt_kprintf("dma_status ==0 \n"); + return; + } - //rt_kprintf("dma_status_reg is 0x%x\n", dma_status_reg); - u32 gmacstatus; - synopGMAC_disable_interrupt_all(gmacdev); - gmacstatus = synopGMACReadReg(gmacdev->MacBase,GmacStatus); + //rt_kprintf("dma_status_reg is 0x%x\n", dma_status_reg); + u32 gmacstatus; + synopGMAC_disable_interrupt_all(gmacdev); + gmacstatus = synopGMACReadReg(gmacdev->MacBase, GmacStatus); - if(dma_status_reg & GmacPmtIntr){ - rt_kprintf("%s:: Interrupt due to PMT module\n",__FUNCTION__); - //synopGMAC_linux_powerup_mac(gmacdev); - } - if(dma_status_reg & GmacMmcIntr){ - rt_kprintf("%s:: Interrupt due to MMC module\n",__FUNCTION__); - DEBUG_MES("%s:: synopGMAC_rx_int_status = %08x\n",__FUNCTION__,synopGMAC_read_mmc_rx_int_status(gmacdev)); - DEBUG_MES("%s:: synopGMAC_tx_int_status = %08x\n",__FUNCTION__,synopGMAC_read_mmc_tx_int_status(gmacdev)); - } + if (dma_status_reg & GmacPmtIntr) + { + rt_kprintf("%s:: Interrupt due to PMT module\n", __FUNCTION__); + //synopGMAC_linux_powerup_mac(gmacdev); + } + if (dma_status_reg & GmacMmcIntr) + { + rt_kprintf("%s:: Interrupt due to MMC module\n", __FUNCTION__); + DEBUG_MES("%s:: synopGMAC_rx_int_status = %08x\n", __FUNCTION__, synopGMAC_read_mmc_rx_int_status(gmacdev)); + DEBUG_MES("%s:: synopGMAC_tx_int_status = %08x\n", __FUNCTION__, synopGMAC_read_mmc_tx_int_status(gmacdev)); + } - if(dma_status_reg & GmacLineIntfIntr){ - rt_kprintf("%s:: Interrupt due to GMAC LINE module\n",__FUNCTION__); - } + if (dma_status_reg & GmacLineIntfIntr) + { + rt_kprintf("%s:: Interrupt due to GMAC LINE module\n", __FUNCTION__); + } - interrupt = synopGMAC_get_interrupt_type(gmacdev); - //rt_kprintf("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt); - if(interrupt & synopGMACDmaError){ - u8 mac_addr0[6]; - rt_kprintf("%s::Fatal Bus Error Inetrrupt Seen\n",__FUNCTION__); + interrupt = synopGMAC_get_interrupt_type(gmacdev); + //rt_kprintf("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt); + if (interrupt & synopGMACDmaError) + { + u8 mac_addr0[6]; + rt_kprintf("%s::Fatal Bus Error Inetrrupt Seen\n", __FUNCTION__); - memcpy(mac_addr0,dev->dev_addr,6); - synopGMAC_disable_dma_tx(gmacdev); - synopGMAC_disable_dma_rx(gmacdev); + memcpy(mac_addr0, dev->dev_addr, 6); + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_disable_dma_rx(gmacdev); - synopGMAC_take_desc_ownership_tx(gmacdev); - synopGMAC_take_desc_ownership_rx(gmacdev); + synopGMAC_take_desc_ownership_tx(gmacdev); + synopGMAC_take_desc_ownership_rx(gmacdev); - synopGMAC_init_tx_rx_desc_queue(gmacdev); + synopGMAC_init_tx_rx_desc_queue(gmacdev); - synopGMAC_reset(gmacdev); + synopGMAC_reset(gmacdev); - synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr0); - synopGMAC_dma_bus_mode_init(gmacdev,DmaFixedBurstEnable| DmaBurstLength8 | DmaDescriptorSkip2 ); - synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward); - synopGMAC_init_rx_desc_base(gmacdev); - synopGMAC_init_tx_desc_base(gmacdev); - synopGMAC_mac_init(gmacdev); - synopGMAC_enable_dma_rx(gmacdev); - synopGMAC_enable_dma_tx(gmacdev); + synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr0); + synopGMAC_dma_bus_mode_init(gmacdev, DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2); + synopGMAC_dma_control_init(gmacdev, DmaStoreAndForward); + synopGMAC_init_rx_desc_base(gmacdev); + synopGMAC_init_tx_desc_base(gmacdev); + synopGMAC_mac_init(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); - } - if(interrupt & synopGMACDmaRxNormal){ - //DEBUG_MES("%s:: Rx Normal \n", __FUNCTION__); - //synop_handle_received_data(netdev); - eth_device_ready(ð_dev.parent); - } - if(interrupt & synopGMACDmaRxAbnormal){ - //rt_kprintf("%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__); - if(GMAC_Power_down == 0){ - adapter->synopGMACNetStats.rx_over_errors++; - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,0x80); - synopGMAC_resume_dma_rx(gmacdev); - } - } - if(interrupt & synopGMACDmaRxStopped){ - rt_kprintf("%s::Receiver stopped seeing Rx interrupts\n",__FUNCTION__); //Receiver gone in to stopped state - } + } + if (interrupt & synopGMACDmaRxNormal) + { + //DEBUG_MES("%s:: Rx Normal \n", __FUNCTION__); + //synop_handle_received_data(netdev); + eth_device_ready(ð_dev.parent); + } + if (interrupt & synopGMACDmaRxAbnormal) + { + //rt_kprintf("%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__); + if (GMAC_Power_down == 0) + { + adapter->synopGMACNetStats.rx_over_errors++; + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus, 0x80); + synopGMAC_resume_dma_rx(gmacdev); + } + } + if (interrupt & synopGMACDmaRxStopped) + { + rt_kprintf("%s::Receiver stopped seeing Rx interrupts\n", __FUNCTION__); //Receiver gone in to stopped state + } - if(interrupt & synopGMACDmaTxNormal){ - DEBUG_MES("%s::Finished Normal Transmission \n",__FUNCTION__); - // synop_handle_transmit_over(netdev); - } + if (interrupt & synopGMACDmaTxNormal) + { + DEBUG_MES("%s::Finished Normal Transmission \n", __FUNCTION__); + // synop_handle_transmit_over(netdev); + } - if(interrupt & synopGMACDmaTxAbnormal){ - rt_kprintf("%s::Abnormal Tx Interrupt Seen\n",__FUNCTION__); - } - if(interrupt & synopGMACDmaTxStopped){ - TR("%s::Transmitter stopped sending the packets\n",__FUNCTION__); - if(GMAC_Power_down == 0){ // If Mac is not in powerdown - synopGMAC_disable_dma_tx(gmacdev); - synopGMAC_take_desc_ownership_tx(gmacdev); + if (interrupt & synopGMACDmaTxAbnormal) + { + rt_kprintf("%s::Abnormal Tx Interrupt Seen\n", __FUNCTION__); + } + if (interrupt & synopGMACDmaTxStopped) + { + TR("%s::Transmitter stopped sending the packets\n", __FUNCTION__); + if (GMAC_Power_down == 0) // If Mac is not in powerdown + { + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_take_desc_ownership_tx(gmacdev); - synopGMAC_enable_dma_tx(gmacdev); - // netif_wake_queue(netdev); - TR("%s::Transmission Resumed\n",__FUNCTION__); - } - } - /* Enable the interrrupt before returning from ISR*/ - synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + synopGMAC_enable_dma_tx(gmacdev); + // netif_wake_queue(netdev); + TR("%s::Transmission Resumed\n", __FUNCTION__); + } + } + /* Enable the interrrupt before returning from ISR*/ + synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); - return; + return; } int rt_hw_eth_init(void) { - u64 base_addr = Gmac_base; - struct synopGMACNetworkAdapter * synopGMACadapter; - static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS; - int index; - - rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + u64 base_addr = Gmac_base; + struct synopGMACNetworkAdapter *synopGMACadapter; + static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS; + int index; - for(index=21; index<=30;index++) - { - pin_set_purpose(index, PIN_PURPOSE_OTHER); - pin_set_remap(index, PIN_REMAP_DEFAULT); - } - pin_set_purpose(35, PIN_PURPOSE_OTHER); - pin_set_remap(35, PIN_REMAP_DEFAULT); - *((volatile unsigned int *)0xbfd00424) &= ~(7 << 28); - *((volatile unsigned int *)0xbfd00424) |= (1 << 30); //wl rmii + rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + + for (index = 21; index <= 30; index++) + { + pin_set_purpose(index, PIN_PURPOSE_OTHER); + pin_set_remap(index, PIN_REMAP_DEFAULT); + } + pin_set_purpose(35, PIN_PURPOSE_OTHER); + pin_set_remap(35, PIN_REMAP_DEFAULT); + *((volatile unsigned int *)0xbfd00424) &= ~(7 << 28); + *((volatile unsigned int *)0xbfd00424) |= (1 << 30); //wl rmii - memset(ð_dev, 0, sizeof(eth_dev)); - synopGMACadapter = (struct synopGMACNetworkAdapter * )plat_alloc_memory(sizeof (struct synopGMACNetworkAdapter)); - if(!synopGMACadapter){ - rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); - } - memset((char *)synopGMACadapter ,0, sizeof (struct synopGMACNetworkAdapter)); + memset(ð_dev, 0, sizeof(eth_dev)); + synopGMACadapter = (struct synopGMACNetworkAdapter *)plat_alloc_memory(sizeof(struct synopGMACNetworkAdapter)); + if (!synopGMACadapter) + { + rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); + } + memset((char *)synopGMACadapter, 0, sizeof(struct synopGMACNetworkAdapter)); - synopGMACadapter->synopGMACdev = NULL; + synopGMACadapter->synopGMACdev = NULL; - synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof (synopGMACdevice)); - if(!synopGMACadapter->synopGMACdev){ - rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); - } - memset((char *)synopGMACadapter->synopGMACdev ,0, sizeof (synopGMACdevice)); - /* - * Attach the device to MAC struct This will configure all the required base addresses - * such as Mac base, configuration base, phy base address(out of 32 possible phys) - * */ - synopGMAC_attach(synopGMACadapter->synopGMACdev,(regbase + MACBASE), regbase + DMABASE, DEFAULT_PHY_BASE, mac_addr0); + synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof(synopGMACdevice)); + if (!synopGMACadapter->synopGMACdev) + { + rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); + } + memset((char *)synopGMACadapter->synopGMACdev, 0, sizeof(synopGMACdevice)); + /* + * Attach the device to MAC struct This will configure all the required base addresses + * such as Mac base, configuration base, phy base address(out of 32 possible phys) + * */ + synopGMAC_attach(synopGMACadapter->synopGMACdev, (regbase + MACBASE), regbase + DMABASE, DEFAULT_PHY_BASE, mac_addr0); - init_phy(synopGMACadapter->synopGMACdev); - synopGMAC_reset(synopGMACadapter->synopGMACdev); + init_phy(synopGMACadapter->synopGMACdev); + synopGMAC_reset(synopGMACadapter->synopGMACdev); - /* MII setup */ - synopGMACadapter->mii.phy_id_mask = 0x1F; - synopGMACadapter->mii.reg_num_mask = 0x1F; - synopGMACadapter->mii.dev = synopGMACadapter; - synopGMACadapter->mii.mdio_read = mdio_read; - synopGMACadapter->mii.mdio_write = mdio_write; - synopGMACadapter->mii.phy_id = synopGMACadapter->synopGMACdev->PhyBase; - synopGMACadapter->mii.supports_gmii = mii_check_gmii_support(&synopGMACadapter->mii); + /* MII setup */ + synopGMACadapter->mii.phy_id_mask = 0x1F; + synopGMACadapter->mii.reg_num_mask = 0x1F; + synopGMACadapter->mii.dev = synopGMACadapter; + synopGMACadapter->mii.mdio_read = mdio_read; + synopGMACadapter->mii.mdio_write = mdio_write; + synopGMACadapter->mii.phy_id = synopGMACadapter->synopGMACdev->PhyBase; + synopGMACadapter->mii.supports_gmii = mii_check_gmii_support(&synopGMACadapter->mii); - eth_dev.iobase = base_addr; - eth_dev.name = "e0"; - eth_dev.priv = synopGMACadapter; - eth_dev.dev_addr[0] = mac_addr0[0]; - eth_dev.dev_addr[1] = mac_addr0[1]; - eth_dev.dev_addr[2] = mac_addr0[2]; - eth_dev.dev_addr[3] = mac_addr0[3]; - eth_dev.dev_addr[4] = mac_addr0[4]; - eth_dev.dev_addr[5] = mac_addr0[5]; + eth_dev.iobase = base_addr; + eth_dev.name = "e0"; + eth_dev.priv = synopGMACadapter; + eth_dev.dev_addr[0] = mac_addr0[0]; + eth_dev.dev_addr[1] = mac_addr0[1]; + eth_dev.dev_addr[2] = mac_addr0[2]; + eth_dev.dev_addr[3] = mac_addr0[3]; + eth_dev.dev_addr[4] = mac_addr0[4]; + eth_dev.dev_addr[5] = mac_addr0[5]; - eth_dev.parent.parent.type = RT_Device_Class_NetIf; - eth_dev.parent.parent.init = eth_init; - eth_dev.parent.parent.open = eth_open; - eth_dev.parent.parent.close = eth_close; - eth_dev.parent.parent.read = eth_read; - eth_dev.parent.parent.write = eth_write; - eth_dev.parent.parent.control = eth_control; - eth_dev.parent.parent.user_data = RT_NULL; + eth_dev.parent.parent.type = RT_Device_Class_NetIf; + eth_dev.parent.parent.init = eth_init; + eth_dev.parent.parent.open = eth_open; + eth_dev.parent.parent.close = eth_close; + eth_dev.parent.parent.read = eth_read; + eth_dev.parent.parent.write = eth_write; + eth_dev.parent.parent.control = eth_control; + eth_dev.parent.parent.user_data = RT_NULL; - eth_dev.parent.eth_tx = rt_eth_tx; - eth_dev.parent.eth_rx = rt_eth_rx; + eth_dev.parent.eth_tx = rt_eth_tx; + eth_dev.parent.eth_rx = rt_eth_rx; - eth_device_init(&(eth_dev.parent), "e0"); + eth_device_init(&(eth_dev.parent), "e0"); - return 0; + return 0; } INIT_DEVICE_EXPORT(rt_hw_eth_init); diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h index 7562dd00d3..889d051eef 100644 --- a/bsp/ls1cdev/rtconfig.h +++ b/bsp/ls1cdev/rtconfig.h @@ -8,15 +8,27 @@ #define RT_NAME_MAX 10 #define RT_ALIGN_SIZE 8 +/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_DEBUG #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -#define RT_DEBUG_THREAD 0 #define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 1024 +/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ /* Inter-Thread communication */ @@ -25,17 +37,23 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP +/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMHEAP_AS_HEAP is not set */ +/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE +/* RT_USING_DEVICE_OPS is not set */ #define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 @@ -46,9 +64,11 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ +/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -58,11 +78,14 @@ #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT +/* FINSH_USING_MSH_ONLY is not set */ #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -72,6 +95,7 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 4 +/* RT_USING_DFS_MNTTABLE is not set */ #define RT_USING_DFS_ELMFAT /* elm-chan's FatFs, Generic FAT Filesystem Module */ @@ -79,40 +103,82 @@ #define RT_DFS_ELM_CODE_PAGE 936 #define RT_DFS_ELM_WORD_ACCESS #define RT_DFS_ELM_USE_LFN_0 +/* RT_DFS_ELM_USE_LFN_1 is not set */ +/* RT_DFS_ELM_USE_LFN_2 is not set */ +/* RT_DFS_ELM_USE_LFN_3 is not set */ #define RT_DFS_ELM_USE_LFN 0 #define RT_DFS_ELM_MAX_LFN 64 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +/* RT_DFS_ELM_USE_ERASE is not set */ #define RT_DFS_ELM_REENTRANT +/* RT_USING_DFS_DEVFS is not set */ +/* RT_USING_DFS_ROMFS is not set */ +/* RT_USING_DFS_RAMFS is not set */ +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ +/* RT_USING_DFS_NFS is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_USING_CAN -#define RT_CAN_USING_HDR +/* RT_CAN_USING_HDR is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_MTD is not set */ +/* RT_USING_PM is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ #define RT_USING_SPI #define RT_USING_SPI_MSD +/* RT_USING_SFUD is not set */ +/* RT_USING_W25QXX is not set */ +/* RT_USING_GD is not set */ +/* RT_USING_ENC28J60 is not set */ +/* RT_USING_SPI_WIFI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_AUDIO is not set */ + +/* Using WiFi */ + +/* RT_USING_WIFI is not set */ /* Using USB */ +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC #define RT_USING_PTHREADS +/* RT_USING_POSIX is not set */ +/* RT_USING_MODULE is not set */ -/* Network stack */ +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ /* light weight TCP/IP stack */ #define RT_USING_LWIP #define RT_USING_LWIP141 +/* RT_USING_LWIP202 is not set */ +/* RT_USING_LWIP210 is not set */ #define RT_LWIP_IGMP #define RT_LWIP_ICMP +/* RT_LWIP_SNMP is not set */ #define RT_LWIP_DNS #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 @@ -125,6 +191,8 @@ #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP +/* RT_LWIP_RAW is not set */ +/* RT_LWIP_PPP is not set */ #define RT_MEMP_NUM_NETCONN 8 #define RT_LWIP_PBUF_NUM 4 #define RT_LWIP_RAW_PCB_NUM 4 @@ -136,24 +204,40 @@ #define RT_LWIP_TCPTHREAD_PRIORITY 12 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 #define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +/* LWIP_NO_RX_THREAD is not set */ +/* LWIP_NO_TX_THREAD is not set */ #define RT_LWIP_ETHTHREAD_PRIORITY 14 #define RT_LWIP_ETHTHREAD_STACKSIZE 512 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +/* RT_LWIP_REASSEMBLY_FRAG is not set */ #define LWIP_NETIF_STATUS_CALLBACK 1 #define SO_REUSE 1 #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +/* RT_LWIP_NETIF_LOOPBACK is not set */ #define LWIP_NETIF_LOOPBACK 0 +/* RT_LWIP_STATS is not set */ +/* RT_LWIP_DEBUG is not set */ /* Modbus master and slave stack */ +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ +/* LWIP_USING_DHCPD is not set */ /* VBUS(Virtual Software BUS) */ +/* RT_USING_VBUS is not set */ /* Utilities */ +/* RT_USING_LOGTRACE is not set */ +/* RT_USING_RYM is not set */ +/* RT_USING_ULOG is not set */ /* RT-Thread online packages */ @@ -161,40 +245,76 @@ /* RT-Thread GUI Engine */ +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ /* IoT - internet of things */ +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ /* Wi-Fi */ /* Marvell WiFi */ +/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ /* security packages */ +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ /* language packages */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ +/* PKG_USING_OPENMV is not set */ /* tools packages */ +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ +/* PKG_USING_IPERF is not set */ /* miscellaneous packages */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ /* example package: hello */ +/* PKG_USING_HELLO is not set */ +/* RT_USING_SELF_BOOT is not set */ #define RT_USING_UART2 #define RT_UART_RX_BUFFER_SIZE 64 #define RT_USING_GMAC_INT_MODE -#define RT_USING_SPI0 -#define RT_USING_SPI1 +/* RT_USING_FPU is not set */ +/* RT_USING_SPI0 is not set */ +/* RT_USING_SPI1 is not set */ #define RT_USING_I2C1 #define RT_USING_I2C2 #define USING_BXCAN0 diff --git a/bsp/mb9bf500r/fm3_easy_kit.ewp b/bsp/mb9bf500r/fm3_easy_kit.ewp index 413df3c022..d51d49cf6b 100644 --- a/bsp/mb9bf500r/fm3_easy_kit.ewp +++ b/bsp/mb9bf500r/fm3_easy_kit.ewp @@ -1784,9 +1784,6 @@ $PROJ_DIR$\..\..\src\mempool.c - - $PROJ_DIR$\..\..\src\module.c - $PROJ_DIR$\..\..\src\object.c diff --git a/bsp/mb9bf500r/project.uvopt b/bsp/mb9bf500r/project.uvopt index af19ecd27e..f4ebac8267 100644 --- a/bsp/mb9bf500r/project.uvopt +++ b/bsp/mb9bf500r/project.uvopt @@ -484,20 +484,6 @@ ..\..\src\mempool.c mempool.c - - 4 - 23 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\module.c - module.c - 4 24 diff --git a/bsp/mb9bf500r/project.uvproj b/bsp/mb9bf500r/project.uvproj index 28a0d0dccf..971e04f6e1 100644 --- a/bsp/mb9bf500r/project.uvproj +++ b/bsp/mb9bf500r/project.uvproj @@ -513,11 +513,6 @@ 1 ..\..\src\mempool.c - - module.c - 1 - ..\..\src\module.c - object.c 1 diff --git a/bsp/mini2440/project.Uv2 b/bsp/mini2440/project.Uv2 index b8dd2195ba..be4f65b05d 100644 --- a/bsp/mini2440/project.Uv2 +++ b/bsp/mini2440/project.Uv2 @@ -30,7 +30,6 @@ File 3,1,<../../src/irq.c> File 3,1,<../../src/kservice.c> File 3,1,<../../src/mem.c> File 3,1,<../../src/mempool.c> -File 3,1,<../../src/module.c> File 3,1,<../../src/object.c> File 3,1,<../../src/scheduler.c> File 3,1,<../../src/signal.c> diff --git a/bsp/mini2440/project.uvproj b/bsp/mini2440/project.uvproj index d29e75e701..5eb27ce34b 100644 --- a/bsp/mini2440/project.uvproj +++ b/bsp/mini2440/project.uvproj @@ -493,13 +493,6 @@ ../../src/mempool.c - - - module.c - 1 - ../../src/module.c - - object.c diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h index 475ba91062..8147715c8f 100644 --- a/bsp/mini2440/rtconfig.h +++ b/bsp/mini2440/rtconfig.h @@ -171,57 +171,6 @@ #define RT_LWIP_MSKADDR "255.255.255.0" //
-//
-#define RT_USING_MODULE -// -#define RT_USING_LIBDL -//
- -//
-// #define RT_USING_RTGUI -// -#define RTGUI_NAME_MAX 16 -// -#define RTGUI_USING_FONT16 -// -#define RTGUI_USING_FONT12 -// -#define RTGUI_USING_FONTHZ -// -#define RTGUI_USING_DFS_FILERW -// -// #define RTGUI_USING_HZ_FILE -// -#define RTGUI_USING_HZ_BMP -// -// #define RTGUI_USING_SMALL_SIZE -// -// #define RTGUI_USING_MOUSE_CURSOR -// -#define RTGUI_IMAGE_XPM -// -#define RTGUI_IMAGE_JPEG -// -//#define RTGUI_IMAGE_PNG -// -#define RTGUI_IMAGE_BMP -//
- // -/* SECTION: FTK support */ -/* using FTK support */ -/* #define RT_USING_FTK */ - -/* - * Note on FTK: - * - * FTK depends : - * #define RT_USING_NEWLIB - * #define DFS_USING_WORKDIR - * - * And the maximal length must great than 64 - * #define RT_DFS_ELM_MAX_LFN 128 - */ - #endif diff --git a/bsp/nios_ii/readme_cn.txt b/bsp/nios_ii/readme_cn.txt index 6884bee2bf..40a1245a3e 100644 --- a/bsp/nios_ii/readme_cn.txt +++ b/bsp/nios_ii/readme_cn.txt @@ -26,8 +26,6 @@ kservice.h mem.c mempool.c - module.c - module.h object.c rtm.c scheduler.c diff --git a/bsp/nuvoton_m05x/.config b/bsp/nuvoton_m05x/.config new file mode 100644 index 0000000000..38716c0942 --- /dev/null +++ b/bsp/nuvoton_m05x/.config @@ -0,0 +1,306 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=512 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=512 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_STM32_SDIO is not set + +# +# Test Packages of RealThread +# +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +CONFIG_RT_USING_UART0=y diff --git a/bsp/tm4c129x-dk/Kconfig b/bsp/nuvoton_m05x/Kconfig similarity index 83% rename from bsp/tm4c129x-dk/Kconfig rename to bsp/nuvoton_m05x/Kconfig index e6e03d257d..b6c00e8e2c 100644 --- a/bsp/tm4c129x-dk/Kconfig +++ b/bsp/nuvoton_m05x/Kconfig @@ -18,7 +18,8 @@ config $PKGS_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" + config RT_USING_UART0 - bool "Using RT_USING_UART0" - default y - + bool "Using Uart0" + select RT_USING_SERIAL + default y \ No newline at end of file diff --git a/bsp/nuvoton_m05x/applications/application.c b/bsp/nuvoton_m05x/applications/application.c deleted file mode 100644 index 8495234fb1..0000000000 --- a/bsp/nuvoton_m05x/applications/application.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-11-23 Bright first implementation - */ - -/** - * @addtogroup STM32 - */ -/*@{*/ - -#include - -#include -#include - -#include "led.h" - -/* led thread entry */ -static void led_thread_entry(void* parameter) -{ - while(1) - { - rt_hw_led_on(); - rt_thread_delay(RT_TICK_PER_SECOND); - rt_hw_led_off(); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void rt_init_thread_entry(void* parameter) -{ - rt_thread_t led_thread; - -/* Initialization RT-Thread Components */ -#ifdef RT_USING_COMPONENTS_INIT - rt_components_init(); -#endif - -/* Set finsh device */ -#ifdef RT_USING_FINSH - finsh_set_device(RT_CONSOLE_DEVICE_NAME); -#endif /* RT_USING_FINSH */ - - /* Create led thread */ - led_thread = rt_thread_create("led", - led_thread_entry, RT_NULL, - 128, 20, 20); - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); -} - -int rt_application_init() -{ - rt_thread_t init_thread; - -#if (RT_THREAD_PRIORITY_MAX == 32) - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 512, 8, 20); -#else - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 512, 80, 20); -#endif - if(init_thread != RT_NULL) - rt_thread_startup(init_thread); - - return 0; -} - - -/*@}*/ diff --git a/bsp/tm4c129x-dk/applications/application.c b/bsp/nuvoton_m05x/applications/main.c similarity index 68% rename from bsp/tm4c129x-dk/applications/application.c rename to bsp/nuvoton_m05x/applications/main.c index 671511c36d..72f567b9dd 100644 --- a/bsp/tm4c129x-dk/applications/application.c +++ b/bsp/nuvoton_m05x/applications/main.c @@ -1,5 +1,5 @@ /* - * File : application.c + * File : main.c * This file is part of RT-Thread RTOS * COPYRIGHT (C) 2014, RT-Thread Development Team * @@ -9,13 +9,13 @@ * * Change Logs: * Date Author Notes - * 2014-07-18 ArdaFu the first version for TM4C129X + * 2018-09-01 ZYH first implementation */ -#include -int main(void) +#include + +int main() { - /* user app entry */ + return 0; } - diff --git a/bsp/nuvoton_m05x/applications/startup.c b/bsp/nuvoton_m05x/applications/startup.c deleted file mode 100644 index 619a68315f..0000000000 --- a/bsp/nuvoton_m05x/applications/startup.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-11-23 Bright first implementation - */ - -#include -#include - -#include "board.h" - -/** - * @addtogroup NUVOTON_M05X - */ - -/*@{*/ - -extern int rt_application_init(void); -#ifdef RT_USING_FINSH -extern int finsh_system_init(void); -extern void finsh_set_device(const char* device); -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define M05X_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define M05X_SRAM_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define M05X_SRAM_BEGIN (&__bss_end) -#endif - -/******************************************************************************* -* Function Name : assert_failed -* Description : Reports the name of the source file and the source line number -* where the assert error has occurred. -* Input : - file: pointer to the source file name -* - line: assert error line source number -* Output : None -* Return : None -*******************************************************************************/ -void assert_failed(uint8_t* file, uint32_t line) -{ - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); - - while (1) ; -} - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)M05X_SRAM_BEGIN, (void*)M05X_SRAM_END); -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init application */ - rt_application_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/nuvoton_m05x/drivers/board.c b/bsp/nuvoton_m05x/drivers/board.c index a4a85ffc41..9208aca24d 100644 --- a/bsp/nuvoton_m05x/drivers/board.c +++ b/bsp/nuvoton_m05x/drivers/board.c @@ -102,14 +102,15 @@ void rt_hw_board_init() /* Initial usart deriver, and set console device */ rt_hw_usart_init(); -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)M05X_SRAM_BEGIN, (void *)M05X_SRAM_END); #endif - - /* Call components board initial (use INIT_BOARD_EXPORT()) */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif } /*@}*/ diff --git a/bsp/nuvoton_m05x/drivers/board.h b/bsp/nuvoton_m05x/drivers/board.h index 6c68944025..ebaca6885f 100644 --- a/bsp/nuvoton_m05x/drivers/board.h +++ b/bsp/nuvoton_m05x/drivers/board.h @@ -21,8 +21,18 @@ #define BOARD_PLL_CLOCK 50000000 /* board configuration */ -// Internal SRAM memory size[Kbytes] -// Default: 64 + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define M05X_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define M05X_SRAM_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define M05X_SRAM_BEGIN (&__bss_end) +#endif + #define M05X_SRAM_SIZE 4 #define M05X_SRAM_END (0x20000000 + M05X_SRAM_SIZE * 1024) diff --git a/bsp/nuvoton_m05x/rtconfig.h b/bsp/nuvoton_m05x/rtconfig.h index 7face48d7b..4d5ab6b201 100644 --- a/bsp/nuvoton_m05x/rtconfig.h +++ b/bsp/nuvoton_m05x/rtconfig.h @@ -1,112 +1,270 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +/* RT-Thread Kernel */ -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 -#define IDLE_THREAD_STACK_SIZE 128 -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -//#define RT_DEBUG -//#define RT_DEBUG_INIT 1 -//#define RT_USING_OVERFLOW_CHECK +/* Inter-Thread communication */ -/* Using Hook */ -/* #define RT_USING_HOOK */ - -/* Using Software Timer */ -/* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 - -/* SECTION: IPC */ -/* Using Semaphore*/ #define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ -/* Using Mutex */ -/* #define RT_USING_MUTEX */ +/* Memory Management */ -/* Using Event */ -/* #define RT_USING_EVENT */ - -/* Using MailBox */ -/* #define RT_USING_MAILBOX */ - -/* Using Message Queue */ -/* #define RT_USING_MESSAGEQUEUE */ - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -/* #define RT_USING_MEMPOOL */ - -/* Using Dynamic Heap Management */ +/* RT_USING_MEMPOOL is not set */ +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP -/* Using Small MM */ -#define RT_USING_SMALL_MEM +/* Kernel Device Object */ -// -#define RT_USING_COMPONENTS_INIT - -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL - -/* SECTION: Console options */ +/* RT_USING_DEVICE_OPS is not set */ +/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE -/* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 64 -// -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +/* RT-Thread Components */ +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 512 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ -/* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH -/* configure finsh parameters */ -#define FINSH_THREAD_PRIORITY 25 -#define FINSH_THREAD_STACK_SIZE 512 -#define FINSH_USING_HISTORY 0 -#define FINSH_HISTORY_LINES 1 -/* Using symbol table */ +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 -/* SECTION: libc management */ -//#define RT_USING_LIBC +/* Device virtual file system */ -/* SECTION: device filesystem */ -/* #define RT_USING_DFS */ -//#define RT_USING_DFS_ELMFAT -#define RT_DFS_ELM_WORD_ACCESS -/* Reentrancy (thread safe) of the FatFs module. */ -#define RT_DFS_ELM_REENTRANT -/* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 -/* Maximum sector size to be handled. */ -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +/* RT_USING_DFS is not set */ -#define RT_USING_DFS_ROMFS +/* Device Drivers */ -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +/* RT_USING_I2C is not set */ +/* RT_USING_PIN is not set */ +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_WIFI is not set */ +/* RT_USING_AUDIO is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +/* RT_USING_LIBC is not set */ +/* RT_USING_PTHREADS is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_LOGTRACE is not set */ +/* RT_USING_RYM is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_STM32F4_HAL is not set */ +/* PKG_USING_STM32F4_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ + +/* sample package */ + +/* PKG_USING_SAMPLES is not set */ + +/* example package: hello */ + +/* PKG_USING_HELLO is not set */ + +/* Privated Packages of RealThread */ + +/* PKG_USING_CODEC is not set */ +/* PKG_USING_PLAYER is not set */ +/* PKG_USING_PERSIMMON_SRC is not set */ + +/* Network Utilities */ + +/* PKG_USING_WICED is not set */ +/* PKG_USING_CLOUDSDK is not set */ +/* PKG_USING_COREMARK is not set */ +/* PKG_USING_POWER_MANAGER is not set */ +/* PKG_USING_RT_OTA is not set */ +/* PKG_USING_RDB is not set */ +/* PKG_USING_RTINSIGHT is not set */ +/* PKG_USING_STM32_SDIO is not set */ + +/* Test Packages of RealThread */ + +/* PKG_USING_JERRYSCRIPT_WIN32 is not set */ +/* PKG_USING_JS_PERSIMMON is not set */ +#define RT_USING_UART0 #endif diff --git a/bsp/nuvoton_m487/.config b/bsp/nuvoton_m487/.config new file mode 100644 index 0000000000..a20bd22939 --- /dev/null +++ b/bsp/nuvoton_m487/.config @@ -0,0 +1,328 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +# CONFIG_RT_USING_MESSAGEQUEUE is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +# CONFIG_DFS_USING_WORKDIR is not set +CONFIG_DFS_FILESYSTEMS_MAX=1 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=64 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP210 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=19 +CONFIG_RT_LWIP_PBUF_NUM=0 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=19 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=2920 +CONFIG_RT_LWIP_TCP_WND=2920 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=768 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set + +# +# RT-Thread online packages +# + +# +# system packages +# + +# +# RT-Thread GUI Engine +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_IPERF is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set diff --git a/bsp/nuvoton_m487/Kconfig b/bsp/nuvoton_m487/Kconfig new file mode 100644 index 0000000000..1b46858ab6 --- /dev/null +++ b/bsp/nuvoton_m487/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +source "$BSP_DIR/driver/Kconfig" + diff --git a/bsp/nuvoton_m487/README.md b/bsp/nuvoton_m487/README.md new file mode 100644 index 0000000000..ca6e82c859 --- /dev/null +++ b/bsp/nuvoton_m487/README.md @@ -0,0 +1,66 @@ +# NuMaker-PFM-M487 + +## 1. 简介 + +核心板板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| M487JIDAE | +|CPU| ARM Cortex-M4 | +|主频| 192MHz | +|片内SRAM| 160kB | +|片内Flash| 512kB | +|SPI FLASH| W25Q32 | +|PHY| IP101GR | +|Audio Codec| NAU88L25 | + + +## 2. 编译说明 + +板级包支持MDK4工程生成、GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| MDK4 | 4.73 | +| GCC | GCC 5.4.1 20160919 (release) | + +使用MDK4打开工程需要安装Nu-Link_Keil_Driver + +## 3. 烧写及执行 + +连接好串口，可以使用115200-N-8-1的配置方式连接到设备上。设备使用的串口引脚是：`[Tx:PB13 Rx:PB12]` + +当正确编译产生出rtthread.bin映像文件后，可以使用NU-link或者JLINK下载 + +### 3.1 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0| + +### 4.1 IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| -- | -- | +| PH0 | LED_R | +| PH1 | LED_Y | +| PH2 | LED_G | +| PG15 | KEY2 | +| PF11| KEY3 | + +## 5. 联系人信息 + +维护人：[bluebear233](https://github.com/bluebear233) + +## 6. 参考 + +* 板子[数据手册][1] +* 芯片[数据手册][2] + + [1]: http://www.nuvoton.com/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.00.pdf + [2]: http://www.nuvoton.com/resource-files/TRM_M480_Series_EN_Rev1.01.pdf \ No newline at end of file diff --git a/bsp/nuvoton_m487/SConscript b/bsp/nuvoton_m487/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/nuvoton_m487/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton_m487/SConstruct b/bsp/nuvoton_m487/SConstruct new file mode 100644 index 0000000000..28e4279763 --- /dev/null +++ b/bsp/nuvoton_m487/SConstruct @@ -0,0 +1,35 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-m487.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton_m487/applications/SConscript b/bsp/nuvoton_m487/applications/SConscript new file mode 100644 index 0000000000..9ffdbcd0f9 --- /dev/null +++ b/bsp/nuvoton_m487/applications/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton_m487/applications/main.c b/bsp/nuvoton_m487/applications/main.c new file mode 100644 index 0000000000..01c276cb28 --- /dev/null +++ b/bsp/nuvoton_m487/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +int main(int argc, char** argv) +{ + printf("Hello RT-Thread!\n"); + + return 0; +} diff --git a/bsp/nuvoton_m487/applications/mnt.c b/bsp/nuvoton_m487/applications/mnt.c new file mode 100644 index 0000000000..d528a7424d --- /dev/null +++ b/bsp/nuvoton_m487/applications/mnt.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include + +int mnt_init(void) +{ + return 0; +} diff --git a/bsp/nuvoton_m487/driver/Kconfig b/bsp/nuvoton_m487/driver/Kconfig new file mode 100644 index 0000000000..1a4baf536d --- /dev/null +++ b/bsp/nuvoton_m487/driver/Kconfig @@ -0,0 +1 @@ + diff --git a/bsp/nuvoton_m487/driver/SConscript b/bsp/nuvoton_m487/driver/SConscript new file mode 100644 index 0000000000..4de25c676a --- /dev/null +++ b/bsp/nuvoton_m487/driver/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Split(''' +board.c +drv_uart.c +''') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton_m487/driver/board.c b/bsp/nuvoton_m487/driver/board.c new file mode 100644 index 0000000000..a80024b0b7 --- /dev/null +++ b/bsp/nuvoton_m487/driver/board.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +#include +#include +#include +#include "NuMicro.h" +#include "drv_uart.h" +#include "board.h" + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +extern int __ram_top; +#endif + +/** + * This function will initial Clock tree. + */ +static void clock_init(void) +{ + /* Unlock protected registers */ + SYS_UnlockReg(); + + SystemInit(); + + /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + + /* Enable External XTAL (4~24 MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + + /* Waiting for 12MHz clock ready */ + CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk); + + /* Switch HCLK clock source to HXT */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); + + /* Set core clock as PLL_CLOCK from PLL */ + CLK_SetCoreClock(FREQ_192MHZ); + + /* Set both PCLK0 and PCLK1 as HCLK/4 */ + CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4; + + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +} + +/** + * This function will initial M487 board. + */ +void rt_hw_board_init(void) +{ + clock_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top); +#endif +#endif /* RT_USING_HEAP */ + + rt_hw_uart_init(); + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + NVIC_SetPriorityGrouping(7); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_cpu_reset(void) +{ + SYS_UnlockReg(); + + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} diff --git a/bsp/nuvoton_m487/driver/board.h b/bsp/nuvoton_m487/driver/board.h new file mode 100644 index 0000000000..515ab1bb39 --- /dev/null +++ b/bsp/nuvoton_m487/driver/board.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <8-64> +#define SRAM_SIZE (160) +#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) + +#define RT_UART_485_MODE 1 +#define RT_UART_FLOW_CTS_CTRL 2 +#define RT_UART_FLOW_RTS_CTRL 3 +#define RT_UART_CLEAR_BUF 4 + +void rt_hw_pdma_init(void); +void rt_hw_uart_handle(void); +void rt_hw_sc_init(void); +void rt_hw_usart_init(void); +void rt_hw_uusart_init(void); +void rt_hw_io_init(void); +void phy_error_led(void); + +unsigned char *eth_get_default_mac(void); +void eth_set_mac(const unsigned char * mac); +void wdt_reload(void); +unsigned int get_uid(void); + +#endif /* BOARD_H_ */ diff --git a/bsp/nuvoton_m487/driver/drv_uart.c b/bsp/nuvoton_m487/driver/drv_uart.c new file mode 100644 index 0000000000..a7ab018f8d --- /dev/null +++ b/bsp/nuvoton_m487/driver/drv_uart.c @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + + +#include +#include +#include +#include "NuMicro.h" + +/* Private Define ---------------------------------------------------------------*/ +#define USEING_UART0 //Tx:PB13 Rx:PB12 + +/* Private Typedef --------------------------------------------------------------*/ +struct usart +{ + rt_serial_t dev; + UART_T *usart_base; +}; +typedef struct usart* usart_t; + +/* Private functions ------------------------------------------------------------*/ + + +static rt_err_t usart_gpio_configure(struct rt_serial_device *serial); +static rt_err_t usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t usart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int usart_send(struct rt_serial_device *serial, char c); +static int usart_receive(struct rt_serial_device *serial); +static void rt_hw_uart_register(usart_t uart, UART_T *uart_base, + char *name); +static void uart_isr(usart_t serial); + +/* Private Variables ------------------------------------------------------------*/ +static const struct rt_uart_ops m487_uart_ops = +{ usart_configure, usart_control, usart_send, usart_receive, + RT_NULL }; + +static const struct serial_configure m487_uart_default_config = +RT_SERIAL_CONFIG_DEFAULT; + +#ifdef USEING_UART0 +struct usart uart0; +#endif + +/* Interrupt Handle Funtion ----------------------------------------------------*/ +#ifdef USEING_UART0 +/* 串口0 中断入口 */ +void UART0_IRQHandler(void) +{ + uart_isr(&uart0); +} +#endif + +/** + * 中断处理函数 + */ +static void uart_isr(usart_t serial) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + // 获取中断事件 + uint32_t u32IntSts= uart_base->INTSTS; + + // 接收中断 + if(u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + } + +} + +/** + * 串口端口配置 + */ +static rt_err_t usart_gpio_configure(struct rt_serial_device *serial) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + switch((uint32_t)uart_base) + { + case UART0_BASE: + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk | SYS_GPB_MFPH_PB13MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB12MFP_UART0_RXD | SYS_GPB_MFPH_PB13MFP_UART0_TXD); + break; + + default: + rt_kprintf("unknow uart module\n"); + RT_ASSERT(0); + } + + return RT_EOK; +} + +/** + * 串口配置 + */ +static rt_err_t usart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + uint32_t uart_module = 0; + uint32_t uart_word_len = 0; + uint32_t uart_stop_bit = 0; + uint32_t uart_parity = 0; + IRQn_Type uart_irq_channel = 0; + + switch((uint32_t)uart_base) + { + case UART0_BASE: + uart_module = UART0_MODULE; + uart_irq_channel = UART0_IRQn; + break; + + default: + rt_kprintf("unknow uart module\n"); + RT_ASSERT(0); + } + + /* Enable IP clock */ + CLK_EnableModuleClock(uart_module); + + /* Select IP clock source */ + CLK_SetModuleClock(uart_module, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1)); + + /* check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + /* check word len */ + switch(cfg->data_bits) + { + case DATA_BITS_5: + uart_word_len = UART_WORD_LEN_5; + break; + + case DATA_BITS_6: + uart_word_len = UART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uart_word_len = UART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uart_word_len = UART_WORD_LEN_8; + break; + + default: + rt_kprintf("unsupose data len"); + RT_ASSERT(0); + } + + /* check stop bit */ + switch(cfg->stop_bits) + { + case STOP_BITS_1: + uart_stop_bit = UART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uart_stop_bit = UART_STOP_BIT_2; + break; + + default: + rt_kprintf("unsupose stop bit"); + RT_ASSERT(0); + } + + /* check stop bit */ + switch(cfg->parity) + { + case PARITY_NONE: + uart_parity = UART_PARITY_NONE; + break; + + case PARITY_ODD: + uart_parity = UART_PARITY_ODD; + break; + + case PARITY_EVEN: + uart_parity = UART_PARITY_EVEN; + break; + + default: + rt_kprintf("unsupose parity"); + RT_ASSERT(0); + } + + /* Open uart */ + { + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + if(uart_base == (UART_T*)UART0 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart_base == (UART_T*)UART1 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart_base == (UART_T*)UART2 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart_base == (UART_T*)UART3 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart_base == (UART_T*)UART4 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart_base == (UART_T*)UART5 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Select UART function */ + uart_base->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart_base->LINE = uart_word_len | uart_stop_bit | uart_parity; + + /* Set UART Rx and RTS trigger level */ + uart_base->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(cfg->baud_rate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), cfg->baud_rate); + + if(u32Baud_Div > 0xFFFFul) + { + uart_base->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), cfg->baud_rate)); + } + else + { + uart_base->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + } + + /* config nvic */ + NVIC_EnableIRQ(uart_irq_channel); + + /* config gpio */ + usart_gpio_configure(serial); + + return RT_EOK; +} + +/** + * 串口中断控制 + */ +static rt_err_t usart_control(struct rt_serial_device *serial, + int cmd, void *arg) +{ + rt_err_t result = RT_EOK; + rt_uint32_t flag; + + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + switch ((uint32_t) arg) + { + case RT_DEVICE_FLAG_INT_RX: + flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + UART_DISABLE_INT(uart_base, flag); + break; + case RT_DEVICE_CTRL_SET_INT: + UART_ENABLE_INT(uart_base, flag); + break; + default: + RT_ASSERT(0); + } + break; +// TODO 完善DMA接口 +// case RT_DEVICE_FLAG_DMA_TX: +// USART_DMACmd(dev->usart_base, USART_DMAReq_Tx, ENABLE); +// stm32_uart_tx_dma_configure(dev, RT_TRUE); +// stm32_uart_tx_dma_nvic(dev, RT_TRUE); +// break; + default: + RT_ASSERT(0) + ; + } + + return result; +} + +/** + * 串口发送函数 + */ +static int usart_send(struct rt_serial_device *serial, char c) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + // 等待FIFO 发送 + while(uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk); + + // 发送字符 + uart_base->DAT = c; + + return 1; +} + +/** + * 串口接收函数 + */ +static int usart_receive(struct rt_serial_device *serial) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + // 如果FIFO 为空返回 + if(uart_base->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + { + return -1; + } + + return UART_READ(uart_base); +} + +/** + * @brief 串口设备注册 + * @param uart : UART设备结构体 + * @param uart_base : STM32 UART外设基地址 + * @param name : STM32 UART设备名 + * @param tx_dma_channel : STM32 UART TX的DMA通道基地址(可选) + */ +static void rt_hw_uart_register(usart_t usart, UART_T * uart_base, char *name) +{ + rt_uint32_t flag; + RT_ASSERT(usart != RT_NULL); + RT_ASSERT(uart_base != RT_NULL); + + // 没有定义对应的硬件I2C + if (!(uart_base == UART0 || uart_base == UART1 || uart_base == UART2 + || uart_base == UART3 || uart_base == UART4 || uart_base == UART5)) + { + RT_ASSERT(0); + } + + usart->usart_base = uart_base; + usart->dev.ops = &m487_uart_ops; + usart->dev.config = m487_uart_default_config; + + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + rt_hw_serial_register(&usart->dev, name, + flag, RT_NULL); +} + +/** + * 硬件串口注册 + */ +int rt_hw_uart_init(void) +{ +#ifdef USEING_UART0 + rt_hw_uart_register(&uart0, UART0, "uart0"); +#endif + + return 0; +} \ No newline at end of file diff --git a/bsp/nuvoton_m487/driver/drv_uart.h b/bsp/nuvoton_m487/driver/drv_uart.h new file mode 100644 index 0000000000..9eb0077e2f --- /dev/null +++ b/bsp/nuvoton_m487/driver/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..8742a56991 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000..726d06eb69 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_math.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..d33f8a9b3b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..74c49c67de --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc_V6.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000000..cd13240ce3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..bb89fbba9e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..711dad5517 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..b04aa39053 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm3.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..b4ac4c7b05 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm4.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..dc840ebf22 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm7.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..3b7530ad50 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..652a48af07 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..f474b0e6f3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000000..66bf5c2a72 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc000.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..514dbd81b9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc300.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..8bd18aa318 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/SConscript b/bsp/nuvoton_m487/libraries/CMSIS/SConscript new file mode 100644 index 0000000000..904fca4146 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/SConscript @@ -0,0 +1,16 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +""") + +path = [cwd + '/Include',] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/M480.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/M480.h new file mode 100644 index 0000000000..c185641bec --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/M480.h @@ -0,0 +1,683 @@ +/**************************************************************************//** + * @file M480.h + * @version V1.00 + * @brief M480 peripheral access layer header file. + * This file contains all the peripheral register's definitions, + * bits definitions and memory mapping for NuMicro M480 MCU. + * + * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +/** + \mainpage NuMicro M480 Driver Reference Guide + * + * Introduction + * + * This user manual describes the usage of M480 Series MCU device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Important Notice + * + * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, + * any malfunction or failure of which may cause loss of human life, bodily injury or severe + * property damage. Such applications are deemed, "Insecure Usage". + * + * Insecure usage includes, but is not limited to: equipment for surgical implementation, + * atomic energy control instruments, airplane or spaceship instruments, the control or + * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal + * instruments, all types of safety devices, and other applications intended to support or + * sustain life. + * + * All Insecure Usage shall be made at customer's risk, and in the event that third parties + * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify + * the damages and liabilities thus incurred by Nuvoton. + * + * Please note that all data and specifications are subject to change without notice. All the + * trademarks of products and companies mentioned in this datasheet belong to their respective + * owners. + * + * Copyright Notice + * + * Copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + */ +#ifndef __M480_H__ +#define __M480_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/** + * @details Interrupt Number Definition. + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + + /****** M480 Specific Interrupt Numbers ********************************************************/ + + BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ + IRC_IRQn = 1, /*!< Internal RC Interrupt */ + PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ + RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ + CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ + GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ + EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ + EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ + EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ + EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ + EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ + EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ + TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ + UART0_IRQn = 36, /*!< UART 0 Interrupt */ + UART1_IRQn = 37, /*!< UART 1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ + PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + ADC0_IRQn = 42, /*!< ADC0 Interrupt */ + ADC1_IRQn = 43, /*!< ADC1 Interrupt */ + ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ + ADC2_IRQn = 46, /*!< ADC2 Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 Interrupt */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + UART3_IRQn = 49, /*!< UART3 Interrupt */ + SPI1_IRQn = 51, /*!< SPI1 Interrupt */ + SPI2_IRQn = 52, /*!< SPI2 Interrupt */ + USBD_IRQn = 53, /*!< USB device Interrupt */ + USBH_IRQn = 54, /*!< USB host Interrupt */ + USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ + CAN0_IRQn = 56, /*!< CAN0 Interrupt */ + CAN1_IRQn = 57, /*!< CAN1 Interrupt */ + SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ + SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ + SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ + SPI3_IRQn = 62, /*!< SPI3 Interrupt */ + EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */ + EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */ + SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ + USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ + I2S0_IRQn = 68, /*!< I2S0 Interrupt */ + OPA_IRQn = 70, /*!< OPA Interrupt */ + CRPT_IRQn = 71, /*!< CRPT Interrupt */ + GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ + EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ + UART4_IRQn = 74, /*!< UART4 Interrupt */ + UART5_IRQn = 75, /*!< UART5 Interrupt */ + USCI0_IRQn = 76, /*!< USCI0 Interrupt */ + USCI1_IRQn = 77, /*!< USCI1 Interrupt */ + BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ + BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ + SPIM_IRQn = 80, /*!< SPIM Interrupt */ + I2C2_IRQn = 82, /*!< I2C2 Interrupt */ + QEI0_IRQn = 84, /*!< QEI0 Interrupt */ + QEI1_IRQn = 85, /*!< QEI1 Interrupt */ + ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ + ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ + GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ + EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ + SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ + HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ + USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ +} +IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1UL /*!< MPU present or not */ +#ifdef __FPU_PRESENT +#undef __FPU_PRESENT +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#else +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#endif + +/*@}*/ /* end of group CMSIS_Device */ + + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_M480.h" /* System include file */ +#include + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Register definitions */ +/******************************************************************************/ + +#include "sys_reg.h" +#include "clk_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "pdma_reg.h" +#include "timer_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "rtc_reg.h" +#include "epwm_reg.h" +#include "bpwm_reg.h" +#include "qei_reg.h" +#include "ecap_reg.h" +#include "uart_reg.h" +#include "emac_reg.h" +#include "sc_reg.h" +#include "i2s_reg.h" +#include "spi_reg.h" +#include "qspi_reg.h" +#include "spim_reg.h" +#include "i2c_reg.h" +#include "uuart_reg.h" +#include "uspi_reg.h" +#include "ui2c_reg.h" +#include "can_reg.h" +#include "sdh_reg.h" +#include "ebi_reg.h" +#include "usbd_reg.h" +#include "hsusbd_reg.h" +#include "usbh_reg.h" +#include "hsusbh_reg.h" +#include "otg_reg.h" +#include "hsotg_reg.h" +#include "crc_reg.h" +#include "crypto_reg.h" +#include "eadc_reg.h" +#include "dac_reg.h" +#include "acmp_reg.h" +#include "opa_reg.h" + + +/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base + Memory Mapped Structure for Peripherals + @{ + */ +/* Peripheral and SRAM base address */ +#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ +#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */ +#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */ + +/*!< AHB peripherals */ +#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) +#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) +#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) +#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) +#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL) +#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) +#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) +#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) +#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) +#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL) +#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL) +#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) +#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) +#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) +#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) +#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) +#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL) + +/*!< APB2 peripherals */ +#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) +#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) +#define OPA_BASE (APBPERIPH_BASE + 0x06000UL) +#define I2S_BASE (APBPERIPH_BASE + 0x08000UL) +#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL) +#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL) +#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) +#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) +#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) +#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART2_BASE (APBPERIPH_BASE + 0x32000UL) +#define UART4_BASE (APBPERIPH_BASE + 0x34000UL) +#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) +#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) +#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) +#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) +#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) + + +/*!< APB1 peripherals */ +#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) +#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) +#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) +#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) +#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) +#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL) +#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL) +#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL) +#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) +#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) +#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) +#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) +#define UART3_BASE (APBPERIPH_BASE + 0x33000UL) +#define UART5_BASE (APBPERIPH_BASE + 0x35000UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) +#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL) +#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) +#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) +#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) +#define CRPT_BASE (0x50080000UL) +#define SPIM_BASE (0x40007000UL) + +#define SC0_BASE (APBPERIPH_BASE + 0x50000UL) +#define SC1_BASE (APBPERIPH_BASE + 0x51000UL) +#define SC2_BASE (APBPERIPH_BASE + 0x52000UL) +#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) +#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL) +#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL) + +/*@}*/ /* end of group PERIPHERAL_MEM_MAP */ + + +/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer + The Declaration of Peripherals + @{ + */ + +#define SYS ((SYS_T *) SYS_BASE) +#define CLK ((CLK_T *) CLK_BASE) +#define NMI ((NMI_T *) NMI_BASE) +#define PA ((GPIO_T *) GPIOA_BASE) +#define PB ((GPIO_T *) GPIOB_BASE) +#define PC ((GPIO_T *) GPIOC_BASE) +#define PD ((GPIO_T *) GPIOD_BASE) +#define PE ((GPIO_T *) GPIOE_BASE) +#define PF ((GPIO_T *) GPIOF_BASE) +#define PG ((GPIO_T *) GPIOG_BASE) +#define PH ((GPIO_T *) GPIOH_BASE) +#define GPA ((GPIO_T *) GPIOA_BASE) +#define GPB ((GPIO_T *) GPIOB_BASE) +#define GPC ((GPIO_T *) GPIOC_BASE) +#define GPD ((GPIO_T *) GPIOD_BASE) +#define GPE ((GPIO_T *) GPIOE_BASE) +#define GPF ((GPIO_T *) GPIOF_BASE) +#define GPG ((GPIO_T *) GPIOG_BASE) +#define GPH ((GPIO_T *) GPIOH_BASE) +#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) +#define PDMA ((PDMA_T *) PDMA_BASE) +#define USBH ((USBH_T *) USBH_BASE) +#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) +#define EMAC ((EMAC_T *) EMAC_BASE) +#define FMC ((FMC_T *) FMC_BASE) +#define SDH0 ((SDH_T *) SDH0_BASE) +#define SDH1 ((SDH_T *) SDH1_BASE) +#define EBI ((EBI_T *) EBI_BASE) +#define CRC ((CRC_T *) CRC_BASE) +#define TAMPER ((TAMPER_T *) TAMPER_BASE) + +#define WDT ((WDT_T *) WDT_BASE) +#define WWDT ((WWDT_T *) WWDT_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define EADC ((EADC_T *) EADC_BASE) +#define ACMP01 ((ACMP_T *) ACMP01_BASE) + +#define I2S0 ((I2S_T *) I2S_BASE) +#define USBD ((USBD_T *) USBD_BASE) +#define OTG ((OTG_T *) OTG_BASE) +#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) +#define HSOTG ((HSOTG_T *) HSOTG_BASE) +#define TIMER0 ((TIMER_T *) TIMER0_BASE) +#define TIMER1 ((TIMER_T *) TIMER1_BASE) +#define TIMER2 ((TIMER_T *) TIMER2_BASE) +#define TIMER3 ((TIMER_T *) TIMER3_BASE) +#define EPWM0 ((EPWM_T *) EPWM0_BASE) +#define EPWM1 ((EPWM_T *) EPWM1_BASE) +#define BPWM0 ((BPWM_T *) BPWM0_BASE) +#define BPWM1 ((BPWM_T *) BPWM1_BASE) +#define ECAP0 ((ECAP_T *) ECAP0_BASE) +#define ECAP1 ((ECAP_T *) ECAP1_BASE) +#define QEI0 ((QEI_T *) QEI0_BASE) +#define QEI1 ((QEI_T *) QEI1_BASE) +#define QSPI0 ((QSPI_T *) QSPI0_BASE) +#define SPI0 ((SPI_T *) SPI0_BASE) +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define UART2 ((UART_T *) UART2_BASE) +#define UART3 ((UART_T *) UART3_BASE) +#define UART4 ((UART_T *) UART4_BASE) +#define UART5 ((UART_T *) UART5_BASE) +#define I2C0 ((I2C_T *) I2C0_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) +#define SC0 ((SC_T *) SC0_BASE) +#define SC1 ((SC_T *) SC1_BASE) +#define SC2 ((SC_T *) SC2_BASE) +#define CAN0 ((CAN_T *) CAN0_BASE) +#define CAN1 ((CAN_T *) CAN1_BASE) +#define CRPT ((CRPT_T *) CRPT_BASE) +#define SPIM ((volatile SPIM_T *) SPIM_BASE) +#define DAC0 ((DAC_T *) DAC0_BASE) +#define DAC1 ((DAC_T *) DAC1_BASE) +#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ +#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */ +#define OPA ((OPA_T *) OPA_BASE) +#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ +#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ +#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ +#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */ + +/*@}*/ /* end of group ERIPHERAL_DECLARATION */ + +/** @addtogroup IO_ROUTINE I/O Routines + The Declaration of I/O Routines + @{ + */ + +typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type +typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type +typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) (*((volatile unsigned char *)(port))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) (*((volatile unsigned char *)(port))) + + +/*@}*/ /* end of group IO_ROUTINE */ + +/******************************************************************************/ +/* Legacy Constants */ +/******************************************************************************/ +/** @addtogroup Legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + +#ifndef NULL +#define NULL (0) ///< NULL pointer +#endif + +#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value +#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value + +#define ENABLE (1UL) ///< Enable, define to use in API parameters +#define DISABLE (0UL) ///< Disable, define to use in API parameters + +/* Define one bit mask */ +#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer +#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer +#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer +#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer +#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer +#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer +#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer +#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer +#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer +#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer +#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer +#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer +#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer +#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer +#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer +#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer +#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer +#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer +#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer +#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer +#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer +#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer +#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer +#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer +#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer +#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer +#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer +#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer +#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer +#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer +#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer +#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer +#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer +#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer +#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer + +#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group Legacy_Constants */ + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "sys.h" +#include "clk.h" + +#include "acmp.h" +#include "dac.h" +#include "emac.h" +#include "uart.h" +#include "usci_spi.h" +#include "gpio.h" +#include "ecap.h" +#include "qei.h" +#include "timer.h" +#include "timer_pwm.h" +#include "pdma.h" +#include "crypto.h" +#include "fmc.h" +#include "spim.h" +#include "i2c.h" +#include "i2s.h" +#include "epwm.h" +#include "eadc.h" +#include "bpwm.h" +#include "wdt.h" +#include "wwdt.h" +#include "opa.h" +#include "crc.h" +#include "ebi.h" +#include "usci_i2c.h" +#include "scuart.h" +#include "sc.h" +#include "spi.h" +#include "qspi.h" +#include "can.h" +#include "rtc.h" +#include "usci_uart.h" +#include "sdh.h" +#include "usbd.h" +#include "hsusbd.h" +#include "otg.h" +#include "hsotg.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* __M480_H__ */ + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h new file mode 100644 index 0000000000..4566f13ab4 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h @@ -0,0 +1,15 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "M480.h" + +#endif /* __NUMICRO_H__ */ + + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h new file mode 100644 index 0000000000..aa68daf6a5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h @@ -0,0 +1,239 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ACMP Analog Comparator Controller(ACMP) + Memory Mapped Structure for ACMP Controller +@{ */ + +typedef struct +{ + + + /** + * @var ACMP_T::CTL + * Offset: 0x00~0x04 Analog Comparator 0/1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator x Disabled. + * | | |1 = Comparator x Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator x interrupt Disabled. + * | | |1 = Comparator x interrupt Enabled + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator x output inverse Disabled. + * | | |1 = Comparator x output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMPx_N pin. + * | | |01 = Internal comparator reference voltage (CRV). + * | | |10 = Band-gap voltage. + * | | |11 = DAC output. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMPx_P0. + * | | |01 = Input from ACMPx_P1. + * | | |10 = Input from ACMPx_P2. + * | | |11 = Input from ACMPx_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIFx will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output. + * | | |1 = Comparator x output to ACMPx_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMPx output is sampled 1 consecutive PCLK. + * | | |010 = ACMPx output is sampled 2 consecutive PCLKs. + * | | |011 = ACMPx output is sampled 4 consecutive PCLKs. + * | | |100 = ACMPx output is sampled 8 consecutive PCLKs. + * | | |101 = ACMPx output is sampled 16 consecutive PCLKs. + * | | |110 = ACMPx output is sampled 32 consecutive PCLKs. + * | | |111 = ACMPx output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[25:24] |HYSSEL |Hysteresis Mode Selection + * | | |00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Propagation Delay Mode Selection + * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. + * | | |01 = Max propagation delay is 2uS, operation current is 3uA. + * | | |10 = Max propagation delay is 600nS, operation current is 10uA. + * | | |11 = Max propagation delay is 200nS, operation current is 75uA. + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) + * | | |is detected on comparator 0 output. + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) + * | | |is detected on comparator 1 output. + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software. + * | | |Cleared when the comparator 1 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CRVCTL |Comparator Reference Voltage Setting + * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). + * |[6] |CRVSSEL |CRV Source Voltage Selection + * | | |0 = VDDA is selected as CRV source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. + */ + __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller +@{ */ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ +#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ + +#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ +#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ACMP_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/bpwm_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/bpwm_reg.h new file mode 100644 index 0000000000..14df066f71 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/bpwm_reg.h @@ -0,0 +1,1834 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) + Memory Mapped Structure for BPWM Controller +@{ */ + +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + +typedef struct +{ + + + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[10]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[55]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE14[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE15[5]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller +@{ */ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ +#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ + +#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ +#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ + +#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ +#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ + +#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ +#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ + +#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ +#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ +#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ +#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ +#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ +#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ +#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ +#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ +#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ +#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ +#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ +#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ +#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ +#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ +#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ +#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ +#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ +#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ +#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ +#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ +#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ +#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ +#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ +#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __BPWM_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/can_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/can_reg.h new file mode 100644 index 0000000000..379e3b2cb8 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/can_reg.h @@ -0,0 +1,758 @@ +/**************************************************************************//** + * @file can_reg.h + * @version V1.00 + * @brief CAN register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CAN_REG_H__ +#define __CAN_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CAN Controller Area Network Controller(CAN) + Memory Mapped Structure for CAN Controller +@{ */ + + +typedef struct +{ + + /** + * @var CAN_IF_T::CREQ + * Offset: 0x20, 0x80 IFn Command Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MessageNumber|Message Number + * | | |0x01-0x20: Valid Message Number, the Message Object in the Message + * | | |RAM is selected for data transfer. + * | | |0x00: Not a valid Message Number, interpreted as 0x20. + * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. + * |[15] |Busy |Busy Flag + * | | |0 = Read/write action has finished. + * | | |1 = Writing to the IFn Command Request Register is in progress + * | | |This bit can only be read by the software. + * @var CAN_IF_T::CMASK + * Offset: 0x24, 0x84 IFn Command Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DAT_B |Access Data Bytes [7:4] + * | | |Write Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. + * |[1] |DAT_A |Access Data Bytes [3:0] + * | | |Write Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. + * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation + * | | |0 = TxRqst bit unchanged. + * | | |1 = Set TxRqst bit. + * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. + * | | |Access New Data Bit when Read Operation. + * | | |0 = NewDat bit remains unchanged. + * | | |1 = Clear NewDat bit in the Message Object. + * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat + * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. + * |[3] |ClrIntPnd |Clear Interrupt Pending Bit + * | | |Write Operation: + * | | |When writing to a Message Object, this bit is ignored. + * | | |Read Operation: + * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. + * | | |1 = Clear IntPnd bit in the Message Object. + * |[4] |Control |Control Access Control Bits + * | | |Write Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to Message Object. + * | | |Read Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to IFn Message Buffer Register. + * |[5] |Arb |Access Arbitration Bits + * | | |Write Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object. + * | | |Read Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. + * |[6] |Mask |Access Mask Bits + * | | |Write Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. + * | | |Read Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. + * |[7] |WR_RD |Write / Read Mode + * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. + * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. + * @var CAN_IF_T::MASK1 + * Offset: 0x28, 0x88 IFn Mask 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |Msk |Identifier Mask 15-0 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * @var CAN_IF_T::MASK2 + * Offset: 0x2C, 0x8C IFn Mask 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |Msk |Identifier Mask 28-16 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * |[14] |MDir |Mask Message Direction + * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. + * | | |1 = The message direction bit (Dir) is used for acceptance filtering. + * |[15] |MXtd |Mask Extended Identifier + * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. + * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. + * | | |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]) + * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. + * @var CAN_IF_T::ARB1 + * Offset: 0x30, 0x90 IFn Arbitration 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ID |Message Identifier 15-0 + * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) + * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) + * @var CAN_IF_T::ARB2 + * Offset: 0x34, 0x94 IFn Arbitration 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |ID |Message Identifier 28-16 + * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) + * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) + * |[13] |Dir |Message Direction + * | | |0 = Direction is receive. + * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted + * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + * | | |1 = Direction is transmit. + * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame + * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). + * |[14] |Xtd |Extended Identifier + * | | |0 = The 11-bit (standard) Identifier will be used for this Message Object. + * | | |1 = The 29-bit (extended) Identifier will be used for this Message Object. + * |[15] |MsgVal |Message Valid + * | | |0 = The Message Object is ignored by the Message Handler. + * | | |1 = The Message Object is configured and should be considered by the Message Handler. + * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]) + * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. + * @var CAN_IF_T::MCON + * Offset: 0x38, 0x98 IFn Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DLC |Data Length Code + * | | |0-8: Data Frame has 0-8 data bytes. + * | | |9-15: Data Frame has 8 data bytes + * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes + * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. + * | | |Data(0): 1st data byte of a CAN Data Frame + * | | |Data(1): 2nd data byte of a CAN Data Frame + * | | |Data(2): 3rd data byte of a CAN Data Frame + * | | |Data(3): 4th data byte of a CAN Data Frame + * | | |Data(4): 5th data byte of a CAN Data Frame + * | | |Data(5): 6th data byte of a CAN Data Frame + * | | |Data(6): 7th data byte of a CAN Data Frame + * | | |Data(7): 8th data byte of a CAN Data Frame + * | | |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last + * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object + * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. + * |[7] |EoB |End of Buffer + * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. + * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. + * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer + * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one + * |[8] |TxRqst |Transmit Request + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * |[9] |RmtEn |Remote Enable Bit + * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. + * | | |1 = At the reception of a Remote Frame, TxRqst is set. + * |[10] |RxIE |Receive Interrupt Enable Bit + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. + * | | |1 = IntPnd will be set after a successful reception of a frame. + * |[11] |TxIE |Transmit Interrupt Enable Bit + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. + * | | |1 = IntPnd will be set after a successful transmission of a frame. + * |[12] |UMask |Use Acceptance Mask + * | | |0 = Mask ignored. + * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. + * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. + * |[13] |IntPnd |Interrupt Pending + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt + * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). + * | | |0 = No message lost since last time this bit was reset by the CPU. + * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. + * |[15] |NewDat |New Data + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_IF_T::DAT_A1 + * Offset: 0x3C, 0x9C IFn Data A1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_0_ |Data Byte 0 + * | | |1st data byte of a CAN Data Frame + * |[15:8] |Data_1_ |Data Byte 1 + * | | |2nd data byte of a CAN Data Frame + * @var CAN_IF_T::DAT_A2 + * Offset: 0x40, 0xA0 IFn Data A2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_2_ |Data Byte 2 + * | | |3rd data byte of CAN Data Frame + * |[15:8] |Data_3_ |Data Byte 3 + * | | |4th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B1 + * Offset: 0x44, 0xA4 IFn Data B1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_4_ |Data Byte 4 + * | | |5th data byte of CAN Data Frame + * |[15:8] |Data_5_ |Data Byte 5 + * | | |6th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B2 + * Offset: 0x48, 0xA8 IFn Data B2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_6_ |Data Byte 6 + * | | |7th data byte of CAN Data Frame. + * |[15:8] |Data_7_ |Data Byte 7 + * | | |8th data byte of CAN Data Frame. + */ + __IO uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */ + __IO uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */ + __IO uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */ + __IO uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */ + __IO uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */ + __IO uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */ + __IO uint32_t MCON; /*!< [0x0038] IFn Message Control Register */ + __IO uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */ + __IO uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */ + __IO uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */ + __IO uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[13]; + /// @endcond //HIDDEN_SYMBOLS +} CAN_IF_T; + + +typedef struct +{ + + + /** + * @var CAN_T::CON + * Offset: 0x00 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |Init |Init Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * |[1] |IE |Module Interrupt Enable Bit + * | | |0 = Function interrupt is Disabled. + * | | |1 = Function interrupt is Enabled. + * |[2] |SIE |Status Change Interrupt Enable Bit + * | | |0 = Disabled - No Status Change Interrupt will be generated. + * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. + * |[3] |EIE |Error Interrupt Enable Bit + * | | |0 = Disabled - No Error Status Interrupt will be generated. + * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. + * |[5] |DAR |Automatic Re-transmission Disable Bit + * | | |0 = Automatic Retransmission of disturbed messages Enabled. + * | | |1 = Automatic Retransmission Disabled. + * |[6] |CCE |Configuration Change Enable Bit + * | | |0 = No write access to the Bit Timing Register. + * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). + * |[7] |Test |Test Mode Enable Bit + * | | |0 = Normal Operation. + * | | |1 = Test Mode. + * @var CAN_T::STATUS + * Offset: 0x04 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code (Type of the Last Error to Occur on the CAN Bus) + * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus + * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error + * | | |The unused code '7' may be written by the CPU to check for updates + * | | |The Error! Reference source not found + * | | |describes the error code. + * |[3] |TxOK |Transmitted a Message Successfully + * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted + * | | |This bit is never reset by the CAN Core. + * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. + * |[4] |RxOK |Received a Message Successfully + * | | |0 = No message has been successfully received since this bit was last reset by the CPU + * | | |This bit is never reset by the CAN Core. + * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). + * |[5] |EPass |Error Passive (Read Only) + * | | |0 = The CAN Core is error active. + * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. + * |[6] |EWarn |Error Warning Status (Read Only) + * | | |0 = Both error counters are below the error warning limit of 96. + * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. + * |[7] |BOff |Bus-off Status (Read Only) + * | | |0 = The CAN module is not in bus-off state. + * | | |1 = The CAN module is in bus-off state. + * @var CAN_T::ERR + * Offset: 0x08 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter. Values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level. + * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. + * @var CAN_T::BTIME + * Offset: 0x0C Bit Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BRP |Baud Rate Prescaler + * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta + * | | |The bit time is built up from a multiple of this quanta + * | | |Valid values for the Baud Rate Prescaler are [0...63] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[7:6] |SJW |(Re)Synchronization Jump Width + * | | |0x0-0x3: Valid programmed values are [0...3] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[11:8] |TSeg1 |Time Segment Before the Sample Point Minus Sync_Seg + * | | |0x01-0x0F: valid values for TSeg1 are [1...15] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. + * |[14:12] |TSeg2 |Time Segment After Sample Point + * | | |0x0-0x7: Valid values for TSeg2 are [0...7] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CAN_T::IIDR + * Offset: 0x10 Interrupt Identifier Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntId |Interrupt Identifier (Indicates the Source of the Interrupt) + * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order + * | | |An interrupt remains pending until the application software has cleared it + * | | |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active + * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. + * | | |The Status Interrupt has the highest priority + * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. + * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]) + * | | |The Status Interrupt is cleared by reading the Status Register. + * @var CAN_T::TEST + * Offset: 0x14 Test Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |Basic |Basic Mode + * | | |0 = Basic Mode Disabled. + * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + * |[3] |Silent |Silent Mode + * | | |0 = Normal operation. + * | | |1 = The module is in Silent Mode. + * |[4] |LBack |Loop Back Mode Enable Bit + * | | |0 = Loop Back Mode is Disabled. + * | | |1 = Loop Back Mode is Enabled. + * |[6:5] |Tx |Tx[1:0]: Control of CAN_TX Pin + * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. + * | | |01 = Sample Point can be monitored at CAN_TX pin. + * | | |10 = CAN_TX pin drives a dominant ('0') value. + * | | |11 = CAN_TX pin drives a recessive ('1') value. + * |[7] |Rx |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) + * | | |0 = The CAN bus is dominant (CAN_RX = '0'). + * | | |1 = The CAN bus is recessive (CAN_RX = '1'). + * @var CAN_T::BRPE + * Offset: 0x18 Baud Rate Prescaler Extension Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension + * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023 + * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. + * @var CAN_T::TXREQ1 + * Offset: 0x100 Transmission Request Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::TXREQ2 + * Offset: 0x104 Transmission Request Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::NDAT1 + * Offset: 0x120 New Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData16_1|New Data Bits 16-1 (of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::NDAT2 + * Offset: 0x124 New Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData32_17|New Data Bits 32-17 (of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::IPND1 + * Offset: 0x140 Interrupt Pending Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::IPND2 + * Offset: 0x144 Interrupt Pending Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::MVLD1 + * Offset: 0x160 Message Valid Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex + * | | |CAN_MVLD1[0] means Message object No.1 is valid or not + * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. + * @var CAN_T::MVLD2 + * Offset: 0x164 Message Valid Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not + * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. + * @var CAN_T::WU_EN + * Offset: 0x168 Wake-up Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_EN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. + * @var CAN_T::WU_STATUS + * Offset: 0x16C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_STS |Wake-up Status + * | | |0 = No wake-up event occurred. + * | | |1 = Wake-up event occurred. + * | | |Note: This bit can be cleared by writing '0'. + */ + __IO uint32_t CON; /*!< [0x0000] Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] Status Register */ + __I uint32_t ERR; /*!< [0x0008] Error Counter Register */ + __IO uint32_t BTIME; /*!< [0x000c] Bit Timing Register */ + __I uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */ + __IO uint32_t TEST; /*!< [0x0014] Test Register */ + __IO uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO CAN_IF_T IF[2]; + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */ + __I uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */ + __I uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */ + __I uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */ + __I uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */ + __IO uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */ + __IO uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */ + +} CAN_T; + +/** + @addtogroup CAN_CONST CAN Bit Field Definition + Constant Definitions for CAN Controller +@{ */ + +#define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */ +#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */ + +#define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */ +#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ + +#define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */ +#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ + +#define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */ +#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ + +#define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */ +#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ + +#define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */ +#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ + +#define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */ +#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */ + +#define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */ +#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +#define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */ +#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */ + +#define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */ +#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */ + +#define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */ +#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */ + +#define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */ +#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */ + +#define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */ +#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */ + +#define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */ +#define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ + +#define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */ +#define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ + +#define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */ +#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ + +#define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */ +#define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ + +#define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */ +#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ + +#define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */ +#define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */ + +#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */ +#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */ + +#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */ +#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */ + +#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +#define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */ +#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */ + +#define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */ +#define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */ + +#define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */ +#define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */ + +#define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */ + +#define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */ +#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */ + +#define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */ +#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */ + +#define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */ +#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */ +#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */ + +#define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */ +#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */ + +#define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */ +#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */ + +#define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */ +#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */ + +#define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */ +#define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */ + +#define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */ +#define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */ + +#define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */ +#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */ + +#define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */ +#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */ + +#define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ + +#define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */ +#define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ + +#define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */ +#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */ + +#define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */ +#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */ + +#define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */ +#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */ + +#define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */ +#define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ + +#define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */ +#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */ + +#define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */ +#define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */ + +#define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */ +#define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */ + +#define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */ +#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */ + +#define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */ +#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */ + +#define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */ +#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */ + +#define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */ +#define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */ + +#define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */ +#define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */ + +#define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */ +#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */ + +#define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */ +#define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */ + +#define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */ +#define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */ + +#define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */ +#define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */ + +#define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */ +#define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */ + +#define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */ +#define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */ + +#define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */ +#define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */ + +#define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */ +#define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */ + +#define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */ +#define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */ + +#define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */ +#define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */ + +#define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */ +#define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */ + +#define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */ +#define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */ + +#define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */ +#define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */ + +#define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */ +#define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */ + +#define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */ +#define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */ + +#define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */ +#define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */ + +#define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */ +#define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */ + +#define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */ +#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ + +#define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ +#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ + +/**@}*/ /* CAN_CONST */ +/**@}*/ /* end of CAN register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CAN_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/clk_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/clk_reg.h new file mode 100644 index 0000000000..3d613b216b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/clk_reg.h @@ -0,0 +1,1606 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller +@{ */ + +typedef struct +{ + + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26] + * | | |When the default clock source is from HXT, this bit is set to 1 automatically. + * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) + * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). + * | | |0 = Clock cycles delay Disabled. + * | | |1 = Clock cycles delay Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. + * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. + * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. + * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally + * | | |If gain control is enabled, crystal will consume more power than gain control off. + * | | |00 = HXT frequency is lower than from 8 MHz. + * | | |01 = HXT frequency is from 8 MHz to 12 MHz. + * | | |10 = HXT frequency is from 12 MHz to 16 MHz. + * | | |11 = HXT frequency is higher than 16 MHz. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Select INV type. + * | | |1 = Select GM type. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = HXT Crystal TURBO mode disabled. + * | | |1 = HXT Crystal TURBO mode enabled. + * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) + * | | |00 = HIRC stable count is 64 clocks. + * | | |01 = HIRC stable count is 24 clocks. + * | | |others = Reserved. + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit + * | | |0 = PDMA peripheral clock Disabled. + * | | |1 = PDMA peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit + * | | |0 = Ethernet Controller engine clock Disabled. + * | | |1 = Ethernet Controller engine clock Enabled. + * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit + * | | |0 = SD0 engine clock Disabled. + * | | |1 = SD0 engine clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit + * | | |0 = HSUSB device controller's clock Disabled. + * | | |1 = HSUSB device controller's clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit + * | | |0 = SPIM controller clock Disabled. + * | | |1 = SPIM controller clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit + * | | |0 = USB HOST peripheral clock Disabled. + * | | |1 = USB HOST peripheral clock Enabled. + * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit + * | | |0 = SD1 engine clock Disabled. + * | | |1 = SD1 engine clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer clock Disabled. + * | | |1 = Watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only + * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) + * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[10] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[14] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[15] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[19] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[20] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[21] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[24] |CAN0CKEN |CAN0 Clock Enable Bit + * | | |0 = CAN0 clock Disabled. + * | | |1 = CAN0 clock Enabled. + * |[25] |CAN1CKEN |CAN1 Clock Enable Bit + * | | |0 = CAN1 clock Disabled. + * | | |1 = CAN1 clock Enabled. + * |[26] |OTGCKEN |USB OTG Clock Enable Bit + * | | |0 = USB OTG clock Disabled. + * | | |1 = USB OTG clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB Device clock Disabled. + * | | |1 = USB Device clock Enabled. + * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * |[29] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 Clock Disabled. + * | | |1 = I2S0 Clock Enabled. + * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit + * | | |0 = HSUSB OTG clock Disabled. + * | | |1 = HSUSB OTG clock Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |SC0 Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[1] |SC1CKEN |SC1 Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2CKEN |SC2 Clock Enable Bit + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * |[6] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[9] |USCI1CKEN |USCI1 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[22] |QEI0CKEN |QEI0 Clock Enable Bit + * | | |0 = QEI0 clock Disabled. + * | | |1 = QEI0 clock Enabled. + * |[23] |QEI1CKEN |QEI1 Clock Enable Bit + * | | |0 = QEI1 clock Disabled. + * | | |1 = QEI1 clock Enabled. + * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit + * | | |0 = OPA clock Disabled. + * | | |1 = OPA clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset + * | | |Therefore the default value is either 000b or 111b. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from PLL. + * | | |011 = Clock source from LIRC. + * | | |111 = Clock source from HIRC. + * | | |Other = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Note: if SysTick clock source is not from HCLK (i.e + * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[25:24] |UART0SEL |UART0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART1SEL |UART1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPWM0SEL |EPWM0 Clock Source Selection + * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[1] |EPWM1SEL |EPWM1 Clock Source Selection + * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |SPI1SEL |SPI1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[11:10] |SPI2SEL |SPI2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |SPI3SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SC1SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SC2SEL |SC2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |RTCSEL |RTC Clock Source Selection + * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * |[17:16] |I2S0SEL |I2S0 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from PCLK. + * | | |11 = Clock source from HIRC clock. + * |[25:24] |UART2SEL |UART2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART3SEL |UART3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |UART4SEL |UART4 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |UART5SEL |UART5 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock + * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source + * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). + * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). + * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source + * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1). + * @var CLK_T::CLKDIV3 + * Offset: 0x2C Clock Divider Number Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK + * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1). + * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source + * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * @var CLK_T::PCLKDIV + * Offset: 0x34 APB Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |APB0DIV |APB0 Clock Divider + * | | |APB0 clock can be divided from HCLK + * | | |000: PCLK0 = HCLK. + * | | |001: PCLK0 = 1/2 HCLK. + * | | |010: PCLK0 = 1/4 HCLK. + * | | |011: PCLK0 = 1/8 HCLK. + * | | |100: PCLK0 = 1/16 HCLK. + * | | |Others: Reserved. + * |[6:4] |APB1DIV |APB1 Clock Divider + * | | |APB1 clock can be divided from HCLK + * | | |000: PCLK1 = HCLK. + * | | |001: PCLK1 = 1/2 HCLK. + * | | |010: PCLK1 = 1/4 HCLK. + * | | |011: PCLK1 = 1/8 HCLK. + * | | |100: PCLK1 = 1/16 HCLK. + * | | |Others: Reserved. + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |0 = PLL is in normal mode. + * | | |1 = PLL is in Power-down mode (default). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect) + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). + * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[28] |BANDSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL low band frequency select. (FVCO range is 200MHz ~ 400MHZ) + * | | |1 = PLL high band frequency select. (FVCO range is 400MHz ~ 500MHZ) + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * | | |Note: This bit is read only. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source + * | | |If switch target clock is stable, this bit will be set to 0 + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is + * | | |Fout = Fin/2(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value + * | | |The bits define the maximum value of frequency range detector window. + * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value + * | | |The bits define the minimum value of frequency range detector window. + * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Power-down mode is selected. (PD) + * | | |001 = Low leakage Power-down mode is selected (LLPD). + * | | |010 =Fast wake-up Power-down mode is selected (FWPD). + * | | |011 = Reserved. + * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention). + * | | |101 = Standby Power-down mode 1 is selected (SPD1). + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |111 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Wake-up timer disable at DPD/SPD mode. + * | | |1 = Wake-up timer enabled at DPD/SPD mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. + * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms). + * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms). + * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms). + * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). + * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). + * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). + * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). + * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = ACMP wake-up disable at Standby Power-down mode. + * | | |1 = ACMP wake-up enabled at Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0) + * | | |This flag is cleared when DPD mode is entered. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[8] |GPAWK |GPA Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins + * | | |This flag is cleared when SPD mode is entered. + * |[9] |GPBWK |GPB Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins + * | | |This flag is cleared when SPD mode is entered. + * |[10] |GPCWK |GPC Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins + * | | |This flag is cleared when SPD mode is entered. + * |[11] |GPDWK |GPD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins + * | | |This flag is cleared when SPD mode is entered. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened + * | | |This flag is cleared when SPD mode is entered. + * |[13] |BODWK |BOD Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened + * | | |This flag is cleared when SPD mode is entered. + * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition + * | | |This flag is cleared when SPD mode is entered. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1 = Clear all wake-up flag. + * @var CLK_T::LDOCTL + * Offset: 0x98 LDO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18] |PDBIASEN |Power-down Bias Enable Bit + * | | |0 = Reserved. + * | | |1 = Power-down bias enabled. + * | | |Note: This bit should set to 1 before chip enter power-down mode. + * @var CLK_T::SWKDBCTL + * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection + * | | |0000 = Sample wake-up input once per 1 clocks. + * | | |0001 = Sample wake-up input once per 2 clocks. + * | | |0010 = Sample wake-up input once per 4 clocks. + * | | |0011 = Sample wake-up input once per 8 clocks. + * | | |0100 = Sample wake-up input once per 16 clocks. + * | | |0101 = Sample wake-up input once per 32 clocks. + * | | |0110 = Sample wake-up input once per 64 clocks. + * | | |0111 = Sample wake-up input once per 128 clocks. + * | | |1000 = Sample wake-up input once per 256 clocks. + * | | |1001 = Sample wake-up input once per 2*256 clocks. + * | | |1010 = Sample wake-up input once per 4*256 clocks. + * | | |1011 = Sample wake-up input once per 8*256 clocks. + * | | |1100 = Sample wake-up input once per 16*256 clocks. + * | | |1101 = Sample wake-up input once per 32*256 clocks. + * | | |1110 = Sample wake-up input once per 64*256 clocks. + * | | |1111 = Sample wake-up input once per 128*256 clocks. + * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * @var CLK_T::PASWKCTL + * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPA group pin wake-up function disabled. + * | | |1 = GPA group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPA group pin rising edge wake-up function disabled. + * | | |1 = GPA group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPA group pin falling edge wake-up function disabled. + * | | |1 = GPA group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select + * | | |0000 = GPA.0 wake-up function enabled. + * | | |0001 = GPA.1 wake-up function enabled. + * | | |0010 = GPA.2 wake-up function enabled. + * | | |0011 = GPA.3 wake-up function enabled. + * | | |0100 = GPA.4 wake-up function enabled. + * | | |0101 = GPA.5 wake-up function enabled. + * | | |0110 = GPA.6 wake-up function enabled. + * | | |0111 = GPA.7 wake-up function enabled. + * | | |1000 = GPA.8 wake-up function enabled. + * | | |1001 = GPA.9 wake-up function enabled. + * | | |1010 = GPA.10 wake-up function enabled. + * | | |1011 = GPA.11 wake-up function enabled. + * | | |1100 = GPA.12 wake-up function enabled. + * | | |1101 = GPA.13 wake-up function enabled. + * | | |1110 = GPA.14 wake-up function enabled. + * | | |1111 = GPA.15 wake-up function enabled. + * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PBSWKCTL + * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPB group pin wake-up function disabled. + * | | |1 = GPB group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPB group pin rising edge wake-up function disabled. + * | | |1 = GPB group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPB group pin falling edge wake-up function disabled. + * | | |1 = GPB group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select + * | | |0000 = GPB.0 wake-up function enabled. + * | | |0001 = GPB.1 wake-up function enabled. + * | | |0010 = GPB.2 wake-up function enabled. + * | | |0011 = GPB.3 wake-up function enabled. + * | | |0100 = GPB.4 wake-up function enabled. + * | | |0101 = GPB.5 wake-up function enabled. + * | | |0110 = GPB.6 wake-up function enabled. + * | | |0111 = GPB.7 wake-up function enabled. + * | | |1000 = GPB.8 wake-up function enabled. + * | | |1001 = GPB.9 wake-up function enabled. + * | | |1010 = GPB.10 wake-up function enabled. + * | | |1011 = GPB.11 wake-up function enabled. + * | | |1100 = GPB.12 wake-up function enabled. + * | | |1101 = GPB.13 wake-up function enabled. + * | | |1110 = GPB.14 wake-up function enabled. + * | | |1111 = GPB.15 wake-up function enabled. + * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PCSWKCTL + * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPC group pin wake-up function disabled. + * | | |1 = GPC group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPC group pin rising edge wake-up function disabled. + * | | |1 = GPC group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPC group pin falling edge wake-up function disabled. + * | | |1 = GPC group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select + * | | |0000 = GPC.0 wake-up function enabled. + * | | |0001 = GPC.1 wake-up function enabled. + * | | |0010 = GPC.2 wake-up function enabled. + * | | |0011 = GPC.3 wake-up function enabled. + * | | |0100 = GPC.4 wake-up function enabled. + * | | |0101 = GPC.5 wake-up function enabled. + * | | |0110 = GPC.6 wake-up function enabled. + * | | |0111 = GPC.7 wake-up function enabled. + * | | |1000 = GPC.8 wake-up function enabled. + * | | |1001 = GPC.9 wake-up function enabled. + * | | |1010 = GPC.10 wake-up function enabled. + * | | |1011 = GPC.11 wake-up function enabled. + * | | |1100 = GPC.12 wake-up function enabled. + * | | |1101 = GPC.13 wake-up function enabled. + * | | |1110 = GPC.14 wake-up function enabled. + * | | |1111 = GPC.15 wake-up function enabled. + * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PDSWKCTL + * Offset: 0xAC GPD Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPD group pin wake-up function disabled. + * | | |1 = GPD group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPD group pin rising edge wake-up function disabled. + * | | |1 = GPD group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPD group pin falling edge wake-up function disabled. + * | | |1 = GPD group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select + * | | |0000 = GPD.0 wake-up function enabled. + * | | |0001 = GPD.1 wake-up function enabled. + * | | |0010 = GPD.2 wake-up function enabled. + * | | |0011 = GPD.3 wake-up function enabled. + * | | |0100 = GPD.4 wake-up function enabled. + * | | |0101 = GPD.5 wake-up function enabled. + * | | |0110 = GPD.6 wake-up function enabled. + * | | |0111 = GPD.7 wake-up function enabled. + * | | |1000 = GPD.8 wake-up function enabled. + * | | |1001 = GPD.9 wake-up function enabled. + * | | |1010 = GPD.10 wake-up function enabled. + * | | |1011 = GPD.11 wake-up function enabled. + * | | |1100 = GPD.12 wake-up function enabled. + * | | |1101 = GPD.13 wake-up function enabled. + * | | |1110 = GPD.14 wake-up function enabled. + * | | |1111 = GPD.15 wake-up function enabled. + * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::IOPDCTL + * Offset: 0xB0 GPIO Standby Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IOHR |GPIO Hold Release + * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status + * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. + * | | |This bit is auto cleared by hardware. + */ + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[1]; + /** @endcond */ + __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[2]; + /** @endcond */ + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE3[3]; + /** @endcond */ + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE4[3]; + /** @endcond */ + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE5[4]; + /** @endcond */ + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */ + __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */ + __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ + __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ + __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ + __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ + __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ +#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ +#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ + +#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ +#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ + +#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ +#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ + +#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */ +#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */ + +#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ +#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ + +#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ +#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ + +#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */ +#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */ + +#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ +#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ + +#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ +#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ + +#define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */ +#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */ + +#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ +#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ + +#define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */ +#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */ + +#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ +#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ + +#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ +#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ + +#define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */ +#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ +#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ +#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ + +#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ +#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ +#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ + +#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */ +#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */ + +#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ +#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ +#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ + +#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ +#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ + +#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ +#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ +#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ + +#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ +#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ +#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ +#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ + +#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ +#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ + +#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ +#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ + +#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ +#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ + +#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */ +#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#if(0) +#define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */ +#define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */ + +#define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */ +#define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */ +#endif + +#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ +#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ + +#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ +#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ +#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ + +#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ +#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ +#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ + +#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ +#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ +#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ +#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ + +#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ +#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ +#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ + +#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ +#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ + +#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ +#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ + +#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ +#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ + +#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ +#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ + +#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ +#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ + +#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ +#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ + +#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ +#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ +#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ + +#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ +#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ +#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ + +#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */ +#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */ + +#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ +#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ +#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ + +#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ +#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ + +#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ +#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ + +#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ +#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ + +#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ +#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ +#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_PLLCTL_BANDSEL_Pos (28) /*!< CLK_T::PLLCTL: BANDSEL Position */ +#define CLK_PLLCTL_BANDSEL_Msk (0x1ul << CLK_PLLCTL_BANDSEL_Pos) /*!< CLK_T::PLLCTL: BANDSEL Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ +#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ + +#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ +#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ +#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ +#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ + +#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ +#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ + +#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ +#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ + +#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ +#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ +#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ + +#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ +#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */ +#define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */ + +#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ + +#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ +#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ + +#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ +#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ + +#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ +#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ + +#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ +#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ + +#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ +#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ + +#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ +#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ + +#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ +#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ + +#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ +#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ + +#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ +#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ + +#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ +#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ + +#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ +#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ + +#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ +#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ + +#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ +#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ + +#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ +#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ + +#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ +#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ + +#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ +#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ + +#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ +#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ + +#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ +#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ + +#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ +#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ + +#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ +#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ + +#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ +#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CLK_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h new file mode 100644 index 0000000000..6e12a14285 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h @@ -0,0 +1,149 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V1.00 + * @brief CRC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRC Cyclic Redundancy Check Controller(CRC) + Memory Mapped Structure for CRC Controller +@{ */ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Enable Bit + * | | |0 = No effect. + * | | |1 = CRC operation Enabled. + * |[1] |CHKSINIT |Checksum Initialization + * | | |0 = No effect. + * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. + * | | |Note: This bit will be cleared automatically. + * |[24] |DATREV |Write Data Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. + * | | |0 = Bit order reversed for CRC write data in Disabled. + * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. + * | | |0 = Bit order reverse for CRC checksum Disabled. + * | | |1 = Bit order reverse for CRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement + * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. + * | | |0 = 1's complement for CRC writes data in Disabled. + * | | |1 = 1's complement for CRC writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement + * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. + * | | |0 = 1's complement for CRC checksum Disabled. + * | | |1 = 1's complement for CRC checksum Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the write data length. + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ + +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller +@{ */ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crypto_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crypto_reg.h new file mode 100644 index 0000000000..ae75c9c7cd --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crypto_reg.h @@ -0,0 +1,2218 @@ +/**************************************************************************//** + * @file crypto_reg.h + * @version V1.00 + * @brief CRYPTO register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRYPTO_REG_H__ +#define __CRYPTO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRPT Cryptographic Accelerator(CRPT) + Memory Mapped Structure for Cryptographic Accelerator +@{ */ + +typedef struct +{ + + /** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Control + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Control + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[8] |TDESIEN |TDES/DES Interrupt Enable Control + * | | |0 = TDES/DES interrupt Disabled. + * | | |1 = TDES/DES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. + * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control + * | | |0 = TDES/DES error interrupt flag Disabled. + * | | |1 = TDES/DES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Control + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Control + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Control + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = SHA/HMAC error interrupt flag Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES interrupt. + * | | |= AES encryption/decryption done interrupt. + * |[1] |AESEIF |AES Error Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption done interrupt. + * |[8] |TDESIF |TDES/DES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No TDES/DES interrupt. + * | | |1 = TDES/DES encryption/decryption done interrupt. + * |[9] |TDESEIF |TDES/DES Error Flag + * | | |This bit includes the operating and setting error + * | | |The detailed flag is shown in the CRPT_TDES_STS register + * | | |This includes operating and setting error. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No TDES/DES error. + * | | |1 = TDES/DES encryption/decryption error interrupt. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[3:2] |KEYSZ |PRNG Generate Key Size + * | | |00 = 64 bits. + * | | |01 = 128 bits. + * | | |10 = 192 bits. + * | | |11 = 256 bits. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * @var CRPT_T::PRNG_KEY[8] + * Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::AES_FDBCK[4] + * Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::TDES_FDBCKH + * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |TDES/DES Feedback + * | | |The feedback value is 64 bits in size. + * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode + * | | |The feedback register is for CBC, CFB, and OFB mode. + * | | |TDES/DES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation + * | | |Then can continue the operation with the original setting. + * @var CRPT_T::TDES_FDBCKL + * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |TDES/DES Feedback + * | | |The feedback value is 64 bits in size. + * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode + * | | |The feedback register is for CBC, CFB, and OFB mode. + * | | |TDES/DES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation + * | | |Then can continue the operation with the original setting. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it's read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it's read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2'b00 = 128 bits key. + * | | |2'b01 = 192 bits key. + * | | |2'b10 = 256 bits key. + * | | |2'b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it's read back. Must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Control + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * |[16] |ENCRPT |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25:24] |CHANNEL |AES Engine Working Channel + * | | |00 = Current control register setting is for channel 0. + * | | |01 = Current control register setting is for channel 1. + * | | |10 = Current control register setting is for channel 2. + * | | |11 = Current control register setting is for channel 3. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |And the key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AESn_CNT Setting Error + * | | |0 = No error in CRPT_AESn_CNT setting. + * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES0_KEY[8] + * Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES0_IV[4] + * Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES0_SADDR + * Offset: 0x140 AES DMA Source Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES0_DADDR + * Offset: 0x144 AES DMA Destination Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES0_CNT + * Offset: 0x148 AES Byte Count Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES1_KEY[8] + * Offset: 0x14C ~ 0x168 AES Key Word 0 ~ 7 Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES1_IV[4] + * Offset: 0x16C ~ 0x178 AES Initial Vector Word 0 ~ 3 Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES1_SADDR + * Offset: 0x17C AES DMA Source Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES1_DADDR + * Offset: 0x180 AES DMA Destination Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES1_CNT + * Offset: 0x184 AES Byte Count Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES2_KEY[8] + * Offset: 0x188 ~ 0x1A4 AES Key Word 0 ~ 7 Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES2_IV[4] + * Offset: 0x1A8 ~ 0x1B4 AES Initial Vector Word 0 ~ 3 Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES2_SADDR + * Offset: 0x1B8 AES DMA Source Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES2_DADDR + * Offset: 0x1BC AES DMA Destination Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES2_CNT + * Offset: 0x1C0 AES Byte Count Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES3_KEY[8] + * Offset: 0x1C4 ~ 0x1E0 AES Key Word 0 ~ 7 Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES3_IV[4] + * Offset: 0x1E4 ~ 0x1F0 AES Initial Vector Word 0 ~ 3 Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES3_SADDR + * Offset: 0x1F4 AES DMA Source Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES3_DADDR + * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES3_CNT + * Offset: 0x1FC AES Byte Count Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::TDES_CTL + * Offset: 0x200 TDES/DES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |TDES/DES Engine Start + * | | |0 = No effect. + * | | |1 = Start TDES/DES engine. The flag BUSY would be set. + * | | |Note: The bit is always 0 when it's read back. + * |[1] |STOP |TDES/DES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop TDES/DES engine. + * | | |Note: The bit is always 0 when it's read back. + * |[2] |TMODE |TDES/DES Engine Operating Mode + * | | |0 = Set DES mode for TDES/DES engine. + * | | |1 = Set Triple DES mode for TDES/DES engine. + * |[3] |3KEYS |TDES/DES Key Number + * | | |0 = Select KEY1 and KEY2 in TDES/DES engine. + * | | |1 = Triple keys in TDES/DES engine Enabled. + * |[5] |DMALAST |TDES/DES Engine Start for the Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set as feeding in last block of data. + * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |TDES/DES Engine DMA Enable Control + * | | |0 = TDES_DMA engine Disabled. + * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN. + * | | |1 = TDES_DMA engine Enabled. + * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |TDES/DES Engine Operation Mode + * | | |0x00 = ECB (Electronic Codebook Mode). + * | | |0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |Others = CTR (Counter Mode). + * |[16] |ENCRPT |TDES/DES Encryption/Decryption + * | | |0 = TDES engine executes decryption operation. + * | | |1 = TDES engine executes encryption operation. + * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap + * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}. + * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. + * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |TDES/DES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25:24] |CHANNEL |TDES/DES Engine Working Channel + * | | |00 = Current control register setting is for channel 0. + * | | |01 = Current control register setting is for channel 1. + * | | |10 = Current control register setting is for channel 2. + * | | |11 = Current control register setting is for channel 3. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = This bit is to protect the content of TDES key from reading + * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |The key content would be cleared as well. + * @var CRPT_T::TDES_STS + * Offset: 0x204 TDES/DES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |TDES/DES Engine Busy + * | | |0 = TDES/DES engine is idle or finished. + * | | |1 = TDES/DES engine is under processing. + * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty + * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process. + * | | |1 = TDES/DES input buffer is empty + * | | |Software needs to feed data to the TDES/DES engine + * | | |Otherwise, the TDES/DES engine will be pending to wait for input data. + * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag + * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine. + * | | |1 = TDES input buffer is full + * | | |Software cannot feed data to the TDES/DES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |TDES/DES in Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the TDES/DES engine. + * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag + * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT + * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty. + * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag + * | | |0 = TDES/DES output buffer is not full. + * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT + * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full. + * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting test result from TDES/DES engine. + * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and TDES/DES engine. + * @var CRPT_T::TDES0_KEY1H + * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY1L + * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY2H + * Offset: 0x210 TDES Key 2 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY2L + * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY3H + * Offset: 0x218 TDES Key 3 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY3L + * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_IVH + * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES0_IVL + * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES0_SA + * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES0_DA + * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES0_CNT + * Offset: 0x230 TDES/DES Byte Count Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES_DATIN + * Offset: 0x234 TDES/DES Engine Input data Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |TDES/DES Engine Input Port + * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS + * | | |Feed data as INBUFFULL is 0. + * @var CRPT_T::TDES_DATOUT + * Offset: 0x238 TDES/DES Engine Output data Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |TDES/DES Engine Output Port + * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::TDES1_KEY1H + * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY1L + * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY2H + * Offset: 0x250 TDES Key 2 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY2L + * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY3H + * Offset: 0x258 TDES Key 3 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY3L + * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_IVH + * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES1_IVL + * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES1_SA + * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES1_DA + * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES1_CNT + * Offset: 0x270 TDES/DES Byte Count Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES2_KEY1H + * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY1L + * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY2H + * Offset: 0x290 TDES Key 2 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY2L + * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY3H + * Offset: 0x298 TDES Key 3 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY3L + * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_IVH + * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES2_IVL + * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES2_SA + * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES2_DA + * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES2_CNT + * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES3_KEY1H + * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY1L + * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY2H + * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY2L + * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY3H + * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY3L + * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_IVH + * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES3_IVL + * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES3_SA + * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES3_DA + * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES3_CNT + * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |This bit is always 0 when it's read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |This bit is always 0 when it's read back. + * |[4] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = execute SHA function. + * | | |1 = execute HMAC function. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |0x0xx: SHA160 + * | | |0x100: SHA256 + * | | |0x101: SHA224 + * | | |0x110: SHA512 + * | | |0x111: SHA384 + * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * @var CRPT_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRPT_T::HMAC_DGST[16] + * Offset: 0x308 ~ 0x344 SHA/HMAC Digest Message 0 ~ 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Digest Message Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_SHA _KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRPT_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. + * | | |CRPT_HMAC_SADDR can be read and written + * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. + * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. + * @var CRPT_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_HMAC_DMACNT can be read and written + * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRPT_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRPT_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it's read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it's read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[7] |DMAEN |ECC Accelerator DMA Enable Control + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2^m)). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication :. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). + * | | |10 = Point addition :. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling :. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division :. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication :. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition :. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction :. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1) + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2) + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRPT_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Remember to clear ECC interrupt flag after ECC accelerator finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator. + * @var CRPT_T::ECC_X1[18] + * Offset: 0x808 ~ 0x84C ECC The X-coordinate word 0 ~ 17 of the first point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1) + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_Y1[18] + * Offset: 0x850 ~ 0x894 ECC The Y-coordinate word 0 ~ 17 of the first point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1) + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_X2[18] + * Offset: 0x898 ~ 0x8DC ECC The X-coordinate word 0 ~ 17 of the second point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2) + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_Y2[18] + * Offset: 0x8E0 ~ 0x924 ECC The Y-coordinate word 0 ~ 17 of the second point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2) + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_A[18] + * Offset: 0x928 ~ 0x96C ECC The parameter CURVEA word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA) + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_B[18] + * Offset: 0x970 ~ 0x9B4 ECC The parameter CURVEB word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA) + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_N[18] + * Offset: 0x9B8 ~ 0x9FC ECC The parameter CURVEN word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN) + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2^m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_K[18] + * Offset: 0xA00 ~ 0xA44 ECC The scalar SCALARK word0 of point multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK) + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |ECC DMA Source Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between + * | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data + * | | |buffer where the source text is stored. Based on the source address, the ECC accelerator + * | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start + * | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are + * | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR + * | | |before triggering START. + * @var CRPT_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START + * @var CRPT_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG + * | | |For example, we want to updated input data from register CRPT_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRPT_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words + * | | |CRPT_ECC_WORDCNT can be read and written + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ + __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */ + __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[38]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ + __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ + __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */ + __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */ + __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */ + __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */ + __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */ + __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */ + __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */ + __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */ + __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */ + __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */ + __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */ + __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */ + __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */ + __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */ + __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */ + __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */ + __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */ + __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */ + __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */ + __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */ + __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */ + __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */ + __IO uint32_t TDES0_SA; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */ + __IO uint32_t TDES0_DA; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */ + __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */ + __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */ + __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */ + __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */ + __IO uint32_t TDES1_SA; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */ + __IO uint32_t TDES1_DA; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */ + __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */ + __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */ + __IO uint32_t TDES2_SA; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */ + __IO uint32_t TDES2_DA; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */ + __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */ + __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */ + __IO uint32_t TDES3_SA; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */ + __IO uint32_t TDES3_DA; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */ + __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[298]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ + __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ + __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ + __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRPT Bit Field Definition + Constant Definitions for CRPT Controller +@{ */ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */ +#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */ + +#define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */ +#define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ +#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ + +#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ +#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ + +#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ +#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ + +#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ +#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */ +#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */ + +#define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */ +#define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ +#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ + +#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ +#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ + +#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ +#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ + +#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ +#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */ +#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */ + +#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */ +#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */ + +#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */ +#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */ + +#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */ +#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ +#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */ +#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */ +#define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */ + +#define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */ +#define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */ + +#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */ +#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */ + +#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */ +#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */ + +#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */ +#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */ + +#define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */ +#define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */ + +#define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */ +#define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */ + +#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */ +#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */ + +#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */ +#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */ + +#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */ +#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */ + +#define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEY[8]: KEY Position */ +#define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEY[8]: KEY Mask */ + +#define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IV[4]: IV Position */ +#define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IV[4]: IV Mask */ + +#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */ +#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */ + +#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */ +#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */ + +#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */ +#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */ + +#define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */ +#define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */ + +#define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */ +#define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */ + +#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */ +#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */ + +#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */ +#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */ + +#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */ +#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */ + +#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */ +#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */ + +#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */ +#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */ + +#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */ +#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */ + +#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */ +#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */ + +#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */ +#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */ + +#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */ +#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */ + +#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */ +#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */ + +#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */ +#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */ + +#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */ +#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */ + +#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */ +#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */ + +#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */ +#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */ + +#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */ +#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */ + +#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */ +#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */ + +#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */ +#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */ + +#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */ +#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */ + +#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */ +#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */ + +#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */ +#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */ + +#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */ +#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */ + +#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */ +#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */ + +#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */ +#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */ +#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */ + +#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */ +#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */ + +#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */ +#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */ + +#define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */ +#define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */ + +#define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */ +#define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */ + +#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */ +#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */ + +#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */ +#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */ + +#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */ +#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */ + +#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */ +#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */ + +#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */ +#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */ + +#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */ +#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */ + +#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */ +#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */ + +#define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */ +#define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */ + +#define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */ +#define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */ + +#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */ +#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */ + +#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */ +#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */ + +#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */ +#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */ + +#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */ +#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */ + +#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */ +#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */ + +#define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */ +#define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */ + +#define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */ +#define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */ + +#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */ +#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */ + +#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */ +#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */ + +#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */ +#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */ + +#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */ +#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */ + +#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */ +#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */ + +#define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */ +#define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */ + +#define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */ +#define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */ + +#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */ +#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */ + +#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */ +#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */ + +#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */ +#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */ + +#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */ +#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */ + +#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */ +#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */ + +#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ +#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ + +#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ +#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ + +#define CRPT_HMAC_CTL_HMACEN_Pos (4) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ +#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ + +#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ +#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ + +#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ +#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ + +#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ +#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ + +#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ +#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ +#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ + +#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ +#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ + +#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ +#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ + +#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ +#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ + +#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ +#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ + +#define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST[16]: DGST Position */ +#define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGST[16]: DGST Mask */ + +#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ +#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ + +#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ +#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ +#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ + +#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ +#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ + +#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ +#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ + +#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ +#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ + +#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ +#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ + +#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ +#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ + +#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ +#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ + +#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ +#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ + +#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ +#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ + +#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ +#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ + +#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ +#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ + +#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ +#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ + +#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ +#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ + +#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ +#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ + +#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ +#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ + +#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ +#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ + +#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ +#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ + +#define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1[18]: POINTX1 Position */ +#define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1[18]: POINTX1 Mask */ + +#define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position */ +#define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask */ + +#define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2[18]: POINTX2 Position */ +#define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask */ + +#define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position */ +#define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask */ + +#define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A[18]: CURVEA Position */ +#define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A[18]: CURVEA Mask */ + +#define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B[18]: CURVEB Position */ +#define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B[18]: CURVEB Mask */ + +#define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N[18]: CURVEN Position */ +#define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N[18]: CURVEN Mask */ + +#define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K[18]: SCALARK Position */ +#define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K[18]: SCALARK Mask */ + +#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ +#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ + +#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ +#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ + +#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */ +#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ + +/**@}*/ /* CRPT_CONST CRYPTO */ +/**@}*/ /* end of CRYPTO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRYPTO_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h new file mode 100644 index 0000000000..bd151e320d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h @@ -0,0 +1,209 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup DAC Digital to Analog Converter(DAC) + Memory Mapped Structure for DAC Controller +@{ */ + +typedef struct +{ + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA under-run interrupt Disabled. + * | | |1 = DMA under-run interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC0_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |110 = EPWM0 trigger. + * | | |111 = EPWM1 trigger. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * |[16] |GRPEN |DAC Group Mode Enable Bit + * | | |0 = DAC0 and DAC1 are not grouped. + * | | |1 = DAC0 and DAC1 are grouped. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output + * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET + * | | |It is cleared to 0 when DAC starts a new conversion + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under-run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. + * | | |SELTTLET = DAC controller clock speed x settling time. + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller +@{ */ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ +#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __DAC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/eadc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/eadc_reg.h new file mode 100644 index 0000000000..7cabdad9b2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/eadc_reg.h @@ -0,0 +1,1710 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * | | |This is a read only register. + * @var EADC_T::CTL + * Offset: 0x50 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |ADC Converter Enable Bit + * | | |0 = Disabled EADC. + * | | |1 = Enabled EADC. + * | | |Note: Before starting ADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. + * |[1] |ADCRST |ADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. + * |[7:6] |RESSEL |Resolution Selection + * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). + * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). + * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). + * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. + * |[11] |PDMAEN |PDMA Transfer Enable Bit + * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 ADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write: + * | | |1 = clear pending flag & cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL[19] + * Offset: 0x80 ADC Sample Module 0~18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0 (slow channel). + * | | |01H = EADC_CH1 (slow channel). + * | | |02H = EADC_CH2 (slow channel). + * | | |03H = EADC_CH3 (slow channel). + * | | |04H = EADC_CH4 (slow channel). + * | | |05H = EADC_CH5 (slow channel). + * | | |06H = EADC_CH6 (slow channel). + * | | |07H = EADC_CH7 (slow channel). + * | | |08H = EADC_CH8 (slow channel). + * | | |09H = EADC_CH9 (slow channel). + * | | |0AH = EADC_CH10 (fast channel). + * | | |0BH = EADC_CH11 (fast channel). + * | | |0CH = EADC_CH12 (fast channel). + * | | |0DH = EADC_CH13 (fast channel). + * | | |0EH = EADC_CH14 (fast channel). + * | | |0FH = EADC_CH15 (fast channel). + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). + * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = EPWM0TG0. + * | | |9H = EPWM0TG1. + * | | |AH = EPWM0TG2. + * | | |BH = EPWM0TG3. + * | | |CH = EPWM0TG4. + * | | |DH = EPWM0TG5. + * | | |EH = EPWM1TG0. + * | | |FH = EPWM1TG1. + * | | |10H = EPWM1TG2. + * | | |11H = EPWM1TG3. + * | | |12H = EPWM1TG4. + * | | |13H = EPWM1TG5. + * | | |14H = BPWM0TG. + * | | |15H = BPWM1TG. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register. (default). + * | | |1 = Sample has two sample result registers. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. + * | | |The range of start delay time is from 0~255 ADC clock. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0 ADC Result Compare Register 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 ADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS1 + * Offset: 0xF4 ADC Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 ADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is s overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |It is read only. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = VBAT/4. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC ADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module + * | | |This register show the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, this bit filed will set to 0x1F. + * | | |This is a read only register. + * @var EADC_T::DDAT[4] + * Offset: 0x100 ADC Double Data Register 0 for Sample Module 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read + * | | |(n=0~3). + * @var EADC_T::PWRM + * Offset: 0x110 ADC Power Management Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) + * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of start up. + * | | |1 = ADC is ready for conversion. + * |[1] |PWUCALEN |Power Up Calibration Function Enable Control + * | | |0 = Disable the function of calibration at power up. + * | | |1 = Enable the function of calibration at power up. + * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following + * | | |{PWUCALEN, CALSEL } Description: + * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. + * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. + * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. + * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. + * |[3:2] |PWDMOD |ADC Power-down Mode + * | | |Set this bit fields to select ADC power down mode when system power-down. + * | | |00 = ADC Deep power down mode. + * | | |01 = ADC Power down. + * | | |10 = ADC Standby mode. + * | | |11 = ADC Deep power down mode. + * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up + * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time + * | | |Set this bit fields to control LDO start-up time + * | | |The minimum required LDO start-up time is 20us + * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. + * @var EADC_T::CALCTL + * Offset: 0x114 ADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CALSTART |Calibration Functional Block Start + * | | |0 = Stops calibration functional block. + * | | |1 = Starts calibration functional block. + * | | |Note: This bit is set by SW and clear by HW after re-calibration finish + * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) + * | | |0 = During a calibration. + * | | |1 = Calibration is completed. + * |[3] |CALSEL |Select Calibration Functional Block + * | | |0 = Load calibration word when calibration functional block is active. + * | | |1 = Execute calibration when calibration functional block is active. + * @var EADC_T::CALDWRD + * Offset: 0x118 ADC Calibration Load Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CALWORD |Calibration Word Bits + * | | |Write to this register with the previous calibration word before load calibration action. + * | | |Read this register after calibration done. + * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. + */ + __I uint32_t DAT[19]; /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SCTL[19]; /*!< [0x0080] ADC Sample Module 0~18 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSRC[4]; /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register. */ + __IO uint32_t CMP[4]; /*!< [0x00e0] ADC Result Compare Register 0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3 */ + __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ + __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ + __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ + +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller +@{ */ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ +#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ + +#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ +#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ + +#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ +#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ + +#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ +#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ + +#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ +#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ + +#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ +#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ + +#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ +#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ + +#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ +#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ + +#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ +#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ + +#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ +#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ + +#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ +#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ + +#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ +#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ + +#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ +#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ + +#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ +#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ + +#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ +#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ + +#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ +#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ + +#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ +#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ + +#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ +#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ + +#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ +#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ + +#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ +#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ + +#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ +#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ + +#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ +#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ + +#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ +#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ + +#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ +#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ + +#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ +#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ + +#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ +#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ + +#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ +#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ + +#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ +#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ + +#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ +#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ + +#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ +#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ +#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */ +#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ +#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ +#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ +#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ +#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ +#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ +#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ +#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ + +#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ +#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ + +#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ +#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ + +#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ +#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ + +#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ +#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ + +#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ +#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ + +#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ +#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ + +#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ +#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ + +#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ +#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ + +#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ +#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ + +#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ +#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ + +#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ +#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ + +#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ +#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ + +#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ +#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ + +#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ +#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ + +#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ +#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ + +#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ +#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ + +#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ +#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ + +#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ +#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ + +#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ +#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ + +#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ +#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ + +#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ +#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ + +#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ +#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ + +#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ +#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ + +#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ +#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ + +#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ +#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ + +#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ +#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ + +#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ +#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ + +#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ +#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ + +#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ +#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ + +#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ +#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ + +#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ +#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ + +#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ +#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ + +#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ +#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ + +#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ +#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ + +#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ +#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ + +#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ +#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ + +#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ +#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ + +#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ +#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ + +#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ +#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ + +#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ +#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ + +#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ +#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ + +#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ +#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ + +#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ +#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ + +#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ +#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ + +#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ +#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ + +#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ +#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ + +#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ +#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ + +#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ +#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ + +#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ +#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ + +#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ +#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ + +#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ +#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ + +#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ +#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ + +#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ +#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ + +#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ +#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ + +#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ +#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ + +#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ +#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ + +#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ +#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ + +#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ +#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ + +#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ +#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ + +#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ +#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ + +#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ +#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ + +#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ +#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ + +#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ +#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ + +#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ +#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ + +#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ +#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ + +#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ +#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ + +#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ +#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ +#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ + +#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ +#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ + +#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ +#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ + +#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ +#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ + +#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ +#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ + +#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ +#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ + +#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ +#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ + +#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ +#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ + +#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ +#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ + +#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ +#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ +#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ + +#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ +#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ + +#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ +#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ + +#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ +#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ + +#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ +#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ + +#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ +#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ + +#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ +#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ + +#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ +#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ + +#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ +#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ + +#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ +#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ +#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ + +#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ +#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ + +#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ +#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ + +#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ +#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ + +#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ +#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ + +#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ +#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ + +#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ +#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ + +#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ +#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ + +#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ +#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ + +#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ +#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ +#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ + +#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ +#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ + +#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ +#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ + +#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ +#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ + +#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ +#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ + +#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ +#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ + +#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ +#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ + +#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ +#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ + +#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ +#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ + +#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ +#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ +#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ + +#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ +#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ + +#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ +#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ + +#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ +#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ + +#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ +#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ + +#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ +#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ + +#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ +#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ + +#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ +#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EADC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h new file mode 100644 index 0000000000..f0a51018a8 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h @@ -0,0 +1,428 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V1.00 + * @brief EBI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller +@{ */ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Bank0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Bank0 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL1 + * Offset: 0x10 External Bus Interface Bank1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL1 + * Offset: 0x14 External Bus Interface Bank1 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL2 + * Offset: 0x20 External Bus Interface Bank2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL2 + * Offset: 0x24 External Bus Interface Bank2 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller +@{ */ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ + +#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ +#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ + +#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ +#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ + +#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ +#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ + +#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ +#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ + +#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ +#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ + +#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ +#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ + +#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ +#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ + +#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ +#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ + +#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ +#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ + +#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ +#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ + +#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ +#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ + +#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ +#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ + +#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ +#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ + +#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ +#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ + +#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */ +#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */ + +#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */ +#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */ + +#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */ +#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */ + +#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */ +#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */ + +#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */ +#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */ + +#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */ +#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */ + +#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */ +#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */ + +#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */ +#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */ + +#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */ +#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */ + +#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */ +#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */ + +#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */ +#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */ + +#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */ +#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */ + +#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */ +#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */ + +#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */ +#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */ + +#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */ +#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */ + +#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */ +#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */ + +#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */ +#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */ + +#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */ +#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */ + +#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */ +#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */ + +#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */ +#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */ + +#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */ +#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */ + +#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */ +#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */ + +#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */ +#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */ + +#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */ +#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */ + +#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */ +#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */ + +#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */ +#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */ + +#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */ +#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */ + +#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */ +#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EBI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h new file mode 100644 index 0000000000..b09379fb62 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @version V1.00 + * @brief ECAP register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller +@{ */ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller +@{ */ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ECAP_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/emac_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/emac_reg.h new file mode 100644 index 0000000000..b75fed4d1f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/emac_reg.h @@ -0,0 +1,2062 @@ +/**************************************************************************//** + * @file emac_reg.h + * @version V1.00 + * @brief EMAC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EMAC_REG_H__ +#define __EMAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EMAC Ethernet MAC Controller(EMAC) + Memory Mapped Structure for EMAC Controller +@{ */ + +typedef struct +{ + + /** + * @var EMAC_T::CAMCTL + * Offset: 0x00 CAM Comparison Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AUP |Accept Unicast Packet + * | | |The AUP controls the unicast packet reception + * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all unicast packets. + * |[1] |AMP |Accept Multicast Packet + * | | |The AMP controls the multicast packet reception + * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all multicast packets. + * |[2] |ABP |Accept Broadcast Packet + * | | |The ABP controls the broadcast packet reception + * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all broadcast packets. + * |[3] |COMPEN |Complement CAM Comparison Enable Bit + * | | |The COMPEN controls the complement of the CAM comparison result + * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address + * | | |configured in CAM entry will be dropped + * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received. + * | | |0 = Complement CAM comparison result Disabled. + * | | |1 = Complement CAM comparison result Enabled. + * |[4] |CMPEN |CAM Compare Enable Bit + * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition + * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address + * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1. + * | | |0 = CAM comparison function for destination MAC address recognition Disabled. + * | | |1 = CAM comparison function for destination MAC address recognition Enabled. + * @var EMAC_T::CAMEN + * Offset: 0x04 CAM Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAMxEN |CAM Entry X Enable Bit + * | | |The CAMxEN controls the validation of CAM entry x. + * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission + * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM + * | | |entries all must be enabled first. + * | | |0 = CAM entry x Disabled. + * | | |1 = CAM entry x Enabled. + * @var EMAC_T::CAM0M + * Offset: 0x08 CAM0 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM0L + * Offset: 0x0C CAM0 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1M + * Offset: 0x10 CAM1 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1L + * Offset: 0x14 CAM1 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2M + * Offset: 0x18 CAM2 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2L + * Offset: 0x1C CAM2 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3M + * Offset: 0x20 CAM3 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3L + * Offset: 0x24 CAM3 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4M + * Offset: 0x28 CAM4 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4L + * Offset: 0x2C CAM4 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5M + * Offset: 0x30 CAM5 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5L + * Offset: 0x34 CAM5 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6M + * Offset: 0x38 CAM6 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6L + * Offset: 0x3C CAM6 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7M + * Offset: 0x40 CAM7 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7L + * Offset: 0x44 CAM7 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8M + * Offset: 0x48 CAM8 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8L + * Offset: 0x4C CAM8 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9M + * Offset: 0x50 CAM9 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9L + * Offset: 0x54 CAM9 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10M + * Offset: 0x58 CAM10 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10L + * Offset: 0x5C CAM10 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11M + * Offset: 0x60 CAM11 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11L + * Offset: 0x64 CAM11 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12M + * Offset: 0x68 CAM12 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12L + * Offset: 0x6C CAM12 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13M + * Offset: 0x70 CAM13 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13L + * Offset: 0x74 CAM13 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14M + * Offset: 0x78 CAM14 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14L + * Offset: 0x7C CAM14 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM15MSB + * Offset: 0x80 CAM15 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame + * | | |In the PAUSE control frame, an op code field defined and is 0x0001. + * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame + * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808. + * @var EMAC_T::CAM15LSB + * Offset: 0x84 CAM15 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:24] |OPERAND |Pause Parameter + * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination + * | | |Ethernet MAC Controller paused + * | | |The unit of the OPERAND is a slot time, the 512-bit time. + * @var EMAC_T::TXDSA + * Offset: 0x88 Transmit Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address + * | | |The TXDSA keeps the start address of transmit descriptor link-list + * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the + * | | |current transmit descriptor start address register (EMAC_CTXDSA) + * | | |The TXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA + * | | |This means that TX descriptors must locate at word boundary memory address. + * @var EMAC_T::RXDSA + * Offset: 0x8C Receive Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address + * | | |The RXDSA keeps the start address of receive descriptor link-list + * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current + * | | |receive descriptor start address register (EMAC_CRXDSA) + * | | |The RXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA + * | | |This means that RX descriptors must locate at word boundary memory address. + * @var EMAC_T::CTL + * Offset: 0x90 MAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXON |Frame Reception ON + * | | |The RXON controls the normal packet reception of EMAC + * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX + * | | |descriptor fetching, packet reception and RX descriptor modification. + * | | |It is necessary to finish EMAC initial sequence before enable RXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet + * | | |reception process after the current packet reception finished. + * | | |0 = Packet reception process stopped. + * | | |1 = Packet reception process started. + * |[1] |ALP |Accept Long Packet + * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception + * | | |If the ALP is set to high, the EMAC will accept the long packet. + * | | |Otherwise, the long packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the long packet. + * | | |1 = Ethernet MAC controller received the long packet. + * |[2] |ARP |Accept Runt Packet + * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception + * | | |If the ARP is set to high, the EMAC will accept the runt packet. + * | | |Otherwise, the runt packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the runt packet. + * | | |1 = Ethernet MAC controller received the runt packet. + * |[3] |ACP |Accept Control Packet + * | | |The ACP controls the control frame reception + * | | |If the ACP is set to high, the EMAC will accept the control frame + * | | |Otherwise, the control frame will be dropped + * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode. + * | | |0 = Ethernet MAC controller dropped the control frame. + * | | |1 = Ethernet MAC controller received the control frame. + * |[4] |AEP |Accept CRC Error Packet + * | | |The AEP controls the EMAC accepts or drops the CRC error packet + * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet. + * | | |0 = Ethernet MAC controller dropped the CRC error packet. + * | | |1 = Ethernet MAC controller received the CRC error packet. + * |[5] |STRIPCRC |Strip CRC Checksum + * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum + * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. + * | | |0 = The 4 bytes CRC checksum is included in packet length calculation. + * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation. + * |[6] |WOLEN |Wake on LAN Enable Bit + * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet + * | | |is Magic Packet and wakeup system from Power-down mode. + * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller + * | | |would generate a wakeup event to wake system up from Power-down mode. + * | | |0 = Wake-up by Magic Packet function Disabled. + * | | |1 = Wake-up by Magic Packet function Enabled. + * |[8] |TXON |Frame Transmission ON + * | | |The TXON controls the normal packet transmission of EMAC + * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX + * | | |descriptor fetching, packet transmission and TX descriptor modification. + * | | |It is must to finish EMAC initial sequence before enable TXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet + * | | |transmission process after the current packet transmission finished. + * | | |0 = Packet transmission process stopped. + * | | |1 = Packet transmission process started. + * |[9] |NODEF |No Deferral + * | | |The NODEF controls the enable of deferral exceed counter + * | | |If NODEF is set to high, the deferral exceed counter is disabled + * | | |The NODEF is only useful while EMAC is operating on half duplex mode. + * | | |0 = The deferral exceed counter Enabled. + * | | |1 = The deferral exceed counter Disabled. + * |[16] |SDPZ |Send PAUSE Frame + * | | |The SDPZ controls the PAUSE control frame transmission. + * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured + * | | |first and the corresponding CAM enable bit of CAMEN register also must be set. + * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission. + * | | |The SDPZ is a self-clear bit + * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. + * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode. + * | | |0 = PAUSE control frame transmission completed. + * | | |1 = PAUSE control frame transmission Enabled. + * |[17] |SQECHKEN |SQE Checking Enable Bit + * | | |The SQECHKEN controls the enable of SQE checking + * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode + * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps + * | | |or full duplex mode. + * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode. + * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode. + * |[18] |FUDUP |Full Duplex Mode Selection + * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode. + * | | |0 = EMAC operates in half duplex mode. + * | | |1 = EMAC operates in full duplex mode. + * |[19] |RMIIRXCTL |RMII RX Control + * | | |The RMIIRXCTL control the receive data sample in RMII mode + * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. + * | | |0 = RMII RX control disabled. + * | | |1 = RMII RX control enabled. + * |[20] |OPMODE |Operation Mode Selection + * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode + * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value. + * | | |0 = EMAC operates in 10Mbps mode. + * | | |1 = EMAC operates in 100Mbps mode. + * |[22] |RMIIEN |RMII Mode Enable Bit + * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII + * | | |interface or RMII interface + * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value. + * | | |0 = Ethernet MAC controller RMII mode Disabled. + * | | |1 = Ethernet MAC controller RMII mode Enabled. + * | | |NOTE: This field must keep 1. + * |[24] |RST |Software Reset + * | | |The RST implements a reset function to make the EMAC return default state + * | | |The RST is a self-clear bit + * | | |This means after the software reset finished, the RST will be cleared automatically + * | | |Enable RST can also reset all control and status registers, exclusive of the control bits + * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]). + * | | |The EMAC re-initial is necessary after the software reset completed. + * | | |0 = Software reset completed. + * | | |1 = Software reset Enabled. + * @var EMAC_T::MIIMDAT + * Offset: 0x94 MII Management Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATA |MII Management Data + * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII + * | | |Management write command or the data from the registers of external PHY for MII Management read command. + * @var EMAC_T::MIIMCTL + * Offset: 0x98 MII Management Control and Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PHYREG |PHY Register Address + * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the + * | | |MII management command. + * |[12:8] |PHYADDR |PHY Address + * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. + * |[16] |WRITE |Write Command + * | | |The Write defines the MII management command is a read or write. + * | | |0 = MII management command is a read command. + * | | |1 = MII management command is a write command. + * |[17] |BUSY |Busy Bit + * | | |The BUSY controls the enable of the MII management frame generation + * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates + * | | |the MII management frame to external PHY through MII Management I/F + * | | |The BUSY is a self-clear bit + * | | |This means the BUSY will be cleared automatically after the MII management command finished. + * | | |0 = MII management command generation finished. + * | | |1 = MII management command generation Enabled. + * |[18] |PREAMSP |Preamble Suppress + * | | |The PREAMSP controls the preamble field generation of MII management frame + * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped. + * | | |0 = Preamble field generation of MII management frame not skipped. + * | | |1 = Preamble field generation of MII management frame skipped. + * |[19] |MDCON |MDC Clock ON + * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on. + * | | |0 = MDC clock off. + * | | |1 = MDC clock on. + * @var EMAC_T::FIFOCTL + * Offset: 0x9C FIFO Threshold Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RXFIFOTH |RXFIFO Low Threshold + * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO + * | | |and system memory + * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold + * | | |The low threshold is the half of high threshold always + * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to + * | | |transfer frame data from RXFIFO to system memory + * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame + * | | |data to system memory. + * | | |00 = Depend on the burst length setting + * | | |If the burst length is 8 words, high threshold is 8 words, too. + * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B. + * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B. + * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B. + * |[9:8] |TXFIFOTH |TXFIFO Low Threshold + * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system + * | | |memory and TXFIFO + * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold + * | | |The high threshold is the twice of low threshold always + * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops + * | | |generate request to transfer frame data from system memory to TXFIFO + * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data + * | | |from system memory to TXFIFO. + * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network + * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold + * | | |during the transmission of the frame + * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame + * | | |out after the frame data are all inside the TXFIFO. + * | | |00 = Undefined. + * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B. + * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B. + * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B. + * |[21:20] |BURSTLEN |DMA Burst Length + * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory. + * | | |00 = 4 words. + * | | |01 = 8 words. + * | | |10 = 16 words. + * | | |11 = 16 words. + * @var EMAC_T::TXST + * Offset: 0xA0 Transmit Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXST |Transmit Start Demand + * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, + * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted + * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write + * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. + * | | |The EMAC_TXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state. + * @var EMAC_T::RXST + * Offset: 0xA4 Receive Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXST |Receive Start Demand + * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, + * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted + * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write + * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. + * | | |The EMAC_RXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state. + * @var EMAC_T::MRFL + * Offset: 0xA8 Maximum Receive Frame Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MRFL |Maximum Receive Frame Length + * | | |The MRFL defines the maximum frame length for received frame + * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) + * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered. + * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to + * | | |receive a frame which length is greater than 1518 bytes. + * @var EMAC_T::INTEN + * Offset: 0xAC MAC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIEN |Receive Interrupt Enable Bit + * | | |The RXIEN controls the RX interrupt generation. + * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU + * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] + * | | |is set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit. + * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled. + * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled. + * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit + * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation + * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CRCEIF (EMAC_INTSTS[1]) is set. + * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled. + * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled. + * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit + * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation + * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXOVIF (EMAC_INTSTS[2]) is set. + * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled. + * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled. + * |[3] |LPIEN |Long Packet Interrupt Enable Bit + * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation + * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF + * | | |(EMAC_INTSTS[3]) is set. + * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled. + * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled. + * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit + * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation + * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXGDIF (EMAC_INTSTS[4]) is set. + * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled. + * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled. + * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit + * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation + * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |ALIEIF (EMAC_INTSTS[5]) is set. + * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled. + * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled. + * |[6] |RPIEN |Runt Packet Interrupt Enable Bit + * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation + * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RPIF (EMAC_INTSTS[6]) is set. + * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled. + * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled. + * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit + * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation + * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MPCOVIF (EMAC_INTSTS[7]) is set. + * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled. + * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled. + * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit + * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation + * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MFLEIF (EMAC_INTSTS[8]) is set. + * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled. + * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled. + * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit + * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation + * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |DENIF (EMAC_INTSTS[9]) is set. + * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled. + * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled. + * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit + * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation + * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RDUIF (EMAC_MIOSTA[10]) register is set. + * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled. + * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled. + * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit + * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation + * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXBEIF (EMAC_INTSTS[11]) is set. + * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled. + * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled. + * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit + * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation + * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CFRIF (EMAC_INTSTS[14]) register is set. + * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled. + * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled. + * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit + * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation + * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |WOLIF (EMAC_INTSTS[15]) is set. + * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled. + * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled. + * |[16] |TXIEN |Transmit Interrupt Enable Bit + * | | |The TXIEN controls the TX interrupt generation. + * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU + * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of + * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit. + * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled. + * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled. + * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit + * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation + * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even + * | | |the TXUDIF (EMAC_INTSTS[17]) is set. + * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled. + * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled. + * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit + * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation + * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXCPIF (EMAC_INTSTS[18]) is set. + * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled. + * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled. + * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit + * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation + * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |EXDEFIF (EMAC_INTSTS[19]) is set. + * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled. + * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled. + * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit + * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation + * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |NCSIF (EMAC_INTSTS[20]) is set. + * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled. + * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled. + * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit + * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation + * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXABTIF (EMAC_INTSTS[21]) is set. + * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled. + * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled. + * |[22] |LCIEN |Late Collision Interrupt Enable Bit + * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation + * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |LCIF (EMAC_INTSTS[22]) is set. + * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled. + * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled. + * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit + * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation + * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TDUIF (EMAC_INTSTS[23]) is set. + * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled. + * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled. + * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit + * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation + * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXBEIF (EMAC_INTSTS[24]) is set. + * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled. + * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled. + * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit + * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation + * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the + * | | |TXTSALMIF (EMAC_INTEN[28]) is set. + * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled. + * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled. + * @var EMAC_T::INTSTS + * Offset: 0xB0 MAC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIF |Receive Interrupt + * | | |The RXIF indicates the RX interrupt status. + * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates + * | | |the EMAC generates RX interrupt to CPU + * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated. + * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1] + * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high. + * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is enabled, too. + * |[1] |CRCEIF |CRC Error Interrupt + * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped + * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and + * | | |CRCEIF will not be set. + * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CRCEIF status. + * | | |0 = The frame does not incur CRC error. + * | | |1 = The frame incurred CRC error. + * |[2] |RXOVIF |Receive FIFO Overflow Interrupt + * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception + * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer + * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, + * | | |the RXFIFOTH of FFTCR register, to higher level. + * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXOVIF status. + * | | |0 = No RXFIFO overflow occurred during packet reception. + * | | |1 = RXFIFO overflow occurred during packet reception. + * |[3] |LPIF |Long Packet Interrupt Flag + * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the + * | | |incoming packet is dropped + * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set. + * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the LPIF status. + * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame. + * | | |1 = The incoming frame is a long frame and dropped. + * |[4] |RXGDIF |Receive Good Interrupt + * | | |The RXGDIF high indicates the frame reception has completed. + * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXGDIF status. + * | | |0 = The frame reception has not complete yet. + * | | |1 = The frame reception has completed. + * |[5] |ALIEIF |Alignment Error Interrupt + * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte + * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the ALIEIF status. + * | | |0 = The frame length is a multiple of byte. + * | | |1 = The frame length is not a multiple of byte. + * |[6] |RPIF |Runt Packet Interrupt + * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped + * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set. + * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RPIF status. + * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame. + * | | |1 = The incoming frame is a short frame and dropped. + * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag + * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow + * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MPCOVIF status. + * | | |0 = The MPCNT has not rolled over yet. + * | | |1 = The MPCNT has rolled over yet. + * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag + * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation + * | | |configured in DMARFC register and the incoming packet is dropped + * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MFLEIF status. + * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC. + * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC. + * |[9] |DENIF |DMA Early Notification Interrupt + * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet. + * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the DENIF status. + * | | |0 = The LENGTH field of incoming packet has not received yet. + * | | |1 = The LENGTH field of incoming packet has received. + * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt + * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and + * | | |RXDMA will stay at Halt state + * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to + * | | |make RXDMA leave Halt state while new RX descriptor is available. + * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RDUIF status. + * | | |0 = RX descriptor is available. + * | | |1 = RX descriptor is unavailable. + * |[11] |RXBEIF |Receive Bus Error Interrupt + * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access + * | | |system memory through RXDMA during packet reception process + * | | |Reset EMAC is recommended while RXBEIF status is high. + * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[14] |CFRIF |Control Frame Receive Interrupt + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CFRIF status. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[15] |WOLIF |Wake on LAN Interrupt Flag + * | | |The WOLIF high indicates EMAC receives a Magic Packet + * | | |The CFRIF only available while system is in power down mode and WOLEN is set high. + * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the WOLIF status. + * | | |0 = The EMAC does not receive the Magic Packet. + * | | |1 = The EMAC receives a Magic Packet. + * |[16] |TXIF |Transmit Interrupt + * | | |The TXIF indicates the TX interrupt status. + * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates + * | | |the EMAC generates TX interrupt to CPU + * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated. + * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17] + * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high + * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is enabled, too. + * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt + * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission + * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically + * | | |without S/W intervention + * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, + * | | |the TXFIFOTH of FFTCR register, to higher level. + * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXUDIF status. + * | | |0 = No TXFIFO underflow occurred during packet transmission. + * | | |1 = TXFIFO underflow occurred during packet transmission. + * |[18] |TXCPIF |Transmit Completion Interrupt + * | | |The TXCPIF indicates the packet transmission has completed correctly. + * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXCPIF status. + * | | |0 = The packet transmission not completed. + * | | |1 = The packet transmission has completed. + * |[19] |EXDEFIF |Defer Exceed Interrupt + * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms + * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode. + * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC + * | | |is operating on half-duplex mode. + * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the EXDEFIF status. + * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * |[20] |NCSIF |No Carrier Sense Interrupt + * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during + * | | |the packet transmission + * | | |The NCSIF is only available while EMAC is operating on half-duplex mode + * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the NCSIF status. + * | | |0 = CRS signal actives correctly. + * | | |1 = CRS signal does not active at the start of or during the packet transmission. + * |[21] |TXABTIF |Transmit Abort Interrupt + * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, + * | | |and then the transmission process for this packet is aborted + * | | |The transmission abort is only available while EMAC is operating on half-duplex mode. + * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXABTIF status. + * | | |0 = Packet does not incur 16 consecutive collisions during transmission. + * | | |1 = Packet incurred 16 consecutive collisions during transmission. + * |[22] |LCIF |Late Collision Interrupt + * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window + * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision + * | | |still occurred. + * | | |The late collision check will only be done while EMAC is operating on half-duplex mode + * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the LCIF status. + * | | |0 = No collision occurred in the outside of 64 bytes collision window. + * | | |1 = Collision occurred in the outside of 64 bytes collision window. + * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt + * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and + * | | |TXDMA will stay at Halt state. + * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make + * | | |TXDMA leave Halt state while new TX descriptor is available. + * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TDUIF status. + * | | |0 = TX descriptor is available. + * | | |1 = TX descriptor is unavailable. + * |[24] |TXBEIF |Transmit Bus Error Interrupt + * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system + * | | |memory through TXDMA during packet transmission process + * | | |Reset EMAC is recommended while TXBEIF status is high. + * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[28] |TSALMIF |Time Stamp Alarm Interrupt + * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and + * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR. + * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TSALMIF status. + * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC. + * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC. + * @var EMAC_T::GENSTS + * Offset: 0xB4 MAC General Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CFR |Control Frame Received + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[1] |RXHALT |Receive Halted + * | | |The RXHALT high indicates the next normal packet reception process will be halted because + * | | |the bit RXON of MCMDR is disabled be S/W. + * | | |0 = Next normal packet reception process will go on. + * | | |1 = Next normal packet reception process will be halted. + * |[2] |RXFFULL |RXFIFO Full + * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO + * | | |and the following incoming packet will be dropped. + * | | |0 = The RXFIFO is not full. + * | | |1 = The RXFIFO is full and the following incoming packet will be dropped. + * |[7:4] |COLCNT |Collision Count + * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission + * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be + * | | |0 and bit TXABTIF will be set to 1. + * |[8] |DEF |Deferred Transmission + * | | |The DEF high indicates the packet transmission has deferred once + * | | |The DEF is only available while EMAC is operating on half-duplex mode. + * | | |0 = Packet transmission does not defer. + * | | |1 = Packet transmission has deferred once. + * |[9] |TXPAUSED |Transmission Paused + * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally + * | | |because EMAC received a PAUSE control frame. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be paused. + * |[10] |SQE |Signal Quality Error + * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode + * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC + * | | |is operating on 10Mbps half-duplex mode. + * | | |0 = No SQE error found at end of packet transmission. + * | | |1 = SQE error found at end of packet transmission. + * |[11] |TXHALT |Transmission Halted + * | | |The TXHALT high indicates the next normal packet transmission process will be halted because + * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be halted. + * |[12] |RPSTS |Remote Pause Status + * | | |The RPSTS indicates that remote pause counter down counting actives. + * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause + * | | |counter down counting + * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet + * | | |transmission until the down counting done. + * | | |0 = Remote pause counter down counting done. + * | | |1 = Remote pause counter down counting actives. + * @var EMAC_T::MPCNT + * Offset: 0xB8 Missed Packet Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MPCNT |Miss Packet Count + * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors + * | | |The following type of receiving error makes missed packet counter increase: + * | | |1. Incoming packet is incurred RXFIFO overflow. + * | | |2. Incoming packet is dropped due to RXON is disabled. + * | | |3. Incoming packet is incurred CRC error. + * @var EMAC_T::RPCNT + * Offset: 0xBC MAC Receive Pause Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RPCNT |MAC Receive Pause Count + * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame + * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused. + * @var EMAC_T::FRSTS + * Offset: 0xC8 DMA Receive Frame Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXFLT |Receive Frame LENGTH + * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet + * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has + * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. + * | | |And, the content of LENGTH field will be stored in RXFLT. + * @var EMAC_T::CTXDSA + * Offset: 0xCC Current Transmit Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address + * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently + * | | |The CTXDSA is read only and write to this register has no effect. + * @var EMAC_T::CTXBSA + * Offset: 0xD0 Current Transmit Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXBSA |Current Transmit Buffer Start Address + * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently + * | | |The CTXBSA is read only and write to this register has no effect. + * @var EMAC_T::CRXDSA + * Offset: 0xD4 Current Receive Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXDSA |Current Receive Descriptor Start Address + * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently + * | | |The CRXDSA is read only and write to this register has no effect. + * @var EMAC_T::CRXBSA + * Offset: 0xD8 Current Receive Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXBSA |Current Receive Buffer Start Address + * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently + * | | |The CRXBSA is read only and write to this register has no effect. + * @var EMAC_T::TSCTL + * Offset: 0x100 Time Stamp Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TSEN |Time Stamp Function Enable Bit + * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not. + * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low + * | | |to disable IEEE 1588 PTP time stamp function. + * | | |0 = I EEE 1588 PTP time stamp function Disabled. + * | | |1 = IEEE 1588 PTP time stamp function Enabled. + * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC + * | | |and EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = Time stamp counter initialization done. + * | | |1 = Time stamp counter initialization Enabled. + * |[2] |TSMODE |Time Stamp Fine Update Enable Bit + * | | |This bit chooses the time stamp counter update mode. + * | | |0 = Time stamp counter is in coarse update mode. + * | | |1 = Time stamp counter is in fine update mode. + * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and + * | | |EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = No action. + * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC. + * |[5] |TSALMEN |Time Stamp Alarm Enable Bit + * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when + * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * @var EMAC_T::TSSEC + * Offset: 0x110 Time Stamp Counter Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second + * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSSUBSEC + * Offset: 0x114 Time Stamp Counter Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second + * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSINC + * Offset: 0x118 Time Stamp Increment Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNTINC |Time Stamp Counter Increment + * | | |Time stamp counter increment value. + * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every + * | | |time when it wants to increase the EMAC_TSSUBSEC value. + * @var EMAC_T::TSADDEND + * Offset: 0x11C Time Stamp Addend Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDEND |Time Stamp Counter Addend + * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC. + * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator + * | | |with this 32-bit value in each HCLK + * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit + * | | |value kept in register EMAC_TSINC. + * @var EMAC_T::UPDSEC + * Offset: 0x120 Time Stamp Update Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value. + * @var EMAC_T::UPDSUBSEC + * Offset: 0x124 Time Stamp Update Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value. + * @var EMAC_T::ALMSEC + * Offset: 0x128 Time Stamp Alarm Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Alarm + * | | |Time stamp counter second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + * @var EMAC_T::ALMSUBSEC + * Offset: 0x12C Time Stamp Alarm Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm + * | | |Time stamp counter sub-second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + */ + __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */ + __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */ + __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */ + __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */ + __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */ + __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */ + __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */ + __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */ + __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */ + __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */ + __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */ + __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */ + __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */ + __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */ + __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */ + __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */ + __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */ + __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */ + __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */ + __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */ + __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */ + __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */ + __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */ + __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */ + __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */ + __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */ + __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */ + __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */ + __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */ + __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */ + __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */ + __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */ + __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */ + __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */ + __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */ + __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */ + __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */ + __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */ + __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */ + __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */ + __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */ + __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */ + __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */ + __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */ + __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */ + __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */ + __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[2]; + /** @endcond */ + __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */ + __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */ + __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */ + __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */ + __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[9]; + /** @endcond */ + __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */ + __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */ + __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */ + __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */ + __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */ + __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */ + __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */ + __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */ + +} EMAC_T; + +/** + @addtogroup EMAC_CONST EMAC Bit Field Definition + Constant Definitions for EMAC Controller +@{ */ + +#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */ +#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */ + +#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */ +#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */ + +#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */ +#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */ + +#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */ +#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */ + +#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */ +#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */ + +#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */ +#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */ + +#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */ +#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */ + +#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */ +#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */ + +#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */ +#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */ + +#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */ +#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */ + +#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */ +#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */ + +#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */ +#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */ + +#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */ +#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */ + +#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */ +#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */ + +#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */ +#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */ + +#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */ +#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */ + +#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */ +#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */ + +#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */ +#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */ + +#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */ +#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */ + +#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */ +#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */ + +#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */ +#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */ + +#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */ +#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */ + +#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */ +#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */ + +#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */ +#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */ + +#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */ +#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */ + +#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */ +#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */ + +#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */ +#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */ + +#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */ +#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */ + +#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */ +#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */ + +#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */ +#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */ + +#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */ +#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */ + +#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */ +#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */ + +#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */ +#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */ + +#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */ +#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */ + +#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */ +#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */ + +#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */ +#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */ + +#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */ +#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */ + +#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */ +#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */ + +#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */ +#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */ + +#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */ +#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */ + +#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */ +#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */ + +#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */ +#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */ + +#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */ +#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */ + +#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */ +#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */ + +#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */ +#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */ + +#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */ +#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */ + +#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */ +#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */ + +#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */ +#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */ + +#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */ +#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */ + +#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */ +#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */ + +#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */ +#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */ + +#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */ +#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */ + +#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */ +#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */ + +#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */ +#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */ + +#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */ +#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */ + +#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */ +#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */ + +#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */ +#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */ + +#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */ +#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */ + +#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */ +#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */ + +#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */ +#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */ + +#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */ +#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */ + +#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */ +#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */ + +#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */ +#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */ + +#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */ +#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */ + +#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */ +#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */ + +#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */ +#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */ + +#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */ +#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */ + +#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */ +#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */ + +#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */ +#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */ + +#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */ +#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */ + +#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */ +#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */ + +#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */ +#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */ + +#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */ +#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */ + +#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */ +#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */ + +#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */ +#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */ + +#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */ +#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */ + +#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */ +#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */ + +#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */ +#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */ + +#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */ +#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */ + +#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */ +#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */ + +#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */ +#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */ + +#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */ +#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */ + +#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */ +#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */ + +#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */ +#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */ + +#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */ +#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */ + +#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */ +#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */ + +#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */ +#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */ + +#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */ +#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */ + +#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */ +#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */ + +#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */ +#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */ + +#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */ +#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */ + +#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */ +#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */ + +#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */ +#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */ + +#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */ +#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */ + +#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */ +#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */ + +#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */ +#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */ + +#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */ +#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */ + +#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */ +#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */ + +#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */ +#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */ + +#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */ +#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */ + +#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */ +#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */ + +#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */ +#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */ + +#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */ +#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */ + +#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */ +#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */ + +#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */ +#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */ + +#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */ +#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */ + +#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */ +#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */ + +#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */ +#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */ + +#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */ +#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */ + +#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */ +#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */ + +#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */ +#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */ + +#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */ +#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */ + +#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */ +#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */ + +#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */ +#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */ + +#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */ +#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */ + +#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */ +#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */ + +#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */ +#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */ + +#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */ +#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */ + +#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */ +#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */ + +#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */ +#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */ + +#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */ +#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */ + +#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */ +#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */ + +#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */ +#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */ + +#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */ +#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */ + +#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */ +#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */ + +#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */ +#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */ + +#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */ +#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */ + +#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */ +#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */ + +#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */ +#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */ + +#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */ +#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */ + +#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */ +#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */ + +#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */ +#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */ + +#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */ +#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */ + +#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */ +#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */ + +#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */ +#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */ + +#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */ +#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */ + +#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */ +#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */ + +#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */ +#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */ + +#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */ +#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */ + +#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */ +#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */ + +#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */ +#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */ + +#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */ +#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */ + +#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */ +#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */ + +#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */ +#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */ + +#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */ +#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */ + +#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */ +#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */ + +#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */ +#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */ + +#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */ +#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */ + +#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */ +#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */ + +#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */ +#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */ + +#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */ +#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */ + +#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */ +#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */ + +#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */ +#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */ + +#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */ +#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */ + +#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */ +#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */ + +#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */ +#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */ + +#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */ +#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */ + +#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */ +#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */ + +#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */ +#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */ + +#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */ +#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */ + +#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */ +#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */ + +#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */ +#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */ + +#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */ +#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */ + +#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */ +#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */ + +#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */ +#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */ + +#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */ +#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */ + +#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */ +#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */ + +#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */ +#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */ + +#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */ +#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */ + +#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */ +#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */ + +#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */ +#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */ + +#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */ +#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */ + +#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */ +#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */ + +#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */ +#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */ + +#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */ +#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */ + +#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */ +#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */ + +#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */ +#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */ + +#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */ +#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */ + +#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */ +#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */ + +#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */ +#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */ + +#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */ +#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */ + +#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */ +#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */ + +#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */ +#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */ + +#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */ +#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */ + +#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */ +#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */ + +#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */ +#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */ + +#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */ +#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */ + +#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */ +#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */ + +#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */ +#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */ + +#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */ +#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */ + +#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */ +#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */ + +#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */ +#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */ + +#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */ +#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */ + +#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */ +#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */ + +#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */ +#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */ + +#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */ +#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */ + +#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */ +#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */ + +#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */ +#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */ + +#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */ +#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */ + +#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */ +#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */ + +#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */ +#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */ + +#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */ +#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */ + +#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */ +#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */ + +#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */ +#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */ + +#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */ +#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */ + +#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */ +#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */ + +#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */ +#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */ + +/**@}*/ /* EMAC_CONST */ +/**@}*/ /* end of EMAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EMAC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/epwm_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/epwm_reg.h new file mode 100644 index 0000000000..ffd4735cac --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/epwm_reg.h @@ -0,0 +1,3755 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @version V1.00 + * @brief EPWM register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EPWM Pulse Width Modulation Controller(EPWM) + Memory Mapped Structure for EPWM Controller +@{ */ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit(S) + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin SYNC is passed to the negative edge detector. + * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CLKPSC[3] + * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD[6] + * Offset: 0x30 EPWM Period Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. + * @var EPWM_T::CMPDAT[6] + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::DTCTL[3] + * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This register is write protected. Refer toREGWRPROT register. + * @var EPWM_T::PHS[3] + * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. + * @var EPWM_T::CNT[6] + * Offset: 0x90 EPWM Counter Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL[3] + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[1] |PINV1 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[2] |PINV2 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[3] |PINV3 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[4] |PINV4 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[5] |PINV5 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[1] |POEN1 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[2] |POEN2 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[3] |POEN3 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[4] |POEN4 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[5] |POEN5 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 edge-detect brake event do not happened. + * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 edge-detect brake event do not happened. + * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 edge-detect brake event do not happened. + * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 edge-detect brake event do not happened. + * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 edge-detect brake event do not happened. + * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 edge-detect brake event do not happened. + * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 level-detect brake event do not happened. + * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 level-detect brake event do not happened. + * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 level-detect brake event do not happened. + * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 level-detect brake event do not happened. + * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 level-detect brake event do not happened. + * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 level-detect brake event do not happened. + * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 edge-detect brake state is released. + * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. + * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 edge-detect brake state is released. + * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. + * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 edge-detect brake state is released. + * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. + * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 edge-detect brake state is released. + * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. + * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 edge-detect brake state is released. + * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. + * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 edge-detect brake state is released. + * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. + * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 level-detect brake state is released. + * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 level-detect brake state is released. + * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 level-detect brake state is released. + * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 level-detect brake state is released. + * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 level-detect brake state is released. + * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 level-detect brake state is released. + * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::DACTRGEN + * Offset: 0xF4 EPWM Trigger DAC Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit + * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit + * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit + * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit + * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit + * @var EPWM_T::FTCMPDAT[3] + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP use to compare with even CNTR to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[24] |DACTRGF |DAC Start of Conversion Flag + * | | |0 = Indicates no DAC start of conversion trigger event has occurred. + * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit + * @var EPWM_T::IFA[6] + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = CNT equal to Zero in channel n. + * | | |01 = CNT equal to PERIOD in channel n. + * | | |10 = CNT equal to CMPU in channel n. + * | | |11 = CNT equal to CMPD in channel n. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator disable. + * | | |1 = EPWM_CHn interrupt flag accumulator enable. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1. + * | | |10 = EPWM_FCAPDAT0/1. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. + * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3. + * | | |10 = EPWM_FCAPDAT2/3. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. + * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5. + * | | |10 = EPWM_FCAPDAT4/5. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. + * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP[3] + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * @var EPWM_T::PBUF[6] + * Offset: 0x304 EPWM PERIOD0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF[6] + * Offset: 0x31C EPWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF[3] + * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Use as EPWM counter clock prescale active register. + * @var EPWM_T::FTCBUF[3] + * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */ + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[41]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ + __I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */ + __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller +@{ */ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ +#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ +#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ +#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ +#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ + +#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ +#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ + +#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ +#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ +#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ + +#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ +#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ + +#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ +#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ +#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ + +#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ +#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ + +#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ +#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ +#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ + +#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ +#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ +#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ + +#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ +#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ +#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ + +#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ +#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ +#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ + +#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ +#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ + +#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ +#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ + +#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ +#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ + +#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ +#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ + +#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ +#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ + +#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ +#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ + +#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ +#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ + +#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ +#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ + +#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ +#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ + +#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ +#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ + +#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ +#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ + +#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ +#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ + +#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ +#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ + +#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ +#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ + +#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ +#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ + +#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ +#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ + +#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ +#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ + +#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ +#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ + +#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ +#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ + +#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ +#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ + +#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ +#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ + +#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ +#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ + +#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ +#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ +#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ +#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ +#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ +#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EPWM_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/fmc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/fmc_reg.h new file mode 100644 index 0000000000..46ab4332e2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/fmc_reg.h @@ -0,0 +1,640 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup FMC Flash Memory Controller(FMC) + Memory Mapped Structure for FMC Controller +@{ */ + +typedef struct +{ + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. + * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect) + * | | |0 = SPROM cannot be updated. + * | | |1 = SPROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |BL |Boot Loader Booting (Write Protect) + * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) + * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded + * | | |This bit is used to check chip boot from Boot Loader or not + * | | |User should keep original value of this bit when updating FMC_ISPCTL register. + * | | |0 = Booting from APROM or LDROM. + * | | |1 = Booting from Boot Loader. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |The NuMicro M480 series is equipped with embedded flash + * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation + * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. + * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. + * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) + * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff + * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment + * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP Command + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x08= Read Flash All-One Result. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. + * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. + * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1.. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |0x40= FLASH 64-bit Read. + * | | |0x61= FLASH 64-bit Program. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::DFBA + * Offset: 0x14 Data Flash Base Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DFBA |Data Flash Base Address + * | | |This register indicates Data Flash start address. It is a read only register. + * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 + * | | |This register is valid when DFEN (CONFIG0[0]) =0 . + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. + * | | |00 = LDROM with IAP mode. + * | | |01 = LDROM without IAP mode. + * | | |10 = APROM with IAP mode. + * | | |11 = APROM without IAP mode. + * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) + * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from Boot Loader. + * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) + * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) + * | | |This bit is set if flash access cycle auto-tuning function is disabled + * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. + * | | |0 = Flash access cycle auto-tuning is enabled. + * | | |1 = Flash access cycle auto-tuning is disabled. + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 + * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. + * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. + * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} + * |[31] |SCODE |Security Code Active Flag + * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation. + * | | |0 = Secured code is inactive. + * | | |1 = Secured code is active. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. + * | | |The HCLK working frequency range range is<27MHz + * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. + * | | | The optimized HCLK working frequency range is 27~54 MHz + * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. + * | | |The optimized HCLK working frequency range is 54~81MHz + * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. + * | | | The optimized HCLK working frequency range is81~108MHz + * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. + * | | |The optimized HCLK working frequency range is 108~135MHz + * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. + * | | | The optimized HCLK working frequency range is 135~162MHz + * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. + * | | | The optimized HCLK working frequency range is 162~192MHz + * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. + * | | |The optimized HCLK working frequency range is >192MHz + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::KPKEY0 + * Offset: 0x50 KPROM KEY0 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) + * | | |Write KPKEY0 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEY1 + * Offset: 0x54 KPROM KEY1 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) + * | | |Write KPKEY1 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEY2 + * Offset: 0x58 KPROM KEY2 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) + * | | |Write KPKEY2 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEYTRG + * Offset: 0x5C KPROM KEY Comparison Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) + * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished + * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. + * | | |0 = KEY comparison operation is finished. + * | | |1 = KEY comparison is progressed. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[1] |TCEN |Timeout Counting Enable (Write Protection) + * | | |0 = Timeout counting is disabled. + * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. + * | | |10 minutes is at least for timeout, and average is about 20 minutes. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::KPKEYSTS + * Offset: 0x60 KPROM KEY Comparison Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) + * | | |0 = KEY comparison is finished. + * | | |1 = KEY comparison is busy. + * |[1] |KEYLOCK |KEY LOCK Flag + * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection + * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 + * | | |This bit also can be set to 1 while + * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or + * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or + * | | | - KEYENROM is programmed a non-0xFF value or + * | | | - Timeout event or + * | | | - FORBID(FMC_KPKEYSTS[3]) is 1 + * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. + * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. + * | | |SPROM write protect is depended on SPFLAG. + * | | |CONFIG write protect is depended on CFGFLAG + * |[2] |KEYMATCH |KEY Match Flag (Read Only) + * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched + * | | |This bit is also cleared to 0 while + * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or + * | | | - Timeout event or + * | | | - KPROM is erased or + * | | | - KEYENROM is programmed to a non-0xFF value. + * | | | - Chip is in power down mode. + * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. + * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. + * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) + * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). + * | | |0 = KEY comparison is not forbidden. + * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. + * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. + * | | |0 = Security Key protection is disabled. + * | | |1 = Security Key protection is enabled. + * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. + * | | |0 = CONFIG write-protection is disabled. + * | | |1 = CONFIG write-protection is enabled. + * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. + * | | |0 = SPROM write-protection is disabled. + * | | |1 = SPROM write-protection is enabled. + * @var FMC_T::KPKEYCNT + * Offset: 0x64 KPROM KEY-Unmatched Counting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) + * | | |KPKECNT is increased when entry keys is wrong in Security Key protection + * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. + * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) + * | | |KPKEMAX is the maximum error key entry number at each power-on + * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated + * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting + * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. + * @var FMC_T::KPCNT + * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) + * | | |KPCNT is the power-on counting for error key entry in Security Key protection + * | | |KPCNT is cleared to 0 if key comparison is matched. + * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) + * | | |KPMAX is the power-on maximum number for error key entry + * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated + * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting + * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-Program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-Program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + */ + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[10]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ + __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ + __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ + __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ + __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ + __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ + __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[12]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller +@{ */ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ +#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ + +#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ +#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ +#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ +#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ +#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ + +#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ +#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */ +#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ +#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ + +#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ +#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ + +#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ +#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ + +#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ +#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ + +#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ +#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ + +#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ +#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ + +#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ +#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ + +#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ +#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ + +#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ +#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ + +#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ +#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ + +#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ +#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ + +#define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */ +#define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */ + +#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ +#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ + +#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ +#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ + +#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ +#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ + +#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ +#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __FMC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/gpio_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/gpio_reg.h new file mode 100644 index 0000000000..e5114d5892 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/gpio_reg.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V1.00 + * @brief GPIO register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + + +typedef struct +{ + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-H Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit. + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-H Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-H Pin[n] Input Signal De-Bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V). + * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V). + * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V. + * | | |11 = Reserved. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-up disable. + * | | |01 = Px.n pull-up enable. + * | | |10 = Px.n pull-down enable. + * | | |11 = Reserved. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation + * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode + * | | |The independent pull-down control register only valid when MODEn set as tri-state mode + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + */ + + __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control */ + __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control */ + __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value */ + __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask */ + __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value */ + __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register */ + __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register */ + __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag */ + __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register */ + __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Enable Register */ + +} GPIO_T; + +typedef struct +{ + + /** + * @var GPIO_DBCTL_T::DBCTL + * Offset: 0x440 Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * |[5] |ICLKON |Interrupt Clock On Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + */ + + __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */ + +} GPIO_DBCTL_T; + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __GPIO_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h new file mode 100644 index 0000000000..01aab99e31 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h @@ -0,0 +1,397 @@ +/**************************************************************************//** + * @file hsotg_reg.h + * @version V1.00 + * @brief HSOTG register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSOTG_REG_H__ +#define __HSOTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG) + Memory Mapped Structure for HSOTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSOTG_T::CTL + * Offset: 0x00 HSOTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var HSOTG_T::PHYCTL + * Offset: 0x04 HSOTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var HSOTG_T::INTEN + * Offset: 0x08 HSOTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var HSOTG_T::INTSTS + * Offset: 0x0C HSOTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var HSOTG_T::STATUS + * Offset: 0x10 HSOTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */ + +} HSOTG_T; + +/** + @addtogroup HSOTG_CONST HSOTG Bit Field Definition + Constant Definitions for HSOTG Controller +@{ */ + +#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */ +#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */ + +#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */ +#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */ + +#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */ +#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */ + +#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */ +#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */ + +#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */ +#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */ + +#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */ +#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */ + +#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */ +#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */ + +#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */ +#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */ + +#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */ +#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */ + +#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */ +#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */ + +#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */ +#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */ + +#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */ +#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */ + +#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */ +#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */ + +#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */ +#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */ + +#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */ +#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */ + +#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */ +#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */ + +#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */ +#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */ + +#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */ +#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */ + +#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */ +#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */ + +#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */ +#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */ + +#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */ +#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */ + +#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */ +#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */ + +#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */ +#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */ + +#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */ +#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */ + +#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */ +#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */ + +#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */ +#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */ + +#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */ +#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */ + +#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */ +#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */ + +#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */ +#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */ + +#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */ +#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */ + +#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */ +#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */ + +#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */ +#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */ + +#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */ +#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */ + +#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */ +#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */ + +#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */ +#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */ + +#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */ +#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */ + +#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */ +#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */ + +#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */ +#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */ + +#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */ +#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */ + +#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */ +#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */ + +#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */ +#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */ + +#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */ +#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */ + +#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */ +#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* HSOTG_CONST */ +/**@}*/ /* end of HSOTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSOTG_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbd_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbd_reg.h new file mode 100644 index 0000000000..052f987660 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbd_reg.h @@ -0,0 +1,1380 @@ +/**************************************************************************//** + * @file hsusbd_reg.h + * @version V1.00 + * @brief HSUSBD register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_REG_H__ +#define __HSUSBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD) + Memory Mapped Structure for HSUSBD Controller +@{ */ + +typedef struct +{ + + /** + * @var HSUSBD_EP_T::EPDAT + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_EP_T::EPDAT_BYTE + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_EP_T::EPINTSTS + * Offset: 0x04 Endpoint n Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIF |Buffer Full + * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write) + * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). + * | | |0 = The endpoint packet buffer is not full. + * | | |1 = The endpoint packet buffer is full. + * | | |Note: This bit is read-only. + * |[1] |BUFEMPTYIF|Buffer Empty + * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. + * | | |0 = The endpoint buffer is not empty. + * | | |1 = The endpoint buffer is empty. + * | | |For an OUT endpoint: + * | | |0 = The currently selected buffer has not a count of 0. + * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). + * | | |Note: This bit is read-only. + * |[2] |SHORTTXIF |Short Packet Transferred Interrupt + * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). + * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is transmitted from the endpoint to the host. + * | | |1 = A data packet is transmitted from the endpoint to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |RXPKIF |Data Packet Received Interrupt + * | | |0 = No data packet is received from the host by the endpoint. + * | | |1 = A data packet is received from the host by the endpoint. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |OUTTKIF |Data OUT Token Interrupt + * | | |0 = A Data OUT token has not been received from the host. + * | | |1 = A Data OUT token has been received from the host + * | | |This bit also set by PING token (in high-speed only). + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |INTKIF |Data IN Token Interrupt + * | | |0 = Not Data IN token has been received from the host. + * | | |1 = A Data IN token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |PINGIF |PING Token Interrupt + * | | |0 = A Data PING token has not been received from the host. + * | | |1 = A Data PING token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |NAKIF |USB NAK Sent + * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK. + * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |STALLIF |USB STALL Sent + * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |NYETIF |NYET Sent + * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. + * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |ERRIF |ERR Sent + * | | |0 = No any error in the transaction. + * | | |1 = There occurs any error in the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |SHORTRXIF |Bulk Out Short Packet Received + * | | |0 = No bulk out short packet is received. + * | | |1 = Received bulk out short packet (including zero length packet). + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_EP_T::EPINTEN + * Offset: 0x08 Endpoint n Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIEN|Buffer Full Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. + * | | |0 = Buffer full interrupt Disabled. + * | | |1 = Buffer full interrupt Enabled. + * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. + * | | |0 = Buffer empty interrupt Disabled. + * | | |1 = Buffer empty interrupt Enabled. + * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. + * | | |0 = Short data packet interrupt Disabled. + * | | |1 = Short data packet interrupt Enabled. + * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host. + * | | |0 = Data packet has been received from the host interrupt Disabled. + * | | |1 = Data packet has been received from the host interrupt Enabled. + * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. + * | | |0 = Data packet has been transmitted to the host interrupt Disabled. + * | | |1 = Data packet has been transmitted to the host interrupt Enabled. + * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. + * | | |0 = Data OUT token interrupt Disabled. + * | | |1 = Data OUT token interrupt Enabled. + * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. + * | | |0 = Data IN token interrupt Disabled. + * | | |1 = Data IN token interrupt Enabled. + * |[7] |PINGIEN |PING Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host. + * | | |0 = PING token interrupt Disabled. + * | | |1 = PING token interrupt Enabled. + * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. + * | | |0 = NAK token interrupt Disabled. + * | | |1 = NAK token interrupt Enabled. + * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host. + * | | |0 = STALL token interrupt Disabled. + * | | |1 = STALL token interrupt Enabled. + * |[10] |NYETIEN |NYET Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. + * | | |0 = NYET condition interrupt Disabled. + * | | |1 = NYET condition interrupt Enabled. + * |[11] |ERRIEN |ERR Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. + * | | |0 = Error event interrupt Disabled. + * | | |1 = Error event interrupt Enabled. + * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. + * | | |0 = Bulk out interrupt Disabled. + * | | |1 = Bulk out interrupt Enabled. + * @var HSUSBD_EP_T::EPDATCNT + * Offset: 0x0C Endpoint n Data Available Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Data Count + * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer. + * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer. + * |[30:16] |DMALOOP |DMA Loop + * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. + * @var HSUSBD_EP_T::EPRSPCTL + * Offset: 0x10 Endpoint n Response Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLUSH |Buffer Flush + * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared + * | | |This bit is self-clearing + * | | |This bit should always be written after an configuration event. + * | | |0 = The packet buffer is not flushed. + * | | |1 = The packet buffer is flushed by user. + * |[2:1] |MODE |Mode Control + * | | |The two bits decide the operation mode of the in-endpoint. + * | | |00: Auto-Validate Mode + * | | |01: Manual-Validate Mode + * | | |10: Fly Mode + * | | |11: Reserved + * | | |These bits are not valid for an out-endpoint + * | | |The auto validate mode will be activated when the reserved mode is selected + * |[3] |TOGGLE |Endpoint Toggle + * | | |This bit is used to clear the endpoint data toggle bit + * | | |Reading this bit returns the current state of the endpoint data toggle bit. + * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host + * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. + * | | |0 = Not clear the endpoint data toggle bit. + * | | |1 = Clear the endpoint data toggle bit. + * |[4] |HALT |Endpoint Halt + * | | |This bit is used to send a STALL handshake as response to the token from the host + * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit. + * | | |0 = Not send a STALL handshake as response to the token from the host. + * | | |1 = Send a STALL handshake as response to the token from the host. + * |[5] |ZEROLEN |Zero Length + * | | |This bit is used to send a zero-length packet response to an IN-token + * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token + * | | |This bit gets cleared once the zero length data packet is sent. + * | | |0 = A zero packet is not sent to the host on reception of an IN-token. + * | | |1 = A zero packet is sent to the host on reception of an IN-token. + * |[6] |SHORTTXEN |Short Packet Transfer Enable + * | | |This bit is applicable only in case of Auto-Validate Method + * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer + * | | |This bit gets cleared once the data packet is sent. + * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * |[7] |DISBUF |Buffer Disable Bit + * | | |This bit is used to receive unknown size OUT short packet + * | | |The received packet size is reference USBD_EPxDATCNT register. + * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received. + * | | |1 = Buffer Disabled when Bulk-OUT short packet is received. + * @var HSUSBD_EP_T::EPMPS + * Offset: 0x14 Endpoint n Maximum Packet Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |EPMPS |Endpoint Maximum Packet Size + * | | |This field determines the Maximum Packet Size of the Endpoint. + * @var HSUSBD_EP_T::EPTXCNT + * Offset: 0x18 Endpoint n Transfer Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |TXCNT |Endpoint Transfer Count + * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. + * | | |For OUT endpoints, this field has no effect. + * @var HSUSBD_EP_T::EPCFG + * Offset: 0x1C Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPEN |Endpoint Valid + * | | |When set, this bit enables this endpoint + * | | |This bit has no effect on Endpoint 0, which is always enabled. + * | | |0 = The endpoint Disabled. + * | | |1 = The endpoint Enabled. + * |[2:1] |EPTYPE |Endpoint Type + * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. + * | | |00 = Reserved. + * | | |01 = Bulk. + * | | |10 = Interrupt. + * | | |11 = Isochronous. + * |[3] |EPDIR |Endpoint Direction + * | | |0 = out-endpoint (Host OUT to Device). + * | | |1 = in-endpoint (Host IN to Device). + * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. + * |[7:4] |EPNUM |Endpoint Number + * | | |This field selects the number of the endpoint. Valid numbers 1 to 15. + * | | |Note: Do not support two endpoints have same endpoint number. + * @var HSUSBD_EP_T::EPBUFST + * Offset: 0x20 Endpoint n RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the endpoint A~L. + * @var HSUSBD_EP_T::EPBUFEND + * Offset: 0x24 Endpoint n RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Endpoint End Address + * | | |This is the end-address of the RAM space allocated for the endpoint A~L. + */ + + union + { + __IO uint32_t EPDAT; + __IO uint8_t EPDAT_BYTE; + + }; /*!< [0x0000] Endpoint n Data Register */ + + __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */ + __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */ + __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */ + __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */ + __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */ + __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */ + __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */ + __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */ + __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */ + +} HSUSBD_EP_T; + +typedef struct +{ + + /** + * @var HSUSBD_T::GINTSTS + * Offset: 0x00 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIF |USB Interrupt + * | | |This bit conveys the interrupt status for USB specific events endpoint + * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[1] |CEPIF |Control Endpoint Interrupt + * | | |This bit conveys the interrupt status for control endpoint + * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[2] |EPAIF |Endpoint a Interrupt + * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[3] |EPBIF |Endpoint B Interrupt + * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[4] |EPCIF |Endpoint C Interrupt + * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[5] |EPDIF |Endpoint D Interrupt + * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[6] |EPEIF |Endpoint E Interrupt + * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[7] |EPFIF |Endpoint F Interrupt + * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[8] |EPGIF |Endpoint G Interrupt + * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[9] |EPHIF |Endpoint H Interrupt + * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[10] |EPIIF |Endpoint I Interrupt + * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[11] |EPJIF |Endpoint J Interrupt + * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[12] |EPKIF |Endpoint K Interrupt + * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[13] |EPLIF |Endpoint L Interrupt + * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * @var HSUSBD_T::GINTEN + * Offset: 0x08 Global Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * @var HSUSBD_T::BUSINTSTS + * Offset: 0x10 USB Bus Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIF |SOF Receive Control + * | | |This bit indicates when a start-of-frame packet has been received. + * | | |0 = No start-of-frame packet has been received. + * | | |1 = Start-of-frame packet has been received. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |RSTIF |Reset Status + * | | |When set, this bit indicates that either the USB root port reset is end. + * | | |0 = No USB root port reset is end. + * | | |1 = USB root port reset is end. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |RESUMEIF |Resume + * | | |When set, this bit indicates that a device resume has occurred. + * | | |0 = No device resume has occurred. + * | | |1 = Device resume has occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |SUSPENDIF |Suspend Request + * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset + * | | |This bit is also set when a USB Suspend request is detected from the host. + * | | |0 = No USB Suspend request is detected from the host. + * | | |1= USB Suspend request is detected from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |HISPDIF |High-speed Settle + * | | |0 = No valid high-speed reset protocol is detected. + * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |DMADONEIF |DMA Completion Interrupt + * | | |0 = No DMA transfer over. + * | | |1 = DMA transfer is over. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |PHYCLKVLDIF|Usable Clock Interrupt + * | | |0 = Usable clock is not available. + * | | |1 = Usable clock is available from the transceiver. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |VBUSDETIF |VBUS Detection Interrupt Status + * | | |0 = No VBUS is plug-in. + * | | |1 = VBUS is plug-in. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::BUSINTEN + * Offset: 0x14 USB Bus Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIEN |SOF Interrupt + * | | |This bit enables the SOF interrupt. + * | | |0 = SOF interrupt Disabled. + * | | |1 = SOF interrupt Enabled. + * |[1] |RSTIEN |Reset Status + * | | |This bit enables the USB-Reset interrupt. + * | | |0 = USB-Reset interrupt Disabled. + * | | |1 = USB-Reset interrupt Enabled. + * |[2] |RESUMEIEN |Resume + * | | |This bit enables the Resume interrupt. + * | | |0 = Resume interrupt Disabled. + * | | |1 = Resume interrupt Enabled. + * |[3] |SUSPENDIEN|Suspend Request + * | | |This bit enables the Suspend interrupt. + * | | |0 = Suspend interrupt Disabled. + * | | |1 = Suspend interrupt Enabled. + * |[4] |HISPDIEN |High-speed Settle + * | | |This bit enables the high-speed settle interrupt. + * | | |0 = High-speed settle interrupt Disabled. + * | | |1 = High-speed settle interrupt Enabled. + * |[5] |DMADONEIEN|DMA Completion Interrupt + * | | |This bit enables the DMA completion interrupt + * | | |0 = DMA completion interrupt Disabled. + * | | |1 = DMA completion interrupt Enabled. + * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt + * | | |This bit enables the usable clock interrupt. + * | | |0 = Usable clock interrupt Disabled. + * | | |1 = Usable clock interrupt Enabled. + * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit + * | | |This bit enables the VBUS floating detection interrupt. + * | | |0 = VBUS floating detection interrupt Disabled. + * | | |1 = VBUS floating detection interrupt Enabled. + * @var HSUSBD_T::OPER + * Offset: 0x18 USB Operational Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RESUMEEN |Generate Resume + * | | |0 = No Resume sequence to be initiated to the host. + * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled + * | | |This bit is self-clearing. + * |[1] |HISPDEN |USB High-speed + * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. + * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol. + * |[2] |CURSPD |USB Current Speed + * | | |0 = The device has settled in Full Speed. + * | | |1 = The USB device controller has settled in High-speed. + * @var HSUSBD_T::FRAMECNT + * Offset: 0x1C USB Frame Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |MFRAMECNT |Micro-frame Counter + * | | |This field contains the micro-frame number for the frame number in the frame counter field. + * |[13:3] |FRAMECNT |Frame Counter + * | | |This field contains the frame count from the most recent start-of-frame packet. + * @var HSUSBD_T::FADDR + * Offset: 0x20 USB Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Function Address + * | | |This field contains the current USB address of the device + * | | |This field is cleared when a root port reset is detected + * @var HSUSBD_T::TEST + * Offset: 0x24 USB Test Mode Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TESTMODE |Test Mode Selection + * | | |000 = Normal Operation. + * | | |001 = Test_J. + * | | |010 = Test_K. + * | | |011 = Test_SE0_NAK. + * | | |100 = Test_Packet. + * | | |101 = Test_Force_Enable. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: This field is cleared when root port reset is detected. + * @var HSUSBD_T::CEPDAT + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_T::CEPDAT_BYTE + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_T::CEPCTL + * Offset: 0x2C Control-Endpoint Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NAKCLR |No Acknowledge Control + * | | |This bit plays a crucial role in any control transfer. + * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase + * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. + * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received + * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[1] |STALLEN |Stall Enable Bit + * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter + * | | |This is typically used for response to invalid/unsupported requests + * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL + * | | |It is automatically cleared on receipt of a next setup-token + * | | |So, the local CPU need not write again to clear this bit. + * | | |0 = No sends a stall handshake in response to any in or out token thereafter. + * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[2] |ZEROLEN |Zero Packet Length + * | | |This bit is valid for Auto Validation mode only. + * | | |0 = No zero length packet to the host during Data stage to an IN token. + * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token + * | | |This bit gets cleared once the zero length data packet is sent + * | | |So, the local CPU need not write again to clear this bit. + * |[3] |FLUSH |CEP-flush Bit + * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. + * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared + * | | |This bit is self-cleaning. + * @var HSUSBD_T::CEPINTEN + * Offset: 0x30 Control-Endpoint Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit + * | | |0 = The SETUP token interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP token interrupt in Control Endpoint Enabled. + * |[1] |SETUPPKIEN|Setup Packet Interrupt + * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled. + * |[2] |OUTTKIEN |Out Token Interrupt + * | | |0 = The OUT token interrupt in Control Endpoint Disabled. + * | | |1 = The OUT token interrupt in Control Endpoint Enabled. + * |[3] |INTKIEN |In Token Interrupt + * | | |0 = The IN token interrupt in Control Endpoint Disabled. + * | | |1 = The IN token interrupt in Control Endpoint Enabled. + * |[4] |PINGIEN |Ping Token Interrupt + * | | |0 = The ping token interrupt in Control Endpoint Disabled. + * | | |1 = The ping token interrupt Control Endpoint Enabled. + * |[5] |TXPKIEN |Data Packet Transmitted Interrupt + * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled. + * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled. + * |[6] |RXPKIEN |Data Packet Received Interrupt + * | | |0 = The data received interrupt in Control Endpoint Disabled. + * | | |1 = The data received interrupt in Control Endpoint Enabled. + * |[7] |NAKIEN |NAK Sent Interrupt + * | | |0 = The NAK sent interrupt in Control Endpoint Disabled. + * | | |1 = The NAK sent interrupt in Control Endpoint Enabled. + * |[8] |STALLIEN |STALL Sent Interrupt + * | | |0 = The STALL sent interrupt in Control Endpoint Disabled. + * | | |1 = The STALL sent interrupt in Control Endpoint Enabled. + * |[9] |ERRIEN |USB Error Interrupt + * | | |0 = The USB Error interrupt in Control Endpoint Disabled. + * | | |1 = The USB Error interrupt in Control Endpoint Enabled. + * |[10] |STSDONEIEN|Status Completion Interrupt + * | | |0 = The Status Completion interrupt in Control Endpoint Disabled. + * | | |1 = The Status Completion interrupt in Control Endpoint Enabled. + * |[11] |BUFFULLIEN|Buffer Full Interrupt + * | | |0 = The buffer full interrupt in Control Endpoint Disabled. + * | | |1 = The buffer full interrupt in Control Endpoint Enabled. + * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |0 = The buffer empty interrupt in Control Endpoint Disabled. + * | | |1= The buffer empty interrupt in Control Endpoint Enabled. + * @var HSUSBD_T::CEPINTSTS + * Offset: 0x34 Control-Endpoint Interrupt Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIF |Setup Token Interrupt + * | | |0 = Not a Setup token is received. + * | | |1 = A Setup token is received. Writing 1 clears this status bit + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |SETUPPKIF |Setup Packet Interrupt + * | | |This bit must be cleared (by writing 1) before the next setup packet can be received + * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. + * | | |0 = Not a Setup packet has been received from the host. + * | | |1 = A Setup packet has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |OUTTKIF |Out Token Interrupt + * | | |0 = The control-endpoint does not received an OUT token from the host. + * | | |1 = The control-endpoint receives an OUT token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |INTKIF |in Token Interrupt + * | | |0 = The control-endpoint does not received an IN token from the host. + * | | |1 = The control-endpoint receives an IN token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |PINGIF |Ping Token Interrupt + * | | |0 = The control-endpoint does not received a ping token from the host. + * | | |1 = The control-endpoint receives a ping token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |RXPKIF |Data Packet Received Interrupt + * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |NAKIF |NAK Sent Interrupt + * | | |0 = Not a NAK-token is sent in response to an IN/OUT token. + * | | |1 = A NAK-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |STALLIF |STALL Sent Interrupt + * | | |0 = Not a stall-token is sent in response to an IN/OUT token. + * | | |1 = A stall-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |ERRIF |USB Error Interrupt + * | | |0 = No error had occurred during the transaction. + * | | |1 = An error had occurred during the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |STSDONEIF |Status Completion Interrupt + * | | |0 = Not a USB transaction has completed successfully. + * | | |1 = The status stage of a USB transaction has completed successfully. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |BUFFULLIF |Buffer Full Interrupt + * | | |0 = The control-endpoint buffer is not full. + * | | |1 = The control-endpoint buffer is full. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |BUFEMPTYIF|Buffer Empty Interrupt + * | | |0 = The control-endpoint buffer is not empty. + * | | |1 = The control-endpoint buffer is empty. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::CEPTXCNT + * Offset: 0x38 Control-Endpoint In-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TXCNT |In-transfer Data Count + * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register + * | | |When zero is written into this field, a zero length packet is sent to the host + * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS. + * @var HSUSBD_T::CEPRXCNT + * Offset: 0x3C Control-Endpoint Out-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RXCNT |Out-transfer Data Count + * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. + * @var HSUSBD_T::CEPDATCNT + * Offset: 0x40 Control-Endpoint data count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Control-endpoint Data Count + * | | |The USB device controller maintains the count of the data of control-endpoint. + * @var HSUSBD_T::SETUP1_0 + * Offset: 0x44 Setup1 & Setup0 bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP0 |Setup Byte 0[7:0] + * | | |This register provides byte 0 of the last setup packet received + * | | |For a Standard Device Request, the following bmRequestType information is returned. + * | | |Bit 7(Direction): + * | | | 0: Host to device + * | | | 1: Device to host + * | | |Bit 6-5 (Type): + * | | | 00: Standard + * | | | 01: Class + * | | | 10: Vendor + * | | | 11: Reserved + * | | |Bit 4-0 (Recipient) + * | | | 00000: Device + * | | | 00001: Interface + * | | | 00010: Endpoint + * | | | 00011: Other + * | | | Others: Reserved + * |[15:8] |SETUP1 |Setup Byte 1[15:8] + * | | |This register provides byte 1 of the last setup packet received + * | | |For a Standard Device Request, the following bRequest Code information is returned. + * | | |00000000 = Get Status. + * | | |00000001 = Clear Feature. + * | | |00000010 = Reserved. + * | | |00000011 = Set Feature. + * | | |00000100 = Reserved. + * | | |00000101 = Set Address. + * | | |00000110 = Get Descriptor. + * | | |00000111 = Set Descriptor. + * | | |00001000 = Get Configuration. + * | | |00001001 = Set Configuration. + * | | |00001010 = Get Interface. + * | | |00001011 = Set Interface. + * | | |00001100 = Sync Frame. + * @var HSUSBD_T::SETUP3_2 + * Offset: 0x48 Setup3 & Setup2 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP2 |Setup Byte 2 [7:0] + * | | |This register provides byte 2 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wValue field is returned + * |[15:8] |SETUP3 |Setup Byte 3 [15:8] + * | | |This register provides byte 3 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wValue field is returned. + * @var HSUSBD_T::SETUP5_4 + * Offset: 0x4C Setup5 & Setup4 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP4 |Setup Byte 4[7:0] + * | | |This register provides byte 4 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wIndex is returned. + * |[15:8] |SETUP5 |Setup Byte 5[15:8] + * | | |This register provides byte 5 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned. + * @var HSUSBD_T::SETUP7_6 + * Offset: 0x50 Setup7 & Setup6 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP6 |Setup Byte 6[7:0] + * | | |This register provides byte 6 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wLength field is returned. + * |[15:8] |SETUP7 |Setup Byte 7[15:8] + * | | |This register provides byte 7 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wLength field is returned. + * @var HSUSBD_T::CEPBUFST + * Offset: 0x54 Control Endpoint RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Control-endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::CEPBUFEND + * Offset: 0x58 Control Endpoint RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Control-endpoint End Address + * | | |This is the end-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::DMACTL + * Offset: 0x5C DMA Control Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |DMA Endpoint Address Bits + * | | |Used to define the Endpoint Address + * |[4] |DMARD |DMA Operation + * | | |0 : The operation is a DMA write (read from USB buffer) + * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. + * | | |1 : The operation is a DMA read (write to USB buffer). + * |[5] |DMAEN |DMA Enable Bit + * | | |0 : DMA function Disabled. + * | | |1 : DMA function Enabled. + * |[6] |SGEN |Scatter Gather Function Enable Bit + * | | |0 : Scatter gather function Disabled. + * | | |1 : Scatter gather function Enabled. + * |[7] |DMARST |Reset DMA State Machine + * | | |0 : No reset the DMA state machine. + * | | |1 : Reset the DMA state machine. + * |[8] |SVINEP |Serve IN Endpoint + * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. + * | | |0: DMA serves OUT endpoint + * | | |1: DMA serves IN endpoint + * @var HSUSBD_T::DMACNT + * Offset: 0x60 DMA Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |DMACNT |DMA Transfer Count + * | | |The transfer count of the DMA operation to be performed is written to this register. + * @var HSUSBD_T::DMAADDR + * Offset: 0x700 AHB DMA Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMAADDR |DMAADDR + * | | |The register specifies the address from which the DMA has to read / write + * | | |The address must WORD (32-bit) aligned. + * @var HSUSBD_T::PHYCTL + * Offset: 0x704 USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |DPPUEN |DP Pull-up + * | | |0 = Pull-up resistor on D+ Disabled. + * | | |1 = Pull-up resistor on D+ Enabled. + * |[9] |PHYEN |PHY Suspend Enable Bit + * | | |0 = The USB PHY is suspend. + * | | |1 = The USB PHY is not suspend. + * |[24] |WKEN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * |[31] |VBUSDET |VBUS Status + * | | |0 = The VBUS is not detected yet. + * | | |1 = The VBUS is detected. + */ + + __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */ + __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */ + __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */ + __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */ + __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */ + __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */ + + union + { + __IO uint32_t CEPDAT; + __IO uint8_t CEPDAT_BYTE; + + }; /*!< [0x0028] Control-Endpoint Data Buffer */ + + __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */ + __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */ + __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */ + __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */ + __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */ + __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */ + __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */ + __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */ + __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */ + __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */ + __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */ + __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */ + __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */ + __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */ + + HSUSBD_EP_T EP[12]; + + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[303]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */ + __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */ + +} HSUSBD_T; + +/** + @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition + Constant Definitions for HSUSBD Controller +@{ */ + +#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */ +#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */ + +#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */ +#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */ + +#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */ +#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */ + +#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */ +#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */ + +#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */ +#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */ + +#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */ +#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */ + +#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */ +#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */ + +#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */ +#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */ + +#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */ +#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */ + +#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */ +#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */ + +#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */ +#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */ + +#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */ +#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */ + +#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */ +#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */ + +#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */ +#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */ + +#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */ +#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */ + +#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */ +#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */ + +#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */ +#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */ + +#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */ +#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */ + +#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */ +#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */ + +#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */ +#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */ + +#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */ +#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */ + +#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */ +#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */ + +#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */ +#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */ + +#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */ +#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */ + +#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */ +#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */ + +#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */ +#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */ + +#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */ +#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */ + +#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */ +#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */ + +#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */ +#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */ + +#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */ +#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */ + +#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */ +#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */ + +#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/ +#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */ + +#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */ +#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */ + +#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/ +#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */ + +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/ +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */ + +#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/ +#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */ + +#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */ +#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */ + +#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */ +#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */ + +#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */ +#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */ + +#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/ +#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */ + +#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */ +#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */ + +#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/ +#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */ + +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/ +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */ + +#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/ +#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */ + +#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */ +#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */ + +#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */ +#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */ + +#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */ +#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */ + +#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */ +#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */ + +#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */ +#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */ + +#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */ +#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */ + +#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */ +#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */ + +#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */ +#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */ + +#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */ +#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */ + +#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */ +#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */ + +#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */ +#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */ + +#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */ +#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */ + +#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */ + +#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */ + +#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */ +#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */ +#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */ + +#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */ +#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */ + +#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */ +#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */ +#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */ +#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */ + +#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */ +#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */ + +#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */ +#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */ + +#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/ +#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/ +#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */ + +#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */ + +#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */ +#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */ +#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */ + +#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */ +#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */ + +#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */ +#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */ +#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */ +#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */ + +#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */ +#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */ + +#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */ +#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */ + +#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/ +#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/ +#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */ +#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */ + +#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */ +#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */ + +#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */ +#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */ + +#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */ +#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */ + +#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */ +#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */ + +#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */ +#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */ + +#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */ +#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */ + +#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */ +#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */ + +#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */ +#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */ + +#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */ +#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */ + +#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */ +#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */ + +#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */ +#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */ + +#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */ +#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */ + +#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */ +#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */ + +#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */ +#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */ + +#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */ +#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */ + +#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */ +#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */ + +#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */ +#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */ + +#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */ +#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */ + +#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */ +#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */ + +#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */ +#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */ + +#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */ +#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */ +#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */ + +#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */ +#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */ + +#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */ +#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */ + +#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */ +#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */ +#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */ + +#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */ +#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */ + +#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */ +#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */ + +#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */ +#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */ + +#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */ +#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */ + +#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */ +#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */ +#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */ + +#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */ +#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */ +#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */ + +#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */ +#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */ + +#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */ +#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */ + +#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */ +#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */ +#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */ + +#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */ +#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */ + +#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */ +#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */ + +#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */ +#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */ + +#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */ +#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */ + +#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */ +#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */ +#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */ + +#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */ +#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */ + +#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */ +#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */ + +#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */ +#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */ + +#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */ +#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */ + +#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */ +#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */ + +#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */ +#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */ + +#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */ +#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */ + +#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */ +#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */ + +#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */ +#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */ + +#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */ +#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */ + +#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */ +#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */ + +#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */ +#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */ + +#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */ +#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */ + +#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */ +#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */ + +#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */ +#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */ + +#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */ +#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */ + +#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */ +#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */ + +#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */ +#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */ + +#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */ +#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */ + +#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */ +#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */ + +#define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */ +#define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */ + +#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */ +#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */ + +/**@}*/ /* HSUSBD_CONST */ +/**@}*/ /* end of HSUSBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBD_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbh_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbh_reg.h new file mode 100644 index 0000000000..245c8a5c03 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbh_reg.h @@ -0,0 +1,652 @@ +/**************************************************************************//** + * @file hsusbh_reg.h + * @version V1.00 + * @brief HSUSBH register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBH_REG_H__ +#define __HSUSBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH) + Memory Mapped Structure for HSUSBH Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSUSBH_T::EHCVNR + * Offset: 0x00 EHCI Version Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CRLEN |Capability Registers Length + * | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space. + * |[31:16] |VERSION |Host Controller Interface Version Number + * | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller + * | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision. + * @var HSUSBH_T::EHCSPR + * Offset: 0x04 EHCI Structural Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |N_PORTS |Number of Physical Downstream Ports + * | | |This field specifies the number of physical downstream ports implemented on this host controller + * | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8) + * | | |Valid values are in the range of 1H to FH. + * | | |A zero in this field is undefined. + * |[4] |PPC |Port Power Control + * | | |This field indicates whether the host controller implementation includes port power control + * | | |A one in this bit indicates the ports have port power switches + * | | |A zero in this bit indicates the port do not have port power stitches + * | | |The value of this field affects the functionality of the Port Power field in each port status and control register. + * |[11:8] |N_PCC |Number of Ports Per Companion Controller + * | | |This field indicates the number of ports supported per companion host controller + * | | |It is used to indicate the port routing configuration to system software. + * | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3 + * | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc + * | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. + * | | |The number in this field must be consistent with N_PORTS and N_CC. + * |[15:12] |N_CC |Number of Companion Controller + * | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller. + * | | |A zero in this field indicates there are no companion host controllers + * | | |Port-ownership hand-off is not supported + * | | |Only high-speed devices are supported on the host controller root ports. + * | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s) + * | | |Port-ownership hand-offs are supported + * | | |High, Full- and Low-speed devices are supported on the host controller root ports. + * @var HSUSBH_T::EHCCPR + * Offset: 0x08 EHCI Capability Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AC64 |64-bit Addressing Capability + * | | |0 = Data structure using 32-bit address memory pointers. + * |[1] |PFLF |Programmable Frame List Flag + * | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller. + * |[2] |ASPC |Asynchronous Schedule Park Capability + * | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule. + * |[7:4] |IST |Isochronous Scheduling Threshold + * | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. + * | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. + * |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP) + * | | |0 = No extended capabilities are implemented. + * @var HSUSBH_T::UCMDR + * Offset: 0x20 USB Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RUN |Run/Stop (R/W) + * | | |When set to a 1, the Host Controller proceeds with execution of the schedule + * | | |The Host Controller continues execution as long as this bit is set to a 1 + * | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts + * | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit + * | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state + * | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e. + * | | |HCHalted in the USBSTS register is a one) + * | | |Doing so will yield undefined results. + * | | |0 = Stop. + * | | |1 = Run. + * |[1] |HCRST |Host Controller Reset (HCRESET) (R/W) + * | | |This control bit is used by software to reset the host controller + * | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset. + * | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc + * | | |to their initial value + * | | |Any transaction currently in progress on USB is immediately terminated + * | | |A USB reset is not driven on downstream ports. + * | | |All operational registers, including port registers and port state machines are set to their initial values + * | | |Port ownership reverts to the companion host controller(s), with the side effects + * | | |Software must reinitialize the host controller in order to return the host controller to an operational state. + * | | |This bit is set to zero by the Host Controller when the reset process is complete + * | | |Software cannot terminate the reset process early by writing a zero to this register. + * | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero + * | | |Attempting to reset an actively running host controller will result in undefined behavior. + * |[3:2] |FLSZ |Frame List Size (R/W or RO) + * | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one + * | | |This field specifies the size of the frame list + * | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index + * | | |Values mean: + * | | |00 = 1024 elements (4096 bytes) Default value. + * | | |01 = 512 elements (2048 bytes). + * | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment. + * | | |11 = Reserved. + * |[4] |PSEN |Periodic Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: + * | | |0 = Do not process the Periodic Schedule. + * | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. + * |[5] |ASEN |Asynchronous Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: + * | | |0 = Do not process the Asynchronous Schedule. + * | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + * |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W) + * | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule + * | | |Software must write a 1 to this bit to ring the doorbell. + * | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register + * | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. + * | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one. + * | | |Software should not write a one to this bit when the asynchronous schedule is disabled + * | | |Doing so will yield undefined results. + * |[23:16] |ITC |Interrupt Threshold Control (R/W) + * | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts + * | | |The only valid values are defined below + * | | |If software writes an invalid value to this register, the results are undefined + * | | |Value Maximum Interrupt Interval + * | | |0x00 = Reserved. + * | | |0x01 = 1 micro-frame. + * | | |0x02 = 2 micro-frames. + * | | |0x04 = 4 micro-frames. + * | | |0x08 = 8 micro-frames (default, equates to 1 ms). + * | | |0x10 = 16 micro-frames (2 ms). + * | | |0x20 = 32 micro-frames (4 ms). + * | | |0x40 = 64 micro-frames (8 ms). + * | | |Any other value in this register yields undefined results. + * | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior. + * @var HSUSBH_T::USTSR + * Offset: 0x24 USB Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBINT |USB Interrupt (USBINT) (R/WC) + * | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. + * | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). + * |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC) + * | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow) + * | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. + * |[2] |PCD |Port Change Detect (R/WC) + * | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port + * | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit. + * | | |This bit is allowed to be maintained in the Auxiliary power well + * | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change). + * |[3] |FLR |Frame List Rollover (R/WC) + * | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero + * | | |The exact value at which the rollover occurs depends on the frame list size + * | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles + * | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. + * |[4] |HSERR |Host System Error (R/WC) + * | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. + * |[5] |IAA |Interrupt on Asynchronous Advance (R/WC) + * | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register + * | | |This status bit indicates the assertion of that interrupt source. + * |[12] |HCHalted |HCHalted (RO) + * | | |This bit is a zero whenever the Run/Stop bit is a one + * | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. + * | | |internal error). + * |[13] |RECLA |Reclamation (RO) + * | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule. + * |[14] |PSS |Periodic Schedule Status (RO) + * | | |The bit reports the current real status of the Periodic Schedule + * | | |If this bit is a zero then the status of the Periodic Schedule is disabled + * | | |If this bit is a one then the status of the Periodic Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register + * | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * |[15] |ASS |Asynchronous Schedule Status (RO) + * | | |The bit reports the current real status of the Asynchronous Schedule + * | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled + * | | |If this bit is a one then the status of the Asynchronous Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register + * | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * @var HSUSBH_T::UIENR + * Offset: 0x28 USB Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBINT bit. + * | | |0 = USB interrupt Disabled. + * | | |1 = USB interrupt Enabled. + * |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBERRINT bit. + * | | |0 = USB Error interrupt Disabled. + * | | |1 = USB Error interrupt Enabled. + * |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Port Change Detect bit. + * | | |0 = Port Change interrupt Disabled. + * | | |1 = Port Change interrupt Enabled. + * |[3] |FLREN |Frame List Rollover Enable or Disable Bit + * | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit. + * | | |0 = Frame List Rollover interrupt Disabled. + * | | |1 = Frame List Rollover interrupt Enabled. + * |[4] |HSERREN |Host System Error Enable or Disable Bit + * | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Host System Error bit. + * | | |0 = Host System Error interrupt Disabled. + * | | |1 = Host System Error interrupt Enabled. + * |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit + * | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit. + * | | |0 = Interrupt on Asynchronous Advance Disabled. + * | | |1 = Interrupt on Asynchronous Advance Enabled. + * @var HSUSBH_T::UFINDR + * Offset: 0x2C USB Frame Index Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Index + * | | |The value in this register increment at the end of each time frame (e.g. + * | | |micro-frame) + * | | |Bits [N:3] are used for the Frame List current index + * | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index + * | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. + * | | |FLSZ (UCMDR[3:2] Number Elements N + * | | |0x0 1024 12 + * | | |0x1 512 11 + * | | |0x2 256 10 + * | | |0x3 Reserved + * @var HSUSBH_T::UPFLBAR + * Offset: 0x34 USB Periodic Frame List Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |BADDR |Base Address + * | | |These bits correspond to memory address signals [31:12], respectively. + * @var HSUSBH_T::UCALAR + * Offset: 0x38 USB Current Asynchronous List Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:5] |LPL |Link Pointer Low (LPL) + * | | |These bits correspond to memory address signals [31:5], respectively + * | | |This field may only reference a Queue Head (QH). + * @var HSUSBH_T::UASSTR + * Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer + * | | |This field defines the AsyncSchedSleepTime of EHCI spec. + * | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty. + * | | |The default value of this timer is 12'hBD6 + * | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us. + * @var HSUSBH_T::UCFGR + * Offset: 0x60 USB Configure Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CF |Configure Flag (CF) + * | | |Host software sets this bit as the last action in its process of configuring the Host Controller + * | | |This bit controls the default port-routing control logic + * | | |Bit values and side-effects are listed below. + * | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller. + * | | |1 = Port routing control logic default-routes all ports to this host controller. + * @var HSUSBH_T::UPSCR[2] + * Offset: 0x64~0x68 USB Port 0~1 Status and Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status (RO) + * | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * | | |This field is zero if Port Power is zero. + * | | |0 = No device is present. + * | | |1 = Device is present on port. + * |[1] |CSC |Connect Status Change (R/W) + * | | |Indicates a change has occurred in the port's Current Connect Status + * | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change + * | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Change in Current Connect Status. + * |[2] |PE |Port Enabled/Disabled (R/W) + * | | |Ports can only be enabled by the host controller as a part of the reset and enable + * | | |Software cannot enable a port by writing a one to this field + * | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. + * | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software + * | | |Note that the bit status does not change until the port state actually changes + * | | |There may be a delay in disabling or enabling a port due to other host controller and bus events. + * | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[3] |PEC |Port Enable/Disable Change (R/WC) + * | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error) + * | | |Software clears this bit by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Port enabled/disabled status has changed. + * |[4] |OCA |Over-current Active (RO) + * | | |This bit will automatically transition from a one to a zero when the over current condition is removed. + * | | |0 = This port does not have an over-current condition. + * | | |1 = This port currently has an over-current condition. + * |[5] |OCC |Over-current Change (R/WC) + * | | |1 = This bit gets set to a one when there is a change to Over-current Active + * | | |Software clears this bit by writing a one to this bit position. + * |[6] |FPR |Force Port Resume (R/W) + * | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit + * | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. + * | | |Software sets this bit to a 1 to drive resume signaling + * | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state + * | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one + * | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit. + * | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0 + * | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one + * | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed + * | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle) + * | | |This bit will remain a one until the port has switched to the high-speed idle + * | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. + * | | |This field is zero if Port Power is zero. + * | | |0 = No resume (K-state) detected/driven on port. + * | | |1 = Resume detected/driven on port. + * |[7] |SUSPEND |Suspend (R/W) + * | | |Port Enabled Bit and Suspend bit of this register define the port states as follows: + * | | |Port enable is 0 and suspend is 0 = Disable. + * | | |Port enable is 0 and suspend is 1 = Disable. + * | | |Port enable is 1 and suspend is 0 = Enable. + * | | |Port enable is 1 and suspend is 1 = Suspend. + * | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset + * | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1 + * | | |In the suspend state, the port is sensitive to resume detection + * | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * | | |A write of zero to this bit is ignored by the host controller + * | | |The host controller will unconditionally set this bit to a zero when: + * | | |Software sets the Force Port Resume bit to a zero (from a one). + * | | |Software sets the Port Reset bit to a one (from a zero). + * | | |If host software sets this bit to a one when the port is not enabled (i.e. + * | | |Port enabled bit is a zero) the results are undefined. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port not in suspend state. + * | | |1 = Port in suspend state. + * |[8] |PRST |Port Reset (R/W) + * | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started + * | | |Software writes a zero to this bit to terminate the bus reset sequence + * | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes + * | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. + * | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero + * | | |The bit status will not read as a zero until after the reset has completed + * | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. + * | | |set the Port Enable bit to a one) + * | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero + * | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. + * | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit + * | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port is not in Reset. + * | | |1 = Port is in Reset. + * |[11:10] |LSTS |Line Status (RO) + * | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines + * | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence + * | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. + * | | |The encoding of the bits are: + * | | |Bits[11:10] USB State Interpretation + * | | |00 = SE0 Not Low-speed device, perform EHCI reset. + * | | |01 = K-state Low-speed device, release ownership of port. + * | | |10 = J-state Not Low-speed device, perform EHCI reset. + * | | |11 = Undefined Not Low-speed device, perform EHCI reset. + * | | |This value of this field is undefined if Port Power is zero. + * |[12] |PP |Port Power (PP) + * | | |Host controller has port power control switches + * | | |This bit represents the Current setting of the switch (0 = off, 1 = on) + * | | |When power is not available on a port (i.e. + * | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. + * | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port). + * |[13] |PO |Port Owner (R/W) + * | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition + * | | |This bit unconditionally goes to 1 whenever the Configured bit is zero. + * | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device) + * | | |Software writes a one to this bit when the attached device is not a high-speed device + * | | |A one in this bit means that a companion host controller owns and controls the port. + * |[19:16] |PTC |Port Test Control (R/W) + * | | |When this field is zero, the port is NOT operating in a test mode + * | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value + * | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved): + * | | |Bits Test Mode + * | | |0x0 = Test mode not enabled. + * | | |0x1 = Test J_STATE. + * | | |0x2 = Test K_STATE. + * | | |0x3 = Test SE0_NAK. + * | | |0x4 = Test Packet. + * | | |0x5 = Test FORCE_ENABLE. + * @var HSUSBH_T::USBPCR0 + * Offset: 0xC4 USB PHY 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 0. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 0 was suspended. + * | | |1 = USB PHY 0 was not suspended. + * |[11] |CLKVALID |UTMI Clock Valid + * | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready + * | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active. + * | | |0 = UTMI clock is not valid. + * | | |1 = UTMI clock is valid. + * @var HSUSBH_T::USBPCR1 + * Offset: 0xC8 USB PHY 1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 1. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 1 was suspended. + * | | |1 = USB PHY 1 was not suspended. + */ + __I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */ + __I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */ + __I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */ + __IO uint32_t USTSR; /*!< [0x0024] USB Status Register */ + __IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */ + __IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */ + __IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */ + __IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */ + __IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[22]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */ + __IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */ + +} HSUSBH_T; + +/** + @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition + Constant Definitions for HSUSBH Controller +@{ */ + +#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */ +#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */ + +#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */ +#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */ + +#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */ +#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */ + +#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */ +#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */ + +#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */ +#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */ + +#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */ +#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */ + +#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */ +#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */ + +#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */ +#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */ + +#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */ +#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */ + +#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */ +#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */ + +#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */ +#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */ + +#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */ +#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */ + +#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */ +#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */ + +#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */ +#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */ + +#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */ +#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */ + +#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */ +#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */ + +#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */ +#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */ + +#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */ +#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */ + +#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */ +#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */ + +#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */ +#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */ + +#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */ +#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */ + +#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */ +#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */ + +#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */ +#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */ + +#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */ +#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */ + +#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */ +#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */ + +#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */ +#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */ + +#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */ +#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */ + +#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */ +#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */ + +#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */ +#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */ + +#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */ +#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */ + +#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */ +#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */ + +#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */ +#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */ + +#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */ +#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */ + +#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */ +#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */ + +#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */ +#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */ + +#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */ +#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */ + +#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */ +#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */ + +#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */ +#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */ + +#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */ +#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */ + +#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */ +#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */ + +#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */ +#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */ + +#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */ +#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */ + +#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */ +#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */ + +#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */ +#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */ + +#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */ +#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */ + +#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */ +#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */ + +#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */ +#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */ + +#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */ +#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */ + +#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */ +#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */ + +#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */ +#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */ + +#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */ +#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */ + +#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */ +#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */ + +#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */ +#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */ + +#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */ +#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */ + +#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */ +#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */ + +/**@}*/ /* HSUSBH_CONST */ +/**@}*/ /* end of HSUSBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBH_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2c_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2c_reg.h new file mode 100644 index 0000000000..e050056474 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2c_reg.h @@ -0,0 +1,724 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2C Inter-IC Bus Controller(I2C) + Memory Mapped Structure for I2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::ADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When Enabled, The time-out period is extend 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear + * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDRMSK0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1 = I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C hold bus after wake-up. + * | | |1 = I2C don't hold bus after wake-up. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function disable. + * | | |1 = Transmit PDMA function enable. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function disable. + * | | |1 = Receive PDMA function enable. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable + * | | |0 = Address match 10-bit function is disabled. + * | | |1 = Address match 10-bit function is enabled. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status Register + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status Register + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[8] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * | | |Note:This bit is read only. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN=0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN=1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function is Disabled. + * | | |1 = The system management function is Enable. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: This bit has no effect in slave mode when ACKMEN=0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled. + * | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Indicates the byte count done interrupt is Disabled. + * | | |1 = Indicates the byte count done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = Indicates the PEC transfer done interrupt is Disabled. + * | | |1 = Indicates the PEC transfer done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Indicates the bus clock low time-out detection is Disabled. + * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. + * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. + * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. + * | | |BUSY =0. + * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. + * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Indicates the clock time out interrupt is Disabled. + * | | |1 = Indicates the clock time out interrupt is Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = Indicates the I2C state machine reset is Disable. + * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = Indicates the PEC value equal the received PEC data packet. + * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: + * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2. Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = Indicates that there is no any time-out or external clock time-out. + * | | |1 = Indicates that a time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Cumulate Time-out Status + * | | |0 = Indicates that the cumulative clock low is no any time-out. + * | | |1 = Indicates that the cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Notice: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ + +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller +@{ */ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2C_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2s_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2s_reg.h new file mode 100644 index 0000000000..c0e57caf9b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2s_reg.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file i2s_reg.h + * @version V1.00 + * @brief I2S register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2S I2S Interface Controller(I2S) + Memory Mapped Structure for I2S Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2S_T::CTL0 + * Offset: 0x00 I2S Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Control + * | | |0 = I2S controller Disabled. + * | | |1 = I2S controller Enabled. + * |[1] |TXEN |Transmit Enable Control + * | | |0 = Data transmission Disabled. + * | | |1 = Data transmission Enabled. + * |[2] |RXEN |Receive Enable Control + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable Control + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |DATWIDTH |Data Width + * | | |This bit field is used to define the bit-width of data word in each audio channel + * | | |00 = The bit-width of data word is 8-bit. + * | | |01 = The bit-width of data word is 16-bit. + * | | |10 = The bit-width of data word is 24-bit. + * | | |11 = The bit-width of data word is 32-bit. + * |[6] |MONO |Monaural Data Control + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte + * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. + * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. + * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. + * | | |1 = Even channel data at low byte. + * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. + * |[8] |SLAVE |Slave Mode Enable Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * | | |Note: I2S can operate as master or slave + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. + * |[15] |MCLKEN |Master Clock Enable Control + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[18] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear TX FIFO. + * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |Note2: This bit is clear by hardware automatically, read it return zero. + * |[19] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear RX FIFO. + * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. + * | | |Note2: This bit is cleared by hardware automatically, read it return zero. + * |[20] |TXPDMAEN |Transmit PDMA Enable Control + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[21] |RXPDMAEN |Receive PDMA Enable Control + * | | |0 = Receiver PDMA function Disabled. + * | | |1 = Receiver PDMA function Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Control + * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. + * | | |0 = Receives channel1 data in MONO mode. + * | | |1 = Receives channel0 data in MONO mode. + * |[26:24] |FORMAT |Data Format Selection + * | | |000 = I2S standard data format. + * | | |001 = I2S with MSB justified. + * | | |010 = I2S with LSB justified. + * | | |011 = Reserved. + * | | |100 = PCM standard data format. + * | | |101 = PCM with MSB justified. + * | | |110 = PCM with LSB justified. + * | | |111 = Reserved. + * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection + * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol + * | | |0 = One BCLK period. + * | | |1 = One channel period. + * | | |Note: This bit is only available in master mode + * |[29:28] |CHWIDTH |Channel Width + * | | |This bit fields are used to define the length of audio channel + * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. + * | | |00 = The bit-width of each audio channel is 8-bit. + * | | |01 = The bit-width of each audio channel is 16-bit. + * | | |10 = The bit-width of each audio channel is 24-bit. + * | | |11 = The bit-width of each audio channel is 32-bit. + * |[31:30] |TDMCHNUM |TDM Channel Number + * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). + * | | |00 = 2 channels in audio frame. + * | | |01 = 4 channels in audio frame. + * | | |10 = 6 channels in audio frame. + * | | |11 = 8 channels in audio frame. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MCLKDIV |Master Clock Divider + * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip + * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. + * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. + * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK + * |[16:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 + * | | |If RXTHIEN bit is enabled, interrupt occur. + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note2: Write 1 to clear this bit to zero + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. + * | | |Note2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is not higher than threshold level. + * | | |1 = Data word(s) in FIFO is higher than threshold level. + * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is zero + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1 + * | | |Note2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is higher than threshold level. + * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. + * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |This bit reflect data word number in transmit FIFO is 16 + * | | |0 = Not full. + * | | |1 = Full. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |This bit reflect data word number in transmit FIFO is zero + * | | |0 = Not empty. + * | | |1 = Empty. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller +@{ */ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2S_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/opa_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/opa_reg.h new file mode 100644 index 0000000000..3f36202d37 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/opa_reg.h @@ -0,0 +1,267 @@ +/**************************************************************************//** + * @file opa_reg.h + * @version V1.00 + * @brief OPA register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_REG_H__ +#define __OPA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OPA OP Amplifier(OPA) + Memory Mapped Structure for OPA Controller +@{ */ + +typedef struct +{ + + + /** + * @var OPA_T::CTL + * Offset: 0x00 OP Amplifier Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPEN0 |OP Amplifier 0 Enable Bit + * | | |0 = OP amplifier0 Disabled. + * | | |1 = OP amplifier0 Enabled. + * | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set. + * |[1] |OPEN1 |OP Amplifier 1 Enable Bit + * | | |0 = OP amplifier1 Disabled. + * | | |1 = OP amplifier1 Enabled. + * | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set. + * |[2] |OPEN2 |OP Amplifier 2 Enable Bit + * | | |0 = OP amplifier2 Disabled. + * | | |1 = OP amplifier2 Enabled. + * | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set. + * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled. + * |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled. + * |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled. + * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 0 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 0 digital output interrupt function Enabled. + * | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated. + * |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 1 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 1 digital output interrupt function Enabled. + * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated. + * |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 2 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 2 digital output interrupt function Enabled. + * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated. + * @var OPA_T::STATUS + * Offset: 0x04 OP Amplifier Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPDO0 |OP Amplifier 0 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0) + * |[1] |OPDO1 |OP Amplifier 1 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0) + * |[2] |OPDO2 |OP Amplifier 2 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0) + * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * @var OPA_T::CALCTL + * Offset: 0x08 OP Amplifier Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance. + * |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance. + * |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance. + * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * @var OPA_T::CALST + * Offset: 0x0C OP Amplifier Calibration Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[4] |DONE1 |OP Amplifier 1 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[8] |DONE2 |OP Amplifier 2 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + */ + __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */ + __IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */ + __I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */ + +} OPA_T; + +/** + @addtogroup OPA_CONST OPA Bit Field Definition + Constant Definitions for OPA Controller +@{ */ + +#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */ +#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */ + +#define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */ +#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */ + +#define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */ +#define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */ + +#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */ +#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */ + +#define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */ +#define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */ + +#define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */ +#define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */ + +#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */ +#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */ + +#define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */ +#define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */ + +#define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */ +#define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */ + +#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */ +#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */ + +#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */ +#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */ + +#define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */ +#define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */ + +#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */ +#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */ + +#define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */ +#define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */ + +#define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */ +#define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */ + +#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */ +#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */ + +#define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */ +#define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */ + +#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */ +#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */ + +#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */ +#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */ + +#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */ +#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */ + +#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */ +#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */ + +#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */ +#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */ + +#define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */ +#define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */ + +#define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */ +#define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */ + +#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */ +#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */ + +#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */ +#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */ + +#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */ +#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */ + +#define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */ +#define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */ + +#define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */ +#define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */ + +#define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */ +#define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */ + +#define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */ +#define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */ + +#define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */ +#define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */ + +#define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */ +#define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */ + +/**@}*/ /* OPA_CONST */ +/**@}*/ /* end of OPA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OPA_REG_H__ */ + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/otg_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/otg_reg.h new file mode 100644 index 0000000000..f88158805f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/otg_reg.h @@ -0,0 +1,398 @@ +/**************************************************************************//** + * @file otg_reg.h + * @version V1.00 + * @brief OTG register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OTG_REG_H__ +#define __OTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OTG USB On-The-Go Controller(OTG) + Memory Mapped Structure for OTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var OTG_T::CTL + * Offset: 0x00 OTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var OTG_T::PHYCTL + * Offset: 0x04 OTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var OTG_T::INTEN + * Offset: 0x08 OTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var OTG_T::INTSTS + * Offset: 0x0C OTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var OTG_T::STATUS + * Offset: 0x10 OTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V, this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ + +} OTG_T; + + +/** + @addtogroup OTG_CONST OTG Bit Field Definition + Constant Definitions for OTG Controller +@{ */ + +#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ +#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ + +#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ +#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ + +#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ +#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ + +#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ +#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ + +#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ +#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ + +#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ +#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ + +#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ +#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ + +#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ +#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ + +#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ +#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ + +#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ +#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ + +#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ +#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ + +#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ +#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ + +#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ +#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ + +#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ +#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ + +#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ +#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ + +#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ +#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ + +#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ +#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ + +#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ +#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ + +#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ +#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ + +#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ +#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ + +#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ +#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ + +#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ +#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ + +#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ +#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ + +#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ +#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ + +#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ +#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ + +#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ +#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ + +#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ +#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ + +#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ +#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ + +#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ +#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ + +#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ +#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ + +#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ +#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ + +#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ +#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ + +#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ +#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ + +#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ +#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ + +#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ +#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ + +#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ +#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ + +#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ +#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ + +#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ +#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ + +#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ +#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ + +#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ +#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ + +#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ +#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ + +#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ +#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ + +#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ +#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* OTG_CONST */ +/**@}*/ /* end of OTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OTG_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/pdma_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/pdma_reg.h new file mode 100644 index 0000000000..0cc32c212e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/pdma_reg.h @@ -0,0 +1,848 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) + Memory Mapped Structure for PDMA Controller +@{ */ + + +typedef struct +{ + + /** + * @var DSCT_T::CTL + * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01= One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04 Source Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA controller. + * @var DSCT_T::DA + * Offset: 0x08 Destination Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA controller. + * @var DSCT_T::NEXT + * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. + * | | |Note: write operation is useless in this field. + * |[31:16] |NEXT |PDMA Next Descriptor Table Offset. + * | | |This field indicates the offset of the next descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. + * | | |Note1: The descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + */ + __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ + __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ + __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ + __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ +} DSCT_T; + + +typedef struct +{ + /** + * @var STRIDE_T::STCR + * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504 Address Stride Offset Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ + __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + +typedef struct +{ + + + /** + * @var PDMA_T::CURSCAT + * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHENn |PDMA Channel Enable Bit + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Stop Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If re-enable the paused channel again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INTENn |PDMA Interrupt Enable Register + * | | |This field is used for enabling PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TDIFn |Transfer Done Flag Register + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ALIGNn |Transfer Alignment Flag Register + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC + * Offset: 0x430 PDMA Time-out Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTENn |PDMA Time-out Enable Bits + * | | |0 = PDMA Channel n time-out function Disable. + * | | |1 = PDMA Channel n time-out function Enable. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits + * | | |0 = PDMA Channel n time-out interrupt Disable. + * | | |1 = PDMA Channel n time-out interrupt Enable. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Request Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA peripheral request. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10=Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Channel connects to USCI1_TX. + * | | |19 = Channel connects to USCI1_RX. + * | | |20 = Channel connects to QSPI0_TX. + * | | |21 = Channel connects to QSPI0_RX. + * | | |22 = Channel connects to SPI0_TX. + * | | |23 = Channel connects to SPI0_RX. + * | | |24 = Channel connects to SPI1_TX. + * | | |25 = Channel connects to SPI1_RX. + * | | |26 = Channel connects to SPI2_TX. + * | | |27 = Channel connects to SPI2_RX. + * | | |28 = Channel connects to SPI3_TX. + * | | |29 = Channel connects to SPI3_RX. + * | | |30 = Reserved. + * | | |31 = Reserved. + * | | |32 = Channel connects to EPWM0_P1_RX. + * | | |33 = Channel connects to EPWM0_P2_RX. + * | | |34 = Channel connects to EPWM0_P3_RX. + * | | |35 = Channel connects to EPWM1_P1_RX. + * | | |36 = Channel connects to EPWM1_P2_RX. + * | | |37 = Channel connects to EPWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to ADC_RX. + * | | |51 = Channel connects to DAC0_TX. + * | | |52 = Channel connects to DAC1_TX. + * | | |53 = Channel connects to EPWM0_CH0_TX. + * | | |54 = Channel connects to EPWM0_CH1_TX. + * | | |55 = Channel connects to EPWM0_CH2_TX. + * | | |56 = Channel connects to EPWM0_CH3_TX. + * | | |57 = Channel connects to EPWM0_CH4_TX. + * | | |58 = Channel connects to EPWM0_CH5_TX. + * | | |59 = Channel connects to EPWM1_CH0_TX. + * | | |60 = Channel connects to EPWM1_CH1_TX. + * | | |61 = Channel connects to EPWM1_CH2_TX. + * | | |62 = Channel connects to EPWM1_CH3_TX. + * | | |63 = Channel connects to EPWM1_CH4_TX. + * | | |64 = Channel connects to EPWM1_CH5_TX. + * | | |65 = Channel connects to ETMC_RX. + * | | |Others = Reserved. + * | | |Note 1: A peripheral can't assign to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL8_11 + * Offset: 0x488 PDMA Request Source Select Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC8 |Channel 8 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 8 + * | | |User can configure the peripheral setting by REQSRC8. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC9 |Channel 9 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 9 + * | | |User can configure the peripheral setting by REQSRC9. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC10 |Channel 10 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 10 + * | | |User can configure the peripheral setting by REQSRC10. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC11 |Channel 11 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 11 + * | | |User can configure the peripheral setting by REQSRC11. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL12_15 + * Offset: 0x48C PDMA Request Source Select Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC12 |Channel 12 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 12 + * | | |User can configure the peripheral setting by REQSRC12. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC13 |Channel 13 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 13 + * | | |User can configure the peripheral setting by REQSRC13. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC14 |Channel 14 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 14 + * | | |User can configure the peripheral setting by REQSRC14. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC15 |Channel 15 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 15 + * | | |User can configure the peripheral setting by REQSRC15. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + DSCT_T DSCT[16]; + __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[176]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ + __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ + __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[28]; + /// @endcond //HIDDEN_SYMBOLS + STRIDE_T STRIDE[6]; +} PDMA_T; + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller +@{ */ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ +#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ + +#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ +#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ + +#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ +#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ + +#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ +#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ + +#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ +#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ + +#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ +#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ + +#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ +#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ + +#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ +#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ + +#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ +#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ +#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ + +#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ +#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ + +#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ +#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ + +#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ +#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ + +#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ +#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ + +#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ +#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ + +#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ +#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ + +#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ +#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ +#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ +#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ +#define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ + +#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ +#define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ + +#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ +#define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ + +#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ +#define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ + +#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ +#define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ + +#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ +#define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ + +#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ +#define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ + +#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ +#define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ + +#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ +#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ + +#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ +#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ + +#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ +#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __PDMA_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qei_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qei_reg.h new file mode 100644 index 0000000000..9484809392 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qei_reg.h @@ -0,0 +1,314 @@ +/**************************************************************************//** + * @file qei_reg.h + * @version V1.00 + * @brief QEI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QEI_REG_H__ +#define __QEI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QEI Quadrature Encoder Interface(QEI) + Memory Mapped Structure for QEI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QEI_T::CNT + * Offset: 0x00 QEI Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |Quadrature Encoder Interface Counter + * | | |A 32-bit up/down counter + * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero + * | | |This register performs an integrator which count value is proportional to the encoder position + * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: + * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0. + * | | |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode. + * | | |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1. + * @var QEI_T::CNTHOLD + * Offset: 0x04 QEI Counter Hold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold + * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. + * @var QEI_T::CNTLATCH + * Offset: 0x08 QEI Counter Index Latch Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch + * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. + * @var QEI_T::CNTCMP + * Offset: 0x0C QEI Counter Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare + * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set + * | | |This register is software writable. + * @var QEI_T::CNTMAX + * Offset: 0x14 QEI Pre-set Maximum Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count + * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode + * @var QEI_T::CTL + * Offset: 0x18 QEI Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock . + * | | |000 = QEI_CLK. + * | | |001 = QEI_CLK/2. + * | | |010 = QEI_CLK/4. + * | | |011 = QEI_CLK/16. + * | | |100 = QEI_CLK/32. + * | | |101 = QEI_CLK/64. + * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit + * | | |0 = The noise filter of QEI controller Enabled. + * | | |1 = The noise filter of QEI controller Disabled. + * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit + * | | |0 = QEA input to QEI Controller Disabled. + * | | |1 = QEA input to QEI Controller Enabled. + * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit + * | | |0 = QEB input to QEI Controller Disabled. + * | | |1 = QEB input to QEI Controller Enabled. + * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit + * | | |0 = IDX input to QEI Controller Disabled. + * | | |1 = IDX input to QEI Controller Enabled. + * |[9:8] |MODE |QEI Counting Mode Selection + * | | |There are four quadrature encoder pulse counter operation modes. + * | | |00 = X4 Free-counting Mode. + * | | |01 = X2 Free-counting Mode. + * | | |10 = X4 Compare-counting Mode. + * | | |11 = X2 Compare-counting Mode. + * |[12] |CHAINV |Inverse QEA Input Polarity + * | | |0 = Not inverse QEA input polarity. + * | | |1 = QEA input polarity is inversed to QEI controller. + * |[13] |CHBINV |Inverse QEB Input Polarity + * | | |0 = Not inverse QEB input polarity. + * | | |1 = QEB input polarity is inversed to QEI controller. + * |[14] |IDXINV |Inverse IDX Input Polarity + * | | |0 = Not inverse IDX input polarity. + * | | |1 = IDX input polarity is inversed to QEI controller. + * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit + * | | |0 = OVUNF can trigger QEI controller interrupt Disabled. + * | | |1 = OVUNF can trigger QEI controller interrupt Enabled. + * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit + * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled. + * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled. + * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit + * | | |0 = CMPF can trigger QEI controller interrupt Disabled. + * | | |1 = CMPF can trigger QEI controller interrupt Enabled. + * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit + * | | |0 = The IDXF can trigger QEI interrupt Disabled. + * | | |1 = The IDXF can trigger QEI interrupt Enabled. + * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0 + * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. + * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1 + * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. + * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2 + * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. + * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3 + * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. + * |[24] |HOLDCNT |Hold QEI_CNT Control + * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0]) + * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). + * | | |0 = No operation. + * | | |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]). + * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. + * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit + * | | |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX. + * | | |0 = The index signal latch QEI counter function Disabled. + * | | |1 = The index signal latch QEI counter function Enabled. + * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit + * | | |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0). + * | | |0 = Reload function Disabled. + * | | |1 = QEI_CNT re-initialized by Index signal Enabled. + * |[28] |CMPEN |The Compare Function Enable Bit + * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit + * | | |0 = QEI controller function Disabled. + * | | |1 = QEI controller function Enabled. + * @var QEI_T::STATUS + * Offset: 0x2C QEI Controller Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDXF |IDX Detected Flag + * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. + * | | |0 = No rising edge detected on signal CHX. + * | | |1 = A rising edge occurs on signal CHX. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CMPF |Compare-match Flag + * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]). + * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]). + * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]). + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag + * | | |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode + * | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]). + * | | |0 = No overflow or underflow occurs in QEI counter. + * | | |1 = QEI counter occurs counting overflow or underflow. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[3] |DIRCHGF |Direction Change Flag + * | | |Flag is set by hardware while QEI counter counting direction is changed. + * | | |Software can clear this bit by writing 1 to it. + * | | |0 = No change in QEI counter counting direction. + * | | |1 = QEI counter counting direction is changed. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[8] |DIRF |QEI Counter Counting Direction Indication + * | | |0 = QEI Counter is in down-counting. + * | | |1 = QEI Counter is in up-counting. + * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. + */ + __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */ + __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */ + __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */ + __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */ + __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */ + +} QEI_T; + +/** + @addtogroup QEI_CONST QEI Bit Field Definition + Constant Definitions for QEI Controller +@{ */ + +#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */ +#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */ + +#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */ +#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */ + +#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */ +#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */ + +#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */ +#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */ + +#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */ +#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */ + +#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */ +#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */ + +#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */ +#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */ + +#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */ +#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */ + +#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */ +#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */ + +#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */ +#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */ + +#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */ +#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */ + +#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */ +#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */ + +#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */ +#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */ + +#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */ +#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */ + +#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */ +#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */ + +#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */ +#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */ + +#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */ +#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */ + +#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */ +#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */ + +#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */ +#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */ + +#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */ +#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */ + +#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */ +#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */ + +#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */ +#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */ + +#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */ +#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */ + +#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */ +#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */ + +#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */ +#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */ + +#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */ +#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */ + +#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */ +#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */ + +#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */ +#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */ + +#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */ +#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */ + +#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */ +#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */ + +#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */ +#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */ + +#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */ +#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */ + +/**@}*/ /* QEI_CONST */ +/**@}*/ /* end of QEI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QEI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qspi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qspi_reg.h new file mode 100644 index 0000000000..1f78d51dda --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qspi_reg.h @@ -0,0 +1,591 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V1.00 + * @brief QSPI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QSPI Serial Peripheral Interface Controller(QSPI) + Memory Mapped Structure for QSPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the QSPIx_SS line to inactive state. + * | | |1 = set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0) + * | | |Slave 3-wire mode is only available in QSPI0 + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0) + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0) + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0) + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0) + * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |QSPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from QSPI data input pin + * | | |This is a read only register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller +@{ */ + +#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */ +#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */ +#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QSPI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/rtc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/rtc_reg.h new file mode 100644 index 0000000000..03f384dc6c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/rtc_reg.h @@ -0,0 +1,1224 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V1.00 + * @brief RTC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup RTC Real Time Clock Controller(RTC) + Memory Mapped Structure for RTC Controller +@{ */ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::RWEN + * Offset: 0x04 RTC Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |RWENF |RTC Register Access Enable Flag (Read Only) + * | | |0 = RTC register read/write Disabled. + * | | |1 = RTC register read/write Enabled. + * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. + * |[24] |RTCBUSY |RTC Write Busy Flag + * | | |This bit indicates RTC registers are writable or not. + * | | |0: RTC registers are writable. + * | | |1: RTC registers can't write, RTC under Busy Status. + * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[21:0] |FREQADJ |Frequency Compensation Register + * | | |User must to get actual LXT frequency for RTC application. + * | | |FCR = 0x200000 * (32768 / LXT frequency). + * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication + * | | |(If RTC_TIME[21] is 1, it indicates PM time message). + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication + * | | |(If RTC_TIME[21] is 1, it indicates PM time message). + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit + * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. + * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. + * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit + * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. + * | | |0 = Tamper 2 interrupt Disabled. + * | | |1 = Tamper 2 interrupt Enabled. + * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit + * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. + * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. + * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit + * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. + * | | |0 = Tamper 4 interrupt Disabled. + * | | |1 = Tamper 4 interrupt Enabled. + * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit + * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. + * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag + * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) + * | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. + * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. + * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[10] |TAMP2IF |Tamper 2 Interrupt Flag + * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). + * | | |0 = No Tamper 2 interrupt flag is generated. + * | | |1 = Tamper 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag + * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) + * | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated + * | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. + * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. + * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[12] |TAMP4IF |Tamper 4 Interrupt Flag + * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). + * | | |0 = No Tamper 4 interrupt flag is generated. + * | | |1 = Tamper 4 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag + * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) + * | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated + * | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. + * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. + * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register is Disabled. + * | | |1 = Spare register is Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Writes 1 to clear this bit. + * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero. + * @var RTC_T::SPR[20] + * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. + * | | |Before storing back-up information in to RTC_SPRx register, + * | | |user should check REWNF (RTC_RWEN[16]) is enabled. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |00 = L0 mode. + * | | |01 = L1 mode. + * | | |10 = L2 mode. + * | | |11 = L3 mode. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode + * | | |00 = PF.4 is input only mode, without pull-up resistor. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mode with internal pull up. + * |[2] |DOUT0 |IO Output Data + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |CTLSEL0 |IO Pin State Backup Selection + * | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function + * | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.4 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off. + * | | |1 = PF.4 pin I/O function is controlled by VBAT power domain. + * | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. + * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-up disable. + * | | |01 = PF.4 pull-down enable. + * | | |10 = PF.4 pull-up enable. + * | | |11 = PF.4 pull-up and pull-up disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode. + * |[9:8] |OPMODE1 |IO Operation Mode + * | | |00 = PF.5 is input only mode, without pull-up resistor. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mode with internal pull up. + * |[10] |DOUT1 |IO Output Data + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11] |CTLSEL1 |IO Pin State Backup Selection + * | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function + * | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.5 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off. + * | | |1 = PF.5 pin I/O function is controlled by VBAT power domain. + * | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. + * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-up disable. + * | | |01 = PF.5 pull-down enable. + * | | |10 = PF.5 pull-up enable. + * | | |11 = PF.5 pull-up and pull-up disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode. + * |[17:16] |OPMODE2 |IO Operation Mode + * | | |00 = PF.6 is input only mode, without pull-up resistor. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mode with internal pull up. + * |[18] |DOUT2 |IO Output Data + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19] |CTLSEL2 |IO Pin State Backup Selection + * | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function + * | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.6 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off. + * | | |1 = PF.6 pin I/O function is controlled by VBAT power domain. + * | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. + * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-up disable. + * | | |01 = PF.6 pull-down enable. + * | | |10 = PF.6 pull-up enable. + * | | |11 = PF.6 pull-up and pull-up disable. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode. + * |[25:24] |OPMODE3 |IO Operation Mode + * | | |00 = PF.7 is input only mode, without pull-up resistor. + * | | |01 = PF.7 is output push pull mode. + * | | |10 = PF.7 is open drain mode. + * | | |11 = PF.7 is quasi-bidirectional mode. + * |[26] |DOUT3 |IO Output Data + * | | |0 = PF.7 output low. + * | | |1 = PF.7 output high. + * |[27] |CTLSEL3 |IO Pin State Backup Selection + * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function + * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.7 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off. + * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain. + * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. + * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. + * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable + * | | |Determine PF.7 I/O pull-up or pull-down. + * | | |00 = PF.7 pull-up and pull-down disable. + * | | |01 = PF.7 pull-down enable. + * | | |10 = PF.7 pull-up enable. + * | | |11 = PF.7 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode. + * @var RTC_T::GPIOCTL1 + * Offset: 0x108 RTC GPIO Control 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE4 |IO Operation Mode + * | | |00 = PF.8 is input only mode, without pull-up resistor. + * | | |01 = PF.8 is output push pull mode. + * | | |10 = PF.8 is open drain mode. + * | | |11 = PF.8 is quasi-bidirectional mode. + * |[2] |DOUT4 |IO Output Data + * | | |0 = PF.8 output low. + * | | |1 = PF.8 output high. + * |[3] |CTLSEL4 |IO Pin State Backup Selection + * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function + * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.8 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off. + * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain. + * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. + * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. + * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable + * | | |Determine PF.8 I/O pull-up or pull-down. + * | | |00 = PF.8 pull-up and pull-down disable. + * | | |01 = PF.8 pull-down enable. + * | | |10 = PF.8 pull-up enable. + * | | |11 = PF.8 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode. + * |[9:8] |OPMODE5 |IO Operation Mode + * | | |00 = PF.9 is input only mode, without pull-up resistor. + * | | |01 = PF.9 is output push pull mode. + * | | |10 = PF.9 is open drain mode. + * | | |11 = PF.9 is quasi-bidirectional mode. + * |[10] |DOUT5 |IO Output Data + * | | |0 = PF.9 output low. + * | | |1 = PF.9 output high. + * |[11] |CTLSEL5 |IO Pin State Backup Selection + * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function + * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.9 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off. + * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain. + * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. + * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable + * | | |Determine PF.9 I/O pull-up or pull-down. + * | | |00 = PF.9 pull-up and pull-down disable. + * | | |01 = PF.9 pull-down enable. + * | | |10 = PF.9 pull-up enable. + * | | |11 = PF.9 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode. + * |[17:16] |OPMODE6 |IO Operation Mode + * | | |00 = PF.10 is input only mode, without pull-up resistor. + * | | |01 = PF.10 is output push pull mode. + * | | |10 = PF.10 is open drain mode. + * | | |11 = PF.10 is quasi-bidirectional mode. + * |[18] |DOUT6 |IO Output Data + * | | |0 = PF.10 output low. + * | | |1 = PF.10 output high. + * |[19] |CTLSEL6 |IO Pin State Backup Selection + * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function + * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.10 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off. + * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain. + * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. + * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable + * | | |Determine PF.10 I/O pull-up or pull-down. + * | | |00 = PF.10 pull-up and pull-down disable. + * | | |01 = PF.10 pull-down enable. + * | | |10 = PF.10 pull-up enable. + * | | |11 = PF.10 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode. + * |[25:24] |OPMODE7 |IO Operation Mode + * | | |00 = PF.11 is input only mode, without pull-up resistor. + * | | |01 = PF.11 is output push pull mode. + * | | |10 = PF.11 is open drain mode. + * | | |11 = PF.11 is quasi-bidirectional mode. + * |[26] |DOUT7 |IO Output Data + * | | |0 = PF.11 output low. + * | | |1 = PF.11 output high. + * |[27] |CTLSEL7 |IO Pin State Backup Selection + * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function + * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.11 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off. + * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain. + * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. + * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable + * | | |Determine PF.11 I/O pull-up or pull-down. + * | | |00 = PF.11 pull-up and pull-down disable. + * | | |01 = PF.11 pull-down enable. + * | | |10 = PF.11 pull-up enable. + * | | |11 = PF.11 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0= Normal mode. + * | | |1= Daylight saving mode. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set + * |[3:2] |DYNSRC |Dynamic Reference Pattern + * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. + * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out. + * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. + * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reload. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note: Before set this bit, the tamper configuration should be set to complete. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 210 * RTC_CLK. + * | | |001 = 211 * RTC_CLK. + * | | |010 = 212 * RTC_CLK. + * | | |011 = 213 * RTC_CLK. + * | | |100 = 214 * RTC_CLK. + * | | |101 = 215 * RTC_CLK. + * | | |110 = 216 * RTC_CLK. + * | | |111 = 217 * RTC_CLK. + * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var RTC_T::TAMPSEED + * Offset: 0x128 RTC Tamper Dynamic Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed Value + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */ + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[28]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller +@{ */ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */ + +#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ +#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ + +#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */ +#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */ + +#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */ +#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */ + +#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */ +#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ +#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ + +#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ +#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ + +#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ +#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ + +#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ +#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ + +#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ +#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ +#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ + +#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ +#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ + +#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ +#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ + +#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ +#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ + +#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ +#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ +#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ + +#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ +#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ + +#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ +#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ + +#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ +#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ + +#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ +#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ + +#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ +#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ + +#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ +#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ + +#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ +#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ + +#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ +#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ + +#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ +#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ + +#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ +#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ + +#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ +#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ + +#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ +#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ + +#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ +#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ + +#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ +#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */ +#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */ +#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */ +#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ +#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ + +#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ +#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ + +#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */ +#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */ + +#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ +#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ + +#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ +#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ + +#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ +#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ + +#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */ +#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */ + +#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ +#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ + +#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ +#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ + +#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ +#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ + +#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */ +#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */ + +#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ +#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ + +#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ +#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ + +#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ +#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ + +#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */ +#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */ + +#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ +#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ + +#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ +#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ + +#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ +#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ + +#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */ +#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */ + +#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ +#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ +#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ + +#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ +#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ + +#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */ +#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ + +#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ +#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ + +#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ +#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ +#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ + +#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ +#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ + +#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ +#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ +#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ + +#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ +#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ + +#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ +#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ + +#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ +#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ + +#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ +#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ + +#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ +#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ + +#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ +#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ +#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ + +#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ +#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ + +#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ +#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ + +#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ +#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ + +#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ +#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ + +#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ +#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ + +#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ +#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ +#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ + +#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ +#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __RTC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sc_reg.h new file mode 100644 index 0000000000..1d1f0eb522 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sc_reg.h @@ -0,0 +1,1018 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V1.00 + * @brief SC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SC Smart Card Host Interface Controller(SC) + Memory Mapped Structure for SC Controller +@{ */ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. If this bit is cleared, + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) + * | | |state and the first data must be 0x3B or 0x3F. + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and + * | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 + * | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an + * | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters + * | | |between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this + * | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserved + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU. + * | | |1= The stop bit length is 1 ETU. + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity + * | | |error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce + * | | |sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and + * | | |the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform + * | | |warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 7.17-54. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5. + * | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation + * | | |at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence + * | | |if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by + * | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will + * | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation + * | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, + * | | |this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit + * | | |will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) + * | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT + * | | |register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, + * | | |the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state + * | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit + + * | | |data bits + parity bit + stop bit). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set + * | | |this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter + * | | |Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), + * | | |hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware + * | | |will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * | | |Note: This bit is read only. + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission + * | | |has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP + * | | |bit of the last byte has not been transmitted. + * | | |Note: This bit is read only. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0. + * | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 7.17-3 for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be '00'. + * |[6] |PBOFF |Parity Bit Disable Control + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is '0'. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 7.17-4. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[5]; + /** @endcond */ + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller +@{ */ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sdh_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sdh_reg.h new file mode 100644 index 0000000000..ed227220c4 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sdh_reg.h @@ -0,0 +1,540 @@ +/**************************************************************************//** + * @file sdh_reg.h + * @version V1.00 + * @brief SDH register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SDH_REG_H__ +#define __SDH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SDH SD Card Host Interface(SDH) + Memory Mapped Structure for SDH Controller +@{ */ + +typedef struct +{ + + /** + * @var SDH_T::FB + * Offset: 0x00~0x7C Shared Buffer (FIFO) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BUFFER |Shared Buffer + * | | |Buffer for DMA transfer + * @var SDH_T::DMACTL + * Offset: 0x400 DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAEN |DMA Engine Enable Bit + * | | |0 = DMA Disabled. + * | | |1 = DMA Enabled. + * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. + * | | |Note: If target abort is occurred, DMAEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |DMA Transfer Is in Progress + * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. + * | | |0 = DMA transfer is not in progress. + * | | |1 = DMA transfer is in progress. + * @var SDH_T::DMASA + * Offset: 0x408 DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var SDH_T::DMABCNT + * Offset: 0x40C DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. + * @var SDH_T::DMAINTEN + * Offset: 0x410 DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. + * @var SDH_T::DMAINTSTS + * Offset: 0x414 DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened + * | | |DMA will stop transfer and respond this event and then go to IDLE state + * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::GCTL + * Offset: 0x800 Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset SD host + * | | |The contents of control register will not be cleared + * | | |This bit will auto cleared after reset complete. + * |[1] |SDEN |Secure Digital Functionality Enable Bit + * | | |0 = SD functionality disabled. + * | | |1 = SD functionality enabled. + * @var SDH_T::GINTEN + * Offset: 0x804 Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. + * @var SDH_T::GINTSTS + * Offset: 0x808 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort is occurred, please reset all engine. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::CTL + * Offset: 0x820 SD Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |COEN |Command Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output a command to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[1] |RIEN |Response Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[2] |DIEN |Data Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[3] |DOEN |Data Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[4] |R2EN |Response R2 Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 8 clock cycles. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[7] |CLKKEEP |SD Clock Enable Control + * | | |0 = SD host decided when to output clock and when to disable clock output automatically. + * | | |1 = SD clock always keeps free running. + * |[13:8] |CMDCODE |SD Command Code + * | | |This register contains the SD command code (0x00 - 0x3F). + * |[14] |CTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters + * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared) + * | | |This bit will be auto cleared after few clock cycles. + * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) + * | | |0 = Data bus width is 1-bit. + * | | |1 = Data bus width is 4-bit. + * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received + * | | |This field contains the block counts for data-in and data-out transfer + * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance + * | | |Don't fill 0x0 to this field. + * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). + * |[27:24] |SDNWR |NWR Parameter for Block Write Operation + * | | |This value indicates the NWR parameter for data block write operation in SD clock counts + * | | |The actual clock cycle will be SDNWR+1. + * @var SDH_T::CMDARG + * Offset: 0x824 SD Command Argument Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARGUMENT |SD Command Argument + * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card + * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. + * @var SDH_T::INTEN + * Offset: 0x828 SD Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit + * | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable. + * | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled. + * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit + * | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable. + * | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled. + * |[8] |CDIEN |SD Card Detection Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed. + * | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable. + * | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled. + * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled. + * | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled. + * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when data input time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled. + * | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled. + * |[14] |WKIEN |Wake-up Signal Generating Enable Bit + * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. + * | | |0 = SD Card interrupt to wake-up chip Disabled. + * | | |1 = SD Card interrupt to wake-up chip Enabled. + * |[30] |CDSRC |SD Card Detect Source Selection + * | | |0 = From SD card's DAT3 pin. + * | | |Host need clock to got data on pin DAT3 + * | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. + * | | |1 = From GPIO pin. + * @var SDH_T::INTSTS + * Offset: 0x82C SD Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has finished all data-in or data-out block transfer + * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. + * | | |0 = Not finished yet. + * | | |1 = Done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer + * | | |When CRC error is occurred, software should reset SD engine + * | | |Some response (ex + * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag + * | | |In this condition, software should ignore CRC error and clears this bit manually. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |CRC7 |CRC7 Check Status (Read Only) + * | | |SD host will check CRC7 correctness during each response in + * | | |If that response does not contain CRC7 information (ex + * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. + * | | |0 = Fault. + * | | |1 = OK. + * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) + * | | |SD host will check CRC16 correctness after data-in transfer. + * | | |0 = Fault. + * | | |1 = OK. + * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) + * | | |SD host will record CRC status of data-out transfer + * | | |Software could use this value to identify what type of error is during data-out transfer. + * | | |010 = Positive CRC status. + * | | |101 = Negative CRC status. + * | | |111 = SD card programming error occurs. + * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) + * | | |This bit is the DAT0 pin status of current selected SD port. + * |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only) + * | | |This bit indicates that SD card is inserted or removed + * | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active. + * | | |0 = No card is inserted or removed. + * | | |1 = There is a card inserted in or removed from SD. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Response time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Data input time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[16] |CDSTS |Card Detect Status of SD (Read Only) + * | | |This bit indicates the card detect pin status of SD, and is used for card detection + * | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal. + * | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. + * | | |0 = Card removed. + * | | |1 = Card inserted. + * | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:. + * | | |0 = Card inserted. + * | | |1 = Card removed. + * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) + * | | |This bit indicates the DAT1 pin status of SD port. + * @var SDH_T::RESP0 + * Offset: 0x830 SD Receiving Response Token Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RESPTK0 |SD Receiving Response Token 0 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This field contains response bit 47-16 of the response token. + * @var SDH_T::RESP1 + * Offset: 0x834 SD Receiving Response Token Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RESPTK1 |SD Receiving Response Token 1 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This register contains the bit 15-8 of the response token. + * @var SDH_T::BLEN + * Offset: 0x838 SD Block Length Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit + * | | |An 11-bit value specifies the SD transfer byte count of a block + * | | |The actual byte count is equal to BLKLEN+1. + * | | |Note: The default SD block length is 512 bytes + * @var SDH_T::TOUT + * Offset: 0x83C SD Response/Data-in Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TOUT |SD Response/Data-in Time-out Value + * | | |A 24-bit value specifies the time-out counts of response and data input + * | | |SD host controller will wait start bit of response or data-in until this value reached + * | | |The time period depends on SD engine clock frequency + * | | |Do not write a small number into this field, or you may never get response or data due to time-out. + * | | |Note: Filling 0x0 into this field will disable hardware time-out function. + */ + + __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[224]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ + __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[250]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ + __I uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ + __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ + __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ + __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ + __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ + __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ + __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ + __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ + +} SDH_T; + + +/** + @addtogroup SDH_CONST SDH Bit Field Definition + Constant Definitions for SDH Controller +@{ */ + +#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ +#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ + +#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ +#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ + +#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ +#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ + +#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ +#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ + +#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ +#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ + +#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ +#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ + +#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ +#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ + +#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ +#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ + +#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ +#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ + +#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ +#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ + +#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ +#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ + +#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ +#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ + +#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ +#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ + +#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ +#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ + +#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ +#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ + +#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ +#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ + +#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ +#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ + +#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ +#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ + +#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ +#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ + +#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ +#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ + +#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ +#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ + +#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ +#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ + +#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ +#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ + +#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ +#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ + +#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ +#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ + +#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ +#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ + +#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ +#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ + +#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ +#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ + +#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ +#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ + +#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ +#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ + +#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ +#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ + +#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ +#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ + +#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ +#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ + +#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ +#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ + +#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ +#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ + +#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ +#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ + +#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ +#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ + +#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ +#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ + +#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ +#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ + +#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ +#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ + +#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ +#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ + +#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ +#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ + +#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ +#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ + +#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ +#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ + +#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ +#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ + +#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ +#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ + +#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ +#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ + +#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ +#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ + +#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ +#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ + +#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ +#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ + +#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ +#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ + +/**@}*/ /* SDH_CONST */ +/**@}*/ /* end of SDH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SDH_REG_H__ */ + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spi_reg.h new file mode 100644 index 0000000000..c9421ce411 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spi_reg.h @@ -0,0 +1,799 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V1.00 + * @brief SPI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPI Serial Peripheral Interface Controller(SPI) + Memory Mapped Structure for SPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: Not supported in I2S mode. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = The SPI controller is disabled. + * | | |1 = The SPI controller is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from SPI data input pin + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register + * | | |This is a read only register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices + * | | |The frequency of master clock, fMCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1,. + * | | |If MCLKDIV = 0,. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2 + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression: + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[11]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */ +#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spim_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spim_reg.h new file mode 100644 index 0000000000..262a3fbe49 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spim_reg.h @@ -0,0 +1,556 @@ +/**************************************************************************//** + * @file spim_reg.h + * @version V1.00 + * @brief SPIM register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPIM_REG_H__ +#define __SPIM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPIM Serial Peripheral Interface Controller Master Mode (SPIM) + Memory Mapped Structure for SPIM Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPIM_T::CTL0 + * Offset: 0x00 Control and Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CIPHOFF |Cipher Disable Control + * | | |0 = Cipher function Enabled. + * | | |1 = Cipher function Disabled. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10. + * | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8. + * |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control + * | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation + * | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled. + * | | |Note: Only useful when cipher is disabled. + * |[5] |B4ADDREN |4-byte Address Mode Enable Control + * | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled. + * | | |1 = 4-byte address mode is enabled. + * | | |Note: Used for DMA write mode, DMA read mode, and DMM mode. + * |[6] |IEN |Interrupt Enable Control + * | | |0 = SPIM Interrupt Disabled. + * | | |1 = SPIM Interrupt Enabled. + * |[7] |IF |Interrupt Flag + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Write 1 to clear. + * | | |(2) Read Operation : + * | | |0 = The transfer has not finished yet. + * | | |1 = The transfer has done. + * |[12:8] |DWIDTH |Transmit/Receive Bit Length + * | | |This specifies how many bits are transmitted/received in one transmit/receive transaction. + * | | |0x7 = 8 bits. + * | | |0xF = 16 bits. + * | | |0x17 = 24 bits. + * | | |0x1F = 32 bits. + * | | |Others = Incorrect transfer result. + * | | |Note1: Only used for normal I/O mode. + * | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer. + * |[14:13] |BURSTNUM |Transmit/Receive Burst Number + * | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer. + * | | |0x0 = Only one transmit/receive transaction will be executed in one transfer. + * | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer. + * | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer. + * | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer. + * | | |Note: Only used for normal I/O Mode. + * |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode + * | | |0 = Interface signals are input. + * | | |1 = Interface signals are output. + * | | |Note: Only used for normal I/O mode. + * |[19:16] |SUSPITV |Suspend Interval + * | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer + * | | |The default value is 0x00 + * | | |When BURSTNUM = 00, setting this field has no effect on transfer + * | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock): + * | | | (SUSPITV+2)*period of AHB clock + * | | | 0x0 = 2 AHB clock cycles. + * | | | 0x1 = 3 AHB clock cycles. + * | | | ...... + * | | | 0xE = 16 AHB clock cycles. + * | | | 0xF = 17 AHB clock cycles. + * | | | Note: Only used for normal I/O mode. + * |[21:20] |BITMODE |SPI Interface Bit Mode + * | | |0x0 = Standard mode. + * | | |0x1 = Dual mode. + * | | |0x2 = Quad mode. + * | | |0x3 = Reserved. + * | | |Note: Only used for normal I/O mode. + * |[23:22] |OPMODE |SPI Function Operation Mode + * | | |0x0 = Normal I/O mode. (Note1) (Note3) + * | | |0x1 = DMA write mode. (Note2) (Note3) + * | | |0x2 = DMA read mode. (Note3) + * | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4) + * | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note2 : In DMA write mode, hardware will send just one page program command per operation + * | | |Users must take care of cross-page cases + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * |[31:24] |CMDCODE |Page Program Command Code (Note4) + * | | |(1) 0x02 = Page program (Used for DMA Write mode). + * | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3) + * | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3) + * | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3) + * | | |The Others = Reserved. + * | | |Read Command Code : + * | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode). + * | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode). + * | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency + * | | |(Note2) + * | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode). + * | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode). + * | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock + * | | |(Note2) + * | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode). + * | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode). + * | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read + * | | |(Note2) + * | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode). + * | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode). + * | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode). + * | | |The Others command codes are Reserved. + * | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK) + * | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock + * | | |(Note2) + * | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands. + * | | |Note2: See SPI flash specifications for support items. + * | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5. + * | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * @var SPIM_T::CTL1 + * Offset: 0x04 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIMEN |Go and Busy Status + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Start the transfer + * | | |This bit remains set during the transfer and is automatically cleared after transfer finished. + * | | |(2) Read Operation : + * | | |0 = The transfer has done. + * | | |1 = The transfer has not finished yet. + * | | |Note: All registers should be set before writing 1 to the SPIMEN bit + * | | |When a transfer is in progress, you should not write to any register of this peripheral. + * |[1] |CACHEOFF |Cache Memory Function Disable Control + * | | |0 = Cache memory function enable. (Default value) + * | | |1 = Cache memory function disable. + * | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enable or disable by user. + * |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control + * | | |0 = CCM mode disable. (Default value) + * | | |1 = CCM mode enable. + * | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enabled or disabled by user. + * | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master + * | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master. + * | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status + * | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space. + * |[3] |CDINVAL |Cache Data Invalid Enable Control + * | | |(1) Write Operation: + * | | |0 = No effect. + * | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically. + * | | |(2) Read Operation : No effect + * | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1 + * | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1. + * |[4] |SS |Slave Select Active Enable Control + * | | |0 = SPIM_SS is in active level. + * | | |1 = SPIM_SS is in inactive level (Default). + * | | |Note: This interface can only drive one device/slave at a given time + * | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer + * | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2. + * |[5] |SSACTPOL |Slave Select Active Level + * | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2. + * | | |0 = The SPIM_SS slave select signal is active low. + * | | |1 = The SPIM_SS slave select signal is active high. + * |[11:8] |IDLETIME |Idle Time Interval + * | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses. + * | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time. + * | | |Note1: Only used for DMM mode. + * | | |Note2 : AHB clock cycle time = 1/AHB clock frequency. + * |[31:16] |DIVIDER |Clock Divider Register + * | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin + * | | |The desired frequency is obtained according to the following equation: + * | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK. + * | | |Note2: SCLK is serial SPI output clock. + * | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock. + * | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ... + * @var SPIM_T::RXCLKDLY + * Offset: 0x0C RX Clock Delay Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode + * | | |For DMA write mode only + * | | |This register sets the deselect time interval of SPI flash (i.e. + * | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode + * | | |(Note1) + * | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2). + * | | |Note1: Please user check the used external SPI flash component to set this register value + * | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation. + * | | |Note2: AHB clock cycle time = 1/AHB clock frequency. + * |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |Determine the number of inserted delay cycles + * | | |Used to adjust the sampling clock of received data to latch the correct data. + * | | |0x0 : No delay. (Default Value) + * | | |0x1 : Delay 1 SPI flash clock. + * | | |0x2 : Delay 2 SPI flash clocks. + * | | |0x3 : Delay 3 SPI flash clocks. + * | | |... + * | | |0x7 : Delay 7 SPI flash clocks + * | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows. + * | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately + * | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example). + * | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1 + * | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly. + * |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |0 : Use SPI input clock rising edge to sample received data. (Default Value) + * | | |1 : Use SPI input clock falling edge to sample received data. + * @var SPIM_T::RX[4] + * Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDAT |Data Receive Register + * | | |The Data Receive Registers hold the received data of the last executed transfer. + * | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first. + * | | |In a byte, received data are held in the most significant bit of RXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0]. + * | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16]. + * | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ..., + * | | |SPIM_RX0[0]. + * @var SPIM_T::TX[4] + * Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDAT |Data Transmit Register + * | | |The Data Transmit Registers hold the data to be transmitted in next transfer. + * | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first. + * | | |In a byte, data are transmitted in the most significant bit of TXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer. + * | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer. + * | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ..., + * | | |SPIM_TX0[0] in next transfer. + * @var SPIM_T::SRAMADDR + * Offset: 0x30 SRAM Memory Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SRAM Memory Address + * | | |For DMA Read mode, this is the destination address for DMA transfer. + * | | |For DMA Write mode, this is the source address for DMA transfer. + * | | |Note: This address must be word-aligned. + * @var SPIM_T::DMACNT + * Offset: 0x34 DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |DMACNT |DMA Transfer Byte Count Register + * | | |It indicates the transfer length for DMA process. + * | | |Note1: The unit for counting is byte. + * | | |Note2: The number must be the multiple of 4. + * | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program. + * @var SPIM_T::FADDR + * Offset: 0x38 SPI Flash Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SPI Flash Address Register + * | | |For DMA Read mode, this is the source address for DMA transfer. + * | | |For DMA Write mode, this is the destination address for DMA transfer. + * | | |Note 1 : This address must be word-aligned. + * | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * @var SPIM_T::KEY1 + * Offset: 0x3C Cipher Key1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY1 |Cipher Key1 Register + * | | |This is the KEY1 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::KEY2 + * Offset: 0x40 Cipher Key2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY2 |Cipher Key2 Register + * | | |This is the KEY2 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::DMMCTL + * Offset: 0x44 Direct Memory Mapping Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0) + * | | |Only for direct memory mapping mode + * | | |Set the mode bits data for continuous read mode (or performance enhance mode). + * | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active + * | | |(Note1) + * | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values. + * | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]). + * |[20:16] |DESELTIM |SPI Flash Deselect Time + * | | |Only for direct memory mapping mode + * | | |Set the minimum time width of SPI flash deselect time (i.e. + * | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8. + * | | |(1) Cache function disable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time. + * | | |(2) Cache function enable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10 + * | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8. + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0) + * | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7" + * | | |0 = Burst Wrap Mode Disable. (Default) + * | | |1 = Burst Wrap Mode Enable. + * | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance + * | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size) + * | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly. + * |[25] |CREN |Continuous Read Mode Enable Control + * | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2) + * | | |0 = Continuous Read Mode Disable. (Default) + * | | |1 = Continuous Read Mode Enable. + * | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data. + * | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications + * | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash. + * |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically + * | | |(Default value) + * | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually. + * | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1. + * |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8. + * | | |(1) ACTSCLKT = 0 (function disable) :. + * | | |Time interval = 1 AHB clock cycle time. + * | | |(2) ACTSCLKT != 0 (function enable) : + * | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : SCLK is SPI output clock + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * @var SPIM_T::CTL2 + * Offset: 0x48 Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |USETEN |User Set Value Enable Control + * | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7 + * | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically. + * | | |Dummy cycle number (DCNUM) : + * | | |Dummy cycle number for read command 0x03 : 0x0 + * | | |Dummy cycle number for read command 0x0B : 0x8 + * | | |Dummy cycle number for read command 0x3B : 0x8 + * | | |Dummy cycle number for read command 0xBB : 0x0 + * | | |Dummy cycle number for read command 0xEB : 0x4 + * | | |Dummy cycle number for read command 0xE7 : 0x2 + * | | |Mode bits data for continuous read mode (CRMDAT) : 0x20 + * | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually. + * | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1. + * |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED. + * |[28:24] |DCNUM |Dummy Cycle Number + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |Set number of dummy cycles + * | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 : + * | | |When read command code do not need any dummy cycles (i.e. + * | | |dummy cycle number = 0x0), user must set DCNUM to 0x0. + * | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification. + * | | |For command code 0xBB, if there is only dummy cycle number (i.e. + * | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification. + * | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification. + * | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED : + * | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification. + * | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types + * | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles. + */ + __IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */ + __I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */ + __IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */ + __IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */ + __IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */ + __IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */ + __O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */ + __O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */ + __IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */ + __IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */ + +} SPIM_T; + +/** + @addtogroup SPIM_CONST SPIM Bit Field Definition + Constant Definitions for SPIM Controller +@{ */ + +#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */ +#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */ + +#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */ +#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */ + +#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */ +#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */ + +#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */ +#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */ + +#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */ +#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */ + +#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */ +#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */ + +#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */ +#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */ + +#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */ +#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */ + +#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */ +#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */ + +#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */ +#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */ + +#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */ +#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */ + +#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */ +#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */ + +#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */ +#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */ + +#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */ +#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */ + +#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */ +#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */ + +#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */ +#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */ + +#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */ +#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */ + +#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */ +#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */ + +#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */ +#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */ + +#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */ +#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */ + +#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */ +#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */ + +#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */ +#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */ + +#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */ +#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */ + +#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */ +#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */ + +#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */ +#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */ + +#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */ +#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */ + +#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */ +#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */ + +#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */ +#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */ + +#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */ +#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */ + +#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */ +#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */ + +#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */ +#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */ + +#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */ +#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */ + +#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */ +#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */ + +#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */ +#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */ + +#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */ +#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */ + +#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */ +#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */ + +#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */ +#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */ + +#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */ +#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */ + +#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */ +#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */ + +/**@}*/ /* SPIM_CONST */ +/**@}*/ /* end of SPIM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPIM_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sys_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sys_reg.h new file mode 100644 index 0000000000..57c2bc985c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sys_reg.h @@ -0,0 +1,3475 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V1.00 + * @brief SYS register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller +@{ */ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |NRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M4. + * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write to clear this bit to 0. + * |[8] |CPULKRF |CPU Lock-up Reset Flag + * | | |0 = No reset from CPU lock-up happened. + * | | |1 = The Cortex-M4 lock-up happened and chip is reset. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. + * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMARST |PDMA Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA controller normal operation. + * | | |1 = PDMA controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |EMACRST |EMAC Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EMAC controller normal operation. + * | | |1 = EMAC controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST0 controller normal operation. + * | | |1 = SDHOST0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = HSUSBD controller normal operation. + * | | |1 = HSUSBD controller reset. + * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |SPIMRST |SPIM Controller Reset + * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SPIM controller normal operation. + * | | |1 = SPIM controller reset. + * |[16] |USBHRST |USBH Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the USBH controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = USBH controller normal operation. + * | | |1 = USBH controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST1 controller normal operation. + * | | |1 = SDHOST1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[10] |I2C2RST |I2C2 Controller Reset + * | | |0 = I2C2 controller normal operation. + * | | |1 = I2C2 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[14] |SPI1RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[15] |SPI2RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[19] |UART3RST |UART3 Controller Reset + * | | |0 = UART3 controller normal operation. + * | | |1 = UART3 controller reset. + * |[20] |UART4RST |UART4 Controller Reset + * | | |0 = UART4 controller normal operation. + * | | |1 = UART4 controller reset. + * |[21] |UART5RST |UART5 Controller Reset + * | | |0 = UART5 controller normal operation. + * | | |1 = UART5 controller reset. + * |[24] |CAN0RST |CAN0 Controller Reset + * | | |0 = CAN0 controller normal operation. + * | | |1 = CAN0 controller reset. + * |[25] |CAN1RST |CAN1 Controller Reset + * | | |0 = CAN1 controller normal operation. + * | | |1 = CAN1 controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADCRST |EADC Controller Reset + * | | |0 = EADC controller normal operation. + * | | |1 = EADC controller reset. + * |[29] |I2S0RST |I2S0 Controller Reset + * | | |0 = I2S0 controller normal operation. + * | | |1 = I2S0 controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * |[6] |SPI3RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[9] |USCI1RST |USCI1 Controller Reset + * | | |0 = USCI1 controller normal operation. + * | | |1 = USCI1 controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[16] |EPWM0RST |EPWM0 Controller Reset + * | | |0 = EPWM0 controller normal operation. + * | | |1 = EPWM0 controller reset. + * |[17] |EPWM1RST |EPWM1 Controller Reset + * | | |0 = EPWM1 controller normal operation. + * | | |1 = EPWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[22] |QEI0RST |QEI0 Controller Reset + * | | |0 = QEI0 controller normal operation. + * | | |1 = QEI0 controller reset. + * |[23] |QEI1RST |QEI1 Controller Reset + * | | |0 = QEI1 controller normal operation. + * | | |1 = QEI1 controller reset. + * |[26] |ECAP0RST |ECAP0 Controller Reset + * | | |0 = ECAP0 controller normal operation. + * | | |1 = ECAP0 controller reset. + * |[27] |ECAP1RST |ECAP1 Controller Reset + * | | |0 = ECAP1 controller normal operation. + * | | |1 = ECAP1 controller reset. + * |[30] |OPARST |OP Amplifier (OPA) Controller Reset + * | | |0 = OPA controller normal operation. + * | | |1 = OPA controller reset. + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-Out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . + * | | |0 = Brown-out INTERRUPT function Enabled. + * | | |1 = Brown-out RESET function Enabled. + * | | |Note1: + * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high + * | | |BOD interrupt will keep till to the BODEN set to 0 + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) + * | | |0 = BOD operate in normal mode (default). + * | | |1 = BOD Low Power mode Enabled. + * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting + * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by RC10K clock. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Brown-Out Detector threshold voltage is 1.6V. + * | | |001 = Brown-Out Detector threshold voltage is 1.8V. + * | | |010 = Brown-Out Detector threshold voltage is 2.0V. + * | | |011 = Brown-Out Detector threshold voltage is 2.2V. + * | | |100 = Brown-Out Detector threshold voltage is 2.4V. + * | | |101 = Brown-Out Detector threshold voltage is 2.6V. + * | | |110 = Brown-Out Detector threshold voltage is 2.8V. + * | | |111 = Brown-Out Detector threshold voltage is 3.0V. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result + * @var SYS_T::PORCTL + * Offset: 0x24 Power-On-Reset Controller Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) + * | | |00000 = VREF is from external pin. + * | | |00011 = VREF is internal 1.6V. + * | | |00111 = VREF is internal 2.0V. + * | | |01011 = VREF is internal 2.5V. + * | | |01111 = VREF is internal 3.0V. + * | | |Others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection. + * | | |00 = pre-load time is 60us for 0.1uF Capacitor. + * | | |01 = pre-load time is 310us for 1uF Capacitor. + * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. + * | | |11 = pre-load time is 2650us for 10uF Capacitor. + * @var SYS_T::USBPHY + * Offset: 0x2C USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |USBROLE |USB Role Option (Write Protect) + * | | |These two bits are used to select the role of USB. + * | | |00 = Standard USB Device mode. + * | | |01 = Standard USB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable + * |[8] |USBEN |USB PHY Enable (Write Protect) + * | | |This bit is used to enable/disable USB PHY. + * | | |0 = USB PHY Disabled. + * | | |1 = USB PHY Enabled. + * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) + * | | |These two bits are used to select the role of HSUSB + * | | |00 = Standard HSUSB Device mode. + * | | |01 = Standard HSUSB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect) + * | | |This bit is used to enable/disable HSUSB PHY. + * | | |0 = HSUSB PHY Disabled. + * | | |1 = HSUSB PHY Enabled. + * |[25] |HSUSBACT |HSUSB PHY Active Control + * | | |This bit is used to control HSUSB PHY at reset state or active state. + * | | |0 = HSUSB PHY at reset state. + * | | |1 = HSUSB PHY at active state. + * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode. + * @var SYS_T::GPA_MFPL + * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x34 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x3C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x44 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection + * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x4C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0x54 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0x5C GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection + * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection + * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection + * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection + * @var SYS_T::GPG_MFPL + * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection + * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection + * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection + * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection + * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection + * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection + * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection + * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection + * @var SYS_T::GPG_MFPH + * Offset: 0x64 GPIOG High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection + * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection + * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection + * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection + * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection + * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection + * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection + * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection + * @var SYS_T::GPH_MFPL + * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection + * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection + * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection + * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection + * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection + * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection + * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection + * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection + * @var SYS_T::GPH_MFPH + * Offset: 0x6C GPIOH High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection + * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection + * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection + * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection + * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection + * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection + * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection + * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection + * @var SYS_T::GPA_MFOS + * Offset: 0x80 GPIOA Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPB_MFOS + * Offset: 0x84 GPIOB Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPC_MFOS + * Offset: 0x88 GPIOC Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPD_MFOS + * Offset: 0x8C GPIOD Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPE_MFOS + * Offset: 0x90 GPIOE Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPF_MFOS + * Offset: 0x94 GPIOF Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPG_MFOS + * Offset: 0x98 GPIOG Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPH_MFOS + * Offset: 0x9C GPIOH Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::SRAM_INTCTL + * Offset: 0xC0 System SRAM Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit + * | | |0 = SRAM parity check error interrupt Disabled. + * | | |1 = SRAM parity check error interrupt Enabled. + * @var SYS_T::SRAM_STATUS + * Offset: 0xC4 System SRAM Parity Error Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIF |SRAM Parity Check Error Flag + * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. + * | | |0 = No System SRAM parity error. + * | | |1 = System SRAM parity error occur. + * @var SYS_T::SRAM_ERRADDR + * Offset: 0xC8 System SRAM Parity Check Error Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ERRADDR |System SRAM Parity Error Address + * | | |This register shows system SRAM parity error byte address. + * @var SYS_T::SRAM_BISTCTL + * Offset: 0xD0 System SRAM BIST Test Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank0. + * | | |0 = system SRAM bank0 BIST Disabled. + * | | |1 = system SRAM bank0 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank1. + * | | |0 = system SRAM bank1 BIST Disabled. + * | | |1 = system SRAM bank1 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CACHE RAM + * | | |0 = system CACHE BIST Disabled. + * | | |1 = system CACHE BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CAN RAM + * | | |0 = system CAN BIST Disabled. + * | | |1 = system CAN BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for USB RAM + * | | |0 = system USB BIST Disabled. + * | | |1 = system USB BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SPIM RAM + * | | |0 = system SPIM BIST Disabled. + * | | |1 = system SPIM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for EMC RAM + * | | |0 = system EMC BIST Disabled. + * | | |1 = system EMC BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for PDMA RAM + * | | |0 = system PDMA BIST Disabled. + * | | |1 = system PDMA BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBD RAM + * | | |0 = system HSUSBD BIST Disabled. + * | | |1 = system HSUSBD BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBH RAM + * | | |0 = system HSUSBH BIST Disabled. + * | | |1 = system HSUSBH BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect) + * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test. + * | | |0 = SRAM bank0 section 0 is deselected when doing bist test. + * | | |1 = SRAM bank0 section 0 is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. + * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect) + * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test. + * | | |0 = SRAM bank0 section 1 is deselected when doing bist test. + * | | |1 = SRAM bank0 section 1 is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. + * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * @var SYS_T::SRAM_BISTSTS + * Offset: 0xD4 System SRAM BIST Test Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag + * | | |0 = 1st system SRAM BIST test pass. + * | | |1 = 1st system SRAM BIST test fail. + * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag + * | | |0 = 2nd system SRAM BIST test pass. + * | | |1 = 2nd system SRAM BIST test fail. + * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag + * | | |0 = System CACHE RAM BIST test pass. + * | | |1 = System CACHE RAM BIST test fail. + * |[3] |CANBEF |CAN SRAM BIST Fail Flag + * | | |0 = CAN SRAM BIST test pass. + * | | |1 = CAN SRAM BIST test fail. + * |[4] |USBBEF |USB SRAM BIST Fail Flag + * | | |0 = USB SRAM BIST test pass. + * | | |1 = USB SRAM BIST test fail. + * |[16] |SRBEND0 |1st SRAM BIST Test Finish + * | | |0 = 1st system SRAM BIST active. + * | | |1 =1st system SRAM BIST finish. + * |[17] |SRBEND1 |2nd SRAM BIST Test Finish + * | | |0 = 2nd system SRAM BIST is active. + * | | |1 = 2nd system SRAM BIST finish. + * |[18] |CRBEND |CACHE SRAM BIST Test Finish + * | | |0 = System CACHE RAM BIST is active. + * | | |1 = System CACHE RAM BIST test finish. + * |[19] |CANBEND |CAN SRAM BIST Test Finish + * | | |0 = CAN SRAM BIST is active. + * | | |1 = CAN SRAM BIST test finish. + * |[20] |USBBEND |USB SRAM BIST Test Finish + * | | |0 = USB SRAM BIST is active. + * | | |1 = USB SRAM BIST test finish. + * @var SYS_T::IRCTCTL + * Offset: 0xF0 HIRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. + * | | |10 = Reserved.. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference from internal USB synchronous mode. + * | | |Note: HIRC trim reference clock is 20Khz in test mode. + * @var SYS_T::IRCTIEN + * Offset: 0xF4 HIRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::IRCTISTS + * Offset: 0xF8 HIRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt + * | | |Write 1 to clear this to 0 + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |Register Lock Control Code + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select(Write Protect) + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect) + * | | |The LVSSTEP value is LDO voltage rising step. + * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV. + * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect) + * | | |The LVSPRD value is the period of each LDO voltage rising step. + * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when core voltage is changing + * | | |After core voltage change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Core voltage change is completed. + * | | |1 = Core voltage change is ongoing. + * |[9:8] |PLSTATUS |Power Level Status (Read Only) + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * @var SYS_T::AHBMCTL + * Offset: 0x400 AHB Bus Matrix Priority Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) + * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix + * | | |0 = Run robin mode. + * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + */ + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[1]; + /** @endcond */ + __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[1]; + /** @endcond */ + __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ + __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[4]; + /** @endcond */ + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ + __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE3[8]; + /** @endcond */ + __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ + __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ + __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE4[1]; + /** @endcond */ + __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ + __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE5[6]; + /** @endcond */ + __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ + __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ + __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE6[1]; + /** @endcond */ + __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE7[61]; + /** @endcond */ + __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ + __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE8[128]; + /** @endcond */ + __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ +#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */ +#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */ +#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ +#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ + +#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ +#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ + +#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ +#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ + +#define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */ +#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ + +#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ +#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ +#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ + +#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */ +#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ +#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ +#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ +#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ +#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ + +#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ +#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */ +#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ +#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ +#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ + +#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ +#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ + +#define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */ +#define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */ + +#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ +#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ + +#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ +#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ + +#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ +#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ + +#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ +#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ + +#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ +#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ + +#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ +#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ +#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ + +#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ +#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ +#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ +#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ +#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ + +#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ +#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ + +#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ +#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ + +#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ +#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ + +#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */ +#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */ + +#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */ +#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */ + +#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ +#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ + +#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ +#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ + +#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ +#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ + +#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */ +#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */ + +#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */ +#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */ + +#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */ +#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */ + +#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */ +#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */ + +#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ +#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ + +#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ +#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ + +#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ +#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ + +#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ +#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ + +#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ +#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ + +#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ +#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ + +#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ +#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ + +#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */ +#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */ + +#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */ +#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */ + +#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */ +#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */ + +#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */ +#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */ + +#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ +#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ + +#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ +#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ + +#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ +#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ + +#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ +#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ + +#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ +#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ + +#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ +#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ + +#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ +#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ + +#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ +#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ + +#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */ +#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */ + +#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */ +#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */ + +#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */ +#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */ + +#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */ +#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ +#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ + +#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ +#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ +#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ +#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ +#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ + +#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ +#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ + +#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ +#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ + +#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ +#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ + +#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ +#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ + +#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ +#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ + +#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ +#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ + +#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ +#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ + +#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ +#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ + +#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ +#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ + +#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ +#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ + +#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ +#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ + +#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ +#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ + +#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ +#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ + +#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ +#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ + +#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ +#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ +#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ + +#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ +#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ + +#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ +#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ + +#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ +#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ + +#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ +#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ + +#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ +#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ + +#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ +#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ + +#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ +#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ + +#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ +#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ + +#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ +#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ + +#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ +#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ + +#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ +#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ + +#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ +#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ + +#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ +#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ + +#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ +#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ + +#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ +#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ + +#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ +#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ + +#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ +#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ + +#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ +#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ + +#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ +#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ + +#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ +#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ + +#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ +#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ + +#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ +#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ +#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ +#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ + +#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ +#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ + +#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ +#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ + +#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ +#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ + +#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ +#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ + +#define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */ +#define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */ + +#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */ +#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ + +#define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */ +#define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */ + +#define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */ +#define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */ +#define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */ +#define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */ +#define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */ +#define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */ +#define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */ +#define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ +#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ +#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ + +#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ +#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ +#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ +#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ +#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ + +#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ +#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ + +#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ +#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ + +#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ +#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ + +#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ +#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ + +#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ +#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ + +#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ +#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ + +#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ +#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ + +#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ +#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ + +#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ +#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ + +#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ +#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ + +#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ +#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ + +#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ +#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ +#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ + +#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ +#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ +#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ + +#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ +#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ + +/**@}*/ /* SYS_CONST */ +/**@}*/ /* end of SYS register group */ + +/** + @addtogroup NMI NMI Controller (NMI) + Memory Mapped Structure for NMI Controller +@{ */ + +typedef struct +{ + + + /** + * @var NMI_T::NMIEN + * Offset: 0x00 NMI Source Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) + * | | |0 = BOD NMI source Disabled. + * | | |1 = BOD NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect) + * | | |0 = IRC TRIM NMI source Disabled. + * | | |1 = IRC TRIM NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect) + * | | |0 = Power-down mode wake-up NMI source Disabled. + * | | |1 = Power-down mode wake-up NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect) + * | | |0 = SRAM parity check error NMI source Disabled. + * | | |1 = SRAM parity check error NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) + * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled. + * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect) + * | | |0 = RTC NMI source Disabled. + * | | |1 = RTC NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect) + * | | |0 = Backup register tamper detected NMI source Disabled. + * | | |1 = Backup register tamper detected NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled. + * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled. + * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. + * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled. + * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled. + * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled. + * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect) + * | | |0 = UART0 NMI source Disabled. + * | | |1 = UART0 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect) + * | | |0 = UART1 NMI source Disabled. + * | | |1 = UART1 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var NMI_T::NMISTS + * Offset: 0x04 NMI Source Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD Interrupt Flag (Read Only) + * | | |0 = BOD interrupt is deasserted. + * | | |1 = BOD interrupt is asserted. + * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only) + * | | |0 = HIRC TRIM interrupt is deasserted. + * | | |1 = HIRC TRIM interrupt is asserted. + * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only) + * | | |0 = Power-down mode wake-up interrupt is deasserted. + * | | |1 = Power-down mode wake-up interrupt is asserted. + * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only) + * | | |0 = SRAM parity check error interrupt is deasserted. + * | | |1 = SRAM parity check error interrupt is asserted. + * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) + * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted. + * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted. + * |[6] |RTC_INT |RTC Interrupt Flag (Read Only) + * | | |0 = RTC interrupt is deasserted. + * | | |1 = RTC interrupt is asserted. + * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only) + * | | |0 = Backup register tamper detected interrupt is deasserted. + * | | |1 = Backup register tamper detected interrupt is asserted. + * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted. + * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted. + * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted. + * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. + * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. + * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. + * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted. + * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted. + * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted. + * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted. + * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + */ + __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ + __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ + +} NMI_T; + +/** + @addtogroup NMI_CONST NMI Bit Field Definition + Constant Definitions for NMI Controller +@{ */ + +#define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ +#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ + +#define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */ +#define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */ + +#define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */ +#define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */ + +#define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */ +#define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */ + +#define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ +#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ + +#define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */ +#define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */ + +#define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */ +#define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */ + +#define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ +#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ + +#define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ +#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ + +#define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ +#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ + +#define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ +#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ + +#define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ +#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ + +#define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ +#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ + +#define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */ +#define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */ + +#define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */ +#define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */ + +#define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ +#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ + +#define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */ +#define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */ + +#define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */ +#define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */ + +#define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */ +#define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */ + +#define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ +#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ + +#define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */ +#define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */ + +#define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */ +#define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */ + +#define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ +#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ + +#define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ +#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ + +#define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ +#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ + +#define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ +#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ + +#define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ +#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ + +#define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ +#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ + +#define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */ +#define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */ + +#define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */ +#define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */ + +/**@}*/ /* NMI_CONST */ +/**@}*/ /* end of NMI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SYS_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/system_M480.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/system_M480.h new file mode 100644 index 0000000000..b161062afd --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/system_M480.h @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file system_M480.h + * @version V1.00 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480 + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __SYSTEM_M480_H__ +#define __SYSTEM_M480_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#define __HSI (12000000UL) /*!< PLL default output is 50MHz */ +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ +#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */ +#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */ + + +#define __SYSTEM_CLOCK (1UL*__HXT) + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the micro controller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M480_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/timer_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/timer_reg.h new file mode 100644 index 0000000000..109926d342 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/timer_reg.h @@ -0,0 +1,1072 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for TIMER Controller +@{ */ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, + * | | |CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. + * | | |1 = Capture Function source is from internal ACMP output signal + * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * | | |Note: This bit is read only. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer External Capture Pin Enable Bit + * | | |This bit enables the TMx_EXT capture pin input function. + * | | |0 =TMx_EXT (x= 0~3) pin Disabled. + * | | |1 =TMx_EXT (x= 0~3) pin Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = External Capture Mode Enabled. + * | | |1 = External Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer external interrupt + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[8] |ACMPSSEL |ACMP Source Selection to Trigger Capture Function + * | | |0 = Capture Function source is from internal ACMP0 output signal. + * | | |1 = Capture Function source is from internal ACMP1 output signal. + * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |100, 101 = Reserved. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the timer external capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status + * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or + * | | |capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC. + * |[1] |TRGEPWM |Trigger EPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. + * | | |000 = TMRx_CLK. + * | | |001 = Internal TIMER0 time-out or capture event. + * | | |010 = Internal TIMER1 time-out or capture event. + * | | |011 = Internal TIMER2 time-out or capture event. + * | | |100 = Internal TIMER3 time-out or capture event. + * | | |Others = Reserved. + * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled + * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled + * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled + * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[17:16] |BKPINSRC |Brake Pin Source Select + * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by BOD event Disabled. + * | | |1 = Brake Function triggered by BOD event Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When in up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMEADCTS + * Offset: 0x90 Timer PWM ADC Trigger Source Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion + * | | |000 = Trigger EADC conversion at zero point (ZIF). + * | | |001 = Trigger EADC conversion at period point (PIF). + * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF). + * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF). + * | | |Others = Reserved. + * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = Indicates the PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[7]; + /** @endcond */ + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller +@{ */ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_ACMPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ACMPSSEL Position */ +#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /*!< TIMER_T::EXTCTL: ACMPSSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */ +#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ +#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ + +#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ +#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ +#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ +#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ +#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ +#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */ +#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */ + +#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */ +#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __TIMER_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uart_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uart_reg.h new file mode 100644 index 0000000000..eb09b65317 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uart_reg.h @@ -0,0 +1,1272 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V1.00 + * @brief UART register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, + * | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |This bit can enable or disable TX PDMA service. + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of 'STOP Bit' + * | | |0 = One 'STOP bit' is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data + * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic '1's is transmitted and checked in each word. + * | | |1 = Even number of logic '1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0 + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS (Request-to-send) Signal Control + * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic '1' when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) + * | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer + * | | |When UART receives one byte from external device, RXPTR increases one + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15 + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared + * | | |The UART controller can not transmit or receive data at this moment + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit" + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit". + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set) + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]) + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]) + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider + * | | |This filed is used in baud rate calculation + * | | |The detail description is shown in Table 7.15-4. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2 + * | | |The detail description is shown in Table 7.15-4 + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode + * | | |The detail description is shown in Table 7.15-4. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode + * | | |The detail description is shown in Table 7.15-4. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is BRKFL + 1. + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FUNCSEL |Function Select + * | | |00 = UART function. + * | | |01 = LIN function. + * | | |10 = IrDA function. + * | | |11 = RS-485 function. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set + * | | |The TX and RX complete current task before disable TX and RX + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character + * | | |User must set the bit before checksum reception. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode + * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization). + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode). + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10 + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled . + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note2: This break field length is BRKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes 'break field'. + * | | |01 = The LIN header includes 'break field' and 'sync field'. + * | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'. + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it + * | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', + * | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', + * | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and + * | | |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note2: This bit can be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. + * | | |nCTS change will wake-up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. + * | | |incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. + * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from + * | | |Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in. + * | | |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode + * | | |and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the. + * | | |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up + * | | |system from Power-down mode. + * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold + * | | |wake-up . + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out + * | | |wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. + * | | |wake-up. + * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UART_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ui2c_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ui2c_reg.h new file mode 100644 index 0000000000..6fa86a0d30 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ui2c_reg.h @@ -0,0 +1,582 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UI2C I2C Mode of USCI Controller(UI2C) + Memory Mapped Structure for UI2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits + * | | |And in I2C protocol, the length fixed as 8 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller +@{ */ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UI2C_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbd_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbd_reg.h new file mode 100644 index 0000000000..6fb5bd1aa9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbd_reg.h @@ -0,0 +1,633 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V1.00 + * @brief USBD register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBD USB Device Controller(USBD) + Memory Mapped Structure for USBD Controller +@{ */ + +typedef struct +{ + + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x000 Endpoint n Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + { BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x004 Endpoint n Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x008 Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint STATE + * | | |00 = Endpoint is Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction + * | | |hardware will toggle automatically in IN token base on the bit. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * @var USBD_EP_T::CFGP + * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is write 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is not attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event does not occur. + * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event does not occur. + * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * | | |Note: This bit is read only. + * |[1] |SUSPEND |Suspend Status + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. + * | | |Note: This bit is read only. + * |[2] |RESUME |Resume Status + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * | | |Note: This bit is read only. + * |[3] |TOUT |Time-out Status + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * | | |Note: This bit is read only. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= the valid LPM Token will be NYET. + * | | |1= the valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * | | |Note: This bit is read only. + * |[13] |L1RESUME |LPM L1 Resume + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state Resume from LPM L1 state suspend. + * | | |Note: This bit is read only. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[03:00] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[07:04] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:08] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token + * @var USBD_T::FN + * Offset: 0x8C USB Frame number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[24]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[283]; + /// @endcond //HIDDEN_SYMBOLS + USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ + +} USBD_T; + + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller +@{ */ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBD_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbh_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbh_reg.h new file mode 100644 index 0000000000..cc299084aa --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbh_reg.h @@ -0,0 +1,796 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @version V1.00 + * @brief USBH register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller +@{ */ + +typedef struct +{ + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this + * | | |Value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBSUSPEND. + * | | |01 = USBOPERATIONAL. + * | | |10 = USBRESUME. + * | | |11 = USBRESET. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 =.Host Controller didn't update HccaDoneHead. + * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a 'Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 =.Not the start of a frame. + * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing '1' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[30:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from 'FFFFh' to '0h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global Switching. + * | | |1 = Individual Switching. + * |[11] |OCPM |over Current Protection Mode + * | | |This bit describes how the over current status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global Over current. + * | | |1 = Individual Over current. + * |[12] |NOCP |No over Current Protection + * | | |This bit describes how the over current status for the Root Hub ports reported. + * | | |0 = Over current status is reported. + * | | |1 = Over current status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if PowerSwitchingMode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower) + * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |over Current Indicator + * | | |This bit reflects the state of the over current status pin + * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |over Current Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus[2] + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write) + * | | |This bit reflects the state of the over current status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[4] |PRS |Port Reset Status + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) + * | | |This bit defines the speed (and bud idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus1[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus1[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus1[1]) didn't change. + * | | |1 = PES (HcRhPortStatus1[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not completed. + * | | |1 = Port resume completed. + * |[19] |OCIC |Port over Current Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus1[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus1[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus1[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBYEN |USB Transceiver Standby Enable Bit + * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. + * | | |0 = The USB transceiver would never enter the standby mode. + * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). + * @var USBH_T::HcMiscControl + * Offset: 0x204 Host Controller Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus ERROR Response + * | | |This bit indicates there is an ERROR response received in AHB bus. + * | | |0 = No ERROR response received. + * | | |1 = ERROR response received. + * |[3] |OCAL |over Current Active Low + * | | |This bit controls the polarity of over current flag from external power IC. + * | | |0 = Over current flag is high active. + * | | |1 = Over current flag is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[105]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller +@{ */ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */ + +#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ +#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ + +#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ +#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ + +#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ +#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ + +#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ +#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBH_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uspi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uspi_reg.h new file mode 100644 index 0000000000..dd2c5bb874 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uspi_reg.h @@ -0,0 +1,676 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USPI SPI Mode of USCI Controller(USPI) + Memory Mapped Structure for USPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Notice: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |MODE0 = The idle state of SPI clock is low level + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |MODE1 = The idle state of SPI clock is low level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE2 = The idle state of SPI clock is high level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE3 = The idle state of SPI clock is high level + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Other values are reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under run event occurs. + * | | |1 = The output data level is 1 if TX under run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event does not occur. + * | | |1 = Transmit start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event does not occur. + * | | |1 = Transmit end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event does not occur. + * | | |1 = Receive start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event does not occur. + * | | |1 = Receive end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only) + * | | |0 = Slave time-out event does not occur. + * | | |1 = Slave time-out event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only) + * | | |0 = Slave bit count error event does not occur. + * | | |1 = Slave bit count error event occurs. + * | | |Note: It is cleared by software writes 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under-run event does not occur. + * | | |1 = Slave transmit under-run event occurs. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller +@{ */ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USPI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uuart_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uuart_reg.h new file mode 100644 index 0000000000..d0b68b4c2e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uuart_reg.h @@ -0,0 +1,678 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V1.00 + * @brief UUART register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UUART UART Mode of USCI Controller(UUART) + Memory Mapped Structure for UUART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable BIt + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and + * | | |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 + * | | |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 10. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |.. + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note 1: It is cleared automatically after one PCLK cycle. + * | | |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected + * | | |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note 1: This bit is used for nRTS auto direction control for RS485. + * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit + * | | |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits + * | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55) + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note 1: It is cleared by software writing one into this bit. + * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' + * | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data + * | | |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and + * | | |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note 1: This bit is set at the same time of ABRDETIF. + * | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller +@{ */ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UUART_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wdt_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wdt_reg.h new file mode 100644 index 0000000000..8d4ef0fea5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wdt_reg.h @@ -0,0 +1,182 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V1.00 + * @brief WDT register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect) + * | | |0 = No effect. + * | | |1 = Reset the internal 18-bit WDT up counter value. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit will be automatically cleared by hardware. + * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the interrupt wake-up flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = WDT Disabled (This action will reset the internal up counter value). + * | | |1 = WDT Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. + * |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period for the WDT. + * | | |000 = 24 * WDT_CLK. + * | | |001 = 26 * WDT_CLK. + * | | |010 = 28 * WDT_CLK. + * | | |011 = 210 * WDT_CLK. + * | | |100 = 212 * WDT_CLK. + * | | |101 = 214 * WDT_CLK. + * | | |110 = 216 * WDT_CLK. + * | | |111 = 218 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) + * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. + * | | |0 = Set WDTEN bit is completed. + * | | |1 = Set WDTEN bit is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened + * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + * | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit + * | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller +@{ */ + +#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */ +#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WDT_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wwdt_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wwdt_reg.h new file mode 100644 index 0000000000..963a4fbf7f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wwdt_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V1.00 + * @brief WWDT register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT + * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgement effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT counter value matches CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller +@{ */ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WWDT_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/ARM/startup_M480.s b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/ARM/startup_M480.s new file mode 100644 index 0000000000..9887fb11a2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/ARM/startup_M480.s @@ -0,0 +1,479 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Stack_Size +Stack_Size EQU 0x00000800 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Heap_Size +Heap_Size EQU 0x00000100 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD EPWM0P0_IRQHandler ; 25: + DCD EPWM0P1_IRQHandler ; 26: + DCD EPWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD EPWM1P0_IRQHandler ; 29: + DCD EPWM1P1_IRQHandler ; 30: + DCD EPWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0 + DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2 + DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD Default_Handler ; 50: Reserved + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD Default_Handler ; 81: ToDo: Add description to this Interrupt + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + IF :LNOT: :DEF: ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + ENDIF + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock + LDR R0, =0x40000100 + LDR R1, =0 + STR R1, [R0] + + LDR R0, =__main + BX R0 + + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT IRC_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT RAMPE_IRQHandler [WEAK] + EXPORT CKFAIL_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT EINT5_IRQHandler [WEAK] + EXPORT GPA_IRQHandler [WEAK] + EXPORT GPB_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT GPD_IRQHandler [WEAK] + EXPORT GPE_IRQHandler [WEAK] + EXPORT GPF_IRQHandler [WEAK] + EXPORT QSPI0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT BRAKE0_IRQHandler [WEAK] + EXPORT EPWM0P0_IRQHandler [WEAK] + EXPORT EPWM0P1_IRQHandler [WEAK] + EXPORT EPWM0P2_IRQHandler [WEAK] + EXPORT BRAKE1_IRQHandler [WEAK] + EXPORT EPWM1P0_IRQHandler [WEAK] + EXPORT EPWM1P1_IRQHandler [WEAK] + EXPORT EPWM1P2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT ADC00_IRQHandler [WEAK] + EXPORT ADC01_IRQHandler [WEAK] + EXPORT ACMP01_IRQHandler [WEAK] + EXPORT ADC02_IRQHandler [WEAK] + EXPORT ADC03_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT OHCI_IRQHandler [WEAK] + EXPORT USBOTG_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT SC0_IRQHandler [WEAK] + EXPORT SC1_IRQHandler [WEAK] + EXPORT SC2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SDH0_IRQHandler [WEAK] + EXPORT USBD20_IRQHandler [WEAK] + EXPORT EMAC_TX_IRQHandler [WEAK] + EXPORT EMAC_RX_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT OPA0_IRQHandler [WEAK] + EXPORT CRYPTO_IRQHandler [WEAK] + EXPORT GPG_IRQHandler [WEAK] + EXPORT EINT6_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT USCI0_IRQHandler [WEAK] + EXPORT USCI1_IRQHandler [WEAK] + EXPORT BPWM0_IRQHandler [WEAK] + EXPORT BPWM1_IRQHandler [WEAK] + EXPORT SPIM_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT QEI0_IRQHandler [WEAK] + EXPORT QEI1_IRQHandler [WEAK] + EXPORT ECAP0_IRQHandler [WEAK] + EXPORT ECAP1_IRQHandler [WEAK] + EXPORT GPH_IRQHandler [WEAK] + EXPORT EINT7_IRQHandler [WEAK] + EXPORT SDH1_IRQHandler [WEAK] + EXPORT EHCI_IRQHandler [WEAK] + EXPORT USBOTG20_IRQHandler [WEAK] + +Default__IRQHandler +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +EPWM0P0_IRQHandler +EPWM0P1_IRQHandler +EPWM0P2_IRQHandler +BRAKE1_IRQHandler +EPWM1P0_IRQHandler +EPWM1P1_IRQHandler +EPWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +ADC00_IRQHandler +ADC01_IRQHandler +ACMP01_IRQHandler +ADC02_IRQHandler +ADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler + + + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END +;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/_syscalls.c b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/_syscalls.c new file mode 100644 index 0000000000..adedf280d8 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/_syscalls.c @@ -0,0 +1,1168 @@ +// +// This file is part of the uOS++ III distribution +// Parts of this file are from the newlib sources, issued under GPL. +// Copyright (c) 2014 Liviu Ionescu +// + +// ---------------------------------------------------------------------------- + +int errno; +void *__dso_handle __attribute__ ((weak)); + +// ---------------------------------------------------------------------------- + +#if !defined(OS_USE_SEMIHOSTING) + +#include <_ansi.h> +#include <_syslist.h> +#include +//#include +#include +#include +#include +#include +#include + +void +__initialize_args(int* p_argc, char*** p_argv); + +// This is the standard default implementation for the routine to +// process args. It returns a single empty arg. +// For semihosting applications, this is redefined to get the real +// args from the debugger. You can also use it if you decide to keep +// some args in a non-volatile memory. + +void __attribute__((weak)) +__initialize_args(int* p_argc, char*** p_argv) +{ + // By the time we reach this, the data and bss should have been initialised. + + // The strings pointed to by the argv array shall be modifiable by the + // program, and retain their last-stored values between program startup + // and program termination. (static, no const) + static char name[] = ""; + + // The string pointed to by argv[0] represents the program name; + // argv[0][0] shall be the null character if the program name is not + // available from the host environment. argv[argc] shall be a null pointer. + // (static, no const) + static char* argv[2] = + { name, NULL }; + + *p_argc = 1; + *p_argv = &argv[0]; + return; +} + +// These functions are defined here to avoid linker errors in freestanding +// applications. They might be called in some error cases from library +// code. +// +// If you detect other functions to be needed, just let us know +// and we'll add them. + +int +raise(int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int +kill(pid_t pid, int sig); + +int +kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +#endif // !defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +// If you need the empty definitions, remove the -ffreestanding option. + +#if __STDC_HOSTED__ == 1 + +char* __env[1] = +{ 0 }; +char** environ = __env; + +#if !defined(OS_USE_SEMIHOSTING) + +// Forward declarations + +int +_chown(const char* path, uid_t owner, gid_t group); + +int +_close(int fildes); + +int +_execve(char* name, char** argv, char** env); + +int +_fork(void); + +int +_fstat(int fildes, struct stat* st); + +int +_getpid(void); + +int +_gettimeofday(struct timeval* ptimeval, void* ptimezone); + +int +_isatty(int file); + +int +_kill(int pid, int sig); + +int +_link(char* existing, char* _new); + +int +_lseek(int file, int ptr, int dir); + +int +_open(char* file, int flags, int mode); + +int +_read(int file, char* ptr, int len); + +int +_readlink(const char* path, char* buf, size_t bufsize); + +int +_stat(const char* file, struct stat* st); + +int +_symlink(const char* path1, const char* path2); + +clock_t +_times(struct tms* buf); + +int +_unlink(char* name); + +int +_wait(int* status); + +int +_write(int file, char* ptr, int len); + +// Definitions + +int __attribute__((weak)) +_chown(const char* path __attribute__((unused)), + uid_t owner __attribute__((unused)), gid_t group __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_close(int fildes __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)), + char** env __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fork(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fstat(int fildes __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_getpid(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_gettimeofday(struct timeval* ptimeval __attribute__((unused)), + void* ptimezone __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_isatty(int file __attribute__((unused))) +{ + errno = ENOSYS; + return 0; +} + +int __attribute__((weak)) +_kill(int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_link(char* existing __attribute__((unused)), + char* _new __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)), + int dir __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_open(char* file __attribute__((unused)), int flags __attribute__((unused)), + int mode __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_read(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_readlink(const char* path __attribute__((unused)), + char* buf __attribute__((unused)), size_t bufsize __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_stat(const char* file __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_symlink(const char* path1 __attribute__((unused)), + const char* path2 __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +clock_t __attribute__((weak)) +_times(struct tms* buf __attribute__((unused))) +{ + errno = ENOSYS; + return ((clock_t) -1); +} + +int __attribute__((weak)) +_unlink(char* name __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_wait(int* status __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_write(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +#else // defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "semihosting.h" + +int _kill (int pid, int sig); + +void __attribute__((noreturn)) _exit (int status); + +// Forward declarations. +int _system (const char*); +int _rename (const char*, const char*); +int _isatty (int); +clock_t _times (struct tms*); +int _gettimeofday (struct timeval *, void*); +int _unlink (const char*); +int _link (void); + +int _stat (const char*, struct stat*); + +int _fstat (int, struct stat*); +int _swistat (int fd, struct stat* st); +int _getpid (int); +int _close (int); +clock_t _clock (void); +int _swiclose (int); +int _open (const char*, int, ...); +int _swiopen (const char*, int); +int _write (int, char*, int); +int _swiwrite (int, char*, int); +int _lseek (int, int, int); +int _swilseek (int, int, int); +int _read (int, char*, int); +int _swiread (int, char*, int); + +void initialise_monitor_handles (void); + +void __initialize_args (int* p_argc, char*** p_argv); + +static int +checkerror (int); +static int +error (int); +static int +get_errno (void); + +// ---------------------------------------------------------------------------- + +#define ARGS_BUF_ARRAY_SIZE 80 +#define ARGV_BUF_ARRAY_SIZE 10 + +typedef struct +{ + char* pCommandLine; + int size; +} CommandLineBlock; + +void __initialize_args (int* p_argc, char*** p_argv) +{ + // Array of chars to receive the command line from the host + static char args_buf[ARGS_BUF_ARRAY_SIZE]; + + // Array of pointers to store the final argv pointers (pointing + // in the above array). + static char* argv_buf[ARGV_BUF_ARRAY_SIZE]; + + int argc = 0; + int isInArgument = 0; + + CommandLineBlock cmdBlock; + cmdBlock.pCommandLine = args_buf; + cmdBlock.size = sizeof(args_buf) - 1; + + int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock); + if (ret == 0) + { + + // In case the host send more than we can chew, limit the + // string to our buffer. + args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0'; + + // The command line is a null terminated string + char* p = cmdBlock.pCommandLine; + + int delim = '\0'; + int ch; + + while ((ch = *p) != '\0') + { + if (isInArgument == 0) + { + if (!isblank(ch)) + { + if (argc >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1)) + break; + + if (ch == '"' || ch == '\'') + { + // Remember the delimiter to search for the + // corresponding terminator + delim = ch; + ++p; // skip the delimiter + ch = *p; + } + // Remember the arg beginning address + argv_buf[argc++] = p; + isInArgument = 1; + } + } + else if (delim != '\0') + { + if ((ch == delim)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + } + else if (isblank(ch)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + ++p; + } + } + + if (argc == 0) + { + // No args found in string, return a single empty name. + args_buf[0] = '\0'; + argv_buf[0] = &args_buf[0]; + ++argc; + } + + // Must end the array with a null pointer. + argv_buf[argc] = NULL; + + *p_argc = argc; + *p_argv = &argv_buf[0]; + + // temporary here + initialise_monitor_handles (); + + return; +} + +// ---------------------------------------------------------------------------- + +void _exit (int status) +{ + /* There is only one SWI for both _exit and _kill. For _exit, call + the SWI with the second argument set to -1, an invalid value for + signum, so that the SWI handler can distinguish the two calls. + Note: The RDI implementation of _kill throws away both its + arguments. */ + report_exception (status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError); +} + +// ---------------------------------------------------------------------------- + +int __attribute__((weak)) +_kill (int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +/* Struct used to keep track of the file position, just so we + can implement fseek(fh,x,SEEK_CUR). */ +struct fdent +{ + int handle; + int pos; +}; + +#define MAX_OPEN_FILES 20 + +/* User file descriptors (fd) are integer indexes into + the openfiles[] array. Error checking is done by using + findslot(). + + This openfiles array is manipulated directly by only + these 5 functions: + + findslot() - Translate entry. + newslot() - Find empty entry. + initilise_monitor_handles() - Initialize entries. + _swiopen() - Initialize entry. + _close() - Handle stdout == stderr case. + + Every other function must use findslot(). */ + +static struct fdent openfiles[MAX_OPEN_FILES]; + +static struct fdent* findslot (int); +static int newslot (void); + +/* Register name faking - works in collusion with the linker. */ +register char* stack_ptr asm ("sp"); + +/* following is copied from libc/stdio/local.h to check std streams */ +extern void _EXFUN(__sinit,(struct _reent*)); +#define CHECK_INIT(ptr) \ + do \ + { \ + if ((ptr) && !(ptr)->__sdidinit) \ + __sinit (ptr); \ + } \ + while (0) + +static int monitor_stdin; +static int monitor_stdout; +static int monitor_stderr; + +/* Return a pointer to the structure associated with + the user file descriptor fd. */ +static struct fdent* +findslot (int fd) +{ + CHECK_INIT(_REENT); + + /* User file descriptor is out of range. */ + if ((unsigned int) fd >= MAX_OPEN_FILES) + { + return NULL; + } + + /* User file descriptor is open? */ + if (openfiles[fd].handle == -1) + { + return NULL; + } + + /* Valid. */ + return &openfiles[fd]; +} + +/* Return the next lowest numbered free file + structure, or -1 if we can't find one. */ +static int +newslot (void) +{ + int i; + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + if (openfiles[i].handle == -1) + { + break; + } + } + + if (i == MAX_OPEN_FILES) + { + return -1; + } + + return i; +} + +void +initialise_monitor_handles (void) +{ + int i; + + /* Open the standard file descriptors by opening the special + * teletype device, ":tt", read-only to obtain a descriptor for + * standard input and write-only to obtain a descriptor for standard + * output. Finally, open ":tt" in append mode to obtain a descriptor + * for standard error. Since this is a write mode, most kernels will + * probably return the same value as for standard output, but the + * kernel can differentiate the two using the mode flag and return a + * different descriptor for standard error. + */ + + int volatile block[3]; + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 0; /* mode "r" */ + monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 4; /* mode "w" */ + monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 8; /* mode "a" */ + monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + /* If we failed to open stderr, redirect to stdout. */ + if (monitor_stderr == -1) + { + monitor_stderr = monitor_stdout; + } + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + openfiles[i].handle = -1; + } + + openfiles[0].handle = monitor_stdin; + openfiles[0].pos = 0; + openfiles[1].handle = monitor_stdout; + openfiles[1].pos = 0; + openfiles[2].handle = monitor_stderr; + openfiles[2].pos = 0; +} + +static int +get_errno (void) +{ + return call_host (SEMIHOSTING_SYS_ERRNO, NULL); +} + +/* Set errno and return result. */ +static int +error (int result) +{ + errno = get_errno (); + return result; +} + +/* Check the return and set errno appropriately. */ +static int +checkerror (int result) +{ + if (result == -1) + { + return error (-1); + } + + return result; +} + +/* fh, is a valid internal file handle. + ptr, is a null terminated string. + len, is the length in bytes to read. + Returns the number of bytes *not* written. */ +int +_swiread (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_READ, block)); +} + +/* fd, is a valid user file handle. + Translates the return of _swiread into + bytes read. */ +int +_read (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiread (pfd->handle, ptr, len); + + if (res == -1) + { + return res; + } + + pfd->pos += len - res; + + /* res == len is not an error, + at least if we want feof() to work. */ + return len - res; +} + +/* fd, is a user file descriptor. */ +int _swilseek (int fd, int ptr, int dir) +{ + int res; + struct fdent *pfd; + + /* Valid file descriptor? */ + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Valid whence? */ + if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END)) + { + errno = EINVAL; + return -1; + } + + /* Convert SEEK_CUR to SEEK_SET */ + if (dir == SEEK_CUR) + { + ptr = pfd->pos + ptr; + /* The resulting file offset would be negative. */ + if (ptr < 0) + { + errno = EINVAL; + if ((pfd->pos > 0) && (ptr > 0)) + { + errno = EOVERFLOW; + } + return -1; + } + dir = SEEK_SET; + } + + int block[2]; + if (dir == SEEK_END) + { + block[0] = pfd->handle; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block)); + if (res == -1) + { + return -1; + } + ptr += res; + } + + /* This code only does absolute seeks. */ + block[0] = pfd->handle; + block[1] = ptr; + res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block)); + + /* At this point ptr is the current file position. */ + if (res >= 0) + { + pfd->pos = ptr; + return ptr; + } + else + { + return -1; + } +} + +int _lseek (int fd, int ptr, int dir) +{ + return _swilseek (fd, ptr, dir); +} + +/* fh, is a valid internal file handle. + Returns the number of bytes *not* written. */ +int _swiwrite (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block)); +} + +/* fd, is a user file descriptor. */ +int _write (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiwrite (pfd->handle, ptr, len); + + /* Clearly an error. */ + if (res < 0) + { + return -1; + } + + pfd->pos += len - res; + + /* We wrote 0 bytes? + Retrieve errno just in case. */ + if ((len - res) == 0) + { + return error (0); + } + + return (len - res); +} + +int _swiopen (const char* path, int flags) +{ + int aflags = 0, fh; + uint32_t block[3]; + + int fd = newslot (); + + if (fd == -1) + { + errno = EMFILE; + return -1; + } + + /* It is an error to open a file that already exists. */ + if ((flags & O_CREAT) && (flags & O_EXCL)) + { + struct stat st; + int res; + res = _stat (path, &st); + if (res != -1) + { + errno = EEXIST; + return -1; + } + } + + /* The flags are Unix-style, so we need to convert them. */ +#ifdef O_BINARY + if (flags & O_BINARY) + { + aflags |= 1; + } +#endif + + /* In O_RDONLY we expect aflags == 0. */ + + if (flags & O_RDWR) + { + aflags |= 2; + } + + if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY)) + { + aflags |= 4; + } + + if (flags & O_APPEND) + { + /* Can't ask for w AND a; means just 'a'. */ + aflags &= ~4; + aflags |= 8; + } + + block[0] = (uint32_t) path; + block[2] = strlen (path); + block[1] = (uint32_t) aflags; + + fh = call_host (SEMIHOSTING_SYS_OPEN, block); + + /* Return a user file descriptor or an error. */ + if (fh >= 0) + { + openfiles[fd].handle = fh; + openfiles[fd].pos = 0; + return fd; + } + else + { + return error (fh); + } +} + +int _open (const char* path, int flags, ...) +{ + return _swiopen (path, flags); +} + +/* fh, is a valid internal file handle. */ +int _swiclose (int fh) +{ + return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh)); +} + +/* fd, is a user file descriptor. */ +int _close (int fd) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Handle stderr == stdout. */ + if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle)) + { + pfd->handle = -1; + return 0; + } + + /* Attempt to close the handle. */ + res = _swiclose (pfd->handle); + + /* Reclaim handle? */ + if (res == 0) + { + pfd->handle = -1; + } + + return res; +} + +int __attribute__((weak)) +_getpid (int n __attribute__ ((unused))) +{ + return 1; +} + +int +_swistat (int fd, struct stat* st) +{ + struct fdent *pfd; + int res; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Always assume a character device, + with 1024 byte blocks. */ + st->st_mode |= S_IFCHR; + st->st_blksize = 1024; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle)); + if (res == -1) + { + return -1; + } + + /* Return the file size. */ + st->st_size = res; + return 0; +} + +int __attribute__((weak)) +_fstat (int fd, struct stat* st) +{ + memset (st, 0, sizeof(*st)); + return _swistat (fd, st); +} + +int __attribute__((weak)) +_stat (const char*fname, struct stat *st) +{ + int fd, res; + memset (st, 0, sizeof(*st)); + /* The best we can do is try to open the file readonly. + If it exists, then we can guess a few things about it. */ + if ((fd = _open (fname, O_RDONLY)) == -1) + { + return -1; + } + st->st_mode |= S_IFREG | S_IREAD; + res = _swistat (fd, st); + /* Not interested in the error. */ + _close (fd); + return res; +} + +int __attribute__((weak)) +_link (void) +{ + errno = ENOSYS; + return -1; +} + +int _unlink (const char* path) +{ + int res; + uint32_t block[2]; + block[0] = (uint32_t) path; + block[1] = strlen (path); + res = call_host (SEMIHOSTING_SYS_REMOVE, block); + + if (res == -1) + { + return error (res); + } + return 0; +} + +int _gettimeofday (struct timeval* tp, void* tzvp) +{ + struct timezone* tzp = tzvp; + if (tp) + { + /* Ask the host for the seconds since the Unix epoch. */ + tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL); + tp->tv_usec = 0; + } + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t _clock (void) +{ + clock_t timeval; + + timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL); + return timeval; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t +_times (struct tms* tp) +{ + clock_t timeval = _clock (); + + if (tp) + { + tp->tms_utime = timeval; /* user time */ + tp->tms_stime = 0; /* system time */ + tp->tms_cutime = 0; /* user time, children */ + tp->tms_cstime = 0; /* system time, children */ + } + + return timeval; +} + +int _isatty (int fd) +{ + struct fdent *pfd; + int tty; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return 0; + } + + tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle); + + if (tty == 1) + { + return 1; + } + + errno = get_errno (); + return 0; +} + +int _system (const char* s) +{ + uint32_t block[2]; + int e; + + /* Hmmm. The ARM debug interface specification doesn't say whether + SYS_SYSTEM does the right thing with a null argument, or assign any + meaning to its return value. Try to do something reasonable.... */ + if (!s) + { + return 1; /* maybe there is a shell available? we can hope. :-P */ + } + block[0] = (uint32_t) s; + block[1] = strlen (s); + e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block)); + if ((e >= 0) && (e < 256)) + { + /* We have to convert e, an exit status to the encoded status of + the command. To avoid hard coding the exit status, we simply + loop until we find the right position. */ + int exit_code; + + for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1) + { + continue; + } + } + return e; +} + +int _rename (const char* oldpath, const char* newpath) +{ + uint32_t block[4]; + block[0] = (uint32_t) oldpath; + block[1] = strlen (oldpath); + block[2] = (uint32_t) newpath; + block[3] = strlen (newpath); + return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0; +} + +// ---------------------------------------------------------------------------- +// Required by Google Tests + +int mkdir (const char *path __attribute__((unused)), mode_t mode __attribute__((unused))) +{ +#if 0 + // always return true + return 0; +#else + errno = ENOSYS; + return -1; +#endif +} + +char *getcwd (char *buf, size_t size) +{ + // no cwd available via semihosting, so we use the temporary folder + strncpy (buf, "/tmp", size); + return buf; +} + +#endif // defined OS_USE_SEMIHOSTING + +#endif // __STDC_HOSTED__ == 1 diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm.ld b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm.ld new file mode 100644 index 0000000000..43c1ee5994 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm.ld @@ -0,0 +1,195 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x28000 /* 160k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm_128k.ld b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm_128k.ld new file mode 100644 index 0000000000..e3d71e6f68 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm_128k.ld @@ -0,0 +1,195 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/semihosting.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/semihosting.h new file mode 100644 index 0000000000..337085416b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/semihosting.h @@ -0,0 +1,116 @@ + +#ifndef ARM_SEMIHOSTING_H_ +#define ARM_SEMIHOSTING_H_ + +// ---------------------------------------------------------------------------- + +// Semihosting operations. +enum OperationNumber +{ + // Regular operations + SEMIHOSTING_EnterSVC = 0x17, + SEMIHOSTING_ReportException = 0x18, + SEMIHOSTING_SYS_CLOSE = 0x02, + SEMIHOSTING_SYS_CLOCK = 0x10, + SEMIHOSTING_SYS_ELAPSED = 0x30, + SEMIHOSTING_SYS_ERRNO = 0x13, + SEMIHOSTING_SYS_FLEN = 0x0C, + SEMIHOSTING_SYS_GET_CMDLINE = 0x15, + SEMIHOSTING_SYS_HEAPINFO = 0x16, + SEMIHOSTING_SYS_ISERROR = 0x08, + SEMIHOSTING_SYS_ISTTY = 0x09, + SEMIHOSTING_SYS_OPEN = 0x01, + SEMIHOSTING_SYS_READ = 0x06, + SEMIHOSTING_SYS_READC = 0x07, + SEMIHOSTING_SYS_REMOVE = 0x0E, + SEMIHOSTING_SYS_RENAME = 0x0F, + SEMIHOSTING_SYS_SEEK = 0x0A, + SEMIHOSTING_SYS_SYSTEM = 0x12, + SEMIHOSTING_SYS_TICKFREQ = 0x31, + SEMIHOSTING_SYS_TIME = 0x11, + SEMIHOSTING_SYS_TMPNAM = 0x0D, + SEMIHOSTING_SYS_WRITE = 0x05, + SEMIHOSTING_SYS_WRITEC = 0x03, + SEMIHOSTING_SYS_WRITE0 = 0x04, + + // Codes returned by SEMIHOSTING_ReportException + ADP_Stopped_ApplicationExit = ((2 << 16) + 38), + ADP_Stopped_RunTimeError = ((2 << 16) + 35), + +}; + +// ---------------------------------------------------------------------------- + +// SWI numbers and reason codes for RDI (Angel) monitors. +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +// For thumb only architectures use the BKPT instruction instead of SWI. +#if defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) \ + || defined(__ARM_ARCH_6M__) +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) +// Testing the local semihosting handler cannot use another BKPT, since this +// configuration cannot trigger HaedFault exceptions while the debugger is +// connected, so we use an illegal op code, that will trigger an +// UsageFault exception. +#define AngelSWITestFault "setend be" +#define AngelSWITestFaultOpCode (0xB658) +#endif + +static inline int +__attribute__ ((always_inline)) +call_host (int reason, void* arg) +{ + int value; + asm volatile ( + + " mov r0, %[rsn] \n" + " mov r1, %[arg] \n" +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + " " AngelSWITestFault " \n" +#else + " " AngelSWIInsn " %[swi] \n" +#endif + " mov %[val], r0" + + : [val] "=r" (value) /* Outputs */ + : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + // Clobbers r0 and r1, and lr if in supervisor mode + ); + + // Accordingly to page 13-77 of ARM DUI 0040D other registers + // can also be clobbered. Some memory positions may also be + // changed by a system call, so they should not be kept in + // registers. Note: we are assuming the manual is right and + // Angel is respecting the APCS. + return value; +} + +// ---------------------------------------------------------------------------- + +// Function used in _exit() to return the status code as Angel exception. +static inline void +__attribute__ ((always_inline,noreturn)) +report_exception (int reason) +{ + call_host (SEMIHOSTING_ReportException, (void*) reason); + + for (;;) + ; +} + +// ---------------------------------------------------------------------------- + +#endif // ARM_SEMIHOSTING_H_ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup.s b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup.s new file mode 100644 index 0000000000..00fdcf9cf3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup.s @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + // Unlock Register + ldr r0, =0x40000100 + ldr r1, =0x59 + str r1, [r0] + ldr r1, =0x16 + str r1, [r0] + ldr r1, =0x88 + str r1, [r0] + + // ENABLE_SPIM_CACHE + ldr r0, =0x40000200 // R0 = Clock Controller Register Base Address + ldr r1, [r0,#0x4] // R1 = 0x40000204 (AHBCLK) + orr r1, r1, #0x4000 + str r1, [r0,#0x4] // CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk// + + ldr r0, =0x40007000 // R0 = SPIM Register Base Address + ldr r1, [r0,#4] // R1 = SPIM->CTL1 + orr r1, r1,#2 // R1 |= SPIM_CTL1_CACHEOFF_Msk + str r1, [r0,#4] // _SPIM_DISABLE_CACHE() + ldr r1, [r0,#4] // R1 = SPIM->CTL1 + orr r1, r1, #4 // R1 |= SPIM_CTL1_CCMEN_Msk + str r1, [r0,#4] // _SPIM_ENABLE_CCM() + + // Lock + ldr r0, =0x40000100 + ldr r1, =0 + str r1, [r0] + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // DCDReserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word BOD_IRQHandler // 0: Brown Out detection + .word IRC_IRQHandler // 1: Internal RC + .word PWRWU_IRQHandler // 2: Power down wake up + .word RAMPE_IRQHandler // 3: RAM parity error + .word CKFAIL_IRQHandler // 4: Clock detection fail + .word Default_Handler // 5: Reserved + .word RTC_IRQHandler // 6: Real Time Clock + .word TAMPER_IRQHandler // 7: Tamper detection + .word WDT_IRQHandler // 8: Watchdog timer + .word WWDT_IRQHandler // 9: Window watchdog timer + .word EINT0_IRQHandler // 10: External Input 0 + .word EINT1_IRQHandler // 11: External Input 1 + .word EINT2_IRQHandler // 12: External Input 2 + .word EINT3_IRQHandler // 13: External Input 3 + .word EINT4_IRQHandler // 14: External Input 4 + .word EINT5_IRQHandler // 15: External Input 5 + .word GPA_IRQHandler // 16: GPIO Port A + .word GPB_IRQHandler // 17: GPIO Port B + .word GPC_IRQHandler // 18: GPIO Port C + .word GPD_IRQHandler // 19: GPIO Port D + .word GPE_IRQHandler // 20: GPIO Port E + .word GPF_IRQHandler // 21: GPIO Port F + .word QSPI0_IRQHandler // 22: QSPI0 + .word SPI0_IRQHandler // 23: SPI0 + .word BRAKE0_IRQHandler // 24: + .word EPWM0P0_IRQHandler // 25: + .word EPWM0P1_IRQHandler // 26: + .word EPWM0P2_IRQHandler // 27: + .word BRAKE1_IRQHandler // 28: + .word EPWM1P0_IRQHandler // 29: + .word EPWM1P1_IRQHandler // 30: + .word EPWM1P2_IRQHandler // 31: + .word TMR0_IRQHandler // 32: Timer 0 + .word TMR1_IRQHandler // 33: Timer 1 + .word TMR2_IRQHandler // 34: Timer 2 + .word TMR3_IRQHandler // 35: Timer 3 + .word UART0_IRQHandler // 36: UART0 + .word UART1_IRQHandler // 37: UART1 + .word I2C0_IRQHandler // 38: I2C0 + .word I2C1_IRQHandler // 39: I2C1 + .word PDMA_IRQHandler // 40: Peripheral DMA + .word DAC_IRQHandler // 41: DAC + .word ADC00_IRQHandler // 42: ADC0 interrupt source 0 + .word ADC01_IRQHandler // 43: ADC0 interrupt source 1 + .word ACMP01_IRQHandler // 44: ACMP0 and ACMP1 + .word Default_Handler // 45: Reserved + .word ADC02_IRQHandler // 46: ADC0 interrupt source 2 + .word ADC03_IRQHandler // 47: ADC0 interrupt source 3 + .word UART2_IRQHandler // 48: UART2 + .word UART3_IRQHandler // 49: UART3 + .word Default_Handler // 50: Reserved + .word SPI1_IRQHandler // 51: SPI1 + .word SPI2_IRQHandler // 52: SPI2 + .word USBD_IRQHandler // 53: USB device + .word OHCI_IRQHandler // 54: OHCI + .word USBOTG_IRQHandler // 55: USB OTG + .word CAN0_IRQHandler // 56: CAN0 + .word CAN1_IRQHandler // 57: CAN1 + .word SC0_IRQHandler // 58: + .word SC1_IRQHandler // 59: + .word SC2_IRQHandler // 60: + .word Default_Handler // 61: + .word SPI3_IRQHandler // 62: SPI3 + .word Default_Handler // 63: + .word SDH0_IRQHandler // 64: SDH0 + .word USBD20_IRQHandler // 65: USBD20 + .word EMAC_TX_IRQHandler // 66: EMAC_TX + .word EMAC_RX_IRQHandler // 67: EMAX_RX + .word I2S0_IRQHandler // 68: I2S0 + .word Default_Handler // 69: ToDo: Add description to this Interrupt + .word OPA0_IRQHandler // 70: OPA0 + .word CRYPTO_IRQHandler // 71: CRYPTO + .word GPG_IRQHandler // 72: + .word EINT6_IRQHandler // 73: + .word UART4_IRQHandler // 74: UART4 + .word UART5_IRQHandler // 75: UART5 + .word USCI0_IRQHandler // 76: USCI0 + .word USCI1_IRQHandler // 77: USCI1 + .word BPWM0_IRQHandler // 78: BPWM0 + .word BPWM1_IRQHandler // 79: BPWM1 + .word SPIM_IRQHandler // 80: SPIM + .word Default_Handler // 81: ToDo: Add description to this Interrupt + .word I2C2_IRQHandler // 82: I2C2 + .word Default_Handler // 83: + .word QEI0_IRQHandler // 84: QEI0 + .word QEI1_IRQHandler // 85: QEI1 + .word ECAP0_IRQHandler // 86: ECAP0 + .word ECAP1_IRQHandler // 87: ECAP1 + .word GPH_IRQHandler // 88: + .word EINT7_IRQHandler // 89: + .word SDH1_IRQHandler // 90: SDH1 + .word Default_Handler // 91: + .word EHCI_IRQHandler // 92: EHCI + .word USBOTG20_IRQHandler // 93: + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler BOD_IRQHandler + def_irq_handler IRC_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler RAMPE_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler EINT4_IRQHandler + def_irq_handler EINT5_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler QSPI0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler DAC_IRQHandler + def_irq_handler ADC00_IRQHandler + def_irq_handler ADC01_IRQHandler + def_irq_handler ACMP01_IRQHandler + def_irq_handler ADC02_IRQHandler + def_irq_handler ADC03_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler OHCI_IRQHandler + def_irq_handler USBOTG_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler SC2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler SDH0_IRQHandler + def_irq_handler USBD20_IRQHandler + def_irq_handler EMAC_TX_IRQHandler + def_irq_handler EMAC_RX_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler OPA0_IRQHandler + def_irq_handler CRYPTO_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler EINT6_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler USCI0_IRQHandler + def_irq_handler USCI1_IRQHandler + def_irq_handler BPWM0_IRQHandler + def_irq_handler BPWM1_IRQHandler + def_irq_handler SPIM_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler EINT7_IRQHandler + def_irq_handler SDH1_IRQHandler + def_irq_handler EHCI_IRQHandler + def_irq_handler USBOTG20_IRQHandler diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup_M480.S b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup_M480.S new file mode 100644 index 0000000000..ee59ad3784 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup_M480.S @@ -0,0 +1,449 @@ +/****************************************************************************//** + * @file startup_M480.S + * @version V1.00 + * @brief CMSIS Cortex-M4 Core Device Startup File for M480 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + + + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000800 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000100 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long BOD_IRQHandler /* 0: BOD */ + .long IRC_IRQHandler /* 1: IRC */ + .long PWRWU_IRQHandler /* 2: PWRWU */ + .long RAMPE_IRQHandler /* 3: RAMPE */ + .long CKFAIL_IRQHandler /* 4: CKFAIL */ + .long 0 /* 5: Reserved */ + .long RTC_IRQHandler /* 6: RTC */ + .long TAMPER_IRQHandler /* 7: TAMPER */ + .long WDT_IRQHandler /* 8: WDT */ + .long WWDT_IRQHandler /* 9: WWDT */ + .long EINT0_IRQHandler /* 10: EINT0 */ + .long EINT1_IRQHandler /* 11: EINT1 */ + .long EINT2_IRQHandler /* 12: EINT2 */ + .long EINT3_IRQHandler /* 13: EINT3 */ + .long EINT4_IRQHandler /* 14: EINT4 */ + .long EINT5_IRQHandler /* 15: EINT5 */ + .long GPA_IRQHandler /* 16: GPA */ + .long GPB_IRQHandler /* 17: GPB */ + .long GPC_IRQHandler /* 18: GPC */ + .long GPD_IRQHandler /* 19: GPD */ + .long GPE_IRQHandler /* 20: GPE */ + .long GPF_IRQHandler /* 21: GPF */ + .long QSPI0_IRQHandler /* 22: QSPI0 */ + .long SPI0_IRQHandler /* 23: SPI0 */ + .long BRAKE0_IRQHandler /* 24: BRAKE0 */ + .long EPWM0P0_IRQHandler /* 25: EPWM0P0 */ + .long EPWM0P1_IRQHandler /* 26: EPWM0P1 */ + .long EPWM0P2_IRQHandler /* 27: EPWM0P2 */ + .long BRAKE1_IRQHandler /* 28: BRAKE1 */ + .long EPWM1P0_IRQHandler /* 29: EPWM1P0 */ + .long EPWM1P1_IRQHandler /* 30: EPWM1P1 */ + .long EPWM1P2_IRQHandler /* 31: EPWM1P2 */ + .long TMR0_IRQHandler /* 32: TIMER0 */ + .long TMR1_IRQHandler /* 33: TIMER1 */ + .long TMR2_IRQHandler /* 34: TIMER2 */ + .long TMR3_IRQHandler /* 35: TIMER3 */ + .long UART0_IRQHandler /* 36: UART0 */ + .long UART1_IRQHandler /* 37: UART1 */ + .long I2C0_IRQHandler /* 38: I2C0 */ + .long I2C1_IRQHandler /* 39: I2C1 */ + .long PDMA_IRQHandler /* 40: PDMA */ + .long DAC_IRQHandler /* 41: DAC */ + .long ADC00_IRQHandler /* 42: ADC00 */ + .long ADC01_IRQHandler /* 43: ADC01 */ + .long ACMP01_IRQHandler /* 44: ACMP */ + .long 0 /* 45: Reserved */ + .long ADC02_IRQHandler /* 46: ADC02 */ + .long ADC03_IRQHandler /* 47: ADC03 */ + .long UART2_IRQHandler /* 48: UART2 */ + .long UART3_IRQHandler /* 49: UART3 */ + .long 0 /* 50: Reserved */ + .long SPI1_IRQHandler /* 51: SPI1 */ + .long SPI2_IRQHandler /* 52: SPI2 */ + .long USBD_IRQHandler /* 53: USBD */ + .long OHCI_IRQHandler /* 54: OHCI */ + .long USBOTG_IRQHandler /* 55: OTG */ + .long CAN0_IRQHandler /* 56: CAN0 */ + .long CAN1_IRQHandler /* 57: CAN1 */ + .long SC0_IRQHandler /* 58: SC0 */ + .long SC1_IRQHandler /* 59: SC1 */ + .long SC2_IRQHandler /* 60: SC2 */ + .long 0 /* 61: Reserved */ + .long SPI3_IRQHandler /* 62: SPI3 */ + .long 0 /* 63: Reserved */ + .long SDH0_IRQHandler /* 64: SDH0 */ + .long USBD20_IRQHandler /* 65: HSUSBD */ + .long EMAC_TX_IRQHandler /* 66: EMAC_TX */ + .long EMAC_RX_IRQHandler /* 67: EMAC_RX */ + .long I2S0_IRQHandler /* 68: I2S */ + .long 0 /* 69: Reserved */ + .long OPA0_IRQHandler /* 70: OPA */ + .long CRYPTO_IRQHandler /* 71: CRYPTO */ + .long GPG_IRQHandler /* 72: GPG */ + .long EINT6_IRQHandler /* 73: EINT6 */ + .long UART4_IRQHandler /* 74: UART4 */ + .long UART5_IRQHandler /* 75: UART5 */ + .long USCI0_IRQHandler /* 76: USCI0 */ + .long USCI1_IRQHandler /* 77: USCI1 */ + .long BPWM0_IRQHandler /* 78: BPWM0 */ + .long BPWM1_IRQHandler /* 79: BPWM1 */ + .long SPIM_IRQHandler /* 80: SPIM */ + .long 0 /* 81: Reserved */ + .long I2C2_IRQHandler /* 82: I2C2 */ + .long 0 /* 83: Reserved */ + .long QEI0_IRQHandler /* 84: QEI0 */ + .long QEI1_IRQHandler /* 85: QEI1 */ + .long ECAP0_IRQHandler /* 86: ECAP0 */ + .long ECAP1_IRQHandler /* 87: ECAP1 */ + .long GPH_IRQHandler /* 88: GPH */ + .long EINT7_IRQHandler /* 89: EINT7 */ + .long SDH1_IRQHandler /* 90: SDH1 */ + .long 0 /* 91: Reserved */ + .long EHCI_IRQHandler /* 92: EHCI */ + .long USBOTG20_IRQHandler /* 93: HSOTG */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +/* Unlock Register */ + ldr r0, =0x40000100 + ldr r1, =0x59 + str r1, [r0] + ldr r1, =0x16 + str r1, [r0] + ldr r1, =0x88 + str r1, [r0] + +#ifndef ENABLE_SPIM_CACHE + ldr r0, =0x40000200 /* R0 = Clock Controller Register Base Address */ + ldr r1, [r0,#0x4] /* R1 = 0x40000204 (AHBCLK) */ + orr r1, r1, #0x4000 + str r1, [r0,#0x4] /* CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; */ + + ldr r0, =0x40007000 /* R0 = SPIM Register Base Address */ + ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */ + orr r1, r1,#2 /* R1 |= SPIM_CTL1_CACHEOFF_Msk */ + str r1, [r0,#4] /* _SPIM_DISABLE_CACHE() */ + ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */ + orr r1, r1, #4 /* R1 |= SPIM_CTL1_CCMEN_Msk */ + str r1, [r0,#4] /* _SPIM_ENABLE_CCM() */ +#endif + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +/* Init POR */ +#if 0 + ldr r0, =0x40000024 + ldr r1, =0x00005AA5 + str r1, [r0] +#endif + +/* Lock register */ + ldr r0, =0x40000100 + ldr r1, =0 + str r1, [r0] + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler BOD_IRQHandler + def_irq_handler IRC_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler RAMPE_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler EINT4_IRQHandler + def_irq_handler EINT5_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler QSPI0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler DAC_IRQHandler + def_irq_handler ADC00_IRQHandler + def_irq_handler ADC01_IRQHandler + def_irq_handler ACMP01_IRQHandler + def_irq_handler ADC02_IRQHandler + def_irq_handler ADC03_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler OHCI_IRQHandler + def_irq_handler USBOTG_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler SC2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler SDH0_IRQHandler + def_irq_handler USBD20_IRQHandler + def_irq_handler EMAC_TX_IRQHandler + def_irq_handler EMAC_RX_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler OPA0_IRQHandler + def_irq_handler CRYPTO_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler EINT6_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler USCI0_IRQHandler + def_irq_handler USCI1_IRQHandler + def_irq_handler BPWM0_IRQHandler + def_irq_handler BPWM1_IRQHandler + def_irq_handler SPIM_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler EINT7_IRQHandler + def_irq_handler SDH1_IRQHandler + def_irq_handler EHCI_IRQHandler + def_irq_handler USBOTG20_IRQHandler + + .end diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/IAR/startup_M480.s b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/IAR/startup_M480.s new file mode 100644 index 0000000000..42ae7c2214 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/IAR/startup_M480.s @@ -0,0 +1,416 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN HardFault_Handler + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD PWM0P0_IRQHandler ; 25: + DCD PWM0P1_IRQHandler ; 26: + DCD PWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD PWM1P0_IRQHandler ; 29: + DCD PWM1P1_IRQHandler ; 30: + DCD PWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0 + DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2 + DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD Default_Handler ; 50: Reserved + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD Default_Handler ; 81: ToDo: Add description to this Interrupt + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + #ifndef ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + #endif + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock register + LDR R0, =0x40000100 + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK BOD_IRQHandler + PUBWEAK IRC_IRQHandler + PUBWEAK PWRWU_IRQHandler + PUBWEAK RAMPE_IRQHandler + PUBWEAK CKFAIL_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK TAMPER_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK WWDT_IRQHandler + PUBWEAK EINT0_IRQHandler + PUBWEAK EINT1_IRQHandler + PUBWEAK EINT2_IRQHandler + PUBWEAK EINT3_IRQHandler + PUBWEAK EINT4_IRQHandler + PUBWEAK EINT5_IRQHandler + PUBWEAK GPA_IRQHandler + PUBWEAK GPB_IRQHandler + PUBWEAK GPC_IRQHandler + PUBWEAK GPD_IRQHandler + PUBWEAK GPE_IRQHandler + PUBWEAK GPF_IRQHandler + PUBWEAK QSPI0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK BRAKE0_IRQHandler + PUBWEAK PWM0P0_IRQHandler + PUBWEAK PWM0P1_IRQHandler + PUBWEAK PWM0P2_IRQHandler + PUBWEAK BRAKE1_IRQHandler + PUBWEAK PWM1P0_IRQHandler + PUBWEAK PWM1P1_IRQHandler + PUBWEAK PWM1P2_IRQHandler + PUBWEAK TMR0_IRQHandler + PUBWEAK TMR1_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK PDMA_IRQHandler + PUBWEAK DAC_IRQHandler + PUBWEAK ADC00_IRQHandler + PUBWEAK ADC01_IRQHandler + PUBWEAK ACMP01_IRQHandler + PUBWEAK ADC02_IRQHandler + PUBWEAK ADC03_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK USBD_IRQHandler + PUBWEAK OHCI_IRQHandler + PUBWEAK USBOTG_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + PUBWEAK SC0_IRQHandler + PUBWEAK SC1_IRQHandler + PUBWEAK SC2_IRQHandler + PUBWEAK SPI3_IRQHandler + PUBWEAK SDH0_IRQHandler + PUBWEAK USBD20_IRQHandler + PUBWEAK EMAC_TX_IRQHandler + PUBWEAK EMAC_RX_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK OPA0_IRQHandler + PUBWEAK CRYPTO_IRQHandler + PUBWEAK GPG_IRQHandler + PUBWEAK EINT6_IRQHandler + PUBWEAK UART4_IRQHandler + PUBWEAK UART5_IRQHandler + PUBWEAK USCI0_IRQHandler + PUBWEAK USCI1_IRQHandler + PUBWEAK BPWM0_IRQHandler + PUBWEAK BPWM1_IRQHandler + PUBWEAK SPIM_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK QEI0_IRQHandler + PUBWEAK QEI1_IRQHandler + PUBWEAK ECAP0_IRQHandler + PUBWEAK ECAP1_IRQHandler + PUBWEAK GPH_IRQHandler + PUBWEAK EINT7_IRQHandler + PUBWEAK SDH1_IRQHandler + PUBWEAK EHCI_IRQHandler + PUBWEAK USBOTG20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) + +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +PWM0P0_IRQHandler +PWM0P1_IRQHandler +PWM0P2_IRQHandler +BRAKE1_IRQHandler +PWM1P0_IRQHandler +PWM1P1_IRQHandler +PWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +ADC00_IRQHandler +ADC01_IRQHandler +ACMP01_IRQHandler +ADC02_IRQHandler +ADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler +Default_Handler + B Default_Handler + + + + + END +;/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/system_M480.c b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/system_M480.c new file mode 100644 index 0000000000..cad72aca2d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/system_M480.c @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file system_M480.c + * @version V1.000 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480 + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ +uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC}; + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t u32Freq, u32ClkSrc; + uint32_t u32HclkDiv; + + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) + { + /* Use PLL clock */ + u32Freq = PllClock; + } + else + { + /* Use the clock sources directly */ + u32Freq = gau32ClkSrcTbl[u32ClkSrc]; + } + + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + + //if(SystemCoreClock == 0) + // __BKPT(0); + + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; +} + +/** + * @brief Set PF.2 and PF.3 to input mode + * @param None + * @return None + * @details GPIO default state could be configured as input or quasi through user config. + * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes + * PF.2 and PF.3 to input mode no matter which mode they are working at. + */ +static __INLINE void HXTInit(void) +{ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + +} + +/** + * @brief Initialize the System + * + * @param none + * @return none + */ +void SystemInit (void) +{ + /* Add your system initialize code here. + Do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + + /* Set access cycle for CPU @ 192MHz */ + FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos); + /* Configure power down bias, must set 1 before entering power down mode. + So set it at the very beginning */ + CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk; + /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */ + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk | + RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk); + RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk | + RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk); + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; + HXTInit(); + +} +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/SConscript b/bsp/nuvoton_m487/libraries/Device/SConscript new file mode 100644 index 0000000000..30f12589f7 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/SConscript @@ -0,0 +1,25 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +Nuvoton/M480/Source/system_M480.c +""") + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['Nuvoton/M480/Source/GCC/startup.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['Nuvoton/M480/Source/ARM/startup_M480.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['Nuvoton/M480/Source/IAR/startup_M480.s'] + +path = [cwd + '/Nuvoton/M480/Include',] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton_m487/libraries/SConscript b/bsp/nuvoton_m487/libraries/SConscript new file mode 100644 index 0000000000..4c815c49b8 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton_m487/libraries/StdDriver/SConscript b/bsp/nuvoton_m487/libraries/StdDriver/SConscript new file mode 100644 index 0000000000..97f035b6a1 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*src/*.c') + Glob('src/*.cpp') +CPPPATH = [cwd + '/inc'] + +group = DefineGroup('M487_StdPeriph', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/acmp.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/acmp.h new file mode 100644 index 0000000000..1a1d577c22 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/acmp.h @@ -0,0 +1,414 @@ +/**************************************************************************//** + * @file ACMP.h + * @version V1.00 + * @brief M480 Series ACMP Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_VDDA (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage \hideinitializer */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */ + + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + * \hideinitializer + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + * \hideinitializer + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + * \hideinitializer + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * \hideinitializer + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function. + * \hideinitializer + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * \hideinitializer + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + * \hideinitializer + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + * \hideinitializer + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + * \hideinitializer + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + * \hideinitializer + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + * \hideinitializer + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + * \hideinitializer + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + * \hideinitializer + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + * \hideinitializer + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + * \hideinitializer + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + * \hideinitializer + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + * \hideinitializer + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __ACMP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/bpwm.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/bpwm.h new file mode 100644 index 0000000000..c5ba58ab41 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/bpwm.h @@ -0,0 +1,360 @@ +/**************************************************************************//** + * @file bpwm.h + * @version V1.00 + * @brief M480 series PWM driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_H__ +#define __BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6) /*!< BPWM channel number \hideinitializer */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BPWM_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/can.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/can.h new file mode 100644 index 0000000000..3b89821258 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/can.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file can.h + * @version V2.00 + * @brief M480 Series CAN Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CAN_H__ +#define __CAN_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CAN Test Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_NORMAL_MODE 0ul /*!< CAN select normal mode \hideinitializer */ +#define CAN_BASIC_MODE 1ul /*!< CAN select basic mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message ID Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_STD_ID 0ul /*!< CAN select standard ID \hideinitializer */ +#define CAN_EXT_ID 1ul /*!< CAN select extended ID \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message Frame Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_REMOTE_FRAME 0ul /*!< CAN frame select remote frame \hideinitializer */ +#define CAN_DATA_FRAME 1ul /*!< CAN frame select data frame \hideinitializer */ + +/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */ + + +/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs + @{ +*/ +/** + * @details CAN message structure + */ +typedef struct +{ + uint32_t IdType; /*!< ID type */ + uint32_t FrameType; /*!< Frame type */ + uint32_t Id; /*!< Message ID */ + uint8_t DLC; /*!< Data length */ + uint8_t Data[8]; /*!< Data */ +} STR_CANMSG_T; + +/** + * @details CAN mask message structure + */ +typedef struct +{ + uint8_t u8Xtd; /*!< Extended ID */ + uint8_t u8Dir; /*!< Direction */ + uint32_t u32Id; /*!< Message ID */ + uint8_t u8IdType; /*!< ID type*/ +} STR_CANMASK_T; + +/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */ + +/** @cond HIDDEN_SYMBOLS */ +#define MSG(id) (id) +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** + * @brief Get interrupt status. + * + * @param[in] can The base address of can module. + * + * @return CAN module status register value. + * + * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]), + * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]). + * \hideinitializer + */ +#define CAN_GET_INT_STATUS(can) ((can)->STATUS) + +/** + * @brief Get specified interrupt pending status. + * + * @param[in] can The base address of can module. + * + * @return The source of the interrupt. + * + * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt + * with the highest priority, disregarding their chronological order. + * \hideinitializer + */ +#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR) + +/** + * @brief Disable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details The macro is used to disable wake-up function. + * \hideinitializer + */ +#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul) + +/** + * @brief Enable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details User can wake-up system when there is a falling edge in the CAN_Rx pin. + * \hideinitializer + */ +#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk) + +/** + * @brief Get specified Message Object new data into bit value. + * + * @param[in] can The base address of can module. + * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31. + * + * @return Specified Message Object new data into bit value. + * + * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers + * or by the Message Handler after reception of a Data Frame or after a successful transmission. + * \hideinitializer + */ +#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define CAN functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate); +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode); +void CAN_Close(CAN_T *tCAN); +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum); +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask); +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask); +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask); +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum); +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask); +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask); +void CAN_LeaveTestMode(CAN_T *tCAN); +uint32_t CAN_GetCANBitRate(CAN_T *tCAN); +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj); +void CAN_LeaveInitMode(CAN_T *tCAN); +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast); +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast); +void CAN_WaitMsg(CAN_T *tCAN); +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg); + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__CAN_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/clk.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/clk.h new file mode 100644 index 0000000000..2f57f55f5d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/clk.h @@ -0,0 +1,614 @@ +/**************************************************************************//** + * @file CLK.h + * @version V1.0 + * @brief M480 Series CLK Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */ +#define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */ +#define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */ +#define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */ +#define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */ +#define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */ +#define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */ +#define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */ +#define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */ +#define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */ +#define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. (Write-protection) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */ + +#if(0) +#define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */ + +#define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */ +#endif + +#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */ + +#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL2 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV4 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PCLKDIV constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#if(1) +#define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */ +#endif +/*---------------------------------------------------------------------------------------------------------*/ +/* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */ +#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */ + +#define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */ +#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */ + +#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */ +#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */ +#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */ + +#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ + +#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* MODULE constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */ + +#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */ +#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */ + +#define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */ +#define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */ +#define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */ +#define USBH_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< USBH Module \hideinitializer */ +#define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */ +#define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */ +#define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */ +#define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */ +#define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */ +#define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */ +#define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */ +#define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */ +#define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */ +#define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */ +#define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */ +#define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */ +#define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */ +#define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */ +#define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */ +#define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */ +#define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */ +#define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */ +#define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */ +#define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QSPI0 Module \hideinitializer */ +#define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI0 Module \hideinitializer */ +#define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI1 Module \hideinitializer */ +#define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI2 Module \hideinitializer */ +#define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */ +#define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */ +#define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */ +#define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */ +#define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */ +#define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */ +#define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */ +#define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */ +#define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */ +#define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< USBD Module \hideinitializer */ +#define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */ +#define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< I2S0 Module \hideinitializer */ +#define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */ +#define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */ +#define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */ +#define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */ +#define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI3 Module \hideinitializer */ +#define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */ +#define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */ +#define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */ +#define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */ +#define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */ +#define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */ +#define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */ +#define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */ +#define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */ +#define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */ +#define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */ +#define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */ + +#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_128 + * - \ref CLK_PMUCTL_WKTMRIS_256 + * - \ref CLK_PMUCTL_WKTMRIS_512 + * - \ref CLK_PMUCTL_WKTMRIS_1024 + * - \ref CLK_PMUCTL_WKTMRIS_4096 + * - \ref CLK_PMUCTL_WKTMRIS_8192 + * - \ref CLK_PMUCTL_WKTMRIS_16384 + * - \ref CLK_PMUCTL_WKTMRIS_65536 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * \hideinitializer + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set Set De-bounce Sampling Cycle Time. + * + * \hideinitializer + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 72MHz => 233016us, 50MHz => 335544us, + * 48MHz => 349525us, 28MHz => 699050us ... + * @return None + * @details Use the SysTick to generate the delay time and the unit is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = 0x0UL; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t delay; + + /* It should <= 349525us for each delay loop */ + delay = 349525UL; + + do + { + if(us > delay) + { + us -= delay; + } + else + { + delay = us; + us = 0UL; + } + + SysTick->LOAD = delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while(us > 0UL); + +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLK_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/crc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/crc.h new file mode 100644 index 0000000000..c981f9108c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/crc.h @@ -0,0 +1,112 @@ +/**************************************************************************//** + * @file crc.h + * @version V1.00 + * @brief M480 series CRC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0) + +/** + * @brief Get CRC Seed Value + * + * @param None + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED() (CRC->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data)) + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/crypto.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/crypto.h new file mode 100644 index 0000000000..da8d9e8803 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/crypto.h @@ -0,0 +1,377 @@ +/**************************************************************************//** + * @file crypto.h + * @version V1.10 + * @brief Cryptographic Accelerator driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + +#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */ + +#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */ + +#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + +typedef enum +{ + /*!< ECC curve \hideinitializer */ + CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */ + CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */ + CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */ + CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */ + CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */ + CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */ + CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */ + CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */ + CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */ + CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */ + CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */ + CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */ + CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */ + CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */ + CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_UNDEF, /*!< Invalid curve \hideinitializer */ +} +E_ECC_CURVE; /*!< ECC curve \hideinitializer */ + + +/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup M480_CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified cripto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified cripto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified cripto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified cripto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified cripto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + + +/*@}*/ /* end of group M480_CRYPTO_EXPORTED_MACROS */ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType); +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]); +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL); +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_Complete(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRYPTO_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/dac.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/dac.h new file mode 100644 index 0000000000..e73cbd193f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/dac.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file dac.h + * @version V1.00 + * @brief M480 series DAC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac Base address of DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac Base address of DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac Base address of DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + * \hideinitializer + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + * \hideinitializer + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac Base address of DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + * \hideinitializer + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable DMA mode. + * \hideinitializer + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * \hideinitializer + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + * \hideinitializer + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + * \hideinitializer + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac Base address of DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + * \hideinitializer + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac Base address of DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + * \hideinitializer + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/eadc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/eadc.h new file mode 100644 index 0000000000..725e6c7bad --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/eadc.h @@ -0,0 +1,590 @@ +/**************************************************************************//** + * @file eadc.h + * @version V0.10 + * @brief M480 series EADC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EADC_H__ +#define __EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * \hideinitializer + */ +#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + * \hideinitializer + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + * \hideinitializer + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + * \hideinitializer + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + * \hideinitializer + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + * \hideinitializer + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + * \hideinitializer + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + * \hideinitializer + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + * \hideinitializer + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * \hideinitializer + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + * \hideinitializer + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + * \hideinitializer + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + * \hideinitializer + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + * \hideinitializer + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + * \hideinitializer + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + * \hideinitializer + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + * \hideinitializer + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * \hideinitializer + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + * \hideinitializer + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + * \hideinitializer + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + * \hideinitializer + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + * \hideinitializer + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + * \hideinitializer + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EADC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/ebi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/ebi.h new file mode 100644 index 0000000000..830a6888d6 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/ebi.h @@ -0,0 +1,351 @@ +/**************************************************************************//** + * @file ebi.h + * @version V3.00 + * @brief M480 series External Bus Interface(EBI) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/ecap.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/ecap.h new file mode 100644 index 0000000000..0c029abd55 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/ecap.h @@ -0,0 +1,457 @@ +/**************************************************************************//** + * @file ecap.h + * @version V3.00 + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ECAP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/emac.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/emac.h new file mode 100644 index 0000000000..ca279a8d6b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/emac.h @@ -0,0 +1,184 @@ +/**************************************************************************//** + * @file emac.h + * @version V1.00 + * @brief M480 EMAC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EMAC_H__ +#define __EMAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EMAC_Driver EMAC Driver + @{ +*/ + +/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants + @{ +*/ + +#define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */ +#define EMAC_RX_DESC_SIZE 4UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */ +#define EMAC_TX_DESC_SIZE 4UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */ + +#define EMAC_LINK_DOWN 0UL /*!< Ethernet link is down \hideinitializer */ +#define EMAC_LINK_100F 1UL /*!< Ethernet link is 100Mbps full duplex \hideinitializer */ +#define EMAC_LINK_100H 2UL /*!< Ethernet link is 100Mbps half duplex \hideinitializer */ +#define EMAC_LINK_10F 3UL /*!< Ethernet link is 10Mbps full duplex \hideinitializer */ +#define EMAC_LINK_10H 4UL /*!< Ethernet link is 10Mbps half duplex \hideinitializer */ + +/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ + + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Enable EMAC Tx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk) + + +/** + * @brief Enable EMAC Rx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0) + +/** + * @brief Disable EMAC Tx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk) + + +/** + * @brief Disable EMAC Rx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk) + +/** + * @brief Enable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk) + +/** + * @brief Disable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk) + +/** + * @brief Enable EMAC to receive broadcast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk) + +/** + * @brief Disable EMAC to receive broadcast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk) + +/** + * @brief Enable EMAC to receive multicast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk) + +/** + * @brief Disable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk) + +/** + * @brief Check if EMAC time stamp alarm interrupt occurred or not + * @param None + * @return If time stamp alarm interrupt occurred or not + * @retval 0 Alarm interrupt does not occur + * @retval 1 Alarm interrupt occurred + * \hideinitializer + */ +#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0) + +/** + * @brief Clear EMAC time stamp alarm interrupt flag + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk) + + +void EMAC_Open(uint8_t *pu8MacAddr); +void EMAC_Close(void); +void EMAC_SetMacAddr(uint8_t *pu8MacAddr); +void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]); +void EMAC_DisableCamEntry(uint32_t u32Entry); + +uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size); +uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec); +void EMAC_RecvPktDone(void); + +uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size); +uint32_t EMAC_SendPktDone(void); +uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec); + +void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_DisableTS(void); +void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec); +void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_DisableAlarm(void); + +uint32_t EMAC_CheckLinkStatus(void); + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EMAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EMAC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/epwm.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/epwm.h new file mode 100644 index 0000000000..1235f21e2d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/epwm.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file epwm.h + * @version V3.00 + * @brief M480 series EPWM driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_H__ +#define __EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ +#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ +#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ +#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ +#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ +#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ +#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ +#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0U<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + { \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EPWM_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/fmc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/fmc.h new file mode 100644 index 0000000000..2b2a083281 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/fmc.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file fmc.h + * @version V1.00 + * @brief M480 Series Flash Memory Controller Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */ +#define FMC_APROM_END 0x00080000UL /*!< APROM end address \hideinitializer */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address \hideinitializer */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM base address \hideinitializer */ +#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address \hideinitializer */ +#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM base address \hideinitializer */ +#define FMC_SPROM_END 0x00201000UL /*!< SPROM end address \hideinitializer */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration address \hideinitializer */ +#define FMC_USER_CONFIG_0 0x00300000UL /*!< User Config 0 address \hideinitializer */ +#define FMC_USER_CONFIG_1 0x00300004UL /*!< User Config 1 address \hideinitializer */ +#define FMC_USER_CONFIG_2 0x00300008UL /*!< User Config 2 address \hideinitializer */ +#define FMC_KPROM_BASE 0x00301000UL /*!< Security ROM base address \hideinitializer */ +#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address \hideinitializer */ + +#define FMC_FLASH_PAGE_SIZE 0x1000UL /*!< Flash Page Size (4K bytes) \hideinitializer */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF000UL /*!< Flash page address mask \hideinitializer */ +#define FMC_MULTI_WORD_PROG_LEN 512 /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size \hideinitializer */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size \hideinitializer */ +#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) \hideinitializer */ +#define FMC_SPROM_SIZE 0x1000UL /*!< SPROM Size (4 Kbytes) \hideinitializer */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Multuple word program \hideinitializer */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: Read double flash word \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: Write double flash word \hideinitializer */ + +#define IS_BOOT_FROM_APROM 0UL /*!< Is booting from APROM \hideinitializer */ +#define IS_BOOT_FROM_LDROM 1UL /*!< Is booting from LDROM \hideinitializer */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */ + + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FMC_EXPORTED_MACROS FMC Exported Macros + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macros */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */ +#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update \hideinitializer */ +#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update \hideinitializer */ +#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */ +#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */ + +/*@}*/ /* end of group FMC_EXPORTED_MACROS */ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); + +/** + * @brief Get current vector mapping address. + * @param None + * @return The current vector mapping address. + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * @param None + * @return The company ID (32-bit) + * @details The company ID of Nuvoton is fixed to be 0xDA + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * @param None + * @return The product ID (32-bit) + * @details This function is used to read product ID. + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read Unique ID + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * @return The 32-bit unique ID data of specified UID index. + * @details To read out 96-bit Unique ID. + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADDR = ((uint32_t)u8Index << 2u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * @return The UCID of specified index + * @details This function is used to read unique chip ID (UCID). + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Set vector mapping address + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * @return To set VECMAP to remap specified page address to 0x0. + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern void FMC_Close(void); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_Erase_SPROM(void); +extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr); +extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr); +extern int32_t FMC_GetBootSource(void); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern uint32_t FMC_ReadDataFlashBaseAddr(void); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_Lock_OTP(uint32_t otp_num); +extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM); +extern int32_t FMC_CompareSPKey(uint32_t key[3]); + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/gpio.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/gpio.h new file mode 100644 index 0000000000..3caff2064e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/gpio.h @@ -0,0 +1,496 @@ +/**************************************************************************//** + * @file GPIO.h + * @version V3.00 + * @brief M480 series GPIO driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */ +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */ +#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */ +#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */ +#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */ +#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */ +#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */ +#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */ +#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */ +#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */ +#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */ +#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */ +#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */ +#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */ +#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */ +#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */ +#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */ +#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */ +#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */ +#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */ +#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */ +#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */ +#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */ +#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */ +#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */ +#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */ +#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */ +#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */ +#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ + + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 00 us. + * \hideinitializer + */ +#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * +* @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + * \hideinitializer + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + * \hideinitializer + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + * \hideinitializer + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ + +/*** (C) COPYRIGHT 2013~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/hsotg.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsotg.h new file mode 100644 index 0000000000..b73ad24cfd --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsotg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file hsotg.h + * @version V0.10 + * @brief M480 Series HSOTG Driver Header File + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __HSOTG_H__ +#define __HSOTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSOTG_Driver HSOTG Driver + @{ +*/ + + +/** @addtogroup HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* HSOTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define HSOTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define HSOTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group HSOTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable HSOTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function. + * \hideinitializer + */ +#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable HSOTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function. + * \hideinitializer + */ +#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable HSOTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable HSOTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref HSOTG_VBUS_EN_ACTIVE_HIGH + * - \ref HSOTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable HSOTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTEN_ROLECHGIEN_Msk + * - \ref HSOTG_INTEN_VBEIEN_Msk + * - \ref HSOTG_INTEN_SRPFIEN_Msk + * - \ref HSOTG_INTEN_HNPFIEN_Msk + * - \ref HSOTG_INTEN_GOIDLEIEN_Msk + * - \ref HSOTG_INTEN_IDCHGIEN_Msk + * - \ref HSOTG_INTEN_PDEVIEN_Msk + * - \ref HSOTG_INTEN_HOSTIEN_Msk + * - \ref HSOTG_INTEN_BVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_AVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_VBCHGIEN_Msk + * - \ref HSOTG_INTEN_SECHGIEN_Msk + * - \ref HSOTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable HSOTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get HSOTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref HSOTG_STATUS_OVERCUR_Msk + * - \ref HSOTG_STATUS_IDSTS_Msk + * - \ref HSOTG_STATUS_SESSEND_Msk + * - \ref HSOTG_STATUS_BVLD_Msk + * - \ref HSOTG_STATUS_AVLD_Msk + * - \ref HSOTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return HSOTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group HSOTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSOTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __HSOTG_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/hsusbd.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsusbd.h new file mode 100644 index 0000000000..f09cf9ad1b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsusbd.h @@ -0,0 +1,382 @@ +/**************************************************************************//** + * @file hsusbd.h + * @version V1.00 + * @brief M480 HSUSBD driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_H__ +#define __HSUSBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + +/** @addtogroup HSUSBD_EXPORTED_CONSTANTS HSUSBD Exported Constants + @{ +*/ +/** @cond HIDDEN_SYMBOLS */ +#define HSUSBD_MAX_EP 12ul + +#define Maximum(a,b) (a)>(b) ? (a) : (b) +#define Minimum(a,b) (((a)<(b)) ? (a) : (b)) + + +#define CEP 0xfful /*!< Control Endpoint \hideinitializer */ +#define EPA 0ul /*!< Endpoint A \hideinitializer */ +#define EPB 1ul /*!< Endpoint B \hideinitializer */ +#define EPC 2ul /*!< Endpoint C \hideinitializer */ +#define EPD 3ul /*!< Endpoint D \hideinitializer */ +#define EPE 4ul /*!< Endpoint E \hideinitializer */ +#define EPF 5ul /*!< Endpoint F \hideinitializer */ +#define EPG 6ul /*!< Endpoint G \hideinitializer */ +#define EPH 7ul /*!< Endpoint H \hideinitializer */ +#define EPI 8ul /*!< Endpoint I \hideinitializer */ +#define EPJ 9ul /*!< Endpoint J \hideinitializer */ +#define EPK 10ul /*!< Endpoint K \hideinitializer */ +#define EPL 11ul /*!< Endpoint L \hideinitializer */ + +/** @endcond HIDDEN_SYMBOLS */ +/********************* Bit definition of CEPCTL register **********************/ +#define HSUSBD_CEPCTL_NAKCLR ((uint32_t)0x00000000ul) /*!PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk))) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk)) /*!FADDR = (addr)) /*!FADDR)) /*!GINTEN = (intr)) /*!BUSINTEN = (intr)) /*!BUSINTSTS) /*!BUSINTSTS = (flag)) /*!CEPINTEN = (intr)) /*!CEPINTSTS = (flag)) /*!CEPCTL = (flag)) /*!CEPTXCNT = (size)) /*!EP[(ep)].EPMPS = (size)) /*!EP[(ep)].EPINTEN = (intr)) /*!EP[(ep)].EPINTSTS) /*!EP[(ep)].EPINTSTS = (flag)) /*!DMACNT = (len)) /*!DMAADDR = (addr)) /*!DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100) /*!DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum)) /*!DMACTL |= HSUSBD_DMACTL_DMAEN_Msk) /*!PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk)) /*!DMACNT = 0ul; + HSUSBD->DMACTL = 0x80ul; + HSUSBD->DMACTL = 0x00ul; +} +/** + * @brief HSUSBD_SetEpBufAddr, Set Endpoint buffer address + * @param[in] u32Ep Endpoint Number + * @param[in] u32Base Buffer Start Address + * @param[in] u32Len Buffer length + * @retval None. + */ +__STATIC_INLINE void HSUSBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len) +{ + if (u32Ep == CEP) + { + HSUSBD->CEPBUFST = u32Base; + HSUSBD->CEPBUFEND = u32Base + u32Len - 1ul; + } + else + { + HSUSBD->EP[u32Ep].EPBUFST = u32Base; + HSUSBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1ul; + } +} + +/** + * @brief HSUSBD_ConfigEp, Config Endpoint + * @param[in] u32Ep USB endpoint + * @param[in] u32EpNum Endpoint number + * @param[in] u32EpType Endpoint type + * @param[in] u32EpDir Endpoint direction + * @retval None. + */ +__STATIC_INLINE void HSUSBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir) +{ + if (u32EpType == HSUSBD_EP_CFG_TYPE_BULK) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_AUTO); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_INT) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_MANUAL); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_ISO) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_FLY); + } + + HSUSBD->EP[u32Ep].EPCFG = (u32EpType|u32EpDir|HSUSBD_EP_CFG_VALID|(u32EpNum << 4)); +} + +/** + * @brief Set USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + */ +__STATIC_INLINE void HSUSBD_SetEpStall(uint32_t u32Ep) +{ + if (u32Ep == CEP) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Set USB endpoint stall state, endpoint will return STALL token. + */ +__STATIC_INLINE void HSUSBD_SetStall(uint32_t u32EpNum) +{ + uint32_t i; + + if (u32EpNum == 0ul) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } + } + } +} + +/** + * @brief Clear USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearEpStall(uint32_t u32Ep) +{ + HSUSBD->EP[u32Ep].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearStall(uint32_t u32EpNum) +{ + uint32_t i; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } +} + +/** + * @brief Get USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * @details Get USB endpoint stall state of the specified endpoint ID. + */ +__STATIC_INLINE uint32_t HSUSBD_GetEpStall(uint32_t u32Ep) +{ + return (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @retval 0: USB endpoint is not stalled. + * @retval non-0: USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + */ +__STATIC_INLINE uint32_t HSUSBD_GetStall(uint32_t u32EpNum) +{ + uint32_t i; + uint32_t val = 0ul; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + val = (HSUSBD->EP[i].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); + break; + } + } + return val; +} + + +/*-------------------------------------------------------------------------------------------*/ +typedef void (*HSUSBD_VENDOR_REQ)(void); /*!CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + * \hideinitializer + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + * \hideinitializer + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + * \hideinitializer + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + * \hideinitializer + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + * \hideinitializer + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + * \hideinitializer + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + * \hideinitializer + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * \hideinitializer + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * \hideinitializer + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * \hideinitializer + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + * \hideinitializer + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C will send STOP after PDMA transfers done automatically. + * \hideinitializer + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + * \hideinitializer + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) + { + } +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/i2s.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/i2s.h new file mode 100644 index 0000000000..f6ae32b4ff --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/i2s.h @@ -0,0 +1,352 @@ +/****************************************************************************//** + * @file i2s.h + * @version V0.10 + * @brief M480 I2S driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */ +#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/opa.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/opa.h new file mode 100644 index 0000000000..3f2b592658 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/opa.h @@ -0,0 +1,208 @@ +/**************************************************************************//** + * @file opa.h + * @version V3.00 + * @brief M480 series OPA driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_H__ +#define __OPA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OPA_Driver OPA Driver + @{ +*/ + +/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants + @{ +*/ +#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */ +#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */ +#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */ + +/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */ + +/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define OPA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32LevelSel); + +/** + * @brief This macro is used to power on the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPx_EN (x=0, 1) bit of OPACR register to power on the OPA circuit. + * @note Remember to enable HIRC clock while power on the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to power down the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPx_EN (x=0, 1) bit of OPACR register to power down the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPSCHx_EN (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPSCHx_EN (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPDIEx (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPDIEx (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to get OPA digital output state + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return OPA digital output state + * @details This macro will return the OPA digital output value. + * \hideinitializer + */ +#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to get OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @retval 0 OPA interrupt does not occur. + * @retval 1 OPA interrupt occurs. + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to clear OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will write 1 to OPDFx (x=0,1) bit of OPASR register to clear interrupt flag. + * \hideinitializer + */ +#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum))) + + +/** + * @brief This function is used to configure and start OPA calibration + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @param[in] u32ClockSel Select OPA calibration clock + * - \ref OPA_CALIBRATION_CLK_1K + * @param[in] u32RefVol Select OPA reference voltage + * - \ref OPA_CALIBRATION_RV_1_2_AVDD + * - \ref OPA_CALIBRATION_RV_H_L_VCM + * @retval 0 PMOS and NMOS calibration successfully. + * @retval -1 only PMOS calibration failed. + * @retval -2 only NMOS calibration failed. + * @retval -3 PMOS and NMOS calibration failed. + */ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, + uint32_t u32OpaNum, + uint32_t u32ClockSel, + uint32_t u32RefVol) +{ + uint32_t u32CALResult; + int32_t i32Ret = 0L; + + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALCLK0_Msk << (u32OpaNum << 1))); + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum)); + (opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum)); + while((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))) {} + + u32CALResult = ((opa)->CALST >> ((u32OpaNum)*4U)) & (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk); + if (u32CALResult == 0U) + { + i32Ret = 0L; + } + else if (u32CALResult == OPA_CALST_CALNS0_Msk) + { + i32Ret = -2L; + } + else if (u32CALResult == OPA_CALST_CALPS0_Msk) + { + i32Ret = -1L; + } + else if (u32CALResult == (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk)) + { + i32Ret = -3L; + } + + return i32Ret; +} + +/** + * @brief This macro is used to generate asynchronous reset signals to OPA controller + * @param None + * @return None + * \hideinitializer + */ +#define OPA_Reset() \ +do { \ + SYS->IPRST2 |= SYS_IPRST2_OPARST_Msk; \ + SYS->IPRST2 &= ~SYS_IPRST2_OPARST_Msk; \ +} while(0) + +/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OPA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __OPA_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/otg.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/otg.h new file mode 100644 index 0000000000..b0af0c421d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/otg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file otg.h + * @version V0.10 + * @brief M480 Series OTG Driver Header File + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __OTG_H__ +#define __OTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OTG_Driver OTG Driver + @{ +*/ + + +/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* OTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable OTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. + * \hideinitializer + */ +#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + * \hideinitializer + */ +#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + * \hideinitializer + */ +#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + * \hideinitializer + */ +#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /*__OTG_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/pdma.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/pdma.h new file mode 100644 index 0000000000..fb713e39a3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/pdma.h @@ -0,0 +1,384 @@ +/**************************************************************************//** + * @file pdma.h + * @version V1.00 + * @brief M480 series PDMA driver header file + * + * @copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) + +/** + * @brief Get Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN)) + +/** + * @brief Clear Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + * \hideinitializer + */ +#define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + * \hideinitializer + */ +#define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PDMA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_Close(PDMA_T * pdma); +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/qei.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/qei.h new file mode 100644 index 0000000000..32dde22922 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/qei.h @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file qei.h + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T* qei); +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T* qei); +void QEI_Stop(QEI_T* qei); + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QEI_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/qspi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/qspi.h new file mode 100644 index 0000000000..ec8a91789d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/qspi.h @@ -0,0 +1,356 @@ +/**************************************************************************//** + * @file qspi.h + * @version V3.00 + * @brief M480 series QSPI driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */ +#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + * \hideinitializer + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + * \hideinitializer + */ +#define QSPI_READ_RX(qspi) ((qspi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + * \hideinitializer + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData)) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + * \hideinitializer + */ +#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk)) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + * \hideinitializer + */ +#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + * \hideinitializer + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + * \hideinitializer + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + * \hideinitializer + */ +#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + * \hideinitializer + */ +#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + * \hideinitializer + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller. + * \hideinitializer + */ +#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller. + * \hideinitializer + */ +#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk ) + + + + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/rtc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/rtc.h new file mode 100644 index 0000000000..c58255839a --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/rtc.h @@ -0,0 +1,336 @@ +/**************************************************************************//** + * @file rtc.h + * @version V3.00 + * @brief M480 series RTC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ +#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */ + + +#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */ +#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */ +#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */ +#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define REF_RANDOM_PATTERN 0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define REF_PREVIOUS_PATTERN 0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */ +#define REF_SEED 0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC snooper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param None + * + * @retval 0 RTC snooper pin interrupt did not occur + * @retval 1 RTC snooper pin interrupt occurred + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC TAMPER Interrupt Status + * + * @param None + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00))) + +/** + * @brief Read Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register(RTC_RWEN). + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void RTC_WaitAccessEnable(void); + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +__STATIC_INLINE void RTC_WaitAccessEnable(void) +{ + while((RTC->RWEN & RTC_RWEN_RTCBUSY_Msk) == RTC_RWEN_RTCBUSY_Msk) + { + } + + /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */ + RTC->RWEN = RTC_WRITE_KEY; + + /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */ + while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == (uint32_t)0x0) + { + } +} + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/sc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/sc.h new file mode 100644 index 0000000000..18d6861947 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/sc.h @@ -0,0 +1,267 @@ +/**************************************************************************//** + * @file sc.h + * @version V1.00 + * @brief M480 Smartcard (SC) driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * @param[in] sc Base address of smartcard module + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * @param[in] sc Base address of smartcard module + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF + * @return None + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * @param[in] sc Base address of smartcard module + * @return One byte read from receive FIFO + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * @param[in] sc Base address of smartcard module + * @param[in] u8Data Data to write to transmit FIFO + * @return None + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * @param[in] sc Base address of smartcard module + * @param[in] u32Len Stop bit length, ether 1 or 2. + * @return None + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry + * @return None + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry + * @return None + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } + +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SC_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/scuart.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/scuart.h new file mode 100644 index 0000000000..40fe3330d0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/scuart.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file scuart.h + * @version V1.00 + * @brief M480 Smartcard UART mode (SCUART) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + + +/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * @param[in] sc The base address of smartcard module. + * @param[in] u8Data Data byte to transmit + * @return None + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get TX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get TX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * @param[in] sc The base address of smartcard module + * @return None + * @note This Macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * @param[in] sc The base address of smartcard module + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1) + +/** + * @brief Check specified Smartcard port Transmission Status + * @param[in] sc The pointer of smartcard module. + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + +/* RX Macros */ + +/** + * @brief Read Rx data register + * @param[in] sc The base address of smartcard module + * @return The oldest data byte in RX FIFO + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get RX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + + +/** + * @brief Get RX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0) + +/* Interrupt Macros */ + +/** + * @brief Enable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * @param[in] sc The base address of smartcard module + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCUART_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/sdh.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/sdh.h new file mode 100644 index 0000000000..2b53fd369c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/sdh.h @@ -0,0 +1,200 @@ +/**************************************************************************//** + * @file sdh.h + * @version V1.00 + * @brief M480 SDH driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include + +#ifndef __SDH_H__ +#define __SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100ul /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01ul) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02ul) /*!< OOM \hideinitializer */ + +/*-- function return value */ +#define Successful 0ul /*!< Success \hideinitializer */ +#define Fail 1ul /*!< Failed \hideinitializer */ + +/*--- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0ul /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1ul /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2ul /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3ul /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4ul /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10ul) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11ul) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12ul) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13ul) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14ul) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15ul) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16ul) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17ul) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18ul) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19ul) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000ul /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000ul /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000ul /*!< output 50MHz to SDH \hideinitializer */ + +#define SD_PORT0 (1 << 0) /*!< Card select SD0 \hideinitializer */ +#define SD_PORT1 (1 << 2) /*!< Card select SD1 \hideinitializer */ +#define CardDetect_From_GPIO (1ul << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1ul << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +typedef struct SDH_info_t +{ + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ +} SDH_INFO_T; /*!< Structure holds SD card info */ + +/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern uint8_t g_u8R3Flag; +extern uint8_t volatile g_u8SDDataReadyFlag; +extern SDH_INFO_T SD0, SD1; +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize) + + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDH_H__ */ +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/spi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/spi.h new file mode 100644 index 0000000000..57c23968f3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/spi.h @@ -0,0 +1,594 @@ +/**************************************************************************//** + * @file spi.h + * @version V3.00 + * @brief M480 series SPI driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ +#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */ +#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0U<STATUS = SPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + * \hideinitializer + */ +#define SPI_READ_RX(spi) ((spi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + * \hideinitializer + */ +#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData)) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + * \hideinitializer + */ +#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + * \hideinitializer + */ +#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + * \hideinitializer + */ +#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + * \hideinitializer + */ +#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + * \hideinitializer + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + * \hideinitializer + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + * \hideinitializer + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + * \hideinitializer + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + * \hideinitializer + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/spim.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/spim.h new file mode 100644 index 0000000000..62da94c050 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/spim.h @@ -0,0 +1,631 @@ +/**************************************************************************//** + * @file spim.h + * @version V1.00 + * @brief M480 series SPIM driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPIM_H__ +#define __SPIM_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + + +/** @addtogroup SPIM_EXPORTED_CONSTANTS SPIM Exported Constants + @{ +*/ + +#define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */ +#define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */ +#define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ +#define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPIM_CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ +#define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ +#define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ + +#define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ + +#define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ + +typedef enum +{ + MFGID_UNKNOW = 0x00U, + MFGID_SPANSION = 0x01U, + MFGID_EON = 0x1CU, + MFGID_ISSI = 0x7FU, + MFGID_MXIC = 0xC2U, + MFGID_WINBOND = 0xEFU +} +E_MFGID; + +/* Flash opcodes. */ +#define OPCODE_WREN 0x06U /* Write enable */ +#define OPCODE_RDSR 0x05U /* Read status register #1*/ +#define OPCODE_WRSR 0x01U /* Write status register #1 */ +#define OPCODE_RDSR2 0x35U /* Read status register #2*/ +#define OPCODE_WRSR2 0x31U /* Write status register #2 */ +#define OPCODE_RDSR3 0x15U /* Read status register #3*/ +#define OPCODE_WRSR3 0x11U /* Write status register #3 */ +#define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ +#define OPCODE_BE_32K 0x52U /* Erase 32KB block */ +#define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ +#define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ +#define OPCODE_READ_ID 0x90U /* Read ID */ +#define OPCODE_RDID 0x9fU /* Read JEDEC ID */ +#define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ +#define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ +#define OPCODE_NORM_READ 0x03U /* Read data bytes */ +#define OPCODE_FAST_READ 0x0bU /* Read data bytes */ +#define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ +#define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ + +/* Used for SST flashes only. */ +#define OPCODE_BP 0x02U /* Byte program */ +#define OPCODE_WRDI 0x04U /* Write disable */ +#define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ + +/* Used for Macronix flashes only. */ +#define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ +#define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ + +#define OPCODE_RDSCUR 0x2bU +#define OPCODE_WRSCUR 0x2fU + +#define OPCODE_RSTEN 0x66U +#define OPCODE_RST 0x99U + +#define OPCODE_ENQPI 0x38U +#define OPCODE_EXQPI 0xFFU + +/* Status Register bits. */ +#define SR_WIP 0x1U /* Write in progress */ +#define SR_WEL 0x2U /* Write enable latch */ +#define SR_QE 0x40U /* Quad Enable for MXIC */ +/* Status Register #2 bits. */ +#define SR2_QE 0x2U /* Quad Enable for Winbond */ +/* meaning of other SR_* bits may differ between vendors */ +#define SR_BP0 0x4U /* Block protect 0 */ +#define SR_BP1 0x8U /* Block protect 1 */ +#define SR_BP2 0x10U /* Block protect 2 */ +#define SR_SRWD 0x80U /* SR write protect */ +#define SR3_ADR 0x01U /* 4-byte u32Address mode */ + +#define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ + +/** @endcond HIDDEN_SYMBOLS */ + +/*@}*/ /* end of group SPIM_EXPORTED_CONSTANTS */ + + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @details Enable cipher. + * \hideinitializer + */ +#define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Disable cipher. + * \hideinitializer + */ +#define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Enable cipher balance + * \hideinitializer + */ +#define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) + +/** + * @details Disable cipher balance + * \hideinitializer + */ +#define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) + +/** + * @details Set 4-byte address to be enabled/disabled. + * \hideinitializer + */ +#define SPIM_SET_4BYTE_ADDR_EN(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ + } while (0) + +/** + * @details Enable SPIM interrupt + * \hideinitializer + */ +#define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) + +/** + * @details Disable SPIM interrupt + * \hideinitializer + */ +#define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) + +/** + * @details Is interrupt flag on. + * \hideinitializer + */ +#define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) + +/** + * @details Clear interrupt flag. + * \hideinitializer + */ +#define SPIM_CLR_INT() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ + } while (0) + +/** + * @details Set transmit/receive bit length + * \hideinitializer + */ +#define SPIM_SET_DATA_WIDTH(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive bit length setting + * \hideinitializer + */ +#define SPIM_GET_DATA_WIDTH() \ + (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) + +/** + * @details Set data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_SET_DATA_NUM(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_GET_DATA_NUM() \ + (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) + +/** + * @details Enable Single Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ + } while (0) + +/** + * @details Enable Single Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ + } while (0) + +/** + * @details Enable Dual Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Dual Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Enable Quad Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Quad Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Set suspend interval which ranges between 0 and 15. + * \hideinitializer + */ +#define SPIM_SET_SUSP_INTVL(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ + } while (0) + +/** + * @details Get suspend interval setting + * \hideinitializer + */ +#define SPIM_GET_SUSP_INTVL() \ + ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) + +/** + * @details Set operation mode. + * \hideinitializer + */ +#define SPIM_SET_OPMODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get operation mode. + * \hideinitializer + */ +#define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) + +/** + * @details Set SPIM mode. + * \hideinitializer + */ +#define SPIM_SET_SPIM_MODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get SPIM mode. + * \hideinitializer + */ +#define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) + +/** + * @details Start operation. + * \hideinitializer + */ +#define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Is engine busy. + * \hideinitializer + */ +#define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Wait for free. + * \hideinitializer + */ +#define SPIM_WAIT_FREE() \ + do { \ + while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \ + } while (0) + +/** + * @details Enable cache. + * \hideinitializer + */ +#define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Disable cache. + * \hideinitializer + */ +#define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Is cache enabled. + * \hideinitializer + */ +#define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) + +/** + * @details Enable CCM + * \hideinitializer + */ +#define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) + +/** + * @details Disable CCM. + * \hideinitializer + */ +#define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) + +/** + * @details Is CCM enabled. + * \hideinitializer + */ +#define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) + +/** + * @details Invalidate cache. + * \hideinitializer + */ +#define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) + +/** + * @details Set SS(Select Active) to active level. + * \hideinitializer + */ +#define SPIM_SET_SS_EN(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ + } while (0) + +/** + * @details Is SS(Select Active) in active level. + * \hideinitializer + */ +#define SPIM_GET_SS_EN() \ + (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) + +/** + * @details Set active level of slave select to be high/low. + * \hideinitializer + */ +#define SPIM_SET_SS_ACTLVL(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ + } while (0) + +/** + * @details Set idle time interval + * \hideinitializer + */ +#define SPIM_SET_IDL_INTVL(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ + } while (0) + +/** + * @details Get idle time interval setting + * \hideinitializer + */ +#define SPIM_GET_IDL_INTVL() \ + ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) + +/** + * @details Set SPIM clock divider + * \hideinitializer + */ +#define SPIM_SET_CLOCK_DIVIDER(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ + } while (0) + +/** + * @details Get SPIM current clock divider setting + * \hideinitializer + */ +#define SPIM_GET_CLOCK_DIVIDER() \ + ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) + +/** + * @details Set SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ + } while (0) + +/** + * @details Get SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_DWDELSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) + +/** + * @details Set sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ + } while (0) + +/** + * @details Get sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_RDDLYSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) + +/** + * @details Set sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ + +/** + * @details Get sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_CLR_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) + +/** + * @details Set mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_SET_DMMCTL_CRMDAT(x) \ + do { \ + (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ + } while (0) + +/** + * @details Get mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_GET_DMMCTL_CRMDAT() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) + +/** + * @details Set DMM mode SPI flash deselect time + * \hideinitializer + */ +#define SPIM_DMM_SET_DESELTIM(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ + } while (0) + +/** + * @details Get current DMM mode SPI flash deselect time setting + * \hideinitializer + */ +#define SPIM_DMM_GET_DESELTIM() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) + +/** + * @details Enable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Disable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Enable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) + +/** + * @details Disable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) + +/** + * @details Set DMM mode SPI flash active SCLK time + * \hideinitializer + */ +#define SPIM_DMM_SET_ACTSCLKT(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ + } while (0) + +/** + * @details Set SPI flash active SCLK time as SPIM default + * \hideinitializer + */ +#define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) + * \hideinitializer + */ +#define SPIM_SET_DCNUM(x) \ + do { \ + SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ + } while (0) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default + * \hideinitializer + */ +#define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Function Prototypes */ +/*---------------------------------------------------------------------------------------------------------*/ + + +int SPIM_InitFlash(int clrWP); +uint32_t SPIM_GetSClkFreq(void); +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); +int SPIM_Is4ByteModeEnable(uint32_t u32NBit); + +void SPIM_ChipErase(uint32_t u32NBit, int isSync); +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); + +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); + +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); + +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); +void SPIM_ExitDirectMapMode(void); + +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIM_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/sys.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/sys.h new file mode 100644 index 0000000000..eadb0b86c8 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/sys.h @@ -0,0 +1,1500 @@ +/**************************************************************************//** + * @file SYS.h + * @version V3.0 + * @brief M480 Series SYS Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef __SYS_H__ +#define __SYS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/ +#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/ +#define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */ +#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */ +#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */ +#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */ +#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */ +#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */ +#define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */ +#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */ + +#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */ +#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */ +#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */ +#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */ +#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */ +#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */ +#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */ +#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */ +#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */ +#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */ +#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */ +#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */ +#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */ +#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */ +#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */ +#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */ +#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */ +#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */ +#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */ +#define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */ +#define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */ +#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */ +#define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */ +#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */ + +#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */ +#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */ +#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */ +#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */ +#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */ +#define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */ +#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */ +#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */ +#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */ +#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */ +#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */ +#define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */ +#define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */ +#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */ +#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */ +#define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */ +#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */ +#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* VREFCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */ +#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */ +#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* USBPHY constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */ +#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ +#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ +#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PLCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_PLCTL_PLSEL_PL0 (0x0UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ; + +*/ +/********************* Bit definition of GPA_MFPL register **********************/ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<BODCTL |= SYS_BODCTL_BODIF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + * \hideinitializer + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + * \hideinitializer + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + * \hideinitializer + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + * \hideinitializer + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + * \hideinitializer + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + * \hideinitializer + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + * \hideinitializer + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + * \hideinitializer + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + * \hideinitializer + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_POR() (SYS->PORCTL = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + * \hideinitializer + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/timer.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer.h new file mode 100644 index 0000000000..d8664d7fa5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer.h @@ -0,0 +1,507 @@ +/**************************************************************************//** + * @file timer.h + * @version V1.00 + * @brief M480 series Timer Controller(Timer) driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while((timer->CNT&TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) + { + ; + } +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__ */ + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/timer_pwm.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer_pwm.h new file mode 100644 index 0000000000..96a2cd1714 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer_pwm.h @@ -0,0 +1,745 @@ +/**************************************************************************//** + * @file timer_pwm.h + * @version V1.00 + * @brief M480 series Timer PWM Controller(Timer PWM) driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_PWM_H__ +#define __TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger ADC Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output function. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Set specified channel output is inversed or not. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If u32ChMask parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If u32ChMask parameter is 0, then output mask function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified UART port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified UART port transmission is over nor not. + * \hideinitializer + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified UART port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified UART port transmission is over. + * \hideinitializer + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + * \hideinitializer + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart); +__STATIC_INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + + + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__UART_H__*/ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usbd.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usbd.h new file mode 100644 index 0000000000..5cf40f5e07 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usbd.h @@ -0,0 +1,692 @@ +/**************************************************************************//** + * @file usbd.h + * @version V1.00 + * @brief M480 series USB driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCT USBD Exported Struct + @{ +*/ +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCT */ + + + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ +#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */ +#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */ + +#define EP0 0ul /*!< Endpoint 0 \hideinitializer */ +#define EP1 1ul /*!< Endpoint 1 \hideinitializer */ +#define EP2 2ul /*!< Endpoint 2 \hideinitializer */ +#define EP3 3ul /*!< Endpoint 3 \hideinitializer */ +#define EP4 4ul /*!< Endpoint 4 \hideinitializer */ +#define EP5 5ul /*!< Endpoint 5 \hideinitializer */ +#define EP6 6ul /*!< Endpoint 6 \hideinitializer */ +#define EP7 7ul /*!< Endpoint 7 \hideinitializer */ +#define EP8 8ul /*!< Endpoint 8 \hideinitializer */ +#define EP9 9ul /*!< Endpoint 9 \hideinitializer */ +#define EP10 10ul /*!< Endpoint 10 \hideinitializer */ +#define EP11 11ul /*!< Endpoint 11 \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00ul +#define REQ_CLASS 0x20ul +#define REQ_VENDOR 0x40ul + +/* USB Standard Request */ +#define GET_STATUS 0x00ul +#define CLEAR_FEATURE 0x01ul +#define SET_FEATURE 0x03ul +#define SET_ADDRESS 0x05ul +#define GET_DESCRIPTOR 0x06ul +#define SET_DESCRIPTOR 0x07ul +#define GET_CONFIGURATION 0x08ul +#define SET_CONFIGURATION 0x09ul +#define GET_INTERFACE 0x0Aul +#define SET_INTERFACE 0x0Bul +#define SYNC_FRAME 0x0Cul + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01ul +#define DESC_CONFIG 0x02ul +#define DESC_STRING 0x03ul +#define DESC_INTERFACE 0x04ul +#define DESC_ENDPOINT 0x05ul +#define DESC_QUALIFIER 0x06ul +#define DESC_OTHERSPEED 0x07ul +#define DESC_IFPOWER 0x08ul +#define DESC_OTG 0x09ul +#define DESC_BOS 0x0Ful +#define DESC_CAPABILITY 0x10ul + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01ul +#define CAP_USB20_EXT 0x02ul + +/* USB HID Descriptor Type */ +#define DESC_HID 0x21ul +#define DESC_HID_RPT 0x22ul + +/* USB Descriptor Length */ +#define LEN_DEVICE 18ul +#define LEN_QUALIFIER 10ul +#define LEN_CONFIG 9ul +#define LEN_INTERFACE 9ul +#define LEN_ENDPOINT 7ul +#define LEN_OTG 5ul +#define LEN_BOS 5ul +#define LEN_HID 9ul +#define LEN_CCID 0x36ul +#define LEN_BOSCAP 7ul + +/* USB Endpoint Type */ +#define EP_ISO 0x01 +#define EP_BULK 0x02 +#define EP_INT 0x03 + +#define EP_INPUT 0x80 +#define EP_OUTPUT 0x00 + +/* USB Feature Selector */ +#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul +#define FEATURE_ENDPOINT_HALT 0x00ul +/** @endcond HIDDEN_SYMBOLS */ + +/******************************************************************************/ +/* USB Specific Macros */ +/******************************************************************************/ + +#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable \hideinitializer */ +#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 \hideinitializer */ + +#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable \hideinitializer */ +#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On \hideinitializer */ +#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable \hideinitializer */ +#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable \hideinitializer */ + +#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt \hideinitializer */ +#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt \hideinitializer */ +#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */ +#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */ + +#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */ +#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */ +#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event \hideinitializer */ +#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */ +#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */ +#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */ +#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */ +#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */ +#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */ +#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */ +#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */ +#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event \hideinitializer */ +#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event \hideinitializer */ +#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event \hideinitializer */ +#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event \hideinitializer */ + +#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset \hideinitializer */ +#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend \hideinitializer */ +#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume \hideinitializer */ +#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout \hideinitializer */ + +#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall \hideinitializer */ +#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall \hideinitializer */ + +#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable \hideinitializer */ +#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint \hideinitializer */ +#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint \hideinitializer */ +#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */ + + + +/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ +/** + * @brief Compare two input numbers and return maximum one. + * + * @param[in] a First number to be compared. + * @param[in] b Second number to be compared. + * + * @return Maximum value between a and b. + * + * @details If a > b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * \hideinitializer + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0)) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * \hideinitializer + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * \hideinitializer + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN)) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * \hideinitializer + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * \hideinitializer + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0)) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * \hideinitializer + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * \hideinitializer + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * \hideinitializer + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * \hideinitializer + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * \hideinitializer + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * \hideinitializer + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag)) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * \hideinitializer + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * + * @details Return USB_ATTR[3:0] for USB bus events. + * \hideinitializer + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf)) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * \hideinitializer + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * \hideinitializer + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * \hideinitializer + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * \hideinitializer + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * \hideinitializer + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + * \hideinitializer + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i=0ul; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + + +extern volatile uint8_t g_usbd_RemoteWakeupEn; + + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__USBD_H__*/ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_i2c.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_i2c.h new file mode 100644 index 0000000000..b57621a5ff --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_i2c.h @@ -0,0 +1,331 @@ +/**************************************************************************//** + * @file USCI_I2C.h + * @version V3.0 + * @brief M480 series USCI I2C(UI2C) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USCI_I2C_H__ +#define __USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */ +#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */ +#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */ +#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */ + +/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK. + * \hideinitializer + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + * \hideinitializer + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + * \hideinitializer + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + * \hideinitializer + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + * \hideinitializer + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + * \hideinitializer + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + * \hideinitializer + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + * \hideinitializer + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function. + * \hideinitializer + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen); + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_spi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_spi.h new file mode 100644 index 0000000000..a951a85d2c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_spi.h @@ -0,0 +1,410 @@ +/****************************************************************************//** + * @file usci_spi.h + * @version V3.00 + * @brief M480 series USCI_SPI driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_SPI_H__ +#define __USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */ +#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */ +#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */ +#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */ +#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */ +#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */ +#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */ +#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */ +#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */ +#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */ +#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */ +#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */ +#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */ +#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */ +#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */ +#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ((uspi)->RXDAT) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi,u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag)) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN |= (u32IntSel)) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN &= ~ (u32IntSel)) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL |= (u32IntSel)) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL &= ~ (u32IntSel)) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN |= (u32IntSel)) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN &= ~ (u32IntSel)) + + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_SPI_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_uart.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_uart.h new file mode 100644 index 0000000000..636b2c4d23 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_uart.h @@ -0,0 +1,438 @@ +/**************************************************************************//** + * @file usci_uart.h + * @version V3.00 + * @brief M480 series USCI UART (UUART) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_UART_H__ +#define __USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */ +#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */ +#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */ +#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */ +#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */ +#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */ + +#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */ +#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */ +#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */ +#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */ +#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */ +#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */ +#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */ +#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */ + + +/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + * \hideinitializer + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + * \hideinitializer + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + * \hideinitializer + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + * \hideinitializer + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + * \hideinitializer + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + * \hideinitializer + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + * \hideinitializer + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_UART_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/wdt.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/wdt.h new file mode 100644 index 0000000000..17dc9fac21 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/wdt.h @@ -0,0 +1,215 @@ +/**************************************************************************//** + * @file wdt.h + * @version V3.00 + * @brief M480 series WDT driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 18-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + return; +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; + return; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); + return; +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WDT_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/wwdt.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/wwdt.h new file mode 100644 index 0000000000..5212ab2e49 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/wwdt.h @@ -0,0 +1,151 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V3.00 + * @brief M480 series WWDT driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/acmp.c b/bsp/nuvoton_m487/libraries/StdDriver/src/acmp.c new file mode 100644 index 0000000000..65d4d7ab88 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/acmp.c @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file acmp.c + * @version V1.00 + * @brief M480 series Analog Comparator(ACMP) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/bpwm.c b/bsp/nuvoton_m487/libraries/StdDriver/src/bpwm.c new file mode 100644 index 0000000000..c8ff0eb394 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/bpwm.c @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V1.00 + * @brief M480 series BPWM driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32PWMClockSrc /= 1000UL; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if (!(1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* all channels share a prescaler */ + u16Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u16Prescale); + + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* all channels share a prescaler */ + u32Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + u32CNR -= 1U; + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + if(u32DutyCycle) + { + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL - 1UL); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTLn_Msk | BPWM_WGCTL0_ZPCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum * (2U)) + (uint32_t)BPWM_WGCTL0_PRDPCTLn_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTLn_Msk | BPWM_WGCTL1_CMPUCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * (2U) + (uint32_t)BPWM_WGCTL1_CMPDCTLn_Pos)); + } + else + { + BPWM_SET_CMR(bpwm, u32ChannelNum, 0U); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTLn_Msk | BPWM_WGCTL0_ZPCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL0_ZPCTLn_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTLn_Msk | BPWM_WGCTL1_CMPUCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL1_CMPDCTLn_Pos)); + } + + return(i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->PERIOD = 0U; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8U)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8U)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) * 8U)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) * 8U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8U)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) * 8U)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (bpwm)->STATUS = (BPWM_STATUS_EADCTRGn_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRGn_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIFn_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIFn_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + + (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIFn_Msk | BPWM_INTSTS_CMPDIFn_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIFn_Msk | BPWM_INTSTS_CMPUIFn_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode PWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/can.c b/bsp/nuvoton_m487/libraries/StdDriver/src/can.c new file mode 100644 index 0000000000..7f17879b92 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/can.c @@ -0,0 +1,1275 @@ +/**************************************************************************//** + * @file can.c + * @version V2.00 + * @brief M480 series CAN driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +#if defined(CAN1) +static uint8_t gu8LockCanIf[2ul][2ul] = {0ul}; /* The chip has two CANs. */ +#elif defined(CAN0) || defined(CAN) +static uint8_t gu8LockCanIf[1ul][2ul] = {0ul}; /* The chip only has one CAN. */ +#endif + +#define RETRY_COUNTS (0x10000000ul) + +#define TSEG1_MIN 2ul +#define TSEG1_MAX 16ul +#define TSEG2_MIN 1ul +#define TSEG2_MAX 8ul +#define BRP_MIN 1ul +#define BRP_MAX 1024ul /* 6-bit BRP field + 4-bit BRPE field*/ +#define SJW_MAX 4ul +#define BRP_INC 1ul + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + +static uint32_t LockIF(CAN_T *tCAN); +static uint32_t LockIF_TL(CAN_T *tCAN); +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo); +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2); + +/** + * @brief Check if any interface is available then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If a interface is + * available, set a flag to lock the interface. + */ +static uint32_t LockIF(CAN_T *tCAN) +{ + uint32_t u32CanNo; + uint32_t u32FreeIfNo; + uint32_t u32IntMask; + +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1ul : 0ul; +#else /* defined(CAN0) || defined(CAN) */ + u32CanNo = 0ul; +#endif + + u32FreeIfNo = 2ul; + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + /* Check interface 1 is available or not */ + if((tCAN->IF[0ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + if(gu8LockCanIf[u32CanNo][0ul] == 0ul) + { + gu8LockCanIf[u32CanNo][0ul] = 1u; + u32FreeIfNo = 0ul; + } + else + { + } + } + else + { + } + + /* Or check interface 2 is available or not */ + if(u32FreeIfNo == 2ul) + { + if((tCAN->IF[1ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + if(gu8LockCanIf[u32CanNo][1ul] == 0ul) + { + gu8LockCanIf[u32CanNo][1ul] = 1u; + u32FreeIfNo = 1ul; + } + else + { + } + } + else + { + } + } + else + { + } + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + + return u32FreeIfNo; +} + +/** + * @brief Check if any interface is available in a time limitation then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If no interface is + * it will try again until time out. If a interface is available, set a flag to + * lock the interface. + */ +static uint32_t LockIF_TL(CAN_T *tCAN) +{ + uint32_t u32Count; + uint32_t u32FreeIfNo; + + for(u32Count = 0ul; u32Count < RETRY_COUNTS; u32Count++) + { + if((u32FreeIfNo = LockIF(tCAN)) != 2ul) + { + break; + } + else + { + } + } + + return u32FreeIfNo; +} + +/** + * @brief Release locked interface. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Info The interface number, 0 or 1. + * @return none + * @details Release the locked interface. + */ +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo) +{ + uint32_t u32IntMask; + uint32_t u32CanNo; + + if(u32IfNo >= 2ul) + { + } + else + { +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1ul : 0ul; +#else /* defined(CAN0) || defined(CAN) */ + u32CanNo = 0ul; +#endif + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + gu8LockCanIf[u32CanNo][u32IfNo] = 0u; + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + } +} + +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2) +{ + *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000; + if (*tseg2 < TSEG2_MIN) + { + *tseg2 = TSEG2_MIN; + } + else + { + } + + if (*tseg2 > TSEG2_MAX) + { + *tseg2 = TSEG2_MAX; + } + else + { + } + + *tseg1 = tseg - *tseg2; + if (*tseg1 > TSEG1_MAX) + { + *tseg1 = TSEG1_MAX; + *tseg2 = tseg - *tseg1; + } + else + { + } + + return 1000 * (tseg + 1 - *tseg2) / (tseg + 1); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Enter initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8Mask Following values can be used. + * \ref CAN_CON_DAR_Msk Disable automatic retransmission. + * \ref CAN_CON_EIE_Msk Enable error interrupt. + * \ref CAN_CON_SIE_Msk Enable status interrupt. + * \ref CAN_CON_IE_Msk CAN interrupt. + * @return None + * @details This function is used to set CAN to enter initialization mode and enable access bit timing + * register. After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + */ +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask) +{ + tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk); +} + + +/** + * @brief Leave initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to set CAN to leave initialization mode to let + * bit timing configuration take effect after configuration ready. + */ +void CAN_LeaveInitMode(CAN_T *tCAN) +{ + tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); + while(tCAN->CON & CAN_CON_INIT_Msk) + { + /* Check INIT bit is released */ + } +} + +/** + * @brief Wait message into message buffer in basic mode. + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode. + */ +void CAN_WaitMsg(CAN_T *tCAN) +{ + tCAN->STATUS = 0x0ul; /* clr status */ + + while(1) + { + if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */ + { + /* New Data IN */ + break; + } + else + { + } + + if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) + { + /* Rx OK */ + } + else + { + } + + if(tCAN->STATUS & CAN_STATUS_LEC_Msk) + { + /* Error */ + } + else + { + } + } +} + +/** + * @brief Get current bit rate + * @param[in] tCAN The pointer to CAN module base address. + * @return Current Bit-Rate (kilo bit per second) + * @details Return current CAN bit rate according to the user bit-timing parameter settings + */ +uint32_t CAN_GetCANBitRate(CAN_T *tCAN) +{ + uint32_t u32Tseg1, u32Tseg2; + uint32_t u32Bpr; + + u32Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos; + u32Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos; + u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6ul); + + return (SystemCoreClock / (u32Bpr + 1ul) / (u32Tseg1 + u32Tseg2 + 3ul)); +} + +/** + * @brief Switch the CAN into test mode. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8TestMask Specifies the configuration in test modes + * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode + * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode + * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode + * \ref CAN_TEST_Tx_Msk Control CAN_TX pin bit field + * @return None + * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/ + * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user + * must call CAN_LeaveInitMode() to let the setting take effect. + */ +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST = u8TestMask; +} + + +/** + * @brief Leave the test mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to Leave the test mode (switch into normal mode). + */ +void CAN_LeaveTestMode(CAN_T *tCAN) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + tCAN->CON &= (~CAN_CON_TEST_Msk); +} + +/** + * @brief Get the waiting status of a received message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @retval non-zero The corresponding message object has a new data bit is set. + * @retval 0 No message object has new data. + * @details This function is used to get the waiting status of a received message. + */ +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj) +{ + return (u8MsgObj < 16ul ? tCAN->NDAT1 & (1ul << u8MsgObj) : tCAN->NDAT2 & (1ul << (u8MsgObj - 16ul))); +} + + +/** + * @brief Send CAN message in BASIC mode of test mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure containing data to transmit. + * @return TRUE: Transmission OK + * FALSE: Check busy flag of interface 0 is timeout + * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode. + */ +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + uint32_t i = 0ul; + int32_t rev = 1l; + + while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + } + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[0].ARB1 = 0ul; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2ul) ; + } + else + { + /* extended ID*/ + tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFul; + tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16ul | CAN_IF_ARB2_XTD_Msk; + + } + + if(pCanMsg->FrameType) + { + tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC; + tCAN->IF[0].DAT_A1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]); + tCAN->IF[0].DAT_A2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]); + tCAN->IF[0].DAT_B1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]); + tCAN->IF[0].DAT_B2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]); + + /* request transmission*/ + tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /* Cannot clear busy for sending ...*/ + rev = 0l; /* return FALSE */ + } + else + { + tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */ + + for(i = 0ul; i < 0xFFFFFul; i++) + { + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + break; + } + else + { + } + } + + if(i >= 0xFFFFFul) + { + /* Cannot send out... */ + rev = 0l; /* return FALSE */ + } + else + { + } + } + + return rev; +} + +/** + * @brief Get a message information in BASIC mode. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @return FALSE No any message received. + * TRUE Receive a message success. + * + */ +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + + if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0ul) + { + /* In basic mode, receive data always save in IF2 */ + rev = 0; /* return FALSE */ + } + else + { + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFul; + + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFul) << 16; + pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1; + } + + pCanMsg->FrameType = (((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos)) ? 0ul : 1ul; + + pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + } + + return rev; +} + +/** + * @brief Set Rx message object, include ID mask. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u32idmask Specifies the identifier mask used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* Command Setting */ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2; + } + else + { + tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16; + } + + tCAN->IF[u32MsgIfNum].MASK1 = (u32idmask & 0xFFFFul); + tCAN->IF[u32MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFul; + + /* tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */ + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Set Rx message object + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* Command Setting */ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2; + } + else + { + tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16; + } + + /* tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */ + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Gets the message + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8Release Specifies the message release indicator. + * This parameter can be one of the following values: + * TRUE: the message object is released when getting the data. + * FALSE:the message object is not released. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * @retval TRUE Success + * @retval FALSE No any message received + * @details Gets the message, if received. + */ +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if(!CAN_IsNewDataReceived(tCAN, u8MsgObj)) + { + rev = 0; /* return FALSE */ + } + else + { + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0ul) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + + while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2ul; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (((tCAN->IF[u32MsgIfNum].ARB2) & 0x1FFFul) << 16) | tCAN->IF[u32MsgIfNum].ARB1; + } + + pCanMsg->DLC = (uint8_t)(tCAN->IF[u32MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + ReleaseIF(tCAN, u32MsgIfNum); + } + } + + return rev; +} + + +/** + * @brief Set bus baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * + * @return u32CurrentBitRate Real baud-rate value. + * + * @details The function is used to set bus timing parameter according current clock and target baud-rate. + */ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate) +{ + long rate; + long best_error = 1000000000, error = 0; + int best_tseg = 0, best_brp = 0, brp = 0; + int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0; + int spt_error = 1000, spt = 0, sampl_pt; + uint64_t clock_freq = (uint64_t)0, u64PCLK_DIV = (uint64_t)1; + uint32_t sjw = (uint32_t)1; + + CAN_EnterInitMode(tCAN, (uint8_t)0); + + SystemCoreClockUpdate(); + if(tCAN == CAN0) + { + u64PCLK_DIV = (uint64_t)(CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk); + u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV); + } + else if(tCAN == CAN1) + { + u64PCLK_DIV = (uint64_t)((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos); + u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV); + } + + clock_freq = SystemCoreClock / u64PCLK_DIV; + + if(u32BaudRate >= (uint32_t)1000000) + { + u32BaudRate = (uint32_t)1000000; + } + + /* Use CIA recommended sample points */ + if (u32BaudRate > (uint32_t)800000) + { + sampl_pt = (int)750; + } + else if (u32BaudRate > (uint32_t)500000) + { + sampl_pt = (int)800; + } + else + { + sampl_pt = (int)875; + } + + /* tseg even = round down, odd = round up */ + for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2ul; tseg--) + { + tsegall = 1ul + tseg / 2ul; + /* Compute all possible tseg choices (tseg=tseg1+tseg2) */ + brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2; + /* chose brp step which is possible in system */ + brp = (brp / BRP_INC) * BRP_INC; + + if ((brp < BRP_MIN) || (brp > BRP_MAX)) + { + continue; + } + rate = clock_freq / (brp * tsegall); + + error = u32BaudRate - rate; + + /* tseg brp biterror */ + if (error < 0) + { + error = -error; + } + if (error > best_error) + { + continue; + } + best_error = error; + if (error == 0) + { + spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2); + error = sampl_pt - spt; + if (error < 0) + { + error = -error; + } + if (error > spt_error) + { + continue; + } + spt_error = error; + } + best_tseg = tseg / 2; + best_brp = brp; + + if (error == 0) + { + break; + } + } + + spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2); + + /* check for sjw user settings */ + /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */ + if (sjw > SJW_MAX) + { + sjw = SJW_MAX; + } + /* bt->sjw must not be higher than tseg2 */ + if (tseg2 < sjw) + { + sjw = tseg2; + } + + /* real bit-rate */ + u32BaudRate = clock_freq / (best_brp * (tseg1 + tseg2 + 1)); + + tCAN->BTIME = ((uint32_t)(tseg2 - 1ul) << CAN_BTIME_TSEG2_Pos) | ((uint32_t)(tseg1 - 1ul) << CAN_BTIME_TSEG1_Pos) | + ((uint32_t)(best_brp - 1ul) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos); + tCAN->BRPE = ((uint32_t)(best_brp - 1ul) >> 6) & 0x0Ful; + + /* printf("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */ + + CAN_LeaveInitMode(tCAN); + + return u32BaudRate; +} + +/** + * @brief The function is used to disable all CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * + * @return None + * + * @details No Status Change Interrupt and Error Status Interrupt will be generated. + */ +void CAN_Close(CAN_T *tCAN) +{ + CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Set CAN operation mode and target baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param[in] u32Mode The CAN operation mode. Valid values are: + * - \ref CAN_NORMAL_MODE Normal operation. + * - \ref CAN_BASIC_MODE Basic mode. + * @return u32CurrentBitRate Real baud-rate value. + * + * @details Set bus timing parameter according current clock and target baud-rate. + * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + */ +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode) +{ + uint32_t u32CurrentBitRate; + + u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate); + + if(u32Mode == CAN_BASIC_MODE) + { + CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk); + } + else + { + } + + return u32CurrentBitRate; +} + +/** + * @brief The function is used to configure a transmit object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No useful interface. + * @retval TRUE Config message object success. + * + * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. + * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission. + */ +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* update the contents needed for transmission*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + else + { + /* extended ID*/ + tCAN->IF[u32MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16 | + CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + { + tCAN->IF[u32MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[1] << 8)) | pCanMsg->Data[0]); + tCAN->IF[u32MsgIfNum].DAT_A2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[3] << 8)) | pCanMsg->Data[2]); + tCAN->IF[u32MsgIfNum].DAT_B1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[5] << 8)) | pCanMsg->Data[4]); + tCAN->IF[u32MsgIfNum].DAT_B2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[7] << 8)) | pCanMsg->Data[6]); + + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Set transmit request bit. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return TRUE: Start transmit message. + * + * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored. + */ +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Enable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. Valid values are: + * - \ref CAN_CON_IE_Msk Module interrupt enable. + * - \ref CAN_CON_SIE_Msk Status change interrupt enable. + * - \ref CAN_CON_EIE_Msk Error interrupt enable. + * + * @return None + * + * @details The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + */ +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) | + (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Disable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk). + * + * @return None + * + * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset. + */ +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))); +} + + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32TimeOutCount = 0ul; + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)(FALSE); /* return FALSE */ + break; + } + else + { + } + } + + return rev; +} + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32TimeOutCount = 0ul; + + while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)FALSE; + break; + } + else + { + } + } + + return rev; +} + +/** + * @brief The function is used to configure several receive message objects. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31). + * @param[in] u32MsgCount the number of MSG RAM of the FIFO. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure receive message objects success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID) +{ + int32_t rev = (int32_t)TRUE; + uint32_t i = 0ul; + uint32_t u32TimeOutCount; + uint32_t u32EOB_Flag = 0ul; + + for(i = 1ul; i < u32MsgCount; i++) + { + u32TimeOutCount = 0ul; + + u32MsgNum += (i - 1ul); + + if(i == u32MsgCount) + { + u32EOB_Flag = 1ul; + } + else + { + } + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)FALSE; + break; + } + else + { + } + } + } + + return rev; +} + + +/** + * @brief Send CAN message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n + * 2. When operation in normal mode: No useful interface. \n + * @retval TRUE Transmit Message success. + * + * @details The receive/transmit priority for the Message Objects is attached to the message number. + * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. + */ +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32Tmp; + + u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk); + + if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) + { + rev = CAN_BasicSendMsg(tCAN, pCanMsg); + } + else + { + if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE) + { + rev = (int32_t)FALSE; + } + else + { + CAN_TriggerTxMsg(tCAN, u32MsgNum); + } + } + + return rev; +} + + +/** + * @brief Gets the message, if received. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No any message received. + * @retval TRUE Receive Message success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32Tmp; + + u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk); + + if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) + { + rev = CAN_BasicReceiveMsg(tCAN, pCanMsg); + } + else + { + rev = CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg); + } + + return rev; +} + +/** + * @brief Clear interrupt pending bit. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return None + * + * @details An interrupt remains pending until the application software has cleared it. + */ +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum) +{ + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + u32MsgIfNum = 0ul; + } + else + { + } + + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); +} + + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/clk.c b/bsp/nuvoton_m487/libraries/StdDriver/src/clk.c new file mode 100644 index 0000000000..657cdefc94 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/clk.c @@ -0,0 +1,1232 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * @brief M480 series CLK driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable clock divider output function + * @param None + * @return None + * @details This function disable clock divider output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK_DisableModuleClock(CLKO_MODULE); +} + +/** + * @brief This function enable clock divider output module clock, + * enable clock divider output function and set frequency selection. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15. + * @param[in] u32ClkDivBy1En is clock divided by one enabled. + * @return None + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n + * The formula is: \n + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. \n + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK_EnableModuleClock(CLKO_MODULE); + + /* Select CKO clock source */ + CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL); +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled and Power-down entry condition */ + CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk; + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq; + + if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq; + if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK0Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + +#if(1) + if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV4) + { + u32Freq = SystemCoreClock / 4UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV8) + { + u32Freq = SystemCoreClock / 8UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV16) + { + u32Freq = SystemCoreClock / 16UL; + } + else + { + u32Freq = SystemCoreClock; + } + + +#else + if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else + { + u32Freq = SystemCoreClock; + } +#endif + + return u32Freq; +} + + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK1Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + +#if(1) + if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV4) + { + u32Freq = SystemCoreClock / 4UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV8) + { + u32Freq = SystemCoreClock / 8UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV16) + { + u32Freq = SystemCoreClock / 16UL; + } + else + { + u32Freq = SystemCoreClock; + } + + +#else + if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else + { + u32Freq = SystemCoreClock; + } +#endif + + return u32Freq; +} + + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* The range of u32Hclk is running up to 192 MHz */ + if(u32Hclk > FREQ_192MHZ) + { + u32Hclk = FREQ_192MHZ; + } + + /* Switch HCLK clock source to HIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); + + /* Configure PLL setting if HXT clock is enabled */ + if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not enabled */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + } + + /* Select HCLK clock source to PLL, + and update system core clock + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + +/** + * @brief This function set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :-------------------------- | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PLL | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PLL | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) | + * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | + * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) | + * + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32sel = 0U, u32div = 0U; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + if(MODULE_CLKDIV(u32ModuleIdx) == 2U) + { + u32div = (uint32_t)&CLK->CLKDIV3; + } + else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) + { + u32div = (uint32_t)&CLK->CLKDIV4; + } + else + { + u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); + } + + /* Apply new divider */ + M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U); + /* Set new clock selection setting */ + M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref EMAC_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref HSUSBD_MODULE + * - \ref CRPT_MODULE + * - \ref SPIM_MODULE + * - \ref USBH_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref CAN0_MODULE + * - \ref CAN1_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref HSOTG_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref SPI3_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref OPA_MODULE + * @return None + * @details This function is used to enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->AHBCLK; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(volatile uint32_t *)u32tmpAddr |= u32tmpVal; +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref EMAC_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref HSUSBD_MODULE + * - \ref CRPT_MODULE + * - \ref SPIM_MODULE + * - \ref USBH_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref CAN0_MODULE + * - \ref CAN1_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref HSOTG_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref SPI3_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref OPA_MODULE + * @return None + * @details This function is used to disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->AHBCLK; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC + * @param[in] u32PllFreq is PLL frequency. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT; + u32PllSrcClk = __HXT; + + /* u32NR start from 2 */ + u32NR = 2UL; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC; + u32PllSrcClk = __HIRC; + + /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ + u32NR = 4UL; + } + + if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinNR = 0UL; + u32MinNF = 0UL; + u32MinNO = 0UL; + u32basFreq = u32PllFreq; + + for(u32NO = 1UL; u32NO <= 4UL; u32NO++) + { + /* Break when get good results */ + if (u32Min == 0UL) + { + break; + } + + if (u32NO != 3UL) + { + + if(u32NO == 4UL) + { + u32PllFreq = u32basFreq << 2; + } + else if(u32NO == 2UL) + { + u32PllFreq = u32basFreq << 1; + } + else + { + } + + for(u32NR = 2UL; u32NR <= 32UL; u32NR++) + { + /* Break when get good results */ + if (u32Min == 0UL) + { + break; + } + + u32Tmp = u32PllSrcClk / u32NR; + if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL)) + { + for(u32NF = 2UL; u32NF <= 513UL; u32NF++) + { + /* u32Tmp2 is shifted 2 bits to avoid overflow */ + u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF); + + if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ)) + { + u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + u32MinNO = u32NO; + + /* Break when get good results */ + if(u32Min == 0UL) + { + break; + } + } + } + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL); + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Actual PLL output clock frequency */ + u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL; + } + else + { + /* Wrong frequency request. Just return default setting. */ + /* Apply default PLL setting and return */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT; + } + else + { + CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Actual PLL output clock frequency */ + u32PllClk = CLK_GetPLLClockFreq(); + } + + return u32PllClk; +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2160000; + uint32_t u32Ret = 1U; + + while((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; + break; + } + } + return u32Ret; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_LLPD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_SPD0 + * - \ref CLK_PMUCTL_PDMSEL_SPD1 + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + * @note Must enable LIRC clock before entering to Standby Power-down Mode + */ + +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + /* Enable LIRC clock before entering to Standby Power-down Mode */ + if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)) + { + /* Enable LIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk; + + /* Wait for LIRC clock stable */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + } + + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode; +} + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin trigger type. + */ + +void CLK_EnableDPDWKPin(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType; +} + +/** + * @brief Get power manager wake up source + * + * @param[in] None + * @return None + * + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + +/** + * @brief Set specified GPIO as wake up source at Stand-by Power down mode + * + * @param[in] u32Port GPIO port. It could be 0~3. + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32TriggerType + * - \ref CLK_SPDWKPIN_RISING + * - \ref CLK_SPDWKPIN_FALLING + * @param[in] u32DebounceEn + * - \ref CLK_SPDWKPIN_DEBOUNCEEN + * - \ref CLK_SPDWKPIN_DEBOUNCEDIS + * @return None + * + * @details This function is used to set specified GPIO as wake up source + * at Stand-by Power down mode. + */ +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) +{ + uint32_t u32tmpAddr = 0UL; + uint32_t u32tmpVal = 0UL; + + /* GPx Stand-by Power-down Wake-up Pin Select */ + u32tmpAddr = (uint32_t)&CLK->PASWKCTL; + u32tmpAddr += (0x4UL * u32Port); + + u32tmpVal = inpw((uint32_t *)u32tmpAddr); + u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | + (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; + outpw((uint32_t *)u32tmpAddr, u32tmpVal); +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) + { + u32PllFreq = 0UL; /* PLL is in power down mode or fix low */ + } + else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) + { + if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + u32PllFreq = u32FIN; + } + else + { + if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL; + } + + return u32PllFreq; +} + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref RTC_MODULE + * - \ref I2S0_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32sel = 0; + uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC}; + + /* Get clock source selection setting */ + if(u32ModuleIdx == EPWM0_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos); + else if(u32ModuleIdx == EPWM1_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos); + else if(u32ModuleIdx == BPWM0_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); + else if(u32ModuleIdx == BPWM1_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); + else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Get clock source selection setting */ + return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + else + return 0; +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref EADC_MODULE + * - \ref SDH0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref EMAC_MODULE + * - \ref SDH1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32div = 0; + uint32_t u32DivTbl[4] = {0x0, 0x4, 0x8, 0x10}; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + else + return 0; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/crc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/crc.c new file mode 100644 index 0000000000..900ed3ba1e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/crc.c @@ -0,0 +1,94 @@ +/**************************************************************************//** + * @file crc.c + * @version V1.00 + * @brief M480 CRC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC->SEED = u32Seed; + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + CRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This macro gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + uint32_t ret; + + switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + ret = (CRC->CHECKSUM & 0xFFFFU); + break; + case CRC_32: + ret = (CRC->CHECKSUM); + break; + case CRC_8: + ret = (CRC->CHECKSUM & 0xFFU); + break; + default: + ret = 0U; + break; + } + + return ret; +} + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/crypto.c b/bsp/nuvoton_m487/libraries/StdDriver/src/crypto.c new file mode 100644 index 0000000000..34b8a1ed0f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/crypto.c @@ -0,0 +1,1990 @@ +/**************************************************************************//** + * @file crypto.c + * @version V1.10 + * @brief Cryptographic Accelerator driver source file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +/** @cond HIDDEN_SYMBOLS */ + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define CRPT_DBGMSG printf +#else +#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +static uint32_t g_AES_CTL[4]; +static uint32_t g_TDES_CTL[4]; + +static char hex_char_tbl[] = "0123456789abcdef"; + +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count); +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx); +static void Hex2Reg(char input[], uint32_t volatile reg[]); +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift); +static char ch2hex(char ch); +static int get_nibble_value(char c); + + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt Reference to Crypto module. + * @param[in] u32KeySize is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if (u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt Reference to Crypto module. + * @return None + */ +void PRNG_Start(CRPT_T *crpt) +{ + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt Reference to Crypto module. + * @param[out] u32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]) +{ + uint32_t i, wcnt; + + wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for (i = 0U; i < wcnt; i++) + { + u32RandKey[i] = crpt->PRNG_KEY[i]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + crpt->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + g_AES_CTL[u32Channel] = crpt->AES_CTL; +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start. + * @return None + */ +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode) +{ + crpt->AES_CTL = g_AES_CTL[u32Channel]; + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t i, wcnt, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL); + wcnt = 4UL + u32KeySize*2UL; + + for (i = 0U; i < wcnt; i++) + { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t i, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_IV[0] + (u32Channel * 0x3CUL); + + for (i = 0U; i < 4U; i++) + { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->AES0_SADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->AES0_DADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->AES0_CNT + (u32Channel * 0x3CUL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open TDES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32EncDec 1: TDES encode; 0: TDES decode + * @param[in] Is3DES 1: TDES; 0: DES + * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode + * @param[in] u32OpMode TDES operation mode, including: + * - \ref TDES_MODE_ECB + * - \ref TDES_MODE_CBC + * - \ref TDES_MODE_CFB + * - \ref TDES_MODE_OFB + * - \ref TDES_MODE_CTR + * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including: + * - \ref TDES_NO_SWAP + * - \ref TDES_WHL_SWAP + * - \ref TDES_OUT_SWAP + * - \ref TDES_OUT_WHL_SWAP + * - \ref TDES_IN_SWAP + * - \ref TDES_IN_WHL_SWAP + * - \ref TDES_IN_OUT_SWAP + * - \ref TDES_IN_OUT_WHL_SWAP + * @return None + */ +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, + uint32_t u32OpMode, uint32_t u32SwapType) +{ + g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) | + u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + if (Is3DES) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk; + } + if (Is3Key) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk; + } +} + +/** + * @brief Start TDES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start. + * @return None + */ +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos); + crpt->TDES_CTL = g_TDES_CTL[u32Channel]; +} + +/** + * @brief Set TDES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word. + * @return None + */ +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]) +{ + uint32_t i, reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_KEY1H + (0x40UL * u32Channel); + + for (i = 0U; i < 3U; i++) + { + outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */ + reg_addr += 4UL; + outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */ + reg_addr += 4UL; + } +} + +/** + * @brief Set TDES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32IVH TDES initial vector high word. + * @param[in] u32IVL TDES initial vector low word. + * @return None + */ +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_IVH + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVH); + + reg_addr = (uint32_t)&crpt->TDES0_IVL + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVL); +} + +/** + * @brief Set TDES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32SrcAddr TDES DMA source address + * @param[in] u32DstAddr TDES DMA destination address + * @param[in] u32TransCnt TDES DMA transfer byte count + * @return None + */ +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_SA + (u32Channel * 0x40UL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->TDES0_DA + (u32Channel * 0x40UL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->TDES0_CNT + (u32Channel * 0x40UL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open SHA encrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32OpMode SHA operation mode, including: + * - \ref SHA_MODE_SHA1 + * - \ref SHA_MODE_SHA224 + * - \ref SHA_MODE_SHA256 + * - \ref SHA_MODE_SHA384 + * - \ref SHA_MODE_SHA512 + * @param[in] u32SwapType is SHA input/output data swap control, including: + * - \ref SHA_NO_SWAP + * - \ref SHA_OUT_SWAP + * - \ref SHA_IN_SWAP + * - \ref SHA_IN_OUT_SWAP + * @param[in] hmac_key_len HMAC key byte count + * @return None + */ +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len) +{ + crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) | + (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos); + + if (hmac_key_len != 0UL) + { + crpt->HMAC_KEYCNT = hmac_key_len; + crpt->HMAC_CTL |= CRPT_HMAC_CTL_HMACEN_Msk; + } +} + +/** + * @brief Start SHA encrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt. + * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start. + * @return None + */ +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode) +{ + crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos); + crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos); +} + +/** + * @brief Set SHA DMA transfer + * @param[in] crpt Reference to Crypto module. + * @param[in] u32SrcAddr SHA DMA source address + * @param[in] u32TransCnt SHA DMA transfer byte count + * @return None + */ +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt) +{ + crpt->HMAC_SADDR = u32SrcAddr; + crpt->HMAC_DMACNT = u32TransCnt; +} + +/** + * @brief Read the SHA digest. + * @param[in] crpt Reference to Crypto module. + * @param[out] u32Digest The SHA encrypt output digest. + * @return None + */ +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]) +{ + uint32_t i, wcnt, reg_addr; + + i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; + + if (i == SHA_MODE_SHA1) + { + wcnt = 5UL; + } + else if (i == SHA_MODE_SHA224) + { + wcnt = 7UL; + } + else if (i == SHA_MODE_SHA256) + { + wcnt = 8UL; + } + else if (i == SHA_MODE_SHA384) + { + wcnt = 12UL; + } + else + { + /* SHA_MODE_SHA512 */ + wcnt = 16UL; + } + + reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]); + for (i = 0UL; i < wcnt; i++) + { + u32Digest[i] = inpw(reg_addr); + reg_addr += 4UL; + } +} + +/** @cond HIDDEN_SYMBOLS */ + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* ECC */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) + +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +enum +{ + CURVE_GF_P, + CURVE_GF_2M, +}; + +/*-----------------------------------------------------*/ +/* Define elliptic curve (EC): */ +/*-----------------------------------------------------*/ + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + +const ECC_CURVE _Curve[] = +{ + { + /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ + CURVE_P_192, + 48, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */ + "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1", + "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012", + "07192b95ffc8da78631011ed6b24cdd573f977a11e794811", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */ + CURVE_P_224, + 56, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */ + "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4", + "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21", + "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */ + 224, /* key_len */ + 9, + 8, + 3, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_P_256, + 64, /* Echar */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */ + "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b", + "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296", + "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5", + 78, /* Epl */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */ + 78, /* Eol */ + "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */ + CURVE_P_384, + 96, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef", + "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7", + "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f", + 116, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */ + 116, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */ + 384, /* key_len */ + 12, + 3, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/ + CURVE_P_521, + 131, /* Echar */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00", + "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66", + "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650", + 157, /* Epl */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */ + 157, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */ + 521, /* key_len */ + 32, + 32, + 32, + CURVE_GF_P + }, + { + /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */ + CURVE_B_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "20a601907b8c953ca1481eb10512f78744a3205fd", + "3f0eba16286a2d57ea0991168d4994637e8343e36", + "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */ + CURVE_B_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000001", + "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad", + "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b", + "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */ + CURVE_B_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000001", + "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5", + "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053", + "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */ + CURVE_B_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f", + "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7", + "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */ + CURVE_B_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a", + "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19", + "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */ + CURVE_K_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "00000000000000000000000000000000000000001", + "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8", + "289070fb05d38ff58321f2e800536d538ccdaa3d9", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */ + CURVE_K_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000001", + "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126", + "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */ + CURVE_K_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000001", + "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836", + "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */ + CURVE_K_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746", + "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */ + CURVE_K_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972", + "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_192, + 48, /* Echar */ + "00000000000000000000000000000000000000000", + "00000000000000000000000000000000000000003", + "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D", + "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37", /* p */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D", /* n */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_224, + 56, /* Echar */ + "00000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000005", + "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C", + "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D", /* p */ + 70, /* Eol */ + "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7", /* n */ + 224, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_256, + 64, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000007", + "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798", + "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8", + 78, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F", /* p */ + 78, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141", /* n */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP256r1 */ + CURVE_BP_256, + 64, /* Echar */ + "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9", /* A */ + "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6", /* B */ + "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262", /* x */ + "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997", /* y */ + 78, /* Epl */ + "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377", /* p */ + 78, /* Eol */ + "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7", /* q */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP384r1 */ + CURVE_BP_384, + 96, /* Echar */ + "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826", /* A */ + "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11", /* B */ + "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E", /* x */ + "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315", /* y */ + 116, /* Epl */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53", /* p */ + 116, /* Eol */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565", /* q */ + 384, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP512r1 */ + CURVE_BP_512, + 128, /* Echar */ + "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA", /* A */ + "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723", /* B */ + "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822", /* x */ + "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892", /* y */ + 156, /* Epl */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3", /* p */ + 156, /* Eol */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069", /* q */ + 512, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, +}; + +static ECC_CURVE *pCurve; +static ECC_CURVE Curve_Copy; + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve); +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve); +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode); + +static char temp_hex_str[160]; + + +#if ENABLE_DEBUG +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + int32_t i; + + printf("%s => ", str); + for (i = 0; i < count; i++) + { + printf("0x%08x ", regs[i]); + } + printf("\n"); +} +#else +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ +} +#endif + +static char ch2hex(char ch) +{ + if (ch <= '9') + { + ch = ch - '0'; + } + else if ((ch <= 'z') && (ch >= 'a')) + { + ch = ch - 'a' + 10U; + } + else + { + ch = ch - 'A' + 10U; + } + return ch; +} + +static void Hex2Reg(char input[], uint32_t volatile reg[]) +{ + char hex; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + + while (si >= 0) + { + val32 = 0UL; + for (i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = ch2hex(input[si]); + val32 |= (uint32_t)hex << (i * 4UL); + si--; + } + reg[ri++] = val32; + } +} + +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift) +{ + uint32_t hex, carry; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0L; + carry = 0UL; + while (si >= 0) + { + val32 = 0UL; + for (i = 0UL; (i < 8UL) && (si >= 0L); i++) + { + hex = (uint32_t)ch2hex(input[si]); + hex <<= shift; + + val32 |= (uint32_t)((hex & 0xFUL) | carry) << (i * 4UL); + carry = (hex >> 4UL) & 0xFUL; + si--; + } + reg[ri++] = val32; + } + if (carry != 0UL) + { + reg[ri] = carry; + } +} + +/** + * @brief Extract specified nibble from an unsigned word in character format. + * For example: + * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'. + * @param[in] val32 The input unsigned word + * @param[in] idx The Nth nibble to be extracted. + * @return The nibble in character format. + */ +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx) +{ + return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ]; +} + + +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]) +{ + int32_t idx, ri; + uint32_t i; + + output[count] = 0U; + idx = count - 1; + + for (ri = 0; idx >= 0; ri++) + { + for (i = 0UL; (i < 8UL) && (idx >= 0); i++) + { + output[idx] = get_Nth_nibble_char(reg[ri], i); + idx--; + } + } +} + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + uint32_t i; + ECC_CURVE *ret = NULL; + + for (i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) + { + if (ecc_curve == _Curve[i].curve_id) + { + memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE)); + ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */ + } + if (ret != NULL) + { + break; + } + } + return ret; +} + +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve) +{ + int32_t i, ret = 0; + + pCurve = get_curve(ecc_curve); + if (pCurve == NULL) + { + CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve); + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_A[i] = 0UL; + crpt->ECC_B[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_N[i] = 0UL; + } + + Hex2Reg(pCurve->Ea, crpt->ECC_A); + Hex2Reg(pCurve->Eb, crpt->ECC_B); + Hex2Reg(pCurve->Px, crpt->ECC_X1); + Hex2Reg(pCurve->Py, crpt->ECC_Y1); + + CRPT_DBGMSG("Key length = %d\n", pCurve->key_len); + dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10); + dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10); + dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10); + dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10); + + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_N[0] = 0x1UL; + crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32)); + crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32)); + crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32)); + crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32)); + } + else + { + Hex2Reg(pCurve->Pp, crpt->ECC_N); + } + } + dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10); + return ret; +} + +static int get_nibble_value(char c) +{ + if ((c >= '0') && (c <= '9')) + { + c = c - '0'; + } + + if ((c >= 'a') && (c <= 'f')) + { + c = c - 'a' + (char)10; + } + + if ((c >= 'A') && (c <= 'F')) + { + c = c - 'A' + (char)10; + } + return (int)c; +} + +static int ecc_strcmp(char *s1, char *s2) +{ + char c1, c2; + + while (*s1 == '0') s1++; + while (*s2 == '0') s2++; + + for ( ; *s1 || *s2; s1++, s2++) + { + if ((*s1 >= 'A') && (*s1 <= 'Z')) + c1 = *s1 + 32; + else + c1 = *s1; + + if ((*s2 >= 'A') && (*s2 <= 'Z')) + c2 = *s2 + 32; + else + c2 = *s2; + + if (c1 != c2) + return 1; + } + return 0; +} + +volatile uint32_t g_ECC_done, g_ECCERR_done; + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief ECC interrupt service routine. User application must invoke this function in + * his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done. + * @param[in] crpt Reference to Crypto module. + * @return none + */ +void ECC_Complete(CRPT_T *crpt) +{ + if (crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if (crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + /* printf("ECCERRIF is set!!\n"); */ + } +} + +/** + * @brief Check if the private key is located in valid range of curve. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k The input private key. + * @return 1 Is valid. + * @return 0 Is not valid. + * @return -1 Invalid curve. + */ +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]) +{ + uint32_t i; + int ret = -1; + + pCurve = get_curve(ecc_curve); + if (pCurve == NULL) + { + ret = -1; + } + + if (strlen(private_k) < strlen(pCurve->Eorder)) + { + ret = 1; + } + + if (strlen(private_k) > strlen(pCurve->Eorder)) + { + ret = 0; + } + + for (i = 0UL; i < strlen(private_k); i++) + { + if (get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) + { + ret = 1; + break; + } + if (get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i])) + { + ret = 0; + break; + } + } + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[in] private_k The input private key. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] public_k1 The output public key 1. + * @param[out] public_k2 The output public key 2. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(private_k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[out] x1 The x-coordinate of input point. + * @param[out] y1 The y-coordinate of input point. + * @param[in] k The private key + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] x2 The x-coordinate of output point. + * @param[out] y2 The y-coordinate of output point. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(x1, crpt->ECC_X1); + Hex2Reg(y1, crpt->ECC_Y1); + Hex2Reg(k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2); + } + + return ret; +} + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + if ((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) || + (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) + { + Hex2RegEx(private_k, crpt->ECC_K, 1); + } + else if ((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) || + (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) + { + Hex2RegEx(private_k, crpt->ECC_K, 2); + } + else + { + Hex2Reg(private_k, crpt->ECC_K); + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z); + } + + return ret; +} + +/** @cond HIDDEN_SYMBOLS */ + +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode) +{ + if ((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE) + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + else + { + if (pCurve->GF == (int)CURVE_GF_2M) + { + /* point */ + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk; + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + while (crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) + { + } +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *d, char *k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Write the random integer k to K register */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_K); + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* 3-(9) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + /* + * 4. Compute s = k ? 1 (e + d r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write 0x1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 4-(3) Write the random integer k to X1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(7) output = %s\n", temp_hex_str); +#endif + + /* 4-(8) Read X1 registers to get k^-1 */ + + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str); +#endif + + /* 4-(9) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(10) Write r, d to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + } + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(d, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(14) output = %s\n", temp_hex_str); +#endif + + /* 4-(15) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(16) Write e to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(20) output = %s\n", temp_hex_str); +#endif + + /* 4-(21) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(22) Write k^-1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(27) Read X1 registers to get s */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result2, S); + + } /* ret == 0 */ + + return ret; +} + +/** + * @brief ECDSA dogotal signature verification. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *public_k1, char *public_k2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + /* 3-(1) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e w (mod n) and u2 = r w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X (x1, y1) = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X(x1, y1) + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 (mod n) + * + * 6. The signature is valid if x1 = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for (i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* (10) Write u2 to K registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X(x1, y1) */ + for (i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if (ecc_strcmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/dac.c b/bsp/nuvoton_m487/libraries/StdDriver/src/dac.c new file mode 100644 index 0000000000..7a448596ea --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/dac.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * @brief M480 series DAC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger + * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, timer event, or EPWM event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac Base address of DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/eadc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/eadc.c new file mode 100644 index 0000000000..fa7c8d8c9d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/eadc.c @@ -0,0 +1,140 @@ +/**************************************************************************//** + * @file eadc.c + * @version V2.00 + * @brief M480 series EADC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL &= (~EADC_CTL_DIFFEN_Msk); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + while (!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {} +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module.. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger + * - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger + * - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger + * - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger + * - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger + * - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger + * - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger + * - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger + * - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger + * - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger + * - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger + * - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/ebi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/ebi.c new file mode 100644 index 0000000000..36aa0cea9b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/ebi.c @@ -0,0 +1,194 @@ +/**************************************************************************//** + * @file ebi.c + * @version V3.00 + * @brief M480 series External Bus Interface(EBI) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + if(u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch(u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index ); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/ecap.c b/bsp/nuvoton_m487/libraries/StdDriver/src/ecap.c new file mode 100644 index 0000000000..5287e6b3f9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/ecap.c @@ -0,0 +1,117 @@ +/**************************************************************************//** + * @file ecap.c + * @version V3.00 + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T* ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); + + /* Enable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_EnableIRQ((IRQn_Type)ECAP0_IRQn); + } + else + { + NVIC_EnableIRQ((IRQn_Type)ECAP1_IRQn); + } +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + ecap->CTL0 &= ~(u32Mask); + + /* Disable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_DisableIRQ((IRQn_Type)ECAP0_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)ECAP1_IRQn); + } +} + +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/emac.c b/bsp/nuvoton_m487/libraries/StdDriver/src/emac.c new file mode 100644 index 0000000000..73598f5cde --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/emac.c @@ -0,0 +1,985 @@ +/**************************************************************************//** + * @file emac.c + * @version V1.00 + * @brief M480 EMAC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EMAC_Driver EMAC Driver + @{ +*/ + + +/* Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ + +/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants + @{ +*/ + +/* PHY Register Description */ +#define PHY_CNTL_REG 0x00UL /*!< PHY control register address */ +#define PHY_STATUS_REG 0x01UL /*!< PHY status register address */ +#define PHY_ID1_REG 0x02UL /*!< PHY ID1 register */ +#define PHY_ID2_REG 0x03UL /*!< PHY ID2 register */ +#define PHY_ANA_REG 0x04UL /*!< PHY auto-negotiation advertisement register */ +#define PHY_ANLPA_REG 0x05UL /*!< PHY auto-negotiation link partner availability register */ +#define PHY_ANE_REG 0x06UL /*!< PHY auto-negotiation expansion register */ + +/* PHY Control Register */ +#define PHY_CNTL_RESET_PHY (1UL << 15UL) +#define PHY_CNTL_DR_100MB (1UL << 13UL) +#define PHY_CNTL_ENABLE_AN (1UL << 12UL) +#define PHY_CNTL_POWER_DOWN (1UL << 11UL) +#define PHY_CNTL_RESTART_AN (1UL << 9UL) +#define PHY_CNTL_FULLDUPLEX (1UL << 8UL) + +/* PHY Status Register */ +#define PHY_STATUS_AN_COMPLETE (1UL << 5UL) +#define PHY_STATUS_LINK_VALID (1UL << 2UL) + +/* PHY Auto-negotiation Advertisement Register */ +#define PHY_ANA_DR100_TX_FULL (1UL << 8UL) +#define PHY_ANA_DR100_TX_HALF (1UL << 7UL) +#define PHY_ANA_DR10_TX_FULL (1UL << 6UL) +#define PHY_ANA_DR10_TX_HALF (1UL << 5UL) +#define PHY_ANA_IEEE_802_3_CSMA_CD (1UL << 0UL) + +/* PHY Auto-negotiation Link Partner Advertisement Register */ +#define PHY_ANLPA_DR100_TX_FULL (1UL << 8UL) +#define PHY_ANLPA_DR100_TX_HALF (1UL << 7UL) +#define PHY_ANLPA_DR10_TX_FULL (1UL << 6UL) +#define PHY_ANLPA_DR10_TX_HALF (1UL << 5UL) + +/* EMAC Tx/Rx descriptor's owner bit */ +#define EMAC_DESC_OWN_EMAC 0x80000000UL /*!< Set owner to EMAC */ +#define EMAC_DESC_OWN_CPU 0x00000000UL /*!< Set owner to CPU */ + +/* Rx Frame Descriptor Status */ +#define EMAC_RXFD_RTSAS 0x0080UL /*!< Time Stamp Available */ +#define EMAC_RXFD_RP 0x0040UL /*!< Runt Packet */ +#define EMAC_RXFD_ALIE 0x0020UL /*!< Alignment Error */ +#define EMAC_RXFD_RXGD 0x0010UL /*!< Receiving Good packet received */ +#define EMAC_RXFD_PTLE 0x0008UL /*!< Packet Too Long Error */ +#define EMAC_RXFD_CRCE 0x0002UL /*!< CRC Error */ +#define EMAC_RXFD_RXINTR 0x0001UL /*!< Interrupt on receive */ + +/* Tx Frame Descriptor's Control bits */ +#define EMAC_TXFD_TTSEN 0x08UL /*!< Tx time stamp enable */ +#define EMAC_TXFD_INTEN 0x04UL /*!< Tx interrupt enable */ +#define EMAC_TXFD_CRCAPP 0x02UL /*!< Append CRC */ +#define EMAC_TXFD_PADEN 0x01UL /*!< Padding mode enable */ + +/* Tx Frame Descriptor Status */ +#define EMAC_TXFD_TXINTR 0x0001UL /*!< Interrupt on Transmit */ +#define EMAC_TXFD_DEF 0x0002UL /*!< Transmit deferred */ +#define EMAC_TXFD_TXCP 0x0008UL /*!< Transmission Completion */ +#define EMAC_TXFD_EXDEF 0x0010UL /*!< Exceed Deferral */ +#define EMAC_TXFD_NCS 0x0020UL /*!< No Carrier Sense Error */ +#define EMAC_TXFD_TXABT 0x0040UL /*!< Transmission Abort */ +#define EMAC_TXFD_LC 0x0080UL /*!< Late Collision */ +#define EMAC_TXFD_TXHA 0x0100UL /*!< Transmission halted */ +#define EMAC_TXFD_PAU 0x0200UL /*!< Paused */ +#define EMAC_TXFD_SQE 0x0400UL /*!< SQE error */ +#define EMAC_TXFD_TTSAS 0x0800UL /*!< Time Stamp available */ + +/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ + +/** @addtogroup EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines + @{ +*/ + +/** Tx/Rx buffer descriptor structure */ +typedef struct +{ + uint32_t u32Status1; /*!< Status word 1 */ + uint32_t u32Data; /*!< Pointer to data buffer */ + uint32_t u32Status2; /*!< Status word 2 */ + uint32_t u32Next; /*!< Pointer to next descriptor */ + uint32_t u32Backup1; /*!< For backup descriptor fields over written by time stamp */ + uint32_t u32Backup2; /*!< For backup descriptor fields over written by time stamp */ +} EMAC_DESCRIPTOR_T; + +/** Tx/Rx buffer structure */ +typedef struct +{ + uint8_t au8Buf[1520]; +} EMAC_FRAME_T; + +/*@}*/ /* end of group EMAC_EXPORTED_TYPEDEF */ + +/* local variables */ +static volatile EMAC_DESCRIPTOR_T rx_desc[EMAC_RX_DESC_SIZE]; +static volatile EMAC_FRAME_T rx_buf[EMAC_RX_DESC_SIZE]; +static volatile EMAC_DESCRIPTOR_T tx_desc[EMAC_TX_DESC_SIZE]; +static volatile EMAC_FRAME_T tx_buf[EMAC_TX_DESC_SIZE]; + + +static uint32_t u32CurrentTxDesc, u32NextTxDesc, u32CurrentRxDesc; +static uint32_t s_u32EnableTs = 0UL; + +static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data); +static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr); +static void EMAC_PhyInit(void); +static void EMAC_TxDescInit(void); +static void EMAC_RxDescInit(void); +static uint32_t EMAC_Subsec2Nsec(uint32_t subsec); +static uint32_t EMAC_Nsec2Subsec(uint32_t nsec); + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + +/** + * @brief Trigger EMAC Rx function + * @param None + * @return None + */ +#define EMAC_TRIGGER_RX() do{EMAC->RXST = 0UL;}while(0) + +/** + * @brief Trigger EMAC Tx function + * @param None + * @return None + */ +#define EMAC_TRIGGER_TX() do{EMAC->TXST = 0UL;}while(0) + + +/** + * @brief Write PHY register + * @param[in] u32Reg PHY register number + * @param[in] u32Addr PHY address, this address is board dependent + * @param[in] u32Data data to write to PHY register + * @return None + */ +static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data) +{ + /* Set data register */ + EMAC->MIIMDAT = u32Data ; + /* Set PHY address, PHY register address, busy bit and write bit */ + EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk; + /* Wait write complete by polling busy bit. */ + while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) + { + ; + } + +} + +/** + * @brief Read PHY register + * @param[in] u32Reg PHY register number + * @param[in] u32Addr PHY address, this address is board dependent + * @return Value read from PHY register + */ +static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr) +{ + /* Set PHY address, PHY register address, busy bit */ + EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk; + /* Wait read complete by polling busy bit */ + while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) + { + ; + } + /* Get return data */ + return EMAC->MIIMDAT; +} + +/** + * @brief Initialize PHY chip, check for the auto-negotiation result. + * @param None + * @return None + */ +static void EMAC_PhyInit(void) +{ + uint32_t reg; + uint32_t i = 0UL; + + /* Reset Phy Chip */ + EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY); + + /* Wait until reset complete */ + while (1) + { + reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ; + if ((reg & PHY_CNTL_RESET_PHY)==0UL) + { + break; + } + } + while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) + { + if(i++ > 80000UL) /* Cable not connected */ + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + break; + } + } + + if(i <= 80000UL) + { + /* Configure auto negotiation capability */ + EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL | + PHY_ANA_DR100_TX_HALF | + PHY_ANA_DR10_TX_FULL | + PHY_ANA_DR10_TX_HALF | + PHY_ANA_IEEE_802_3_CSMA_CD); + /* Restart auto negotiation */ + EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN); + + /* Wait for auto-negotiation complete */ + while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE)) + { + ; + } + /* Check link valid again. Some PHYs needs to check result after link valid bit set */ + while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) + { + ; + } + + /* Check link partner capability */ + reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ; + if (reg & PHY_ANLPA_DR100_TX_FULL) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + } + else if (reg & PHY_ANLPA_DR100_TX_HALF) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + } + else if (reg & PHY_ANLPA_DR10_TX_FULL) + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + } + else + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + } + } +} + +/** + * @brief Initial EMAC Tx descriptors and get Tx descriptor base address + * @param None + * @return None + */ +static void EMAC_TxDescInit(void) +{ + uint32_t i; + + /* Get Frame descriptor's base address. */ + EMAC->TXDSA = (uint32_t)&tx_desc[0]; + u32NextTxDesc = u32CurrentTxDesc = (uint32_t)&tx_desc[0]; + + for(i = 0UL; i < EMAC_TX_DESC_SIZE; i++) + { + + if(s_u32EnableTs) + { + tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN; + } + else + { + tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN; + } + tx_desc[i].u32Data = (uint32_t)((uint32_t)&tx_buf[i]); + tx_desc[i].u32Backup1 = tx_desc[i].u32Data; + tx_desc[i].u32Status2 = 0UL; + tx_desc[i].u32Next = (uint32_t)&tx_desc[(i + 1UL) % EMAC_TX_DESC_SIZE]; + tx_desc[i].u32Backup2 = tx_desc[i].u32Next; + + } + +} + + +/** + * @brief Initial EMAC Rx descriptors and get Rx descriptor base address + * @param None + * @return None + */ +static void EMAC_RxDescInit(void) +{ + + uint32_t i; + + /* Get Frame descriptor's base address. */ + EMAC->RXDSA = (uint32_t)&rx_desc[0]; + u32CurrentRxDesc = (uint32_t)&rx_desc[0]; + + for(i = 0UL; i < EMAC_RX_DESC_SIZE; i++) + { + rx_desc[i].u32Status1 = EMAC_DESC_OWN_EMAC; + rx_desc[i].u32Data = (uint32_t)((uint32_t)&rx_buf[i]); + rx_desc[i].u32Backup1 = rx_desc[i].u32Data; + rx_desc[i].u32Status2 = 0UL; + rx_desc[i].u32Next = (uint32_t)&rx_desc[(i + 1UL) % EMAC_RX_DESC_SIZE]; + rx_desc[i].u32Backup2 = rx_desc[i].u32Next; + } + +} + +/** + * @brief Convert subsecond value to nano second + * @param[in] subsec Subsecond value to be convert + * @return Nano second + */ +static uint32_t EMAC_Subsec2Nsec(uint32_t subsec) +{ + /* 2^31 subsec == 10^9 ns */ + uint64_t i; + i = 1000000000ull * (uint64_t)subsec; + i >>= 31; + return((uint32_t)i); +} + +/** + * @brief Convert nano second to subsecond value + * @param[in] nsec Nano second to be convert + * @return Subsecond + */ +static uint32_t EMAC_Nsec2Subsec(uint32_t nsec) +{ + /* 10^9 ns = 2^31 subsec */ + uint64_t i; + i = (1ull << 31) * nsec; + i /= 1000000000ull; + return((uint32_t)i); +} + + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + + + +/** @endcond HIDDEN_SYMBOLS */ + + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Initialize EMAC interface, including descriptors, MAC address, and PHY. + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with + * \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT + * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to + * enable receive and transmit function. + */ +void EMAC_Open(uint8_t *pu8MacAddr) +{ + /* Enable transmit and receive descriptor */ + EMAC_TxDescInit(); + EMAC_RxDescInit(); + + /* Set the CAM Control register and the MAC address value */ + EMAC_SetMacAddr(pu8MacAddr); + + /* Configure the MAC interrupt enable register. */ + EMAC->INTEN = EMAC_INTEN_RXIEN_Msk | + EMAC_INTEN_TXIEN_Msk | + EMAC_INTEN_RXGDIEN_Msk | + EMAC_INTEN_TXCPIEN_Msk | + EMAC_INTEN_RXBEIEN_Msk | + EMAC_INTEN_TXBEIEN_Msk | + EMAC_INTEN_RDUIEN_Msk | + EMAC_INTEN_TSALMIEN_Msk | + EMAC_INTEN_WOLIEN_Msk; + + /* Configure the MAC control register. */ + EMAC->CTL = EMAC_CTL_STRIPCRC_Msk | + EMAC_CTL_RMIIEN_Msk; + + /* Accept packets for us and all broadcast and multicast packets */ + EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | + EMAC_CAMCTL_AMP_Msk | + EMAC_CAMCTL_ABP_Msk; + + /* Limit the max receive frame length to 1514 + 4 */ + EMAC->MRFL = 1518; + EMAC_PhyInit(); +} + +/** + * @brief This function stop all receive and transmit activity and disable MAC interface + * @param None + * @return None + */ + +void EMAC_Close(void) +{ + EMAC->CTL |= EMAC_CTL_RST_Msk; + while(EMAC->CTL & EMAC_CTL_RST_Msk) {} +} + +/** + * @brief Set the device MAC address + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + */ +void EMAC_SetMacAddr(uint8_t *pu8MacAddr) +{ + EMAC_EnableCamEntry(0UL, pu8MacAddr); + +} + +/** + * @brief Fill a CAM entry for MAC address comparison. + * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it. + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + */ +void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]) +{ + uint32_t u32Lsw, u32Msw; + uint32_t reg; + u32Lsw = (uint32_t)(((uint32_t)pu8MacAddr[4] << 24) | + ((uint32_t)pu8MacAddr[5] << 16)); + u32Msw = (uint32_t)(((uint32_t)pu8MacAddr[0] << 24)| + ((uint32_t)pu8MacAddr[1] << 16)| + ((uint32_t)pu8MacAddr[2] << 8)| + (uint32_t)pu8MacAddr[3]); + + reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL; + *(uint32_t volatile *)reg = u32Msw; + reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL; + *(uint32_t volatile *)reg = u32Lsw; + + EMAC->CAMEN |= (1UL << u32Entry); +} + +/** + * @brief Disable a specified CAM entry + * @param[in] u32Entry CAM entry to be disabled + * @return None + */ +void EMAC_DisableCamEntry(uint32_t u32Entry) +{ + EMAC->CAMEN &= ~(1UL << u32Entry); +} + + +/** + * @brief Receive an Ethernet packet + * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed) + * @param[in] pu32Size Received packet size (without 4 byte CRC). + * @return Packet receive success or not + * @retval 0 No packet available for receive + * @retval 1 A packet is received + * @note Return 0 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + /* Clear Rx interrupt flags */ + reg = EMAC->INTSTS; + EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all RX related interrupt status */ + + if (reg & EMAC_INTSTS_RXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* If we reach last recv Rx descriptor, leave the loop */ + if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + + status = desc->u32Status1 >> 16; + + /* If Rx frame is good, process received frame */ + if(status & EMAC_RXFD_RXGD) + { + /* lower 16 bit in descriptor status1 stores the Rx packet length */ + *pu32Size = desc->u32Status1 & 0xFFFFUL; + memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size); + u32Count = 1UL; + } + else + { + /* Save Error status if necessary */ + if (status & EMAC_RXFD_RP) {} + if (status & EMAC_RXFD_ALIE) {} + if (status & EMAC_RXFD_PTLE) {} + if (status & EMAC_RXFD_CRCE) {} + } + } + } + return(u32Count); +} + +/** + * @brief Receive an Ethernet packet and the time stamp while it's received + * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed) + * @param[out] pu32Size Received packet size (without 4 byte CRC). + * @param[out] pu32Sec Second value while packet received + * @param[out] pu32Nsec Nano second value while packet received + * @return Packet receive success or not + * @retval 0 No packet available for receive + * @retval 1 A packet is received + * @note Return 0 doesn't guarantee the packet will be sent and received successfully. + * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give + * a buffer large enough to store such packet + */ +uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + /* Clear Rx interrupt flags */ + reg = EMAC->INTSTS; + EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */ + + if (reg & EMAC_INTSTS_RXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* If we reach last recv Rx descriptor, leave the loop */ + if(EMAC->CRXDSA != (uint32_t)desc) + { + if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + + status = desc->u32Status1 >> 16; + + /* If Rx frame is good, process received frame */ + if(status & EMAC_RXFD_RXGD) + { + /* lower 16 bit in descriptor status1 stores the Rx packet length */ + *pu32Size = desc->u32Status1 & 0xFFFFUL; + memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size); + + *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */ + *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */ + + u32Count = 1UL; + } + else + { + /* Save Error status if necessary */ + if (status & EMAC_RXFD_RP) {} + if (status & EMAC_RXFD_ALIE) {} + if (status & EMAC_RXFD_PTLE) {} + if (status & EMAC_RXFD_CRCE) {} + } + } + } + } + return(u32Count); +} + +/** + * @brief Clean up process after a packet is received + * @param None + * @return None + * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process + * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1 + */ +void EMAC_RecvPktDone(void) +{ + EMAC_DESCRIPTOR_T *desc; + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + + /* Get Next Frame Descriptor pointer to process */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Rx descriptor */ + u32CurrentRxDesc = (uint32_t)desc; + + /* Change ownership to DMA for next use */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + EMAC_TRIGGER_RX(); +} + + +/** + * @brief Send an Ethernet packet + * @param[in] pu8Data Pointer to a buffer holds the packet to transmit + * @param[in] u32Size Packet size (without 4 byte CRC). + * @return Packet transmit success or not + * @retval 0 Transmit failed due to descriptor unavailable. + * @retval 1 Packet is copied to descriptor and triggered to transmit. + * @note Return 1 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status; + uint32_t ret = 0UL; + /* Get Tx frame descriptor & data pointer */ + desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc; + + status = desc->u32Status1; + + /* Check descriptor ownership */ + if((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size); + + /* Set Tx descriptor transmit byte count */ + desc->u32Status2 = u32Size; + + /* Change descriptor ownership to EMAC */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + /* Get next Tx descriptor */ + u32NextTxDesc = (uint32_t)(desc->u32Next); + + /* Trigger EMAC to send the packet */ + EMAC_TRIGGER_TX(); + ret = 1UL; + } + return(ret); +} + + +/** + * @brief Clean up process after packet(s) are sent + * @param None + * @return Number of packet sent between two function calls + * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to + * release the resource use by transmit process + */ +uint32_t EMAC_SendPktDone(void) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t last_tx_desc; + uint32_t u32Count = 0UL; + + reg = EMAC->INTSTS; + /* Clear Tx interrupt flags */ + EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk); + + + if (reg & EMAC_INTSTS_TXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + /* Process the descriptor(s). */ + last_tx_desc = EMAC->CTXDSA ; + /* Get our first descriptor to process */ + desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc; + do + { + /* Descriptor ownership is still EMAC, so this packet haven't been send. */ + if(desc->u32Status1 & EMAC_DESC_OWN_EMAC) + { + break; + } + /* Get Tx status stored in descriptor */ + status = desc->u32Status2 >> 16UL; + if (status & EMAC_TXFD_TXCP) + { + u32Count++; + } + else + { + /* Do nothing here on error. */ + if (status & EMAC_TXFD_TXABT) {} + if (status & EMAC_TXFD_DEF) {} + if (status & EMAC_TXFD_PAU) {} + if (status & EMAC_TXFD_EXDEF) {} + if (status & EMAC_TXFD_NCS) {} + if (status & EMAC_TXFD_SQE) {} + if (status & EMAC_TXFD_LC) {} + if (status & EMAC_TXFD_TXHA) {} + } + + /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + /* go to next descriptor in link */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + } + while (last_tx_desc != (uint32_t)desc); /* If we reach last sent Tx descriptor, leave the loop */ + /* Save last processed Tx descriptor */ + u32CurrentTxDesc = (uint32_t)desc; + } + return(u32Count); +} + +/** + * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent + * @param[in] pu32Sec Second value while packet sent + * @param[in] pu32Nsec Nano second value while packet sent + * @return If a packet sent successfully + * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless + * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent + * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to + * release the resource use by transmit process + */ +uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + reg = EMAC->INTSTS; + /* Clear Tx interrupt flags */ + EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk); + + + if (reg & EMAC_INTSTS_TXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + /* Process the descriptor. + Get our first descriptor to process */ + desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc; + + /* Descriptor ownership is still EMAC, so this packet haven't been send. */ + if((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + /* Get Tx status stored in descriptor */ + status = desc->u32Status2 >> 16UL; + if (status & EMAC_TXFD_TXCP) + { + u32Count = 1UL; + *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */ + *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */ + } + else + { + /* Do nothing here on error. */ + if (status & EMAC_TXFD_TXABT) {} + if (status & EMAC_TXFD_DEF) {} + if (status & EMAC_TXFD_PAU) {} + if (status & EMAC_TXFD_EXDEF) {} + if (status & EMAC_TXFD_NCS) {} + if (status & EMAC_TXFD_SQE) {} + if (status & EMAC_TXFD_LC) {} + if (status & EMAC_TXFD_TXHA) {} + } + + /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + /* go to next descriptor in link */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Tx descriptor */ + u32CurrentTxDesc = (uint32_t)desc; + } + } + + return(u32Count); +} + +/** + * @brief Enable IEEE1588 time stamp function and set current time + * @param[in] u32Sec Second value + * @param[in] u32Nsec Nano second value + * @return None + */ +void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec) +{ + double f; + uint32_t reg; + EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; + EMAC->UPDSEC = u32Sec; /* Assume current time is 0 sec + 0 nano sec */ + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + + /* PTP source clock is 160MHz (Real chip using PLL). Each tick is 6.25ns + Assume we want to set each tick to 100ns. + Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7 + Addend register = 2^32 * tick_freq / (160MHz), where tick_freq = (2^31 / 215) MHz + From above equation, addend register = 2^63 / (160M * 215) ~= 268121280 = 0xFFB34C0 + So: + EMAC->TSIR = 0xD7; + EMAC->TSAR = 0x1E70C600; */ + f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5; + EMAC->TSINC = (reg = (uint32_t)f); + f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg); + EMAC->TSADDEND = (uint32_t)f; + EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine update */ +} + +/** + * @brief Disable IEEE1588 time stamp function + * @param None + * @return None + */ +void EMAC_DisableTS(void) +{ + EMAC->TSCTL = 0UL; +} + +/** + * @brief Get current time stamp + * @param[out] pu32Sec Current second value + * @param[out] pu32Nsec Current nano second value + * @return None + */ +void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + /* Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read. */ + *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC); + *pu32Sec = EMAC->TSSEC; +} + +/** + * @brief Set current time stamp + * @param[in] u32Sec Second value + * @param[in] u32Nsec Nano second value + * @return None + */ +void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec) +{ + /* Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk) */ + EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; + EMAC->UPDSEC = u32Sec; + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); + +} + +/** + * @brief Enable alarm function and set alarm time + * @param[in] u32Sec Second value to trigger alarm + * @param[in] u32Nsec Nano second value to trigger alarm + * @return None + */ +void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec) +{ + + EMAC->ALMSEC = u32Sec; + EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk; + +} + +/** + * @brief Disable alarm function + * @param None + * @return None + */ +void EMAC_DisableAlarm(void) +{ + + EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk; + +} + +/** + * @brief Add a offset to current time + * @param[in] u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0). + * @param[in] u32Sec Second value to add to current time + * @param[in] u32Nsec Nano second value to add to current time + * @return None + */ +void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec) +{ + EMAC->UPDSEC = u32Sec; + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + if(u32Neg) + { + EMAC->UPDSUBSEC |= BIT31; /* Set bit 31 indicates this is a negative value */ + } + EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk; + +} + +/** + * @brief Check Ethernet link status + * @param None + * @return Current link status, could be one of following value. + * - \ref EMAC_LINK_DOWN + * - \ref EMAC_LINK_100F + * - \ref EMAC_LINK_100H + * - \ref EMAC_LINK_10F + * - \ref EMAC_LINK_10H + * @note This API should be called regularly to sync EMAC setting with real connection status + */ +uint32_t EMAC_CheckLinkStatus(void) +{ + uint32_t reg, ret = EMAC_LINK_DOWN; + + /* Check link valid again */ + if(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID) + { + /* Check link partner capability */ + reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ; + if (reg & PHY_ANLPA_DR100_TX_FULL) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_100F; + } + else if (reg & PHY_ANLPA_DR100_TX_HALF) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_100H; + } + else if (reg & PHY_ANLPA_DR10_TX_FULL) + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_10F; + } + else + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_10H; + } + } + return ret; +} + + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EMAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/epwm.c b/bsp/nuvoton_m487/libraries/StdDriver/src/epwm.c new file mode 100644 index 0000000000..61cc2f30e6 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/epwm.c @@ -0,0 +1,1438 @@ +/**************************************************************************//** + * @file epwm.c + * @version V3.00 + * $Revision: 3 $ + * $Date: 16/06/23 11:14a $ + * @brief M480 series EPWM driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32EPWMClockSrc /= 1000U; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc)))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* every two channels share a prescaler */ + u16Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((1UL << EPWM_CTL1_CNTTYPE0_Pos) << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32EPWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32EPWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* every two channels share a prescaler */ + u32Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(((1UL << EPWM_CTL1_CNTTYPE0_Pos) << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum))); + + u32CNR -= 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~(((1UL << EPWM_WGCTL0_PRDPCTL0_Pos) | (1UL << EPWM_WGCTL0_ZPCTL0_Pos)) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~(((1UL << EPWM_WGCTL1_CMPDCTL0_Pos) | (1UL << EPWM_WGCTL1_CMPUCTL0_Pos)) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0U; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \ + EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @param[in] u32Condition The condition to trigger DAC. This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger DAC flag. + */ +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk; +} + +/** + * @brief Get selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @retval 0 The specified channel trigger DAC to start of conversion flag is not set + * @retval 1 The specified channel trigger DAC to start of conversion flag is set + * @details This function is used to get selected channel trigger DAC flag. + */ +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFU); + } + else + { + (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource; + } + } + + if(u32LevelMask & (1UL << i)) + { + if((i & 0x1U) == 0U) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if((i & 0x1U) == 0U) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1U; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk; + (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) ); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1U; + (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U))); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1U; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/fmc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/fmc.c new file mode 100644 index 0000000000..82ecac7560 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/fmc.c @@ -0,0 +1,847 @@ +/**************************************************************************//** + * @file fmc.c + * @version V1.00 + * @brief M480 series FMC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include + +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + + +/** + * @brief Disable FMC ISP function. + * @return None + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes. + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 4096 bytes aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t ret = 0; + + if (u32PageAddr == FMC_SPROM_BASE) + { + ret = FMC_Erase_SPROM(); + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes. + * @return SPROM page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_SPROM(void) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = FMC_SPROM_BASE; + FMC->ISPDAT = 0x0055AA03UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages. + * @param[in] u32BlockAddr Address of the flash block to be erased. + * It must be a 4 pages aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_Block(uint32_t u32BlockAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE; + FMC->ISPADDR = u32BlockAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block. + * @param[in] u32BankAddr Base address of the flash bank to be erased. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_Bank(uint32_t u32BankAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE; + FMC->ISPADDR = u32BankAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Get the current boot source. + * @return The current boot source. + * @retval 0 Is boot from APROM. + * @retval 1 Is boot from LDROM. + */ +int32_t FMC_GetBootSource (void) +{ + int32_t ret = 0; + + if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + ret = 1; + } + + return ret; +} + + +/** + * @brief Enable FMC ISP function + * @return None + */ +void FMC_Open(void) +{ + FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Execute FMC_ISPCMD_READ command to read a word from flash. + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * @return The word data read from specified flash address. + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = u32Addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + return FMC->ISPDAT; +} + + +/** + * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash. + * @param[in] u32addr Address of the flash location to be read. + * It must be a double-word aligned address. + * @param[out] u32data0 Place holder of word 0 read from flash address u32addr. + * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + */ +int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32data0 = FMC->MPDAT0; + *u32data1 = FMC->MPDAT1; + } + return ret; +} + + +/** + * @brief Get the base address of Data Flash if enabled. + * @retval The base address of Data Flash + */ +uint32_t FMC_ReadDataFlashBaseAddr(void) +{ + return FMC->DFBA; +} + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * @return None + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash. + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * @return None + */ +void FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash. + * @param[in] u32addr Address of the flash location to be programmed. + * It must be a double-word aligned address. + * @param[in] u32data0 The word data to be programmed to flash address u32addr. + * @param[in] u32data1 The word data to be programmed to flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + */ +int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64; + FMC->ISPADDR = u32addr; + FMC->MPDAT0 = u32data0; + FMC->MPDAT1 = u32data1; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + return ret; +} + + +/** + * @brief Program Multi-Word data into specified address of flash. + * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into. + * This address must be 8-bytes aligned to flash address. + * @param[in] pu32Buf Buffer that carry the data chunk. + * @param[in] u32Len Length of the data chunk in bytes. + * @retval >=0 Number of data bytes were programmed. + * @return -1 Invalid address. + */ +int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) +{ + int i, idx, retval = 0; + + if ((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) + { + return -1; + } + + u32Len = u32Len - (u32Len % 8); /* u32Len must be multiple of 8. */ + + idx = 0; + + while (u32Len >= 8) + { + FMC->ISPADDR = u32Addr; + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + for (i = 16; i < FMC_MULTI_WORD_PROG_LEN; ) + { + while (FMC->MPSTS & (FMC_MPSTS_D0_Msk | FMC_MPSTS_D1_Msk)) + ; + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D0D1 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + + if (i == FMC_MULTI_WORD_PROG_LEN/4) + break; // done + + while (FMC->MPSTS & (FMC_MPSTS_D2_Msk | FMC_MPSTS_D3_Msk)) + ; + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D2D3 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + } + + if (i != FMC_MULTI_WORD_PROG_LEN) + { + /* printf(" [WARNING] Multi-word program interrupted at 0x%x !!\n", i); */ + return retval; + } + + while (FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) ; + + u32Addr += FMC_MULTI_WORD_PROG_LEN; + } + return retval; +} + + +/** + * @brief Program a 64-bits data to the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Program failed. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL; + FMC->ISPDAT = low_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL; + FMC->ISPDAT = high_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Read the 64-bits data from the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Read failed. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *low_word = FMC->MPDAT0; + *high_word = FMC->MPDAT1; + } + } + return ret; +} + +/** + * @brief Lock the specified OTP. + * @param[in] otp_num The OTP number. + * @retval 0 Success + * @retval -1 Failed to write OTP lock bits. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Lock_OTP(uint32_t otp_num) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPDAT = 0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Check the OTP is locked or not. + * @param[in] otp_num The OTP number. + * @retval 1 OTP is locked. + * @retval 0 OTP is not locked. + * @retval -1 Failed to read OTP lock bits. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Is_OTP_Locked(uint32_t otp_num) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + if (FMC->ISPDAT != 0xFFFFFFFFUL) + { + ret = 1; /* Lock work was progrmmed. OTP was locked. */ + } + } + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_READ command to read User Configuration. + * @param[out] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Available word count in u32Config. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + + u32Config[0] = FMC_Read(FMC_CONFIG_BASE); + + if (u32Count < 2UL) + { + ret = -1; + } + else + { + u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL); + } + return ret; +} + + +/** + * @brief Execute ISP commands to erase then write User Configuration. + * @param[in] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Always be 2 in this BSP. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count) +{ + FMC_ENABLE_CFG_UPDATE(); + FMC_Erase(FMC_CONFIG_BASE); + FMC_Write(FMC_CONFIG_BASE, u32Config[0]); + FMC_Write(FMC_CONFIG_BASE+4UL, u32Config[1]); + FMC_DISABLE_CFG_UPDATE(); + return 0; +} + + +/** + * @brief Run CRC32 checksum calculation and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + + if ((u32addr % 512UL) || (u32count % 512UL)) + { + ret = 0xFFFFFFFF; + } + else + { + FMC->ISPCMD = FMC_ISPCMD_RUN_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + FMC->ISPCMD = FMC_ISPCMD_READ_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Run flash all one verification and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + + FMC->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + do + { + FMC->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + } + while (FMC->ISPDAT == 0UL); + + if (FMC->ISPDAT == READ_ALLONE_YES) + { + ret = FMC->ISPDAT; + } + + if (FMC->ISPDAT == READ_ALLONE_NOT) + { + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Setup security key. + * @param[in] key Key 0~2 to be setup. + * @param[in] kpmax Maximum unmatched power-on counting number. + * @param[in] kemax Maximum unmatched counting number. + * @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG. + * @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. + * @retval 0 Success. + * @retval -1 Key is locked. Cannot overwrite the current key. + * @retval -2 Failed to erase flash. + * @retval -3 Failed to program key. + * @retval -4 Key lock function failed. + * @retval -5 CONFIG lock function failed. + * @retval -6 SPROM lock function failed. + * @retval -7 KPMAX function failed. + * @retval -8 KEMAX function failed. + */ +int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, + const int32_t lock_CONFIG, const int32_t lock_SPROM) +{ + uint32_t lock_ctrl = 0UL; + uint32_t u32KeySts; + int32_t ret = 0; + + if (FMC->KPKEYSTS != 0x200UL) + { + ret = -1; + } + + if (FMC_Erase(FMC_KPROM_BASE)) + { + ret = -2; + } + + if (FMC_Erase(FMC_KPROM_BASE+0x200UL)) + { + ret = -3; + } + + if (!lock_CONFIG) + { + lock_ctrl |= 0x1UL; + } + + if (!lock_SPROM) + { + lock_ctrl |= 0x2UL; + } + + if (ret == 0) + { + FMC_Write(FMC_KPROM_BASE, key[0]); + FMC_Write(FMC_KPROM_BASE+0x4UL, key[1]); + FMC_Write(FMC_KPROM_BASE+0x8UL, key[2]); + FMC_Write(FMC_KPROM_BASE+0xCUL, kpmax); + FMC_Write(FMC_KPROM_BASE+0x10UL, kemax); + FMC_Write(FMC_KPROM_BASE+0x14UL, lock_ctrl); + + while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* Security key lock failed! */ + ret = -4; + } + else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) || + ((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -5; + } + else if ((lock_SPROM && (!(u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) || + ((!lock_SPROM) && (u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -6; + } + else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) + { + /* KPMAX failed! */ + ret = -7; + } + else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) + { + /* KEMAX failed! */ + ret = -8; + } + } + return ret; +} + + +/** + * @brief Execute security key comparison. + * @param[in] key Key 0~2 to be compared. + * @retval 0 Key matched. + * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count. + * @retval -2 Key mismatched. + * @retval -3 No security key lock. Key comparison is not required. + */ +int32_t FMC_CompareSPKey(uint32_t key[3]) +{ + uint32_t u32KeySts; + int32_t ret = 0; + + if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) + { + /* FMC_CompareSPKey - FORBID! */ + ret = -1; + } + + if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* FMC_CompareSPKey - key is not locked! */ + ret = -3; + } + + if (ret == 0) + { + FMC->KPKEY0 = key[0]; + FMC->KPKEY1 = key[1]; + FMC->KPKEY2 = key[2]; + FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk; + + while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) + { + /* Key mismatched! */ + ret = -2; + } + else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) + { + /* Key matched, but still be locked! */ + ret = -2; + } + } + return ret; +} + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/gpio.c b/bsp/nuvoton_m487/libraries/StdDriver/src/gpio.c new file mode 100644 index 0000000000..66adc59468 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/gpio.c @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * @brief M480 series GPIO driver source file + * + * @copyright (C) 2011~2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @param[in] u32Mode Operation mode. It could be \n + * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if((u32PinMask & (1ul << i))==(1ul << i)) + { + port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + port->INTTYPE = (port->INTTYPE&~(1ul<> 24) & 0xFFUL) << u32Pin); + port->INTEN = (port->INTEN&~(0x00010001ul<INTTYPE &= ~(1UL << u32Pin); + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * @param[in] u32Mode Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V) + * \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V) + * \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1ul << i)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * \ref GPIO_PUSEL_DISABLE + * \ref GPIO_PUSEL_PULL_UP + * \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1ul << i)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2011~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/hsusbd.c b/bsp/nuvoton_m487/libraries/StdDriver/src/hsusbd.c new file mode 100644 index 0000000000..37950014f9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/hsusbd.c @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file hsusbd.c + * @version V1.00 + * @brief M480 HSUSBD driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + + +/** @addtogroup HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions + @{ +*/ +/*--------------------------------------------------------------------------*/ +/** @cond HIDDEN_SYMBOLS */ +/* Global variables for Control Pipe */ +S_HSUSBD_CMD_T gUsbCmd; +S_HSUSBD_INFO_T *g_hsusbd_sInfo; + +HSUSBD_VENDOR_REQ g_hsusbd_pfnVendorRequest = NULL; +HSUSBD_CLASS_REQ g_hsusbd_pfnClassRequest = NULL; +HSUSBD_SET_INTERFACE_REQ g_hsusbd_pfnSetInterface = NULL; +uint32_t g_u32HsEpStallLock = 0ul; /* Bit map flag to lock specified EP when SET_FEATURE */ + +static uint8_t *g_hsusbd_CtrlInPointer = 0; +static uint32_t g_hsusbd_CtrlMaxPktSize = 64ul; +static uint8_t g_hsusbd_UsbConfig = 0ul; +static uint8_t g_hsusbd_UsbAltInterface = 0ul; +static uint8_t g_hsusbd_EnableTestMode = 0ul; +static uint8_t g_hsusbd_TestSelector = 0ul; + +#ifdef __ICCARM__ +#pragma data_alignment=4 +static uint8_t g_hsusbd_buf[12]; +#else +static uint8_t g_hsusbd_buf[12] __attribute__((aligned(4))); +#endif + +uint8_t g_hsusbd_Configured = 0ul; +uint8_t g_hsusbd_CtrlZero = 0ul; +uint8_t g_hsusbd_UsbAddr = 0ul; +uint8_t g_hsusbd_ShortPacket = 0ul; +uint32_t volatile g_hsusbd_DmaDone = 0ul; +uint32_t g_hsusbd_CtrlInSize = 0ul; +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief HSUSBD Initial + * + * @param[in] param Descriptor + * @param[in] pfnClassReq Class Request Callback Function + * @param[in] pfnSetInterface SetInterface Request Callback Function + * + * @return None + * + * @details This function is used to initial HSUSBD. + */ +void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface) +{ + g_hsusbd_sInfo = param; + g_hsusbd_pfnClassRequest = pfnClassReq; + g_hsusbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_hsusbd_CtrlMaxPktSize = g_hsusbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + /* Enable PHY */ + HSUSBD_ENABLE_PHY(); + /* wait PHY clock ready */ + while (1) + { + HSUSBD->EP[EPA].EPMPS = 0x20ul; + if (HSUSBD->EP[EPA].EPMPS == 0x20ul) + { + break; + } + } + /* Force SE0, and then clear it to connect*/ + HSUSBD_SET_SE0(); +} + +/** + * @brief HSUSBD Start + * + * @param[in] None + * + * @return None + * + * @details This function is used to start transfer + */ +void HSUSBD_Start(void) +{ + HSUSBD_CLR_SE0(); +} + +/** + * @brief Process Setup Packet + * + * @param[in] None + * + * @return None + * + * @details This function is used to process Setup packet. + */ +void HSUSBD_ProcessSetupPacket(void) +{ + /* Setup packet process */ + gUsbCmd.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0 & 0xfful); + gUsbCmd.bRequest = (uint8_t)((HSUSBD->SETUP1_0 >> 8) & 0xfful); + gUsbCmd.wValue = (uint16_t)HSUSBD->SETUP3_2; + gUsbCmd.wIndex = (uint16_t)HSUSBD->SETUP5_4; + gUsbCmd.wLength = (uint16_t)HSUSBD->SETUP7_6; + + /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */ + switch (gUsbCmd.bmRequestType & 0x60ul) + { + case REQ_STANDARD: + { + HSUSBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if (g_hsusbd_pfnClassRequest != NULL) + { + g_hsusbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if (g_hsusbd_pfnVendorRequest != NULL) + { + g_hsusbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } +} + +/** + * @brief Get Descriptor request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process GetDescriptor request. + */ +int HSUSBD_GetDescriptor(void) +{ + uint32_t u32Len; + int val = 0; + + u32Len = gUsbCmd.wLength; + g_hsusbd_CtrlZero = (uint8_t)0ul; + + switch ((gUsbCmd.wValue & 0xff00ul) >> 8) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = Minimum(u32Len, LEN_DEVICE); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8ConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FullConfigDesc, u32Len); + } + + break; + } + /* Get Qualifier Descriptor */ + case DESC_QUALIFIER: + { + u32Len = Minimum(u32Len, LEN_QUALIFIER); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8QualDesc, u32Len); + break; + } + /* Get Other Speed Descriptor - Full speed */ + case DESC_OTHERSPEED: + { + uint32_t u32TotalLen; + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HSOtherConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSOtherConfigDesc, u32Len); + } + + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + u32Len = Minimum(u32Len, LEN_HID); + HSUSBD_MemCopy(g_hsusbd_buf, &g_hsusbd_sInfo->gu8ConfigDesc[LEN_CONFIG+LEN_INTERFACE], u32Len); + HSUSBD_PrepareCtrlIn(g_hsusbd_buf, u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + if (u32Len > g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]) + { + u32Len = g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len); + } + else + { + if (u32Len > g_hsusbd_sInfo->gu32FSHidReportSize[gUsbCmd.wIndex & 0xfful]) + { + u32Len = g_hsusbd_sInfo->gu32FSHidReportSize[gUsbCmd.wIndex & 0xfful]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSHidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len); + } + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + if((gUsbCmd.wValue & 0xfful) < 8ul) + { + if (u32Len > g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]) + { + u32Len = g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful], u32Len); + } + else + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + } + break; + } + default: + /* Not support. Reply STALL. */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + break; + } + return val; +} + + +/** + * @brief Process USB standard request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process USB Standard Request. + */ +void HSUSBD_StandardRequest(void) +{ + /* clear global variables for new request */ + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + + if ((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch (gUsbCmd.bRequest) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_DESCRIPTOR: + { + if (!HSUSBD_GetDescriptor()) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + } + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_STATUS: + { + /* Device */ + if (gUsbCmd.bmRequestType == 0x80ul) + { + if ((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + g_hsusbd_buf[0] = (uint8_t)1ul; /* Self-Powered */ + } + else + { + g_hsusbd_buf[0] = (uint8_t)0ul; /* bus-Powered */ + } + } + /* Interface */ + else if (gUsbCmd.bmRequestType == 0x81ul) + { + g_hsusbd_buf[0] = (uint8_t)0ul; + } + /* Endpoint */ + else if (gUsbCmd.bmRequestType == 0x82ul) + { + uint8_t ep = (uint8_t)(gUsbCmd.wIndex & 0xFul); + g_hsusbd_buf[0] = (uint8_t)HSUSBD_GetStall((uint32_t)ep)? (uint8_t)1 : (uint8_t)0; + } + g_hsusbd_buf[1] = (uint8_t)0ul; + HSUSBD_PrepareCtrlIn(g_hsusbd_buf, 2ul); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } + else + { + /* Host to device */ + switch (gUsbCmd.bRequest) + { + case CLEAR_FEATURE: + { + if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT) + { + + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32HsEpStallLock is added to support it */ + epNum = (uint32_t)(gUsbCmd.wIndex & 0xFul); + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == epNum) && ((g_u32HsEpStallLock & (1ul << i)) == 0ul)) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xeful) | HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_ADDRESS: + { + g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue; + /* Status Stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_CONFIGURATION: + { + g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue; + g_hsusbd_Configured = (uint8_t)1ul; + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_FEATURE: + { + if ((gUsbCmd.wValue & 0x3ul) == 2ul) /* TEST_MODE */ + { + g_hsusbd_EnableTestMode = (uint8_t)1ul; + g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8); + } + if ((gUsbCmd.wValue & 0x3ul) == 3ul) /* HNP ebable */ + { + HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk); + } + + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_INTERFACE: + { + g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue; + if (g_hsusbd_pfnSetInterface != NULL) + { + g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface); + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } +} + +/** + * @brief Update Device State + * + * @param[in] None + * + * @return None + * + * @details This function is used to update Device state when Setup packet complete + */ +/** @cond HIDDEN_SYMBOLS */ +#define TEST_J 0x01ul +#define TEST_K 0x02ul +#define TEST_SE0_NAK 0x03ul +#define TEST_PACKET 0x04ul +#define TEST_FORCE_ENABLE 0x05ul +/** @endcond HIDDEN_SYMBOLS */ + +void HSUSBD_UpdateDeviceState(void) +{ + switch (gUsbCmd.bRequest) + { + case SET_ADDRESS: + { + HSUSBD_SET_ADDR(g_hsusbd_UsbAddr); + break; + } + case SET_CONFIGURATION: + { + if (g_hsusbd_UsbConfig == 0ul) + { + uint32_t volatile i; + /* Reset PID DATA0 */ + for (i=0ul; iEP[i].EPCFG & 0x1ul) == 0x1ul) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + break; + } + case SET_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_SetStall(idx); + } + else if (g_hsusbd_EnableTestMode) + { + g_hsusbd_EnableTestMode = (uint8_t)0ul; + if (g_hsusbd_TestSelector == TEST_J) + { + HSUSBD->TEST = TEST_J; + } + else if (g_hsusbd_TestSelector == TEST_K) + { + HSUSBD->TEST = TEST_K; + } + else if (g_hsusbd_TestSelector == TEST_SE0_NAK) + { + HSUSBD->TEST = TEST_SE0_NAK; + } + else if (g_hsusbd_TestSelector == TEST_PACKET) + { + HSUSBD->TEST = TEST_PACKET; + } + else if (g_hsusbd_TestSelector == TEST_FORCE_ENABLE) + { + HSUSBD->TEST = TEST_FORCE_ENABLE; + } + } + break; + } + case CLEAR_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_ClearStall(idx); + } + break; + } + default: + break; + } +} + + +/** + * @brief Prepare Control IN transaction + * + * @param[in] pu8Buf Control IN data pointer + * @param[in] u32Size IN transfer size + * + * @return None + * + * @details This function is used to prepare Control IN transfer + */ +void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + g_hsusbd_CtrlInPointer = pu8Buf; + g_hsusbd_CtrlInSize = u32Size; +} + + + +/** + * @brief Start Control IN transfer + * + * @param[in] None + * + * @return None + * + * @details This function is used to start Control IN + */ +void HSUSBD_CtrlIn(void) +{ + uint32_t volatile i, cnt; + uint8_t u8Value; + if(g_hsusbd_CtrlInSize >= g_hsusbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + cnt = g_hsusbd_CtrlMaxPktSize >> 2; + for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer = (uint8_t *)(g_hsusbd_CtrlInPointer + 4ul); + } + HSUSBD_START_CEP_IN(g_hsusbd_CtrlMaxPktSize); + g_hsusbd_CtrlInSize -= g_hsusbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + cnt = g_hsusbd_CtrlInSize >> 2; + for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer += 4ul; + } + + for (i=0ul; i<(g_hsusbd_CtrlInSize % 4ul); i++) + { + u8Value = *(uint8_t *)(g_hsusbd_CtrlInPointer+i); + outpb(&HSUSBD->CEPDAT, u8Value); + } + + HSUSBD_START_CEP_IN(g_hsusbd_CtrlInSize); + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + } +} + +/** + * @brief Start Control OUT transaction + * + * @param[in] pu8Buf Control OUT data pointer + * @param[in] u32Size OUT transfer size + * + * @return None + * + * @details This function is used to start Control OUT transfer + */ +void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t volatile i; + while(1) + { + if ((HSUSBD->CEPINTSTS & HSUSBD_CEPINTSTS_RXPKIF_Msk) == HSUSBD_CEPINTSTS_RXPKIF_Msk) + { + for (i=0ul; iCEPDAT); + } + HSUSBD->CEPINTSTS = HSUSBD_CEPINTSTS_RXPKIF_Msk; + break; + } + } +} + +/** + * @brief Clear all software flags + * + * @param[in] None + * + * @return None + * + * @details This function is used to clear all software control flag + */ +void HSUSBD_SwReset(void) +{ + /* Reset all variables for protocol */ + g_hsusbd_UsbAddr = (uint8_t)0ul; + g_hsusbd_DmaDone = 0ul; + g_hsusbd_ShortPacket = (uint8_t)0ul; + g_hsusbd_Configured = (uint8_t)0ul; + + /* Reset USB device address */ + HSUSBD_SET_ADDR(0ul); +} + +/** + * @brief HSUSBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set HSUSBD vendor request callback function + */ +void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq) +{ + g_hsusbd_pfnVendorRequest = pfnVendorReq; +} + + +/*@}*/ /* end of group HSUSBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSUSBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/i2c.c b/bsp/nuvoton_m487/libraries/StdDriver/src/i2c.c new file mode 100644 index 0000000000..ee937f56bd --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/i2c.c @@ -0,0 +1,1468 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * @brief M480 series I2C driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + + if(u8Start) + { + u32Reg |= I2C_CTL_STA; + } + + if(u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + + if(u8Si) + { + u32Reg |= I2C_CTL_SI; + } + + if(u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1U) << 2U)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + uint32_t u32Value; + + if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk) + { + u32Value = 1U; + } + else + { + u32Value = 0U; + } + + return u32Value; +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if(u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32Hclk_kHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32Hclk_kHz = u32Hclk / 1000U; + u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U; + if(u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + + I2C_START(i2c); + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < 1u) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/i2s.c b/bsp/nuvoton_m487/libraries/StdDriver/src/i2s.c new file mode 100644 index 0000000000..50d3c99c23 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/i2s.c @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file i2s.c + * @version V0.10 + * @brief M480 I2S driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s is the base address of I2S module. + * @return I2S source clock frequency (Hz). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq, u32ClkSrcSel; + + /* get I2S selection clock source */ + u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk; + + switch (u32ClkSrcSel) + { + case CLK_CLKSEL3_I2S0SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL3_I2S0SEL_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL3_I2S0SEL_PCLK0: + u32Freq = (uint32_t)CLK_GetPCLK0Freq(); + break; + + default: + u32Freq = __HIRC; + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData: Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat | I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + u32BitRate = u32SampleRate * (((u32WordWidth>>4U) & 0x3U) + 1U) * 16U; + //u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U; + u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U); + + /* calculate real sample rate */ + u32BitRate = u32SrcClk / (2U*((uint32_t)u16Divider+1U)); + u32SampleRate = u32BitRate / ((((u32WordWidth>>4U) & 0x3U) + 1U) * 16U); + + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function and I2S clock. + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief This function enables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief This function disables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable MCLK . + * @param[in] i2s is the base address of I2S module. + * @param[in] u32BusClock is the target MCLK clock + * @return Actual MCLK clock + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if (u32BusClock == u32SrcClk) + { + u8Divider = 0U; + } + else + { + u8Divider = (uint8_t)(u32SrcClk/u32BusClock) >> 1U; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if (u32Reg == 0U) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = ((u32SrcClk >> 1U) / u32Reg); + } + + return u32Clock; +} + +/** + * @brief Disable MCLK . + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos)); +} + + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos)); +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/pdma.c b/bsp/nuvoton_m487/libraries/StdDriver/src/pdma.c new file mode 100644 index 0000000000..f5ffa36178 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/pdma.c @@ -0,0 +1,444 @@ +/**************************************************************************//** + * @file pdma.c + * @version V1.00 + * @brief M480 series PDMA driver source file + * + * @copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +static uint8_t u32ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask) +{ + uint32_t i; + + for (i=0UL; iDSCT[i].CTL = 0UL; + u32ChSelect[i] = PDMA_MEM; + } + } + + pdma->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T * pdma) +{ + pdma->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->STRIDE[u32Ch].ASOCR =(u32DestLen<<16) | u32SrcLen; + pdma->STRIDE[u32Ch].STCR = u32TransCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + pdma->DSCT[u32Ch].SA = u32SrcAddr; + pdma->DSCT[u32Ch].DA = u32DstAddr; + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_ADC_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + u32ChSelect[u32Ch] = u32Peripheral; + switch(u32Ch) + { + case 0ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + case 1ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + case 2ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + case 3ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + case 4ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + case 5ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + case 6ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + case 7ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + case 8ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral; + break; + case 9ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos); + break; + case 10ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos); + break; + case 11ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos); + break; + case 12ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral; + break; + case 13ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos); + break; + case 14ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos); + break; + case 15ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos); + break; + default: + break; + } + + if(u32ScatterEn) + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + pdma->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA); + } + else + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + */ +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + pdma->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + */ +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + pdma->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel, + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + * @note M480 only supported channel 0/1. + */ +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch(u32Ch) + { + case 0ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + case 1ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + default: + break; + } +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch) +{ + if(u32ChSelect[u32Ch] == PDMA_MEM) + { + pdma->SWREQ = (1ul << u32Ch); + } + else {} +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN |= (1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN |= (1ul << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN &= ~(1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN &= ~(1ul << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2014~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/qei.c b/bsp/nuvoton_m487/libraries/StdDriver/src/qei.c new file mode 100644 index 0000000000..4a890fc5aa --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/qei.c @@ -0,0 +1,143 @@ +/**************************************************************************//** + * @file qei.c + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions + @{ +*/ + +/** + * @brief Close QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function reset QEI configuration and stop QEI counting. + */ +void QEI_Close(QEI_T* qei) +{ + /* Reset QEI configuration */ + qei->CTL = (uint32_t)0; +} + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable QEI specified interrupt. + */ +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Disable QEI specified interrupt */ + QEI_DISABLE_INT(qei, u32IntSel); + + /* Disable NVIC QEI IRQ */ + if(qei ==(QEI_T*)QEI0) + { + NVIC_DisableIRQ((IRQn_Type)QEI0_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)QEI1_IRQn); + } +} + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable QEI specified interrupt. + */ +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Enable QEI specified interrupt */ + QEI_ENABLE_INT(qei, u32IntSel); + + /* Enable NVIC QEI IRQ */ + if(qei == (QEI_T*)QEI0) + { + NVIC_EnableIRQ(QEI0_IRQn); + } + else + { + NVIC_EnableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Open QEI in specified mode and enable input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set QEI in specified mode and enable input. + */ +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set QEI function configuration */ + /* Set QEI counting mode */ + /* Enable IDX, QEA and QEB input to QEI controller */ + qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk); + + /* Set QEI maximum count value in in compare-counting mode */ + qei->CNTMAX = u32Value; +} + +/** + * @brief Start QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function enable QEI function and start QEI counting. + */ +void QEI_Start(QEI_T* qei) +{ + /* Enable QEI controller function */ + qei->CTL |= QEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function disable QEI function and stop QEI counting. + */ +void QEI_Stop(QEI_T* qei) +{ + /* Disable QEI controller function */ + qei->CTL &= (~QEI_CTL_QEIEN_Msk); +} + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/qspi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/qspi.c new file mode 100644 index 0000000000..d5bad7fb98 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/qspi.c @@ -0,0 +1,763 @@ +/**************************************************************************//** + * @file qspi.c + * @version V3.00 + * @brief M480 series QSPI driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + + /* Check clock source of QSPI */ + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0xFFU) + { + u32Div = 0xFFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will reset QSPI controller. + */ +void QSPI_Close(QSPI_T *qspi) +{ + /* Reset QSPI */ + SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + + /* Check clock source of SPI */ + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if(u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_QSPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk; + /* Check QSPIEN flag */ + if((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_QSPIEN_STS_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk; + /* Check QSPIx_SS line status */ + if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/rtc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/rtc.c new file mode 100644 index 0000000000..eca33dea8c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/rtc.c @@ -0,0 +1,1067 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * @brief M480 series RTC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIT = RTC_INIT_KEY; + + if(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + while(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + } + } + + if(sPt == 0) + { + } + else + { + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +} + +/** + * @brief Set Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512. + * + * @return None + * + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + uint64_t u64Compensate; + + u64Compensate = (uint64_t)(0x2710000000000); + u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000); + + if(u64Compensate >= (uint64_t)0x400000) + { + u64Compensate = (uint64_t)0x3FFFFF; + } + + RTC_WaitAccessEnable(); + RTC->FREQADJ = (uint32_t)u64Compensate; +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + RTC_WaitAccessEnable(); + g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + RTC_WaitAccessEnable(); + g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if(sPt == 0ul) + { + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((sPt->u32Month / 10ul) << 12); + u32RegCAL |= ((sPt->u32Month % 10ul) << 8); + u32RegCAL |= ((sPt->u32Day / 10ul) << 4); + u32RegCAL |= (sPt->u32Day % 10ul); + + u32RegTIME = ((sPt->u32Hour / 10ul) << 20); + u32RegTIME |= ((sPt->u32Hour % 10ul) << 16); + u32RegTIME |= ((sPt->u32Minute / 10ul) << 12); + u32RegTIME |= ((sPt->u32Minute % 10ul) << 8); + u32RegTIME |= ((sPt->u32Second / 10ul) << 4); + u32RegTIME |= (sPt->u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if(sPt == 0) + { + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((sPt->u32Month / 10ul) << 12); + u32RegCALM |= ((sPt->u32Month % 10ul) << 8); + u32RegCALM |= ((sPt->u32Day / 10ul) << 4); + u32RegCALM |= (sPt->u32Day % 10ul); + + u32RegTALM = ((sPt->u32Hour / 10ul) << 20); + u32RegTALM |= ((sPt->u32Hour % 10ul) << 16); + u32RegTALM |= ((sPt->u32Minute / 10ul) << 12); + u32RegTALM |= ((sPt->u32Minute % 10ul) << 8); + u32RegTALM |= ((sPt->u32Second / 10ul) << 4); + u32RegTALM |= (sPt->u32Second % 10ul); + + RTC_WaitAccessEnable(); + RTC->CALM = (uint32_t)u32RegCALM; + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((u32Month / 10ul) << 12); + u32RegCAL |= ((u32Month % 10ul) << 8); + u32RegCAL |= ((u32Day / 10ul) << 4); + u32RegCAL |= (u32Day % 10ul); + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTIME = ((u32Hour / 10ul) << 20); + u32RegTIME |= ((u32Hour % 10ul) << 16); + u32RegTIME |= ((u32Minute / 10ul) << 12); + u32RegTIME |= ((u32Minute % 10ul) << 8); + u32RegTIME |= ((u32Second / 10ul) << 4); + u32RegTIME |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((u32Month / 10ul) << 12); + u32RegCALM |= ((u32Month % 10ul) << 8); + u32RegCALM |= ((u32Day / 10ul) << 4); + u32RegCALM |= (u32Day % 10ul); + + RTC_WaitAccessEnable(); + + /* Set RTC Alarm Date */ + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTALM = ((u32Hour / 10ul) << 20); + u32RegTALM |= ((u32Hour % 10ul) << 16); + u32RegTALM |= ((u32Minute / 10ul) << 12); + u32RegTALM |= ((u32Minute % 10ul) << 8); + u32RegTALM |= ((u32Second / 10ul) << 4); + u32RegTALM |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + RTC_WaitAccessEnable(); + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + RTC_WaitAccessEnable(); + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC_WaitAccessEnable(); + + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC_WaitAccessEnable(); + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + RTC_WaitAccessEnable(); + RTC->INTEN &= ~u32IntFlagMask; + RTC_WaitAccessEnable(); + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~19 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) ); + + for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1ul << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul)); + u32Reg |= (u32TmpReg << (i*4ul)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1ul << i)) + { + u32Reg &= ~(u32TmpReg << (i*4ul)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | + RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + + for(i = 0ul; i < MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1ul << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul)); + u32Reg |= (u32TmpReg << (i*8ul)); + } + } + + if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void RTC_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0ul, u32Tamper4En = 0ul; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk; + } + + if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk; + } + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + + for(i = 0ul; i < MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1ul << i)) + { + u32Reg &= ~(u32TmpReg << ((i*8ul))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Config dynamic tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref RTC_2POW10_CLK + * - \ref RTC_2POW11_CLK + * - \ref RTC_2POW12_CLK + * - \ref RTC_2POW13_CLK + * - \ref RTC_2POW14_CLK + * - \ref RTC_2POW15_CLK + * - \ref RTC_2POW16_CLK + * - \ref RTC_2POW17_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref REF_RANDOM_PATTERN + * - \ref REF_PREVIOUS_PATTERN + * - \ref REF_SEED + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1ul) << RTC_TAMPCTL_SEEDRLD_Pos) | + ((u32RefPattern & 0x3ul) << RTC_TAMPCTL_DYNSRC_Pos); + + RTC_WaitAccessEnable(); + RTC->TAMPSEED = u32Seed; /* need set seed value before re-load seed */ + RTC->TAMPCTL = u32Reg; +} + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/sc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/sc.c new file mode 100644 index 0000000000..a03cddf5fb --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/sc.c @@ -0,0 +1,399 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief M480 Smartcard(SC) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief This function indicates specified smartcard slot status + * @param[in] sc Base address of smartcard module + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t ret; + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if((sc == SC0) && (u32CardStateIgnore[0] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if((sc == SC1) && (u32CardStateIgnore[1] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if((sc == SC2) && (u32CardStateIgnore[2] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if(cond1 != cond2) + { + ret = (uint32_t)FALSE; + } + else + { + ret = (uint32_t)TRUE; + } + return ret; +} + +/** + * @brief This function reset both transmit and receive FIFO of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ClearFIFO(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief This function disable specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + while(sc->PINCTL & SC_PINCTL_SYNC_Msk) + { + ; + } + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = 0UL; +} + +/** + * @brief This function initialized smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CardDet Card detect polarity, select the CD pin state which indicates card absent. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present + * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * @return None + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + if(u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL: SC_CTL_CDLV_Msk; + u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief This function reset specified smartcard module to its default state for activate smartcard + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL= 371UL; + + + /* Enable necessary interrupt for smartcard operation */ + if(u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_CDIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + return; +} + +/** + * @brief This function block guard time (BGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32 + * @return None + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief This function character guard time (CGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267 + * @return None + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL: 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief This function stop all smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + * @note This function stop the timers within smartcard module, \b not timer module + */ +void SC_StopAllTimer(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief This function configure and start a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs + * @return None + * @note This function start the timer within smartcard module, \b not timer module + * @note Depend on the timer operating mode, timer may not start counting immediately + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if(u32TimerNum == 0UL) + { + while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) + { + ; + } + sc->TMRCTL0 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) + { + ; + } + sc->TMRCTL1 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) + { + ; + } + sc->TMRCTL2 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function stop a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * @return None + * @note This function stop the timer within smartcard module, \b not timer module + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if(u32TimerNum == 0UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function gets smartcard clock frequency. + * @param[in] sc Base address of smartcard module + * @return Smartcard frequency in kHz + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if(sc == SC0) + { + u32Num = 0UL; + } + else if(sc == SC1) + { + u32Num = 1UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL) * 1000UL; + return u32Clk; +} + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/scuart.c b/bsp/nuvoton_m487/libraries/StdDriver/src/scuart.c new file mode 100644 index 0000000000..44a7890db5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/scuart.c @@ -0,0 +1,241 @@ +/**************************************************************************//** + * @file scuart.c + * @version V3.00 + * @brief M480 Smartcard UART mode (SCUART) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +static uint32_t SCUART_GetClock(SC_T *sc); + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief The function is used to disable smartcard interface UART mode. + * @param sc The base address of smartcard module. + * @return None + */ +void SCUART_Close(SC_T* sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; + +} +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief This function returns module clock of specified SC interface + * @param[in] sc The base address of smartcard module. + * @return Module clock of specified SC interface + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if(sc == SC0) + { + u32Num = 0UL; + } + else if(sc == SC1) + { + u32Num = 1UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL); + + + return u32Clk; +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief This function use to enable smartcard module UART mode and set baudrate. + * @param[in] sc The base address of smartcard module. + * @param[in] u32baudrate Target baudrate of smartcard module. + * @return Actual baudrate of smartcard mode + * @details This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL; + + /* Enable smartcard interface and stop bit = 1 */ + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; + /* Enable UART mode, disable parity and 8 bit per character */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; + sc->ETUCTL = u32Div; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief The function is used to read Rx data from RX FIFO. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data + * @param[in] u32ReadBytes Target number of characters to receive + * @return Actual character number reads to buffer + * @note This function does not block and return immediately if there's no data available + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc)) /* no data available */ + { + break; + } + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */ + } + + return u32Count; +} + +/** + * @brief This function use to configure smartcard UART mode line setting. + * @param[in] sc The base address of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * @return Actual baudrate of smartcard + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0UL) /* keep original baudrate setting */ + { + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL)/ u32Baudrate - 1UL; + sc->ETUCTL = u32Div; + } + /* Set stop bit */ + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; + /* Set character width and parity */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief This function use to set receive timeout count. + * @param[in] sc The base address of smartcard module. + * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable timeout counter + * @return None + * @details The time-out counter resets and starts counting whenever the RX buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RXTOUT= u32TOC; +} + + +/** + * @brief This function is to write data into transmit FIFO to send data out. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * @return None + * @note This function blocks until all data write into FIFO + */ +void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while(SCUART_GET_TX_FULL(sc)) + { + ; + } + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; + } +} + + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/sdh.c b/bsp/nuvoton_m487/libraries/StdDriver/src/sdh.c new file mode 100644 index 0000000000..5a807b698b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/sdh.c @@ -0,0 +1,1262 @@ +/**************************************************************************//** + * @file SDH.c + * @version V1.00 + * @brief M480 SDH driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ +#define SDH_BLOCK_SIZE 512ul + +/** @cond HIDDEN_SYMBOLS */ + +/* global variables */ +/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */ +/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */ +/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */ +uint8_t g_u8R3Flag = 0ul; +uint8_t volatile g_u8SDDataReadyFlag = FALSE; + +static uint32_t _SDH_uR7_CMD = 0ul; +static uint32_t _SDH_ReferenceClock; + +#ifdef __ICCARM__ +#pragma data_alignment = 4 +static uint8_t _SDH_ucSDHCBuffer[512]; +#else +static uint8_t _SDH_ucSDHCBuffer[512] __attribute__((aligned(4))); +#endif + +int SDH_ok = 0; + +SDH_INFO_T SD0, SD1; + +void SDH_CheckRB(SDH_T *sdh) +{ + while(1) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk) + { + break; + } + } +} + + +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf, val = 0ul; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) + { + if (pSD->IsCardInsert == 0ul) + { + val = SDH_NO_SD_CARD; + } + } + return val; +} + + +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); + sdh->CTL = buf; + + if (ntickCount > 0ul) + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if(ntickCount-- == 0ul) + { + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ + return 2ul; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + else + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + + if (_SDH_uR7_CMD) + { + uint32_t tmp0 = 0ul, tmp1= 0ul; + tmp1 = sdh->RESP1 & 0xfful; + tmp0 = sdh->RESP0 & 0xful; + if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul)) + { + _SDH_uR7_CMD = 0ul; + return SDH_CMD8_ERROR; + } + } + + if (!g_u8R3Flag) + { + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } + } + else + { + /* ignore CRC error for R3 case */ + g_u8R3Flag = 0ul; + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return Successful; + } +} + + +uint32_t SDH_Swap32(uint32_t val) +{ + uint32_t buf; + + buf = val; + val <<= 24; + val |= (buf<<8) & 0xff0000ul; + val |= (buf>>8) & 0xff00ul; + val |= (buf>>24)& 0xfful; + return val; +} + +/* Get 16 bytes CID or CSD */ +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[]) +{ + uint32_t i, buf; + uint32_t tmpBuf[5]; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) + { + for (i=0ul; i<5ul; i++) + { + tmpBuf[i] = SDH_Swap32(sdh->FB[i]); + } + for (i=0ul; i<4ul; i++) + { + puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful)<<8) | ((tmpBuf[i+1ul] & 0xff000000ul)>>24); + } + } + else + { + return SDH_CRC7_ERROR; + } + return Successful; +} + + +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)| + (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) + { + /* check CRC7 */ + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) + { + /* check CRC16 */ + return SDH_CRC16_ERROR; + } + return 0ul; +} + +/* there are 8 bits for divider0, maximum is 256 */ +#define SDH_CLK_DIV0_MAX 256ul + +void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz) +{ + uint32_t rate, div1; + static uint32_t u32SD_ClkSrc = 0ul, u32SD_PwrCtl = 0ul; + + SYS_UnlockReg(); + + /* initial state, clock source use HIRC */ + if (sd_clock_khz <= 400ul) + { + u32SD_PwrCtl = CLK->PWRCTL; + if ((u32SD_PwrCtl & CLK_PWRCTL_HIRCEN_Msk) != 0x4ul) + { + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + } + + if (sdh == SDH0) + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC; + } + else + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC; + } + _SDH_ReferenceClock = (__HIRC / 1000ul); + } + /* transfer state, clock source use sys_init() */ + else + { + CLK->PWRCTL = u32SD_PwrCtl; + if (sdh == SDH0) + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) + { + _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) + { + _SDH_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_PLL) + { + _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) + { + _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HXT) + { + _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HIRC) + { + _SDH_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_PLL) + { + _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HCLK) + { + _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + + if(sd_clock_khz >= 50000ul) + { + sd_clock_khz = 50000ul; + } + } + rate = _SDH_ReferenceClock / sd_clock_khz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if ((_SDH_ReferenceClock % sd_clock_khz) != 0ul) + { + rate++; + } + + if(rate >= SDH_CLK_DIV0_MAX) + { + rate = SDH_CLK_DIV0_MAX; + } + + /*--- calculate the second divider CLKDIV0[SDHOST_N]*/ + div1 = (rate - 1ul) & 0xFFul; + + /*--- setup register */ + if (sdh == SDH0) + { + CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; + CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos); + } + else + { + CLK->CLKDIV3 &= ~CLK_CLKDIV3_SDH1DIV_Msk; + CLK->CLKDIV3 |= (div1 << CLK_CLKDIV3_SDH1DIV_Pos); + } + return; +} + +uint32_t SDH_CardDetection(SDH_T *sdh) +{ + uint32_t i, val = TRUE; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + + if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card remove */ + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + else + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + } + else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for(i= 0ul; i < 5000ul; i++) + { + } + + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card insert */ + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + else + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return val; +} + +uint32_t SDH_Init(SDH_T *sdh) +{ + uint32_t volatile i, status; + uint32_t resp; + uint32_t CIDBuffer[4]; + uint32_t volatile u32CmdTimeOut; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + /* set the clock to 300KHz */ + SDH_Set_clock(sdh, 300ul); + + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x1000ul; i>0ul; i--) + { + } + + /* initial SDHC */ + _SDH_uR7_CMD = 1ul; + u32CmdTimeOut = 0xFFFFFul; + + i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut); + if (i == Successful) + { + /* SD 2.0 */ + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */ + resp = sdh->RESP0; + + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + } + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_SD_HIGH; + } + else + { + pSD->CardType = SDH_TYPE_SD_LOW; + } + } + else + { + /* SD 1.1 */ + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x100ul; i>0ul; i--) + { + } + + i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + if (i == 2ul) /* MMC memory */ + { + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset */ + for (i=0x100ul; i>0ul; i--) + { + } + + g_u8R3Flag = 1ul; + + if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) /* eMMC memory */ + { + resp = sdh->RESP0; + while ((resp & 0x00800000ul) != 0x00800000ul) + { + /* check if card is ready */ + g_u8R3Flag = 1ul; + + SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut); /* high voltage */ + resp = sdh->RESP0; + } + + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_EMMC; + } + else + { + pSD->CardType = SDH_TYPE_MMC; + } + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_ERR_DEVICE; + } + } + else if (i == 0ul) /* SD Memory */ + { + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + } + pSD->CardType = SDH_TYPE_SD_LOW; + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_INIT_ERROR; + } + } + + if (pSD->CardType != SDH_TYPE_UNKNOWN) + { + SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer); + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful) /* set RCA */ + { + return status; + } + pSD->RCA = 0x10000ul; + } + else + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful) /* get RCA */ + { + return status; + } + else + { + pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000; + } + } + } + return Successful; +} + + +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD) +{ + uint32_t volatile status=0ul; + uint16_t current_comsumption, busy_status0; + + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 63ul; + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful) + { + return Fail; + } + + current_comsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8; + current_comsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if (!current_comsumption) + { + return Fail; + } + + busy_status0 = (uint16_t)_SDH_ucSDHCBuffer[28] << 8; + busy_status0 |= (uint16_t)_SDH_ucSDHCBuffer[29]; + + if (!busy_status0) /* function ready */ + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 63ul; /* 512 bit */ + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful) + { + return Fail; + } + + /* function change timing: 8 clocks */ + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + current_comsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8; + current_comsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if (!current_comsumption) + { + return Fail; + } + + return Successful; + } + else + { + return Fail; + } +} + + +uint32_t SDH_SelectCardType(SDH_T *sdh) +{ + uint32_t volatile status=0ul; + uint32_t param; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* if SD card set 4bit */ + if (pSD->CardType == SDH_TYPE_SD_HIGH) + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 0x07ul; /* 64 bit */ + sdh->DMACTL |= SDH_DMACTL_DMARST_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2); + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + if ((_SDH_ucSDHCBuffer[0] & 0xful) == 0x2ul) + { + status = SDH_SwitchToHighSpeed(sdh, pSD); + if (status == Successful) + { + /* divider */ + SDH_Set_clock(sdh, SDHC_FREQ); + } + } + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) /* set bus width */ + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if (pSD->CardType == SDH_TYPE_SD_LOW) + { + sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer; + sdh->BLEN = 0x07ul; + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */ + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if ((pSD->CardType == SDH_TYPE_MMC) ||(pSD->CardType == SDH_TYPE_EMMC)) + { + + if(pSD->CardType == SDH_TYPE_MMC) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + + /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */ + /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */ + param = (3ul << 24) | (183ul << 16) | (1ul << 8); + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */ + + } + + if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful) + { + return status; + } + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk; + + return Successful; +} + +void SDH_Get_SD_info(SDH_T *sdh) +{ + unsigned int R_LEN, C_Size, MULT, size; + uint32_t Buffer[4]; + //unsigned char *ptr; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer); + + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + /* for MMC/eMMC card */ + if ((Buffer[0] & 0xc0000000) == 0xc0000000) + { + /* CSD_STRUCTURE [127:126] is 3 */ + /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */ + SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul); + + //ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer ); + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 511ul; /* read 512 bytes for EXT_CSD */ + + if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful) + { + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + pSD->totalSectorN = (uint32_t)_SDH_ucSDHCBuffer[215]<<24; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[214]<<16; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[213]<<8; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[212]; + pSD->diskSize = pSD->totalSectorN / 2ul; + } + } + else + { + /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */ + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + else + { + if ((Buffer[0] & 0xc0000000) != 0x0ul) + { + C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16); + size = (C_Size+1ul) * 512ul; /* Kbytes */ + + pSD->diskSize = size; + pSD->totalSectorN = size << 1; + } + else + { + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + pSD->sectorSize = (int)512; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief This function use to reset SD function and select card detection source and pin. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3) + * + * @return None + */ +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc) +{ + sdh->DMACTL = SDH_DMACTL_DMARST_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) + { + } + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + + sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; + while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk) + { + } + + if (sdh == SDH0) + { + NVIC_EnableIRQ(SDH0_IRQn); + memset(&SD0, 0, sizeof(SDH_INFO_T)); + } + else if (sdh == SDH1) + { + NVIC_EnableIRQ(SDH1_IRQn); + memset(&SD1, 0, sizeof(SDH_INFO_T)); + } + else + { + } + + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3) + { + sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk; + } + else + { + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + } + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; + while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk) + { + } +} + +/** + * @brief This function use to initial SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return None + * + * @details This function is used to initial SD card. + * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source. + * And then switch back to the user's setting. + */ +uint32_t SDH_Probe(SDH_T *sdh) +{ + uint32_t val; + + sdh->GINTEN = 0ul; + sdh->CTL &= ~SDH_CTL_SDNWR_Msk; + sdh->CTL |= 0x09ul << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */ + sdh->CTL &= ~SDH_CTL_BLKCNT_Msk; + sdh->CTL |= 0x01ul << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */ + sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */ + + if(!(SDH_CardDetection(sdh))) + { + return SDH_NO_SD_CARD; + } + + if ((val = SDH_Init(sdh)) != 0ul) + { + return val; + } + + /* divider */ + if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC)) + { + SDH_Set_clock(sdh, MMC_FREQ); + } + else + { + SDH_Set_clock(sdh, SD_FREQ); + } + SDH_Get_SD_info(sdh); + + if ((val = SDH_SelectCardType(sdh)) != 0ul) + { + return val; + } + + SDH_ok = 1; + return 0ul; +} + +/** + * @brief This function use to read data from SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[out] pu8BufAddr The buffer to receive the data from SD card. + * @param[in] u32StartSec The start read sector address. + * @param[in] u32SecCount The the read sector number of data + * + * @return None + */ +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE, buf; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + uint32_t blksize = SDH_BLOCK_SIZE; + + SDH_INFO_T *pSD; + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->BLEN = blksize - 1ul; /* the actual byte count is equal to (SDBLEN+1) */ + + if ( (pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC) ) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * blksize; + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + + loop = u32SecCount / 255ul; + for (i=0ul; iCTL & ~SDH_CTL_CMDCODE_Msk; + reg = reg | 0xff0000ul; /* set BLK_CNT to 255 */ + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(g_u8SDDataReadyFlag) + { + break; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk); + reg = reg & (~SDH_CTL_BLKCNT_Msk); + reg |= (loop << 16); /* setup SDCR_BLKCNT */ + + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + return Successful; +} + + +/** + * @brief This function use to write data to SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] pu8BufAddr The buffer to send the data to SD card. + * @param[in] u32StartSec The start write sector address. + * @param[in] u32SecCount The the write sector number of data. + * + * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n + * \ref SDH_NO_SD_CARD : SD card be removed. \n + * \ref SDH_CRC_ERROR : CRC error happen. \n + * \ref SDH_CRC7_ERROR : CRC7 error happen. \n + * \ref Successful : Write data to SD card success. + */ +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */ + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */ + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + loop = u32SecCount / 255ul; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */ + for (i=0ul; iCTL & 0xff00c080; + reg = reg | 0xff0000ul; /* set BLK_CNT to 0xFF=255 */ + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + reg = (sdh->CTL & 0xff00c080) | (loop << 16); + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + return Successful; +} + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + + + + + + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/spi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/spi.c new file mode 100644 index 0000000000..b011552618 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/spi.c @@ -0,0 +1,1442 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * @brief M480 series SPI driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if(spi == SPI2) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0xFFU) + { + u32Div = 0xFFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI2) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if(spi == SPI0) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(spi == SPI1) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(spi == SPI2) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + /* Reset SPI */ + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + else if(spi == SPI1) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + else if(spi == SPI2) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + else + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_BUSY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk; + /* Check SPIEN flag */ + if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk; + /* Check SPIx_SS line status */ + if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[27:26]). + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if(i2s == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if(i2s == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32Freq = CLK_GetPCLK0Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if(i2s == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32Freq = CLK_GetPCLK0Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + + /* Reset SPI/I2S */ + if(i2s == SPI0) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(i2s == SPI1) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(i2s == SPI2) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2; + + if(u32MasterSlave == SPI_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U; + u32Divider = ((u32SrcClk / u32BitRate) >> 1U) - 1U; + //u32Divider = ((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + + if(i2s == SPI0) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(i2s == SPI1) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(i2s == SPI2) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u32Divider = 0U; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1U; + /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */ + if(u32Divider > 0x3FU) + { + u32Divider = 0x3FU; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if(u32Divider == 0U) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/spim.c b/bsp/nuvoton_m487/libraries/StdDriver/src/spim.c new file mode 100644 index 0000000000..33fb1c6492 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/spim.c @@ -0,0 +1,1278 @@ +/**************************************************************************//** + * @file spim.c + * @version V1.00 + * @brief M480 series SPIM driver + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/** @cond HIDDEN_SYMBOLS */ + + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define SPIM_DBGMSG printf +#else +#define SPIM_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +static volatile uint8_t g_Supported_List[] = +{ + MFGID_WINBOND, + MFGID_MXIC, + MFGID_EON, + MFGID_ISSI, + MFGID_SPANSION +}; + +static void N_delay(int n); +static void SwitchNBitOutput(uint32_t u32NBit); +static void SwitchNBitInput(uint32_t u32NBit); +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx); +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx); +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static int spim_is_write_done(uint32_t u32NBit); +static int spim_wait_write_done(uint32_t u32NBit); +static void spim_set_write_enable(int isEn, uint32_t u32NBit); +static void spim_enable_spansion_quad_mode(int isEn); +static void spim_eon_set_qpi_mode(int isEn); +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit); +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync); +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync); + + +static void N_delay(int n) +{ + while (n-- > 0) + { + __NOP(); + } +} + +static void SwitchNBitOutput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */ + break; + + default: + break; + } +} + +static void SwitchNBitInput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */ + break; + + default: + break; + } +} + + +/** + * @brief Write data to SPI slave. + * @param pu8TxBuf Transmit buffer. + * @param u32NTx Number of bytes to transmit. + * @return None. + */ +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx) +{ + uint32_t buf_idx = 0UL; + + while (u32NTx) + { + uint32_t dataNum = 0UL, dataNum2; + + if (u32NTx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NTx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NTx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NTx >= 4UL) + { + dataNum = 1UL; + } + + dataNum2 = dataNum; + while (dataNum2) + { + uint32_t tmp; + + memcpy(&tmp, &pu8TxBuf[buf_idx], 4U); + buf_idx += 4UL; + u32NTx -= 4UL; + + dataNum2 --; + /* *((__O uint32_t *) &SPIM->TX0 + dataNum2) = tmp; */ + SPIM->TX[dataNum2] = tmp; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + + if (u32NTx && (u32NTx < 4UL)) + { + uint32_t rnm, tmp; + + rnm = u32NTx; + memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx); + buf_idx += u32NTx; + u32NTx = 0UL; + SPIM->TX[0] = tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(rnm * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + } +} + +/** + * @brief Read data from SPI slave. + * @param pu8TxBuf Receive buffer. + * @param u32NRx Size of receive buffer in bytes. + * @return None. + */ +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx) +{ + uint32_t buf_idx = 0UL; + + while (u32NRx) + { + uint32_t dataNum = 0UL; /* number of words */ + + if (u32NRx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NRx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NRx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NRx >= 4UL) + { + dataNum = 1UL; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + + while (dataNum) + { + uint32_t tmp; + + tmp = SPIM->RX[dataNum-1UL]; + memcpy(&pu8RxBuf[buf_idx], &tmp, 4U); + buf_idx += 4UL; + dataNum --; + u32NRx -= 4UL; + } + + if (u32NRx && (u32NRx < 4UL)) + { + uint32_t tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(u32NRx * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + + tmp = SPIM->RX[0]; + memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx); + buf_idx += u32NRx; + u32NRx = 0UL; + } + } +} + +/** + * @brief Issue Read Status Register #1 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Write Status Register #1 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U}; /* 1-byte Write Status Register #1 command + 1-byte data. */ + + cmdBuf[1] = dataBuf[0]; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Read Status Register #2 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR2}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Winbond Write Status Register command. This command write both Status Register-1 + * and Status Register-2. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U}; + + cmdBuf[1] = dataBuf[0]; + cmdBuf[2] = dataBuf[1]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Status Register #3 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Status Register #3 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR3}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Security Register command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Security Register command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSCUR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Check if Erase/Write is done. + * @return 0: Not done. 1: Done. + */ +static int spim_is_write_done(uint32_t u32NBit) +{ + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), u32NBit); + return ! (status[0] & SR_WIP); +} + +/** + * @brief Wait until Erase/Write done. + * @param u32NBit N-bit transmit/receive. + * @return 0 SPIM write done. + */ +static int spim_wait_write_done(uint32_t u32NBit) +{ + uint32_t count; + int ret = -1; + + for (count = 0UL; count < SystemCoreClock/1000UL; count++) + { + if (spim_is_write_done(u32NBit)) + { + ret = 0; + break; + } + } + if (ret != 0) + { + SPIM_DBGMSG("spim_wait_write_done time-out!!\n"); + } + return -1; +} + +/** + * @brief Issue Write Enable/disable command. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void spim_set_write_enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {0U}; /* 1-byte Write Enable command. */ + cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Get SPIM serial clock. + * @return SPI serial clock. + * @details This function calculates the serial clock of SPI in Hz. + */ +uint32_t SPIM_GetSClkFreq(void) +{ + uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER(); + + return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock; +} + +/** + * @brief Initialize SPIM flash. + * @param clrWP Clear Write Protect or not. + * @return 0 Success. + * @return -1 Unrecognized manufacture ID or failed on reading manufacture ID. + */ +int SPIM_InitFlash(int clrWP) +{ + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; + uint32_t i; + int32_t ret = -1; + + SPIM_SET_SS_ACTLVL(0); + + /* + * Because not sure in SPI or QPI mode, do QPI reset and then SPI reset. + */ + /* QPI Reset Enable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* QPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI ResetEnable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (clrWP) + { + uint8_t dataBuf[] = {0x00U}; + + spim_set_write_enable(1, 1UL); /* Clear Block Protect. */ + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U); + spim_wait_write_done(1UL); + } + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), 1UL); + + /* printf("ID: 0x%x, 0x%x, px%x\n", idBuf[0], idBuf[1], idBuf[2]); */ + + for (i = 0UL; i < sizeof(g_Supported_List)/sizeof(g_Supported_List[0]); i++) + { + if (idBuf[0] == g_Supported_List[i]) + { + ret = 0; + } + } + if (ret != 0) + { + SPIM_DBGMSG("Flash initialize failed!! 0x%x\n", idBuf[0]); + } + return ret; +} + +/** + * @brief Issue JEDEC ID command. + * @param idBuf ID buffer. + * @param u32NRx Size of ID buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = { OPCODE_RDID }; /* 1-byte JEDEC ID command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(idBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +static void spim_enable_spansion_quad_mode(int isEn) +{ + uint8_t cmdBuf[3]; + uint8_t dataBuf[1], status1; + + cmdBuf[0] = 0x5U; /* Read Status Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */ + + status1 = dataBuf[0]; + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + + spim_set_write_enable(1, 1UL); + + cmdBuf[0] = 0x1U; /* Write register */ + cmdBuf[1] = status1; + + if (isEn) + { + cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */ + } + else + { + cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */ + } + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 3UL); + SPIM_SET_SS_EN(0); + + spim_set_write_enable(0, 1UL); + + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + N_delay(10000); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Set Quad Enable/disable. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit) +{ + uint8_t idBuf[3]; + uint8_t dataBuf[2]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]); + + switch (idBuf[0]) + { + case MFGID_WINBOND: /* Winbond SPI flash */ + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + if (isEn) + { + dataBuf[1] |= SR2_QE; + } + else + { + dataBuf[1] &= ~SR2_QE; + } + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + break; + + case MFGID_MXIC: /* MXIC SPI flash. */ + case MFGID_EON: + case MFGID_ISSI: /* ISSI SPI flash. */ + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + dataBuf[0] = isEn ? SR_QE : 0U; + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + break; + + case MFGID_SPANSION: + spim_enable_spansion_quad_mode(isEn); + break; + + default: + break; + } +} + +/** + * @brief Enter/exit QPI mode. + * @param isEn Enable/disable. + * @return None. + */ +static void spim_eon_set_qpi_mode(int isEn) +{ + uint8_t cmdBuf[1]; /* 1-byte command. */ + + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); + + if (isEn) /* Assume in SPI mode. */ + { + cmdBuf[0] = OPCODE_ENQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + else /* Assume in QPI mode. */ + { + cmdBuf[0] = OPCODE_EXQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(4UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); +} + + +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[2]; + uint8_t dataBuf[1]; + + cmdBuf[0] = OPCODE_BRRD; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, 1UL); + SwitchNBitInput(1UL); + spim_read(dataBuf, 1UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]); + + cmdBuf[0] = OPCODE_BRWR; + + if (isEn) + { + cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */ + } + else + { + cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */ + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 2UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Query 4-byte address mode enabled or not. + * @param u32NBit N-bit transmit/receive. + * @return 0: 4-byte address mode disabled. 1: 4-byte address mode enabled. + */ +int SPIM_Is4ByteModeEnable(uint32_t u32NBit) +{ + int isEn = 0; + int isSupt = 0; + uint8_t idBuf[3]; + uint8_t dataBuf[1]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + default: + break; + } + + if (isSupt != 0) + { + if (idBuf[0] == MFGID_WINBOND) + { + /* Winbond SPI flash. */ + SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SR3_ADR); + } + else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON)) + { + /* MXIC/EON SPI flash. */ + SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SCUR_4BYTE); + } + } + + return isEn; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief Enter/Exit 4-byte address mode. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return 0 success + * -1 failed + */ +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit) +{ + int isSupt = 0L, ret = -1; + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; /* 1-byte Enter/Exit 4-Byte Mode command. */ + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + case MFGID_SPANSION: + SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit); + isSupt = 1L; + ret = 0L; + break; + + default: + break; + } + + if ((isSupt) && (idBuf[0] != MFGID_SPANSION)) + { + cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* + * FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which + * doesn't match spec(MX25L25635E), so skip the check below. + */ + if (idBuf[0] != MFGID_MXIC) + { + if (isEn) + { + while (! SPIM_Is4ByteModeEnable(u32NBit)) { } + } + else + { + while (SPIM_Is4ByteModeEnable(u32NBit)) { } + } + } + ret = 0; + } + return ret; +} + +/** + * @brief Erase whole chip. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_ChipErase(uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE }; /* 1-byte Chip Erase command. */ + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + +/** + * @brief Erase one block. + * @param u32Addr Block to erase which contains the u32Addr. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u8ErsCmd Erase command. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx = 0UL; + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + cmdBuf[buf_idx++] = u8ErsCmd; + + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, buf_idx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Write data in the same page by I/O mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + spim_set_write_enable(1, u32NBitCmd); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + + SwitchNBitOutput(u32NBitCmd); + cmdBuf[0] = wrCmd; + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + SwitchNBitOutput(u32NBitDat); + spim_write(pu8TxBuf, u32NTx); /* Write out data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBitCmd); + } +} + +/** + * @brief Write data in the same page by Page Write mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync) +{ + if ((wrCmd == CMD_QUAD_PAGE_PROGRAM_WINBOND) || + (wrCmd == CMD_QUAD_PAGE_PROGRAM_MXIC)) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + } + else if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + spim_eon_set_qpi_mode(1); /* Enter QPI mode. */ + } + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */ + SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8TxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NTx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE(); + } + + if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + spim_eon_set_qpi_mode(0); /* Exit QPI mode. */ + } +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Write data to SPI Flash by sending commands manually (I/O mode). + * @param u32Addr: Start u32Address to write. + * @param is4ByteAddr: 4-byte u32Address or not. + * @param u32NTx: Number of bytes to write. + * @param pu8TxBuf: Transmit buffer. + * @param wrCmd: Write command. + * @param u32NBitCmd: N-bit transmit command. + * @param u32NBitAddr: N-bit transmit u32Address. + * @param u32NBitDat: N-bit transmit/receive data. + * @return None. + */ +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) /* Do all the bytes fit onto one page ? */ + { + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by sending commands manually (I/O mode). + * @param u32Addr Start u32Address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param rdCmd Read command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param u32NDummy Number of dummy bytes following address. + * @return None. + */ +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + SPIM_SET_SS_EN(1); /* CS activated. */ + + cmdBuf[0] = rdCmd; + SwitchNBitOutput(u32NBitCmd); + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + buf_idx = 0UL; + while (u32NDummy --) + { + cmdBuf[buf_idx++] = 0x00U; + } + + /* Same bit mode as above. */ + spim_write(cmdBuf, buf_idx); /* Write out dummy bytes. */ + + SwitchNBitInput(u32NBitDat); + spim_read(pu8RxBuf, u32NRx); /* Read back data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Write data to SPI Flash by Page Write mode. + * @param u32Addr Start address to write. + * @param is4ByteAddr 4-byte address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @return None. + */ +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) + { + /* Do all the bytes fit onto one page ? */ + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by Page Read mode. + * @param u32Addr Start address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param u32RdCmd Read command. + * @param isSync Block or not. + * @return None. + */ +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], + uint32_t u32RdCmd, int isSync) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8RxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NRx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE(); /* Wait for DMA done. */ + } +} + +/** + * @brief Enter Direct Map mode. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32RdCmd Read command. + * @param u32IdleIntvl Idle interval. + * @return None. + */ +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl) +{ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */ +} + +/** + * @brief Exit Direct Map mode. + * @return None. + */ +void SPIM_ExitDirectMapMode(void) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */ +} + + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/sys.c b/bsp/nuvoton_m487/libraries/StdDriver/src/sys.c new file mode 100644 index 0000000000..f0347d6749 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/sys.c @@ -0,0 +1,255 @@ +/**************************************************************************//** + * @file sys.c + * @version V1.00 + * @brief M480 series SYS driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS |= u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BODVL setting or BODEN is 0. + * @retval 1 System voltage is lower than BODVL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return SYS->REGLCTL & 1UL ? 0UL : 1UL; +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA_RST + * - \ref EBI_RST + * - \ref EMAC_RST + * - \ref SDH0_RST + * - \ref CRC_RST + * - \ref HSUSBD_RST + * - \ref CRPT_RST + * - \ref SPIM_RST + * - \ref USBH_RST + * - \ref SDH1_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref ACMP01_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref CAN0_RST + * - \ref CAN1_RST + * - \ref USBD_RST + * - \ref EADC_RST + * - \ref I2S0_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * - \ref SPI3_RST + * - \ref USCI0_RST + * - \ref USCI1_RST + * - \ref DAC_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref QEI0_RST + * - \ref QEI1_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * - \ref OPA_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(uint32_t *)u32tmpAddr |= u32tmpVal; + + /* Release corresponding module from reset state */ + u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; + + /* Enable Brown-out interrupt or reset function */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode; + + /* Select Brown-out Detector threshold voltage */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel; +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 + * - \ref SYS_PLCTL_PLSEL_PL1 + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + /* Set power voltage level */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); +} + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/timer.c b/bsp/nuvoton_m487/libraries/StdDriver/src/timer.c new file mode 100644 index 0000000000..e5fbd9ef35 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/timer.c @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file timer.c + * @brief M480 Timer Controller(Timer) driver source file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return(u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */ + for(; delay > 0UL; delay--) + { + __NOP(); + } + + while(timer->CTL & TIMER_CTL_ACTSTS_Msk) + { + ; + } +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32Clk; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; + } + else if(timer == TIMER1) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; + } + else if(timer == TIMER2) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; + } + else /* Timer 3 */ + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1)) + { + u32Clk = CLK_GetPCLK0Freq(); + } + else + { + u32Clk = CLK_GetPCLK1Freq(); + } + } + else + { + u32Clk = au32Clk[u32Src]; + } + + return u32Clk; +} + + + +/** + * @brief This function is used to enable the Timer frequency counter function + * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2 + * @param[in] u32DropCount This parameter has no effect in M480 series BSP + * @param[in] u32Timeout This parameter has no effect in M480 series BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * @return None + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; /* store the timer base to configure compare value */ + + t = (timer == TIMER0) ? TIMER1 : TIMER3; + + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + + return; +} +/** + * @brief This function is used to disable the Timer frequency counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + + +/** + * @brief This function is used to select the interrupt source used to trigger other modules. + * @param[in] timer The base address of Timer module + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * @return None + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief This function is used to set modules trigger by timer interrupt + * @param[in] timer The base address of Timer module + * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_TRG_TO_EPWM, + * - \ref TIMER_TRG_TO_EADC, + * - \ref TIMER_TRG_TO_DAC, and + * - \ref TIMER_TRG_TO_PDMA + * @return None + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/timer_pwm.c b/bsp/nuvoton_m487/libraries/StdDriver/src/timer_pwm.c new file mode 100644 index 0000000000..5ae3a7ee5c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/timer_pwm.c @@ -0,0 +1,442 @@ +/**************************************************************************//** + * @file timer_pwm.c + * @brief M480 Timer PWM Controller(Timer PWM) driver source file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate u16PERIOD and u16PSC */ + for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if(u32Period <= 0x10000UL) + { + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE; + + /* Convert to real register value */ + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + if(u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMEADCTS = 0x0UL; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource))? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable load mode of selected channel + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + + +/** + * @brief Enable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable PWM brake pin inverse function. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable PWM brake pin inverse function. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set brake pin source + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @return None + * @details This function is used to set PWM brake pin source. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/uart.c b/bsp/nuvoton_m487/libraries/StdDriver/src/uart.c new file mode 100644 index 0000000000..c54982fa6f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/uart.c @@ -0,0 +1,656 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * @brief M480 series UART driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + + if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk; + uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + else + { + } + + if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + + if(uart==(UART_T*)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==(UART_T*)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==(UART_T*)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==(UART_T*)UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==(UART_T*)UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==(UART_T*)UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; + +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + + if(uart==(UART_T*)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==(UART_T*)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==(UART_T*)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==(UART_T*)UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==(UART_T*)UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==(UART_T*)UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + else + { + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + + if(uart==UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + else + { + } + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate); + + if(u32Baud_Div < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + else + { + } + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The break field length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0ul) /* Wait Tx empty and Time-out manner */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; + +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usbd.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usbd.c new file mode 100644 index 0000000000..15f9b7392f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usbd.c @@ -0,0 +1,729 @@ +/**************************************************************************//** + * @file usbd.c + * @version V1.00 + * @brief M480 USBD driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_usbd_SetupPacket[8] = {0ul}; /*!< Setup packet buffer */ +volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static uint8_t *g_usbd_CtrlInPointer = 0; +static uint8_t *g_usbd_CtrlOutPointer = 0; +static volatile uint32_t g_usbd_CtrlInSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul; +static volatile uint32_t g_usbd_UsbAddr = 0ul; +static volatile uint32_t g_usbd_UsbConfig = 0ul; +static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul; +static volatile uint32_t g_usbd_UsbAltInterface = 0ul; +static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul; +/** + * @endcond + */ + +const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_usbd_sInfo = param; + g_usbd_pfnClassRequest = pfnClassReq; + g_usbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + USBD->ATTR = 0x6D0ul; + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + USBD->ATTR = 0x7D0ul; + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul); + + /* Check the request type */ + switch(g_usbd_SetupPacket[0] & 0x60ul) + { + case REQ_STANDARD: + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if(g_usbd_pfnClassRequest != NULL) + { + g_usbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if(g_usbd_pfnVendorRequest != NULL) + { + g_usbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + u32Len = 0ul; + u32Len = g_usbd_SetupPacket[7]; + u32Len <<= 8ul; + u32Len += g_usbd_SetupPacket[6]; + + switch(g_usbd_SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len); + + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len); + + break; + } + + /* Get BOS Descriptor */ + case DESC_BOS: + { + u32Len = USBD_Minimum(u32Len, LEN_BOS+LEN_BOSCAP); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len); + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = USBD_Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if (u32Len > g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]) + { + u32Len = g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if(g_usbd_SetupPacket[2] < 4ul) + { + if (u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]) + { + u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len); + + + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + default: + /* Not support. Reply STALL.*/ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + uint32_t addr; + /* clear global variables for new request */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + + if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch(g_usbd_SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0ul); /* For status stage */ + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_STATUS: + { + /* Device */ + if(g_usbd_SetupPacket[0] == 0x80ul) + { + uint8_t u8Tmp; + + u8Tmp = (uint8_t)0ul; + if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/ + } + if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul) + { + u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */ + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = u8Tmp; + + } + /* Interface */ + else if(g_usbd_SetupPacket[0] == 0x81ul) + { + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)0ul; + } + /* Endpoint */ + else if(g_usbd_SetupPacket[0] == 0x82ul) + { + uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul); + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul; + M8(addr) = (uint8_t)0ul; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + /* Host to device */ + switch(g_usbd_SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + for(i = 0ul; i < USBD_MAX_EP; i++) + { + if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul)) + { + USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + } + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)0; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_ADDRESS: + { + g_usbd_UsbAddr = g_usbd_SetupPacket[2]; + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + case SET_CONFIGURATION: + { + g_usbd_UsbConfig = g_usbd_SetupPacket[2]; + + if(g_usbd_pfnSetConfigCallback) + { + g_usbd_pfnSetConfigCallback(); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_FEATURE: + { + if( (g_usbd_SetupPacket[0] & 0xFul) == 0ul ) /* 0: device */ + { + if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) /* 3: HNP enable */ + { + OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); + } + } + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul)); + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)1ul; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + case SET_INTERFACE: + { + g_usbd_UsbAltInterface = g_usbd_SetupPacket[2]; + if(g_usbd_pfnSetInterface != NULL) + { + g_usbd_pfnSetInterface(g_usbd_UsbAltInterface); + } + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t addr; + if(u32Size > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + } + else + { + /* Data size <= MXPLD */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + uint32_t addr; + + if(g_usbd_CtrlInSize) + { + /* Process remained data */ + if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize); + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + } + } + else + { + /* In ACK for Set address */ + if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) + { + addr = USBD_GET_ADDR(); + if((addr != g_usbd_UsbAddr) && (addr == 0ul)) + { + USBD_SET_ADDR(g_usbd_UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_usbd_CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + } + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_usbd_CtrlOutPointer = pu8Buf; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + uint32_t addr; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1); + USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size); + g_usbd_CtrlOutPointer += u32Size; + g_usbd_CtrlOutSize += u32Size; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } + + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i; + + /* Reset all variables for protocol */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + g_usbd_CtrlOutPointer = 0; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = 0ul; + g_u32EpStallLock = 0ul; + memset(g_usbd_SetupPacket, 0, 8ul); + + /* Reset PID DATA0 */ + for(i=0ul; iEP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + + /* Reset USB device address */ + USBD_SET_ADDR(0ul); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_usbd_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_usbd_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_u32EpStallLock = u32EpBitmap; +} + + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usci_i2c.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_i2c.c new file mode 100644 index 0000000000..dfa5dcdafe --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_i2c.c @@ -0,0 +1,1678 @@ +/****************************************************************************//** + * @file usci_i2c.c + * @version V3.00 + * @brief M480 series USCI I2C(UI2C) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; + ui2c->CTL = 4U << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + ui2c->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *ui2c) +{ + /* Disable USCI_I2C function */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c) +{ + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if (u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + if (u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + if (u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + if (u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + + ui2c->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + + /* Disable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + + /* Disable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + + /* Disable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Disable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Disable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + + /* Enable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + + /* Enable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + + /* Enable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Enable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Enable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Enable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + if (ui2c == UI2C0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return ( u32Pclk / ((u32Divider+1U)<<1U) ); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + /* Check Time-out Interrupt Flag */ + if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + /* Check Start Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + /* Check Stop Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + /* Check Non-Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + /* Check Arbitration Lost Interrupt Flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + /* Check Error Interrupt Flag */ + if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + /* Check Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if(u32Mask & UI2C_TO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + + /* Clear Start Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STAR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + + /* Clear Stop Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STOR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + + /* Clear Non-Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_NACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + + /* Clear Arbitration Lost Interrupt Flag */ + if(u32Mask & UI2C_ARBLO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + + /* Clear Error Interrupt Flag */ + if(u32Mask & UI2C_ERR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + + /* Clear Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_ACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *ui2c) +{ + return ( ui2c->RXDAT ); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data) +{ + ui2c->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if(u8SlaveNo) + { + ui2c->DEVADDR1 = u16SlaveAddr; + } + else + { + ui2c->DEVADDR0 = u16SlaveAddr; + } + + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) |u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if(u8SlaveNo) + { + ui2c->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + ui2c->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt) +{ + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *ui2c) +{ + ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode) +{ + ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *ui2c) +{ + ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 2U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if (u32txLen < u32wLen) + { + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usci_spi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_spi.c new file mode 100644 index 0000000000..760a540200 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_spi.c @@ -0,0 +1,663 @@ +/****************************************************************************//** + * @file usci_spi.c + * @version V3.00 + * @brief M480 series USCI_SPI driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0ul; + uint32_t u32Pclk; + uint32_t u32UspiClk = 0ul; + + if(uspi == (USPI_T *)USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + if(u32BusClock != 0ul) + { + u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */ + } + else {} + + /* Enable USCI_SPI protocol */ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; + uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if(u32DataWidth == 16ul) + { + u32DataWidth = 0ul; + } + else {} + uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if(u32MasterSlave == USPI_MASTER) + { + uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + uspi->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if(u32BusClock != 0ul) + { + u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) ); + } + else {} + + return u32UspiClk; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *uspi) +{ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *uspi) +{ + uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if(uspi == USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1ul)<<1) ); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *uspi) +{ + uint32_t u32BusClk; + uint32_t u32ClkDiv; + + u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if(uspi == USPI0) + { + u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) ); + } + else + { + u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) ); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + /* Enable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + /* Enable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + /* Enable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + /* Enable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + else {} + /* Enable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + else {} + /* Enable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + else {} + /* Enable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + /* Disable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + /* Disable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + /* Disable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + /* Disable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + /* Disable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + else {} + /* Disable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + else {} + /* Disable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + else {} + /* Disable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Get interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32TmpFlag; + uint32_t u32IntFlag = 0ul; + + /* Check slave selection signal inactive interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk; + if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) ) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + else {} + /* Check slave selection signal active interrupt flag */ + + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk; + if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + else {} + + /* Check slave time-out interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk; + if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + else {} + + /* Check slave bit count error interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk; + if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + else {} + + /* Check TX under run interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk; + if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + else {} + + /* Check RX overrun interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk; + if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + else {} + + /* Check TX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk; + if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + else {} + + /* Check TX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk; + if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + else {} + + /* Check RX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk; + if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + else {} + + /* Check RX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk; + if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + else {} + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + else {} + /* Clear slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + else {} + /* Clear slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + else {} + /* Clear slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + else {} + /* Clear TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + else {} + /* Clear RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + else {} + /* Clear TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + else {} + /* Clear TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + else {} + /* Clear RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + else {} + + /* Clear RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } + else {} +} + +/** + * @brief Get USCI_SPI status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0ul; + uint32_t u32TmpFlag; + + /* Check busy status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk; + if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + else {} + + /* Check RX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk; + if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + else {} + + /* Check RX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk; + if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + else {} + + /* Check TX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk; + if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + else {} + + /* Check TX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk; + if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + else {} + + /* Check USCI_SPI_SS line status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk; + if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + else {} + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *uspi) +{ + uspi->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *uspi) +{ + uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usci_uart.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_uart.c new file mode 100644 index 0000000000..3aad6697c4 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_uart.c @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V3.00 + * @brief M480 series USCI UART (UUART) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + + if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; + +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T* uuart) +{ + uuart->CTL = 0ul; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if( uuart == UUART0) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + u32Tmp = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + /* Enable USCI_UART protocol */ + uuart->CTL &= ~UUART_CTL_FUNMODE_Msk; + uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + + uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The register value of baud rate of USCI_UART module. + * If u32baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32data_width The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if(uuart == UUART0) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else /* UUART1 */ + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + if(u32baudrate != 0ul) + { + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul; + u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul; + u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul; + } + + /* Set USCI_UART line configuration */ + uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width; + uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32parity; + uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; + +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. + * - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode + * - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode) +{ + uuart->PROTCTL |= u32WakeupMode; + uuart->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T* uuart) +{ + uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk); + uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T* uuart) +{ + /* Set RTS signal is low level active */ + uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T* uuart) +{ + /* Disable CTS and RTS auto flow control function */ + uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk); +} + + + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/wdt.c b/bsp/nuvoton_m487/libraries/StdDriver/src/wdt.c new file mode 100644 index 0000000000..7506acf46b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/wdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * @brief M480 series WDT driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + return; +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/wwdt.c b/bsp/nuvoton_m487/libraries/StdDriver/src/wwdt.c new file mode 100644 index 0000000000..d909bd78ef --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/wwdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * @brief M480 series WWDT driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note This WWDT_CTL register can be write only one time after chip is powered on or reset. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) | + WWDT_CTL_WWDTEN_Msk; + return; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/tm4c129x-dk/tm4c_rom.ld b/bsp/nuvoton_m487/link.ld similarity index 64% rename from bsp/tm4c129x-dk/tm4c_rom.ld rename to bsp/nuvoton_m487/link.ld index 7b266ed519..f792b66e84 100644 --- a/bsp/tm4c129x-dk/tm4c_rom.ld +++ b/bsp/nuvoton_m487/link.ld @@ -1,42 +1,33 @@ -/****************************************************************************** +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * blinky.ld - Linker configuration file for blinky. + * SPDX-License-Identifier: Apache-2.0 * - * Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. - * Software License Agreement - * - * Texas Instruments (TI) is supplying this software for use solely and - * exclusively on TI's microcontroller products. The software is owned by - * TI and/or its suppliers, and is protected under applicable copyright - * laws. You may not combine this software with "viral" open-source - * software in order to form a larger program. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. - * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT - * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY - * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL - * DAMAGES, FOR ANY REASON WHATSOEVER. - * - * This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. - * - *****************************************************************************/ + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ +/* Program Entry, set to mark it as "used" and avoid gc */ MEMORY { - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 - DATA (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512K flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 160k /* 160K sram */ } - -ENTRY(ResetISR) -_system_stack_size = 0x200; +ENTRY(Reset_Handler) +_system_stack_size = 0x400; SECTIONS { - .text : + .vector : { . = ALIGN(4); + _stext = .; KEEP(*(.isr_vector)) /* Startup code */ + } > CODE = 0 + + .text : + { . = ALIGN(4); *(.text) /* remaining code */ *(.text.*) /* remaining code */ @@ -57,43 +48,40 @@ SECTIONS __vsymtab_end = .; . = ALIGN(4); + /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; . = ALIGN(4); - PROVIDE(__ctors_start__ = .); - /* old GCC version uses .ctors */ - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - /* new GCC version uses .init_array */ - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE(__ctors_end__ = .); - . = ALIGN(4); _etext = .; } > CODE = 0 - .ARM.extab : - { - *(.ARM.extab*) + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) - . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sidata = .; } > CODE + __exidx_end = .; /* .data section which is used for initialized data */ + + .stack : + { + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + .data : AT (_sidata) { - . = ALIGN(4); - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sdata = . ; @@ -105,13 +93,6 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; - } > DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; } >DATA __bss_start = .; @@ -127,12 +108,14 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; + _ebss = . ; + *(.bss.init) } > DATA __bss_end = .; - _end = .; + + __ram_top = ORIGIN(DATA) + LENGTH(DATA); /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/bsp/tm4c129x-dk/rtconfig.h b/bsp/nuvoton_m487/rtconfig.h similarity index 51% rename from bsp/tm4c129x-dk/rtconfig.h rename to bsp/nuvoton_m487/rtconfig.h index d9e6e561c9..6e3b9c097e 100644 --- a/bsp/tm4c129x-dk/rtconfig.h +++ b/bsp/nuvoton_m487/rtconfig.h @@ -8,17 +8,15 @@ #define RT_NAME_MAX 8 #define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_DEBUG #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -/* RT_DEBUG_THREAD is not set */ #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG /* Inter-Thread communication */ @@ -26,16 +24,11 @@ #define RT_USING_MUTEX #define RT_USING_EVENT #define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ -#define RT_USING_MEMPOOL -#define RT_USING_MEMHEAP -#define RT_USING_HEAP #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ +#define RT_USING_HEAP /* Kernel Device Object */ @@ -43,70 +36,72 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -/* RT_USING_MODULE is not set */ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ #define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION #define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 1024 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ -/* FINSH_USING_MSH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 /* Device virtual file system */ -/* RT_USING_DFS is not set */ +#define RT_USING_DFS +#define DFS_FILESYSTEMS_MAX 1 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 32 +#define RT_USING_DFS_DEVFS /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 64 #define RT_USING_SERIAL -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_I2C is not set */ -/* RT_USING_PIN is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ + +/* Using WiFi */ + + +/* Using USB */ + /* POSIX layer and C standard library */ -/* RT_USING_LIBC is not set */ -/* RT_USING_PTHREADS is not set */ +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ -/* Network stack */ /* light weight TCP/IP stack */ #define RT_USING_LWIP -#define RT_USING_LWIP141 -/* RT_USING_LWIP202 is not set */ -/* RT_LWIP_IGMP is not set */ +#define RT_USING_LWIP202 +#define RT_LWIP_IGMP #define RT_LWIP_ICMP -/* RT_LWIP_SNMP is not set */ #define RT_LWIP_DNS #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 #define IP_SOF_BROADCAST_RECV 1 -/* LWIP_USING_DHCPD is not set */ /* Static IPv4 Address */ @@ -115,80 +110,74 @@ #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP -/* RT_LWIP_RAW is not set */ -/* RT_LWIP_PPP is not set */ -/* RT_LWIP_PPPOE is not set */ -/* RT_LWIP_PPPOS is not set */ -#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 19 +#define RT_LWIP_PBUF_NUM 0 #define RT_LWIP_RAW_PCB_NUM 4 #define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 19 #define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8196 -#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCP_SND_BUF 2920 +#define RT_LWIP_TCP_WND 2920 #define RT_LWIP_TCPTHREAD_PRIORITY 10 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 #define RT_LWIP_TCPTHREAD_STACKSIZE 1024 #define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_STACKSIZE 768 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -/* RT_LWIP_REASSEMBLY_FRAG is not set */ #define LWIP_NETIF_STATUS_CALLBACK 1 #define SO_REUSE 1 #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +#define LWIP_NETIF_LOOPBACK 0 /* Modbus master and slave stack */ -/* RT_USING_MODBUS is not set */ -/* RT_USING_NETUTILS is not set */ -/* RT-Thread UI Engine */ +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ -/* PKG_USING_GUIENGINE is not set */ /* RT-Thread online packages */ /* system packages */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ +/* RT-Thread GUI Engine */ + /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_EZXML is not set */ + +/* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_MARVELLWIFI is not set */ + +/* Wiced WiFi */ + /* security packages */ -/* PKG_USING_MBEDTLS is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ /* multimedia packages */ + /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ /* miscellaneous packages */ -/* PKG_USING_HELLO is not set */ -/* BSP_SPECIAL CONFIG */ +/* example package: hello */ -#define RT_USING_UART0 #endif diff --git a/bsp/tm4c129x-dk/rtconfig.py b/bsp/nuvoton_m487/rtconfig.py similarity index 52% rename from bsp/tm4c129x-dk/rtconfig.py rename to bsp/nuvoton_m487/rtconfig.py index 8db01c509b..3223847a28 100644 --- a/bsp/tm4c129x-dk/rtconfig.py +++ b/bsp/nuvoton_m487/rtconfig.py @@ -1,60 +1,63 @@ -# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) - import os # toolchains options ARCH='arm' CPU='cortex-m4' -CROSS_TOOL='keil' +CROSS_TOOL='gcc' if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -#device options -PART_TYPE = 'PART_TM4C129XNCZAD' + CROSS_TOOL = os.getenv('RTT_CC') + # cross_tool provides the cross compiler # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:\ArdaArmTools\Sourcery_Lite\bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:\Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') -#BUILD = 'debug' -BUILD = 'release' +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/Program Files (x86)/GNU Tools ARM Embedded/6 2017-q2-update/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = '' +# BUILD = 'debug' + if PLATFORM == 'gcc': - # tool-chains + # toolchains PREFIX = 'arm-none-eabi-' CC = PREFIX + 'gcc' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' + LINK = PREFIX + 'g++' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -std=c99 -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-tm4c129x.map,-cref,-u,Reset_Handler -T tm4c_rom.ld' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + + if BUILD == 'debug': + DEVICE = DEVICE + ' -DDEBUG' + + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-nuc487.map -T link.ld ' CPATH = '' LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' + CFLAGS += ' -O0 -gdwarf-2' AFLAGS += ' -gdwarf-2' else: - CFLAGS += ' -O2' + CFLAGS += ' -O2 -gdwarf-2' + AFLAGS += ' -gdwarf-2' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -66,15 +69,16 @@ elif PLATFORM == 'armcc': LINK = 'armlink' TARGET_EXT = 'axf' - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter tm4c_rom.sct --info sizes --info totals --info unused --info veneers --list rtthread-tm4c129x.map --strict' + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nuc487.map --scatter nuc487_flash.sct' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB' - - EXEC_PATH += '/arm/armcc/bin/' + CFLAGS += ' --c99' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' if BUILD == 'debug': CFLAGS += ' -g -O0' @@ -92,7 +96,7 @@ elif PLATFORM == 'iar': LINK = 'ilinkarm' TARGET_EXT = 'out' - DEVICE = '-Dewarm' # + ' -D' + PART_TYPE + DEVICE = ' ' CFLAGS = DEVICE CFLAGS += ' --diag_suppress Pa050' @@ -103,31 +107,26 @@ elif PLATFORM == 'iar': CFLAGS += ' --no_tbaa' CFLAGS += ' --no_clustering' CFLAGS += ' --no_scheduling' - + CFLAGS += ' --debug' CFLAGS += ' --endian=little' CFLAGS += ' --cpu=Cortex-M4' CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --fpu=None' CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' AFLAGS += ' -s+' AFLAGS += ' -w+' AFLAGS += ' -r' AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "tm4c_rom.icf"' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config nuc487_flash.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' LFLAGS += ' --entry __iar_program_start' - #LFLAGS += ' --silent' - + EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' \ No newline at end of file + POST_ACTION = '' diff --git a/bsp/tm4c129x-dk/template.uvproj b/bsp/nuvoton_m487/template.uvproj similarity index 85% rename from bsp/tm4c129x-dk/template.uvproj rename to bsp/nuvoton_m487/template.uvproj index 342711d8be..9a3bc4a384 100644 --- a/bsp/tm4c129x-dk/template.uvproj +++ b/bsp/nuvoton_m487/template.uvproj @@ -7,31 +7,29 @@ - RT-Thread TM4C129X + rtthread-m487 0x4 ARM-ADS - TM4C1294NCPDT - Texas Instruments - Keil.TM4C_DFP.1.0.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE + M487JIDAE + Nuvoton + IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2 - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCPDT$Flash\TM4C129_1024.FLM)) - 7088 - $$Device:TM4C1294NCPDT$Device\Include\TM4C129\TM4C129.h + undefined + + 0 + - -DTM4C1294NCPDT + - $$Device:TM4C1294NCPDT$SVD\TM4C129\TM4C1294NCPDT.svd + SFD\Nuvoton\M481_v1.SFR 0 0 @@ -47,13 +45,13 @@ 1 .\build\ - rtthread-tm4c + template 1 0 - 0 + 1 1 1 - .\ + .\build\ 1 0 0 @@ -74,8 +72,6 @@ 0 0 - 0 - 0 0 @@ -106,13 +102,13 @@ SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 + + DARMCM1.DLL + SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 + + TARMCM1.DLL + @@ -132,7 +128,6 @@ 1 1 0 - 1 1 @@ -144,11 +139,9 @@ 0 1 1 - 1 - 1 0 - 6 + 10 @@ -162,7 +155,7 @@ - Segger\JL2CM3.dll + NULink\Nu_Link.dll @@ -172,10 +165,10 @@ 0 1 1 - 4096 + 4101 - 1 - BIN\UL2CM3.DLL + 0 + NULink\Nu_Link.dll "" () @@ -221,7 +214,7 @@ 1 0 0 - 2 + 1 0 0 8 @@ -281,12 +274,12 @@ 0 0x20000000 - 0x40000 + 0x28000 1 0x0 - 0x100000 + 0x80000 0 @@ -311,7 +304,7 @@ 1 0x0 - 0x100000 + 0x80000 1 @@ -336,7 +329,7 @@ 0 0x20000000 - 0x40000 + 0x28000 0 @@ -357,11 +350,9 @@ 0 0 0 - 2 + 0 0 0 - 0 - 0 @@ -378,7 +369,6 @@ 0 0 0 - 0 @@ -387,16 +377,15 @@ - 0 + 1 0 0 0 1 0 0x00000000 - 0x00000000 - - tm4c_rom.sct + 0x20000000 + diff --git a/bsp/nuvoton_nuc472/rtconfig.py b/bsp/nuvoton_nuc472/rtconfig.py index f37ab79b7a..7fb23e306a 100644 --- a/bsp/nuvoton_nuc472/rtconfig.py +++ b/bsp/nuvoton_nuc472/rtconfig.py @@ -41,7 +41,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' CFLAGS = DEVICE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-nuc472.map -T ldscripts/mem.ld -T ldscripts/libs.ld -T ldscripts/sections.ld ' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-nuc472.map -T ldscripts/sections.ld ' CPATH = '' LPATH = '' diff --git a/bsp/pic32ethernet/project.cbp b/bsp/pic32ethernet/project.cbp index cdba10e0a6..ad51307464 100644 --- a/bsp/pic32ethernet/project.cbp +++ b/bsp/pic32ethernet/project.cbp @@ -412,10 +412,6 @@ - - - diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config index 15d4f1cebd..7c6c2dc1df 100644 --- a/bsp/qemu-vexpress-a9/.config +++ b/bsp/qemu-vexpress-a9/.config @@ -7,6 +7,8 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -15,8 +17,9 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 @@ -63,10 +66,10 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -# CONFIG_RT_USING_MODULE is not set CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_ARCH_ARM_CORTEX_A9=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -145,19 +148,22 @@ CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_I2C=y CONFIG_RT_USING_I2C_BITOPS=y CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set CONFIG_RT_USING_MTD_NOR=y CONFIG_RT_USING_MTD_NAND=y CONFIG_RT_MTD_NAND_DEBUG=y +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RTC_SYNC_USING_NTP is not set +CONFIG_RT_USING_SOFT_RTC=y CONFIG_RT_USING_SDIO=y CONFIG_RT_SDIO_STACK_SIZE=512 CONFIG_RT_SDIO_THREAD_PRIORITY=15 CONFIG_RT_MMCSD_STACK_SIZE=1024 CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set CONFIG_RT_USING_SPI=y CONFIG_RT_USING_SPI_MSD=y CONFIG_RT_USING_SFUD=y @@ -169,9 +175,13 @@ CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set CONFIG_RT_USING_WDT=y -# CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_AUDIO is not set +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + # # Using USB # @@ -187,6 +197,7 @@ CONFIG_RT_USING_POSIX=y CONFIG_RT_USING_POSIX_MMAP=y CONFIG_RT_USING_POSIX_TERMIOS=y CONFIG_RT_USING_POSIX_AIO=y +# CONFIG_RT_USING_MODULE is not set # # Network @@ -210,6 +221,7 @@ CONFIG_SAL_PROTO_FAMILIES_NUM=4 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP210 is not set CONFIG_RT_USING_LWIP_IPV6=y # CONFIG_RT_LWIP_IGMP is not set CONFIG_RT_LWIP_ICMP=y @@ -285,6 +297,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_LOG_TRACE_USING_LEVEL_DEBUG is not set # CONFIG_LOG_TRACE_USING_MEMLOG is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set # # RT-Thread online packages @@ -327,6 +340,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_ONENET is not set # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set # # security packages @@ -377,6 +391,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_STM32F4_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set # # miscellaneous packages diff --git a/bsp/qemu-vexpress-a9/cpu/context_gcc.S b/bsp/qemu-vexpress-a9/cpu/context_gcc.S index 86efcede9f..2b13690e67 100644 --- a/bsp/qemu-vexpress-a9/cpu/context_gcc.S +++ b/bsp/qemu-vexpress-a9/cpu/context_gcc.S @@ -20,9 +20,19 @@ * Change Logs: * Date Author Notes * 2013-07-05 Bernard the first version + * 2018-11-22 Jesven in the smp version, using macro to + * define rt_hw_interrupt_enable and rt_hw_interrupt_disable + * rt_hw_context_switch_interrupt switches to the new thread directly */ +#include "rtconfig.h" .section .text, "ax" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + /* * rt_base_t rt_hw_interrupt_disable(); */ @@ -48,6 +58,11 @@ rt_hw_interrupt_enable: rt_hw_context_switch_to: ldr sp, [r0] @ get new task stack pointer +#ifdef RT_USING_SMP + mov r0, r1 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + ldmfd sp!, {r4} @ pop new task spsr msr spsr_cxsf, r4 @@ -77,6 +92,11 @@ rt_hw_context_switch: str sp, [r0] @ store sp in preempted tasks TCB ldr sp, [r1] @ get new task stack pointer +#ifdef RT_USING_SMP + mov r0, r2 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + ldmfd sp!, {r4} @ pop new task cpsr to spsr msr spsr_cxsf, r4 ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr @@ -84,11 +104,60 @@ rt_hw_context_switch: /* * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); */ +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread .globl rt_interrupt_to_thread .globl rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt: +#ifdef RT_USING_SMP + /* r0 :irq_mod context + * r1 :addr of from_thread's sp + * r2 :addr of to_thread's sp + * r3 :to_thread's tcb + */ + + @ r0 point to {r0-r3} in stack + push {r1 - r3} + mov r1, r0 + add r0, r0, #4*4 + ldmfd r0!, {r4-r12,lr}@ reload saved registers + mrs r3, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r0, {r4-r7} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r4-r7} @ push old task's r0-r3 + stmfd sp!, {r3} @ push old task's cpsr + + msr cpsr_c, #I_Bit|F_Bit|Mode_IRQ + pop {r1 - r3} + mov sp, r0 + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + str sp, [r1] + + ldr sp, [r2] + mov r0, r3 + bl rt_cpus_lock_status_restore + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +#else /*RT_USING_SMP*/ ldr r2, =rt_thread_switch_interrupt_flag ldr r3, [r2] cmp r3, #1 @@ -101,3 +170,4 @@ _reswitch: ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread str r1, [r2] bx lr +#endif /*RT_USING_SMP*/ diff --git a/bsp/qemu-vexpress-a9/cpu/cpu.c b/bsp/qemu-vexpress-a9/cpu/cpu.c index 426da965ad..10099809a3 100644 --- a/bsp/qemu-vexpress-a9/cpu/cpu.c +++ b/bsp/qemu-vexpress-a9/cpu/cpu.c @@ -10,12 +10,26 @@ * Change Logs: * Date Author Notes * 2011-09-15 Bernard first version + * 2018-11-22 Jesven add rt_hw_cpu_id() */ #include #include #include +#ifdef RT_USING_SMP +int rt_hw_cpu_id(void) +{ + int cpu_id; + __asm__ volatile ( + "mrc p15, 0, %0, c0, c0, 5" + :"=r"(cpu_id) + ); + cpu_id &= 0xf; + return cpu_id; +}; +#endif + /** * @addtogroup ARM CPU */ diff --git a/bsp/qemu-vexpress-a9/cpu/gic.c b/bsp/qemu-vexpress-a9/cpu/gic.c index cbef00af22..66876518ce 100644 --- a/bsp/qemu-vexpress-a9/cpu/gic.c +++ b/bsp/qemu-vexpress-a9/cpu/gic.c @@ -11,8 +11,11 @@ * Date Author Notes * 2013-07-20 Bernard first version * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() */ +#include #include #include @@ -278,3 +281,19 @@ void arm_gic_set_group(rt_uint32_t index, int vector, int group) vector) |= (1 << (vector % 32)); } } + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) + { + /* note: ipi_vector maybe different with irq_vector */ + GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector; +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/bsp/qemu-vexpress-a9/cpu/gic.h b/bsp/qemu-vexpress-a9/cpu/gic.h index 42c061dc1b..9d0368ec94 100644 --- a/bsp/qemu-vexpress-a9/cpu/gic.h +++ b/bsp/qemu-vexpress-a9/cpu/gic.h @@ -27,6 +27,7 @@ int arm_gic_get_active_irq(rt_uint32_t index); void arm_gic_ack(rt_uint32_t index, int irq); void arm_gic_dump_type(rt_uint32_t index); +void rt_hw_vector_init(void); #endif diff --git a/bsp/qemu-vexpress-a9/cpu/interrupt.c b/bsp/qemu-vexpress-a9/cpu/interrupt.c index e66f746042..febf86a66e 100644 --- a/bsp/qemu-vexpress-a9/cpu/interrupt.c +++ b/bsp/qemu-vexpress-a9/cpu/interrupt.c @@ -10,6 +10,7 @@ * Change Logs: * Date Author Notes * 2013-07-06 Bernard first version + * 2018-11-22 Jesven add smp support */ #include @@ -19,21 +20,21 @@ #define MAX_HANDLERS NR_IRQS_PBA8 -extern volatile rt_uint8_t rt_interrupt_nest; - /* exception and interrupt handler table */ struct rt_irq_desc isr_table[MAX_HANDLERS]; +#ifndef RT_USING_SMP /* Those varibles will be accessed in ISR, so we need to share them. */ rt_uint32_t rt_interrupt_from_thread; rt_uint32_t rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; +#endif const unsigned int VECTOR_BASE = 0x00; extern void rt_cpu_vector_set_base(unsigned int addr); extern int system_vectors; -static void rt_hw_vector_init(void) +void rt_hw_vector_init(void) { rt_cpu_vector_set_base((unsigned int)&system_vectors); } @@ -60,10 +61,11 @@ void rt_hw_interrupt_init(void) arm_gic_cpu_init(0, gic_cpu_base); /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; +#ifndef RT_USING_SMP rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; +#endif } /** diff --git a/bsp/qemu-vexpress-a9/cpu/start_gcc.S b/bsp/qemu-vexpress-a9/cpu/start_gcc.S index 569b14fbc1..d380d02d08 100644 --- a/bsp/qemu-vexpress-a9/cpu/start_gcc.S +++ b/bsp/qemu-vexpress-a9/cpu/start_gcc.S @@ -20,8 +20,12 @@ * Change Logs: * Date Author Notes * 2013-07-05 Bernard the first version + * 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks + * and switches to a new thread */ +#include "rtconfig.h" + .equ Mode_USR, 0x10 .equ Mode_FIQ, 0x11 .equ Mode_IRQ, 0x12 @@ -64,6 +68,17 @@ _reset: orr r0, r0, #0x13 msr cpsr_c, r0 + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 //enable smp + + ldr lr, =after_enable_mmu + ldr r0, =mtbl + b enable_mmu + +after_enable_mmu: + /* setup stack */ bl stack_setup @@ -93,6 +108,7 @@ ctor_loop: ctor_end: /* start RT-Thread Kernel */ + bl flush_cache_all ldr pc, _rtthread_startup _rtthread_startup: .word rtthread_startup @@ -127,6 +143,85 @@ stack_setup: msr cpsr_c, #Mode_SVC|I_Bit|F_Bit bx lr + .global enable_mmu +enable_mmu: + orr r0, #0x18 + mcr p15, 0, r0, c2, c0, 0 @ttbr0 + + mov r0, #(1 << 5) @PD1=1 + mcr p15, 0, r0, c2, c0, 2 @ttbcr + + mov r0, #1 + mcr p15, 0, r0, c3, c0, 0 @dacr + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c7, c5, 0 @iciallu + mcr p15, 0, r0, c7, c5, 6 @bpiall + + mrc p15, 0, r0, c1, c0, 0 + orr r0, #(1 | 4) + orr r0, #(1 << 12) + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + mov pc, lr + +.global flush_cache_all +flush_cache_all: + stmfd sp!, {r0-r12, lr} + bl v7_flush_dcache_all + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + ldmfd sp!, {r0-r12, lr} + mov pc, lr + + v7_flush_dcache_all: + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt loop1 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb + isb + mov pc, lr + /* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ .section .text.isr, "ax" .align 5 @@ -143,17 +238,25 @@ vector_fiq: .globl rt_interrupt_from_thread .globl rt_interrupt_to_thread -.globl rt_current_thread - .align 5 .globl vector_irq vector_irq: +#ifdef RT_USING_SMP + clrex +#endif stmfd sp!, {r0-r12,lr} bl rt_interrupt_enter bl rt_hw_trap_irq bl rt_interrupt_leave +#ifdef RT_USING_SMP + mov r0, sp + bl rt_scheduler_do_irq_switch + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 +#else @ if rt_thread_switch_interrupt_flag set, jump to @ rt_hw_context_switch_interrupt_do and don't return ldr r0, =rt_thread_switch_interrupt_flag @@ -198,6 +301,8 @@ rt_hw_context_switch_interrupt_do: ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr +#endif + .macro push_svc_reg sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ stmia sp, {r0 - r12} @/* Calling r0-r12 */ @@ -244,3 +349,87 @@ vector_resv: push_svc_reg bl rt_hw_trap_resv b . + +#ifdef RT_USING_SMP +.global set_secondary_cpu_boot_address +set_secondary_cpu_boot_address: + ldr r0, =secondary_cpu_start + + mvn r1, #0 //0xffffffff + ldr r2, =0x10000034 + str r1, [r2] + str r0, [r2, #-4] + mov pc, lr + +.global secondary_cpu_start +secondary_cpu_start: + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 //enable smp + + ldr r0, =mtbl + ldr lr, =1f + + b enable_mmu +1: + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1<<13) + mcr p15, 0, r0, c1, c0, 0 + + cps #Mode_IRQ + ldr sp, =irq_stack_2_limit + + cps #Mode_FIQ + ldr sp, =irq_stack_2_limit + + cps #Mode_SVC + ldr sp, =svc_stack_2_limit + + b secondary_cpu_c_start +#endif + +.bss +.align 2 //align to 2~2=4 +svc_stack_2: + .space (1 << 10) +svc_stack_2_limit: + +irq_stack_2: + .space (1 << 10) +irq_stack_2_limit: + +.data +#define DEVICE_MEM 0x10406 +#define NORMAL_MEM 0x1140e +.align 14 +mtbl: + + //vaddr: 0x00000000 + .rept 0x100 + .word 0x0 + .endr + + //vaddr: 0x10000000 + .equ mmu_tbl_map_paddr, 0x10000000 + .rept 0x400 + .word mmu_tbl_map_paddr | DEVICE_MEM + .equ mmu_tbl_map_paddr, mmu_tbl_map_paddr + 0x100000 + .endr + + //vaddr: 0x50000000 + .rept 0x100 + .word 0x0 + .endr + + //vaddr: 0x60000000 + .equ mmu_tbl_map_paddr, 0x60000000 + .rept 0x800 + .word mmu_tbl_map_paddr | NORMAL_MEM + .equ mmu_tbl_map_paddr, mmu_tbl_map_paddr + 0x100000 + .endr + + //vaddr: 0xe0000000 + .rept 0x200 + .word 0x0 + .endr diff --git a/bsp/qemu-vexpress-a9/cpu/trap.c b/bsp/qemu-vexpress-a9/cpu/trap.c index e3283d7e7e..a1f00d0075 100644 --- a/bsp/qemu-vexpress-a9/cpu/trap.c +++ b/bsp/qemu-vexpress-a9/cpu/trap.c @@ -20,7 +20,6 @@ #include "gic.h" -extern struct rt_thread *rt_current_thread; #ifdef RT_USING_FINSH extern long list_thread(void); #endif diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c index c598c33635..55ac034ab9 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c @@ -103,7 +103,7 @@ void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val) if (v & (AACI_SLFR_1TXB | AACI_SLFR_2TXB)) { - dbg_log(DBG_ERROR, "timeout waiting for write to complete\n"); + LOG_E("timeout waiting for write to complete"); } } @@ -126,7 +126,7 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg) if (v & AACI_SLFR_1TXB) { - dbg_log(DBG_ERROR, "timeout on slot 1 TX busy\n"); + LOG_E("timeout on slot 1 TX busy"); v = ~0x0; return v; } @@ -142,7 +142,7 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg) if (v != (AACI_SLFR_1RXV | AACI_SLFR_2RXV)) { - dbg_log(DBG_ERROR, "timeout on RX valid\n"); + LOG_E("timeout on RX valid"); v = ~0x0; return v; } @@ -157,12 +157,12 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg) } else if (--retries) { - dbg_log(DBG_ERROR, "ac97 read back fail. retry\n"); + LOG_E("ac97 read back fail. retry"); continue; } else { - dbg_log(DBG_ERROR, "wrong ac97 register read back (%x != %x)\n", v, reg); + LOG_E("wrong ac97 register read back (%x != %x)", v, reg); v = ~0x0; } } @@ -277,7 +277,7 @@ rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_da { if (channle < 0 || channle >= PL041_CHANNLE_NUM) { - dbg_log(DBG_ERROR, "%s channle:%d err.\n", __FUNCTION__, channle); + LOG_E("%s channle:%d err.", __FUNCTION__, channle); return -RT_ERROR; } irq_tbl[channle].fun = fun; @@ -289,7 +289,7 @@ rt_err_t aaci_pl041_irq_unregister(int channle) { if (channle < 0 || channle >= PL041_CHANNLE_NUM) { - dbg_log(DBG_ERROR, "%s channle:%d err.\n", __FUNCTION__, channle); + LOG_E("%s channle:%d err.", __FUNCTION__, channle); return -RT_ERROR; } irq_tbl[channle].fun = RT_NULL; @@ -312,17 +312,17 @@ static void aaci_pl041_irq_handle(int irqno, void *param) m = mask & 0x7f; if (m & AACI_ISR_ORINTR) { - dbg_log(DBG_WARNING, "RX overrun on chan %d\n", channle); + LOG_W("RX overrun on chan %d", channle); } if (m & AACI_ISR_RXTOINTR) { - dbg_log(DBG_WARNING, "RX timeout on chan %d\n", channle); + LOG_W("RX timeout on chan %d", channle); } if (mask & AACI_ISR_URINTR) { - dbg_log(DBG_WARNING, "TX underrun on chan %d\n", channle); + LOG_W("TX underrun on chan %d", channle); } p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14); diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c index 8be0a47103..26aad5bda1 100644 --- a/bsp/qemu-vexpress-a9/drivers/board.c +++ b/bsp/qemu-vexpress-a9/drivers/board.c @@ -1,74 +1,24 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2012-11-20 Bernard the first version + * 2018-11-22 Jesven add rt_hw_spin_lock + * add rt_hw_spin_unlock + * add smp ipi init */ #include #include #include "board.h" - -#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) -#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) -#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) -#define TIMER_CTRL_ONESHOT (1 << 0) -#define TIMER_CTRL_32BIT (1 << 1) -#define TIMER_CTRL_DIV1 (0 << 2) -#define TIMER_CTRL_DIV16 (1 << 2) -#define TIMER_CTRL_DIV256 (2 << 2) -#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ -#define TIMER_CTRL_PERIODIC (1 << 6) -#define TIMER_CTRL_ENABLE (1 << 7) - -#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) -#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) -#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) -#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) +#include "drv_timer.h" #define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) -#define TIMER_HW_BASE REALVIEW_TIMER2_3_BASE - -static void rt_hw_timer_isr(int vector, void *param) -{ - rt_tick_increase(); - /* clear interrupt */ - TIMER_INTCLR(TIMER_HW_BASE) = 0x01; -} - -int rt_hw_timer_init(void) -{ - rt_uint32_t val; - - SYS_CTRL |= REALVIEW_REFCLK; - - /* Setup Timer0 for generating irq */ - val = TIMER_CTRL(TIMER_HW_BASE); - val &= ~TIMER_CTRL_ENABLE; - val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); - TIMER_CTRL(TIMER_HW_BASE) = val; - - TIMER_LOAD(TIMER_HW_BASE) = 1000; - - /* enable timer */ - TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE; - - rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3); - - return 0; -} -INIT_BOARD_EXPORT(rt_hw_timer_init); - void idle_wfi(void) { asm volatile ("wfi"); @@ -79,13 +29,57 @@ void idle_wfi(void) */ void rt_hw_board_init(void) { - /* initialzie hardware interrupt */ + /* initialize hardware interrupt */ rt_hw_interrupt_init(); + /* initialize system heap */ rt_system_heap_init(HEAP_BEGIN, HEAP_END); rt_components_board_init(); rt_console_set_device(RT_CONSOLE_DEVICE_NAME); rt_thread_idle_sethook(idle_wfi); + +#ifdef RT_USING_SMP + /* install IPI interrupt */ + rt_hw_interrupt_install(RT_SCHEDULE_IPI_IRQ, rt_scheduler_ipi_handler, RT_NULL, "ipi"); + rt_hw_interrupt_umask(RT_SCHEDULE_IPI_IRQ); +#endif } +#ifdef RT_USING_SMP +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) { + __asm__ __volatile__("wfe":::"memory"); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __asm__ volatile ("dmb":::"memory"); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __asm__ volatile ("dmb":::"memory"); + lock->tickets.owner++; + __asm__ volatile ("dsb ishst\nsev":::"memory"); +} +#endif /*RT_USING_SMP*/ diff --git a/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c b/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c index f89146e3f1..7b1a49db55 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_keyboard.c @@ -196,47 +196,47 @@ static void keyboard_report_event(void * device, rt_uint32_t flag, rt_uint8_t da { if (map[i].data == data) { - dbg_log(DBG_LOG,"KEY info:\n"); + LOG_D("KEY info:"); if (flag & KBD_CAPS_LOCK) { - dbg_log(DBG_LOG,"CAPS:LOCK\n"); + LOG_D("CAPS:LOCK"); } else { - dbg_log(DBG_LOG,"CAPS:UNLOCK\n"); + LOG_D("CAPS:UNLOCK"); } if (flag & KBD_LEFT_SHIFT) { mod |= RTGUI_KMOD_LSHIFT; - dbg_log(DBG_LOG,"SHIFT:LEFT\n"); + LOG_D("SHIFT:LEFT"); } else if (flag & KBD_RIGHT_SHIFT) { mod |= RTGUI_KMOD_RSHIFT; - dbg_log(DBG_LOG,"SHIFT:RIGHT\n"); + LOG_D("SHIFT:RIGHT"); } else { - dbg_log(DBG_LOG,"SHIFT:NULL\n"); + LOG_D("SHIFT:NULL"); } if (flag & KBD_LEFT_CTRL) { mod |= RTGUI_KMOD_LCTRL; - dbg_log(DBG_LOG,"CTRL:LEFT\n"); + LOG_D("CTRL:LEFT"); } else if (flag & KBD_RIGHT_CTRL) { mod |= RTGUI_KMOD_RCTRL; - dbg_log(DBG_LOG,"CTRL:RIGHT\n"); + LOG_D("CTRL:RIGHT"); } else { - dbg_log(DBG_LOG,"CTRL:NULL\n"); + LOG_D("CTRL:NULL"); } - dbg_log(DBG_LOG,"flag:0x%08x value:0x%x key:%s status:%s\n", \ + LOG_D("flag:0x%08x value:0x%x key:%s status:%s", \ flag, data, map[i].normal_key, press ==0 ? "UP" : "DOWN"); find_key = 1; break; @@ -244,7 +244,7 @@ static void keyboard_report_event(void * device, rt_uint32_t flag, rt_uint8_t da } if (find_key == 0) { - dbg_log(DBG_LOG,"flag:0x%08x value:0x%x key:%s status:%s\n", \ + LOG_D("flag:0x%08x value:0x%x key:%s status:%s", \ flag, data, "UNKNOWN", press ==0 ? "UP" : "DOWN"); return; } @@ -435,14 +435,14 @@ int rt_hw_keyboard_init(void) if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x050) { - dbg_log(DBG_ERROR, "read id fail id:0x%08x\n", id); + LOG_E("read id fail id:0x%08x", id); return RT_ERROR; } pdat = rt_malloc(sizeof(struct keyboard_pl050_pdata_t)); if(!pdat) { - dbg_log(DBG_ERROR, "malloc memory\n", id); + LOG_E("malloc memory", id); return RT_ERROR; } rt_memset(pdat, 0, sizeof(struct keyboard_pl050_pdata_t)); diff --git a/bsp/qemu-vexpress-a9/drivers/drv_mouse.c b/bsp/qemu-vexpress-a9/drivers/drv_mouse.c index 4e1920a635..5fc1434166 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_mouse.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_mouse.c @@ -115,7 +115,7 @@ void push_event_touch_move(int x, int y) emouse.ts = rt_tick_get(); emouse.id = emouse_id; - dbg_log(DBG_LOG, "[line]:%d motion event id:%d x:%d y:%d\n", __LINE__, emouse.id, x, y); + LOG_D("[line]:%d motion event id:%d x:%d y:%d", __LINE__, emouse.id, x, y); rtgui_server_post_event(&emouse.parent, sizeof(emouse)); } @@ -134,7 +134,7 @@ void push_event_touch_begin(int x, int y) emouse.y = y; emouse.ts = rt_tick_get(); emouse.id = emouse_id; - dbg_log(DBG_LOG, "[line]:%d down event id:%d x:%d y:%d\n", __LINE__, emouse.id, x, y); + LOG_D("[line]:%d down event id:%d x:%d y:%d", __LINE__, emouse.id, x, y); rtgui_server_post_event(&emouse.parent, sizeof(emouse)); } @@ -152,7 +152,7 @@ void push_event_touch_end(int x, int y) emouse.ts = rt_tick_get(); emouse.id = emouse_id; - dbg_log(DBG_LOG, "[line]:%d up event id:%d x:%d y:%d\n", __LINE__, emouse.id, x, y); + LOG_D("[line]:%d up event id:%d x:%d y:%d", __LINE__, emouse.id, x, y); rtgui_server_post_event(&emouse.parent, sizeof(emouse)); } @@ -239,14 +239,14 @@ int rt_hw_mouse_init(void) if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x050) { - dbg_log(DBG_ERROR, "read id fail id:0x%08x\n", id); + LOG_E("read id fail id:0x%08x", id); return RT_ERROR; } pdat = rt_malloc(sizeof(struct mouse_pl050_pdata_t)); if(!pdat) { - dbg_log(DBG_ERROR, "malloc memory\n", id); + LOG_E("malloc memory", id); return RT_ERROR; } rt_memset(pdat, 0, sizeof(struct mouse_pl050_pdata_t)); diff --git a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c index fa0ea725d6..5f2470f83d 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c @@ -121,14 +121,14 @@ static rt_err_t pl180_transfer_command(struct sdhci_pl180_pdata_t * pdat, struct do { status = read32(pdat->virt + PL180_STATUS); } while(!(status & (PL180_STAT_CMD_SENT | PL180_STAT_CMD_RESP_END | PL180_STAT_CMD_TIME_OUT | PL180_STAT_CMD_CRC_FAIL))); - dbg_log(DBG_LOG, "mmc status done!\n"); + LOG_D("mmc status done!"); if(cmd->resptype & PL180_RSP_PRESENT) { cmd->response[0] = read32(pdat->virt + PL180_RESP0); if(cmd->resptype & PL180_RSP_136BIT) { - dbg_log(DBG_LOG, "136bit response\n"); + LOG_D("136bit response"); cmd->response[1] = read32(pdat->virt + PL180_RESP1); cmd->response[2] = read32(pdat->virt + PL180_RESP2); cmd->response[3] = read32(pdat->virt + PL180_RESP3); @@ -344,17 +344,17 @@ static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re req->cmd->err = sdhci_pl180_transfer(sdhci, &cmd, RT_NULL); } - dbg_log(DBG_INFO, "cmdarg:%d\n", cmd.cmdarg); - dbg_log(DBG_INFO, "cmdidx:%d\n", cmd.cmdidx); + LOG_I("cmdarg:%d", cmd.cmdarg); + LOG_I("cmdidx:%d", cmd.cmdidx); - dbg_log(DBG_INFO, "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x\n", cmd.response[0], cmd.response[1], cmd.response[2], cmd.response[3]); + LOG_I("[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x", cmd.response[0], cmd.response[1], cmd.response[2], cmd.response[3]); req->cmd->resp[3] = cmd.response[3]; req->cmd->resp[2] = cmd.response[2]; req->cmd->resp[1] = cmd.response[1]; req->cmd->resp[0] = cmd.response[0]; if(req->cmd->err) - dbg_log(DBG_ERROR, "transfer cmd err \n"); + LOG_E("transfer cmd err "); if (req->stop) { @@ -381,7 +381,7 @@ static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io sdhci_pl180_setclock(sdhci, io_cfg->clock); sdhci_pl180_setwidth(sdhci, io_cfg->bus_width); - dbg_log(DBG_INFO, "clock:%d bus_width:%d\n", io_cfg->clock, io_cfg->bus_width); + LOG_I("clock:%d bus_width:%d", io_cfg->clock, io_cfg->bus_width); } static const struct rt_mmcsd_host_ops ops = @@ -403,14 +403,14 @@ int pl180_init(void) host = mmcsd_alloc_host(); if (!host) { - dbg_log(DBG_ERROR, "alloc host failed\n"); + LOG_E("alloc host failed"); goto err; } sdhci = rt_malloc(sizeof(struct sdhci_t)); if (!sdhci) { - dbg_log(DBG_ERROR, "alloc sdhci failed\n"); + LOG_E("alloc sdhci failed"); goto err; } rt_memset(sdhci, 0, sizeof(struct sdhci_t)); @@ -421,10 +421,10 @@ int pl180_init(void) ((read32((virt + 0xfe4)) & 0xff) << 8) | ((read32((virt + 0xfe0)) & 0xff) << 0)); - dbg_log(DBG_LOG, "id=0x%08x\n", id); + LOG_D("id=0x%08x", id); if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x181) { - dbg_log(DBG_ERROR, "check id failed\n"); + LOG_E("check id failed"); goto err; } diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.c b/bsp/qemu-vexpress-a9/drivers/drv_timer.c new file mode 100644 index 0000000000..a470142202 --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include "board.h" + +#define TIMER01_HW_BASE 0x10011000 +#define TIMER23_HW_BASE 0x10012000 + +#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) +#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) +#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) +#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) +#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) +#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) + +#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) +#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) +#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) +#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) +#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) +#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) + +#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) +#define TIMER_HW_BASE REALVIEW_TIMER2_3_BASE + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + /* clear interrupt */ + TIMER_INTCLR(TIMER_HW_BASE) = 0x01; +} + +int rt_hw_timer_init(void) +{ + rt_uint32_t val; + + SYS_CTRL |= REALVIEW_REFCLK; + + /* Setup Timer0 for generating irq */ + val = TIMER_CTRL(TIMER_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER_HW_BASE) = val; + + TIMER_LOAD(TIMER_HW_BASE) = 1000; + + /* enable timer */ + TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE; + + rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + +void timer_init(int timer, unsigned int preload) +{ + uint32_t val; + + if (timer == 0) + { + /* Setup Timer0 for generating irq */ + val = TIMER_CTRL(TIMER01_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER01_HW_BASE) = val; + + TIMER_LOAD(TIMER01_HW_BASE) = preload; + + /* enable timer */ + TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE; + } + else + { + /* Setup Timer1 for generating irq */ + val = TIMER_CTRL(TIMER23_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER23_HW_BASE) = val; + + TIMER_LOAD(TIMER23_HW_BASE) = preload; + + /* enable timer */ + TIMER_CTRL(TIMER23_HW_BASE) |= TIMER_CTRL_ENABLE; + } +} + +void timer_clear_pending(int timer) +{ + if (timer == 0) + { + TIMER_INTCLR(TIMER01_HW_BASE) = 0x01; + } + else + { + TIMER_INTCLR(TIMER23_HW_BASE) = 0x01; + } +} diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.h b/bsp/qemu-vexpress-a9/drivers/drv_timer.h new file mode 100644 index 0000000000..718f5d43cf --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#ifndef DRV_TIMER_H__ +#define DRV_TIMER_H__ + +void timer_init(int timer, unsigned int preload); +void timer_clear_pending(int timer); + +#endif diff --git a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c new file mode 100644 index 0000000000..b8b5436929 --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include "board.h" +#include "gic.h" +#include "drv_timer.h" + +#ifdef RT_USING_SMP +static void rt_hw_timer2_isr(int vector, void *param) +{ + rt_tick_increase(); + /* clear interrupt */ + timer_clear_pending(0); +} + +void rt_hw_secondary_cpu_up(void) +{ + extern void set_secondary_cpu_boot_address(void); + + set_secondary_cpu_boot_address(); + __asm__ volatile ("dsb":::"memory"); + rt_hw_ipi_send(0, 1 << 1); +} + +void secondary_cpu_c_start(void) +{ + rt_hw_vector_init(); + + rt_hw_spin_lock(&_cpus_lock); + + arm_gic_cpu_init(0, REALVIEW_GIC_CPU_BASE); + arm_gic_set_cpu(0, IRQ_PBA8_TIMER0_1, 0x2); + + timer_init(0, 1000); + rt_hw_interrupt_install(IRQ_PBA8_TIMER0_1, rt_hw_timer2_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_PBA8_TIMER0_1); + + /* install IPI interrupt */ + rt_hw_interrupt_install(RT_SCHEDULE_IPI_IRQ, rt_scheduler_ipi_handler, RT_NULL, "ipi"); + rt_hw_interrupt_umask(RT_SCHEDULE_IPI_IRQ); + + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + asm volatile ("wfe":::"memory", "cc"); +} + +#endif diff --git a/bsp/qemu-vexpress-a9/link.lds b/bsp/qemu-vexpress-a9/link.lds index 51b2ced922..78c38cde11 100644 --- a/bsp/qemu-vexpress-a9/link.lds +++ b/bsp/qemu-vexpress-a9/link.lds @@ -2,7 +2,7 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) SECTIONS { - . = 0x60000000; + . = 0x60010000; __text_start = .; .text : diff --git a/bsp/qemu-vexpress-a9/qemu-nographic.sh b/bsp/qemu-vexpress-a9/qemu-nographic.sh index 61abb6878d..b4168b8d5c 100755 --- a/bsp/qemu-vexpress-a9/qemu-nographic.sh +++ b/bsp/qemu-vexpress-a9/qemu-nographic.sh @@ -2,5 +2,5 @@ if [ ! -f "sd.bin" ]; then dd if=/dev/zero of=sd.bin bs=1024 count=65536 fi -qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -nographic -sd sd.bin -net nic -net tap +qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -nographic -sd sd.bin -net nic -net tap diff --git a/bsp/qemu-vexpress-a9/qemu.bat b/bsp/qemu-vexpress-a9/qemu.bat index 4a4acb3324..460020c151 100644 --- a/bsp/qemu-vexpress-a9/qemu.bat +++ b/bsp/qemu-vexpress-a9/qemu.bat @@ -3,4 +3,4 @@ if exist sd.bin goto run qemu-img create -f raw sd.bin 64M :run -qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.bin +qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -serial stdio -sd sd.bin diff --git a/bsp/qemu-vexpress-a9/qemu.sh b/bsp/qemu-vexpress-a9/qemu.sh index c8fef610c7..ff2cec6f81 100755 --- a/bsp/qemu-vexpress-a9/qemu.sh +++ b/bsp/qemu-vexpress-a9/qemu.sh @@ -2,4 +2,4 @@ if [ ! -f "sd.bin" ]; then dd if=/dev/zero of=sd.bin bs=1024 count=65536 fi -qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.bin +qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -serial stdio -sd sd.bin diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h index 9dd617da97..2ac692c692 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.h +++ b/bsp/qemu-vexpress-a9/rtconfig.h @@ -7,18 +7,33 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 +#define RT_USING_SMP +#define RT_CPUS_NR 2 #define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 1024 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 1024 #define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ /* Inter-Thread communication */ @@ -33,13 +48,17 @@ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP +/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMHEAP_AS_HEAP is not set */ #define RT_USING_MEMTRACE #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE +/* RT_USING_DEVICE_OPS is not set */ #define RT_USING_INTERRUPT_INFO #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 @@ -47,6 +66,7 @@ #define ARCH_ARM #define ARCH_ARM_CORTEX_A #define ARCH_ARM_CORTEX_A9 +/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ /* RT-Thread Components */ @@ -67,11 +87,14 @@ #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT +/* FINSH_USING_MSH_ONLY is not set */ #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -81,49 +104,78 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 16 +/* RT_USING_DFS_MNTTABLE is not set */ #define RT_USING_DFS_ELMFAT /* elm-chan's FatFs, Generic FAT Filesystem Module */ #define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS +/* RT_DFS_ELM_USE_LFN_0 is not set */ +/* RT_DFS_ELM_USE_LFN_1 is not set */ +/* RT_DFS_ELM_USE_LFN_2 is not set */ #define RT_DFS_ELM_USE_LFN_3 #define RT_DFS_ELM_USE_LFN 3 #define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +/* RT_DFS_ELM_USE_ERASE is not set */ #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS #define RT_USING_DFS_ROMFS #define RT_USING_DFS_RAMFS +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ +/* RT_USING_DFS_NFS is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN +/* RT_USING_ADC is not set */ +/* RT_USING_PWM is not set */ #define RT_USING_MTD_NOR #define RT_USING_MTD_NAND #define RT_MTD_NAND_DEBUG +/* RT_USING_MTD is not set */ +/* RT_USING_PM is not set */ #define RT_USING_RTC +#define RT_USING_SOFT_RTC #define RT_USING_SDIO #define RT_SDIO_STACK_SIZE 512 #define RT_SDIO_THREAD_PRIORITY 15 #define RT_MMCSD_STACK_SIZE 1024 #define RT_MMCSD_THREAD_PREORITY 22 #define RT_MMCSD_MAX_PARTITION 16 +/* RT_SDIO_DEBUG is not set */ #define RT_USING_SPI #define RT_USING_SPI_MSD #define RT_USING_SFUD #define RT_SFUD_USING_SFDP #define RT_SFUD_USING_FLASH_INFO_TABLE +/* RT_DEBUG_SFUD is not set */ +/* RT_USING_W25QXX is not set */ +/* RT_USING_GD is not set */ +/* RT_USING_ENC28J60 is not set */ +/* RT_USING_SPI_WIFI is not set */ #define RT_USING_WDT +/* RT_USING_AUDIO is not set */ + +/* Using WiFi */ + +/* RT_USING_WIFI is not set */ /* Using USB */ +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ @@ -133,6 +185,7 @@ #define RT_USING_POSIX_MMAP #define RT_USING_POSIX_TERMIOS #define RT_USING_POSIX_AIO +/* RT_USING_MODULE is not set */ /* Network */ @@ -149,9 +202,13 @@ /* light weight TCP/IP stack */ #define RT_USING_LWIP +/* RT_USING_LWIP141 is not set */ #define RT_USING_LWIP202 +/* RT_USING_LWIP210 is not set */ #define RT_USING_LWIP_IPV6 +/* RT_LWIP_IGMP is not set */ #define RT_LWIP_ICMP +/* RT_LWIP_SNMP is not set */ #define RT_LWIP_DNS #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 @@ -164,6 +221,8 @@ #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP +/* RT_LWIP_RAW is not set */ +/* RT_LWIP_PPP is not set */ #define RT_MEMP_NUM_NETCONN 8 #define RT_LWIP_PBUF_NUM 16 #define RT_LWIP_RAW_PCB_NUM 4 @@ -175,6 +234,8 @@ #define RT_LWIP_TCPTHREAD_PRIORITY 10 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 #define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +/* LWIP_NO_RX_THREAD is not set */ +/* LWIP_NO_TX_THREAD is not set */ #define RT_LWIP_ETHTHREAD_PRIORITY 12 #define RT_LWIP_ETHTHREAD_STACKSIZE 1024 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 @@ -184,68 +245,141 @@ #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +/* RT_LWIP_NETIF_LOOPBACK is not set */ #define LWIP_NETIF_LOOPBACK 0 +/* RT_LWIP_STATS is not set */ +/* RT_LWIP_DEBUG is not set */ /* Modbus master and slave stack */ +/* RT_USING_MODBUS is not set */ /* AT commands */ +/* RT_USING_AT is not set */ +/* LWIP_USING_DHCPD is not set */ /* VBUS(Virtual Software BUS) */ +/* RT_USING_VBUS is not set */ /* Utilities */ #define RT_USING_LOGTRACE #define LOG_TRACE_MAX_SESSION 16 +/* LOG_TRACE_USING_LEVEL_NOTRACE is not set */ +/* LOG_TRACE_USING_LEVEL_ERROR is not set */ +/* LOG_TRACE_USING_LEVEL_WARNING is not set */ #define LOG_TRACE_USING_LEVEL_INFO +/* LOG_TRACE_USING_LEVEL_VERBOSE is not set */ +/* LOG_TRACE_USING_LEVEL_DEBUG is not set */ +/* LOG_TRACE_USING_MEMLOG is not set */ +/* RT_USING_RYM is not set */ +/* RT_USING_ULOG is not set */ /* RT-Thread online packages */ /* IoT - internet of things */ +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ /* Wi-Fi */ /* Marvell WiFi */ +/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ /* IoT Cloud */ +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ /* security packages */ +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ /* language packages */ +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ /* tools packages */ +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ /* system packages */ +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_PERSIMMON is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ /* peripheral libraries and drivers */ +/* PKG_USING_STM32F4_HAL is not set */ +/* PKG_USING_STM32F4_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_AHT10 is not set */ /* miscellaneous packages */ +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ /* sample package */ +/* PKG_USING_SAMPLES is not set */ /* example package: hello */ +/* PKG_USING_HELLO is not set */ #define SOC_VEXPRESS_A9 #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_DRV_EMAC +/* BSP_DRV_AUDIO is not set */ #endif diff --git a/bsp/qemu-vexpress-a9/rtconfig.py b/bsp/qemu-vexpress-a9/rtconfig.py index 545ba76af9..3f833d682d 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.py +++ b/bsp/qemu-vexpress-a9/rtconfig.py @@ -32,7 +32,7 @@ if PLATFORM == 'gcc': DEVICE = ' -march=armv7-a -marm -msoft-float' CFLAGS = DEVICE + ' -Wall' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__ -I.' LINK_SCRIPT = 'link.lds' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors'+\ ' -T %s' % LINK_SCRIPT diff --git a/bsp/qemu-vexpress-gemini/.config b/bsp/qemu-vexpress-gemini/.config new file mode 100644 index 0000000000..02c5ee7d12 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/.config @@ -0,0 +1,322 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=6 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_USING_MODULE is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A9=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +# CONFIG_RT_USING_USER_MAIN is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=4 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +CONFIG_RT_USING_PTHREADS=y +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +CONFIG_RT_USING_VBUS=y +# CONFIG_RT_USING_VBUS_RFS is not set +# CONFIG_RT_USING_VBUS_RSHELL is not set +CONFIG_RT_VBUS_USING_TESTS=y +CONFIG__RT_VBUS_RING_BASE=0x6f800000 +CONFIG__RT_VBUS_RING_SZ=2097152 +CONFIG_RT_VBUS_GUEST_VIRQ=14 +CONFIG_RT_VBUS_HOST_VIRQ=15 +CONFIG_RT_VBUS_SHELL_DEV_NAME="vbser0" +CONFIG_RT_VBUS_RFS_DEV_NAME="rfs" + +# +# Utilities +# +CONFIG_RT_USING_LOGTRACE=y +CONFIG_LOG_TRACE_MAX_SESSION=16 +# CONFIG_LOG_TRACE_USING_LEVEL_NOTRACE is not set +# CONFIG_LOG_TRACE_USING_LEVEL_ERROR is not set +# CONFIG_LOG_TRACE_USING_LEVEL_WARNING is not set +CONFIG_LOG_TRACE_USING_LEVEL_INFO=y +# CONFIG_LOG_TRACE_USING_LEVEL_VERBOSE is not set +# CONFIG_LOG_TRACE_USING_LEVEL_DEBUG is not set +# CONFIG_LOG_TRACE_USING_MEMLOG is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_VEXPRESS_GEMINI=y +# CONFIG_RT_USING_UART0 is not set +CONFIG_RT_USING_UART1=y diff --git a/bsp/qemu-vexpress-gemini/Kconfig b/bsp/qemu-vexpress-gemini/Kconfig new file mode 100644 index 0000000000..680c776d0f --- /dev/null +++ b/bsp/qemu-vexpress-gemini/Kconfig @@ -0,0 +1,26 @@ +mainmenu "RT-Thread Project Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_VEXPRESS_GEMINI + bool + select ARCH_ARM_CORTEX_A9 + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/qemu-vexpress-gemini/SConscript b/bsp/qemu-vexpress-gemini/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/qemu-vexpress-gemini/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/tm4c129x-dk/SConstruct b/bsp/qemu-vexpress-gemini/SConstruct similarity index 85% rename from bsp/tm4c129x-dk/SConstruct rename to bsp/qemu-vexpress-gemini/SConstruct index 16877dd5b4..6fa1553e4d 100644 --- a/bsp/tm4c129x-dk/SConstruct +++ b/bsp/qemu-vexpress-gemini/SConstruct @@ -10,7 +10,7 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * -TARGET = 'rtthread.' + rtconfig.TARGET_EXT +TARGET = 'rtthread-vexpress.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, @@ -23,7 +23,7 @@ Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +objs = PrepareBuilding(env, RTT_ROOT,has_libcpu=True) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/tm4c129x-dk/applications/SConscript b/bsp/qemu-vexpress-gemini/applications/SConscript similarity index 100% rename from bsp/tm4c129x-dk/applications/SConscript rename to bsp/qemu-vexpress-gemini/applications/SConscript diff --git a/bsp/beaglebone/applications/application.c b/bsp/qemu-vexpress-gemini/applications/application.c similarity index 69% rename from bsp/beaglebone/applications/application.c rename to bsp/qemu-vexpress-gemini/applications/application.c index 04a09d081e..c0160df189 100644 --- a/bsp/beaglebone/applications/application.c +++ b/bsp/qemu-vexpress-gemini/applications/application.c @@ -12,22 +12,20 @@ * 2012-11-20 Bernard the first version */ -#include #include -#ifdef RT_USING_GDB -#include -#endif +void init_thread(void* parameter) +{ + rt_components_init(); +} int rt_application_init() { - /* do component initialization */ - rt_components_init(); + rt_thread_t tid; -#ifdef RT_USING_GDB - gdb_set_device("uart4"); - gdb_start(); -#endif + tid = rt_thread_create("init", init_thread, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX/3, 10); + if (tid != RT_NULL) rt_thread_startup(tid); return 0; } diff --git a/bsp/imx6sx/cortex-a9/applications/startup.c b/bsp/qemu-vexpress-gemini/applications/startup.c similarity index 96% rename from bsp/imx6sx/cortex-a9/applications/startup.c rename to bsp/qemu-vexpress-gemini/applications/startup.c index be041e0c0f..fa17c0571b 100644 --- a/bsp/imx6sx/cortex-a9/applications/startup.c +++ b/bsp/qemu-vexpress-gemini/applications/startup.c @@ -25,9 +25,6 @@ extern void rt_hw_board_init(void); */ void rtthread_startup(void) { - // platform_init(); - // print_version(); - /* initialzie hardware interrupt */ rt_hw_interrupt_init(); @@ -72,3 +69,4 @@ int main(void) return 0; } + diff --git a/bsp/qemu-vexpress-gemini/applications/vbus_echo.c b/bsp/qemu-vexpress-gemini/applications/vbus_echo.c new file mode 100644 index 0000000000..430d6efe26 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/applications/vbus_echo.c @@ -0,0 +1,108 @@ +#include +#include +#include + +#include + +#define BUFLEN 1024 +static char buf[BUFLEN]; + +static void _vbus_on_tx_cmp(void *p) +{ + struct rt_completion *cmp = p; + + rt_completion_done(cmp); +} + +static rt_size_t _vbus_write_sync(rt_device_t dev, void *buf, rt_size_t len) +{ + rt_size_t sd; + struct rt_completion cmp; + struct rt_vbus_dev_liscfg liscfg; + + rt_completion_init(&cmp); + liscfg.event = RT_VBUS_EVENT_ID_TX; + liscfg.listener = _vbus_on_tx_cmp; + liscfg.ctx = &cmp; + + rt_device_control(dev, VBUS_IOC_LISCFG, &liscfg); + sd = rt_device_write(dev, 0, buf, len); + + rt_completion_wait(&cmp, RT_WAITING_FOREVER); + + return sd; +} + +static void _rev_str(char *buf, rt_size_t len) +{ + char tmp; + rt_size_t i, mid; + + RT_ASSERT(buf); + + if (!len) + return; + + mid = len / 2; + for (i = 0; i < mid; i++) + { + tmp = buf[i]; + buf[i] = buf[len - 1 - i]; + buf[len - 1 - i] = tmp; + } +} + +static void _test_write(void *devname) +{ + int i; + rt_device_t dev; + + dev = rt_device_find(devname); + + if (!dev) + { + rt_kprintf("could not find %s\n", devname); + return; + } + +again: + i = rt_device_open(dev, RT_DEVICE_OFLAG_RDWR); + if (i) + { + rt_kprintf("open dev err:%d\n", i); + return; + } + + for (i = 0; i < sizeof(buf) - 1;i++) + { + int len; + + len = rt_device_read(dev, 0, buf + i, 1); + if (len != 1 || buf[i] == '\n') + break; + } + buf[i] = '\0'; + rt_kprintf("recv: %s\n", buf); + /* Don't swap the \n. */ + _rev_str(buf, i - 1); + /* Don't write the \0. */ + rt_kprintf("write: %s\n", buf); + _vbus_write_sync(dev, buf, i - 1); + + rt_device_close(dev); + goto again; +} + +int vser_echo_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("vecho", _test_write, "vecho", + 1024, 0, 20); + RT_ASSERT(tid); + return rt_thread_startup(tid); +} + +#ifdef RT_USING_COMPONENTS_INIT +INIT_APP_EXPORT(vser_echo_init); +#endif diff --git a/bsp/qemu-vexpress-gemini/build.sh b/bsp/qemu-vexpress-gemini/build.sh new file mode 100755 index 0000000000..6e7330a21b --- /dev/null +++ b/bsp/qemu-vexpress-gemini/build.sh @@ -0,0 +1,2 @@ +scons +cp rtthread.bin $MO_DIR diff --git a/bsp/qemu-vexpress-gemini/cpu/SConscript b/bsp/qemu-vexpress-gemini/cpu/SConscript new file mode 100644 index 0000000000..61057c04cc --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/SConscript @@ -0,0 +1,17 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') +elif rtconfig.PLATFORM == 'gcc': + src += Glob('*_gcc.S') +elif rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/qemu-vexpress-gemini/cpu/armv7.h b/bsp/qemu-vexpress-gemini/cpu/armv7.h new file mode 100644 index 0000000000..69c556eb3c --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/armv7.h @@ -0,0 +1,64 @@ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/bsp/qemu-vexpress-gemini/cpu/context_gcc.S b/bsp/qemu-vexpress-gemini/cpu/context_gcc.S new file mode 100644 index 0000000000..01593a7c0a --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/context_gcc.S @@ -0,0 +1,105 @@ +/* + * File : context.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .text, "ax" +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid i + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr, r0 + bx lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + +.section .bss.share.isr +_guest_switch_lvl: + .word 0 + +.globl vmm_virq_update + +.section .text.isr, "ax" +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + orrne r4, r4, #0x20 @ it's thumb code + + stmfd sp!, {r4} @ push cpsr + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task cpsr to spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r0, [ip] + str r3, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr diff --git a/bsp/qemu-vexpress-gemini/cpu/cp15.h b/bsp/qemu-vexpress-gemini/cpu/cp15.h new file mode 100644 index 0000000000..ebea3f0fe3 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/cp15.h @@ -0,0 +1,12 @@ +#ifndef __CP15_H__ +#define __CP15_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S b/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S new file mode 100644 index 0000000000..f1ed6492aa --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S @@ -0,0 +1,140 @@ +/* + * File : cp15_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * http://www.rt-thread.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7ff + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_cpu_mmu_disable +rt_cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl rt_cpu_mmu_enable +rt_cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl rt_cpu_tlb_set +rt_cpu_tlb_set: + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr diff --git a/bsp/qemu-vexpress-gemini/cpu/cpu.c b/bsp/qemu-vexpress-gemini/cpu/cpu.c new file mode 100644 index 0000000000..7dd426e4dd --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/cpu.c @@ -0,0 +1,37 @@ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/bsp/qemu-vexpress-gemini/cpu/gic.c b/bsp/qemu-vexpress-gemini/cpu/gic.c new file mode 100644 index 0000000000..4cff1bad3e --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/gic.c @@ -0,0 +1,316 @@ +/* + * File : gic.c, ARM Generic Interrupt Controller + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + */ + +#include +#include + +#include "gic.h" +#include "cp15.h" + +struct arm_gic +{ + rt_uint32_t offset; + + rt_uint32_t dist_hw_base; + rt_uint32_t cpu_hw_base; +}; +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) + +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_pending(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n"); +} +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); +#endif + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) + _gic_max_irq = ARM_GIC_NR_IRQS; + +#ifndef RT_PRETENT_AS_CPU0 + /* If we are run on the second core, the GIC should have already been setup + * by BootStrapProcessor. */ + if ((rt_cpu_get_smp_id() & 0xF) != 0) + return 0; +#endif +#ifdef RT_USING_VMM + return 0; +#endif + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; + + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x03; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + +#ifndef RT_PRETENT_AS_CPU0 + /* If we are run on the second core, the GIC should have already been setup + * by BootStrapProcessor. */ + if ((rt_cpu_get_smp_id() & 0xF) != 0) + return 0; +#endif +#ifdef RT_USING_VMM + return 0; +#endif + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_set_group(rt_uint32_t index, int vector, int group) +{ + /* As for GICv2, there are only group0 and group1. */ + RT_ASSERT(group <= 1); + RT_ASSERT(vector < _gic_max_irq); + + if (group == 0) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) &= ~(1 << (vector % 32)); + } + else if (group == 1) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) |= (1 << (vector % 32)); + } +} + +void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) +{ + unsigned int reg; + + RT_ASSERT(irq <= 15); + RT_ASSERT(target_cpu <= 255); + + reg = (target_cpu << 16) | irq; + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; +} + +void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) +{ + RT_ASSERT(irq <= 15); + RT_ASSERT(target_cpu <= 255); + + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4); +} diff --git a/bsp/qemu-vexpress-gemini/cpu/gic.h b/bsp/qemu-vexpress-gemini/cpu/gic.h new file mode 100644 index 0000000000..41a7727da2 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/gic.h @@ -0,0 +1,35 @@ +/* + * File : gic.h, ARM Generic Interrupt Controller + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +void arm_gic_set_group(rt_uint32_t index, int vector, int group); + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); +void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); + +void arm_gic_dump_type(rt_uint32_t index); + +#endif + diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.c b/bsp/qemu-vexpress-gemini/cpu/interrupt.c new file mode 100644 index 0000000000..a189566222 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.c @@ -0,0 +1,146 @@ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + * 2014-04-03 Grissiom port to VMM + */ + +#include +#include +#include "realview.h" +#include "gic.h" +#include "cp15.h" + +#ifdef RT_USING_VMM +#include +#endif + +#define MAX_HANDLERS NR_IRQS_PBA8 + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +extern void rt_cpu_vector_set_base(unsigned int addr); +extern int system_vectors; + +static void rt_hw_vector_init(void) +{ + int sctrl; + unsigned int *src = (unsigned int *)&system_vectors; + + /* C12-C0 is only active when SCTLR.V = 0 */ + asm volatile ("mrc p15, #0, %0, c1, c0, #0" + :"=r" (sctrl)); + sctrl &= ~(1 << 13); + asm volatile ("mcr p15, #0, %0, c1, c0, #0" + : + :"r" (sctrl)); + + asm volatile ("mcr p15, #0, %0, c12, c0, #0" + : + :"r" (src)); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t gic_cpu_base; + rt_uint32_t gic_dist_base; + + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = REALVIEW_GIC_DIST_BASE; + gic_cpu_base = REALVIEW_GIC_CPU_BASE; + arm_gic_dist_init(0, gic_dist_base, 0); + arm_gic_cpu_init(0, gic_cpu_base); + /*arm_gic_dump_type(0);*/ + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); + } + + return old_handler; +} + +/** + * Trigger a software IRQ + * + * Since we are running in single core, the target CPU are always CPU0. + */ +void rt_hw_interrupt_trigger(int vector) +{ + arm_gic_trigger(0, 1, vector); +} + +void rt_hw_interrupt_clear(int vector) +{ + arm_gic_clear_sgi(0, 1, vector); +} diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.h b/bsp/qemu-vexpress-gemini/cpu/interrupt.h new file mode 100644 index 0000000000..d81f1c81ae --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.h @@ -0,0 +1,50 @@ +/* + * File : interrupt.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) +#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) + +void rt_hw_interrupt_control(int vector, int priority, int route); +int rt_hw_interrupt_get_active(int fiq_irq); +void rt_hw_interrupt_ack(int fiq_irq); +void rt_hw_interrupt_trigger(int vector); +void rt_hw_interrupt_clear(int vector); + +#endif diff --git a/bsp/qemu-vexpress-gemini/cpu/mmu.c b/bsp/qemu-vexpress-gemini/cpu/mmu.c new file mode 100644 index 0000000000..b2503e4260 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/mmu.c @@ -0,0 +1,207 @@ +/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + */ + +#include +#include +#include + +#include "cp15.h" + +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO +#define XN (1<<4) // eXecute Never + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* Read/Write, cache, write back */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +/* Read/Write, cache, write through */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +/* Read/Write without cache and write buffer */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +/* Read/Write without cache and write buffer, no execute */ +#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) +/* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_mmu_init(void) +{ + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /* set page table */ + /* 4G 1:1 memory */ + rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB); + /* IO memory region */ + rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/bsp/qemu-vexpress-gemini/cpu/pmu.c b/bsp/qemu-vexpress-gemini/cpu/pmu.c new file mode 100644 index 0000000000..07911a2db7 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/pmu.c @@ -0,0 +1,12 @@ +#include +#include "pmu.h" + +void rt_hw_pmu_dump_feature(void) +{ + unsigned long reg; + + reg = rt_hw_pmu_get_control(); + rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", + reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); + RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); +} diff --git a/bsp/qemu-vexpress-gemini/cpu/pmu.h b/bsp/qemu-vexpress-gemini/cpu/pmu.h new file mode 100644 index 0000000000..05c1420dd8 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/pmu.h @@ -0,0 +1,151 @@ +#ifndef __PMU_H__ +#define __PMU_H__ + +#include "board.h" + +/* Number of counters */ +#define ARM_PMU_CNTER_NR 4 + +enum rt_hw_pmu_event_type { + ARM_PMU_EVENT_PMNC_SW_INCR = 0x00, + ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01, + ARM_PMU_EVENT_ITLB_REFILL = 0x02, + ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03, + ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04, + ARM_PMU_EVENT_DTLB_REFILL = 0x05, + ARM_PMU_EVENT_MEM_READ = 0x06, + ARM_PMU_EVENT_MEM_WRITE = 0x07, + ARM_PMU_EVENT_INSTR_EXECUTED = 0x08, + ARM_PMU_EVENT_EXC_TAKEN = 0x09, + ARM_PMU_EVENT_EXC_EXECUTED = 0x0A, + ARM_PMU_EVENT_CID_WRITE = 0x0B, +}; + +/* Enable bit */ +#define ARM_PMU_PMCR_E (0x01 << 0) +/* Event counter reset */ +#define ARM_PMU_PMCR_P (0x01 << 1) +/* Cycle counter reset */ +#define ARM_PMU_PMCR_C (0x01 << 2) +/* Cycle counter divider */ +#define ARM_PMU_PMCR_D (0x01 << 3) + +#ifdef __GNUC__ +rt_inline void rt_hw_pmu_enable_cnt(int divide64) +{ + unsigned long pmcr; + unsigned long pmcntenset; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C; + if (divide64) + pmcr |= ARM_PMU_PMCR_D; + else + pmcr &= ~ARM_PMU_PMCR_D; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + + /* enable all the counters */ + pmcntenset = ~0; + asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset)); + /* clear overflows(just in case) */ + asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset)); +} + +rt_inline unsigned long rt_hw_pmu_get_control(void) +{ + unsigned long pmcr; + asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + return pmcr; +} + +rt_inline unsigned long rt_hw_pmu_get_ceid(void) +{ + unsigned long reg; + /* only PMCEID0 is supported, PMCEID1 is RAZ. */ + asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_cnten(void) +{ + unsigned long pmcnt; + asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt)); + return pmcnt; +} + +rt_inline void rt_hw_pmu_reset_cycle(void) +{ + unsigned long pmcr; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_C; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile ("isb"); +} + +rt_inline void rt_hw_pmu_reset_event(void) +{ + unsigned long pmcr; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_P; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile ("isb"); +} + +rt_inline unsigned long rt_hw_pmu_get_cycle(void) +{ + unsigned long cyc; + asm volatile ("isb"); + asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc)); + return cyc; +} + +rt_inline void rt_hw_pmu_select_counter(int idx) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx)); + /* Linux add an isb here, don't know why here. */ + asm volatile ("isb"); +} + +rt_inline void rt_hw_pmu_select_event(int idx, + enum rt_hw_pmu_event_type eve) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + rt_hw_pmu_select_counter(idx); + asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve)); +} + +rt_inline unsigned long rt_hw_pmu_read_counter(int idx) +{ + unsigned long reg; + + rt_hw_pmu_select_counter(idx); + asm volatile ("isb"); + asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_ovsr(void) +{ + unsigned long reg; + asm volatile ("isb"); + asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); + return reg; +} + +rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) +{ + asm ("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg)); + asm volatile ("isb"); +} + +#endif + +void rt_hw_pmu_dump_feature(void); + +#endif /* end of include guard: __PMU_H__ */ + diff --git a/bsp/qemu-vexpress-gemini/cpu/stack.c b/bsp/qemu-vexpress-gemini/cpu/stack.c new file mode 100644 index 0000000000..4ae1536a20 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/stack.c @@ -0,0 +1,65 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S new file mode 100644 index 0000000000..ca8c1f930f --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S @@ -0,0 +1,249 @@ +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000100 +.equ ABT_Stack_Size, 0x00000000 +.equ RT_FIQ_STACK_PGSZ, 0x00000000 +.equ RT_IRQ_STACK_PGSZ, 0x00000100 +.equ USR_Stack_Size, 0x00000100 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) + +.section .data.share.isr +/* stack */ +.globl stack_start +.globl stack_top + +stack_start: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top: + +.text +/* reset entry */ +.globl _reset +_reset: + bl rt_cpu_mmu_disable + /* set the cpu to SVC32 mode and disable interrupt */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0x13 + msr cpsr_c, r0 + + /* setup stack */ + bl stack_setup + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup +_rtthread_startup: + .word rtthread_startup + +stack_setup: + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_FIQ_STACK_PGSZ + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_IRQ_STACK_PGSZ + + /* come back to SVC mode */ + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + bx lr + +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ +.section .text.isr, "ax" + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc, lr, #4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + +.globl rt_current_thread +.globl vmm_thread +.globl vmm_virq_check + + .align 5 +.globl vector_irq +vector_irq: + stmfd sp!, {r0-r12,lr} + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. If the usr mode guest is + @ interrupted, this will just switch to the stack of kernel space. + @ save the registers in kernel space won't trigger data abort. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] @ get new task's stack pointer + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 + .globl vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + bl rt_hw_trap_undef + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/bsp/qemu-vexpress-gemini/cpu/trap.c b/bsp/qemu-vexpress-gemini/cpu/trap.c new file mode 100644 index 0000000000..a6397d20d2 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/trap.c @@ -0,0 +1,204 @@ +/* + * File : trap.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include + +#include "armv7.h" + +#ifdef RT_USING_VMM +#include +#endif + +#include "gic.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK 0x000003ff + +void rt_hw_trap_irq(void) +{ + void *param; + unsigned long ir; + unsigned long fullir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + fullir = arm_gic_get_active_irq(0); + ir = fullir & GIC_ACK_INTID_MASK; + + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } +#ifdef RT_USING_VMM + else + { + /* We have to EOI before masking the interrupts */ + arm_gic_ack(0, fullir); + vmm_virq_pending(ir); + return; + } +#endif + + /* end of interrupt */ + arm_gic_ack(0, fullir); +} + +void rt_hw_trap_fiq(void) +{ + void *param; + unsigned long ir; + unsigned long fullir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + fullir = arm_gic_get_active_irq(0); + ir = fullir & GIC_ACK_INTID_MASK; + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + + /* end of interrupt */ + arm_gic_ack(0, fullir); +} + diff --git a/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S b/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S new file mode 100644 index 0000000000..4a44a7395c --- /dev/null +++ b/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S @@ -0,0 +1,65 @@ +/* + * File : vector_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef diff --git a/bsp/qemu-vexpress-gemini/drivers/Kconfig b/bsp/qemu-vexpress-gemini/drivers/Kconfig new file mode 100644 index 0000000000..f65ac0c6d3 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/Kconfig @@ -0,0 +1,7 @@ +config RT_USING_UART0 + bool "Enable UART0" + default n + +config RT_USING_UART1 + bool "Enable UART1" + default y diff --git a/bsp/qemu-vexpress-gemini/drivers/SConscript b/bsp/qemu-vexpress-gemini/drivers/SConscript new file mode 100644 index 0000000000..9987f53e4b --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/SConscript @@ -0,0 +1,13 @@ +import copy +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/qemu-vexpress-gemini/drivers/board.c b/bsp/qemu-vexpress-gemini/drivers/board.c new file mode 100644 index 0000000000..3de322c52e --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/board.c @@ -0,0 +1,87 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + */ + +#include +#include + +#include "board.h" + +#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) +#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) +#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) +#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) +#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) +#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) + +#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) + +#define TIMER_HW_BASE REALVIEW_TIMER2_3_BASE + +void rt_hw_timer_ack(void) +{ + /* clear interrupt */ + TIMER_INTCLR(TIMER_HW_BASE) = 0x01; +} + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + + rt_hw_timer_ack(); +} + +int rt_hw_timer_init(void) +{ + rt_uint32_t val; + + SYS_CTRL |= REALVIEW_REFCLK; + + /* Setup Timer0 for generating irq */ + val = TIMER_CTRL(TIMER_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER_HW_BASE) = val; + + TIMER_LOAD(TIMER_HW_BASE) = 1000; + + /* enable timer */ + TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE; + + rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + +/** + * This function will initialize beaglebone board + */ +void rt_hw_board_init(void) +{ + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +/*@}*/ diff --git a/bsp/qemu-vexpress-gemini/drivers/board.h b/bsp/qemu-vexpress-gemini/drivers/board.h new file mode 100644 index 0000000000..0a9bb3670c --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/board.h @@ -0,0 +1,32 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#define HEAP_END (void*)(0x70000000) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/qemu-vexpress-gemini/drivers/realview.h b/bsp/qemu-vexpress-gemini/drivers/realview.h new file mode 100644 index 0000000000..1780583e80 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/realview.h @@ -0,0 +1,342 @@ +#ifndef __AM33XX_H__ +#define __AM33XX_H__ + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +/* + * Peripheral memory map + * Address range Size Description + * 0xE000_0000-0xFFFF_FFFF 512MB External AXI between daughterboards + * 0xA000_0000-0xDFFF_FFFF 1GB Daughterboard, private + * 0x8000_0000-0x9FFF_FFFF 512MB Local DDR2 + * 0x8000_0000-0x81FF_FFFF 64MB Remappable memory location + * 0x6000_0000-0x7FFF_FFFF 512MB Local DDR2 lower + * 0x5C00-0000-0x5FFF_FFFF 64MB Reserved + * 0x4000_0000-0x5BFF_FFFF 448MB Motherboard peripherals, typically, memory devices + * 0x2000_0000-0x3FFF_FFFF 512MB Reserved + * 0x1002_0000-0x1FFF_FFFF ~256MB Daughterboard, private + * 0x1000_0000-0x1001_FFFF 128KB Motherboard peripherals, CS7 + * 0x0000_0000-0x0FFF_FFFF 64MB Remappable memory section + */ + +/* + * Peripheral addresses + */ +#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ +#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ +#define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ +#define REALVIEW_SCTL_BASE 0x1001A000 /* System Controller */ +#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ +#define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */ +#define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */ +#define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */ + +#define REALVIEW_GIC_CPU_BASE 0x1E000100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ + +#define REALVIEW_FLASH0_BASE 0x40000000 +#define REALVIEW_FLASH0_SIZE SZ_64M +#define REALVIEW_FLASH1_BASE 0x44000000 +#define REALVIEW_FLASH1_SIZE SZ_64M +#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ +#define REALVIEW_USB_BASE 0x4F000000 /* USB */ +#define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */ +#define REALVIEW_SDRAM6_BASE 0x60000000 /* SDRAM bank 6 256MB */ +#define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ + +#define REALVIEW_SYS_PLD_CTRL1 0x74 + +/* + * PCI regions + */ +#define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */ +#define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ +#define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ + +#define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */ +#define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */ +#define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */ + +/* + * Memory definitions + */ +#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */ +#define REALVIEW_BOOT_ROM_HI 0x30000000 +#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ +#define REALVIEW_BOOT_ROM_SIZE SZ_64M + +#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ +#define REALVIEW_SSRAM_SIZE SZ_2M + +/* + * SDRAM + */ +#define REALVIEW_SDRAM_BASE 0x00000000 + +/* + * Logic expansion modules + * + */ +#define IRQ_PBA8_GIC_START 32 + +/* + * PB-A8 on-board gic irq sources + */ +#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ +#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 2) /* Timer 0/1 (default timer) */ +#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 3) /* Timer 2/3 */ +#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */ +/* 9 reserved */ +#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 4) /* Real Time Clock */ +#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 5) /* UART 0 on development chip */ +#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 6) /* UART 1 on development chip */ +#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 7) /* UART 2 on development chip */ +#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 8) /* UART 3 on development chip */ +#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ +#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ +#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ +#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ +#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ +#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ +#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ +#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ + +#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */ + +/* ... */ +#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) +#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) +#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) +#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) + +#define IRQ_PBA8_SMC -1 +#define IRQ_PBA8_SCTL -1 + +#define NR_GIC_PBA8 1 + +/* + * Only define NR_IRQS if less than NR_IRQS_PBA8 + */ +#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) + +/* ------------------------------------------------------------------------ + * RealView Registers + * ------------------------------------------------------------------------ + * + */ +#define REALVIEW_SYS_ID_OFFSET 0x00 +#define REALVIEW_SYS_SW_OFFSET 0x04 +#define REALVIEW_SYS_LED_OFFSET 0x08 +#define REALVIEW_SYS_OSC0_OFFSET 0x0C + +#define REALVIEW_SYS_OSC1_OFFSET 0x10 +#define REALVIEW_SYS_OSC2_OFFSET 0x14 +#define REALVIEW_SYS_OSC3_OFFSET 0x18 +#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ + +#define REALVIEW_SYS_LOCK_OFFSET 0x20 +#define REALVIEW_SYS_100HZ_OFFSET 0x24 +#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 +#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C +#define REALVIEW_SYS_FLAGS_OFFSET 0x30 +#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 +#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 +#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 +#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 +#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C +#define REALVIEW_SYS_RESETCTL_OFFSET 0x40 +#define REALVIEW_SYS_PCICTL_OFFSET 0x44 +#define REALVIEW_SYS_MCI_OFFSET 0x48 +#define REALVIEW_SYS_FLASH_OFFSET 0x4C +#define REALVIEW_SYS_CLCD_OFFSET 0x50 +#define REALVIEW_SYS_CLCDSER_OFFSET 0x54 +#define REALVIEW_SYS_BOOTCS_OFFSET 0x58 +#define REALVIEW_SYS_24MHz_OFFSET 0x5C +#define REALVIEW_SYS_MISC_OFFSET 0x60 +#define REALVIEW_SYS_IOSEL_OFFSET 0x70 +#define REALVIEW_SYS_PROCID_OFFSET 0x84 +#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 +#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 +#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 +#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC +#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 + +#define REALVIEW_SYS_BASE 0x10000000 +#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) +#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) +#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) +#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) +#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) + +#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) +#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) +#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) +#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) +#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) +#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) +#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) +#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) +#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) +#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) +#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) +#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) +#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) +#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) +#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) +#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) +#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) +#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) +#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) +#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) +#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) +#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) +#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) +#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) +#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) +#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) + +#define REALVIEW_SYS_CTRL_LED (1 << 0) + +/* ------------------------------------------------------------------------ + * RealView control registers + * ------------------------------------------------------------------------ + */ + +/* + * REALVIEW_IDFIELD + * + * 31:24 = manufacturer (0x41 = ARM) + * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) + * 15:12 = FPGA (0x3 = XVC600 or XVC600E) + * 11:4 = build value + * 3:0 = revision number (0x1 = rev B (AHB)) + */ + +/* + * REALVIEW_SYS_LOCK + * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, + * SYS_CLD, SYS_BOOTCS + */ +#define REALVIEW_SYS_LOCK_LOCKED (1 << 16) +#define REALVIEW_SYS_LOCKVAL 0xA05F +#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ + +/* + * REALVIEW_SYS_FLASH + */ +#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ + +/* + * REALVIEW_INTREG + * - used to acknowledge and control MMCI and UART interrupts + */ +#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ +#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ +#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ +/* write 1 to acknowledge and clear */ +#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ +#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ + +/* + * LED settings, bits [7:0] + */ +#define REALVIEW_SYS_LED0 (1 << 0) +#define REALVIEW_SYS_LED1 (1 << 1) +#define REALVIEW_SYS_LED2 (1 << 2) +#define REALVIEW_SYS_LED3 (1 << 3) +#define REALVIEW_SYS_LED4 (1 << 4) +#define REALVIEW_SYS_LED5 (1 << 5) +#define REALVIEW_SYS_LED6 (1 << 6) +#define REALVIEW_SYS_LED7 (1 << 7) + +#define ALL_LEDS 0xFF + +#define LED_BANK REALVIEW_SYS_LED + +/* + * Control registers + */ +#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ +#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ +#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ +#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ + +/* + * Clean base - dummy + * + */ +#define CLEAN_BASE REALVIEW_BOOT_ROM_HI + +/* + * System controller bit assignment + */ +#define REALVIEW_REFCLK 0 +#define REALVIEW_TIMCLK 1 + +#define REALVIEW_TIMER1_EnSel 15 +#define REALVIEW_TIMER2_EnSel 17 +#define REALVIEW_TIMER3_EnSel 19 +#define REALVIEW_TIMER4_EnSel 21 + +/* + *struct rt_hw_register + *{ + * unsigned long r0; + * unsigned long r1; + * unsigned long r2; + * unsigned long r3; + * unsigned long r4; + * unsigned long r5; + * unsigned long r6; + * unsigned long r7; + * unsigned long r8; + * unsigned long r9; + * unsigned long r10; + * unsigned long fp; + * unsigned long ip; + * unsigned long sp; + * unsigned long lr; + * unsigned long pc; + * unsigned long cpsr; + * unsigned long ORIG_r0; + *}; + */ + +#include + +/* Interrupt Control Interface */ +#define ARM_GIC_CPU_BASE 0x1E000000 + +/* number of interrupts on board */ +#define ARM_GIC_NR_IRQS 96 +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 + +#endif + diff --git a/bsp/qemu-vexpress-gemini/drivers/serial.c b/bsp/qemu-vexpress-gemini/drivers/serial.c new file mode 100644 index 0000000000..92e8b949fa --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/serial.c @@ -0,0 +1,195 @@ +/* + * serial.c UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * Maintainer: bernard.xiong + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#include +#include + +#include "serial.h" + +struct hw_uart_device +{ + rt_uint32_t hw_base; + rt_uint32_t irqno; +}; + +#define UART_DR(base) __REG32(base + 0x00) +#define UART_FR(base) __REG32(base + 0x18) +#define UART_CR(base) __REG32(base + 0x30) +#define UART_IMSC(base) __REG32(base + 0x38) +#define UART_ICR(base) __REG32(base + 0x44) + +#define UARTFR_RXFE 0x10 +#define UARTFR_TXFF 0x20 +#define UARTIMSC_RXIM 0x10 +#define UARTIMSC_TXIM 0x20 +#define UARTICR_RXIC 0x10 +#define UARTICR_TXIC 0x20 + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_IMSC(uart->hw_base) &= ~UARTIMSC_RXIM; + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_IMSC(uart->hw_base) |= UARTIMSC_RXIM; + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart"); + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while (UART_FR(uart->hw_base) & UARTFR_TXFF); + UART_DR(uart->hw_base) = c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + ch = -1; + if (!(UART_FR(uart->hw_base) & UARTFR_RXFE)) + { + ch = UART_DR(uart->hw_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + REALVIEW_UART0_BASE, + IRQ_PBA8_UART0, +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + REALVIEW_UART1_BASE, + IRQ_PBA8_UART1, +}; +static struct rt_serial_device _serial1; +#endif + +int uart_isr_test(void) +{ + return uart_getc(&_serial1); +} + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config; + + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + +#ifdef RT_USING_UART0 + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + /* enable Rx and Tx of UART */ + UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9); +#endif + +#ifdef RT_USING_UART1 + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + /* enable Rx and Tx of UART */ + UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9); +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/qemu-vexpress-gemini/drivers/serial.h b/bsp/qemu-vexpress-gemini/drivers/serial.h new file mode 100644 index 0000000000..52e6f07ea3 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/serial.h @@ -0,0 +1,39 @@ +/* + * UART driver + * + * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * Maintainer: bernard.xiong + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-03-30 Bernard the first verion + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include + +int rt_hw_uart_init(void); + +#endif + + diff --git a/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c b/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c new file mode 100644 index 0000000000..0f522a271d --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c @@ -0,0 +1,120 @@ +/* + * VMM Bus Driver + * + * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd + * http://www.rt-thread.com + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2015-01-07 Grissiom add comment + */ + +#include + +#ifdef RT_USING_VBUS +#include +#include +#include +#include +#include + +int rt_vbus_do_init(void) +{ + return rt_vbus_init((void*)_RT_VBUS_RING_BASE, + (void*)(_RT_VBUS_RING_BASE + _RT_VBUS_RING_SZ)); +} +INIT_COMPONENT_EXPORT(rt_vbus_do_init); + +static void _bus_resume_in_thread(int irqnr, void *param) +{ + rt_vbus_isr(irqnr, RT_NULL); +} + +int rt_vbus_hw_init(void) +{ + rt_kprintf("install irq: %d\n", RT_VBUS_HOST_VIRQ); + rt_hw_interrupt_install(RT_VBUS_HOST_VIRQ, + _bus_resume_in_thread, RT_NULL, + "vbusin"); + rt_hw_interrupt_umask(RT_VBUS_HOST_VIRQ); + + return 0; +} + +int rt_vbus_hw_eoi(int irqnr, void *param) +{ + rt_hw_interrupt_clear(irqnr); + + return 0; +} + +#define RT_VBUS_SER_PRIO 20 +#define RT_VBUS_RFS_PRIO 19 +#define RT_VBUS_TASK2_PRIO 6 +#define RT_VBUS_INT_PRIO 4 + +struct rt_vbus_dev rt_vbus_chn_devx[] = { + { + .req = + { + .prio = RT_VBUS_SER_PRIO, + .name = RT_VBUS_SHELL_DEV_NAME, + .is_server = 1, + .recv_wm.low = RT_VMM_RB_BLK_NR / 3, + .recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3, + .post_wm.low = RT_VMM_RB_BLK_NR / 3, + .post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3, + } + }, + { + .req = + { + .prio = 23, + .name = RT_VBUS_RFS_DEV_NAME, + .is_server = 0, + .recv_wm.low = RT_VMM_RB_BLK_NR / 3, + .recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3, + .post_wm.low = RT_VMM_RB_BLK_NR / 3, + .post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3, + } + }, + { + .req = + { + .prio = 30, + .name = "vecho", + .is_server = 1, + .recv_wm.low = RT_VMM_RB_BLK_NR / 3, + .recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3, + .post_wm.low = RT_VMM_RB_BLK_NR / 3, + .post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3, + } + }, + { + .req = + { + .name = RT_NULL, + } + }, +}; + +#endif /* RT_USING_VBUS */ + diff --git a/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h b/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h new file mode 100644 index 0000000000..7eb02f2588 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h @@ -0,0 +1,54 @@ +/* + * VMM Bus + * + * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd + * + * This file is part of RT-Thread (http://www.rt-thread.org) + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2015-01-07 Grissiom init commit + */ + +#include +#include +#include + +rt_inline void rt_vbus_tick(unsigned int target_cpu, unsigned int irqnr) +{ + arm_gic_trigger(0, 1, irqnr); +} + +/* Read memory barrier. */ +rt_inline void rt_vbus_smp_rmb(void) +{ + asm volatile ("dsb" : : : "memory"); +} + +/* Write memory barrier. */ +rt_inline void rt_vbus_smp_wmb(void) +{ + asm volatile ("dsb" : : : "memory"); +} + +/* General memory barrier. */ +rt_inline void rt_vbus_smp_mb(void) +{ + asm volatile ("dsb" : : : "memory"); +} diff --git a/bsp/qemu-vexpress-gemini/qemu.sh b/bsp/qemu-vexpress-gemini/qemu.sh new file mode 100755 index 0000000000..ad506c0d46 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/qemu.sh @@ -0,0 +1 @@ +qemu-system-arm -M vexpress-a9 -cpu cortex-a9 -m 256M -kernel rtthread-vexpress.elf -serial vc -serial vc diff --git a/bsp/qemu-vexpress-gemini/rtconfig.h b/bsp/qemu-vexpress-gemini/rtconfig.h new file mode 100644 index 0000000000..a1dcba1248 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/rtconfig.h @@ -0,0 +1,289 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 6 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMTRACE is not set */ +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +/* RT_USING_DEVICE_OPS is not set */ +#define RT_USING_INTERRUPT_INFO +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +/* RT_USING_MODULE is not set */ +#define ARCH_ARM +#define ARCH_ARM_CORTEX_A +#define ARCH_ARM_CORTEX_A9 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +/* RT_USING_USER_MAIN is not set */ + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +/* FINSH_USING_MSH_ONLY is not set */ +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 4 +/* RT_USING_DFS_MNTTABLE is not set */ +/* RT_USING_DFS_ELMFAT is not set */ +#define RT_USING_DFS_DEVFS +/* RT_USING_DFS_ROMFS is not set */ +/* RT_USING_DFS_RAMFS is not set */ +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ +/* RT_USING_DFS_NFS is not set */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +/* RT_USING_I2C is not set */ +#define RT_USING_PIN +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_WIFI is not set */ +/* RT_USING_AUDIO is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_PTHREADS +#define RT_USING_POSIX +/* RT_USING_POSIX_MMAP is not set */ +/* RT_USING_POSIX_TERMIOS is not set */ +/* RT_USING_POSIX_AIO is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +#define RT_USING_VBUS +/* RT_USING_VBUS_RFS is not set */ +/* RT_USING_VBUS_RSHELL is not set */ +#define RT_VBUS_USING_TESTS +#define _RT_VBUS_RING_BASE 0x6f800000 +#define _RT_VBUS_RING_SZ 2097152 +#define RT_VBUS_GUEST_VIRQ 14 +#define RT_VBUS_HOST_VIRQ 15 +#define RT_VBUS_SHELL_DEV_NAME "vbser0" +#define RT_VBUS_RFS_DEV_NAME "rfs" + +/* Utilities */ + +#define RT_USING_LOGTRACE +#define LOG_TRACE_MAX_SESSION 16 +/* LOG_TRACE_USING_LEVEL_NOTRACE is not set */ +/* LOG_TRACE_USING_LEVEL_ERROR is not set */ +/* LOG_TRACE_USING_LEVEL_WARNING is not set */ +#define LOG_TRACE_USING_LEVEL_INFO +/* LOG_TRACE_USING_LEVEL_VERBOSE is not set */ +/* LOG_TRACE_USING_LEVEL_DEBUG is not set */ +/* LOG_TRACE_USING_MEMLOG is not set */ +/* RT_USING_RYM is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_PERSIMMON is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_STM32F4_HAL is not set */ +/* PKG_USING_STM32F4_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_AHT10 is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ + +/* sample package */ + +/* PKG_USING_SAMPLES is not set */ + +/* example package: hello */ + +/* PKG_USING_HELLO is not set */ +#define SOC_VEXPRESS_GEMINI +/* RT_USING_UART0 is not set */ +#define RT_USING_UART1 + +#endif diff --git a/bsp/qemu-vexpress-gemini/rtconfig.py b/bsp/qemu-vexpress-gemini/rtconfig.py new file mode 100644 index 0000000000..462b218a20 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/rtconfig.py @@ -0,0 +1,55 @@ +import os + +# toolchains options +ARCH='arm' +CPU='vexpress-a9' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + # EXEC_PATH = r'/opt/arm-2012.09/bin' + EXEC_PATH = r'C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin' + EXEC_PATH = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LINK_SCRIPT = 'vexpress.lds' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=vexpress.map,-cref,-u,system_vectors'+\ + ' -T %s' % LINK_SCRIPT + + CPATH = '' + LPATH = '' + + # generate debug info in all cases + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -g -gdwarf-2' + + if BUILD == 'debug': + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' diff --git a/bsp/qemu-vexpress-gemini/vexpress.lds b/bsp/qemu-vexpress-gemini/vexpress.lds new file mode 100644 index 0000000000..96863d3f89 --- /dev/null +++ b/bsp/qemu-vexpress-gemini/vexpress.lds @@ -0,0 +1,91 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + . = 0x6FC00000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + __data_start = .; + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(4); + __bss_start = __data_end; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/raspi2/.config b/bsp/raspi2/.config new file mode 100644 index 0000000000..b9827ac3ed --- /dev/null +++ b/bsp/raspi2/.config @@ -0,0 +1,290 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_USING_MODULE is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_BCM2836_SOC=y +CONFIG_RT_USING_UART1=y diff --git a/bsp/raspi2/Kconfig b/bsp/raspi2/Kconfig new file mode 100644 index 0000000000..d2a2d11399 --- /dev/null +++ b/bsp/raspi2/Kconfig @@ -0,0 +1,26 @@ +mainmenu "RT-Thread Project Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BCM2836_SOC + bool + select ARCH_ARM_CORTEX_A7 + default y + +source "driver/Kconfig" diff --git a/bsp/raspi2/README.md b/bsp/raspi2/README.md new file mode 100644 index 0000000000..d65a954728 --- /dev/null +++ b/bsp/raspi2/README.md @@ -0,0 +1,106 @@ +# Raspberry PI 2B板级支持包说明 + +## 1. 简介 + +树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派2采用4核Broadcom BCM2836 (ARMv7-A)芯片、双核VideoCore IV GPU和1GB内存。 + +这份RT-Thread BSP是针对 Raspberry Pi 2B 的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。 + +![raspi2](figures/raspi2.png) + +当前Raspberry Pi 2B对应的硬件特性： + +| 硬件 | 描述 | +|------- | ------------------------------- | +| CPU | ARM Cortex-A7（4核心） | +| 主频 | 900M | +| Memory | 1GB (0x0000000 - 0x40000000) | +| | 其中0x3f000000 - 0x40000000为peripheral | + +## 2. 编译说明 + +Windows环境下推荐使用[env工具][1]进行编译。 + +Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。 + +``` +tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2 +``` + +Linux环境下需要修改编译器目录设置，修改`bsp/raspi2/rtconfig.py`中的 + +``` +EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin' +``` + +为编译工具的实际所在目录，这里注意要加上后缀 `/bin` + +进入到`rt-thread/bsp/raspi2`目录中，运行以下命令： + +``` +scons +``` + +来编译这个板级支持包。如果编译正确无误，会产生kernel.elf、kernel.img文件。 +kernel.img即是要cp到raspberry SD卡中根目录的文件 + +## 3. 执行 + +### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡 + +Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具 + +解开下载的镜像文件, linux下使用如下的命令 + +``` +unzip 2018-06-27-raspbian-stretch-lite.zip +``` + +准备一张空SD卡，linux环境下，插入电脑并执行 + +``` +sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync +``` + +**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。** + +Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。 + +最后把kernel7.img放入SD boot分区，覆盖原来的文件。 + +### 3.2 准备好串口线 + +目前版本是使用raspi2的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示： + +![raspi2](figures/raspi_uart.png) + +串口参数： 115200 8N1 ，硬件和软件流控为关。 + +按上面的方法做好SD卡后，插入树莓派2B，通电可以在串口上看到如下所示的输出信息： + +```text + heap: 0x00020b20 - 0x00400000 + + \ | / +- RT - Thread Operating System + / | \ 3.1.0 build Aug 23 2018 + 2006 - 2018 Copyright by rt-thread team +Hello RT-Thread! +msh > +``` + +## 4. 支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0| + +## 5. 联系人信息 + +维护人：[bernard][5] + + [1]: https://www.rt-thread.org/page/download.html + [2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2 + [3]: https://downloads.raspberrypi.org/raspbian_lite_latest + [4]: https://etcher.io + [5]: https://github.com/BernardXiong diff --git a/bsp/raspi2/SConscript b/bsp/raspi2/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/raspi2/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/raspi2/SConstruct b/bsp/raspi2/SConstruct new file mode 100644 index 0000000000..1326632477 --- /dev/null +++ b/bsp/raspi2/SConstruct @@ -0,0 +1,27 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/raspi2/applications/SConscript b/bsp/raspi2/applications/SConscript new file mode 100644 index 0000000000..533df8ac31 --- /dev/null +++ b/bsp/raspi2/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/lwp/lwp_mem.h b/bsp/raspi2/applications/main.c similarity index 68% rename from components/lwp/lwp_mem.h rename to bsp/raspi2/applications/main.c index 117a18f677..101386fdfd 100644 --- a/components/lwp/lwp_mem.h +++ b/bsp/raspi2/applications/main.c @@ -1,7 +1,7 @@ /* - * File : lwp_mem.h + * File : main.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * COPYRIGHT (C) 2017, RT-Thread Development Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,16 +19,18 @@ * * Change Logs: * Date Author Notes + * 2017-5-30 Bernard the first version */ +#include +#include +#include -#ifndef __LWP_MEM_H__ -#define __LWP_MEM_H__ +#include -extern void rt_lwp_mem_init(struct rt_lwp *lwp); -extern void rt_lwp_mem_deinit(struct rt_lwp *lwp); +int main(int argc, char** argv) +{ + rt_kprintf("Hello RT-Thread!\n"); -extern void *rt_lwp_mem_malloc(rt_uint32_t size); -extern void rt_lwp_mem_free(void *addr); -extern void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize); + return 0; +} -#endif diff --git a/components/drivers/wlan/wlan_cmd.h b/bsp/raspi2/applications/mnt.c similarity index 52% rename from components/drivers/wlan/wlan_cmd.h rename to bsp/raspi2/applications/mnt.c index a981601f5e..8da1dc1ece 100644 --- a/components/drivers/wlan/wlan_cmd.h +++ b/bsp/raspi2/applications/mnt.c @@ -1,8 +1,7 @@ /* - * File : wlan_cmd.h - * Wi-Fi common commands + * File : mnt.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * COPYRIGHT (C) 2017, RT-Thread Development Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,31 +19,11 @@ * * Change Logs: * Date Author Notes - * 2018-06-05 RT-Thread first version */ -#ifndef WLAN_CMD_H__ -#define WLAN_CMD_H__ +#include -struct netif; - -int wifi_get_mode(void); -int wifi_set_mode(int mode); - -/* do the wifi default action: read wifi setting and then join or start soft-AP */ -int wifi_default(void); -/* setup netif for soft-ap */ -int wifi_softap_setup_netif(struct netif *netif); - -int wifi_set_setting(const char *ssid, const char *pwd); - -#ifdef PKG_USING_CJSON -int wifi_read_cfg(const char *filename); -int wifi_save_cfg(const char *filename); -#endif -/* save wifi setting with default storage file */ -int wifi_save_setting(void); - -extern struct rt_wlan_info info; - -#endif +int mnt_init(void) +{ + return 0; +} diff --git a/bsp/raspi2/cpu/SConscript b/bsp/raspi2/cpu/SConscript new file mode 100644 index 0000000000..eb4ee7a585 --- /dev/null +++ b/bsp/raspi2/cpu/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspi2/cpu/armv7.h b/bsp/raspi2/cpu/armv7.h new file mode 100644 index 0000000000..a07d9de2a9 --- /dev/null +++ b/bsp/raspi2/cpu/armv7.h @@ -0,0 +1,64 @@ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/bsp/raspi2/cpu/context_gcc.S b/bsp/raspi2/cpu/context_gcc.S new file mode 100644 index 0000000000..48402739f9 --- /dev/null +++ b/bsp/raspi2/cpu/context_gcc.S @@ -0,0 +1,105 @@ +/* + * File : context.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .text, "ax" +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid i + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr_c, r0 + bx lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + +.section .bss.share.isr +_guest_switch_lvl: + .word 0 + +.globl vmm_virq_update + +.section .text.isr, "ax" +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + orrne r4, r4, #0x20 @ it's thumb code + + stmfd sp!, {r4} @ push cpsr + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task cpsr to spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r0, [ip] + str r3, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr diff --git a/bsp/raspi2/cpu/cp15.h b/bsp/raspi2/cpu/cp15.h new file mode 100644 index 0000000000..ebea3f0fe3 --- /dev/null +++ b/bsp/raspi2/cpu/cp15.h @@ -0,0 +1,12 @@ +#ifndef __CP15_H__ +#define __CP15_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/bsp/raspi2/cpu/cp15_gcc.S b/bsp/raspi2/cpu/cp15_gcc.S new file mode 100644 index 0000000000..f1ed6492aa --- /dev/null +++ b/bsp/raspi2/cpu/cp15_gcc.S @@ -0,0 +1,140 @@ +/* + * File : cp15_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * http://www.rt-thread.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7ff + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_cpu_mmu_disable +rt_cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl rt_cpu_mmu_enable +rt_cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl rt_cpu_tlb_set +rt_cpu_tlb_set: + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr diff --git a/bsp/raspi2/cpu/cpu.c b/bsp/raspi2/cpu/cpu.c new file mode 100644 index 0000000000..8bf16d19e8 --- /dev/null +++ b/bsp/raspi2/cpu/cpu.c @@ -0,0 +1,37 @@ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/bsp/raspi2/cpu/interrupt.c b/bsp/raspi2/cpu/interrupt.c new file mode 100644 index 0000000000..b9f0a00dd7 --- /dev/null +++ b/bsp/raspi2/cpu/interrupt.c @@ -0,0 +1,136 @@ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2018/5/3 Bernard first version + */ + +#include +#include + +#include "cp15.h" +#include + +#define MAX_HANDLERS 64 + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +extern int system_vectors; + +static void default_isr_handler(int vector, void *param) +{ + rt_kprintf("unhandled irq: %d\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + uint32_t index; + + /* mask all of interrupts */ + IRQ_DISABLE_BASIC = 0x000000ff; + IRQ_DISABLE1 = 0xffffffff; + IRQ_DISABLE2 = 0xffffffff; + + for (index = 0; index < MAX_HANDLERS; index ++) + { + isr_table[index].handler = default_isr_handler; + isr_table[index].param = NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); + isr_table[index].counter = 0; +#endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + if (vector < 8) + { + IRQ_DISABLE_BASIC = (1 << vector); + } + else if (vector < 32) + { + IRQ_DISABLE1 = (1 << vector); + } + else + { + vector = vector % 32; + IRQ_DISABLE2 = (1 << vector); + } +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector < 8) + { + IRQ_ENABLE_BASIC = (1 << vector); + } + else if (vector < 32) + { + IRQ_ENABLE1 = (1 << vector); + } + else + { + vector = vector % 32; + IRQ_ENABLE2 = (1 << vector); + } +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} diff --git a/bsp/raspi2/cpu/mmu.c b/bsp/raspi2/cpu/mmu.c new file mode 100644 index 0000000000..b2503e4260 --- /dev/null +++ b/bsp/raspi2/cpu/mmu.c @@ -0,0 +1,207 @@ +/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + */ + +#include +#include +#include + +#include "cp15.h" + +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO +#define XN (1<<4) // eXecute Never + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* Read/Write, cache, write back */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +/* Read/Write, cache, write through */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +/* Read/Write without cache and write buffer */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +/* Read/Write without cache and write buffer, no execute */ +#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) +/* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_mmu_init(void) +{ + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /* set page table */ + /* 4G 1:1 memory */ + rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB); + /* IO memory region */ + rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/bsp/raspi2/cpu/stack.c b/bsp/raspi2/cpu/stack.c new file mode 100644 index 0000000000..e60e8c7170 --- /dev/null +++ b/bsp/raspi2/cpu/stack.c @@ -0,0 +1,68 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/bsp/raspi2/cpu/start_gcc.S b/bsp/raspi2/cpu/start_gcc.S new file mode 100644 index 0000000000..e64563c91e --- /dev/null +++ b/bsp/raspi2/cpu/start_gcc.S @@ -0,0 +1,279 @@ +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013-2014, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000100 +.equ ABT_Stack_Size, 0x00000000 +.equ RT_FIQ_STACK_PGSZ, 0x00000000 +.equ RT_IRQ_STACK_PGSZ, 0x00000100 +.equ USR_Stack_Size, 0x00000100 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) + +.section .data.share.isr +/* stack */ +.globl stack_start +.globl stack_top + +stack_start: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top: + +.text +/* reset entry */ +.globl _reset +_reset: + /* Disable IRQ & FIQ */ + cpsid if + + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +overHyped: /* Get out of HYP mode */ + ldr r1, =continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret + +continue: + + /* disable smp */ + bl arm_smp_disable + + /* disable mmu */ + bl rt_cpu_mmu_disable + /* set the cpu to SVC32 mode and disable interrupt */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0x13 + msr cpsr_c, r0 + + /* setup stack */ + bl stack_setup + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup +_rtthread_startup: + .word rtthread_startup + +stack_setup: + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + sub r0, r0, #SVC_Stack_Size + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_FIQ_STACK_PGSZ + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_IRQ_STACK_PGSZ + + /* come back to SVC mode */ + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + bx lr + +.text +;@ void arm_smp_enable(void); +.globl arm_smp_enable +arm_smp_enable: + mrc p15, 0, r0, c1, c0, 1 ;@ set SMP bit in ACTLR + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + bx lr + +.text +;@ void arm_smp_disable(void); +.globl arm_smp_disable +arm_smp_disable: + mrc p15, 0, r0, c1, c0, 1 ;@ clear SMP bit in ACTLR + bic r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + bx lr + +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ +.section .text.isr, "ax" + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc, lr, #4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + +.globl rt_current_thread +.globl vmm_thread +.globl vmm_virq_check + + .align 5 +.globl vector_irq +vector_irq: + stmfd sp!, {r0-r12,lr} + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. If the usr mode guest is + @ interrupted, this will just switch to the stack of kernel space. + @ save the registers in kernel space won't trigger data abort. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] @ get new task's stack pointer + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 + .globl vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + bl rt_hw_trap_undef + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/bsp/raspi2/cpu/trap.c b/bsp/raspi2/cpu/trap.c new file mode 100644 index 0000000000..3012c26e2c --- /dev/null +++ b/bsp/raspi2/cpu/trap.c @@ -0,0 +1,183 @@ +/* + * File : trap.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include + +#include "armv7.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +void rt_hw_trap_irq(void) +{ + void *param; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + uint32_t value = 0; + + // rt_kprintf("pend basic: 0x%08x\n", IRQ_PEND_BASIC); + // rt_kprintf(" pend1: 0x%08x\n", IRQ_PEND1); + // rt_kprintf(" pend2: 0x%08x\n", IRQ_PEND2); + + value = IRQ_PEND_BASIC & 0x3ff; + if (value) + { + uint32_t irq; + + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) - 1; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +} + +void rt_hw_trap_fiq(void) +{ + /* TODO */ +} diff --git a/bsp/raspi2/cpu/vector_gcc.S b/bsp/raspi2/cpu/vector_gcc.S new file mode 100644 index 0000000000..17c2d69c30 --- /dev/null +++ b/bsp/raspi2/cpu/vector_gcc.S @@ -0,0 +1,65 @@ +/* + * File : vector_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2013, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef diff --git a/bsp/raspi2/driver/Kconfig b/bsp/raspi2/driver/Kconfig new file mode 100644 index 0000000000..95c536178d --- /dev/null +++ b/bsp/raspi2/driver/Kconfig @@ -0,0 +1,3 @@ +config RT_USING_UART1 + bool "Enable UART1" + default y diff --git a/bsp/raspi2/driver/SConscript b/bsp/raspi2/driver/SConscript new file mode 100644 index 0000000000..25e7ef2e55 --- /dev/null +++ b/bsp/raspi2/driver/SConscript @@ -0,0 +1,17 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Split(''' +board.c +drv_uart.c +''') +CPPPATH = [cwd] + +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspi2/driver/bcm283x.h b/bsp/raspi2/driver/bcm283x.h new file mode 100644 index 0000000000..85422e2a22 --- /dev/null +++ b/bsp/raspi2/driver/bcm283x.h @@ -0,0 +1,125 @@ +#ifndef BCM283X_H__ +#define BCM283X_H__ + +#include + +#define PER_BASE (0x3F000000) +#define PER_BASE_40000000 (0x40000000) + +/* + * GPIO + */ +#define GPIO_BASE (PER_BASE + 0x200000) +#define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x00) /* GPIO Function Select 0 32bit R/W */ +#define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x04) /* GPIO Function Select 1 32bit R/W */ +#define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x08) /* GPIO Function Select 2 32bit R/W */ +#define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x10) /* GPIO Function Select 4 32bit R/W */ +#define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x1C) +#define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x28) +#define GPIO_GPPUD HWREG32(GPIO_BASE + 0x94) /* GPIO Pin Pull-up/down Enable */ +#define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x98) /* GPIO Pin Pull-up/down Enable Clock 0 */ +#define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x9C) /* GPIO Pin Pull-up/down Enable Clock 1 */ + +/* + * Interrupt Controler + */ +#define IRQ_BASE (PER_BASE + 0xB200) +#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00) +#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04) +#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08) +#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C) +#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10) +#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14) +#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18) +#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C) +#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20) +#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24) + +/* + * System Timer + */ +#define STIMER_BASE (PER_BASE + 0x3000) +#define STIMER_CS HWREG32(STIMER_BASE + 0x00) +#define STIMER_CLO HWREG32(STIMER_BASE + 0x04) +#define STIMER_CHI HWREG32(STIMER_BASE + 0x08) +#define STIMER_C0 HWREG32(STIMER_BASE + 0x0C) +#define STIMER_C1 HWREG32(STIMER_BASE + 0x10) +#define STIMER_C2 HWREG32(STIMER_BASE + 0x14) +#define STIMER_C3 HWREG32(STIMER_BASE + 0x18) + +/* + * ARM Timer + */ +#define ARM_TIMER_BASE (PER_BASE + 0xB000) + +#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) +#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) +#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) +#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) +#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) +#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) +#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) +#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) +#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) + +/* + * Core Timer + */ +#define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */ +#define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */ +#define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C) /* Core timer access LS 32 bits */ +#define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20) /* Core timer access MS 32 bits */ + +/* + * ARM Core Timer + */ +#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */ +#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */ +#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */ +#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */ + +/* + * ARM Core Mailbox interrupt + */ +#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */ +#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */ +#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */ +#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */ + +/* + * ARM Core IRQ/FIQ status + */ +#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */ +#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */ +#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */ +#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */ +#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */ +#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */ +#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */ +#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */ + +#define IRQ_ARM_TIMER 0 +#define IRQ_ARM_MAILBOX 1 +#define IRQ_ARM_DB0 2 +#define IRQ_ARM_DB1 3 +#define IRQ_ARM_GPU0_HALT 4 +#define IRQ_ARM_GPU1_HALT 5 +#define IRQ_ARM_ILLEGAL_ACC1 6 +#define IRQ_ARM_ILLEGAL_ACC0 7 + +#define IRQ_AUX 29 +#define IRQ_IIC_SPI_SLV 43 +#define IRQ_PWA0 45 +#define IRQ_PWA1 46 +#define IRQ_SMI 48 +#define IRQ_GPIO0 49 +#define IRQ_GPIO1 50 +#define IRQ_GPIO2 51 +#define IRQ_GPIO3 52 +#define IRQ_IIC 53 +#define IRQ_SPI 54 +#define IRQ_PCM 55 +#define IRQ_UART 57 + +#endif + diff --git a/bsp/raspi2/driver/board.c b/bsp/raspi2/driver/board.c new file mode 100644 index 0000000000..30f8cd93a1 --- /dev/null +++ b/bsp/raspi2/driver/board.c @@ -0,0 +1,90 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" + +void rt_hw_timer_isr(int vector, void *parameter) +{ + ARM_TIMER_IRQCLR = 0; + + rt_tick_increase(); +} + +int rt_hw_timer_init(void) +{ + /* timer_clock = apb_clock/(pre_divider + 1) */ + ARM_TIMER_PREDIV = (250 - 1); + + ARM_TIMER_RELOAD = 0; + ARM_TIMER_LOAD = 0; + ARM_TIMER_IRQCLR = 0; + ARM_TIMER_CTRL = 0; + + ARM_TIMER_RELOAD = 10000; + ARM_TIMER_LOAD = 10000; + + /* 23-bit counter, enable interrupt, enable timer */ + ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7); + + rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_ARM_TIMER); + + return 0; +} + +void vector_copy(void) +{ + rt_memcpy((void*)0x0, (void*)0x8000, 64); +} + +void rt_hw_board_init(void) +{ + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + vector_copy(); + + /* initialize uart */ + rt_hw_uart_init(); + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + + /* initialize timer for os tick */ + // rt_hw_timer_init(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/amebaz/drivers/wlan/amebaz_wlan.h b/bsp/raspi2/driver/board.h similarity index 58% rename from bsp/amebaz/drivers/wlan/amebaz_wlan.h rename to bsp/raspi2/driver/board.h index e062797290..92ef5de76c 100644 --- a/bsp/amebaz/drivers/wlan/amebaz_wlan.h +++ b/bsp/raspi2/driver/board.h @@ -1,5 +1,5 @@ /* - * File : amebaz_wlan.h + * File : board.h * This file is part of RT-Thread RTOS * COPYRIGHT (C) 2017, RT-Thread Development Team * @@ -20,35 +20,23 @@ * Change Logs: * Date Author Notes * 2017-5-30 Bernard the first version - * 2018-6-12 flyingcys add amebaz wlan interface */ - -#ifndef __AMEBAZ_WLAN_H__ -#define __AMEBAZ_WLAN_H__ -int amebaz_wifi_scan(); +#ifndef BOARD_H__ +#define BOARD_H__ -void amebaz_wifi_info_init(void); +#include -int amebaz_wifi_set_sta_info(char *ssid, char *passwd); +#include +#include -int amebaz_wifi_set_ap_info(char *ssid, char *passwd); +extern unsigned char __bss_start; +extern unsigned char __bss_end; -int amebaz_wifi_connect(char *ssid, char *passwd); +#define RT_HW_HEAP_BEGIN (void*)&__bss_end +#define RT_HW_HEAP_END (void*)(0x0 + 4 * 1024 * 1024) -int amebaz_wifi_disconnect(void); +void rt_hw_board_init(void); -int amebaz_wifi_ap_start(char *ssid, char *passwd, int channel); - -int amebaz_wifi_ap_stop(void); - -int amebaz_wifi_get_rssi(void); - -void amebaz_wifi_set_channel(int channel); - -int amebaz_wifi_get_channel(void); - -int amebaz_wifi_init(rt_wlan_mode_t mode); - -#endif /* __AMEBAZ_WLAN_H__ */ +#endif diff --git a/bsp/raspi2/driver/drv_uart.c b/bsp/raspi2/driver/drv_uart.c new file mode 100644 index 0000000000..de7b987c2a --- /dev/null +++ b/bsp/raspi2/driver/drv_uart.c @@ -0,0 +1,199 @@ +/* + * File : drv_uart.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018/5/5 Bernard The first version + */ + +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include + +#define AUX_BASE (0x3F000000 + 0x215000) + +struct hw_uart_device +{ + rt_uint32_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if (uart->hw_base == AUX_BASE) + { + uint32_t value; + + /* GPIO function set */ + value = GPIO_GPFSEL1; + value &= ~(7<<12); /* GPIO14 */ + value |= 2<<12 ; /* ALT5 */ + value &= ~(7<<15); /* GPIO15 */ + value |= 2<<15 ; /* ALT5 */ + GPIO_GPFSEL1 = value; + + /* PullUD disable */ + GPIO_GPPUD = 0; + GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15); + GPIO_GPPUDCLK0 = 0; + + AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */ + AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */ + AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */ + AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */ + AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */ + AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */ + AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */ + AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */ + } + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + AUX_MU_IER_REG(uart->hw_base) = 0x0; + rt_hw_interrupt_mask(uart->irqno); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + AUX_MU_IER_REG(uart->hw_base) = 0x1; + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20)); + AUX_MU_IO_REG(uart->hw_base) = c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01)) + { + ch = AUX_MU_IO_REG(uart->hw_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device*)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + RPI_UART0_BASE, + IRQ_PBA8_UART0, +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + AUX_BASE, + IRQ_AUX, +}; +static struct rt_serial_device _serial1; +#endif + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART0 + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0"); +#endif + +#ifdef RT_USING_UART1 + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + /* enable Rx and Tx of UART */ + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1"); +#endif + + return 0; +} diff --git a/bsp/raspi2/driver/drv_uart.h b/bsp/raspi2/driver/drv_uart.h new file mode 100644 index 0000000000..e489eaae65 --- /dev/null +++ b/bsp/raspi2/driver/drv_uart.h @@ -0,0 +1,56 @@ +/* + * File : drv_uart.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +/* + * Auxiliary + */ +#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ +#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ +#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ +#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */ +#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */ +#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ +#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ +#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ +#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ +#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ +#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */ +#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */ +#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ +#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */ +#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */ +#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ +#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ +#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */ +#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */ +#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */ + +int rt_hw_uart_init(void); + +#endif /* DRV_UART_H__ */ + diff --git a/bsp/raspi2/figures/raspi2.png b/bsp/raspi2/figures/raspi2.png new file mode 100644 index 0000000000..2f2e25d9cb Binary files /dev/null and b/bsp/raspi2/figures/raspi2.png differ diff --git a/bsp/raspi2/figures/raspi_uart.png b/bsp/raspi2/figures/raspi_uart.png new file mode 100644 index 0000000000..c6ae382182 Binary files /dev/null and b/bsp/raspi2/figures/raspi_uart.png differ diff --git a/bsp/raspi2/link.lds b/bsp/raspi2/link.lds new file mode 100644 index 0000000000..75e0845943 --- /dev/null +++ b/bsp/raspi2/link.lds @@ -0,0 +1,149 @@ +/* + * File : link.lds + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * 2017-5-30 bernard first version + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +SECTIONS +{ + . = 0x00008000; + . = ALIGN(4); + .text : + { + *(.vectors) + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(4); + .bss : + { + PROVIDE(__bss_start = .); + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + PROVIDE(__bss_end = .); + } + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/raspi2/rtconfig.h b/bsp/raspi2/rtconfig.h new file mode 100644 index 0000000000..073c18bed2 --- /dev/null +++ b/bsp/raspi2/rtconfig.h @@ -0,0 +1,257 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMTRACE is not set */ +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +/* RT_USING_DEVICE_OPS is not set */ +/* RT_USING_INTERRUPT_INFO is not set */ +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +/* RT_USING_MODULE is not set */ +#define ARCH_ARM +#define ARCH_ARM_CORTEX_A +#define ARCH_ARM_CORTEX_A7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +/* RT_USING_DFS is not set */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +/* RT_USING_I2C is not set */ +/* RT_USING_PIN is not set */ +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_WIFI is not set */ +/* RT_USING_AUDIO is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +/* RT_USING_LIBC is not set */ +/* RT_USING_PTHREADS is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_LOGTRACE is not set */ +/* RT_USING_RYM is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_PERSIMMON is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_STM32F4_HAL is not set */ +/* PKG_USING_STM32F4_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_AHT10 is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ + +/* sample package */ + +/* PKG_USING_SAMPLES is not set */ + +/* example package: hello */ + +/* PKG_USING_HELLO is not set */ +#define BCM2836_SOC +#define RT_USING_UART1 + +#endif diff --git a/bsp/raspi2/rtconfig.py b/bsp/raspi2/rtconfig.py new file mode 100644 index 0000000000..37475595a2 --- /dev/null +++ b/bsp/raspi2/rtconfig.py @@ -0,0 +1,53 @@ +import os + +# toolchains options +ARCH ='arm' +CPU ='cortex-a7' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = r'../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +PLATFORM = 'gcc' +EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mfpu=neon-vfpv4 -mfloat-abi=softfp -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n' diff --git a/bsp/rx/project.vpj b/bsp/rx/project.vpj index 9e8b56055f..741e2059d6 100644 --- a/bsp/rx/project.vpj +++ b/bsp/rx/project.vpj @@ -303,8 +303,6 @@ - - diff --git a/bsp/samd21/rtconfig.py b/bsp/samd21/rtconfig.py index af3ca84f5d..2f2460e77b 100644 --- a/bsp/samd21/rtconfig.py +++ b/bsp/samd21/rtconfig.py @@ -44,7 +44,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m0+ -mthumb -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m0plus -mthumb -ffunction-sections -fdata-sections' CFLAGS = DEVICE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-MKL15Z128.map,-cref,-u,Reset_Handler -T MKL15Z128_FLASH.ld' diff --git a/bsp/stm32f0x/applications/application.c b/bsp/stm32f0x/applications/application.c index c0fb3b4b2f..0eedb8022c 100644 --- a/bsp/stm32f0x/applications/application.c +++ b/bsp/stm32f0x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f0x/applications/startup.c b/bsp/stm32f0x/applications/startup.c index 4d9bfaa689..61ff677cc3 100644 --- a/bsp/stm32f0x/applications/startup.c +++ b/bsp/stm32f0x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,7 +22,7 @@ extern int rt_application_init(void); -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f0x/drivers/board.c b/bsp/stm32f0x/drivers/board.c index 5e9fc2add5..e8833b43ee 100644 --- a/bsp/stm32f0x/drivers/board.c +++ b/bsp/stm32f0x/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f0x/drivers/board.h b/bsp/stm32f0x/drivers/board.h index ea4e537f3a..50325790e4 100644 --- a/bsp/stm32f0x/drivers/board.h +++ b/bsp/stm32f0x/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f0x/drivers/led.c b/bsp/stm32f0x/drivers/led.c index 2a17a55adb..b038b5b253 100644 --- a/bsp/stm32f0x/drivers/led.c +++ b/bsp/stm32f0x/drivers/led.c @@ -1,11 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f0x/drivers/led.h b/bsp/stm32f0x/drivers/led.h index af513637a2..0d303ae18c 100644 --- a/bsp/stm32f0x/drivers/led.h +++ b/bsp/stm32f0x/drivers/led.h @@ -1,11 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f0x/drivers/usart.c b/bsp/stm32f0x/drivers/usart.c index 1f6fbab7a2..0c4aa15821 100644 --- a/bsp/stm32f0x/drivers/usart.c +++ b/bsp/stm32f0x/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f0x/drivers/usart.h b/bsp/stm32f0x/drivers/usart.h index 6d733a2d61..aed5b1448f 100644 --- a/bsp/stm32f0x/drivers/usart.h +++ b/bsp/stm32f0x/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/applications/application.c b/bsp/stm32f107/applications/application.c index 6312734000..f220cb4917 100644 --- a/bsp/stm32f107/applications/application.c +++ b/bsp/stm32f107/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/applications/startup.c b/bsp/stm32f107/applications/startup.c index 9041d59002..d64943c32b 100644 --- a/bsp/stm32f107/applications/startup.c +++ b/bsp/stm32f107/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,7 +21,7 @@ extern int rt_application_init(void); -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f107/drivers/board.c b/bsp/stm32f107/drivers/board.c index 9f70058c37..9013e5d07c 100644 --- a/bsp/stm32f107/drivers/board.c +++ b/bsp/stm32f107/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/drivers/board.h b/bsp/stm32f107/drivers/board.h index 7d067fcc5d..9b5dff53e3 100644 --- a/bsp/stm32f107/drivers/board.h +++ b/bsp/stm32f107/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/drivers/gpio.c b/bsp/stm32f107/drivers/gpio.c index e0778f35d5..b92685ebdf 100644 --- a/bsp/stm32f107/drivers/gpio.c +++ b/bsp/stm32f107/drivers/gpio.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/drivers/gpio.h b/bsp/stm32f107/drivers/gpio.h index 03b744b333..5e75adf443 100644 --- a/bsp/stm32f107/drivers/gpio.h +++ b/bsp/stm32f107/drivers/gpio.h @@ -1,11 +1,7 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/drivers/stm32f1_rtc.c b/bsp/stm32f107/drivers/stm32f1_rtc.c index 68fab1ce00..62a4afcafe 100644 --- a/bsp/stm32f107/drivers/stm32f1_rtc.c +++ b/bsp/stm32f107/drivers/stm32f1_rtc.c @@ -1,11 +1,7 @@ /* - * File : stm32f1_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/drivers/stm32f1_rtc.h b/bsp/stm32f107/drivers/stm32f1_rtc.h index 02f463fce5..3bd050a178 100644 --- a/bsp/stm32f107/drivers/stm32f1_rtc.h +++ b/bsp/stm32f107/drivers/stm32f1_rtc.h @@ -1,11 +1,7 @@ /* - * File : stm32f1_rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f107/drivers/usart.c b/bsp/stm32f107/drivers/usart.c index c82fba3ee3..2ce119670f 100644 --- a/bsp/stm32f107/drivers/usart.c +++ b/bsp/stm32f107/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -398,8 +394,8 @@ void rt_hw_usart_init(void) uart = &uart3; config.baud_rate = BAUD_RATE_115200; - serial2.ops = &stm32_uart_ops; - serial2.config = config; + serial3.ops = &stm32_uart_ops; + serial3.config = config; NVIC_Configuration(&uart3); diff --git a/bsp/stm32f107/drivers/usart.h b/bsp/stm32f107/drivers/usart.h index 438578d86b..2127f3d533 100644 --- a/bsp/stm32f107/drivers/usart.h +++ b/bsp/stm32f107/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/Kconfig b/bsp/stm32f10x-HAL/Kconfig index 534e930ba8..2b3ffc04af 100644 --- a/bsp/stm32f10x-HAL/Kconfig +++ b/bsp/stm32f10x-HAL/Kconfig @@ -182,6 +182,22 @@ if RT_USING_SPI default n endif + +menuconfig BSP_USING_WDT + bool "Using wdt" + select RT_USING_WDT + default n +if BSP_USING_WDT + config BSP_USING_WDT_IWDG + bool "Enable iwdg" + default n +endif + +menuconfig BSP_USING_RTC + bool "Using rtc" + select RT_USING_RTC + default n + if RT_USING_DEVICE_IPC && (STM32F103RC || STM32F103RD || STM32F103RE || STM32F103RF || STM32F103RG ||STM32F103VC || STM32F103VD || STM32F103VE || STM32F103VF || STM32F103VG ||STM32F103ZC || STM32F103ZD || STM32F103ZE || STM32F103ZF || STM32F103ZG) config RT_USING_SDCARD bool "Using sdcard with sdio" @@ -195,3 +211,122 @@ if RT_USING_DEVICE_IPC && (STM32F103RC || STM32F103RD || STM32F103RE || STM32F10 default n depends on RT_USING_SDCARD endif + + + +menuconfig BSP_USING_PWM1 + bool "Using PWM1" + select RT_USING_PWM + default n + +if BSP_USING_PWM1 + config BSP_USING_PWM1_CH1 + bool "Enable Channel 1 (PE9)" + default n + config BSP_USING_PWM1_CH2 + bool "Enable Channel 2 (PE11)" + default n +endif + +menuconfig BSP_USING_PWM2 + bool "Using PWM2" + select RT_USING_PWM + default n + +if BSP_USING_PWM2 + config BSP_USING_PWM2_CH1 + bool "Enable Channel 1 (PB10)" + default n + config BSP_USING_PWM2_CH2 + bool "Enable Channel 2 (PB11)" + default n + config BSP_USING_PWM2_CH3 + bool "Enable Channel 3 (PA15)" + default n + config BSP_USING_PWM2_CH4 + bool "Enable Channel 4 (PB3)" + default n +endif + +menuconfig BSP_USING_PWM3 + bool "Using PWM3" + select RT_USING_PWM + default n + +if BSP_USING_PWM3 + config BSP_USING_PWM3_CH1 + bool "Enable Channel 1 (PA6)" + default n + config BSP_USING_PWM3_CH2 + bool "Enable Channel 2 (PA7)" + default n + config BSP_USING_PWM3_CH3 + bool "Enable Channel 3 (PB0)" + default n + config BSP_USING_PWM3_CH4 + bool "Enable Channel 4 (PB1)" + default n +endif + +menuconfig BSP_USING_PWM4 + bool "Using PWM4" + select RT_USING_PWM + default n + +if BSP_USING_PWM4 + config BSP_USING_PWM4_CH1 + bool "Enable Channel 1 (PD12)" + default n + config BSP_USING_PWM4_CH2 + bool "Enable Channel 2 (PD13)" + default n + config BSP_USING_PWM4_CH3 + bool "Enable Channel 3 (PD14)" + default n + config BSP_USING_PWM4_CH4 + bool "Enable Channel 4 (PD15)" + default n +endif + +menuconfig BSP_USING_PWM5 + bool "Using PWM5" + select RT_USING_PWM + default n + +if BSP_USING_PWM5 + config BSP_USING_PWM5_CH1 + bool "Enable Channel 1 (PA0)" + default n + config BSP_USING_PWM5_CH2 + bool "Enable Channel 2 (PA1)" + default n + config BSP_USING_PWM5_CH3 + bool "Enable Channel 3 (PA2)" + default n + config BSP_USING_PWM5_CH4 + bool "Enable Channel 4 (PA3)" + default n +endif + +menuconfig BSP_USING_PWM8 + bool "Using PWM8" + select RT_USING_PWM + default n + +if BSP_USING_PWM8 + config BSP_USING_PWM8_CH1 + bool "Enable Channel 1 (PC6)" + default n + config BSP_USING_PWM8_CH2 + bool "Enable Channel 2 (PC7)" + default n + config BSP_USING_PWM8_CH3 + bool "Enable Channel 3 (PC8)" + default n + config BSP_USING_PWM8_CH4 + bool "Enable Channel 4 (PC9)" + default n +endif + + + diff --git a/bsp/stm32f10x-HAL/applications/main.c b/bsp/stm32f10x-HAL/applications/main.c index 0f5e6000a8..77536078ae 100644 --- a/bsp/stm32f10x-HAL/applications/main.c +++ b/bsp/stm32f10x-HAL/applications/main.c @@ -1,11 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/SConscript b/bsp/stm32f10x-HAL/drivers/SConscript index 3568c9a89b..5d66355fe2 100644 --- a/bsp/stm32f10x-HAL/drivers/SConscript +++ b/bsp/stm32f10x-HAL/drivers/SConscript @@ -20,6 +20,17 @@ if GetDepend(['RT_USING_USB_DEVICE']): src += ['drv_usb.c'] if GetDepend(['RT_USING_SDCARD']): src += ['drv_sdcard.c'] +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + src += ['drv_i2c.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drv_iwg.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['drv_rtc.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] if rtconfig.CROSS_TOOL == 'gcc': src += ['gcc_startup.s'] diff --git a/bsp/stm32f10x-HAL/drivers/board.c b/bsp/stm32f10x-HAL/drivers/board.c index 0c880d4746..5c7e44c4f8 100644 --- a/bsp/stm32f10x-HAL/drivers/board.c +++ b/bsp/stm32f10x-HAL/drivers/board.c @@ -1,11 +1,8 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes @@ -47,6 +44,7 @@ void HAL_MspInit(void) __HAL_AFIO_REMAP_SWJ_NOJTAG(); } + void SystemClock_Config(void) { rt_err_t ret = RT_EOK; @@ -63,7 +61,19 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); - RT_ASSERT(ret == HAL_OK); + if(ret == HAL_TIMEOUT) + { + /* HSE timeout switch to HSI */ + rt_memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct)); + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; + ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); + RT_ASSERT(ret == HAL_OK); + } /* Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | @@ -103,6 +113,39 @@ void SystemClock_Config(void) #endif } +static void m3_m4_delay_us(rt_uint32_t us) +{ + __IO uint32_t Delay = us * (SystemCoreClock / 8U / 1000000U); + do + { + __NOP(); + } + while (Delay --); +} + +void HAL_Delay(__IO uint32_t Delay) +{ + m3_m4_delay_us(Delay * 10); +} + +extern __IO uint32_t uwTick; +uint32_t HAL_GetTick(void) +{ + HAL_Delay(1); + uwTick ++; + return uwTick; +} + +void HAL_SuspendTick(void) +{ + /* we should not suspend tick */ +} + +void HAL_ResumeTick(void) +{ + /* we should not resume tick */ +} + /** * This is the timer interrupt service routine. * @@ -111,6 +154,7 @@ void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); + HAL_IncTick(); rt_tick_increase(); /* leave interrupt */ diff --git a/bsp/stm32f10x-HAL/drivers/board.h b/bsp/stm32f10x-HAL/drivers/board.h index 731dc67a41..2268753677 100644 --- a/bsp/stm32f10x-HAL/drivers/board.h +++ b/bsp/stm32f10x-HAL/drivers/board.h @@ -1,11 +1,8 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_gpio.c b/bsp/stm32f10x-HAL/drivers/drv_gpio.c index 5c780435c7..7fd20db49a 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_gpio.c +++ b/bsp/stm32f10x-HAL/drivers/drv_gpio.c @@ -1,11 +1,8 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_gpio.h b/bsp/stm32f10x-HAL/drivers/drv_gpio.h index 4d7101da1a..49a6149ff4 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_gpio.h +++ b/bsp/stm32f10x-HAL/drivers/drv_gpio.h @@ -1,11 +1,8 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_i2c.c b/bsp/stm32f10x-HAL/drivers/drv_i2c.c new file mode 100644 index 0000000000..3109e95bd3 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_i2c.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-06-05 tanek first implementation. + * 2018-03-08 ZYH Porting for stm32f4xx + */ +#include +#include +#include +#include "drv_i2c.h" +#include +/*user can change this*/ +#define I2C_BUS_NAME "i2c2" +/*user should change this to adapt specific board*/ +#define I2C_SCL_PIN GPIO_PIN_6 +#define I2C_SCL_PORT GPIOB +#define I2C_SCL_PORT_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define I2C_SDA_PIN GPIO_PIN_7 +#define I2C_SDA_PORT GPIOB +#define I2C_SDA_PORT_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE + +static void drv_i2c_gpio_init() +{ + GPIO_InitTypeDef GPIO_Initure; + I2C_SCL_PORT_CLK_ENABLE(); + I2C_SDA_PORT_CLK_ENABLE(); + GPIO_Initure.Pin = I2C_SCL_PIN; + GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(I2C_SCL_PORT, &GPIO_Initure); + GPIO_Initure.Pin = I2C_SDA_PIN; + GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(I2C_SDA_PORT, &GPIO_Initure); + HAL_GPIO_WritePin(I2C_SCL_PORT, I2C_SCL_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(I2C_SDA_PORT, I2C_SDA_PIN, GPIO_PIN_SET); +} + +static void drv_set_sda(void *data, rt_int32_t state) +{ + HAL_GPIO_WritePin(I2C_SDA_PORT, I2C_SDA_PIN, state ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + +static void drv_set_scl(void *data, rt_int32_t state) +{ + HAL_GPIO_WritePin(I2C_SCL_PORT, I2C_SCL_PIN, state ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + +static rt_int32_t drv_get_sda(void *data) +{ + return HAL_GPIO_ReadPin(I2C_SDA_PORT, I2C_SDA_PIN) ? 1 : 0; +} + +static rt_int32_t drv_get_scl(void *data) +{ + return HAL_GPIO_ReadPin(I2C_SCL_PORT, I2C_SCL_PIN) ? 1 : 0; +} + +static void drv_udelay(rt_uint32_t us) +{ + __IO uint32_t Delay = us * (SystemCoreClock / 8U / 1000000U); + do + { + __NOP(); + } + while (Delay --); +} + +static const struct rt_i2c_bit_ops drv_bit_ops = +{ + RT_NULL, + drv_set_sda, + drv_set_scl, + drv_get_sda, + drv_get_scl, + drv_udelay, + 1, + 100 +}; + +int drv_i2c_init(void) +{ + static struct rt_i2c_bus_device i2c2_bus; + drv_i2c_gpio_init(); + rt_memset((void *)&i2c2_bus, 0, sizeof(struct rt_i2c_bus_device)); + i2c2_bus.priv = (void *)&drv_bit_ops; + rt_i2c_bit_add_bus(&i2c2_bus, I2C_BUS_NAME); + return RT_EOK; +} +INIT_DEVICE_EXPORT(drv_i2c_init); +/* end of i2c driver */ diff --git a/bsp/stm32f10x-HAL/drivers/drv_i2c.h b/bsp/stm32f10x-HAL/drivers/drv_i2c.h new file mode 100644 index 0000000000..f41b5406b9 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_i2c.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-06-05 tanek first implementation. + */ +#ifndef __DRV_I2C__ +#define __DRV_I2C__ +int hw_i2c_init(void); +#endif diff --git a/bsp/stm32f10x-HAL/drivers/drv_iwg.c b/bsp/stm32f10x-HAL/drivers/drv_iwg.c new file mode 100644 index 0000000000..1d170b2df0 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_iwg.c @@ -0,0 +1,71 @@ +/* + * File : drv_iwg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2017-11-08 ZYH the first version + */ + +#include +#include +#include +#include + + +#ifdef RT_USING_WDT +IWDG_HandleTypeDef hiwdg; +static rt_err_t drv_init(rt_watchdog_t *wdt) +{ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_16; //1s + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + RT_ASSERT(0); + } + return RT_EOK; +} + +static rt_err_t drv_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + hiwdg.Init.Reload = (rt_uint32_t)arg; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + return RT_ERROR; + } + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + HAL_IWDG_Refresh(&hiwdg); + break; + default: + return RT_ERROR; + } + return RT_EOK; +} + +static struct rt_watchdog_ops _ops = + { + drv_init, + drv_control + }; + +static rt_watchdog_t _iwg = + { + .ops = &_ops + }; + +int rt_iwg_init(void) +{ + return rt_hw_watchdog_register(&_iwg, "iwg", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL); +} +INIT_BOARD_EXPORT(rt_iwg_init); +#endif diff --git a/bsp/stm32f10x-HAL/drivers/drv_iwg.h b/bsp/stm32f10x-HAL/drivers/drv_iwg.h new file mode 100644 index 0000000000..4bd63a6ca9 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_iwg.h @@ -0,0 +1,18 @@ +/* + * File : drv_iwg.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2017-11-08 ZYH the first version + */ + +#ifndef __DRV_IWG_H__ +#define __DRV_IWG_H__ +extern int rt_iwg_init(void); +#endif diff --git a/bsp/stm32f10x-HAL/drivers/drv_pwm.c b/bsp/stm32f10x-HAL/drivers/drv_pwm.c new file mode 100644 index 0000000000..f08cb66806 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_pwm.c @@ -0,0 +1,842 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-07-15 ZYH first version + * 2018-10-19 XXXXzzzz000 transplant from stm32f4xx-HAL drv_pwm.c + */ +#include +#include +#include +#include + +#define MAX_PERIOD 65535 +#define MIN_PERIOD 3 +#define MIN_PULSE 2 + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static struct rt_pwm_ops drv_ops = + { + drv_pwm_control}; + +static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + if (!enable) + { + HAL_TIM_PWM_Stop(htim, channel); + } + else + { + HAL_TIM_PWM_Start(htim, channel); + } + return RT_EOK; +} + +static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + rt_uint32_t tim_clock; + + tim_clock = SystemCoreClock; + + if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) + { + tim_clock = tim_clock / 2; + } + else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4) + { + tim_clock = tim_clock / 4; + } + tim_clock /= 1000000UL; + configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; + configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; + return RT_EOK; +} + +static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint32_t tim_clock, psc; + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + + tim_clock = SystemCoreClock; + + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL; + psc = period / MAX_PERIOD + 1; + period = period / psc; + __HAL_TIM_SET_PRESCALER(htim, psc - 1); + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + __HAL_TIM_SET_AUTORELOAD(htim, period - 1); + pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1); + __HAL_TIM_SET_COUNTER(htim, 0); + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(htim, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(htim, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(htim, configuration); + case PWM_CMD_GET: + return drv_pwm_get(htim, configuration); + default: + return RT_EINVAL; + } +} + +static void HAL_TIM_MspPostInit(TIM_HandleTypeDef *timHandle); + +#ifdef BSP_USING_PWM1 +TIM_HandleTypeDef htim1; +#endif +#ifdef BSP_USING_PWM2 +TIM_HandleTypeDef htim2; +#endif +#ifdef BSP_USING_PWM3 +TIM_HandleTypeDef htim3; +#endif +#ifdef BSP_USING_PWM4 +TIM_HandleTypeDef htim4; +#endif +#ifdef BSP_USING_PWM5 +TIM_HandleTypeDef htim5; +#endif +#ifdef BSP_USING_PWM8 +TIM_HandleTypeDef htim8; +#endif + +#ifdef BSP_USING_PWM1 +static void MX_TIM1_Init(void) +{ + TIM_MasterConfigTypeDef sMasterConfig; + TIM_OC_InitTypeDef sConfigOC; + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig; + + htim1.Instance = TIM1; + htim1.Init.Prescaler = 0; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.Period = 0; + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim1.Init.RepetitionCounter = 0; + if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) + { + RT_ASSERT(0); + } + if (HAL_TIM_OC_Init(&htim1) != HAL_OK) + { + RT_ASSERT(0); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + { + RT_ASSERT(0); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + +#ifdef BSP_USING_PWM1_CH1 + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM1_CH1 */ + +#ifdef BSP_USING_PWM1_CH2 + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM1_CH2 */ + sConfigOC.OCMode = TIM_OCMODE_TIMING; +#ifdef BSP_USING_PWM1_CH3 + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM1_CH3 */ + +#ifdef BSP_USING_PWM1_CH4 + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM1_CH4 */ + + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = 0; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + + if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) + { + RT_ASSERT(0); + } + HAL_TIM_MspPostInit(&htim1); +} +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +static void MX_TIM2_Init(void) +{ + TIM_MasterConfigTypeDef sMasterConfig; + TIM_OC_InitTypeDef sConfigOC; + + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + { + RT_ASSERT(0); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + RT_ASSERT(0); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + +#ifdef BSP_USING_PWM2_CH1 + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM2_CH1 */ + +#ifdef BSP_USING_PWM2_CH2 + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM2_CH2 */ + +#ifdef BSP_USING_PWM2_CH3 + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM2_CH3 */ + +#ifdef BSP_USING_PWM2_CH4 + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM2_CH3 */ + + HAL_TIM_MspPostInit(&htim2); +} +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +void MX_TIM3_Init(void) +{ + TIM_MasterConfigTypeDef sMasterConfig; + TIM_OC_InitTypeDef sConfigOC; + + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 0; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + RT_ASSERT(0); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + RT_ASSERT(0); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; +#ifdef BSP_USING_PWM3_CH1 + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM3_CH1 */ + +#ifdef BSP_USING_PWM3_CH2 + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM3_CH2 */ + +#ifdef BSP_USING_PWM3_CH3 + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM3_CH3 */ + +#ifdef BSP_USING_PWM3_CH4 + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM3_CH4 */ + + HAL_TIM_MspPostInit(&htim3); +} +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +void MX_TIM4_Init(void) +{ + TIM_MasterConfigTypeDef sMasterConfig; + TIM_OC_InitTypeDef sConfigOC; + + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 0; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { + RT_ASSERT(0); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + RT_ASSERT(0); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; +#ifdef BSP_USING_PWM4_CH1 + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM4_CH1 */ + +#ifdef BSP_USING_PWM4_CH2 + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM4_CH2 */ + +#ifdef BSP_USING_PWM4_CH3 + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM4_CH3 */ + +#ifdef BSP_USING_PWM4_CH4 + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM4_CH4 */ + + HAL_TIM_MspPostInit(&htim4); +} +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +void MX_TIM5_Init(void) +{ + TIM_MasterConfigTypeDef sMasterConfig; + TIM_OC_InitTypeDef sConfigOC; + + htim5.Instance = TIM5; + htim5.Init.Prescaler = 0; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 0; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_PWM_Init(&htim5) != HAL_OK) + { + RT_ASSERT(0); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + RT_ASSERT(0); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; +#ifdef BSP_USING_PWM5_CH1 + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM5_CH1 */ + +#ifdef BSP_USING_PWM5_CH2 + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM5_CH2 */ + +#ifdef BSP_USING_PWM5_CH3 + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM5_CH3 */ + +#ifdef BSP_USING_PWM5_CH4 + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM5_CH3 */ + + HAL_TIM_MspPostInit(&htim5); +} +#endif /* BSP_USING_PWM5 */ + +#ifdef BSP_USING_PWM8 +static void MX_TIM8_Init(void) +{ + TIM_MasterConfigTypeDef sMasterConfig; + TIM_OC_InitTypeDef sConfigOC; + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig; + + htim8.Instance = TIM8; + htim8.Init.Prescaler = 0; + htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + htim8.Init.Period = 0; + htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim8.Init.RepetitionCounter = 0; + if (HAL_TIM_PWM_Init(&htim8) != HAL_OK) + { + RT_ASSERT(0); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + { + RT_ASSERT(0); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + +#ifdef BSP_USING_PWM8_CH1 + if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM8_CH1 */ + +#ifdef BSP_USING_PWM8_CH2 + if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM8_CH2 */ + +#ifdef BSP_USING_PWM8_CH3 + if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM8_CH3 */ + +#ifdef BSP_USING_PWM8_CH4 + if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + RT_ASSERT(0); + } +#endif /* BSP_USING_PWM8_CH4 */ + + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = 0; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + + if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK) + { + RT_ASSERT(0); + } + HAL_TIM_MspPostInit(&htim8); +} +#endif /* BSP_USING_PWM8 */ + +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *tim_pwmHandle) +{ + if (tim_pwmHandle->Instance == TIM1) + { + __HAL_RCC_TIM1_CLK_ENABLE(); + } + else if (tim_pwmHandle->Instance == TIM2) + { + __HAL_RCC_TIM2_CLK_ENABLE(); + } + else if (tim_pwmHandle->Instance == TIM3) + { + __HAL_RCC_TIM3_CLK_ENABLE(); + } + else if (tim_pwmHandle->Instance == TIM4) + { + __HAL_RCC_TIM4_CLK_ENABLE(); + } + else if (tim_pwmHandle->Instance == TIM5) + { + __HAL_RCC_TIM5_CLK_ENABLE(); + } + else if (tim_pwmHandle->Instance == TIM8) + { + __HAL_RCC_TIM8_CLK_ENABLE(); + } +} + +static void HAL_TIM_MspPostInit(TIM_HandleTypeDef *timHandle) +{ + GPIO_InitTypeDef GPIO_InitStruct; + if (timHandle->Instance == TIM1) + { + /**TIM1 GPIO Configuration + PE9 ------> TIM1_CH1 + PE11 ------> TIM1_CH2 + PE13 ------> TIM1_CH3 + PE14 ------> TIM1_CH4 + */ +#if defined(BSP_USING_PWM1_CH1) || defined(BSP_USING_PWM1_CH2) || defined(BSP_USING_PWM1_CH3) || defined(BSP_USING_PWM1_CH4) + __HAL_RCC_GPIOE_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; + +#ifdef BSP_USING_PWM1_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_9; +#endif +#ifdef BSP_USING_PWM1_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_11; +#endif + /* FIXME:通道3,4无输出 +#ifdef BSP_USING_PWM1_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_13; +#endif +#ifdef BSP_USING_PWM1_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_14; +#endif +*/ + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + __HAL_AFIO_REMAP_TIM1_ENABLE(); +#endif + } + else if (timHandle->Instance == TIM2) + { + /**TIM2 GPIO Configuration + PB10 ------> TIM2_CH3 + PB11 ------> TIM2_CH4 + PA15 ------> TIM2_CH1 + PB3 ------> TIM2_CH2 + */ +#if defined(BSP_USING_PWM2_CH1) || defined(BSP_USING_PWM2_CH2) || defined(BSP_USING_PWM2_CH4) + + __HAL_RCC_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM2_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_10; +#endif +#ifdef BSP_USING_PWM2_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_11; +#endif +#ifdef BSP_USING_PWM2_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_3; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + +#if defined(BSP_USING_PWM2_CH3) + __HAL_RCC_GPIOA_CLK_ENABLE(); + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM2_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_15; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM2_ENABLE(); +#endif + } + else if (timHandle->Instance == TIM3) + { + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + PB0 ------> TIM3_CH3 + PB1 ------> TIM3_CH4 + */ +#if defined(BSP_USING_PWM3_CH1) || defined(BSP_USING_PWM3_CH2) + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM3_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_6; +#endif +#ifdef BSP_USING_PWM3_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_7; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + GPIO_InitStruct.Pin = 0x00; +#endif + +#if defined(BSP_USING_PWM3_CH3) || defined(BSP_USING_PWM3_CH4) + __HAL_RCC_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM3_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_0; +#endif +#ifdef BSP_USING_PWM3_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_1; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + } + else if (timHandle->Instance == TIM4) + { + /**TIM4 GPIO Configuration + PD12 ------> TIM4_CH1 + PD13 ------> TIM4_CH2 + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ +#if defined(BSP_USING_PWM4_CH1) || defined(BSP_USING_PWM4_CH2) || defined(BSP_USING_PWM4_CH3) || defined(BSP_USING_PWM4_CH4) + __HAL_RCC_GPIOD_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM4_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_12; +#endif +#ifdef BSP_USING_PWM4_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_13; +#endif +#ifdef BSP_USING_PWM4_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_14; +#endif +#ifdef BSP_USING_PWM4_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_15; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM4_ENABLE(); +#endif + } + else if (timHandle->Instance == TIM5) + { + /**TIM5 GPIO Configuration + PA0-WKUP ------> TIM5_CH1 + PA1 ------> TIM5_CH2 + PA2 ------> TIM5_CH3 + PA3 ------> TIM5_CH4 + */ +#if defined(BSP_USING_PWM5_CH1) || defined(BSP_USING_PWM5_CH2) || defined(BSP_USING_PWM5_CH3) || defined(BSP_USING_PWM5_CH4) + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM5_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_0; +#endif +#ifdef BSP_USING_PWM5_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_1; +#endif +#ifdef BSP_USING_PWM5_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_2; +#endif +#ifdef BSP_USING_PWM5_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_3; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif + } + else if (timHandle->Instance == TIM8) + { + /**TIM8 GPIO Configuration + PC6 ------> TIM8_CH1 + PC7 ------> TIM8_CH2 + PC8 ------> TIM8_CH3 + PC9 ------> TIM8_CH4 + */ +#if defined(BSP_USING_PWM8_CH1) || defined(BSP_USING_PWM8_CH2) || defined(BSP_USING_PWM8_CH3) || defined(BSP_USING_PWM8_CH4) + __HAL_RCC_GPIOC_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM8_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_6; +#endif +#ifdef BSP_USING_PWM8_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_7; +#endif +#ifdef BSP_USING_PWM8_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_8; +#endif +#ifdef BSP_USING_PWM8_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_9; +#endif + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); +#endif + } +} + +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *tim_pwmHandle) +{ + if (tim_pwmHandle->Instance == TIM1) + { + __HAL_RCC_TIM1_CLK_DISABLE(); + } + else if (tim_pwmHandle->Instance == TIM2) + { + __HAL_RCC_TIM2_CLK_DISABLE(); + } + else if (tim_pwmHandle->Instance == TIM3) + { + __HAL_RCC_TIM3_CLK_DISABLE(); + } + else if (tim_pwmHandle->Instance == TIM4) + { + __HAL_RCC_TIM4_CLK_DISABLE(); + } + else if (tim_pwmHandle->Instance == TIM5) + { + __HAL_RCC_TIM5_CLK_DISABLE(); + } + else if (tim_pwmHandle->Instance == TIM8) + { + __HAL_RCC_TIM8_CLK_DISABLE(); + } +} +int drv_pwm_init(void) +{ +#ifdef BSP_USING_PWM1 + MX_TIM1_Init(); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm1", &drv_ops, &htim1); +#endif + +#ifdef BSP_USING_PWM2 + MX_TIM2_Init(); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm2", &drv_ops, &htim2); +#endif + +#ifdef BSP_USING_PWM3 + MX_TIM3_Init(); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm3", &drv_ops, &htim3); +#endif + +#ifdef BSP_USING_PWM4 + MX_TIM4_Init(); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm4", &drv_ops, &htim4); +#endif + +#ifdef BSP_USING_PWM5 + MX_TIM5_Init(); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm5", &drv_ops, &htim5); +#endif +#ifdef BSP_USING_PWM8 + MX_TIM8_Init(); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm8", &drv_ops, &htim8); +#endif + return 0; +} +INIT_DEVICE_EXPORT(drv_pwm_init); + +/* pwm test cmd */ +static int pwm_test(int argc, char **argv) +{ + char *pwmc = argv[1]; + rt_device_t pwmd = rt_device_find(argv[1]); + struct rt_pwm_configuration cfg = + { + .channel = 0, /* 0-n */ + .period = 100, /* unit:ns 1ns~4.29s:1Ghz~0.23hz */ + .pulse = 50 /* unit:ns (pulse<=period) */ + }; + for (int i = 1; i < 5; i++) + { + cfg.channel = i; + rt_device_control(pwmd, PWM_CMD_SET, &cfg); + rt_device_control(pwmd, PWM_CMD_ENABLE, &cfg); + } +} +MSH_CMD_EXPORT(pwm_test, pwm_test pwm1); \ No newline at end of file diff --git a/bsp/stm32f10x-HAL/drivers/drv_rtc.c b/bsp/stm32f10x-HAL/drivers/drv_rtc.c new file mode 100644 index 0000000000..fee0fb0b27 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_rtc.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-25 ZYH first implementation + * 2018-10-23 XXXXzzzz000 first implementation,referance:stm32f4xx-HAL/drv_rtc.c + */ +#include +#include +#include +#include + +#include +#include +RTC_HandleTypeDef hrtc; +/* RTC init function */ +void MX_RTC_Init(void) +{ + RTC_TimeTypeDef sTime; + RTC_DateTypeDef sDate; + /* Initialize RTC Only */ + hrtc.Instance = RTC; + hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; + hrtc.Init.OutPut = RTC_OUTPUTSOURCE_NONE; + RT_ASSERT(HAL_RTC_Init(&hrtc) == HAL_OK); + /* Initialize RTC and set the Time and Date */ + if (HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_DR1) != 0x32F1) + { + sTime.Hours = 0x0; + sTime.Minutes = 0x0; + sTime.Seconds = 0x0; + RT_ASSERT(HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK); + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + sDate.Month = RTC_MONTH_JANUARY; + sDate.Date = 1; + sDate.Year = 0; + RT_ASSERT(HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK); + } + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_DR1, 0x32F1); +} + +void HAL_RTC_MspInit(RTC_HandleTypeDef *rtcHandle) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + if (rtcHandle->Instance == RTC) + { + + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWR_EnableBkUpAccess(); + + __HAL_RCC_BKP_CLK_ENABLE(); + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + __HAL_RCC_RTC_ENABLE(); + } +} + +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *rtcHandle) +{ + if (rtcHandle->Instance == RTC) + { + /* 禁用RTC时钟 */ + __HAL_RCC_RTC_DISABLE(); + + /* 禁用PWR时钟和读取备份域 */ + HAL_PWR_DisableBkUpAccess(); + __HAL_RCC_PWR_CLK_DISABLE(); + + /* 禁用备份时钟：备份寄存器 */ + __HAL_RCC_BKP_CLK_DISABLE(); + } +} + +static rt_err_t stm32_rtc_control(struct rt_device *dev, + int cmd, + void *args) +{ + struct tm *tm_now; + struct tm now; + RTC_TimeTypeDef sTime; + RTC_DateTypeDef sDate; + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN); + HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN); + now.tm_hour = sTime.Hours; + now.tm_min = sTime.Minutes; + now.tm_sec = sTime.Seconds; + now.tm_year = sDate.Year + 100; + now.tm_mon = sDate.Month - 1; + now.tm_mday = sDate.Date; + *((time_t *)args) = mktime(&now); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + rt_enter_critical(); + /* converts calendar time time into local time. */ + tm_now = localtime((const time_t *)args); + /* copy the statically located variable */ + memcpy(&now, tm_now, sizeof(struct tm)); + /* unlock scheduler. */ + rt_exit_critical(); + sTime.Hours = now.tm_hour; + sTime.Minutes = now.tm_min; + sTime.Seconds = now.tm_sec; + sDate.Year = now.tm_year - 100; + sDate.Month = now.tm_mon + 1; + sDate.Date = now.tm_mday; + HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN); + HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN); + break; + } + return RT_EOK; +} + +static rt_err_t stm32_rtc_init(struct rt_device *dev) +{ + return RT_EOK; +} + +static rt_err_t stm32_rtc_open(struct rt_device *dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t stm32_rtc_close(struct rt_device *dev) +{ + return RT_EOK; +} + +static rt_size_t stm32_rtc_read(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + stm32_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer); + return size; +} + +static rt_size_t stm32_rtc_write(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + stm32_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer); + return size; +} + +struct rt_device rtc_device; +int rt_hw_rtc_init(void) +{ + MX_RTC_Init(); + rtc_device.type = RT_Device_Class_RTC; + rtc_device.rx_indicate = RT_NULL; + rtc_device.tx_complete = RT_NULL; + rtc_device.init = stm32_rtc_init; + rtc_device.open = stm32_rtc_open; + rtc_device.close = stm32_rtc_close; + rtc_device.read = stm32_rtc_read; + rtc_device.write = stm32_rtc_write; + rtc_device.control = stm32_rtc_control; + rtc_device.user_data = RT_NULL; + /* register a character device */ + return rt_device_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR); +} +INIT_BOARD_EXPORT(rt_hw_rtc_init); + +static void rtc_set(uint8_t argc, char **argv) +{ + rt_device_t rtc = rt_device_find("rtc"); + RT_ASSERT(rtc != NULL); + struct tm now = { + .tm_hour = 10, + .tm_min = 35, + .tm_sec = 0, + .tm_year = 2018 - 1900, + .tm_mon = 10 - 1, + .tm_mday = 23, + }; + time_t tim = mktime(&now); + rt_device_control(rtc, RT_DEVICE_CTRL_RTC_SET_TIME, &tim); + int ret = rt_device_write(rtc, 0, &tim, 0); +} +MSH_CMD_EXPORT(rtc_set, rtc_set yyyy mm dd hh mm ss); + +static void rtc_get(uint8_t argc, char **argv) +{ + rt_device_t rtc = rt_device_find("rtc"); + RT_ASSERT(rtc != NULL); + struct tm *tm_now; + time_t tim; + struct tm now; + rt_device_control(rtc, RT_DEVICE_CTRL_RTC_GET_TIME, &tim); + + rt_enter_critical(); + tm_now = localtime(&tim); + memcpy(&now, tm_now, sizeof(struct tm)); + rt_exit_critical(); + rt_kprintf("%d/%d/%d %d:%d:%d\n", now.tm_year + 1900, now.tm_mon + 1, now.tm_mday, now.tm_hour, now.tm_min, now.tm_sec); +} +MSH_CMD_EXPORT(rtc_get, rtc_get); \ No newline at end of file diff --git a/bsp/stm32f10x-HAL/drivers/drv_rtc.h b/bsp/stm32f10x-HAL/drivers/drv_rtc.h new file mode 100644 index 0000000000..ed76f70160 --- /dev/null +++ b/bsp/stm32f10x-HAL/drivers/drv_rtc.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-25 ZYH first implementation + * 2018-10-23 XXXXzzzz000 first implementation,referance:stm32f4xx-HAL/drv_rtc.h + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ +extern int rt_hw_rtc_init(void); +#endif diff --git a/bsp/stm32f10x-HAL/drivers/drv_sdcard.c b/bsp/stm32f10x-HAL/drivers/drv_sdcard.c index e3486d1959..7e5959f63b 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_sdcard.c +++ b/bsp/stm32f10x-HAL/drivers/drv_sdcard.c @@ -1,21 +1,8 @@ /* - * File : drv_sdcard.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * SPDX-License-Identifier: Apache-2.0 * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_sdcard.h b/bsp/stm32f10x-HAL/drivers/drv_sdcard.h index beaf1faf2b..133173832f 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_sdcard.h +++ b/bsp/stm32f10x-HAL/drivers/drv_sdcard.h @@ -1,21 +1,8 @@ /* - * File : drv_sdcard.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * SPDX-License-Identifier: Apache-2.0 * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_spi.c b/bsp/stm32f10x-HAL/drivers/drv_spi.c index 14b24365fb..2262f76caa 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_spi.c +++ b/bsp/stm32f10x-HAL/drivers/drv_spi.c @@ -1,11 +1,8 @@ /* - * File : dev_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_spi.h b/bsp/stm32f10x-HAL/drivers/drv_spi.h index ce88c2be34..90dcbf6b5a 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_spi.h +++ b/bsp/stm32f10x-HAL/drivers/drv_spi.h @@ -1,11 +1,8 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_usart.c b/bsp/stm32f10x-HAL/drivers/drv_usart.c index 771f4d62a1..2650469921 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_usart.c +++ b/bsp/stm32f10x-HAL/drivers/drv_usart.c @@ -1,11 +1,8 @@ /* - * File : drv_usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes @@ -220,8 +217,6 @@ void USART3_IRQHandler(void) } #endif /* RT_USING_UART2 */ -static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle); - int rt_hw_usart_init(void) { struct stm32_uart *uart; @@ -231,7 +226,6 @@ int rt_hw_usart_init(void) config.baud_rate = BAUD_RATE_115200; serial1.ops = &stm32_uart_ops; serial1.config = config; - MX_USART_UART_Init(&uart->huart); /* register UART1 device */ rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -243,7 +237,6 @@ int rt_hw_usart_init(void) config.baud_rate = BAUD_RATE_115200; serial2.ops = &stm32_uart_ops; serial2.config = config; - MX_USART_UART_Init(&uart->huart); /* register UART1 device */ rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -255,7 +248,6 @@ int rt_hw_usart_init(void) config.baud_rate = BAUD_RATE_115200; serial3.ops = &stm32_uart_ops; serial3.config = config; - MX_USART_UART_Init(&uart->huart); /* register UART1 device */ rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, @@ -265,22 +257,6 @@ int rt_hw_usart_init(void) } INIT_BOARD_EXPORT(rt_hw_usart_init); -static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle) -{ - rt_err_t result; - uartHandle->Init.BaudRate = 115200; - uartHandle->Init.WordLength = UART_WORDLENGTH_8B; - uartHandle->Init.StopBits = UART_STOPBITS_1; - uartHandle->Init.Parity = UART_PARITY_NONE; - uartHandle->Init.Mode = UART_MODE_TX_RX; - uartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE; - uartHandle->Init.OverSampling = UART_OVERSAMPLING_16; - result = HAL_UART_Init(uartHandle); - RT_ASSERT(result == HAL_OK); - -} -/* USART2 init function */ - void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) { GPIO_InitTypeDef GPIO_InitStruct; diff --git a/bsp/stm32f10x-HAL/drivers/drv_usart.h b/bsp/stm32f10x-HAL/drivers/drv_usart.h index 78b46739e5..a7352914a8 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_usart.h +++ b/bsp/stm32f10x-HAL/drivers/drv_usart.h @@ -1,11 +1,8 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_usb.c b/bsp/stm32f10x-HAL/drivers/drv_usb.c index 111fc1b308..b9bf9bb535 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_usb.c +++ b/bsp/stm32f10x-HAL/drivers/drv_usb.c @@ -1,11 +1,8 @@ /* - * File : drv_usb.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/drv_usb.h b/bsp/stm32f10x-HAL/drivers/drv_usb.h index 37932fae2a..c17204fca9 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_usb.h +++ b/bsp/stm32f10x-HAL/drivers/drv_usb.h @@ -1,11 +1,8 @@ /* - * File : drv_usb.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x-HAL/drivers/stm32f1xx_hal_conf.h b/bsp/stm32f10x-HAL/drivers/stm32f1xx_hal_conf.h index 32be5f38d0..1e5798337b 100644 --- a/bsp/stm32f10x-HAL/drivers/stm32f1xx_hal_conf.h +++ b/bsp/stm32f10x-HAL/drivers/stm32f1xx_hal_conf.h @@ -70,7 +70,7 @@ extern "C" { // #define HAL_I2C_MODULE_ENABLED // #define HAL_I2S_MODULE_ENABLED // #define HAL_IRDA_MODULE_ENABLED -// #define HAL_IWDG_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED // #define HAL_NAND_MODULE_ENABLED // #define HAL_NOR_MODULE_ENABLED // #define HAL_PCCARD_MODULE_ENABLED @@ -79,7 +79,9 @@ extern "C" { #endif #define HAL_PWR_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED -// #define HAL_RTC_MODULE_ENABLED +#ifdef RT_USING_RTC +#define HAL_RTC_MODULE_ENABLED +#endif #ifdef RT_USING_SDCARD #define HAL_SD_MODULE_ENABLED #endif diff --git a/bsp/stm32f10x-HAL/project.uvprojx b/bsp/stm32f10x-HAL/project.uvprojx index 3f5830884c..ec6814f43a 100644 --- a/bsp/stm32f10x-HAL/project.uvprojx +++ b/bsp/stm32f10x-HAL/project.uvprojx @@ -1,43 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rtthread-stm32 0x4 ARM-ADS - 5060528::V5.06 update 5 (build 528)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC 0 - STM32F103RB + STM32F103RC STMicroelectronics Keil.STM32F1xx_DFP.2.2.0 http://www.keil.com/pack/ - IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + IRAM(0x20000000,0xC000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM)) 0 - $$Device:STM32F103RB$Device\Include\stm32f10x.h - - - - - - - - - - $$Device:STM32F103RB$SVD\STM32F103xx.svd + $$Device:STM32F103RC$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RC$SVD\STM32F103xx.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,17 +104,17 @@ 0 0 3 - - + + 1 SARMCM3.DLL -REMAP - DCM.DLL - -pCM3 + DARMSTM.DLL + -pSTM32F103RC SARMCM3.DLL - + TCM.DLL -pCM3 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - "" () - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -241,12 +244,12 @@ 0 0x20000000 - 0x5000 + 0xc000 1 0x8000000 - 0x20000 + 0x40000 0 @@ -271,7 +274,7 @@ 1 0x8000000 - 0x20000 + 0x40000 1 @@ -296,7 +299,7 @@ 0 0x20000000 - 0x5000 + 0xc000 0 @@ -304,7 +307,7 @@ 0x0 - + 1 @@ -321,6 +324,7 @@ 0 0 1 + 0 0 1 1 @@ -330,9 +334,9 @@ 0 0 - + STM32F103xB, USE_HAL_DRIVER - + drivers;applications;.;Libraries/CMSIS/Device/ST/STM32F1xx/Include;Libraries/STM32F1xx_HAL_Driver/Inc;Libraries/CMSIS/Include;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/finsh @@ -348,10 +352,10 @@ 0 0 - - - - + + + + @@ -363,13 +367,13 @@ 0 0x08000000 0x20000000 - - - - - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + .\build\rtthread-stm32.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + @@ -382,22 +386,16 @@ 1 drivers/board.c - - stm32f1xx_it.c 1 drivers/stm32f1xx_it.c - - drv_gpio.c 1 drivers/drv_gpio.c - - drv_usart.c 1 @@ -423,330 +421,236 @@ 1 Libraries/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c - - stm32f1xx_hal_adc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c - - stm32f1xx_hal_adc_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c - - stm32f1xx_hal_gpio.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c - - stm32f1xx_hal_gpio_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c - - stm32f1xx_hal_flash.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c - - stm32f1xx_hal_flash_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c - - stm32f1xx_hal_dma.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c - - stm32f1xx_hal_cortex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c - - stm32f1xx_hal_crc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c - - stm32f1xx_hal_i2c.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c - - stm32f1xx_hal_irda.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_irda.c - - stm32f1xx_hal_iwdg.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c - - stm32f1xx_hal_pwr.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c - - stm32f1xx_hal_rcc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c - - stm32f1xx_hal_rcc_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c - - stm32f1xx_hal_rtc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c - - stm32f1xx_hal_rtc_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c - - stm32f1xx_hal_smartcard.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c - - stm32f1xx_hal_spi.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c - - stm32f1xx_hal_spi_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c - - stm32f1xx_hal_tim.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c - - stm32f1xx_hal_tim_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c - - stm32f1xx_hal_uart.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c - - stm32f1xx_hal_usart.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c - - stm32f1xx_hal_wwdg.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c - - stm32f1xx_hal.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c - - stm32f1xx_ll_adc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c - - stm32f1xx_ll_crc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c - - stm32f1xx_ll_dac.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c - - stm32f1xx_ll_dma.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c - - stm32f1xx_ll_exti.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c - - stm32f1xx_ll_fsmc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c - - stm32f1xx_ll_gpio.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c - - stm32f1xx_ll_i2c.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c - - stm32f1xx_ll_pwr.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c - - stm32f1xx_ll_rcc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c - - stm32f1xx_ll_rtc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rtc.c - - stm32f1xx_ll_sdmmc.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c - - stm32f1xx_ll_spi.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c - - stm32f1xx_ll_tim.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c - - stm32f1xx_ll_usart.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c - - stm32f1xx_ll_usb.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c - - stm32f1xx_ll_utils.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c - - stm32f1xx_hal_can.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c - - stm32f1xx_hal_pcd.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c - - stm32f1xx_hal_pcd_ex.c 1 Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c - - startup_stm32f103xb.s 2 @@ -762,99 +666,71 @@ 1 ../../src/clock.c - - components.c 1 ../../src/components.c - - device.c 1 ../../src/device.c - - idle.c 1 ../../src/idle.c - - ipc.c 1 ../../src/ipc.c - - irq.c 1 ../../src/irq.c - - kservice.c 1 ../../src/kservice.c - - mem.c 1 ../../src/mem.c - - memheap.c 1 ../../src/memheap.c - - mempool.c 1 ../../src/mempool.c - - object.c 1 ../../src/object.c - - scheduler.c 1 ../../src/scheduler.c - - signal.c 1 ../../src/signal.c - - thread.c 1 ../../src/thread.c - - timer.c 1 @@ -870,29 +746,21 @@ 1 ../../libcpu/arm/cortex-m3/cpuport.c - - context_rvds.S 2 ../../libcpu/arm/cortex-m3/context_rvds.S - - backtrace.c 1 ../../libcpu/arm/common/backtrace.c - - div0.c 1 ../../libcpu/arm/common/div0.c - - showmem.c 1 @@ -908,50 +776,36 @@ 1 ../../components/drivers/misc/pin.c - - serial.c 1 ../../components/drivers/serial/serial.c - - completion.c 1 ../../components/drivers/src/completion.c - - dataqueue.c 1 ../../components/drivers/src/dataqueue.c - - pipe.c 1 ../../components/drivers/src/pipe.c - - ringbuffer.c 1 ../../components/drivers/src/ringbuffer.c - - waitqueue.c 1 ../../components/drivers/src/waitqueue.c - - workqueue.c 1 @@ -967,36 +821,26 @@ 1 ../../components/finsh/shell.c - - symbol.c 1 ../../components/finsh/symbol.c - - cmd.c 1 ../../components/finsh/cmd.c - - msh.c 1 ../../components/finsh/msh.c - - msh_cmd.c 1 ../../components/finsh/msh_cmd.c - - msh_file.c 1 @@ -1007,9 +851,11 @@ + - - - + + + + diff --git a/bsp/stm32f10x-HAL/template.uvprojx b/bsp/stm32f10x-HAL/template.uvprojx index 4559d8f28c..5f542f225b 100644 --- a/bsp/stm32f10x-HAL/template.uvprojx +++ b/bsp/stm32f10x-HAL/template.uvprojx @@ -14,16 +14,16 @@ 0 - STM32F103RB + STM32F103RC STMicroelectronics Keil.STM32F1xx_DFP.2.2.0 http://www.keil.com/pack/ - IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + IRAM(0x20000000,0xC000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM)) 0 - $$Device:STM32F103RB$Device\Include\stm32f10x.h + $$Device:STM32F103RC$Device\Include\stm32f10x.h @@ -33,7 +33,7 @@ - $$Device:STM32F103RB$SVD\STM32F103xx.svd + $$Device:STM32F103RC$SVD\STM32F103xx.svd 0 0 @@ -111,8 +111,8 @@ SARMCM3.DLL -REMAP - DCM.DLL - -pCM3 + DARMSTM.DLL + -pSTM32F103RC SARMCM3.DLL TCM.DLL @@ -138,7 +138,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -244,12 +244,12 @@ 0 0x20000000 - 0x5000 + 0xc000 1 0x8000000 - 0x20000 + 0x40000 0 @@ -274,7 +274,7 @@ 1 0x8000000 - 0x20000 + 0x40000 1 @@ -299,7 +299,7 @@ 0 0x20000000 - 0x5000 + 0xc000 0 @@ -324,6 +324,7 @@ 0 0 1 + 0 0 1 1 diff --git a/bsp/stm32f10x/applications/application.c b/bsp/stm32f10x/applications/application.c index 774940de46..3db9063f53 100644 --- a/bsp/stm32f10x/applications/application.c +++ b/bsp/stm32f10x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/applications/canapp.c b/bsp/stm32f10x/applications/canapp.c index ba9d592247..542fbd04bc 100644 --- a/bsp/stm32f10x/applications/canapp.c +++ b/bsp/stm32f10x/applications/canapp.c @@ -1,11 +1,7 @@ /* - * File : canapp.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/applications/startup.c b/bsp/stm32f10x/applications/startup.c index 713d221396..31a2fa911c 100644 --- a/bsp/stm32f10x/applications/startup.c +++ b/bsp/stm32f10x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,7 +21,7 @@ extern int rt_application_init(void); -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #elif __ICCARM__ #pragma section="HEAP" @@ -66,7 +62,7 @@ void rtthread_startup(void) #if STM32_EXT_SRAM rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END); #else -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END); diff --git a/bsp/stm32f10x/drivers/Kconfig b/bsp/stm32f10x/drivers/Kconfig index 763009674b..0e326c88ec 100644 --- a/bsp/stm32f10x/drivers/Kconfig +++ b/bsp/stm32f10x/drivers/Kconfig @@ -1,3 +1,9 @@ +config BSP_USING_I2C + bool "Enable I2C1 (PB6/7)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + config RT_USING_UART1 bool "Enable UART1 (PA9/10)" default y diff --git a/bsp/stm32f10x/drivers/SConscript b/bsp/stm32f10x/drivers/SConscript index 8e40f0c280..a518c1cffb 100644 --- a/bsp/stm32f10x/drivers/SConscript +++ b/bsp/stm32f10x/drivers/SConscript @@ -15,6 +15,9 @@ usart.c if GetDepend(['RT_USING_PIN']): src += ['gpio.c'] +if GetDepend(['BSP_USING_I2C']): + src += ['i2c.c'] + # add canbus driver. if GetDepend('RT_USING_CAN'): src += ['bxcan.c'] diff --git a/bsp/stm32f10x/drivers/board.c b/bsp/stm32f10x/drivers/board.c index f2525b718e..3829371308 100644 --- a/bsp/stm32f10x/drivers/board.c +++ b/bsp/stm32f10x/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/board.h b/bsp/stm32f10x/drivers/board.h index 79360b2d28..1a55866b50 100644 --- a/bsp/stm32f10x/drivers/board.h +++ b/bsp/stm32f10x/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/bxcan.c b/bsp/stm32f10x/drivers/bxcan.c index a3b717b786..e9032d8261 100644 --- a/bsp/stm32f10x/drivers/bxcan.c +++ b/bsp/stm32f10x/drivers/bxcan.c @@ -1,11 +1,7 @@ /* - * File : bxcan.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -512,12 +508,14 @@ static rt_err_t bxcancalcbaseoff(struct stm_bxcan *pbxcan, rt_int32_t hdr, rt_uint32_t fifo1start, fifo1end; rt_uint32_t ptr; fifo0start = 0; - fifo0end = pbxcan->filtermap[0].id32mask_cnt + fifo0end = fifo0start + + pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt + pbxcan->filtermap[0].id16mask_cnt + pbxcan->filtermap[0].id16bit_cnt ; fifo1start = pbxcan->fifo1filteroff * 4; - fifo1end = pbxcan->filtermap[1].id32mask_cnt + fifo1end = fifo1start + + pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt + pbxcan->filtermap[1].id16mask_cnt + pbxcan->filtermap[1].id16bit_cnt ; @@ -525,17 +523,18 @@ static rt_err_t bxcancalcbaseoff(struct stm_bxcan *pbxcan, rt_int32_t hdr, { *pbase = 0; ptr = 0; + hdr -= fifo0start; } else if (hdr >= fifo1start && hdr < fifo1end) { *pbase = pbxcan->fifo1filteroff; ptr = 1; + hdr -= fifo1start; } else { return RT_ERROR; } - ptr = 0; if (hdr > pbxcan->filtermap[ptr].id32mask_cnt) { hdr -= pbxcan->filtermap[ptr].id32mask_cnt; diff --git a/bsp/stm32f10x/drivers/bxcan.h b/bsp/stm32f10x/drivers/bxcan.h index 5e6cad087c..51ac616f3a 100644 --- a/bsp/stm32f10x/drivers/bxcan.h +++ b/bsp/stm32f10x/drivers/bxcan.h @@ -1,11 +1,7 @@ /* - * File : bxcan.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/dm9000a.c b/bsp/stm32f10x/drivers/dm9000a.c index a622122c58..0aa1ddb58c 100644 --- a/bsp/stm32f10x/drivers/dm9000a.c +++ b/bsp/stm32f10x/drivers/dm9000a.c @@ -1,11 +1,7 @@ /* - * File : dm9000a.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/dm9000a.h b/bsp/stm32f10x/drivers/dm9000a.h index a269f64215..0bfdadf16b 100644 --- a/bsp/stm32f10x/drivers/dm9000a.h +++ b/bsp/stm32f10x/drivers/dm9000a.h @@ -1,11 +1,7 @@ /* - * File : dm9000a.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/fm24cl64.c b/bsp/stm32f10x/drivers/fm24cl64.c index 2cf60e9068..05c02448dd 100644 --- a/bsp/stm32f10x/drivers/fm24cl64.c +++ b/bsp/stm32f10x/drivers/fm24cl64.c @@ -1,11 +1,7 @@ /* - * File : fm24cl64.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/fm24cl64.h b/bsp/stm32f10x/drivers/fm24cl64.h index bc613fea72..3b76d5ff41 100644 --- a/bsp/stm32f10x/drivers/fm24cl64.h +++ b/bsp/stm32f10x/drivers/fm24cl64.h @@ -1,11 +1,7 @@ /* - * File : fm24cl64.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/gpio.c b/bsp/stm32f10x/drivers/gpio.c index 5dc10faf32..d8c335fb3b 100755 --- a/bsp/stm32f10x/drivers/gpio.c +++ b/bsp/stm32f10x/drivers/gpio.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/gpio.h b/bsp/stm32f10x/drivers/gpio.h index 03b744b333..5e75adf443 100644 --- a/bsp/stm32f10x/drivers/gpio.h +++ b/bsp/stm32f10x/drivers/gpio.h @@ -1,11 +1,7 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/i2c.c b/bsp/stm32f10x/drivers/i2c.c new file mode 100644 index 0000000000..ad39335ad5 --- /dev/null +++ b/bsp/stm32f10x/drivers/i2c.c @@ -0,0 +1,85 @@ +#include "i2c.h" +#include + +void stm32_set_sda(void *data, rt_int32_t state) +{ + if(state == 1) + GPIO_SetBits(I2C1_GPIO , I2C1_GPIO_SDA); //GPIOB->BSRRL = I2C1_GPIO_SDA + else if(state == 0) + GPIO_ResetBits(I2C1_GPIO , I2C1_GPIO_SDA); //GPIOB->BSRRH = I2C1_GPIO_SDA +} + +void stm32_set_scl(void *data, rt_int32_t state) +{ + if(state == 1) + GPIO_SetBits(I2C1_GPIO , I2C1_GPIO_SCL); //GPIOB->BSRRL = I2C1_GPIO_SCL + else if(state == 0) + GPIO_ResetBits(I2C1_GPIO , I2C1_GPIO_SCL); //GPIOB->BSRRH = I2C1_GPIO_SCL +} + +rt_int32_t stm32_get_sda(void *data) +{ + return (rt_int32_t)GPIO_ReadInputDataBit(I2C1_GPIO , I2C1_GPIO_SDA); //return(GPIOB->IDR & I2C1_GPIO_SDA) +} + +rt_int32_t stm32_get_scl(void *data) +{ + return (rt_int32_t)GPIO_ReadInputDataBit(I2C1_GPIO , I2C1_GPIO_SCL); //return(GPIOB->IDR & I2C1_GPIO_SCL) +} + +void stm32_udelay(rt_uint32_t us) +{ + rt_uint32_t delta; + /* sysTick->LOAD=21000, RT_TICK_PER_SECOND=1000 */ + us = us * (SysTick->LOAD/(1000000/RT_TICK_PER_SECOND)); + delta = SysTick->VAL; + /* delay us */ + while (delta - SysTick->VAL< us); +} + +void stm32_mdelay(rt_uint32_t ms) +{ + stm32_udelay(ms * 1000); +} + +static const struct rt_i2c_bit_ops stm32_i2c_bit_ops = +{ + (void*)0xaa, //no use in set_sda,set_scl,get_sda,get_scl + stm32_set_sda, + stm32_set_scl, + stm32_get_sda, + stm32_get_scl, + stm32_udelay, + 20, +}; + +static void RCC_Configuration(void) +{ + RCC->APB2ENR|=1<<4; + RCC_APB2PeriphClockCmd( RCC_I2C, ENABLE ); +} + + +static void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = I2C1_GPIO_SDA | I2C1_GPIO_SCL; + GPIO_InitStructure.GPIO_Mode =GPIO_Mode_Out_OD ; + GPIO_InitStructure.GPIO_Speed =GPIO_Speed_50MHz; + GPIO_Init(I2C1_GPIO, &GPIO_InitStructure); +} + +int rt_hw_i2c_init(void) +{ + static struct rt_i2c_bus_device stm32_i2c; + + RCC_Configuration(); + GPIO_Configuration(); + + rt_memset((void *)&stm32_i2c, 0, sizeof(struct rt_i2c_bus_device)); + stm32_i2c.priv = (void *)&stm32_i2c_bit_ops; + rt_i2c_bit_add_bus(&stm32_i2c, "i2c1"); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); diff --git a/bsp/stm32f10x/drivers/i2c.h b/bsp/stm32f10x/drivers/i2c.h new file mode 100644 index 0000000000..4bc8217ae8 --- /dev/null +++ b/bsp/stm32f10x/drivers/i2c.h @@ -0,0 +1,25 @@ +#ifndef __I2C_SOFT_INIT_H__ +#define __I2C_SOFT_INIT_H__ + +#include +#include + +#define I2C1_GPIO GPIOB +#define I2C1_GPIO_SCL GPIO_Pin_6 +#define I2C1_GPIO_SDA GPIO_Pin_7 +#define RCC_I2C RCC_APB2Periph_GPIOB + +int rt_hw_i2c_init(void); + +void stm32_set_sda(void *data, rt_int32_t state); +void stm32_set_scl(void *data, rt_int32_t state); +rt_int32_t stm32_get_sda(void *data); +rt_int32_t stm32_get_scl(void *data); + +void stm32_udelay(rt_uint32_t us); +void stm32_mdelay(rt_uint32_t ms); + +static void RCC_Configuration(void); +static void GPIO_Configuration(void); + +#endif diff --git a/bsp/stm32f10x/drivers/led.c b/bsp/stm32f10x/drivers/led.c index 2a25fc19ac..ff43f4fa30 100644 --- a/bsp/stm32f10x/drivers/led.c +++ b/bsp/stm32f10x/drivers/led.c @@ -1,11 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/led.h b/bsp/stm32f10x/drivers/led.h index 31900cdc65..146a4260db 100644 --- a/bsp/stm32f10x/drivers/led.h +++ b/bsp/stm32f10x/drivers/led.h @@ -1,11 +1,8 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/stm32f1_i2c.c b/bsp/stm32f10x/drivers/stm32f1_i2c.c index e34cd0c63c..f7f7c8bf01 100644 --- a/bsp/stm32f10x/drivers/stm32f1_i2c.c +++ b/bsp/stm32f10x/drivers/stm32f1_i2c.c @@ -1,11 +1,7 @@ /* - * File : stm32f1_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/stm32f1_i2c.h b/bsp/stm32f10x/drivers/stm32f1_i2c.h index 0cebe02e85..c0658315bd 100644 --- a/bsp/stm32f10x/drivers/stm32f1_i2c.h +++ b/bsp/stm32f10x/drivers/stm32f1_i2c.h @@ -1,11 +1,7 @@ /* - * File : stm32f1_i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/stm32f1_rtc.c b/bsp/stm32f10x/drivers/stm32f1_rtc.c index 68fab1ce00..62a4afcafe 100644 --- a/bsp/stm32f10x/drivers/stm32f1_rtc.c +++ b/bsp/stm32f10x/drivers/stm32f1_rtc.c @@ -1,11 +1,7 @@ /* - * File : stm32f1_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/stm32f1_rtc.h b/bsp/stm32f10x/drivers/stm32f1_rtc.h index 02f463fce5..3bd050a178 100644 --- a/bsp/stm32f10x/drivers/stm32f1_rtc.h +++ b/bsp/stm32f10x/drivers/stm32f1_rtc.h @@ -1,11 +1,7 @@ /* - * File : stm32f1_rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/stm32f1_wdg.c b/bsp/stm32f10x/drivers/stm32f1_wdg.c index a26283fb27..d246219c96 100644 --- a/bsp/stm32f10x/drivers/stm32f1_wdg.c +++ b/bsp/stm32f10x/drivers/stm32f1_wdg.c @@ -1,11 +1,7 @@ /* - * File : stm32f1_wdg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/usart.c b/bsp/stm32f10x/drivers/usart.c index 65a05c3afe..3841a5c9f1 100644 --- a/bsp/stm32f10x/drivers/usart.c +++ b/bsp/stm32f10x/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f10x/drivers/usart.h b/bsp/stm32f10x/drivers/usart.h index 438578d86b..2127f3d533 100644 --- a/bsp/stm32f10x/drivers/usart.h +++ b/bsp/stm32f10x/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/24LCxx.c b/bsp/stm32f20x/Drivers/24LCxx.c index 1142a69aad..1903a85b82 100644 --- a/bsp/stm32f20x/Drivers/24LCxx.c +++ b/bsp/stm32f20x/Drivers/24LCxx.c @@ -1,11 +1,7 @@ /* - * File : 24LCxx.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/board.c b/bsp/stm32f20x/Drivers/board.c index 8bf9c07526..e3cfdbbc12 100644 --- a/bsp/stm32f20x/Drivers/board.c +++ b/bsp/stm32f20x/Drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/board.h b/bsp/stm32f20x/Drivers/board.h index a938eaf569..63a97b6b1c 100644 --- a/bsp/stm32f20x/Drivers/board.h +++ b/bsp/stm32f20x/Drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/drv_rtc.c b/bsp/stm32f20x/Drivers/drv_rtc.c index 1715a431d3..3c70a417d2 100644 --- a/bsp/stm32f20x/Drivers/drv_rtc.c +++ b/bsp/stm32f20x/Drivers/drv_rtc.c @@ -1,11 +1,7 @@ /* - * File : rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/drv_rtc.h b/bsp/stm32f20x/Drivers/drv_rtc.h index 1f54d59328..8f6c9a00a0 100644 --- a/bsp/stm32f20x/Drivers/drv_rtc.h +++ b/bsp/stm32f20x/Drivers/drv_rtc.h @@ -1,11 +1,7 @@ /* - * File : rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/i2c.c b/bsp/stm32f20x/Drivers/i2c.c index 7d3e0d8859..e1b4b02ffa 100644 --- a/bsp/stm32f20x/Drivers/i2c.c +++ b/bsp/stm32f20x/Drivers/i2c.c @@ -1,11 +1,7 @@ /* - * File : i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -93,7 +89,7 @@ Status I2C_AcknowledgePolling(I2C_TypeDef* I2Cx ,uint8_t Addr) } I2Cx->CR1 |= CR1_START_Set; - tmp = I2Cx->SR1;//MSB + tmp = I2Cx->SR1;//MSB I2Cx->DR = Addr; }while((I2Cx->SR1&0x0002) != 0x0002); diff --git a/bsp/stm32f20x/Drivers/serial.c b/bsp/stm32f20x/Drivers/serial.c index 644f1a2a55..4ccc041689 100644 --- a/bsp/stm32f20x/Drivers/serial.c +++ b/bsp/stm32f20x/Drivers/serial.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/serial.h b/bsp/stm32f20x/Drivers/serial.h index f1c698f74a..8ab56b4839 100644 --- a/bsp/stm32f20x/Drivers/serial.h +++ b/bsp/stm32f20x/Drivers/serial.h @@ -1,11 +1,7 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/usart.c b/bsp/stm32f20x/Drivers/usart.c index ae6a4ba926..ff82ab9f8a 100644 --- a/bsp/stm32f20x/Drivers/usart.c +++ b/bsp/stm32f20x/Drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Drivers/usart.h b/bsp/stm32f20x/Drivers/usart.h index 48925df880..176c179e5b 100644 --- a/bsp/stm32f20x/Drivers/usart.h +++ b/bsp/stm32f20x/Drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c b/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c index 63938af735..8db1e630f6 100644 --- a/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c +++ b/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c @@ -385,7 +385,7 @@ static void SetSysClock(void) RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) { } } diff --git a/bsp/stm32f20x/applications/application.c b/bsp/stm32f20x/applications/application.c index fcb378f62e..4f37de7b30 100644 --- a/bsp/stm32f20x/applications/application.c +++ b/bsp/stm32f20x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f20x/applications/startup.c b/bsp/stm32f20x/applications/startup.c index 71f4440507..77f915cbbd 100644 --- a/bsp/stm32f20x/applications/startup.c +++ b/bsp/stm32f20x/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,7 +22,7 @@ extern int rt_application_init(void); -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #elif __ICCARM__ #pragma section="HEAP" @@ -78,7 +74,7 @@ void rtthread_startup(void) #if STM32_EXT_SRAM rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END); #else - #ifdef __CC_ARM + #if defined(__CC_ARM) || defined(__CLANG_ARM) rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END); diff --git a/bsp/stm32f40x/.config b/bsp/stm32f40x/.config index f900be8d0c..b7945e1820 100644 --- a/bsp/stm32f40x/.config +++ b/bsp/stm32f40x/.config @@ -44,10 +44,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -60,7 +61,6 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -# CONFIG_RT_USING_MODULE is not set CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -69,7 +69,9 @@ CONFIG_ARCH_ARM_CORTEX_M4=y # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y -# CONFIG_RT_USING_USER_MAIN is not set +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -103,6 +105,7 @@ CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FILESYSTEMS_MAX=2 CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y # @@ -125,7 +128,6 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers @@ -163,7 +165,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set # CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_LWP is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -172,70 +174,22 @@ CONFIG_RT_USING_POSIX=y # # Socket abstraction layer # -CONFIG_RT_USING_SAL=y - -# -# protocol stack implement -# -CONFIG_SAL_USING_LWIP=y -CONFIG_SAL_USING_POSIX=y -CONFIG_SAL_PROTO_FAMILIES_NUM=4 +# CONFIG_RT_USING_SAL is not set # # light weight TCP/IP stack # -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP141 is not set -CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=5 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8192 -CONFIG_RT_LWIP_TCP_WND=8192 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=4 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=15 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=512 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=4 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set -CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_USING_LWIP is not set # # Modbus master and slave stack # # CONFIG_RT_USING_MODBUS is not set -# CONFIG_LWIP_USING_DHCPD is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set # # VBUS(Virtual Software BUS) @@ -270,7 +224,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set # # Wi-Fi @@ -288,9 +241,16 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_ONENET is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + # # security packages # @@ -339,10 +299,15 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_STM32F4_HAL is not set # CONFIG_PKG_USING_STM32F4_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set # # miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set @@ -355,7 +320,14 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # # sample package # -# CONFIG_PKG_USING_SAMPLES is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # # example package: hello diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c index 18fa12b803..1cd0875538 100644 --- a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c @@ -400,7 +400,7 @@ static void SetSysClock(void) RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) { } } diff --git a/bsp/stm32f40x/applications/application.c b/bsp/stm32f40x/applications/application.c deleted file mode 100644 index d0bffdc05e..0000000000 --- a/bsp/stm32f40x/applications/application.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2014-04-27 Bernard make code cleanup. - */ - -#include -#include - -#ifdef RT_USING_LWIP -#include -#include -#include -#include "stm32f4xx_eth.h" -#endif - -#ifdef RT_USING_FINSH -#include -#include -#endif - -#ifdef RT_USING_GDB -#include -#endif - -void rt_init_thread_entry(void* parameter) -{ - /* initialization RT-Thread Components */ - rt_components_init(); - - /* GDB STUB */ -#ifdef RT_USING_GDB - gdb_set_device("uart6"); - gdb_start(); -#endif -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - - if (tid != RT_NULL) - rt_thread_startup(tid); - - return 0; -} diff --git a/bsp/stm32f40x/applications/main.c b/bsp/stm32f40x/applications/main.c new file mode 100644 index 0000000000..41964f50dc --- /dev/null +++ b/bsp/stm32f40x/applications/main.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + * 2011-06-05 Bernard modify for STM32F107 version + */ + +#include +#include + +/** + * @addtogroup STM32 + */ + +/*@{*/ + +int main(void) +{ + /* user app entry */ + return 0; +} + +/*@}*/ diff --git a/bsp/stm32f40x/drivers/board.c b/bsp/stm32f40x/drivers/board.c index fe6742b70a..123f56bdad 100644 --- a/bsp/stm32f40x/drivers/board.c +++ b/bsp/stm32f40x/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -93,6 +89,10 @@ void rt_hw_board_init() /* Configure the SysTick */ SysTick_Configuration(); +#ifdef RT_USING_HEAP + rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END); +#endif + rt_components_board_init(); #ifdef RT_USING_CONSOLE diff --git a/bsp/stm32f40x/drivers/board.h b/bsp/stm32f40x/drivers/board.h index 4ca3cf41c6..2aeb007274 100644 --- a/bsp/stm32f40x/drivers/board.h +++ b/bsp/stm32f40x/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -46,6 +42,17 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define STM32_SRAM_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define STM32_SRAM_BEGIN (&__bss_end) +#endif + void rt_hw_board_init(void); #endif diff --git a/bsp/stm32f40x/drivers/drv_hwtimer.c b/bsp/stm32f40x/drivers/drv_hwtimer.c index 8802021e18..9feb19e145 100644 --- a/bsp/stm32f40x/drivers/drv_hwtimer.c +++ b/bsp/stm32f40x/drivers/drv_hwtimer.c @@ -1,11 +1,7 @@ /* - * File : drv_hwtimer.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f40x/drivers/gpio.c b/bsp/stm32f40x/drivers/gpio.c index 61fb8b3977..8a4c5bf2e4 100644 --- a/bsp/stm32f40x/drivers/gpio.c +++ b/bsp/stm32f40x/drivers/gpio.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -763,7 +759,7 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32 } else if (enabled == PIN_IRQ_DISABLE) { - irq = get_pin_irq(index->pin); + irq = get_pin_irq(pin); if (irq == RT_NULL) { return -RT_ENOSYS; diff --git a/bsp/stm32f40x/drivers/gpio.h b/bsp/stm32f40x/drivers/gpio.h index a4947b100d..be40ba3658 100644 --- a/bsp/stm32f40x/drivers/gpio.h +++ b/bsp/stm32f40x/drivers/gpio.h @@ -1,11 +1,7 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f40x/drivers/stm32f4_rtc.c b/bsp/stm32f40x/drivers/stm32f4_rtc.c index 246622ccc8..96a62fc637 100644 --- a/bsp/stm32f40x/drivers/stm32f4_rtc.c +++ b/bsp/stm32f40x/drivers/stm32f4_rtc.c @@ -1,11 +1,7 @@ /* - * File : stm32f4_rtc.c - * This file is stm32f4 rtc driver part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f40x/drivers/stm32f4_rtc.h b/bsp/stm32f40x/drivers/stm32f4_rtc.h index 42fa4ebed7..0fb2a4694c 100644 --- a/bsp/stm32f40x/drivers/stm32f4_rtc.h +++ b/bsp/stm32f40x/drivers/stm32f4_rtc.h @@ -1,11 +1,7 @@ /* - * File : stm32f4_rtc.h - * This file is stm32f4 rtc driver part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f40x/drivers/stm32f4xx_conf.h b/bsp/stm32f40x/drivers/stm32f4xx_conf.h index 065e72e94f..cc94ecdc12 100644 --- a/bsp/stm32f40x/drivers/stm32f4xx_conf.h +++ b/bsp/stm32f40x/drivers/stm32f4xx_conf.h @@ -69,7 +69,6 @@ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ -#define USE_FULL_ASSERT 1 /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT diff --git a/bsp/stm32f40x/drivers/usart.c b/bsp/stm32f40x/drivers/usart.c index 03d8c23235..0633c82cdd 100644 --- a/bsp/stm32f40x/drivers/usart.c +++ b/bsp/stm32f40x/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f40x/drivers/usart.h b/bsp/stm32f40x/drivers/usart.h index 3faf85fcde..12cfd253cf 100644 --- a/bsp/stm32f40x/drivers/usart.h +++ b/bsp/stm32f40x/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f40x/project.uvproj b/bsp/stm32f40x/project.uvproj index 81d13c4eab..cedaa18f20 100644 --- a/bsp/stm32f40x/project.uvproj +++ b/bsp/stm32f40x/project.uvproj @@ -1,36 +1,42 @@ + 1.1 +
### uVision Project, (C) Keil Software
+ rt-thread_stm32f4xx 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32F407VG STMicroelectronics IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 - + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) 6103 stm32f4xx.h - - - - - - - - - + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 0 - - - + + + ST\STM32F4xx\ ST\STM32F4xx\ @@ -54,29 +60,35 @@ 0 0 - - + + 0 0 + 0 + 0 0 0 - - + + 0 0 + 0 + 0 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 + 0 + 0 0 - + 0 @@ -90,8 +102,9 @@ 0 0 3 - - + + + 1 SARMCM3.DLL @@ -121,6 +134,7 @@ 1 1 0 + 1 1 @@ -131,22 +145,24 @@ 1 0 1 + 0 + 1 0 - 8 + -1 - - - - - + + + + + - - - - - + + + + + STLink\ST-LINKIII-KEIL.dll @@ -159,9 +175,14 @@ 1 4100 + 0 STLink\ST-LINKIII-KEIL.dll "" () - + + + + + 0 @@ -193,7 +214,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -208,6 +229,7 @@ 0 0 0 + 0 3 3 0 @@ -324,7 +346,7 @@ 0x10000 - + 1 @@ -339,11 +361,22 @@ 0 0 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 - + RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - - applications;.;drivers;Libraries\STM32F4xx_StdPeriph_Driver\inc;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + + applications;.;drivers;Libraries\STM32F4xx_StdPeriph_Driver\inc;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time @@ -354,11 +387,14 @@ 0 0 0 + 0 + 0 + 0 - - - - + + + + @@ -370,12 +406,13 @@ 0 0x08000000 0x20000000 - - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + @@ -384,16 +421,9 @@ Applications - application.c + main.c 1 - applications\application.c - - - - - startup.c - 1 - applications\startup.c + applications\main.c @@ -405,29 +435,16 @@ 1 drivers\board.c - - stm32f4xx_it.c 1 drivers\stm32f4xx_it.c - - usart.c 1 drivers\usart.c - - - - stm32f4xx_eth.c - 1 - drivers\stm32f4xx_eth.c - - - gpio.c 1 @@ -443,225 +460,161 @@ 1 Libraries\CMSIS\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - - misc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\misc.c - - stm32f4xx_adc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_adc.c - - stm32f4xx_can.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_can.c - - stm32f4xx_crc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c - - stm32f4xx_cryp.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp.c - - stm32f4xx_cryp_aes.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_aes.c - - stm32f4xx_cryp_des.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_des.c - - stm32f4xx_cryp_tdes.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_tdes.c - - stm32f4xx_dac.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c - - stm32f4xx_dbgmcu.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dbgmcu.c - - stm32f4xx_dcmi.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dcmi.c - - stm32f4xx_dma.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c - - stm32f4xx_exti.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c - - stm32f4xx_flash.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c - - stm32f4xx_fsmc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c - - stm32f4xx_gpio.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c - - stm32f4xx_hash.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash.c - - stm32f4xx_hash_md5.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_md5.c - - stm32f4xx_hash_sha1.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_sha1.c - - stm32f4xx_i2c.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_i2c.c - - stm32f4xx_iwdg.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_iwdg.c - - stm32f4xx_pwr.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c - - stm32f4xx_rcc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c - - stm32f4xx_rng.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rng.c - - stm32f4xx_rtc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c - - stm32f4xx_sdio.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c - - stm32f4xx_spi.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c - - stm32f4xx_syscfg.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c - - stm32f4xx_tim.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c - - stm32f4xx_usart.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c - - stm32f4xx_wwdg.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c - - startup_stm32f4xx.s 2 @@ -677,92 +630,71 @@ 1 ..\..\src\clock.c - - components.c 1 ..\..\src\components.c - - device.c 1 ..\..\src\device.c - - idle.c 1 ..\..\src\idle.c - - ipc.c 1 ..\..\src\ipc.c - - irq.c 1 ..\..\src\irq.c - - kservice.c 1 ..\..\src\kservice.c - - mem.c 1 ..\..\src\mem.c - - + + memheap.c + 1 + ..\..\src\memheap.c + mempool.c 1 ..\..\src\mempool.c - - object.c 1 ..\..\src\object.c - - scheduler.c 1 ..\..\src\scheduler.c - - signal.c 1 ..\..\src\signal.c - - thread.c 1 ..\..\src\thread.c - - timer.c 1 @@ -778,29 +710,21 @@ 1 ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\libcpu\arm\common\div0.c - - showmem.c 1 @@ -816,57 +740,41 @@ 1 ..\..\components\dfs\src\dfs.c - - dfs_file.c 1 ..\..\components\dfs\src\dfs_file.c - - dfs_fs.c 1 ..\..\components\dfs\src\dfs_fs.c - - dfs_posix.c 1 ..\..\components\dfs\src\dfs_posix.c - - poll.c 1 ..\..\components\dfs\src\poll.c - - select.c 1 ..\..\components\dfs\src\select.c - - devfs.c 1 ..\..\components\dfs\filesystems\devfs\devfs.c - - dfs_elm.c 1 ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - ff.c 1 @@ -882,50 +790,41 @@ 1 ..\..\components\drivers\misc\pin.c - - serial.c 1 ..\..\components\drivers\serial\serial.c - - completion.c 1 ..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\components\drivers\src\pipe.c - - + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 @@ -941,106 +840,76 @@ 1 ..\..\components\finsh\shell.c - - symbol.c 1 ..\..\components\finsh\symbol.c - - cmd.c 1 ..\..\components\finsh\cmd.c - - msh.c 1 ..\..\components\finsh\msh.c - - msh_cmd.c 1 ..\..\components\finsh\msh_cmd.c - - msh_file.c 1 ..\..\components\finsh\msh_file.c - - finsh_compiler.c 1 ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 @@ -1056,34 +925,31 @@ 1 ..\..\components\libc\compilers\armlibc\libc.c - - mem_std.c 1 ..\..\components\libc\compilers\armlibc\mem_std.c - - stdio.c 1 ..\..\components\libc\compilers\armlibc\stdio.c - - stubs.c 1 ..\..\components\libc\compilers\armlibc\stubs.c - - time.c 1 ..\..\components\libc\compilers\armlibc\time.c + + gmtime_r.c + 1 + ..\..\components\libc\compilers\common\gmtime_r.c + @@ -1094,85 +960,61 @@ 1 ..\..\components\libc\pthreads\mqueue.c - - pthread.c 1 ..\..\components\libc\pthreads\pthread.c - - pthread_attr.c 1 ..\..\components\libc\pthreads\pthread_attr.c - - pthread_barrier.c 1 ..\..\components\libc\pthreads\pthread_barrier.c - - pthread_cond.c 1 ..\..\components\libc\pthreads\pthread_cond.c - - pthread_mutex.c 1 ..\..\components\libc\pthreads\pthread_mutex.c - - pthread_rwlock.c 1 ..\..\components\libc\pthreads\pthread_rwlock.c - - pthread_spin.c 1 ..\..\components\libc\pthreads\pthread_spin.c - - pthread_tls.c 1 ..\..\components\libc\pthreads\pthread_tls.c - - sched.c 1 ..\..\components\libc\pthreads\sched.c - - semaphore.c 1 ..\..\components\libc\pthreads\semaphore.c - - clock_time.c 1 ..\..\components\libc\time\clock_time.c - - posix_sleep.c 1 @@ -1180,307 +1022,8 @@ - - lwIP - - - sys_arch.c - 1 - ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - - - api_lib.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - - - - api_msg.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - - - - err.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\err.c - - - - - netbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - - - - netdb.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - - - - netifapi.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - - - - sockets.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - - - - tcpip.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - - - - def.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\def.c - - - - - dns.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\dns.c - - - - - inet_chksum.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - - - init.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\init.c - - - - - ip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ip.c - - - - - memp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\memp.c - - - - - netif.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\netif.c - - - - - pbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - - - autoip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - - - dhcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - - - etharp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - - - icmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - - - igmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - - - ip4.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - - - ip4_addr.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - - - ip4_frag.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - - - - - SAL - - - sal_ipaddr.c - 1 - ..\..\components\net\sal_socket\src\sal_ipaddr.c - - - - - sal_socket.c - 1 - ..\..\components\net\sal_socket\src\sal_socket.c - - - - - net_netdb.c - 1 - ..\..\components\net\sal_socket\socket\net_netdb.c - - - - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - - - - - af_inet_lwip.c - 1 - ..\..\components\net\sal_socket\impl\af_inet_lwip.c - - - - - dfs_net.c - 1 - ..\..\components\net\sal_socket\dfs_net\dfs_net.c - - - + diff --git a/bsp/stm32f40x/project.uvprojx b/bsp/stm32f40x/project.uvprojx index 74e509d3f7..3f2b878128 100644 --- a/bsp/stm32f40x/project.uvprojx +++ b/bsp/stm32f40x/project.uvprojx @@ -10,36 +10,37 @@ rt-thread_stm32f4xx 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32F407VG STMicroelectronics - Keil.STM32F4xx_DFP.2.11.0 + Keil.STM32F4xx_DFP.2.13.0 http://www.keil.com/pack - IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) - 0 - $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - + -DSTM32F40_41xxx - $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd + $$Device:STM32F407VG$CMSIS\SVD\STM32F40x.svd 0 0 - ST\STM32F4xx\ - ST\STM32F4xx\ + + 0 0 @@ -109,7 +110,7 @@ SARMCM3.DLL - -MPU + -MPU -REMAP DCM.DLL -pCM4 SARMCM3.DLL @@ -137,7 +138,7 @@ 1 STLink\ST-LINKIII-KEIL.dll - "" () + @@ -191,7 +192,7 @@ 0 0 3 - 3 + 4 0 0 0 @@ -322,7 +323,8 @@ 0 0 0 - 1 + 0 + 0 0 1 1 @@ -335,7 +337,7 @@ RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - applications;.;drivers;Libraries\STM32F4xx_StdPeriph_Driver\inc;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + applications;.;drivers;Libraries\STM32F4xx_StdPeriph_Driver\inc;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time @@ -380,14 +382,9 @@ Applications - application.c + main.c 1 - applications\application.c - - - startup.c - 1 - applications\startup.c + applications\main.c @@ -409,11 +406,6 @@ 1 drivers\usart.c - - stm32f4xx_eth.c - 1 - drivers\stm32f4xx_eth.c - gpio.c 1 @@ -634,6 +626,11 @@ 1 ..\..\src\mem.c + + memheap.c + 1 + ..\..\src\memheap.c + mempool.c 1 @@ -774,6 +771,11 @@ 1 ..\..\components\drivers\src\pipe.c + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + ringbuffer.c 1 @@ -904,6 +906,11 @@ 1 ..\..\components\libc\compilers\armlibc\time.c + + gmtime_r.c + 1 + ..\..\components\libc\compilers\common\gmtime_r.c + @@ -977,224 +984,7 @@ - lwIP - - - sys_arch.c - 1 - ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - api_lib.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - - api_msg.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - - err.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\err.c - - - netbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - - netdb.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - - netifapi.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - - sockets.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - - tcpip.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - - def.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\def.c - - - dns.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\dns.c - - - inet_chksum.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - init.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\init.c - - - ip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ip.c - - - memp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\memp.c - - - netif.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\netif.c - - - pbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - autoip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - dhcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - etharp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - icmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - igmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - ip4.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - ip4_addr.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - ip4_frag.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - - - - - SAL - - - sal_ipaddr.c - 1 - ..\..\components\net\sal_socket\src\sal_ipaddr.c - - - sal_socket.c - 1 - ..\..\components\net\sal_socket\src\sal_socket.c - - - net_netdb.c - 1 - ..\..\components\net\sal_socket\socket\net_netdb.c - - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - - - af_inet_lwip.c - 1 - ..\..\components\net\sal_socket\impl\af_inet_lwip.c - - - dfs_net.c - 1 - ..\..\components\net\sal_socket\dfs_net\dfs_net.c - - + ::CMSIS @@ -1202,7 +992,14 @@ - + + + + + + + + diff --git a/bsp/stm32f40x/rtconfig.h b/bsp/stm32f40x/rtconfig.h index 92b95c9317..9482d19aa3 100644 --- a/bsp/stm32f40x/rtconfig.h +++ b/bsp/stm32f40x/rtconfig.h @@ -28,6 +28,7 @@ /* Memory Management */ #define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP #define RT_USING_SMALL_MEM #define RT_USING_HEAP @@ -36,7 +37,7 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_CONSOLE_DEVICE_NAME "uart1" #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -44,6 +45,9 @@ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ @@ -104,56 +108,16 @@ /* Socket abstraction layer */ -#define RT_USING_SAL - -/* protocol stack implement */ - -#define SAL_USING_LWIP -#define SAL_USING_POSIX -#define SAL_PROTO_FAMILIES_NUM 4 /* light weight TCP/IP stack */ -#define RT_USING_LWIP -#define RT_USING_LWIP202 -#define RT_LWIP_IGMP -#define RT_LWIP_ICMP -#define RT_LWIP_DNS -#define RT_LWIP_DHCP -#define IP_SOF_BROADCAST 1 -#define IP_SOF_BROADCAST_RECV 1 - -/* Static IPv4 Address */ - -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" -#define RT_LWIP_MSKADDR "255.255.255.0" -#define RT_LWIP_UDP -#define RT_LWIP_TCP -#define RT_MEMP_NUM_NETCONN 8 -#define RT_LWIP_PBUF_NUM 16 -#define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 5 -#define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8192 -#define RT_LWIP_TCP_WND 8192 -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define LWIP_NETIF_STATUS_CALLBACK 1 -#define SO_REUSE 1 -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -#define LWIP_SO_RCVBUF 1 -#define LWIP_NETIF_LOOPBACK 0 /* Modbus master and slave stack */ +/* AT commands */ + + /* VBUS(Virtual Software BUS) */ @@ -176,6 +140,9 @@ /* Wiced WiFi */ +/* IoT Cloud */ + + /* security packages */ @@ -199,6 +166,8 @@ /* sample package */ +/* samples: kernel and components samples */ + /* example package: hello */ diff --git a/bsp/stm32f40x/template.uvprojx b/bsp/stm32f40x/template.uvprojx index 367b472a68..89875ab043 100644 --- a/bsp/stm32f40x/template.uvprojx +++ b/bsp/stm32f40x/template.uvprojx @@ -1,7 +1,7 @@ - 1.1 + 2.1
### uVision Project, (C) Keil Software
@@ -10,382 +10,380 @@ rt-thread_stm32f4xx 0x4 ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 - - STM32F407VG - STMicroelectronics - Keil.STM32F4xx_DFP.2.2.0 - http://www.keil.com/pack - IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) - 0 - $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - - - - $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd - 0 - 0 - - - - ST\STM32F4xx\ - ST\STM32F4xx\ - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-stm32f4xx - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - 0 - 8 - - - - - - - - - - - - - - STLink\ST-LINKIII-KEIL.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4100 - - STLink\ST-LINKIII-KEIL.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x10000000 - 0x10000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - + + STM32F407VGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.13.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-stm32f4xx + 1 + 0 + 1 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output @H.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\stm32_rom.sct + + + + + + + + + + + + + diff --git a/bsp/stm32f411-nucleo/applications/main.c b/bsp/stm32f411-nucleo/applications/main.c index ae855a5b1e..5be09a6aa6 100644 --- a/bsp/stm32f411-nucleo/applications/main.c +++ b/bsp/stm32f411-nucleo/applications/main.c @@ -1,11 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f411-nucleo/drivers/board.c b/bsp/stm32f411-nucleo/drivers/board.c index 008d6f5a78..0504dac9e3 100644 --- a/bsp/stm32f411-nucleo/drivers/board.c +++ b/bsp/stm32f411-nucleo/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f411-nucleo/drivers/board.h b/bsp/stm32f411-nucleo/drivers/board.h index 4e23c44afe..5aceadc899 100644 --- a/bsp/stm32f411-nucleo/drivers/board.h +++ b/bsp/stm32f411-nucleo/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +19,7 @@ #define STM32_SRAM_SIZE 128 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f411-nucleo/drivers/drv_usart.h b/bsp/stm32f411-nucleo/drivers/drv_usart.h index ff08702d57..ecd3412ef8 100644 --- a/bsp/stm32f411-nucleo/drivers/drv_usart.h +++ b/bsp/stm32f411-nucleo/drivers/drv_usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f411-nucleo/settings/project.Debug.cspy.bat b/bsp/stm32f411-nucleo/settings/project.Debug.cspy.bat deleted file mode 100644 index de8c5e92a2..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.Debug.cspy.bat +++ /dev/null @@ -1,40 +0,0 @@ -@REM This batch file has been generated by the IAR Embedded Workbench -@REM C-SPY Debugger, as an aid to preparing a command line for running -@REM the cspybat command line utility using the appropriate settings. -@REM -@REM Note that this file is generated every time a new debug session -@REM is initialized, so you may want to move or rename the file before -@REM making changes. -@REM -@REM You can launch cspybat by typing the name of this batch file followed -@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). -@REM -@REM Read about available command line parameters in the C-SPY Debugging -@REM Guide. Hints about additional command line parameters that may be -@REM useful in specific cases: -@REM --download_only Downloads a code image without starting a debug -@REM session afterwards. -@REM --silent Omits the sign-on message. -@REM --timeout Limits the maximum allowed execution time. -@REM - - -@echo off - -if not "%1" == "" goto debugFile - -@echo on - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\project.Debug.general.xcl" --backend -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\project.Debug.driver.xcl" - -@echo off -goto end - -:debugFile - -@echo on - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\project.Debug.general.xcl" "--debug_file=%1" --backend -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\project.Debug.driver.xcl" - -@echo off -:end \ No newline at end of file diff --git a/bsp/stm32f411-nucleo/settings/project.Debug.driver.xcl b/bsp/stm32f411-nucleo/settings/project.Debug.driver.xcl deleted file mode 100644 index 8c090cd636..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.Debug.driver.xcl +++ /dev/null @@ -1,25 +0,0 @@ - -B - -"--endian=little" - -"--cpu=Cortex-M4" - -"--fpu=VFPv4_SP" - -"-p" - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\ST\STM32F411RE.ddf" - -"--semihosting" - -"--device=STM32F411RE" - -"--drv_interface=SWD" - -"--stlink_reset_strategy=0,0" - -"--drv_swo_clock_setup=100000000,0,2000000" - - - - diff --git a/bsp/stm32f411-nucleo/settings/project.Debug.general.xcl b/bsp/stm32f411-nucleo/settings/project.Debug.general.xcl deleted file mode 100644 index c36684fc2e..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.Debug.general.xcl +++ /dev/null @@ -1,15 +0,0 @@ -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\bin\armproc.dll" - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\bin\armstlink.dll" - -"D:\Proj_DRMP\Firmware\bsp\stm32f411RE\build\Exe\rtthread.out" - ---plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\bin\armbat.dll" - ---device_macro "C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\ST\STM32F4xx.dmac" - ---flash_loader "C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\ST\FlashSTM32F411xE.board" - - - - diff --git a/bsp/stm32f411-nucleo/settings/project.crun b/bsp/stm32f411-nucleo/settings/project.crun deleted file mode 100644 index ef39dce8f4..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.crun +++ /dev/null @@ -1,16 +0,0 @@ - - - - 1 - - - * - * - * - 0 - 1 - - - - - diff --git a/bsp/stm32f411-nucleo/settings/project.dbgdt b/bsp/stm32f411-nucleo/settings/project.dbgdt deleted file mode 100644 index ea0c96fb42..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.dbgdt +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - 300Build201199 - - - - - - 2089923959300Debug-Log - - - - - - - 312272727 - - - - - - Disassembly_I0 - - - - 50020 - - - - 20011 - 200ExpressionLocationTypeValue100150100100200ExpressionLocationTypeValue1001501001002003000ExpressionLocationTypeValue100150100154a - - - - - - - - TabID-21538-6852 - Workspace - Workspace - - - projectproject/Applicationsproject/Driversproject/EasyFlash - - - - 0TabID-17821-27432Debug LogDebug-Log0TabID-11016-9421Watch 1WATCH_1TabID-21221-12709Quick WatchQuickWatch1TabID-27788-12791DisassemblyDisassembly0TabID-13902-12847RegisterRegister00000 - - - - - - 0100000010000001 - - - - - - - iaridepm.enu1debuggergui.enu1armstlink.enu1-2-277403-2-24053131582032306561582035821700084740144-275267274104297201916158203675755-2-2992602-2-2267274104297201916235938732498-26009921584600-2267274104297201916384375732498-2-22722562-2-225642741001562201916104297201916 - - - - diff --git a/bsp/stm32f411-nucleo/settings/project.dni b/bsp/stm32f411-nucleo/settings/project.dni deleted file mode 100644 index 31d6f30e4f..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.dni +++ /dev/null @@ -1,107 +0,0 @@ -[DebugChecksum] -Checksum=415057771 -[CodeCoverage] -Enabled=_ 0 -[Stack] -FillEnabled=0 -OverflowWarningsEnabled=1 -WarningThreshold=90 -SpWarningsEnabled=1 -WarnLogOnly=1 -UseTrigger=1 -TriggerName=main -LimitSize=0 -ByteLimit=50 -[Exceptions] -StopOnUncaught=_ 0 -StopOnThrow=_ 0 -[CallStack] -ShowArgs=0 -[Disassembly] -MixedMode=1 -[Interrupts] -Enabled=1 -[MemConfig] -Base=1 -Manual=0 -Ddf=1 -TypeViol=0 -Stop=1 -[Trace1] -Enabled=0 -ShowSource=1 -[Simulator] -Freq=10000000 -MultiCoreRunAll=1 -[stlink] -stlinkserialNo=A4D3112E -stlinkfoundProbes= -[SWOTraceHWSettings] -OverrideDefaultClocks=0 -CpuClock=100000000 -ClockAutoDetect=0 -ClockWanted=2000000 -JtagSpeed=2000000 -Prescaler=50 -TimeStampPrescIndex=0 -TimeStampPrescData=0 -PcSampCYCTAP=1 -PcSampPOSTCNT=15 -PcSampIndex=0 -DataLogMode=0 -ITMportsEnable=0 -ITMportsTermIO=0 -ITMportsLogFile=0 -ITMlogFile=$PROJ_DIR$\ITM.log -[Trace2] -Enabled=0 -ShowSource=0 -[SWOTraceWindow] -PcSampling=0 -InterruptLogs=0 -ForcedTimeStamps=0 -EventCPI=0 -EventEXC=0 -EventFOLD=0 -EventLSU=0 -EventSLEEP=0 -[DataLog] -LogEnabled=0 -GraphEnabled=0 -ShowTimeLog=1 -SumEnabled=0 -ShowTimeSum=1 -[InterruptLog] -LogEnabled=0 -GraphEnabled=0 -ShowTimeLog=1 -SumEnabled=0 -ShowTimeSum=1 -SumSortOrder=0 -[Disassemble mode] -mode=0 -[Breakpoints2] -Count=0 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Aliases] -A0=_ "D:\Proj_DRMP\Firmware_411RET6\include\rtservice.h" "" -A1=_ "D:\Proj_DRMP\Firmware_411RET6\src\components.c" "D:\Proj_DRMP\Firmware\src\components.c" -A2=_ "D:\Proj_DRMP\Firmware_411RET6\src\idle.c" "" -Count=3 -SuppressDialog=1 -[DriverProfiling] -Enabled=0 -Mode=3 -Graph=0 -Symbiont=0 -Exclusions= -[CallStackLog] -Enabled=0 -[CallStackStripe] -ShowTiming=1 diff --git a/bsp/stm32f411-nucleo/settings/project.wsdt b/bsp/stm32f411-nucleo/settings/project.wsdt deleted file mode 100644 index 712cbcf306..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.wsdt +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - project/Debug - - - - - - - - - 613272727 - - - - - - - 2089923959 - - - - - - - - - TabID-3701-6777 - Workspace - Workspace - - - projectproject/Applications - - - - 0 - - - TabID-13926-6790 - Build - Build - - - - - 0 - - - - - - TextEditor$WS_DIR$\..\..\src\idle.c0000017158065806TextEditor$WS_DIR$\applications\main.c0000007707701TextEditor$WS_DIR$\..\..\src\kservice.c000001084000100000010000001 - - - - - - - iaridepm.enu1debuggergui.enu1armstlink.enu1-2-2841687-2-217523968359176124269141621223-2-24712562-2-22564473100156234856368359176124 - - - - diff --git a/bsp/stm32f411-nucleo/settings/project.wspos b/bsp/stm32f411-nucleo/settings/project.wspos deleted file mode 100644 index 5a1bc89077..0000000000 --- a/bsp/stm32f411-nucleo/settings/project.wspos +++ /dev/null @@ -1,2 +0,0 @@ -[MainWindow] -WindowPlacement=_ 640 230 1920 1170 3 diff --git a/bsp/stm32f411-nucleo/settings/template.Debug.cspy.bat b/bsp/stm32f411-nucleo/settings/template.Debug.cspy.bat deleted file mode 100644 index 723524598d..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.Debug.cspy.bat +++ /dev/null @@ -1,40 +0,0 @@ -@REM This batch file has been generated by the IAR Embedded Workbench -@REM C-SPY Debugger, as an aid to preparing a command line for running -@REM the cspybat command line utility using the appropriate settings. -@REM -@REM Note that this file is generated every time a new debug session -@REM is initialized, so you may want to move or rename the file before -@REM making changes. -@REM -@REM You can launch cspybat by typing the name of this batch file followed -@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). -@REM -@REM Read about available command line parameters in the C-SPY Debugging -@REM Guide. Hints about additional command line parameters that may be -@REM useful in specific cases: -@REM --download_only Downloads a code image without starting a debug -@REM session afterwards. -@REM --silent Omits the sign-on message. -@REM --timeout Limits the maximum allowed execution time. -@REM - - -@echo off - -if not "%1" == "" goto debugFile - -@echo on - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\template.Debug.general.xcl" --backend -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\template.Debug.driver.xcl" - -@echo off -goto end - -:debugFile - -@echo on - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\template.Debug.general.xcl" "--debug_file=%1" --backend -f "D:\Proj_DRMP\Firmware\bsp\stm32f411RE\settings\template.Debug.driver.xcl" - -@echo off -:end \ No newline at end of file diff --git a/bsp/stm32f411-nucleo/settings/template.Debug.driver.xcl b/bsp/stm32f411-nucleo/settings/template.Debug.driver.xcl deleted file mode 100644 index 8c090cd636..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.Debug.driver.xcl +++ /dev/null @@ -1,25 +0,0 @@ - -B - -"--endian=little" - -"--cpu=Cortex-M4" - -"--fpu=VFPv4_SP" - -"-p" - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\ST\STM32F411RE.ddf" - -"--semihosting" - -"--device=STM32F411RE" - -"--drv_interface=SWD" - -"--stlink_reset_strategy=0,0" - -"--drv_swo_clock_setup=100000000,0,2000000" - - - - diff --git a/bsp/stm32f411-nucleo/settings/template.Debug.general.xcl b/bsp/stm32f411-nucleo/settings/template.Debug.general.xcl deleted file mode 100644 index bf9eb40c90..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.Debug.general.xcl +++ /dev/null @@ -1,13 +0,0 @@ -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\bin\armproc.dll" - -"C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\bin\armstlink.dll" - -"D:\Proj_DRMP\Firmware\bsp\stm32f411RE\build\Exe\rtthread.out" - ---plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\bin\armbat.dll" - ---device_macro "C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\ST\STM32F4xx.dmac" - - - - diff --git a/bsp/stm32f411-nucleo/settings/template.crun b/bsp/stm32f411-nucleo/settings/template.crun deleted file mode 100644 index ef39dce8f4..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.crun +++ /dev/null @@ -1,16 +0,0 @@ - - - - 1 - - - * - * - * - 0 - 1 - - - - - diff --git a/bsp/stm32f411-nucleo/settings/template.dbgdt b/bsp/stm32f411-nucleo/settings/template.dbgdt deleted file mode 100644 index e068f91d1e..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.dbgdt +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/bsp/stm32f411-nucleo/settings/template.dni b/bsp/stm32f411-nucleo/settings/template.dni deleted file mode 100644 index c809ec9fc1..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.dni +++ /dev/null @@ -1,44 +0,0 @@ -[InterruptLog] -LogEnabled=0 -GraphEnabled=0 -ShowTimeLog=1 -SumEnabled=0 -ShowTimeSum=1 -SumSortOrder=0 -[DataLog] -LogEnabled=0 -GraphEnabled=0 -ShowTimeLog=1 -SumEnabled=0 -ShowTimeSum=1 -[Stack] -FillEnabled=0 -OverflowWarningsEnabled=1 -WarningThreshold=90 -SpWarningsEnabled=1 -WarnLogOnly=1 -UseTrigger=1 -TriggerName=main -LimitSize=0 -ByteLimit=50 -[Interrupts] -Enabled=1 -[MemConfig] -Base=1 -Manual=0 -Ddf=1 -TypeViol=0 -Stop=1 -[Trace1] -Enabled=0 -ShowSource=1 -[Simulator] -Freq=10000000 -MultiCoreRunAll=1 -[Disassemble mode] -mode=0 -[Breakpoints2] -Count=0 -[Aliases] -Count=0 -SuppressDialog=0 diff --git a/bsp/stm32f411-nucleo/settings/template.wsdt b/bsp/stm32f411-nucleo/settings/template.wsdt deleted file mode 100644 index 9a1efee9c5..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.wsdt +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - template/Debug - - - - - - - - - 124272727 - - - - - - - - TabID-23566-6405 - Workspace - Workspace - - - - - - - 0 - - - - - - 0100000010000001 - - - - - - - iaridepm.enu1-2-2836198-2-2200203158228230420158228951192 - - - - diff --git a/bsp/stm32f411-nucleo/settings/template.wspos b/bsp/stm32f411-nucleo/settings/template.wspos deleted file mode 100644 index 86ce159df4..0000000000 --- a/bsp/stm32f411-nucleo/settings/template.wspos +++ /dev/null @@ -1,2 +0,0 @@ -[MainWindow] -WindowPlacement=_ 640 230 1920 1170 1 diff --git a/bsp/stm32f411-nucleo/template.emProject b/bsp/stm32f411-nucleo/template.emProject new file mode 100644 index 0000000000..cbbf266c65 --- /dev/null +++ b/bsp/stm32f411-nucleo/template.emProject @@ -0,0 +1,45 @@ + + + + + + + + + diff --git a/bsp/stm32f429-apollo/applications/application.c b/bsp/stm32f429-apollo/applications/application.c index 8d1f447ef6..8846e98a5e 100644 --- a/bsp/stm32f429-apollo/applications/application.c +++ b/bsp/stm32f429-apollo/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/applications/rtgui_demo.c b/bsp/stm32f429-apollo/applications/rtgui_demo.c index 9d6d34dafa..7db3945ef4 100644 --- a/bsp/stm32f429-apollo/applications/rtgui_demo.c +++ b/bsp/stm32f429-apollo/applications/rtgui_demo.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/applications/rtgui_demo.h b/bsp/stm32f429-apollo/applications/rtgui_demo.h index e27f7b5609..1662a4d346 100644 --- a/bsp/stm32f429-apollo/applications/rtgui_demo.h +++ b/bsp/stm32f429-apollo/applications/rtgui_demo.h @@ -1,11 +1,7 @@ /* - * File : dc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/applications/startup.c b/bsp/stm32f429-apollo/applications/startup.c index 9e55b3bc40..5448f3f854 100644 --- a/bsp/stm32f429-apollo/applications/startup.c +++ b/bsp/stm32f429-apollo/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/Kconfig b/bsp/stm32f429-apollo/drivers/Kconfig index f9691bbe45..39addd5bcd 100644 --- a/bsp/stm32f429-apollo/drivers/Kconfig +++ b/bsp/stm32f429-apollo/drivers/Kconfig @@ -18,6 +18,11 @@ config RT_USING_SPI5 bool "Enable SPI5" default y +config RT_USING_SAI_AUDIO + select RT_USING_AUDIO + bool "Enable AUDIO" + default n + config RT_RTC_NAME string "The name of RTC device" default rtc diff --git a/bsp/stm32f429-apollo/drivers/SConscript b/bsp/stm32f429-apollo/drivers/SConscript index 3c05f05d71..c8ba0bed2b 100644 --- a/bsp/stm32f429-apollo/drivers/SConscript +++ b/bsp/stm32f429-apollo/drivers/SConscript @@ -2,8 +2,12 @@ from building import * cwd = GetCurrentDir() +# init src and inc vars +src = [] +inc = [] + # add the general drivers. -src = Split(""" +src += Split(""" board.c stm32f4xx_it.c usart.c @@ -12,6 +16,9 @@ drv_rtc.c drv_mpu.c """) +# add dwin basic include +inc += [cwd] + # add sdio driver if GetDepend('RT_USING_DFS'): src += ['drv_sdio_sd.c'] @@ -39,12 +46,15 @@ if GetDepend('RT_USING_SPI'): if GetDepend('RT_USING_SFUD'): src += ['drv_spi_flash.c'] +# add audio drivers. +if GetDepend('RT_USING_SAI_AUDIO'): + src += Glob('./audio/*.c') + inc += [cwd + "/audio"] + # add lcd drivers. if GetDepend('PKG_USING_GUIENGINE'): src += ['drv_lcd.c'] - -CPPPATH = [cwd] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = inc) Return('group') diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_audio.h b/bsp/stm32f429-apollo/drivers/audio/drv_audio.h new file mode 100644 index 0000000000..e04a897a55 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_audio.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#ifndef __DRV_AUDIO_H__ +#define __DRV_AUDIO_H__ + +#include +#include +#include + +/* SAIA DMA Stream TX definitions */ +#define SAIA_TX_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE() +#define SAIA_TX_DMAx_CLK_DISABLE() __HAL_RCC_DMA2_CLK_DISABLE() +#define SAIA_TX_DMAx_STREAM DMA2_Stream3 +#define SAIA_TX_DMAx_CHANNEL DMA_CHANNEL_0 +#define SAIA_TX_DMAx_IRQ DMA2_Stream3_IRQn +#define SAIA_TX_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD +#define SAIA_TX_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD +#define SAIA_TX_DMAx_IRQHandler DMA2_Stream3_IRQHandler + +/* SAIB DMA Stream TX definitions */ +#define SAIA_RX_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE() +#define SAIA_RX_DMAx_CLK_DISABLE() __HAL_RCC_DMA2_CLK_DISABLE() +#define SAIA_RX_DMAx_STREAM DMA2_Stream5 +#define SAIA_RX_DMAx_CHANNEL DMA_CHANNEL_0 +#define SAIA_RX_DMAx_IRQ DMA2_Stream5_IRQn +#define SAIA_RX_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD +#define SAIA_RX_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD +#define SAIA_RX_DMAx_IRQHandler DMA2_Stream5_IRQHandler + +int SAIA_SampleRate_Set(uint32_t samplerate); +int rt_hw_audio_init(char *i2c_bus_name); + +#endif diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_mic.c b/bsp/stm32f429-apollo/drivers/audio/drv_mic.c new file mode 100644 index 0000000000..873f37e9b7 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_mic.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#include +#include +#include + +#include + +#include "drv_audio.h" +#include "drv_wm8978.h" +#include + +#define DBG_ENABLE +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#define DBG_SECTION_NAME "MIC" +#include + +struct micphone_device +{ + struct rt_device parent; + rt_uint16_t *recv_fifo; + struct rt_audio_pipe record_pipe; + + /* i2c mode */ + struct rt_i2c_bus_device *i2c_device; +}; + +#define AUDIO_RECV_BUFFER_SIZE (2048) + +extern SAI_HandleTypeDef SAI1B_Handler; +extern DMA_HandleTypeDef SAI1_RXDMA_Handler; +extern SAI_HandleTypeDef SAI1A_Handler; +extern DMA_HandleTypeDef SAI1_TXDMA_Handler; + +static struct micphone_device micphone; +static uint16_t send_fifo[2] = {0, 0}; + +static void SAIB_Init(void) +{ + HAL_SAI_DeInit(&SAI1B_Handler); + SAI1B_Handler.Instance = SAI1_Block_B; + SAI1B_Handler.Init.AudioMode = SAI_MODESLAVE_RX; + SAI1B_Handler.Init.Synchro = SAI_SYNCHRONOUS; + SAI1B_Handler.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + SAI1B_Handler.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + SAI1B_Handler.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; + SAI1B_Handler.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; + SAI1B_Handler.Init.MonoStereoMode = SAI_MONOMODE; + SAI1B_Handler.Init.Protocol = SAI_FREE_PROTOCOL; + SAI1B_Handler.Init.DataSize = SAI_DATASIZE_16; + SAI1B_Handler.Init.FirstBit = SAI_FIRSTBIT_MSB; + SAI1B_Handler.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + SAI1B_Handler.FrameInit.FrameLength = 64; + SAI1B_Handler.FrameInit.ActiveFrameLength = 32; + SAI1B_Handler.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + SAI1B_Handler.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + SAI1B_Handler.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + SAI1B_Handler.SlotInit.FirstBitOffset = 0; + SAI1B_Handler.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + SAI1B_Handler.SlotInit.SlotNumber = 2; + SAI1B_Handler.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + HAL_SAI_Init(&SAI1B_Handler); + __HAL_SAI_ENABLE(&SAI1B_Handler); + + SAIA_RX_DMAx_CLK_ENABLE(); + __HAL_LINKDMA(&SAI1B_Handler, hdmarx, SAI1_RXDMA_Handler); + SAI1_RXDMA_Handler.Instance = SAIA_RX_DMAx_STREAM; + SAI1_RXDMA_Handler.Init.Channel = SAIA_RX_DMAx_CHANNEL; + SAI1_RXDMA_Handler.Init.Direction = DMA_PERIPH_TO_MEMORY; + SAI1_RXDMA_Handler.Init.PeriphInc = DMA_PINC_DISABLE; + SAI1_RXDMA_Handler.Init.MemInc = DMA_MINC_ENABLE; + SAI1_RXDMA_Handler.Init.PeriphDataAlignment = SAIA_RX_DMAx_PERIPH_DATA_SIZE; + SAI1_RXDMA_Handler.Init.MemDataAlignment = SAIA_RX_DMAx_MEM_DATA_SIZE; + SAI1_RXDMA_Handler.Init.Mode = DMA_CIRCULAR; + SAI1_RXDMA_Handler.Init.Priority = DMA_PRIORITY_MEDIUM; + SAI1_RXDMA_Handler.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + SAI1_RXDMA_Handler.Init.MemBurst = DMA_MBURST_SINGLE; + SAI1_RXDMA_Handler.Init.PeriphBurst = DMA_PBURST_SINGLE; + HAL_DMA_DeInit(&SAI1_RXDMA_Handler); + HAL_DMA_Init(&SAI1_RXDMA_Handler); + + HAL_NVIC_SetPriority(SAIA_RX_DMAx_IRQ, 0, 1); + HAL_NVIC_EnableIRQ(SAIA_RX_DMAx_IRQ); +} + +void SAIA_RX_DMAx_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&SAI1_RXDMA_Handler); +} + +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &SAI1B_Handler) + { + rt_device_write(&micphone.record_pipe.parent, 0, micphone.recv_fifo, AUDIO_RECV_BUFFER_SIZE / 2); + } +} + +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &SAI1B_Handler) + { + rt_device_write(&micphone.record_pipe.parent, 0, micphone.recv_fifo + (AUDIO_RECV_BUFFER_SIZE / 4), AUDIO_RECV_BUFFER_SIZE / 2); + } +} + +static rt_err_t micphone_init(rt_device_t dev) +{ + SAIB_Init(); + + return RT_EOK; +} + +static rt_err_t micphone_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct micphone_device *mic = RT_NULL; + + mic = (struct micphone_device *)dev; + + if (oflag & RT_DEVICE_OFLAG_RDONLY) + { + LOG_I("Open Micphone Device!"); + + rt_device_open(&mic->record_pipe.parent, RT_DEVICE_OFLAG_RDONLY); + /* Disable DMA Interruption */ + __HAL_DMA_DISABLE_IT(&SAI1_TXDMA_Handler, DMA_IT_TC | DMA_IT_HT); + HAL_DMA_Start(&SAI1_TXDMA_Handler, (uint32_t)&send_fifo[0], (uint32_t)&SAI1_Block_A->DR, 2); + /* Start RX DMA */ + HAL_SAI_Receive_DMA(&SAI1B_Handler, (uint8_t *)(micphone.recv_fifo), AUDIO_RECV_BUFFER_SIZE / 2); + } + + return RT_EOK; +} + +static rt_size_t micphone_read(rt_device_t dev, rt_off_t pos, + void *buffer, rt_size_t size) +{ + struct micphone_device *mic = RT_NULL; + + mic = (struct micphone_device *)dev; + return rt_device_read(&mic->record_pipe.parent, pos, buffer, size); +} + +static rt_err_t micphone_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t value, result = RT_EOK; + + switch (cmd) + { + case CODEC_CMD_SET_VOLUME: + { + // TODO + break; + } + + case CODEC_CMD_SAMPLERATE: + { + value = *(int *)args; + LOG_I("Set Samplerate %d", value); + result = SAIA_SampleRate_Set(value); + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t micphone_close(rt_device_t dev) +{ + struct micphone_device *mic = RT_NULL; + + mic = (struct micphone_device *)dev; + HAL_SAI_DMAStop(&SAI1A_Handler); + HAL_SAI_DMAStop(&SAI1B_Handler); + rt_device_close(&mic->record_pipe.parent); + LOG_I("Close Micphone Device!"); + + return RT_EOK; +} + +int rt_hw_micphone_init(char *i2c_bus_name) +{ + int result = RT_EOK; + struct micphone_device *mic = &micphone; + + if (mic->recv_fifo != RT_NULL) + { + return RT_EOK; + } + + mic->recv_fifo = rt_malloc(AUDIO_RECV_BUFFER_SIZE); + if (mic->recv_fifo == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(mic->recv_fifo, 0, AUDIO_RECV_BUFFER_SIZE); + + mic->parent.type = RT_Device_Class_Sound; + mic->parent.init = micphone_init; + mic->parent.open = micphone_open; + mic->parent.control = micphone_control; + mic->parent.write = RT_NULL; + mic->parent.read = micphone_read; + mic->parent.close = micphone_close; + mic->parent.user_data = mic; + + /* register the device */ + rt_device_register(&mic->parent, "mic", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_DMA_RX); + + rt_device_init(&mic->parent); + + { + rt_uint8_t *buffer = rt_malloc(AUDIO_RECV_BUFFER_SIZE); + if (buffer == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(buffer, 0, AUDIO_RECV_BUFFER_SIZE); + + rt_audio_pipe_init(&mic->record_pipe, + "voice", + RT_PIPE_FLAG_FORCE_WR | RT_PIPE_FLAG_BLOCK_RD, + buffer, + AUDIO_RECV_BUFFER_SIZE); + } + + return RT_EOK; + +__exit: + if (mic->recv_fifo) + { + rt_free(mic->recv_fifo); + mic->recv_fifo = RT_NULL; + } + + return result; +} diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_sound.c b/bsp/stm32f429-apollo/drivers/audio/drv_sound.c new file mode 100644 index 0000000000..43bbadf412 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_sound.c @@ -0,0 +1,594 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#include +#include +#include + +#include +#include + +#include "drv_audio.h" +#include "drv_wm8978.h" +#include + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#define DBG_SECTION_NAME "Sound" +#include + +/** + * Audio Memory Node Manage + */ +struct rt_data_node +{ + char *data_ptr; + rt_uint32_t data_size; +}; + +struct rt_data_node_list +{ + struct rt_data_node *node; + rt_uint32_t size; + rt_uint32_t read_index, write_index; + rt_uint32_t data_offset; + void (*read_complete)(struct rt_data_node *node, void *user_data); + void *user_data; +}; + +int rt_data_node_init(struct rt_data_node_list **node_list, rt_uint32_t size) +{ + int result = RT_EOK; + struct rt_data_node_list *list = RT_NULL; + struct rt_data_node *node = RT_NULL; + + list = rt_malloc(sizeof(struct rt_data_node_list)); + if (list == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(list, 0, sizeof(struct rt_data_node_list)); + + node = rt_malloc(sizeof(struct rt_data_node) * size); + if (size == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(node, 0, sizeof(struct rt_data_node)); + + list->node = node; + list->size = size; + list->read_index = 0; + list->write_index = 0; + list->data_offset = 0; + list->read_complete = RT_NULL; + list->user_data = 0; + + *node_list = list; + + return result; + +__exit: + if (list) + rt_free(list); + + if (node) + rt_free(node); + + return result; +} + +int rt_data_node_is_empty(struct rt_data_node_list *node_list) +{ + rt_uint32_t read_index, write_index; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + if (read_index == write_index) + { + return RT_TRUE; + } + else + { + return RT_FALSE; + } +} + +void wait_node_free(struct rt_data_node_list *node_list) +{ + while (node_list->read_index != node_list->write_index) + rt_thread_mdelay(5); +} + +int rt_data_node_write(struct rt_data_node_list *node_list, void *buffer, rt_uint32_t size) +{ + struct rt_data_node *node = RT_NULL; + rt_uint32_t read_index, write_index, next_index; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + next_index = write_index + 1; + if (next_index >= node_list->size) + next_index = 0; + + if (next_index == read_index) + { + rt_kprintf("[node]:node list full, write index = %d, read index = %d \n", write_index, read_index); + return -RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + /* set node attribute */ + node = &node_list->node[write_index]; + node->data_ptr = (char *) buffer; + node->data_size = size; + node_list->write_index = next_index; + rt_hw_interrupt_enable(level); + + return size; +} + +int rt_data_node_read(struct rt_data_node_list *node_list, void *buffer, rt_uint32_t size) +{ + struct rt_data_node *node = RT_NULL; + rt_uint32_t read_index, write_index, next_index; + rt_int32_t remain_len, copy_size; + rt_uint32_t read_offset, data_offset; + rt_base_t level; + rt_uint32_t result = size; + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + read_offset = 0; + if (read_index == write_index) + { + result = 0; + } + else + { + do + { + node = &node_list->node[node_list->read_index]; + data_offset = node_list->data_offset; + remain_len = node->data_size - data_offset; + if (size - read_offset > remain_len) + { + /* Full*/ + copy_size = remain_len; + } + else + { + /* reamain buffer */ + copy_size = size - read_offset; + } + + memcpy((char *)buffer + read_offset, node->data_ptr + data_offset, copy_size); + read_offset += copy_size; + data_offset += copy_size; + node_list->data_offset = data_offset; + + if (data_offset >= node->data_size) + { + /* notify transmitted complete. */ + if (node_list->read_complete != RT_NULL) + { + node_list->read_complete(node, node_list->user_data); + } + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + next_index = read_index + 1; + if (next_index >= node_list->size) + next_index = 0; + + level = rt_hw_interrupt_disable(); + node_list->read_index = next_index; + node_list->data_offset = 0; + rt_hw_interrupt_enable(level); + + if (next_index == write_index) + { + result = read_offset; + break; + } + } + } + while (read_offset < size); + } + + return result; +} + +static void data_node_read_complete(struct rt_data_node *node, void *user_data) +{ + struct rt_device *dev = RT_NULL; + + dev = (struct rt_device *)user_data; + if (dev->tx_complete != RT_NULL) + { + dev->tx_complete(dev, node->data_ptr); + } +} + +/** + * RT-Thread Audio Device Driver + */ +struct sound_device +{ + struct rt_device parent; + struct rt_data_node_list *node_list; + + /* i2c mode */ + struct rt_i2c_bus_device *i2c_device; + + char *send_fifo; +}; + +#define AUDIO_SEND_BUFFER_SIZE (2048 * 2) + +SAI_HandleTypeDef SAI1B_Handler; +DMA_HandleTypeDef SAI1_RXDMA_Handler; +SAI_HandleTypeDef SAI1A_Handler; +DMA_HandleTypeDef SAI1_TXDMA_Handler; + +static struct sound_device *sound; + +static void SAIA_Init(void) +{ + HAL_SAI_DeInit(&SAI1A_Handler); + // SAI1A_Handler.Init.AudioFrequency = 44100; + SAI1A_Handler.Instance = SAI1_Block_A; + SAI1A_Handler.Init.AudioMode = SAI_MODEMASTER_TX; + SAI1A_Handler.Init.Synchro = SAI_ASYNCHRONOUS; + SAI1A_Handler.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + SAI1A_Handler.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + SAI1A_Handler.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + SAI1A_Handler.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; + SAI1A_Handler.Init.MonoStereoMode = SAI_STEREOMODE; + SAI1A_Handler.Init.Protocol = SAI_FREE_PROTOCOL; + SAI1A_Handler.Init.DataSize = SAI_DATASIZE_16; + SAI1A_Handler.Init.FirstBit = SAI_FIRSTBIT_MSB; + SAI1A_Handler.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + SAI1A_Handler.FrameInit.FrameLength = 64; + SAI1A_Handler.FrameInit.ActiveFrameLength = 32; + SAI1A_Handler.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + SAI1A_Handler.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + SAI1A_Handler.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + SAI1A_Handler.SlotInit.FirstBitOffset = 0; + SAI1A_Handler.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + SAI1A_Handler.SlotInit.SlotNumber = 2; + SAI1A_Handler.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + HAL_SAI_Init(&SAI1A_Handler); + __HAL_SAI_ENABLE(&SAI1A_Handler); + + /* DMA Configuration */ + SAIA_TX_DMAx_CLK_ENABLE(); + __HAL_LINKDMA(&SAI1A_Handler, hdmatx, SAI1_TXDMA_Handler); + SAI1_TXDMA_Handler.Instance = SAIA_TX_DMAx_STREAM; + SAI1_TXDMA_Handler.Init.Channel = SAIA_TX_DMAx_CHANNEL; + SAI1_TXDMA_Handler.Init.Direction = DMA_MEMORY_TO_PERIPH; + SAI1_TXDMA_Handler.Init.PeriphInc = DMA_PINC_DISABLE; + SAI1_TXDMA_Handler.Init.MemInc = DMA_MINC_ENABLE; + SAI1_TXDMA_Handler.Init.PeriphDataAlignment = SAIA_TX_DMAx_PERIPH_DATA_SIZE; + SAI1_TXDMA_Handler.Init.MemDataAlignment = SAIA_TX_DMAx_MEM_DATA_SIZE; + SAI1_TXDMA_Handler.Init.Mode = DMA_CIRCULAR; + SAI1_TXDMA_Handler.Init.Priority = DMA_PRIORITY_HIGH; + SAI1_TXDMA_Handler.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + SAI1_TXDMA_Handler.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; + SAI1_TXDMA_Handler.Init.MemBurst = DMA_MBURST_SINGLE; + SAI1_TXDMA_Handler.Init.PeriphBurst = DMA_PBURST_SINGLE; + HAL_DMA_DeInit(&SAI1_TXDMA_Handler); + HAL_DMA_Init(&SAI1_TXDMA_Handler); + + HAL_NVIC_SetPriority(SAIA_TX_DMAx_IRQ, 0, 0); + HAL_NVIC_EnableIRQ(SAIA_TX_DMAx_IRQ); +} + +const uint16_t SAI_PSC_TBL[][5] = +{ + {800, 344, 7, 0, 12}, + {1102, 429, 2, 18, 2}, + {1600, 344, 7, 0, 6}, + {2205, 429, 2, 18, 1}, + {3200, 344, 7, 0, 3}, + {4410, 429, 2, 18, 0}, + {4800, 344, 7, 0, 2}, + {8820, 271, 2, 2, 1}, + {9600, 344, 7, 0, 1}, + {17640, 271, 2, 2, 0}, + {19200, 344, 7, 0, 0}, +}; + +void SAIA_DMA_Enable(void) +{ + SAI1_Block_A->CR1 |= SAI_xCR1_DMAEN; +} + +void SAIA_DMA_Disable(void) +{ + SAI1_Block_A->CR1 &= ~SAI_xCR1_DMAEN; +} + +int SAIA_SampleRate_Set(uint32_t samplerate) +{ + uint16_t i = 0; + + RCC_PeriphCLKInitTypeDef RCCSAI1_Sture; + for (i = 0; i < (sizeof(SAI_PSC_TBL) / 10); i++) + { + if ((samplerate / 10) == SAI_PSC_TBL[i][0]) + break; + } + if (i == (sizeof(SAI_PSC_TBL) / 10)) + return -RT_ERROR; + RCCSAI1_Sture.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S; + RCCSAI1_Sture.PLLI2S.PLLI2SN = (uint32_t)SAI_PSC_TBL[i][1]; + RCCSAI1_Sture.PLLI2S.PLLI2SQ = (uint32_t)SAI_PSC_TBL[i][2]; + RCCSAI1_Sture.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1; + HAL_RCCEx_PeriphCLKConfig(&RCCSAI1_Sture); + + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S); + + __HAL_SAI_DISABLE(&SAI1A_Handler); + SAIA_DMA_Disable(); + SAI1A_Handler.Init.AudioFrequency = samplerate; + HAL_SAI_Init(&SAI1A_Handler); + SAIA_DMA_Enable(); + __HAL_SAI_ENABLE(&SAI1A_Handler); + + return RT_EOK; +} + +void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) +{ + GPIO_InitTypeDef GPIO_Initure; + __HAL_RCC_SAI1_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + + GPIO_Initure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; + GPIO_Initure.Mode = GPIO_MODE_AF_PP; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Alternate = GPIO_AF6_SAI1; + HAL_GPIO_Init(GPIOE, &GPIO_Initure); +} + +void SAIA_TX_DMAx_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&SAI1_TXDMA_Handler); +} + +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + int result; + struct sound_device *snd = sound; + + if (hsai == &SAI1A_Handler) + { + result = rt_data_node_is_empty(snd->node_list); + if (result) + { + rt_kprintf("# "); + memset(snd->send_fifo, 0, AUDIO_SEND_BUFFER_SIZE / 2); + } + else + { + memset(snd->send_fifo, 0, AUDIO_SEND_BUFFER_SIZE / 2); + rt_data_node_read(snd->node_list, snd->send_fifo, AUDIO_SEND_BUFFER_SIZE / 2); + } + } +} + +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + int result; + struct sound_device *snd = sound; + + if (hsai == &SAI1A_Handler) + { + result = rt_data_node_is_empty(snd->node_list); + if (result) + { + rt_kprintf("* "); + memset(snd->send_fifo + (AUDIO_SEND_BUFFER_SIZE / 2), 0, AUDIO_SEND_BUFFER_SIZE / 2); + } + else + { + memset(snd->send_fifo + (AUDIO_SEND_BUFFER_SIZE / 2), 0, AUDIO_SEND_BUFFER_SIZE / 2); + rt_data_node_read(snd->node_list, snd->send_fifo + (AUDIO_SEND_BUFFER_SIZE / 2), AUDIO_SEND_BUFFER_SIZE / 2); + } + + } +} + +void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) +{ + rt_kprintf("x "); +} + + +static rt_err_t sound_init(rt_device_t dev) +{ + int result; + struct sound_device *snd = (struct sound_device *)dev; + + SAIA_Init(); + result = wm8978_init(snd->i2c_device); + + return result; +} + +static rt_err_t sound_open(rt_device_t dev, rt_uint16_t oflag) +{ + int result = RT_EOK; + struct sound_device *snd = (struct sound_device *)dev; + + LOG_I("Open Sound Device!"); + + /* Configure DMA transmit */ + result = HAL_SAI_Transmit_DMA(&SAI1A_Handler, (uint8_t *)(snd->send_fifo), AUDIO_SEND_BUFFER_SIZE / 2); + if (result != HAL_OK) + { + LOG_E("Start DMA Transmit Failed!"); + result = -RT_ERROR; + } + + return result; +} + +static rt_err_t sound_control(rt_device_t dev, int cmd, void *args) +{ + int value, result = RT_EOK; + struct sound_device *snd = (struct sound_device *)dev; + + switch (cmd) + { + case CODEC_CMD_SET_VOLUME: + value = *(int *)args; + if (value < 0 || value > 99) + { + LOG_W("Please volume level 0 ~ 99"); + result = -RT_EINVAL; + } + else + { + LOG_I("Set volume level to %d", value); + wm8978_set_volume(snd->i2c_device, value); + result = RT_EOK; + } + break; + + case CODEC_CMD_SAMPLERATE: + value = *(int *)args; + LOG_I("Set Samplerate %d", value); + SAIA_SampleRate_Set(value); + break; + + default: + result = RT_EOK; + } + return result; +} + +static rt_size_t sound_write(rt_device_t dev, rt_off_t pos, + const void *buffer, rt_size_t size) +{ + int result = RT_EOK; + struct sound_device *snd = (struct sound_device *)dev; + + result = rt_data_node_write(snd->node_list, (void *)buffer, size); + + return result; +} + +static rt_err_t sound_close(rt_device_t dev) +{ + HAL_SAI_DMAStop(&SAI1A_Handler); + LOG_I("Close Sound Device!"); + + return RT_EOK; +} + +int rt_hw_sound_hw_init(char *i2c_bus_name) +{ + int result = RT_EOK; + + if (sound != RT_NULL) + return RT_EOK; + + HAL_SAI_MspInit(NULL); + sound = rt_malloc(sizeof(struct sound_device)); + if (sound == RT_NULL) + { + LOG_E("malloc memory for sound device failed!"); + result = -RT_ENOMEM; + goto __exit; + } + memset(sound, 0, sizeof(struct sound_device)); + + sound->i2c_device = rt_i2c_bus_device_find(i2c_bus_name); + if (sound->i2c_device == RT_NULL) + { + LOG_E("i2c bus device %s not found!", i2c_bus_name); + result = -RT_ENOSYS; + goto __exit; + } + + sound->send_fifo = rt_malloc(AUDIO_SEND_BUFFER_SIZE); + if (sound->send_fifo == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(sound->send_fifo, 0, AUDIO_SEND_BUFFER_SIZE); + + rt_data_node_init(&sound->node_list, 10); + sound->node_list->read_complete = data_node_read_complete; + sound->node_list->user_data = sound; + + sound->parent.type = RT_Device_Class_Sound; + sound->parent.init = sound_init; + sound->parent.open = sound_open; + sound->parent.control = sound_control; + sound->parent.write = sound_write; + sound->parent.read = RT_NULL; + sound->parent.close = sound_close; + sound->parent.user_data = sound; + + /* register the device */ + rt_device_register(&sound->parent, "sound", RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX); + rt_device_init(&sound->parent); + + return RT_EOK; + +__exit: + if (sound->send_fifo != RT_NULL) + { + rt_free(sound->send_fifo); + sound->send_fifo = RT_NULL; + } + + if (sound != RT_NULL) + { + rt_free(sound); + sound = RT_NULL; + } + + return result; +} + +extern int rt_hw_micphone_init(char *i2c_bus_name); + +int rt_hw_audio_init(char *i2c_bus_name) +{ + rt_hw_sound_hw_init(i2c_bus_name); + rt_hw_micphone_init(i2c_bus_name); + + return RT_EOK; +} diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.c b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.c new file mode 100644 index 0000000000..196a5b2107 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.c @@ -0,0 +1,733 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#include +#include + +#include "drv_wm8978.h" + + +/* Register Definitions */ +#define REG_SOFTWARE_RESET ((uint16_t)0) +#define REG_POWER_MANAGEMENT1 ((uint16_t)(1 << 9)) +#define REG_POWER_MANAGEMENT2 ((uint16_t)(2 << 9)) +#define REG_POWER_MANAGEMENT3 ((uint16_t)(3 << 9)) +#define REG_AUDIO_INTERFACE ((uint16_t)(4 << 9)) +#define REG_COMPANDING ((uint16_t)(5 << 9)) +#define REG_CLOCK_GEN ((uint16_t)(6 << 9)) +#define REG_ADDITIONAL ((uint16_t)(7 << 9)) +#define REG_GPIO ((uint16_t)(8 << 9)) +#define REG_JACK_DETECT1 ((uint16_t)(9 << 9)) +#define REG_DAC ((uint16_t)(10 << 9)) +#define REG_LEFT_DAC_VOL ((uint16_t)(11 << 9)) +#define REG_RIGHT_DAC_VOL ((uint16_t)(12 << 9)) +#define REG_JACK_DETECT2 ((uint16_t)(13 << 9)) +#define REG_ADC ((uint16_t)(14 << 9)) +#define REG_LEFT_ADC_VOL ((uint16_t)(15 << 9)) +#define REG_RIGHT_ADC_VOL ((uint16_t)(16 << 9)) +#define REG_EQ1 ((uint16_t)(18 << 9)) +#define REG_EQ2 ((uint16_t)(19 << 9)) +#define REG_EQ3 ((uint16_t)(20 << 9)) +#define REG_EQ4 ((uint16_t)(21 << 9)) +#define REG_EQ5 ((uint16_t)(22 << 9)) +#define REG_DAC_LIMITER1 ((uint16_t)(24 << 9)) +#define REG_DAC_LIMITER2 ((uint16_t)(25 << 9)) +#define REG_NOTCH_FILTER1 ((uint16_t)(27 << 9)) +#define REG_NOTCH_FILTER2 ((uint16_t)(28 << 9)) +#define REG_NOTCH_FILTER3 ((uint16_t)(29 << 9)) +#define REG_NOTCH_FILTER4 ((uint16_t)(30 << 9)) +#define REG_ALC1 ((uint16_t)(32 << 9)) +#define REG_ALC2 ((uint16_t)(33 << 9)) +#define REG_ALC3 ((uint16_t)(34 << 9)) +#define REG_NOISE_GATE ((uint16_t)(35 << 9)) +#define REG_PLL_N ((uint16_t)(36 << 9)) +#define REG_PLL_K1 ((uint16_t)(37 << 9)) +#define REG_PLL_K2 ((uint16_t)(38 << 9)) +#define REG_PLL_K3 ((uint16_t)(39 << 9)) +#define REG_3D ((uint16_t)(41 << 9)) +#define REG_BEEP ((uint16_t)(43 << 9)) +#define REG_INPUT ((uint16_t)(44 << 9)) +#define REG_LEFT_PGA_GAIN ((uint16_t)(45 << 9)) +#define REG_RIGHT_PGA_GAIN ((uint16_t)(46 << 9)) +#define REG_LEFT_ADC_BOOST ((uint16_t)(47 << 9)) +#define REG_RIGHT_ADC_BOOST ((uint16_t)(48 << 9)) +#define REG_OUTPUT ((uint16_t)(49 << 9)) +#define REG_LEFT_MIXER ((uint16_t)(50 << 9)) +#define REG_RIGHT_MIXER ((uint16_t)(51 << 9)) +#define REG_LOUT1_VOL ((uint16_t)(52 << 9)) +#define REG_ROUT1_VOL ((uint16_t)(53 << 9)) +#define REG_LOUT2_VOL ((uint16_t)(54 << 9)) +#define REG_ROUT2_VOL ((uint16_t)(55 << 9)) +#define REG_OUT3_MIXER ((uint16_t)(56 << 9)) +#define REG_OUT4_MIXER ((uint16_t)(57 << 9)) + +// R01 REG_POWER_MANAGEMENT1 +#define BUFDCOPEN (1 << 8) +#define OUT4MIXEN (1 << 7) +#define OUT3MIXEN (1 << 6) +#define PLLEN (1 << 5) +#define MICBEN (1 << 4) +#define BIASEN (1 << 3) +#define BUFIOEN (1 << 2) +#define VMIDSEL_OFF (0) +#define VMIDSEL_75K (1) +#define VMIDSEL_300K (2) +#define VMIDSEL_5K (3) + +// R02 REG_POWER_MANAGEMENT2 +#define ROUT1EN (1 << 8) +#define LOUT1EN (1 << 7) +#define SLEEP (1 << 6) +#define BOOSTENR (1 << 5) +#define BOOSTENL (1 << 4) +#define INPPGAENR (1 << 3) +#define INPPGAENL (1 << 2) +#define ADCENR (1 << 1) +#define ADCENL (1) + +// R03 REG_POWER_MANAGEMENT3 +#define OUT4EN (1 << 8) +#define OUT3EN (1 << 7) +#define LOUT2EN (1 << 6) +#define ROUT2EN (1 << 5) +#define RMIXEN (1 << 3) +#define LMIXEN (1 << 2) +#define DACENR (1 << 1) +#define DACENL (1) + +// R04 REG_AUDIO_INTERFACE +#define BCP_NORMAL (0) +#define BCP_INVERTED (1 << 8) +#define LRP_NORMAL (0) +#define LRP_INVERTED (1 << 7) +#define WL_16BITS (0) +#define WL_20BITS (1 << 5) +#define WL_24BITS (2 << 5) // Default value +#define WL_32BITS (3 << 5) +#define FMT_RIGHT_JUSTIFIED (0) +#define FMT_LEFT_JUSTIFIED (1 << 3) +#define FMT_I2S (2 << 3) // Default value +#define FMT_PCM (3 << 3) +#define DACLRSWAP (1 << 2) +#define ADCLRSWAP (1 << 1) +#define MONO (1) + +// R05 REG_COMPANDING +#define WL8 (1 << 5) +#define DAC_COMP_OFF (0) // Default value +#define DAC_COMP_ULAW (2 << 3) +#define DAC_COMP_ALAW (3 << 3) +#define ADC_COMP_OFF (0) // Default value +#define ADC_COMP_ULAW (2 << 1) +#define ADC_COMP_ALAW (3 << 1) +#define LOOPBACK (1) + +// R06 REG_CLOCK_GEN +#define CLKSEL_MCLK (0) +#define CLKSEL_PLL (1 << 8) // Default value +#define MCLK_DIV1 (0) +#define MCLK_DIV1_5 (1 << 5) +#define MCLK_DIV2 (2 << 5) // Default value +#define MCLK_DIV3 (3 << 5) +#define MCLK_DIV4 (4 << 5) +#define MCLK_DIV6 (5 << 5) +#define MCLK_DIV8 (6 << 5) +#define MCLK_DIV12 (7 << 5) +#define BCLK_DIV1 (0) // Default value +#define BCLK_DIV2 (1 << 2) +#define BCLK_DIV4 (2 << 2) +#define BCLK_DIV8 (3 << 2) +#define BCLK_DIV16 (4 << 2) +#define BCLK_DIV32 (5 << 2) +#define MS (1) + +// R07 REG_ADDITIONAL +#define WM_SR_48KHZ (0) // Default value +#define WM_SR_32KHZ (1 << 1) +#define WM_SR_24KHZ (2 << 1) +#define WM_SR_16KHZ (3 << 1) +#define WM_SR_12KHZ (4 << 1) +#define WM_SR_8KHZ (5 << 1) +#define SLOWCLKEN (1) + +// R08 REG_GPIO +#define OPCLK_DIV1 (0) // Default value +#define OPCLK_DIV2 (1 << 4) +#define OPCLK_DIV3 (2 << 4) +#define OPCLK_DIV4 (3 << 4) +#define GPIO1POL_NONINVERTED (0) // Default value +#define GPIO1POL_INVERTED (1 << 3) +#define GPIO1SEL_INPUT (0) // Default value +#define GPIO1SEL_TEMP_OK (2) +#define GPIO1SEL_AMUTE_ACTIVE (3) +#define GPIO1SEL_PLL_CLK_OP (4) +#define GPIO1SEL_PLL_LOCK (5) +#define GPIO1SEL_LOGIC1 (6) +#define GPIO1SEL_LOGIC0 (7) + +// R09 REG_JACK_DETECT1 +#define JD_VMID_EN1 (1 << 8) +#define JD_VMID_EN0 (1 << 7) +#define JD_EN (1 << 6) +#define JD_SEL_GPIO1 (0 << 4) // Default value +#define JD_SEL_GPIO2 (1 << 4) +#define JD_SEL_GPIO3 (2 << 4) + +// R10 REG_DAC +#define SOFTMUTE (1 << 6) +#define DACOSR128 (1 << 3) +#define AMUTE (1 << 2) +#define DACPOLR (1 << 1) +#define DACPOLL (1) + +// R11 & R12 REG_LEFT_DAC_VOL & REG_RIGHT_DAC_VOL +#define DACVU (1 << 8) +#define DACVOL_POS (0) +#define DACVOL_MASK (0xFF) + +// R13 REG_JACK_DETECT2 +#define JD_OUT4_EN1 (1 << 7) +#define JD_OUT3_EN1 (1 << 6) +#define JD_OUT2_EN1 (1 << 5) +#define JD_OUT1_EN1 (1 << 4) +#define JD_OUT4_EN0 (1 << 3) +#define JD_OUT3_EN0 (1 << 2) +#define JD_OUT2_EN0 (1 << 1) +#define JD_OUT1_EN0 (1) + +// R14 REG_ADC +#define HPFEN (1 << 8) +#define HPFAPP (1 << 7) +#define HPFCUT_POS (4) +#define HPFCUT_MASK (7) +#define HPFCUT_0 (0) +#define HPFCUT_1 (1 << 4) +#define HPFCUT_2 (2 << 4) +#define HPFCUT_3 (3 << 4) +#define HPFCUT_4 (4 << 4) +#define HPFCUT_5 (5 << 4) +#define HPFCUT_6 (6 << 4) +#define HPFCUT_7 (7 << 4) +#define ADCOSR128 (1 << 3) +#define ADCRPOL (1 << 1) +#define ADCLPOL (1) + +// R15 & R16 REG_LEFT_ADC_VOL & REG_RIGHT_ADC_VOL +#define ADCVU (1 << 8) +#define ADCVOL_POS (0) +#define ADCVOL_MASK (0xFF) + +// R18 REG_EQ1 +#define EQ3DMODE_ADC (0) +#define EQ3DMODE_DAC (1 << 8) // Default value +#define EQ1C_80HZ (0) +#define EQ1C_105HZ (1 << 5) // Default value +#define EQ1C_135HZ (2 << 5) +#define EQ1C_175HZ (3 << 5) + +// R19 REG_EQ2 +#define EQ2BW_NARROW (0) // Default value +#define EQ2BW_WIDE (1 << 8) +#define EQ2C_230HZ (0) +#define EQ2C_300HZ (1 << 5) // Default value +#define EQ2C_385HZ (2 << 5) +#define EQ2C_500HZ (3 << 5) + +// R20 REG_EQ3 +#define EQ3BW_NARROW (0) // Default value +#define EQ3BW_WIDE (1 << 8) +#define EQ3C_650HZ (0) +#define EQ3C_850HZ (1 << 5) // Default value +#define EQ3C_1_1KHZ (2 << 5) +#define EQ3C_1_4KHZ (3 << 5) + +// R21 REG_EQ4 +#define EQ4BW_NARROW (0) // Default value +#define EQ4BW_WIDE (1 << 8) +#define EQ4C_1_8KHZ (0) +#define EQ4C_2_4KHZ (1 << 5) // Default value +#define EQ4C_3_2KHZ (2 << 5) +#define EQ4C_4_1KHZ (3 << 5) + +// R22 REG_EQ5 +#define EQ5C_5_3KHZ (0) +#define EQ5C_6_9KHZ (1 << 5) // Default value +#define EQ5C_9KHZ (2 << 5) +#define EQ5C_11_7KHZ (3 << 5) + +// R18 - R22 +#define EQC_POS (5) +#define EQC_MASK (3) +#define EQG_POS (0) +#define EQG_MASK (31) + +// R24 REG_DAC_LIMITER1 +#define LIMEN (1 << 8) +#define LIMDCY_POS (4) +#define LIMDCY_MASK (15) +#define LIMDCY_750US (0) +#define LIMDCY_1_5MS (1 << 4) +#define LIMDCY_3MS (2 << 4) +#define LIMDCY_6MS (3 << 4) // Default value +#define LIMDCY_12MS (4 << 4) +#define LIMDCY_24MS (5 << 4) +#define LIMDCY_48MS (6 << 4) +#define LIMDCY_96MS (7 << 4) +#define LIMDCY_192MS (8 << 4) +#define LIMDCY_384MS (9 << 4) +#define LIMDCY_768MS (10 << 4) +#define LIMATK_POS (0) +#define LIMATK_MASK (15) +#define LIMATK_94US (0) +#define LIMATK_188US (1) +#define LIMATK_375US (2) // Default value +#define LIMATK_750US (3) +#define LIMATK_1_5MS (4) +#define LIMATK_3MS (5) +#define LIMATK_6MS (6) +#define LIMATK_12MS (7) +#define LIMATK_24MS (8) +#define LIMATK_48MS (9) +#define LIMATK_96MS (10) +#define LIMATK_192MS (11) + +// R25 REG_DAC_LIMITER2 +#define LIMLVL_POS (4) +#define LIMLVL_MASK (7) +#define LIMLVL_N1DB (0) // Default value +#define LIMLVL_N2DB (1 << 4) +#define LIMLVL_N3DB (2 << 4) +#define LIMLVL_N4DB (3 << 4) +#define LIMLVL_N5DB (4 << 4) +#define LIMLVL_N6DB (5 << 4) +#define LIMBOOST_POS (0) +#define LIMBOOST_MASK (15) +#define LIMBOOST_0DB (0) +#define LIMBOOST_1DB (1) +#define LIMBOOST_2DB (2) +#define LIMBOOST_3DB (3) +#define LIMBOOST_4DB (4) +#define LIMBOOST_5DB (5) +#define LIMBOOST_6DB (6) +#define LIMBOOST_7DB (7) +#define LIMBOOST_8DB (8) +#define LIMBOOST_9DB (9) +#define LIMBOOST_10DB (10) +#define LIMBOOST_11DB (11) +#define LIMBOOST_12DB (12) + +// R27 - R30 REG_NOTCH_FILTER1 - REG_NOTCH_FILTER4 +#define NFU (1 << 8) +#define NFEN (1 << 7) +#define NFA_POS (0) +#define NFA_MASK (127) + +// R32 REG_ALC1 +#define ALCSEL_OFF (0) // Default value +#define ALCSEL_RIGHT_ONLY (1 << 7) +#define ALCSEL_LEFT_ONLY (2 << 7) +#define ALCSEL_BOTH_ON (3 << 7) +#define ALCMAXGAIN_POS (3) +#define ALCMAXGAIN_MASK (7) +#define ALCMAXGAIN_N6_75DB (0) +#define ALCMAXGAIN_N0_75DB (1 << 3) +#define ALCMAXGAIN_5_25DB (2 << 3) +#define ALCMAXGAIN_11_25DB (3 << 3) +#define ALCMAXGAIN_17_25DB (4 << 3) +#define ALCMAXGAIN_23_25DB (5 << 3) +#define ALCMAXGAIN_29_25DB (6 << 3) +#define ALCMAXGAIN_35_25DB (7 << 3) // Default value +#define ALCMINGAIN_POS (0) +#define ALCMINGAIN_MASK (7) +#define ALCMINGAIN_N12DB (0) // Default value +#define ALCMINGAIN_N6DB (1) +#define ALCMINGAIN_0DB (2) +#define ALCMINGAIN_6DB (3) +#define ALCMINGAIN_12DB (4) +#define ALCMINGAIN_18DB (5) +#define ALCMINGAIN_24DB (6) +#define ALCMINGAIN_30DB (7) + +// R33 REG_ALC2 +#define ALCHLD_POS (4) +#define ALCHLD_MASK (15) +#define ALCHLD_0MS (0) // Default value +#define ALCHLD_2_67MS (1 << 4) +#define ALCHLD_5_33MS (2 << 4) +#define ALCHLD_10_67MS (3 << 4) +#define ALCHLD_21_33MS (4 << 4) +#define ALCHLD_42_67MS (5 << 4) +#define ALCHLD_85_33MS (6 << 4) +#define ALCHLD_170_67MS (7 << 4) +#define ALCHLD_341_33MS (8 << 4) +#define ALCHLD_682_67MS (9 << 4) +#define ALCHLD_1_36S (10 << 4) +#define ALCLVL_POS (0) +#define ALCLVL_MASK (15) +#define ALCLVL_N22_5DBFS (0) +#define ALCLVL_N21DBFS (1) +#define ALCLVL_N19_5DBFS (2) +#define ALCLVL_N18DBFS (3) +#define ALCLVL_N16_5DBFS (4) +#define ALCLVL_N15DBFS (5) +#define ALCLVL_N13_5DBFS (6) +#define ALCLVL_N12DBFS (7) +#define ALCLVL_N10_5DBFS (8) +#define ALCLVL_N9DBFS (9) +#define ALCLVL_N7_5DBFS (10) +#define ALCLVL_N6DBFS (11) // Default value +#define ALCLVL_N4_5DBFS (12) +#define ALCLVL_N3DBFS (13) +#define ALCLVL_N1_5DBFS (14) + +// R34 REG_ALC3 +#define ALCMODE_ALC (0) // Default value +#define ALCMODE_LIMITER (1 << 8) +#define ALCDCY_POS (4) +#define ALCDCY_MASK (15) +#define ALCDCY_0 (0) +#define ALCDCY_1 (1 << 4) +#define ALCDCY_2 (2 << 4) +#define ALCDCY_3 (3 << 4) // Default value +#define ALCDCY_4 (4 << 4) +#define ALCDCY_5 (5 << 4) +#define ALCDCY_6 (6 << 4) +#define ALCDCY_7 (7 << 4) +#define ALCDCY_8 (8 << 4) +#define ALCDCY_9 (9 << 4) +#define ALCDCY_10 (10 << 4) +#define ALCATK_POS (0) +#define ALCATK_MASK (15) +#define ALCATK_0 (0) +#define ALCATK_1 (1) +#define ALCATK_2 (2) // Default value +#define ALCATK_3 (3) +#define ALCATK_4 (4) +#define ALCATK_5 (5) +#define ALCATK_6 (6) +#define ALCATK_7 (7) +#define ALCATK_8 (8) +#define ALCATK_9 (9) +#define ALCATK_10 (10) + +// R35 REG_NOISE_GATE +#define NGEN (1 << 3) +#define NGTH_POS (0) +#define NGTH_MASK (7) +#define NGTH_N39DB (0) // Default value +#define NGTH_N45DB (1) +#define NGTH_N51DB (2) +#define NGTH_N57DB (3) +#define NGTH_N63DB (4) +#define NGTH_N69DB (5) +#define NGTH_N75DB (6) +#define NGTH_N81DB (7) + +// R36 REG_PLL_N +#define PLLPRESCALE (1 << 4) +#define PLLN_POS (0) +#define PLLN_MASK (15) + +// R37 - R39 REG_PLL_K1 - REG_PLL_K3 +#define PLLK1_POS (0) +#define PLLK1_MASK (63) +#define PLLK2_POS (0) +#define PLLK2_MASK (511) +#define PLLK3_POS (0) +#define PLLK3_MASK (511) + +// R41 REG_3D +#define DEPTH3D_POS (0) +#define DEPTH3D_MASK (15) +#define DEPTH3D_0 (0) // Default value +#define DEPTH3D_6_67 (1) +#define DEPTH3D_13_33 (2) +#define DEPTH3D_20 (3) +#define DEPTH3D_26_67 (4) +#define DEPTH3D_33_33 (5) +#define DEPTH3D_40 (6) +#define DEPTH3D_46_67 (7) +#define DEPTH3D_53_33 (8) +#define DEPTH3D_60 (9) +#define DEPTH3D_66_67 (10) +#define DEPTH3D_73_33 (11) +#define DEPTH3D_80 (12) +#define DEPTH3D_86_67 (13) +#define DEPTH3D_93_33 (14) +#define DEPTH3D_100 (15) + +// R43 REG_BEEP +#define MUTERPGA2INV (1 << 5) +#define INVROUT2 (1 << 4) +#define BEEPVOL_POS (1) +#define BEEPVOL_MASK (7) +#define BEEPVOL_N15DB (0) +#define BEEPVOL_N12DB (1 << 1) +#define BEEPVOL_N9DB (2 << 1) +#define BEEPVOL_N6DB (3 << 1) +#define BEEPVOL_N3DB (4 << 1) +#define BEEPVOL_0DB (5 << 1) +#define BEEPVOL_3DB (6 << 1) +#define BEEPVOL_6DB (7 << 1) +#define BEEPEN (1) + +// R44 REG_INPUT +#define MBVSEL_0_9AVDD (0) // Default value +#define MBVSEL_0_65AVDD (1 << 8) +#define R2_2INPVGA (1 << 6) +#define RIN2INPVGA (1 << 5) // Default value +#define RIP2INPVGA (1 << 4) // Default value +#define L2_2INPVGA (1 << 2) +#define LIN2INPVGA (1 << 1) // Default value +#define LIP2INPVGA (1) // Default value + +// R45 REG_LEFT_PGA_GAIN +#define INPPGAUPDATE (1 << 8) +#define INPPGAZCL (1 << 7) +#define INPPGAMUTEL (1 << 6) + +// R46 REG_RIGHT_PGA_GAIN +#define INPPGAZCR (1 << 7) +#define INPPGAMUTER (1 << 6) + +// R45 - R46 +#define INPPGAVOL_POS (0) +#define INPPGAVOL_MASK (63) + +// R47 REG_LEFT_ADC_BOOST +#define PGABOOSTL (1 << 8) // Default value +#define L2_2BOOSTVOL_POS (4) +#define L2_2BOOSTVOL_MASK (7) +#define L2_2BOOSTVOL_DISABLED (0) // Default value +#define L2_2BOOSTVOL_N12DB (1 << 4) +#define L2_2BOOSTVOL_N9DB (2 << 4) +#define L2_2BOOSTVOL_N6DB (3 << 4) +#define L2_2BOOSTVOL_N3DB (4 << 4) +#define L2_2BOOSTVOL_0DB (5 << 4) +#define L2_2BOOSTVOL_3DB (6 << 4) +#define L2_2BOOSTVOL_6DB (7 << 4) +#define AUXL2BOOSTVOL_POS (0) +#define AUXL2BOOSTVOL_MASK (7) +#define AUXL2BOOSTVOL_DISABLED (0) // Default value +#define AUXL2BOOSTVOL_N12DB (1) +#define AUXL2BOOSTVOL_N9DB (2) +#define AUXL2BOOSTVOL_N6DB (3) +#define AUXL2BOOSTVOL_N3DB (4) +#define AUXL2BOOSTVOL_0DB (5) +#define AUXL2BOOSTVOL_3DB (6) +#define AUXL2BOOSTVOL_6DB (7) + +// R48 REG_RIGHT_ADC_BOOST +#define PGABOOSTR (1 << 8) // Default value +#define R2_2BOOSTVOL_POS (4) +#define R2_2BOOSTVOL_MASK (7) +#define R2_2BOOSTVOL_DISABLED (0) // Default value +#define R2_2BOOSTVOL_N12DB (1 << 4) +#define R2_2BOOSTVOL_N9DB (2 << 4) +#define R2_2BOOSTVOL_N6DB (3 << 4) +#define R2_2BOOSTVOL_N3DB (4 << 4) +#define R2_2BOOSTVOL_0DB (5 << 4) +#define R2_2BOOSTVOL_3DB (6 << 4) +#define R2_2BOOSTVOL_6DB (7 << 4) +#define AUXR2BOOSTVOL_POS (0) +#define AUXR2BOOSTVOL_MASK (7) +#define AUXR2BOOSTVOL_DISABLED (0) // Default value +#define AUXR2BOOSTVOL_N12DB (1) +#define AUXR2BOOSTVOL_N9DB (2) +#define AUXR2BOOSTVOL_N6DB (3) +#define AUXR2BOOSTVOL_N3DB (4) +#define AUXR2BOOSTVOL_0DB (5) +#define AUXR2BOOSTVOL_3DB (6) +#define AUXR2BOOSTVOL_6DB (7) + +// R49 REG_OUTPUT +#define DACL2RMIX (1 << 6) +#define DACR2LMIX (1 << 5) +#define OUT4BOOST (1 << 4) +#define OUT3BOOST (1 << 3) +#define SPKBOOST (1 << 2) +#define TSDEN (1 << 1) +#define VROI (1) + +// R50 REG_LEFT_MIXER +#define AUXLMIXVOL_POS (6) +#define AUXLMIXVOL_MASK (7) +#define AUXLMIXVOL_N15DB (0) // Default value +#define AUXLMIXVOL_N12DB (1 << 6) +#define AUXLMIXVOL_N9DB (2 << 6) +#define AUXLMIXVOL_N6DB (3 << 6) +#define AUXLMIXVOL_N3DB (4 << 6) +#define AUXLMIXVOL_0DB (5 << 6) +#define AUXLMIXVOL_3DB (6 << 6) +#define AUXLMIXVOL_6DB (7 << 6) +#define AUXL2LMIX (1 << 5) +#define BYPLMIXVOL_POS (2) +#define BYPLMIXVOL_MASK (7) +#define BYPLMIXVOL_N15DB (0) // Default value +#define BYPLMIXVOL_N12DB (1 << 2) +#define BYPLMIXVOL_N9DB (2 << 2) +#define BYPLMIXVOL_N6DB (3 << 2) +#define BYPLMIXVOL_N3DB (4 << 2) +#define BYPLMIXVOL_0DB (5 << 2) +#define BYPLMIXVOL_3DB (6 << 2) +#define BYPLMIXVOL_6DB (7 << 2) +#define BYPL2LMIX (1 << 1) +#define DACL2LMIX (1) + +// R51 REG_RIGHT_MIXER +#define AUXRMIXVOL_POS (6) +#define AUXRMIXVOL_MASK (7) +#define AUXRMIXVOL_N15DB (0) // Default value +#define AUXRMIXVOL_N12DB (1 << 6) +#define AUXRMIXVOL_N9DB (2 << 6) +#define AUXRMIXVOL_N6DB (3 << 6) +#define AUXRMIXVOL_N3DB (4 << 6) +#define AUXRMIXVOL_0DB (5 << 6) +#define AUXRMIXVOL_3DB (6 << 6) +#define AUXRMIXVOL_6DB (7 << 6) +#define AUXR2RMIX (1 << 5) +#define BYPRMIXVOL_POS (2) +#define BYPRMIXVOL_MASK (7) +#define BYPRMIXVOL_N15DB (0) // Default value +#define BYPRMIXVOL_N12DB (1 << 2) +#define BYPRMIXVOL_N9DB (2 << 2) +#define BYPRMIXVOL_N6DB (3 << 2) +#define BYPRMIXVOL_N3DB (4 << 2) +#define BYPRMIXVOL_0DB (5 << 2) +#define BYPRMIXVOL_3DB (6 << 2) +#define BYPRMIXVOL_6DB (7 << 2) +#define BYPR2RMIX (1 << 1) +#define DACR2RMIX (1) + +// R52 - R55 REG_LOUT1_VOL - REG_ROUT2_VOL +#define HPVU (1 << 8) +#define SPKVU (1 << 8) +#define LOUT1ZC (1 << 7) +#define LOUT1MUTE (1 << 6) +#define ROUT1ZC (1 << 7) +#define ROUT1MUTE (1 << 6) +#define LOUT2ZC (1 << 7) +#define LOUT2MUTE (1 << 6) +#define ROUT2ZC (1 << 7) +#define ROUT2MUTE (1 << 6) +#define VOL_POS (0) +#define VOL_MASK (63) + +// R56 REG_OUT3_MIXER +#define OUT3MUTE (1 << 6) +#define OUT4_2OUT3 (1 << 3) +#define BYPL2OUT3 (1 << 2) +#define LMIX2OUT3 (1 << 1) +#define LDAC2OUT3 (1) + +// R57 REG_OUT4_MIXER +#define OUT4MUTE (1 << 6) +#define HALFSIG (1 << 5) +#define LMIX2OUT4 (1 << 4) +#define LDAC2OUT4 (1 << 3) +#define BYPR2OUT4 (1 << 2) +#define RMIX2OUT4 (1 << 1) +#define RDAC2OUT4 (1) + +static void write_reg(struct rt_i2c_bus_device *dev, rt_uint16_t s_data) +{ + struct rt_i2c_msg msg; + rt_uint8_t send_buffer[2]; + RT_ASSERT(dev != RT_NULL); + send_buffer[0] = (rt_uint8_t)(s_data >> 8); + send_buffer[1] = (rt_uint8_t)(s_data); + msg.addr = 0x1A; + msg.flags = RT_I2C_WR; + msg.len = 2; + msg.buf = send_buffer; + rt_i2c_transfer(dev, &msg, 1); +} + +/** + * @brief Init WM8978 Codec device. + * @param dev: I2C device handle + * @retval RT_EOK if correct communication, else wrong communication + */ +int wm8978_init(struct rt_i2c_bus_device *dev) +{ + write_reg(dev, REG_SOFTWARE_RESET); + + /* 1.5x boost power up sequence,Mute all outputs. */ + write_reg(dev, REG_LOUT1_VOL | LOUT1MUTE); + write_reg(dev, REG_ROUT1_VOL | ROUT1MUTE); + write_reg(dev, REG_LOUT2_VOL | LOUT2MUTE); + write_reg(dev, REG_ROUT2_VOL | ROUT2MUTE); + + /* Enable unused output chosen from L/ROUT2, OUT3 or OUT4. */ + write_reg(dev, REG_POWER_MANAGEMENT3 | OUT4EN); + /* Set BUFDCOPEN=1 and BUFIOEN=1 in register R1 */ + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN); + /* Set SPKBOOST=1 in register R49. */ + write_reg(dev, REG_OUTPUT | SPKBOOST); + /* Set VMIDSEL[1:0] to required value in register R1. */ + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); + /* Set L/RMIXEN=1 and DACENL/R=1 in register R3.*/ + write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR); + /* Set BIASEN=1 in register R1. */ + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); + /* Set L/ROUT2EN=1 in register R3. */ + write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN); + /* Enable other mixers as required. */ + /* Enable other outputs as required. */ + write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR); + write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR | ADCENL | ADCENR); + + /* Digital inferface setup. */ + write_reg(dev, REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S); + + write_reg(dev, REG_ADDITIONAL | WM_SR_8KHZ); + + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | MICBEN | BIASEN); + write_reg(dev, REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1); + + /* Enable DAC 128x oversampling. */ + write_reg(dev, REG_DAC | DACOSR128); + + /* Set LOUT2/ROUT2 in BTL operation. */ + write_reg(dev, REG_BEEP | INVROUT2); + + /* MIC config. */ + write_reg(dev, REG_INPUT | MBVSEL_0_65AVDD | RIN2INPVGA | RIP2INPVGA | LIN2INPVGA | LIP2INPVGA); + + /* MIC PGA -12db to 35.25db, 0.75setp default: 16(0db). */ + write_reg(dev, REG_LEFT_PGA_GAIN | INPPGAZCL | (36 & INPPGAVOL_MASK)); + write_reg(dev, REG_RIGHT_PGA_GAIN | INPPGAZCR | (36 & INPPGAVOL_MASK) | INPPGAUPDATE); + + write_reg(dev, REG_LEFT_ADC_BOOST | PGABOOSTL | L2_2BOOSTVOL_DISABLED | AUXL2BOOSTVOL_DISABLED); + write_reg(dev, REG_RIGHT_ADC_BOOST | PGABOOSTR | R2_2BOOSTVOL_DISABLED | AUXR2BOOSTVOL_DISABLED); + + /* Set output volume. */ + wm8978_set_volume(dev, 55); + + return RT_EOK; +} + +/** + * @brief Set WM8978 DAC volume level. + * @param dev: I2C device handle + * @param vol: volume level(0 ~ 99) + * @retval RT_EOK if correct communication, else wrong communication + */ +int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol) +{ + vol = 63 * vol / 100; + vol = (vol & VOL_MASK) << VOL_POS; + write_reg(dev, REG_LOUT1_VOL | vol); + write_reg(dev, REG_ROUT1_VOL | HPVU | vol); + write_reg(dev, REG_LOUT2_VOL | vol); + write_reg(dev, REG_ROUT2_VOL | SPKVU | vol); + + return RT_EOK; +} diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.h b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.h new file mode 100644 index 0000000000..483fea38fc --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ +#ifndef __DRV_WM8978_H__ +#define __DRV_WM8978_H__ + +#include +#include + +int wm8978_init(struct rt_i2c_bus_device *dev); +int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol); + +#endif diff --git a/bsp/stm32f429-apollo/drivers/board.c b/bsp/stm32f429-apollo/drivers/board.c index 9788ebc370..8943f91456 100644 --- a/bsp/stm32f429-apollo/drivers/board.c +++ b/bsp/stm32f429-apollo/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/board.h b/bsp/stm32f429-apollo/drivers/board.h index ee15a29582..30f8fd6995 100644 --- a/bsp/stm32f429-apollo/drivers/board.h +++ b/bsp/stm32f429-apollo/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -46,7 +42,7 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f429-apollo/drivers/drv_eth.c b/bsp/stm32f429-apollo/drivers/drv_eth.c index 78e2342c0f..5d363194e3 100644 --- a/bsp/stm32f429-apollo/drivers/drv_eth.c +++ b/bsp/stm32f429-apollo/drivers/drv_eth.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_gpio.c b/bsp/stm32f429-apollo/drivers/drv_gpio.c index fe26d0027a..6f7edddffa 100644 --- a/bsp/stm32f429-apollo/drivers/drv_gpio.c +++ b/bsp/stm32f429-apollo/drivers/drv_gpio.c @@ -1,11 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_gpio.h b/bsp/stm32f429-apollo/drivers/drv_gpio.h index f263a87c2d..60199bd34b 100644 --- a/bsp/stm32f429-apollo/drivers/drv_gpio.h +++ b/bsp/stm32f429-apollo/drivers/drv_gpio.h @@ -1,11 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_i2c.c b/bsp/stm32f429-apollo/drivers/drv_i2c.c index 38321e8b51..2f334ccea4 100644 --- a/bsp/stm32f429-apollo/drivers/drv_i2c.c +++ b/bsp/stm32f429-apollo/drivers/drv_i2c.c @@ -1,11 +1,7 @@ /* - * File : drv_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_i2c.h b/bsp/stm32f429-apollo/drivers/drv_i2c.h index 8e91be0e0e..e0c17f2f57 100644 --- a/bsp/stm32f429-apollo/drivers/drv_i2c.h +++ b/bsp/stm32f429-apollo/drivers/drv_i2c.h @@ -1,12 +1,8 @@ /* -* File : drv_i2c.h -* This file is part of RT-Thread RTOS -* COPYRIGHT (C) 2017 RT-Thread Develop Team -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rt-thread.org/license/LICENSE -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2017-06-05 tanek first implementation. diff --git a/bsp/stm32f429-apollo/drivers/drv_lcd.c b/bsp/stm32f429-apollo/drivers/drv_lcd.c index 2608081acf..0291d53c45 100644 --- a/bsp/stm32f429-apollo/drivers/drv_lcd.c +++ b/bsp/stm32f429-apollo/drivers/drv_lcd.c @@ -1,11 +1,7 @@ /* - * File : drv_lcd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_nand.c b/bsp/stm32f429-apollo/drivers/drv_nand.c index d546bbd197..124515878b 100644 --- a/bsp/stm32f429-apollo/drivers/drv_nand.c +++ b/bsp/stm32f429-apollo/drivers/drv_nand.c @@ -1,11 +1,7 @@ /* - * File : drv_nand.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_pcf8574.c b/bsp/stm32f429-apollo/drivers/drv_pcf8574.c index 4801a92bc2..90f7793770 100644 --- a/bsp/stm32f429-apollo/drivers/drv_pcf8574.c +++ b/bsp/stm32f429-apollo/drivers/drv_pcf8574.c @@ -1,11 +1,7 @@ /* - * File : drv_iic.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_rtc.c b/bsp/stm32f429-apollo/drivers/drv_rtc.c index 3318606e8d..4da872d2d8 100644 --- a/bsp/stm32f429-apollo/drivers/drv_rtc.c +++ b/bsp/stm32f429-apollo/drivers/drv_rtc.c @@ -1,11 +1,7 @@ /* - * File : drv_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_rtc.h b/bsp/stm32f429-apollo/drivers/drv_rtc.h index 37b34540c1..558486428e 100644 --- a/bsp/stm32f429-apollo/drivers/drv_rtc.h +++ b/bsp/stm32f429-apollo/drivers/drv_rtc.h @@ -1,19 +1,13 @@ - /***************************************************************************//** - * @file drv_rtc.h - * @brief RTC driver of RT-Thread RTOS for EFM32 - * COPYRIGHT (C) 2012, RT-Thread Development Team - * @author Bernard, onelife - * @version 1.0 - ******************************************************************************* - * @section License - * The license and distribution terms for this file may be found in the file - * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE - ******************************************************************************* - * @section Change Logs +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs * Date Author Notes * 2009-01-05 Bernard the first version * 2010-12-27 onelife Modification for EFM32 - *********************************************************************/ + */ #ifndef __DRV_RTC_H__ #define __DRV_RTC_H__ #include diff --git a/bsp/stm32f429-apollo/drivers/drv_sdram.c b/bsp/stm32f429-apollo/drivers/drv_sdram.c index c7f463c08e..f500184ca0 100644 --- a/bsp/stm32f429-apollo/drivers/drv_sdram.c +++ b/bsp/stm32f429-apollo/drivers/drv_sdram.c @@ -1,21 +1,7 @@ /* - * File : drv_sdram.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_sdram.h b/bsp/stm32f429-apollo/drivers/drv_sdram.h index 5cb3d128a6..73f29bf966 100644 --- a/bsp/stm32f429-apollo/drivers/drv_sdram.h +++ b/bsp/stm32f429-apollo/drivers/drv_sdram.h @@ -1,11 +1,7 @@ /* - * File : drv_sdram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_spi.c b/bsp/stm32f429-apollo/drivers/drv_spi.c index a82454d907..530b59b437 100644 --- a/bsp/stm32f429-apollo/drivers/drv_spi.c +++ b/bsp/stm32f429-apollo/drivers/drv_spi.c @@ -1,11 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -543,7 +539,7 @@ struct stm32f4_spi stm32f4_spi5 = static struct rt_spi_bus spi5_bus; - +#ifdef SPI_USE_DMA /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -562,6 +558,7 @@ void DMA2_Stream4_IRQHandler(void) { HAL_DMA_IRQHandler(stm32f4_spi5.spi_handle.hdmatx); } +#endif /* SPI_USE_DMA */ #endif diff --git a/bsp/stm32f429-apollo/drivers/drv_spi.h b/bsp/stm32f429-apollo/drivers/drv_spi.h index 8c74fdb626..f6b9156628 100644 --- a/bsp/stm32f429-apollo/drivers/drv_spi.h +++ b/bsp/stm32f429-apollo/drivers/drv_spi.h @@ -1,11 +1,7 @@ /* - * File : stm32f20x_40x_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/drv_spi_flash.c b/bsp/stm32f429-apollo/drivers/drv_spi_flash.c index f6c5748dac..a73e86179a 100644 --- a/bsp/stm32f429-apollo/drivers/drv_spi_flash.c +++ b/bsp/stm32f429-apollo/drivers/drv_spi_flash.c @@ -1,11 +1,7 @@ /* - * File : stm32f20x_40x_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h b/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h index a7633ed68a..06c1599e2a 100644 --- a/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h +++ b/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h @@ -71,7 +71,7 @@ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED /* */ -/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SAI_MODULE_ENABLED /* */ #define HAL_SD_MODULE_ENABLED /* */ #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ diff --git a/bsp/stm32f429-apollo/drivers/usart.c b/bsp/stm32f429-apollo/drivers/usart.c index b6606e90f8..ecca8b7307 100644 --- a/bsp/stm32f429-apollo/drivers/usart.c +++ b/bsp/stm32f429-apollo/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/drivers/usart.h b/bsp/stm32f429-apollo/drivers/usart.h index 3faf85fcde..12cfd253cf 100644 --- a/bsp/stm32f429-apollo/drivers/usart.h +++ b/bsp/stm32f429-apollo/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-apollo/project.ewp b/bsp/stm32f429-apollo/project.ewp index 6534098cdb..9b4e576da8 100644 --- a/bsp/stm32f429-apollo/project.ewp +++ b/bsp/stm32f429-apollo/project.ewp @@ -1,2613 +1,2726 @@ - - + - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 + 3 + + Debug + + ARM + 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - 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$PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c + + + $PROJ_DIR$\Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + - - diff --git a/bsp/stm32f429-apollo/project.uvproj b/bsp/stm32f429-apollo/project.uvproj index 994592cd52..9f73e8989d 100644 --- a/bsp/stm32f429-apollo/project.uvproj +++ b/bsp/stm32f429-apollo/project.uvproj @@ -359,7 +359,7 @@ USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32F429xx - applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\dfs\filesystems\romfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\dfs\filesystems\romfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket @@ -1768,16 +1768,16 @@ - net_sockets.c + af_inet_lwip.c 1 - ..\..\components\net\sal_socket\socket\net_sockets.c + ..\..\components\net\sal_socket\impl\af_inet_lwip.c - af_inet_lwip.c + net_sockets.c 1 - ..\..\components\net\sal_socket\impl\af_inet_lwip.c + ..\..\components\net\sal_socket\socket\net_sockets.c diff --git a/bsp/stm32f429-apollo/project.uvprojx b/bsp/stm32f429-apollo/project.uvprojx index 61435f8369..bf4393b318 100644 --- a/bsp/stm32f429-apollo/project.uvprojx +++ b/bsp/stm32f429-apollo/project.uvprojx @@ -10,12 +10,13 @@ rt_thread_stm32f429 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32F429IGHx STMicroelectronics - Keil.STM32F4xx_DFP.2.11.0 + Keil.STM32F4xx_DFP.2.13.0 http://www.keil.com/pack IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -323,6 +324,7 @@ 0 0 1 + 0 0 1 1 @@ -335,7 +337,7 @@ USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32F429xx - applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\dfs\filesystems\romfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\dfs\filesystems\romfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket @@ -1016,6 +1018,7 @@ 2 2 2 + 2 2 0 0 @@ -1122,6 +1125,11 @@ 1 ..\..\components\drivers\src\pipe.c + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + ringbuffer.c 1 @@ -1237,6 +1245,11 @@ 1 ..\..\components\libc\compilers\armlibc\time.c + + gmtime_r.c + 1 + ..\..\components\libc\compilers\common\gmtime_r.c + @@ -1442,16 +1455,16 @@ 1 ..\..\components\net\sal_socket\socket\net_netdb.c - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - af_inet_lwip.c 1 ..\..\components\net\sal_socket\impl\af_inet_lwip.c + + net_sockets.c + 1 + ..\..\components\net\sal_socket\socket\net_sockets.c + dfs_net.c 1 diff --git a/bsp/stm32f429-armfly/applications/application.c b/bsp/stm32f429-armfly/applications/application.c index c4752b0140..7a44930cef 100644 --- a/bsp/stm32f429-armfly/applications/application.c +++ b/bsp/stm32f429-armfly/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/applications/rtgui_demo.c b/bsp/stm32f429-armfly/applications/rtgui_demo.c index d4ef2dba44..a26fdfe0fd 100644 --- a/bsp/stm32f429-armfly/applications/rtgui_demo.c +++ b/bsp/stm32f429-armfly/applications/rtgui_demo.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/applications/rtgui_demo.h b/bsp/stm32f429-armfly/applications/rtgui_demo.h index e27f7b5609..1662a4d346 100644 --- a/bsp/stm32f429-armfly/applications/rtgui_demo.h +++ b/bsp/stm32f429-armfly/applications/rtgui_demo.h @@ -1,11 +1,7 @@ /* - * File : dc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/applications/startup.c b/bsp/stm32f429-armfly/applications/startup.c index 63fa63123c..5d58727d82 100644 --- a/bsp/stm32f429-armfly/applications/startup.c +++ b/bsp/stm32f429-armfly/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/board.c b/bsp/stm32f429-armfly/drivers/board.c index d0a3cbf366..94ac6b5f50 100644 --- a/bsp/stm32f429-armfly/drivers/board.c +++ b/bsp/stm32f429-armfly/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/board.h b/bsp/stm32f429-armfly/drivers/board.h index 6667446d5d..f9aeb2f508 100644 --- a/bsp/stm32f429-armfly/drivers/board.h +++ b/bsp/stm32f429-armfly/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,7 +29,7 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RTT_HEAP$$ZI$$Base; extern int Image$$RTT_HEAP$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) diff --git a/bsp/stm32f429-armfly/drivers/drv_eth.c b/bsp/stm32f429-armfly/drivers/drv_eth.c index b4bf070ab8..d7754d2183 100644 --- a/bsp/stm32f429-armfly/drivers/drv_eth.c +++ b/bsp/stm32f429-armfly/drivers/drv_eth.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_ft5x06.c b/bsp/stm32f429-armfly/drivers/drv_ft5x06.c index 70be723c50..077ee84e23 100644 --- a/bsp/stm32f429-armfly/drivers/drv_ft5x06.c +++ b/bsp/stm32f429-armfly/drivers/drv_ft5x06.c @@ -1,21 +1,7 @@ /* - * File : drv_ft5x06.c - * ft5x06 touch driver - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_i2c.c b/bsp/stm32f429-armfly/drivers/drv_i2c.c index d1ca48b017..f3d3796a3c 100644 --- a/bsp/stm32f429-armfly/drivers/drv_i2c.c +++ b/bsp/stm32f429-armfly/drivers/drv_i2c.c @@ -1,11 +1,7 @@ /* - * File : drv_iic.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_lcd.c b/bsp/stm32f429-armfly/drivers/drv_lcd.c index df68ae8db7..96444d5b5f 100644 --- a/bsp/stm32f429-armfly/drivers/drv_lcd.c +++ b/bsp/stm32f429-armfly/drivers/drv_lcd.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_sdram.c b/bsp/stm32f429-armfly/drivers/drv_sdram.c index 0b3c642728..0a9fa7e406 100644 --- a/bsp/stm32f429-armfly/drivers/drv_sdram.c +++ b/bsp/stm32f429-armfly/drivers/drv_sdram.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_spi.c b/bsp/stm32f429-armfly/drivers/drv_spi.c index 6f439d6de7..e8ab90d032 100644 --- a/bsp/stm32f429-armfly/drivers/drv_spi.c +++ b/bsp/stm32f429-armfly/drivers/drv_spi.c @@ -1,11 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_spi.h b/bsp/stm32f429-armfly/drivers/drv_spi.h index 17e3d3852c..e1cc65c645 100644 --- a/bsp/stm32f429-armfly/drivers/drv_spi.h +++ b/bsp/stm32f429-armfly/drivers/drv_spi.h @@ -1,11 +1,7 @@ /* - * File : stm32f20x_40x_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/drv_spi_flash.c b/bsp/stm32f429-armfly/drivers/drv_spi_flash.c index 00b8cb75e0..ff6e75e7f5 100644 --- a/bsp/stm32f429-armfly/drivers/drv_spi_flash.c +++ b/bsp/stm32f429-armfly/drivers/drv_spi_flash.c @@ -1,11 +1,7 @@ /* - * File : stm32f20x_40x_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/usart.c b/bsp/stm32f429-armfly/drivers/usart.c index b6606e90f8..ecca8b7307 100644 --- a/bsp/stm32f429-armfly/drivers/usart.c +++ b/bsp/stm32f429-armfly/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/drivers/usart.h b/bsp/stm32f429-armfly/drivers/usart.h index 3faf85fcde..12cfd253cf 100644 --- a/bsp/stm32f429-armfly/drivers/usart.h +++ b/bsp/stm32f429-armfly/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-armfly/project.uvprojx b/bsp/stm32f429-armfly/project.uvprojx index 752283b635..c7c1d3968e 100644 --- a/bsp/stm32f429-armfly/project.uvprojx +++ b/bsp/stm32f429-armfly/project.uvprojx @@ -10,12 +10,13 @@ rt-thread_stm32f4xx 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32F429BITx STMicroelectronics - Keil.STM32F4xx_DFP.2.11.0 + Keil.STM32F4xx_DFP.2.13.0 http://www.keil.com/pack IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -323,6 +324,7 @@ 0 0 0 + 0 0 1 1 @@ -335,7 +337,7 @@ USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32F429xx - applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket @@ -981,6 +983,7 @@ 2 2 2 + 2 2 0 0 @@ -1412,16 +1415,16 @@ 1 ..\..\components\net\sal_socket\socket\net_netdb.c - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - af_inet_lwip.c 1 ..\..\components\net\sal_socket\impl\af_inet_lwip.c + + net_sockets.c + 1 + ..\..\components\net\sal_socket\socket\net_sockets.c + dfs_net.c 1 diff --git a/bsp/stm32f429-disco/.config b/bsp/stm32f429-disco/.config index 20b6514e3d..a2d11a94c3 100644 --- a/bsp/stm32f429-disco/.config +++ b/bsp/stm32f429-disco/.config @@ -13,13 +13,22 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=1 -CONFIG_RT_DEBUG_THREAD=0 CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -47,11 +56,11 @@ CONFIG_RT_USING_HEAP=y # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -# CONFIG_RT_USING_MODULE is not set # # RT-Thread Components @@ -73,6 +82,7 @@ CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 @@ -80,32 +90,49 @@ CONFIG_FINSH_CMD_SIZE=80 CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y # CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # -# CONFIG_RT_USING_DFS is not set -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# # CONFIG_RT_USING_WIFI is not set # @@ -118,13 +145,22 @@ CONFIG_RT_USING_PIN=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y -CONFIG_RT_USING_PTHREADS=y -# CONFIG_HAVE_SYS_SIGNALS is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set # -# Network stack +# Network # +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + # # light weight TCP/IP stack # @@ -135,6 +171,11 @@ CONFIG_RT_USING_PTHREADS=y # # CONFIG_RT_USING_MODBUS is not set +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + # # VBUS(Virtual Software BUS) # @@ -150,19 +191,6 @@ CONFIG_RT_USING_PTHREADS=y # RT-Thread online packages # -# -# system packages -# - -# -# RT-Thread GUI Engine -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set - # # IoT - internet of things # @@ -171,10 +199,10 @@ CONFIG_RT_USING_PTHREADS=y # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set # # Wi-Fi @@ -192,6 +220,16 @@ CONFIG_RT_USING_PTHREADS=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set # # security packages @@ -203,6 +241,7 @@ CONFIG_RT_USING_PTHREADS=y # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set @@ -210,29 +249,85 @@ CONFIG_RT_USING_PTHREADS=y # multimedia packages # # CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_IPERF is not set +# CONFIG_PKG_USING_RDB is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT_V001 is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT_LATEST_VERSION is not set +# CONFIG_LV_MEM_STATIC is not set +# CONFIG_LV_MEM_DYNAMIC is not set +# CONFIG_LV_COLOR_DEPTH_1 is not set +# CONFIG_LV_COLOR_DEPTH_8 is not set +# CONFIG_LV_COLOR_DEPTH_16 is not set +# CONFIG_LV_COLOR_DEPTH_24 is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set # # miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # # example package: hello # # CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set +CONFIG_RT_USING_ILI9341_LCD=y +CONFIG_RT_USING_STMPE811_TOUCH=y CONFIG_RT_USING_EXT_SDRAM=y CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set # CONFIG_RT_USING_SPI5 is not set +CONFIG_RT_USING_I2C3=y diff --git a/bsp/stm32f429-disco/applications/application.c b/bsp/stm32f429-disco/applications/application.c index e6ad9e652f..264c553c0b 100644 --- a/bsp/stm32f429-disco/applications/application.c +++ b/bsp/stm32f429-disco/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,8 +28,11 @@ #include #endif + void rt_init_thread_entry(void* parameter) { + rt_thread_t tid; + /* GDB STUB */ #ifdef RT_USING_GDB gdb_set_device("uart6"); @@ -55,10 +54,9 @@ void rt_init_thread_entry(void* parameter) rt_kprintf("TCP/IP initialized!\n"); } #endif - -#ifdef RT_USING_FINSH - finsh_system_init(); -#endif + + rt_components_init(); + } int rt_application_init() diff --git a/bsp/stm32f429-disco/applications/startup.c b/bsp/stm32f429-disco/applications/startup.c index f7cf47ae6b..c41f3dcb40 100644 --- a/bsp/stm32f429-disco/applications/startup.c +++ b/bsp/stm32f429-disco/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-disco/drivers/Kconfig b/bsp/stm32f429-disco/drivers/Kconfig index 77c7d9ce6e..4e77b93df5 100644 --- a/bsp/stm32f429-disco/drivers/Kconfig +++ b/bsp/stm32f429-disco/drivers/Kconfig @@ -1,3 +1,13 @@ +config RT_USING_ILI9341_LCD + bool "Enable LCD on the board" + default y + select RT_USING_EXT_SDRAM + +config RT_USING_STMPE811_TOUCH + bool "Enable Touchscreen on the board" + default y + select RT_USING_I2C3 + config RT_USING_EXT_SDRAM bool "Enable SDRAM on the board" default y @@ -16,4 +26,10 @@ config RT_USING_UART3 config RT_USING_SPI5 bool "Enable SPI5" - default n + default n + +config RT_USING_I2C3 + bool "Enable I2C3" + default y + select RT_USING_I2C + select RT_USING_I2C_BITOPS diff --git a/bsp/stm32f429-disco/drivers/SConscript b/bsp/stm32f429-disco/drivers/SConscript index 16cd3a1869..3b595f8a5f 100644 --- a/bsp/stm32f429-disco/drivers/SConscript +++ b/bsp/stm32f429-disco/drivers/SConscript @@ -9,9 +9,20 @@ src = Split(""" board.c stm32f4xx_it.c usart.c -drv_sdram.c """) +if GetDepend(['RT_USING_EXT_SDRAM']): + src += ['drv_sdram.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['drv_i2c.c'] + +if GetDepend(['RT_USING_ILI9341_LCD']): + src += ['drv_lcd.c'] + +if GetDepend(['RT_USING_STMPE811_TOUCH']): + src += ['drv_touch.c'] + CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/stm32f429-disco/drivers/board.c b/bsp/stm32f429-disco/drivers/board.c index 708d30345a..d2d2b55da2 100644 --- a/bsp/stm32f429-disco/drivers/board.c +++ b/bsp/stm32f429-disco/drivers/board.c @@ -1,25 +1,27 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-01-05 Bernard first implementation */ + #include #include #include +#ifdef PKG_USING_GUIENGINE +#include +#endif + #include "stm32f4xx.h" #include "board.h" #include "usart.h" #include "stm32f4xx_hal.h" + void _init(void) { @@ -133,6 +135,10 @@ void HAL_Delay(__IO uint32_t Delay) */ void rt_hw_board_init() { +#ifdef PKG_USING_GUIENGINE + rt_device_t lcd; +#endif + HAL_Init(); SystemClock_Config(); @@ -142,10 +148,16 @@ void rt_hw_board_init() #else stm32_hw_usart_init(); #endif - + #ifdef RT_USING_CONSOLE rt_console_set_device(CONSOLE_DEVICE); #endif + +#ifdef PKG_USING_GUIENGINE + lcd = rt_device_find("lcd"); + rtgui_graphic_set_device(lcd); +#endif + } /*@}*/ diff --git a/bsp/stm32f429-disco/drivers/board.h b/bsp/stm32f429-disco/drivers/board.h index 8a32a11d8a..cc7db8e323 100644 --- a/bsp/stm32f429-disco/drivers/board.h +++ b/bsp/stm32f429-disco/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -44,7 +40,7 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f429-disco/drivers/drv_i2c.c b/bsp/stm32f429-disco/drivers/drv_i2c.c new file mode 100644 index 0000000000..a6afde74ce --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_i2c.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-06-05 tanek first implementation. + */ + +#include "drv_i2c.h" + +#include +#include +#include +#include + +#define DEBUG + +#ifdef DEBUG +#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + +static void stm32f4_i2c_gpio_init() +{ + GPIO_InitTypeDef GPIO_Initure; + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + GPIO_Initure.Pin = GPIO_PIN_8; + GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOA, &GPIO_Initure); + + GPIO_Initure.Pin = GPIO_PIN_9; + GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOC, &GPIO_Initure); + + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET); +} + +static void stm32f4_set_sda(void *data, rt_int32_t state) +{ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, (GPIO_PinState)state); +} + +static void stm32f4_set_scl(void *data, rt_int32_t state) +{ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (GPIO_PinState)state); +} + +static rt_int32_t stm32f4_get_sda(void *data) +{ + return (rt_int32_t)HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_9); +} + +static rt_int32_t stm32f4_get_scl(void *data) +{ + return (rt_int32_t)HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_8); +} + +static void stm32f4_udelay(rt_uint32_t us) +{ + rt_int32_t i; + for (; us > 0; us--) + { + i = 50; + while (i > 0) + { + i--; + } + } +} + +static const struct rt_i2c_bit_ops bit_ops = { + RT_NULL, + stm32f4_set_sda, + stm32f4_set_scl, + stm32f4_get_sda, + stm32f4_get_scl, + + stm32f4_udelay, + + 5, + 100 +}; + +int stm32f4_i2c_init(void) +{ + struct rt_i2c_bus_device *bus; + + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } + + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + + bus->priv = (void *)&bit_ops; + + stm32f4_i2c_gpio_init(); + + rt_i2c_bit_add_bus(bus, "i2c3"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(stm32f4_i2c_init); diff --git a/bsp/stm32f429-disco/drivers/drv_i2c.h b/bsp/stm32f429-disco/drivers/drv_i2c.h new file mode 100644 index 0000000000..cebcebc63b --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_i2c.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + + * Change Logs: + * Date Author Notes + * 2017-06-05 tanek first implementation. + */ + +#ifndef STM32F4XX_IIC_INCLUDED +#define STM32F4XX_IIC_INCLUDED + +#include +#include + +#include "stm32f4xx_hal.h" + + +#endif // STM32F20X_40X_SPI_H_INCLUDED diff --git a/bsp/stm32f429-disco/drivers/drv_lcd.c b/bsp/stm32f429-disco/drivers/drv_lcd.c new file mode 100644 index 0000000000..6612f60928 --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_lcd.c @@ -0,0 +1,952 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-13 xuzhuoyi first implementation + */ + +#include "drv_lcd.h" +#include + +//#define DEBUG + +#ifdef DEBUG +#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + +typedef struct +{ + rt_uint16_t width; + rt_uint16_t height; + rt_uint16_t id; + rt_uint8_t dir; //Horizontal or vertical screen control: 0, vertical; 1, horizontal + rt_uint16_t wramcmd; + rt_uint16_t setxcmd; + rt_uint16_t setycmd; +} lcd_info_t; + +typedef struct +{ + volatile rt_uint16_t reg; + volatile rt_uint16_t ram; +} lcd_ili9341_t; + +#define LCD_ILI9341_BASE ((rt_uint32_t)(0x60000000 | 0x0007FFFE)) +#define ili9341 ((lcd_ili9341_t *) LCD_ILI9341_BASE) +////////////////////////////////////////////////////////////////////////////////// + +//Definition of scan direction +#define L2R_U2D 0 +#define L2R_D2U 1 +#define R2L_U2D 2 +#define R2L_D2U 3 +#define U2D_L2R 4 +#define U2D_R2L 5 +#define D2U_L2R 6 +#define D2U_R2L 7 +#define DFT_SCAN_DIR L2R_U2D + +static lcd_info_t lcddev; +LTDC_HandleTypeDef LtdcHandler; +static RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; +/* Default LCD configuration with LCD Layer 1 */ +static uint32_t ActiveLayer = 0; +SPI_HandleTypeDef hspi5; +static SPI_HandleTypeDef SpiHandle; + +void delay_us(rt_uint32_t nus) +{ + //rt_thread_delay(1); + while (nus--) { + __NOP(); + } +} + +void delay_ms(rt_uint32_t nms) +{ + //rt_thread_delay((RT_TICK_PER_SECOND * nms + 999) / 1000); + while (nms--) + { + int i; + for (i = 0; i < 10000; i++) + { + __NOP(); + } + } +} + +/** + * @brief SPI MSP Init. + * @param hspi: SPI handle + */ +static void SPIx_MspInit(SPI_HandleTypeDef *hspi) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable SPIx clock */ + DISCOVERY_SPIx_CLK_ENABLE(); + + /* Enable DISCOVERY_SPI GPIO clock */ + DISCOVERY_SPIx_GPIO_CLK_ENABLE(); + + /* configure SPI SCK, MOSI and MISO */ + GPIO_InitStructure.Pin = (DISCOVERY_SPIx_SCK_PIN | DISCOVERY_SPIx_MOSI_PIN | DISCOVERY_SPIx_MISO_PIN); + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_PULLDOWN; + GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM; + GPIO_InitStructure.Alternate = DISCOVERY_SPIx_AF; + HAL_GPIO_Init(DISCOVERY_SPIx_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief Selects the LCD Layer. + * @param LayerIndex: the Layer foreground or background. + */ +void BSP_LCD_SelectLayer(uint32_t LayerIndex) +{ + ActiveLayer = LayerIndex; +} + +/** + * @brief Initializes the LTDC MSP. + */ +__weak void BSP_LCD_MspInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable the LTDC and DMA2D Clock */ + __HAL_RCC_LTDC_CLK_ENABLE(); + __HAL_RCC_DMA2D_CLK_ENABLE(); + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /* GPIOs Configuration */ + /* + +------------------------+-----------------------+----------------------------+ + + LCD pins assignment + + +------------------------+-----------------------+----------------------------+ + | LCD_TFT R2 <-> PC.10 | LCD_TFT G2 <-> PA.06 | LCD_TFT B2 <-> PD.06 | + | LCD_TFT R3 <-> PB.00 | LCD_TFT G3 <-> PG.10 | LCD_TFT B3 <-> PG.11 | + | LCD_TFT R4 <-> PA.11 | LCD_TFT G4 <-> PB.10 | LCD_TFT B4 <-> PG.12 | + | LCD_TFT R5 <-> PA.12 | LCD_TFT G5 <-> PB.11 | LCD_TFT B5 <-> PA.03 | + | LCD_TFT R6 <-> PB.01 | LCD_TFT G6 <-> PC.07 | LCD_TFT B6 <-> PB.08 | + | LCD_TFT R7 <-> PG.06 | LCD_TFT G7 <-> PD.03 | LCD_TFT B7 <-> PB.09 | + ------------------------------------------------------------------------------- + | LCD_TFT HSYNC <-> PC.06 | LCDTFT VSYNC <-> PA.04 | + | LCD_TFT CLK <-> PG.07 | LCD_TFT DE <-> PF.10 | + ----------------------------------------------------- + */ + + /* GPIOA configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_6 | + GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + GPIO_InitStructure.Alternate= GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOB configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_8 | \ + GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* GPIOC configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_10; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* GPIOD configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_3 | GPIO_PIN_6; + HAL_GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* GPIOF configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_10; + HAL_GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* GPIOG configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7 | \ + GPIO_PIN_11; + HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* GPIOB configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1; + GPIO_InitStructure.Alternate= GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* GPIOG configuration */ + GPIO_InitStructure.Pin = GPIO_PIN_10 | GPIO_PIN_12; + HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); +} + +/** + * @brief SPIx error treatment function. + */ +static void SPIx_Error(void) +{ + /* De-initialize the SPI communication BUS */ + HAL_SPI_DeInit(&hspi5); + + /* Re- Initialize the SPI communication BUS */ + /* SPI5 parameter configuration*/ + hspi5.Instance = SPI5; + hspi5.Init.Mode = SPI_MODE_MASTER; + hspi5.Init.Direction = SPI_DIRECTION_2LINES; + hspi5.Init.DataSize = SPI_DATASIZE_8BIT; + hspi5.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi5.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi5.Init.NSS = SPI_NSS_SOFT; + hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi5.Init.TIMode = SPI_TIMODE_DISABLE; + hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi5.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi5) != HAL_OK) + { + //_Error_Handler(__FILE__, __LINE__); + } +} + +/** + * @brief Writes a byte to device. + * @param Value: value to be written + */ +static void SPIx_Write(uint16_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + + status = HAL_SPI_Transmit(&hspi5, (uint8_t*) &Value, 1, 0x1000); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Re-Initialize the BUS */ + SPIx_Error(); + } +} + +/** + * @brief Reads 4 bytes from device. + * @param ReadSize: Number of bytes to read (max 4 bytes) + * @retval Value read on the SPI + */ +static uint32_t SPIx_Read(uint8_t ReadSize) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t readvalue; + + status = HAL_SPI_Receive(&hspi5, (uint8_t*) &readvalue, ReadSize, 0x1000); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Re-Initialize the BUS */ + SPIx_Error(); + } + + return readvalue; +} + +/** + * @brief Configures the LCD_SPI interface. + */ +void LCD_IO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + + /* Configure NCS in Output Push-Pull mode */ + LCD_WRX_GPIO_CLK_ENABLE(); + GPIO_InitStructure.Pin = LCD_WRX_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(LCD_WRX_GPIO_PORT, &GPIO_InitStructure); + + LCD_RDX_GPIO_CLK_ENABLE(); + GPIO_InitStructure.Pin = LCD_RDX_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(LCD_RDX_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the LCD Control pins ----------------------------------------*/ + LCD_NCS_GPIO_CLK_ENABLE(); + + /* Configure NCS in Output Push-Pull mode */ + GPIO_InitStructure.Pin = LCD_NCS_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); + + /* Set or Reset the control line */ + LCD_CS_LOW(); + LCD_CS_HIGH(); + + /* SPI configuration -----------------------------------------------------*/ + SpiHandle.Instance = DISCOVERY_SPIx; + /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz) + to verify these constraints: + - ILI9341 LCD SPI interface max baudrate is 10MHz for write and 6.66MHz for read + - l3gd20 SPI interface max baudrate is 10MHz for write/read + - PCLK2 frequency is set to 90 MHz + */ + SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + + /* On STM32F429I-Discovery, LCD ID cannot be read then keep a common configuration */ + /* for LCD and GYRO (SPI_DIRECTION_2LINES) */ + /* Note: To read a register a LCD, SPI_DIRECTION_1LINE should be set */ + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE; + SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW; + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + SpiHandle.Init.CRCPolynomial = 7; + SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT; + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + SpiHandle.Init.NSS = SPI_NSS_SOFT; + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; + SpiHandle.Init.Mode = SPI_MODE_MASTER; + + SPIx_MspInit(&SpiHandle); + HAL_SPI_Init(&SpiHandle); + +} + +/** + * @brief Writes to the selected LCD register. + * @param LCD_Reg: address of the selected register. + * @retval None + */ +void ili9341_WriteReg(uint8_t LCD_Reg) +{ + /* Reset WRX to send command */ + LCD_WRX_LOW(); + + /* Reset LCD control line(/CS) and Send command */ + LCD_CS_LOW(); + SPIx_Write(LCD_Reg); + + /* Deselect: Chip Select high */ + LCD_CS_HIGH(); +} + +/** + * @brief Writes data to the selected LCD register. + * @param LCD_Reg: address of the selected register. + * @retval None + */ +void ili9341_WriteData(uint16_t RegValue) +{ + /* Set WRX to send data */ + LCD_WRX_HIGH(); + + /* Reset LCD control line(/CS) and Send data */ + LCD_CS_LOW(); + SPIx_Write(RegValue); + + /* Deselect: Chip Select high */ + LCD_CS_HIGH(); +} + +/** + * @brief Reads the selected LCD Register. + * @param RegValue: Address of the register to read + * @param ReadSize: Number of bytes to read + * @retval LCD Register Value. + */ +uint32_t ili9341_ReadData(uint16_t RegValue, uint8_t ReadSize) +{ + uint32_t readvalue = 0; + + /* Select: Chip Select low */ + LCD_CS_LOW(); + + /* Reset WRX to send command */ + LCD_WRX_LOW(); + + SPIx_Write(RegValue); + + readvalue = SPIx_Read(ReadSize); + + /* Set WRX to send data */ + LCD_WRX_HIGH(); + + /* Deselect: Chip Select high */ + LCD_CS_HIGH(); + + return readvalue; +} + +/** + * @brief Enables the Display. + */ +void BSP_LCD_DisplayOn(void) +{ + /* Display On */ + ili9341_WriteReg(LCD_DISPLAY_ON); +} + +/** + * @brief Disables the Display. + */ +void BSP_LCD_DisplayOff(void) +{ + /* Display Off */ + ili9341_WriteReg(LCD_DISPLAY_OFF); +} + +void ili9341_Init(void) +{ + /* Initialize ILI9341 low level bus layer ----------------------------------*/ + LCD_IO_Init(); + + /* Configure LCD */ + ili9341_WriteReg(0xCA); + ili9341_WriteData(0xC3); + ili9341_WriteData(0x08); + ili9341_WriteData(0x50); + ili9341_WriteReg(LCD_POWERB); + ili9341_WriteData(0x00); + ili9341_WriteData(0xC1); + ili9341_WriteData(0x30); + ili9341_WriteReg(LCD_POWER_SEQ); + ili9341_WriteData(0x64); + ili9341_WriteData(0x03); + ili9341_WriteData(0x12); + ili9341_WriteData(0x81); + ili9341_WriteReg(LCD_DTCA); + ili9341_WriteData(0x85); + ili9341_WriteData(0x00); + ili9341_WriteData(0x78); + ili9341_WriteReg(LCD_POWERA); + ili9341_WriteData(0x39); + ili9341_WriteData(0x2C); + ili9341_WriteData(0x00); + ili9341_WriteData(0x34); + ili9341_WriteData(0x02); + ili9341_WriteReg(LCD_PRC); + ili9341_WriteData(0x20); + ili9341_WriteReg(LCD_DTCB); + ili9341_WriteData(0x00); + ili9341_WriteData(0x00); + ili9341_WriteReg(LCD_FRMCTR1); + ili9341_WriteData(0x00); + ili9341_WriteData(0x1B); + ili9341_WriteReg(LCD_DFC); + ili9341_WriteData(0x0A); + ili9341_WriteData(0xA2); + ili9341_WriteReg(LCD_POWER1); + ili9341_WriteData(0x10); + ili9341_WriteReg(LCD_POWER2); + ili9341_WriteData(0x10); + ili9341_WriteReg(LCD_VCOM1); + ili9341_WriteData(0x45); + ili9341_WriteData(0x15); + ili9341_WriteReg(LCD_VCOM2); + ili9341_WriteData(0x90); + ili9341_WriteReg(LCD_MAC); + ili9341_WriteData(0xC8); + ili9341_WriteReg(LCD_3GAMMA_EN); + ili9341_WriteData(0x00); + ili9341_WriteReg(LCD_RGB_INTERFACE); + ili9341_WriteData(0xC2); + ili9341_WriteReg(LCD_DFC); + ili9341_WriteData(0x0A); + ili9341_WriteData(0xA7); + ili9341_WriteData(0x27); + ili9341_WriteData(0x04); + + /* Colomn address set */ + ili9341_WriteReg(LCD_COLUMN_ADDR); + ili9341_WriteData(0x00); + ili9341_WriteData(0x00); + ili9341_WriteData(0x00); + ili9341_WriteData(0xEF); + /* Page address set */ + ili9341_WriteReg(LCD_PAGE_ADDR); + ili9341_WriteData(0x00); + ili9341_WriteData(0x00); + ili9341_WriteData(0x01); + ili9341_WriteData(0x3F); + ili9341_WriteReg(LCD_INTERFACE); + ili9341_WriteData(0x01); + ili9341_WriteData(0x00); + ili9341_WriteData(0x06); + + ili9341_WriteReg(LCD_GRAM); + delay_ms(200); + + ili9341_WriteReg(LCD_GAMMA); + ili9341_WriteData(0x01); + + ili9341_WriteReg(LCD_PGAMMA); + ili9341_WriteData(0x0F); + ili9341_WriteData(0x29); + ili9341_WriteData(0x24); + ili9341_WriteData(0x0C); + ili9341_WriteData(0x0E); + ili9341_WriteData(0x09); + ili9341_WriteData(0x4E); + ili9341_WriteData(0x78); + ili9341_WriteData(0x3C); + ili9341_WriteData(0x09); + ili9341_WriteData(0x13); + ili9341_WriteData(0x05); + ili9341_WriteData(0x17); + ili9341_WriteData(0x11); + ili9341_WriteData(0x00); + ili9341_WriteReg(LCD_NGAMMA); + ili9341_WriteData(0x00); + ili9341_WriteData(0x16); + ili9341_WriteData(0x1B); + ili9341_WriteData(0x04); + ili9341_WriteData(0x11); + ili9341_WriteData(0x07); + ili9341_WriteData(0x31); + ili9341_WriteData(0x33); + ili9341_WriteData(0x42); + ili9341_WriteData(0x05); + ili9341_WriteData(0x0C); + ili9341_WriteData(0x0A); + ili9341_WriteData(0x28); + ili9341_WriteData(0x2F); + ili9341_WriteData(0x0F); + + ili9341_WriteReg(LCD_SLEEP_OUT); + delay_ms(200); + ili9341_WriteReg(LCD_DISPLAY_ON); + /* GRAM start writing */ + ili9341_WriteReg(LCD_GRAM); +} + +/** + * @brief Initializes the LCD layers. + * @param LayerIndex: the layer foreground or background. + * @param FB_Address: the layer frame buffer. + */ +void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address) +{ + LTDC_LayerCfgTypeDef Layercfg; + + /* Layer Init */ + Layercfg.WindowX0 = 0; + Layercfg.WindowX1 = 240; + Layercfg.WindowY0 = 0; + Layercfg.WindowY1 = 320; + Layercfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; + Layercfg.FBStartAdress = FB_Address; + Layercfg.Alpha = 255; + Layercfg.Alpha0 = 0; + Layercfg.Backcolor.Blue = 0; + Layercfg.Backcolor.Green = 0; + Layercfg.Backcolor.Red = 0; + Layercfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + Layercfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + Layercfg.ImageWidth = 240; + Layercfg.ImageHeight = 320; + + HAL_LTDC_ConfigLayer(&LtdcHandler, &Layercfg, LayerIndex); + + //DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE; + //DrawProp[LayerIndex].pFont = &Font24; + //DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK; + + /* Dithering activation */ + HAL_LTDC_EnableDither(&LtdcHandler); +} + +uint8_t BSP_LCD_Init(void) +{ + /* On STM32F429I-DISCO, it is not possible to read ILI9341 ID because */ + /* PIN EXTC is not connected to VDD and then LCD_READ_ID4 is not accessible. */ + /* In this case, ReadID function is bypassed.*/ + /*if(ili9341_drv.ReadID() == ILI9341_ID)*/ + + /* LTDC Configuration ----------------------------------------------------*/ + LtdcHandler.Instance = LTDC; + + /* Timing configuration (Typical configuration from ILI9341 datasheet) + HSYNC=10 (9+1) + HBP=20 (29-10+1) + ActiveW=240 (269-20-10+1) + HFP=10 (279-240-20-10+1) + + VSYNC=2 (1+1) + VBP=2 (3-2+1) + ActiveH=320 (323-2-2+1) + VFP=4 (327-320-2-2+1) + */ + + /* Configure horizontal synchronization width */ + LtdcHandler.Init.HorizontalSync = ILI9341_HSYNC; + /* Configure vertical synchronization height */ + LtdcHandler.Init.VerticalSync = ILI9341_VSYNC; + /* Configure accumulated horizontal back porch */ + LtdcHandler.Init.AccumulatedHBP = ILI9341_HBP; + /* Configure accumulated vertical back porch */ + LtdcHandler.Init.AccumulatedVBP = ILI9341_VBP; + /* Configure accumulated active width */ + LtdcHandler.Init.AccumulatedActiveW = 269; + /* Configure accumulated active height */ + LtdcHandler.Init.AccumulatedActiveH = 323; + /* Configure total width */ + LtdcHandler.Init.TotalWidth = 279; + /* Configure total height */ + LtdcHandler.Init.TotalHeigh = 327; + + /* Configure R,G,B component values for LCD background color */ + LtdcHandler.Init.Backcolor.Red= 0; + LtdcHandler.Init.Backcolor.Blue= 0; + LtdcHandler.Init.Backcolor.Green= 0; + + /* LCD clock configuration */ + /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */ + /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/4 = 48 Mhz */ + /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_8 = 48/4 = 6Mhz */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 4; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Polarity */ + LtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL; + LtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL; + LtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL; + LtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + + BSP_LCD_MspInit(); + HAL_LTDC_Init(&LtdcHandler); + + /* Select the device */ + //LcdDrv = &ili9341_drv; + + /* LCD Init */ + ili9341_Init(); + + /* Initialize the SDRAM */ + //BSP_SDRAM_Init(); + + /* Initialize the font */ + //BSP_LCD_SetFont(&LCD_DEFAULT_FONT); + + return 0; +} + +void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code) +{ + /* Write data value to all SDRAM memory */ + *(__IO uint32_t*) (LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*240 + Xpos))) = RGB_Code; +} + +void BSP_LCD_DrawLine(uint32_t pixel, uint16_t X1, uint16_t Y1, uint16_t X2, uint16_t Y2) +{ + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, + curpixel = 0; + + deltax = ABS(X2 - X1); /* The difference between the x's */ + deltay = ABS(Y2 - Y1); /* The difference between the y's */ + x = X1; /* Start x off at the first pixel */ + y = Y1; /* Start y off at the first pixel */ + + if (X2 >= X1) /* The x-values are increasing */ + { + xinc1 = 1; + xinc2 = 1; + } + else /* The x-values are decreasing */ + { + xinc1 = -1; + xinc2 = -1; + } + + if (Y2 >= Y1) /* The y-values are increasing */ + { + yinc1 = 1; + yinc2 = 1; + } + else /* The y-values are decreasing */ + { + yinc1 = -1; + yinc2 = -1; + } + + if (deltax >= deltay) /* There is at least one x-value for every y-value */ + { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + yinc2 = 0; /* Don't change the y for every iteration */ + den = deltax; + num = deltax / 2; + numadd = deltay; + numpixels = deltax; /* There are more x-values than y-values */ + } + else /* There is at least one y-value for every x-value */ + { + xinc2 = 0; /* Don't change the x for every iteration */ + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + den = deltay; + num = deltay / 2; + numadd = deltax; + numpixels = deltay; /* There are more y-values than x-values */ + } + + for (curpixel = 0; curpixel <= numpixels; curpixel++) + { + BSP_LCD_DrawPixel(x, y, pixel); /* Draw the current pixel */ + num += numadd; /* Increase the numerator by the top of the fraction */ + if (num >= den) /* Check if numerator >= denominator */ + { + num -= den; /* Calculate the new numerator value */ + x += xinc1; /* Change the x as appropriate */ + y += yinc1; /* Change the y as appropriate */ + } + x += xinc2; /* Change the x as appropriate */ + y += yinc2; /* Change the y as appropriate */ + } +} + +rt_uint16_t ili9341_bgr2rgb(rt_uint16_t value) +{ + rt_uint16_t red, green, blue; + + blue = (value >> 0) & 0x1f; + green = (value >> 5) & 0x3f; + red = (value >> 11) & 0x1f; + + return (blue << 11) + (green << 5) + (red << 0); +} + +void _lcd_low_level_init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, CSX_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET); + + + /*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */ + GPIO_InitStruct.Pin = CSX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */ + GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + + BSP_LCD_Init(); + BSP_LCD_LayerDefaultInit(0,0xD0000000); + BSP_LCD_SelectLayer(0); + BSP_LCD_DisplayOn(); + lcddev.width = 240; + lcddev.height = 320; + //ili9341_set_display_direction(0); + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); +} + + +static rt_err_t lcd_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t lcd_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t lcd_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t lcd_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info *info; + + info = (struct rt_device_graphic_info*) args; + RT_ASSERT(info != RT_NULL); + + info->bits_per_pixel = 16; + info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + info->framebuffer = (rt_uint8_t *)LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress; + info->width = 240; + info->height = 320; + } + break; + + case RTGRAPHIC_CTRL_RECT_UPDATE: + /* nothong to be done */ + break; + + default: + break; + } + + return RT_EOK; +} + +static void ili9341_lcd_set_pixel(const char* pixel, int x, int y) +{ + *(__IO uint16_t*)(LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(y * 240 + x))) = *(uint16_t *)pixel; +} +#ifdef RT_USING_FINSH +static void lcd_set_pixel(uint16_t color, int x, int y) +{ + rt_kprintf("lcd set pixel, color: %X, x: %d, y: %d", color, x, y); + ili9341_lcd_set_pixel((const char *)&color, x, y); +} +FINSH_FUNCTION_EXPORT(lcd_set_pixel, set pixel in lcd display); +#endif + +static void ili9341_lcd_get_pixel(char* pixel, int x, int y) +{ + uint32_t ret = 0; + + if(LtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + /* Read data value from SDRAM memory */ + ret = *(__IO uint32_t*) (LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(y * 240 + x))); + } + else if(LtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + /* Read data value from SDRAM memory */ + ret = (*(__IO uint32_t*) (LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(y*240 + x))) & 0x00FFFFFF); + } + else if((LtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (LtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (LtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + /* Read data value from SDRAM memory */ + ret = *(__IO uint16_t*) (LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(y*240 + x))); + } + else + { + /* Read data value from SDRAM memory */ + ret = *(__IO uint8_t*) (LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(y*240 + x))); + } + + *pixel = ret; +} +#ifdef RT_USING_FINSH +static void lcd_get_pixel(int x, int y) +{ + uint16_t pixel; + ili9341_lcd_get_pixel((char *)&pixel, x, y); + rt_kprintf("lcd get pixel, pixel: 0x%X, x: %d, y: %d", pixel, x, y); +} +FINSH_FUNCTION_EXPORT(lcd_get_pixel, get pixel in lcd display); +#endif + +static void ili9341_lcd_draw_hline(const char* pixel, int x1, int x2, int y) +{ + BSP_LCD_DrawLine(*pixel, x1, y, x2, y); +} +#ifdef RT_USING_FINSH +static void lcd_draw_hline(uint16_t pixel, int x1, int x2, int y) +{ + ili9341_lcd_draw_hline((const char *)&pixel, x1, x2, y); + rt_kprintf("lcd draw hline, pixel: 0x%X, x1: %d, x2: %d, y: %d", pixel, x1, x2, y); +} +FINSH_FUNCTION_EXPORT(lcd_draw_hline, draw hline in lcd display); +#endif + +static void ili9341_lcd_draw_vline(const char* pixel, int x, int y1, int y2) +{ + BSP_LCD_DrawLine(*pixel, x, y1, x, y2); +} +#ifdef RT_USING_FINSH +static void lcd_draw_vline(uint16_t pixel, int x, int y1, int y2) +{ + ili9341_lcd_draw_vline((const char *)&pixel, x, y1, y2); + rt_kprintf("lcd draw hline, pixel: 0x%X, x: %d, y: %d", pixel, y1, y2); +} +FINSH_FUNCTION_EXPORT(lcd_draw_vline, draw vline in lcd display); +#endif + +static void ili9341_lcd_blit_line(const char* pixels, int x, int y, rt_size_t size) +{ + int i = 0; + while(size--) + *(__IO uint16_t*) (LtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(y*240 + x + i++))) = *(uint16_t *)pixels++; +} +#ifdef RT_USING_FINSH +#define LINE_LEN 30 +static void lcd_blit_line(int x, int y) +{ + uint16_t pixels[LINE_LEN]; + int i; + + for (i = 0; i < LINE_LEN; i++) + { + pixels[i] = i * 40 + 50; + } + + ili9341_lcd_blit_line((const char *)pixels, x, y, LINE_LEN); + rt_kprintf("lcd blit line, x: %d, y: %d", x, y); +} +FINSH_FUNCTION_EXPORT(lcd_blit_line, draw blit line in lcd display); +#endif + +static int rt_hw_lcd_init(void) +{ + _lcd_low_level_init(); + + static struct rt_device lcd_device; + + static struct rt_device_graphic_ops ili9341_ops = + { + ili9341_lcd_set_pixel, + ili9341_lcd_get_pixel, + ili9341_lcd_draw_hline, + ili9341_lcd_draw_vline, + ili9341_lcd_blit_line + }; + + /* register lcd device */ + lcd_device.type = RT_Device_Class_Graphic; + lcd_device.init = lcd_init; + lcd_device.open = lcd_open; + lcd_device.close = lcd_close; + lcd_device.control = lcd_control; + lcd_device.read = RT_NULL; + lcd_device.write = RT_NULL; + + lcd_device.user_data = &ili9341_ops; + + /* register graphic device driver */ + rt_device_register(&lcd_device, "lcd", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_lcd_init); diff --git a/bsp/stm32f429-disco/drivers/drv_lcd.h b/bsp/stm32f429-disco/drivers/drv_lcd.h new file mode 100644 index 0000000000..4cde98eb55 --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_lcd.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-13 xuzhuoyi first implementation + */ + +#ifndef __DRV_LCD_H__ +#define __DRV_LCD_H__ + +#include +#include "stm32f4xx_hal.h" + +#define ILI9341_HSYNC ((uint32_t)9) /* Horizontal synchronization */ +#define ILI9341_HBP ((uint32_t)29) /* Horizontal back porch */ +#define ILI9341_HFP ((uint32_t)2) /* Horizontal front porch */ +#define ILI9341_VSYNC ((uint32_t)1) /* Vertical synchronization */ +#define ILI9341_VBP ((uint32_t)3) /* Vertical back porch */ +#define ILI9341_VFP ((uint32_t)2) /* Vertical front porch */ + + +/** + * @brief ILI9341 Registers + */ + +/* Level 1 Commands */ +#define LCD_SWRESET 0x01 /* Software Reset */ +#define LCD_READ_DISPLAY_ID 0x04 /* Read display identification information */ +#define LCD_RDDST 0x09 /* Read Display Status */ +#define LCD_RDDPM 0x0A /* Read Display Power Mode */ +#define LCD_RDDMADCTL 0x0B /* Read Display MADCTL */ +#define LCD_RDDCOLMOD 0x0C /* Read Display Pixel Format */ +#define LCD_RDDIM 0x0D /* Read Display Image Format */ +#define LCD_RDDSM 0x0E /* Read Display Signal Mode */ +#define LCD_RDDSDR 0x0F /* Read Display Self-Diagnostic Result */ +#define LCD_SPLIN 0x10 /* Enter Sleep Mode */ +#define LCD_SLEEP_OUT 0x11 /* Sleep out register */ +#define LCD_PTLON 0x12 /* Partial Mode ON */ +#define LCD_NORMAL_MODE_ON 0x13 /* Normal Display Mode ON */ +#define LCD_DINVOFF 0x20 /* Display Inversion OFF */ +#define LCD_DINVON 0x21 /* Display Inversion ON */ +#define LCD_GAMMA 0x26 /* Gamma register */ +#define LCD_DISPLAY_OFF 0x28 /* Display off register */ +#define LCD_DISPLAY_ON 0x29 /* Display on register */ +#define LCD_COLUMN_ADDR 0x2A /* Colomn address register */ +#define LCD_PAGE_ADDR 0x2B /* Page address register */ +#define LCD_GRAM 0x2C /* GRAM register */ +#define LCD_RGBSET 0x2D /* Color SET */ +#define LCD_RAMRD 0x2E /* Memory Read */ +#define LCD_PLTAR 0x30 /* Partial Area */ +#define LCD_VSCRDEF 0x33 /* Vertical Scrolling Definition */ +#define LCD_TEOFF 0x34 /* Tearing Effect Line OFF */ +#define LCD_TEON 0x35 /* Tearing Effect Line ON */ +#define LCD_MAC 0x36 /* Memory Access Control register*/ +#define LCD_VSCRSADD 0x37 /* Vertical Scrolling Start Address */ +#define LCD_IDMOFF 0x38 /* Idle Mode OFF */ +#define LCD_IDMON 0x39 /* Idle Mode ON */ +#define LCD_PIXEL_FORMAT 0x3A /* Pixel Format register */ +#define LCD_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */ +#define LCD_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */ +#define LCD_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */ +#define LCD_GET_SCANLINE 0x45 /* Get Scanline */ +#define LCD_WDB 0x51 /* Write Brightness Display register */ +#define LCD_RDDISBV 0x52 /* Read Display Brightness */ +#define LCD_WCD 0x53 /* Write Control Display register*/ +#define LCD_RDCTRLD 0x54 /* Read CTRL Display */ +#define LCD_WRCABC 0x55 /* Write Content Adaptive Brightness Control */ +#define LCD_RDCABC 0x56 /* Read Content Adaptive Brightness Control */ +#define LCD_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */ +#define LCD_READ_CABC 0x5F /* Read CABC Minimum Brightness */ +#define LCD_READ_ID1 0xDA /* Read ID1 */ +#define LCD_READ_ID2 0xDB /* Read ID2 */ +#define LCD_READ_ID3 0xDC /* Read ID3 */ + +/* Level 2 Commands */ +#define LCD_RGB_INTERFACE 0xB0 /* RGB Interface Signal Control */ +#define LCD_FRMCTR1 0xB1 /* Frame Rate Control (In Normal Mode) */ +#define LCD_FRMCTR2 0xB2 /* Frame Rate Control (In Idle Mode) */ +#define LCD_FRMCTR3 0xB3 /* Frame Rate Control (In Partial Mode) */ +#define LCD_INVTR 0xB4 /* Display Inversion Control */ +#define LCD_BPC 0xB5 /* Blanking Porch Control register */ +#define LCD_DFC 0xB6 /* Display Function Control register */ +#define LCD_ETMOD 0xB7 /* Entry Mode Set */ +#define LCD_BACKLIGHT1 0xB8 /* Backlight Control 1 */ +#define LCD_BACKLIGHT2 0xB9 /* Backlight Control 2 */ +#define LCD_BACKLIGHT3 0xBA /* Backlight Control 3 */ +#define LCD_BACKLIGHT4 0xBB /* Backlight Control 4 */ +#define LCD_BACKLIGHT5 0xBC /* Backlight Control 5 */ +#define LCD_BACKLIGHT7 0xBE /* Backlight Control 7 */ +#define LCD_BACKLIGHT8 0xBF /* Backlight Control 8 */ +#define LCD_POWER1 0xC0 /* Power Control 1 register */ +#define LCD_POWER2 0xC1 /* Power Control 2 register */ +#define LCD_VCOM1 0xC5 /* VCOM Control 1 register */ +#define LCD_VCOM2 0xC7 /* VCOM Control 2 register */ +#define LCD_NVMWR 0xD0 /* NV Memory Write */ +#define LCD_NVMPKEY 0xD1 /* NV Memory Protection Key */ +#define LCD_RDNVM 0xD2 /* NV Memory Status Read */ +#define LCD_READ_ID4 0xD3 /* Read ID4 */ +#define LCD_PGAMMA 0xE0 /* Positive Gamma Correction register */ +#define LCD_NGAMMA 0xE1 /* Negative Gamma Correction register */ +#define LCD_DGAMCTRL1 0xE2 /* Digital Gamma Control 1 */ +#define LCD_DGAMCTRL2 0xE3 /* Digital Gamma Control 2 */ +#define LCD_INTERFACE 0xF6 /* Interface control register */ + +/* Extend register commands */ +#define LCD_POWERA 0xCB /* Power control A register */ +#define LCD_POWERB 0xCF /* Power control B register */ +#define LCD_DTCA 0xE8 /* Driver timing control A */ +#define LCD_DTCB 0xEA /* Driver timing control B */ +#define LCD_POWER_SEQ 0xED /* Power on sequence register */ +#define LCD_3GAMMA_EN 0xF2 /* 3 Gamma enable register */ +#define LCD_PRC 0xF7 /* Pump ratio control register */ + +/* Size of read registers */ +#define LCD_READ_ID4_SIZE 3 /* Size of Read ID4 */ + +#define ABS(X) ((X) > 0 ? (X) : -(X)) + +#define CSX_Pin GPIO_PIN_2 +#define CSX_GPIO_Port GPIOC +#define RDX_Pin GPIO_PIN_12 +#define RDX_GPIO_Port GPIOD +#define WRX_DCX_Pin GPIO_PIN_13 +#define WRX_DCX_GPIO_Port GPIOD + +/* Chip Select macro definition */ +#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_RESET) +#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_SET) + +/* Set WRX High to send data */ +#define LCD_WRX_LOW() HAL_GPIO_WritePin(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PIN_RESET) +#define LCD_WRX_HIGH() HAL_GPIO_WritePin(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PIN_SET) + +/* Set WRX High to send data */ +#define LCD_RDX_LOW() HAL_GPIO_WritePin(LCD_RDX_GPIO_PORT, LCD_RDX_PIN, GPIO_PIN_RESET) +#define LCD_RDX_HIGH() HAL_GPIO_WritePin(LCD_RDX_GPIO_PORT, LCD_RDX_PIN, GPIO_PIN_SET) + +/** + * @brief LCD Control pin + */ +#define LCD_NCS_PIN GPIO_PIN_2 +#define LCD_NCS_GPIO_PORT GPIOC +#define LCD_NCS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LCD_NCS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() +/** + * @} + */ +/** + * @brief LCD Command/data pin + */ +#define LCD_WRX_PIN GPIO_PIN_13 +#define LCD_WRX_GPIO_PORT GPIOD +#define LCD_WRX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define LCD_WRX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() + +#define LCD_RDX_PIN GPIO_PIN_12 +#define LCD_RDX_GPIO_PORT GPIOD +#define LCD_RDX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define LCD_RDX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() + +/*############################### SPIx #######################################*/ +#define DISCOVERY_SPIx SPI5 +#define DISCOVERY_SPIx_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE() +#define DISCOVERY_SPIx_GPIO_PORT GPIOF /* GPIOF */ +#define DISCOVERY_SPIx_AF GPIO_AF5_SPI5 +#define DISCOVERY_SPIx_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() +#define DISCOVERY_SPIx_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() +#define DISCOVERY_SPIx_SCK_PIN GPIO_PIN_7 /* PF.07 */ +#define DISCOVERY_SPIx_MISO_PIN GPIO_PIN_8 /* PF.08 */ +#define DISCOVERY_SPIx_MOSI_PIN GPIO_PIN_9 /* PF.09 */ +/* Maximum Timeout values for flags waiting loops. These timeouts are not based + on accurate values, they just guarantee that the application will not remain + stuck if the SPI communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...). */ +#define SPIx_TIMEOUT_MAX ((uint32_t)0x1000) + +int rt_lcd_init(void); + +#endif + + + + + diff --git a/bsp/stm32f429-disco/drivers/drv_sdram.c b/bsp/stm32f429-disco/drivers/drv_sdram.c index 529cfb51b8..095f8dd0bc 100644 --- a/bsp/stm32f429-disco/drivers/drv_sdram.c +++ b/bsp/stm32f429-disco/drivers/drv_sdram.c @@ -1,21 +1,7 @@ /* - * File : drv_sdram.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-disco/drivers/drv_sdram.h b/bsp/stm32f429-disco/drivers/drv_sdram.h index 67825f602d..7f70783ef9 100644 --- a/bsp/stm32f429-disco/drivers/drv_sdram.h +++ b/bsp/stm32f429-disco/drivers/drv_sdram.h @@ -1,11 +1,7 @@ /* - * File : drv_sdram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,7 +21,7 @@ #include -#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) +#define SDRAM_BANK_ADDR ((uint32_t)0xD0030000) /*0xD0000000-0xD002FFFF used for LCD framebuffer*/ /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 diff --git a/bsp/stm32f429-disco/drivers/drv_touch.c b/bsp/stm32f429-disco/drivers/drv_touch.c new file mode 100644 index 0000000000..ea60c858c5 --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_touch.c @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 xuzhuoyi first implementation. + */ + +#include "drv_touch.h" +#include "drivers/i2c.h" + +#ifdef PKG_USING_LITTLEVGL2RTT +#include "littlevgl2rtt.h" +#endif + + +#define TSC_I2C_ADDR 0x41 /* 7-bit I2C address */ + +static struct rt_i2c_bus_device *stmpe811_i2c_bus; + + +/** + \fn int32_t touch_readRegister (uint8_t reg, uint8_t *val) + \brief Read register value from Touchscreen controller + \param[in] reg Register address + \param[out] val Pointer where data will be read from register + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +static int32_t touch_read (uint8_t reg, uint8_t *val) +{ + struct rt_i2c_msg msgs[2]; + + msgs[0].addr = TSC_I2C_ADDR; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = ® + msgs[0].len = 1; + + msgs[1].addr = TSC_I2C_ADDR; + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = val; + msgs[1].len = 1; + + if (rt_i2c_transfer(stmpe811_i2c_bus, msgs, 2) == 2) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } + +} + +/** + \fn int32_t touch_writeData (uint8_t reg, const uint8_t *val) + \brief Write value to Touchscreen controller register + \param[in] reg Register address + \param[in] val Pointer with data to write to register + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +static int32_t touch_write(uint8_t reg, uint8_t val) +{ + struct rt_i2c_msg msgs; + rt_uint8_t buf[2] = {reg, val}; + + msgs.addr = TSC_I2C_ADDR; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = 2; + + if (rt_i2c_transfer(stmpe811_i2c_bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } + +} + + +/** + \fn int32_t Touch_Initialize (void) + \brief Initialize touchscreen + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +static rt_err_t stmpe811_touch_init(rt_device_t dev) +{ + stmpe811_i2c_bus = rt_i2c_bus_device_find("i2c3"); + + touch_write(STMPE811_SYS_CTRL1, 0x02); /* Reset Touch-screen controller */ + rt_thread_mdelay(10); /* Wait 10ms */ + + + touch_write(STMPE811_SYS_CTRL2, 0x0C); /* Enable TSC and ADC */ + touch_write(STMPE811_ADC_CTRL1, 0x68); /* Set sample time , 12-bit mode */ + rt_thread_mdelay(1); /* Wait 1ms */ + + touch_write(STMPE811_ADC_CTRL2, 0x01); /* ADC frequency 3.25 MHz */ + touch_write(STMPE811_TSC_CFG, 0xC2); /* Detect delay 10us, + Settle time 500us */ + touch_write(STMPE811_FIFO_TH, 0x01); /* Threshold for FIFO */ + touch_write(STMPE811_FIFO_STA, 0x01); /* FIFO reset */ + touch_write(STMPE811_FIFO_STA, 0x00); /* FIFO not reset */ + touch_write(STMPE811_TSC_FRACTION_Z, 0x07); /* Fraction z */ + touch_write(STMPE811_TSC_I_DRIVE, 0x01); /* Drive 50 mA typical */ + touch_write(STMPE811_GPIO_AF, 0x00); /* Pins are used for touchscreen */ + touch_write(STMPE811_TSC_CTRL, 0x01); /* Enable TSC */ + + return 0; +} + +/** + \fn int32_t Touch_Uninitialize (void) + \brief De-initialize touchscreen + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t touch_uninitialize (void) { + touch_write(STMPE811_SYS_CTRL1, 0x02); /* Reset Touch-screen controller */ + return 0; +} + +/** + \fn int32_t Touch_GetState (TOUCH_STATE *pState) + \brief Get touchscreen state + \param[out] pState pointer to TOUCH_STATE structure + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t touch_get_state(struct touch_state *state) +{ + uint8_t val; + uint8_t num; + uint8_t xyz[4]; + int32_t res; + struct rt_i2c_msg msgs[2]; + + /* Read touch status */ + res = touch_read(STMPE811_TSC_CTRL, &val); + if (res < 0) return -1; + state->pressed = (val & (1 << 7)) ? 1 : 0; + + if (state->pressed) + { + val = STMPE811_TSC_DATA; + + /* If FIFO overflow, discard all samples except the last one */ + res = touch_read(STMPE811_FIFO_SIZE, &num); + if (res < 0 || num == 0) return -1; + + while (num--) + { + msgs[0].addr = TSC_I2C_ADDR; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = &val; + msgs[0].len = 1; + + //rt_i2c_transfer(stmpe811_i2c_bus, &msgs, 1); + //ptrI2C->MasterTransmit (TSC_I2C_ADDR, &val, 1, true); + //while (ptrI2C->GetStatus().busy); + msgs[1].addr = TSC_I2C_ADDR; + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = xyz; + msgs[1].len = 4; + rt_i2c_transfer(stmpe811_i2c_bus, msgs, 2); + //ptrI2C->MasterReceive (TSC_I2C_ADDR, xyz, 4, false); + //while (ptrI2C->GetStatus().busy); + } + state->x = (int16_t)((xyz[0] << 4) | ((xyz[1] & 0xF0) >> 4)); + state->y = (int16_t) (xyz[2] | ((xyz[1] & 0x0F) << 8)); + } + else + { + /* Clear all data in FIFO */ + touch_write(STMPE811_FIFO_STA, 0x1); + touch_write(STMPE811_FIFO_STA, 0x0); + } + + return 0; +} + +void touch_show_state() +{ + int16_t x; + int16_t y; + struct touch_state ts; + touch_get_state(&ts); + x = (3706 - ts.x) / 14; + y = (-461 + ts.y) / 10.5; + rt_kprintf("[drv_touch] touch_show_state, x: %d, y: %d, pressed: %d, padding: %d\n", ts.x , ts.y, ts.pressed, ts.padding); + rt_kprintf("[drv_touch] touch_show_state, phy x: %d, phy y: %d\n", x , y); +} +MSH_CMD_EXPORT(touch_show_state, show screen coordinate in touching); + +static int rt_hw_touch_init(void) +{ + static struct rt_device touch; + + /* init device structure */ + touch.type = RT_Device_Class_Unknown; + touch.init = stmpe811_touch_init; + touch.user_data = RT_NULL; + + /* register touch device to RT-Thread */ + rt_device_register(&touch, "touch", RT_DEVICE_FLAG_RDWR); + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_touch_init); diff --git a/bsp/stm32f429-disco/drivers/drv_touch.h b/bsp/stm32f429-disco/drivers/drv_touch.h new file mode 100644 index 0000000000..68c8f92b7f --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_touch.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 xuzhuoyi first implementation. + */ + +#ifndef __DRV_TOUCH_H__ +#define __DRV_TOUCH_H__ + +#include + +/* Register addresses */ +#define STMPE811_CHIP_ID 0x00 +#define STMPE811_ID_VER 0x02 +#define STMPE811_SYS_CTRL1 0x03 +#define STMPE811_SYS_CTRL2 0x04 +#define STMPE811_SPI_CFG 0x08 +#define STMPE811_INT_CTRL 0x09 +#define STMPE811_INT_EN 0x0A +#define STMPE811_INT_STA 0x0B +#define STMPE811_GPIO_EN 0x0C +#define STMPE811_GPIO_INT_STA 0x0D +#define STMPE811_ADC_INT_EN 0x0E +#define STMPE811_ADC_INT_STA 0x0F +#define STMPE811_GPIO_SET_PIN 0x10 +#define STMPE811_GPIO_CLR_PIN 0x11 +#define STMPE811_GPIO_MP_STA 0x12 +#define STMPE811_GPIO_DIR 0x13 +#define STMPE811_GPIO_ED 0x14 +#define STMPE811_GPIO_RE 0x15 +#define STMPE811_GPIO_FE 0x16 +#define STMPE811_GPIO_AF 0x17 +#define STMPE811_ADC_CTRL1 0x20 +#define STMPE811_ADC_CTRL2 0x21 +#define STMPE811_ADC_CAPT 0x22 +#define STMPE811_ADC_DATA_CH0 0x30 +#define STMPE811_ADC_DATA_CH1 0x32 +#define STMPE811_ADC_DATA_CH2 0x34 +#define STMPE811_ADC_DATA_CH3 0x36 +#define STMPE811_ADC_DATA_CH4 0x38 +#define STMPE811_ADC_DATA_CH5 0x3A +#define STMPE811_ADC_DATA_CH6 0x3C +#define STMPE811_ADC_DATA_CH7 0x3E +#define STMPE811_TSC_CTRL 0x40 +#define STMPE811_TSC_CFG 0x41 +#define STMPE811_WDW_TR_X 0x42 +#define STMPE811_WDW_TR_Y 0x44 +#define STMPE811_WDW_BL_X 0x46 +#define STMPE811_WDW_BL_Y 0x48 +#define STMPE811_FIFO_TH 0x4A +#define STMPE811_FIFO_STA 0x4B +#define STMPE811_FIFO_SIZE 0x4C +#define STMPE811_TSC_DATA_X 0x4D +#define STMPE811_TSC_DATA_Y 0x4F +#define STMPE811_TSC_DATA_Z 0x51 +#define STMPE811_TSC_FRACTION_Z 0x56 +#define STMPE811_TSC_DATA_XYZ 0x57 +#define STMPE811_TSC_DATA 0xD7 +#define STMPE811_TSC_I_DRIVE 0x58 +#define STMPE811_TSC_SHIELD 0x59 +#define STMPE811_TEMP_CTRL 0x60 +#define STMPE811_TEMP_DATA 0x61 +#define STMPE811_TEMP_TH 0x62 + +/* Touch state */ +struct touch_state { + int16_t x; ///< Position X + int16_t y; ///< Position Y + uint8_t pressed; ///< Pressed flag + uint8_t padding; +}; + +int32_t touch_get_state(struct touch_state *state); + +#endif /* __DRV_TOUCH_H__ */ diff --git a/bsp/stm32f429-disco/drivers/stm32f4xx_hal_conf.h b/bsp/stm32f429-disco/drivers/stm32f4xx_hal_conf.h index a010dda5e1..0bff765afe 100644 --- a/bsp/stm32f429-disco/drivers/stm32f4xx_hal_conf.h +++ b/bsp/stm32f429-disco/drivers/stm32f4xx_hal_conf.h @@ -68,12 +68,12 @@ /* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_LTDC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED /* #define HAL_USART_MODULE_ENABLED */ diff --git a/bsp/stm32f429-disco/drivers/usart.c b/bsp/stm32f429-disco/drivers/usart.c index 62a40df4ee..f7ba2ed277 100644 --- a/bsp/stm32f429-disco/drivers/usart.c +++ b/bsp/stm32f429-disco/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-disco/drivers/usart.h b/bsp/stm32f429-disco/drivers/usart.h index 3faf85fcde..12cfd253cf 100644 --- a/bsp/stm32f429-disco/drivers/usart.h +++ b/bsp/stm32f429-disco/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f429-disco/project.uvproj b/bsp/stm32f429-disco/project.uvproj index 26737e7aab..96e60d1f13 100644 --- a/bsp/stm32f429-disco/project.uvproj +++ b/bsp/stm32f429-disco/project.uvproj @@ -1,37 +1,42 @@ + 1.1 +
### uVision Project, (C) Keil Software
+ rt-thread_stm32f4xx 0x4 ARM-ADS + 6100001::V6.10.1::.\ARMCLANG + 1 STM32F429ZG STMicroelectronics IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 - + "Startup\ST\STM32F4xx\startup_stm32f429_439xx.s" ("STM32F429/439xx Startup Code") UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) 7029 stm32f4xx.h - - - - - - + + + + + + -DSTM32F429_439xx - - + + SFD\ST\STM32F4xx\STM32F429x.SFR 0 0 - - - + + + ST\STM32F4xx\ ST\STM32F4xx\ @@ -55,8 +60,8 @@ 0 0 - - + + 0 0 0 @@ -65,21 +70,25 @@ 0 0 - - + + 0 0 + 0 + 0 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 + 0 + 0 0 - + 0 @@ -93,8 +102,8 @@ 0 0 3 - - + + 1 @@ -138,23 +147,22 @@ 1 0 1 - 0 0 - 1 + 0 - - - - - + + + + + - - - - - + + + + + BIN\UL2CM3.DLL @@ -170,10 +178,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -206,7 +214,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -215,12 +223,14 @@ 0 0 2 + 0 1 0 8 0 0 0 + 0 3 3 0 @@ -337,11 +347,11 @@ 0x10000 - + 1 - 1 + 7 0 0 0 @@ -350,16 +360,24 @@ 0 0 0 - 0 + 3 0 0 0 + 0 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 - + USE_HAL_DRIVER, STM32F429xx - - drivers;applications;.;Libraries/STM32F4xx_HAL_Driver/Inc;Libraries/CMSIS/Device/ST/STM32F4xx/Include;Libraries/CMSIS/Include;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh + + applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh @@ -372,11 +390,12 @@ 0 0 0 + 0 - - - - + + + + @@ -388,62 +407,59 @@ 0 0x08000000 0x20000000 - - - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + - - Drivers - - - board.c - 1 - drivers/board.c - - - - - stm32f4xx_it.c - 1 - drivers/stm32f4xx_it.c - - - - - usart.c - 1 - drivers/usart.c - - - - - drv_sdram.c - 1 - drivers/drv_sdram.c - - - Applications application.c 1 - applications/application.c + applications\application.c - - startup.c 1 - applications/startup.c + applications\startup.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + stm32f4xx_it.c + 1 + drivers\stm32f4xx_it.c + + + usart.c + 1 + drivers\usart.c + + + drv_sdram.c + 1 + drivers\drv_sdram.c + + + drv_lcd.c + 1 + drivers\drv_lcd.c @@ -453,483 +469,347 @@ system_stm32f4xx.c 1 - Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c + Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - - stm32f4xx_hal.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - - stm32f4xx_hal_adc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c - - stm32f4xx_hal_adc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c - - stm32f4xx_hal_can.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c - - stm32f4xx_hal_cec.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c - - stm32f4xx_hal_cortex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - - stm32f4xx_hal_crc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - - stm32f4xx_hal_cryp.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c - - stm32f4xx_hal_cryp_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c - - stm32f4xx_hal_dac.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c - - stm32f4xx_hal_dac_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c - - stm32f4xx_hal_dcmi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c - - stm32f4xx_hal_dcmi_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c - - stm32f4xx_hal_dfsdm.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c - - stm32f4xx_hal_dma.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - - stm32f4xx_hal_dma2d.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c - - stm32f4xx_hal_dma_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - - stm32f4xx_hal_dsi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c - - stm32f4xx_hal_eth.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c - - stm32f4xx_hal_flash.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c - - stm32f4xx_hal_flash_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c - - stm32f4xx_hal_flash_ramfunc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c - - stm32f4xx_hal_fmpi2c.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c - - stm32f4xx_hal_fmpi2c_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c - - stm32f4xx_hal_gpio.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - - stm32f4xx_hal_hash.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c - - stm32f4xx_hal_hash_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c - - stm32f4xx_hal_hcd.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c - - stm32f4xx_hal_i2c.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c - - stm32f4xx_hal_i2c_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c - - stm32f4xx_hal_i2s.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c - - stm32f4xx_hal_i2s_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c - - stm32f4xx_hal_irda.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c - - stm32f4xx_hal_iwdg.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c - - stm32f4xx_hal_lptim.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c - - stm32f4xx_hal_ltdc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c - - stm32f4xx_hal_ltdc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c - - stm32f4xx_hal_nand.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c - - stm32f4xx_hal_nor.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c - - stm32f4xx_hal_pccard.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c - - stm32f4xx_hal_pcd.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c - - stm32f4xx_hal_pcd_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c - - stm32f4xx_hal_pwr.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - - stm32f4xx_hal_pwr_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - - stm32f4xx_hal_qspi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c - - stm32f4xx_hal_rcc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - - stm32f4xx_hal_rcc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - - stm32f4xx_hal_rng.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c - - stm32f4xx_hal_rtc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c - - stm32f4xx_hal_rtc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c - - stm32f4xx_hal_sai.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c - - stm32f4xx_hal_sai_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c - - stm32f4xx_hal_sd.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c - - stm32f4xx_hal_sdram.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c - - stm32f4xx_hal_smartcard.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c - - stm32f4xx_hal_spdifrx.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c - - stm32f4xx_hal_spi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c - - stm32f4xx_hal_sram.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c - - stm32f4xx_hal_tim.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c - - stm32f4xx_hal_tim_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c - - stm32f4xx_hal_uart.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - - stm32f4xx_hal_usart.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c - - stm32f4xx_hal_wwdg.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c - - stm32f4xx_ll_fmc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c - - stm32f4xx_ll_fsmc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c - - stm32f4xx_ll_sdmmc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c - - stm32f4xx_ll_usb.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c - - startup_stm32f429xx.s 2 - Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s + Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f429xx.s @@ -939,105 +819,77 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c - - components.c 1 - ../../src/components.c + ..\..\src\components.c - - device.c 1 - ../../src/device.c + ..\..\src\device.c - - idle.c 1 - ../../src/idle.c + ..\..\src\idle.c - - ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c - - irq.c 1 - ../../src/irq.c + ..\..\src\irq.c - - kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c - - mem.c 1 - ../../src/mem.c + ..\..\src\mem.c - - memheap.c 1 - ../../src/memheap.c + ..\..\src\memheap.c - - mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c - - object.c 1 - ../../src/object.c + ..\..\src\object.c - - scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c - - signal.c 1 - ../../src/signal.c + ..\..\src\signal.c - - thread.c 1 - ../../src/thread.c + ..\..\src\thread.c - - timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -1047,87 +899,102 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m4/cpuport.c + ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 - ../../libcpu/arm/cortex-m4/context_rvds.S + ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c - - showmem.c 1 - ../../libcpu/arm/common/showmem.c + ..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c DeviceDrivers + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + serial.c 1 - ../../components/drivers/serial/serial.c + ..\..\components\drivers\serial\serial.c - - completion.c 1 - ../../components/drivers/src/completion.c + ..\..\components\drivers\src\completion.c - - dataqueue.c 1 - ../../components/drivers/src/dataqueue.c + ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 - ../../components/drivers/src/pipe.c + ..\..\components\drivers\src\pipe.c - - ringbuffer.c 1 - ../../components/drivers/src/ringbuffer.c + ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 - ../../components/drivers/src/waitqueue.c + ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 - ../../components/drivers/src/workqueue.c + ..\..\components\drivers\src\workqueue.c @@ -1137,116 +1004,87 @@ shell.c 1 - ../../components/finsh/shell.c + ..\..\components\finsh\shell.c - - symbol.c 1 - ../../components/finsh/symbol.c + ..\..\components\finsh\symbol.c - - cmd.c 1 - ../../components/finsh/cmd.c + ..\..\components\finsh\cmd.c - - msh.c 1 - ../../components/finsh/msh.c + ..\..\components\finsh\msh.c - - msh_cmd.c 1 - ../../components/finsh/msh_cmd.c + ..\..\components\finsh\msh_cmd.c - - msh_file.c 1 - ../../components/finsh/msh_file.c + ..\..\components\finsh\msh_file.c - - finsh_compiler.c 1 - ../../components/finsh/finsh_compiler.c + ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 - ../../components/finsh/finsh_error.c + ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 - ../../components/finsh/finsh_heap.c + ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 - ../../components/finsh/finsh_init.c + ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 - ../../components/finsh/finsh_node.c + ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 - ../../components/finsh/finsh_ops.c + ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 - ../../components/finsh/finsh_parser.c + ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 - ../../components/finsh/finsh_var.c + ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 - ../../components/finsh/finsh_vm.c + ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 - ../../components/finsh/finsh_token.c + ..\..\components\finsh\finsh_token.c + diff --git a/bsp/stm32f429-disco/project.uvprojx b/bsp/stm32f429-disco/project.uvprojx index d6141cd54a..f251a79413 100644 --- a/bsp/stm32f429-disco/project.uvprojx +++ b/bsp/stm32f429-disco/project.uvprojx @@ -1,42 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt_thread_stm32f429 0x4 ARM-ADS - 5060300::V5.06 update 3 (build 300)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32F429ZITx STMicroelectronics - Keil.STM32F4xx_DFP.2.5.0 + Keil.STM32F4xx_DFP.2.13.0 http://www.keil.com/pack IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32F429ZITx$CMSIS\Flash\STM32F4xx_2048.FLM)) 0 $$Device:STM32F429ZITx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - - - + + + + + + + + + $$Device:STM32F429ZITx$CMSIS\SVD\STM32F429x.svd 0 0 - - - - - + + + + + 0 0 @@ -50,7 +54,7 @@ 0 0 1 - 1 + 0 .\Listings\ 1 0 @@ -58,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -78,15 +82,15 @@ 0 0 - - + + 0 0 0 0 0 - + 0 @@ -100,8 +104,8 @@ 0 0 3 - - + + 1 @@ -129,16 +133,16 @@ 0 0 1 - 0 + 1 -1 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -171,7 +175,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -180,6 +184,7 @@ 0 0 2 + 0 1 0 8 @@ -303,7 +308,7 @@ 0x10000 - + 1 @@ -320,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -329,10 +335,10 @@ 0 0 - - USE_HAL_DRIVER, STM32F429xx - - drivers;applications;.;Libraries/STM32F4xx_HAL_Driver/Inc;Libraries/CMSIS/Device/ST/STM32F4xx/Include;Libraries/CMSIS/Include;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh + + USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32F429xx + + applications;.;drivers;Libraries\STM32F4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc @@ -347,10 +353,10 @@ 0 0 - - - - + + + + @@ -362,62 +368,69 @@ 0 0x08000000 0x20000000 - - - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + - - Drivers - - - board.c - 1 - drivers/board.c - - - - - stm32f4xx_it.c - 1 - drivers/stm32f4xx_it.c - - - - - usart.c - 1 - drivers/usart.c - - - - - drv_sdram.c - 1 - drivers/drv_sdram.c - - - Applications application.c 1 - applications/application.c + applications\application.c - - startup.c 1 - applications/startup.c + applications\startup.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + stm32f4xx_it.c + 1 + drivers\stm32f4xx_it.c + + + usart.c + 1 + drivers\usart.c + + + drv_sdram.c + 1 + drivers\drv_sdram.c + + + drv_i2c.c + 1 + drivers\drv_i2c.c + + + drv_lcd.c + 1 + drivers\drv_lcd.c + + + drv_touch.c + 1 + drivers\drv_touch.c @@ -427,483 +440,347 @@ system_stm32f4xx.c 1 - Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c + Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - - stm32f4xx_hal.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - - stm32f4xx_hal_adc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c - - stm32f4xx_hal_adc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c - - stm32f4xx_hal_can.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c - - stm32f4xx_hal_cec.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c - - stm32f4xx_hal_cortex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - - stm32f4xx_hal_crc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - - stm32f4xx_hal_cryp.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c - - stm32f4xx_hal_cryp_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c - - stm32f4xx_hal_dac.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c - - stm32f4xx_hal_dac_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c - - stm32f4xx_hal_dcmi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c - - stm32f4xx_hal_dcmi_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c - - stm32f4xx_hal_dfsdm.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c - - stm32f4xx_hal_dma.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - - stm32f4xx_hal_dma2d.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c - - stm32f4xx_hal_dma_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - - stm32f4xx_hal_dsi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c - - stm32f4xx_hal_eth.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c - - stm32f4xx_hal_flash.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c - - stm32f4xx_hal_flash_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c - - stm32f4xx_hal_flash_ramfunc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c - - stm32f4xx_hal_fmpi2c.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c - - stm32f4xx_hal_fmpi2c_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c - - stm32f4xx_hal_gpio.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - - stm32f4xx_hal_hash.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c - - stm32f4xx_hal_hash_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash_ex.c - - stm32f4xx_hal_hcd.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c - - stm32f4xx_hal_i2c.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c - - stm32f4xx_hal_i2c_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c - - stm32f4xx_hal_i2s.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.c - - stm32f4xx_hal_i2s_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.c - - stm32f4xx_hal_irda.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_irda.c - - stm32f4xx_hal_iwdg.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c - - stm32f4xx_hal_lptim.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_lptim.c - - stm32f4xx_hal_ltdc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c - - stm32f4xx_hal_ltdc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c - - stm32f4xx_hal_nand.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nand.c - - stm32f4xx_hal_nor.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_nor.c - - stm32f4xx_hal_pccard.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pccard.c - - stm32f4xx_hal_pcd.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c - - stm32f4xx_hal_pcd_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c - - stm32f4xx_hal_pwr.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - - stm32f4xx_hal_pwr_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - - stm32f4xx_hal_qspi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c - - stm32f4xx_hal_rcc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - - stm32f4xx_hal_rcc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - - stm32f4xx_hal_rng.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c - - stm32f4xx_hal_rtc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c - - stm32f4xx_hal_rtc_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c - - stm32f4xx_hal_sai.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c - - stm32f4xx_hal_sai_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c - - stm32f4xx_hal_sd.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c - - stm32f4xx_hal_sdram.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c - - stm32f4xx_hal_smartcard.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c - - stm32f4xx_hal_spdifrx.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c - - stm32f4xx_hal_spi.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c - - stm32f4xx_hal_sram.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c - - stm32f4xx_hal_tim.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c - - stm32f4xx_hal_tim_ex.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c - - stm32f4xx_hal_uart.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - - stm32f4xx_hal_usart.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c - - stm32f4xx_hal_wwdg.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c - - stm32f4xx_ll_fmc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c - - stm32f4xx_ll_fsmc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c - - stm32f4xx_ll_sdmmc.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c - - stm32f4xx_ll_usb.c 1 - Libraries/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + Libraries\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c - - startup_stm32f429xx.s 2 - Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s + Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f429xx.s @@ -913,105 +790,77 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c - - components.c 1 - ../../src/components.c + ..\..\src\components.c - - device.c 1 - ../../src/device.c + ..\..\src\device.c - - idle.c 1 - ../../src/idle.c + ..\..\src\idle.c - - ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c - - irq.c 1 - ../../src/irq.c + ..\..\src\irq.c - - kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c - - mem.c 1 - ../../src/mem.c + ..\..\src\mem.c - - memheap.c 1 - ../../src/memheap.c + ..\..\src\memheap.c - - mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c - - object.c 1 - ../../src/object.c + ..\..\src\object.c - - scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c - - signal.c 1 - ../../src/signal.c + ..\..\src\signal.c - - thread.c 1 - ../../src/thread.c + ..\..\src\thread.c - - timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -1021,87 +870,132 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m4/cpuport.c + ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 - ../../libcpu/arm/cortex-m4/context_rvds.S + ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c - - showmem.c 1 - ../../libcpu/arm/common/showmem.c + ..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c DeviceDrivers + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + serial.c 1 - ../../components/drivers/serial/serial.c + ..\..\components\drivers\serial\serial.c - - completion.c 1 - ../../components/drivers/src/completion.c + ..\..\components\drivers\src\completion.c - - dataqueue.c 1 - ../../components/drivers/src/dataqueue.c + ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 - ../../components/drivers/src/pipe.c + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c - - ringbuffer.c 1 - ../../components/drivers/src/ringbuffer.c + ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 - ../../components/drivers/src/waitqueue.c + ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 - ../../components/drivers/src/workqueue.c + ..\..\components\drivers\src\workqueue.c @@ -1111,116 +1005,123 @@ shell.c 1 - ../../components/finsh/shell.c + ..\..\components\finsh\shell.c - - symbol.c 1 - ../../components/finsh/symbol.c + ..\..\components\finsh\symbol.c - - cmd.c 1 - ../../components/finsh/cmd.c + ..\..\components\finsh\cmd.c - - msh.c 1 - ../../components/finsh/msh.c + ..\..\components\finsh\msh.c - - msh_cmd.c 1 - ../../components/finsh/msh_cmd.c + ..\..\components\finsh\msh_cmd.c - - msh_file.c 1 - ../../components/finsh/msh_file.c + ..\..\components\finsh\msh_file.c - - finsh_compiler.c 1 - ../../components/finsh/finsh_compiler.c + ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 - ../../components/finsh/finsh_error.c + ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 - ../../components/finsh/finsh_heap.c + ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 - ../../components/finsh/finsh_init.c + ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 - ../../components/finsh/finsh_node.c + ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 - ../../components/finsh/finsh_ops.c + ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 - ../../components/finsh/finsh_parser.c + ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 - ../../components/finsh/finsh_var.c + ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 - ../../components/finsh/finsh_vm.c + ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 - ../../components/finsh/finsh_token.c + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c + + + + + + + diff --git a/bsp/stm32f429-disco/readme.md b/bsp/stm32f429-disco/readme.md index 3971dafdfa..66d55cfe51 100644 --- a/bsp/stm32f429-disco/readme.md +++ b/bsp/stm32f429-disco/readme.md @@ -1,12 +1,84 @@ -board info: -STM32F429I-DISC1 -http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/32f429idiscovery.html +# STM32F429-DISCO -note: -in drivers/stm32f4xx_conf.h - /* Redefine the HSE value; it's equal to 8 MHz on the STM32F429I-DISC1 Kit */ - #define HSE_VALUE ((uint32_t)8000000) +## 1. 简介 + +STM32F429I-DISCOVERY 开发板使用高性能 MCU STM32F429，可以用于实现高级图形用户界面。 +本 BSP 兼容 STM32F429I-DISCO 和 STM32F429I-DISC1 两个版本的 DISCOVERY 开发板。 + +核心板板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| STM32F429ZIT6 | +|CPU| ARM Cortex-M4F | +|主频| 180MHz | +|片内 SRAM| 256KB | +|片外 SDRAM| 64-Mbit SDRAM | +|片内 Flash| 2MB | +|显示设备| 2.4" QVGA TFT LCD| +|‎运动传感器‎| L3GD20 | +|LED| 6 个 | +|按键| 2 个 | + +本 BSP 已测试支持 RT-Thread GUIEngine 和 Littlevgl，可以使用 env 工具安装相应的 Package。 + +## 2. 编译说明 + +STM32F429-DISCO 板级包支持 MDK4﹑MDK5﹑IAR 开发环境和 GCC 编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| MDK4 | MDK4.74 | +| MDK5 | MDK V5.25.2.0 | +| IAR | 未测试 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 3. 烧写及执行 + +供电方式：使用 Mini USB 线连接电脑和板子的 USB ST-LINK 口。 + +串口连接：STM32F429I-DISC1 版本的开发板的板载调试器为 ST-LINK/V2-B，支持 VCP 虚拟串口，所以可以直接使用虚拟串口输出默认控制台设备 USART1。 + +老版本的 STM32F429I-DISCO 开发板需要从板子上的引脚外接串口，并更改控制台设备到相应 USART。 + +在PC上使用终端软件以115200-N-8-1的配置方式连接到对应的COM设备上。 + +STM32F429-DISCO/DISC1 使用板载编程器下载程序。 + +### 3.1 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到 RT-Thread 的启动 logo 信息： + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.0 build Aug 31 2018 + 2006 - 2018 Copyright by rt-thread team +finsh /> + +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| USART | 支持 | USART1/2/3 | +| SPI | 支持 | SPI5 | +| IIC | 支持 | IIC3 | +| SDRAM | 支持 | | +| LCD | 支持 | 支持 FrameBuffer 模式 LCD 显示 | +| 触摸屏 | 支持 | IIC 接口 STMPE811 | +| USB OTG Host| 即将支持 | 预计 2018/11 | +| USB OTG Device| 未支持 | | +| GPIO | 未支持 | | +| L3GD20 | 未支持 | | - **TODO** - auto add *.icf by scons script + +## 5. 联系人信息 + +维护人：[xuzhuoyi](https://github.com/xuzhuoyi) + +## 6. 参考 + +* [板子相关资料](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/32f429idiscovery.html) diff --git a/bsp/stm32f429-disco/rtconfig.h b/bsp/stm32f429-disco/rtconfig.h index f06e44d2c0..962f62bc55 100644 --- a/bsp/stm32f429-disco/rtconfig.h +++ b/bsp/stm32f429-disco/rtconfig.h @@ -8,18 +8,14 @@ #define RT_NAME_MAX 8 #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_DEBUG #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 1 -#define RT_DEBUG_THREAD 0 #define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 1024 -/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG /* Inter-Thread communication */ @@ -28,36 +24,27 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMHEAP_AS_HEAP is not set */ -/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE -/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -/* RT_USING_MODULE is not set */ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT -/* RT_USING_USER_MAIN is not set */ /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -70,139 +57,107 @@ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ +#define FINSH_ARG_MAX 10 /* Device virtual file system */ -/* RT_USING_DFS is not set */ -/* RT_DFS_ELM_USE_LFN_0 is not set */ -/* RT_DFS_ELM_USE_LFN_1 is not set */ -/* RT_DFS_ELM_USE_LFN_2 is not set */ -/* RT_DFS_ELM_USE_LFN_3 is not set */ +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ -/* RT_USING_I2C is not set */ +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_WIFI is not set */ + +/* Using WiFi */ + /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -#define RT_USING_PTHREADS -/* HAVE_SYS_SIGNALS is not set */ +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ -/* Network stack */ /* light weight TCP/IP stack */ -/* RT_USING_LWIP is not set */ /* Modbus master and slave stack */ -/* RT_USING_MODBUS is not set */ + +/* AT commands */ + /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_LOGTRACE is not set */ -/* RT_USING_RYM is not set */ /* RT-Thread online packages */ -/* system packages */ - -/* RT-Thread GUI Engine */ - -/* PKG_USING_GUIENGINE is not set */ -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ - /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ -/* PKG_USING_NETUTILS is not set */ + +/* IoT Cloud */ + /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_IPERF is not set */ + +/* system packages */ + + +/* peripheral libraries and drivers */ + /* miscellaneous packages */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* PKG_USING_QUICKLZ is not set */ + +/* sample package */ + +/* samples: kernel and components samples */ + /* example package: hello */ -/* PKG_USING_HELLO is not set */ -/* PKG_USING_MULTIBUTTON is not set */ +#define RT_USING_ILI9341_LCD +#define RT_USING_STMPE811_TOUCH #define RT_USING_EXT_SDRAM #define RT_USING_UART1 -/* RT_USING_UART2 is not set */ -/* RT_USING_UART3 is not set */ -/* RT_USING_SPI5 is not set */ +#define RT_USING_I2C3 #endif diff --git a/bsp/stm32f4xx-HAL/Kconfig b/bsp/stm32f4xx-HAL/Kconfig index 62eec30473..95ffd73be8 100644 --- a/bsp/stm32f4xx-HAL/Kconfig +++ b/bsp/stm32f4xx-HAL/Kconfig @@ -21,7 +21,7 @@ source "$PKGS_DIR/Kconfig" choice prompt "Device type" - default STM32F401RC + default SOC_STM32F401RC config SOC_STM32F405RG bool "STM32F405RG" config SOC_STM32F405VG @@ -297,16 +297,24 @@ config RT_HSE_VALUE config RT_HSE_HCLK int "System Clock Value" default 84000000 -config RT_USING_UART1 +config BSP_USING_UART1 bool "Using UART1" + select RT_USING_SERIAL default y -config RT_USING_UART2 +config BSP_USING_UART2 bool "Using UART2" - default n - -config RT_USING_UART6 + select RT_USING_SERIAL + default n + +config BSP_USING_UART3 + bool "Using UART3" + select RT_USING_SERIAL + default n + +config BSP_USING_UART6 bool "Using UART6" + select RT_USING_SERIAL default n if RT_USING_CAN diff --git a/bsp/stm32f4xx-HAL/applications/main.c b/bsp/stm32f4xx-HAL/applications/main.c index c9008d5a82..c68bad6501 100644 --- a/bsp/stm32f4xx-HAL/applications/main.c +++ b/bsp/stm32f4xx-HAL/applications/main.c @@ -1,11 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/board.c b/bsp/stm32f4xx-HAL/drivers/board.c index 99b868903a..b618bd36ee 100644 --- a/bsp/stm32f4xx-HAL/drivers/board.c +++ b/bsp/stm32f4xx-HAL/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/board.h b/bsp/stm32f4xx-HAL/drivers/board.h index bb68b2a908..fb46678a0d 100644 --- a/bsp/stm32f4xx-HAL/drivers/board.h +++ b/bsp/stm32f4xx-HAL/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -370,7 +366,7 @@ #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f4xx-HAL/drivers/drv_can.c b/bsp/stm32f4xx-HAL/drivers/drv_can.c index a5ef6def54..603a2a745b 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_can.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_can.c @@ -1,21 +1,7 @@ /* - * File : drv_can.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_can.h b/bsp/stm32f4xx-HAL/drivers/drv_can.h index 14c0d3eb22..e8c24f1a73 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_can.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_can.h @@ -1,11 +1,7 @@ /* - * File : drv_can.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_gpio.c b/bsp/stm32f4xx-HAL/drivers/drv_gpio.c index 702305d8fd..f000da5ede 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_gpio.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_gpio.c @@ -1,11 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_gpio.h b/bsp/stm32f4xx-HAL/drivers/drv_gpio.h index 7928233b86..a258b78194 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_gpio.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_gpio.h @@ -1,11 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_i2c.c b/bsp/stm32f4xx-HAL/drivers/drv_i2c.c index f1e4ca5a5f..3109e95bd3 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_i2c.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_i2c.c @@ -1,21 +1,7 @@ /* - * File : drv_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -78,11 +64,12 @@ static rt_int32_t drv_get_scl(void *data) static void drv_udelay(rt_uint32_t us) { - int i = (HAL_RCC_GetHCLKFreq() / 4000000 * us); - while (i) + __IO uint32_t Delay = us * (SystemCoreClock / 8U / 1000000U); + do { - i--; - } + __NOP(); + } + while (Delay --); } static const struct rt_i2c_bit_ops drv_bit_ops = diff --git a/bsp/stm32f4xx-HAL/drivers/drv_i2c.h b/bsp/stm32f4xx-HAL/drivers/drv_i2c.h index 04c0b2b773..ba4004e316 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_i2c.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_i2c.h @@ -1,21 +1,8 @@ /* - * File : drv_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_iwg.c b/bsp/stm32f4xx-HAL/drivers/drv_iwg.c index ecacad1445..feda1f3e34 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_iwg.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_iwg.c @@ -1,11 +1,7 @@ /* - * File : drv_iwg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +32,7 @@ static rt_err_t drv_control(rt_watchdog_t *wdt, int cmd, void *arg) switch (cmd) { case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: - hiwdg.Init.Reload = (rt_uint32_t)arg; + hiwdg.Init.Reload = (rt_uint32_t)*arg; if (HAL_IWDG_Init(&hiwdg) != HAL_OK) { return RT_ERROR; diff --git a/bsp/stm32f4xx-HAL/drivers/drv_iwg.h b/bsp/stm32f4xx-HAL/drivers/drv_iwg.h index a2593efcea..566138b6f9 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_iwg.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_iwg.h @@ -1,11 +1,7 @@ /* - * File : drv_iwg.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c index f046090c96..58b611e04f 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c @@ -1,21 +1,7 @@ /* - * File : drv_pwm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,20 +12,20 @@ #include #include -#define MAX_PERIOD 65535 +#define MAX_PERIOD 65535 #define MIN_PERIOD 3 #define MIN_PULSE 2 static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); -static struct rt_pwm_ops drv_ops = +static struct rt_pwm_ops drv_ops = { drv_pwm_control }; -static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) +static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) { rt_uint32_t channel = 0x04 * (configuration->channel - 1); - if(!enable) + if (!enable) { HAL_TIM_PWM_Stop(htim, channel); } @@ -50,27 +36,27 @@ static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configura return RT_EOK; } -static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) { rt_uint32_t channel = 0x04 * (configuration->channel - 1); rt_uint32_t tim_clock; #if (RT_HSE_HCLK > 100000000UL)//100M - if(htim->Instance == TIM1 && htim->Instance == TIM8) + if (htim->Instance == TIM1 && htim->Instance == TIM8) { tim_clock = SystemCoreClock; } else { - tim_clock = SystemCoreClock/2; + tim_clock = SystemCoreClock / 2; } #else tim_clock = SystemCoreClock; #endif - if(__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) + if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) { tim_clock = tim_clock / 2; } - else if(__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4) + else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4) { tim_clock = tim_clock / 4; } @@ -80,19 +66,19 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio return RT_EOK; } -static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) { rt_uint32_t period, pulse; rt_uint32_t tim_clock, psc; rt_uint32_t channel = 0x04 * (configuration->channel - 1); #if (RT_HSE_HCLK > 100000000UL)//100M - if(htim->Instance == TIM1 && htim->Instance == TIM8) + if (htim->Instance == TIM1 && htim->Instance == TIM8) { tim_clock = SystemCoreClock; } else { - tim_clock = SystemCoreClock/2; + tim_clock = SystemCoreClock / 2; } #else tim_clock = SystemCoreClock; @@ -102,30 +88,31 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio psc = period / MAX_PERIOD + 1; period = period / psc; __HAL_TIM_SET_PRESCALER(htim, psc - 1); - if(period < MIN_PERIOD) + if (period < MIN_PERIOD) { period = MIN_PERIOD; } __HAL_TIM_SET_AUTORELOAD(htim, period - 1); - pulse = configuration->pulse * tim_clock / psc / 1000UL; - if(pulse < MIN_PULSE) + pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) { pulse = MIN_PULSE; } - else if(pulse > period) + else if (pulse > period) { pulse = period; } - __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1 ); + __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1); + __HAL_TIM_SET_COUNTER(htim, 0); return RT_EOK; } static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { - struct rt_pwm_configuration * configuration = (struct rt_pwm_configuration *)arg; - TIM_HandleTypeDef * htim = (TIM_HandleTypeDef *)device->parent.user_data; - - switch(cmd) + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data; + + switch (cmd) { case PWM_CMD_ENABLE: return drv_pwm_enable(htim, configuration, RT_TRUE); @@ -140,22 +127,22 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg } } -static void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle); +static void HAL_TIM_MspPostInit(TIM_HandleTypeDef *timHandle); #ifdef BSP_USING_PWM1 -TIM_HandleTypeDef htim1; + TIM_HandleTypeDef htim1; #endif #ifdef BSP_USING_PWM2 -TIM_HandleTypeDef htim2; + TIM_HandleTypeDef htim2; #endif #ifdef BSP_USING_PWM3 -TIM_HandleTypeDef htim3; + TIM_HandleTypeDef htim3; #endif #ifdef BSP_USING_PWM4 -TIM_HandleTypeDef htim4; + TIM_HandleTypeDef htim4; #endif #ifdef BSP_USING_PWM5 -TIM_HandleTypeDef htim5; + TIM_HandleTypeDef htim5; #endif #ifdef BSP_USING_PWM1 @@ -465,179 +452,258 @@ void MX_TIM5_Init(void) } #endif /* BSP_USING_PWM5 */ -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *tim_pwmHandle) { - if(tim_pwmHandle->Instance==TIM1) + if (tim_pwmHandle->Instance == TIM1) { __HAL_RCC_TIM1_CLK_ENABLE(); } - else if(tim_pwmHandle->Instance==TIM2) + else if (tim_pwmHandle->Instance == TIM2) { __HAL_RCC_TIM2_CLK_ENABLE(); } - else if(tim_pwmHandle->Instance==TIM3) + else if (tim_pwmHandle->Instance == TIM3) { __HAL_RCC_TIM3_CLK_ENABLE(); } - else if(tim_pwmHandle->Instance==TIM4) + else if (tim_pwmHandle->Instance == TIM4) { __HAL_RCC_TIM4_CLK_ENABLE(); } - else if(tim_pwmHandle->Instance==TIM5) + else if (tim_pwmHandle->Instance == TIM5) { __HAL_RCC_TIM5_CLK_ENABLE(); } } -static void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +static void HAL_TIM_MspPostInit(TIM_HandleTypeDef *timHandle) { GPIO_InitTypeDef GPIO_InitStruct; - if(timHandle->Instance==TIM1) + if (timHandle->Instance == TIM1) { - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM1 GPIO Configuration + /**TIM1 GPIO Configuration PA8 ------> TIM1_CH1 PA9 ------> TIM1_CH2 PA10 ------> TIM1_CH3 - PA11 ------> TIM1_CH4 + PA11 ------> TIM1_CH4 */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11; +#if defined(BSP_USING_PWM1_CH1) || defined(BSP_USING_PWM1_CH2) || defined(BSP_USING_PWM1_CH3) || defined(BSP_USING_PWM1_CH4) + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM1_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_8; +#endif +#ifdef BSP_USING_PWM1_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_9; +#endif +#ifdef BSP_USING_PWM1_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_10; +#endif +#ifdef BSP_USING_PWM1_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_11; +#endif GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif } - else if(timHandle->Instance==TIM2) + else if (timHandle->Instance == TIM2) { - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM2 GPIO Configuration + /**TIM2 GPIO Configuration PA3 ------> TIM2_CH4 PA5 ------> TIM2_CH1 PB10 ------> TIM2_CH3 - PB3 ------> TIM2_CH2 + PB3 ------> TIM2_CH2 */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; +#if defined(BSP_USING_PWM2_CH1) || defined(BSP_USING_PWM2_CH4) + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM2_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_3; +#endif +#ifdef BSP_USING_PWM2_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_5; +#endif GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif - GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_3; +#if defined(BSP_USING_PWM2_CH2) || defined(BSP_USING_PWM2_CH3) + __HAL_RCC_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM2_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_3; +#endif +#ifdef BSP_USING_PWM2_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_10; +#endif GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif } - else if(timHandle->Instance==TIM3) + else if (timHandle->Instance == TIM3) { - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM3 GPIO Configuration + /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 PB0 ------> TIM3_CH3 - PB1 ------> TIM3_CH4 + PB1 ------> TIM3_CH4 */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; +#if defined(BSP_USING_PWM3_CH1) || defined(BSP_USING_PWM3_CH2) + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM3_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_6; +#endif +#ifdef BSP_USING_PWM3_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_7; +#endif GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + GPIO_InitStruct.Pin = 0x00; +#endif - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; +#if defined(BSP_USING_PWM3_CH3) || defined(BSP_USING_PWM3_CH4) + __HAL_RCC_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM3_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_0; +#endif +#ifdef BSP_USING_PWM3_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_1; +#endif GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif } - else if(timHandle->Instance==TIM4) + else if (timHandle->Instance == TIM4) { - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM4 GPIO Configuration + /**TIM4 GPIO Configuration PB6 ------> TIM4_CH1 PB7 ------> TIM4_CH2 PB8 ------> TIM4_CH3 - PB9 ------> TIM4_CH4 + PB9 ------> TIM4_CH4 */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; +#if defined(BSP_USING_PWM4_CH1) || defined(BSP_USING_PWM4_CH2) || defined(BSP_USING_PWM4_CH3) || defined(BSP_USING_PWM4_CH4) + __HAL_RCC_GPIOB_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM4_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_6; +#endif +#ifdef BSP_USING_PWM4_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_7; +#endif +#ifdef BSP_USING_PWM4_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_8; +#endif +#ifdef BSP_USING_PWM4_CH4 + GPIO_InitStruct.Pin |= GPIO_PIN_9; +#endif GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif } - else if(timHandle->Instance==TIM5) + else if (timHandle->Instance == TIM5) { - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**TIM5 GPIO Configuration + /**TIM5 GPIO Configuration PA0-WKUP ------> TIM5_CH1 PA1 ------> TIM5_CH2 - PA2 ------> TIM5_CH3 + PA2 ------> TIM5_CH3 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2; +#if defined(BSP_USING_PWM5_CH1) || defined(BSP_USING_PWM5_CH2) || defined(BSP_USING_PWM5_CH3) + __HAL_RCC_GPIOA_CLK_ENABLE(); + + GPIO_InitStruct.Pin = 0x00; +#ifdef BSP_USING_PWM5_CH1 + GPIO_InitStruct.Pin |= GPIO_PIN_0; +#endif +#ifdef BSP_USING_PWM5_CH2 + GPIO_InitStruct.Pin |= GPIO_PIN_1; +#endif +#ifdef BSP_USING_PWM5_CH3 + GPIO_InitStruct.Pin |= GPIO_PIN_2; +#endif + GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +#endif } - } -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *tim_pwmHandle) { - if(tim_pwmHandle->Instance==TIM1) + if (tim_pwmHandle->Instance == TIM1) { __HAL_RCC_TIM1_CLK_DISABLE(); } - else if(tim_pwmHandle->Instance==TIM2) + else if (tim_pwmHandle->Instance == TIM2) { __HAL_RCC_TIM2_CLK_DISABLE(); } - else if(tim_pwmHandle->Instance==TIM3) + else if (tim_pwmHandle->Instance == TIM3) { __HAL_RCC_TIM3_CLK_DISABLE(); } - else if(tim_pwmHandle->Instance==TIM4) + else if (tim_pwmHandle->Instance == TIM4) { __HAL_RCC_TIM4_CLK_DISABLE(); } - else if(tim_pwmHandle->Instance==TIM5) + else if (tim_pwmHandle->Instance == TIM5) { __HAL_RCC_TIM5_CLK_DISABLE(); } -} +} int drv_pwm_init(void) { #ifdef BSP_USING_PWM1 MX_TIM1_Init(); - rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm1", &drv_ops, &htim1); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm1", &drv_ops, &htim1); #endif #ifdef BSP_USING_PWM2 MX_TIM2_Init(); - rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm2", &drv_ops, &htim2); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm2", &drv_ops, &htim2); #endif #ifdef BSP_USING_PWM3 MX_TIM3_Init(); - rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm3", &drv_ops, &htim3); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm3", &drv_ops, &htim3); #endif #ifdef BSP_USING_PWM4 MX_TIM4_Init(); - rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm4", &drv_ops, &htim4); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm4", &drv_ops, &htim4); #endif #ifdef BSP_USING_PWM5 MX_TIM5_Init(); - rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm5", &drv_ops, &htim5); + rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), "pwm5", &drv_ops, &htim5); #endif return 0; } diff --git a/bsp/stm32f4xx-HAL/drivers/drv_rtc.c b/bsp/stm32f4xx-HAL/drivers/drv_rtc.c index 73bbf9d6cb..088c95f1c6 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_rtc.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_rtc.c @@ -1,21 +1,7 @@ /* - * File : drv_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_rtc.h b/bsp/stm32f4xx-HAL/drivers/drv_rtc.h index 4e94ed1c42..f1b6d7f754 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_rtc.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_rtc.h @@ -1,21 +1,7 @@ /* - * File : drv_rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_spi.c b/bsp/stm32f4xx-HAL/drivers/drv_spi.c index 594383509a..0841ae1cd2 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_spi.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_spi.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_spi.h b/bsp/stm32f4xx-HAL/drivers/drv_spi.h index 21cae8450e..7abba78b74 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_spi.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_spi.h @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_spiflash.c b/bsp/stm32f4xx-HAL/drivers/drv_spiflash.c index cf30b949a6..4eaedb8991 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_spiflash.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_spiflash.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_spiflash.h b/bsp/stm32f4xx-HAL/drivers/drv_spiflash.h index be546ffe81..8cacc38a9a 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_spiflash.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_spiflash.h @@ -1,11 +1,7 @@ /* - * File : drv_spiflash.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usart.c b/bsp/stm32f4xx-HAL/drivers/drv_usart.c index 7a58042a45..db3321ab34 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usart.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_usart.c @@ -147,7 +147,7 @@ static const struct rt_uart_ops drv_uart_ops = drv_getc, }; -#if defined(RT_USING_UART1) +#if defined(BSP_USING_UART1) /* UART1 device driver structure */ static struct drv_uart uart1; struct rt_serial_device serial1; @@ -168,9 +168,9 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* RT_USING_UART1 */ +#endif /* BSP_USING_UART1 */ -#if defined(RT_USING_UART2) +#if defined(BSP_USING_UART2) /* UART2 device driver structure */ static struct drv_uart uart2; struct rt_serial_device serial2; @@ -191,10 +191,33 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* RT_USING_UART2 */ +#endif /* BSP_USING_UART2 */ -#if defined(RT_USING_UART6) -/* UART2 device driver structure */ +#if defined(BSP_USING_UART3) +/* UART3 device driver structure */ +static struct drv_uart uart3; +struct rt_serial_device serial3; +void USART3_IRQHandler(void) +{ + struct drv_uart *uart; + uart = &uart3; + /* enter interrupt */ + rt_interrupt_enter(); + /* UART in mode Receiver -------------------------------------------------*/ + if ((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_RXNE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&uart->UartHandle, UART_IT_RXNE) != RESET)) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + __HAL_UART_CLEAR_FLAG(&uart->UartHandle, UART_FLAG_RXNE); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART6) +/* UART6 device driver structure */ static struct drv_uart uart6; struct rt_serial_device serial6; void USART6_IRQHandler(void) @@ -214,7 +237,7 @@ void USART6_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* RT_USING_UART3 */ +#endif /* BSP_USING_UART6 */ /** * @brief UART MSP Initialization @@ -228,6 +251,7 @@ void USART6_IRQHandler(void) void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) { GPIO_InitTypeDef GPIO_InitStruct; +#ifdef BSP_USING_UART1 if (uartHandle->Instance == USART1) { /* USART1 clock enable */ @@ -244,7 +268,9 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } - else if (uartHandle->Instance == USART2) +#endif /* BSP_USING_UART1 */ +#ifdef BSP_USING_UART2 + if (uartHandle->Instance == USART2) { /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); @@ -260,7 +286,27 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } - else if (uartHandle->Instance == USART6) +#endif /* BSP_USING_UART2 */ +#ifdef BSP_USING_UART3 + if (uartHandle->Instance == USART3) + { + /* USART3 clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + } +#endif /* BSP_USING_UART3 */ +#ifdef BSP_USING_UART6 + if (uartHandle->Instance == USART6) { /* USART6 clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); @@ -276,10 +322,12 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle) GPIO_InitStruct.Alternate = GPIO_AF8_USART6; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); } +#endif /* BSP_USING_UART6 */ } void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) { +#ifdef BSP_USING_UART1 if (uartHandle->Instance == USART1) { /* Peripheral clock disable */ @@ -290,7 +338,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9 | GPIO_PIN_10); } - else if (uartHandle->Instance == USART2) +#endif /* BSP_USING_UART1 */ +#ifdef BSP_USING_UART2 + if (uartHandle->Instance == USART2) { /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); @@ -300,7 +350,21 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3); } - else if (uartHandle->Instance == USART6) +#endif /* BSP_USING_UART2 */ +#ifdef BSP_USING_UART3 + if (uartHandle->Instance == USART3) + { + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10 | GPIO_PIN_11); + } +#endif /* BSP_USING_UART3 */ +#ifdef BSP_USING_UART6 + if (uartHandle->Instance == USART6) { /* Peripheral clock disable */ __HAL_RCC_USART6_CLK_DISABLE(); @@ -310,13 +374,14 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle) */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6 | GPIO_PIN_7); } +#endif /* BSP_USING_UART6 */ } int hw_usart_init(void) { struct drv_uart *uart; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; -#ifdef RT_USING_UART1 +#ifdef BSP_USING_UART1 uart = &uart1; uart->UartHandle.Instance = USART1; uart->irq = USART1_IRQn; @@ -326,8 +391,8 @@ int hw_usart_init(void) rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* RT_USING_UART1 */ -#ifdef RT_USING_UART2 +#endif /* BSP_USING_UART1 */ +#ifdef BSP_USING_UART2 uart = &uart2; uart->UartHandle.Instance = USART2; uart->irq = USART2_IRQn; @@ -337,18 +402,30 @@ int hw_usart_init(void) rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* RT_USING_UART2 */ -#ifdef RT_USING_UART6 +#endif /* BSP_USING_UART2 */ +#ifdef BSP_USING_UART3 + uart = &uart3; + uart->UartHandle.Instance = USART3; + uart->irq = USART3_IRQn; + serial3.ops = &drv_uart_ops; + serial3.config = config; + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ +#ifdef BSP_USING_UART6 uart = &uart6; uart->UartHandle.Instance = USART6; uart->irq = USART6_IRQn; serial6.ops = &drv_uart_ops; serial6.config = config; - /* register UART2 device */ + /* register UART6 device */ rt_hw_serial_register(&serial6, "uart6", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* RT_USING_UART2 */ +#endif /* BSP_USING_UART6 */ + return 0; } INIT_BOARD_EXPORT(hw_usart_init); diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usart.h b/bsp/stm32f4xx-HAL/drivers/drv_usart.h index 1500bf07c2..c0bd8b3d98 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usart.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usbd.c b/bsp/stm32f4xx-HAL/drivers/drv_usbd.c index 7e0271e9dd..9f06e5167c 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usbd.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_usbd.c @@ -1,11 +1,7 @@ /* - * File : stm32_usbd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usbd.h b/bsp/stm32f4xx-HAL/drivers/drv_usbd.h index 0f748e1c6b..942f234062 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usbd.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_usbd.h @@ -1,11 +1,7 @@ /* - * File : stm32_usbd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usbh.c b/bsp/stm32f4xx-HAL/drivers/drv_usbh.c index d640f5a6c3..e002c2f7e6 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usbh.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_usbh.c @@ -1,11 +1,7 @@ /* - * File : stm32_usbh.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -183,6 +179,9 @@ static int drv_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbyte { pipe->callback(pipe); } + if (pipe->ep.bEndpointAddress & 0x80) { + return HAL_HCD_HC_GetXferCount(&_stm_hhcd_fs, pipe->pipe_index); + } return nbytes; } return -1; diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usbh.h b/bsp/stm32f4xx-HAL/drivers/drv_usbh.h index 9c245555a3..8a7e0ff071 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usbh.h +++ b/bsp/stm32f4xx-HAL/drivers/drv_usbh.h @@ -1,11 +1,7 @@ /* - * File : stm32_usbh.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f4xx-HAL/rtconfig.py b/bsp/stm32f4xx-HAL/rtconfig.py index d8de63dca7..39d157a9dc 100644 --- a/bsp/stm32f4xx-HAL/rtconfig.py +++ b/bsp/stm32f4xx-HAL/rtconfig.py @@ -3,16 +3,15 @@ import os # toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' +ARCH = 'arm' +CPU = 'cortex-m4' +CROSS_TOOL = 'gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') #device options - # cross_tool provides the cross compiler # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR if CROSS_TOOL == 'gcc': @@ -44,7 +43,7 @@ if PLATFORM == 'gcc': OBJCPY = PREFIX + 'objcopy' DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -std=c99 -Dgcc' # -D' + PART_TYPE + CFLAGS = DEVICE + ' -std=c99' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld' diff --git a/bsp/stm32f4xx-HAL/stm32_rom.ld b/bsp/stm32f4xx-HAL/stm32_rom.ld index aa9c9b2af2..58851b43a2 100644 --- a/bsp/stm32f4xx-HAL/stm32_rom.ld +++ b/bsp/stm32f4xx-HAL/stm32_rom.ld @@ -80,6 +80,7 @@ SECTIONS .stack : { + _sstack = .; . = . + _system_stack_size; . = ALIGN(4); _estack = .; diff --git a/bsp/stm32f7-disco/applications/main.c b/bsp/stm32f7-disco/applications/main.c index a0b14aee41..6ac61f0e2c 100644 --- a/bsp/stm32f7-disco/applications/main.c +++ b/bsp/stm32f7-disco/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/board.c b/bsp/stm32f7-disco/drivers/board.c index aee2db1d4b..c86025d292 100644 --- a/bsp/stm32f7-disco/drivers/board.c +++ b/bsp/stm32f7-disco/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/board.h b/bsp/stm32f7-disco/drivers/board.h index 837b978534..20e7290b94 100644 --- a/bsp/stm32f7-disco/drivers/board.h +++ b/bsp/stm32f7-disco/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -21,7 +17,7 @@ #define EXT_SDRAM_SIZE (0x800000) #define EXT_SDRAM_END (EXT_SDRAM_BEGIN + EXT_SDRAM_SIZE) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32f7-disco/drivers/drv_cache.c b/bsp/stm32f7-disco/drivers/drv_cache.c index 35216b6b7c..d5ac4eb441 100644 --- a/bsp/stm32f7-disco/drivers/drv_cache.c +++ b/bsp/stm32f7-disco/drivers/drv_cache.c @@ -1,21 +1,7 @@ /* - * File : drv_cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/drv_mpu.c b/bsp/stm32f7-disco/drivers/drv_mpu.c index 825b82ff9d..09857d3cf5 100644 --- a/bsp/stm32f7-disco/drivers/drv_mpu.c +++ b/bsp/stm32f7-disco/drivers/drv_mpu.c @@ -1,21 +1,7 @@ /* - * File : drv_mpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/drv_mpu.h b/bsp/stm32f7-disco/drivers/drv_mpu.h index 675be55ca4..8e2e4a699e 100644 --- a/bsp/stm32f7-disco/drivers/drv_mpu.h +++ b/bsp/stm32f7-disco/drivers/drv_mpu.h @@ -1,21 +1,7 @@ /* - * File : drv_mpu.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/drv_sdram.c b/bsp/stm32f7-disco/drivers/drv_sdram.c index c141c26af2..b5afa0361d 100644 --- a/bsp/stm32f7-disco/drivers/drv_sdram.c +++ b/bsp/stm32f7-disco/drivers/drv_sdram.c @@ -1,21 +1,7 @@ /* - * File : drv_sdram.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/drv_sdram.h b/bsp/stm32f7-disco/drivers/drv_sdram.h index f3b66e8d27..91b9cc2c9a 100644 --- a/bsp/stm32f7-disco/drivers/drv_sdram.h +++ b/bsp/stm32f7-disco/drivers/drv_sdram.h @@ -1,15 +1,12 @@ /* - * File : drv_sdram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015 RT-Thread Develop Team +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2015-08-03 xiaonong The first version for STM32F7 + * 2015-08-03 xiaonong The first version for STM32F7 */ #ifndef __DRV_SDRAM_H__ diff --git a/bsp/stm32f7-disco/drivers/drv_usart.c b/bsp/stm32f7-disco/drivers/drv_usart.c index 59471c9972..5d54d6903b 100644 --- a/bsp/stm32f7-disco/drivers/drv_usart.c +++ b/bsp/stm32f7-disco/drivers/drv_usart.c @@ -1,21 +1,7 @@ /* - * File : drv_usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32f7-disco/drivers/drv_usart.h b/bsp/stm32f7-disco/drivers/drv_usart.h index 184bffbefd..def63ebcae 100644 --- a/bsp/stm32f7-disco/drivers/drv_usart.h +++ b/bsp/stm32f7-disco/drivers/drv_usart.h @@ -1,21 +1,7 @@ /* - * File : drv_usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/.config b/bsp/stm32h743-nucleo/.config new file mode 100644 index 0000000000..bb13ccfc66 --- /dev/null +++ b/bsp/stm32h743-nucleo/.config @@ -0,0 +1,319 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_STM32_SDIO is not set + +# +# Test Packages of RealThread +# +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +CONFIG_RT_USING_UART1=y diff --git a/bsp/stm32h743-nucleo/Kconfig b/bsp/stm32h743-nucleo/Kconfig new file mode 100644 index 0000000000..07e59e8ebb --- /dev/null +++ b/bsp/stm32h743-nucleo/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config RT_USING_UART1 + bool "Using uart1" + select RT_USING_SERIAL + default y + diff --git a/bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.S b/bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s similarity index 100% rename from bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.S rename to bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s diff --git a/bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.S b/bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s similarity index 100% rename from bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.S rename to bsp/stm32h743-nucleo/Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s diff --git a/bsp/stm32h743-nucleo/applications/main.c b/bsp/stm32h743-nucleo/applications/main.c index 980c32a729..a41c241683 100644 --- a/bsp/stm32h743-nucleo/applications/main.c +++ b/bsp/stm32h743-nucleo/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,35 +9,10 @@ * 2014-04-27 Bernard make code cleanup. * 2017-08-25 LongfeiMa transplantation for stm32h7xx */ - -#include -#include - -#include "board.h" -#include - -#include "lan8742a.h" - -#include "netif/ethernetif.h" - - +#include int main(void) { -// rt_kprintf("here we are in the main \r\n"); - /* LwIP Initialization */ -#ifdef RT_USING_LWIP - { -// extern void lwip_sys_init(void); -// eth_system_device_init(); - - /* register ethernetif device */ -// rt_hw_lan8742a_init(); - - /* init lwip system */ -// lwip_sys_init(); - rt_kprintf("TCP/IP initialized!\n"); - } -#endif + return 0; } diff --git a/bsp/stm32h743-nucleo/applications/sram.c b/bsp/stm32h743-nucleo/applications/sram.c index 3b38fd3053..8186a7e8a3 100644 --- a/bsp/stm32h743-nucleo/applications/sram.c +++ b/bsp/stm32h743-nucleo/applications/sram.c @@ -1,21 +1,7 @@ /* -* File : sram.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/applications/sram.h b/bsp/stm32h743-nucleo/applications/sram.h index 03c2b0a288..00d324afb5 100644 --- a/bsp/stm32h743-nucleo/applications/sram.h +++ b/bsp/stm32h743-nucleo/applications/sram.h @@ -1,11 +1,7 @@ /* - * File : sram.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/SConscript b/bsp/stm32h743-nucleo/drivers/SConscript index f5db56a368..709c7c6e1d 100644 --- a/bsp/stm32h743-nucleo/drivers/SConscript +++ b/bsp/stm32h743-nucleo/drivers/SConscript @@ -1,8 +1,17 @@ from building import * cwd = GetCurrentDir() -src = Glob('*.c') +src = Split(""" +board.c +stm32h7xx_it.c +drv_mpu.c +""") +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend('RT_USING_LWIP'): + src += ['lan8742a.c'] CPPPATH = [cwd] diff --git a/bsp/stm32h743-nucleo/drivers/board.c b/bsp/stm32h743-nucleo/drivers/board.c index 26635ff277..ee9310e14c 100644 --- a/bsp/stm32h743-nucleo/drivers/board.c +++ b/bsp/stm32h743-nucleo/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/board.h b/bsp/stm32h743-nucleo/drivers/board.h index 6a597b6b09..da8f6d155b 100644 --- a/bsp/stm32h743-nucleo/drivers/board.h +++ b/bsp/stm32h743-nucleo/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/drv_led.c b/bsp/stm32h743-nucleo/drivers/drv_led.c index a859be3eeb..b4d164d2d5 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_led.c +++ b/bsp/stm32h743-nucleo/drivers/drv_led.c @@ -1,21 +1,7 @@ /* - * File : drv_led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/drv_led.h b/bsp/stm32h743-nucleo/drivers/drv_led.h index bf8fd3e48b..5758b559a9 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_led.h +++ b/bsp/stm32h743-nucleo/drivers/drv_led.h @@ -1,11 +1,7 @@ /* - * File : drv_led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/drv_mpu.c b/bsp/stm32h743-nucleo/drivers/drv_mpu.c index 1f091a8e7f..9b25f36d59 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_mpu.c +++ b/bsp/stm32h743-nucleo/drivers/drv_mpu.c @@ -1,21 +1,7 @@ /* - * File : drv_mpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/drv_mpu.h b/bsp/stm32h743-nucleo/drivers/drv_mpu.h index 2f06d4ce23..4a0cc43674 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_mpu.h +++ b/bsp/stm32h743-nucleo/drivers/drv_mpu.h @@ -1,11 +1,7 @@ /* - * File : drv_mpu.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/drv_usart.c b/bsp/stm32h743-nucleo/drivers/drv_usart.c index ec18809c77..e8620b65ee 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_usart.c +++ b/bsp/stm32h743-nucleo/drivers/drv_usart.c @@ -1,21 +1,7 @@ /* - * File : drv_usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/drv_usart.h b/bsp/stm32h743-nucleo/drivers/drv_usart.h index fcf01177bb..75f83ffe93 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_usart.h +++ b/bsp/stm32h743-nucleo/drivers/drv_usart.h @@ -1,11 +1,7 @@ /* - * File : drv_usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/lan8742a.c b/bsp/stm32h743-nucleo/drivers/lan8742a.c index 4e6a71f3ef..8624b7f0bd 100644 --- a/bsp/stm32h743-nucleo/drivers/lan8742a.c +++ b/bsp/stm32h743-nucleo/drivers/lan8742a.c @@ -1,21 +1,7 @@ /* - * File : drv_mpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/drivers/lan8742a.h b/bsp/stm32h743-nucleo/drivers/lan8742a.h index 56d6fbf160..c0c14ab332 100644 --- a/bsp/stm32h743-nucleo/drivers/lan8742a.h +++ b/bsp/stm32h743-nucleo/drivers/lan8742a.h @@ -1,11 +1,7 @@ /* - * File : lan8742a.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32h743-nucleo/rtconfig.h b/bsp/stm32h743-nucleo/rtconfig.h index 9eab3fb8ab..e341d043f9 100644 --- a/bsp/stm32h743-nucleo/rtconfig.h +++ b/bsp/stm32h743-nucleo/rtconfig.h @@ -1,233 +1,283 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -// +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -// -#define RT_NAME_MAX 8 -// -#define RT_ALIGN_SIZE 4 -// -// 8 -// 32 -// 256 -// -#define RT_THREAD_PRIORITY_MAX 32 -// -#define RT_TICK_PER_SECOND 1000 -// -#define IDLE_THREAD_STACK_SIZE 512 -// -//#define RT_USING_MODULE -//
-#define RT_DEBUG -// -// #define RT_THREAD_DEBUG -// +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK -//
- -// #define RT_USING_HOOK -//
-#define RT_USING_TIMER_SOFT -// -#define RT_TIMER_THREAD_PRIO 4 -// -#define RT_TIMER_THREAD_STACK_SIZE 512 -// -#define RT_TIMER_TICK_PER_SECOND 200 -//
+#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ + +/* Inter-Thread communication */ -//
-// #define RT_USING_SEMAPHORE -// #define RT_USING_MUTEX -// #define RT_USING_EVENT -// #define RT_USING_MAILBOX -// #define RT_USING_MESSAGEQUEUE -//
+/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ -//
-// #define RT_USING_MEMPOOL -// -#define RT_USING_MEMHEAP -// -#define RT_USING_HEAP -// +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -// -// #define RT_USING_SLAB -//
+/* RT_USING_SLAB is not set */ +/* RT_USING_MEMTRACE is not set */ +#define RT_USING_HEAP + +/* Kernel Device Object */ -//
#define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL -// -#define RT_SERIAL_RB_BUFSZ 64 -// -//#define RT_USING_MTD_NAND -// -//#define RT_MTD_NAND_DEBUG -// -//#define RT_USING_NFTL -// -//#define RT_USING_SPI -// -//#define RT_USING_I2C -// -//#define RT_USING_RTC -// -//#define RT_MMCSD_THREAD_PREORITY 15 -//
+/* RT_USING_DEVICE_OPS is not set */ +/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE -// -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart1" -//
+#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" -// -#define RT_USING_COMPONENTS_INIT -//
-#define RT_USING_FINSH -#define FINSH_THREAD_PRIORITY 0xa -// -#define FINSH_USING_SYMTAB -// -#define FINSH_USING_DESCRIPTION -// -#define FINSH_THREAD_STACK_SIZE 4096 -// -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -//
- -//
-// -#define RT_USING_LIBC -// -#define RT_USING_PTHREADS -//
- -//
-//#define RT_USING_DFS -// -#define DFS_USING_WORKDIR -// -#define DFS_FILESYSTEM_TYPES_MAX 4 -// -#define DFS_FILESYSTEMS_MAX 4 -// -#define DFS_FD_MAX 32 -// -#define RT_USING_DFS_ELMFAT -// -#define RT_DFS_ELM_DRIVES 4 -// -#define RT_DFS_ELM_REENTRANT -// -// 1 -// 2 -// 3 -// -#define RT_DFS_ELM_USE_LFN 3 -// -#define RT_DFS_ELM_CODE_PAGE 437 -// -// #define RT_DFS_ELM_CODE_PAGE_FILE -// -#define RT_DFS_ELM_MAX_LFN 256 -// -#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 -// -// #define RT_DFS_ELM_USE_ERASE -// -// #define RT_USING_DFS_YAFFS2 -// -// #define RT_USING_DFS_UFFS -// -#define RT_USING_DFS_DEVFS -// -//#define RT_USING_DFS_ROMFS -// -// #define RT_USING_DFS_NFS -// -#define RT_NFS_HOST_EXPORT "192.168.137.1:/" -//
- -//
-#define RT_USING_LWIP -// -#define RT_USING_LWIP141 -// -#define RT_LWIP_ICMP -// -// #define RT_LWIP_IGMP -// -#define RT_LWIP_UDP -// -#define RT_LWIP_TCP -// -#define RT_LWIP_DNS -// -#define RT_LWIP_PBUF_NUM 8 -// -#define RT_LWIP_TCP_PCB_NUM 8 -// -#define RT_LWIP_TCP_SND_BUF 8192 -// -#define RT_LWIP_TCP_WND 8192 -// -// #define RT_LWIP_SNMP -// -#define RT_LWIP_DHCP -// -//#define RT_LWIP_TCP_SEG_NUM 8 -// -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -// -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -// -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 -// -#define RT_LWIP_ETHTHREAD_PRIORITY 14 -// -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -// -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 -// -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 137 -#define RT_LWIP_IPADDR3 30 -// -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 137 -#define RT_LWIP_GWADDR3 1 -// -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 -//
- -// - -/* enable SDRAM */ -//#define RT_USING_EXT_SDRAM +/* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +/* FINSH_USING_MSH_ONLY is not set */ +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +/* RT_USING_DFS_MNTTABLE is not set */ +/* RT_USING_DFS_ELMFAT is not set */ +#define RT_USING_DFS_DEVFS +/* RT_USING_DFS_ROMFS is not set */ +/* RT_USING_DFS_RAMFS is not set */ +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ +/* RT_USING_DFS_NFS is not set */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +/* RT_USING_I2C is not set */ +/* RT_USING_PIN is not set */ +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_WIFI is not set */ +/* RT_USING_AUDIO is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +/* RT_USING_PTHREADS is not set */ +/* RT_USING_MODULE is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_LOGTRACE is not set */ +/* RT_USING_RYM is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_STM32F4_HAL is not set */ +/* PKG_USING_STM32F4_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ + +/* sample package */ + +/* PKG_USING_SAMPLES is not set */ + +/* example package: hello */ + +/* PKG_USING_HELLO is not set */ + +/* Privated Packages of RealThread */ + +/* PKG_USING_CODEC is not set */ +/* PKG_USING_PLAYER is not set */ +/* PKG_USING_PERSIMMON_SRC is not set */ + +/* Network Utilities */ + +/* PKG_USING_WICED is not set */ +/* PKG_USING_CLOUDSDK is not set */ +/* PKG_USING_COREMARK is not set */ +/* PKG_USING_POWER_MANAGER is not set */ +/* PKG_USING_RT_OTA is not set */ +/* PKG_USING_RDB is not set */ +/* PKG_USING_RTINSIGHT is not set */ +/* PKG_USING_STM32_SDIO is not set */ + +/* Test Packages of RealThread */ + +/* PKG_USING_JERRYSCRIPT_WIN32 is not set */ +/* PKG_USING_JS_PERSIMMON is not set */ +#define RT_USING_UART1 #endif diff --git a/bsp/stm32h743-nucleo/rtconfig.py b/bsp/stm32h743-nucleo/rtconfig.py index 8ef89a1258..8f8a36acb8 100644 --- a/bsp/stm32h743-nucleo/rtconfig.py +++ b/bsp/stm32h743-nucleo/rtconfig.py @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': STRIP = PREFIX + 'strip' DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -g -Wall -DSTM32H743xx -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_USED -eentry' + CFLAGS = DEVICE + ' -g -Wall -DSTM32H743xx -DUSE_HAL_DRIVER -D__ASSEMBLY__ -eentry' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_stm32h7xx.map,-cref,-u,Reset_Handler -T rtthread-stm32h7xx.ld' diff --git a/bsp/stm32l072/app/application.c b/bsp/stm32l072/app/application.c index f0e9932a65..aad725735e 100644 --- a/bsp/stm32l072/app/application.c +++ b/bsp/stm32l072/app/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l072/app/startup.c b/bsp/stm32l072/app/startup.c index 3722037db1..b1342f76d9 100644 --- a/bsp/stm32l072/app/startup.c +++ b/bsp/stm32l072/app/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,7 +22,7 @@ extern int rt_application_init(void); -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32l072/board/board.c b/bsp/stm32l072/board/board.c index 37f96c586b..923af2e8b9 100644 --- a/bsp/stm32l072/board/board.c +++ b/bsp/stm32l072/board/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l072/board/board.h b/bsp/stm32l072/board/board.h index 5e97446610..be00344b8f 100644 --- a/bsp/stm32l072/board/board.h +++ b/bsp/stm32l072/board/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l072/board/drv_spi.c b/bsp/stm32l072/board/drv_spi.c index ac1311937d..b963629024 100644 --- a/bsp/stm32l072/board/drv_spi.c +++ b/bsp/stm32l072/board/drv_spi.c @@ -1,11 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l072/board/gpio.c b/bsp/stm32l072/board/gpio.c index 30295eff18..da5660e3f3 100644 --- a/bsp/stm32l072/board/gpio.c +++ b/bsp/stm32l072/board/gpio.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l072/board/usart.c b/bsp/stm32l072/board/usart.c index a3880c8250..9b016cefe1 100644 --- a/bsp/stm32l072/board/usart.c +++ b/bsp/stm32l072/board/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l072/board/usart.h b/bsp/stm32l072/board/usart.h index ffc55552b3..cb48abde4b 100644 --- a/bsp/stm32l072/board/usart.h +++ b/bsp/stm32l072/board/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l475-iot-disco/applications/application.c b/bsp/stm32l475-iot-disco/applications/application.c index b66b0dd93e..871e843f16 100644 --- a/bsp/stm32l475-iot-disco/applications/application.c +++ b/bsp/stm32l475-iot-disco/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l475-iot-disco/applications/startup.c b/bsp/stm32l475-iot-disco/applications/startup.c index f1e3c185bb..f726f8d854 100644 --- a/bsp/stm32l475-iot-disco/applications/startup.c +++ b/bsp/stm32l475-iot-disco/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l475-iot-disco/drivers/board.c b/bsp/stm32l475-iot-disco/drivers/board.c index 5164ca564c..689f45b3f5 100644 --- a/bsp/stm32l475-iot-disco/drivers/board.c +++ b/bsp/stm32l475-iot-disco/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l475-iot-disco/drivers/board.h b/bsp/stm32l475-iot-disco/drivers/board.h index 64e75ba568..65fd35f9d1 100644 --- a/bsp/stm32l475-iot-disco/drivers/board.h +++ b/bsp/stm32l475-iot-disco/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,7 +25,7 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32l475-iot-disco/drivers/usart.c b/bsp/stm32l475-iot-disco/drivers/usart.c index febe9545a6..fa5a68e7cb 100644 --- a/bsp/stm32l475-iot-disco/drivers/usart.c +++ b/bsp/stm32l475-iot-disco/drivers/usart.c @@ -1,11 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l475-iot-disco/drivers/usart.h b/bsp/stm32l475-iot-disco/drivers/usart.h index 3faf85fcde..12cfd253cf 100644 --- a/bsp/stm32l475-iot-disco/drivers/usart.h +++ b/bsp/stm32l475-iot-disco/drivers/usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l476-nucleo/applications/main.c b/bsp/stm32l476-nucleo/applications/main.c index 5f289cf43d..d62b7bff68 100644 --- a/bsp/stm32l476-nucleo/applications/main.c +++ b/bsp/stm32l476-nucleo/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l476-nucleo/drivers/board.c b/bsp/stm32l476-nucleo/drivers/board.c index 063e5806ff..4c5d7d8313 100644 --- a/bsp/stm32l476-nucleo/drivers/board.c +++ b/bsp/stm32l476-nucleo/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l476-nucleo/drivers/board.h b/bsp/stm32l476-nucleo/drivers/board.h index 9c77d91894..dee99dd053 100644 --- a/bsp/stm32l476-nucleo/drivers/board.h +++ b/bsp/stm32l476-nucleo/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,7 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32l476-nucleo/drivers/drv_gpio.c b/bsp/stm32l476-nucleo/drivers/drv_gpio.c index 92b4697dd1..7ebe789cd6 100644 --- a/bsp/stm32l476-nucleo/drivers/drv_gpio.c +++ b/bsp/stm32l476-nucleo/drivers/drv_gpio.c @@ -1,21 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l476-nucleo/drivers/drv_gpio.h b/bsp/stm32l476-nucleo/drivers/drv_gpio.h index e8b3dae79e..90ded72340 100644 --- a/bsp/stm32l476-nucleo/drivers/drv_gpio.h +++ b/bsp/stm32l476-nucleo/drivers/drv_gpio.h @@ -1,11 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l476-nucleo/drivers/drv_usart.h b/bsp/stm32l476-nucleo/drivers/drv_usart.h index 7fc3172209..fd1f519abc 100644 --- a/bsp/stm32l476-nucleo/drivers/drv_usart.h +++ b/bsp/stm32l476-nucleo/drivers/drv_usart.h @@ -1,11 +1,7 @@ /* - * File : usart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/tm4c129x-dk/.config b/bsp/tm4c129x-dk/.config deleted file mode 100644 index 65b5b05742..0000000000 --- a/bsp/tm4c129x-dk/.config +++ /dev/null @@ -1,219 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -CONFIG_RT_ALIGN_SIZE=4 -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -# CONFIG_RT_DEBUG_THREAD is not set -CONFIG_RT_USING_HOOK=y -CONFIG_IDLE_THREAD_STACK_SIZE=256 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_USING_HEAP=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -# CONFIG_RT_USING_MODULE is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -# CONFIG_FINSH_USING_MSH is not set - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PIN is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set - -# -# Network stack -# - -# -# light weight TCP/IP stack -# -CONFIG_RT_USING_LWIP=y -CONFIG_RT_USING_LWIP141=y -# CONFIG_RT_USING_LWIP202 is not set -# CONFIG_RT_LWIP_IGMP is not set -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 -# CONFIG_LWIP_USING_DHCPD is not set - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set -# CONFIG_RT_LWIP_PPP is not set -# CONFIG_RT_LWIP_PPPOE is not set -# CONFIG_RT_LWIP_PPPOS is not set -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set -# CONFIG_RT_USING_NETUTILS is not set - -# -# RT-Thread UI Engine -# -# CONFIG_PKG_USING_GUIENGINE is not set - -# -# RT-Thread online packages -# - -# -# system packages -# -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_EZXML is not set - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_MARVELLWIFI is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set - -# -# language packages -# -# CONFIG_PKG_USING_JERRYSCRIPT is not set - -# -# multimedia packages -# - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYLOGGER is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_HELLO is not set - -# -# BSP_SPECIAL CONFIG -# -CONFIG_RT_USING_UART0=y diff --git a/bsp/tm4c129x-dk/README.md b/bsp/tm4c129x-dk/README.md deleted file mode 100644 index 8c01a26cf1..0000000000 --- a/bsp/tm4c129x-dk/README.md +++ /dev/null @@ -1,65 +0,0 @@ -# TM4C129X-Development Board -http://www.ti.com/tool/dk-tm4c129x - -## 1. 简介 - -TM4C129X-DK是TI官方的开发板，此为其中一款开发板，带屏幕，配置更高。 -TI官方提供了详细的SDK支持，含USB，LWIP，甚至图形库。 - -核心板板载主要资源如下： - -| 硬件 | 描述 | -| -- | -- | -|芯片型号| TM4C129XNCZAD | -|CPU| ARM Cortex-M4F | -|主频| 120MHz | -|片内Flash| 1024B | -|片内SRAM| 256KB | - - -## 2. 编译说明 - -TM4C129X-DK板级包目前仅支持MDK5编译器，以下是具体版本信息： - -| IDE/编译器 | 已测试版本 | -| ---------- | ---------------------------- | -| MDK5 | MDK521a | - - -## 3. 烧写及执行 - -TM4C129X-DK本身提供了一个烧录接口，是Stellaris ICDI，keil本身不提供该驱动，需自行下载。 -http://www.ti.com.cn/tool/cn/stellaris_icdi_drivers - -供电方式：使用ICDI接口即可供电 - -### 3.1 运行结果 - -如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： - -```bash - \ | / -- RT - Thread Operating System - / | \ 3.0.3 build Feb 28 2018 - 2006 - 2018 Copyright by rt-thread team -finsh /> - -``` - -## 4. 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| ------ | ---- | :------: | - -### 4.1 IO在板级支持包中的映射情况 - -| IO号 | 板级包中的定义 | -| -- | -- | - -## 5. 联系人信息 - -维护人：[zero](https://github.com/Zero-Sky) - -## 6. 参考 - - diff --git a/bsp/tm4c129x-dk/applications/board.c b/bsp/tm4c129x-dk/applications/board.c deleted file mode 100644 index 0da547e867..0000000000 --- a/bsp/tm4c129x-dk/applications/board.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - * 2014-07-18 ArdaFu Port to TM4C129X - */ - -#include -#include -#include "board.h" - - -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/systick.h" -#include "driverlib/fpu.h" -#include "driverlib/rom_map.h" - -#define SYS_CLOCK_DEFAULT 120000000 -uint32_t SystemCoreClock; -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -extern void PendSV_Handler(void); -extern void HardFault_Handler(void); - -/** - * This function will initial LPC40xx board. - */ -void rt_hw_board_init() -{ - //init low level drivers. e.g. cpu uart etc. - rt_components_board_init(); - //redirect RTT stdio to CONSOLE device - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -} - -int rt_hw_cpu_init(void) -{ - MAP_IntMasterDisable(); - IntRegister(FAULT_HARD, HardFault_Handler); - IntRegister(FAULT_PENDSV, PendSV_Handler); - IntRegister(FAULT_SYSTICK, SysTick_Handler); - - // Enable lazy stacking for interrupt handlers. This allows floating-point - // instructions to be used within interrupt handlers, but at the expense of - // extra stack usage. - MAP_FPULazyStackingEnable(); - - // Set the clocking to run directly from the external crystal/oscillator. - // TODO: The SYSCTL_XTAL_ value must be changed to match the value of the - // crystal on your board. - SystemCoreClock = MAP_SysCtlClockFreqSet( - (SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), - SYS_CLOCK_DEFAULT); - - MAP_SysTickDisable(); - MAP_SysTickPeriodSet(SystemCoreClock/ RT_TICK_PER_SECOND - 1); - MAP_SysTickIntEnable(); - MAP_SysTickEnable(); - - return 0; -} -// rt_hw_cpu_init should be run before any other INIT_BOARD_EXPORT -// We use INIT_EXPORT here and set the sequence index to "0.xxxx" -INIT_EXPORT(rt_hw_cpu_init, "0.post"); diff --git a/bsp/tm4c129x-dk/applications/board.h b/bsp/tm4c129x-dk/applications/board.h deleted file mode 100644 index 8103d0b1f1..0000000000 --- a/bsp/tm4c129x-dk/applications/board.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2010-02-04 Magicoe add board.h to LPC176x bsp - * 2014-07-18 ArdaFu port it to TM4C129X bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include "tm4c1294ncpdt.h" -#include -#include -#include - -extern uint32_t SystemCoreClock; -#ifdef __CC_ARM -extern int Image$$RW_IRAM$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int _ebss; -#define HEAP_BEGIN ((void *)&_ebss) -#endif -#define HEAP_END (0x20000000 + 256*1024) - -#define FINSH_DEVICE_NAME RT_CONSOLE_DEVICE_NAME -void rt_hw_board_init(void); - -#endif diff --git a/bsp/tm4c129x-dk/context_rvds.lst b/bsp/tm4c129x-dk/context_rvds.lst deleted file mode 100644 index c112e11f8a..0000000000 --- a/bsp/tm4c129x-dk/context_rvds.lst +++ /dev/null @@ -1,551 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;/* - 2 00000000 ; * File : context_rvds.S - 3 00000000 ; * This file is part of RT-Thread RTOS - 4 00000000 ; * COPYRIGHT (C) 2009, RT-Thread Development Team - 5 00000000 ; * - 6 00000000 ; * The license and distribution terms for this file may - be - 7 00000000 ; * found in the file LICENSE in this distribution or at - - 8 00000000 ; * http://www.rt-thread.org/license/LICENSE - 9 00000000 ; * - 10 00000000 ; * Change Logs: - 11 00000000 ; * Date Author Notes - 12 00000000 ; * 2009-01-17 Bernard first version. - 13 00000000 ; * 2012-01-01 aozima support context switch l - oad/store FPU register. - 14 00000000 ; * 2013-06-18 aozima add restore MSP feature. - - 15 00000000 ; * 2013-06-23 aozima support lazy stack optim - ized. - 16 00000000 ; */ - 17 00000000 - 18 00000000 ;/** - 19 00000000 ; * @addtogroup cortex-m4 - 20 00000000 ; */ - 21 00000000 ;/*@{*/ - 22 00000000 - 23 00000000 E000ED08 - SCB_VTOR - EQU 0xE000ED08 ; Vector Table Offs - et Register - 24 00000000 E000ED04 - NVIC_INT_CTRL - EQU 0xE000ED04 ; interrupt control - state register - 25 00000000 E000ED20 - NVIC_SYSPRI2 - EQU 0xE000ED20 ; system priority r - egister (2) - 26 00000000 00FF0000 - NVIC_PENDSV_PRI - EQU 0x00FF0000 ; PendSV priority v - alue (lowest) - 27 00000000 10000000 - NVIC_PENDSVSET - EQU 0x10000000 ; value to trigger - PendSV exception - 28 00000000 - 29 00000000 AREA |.text|, CODE, READONLY, ALIGN= -2 - 30 00000000 THUMB - 31 00000000 REQUIRE8 - 32 00000000 PRESERVE8 - 33 00000000 - 34 00000000 IMPORT rt_thread_switch_interrupt_flag - 35 00000000 IMPORT rt_interrupt_from_thread - 36 00000000 IMPORT rt_interrupt_to_thread - 37 00000000 - 38 00000000 ;/* - - - -ARM Macro Assembler Page 2 - - - 39 00000000 ; * rt_base_t rt_hw_interrupt_disable(); - 40 00000000 ; */ - 41 00000000 rt_hw_interrupt_disable - PROC - 42 00000000 EXPORT rt_hw_interrupt_disable - 43 00000000 F3EF 8010 MRS r0, PRIMASK - 44 00000004 B672 CPSID I - 45 00000006 4770 BX LR - 46 00000008 ENDP - 47 00000008 - 48 00000008 ;/* - 49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); - 50 00000008 ; */ - 51 00000008 rt_hw_interrupt_enable - PROC - 52 00000008 EXPORT rt_hw_interrupt_enable - 53 00000008 F380 8810 MSR PRIMASK, r0 - 54 0000000C 4770 BX LR - 55 0000000E ENDP - 56 0000000E - 57 0000000E ;/* - 58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 - to); - 59 0000000E ; * r0 --> from - 60 0000000E ; * r1 --> to - 61 0000000E ; */ - 62 0000000E rt_hw_context_switch_interrupt - 63 0000000E EXPORT rt_hw_context_switch_interrupt - 64 0000000E rt_hw_context_switch - PROC - 65 0000000E EXPORT rt_hw_context_switch - 66 0000000E - 67 0000000E ; set rt_thread_switch_interrupt_flag to 1 - 68 0000000E 4A3A LDR r2, =rt_thread_switch_interrupt -_flag - 69 00000010 6813 LDR r3, [r2] - 70 00000012 2B01 CMP r3, #1 - 71 00000014 D004 BEQ _reswitch - 72 00000016 F04F 0301 MOV r3, #1 - 73 0000001A 6013 STR r3, [r2] - 74 0000001C - 75 0000001C 4A37 LDR r2, =rt_interrupt_from_thread ; - set rt_interrupt_f - rom_thread - 76 0000001E 6010 STR r0, [r2] - 77 00000020 - 78 00000020 _reswitch - 79 00000020 4A37 LDR r2, =rt_interrupt_to_thread ; s - et rt_interrupt_to_ - thread - 80 00000022 6011 STR r1, [r2] - 81 00000024 - 82 00000024 4837 LDR r0, =NVIC_INT_CTRL ; trigger th - e PendSV exception - (causes context swi - tch) - 83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET - 84 0000002A 6001 STR r1, [r0] - 85 0000002C 4770 BX LR - - - -ARM Macro Assembler Page 3 - - - 86 0000002E ENDP - 87 0000002E - 88 0000002E ; r0 --> switch from thread stack - 89 0000002E ; r1 --> switch to thread stack - 90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from - ] stack - 91 0000002E PendSV_Handler - PROC - 92 0000002E EXPORT PendSV_Handler - 93 0000002E - 94 0000002E ; disable interrupt to protect context switch - 95 0000002E F3EF 8210 MRS r2, PRIMASK - 96 00000032 B672 CPSID I - 97 00000034 - 98 00000034 ; get rt_thread_switch_interrupt_flag - 99 00000034 4830 LDR r0, =rt_thread_switch_interrupt -_flag - 100 00000036 6801 LDR r1, [r0] - 101 00000038 B351 CBZ r1, pendsv_exit ; pendsv alread - y handled - 102 0000003A - 103 0000003A ; clear rt_thread_switch_interrupt_flag to 0 - 104 0000003A F04F 0100 MOV r1, #0x00 - 105 0000003E 6001 STR r1, [r0] - 106 00000040 - 107 00000040 482E LDR r0, =rt_interrupt_from_thread - 108 00000042 6801 LDR r1, [r0] - 109 00000044 B191 CBZ r1, switch_to_thread ; skip reg - ister save at the f - irst time - 110 00000046 - 111 00000046 F3EF 8109 MRS r1, psp ; get from thread s - tack pointer - 112 0000004A - 113 0000004A IF {FPU} != "SoftVFP" - 114 0000004A F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4] - ) - 115 0000004E BF08 ED21 - 8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi - ster s16~s31 - 116 00000054 ENDIF - 117 00000054 - 118 00000054 E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 - register - 119 00000058 - 120 00000058 IF {FPU} != "SoftVFP" - 121 00000058 F04F 0400 MOV r4, #0x00 ; flag = 0 - 122 0000005C - 123 0000005C F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4] - ) - 124 00000060 BF08 2401 MOVEQ r4, #0x01 ; flag = 1 - 125 00000064 - 126 00000064 F841 4D04 STMFD r1!, {r4} ; push flag - 127 00000068 ENDIF - 128 00000068 - 129 00000068 6800 LDR r0, [r0] - 130 0000006A 6001 STR r1, [r0] ; update from threa - d stack pointer - 131 0000006C - - - -ARM Macro Assembler Page 4 - - - 132 0000006C switch_to_thread - 133 0000006C 4924 LDR r1, =rt_interrupt_to_thread - 134 0000006E 6809 LDR r1, [r1] - 135 00000070 6809 LDR r1, [r1] ; load thread stack - pointer - 136 00000072 - 137 00000072 IF {FPU} != "SoftVFP" - 138 00000072 C908 LDMFD r1!, {r3} ; pop flag - 139 00000074 ENDIF - 140 00000074 - 141 00000074 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 - register - 142 00000078 - 143 00000078 IF {FPU} != "SoftVFP" - 144 00000078 2B00 CMP r3, #0 ; if(flag_r3 != 0) - 145 0000007A BF18 ECB1 - 8B10 VLDMFDNE r1!, {d8 - d15} ; pop FPU regis - ter s16~s31 - 146 00000080 ENDIF - 147 00000080 - 148 00000080 F381 8809 MSR psp, r1 ; update stack poin - ter - 149 00000084 - 150 00000084 IF {FPU} != "SoftVFP" - 151 00000084 F04E 0E10 ORR lr, lr, #0x10 ; lr |= (1 << 4) - , clean FPCA. - 152 00000088 2B00 CMP r3, #0 ; if(flag_r3 != 0) - 153 0000008A BF18 F02E - 0E10 BICNE lr, lr, #0x10 ; lr &= ~(1 << 4) - , set FPCA. - 154 00000090 ENDIF - 155 00000090 - 156 00000090 pendsv_exit - 157 00000090 ; restore interrupt - 158 00000090 F382 8810 MSR PRIMASK, r2 - 159 00000094 - 160 00000094 F04E 0E04 ORR lr, lr, #0x04 - 161 00000098 4770 BX lr - 162 0000009A ENDP - 163 0000009A - 164 0000009A ;/* - 165 0000009A ; * void rt_hw_context_switch_to(rt_uint32 to); - 166 0000009A ; * r0 --> to - 167 0000009A ; * this fucntion is used to perform the first thread sw - itch - 168 0000009A ; */ - 169 0000009A rt_hw_context_switch_to - PROC - 170 0000009A EXPORT rt_hw_context_switch_to - 171 0000009A ; set to thread - 172 0000009A 4919 LDR r1, =rt_interrupt_to_thread - 173 0000009C 6008 STR r0, [r1] - 174 0000009E - 175 0000009E IF {FPU} != "SoftVFP" - 176 0000009E ; CLEAR CONTROL.FPCA - 177 0000009E F3EF 8214 MRS r2, CONTROL ; read - 178 000000A2 F022 0204 BIC r2, #0x04 ; modify - 179 000000A6 F382 8814 MSR CONTROL, r2 ; write-back - 180 000000AA ENDIF - - - -ARM Macro Assembler Page 5 - - - 181 000000AA - 182 000000AA ; set from thread to 0 - 183 000000AA 4914 LDR r1, =rt_interrupt_from_thread - 184 000000AC F04F 0000 MOV r0, #0x0 - 185 000000B0 6008 STR r0, [r1] - 186 000000B2 - 187 000000B2 ; set interrupt flag to 1 - 188 000000B2 4911 LDR r1, =rt_thread_switch_interrupt -_flag - 189 000000B4 F04F 0001 MOV r0, #1 - 190 000000B8 6008 STR r0, [r1] - 191 000000BA - 192 000000BA ; set the PendSV exception priority - 193 000000BA 4813 LDR r0, =NVIC_SYSPRI2 - 194 000000BC F44F 017F LDR r1, =NVIC_PENDSV_PRI - 195 000000C0 F8D0 2000 LDR.W r2, [r0,#0x00] ; read - 196 000000C4 EA41 0102 ORR r1,r1,r2 ; modify - 197 000000C8 6001 STR r1, [r0] ; write-back - 198 000000CA - 199 000000CA ; trigger the PendSV exception (causes context switch) - 200 000000CA 480E LDR r0, =NVIC_INT_CTRL - 201 000000CC F04F 5180 LDR r1, =NVIC_PENDSVSET - 202 000000D0 6001 STR r1, [r0] - 203 000000D2 - 204 000000D2 ; restore MSP - 205 000000D2 480E LDR r0, =SCB_VTOR - 206 000000D4 6800 LDR r0, [r0] - 207 000000D6 6800 LDR r0, [r0] - 208 000000D8 F380 8808 MSR msp, r0 - 209 000000DC - 210 000000DC ; enable interrupts at processor level - 211 000000DC B661 CPSIE F - 212 000000DE B662 CPSIE I - 213 000000E0 - 214 000000E0 ; never reach here! - 215 000000E0 ENDP - 216 000000E0 - 217 000000E0 ; compatible with old version - 218 000000E0 rt_hw_interrupt_thread_switch - PROC - 219 000000E0 EXPORT rt_hw_interrupt_thread_switch - 220 000000E0 4770 BX lr - 221 000000E2 ENDP - 222 000000E2 - 223 000000E2 IMPORT rt_hw_hard_fault_exception - 224 000000E2 EXPORT HardFault_Handler - 225 000000E2 HardFault_Handler - PROC - 226 000000E2 - 227 000000E2 ; get current context - 228 000000E2 F3EF 8009 MRS r0, psp ; get fault thread - stack pointer - 229 000000E6 B500 PUSH {lr} - 230 000000E8 F7FF FFFE BL rt_hw_hard_fault_exception - 231 000000EC F85D EB04 POP {lr} - 232 000000F0 - 233 000000F0 F04E 0E04 ORR lr, lr, #0x04 - 234 000000F4 4770 BX lr - 235 000000F6 ENDP - - - -ARM Macro Assembler Page 6 - - - 236 000000F6 - 237 000000F6 00 00 ALIGN 4 - 238 000000F8 - 239 000000F8 END - 00000000 - 00000000 - 00000000 - E000ED04 - E000ED20 - E000ED08 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int -erwork --depend=.\build\context_rvds.d -o.\build\context_rvds.o -IC:\Users\zylw -w\Documents\Study\CodeHub\rt-thread\bsp\tm4c129x-dk\RTE -IC:\Software\Keil\ARM\ -PACK\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C129 -IC:\Software\Keil\ARM\CMSIS\In -clude --predefine="__UVISION_VERSION SETA 521" --predefine="TM4C129XNCZAD SETA -1" --list=.\context_rvds.lst ../../libcpu/arm/cortex-m4/context_rvds.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 29 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - None -Comment: .text unused -HardFault_Handler 000000E2 - -Symbol: HardFault_Handler - Definitions - At line 225 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 224 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: HardFault_Handler used once -PendSV_Handler 0000002E - -Symbol: PendSV_Handler - Definitions - At line 91 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 92 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: PendSV_Handler used once -_reswitch 00000020 - -Symbol: _reswitch - Definitions - At line 78 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 71 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: _reswitch used once -pendsv_exit 00000090 - -Symbol: pendsv_exit - Definitions - At line 156 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 101 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: pendsv_exit used once -rt_hw_context_switch 0000000E - -Symbol: rt_hw_context_switch - Definitions - At line 64 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 65 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_context_switch used once -rt_hw_context_switch_interrupt 0000000E - -Symbol: rt_hw_context_switch_interrupt - Definitions - At line 62 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 63 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_context_switch_interrupt used once -rt_hw_context_switch_to 0000009A - -Symbol: rt_hw_context_switch_to - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 169 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 170 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_context_switch_to used once -rt_hw_interrupt_disable 00000000 - -Symbol: rt_hw_interrupt_disable - Definitions - At line 41 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 42 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_interrupt_disable used once -rt_hw_interrupt_enable 00000008 - -Symbol: rt_hw_interrupt_enable - Definitions - At line 51 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 52 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_interrupt_enable used once -rt_hw_interrupt_thread_switch 000000E0 - -Symbol: rt_hw_interrupt_thread_switch - Definitions - At line 218 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 219 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_interrupt_thread_switch used once -switch_to_thread 0000006C - -Symbol: switch_to_thread - Definitions - At line 132 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 109 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: switch_to_thread used once -12 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -NVIC_INT_CTRL E000ED04 - -Symbol: NVIC_INT_CTRL - Definitions - At line 24 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 82 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 200 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -NVIC_PENDSVSET 10000000 - -Symbol: NVIC_PENDSVSET - Definitions - At line 27 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 83 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 201 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -NVIC_PENDSV_PRI 00FF0000 - -Symbol: NVIC_PENDSV_PRI - Definitions - At line 26 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 194 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: NVIC_PENDSV_PRI used once -NVIC_SYSPRI2 E000ED20 - -Symbol: NVIC_SYSPRI2 - Definitions - At line 25 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 193 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: NVIC_SYSPRI2 used once -SCB_VTOR E000ED08 - -Symbol: SCB_VTOR - Definitions - At line 23 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 205 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: SCB_VTOR used once -5 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -rt_hw_hard_fault_exception 00000000 - -Symbol: rt_hw_hard_fault_exception - Definitions - At line 223 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 230 in file ../../libcpu/arm/cortex-m4/context_rvds.S -Comment: rt_hw_hard_fault_exception used once -rt_interrupt_from_thread 00000000 - -Symbol: rt_interrupt_from_thread - Definitions - At line 35 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 75 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 107 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 183 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -rt_interrupt_to_thread 00000000 - -Symbol: rt_interrupt_to_thread - Definitions - At line 36 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 79 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 133 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 172 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -rt_thread_switch_interrupt_flag 00000000 - -Symbol: rt_thread_switch_interrupt_flag - Definitions - At line 34 in file ../../libcpu/arm/cortex-m4/context_rvds.S - Uses - At line 68 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 99 in file ../../libcpu/arm/cortex-m4/context_rvds.S - At line 188 in file ../../libcpu/arm/cortex-m4/context_rvds.S - -4 symbols -356 symbols in table diff --git a/bsp/tm4c129x-dk/drivers/drv_eth.c b/bsp/tm4c129x-dk/drivers/drv_eth.c deleted file mode 100644 index baa46f1f01..0000000000 --- a/bsp/tm4c129x-dk/drivers/drv_eth.c +++ /dev/null @@ -1,1444 +0,0 @@ -/* - * File : drv_eth.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-25 ArdaFu Port to TM4C129X - */ - -/** - * @file - tivaif.c - * lwIP Ethernet interface for Stellaris LM4F Devices - * - */ - -/** - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICui32AR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/** - * Copyright (c) 2008-2012 Texas Instruments Incorporated - * - * This file is derived from the ``ethernetif.c'' skeleton Ethernet network - * interface driver for lwIP. - * - */ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include "lwip/tcpip.h" -#include "netif/etharp.h" -#include "netif/ppp_oe.h" - - -/** - * Sanity Check: This interface driver will NOT work if the following defines - * are incorrect. - * - */ -#if (PBUF_LINK_HLEN != 16) -#error "PBUF_LINK_HLEN must be 16 for this interface driver!" -#endif -#if (ETH_PAD_SIZE != 0) -#error "ETH_PAD_SIZE must be 0 for this interface driver!" -#endif -#if (!SYS_LIGHTWEIGHT_PROT) -#error "SYS_LIGHTWEIGHT_PROT must be enabled for this interface driver!" -#endif - -/** - * Set the physical address of the PHY we will be using if this is not - * specified in lwipopts.h. We assume 0 for the internal PHY. - */ -#ifndef PHY_PHYS_ADDR -#define PHY_PHYS_ADDR 0 -#endif - -#ifndef EMAC_PHY_CONFIG -#define EMAC_PHY_CONFIG (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN | \ - EMAC_PHY_AN_100B_T_FULL_DUPLEX) -#endif - -/** - * If necessary, set the defaui32t number of transmit and receive DMA descriptors - * used by the Ethernet MAC. - * - */ -#ifndef NUM_RX_DESCRIPTORS -#define NUM_RX_DESCRIPTORS 4 -#endif - -#ifndef NUM_TX_DESCRIPTORS -#define NUM_TX_DESCRIPTORS 8 -#endif - -/** - * Setup processing for PTP (IEEE-1588). - * - */ -#if LWIP_PTPD -extern uint32_t g_ui32SysClk; -extern uint32_t g_ui32PTPTickRate; -extern void lwIPHostGetTime(u32_t *time_s, u32_t *time_ns); -#endif - -/** - * Stellaris DriverLib Header Files required for this interface driver. - * - */ -#include -#include -#include "inc/hw_emac.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" - -#include "driverlib/emac.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/flash.h" -#include "driverlib/interrupt.h" - -#include "driverlib/pin_map.h" -#include "driverlib/rom_map.h" -#include "driverlib/gpio.h" - -#include -#include "lwipopts.h" -#include "drv_eth.h" - -/** - * A structure used to keep track of driver state and error counts. - */ -typedef struct { - uint32_t ui32TXCount; - uint32_t ui32TXCopyCount; - uint32_t ui32TXCopyFailCount; - uint32_t ui32TXNoDescCount; - uint32_t ui32TXBufQueuedCount; - uint32_t ui32TXBufFreedCount; - uint32_t ui32RXBufReadCount; - uint32_t ui32RXPacketReadCount; - uint32_t ui32RXPacketErrCount; - uint32_t ui32RXPacketCBErrCount; - uint32_t ui32RXNoBufCount; -} -tDriverStats; - -tDriverStats g_sDriverStats; - -#ifdef DEBUG -/** - * Note: This rather weird construction where we invoke the macro with the - * name of the field minus its Hungarian prefix is a workaround for a problem - * experienced with GCC which does not like concatenating tokens after an - * operator, specifically '.' or '->', in a macro. - */ -#define DRIVER_STATS_INC(x) do{ g_sDriverStats.ui32##x++; } while(0) -#define DRIVER_STATS_DEC(x) do{ g_sDriverStats.ui32##x--; } while(0) -#define DRIVER_STATS_ADD(x, inc) do{ g_sDriverStats.ui32##x += (inc); } while(0) -#define DRIVER_STATS_SUB(x, dec) do{ g_sDriverStats.ui32##x -= (dec); } while(0) -#else -#define DRIVER_STATS_INC(x) -#define DRIVER_STATS_DEC(x) -#define DRIVER_STATS_ADD(x, inc) -#define DRIVER_STATS_SUB(x, dec) -#endif - -/** - * Helper struct holding a DMA descriptor and the pbuf it currently refers - * to. - */ -typedef struct { - tEMACDMADescriptor Desc; - struct pbuf *pBuf; -} tDescriptor; - -typedef struct { - tDescriptor *pDescriptors; - uint32_t ui32NumDescs; - uint32_t ui32Read; - uint32_t ui32Write; -} tDescriptorList; - -/** - * Helper struct to hold private data used to operate your ethernet interface. - * Keeping the ethernet address of the MAC in this struct is not necessary - * as it is already kept in the struct netif. - * But this is only an example, anyway... - */ -typedef struct { - struct eth_addr *ethaddr; - /* Add whatever per-interface state that is needed here. */ - tDescriptorList *pTxDescList; - tDescriptorList *pRxDescList; -} tStellarisIF; - -/** - * Global variable for this interface's private data. Needed to allow - * the interrupt handlers access to this information outside of the - * context of the lwIP netif. - * - */ -tDescriptor g_pTxDescriptors[NUM_TX_DESCRIPTORS]; -tDescriptor g_pRxDescriptors[NUM_RX_DESCRIPTORS]; -tDescriptorList g_TxDescList = { - g_pTxDescriptors, NUM_TX_DESCRIPTORS, 0, 0 -}; -tDescriptorList g_RxDescList = { - g_pRxDescriptors, NUM_RX_DESCRIPTORS, 0, 0 -}; -static tStellarisIF g_StellarisIFData = { - 0, &g_TxDescList, &g_RxDescList -}; - -/** - * Interrupt counters (for debug purposes). - */ -volatile uint32_t g_ui32NormalInts; -volatile uint32_t g_ui32AbnormalInts; - -/** - * A macro which determines whether a pointer is within the SRAM address - * space and, hence, points to a buffer that the Ethernet MAC can directly - * DMA from. - */ -#define PTR_SAFE_FOR_EMAC_DMA(ptr) (((uint32_t)(ptr) >= 0x2000000) && \ - ((uint32_t)(ptr) < 0x20070000)) - - -typedef struct -{ - /* inherit from ethernet device */ - struct eth_device parent; - tStellarisIF* dma_if; - /* for rx_thread async get pbuf */ - rt_mailbox_t rx_pbuf_mb; -} net_device; -typedef net_device* net_device_t; - -static char rx_pbuf_mb_pool[8*4]; -static struct rt_mailbox eth_rx_pbuf_mb; -static net_device eth_dev_entry; -static net_device_t eth_dev = ð_dev_entry; - -/** - * Initialize the transmit and receive DMA descriptor lists. - */ -void -InitDMADescriptors(void) -{ - uint32_t ui32Loop; - - /* Transmit list - mark all descriptors as not owned by the hardware */ - for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++) - { - g_pTxDescriptors[ui32Loop].pBuf = (struct pbuf *)0; - g_pTxDescriptors[ui32Loop].Desc.ui32Count = 0; - g_pTxDescriptors[ui32Loop].Desc.pvBuffer1 = 0; - g_pTxDescriptors[ui32Loop].Desc.DES3.pLink = - ((ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ? - &g_pTxDescriptors[0].Desc : &g_pTxDescriptors[ui32Loop + 1].Desc); - g_pTxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_TX_CTRL_INTERRUPT | - DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_IP_ALL_CKHSUMS; - - } - - g_TxDescList.ui32Read = 0; - g_TxDescList.ui32Write = 0; - - - /* Receive list - tag each descriptor with a pbuf and set all fields to - * allow packets to be received. - */ - for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++) - { - g_pRxDescriptors[ui32Loop].pBuf = pbuf_alloc(PBUF_RAW, PBUF_POOL_BUFSIZE, - PBUF_POOL); - g_pRxDescriptors[ui32Loop].Desc.ui32Count = DES1_RX_CTRL_CHAINED; - if(g_pRxDescriptors[ui32Loop].pBuf) - { - /* Set the DMA to write directly into the pbuf payload. */ - g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = - g_pRxDescriptors[ui32Loop].pBuf->payload; - g_pRxDescriptors[ui32Loop].Desc.ui32Count |= - (g_pRxDescriptors[ui32Loop].pBuf->len << DES1_RX_CTRL_BUFF1_SIZE_S); - g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = DES0_RX_CTRL_OWN; - } - else - { - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_init: pbuf_alloc error\n")); - - /* No pbuf available so leave the buffer pointer empty. */ - g_pRxDescriptors[ui32Loop].Desc.pvBuffer1 = 0; - g_pRxDescriptors[ui32Loop].Desc.ui32CtrlStatus = 0; - } - g_pRxDescriptors[ui32Loop].Desc.DES3.pLink = - ((ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ? - &g_pRxDescriptors[0].Desc : &g_pRxDescriptors[ui32Loop + 1].Desc); - } - - g_TxDescList.ui32Read = 0; - g_TxDescList.ui32Write = 0; - - // - // Set the descriptor pointers in the hardware. - // - EMACRxDMADescriptorListSet(EMAC0_BASE, &g_pRxDescriptors[0].Desc); - EMACTxDMADescriptorListSet(EMAC0_BASE, &g_pTxDescriptors[0].Desc); -} - -/** - * In this function, the hardware should be initialized. - * Called from tivaif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -static void -tivaif_hwinit(struct netif *psNetif) -{ - uint16_t ui16Val; - - /* Initialize the DMA descriptors. */ - InitDMADescriptors(); - - /* Clear any stray PHY interrupts that may be set. */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2); - - /* Configure and enable the link status change interrupt in the PHY. */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR); - ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT); - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val); - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN | - EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN)); - - /* Read the PHY interrupt status to clear any stray events. */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - - /** - * Set MAC filtering options. We receive all broadcast and mui32ticast - * packets along with those addressed specifically for us. - */ - EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_HASH_AND_PERFECT | - EMAC_FRMFILTER_PASS_MULTICAST)); - -#if LWIP_PTPD - // - // Enable timestamping on all received packets. - // - // We set the fine clock adjustment mode and configure the subsecond - // increment to half the 25MHz PTPD clock. This will give us maximum control - // over the clock rate adjustment and keep the arithmetic easy later. It - // should be possible to synchronize with higher accuracy than this with - // appropriate juggling of the subsecond increment count and the addend - // register value, though. - // - EMACTimestampConfigSet(EMAC0_BASE, (EMAC_TS_ALL_RX_FRAMES | - EMAC_TS_DIGITAL_ROLLOVER | - EMAC_TS_PROCESS_IPV4_UDP | EMAC_TS_ALL | - EMAC_TS_PTP_VERSION_1 | EMAC_TS_UPDATE_FINE), - (1000000000 / (25000000 / 2))); - EMACTimestampAddendSet(EMAC0_BASE, 0x80000000); - EMACTimestampEnable(EMAC0_BASE); -#endif - - /* Clear any pending MAC interrupts. */ - EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false)); - - /* Enable the Ethernet MAC transmitter and receiver. */ - EMACTxEnable(EMAC0_BASE); - EMACRxEnable(EMAC0_BASE); - - /* Enable the Ethernet RX and TX interrupt source. */ - EMACIntEnable(EMAC0_BASE, (EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT | - EMAC_INT_TX_STOPPED | EMAC_INT_RX_NO_BUFFER | - EMAC_INT_RX_STOPPED | EMAC_INT_PHY)); - - /* Enable the Ethernet interrupt. */ - IntEnable(INT_EMAC0); - - /* Enable all processor interrupts. */ - IntMasterEnable(); - - /* Tell the PHY to start an auto-negotiation cycle. */ - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, (EPHY_BMCR_ANEN | - EPHY_BMCR_RESTARTAN)); -} - -#ifdef DEBUG -/** - * Dump the chain of pbuf pointers to the debug output. - */ -void -tivaif_trace_pbuf(const char *pcTitle, struct pbuf *p) -{ - LWIP_DEBUGF(NETIF_DEBUG, ("%s %08x (%d, %d)", pcTitle, p, p->tot_len, - p->len)); - - do - { - p = p->next; - if(p) - { - LWIP_DEBUGF(NETIF_DEBUG, ("->%08x(%d)", p, p->len)); - } - else - { - LWIP_DEBUGF(NETIF_DEBUG, ("->%08x", p)); - } - - } while((p != NULL) && (p->tot_len != p->len)); - - LWIP_DEBUGF(NETIF_DEBUG, ("\n")); -} -#endif - -/** - * This function is used to check whether a passed pbuf contains only buffers - * resident in regions of memory that the Ethernet MAC can access. If any - * buffers in the chain are outside a directly-DMAable section of memory, - * the pbuf is copied to SRAM and a different pointer returned. If all - * buffers are safe, the pbuf reference count is incremented and the original - * pointer returned. - */ -static struct pbuf * -tivaif_check_pbuf(struct pbuf *p) -{ - struct pbuf *pBuf; - rt_err_t Err; - - pBuf = p; - -#ifdef DEBUG - tivaif_trace_pbuf("Original:", p); -#endif - - /* Walk the list of buffers in the pbuf checking each. */ - do - { - /* Does this pbuf's payload reside in memory that the Ethernet DMA - * can access? - */ - if(!PTR_SAFE_FOR_EMAC_DMA(pBuf->payload)) - { - /* This buffer is outside the DMA-able memory space so we need - * to copy the pbuf. - */ - pBuf = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_POOL); - - /* If we got a new pbuf... */ - if(pBuf) - { - /* ...copy the old pbuf into the new one. */ - Err = pbuf_copy(pBuf, p); - - /* If we failed to copy the pbuf, free the newly allocated one - * and make sure we return a NULL to show a problem. - */ - if(Err != RT_EOK) - { - DRIVER_STATS_INC(TXCopyFailCount); - pbuf_free(pBuf); - pBuf = NULL; - } - else - { -#ifdef DEBUG - tivaif_trace_pbuf("Copied:", pBuf); -#endif - DRIVER_STATS_INC(TXCopyCount); - - /* Reduce the reference count on the original pbuf since - * we're not going to hold on to it after returning from - * tivaif_transmit. Note that we already bumped - * the reference count at the top of tivaif_transmit. - */ - pbuf_free(p); - } - } - - /* Send back the new pbuf pointer or NULL if an error occurred. */ - return(pBuf); - } - - /* Move on to the next buffer in the queue */ - pBuf = pBuf->next; - } - while(pBuf); - - /** - * If we get here, the passed pbuf can be safely used without needing to - * be copied. - */ - return(p); -} - -/** - * This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf might be - * chained. - * - * @param psNetif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return RT_EOK if the packet coui32d be sent - * an err_t value if the packet coui32dn't be sent - */ -static rt_err_t -tivaif_transmit(net_device_t dev, struct pbuf *p) -{ - tStellarisIF *pIF; - tDescriptor *pDesc; - struct pbuf *pBuf; - uint32_t ui32NumChained, ui32NumDescs; - bool bFirst; - SYS_ARCH_DECL_PROTECT(lev); - - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_transmit 0x%08x, len %d\n", p, - p->tot_len)); - - /** - * This entire function must run within a "critical section" to preserve - * the integrity of the transmit pbuf queue. - */ - SYS_ARCH_PROTECT(lev); - - /* Update our transmit attempt counter. */ - DRIVER_STATS_INC(TXCount); - - /** - * Increase the reference count on the packet provided so that we can - * hold on to it until we are finished transmitting its content. - */ - pbuf_ref(p); - - /** - * Determine whether all buffers passed are within SRAM and, if not, copy - * the pbuf into SRAM-resident buffers so that the Ethernet DMA can access - * the data. - */ - p = tivaif_check_pbuf(p); - - /* Make sure we still have a valid buffer (it may have been copied) */ - if(!p) - { - LINK_STATS_INC(link.memerr); - SYS_ARCH_UNPROTECT(lev); - return(-RT_ENOMEM); - } - - /* Get our state data from the netif structure we were passed. */ - //pIF = (tStellarisIF *)psNetif->state; - pIF = dev->dma_if; - - /* Make sure that the transmit descriptors are not all in use */ - pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]); - if(pDesc->pBuf) - { - /** - * The current write descriptor has a pbuf attached to it so this - * implies that the ring is fui32l. Reject this transmit request with a - * memory error since we can't satisfy it just now. - */ - pbuf_free(p); - LINK_STATS_INC(link.memerr); - DRIVER_STATS_INC(TXNoDescCount); - SYS_ARCH_UNPROTECT(lev); - return (-RT_ENOMEM); - } - - /* How many pbufs are in the chain passed? */ - ui32NumChained = (uint32_t)pbuf_clen(p); - - /* How many free transmit descriptors do we have? */ - ui32NumDescs = (pIF->pTxDescList->ui32Read > pIF->pTxDescList->ui32Write) ? - (pIF->pTxDescList->ui32Read - pIF->pTxDescList->ui32Write) : - ((NUM_TX_DESCRIPTORS - pIF->pTxDescList->ui32Write) + - pIF->pTxDescList->ui32Read); - - /* Do we have enough free descriptors to send the whole packet? */ - if(ui32NumDescs < ui32NumChained) - { - /* No - we can't transmit this whole packet so return an error. */ - pbuf_free(p); - LINK_STATS_INC(link.memerr); - DRIVER_STATS_INC(TXNoDescCount); - SYS_ARCH_UNPROTECT(lev); - return (-RT_ENOMEM); - } - - /* Tag the first descriptor as the start of the packet. */ - bFirst = true; - pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG; - - /* Here, we know we can send the packet so write it to the descriptors */ - pBuf = p; - - while(ui32NumChained) - { - /* Get a pointer to the descriptor we will write next. */ - pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]); - - /* Fill in the buffer pointer and length */ - pDesc->Desc.ui32Count = (uint32_t)pBuf->len; - pDesc->Desc.pvBuffer1 = pBuf->payload; - - /* Tag the first descriptor as the start of the packet. */ - if(bFirst) - { - bFirst = false; - pDesc->Desc.ui32CtrlStatus = DES0_TX_CTRL_FIRST_SEG; - } - else - { - pDesc->Desc.ui32CtrlStatus = 0; - } - - pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_IP_ALL_CKHSUMS | - DES0_TX_CTRL_CHAINED); - - /* Decrement our descriptor counter, move on to the next buffer in the - * pbuf chain. */ - ui32NumChained--; - pBuf = pBuf->next; - - /* Update the descriptor list write index. */ - pIF->pTxDescList->ui32Write++; - if(pIF->pTxDescList->ui32Write == NUM_TX_DESCRIPTORS) - { - pIF->pTxDescList->ui32Write = 0; - } - - /* If this is the last descriptor, mark it as the end of the packet. */ - if(!ui32NumChained) - { - pDesc->Desc.ui32CtrlStatus |= (DES0_TX_CTRL_LAST_SEG | - DES0_TX_CTRL_INTERRUPT); - - /* Tag the descriptor with the original pbuf pointer. */ - pDesc->pBuf = p; - } - else - { - /* Set the lsb of the pbuf pointer. We use this as a signal that - * we should not free the pbuf when we are walking the descriptor - * list while processing the transmit interrupt. We only free the - * pbuf when processing the last descriptor used to transmit its - * chain. - */ - pDesc->pBuf = (struct pbuf *)((uint32_t)p + 1); - } - - DRIVER_STATS_INC(TXBufQueuedCount); - - /* Hand the descriptor over to the hardware. */ - pDesc->Desc.ui32CtrlStatus |= DES0_TX_CTRL_OWN; - } - - /* Tell the transmitter to start (in case it had stopped). */ - EMACTxDMAPollDemand(EMAC0_BASE); - - /* Update lwIP statistics */ - LINK_STATS_INC(link.xmit); - - SYS_ARCH_UNPROTECT(lev); - - return(RT_EOK); -} - -/** - * This function will process all transmit descriptors and free pbufs attached - * to any that have been transmitted since we last checked. - * - * This function is called only from the Ethernet interrupt handler. - * - * @param netif the lwip network interface structure for this ethernetif - * @return None. - */ -static void -tivaif_process_transmit(tStellarisIF *pIF) -{ - tDescriptorList *pDescList; - uint32_t ui32NumDescs; - - /* Get a pointer to the transmit descriptor list. */ - pDescList = pIF->pTxDescList; - - /* Walk the list until we have checked all descriptors or we reach the - * write pointer or find a descriptor that the hardware is still working - * on. - */ - for(ui32NumDescs = 0; ui32NumDescs < pDescList->ui32NumDescs; ui32NumDescs++) - { - /* Has the buffer attached to this descriptor been transmitted? */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_TX_CTRL_OWN) - { - /* No - we're finished. */ - break; - } - - /* Does this descriptor have a buffer attached to it? */ - if(pDescList->pDescriptors[pDescList->ui32Read].pBuf) - { - /* Yes - free it if it's not marked as an intermediate pbuf */ - if(!((uint32_t)(pDescList->pDescriptors[pDescList->ui32Read].pBuf) & 1)) - { - pbuf_free(pDescList->pDescriptors[pDescList->ui32Read].pBuf); - DRIVER_STATS_INC(TXBufFreedCount); - } - pDescList->pDescriptors[pDescList->ui32Read].pBuf = NULL; - } - else - { - /* If the descriptor has no buffer, we are finished. */ - break; - } - - /* Move on to the next descriptor. */ - pDescList->ui32Read++; - if(pDescList->ui32Read == pDescList->ui32NumDescs) - { - pDescList->ui32Read = 0; - } - } -} - -/** - * This function will process all receive descriptors that contain newly read - * data and pass complete frames up the lwIP stack as they are found. The - * timestamp of the packet will be placed into the pbuf structure if PTPD is - * enabled. - * - * This function is called only from the Ethernet interrupt handler. - * - * @param psNetif the lwip network interface structure for this ethernetif - * @return None. - */ -static void -tivaif_receive(net_device_t dev) -{ - tDescriptorList *pDescList; - tStellarisIF *pIF; - struct pbuf *pBuf; - uint32_t ui32DescEnd; - - /* Get a pointer to our state data */ - pIF = dev->dma_if; - - /* Get a pointer to the receive descriptor list. */ - pDescList = pIF->pRxDescList; - - /* Start with a NULL pbuf so that we don't try to link chain the first - * time round. - */ - pBuf = NULL; - - /* Determine where we start and end our walk of the descriptor list */ - ui32DescEnd = pDescList->ui32Read ? (pDescList->ui32Read - 1) : (pDescList->ui32NumDescs - 1); - - /* Step through the descriptors that are marked for CPU attention. */ - while(pDescList->ui32Read != ui32DescEnd) - { - /* Does the current descriptor have a buffer attached to it? */ - if(pDescList->pDescriptors[pDescList->ui32Read].pBuf) - { - /* Yes - determine if the host has filled it yet. */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_CTRL_OWN) - { - /* The DMA engine still owns the descriptor so we are finished */ - break; - } - - DRIVER_STATS_INC(RXBufReadCount); - - /* If this descriptor contains the end of the packet, fix up the - * buffer size accordingly. - */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_LAST_DESC) - { - /* This is the last descriptor for the frame so fix up the - * length. It is safe for us to modify the internal fields - * directly here (rather than calling pbuf_realloc) since we - * know each of these pbufs is never chained. - */ - pDescList->pDescriptors[pDescList->ui32Read].pBuf->len = - (pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_FRAME_LENGTH_M) >> - DES0_RX_STAT_FRAME_LENGTH_S; - pDescList->pDescriptors[pDescList->ui32Read].pBuf->tot_len = - pDescList->pDescriptors[pDescList->ui32Read].pBuf->len; - } - - if(pBuf) - { - /* Link this pbuf to the last one we looked at since this buffer - * is a continuation of an existing frame (split across mui32tiple - * pbufs). Note that we use pbuf_cat() here rather than - * pbuf_chain() since we don't want to increase the reference - * count of either pbuf - we only want to link them together. - */ - pbuf_cat(pBuf, pDescList->pDescriptors[pDescList->ui32Read].pBuf); - pDescList->pDescriptors[pDescList->ui32Read].pBuf = pBuf; - } - - /* Remember the buffer associated with this descriptor. */ - pBuf = pDescList->pDescriptors[pDescList->ui32Read].pBuf; - - /* Is this the last descriptor for the current frame? */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_LAST_DESC) - { - /* Yes - does the frame contain errors? */ - if(pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus & - DES0_RX_STAT_ERR) - { - /* This is a bad frame so discard it and update the relevant - * statistics. - */ - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: packet error\n")); - pbuf_free(pBuf); - LINK_STATS_INC(link.drop); - DRIVER_STATS_INC(RXPacketErrCount); - } - else - { - /* This is a good frame so pass it up the stack. */ - LINK_STATS_INC(link.recv); - DRIVER_STATS_INC(RXPacketReadCount); - -#if LWIP_PTPD - /* Place the timestamp in the PBUF if PTPD is enabled */ - pBuf->time_s = - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeHi; - pBuf->time_ns = - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32IEEE1588TimeLo; -#endif - -#if NO_SYS - if(ethernet_input(pBuf, psNetif) != RT_EOK) - { -#else - //if(tcpip_input(pBuf, psNetif) != RT_EOK) - if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) || - (eth_device_ready(&(dev->parent)) != RT_EOK)) - { -#endif - /* drop the packet */ - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_input: input error\n")); - pbuf_free(pBuf); - - /* Adjust the link statistics */ - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - DRIVER_STATS_INC(RXPacketCBErrCount); - } - - /* We're finished with this packet so make sure we don't try - * to link the next buffer to it. - */ - pBuf = NULL; - } - } - } - - /* Allocate a new buffer for this descriptor */ - pDescList->pDescriptors[pDescList->ui32Read].pBuf = pbuf_alloc(PBUF_RAW, - PBUF_POOL_BUFSIZE, - PBUF_POOL); - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count = - DES1_RX_CTRL_CHAINED; - if(pDescList->pDescriptors[pDescList->ui32Read].pBuf) - { - /* We got a buffer so fill in the payload pointer and size. */ - pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = - pDescList->pDescriptors[pDescList->ui32Read].pBuf->payload; - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32Count |= - (pDescList->pDescriptors[pDescList->ui32Read].pBuf->len << - DES1_RX_CTRL_BUFF1_SIZE_S); - - /* Give this descriptor back to the hardware */ - pDescList->pDescriptors[pDescList->ui32Read].Desc.ui32CtrlStatus = - DES0_RX_CTRL_OWN; - } - else - { - LWIP_DEBUGF(NETIF_DEBUG, ("tivaif_receive: pbuf_alloc error\n")); - - pDescList->pDescriptors[pDescList->ui32Read].Desc.pvBuffer1 = 0; - - /* Update the stats to show we coui32dn't allocate a pbuf. */ - DRIVER_STATS_INC(RXNoBufCount); - LINK_STATS_INC(link.memerr); - - /* Stop parsing here since we can't leave a broken descriptor in - * the chain. - */ - break; - } - - /* Move on to the next descriptor in the chain, taking care to wrap. */ - pDescList->ui32Read++; - if(pDescList->ui32Read == pDescList->ui32NumDescs) - { - pDescList->ui32Read = 0; - } - } -} - -/** - * Process interrupts from the PHY. - * - * should be called from the Stellaris Ethernet Interrupt Handler. This - * function will read packets from the Stellaris Ethernet fifo and place them - * into a pbuf queue. If the transmitter is idle and there is at least one packet - * on the transmit queue, it will place it in the transmit fifo and start the - * transmitter. - * - */ -void -tivaif_process_phy_interrupt(net_device_t dev) -{ - uint16_t ui16Val, ui16Status; - uint32_t ui32Config, ui32Mode, ui32RxMaxFrameSize; - - /* Read the PHY interrupt status. This clears all interrupt sources. - * Note that we are only enabling sources in EPHY_MISR1 so we don't - * read EPHY_MISR2. - */ - ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - - /* - * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register - */ - EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); - /* Read the current PHY status. */ - ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS); - - /* Has the link status changed? */ - if(ui16Val & EPHY_MISR1_LINKSTAT) - { - /* Is link up or down now? */ - if(ui16Status & EPHY_STS_LINK) - { - /* Tell lwIP the link is up. */ -#if NO_SYS - netif_set_link_up(psNetif); -#else - //tcpip_callback((tcpip_callback_fn)netif_set_link_up, psNetif); - eth_device_linkchange(&(dev->parent), RT_TRUE); -#endif - - /* In this case we drop through since we may need to reconfigure - * the MAC depending upon the speed and half/fui32l-duplex settings. - */ - } - else - { - /* Tell lwIP the link is down */ -#if NO_SYS - netif_set_link_down(psNetif); -#else - //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif); - eth_device_linkchange(&(dev->parent), RT_FALSE); -#endif - } - } - - /* Has the speed or duplex status changed? */ - if(ui16Val & (EPHY_MISR1_SPEED | EPHY_MISR1_SPEED | EPHY_MISR1_ANC)) - { - /* Get the current MAC configuration. */ - EMACConfigGet(EMAC0_BASE, &ui32Config, &ui32Mode, - &ui32RxMaxFrameSize); - - /* What speed is the interface running at now? - */ - if(ui16Status & EPHY_STS_SPEED) - { - /* 10Mbps is selected */ - ui32Config &= ~EMAC_CONFIG_100MBPS; - } - else - { - /* 100Mbps is selected */ - ui32Config |= EMAC_CONFIG_100MBPS; - } - - /* Are we in fui32l- or half-duplex mode? */ - if(ui16Status & EPHY_STS_DUPLEX) - { - /* Fui32l duplex. */ - ui32Config |= EMAC_CONFIG_FULL_DUPLEX; - } - else - { - /* Half duplex. */ - ui32Config &= ~EMAC_CONFIG_FULL_DUPLEX; - } - - /* Reconfigure the MAC */ - EMACConfigSet(EMAC0_BASE, ui32Config, ui32Mode, ui32RxMaxFrameSize); - } -} - -/** - * Process tx and rx packets at the low-level interrupt. - * - * should be called from the Stellaris Ethernet Interrupt Handler. This - * function will read packets from the Stellaris Ethernet fifo and place them - * into a pbuf queue. If the transmitter is idle and there is at least one packet - * on the transmit queue, it will place it in the transmit fifo and start the - * transmitter. - * - */ -void -tivaif_interrupt(net_device_t dev, uint32_t ui32Status) -{ - - /* Update our debug interrupt counters. */ - if(ui32Status & EMAC_INT_NORMAL_INT) - { - g_ui32NormalInts++; - } - - if(ui32Status & EMAC_INT_ABNORMAL_INT) - { - g_ui32AbnormalInts++; - } - - /* Is this an interrupt from the PHY? */ - if(ui32Status & EMAC_INT_PHY) - { - tivaif_process_phy_interrupt(dev); - } - - /* Process the transmit DMA list, freeing any buffers that have been - * transmitted since our last interrupt. - */ - if(ui32Status & EMAC_INT_TRANSMIT) - { - tivaif_process_transmit(dev->dma_if); - } - - /** - * Process the receive DMA list and pass all successfui32ly received packets - * up the stack. We also call this function in cases where the receiver has - * stalled due to missing buffers since the receive function will attempt to - * allocate new pbufs for descriptor entries which have none. - */ - if(ui32Status & (EMAC_INT_RECEIVE | EMAC_INT_RX_NO_BUFFER | - EMAC_INT_RX_STOPPED)) - { - tivaif_receive(dev); - } -} - -#if NETIF_DEBUG -/* Print an IP header by using LWIP_DEBUGF - * @param p an IP packet, p->payload pointing to the IP header - */ -void -tivaif_debug_print(struct pbuf *p) -{ - struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload; - u16_t *plen = (u16_t *)p->payload; - - LWIP_DEBUGF(NETIF_DEBUG, ("ETH header:\n")); - LWIP_DEBUGF(NETIF_DEBUG, ("Packet Length:%5"U16_F" \n",*plen)); - LWIP_DEBUGF(NETIF_DEBUG, ("Destination: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n", - ethhdr->dest.addr[0], - ethhdr->dest.addr[1], - ethhdr->dest.addr[2], - ethhdr->dest.addr[3], - ethhdr->dest.addr[4], - ethhdr->dest.addr[5])); - LWIP_DEBUGF(NETIF_DEBUG, ("Source: %02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"-%02"X8_F"\n", - ethhdr->src.addr[0], - ethhdr->src.addr[1], - ethhdr->src.addr[2], - ethhdr->src.addr[3], - ethhdr->src.addr[4], - ethhdr->src.addr[5])); - LWIP_DEBUGF(NETIF_DEBUG, ("Packet Type:0x%04"U16_F" \n", ethhdr->type)); -} -#endif /* NETIF_DEBUG */ - -void lwIPEthernetIntHandler(void) -{ - uint32_t ui32Status; -#ifdef DEF_INT_TEMPSTAMP - uint32_t ui32TimerStatus; -#endif - // - // Read and Clear the interrupt. - // - ui32Status = MAP_EMACIntStatus(EMAC0_BASE, true); - - // - // If the interrupt really came from the Ethernet and not our - // timer, clear it. - // - if(ui32Status) - { - MAP_EMACIntClear(EMAC0_BASE, ui32Status); - } -#ifdef DEF_INT_TEMPSTAMP - // - // Check to see whether a hardware timer interrupt has been reported. - // - if(ui32Status & EMAC_INT_TIMESTAMP) - { - // - // Yes - read and clear the timestamp interrupt status. - // - ui32TimerStatus = EMACTimestampIntStatus(EMAC0_BASE); - - // - // If a timer interrupt handler has been registered, call it. - // - if(g_pfnTimerHandler) - { - g_pfnTimerHandler(EMAC0_BASE, ui32TimerStatus); - } - } -#endif - // - // The handling of the interrupt is different based on the use of a RTOS. - // - - // - // No RTOS is being used. If a transmit/receive interrupt was active, - // run the low-level interrupt handler. - // - if(ui32Status) - { - tivaif_interrupt(eth_dev, ui32Status); - } - - // - // Service the lwIP timers. - // - //lwIPServiceTimers(); -} - - -// OUI:00-12-37 (hex) Texas Instruments, only for test -static int tiva_eth_mac_addr_init(void) -{ - int retVal =0; - uint32_t ulUser[2]; - uint8_t mac_addr[6]; - - MAP_FlashUserGet(&ulUser[0], &ulUser[1]); - if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff)) - { - rt_kprintf("Fail to get mac address from eeprom.\n"); - rt_kprintf("Using default mac address\n"); - // OUI:00-12-37 (hex) Texas Instruments, only for test - // Configure the hardware MAC address - ulUser[0] = 0x00371200; - ulUser[1] = 0x00563412; - //FlashUserSet(ulUser0, ulUser1); - retVal =-1; - } - - - //Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC - //address needed to program the hardware registers, then program the MAC - //address into the Ethernet Controller registers. - - mac_addr[0] = ((ulUser[0] >> 0) & 0xff); - mac_addr[1] = ((ulUser[0] >> 8) & 0xff); - mac_addr[2] = ((ulUser[0] >> 16) & 0xff); - mac_addr[3] = ((ulUser[1] >> 0) & 0xff); - mac_addr[4] = ((ulUser[1] >> 8) & 0xff); - mac_addr[5] = ((ulUser[1] >> 16) & 0xff); - - // - // Program the hardware with its MAC address (for filtering). - // - MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr); - return retVal; -} - - void tiva_eth_lowlevel_init(void) -{ - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); - // - // PF1/PK4/PK6 are used for Ethernet LEDs. - // - MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0); - MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1); - GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0); - GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4); - - // - // Enable the ethernet peripheral. - // - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); - MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); - // - // Enable the internal PHY if it's present and we're being - // asked to use it. - // - if((EMAC_PHY_CONFIG & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL) - { - // - // We've been asked to configure for use with the internal - // PHY. Is it present? - // - if(SysCtlPeripheralPresent(SYSCTL_PERIPH_EPHY0)) - { - // - // Yes - enable and reset it. - // - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); - MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); - } - else - { - // - // Internal PHY is not present on this part so hang here. - // - rt_kprintf("Internal PHY is not present on this part.\n"); - while(1) - { - } - } - } - - // - // Wait for the MAC to come out of reset. - // - while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0)) - { - } - - // - // Configure for use with whichever PHY the user requires. - // - MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG); - - // - // Initialize the MAC and set the DMA mode. - // - MAP_EMACInit(EMAC0_BASE, 120000000, //system clock = 120MHz - EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED, - 4, 4, 0); - - // - // Set MAC configuration options. - // - MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX | - EMAC_CONFIG_CHECKSUM_OFFLOAD | - EMAC_CONFIG_7BYTE_PREAMBLE | - EMAC_CONFIG_IF_GAP_96BITS | - EMAC_CONFIG_USE_MACADDR0 | - EMAC_CONFIG_SA_FROM_DESCRIPTOR | - EMAC_CONFIG_BO_LIMIT_1024), - (EMAC_MODE_RX_STORE_FORWARD | - EMAC_MODE_TX_STORE_FORWARD | - EMAC_MODE_TX_THRESHOLD_64_BYTES | - EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); - - EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler); - -} - -static rt_err_t eth_dev_init(rt_device_t device) -{ - net_device_t net_dev = (net_device_t)device; - struct netif *psNetif = (net_dev->parent.netif); - - LWIP_ASSERT("psNetif != NULL", (psNetif != NULL)); - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - psNetif->hostname = "t4mc"; -#endif /* LWIP_NETIF_HOSTNAME */ - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000); - - net_dev->dma_if = &g_StellarisIFData; - - /* Remember our MAC address. */ - g_StellarisIFData.ethaddr = (struct eth_addr *)&(psNetif->hwaddr[0]); - - /* Initialize the hardware */ - tivaif_hwinit(psNetif); - return RT_EOK; -} - -/* control the interface */ -static rt_err_t eth_dev_control(rt_device_t dev, int cmd, void *args) -{ - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) - MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args); - else - return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -/* Open the interface */ -static rt_err_t eth_dev_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -/* Close the interface */ -static rt_err_t eth_dev_close(rt_device_t dev) -{ - return RT_EOK; -} - -/* Read */ -static rt_size_t eth_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -/* Write */ -static rt_size_t eth_dev_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_err_t eth_dev_tx(rt_device_t dev, struct pbuf *p) -{ - return tivaif_transmit((net_device_t)dev, p); -} - -static struct pbuf* eth_dev_rx(rt_device_t dev) -{ - rt_err_t result; - rt_uint32_t temp =0; - net_device_t net_dev = (net_device_t)dev; - result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO); - - return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL; -} - -int rt_hw_tiva_eth_init(void) -{ - rt_err_t result; - - /* Clock GPIO and etc */ - tiva_eth_lowlevel_init(); - tiva_eth_mac_addr_init(); - - /* init rt-thread device interface */ - eth_dev->parent.parent.init = eth_dev_init; - eth_dev->parent.parent.open = eth_dev_open; - eth_dev->parent.parent.close = eth_dev_close; - eth_dev->parent.parent.read = eth_dev_read; - eth_dev->parent.parent.write = eth_dev_write; - eth_dev->parent.parent.control = eth_dev_control; - eth_dev->parent.eth_rx = eth_dev_rx; - eth_dev->parent.eth_tx = eth_dev_tx; - - result = rt_mb_init(ð_rx_pbuf_mb, "epbuf", - &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4, - RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - eth_dev->rx_pbuf_mb = ð_rx_pbuf_mb; - - - result = eth_device_init(&(eth_dev->parent), "e0"); - return result; -} -// eth_device_init using malloc -// We use INIT_COMPONENT_EXPORT insted of INIT_BOARD_EXPORT -INIT_COMPONENT_EXPORT(rt_hw_tiva_eth_init); - - -#if 0 -#ifdef RT_USING_FINSH -#include "finsh.h" -void PHY_Read(uint8_t addr) -{ - uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr); - rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data); -} -FINSH_FUNCTION_EXPORT(PHY_Read, (add)); - -void PHY_Write(uint8_t addr , uint16_t data) -{ - EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, addr, data); - rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data); -} -FINSH_FUNCTION_EXPORT(PHY_Write, (add, data)); - -void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, - uint8_t addr3, uint8_t addr4, uint8_t addr5) -{ - uint32_t ulUser[2]; - ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0; - ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3; - - MAP_FlashUserSet(ulUser[0], ulUser[1]); - MAP_FlashUserSave(); - rt_kprintf("Save to EEPROM. please reboot."); -} -FINSH_FUNCTION_EXPORT(PHY_SetAdd, (add0-add5)); -#endif //RT_USING_FINSH -#endif diff --git a/bsp/tm4c129x-dk/drivers/drv_eth.h b/bsp/tm4c129x-dk/drivers/drv_eth.h deleted file mode 100644 index 54431405fe..0000000000 --- a/bsp/tm4c129x-dk/drivers/drv_eth.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * File : drv_eth.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-25 ArdaFu Port to TM4C129X - */ - -#ifndef __TIVA_ETH_H__ -#define __TIVA_ETH_H__ - -int rt_hw_tiva_eth_init(void); - -#endif diff --git a/bsp/tm4c129x-dk/drivers/drv_uart.c b/bsp/tm4c129x-dk/drivers/drv_uart.c deleted file mode 100644 index ef95144af1..0000000000 --- a/bsp/tm4c129x-dk/drivers/drv_uart.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2013-05-18 Bernard The first version for LPC40xx - * 2014-07-18 ArdaFu Port to TM4C129X - */ - -#include -#include -#include - -#include "board.h" - -#include "inc/hw_memmap.h" -#include "driverlib/sysctl.h" -#include "driverlib/gpio.h" -#include "driverlib/uart.h" -#include "driverlib/pin_map.h" -#include "driverlib/interrupt.h" -#include "driverlib/rom_map.h" -typedef struct hw_uart_device -{ - uint32_t hw_base; // base address -}hw_uart_t; - -#define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data)) - -static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - uint32_t config = 0; - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - MAP_UARTDisable(uart->hw_base); - // build UART Configuration parameter structure - switch(cfg->data_bits) - { - case DATA_BITS_9: - // enable 9bit address mode and set DATA_BIT_8 - MAP_UART9BitEnable(uart->hw_base); - case DATA_BITS_8: - config |= UART_CONFIG_WLEN_8; - break; - case DATA_BITS_7: - config |= UART_CONFIG_WLEN_7; - break; - case DATA_BITS_6: - config |= UART_CONFIG_WLEN_6; - break; - case DATA_BITS_5: - config |= UART_CONFIG_WLEN_5; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->parity) - { - case PARITY_ODD: - config |= UART_CONFIG_PAR_ODD; - break; - case PARITY_EVEN: - config |= UART_CONFIG_PAR_EVEN; - break; - case PARITY_NONE: - config |= UART_CONFIG_PAR_NONE; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->stop_bits) - { - case STOP_BITS_1: - config |= UART_CONFIG_STOP_ONE; - break; - case STOP_BITS_2: - config |= UART_CONFIG_STOP_TWO; - break; - default: - RT_ASSERT(0); - break; - } - - // Initialize UART0 peripheral with given to corresponding parameter - MAP_UARTConfigSetExpClk(uart->hw_base, SystemCoreClock, cfg->baud_rate, config); - MAP_UARTFIFOEnable(uart->hw_base); - - // Enable the UART. - MAP_UARTEnable(uart->hw_base); - return RT_EOK; -} - -static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - MAP_UARTIntDisable(uart->hw_base, UART_INT_RX | UART_INT_RT); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - MAP_UARTIntEnable(uart->hw_base, UART_INT_RX | UART_INT_RT); - break; - } - - return RT_EOK; -} - -static int hw_putc(struct rt_serial_device *serial, char c) -{ - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c)); - return 1; -} - -static int hw_getc(struct rt_serial_device *serial) -{ - hw_uart_t* uart; - RT_ASSERT(serial != RT_NULL); - uart = mUartGetHwPtr(serial); - - return MAP_UARTCharGetNonBlocking(uart->hw_base); -} - -static const struct rt_uart_ops hw_uart_ops = -{ - hw_configure, - hw_control, - hw_putc, - hw_getc, -}; - -#if defined(RT_USING_UART0) -/* UART0 device driver structure */ -struct rt_serial_device serial0; -hw_uart_t uart0 = -{ - UART0_BASE, -}; - -void UART0_IRQHandler(void) -{ - uint32_t intsrc; - hw_uart_t *uart = &uart0; - - /* enter interrupt */ - rt_interrupt_enter(); - - /* Determine the interrupt source */ - intsrc = MAP_UARTIntStatus(uart->hw_base, true); - - // Receive Data Available or Character time-out - if (intsrc & (UART_INT_RX | UART_INT_RT)) - { - MAP_UARTIntClear(uart->hw_base, intsrc); - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - } - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -int rt_hw_uart_init(void) -{ - hw_uart_t* uart; - struct serial_configure config; - - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - -#ifdef RT_USING_UART0 - uart = &uart0; - serial0.ops = &hw_uart_ops; - serial0.config = config; - - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - MAP_GPIOPinConfigure(GPIO_PA0_U0RX); - MAP_GPIOPinConfigure(GPIO_PA1_U0TX); - - MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* preemption = 1, sub-priority = 1 */ - //IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01)); - - /* Enable Interrupt for UART channel */ - UARTIntRegister(uart->hw_base, UART0_IRQHandler); - MAP_IntEnable(INT_UART0); - MAP_UARTEnable(uart->hw_base); - - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif - return 0; -} -INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/tm4c129x-dk/drivers/drv_uart.h b/bsp/tm4c129x-dk/drivers/drv_uart.h deleted file mode 100644 index 312c6da6b3..0000000000 --- a/bsp/tm4c129x-dk/drivers/drv_uart.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2013-05-18 Bernard The first version for LPC40xx - * 2014-07-18 ArdaFu Port to TM4C129X - */ -#ifndef __UART_H__ -#define __UART_H__ - -void rt_hw_uart_init(void); - -#endif diff --git a/bsp/tm4c129x-dk/libraries/SConscript b/bsp/tm4c129x-dk/libraries/SConscript deleted file mode 100644 index 56c7b84ab3..0000000000 --- a/bsp/tm4c129x-dk/libraries/SConscript +++ /dev/null @@ -1,26 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -# The set of source files associated with this SConscript file. -cwd = GetCurrentDir() -src = Glob('driverlib/*.c') -SrcRemove(src, 'onewire.c') -CCFLAGS = '' - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src += ['startup/startup_gcc.c'] -elif rtconfig.CROSS_TOOL == 'keil': - src += ['startup/startup_rvmdk.S'] -elif rtconfig.CROSS_TOOL == 'iar': - src += ['startup/startup_ewarm.c'] - CCFLAGS += ' --diag_suppress=pe177' - -CPPPATH = [cwd, cwd + '/inc', cwd + '/driverlib'] - - -CPPDEFINES = [rtconfig.PART_TYPE] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, CCFLAGS = CCFLAGS) - -Return('group') diff --git a/bsp/tm4c129x-dk/libraries/driverlib/adc.c b/bsp/tm4c129x-dk/libraries/driverlib/adc.c deleted file mode 100644 index 81e7dc05fc..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/adc.c +++ /dev/null @@ -1,2073 +0,0 @@ -//***************************************************************************** -// -// adc.c - Driver for the ADC. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup adc_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_adc.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "driverlib/adc.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// These defines are used by the ADC driver to simplify access to the ADC -// sequencer's registers. -// -//***************************************************************************** -#define ADC_SEQ (ADC_O_SSMUX0) -#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0) -#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0) -#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0) -#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0) -#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0) -#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0) -#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0) -#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0) -#define ADC_SSTSH (ADC_O_SSTSH0 - ADC_O_SSMUX0) - -//***************************************************************************** -// -// The currently configured software oversampling factor for each of the ADC -// sequencers. -// -//***************************************************************************** -static uint8_t g_pui8OversampleFactor[2][3]; - -//***************************************************************************** -// -//! Returns the interrupt number for a given ADC base address and sequence -//! number. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function returns the interrupt number for the ADC module and sequence -//! number provided in the \e ui32Base and \e ui32SequenceNum parameters. -//! -//! \return Returns the ADC sequence interrupt number or 0 if the interrupt -//! does not exist. -// -//***************************************************************************** -static uint_fast8_t -_ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - uint_fast8_t ui8Int; - - // - // Determine the interrupt to register based on the sequence number. - // - if(CLASS_IS_TM4C123) - { - ui8Int = ((ui32Base == ADC0_BASE) ? - (INT_ADC0SS0_TM4C123 + ui32SequenceNum) : - (INT_ADC1SS0_TM4C123 + ui32SequenceNum)); - } - else if(CLASS_IS_TM4C129) - { - ui8Int = ((ui32Base == ADC0_BASE) ? - (INT_ADC0SS0_TM4C129 + ui32SequenceNum) : - (INT_ADC1SS0_TM4C129 + ui32SequenceNum)); - } - else - { - ui8Int = 0; - } - - return(ui8Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for an ADC interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param pfnHandler is a pointer to the function to be called when the -//! ADC sample sequence interrupt occurs. -//! -//! This function sets the handler to be called when a sample sequence -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; the sequence interrupt must be enabled with -//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the -//! interrupt source via ADCIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, - void (*pfnHandler)(void)) -{ - uint_fast8_t ui8Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine the interrupt to register based on the sequence number. - // - ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum); - ASSERT(ui8Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui8Int, pfnHandler); - - // - // Enable the timer interrupt. - // - IntEnable(ui8Int); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for an ADC interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function unregisters the interrupt handler. This function disables -//! the global interrupt in the interrupt controller; the sequence interrupt -//! must be disabled via ADCIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - uint_fast8_t ui8Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine the interrupt to unregister based on the sequence number. - // - ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum); - ASSERT(ui8Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui8Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui8Int); -} - -//***************************************************************************** -// -//! Disables a sample sequence interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function disables the requested sample sequence interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable this sample sequence interrupt. - // - HWREG(ui32Base + ADC_O_IM) &= ~(1 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Enables a sample sequence interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function enables the requested sample sequence interrupt. Any -//! outstanding interrupts are cleared before enabling the sample sequence -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear any outstanding interrupts on this sample sequence. - // - HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum; - - // - // Enable this sample sequence interrupt. - // - HWREG(ui32Base + ADC_O_IM) |= 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified sample -//! sequence. Either the raw interrupt status or the status of interrupts that -//! are allowed to reflect to the processor can be returned. -//! -//! \return The current raw or masked interrupt status. -// -//***************************************************************************** -uint32_t -ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, bool bMasked) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - ui32Temp = HWREG(ui32Base + ADC_O_ISC) & (0x10001 << ui32SequenceNum); - } - else - { - ui32Temp = (HWREG(ui32Base + ADC_O_RIS) & - (0x10000 | (1 << ui32SequenceNum))); - - // - // If the digital comparator status bit is set, reflect it to the - // appropriate sequence bit. - // - if(ui32Temp & 0x10000) - { - ui32Temp |= 0xF0000; - ui32Temp &= ~(0x10000 << ui32SequenceNum); - } - } - - // - // Return the interrupt status - // - return(ui32Temp); -} - -//***************************************************************************** -// -//! Clears sample sequence interrupt source. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! The specified sample sequence interrupt is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep -//! the interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear the interrupt. - // - HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Enables a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Allows the specified sample sequence to be captured when its trigger is -//! detected. A sample sequence must be configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Enable the specified sequence. - // - HWREG(ui32Base + ADC_O_ACTSS) |= 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Disables a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Prevents the specified sample sequence from being captured when its trigger -//! is detected. A sample sequence must be disabled before it is configured. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable the specified sequences. - // - HWREG(ui32Base + ADC_O_ACTSS) &= ~(1 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Configures the trigger source and priority of a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Trigger is the trigger source that initiates the sample -//! sequence; must be one of the \b ADC_TRIGGER_* values. -//! \param ui32Priority is the relative priority of the sample sequence with -//! respect to the other sample sequences. -//! -//! This function configures the initiation criteria for a sample sequence. -//! Valid sample sequencers range from zero to three; sequencer zero captures -//! up to eight samples, sequencers one and two capture up to four samples, -//! and sequencer three captures a single sample. The trigger condition and -//! priority (with respect to other sample sequencer execution) are set. -//! -//! The \e ui32Trigger parameter can take on the following values: -//! -//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the -//! ADCProcessorTrigger() function. -//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port -//! B4 pin. Note that some microcontrollers can -//! select from any GPIO using the -//! GPIOADCTriggerEnable() function. -//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with -//! TimerControlTrigger(). -//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the -//! sample sequence to capture repeatedly (so long as -//! there is not a higher priority source active). -//! -//! When \b ADC_TRIGGER_PWM0, \b ADC_TRIGGER_PWM1, \b ADC_TRIGGER_PWM2 or -//! \b ADC_TRIGGER_PWM3 is specified, one of the following should be ORed into -//! \e ui32Trigger to select the PWM module from which the triggers will be -//! routed for this sequence: -//! -//! - \b ADC_TRIGGER_PWM_MOD0 - Selects PWM module 0 as the source of the -//! PWM0 to PWM3 triggers for this sequence. -//! - \b ADC_TRIGGER_PWM_MOD1 - Selects PWM module 1 as the source of the -//! PWM0 to PWM3 triggers for this sequence. -//! -//! Note that not all trigger sources are available on all Tiva family -//! members; consult the data sheet for the device in question to determine the -//! availability of triggers. -//! -//! The \e ui32Priority parameter is a value between 0 and 3, where 0 -//! represents the highest priority and 3 the lowest. Note that when -//! programming the priority among a set of sample sequences, each must have -//! unique priority; it is up to the caller to guarantee the uniqueness of the -//! priorities. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Trigger, uint32_t ui32Priority) -{ - uint32_t ui32Gen; - - // - // Check the arugments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - ASSERT(((ui32Trigger & 0xF) == ADC_TRIGGER_PROCESSOR) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP0) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP1) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_COMP2) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_EXTERNAL) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_TIMER) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM0) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM1) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM2) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_PWM3) || - ((ui32Trigger & 0xF) == ADC_TRIGGER_ALWAYS) || - ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD0) || - ((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD1)); - ASSERT(ui32Priority < 4); - - // - // Compute the shift for the bits that control this sample sequence. - // - ui32SequenceNum *= 4; - - // - // Set the trigger event for this sample sequence. - // - HWREG(ui32Base + ADC_O_EMUX) = ((HWREG(ui32Base + ADC_O_EMUX) & - ~(0xf << ui32SequenceNum)) | - ((ui32Trigger & 0xf) << ui32SequenceNum)); - - // - // Set the priority for this sample sequence. - // - HWREG(ui32Base + ADC_O_SSPRI) = ((HWREG(ui32Base + ADC_O_SSPRI) & - ~(0xf << ui32SequenceNum)) | - ((ui32Priority & 0x3) << - ui32SequenceNum)); - - // - // Set the source PWM module for this sequence's PWM triggers. - // - ui32Gen = ui32Trigger & 0x0f; - if(ui32Gen >= ADC_TRIGGER_PWM0 && ui32Gen <= ADC_TRIGGER_PWM3) - { - // - // Set the shift for the module and generator - // - ui32Gen = (ui32Gen - ADC_TRIGGER_PWM0) * 8; - - HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) & - ~(0x30 << ui32Gen)) | - ((ui32Trigger & 0x30) << ui32Gen)); - } -} - -//***************************************************************************** -// -//! Configure a step of the sample sequencer. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Step is the step to be configured. -//! \param ui32Config is the configuration of this step; must be a logical OR -//! of \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the -//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of -//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7). -//! -//! This function configures the ADC for one step of a sample sequence. The -//! ADC can be configured for single-ended or differential operation (the -//! \b ADC_CTL_D bit selects differential operation when set), the channel to -//! be sampled can be chosen (the \b ADC_CTL_CH0 through \b ADC_CTL_CH23 -//! values), and the internal temperature sensor can be selected (the -//! \b ADC_CTL_TS bit). Additionally, this step can be defined as the last in -//! the sequence (the \b ADC_CTL_END bit) and it can be configured to cause an -//! interrupt when the step is complete (the \b ADC_CTL_IE bit). If the -//! digital comparators are present on the device, this step may also be -//! configured to send the ADC sample to the selected comparator using -//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration is used by the -//! ADC at the appropriate time when the trigger for this sequence occurs. -//! -//! \note If the Digital Comparator is present and enabled using the -//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT -//! written into the ADC sequence data FIFO. -//! -//! The \e ui32Step parameter determines the order in which the samples are -//! captured by the ADC when the trigger occurs. It can range from zero to -//! seven for the first sample sequencer, from zero to three for the second and -//! third sample sequencer, and can only be zero for the fourth sample -//! sequencer. -//! -//! Differential mode only works with adjacent channel pairs (for example, 0 -//! and 1). The channel select must be the number of the channel pair to -//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 -//! and 3) or undefined results are returned by the ADC. Additionally, if -//! differential mode is selected when the temperature sensor is being sampled, -//! undefined results are returned by the ADC. -//! -//! It is the responsibility of the caller to ensure that a valid configuration -//! is specified; this function does not check the validity of the specified -//! configuration. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Step, uint32_t ui32Config) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - ASSERT(((ui32SequenceNum == 0) && (ui32Step < 8)) || - ((ui32SequenceNum == 1) && (ui32Step < 4)) || - ((ui32SequenceNum == 2) && (ui32Step < 4)) || - ((ui32SequenceNum == 3) && (ui32Step < 1))); - - // - // Get the offset of the sequence to be configured. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ui32Step *= 4; - - // - // Set the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) & - ~(0x0000000f << ui32Step)) | - ((ui32Config & 0x0f) << ui32Step)); - - // - // Set the upper bits of the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf00) >> 8) << ui32Step)); - - // - // Set the control value for this step. - // - HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf0) >> 4) << ui32Step)); - - // - // Set the sample and hold time for this step. This is not available on - // all devices, however on devices that do not support this feature these - // reserved bits are ignored on write access. - // - HWREG(ui32Base + ADC_SSTSH) = ((HWREG(ui32Base + ADC_SSTSH) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf00000) >> 20) << ui32Step)); - - // - // Enable digital comparator if specified in the ui32Config bit-fields. - // - if(ui32Config & 0x000F0000) - { - // - // Program the comparator for the specified step. - // - ui32Temp = HWREG(ui32Base + ADC_SSDC); - ui32Temp &= ~(0xF << ui32Step); - ui32Temp |= (((ui32Config & 0x00070000) >> 16) << ui32Step); - HWREG(ui32Base + ADC_SSDC) = ui32Temp; - - // - // Enable the comparator. - // - HWREG(ui32Base + ADC_SSOP) |= (1 << ui32Step); - } - - // - // Disable digital comparator if not specified. - // - else - { - HWREG(ui32Base + ADC_SSOP) &= ~(1 << ui32Step); - } -} - -//***************************************************************************** -// -//! Determines if a sample sequence overflow occurred. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function determines if a sample sequence overflow has occurred. -//! Overflow happens if the captured samples are not read from the FIFO before -//! the next trigger occurs. -//! -//! \return Returns zero if there was not an overflow, and non-zero if there -//! was. -// -//***************************************************************************** -int32_t -ADCSequenceOverflow(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine if there was an overflow on this sequence. - // - return(HWREG(ui32Base + ADC_O_OSTAT) & (1 << ui32SequenceNum)); -} - -//***************************************************************************** -// -//! Clears the overflow condition on a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function clears an overflow condition on one of the sample sequences. -//! The overflow condition must be cleared in order to detect a subsequent -//! overflow condition (it otherwise causes no harm). -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceOverflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear the overflow condition for this sequence. - // - HWREG(ui32Base + ADC_O_OSTAT) = 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Determines if a sample sequence underflow occurred. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function determines if a sample sequence underflow has occurred. -//! Underflow happens if too many samples are read from the FIFO. -//! -//! \return Returns zero if there was not an underflow, and non-zero if there -//! was. -// -//***************************************************************************** -int32_t -ADCSequenceUnderflow(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Determine if there was an underflow on this sequence. - // - return(HWREG(ui32Base + ADC_O_USTAT) & (1 << ui32SequenceNum)); -} - -//***************************************************************************** -// -//! Clears the underflow condition on a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function clears an underflow condition on one of the sample -//! sequencers. The underflow condition must be cleared in order to detect a -//! subsequent underflow condition (it otherwise causes no harm). -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceUnderflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Clear the underflow condition for this sequence. - // - HWREG(ui32Base + ADC_O_USTAT) = 1 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param pui32Buffer is the address where the data is stored. -//! -//! This function copies data from the specified sample sequencer output FIFO -//! to a memory resident buffer. The number of samples available in the -//! hardware FIFO are copied into the buffer, which is assumed to be large -//! enough to hold that many samples. This function only returns the samples -//! that are presently available, which may not be the entire sample sequence -//! if it is in the process of being executed. -//! -//! \return Returns the number of samples copied to the buffer. -// -//***************************************************************************** -int32_t -ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t *pui32Buffer) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Get the offset of the sequence to be read. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Read samples from the FIFO until it is empty. - // - ui32Count = 0; - while(!(HWREG(ui32Base + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && - (ui32Count < 8)) - { - // - // Read the FIFO and copy it to the destination. - // - *pui32Buffer++ = HWREG(ui32Base + ADC_SSFIFO); - - // - // Increment the count of samples read. - // - ui32Count++; - } - - // - // Return the number of samples read. - // - return(ui32Count); -} - -//***************************************************************************** -// -//! Causes a processor trigger for a sample sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number, with -//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it. -//! -//! This function triggers a processor-initiated sample sequence if the sample -//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If -//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the -//! processor-initiated trigger is delayed until a later processor-initiated -//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL, -//! allowing multiple ADCs to start from a processor-initiated trigger in a -//! synchronous manner. -//! -//! \return None. -// -//***************************************************************************** -void -ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Generate a processor trigger for this sample sequence. - // - HWREG(ui32Base + ADC_O_PSSI) |= ((ui32SequenceNum & 0xffff0000) | - (1 << (ui32SequenceNum & 0xf))); -} - -//***************************************************************************** -// -//! Configures the software oversampling factor of the ADC. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Factor is the number of samples to be averaged. -//! -//! This function configures the software oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. -//! Three different oversampling rates are supported; 2x, 4x, and 8x. -//! -//! Oversampling is only supported on the sample sequencers that are more than -//! one sample in depth (that is, the fourth sample sequencer is not -//! supported). Oversampling by 2x (for example) divides the depth of the -//! sample sequencer by two; so 2x oversampling on the first sample sequencer -//! can only provide four samples per trigger. This also means that 8x -//! oversampling is only available on the first sample sequencer. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Factor) -{ - uint32_t ui32Value; - uint32_t ui32ADCInst; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 3); - ASSERT(((ui32Factor == 2) || (ui32Factor == 4) || (ui32Factor == 8)) && - ((ui32SequenceNum == 0) || (ui32Factor != 8))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ui32Value = 0, ui32Factor >>= 1; ui32Factor; - ui32Value++, ui32Factor >>= 1) - { - } - - // - // Evaluate the ADC Instance. - // - if(ui32Base == ADC0_BASE) - { - ui32ADCInst = 0; - } - else - { - ui32ADCInst = 1; - } - - // - // Save the shift factor. - // - g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum] = ui32Value; -} - -//***************************************************************************** -// -//! Configures a step of the software oversampled sequencer. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param ui32Step is the step to be configured. -//! \param ui32Config is the configuration of this step. -//! -//! This function configures a step of the sample sequencer when using the -//! software oversampling feature. The number of steps available depends on -//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value -//! of \e ui32Config is the same as defined for ADCSequenceStepConfigure(). -//! -//! \return None. -// -//***************************************************************************** -void -ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Step, uint32_t ui32Config) -{ - uint32_t ui32ADCInst; - - // - // Evaluate the ADC Instance. - // - if(ui32Base == ADC0_BASE) - { - ui32ADCInst = 0; - } - else - { - ui32ADCInst = 1; - } - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 3); - ASSERT(((ui32SequenceNum == 0) && - (ui32Step < - (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || - (ui32Step < - (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); - - // - // Get the offset of the sequence to be configured. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ui32Step *= 4 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; - - // - // Loop through the hardware steps that make up this step of the software - // oversampled sequence. - // - for(ui32SequenceNum = - (1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]); - ui32SequenceNum; ui32SequenceNum--) - { - // - // Set the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) & - ~(0x0000000f << ui32Step)) | - ((ui32Config & 0x0f) << ui32Step)); - - // - // Set the upper bits of the analog mux value for this step. - // - HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf00) >> 8) << - ui32Step)); - - // - // Set the control value for this step. - // - HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) & - ~(0x0000000f << ui32Step)) | - (((ui32Config & 0xf0) >> 4) << - ui32Step)); - if(ui32SequenceNum != 1) - { - HWREG(ui32Base + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 | - ADC_SSCTL0_END0) << ui32Step); - } - - // - // Go to the next hardware step. - // - ui32Step += 4; - } -} - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence using software oversampling. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! \param pui32Buffer is the address where the data is stored. -//! \param ui32Count is the number of samples to be read. -//! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer with software oversampling applied. The requested -//! number of samples are copied into the data buffer; if there are not enough -//! samples in the hardware FIFO to satisfy this many oversampled data items, -//! then incorrect results are returned. It is the caller's responsibility to -//! read only the samples that are available and wait until enough data is -//! available, for example as a result of receiving an interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t *pui32Buffer, uint32_t ui32Count) -{ - uint32_t ui32Idx, ui32Accum; - uint32_t ui32ADCInst; - - // - // Evaluate the ADC Instance. - // - if(ui32Base == ADC0_BASE) - { - ui32ADCInst = 0; - } - else - { - ui32ADCInst = 1; - } - - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 3); - ASSERT(((ui32SequenceNum == 0) && - (ui32Count < - (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || - (ui32Count < - (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); - - // - // Get the offset of the sequence to be read. - // - ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum); - - // - // Read the samples from the FIFO until it is empty. - // - while(ui32Count--) - { - // - // Compute the sum of the samples. - // - ui32Accum = 0; - for(ui32Idx = 1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; - ui32Idx; ui32Idx--) - { - // - // Read the FIFO and add it to the accumulator. - // - ui32Accum += HWREG(ui32Base + ADC_SSFIFO); - } - - // - // Write the averaged sample to the output buffer. - // - *pui32Buffer++ = - ui32Accum >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; - } -} - -//***************************************************************************** -// -//! Configures the hardware oversampling factor of the ADC. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Factor is the number of samples to be averaged. -//! -//! This function configures the hardware oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. Six -//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. -//! Specifying an oversampling factor of zero disables hardware -//! oversampling. -//! -//! Hardware oversampling applies uniformly to all sample sequencers. It does -//! not reduce the depth of the sample sequencers like the software -//! oversampling APIs; each sample written into the sample sequencer FIFO is a -//! fully oversampled analog input reading. -//! -//! Enabling hardware averaging increases the precision of the ADC at the cost -//! of throughput. For example, enabling 4x oversampling reduces the -//! throughput of a 250 k samples/second ADC to 62.5 k samples/second. -//! -//! \return None. -// -//***************************************************************************** -void -ADCHardwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32Factor) -{ - uint32_t ui32Value; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(((ui32Factor == 0) || (ui32Factor == 2) || (ui32Factor == 4) || - (ui32Factor == 8) || (ui32Factor == 16) || (ui32Factor == 32) || - (ui32Factor == 64))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ui32Value = 0, ui32Factor >>= 1; ui32Factor; - ui32Value++, ui32Factor >>= 1) - { - } - - // - // Write the shift factor to the ADC to configure the hardware oversampler. - // - HWREG(ui32Base + ADC_O_SAC) = ui32Value; -} - -//***************************************************************************** -// -//! Configures an ADC digital comparator. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Comp is the index of the comparator to configure. -//! \param ui32Config is the configuration of the comparator. -//! -//! This function configures a comparator. The \e ui32Config parameter is -//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and -//! \b ADC_COMP_INT_xxx values. -//! -//! The \b ADC_COMP_TRIG_xxx term can take on the following values: -//! -//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition. -//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when -//! ADC output is in the low-band. -//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC -//! output transitions into the low-band. -//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when -//! ADC output is in the low-band only if ADC output has been in the high-band -//! since the last trigger output. -//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC -//! output transitions into low-band only if ADC output has been in the -//! high-band since the last trigger output. -//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when -//! ADC output is in the mid-band. -//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC -//! output transitions into the mid-band. -//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when -//! ADC output is in the high-band. -//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC -//! output transitions into the high-band. -//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when -//! ADC output is in the high-band only if ADC output has been in the low-band -//! since the last trigger output. -//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC -//! output transitions into high-band only if ADC output has been in the -//! low-band since the last trigger output. -//! -//! The \b ADC_COMP_INT_xxx term can take on the following values: -//! -//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt. -//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC -//! output is in the low-band. -//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output -//! transitions into the low-band. -//! - \b ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC -//! output is in the low-band only if ADC output has been in the high-band -//! since the last trigger output. -//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output -//! transitions into low-band only if ADC output has been in the high-band -//! since the last trigger output. -//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC -//! output is in the mid-band. -//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output -//! transitions into the mid-band. -//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC -//! output is in the high-band. -//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output -//! transitions into the high-band. -//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC -//! output is in the high-band only if ADC output has been in the low-band -//! since the last trigger output. -//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output -//! transitions into high-band only if ADC output has been in the low-band -//! since the last trigger output. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32Comp < 8); - - // - // Save the new setting. - // - HWREG(ui32Base + ADC_O_DCCTL0 + (ui32Comp * 4)) = ui32Config; -} - -//***************************************************************************** -// -//! Defines the ADC digital comparator regions. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Comp is the index of the comparator to configure. -//! \param ui32LowRef is the reference point for the low/mid band threshold. -//! \param ui32HighRef is the reference point for the mid/high band threshold. -//! -//! The ADC digital comparator operation is based on three ADC value regions: -//! - \b low-band is defined as any ADC value less than or equal to the -//! \e ui32LowRef value. -//! - \b mid-band is defined as any ADC value greater than the \e ui32LowRef -//! value but less than or equal to the \e ui32HighRef value. -//! - \b high-band is defined as any ADC value greater than the \e ui32HighRef -//! value. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32LowRef, uint32_t ui32HighRef) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32Comp < 8); - ASSERT((ui32LowRef < 4096) && (ui32LowRef <= ui32HighRef)); - ASSERT(ui32HighRef < 4096); - - // - // Save the new region settings. - // - HWREG(ui32Base + ADC_O_DCCMP0 + (ui32Comp * 4)) = ((ui32HighRef << 16) | - ui32LowRef); -} - -//***************************************************************************** -// -//! Resets the current ADC digital comparator conditions. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Comp is the index of the comparator. -//! \param bTrigger is the flag to indicate reset of Trigger conditions. -//! \param bInterrupt is the flag to indicate reset of Interrupt conditions. -//! -//! Because the digital comparator uses current and previous ADC values, this -//! function allows the comparator to be reset to its initial -//! value to prevent stale data from being used when a sequence is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, bool bTrigger, - bool bInterrupt) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32Comp < 8); - - // - // Set the appropriate bits to reset the trigger and/or interrupt - // comparator conditions. - // - ui32Temp = 0; - if(bTrigger) - { - ui32Temp |= (1 << (16 + ui32Comp)); - } - if(bInterrupt) - { - ui32Temp |= (1 << ui32Comp); - } - - HWREG(ui32Base + ADC_O_DCRIC) = ui32Temp; -} - -//***************************************************************************** -// -//! Disables a sample sequence comparator interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function disables the requested sample sequence comparator interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable this sample sequence comparator interrupt. - // - HWREG(ui32Base + ADC_O_IM) &= ~(0x10000 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Enables a sample sequence comparator interrupt. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! This function enables the requested sample sequence comparator interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Enable this sample sequence interrupt. - // - HWREG(ui32Base + ADC_O_IM) |= 0x10000 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Gets the current comparator interrupt status. -//! -//! \param ui32Base is the base address of the ADC module. -//! -//! This function returns the digital comparator interrupt status bits. This -//! status is sequence agnostic. -//! -//! \return The current comparator interrupt status. -// -//***************************************************************************** -uint32_t -ADCComparatorIntStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return the digital comparator interrupt status. - // - return(HWREG(ui32Base + ADC_O_DCISC)); -} - -//***************************************************************************** -// -//! Clears sample sequence comparator interrupt source. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Status is the bit-mapped interrupts status to clear. -//! -//! The specified interrupt status is cleared. -//! -//! \return None. -// -//***************************************************************************** -void -ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Clear the interrupt. - // - HWREG(ui32Base + ADC_O_DCISC) = ui32Status; -} - -//***************************************************************************** -// -//! Disables ADC interrupt sources. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function disables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0. -//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1. -//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2. -//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3. -//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0. -//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1. -//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2. -//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3. -//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample -//! sequence 0. -//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample -//! sequence 1. -//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample -//! sequence 2. -//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample -//! sequence 3. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Disable the requested interrupts. - // - HWREG(ui32Base + ADC_O_IM) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables ADC interrupt sources. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function enables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0. -//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1. -//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2. -//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3. -//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0. -//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1. -//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2. -//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3. -//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample -//! sequence 0. -//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample -//! sequence 1. -//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample -//! sequence 2. -//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample -//! sequence 3. -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Enable the requested interrupts. - // - HWREG(ui32Base + ADC_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified ADC module. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return Returns the current interrupt status for the specified ADC module. -//! The value returned is the logical OR of the \b ADC_INT_* values that are -//! currently active. -// -//***************************************************************************** -uint32_t -ADCIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return either the masked interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - ui32Temp = HWREG(ui32Base + ADC_O_ISC); - } - else - { - // - // Read the Raw interrupt status to see if a digital comparator - // interrupt is active. - // - ui32Temp = HWREG(ui32Base + ADC_O_RIS); - - // - // Since, the raw interrupt status only indicates that any one of the - // digital comparators caused an interrupt, if the raw interrupt status - // is set then the return value is modified to indicate that all sample - // sequences have a pending digital comparator interrupt. - // This is exactly how the hardware works so the return code is - // modified to match this behavior. - // - if(ui32Temp & ADC_RIS_INRDC) - { - ui32Temp |= (ADC_INT_DCON_SS3 | ADC_INT_DCON_SS2 | - ADC_INT_DCON_SS1 | ADC_INT_DCON_SS0); - } - } - return(ui32Temp); -} - -//***************************************************************************** -// -//! Clears the specified ADC interrupt sources. -//! -//! \param ui32Base is the base address of the ADC port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! Clears the interrupt for the specified interrupt source(s). -//! -//! The \e ui32IntFlags parameter is the logical OR of the \b ADC_INT_* values. -//! See the ADCIntEnableEx() function for the list of possible \b ADC_INT* -//! values. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Note: The interrupt bits are "W1C" so we DO NOT use a logical OR - // here to clear the requested bits. Doing so would clear all outstanding - // interrupts rather than just those which the caller has specified. - // - HWREG(ui32Base + ADC_O_ISC) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Selects the ADC reference. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Ref is the reference to use. -//! -//! The ADC reference is set as specified by \e ui32Ref. It must be one of -//! \b ADC_REF_INT, or \b ADC_REF_EXT_3V for internal or external reference -//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and -//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then -//! a 3V reference must be supplied to the AVREF pin. -//! -//! \note The ADC reference can only be selected on parts that have an external -//! reference. Consult the data sheet for your part to determine if there is -//! an external reference. -//! -//! \return None. -// -//***************************************************************************** -void -ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V)); - - // - // Set the reference. - // - HWREG(ui32Base + ADC_O_CTL) = - (HWREG(ui32Base + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ui32Ref; -} - -//***************************************************************************** -// -//! Returns the current setting of the ADC reference. -//! -//! \param ui32Base is the base address of the ADC module. -//! -//! Returns the value of the ADC reference setting. The returned value is one -//! of \b ADC_REF_INT, or \b ADC_REF_EXT_3V. -//! -//! \note The value returned by this function is only meaningful if used on a -//! part that is capable of using an external reference. Consult the data -//! sheet for your part to determine if it has an external reference input. -//! -//! \return The current setting of the ADC reference. -// -//***************************************************************************** -uint32_t -ADCReferenceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return the value of the reference. - // - return(HWREG(ui32Base + ADC_O_CTL) & ADC_CTL_VREF_M); -} - -//***************************************************************************** -// -//! Sets the phase delay between a trigger and the start of a sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32Phase is the phase delay, specified as one of \b ADC_PHASE_0, -//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, -//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, -//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, -//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. -//! -//! This function sets the phase delay between the detection of an ADC trigger -//! event and the start of the sample sequence. By selecting a different phase -//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and -//! \b ADC_PHASE_180) and having each ADC module sample the same analog input, -//! it is possible to increase the sampling rate of the analog input (with -//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1, -//! N+3, N+5, and so on, coming from the second ADC). The ADC module has a -//! single phase delay that is applied to all sample sequences within that -//! module. -//! -//! \note This capability is not available on all parts. -//! -//! \return None. -// -//***************************************************************************** -void -ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32Phase == ADC_PHASE_0) || (ui32Phase == ADC_PHASE_22_5) || - (ui32Phase == ADC_PHASE_45) || (ui32Phase == ADC_PHASE_67_5) || - (ui32Phase == ADC_PHASE_90) || (ui32Phase == ADC_PHASE_112_5) || - (ui32Phase == ADC_PHASE_135) || (ui32Phase == ADC_PHASE_157_5) || - (ui32Phase == ADC_PHASE_180) || (ui32Phase == ADC_PHASE_202_5) || - (ui32Phase == ADC_PHASE_225) || (ui32Phase == ADC_PHASE_247_5) || - (ui32Phase == ADC_PHASE_270) || (ui32Phase == ADC_PHASE_292_5) || - (ui32Phase == ADC_PHASE_315) || (ui32Phase == ADC_PHASE_337_5)); - - // - // Set the phase delay. - // - HWREG(ui32Base + ADC_O_SPC) = ui32Phase; -} - -//***************************************************************************** -// -//! Gets the phase delay between a trigger and the start of a sequence. -//! -//! \param ui32Base is the base address of the ADC module. -//! -//! This function gets the current phase delay between the detection of an ADC -//! trigger event and the start of the sample sequence. -//! -//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0, -//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90, -//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180, -//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270, -//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5. -// -//***************************************************************************** -uint32_t -ADCPhaseDelayGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Return the phase delay. - // - return(HWREG(ui32Base + ADC_O_SPC)); -} - -//***************************************************************************** -// -//! Enables DMA for sample sequencers. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Allows DMA requests to be generated based on the FIFO level of the sample -//! sequencer. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Enable the DMA on the specified sequencer. - // - HWREG(ui32Base + ADC_O_ACTSS) |= 0x100 << ui32SequenceNum; -} - -//***************************************************************************** -// -//! Disables DMA for sample sequencers. -//! -//! \param ui32Base is the base address of the ADC module. -//! \param ui32SequenceNum is the sample sequence number. -//! -//! Prevents the specified sample sequencer from generating DMA requests. -//! -//! \return None. -// -//***************************************************************************** -void -ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT(ui32SequenceNum < 4); - - // - // Disable the DMA on the specified sequencer. - // - HWREG(ui32Base + ADC_O_ACTSS) &= ~(0x100 << ui32SequenceNum); -} - -//***************************************************************************** -// -//! Determines whether the ADC is busy or not. -//! -//! \param ui32Base is the base address of the ADC. -//! -//! This function allows the caller to determine whether or not the ADC is -//! currently sampling . If \b false is returned, then the ADC is not -//! sampling data. -//! -//! Use this function to detect that the ADC is finished sampling data before -//! putting the device into deep sleep. Before using this function, it is -//! highly recommended that the event trigger is changed to -//! \b ADC_TRIGGER_NEVER on all enabled sequencers to prevent the ADC from -//! starting after checking the busy status. -//! -//! \return Returns \b true if the ADC is sampling or \b false if all -//! samples are complete. -// -//***************************************************************************** -bool -ADCBusy(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Determine if the ADC is busy. - // - return((HWREG(ui32Base + ADC_O_ACTSS) & ADC_ACTSS_BUSY) ? true : false); -} - -//***************************************************************************** -// -//! Sets the clock configuration for the ADC. -//! -//! \param ui32Base is the base address of the ADC to configure, which must -//! always be \b ADC0_BASE. -//! \param ui32Config is a combination of the \b ADC_CLOCK_SRC_ and -//! \b ADC_CLOCK_RATE_* values used to configure the ADC clock input. -//! \param ui32ClockDiv is the input clock divider for the clock selected by -//! the \b ADC_CLOCK_SRC value. -//! -//! This function is used to configure the input clock to the ADC modules. The -//! clock configuration is shared across ADC units so \e ui32Base must -//! always be \b ADC0_BASE. The \e ui32Config value is logical OR of one -//! of the \b ADC_CLOCK_RATE_ and one of the \b ADC_CLOCK_SRC_ values defined -//! below. The \b ADC_CLOCK_SRC_* values determine the input clock for the ADC. -//! Not all values are available on all devices so check the device data sheet -//! to determine value configuration options. Regardless of the source, the -//! final frequency for TM4C123x devices must be 16 MHz and for TM4C129x parts -//! after dividing must be between 16 and 32 MHz. -//! -//! \note For TM4C123x devices, if the PLL is enabled, the PLL/25 is used as -//! the ADC clock unless ADC_CLOCK_SRC_PIOSC is specified. If the PLL is -//! disabled, the MOSC is used as the clock source unless ADC_CLOCK_SRC_PIOSC -//! is specified. -//! -//! - \b ADC_CLOCK_SRC_PLL - The main PLL output (TM4x129 class only). -//! - \b ADC_CLOCK_SRC_PIOSC - The internal PIOSC at 16 MHz. -//! - \b ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control -//! module (TM4x129 class only). -//! - \b ADC_CLOCK_SRC_MOSC - The external MOSC (TM4x129 class only). -//! -//! \b ADC_CLOCK_RATE values control how often samples are provided back to the -//! application. The values are the following: -//! -//! - \b ADC_CLOCK_RATE_FULL - All samples. -//! - \b ADC_CLOCK_RATE_HALF - Every other sample. -//! - \b ADC_CLOCK_RATE_QUARTER - Every fourth sample. -//! - \b ADC_CLOCK_RATE_EIGHTH - Every either sample. -//! -//! The \e ui32ClockDiv parameter allows for dividing a higher frequency down -//! into the valid range for the ADCs. This parameter is typically only used -//! \b ADC_CLOCK_SRC_PLL option because it is the only clock value that can be -//! with the in the correct range to use the divider. The actual value ranges -//! from 1 to 64. -//! -//! \b Example: ADC Clock Configurations -//! -//! \verbatim -//! -//! // -//! // Configure the ADC to use PIOSC divided by one (16 MHz) and sample at -//! // half the rate. -//! // -//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_HALF, 1); -//! -//! ... -//! -//! // -//! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC -//! // clock of 20 MHz. -//! // -//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32ClockDiv) -{ - // - // Check the argument. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S)); - - // - // A rate must be supplied. - // - ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0); - - // - // Write the sample conversion rate. - // - HWREG(ui32Base + ADC_O_PC) = (ui32Config >> 4) & ADC_PC_SR_M; - - // - // Write the clock select and divider. - // - HWREG(ui32Base + ADC_O_CC) = (ui32Config & ADC_CC_CS_M) | - (((ui32ClockDiv - 1) << ADC_CC_CLKDIV_S)) ; -} - -//***************************************************************************** -// -//! Returns the clock configuration for the ADC. -//! -//! \param ui32Base is the base address of the ADC to configure, which must -//! always be \b ADC0_BASE. -//! \param pui32ClockDiv is a pointer to the input clock divider for the clock -//! selected by the \b ADC_CLOCK_SRC in use by the ADCs. -//! -//! This function returns the ADC clock configuration and the clock divider for -//! the ADCs. -//! -//! \b Example: Read the current ADC clock configuration. -//! -//! \verbatim -//! uint32_t ui32Config, ui32ClockDiv; -//! -//! // -//! // Read the current ADC clock configuration. -//! // -//! ui32Config = ADCClockConfigGet(ADC0_BASE, &ui32ClockDiv); -//! \endverbatim -//! -//! \return The current clock configuration of the ADC defined as a combination -//! of one of \b ADC_CLOCK_SRC_PLL, \b ADC_CLOCK_SRC_PIOSC, -//! \b ADC_CLOCK_SRC_MOSC, or \b ADC_CLOCK_SRC_ALTCLK logical ORed with one of -//! \b ADC_CLOCK_RATE_FULL, \b ADC_CLOCK_RATE_HALF, \b ADC_CLOCK_RATE_QUARTER, -//! or \b ADC_CLOCK_RATE_EIGHTH. See ADCClockConfigSet() for more information -//! on these values. -// -//***************************************************************************** -uint32_t -ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) -{ - uint32_t ui32Config; - - // - // Check the argument. - // - ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - - // - // Read the current configuration. - // - ui32Config = HWREG(ui32Base + ADC_O_CC); - - // - // If the clock divider was requested provide the current value. - // - if(pui32ClockDiv) - { - *pui32ClockDiv = - ((ui32Config & ADC_CC_CLKDIV_M) >> ADC_CC_CLKDIV_S) + 1; - } - - // - // Clear out the divider bits. - // - ui32Config &= ~ADC_CC_CLKDIV_M; - - // - // Add in the sample interval to the configuration. - // - ui32Config |= (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4; - - return(ui32Config); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/adc.h b/bsp/tm4c129x-dk/libraries/driverlib/adc.h deleted file mode 100644 index 993b6a3fb5..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/adc.h +++ /dev/null @@ -1,327 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ADC_H__ -#define __DRIVERLIB_ADC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ui32Trigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event -#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event -#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0 -#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1 - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ui32Config -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 -#define ADC_CTL_CH8 0x00000008 // Input channel 8 -#define ADC_CTL_CH9 0x00000009 // Input channel 9 -#define ADC_CTL_CH10 0x0000000A // Input channel 10 -#define ADC_CTL_CH11 0x0000000B // Input channel 11 -#define ADC_CTL_CH12 0x0000000C // Input channel 12 -#define ADC_CTL_CH13 0x0000000D // Input channel 13 -#define ADC_CTL_CH14 0x0000000E // Input channel 14 -#define ADC_CTL_CH15 0x0000000F // Input channel 15 -#define ADC_CTL_CH16 0x00000100 // Input channel 16 -#define ADC_CTL_CH17 0x00000101 // Input channel 17 -#define ADC_CTL_CH18 0x00000102 // Input channel 18 -#define ADC_CTL_CH19 0x00000103 // Input channel 19 -#define ADC_CTL_CH20 0x00000104 // Input channel 20 -#define ADC_CTL_CH21 0x00000105 // Input channel 21 -#define ADC_CTL_CH22 0x00000106 // Input channel 22 -#define ADC_CTL_CH23 0x00000107 // Input channel 23 -#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 -#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 -#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 -#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 -#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 -#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 -#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 -#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 -#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks -#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks -#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks -#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks -#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks -#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks -#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks - -//***************************************************************************** -// -// Values that can be passed to ADCComparatorConfigure as part of the -// ui32Config parameter. -// -//***************************************************************************** -#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled -#define ADC_COMP_TRIG_LOW_ALWAYS \ - 0x00001000 // Trigger Low Always -#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once -#define ADC_COMP_TRIG_LOW_HALWAYS \ - 0x00001200 // Trigger Low Always (Hysteresis) -#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) -#define ADC_COMP_TRIG_MID_ALWAYS \ - 0x00001400 // Trigger Mid Always -#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once -#define ADC_COMP_TRIG_HIGH_ALWAYS \ - 0x00001C00 // Trigger High Always -#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once -#define ADC_COMP_TRIG_HIGH_HALWAYS \ - 0x00001E00 // Trigger High Always (Hysteresis) -#define ADC_COMP_TRIG_HIGH_HONCE \ - 0x00001F00 // Trigger High Once (Hysteresis) - -#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled -#define ADC_COMP_INT_LOW_ALWAYS \ - 0x00000010 // Interrupt Low Always -#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once -#define ADC_COMP_INT_LOW_HALWAYS \ - 0x00000012 // Interrupt Low Always - // (Hysteresis) -#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) -#define ADC_COMP_INT_MID_ALWAYS \ - 0x00000014 // Interrupt Mid Always -#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once -#define ADC_COMP_INT_HIGH_ALWAYS \ - 0x0000001C // Interrupt High Always -#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once -#define ADC_COMP_INT_HIGH_HALWAYS \ - 0x0000001E // Interrupt High Always - // (Hysteresis) -#define ADC_COMP_INT_HIGH_HONCE \ - 0x0000001F // Interrupt High Once (Hysteresis) - -//***************************************************************************** -// -// Values that can be used to modify the sequence number passed to -// ADCProcessorTrigger in order to get cross-module synchronous processor -// triggers. -// -//***************************************************************************** -#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger -#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger - -//***************************************************************************** -// -// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and -// returned from ADCPhaseDelayGet. -// -//***************************************************************************** -#define ADC_PHASE_0 0x00000000 // 0 degrees -#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees -#define ADC_PHASE_45 0x00000002 // 45 degrees -#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees -#define ADC_PHASE_90 0x00000004 // 90 degrees -#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees -#define ADC_PHASE_135 0x00000006 // 135 degrees -#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees -#define ADC_PHASE_180 0x00000008 // 180 degrees -#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees -#define ADC_PHASE_225 0x0000000A // 225 degrees -#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees -#define ADC_PHASE_270 0x0000000C // 270 degrees -#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees -#define ADC_PHASE_315 0x0000000E // 315 degrees -#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees - -//***************************************************************************** -// -// Values that can be passed to ADCReferenceSet as the ui32Ref parameter. -// -//***************************************************************************** -#define ADC_REF_INT 0x00000000 // Internal reference -#define ADC_REF_EXT_3V 0x00000001 // External 3V reference - -//***************************************************************************** -// -// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), -// ADCIntClearEx() and ADCIntStatusEx(). -// -//***************************************************************************** -#define ADC_INT_SS0 0x00000001 -#define ADC_INT_SS1 0x00000002 -#define ADC_INT_SS2 0x00000004 -#define ADC_INT_SS3 0x00000008 -#define ADC_INT_DMA_SS0 0x00000100 -#define ADC_INT_DMA_SS1 0x00000200 -#define ADC_INT_DMA_SS2 0x00000400 -#define ADC_INT_DMA_SS3 0x00000800 -#define ADC_INT_DCON_SS0 0x00010000 -#define ADC_INT_DCON_SS1 0x00020000 -#define ADC_INT_DCON_SS2 0x00040000 -#define ADC_INT_DCON_SS3 0x00080000 - -//***************************************************************************** -// -// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet(). -// -//***************************************************************************** -#define ADC_CLOCK_RATE_FULL 0x00000070 -#define ADC_CLOCK_RATE_HALF 0x00000050 -#define ADC_CLOCK_RATE_FOURTH 0x00000030 -#define ADC_CLOCK_RATE_EIGHTH 0x00000010 -#define ADC_CLOCK_SRC_PLL 0x00000000 -#define ADC_CLOCK_SRC_PIOSC 0x00000001 -#define ADC_CLOCK_SRC_ALTCLK 0x00000001 -#define ADC_CLOCK_SRC_MOSC 0x00000002 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, - bool bMasked); -extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t ui32Trigger, uint32_t ui32Priority); -extern void ADCSequenceStepConfigure(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t ui32Step, uint32_t ui32Config); -extern int32_t ADCSequenceOverflow(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern void ADCSequenceOverflowClear(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern int32_t ADCSequenceUnderflow(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern void ADCSequenceUnderflowClear(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, - uint32_t *pui32Buffer); -extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t ui32Factor); -extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t ui32Step, - uint32_t ui32Config); -extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base, - uint32_t ui32SequenceNum, - uint32_t *pui32Buffer, - uint32_t ui32Count); -extern void ADCHardwareOversampleConfigure(uint32_t ui32Base, - uint32_t ui32Factor); -extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32ClockDiv); -extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv); - -extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32Config); -extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32LowRef, uint32_t ui32HighRef); -extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, - bool bTrigger, bool bInterrupt); -extern void ADCComparatorIntDisable(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern void ADCComparatorIntEnable(uint32_t ui32Base, - uint32_t ui32SequenceNum); -extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base); -extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status); -extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked); -extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum); -extern bool ADCBusy(uint32_t ui32Base); -extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref); -extern uint32_t ADCReferenceGet(uint32_t ui32Base); -extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase); -extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base); -extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock, - uint32_t ui32Rate); -extern uint32_t ADCSampleRateGet(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_ADC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/aes.c b/bsp/tm4c129x-dk/libraries/driverlib/aes.c deleted file mode 100644 index 06cf55bb0b..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/aes.c +++ /dev/null @@ -1,1305 +0,0 @@ -//***************************************************************************** -// -// aes.c - Driver for the AES module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup aes_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_aes.h" -#include "inc/hw_ccm.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/aes.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Resets the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! -//! This function performs a softreset the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESReset(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Trigger the reset. - // - HWREG(ui32Base + AES_O_SYSCONFIG) |= AES_SYSCONFIG_SOFTRESET; - - // - // Wait for the reset to finish. - // - while((HWREG(ui32Base + AES_O_SYSSTATUS) & - AES_SYSSTATUS_RESETDONE) == 0) - { - } -} - -//***************************************************************************** -// -//! Configures the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Config is the configuration of the AES module. -//! -//! This function configures the AES module based on the specified parameters. -//! It does not change any DMA- or interrupt-related parameters. -//! -//! The ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped based on their function. -//! -//! The direction of the operation is specified with only of following flags: -//! -//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode -//! - \b AES_CFG_DIR_DECRYPT - Decryption mode -//! -//! The key size is specified with only one of the following flags: -//! -//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits -//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits -//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits -//! -//! The mode of operation is specified with only one of the following flags. -//! -//! - \b AES_CFG_MODE_ECB - Electronic codebook mode -//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode -//! - \b AES_CFG_MODE_CFB - Cipher feedback mode -//! - \b AES_CFG_MODE_CTR - Counter mode -//! - \b AES_CFG_MODE_ICM - Integer counter mode -//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode -//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with previous/intermediate tweak value and j loaded -//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2, i and j loaded -//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2 and i loaded, j = 0 -//! - \b AES_CFG_MODE_F8 - F8 mode -//! - \b AES_CFG_MODE_F9 - F9 mode -//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication -//! code mode -//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H -//! loaded, Y0-encrypted forced to zero and counter is not enabled. -//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H -//! loaded, Y0-encrypted calculated internally and counter is enabled. -//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH -//! (both H and Y0-encrypted calculated internally) and counter is enabled. -//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode -//! -//! The following defines are used to specify the counter width. It is only -//! required to be defined when using CTR, CCM, or GCM modes, only one of the -//! following defines must be used to specify the counter width length: -//! -//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits -//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits -//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits -//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits -//! -//! Only one of the following defines must be used to specify the length field -//! for CCM operations (L): -//! -//! - \b AES_CFG_CCM_L_1 - 1 byte -//! - \b AES_CFG_CCM_L_2 - 2 bytes -//! - \b AES_CFG_CCM_L_3 - 3 bytes -//! - \b AES_CFG_CCM_L_4 - 4 bytes -//! - \b AES_CFG_CCM_L_5 - 5 bytes -//! - \b AES_CFG_CCM_L_6 - 6 bytes -//! - \b AES_CFG_CCM_L_7 - 7 bytes -//! - \b AES_CFG_CCM_L_8 - 8 bytes -//! -//! Only one of the following defines must be used to specify the length of the -//! authentication field for CCM operations (M) through the \e ui32Config -//! argument in the AESConfigSet() function: -//! -//! - \b AES_CFG_CCM_M_4 - 4 bytes -//! - \b AES_CFG_CCM_M_6 - 6 bytes -//! - \b AES_CFG_CCM_M_8 - 8 bytes -//! - \b AES_CFG_CCM_M_10 - 10 bytes -//! - \b AES_CFG_CCM_M_12 - 12 bytes -//! - \b AES_CFG_CCM_M_14 - 14 bytes -//! - \b AES_CFG_CCM_M_16 - 16 bytes -//! -//! \note When performing a basic GHASH operation for used with GCM mode, use -//! the \b AES_CFG_MODE_GCM_HLY0ZERO and do not specify a direction. -//! -//! \return None. -// -//***************************************************************************** -void -AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) || - (ui32Config & AES_CFG_DIR_DECRYPT)); - ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) || - (ui32Config & AES_CFG_KEY_SIZE_192BIT) || - (ui32Config & AES_CFG_KEY_SIZE_256BIT)); - ASSERT((ui32Config & AES_CFG_MODE_ECB) || - (ui32Config & AES_CFG_MODE_CBC) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_ICM) || - (ui32Config & AES_CFG_MODE_CFB) || - (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) || - (ui32Config & AES_CFG_MODE_XTS_K2IJL) || - (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) || - (ui32Config & AES_CFG_MODE_F8) || - (ui32Config & AES_CFG_MODE_F9) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_CBCMAC) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)); - ASSERT(((ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)) && - ((ui32Config & AES_CFG_CTR_WIDTH_32) || - (ui32Config & AES_CFG_CTR_WIDTH_64) || - (ui32Config & AES_CFG_CTR_WIDTH_96) || - (ui32Config & AES_CFG_CTR_WIDTH_128))); - ASSERT((ui32Config & AES_CFG_MODE_CCM) && - ((ui32Config & AES_CFG_CCM_L_1) || - (ui32Config & AES_CFG_CCM_L_2) || - (ui32Config & AES_CFG_CCM_L_3) || - (ui32Config & AES_CFG_CCM_L_4) || - (ui32Config & AES_CFG_CCM_L_5) || - (ui32Config & AES_CFG_CCM_L_6) || - (ui32Config & AES_CFG_CCM_L_7) || - (ui32Config & AES_CFG_CCM_L_8)) && - ((ui32Config & AES_CFG_CCM_M_4) || - (ui32Config & AES_CFG_CCM_M_6) || - (ui32Config & AES_CFG_CCM_M_8) || - (ui32Config & AES_CFG_CCM_M_10) || - (ui32Config & AES_CFG_CCM_M_12) || - (ui32Config & AES_CFG_CCM_M_14) || - (ui32Config & AES_CFG_CCM_M_16))); - - // - // Backup the save context field before updating the register. - // - if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) - { - ui32Config |= AES_CTRL_SAVE_CONTEXT; - } - - // - // Write the CTRL register with the new value - // - HWREG(ui32Base + AES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Writes the key 1 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui32Key is an array of 32-bit words, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes key 1 configuration registers based on the key -//! size. This function is used in all modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY1_0) = pui32Key[0]; - HWREG(ui32Base + AES_O_KEY1_1) = pui32Key[1]; - HWREG(ui32Base + AES_O_KEY1_2) = pui32Key[2]; - HWREG(ui32Base + AES_O_KEY1_3) = pui32Key[3]; - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY1_4) = pui32Key[4]; - HWREG(ui32Base + AES_O_KEY1_5) = pui32Key[5]; - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY1_6) = pui32Key[6]; - HWREG(ui32Base + AES_O_KEY1_7) = pui32Key[7]; - } -} - -//***************************************************************************** -// -//! Writes the key 2 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui32Key is an array of 32-bit words, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes the key 2 configuration registers based on the key -//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY2_0) = pui32Key[0]; - HWREG(ui32Base + AES_O_KEY2_1) = pui32Key[1]; - HWREG(ui32Base + AES_O_KEY2_2) = pui32Key[2]; - HWREG(ui32Base + AES_O_KEY2_3) = pui32Key[3]; - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[4]; - HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[5]; - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[6]; - HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[7]; - } -} - -//***************************************************************************** -// -//! Writes key 3 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui32Key is a pointer to an array of 4 words (128 bits), containing -//! the key to be configured. The least significant word is in the 0th index. -//! -//! This function writes the key 2 configuration registers with key 3 data -//! used in CBC-MAC and F8 modes. This key is always 128 bits. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the key into the upper 4 key registers - // - HWREG(ui32Base + AES_O_KEY2_4) = pui32Key[0]; - HWREG(ui32Base + AES_O_KEY2_5) = pui32Key[1]; - HWREG(ui32Base + AES_O_KEY2_6) = pui32Key[2]; - HWREG(ui32Base + AES_O_KEY2_7) = pui32Key[3]; -} - -//***************************************************************************** -// -//! Writes the Initial Vector (IV) register, needed in some of the AES Modes. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32IVdata is an array of 4 words (128 bits), containing the IV -//! value to be configured. The least significant word is in the 0th index. -//! -//! This functions writes the initial vector registers in the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the initial vector registers. - // - HWREG(ui32Base + AES_O_IV_IN_0) = pui32IVdata[0]; - HWREG(ui32Base + AES_O_IV_IN_1) = pui32IVdata[1]; - HWREG(ui32Base + AES_O_IV_IN_2) = pui32IVdata[2]; - HWREG(ui32Base + AES_O_IV_IN_3) = pui32IVdata[3]; -} - -//***************************************************************************** -// -//! Saves the Initial Vector (IV) registers to a user-defined location. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32IVData is pointer to the location that stores the IV data. -//! -//! This function stores the IV for use with authenticated encryption and -//! decryption operations. It is assumed that the AES_CTRL_SAVE_CONTEXT -//! bit is set in the AES_CTRL register. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVRead(uint32_t ui32Base, uint32_t *pui32IVData) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for the output context to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read the tag data. - // - pui32IVData[0] = HWREG((ui32Base + AES_O_IV_IN_0)); - pui32IVData[1] = HWREG((ui32Base + AES_O_IV_IN_1)); - pui32IVData[2] = HWREG((ui32Base + AES_O_IV_IN_2)); - pui32IVData[3] = HWREG((ui32Base + AES_O_IV_IN_3)); -} - -//***************************************************************************** -// -//! Saves the tag registers to a user-defined location. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32TagData is pointer to the location that stores the tag data. -//! -//! This function stores the tag data for use authenticated encryption and -//! decryption operations. It is assumed that the AES_CTRL_SAVE_CONTEXT -//! bit is set in the AES_CTRL register. -//! -//! \return None. -// -//***************************************************************************** -void -AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for the output context to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read the tag data. - // - pui32TagData[0] = HWREG((ui32Base + AES_O_TAG_OUT_0)); - pui32TagData[1] = HWREG((ui32Base + AES_O_TAG_OUT_1)); - pui32TagData[2] = HWREG((ui32Base + AES_O_TAG_OUT_2)); - pui32TagData[3] = HWREG((ui32Base + AES_O_TAG_OUT_3)); -} - -//***************************************************************************** -// -//! Used to set the write crypto data length in the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui64Length is the crypto data length in bytes. -//! -//! This function stores the cryptographic data length in blocks for all modes. -//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up -//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. -//! For basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the -//! length field, indicating that the length is infinite. -//! -//! When this function is called, the engine is triggered to start using -//! this context. -//! -//! \note This length does not include the authentication-only data used in -//! some modes. Use the AESAuthLengthSet() function to specify the -//! authentication data length. -//! -//! \return None -// -//***************************************************************************** -void -AESLengthSet(uint32_t ui32Base, uint64_t ui64Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register by shifting the 64-bit ui64Length. - // - HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length); - HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32); -} - -//***************************************************************************** -// -//! Sets the authentication data length in the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Length is the length in bytes. -//! -//! This function is only used to write the authentication data length in the -//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM -//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can -//! be used. For XTS mode, this register is used to load j. Loading of j is -//! only required if j != 0. j represents the sequential number of the 128-bit -//! blocks inside the data unit. Consequently, j must be multiplied by 16 -//! when passed to this function, thereby placing the block number in -//! bits [31:4] of the register. -//! -//! When this function is called, the engine is triggered to start using -//! this context for GCM and CCM. -//! -//! \return None -// -//***************************************************************************** -void -AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length into the register. - // - HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Dest is a pointer to an array of words of data. -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output data is not ready, the function returns -//! false. If the read completed successfully, the function returns true. -//! A block is 16 bytes or 4 words. -//! -//! \return true or false. -// -//***************************************************************************** -bool -AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Check if the output is ready before reading the data. If it not ready, - // return false. - // - if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); - - // - // Read successful, return true. - // - return(true); -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Dest is a pointer to an array of words. -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output is not ready, the function waits until it is -//! ready. A block is 16 bytes or 4 words. -//! -//! \return None. -// -//***************************************************************************** -void -AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for the output to be ready before reading the data. - // - while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to an array of words of data. -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function returns false. If the -//! write completed successfully, the function returns true. A block is 16 -//! bytes or 4 words. -//! -//! \return True or false. -// -//***************************************************************************** -bool -AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Check if the input is ready. If not, then return false. - // - if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL)))) - { - return(false); - } - - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; - - // - // Write successful, return true. - // - return(true); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers with blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to an array of bytes. -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function waits until it is -//! ready before performing the write. A block is 16 bytes or 4 words. -//! -//! \return None. -// -//***************************************************************************** -void -AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Wait for input ready. - // - while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; -} - -//***************************************************************************** -// -//! Used to process(transform) blocks of data, either encrypt or decrypt it. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param pui32Dest is a pointer to the memory location output is written. -//! The space for written data must be rounded up to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! -//! This function iterates the encryption or decryption mechanism number over -//! the data length. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only ECB, -//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data -//! is processed in 4-word (16-byte) blocks. -//! -//! \note This function only supports values of \e ui32Length less than 2^32, -//! because the memory size is restricted to between 0 to 2^32 bytes. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESLengthSet(AES_BASE, (uint64_t)ui32Length); - - // - // Now loop until the blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); - - // - // Read the data registers. - // - AESDataRead(ui32Base, pui32Dest + (ui32Count / 4)); - } - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Used to authenticate blocks of data by generating a hash tag. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui32Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function processes data to produce a hash tag that can be used tor -//! authentication. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only -//! CBC-MAC and F9 modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, uint32_t ui32Length, - uint32_t *pui32Tag) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESLengthSet(ui32Base, (uint64_t)ui32Length); - - // - // Now loop until the blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); - } - - // - // Read the hash tag value. - // - AESTagRead(ui32Base, pui32Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Processes and authenticates blocks of data, either encrypt it or decrypts -//! it. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui32Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param pui32Dest is a pointer to the memory location output is written. -//! The space for written data must be rounded up to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui32AuthSrc is a pointer to the memory location where the -//! additional authentication data is stored. The data must be padded to the -//! 16-byte boundary. -//! \param ui32AuthLength is the length of the additional authentication -//! data in bytes. -//! \param pui32Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function encrypts or decrypts blocks of data in addition to -//! authentication data. A hash tag is also produced. Before calling this -//! function, ensure that the AES module is properly configured the key, -//! data size, mode, etc. Only CCM and GCM modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length, - uint32_t *pui32AuthSrc, uint32_t ui32AuthLength, - uint32_t *pui32Tag) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Set the data length. - // - AESLengthSet(ui32Base, (uint64_t)ui32Length); - - // - // Set the additional authentication data length. - // - AESAuthLengthSet(ui32Base, ui32AuthLength); - - // - // Now loop until the authentication data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32AuthSrc + (ui32Count / 4)); - } - - // - // Now loop until the data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui32Src + (ui32Count / 4)); - - // - // - // Read the data registers. - // - AESDataRead(ui32Base, pui32Dest + (ui32Count / 4)); - } - - // - // Read the hash tag value. - // - AESTagRead(ui32Base, pui32Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Returns the current AES module interrupt status. -//! -//! \param ui32Base is the base address of the AES module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! \return Returns a bit mask of the interrupt sources, which is a logical OR -//! of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt. -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -// -//***************************************************************************** -uint32_t -AESIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Status, ui32Enable, ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Read the IRQ status register and return the value. - // - ui32Status = HWREG(ui32Base + AES_O_IRQSTATUS); - if(bMasked) - { - ui32Enable = HWREG(ui32Base + AES_O_IRQENABLE); - ui32Temp = HWREG(ui32Base + AES_O_DMAMIS); - return((ui32Status & ui32Enable) | - (((ui32Temp & 0x00000001) << 16) | - ((ui32Temp & 0x00000002) << 18) | - ((ui32Temp & 0x0000000c) << 15))); - } - else - { - ui32Temp = HWREG(ui32Base + AES_O_DMARIS); - return(ui32Status | - (((ui32Temp & 0x00000001) << 16) | - ((ui32Temp & 0x00000002) << 18) | - ((ui32Temp & 0x0000000c) << 15))); - } -} - -//***************************************************************************** -// -//! Enables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to enable. -//! -//! This function enables the interrupts in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Interrupts that have been previously been enabled are not disabled -//! when this function is called. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Set the flags. - // - HWREG(ui32Base + AES_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 16) | - ((ui32IntFlags & 0x00060000) >> 15) | - ((ui32IntFlags & 0x00080000) >> 18)); - HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function disables the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Clear the flags. - // - HWREG(ui32Base + AES_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 16) | - ((ui32IntFlags & 0x00060000) >> 15) | - ((ui32IntFlags & 0x00080000) >> 18)); - HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function clears the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Only the DMA done interrupts can be cleared. The remaining -//! interrupts should be disabled with AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - HWREG(ui32Base + AES_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 16) | - ((ui32IntFlags & 0x00060000) >> 15) | - ((ui32IntFlags & 0x00080000) >> 18)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled AES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables AES interrupts on the interrupt controller; specific AES -//! interrupt sources must be enabled using AESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! AESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() is used to enable AES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_AES0_TM4C129, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_AES0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_AES0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_AES0_TM4C129); -} - -//***************************************************************************** -// -//! Enables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be enabled. -//! -//! This function enables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Set the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be disabled. -//! -//! This function disables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the -//! following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Clear the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/aes.h b/bsp/tm4c129x-dk/libraries/driverlib/aes.h deleted file mode 100644 index 6cf44780dd..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/aes.h +++ /dev/null @@ -1,218 +0,0 @@ -//***************************************************************************** -// -// aes.h - Defines and Macros for the AES module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_AES_H__ -#define __DRIVERLIB_AES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the operation direction in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_DIR_ENCRYPT 0x00000004 -#define AES_CFG_DIR_DECRYPT 0x00000000 - -//***************************************************************************** -// -// The following defines are used to specify the key size in the ui32Config -// argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_KEY_SIZE_128BIT 0x00000008 -#define AES_CFG_KEY_SIZE_192BIT 0x00000010 -#define AES_CFG_KEY_SIZE_256BIT 0x00000018 - -//***************************************************************************** -// -// The following defines are used to specify the mode of operation in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_MODE_M 0x2007fe60 -#define AES_CFG_MODE_ECB 0x00000000 -#define AES_CFG_MODE_CBC 0x00000020 -#define AES_CFG_MODE_CTR 0x00000040 -#define AES_CFG_MODE_ICM 0x00000200 -#define AES_CFG_MODE_CFB 0x00000400 -#define AES_CFG_MODE_XTS_TWEAKJL \ - 0x00000800 -#define AES_CFG_MODE_XTS_K2IJL \ - 0x00001000 -#define AES_CFG_MODE_XTS_K2ILJ0 \ - 0x00001800 -#define AES_CFG_MODE_F8 0x00002000 -#define AES_CFG_MODE_F9 0x20004000 -#define AES_CFG_MODE_CBCMAC 0x20008000 -#define AES_CFG_MODE_GCM_HLY0ZERO \ - 0x20010000 -#define AES_CFG_MODE_GCM_HLY0CALC \ - 0x20020040 -#define AES_CFG_MODE_GCM_HY0CALC \ - 0x20030040 -#define AES_CFG_MODE_CCM 0x20040040 - -//***************************************************************************** -// -// The following defines are used to specify the counter width in the -// ui32Config argument in the AESConfig function. It is only required to -// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. -// -//***************************************************************************** -#define AES_CFG_CTR_WIDTH_32 0x00000000 -#define AES_CFG_CTR_WIDTH_64 0x00000080 -#define AES_CFG_CTR_WIDTH_96 0x00000100 -#define AES_CFG_CTR_WIDTH_128 0x00000180 - -//***************************************************************************** -// -// The following defines are used to define the width of the length field for -// CCM operation through the ui32Config argument in the AESConfig function. -// This value is also known as L. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_L_1 0x00000000 -#define AES_CFG_CCM_L_2 0x00080000 -#define AES_CFG_CCM_L_3 0x00100000 -#define AES_CFG_CCM_L_4 0x00180000 -#define AES_CFG_CCM_L_5 0x00200000 -#define AES_CFG_CCM_L_6 0x00280000 -#define AES_CFG_CCM_L_7 0x00300000 -#define AES_CFG_CCM_L_8 0x00380000 - -//***************************************************************************** -// -// The following defines are used to define the length of the authentication -// field for CCM operations through the ui32Config argument in the AESConfig -// function. This value is also known as M. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_M_4 0x00400000 -#define AES_CFG_CCM_M_6 0x00800000 -#define AES_CFG_CCM_M_8 0x00c00000 -#define AES_CFG_CCM_M_10 0x01000000 -#define AES_CFG_CCM_M_12 0x01400000 -#define AES_CFG_CCM_M_14 0x01800000 -#define AES_CFG_CCM_M_16 0x01c00000 - -//***************************************************************************** -// -// Interrupt flags for use with the AESIntEnable, AESIntDisable, and -// AESIntStatus functions. -// -//***************************************************************************** -#define AES_INT_CONTEXT_IN 0x00000001 -#define AES_INT_CONTEXT_OUT 0x00000008 -#define AES_INT_DATA_IN 0x00000002 -#define AES_INT_DATA_OUT 0x00000004 -#define AES_INT_DMA_CONTEXT_IN 0x00010000 -#define AES_INT_DMA_CONTEXT_OUT 0x00080000 -#define AES_INT_DMA_DATA_IN 0x00020000 -#define AES_INT_DMA_DATA_OUT 0x00040000 - -//***************************************************************************** -// -// Defines used when enabling and disabling DMA requests in the -// AESEnableDMA and AESDisableDMA functions. -// -//***************************************************************************** -#define AES_DMA_DATA_IN 0x00000020 -#define AES_DMA_DATA_OUT 0x00000040 -#define AES_DMA_CONTEXT_IN 0x00000080 -#define AES_DMA_CONTEXT_OUT 0x00000100 - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length); -extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t ui32Length, uint32_t *pui32Tag); -extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length, - uint32_t *pui32AuthSrc, - uint32_t ui32AuthLength, uint32_t *pui32Tag); -extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src); -extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); -extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); -extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); -extern void AESIntUnregister(uint32_t ui32Base); -extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata); -extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata); -extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t ui32Keysize); -extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t ui32Keysize); -extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key); -extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length); -extern void AESReset(uint32_t ui32Base); -extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_AES_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/can.h b/bsp/tm4c129x-dk/libraries/driverlib/can.h deleted file mode 100644 index 199721906b..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/can.h +++ /dev/null @@ -1,449 +0,0 @@ -//***************************************************************************** -// -// can.h - Defines and Macros for the CAN controller. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CAN_H__ -#define __DRIVERLIB_CAN_H__ - -//***************************************************************************** -// -//! \addtogroup can_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Miscellaneous defines for Message ID Types -// -//***************************************************************************** - -//***************************************************************************** -// -// These are the flags used by the tCANMsgObject.ui32Flags value when calling -// the CANMessageSet() and CANMessageGet() functions. -// -//***************************************************************************** - -// -//! This indicates that transmit interrupts are enabled. -// -#define MSG_OBJ_TX_INT_ENABLE 0x00000001 - -// -//! This indicates that receive interrupts are enabled. -// -#define MSG_OBJ_RX_INT_ENABLE 0x00000002 - -// -//! This indicates that a message object is using an extended identifier. -// -#define MSG_OBJ_EXTENDED_ID 0x00000004 - -// -//! This indicates that a message object is using filtering based on the -//! object's message identifier. -// -#define MSG_OBJ_USE_ID_FILTER 0x00000008 - -// -//! This indicates that new data was available in the message object. -// -#define MSG_OBJ_NEW_DATA 0x00000080 - -// -//! This indicates that data was lost since this message object was last -//! read. -// -#define MSG_OBJ_DATA_LOST 0x00000100 - -// -//! This indicates that a message object uses or is using filtering -//! based on the direction of the transfer. If the direction filtering is -//! used, then ID filtering must also be enabled. -// -#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER) - -// -//! This indicates that a message object uses or is using message -//! identifier filtering based on the extended identifier. If the extended -//! identifier filtering is used, then ID filtering must also be enabled. -// -#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER) - -// -//! This indicates that a message object is a remote frame. -// -#define MSG_OBJ_REMOTE_FRAME 0x00000040 - -// -//! This indicates that this message object is part of a FIFO structure and -//! not the final message object in a FIFO. -// -#define MSG_OBJ_FIFO 0x00000200 - -// -//! This indicates that a message object has no flags set. -// -#define MSG_OBJ_NO_FLAGS 0x00000000 - -//***************************************************************************** -// -//! This define is used with the flag values to allow checking only status -//! flags and not configuration flags. -// -//***************************************************************************** -#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) - -//***************************************************************************** -// -//! The structure used for encapsulating all the items associated with a CAN -//! message object in the CAN controller. -// -//***************************************************************************** -typedef struct -{ - // - //! The CAN message identifier used for 11 or 29 bit identifiers. - // - uint32_t ui32MsgID; - - // - //! The message identifier mask used when identifier filtering is enabled. - // - uint32_t ui32MsgIDMask; - - // - //! This value holds various status flags and settings specified by - //! tCANObjFlags. - // - uint32_t ui32Flags; - - // - //! This value is the number of bytes of data in the message object. - // - uint32_t ui32MsgLen; - - // - //! This is a pointer to the message object's data. - // - uint8_t *pui8MsgData; -} -tCANMsgObject; - -//***************************************************************************** -// -//! This structure is used for encapsulating the values associated with setting -//! up the bit timing for a CAN controller. The structure is used when calling -//! the CANGetBitTiming and CANSetBitTiming functions. -// -//***************************************************************************** -typedef struct -{ - // - //! This value holds the sum of the Synchronization, Propagation, and Phase - //! Buffer 1 segments, measured in time quanta. The valid values for this - //! setting range from 2 to 16. - // - uint32_t ui32SyncPropPhase1Seg; - - // - //! This value holds the Phase Buffer 2 segment in time quanta. The valid - //! values for this setting range from 1 to 8. - // - uint32_t ui32Phase2Seg; - - // - //! This value holds the Resynchronization Jump Width in time quanta. The - //! valid values for this setting range from 1 to 4. - // - uint32_t ui32SJW; - - // - //! This value holds the CAN_CLK divider used to determine time quanta. - //! The valid values for this setting range from 1 to 1023. - // - uint32_t ui32QuantumPrescaler; -} -tCANBitClkParms; - -//***************************************************************************** -// -//! This data type is used to identify the interrupt status register. This is -//! used when calling the CANIntStatus() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the CAN interrupt status information. - // - CAN_INT_STS_CAUSE, - - // - //! Read a message object's interrupt status. - // - CAN_INT_STS_OBJECT -} -tCANIntStsReg; - -//***************************************************************************** -// -//! This data type is used to identify which of several status registers to -//! read when calling the CANStatusGet() function. -// -//***************************************************************************** -typedef enum -{ - // - //! Read the full CAN controller status. - // - CAN_STS_CONTROL, - - // - //! Read the full 32-bit mask of message objects with a transmit request - //! set. - // - CAN_STS_TXREQUEST, - - // - //! Read the full 32-bit mask of message objects with new data available. - // - CAN_STS_NEWDAT, - - // - //! Read the full 32-bit mask of message objects that are enabled. - // - CAN_STS_MSGVAL -} -tCANStsReg; - -//***************************************************************************** -// -// These definitions are used to specify interrupt sources to CANIntEnable() -// and CANIntDisable(). -// -//***************************************************************************** -// -//! This flag is used to allow a CAN controller to generate error -//! interrupts. -// -#define CAN_INT_ERROR 0x00000008 - -// -//! This flag is used to allow a CAN controller to generate status -//! interrupts. -// -#define CAN_INT_STATUS 0x00000004 - -// -//! This flag is used to allow a CAN controller to generate any CAN -//! interrupts. If this is not set, then no interrupts are generated -//! by the CAN controller. -// -#define CAN_INT_MASTER 0x00000002 - -//***************************************************************************** -// -//! This definition is used to determine the type of message object that is -//! set up via a call to the CANMessageSet() API. -// -//***************************************************************************** -typedef enum -{ - // - //! Transmit message object. - // - MSG_OBJ_TYPE_TX, - - // - //! Transmit remote request message object - // - MSG_OBJ_TYPE_TX_REMOTE, - - // - //! Receive message object. - // - MSG_OBJ_TYPE_RX, - - // - //! Receive remote request message object. - // - MSG_OBJ_TYPE_RX_REMOTE, - - // - //! Remote frame receive remote, with auto-transmit message object. - // - MSG_OBJ_TYPE_RXTX_REMOTE -} -tMsgObjType; - -//***************************************************************************** -// -// The following enumeration contains all error or status indicators that can -// be returned when calling the CANStatusGet() function. -// -//***************************************************************************** -// -//! CAN controller has entered a Bus Off state. -// -#define CAN_STATUS_BUS_OFF 0x00000080 - -// -//! CAN controller error level has reached warning level. -// -#define CAN_STATUS_EWARN 0x00000040 - -// -//! CAN controller error level has reached error passive level. -// -#define CAN_STATUS_EPASS 0x00000020 - -// -//! A message was received successfully since the last read of this status. -// -#define CAN_STATUS_RXOK 0x00000010 - -// -//! A message was transmitted successfully since the last read of this -//! status. -// -#define CAN_STATUS_TXOK 0x00000008 - -// -//! This is the mask for the last error code field. -// -#define CAN_STATUS_LEC_MSK 0x00000007 - -// -//! There was no error. -// -#define CAN_STATUS_LEC_NONE 0x00000000 - -// -//! A bit stuffing error has occurred. -// -#define CAN_STATUS_LEC_STUFF 0x00000001 - -// -//! A formatting error has occurred. -// -#define CAN_STATUS_LEC_FORM 0x00000002 - -// -//! An acknowledge error has occurred. -// -#define CAN_STATUS_LEC_ACK 0x00000003 - -// -//! The bus remained a bit level of 1 for longer than is allowed. -// -#define CAN_STATUS_LEC_BIT1 0x00000004 - -// -//! The bus remained a bit level of 0 for longer than is allowed. -// -#define CAN_STATUS_LEC_BIT0 0x00000005 - -// -//! A CRC error has occurred. -// -#define CAN_STATUS_LEC_CRC 0x00000006 - -// -//! This is the mask for the CAN Last Error Code (LEC). -// -#define CAN_STATUS_LEC_MASK 0x00000007 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms); -extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms); -extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, - uint32_t ui32BitRate); -extern void CANDisable(uint32_t ui32Base); -extern void CANEnable(uint32_t ui32Base); -extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, - uint32_t *pui32TxCount); -extern void CANInit(uint32_t ui32Base); -extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr); -extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg); -extern void CANIntUnregister(uint32_t ui32Base); -extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID); -extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, bool bClrPendingInt); -extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, tMsgObjType eMsgType); -extern bool CANRetryGet(uint32_t ui32Base); -extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry); -extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CAN_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/comp.c b/bsp/tm4c129x-dk/libraries/driverlib/comp.c deleted file mode 100644 index 6f03b7c01a..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/comp.c +++ /dev/null @@ -1,452 +0,0 @@ -//***************************************************************************** -// -// comp.c - Driver for the analog comparator. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup comp_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_comp.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/comp.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Configures a comparator. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator to configure. -//! \param ui32Config is the configuration of the comparator. -//! -//! This function configures a comparator. The \e ui32Config parameter is the -//! result of a logical OR operation between the \b COMP_TRIG_xxx, -//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. -//! -//! The \b COMP_TRIG_xxx term can take on the following values: -//! -//! - \b COMP_TRIG_NONE to have no trigger to the ADC. -//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. -//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. -//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. -//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes -//! high. -//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low -//! or high. -//! -//! The \b COMP_INT_xxx term can take on the following values: -//! -//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is -//! high. -//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is -//! low. -//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes -//! low. -//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes -//! high. -//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes -//! low or high. -//! -//! The \b COMP_ASRCP_xxx term can take on the following values: -//! -//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference -//! voltage. -//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this -//! the same as \b COMP_ASRCP_PIN for the comparator 0). -//! - \b COMP_ASRCP_REF to use the internally generated voltage as the -//! reference voltage. -//! -//! The \b COMP_OUTPUT_xxx term can take on the following values: -//! -//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator -//! to a device pin. -//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to -//! a device pin. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Configure this comparator. - // - HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACCTL0) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the internal reference voltage. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Ref is the desired reference voltage. -//! -//! This function sets the internal reference voltage value. The voltage is -//! specified as one of the following values: -//! -//! - \b COMP_REF_OFF to turn off the reference voltage -//! - \b COMP_REF_0V to set the reference voltage to 0 V -//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V -//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V -//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V -//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V -//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V -//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V -//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V -//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V -//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V -//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V -//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V -//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V -//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V -//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V -//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V -//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V -//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V -//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V -//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V -//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V -//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V -//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V -//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V -//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V -//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V -//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V -//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - - // - // Set the voltage reference voltage as requested. - // - HWREG(ui32Base + COMP_O_ACREFCTL) = ui32Ref; -} - -//***************************************************************************** -// -//! Gets the current comparator output value. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function retrieves the current value of the comparator output. -//! -//! \return Returns \b true if the comparator output is high and \b false if -//! the comparator output is low. -// -//***************************************************************************** -bool -ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Return the appropriate value based on the comparator's present output - // value. - // - if(HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACSTAT0) & - COMP_ACSTAT0_OVAL) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! \param pfnHandler is a pointer to the function to be called when the -//! comparator interrupt occurs. -//! -//! This function sets the handler to be called when the comparator interrupt -//! occurs and enables the interrupt in the interrupt controller. It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! ComparatorIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_COMP0_TM4C123 + ui32Comp, pfnHandler); - - // - // Enable the interrupt in the interrupt controller. - // - IntEnable(INT_COMP0_TM4C123 + ui32Comp); - - // - // Enable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp; -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function clears the handler to be called when a comparator interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp); - - // - // Disable the interrupt in the interrupt controller. - // - IntDisable(INT_COMP0_TM4C123 + ui32Comp); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_COMP0_TM4C123 + ui32Comp); -} - -//***************************************************************************** -// -//! Enables the comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function enables generation of an interrupt from the specified -//! comparator. Only enabled comparator interrupts can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Enable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp; -} - -//***************************************************************************** -// -//! Disables the comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! This function disables generation of an interrupt from the specified -//! comparator. Only enabled comparator interrupts can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the comparator. Either the -//! raw or the masked interrupt status can be returned. -//! -//! \return \b true if the interrupt is asserted and \b false if it is not -//! asserted. -// -//***************************************************************************** -bool -ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(((HWREG(ui32Base + COMP_O_ACMIS) >> ui32Comp) & 1) ? true : - false); - } - else - { - return(((HWREG(ui32Base + COMP_O_ACRIS) >> ui32Comp) & 1) ? true : - false); - } -} - -//***************************************************************************** -// -//! Clears a comparator interrupt. -//! -//! \param ui32Base is the base address of the comparator module. -//! \param ui32Comp is the index of the comparator. -//! -//! The comparator interrupt is cleared, so that it no longer asserts. This -//! function must be called in the interrupt handler to keep the handler from -//! being called again immediately upon exit. Note that for a level-triggered -//! interrupt, the interrupt cannot be cleared until it stops asserting. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == COMP_BASE); - ASSERT(ui32Comp < 3); - - // - // Clear the interrupt. - // - HWREG(ui32Base + COMP_O_ACMIS) = 1 << ui32Comp; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/comp.h b/bsp/tm4c129x-dk/libraries/driverlib/comp.h deleted file mode 100644 index 2f95df09c9..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/comp.h +++ /dev/null @@ -1,141 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_COMP_H__ -#define __DRIVERLIB_COMP_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ui32Config -// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and -// so on), one of the values may be selected and combined together with values -// from the other groups via a logical OR. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, - uint32_t ui32Config); -extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref); -extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp); -extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp); -extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp); -extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp); -extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, - bool bMasked); -extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_COMP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/cpu.c b/bsp/tm4c129x-dk/libraries/driverlib/cpu.c deleted file mode 100644 index 0cddffc340..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/cpu.c +++ /dev/null @@ -1,457 +0,0 @@ -//***************************************************************************** -// -// cpu.c - Instruction wrappers for special CPU instructions needed by the -// drivers. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include "driverlib/cpu.h" - -//***************************************************************************** -// -// Wrapper function for the CPSID instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUcpsid(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - cpsid i; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function returning the state of PRIMASK (indicating whether -// interrupts are enabled or disabled). -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUprimask(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUcpsie(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - mrs r0, PRIMASK; - cpsie i; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the WFI instruction. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -void __attribute__((naked)) -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - wfi; - bx lr -} -#endif -#if defined(ccs) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for writing the BASEPRI register. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -void __attribute__((naked)) -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - msr BASEPRI, r0; - bx lr -} -#endif -#if defined(ccs) -void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for reading the BASEPRI register. -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUbasepriGet(void) -{ - uint32_t ui32Ret; - - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n" - : "=r" (ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(ewarm) -uint32_t -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - mrs r0, BASEPRI; - bx lr -} -#endif -#if defined(ccs) -uint32_t -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif diff --git a/bsp/tm4c129x-dk/libraries/driverlib/crc.c b/bsp/tm4c129x-dk/libraries/driverlib/crc.c deleted file mode 100644 index 55bd4d6048..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/crc.c +++ /dev/null @@ -1,311 +0,0 @@ -//***************************************************************************** -// -// crc.c - Driver for the CRC module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup crc_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ccm.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/crc.h" -#include "driverlib/debug.h" - - -//***************************************************************************** -// -//! Set the configuration of CRC functionality with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32CRCConfig is the configuration of the CRC engine. -//! -//! This function configures the operation of the CRC engine within the EC -//! module. The configuration is specified with the \e ui32CRCConfig argument. -//! It is the logical OR of any of the following options: -//! -//! CRC Initialization Value -//! - \b CRC_CFG_INIT_SEED - Initialize with seed value -//! - \b CRC_CFG_INIT_0 - Initialize to all '0s' -//! - \b CRC_CFG_INIT_1 - Initialize to all '1s' -//! -//! Input Data Size -//! - \b CRC_CFG_SIZE_8BIT - Input data size of 8 bits -//! - \b CRC_CFG_SIZE_32BIT - Input data size of 32 bits -//! -//! Post Process Reverse/Inverse -//! - \b CRC_CFG_RESINV - Result inverse enable -//! - \b CRC_CFG_OBR - Output reverse enable -//! -//! Input Bit Reverse -//! - \b CRC_CFG_IBR - Bit reverse enable -//! -//! Endian Control -//! - \b CRC_CFG_ENDIAN_SBHW - Swap byte in half-word -//! - \b CRC_CFG_ENDIAN_SHW - Swap half-word -//! -//! Operation Type -//! - \b CRC_CFG_TYPE_P8005 - Polynomial 0x8005 -//! - \b CRC_CFG_TYPE_P1021 - Polynomial 0x1021 -//! - \b CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7 -//! - \b CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41 -//! - \b CRC_CFG_TYPE_TCPCHKSUM - TCP checksum -//! -//! \return None. -// -//***************************************************************************** -void -CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) || - (ui32CRCConfig & CRC_CFG_INIT_0) || - (ui32CRCConfig & CRC_CFG_INIT_1) || - (ui32CRCConfig & CRC_CFG_SIZE_8BIT) || - (ui32CRCConfig & CRC_CFG_SIZE_32BIT) || - (ui32CRCConfig & CRC_CFG_RESINV) || - (ui32CRCConfig & CRC_CFG_OBR) || - (ui32CRCConfig & CRC_CFG_IBR) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) || - (ui32CRCConfig & CRC_CFG_TYPE_P8005) || - (ui32CRCConfig & CRC_CFG_TYPE_P1021) || - (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) || - (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) || - (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM)); - - // - // Write the control register with the configuration. - // - HWREG(ui32Base + CCM_O_CRCCTRL) = ui32CRCConfig; -} - -//***************************************************************************** -// -//! Write the seed value for CRC operations in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Seed is the seed value. -//! -//! This function writes the seed value for use with CRC operations in the -//! EC module. This value is the start value for CRC operations. If this -//! value is not written, then the residual seed from the previous operation -//! is used as the starting value. -//! -//! \note The seed must be written only if \b CRC_CFG_INIT_SEED is -//! set with the CRCConfigSet() function. -// -//***************************************************************************** -void -CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // Write the seed value to the seed register. - // - HWREG(ui32Base + CCM_O_CRCSEED) = ui32Seed; -} - -//***************************************************************************** -// -//! Write data into the EC module for CRC operations. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Data is the data to be written. -//! -//! This function writes either 8 or 32 bits of data into the EC module for -//! CRC operations. The distinction between 8 and 32 bits of data is made -//! when the \b CRC_CFG_SIZE_8BIT or \b CRC_CFG_SIZE_32BIT flag -//! is set using the CRCConfigSet() function. -//! -//! When writing 8 bits of data, ensure the data is in the least significant -//! byte position. The remaining bytes should be written with zero. For -//! example, when writing 0xAB, \e ui32Data should be 0x000000AB. -//! -//! \return None -// -//***************************************************************************** -void -CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // Write the data - // - HWREG(ui32Base + CCM_O_CRCDIN) = ui32Data; -} - -//***************************************************************************** -// -//! Reads the result of a CRC operation in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param bPPResult is \b true to read the post-processed result, or \b false -//! to read the unmodified result. -//! -//! This function reads either the unmodified CRC result or the post -//! processed CRC result from the EC module. The post-processing options -//! are selectable through \b CRC_CFG_RESINV and \b CRC_CFG_OBR -//! parameters in the CRCConfigSet() function. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCResultRead(uint32_t ui32Base, bool bPPResult) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // Depending on the value of bPPResult, read the appropriate register and - // return value. - // - if(bPPResult) - { - return(HWREG(ui32Base + CCM_O_CRCRSLTPP)); - } - else - { - return(HWREG(ui32Base + CCM_O_CRCSEED)); - } -} - -//***************************************************************************** -// -//! Process data to generate a CRC with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param pui32DataIn is a pointer to an array of data that is processed. -//! \param ui32DataLength is the number of data items that are processed -//! to produce the CRC. -//! \param bPPResult is \b true to read the post-processed result, or \b false -//! to read the unmodified result. -//! -//! This function processes an array of data to produce a CRC result. -//! -//! The data in the array pointed to be \e pui32DataIn is either an array -//! of bytes or an array or words depending on the selection of the input -//! data size options \b CRC_CFG_SIZE_8BIT and -//! \b CRC_CFG_SIZE_32BIT. -//! -//! This function returns either the unmodified CRC result or the -//! post- processed CRC result from the EC module. The post-processing -//! options are selectable through \b CRC_CFG_RESINV and -//! \b CRC_CFG_OBR parameters. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, - uint32_t ui32DataLength, bool bPPResult) -{ - uint8_t *pui8DataIn; - - // - // Check the arguments. - // - ASSERT(ui32Base == CCM0_BASE); - - // - // See if the CRC is operating in 8-bit or 32-bit mode. - // - if(HWREG(ui32Base + CCM_O_CRCCTRL) & CCM_CRCCTRL_SIZE) - { - // - // The CRC is operating in 8-bit mode, so create an 8-bit pointer to - // the data. - // - pui8DataIn = (uint8_t *)pui32DataIn; - - // - // Loop through the input data. - // - while(ui32DataLength--) - { - // - // Write the next data byte. - // - HWREG(ui32Base + CCM_O_CRCDIN) = *pui8DataIn++; - } - } - else - { - // - // The CRC is operating in 32-bit mode, so loop through the input data. - // - while(ui32DataLength--) - { - // - // Write the next data word. - // - HWREG(ui32Base + CCM_O_CRCDIN) = *pui32DataIn++; - } - } - - // - // Return the result. - // - return(CRCResultRead(ui32Base, bPPResult)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/crc.h b/bsp/tm4c129x-dk/libraries/driverlib/crc.h deleted file mode 100644 index 7d33e84cb6..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/crc.h +++ /dev/null @@ -1,101 +0,0 @@ -//***************************************************************************** -// -// crc.h - Defines and Macros for CRC module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CRC_H__ -#define __DRIVERLIB_CRC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used in the ui32Config argument of the -// ECConfig function. -// -//***************************************************************************** -#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed -#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' -#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' -#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size -#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size -#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable -#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable -#define CRC_CFG_IBR 0x00000080 // Bit reverse enable -#define CRC_CFG_ENDIAN_SBHW 0x00000020 // Swap byte in half-word -#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word -#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 -#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 -#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 -#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -#if 0 -extern void ECClockGatingReqest(uint32_t ui32Base, uint32_t ui32ECIP, - bool bGate); -#endif -extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); -extern uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, - uint32_t ui32DataLength, bool bPPResult); -extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); -extern uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult); -extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CRC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/des.c b/bsp/tm4c129x-dk/libraries/driverlib/des.c deleted file mode 100644 index 1b6e86a2a8..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/des.c +++ /dev/null @@ -1,807 +0,0 @@ -//***************************************************************************** -// -// des.c - Driver for the DES data transformation. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup des_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_des.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/des.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Resets the DES Module. -//! -//! \param ui32Base is the base address of the DES module. -//! -//! This function performs a soft-reset sequence of the DES module. -//! -//! \return None. -// -//***************************************************************************** -void -DESReset(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Trigger the soft reset. - // - HWREG(ui32Base + DES_O_SYSCONFIG) |= DES_SYSCONFIG_SOFTRESET; - - // - // Wait for the reset to finish. - // - while((HWREG(ui32Base + DES_O_SYSSTATUS) & - DES_SYSSTATUS_RESETDONE) == 0) - { - } -} - -//***************************************************************************** -// -//! Configures the DES module for operation. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Config is the configuration of the DES module. -//! -//! This function configures the DES module for operation. -//! -//! The \e ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped below based on their function. -//! -//! The direction of the operation is specified with one of the following two -//! flags. Only one is permitted. -//! -//! - \b DES_CFG_DIR_ENCRYPT - Encryption -//! - \b DES_CFG_DIR_DECRYPT - Decryption -//! -//! The operational mode of the DES engine is specified with one of the -//! following flags. Only one is permitted. -//! -//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode -//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode -//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode -//! -//! The selection of single DES or triple DES is specified with one of the -//! following two flags. Only one is permitted. -//! -//! - \b DES_CFG_SINGLE - Single DES -//! - \b DES_CFG_TRIPLE - Triple DES -//! -//! \return None. -// -//***************************************************************************** -void -DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Backup the save context field. - // - ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); - - // - // Write the control register. - // - HWREG(ui32Base + DES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the key used for DES operations. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Key is a pointer to an array that holds the key -//! -//! This function sets the key used for DES operations. -//! -//! \e pui32Key should be 64 bits long (2 words) if single DES is being used or -//! 192 bits (6 words) if triple DES is being used. -//! -//! \return None. -// -//***************************************************************************** -void -DESKeySet(uint32_t ui32Base, uint32_t *pui32Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the first part of the key. - // - HWREG(ui32Base + DES_O_KEY1_L) = pui32Key[0]; - HWREG(ui32Base + DES_O_KEY1_H) = pui32Key[1]; - - // - // If we are performing tripe DES, then write the key registers for - // the second and third rounds. - // - if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) - { - HWREG(ui32Base + DES_O_KEY2_L) = pui32Key[2]; - HWREG(ui32Base + DES_O_KEY2_H) = pui32Key[3]; - HWREG(ui32Base + DES_O_KEY3_L) = pui32Key[4]; - HWREG(ui32Base + DES_O_KEY3_H) = pui32Key[5]; - } -} - -//***************************************************************************** -// -//! Sets the initialization vector in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32IVdata is a pointer to an array of 64 bits (2 words) of data to -//! be written into the initialization vectors registers. -//! -//! This function sets the initialization vector in the DES module. It returns -//! true if the registers were successfully written. If the context registers -//! cannot be written at the time the function was called, then false is -//! returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check to see if context registers can be overwritten. If not, return - // false. - // - if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) - { - return(false); - } - - // - // Write the initialization vector registers. - // - HWREG(ui32Base + DES_O_IV_L) = pui32IVdata[0]; - HWREG(ui32Base + DES_O_IV_H) = pui32IVdata[1]; - - // - // Return true to indicate the write was successful. - // - return(true); -} - -//***************************************************************************** -// -//! Sets the crytographic data length in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Length is the length of the data in bytes. -//! -//! This function writes the cryptographic data length into the DES module. -//! When this register is written, the engine is triggered to start using this -//! context. -//! -//! \note Data lengths up to (2^32 - 1) bytes are allowed. -//! -//! \return None. -// -//***************************************************************************** -void -DESLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the length register. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Dest is a pointer to an array of 2 words. -//! -//! This function returns true if the data was ready when the function was -//! called. If the data was not ready, false is returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check to see if the data is ready to be read. - // - if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Dest is a pointer to an array of bytes. -//! -//! This function waits until the DES module is finished and encrypted or -//! decrypted data is ready. The output data is then stored in the pui32Dest -//! array. -//! -//! \return None -// -//***************************************************************************** -void -DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Wait for data output to be ready. - // - while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0) - { - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Src is a pointer to an array of 2 words. -//! -//! This function returns false if the DES module is not ready to accept -//! data. It returns true if the data was written successfully. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check if the DES module is ready to encrypt or decrypt data. If it - // is not, return false. - // - if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL)))) - { - return(false); - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Src is a pointer to an array of bytes. -//! -//! This function waits until the DES module is ready before writing the -//! data contained in the pui32Src array. -//! -//! \return None. -// -//***************************************************************************** -void -DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Wait for the input ready bit to go high. - // - while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0) - { - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; -} - -//***************************************************************************** -// -//! Processes blocks of data through the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui32Src is a pointer to an array of words that contains the -//! source data for processing. -//! \param pui32Dest is a pointer to an array of words consisting of the -//! processed data. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! It must be a multiple of eight. -//! -//! This function takes the data contained in the pui32Src array and processes -//! it using the DES engine. The resulting data is stored in the -//! pui32Dest array. The function blocks until all of the data has been -//! processed. If processing is successful, the function returns true. -//! -//! \note This functions assumes that the DES module has been configured, -//! and initialization values and keys have been written. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, uint32_t *pui32Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Length % 8) == 0); - - // - // Write the length register first. This triggers the engine to start - // using this context. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; - - // - // Now loop until the blocks are written. - // - for(ui32Count = 0; ui32Count < (ui32Length / 4); ui32Count += 2) - { - // - // Check if the input ready is fine - // - while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - } - - // - // Write the block data. - // - DESDataWriteNonBlocking(ui32Base, pui32Src + ui32Count); - - // - // Wait for the output ready - // - while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - } - - // - // Read the processed data block. - // - DESDataReadNonBlocking(ui32Base, pui32Dest + ui32Count); - } - - // - // Return true to indicate the process was successful. - // - return(true); -} - -//***************************************************************************** -// -//! Returns the current interrupt status of the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function gets the current interrupt status of the DES module. -//! The value returned is a logical OR of the following values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT_INT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return A bit mask of the current interrupt status. -// -//***************************************************************************** -uint32_t -DESIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Status, ui32Enable; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Read the status register and return the value. - // - ui32Status = HWREG(ui32Base + DES_O_IRQSTATUS); - if(bMasked) - { - ui32Enable = HWREG(ui32Base + DES_O_IRQENABLE); - return((ui32Status & ui32Enable) | - (HWREG(ui32Base + DES_O_DMAMIS) << 16)); - } - else - { - return(ui32Status | (HWREG(ui32Base + DES_O_DMARIS) << 16)); - } -} - -//***************************************************************************** -// -//! Enables interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be enabled. -//! -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return None. -// -//***************************************************************************** -void -DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DATA_IN) || - (ui32IntFlags & DES_INT_DATA_OUT) || - (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - // - // Enable the interrupts from the flags. - // - HWREG(ui32Base + DES_O_DMAIM) |= (ui32IntFlags & 0x00070000) >> 16; - HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return None. -// -//***************************************************************************** -void -DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DATA_IN) || - (ui32IntFlags & DES_INT_DATA_OUT) || - (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - // - // Clear the interrupts from the flags. - // - HWREG(ui32Base + DES_O_DMAIM) &= ~((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using DESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - HWREG(ui32Base + DES_O_DMAIC) = (ui32IntFlags & 0x00070000) >> 16; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled DES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables DES interrupts on the interrupt controller; specific DES -//! interrupt sources must be enabled using DESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! DESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable DES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_DES0_TM4C129, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(INT_DES0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_DES0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_DES0_TM4C129); -} - -//***************************************************************************** -// -//! Enables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be enabled. -//! -//! This function enables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Set the data in and data out DMA request enable bits. - // - HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be disabled. -//! -//! This function disables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Disable the DMA sources. - // - HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/des.h b/bsp/tm4c129x-dk/libraries/driverlib/des.h deleted file mode 100644 index 9f6c8d1853..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/des.h +++ /dev/null @@ -1,140 +0,0 @@ -//***************************************************************************** -// -// des.h - Defines and Macros for the DES module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_DES_H__ -#define __DRIVERLIB_DES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the direction with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_DIR_DECRYPT 0x00000000 -#define DES_CFG_DIR_ENCRYPT 0x00000004 - -//***************************************************************************** -// -// The following defines are used to specify the operational with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_MODE_ECB 0x00000000 -#define DES_CFG_MODE_CBC 0x00000010 -#define DES_CFG_MODE_CFB 0x00000020 - -//***************************************************************************** -// -// The following defines are used to select between single DES and triple DES -// with the ui32Config argument in the DESConfig() function. Only one is -// permitted. -// -//***************************************************************************** -#define DES_CFG_SINGLE 0x00000000 -#define DES_CFG_TRIPLE 0x00000008 - -//***************************************************************************** -// -// The following defines are used with the DESIntEnable(), DESIntDisable() and -// DESIntStatus() functions. -// -//***************************************************************************** -#define DES_INT_CONTEXT_IN 0x00000001 -#define DES_INT_DATA_IN 0x00000002 -#define DES_INT_DATA_OUT 0x00000004 -#define DES_INT_DMA_CONTEXT_IN 0x00010000 -#define DES_INT_DMA_DATA_IN 0x00020000 -#define DES_INT_DMA_DATA_OUT 0x00040000 - -//***************************************************************************** -// -// The following defines are used with the DESEnableDMA() and DESDisableDMA() -// functions. -// -//***************************************************************************** -#define DES_DMA_CONTEXT_IN 0x00000080 -#define DES_DMA_DATA_OUT 0x00000040 -#define DES_DMA_DATA_IN 0x00000020 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest); -extern bool DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src, - uint32_t *pui32Dest, uint32_t ui32Length); -extern void DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src); -extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); -extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); -extern void DESIntUnregister(uint32_t ui32Base); -extern bool DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata); -extern void DESKeySet(uint32_t ui32Base, uint32_t *pui32Key); -extern void DESLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern void DESReset(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_DES_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.c b/bsp/tm4c129x-dk/libraries/driverlib/eeprom.c deleted file mode 100644 index 6daae87be0..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.c +++ /dev/null @@ -1,1156 +0,0 @@ -//***************************************************************************** -// -// eeprom.c - Driver for programming the on-chip EEPROM. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include -#include "inc/hw_eeprom.h" -#include "inc/hw_flash.h" -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/flash.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/eeprom.h" - -//***************************************************************************** -// -//! \addtogroup eeprom_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Useful macros to extract the number of EEPROM blocks available on the target -// device and the total EEPROM storage in bytes from the EESIZE register. -// -//***************************************************************************** -#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >> \ - EEPROM_EESIZE_BLKCNT_S) -#define SIZE_FROM_EESIZE(x) ((((x) & EEPROM_EESIZE_WORDCNT_M) >> \ - EEPROM_EESIZE_WORDCNT_S) * 4) - -//***************************************************************************** -// -// Useful macro to extract the offset from a linear address. -// -//***************************************************************************** -#define OFFSET_FROM_ADDR(x) (((x) >> 2) & 0x0F) - -//***************************************************************************** -// -// The key value required to initiate a mass erase. -// -//***************************************************************************** -#define EEPROM_MASS_ERASE_KEY ((uint32_t)0xE37B << EEPROM_EEDBGME_KEY_S) - -//***************************************************************************** -// -// This function implements a workaround for a bug in Blizzard rev A silicon. -// It ensures that only the 1KB flash sector containing a given EEPROM address -// is erased if an erase/copy operation is required as a result of a following -// EEPROM write. -// -//***************************************************************************** -static void -_EEPROMSectorMaskSet(uint32_t ui32Address) -{ - uint32_t ui32Mask; - - // - // Determine which page contains the passed EEPROM address. The 2KB EEPROM - // is implemented in 16KB of flash with each 1KB sector of flash holding - // values for 32 consecutive EEPROM words (or 128 bytes). - // - ui32Mask = ~(1 << (ui32Address >> 7)); - - SysCtlDelay(10); - HWREG(0x400FD0FC) = 3; - SysCtlDelay(10); - HWREG(0x400AE2C0) = ui32Mask; - SysCtlDelay(10); - HWREG(0x400FD0FC) = 0; - SysCtlDelay(10); -} - -//***************************************************************************** -// -// Clear the FSM sector erase mask to ensure that any following main array -// flash erase operations operate as expected. -// -//***************************************************************************** -static void -_EEPROMSectorMaskClear(void) -{ - SysCtlDelay(10); - HWREG(0x400FD0FC) = 3; - SysCtlDelay(10); - HWREG(0x400AE2C0) = 0; - SysCtlDelay(10); - HWREG(0x400FD0FC) = 0; - SysCtlDelay(10); -} - -//***************************************************************************** -// -// Block until the EEPROM peripheral is not busy. -// -//***************************************************************************** -static void -_EEPROMWaitForDone(void) -{ - // - // Is the EEPROM still busy? - // - while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) - { - // - // Spin while EEPROM is busy. - // - } -} - -//***************************************************************************** -// -//! Performs any necessary recovery in case of power failures during write. -//! -//! This function \b must be called after SysCtlPeripheralEnable() and before -//! the EEPROM is accessed. It is used to check for errors in the EEPROM state -//! such as from power failure during a previous write operation. The function -//! detects these errors and performs as much recovery as possible. -//! -//! If \b EEPROM_INIT_ERROR is returned, the EEPROM was unable to recover its -//! state. If power is stable when this occurs, this indicates a fatal -//! error and is likely an indication that the EEPROM memory has exceeded its -//! specified lifetime write/erase specification. If the supply voltage is -//! unstable when this return code is observed, retrying the operation once the -//! voltage is stabilized may clear the error. -//! -//! Failure to call this function after a reset may lead to incorrect operation -//! or permanent data loss if the EEPROM is later written. -//! -//! \return Returns \b EEPROM_INIT_OK if no errors were detected or \b -//! EEPROM_INIT_ERROR if the EEPROM peripheral cannot currently recover from -//! an interrupted write or erase operation. -// -//***************************************************************************** -uint32_t -EEPROMInit(void) -{ - uint32_t ui32Status; - - // - // Insert a small delay (6 cycles + call overhead) to guard against the - // possibility that this function is called immediately after the EEPROM - // peripheral is enabled. Without this delay, there is a slight chance - // that the first EEPROM register read will fault if you are using a - // compiler with a ridiculously good optimizer! - // - SysCtlDelay(2); - - // - // Make sure the EEPROM has finished any ongoing processing. - // - _EEPROMWaitForDone(); - - // - // Read the EESUPP register to see if any errors have been reported. - // - ui32Status = HWREG(EEPROM_EESUPP); - - // - // Did an error of some sort occur during initialization? - // - if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) - { - return(EEPROM_INIT_ERROR); - } - - // - // Perform a second EEPROM reset. - // - SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); - - // - // Wait for the EEPROM to complete its reset processing once again. - // - SysCtlDelay(2); - _EEPROMWaitForDone(); - - // - // Read EESUPP once again to determine if any error occurred. - // - ui32Status = HWREG(EEPROM_EESUPP); - - // - // Was an error reported following the second reset? - // - if(ui32Status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY)) - { - return(EEPROM_INIT_ERROR); - } - - // - // The EEPROM does not indicate that any error occurred. - // - return(EEPROM_INIT_OK); -} - - -//***************************************************************************** -// -//! Determines the size of the EEPROM. -//! -//! This function returns the size of the EEPROM in bytes. -//! -//! \return Returns the total number of bytes in the EEPROM. -// -//***************************************************************************** -uint32_t -EEPROMSizeGet(void) -{ - // - // Return the size of the EEPROM in bytes. - // - return(SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); -} - -//***************************************************************************** -// -//! Determines the number of blocks in the EEPROM. -//! -//! This function may be called to determine the number of blocks in the -//! EEPROM. Each block is the same size and the number of bytes of storage -//! contained in a block may be determined by dividing the size of the device, -//! obtained via a call to the EEPROMSizeGet() function, by the number of -//! blocks returned by this function. -//! -//! \return Returns the total number of blocks in the device EEPROM. -// -//***************************************************************************** -uint32_t -EEPROMBlockCountGet(void) -{ - // - // Extract the number of blocks and return it to the caller. - // -#ifdef EEPROM_SIZE_LIMIT - // - // If a size limit has been specified, fake the number of blocks to match. - // - return(EEPROM_SIZE_LIMIT / 48); -#else - // - // Return the actual number of blocks supported by the hardware. - // - return(BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); -#endif -} - -//***************************************************************************** -// -//! Reads data from the EEPROM. -//! -//! \param pui32Data is a pointer to storage for the data read from the EEPROM. -//! This pointer must point to at least \e ui32Count bytes of available memory. -//! \param ui32Address is the byte address within the EEPROM from which data is -//! to be read. This value must be a multiple of 4. -//! \param ui32Count is the number of bytes of data to read from the EEPROM. -//! This value must be a multiple of 4. -//! -//! This function may be called to read a number of words of data from a -//! word-aligned address within the EEPROM. Data read is copied into the -//! buffer pointed to by the \e pui32Data parameter. -//! -//! \return None. -// -//***************************************************************************** -void -EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) -{ - // - // Check parameters in a debug build. - // - ASSERT(pui32Data); - ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address + ui32Count) <= - SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address & 3) == 0); - ASSERT((ui32Count & 3) == 0); - - // - // Set the block and offset appropriately to read the first word. - // - HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); - HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); - - // - // Convert the byte count to a word count. - // - ui32Count /= 4; - - // - // Read each word in turn. - // - while(ui32Count) - { - // - // Read the next word through the autoincrementing register. - // - *pui32Data = HWREG(EEPROM_EERDWRINC); - - // - // Move on to the next word. - // - pui32Data++; - ui32Count--; - - // - // Do we need to move to the next block? This is the case if the - // offset register has just wrapped back to 0. Note that we only - // write the block register if we have more data to read. If this - // register is written, the hardware expects a read or write operation - // next. If a mass erase is requested instead, the mass erase will - // fail. - // - if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0)) - { - HWREG(EEPROM_EEBLOCK) += 1; - } - } -} - -//***************************************************************************** -// -//! Writes data to the EEPROM. -//! -//! \param pui32Data points to the first word of data to write to the EEPROM. -//! \param ui32Address defines the byte address within the EEPROM that the data -//! is to be written to. This value must be a multiple of 4. -//! \param ui32Count defines the number of bytes of data that is to be written. -//! This value must be a multiple of 4. -//! -//! This function may be called to write data into the EEPROM at a given -//! word-aligned address. The call is synchronous and returns only after -//! all data has been written or an error occurs. -//! -//! \return Returns 0 on success or non-zero values on failure. Failure codes -//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. -// -//***************************************************************************** -uint32_t -EEPROMProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) -{ - uint32_t ui32Status; - - // - // Check parameters in a debug build. - // - ASSERT(pui32Data); - ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address + ui32Count) <= - SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address & 3) == 0); - ASSERT((ui32Count & 3) == 0); - - // - // Make sure the EEPROM is idle before we start. - // - do - { - // - // Read the status. - // - ui32Status = HWREG(EEPROM_EEDONE); - } - while(ui32Status & EEPROM_EEDONE_WORKING); - - // - // Set the block and offset appropriately to program the first word. - // - HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); - HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); - - // - // Convert the byte count to a word count. - // - ui32Count /= 4; - - // - // Write each word in turn. - // - while(ui32Count) - { - // - // This is a workaround for a silicon problem on Blizzard rev A. We - // need to do this before every word write to ensure that we don't - // have problems in multi-word writes that span multiple flash sectors. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskSet(ui32Address); - } - - // - // Write the next word through the autoincrementing register. - // - HWREG(EEPROM_EERDWRINC) = *pui32Data; - - // - // Wait a few cycles. In some cases, the WRBUSY bit is not set - // immediately and this prevents us from dropping through the polling - // loop before the bit is set. - // - SysCtlDelay(10); - - // - // Wait for the write to complete. - // - do - { - // - // Read the status. - // - ui32Status = HWREG(EEPROM_EEDONE); - } - while(ui32Status & EEPROM_EEDONE_WORKING); - - // - // Make sure we completed the write without errors. Note that we - // must check this per-word because write permission can be set per - // block resulting in only a section of the write not being performed. - // - if(ui32Status & EEPROM_EEDONE_NOPERM) - { - // - // An error was reported that would prevent the values from - // being written correctly. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } - return(ui32Status); - } - - // - // Move on to the next word. - // - pui32Data++; - ui32Count--; - - // - // Do we need to move to the next block? This is the case if the - // offset register has just wrapped back to 0. Note that we only - // write the block register if we have more data to read. If this - // register is written, the hardware expects a read or write operation - // next. If a mass erase is requested instead, the mass erase will - // fail. - // - if(ui32Count && (HWREG(EEPROM_EEOFFSET) == 0)) - { - HWREG(EEPROM_EEBLOCK) += 1; - } - } - - // - // Clear the sector protection bits to prevent possible problems when - // programming the main flash array later. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } - - // - // Return the current status to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Writes a word to the EEPROM. -//! -//! \param ui32Data is the word to write to the EEPROM. -//! \param ui32Address defines the byte address within the EEPROM to which the -//! data is to be written. This value must be a multiple of 4. -//! -//! This function is intended to allow EEPROM programming under interrupt -//! control. It may be called to start the process of writing a single word of -//! data into the EEPROM at a given word-aligned address. The call is -//! asynchronous and returns immediately without waiting for the write to -//! complete. Completion of the operation is signaled by means of an -//! interrupt from the EEPROM module. The EEPROM peripheral shares a single -//! interrupt vector with the flash memory subsystem, \b INT_FLASH. -//! -//! \return Returns status and error information in the form of a logical OR -//! combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE and \b EEPROM_RC_WORKING. Flags -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING are -//! expected in normal operation and do not indicate an error. -// -//***************************************************************************** -uint32_t -EEPROMProgramNonBlocking(uint32_t ui32Data, uint32_t ui32Address) -{ - // - // Check parameters in a debug build. - // - ASSERT(ui32Address < SIZE_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT((ui32Address & 3) == 0); - - // - // This is a workaround for a silicon problem on Blizzard rev A. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskSet(ui32Address); - } - - // - // Set the block and offset appropriately to program the desired word. - // - HWREG(EEPROM_EEBLOCK) = EEPROMBlockFromAddr(ui32Address); - HWREG(EEPROM_EEOFFSET) = OFFSET_FROM_ADDR(ui32Address); - - // - // Write the new word using the auto-incrementing register just in case - // the caller wants to write follow-on words using direct register access - // - HWREG(EEPROM_EERDWRINC) = ui32Data; - - // - // Return the current status to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Erases the EEPROM and returns it to the factory default condition. -//! -//! This function completely erases the EEPROM and removes any and -//! all access protection on its blocks, leaving the device in the factory -//! default condition. After this operation, all EEPROM words contain the -//! value 0xFFFFFFFF and all blocks are accessible for both read and write -//! operations in all CPU modes. No passwords are active. -//! -//! The function is synchronous and does not return until the erase operation -//! has completed. -//! -//! \return Returns 0 on success or non-zero values on failure. Failure codes -//! are logical OR combinations of \b EEPROM_RC_WRBUSY, \b EEPROM_RC_NOPERM, -//! \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b EEPROM_RC_WORKING. -// -//***************************************************************************** -uint32_t -EEPROMMassErase(void) -{ - // - // This is a workaround for a silicon problem on Blizzard rev A. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } - - // - // Start the mass erase processing - // - HWREG(EEPROM_EEDBGME) = EEPROM_MASS_ERASE_KEY | EEPROM_EEDBGME_ME; - - // - // Wait for completion. - // - _EEPROMWaitForDone(); - - // - // Reset the peripheral. This is required so that all protection - // mechanisms and passwords are reset now that the EEPROM data has been - // scrubbed. - // - SysCtlPeripheralReset(SYSCTL_PERIPH_EEPROM0); - - // - // Wait for completion again. - // - SysCtlDelay(2); - _EEPROMWaitForDone(); - - // - // Pass any error codes back to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Returns the current protection level for an EEPROM block. -//! -//! \param ui32Block is the block number for which the protection level is to -//! be queried. -//! -//! This function returns the current protection settings for a given -//! EEPROM block. If block 0 is currently locked, it must be unlocked prior -//! to calling this function to query the protection setting for other blocks. -//! -//! \return Returns one of \b EEPROM_PROT_RW_LRO_URW, \b EEPROM_PROT_NA_LNA_URW -//! or \b EEPROM_PROT_RO_LNA_URO optionally OR-ed with -//! \b EEPROM_PROT_SUPERVISOR_ONLY. -// -//***************************************************************************** -uint32_t -EEPROMBlockProtectGet(uint32_t ui32Block) -{ - // - // Parameter validity check. - // - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Set the current block. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Return the protection flags for this block. - // - return(HWREG(EEPROM_EEPROT)); -} - -//***************************************************************************** -// -//! Set the current protection options for an EEPROM block. -//! -//! \param ui32Block is the block number for which the protection options are -//! to be set. -//! \param ui32Protect consists of one of the values \b EEPROM_PROT_RW_LRO_URW, -//! \b EEPROM_PROT_NA_LNA_URW or \b EEPROM_PROT_RO_LNA_URO optionally ORed with -//! \b EEPROM_PROT_SUPERVISOR_ONLY. -//! -//! This function sets the protection settings for a given EEPROM block -//! assuming no protection settings have previously been written. Note that -//! protection settings applied to block 0 have special meaning and control -//! access to the EEPROM peripheral as a whole. Protection settings applied to -//! blocks numbered 1 and above are layered above any protection set on block 0 -//! such that the effective protection on each block is the logical OR of the -//! protection flags set for block 0 and for the target block. This protocol -//! allows global protection options to be set for the whole device via block -//! 0 and more restrictive protection settings to be set on a block-by-block -//! basis. -//! -//! The protection flags indicate access permissions as follow: -//! -//! \b EEPROM_PROT_SUPERVISOR_ONLY restricts access to the block to threads -//! running in supervisor mode. If clear, both user and supervisor threads -//! can access the block. -//! -//! \b EEPROM_PROT_RW_LRO_URW provides read/write access to the block if no -//! password is set or if a password is set and the block is unlocked. If the -//! block is locked, only read access is permitted. -//! -//! \b EEPROM_PROT_NA_LNA_URW provides neither read nor write access unless -//! a password is set and the block is unlocked. If the block is unlocked, -//! both read and write access are permitted. -//! -//! \b EEPROM_PROT_RO_LNA_URO provides read access to the block if no password -//! is set or if a password is set and the block is unlocked. If the block is -//! password protected and locked, neither read nor write access is permitted. -//! -//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b -//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b -//! EEPROM_RC_WORKING to indicate status and error conditions. -// -//***************************************************************************** -uint32_t -EEPROMBlockProtectSet(uint32_t ui32Block, uint32_t ui32Protect) -{ - // - // Parameter validity check. - // - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Set the current block. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Set the protection options for this block. - // - HWREG(EEPROM_EEPROT) = ui32Protect; - - // - // Wait for the write to complete. - // - while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) - { - // - // Still working. - // - } - - // - // Pass any error codes back to the caller. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Sets the password used to protect an EEPROM block. -//! -//! \param ui32Block is the EEPROM block number for which the password is to be -//! set. -//! \param pui32Password points to an array of uint32_t values comprising -//! the password to set. Each element may be any 32-bit value other than -//! 0xFFFFFFFF. This array must contain the number of elements given by the -//! \e ui32Count parameter. -//! \param ui32Count provides the number of uint32_ts in the \e ui32Password. -//! Valid values are 1, 2 and 3. -//! -//! This function allows the password used to unlock an EEPROM block to be -//! set. Valid passwords may be either 32, 64 or 96 bits comprising words -//! with any value other than 0xFFFFFFFF. The password may only be set once. -//! Any further attempts to set the password result in an error. Once the -//! password is set, the block remains unlocked until EEPROMBlockLock() is -//! called for that block or block 0, or a reset occurs. -//! -//! If a password is set on block 0, this affects locking of the peripheral as -//! a whole. When block 0 is locked, all other EEPROM blocks are inaccessible -//! until block 0 is unlocked. Once block 0 is unlocked, other blocks -//! become accessible according to any passwords set on those blocks and the -//! protection set for that block via a call to EEPROMBlockProtectSet(). -//! -//! \return Returns a logical OR combination of \b EEPROM_RC_WRBUSY, \b -//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b -//! EEPROM_RC_WORKING to indicate status and error conditions. -// -//***************************************************************************** -uint32_t -EEPROMBlockPasswordSet(uint32_t ui32Block, uint32_t *pui32Password, - uint32_t ui32Count) -{ - uint32_t ui32Reg; - - // - // Check parameters in a debug build. - // - ASSERT(pui32Password); - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT(ui32Count <= 3); - - // - // Set the block number whose password we are about to write. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Start with the first password word. - // - ui32Reg = EEPROM_EEPASS0; - - // - // Write the password. - // - while(ui32Count) - { - // - // Start the process of writing the password. - // - HWREG(ui32Reg) = *pui32Password; - - // - // Update values in preparation for writing the next word. - // - pui32Password++; - ui32Reg += 4; - ui32Count--; - - // - // Wait for the last word write to complete or an error to be reported. - // - while(HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) - { - // - // Still working. - // - } - } - - // - // Return the final write status. - // - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -//! Locks a password-protected EEPROM block. -//! -//! \param ui32Block is the EEPROM block number which is to be locked. -//! -//! This function locks an EEPROM block that has previously been protected by -//! writing a password. Access to the block once it is locked is determined -//! by the protection settings applied via a previous call to the -//! EEPROMBlockProtectSet() function. If no password has previously been set -//! for the block, this function has no effect. -//! -//! Locking block 0 has the effect of making all other blocks in the EEPROM -//! inaccessible. -//! -//! \return Returns the lock state for the block on exit, 1 if unlocked (as -//! would be the case if no password was set) or 0 if locked. -//! -//***************************************************************************** -uint32_t -EEPROMBlockLock(uint32_t ui32Block) -{ - // - // Check parameters in a debug build. - // - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Select the block we are going to lock. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Lock the block. - // - HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; - - // - // Return the current lock state. - // - return(HWREG(EEPROM_EEUNLOCK)); -} - -//***************************************************************************** -// -//! Unlocks a password-protected EEPROM block. -//! -//! \param ui32Block is the EEPROM block number which is to be unlocked. -//! \param pui32Password points to an array of uint32_t values containing -//! the password for the block. Each element must match the password -//! originally set via a call to EEPROMBlockPasswordSet(). -//! \param ui32Count provides the number of elements in the \e pui32Password -//! array and must match the value originally passed to -//! EEPROMBlockPasswordSet(). Valid values are 1, 2 and 3. -//! -//! This function unlocks an EEPROM block that has previously been protected by -//! writing a password. Access to the block once it is unlocked is determined -//! by the protection settings applied via a previous call to the -//! EEPROMBlockProtectSet() function. -//! -//! To successfully unlock an EEPROM block, the password provided must match -//! the password provided on the original call to EEPROMBlockPasswordSet(). If -//! an incorrect password is provided, the block remains locked. -//! -//! Unlocking block 0 has the effect of making all other blocks in the device -//! accessible according to their own access protection settings. When block -//! 0 is locked, all other EEPROM blocks are inaccessible. -//! -//! \return Returns the lock state for the block on exit, 1 if unlocked or 0 if -//! locked. -//! -//***************************************************************************** -uint32_t -EEPROMBlockUnlock(uint32_t ui32Block, uint32_t *pui32Password, - uint32_t ui32Count) -{ - // - // Check parameters in a debug build. - // - ASSERT(pui32Password); - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - ASSERT(ui32Count <= 3); - - // - // Set the block that we are trying to unlock. - // - HWREG(EEPROM_EEBLOCK) = ui32Block; - - // - // Write the unlock register with 0xFFFFFFFF to reset the unlock - // sequence just in case a short password was previously used to try to - // unlock the block. - // - HWREG(EEPROM_EEUNLOCK) = 0xFFFFFFFF; - - // - // We need to write the password words in the opposite order when unlocking - // compared to locking so start at the end of the array. - // - pui32Password += (ui32Count - 1); - - // - // Write the supplied password to unlock the block. - // - while(ui32Count) - { - HWREG(EEPROM_EEUNLOCK) = *pui32Password--; - ui32Count--; - } - - // - // Let the caller know if their password worked. - // - return(HWREG(EEPROM_EEUNLOCK)); -} - -//***************************************************************************** -// -//! Hides an EEPROM block until the next reset. -//! -//! \param ui32Block is the EEPROM block number which is to be hidden. -//! -//! This function hides an EEPROM block other than block 0. Once hidden, a -//! block is completely inaccessible until the next reset. This mechanism -//! allows initialization code to have access to data which is to be hidden -//! from the rest of the application. Unlike applications using passwords, an -//! application making using of block hiding need not contain any embedded -//! passwords which could be found through disassembly. -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMBlockHide(uint32_t ui32Block) -{ - // - // Check parameters in a debug build. - // - ASSERT(!ui32Block); - ASSERT(ui32Block < BLOCKS_FROM_EESIZE(HWREG(EEPROM_EESIZE))); - - // - // Hide the requested block. - // - HWREG(EEPROM_EEHIDE) = (1 << ui32Block); -} - -//***************************************************************************** -// -//! Enables the EEPROM interrupt. -//! -//! \param ui32IntFlags indicates which EEPROM interrupt source to enable. -//! This must be \b EEPROM_INT_PROGRAM currently. -//! -//! This function enables the EEPROM interrupt. When enabled, an interrupt -//! is generated when any EEPROM write or erase operation completes. The -//! EEPROM peripheral shares a single interrupt vector with the flash memory -//! subsystem, \b INT_FLASH. This function is provided as a convenience but -//! the EEPROM interrupt can also be enabled using a call to FlashIntEnable() -//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter. -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMIntEnable(uint32_t ui32IntFlags) -{ - // - // Look for valid interrupt sources. - // - ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM); - - // - // Enable interrupts from the EEPROM module. - // - HWREG(EEPROM_EEINT) |= EEPROM_EEINT_INT; - - // - // Enable the EEPROM interrupt in the flash controller module. - // - HWREG(FLASH_FCIM) |= FLASH_FCRIS_ERIS; -} - -//***************************************************************************** -// -//! Disables the EEPROM interrupt. -//! -//! \param ui32IntFlags indicates which EEPROM interrupt source to disable. -//! This must be \b EEPROM_INT_PROGRAM currently. -//! -//! This function disables the EEPROM interrupt and prevents calls to the -//! interrupt vector when any EEPROM write or erase operation completes. The -//! EEPROM peripheral shares a single interrupt vector with the flash memory -//! subsystem, \b INT_FLASH. This function is provided as a convenience but -//! the EEPROM interrupt can also be disabled using a call to FlashIntDisable() -//! passing FLASH_INT_EEPROM in the \e ui32IntFlags parameter. -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMIntDisable(uint32_t ui32IntFlags) -{ - // - // Look for valid interrupt sources. - // - ASSERT(ui32IntFlags == EEPROM_INT_PROGRAM); - - // - // Disable the EEPROM interrupt in the flash controller module. - // - HWREG(FLASH_FCIM) &= ~FLASH_FCIM_EMASK; - - // - // Disable interrupts from the EEPROM module. - // - HWREG(EEPROM_EEINT) &= ~EEPROM_EEINT_INT; -} - -//***************************************************************************** -// -//! Reports the state of the EEPROM interrupt. -//! -//! \param bMasked determines whether the masked or unmasked state of the -//! interrupt is to be returned. If bMasked is \b true, the masked state is -//! returned, otherwise the unmasked state is returned. -//! -//! This function allows an application to query the state of the EEPROM -//! interrupt. If active, the interrupt may be cleared by calling -//! EEPROMIntClear(). -//! -//! \return Returns \b EEPROM_INT_PROGRAM if an interrupt is being signaled or -//! 0 otherwise. -// -//***************************************************************************** -uint32_t -EEPROMIntStatus(bool bMasked) -{ - if(bMasked) - { - // - // If asked for the masked interrupt status, we check to see if the - // relevant interrupt is pending in the flash controller then return - // the appropriate EEPROM flag if it is. - // - return((HWREG(FLASH_FCMISC) & FLASH_FCMISC_EMISC) ? - EEPROM_INT_PROGRAM : 0); - } - else - { - // - // If asked for the unmasked interrupt status, infer that an interrupt - // is pending if the WORKING bit of the EEDONE register is clear. The - // actual interrupt fires on the high to low transition of this bit - // but we don't have access to an unmasked interrupt status for the - // EEPROM because it's handled via the flash controller so we have to - // make do with this instead. - // - return((HWREG(EEPROM_EEDONE) & EEPROM_EEDONE_WORKING) ? - 0 : EEPROM_INT_PROGRAM); - } -} - -//***************************************************************************** -// -//! Clears the EEPROM interrupt. -//! -//! \param ui32IntFlags indicates which interrupt sources to clear. Currently, -//! the only valid value is \b EEPROM_INT_PROGRAM. -//! -//! This function allows an application to clear the EEPROM interrupt. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -//! -//***************************************************************************** -void -EEPROMIntClear(uint32_t ui32IntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_EMISC; - - // - // Clear the sector protection bits to prevent possible problems when - // programming the main flash array later. - // - if(CLASS_IS_TM4C123 && REVISION_IS_A0) - { - _EEPROMSectorMaskClear(); - } -} - -//***************************************************************************** -// -//! Returns status on the last EEPROM program or erase operation. -//! -//! This function returns the current status of the last program or erase -//! operation performed by the EEPROM. It is intended to provide error -//! information to applications programming or setting EEPROM protection -//! options under interrupt control. -//! -//! \return Returns 0 if the last program or erase operation completed without -//! any errors. If an operation is ongoing or an error occurred, the return -//! value is a logical OR combination of \b EEPROM_RC_WRBUSY, \b -//! EEPROM_RC_NOPERM, \b EEPROM_RC_WKCOPY, \b EEPROM_RC_WKERASE, and \b -//! EEPROM_RC_WORKING. -//! -//***************************************************************************** -uint32_t -EEPROMStatusGet(void) -{ - return(HWREG(EEPROM_EEDONE)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.h b/bsp/tm4c129x-dk/libraries/driverlib/eeprom.h deleted file mode 100644 index 0336010e06..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/eeprom.h +++ /dev/null @@ -1,284 +0,0 @@ -//***************************************************************************** -// -// eeprom.h - Prototypes for the EEPROM driver. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_EEPROM_H__ -#define __DRIVERLIB_EEPROM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup eeprom_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Values returned by EEPROMInit. -// -//***************************************************************************** - -// -//! This value may be returned from a call to EEPROMInit(). It indicates that -//! no previous write operations were interrupted by a reset event and that the -//! EEPROM peripheral is ready for use. -// -#define EEPROM_INIT_OK 0 - -// -//! This value may be returned from a call to EEPROMInit(). It indicates that -//! a previous data or protection write operation was interrupted by a reset -//! event and that the EEPROM peripheral was unable to clean up after the -//! problem. This situation may be resolved with another reset or may be fatal -//! depending upon the cause of the problem. For example, if the voltage to -//! the part is unstable, retrying once the voltage has stabilized may clear -//! the error. -// -#define EEPROM_INIT_ERROR 2 - -//***************************************************************************** -// -// Error indicators returned by various EEPROM API calls. These will be ORed -// together into the final return code. -// -//***************************************************************************** - -// -//! This return code bit indicates that an attempt was made to read from -//! the EEPROM while a write operation was in progress. -// -#define EEPROM_RC_WRBUSY 0x00000020 - -// -//! This return code bit indicates that an attempt was made to write a -//! value but the destination permissions disallow write operations. This -//! may be due to the destination block being locked, access protection set -//! to prohibit writes or an attempt to write a password when one is already -//! written. -// -#define EEPROM_RC_NOPERM 0x00000010 - -// -//! This return code bit indicates that the EEPROM programming state machine -//! is currently copying to or from the internal copy buffer to make room for -//! a newly written value. It is provided as a status indicator and does not -//! indicate an error. -// -#define EEPROM_RC_WKCOPY 0x00000008 - -// -//! This return code bit indicates that the EEPROM programming state machine -//! is currently erasing the internal copy buffer. It is provided as a -//! status indicator and does not indicate an error. -// -#define EEPROM_RC_WKERASE 0x00000004 - -// -//! This return code bit indicates that the EEPROM programming state machine -//! is currently working. No new write operations should be attempted until -//! this bit is clear. -// -#define EEPROM_RC_WORKING 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect -// parameter, and returned by EEPROMBlockProtectGet(). -// -//***************************************************************************** - -// -//! This bit may be ORed with the protection option passed to -//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It -//! restricts EEPROM access to threads running in supervisor mode and prevents -//! access to an EEPROM block when the CPU is in user mode. -// -#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008 - -// -//! This value may be passed to EEPROMBlockProtectSet() or returned from -//! EEPROMBlockProtectGet(). It indicates that the block should offer -//! read/write access when no password is set or when a password is set and -//! the block is unlocked, and read-only access when a password is set but -//! the block is locked. -// -#define EEPROM_PROT_RW_LRO_URW 0x00000000 - -// -//! This value may be passed to EEPROMBlockProtectSet() or returned from -//! EEPROMBlockProtectGet(). It indicates that the block should offer neither -//! read nor write access unless it is protected by a password and unlocked. -// -#define EEPROM_PROT_NA_LNA_URW 0x00000001 - -// -//! This value may be passed to EEPROMBlockProtectSet() or returned from -//! EEPROMBlockProtectGet(). It indicates that the block should offer -//! read-only access when no password is set or when a password is set and the -//! block is unlocked. When a password is set and the block is locked, neither -//! read nor write access is permitted. -// -#define EEPROM_PROT_RO_LNA_URO 0x00000002 - -//***************************************************************************** -// -//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is -//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being -//! signaled. -// -//***************************************************************************** -#define EEPROM_INT_PROGRAM 0x00000004 - -//***************************************************************************** -// -//! Returns the EEPROM block number containing a given offset address. -//! -//! \param ui32Addr is the linear, byte address of the EEPROM location whose -//! block number is to be returned. This is a zero-based offset from the start -//! of the EEPROM storage. -//! -//! This macro may be used to translate an EEPROM address offset into a -//! block number suitable for use in any of the driver's block protection -//! functions. The address provided is expressed as a byte offset from the -//! base of the EEPROM. -//! -//! \return Returns the zero-based block number which contains the passed -//! address. -// -//***************************************************************************** -#define EEPROMBlockFromAddr(ui32Addr) ((ui32Addr) >> 6) - -//***************************************************************************** -// -//! Returns the offset address of the first word in an EEPROM block. -//! -//! \param ui32Block is the index of the EEPROM block whose first word address -//! is to be returned. -//! -//! This macro may be used to determine the address of the first word in a -//! given EEPROM block. The address returned is expressed as a byte offset -//! from the base of EEPROM storage. -//! -//! \return Returns the address of the first word in the given EEPROM block. -// -//***************************************************************************** -#define EEPROMAddrFromBlock(ui32Block) ((ui32Block) << 6) - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern uint32_t EEPROMInit(void); -extern uint32_t EEPROMSizeGet(void); -extern uint32_t EEPROMBlockCountGet(void); -extern void EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address, - uint32_t ui32Count); -extern uint32_t EEPROMProgram(uint32_t *pui32Data, - uint32_t ui32Address, - uint32_t ui32Count); -extern uint32_t EEPROMProgramNonBlocking(uint32_t ui32Data, - uint32_t ui32Address); -extern uint32_t EEPROMStatusGet(void); -extern uint32_t EEPROMMassErase(void); -extern uint32_t EEPROMBlockProtectGet(uint32_t ui32Block); -extern uint32_t EEPROMBlockProtectSet(uint32_t ui32Block, - uint32_t ui32Protect); -extern uint32_t EEPROMBlockPasswordSet(uint32_t ui32Block, - uint32_t *pui32Password, - uint32_t ui32Count); -extern uint32_t EEPROMBlockLock(uint32_t ui32Block); -extern uint32_t EEPROMBlockUnlock(uint32_t ui32Block, - uint32_t *pui32Password, - uint32_t ui32Count); -extern void EEPROMBlockHide(uint32_t ui32Block); -extern void EEPROMIntEnable(uint32_t ui32IntFlags); -extern void EEPROMIntDisable(uint32_t ui32IntFlags); -extern uint32_t EEPROMIntStatus(bool bMasked); -extern void EEPROMIntClear(uint32_t ui32IntFlags); - -#ifndef DEPRECATED -//***************************************************************************** -// -// The following definitions appeared in previous revisions of this file -// but have been deprecated and should not be used by applications. -// -//***************************************************************************** - -// -// This value used to be one of those which could be returned from a call to -// EEPROMInit(). It transpires that it is was incorrect and has been removed -// after EEPROMInit() was reworked for TivaWare 2.1. -// -#define EEPROM_INIT_RETRY 1 - -// -// This return code is not available from any Tiva part and has been removed. -// -#define EEPROM_RC_INVPL 0x00000100 - -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_EEPROM_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/emac.c b/bsp/tm4c129x-dk/libraries/driverlib/emac.c deleted file mode 100644 index 8c238d299e..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/emac.c +++ /dev/null @@ -1,4983 +0,0 @@ -//***************************************************************************** -// -// emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class -// Tiva devices. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup emac_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_emac.h" -#include "driverlib/debug.h" -#include "driverlib/emac.h" -#include "driverlib/sysctl.h" -#include "driverlib/interrupt.h" -#include "driverlib/sw_crc.h" - -//***************************************************************************** -// -// Combined defines used in parameter validity checks. -// -//***************************************************************************** - -//***************************************************************************** -// -// Combined valid configuration flags. -// -//***************************************************************************** -#define VALID_CONFIG_FLAGS (EMAC_CONFIG_USE_MACADDR1 | \ - EMAC_CONFIG_SA_INSERT | \ - EMAC_CONFIG_SA_REPLACE | \ - EMAC_CONFIG_2K_PACKETS | \ - EMAC_CONFIG_STRIP_CRC | \ - EMAC_CONFIG_JABBER_DISABLE | \ - EMAC_CONFIG_JUMBO_ENABLE | \ - EMAC_CONFIG_IF_GAP_MASK | \ - EMAC_CONFIG_CS_DISABLE | \ - EMAC_CONFIG_100MBPS | \ - EMAC_CONFIG_RX_OWN_DISABLE | \ - EMAC_CONFIG_LOOPBACK | \ - EMAC_CONFIG_FULL_DUPLEX | \ - EMAC_CONFIG_CHECKSUM_OFFLOAD | \ - EMAC_CONFIG_RETRY_DISABLE | \ - EMAC_CONFIG_AUTO_CRC_STRIPPING | \ - EMAC_CONFIG_BO_MASK | \ - EMAC_CONFIG_DEFERRAL_CHK_ENABLE | \ - EMAC_CONFIG_PREAMBLE_MASK) - -//***************************************************************************** -// -// Combined valid frame filter flags. -// -//***************************************************************************** -#define VALID_FRMFILTER_FLAGS (EMAC_FRMFILTER_RX_ALL | \ - EMAC_FRMFILTER_VLAN | \ - EMAC_FRMFILTER_HASH_AND_PERFECT | \ - EMAC_FRMFILTER_SADDR | \ - EMAC_FRMFILTER_INV_SADDR | \ - EMAC_FRMFILTER_PASS_NO_PAUSE | \ - EMAC_FRMFILTER_PASS_ALL_CTRL | \ - EMAC_FRMFILTER_PASS_ADDR_CTRL | \ - EMAC_FRMFILTER_BROADCAST | \ - EMAC_FRMFILTER_PASS_MULTICAST | \ - EMAC_FRMFILTER_INV_DADDR | \ - EMAC_FRMFILTER_HASH_MULTICAST | \ - EMAC_FRMFILTER_HASH_UNICAST | \ - EMAC_FRMFILTER_PROMISCUOUS) - -//***************************************************************************** -// -// Combined valid maskable interrupts. -// -//***************************************************************************** -#define EMAC_MASKABLE_INTS (EMAC_INT_EARLY_RECEIVE | \ - EMAC_INT_BUS_ERROR | \ - EMAC_INT_EARLY_TRANSMIT | \ - EMAC_INT_RX_WATCHDOG | \ - EMAC_INT_RX_STOPPED | \ - EMAC_INT_RX_NO_BUFFER | \ - EMAC_INT_RECEIVE | \ - EMAC_INT_TX_UNDERFLOW | \ - EMAC_INT_RX_OVERFLOW | \ - EMAC_INT_TX_JABBER | \ - EMAC_INT_TX_NO_BUFFER | \ - EMAC_INT_TX_STOPPED | \ - EMAC_INT_TRANSMIT | \ - EMAC_INT_NORMAL_INT | \ - EMAC_INT_ABNORMAL_INT | \ - EMAC_INT_PHY) - -//***************************************************************************** -// -// Combined valid normal interrupts. -// -//***************************************************************************** -#define EMAC_NORMAL_INTS (EMAC_INT_TRANSMIT | \ - EMAC_INT_RECEIVE | \ - EMAC_INT_EARLY_RECEIVE | \ - EMAC_INT_TX_NO_BUFFER) - -//***************************************************************************** -// -// Combined valid abnormal interrupts. -// -//***************************************************************************** -#define EMAC_ABNORMAL_INTS (EMAC_INT_TX_STOPPED | \ - EMAC_INT_TX_JABBER | \ - EMAC_INT_RX_OVERFLOW | \ - EMAC_INT_TX_UNDERFLOW | \ - EMAC_INT_RX_NO_BUFFER | \ - EMAC_INT_RX_STOPPED | \ - EMAC_INT_RX_WATCHDOG | \ - EMAC_INT_EARLY_TRANSMIT | \ - EMAC_INT_BUS_ERROR) - -//***************************************************************************** -// -// Interrupt sources reported via the DMARIS register but which are not -// masked (or enabled) via the DMAIM register. -// -//***************************************************************************** -#define EMAC_NON_MASKED_INTS (EMAC_DMARIS_LPI | \ - EMAC_DMARIS_TT | \ - EMAC_DMARIS_PMT | \ - EMAC_DMARIS_MMC) - -//***************************************************************************** -// -// The number of MAC addresses the module can store for filtering purposes. -// -//***************************************************************************** -#define NUM_MAC_ADDR 4 - -//***************************************************************************** -// -// Macros aiding access to the MAC address registers. -// -//***************************************************************************** -#define MAC_ADDR_OFFSET (EMAC_O_ADDR1L - EMAC_O_ADDR0L) -#define EMAC_O_ADDRL(n) (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n))) -#define EMAC_O_ADDRH(n) (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n))) - -//***************************************************************************** -// -// A structure used to help in choosing the correct clock divisor for the MII -// based on the current system clock rate. -// -//***************************************************************************** -static const struct -{ - uint32_t ui32SysClockMax; - uint32_t ui32Divisor; -} -g_pi16MIIClockDiv[] = -{ - { 64000000, EMAC_MIIADDR_CR_35_60 }, - { 104000000, EMAC_MIIADDR_CR_60_100 }, - { 150000000, EMAC_MIIADDR_CR_100_150 } -}; - -//***************************************************************************** -// -// The number of clock divisors in the above table. -// -//***************************************************************************** -#define NUM_CLOCK_DIVISORS (sizeof(g_pi16MIIClockDiv) / \ - sizeof(g_pi16MIIClockDiv[0])) - -//***************************************************************************** -// -// The define for accessing PHY registers in the MMD address space. -// -//***************************************************************************** -#define DEV_ADDR(x) ((x & 0xF000) >> 12) -#define REG_ADDR(x) ((x & 0x0FFF)) - -//***************************************************************************** -// -//! Initializes the Ethernet MAC and sets bus-related DMA parameters. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32SysClk is the current system clock frequency in Hertz. -//! \param ui32BusConfig defines the bus operating mode for the Ethernet MAC -//! DMA controller. -//! \param ui32RxBurst is the maximum receive burst size in words. -//! \param ui32TxBurst is the maximum transmit burst size in words. -//! \param ui32DescSkipSize is the number of 32-bit words to skip between -//! two unchained DMA descriptors. Values in the range 0 to 31 are valid. -//! -//! This function sets bus-related parameters for the Ethernet MAC DMA -//! engines. It must be called after EMACPHYConfigSet() and called again -//! after any subsequent call to EMACPHYConfigSet(). -//! -//! The \e ui32BusConfig parameter is the logical OR of various fields. The -//! first sets the DMA channel priority weight: -//! -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 -//! - \b EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 -//! -//! The second field sets the receive and transmit priorities used when -//! arbitrating between the Rx and Tx DMA. The priorities are Rx:Tx unless -//! \b EMAC_BCONFIG_TX_PRIORITY is also specified, in which case they become -//! Tx:Rx. The priority provided here is ignored if -//! \b EMAC_BCONFIG_PRIORITY_FIXED is specified. -//! -//! - \b EMAC_BCONFIG_PRIORITY_1_1 -//! - \b EMAC_BCONFIG_PRIORITY_2_1 -//! - \b EMAC_BCONFIG_PRIORITY_3_1 -//! - \b EMAC_BCONFIG_PRIORITY_4_1 -//! -//! The following additional flags may also be defined: -//! -//! - \b EMAC_BCONFIG_TX_PRIORITY indicates that the transmit DMA should be -//! higher priority in all arbitration for the system-side bus. If this is not -//! defined, the receive DMA has higher priority. -//! - \b EMAC_BCONFIG_ADDR_ALIGNED works in tandem with -//! \b EMAC_BCONFIG_FIXED_BURST to control address alignment of AHB bursts. -//! When both flags are specified, all bursts are aligned to the start address -//! least significant bits. If \b EMAC_BCONFIG_FIXED_BURST is not specified, -//! the first burst is unaligned but subsequent bursts are aligned to the -//! address. -//! - \b EMAC_BCONFIG_ALT_DESCRIPTORS indicates that the DMA engine should -//! use the alternate descriptor format as defined in type -//! \b tEMACDMADescriptor. If absent, the basic descriptor type is used. -//! Alternate descriptors are required if using IEEE 1588-2008 advanced -//! timestamping, VLAN or TCP/UDP/ICMP CRC insertion features. Note that, -//! for clarity, emac.h does not contain type definitions for the basic -//! descriptor type. Please see the part datasheet for information on basic -//! descriptor structures. -//! - \b EMAC_BCONFIG_PRIORITY_FIXED indicates that a fixed priority scheme -//! should be employed when arbitrating between the transmit and receive DMA -//! for system-side bus access. In this case, the receive channel always has -//! priority unless \b EMAC_BCONFIG_TX_PRIORITY is set, in which case the -//! transmit channel has priority. If \b EMAC_BCONFIG_PRIORITY_FIXED is not -//! specified, a weighted round-robin arbitration scheme is used with the -//! weighting defined using \b EMAC_BCONFIG_PRIORITY_1_1, -//! \b EMAC_BCONFIG_PRIORITY_2_1, \b EMAC_BCONFIG_PRIORITY_3_1 or -//! \b EMAC_BCONFIG_PRIORITY_4_1, and \b EMAC_BCONFIG_TX_PRIORITY. -//! - \b EMAC_BCONFIG_FIXED_BURST indicates that fixed burst transfers should -//! be used. -//! - \b EMAC_BCONFIG_MIXED_BURST indicates that the DMA engine should use -//! mixed burst types depending on the length of data to be transferred -//! across the system bus. -//! -//! The \e ui32RxBurst and \e ui32TxBurst parameters indicate the maximum -//! number of words that the relevant DMA should transfer in a single -//! transaction. Valid values are 1, 2, 4, 8, 16 and 32. Any other value -//! results in undefined behavior. -//! -//! The \e ui32DescSkipSize parameter is used when the descriptor lists are -//! using ring mode (where descriptors are contiguous in memory with the last -//! descriptor marked with the \b END_OF_RING flag) rather than chained mode -//! (where each descriptor includes a field that points to the next descriptor -//! in the list). In ring mode, the hardware uses the \e ui32DescSkipSize to -//! skip past any application-defined fields after the end of the hardware- -//! defined descriptor fields. The parameter value indicates the number of -//! 32-bit words to skip after the last field of the hardware-defined -//! descriptor to get to the first field of the next descriptor. When using -//! arrays of either the \b tEMACDMADescriptor or \b tEMACAltDMADescriptor -//! types defined for this driver, \e ui32DescSkipSize must be set to 1 to skip -//! the \e pvNext pointer added to the end of each of these structures. -//! Applications may modify these structure definitions to include their own -//! application-specific data and modify \e ui32DescSkipSize appropriately if -//! desired. -//! -//! \return None. -// -//***************************************************************************** -void -EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig, - uint32_t ui32RxBurst, uint32_t ui32TxBurst, uint32_t ui32DescSkipSize) -{ - uint32_t ui32Val, ui32Div; - - // - // Parameter sanity checks. - // - ASSERT(ui32DescSkipSize < 32); - ASSERT(ui32TxBurst < (32 * 8)); - ASSERT(ui32RxBurst < (32 * 8)); - - // - // Make sure that the DMA software reset is clear before continuing. - // - while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR) - { - } - - // - // Set common flags. Note that this driver assumes we are always using - // 8 word descriptors so we need to OR in EMAC_DMABUSMOD_ATDS here. - // - ui32Val = (ui32BusConfig | (ui32DescSkipSize << EMAC_DMABUSMOD_DSL_S) | - EMAC_DMABUSMOD_ATDS); - - // - // Do we need to use the 8X burst length multiplier? - // - if((ui32TxBurst > 32) || (ui32RxBurst > 32)) - { - // - // Divide both burst lengths by 8 and set the 8X burst length - // multiplier. - // - ui32Val |= EMAC_DMABUSMOD_8XPBL; - ui32TxBurst >>= 3; - ui32RxBurst >>= 3; - - // - // Sanity check - neither burst length should have become zero. If - // they did, this indicates that the values passed are invalid. - // - ASSERT(ui32RxBurst); - ASSERT(ui32TxBurst); - } - - // - // Are the receive and transmit burst lengths the same? - // - if(ui32RxBurst == ui32TxBurst) - { - // - // Yes - set up to use a single burst length. - // - ui32Val |= (ui32TxBurst << EMAC_DMABUSMOD_PBL_S); - } - else - { - // - // No - we need to use separate burst lengths for each. - // - ui32Val |= (EMAC_DMABUSMOD_USP | - (ui32TxBurst << EMAC_DMABUSMOD_PBL_S) | - (ui32RxBurst << EMAC_DMABUSMOD_RPBL_S)); - } - - // - // Finally, write the bus mode register. - // - HWREG(ui32Base + EMAC_O_DMABUSMOD) = ui32Val; - - // - // Default the MII CSR clock divider based on the fastest system clock. - // - ui32Div = g_pi16MIIClockDiv[NUM_CLOCK_DIVISORS - 1].ui32Divisor; - - // - // Find the MII CSR clock divider to use based on the current system clock. - // - for(ui32Val = 0; ui32Val < NUM_CLOCK_DIVISORS; ui32Val++) - { - if(ui32SysClk <= g_pi16MIIClockDiv[ui32Val].ui32SysClockMax) - { - ui32Div = g_pi16MIIClockDiv[ui32Val].ui32Divisor; - break; - } - } - - // - // Set the MII CSR clock speed. - // - HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & - ~EMAC_MIIADDR_CR_M) | ui32Div); - - // - // Disable all the MMC interrupts as these are enabled by default at reset. - // - HWREG(ui32Base + EMAC_O_MMCRXIM) = 0xFFFFFFFF; - HWREG(ui32Base + EMAC_O_MMCTXIM) = 0xFFFFFFFF; -} - -//***************************************************************************** -// -//! Resets the Ethernet MAC. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function performs a reset of the Ethernet MAC by resetting all logic -//! and returning all registers to their default values. The function returns -//! only after the hardware indicates that the reset has completed. -//! -//! \note To ensure that the reset completes, the selected PHY clock must be -//! enabled when this function is called. If the PHY clock is absent, this -//! function does not return. -//! -//! \return None. -// -//***************************************************************************** -void -EMACReset(uint32_t ui32Base) -{ - // - // Reset the Ethernet MAC. - // - HWREG(ui32Base + EMAC_O_DMABUSMOD) |= EMAC_DMABUSMOD_SWR; - - // - // Wait for the reset to complete. - // - while(HWREG(ui32Base + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR) - { - } -} - -//***************************************************************************** -// -//! Selects the Ethernet PHY in use. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32Config selects the PHY in use and, when using the internal -//! PHY, allows various various PHY parameters to be configured. -//! -//! This function must be called prior to EMACInit() and EMACConfigSet() to -//! select the Ethernet PHY to be used. If the internal PHY is selected, the -//! function also allows configuration of various PHY parameters. Note that -//! the Ethernet MAC is reset during this function call because parameters used -//! by this function are latched by the hardware only on a MAC reset. The call -//! sequence to select and configure the PHY, therefore, must be as follows: -//! -//! \verbatim -//! // Enable and reset the MAC. -//! SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); -//! SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); -//! if() -//! { -//! // Enable and reset the internal PHY. -//! SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); -//! SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); -//! } -//! -//! // Ensure the MAC is completed its reset. -//! while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0)) -//! { -//! } -//! -//! // Set the PHY type and configuration options. -//! EMACPHYConfigSet(EMAC0_BASE, ); -//! -//! // Initialize and configure the MAC. -//! EMACInit(EMAC0_BASE, , , -//! , , ); -//! EMACConfigSet(EMAC0_BASE, ); -//! \endverbatim -//! -//! The \e ui32Config parameter must specify one of the following values: -//! -//! - \b EMAC_PHY_TYPE_INTERNAL selects the internal Ethernet PHY. -//! - \b EMAC_PHY_TYPE_EXTERNAL_MII selects an external PHY connected via the -//! MII interface. -//! - \b EMAC_PHY_TYPE_EXTERNAL_RMII selects an external PHY connected via the -//! RMII interface. -//! -//! If \b EMAC_PHY_TYPE_INTERNAL is selected, the following flags may be ORed -//! into \e ui32Config to control various PHY features and modes. These flags -//! are ignored if an external PHY is selected. -//! -//! - \b EMAC_PHY_INT_NIB_TXERR_DET_DIS disables odd nibble transmit error -//! detection (sets the default value of PHY register MR10, bit 1). -//! - \b EMAC_PHY_INT_RX_ER_DURING_IDLE enables receive error detection during -//! idle (sets the default value of PHY register MR10, bit 2). -//! - \b EMAC_PHY_INT_ISOLATE_MII_LLOSS ties the MII outputs low if no link is -//! established in 100B-T and full duplex modes (sets the default value of PHY -//! register MR10, bit 3). -//! - \b EMAC_PHY_INT_LINK_LOSS_RECOVERY enables link loss recovery (sets the -//! default value of PHY register MR9, bit 7). -//! - \b EMAC_PHY_INT_TDRRUN enables execution of the TDR procedure after a link -//! down event (sets the default value of PHY register MR9, bit 8). -//! - \b EMAC_PHY_INT_LD_ON_RX_ERR_COUNT enables link down if the receiver -//! error count reaches 32 within a 10-us interval (sets the default value of -//! PHY register MR11 bit 3). -//! - \b EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT enables link down if the MTL3 error -//! count reaches 20 in a 10 us-interval (sets the default value of PHY register -//! MR11 bit 2). -//! - \b EMAC_PHY_INT_LD_ON_LOW_SNR enables link down if the low SNR threshold -//! is crossed 20 times in a 10 us-interval (sets the default value of PHY -//! register MR11 bit 1). -//! - \b EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY enables link down if energy detector -//! indicates Energy Loss (sets the default value of PHY register MR11 bit 0). -//! - \b EMAC_PHY_INT_POLARITY_SWAP inverts the polarity on both TPTD and TPRD -//! pairs (sets the default value of PHY register MR11 bit 5). -//! - \b EMAC_PHY_INT_MDI_SWAP swaps the MDI pairs putting receive on the TPTD -//! pair and transmit on TPRD (sets the default value of PHY register MR11 bit -//! 6). -//! - \b EMAC_PHY_INT_ROBUST_MDIX enables robust auto MDI-X resolution (sets the -//! default value of PHY register MR9 bit 5). -//! - \b EMAC_PHY_INT_FAST_MDIX enables fast auto-MDI/MDIX resolution (sets the -//! default value of PHY register MR9 bit 6). -//! - \b EMAC_PHY_INT_MDIX_EN enables auto-MDI/MDIX crossover (sets the -//! default value of PHY register MR9 bit 14). -//! - \b EMAC_PHY_INT_FAST_RXDV_DETECT enables fast RXDV detection (set the -//! default value of PHY register MR9 bit 1). -//! - \b EMAC_PHY_INT_FAST_L_UP_DETECT enables fast link-up time during parallel -//! detection (sets the default value of PHY register MR10 bit 6) -//! - \b EMAC_PHY_INT_EXT_FULL_DUPLEX forces full-duplex while working with a -//! link partner in forced 100B-TX (sets the default value of PHY register -//! MR10 bit 5). -//! - \b EMAC_PHY_INT_FAST_AN_80_50_35 enables fast auto-negotiation using -//! break link, link fail inhibit and wait timers set to 80, 50 and 35 -//! respectively (sets the default value of PHY register MR9 bits [4:2] to -//! 3b100). -//! - \b EMAC_PHY_INT_FAST_AN_120_75_50 enables fast auto-negotiation using -//! break link, link fail inhibit and wait timers set to 120, 75 and 50 -//! respectively (sets the default value of PHY register MR9 bits [4:2] to -//! 3b101). -//! - \b EMAC_PHY_INT_FAST_AN_140_150_100 enables fast auto-negotiation using -//! break link, link fail inhibit and wait timers set to 140, 150 and 100 -//! respectively (sets the default value of PHY register MR9 bits [4:2] to -//! 3b110). -//! - \b EMAC_PHY_FORCE_10B_T_HALF_DUPLEX disables auto-negotiation and forces -//! operation in 10Base-T, half duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b000). -//! - \b EMAC_PHY_FORCE_10B_T_FULL_DUPLEX disables auto-negotiation and forces -//! operation in 10Base-T, full duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b001). -//! - \b EMAC_PHY_FORCE_100B_T_HALF_DUPLEX disables auto-negotiation and forces -//! operation in 100Base-T, half duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b010). -//! - \b EMAC_PHY_FORCE_100B_T_FULL_DUPLEX disables auto-negotiation and forces -//! operation in 100Base-T, full duplex mode (sets the default value of PHY -//! register MR9 bits [13:11] to 3b011). -//! - \b EMAC_PHY_AN_10B_T_HALF_DUPLEX enables auto-negotiation and advertises -//! 10Base-T, half duplex mode (sets the default value of PHY register MR9 bits -//! [13:11] to 3b100). -//! - \b EMAC_PHY_AN_10B_T_FULL_DUPLEX enables auto-negotiation and advertises -//! 10Base-T half or full duplex modes (sets the default value of PHY register -//! MR9 bits [13:11] to 3b101). -//! - \b EMAC_PHY_AN_100B_T_HALF_DUPLEX enables auto-negotiation and advertises -//! 10Base-T half or full duplex, and 100Base-T half duplex modes (sets the -//! default value of PHY register MR9 bits [13:11] to 3b110). -//! - \b EMAC_PHY_AN_100B_T_FULL_DUPLEX enables auto-negotiation and advertises -//! 10Base-T half or full duplex, and 100Base-T half or full duplex modes (sets -//! the default value of PHY register MR9 bits [13:11] to 3b111). -//! - \b EMAC_PHY_INT_HOLD prevents the PHY from transmitting energy on the -//! line. -//! -//! As a side effect of this function, the Ethernet MAC is reset so any -//! previous MAC configuration is lost. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Write the Ethernet PHY configuration to the peripheral configuration - // register. - // - HWREG(ui32Base + EMAC_O_PC) = ui32Config; - - // - // If using the internal PHY, reset it to ensure that new configuration is - // latched there. - // - if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL) - { - SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0); - while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0)) - { - // - // Wait for the PHY reset to complete. - // - } - - // - // Delay a bit longer to ensure that the PHY reset has completed. - // - SysCtlDelay(10000); - } - - // - // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC - // Clock Configuration Register. - // - if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII) - { - // - // Select and enable the external clock from the RMII PHY. - // - HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN; - } - else - { - // - // Disable the external clock. - // - HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN; - } - - // - // Reset the MAC regardless of whether the PHY connection changed or not. - // - EMACReset(EMAC0_BASE); - - SysCtlDelay(1000); -} - -//***************************************************************************** -// -//! Configures basic Ethernet MAC operation parameters. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32Config provides various flags and values configuring the MAC. -//! \param ui32ModeFlags provides configuration relating to the transmit and -//! receive DMA engines. -//! \param ui32RxMaxFrameSize sets the maximum receive frame size above which -//! an error is reported. -//! -//! This function is called to configure basic operating parameters for the -//! MAC and its DMA engines. -//! -//! The \e ui32Config parameter is the logical OR of various fields and -//! flags. The first field determines which MAC address is used during -//! insertion or replacement for all transmitted frames. Valid options are -//! -//! - \b EMAC_CONFIG_USE_MACADDR1 and -//! - \b EMAC_CONFIG_USE_MACADDR0 -//! -//! The interframe gap between transmitted frames is controlled using one of -//! the following values: -//! -//! - \b EMAC_CONFIG_IF_GAP_96BITS -//! - \b EMAC_CONFIG_IF_GAP_88BITS -//! - \b EMAC_CONFIG_IF_GAP_80BITS -//! - \b EMAC_CONFIG_IF_GAP_72BITS -//! - \b EMAC_CONFIG_IF_GAP_64BITS -//! - \b EMAC_CONFIG_IF_GAP_56BITS -//! - \b EMAC_CONFIG_IF_GAP_48BITS -//! - \b EMAC_CONFIG_IF_GAP_40BITS -//! -//! The number of bytes of preamble added to the beginning of every transmitted -//! frame is selected using one of the following values: -//! -//! - \b EMAC_CONFIG_7BYTE_PREAMBLE -//! - \b EMAC_CONFIG_5BYTE_PREAMBLE -//! - \b EMAC_CONFIG_3BYTE_PREAMBLE -//! -//! The back-off limit determines the range of the random time that the MAC -//! delays after a collision and before attempting to retransmit a frame. One -//! of the following values must be used to select this limit. In each case, -//! the retransmission delay in terms of 512 bit time slots, is the lower of -//! (2 ** N) and a random number between 0 and the selected backoff-limit. -//! -//! - \b EMAC_CONFIG_BO_LIMIT_1024 -//! - \b EMAC_CONFIG_BO_LIMIT_256 -//! - \b EMAC_CONFIG_BO_LIMIT_16 -//! - \b EMAC_CONFIG_BO_LIMIT_2 -//! -//! Control over insertion or replacement of the source address in all -//! transmitted frames is provided by using one of the following fields: -//! -//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending -//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1 -//! was specified) to be inserted into all transmitted frames. -//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with -//! the selected address in all transmitted frames. -//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address -//! insertion or deletion to be controlled by fields in the DMA transmit -//! descriptor, allowing control on a frame-by-frame basis. -//! -//! Whether the interface attempts to operate in full- or half-duplex mode is -//! controlled by one of the following flags: -//! -//! - \b EMAC_CONFIG_FULL_DUPLEX -//! - \b EMAC_CONFIG_HALF_DUPLEX -//! -//! The following additional flags may also be specified: -//! -//! - \b EMAC_CONFIG_2K_PACKETS enables IEEE802.3as support for 2K packets. -//! When specified, the MAC considers all frames up to 2000 bytes in length as -//! normal packets. When \b EMAC_CONFIG_JUMBO_ENABLE is not specified, all -//! frames larger than 2000 bytes are treated as Giant frames. This flag is -//! ignored if \b EMAC_CONFIG_JUMBO_ENABLE is specified. -//! - \b EMAC_CONFIG_STRIP_CRC causes the 4-byte CRC of all Ethernet type -//! frames to be stripped and dropped before the frame is forwarded to the -//! application. -//! - \b EMAC_CONFIG_JABBER_DISABLE disables the jabber timer on the -//! transmitter and enables frames of up to 16384 bytes to be transmitted. If -//! this flag is absent, the MAC does not allow more than 2048 (or 10240 if -//! \b EMAC_CONFIG_JUMBO_ENABLE is specified) bytes to be sent in any one -//! frame. -//! - \b EMAC_CONFIG_JUMBO_ENABLE enables Jumbo Frames, allowing frames of -//! up to 9018 (or 9022 if using VLAN tagging) to be handled without reporting -//! giant frame errors. -//! - \b EMAC_CONFIG_100MBPS forces the MAC to communicate with the PHY using -//! 100Mbps signaling. If this option is not specified, the MAC uses 10Mbps -//! signaling. This speed setting is important when using an external RMII -//! PHY where the selected rate must match the PHY's setting which may have -//! been made as a result of auto-negotiation. When using the internal PHY -//! or an external MII PHY, the signaling rate is controlled by the PHY- -//! provided transmit and receive clocks. -//! - \b EMAC_CONFIG_CS_DISABLE disables Carrier Sense during transmission -//! when operating in half-duplex mode. -//! - \b EMAC_CONFIG_RX_OWN_DISABLE disables reception of transmitted frames -//! when operating in half-duplex mode. -//! - \b EMAC_CONFIG_LOOPBACK enables internal loopback. -//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD enables IPv4 header checksum checking -//! and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking. The results -//! of the checksum calculations are reported via status fields in the DMA -//! receive descriptors. -//! - \b EMAC_CONFIG_RETRY_DISABLE disables retransmission in cases where -//! half-duplex mode is in use and a collision occurs. This condition causes -//! the current frame to be ignored and a frame abort to be reported in the -//! transmit frame status. -//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING strips the last 4 bytes (frame check -//! sequence) from all Ether type frames before forwarding the frames to the -//! application. -//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE enables transmit deferral checking -//! in half-duplex mode. When enabled, the transmitter reports an error if it -//! is unable to transmit a frame for more than 24288 bit times (or 155680 -//! bit times in Jumbo frame mode) due to an active carrier sense signal on -//! the MII. -//! -//! The \e ui32ModeFlags parameter sets operating parameters related to the -//! internal MAC FIFOs. It comprises a logical OR of the following fields. -//! The first selects the transmit FIFO threshold. Transmission of a frame -//! begins when this amount of data or a full frame exists in the transmit -//! FIFO. This field is ignored if \b EMAC_MODE_TX_STORE_FORWARD is -//! included. One of the following must be specified: -//! -//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES -//! -//! The second field controls the receive FIFO threshold. DMA transfers of -//! received data begin either when the receive FIFO contains a full frame -//! or this number of bytes. This field is ignored if -//! \b EMAC_MODE_RX_STORE_FORWARD is included. One of the following must be -//! specified: -//! -//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES -//! -//! The following additional flags may be specified: -//! -//! - \b EMAC_MODE_KEEP_BAD_CRC causes frames with TCP/IP checksum errors -//! to be forwarded to the application if those frames do not have any errors -//! (including FCS errors) in the Ethernet framing. In these cases, the frames -//! have errors only in the payload. If this flag is not specified, all frames -//! with any detected error are discarded unless \b EMAC_MODE_RX_ERROR_FRAMES -//! is also specified. -//! - \b EMAC_MODE_RX_STORE_FORWARD causes the receive DMA to read frames -//! from the FIFO only after the complete frame has been written to it. If -//! this mode is enabled, the receive threshold is ignored. -//! - \b EMAC_MODE_RX_FLUSH_DISABLE disables the flushing of received frames -//! in cases where receive descriptors or buffers are unavailable. -//! - \b EMAC_MODE_TX_STORE_FORWARD causes the transmitter to start -//! transmitting a frame only after the whole frame has been written to the -//! transmit FIFO. If this mode is enabled, the transmit threshold is ignored. -//! - \b EMAC_MODE_RX_ERROR_FRAMES causes all frames other than runt error -//! frames to be forwarded to the receive DMA regardless of any errors detected -//! in the frames. -//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES causes undersized frames (frames -//! shorter than 64 bytes but with no errors) to the application. If this -//! option is not selected, all undersized frames are dropped by the receiver -//! unless it has already started transferring them to the receive FIFO due to -//! the receive threshold setting. -//! - \b EMAC_MODE_OPERATE_2ND_FRAME enables the transmit DMA to operate on a -//! second frame while waiting for the previous frame to be transmitted and -//! associated status and timestamps to be reported. If absent, the transmit -//! DMA works on a single frame at any one time, waiting for that frame to be -//! transmitted and its status to be received before moving on to the next -//! frame. -//! -//! The \e ui32RxMaxFrameSize parameter may be used to override the default -//! setting for the maximum number of bytes that can be received in a frame -//! before that frame is flagged as being in error. If the parameter is set -//! to 0, the default hardware settings are applied. If non-zero, any frame -//! received which is longer than the \e ui32RxMaxFrameSize, regardless of -//! whether the MAC is configured for normal or Jumbo frame operation, is -//! flagged as an error. -//! -//! \return None. -// -//***************************************************************************** -void -EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags, - uint32_t ui32RxMaxFrameSize) -{ - // - // Parameter sanity check. Note that we allow TX_ENABLED and RX_ENABLED - // here because we'll mask them off before writing the value and this - // makes back-to-back EMACConfigGet/EMACConfigSet calls work without the - // caller needing to explicitly remove these bits from the parameter. - // - ASSERT((ui32Config & ~(VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED | - EMAC_CONFIG_RX_ENABLED)) == 0); - ASSERT(!ui32RxMaxFrameSize || ((ui32RxMaxFrameSize < 0x4000) && - (ui32RxMaxFrameSize > 1522))); - - // - // Set the configuration flags as specified. Note that we unconditionally - // OR in the EMAC_CFG_PS bit here since this implementation supports only - // MII and RMII interfaces to the PHYs. - // - HWREG(ui32Base + EMAC_O_CFG) = - ((HWREG(ui32Base + EMAC_O_CFG) & ~VALID_CONFIG_FLAGS) | ui32Config | - EMAC_CFG_PS); - - // - // Set the maximum receive frame size. If 0 is passed, this implies - // that the default maximum frame size should be used so just turn off - // the override. - // - if(ui32RxMaxFrameSize) - { - HWREG(ui32Base + EMAC_O_WDOGTO) = ui32RxMaxFrameSize | EMAC_WDOGTO_PWE; - } - else - { - HWREG(ui32Base + EMAC_O_WDOGTO) &= ~EMAC_WDOGTO_PWE; - } - - // - // Set the operating mode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) = ui32ModeFlags; -} - -//***************************************************************************** -// -//! Returns the Ethernet MAC's current basic configuration parameters. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param pui32Config points to storage that is written with Ethernet MAC -//! configuration. -//! \param pui32Mode points to storage that is written with Ethernet MAC mode -//! information. -//! \param pui32RxMaxFrameSize points to storage that is written with the -//! maximum receive frame size. -//! -//! This function is called to query the basic operating parameters for the -//! MAC and its DMA engines. -//! -//! The \e pui32Config parameter is written with the logical OR of various -//! fields and flags. The first field describes which MAC address is used -//! during insertion or replacement for all transmitted frames. Valid options -//! are -//! -//! - \b EMAC_CONFIG_USE_MACADDR1 -//! - \b EMAC_CONFIG_USE_MACADDR0 -//! -//! The interframe gap between transmitted frames is given using one of the -//! following values: -//! -//! - \b EMAC_CONFIG_IF_GAP_96BITS -//! - \b EMAC_CONFIG_IF_GAP_88BITS -//! - \b EMAC_CONFIG_IF_GAP_80BITS -//! - \b EMAC_CONFIG_IF_GAP_72BITS -//! - \b EMAC_CONFIG_IF_GAP_64BITS -//! - \b EMAC_CONFIG_IF_GAP_56BITS -//! - \b EMAC_CONFIG_IF_GAP_48BITS -//! - \b EMAC_CONFIG_IF_GAP_40BITS -//! -//! The number of bytes of preamble added to the beginning of every transmitted -//! frame is described using one of the following values: -//! -//! - \b EMAC_CONFIG_7BYTE_PREAMBLE -//! - \b EMAC_CONFIG_5BYTE_PREAMBLE -//! - \b EMAC_CONFIG_3BYTE_PREAMBLE -//! -//! The back-off limit determines the range of the random time that the MAC -//! delays after a collision and before attempting to retransmit a frame. One -//! of the following values provides the currently selected limit. In each -//! case the retransmission delay in terms of 512 bit time slots, is the -//! lower of (2 ** N) and a random number between 0 and the reported -//! backoff-limit. -//! -//! - \b EMAC_CONFIG_BO_LIMIT_1024 -//! - \b EMAC_CONFIG_BO_LIMIT_256 -//! - \b EMAC_CONFIG_BO_LIMIT_16 -//! - \b EMAC_CONFIG_BO_LIMIT_2 -//! -//! Handling of insertion or replacement of the source address in all -//! transmitted frames is described by one of the following fields: -//! -//! - \b EMAC_CONFIG_SA_INSERT causes the MAC address (0 or 1 depending -//! on whether \b EMAC_CONFIG_USE_MACADDR0 or \b EMAC_CONFIG_USE_MACADDR1 -//! was specified) to be inserted into all transmitted frames. -//! - \b EMAC_CONFIG_SA_REPLACE causes the MAC address to be replaced with -//! the selected address in all transmitted frames. -//! - \b EMAC_CONFIG_SA_FROM_DESCRIPTOR causes control of source address -//! insertion or deletion to be controlled by fields in the DMA transmit -//! descriptor, allowing control on a frame-by-frame basis. -//! -//! Whether the interface attempts to operate in full- or half-duplex mode is -//! reported by one of the following flags: -//! -//! - \b EMAC_CONFIG_FULL_DUPLEX -//! - \b EMAC_CONFIG_HALF_DUPLEX -//! -//! The following additional flags may also be included: -//! -//! - \b EMAC_CONFIG_2K_PACKETS indicates that IEEE802.3as support for 2K -//! packets is enabled. When present, the MAC considers all frames up to 2000 -//! bytes in length as normal packets. When \b EMAC_CONFIG_JUMBO_ENABLE is -//! not reported, all frames larger than 2000 bytes are treated as Giant -//! frames. The value of this flag should be ignored if -//! \b EMAC_CONFIG_JUMBO_ENABLE is also reported. -//! - \b EMAC_CONFIG_STRIP_CRC indicates that the 4-byte CRC of all Ethernet -//! type frames is being stripped and dropped before the frame is forwarded to -//! the application. -//! - \b EMAC_CONFIG_JABBER_DISABLE indicates that the the jabber timer on the -//! transmitter is disabled, allowing frames of up to 16384 bytes to be -//! transmitted. If this flag is absent, the MAC does not allow more than 2048 -//! (or 10240 if \b EMAC_CONFIG_JUMBO_ENABLE is reported) bytes to be sent in -//! any one frame. -//! - \b EMAC_CONFIG_JUMBO_ENABLE indicates that Jumbo Frames of up to 9018 -//! (or 9022 if using VLAN tagging) are enabled. -//! - \b EMAC_CONFIG_CS_DISABLE indicates that Carrier Sense is disabled -//! during transmission when operating in half-duplex mode. -//! - \b EMAC_CONFIG_100MBPS indicates that the MAC is using 100Mbps -//! signaling to communicate with the PHY. -//! - \b EMAC_CONFIG_RX_OWN_DISABLE indicates that reception of transmitted -//! frames is disabled when operating in half-duplex mode. -//! - \b EMAC_CONFIG_LOOPBACK indicates that internal loopback is enabled. -//! - \b EMAC_CONFIG_CHECKSUM_OFFLOAD indicates that IPv4 header checksum -//! checking and IPv4 or IPv6 TCP, UPD or ICMP payload checksum checking is -//! enabled. The results of the checksum calculations are reported via status -//! fields in the DMA receive descriptors. -//! - \b EMAC_CONFIG_RETRY_DISABLE indicates that retransmission is disabled -//! in cases where half-duplex mode is in use and a collision occurs. This -//! condition causes the current frame to be ignored and a frame abort to be -//! reported in the transmit frame status. -//! - \b EMAC_CONFIG_AUTO_CRC_STRIPPING indicates that the last 4 bytes -//! (frame check sequence) from all Ether type frames are being stripped before -//! frames are forwarded to the application. -//! - \b EMAC_CONFIG_DEFERRAL_CHK_ENABLE indicates that transmit deferral -//! checking is disabled in half-duplex mode. When enabled, the transmitter -//! reports an error if it is unable to transmit a frame for more than 24288 -//! bit times (or 155680 bit times in Jumbo frame mode) due to an active -//! carrier sense signal on the MII. -//! - \b EMAC_CONFIG_TX_ENABLED indicates that the MAC transmitter is -//! currently enabled. -//! - \b EMAC_CONFIG_RX_ENABLED indicates that the MAC receiver is -//! currently enabled. -//! -//! The \e pui32ModeFlags parameter is written with operating parameters -//! related to the internal MAC FIFOs. It comprises a logical OR of the -//! following fields. The first field reports the transmit FIFO threshold. -//! Transmission of a frame begins when this amount of data or a full frame -//! exists in the transmit FIFO. This field should be ignored if -//! \b EMAC_MODE_TX_STORE_FORWARD is also reported. One of the following -//! values is reported: -//! -//! - \b EMAC_MODE_TX_THRESHOLD_16_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_24_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_40_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_128_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_192_BYTES -//! - \b EMAC_MODE_TX_THRESHOLD_256_BYTES -//! -//! The second field reports the receive FIFO threshold. DMA transfers of -//! received data begin either when the receive FIFO contains a full frame -//! or this number of bytes. This field should be ignored if -//! \b EMAC_MODE_RX_STORE_FORWARD is included. One of the following values -//! is reported: -//! -//! - \b EMAC_MODE_RX_THRESHOLD_64_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_32_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_96_BYTES -//! - \b EMAC_MODE_RX_THRESHOLD_128_BYTES -//! -//! The following additional flags may be included: -//! -//! - \b EMAC_MODE_KEEP_BAD_CRC indicates that frames with TCP/IP checksum -//! errors are being forwarded to the application if those frames do not have -//! any errors (including FCS errors) in the Ethernet framing. In these cases, -//! the frames have errors only in the payload. If this flag is not reported, -//! all frames with any detected error are discarded unless -//! \b EMAC_MODE_RX_ERROR_FRAMES is also reported. -//! - \b EMAC_MODE_RX_STORE_FORWARD indicates that the receive DMA is -//! configured to read frames from the FIFO only after the complete frame has -//! been written to it. If this mode is enabled, the receive threshold is -//! ignored. -//! - \b EMAC_MODE_RX_FLUSH_DISABLE indicates that the flushing of received -//! frames is disabled in cases where receive descriptors or buffers are -//! unavailable. -//! - \b EMAC_MODE_TX_STORE_FORWARD indicates that the transmitter is -//! configured to transmit a frame only after the whole frame has been written -//! to the transmit FIFO. If this mode is enabled, the transmit threshold is -//! ignored. -//! - \b EMAC_MODE_RX_ERROR_FRAMES indicates that all frames other than runt -//! error frames are being forwarded to the receive DMA regardless of any -//! errors detected in the frames. -//! - \b EMAC_MODE_RX_UNDERSIZED_FRAMES indicates that undersized frames -//! (frames shorter than 64 bytes but with no errors) are being forwarded to -//! the application. If this option is not reported, all undersized frames are -//! dropped by the receiver unless it has already started transferring them to -//! the receive FIFO due to the receive threshold setting. -//! - \b EMAC_MODE_OPERATE_2ND_FRAME indicates that the transmit DMA is -//! configured to operate on a second frame while waiting for the previous -//! frame to be transmitted and associated status and timestamps to be reported. -//! If absent, the transmit DMA works on a single frame at any one time, -//! waiting for that frame to be transmitted and its status to be received -//! before moving on to the next frame. -//! - \b EMAC_MODE_TX_DMA_ENABLED indicates that the transmit DMA engine is -//! currently enabled. -//! - \b EMAC_MODE_RX_DMA_ENABLED indicates that the receive DMA engine is -//! currently enabled. -//! -//! The \e pui32RxMaxFrameSize is written with the currently configured maximum -//! receive packet size. Packets larger than this are flagged as being in -//! error. -//! -//! \return None. -// -//***************************************************************************** -void -EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, uint32_t *pui32Mode, - uint32_t *pui32RxMaxFrameSize) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(pui32Mode); - ASSERT(pui32Config); - ASSERT(pui32RxMaxFrameSize); - - // - // Return the mode information from the operation mode register. - // - *pui32Mode = HWREG(ui32Base + EMAC_O_DMAOPMODE); - - // - // Return the current configuration flags from the EMAC_O_CFG register. - // - *pui32Config = (HWREG(ui32Base + EMAC_O_CFG) & - (VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED | - EMAC_CONFIG_RX_ENABLED)); - - // - // Get the receive packet size watchdog value. - // - ui32Value = HWREG(ui32Base + EMAC_O_WDOGTO); - if(ui32Value & EMAC_WDOGTO_PWE) - { - // - // The watchdog is enables so the maximum packet length can be read - // from the watchdog timeout register. - // - *pui32RxMaxFrameSize = ui32Value & EMAC_WDOGTO_WTO_M; - } - else - { - // - // The maximum packet size override found in the watchdog timer - // register is not enabled so the maximum packet size is determined - // by whether or not jumbo frame mode is enabled. - // - if(HWREG(ui32Base + EMAC_O_CFG) & EMAC_CFG_JFEN) - { - // - // Jumbo frames are enabled so the watchdog kicks in at 10240 - // bytes. - // - *pui32RxMaxFrameSize = 10240; - } - else - { - // - // Jumbo frames are not enabled so the watchdog kicks in at - // 2048 bytes. - // - *pui32RxMaxFrameSize = 2048; - } - } -} - -//***************************************************************************** -// -//! Sets the MAC address of the Ethernet controller. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui32Index is the zero-based index of the MAC address to set. -//! \param pui8MACAddr is the pointer to the array of MAC-48 address octets. -//! -//! This function programs the IEEE-defined MAC-48 address specified in -//! \e pui8MACAddr into the Ethernet controller. This address is used by the -//! Ethernet controller for hardware-level filtering of incoming Ethernet -//! packets (when promiscuous mode is not enabled). Index 0 is used to hold -//! the local node's MAC address which is inserted into all transmitted -//! packets. -//! -//! The controller may support several Ethernet MAC address slots, each of which -//! may be programmed independently and used to filter incoming packets. The -//! number of MAC addresses that the hardware supports may be queried using a -//! call to EMACNumAddrGet(). The value of the \e ui32Index parameter must -//! lie in the range from 0 to (number of MAC addresses - 1) inclusive. -//! -//! The MAC-48 address is defined as 6 octets, illustrated by the following -//! example address. The numbers are shown in hexadecimal format. -//! -//! AC-DE-48-00-00-80 -//! -//! In this representation, the first three octets (AC-DE-48) are the -//! Organizationally Unique Identifier (OUI). This is a number assigned by -//! the IEEE to an organization that requests a block of MAC addresses. The -//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner -//! to uniquely identify a piece of hardware within that organization that is -//! to be connected to the Ethernet. -//! -//! In this representation, the octets are transmitted from left to right, -//! with the ``AC'' octet being transmitted first and the ``80'' octet being -//! transmitted last. Within an octet, the bits are transmitted LSB to MSB. -//! For this address, the first bit to be transmitted would be ``0'', the LSB -//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of -//! ``80''. -//! -//! The address passed to this function in the \e pui8MACAddr array is -//! ordered with the first byte to be transmitted in the first array entry. -//! For example, the address given above could be represented using the -//! following array: -//! -//! uint8_t g_pui8MACAddr[] = { 0xAC, 0xDE, 0x48, 0x00, 0x00, 0x80 }; -//! -//! If the MAC address set by this function is currently enabled, it remains -//! enabled following this call. Similarly, any filter configured for -//! the MAC address remains unaffected by a change in the address. -//! -//! \return None. -// -//***************************************************************************** -void -EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT(pui8MACAddr); - - // - // Set the high 2 bytes of the MAC address. Note that we must set the - // registers in this order since the address is latched internally - // on the write to EMAC_O_ADDRL. - // - HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) = - ((HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF0000) | - pui8MACAddr[4] | (pui8MACAddr[5] << 8)); - - // - // Set the first 4 bytes of the MAC address - // - HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = - (pui8MACAddr[0] | (pui8MACAddr[1] << 8) | (pui8MACAddr[2] << 16) | - (pui8MACAddr[3] << 24)); -} - -//***************************************************************************** -// -//! Gets one of the MAC addresses stored in the Ethernet controller. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Index is the zero-based index of the MAC address to return. -//! \param pui8MACAddr is the pointer to the location in which to store the -//! array of MAC-48 address octets. -//! -//! This function reads the currently programmed MAC address into the -//! \e pui8MACAddr buffer. The \e ui32Index parameter defines which of the -//! hardware's MAC addresses to return. The number of MAC addresses supported -//! by the controller may be queried using a call to EMACNumAddrGet(). -//! Index 0 refers to the MAC address of the local node. Other indices are -//! used to define MAC addresses when filtering incoming packets. -//! -//! The address is written to the pui8MACAddr array ordered with the first byte -//! to be transmitted in the first array entry. For example, if the address -//! is written in its usual form with the Organizationally Unique Identifier -//! (OUI) shown first as: -//! -//! AC-DE-48-00-00-80 -//! -//! the data is returned with 0xAC in the first byte of the array, 0xDE in -//! the second, 0x48 in the third and so on. -//! -//! \return None. -// -//***************************************************************************** -void -EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, uint8_t *pui8MACAddr) -{ - uint32_t ui32Val; - - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT(pui8MACAddr); - - // - // Get the first 4 bytes of the MAC address. - // - ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)); - pui8MACAddr[0] = ui32Val & 0xFF; - pui8MACAddr[1] = (ui32Val >> 8) & 0xFF; - pui8MACAddr[2] = (ui32Val >> 16) & 0xFF; - pui8MACAddr[3] = (ui32Val >> 24) & 0xFF; - - // - // Get the last 2 bytes of the MAC address. - // - ui32Val = HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)); - pui8MACAddr[4] = ui32Val & 0xFF; - pui8MACAddr[5] = (ui32Val >> 8) & 0xFF; -} - -//***************************************************************************** -// -//! Returns the number of MAC addresses supported by the Ethernet controller. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function may be used to determine the number of MAC addresses that the -//! given controller supports. MAC address slots may be used when performing -//! perfect (rather than hash table) filtering of packets. -//! -//! \return Returns the number of supported MAC addresses. -// -//***************************************************************************** -uint32_t -EMACNumAddrGet(uint32_t ui32Base) -{ - // - // The only Ethernet controller on Snowflake supports 4 MAC addresses. - // - return(NUM_MAC_ADDR); -} - -//***************************************************************************** -// -//! Sets filtering parameters associated with one of the configured MAC -//! addresses. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Index is the index of the MAC address slot for which the filter -//! is to be set. -//! \param ui32Config sets the filter parameters for the given MAC address. -//! -//! This function sets filtering parameters associated with one of the MAC -//! address slots that the controller supports. This configuration is used -//! when perfect filtering (rather than hash table filtering) is selected. -//! -//! Valid values for \e ui32Index are from 1 to (number of MAC address -//! slots - 1). The number of supported MAC address slots may be found by -//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does -//! not have filtering parameters associated with it. -//! -//! The \e ui32Config parameter determines how the given MAC address is used -//! when filtering incoming Ethernet frames. It is comprised of a logical OR -//! of the fields: -//! -//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled -//! and should be used when performing perfect filtering. If this flag is -//! absent, the MAC address at the given index is disabled and is not used -//! in filtering. -//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given -//! index is compared to the source address of incoming frames while -//! performing perfect filtering. If absent, the MAC address is compared -//! against the destination address. -//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC should ignore the -//! sixth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC should ignore the -//! fifth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC should ignore the -//! fourth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC should ignore the -//! third byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC should ignore the -//! second byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC should ignore the -//! first byte of the source or destination address when filtering. -//! -//! \return None. -// -//***************************************************************************** -void -EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config) -{ - uint32_t ui32Val; - - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT((ui32Config & ~(EMAC_FILTER_BYTE_MASK_M | - EMAC_FILTER_ADDR_ENABLE | - EMAC_FILTER_SOURCE_ADDR)) == 0); - ASSERT(ui32Index); - - // - // Set the filter configuration for a particular MAC address. - // - HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) = - (HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF) | ui32Config; - - // - // Read and rewrite the low half of the MAC address register to ensure - // that the upper half's data is latched. - // - ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)); - HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = ui32Val; -} - -//***************************************************************************** -// -//! Gets filtering parameters associated with one of the configured MAC -//! addresses. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Index is the index of the MAC address slot for which the filter -//! is to be queried. -//! -//! This function returns filtering parameters associated with one of the MAC -//! address slots that the controller supports. This configuration is used -//! when perfect filtering (rather than hash table filtering) is selected. -//! -//! Valid values for \e ui32Index are from 1 to (number of MAC address -//! slots - 1). The number of supported MAC address slots may be found by -//! calling EMACNumAddrGet(). MAC index 0 is the local MAC address and does -//! not have filtering parameters associated with it. -//! -//! \return Returns the filter configuration as the logical OR of the -//! following labels: -//! -//! - \b EMAC_FILTER_ADDR_ENABLE indicates that this MAC address is enabled -//! and is used when performing perfect filtering. If this flag is absent, -//! the MAC address at the given index is disabled and is not used in -//! filtering. -//! - \b EMAC_FILTER_SOURCE_ADDR indicates that the MAC address at the given -//! index is compared to the source address of incoming frames while performing -//! perfect filtering. If absent, the MAC address is compared against the -//! destination address. -//! - \b EMAC_FILTER_MASK_BYTE_6 indicates that the MAC ignores the -//! sixth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_5 indicates that the MAC ignores the -//! fifth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_4 indicates that the MAC ignores the -//! fourth byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_3 indicates that the MAC ignores the -//! third byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_2 indicates that the MAC ignores the -//! second byte of the source or destination address when filtering. -//! - \b EMAC_FILTER_MASK_BYTE_1 indicates that the MAC ignores the -//! first byte of the source or destination address when filtering. -// -//***************************************************************************** -uint32_t -EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Index < NUM_MAC_ADDR); - ASSERT(ui32Index); - - // - // Read and return the filter settings for the requested MAC address slot. - // - return(HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & - (EMAC_FILTER_BYTE_MASK_M | EMAC_FILTER_ADDR_ENABLE | - EMAC_FILTER_SOURCE_ADDR)); -} - -//***************************************************************************** -// -//! Sets options related to Ethernet frame filtering. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32FilterOpts is a logical OR of flags defining the required MAC -//! address filtering options. -//! -//! This function allows various filtering options to be defined and allows -//! an application to control which frames are received based on various -//! criteria related to the frame source and destination MAC addresses or VLAN -//! tagging. -//! -//! The \e ui32FilterOpts parameter is a logical OR of any of the following -//! flags: -//! -//! - \b EMAC_FRMFILTER_RX_ALL configures the MAC to pass all received frames -//! regardless of whether or not they pass any address filter that is -//! configured. The receive status word in the relevant DMA descriptor is -//! updated to indicate whether the configured filter passed or failed for -//! the frame. -//! - \b EMAC_FRMFILTER_VLAN configures the MAC to drop any frames that do -//! not pass the VLAN tag comparison. -//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT configures the MAC to filter frames -//! based on both any perfect filters set and the hash filter if enabled using -//! \b EMAC_FRMFILTER_HASH_UNICAST or \b EMAC_FRMFILTER_HASH_MULTICAST. In -//! this case, only if both filters fail is the packet rejected. If this -//! option is absent, only one of the filter types is used, as controlled by -//! \b EMAC_FRMFILTER_HASH_UNICAST and \b EMAC_FRMFILTER_HASH_MULTICAST -//! for unicast and multicast frames respectively. -//! - \b EMAC_FRMFILTER_SADDR configures the MAC to drop received frames -//! when the source address field in the frame does not match the values -//! programmed into the enabled SA registers. -//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. -//! When this option is specified, frames for which the SA does not match the -//! SA registers are marked as passing the source address filter. -//! - \b EMAC_FRMFILTER_BROADCAST configures the MAC to discard all incoming -//! broadcast frames. -//! - \b EMAC_FRMFILTER_PASS_MULTICAST configures the MAC to pass all -//! incoming frames with multicast destinations addresses. -//! - \b EMAC_FRMFILTER_INV_DADDR inverts the sense of the destination -//! address filtering for both unicast and multicast frames. -//! - \b EMAC_FRMFILTER_HASH_MULTICAST enables destination address filtering -//! of received multicast frames using the hash table. If absent, perfect -//! destination address filtering is used. If used in conjunction with \b -//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter -//! should be used for incoming multicast packets along with the perfect -//! filter. -//! - \b EMAC_FRMFILTER_HASH_UNICAST enables destination address filtering -//! of received unicast frames using the hash table. If absent, perfect -//! destination address filtering is used. If used in conjunction with \b -//! EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates that the hash filter -//! should be used for incoming unicast packets along with the perfect filter. -//! - \b EMAC_FRMFILTER_PROMISCUOUS configures the MAC to operate in -//! promiscuous mode where all received frames are passed to the application -//! and the SA and DA filter status bits of the descriptor receive status word -//! are always cleared. -//! -//! Control frame filtering may be configured by ORing one of the following -//! values into \e ui32FilterOpts: -//! -//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching -//! the application. -//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they -//! pass the configured address filter. -//! -//! \return None. -// -//***************************************************************************** -void -EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts) -{ - ASSERT((ui32FilterOpts & ~VALID_FRMFILTER_FLAGS) == 0); - - // - // Set the Ethernet MAC frame filter according to the flags passed. - // - HWREG(ui32Base + EMAC_O_FRAMEFLTR) = - ((HWREG(ui32Base + EMAC_O_FRAMEFLTR) & ~VALID_FRMFILTER_FLAGS) | - ui32FilterOpts); -} - -//***************************************************************************** -// -//! Returns the current Ethernet frame filtering settings. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be called to retrieve the frame filtering configuration -//! set using a prior call to EMACFrameFilterSet(). -//! -//! \return Returns a value comprising the logical OR of various flags -//! indicating the frame filtering options in use. Possible flags are: -//! -//! - \b EMAC_FRMFILTER_RX_ALL indicates that the MAC to is configured to -//! pass all received frames regardless of whether or not they pass any -//! address filter that is configured. The receive status word in the -//! relevant DMA descriptor is updated to indicate whether the configured -//! filter passed or failed for the frame. -//! - \b EMAC_FRMFILTER_VLAN indicates that the MAC is configured to drop any -//! frames which do not pass the VLAN tag comparison. -//! - \b EMAC_FRMFILTER_HASH_AND_PERFECT indicates that the MAC is configured -//! to pass frames if they match either the hash filter or the perfect filter. -//! If this flag is absent, frames passing based on the result of a single -//! filter, the perfect filter if \b EMAC_FRMFILTER_HASH_MULTICAST or -//! \b EMAC_FRMFILTER_HASH_UNICAST are clear or the hash filter otherwise. -//! - \b EMAC_FRMFILTER_SADDR indicates that the MAC is configured to drop -//! received frames when the source address field in the frame does not match -//! the values programmed into the enabled SA registers. -//! - \b EMAC_FRMFILTER_INV_SADDR enables inverse source address filtering. -//! When this option is specified, frames for which the SA does not match the -//! SA registers are marked as passing the source address filter. -//! - \b EMAC_FRMFILTER_BROADCAST indicates that the MAC is configured to -//! discard all incoming broadcast frames. -//! - \b EMAC_FRMFILTER_PASS_MULTICAST indicates that the MAC is configured -//! to pass all incoming frames with multicast destinations addresses. -//! - \b EMAC_FRMFILTER_INV_DADDR indicates that the sense of the destination -//! address filtering for both unicast and multicast frames is inverted. -//! - \b EMAC_FRMFILTER_HASH_MULTICAST indicates that destination address -//! filtering of received multicast frames is enabled using the hash table. If -//! absent, perfect destination address filtering is used. If used in -//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates -//! that the hash filter should be used for incoming multicast packets along -//! with the perfect filter. -//! - \b EMAC_FRMFILTER_HASH_UNICAST indicates that destination address -//! filtering of received unicast frames is enabled using the hash table. If -//! absent, perfect destination address filtering is used. If used in -//! conjunction with \b EMAC_FRMFILTER_HASH_AND_PERFECT, this flag indicates -//! that the hash filter should be used for incoming unicast packets along with -//! the perfect filter. -//! - \b EMAC_FRMFILTER_PROMISCUOUS indicates that the MAC is configured to -//! operate in promiscuous mode where all received frames are passed to the -//! application and the SA and DA filter status bits of the descriptor receive -//! status word are always cleared. -//! -//! Control frame filtering configuration is indicated by one of the following -//! values which may be extracted from the returned value using the mask -//! \b EMAC_FRMFILTER_PASS_MASK: -//! -//! - \b EMAC_FRMFILTER_PASS_NO_CTRL prevents any control frame from reaching -//! the application. -//! - \b EMAC_FRMFILTER_PASS_NO_PAUSE passes all control frames other than -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ALL_CTRL passes all control frames, including -//! PAUSE even if they fail the configured address filter. -//! - \b EMAC_FRMFILTER_PASS_ADDR_CTRL passes all control frames only if they -//! pass the configured address filter. -// -//***************************************************************************** -uint32_t -EMACFrameFilterGet(uint32_t ui32Base) -{ - // - // Return the current MAC frame filter setting. - // - return(HWREG(ui32Base + EMAC_O_FRAMEFLTR) & VALID_FRMFILTER_FLAGS); -} - -//***************************************************************************** -// -//! Sets the MAC address hash filter table. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32HashHi is the upper 32 bits of the current 64-bit hash filter -//! table to set. -//! \param ui32HashLo is the lower 32 bits of the current 64-bit hash filter -//! table to set. -//! -//! This function may be used to set the current 64-bit hash filter table -//! used by the MAC to filter incoming packets when hash filtering is enabled. -//! Hash filtering is enabled by passing \b EMAC_FRMFILTER_HASH_UNICAST -//! and/or \b EMAC_FRMFILTER_HASH_MULTICAST in the \e ui32FilterOpts parameter -//! to EMACFrameFilterSet(). The current hash filter may be retrieved -//! by calling EMACHashFilterGet(). -//! -//! Hash table filtering allows many different MAC addresses to be filtered -//! simultaneously at the cost of some false-positive results (in the form of -//! packets passing the filter when their MAC address was not one of those -//! required). A CRC of the packet source or destination MAC address is -//! calculated and the bottom 6 bits are used as a bit index into the 64-bit -//! hash filter table. If the bit in the hash table is set, the filter is -//! considered to have passed. If the bit is clear, the filter fails and the -//! packet is rejected (assuming normal rather than inverse filtering is -//! configured). -//! -//! \return None. -// -//***************************************************************************** -void -EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo) -{ - // Set the hash table with the values provided. - HWREG(ui32Base + EMAC_O_HASHTBLL) = ui32HashLo; - HWREG(ui32Base + EMAC_O_HASHTBLH) = ui32HashHi; -} - -//***************************************************************************** -// -//! Returns the current MAC address hash filter table. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui32HashHi points to storage to be written with the upper 32 bits -//! of the current 64-bit hash filter table. -//! \param pui32HashLo points to storage to be written with the lower 32 bits -//! of the current 64-bit hash filter table. -//! -//! This function may be used to retrieve the current 64-bit hash filter table -//! from the MAC prior to making changes and setting the new hash filter via a -//! call to EMACHashFilterSet(). -//! -//! Hash table filtering allows many different MAC addresses to be filtered -//! simultaneously at the cost of some false-positive results in the form of -//! packets passing the filter when their MAC address was not one of those -//! required. A CRC of the packet source or destination MAC address is -//! calculated and the bottom 6 bits are used as a bit index into the 64-bit -//! hash filter table. If the bit in the hash table is set, the filter is -//! considered to have passed. If the bit is clear, the filter fails and the -//! packet is rejected (assuming normal rather than inverse filtering is -//! configured). -//! -//! \return None. -// -//***************************************************************************** -void -EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, - uint32_t *pui32HashLo) -{ - ASSERT(pui32HashHi); - ASSERT(pui32HashLo); - - // - // Get the current hash table values. - // - *pui32HashLo = HWREG(ui32Base + EMAC_O_HASHTBLL); - *pui32HashHi = HWREG(ui32Base + EMAC_O_HASHTBLH); -} - -//***************************************************************************** -// -//! Returns the bit number to set in the MAC hash filter corresponding to a -//! given MAC address. -//! -//! \param pui8MACAddr points to a buffer containing the 6-byte MAC address -//! for which the hash filter bit is to be determined. -//! -//! This function may be used to determine which bit in the MAC address hash -//! filter to set to describe a given 6-byte MAC address. The returned value is -//! a 6-bit number where bit 5 indicates which of the two hash table words is -//! affected and the bottom 5 bits indicate the bit number to set within that -//! word. For example, if 0x22 (100010b) is returned, this indicates that bit -//! 2 of word 1 (\e ui32HashHi as passed to EMACHashFilterSet()) must be set -//! to describe the passed MAC address. -//! -//! \return Returns the bit number to set in the MAC hash table to describe the -//! passed MAC address. -// -//***************************************************************************** -uint32_t -EMACHashFilterBitCalculate(uint8_t *pui8MACAddr) -{ - uint32_t ui32CRC, ui32Mask, ui32Loop; - - // - // Parameter sanity check. - // - ASSERT(pui8MACAddr); - - // - // Calculate the CRC for the MAC address. - // - ui32CRC = Crc32(0xFFFFFFFF, pui8MACAddr, 6); - ui32CRC ^= 0xFFFFFFFF; - - // - // Determine the hash bit to use from the calculated CRC. This is the - // top 6 bits of the reversed CRC (or the bottom 6 bits of the calculated - // CRC with the bit order of those 6 bits reversed). - // - ui32Mask = 0; - - // - // Reverse the order of the bottom 6 bits of the calculated CRC. - // - for(ui32Loop = 0; ui32Loop < 6; ui32Loop++) - { - ui32Mask <<= 1; - ui32Mask |= (ui32CRC & 1); - ui32CRC >>= 1; - } - - // - // Return the final hash table bit index. - // - return(ui32Mask); -} - -//***************************************************************************** -// -//! Sets the receive interrupt watchdog timer period. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! \param ui8Timeout is the desired timeout expressed as a number of 256 -//! system clock periods. -//! -//! This function configures the receive interrupt watchdog timer. -//! The \e uiTimeout parameter specifies the number of 256 system clock periods -//! that elapse before the timer expires. In cases where the DMA has -//! transferred a frame using a descriptor that has -//! \b DES1_RX_CTRL_DISABLE_INT set, the watchdog causes a receive -//! interrupt to be generated when it times out. The watchdog timer is reset -//! whenever a packet is transferred to memory using a DMA descriptor that -//! does not disable the receive interrupt. -//! -//! To disable the receive interrupt watchdog function, set \e ui8Timeout to 0. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout) -{ - // - // Set the receive interrupt watchdog timeout period. - // - HWREG(ui32Base + EMAC_O_RXINTWDT) = (uint32_t)ui8Timeout; -} - -//***************************************************************************** -// -//! Returns the current Ethernet MAC status. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function returns information on the current status of all the main -//! modules in the MAC transmit and receive data paths. -//! -//! \return Returns the current MAC status as a logical OR of any of the -//! following flags: -//! -//! - \b EMAC_STATUS_TX_NOT_EMPTY -//! - \b EMAC_STATUS_TX_WRITING_FIFO -//! - \b EMAC_STATUS_TX_PAUSED -//! - \b EMAC_STATUS_MAC_NOT_IDLE -//! - \b EMAC_STATUS_RWC_ACTIVE -//! - \b EMAC_STATUS_RPE_ACTIVE -//! -//! The transmit frame controller status can be extracted from the returned -//! value by ANDing with \b EMAC_STATUS_TFC_STATE_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_TFC_STATE_IDLE -//! - \b EMAC_STATUS_TFC_STATE_WAITING -//! - \b EMAC_STATUS_TFC_STATE_PAUSING -//! - \b EMAC_STATUS_TFC_STATE_WRITING -//! -//! The transmit FIFO read controller status can be extracted from the returned -//! value by ANDing with \b EMAC_STATUS_TRC_STATE_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_TRC_STATE_IDLE -//! - \b EMAC_STATUS_TRC_STATE_READING -//! - \b EMAC_STATUS_TRC_STATE_WAITING -//! - \b EMAC_STATUS_TRC_STATE_STATUS -//! -//! The current receive FIFO levels can be extracted from the returned value -//! by ANDing with \b EMAC_STATUS_RX_FIFO_LEVEL_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_RX_FIFO_EMPTY indicating that the FIFO is empty. -//! - \b EMAC_STATUS_RX_FIFO_BELOW indicating that the FIFO fill level is -//! below the flow-control deactivate threshold. -//! - \b EMAC_STATUS_RX_FIFO_ABOVE indicating that the FIFO fill level is -//! above the flow-control activate threshold. -//! - \b EMAC_STATUS_RX_FIFO_FULL indicating that the FIFO is full. -//! -//! The current receive FIFO state can be extracted from the returned value -//! by ANDing with \b EMAC_STATUS_RX_FIFO_STATE_MASK and is one of the -//! following: -//! -//! - \b EMAC_STATUS_RX_FIFO_IDLE -//! - \b EMAC_STATUS_RX_FIFO_READING -//! - \b EMAC_STATUS_RX_FIFO_STATUS -//! - \b EMAC_STATUS_RX_FIFO_FLUSHING -// -//***************************************************************************** -uint32_t -EMACStatusGet(uint32_t ui32Base) -{ - // - // Read and return the MAC status register content. - // - return(HWREG(ui32Base + EMAC_O_STATUS)); -} - -//***************************************************************************** -// -//! Orders the MAC DMA controller to attempt to acquire the next transmit -//! descriptor. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function must be called to restart the transmitter if it has been -//! suspended due to the current transmit DMA descriptor being owned by the -//! host. Once the application writes new values to the descriptor and marks -//! it as being owned by the MAC DMA, this function causes the hardware to -//! attempt to acquire the descriptor and start transmission of the new -//! data. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxDMAPollDemand(uint32_t ui32Base) -{ - // - // Any write to the MACTXPOLLD register causes the transmit DMA to attempt - // to resume. - // - HWREG(ui32Base + EMAC_O_TXPOLLD) = 0; -} - -//***************************************************************************** -// -//! Orders the MAC DMA controller to attempt to acquire the next receive -//! descriptor. -//! -//! \param ui32Base is the base address of the Ethernet controller. -//! -//! This function must be called to restart the receiver if it has been -//! suspended due to the current receive DMA descriptor being owned by the -//! host. Once the application reads any data from the descriptor and marks -//! it as being owned by the MAC DMA, this function causes the hardware to -//! attempt to acquire the descriptor before writing the next received packet -//! into its buffer(s). -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxDMAPollDemand(uint32_t ui32Base) -{ - // - // Any write to the MACRXPOLLD register causes the receive DMA to attempt - // to resume. - // - HWREG(ui32Base + EMAC_O_RXPOLLD) = 0; -} - -//***************************************************************************** -// -//! Sets the DMA receive descriptor list pointer. -//! -//! \param ui32Base is the base address of the controller. -//! \param pDescriptor points to the first DMA descriptor in the list to -//! be passed to the receive DMA engine. -//! -//! This function sets the Ethernet MAC's receive DMA descriptor list pointer. -//! The \e pDescriptor pointer must point to one or more descriptor -//! structures. -//! -//! When multiple descriptors are provided, they can be either chained or -//! unchained. Chained descriptors are indicated by setting the -//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant -//! word of the transmit or receive descriptor. If this bit is clear, -//! unchained descriptors are assumed. -//! -//! Chained descriptors use a link pointer in each descriptor to -//! point to the next descriptor in the chain. -//! -//! Unchained descriptors are assumed to be contiguous in memory with a -//! consistent offset between the start of one descriptor and the next. -//! If unchained descriptors are used, the \e pvLink field in the descriptor -//! becomes available to store a second buffer pointer, allowing each -//! descriptor to point to two buffers rather than one. In this case, -//! the \e ui32DescSkipSize parameter to EMACInit() must previously have -//! been set to the number of words between the end of one descriptor and -//! the start of the next. This value must be 0 in cases where a packed array -//! of \b tEMACDMADescriptor structures is used. If the application wishes to -//! add new state fields to the end of the descriptor structure, the skip size -//! should be set to accommodate the newly sized structure. -//! -//! Applications are responsible for initializing all descriptor fields -//! appropriately before passing the descriptor list to the hardware. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) -{ - // - // Parameter sanity check. - // - ASSERT(pDescriptor); - ASSERT(((uint32_t)pDescriptor & 3) == 0); - - // - // Write the supplied address to the MACRXDLADDR register. - // - HWREG(ui32Base + EMAC_O_RXDLADDR) = (uint32_t)pDescriptor; -} - -//***************************************************************************** -// -//! Returns a pointer to the start of the DMA receive descriptor list. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the head of the Ethernet MAC's receive -//! DMA descriptor list. This value corresponds to the pointer originally set -//! using a call to EMACRxDMADescriptorListSet(). -//! -//! \return Returns a pointer to the start of the DMA receive descriptor list. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACRxDMADescriptorListGet(uint32_t ui32Base) -{ - // - // Return the current receive DMA descriptor list pointer. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_RXDLADDR)); -} - -//***************************************************************************** -// -//! Returns the current DMA receive descriptor pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the current Ethernet receive descriptor -//! read by the DMA. -//! -//! \return Returns a pointer to the start of the current receive DMA -//! descriptor. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACRxDMACurrentDescriptorGet(uint32_t ui32Base) -{ - // - // Return the address of the current receive descriptor written by the DMA. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSRXDESC)); -} - -//***************************************************************************** -// -//! Returns the current DMA receive buffer pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be called to determine which buffer the receive DMA -//! engine is currently writing to. -//! -//! \return Returns the receive buffer address currently being written by -//! the DMA engine. -// -//***************************************************************************** -uint8_t * -EMACRxDMACurrentBufferGet(uint32_t ui32Base) -{ - // - // Return the receive buffer address currently being written by the DMA. - // - return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSRXBA)); -} - -//***************************************************************************** -// -//! Sets the DMA transmit descriptor list pointer. -//! -//! \param ui32Base is the base address of the controller. -//! \param pDescriptor points to the first DMA descriptor in the list to -//! be passed to the transmit DMA engine. -//! -//! This function sets the Ethernet MAC's transmit DMA descriptor list pointer. -//! The \e pDescriptor pointer must point to one or more descriptor -//! structures. -//! -//! When multiple descriptors are provided, they can be either chained or -//! unchained. Chained descriptors are indicated by setting the -//! \b DES0_TX_CTRL_CHAINED or \b DES1_RX_CTRL_CHAINED bit in the relevant -//! word of the transmit or receive descriptor. If this bit is clear, -//! unchained descriptors are assumed. -//! -//! Chained descriptors use a link pointer in each descriptor to -//! point to the next descriptor in the chain. -//! -//! Unchained descriptors are assumed to be contiguous in memory with a -//! consistent offset between the start of one descriptor and the next. -//! If unchained descriptors are used, the \e pvLink field in the descriptor -//! becomes available to store a second buffer pointer, allowing each -//! descriptor to point to two buffers rather than one. In this case, -//! the \e ui32DescSkipSize parameter to EMACInit() must previously have -//! been set to the number of words between the end of one descriptor and -//! the start of the next. This value must be 0 in cases where a packed array -//! of \b tEMACDMADescriptor structures is used. If the application wishes to -//! add new state fields to the end of the descriptor structure, the skip size -//! should be set to accommodate the newly sized structure. -//! -//! Applications are responsible for initializing all descriptor fields -//! appropriately before passing the descriptor list to the hardware. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor) -{ - // - // Parameter sanity check. - // - ASSERT(pDescriptor); - ASSERT(((uint32_t)pDescriptor & 3) == 0); - - // - // Write the supplied address to the MACTXDLADDR register. - // - HWREG(ui32Base + EMAC_O_TXDLADDR) = (uint32_t)pDescriptor; -} - -//***************************************************************************** -// -//! Returns a pointer to the start of the DMA transmit descriptor list. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the head of the Ethernet MAC's transmit -//! DMA descriptor list. This value corresponds to the pointer originally set -//! using a call to EMACTxDMADescriptorListSet(). -//! -//! \return Returns a pointer to the start of the DMA transmit descriptor list. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACTxDMADescriptorListGet(uint32_t ui32Base) -{ - // - // Return the current transmit DMA descriptor list pointer. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_TXDLADDR)); -} - -//***************************************************************************** -// -//! Returns the current DMA transmit descriptor pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns a pointer to the current Ethernet transmit descriptor -//! read by the DMA. -//! -//! \return Returns a pointer to the start of the current transmit DMA -//! descriptor. -// -//***************************************************************************** -tEMACDMADescriptor * -EMACTxDMACurrentDescriptorGet(uint32_t ui32Base) -{ - // - // Return the address of the current transmit descriptor read by the DMA. - // - return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSTXDESC)); -} - -//***************************************************************************** -// -//! Returns the current DMA transmit buffer pointer. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be called to determine which buffer the transmit DMA -//! engine is currently reading from. -//! -//! \return Returns the transmit buffer address currently being read by the -//! DMA engine. -// -//***************************************************************************** -uint8_t * -EMACTxDMACurrentBufferGet(uint32_t ui32Base) -{ - // - // Return the transmit buffer address currently being read by the DMA. - // - return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSTXBA)); -} - -//***************************************************************************** -// -//! Returns the current states of the Ethernet MAC transmit and receive DMA -//! engines. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to query the current states of the transmit and -//! receive DMA engines. The return value contains two fields, one providing -//! the transmit state and the other the receive state. Macros -//! \b EMAC_TX_DMA_STATE() and \b EMAC_RX_DMA_STATE() may be used to -//! extract these fields from the returned value. Alternatively, masks -//! \b EMAC_DMA_TXSTAT_MASK and \b EMAC_DMA_RXSTAT_MASK may be used -//! directly to mask out the individual states from the returned value. -//! -//! \return Returns the states of the transmit and receive DMA engines. These -//! states are ORed together into a single word containing one of: -//! -//! - \b EMAC_DMA_TXSTAT_STOPPED indicating that the transmit engine is -//! stopped. -//! - \b EMAC_DMA_TXSTAT_RUN_FETCH_DESC indicating that the transmit engine -//! is fetching the next descriptor. -//! - \b EMAC_DMA_TXSTAT_RUN_WAIT_STATUS indicating that the transmit engine -//! is waiting for status from the MAC. -//! - \b EMAC_DMA_TXSTAT_RUN_READING indicating that the transmit engine is -//! currently transferring data from memory to the MAC transmit FIFO. -//! - \b EMAC_DMA_TXSTAT_RUN_CLOSE_DESC indicating that the transmit engine -//! is closing the descriptor after transmission of the buffer data. -//! - \b EMAC_DMA_TXSTAT_TS_WRITE indicating that the transmit engine is -//! currently writing timestamp information to the descriptor. -//! - \b EMAC_DMA_TXSTAT_SUSPENDED indicating that the transmit engine is -//! suspended due to the next descriptor being unavailable (owned by the host) -//! or a transmit buffer underflow. -//! -//! and one of: -//! -//! - \b EMAC_DMA_RXSTAT_STOPPED indicating that the receive engine is -//! stopped. -//! - \b EMAC_DMA_RXSTAT_RUN_FETCH_DESC indicating that the receive engine -//! is fetching the next descriptor. -//! - \b EMAC_DMA_RXSTAT_RUN_WAIT_PACKET indicating that the receive engine -//! is waiting for the next packet. -//! - \b EMAC_DMA_RXSTAT_SUSPENDED indicating that the receive engine is -//! suspended due to the next descriptor being unavailable. -//! - \b EMAC_DMA_RXSTAT_RUN_CLOSE_DESC indicating that the receive engine -//! is closing the descriptor after receiving a buffer of data. -//! - \b EMAC_DMA_RXSTAT_TS_WRITE indicating that the transmit engine is -//! currently writing timestamp information to the descriptor. -//! - \b EMAC_DMA_RXSTAT_RUN_RECEIVING indicating that the receive engine is -//! currently transferring data from the MAC receive FIFO to memory. -//! -//! Additionally, a DMA bus error may be signaled using \b EMAC_DMA_ERROR. -//! If this flag is present, the source of the error is identified using one -//! of the following values which may be extracted from the return value using -//! \b EMAC_DMA_ERR_MASK: -//! -//! - \b EMAC_DMA_ERR_RX_DATA_WRITE indicates that an error occurred when -//! writing received data to memory. -//! - \b EMAC_DMA_ERR_TX_DATA_READ indicates that an error occurred when -//! reading data from memory for transmission. -//! - \b EMAC_DMA_ERR_RX_DESC_WRITE indicates that an error occurred when -//! writing to the receive descriptor. -//! - \b EMAC_DMA_ERR_TX_DESC_WRITE indicates that an error occurred when -//! writing to the transmit descriptor. -//! - \b EMAC_DMA_ERR_RX_DESC_READ indicates that an error occurred when -//! reading the receive descriptor. -//! - \b EMAC_DMA_ERR_TX_DESC_READ indicates that an error occurred when -//! reading the transmit descriptor. -// -//***************************************************************************** -uint32_t -EMACDMAStateGet(uint32_t ui32Base) -{ - // - // Return the status of the DMA channels. - // - return(HWREG(ui32Base + EMAC_O_DMARIS) & - (EMAC_DMARIS_FBI | EMAC_DMARIS_AE_M | EMAC_DMARIS_RS_M | - EMAC_DMARIS_TS_M)); -} - -//***************************************************************************** -// -//! Flushes the Ethernet controller transmit FIFO. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function flushes any data currently held in the Ethernet transmit -//! FIFO. Data that has already been passed to the MAC for transmission is -//! transmitted, possibly resulting in a transmit underflow or runt frame -//! transmission. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxFlush(uint32_t ui32Base) -{ - // - // Check to make sure that the FIFO is not already empty. - // - if(HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_TXFE) - { - // - // Flush the transmit FIFO since it is not currently empty. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_FTF; - - // - // Wait for the flush to complete. - // - while(HWREG(ui32Base + EMAC_O_DMAOPMODE) & EMAC_DMAOPMODE_FTF) - { - } - } -} - -//***************************************************************************** -// -//! Enables the Ethernet controller transmitter. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When starting operations on the Ethernet interface, this function should -//! be called to enable the transmitter after all configuration has been -//! completed. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxEnable(uint32_t ui32Base) -{ - // - // Enable the MAC transmit path in the opmode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_ST; - - // - // Enable transmission in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_TE; -} - -//***************************************************************************** -// -//! Disables the Ethernet controller transmitter. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When terminating operations on the Ethernet interface, this function should -//! be called. This function disables the transmitter. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTxDisable(uint32_t ui32Base) -{ - // - // Disable transmission in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; - - // - // Disable the MAC transmit path in the opmode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; -} - -//***************************************************************************** -// -//! Enables the Ethernet controller receiver. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When starting operations on the Ethernet interface, this function should -//! be called to enable the receiver after all configuration has been -//! completed. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxEnable(uint32_t ui32Base) -{ - // - // Enable the MAC receive path. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_SR; - - // - // Enable receive in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_RE; -} - -//***************************************************************************** -// -//! Disables the Ethernet controller receiver. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When terminating operations on the Ethernet interface, this function should -//! be called. This function disables the receiver. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRxDisable(uint32_t ui32Base) -{ - // - // Disable reception in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_RE; - - // - // Disable the MAC receive path. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for an Ethernet interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled Ethernet interrupts occur. -//! -//! This function sets the handler to be called when the Ethernet interrupt -//! occurs. This function enables the global interrupt in the interrupt -//! controller; specific Ethernet interrupts must be enabled via -//! EMACIntEnable(). It is the interrupt handler's responsibility to clear -//! the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler != 0); - - // - // Register the interrupt handler. - // - IntRegister(INT_EMAC0_TM4C129, pfnHandler); - - // - // Enable the Ethernet interrupt. - // - IntEnable(INT_EMAC0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for an Ethernet interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function unregisters the interrupt handler. This function disables -//! the global interrupt in the interrupt controller so that the interrupt -//! handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntUnregister(uint32_t ui32Base) -{ - // - // Disable the interrupt. - // - IntDisable(INT_EMAC0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_EMAC0_TM4C129); -} - -//***************************************************************************** -// -//! Enables individual Ethernet MAC interrupt sources. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated Ethernet MAC interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. -//! Software must read and write the appropriate PHY registers to enable and -//! disable particular notifications. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! -//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and -//! \b EMAC_INT_ABNORMAL_INT are enabled automatically by the driver if any -//! of their constituent sources are enabled. Applications do not need to -//! explicitly enable these bits. -//! -//! \note Timestamp-related interrupts from the IEEE 1588 module must be -//! enabled independently by using a call to EMACTimestampTargetIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Parameter sanity check. - // - ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0); - - // - // Enable the normal interrupt if any of its individual sources are - // enabled. - // - if(ui32IntFlags & EMAC_NORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_NORMAL_INT; - } - - // - // Similarly, enable the abnormal interrupt if any of its individual - // sources are enabled. - // - if(ui32IntFlags & EMAC_ABNORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_ABNORMAL_INT; - } - - // - // Set the MAC DMA interrupt mask appropriately if any of the sources - // we've been asked to enable are found in that register. - // - if(ui32IntFlags & ~EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_DMAIM) |= ui32IntFlags & ~EMAC_INT_PHY; - } - - // - // Enable the PHY interrupt if we've been asked to do this. - // - if(ui32IntFlags & EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_EPHYIM) |= EMAC_EPHYIM_INT; - } -} - -//***************************************************************************** -// -//! Disables individual Ethernet MAC interrupt sources. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated Ethernet MAC interrupt sources. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. -//! Software must read and write the appropriate PHY registers to enable and -//! disable particular notifications. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! - \b EMAC_INT_TIMESTAMP indicates that an interrupt from the timestamp -//! module has occurred. This precise source of the interrupt can be -//! determined by calling EMACTimestampIntStatus(), which also clears this -//! bit. -//! -//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and -//! \b EMAC_INT_ABNORMAL_INT are disabled automatically by the driver if none -//! of their constituent sources are enabled. Applications do not need to -//! explicitly disable these bits. -//! -//! \note Timestamp-related interrupts from the IEEE 1588 module must be -//! disabled independently by using a call to EMACTimestampTargetIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - uint32_t ui32Mask; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0); - - // - // Get the current interrupt mask. - // - ui32Mask = HWREG(ui32Base + EMAC_O_DMAIM); - - // - // Clear the requested bits. - // - ui32Mask &= ~(ui32IntFlags & ~EMAC_INT_PHY); - - // - // If none of the normal interrupt sources are enabled, disable the - // normal interrupt. - // - if(!(ui32Mask & EMAC_NORMAL_INTS)) - { - ui32Mask &= ~EMAC_INT_NORMAL_INT; - } - - // - // Similarly, if none of the abnormal interrupt sources are enabled, - // disable the abnormal interrupt. - // - if(!(ui32Mask & EMAC_ABNORMAL_INTS)) - { - ui32Mask &= ~EMAC_INT_ABNORMAL_INT; - } - - // - // Write the new mask back to the hardware. - // - HWREG(ui32Base + EMAC_O_DMAIM) = ui32Mask; - - // - // Disable the PHY interrupt if we've been asked to do this. - // - if(ui32IntFlags & EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_EPHYIM) &= ~EMAC_EPHYIM_INT; - } -} - -//***************************************************************************** -// -//! Gets the current Ethernet MAC interrupt status. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param bMasked is \b true to return the masked interrupt status or \b false -//! to return the unmasked status. -//! -//! This function returns the interrupt status for the Ethernet MAC. Either -//! the raw interrupt status or the status of interrupts that are allowed -//! to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status as the logical OR of any of -//! the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY interrupt has occurred. -//! Software must read the relevant PHY interrupt status register to determine -//! the cause. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. The cause of the error can be -//! determined by calling EMACDMAStateGet(). -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! - \b EMAC_INT_NORMAL_INT is a summary interrupt comprising the logical -//! OR of the masked state of \b EMAC_INT_TRANSMIT, \b EMAC_INT_RECEIVE, -//! \b EMAC_INT_TX_NO_BUFFER and \b EMAC_INT_EARLY_RECEIVE. -//! - \b EMAC_INT_ABNORMAL_INT is a summary interrupt comprising the logical -//! OR of the masked state of \b EMAC_INT_TX_STOPPED, \b EMAC_INT_TX_JABBER, -//! \b EMAC_INT_RX_OVERFLOW, \b EMAC_INT_TX_UNDERFLOW, -//! \b EMAC_INT_RX_NO_BUFFER, \b EMAC_INT_RX_STOPPED, -//! \b EMAC_INT_RX_WATCHDOG, \b EMAC_INT_EARLY_TRANSMIT and -//! \b EMAC_INT_BUS_ERROR. -// -//***************************************************************************** -uint32_t -EMACIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Val, ui32PHYStat; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Get the unmasked interrupt status and clear any unwanted status fields. - // - ui32Val = HWREG(ui32Base + EMAC_O_DMARIS); - ui32Val &= ~(EMAC_DMARIS_AE_M | EMAC_DMARIS_TS_M | EMAC_DMARIS_RS_M); - - // - // This peripheral doesn't have a masked interrupt status register - // so perform the masking manually. Note that only the bottom 16 bits - // of the register can be masked so make sure we take this into account. - // - if(bMasked) - { - ui32Val &= (EMAC_NON_MASKED_INTS | HWREG(ui32Base + EMAC_O_DMAIM)); - } - - // - // Read the PHY interrupt status. - // - if(bMasked) - { - ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYMISC); - } - else - { - ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYRIS); - } - - // - // If the PHY interrupt is reported, add the appropriate flag to the - // return value. - // - if(ui32PHYStat & EMAC_EPHYMISC_INT) - { - ui32Val |= EMAC_INT_PHY; - } - - return(ui32Val); -} - -//***************************************************************************** -// -//! Clears individual Ethernet MAC interrupt sources. -//! -//! \param ui32Base is the base address of the Ethernet MAC. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. -//! -//! This function disables the indicated Ethernet MAC interrupt sources. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b EMAC_INT_PHY indicates that the PHY has signaled a change of state. -//! Software must read and write the appropriate PHY registers to enable, -//! disable and clear particular notifications. -//! - \b EMAC_INT_EARLY_RECEIVE indicates that the DMA engine has filled the -//! first data buffer of a packet. -//! - \b EMAC_INT_BUS_ERROR indicates that a fatal bus error has occurred and -//! that the DMA engine has been disabled. -//! - \b EMAC_INT_EARLY_TRANSMIT indicates that a frame to be transmitted has -//! been fully written from memory into the MAC transmit FIFO. -//! - \b EMAC_INT_RX_WATCHDOG indicates that a frame with length greater than -//! 2048 bytes (of 10240 bytes in Jumbo Frame mode) was received. -//! - \b EMAC_INT_RX_STOPPED indicates that the receive process has entered -//! the stopped state. -//! - \b EMAC_INT_RX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's receive descriptor list and the DMA cannot, therefore, acquire -//! a buffer. The receive process is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACRxDMAPollDemand(). -//! - \b EMAC_INT_RECEIVE indicates that reception of a frame has completed -//! and all requested status has been written to the appropriate DMA receive -//! descriptor. -//! - \b EMAC_INT_TX_UNDERFLOW indicates that the transmitter experienced an -//! underflow during transmission. The transmit process is suspended. -//! - \b EMAC_INT_RX_OVERFLOW indicates that an overflow was experienced -//! during reception. -//! - \b EMAC_INT_TX_JABBER indicates that the transmit jabber timer expired. -//! This condition occurs when the frame size exceeds 2048 bytes (or 10240 -//! bytes in Jumbo Frame mode) and causes the transmit process to abort and -//! enter the Stopped state. -//! - \b EMAC_INT_TX_NO_BUFFER indicates that the host owns the next buffer -//! in the DMA's transmit descriptor list and that the DMA cannot, therefore, -//! acquire a buffer. Transmission is suspended and can be resumed by changing -//! the descriptor ownership and calling EMACTxDMAPollDemand(). -//! - \b EMAC_INT_TX_STOPPED indicates that the transmit process has stopped. -//! - \b EMAC_INT_TRANSMIT indicates that transmission of a frame has -//! completed and that all requested status has been updated in the descriptor. -//! -//! Summary interrupt bits \b EMAC_INT_NORMAL_INT and -//! \b EMAC_INT_ABNORMAL_INT are cleared automatically by the driver if any -//! of their constituent sources are cleared. Applications do not need to -//! explicitly clear these bits. -//! -//! \return None. -// -//***************************************************************************** -void -EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Mask in the normal interrupt if one of the sources it relates to is - // specified. - // - if(ui32IntFlags & EMAC_NORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_NORMAL_INT; - } - - // - // Similarly, mask in the abnormal interrupt if one of the sources it - // relates to is specified. - // - if(ui32IntFlags & EMAC_ABNORMAL_INTS) - { - ui32IntFlags |= EMAC_INT_ABNORMAL_INT; - } - - // - // Clear the maskable interrupt sources. We write exactly the value passed - // (with the summary sources added if necessary) but remember that only - // the bottom 17 bits of the register are actually clearable. Only do - // this if some bits are actually set that refer to the DMA interrupt - // sources. - // - if(ui32IntFlags & ~EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_DMARIS) = (ui32IntFlags & ~EMAC_INT_PHY); - } - - // - // Clear the PHY interrupt if we've been asked to do this. - // - if(ui32IntFlags & EMAC_INT_PHY) - { - HWREG(ui32Base + EMAC_O_EPHYMISC) |= EMAC_EPHYMISC_INT; - } -} - -//***************************************************************************** -// -//! Writes to the PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui8RegAddr is the address of the PHY register to be accessed. -//! \param ui16Data is the data to be written to the PHY register. -//! -//! This function writes the \e ui16Data value to the PHY register specified by -//! \e ui8RegAddr. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr, - uint16_t ui16Data) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - - // - // Make sure the MII is idle. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } - - // - // Write the value provided. - // - HWREG(ui32Base + EMAC_O_MIIDATA) = ui16Data; - - // - // Tell the MAC to write the given PHY register. - // - HWREG(ui32Base + EMAC_O_MIIADDR) = - ((HWREG(ui32Base + EMAC_O_MIIADDR) & - EMAC_MIIADDR_CR_M) | (ui8RegAddr << EMAC_MIIADDR_MII_S) | - (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIW | - EMAC_MIIADDR_MIIB); - - // - // Wait for the write to complete. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } -} - -//***************************************************************************** -// -//! Reads from a PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui8RegAddr is the address of the PHY register to be accessed. -//! -//! This function returns the contents of the PHY register specified by -//! \e ui8RegAddr. -//! -//! \return Returns the 16-bit value read from the PHY. -// -//***************************************************************************** -uint16_t -EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - ASSERT(ui32Base == EMAC0_BASE); - - // - // Make sure the MII is idle. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } - - // - // Tell the MAC to read the given PHY register. - // - HWREG(ui32Base + EMAC_O_MIIADDR) = - ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) | - (ui8RegAddr << EMAC_MIIADDR_MII_S) | - (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB); - - // - // Wait for the read to complete. - // - while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) - { - } - - // - // Return the result. - // - return(HWREG(ui32Base + EMAC_O_MIIDATA) & EMAC_MIIDATA_DATA_M); -} - -//***************************************************************************** -// -//! Reads from an extended PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! -//! When using the internal PHY or when connected to an external PHY -//! supporting extended registers, this function returns the contents of the -//! extended PHY register specified by \e ui16RegAddr. -//! -//! \return Returns the 16-bit value read from the PHY. -// -//***************************************************************************** -uint16_t -EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - ASSERT(ui32Base == EMAC0_BASE); - - // - // Set the address of the register we're about to read. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F); - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr); - - // - // Read the extended register value. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F); - return(EMACPHYRead(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR)); -} - -//***************************************************************************** -// -//! Writes a value to an extended PHY register. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! \param ui16Value is the value to write to the register. -//! -//! When using the internal PHY or when connected to an external PHY -//! supporting extended registers, this function allows a value to be written -//! to the extended PHY register specified by \e ui16RegAddr. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr, uint16_t ui16Value) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - ASSERT(ui32Base == EMAC0_BASE); - - // - // Set the address of the register we're about to write. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F); - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr); - - // - // Write the extended register. - // - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F); - EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16Value); -} - -//***************************************************************************** -// -//! Powers off the Ethernet PHY. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to power down. -//! -//! This function powers off the Ethernet PHY, reducing the current -//! consumption of the device. While in the powered-off state, the Ethernet -//! controller is unable to connect to Ethernet. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr) -{ - // - // Set the PWRDN bit and clear the ANEN bit in the PHY, putting it into - // its low power mode. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR, - (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) & - ~EPHY_BMCR_ANEN) | EPHY_BMCR_PWRDWN); -} - -//***************************************************************************** -// -//! Powers on the Ethernet PHY. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to power up. -//! -//! This function powers on the Ethernet PHY, enabling it return to normal -//! operation. By default, the PHY is powered on, so this function is only -//! called if EMACPHYPowerOff() has previously been called. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr) -{ - // - // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into - // normal operating mode. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR, - (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) & - ~EPHY_BMCR_PWRDWN) | EPHY_BMCR_ANEN); -} - -//***************************************************************************** -// -//! Configures the Ethernet MAC's IEEE 1588 timestamping options. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Config contains flags selecting particular configuration -//! options. -//! \param ui32SubSecondInc is the number that the IEEE 1588 subsecond clock -//! should increment on each tick. -//! -//! This function is used to configure the operation of the Ethernet MAC's -//! internal timestamping clock. This clock is used to timestamp incoming -//! and outgoing packets and as an accurate system time reference when -//! IEEE 1588 Precision Time Protocol is in use. -//! -//! The \e ui32Config parameter contains a collection of flags selecting the -//! desired options. Valid flags are: -//! -//! One of the following to determine whether IEEE 1588 version 1 or version 2 -//! packet format is to be processed: -//! -//! - \b EMAC_TS_PTP_VERSION_2 -//! - \b EMAC_TS_PTP_VERSION_1 -//! -//! One of the following to determine how the IEEE 1588 clock's subsecond -//! value should be interpreted and handled: -//! -//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll -//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered -//! as a nanosecond counter with each digit representing 1 ns. -//! - \b EMAC_TS_BINARY_ROLLOVER causes the clock's subsecond value to roll -//! over at 0x7FFFFFFF. In this mode, the subsecond value counts 0.465 ns -//! periods. -//! -//! One of the following to enable or disable MAC address filtering. When -//! enabled, PTP frames are filtered unless the destination MAC address matches -//! any of the currently programmed MAC addresses. -//! -//! - \b EMAC_TS_MAC_FILTER_ENABLE -//! - \b EMAC_TS_MAC_FILTER_DISABLE -//! -//! One of the following to determine how the clock is updated: -//! - \b EMAC_TS_UPDATE_COARSE causes the IEEE 1588 clock to advance by -//! the value supplied in the \e ui32SubSecondInc parameter on each main -//! oscillator clock cycle. -//! - \b EMAC_TS_UPDATE_FINE selects the fine update method which causes the -//! IEEE 1588 clock to advance by the the value supplied in the -//! \e ui32SubSecondInc parameter each time a carry is generated from the -//! addend accumulator register. -//! -//! One of the following to determine which IEEE 1588 messages are timestamped: -//! -//! - \b EMAC_TS_SYNC_FOLLOW_DREQ_DRESP timestamps SYNC, Follow_Up, Delay_Req -//! and Delay_Resp messages. -//! - \b EMAC_TS_SYNC_ONLY timestamps only SYNC messages. -//! - \b EMAC_TS_DELAYREQ_ONLY timestamps only Delay_Req messages. -//! - \b EMAC_TS_ALL timestamps all IEEE 1588 messages. -//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and -//! Pdelay_Resp messages. -//! - \b EMAC_TS_DREQ_PDREQ_PDRESP timestamps only Delay_Req, Pdelay_Req and -//! Pdelay_Resp messages. -//! - \b EMAC_TS_SYNC_DELAYREQ timestamps only Delay_Req messages. -//! - \b EMAC_TS_PDREQ_PDRESP timestamps only Pdelay_Req and Pdelay_Resp -//! messages. -//! -//! Optional, additional flags are: -//! -//! - \b EMAC_TS_PROCESS_IPV4_UDP processes PTP packets encapsulated in UDP -//! over IPv4 packets. If absent, the MAC ignores these frames. -//! - \b EMAC_TS_PROCESS_IPV6_UDP processes PTP packets encapsulated in UDP -//! over IPv6 packets. If absent, the MAC ignores these frames. -//! - \b EMAC_TS_PROCESS_ETHERNET processes PTP packets encapsulated directly -//! in Ethernet frames. If absent, the MAC ignores these frames. -//! - \b EMAC_TS_ALL_RX_FRAMES enables timestamping for all frames received -//! by the MAC, regardless of type. -//! -//! The \e ui32SubSecondInc controls the rate at which the timestamp clock's -//! subsecond count increments. Its meaning depends on which of \b -//! EMAC_TS_DIGITAL_ROLLOVER or \b EMAC_TS_BINARY_ROLLOVER and -//! \b EMAC_TS_UPDATE_FINE or \b EMAC_TS_UPDATE_COARSE were included -//! in \e ui32Config. -//! -//! The timestamp second counter is incremented each time the subsecond counter -//! rolls over. In digital rollover mode, the subsecond counter acts as a -//! simple 31-bit counter, rolling over to 0 after reaching 0x7FFFFFFF. In -//! this case, each lsb of the subsecond counter represents 0.465 ns (assuming -//! the definition of 1 second resolution for the seconds counter). When -//! binary rollover mode is selected, the subsecond counter acts as a -//! nanosecond counter and rolls over to 0 after reaching 999,999,999 making -//! each lsb represent 1 nanosecond. -//! -//! In coarse update mode, the timestamp subsecond counter is incremented by -//! \e ui32SubSecondInc on each main oscillator clock tick. Setting -//! \e ui32SubSecondInc to the main oscillator clock period in either 1 ns or -//! 0.465 ns units ensures that the time stamp, read as seconds and -//! subseconds, increments at the same rate as the main oscillator clock. For -//! example, if the main oscillator is 25 MHz, \e ui32SubSecondInc is set to 40 -//! if digital rollover mode is selected or (40 / 0.465) = 86 in binary -//! rollover mode. -//! -//! In fine update mode, the subsecond increment value must be set according -//! to the desired accuracy of the recovered IEEE 1588 clock which must be -//! lower than the system clock rate. Fine update mode is typically used when -//! synchronizing the local clock to the IEEE 1588 master clock. The subsecond -//! counter is incremented by \e ui32SubSecondInc counts each time a 32-bit -//! accumulator register generates a carry. The accumulator register is -//! incremented by the addend value on each main oscillator tick and this -//! addend value is modified to allow fine control over the rate of change of -//! the timestamp counter. The addend value is calculated using the ratio of -//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the -//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588 -//! clock rate. As an example, using digital rollover mode and a 25-MHz -//! main oscillator clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, -//! we would set \e ui32SubSecondInc to the 12.5-MHz clock period of 80 ns and -//! set the initial addend value to 0x80000000 to generate a carry on every -//! second system clock. -//! -//! \sa EMACTimestampAddendSet() -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32SubSecondInc) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Ensure that the PTP module clock is enabled. - // - HWREG(ui32Base + EMAC_O_CC) |= EMAC_CC_PTPCEN; - - // - // Write the subsecond increment value. - // - HWREG(ui32Base + EMAC_O_SUBSECINC) = ((ui32SubSecondInc << - EMAC_SUBSECINC_SSINC_S) & - EMAC_SUBSECINC_SSINC_M); - - // - // Set the timestamp configuration. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Returns the current IEEE 1588 timestamping configuration. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui32SubSecondInc points to storage that is written with the -//! current subsecond increment value for the IEEE 1588 clock. -//! -//! This function may be used to retreive the current MAC timestamping -//! configuration. -//! -//! \sa EMACTimestampConfigSet() -//! -//! \return Returns the current timestamping configuration as a logical OR of -//! the following flags: -//! -//! - \b EMAC_TS_PTP_VERSION_2 indicates that the MAC is processing PTP -//! version 2 messages. If this flag is absent, PTP version 1 messages are -//! expected. -//! - \b EMAC_TS_DIGITAL_ROLLOVER causes the clock's subsecond value to roll -//! over at 0x3BA9C9FF (999999999 decimal). In this mode, it can be considered -//! as a nanosecond counter with each digit representing 1 ns. If this flag is -//! absent, the subsecond value rolls over at 0x7FFFFFFF, effectively counting -//! increments of 0.465 ns. -//! - \b EMAC_TS_MAC_FILTER_ENABLE indicates that incoming PTP messages -//! are filtered using any of the configured MAC addresses. Messages with a -//! destination address programmed into the MAC address filter are passed, -//! others are discarded. If this flag is absent, the MAC address is ignored. -//! - \b EMAC_TS_UPDATE_FINE implements the fine update method that causes the -//! IEEE 1588 clock to advance by the the value returned in the -//! \e *pui32SubSecondInc parameter each time a carry is generated from the -//! addend accumulator register. If this flag is absent, the coarse update -//! method is in use and the clock is advanced by the \e *pui32SubSecondInc -//! value on each system clock tick. -//! - \b EMAC_TS_SYNC_ONLY indicates that timestamps are only generated for -//! SYNC messages. -//! - \b EMAC_TS_DELAYREQ_ONLY indicates that timestamps are only generated -//! for Delay_Req messages. -//! - \b EMAC_TS_ALL indicates that timestamps are generated for all -//! IEEE 1588 messages. -//! - \b EMAC_TS_SYNC_PDREQ_PDRESP timestamps only SYNC, Pdelay_Req and -//! Pdelay_Resp messages. -//! - \b EMAC_TS_DREQ_PDREQ_PDRESP indicates that timestamps are only -//! generated for Delay_Req, Pdelay_Req and Pdelay_Resp messages. -//! - \b EMAC_TS_SYNC_DELAYREQ indicates that timestamps are only generated -//! for Delay_Req messages. -//! - \b EMAC_TS_PDREQ_PDRESP indicates that timestamps are only generated -//! for Pdelay_Req and Pdelay_Resp messages. -//! - \b EMAC_TS_PROCESS_IPV4_UDP indicates that PTP packets encapsulated in -//! UDP over IPv4 packets are being processed. If absent, the MAC ignores -//! these frames. -//! - \b EMAC_TS_PROCESS_IPV6_UDP indicates that PTP packets encapsulated in -//! UDP over IPv6 packets are being processed. If absent, the MAC ignores -//! these frames. -//! - \b EMAC_TS_PROCESS_ETHERNET indicates that PTP packets encapsulated -//! directly in Ethernet frames are being processd. If absent, the MAC ignores -//! these frames. -//! - \b EMAC_TS_ALL_RX_FRAMES indicates that timestamping is enabled for all -//! frames received by the MAC, regardless of type. -//! -//! If \b EMAC_TS_ALL_RX_FRAMES and none of the options specifying subsets -//! of PTP packets to timestamp are set, the MAC is configured to timestamp -//! SYNC, Follow_Up, Delay_Req and Delay_Resp messages only. -// -//***************************************************************************** -uint32_t -EMACTimestampConfigGet(uint32_t ui32Base, uint32_t *pui32SubSecondInc) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui32SubSecondInc); - - // - // Read the current subsecond increment value. - // - *pui32SubSecondInc = (HWREG(ui32Base + EMAC_O_SUBSECINC) & - EMAC_SUBSECINC_SSINC_M) >> EMAC_SUBSECINC_SSINC_S; - - // - // Return the current timestamp configuration. - // - return(HWREG(ui32Base + EMAC_O_TIMSTCTRL)); -} - -//***************************************************************************** -// -//! Enables packet timestamping and starts the system clock running. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to enable the system clock used to timestamp -//! Ethernet frames and to enable that timestamping. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampEnable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Enable IEEE 1588 timestamping. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSEN; - - // - // If necessary, initialize the timestamping system. This bit self-clears - // once the system time is loaded. Only do this if initialization is not - // currently ongoing. - // - if(!(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT)) - { - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT; - } -} - -//***************************************************************************** -// -//! Disables packet timestamping and stops the system clock. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to stop the system clock used to timestamp -//! Ethernet frames and to disable timestamping. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampDisable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Disable IEEE 1588 timestamping. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_TSEN; -} - -//***************************************************************************** -// -//! Sets the current system time. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Seconds is the seconds value of the new system clock setting. -//! \param ui32SubSeconds is the subseconds value of the new system clock -//! setting. -//! -//! This function may be used to set the current system time. The system -//! clock is set to the value passed in the \e ui32Seconds and -//! \e ui32SubSeconds parameters. -//! -//! The meaning of \e ui32SubSeconds depends on the current system time -//! configuration. If EMACTimestampConfigSet() was previously called with -//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the -//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was -//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the new time to the system time update registers. - // - HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds; - HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds; - - // - // Wait for any previous update to complete. - // - while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT) - { - // - // Spin for a while. - // - } - - // - // Force the system clock to reset. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT; -} - -//***************************************************************************** -// -//! Gets the current system time. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui32Seconds points to storage for the current seconds value. -//! \param pui32SubSeconds points to storage for the current subseconds value. -//! -//! This function may be used to get the current system time. -//! -//! The meaning of \e ui32SubSeconds depends on the current system time -//! configuration. If EMACTimestampConfigSet() was previously called with -//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the -//! \e ui32SubSeconds value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was -//! specified instead, a \e ui32SubSeconds bit represents 0.46 ns. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, - uint32_t *pui32SubSeconds) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui32Seconds); - ASSERT(pui32SubSeconds); - - // - // Read the two-part system time from the seconds and nanoseconds - // registers. We do this in a way that should guard against us reading - // the registers across a nanosecond wrap. - // - do - { - *pui32Seconds = HWREG(ui32Base + EMAC_O_TIMSEC); - *pui32SubSeconds = HWREG(ui32Base + EMAC_O_TIMNANO); - } - while(*pui32SubSeconds > HWREG(ui32Base + EMAC_O_TIMNANO)); -} - -//***************************************************************************** -// -//! Adjusts the current system time upwards or downwards by a given amount. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Seconds is the seconds value of the time update to apply. -//! \param ui32SubSeconds is the subseconds value of the time update to apply. -//! \param bInc defines the direction of the update. -//! -//! This function may be used to adjust the current system time either upwards -//! or downwards by a given amount. The size of the adjustment is given by -//! the \e ui32Seconds and \e ui32SubSeconds parameter and the direction -//! by the \e bInc parameter. When \e bInc is \e true, the system time is -//! advanced by the interval given. When it is \e false, the time is retarded -//! by the interval. -//! -//! The meaning of \e ui32SubSeconds depends on the current system time -//! configuration. If EMACTimestampConfigSet() was previously called with -//! the \e EMAC_TS_DIGITAL_ROLLOVER configuration option, each bit in the -//! subsecond value represents 1 ns. If \e EMAC_TS_BINARY_ROLLOVER was -//! specified instead, a subsecond bit represents 0.46 ns. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds, bool bInc) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the new time to the system time update registers. - // - HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds; - HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds | - (bInc ? 0 : EMAC_TIMNANOU_ADDSUB); - - // - // Wait for any previous update to complete. - // - while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSUPDT) - { - // - // Spin for a while. - // - } - - // - // Force the system clock to update by the value provided. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSUPDT; -} - -//***************************************************************************** -// -//! Adjusts the system time update rate when using the fine correction method. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Increment is the number to add to the accumulator register on -//! each tick of the 25-MHz main oscillator. -//! -//! This function is used to control the rate of update of the system time -//! when in fine update mode. Fine correction mode is selected if -//! \e EMAC_TS_UPDATE_FINE is supplied in the \e ui32Config parameter passed -//! to a previous call to EMACTimestampConfigSet(). Fine update mode is -//! typically used when synchronizing the local clock to the IEEE 1588 master -//! clock. The subsecond counter is incremented by the number passed to -//! EMACTimestampConfigSet() in the \e ui32SubSecondInc parameter each time a -//! 32-bit accumulator register generates a carry. The accumulator register is -//! incremented by the "addend" value on each main oscillator tick, and this -//! addend value is modified to allow fine control over the rate of change of -//! the timestamp counter. The addend value is calculated using the ratio of -//! the main oscillator clock rate and the desired IEEE 1588 clock rate and the -//! \e ui32SubSecondInc value is set to correspond to the desired IEEE 1588 -//! clock rate. -//! -//! As an example, using digital rollover mode and a 25-MHz main oscillator -//! clock with a desired IEEE 1588 clock accuracy of 12.5 MHz, and having made -//! a previous call to EMACTimestampConfigSet() with \e ui32SubSecondInc set to -//! the 12.5-MHz clock period of 80 ns, the initial \e ui32Increment value -//! would be set to 0x80000000 to generate a carry on every second main -//! oscillator tick. Because the system time updates each time the accumulator -//! overflows, small changes in the \e ui32Increment value can be used to very -//! finely control the system time rate. -//! -//! \return None. -//! -//! \sa EMACTimestampConfigSet() -// -//***************************************************************************** -void -EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Increment) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - HWREG(ui32Base + EMAC_O_TIMADD) = ui32Increment; - - // - // Wait for any previous update to complete. - // - while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_ADDREGUP) - { - // - // Spin for a while. - // - } - - // - // Force the system clock to update by the value provided. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_ADDREGUP; -} - -//***************************************************************************** -// -//! Sets the target system time at which the next Ethernet timer interrupt is -//! generated. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Seconds is the second value of the desired target time. -//! \param ui32SubSeconds is the subseconds value of the desired target time. -//! -//! This function may be used to schedule an interrupt at some future time. -//! The time reference for the function is the IEEE 1588 time as returned by -//! EMACTimestampSysTimeGet(). To generate an interrupt when the system -//! time exceeds a given value, call this function to set the desired time, -//! then EMACTimestampTargetIntEnable() to enable the interrupt. When the -//! system time increments past the target time, an Ethernet interrupt with -//! status \b EMAC_INT_TIMESTAMP is generated. -//! -//! The accuracy of the interrupt timing depends on the Ethernet timer -//! update frequency and the subsecond increment value currently in use. The -//! interrupt is generated on the first timer increment that causes the -//! system time to be greater than or equal to the target time set. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Wait for any previous write to complete. - // - while(HWREG(ui32Base + EMAC_O_TARGNANO) & EMAC_TARGNANO_TRGTBUSY) - { - } - - // - // Write the new target time. - // - HWREG(ui32Base + EMAC_O_TARGSEC) = ui32Seconds; - HWREG(ui32Base + EMAC_O_TARGNANO) = ui32SubSeconds; -} - -//***************************************************************************** -// -//! Enables the Ethernet system time interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used after EMACTimestampTargetSet() to schedule an -//! interrupt at some future time. The time reference for the function is -//! the IEEE 1588 time as returned by EMACTimestampSysTimeGet(). To generate -//! an interrupt when the system time exceeds a given value, call this function -//! to set the desired time, then EMACTimestampTargetIntEnable() to enable the -//! interrupt. When the system time increments past the target time, an -//! Ethernet interrupt with status \b EMAC_INT_TIMESTAMP is generated. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampTargetIntEnable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Set the bit to enable the timestamp target interrupt. This bit clears - // automatically when the interrupt fires after which point, you must - // set a new target time and re-enable the interrupts. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_INTTRIG; -} - -//***************************************************************************** -// -//! Disables the Ethernet system time interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to disable any pending Ethernet system time -//! interrupt previously scheduled using calls to EMACTimestampTargetSet() -//! and EMACTimestampTargetIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampTargetIntDisable(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Clear the bit to disable the timestamp target interrupt. This bit - // clears automatically when the interrupt fires, so it only must be - // disabled if you want to cancel a previously-set interrupt. - // - HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_INTTRIG; -} - -//***************************************************************************** -// -//! Reads the status of the Ethernet system time interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! -//! When an Ethernet interrupt occurs and \b EMAC_INT_TIMESTAMP is reported -//! bu EMACIntStatus(), this function must be called to read and clear the -//! timer interrupt status. -//! -//! \return The return value is the logical OR of the values -//! \b EMAC_TS_INT_TS_SEC_OVERFLOW and \b EMAC_TS_INT_TARGET_REACHED. -//! -//! - \b EMAC_TS_INT_TS_SEC_OVERFLOW indicates that the second counter in the -//! hardware timer has rolled over. -//! - \b EMAC_TS_INT_TARGET_REACHED indicates that the system time incremented -//! past the value set in an earlier call to EMACTimestampTargetSet(). When -//! this occurs, a new target time may be set and the interrupt re-enabled -//! using calls to EMACTimestampTargetSet() and -//! EMACTimestampTargetIntEnable(). -// -//***************************************************************************** -uint32_t -EMACTimestampIntStatus(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Return the current interrupt status from the timestamp module. - // - return(HWREG(ui32Base + EMAC_O_TIMSTAT)); -} - -//***************************************************************************** -// -//! Configures the Ethernet MAC PPS output in simple mode. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32FreqConfig determines the frequency of the output generated on -//! the PPS pin. -//! -//! This function configures the Ethernet MAC PPS (Pulse Per Second) engine to -//! operate in its simple mode which allows the generation of a few, fixed -//! frequencies and pulse widths on the PPS pin. If more complex pulse -//! train generation is required, the MAC also provides a command-based -//! PPS control mode that can be selected by calling -//! EMACTimestampPPSCommandModeSet(). -//! -//! The \e ui32FreqConfig parameter may take one of the following values: -//! -//! - \b EMAC_PPS_SINGLE_PULSE generates a single high pulse on the PPS -//! output once per second. The pulse width is the same as the system clock -//! period. -//! - \b EMAC_PPS_1HZ generates a 1Hz signal on the PPS output. This option -//! is not available if the system time subsecond counter is currently -//! configured to operate in binary rollover mode. -//! - \b EMAC_PPS_2HZ, \b EMAC_PPS_4HZ, \b EMAC_PPS_8HZ, -//! \b EMAC_PPS_16HZ, \b EMAC_PPS_32HZ, \b EMAC_PPS_64HZ, -//! \b EMAC_PPS_128HZ, \b EMAC_PPS_256HZ, \b EMAC_PPS_512HZ, -//! \b EMAC_PPS_1024HZ, \b EMAC_PPS_2048HZ, \b EMAC_PPS_4096HZ, -//! \b EMAC_PPS_8192HZ, \b EMAC_PPS_16384HZ generate the requested -//! frequency on the PPS output in both binary and digital rollover modes. -//! - \b EMAC_PPS_32768HZ generates a 32KHz signal on the PPS output. This -//! option is not available if the system time subsecond counter is currently -//! configured to operate in digital rollover mode. -//! -//! Except when \b EMAC_PPS_SINGLE_PULSE is specified, the signal generated -//! on PPS has a duty cycle of 50% when binary rollover mode is used for the -//! system time subsecond count. In digital mode, the output frequency -//! averages the value requested and is resynchronized each second. For -//! example, if \b EMAC_PPS_4HZ is selected in digital rollover mode, the -//! output generates three clocks with 50 percent duty cycle and 268 ms -//! period followed by a fourth clock of 195 ms period, 134 ms low and 61 ms high. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, uint32_t ui32FreqConfig) -{ - bool bDigital; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Are we currently running the clock in digital or binary rollover mode? - // - bDigital = (HWREG(ui32Base + EMAC_O_TIMSTCTRL) & - EMAC_TS_DIGITAL_ROLLOVER) ? true : false; - - // - // Weed out some unsupported frequencies. The hardware can't produce a - // 1Hz output when we are in binary rollover mode and can't produce a - // 32KHz output when we are digital rollover mode. - // - ASSERT(bDigital || (ui32FreqConfig != EMAC_PPS_1HZ)); - ASSERT(!bDigital || (ui32FreqConfig != EMAC_PPS_32768HZ)); - - // - // Adjust the supplied frequency if we are currently in binary update mode - // where the control value generates an output that is twice as fast as - // in digital mode. - // - if((ui32FreqConfig != EMAC_PPS_SINGLE_PULSE) && !bDigital) - { - ui32FreqConfig--; - } - - // - // Write the frequency control value to the PPS control register, clearing - // the PPSEN0 bit to ensure that the PPS engine is in simple mode and not - // waiting for a command. We also clear the TRGMODS0 field to revert to - // the default operation of the target time registers. - // - HWREG(ui32Base + EMAC_O_PPSCTRL) = ui32FreqConfig; -} - -//***************************************************************************** -// -//! Configures the Ethernet MAC PPS output in command mode. - -//! \param ui32Base is the base address of the controller. -//! \param ui32Config determines how the system target time is used. -//! -//! The simple mode of operation offered by the PPS (Pulse Per Second) engine -//! may be too restrictive for some applications. The second mode, however, -//! allows complex pulse trains to be generated using commands that tell the -//! engine to send individual pulses or start and stop trains if pulses. In -//! this mode, the pulse width and period may be set arbitrarily based on -//! ticks of the clock used to update the system time. Commands are triggered -//! at specific times using the target time last set using a call to -//! EMACTimestampTargetSet(). -//! -//! The \e ui32Config parameter may be used to control whether the target -//! time is used to trigger commands only or can also generate an interrupt -//! to the CPU. Valid values are: -//! -//! - \b EMAC_PPS_TARGET_INT configures the target time to only raise -//! an interrupt and not to trigger any pending PPS command. -//! - \b EMAC_PPS_TARGET_PPS configures the target time to trigger a pending -//! PPS command but not raise an interrupt. -//! - \b EMAC_PPS_TARGET_BOTH configures the target time to trigger any -//! pending PPS command and also raise an interrupt. -//! -//! To use command mode, an application must call this function to enable the -//! mode, then call: -//! -//! - EMACTimestampPPSPeriodSet() to set the desired pulse width and period -//! then -//! - EMACTimestampTargetSet() to set the time at which the next command is -//! executed, and finally -//! - EMACTimestampPPSCommand() to send a command to cause the pulse or -//! pulse train to be started at the required time. -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSCommandModeSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(!(ui32Config & (EMAC_PPS_TARGET_INT | EMAC_PPS_TARGET_PPS | - EMAC_PPS_TARGET_BOTH))); - - // - // Wait for any previous command write to complete. - // - while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M) - { - // - // Wait a bit. - // - } - - // - // Write the configuration value to the PPS control register, setting the - // PPSEN0 bit to ensure that the PPS engine is in command mode and - // clearing the command in the PPSCTRL field. - // - HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui32Config); -} - -//***************************************************************************** -// -//! Sends a command to control the PPS output from the Ethernet MAC. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8Cmd identifies the command to be sent. -//! -//! This function may be used to send a command to the MAC PPS (Pulse Per -//! Second) controller when it is operating in command mode. Command mode -//! is selected by calling EMACTimestampPPSCommandModeSet(). Valid -//! commands are as follow: -//! -//! - \b EMAC_PPS_COMMAND_NONE indicates no command. -//! - \b EMAC_PPS_COMMAND_START_SINGLE indicates that a single high pulse -//! should be generated when the system time reaches the current target time. -//! - \b EMAC_PPS_COMMAND_START_TRAIN indicates that a train of pulses -//! should be started when the system time reaches the current target time. -//! - \b EMAC_PPS_COMMAND_CANCEL_START cancels any pending start command if -//! the system time has not yet reached the programmed target time. -//! - \b EMAC_PPS_COMMAND_STOP_AT_TIME indicates that the current pulse -//! train should be stopped when the system time reaches the current target -//! time. -//! - \b EMAC_PPS_COMMAND_STOP_NOW indicates that the current pulse train -//! should be stopped immediately. -//! - \b EMAC_PPS_COMMAND_CANCEL_STOP cancels any pending stop command if -//! the system time has not yet reached the programmed target time. -//! -//! In all cases, the width of the pulses generated is governed by the -//! \e ui32Width parameter passed to EMACTimestampPPSPeriodSet(). If a -//! command starts a train of pulses, the period of the pulses is governed -//! by the \e ui32Period parameter passed to the same function. -//! Target times associated with PPS commands are set by calling -//! EMACTimestampTargetSet(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Wait for any previous command write to complete. - // - while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M) - { - // - // Wait a bit. - // - } - - // - // Write the command to the PPS control register. - // - HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui8Cmd); -} - -//***************************************************************************** -// -//! Sets the period and width of the pulses on the Ethernet MAC PPS output. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Period is the period of the PPS output expressed in terms of -//! system time update ticks. -//! \param ui32Width is the width of the high portion of the PPS output -//! expressed in terms of system time update ticks. -//! -//! This function may be used to control the period and duty cycle of the -//! signal output on the Ethernet MAC PPS pin when the PPS generator is -//! operating in command mode and a command to send one or more pulses has been -//! executed. Command mode is selected by calling -//! EMACTimestampPPSCommandModeSet(). -//! -//! In simple mode, the PPS output signal frequency is controlled by the -//! \e ui32FreqConfig parameter passed to EMACTimestampPPSSimpleModeSet(). -//! -//! The \e ui32Period and \e ui32Width parameters are expressed in terms of -//! system time update ticks. When the system time is operating in coarse -//! update mode, each tick is equivalent to the system clock. In fine update -//! mode, a tick occurs every time the 32-bit system time accumulator overflows -//! and this, in turn, is determined by the value passed to the function -//! EMACTimestampAddendSet(). Regardless of the tick source, each tick -//! increments the actual system time, queried using EMACTimestampSysTimeGet() -//! by the subsecond increment value passed in the \e ui32SubSecondInc to -//! EMACTimestampConfigSet(). -//! -//! \return None. -// -//***************************************************************************** -void -EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, - uint32_t ui32Width) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the desired PPS period and pulse width. - // - HWREG(ui32Base + EMAC_O_PPS0INTVL) = ui32Period; - HWREG(ui32Base + EMAC_O_PPS0WIDTH) = ui32Width; -} - -//***************************************************************************** -// -//! Sets options related to reception of VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui16Tag is the IEEE 802.1Q VLAN tag expected for incoming frames. -//! \param ui32Config determines how the receiver handles VLAN-tagged frames. -//! -//! This function configures the receiver's handling of IEEE 802.1Q VLAN -//! tagged frames. Incoming tagged frames are filtered using either a perfect -//! filter or a hash filter. When hash filtering is disabled, VLAN frames -//! tagged with the value of \e ui16Tag pass the filter and all others are -//! rejected. The tag comparison may involve all 16 bits or only the 12-bit -//! VLAN ID portion of the tag. -//! -//! The \e ui32Config parameter is a logical OR of the following values: -//! -//! - \b EMAC_VLAN_RX_HASH_ENABLE enables hash filtering for VLAN tags. If -//! this flag is absent, perfect filtering using the tag supplied in \e ui16Tag -//! is performed. The hash filter may be set using EMACVLANHashFilterSet(), -//! and EMACVLANHashFilterBitCalculate() may be used to determine which bits -//! to set in the filter for given VLAN tags. -//! - \b EMAC_VLAN_RX_SVLAN_ENABLE causes the receiver to recognize S-VLAN -//! (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only -//! frames with type 0x8100 are considered valid VLAN frames. -//! - \b EMAC_VLAN_RX_INVERSE_MATCH causes the receiver to pass all VLAN -//! frames for which the tags do not match the supplied \e ui16Tag value. If -//! this flag is absent, only tagged frames matching \e ui16Tag are passed. -//! - \b EMAC_VLAN_RX_12BIT_TAG causes the receiver to compare only the -//! bottom 12 bits of \e ui16Tag when performing either perfect or hash -//! filtering of VLAN frames. If this flag is absent, all 16 bits of the frame -//! tag are examined when filtering. If this flag is set and \e ui16Tag has -//! all bottom 12 bits clear, the receiver passes all frames with types -//! 0x8100 or 0x88A8 regardless of the tag values they contain. -//! -//! \note To ensure that VLAN frames that fail the tag filter are dropped -//! by the MAC, EMACFrameFilterSet() must be called with the \b -//! EMAC_FRMFILTER_VLAN flag set in the \e ui32FilterOpts parameter. If -//! this flag is not set, failing VLAN packets are received by the -//! application, but bit 10 of RDES0 (\b EMAC_FRMFILTER_VLAN) is clear -//! indicating that the packet did not match the current VLAG tag filter. -//! -//! \sa EMACVLANRxConfigGet() -//! -//! \return None -// -//***************************************************************************** -void -EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the VLAN tag register. - // - HWREG(ui32Base + EMAC_O_VLANTG) = - ui32Config | (((uint32_t)ui16Tag) << EMAC_VLANTG_VL_S); -} - -//***************************************************************************** -// -//! Returns the currently-set options related to reception of VLAN-tagged -//! frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui16Tag points to storage which is written with the currently -//! configured VLAN tag used for perfect filtering. -//! -//! This function returns information on how the receiver is currently -//! handling IEEE 802.1Q VLAN-tagged frames. -//! -//! \sa EMACVLANRxConfigSet() -//! -//! \return Returns flags defining how VLAN-tagged frames are handled. The -//! value is a logical OR of the following flags: -//! -//! - \b EMAC_VLAN_RX_HASH_ENABLE indicates that hash filtering is enabled -//! for VLAN tags. If this flag is absent, perfect filtering using the tag -//! returned in \e *pui16Tag is performed. -//! - \b EMAC_VLAN_RX_SVLAN_ENABLE indicates that the receiver recognizes -//! S-VLAN (Type = 0x88A8) frames as valid VLAN-tagged frames. If absent, only -//! frames with type 0x8100 are considered valid VLAN frames. -//! - \b EMAC_VLAN_RX_INVERSE_MATCH indicates that the receiver passes all -//! VLAN frames for which the tags do not match the \e *pui16Tag value. If -//! this flag is absent, only tagged frames matching \e *pui16Tag are passed. -//! - \b EMAC_VLAN_RX_12BIT_TAG indicates that the receiver is comparing only -//! the bottom 12 bits of \e *pui16Tag when performing either perfect or hash -//! filtering of VLAN frames. If this flag is absent, all 16 bits of the frame -//! tag are examined when filtering. If this flag is set and \e *pui16Tag has -//! all bottom 12 bits clear, the receiver passes all frames with types -//! 0x8100 or 0x88A8 regardless of the tag values they contain. -// -//***************************************************************************** -uint32_t -EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui16Tag); - - // - // Read the VLAN tag register. - // - ui32Value = HWREG(ui32Base + EMAC_O_VLANTG); - - // - // Extract the VLAN tag from the register. - // - *pui16Tag = (ui32Value & EMAC_VLANTG_VL_M) >> EMAC_VLANTG_VL_S; - - // - // Return the configuration flags. - // - return(ui32Value & ~EMAC_VLANTG_VL_M); -} - -//***************************************************************************** -// -//! Sets options related to transmission of VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui16Tag is the VLAN tag to be used when inserting or replacing tags -//! in transmitted frames. -//! \param ui32Config determines the VLAN-related processing performed by -//! the transmitter. -//! -//! This function is used to configure transmitter options relating to -//! IEEE 802.1Q VLAN tagging. The transmitter may be set to insert tagging -//! into untagged frames or replace existing tags with new values. -//! -//! The \e ui16Tag parameter contains the VLAN tag to be used in outgoing -//! tagged frames. The \e ui32Config parameter is a logical OR of the -//! following labels: -//! -//! - \b EMAC_VLAN_TX_SVLAN uses the S-VLAN type (0x88A8) when inserting or -//! replacing tags in transmitted frames. If this label is absent, C-VLAN -//! type (0x8100) is used. -//! - \b EMAC_VLAN_TX_USE_VLC informs the transmitter that the VLAN tag -//! handling should be defined by the VLAN control (VLC) value provided in -//! this function call. If this tag is absent, VLAN handling is controlled -//! by fields in the transmit descriptor. -//! -//! If \b EMAC_VLAN_TX_USE_VLC is set, one of the following four labels -//! must also be included to define the transmit VLAN tag handling: -//! -//! - \b EMAC_VLAN_TX_VLC_NONE instructs the transmitter to perform no VLAN -//! tag insertion, deletion or replacement. -//! - \b EMAC_VLAN_TX_VLC_DELETE instructs the transmitter to remove VLAN -//! tags from all transmitted frames that contain them. As a result, bytes -//! 13, 14, 15 and 16 are removed from all frames with types 0x8100 or 0x88A8. -//! - \b EMAC_VLAN_TX_VLC_INSERT instructs the transmitter to insert a VLAN -//! type and tag into all outgoing frames regardless of whether or not they -//! already contain a VLAN tag. -//! - \b EMAC_VLAN_TX_VLC_REPLACE instructs the transmitter to replace the -//! VLAN tag in all frames of type 0x8100 or 0x88A8 with the value provided to -//! this function in the \e ui16Tag parameter. -//! -//! \return None -// -//***************************************************************************** -void -EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the VLAN Tag Inclusion or Replacement register. - // - HWREG(ui32Base + EMAC_O_VLNINCREP) = - ui32Config | ((uint32_t)ui16Tag << EMAC_VLNINCREP_VLT_S); -} - -//***************************************************************************** -// -//! Returns currently-selected options related to transmission of VLAN-tagged -//! frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param pui16Tag points to storage that is written with the VLAN tag -//! currently being used for insertion or replacement. -//! -//! This function returns information on the current settings related to VLAN -//! tagging of transmitted frames. -//! -//! \sa EMACVLANTxConfigSet() -//! -//! \return Returns flags describing the current VLAN configuration relating -//! to frame transmission. The return value is a logical OR of the following -//! values: -//! -//! - \b EMAC_VLAN_TX_SVLAN indicates that the S-VLAN type (0x88A8) is -//! being used when inserting or replacing tags in transmitted frames. If -//! this label is absent, C-VLAN type (0x8100) is being used. -//! - \b EMAC_VLAN_TX_USE_VLC indicates that the transmitter is processing -//! VLAN frames according to the VLAN control (VLC) value returned here. If -//! this tag is absent, VLAN handling is controlled by fields in the transmit -//! descriptor. -//! -//! If \b EMAC_VLAN_TX_USE_VLC is returned, one of the following four labels -//! is also included to define the transmit VLAN tag handling. Note that this -//! value may be extracted from the return value using the mask \b -//! EMAC_VLAN_TX_VLC_MASK. -//! -//! - \b EMAC_VLAN_TX_VLC_NONE indicates that the transmitter is not -//! performing VLAN tag insertion, deletion or replacement. -//! - \b EMAC_VLAN_TX_VLC_DELETE indicates that the transmitter is removing -//! VLAN tags from all transmitted frames which contain them. -//! - \b EMAC_VLAN_TX_VLC_INSERT indicates that the transmitter is inserting -//! a VLAN type and tag into all outgoing frames regardless of whether or not -//! they already contain a VLAN tag. -//! - \b EMAC_VLAN_TX_VLC_REPLACE indicates that the transmitter is replacing -//! the VLAN tag in all transmitted frames of type 0x8100 or 0x88A8 with the -//! value returned in \e *pui16Tag. -// -//***************************************************************************** -uint32_t -EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pui16Tag); - - // - // Read the VLAN Tag Inclusion or Replacement register. - // - ui32Value = HWREG(ui32Base + EMAC_O_VLNINCREP); - - // - // Extract the tag. - // - *pui16Tag = (uint16_t)((ui32Value & EMAC_VLNINCREP_VLT_M) >> - EMAC_VLNINCREP_VLT_S); - - // - // Return the configuration flags. - // - return(ui32Value & ~EMAC_VLNINCREP_VLT_M); -} - -//***************************************************************************** -// -//! Returns the bit number to set in the VLAN hash filter corresponding to a -//! given tag. -//! -//! \param ui16Tag is the VLAN tag for which the hash filter bit number is to -//! be determined. -//! -//! This function may be used to determine which bit in the VLAN hash filter -//! to set to describe a given 12- or 16-bit VLAN tag. The returned value is -//! a 4-bit value indicating the bit number to set within the 16-bit VLAN -//! hash filter. For example, if 0x02 is returned, this indicates that bit -//! 2 of the hash filter must be set to pass the supplied VLAN tag. -//! -//! \return Returns the bit number to set in the VLAN hash filter to describe -//! the passed tag. -// -//***************************************************************************** -uint32_t -EMACVLANHashFilterBitCalculate(uint16_t ui16Tag) -{ - uint32_t ui32CRC, ui32Mask, ui32Loop; - - // - // Calculate the CRC for the MAC address. - // - ui32CRC = Crc32(0xFFFFFFFF, (uint8_t *)&ui16Tag, 2); - ui32CRC ^= 0xFFFFFFFF; - - // - // Determine the hash bit to use from the calculated CRC. This is the - // top 4 bits of the reversed CRC (or the bottom 4 bits of the calculated - // CRC with the bit order of those 4 bits reversed). - // - ui32Mask = 0; - - // - // Reverse the order of the bottom 4 bits of the calculated CRC. - // - for(ui32Loop = 0; ui32Loop < 4; ui32Loop++) - { - ui32Mask <<= 1; - ui32Mask |= (ui32CRC & 1); - ui32CRC >>= 1; - } - - // - // Return the final hash filter bit index. - // - return(ui32Mask); -} - -//***************************************************************************** -// -//! Sets the hash filter used to control reception of VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Hash is the hash filter value to set. -//! -//! This function allows the VLAG tag hash filter to be set. By using hash -//! filtering, several different VLAN tags can be filtered very easily at the -//! cost of some false positive results that must be removed by software. -//! -//! The hash filter value passed in \e ui32Hash may be built up by calling -//! EMACVLANHashFilterBitCalculate() for each VLAN tag that is to pass the -//! filter and then set each of the bits for which the numbers are returned by -//! that function. Care must be taken when clearing bits in the hash filter -//! due to the fact that there is a many-to-one correspondence between VLAN -//! tags and hash filter bits. -//! -//! \return None -// -//***************************************************************************** -void -EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Write the VLAN Hash Table register. - // - HWREG(ui32Base + EMAC_O_VLANHASH) = ui32Hash; -} - -//***************************************************************************** -// -//! Returns the current value of the hash filter used to control reception of -//! VLAN-tagged frames. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function allows the current VLAN tag hash filter value to be returned. -//! Additional VLAN tags may be added to this filter by setting the appropriate -//! bits, determined by calling EMACVLANHashFilterBitCalculate(), and then -//! calling EMACVLANHashFilterSet() to set the new filter value. -//! -//! \return Returns the current value of the VLAN hash filter. -// -//***************************************************************************** -uint32_t -EMACVLANHashFilterGet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Return the VLAN Hash Table register. - // - return(HWREG(ui32Base + EMAC_O_VLANHASH)); -} - -//***************************************************************************** -// -//! Sets values defining up to four frames used to trigger a remote wake-up. -//! -//! \param ui32Base is the base address of the controller. -//! \param pFilter points to the structure containing remote wake-up frame -//! filter information. -//! -//! This function may be used to define up to four different frames that -//! are considered by the Ethernet MAC to be remote wake-up signals. The -//! data passed to the function describes a wake-up frame in terms of a CRC -//! calculated on up to 31 payload bytes in the frame. The actual bytes used -//! in the CRC calculation are defined by means of a bit mask where a ``1'' -//! indicates that a byte in the frame should contribute to the CRC -//! calculation and a ``0'' indicates that the byte should be skipped, as well -//! as an offset from the start of the frame to the payload byte that represents -//! the first byte in the 31-byte CRC-checked sequence. -//! -//! The \e pFilter parameter points to a structure containing the information -//! necessary to set up the filters. This structure contains the following -//! fields, each of which is replicated 4 times, once for each possible wake-up -//! frame: -//! -//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte -//! sequence within the frame should contribute to the CRC calculation or not. -//! A 1 indicates that the byte should contribute to the calculation, a 0 -//! causes the byte to be skipped. -//! - \b pui8Command contains flags defining whether this filter is enabled -//! and, if so, whether it refers to unicast or multicast packets. Valid -//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b -//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or -//! \b EMAC_RWU_FILTER_DISABLE. -//! - \b pui8Offset defines the zero-based index of the byte within the frame -//! at which CRC checking defined by \b pui32ByteMask begins. -//! Alternatively, this value can be thought of as the number of bytes in the -//! frame that the MAC skips before accumulating the CRC based on the pattern -//! in \b pui32ByteMask. -//! - \b pui16CRC provides the value of the calculated CRC for a valid remote -//! wake-up frame. If the incoming frame is processed according to the filter -//! values provided and the final CRC calculation equals this value, the -//! frame is considered to be a valid remote wake-up frame. -//! -//! Note that this filter uses CRC16 rather than CRC32 as used in frame -//! checksums. The required CRC uses a direct algorithm with polynomial 0x8005, -//! initial seed value 0xFFFF, no final XOR and reversed data order. CRCs -//! for use in this function may be determined using the online calculator -//! found at http://www.zorc.breitbandkatze.de/crc.html. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, - const tEMACWakeUpFrameFilter *pFilter) -{ - uint32_t *pui32Data; - uint32_t ui32Loop; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pFilter); - - // - // Make sure that the internal register counter for the frame filter - // is reset. This bit automatically resets after 1 clock cycle. - // - HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST; - - // - // Get a word pointer to the supplied structure. - // - pui32Data = (uint32_t *)pFilter; - - // - // Write the 8 words of the wake-up filter definition to the hardware. - // - for(ui32Loop = 0; ui32Loop < 8; ui32Loop++) - { - // - // Write a word of the filter definition. - // - HWREG(ui32Base + EMAC_O_RWUFF) = pui32Data[ui32Loop]; - } -} - -//***************************************************************************** -// -//! Returns the current remote wake-up frame filter configuration. -//! -//! \param ui32Base is the base address of the controller. -//! \param pFilter points to the structure that is written with the current -//! remote wake-up frame filter information. -//! -//! This function may be used to read the current wake-up frame filter -//! settings. The data returned by the function describes wake-up frames in -//! terms of a CRC calculated on up to 31 payload bytes in the frame. The -//! actual bytes used in the CRC calculation are defined by means of a bit mask -//! where a ``1'' indicates that a byte in the frame should contribute to the -//! CRC calculation and a ``0'' indicates that the byte should be skipped, and -//! an offset from the start of the frame to the payload byte that represents -//! the first byte in the 31-byte CRC-checked sequence. -//! -//! The \e pFilter parameter points to storage that is written with a -//! structure containing the information defining the frame filters. This -//! structure contains the following fields, each of which is replicated 4 -//! times, once for each possible wake-up frame: -//! -//! - \b pui32ByteMask defines whether a given byte in the chosen 31-byte -//! sequence within the frame should contribute to the CRC calculation or not. -//! A 1 indicates that the byte should contribute to the calculation, a 0 -//! causes the byte to be skipped. -//! - \b pui8Command contains flags defining whether this filter is enabled -//! and, if so, whether it refers to unicast or multicast packets. Valid -//! values are one of \b EMAC_RWU_FILTER_MULTICAST or \b -//! EMAC_RWU_FILTER_UNICAST ORed with one of \b EMAC_RWU_FILTER_ENABLE or -//! \b EMAC_RWU_FILTER_DISABLE. -//! - \b pui8Offset defines the zero-based index of the byte within the frame -//! at which CRC checking defined by \b pui32ByteMask begins. -//! Alternatively, this value can be thought of as the number of bytes in the -//! frame that the MAC skips before accumulating the CRC based on the pattern -//! in \b pui32ByteMask. -//! - \b pui16CRC provides the value of the calculated CRC for a valid remote -//! wake-up frame. If the incoming frame is processed according to the filter -//! values provided and the final CRC calculation equals this value, the -//! frame is considered to be a valid remote wake-up frame. -//! -//! Note that this filter uses CRC16 rather than CRC32 as used in frame -//! checksums. -//! -//! \return None. -// -//***************************************************************************** -void -EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, - tEMACWakeUpFrameFilter *pFilter) -{ - uint32_t *pui32Data; - uint32_t ui32Loop; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(pFilter); - - // - // Make sure that the internal register counter for the frame filter - // is reset. This bit automatically resets after 1 clock cycle. - // - HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST; - - // - // Get a word pointer to the supplied structure. - // - pui32Data = (uint32_t *)pFilter; - - // - // Read the 8 words of the wake-up filter definition from the hardware. - // - for(ui32Loop = 0; ui32Loop < 8; ui32Loop++) - { - // - // Read a word of the filter definition. - // - pui32Data[ui32Loop] = HWREG(ui32Base + EMAC_O_RWUFF); - } -} - -//***************************************************************************** -// -//! Sets the Ethernet MAC remote wake-up configuration. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Flags defines which types of frame should trigger a remote -//! wake-up and allows the MAC to be put into power-down mode. -//! -//! This function allows the MAC's remote wake-up features to be configured, -//! determining which types of frame should trigger a wake-up event and -//! allowing an application to place the MAC in power-down mode. In this -//! mode, the MAC ignores all received frames until one matching a -//! configured remote wake-up frame is received, at which point the MAC -//! automatically exits power-down mode and continues to receive frames. -//! -//! The \e ui32Flags parameter is a logical OR of the following flags: -//! -//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE instructs the MAC to wake up when any -//! unicast frame matching the MAC destination address filter is received. -//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE instructs the MAC to wake up when any -//! received frame matches the remote wake-up filter configured via a call -//! to EMACRemoteWakeUpFrameFilterSet(). -//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE instructs the MAC to wake up when a -//! standard Wake-on-LAN "magic packet" is received. The magic packet contains -//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination -//! MAC address. -//! - \b EMAC_PMT_POWER_DOWN instructs the MAC to enter power-down mode and -//! wait for an incoming frame matching the remote wake-up frames as described -//! by other flags and via the remote wake-up filter. This flag should only -//! set set if at least one other flag is specified to configure a wake-up -//! frame type. -//! -//! When the MAC is in power-down mode, software may exit the mode by calling -//! this function with the \b EMAC_PMT_POWER_DOWN flag absent from \e ui32Flags. -//! If a configured wake-up frame is received while in power-down mode, the -//! \b EMAC_INT_POWER_MGMNT interrupt is signaled and may be cleared by reading -//! the status using EMACPowerManagementStatusGet(). -//! -//! \note While it is possible to gate the clock to the MAC while it is in -//! power-down mode, doing so prevents the reading of the registers required -//! to determine the interrupt status and also prevents power-down mode from -//! exiting via another call to this function. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPowerManagementControlSet(uint32_t ui32Base, uint32_t ui32Flags) -{ - uint32_t ui32Value; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - ASSERT(~(ui32Flags & ~(EMAC_PMT_GLOBAL_UNICAST_ENABLE | - EMAC_PMT_WAKEUP_PACKET_ENABLE | - EMAC_PMT_MAGIC_PACKET_ENABLE | - EMAC_PMT_POWER_DOWN))); - - // - // Read the control/status register, clear all the bits we can set, mask - // in the new values then rewrite the new register value. - // - ui32Value = HWREG(ui32Base + EMAC_O_PMTCTLSTAT); - ui32Value &= ~(EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN | - EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN); - ui32Value |= ui32Flags; - HWREG(ui32Base + EMAC_O_PMTCTLSTAT) = ui32Value; -} - -//***************************************************************************** -// -//! Queries the current Ethernet MAC remote wake-up configuration. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function allows the MAC's remote wake-up settings to be queried. -//! These settings determine which types of frame should trigger a remote -//! wake-up event -//! -//! \return Returns a logical OR of the following flags: -//! -//! - \b EMAC_PMT_GLOBAL_UNICAST_ENABLE indicates that the MAC wakes up when -//! any unicast frame matching the MAC destination address filter is received. -//! - \b EMAC_PMT_WAKEUP_PACKET_ENABLE indicates that the MAC wakes up when any -//! received frame matches the remote wake-up filter configured via a call -//! to EMACRemoteWakeUpFrameFilterSet(). -//! - \b EMAC_PMT_MAGIC_PACKET_ENABLE indicates that the MAC wakes up when a -//! standard Wake-on-LAN "magic packet" is received. The magic packet contains -//! 6 bytes of 0xFF followed immediately by 16 repetitions of the destination -//! MAC address. -//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down -//! mode and is waiting for an incoming frame matching the remote wake-up -//! frames as described by other returned flags and via the remote wake-up -//! filter. -// -//***************************************************************************** -uint32_t -EMACPowerManagementControlGet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Read the control/status register and mask off the control bits to return - // them to the caller. - // - return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) & - (EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN | - EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN)); -} - -//***************************************************************************** -// -//! Queries the current Ethernet MAC remote wake-up status. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function returns information on the remote wake-up state of the -//! Ethernet MAC. If the MAC has been woken up since the last call, the -//! returned value indicates the type of received frame that caused the MAC -//! to exit power-down state. -//! -//! \return Returns a logical OR of the following flags: -//! -//! - \b EMAC_PMT_POWER_DOWN indicates that the MAC is currently in power-down -//! mode. -//! - \b EMAC_PMT_WAKEUP_PACKET_RECEIVED indicates that the MAC exited -//! power-down mode due to a remote wake-up frame being received. This -//! function call clears this flag. -//! - \b EMAC_PMT_MAGIC_PACKET_RECEIVED indicates that the MAC exited -//! power-down mode due to a wake-on-LAN magic packet being received. This -//! function call clears this flag. -// -//***************************************************************************** -uint32_t -EMACPowerManagementStatusGet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Read the control/status register and mask off the status bits to return - // them to the caller. - // - return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) & - (EMAC_PMTCTLSTAT_WUPRX | EMAC_PMTCTLSTAT_MGKPRX | - EMAC_PMTCTLSTAT_PWRDWN)); -} - -//***************************************************************************** -// -//! Enables the wake-on-LAN feature of the MAC controller. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to enable the wake-on-LAN feature of the MAC -//! controller. It is done by first checking if the transmit path is idle and -//! disabling the trasnmitter and the transmit DMA controller. Then it checks -//! if any data from the network is being actively received and if not then it -//! disables the receive DMA controller. -//! -//! \return None. -// -//***************************************************************************** -void -EMACWoLEnter(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Check if the Transmit interrupt bit is clear. - // - while(HWREG(ui32Base + EMAC_O_DMARIS) == EMAC_DMARIS_TI) - { - } - - // - // Disable transmission in the MAC configuration register. - // - HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; - - // - // Disable the MAC transmit path in the opmode register. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; - - // - // Check if the Receive FIFO is empty. - // - while((HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_RX_FIFO_LEVEL_MASK) == - EMAC_STATUS_RX_FIFO_EMPTY) - { - } - - // - // Disable the MAC receive path. - // - HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; -} - -//***************************************************************************** -// -//! Configures the LPI timers and control register. -//! -//! \param ui32Base is the base address of the controller. -//! \param bLPIConfig is state of LPI trasnmit automate bit. -//! \param ui16LPILSTimer is the value of LS timer in milli-seconds. -//! \param ui16LPITWTimer is the value of TW timer in micro-seconds. -//! -//! This function is used to configure the LPI timer and control registers when -//! the link is established as EEE mode or when the link is lost. When the link -//! is established as EEE, then \e ui16LPILSTimer is programmed as the link -//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait -//! timer value. The parameter \e bLPIConfig is used to decide if the transmit -//! path must be automated or should be under user control. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer, - uint16_t ui16LPITWTimer) -{ - uint32_t ui32TimerValue; - - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - ui32TimerValue = ((ui16LPILSTimer << EMAC_LPITIMERCTL_LST_S) & - EMAC_LPITIMERCTL_LST_M); - ui32TimerValue |= ui16LPITWTimer & EMAC_LPITIMERCTL_TWT_M; - - // - // Update the LPI Timer. - // - HWREG(ui32Base + EMAC_O_LPITIMERCTL) = ui32TimerValue; - - // - // Configure the LPI Control registers. - // - if(bLPIConfig) - { - HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPITXA; - } - else - { - HWREG(ui32Base + EMAC_O_LPICTLSTAT) = 0x0; - } -} - -//***************************************************************************** -// -//! Enables the transmit path for LPI mode entry. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to enable the transmit path in LPI mode when there -//! is no more data to be transmitted by the MAC controller. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPIEnter(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPIEN; -} - -//***************************************************************************** -// -//! Returns the status of the LPI link. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to read the status of the transmit and receive -//! path when the link is configured in LPI mode. -//! -//! \return Returns the lower 16 bits of the LPI Control and Status register. -// -//***************************************************************************** -uint16_t -EMACLPIStatus(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Configure the LPI Control registers. - // - return(HWREG(ui32Base + EMAC_O_LPICTLSTAT) & 0xFFFF); -} - -//***************************************************************************** -// -//! Sets the link status of the external PHY. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to set the link status of the external PHY when the -//! link is established in EEE mode. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPILinkSet(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Configure the LPI Control registers. - // - HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_PLS; -} - -//***************************************************************************** -// -//! Clears the link status of the external PHY. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function is used to clear the link status of the external PHY when the -//! link is lost due to a disconnect or EEE mode link is not established. -//! -//! \return None. -// -//***************************************************************************** -void -EMACLPILinkClear(uint32_t ui32Base) -{ - // - // Parameter sanity check. - // - ASSERT(ui32Base == EMAC0_BASE); - - // - // Configure the LPI Control registers. - // - HWREG(ui32Base + EMAC_O_LPICTLSTAT) &= ~(EMAC_LPICTLSTAT_PLS); -} - -//***************************************************************************** -// -//! Writes a value to an extended PHY register in MMD address space. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! \param ui16Value is the value to write to the register. -//! -//! When uhen connected to an external PHY supporting extended registers in MMD -//! address space, this function allows a value to be written to the MMD -//! register specified by \e ui16RegAddr. -//! -//! \return None. -// -//***************************************************************************** -void -EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, - uint16_t ui16Data) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - - // - // Set the address of the register we're about to write. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); - - // - // Write the extended register value. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, - (0x4000 | DEV_ADDR(ui16RegAddr))); - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, ui16Data); -} - -//***************************************************************************** -// -//! Reads from an extended PHY register in MMD address space. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8PhyAddr is the physical address of the PHY to access. -//! \param ui16RegAddr is the address of the PHY extended register to be -//! accessed. -//! -//! When connected to an external PHY supporting extended registers, this -//! this function returns the contents of the MMD register specified by -//! \e ui16RegAddr. -//! -//! \return Returns the 16-bit value read from the PHY. -// -//***************************************************************************** -uint16_t -EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr) -{ - // - // Parameter sanity check. - // - ASSERT(ui8PhyAddr < 32); - - // - // Set the address of the register we're about to read. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); - - // - // Read the extended register value. - // - EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, - (0x4000 | DEV_ADDR(ui16RegAddr))); - return(EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_ADDAR)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/emac.h b/bsp/tm4c129x-dk/libraries/driverlib/emac.h deleted file mode 100644 index f82919c8c0..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/emac.h +++ /dev/null @@ -1,1041 +0,0 @@ -//***************************************************************************** -// -// emac.h - Defines and Macros for the Ethernet module on Snowflake-class -// devices. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_EMAC_H__ -#define __DRIVERLIB_EMAC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup emac_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// The physical address of the internal PHY. This should be in hw_emac.h. -// -//***************************************************************************** -#define EMAC_PHY_ADDR 0 - -//***************************************************************************** -// -// Helper Macros for Ethernet Processing -// -//***************************************************************************** -// -// htonl/ntohl - Big endian/little endian byte swapping macros for 32-bit -// values. -// -//***************************************************************************** -#ifndef htonl - #define htonl(a) \ - ((((a) >> 24) & 0x000000ff) | \ - (((a) >> 8) & 0x0000ff00) | \ - (((a) << 8) & 0x00ff0000) | \ - (((a) << 24) & 0xff000000)) -#endif - -#ifndef ntohl - #define ntohl(a) htonl((a)) -#endif - -//***************************************************************************** -// -// htons/ntohs - Big endian/little endian byte swapping macros for 16-bit -// values. -// -//***************************************************************************** -#ifndef htons - #define htons(a) \ - ((((a) >> 8) & 0x00ff) | \ - (((a) << 8) & 0xff00)) -#endif - -#ifndef ntohs - #define ntohs(a) htons((a)) -#endif - -//***************************************************************************** -// -// Forward reference to the Ethernet DMA descriptor structure. -// -//***************************************************************************** -typedef struct tEMACDMADescriptor tEMACDMADescriptor; - -//***************************************************************************** -// -//! A union used to describe the two overlapping fields forming the third -//! word of the Ethernet DMA descriptor. -// -//***************************************************************************** -typedef union -{ - // - //! When DMA descriptors are used in chained mode, this field is used to - //! provide a link to the next descriptor. - // - tEMACDMADescriptor *pLink; - - // - //! When the DMA descriptors are unchained, this field may be used to point - //! to a second buffer containing data for transmission or providing - //! storage for a received frame. - // - void *pvBuffer2; -} -tEMACDES3; - -//***************************************************************************** -// -//! A structure defining a single Ethernet DMA buffer descriptor. -// -//***************************************************************************** -struct tEMACDMADescriptor -{ - // - //! The first DMA descriptor word contains various control and status bits - //! depending upon whether the descriptor is in the transmit or receive - //! queue. Bit 31 is always the ``OWN'' bit which, when set, indicates - //! that the hardware has control of the descriptor. - // - volatile uint32_t ui32CtrlStatus; - - // - //! The second descriptor word contains information on the size of the - //! buffer or buffers attached to the descriptor and various additional - //! control bits. - // - volatile uint32_t ui32Count; - - // - //! The third descriptor word contains a pointer to the buffer containing - //! data to transmit or into which received data should be written. This - //! pointer must refer to a buffer in internal SRAM. Pointers to flash or - //! EPI-connected memory may not be used and will result in the MAC - //! reporting a bus error. - // - void *pvBuffer1; - - // - //! The fourth descriptor word contains either a pointer to the next - //! descriptor in the ring or a pointer to a second data buffer. The - //! meaning of the word is controlled by the ``CHAINED'' control bit which - //! appears in the first word of the transmit descriptor or the second - //! word of the receive descriptor. - //! - tEMACDES3 DES3; - - // - //! The fifth descriptor word is reserved for transmit descriptors but - //! used to report extended status in a receive descriptor. - // - volatile uint32_t ui32ExtRxStatus; - - // - //! The sixth descriptor word is reserved for both transmit and receive - //! descriptors. - // - uint32_t ui32Reserved; - - // - //! The seventh descriptor word contains the low 32 bits of the 64-bit - //! timestamp captured for transmitted or received data. The value is set - //! only when the transmitted or received data contains the end of a - //! packet. Availability of the timestamp is indicated via a status bit - //! in the first descriptor word. - // - volatile uint32_t ui32IEEE1588TimeLo; - - // - //! The eighth descriptor word contains the high 32 bits of the 64-bit - //! timestamp captured for transmitted or received data. - // - volatile uint32_t ui32IEEE1588TimeHi; -}; - -//***************************************************************************** -// -// Fields found in the DES0 word of the transmit descriptor (ui32CtrlStatus in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES0_TX_CTRL_OWN 0x80000000 -#define DES0_TX_CTRL_INTERRUPT 0x40000000 -#define DES0_TX_CTRL_LAST_SEG 0x20000000 -#define DES0_TX_CTRL_FIRST_SEG 0x10000000 - -// -// This value indicates that the MAC should not append a CRC to transmitted -// packets. If used with DES0_TX_CTRL_REPLACE_CRC, the last 4 bytes of the -// packet passed to the transmitter are replaced with a newly calculated CRC. -// If DES0_TX_CTRL_REPLACE_CRC is not specified, it is assumed that packets -// transmitted have valid CRCs precomputed and included in the frame data. -// -// If DES0_TX_CTRL_DISABLE_CRC is not specified, the MAC will calculate the -// CRC for all frames transmitted and append this value as the 4-byte FCS -// after the last data byte in the frame. -// -#define DES0_TX_CTRL_DISABLE_CRC 0x08000000 -#define DES0_TX_CTRL_DISABLE_PADDING 0x04000000 -#define DES0_TX_CTRL_ENABLE_TS 0x02000000 - -// -// This value is only valid if used alongside DES0_TX_CTRL_DISABLE_CRC. When -// specified, the MAC will replace the last 4 bytes of a transmitted frame -// with a newly calculated CRC. -// -#define DES0_TX_CTRL_REPLACE_CRC 0x01000000 -#define DES0_TX_CTRL_CHKSUM_M 0x00C00000 -#define DES0_TX_CTRL_NO_CHKSUM 0x00000000 -#define DES0_TX_CTRL_IP_HDR_CHKSUM 0x00400000 -#define DES0_TX_CTRL_IP_HDR_PAY_CHKSUM 0x00800000 -#define DES0_TX_CTRL_IP_ALL_CKHSUMS 0x00C00000 -#define DES0_TX_CTRL_END_OF_RING 0x00200000 -#define DES0_TX_CTRL_CHAINED 0x00100000 -#define DES0_TX_CTRL_VLAN_M 0x000C0000 -#define DES0_TX_CTRL_VLAN_NONE 0x00000000 -#define DES0_TX_CTRL_VLAN_REMOVE 0x00040000 -#define DES0_TX_CTRL_VLAN_INSERT 0x00080000 -#define DES0_TX_CTRL_VLAN_REPLACE 0x000C0000 -#define DES0_TX_STAT_TS_CAPTURED 0x00020000 -#define DES0_TX_STAT_IPH_ERR 0x00010000 -#define DES0_TX_STAT_ERR 0x00008000 -#define DES0_TX_STAT_JABBER_TO 0x00004000 -#define DES0_TX_STAT_FLUSHED 0x00002000 -#define DES0_TX_STAT_PAYLOAD_ERR 0x00001000 -#define DES0_TX_STAT_CARRIER_LOST 0x00000800 -#define DES0_TX_STAT_NO_CARRIER 0x00000400 -#define DES0_TX_STAT_TX_L_COLLISION 0x00000200 -#define DES0_TX_STAT_E_COLLISION 0x00000100 -#define DES0_TX_STAT_VLAN_FRAME 0x00000080 -#define DES0_TX_STAT_COL_COUNT_M 0x00000078 -#define DES0_TX_STAT_COL_COUNT_S 3 -#define DES0_TX_STAT_E_DEFERRAL 0x00000004 -#define DES0_TX_STAT_UNDERFLOW 0x00000002 -#define DES0_TX_STAT_DEFERRED 0x00000001 - -//***************************************************************************** -// -// Fields found in the DES1 word of the transmit descriptor (ui32Count in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES1_TX_CTRL_SADDR_MAC1 0x80000000 -#define DES1_TX_CTRL_SADDR_M 0x60000000 -#define DES1_TX_CTRL_SADDR_NONE 0x00000000 -#define DES1_TX_CTRL_SADDR_INSERT 0x20000000 -#define DES1_TX_CTRL_SADDR_REPLACE 0x40000000 -#define DES1_TX_CTRL_BUFF2_SIZE_M 0x1FFF0000 -#define DES1_TX_CTRL_BUFF1_SIZE_M 0x00001FFF -#define DES1_TX_CTRL_BUFF2_SIZE_S 16 -#define DES1_TX_CTRL_BUFF1_SIZE_S 0 - -//***************************************************************************** -// -// Fields found in the DES0 word of the receive descriptor (ui32CtrlStatus in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES0_RX_CTRL_OWN 0x80000000 -#define DES0_RX_STAT_DEST_ADDR_FAIL 0x40000000 -#define DES0_RX_STAT_FRAME_LENGTH_M 0x3FFF0000 -#define DES0_RX_STAT_FRAME_LENGTH_S 16 -#define DES0_RX_STAT_ERR 0x00008000 -#define DES0_RX_STAT_DESCRIPTOR_ERR 0x00004000 -#define DES0_RX_STAT_SRC_ADDR_FAIL 0x00002000 -#define DES0_RX_STAT_LENGTH_ERR 0x00001000 -#define DES0_RX_STAT_OVERFLOW 0x00000800 -#define DES0_RX_STAT_VLAN_TAG 0x00000400 -#define DES0_RX_STAT_FIRST_DESC 0x00000200 -#define DES0_RX_STAT_LAST_DESC 0x00000100 -#define DES0_RX_STAT_TS_AVAILABLE 0x00000080 -#define DES0_RX_STAT_RX_L_COLLISION 0x00000040 -#define DES0_RX_STAT_FRAME_TYPE 0x00000020 -#define DES0_RX_STAT_WDOG_TIMEOUT 0x00000010 -#define DES0_RX_STAT_RX_ERR 0x00000008 -#define DES0_RX_STAT_DRIBBLE_ERR 0x00000004 -#define DES0_RX_STAT_CRC_ERR 0x00000002 -#define DES0_RX_STAT_MAC_ADDR 0x00000001 -#define DES0_RX_STAT_EXT_AVAILABLE 0x00000001 - -//***************************************************************************** -// -// Fields found in the DES1 word of the receive descriptor (ui32Count in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES1_RX_CTRL_DISABLE_INT 0x80000000 -#define DES1_RX_CTRL_BUFF2_SIZE_M 0x1FFF0000 -#define DES1_RX_CTRL_BUFF2_SIZE_S 16 -#define DES1_RX_CTRL_END_OF_RING 0x00008000 -#define DES1_RX_CTRL_CHAINED 0x00004000 -#define DES1_RX_CTRL_BUFF1_SIZE_M 0x00001FFF -#define DES1_RX_CTRL_BUFF1_SIZE_S 0 - -//***************************************************************************** -// -// Fields found in the DES4 word of the receive descriptor (ui32ExtRxStatus in -// tEMACDMADescriptor) -// -//***************************************************************************** -#define DES4_RX_STAT_TS_DROPPED 0x00004000 -#define DES4_RX_STAT_PTP_VERSION2 0x00002000 -#define DES4_RX_STAT_PTP_TYPE_ETH 0x00001000 -#define DES4_RX_STAT_PTP_TYPE_UDP 0x00000000 -#define DES4_RX_STAT_PTP_MT_M 0x00000F00 -#define DES4_RX_STAT_PTP_MT_NONE 0x00000000 -#define DES4_RX_STAT_PTP_MT_SYNC 0x00000100 -#define DES4_RX_STAT_PTP_MT_FOLLOW_UP 0x00000200 -#define DES4_RX_STAT_PTP_MT_DELAY_REQ 0x00000300 -#define DES4_RX_STAT_PTP_MT_DELAY_RESP 0x00000400 -#define DES4_RX_STAT_PTP_MT_PDELAY_REQ 0x00000500 -#define DES4_RX_STAT_PTP_MT_PDELAY_RESP 0x00000600 -#define DES4_RX_STAT_PTP_MT_PDELAY_RFU 0x00000700 -#define DES4_RX_STAT_PTP_MT_ANNOUNCE 0x00000800 -#define DES4_RX_STAT_PTP_MT_SIGNALLING 0x00000A00 -#define DES4_RX_STAT_PTP_MT_RESERVED 0x00000F00 -#define DES4_RX_STAT_IPV6 0x00000080 -#define DES4_RX_STAT_IPV4 0x00000040 -#define DES4_RX_STAT_IP_CHK_BYPASSED 0x00000020 -#define DES4_RX_STAT_IP_PAYLOAD_ERR 0x00000010 -#define DES4_RX_STAT_IP_HEADER_ERR 0x00000008 -#define DES4_RX_STAT_PAYLOAD_M 0x00000007 -#define DES4_RX_STAT_PAYLOAD_UNKNOWN 0x00000000 -#define DES4_RX_STAT_PAYLOAD_UDP 0x00000001 -#define DES4_RX_STAT_PAYLOAD_TCP 0x00000002 -#define DES4_RX_STAT_PAYLOAD_ICMP 0x00000003 - -//***************************************************************************** -// -// Values used in the ui32BusConfig parameter to EMACInit(). -// -//*************************************************************************** -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_M 0x30000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 0x00000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 0x10000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_3 0x20000000 -#define EMAC_BCONFIG_DMA_PRIO_WEIGHT_4 0x30000000 -#define EMAC_BCONFIG_TX_PRIORITY 0x08000000 -#define EMAC_BCONFIG_ADDR_ALIGNED 0x02000000 -#define EMAC_BCONFIG_PRIORITY_M 0x0000C000 -#define EMAC_BCONFIG_PRIORITY_1_1 (0 << 14) -#define EMAC_BCONFIG_PRIORITY_2_1 (1 << 14) -#define EMAC_BCONFIG_PRIORITY_3_1 (2 << 14) -#define EMAC_BCONFIG_PRIORITY_4_1 (3 << 14) -#define EMAC_BCONFIG_PRIORITY_FIXED 0x00000002 -#define EMAC_BCONFIG_FIXED_BURST 0x00010000 -#define EMAC_BCONFIG_MIXED_BURST 0x04000000 - -//***************************************************************************** -// -// Options used in the ui32Config parameter to EMACPHYConfigSet(). -// -//***************************************************************************** -#define EMAC_PHY_TYPE_INTERNAL 0x00000000 -#define EMAC_PHY_TYPE_EXTERNAL_MII 0x80000000 -#define EMAC_PHY_TYPE_EXTERNAL_RMII 0xC0000000 -#define EMAC_PHY_INT_NIB_TXERR_DET_DIS 0x01000000 -#define EMAC_PHY_INT_RX_ER_DURING_IDLE 0x00800000 -#define EMAC_PHY_INT_ISOLATE_MII_LLOSS 0x00400000 -#define EMAC_PHY_INT_LINK_LOSS_RECOVERY 0x00200000 -#define EMAC_PHY_INT_TDRRUN 0x00100000 -#define EMAC_PHY_INT_LD_ON_RX_ERR_COUNT 0x00040000 -#define EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT 0x00020000 -#define EMAC_PHY_INT_LD_ON_LOW_SNR 0x00010000 -#define EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY 0x00008000 -#define EMAC_PHY_INT_POLARITY_SWAP 0x00004000 -#define EMAC_PHY_INT_MDI_SWAP 0x00002000 -#define EMAC_PHY_INT_ROBUST_MDIX 0x00001000 -#define EMAC_PHY_INT_FAST_MDIX 0x00000800 -#define EMAC_PHY_INT_MDIX_EN 0x00000400 -#define EMAC_PHY_INT_FAST_RXDV_DETECT 0x00000200 -#define EMAC_PHY_INT_FAST_L_UP_DETECT 0x00000100 -#define EMAC_PHY_INT_EXT_FULL_DUPLEX 0x00000080 -#define EMAC_PHY_INT_FAST_AN_80_50_35 0x00000040 -#define EMAC_PHY_INT_FAST_AN_120_75_50 0x00000050 -#define EMAC_PHY_INT_FAST_AN_140_150_100 0x00000060 -#define EMAC_PHY_FORCE_10B_T_HALF_DUPLEX 0x00000000 -#define EMAC_PHY_FORCE_10B_T_FULL_DUPLEX 0x00000002 -#define EMAC_PHY_FORCE_100B_T_HALF_DUPLEX 0x00000004 -#define EMAC_PHY_FORCE_100B_T_FULL_DUPLEX 0x00000006 -#define EMAC_PHY_AN_10B_T_HALF_DUPLEX 0x00000008 -#define EMAC_PHY_AN_10B_T_FULL_DUPLEX 0x0000000A -#define EMAC_PHY_AN_100B_T_HALF_DUPLEX 0x0000000C -#define EMAC_PHY_AN_100B_T_FULL_DUPLEX 0x0000000E -#define EMAC_PHY_INT_HOLD 0x00000001 - -#define EMAC_PHY_TYPE_MASK 0xC0000000 - -//***************************************************************************** -// -// Options used in the ui32Config parameter to EMACConfigSet(). -// -//***************************************************************************** -#define EMAC_CONFIG_USE_MACADDR1 0x40000000 -#define EMAC_CONFIG_USE_MACADDR0 0x00000000 -#define EMAC_CONFIG_SA_FROM_DESCRIPTOR 0x00000000 -#define EMAC_CONFIG_SA_INSERT 0x20000000 -#define EMAC_CONFIG_SA_REPLACE 0x30000000 -#define EMAC_CONFIG_2K_PACKETS 0x08000000 -#define EMAC_CONFIG_STRIP_CRC 0x02000000 -#define EMAC_CONFIG_JABBER_DISABLE 0x00400000 -#define EMAC_CONFIG_JUMBO_ENABLE 0x00100000 -#define EMAC_CONFIG_IF_GAP_MASK 0x000E0000 -#define EMAC_CONFIG_IF_GAP_96BITS (0x0 << 17) -#define EMAC_CONFIG_IF_GAP_88BITS (0x1 << 17) -#define EMAC_CONFIG_IF_GAP_80BITS (0x2 << 17) -#define EMAC_CONFIG_IF_GAP_72BITS (0x3 << 17) -#define EMAC_CONFIG_IF_GAP_64BITS (0x4 << 17) -#define EMAC_CONFIG_IF_GAP_56BITS (0x5 << 17) -#define EMAC_CONFIG_IF_GAP_48BITS (0x6 << 17) -#define EMAC_CONFIG_IF_GAP_40BITS (0x7 << 17) -#define EMAC_CONFIG_CS_DISABLE 0x00010000 -#define EMAC_CONFIG_100MBPS 0x00004000 -#define EMAC_CONFIG_10MBPS 0x00000000 -#define EMAC_CONFIG_RX_OWN_DISABLE 0x00002000 -#define EMAC_CONFIG_LOOPBACK 0x00001000 -#define EMAC_CONFIG_FULL_DUPLEX 0x00000800 -#define EMAC_CONFIG_HALF_DUPLEX 0x00000000 -#define EMAC_CONFIG_CHECKSUM_OFFLOAD 0x00000400 -#define EMAC_CONFIG_RETRY_DISABLE 0x00000200 -#define EMAC_CONFIG_AUTO_CRC_STRIPPING 0x00000080 -#define EMAC_CONFIG_BO_MASK 0x00000060 -#define EMAC_CONFIG_BO_LIMIT_1024 (0x0 << 5) -#define EMAC_CONFIG_BO_LIMIT_256 (0x1 << 5) -#define EMAC_CONFIG_BO_LIMIT_16 (0x2 << 5) -#define EMAC_CONFIG_BO_LIMIT_2 (0x3 << 5) -#define EMAC_CONFIG_DEFERRAL_CHK_ENABLE 0x00000010 -#define EMAC_CONFIG_PREAMBLE_MASK 0x00000003 -#define EMAC_CONFIG_7BYTE_PREAMBLE 0x00000000 -#define EMAC_CONFIG_5BYTE_PREAMBLE 0x00000001 -#define EMAC_CONFIG_3BYTE_PREAMBLE 0x00000002 - -//***************************************************************************** -// -// Options used in the ui32ModeFlags parameter to EMACConfigSet(). -// -//***************************************************************************** -#define EMAC_MODE_KEEP_BAD_CRC 0x04000000 -#define EMAC_MODE_RX_STORE_FORWARD 0x02000000 -#define EMAC_MODE_RX_FLUSH_DISABLE 0x01000000 -#define EMAC_MODE_TX_STORE_FORWARD 0x00200000 -#define EMAC_MODE_TX_THRESHOLD_16_BYTES (7 << 14) -#define EMAC_MODE_TX_THRESHOLD_24_BYTES (6 << 14) -#define EMAC_MODE_TX_THRESHOLD_32_BYTES (5 << 14) -#define EMAC_MODE_TX_THRESHOLD_40_BYTES (4 << 14) -#define EMAC_MODE_TX_THRESHOLD_64_BYTES (0 << 14) -#define EMAC_MODE_TX_THRESHOLD_128_BYTES (1 << 14) -#define EMAC_MODE_TX_THRESHOLD_192_BYTES (2 << 14) -#define EMAC_MODE_TX_THRESHOLD_256_BYTES (3 << 14) -#define EMAC_MODE_RX_ERROR_FRAMES 0x00000080 -#define EMAC_MODE_RX_UNDERSIZED_FRAMES 0x00000040 -#define EMAC_MODE_RX_THRESHOLD_64_BYTES (0 << 3) -#define EMAC_MODE_RX_THRESHOLD_32_BYTES (1 << 3) -#define EMAC_MODE_RX_THRESHOLD_96_BYTES (2 << 3) -#define EMAC_MODE_RX_THRESHOLD_128_BYTES (3 << 3) -#define EMAC_MODE_OPERATE_2ND_FRAME 0x00000002 - -//***************************************************************************** -// -// These two values may be returned by EMACConfigGet() in the *pui32Config -// parameter. The transmitter and receiver are, however, enabled and disabled -// using independent functions, EMACTxEnable/Disable() and -// EMACRxEnable/Disable(). -// -//***************************************************************************** -#define EMAC_CONFIG_TX_ENABLED 0x00000008 -#define EMAC_CONFIG_RX_ENABLED 0x00000004 - -//***************************************************************************** -// -// These two values may be returned by EMACConfigGet() in the *pui32Mode -// parameter. The transmit and receive DMA channels are, however, enabled and -// disabled using independent functions, EMACTxEnable/Disable() and -// EMACRxEnable/Disable(). -// -//***************************************************************************** -#define EMAC_MODE_TX_DMA_ENABLED 0x00002000 -#define EMAC_MODE_RX_DMA_ENABLED 0x00000002 - -//***************************************************************************** -// -// These values may be passed to EMACFrameFilterSet() in the ui32FilterOpts -// parameter, and are returned by EMACFrameFilterGet(). -// -//***************************************************************************** -#define EMAC_FRMFILTER_RX_ALL 0x80000000 -#define EMAC_FRMFILTER_VLAN 0x00010000 -#define EMAC_FRMFILTER_HASH_AND_PERFECT 0x00000400 -#define EMAC_FRMFILTER_SADDR 0x00000200 -#define EMAC_FRMFILTER_INV_SADDR 0x00000100 -#define EMAC_FRMFILTER_PASS_MASK (0x03 << 6) -#define EMAC_FRMFILTER_PASS_NO_CTRL (0x00 << 6) -#define EMAC_FRMFILTER_PASS_NO_PAUSE (0x01 << 6) -#define EMAC_FRMFILTER_PASS_ALL_CTRL (0x02 << 6) -#define EMAC_FRMFILTER_PASS_ADDR_CTRL (0x03 << 6) -#define EMAC_FRMFILTER_BROADCAST 0x00000020 -#define EMAC_FRMFILTER_PASS_MULTICAST 0x00000010 -#define EMAC_FRMFILTER_INV_DADDR 0x00000008 -#define EMAC_FRMFILTER_HASH_MULTICAST 0x00000004 -#define EMAC_FRMFILTER_HASH_UNICAST 0x00000002 -#define EMAC_FRMFILTER_PROMISCUOUS 0x00000001 - -//***************************************************************************** -// -// Values which may be returned by EMACStatusGet(). -// -//***************************************************************************** -#define EMAC_STATUS_TX_NOT_EMPTY 0x01000000 -#define EMAC_STATUS_TX_WRITING_FIFO 0x00400000 -#define EMAC_STATUS_TRC_STATE_MASK 0x00300000 -#define EMAC_STATUS_TRC_STATE_IDLE (0x00 << 20) -#define EMAC_STATUS_TRC_STATE_READING (0x01 << 20) -#define EMAC_STATUS_TRC_STATE_WAITING (0x02 << 20) -#define EMAC_STATUS_TRC_STATE_STATUS (0x03 << 20) -#define EMAC_STATUS_TX_PAUSED 0x00080000 -#define EMAC_STATUS_TFC_STATE_MASK 0x00060000 -#define EMAC_STATUS_TFC_STATE_IDLE (0x00 << 17) -#define EMAC_STATUS_TFC_STATE_WAITING (0x01 << 17) -#define EMAC_STATUS_TFC_STATE_PAUSING (0x02 << 17) -#define EMAC_STATUS_TFC_STATE_WRITING (0x03 << 17) -#define EMAC_STATUS_MAC_NOT_IDLE 0x00010000 -#define EMAC_STATUS_RX_FIFO_LEVEL_MASK 0x00000300 -#define EMAC_STATUS_RX_FIFO_EMPTY (0x00 << 8) -#define EMAC_STATUS_RX_FIFO_BELOW (0x01 << 8) -#define EMAC_STATUS_RX_FIFO_ABOVE (0x02 << 8) -#define EMAC_STATUS_RX_FIFO_FULL (0x03 << 8) -#define EMAC_STATUS_RX_FIFO_STATE_MASK 0x00000060 -#define EMAC_STATUS_RX_FIFO_IDLE (0x00 << 5) -#define EMAC_STATUS_RX_FIFO_READING (0x01 << 5) -#define EMAC_STATUS_RX_FIFO_STATUS (0x02 << 5) -#define EMAC_STATUS_RX_FIFO_FLUSHING (0x03 << 5) -#define EMAC_STATUS_RWC_ACTIVE 0x00000010 -#define EMAC_STATUS_RPE_ACTIVE 0x00000001 - -//***************************************************************************** -// -// Values which may be returned by EMACDMAStateGet(). -// -//***************************************************************************** -#define EMAC_DMA_TXSTAT_MASK (0x07 << 20) -#define EMAC_DMA_TXSTAT_STOPPED (0x00 << 20) -#define EMAC_DMA_TXSTAT_RUN_FETCH_DESC (0x01 << 20) -#define EMAC_DMA_TXSTAT_RUN_WAIT_STATUS (0x02 << 20) -#define EMAC_DMA_TXSTAT_RUN_READING (0x03 << 20) -#define EMAC_DMA_TXSTAT_RUN_CLOSE_DESC (0x07 << 20) -#define EMAC_DMA_TXSTAT_TS_WRITE (0x04 << 20) -#define EMAC_DMA_TXSTAT_SUSPENDED (0x06 << 20) - -#define EMAC_DMA_RXSTAT_MASK (0x07 << 17) -#define EMAC_DMA_RXSTAT_STOPPED (0x00 << 17) -#define EMAC_DMA_RXSTAT_RUN_FETCH_DESC (0x01 << 17) -#define EMAC_DMA_RXSTAT_RUN_WAIT_PACKET (0x03 << 17) -#define EMAC_DMA_RXSTAT_SUSPENDED (0x04 << 17) -#define EMAC_DMA_RXSTAT_RUN_CLOSE_DESC (0x05 << 17) -#define EMAC_DMA_RXSTAT_TS_WRITE (0x06 << 17) -#define EMAC_DMA_RXSTAT_RUN_RECEIVING (0x07 << 17) - -#define EMAC_TX_DMA_STATE(x) ((x) & EMAC_DMA_TXSTAT_MASK) -#define EMAC_RX_DMA_STATE(x) ((x) & EMAC_DMA_RXSTAT_MASK) - -#define EMAC_DMA_ERROR 0x00002000 -#define EMAC_DMA_ERR_MASK 0x03800000 -#define EMAC_DMA_ERR_RX_DATA_WRITE 0x00000000 -#define EMAC_DMA_ERR_TX_DATA_READ 0x01800000 -#define EMAC_DMA_ERR_RX_DESC_WRITE 0x02000000 -#define EMAC_DMA_ERR_TX_DESC_WRITE 0x02800000 -#define EMAC_DMA_ERR_RX_DESC_READ 0x03000000 -#define EMAC_DMA_ERR_TX_DESC_READ 0x03800000 - -//***************************************************************************** -// -// Values which may be ORed together in the ui32Config parameter passed to -// EMACAddrFilterSet and which may be returned by EMACAddrFilterGet. -// -//***************************************************************************** -#define EMAC_FILTER_ADDR_ENABLE 0x80000000 -#define EMAC_FILTER_SOURCE_ADDR 0x40000000 -#define EMAC_FILTER_MASK_BYTE_6 0x20000000 -#define EMAC_FILTER_MASK_BYTE_5 0x10000000 -#define EMAC_FILTER_MASK_BYTE_4 0x08000000 -#define EMAC_FILTER_MASK_BYTE_3 0x04000000 -#define EMAC_FILTER_MASK_BYTE_2 0x03000000 -#define EMAC_FILTER_MASK_BYTE_1 0x01000000 - -#define EMAC_FILTER_BYTE_MASK_M 0x3F000000 -#define EMAC_FILTER_BYTE_MASK_S 24 - -//***************************************************************************** -// -// Flags passed to EMACTimestampConfigSet or returned from -// EMACTimestampConfigGet. -// -//***************************************************************************** -#define EMAC_TS_MAC_FILTER_ENABLE 0x00040000 -#define EMAC_TS_MAC_FILTER_DISABLE 0x00000000 -#define EMAC_TS_SYNC_FOLLOW_DREQ_DRESP 0x00000000 -#define EMAC_TS_SYNC_ONLY 0x00004000 -#define EMAC_TS_DELAYREQ_ONLY 0x0000C000 -#define EMAC_TS_ALL 0x00010000 -#define EMAC_TS_SYNC_PDREQ_PDRESP 0x00014000 -#define EMAC_TS_DREQ_PDREQ_PDRESP 0x0001C000 -#define EMAC_TS_SYNC_DELAYREQ 0x00020000 -#define EMAC_TS_PDREQ_PDRESP 0x00030000 -#define EMAC_TS_PROCESS_IPV4_UDP 0x00002000 -#define EMAC_TS_PROCESS_IPV6_UDP 0x00001000 -#define EMAC_TS_PROCESS_ETHERNET 0x00000800 -#define EMAC_TS_PTP_VERSION_2 0x00000400 -#define EMAC_TS_PTP_VERSION_1 0x00000000 -#define EMAC_TS_DIGITAL_ROLLOVER 0x00000200 -#define EMAC_TS_BINARY_ROLLOVER 0x00000000 -#define EMAC_TS_ALL_RX_FRAMES 0x00000100 -#define EMAC_TS_UPDATE_FINE 0x00000002 -#define EMAC_TS_UPDATE_COARSE 0x00000000 - -//***************************************************************************** -// -// Some register bit definitions relating to external PHYs. These are not -// relevant (or available) when using the internal Ethernet PHY but having -// the definitions here helps when using an external MII or RMII PHY. -// -//***************************************************************************** -#define EPHY_SCR_INPOL_EXT 0x00000008 -#define EPHY_SCR_TINT_EXT 0x00000004 -#define EPHY_SCR_INTEN_EXT 0x00000002 -#define EPHY_SCR_INTOE_EXT 0x00000001 - -//***************************************************************************** -// -// These interrupt sources may be passed to EMACIntEnable() and -// EMACIntDisable() to enable or disable various Ethernet interrupt sources. -// -//***************************************************************************** -// -// Note that interrupts relating to timestamping and power management must be -// independently enabled via calls to functions EMACTimestampTargetIntEnable -// and EMACPowerManagementControlSet. -// -// EMAC_INT_PHY is deliberately set to a reserved bit in the MAC interrupt -// register. We handle the fact that the PHY interrupt is controlled via an -// independent register within the code. If we didn't do this, the app would -// have to enable the MAC interrupt then enable the PHY interrupt via a -// different API (since they share a vector). To further complicate matters, -// they would have to call EMACIntStatus() and then, if it returned 0, -// read the PHY interrupt status to see that it fired. This would be nasty -// and unfriendly so we hide it inside DriverLib. -// -//***************************************************************************** -#define EMAC_INT_PHY 0x80000000 -#define EMAC_INT_EARLY_RECEIVE 0x00004000 -#define EMAC_INT_BUS_ERROR 0x00002000 -#define EMAC_INT_EARLY_TRANSMIT 0x00000400 -#define EMAC_INT_RX_WATCHDOG 0x00000200 -#define EMAC_INT_RX_STOPPED 0x00000100 -#define EMAC_INT_RX_NO_BUFFER 0x00000080 -#define EMAC_INT_RECEIVE 0x00000040 -#define EMAC_INT_TX_UNDERFLOW 0x00000020 -#define EMAC_INT_RX_OVERFLOW 0x00000010 -#define EMAC_INT_TX_JABBER 0x00000008 -#define EMAC_INT_TX_NO_BUFFER 0x00000004 -#define EMAC_INT_TX_STOPPED 0x00000002 -#define EMAC_INT_TRANSMIT 0x00000001 - -// -// These interrupt sources are summary indicators. They are readable -// using EMACIntStatus() and must be cleared using EMACIntClear(). They -// may be enabled or disabled independently of the group of interrupts that -// they are derived from but offer merely a simple way to be informed of a -// normal or abnormal condition requiring software attention. -// -// EMAC_INT_NORMAL_INT is the logical OR of the masked state of -// EMAC_INT_TRANSMIT | EMAC_INT_RECEIVE | EMAC_INT_TX_NO_BUFFER | -// EMAC_INT_EARLY_RECEIVE. -// -// EMAC_INT_ABNORMAL_INT is the logical OR of the masked state of -// EMAC_INT_TX_STOPPED | EMAC_INT_TX_JABBER | EMAC_INT_RX_OVERFLOW | -// EMAC_INT_TX_UNDERFLOW | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED | -// EMAC_INT_RX_WATCHDOG | EMAC_INT_EARLY_TRANSMIT | EMAC_INT_BUS_ERROR. -// -#define EMAC_INT_NORMAL_INT 0x00010000 -#define EMAC_INT_ABNORMAL_INT 0x00008000 - -// -// This interrupt source is readable using EMACIntStatus but must -// be cleared by calling the EMACEEEStatus(). -// -#define EMAC_INT_LPI 0x40000000 - -// -// This interrupt source is readable using EMACIntStatus but must -// be cleared by calling the EMACTimestampIntStatus(). -// -#define EMAC_INT_TIMESTAMP 0x20000000 - -// -// Interrupt sources which may be returned from EMACTimestampIntStatus(). -// -#define EMAC_TS_INT_TARGET_REACHED 0x00000002 -#define EMAC_TS_INT_TS_SEC_OVERFLOW 0x00000001 - -// -// This interrupt source is readable using EMACIntStatus but must -// be cleared by calling EMACPowerManagementStatusGet(). -// -#define EMAC_INT_POWER_MGMNT 0x10000000 - -//***************************************************************************** -// -// Configuration flags that may be passed in the ui32FreqConfig parameter to -// EMACTimestampPPSSimpleModeSet(). -// -//***************************************************************************** -#define EMAC_PPS_SINGLE_PULSE 0x00000000 -#define EMAC_PPS_1HZ 0x00000001 -#define EMAC_PPS_2HZ 0x00000002 -#define EMAC_PPS_4HZ 0x00000003 -#define EMAC_PPS_8HZ 0x00000004 -#define EMAC_PPS_16HZ 0x00000005 -#define EMAC_PPS_32HZ 0x00000006 -#define EMAC_PPS_64HZ 0x00000007 -#define EMAC_PPS_128HZ 0x00000008 -#define EMAC_PPS_256HZ 0x00000009 -#define EMAC_PPS_512HZ 0x0000000A -#define EMAC_PPS_1024HZ 0x0000000B -#define EMAC_PPS_2048HZ 0x0000000C -#define EMAC_PPS_4096HZ 0x0000000D -#define EMAC_PPS_8192HZ 0x0000000E -#define EMAC_PPS_16384HZ 0x0000000F -#define EMAC_PPS_32768HZ 0x00000010 - -//***************************************************************************** -// -// Configuration flags that may be passed in the ui32Config parameter to -// EMACTimestampPPSCommandModeSet(). -// -//***************************************************************************** -#define EMAC_PPS_TARGET_INT 0x00000000 -#define EMAC_PPS_TARGET_PPS 0x00000060 -#define EMAC_PPS_TARGET_BOTH 0x00000040 - -//***************************************************************************** -// -// Commands which may be passed to EMACTimestampPPSCmd. -// -//***************************************************************************** -#define EMAC_PPS_COMMAND_NONE 0x00 -#define EMAC_PPS_COMMAND_START_SINGLE 0x01 -#define EMAC_PPS_COMMAND_START_TRAIN 0x02 -#define EMAC_PPS_COMMAND_CANCEL_START 0x03 -#define EMAC_PPS_COMMAND_STOP_AT_TIME 0x04 -#define EMAC_PPS_COMMAND_STOP_NOW 0x05 -#define EMAC_PPS_COMMAND_CANCEL_STOP 0x06 - -//***************************************************************************** -// -// Values which may be passed to EMACVLANRxConfigSet in the ui32Config -// parameter and which may be returned from EMACVLANRxConfigGet. -// -//***************************************************************************** -#define EMAC_VLAN_RX_HASH_ENABLE 0x00080000 -#define EMAC_VLAN_RX_HASH_DISABLE 0x00000000 -#define EMAC_VLAN_RX_SVLAN_ENABLE 0x00040000 -#define EMAC_VLAN_RX_SVLAN_DISABLE 0x00000000 -#define EMAC_VLAN_RX_NORMAL_MATCH 0x00000000 -#define EMAC_VLAN_RX_INVERSE_MATCH 0x00020000 -#define EMAC_VLAN_RX_12BIT_TAG 0x00010000 -#define EMAC_VLAN_RX_16BIT_TAG 0x00000000 - -//***************************************************************************** -// -// Values which may be passed to EMACVLANTxConfigSet in the ui32Config -// parameter and which may be returned from EMACVLANTxConfigGet. -// -//***************************************************************************** -#define EMAC_VLAN_TX_CVLAN 0x00000000 -#define EMAC_VLAN_TX_SVLAN 0x00080000 -#define EMAC_VLAN_TX_USE_VLC 0x00040000 -#define EMAC_VLAN_TX_VLC_NONE 0x00000000 -#define EMAC_VLAN_TX_VLC_DELETE 0x00010000 -#define EMAC_VLAN_TX_VLC_INSERT 0x00020000 -#define EMAC_VLAN_TX_VLC_REPLACE 0x00030000 - -#define EMAC_VLAN_TX_VLC_MASK 0x00030000 - -#define EMAC_RWU_FILTER_ENABLE 1 -#define EMAC_RWU_FILTER_DISABLE 0 -#define EMAC_RWU_FILTER_MULTICAST 8 -#define EMAC_RWU_FILTER_UNICAST 0 - -//***************************************************************************** -// -// The following structure fields must be packed. -// -//***************************************************************************** -#ifdef ewarm -#pragma pack(1) -#endif - -//***************************************************************************** -// -//! This structure defines up to 4 filters that can be used to define specific -//! frames which will cause the MAC to wake up from sleep mode. -// -//***************************************************************************** -typedef struct -{ - // - //! A byte mask for each filter defining which bytes from a sequence of - //! 31 (bit 31 must be clear in each mask) are used to filter incoming - //! packets. A 1 indicates that the relevant byte is used to update the - //! CRC16 for the filter, a 0 indicates that the byte is ignored. - // - uint32_t pui32ByteMask[4]; - - // - //! Defines whether each filter is enabled and, if so, whether it filters - //! multicast or unicast frames. Valid values are one of - //! EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE ORed with one of - //! EMAC_RWU_FILTER_UNICAST or EMAC_RWU_FILTER_MULTICAST. - // - uint8_t pui8Command[4]; - - // - //! Determines the byte offset within the frame at which the filter starts - //! examining bytes. The minimum value for each offset is 12. The first - //! byte of a frame is offset 0. - // - uint8_t pui8Offset[4]; - - // - //! The CRC16 value that is expected for each filter if it passes. The - //! CRC is calculated using all bytes indicated by the filter's mask. - // - uint16_t pui16CRC[4]; -} -#if defined(ccs) || \ - defined(codered) || \ - defined(gcc) || \ - defined(rvmdk) || \ - defined(__ARMCC_VERSION) || \ - defined(sourcerygxx) -__attribute__ ((packed)) tEMACWakeUpFrameFilter; -#else -tEMACWakeUpFrameFilter; -#endif - -//***************************************************************************** -// -// Turn off structure packing again. -// -//***************************************************************************** -#ifdef ewarm -#pragma pack() -#endif - -//***************************************************************************** -// -// Values which may be ORed together and used in the ui32Flags parameter to -// EMACPowerManagementControlSet. These may also returned be from a call to -// EMACPowerManagementControlGet. -// -//***************************************************************************** -#define EMAC_PMT_GLOBAL_UNICAST_ENABLE 0x00000200 -#define EMAC_PMT_WAKEUP_PACKET_ENABLE 0x00000004 -#define EMAC_PMT_MAGIC_PACKET_ENABLE 0x00000002 -#define EMAC_PMT_POWER_DOWN 0x00000001 - -//***************************************************************************** -// -// Values which may be ORed together and returned from a call to -// EMACPowerManagementStatusGet. This call will also return -// EMAC_PMT_POWER_DOWN if the MAC is in power-down mode. -// -//***************************************************************************** -#define EMAC_PMT_WAKEUP_PACKET_RECEIVED 0x00000040 -#define EMAC_PMT_MAGIC_PACKET_RECEIVED 0x00000020 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Public function prototypes. -// -//***************************************************************************** -extern void EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, - uint32_t ui32BusConfig, uint32_t ui32RxBurst, - uint32_t ui32TxBurst, uint32_t ui32DescSkipSize); -extern void EMACReset(uint32_t ui32Base); -extern void EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32ModeFlags, - uint32_t ui32RxMaxFrameSize); -extern void EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts); -extern uint32_t EMACFrameFilterGet(uint32_t ui32Base); -extern void EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, - uint32_t ui32HashLo); -extern void EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi, - uint32_t *pui32HashLo); -extern uint32_t EMACHashFilterBitCalculate(uint8_t *pui8MACAddr); -extern void EMACTxDMAPollDemand(uint32_t ui32Base); -extern void EMACRxDMAPollDemand(uint32_t ui32Base); -extern void EMACRxDMADescriptorListSet(uint32_t ui32Base, - tEMACDMADescriptor *pDescriptor); -extern tEMACDMADescriptor *EMACRxDMADescriptorListGet(uint32_t ui32Base); -extern tEMACDMADescriptor *EMACRxDMACurrentDescriptorGet(uint32_t ui32Base); -extern uint8_t *EMACRxDMACurrentBufferGet(uint32_t ui32Base); -extern void EMACTxDMADescriptorListSet(uint32_t ui32Base, - tEMACDMADescriptor *pDescriptor); -extern tEMACDMADescriptor *EMACTxDMADescriptorListGet(uint32_t ui32Base); -extern tEMACDMADescriptor *EMACTxDMACurrentDescriptorGet(uint32_t ui32Base); -extern uint8_t *EMACTxDMACurrentBufferGet(uint32_t ui32Base); -extern void EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, - uint32_t *pui32Mode, uint32_t *pui32RxMaxFrameSize); -extern void EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, - const uint8_t *pui8MACAddr); -extern void EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, - uint8_t *pui8MACAddr); -extern uint32_t EMACNumAddrGet(uint32_t ui32Base); -extern void EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, - uint32_t ui32Config); -extern uint32_t EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index); -extern void EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout); -extern uint32_t EMACStatusGet(uint32_t ui32Base); -extern uint32_t EMACDMAStateGet(uint32_t ui32Base); -extern void EMACTxFlush(uint32_t ui32Base); -extern void EMACTxEnable(uint32_t ui32Base); -extern void EMACTxDisable(uint32_t ui32Base); -extern void EMACRxEnable(uint32_t ui32Base); -extern void EMACRxDisable(uint32_t ui32Base); -extern void EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t EMACIntStatus(uint32_t ui32Base, bool bMasked); -extern void EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void EMACIntUnregister(uint32_t ui32Base); -extern void EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint8_t ui8RegAddr, uint16_t ui16Data); -extern void EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr, uint16_t ui16Data); -extern uint16_t EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint8_t ui8RegAddr); -extern uint16_t EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr); -extern void EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr); -extern void EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr); -extern void EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32SubSecondInc); -extern uint32_t EMACTimestampConfigGet(uint32_t ui32Base, - uint32_t *pui32SubSecondInc); -extern void EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Seconds); -extern void EMACTimestampEnable(uint32_t ui32Base); -extern void EMACTimestampDisable(uint32_t ui32Base); -extern void EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds); -extern void EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds, - uint32_t *pui32SubSeconds); -extern void EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32SubSeconds, bool bInc); -extern void EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds, - uint32_t ui32Nanoseconds); -extern void EMACTimestampTargetIntEnable(uint32_t ui32Base); -extern void EMACTimestampTargetIntDisable(uint32_t ui32Base); -extern uint32_t EMACTimestampIntStatus(uint32_t ui32Base); -extern void EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, - uint32_t ui32FreqConfig); -extern void EMACTimestampPPSCommandModeSet(uint32_t ui32Base, - uint32_t ui32Config); -extern void EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd); -extern void EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period, - uint32_t ui32Width); -extern void EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, - uint32_t ui32Config); -extern uint32_t EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); -extern void EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, - uint32_t ui32Config); -extern uint32_t EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag); -extern uint32_t EMACVLANHashFilterBitCalculate(uint16_t ui16Tag); -extern void EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash); -extern uint32_t EMACVLANHashFilterGet(uint32_t ui32Base); -extern void EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base, - const tEMACWakeUpFrameFilter *pFilter); -extern void EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base, - tEMACWakeUpFrameFilter *pFilter); -extern void EMACPowerManagementControlSet(uint32_t ui32Base, - uint32_t ui32Flags); -extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base); -extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base); -extern void EMACWoLEnter(uint32_t ui32Base); -extern void EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, - uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer); -extern void EMACLPIEnter(uint32_t ui32Base); -extern uint16_t EMACLPIStatus(uint32_t ui32Base); -extern void EMACLPILinkSet(uint32_t ui32Base); -extern void EMACLPILinkClear(uint32_t ui32Base); -extern void EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr, uint16_t ui16Data); -extern uint16_t EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, - uint16_t ui16RegAddr); -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_EMAC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/epi.c b/bsp/tm4c129x-dk/libraries/driverlib/epi.c deleted file mode 100644 index c85a02621e..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/epi.c +++ /dev/null @@ -1,2187 +0,0 @@ -//***************************************************************************** -// -// epi.c - Driver for the EPI module. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include -#include "inc/hw_epi.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/epi.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! \addtogroup epi_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// Helper masks for chip select configuration options. -// -//***************************************************************************** -#define EPI_HB8_CS_MASK (EPI_HB8_MODE_FIFO | EPI_HB8_RDWAIT_3 | \ - EPI_HB8_WRWAIT_3 | EPI_HB8_RDHIGH | \ - EPI_HB8_WRHIGH | EPI_HB8_ALE_HIGH) - -#define EPI_HB16_CS_MASK (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC) - -//***************************************************************************** -// -// Ensure that erratum workaround inline functions have a public version -// available in exactly one object module (this one). -// -//***************************************************************************** - -//***************************************************************************** -// -//! Safely writes a word to the EPI 0x10000000 address space. -//! -//! \param pui32Addr is the address which is to be written. -//! \param ui32Value is the 32-bit word to write. -//! -//! This function must be used when writing words to EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return None. -// -//***************************************************************************** -extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value); - -//***************************************************************************** -// -//! Safely reads a word from the EPI 0x10000000 address space. -//! -//! \param pui32Addr is the address which is to be read. -//! -//! This function must be used when reading words from EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return The 32-bit word stored at address \e pui32Addr. -// -//***************************************************************************** -extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr); - -//***************************************************************************** -// -//! Safely writes a half-word to the EPI 0x10000000 address space. -//! -//! \param pui16Addr is the address which is to be written. -//! \param ui16Value is the 16-bit half-word to write. -//! -//! This function must be used when writing half-words to EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return None. -// -//***************************************************************************** -extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value); - -//***************************************************************************** -// -//! Safely reads a half-word from the EPI 0x10000000 address space. -//! -//! \param pui16Addr is the address which is to be read. -//! -//! This function must be used when reading half-words from EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return The 16-bit word stored at address \e pui16Addr. -// -//***************************************************************************** -extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr); - -//***************************************************************************** -// -//! Safely writes a byte to the EPI 0x10000000 address space. -//! -//! \param pui8Addr is the address which is to be written. -//! \param ui8Value is the 8-bit byte to write. -//! -//! This function must be used when writing bytes to EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return None. -// -//***************************************************************************** -extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value); - -//***************************************************************************** -// -//! Safely reads a byte from the EPI 0x10000000 address space. -//! -//! \param pui8Addr is the address which is to be read. -//! -//! This function must be used when reading bytes from EPI-attached memory -//! configured to use the address space at 0x10000000 on devices affected by -//! the EPI#01 erratum. Direct access to memory in these cases can cause data -//! corruption depending upon memory accesses immediately before or after the -//! EPI access but using this function will allow EPI accesses to complete -//! correctly. The function is defined as ``inline'' in epi.h. -//! -//! Use of this function on a device not affected by the erratum is safe but -//! will impact performance due to an additional overhead of at least 2 cycles -//! per access. This erratum affects only the 0x10000000 address space -//! typically used to store the LCD controller frame buffer. The 0x60000000 -//! address space is not affected and applications using this address mapping -//! need not use this function. -//! -//! \return The 8-bit byte stored at address \e pui8Addr. -// -//***************************************************************************** -extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr); - -//***************************************************************************** -// -//! Sets the usage mode of the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Mode is the usage mode of the EPI module. -//! -//! This functions sets the operating mode of the EPI module. The parameter -//! \e ui32Mode must be one of the following: -//! -//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation -//! - \b EPI_MODE_SDRAM - use with SDRAM device -//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface -//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface -//! - \b EPI_MODE_DISABLE - disable the EPI module -//! -//! Selection of any of the above modes enables the EPI module, except -//! for \b EPI_MODE_DISABLE, which is used to disable the module. -//! -//! \return None. -// -//***************************************************************************** -void -EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT((ui32Mode == EPI_MODE_GENERAL) || - (ui32Mode == EPI_MODE_SDRAM) || - (ui32Mode == EPI_MODE_HB8) || - (ui32Mode == EPI_MODE_HB16) || - (ui32Mode == EPI_MODE_DISABLE)); - - // - // Write the mode word to the register. - // - HWREG(ui32Base + EPI_O_CFG) = ui32Mode; -} - -//***************************************************************************** -// -//! Sets the clock divider for the EPI module's CS0n/CS1n. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Divider is the value of the clock divider to be applied to -//! the external interface (0-65535). -//! -//! This function sets the clock divider(s) that is used to determine the -//! clock rate of the external interface. The \e ui32Divider value is used to -//! derive the EPI clock rate from the system clock based on the following -//! formula. -//! -//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) -//! -//! For example, a divider value of 1 results in an EPI clock rate of half -//! the system clock, value of 2 or 3 yields one quarter of the system clock -//! and a value of 4 results in one sixth of the system clock rate. -//! -//! In cases where a dual chip select mode is in use and different clock rates -//! are required for each chip select, the \e ui32Divider parameter must -//! contain two dividers. The lower 16 bits define the divider to be used with -//! CS0n and the upper 16 bits define the divider for CS1n. -//! -//! \return None. -// -//***************************************************************************** -void -EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Write the divider value to the register. - // - HWREG(ui32Base + EPI_O_BAUD) = ui32Divider; -} - -//***************************************************************************** -// -//! Sets the clock divider for the specified CS in the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select to modify and has a valid range of 0-3. -//! \param ui32Divider is the value of the clock divider to be applied to -//! the external interface (0-65535). -//! -//! This function sets the clock divider(s) for the specified CS that is used -//! to determine the clock rate of the external interface. The \e ui32Divider -//! value is used to derive the EPI clock rate from the system clock based on -//! the following formula. -//! -//! EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2)) -//! -//! For example, a divider value of 1 results in an EPI clock rate of half -//! the system clock, value of 2 or 3 yields one quarter of the system clock -//! and a value of 4 results in one sixth of the system clock rate. -//! -//! \note The availability of CS2n and CS3n varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Divider) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Write the divider value to the register bitfield. - // - if(ui32CS < 2) - { - ui32Reg = HWREG(ui32Base + EPI_O_BAUD) & ~(0xffff << (16 * ui32CS)); - ui32Reg |= ((ui32Divider & 0xffff) << (16 * ui32CS)); - HWREG(ui32Base + EPI_O_BAUD) = ui32Reg; - } - else - { - ui32Reg = (HWREG(ui32Base + EPI_O_BAUD2) & - ~(0xffff << (16 * (ui32CS - 2)))); - ui32Reg |= ((ui32Divider & 0xffff) << (16 * (ui32CS - 2))); - HWREG(ui32Base + EPI_O_BAUD2) = ui32Reg; - } -} - -//***************************************************************************** -// -//! Sets the transfer count for uDMA transmit operations on EPI. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the number of units to transmit by uDMA to WRFIFO. -//! -//! This function is used to help configure the EPI uDMA transmit operations. -//! A non-zero transmit count in combination with a FIFO threshold trigger -//! asserts an EPI uDMA transmit. -//! -//! Note that, although the EPI peripheral can handle counts of up to 65535, -//! a single uDMA transfer has a maximum length of 1024 units so \e ui32Count -//! should be set to values less than or equal to 1024. -//! -//! \note The availability of the EPI DMA TX count varies based on the -//! Tiva part in use. Please consult the data sheet to determine if this -//! feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count <= 1024); - - // - // Assign the DMA TX count value provided. - // - HWREG(ui32Base + EPI_O_DMATXCNT) = ui32Count & 0xffff; -} - -//***************************************************************************** -// -//! Configures the SDRAM mode of operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the SDRAM interface configuration. -//! \param ui32Refresh is the refresh count in core clocks (0-2047). -//! -//! This function is used to configure the SDRAM interface, when the SDRAM -//! mode is chosen with the function EPIModeSet(). The parameter -//! \e ui32Config is the logical OR of several sets of choices: -//! -//! The processor core frequency must be specified with one of the following: -//! -//! - \b EPI_SDRAM_CORE_FREQ_0_15 defines core clock as 0 MHz < clk <= 15 MHz -//! - \b EPI_SDRAM_CORE_FREQ_15_30 defines core clock as 15 MHz < clk <= 30 MHz -//! - \b EPI_SDRAM_CORE_FREQ_30_50 defines core clock as 30 MHz < clk <= 50 MHz -//! - \b EPI_SDRAM_CORE_FREQ_50_100 defines core clock as 50 MHz < clk <= -//! 100 MHz -//! -//! The low power mode is specified with one of the following: -//! -//! - \b EPI_SDRAM_LOW_POWER enter low power, self-refresh state. -//! - \b EPI_SDRAM_FULL_POWER normal operating state. -//! -//! The SDRAM device size is specified with one of the following: -//! -//! - \b EPI_SDRAM_SIZE_64MBIT size is a 64 Mbit device (8 MB). -//! - \b EPI_SDRAM_SIZE_128MBIT size is a 128 Mbit device (16 MB). -//! - \b EPI_SDRAM_SIZE_256MBIT size is a 256 Mbit device (32 MB). -//! - \b EPI_SDRAM_SIZE_512MBIT size is a 512 Mbit device (64 MB). -//! -//! The parameter \e ui16Refresh sets the refresh counter in units of core -//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32Refresh) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Refresh < 2048); - - // - // Fill in the refresh count field of the configuration word. - // - ui32Config &= ~EPI_SDRAMCFG_RFSH_M; - ui32Config |= ui32Refresh << EPI_SDRAMCFG_RFSH_S; - - // - // Write the SDRAM configuration register. - // - HWREG(ui32Base + EPI_O_SDRAMCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the interface for Host-bus 8 operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the interface configuration. -//! \param ui32MaxWait is the maximum number of external clocks to wait -//! if a FIFO ready signal is holding off the transaction, 0-255. -//! -//! This function is used to configure the interface when used in host-bus 8 -//! operation as chosen with the function EPIModeSet(). The parameter -//! \e ui32Config is the logical OR of the following: -//! -//! - Host-bus 8 submode, select one of: -//! - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0] -//! - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0] -//! - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address -//! switch for multiple reads instead of OEn strobing, D[7:0] -//! - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO -//! empty, D[7:0] -//! -//! - \b EPI_HB8_USE_TXEMPTY enables TXEMPTY signal with FIFO -//! - \b EPI_HB8_USE_RXFULL enables RXFULL signal with FIFO -//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is -//! active low -//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is -//! active low -//! -//! - Write wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default) -//! - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks -//! - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks -//! - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks -//! -//! - Read wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default) -//! - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks -//! - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks -//! - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks -//! -//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the -//! correct byte lanes allowing data to be stored in bits [31:8]. If absent, -//! all data transfers use bits [7:0]. -//! -//! - \b EPI_HB8_CLOCK_GATE_IDLE sets the EPI clock to be held low when no data -//! is available to read or write -//! - \b EPI_HB8_CLOCK_INVERT inverts the EPI clock -//! - \b EPI_HB8_IN_READY_EN sets EPIS032 as a ready/stall signal, active high -//! - \b EPI_HB8_IN_READY_EN_INVERT sets EPIS032 as ready/stall signal, active -//! low -//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default) -//! - \b EPI_HB8_ALE_LOW sets address latch active low -//! - \b EPI_HB8_CSBAUD use different baud rates when accessing devices on each -//! chip select. CS0n uses the baud rate specified by the lower 16 bits -//! of the divider passed to EPIDividerSet() and CS1n uses the divider passed -//! in the upper 16 bits. If this option is absent, both chip selects use -//! the baud rate resulting from the divider in the lower 16 bits of the -//! parameter passed to EPIDividerSet(). -//! -//! In addition, some parts support CS2n and CS3n for a total of 4 chip -//! selects. If \b EPI_HB8_CSBAUD is configured, EPIDividerCSSet() should be -//! used to to configure the divider for CS2n and CS3n. They both also use the -//! lower 16 bits passed to EPIDividerSet() if this option is absent. -//! -//! The use of \b EPI_HB8_CSBAUD also allows for unique chip select -//! configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by -//! calling EPIConfigHB8CSSet() if \b EPI_HB8_CSBAUD is used. Otherwise, the -//! configuration provided in \e ui32Config is used for all chip selects -//! enabled. -//! -//! - Chip select configuration, select one of: -//! - \b EPI_HB8_CSCFG_CS sets EPIS030 to operate as a chip select signal. -//! - \b EPI_HB8_CSCFG_ALE sets EPIS030 to operate as an address latch -//! (ALE). -//! - \b EPI_HB8_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 -//! as CS1n with the asserted chip select determined from the most -//! significant address bit for the respective external address map. -//! - \b EPI_HB8_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), -//! EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select -//! determined from the most significant address bit for the respective -//! external address map. -//! - \b EPI_HB8_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address -//! latch (ALE) and EPIS027 is used as a chip select. -//! - \b EPI_HB8_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, -//! EPIS034 as CS2n and EPIS033 as CS3n. -//! - \b EPI_HB8_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch (ALE), -//! EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 as CS3n. -//! \note Dual or quad chip select configurations cannot be used with -//! EPI_HB8_MODE_SRAM. -//! -//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen. If a -//! FIFO is used aint32_t with RXFULL or TXEMPTY ready signals, then this -//! parameter determines the maximum number of clocks to wait when the -//! transaction is being held off by by the FIFO using one of these ready -//! signals. A value of 0 means to wait forever. -//! -//! \note Availability of configuration options varies based on the Tiva -//! part in use. Please consult the data sheet to determine if the features -//! desired are available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxWait) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32MaxWait < 256); - - // - // Determine the CS and word access modes. - // - HWREG(ui32Base + EPI_O_HB8CFG2) = - ((ui32Config & EPI_HB8_CSBAUD) ? EPI_HB8CFG2_CSBAUD : 0) | - ((ui32Config & EPI_HB8_CSCFG_MASK) << 15); - - // - // Fill in the max wait field of the configuration word. - // - ui32Config &= ~EPI_HB8CFG_MAXWAIT_M; - ui32Config |= ui32MaxWait << EPI_HB8CFG_MAXWAIT_S; - - // - // Write the main HostBus8 configuration register. - // - HWREG(ui32Base + EPI_O_HB8CFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the interface for Host-bus 16 operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the interface configuration. -//! \param ui32MaxWait is the maximum number of external clocks to wait -//! if a FIFO ready signal is holding off the transaction. -//! -//! This function is used to configure the interface when used in Host-bus 16 -//! operation as chosen with the function EPIModeSet(). The parameter -//! \e ui32Config is the logical OR of the following: -//! - Host-bus 16 submode, select one of: -//! - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0]. -//! - \b EPI_HB16_MODE_ADDEMUX sets up data and address as separate, -//! D[15:0]. -//! - \b EPI_HB16_MODE_SRAM sets as \b EPI_HB16_MODE_ADDEMUX but uses -//! address switch for multiple reads instead of OEn strobing, D[15:0]. -//! - \b EPI_HB16_MODE_FIFO addes XFIFO controls with sense of XFIFO full -//! and XFIFO empty, D[15:0]. This submode uses no address or ALE. -//! -//! - \b EPI_HB16_USE_TXEMPTY enables TXEMPTY signal with FIFO. -//! - \b EPI_HB16_USE_RXFULL enables RXFULL signal with FIFO. -//! - \b EPI_HB16_WRHIGH use active high write strobe, otherwise it is -//! active low. -//! - \b EPI_HB16_RDHIGH use active high read strobe, otherwise it is -//! active low. -//! - Write wait state, select one of: -//! - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks. -//! - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks. -//! - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks. -//! - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks. -//! -//! - Read wait state, select one of: -//! - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks. -//! - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks. -//! - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks. -//! - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks. -//! -//! - \b EPI_HB16_WORD_ACCESS use Word Access mode to route bytes to the -//! correct byte lanes allowing data to be stored in bits [31:16]. If -//! absent, all data transfers use bits [15:0]. -//! -//! \note \b EPI_HB16_WORD_ACCESS is not available on all parts. Please -//! consult the data sheet to determine if this feature is available. -//! -//! - \b EPI_HB16_CLOCK_GATE_IDLE holds the EPI clock low when no data is -//! available to read or write. -//! - \b EPI_HB16_CLOCK_INVERT inverts the EPI clock. -//! - \b EPI_HB16_IN_READY_EN sets EPIS032 as a ready/stall signal, active -//! high. -//! - \b EPI_HB16_IN_READY_EN_INVERTED sets EPIS032 as ready/stall signal, -//! active low. -//! - Address latch logic, select one of: -//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default). -//! - \b EPI_HB16_ALE_LOW sets address latch active low. -//! -//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with -//! \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an -//! ALE. -//! - \b EPI_HB16_BSEL enables byte selects. In this mode, two EPI signals -//! operate as byte selects allowing 8-bit transfers. If this flag is not -//! specified, data must be read and written using only 16-bit transfers. -//! - \b EPI_HB16_CSBAUD use different baud rates when accessing devices -//! on each chip select. CS0n uses the baud rate specified by the lower 16 -//! bits of the divider passed to EPIDividerSet() and CS1n uses the divider -//! passed in the upper 16 bits. If this option is absent, both chip selects -//! use the baud rate resulting from the divider in the lower 16 bits of the -//! parameter passed to EPIDividerSet(). -//! -//! In addition, some parts support CS2n and CS3n for a total of 4 chip -//! selects. If \b EPI_HB16_CSBAUD is configured, EPIDividerCSSet() should be -//! used to to configure the divider for CS2n and CS3n. They both also use the -//! lower 16 bits passed to EPIDividerSet() if this option is absent. -//! -//! The use of \b EPI_HB16_CSBAUD also allows for unique chip select -//! configurations. CS0n, CS1n, CS2n, and CS3n can each be configured by -//! calling EPIConfigHB16CSSet() if \b EPI_HB16_CSBAUD is used. Otherwise, the -//! configuration provided in \e ui32Config is used for all chip selects. -//! -//! - Chip select configuration, select one of: -//! - \b EPI_HB16_CSCFG_CS sets EPIS030 to operate as a chip select signal. -//! - \b EPI_HB16_CSCFG_ALE sets EPIS030 to operate as an address latch -//! (ALE). -//! - \b EPI_HB16_CSCFG_DUAL_CS sets EPIS030 to operate as CS0n and EPIS027 -//! as CS1n with the asserted chip select determined from the most -//! significant address bit for the respective external address map. -//! - \b EPI_HB16_CSCFG_ALE_DUAL_CS sets EPIS030 as an address latch (ALE), -//! EPIS027 as CS0n and EPIS026 as CS1n with the asserted chip select -//! determined from the most significant address bit for the respective -//! external address map. -//! - \b EPI_HB16_CSCFG_ALE_SINGLE_CS sets EPIS030 to operate as an address -//! latch (ALE) and EPIS027 is used as a chip select. -//! - \b EPI_HB16_CSCFG_QUAD_CS sets EPIS030 as CS0n, EPIS027 as CS1n, -//! EPIS034 as CS2n and EPIS033 as CS3n. -//! - \b EPI_HB16_CSCFG_ALE_QUAD_CS sets EPIS030 as an address latch -//! (ALE), EPIS026 as CS0n, EPIS027 as CS1n, EPIS034 as CS2n and EPIS033 -//! as CS3n. -//! \note Dual or quad chip select configurations cannot be used with -//! EPI_HB16_MODE_SRAM. -//! -//! The parameter \e ui32MaxWait is used if the FIFO mode is chosen. If a -//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this -//! parameter determines the maximum number of clocks to wait when the -//! transaction is being held off by by the FIFO using one of these ready -//! signals. A value of 0 means to wait forever. -//! -//! \note Availability of configuration options varies based on the Tiva -//! part in use. Please consult the data sheet to determine if the features -//! desired are available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32MaxWait < 256); - - // - // Determine the CS and word access modes. - // - HWREG(ui32Base + EPI_O_HB16CFG2) = - ((ui32Config & EPI_HB16_CSBAUD) ? EPI_HB16CFG2_CSBAUD : 0) | - ((ui32Config & EPI_HB16_CSCFG_MASK) << 15); - - // - // Fill in the max wait field of the configuration word. - // - ui32Config &= ~EPI_HB16CFG_MAXWAIT_M; - ui32Config |= ui32MaxWait << EPI_HB16CFG_MAXWAIT_S; - - // - // Write the main HostBus16 configuration register. - // - HWREG(ui32Base + EPI_O_HB16CFG) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the individual chip select configuration for the Host-bus 8 interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to configure individual chip select settings for the -//! Host-bus 8 interface mode. EPIConfigHB8Set() must have been setup with -//! the \b EPI_HB8_CSBAUD flag for the individual chip select configuration -//! option to be available. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - Host-bus 8 submode, select one of: -//! - \b EPI_HB8_MODE_ADMUX sets data and address muxed, AD[7:0]. -//! - \b EPI_HB8_MODE_ADDEMUX sets up data and address separate, D[7:0]. -//! - \b EPI_HB8_MODE_SRAM as \b EPI_HB8_MODE_ADDEMUX, but uses address -//! switch for multiple reads instead of OEn strobing, D[7:0]. -//! - \b EPI_HB8_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO -//! empty, D[7:0]. This is only available for CS0n and CS1n. -//! -//! - \b EPI_HB8_WRHIGH sets active high write strobe, otherwise it is -//! active low. -//! - \b EPI_HB8_RDHIGH sets active high read strobe, otherwise it is -//! active low. -//! - Write wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_WRWAIT_0 sets write wait state to 2 EPI clocks (default). -//! - \b EPI_HB8_WRWAIT_1 sets write wait state to 4 EPI clocks. -//! - \b EPI_HB8_WRWAIT_2 sets write wait state to 6 EPI clocks. -//! - \b EPI_HB8_WRWAIT_3 sets write wait state to 8 EPI clocks. -//! - Read wait state when \b EPI_HB8_BAUD is used, select one of: -//! - \b EPI_HB8_RDWAIT_0 sets read wait state to 2 EPI clocks (default). -//! - \b EPI_HB8_RDWAIT_1 sets read wait state to 4 EPI clocks. -//! - \b EPI_HB8_RDWAIT_2 sets read wait state to 6 EPI clocks. -//! - \b EPI_HB8_RDWAIT_3 sets read wait state to 8 EPI clocks. -//! - \b EPI_HB8_ALE_HIGH sets the address latch active high (default). -//! - \b EPI_HB8_ALE_LOW sets address latch active low. -//! -//! \note The availability of a unique chip select configuration within -//! Host-bus 8 interface mode varies based on the Tiva part in use. -//! Please consult the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - uint32_t ui32Offset, ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB8CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB8CFG3 + ((ui32CS - 2) << 2); - } - - // - // Preserve the bits that will not be modified. - // - ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB8_CS_MASK; - - // - // Write the target chip select HostBus8 configuration fields. - // - HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config); -} - -//***************************************************************************** -// -//! Sets the individual chip select configuration for the Host-bus 16 -//! interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to configure individual chip select settings for the -//! Host-bus 16 interface mode. EPIConfigHB16Set() must have been set up with -//! the \b EPI_HB16_CSBAUD flag for the individual chip select configuration -//! option to be available. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR the -//! following: -//! -//! - Host-bus 16 submode, select one of: -//! - \b EPI_HB16_MODE_ADMUX sets data and address muxed, AD[15:0]. -//! - \b EPI_HB16_MODE_ADDEMUX sets up data and address separate, D[15:0]. -//! - \b EPI_HB16_MODE_SRAM same as \b EPI_HB8_MODE_ADDEMUX, but uses -//! address switch for multiple reads instead of OEn strobing, D[15:0]. -//! - \b EPI_HB16_MODE_FIFO adds XFIFO with sense of XFIFO full and XFIFO -//! empty, D[15:0]. This feature is only available on CS0n and CS1n. -//! - \b EPI_HB16_WRHIGH sets active high write strobe, otherwise it is -//! active low. -//! - \b EPI_HB16_RDHIGH sets active high read strobe, otherwise it is -//! active low. -//! - Write wait state when \b EPI_HB16_BAUD is used, select one of: -//! - \b EPI_HB16_WRWAIT_0 sets write wait state to 2 EPI clocks (default). -//! - \b EPI_HB16_WRWAIT_1 sets write wait state to 4 EPI clocks. -//! - \b EPI_HB16_WRWAIT_2 sets write wait state to 6 EPI clocks. -//! - \b EPI_HB16_WRWAIT_3 sets write wait state to 8 EPI clocks. -//! - Read wait state when \b EPI_HB16_BAUD is used, select one of: -//! - \b EPI_HB16_RDWAIT_0 sets read wait state to 2 EPI clocks (default). -//! - \b EPI_HB16_RDWAIT_1 sets read wait state to 4 EPI clocks. -//! - \b EPI_HB16_RDWAIT_2 sets read wait state to 6 EPI clocks. -//! - \b EPI_HB16_RDWAIT_3 sets read wait state to 8 EPI clocks. -//! - \b EPI_HB16_ALE_HIGH sets the address latch active high (default). -//! - \b EPI_HB16_ALE_LOW sets address latch active low. -//! - \b EPI_HB16_BURST_TRAFFIC enables burst traffic. Only valid with -//! \b EPI_HB16_MODE_ADMUX and a chip select configuration that utilizes an -//! ALE. -//! -//! \note The availability of the unique chip select configuration within the -//! Host-bus 16 interface mode varies based on the Tiva part in use. -//! Please consult the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - uint32_t ui32Offset, ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Preserve the bits that will not be modified. - // - ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB16_CS_MASK; - - // - // Write the target chip select HostBus16 configuration fields. - // - HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config); -} - -//***************************************************************************** -// -//! Sets the individual chip select timing settings for the Host-bus 8 -//! interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to set individual chip select timings for the -//! Host-bus 8 interface mode. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - Input ready stall delay, select one of: -//! - \b EPI_HB8_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) -//! to start 1 EPI clock after signaled. -//! - \b EPI_HB8_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) -//! to start 2 EPI clocks after signaled. -//! - \b EPI_HB8_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) -//! to start 3 EPI clocks after signaled. -//! -//! - Host bus transfer delay, select one of: -//! - \b EPI_HB8_CAP_WIDTH_1 defines the inter-transfer capture width to -//! create a delay of 1 EPI clock. -//! - \b EPI_HB8_CAP_WIDTH_2 defines the inter-transfer capture width -//! to create a delay of 2 EPI clocks. -//! -//! - \b EPI_HB8_WRWAIT_MINUS_DISABLE disables the additional write wait state -//! reduction. -//! - \b EPI_HB8_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait state -//! reduction. -//! - \b EPI_HB8_RDWAIT_MINUS_DISABLE disables the additional read wait state -//! reduction. -//! - \b EPI_HB8_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state -//!reduction. -//! -//! \note The availability of unique chip select timings within Host-bus 8 -//! interface mode varies based on the Tiva part in use. Please consult -//! the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Write the target chip select HostBus8 timing register. - // - HWREG(ui32Base + (EPI_O_HB8TIME + (ui32CS << 2))) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the individual chip select timing settings for the Host-bus 16 -//! interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select value to configure. -//! \param ui32Config is the configuration settings. -//! -//! This function is used to set individual chip select timings for the -//! Host-bus 16 interface mode. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - Input ready stall delay, select one of: -//! - \b EPI_HB16_IN_READY_DELAY_1 sets the stall on input ready (EPIS032) -//! to start 1 EPI clock after signaled. -//! - \b EPI_HB16_IN_READY_DELAY_2 sets the stall on input ready (EPIS032) -//! to start 2 EPI clocks after signaled. -//! - \b EPI_HB16_IN_READY_DELAY_3 sets the stall on input ready (EPIS032) -//! to start 3 EPI clocks after signaled. -//! -//! - PSRAM size limitation, select one of: -//! - \b EPI_HB16_PSRAM_NO_LIMIT defines no row size limitation. -//! - \b EPI_HB16_PSRAM_128 defines the PSRAM row size to 128 bytes. -//! - \b EPI_HB16_PSRAM_256 defines the PSRAM row size to 256 bytes. -//! - \b EPI_HB16_PSRAM_512 defines the PSRAM row size to 512 bytes. -//! - \b EPI_HB16_PSRAM_1024 defines the PSRAM row size to 1024 bytes. -//! - \b EPI_HB16_PSRAM_2048 defines the PSRAM row size to 2048 bytes. -//! - \b EPI_HB16_PSRAM_4096 defines the PSRAM row size to 4096 bytes. -//! - \b EPI_HB16_PSRAM_8192 defines the PSRAM row size to 8192 bytes. -//! -//! - Host bus transfer delay, select one of: -//! - \b EPI_HB16_CAP_WIDTH_1 defines the inter-transfer capture width to -//! create a delay of 1 EPI clock -//! - \b EPI_HB16_CAP_WIDTH_2 defines the inter-transfer capture width -//! to create a delay of 2 EPI clocks. -//! -//! - Write wait state timing reduction, select one of: -//! - \b EPI_HB16_WRWAIT_MINUS_DISABLE disables the additional write wait -//! state reduction. -//! - \b EPI_HB16_WRWAIT_MINUS_ENABLE enables a 1 EPI clock write wait -//! state reduction. -//! -//! - Read wait state timing reduction, select one of: -//! - \b EPI_HB16_RDWAIT_MINUS_DISABLE disables the additional read wait -//! state reduction. -//! - \b EPI_HB16_RDWAIT_MINUS_ENABLE enables a 1 EPI clock read wait state -//! reduction. -//! -//! \note The availability of unique chip select timings within Host-bus 16 -//! interface mode varies based on the Tiva part in use. Please consult -//! the data sheet to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Write the target chip select HostBus16 timing register. - // - HWREG(ui32Base + (EPI_O_HB16TIME + (ui32CS << 2))) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the PSRAM configuration register. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! \param ui32CR is the PSRAM configuration register value. -//! -//! This function sets the PSRAM's configuration register by using the PSRAM -//! configuration register enable signal. The Host-bus 16 interface mode -//! should be configured prior to calling this function. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The parameter \e ui32CR value is determined by -//! consulting the PSRAM's data sheet. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Setup for the PSRAM configuration register write. Only 21 bits are - // valid on a write. - // - HWREG(ui32Base + EPI_O_HBPSRAM) = (ui32CR & 0x1fffff); - - // - // Set the PSRAM configuration register write enable. - // - HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_WRCRE; -} - -//***************************************************************************** -// -//! Requests a configuration register read from the PSRAM. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! -//! This function requests a read of the PSRAM's configuration register. The -//! Host-bus 16 interface mode should be configured prior to calling this -//! function. -//! The EPIPSRAMConfigRegGet() and EPIPSRAMConfigRegGetNonBlocking() can -//! be used to retrieve the configuration register value. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return none. -// -//***************************************************************************** -void -EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Set the PSRAM configuration register read enable. - // - HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_RDCRE; -} - -//***************************************************************************** -// -//! Retrieves the contents of the EPI PSRAM configuration register. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! \param pui32CR is the provided storage used to hold the register value. -//! -//! This function copies the contents of the EPI PSRAM configuration register -//! to the provided storage if the PSRAM read configuration register enable -//! is no longer asserted. Otherwise the provided storage is not modified. -//! -//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() -//! should be called prior to calling this function. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. The \e pui32CR parameter is a pointer to provided -//! storage used to hold the register value. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return \b true if the value was copied to the provided storage and -//! \b false if it was not. -// -//***************************************************************************** -bool -EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS, - uint32_t *pui32CR) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Verify PSRAM read enable is not asserted. - // - if(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE) - { - return(false); - } - - // - // Copy the PSRAM configuration register value to the provided storage. - // Only the lower 16 bits are valid on a read. - // - *pui32CR = HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff; - - // - // Notify caller the provided storage holds the EPI PSRAM configuration - // register contents. - // - return(true); -} - -//***************************************************************************** -// -//! Retrieves the contents of the EPI PSRAM configuration register. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32CS is the chip select target. -//! -//! This function retrieves the EPI PSRAM configuration register. The register -//! is read once the EPI PSRAM configuration register read enable signal is -//! de-asserted. -//! -//! The Host-bus 16 interface mode should be set up and EPIPSRAMConfigRegRead() -//! should be called prior to calling this function. -//! -//! The \e ui32Base parameter is the base address for the EPI hardware module. -//! The \e ui32CS parameter specifies the chip select to configure and has a -//! valid range of 0-3. -//! -//! \note The availability of PSRAM support varies based on the Tiva part -//! in use. Please consult the data sheet to determine if this feature is -//! available. -//! -//! \return none. -// -//***************************************************************************** -uint32_t -EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32CS < 4); - - // - // Determine the register offset based on the ui32CS provided. - // - if(ui32CS < 2) - { - ui32Offset = EPI_O_HB16CFG + (ui32CS << 2); - } - else - { - ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2); - } - - // - // Wait for PSRAM read enable to deassert if necessary. - // - while(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE) - { - } - - // - // Return the EPI PSRAM configuration register contents. - // Only the lower 16 bits are valid on a read. - // - return(HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff); -} - -//***************************************************************************** -// -//! Configures the interface for general-purpose mode operation. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the interface configuration. -//! \param ui32FrameCount is the frame size in clocks, if the frame signal -//! is used (0-15). -//! \param ui32MaxWait is currently not used. -//! -//! This function is used to configure the interface when used in -//! general-purpose operation as chosen with the function EPIModeSet(). The -//! parameter \e ui32Config is the logical OR of the following: -//! -//! - \b EPI_GPMODE_CLKPIN interface clock as output on a pin. -//! - \b EPI_GPMODE_CLKGATE clock is stopped when there is no transaction, -//! otherwise it is free-running. -//! - \b EPI_GPMODE_FRAME50 framing signal is 50/50 duty cycle, otherwise it -//! is a pulse. -//! - \b EPI_GPMODE_WRITE2CYCLE a two-cycle write is used, otherwise a -//! single-cycle write is used. -//! - Address bus size, select one of: -//! - \b EPI_GPMODE_ASIZE_NONE sets no address bus. -//! - \b EPI_GPMODE_ASIZE_4 sets an address bus size of 4 bits. -//! - \b EPI_GPMODE_ASIZE_12 sets an address bus size of 12 bits. -//! - \b EPI_GPMODE_ASIZE_20 sets an address bus size of 20 bits. -//! - Data bus size, select one of: -//! - \b EPI_GPMODE_DSIZE_8 sets a data bus size of 8 bits. -//! - \b EPI_GPMODE_DSIZE_16 sets a data bus size of 16 bits. -//! - \b EPI_GPMODE_DSIZE_24 sets a data bus size of 24 bits. -//! - \b EPI_GPMODE_DSIZE_32 sets a data bus size of 32 bits. -//! -//! The parameter \e ui32FrameCount is the number of clocks used to form the -//! framing signal, if the framing signal is used. The behavior depends on -//! whether the frame signal is a pulse or a 50/50 duty cycle. -//! -//! -//! \return None. -// -//***************************************************************************** -void -EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32FrameCount, uint32_t ui32MaxWait) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32FrameCount < 16); - ASSERT(ui32MaxWait < 256); - - // - // Fill in the frame count field of the configuration word. - // - ui32Config &= ~EPI_GPCFG_FRMCNT_M; - ui32Config |= ui32FrameCount << EPI_GPCFG_FRMCNT_S; - - // - // Write the non-moded configuration register. - // - HWREG(ui32Base + EPI_O_GPCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the address map for the external interface. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Map is the address mapping configuration. -//! -//! This function is used to configure the address mapping for the external -//! interface, which then determines the base address of the external memory or -//! device within the processor peripheral and/or memory space. -//! -//! The parameter \e ui32Map is the logical OR of the following: -//! -//! - Peripheral address space size, select one of: -//! - \b EPI_ADDR_PER_SIZE_256B sets the peripheral address space to 256 -//! bytes. -//! - \b EPI_ADDR_PER_SIZE_64KB sets the peripheral address space to 64 -//! Kbytes. -//! - \b EPI_ADDR_PER_SIZE_16MB sets the peripheral address space to 16 -//! Mbytes. -//! - \b EPI_ADDR_PER_SIZE_256MB sets the peripheral address space to 256 -//! Mbytes. -//! - Peripheral base address, select one of: -//! - \b EPI_ADDR_PER_BASE_NONE sets the peripheral base address to none. -//! - \b EPI_ADDR_PER_BASE_A sets the peripheral base address to -//! 0xA0000000. -//! - \b EPI_ADDR_PER_BASE_C sets the peripheral base address to -//! 0xC0000000. -//! - RAM address space, select one of: -//! - \b EPI_ADDR_RAM_SIZE_256B sets the RAM address space to 256 bytes. -//! - \b EPI_ADDR_RAM_SIZE_64KB sets the RAM address space to 64 Kbytes. -//! - \b EPI_ADDR_RAM_SIZE_16MB sets the RAM address space to 16 Mbytes. -//! - \b EPI_ADDR_RAM_SIZE_256MB sets the RAM address space to 256 Mbytes. -//! - RAM base address, select one of: -//! - \b EPI_ADDR_RAM_BASE_NONE sets the RAM space address to none. -//! - \b EPI_ADDR_RAM_BASE_6 sets the RAM space address to 0x60000000. -//! - \b EPI_ADDR_RAM_BASE_8 sets the RAM space address to 0x80000000. -//! - \b EPI_ADDR_RAM_QUAD_MODE maps CS0n to 0x60000000, CS1n to 0x80000000, -//! CS2n to 0xA0000000, and CS3n to 0xC0000000. -//! - \b EPI_ADDR_CODE_SIZE_256B sets an external code size of 256 bytes, range -//! 0x00 to 0xFF. -//! - \b EPI_ADDR_CODE_SIZE_64KB sets an external code size of 64 Kbytes, range -//! 0x0000 to 0xFFFF. -//! - \b EPI_ADDR_CODE_SIZE_16MB sets an external code size of 16 Mbytes, range -//! 0x000000 to 0xFFFFFF. -//! - \b EPI_ADDR_CODE_SIZE_256MB sets an external code size of 256 Mbytes, -//! range 0x0000000 to 0xFFFFFFF. -//! - \b EPI_ADDR_CODE_BASE_NONE sets external code base to not mapped. -//! - \b EPI_ADDR_CODE_BASE_1 sets external code base to 0x10000000. -//! -//! \note The availability of \b EPI_ADDR_RAM_QUAD_MODE and \b EPI_ADDR_CODE_* -//! varies based on the Tiva part in use. Please consult the data sheet -//! to determine if these features are available. -//! -//! \return None. -// -//***************************************************************************** -void -EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Map < 0x1000); - - // - // Set the value of the address mapping register. - // - HWREG(ui32Base + EPI_O_ADDRMAP) = ui32Map; -} - -//***************************************************************************** -// -//! Configures a non-blocking read transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! \param ui32DataSize is the size of the data items to read. -//! \param ui32Address is the starting address to read. -//! -//! This function is used to configure a non-blocking read channel for a -//! transaction. Two channels are available that can be used in a ping-pong -//! method for continuous reading. It is not necessary to use both channels -//! to perform a non-blocking read. -//! -//! The parameter \e ui8DataSize is one of \b EPI_NBCONFIG_SIZE_8, -//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit, -//! or 32-bit sized data transfers. -//! -//! The parameter \e ui32Address is the starting address for the read, relative -//! to the external device. The start of the device is address 0. -//! -//! Once configured, the non-blocking read is started by calling -//! EPINonBlockingReadStart(). If the addresses to be read from the device -//! are in a sequence, it is not necessary to call this function multiple -//! times. Until it is changed, the EPI module stores the last address -//! that was used for a non-blocking read (per channel). -//! -//! \return None. -// -//***************************************************************************** -void -EPINonBlockingReadConfigure(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32DataSize, uint32_t ui32Address) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - ASSERT(ui32DataSize < 4); - ASSERT(ui32Address < 0x20000000); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RSIZE1 - EPI_O_RSIZE0); - - // - // Write the data size register for the channel. - // - HWREG(ui32Base + EPI_O_RSIZE0 + ui32Offset) = ui32DataSize; - - // - // Write the starting address register for the channel. - // - HWREG(ui32Base + EPI_O_RADDR0 + ui32Offset) = ui32Address; -} - -//***************************************************************************** -// -//! Starts a non-blocking read transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! \param ui32Count is the number of items to read (1-4095). -//! -//! This function starts a non-blocking read that was previously configured -//! with the function EPINonBlockingReadConfigure(). Once this function is -//! called, the EPI module begins reading data from the external device -//! into the read FIFO. The EPI stops reading when the FIFO fills up -//! and resumes reading when the application drains the FIFO, until the -//! total specified count of data items has been read. -//! -//! Once a read transaction is completed and the FIFO drained, another -//! transaction can be started from the next address by calling this -//! function again. -//! -//! \return None. -// -//***************************************************************************** -void -EPINonBlockingReadStart(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Count) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - ASSERT(ui32Count < 4096); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); - - // - // Write to the read count register. - // - HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = ui32Count; -} - -//***************************************************************************** -// -//! Stops a non-blocking read transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! -//! This function cancels a non-blocking read transaction that is already -//! in progress. -//! -//! \return None. -// -//***************************************************************************** -void -EPINonBlockingReadStop(uint32_t ui32Base, uint32_t ui32Channel) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); - - // - // Write a 0 to the read count register, which cancels the transaction. - // - HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = 0; -} - -//***************************************************************************** -// -//! Get the count remaining for a non-blocking transaction. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Channel is the read channel (0 or 1). -//! -//! This function gets the remaining count of items for a non-blocking read -//! transaction. -//! -//! \return The number of items remaining in the non-blocking read transaction. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadCount(uint32_t ui32Base, uint32_t ui32Channel) -{ - uint32_t ui32Offset; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Channel < 2); - - // - // Compute the offset needed to select the correct channel regs. - // - ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0); - - // - // Read the count remaining and return the value to the caller. - // - return(HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset)); -} - -//***************************************************************************** -// -//! Get the count of items available in the read FIFO. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function gets the number of items that are available to read in -//! the read FIFO. The read FIFO is filled by a non-blocking read transaction -//! which is configured by the functions EPINonBlockingReadConfigure() and -//! EPINonBlockingReadStart(). -//! -//! \return The number of items available to read in the read FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadAvail(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Read the FIFO count and return it to the caller. - // - return(HWREG(ui32Base + EPI_O_RFIFOCNT)); -} - -//***************************************************************************** -// -//! Read available data from the read FIFO, as 32-bit data items. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the maximum count of items to read. -//! \param pui32Buf is the caller supplied buffer where the read data is -//! stored. -//! -//! This function reads 32-bit data items from the read FIFO and stores -//! the values in a caller-supplied buffer. The function reads and stores -//! data from the FIFO until there is no more data in the FIFO or the maximum -//! count is reached as specified in the parameter \e ui32Count. The actual -//! count of items is returned. -//! -//! \return The number of items read from the FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadGet32(uint32_t ui32Base, uint32_t ui32Count, - uint32_t *pui32Buf) -{ - uint32_t ui32CountRead = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count < 4096); - ASSERT(pui32Buf); - - // - // Read from the FIFO while there are any items to read and - // the caller's specified count is not exceeded. - // - while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) - { - // - // Read from the FIFO and store in the caller supplied buffer. - // - *pui32Buf = HWREG(ui32Base + EPI_O_READFIFO0); - - // - // Update the caller's buffer pointer and the count of items read. - // - pui32Buf++; - ui32CountRead++; - } - - // - // Return the count of items read to the caller. - // - return(ui32CountRead); -} - -//***************************************************************************** -// -//! Read available data from the read FIFO, as 16-bit data items. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the maximum count of items to read. -//! \param pui16Buf is the caller-supplied buffer where the read data is -//! stored. -//! -//! This function reads 16-bit data items from the read FIFO and stores -//! the values in a caller-supplied buffer. The function reads and stores -//! data from the FIFO until there is no more data in the FIFO or the maximum -//! count is reached as specified in the parameter \e ui32Count. The actual -//! count of items is returned. -//! -//! \return The number of items read from the FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadGet16(uint32_t ui32Base, uint32_t ui32Count, - uint16_t *pui16Buf) -{ - uint32_t ui32CountRead = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count < 4096); - ASSERT(pui16Buf); - - // - // Read from the FIFO while there are any items to read, and - // the caller's specified count is not exceeded. - // - while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) - { - // - // Read from the FIFO and store in the caller-supplied buffer. - // - *pui16Buf = (uint16_t)HWREG(ui32Base + EPI_O_READFIFO0); - - // - // Update the caller's buffer pointer and the count of items read. - // - pui16Buf++; - ui32CountRead++; - } - - // - // Return the count of items read to the caller. - // - return(ui32CountRead); -} - -//***************************************************************************** -// -//! Read available data from the read FIFO, as 8-bit data items. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Count is the maximum count of items to read. -//! \param pui8Buf is the caller-supplied buffer where the read data is -//! stored. -//! -//! This function reads 8-bit data items from the read FIFO and stores -//! the values in a caller-supplied buffer. The function reads and stores -//! data from the FIFO until there is no more data in the FIFO or the maximum -//! count is reached as specified in the parameter \e ui32Count. The actual -//! count of items is returned. -//! -//! \return The number of items read from the FIFO. -// -//***************************************************************************** -uint32_t -EPINonBlockingReadGet8(uint32_t ui32Base, uint32_t ui32Count, - uint8_t *pui8Buf) -{ - uint32_t ui32CountRead = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Count < 4096); - ASSERT(pui8Buf); - - // - // Read from the FIFO while there are any items to read, and - // the caller's specified count is not exceeded. - // - while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--) - { - // - // Read from the FIFO and store in the caller supplied buffer. - // - *pui8Buf = (uint8_t)HWREG(ui32Base + EPI_O_READFIFO0); - - // - // Update the caller's buffer pointer and the count of items read. - // - pui8Buf++; - ui32CountRead++; - } - - // - // Return the count of items read to the caller. - // - return(ui32CountRead); -} - -//***************************************************************************** -// -//! Configures the read FIFO. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32Config is the FIFO configuration. -//! -//! This function configures the FIFO trigger levels and error -//! generation. The parameter \e ui32Config is the logical OR of the -//! following: -//! -//! - \b EPI_FIFO_CONFIG_WTFULLERR enables an error interrupt when a write is -//! attempted and the write FIFO is full -//! - \b EPI_FIFO_CONFIG_RSTALLERR enables an error interrupt when a read is -//! stalled due to an interleaved write or other reason -//! - FIFO TX trigger level, select one of: -//! - \b EPI_FIFO_CONFIG_TX_EMPTY sets the FIFO TX trigger level to empty. -//! - \b EPI_FIFO_CONFIG_TX_1_4 sets the FIFO TX trigger level to 1/4. -//! - \b EPI_FIFO_CONFIG_TX_1_2 sets the FIFO TX trigger level to 1/2. -//! - \b EPI_FIFO_CONFIG_TX_3_4 sets the FIFO TX trigger level to 3/4. -//! - FIFO RX trigger level, select one of: -//! - \b EPI_FIFO_CONFIG_RX_1_8 sets the FIFO RX trigger level to 1/8. -//! - \b EPI_FIFO_CONFIG_RX_1_4 sets the FIFO RX trigger level to 1/4. -//! - \b EPI_FIFO_CONFIG_RX_1_2 sets the FIFO RX trigger level to 1/2. -//! - \b EPI_FIFO_CONFIG_RX_3_4 sets the FIFO RX trigger level to 3/4. -//! - \b EPI_FIFO_CONFIG_RX_7_8 sets the FIFO RX trigger level to 7/8. -//! - \b EPI_FIFO_CONFIG_RX_FULL sets the FIFO RX trigger level to full. -//! -//! \return None. -// -//***************************************************************************** -void -EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32Config == (ui32Config & 0x00030077)); - - // - // Load the configuration into the FIFO config reg. - // - HWREG(ui32Base + EPI_O_FIFOLVL) = ui32Config; -} - -//***************************************************************************** -// -//! Reads the number of empty slots in the write transaction FIFO. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function returns the number of slots available in the transaction -//! FIFO. It can be used in a polling method to avoid attempting a write -//! that would stall. -//! -//! \return The number of empty slots in the transaction FIFO. -// -//***************************************************************************** -uint32_t -EPIWriteFIFOCountGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Read the FIFO count and return it to the caller. - // - return(HWREG(ui32Base + EPI_O_WFIFOCNT)); -} - -//***************************************************************************** -// -//! Enables EPI interrupt sources. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the specified EPI sources to generate interrupts. -//! The \e ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. -//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. -//! - \b EPI_INT_ERR interrupt when an error condition occurs. -//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. -//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. -//! -//! \return Returns None. -// -//***************************************************************************** -void -EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32IntFlags < 17); - - // - // Write the interrupt flags mask to the mask register. - // - HWREG(ui32Base + EPI_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables EPI interrupt sources. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! This function disables the specified EPI sources for interrupt -//! generation. The \e ui32IntFlags parameter can be the logical OR of any of -//! the following values: -//! -//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. -//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. -//! - \b EPI_INT_ERR interrupt when an error condition occurs. -//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. -//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. -//! -//! \return Returns None. -// -//***************************************************************************** -void -EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32IntFlags < 17); - - // - // Write the interrupt flags mask to the mask register. - // - HWREG(ui32Base + EPI_O_IM) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the EPI interrupt status. -//! -//! \param ui32Base is the EPI module base address. -//! \param bMasked is set \b true to get the masked interrupt status, or -//! \b false to get the raw interrupt status. -//! -//! This function returns the EPI interrupt status. It can return either -//! the raw or masked interrupt status. -//! -//! \return Returns the masked or raw EPI interrupt status, as a bit field -//! of any of the following values: -//! -//! - \b EPI_INT_TXREQ interrupt when transmit FIFO is below the trigger level. -//! - \b EPI_INT_RXREQ interrupt when read FIFO is above the trigger level. -//! - \b EPI_INT_ERR interrupt when an error condition occurs. -//! - \b EPI_INT_DMA_TX_DONE interrupt when the transmit DMA completes. -//! - \b EPI_INT_DMA_RX_DONE interrupt when the read DMA completes. -// -//***************************************************************************** -uint32_t -EPIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + EPI_O_MIS)); - } - else - { - return(HWREG(ui32Base + EPI_O_RIS)); - } -} - -//***************************************************************************** -// -//! Gets the EPI error interrupt status. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function returns the error status of the EPI. If the return value of -//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this -//! function can be used to determine the cause of the error. -//! -//! \return Returns a bit mask of error flags, which can be the logical -//! OR of any of the following: -//! -//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction -//! FIFO was full -//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled -//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held -//! off a transaction longer than the configured maximum wait time -// -//***************************************************************************** -uint32_t -EPIIntErrorStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Read the error status and return to caller. - // - return(HWREG(ui32Base + EPI_O_EISC)); -} - -//***************************************************************************** -// -//! Clears pending EPI error sources. -//! -//! \param ui32Base is the EPI module base address. -//! \param ui32ErrFlags is a bit mask of the error sources to be cleared. -//! -//! This function clears the specified pending EPI errors. The \e ui32ErrFlags -//! parameter can be the logical OR of any of the following values: -//! -//! - \b EPI_INT_ERR_DMAWRIC clears the EPI_INT_DMA_TX_DONE as an interrupt -//! source -//! - \b EPI_INT_ERR_DMARDIC clears the EPI_INT_DMA_RX_DONE as an interrupt -//! source -//! - \b EPI_INT_ERR_WTFULL occurs when a write stalled when the transaction -//! FIFO was full -//! - \b EPI_INT_ERR_RSTALL occurs when a read stalled -//! - \b EPI_INT_ERR_TIMEOUT occurs when the external clock enable held -//! off a transaction longer than the configured maximum wait time -//! -//! \return Returns None. -// -//***************************************************************************** -void -EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(ui32ErrFlags < 0x20); - - // - // Write the error flags to the register to clear the pending errors. - // - HWREG(ui32Base + EPI_O_EISC) = ui32ErrFlags; -} - -//***************************************************************************** -// -//! Returns the interrupt number for a given EPI base address. -//! -//! \param ui32Base is the base address of the EPI module. -//! -//! This function returns the interrupt number for the EPI module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns the EPI interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_EPIIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // By default, assume EPI is not supported. - // - ui32Int = 0; - - if(CLASS_IS_TM4C129) - { - ui32Int = INT_EPI0_TM4C129; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This sets and enables the handler to be called when the EPI module -//! generates an interrupt. Specific EPI interrupts must still be enabled -//! with the EPIIntEnable() function. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - ASSERT(pfnHandler); - - // - // Get the interrupt number for the EPI interface. - // - ui32Int = _EPIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the EPI interface interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes a registered interrupt handler for the EPI module. -//! -//! \param ui32Base is the EPI module base address. -//! -//! This function disables and clears the handler to be called when the -//! EPI interrupt occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -EPIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == EPI0_BASE); - - // - // Get the interrupt number for the EPI interface. - // - ui32Int = _EPIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the EPI interface interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/epi.h b/bsp/tm4c129x-dk/libraries/driverlib/epi.h deleted file mode 100644 index fc26a81469..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/epi.h +++ /dev/null @@ -1,762 +0,0 @@ -//***************************************************************************** -// -// epi.h - Prototypes and macros for the EPI module. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_EPI_H__ -#define __DRIVERLIB_EPI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to EPIModeSet() -// -//***************************************************************************** -#define EPI_MODE_GENERAL 0x00000010 -#define EPI_MODE_SDRAM 0x00000011 -#define EPI_MODE_HB8 0x00000012 -#define EPI_MODE_HB16 0x00000013 -#define EPI_MODE_DISABLE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigSDRAMSet() -// -//***************************************************************************** -#define EPI_SDRAM_CORE_FREQ_0_15 \ - 0x00000000 -#define EPI_SDRAM_CORE_FREQ_15_30 \ - 0x40000000 -#define EPI_SDRAM_CORE_FREQ_30_50 \ - 0x80000000 -#define EPI_SDRAM_CORE_FREQ_50_100 \ - 0xC0000000 -#define EPI_SDRAM_LOW_POWER 0x00000200 -#define EPI_SDRAM_FULL_POWER 0x00000000 -#define EPI_SDRAM_SIZE_64MBIT 0x00000000 -#define EPI_SDRAM_SIZE_128MBIT 0x00000001 -#define EPI_SDRAM_SIZE_256MBIT 0x00000002 -#define EPI_SDRAM_SIZE_512MBIT 0x00000003 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigGPModeSet() -// -//***************************************************************************** -#define EPI_GPMODE_CLKPIN 0x80000000 -#define EPI_GPMODE_CLKGATE 0x40000000 -#define EPI_GPMODE_FRAME50 0x04000000 -#define EPI_GPMODE_WRITE2CYCLE 0x00080000 -#define EPI_GPMODE_ASIZE_NONE 0x00000000 -#define EPI_GPMODE_ASIZE_4 0x00000010 -#define EPI_GPMODE_ASIZE_12 0x00000020 -#define EPI_GPMODE_ASIZE_20 0x00000030 -#define EPI_GPMODE_DSIZE_8 0x00000000 -#define EPI_GPMODE_DSIZE_16 0x00000001 -#define EPI_GPMODE_DSIZE_24 0x00000002 -#define EPI_GPMODE_DSIZE_32 0x00000003 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB8ModeSet() -// -//***************************************************************************** -#define EPI_HB8_USE_TXEMPTY 0x00800000 -#define EPI_HB8_USE_RXFULL 0x00400000 -#define EPI_HB8_WRHIGH 0x00200000 -#define EPI_HB8_RDHIGH 0x00100000 -#define EPI_HB8_ALE_HIGH 0x00080000 -#define EPI_HB8_ALE_LOW 0x00000000 -#define EPI_HB8_WRWAIT_0 0x00000000 -#define EPI_HB8_WRWAIT_1 0x00000040 -#define EPI_HB8_WRWAIT_2 0x00000080 -#define EPI_HB8_WRWAIT_3 0x000000C0 -#define EPI_HB8_RDWAIT_0 0x00000000 -#define EPI_HB8_RDWAIT_1 0x00000010 -#define EPI_HB8_RDWAIT_2 0x00000020 -#define EPI_HB8_RDWAIT_3 0x00000030 -#define EPI_HB8_MODE_ADMUX 0x00000000 -#define EPI_HB8_MODE_ADDEMUX 0x00000001 -#define EPI_HB8_MODE_SRAM 0x00000002 -#define EPI_HB8_MODE_FIFO 0x00000003 -#define EPI_HB8_WORD_ACCESS 0x00000100 -#define EPI_HB8_CSCFG_ALE 0x00000000 -#define EPI_HB8_CSCFG_CS 0x00000200 -#define EPI_HB8_CSCFG_DUAL_CS 0x00000400 -#define EPI_HB8_CSCFG_ALE_DUAL_CS \ - 0x00000600 -#define EPI_HB8_CSCFG_ALE_SINGLE_CS \ - 0x00001000 -#define EPI_HB8_CSCFG_QUAD_CS 0x00001200 -#define EPI_HB8_CSCFG_ALE_QUAD_CS \ - 0x00001400 -#define EPI_HB8_CSBAUD 0x00000800 -#define EPI_HB8_CLOCK_GATE 0x80000000 -#define EPI_HB8_CLOCK_GATE_IDLE \ - 0x40000000 -#define EPI_HB8_CLOCK_INVERT 0x20000000 -#define EPI_HB8_IN_READY_EN 0x10000000 -#define EPI_HB8_IN_READY_EN_INVERT \ - 0x18000000 -#define EPI_HB8_CSCFG_MASK 0x00001600 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB16ModeSet() -// -//***************************************************************************** -#define EPI_HB16_USE_TXEMPTY 0x00800000 -#define EPI_HB16_USE_RXFULL 0x00400000 -#define EPI_HB16_WRHIGH 0x00200000 -#define EPI_HB16_RDHIGH 0x00100000 -#define EPI_HB16_WRWAIT_0 0x00000000 -#define EPI_HB16_WRWAIT_1 0x00000040 -#define EPI_HB16_WRWAIT_2 0x00000080 -#define EPI_HB16_WRWAIT_3 0x000000C0 -#define EPI_HB16_RDWAIT_0 0x00000000 -#define EPI_HB16_RDWAIT_1 0x00000010 -#define EPI_HB16_RDWAIT_2 0x00000020 -#define EPI_HB16_RDWAIT_3 0x00000030 -#define EPI_HB16_MODE_ADMUX 0x00000000 -#define EPI_HB16_MODE_ADDEMUX 0x00000001 -#define EPI_HB16_MODE_SRAM 0x00000002 -#define EPI_HB16_MODE_FIFO 0x00000003 -#define EPI_HB16_BSEL 0x00000004 -#define EPI_HB16_WORD_ACCESS 0x00000100 -#define EPI_HB16_CSCFG_ALE 0x00000000 -#define EPI_HB16_CSCFG_CS 0x00000200 -#define EPI_HB16_CSCFG_DUAL_CS 0x00000400 -#define EPI_HB16_CSCFG_ALE_DUAL_CS \ - 0x00000600 -#define EPI_HB16_CSCFG_ALE_SINGLE_CS \ - 0x00001000 -#define EPI_HB16_CSCFG_QUAD_CS 0x00001200 -#define EPI_HB16_CSCFG_ALE_QUAD_CS \ - 0x00001400 -#define EPI_HB16_CLOCK_GATE 0x80000000 -#define EPI_HB16_CLOCK_GATE_IDLE \ - 0x40000000 -#define EPI_HB16_CLOCK_INVERT 0x20000000 -#define EPI_HB16_IN_READY_EN 0x10000000 -#define EPI_HB16_IN_READY_EN_INVERTED \ - 0x18000000 -#define EPI_HB16_ALE_HIGH 0x00080000 -#define EPI_HB16_ALE_LOW 0x00000000 -#define EPI_HB16_BURST_TRAFFIC 0x00010000 -#define EPI_HB16_CSBAUD 0x00000800 -#define EPI_HB16_CSCFG_MASK 0x00001600 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB8TimingSet(). -// -//***************************************************************************** -#define EPI_HB8_IN_READY_DELAY_1 \ - 0x01000000 -#define EPI_HB8_IN_READY_DELAY_2 \ - 0x02000000 -#define EPI_HB8_IN_READY_DELAY_3 \ - 0x03000000 -#define EPI_HB8_CAP_WIDTH_1 0x00001000 -#define EPI_HB8_CAP_WIDTH_2 0x00002000 -#define EPI_HB8_WRWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB8_WRWAIT_MINUS_ENABLE \ - 0x00000010 -#define EPI_HB8_RDWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB8_RDWAIT_MINUS_ENABLE \ - 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EPIConfigHB16TimingSet(). -// -//***************************************************************************** -#define EPI_HB16_IN_READY_DELAY_1 \ - 0x01000000 -#define EPI_HB16_IN_READY_DELAY_2 \ - 0x02000000 -#define EPI_HB16_IN_READY_DELAY_3 \ - 0x03000000 -#define EPI_HB16_PSRAM_NO_LIMIT 0x00000000 -#define EPI_HB16_PSRAM_128 0x00010000 -#define EPI_HB16_PSRAM_256 0x00020000 -#define EPI_HB16_PSRAM_512 0x00030000 -#define EPI_HB16_PSRAM_1024 0x00040000 -#define EPI_HB16_PSRAM_2048 0x00050000 -#define EPI_HB16_PSRAM_4096 0x00060000 -#define EPI_HB16_PSRAM_8192 0x00070000 -#define EPI_HB16_CAP_WIDTH_1 0x00001000 -#define EPI_HB16_CAP_WIDTH_2 0x00002000 -#define EPI_HB16_WRWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB16_WRWAIT_MINUS_ENABLE \ - 0x00000008 -#define EPI_HB16_RDWAIT_MINUS_DISABLE \ - 0x00000000 -#define EPI_HB16_RDWAIT_MINUS_ENABLE \ - 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EPIAddressMapSet(). -// -//***************************************************************************** -#define EPI_ADDR_PER_SIZE_256B 0x00000000 -#define EPI_ADDR_PER_SIZE_64KB 0x00000040 -#define EPI_ADDR_PER_SIZE_16MB 0x00000080 -#define EPI_ADDR_PER_SIZE_256MB 0x000000C0 -#define EPI_ADDR_PER_BASE_NONE 0x00000000 -#define EPI_ADDR_PER_BASE_A 0x00000010 -#define EPI_ADDR_PER_BASE_C 0x00000020 -#define EPI_ADDR_RAM_SIZE_256B 0x00000000 -#define EPI_ADDR_RAM_SIZE_64KB 0x00000004 -#define EPI_ADDR_RAM_SIZE_16MB 0x00000008 -#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C -#define EPI_ADDR_RAM_BASE_NONE 0x00000000 -#define EPI_ADDR_RAM_BASE_6 0x00000001 -#define EPI_ADDR_RAM_BASE_8 0x00000002 -#define EPI_ADDR_QUAD_MODE 0x00000033 -#define EPI_ADDR_CODE_SIZE_256B 0x00000000 -#define EPI_ADDR_CODE_SIZE_64KB 0x00000400 -#define EPI_ADDR_CODE_SIZE_16MB 0x00000800 -#define EPI_ADDR_CODE_SIZE_256MB \ - 0x00000C00 -#define EPI_ADDR_CODE_BASE_NONE 0x00000000 -#define EPI_ADDR_CODE_BASE_1 0x00000100 - -//***************************************************************************** -// -// Values that can be passed to EPINonBlockingReadConfigure() -// -//***************************************************************************** -#define EPI_NBCONFIG_SIZE_8 1 -#define EPI_NBCONFIG_SIZE_16 2 -#define EPI_NBCONFIG_SIZE_32 3 - -//***************************************************************************** -// -// Values that can be passed to EPIFIFOConfig() -// -//***************************************************************************** -#define EPI_FIFO_CONFIG_WTFULLERR \ - 0x00020000 -#define EPI_FIFO_CONFIG_RSTALLERR \ - 0x00010000 -#define EPI_FIFO_CONFIG_TX_EMPTY \ - 0x00000000 -#define EPI_FIFO_CONFIG_TX_1_4 0x00000020 -#define EPI_FIFO_CONFIG_TX_1_2 0x00000030 -#define EPI_FIFO_CONFIG_TX_3_4 0x00000040 -#define EPI_FIFO_CONFIG_RX_1_8 0x00000001 -#define EPI_FIFO_CONFIG_RX_1_4 0x00000002 -#define EPI_FIFO_CONFIG_RX_1_2 0x00000003 -#define EPI_FIFO_CONFIG_RX_3_4 0x00000004 -#define EPI_FIFO_CONFIG_RX_7_8 0x00000005 -#define EPI_FIFO_CONFIG_RX_FULL 0x00000006 - -//***************************************************************************** -// -// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned -// as flags from EPIIntStatus() -// -//***************************************************************************** -#define EPI_INT_DMA_TX_DONE 0x00000010 -#define EPI_INT_DMA_RX_DONE 0x00000008 -#define EPI_INT_TXREQ 0x00000004 -#define EPI_INT_RXREQ 0x00000002 -#define EPI_INT_ERR 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to EPIIntErrorClear(), or returned as flags from -// EPIIntErrorStatus() -// -//***************************************************************************** -#define EPI_INT_ERR_DMAWRIC 0x00000010 -#define EPI_INT_ERR_DMARDIC 0x00000008 -#define EPI_INT_ERR_WTFULL 0x00000004 -#define EPI_INT_ERR_RSTALL 0x00000002 -#define EPI_INT_ERR_TIMEOUT 0x00000001 - -#ifdef rvmdk -//***************************************************************************** -// -// Keil case. -// -//***************************************************************************** -inline void -EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) -{ - uint32_t ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the write we're actually interested in. - // - STR ui32Value, [pui32Addr] - - // - // Read from SRAM to ensure that we don't have an EPI write followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } -} - -inline uint32_t -EPIWorkaroundWordRead(uint32_t *pui32Addr) -{ - uint32_t ui32Value, ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the read we're actually interested in. - // - LDR ui32Value, [pui32Addr] - - // - // Read from SRAM to ensure that we don't have an EPI read followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } - - return(ui32Value); -} - -inline void -EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) -{ - uint32_t ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the write we're actually interested in. - // - STRH ui16Value, [pui16Addr] - - // - // Read from SRAM to ensure that we don't have an EPI write followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } -} - -inline uint16_t -EPIWorkaroundHWordRead(uint16_t *pui16Addr) -{ - uint32_t ui32Scratch; - uint16_t ui16Value; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the read we're actually interested in. - // - LDRH ui16Value, [pui16Addr] - - // - // Read from SRAM to ensure that we don't have an EPI read followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } - - return(ui16Value); -} - -inline void -EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) -{ - uint32_t ui32Scratch; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the write we're actually interested in. - // - STRB ui8Value, [pui8Addr] - - // - // Read from SRAM to ensure that we don't have an EPI write followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } -} - -inline uint8_t -EPIWorkaroundByteRead(uint8_t *pui8Addr) -{ - uint32_t ui32Scratch; - uint8_t ui8Value; - - __asm - { - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - NOP - - // - // Perform the read we're actually interested in. - // - LDRB ui8Value, [pui8Addr] - - // - // Read from SRAM to ensure that we don't have an EPI read followed by - // a flash read. - // - LDR ui32Scratch, [__current_sp()] - } - - return(ui8Value); -} -#endif - -#ifdef ccs -//***************************************************************************** -// -// Code Composer Studio versions of these functions can be found in separate -// source file epi_workaround_ccs.s. -// -//***************************************************************************** -extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value); -extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr); -extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value); -extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr); -extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value); -extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr); - -#endif - -#if (defined gcc) || (defined ewarm) || (defined sourcerygxx) || \ - (defined codered) -//***************************************************************************** -// -// GCC-based toolchain and IAR case. -// -//***************************************************************************** -inline void -EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value) -{ - volatile register uint32_t ui32Scratch; - - __asm volatile ( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " STR %[value],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui32Addr), [value] "r" (ui32Value) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; -} - -inline uint32_t -EPIWorkaroundWordRead(uint32_t *pui32Addr) -{ - volatile register uint32_t ui32Data, ui32Scratch; - - // - // ui32Scratch is not used other than to add a padding read following the - // "real" read. - // - - __asm volatile( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " LDR %[ret],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [ret] "=r" (ui32Data), - [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui32Addr) - ); - - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; - - return(ui32Data); -} - -inline void -EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value) -{ - volatile register uint32_t ui32Scratch; - - __asm volatile ( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " STRH %[value],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui16Addr), [value] "r" (ui16Value) - ); - - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; -} - -inline uint16_t -EPIWorkaroundHWordRead(uint16_t *pui16Addr) -{ - register uint16_t ui16Data; - register uint32_t ui32Scratch; - - // - // ui32Scratch is not used other than to add a padding read following the - // "real" read. - // - - __asm volatile( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " LDRH %[ret],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [ret] "=r" (ui16Data), - [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui16Addr) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; - - return(ui16Data); -} - -inline void -EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value) -{ - volatile register uint32_t ui32Scratch; - - __asm volatile ( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " STRB %[value],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui8Addr), [value] "r" (ui8Value) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; -} - -inline uint8_t -EPIWorkaroundByteRead(uint8_t *pui8Addr) -{ - register uint8_t ui8Data; - register uint32_t ui32Scratch; - - // - // ui32Scratch is not used other than to add a padding read following the - // "real" read. - // - - __asm volatile( - // - // Add a NOP to ensure we dont have a flash read immediately before - // the EPI read. - // - " NOP\n" - " LDRB %[ret],[%[addr]]\n" - " LDR %[scratch],[sp]\n" - : [ret] "=r" (ui8Data), - [scratch] "=r" (ui32Scratch) - : [addr] "r" (pui8Addr) - ); - - // - // Keep the compiler from generating a warning. - // - ui32Scratch = ui32Scratch; - - return(ui8Data); -} -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode); -extern void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider); -extern void EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Divider); -extern void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count); -extern void EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32FrameCount, uint32_t ui32MaxWait); -extern void EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxWait); -extern void EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxWait); -extern void EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32Config); -extern void EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, - uint32_t ui32CR); -extern void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS); -extern bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, - uint32_t ui32CS, - uint32_t *pui32CR); -extern uint32_t EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS); -extern void EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32Refresh); -extern void EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map); -extern void EPINonBlockingReadConfigure(uint32_t ui32Base, - uint32_t ui32Channel, - uint32_t ui32DataSize, - uint32_t ui32Address); -extern void EPINonBlockingReadStart(uint32_t ui32Base, - uint32_t ui32Channel, - uint32_t ui32Count); -extern void EPINonBlockingReadStop(uint32_t ui32Base, - uint32_t ui32Channel); -extern uint32_t EPINonBlockingReadCount(uint32_t ui32Base, - uint32_t ui32Channel); -extern uint32_t EPINonBlockingReadAvail(uint32_t ui32Base); -extern uint32_t EPINonBlockingReadGet32(uint32_t ui32Base, - uint32_t ui32Count, - uint32_t *pui32Buf); -extern uint32_t EPINonBlockingReadGet16(uint32_t ui32Base, - uint32_t ui32Count, - uint16_t *pui16Buf); -extern uint32_t EPINonBlockingReadGet8(uint32_t ui32Base, - uint32_t ui32Count, - uint8_t *pui8Buf); -extern void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config); -extern uint32_t EPIWriteFIFOCountGet(uint32_t ui32Base); -extern void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t EPIIntStatus(uint32_t ui32Base, bool bMasked); -extern uint32_t EPIIntErrorStatus(uint32_t ui32Base); -extern void EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags); -extern void EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void EPIIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_EPI_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/flash.c b/bsp/tm4c129x-dk/libraries/driverlib/flash.c deleted file mode 100644 index 158176a766..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/flash.c +++ /dev/null @@ -1,977 +0,0 @@ -//***************************************************************************** -// -// flash.c - Driver for programming the on-chip flash. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_flash.h" -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/flash.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Program Enable (FMPPE) register. -// -//***************************************************************************** -static const uint32_t g_pui32FMPPERegs[] = -{ - FLASH_FMPPE0, - FLASH_FMPPE1, - FLASH_FMPPE2, - FLASH_FMPPE3, - FLASH_FMPPE4, - FLASH_FMPPE5, - FLASH_FMPPE6, - FLASH_FMPPE7, - FLASH_FMPPE8, - FLASH_FMPPE9, - FLASH_FMPPE10, - FLASH_FMPPE11, - FLASH_FMPPE12, - FLASH_FMPPE13, - FLASH_FMPPE14, - FLASH_FMPPE15, -}; - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Read Enable (FMPRE) register. -// -//***************************************************************************** -static const uint32_t g_pui32FMPRERegs[] = -{ - FLASH_FMPRE0, - FLASH_FMPRE1, - FLASH_FMPRE2, - FLASH_FMPRE3, - FLASH_FMPRE4, - FLASH_FMPRE5, - FLASH_FMPRE6, - FLASH_FMPRE7, - FLASH_FMPRE8, - FLASH_FMPRE9, - FLASH_FMPRE10, - FLASH_FMPRE11, - FLASH_FMPRE12, - FLASH_FMPRE13, - FLASH_FMPRE14, - FLASH_FMPRE15, -}; - -//***************************************************************************** -// -//! Erases a block of flash. -//! -//! \param ui32Address is the start address of the flash block to be erased. -//! -//! This function erases a block of the on-chip flash. After erasing, the -//! block is filled with 0xFF bytes. Read-only and execute-only blocks cannot -//! be erased. -//! -//! The flash block size is device-class dependent. All TM4C123x devices use -//! 1-KB blocks but TM4C129x devices use 16-KB blocks. Please consult the -//! device datasheet to determine the block size in use. -//! -//! This function does not return until the block has been erased. -//! -//! \return Returns 0 on success, or -1 if an invalid block address was -//! specified or the block is write-protected. -// -//***************************************************************************** -int32_t -FlashErase(uint32_t ui32Address) -{ - // - // Check the arguments. - // - ASSERT(!(ui32Address & (FLASH_ERASE_SIZE - 1))); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | - FLASH_FCMISC_ERMISC); - - // - // Erase the block. - // - HWREG(FLASH_FMA) = ui32Address; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; - - // - // Wait until the block has been erased. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) - { - } - - // - // Return an error if an access violation or erase error occurred. - // - if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | - FLASH_FCRIS_ERRIS)) - { - return(-1); - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Programs flash. -//! -//! \param pui32Data is a pointer to the data to be programmed. -//! \param ui32Address is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ui32Count is the number of bytes to be programmed. Must be a -//! multiple of four. -//! -//! This function programs a sequence of words into the on-chip flash. -//! Because the flash is programmed one word at a time, the starting address -//! and byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function does not return until the data has been programmed. -//! -//! \return Returns 0 on success, or -1 if a programming error is encountered. -// -//***************************************************************************** -int32_t -FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, uint32_t ui32Count) -{ - // - // Check the arguments. - // - ASSERT(!(ui32Address & 3)); - ASSERT(!(ui32Count & 3)); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | - FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC); - - // - // Loop over the words to be programmed. - // - while(ui32Count) - { - // - // Set the address of this block of words. - // - HWREG(FLASH_FMA) = ui32Address & ~(0x7f); - - // - // Loop over the words in this 32-word block. - // - while(((ui32Address & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) && - (ui32Count != 0)) - { - // - // Write this word into the write buffer. - // - HWREG(FLASH_FWBN + (ui32Address & 0x7c)) = *pui32Data++; - ui32Address += 4; - ui32Count -= 4; - } - - // - // Program the contents of the write buffer into flash. - // - HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF; - - // - // Wait until the write buffer has been programmed. - // - while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF) - { - } - } - - // - // Return an error if an access violation occurred. - // - if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | - FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)) - { - return(-1); - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Gets the protection setting for a block of flash. -//! -//! \param ui32Address is the start address of the flash block to be queried. -//! -//! This function gets the current protection for the specified block of flash. -//! Refer to the device data sheet to determine the granularity for each -//! protection option. A block can be read/write, read-only, or execute-only. -//! Read/write blocks can be read, executed, erased, and programmed. Read-only -//! blocks can be read and executed. Execute-only blocks can only be executed; -//! processor and debugger data reads are not allowed. -//! -//! \return Returns the protection setting for this block. See -//! FlashProtectSet() for possible values. -// -//***************************************************************************** -tFlashProtection -FlashProtectGet(uint32_t ui32Address) -{ - uint32_t ui32FMPRE, ui32FMPPE; - uint32_t ui32Bank; - - // - // Check the argument. - // - ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1))); - - // - // Calculate the Flash Bank from Base Address, and mask off the Bank - // from ui32Address for subsequent reference. - // - ui32Bank = (((ui32Address / FLASH_PROTECT_SIZE) / 32) % 4); - ui32Address &= ((FLASH_PROTECT_SIZE * 32) - 1); - - // - // Read the appropriate flash protection registers for the specified - // flash bank. - // - ui32FMPRE = HWREG(g_pui32FMPRERegs[ui32Bank]); - ui32FMPPE = HWREG(g_pui32FMPPERegs[ui32Bank]); - - // - // Check the appropriate protection bits for the block of memory that - // is specified by the address. - // - switch((((ui32FMPRE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1) << 1) | - ((ui32FMPPE >> (ui32Address / FLASH_PROTECT_SIZE)) & 0x1)) - { - // - // This block is marked as execute only (that is, it can not be erased - // or programmed, and the only reads allowed are via the instruction - // fetch interface). - // - case 0: - case 1: - { - return(FlashExecuteOnly); - } - - // - // This block is marked as read only (that is, it can not be erased or - // programmed). - // - case 2: - { - return(FlashReadOnly); - } - - // - // This block is read/write; it can be read, erased, and programmed. - // - case 3: - default: - { - return(FlashReadWrite); - } - } -} - -//***************************************************************************** -// -//! Sets the protection setting for a block of flash. -//! -//! \param ui32Address is the start address of the flash block to be protected. -//! \param eProtect is the protection to be applied to the block. Can be one -//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. -//! -//! This function sets the protection for the specified block of flash. Refer -//! to the device data sheet to determine the granularity for each protection -//! option. Blocks that are read/write can be made read-only or execute-only. -//! Blocks that are read-only can be made execute-only. Blocks that are -//! execute-only cannot have their protection modified. Attempts to make the -//! block protection less stringent (that is, read-only to read/write) -//! result in a failure (and are prevented by the hardware). -//! -//! Changes to the flash protection are maintained only until the next reset. -//! This protocol allows the application to be executed in the desired flash -//! protection environment to check for inappropriate flash access (via the -//! flash interrupt). To make the flash protection permanent, use the -//! FlashProtectSave() function. -//! -//! \return Returns 0 on success, or -1 if an invalid address or an invalid -//! protection was specified. -// -//***************************************************************************** -int32_t -FlashProtectSet(uint32_t ui32Address, tFlashProtection eProtect) -{ - uint32_t ui32ProtectRE, ui32ProtectPE; - uint32_t ui32Bank; - - // - // Check the argument. - // - ASSERT(!(ui32Address & (FLASH_PROTECT_SIZE - 1))); - ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || - (eProtect == FlashExecuteOnly)); - - // - // Convert the address into a block number. - // - ui32Address /= FLASH_PROTECT_SIZE; - - // - // ui32Address contains a "raw" block number. Derive the Flash Bank from - // the "raw" block number, and convert ui32Address to a "relative" - // block number. - // - ui32Bank = ((ui32Address / 32) % 4); - ui32Address %= 32; - - // - // Get the current protection for the specified flash bank. - // - ui32ProtectRE = HWREG(g_pui32FMPRERegs[ui32Bank]); - ui32ProtectPE = HWREG(g_pui32FMPPERegs[ui32Bank]); - - // - // Set the protection based on the requested protection. - // - switch(eProtect) - { - // - // Make this block execute only. - // - case FlashExecuteOnly: - { - // - // Turn off the read and program bits for this block. - // - ui32ProtectRE &= ~(0x1 << ui32Address); - ui32ProtectPE &= ~(0x1 << ui32Address); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read only. - // - case FlashReadOnly: - { - // - // The block can not be made read only if it is execute only. - // - if(((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) - { - return(-1); - } - - // - // Make this block read only. - // - ui32ProtectPE &= ~(0x1 << ui32Address); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read/write. - // - case FlashReadWrite: - default: - { - // - // The block can not be made read/write if it is not already - // read/write. - // - if((((ui32ProtectRE >> ui32Address) & 0x1) != 0x1) || - (((ui32ProtectPE >> ui32Address) & 0x1) != 0x1)) - { - return(-1); - } - - // - // The block is already read/write, so there is nothing to do. - // - return(0); - } - } - - // - // Set the new protection for the specified flash bank. - // - HWREG(g_pui32FMPRERegs[ui32Bank]) = ui32ProtectRE; - HWREG(g_pui32FMPPERegs[ui32Bank]) = ui32ProtectPE; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Saves the flash protection settings. -//! -//! This function makes the currently programmed flash protection settings -//! permanent. This operation is non-reversible; a chip reset or power cycle -//! does not change the flash protection. -//! -//! This function does not return until the protection has been saved. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashProtectSave(void) -{ - uint32_t ui32Temp; - - // - // Save the entire bank of 8 flash protection registers. - // - for(ui32Temp = 0; ui32Temp < 8; ui32Temp++) - { - // - // Tell the flash controller to write the flash protection register. - // - HWREG(FLASH_FMA) = ui32Temp; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Gets the user registers. -//! -//! \param pui32User0 is a pointer to the location to store USER Register 0. -//! \param pui32User1 is a pointer to the location to store USER Register 1. -//! -//! This function reads the contents of user registers 0 and 1, and -//! stores them in the specified locations. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1) -{ - // - // Verify that the pointers are valid. - // - ASSERT(pui32User0 != 0); - ASSERT(pui32User1 != 0); - - // - // Get and store the current value of the user registers. - // - *pui32User0 = HWREG(FLASH_USERREG0); - *pui32User1 = HWREG(FLASH_USERREG1); - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the user registers. -//! -//! \param ui32User0 is the value to store in USER Register 0. -//! \param ui32User1 is the value to store in USER Register 1. -//! -//! This function sets the contents of the user registers 0 and 1 to -//! the specified values. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashUserSet(uint32_t ui32User0, uint32_t ui32User1) -{ - // - // Save the new values into the user registers. - // - HWREG(FLASH_USERREG0) = ui32User0; - HWREG(FLASH_USERREG1) = ui32User1; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Gets all the user registers. -//! -//! \param pui32User0 is a pointer to the location to store USER Register 0. -//! \param pui32User1 is a pointer to the location to store USER Register 1. -//! \param pui32User2 is a pointer to the location to store USER Register 2. -//! \param pui32User3 is a pointer to the location to store USER Register 3. -//! -//! This function reads the contents of user registers 0, 1, 2 and 3, and -//! stores them in the specified locations. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashAllUserRegisterGet(uint32_t *pui32User0, uint32_t *pui32User1, - uint32_t *pui32User2, uint32_t *pui32User3) -{ - // - // Verify that the pointers are valid. - // - ASSERT(pui32User0 != 0); - ASSERT(pui32User1 != 0); - ASSERT(pui32User2 != 0); - ASSERT(pui32User3 != 0); - - // - // Get and store the current value of the user registers. - // - *pui32User0 = HWREG(FLASH_USERREG0); - *pui32User1 = HWREG(FLASH_USERREG1); - *pui32User2 = HWREG(FLASH_USERREG2); - *pui32User3 = HWREG(FLASH_USERREG3); - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the user registers 0 to 3 -//! -//! \param ui32User0 is the value to store in USER Register 0. -//! \param ui32User1 is the value to store in USER Register 1. -//! \param ui32User2 is the value to store in USER Register 2. -//! \param ui32User3 is the value to store in USER Register 3. -//! -//! This function sets the contents of the user registers 0, 1, 2 and 3 to -//! the specified values. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashAllUserRegisterSet(uint32_t ui32User0, uint32_t ui32User1, - uint32_t ui32User2, uint32_t ui32User3) -{ - // - // Save the new values into the user registers. - // - HWREG(FLASH_USERREG0) = ui32User0; - HWREG(FLASH_USERREG1) = ui32User1; - HWREG(FLASH_USERREG2) = ui32User2; - HWREG(FLASH_USERREG3) = ui32User3; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Saves the user registers 0 and 1. -//! -//! This function makes the currently programmed user register 0 and 1 settings -//! permanent. This operation is non-reversible; a chip reset or power cycle -//! does not change the flash protection. -//! -//! This function does not return until the protection has been saved. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashUserSave(void) -{ - // - // Setting the MSB of FMA will trigger a permanent save of a USER - // register. Bit 0 will indicate User 0 (0) or User 1 (1). - // - HWREG(FLASH_FMA) = 0x80000000; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Tell the flash controller to write the USER1 Register. - // - HWREG(FLASH_FMA) = 0x80000001; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Saves the user registers. -//! -//! This function makes the currently programmed user register 0, 1, 2 and 3 -//! settings permanent. This operation is non-reversible; a chip reset or -//! power cycle does not change the flash protection. -//! -//! This function does not return until the protection has been saved. -//! -//! \note To ensure data integrity of the user registers, the commits should -//! not be interrupted with a power loss. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -int32_t -FlashAllUserRegisterSave(void) -{ - uint32_t ui32Index; - - // - // Setting the MSB of FMA will trigger a permanent save of a USER Register. - // The 2 least signigicant bits, specify the exact User Register to save. - // The value of the least significant bits for - // USER Register 0 is 00, - // USER Register 1 is 01, - // USER Register 2 is 10 and - // USER Register 3 is 11. - // - for(ui32Index = 0; ui32Index < 4; ui32Index++) - { - // - // Tell the flash controller to commit a USER Register. - // - HWREG(FLASH_FMA) = (0x80000000 + ui32Index); - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the flash interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! This function sets the handler to be called when the flash interrupt -//! occurs. The flash controller can generate an interrupt when an invalid -//! flash access occurs, such as trying to program or erase a read-only block, -//! or trying to read from an execute-only block. It can also generate an -//! interrupt when a program or erase operation has completed. The interrupt -//! is automatically enabled when the handler is registered. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_FLASH_TM4C123, pfnHandler); - - // - // Enable the flash interrupt. - // - IntEnable(INT_FLASH_TM4C123); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash interrupt. -//! -//! This function clears the handler to be called when the flash interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_FLASH_TM4C123); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_FLASH_TM4C123); -} - -//***************************************************************************** -// -//! Enables individual flash controller interrupt sources. -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! The ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted -//! on a block of flash that is marked as read-only or execute-only. -//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. -//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of -//! the EEPROM interrupt can be determined by reading the EEDONE register. -//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during -//! the flash operation and the operation was terminated. -//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that -//! contains a 0 to a 1. -//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. -//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. -//! -//! This function enables the indicated flash controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntEnable(uint32_t ui32IntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(FLASH_FCIM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual flash controller interrupt sources. -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! The ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted -//! on a block of flash that is marked as read-only or execute-only. -//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. -//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of -//! the EEPROM interrupt can be determined by reading the EEDONE register. -//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during -//! the flash operation and the operation was terminated. -//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that -//! contains a 0 to a 1. -//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. -//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. -//! -//! This function disables the indicated flash controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntDisable(uint32_t ui32IntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(FLASH_FCIM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the flash controller. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b FLASH_INT_ACCESS, \b FLASH_INT_PROGRAM, \b FLASH_INT_EEPROM, -//! FLASH_INT_VOLTAGE_ERR, FLASH_INT_DATA_ERR, FLASH_INT_ERASE_ERR, and -//! FLASH_INT_PROGRAM_ERR. -// -//***************************************************************************** -uint32_t -FlashIntStatus(bool bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(FLASH_FCMISC)); - } - else - { - return(HWREG(FLASH_FCRIS)); - } -} - -//***************************************************************************** -// -//! Clears flash controller interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. -//! -//! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. The -//! ui32IntFlags parameter can be the logical OR of any of the following -//! values: -//! -//! - \b FLASH_INT_ACCESS occurs when a program or erase action was attempted -//! on a block of flash that is marked as read-only or execute-only. -//! - \b FLASH_INT_PROGRAM occurs when a programming or erase cycle completes. -//! - \b FLASH_INT_EEPROM occurs when an EEPROM interrupt occurs. The source of -//! the EEPROM interrupt can be determined by reading the EEDONE register. -//! - \b FLASH_INT_VOLTAGE_ERR occurs when the voltage was out of spec during -//! the flash operation and the operation was terminated. -//! - \b FLASH_INT_DATA_ERR occurs when an operation attempts to program a bit that -//! contains a 0 to a 1. -//! - \b FLASH_INT_ERASE_ERR occurs when an erase operation fails. -//! - \b FLASH_INT_PROGRAM_ERR occurs when a program operation fails. -//! -//! This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntClear(uint32_t ui32IntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_FCMISC) = ui32IntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/flash.h b/bsp/tm4c129x-dk/libraries/driverlib/flash.h deleted file mode 100644 index 0d20ab1c48..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/flash.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_FLASH_H__ -#define __DRIVERLIB_FLASH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and -// returned from FlashIntStatus(). -// -//***************************************************************************** -#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask -#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask -#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask -#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask -#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask -#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern int32_t FlashErase(uint32_t ui32Address); -extern int32_t FlashProgram(uint32_t *pui32Data, uint32_t ui32Address, - uint32_t ui32Count); -extern tFlashProtection FlashProtectGet(uint32_t ui32Address); -extern int32_t FlashProtectSet(uint32_t ui32Address, - tFlashProtection eProtect); -extern int32_t FlashProtectSave(void); -extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1); -extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1); -extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0, - uint32_t *pui32User1, - uint32_t *pui32User2, - uint32_t *pui32User3); -extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0, - uint32_t ui32User1, - uint32_t ui32User2, - uint32_t ui32User3); -extern int32_t FlashUserSave(void); -extern int32_t FlashAllUserRegisterSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(uint32_t ui32IntFlags); -extern void FlashIntDisable(uint32_t ui32IntFlags); -extern uint32_t FlashIntStatus(bool bMasked); -extern void FlashIntClear(uint32_t ui32IntFlags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_FLASH_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/fpu.c b/bsp/tm4c129x-dk/libraries/driverlib/fpu.c deleted file mode 100644 index 8e0d793da6..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/fpu.c +++ /dev/null @@ -1,300 +0,0 @@ -//***************************************************************************** -// -// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M -// processor. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup fpu_api -//! @{ -// -//***************************************************************************** - -#include -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/fpu.h" - -//***************************************************************************** -// -//! Enables the floating-point unit. -//! -//! This function enables the floating-point unit, allowing the floating-point -//! instructions to be executed. This function must be called prior to -//! performing any hardware floating-point operations; failure to do so results -//! in a NOCP usage fault. -//! -//! \return None. -// -//***************************************************************************** -void -FPUEnable(void) -{ - // - // Enable the coprocessors used by the floating-point unit. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); -} - -//***************************************************************************** -// -//! Disables the floating-point unit. -//! -//! This function disables the floating-point unit, preventing floating-point -//! instructions from executing (generating a NOCP usage fault instead). -//! -//! \return None. -// -//***************************************************************************** -void -FPUDisable(void) -{ - // - // Disable the coprocessors used by the floating-point unit. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS); -} - -//***************************************************************************** -// -//! Enables the stacking of floating-point registers. -//! -//! This function enables the stacking of floating-point registers s0-s15 when -//! an interrupt is handled. When enabled, space is reserved on the stack for -//! the floating-point context and the floating-point state is saved into this -//! stack space. Upon return from the interrupt, the floating-point context is -//! restored. -//! -//! If the floating-point registers are not stacked, floating-point -//! instructions cannot be safely executed in an interrupt handler because the -//! values of s0-s15 are not likely to be preserved for the interrupted code. -//! On the other hand, stacking the floating-point registers increases the -//! stacking operation from 8 words to 26 words, also increasing the interrupt -//! response latency. -//! -//! \return None. -// -//***************************************************************************** -void -FPUStackingEnable(void) -{ - // - // Enable automatic state preservation for the floating-point unit, and - // disable lazy state preservation (meaning that the floating-point state - // is always stacked when floating-point instructions are used). - // - HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN; -} - -//***************************************************************************** -// -//! Enables the lazy stacking of floating-point registers. -//! -//! This function enables the lazy stacking of floating-point registers s0-s15 -//! when an interrupt is handled. When lazy stacking is enabled, space is -//! reserved on the stack for the floating-point context, but the -//! floating-point state is not saved. If a floating-point instruction is -//! executed from within the interrupt context, the floating-point context is -//! first saved into the space reserved on the stack. On completion of the -//! interrupt handler, the floating-point context is only restored if it was -//! saved (as the result of executing a floating-point instruction). -//! -//! This method provides a compromise between fast interrupt response (because -//! the floating-point state is not saved on interrupt entry) and the ability -//! to use floating-point in interrupt handlers (because the floating-point -//! state is saved if floating-point instructions are used). -//! -//! \return None. -// -//***************************************************************************** -void -FPULazyStackingEnable(void) -{ - // - // Enable automatic and lazy state preservation for the floating-point - // unit. - // - HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN; -} - -//***************************************************************************** -// -//! Disables the stacking of floating-point registers. -//! -//! This function disables the stacking of floating-point registers s0-s15 when -//! an interrupt is handled. When floating-point context stacking is disabled, -//! floating-point operations performed in an interrupt handler destroy the -//! floating-point context of the main thread of execution. -//! -//! \return None. -// -//***************************************************************************** -void -FPUStackingDisable(void) -{ - // - // Disable automatic and lazy state preservation for the floating-point - // unit. - // - HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN); -} - -//***************************************************************************** -// -//! Selects the format of half-precision floating-point values. -//! -//! \param ui32Mode is the format for half-precision floating-point value, -//! which is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. -//! -//! This function selects between the IEEE half-precision floating-point -//! representation and the Cortex-M processor alternative representation. The -//! alternative representation has a larger range but does not have a way to -//! encode infinity (positive or negative) or NaN (quiet or signaling). The -//! default setting is the IEEE format. -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPUHalfPrecisionModeSet(uint32_t ui32Mode) -{ - // - // Set the half-precision floating-point format. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ui32Mode; -} - -//***************************************************************************** -// -//! Selects the NaN mode. -//! -//! \param ui32Mode is the mode for NaN results; which is either -//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT. -//! -//! This function selects the handling of NaN results during floating-point -//! computations. NaNs can either propagate (the default), or they can return -//! the default NaN. -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPUNaNModeSet(uint32_t ui32Mode) -{ - // - // Set the NaN mode. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ui32Mode; -} - -//***************************************************************************** -// -//! Selects the flush-to-zero mode. -//! -//! \param ui32Mode is the flush-to-zero mode; which is either -//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN. -//! -//! This function enables or disables the flush-to-zero mode of the -//! floating-point unit. When disabled (the default), the floating-point unit -//! is fully IEEE compliant. When enabled, values close to zero are treated as -//! zero, greatly improving the execution speed at the expense of some accuracy -//! (as well as IEEE compliance). -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPUFlushToZeroModeSet(uint32_t ui32Mode) -{ - // - // Set the flush-to-zero mode. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ui32Mode; -} - -//***************************************************************************** -// -//! Selects the rounding mode for floating-point results. -//! -//! \param ui32Mode is the rounding mode. -//! -//! This function selects the rounding mode for floating-point results. After -//! a floating-point operation, the result is rounded toward the specified -//! value. The default mode is \b FPU_ROUND_NEAREST. -//! -//! The following rounding modes are available (as specified by \e ui32Mode): -//! -//! - \b FPU_ROUND_NEAREST - round toward the nearest value -//! - \b FPU_ROUND_POS_INF - round toward positive infinity -//! - \b FPU_ROUND_NEG_INF - round toward negative infinity -//! - \b FPU_ROUND_ZERO - round toward zero -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -void -FPURoundingModeSet(uint32_t ui32Mode) -{ - // - // Set the rounding mode. - // - HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ui32Mode; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/fpu.h b/bsp/tm4c129x-dk/libraries/driverlib/fpu.h deleted file mode 100644 index c96d69a734..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/fpu.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// fpu.h - Prototypes for the floatint point manipulation routines. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_FPU_H__ -#define __DRIVERLIB_FPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter. -// -//***************************************************************************** -#define FPU_HALF_IEEE 0x00000000 -#define FPU_HALF_ALTERNATE 0x04000000 - -//***************************************************************************** -// -// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter. -// -//***************************************************************************** -#define FPU_NAN_PROPAGATE 0x00000000 -#define FPU_NAN_DEFAULT 0x02000000 - -//***************************************************************************** -// -// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode -// parameter. -// -//***************************************************************************** -#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 -#define FPU_FLUSH_TO_ZERO_EN 0x01000000 - -//***************************************************************************** -// -// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter. -// -//***************************************************************************** -#define FPU_ROUND_NEAREST 0x00000000 -#define FPU_ROUND_POS_INF 0x00400000 -#define FPU_ROUND_NEG_INF 0x00800000 -#define FPU_ROUND_ZERO 0x00c00000 - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void FPUEnable(void); -extern void FPUDisable(void); -extern void FPUStackingEnable(void); -extern void FPULazyStackingEnable(void); -extern void FPUStackingDisable(void); -extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode); -extern void FPUNaNModeSet(uint32_t ui32Mode); -extern void FPUFlushToZeroModeSet(uint32_t ui32Mode); -extern void FPURoundingModeSet(uint32_t ui32Mode); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_FPU_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/gpio.c b/bsp/tm4c129x-dk/libraries/driverlib/gpio.c deleted file mode 100644 index 5e55dd7f1c..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/gpio.c +++ /dev/null @@ -1,2622 +0,0 @@ -//***************************************************************************** -// -// gpio.c - API for GPIO ports -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup gpio_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_gpio.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/gpio.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// A mapping of GPIO port address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32GPIOIntMapBlizzard[][2] = -{ - { GPIO_PORTA_BASE, INT_GPIOA_TM4C123 }, - { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C123 }, - { GPIO_PORTB_BASE, INT_GPIOB_TM4C123 }, - { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C123 }, - { GPIO_PORTC_BASE, INT_GPIOC_TM4C123 }, - { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C123 }, - { GPIO_PORTD_BASE, INT_GPIOD_TM4C123 }, - { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C123 }, - { GPIO_PORTE_BASE, INT_GPIOE_TM4C123 }, - { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C123 }, - { GPIO_PORTF_BASE, INT_GPIOF_TM4C123 }, - { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C123 }, - { GPIO_PORTG_BASE, INT_GPIOG_TM4C123 }, - { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C123 }, - { GPIO_PORTH_BASE, INT_GPIOH_TM4C123 }, - { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C123 }, - { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C123 }, - { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C123 }, - { GPIO_PORTK_BASE, INT_GPIOK_TM4C123 }, - { GPIO_PORTL_BASE, INT_GPIOL_TM4C123 }, - { GPIO_PORTM_BASE, INT_GPIOM_TM4C123 }, - { GPIO_PORTN_BASE, INT_GPION_TM4C123 }, - { GPIO_PORTP_BASE, INT_GPIOP0_TM4C123 }, - { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C123 }, -}; -static const uint_fast32_t g_ui32GPIOIntMapBlizzardRows = - sizeof(g_ppui32GPIOIntMapBlizzard) / sizeof(g_ppui32GPIOIntMapBlizzard[0]); - -static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] = -{ - { GPIO_PORTA_BASE, INT_GPIOA_TM4C129 }, - { GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C129 }, - { GPIO_PORTB_BASE, INT_GPIOB_TM4C129 }, - { GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C129 }, - { GPIO_PORTC_BASE, INT_GPIOC_TM4C129 }, - { GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C129 }, - { GPIO_PORTD_BASE, INT_GPIOD_TM4C129 }, - { GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C129 }, - { GPIO_PORTE_BASE, INT_GPIOE_TM4C129 }, - { GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C129 }, - { GPIO_PORTF_BASE, INT_GPIOF_TM4C129 }, - { GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C129 }, - { GPIO_PORTG_BASE, INT_GPIOG_TM4C129 }, - { GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C129 }, - { GPIO_PORTH_BASE, INT_GPIOH_TM4C129 }, - { GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C129 }, - { GPIO_PORTJ_BASE, INT_GPIOJ_TM4C129 }, - { GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C129 }, - { GPIO_PORTK_BASE, INT_GPIOK_TM4C129 }, - { GPIO_PORTL_BASE, INT_GPIOL_TM4C129 }, - { GPIO_PORTM_BASE, INT_GPIOM_TM4C129 }, - { GPIO_PORTN_BASE, INT_GPION_TM4C129 }, - { GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 }, - { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 }, - { GPIO_PORTR_BASE, INT_GPIOR_TM4C129 }, - { GPIO_PORTS_BASE, INT_GPIOS_TM4C129 }, - { GPIO_PORTT_BASE, INT_GPIOT_TM4C129 }, -}; -static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows = - (sizeof(g_ppui32GPIOIntMapSnowflake) / - sizeof(g_ppui32GPIOIntMapSnowflake[0])); - -//***************************************************************************** -// -// The base addresses of all the GPIO modules. Both the APB and AHB apertures -// are provided. -// -//***************************************************************************** -static const uint32_t g_pui32GPIOBaseAddrs[] = -{ - GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE, - GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE, - GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE, - GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE, - GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE, - GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE, - GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE, - GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE, - GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE, - GPIO_PORTK_BASE, GPIO_PORTK_BASE, - GPIO_PORTL_BASE, GPIO_PORTL_BASE, - GPIO_PORTM_BASE, GPIO_PORTM_BASE, - GPIO_PORTN_BASE, GPIO_PORTN_BASE, - GPIO_PORTP_BASE, GPIO_PORTP_BASE, - GPIO_PORTQ_BASE, GPIO_PORTQ_BASE, - GPIO_PORTR_BASE, GPIO_PORTR_BASE, - GPIO_PORTS_BASE, GPIO_PORTS_BASE, - GPIO_PORTT_BASE, GPIO_PORTT_BASE, -}; - -//***************************************************************************** -// -//! \internal -//! Checks a GPIO base address. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! This function determines if a GPIO port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_GPIOBaseValid(uint32_t ui32Port) -{ - return((ui32Port == GPIO_PORTA_BASE) || - (ui32Port == GPIO_PORTA_AHB_BASE) || - (ui32Port == GPIO_PORTB_BASE) || - (ui32Port == GPIO_PORTB_AHB_BASE) || - (ui32Port == GPIO_PORTC_BASE) || - (ui32Port == GPIO_PORTC_AHB_BASE) || - (ui32Port == GPIO_PORTD_BASE) || - (ui32Port == GPIO_PORTD_AHB_BASE) || - (ui32Port == GPIO_PORTE_BASE) || - (ui32Port == GPIO_PORTE_AHB_BASE) || - (ui32Port == GPIO_PORTF_BASE) || - (ui32Port == GPIO_PORTF_AHB_BASE) || - (ui32Port == GPIO_PORTG_BASE) || - (ui32Port == GPIO_PORTG_AHB_BASE) || - (ui32Port == GPIO_PORTH_BASE) || - (ui32Port == GPIO_PORTH_AHB_BASE) || - (ui32Port == GPIO_PORTJ_BASE) || - (ui32Port == GPIO_PORTJ_AHB_BASE) || - (ui32Port == GPIO_PORTK_BASE) || - (ui32Port == GPIO_PORTL_BASE) || - (ui32Port == GPIO_PORTM_BASE) || - (ui32Port == GPIO_PORTN_BASE) || - (ui32Port == GPIO_PORTP_BASE) || - (ui32Port == GPIO_PORTQ_BASE) || - (ui32Port == GPIO_PORTR_BASE) || - (ui32Port == GPIO_PORTS_BASE) || - (ui32Port == GPIO_PORTT_BASE)); -} -#endif - -//***************************************************************************** -// -//! Gets the GPIO interrupt number. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! Given a GPIO base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns a GPIO interrupt number, or 0 if \e ui32Port is invalid. -// -//***************************************************************************** -static uint32_t -_GPIOIntNumberGet(uint32_t ui32Port) -{ - uint_fast32_t ui32Idx, ui32Rows; - const uint32_t (*ppui32GPIOIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - ppui32GPIOIntMap = g_ppui32GPIOIntMapBlizzard; - ui32Rows = g_ui32GPIOIntMapBlizzardRows; - - if(CLASS_IS_TM4C129) - { - ppui32GPIOIntMap = g_ppui32GPIOIntMapSnowflake; - ui32Rows = g_ui32GPIOIntMapSnowflakeRows; - } - - // - // Loop through the table that maps I2C base addresses to interrupt - // numbers. - // - for(ui32Idx = 0; ui32Idx < ui32Rows; ui32Idx++) - { - // - // See if this base address matches. - // - if(ppui32GPIOIntMap[ui32Idx][0] == ui32Port) - { - // - // Return the corresponding interrupt number. - // - return(ppui32GPIOIntMap[ui32Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the direction and mode of the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui32PinIO is the pin direction and/or mode. -//! -//! This function configures the specified pin(s) on the selected GPIO port -//! as either input or output under software control, or it configures the -//! pin to be under hardware control. -//! -//! The parameter \e ui32PinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_DIR_MODE_IN -//! - \b GPIO_DIR_MODE_OUT -//! - \b GPIO_DIR_MODE_HW -//! -//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a -//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is -//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW -//! specifies that the pin is placed under hardware control. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note GPIOPadConfigSet() must also be used to configure the corresponding -//! pad(s) in order for them to propagate the signal to/from the GPIO. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32PinIO) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT((ui32PinIO == GPIO_DIR_MODE_IN) || - (ui32PinIO == GPIO_DIR_MODE_OUT) || - (ui32PinIO == GPIO_DIR_MODE_HW)); - - // - // Set the pin direction and mode. - // - HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ? - (HWREG(ui32Port + GPIO_O_DIR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_DIR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ? - (HWREG(ui32Port + GPIO_O_AFSEL) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_AFSEL) & - ~(ui8Pins))); -} - -//***************************************************************************** -// -//! Gets the direction and mode of a pin. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pin is the pin number. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input or -//! output under software control, or it can be under hardware control. The -//! type of control and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -uint32_t -GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin) -{ - uint32_t ui32Dir, ui32AFSEL; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(ui8Pin < 8); - - // - // Convert from a pin number to a bit position. - // - ui8Pin = 1 << ui8Pin; - - // - // Return the pin direction and mode. - // - ui32Dir = HWREG(ui32Port + GPIO_O_DIR); - ui32AFSEL = HWREG(ui32Port + GPIO_O_AFSEL); - return(((ui32Dir & ui8Pin) ? 1 : 0) | ((ui32AFSEL & ui8Pin) ? 2 : 0)); -} - -//***************************************************************************** -// -//! Sets the interrupt type for the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui32IntType specifies the type of interrupt trigger mechanism. -//! -//! This function sets up the various interrupt trigger mechanisms for the -//! specified pin(s) on the selected GPIO port. -//! -//! One of the following flags can be used to define the \e ui32IntType -//! parameter: -//! -//! - \b GPIO_FALLING_EDGE sets detection to edge and trigger to falling -//! - \b GPIO_RISING_EDGE sets detection to edge and trigger to rising -//! - \b GPIO_BOTH_EDGES sets detection to both edges -//! - \b GPIO_LOW_LEVEL sets detection to low level -//! - \b GPIO_HIGH_LEVEL sets detection to high level -//! -//! In addition to the above flags, the following flag can be OR'd in to the -//! \e ui32IntType parameter: -//! -//! - \b GPIO_DISCRETE_INT sets discrete interrupts for each pin on a GPIO -//! port. -//! -//! The \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports, -//! consult the data sheet to ensure that the device and the GPIO port supports -//! discrete interrupts. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note In order to avoid any spurious interrupts, the user must ensure that -//! the GPIO inputs remain stable for the duration of this function. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32IntType) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(((ui32IntType & 0xF) == GPIO_FALLING_EDGE) || - ((ui32IntType & 0xF) == GPIO_RISING_EDGE) || - ((ui32IntType & 0xF) == GPIO_BOTH_EDGES) || - ((ui32IntType & 0xF) == GPIO_LOW_LEVEL) || - ((ui32IntType & 0xF) == GPIO_HIGH_LEVEL)); - ASSERT(((ui32IntType & 0x000F0000) == 0) || - (((ui32IntType & 0x000F0000) == GPIO_DISCRETE_INT) && - ((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)))); - - // - // Set the pin interrupt type. - // - HWREG(ui32Port + GPIO_O_IBE) = ((ui32IntType & 1) ? - (HWREG(ui32Port + GPIO_O_IBE) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_IBE) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_IS) = ((ui32IntType & 2) ? - (HWREG(ui32Port + GPIO_O_IS) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_IS) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_IEV) = ((ui32IntType & 4) ? - (HWREG(ui32Port + GPIO_O_IEV) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_IEV) & ~(ui8Pins))); - - // - // Set or clear the discrete interrupt feature. This is not available - // on all parts or ports but is safe to write in all cases. - // - HWREG(ui32Port + GPIO_O_SI) = ((ui32IntType & 0x10000) ? - (HWREG(ui32Port + GPIO_O_SI) | 0x01) : - (HWREG(ui32Port + GPIO_O_SI) & ~(0x01))); -} - -//***************************************************************************** -// -//! Gets the interrupt type for a pin. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pin is the pin number. -//! -//! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or -//! both-edges detected interrupt, or it can be configured as a low-level or -//! high-level detected interrupt. The type of interrupt detection mechanism -//! is returned and can include the \b GPIO_DISCRETE_INT flag. -//! -//! \return Returns one of the flags described for GPIOIntTypeSet(). -// -//***************************************************************************** -uint32_t -GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin) -{ - uint32_t ui32IBE, ui32IS, ui32IEV, ui32SI; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(ui8Pin < 8); - - // - // Convert from a pin number to a bit position. - // - ui8Pin = 1 << ui8Pin; - - // - // Return the pin interrupt type. - // - ui32IBE = HWREG(ui32Port + GPIO_O_IBE); - ui32IS = HWREG(ui32Port + GPIO_O_IS); - ui32IEV = HWREG(ui32Port + GPIO_O_IEV); - ui32SI = HWREG(ui32Port + GPIO_O_SI); - return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) | - ((ui32IEV & ui8Pin) ? 4 : 0) | (ui32SI & 0x01) ? 0x10000 : 0); -} - -//***************************************************************************** -// -//! Sets the pad configuration for the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui32Strength specifies the output drive strength. -//! \param ui32PinType specifies the pin type. -//! -//! This function sets the drive strength and type for the specified pin(s) -//! on the selected GPIO port. For pin(s) configured as input ports, the -//! pad is configured as requested, but the only real effect on the input -//! is the configuration of the pull-up or pull-down termination. -//! -//! The parameter \e ui32Strength can be one of the following values: -//! -//! - \b GPIO_STRENGTH_2MA -//! - \b GPIO_STRENGTH_4MA -//! - \b GPIO_STRENGTH_8MA -//! - \b GPIO_STRENGTH_8MA_SC -//! - \b GPIO_STRENGTH_6MA -//! - \b GPIO_STRENGTH_10MA -//! - \b GPIO_STRENGTH_12MA -//! -//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive -//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with -//! slew control. -//! -//! Some Tiva devices also support output drive strengths of 6, 10, and 12 -//! mA. -//! -//! The parameter \e ui32PinType can be one of the following values: -//! -//! - \b GPIO_PIN_TYPE_STD -//! - \b GPIO_PIN_TYPE_STD_WPU -//! - \b GPIO_PIN_TYPE_STD_WPD -//! - \b GPIO_PIN_TYPE_OD -//! - \b GPIO_PIN_TYPE_ANALOG -//! - \b GPIO_PIN_TYPE_WAKE_HIGH -//! - \b GPIO_PIN_TYPE_WAKE_LOW -//! -//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* -//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD -//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an analog -//! input. -//! -//! The \b GPIO_PIN_TYPE_WAKE_* settings specify the pin to be used as a -//! hibernation wake source. The pin sense level can be high or low. These -//! settings are only available on some Tiva devices. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32Strength, uint32_t ui32PinType) -{ - uint8_t ui8Bit; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT((ui32Strength == GPIO_STRENGTH_2MA) || - (ui32Strength == GPIO_STRENGTH_4MA) || - (ui32Strength == GPIO_STRENGTH_6MA) || - (ui32Strength == GPIO_STRENGTH_8MA) || - (ui32Strength == GPIO_STRENGTH_8MA_SC) || - (ui32Strength == GPIO_STRENGTH_10MA) || - (ui32Strength == GPIO_STRENGTH_12MA)); - ASSERT((ui32PinType == GPIO_PIN_TYPE_STD) || - (ui32PinType == GPIO_PIN_TYPE_STD_WPU) || - (ui32PinType == GPIO_PIN_TYPE_STD_WPD) || - (ui32PinType == GPIO_PIN_TYPE_OD) || - (ui32PinType == GPIO_PIN_TYPE_WAKE_LOW) || - (ui32PinType == GPIO_PIN_TYPE_WAKE_HIGH) || - (ui32PinType == GPIO_PIN_TYPE_ANALOG)); - - - // - // Set the GPIO peripheral configuration register first as required. This - // register only appears in TM4E111 and later device classes, but is a - // harmless write on older devices. Walk pins 0-7 and clear or set the - // provided PC[EDMn] encoding. - // - for(ui8Bit = 0; ui8Bit < 8; ui8Bit++) - { - if(ui8Pins & (1 << ui8Bit)) - { - HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & - ~(0x3 << (2 * ui8Bit))); - HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) << - (2 * ui8Bit)); - } - } - - // - // Set the output drive strength. - // - HWREG(ui32Port + GPIO_O_DR2R) = ((ui32Strength & 1) ? - (HWREG(ui32Port + GPIO_O_DR2R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR2R) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_DR4R) = ((ui32Strength & 2) ? - (HWREG(ui32Port + GPIO_O_DR4R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR4R) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_DR8R) = ((ui32Strength & 4) ? - (HWREG(ui32Port + GPIO_O_DR8R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR8R) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_SLR) = ((ui32Strength & 8) ? - (HWREG(ui32Port + GPIO_O_SLR) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_SLR) & - ~(ui8Pins))); - - // - // Set the 12-mA drive select register. This register only appears in - // TM4E111 and later device classes, but is a harmless write on older - // devices. - // - HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ? - (HWREG(ui32Port + GPIO_O_DR12R) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_DR12R) & - ~(ui8Pins))); - - // - // Set the pin type. - // - HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ? - (HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ? - (HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ? - (HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ? - (HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins))); - - // - // Set the wake pin enable register and the wake level register. These - // registers only appear in TM4E111 and later device classes, but are - // harmless writes on older devices. - // - HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? - (HWREG(ui32Port + GPIO_O_WAKELVL) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_WAKELVL) & - ~(ui8Pins))); - HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? - (HWREG(ui32Port + GPIO_O_WAKEPEN) | - ui8Pins) : - (HWREG(ui32Port + GPIO_O_WAKEPEN) & - ~(ui8Pins))); - - // - // Set the analog mode select register. - // - HWREG(ui32Port + GPIO_O_AMSEL) = - ((ui32PinType == GPIO_PIN_TYPE_ANALOG) ? - (HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) : - (HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins))); -} - -//***************************************************************************** -// -//! Gets the pad configuration for a pin. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pin is the pin number. -//! \param pui32Strength is a pointer to storage for the output drive strength. -//! \param pui32PinType is a pointer to storage for the output drive type. -//! -//! This function gets the pad configuration for a specified pin on the -//! selected GPIO port. The values returned in \e pui32Strength and -//! \e pui32PinType correspond to the values used in GPIOPadConfigSet(). This -//! function also works for pin(s) configured as input pin(s); however, the -//! only meaningful data returned is whether the pin is terminated with a -//! pull-up or down resistor. -//! -//! \return None -// -//***************************************************************************** -void -GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, - uint32_t *pui32Strength, uint32_t *pui32PinType) -{ - uint32_t ui32PinType, ui32Strength; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT(ui8Pin < 8); - - // - // Convert from a pin number to a bit position. - // - ui8Pin = (1 << ui8Pin); - - // - // Get the drive strength for this pin. - // - ui32Strength = ((HWREG(ui32Port + GPIO_O_DR2R) & ui8Pin) ? 1 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR4R) & ui8Pin) ? 2 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR8R) & ui8Pin) ? 4 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_SLR) & ui8Pin) ? 8 : 0); - ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0); - ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >> - (2 * ui8Pin)) & 0x3) << 5); - *pui32Strength = ui32Strength; - - // - // Get the pin type. - // - ui32PinType = ((HWREG(ui32Port + GPIO_O_ODR) & ui8Pin) ? 1 : 0); - ui32PinType |= ((HWREG(ui32Port + GPIO_O_PUR) & ui8Pin) ? 2 : 0); - ui32PinType |= ((HWREG(ui32Port + GPIO_O_PDR) & ui8Pin) ? 4 : 0); - ui32PinType |= ((HWREG(ui32Port + GPIO_O_DEN) & ui8Pin) ? 8 : 0); - if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin) - { - ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ? - 0x200 : 0x100); - } - *pui32PinType = ui32PinType; -} - -//***************************************************************************** -// -//! Enables the specified GPIO interrupts. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to enable. -//! -//! This function enables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module. -//! -//! \note If this call is being used to enable summary interrupts on GPIO port -//! P or Q (GPIOIntTypeSet() with GPIO_DISCRETE_INT not enabled), then all -//! individual interrupts for these ports must be enabled in the GPIO module -//! using GPIOIntEnable() and all but the interrupt for pin 0 must be disabled -//! in the NVIC using the IntDisable() function. The summary interrupts for -//! the ports are routed to the INT_GPIOP0 or INT_GPIOQ0 which must be enabled -//! to handle the interrupt. If this is not done then any individual GPIO pin -//! interrupts that are left enabled also trigger the individual interrupts. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Enable the interrupts. - // - HWREG(ui32Port + GPIO_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the specified GPIO interrupts. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function disables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Disable the interrupts. - // - HWREG(ui32Port + GPIO_O_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return Returns the current interrupt status for the specified GPIO module. -//! The value returned is the logical OR of the \b GPIO_INT_* values that are -//! currently active. -// -//***************************************************************************** -uint32_t -GPIOIntStatus(uint32_t ui32Port, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Return the interrupt status. - // - if(bMasked) - { - return(HWREG(ui32Port + GPIO_O_MIS)); - } - else - { - return(HWREG(ui32Port + GPIO_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the specified interrupt sources. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to disable. -//! -//! Clears the interrupt for the specified interrupt source(s). -//! -//! The \e ui32IntFlags parameter is the logical OR of the \b GPIO_INT_* -//! values. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Clear the interrupts. - // - HWREG(ui32Port + GPIO_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling -//! function. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function also enables the corresponding GPIO interrupt -//! in the interrupt controller; individual pin interrupts and interrupt -//! sources must be enabled with GPIOIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnIntHandler); - - // - // Enable the GPIO interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! This function unregisters the interrupt handler for the specified -//! GPIO port. This function also disables the corresponding -//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts -//! and interrupt sources must be disabled with GPIOIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntUnregister(uint32_t ui32Port) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - ASSERT(ui32Int != 0); - - // - // Disable the GPIO interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for an individual pin of a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32Pin is the pin whose interrupt is to be registered. -//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling -//! function. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected from the selected -//! pin of a GPIO port. This function also enables the corresponding GPIO pin -//! interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, - void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); - ASSERT((ui32Pin > 0) && (ui32Pin < 8)); - ASSERT(pfnIntHandler != 0); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - // - // Register the interrupt handler. - // - IntRegister((ui32Int + ui32Pin), pfnIntHandler); - - // - // Enable the GPIO pin interrupt. - // - IntEnable(ui32Int + ui32Pin); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for an individual pin of a GPIO port. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui32Pin is the pin whose interrupt is to be unregistered. -//! -//! This function unregisters the interrupt handler for the specified pin of a -//! GPIO port. This function also disables the corresponding GPIO pin -//! interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); - ASSERT((ui32Pin > 0) && (ui32Pin < 8)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ui32Int = _GPIOIntNumberGet(ui32Port); - - // - // Disable the GPIO pin interrupt. - // - IntDisable(ui32Int + ui32Pin); - - // - // UnRegister the interrupt handler. - // - IntUnregister(ui32Int + ui32Pin); -} - -//***************************************************************************** -// -//! Reads the values present of the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The values at the specified pin(s) are read, as specified by \e ui8Pins. -//! Values are returned for both input and output pin(s), and the value -//! for pin(s) that are not specified by \e ui8Pins are set to 0. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return Returns a bit-packed byte providing the state of the specified -//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents -//! GPIO port pin 1, and so on. Any bit that is not specified by \e ui8Pins -//! is returned as a 0. Bits 31:8 should be ignored. -// -//***************************************************************************** -int32_t -GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Return the pin value(s). - // - return(HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2)))); -} - -//***************************************************************************** -// -//! Writes a value to the specified pin(s). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! \param ui8Val is the value to write to the pin(s). -//! -//! Writes the corresponding bit values to the output pin(s) specified by -//! \e ui8Pins. Writing to a pin configured as an input pin has no effect. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Write the pins. - // - HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))) = ui8Val; -} - -//***************************************************************************** -// -//! Configures pin(s) for use as analog-to-digital converter inputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The analog-to-digital converter input pins must be properly configured for -//! the analog-to-digital peripheral to function correctly. This function -//! provides the proper configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an ADC input; it -//! only configures an ADC input pin for proper operation. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as a CAN device. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The CAN pins must be properly configured for the CAN peripherals to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a CAN pin; it only -//! configures a CAN pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the CAN -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an analog comparator input. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The analog comparator input pins must be properly configured for the analog -//! comparator to function correctly. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an analog -//! comparator input; it only configures an analog comparator pin for proper -//! operation. Note that a GPIOPinConfigure() function call is also required -//! to properly configure a pin for the analog comparator function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an analog comparator output. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The analog comparator output pins must be properly configured for the analog -//! comparator to function correctly. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an clock to be output from the device. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The system control output pin must be properly configured for the DIVSCLK to -//! function correctly. This function provides the proper configuration for -//! those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the external peripheral interface. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The external peripheral interface pins must be properly configured for the -//! external peripheral interface to function correctly. This function -//! provides a typical configuration for those pin(s); other configurations may -//! work as well depending upon the board setup (for example, using the on-chip -//! pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an external -//! peripheral interface pin; it only configures an external peripheral -//! interface pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the -//! external peripheral interface function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Ethernet peripheral as LED signals. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The Ethernet peripheral provides four signals that can be used to drive -//! an LED (for example, for link status/activity). This function provides a -//! typical configuration for the pins. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an Ethernet LED -//! pin; it only configures an Ethernet LED pin for proper operation. Note -//! that a GPIOPinConfigure() function call is also required to properly -//! configure the pin for the Ethernet LED function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Ethernet peripheral as MII signals. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The Ethernet peripheral on some parts provides a set of MII signals that -//! are used to connect to an external PHY. This function provides a typical -//! configuration for the pins. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an Ethernet MII -//! pin; it only configures an Ethernet MII pin for proper operation. Note -//! that a GPIOPinConfigure() function call is also required to properly -//! configure the pin for the Ethernet MII function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as GPIO inputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! GPIO inputs. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as GPIO outputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! GPIO outputs. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); - - // - // Make the pin(s) be outputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as GPIO open drain outputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! GPIO outputs. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); - - // - // Make the pin(s) be outputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an Hibernate RTC Clock. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The hibernate output pin must be properly configured for the RTCCLK to -//! function correctly. This function provides the proper configuration for the -//! RTC Clock to be output from the device. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin for use as SDA by the I2C peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin. -//! -//! The I2C pins must be properly configured for the I2C peripheral to function -//! correctly. This function provides the proper configuration for the SDA -//! pin. -//! -//! The pin is specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an I2C SDA pin; it -//! only configures an I2C SDA pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the I2C SDA function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for open-drain operation with a weak pull-up. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD); -} - -//***************************************************************************** -// -//! Configures pin for use as SCL by the I2C peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin. -//! -//! The I2C pins must be properly configured for the I2C peripheral to function -//! correctly. This function provides the proper configuration for the SCL -//! pin. -//! -//! The pin is specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an I2C SCL pin; it -//! only configures an I2C SCL pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the I2C SCL function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the LCD Controller. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The LCD controller pins must be properly configured for the LCD controller -//! to function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an LCD pin; it only -//! configures an LCD pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the LCD -//! controller function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation and beefed up drive. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the 1-Wire module. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The 1-Wire pin must be properly configured for the 1-Wire peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a 1-Wire pin; it -//! only configures a 1-Wire pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the 1-Wire function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the PWM peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The PWM pins must be properly configured for the PWM peripheral to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a PWM pin; it only -//! configures a PWM pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the PWM -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the QEI peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The QEI pins must be properly configured for the QEI peripheral to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, not using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a QEI pin; it only -//! configures a QEI pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the QEI -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation with a weak pull-up. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_STD_WPU); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the SSI peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The SSI pins must be properly configured for the SSI peripheral to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a SSI pin; it only -//! configures a SSI pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the SSI -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Timer peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The CCP pins must be properly configured for the timer peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a timer pin; it -//! only configures a timer pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the CCP function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the Trace peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The Trace pins must be properly configured for the Trace peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a trace pin; it -//! only configures a trace pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the Trace function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the UART peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The UART pins must be properly configured for the UART peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a UART pin; it -//! only configures a UART pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the UART function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the USB peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! USB analog pins must be properly configured for the USB peripheral to -//! function correctly. This function provides the proper configuration for -//! any USB analog pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the USB -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures pin(s) for use by the USB peripheral. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! USB digital pins must be properly configured for the USB peripheral to -//! function correctly. This function provides a typical configuration for -//! the digital USB pin(s); other configurations may work as well depending -//! upon the board setup (for example, using the on-chip pull-ups). -//! -//! This function should only be used with EPEN and PFAULT pins as all other -//! USB pins are analog in nature or are not used in devices without OTG -//! functionality. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a USB pin; it only -//! configures a USB pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the USB -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as a hibernate wake-on-high source. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! hibernate wake-high inputs. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for wake-high operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_WAKE_HIGH); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as a hibernate wake-on-low source. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! hibernate wake-low inputs. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for wake-high operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_WAKE_LOW); -} - -//***************************************************************************** -// -//! Retrieves the wake pins status. -//! -//! \param ui32Port is the base address of the GPIO port. -//! -//! This function returns the GPIO wake pin status values. The returned -//! bitfield shows low or high pin state via a value of 0 or 1. -//! -//! \note This function is not available on all devices, consult the data sheet -//! to ensure that the device you are using supports GPIO wake pins. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return Returns the wake pin status. -// -//***************************************************************************** -uint32_t -GPIOPinWakeStatus(uint32_t ui32Port) -{ - return(HWREG(ui32Port + GPIO_O_WAKESTAT)); -} - -//***************************************************************************** -// -//! Configures the alternate function of a GPIO pin. -//! -//! \param ui32PinConfig is the pin configuration value, specified as only one -//! of the \b GPIO_P??_??? values. -//! -//! This function configures the pin mux that selects the peripheral function -//! associated with a particular GPIO pin. Only one peripheral function at a -//! time can be associated with a GPIO pin, and each peripheral function should -//! only be associated with a single GPIO pin at a time (despite the fact that -//! many of them can be associated with more than one GPIO pin). To fully -//! configure a pin, a GPIOPinType*() function should also be called. -//! -//! The available mappings are supplied on a per-device basis in -//! pin_map.h. The \b PART_ defines controls which set of -//! defines are included so that they match the device that is being used. -//! For example, \b PART_TM4C129XNCZAD must be defined in order to get the -//! correct pin mappings for the TM4C129XNCZAD device. -//! -//! \note If the same signal is assigned to two different GPIO port -//! pins, the signal is assigned to the port with the lowest letter and the -//! assignment to the higher letter port is ignored. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinConfigure(uint32_t ui32PinConfig) -{ - uint32_t ui32Base, ui32Shift; - - // - // Check the argument. - // - ASSERT(((ui32PinConfig >> 16) & 0xff) < 18); - ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0); - - // - // Extract the base address index from the input value. - // - ui32Base = (ui32PinConfig >> 16) & 0xff; - - // - // Get the base address of the GPIO module, selecting either the APB or the - // AHB aperture as appropriate. - // - if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ui32Base)) - { - ui32Base = g_pui32GPIOBaseAddrs[(ui32Base << 1) + 1]; - } - else - { - ui32Base = g_pui32GPIOBaseAddrs[ui32Base << 1]; - } - - // - // Extract the shift from the input value. - // - ui32Shift = (ui32PinConfig >> 8) & 0xff; - - // - // Write the requested pin muxing value for this GPIO pin. - // - HWREG(ui32Base + GPIO_O_PCTL) = ((HWREG(ui32Base + GPIO_O_PCTL) & - ~(0xf << ui32Shift)) | - ((ui32PinConfig & 0xf) << ui32Shift)); -} - -//***************************************************************************** -// -//! Enables a GPIO pin as a trigger to start a DMA transaction. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function enables a GPIO pin to be used as a trigger to start a uDMA -//! transaction. Any GPIO pin can be configured to be an external trigger for -//! the uDMA. The GPIO pin still generates interrupts if the interrupt is -//! enabled for the selected pin. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_DMACTL) |= ui8Pins; -} - -//***************************************************************************** -// -//! Disables a GPIO pin as a trigger to start a DMA transaction. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function disables a GPIO pin from being used as a trigger to start a -//! uDMA transaction. This function can be used to disable this feature if it -//! was enabled via a call to GPIODMATriggerEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_DMACTL) &= (~ui8Pins); -} - -//***************************************************************************** -// -//! Enables a GPIO pin as a trigger to start an ADC capture. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function enables a GPIO pin to be used as a trigger to start an ADC -//! sequence. Any GPIO pin can be configured to be an external trigger for an -//! ADC sequence. The GPIO pin still generates interrupts if the interrupt is -//! enabled for the selected pin. To enable the use of a GPIO pin to trigger -//! the ADC module, the ADCSequenceConfigure() function must be called with the -//! \b ADC_TRIGGER_EXTERNAL parameter. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_ADCCTL) |= ui8Pins; -} - -//***************************************************************************** -// -//! Disable a GPIO pin as a trigger to start an ADC capture. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! This function disables a GPIO pin to be used as a trigger to start an ADC -//! sequence. This function can be used to disable this feature if it was -//! enabled via a call to GPIOADCTriggerEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Set the pin as a DMA trigger. - // - HWREG(ui32Port + GPIO_O_ADCCTL) &= (~ui8Pins); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/gpio.h b/bsp/tm4c129x-dk/libraries/driverlib/gpio.h deleted file mode 100644 index 47b0dd71b4..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/gpio.h +++ /dev/null @@ -1,204 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_GPIO_H__ -#define __DRIVERLIB_GPIO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ui8Pins argument to -// several of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, -// and returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level -#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, -// and returned by GPIOPadConfigGet in the *pui32Strength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength -#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control -#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength -#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, -// and returned by GPIOPadConfigGet in the *pui32PadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator -#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high -#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low - -//***************************************************************************** -// -// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions -// in the ui32IntFlags parameter. -// -//***************************************************************************** -#define GPIO_INT_PIN_0 0x00000001 -#define GPIO_INT_PIN_1 0x00000002 -#define GPIO_INT_PIN_2 0x00000004 -#define GPIO_INT_PIN_3 0x00000008 -#define GPIO_INT_PIN_4 0x00000010 -#define GPIO_INT_PIN_5 0x00000020 -#define GPIO_INT_PIN_6 0x00000040 -#define GPIO_INT_PIN_7 0x00000080 -#define GPIO_INT_DMA 0x00000100 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32PinIO); -extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); -extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32IntType); -extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); -extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, - uint32_t ui32Strength, uint32_t ui32PadType); -extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, - uint32_t *pui32Strength, uint32_t *pui32PadType); -extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); -extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); -extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); -extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); -extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); -extern void GPIOIntUnregister(uint32_t ui32Port); -extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, - void (*pfnIntHandler)(void)); -extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin); -extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); -extern void GPIOPinConfigure(uint32_t ui32PinConfig); -extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); -extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); -extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); -extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_GPIO_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.c b/bsp/tm4c129x-dk/libraries/driverlib/hibernate.c deleted file mode 100644 index a371578387..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.c +++ /dev/null @@ -1,2553 +0,0 @@ -//***************************************************************************** -// -// hibernate.c - Driver for the Hibernation module -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup hibernate_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_hibernate.h" -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/hibernate.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -// The delay in microseconds for writing to the Hibernation module registers. -// -//***************************************************************************** -#define DELAY_USECS 95 - -//***************************************************************************** -// -// The number of processor cycles to execute one pass of the delay loop. -// -//***************************************************************************** -#define LOOP_CYCLES 3 - -//***************************************************************************** -// -// A macro used to determine whether the target part supports Wake from IO -// pins. -// -//***************************************************************************** -#define HIBERNATE_WAKE_IO CLASS_IS_TM4C129 - -//***************************************************************************** -// -// A macro used to determine whether the target part supports Wake from IO -// pins. -// -//***************************************************************************** -#define HIBERNATE_CLOCK_OUTPUT CLASS_IS_TM4C129 - -//***************************************************************************** -// -//! \internal -//! -//! Polls until the write complete (WRC) bit in the hibernate control register -//! is set. -//! -//! \param None. -//! -//! The Hibernation module provides an indication when any write is completed. -//! This mechanism is used to pace writes to the module. This function merely -//! polls this bit and returns as soon as it is set. At this point, it is safe -//! to perform another write to the module. -//! -//! \return None. -// -//***************************************************************************** -static void -_HibernateWriteComplete(void) -{ - // - // Spin until the write complete bit is set. - // - while(!(HWREG(HIB_CTL) & HIB_CTL_WRC)) - { - } -} - -//***************************************************************************** -// -//! Enables the Hibernation module for operation. -//! -//! \param ui32HibClk is the rate of the clock supplied to the Hibernation -//! module. -//! -//! This function enables the Hibernation module for operation. This function -//! should be called before any of the Hibernation module features are used. -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! \return None. -// -//***************************************************************************** -void -HibernateEnableExpClk(uint32_t ui32HibClk) -{ - // - // Turn on the clock enable bit. - // - HWREG(HIB_CTL) |= HIB_CTL_CLK32EN; - - // - // Wait for write complete following register load (above). - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables the Hibernation module for operation. -//! -//! This function disables the Hibernation module. After this function is -//! called, none of the Hibernation module features are available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateDisable(void) -{ - // - // Turn off the clock enable bit. - // - HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Configures the clock input for the Hibernation module. -//! -//! \param ui32Config is one of the possible configuration options for the -//! clock input listed below. -//! -//! This function is used to configure the clock input for the Hibernation -//! module. The \e ui32Config parameter can be one of the following values: -//! -//! - \b HIBERNATE_OSC_DISABLE specifies that the internal oscillator -//! is powered off. This option is used when an externally supplied oscillator -//! is connected to the XOSC0 pin or to save power when the LFIOSC is used in -//! devices that have an LFIOSC in the Hibernation module. -//! - \b HIBERNATE_OSC_HIGHDRIVE specifies a higher drive strength when a 24-pF -//! filter capacitor is used with a crystal. -//! - \b HIBERNATE_OSC_LOWDRIVE specifies a lower drive strength when a 12-pF -//! filter capacitor is used with a crystal. -//! -//! On some devices, there is an option to use an internal low frequency -//! oscillator (LFIOSC) as the clock source for the Hibernation module. -//! Because of the low accuracy of this oscillator, this option should not be -//! used when the system requires a real time counter. Adding the -//! \b HIBERNATE_OSC_LFIOSC value enables the LFIOSC as the clock source to -//! the Hibernation module. -//! -//! - \b HIBERNATE_OSC_LFIOSC enables the Hibernation module's internal low -//! frequency oscillator as the clock to the Hibernation module. -//! -//! This \e ui32Config also configures how the clock output from the -//! hibernation is used to clock other peripherals in the system. The ALT -//! clock settings allow clocking a subset of the peripherals. See the -//! hibernate section in the datasheet to determine which peripherals can be -//! clocked by the ALT clock outputs from the Hibernation module. -//! The \e ui32Config parameter can have any combination of the following -//! values: -//! -//! - \b HIBERNATE_OUT_SYSCLK enables the hibernate clock output to the system -//! clock. -//! -//! The \b HIBERNATE_OSC_DISABLE option is used to disable and power down the -//! internal oscillator if an external clock source or no clock source is used -//! instead of a 32.768-kHz crystal. In the case where an external crystal is -//! used, either the \b HIBERNATE_OSC_HIGHDRIVE or \b HIBERNATE_OSC_LOWDRIVE is -//! used. These settings optimizes the oscillator drive strength to match the -//! size of the filter capacitor that is used with the external crystal -//! circuit. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateClockConfig(uint32_t ui32Config) -{ - uint32_t ui32HIBCtl; - - ASSERT((ui32Config & ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | - HIBERNATE_OSC_DISABLE)) == 0); - - ui32HIBCtl = HWREG(HIB_CTL); - - // - // Clear the current configuration bits. - // - ui32HIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE | - HIBERNATE_OSC_LFIOSC | HIBERNATE_OSC_DISABLE); - - // - // Set the new configuration bits. - // - ui32HIBCtl |= ui32Config & (HIBERNATE_OSC_HIGHDRIVE | - HIBERNATE_OSC_LOWDRIVE | - HIBERNATE_OSC_LFIOSC | - HIBERNATE_OSC_DISABLE); - - // - // Must be sure that the 32KHz clock is enabled if the hibernate is about - // to switch to it. - // - if(ui32Config & HIBERNATE_OSC_LFIOSC) - { - ui32HIBCtl |= HIB_CTL_CLK32EN; - } - - // - // Set the hibernation clocking configuration. - // - HWREG(HIB_CTL) = ui32HIBCtl; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - - // - // Write the output clock configuration for devices that support - // controlling the output clocks from the hibernate module. - // - if(HIBERNATE_CLOCK_OUTPUT) - { - HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK | - HIBERNATE_OUT_ALT1CLK); - } -} - -//***************************************************************************** -// -//! Enables the RTC feature of the Hibernation module. -//! -//! This function enables the RTC in the Hibernation module. The RTC can be -//! used to wake the processor from hibernation at a certain time, or to -//! generate interrupts at certain times. This function must be called before -//! using any of the RTC features of the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCEnable(void) -{ - // - // Turn on the RTC enable bit. - // - HWREG(HIB_CTL) |= HIB_CTL_RTCEN; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables the RTC feature of the Hibernation module. -//! -//! This function disables the RTC in the Hibernation module. After calling -//! this function, the RTC features of the Hibernation module are not -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCDisable(void) -{ - // - // Turn off the RTC enable bit. - // - HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Forces the Hibernation module to initiate a check of the battery voltage. -//! -//! This function forces the Hibernation module to initiate a check of the -//! battery voltage immediately rather than waiting for the next check interval -//! to pass. After calling this function, the application should call the -//! HibernateBatCheckDone() function and wait for the function to return a zero -//! value before calling the HibernateIntStatus() to check if the return code -//! has the \b HIBERNATE_INT_LOW_BAT set. If \b HIBERNATE_INT_LOW_BAT is set, -//! the battery level is low. The application can also enable the -//! \b HIBERNATE_INT_LOW_BAT interrupt and wait for an interrupt to indicate -//! that the battery level is low. -//! -//! \note A hibernation request is held off if a battery check is in progress. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateBatCheckStart(void) -{ - // - // Initiated a forced battery check. - // - HWREG(HIB_CTL) |= HIB_CTL_BATCHK; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Determines whether or not a forced battery check has completed. -//! -//! This function determines whether the forced battery check initiated by a -//! call to the HibernateBatCheckStart() function has completed. This function -//! returns a non-zero value until the battery level check has completed. Once -//! this function returns a value of zero, the Hibernation module has completed -//! the battery check and the HibernateIntStatus() function can be used to -//! check if the battery was low by checking if the value returned has the -//! \b HIBERNATE_INT_LOW_BAT set. -//! -//! \return The value is zero when the battery level check has completed or -//! non-zero if the check is still in process. -// -//***************************************************************************** -uint32_t -HibernateBatCheckDone(void) -{ - // - // Read the current state of the battery check. - // - return(HWREG(HIB_CTL) & HIB_CTL_BATCHK); -} - -//***************************************************************************** -// -//! Configures the wake conditions for the Hibernation module. -//! -//! \param ui32WakeFlags specifies which conditions should be used for waking. -//! -//! This function enables the conditions under which the Hibernation module -//! wakes. The \e ui32WakeFlags parameter is the logical OR of any combination -//! of the following: -//! -//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. -//! - \b HIBERNATE_WAKE_RTC - wake when the RTC match occurs. -//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernate due to a low-battery -//! level being detected. -//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted. -//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted. -//! -//! If the \b HIBERNATE_WAKE_GPIO flag is set, then one of the GPIO -//! configuration functions GPIOPinTypeWakeHigh() or GPIOPinTypeWakeLow() must -//! be called to properly configure and enable a GPIO as a wake source for -//! hibernation. -//! -//! \note The \b HIBERNATE_WAKE_GPIO and \b HIBERNATE_WAKE_RESET parameters are -//! only available on some Tiva devices. -//! -//! \note On some Tiva devices a tamper event acts as a wake source for the -//! Hibernation module. Refer the function \b HibernateTamperEventsConfig() to -//! wake from hibernation on a tamper event. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateWakeSet(uint32_t ui32WakeFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32WakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_GPIO | HIBERNATE_WAKE_RESET | - HIBERNATE_WAKE_LOW_BAT))); - - // - // Set the specified wake flags in the control register. - // - HWREG(HIB_CTL) = (ui32WakeFlags | (HWREG(HIB_CTL) & - ~(HIBERNATE_WAKE_PIN | - HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_LOW_BAT))); - - // - // Wait for write completion - // - _HibernateWriteComplete(); - - // - // Write the hibernate IO register if requested. - // - if(HIBERNATE_WAKE_IO) - { - // - // If the reset or GPIOs are begin used as a wake source then the - // the VDD3ON needs to be set to allow the pads to remained - // powered. - // - if((ui32WakeFlags & (HIBERNATE_WAKE_RESET | HIBERNATE_WAKE_GPIO)) && - ((HWREG(HIB_CTL) & HIB_CTL_VDD3ON) == 0)) - { - // - // Make sure that VDD3ON mode is enabled so that the pads can - // retain their state. - // - HWREG(HIB_CTL) |= HIB_CTL_VDD3ON; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - } - - // - // Set the requested flags. - // - HWREG(HIB_IO) = (ui32WakeFlags >> 16) | HIB_IO_WUUNLK; - - // - // Spin until the write complete bit is set. - // - while((HWREG(HIB_IO) & HIB_IO_IOWRC) == 0) - { - } - - // - // Clear the write unlock bit. - // - HWREG(HIB_IO) &= ~HIB_IO_WUUNLK; - } -} - -//***************************************************************************** -// -//! Gets the currently configured wake conditions for the Hibernation module. -//! -//! This function returns the flags representing the wake configuration for the -//! Hibernation module. The return value is a combination of the following -//! flags: -//! -//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted -//! - \b HIBERNATE_WAKE_RTC - wake when the RTC matches occurs -//! - \b HIBERNATE_WAKE_LOW_BAT - wake from hibernation due to a low-battery -//! level being detected -//! - \b HIBERNATE_WAKE_GPIO - wake when a GPIO pin is asserted -//! - \b HIBERNATE_WAKE_RESET - wake when a reset pin is asserted -//! -//! \note The \b HIBERNATE_WAKE_LOW_BAT, \b HIBERNATE_WAKE_GPIO, and -//! \b HIBERNATE_WAKE_RESET parameters are only available on some Tiva devices. -//! -//! \note On some Tiva devices a tamper event acts as a wake source for the -//! Hibernation module. Refer the function \b HibernateTamperEventsConfig() to -//! wake from hibernation on a tamper event. -//! -//! \return Returns flags indicating the configured wake conditions. -// -//***************************************************************************** -uint32_t -HibernateWakeGet(void) -{ - uint32_t ui32Ctrl; - - // - // Read the wake bits from the control register and return those bits to - // the caller. - // - if(HIBERNATE_WAKE_IO) - { - ui32Ctrl = HWREG(HIB_CTL); - return((ui32Ctrl & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_LOW_BAT)) | - ((HWREG(HIB_IO) << 16) & (HIBERNATE_WAKE_RESET | - HIBERNATE_WAKE_GPIO))); - } - else - { - return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC | - HIBERNATE_WAKE_LOW_BAT)); - } -} - -//***************************************************************************** -// -//! Configures the low-battery detection. -//! -//! \param ui32LowBatFlags specifies behavior of low-battery detection. -//! -//! This function enables the low-battery detection and whether hibernation is -//! allowed if a low battery is detected. If low-battery detection is enabled, -//! then a low-battery condition is indicated in the raw interrupt status -//! register, which can be enabled to trigger an interrupt. Optionally, -//! hibernation can be aborted if a low battery condition is detected. -//! -//! The \e ui32LowBatFlags parameter is one of the following values: -//! -//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low-battery condition -//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low-battery condition and abort -//! hibernation if low-battery is detected -//! -//! The other setting in the \e ui32LowBatFlags allows the caller to set one of -//! the following voltage level trigger values : -//! -//! - \b HIBERNATE_LOW_BAT_1_9V - voltage low level is 1.9 V -//! - \b HIBERNATE_LOW_BAT_2_1V - voltage low level is 2.1 V -//! - \b HIBERNATE_LOW_BAT_2_3V - voltage low level is 2.3 V -//! - \b HIBERNATE_LOW_BAT_2_5V - voltage low level is 2.5 V -//! -//! \b Example: Abort hibernate if the voltage level is below 2.1 V. -//! -//! \verbatim -//! HibernateLowBatSet(HIBERNATE_LOW_BAT_ABORT | HIBERNATE_LOW_BAT_2_1V); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -HibernateLowBatSet(uint32_t ui32LowBatFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32LowBatFlags & - ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT))); - - // - // Set the low-battery detect and abort bits in the control register, - // according to the parameter. - // - HWREG(HIB_CTL) = (ui32LowBatFlags | - (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M | - HIBERNATE_LOW_BAT_ABORT))); - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the currently configured low-battery detection behavior. -//! -//! This function returns a value representing the currently configured low -//! battery detection behavior. -//! -//! The return value is a combination of the values described in the -//! HibernateLowBatSet() function. -//! -//! \return Returns a value indicating the configured low-battery detection. -// -//***************************************************************************** -uint32_t -HibernateLowBatGet(void) -{ - // - // Read the supported low bat bits from the control register and return - // those bits to the caller. - // - return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)); -} - -//***************************************************************************** -// -//! Sets the value of the real time clock (RTC) counter. -//! -//! \param ui32RTCValue is the new value for the RTC. -//! -//! This function sets the value of the RTC. The RTC counter contains the -//! count in seconds when a 32.768kHz clock source is in use. The RTC must be -//! enabled by calling HibernateRTCEnable() before calling this function. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCSet(uint32_t ui32RTCValue) -{ - // - // Load register requires unlock. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Write the new RTC value to the RTC load register. - // - HWREG(HIB_RTCLD) = ui32RTCValue; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - - // - // Unlock. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the value of the real time clock (RTC) counter. -//! -//! This function gets the value of the RTC and returns it to the caller. -//! -//! \return Returns the value of the RTC counter in seconds. -// -//***************************************************************************** -uint32_t -HibernateRTCGet(void) -{ - // - // Return the value of the RTC counter register to the caller. - // - return(HWREG(HIB_RTCC)); -} - -//***************************************************************************** -// -//! Sets the value of the RTC match register. -//! -//! \param ui32Match is the index of the match register. -//! \param ui32Value is the value for the match register. -//! -//! This function sets a match register for the RTC. The Hibernation -//! module can be configured to wake from hibernation, and/or generate an -//! interrupt when the value of the RTC counter is the same as the match -//! register. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value) -{ - ASSERT(ui32Match == 0); - - // - // Write the new match value to the match register. - // - HWREG(HIB_RTCM0) = ui32Value; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the value of the requested RTC match register. -//! -//! \param ui32Match is the index of the match register. -//! -//! This function gets the value of the match register for the RTC. The only -//! value that can be used with the \e ui32Match parameter is zero, other -//! values are reserved for future use. -//! -//! \return Returns the value of the requested match register. -// -//***************************************************************************** -uint32_t -HibernateRTCMatchGet(uint32_t ui32Match) -{ - ASSERT(ui32Match == 0); - - // - // Return the value of the match register to the caller. - // - return(HWREG(HIB_RTCM0)); -} - -//***************************************************************************** -// -//! Sets the value of the RTC sub second match register. -//! -//! \param ui32Match is the index of the match register. -//! \param ui32Value is the value for the sub second match register. -//! -//! This function sets the sub second match register for the RTC in 1/32768 -//! of a second increments. The Hibernation module can be configured to wake -//! from hibernation, and/or generate an interrupt when the value of the RTC -//! counter is the same as the match combined with the sub second match -//! register. The only value that can be used with the \e ui32Match -//! parameter is zero, other values are reserved for future use. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value) -{ - ASSERT(ui32Match == 0); - - // - // Write the new sub second match value to the sub second match register. - // - HWREG(HIB_RTCSS) = ui32Value << HIB_RTCSS_RTCSSM_S; - - // - // Wait for write complete to be signaled on later devices. - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the value of the requested RTC sub second match register. -//! -//! \param ui32Match is the index of the match register. -//! -//! This function returns the current value of the sub second match register -//! for the RTC. The value returned is in 1/32768 second increments. The only -//! value that can be used with the \e ui32Match parameter is zero, other -//! values are reserved for future use. -//! -//! \return Returns the value of the requested sub section match register. -// -//***************************************************************************** -uint32_t -HibernateRTCSSMatchGet(uint32_t ui32Match) -{ - ASSERT(ui32Match == 0); - - // - // Read the current second RTC count. - // - return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S); -} - -//***************************************************************************** -// -//! Returns the current value of the RTC sub second count. -//! -//! This function returns the current value of the sub second count for the RTC -//! in 1/32768 of a second increments. The only value that can be used with -//! the \e ui32Match parameter is zero, other values are reserved for future -//! use. -//! -//! \return The current RTC sub second count in 1/32768 seconds. -// -//***************************************************************************** -uint32_t -HibernateRTCSSGet(void) -{ - // - // Read the current second RTC count. - // - return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M); -} - -//***************************************************************************** -// -//! Sets the value of the RTC pre-divider trim register. -//! -//! \param ui32Trim is the new value for the pre-divider trim register. -//! -//! This function sets the value of the pre-divider trim register. The input -//! time source is divided by the pre-divider to achieve a one-second clock -//! rate. Once every 64 seconds, the value of the pre-divider trim register is -//! applied to the pre-divider to allow fine-tuning of the RTC rate, in order -//! to make corrections to the rate. The software application can make -//! adjustments to the pre-divider trim register to account for variations in -//! the accuracy of the input time source. The nominal value is 0x7FFF, and it -//! can be adjusted up or down in order to fine-tune the RTC rate. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRTCTrimSet(uint32_t ui32Trim) -{ - // - // Check the arguments. - // - ASSERT(ui32Trim < 0x10000); - - // - // Write the new trim value to the trim register. - // - HWREG(HIB_RTCT) = ui32Trim; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Gets the value of the RTC pre-divider trim register. -//! -//! This function gets the value of the pre-divider trim register. This -//! function can be used to get the current value of the trim register prior -//! to making an adjustment by using the HibernateRTCTrimSet() function. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -HibernateRTCTrimGet(void) -{ - // - // Return the value of the trim register to the caller. - // - return(HWREG(HIB_RTCT)); -} - -//***************************************************************************** -// -//! Stores data in the battery-backed memory of the Hibernation module. -//! -//! \param pui32Data points to the data that the caller wants to store in the -//! memory of the Hibernation module. -//! \param ui32Count is the count of 32-bit words to store. -//! -//! Stores a set of data in the Hibernation module battery-backed memory. -//! This memory is preserved when the power to the processor is turned off -//! and can be used to store application state information that is needed when -//! the processor wakes. Up to 16 32-bit words can be stored in the -//! battery-backed memory. The data can be restored by calling the -//! HibernateDataGet() function. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Count <= 64); - ASSERT(pui32Data != 0); - - // - // Loop through all the words to be stored, storing one at a time. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) - { - // - // Write a word to the battery-backed storage area. - // - HWREG(HIB_DATA + (ui32Idx * 4)) = pui32Data[ui32Idx]; - - // - // Wait for write completion - // - _HibernateWriteComplete(); - } -} - -//***************************************************************************** -// -//! Reads a set of data from the battery-backed memory of the Hibernation -//! module. -//! -//! \param pui32Data points to a location where the data that is read from the -//! Hibernation module is stored. -//! \param ui32Count is the count of 32-bit words to read. -//! -//! This function retrieves a set of data from the Hibernation module -//! battery-backed memory that was previously stored with the -//! HibernateDataSet() function. The caller must ensure that \e pui32Data -//! points to a large enough memory block to hold all the data that is read -//! from the battery-backed memory. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Count <= 64); - ASSERT(pui32Data != 0); - - // - // Loop through all the words to be restored, reading one at a time. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) - { - // - // Read a word from the battery-backed storage area. No delay is - // required between reads. - // - pui32Data[ui32Idx] = HWREG(HIB_DATA + (ui32Idx * 4)); - } -} - -//***************************************************************************** -// -//! Requests hibernation mode. -//! -//! This function requests the Hibernation module to disable the external -//! regulator, thus removing power from the processor and all peripherals. The -//! Hibernation module remains powered from the battery or auxiliary power -//! supply. -//! -//! The Hibernation module re-enables the external regulator when one of -//! the configured wake conditions occurs (such as RTC match or external -//! \b WAKE pin). When the power is restored, the processor goes through a -//! power-on reset although the Hibernation module is not reset. The processor -//! can retrieve saved state information with the HibernateDataGet() function. -//! Prior to calling the function to request hibernation mode, the conditions -//! for waking must have already been set by using the HibernateWakeSet() -//! function. -//! -//! Note that this function may return because some time may elapse before the -//! power is actually removed, or it may not be removed at all. For this -//! reason, the processor continues to execute instructions for some time, -//! and the caller should be prepared for this function to return. There are -//! various reasons why the power may not be removed. For example, if the -//! HibernateLowBatSet() function was used to configure an abort if low -//! battery is detected, then the power is not removed if the battery -//! voltage is too low. There may be other reasons related to the external -//! circuit design, that a request for hibernation may not actually occur. -//! -//! For all these reasons, the caller must be prepared for this function to -//! return. The simplest way to handle it is to just enter an infinite loop -//! and wait for the power to be removed. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateRequest(void) -{ - // - // Set the bit in the control register to cut main power to the processor. - // - HWREG(HIB_CTL) |= HIB_CTL_HIBREQ; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Enables interrupts for the Hibernation module. -//! -//! \param ui32IntFlags is the bit mask of the interrupts to be enabled. -//! -//! This function enables the specified interrupt sources from the Hibernation -//! module. -//! -//! The \e ui32IntFlags parameter must be the logical OR of any combination of -//! the following: -//! -//! - \b HIBERNATE_INT_WR_COMPLETE - write complete interrupt -//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt -//! - \b HIBERNATE_INT_LOW_BAT - low-battery interrupt -//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt -//! - \b HIBERNATE_INT_VDDFAIL - supply failure interrupt. -//! - \b HIBERNATE_INT_RESET_WAKE - wake from reset pin interrupt -//! - \b HIBERNATE_INT_GPIO_WAKE - wake from GPIO pin or reset pin interrupt. -//! -//! \note The \b HIBERNATE_INT_RESET_WAKE, \b HIBERNATE_INT_GPIO_WAKE, and -//! \b HIBERNATE_INT_VDDFAIL settings are not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you are using to -//! determine if these interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntEnable(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | - HIBERNATE_INT_VDDFAIL | - HIBERNATE_INT_RESET_WAKE | - HIBERNATE_INT_GPIO_WAKE | - HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_WR_COMPLETE))); - - // - // Set the specified interrupt mask bits. - // - HWREG(HIB_IM) |= ui32IntFlags; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables interrupts for the Hibernation module. -//! -//! \param ui32IntFlags is the bit mask of the interrupts to be disabled. -//! -//! This function disables the specified interrupt sources from the -//! Hibernation module. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to the HibernateIntEnable() function. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntDisable(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | - HIBERNATE_INT_VDDFAIL | - HIBERNATE_INT_RESET_WAKE | - HIBERNATE_INT_GPIO_WAKE | - HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_WR_COMPLETE))); - - // - // Clear the specified interrupt mask bits. - // - HWREG(HIB_IM) &= ~ui32IntFlags; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the hibernate module interrupt number. -//! -//! This function returns the interrupt number for the hibernate module. -//! -//! \return Returns a hibernate interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_HibernateIntNumberGet(void) -{ - uint32_t ui32Int; - - // - // Find the valid interrupt number for the hibernate module. - // - if(CLASS_IS_TM4C129) - { - ui32Int = INT_HIBERNATE_TM4C129; - } - else - { - ui32Int = INT_HIBERNATE_TM4C123; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the Hibernation module interrupt. -//! -//! \param pfnHandler points to the function to be called when a hibernation -//! interrupt occurs. -//! -//! This function registers the interrupt handler in the system interrupt -//! controller. The interrupt is enabled at the global level, but individual -//! interrupt sources must still be enabled with a call to -//! HibernateIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntRegister(void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Get the interrupt number for the Hibernate module. - // - ui32Int = _HibernateIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the hibernate module interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the Hibernation module interrupt. -//! -//! This function unregisters the interrupt handler in the system interrupt -//! controller. The interrupt is disabled at the global level, and the -//! interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntUnregister(void) -{ - uint32_t ui32Int; - - // - // Get the interrupt number for the Hibernate module. - // - ui32Int = _HibernateIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Disable the hibernate interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Gets the current interrupt status of the Hibernation module. -//! -//! \param bMasked is false to retrieve the raw interrupt status, and true to -//! retrieve the masked interrupt status. -//! -//! This function returns the interrupt status of the Hibernation module. The -//! caller can use this function to determine the cause of a hibernation -//! interrupt. Either the masked or raw interrupt status can be returned. -//! -//! \note A wake from reset pin also signals a wake from GPIO pin with the -//! value returned being HIBERNATE_INT_GPIO_WAKE | HIBERNATE_INT_RESET_WAKE. -//! Hence a wake from reset pin should take priority over wake from GPIO pin. -//! -//! \return Returns the interrupt status as a bit field with the values as -//! described in the HibernateIntEnable() function. -// -//***************************************************************************** -uint32_t -HibernateIntStatus(bool bMasked) -{ - // - // Read and return the Hibernation module raw or masked interrupt status. - // - if(bMasked == true) - { - return(HWREG(HIB_MIS)); - } - else - { - return(HWREG(HIB_RIS)); - } -} - -//***************************************************************************** -// -//! Clears pending interrupts from the Hibernation module. -//! -//! \param ui32IntFlags is the bit mask of the interrupts to be cleared. -//! -//! This function clears the specified interrupt sources. This function must -//! be called within the interrupt handler or else the handler is called again -//! upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to the HibernateIntEnable() function. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -HibernateIntClear(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT | - HIBERNATE_INT_VDDFAIL | - HIBERNATE_INT_RESET_WAKE | - HIBERNATE_INT_GPIO_WAKE | - HIBERNATE_INT_RTC_MATCH_0 | - HIBERNATE_INT_WR_COMPLETE))); - - // - // Write the specified interrupt bits into the interrupt clear register. - // - HWREG(HIB_IC) |= ui32IntFlags; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Checks to see if the Hibernation module is already powered up. -//! -//! This function queries the control register to determine if the module is -//! already active. This function can be called at a power-on reset to help -//! determine if the reset is due to a wake from hibernation or a cold start. -//! If the Hibernation module is already active, then it does not need to be -//! re-enabled, and its status can be queried immediately. -//! -//! The software application should also use the HibernateIntStatus() function -//! to read the raw interrupt status to determine the cause of the wake. The -//! HibernateDataGet() function can be used to restore state. These -//! combinations of functions can be used by the software to determine if the -//! processor is waking from hibernation and the appropriate action to take as -//! a result. -//! -//! \return Returns \b true if the module is already active, and \b false if -//! not. -// -//***************************************************************************** -uint32_t -HibernateIsActive(void) -{ - // - // Read the control register, and return true if the module is enabled. - // - return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0); -} - -//***************************************************************************** -// -//! Enables GPIO retention after wake from hibernation. -//! -//! This function enables the GPIO pin state to be maintained during -//! hibernation and remain active even when waking from hibernation. The GPIO -//! module itself is reset upon entering hibernation and no longer controls the -//! output pins. To maintain the current output level after waking from -//! hibernation, the GPIO module must be reconfigured and then the -//! HibernateGPIORetentionDisable() function must be called to return control -//! of the GPIO pin to the GPIO module. -//! -//! \note The hibernation GPIO retention setting is not available on all -//! Tiva devices. Please consult the data sheet to determine if the -//! device you are using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateGPIORetentionEnable(void) -{ - // - // Enable power to the pads and enable GPIO retention during hibernate. - // - HWREG(HIB_CTL) |= HIB_CTL_VDD3ON | HIB_CTL_RETCLR; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables GPIO retention after wake from hibernation. -//! -//! This function disables the retention of the GPIO pin state during -//! hibernation and allows the GPIO pins to be controlled by the system. If -//! the HibernateGPIORetentionEnable() function is called before entering -//! hibernation, this function must be called after returning from hibernation -//! to allow the GPIO pins to be controlled by GPIO module. -//! -//! \note The hibernate GPIO retention setting is not available on all -//! Tiva devices. Please consult the data sheet to determine if the -//! device you are using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateGPIORetentionDisable(void) -{ - // - // Reset the GPIO configuration after waking from hibernate and disable - // the hibernate power to the pads. - // - HWREG(HIB_CTL) &= ~(HIB_CTL_RETCLR | HIB_CTL_VDD3ON); - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the current setting for GPIO retention. -//! -//! This function returns the current setting for GPIO retention in the -//! hibernate module. -//! -//! \note The hibernation GPIO retention setting is not available on all -//! Tiva devices. Please consult the data sheet to determine if the -//! device you are using supports this feature in the Hibernation module. -//! -//! \return Returns true if GPIO retention is enabled and false if GPIO -//! retention is disabled. -// -//***************************************************************************** -bool -HibernateGPIORetentionGet(void) -{ - // - // Read the current GPIO retention configuration. - // - if((HWREG(HIB_CTL) & (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) == - (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) - { - return(true); - } - return(false); -} - -//***************************************************************************** -// -//! Configures the Hibernation module's internal counter mode. -//! -//! \param ui32Config is the configuration to use for the Hibernation module's -//! counter. -//! -//! This function configures the Hibernate module's counter mode to operate -//! as a standard RTC counter or to operate in a calendar mode. The -//! \e ui32Config parameter is used to provide the configuration for -//! the counter and must include only one of the following values: -//! -//! - \b HIBERNATE_COUNTER_24HR specifies 24-hour calendar mode. -//! - \b HIBERNATE_COUNTER_12HR specifies 12-hour AM/PM calendar mode. -//! - \b HIBERNATE_COUNTER_RTC specifies RTC counter mode. -//! -//! The HibernateCalendar functions can only be called when either -//! \b HIBERNATE_COUNTER_24HR or \b HIBERNATE_COUNTER_12HR is specified. -//! -//! \b Example: Configure hibernate counter to 24-hour calendar mode. -//! -//! \verbatim -//! -//! // -//! // Configure the hibernate module counter to 24-hour calendar mode. -//! // -//! HibernateCounterMode(HIBERNATE_COUNTER_24HR); -//! -//! \endverbatim -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateCounterMode(uint32_t ui32Config) -{ - // - // Set the requested configuration. - // - HWREG(HIB_CALCTL) = ui32Config; - - // - // Wait for write completion - // - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -// Internal function to parse the time structure to set the calendar fields. -// -//***************************************************************************** -static void -_HibernateCalendarSet(uint32_t ui32Reg, struct tm *psTime) -{ - uint32_t ui32Time, ui32Date; - - ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); - - // - // Minutes and seconds are consistent in all modes. - // - ui32Time = (((psTime->tm_min << HIB_CALLD0_MIN_S) & HIB_CALLD0_MIN_M) | - ((psTime->tm_sec << HIB_CALLD0_SEC_S) & HIB_CALLD0_SEC_M)); - - // - // 24 Hour time is used directly for Calendar set. - // - if(HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) - { - ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S); - - // - // for Calendar match, if it is every hour, AMPM bit should be clear - // - if((ui32Reg == HIB_CALM0) && (psTime->tm_hour == 0xFF) ) - { - // - // clear AMPM bit - // - ui32Time &= ~HIB_CAL0_AMPM; - } - } - else - { - // - // In AM/PM time hours have to be capped at 12. - // If the hours are all 1s, it means the match for the hour is - // always true. We need to set 1F in the hw field. - // - if(psTime->tm_hour == 0xFF) - { - // - // Match every hour. - // - ui32Time |= HIB_CALLD0_HR_M; - } - else if(psTime->tm_hour >= 12) - { - // - // Need to set the PM bit if it is noon or later. - // - ui32Time |= (((psTime->tm_hour - 12) << HIB_CALLD0_HR_S) | - HIB_CAL0_AMPM); - } - else - { - // - // All other times are normal and AM. - // - ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S); - } - } - - // - // Create the date in the correct register format. - // - if(ui32Reg == HIB_CAL0) - { - // - // We must add 1 to the month, since the time structure lists - // the month from 0 to 11 and the HIB lists it from 1 to 12. - // - ui32Date = ((psTime->tm_mday << HIB_CAL1_DOM_S) | - ((psTime->tm_mon + 1) << HIB_CAL1_MON_S) | - (psTime->tm_wday << HIB_CAL1_DOW_S) | - ((psTime->tm_year - 100) << HIB_CAL1_YEAR_S)); - } - else - { - // - // Wday, month and year are not included in the match - // Functionality. - // - if(psTime->tm_mday == 0xFF) - { - // - // program 0 to match every day - // - ui32Date = 0 << HIB_CAL1_DOM_M; - } - else - { - ui32Date = (psTime->tm_mday << HIB_CAL1_DOM_S); - } - } - - // - // Load register requires unlock. - // - if(ui32Reg == HIB_CAL0) - { - // - // Unlock the hibernate counter load registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - } - - // - // Set the requested time and date. - // - if(ui32Reg == HIB_CAL0) - { - HWREG(HIB_CALLD0) = ui32Time; - _HibernateWriteComplete(); - HWREG(HIB_CALLD1) = ui32Date; - _HibernateWriteComplete(); - } - else - { - HWREG(HIB_CALM0) = ui32Time; - _HibernateWriteComplete(); - HWREG(HIB_CALM1) = ui32Date; - _HibernateWriteComplete(); - } - - // - // Load register requires unlock. - // - if(ui32Reg == HIB_CAL0) - { - // - // Lock the hibernate counter load registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); - } -} - -//***************************************************************************** -// -//! Sets the Hibernation module's date and time in calendar mode. -//! -//! \param psTime is the structure that holds the information for the current -//! date and time. -//! -//! This function uses the \e psTime parameter to set the current date and -//! time when the Hibernation module is in calendar mode. Regardless of -//! whether 24-hour or 12-hour mode is in use, the \e psTime structure uses a -//! 24-hour representation of the time. This function can only be called when -//! the hibernate counter is configured in calendar mode using the -//! HibernateCounterMode() function with one of the calendar modes. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateCalendarSet(struct tm *psTime) -{ - // - // Load a new date/time. - // - _HibernateCalendarSet(HIB_CAL0, psTime); -} - -//***************************************************************************** -// -//! Returns the Hibernation module's date and time in calendar mode. -//! -//! \param psTime is the structure that is filled with the current date and -//! time. -//! -//! This function returns the current date and time in the structure provided -//! by the \e psTime parameter. Regardless of the calendar mode, the -//! \e psTime parameter uses a 24-hour representation of the time. This -//! function can only be called when the Hibernation module is configured in -//! calendar mode using the HibernateCounterMode() function with one of the -//! calendar modes. -//! -//! The only case where this function fails and returns a non-zero value is -//! when the function detects that the counter is passing from the last second -//! of the day to the first second of the next day. This exception must be -//! handled in the application by waiting at least one second before calling -//! again to get the updated calendar information. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return Returns zero if the time and date were read successfully and -//! returns a non-zero value if the \e psTime structure was not updated. -// -//***************************************************************************** -int -HibernateCalendarGet(struct tm *psTime) -{ - uint32_t ui32Date, ui32Time; - - ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); - - // - // Wait for the value to be valid, this should never be more than a few - // loops and should never hang. - // - do - { - ui32Date = HWREG(HIB_CAL1); - } - while((ui32Date & HIB_CAL1_VALID) == 0); - - // - // Wait for the value to be valid, this should never be more than a few - // loops and should never hang. - // - do - { - ui32Time = HWREG(HIB_CAL0); - } - while((ui32Time & HIB_CAL0_VALID) == 0); - - // - // The date changed after reading the time so fail this call and let the - // application call again since it knows how int32_t to wait until another - // second passes. - // - if(ui32Date != HWREG(HIB_CAL1)) - { - return(-1); - } - - // - // Populate the date and time fields in the psTime structure. - // We must subtract 1 from the month, since the time structure lists - // the month from 0 to 11 and the HIB lists it from 1 to 12. - // - psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S; - psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S; - psTime->tm_mon = (((ui32Date & HIB_CAL1_MON_M) >> HIB_CAL1_MON_S) - 1); - psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S; - psTime->tm_wday = (ui32Date & HIB_CAL1_DOW_M) >> HIB_CAL1_DOW_S; - psTime->tm_year = ((ui32Date & HIB_CAL1_YEAR_M) >> HIB_CAL1_YEAR_S) + 100; - psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S; - - // - // Fix up the hour in the non-24-hour mode and the time is in PM. - // - if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) && - (ui32Time & HIB_CAL0_AMPM)) - { - psTime->tm_hour += 12; - } - - return(0); -} - -//***************************************************************************** -// -//! Sets the Hibernation module's date and time match value in calendar mode. -//! -//! \param ui32Index indicates which match register to access. -//! \param psTime is the structure that holds all of the information to set -//! the current date and time match values. -//! -//! This function uses the \e psTime parameter to set the current date and time -//! match value in the Hibernation module's calendar. Regardless of the mode, -//! the \e psTime parameter uses a 24-hour clock representation of time. -//! This function can only be called when the Hibernation module is -//! configured in calendar mode using the HibernateCounterMode() -//! function. The \e ui32Index value is reserved for future use and should -//! always be zero. -//! Calendar match can be enabled for every day, every hour, every minute or -//! every second, setting any of these fields to 0xFF causes a match for -//! that field. For example, setting the day of month field to 0xFF -//! results in a calendar match daily at the same time. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime) -{ - // - // Set the Match value. - // - _HibernateCalendarSet(HIB_CALM0, psTime); -} - -//***************************************************************************** -// -//! Returns the Hibernation module's date and time match value in calendar -//! mode. -//! -//! \param ui32Index indicates which match register to access. -//! \param psTime is the structure to fill with the current date and time -//! match value. -//! -//! This function returns the current date and time match value in the -//! structure provided by the \e psTime parameter. Regardless of the mode, the -//! \e psTime parameter uses a 24-hour clock representation of time. -//! This function can only be called when the Hibernation module is configured -//! in calendar mode using the HibernateCounterMode() function. -//! The \e ui32Index value is reserved for future use and should always be -//! zero. -//! -//! \note The hibernate calendar mode is not available on all Tiva -//! devices. Please consult the data sheet to determine if the device you are -//! using supports this feature in the Hibernation module. -//! -//! \return Returns zero if the time and date match value were read -//! successfully and returns a non-zero value if the psTime structure was not -//! updated. -// -//***************************************************************************** -void -HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime) -{ - uint32_t ui32Date, ui32Time; - - ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN); - - // - // Get the date field. - // - ui32Date = HWREG(HIB_CALM1); - - // - // Get the time field. - // - ui32Time = HWREG(HIB_CALM0); - - // - // Populate the date and time fields in the psTime structure. - // - if((ui32Time & HIB_CAL0_MIN_M) == HIB_CAL0_MIN_M) - { - // - // Match every minute - // - psTime->tm_min = 0xFF; - } - else - { - psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S; - } - - if((ui32Time & HIB_CAL0_SEC_M) == HIB_CAL0_SEC_M) - { - // - // Match every second - // - psTime->tm_sec = 0xFF; - } - else - { - psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S; - } - - if((ui32Time & HIB_CAL0_HR_M) == HIB_CAL0_HR_M) - { - // - // Match every hour - // - psTime->tm_hour = 0xFF; - } - else - { - psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S; - } - - if((ui32Date & HIB_CAL1_DOM_M) == 0) - { - // - // Match every day - // - psTime->tm_mday = 0xFF; - } - else - { - psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S; - } - - // - // Fix up the hour in the non-24-hour mode and the time is in PM. - // - if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) && - (ui32Time & HIB_CAL0_AMPM)) - { - psTime->tm_hour += 12; - } -} - -//***************************************************************************** -// -//! Configures the tamper feature event response. -//! -//! \param ui32Config specifies the configuration options for tamper events. -//! -//! This function is used to configure the event response options for the -//! tamper feature. The \e ui32Config parameter provides a combination of the -//! \b HIBERNATE_TAMPER_EVENTS_* features to set these options. The -//! application should choose from the following set of defines to determine -//! what happens to the system when a tamper event occurs: -//! -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM all of the Hibernation -//! module's battery-backed RAM is cleared due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM the upper half of the -//! Hibernation module's battery-backed RAM is cleared due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM the lower half of the -//! Hibernation module's battery-backed RAM is cleared due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_ERASE_NO_HIB_MEM the Hibernation module's -//! battery-backed RAM is not changed due to a tamper event -//! - \b HIBERNATE_TAMPER_EVENTS_HIB_WAKE a tamper event wakes the MCU from -//! hibernation -//! - \b HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE a tamper event does not wake the -//! MCU from hibernation -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEventsConfig(uint32_t ui32Config) -{ - uint32_t ui32Temp; - - // - // Mask out the on-event configuration options. - // - ui32Temp = (HWREG(HIB_TPCTL) & ~HIB_TPCTL_MEMCLR_M); - - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the on-event configuration. - // - HWREG(HIB_TPCTL) = (ui32Temp | ui32Config); - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Enables the tamper feature. -//! -//! This function is used to enable the tamper feature functionality. This -//! function should only be called after the global configuration is set with -//! a call to HibernateTamperEventsConfig() and the tamper inputs have been -//! configured with a call to HibernateTamperIOEnable(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEnable(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the tamper enable bit. - // - HWREG(HIB_TPCTL) |= HIB_TPCTL_TPEN; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables the tamper feature. -//! -//! This function is used to disable the tamper feature functionality. All -//! other configuration settings are left unmodified, allowing a call to -//! HibernateTamperEnable() to quickly enable the tamper feature with its -//! previous configuration. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperDisable(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Clear the tamper enable bit. - // - HWREG(HIB_TPCTL) &= ~HIB_TPCTL_TPEN; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Configures an input to the tamper feature. -//! -//! \param ui32Input is the tamper input to configure. -//! \param ui32Config holds the configuration options for a given input to the -//! tamper feature. -//! -//! This function is used to configure an input to the tamper feature. The -//! \e ui32Input parameter specifies the tamper signal to configure and has a -//! valid range of 0-3. The \e ui32Config parameter provides the set of tamper -//! features in the \b HIBERNATE_TAMPER_IO_* values. The values that are valid -//! in the \e ui32Config parameter are: -//! -//! - \b HIBERNATE_TAMPER_IO_MATCH_SHORT configures the trigger to match after -//! 2 hibernation clocks -//! - \b HIBERNATE_TAMPER_IO_MATCH_LONG configures the trigger to match after -//! 3071 hibernation clocks -//! - \b HIBERNATE_TAMPER_IO_WPU_ENABLED turns on an internal weak pull up -//! - \b HIBERNATE_TAMPER_IO_WPU_DISABLED turns off an internal weak pull up -//! - \b HIBERNATE_TAMPER_IO_TRIGGER_HIGH sets the tamper event to active high -//! - \b HIBERNATE_TAMPER_IO_TRIGGER_LOW sets the tamper event to active low -//! -//! \note None of the GPIO API functions are needed to configure the tamper -//! pins. The tamper pins configured by using this function overrides any -//! configuration by GPIO APIs. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config) -{ - uint32_t ui32Temp, ui32Mask; - - // - // Verify parameters. - // - ASSERT(ui32Input < 4); - - // - // Read the current tamper I/O configuration. - // - ui32Temp = HWREG(HIB_TPIO); - - // - // Mask out configuration options for the requested input. - // - ui32Mask = (ui32Temp & (~((HIB_TPIO_GFLTR0 | HIB_TPIO_PUEN0 | - HIB_TPIO_LEV0 | HIB_TPIO_EN0) << - (ui32Input << 3)))); - - // - // Set tamper I/O configuration for the requested input. - // - ui32Temp = (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3))); - - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Write to the register. - // - HWREG(HIB_TPIO) = ui32Temp; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Disables an input to the tamper feature. -//! -//! \param ui32Input is the tamper input to disable. -//! -//! This function is used to disable an input to the tamper feature. The -//! \e ui32Input parameter specifies the tamper signal to disable and has a -//! valid range of 0-3. -//! -//! \note None of the GPIO API functions are needed to configure the tamper -//! pins. The tamper pins configured by using this function overrides any -//! configuration by GPIO APIs. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperIODisable(uint32_t ui32Input) -{ - // - // Verify parameters. - // - ASSERT(ui32Input < 4); - - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Clear the I/O enable bit. - // - HWREG(HIB_TPIO) &= ((~HIB_TPIO_EN0) << (ui32Input << 3)); - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Clears the tamper feature events. -//! -//! This function is used to clear all tamper events. This function always -//! clears the tamper feature event state indicator along with all tamper log -//! entries. Logged event data should be retrieved with -//! HibernateTamperEventsGet() prior to requesting a event clear. -//! -//! HibernateTamperEventsClear() should be called prior to clearing the system -//! control NMI that resulted from the tamper event. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEventsClear(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the tamper event clear bit. - // - HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Clears the tamper feature events without Unlock and Lock. -//! -//! This function is used to clear all tamper events without unlock/locking -//! the tamper control registers, so API HibernateTamperUnLock() should be -//! called before this function, and API HibernateTamperLock() should be -//! called after to ensure that tamper control registers are locked. -//! -//! This function doesn't block until the write is complete. -//! Therefore, care must be taken to ensure the next immediate write will -//! occure only after the write complete bit is set. -//! -//! This function is used to implement a software workaround in NMI interrupt -//! handler to fix an issue when a new tamper event could be missed during -//! the clear of current tamper event. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperEventsClearNoLock(void) -{ - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Set the tamper event clear bit. - // - HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR; - -} - -//***************************************************************************** -// -//! Unlock temper registers. -//! -//! This function is used to unlock the temper control registers. This -//! function should be only used before calling API -//! HibernateTamperEventsClearNoLock(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperUnLock(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Lock temper registers. -//! -//! This function is used to lock the temper control registers. This -//! function should be used after calling API -//! HibernateTamperEventsClearNoLock(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperLock(void) -{ - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Returns the current tamper feature status. -//! -//! This function is used to return the tamper feature status. This function -//! returns one of the values from this group of options: -//! -//! - \b HIBERNATE_TAMPER_STATUS_INACTIVE indicates tamper detection is -//! disabled -//! - \b HIBERNATE_TAMPER_STATUS_ACTIVE indicates tamper detection is enabled -//! and ready -//! - \b HIBERNATE_TAMPER_STATUS_EVENT indicates tamper event was detected -//! -//! In addition, one of the values is included from this group: -//! -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE indicates the external -//! oscillator is not active -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE indicates the external -//! oscillator is active -//! -//! And one of the values is included from this group: -//! -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED indicates the external -//! oscillator signal has transitioned from valid to invalid -//! - \b HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID indicates the external -//! oscillator is providing a valid signal -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return Returns a combination of the \b HIBERNATE_TAMPER_STATUS_* values. -// -//***************************************************************************** -uint32_t -HibernateTamperStatusGet(void) -{ - uint32_t ui32Status, ui32Reg; - - // - // Retrieve the raw register value. - // - ui32Reg = HWREG(HIB_TPSTAT); - - // - // Setup the oscillator status indicators. - // - ui32Status = (ui32Reg & (HIB_TPSTAT_XOSCST | HIB_TPSTAT_XOSCFAIL)); - ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCST) ? 0 : - HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE); - ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCFAIL) ? 0 : - HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID); - - // - // Retrieve the tamper status indicators. - // - ui32Status |= ((ui32Reg & HIB_TPSTAT_STATE_M) << 3); - - // - // The HW shows "disabled" with a zero value, use bit[0] as a flag - // for this purpose. - // - if((ui32Reg & HIB_TPSTAT_STATE_M) == 0) - { - ui32Status |= HIBERNATE_TAMPER_STATUS_INACTIVE; - } - - // - // Return the API status flags. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Returns a tamper log entry. -//! -//! \param ui32Index is the index of the log entry to return. -//! \param pui32RTC is a pointer to the memory to store the logged RTC data. -//! \param pui32Event is a pointer to the memory to store the logged tamper -//! event. -//! -//! This function is used to return a tamper log entry from the hibernate -//! feature. The \e ui32Index specifies the zero-based index of the log entry -//! to query and has a valid range of 0-3. -//! -//! When this function returns, the \e pui32RTC value contains the time value -//! and \e pui32Event parameter contains the tamper I/O event that triggered -//! this log. -//! -//! The format of the returned \e pui32RTC data is dependent on the -//! configuration of the RTC within the Hibernation module. If the RTC is -//! configured for counter mode, the returned data contains counted seconds -//! from the RTC enable. If the RTC is configured for calendar mode, the data -//! returned is formatted as follows: -//! -//! \verbatim -//! +----------------------------------------------------------------------+ -//! | 31:26 | 25:22 | 21:17 | 16:12 | 11:6 | 5:0 | -//! +----------------------------------------------------------------------+ -//! | year | month | day of month | hours | minutes | seconds | -//! +----------------------------------------------------------------------+ -//! \endverbatim -//! -//! The data returned in the \e pui32Events parameter could include any of the -//! following flags: -//! -//! - \b HIBERNATE_TAMPER_EVENT_0 indicates a tamper event was triggered on I/O -//! signal 0 -//! - \b HIBERNATE_TAMPER_EVENT_1 indicates a tamper event was triggered on I/O -//! signal 1 -//! - \b HIBERNATE_TAMPER_EVENT_2 indicates a tamper event was triggered on I/O -//! signal 2 -//! - \b HIBERNATE_TAMPER_EVENT_3 indicates a tamper event was triggered on I/O -//! signal 3 -//! - \b HIBERNATE_TAMPER_EVENT_XOSC indicates an external oscillator failure -//! triggered the tamper event -//! -//! \note Tamper event logs are not consumed when read and remain available -//! until cleared. Events are only logged if unused log space is available. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return Returns \b true if the \e pui32RTC and \e pui32Events were updated -//! successfully and returns \b false if the values were not updated. -// -//***************************************************************************** -bool -HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC, - uint32_t *pui32Event) -{ - uint32_t ui32Reg; - - // - // Verify parameters. - // - ASSERT(pui32RTC); - ASSERT(pui32Event); - ASSERT(ui32Index < 4); - - // - // Retrieve the event log data for the requested index if available. - // - ui32Reg = HWREG(HIB_TPLOG0 + ((ui32Index << 3) + 4)); - if(ui32Reg == 0) - { - // - // No event data is available for this index. - // - return(false); - } - - // - // Store the event data in the provided location. - // - *pui32Event = ui32Reg; - - // - // Retrieve the calendar information. - // - *pui32RTC = HWREG(HIB_TPLOG0 + (ui32Index << 3)); - - // - // Convert the hour to 24hr mode if the Calendar is enabled - // and in 24hr mode. - // - if((HWREG(HIB_CALCTL) & (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) == - (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) - { - if(HWREG(HIB_CAL0) & HIB_CAL0_AMPM) - { - // - // Add 12 hour since it is PM - // - ui32Reg = ((*pui32RTC & 0X0001f000) + (12<<12)) & 0X0001f000; - *pui32RTC &= ~0X0001f000; - *pui32RTC |= ui32Reg; - } - } - - // - // Return success. - // - return(true); -} - -//***************************************************************************** -// -//! Attempts to recover the external oscillator. -//! -//! This function is used to attempt to recover the external oscillator after a -//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status is reported. This -//! function must not be called if the external oscillator is not used as -//! the hibernation clock input. HibernateTamperExtOscValid() should be called -//! before calling this function. -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -HibernateTamperExtOscRecover(void) -{ - // - // Unlock the tamper registers. - // - HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY; - _HibernateWriteComplete(); - - // - // Set the XOSCFAIL clear bit. - // - HWREG(HIB_TPSTAT) |= HIB_TPSTAT_XOSCFAIL; - - // - // Wait for write completion. - // - _HibernateWriteComplete(); - - // - // Lock the tamper registers. - // - HWREG(HIB_LOCK) = 0; - _HibernateWriteComplete(); -} - -//***************************************************************************** -// -//! Reports if the external oscillator signal is active and stable. -//! -//! This function should be used to verify the external oscillator is active -//! and valid before attempting to recover from a -//! \b HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED status by calling -//! HibernateTamperExtOscRecover(). -//! -//! \note The hibernate tamper feature is not available on all Tiva -//! devices. Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return Returns \b true if the external oscillator is both active and -//! stable, otherwise a \b false indicator is returned. -// -//***************************************************************************** -bool -HibernateTamperExtOscValid(void) -{ - if(HibernateTamperStatusGet() & (HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE | - HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID)) - { - return(true); - } - - return(false); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.h b/bsp/tm4c129x-dk/libraries/driverlib/hibernate.h deleted file mode 100644 index 80633b950c..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/hibernate.h +++ /dev/null @@ -1,257 +0,0 @@ -//***************************************************************************** -// -// hibernate.h - API definition for the Hibernation module. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_HIBERNATE_H__ -#define __DRIVERLIB_HIBERNATE_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macros need to configure wake events for HibernateWakeSet() -// -//***************************************************************************** -#define HIBERNATE_WAKE_PIN 0x00000010 -#define HIBERNATE_WAKE_RTC 0x00000008 -#define HIBERNATE_WAKE_LOW_BAT 0x00000200 -#define HIBERNATE_WAKE_GPIO 0x00000010 -#define HIBERNATE_WAKE_RESET 0x00100010 -#define HIBERNATE_WAKE_TAMPER 0x08000010 - -//***************************************************************************** -// -// Macros needed to configure low battery detect for HibernateLowBatSet() -// -//***************************************************************************** -#define HIBERNATE_LOW_BAT_DETECT \ - 0x00000020 -#define HIBERNATE_LOW_BAT_ABORT 0x000000A0 -#define HIBERNATE_LOW_BAT_1_9V 0x00000000 -#define HIBERNATE_LOW_BAT_2_1V 0x00002000 -#define HIBERNATE_LOW_BAT_2_3V 0x00004000 -#define HIBERNATE_LOW_BAT_2_5V 0x00006000 - -//***************************************************************************** -// -// Macros defining interrupt source bits for the interrupt functions. -// -//***************************************************************************** -#define HIBERNATE_INT_VDDFAIL 0x00000080 -#define HIBERNATE_INT_RESET_WAKE \ - 0x00000040 -#define HIBERNATE_INT_GPIO_WAKE 0x00000020 -#define HIBERNATE_INT_WR_COMPLETE \ - 0x00000010 -#define HIBERNATE_INT_PIN_WAKE 0x00000008 -#define HIBERNATE_INT_LOW_BAT 0x00000004 -#define HIBERNATE_INT_RTC_MATCH_0 \ - 0x00000001 - -//***************************************************************************** -// -// Macros defining oscillator configuration options for the -// HibernateClockConfig() function. -// -//***************************************************************************** -#define HIBERNATE_OSC_LFIOSC 0x00080000 -#define HIBERNATE_OSC_LOWDRIVE 0x00000000 -#define HIBERNATE_OSC_HIGHDRIVE 0x00020000 -#define HIBERNATE_OSC_DISABLE 0x00010000 -#define HIBERNATE_OUT_WRSTALL 0x20000000 -#define HIBERNATE_OUT_SYSCLK 0x00000001 -#define HIBERNATE_OUT_ALT1CLK 0x00000002 - -//***************************************************************************** -// -// The following defines are used with the HibernateCounterMode() API. -// -//***************************************************************************** -#define HIBERNATE_COUNTER_RTC 0x00000000 -#define HIBERNATE_COUNTER_12HR 0x00000001 -#define HIBERNATE_COUNTER_24HR 0x00000005 - -//***************************************************************************** -// -// Tamper event configuration options used with HibernateTamperEventsConfig(). -// -//***************************************************************************** -#define HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE \ - 0x00000000 -#define HIBERNATE_TAMPER_EVENTS_HIB_WAKE \ - 0x00000800 -#define HIBERNATE_TAMPER_EVENTS_NO_ERASE_HIB_MEM \ - 0x00000000 -#define HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM \ - 0x00000100 -#define HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM \ - 0x00000200 -#define HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM \ - 0x00000300 - -//***************************************************************************** -// -// Status flags returned by the HibernateTamperStatus() function. -// -//***************************************************************************** -#define HIBERNATE_TAMPER_STATUS_INACTIVE \ - 0x00000010 -#define HIBERNATE_TAMPER_STATUS_ACTIVE \ - 0x00000020 -#define HIBERNATE_TAMPER_STATUS_EVENT \ - 0x00000040 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE \ - 0x00000008 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE \ - 0x00000002 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID \ - 0x00000004 -#define HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED \ - 0x00000001 - -//***************************************************************************** -// -// Configuration options used with HibernateTamperIOEnable(). -// -//***************************************************************************** -#define HIBERNATE_TAMPER_IO_TRIGGER_LOW \ - 0x00000000 -#define HIBERNATE_TAMPER_IO_TRIGGER_HIGH \ - 0x00000002 -#define HIBERNATE_TAMPER_IO_WPU_DISABLED \ - 0x00000000 -#define HIBERNATE_TAMPER_IO_WPU_ENABLED \ - 0x00000004 -#define HIBERNATE_TAMPER_IO_MATCH_SHORT \ - 0x00000000 -#define HIBERNATE_TAMPER_IO_MATCH_LONG \ - 0x00000008 - -//***************************************************************************** -// -// Tamper log event flags. -// -//***************************************************************************** -#define HIBERNATE_TAMPER_EVENT_0 \ - 0x00000001 -#define HIBERNATE_TAMPER_EVENT_1 \ - 0x00000002 -#define HIBERNATE_TAMPER_EVENT_2 \ - 0x00000004 -#define HIBERNATE_TAMPER_EVENT_3 \ - 0x00000008 -#define HIBERNATE_TAMPER_EVENT_EXT_OSC \ - 0x00010000 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HibernateGPIORetentionEnable(void); -extern void HibernateGPIORetentionDisable(void); -extern bool HibernateGPIORetentionGet(void); -extern void HibernateEnableExpClk(uint32_t ui32HibClk); -extern void HibernateDisable(void); -extern void HibernateRTCEnable(void); -extern void HibernateRTCDisable(void); -extern void HibernateWakeSet(uint32_t ui32WakeFlags); -extern uint32_t HibernateWakeGet(void); -extern void HibernateLowBatSet(uint32_t ui32LowBatFlags); -extern uint32_t HibernateLowBatGet(void); -extern void HibernateRTCSet(uint32_t ui32RTCValue); -extern uint32_t HibernateRTCGet(void); -extern void HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value); -extern uint32_t HibernateRTCMatchGet(uint32_t ui32Match); -extern void HibernateRTCTrimSet(uint32_t ui32Trim); -extern uint32_t HibernateRTCTrimGet(void); -extern void HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count); -extern void HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count); -extern void HibernateRequest(void); -extern void HibernateIntEnable(uint32_t ui32IntFlags); -extern void HibernateIntDisable(uint32_t ui32IntFlags); -extern void HibernateIntRegister(void (*pfnHandler)(void)); -extern void HibernateIntUnregister(void); -extern uint32_t HibernateIntStatus(bool bMasked); -extern void HibernateIntClear(uint32_t ui32IntFlags); -extern uint32_t HibernateIsActive(void); -extern void HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value); -extern uint32_t HibernateRTCSSMatchGet(uint32_t ui32Match); -extern uint32_t HibernateRTCSSGet(void); -extern void HibernateClockConfig(uint32_t ui32Config); -extern void HibernateBatCheckStart(void); -extern uint32_t HibernateBatCheckDone(void); -extern void HibernateCounterMode(uint32_t ui32Config); -extern void HibernateCalendarSet(struct tm *psTime); -extern int HibernateCalendarGet(struct tm *psTime); -extern void HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime); -extern void HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime); -extern void HibernateTamperEnable(void); -extern void HibernateTamperEventsConfig(uint32_t ui32Config); -extern bool HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC, - uint32_t *pui32Event); -extern void HibernateTamperEventsClear(void); -extern void HibernateTamperEventsClearNoLock(void); -extern void HibernateTamperUnLock(void); -extern void HibernateTamperLock(void); -extern void HibernateTamperDisable(void); -extern void HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config); -extern void HibernateTamperIODisable(uint32_t ui32Input); -extern uint32_t HibernateTamperStatusGet(void); -extern void HibernateTamperExtOscRecover(void); -extern bool HibernateTamperExtOscValid(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_HIBERNATE_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/i2c.c b/bsp/tm4c129x-dk/libraries/driverlib/i2c.c deleted file mode 100644 index 37aa1d764b..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/i2c.c +++ /dev/null @@ -1,2193 +0,0 @@ -//***************************************************************************** -// -// i2c.c - Driver for Inter-IC (I2C) bus block. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup i2c_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_i2c.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/i2c.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// A mapping of I2C base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32I2CIntMap[][2] = -{ - { I2C0_BASE, INT_I2C0_TM4C123 }, - { I2C1_BASE, INT_I2C1_TM4C123 }, - { I2C2_BASE, INT_I2C2_TM4C123 }, - { I2C3_BASE, INT_I2C3_TM4C123 }, - { I2C4_BASE, INT_I2C4_TM4C123 }, - { I2C5_BASE, INT_I2C5_TM4C123 }, -}; - -static const int_fast8_t g_i8I2CIntMapRows = - sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]); - -static const uint32_t g_ppui32I2CIntMapSnowflake[][2] = -{ - { I2C0_BASE, INT_I2C0_TM4C129 }, - { I2C1_BASE, INT_I2C1_TM4C129 }, - { I2C2_BASE, INT_I2C2_TM4C129 }, - { I2C3_BASE, INT_I2C3_TM4C129 }, - { I2C4_BASE, INT_I2C4_TM4C129 }, - { I2C5_BASE, INT_I2C5_TM4C129 }, - { I2C6_BASE, INT_I2C6_TM4C129 }, - { I2C7_BASE, INT_I2C7_TM4C129 }, - { I2C8_BASE, INT_I2C8_TM4C129 }, - { I2C9_BASE, INT_I2C9_TM4C129 }, -}; -static const int_fast8_t g_i8I2CIntMapSnowflakeRows = - sizeof(g_ppui32I2CIntMapSnowflake) / sizeof(g_ppui32I2CIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks an I2C base address. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function determines if a I2C module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_I2CBaseValid(uint32_t ui32Base) -{ - return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || - (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || - (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || - (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || - (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the I2C interrupt number. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! Given a I2C base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -_I2CIntNumberGet(uint32_t ui32Base) -{ - int_fast8_t i8Idx, i8Rows; - const uint32_t (*ppui32I2CIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - ppui32I2CIntMap = g_ppui32I2CIntMap; - i8Rows = g_i8I2CIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32I2CIntMap = g_ppui32I2CIntMapSnowflake; - i8Rows = g_i8I2CIntMapSnowflakeRows; - } - - // - // Loop through the table that maps I2C base addresses to interrupt - // numbers. - // - for(i8Idx = 0; i8Idx < i8Rows; i8Idx++) - { - // - // See if this base address matches. - // - if(ppui32I2CIntMap[i8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32I2CIntMap[i8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. -//! \param bFast set up for fast data transfers. -//! -//! This function initializes operation of the I2C Master block by configuring -//! the bus speed for the master and enabling the I2C Master block. -//! -//! If the parameter \e bFast is \b true, then the master block is set up to -//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at -//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually -//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) -//! mode, a specific command is used to switch to the faster clocks after the -//! initial communication with the slave is done at either 100 Kbps or -//! 400 Kbps. -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast) -{ - uint32_t ui32SCLFreq; - uint32_t ui32TPR; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ui32Base); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ui32SCLFreq = 400000; - } - else - { - ui32SCLFreq = 100000; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biased to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / - (2 * 10 * ui32SCLFreq)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; - - // - // Check to see if this I2C peripheral is High-Speed enabled. If yes, also - // choose the fastest speed that is less than or equal to 3.4 Mbps. - // - if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) - { - ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) / - (2 * 3 * 3400000)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; - } -} - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8SlaveAddr 7-bit slave address -//! -//! This function initializes operation of the I2C Slave block by configuring -//! the slave address and enabling the I2C Slave block. -//! -//! The parameter \e ui8SlaveAddr is the value that is compared against the -//! slave address sent by an I2C master. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Must enable the device before doing anything else. - // - I2CSlaveEnable(ui32Base); - - // - // Set up the slave address. - // - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; -} - -//***************************************************************************** -// -//! Sets the I2C slave address. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8AddrNum determines which slave address is set. -//! \param ui8SlaveAddr is the 7-bit slave address -//! -//! This function writes the specified slave address. The \e ui32AddrNum field -//! dictates which slave address is configured. For example, a value of 0 -//! configures the primary address and a value of 1 configures the secondary. -//! -//! \note Not all Tiva devices support a secondary address. Please -//! consult the device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8AddrNum > 1)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Determine which slave address is being set. - // - switch(ui8AddrNum) - { - // - // Set up the primary slave address. - // - case 0: - { - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; - break; - } - - // - // Set up and enable the secondary slave address. - // - case 1: - { - HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; - break; - } - } -} - -//***************************************************************************** -// -//! Enables the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function enables operation of the I2C Master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; -} - -//***************************************************************************** -// -//! Enables the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This fucntion enables operation of the I2C Slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; - - // - // Enable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disables the I2C master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables operation of the I2C master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); -} - -//***************************************************************************** -// -//! Disables the I2C slave block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables operation of the I2C slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = 0; - - // - // Disable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2C interrupt occurs. -//! -//! This function sets the handler to be called when an I2C interrupt occurs. -//! This function enables the global interrupt in the interrupt controller; -//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and -//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via I2CMasterIntClear() and -//! I2CSlaveIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the I2C interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function clears the handler to be called when an I2C interrupt -//! occurs. This function also masks off the interrupt in the interrupt r -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function enables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 1; -} - -//***************************************************************************** -// -//! Enables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Master interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt -//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt -//! - \b I2C_MASTER_INT_START - Start Condition interrupt -//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt -//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt -//! - \b I2C_MASTER_INT_DATA - Data interrupt -//! -//! \note Not all Tiva devices support all of the listed interrupt -//! sources. Please consult the device data sheet to determine if these -//! features are supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function enables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Enables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Slave interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt -//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt -//! - \b I2C_SLAVE_INT_DATA - Data interrupt -//! -//! \note Not all Tiva devices support the all of the listed interrupts. -//! Please consult the device data sheet to determine if these features are -//! supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 0; -} - -//***************************************************************************** -// -//! Disables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Master interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Disables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Slave interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CMasterIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_MMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_MRIS)); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CSlaveIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_SMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_SRIS)); - } -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! The I2C Master interrupt source is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; - - // - // Workaround for I2C master interrupt clear errata for rev B Tiva - // devices. For later devices, this write is ignored and therefore - // harmless (other than the slight performance hit). - // - HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Master interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This function must be called in the interrupt handler to keep the interrupt -//! from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Sets the address that the I2C Master places on the bus. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8SlaveAddr 7-bit slave address -//! \param bReceive flag indicating the type of communication with the slave -//! -//! This function configures the address that the I2C Master places on the -//! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address indicates that the I2C Master is initiating a -//! read from the slave; otherwise the address indicates that the I2C -//! Master is initiating a write to the slave. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, - bool bReceive) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Set the address of the slave with which the master will communicate. - // - HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; -} - -//***************************************************************************** -// -//! Reads the state of the SDA and SCL pins. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns the state of the I2C bus by providing the real time -//! values of the SDA and SCL pins. -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return Returns the state of the bus with SDA in bit position 1 and SCL in -//! bit position 0. -// -//***************************************************************************** -uint32_t -I2CMasterLineStateGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the line state. - // - return(HWREG(ui32Base + I2C_O_MBMON)); -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C Master is busy. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \return Returns \b true if the I2C Master is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns an indication of whether or not the I2C bus is busy. -//! This function can be used in a multi-master environment to determine if -//! another master is currently using the bus. -//! -//! \return Returns \b true if the I2C bus is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the bus busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Controls the state of the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Cmd command to be issued to the I2C Master. -//! -//! This function is used to control the state of the Master send and -//! receive operations. The \e ui8Cmd parameter can be one of the following -//! values: -//! -//! - \b I2C_MASTER_CMD_SINGLE_SEND -//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_BURST_SEND_START -//! - \b I2C_MASTER_CMD_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! - \b I2C_MASTER_CMD_QUICK_COMMAND -//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP -//! -//! \note Not all Tiva devices have an I2C FIFO and support the FIFO -//! commands. Please consult the device data sheet to determine if this -//! feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); - - // - // Send the command. - // - HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; -} - -//***************************************************************************** -// -//! Gets the error status of the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function is used to obtain the error status of the Master send -//! and receive operations. -//! -//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, -//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or -//! \b I2C_MASTER_ERR_ARB_LOST. -// -//***************************************************************************** -uint32_t -I2CMasterErr(uint32_t ui32Base) -{ - uint32_t ui32Err; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get the raw error state - // - ui32Err = HWREG(ui32Base + I2C_O_MCS); - - // - // If the I2C master is busy, then all the other bit are invalid, and - // don't have an error to report. - // - if(ui32Err & I2C_MCS_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) - { - return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data data to be transmitted from the I2C Master. -//! -//! This function places the supplied data into I2C Master Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_MDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CMasterDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_MDR)); -} - -//***************************************************************************** -// -//! Sets the Master clock timeout value. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Value is the number of I2C clocks before the timeout is -//! asserted. -//! -//! This function enables and configures the clock low timeout feature in the -//! I2C peripheral. This feature is implemented as a 12-bit counter, with the -//! upper 8-bits being programmable. For example, to program a timeout of 20ms -//! with a 100-kHz SCL frequency, \e ui32Value is 0x7d. -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the timeout value. - // - HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; -} - -//***************************************************************************** -// -//! Configures ACK override behavior of the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bEnable enables or disables ACK override. -//! -//! This function enables or disables ACK override, allowing the user -//! application to drive the value on SDA during the ACK cycle. -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable or disable based on bEnable. - // - if(bEnable) - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; - } -} - -//***************************************************************************** -// -//! Writes the ACK value. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. -//! -//! This function puts the desired ACK value on SDA during the ACK cycle. The -//! value written is only valid when ACK override is enabled using -//! I2CSlaveACKOverride(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // ACK or NACK based on the value of bACK. - // - if(bACK) - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; - } -} - -//***************************************************************************** -// -//! Gets the I2C Slave status -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns the action requested from a master, if any. -//! Possible values are: -//! -//! - \b I2C_SLAVE_ACT_NONE -//! - \b I2C_SLAVE_ACT_RREQ -//! - \b I2C_SLAVE_ACT_TREQ -//! - \b I2C_SLAVE_ACT_RREQ_FBR -//! - \b I2C_SLAVE_ACT_OWN2SEL -//! - \b I2C_SLAVE_ACT_QCMD -//! - \b I2C_SLAVE_ACT_QCMD_DATA -//! -//! \note Not all Tiva devices support the second I2C slave's own address -//! or the quick command function. Please consult the device data sheet to -//! determine if these features are supported. -//! -//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been -//! requested of the I2C Slave, \b I2C_SLAVE_ACT_RREQ to indicate that -//! an I2C master has sent data to the I2C Slave, \b I2C_SLAVE_ACT_TREQ -//! to indicate that an I2C master has requested that the I2C Slave send -//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent -//! data to the I2C slave and the first byte following the slave's own address -//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C -//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick -//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the -//! data bit was set when the quick command was received. -// -//***************************************************************************** -uint32_t -I2CSlaveStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the slave status. - // - return(HWREG(ui32Base + I2C_O_SCSR)); -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be transmitted from the I2C Slave -//! -//! This function places the supplied data into I2C Slave Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_SDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CSlaveDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_SDR)); -} - -//***************************************************************************** -// -//! Configures the I2C transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can -//! be used by the master or slave, but not both. The following macros are -//! used to configure the TX FIFO behavior for master or slave, with or without -//! DMA: -//! -//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE, -//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2, -//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4, -//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6, -//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8 -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; - - // - // Store new transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function flushes the I2C transmit FIFO. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; -} - -//***************************************************************************** -// -//! Configures the I2C receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be -//! used by the master or slave, but not both. The following macros are used -//! to configure the RX FIFO behavior for master or slave, with or without DMA: -//! -//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE, -//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2, -//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4, -//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6, -//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8 -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; - - // - // Store new receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function flushes the I2C receive FIFO. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; -} - -//***************************************************************************** -// -//! Gets the current FIFO status. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function retrieves the status for both the transmit (TX) and receive -//! (RX) FIFOs. The trigger level for the transmit FIFO is set using -//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return Returns the FIFO status, enumerated as a bit field containing -//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY, -//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and -//! \b I2C_FIFO_TX_EMPTY. -// -//***************************************************************************** -uint32_t -I2CFIFOStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the contents of the FIFO status register. - // - return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function waits for space to become -//! available before returning. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is space. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - } - - // - // Place data into the FIFO. - // - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function returns a zero. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return The number of elements added to the I2C transmit FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If FIFO is full, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - return(0); - } - else - { - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; - return(1); - } -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this function waits until data is received before returning. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return The data byte. -// -//***************************************************************************** -uint32_t -I2CFIFODataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is data to read. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - } - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_FIFODATA)); -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param pui8Data is a pointer where the read data is stored. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this functions returns 0. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return The number of elements read from the I2C receive FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If nothing in the FIFO, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - return(0); - } - else - { - *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); - return(1); - } -} - -//***************************************************************************** -// -//! Set the burst length for a I2C master FIFO operation. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Length is the length of the burst transfer. -//! -//! This function configures the burst length for a I2C Master FIFO operation. -//! The burst field is limited to 8 bits or 256 bytes. The burst length -//! applies to a single I2CMCS BURST operation meaning that it specifies the -//! burst length for only the current operation (can be TX or RX). Each burst -//! operation must configure the burst length prior to writing the BURST bit -//! in the I2CMCS using I2CMasterControl(). -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 256)); - - // - // Set the burst length. - // - HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; -} - -//***************************************************************************** -// -//! Returns the current value of the burst transfer counter. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function returns the current value of the burst transfer counter that -//! is used by the FIFO mechanism. Software can use this value to determine -//! how many bytes remain in a transfer, or where in the transfer the burst -//! operation was if an error has occurred. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -I2CMasterBurstCountGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get burst count. - // - return(HWREG(ui32Base + I2C_O_MBCNT)); -} - -//***************************************************************************** -// -//! Configures the I2C Master glitch filter. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the glitch filter configuration. -//! -//! This function configures the I2C Master glitch filter. The value passed in -//! to \e ui32Config determines the sampling range of the glitch filter, which -//! is configurable between 1 and 32 system clock cycles. The default -//! configuration of the glitch filter is 0 system clock cycles, which means -//! that it's disabled. -//! -//! The \e ui32Config field should be any of the following values: -//! -//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED -//! - \b I2C_MASTER_GLITCH_FILTER_1 -//! - \b I2C_MASTER_GLITCH_FILTER_2 -//! - \b I2C_MASTER_GLITCH_FILTER_3 -//! - \b I2C_MASTER_GLITCH_FILTER_4 -//! - \b I2C_MASTER_GLITCH_FILTER_8 -//! - \b I2C_MASTER_GLITCH_FILTER_16 -//! - \b I2C_MASTER_GLITCH_FILTER_32 -//! -//! \note Not all Tiva devices support this function. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Configure the glitch filter field of MTPR if it is TM4C129 - // - if(CLASS_IS_TM4C129) - { - HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; - } - - // - // Configure the glitch filter if it is TM4C123 - // - if(CLASS_IS_TM4C123) - { - // - // Configure the glitch filter pulse width - // - HWREG(ui32Base + I2C_O_MCR2) |= (ui32Config >> 12); - - // - // Enable the glitch filter by setting the GFE bit - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_GFE; - } -} - -//***************************************************************************** -// -//! Enables FIFO usage for the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Config is the desired FIFO configuration of the I2C Slave. -//! -//! This function configures the I2C Slave to use the FIFO(s). This -//! function should be used in combination with I2CTxFIFOConfigSet() and/or -//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell -//! the FIFO hardware whether to interact with the I2C Master or Slave. The -//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and -//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config -//! field. -//! -//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), -//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. -//! Therefore, application software should call I2CSlaveEnable() followed by -//! I2CSlaveFIFOEnable() with the desired FIFO configuration. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the FIFOs for the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disable FIFO usage for the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function disables the FIFOs for the I2C Slave. After calling this -//! this function, the FIFOs are disabled, but the Slave remains active. -//! -//! \note Not all Tiva devices have an I2C FIFO. Please consult the -//! device data sheet to determine if this feature is supported. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFODisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable slave FIFOs. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Enables internal loopback mode for an I2C port. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function configures an I2C port in internal loopback mode to help with -//! diagnostics and debug. In this mode, the SDA and SCL signals from master -//! and slave modules are internally connected. This allows data to be -//! transferred between the master and slave modules of the same I2C port, -//! without having to go through I/O's. I2CMasterDataPut(), I2CSlaveDataPut(), -//! I2CMasterDataGet(),I2CSlaveDataGet() can be used along with this function. -//! -//! \return None. -// -//***************************************************************************** -void I2CLoopbackEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the loopback enable bit to the register. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_LPBK; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/i2c.h b/bsp/tm4c129x-dk/libraries/driverlib/i2c.h deleted file mode 100644 index ab7b44e4fe..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/i2c.h +++ /dev/null @@ -1,362 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_I2C_H__ -#define __DRIVERLIB_I2C_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** - -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ - 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_QUICK_COMMAND \ - 0x00000027 -#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ - 0x00000013 -#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ - 0x00000042 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ - 0x00000040 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ - 0x0000004a -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ - 0x00000048 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 - -//***************************************************************************** -// -// I2C Master glitch filter configuration. -// -//***************************************************************************** -#define I2C_MASTER_GLITCH_FILTER_DISABLED \ - 0 -#define I2C_MASTER_GLITCH_FILTER_1 \ - 0x00010000 -#define I2C_MASTER_GLITCH_FILTER_2 \ - 0x00020000 -#define I2C_MASTER_GLITCH_FILTER_3 \ - 0x00030000 -#define I2C_MASTER_GLITCH_FILTER_4 \ - 0x00040000 -#define I2C_MASTER_GLITCH_FILTER_8 \ - 0x00050000 -#define I2C_MASTER_GLITCH_FILTER_16 \ - 0x00060000 -#define I2C_MASTER_GLITCH_FILTER_32 \ - 0x00070000 - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 -#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte -#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave -#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command -#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value - -//***************************************************************************** -// -// Miscellaneous I2C driver definitions. -// -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// I2C Master interrupts. -// -//***************************************************************************** -#define I2C_MASTER_INT_RX_FIFO_FULL \ - 0x00000800 // RX FIFO Full Interrupt -#define I2C_MASTER_INT_TX_FIFO_EMPTY \ - 0x00000400 // TX FIFO Empty Interrupt -#define I2C_MASTER_INT_RX_FIFO_REQ \ - 0x00000200 // RX FIFO Request Interrupt -#define I2C_MASTER_INT_TX_FIFO_REQ \ - 0x00000100 // TX FIFO Request Interrupt -#define I2C_MASTER_INT_ARB_LOST \ - 0x00000080 // Arb Lost Interrupt -#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt -#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt -#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt -#define I2C_MASTER_INT_TX_DMA_DONE \ - 0x00000008 // TX DMA Complete Interrupt -#define I2C_MASTER_INT_RX_DMA_DONE \ - 0x00000004 // RX DMA Complete Interrupt -#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt -#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave interrupts. -// -//***************************************************************************** -#define I2C_SLAVE_INT_RX_FIFO_FULL \ - 0x00000100 // RX FIFO Full Interrupt -#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ - 0x00000080 // TX FIFO Empty Interrupt -#define I2C_SLAVE_INT_RX_FIFO_REQ \ - 0x00000040 // RX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_FIFO_REQ \ - 0x00000020 // TX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_DMA_DONE \ - 0x00000010 // TX DMA Complete Interrupt -#define I2C_SLAVE_INT_RX_DMA_DONE \ - 0x00000008 // RX DMA Complete Interrupt -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave FIFO configuration macros. -// -//***************************************************************************** -#define I2C_SLAVE_TX_FIFO_ENABLE \ - 0x00000002 -#define I2C_SLAVE_RX_FIFO_ENABLE \ - 0x00000004 - -//***************************************************************************** -// -// I2C FIFO configuration macros. -// -//***************************************************************************** -#define I2C_FIFO_CFG_TX_MASTER 0x00000000 -#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 -#define I2C_FIFO_CFG_RX_MASTER 0x00000000 -#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 -#define I2C_FIFO_CFG_TX_MASTER_DMA \ - 0x00002000 -#define I2C_FIFO_CFG_TX_SLAVE_DMA \ - 0x0000a000 -#define I2C_FIFO_CFG_RX_MASTER_DMA \ - 0x20000000 -#define I2C_FIFO_CFG_RX_SLAVE_DMA \ - 0xa0000000 -#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 -#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 -#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 -#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 -#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 -#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 -#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 -#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 -#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 -#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 -#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 -#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 -#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 -#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 -#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 -#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 - -//***************************************************************************** -// -// I2C FIFO status. -// -//***************************************************************************** -#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ - 0x00040000 -#define I2C_FIFO_RX_FULL 0x00020000 -#define I2C_FIFO_RX_EMPTY 0x00010000 -#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ - 0x00000004 -#define I2C_FIFO_TX_FULL 0x00000002 -#define I2C_FIFO_TX_EMPTY 0x00000001 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); -extern void I2CIntUnregister(uint32_t ui32Base); -extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CTxFIFOFlush(uint32_t ui32Base); -extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CRxFIFOFlush(uint32_t ui32Base); -extern uint32_t I2CFIFOStatus(uint32_t ui32Base); -extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); -extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, - uint8_t ui8Data); -extern uint32_t I2CFIFODataGet(uint32_t ui32Base); -extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, - uint8_t *pui8Data); -extern void I2CMasterBurstLengthSet(uint32_t ui32Base, - uint8_t ui8Length); -extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); -extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, - uint32_t ui32Config); -extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CSlaveFIFODisable(uint32_t ui32Base); -extern bool I2CMasterBusBusy(uint32_t ui32Base); -extern bool I2CMasterBusy(uint32_t ui32Base); -extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); -extern uint32_t I2CMasterDataGet(uint32_t ui32Base); -extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CMasterDisable(uint32_t ui32Base); -extern void I2CMasterEnable(uint32_t ui32Base); -extern uint32_t I2CMasterErr(uint32_t ui32Base); -extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast); -extern void I2CMasterIntClear(uint32_t ui32Base); -extern void I2CMasterIntDisable(uint32_t ui32Base); -extern void I2CMasterIntEnable(uint32_t ui32Base); -extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); -extern void I2CMasterIntEnableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern void I2CMasterIntClearEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); -extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); -extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); -extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); -extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, - uint8_t ui8SlaveAddr, - bool bReceive); -extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); -extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CSlaveDisable(uint32_t ui32Base); -extern void I2CSlaveEnable(uint32_t ui32Base); -extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); -extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, - uint8_t ui8SlaveAddr); -extern void I2CSlaveIntClear(uint32_t ui32Base); -extern void I2CSlaveIntDisable(uint32_t ui32Base); -extern void I2CSlaveIntEnable(uint32_t ui32Base); -extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void I2CSlaveIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); -extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern uint32_t I2CSlaveStatus(uint32_t ui32Base); -extern void I2CLoopbackEnable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_I2C_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.c b/bsp/tm4c129x-dk/libraries/driverlib/interrupt.c deleted file mode 100644 index ebf5f95bd3..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.c +++ /dev/null @@ -1,1060 +0,0 @@ -//***************************************************************************** -// -// interrupt.c - Driver for the NVIC Interrupt Controller. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/cpu.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -static const uint32_t g_pui32Priority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32Regs[] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, - NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, - NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, - NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, - NVIC_PRI32, NVIC_PRI33, NVIC_PRI34 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt enable for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32EnRegs[] = -{ - NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt disable for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32Dii16Regs[] = -{ - NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt pend for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32PendRegs[] = -{ - NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt unpend for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32UnpendRegs[] = -{ - NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4 -}; - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts must be disabled before unregistering the -//! corresponding handler, this should never be called during normal operation. -//! -//! \return None. -// -//***************************************************************************** -static void -_IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// The processor vector table. -// -// This contains a list of the handlers for the various interrupt sources in -// the system. The layout of this list is defined by the hardware; assertion -// of an interrupt causes the processor to start executing directly at the -// address given in the corresponding location in this list. -// -//***************************************************************************** -// -// Set the size of the vector table to the largest number of interrupts of -// any device -// -#undef NUM_INTERRUPTS -#define NUM_INTERRUPTS 155 -#if defined(ewarm) -#pragma data_alignment=1024 -static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; -#elif defined(sourcerygxx) -static __attribute__((section(".cs3.region-head.ram"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024))); -#elif defined(ccs) || defined(DOXYGEN) -#pragma DATA_ALIGN(g_pfnRAMVectors, 1024) -#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable") -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#else -static __attribute__((section("vtable"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(1024))); -#endif - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! This function allows the processor to respond to interrupts. This function -//! does not affect the set of interrupts enabled in the interrupt controller; -//! it just gates the single interrupt from the controller to the processor. -//! -//! \b Example: Enable interrupts to the processor. -//! -//! \verbatim -//! // -//! // Enable interrupts to the processor. -//! // -//! IntMasterEnable(); -//! -//! \endverbatim -//! -//! \return Returns \b true if interrupts were disabled when the function was -//! called or \b false if they were initially enabled. -// -//***************************************************************************** -bool -IntMasterEnable(void) -{ - // - // Enable processor interrupts. - // - return(CPUcpsie()); -} - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! This function prevents the processor from receiving interrupts. This -//! function does not affect the set of interrupts enabled in the interrupt -//! controller; it just gates the single interrupt from the controller to the -//! processor. -//! -//! \note Previously, this function had no return value. As such, it was -//! possible to include interrupt.h and call this function without -//! having included hw_types.h. Now that the return is a -//! bool, a compiler error occurs in this case. The solution -//! is to include hw_types.h before including interrupt.h. -//! -//! \b Example: Disable interrupts to the processor. -//! -//! \verbatim -//! // -//! // Disable interrupts to the processor. -//! // -//! IntMasterDisable(); -//! -//! \endverbatim -//! -//! \return Returns \b true if interrupts were already disabled when the -//! function was called or \b false if they were initially enabled. -// -//***************************************************************************** -bool -IntMasterDisable(void) -{ - // - // Disable processor interrupts. - // - return(CPUcpsid()); -} - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! \param pfnHandler is a pointer to the function to be called. -//! -//! This function is used to specify the handler function to be called when the -//! given interrupt is asserted to the processor. The \e ui32Interrupt -//! parameter must be one of the valid \b INT_* values listed in Peripheral -//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. -//! When the interrupt occurs, if it is enabled (via IntEnable()), the handler -//! function is called in interrupt context. Because the handler function can -//! preempt other code, care must be taken to protect memory or peripherals -//! that are accessed by the handler and other non-handler code. -//! -//! \note The use of this function (directly or indirectly via a peripheral -//! driver interrupt register function) moves the interrupt vector table from -//! flash to SRAM. Therefore, care must be taken when linking the application -//! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise the NVIC does not look in the correct portion of memory for the -//! vector table (it requires the vector table be on a 1 kB memory alignment). -//! Normally, the SRAM vector table is so placed via the use of linker scripts. -//! See the discussion of compile-time versus run-time interrupt handler -//! registration in the introduction to this chapter. -//! -//! \b Example: Set the UART 0 interrupt handler. -//! -//! \verbatim -//! -//! // -//! // UART 0 interrupt handler. -//! // -//! void -//! UART0Handler(void) -//! { -//! // -//! // Handle interrupt. -//! // -//! } -//! -//! // -//! // Set the UART 0 interrupt handler. -//! // -//! IntRegister(INT_UART0, UART0Handler); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) -{ - uint32_t ui32Idx, ui32Value; - - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Make sure that the RAM vector table is correctly aligned. - // - ASSERT(((uint32_t)g_pfnRAMVectors & 0x000003ff) == 0); - - // - // See if the RAM vector table has been initialized. - // - if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) - { - // - // Copy the vector table from the beginning of FLASH to the RAM vector - // table. - // - ui32Value = HWREG(NVIC_VTABLE); - for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) - { - g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + - ui32Value); - } - - // - // Point the NVIC at the RAM vector table. - // - HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; - } - - // - // Save the interrupt handler. - // - g_pfnRAMVectors[ui32Interrupt] = pfnHandler; -} - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! -//! This function is used to indicate that no handler is called when the -//! given interrupt is asserted to the processor. The \e ui32Interrupt -//! parameter must be one of the valid \b INT_* values listed in Peripheral -//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. -//! The interrupt source is automatically disabled (via IntDisable()) if -//! necessary. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \b Example: Reset the UART 0 interrupt handler to the default handler. -//! -//! \verbatim -//! // -//! // Reset the UART 0 interrupt handler to the default handler. -//! // -//! IntUnregister(INT_UART0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntUnregister(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Reset the interrupt handler. - // - g_pfnRAMVectors[ui32Interrupt] = _IntDefaultHandler; -} - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param ui32Bits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! sub-priority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the Tiva C and E Series family, three bits are available for hardware -//! interrupt prioritization and therefore priority grouping values of three -//! through seven have the same effect. -//! -//! \b Example: Set the priority grouping for the interrupt controller. -//! -//! \verbatim -//! // -//! // Set the priority grouping for the interrupt controller to 2 bits. -//! // -//! IntPriorityGroupingSet(2); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityGroupingSet(uint32_t ui32Bits) -{ - // - // Check the arguments. - // - ASSERT(ui32Bits < NUM_PRIORITY); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; -} - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! sub-priority levels in the interrupt priority specification. -//! -//! \b Example: Get the priority grouping for the interrupt controller. -//! -//! \verbatim -//! // -//! // Get the priority grouping for the interrupt controller. -//! // -//! IntPriorityGroupingGet(); -//! -//! \endverbatim -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -uint32_t -IntPriorityGroupingGet(void) -{ - uint32_t ui32Loop, ui32Value; - - // - // Read the priority grouping. - // - ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) - { - // - // Stop looping if this value matches. - // - if(ui32Value == g_pui32Priority[ui32Loop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ui32Loop); -} - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! \param ui8Priority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. The \e ui8Priority parameter specifies the interrupts -//! hardware priority level of the interrupt in the interrupt controller. -//! When multiple interrupts are asserted simultaneously, the ones with the -//! highest priority are processed before the lower priority interrupts. -//! Smaller numbers correspond to higher interrupt priorities; priority 0 is -//! the highest interrupt priority. -//! -//! \note The hardware priority mechanism only looks at the upper 3 bits of the -//! priority level, so any prioritization must be performed in those bits. The -//! remaining bits can be used to sub-prioritize the interrupt sources, and may -//! be used by the hardware priority mechanism on a future part. This -//! arrangement allows priorities to migrate to different NVIC implementations -//! without changing the gross prioritization of the interrupts. -//! -//! \b Example: Set priorities for UART 0 and USB interrupts. -//! -//! \verbatim -//! // -//! // Set the UART 0 interrupt priority to the lowest priority. -//! // -//! IntPrioritySet(INT_UART0, 0xE0); -//! -//! // -//! // Set the USB 0 interrupt priority to the highest priority. -//! // -//! IntPrioritySet(INT_USB0, 0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Set the interrupt priority. - // - ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); - ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); - ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); - HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; -} - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. The \e ui32Interrupt -//! parameter must be one of the valid \b INT_* values listed in Peripheral -//! Driver Library User's Guide and defined in the inc/hw_ints.h header file. -//! See IntPrioritySet() for a full definition of the priority value. -//! -//! \b Example: Get the current UART 0 interrupt priority. -//! -//! \verbatim -//! // -//! // Get the current UART 0 interrupt priority. -//! // -//! IntPriorityGet(INT_UART0); -//! -//! \endverbatim -//! -//! \return Returns the interrupt priority for the given interrupt. -// -//***************************************************************************** -int32_t -IntPriorityGet(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> - (8 * (ui32Interrupt & 3))) & 0xFF); -} - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. Other enables for the interrupt (such as at the peripheral -//! level) are unaffected by this function. -//! -//! \b Example: Enable the UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Enable the UART 0 interrupt in the interrupt controller. -//! // -//! IntEnable(INT_UART0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntEnable(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - } - else if(ui32Interrupt >= 16) - { - // - // Enable the general interrupt. - // - HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. Other enables for the interrupt (such as at the peripheral -//! level) are unaffected by this function. -//! -//! \b Example: Disable the UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Disable the UART 0 interrupt in the interrupt controller. -//! // -//! IntDisable(INT_UART0); -//! -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntDisable(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - } - else if(ui32Interrupt >= 16) - { - // - // Disable the general interrupt. - // - HWREG(g_pui32Dii16Regs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Returns if a peripheral interrupt is enabled. -//! -//! \param ui32Interrupt specifies the interrupt to check. -//! -//! This function checks if the specified interrupt is enabled in the interrupt -//! controller. The \e ui32Interrupt parameter must be one of the valid -//! \b INT_* values listed in Peripheral Driver Library User's Guide and -//! defined in the inc/hw_ints.h header file. -//! -//! \b Example: Disable the UART 0 interrupt if it is enabled. -//! -//! \verbatim -//! // -//! // Disable the UART 0 interrupt if it is enabled. -//! // -//! if(IntIsEnabled(INT_UART0)) -//! { -//! IntDisable(INT_UART0); -//! } -//! \endverbatim -//! -//! \return A non-zero value if the interrupt is enabled. -// -//***************************************************************************** -uint32_t -IntIsEnabled(uint32_t ui32Interrupt) -{ - uint32_t ui32Ret; - - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Initialize the return value. - // - ui32Ret = 0; - - // - // Determine the interrupt to disable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Check the MemManage interrupt. - // - ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM; - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Check the bus fault interrupt. - // - ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS; - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Check the usage fault interrupt. - // - ui32Ret = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Check the System Tick interrupt. - // - ui32Ret = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN; - } - else if(ui32Interrupt >= 16) - { - // - // Check the general interrupt. - // - ui32Ret = HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) & - (1 << ((ui32Interrupt - 16) & 31)); - } - return(ui32Ret); -} - -//***************************************************************************** -// -//! Pends an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be pended. -//! -//! The specified interrupt is pended in the interrupt controller. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. Pending an interrupt causes the interrupt controller to -//! execute the corresponding interrupt handler at the next available time, -//! based on the current interrupt state priorities. For example, if called by -//! a higher priority interrupt handler, the specified interrupt handler is not -//! called until after the current interrupt handler has completed execution. -//! The interrupt must have been enabled for it to be called. -//! -//! \b Example: Pend a UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Pend a UART 0 interrupt. -//! // -//! IntPendSet(INT_UART0); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPendSet(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to pend. - // - if(ui32Interrupt == FAULT_NMI) - { - // - // Pend the NMI interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; - } - else if(ui32Interrupt == FAULT_PENDSV) - { - // - // Pend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Pend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; - } - else if(ui32Interrupt >= 16) - { - // - // Pend the general interrupt. - // - HWREG(g_pui32PendRegs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Un-pends an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be un-pended. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. -//! -//! The specified interrupt is un-pended in the interrupt controller. This -//! causes any previously generated interrupts that have not been handled -//! yet (due to higher priority interrupts or the interrupt not having been -//! enabled yet) to be discarded. -//! -//! \b Example: Un-pend a UART 0 interrupt. -//! -//! \verbatim -//! // -//! // Un-pend a UART 0 interrupt. -//! // -//! IntPendClear(INT_UART0); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPendClear(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to unpend. - // - if(ui32Interrupt == FAULT_PENDSV) - { - // - // Unpend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Unpend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; - } - else if(ui32Interrupt >= 16) - { - // - // Unpend the general interrupt. - // - HWREG(g_pui32UnpendRegs[(ui32Interrupt - 16) / 32]) = - 1 << ((ui32Interrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Sets the priority masking level -//! -//! \param ui32PriorityMask is the priority level that is masked. -//! -//! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level are masked. Masking -//! interrupts can be used to globally disable a set of interrupts with -//! priority below a predetermined threshold. A value of 0 disables priority -//! masking. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 allows interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater are blocked. -//! -//! \note The hardware priority mechanism only looks at the upper 3 bits of the -//! priority level, so any prioritization must be performed in those bits. -//! -//! \b Example: Mask of interrupt priorities greater than or equal to 0x80. -//! -//! \verbatim -//! // -//! // Mask of interrupt priorities greater than or equal to 0x80. -//! // -//! IntPriorityMaskSet(0x80); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityMaskSet(uint32_t ui32PriorityMask) -{ - // - // Set the priority mask. - // - CPUbasepriSet(ui32PriorityMask); -} - -//***************************************************************************** -// -//! Gets the priority masking level -//! -//! This function gets the current setting of the interrupt priority masking -//! level. The value returned is the priority level such that all interrupts -//! of that and lesser priority are masked. A value of 0 means that priority -//! masking is disabled. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 allows interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater are blocked. -//! -//! The hardware priority mechanism only looks at the upper 3 bits of the -//! priority level, so any prioritization must be performed in those bits. -//! -//! \b Example: Get the current interrupt priority mask. -//! -//! \verbatim -//! // -//! // Get the current interrupt priority mask. -//! // -//! IntPriorityMaskGet(); -//! \endverbatim -//! -//! \return Returns the value of the interrupt priority level mask. -// -//***************************************************************************** -uint32_t -IntPriorityMaskGet(void) -{ - // - // Return the current priority mask. - // - return(CPUbasepriGet()); -} - -//***************************************************************************** -// -//! Triggers an interrupt. -//! -//! \param ui32Interrupt specifies the interrupt to be triggered. -//! -//! This function performs a software trigger of an interrupt. The -//! \e ui32Interrupt parameter must be one of the valid \b INT_* values listed -//! in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h -//! header file. The interrupt controller behaves as if the corresponding -//! interrupt line was asserted, and the interrupt is handled in the same -//! manner (meaning that it must be enabled in order to be processed, and the -//! processing is based on its priority with respect to other unhandled -//! interrupts). -//! -//! \return None. -// -//***************************************************************************** -void -IntTrigger(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 16) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Trigger this interrupt. - // - HWREG(NVIC_SW_TRIG) = ui32Interrupt - 16; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.h b/bsp/tm4c129x-dk/libraries/driverlib/interrupt.h deleted file mode 100644 index effb30c88a..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/interrupt.h +++ /dev/null @@ -1,94 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_INTERRUPT_H__ -#define __DRIVERLIB_INTERRUPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Macro to generate an interrupt priority mask based on the number of bits -// of priority supported by the hardware. -// -//***************************************************************************** -#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern bool IntMasterEnable(void); -extern bool IntMasterDisable(void); -extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); -extern void IntUnregister(uint32_t ui32Interrupt); -extern void IntPriorityGroupingSet(uint32_t ui32Bits); -extern uint32_t IntPriorityGroupingGet(void); -extern void IntPrioritySet(uint32_t ui32Interrupt, - uint8_t ui8Priority); -extern int32_t IntPriorityGet(uint32_t ui32Interrupt); -extern void IntEnable(uint32_t ui32Interrupt); -extern void IntDisable(uint32_t ui32Interrupt); -extern uint32_t IntIsEnabled(uint32_t ui32Interrupt); -extern void IntPendSet(uint32_t ui32Interrupt); -extern void IntPendClear(uint32_t ui32Interrupt); -extern void IntPriorityMaskSet(uint32_t ui32PriorityMask); -extern uint32_t IntPriorityMaskGet(void); -extern void IntTrigger(uint32_t ui32Interrupt); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_INTERRUPT_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/lcd.c b/bsp/tm4c129x-dk/libraries/driverlib/lcd.c deleted file mode 100644 index 195d0ef0ba..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/lcd.c +++ /dev/null @@ -1,1805 +0,0 @@ -//***************************************************************************** -// -// lcd.c - Defines and Macros for the LCD Controller module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup lcd_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_lcd.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "driverlib/lcd.h" -#include "driverlib/debug.h" - -//***************************************************************************** -// -// These are currently missing from hw_lcd.h and included here as a stopgap -// until the hardware header is updated. -// -//***************************************************************************** -#ifndef LCD_RASTRTIM0_MSBPPL_S -#define LCD_RASTRTIM0_MSBPPL_S 3 -#endif -#ifndef LCD_RASTRTIM2_MSBLPP_S -#define LCD_RASTRTIM2_MSBLPP_S 26 -#endif - -//***************************************************************************** -// -//! Configures the basic operating mode and clock rate for the LCD controller. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui8Mode specifies the basic operating mode to be used. -//! \param ui32PixClk specifies the desired LCD controller pixel or master -//! clock rate in Hz. -//! \param ui32SysClk specifies the current system clock rate in Hz. -//! -//! This function sets the basic operating mode of the LCD controller and also -//! its master clock. The \e ui8Mode parameter may be set to either \b -//! LCD_MODE_LIDD or \b LCD_MODE_RASTER. \b LCD_MODE_LIDD is used to select -//! LCD Interface Display Driver mode for character panels connected via -//! an asynchronous interface (CS, WE, OE, ALE, data) and \b LCD_MODE_RASTER -//! is used to communicate with panels via a synchronous video interface using -//! data and sync signals. Additionally, \b LCD_MODE_AUTO_UFLOW_RESTART may -//! be ORed with either of these modes to indicate that the hardware should -//! restart automatically if a data underflow occurs. -//! -//! The \e ui32PixClk parameter specifies the desired master clock for the -//! the LCD controller. In LIDD mode, this value controls the MCLK used in -//! communication with the display and valid values are between \e ui32SysClk -//! and \e ui32SysClk/255. In raster mode, \e ui32PixClk specifies the pixel -//! clock rate for the raster interface and valid values are between \e -//! ui32SysClk/2 and \e ui32SysClk/255. The actual clock rate set may differ -//! slightly from the desired rate due to the fact that only integer dividers -//! are supported. The rate set will, however, be no higher than the requested -//! value. -//! -//! The \e ui32SysClk parameter provides the current system clock rate and is -//! used to allow the LCD controller clock rate divisor to be correctly set -//! to give the desired \e ui32PixClk rate. -//! -//! \return Returns the actual LCD controller pixel clock or MCLK rate set. -// -//***************************************************************************** -uint32_t -LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, uint32_t ui32PixClk, - uint32_t ui32SysClk) -{ - uint32_t ui32Div; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui8Mode & ~(LCD_MODE_RASTER | LCD_MODE_LIDD | - LCD_MODE_AUTO_UFLOW_RESTART)) == 0); - - // - // Enable clocks to the LCD controller submodules. - // - HWREG(ui32Base + LCD_O_CLKEN) = (LCD_CLKEN_DMA | LCD_CLKEN_CORE | - LCD_CLKEN_LIDD); - - // - // Determine the clock divider to use to get as close as possible to the - // desired pixel clock. Note that we set the division up so that we - // round the divisor up and ensure that the clock used is never faster - // than the requested rate. - // - ui32Div = (ui32SysClk + (ui32PixClk - 1)) / ui32PixClk; - - // - // Check that the calculated value is valid. - // - ASSERT(ui32Div); - ASSERT(ui32Div < 256); - ASSERT(!((ui8Mode & LCD_MODE_RASTER) && (ui32Div < 2))); - - // - // Write the LCDCTL register to set the mode. - // - HWREG(ui32Base + LCD_O_CTL) = (uint32_t)ui8Mode | - (ui32Div << LCD_CTL_CLKDIV_S); - - // - // Return the selected clock rate. Finding ui32Div set to 0 should not - // happen unless someone passed pathological arguments and builds without - // the ASSERTS, but we guard against it just in case. - // - return(ui32Div ? (ui32SysClk / ui32Div) : ui32SysClk); -} - -//***************************************************************************** -// -//! Resets one or more of the LCD controller clock domains. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32Clocks defines the subset of clock domains to be reset. -//! -//! This function allows sub-modules of the LCD controller to be reset under -//! software control. The \e ui32Clocks parameter is the logical OR of the -//! following clocks: -//! -//! - \b LCD_CLOCK_MAIN causes the entire LCD controller module to be reset. -//! - \b LCD_CLOCK_DMA causes the DMA controller submodule to be reset. -//! - \b LCD_CLOCK_LIDD causes the LIDD submodule to be reset. -//! - \b LCD_CLOCK_CORE causes the core module, including the raster logic to -//! be reset. -//! -//! In all cases, LCD controller register values are preserved across these -//! resets. -//! -//! \return None. -// -//***************************************************************************** -void -LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Clocks & ~(LCD_CLOCK_MAIN | LCD_CLOCK_LIDD | LCD_CLOCK_DMA | - LCD_CLOCK_CORE))); - - // - // Reset the required LCD controller sub-module(s). - // - HWREG(LCD0_BASE + 0x70) = ui32Clocks; - - // - // Wait a while. - // - SysCtlDelay(10); - - // - // Remove software reset. - // - HWREG(LCD0_BASE + 0x70) = 0x00000000; - - // - // Wait a while. - // - SysCtlDelay(10); -} - -//***************************************************************************** -// -//! Sets the LCD controller communication parameters when in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32Config defines the display interface configuration. -//! -//! This function is used when the LCD controller is configured in LIDD -//! mode and specifies the configuration of the interface between the -//! controller and the display panel. The \e ui32Config parameter is -//! comprised of one of the following modes: -//! -//! - \b LIDD_CONFIG_SYNC_MPU68 selects Sync MPU68 mode. LCDCP = EN, LCDLP = -//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK. -//! - \b LIDD_CONFIG_ASYNC_MPU68 selects Async MPU68 mode. LCDCP = EN, LCDLP = -//! DIR, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1. -//! - \b LIDD_CONFIG_SYNC_MPU80 selects Sync MPU80 mode. LCDCP = RS, LCDLP = -//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = MCLK. -//! - \b LIDD_CONFIG_ASYNC_MPU80 selects Async MPU80 mode. LCDCP = RS, LCDLP = -//! WS, LCDFP = ALE, LCDAC = CS0, LCDMCLK = CS1. -//! - \b LIDD_CONFIG_ASYNC_HITACHI selects Hitachi (async) mode. LCDCP = N/C, -//! LCDLP = DIR, LCDFP = ALE, LCDAC = E0, LCDMCLK = E1. -//! -//! Additional flags may be ORed into \e ui32Config to control the polarities -//! of various control signals: -//! -//! - \b LIDD_CONFIG_INVERT_ALE - Address Latch Enable (ALE) polarity control. -//! By default, ALE is active low. If this flag is set, it becomes active -//! high. -//! - \b LIDD_CONFIG_INVERT_RS_EN - Read Strobe/Enable polarity control. By -//! default, RS is active low and Enable is active high. If this flag is set, -//! RS becomes active high and Enable active low. -//! - \b LIDD_CONFIG_INVERT_WS_DIR - Write Strobe/Direction polarity control. -//! By default, WS is active low and Direction write low/read high. If this -//! flag is set, WS becomes active high and Direction becomes write high/read -//! low. -//! - \b LIDD_CONFIG_INVERT_CS0 - Chip Select 0/Enable 0 polarity control. By -//! default, CS0 and E0 are active high. If this flag is set, they become -//! active low. -//! - \b LIDD_CONFIG_INVERT_CS1 - Chip Select 1/Enable 1 polarity control. By -//! default, CS1 and E1 are active high. If this flag is set, they become -//! active low. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Config & ~(LIDD_CONFIG_SYNC_MPU68 | LIDD_CONFIG_ASYNC_MPU68 | - LIDD_CONFIG_SYNC_MPU80 | LIDD_CONFIG_ASYNC_MPU80 | - LIDD_CONFIG_ASYNC_HITACHI | - LIDD_CONFIG_INVERT_ALE | - LIDD_CONFIG_INVERT_RS_EN | - LIDD_CONFIG_INVERT_WS_DIR | - LIDD_CONFIG_INVERT_CS0 | LIDD_CONFIG_INVERT_CS1))); - - // - // Write the LIDD Control Register. - // - HWREG(ui32Base + LCD_O_LIDDCTL) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the LCD controller interface timing when in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select whose timings are to be set. -//! \param pTiming points to a structure containing the desired timing -//! parameters. -//! -//! This function is used in LIDD mode to set the setup, strobe and hold times -//! for the various interface control signals. Independent timings are stored -//! for each of the two supported chip selects offered by the LCD controller. -//! -//! For a definition of the timing parameters required, see the definition of -//! tLCDIDDTiming. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None -// -//***************************************************************************** -void -LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS, - const tLCDIDDTiming *pTiming) -{ - uint32_t ui32Val; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - ASSERT(pTiming); - ASSERT(pTiming->ui8WSSetup < 32); - ASSERT(pTiming->ui8WSDuration && (pTiming->ui8WSDuration < 64)); - ASSERT(pTiming->ui8WSHold && (pTiming->ui8WSHold < 16)); - ASSERT(pTiming->ui8RSSetup < 32); - ASSERT(pTiming->ui8RSDuration && (pTiming->ui8RSDuration < 64)); - ASSERT(pTiming->ui8RSHold && (pTiming->ui8RSHold < 16)); - ASSERT(pTiming->ui8DelayCycles && (pTiming->ui8DelayCycles < 5)); - - // - // Convert the timings provided into a value ready for the register. - // - ui32Val = - (((uint32_t)(pTiming->ui8WSSetup) << LCD_LIDDCS0CFG_WRSU_S) | - ((uint32_t)(pTiming->ui8WSDuration) << LCD_LIDDCS0CFG_WRDUR_S) | - ((uint32_t)(pTiming->ui8WSHold) << LCD_LIDDCS0CFG_WRHOLD_S) | - ((uint32_t)(pTiming->ui8RSSetup) << LCD_LIDDCS0CFG_RDSU_S) | - ((uint32_t)(pTiming->ui8RSDuration) << LCD_LIDDCS0CFG_RDDUR_S) | - ((uint32_t)(pTiming->ui8RSHold) << LCD_LIDDCS0CFG_RDHOLD_S) | - ((uint32_t)(pTiming->ui8DelayCycles - 1) << LCD_LIDDCS0CFG_GAP_S)); - - // - // Write the appropriate LCD LIDD CS configuration register. - // - if(!ui32CS) - { - HWREG(ui32Base + LCD_O_LIDDCS0CFG) = ui32Val; - } - else - { - HWREG(ui32Base + LCD_O_LIDDCS1CFG) = ui32Val; - } -} - -//***************************************************************************** -// -//! Disables internal DMA operation when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! -//! When the LCD controller is operating in LCD Interface Display Driver mode, -//! this function must be called after completion of a DMA transaction and -//! before calling LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(), -//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead() to disable -//! DMA mode and allow CPU-initiated transactions to the display. -//! -//! \note LIDD DMA mode is enabled automatically when LCDIDDDMAWrite() is -//! called. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDDMADisable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable DMA. - // - HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN; -} - -//***************************************************************************** -// -//! Writes a command to the display when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Cmd is the 16-bit command word to write. -//! -//! This function writes a 16-bit command word to the display when the LCD -//! controller is in LIDD mode. A command write occurs with the ALE signal -//! active. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Cmd) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to write based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Write the command/address to the register. - // - HWREG(ui32Base + ui32Reg) = ui16Cmd; -} - -//***************************************************************************** -// -//! Writes a data value to the display when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Data is the 16-bit data word to write. -//! -//! This function writes a 16-bit data word to the display when the LCD -//! controller is in LIDD mode. A data write occurs with the ALE signal -//! inactive. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Data) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to write based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Write the data value to the register. - // - HWREG(ui32Base + ui32Reg) = ui16Data; -} - -//***************************************************************************** -// -//! Writes data to a given display register when the LCD controller is in LIDD -//! mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Addr is the address of the display register to write. -//! \param ui16Data is the data to write. -//! -//! This function writes a 16-bit data word to a register in the display when -//! the LCD controller is in LIDD mode and configured to use either the -//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or -//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes -//! that employ an external address latch. -//! -//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this -//! function should not be used. In this case the functions -//! LCDIDDCommandWrite() and LCDIDDDataWrite() may be used to transfer -//! command and data bytes to the panel. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr, - uint16_t ui16Data) -{ - uint32_t ui32Addr; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the address register to write. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Write the address. - // - HWREG(ui32Base + ui32Addr) = ui16Addr; - - // - // Determine the data register to write. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Write the data. - // - HWREG(ui32Base + ui32Addr) = ui16Data; -} - -//***************************************************************************** -// -//! Reads a status word from the display when the LCD controller is in LIDD -//! mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! -//! This function reads the 16-bit status word from the display when the LCD -//! controller is in LIDD mode. A status read occurs with the ALE signal -//! active. If the interface is configured in Hitachi mode (\b -//! LIDD_CONFIG_ASYNC_HITACHI), this operation corresponds to a command mode -//! read. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return Returns the status word read from the display panel. -// -//***************************************************************************** -uint16_t -LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to read based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Read the relevant status register. - // - return((uint16_t)HWREG(ui32Base + ui32Reg)); -} - -//***************************************************************************** -// -//! Reads a data word from the display when the LCD controller is in LIDD -//! mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! -//! This function reads the 16-bit data word from the display when the LCD -//! controller is in LIDD mode. A data read occurs with the ALE signal -//! inactive. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return Returns the status word read from the display panel. -// -//***************************************************************************** -uint16_t -LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS) -{ - uint32_t ui32Reg; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the register to read based on the CS value supplied. - // - ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Read the relevant data register. - // - return((uint16_t)HWREG(ui32Base + ui32Reg)); -} - -//***************************************************************************** -// -//! Reads a given display register when the LCD controller is in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param ui16Addr is the address of the display register to read. -//! -//! This function reads a 16-bit word from a register in the display when -//! the LCD controller is in LIDD mode and configured to use either the -//! Motorola (\b LIDD_CONFIG_SYNC_MPU68 or \b LIDD_CONFIG_ASYNC_MPU68) or -//! Intel (\b LIDD_CONFIG_SYNC_MPU80 or \b LIDD_CONFIG_ASYNC_MPU80) modes -//! that employ an external address latch. -//! -//! When configured in Hitachi mode (\b LIDD_CONFIG_ASYNC_HITACHI), this -//! function should not be used. In this case, the functions -//! LCDIDDStatusRead() and LCDIDDDataRead() may be used to read status -//! and data bytes from the panel. -//! -//! This function must not be called if the LIDD interface is currently -//! configured to expect DMA transactions. If DMA was previously used to -//! write to the panel, LCDIDDDMADisable() must be called before this function -//! can be used. -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -uint16_t -LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr) -{ - uint32_t ui32Addr; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - - // - // Determine the address register to write. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR; - - // - // Write the address. - // - HWREG(ui32Base + ui32Addr) = ui16Addr; - - // - // Determine the data register to read. - // - ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA; - - // - // Return the data read. - // - return((uint16_t)HWREG(ui32Base + ui32Addr)); -} - -//***************************************************************************** -// -//! Writes a block of data to the display using DMA when the LCD controller is -//! in LIDD mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32CS specifies the chip select to use. Valid values are 0 and 1. -//! \param pui32Data is the address of the first 16-bit word to write. This -//! address must be aligned on a 32-bit word boundary. -//! \param ui32Count is the number of 16-bit words to write. This value must -//! be a multiple of 2. -//! -//! This function writes a block of 16-bit data words to the display using -//! DMA. It is only valid when the LCD controller is in LIDD mode. -//! Completion of the DMA transfer is signaled by the \b -//! LCD_INT_DMA_DONE interrupt. -//! -//! This function enables DMA mode prior to starting the transfer. The -//! caller is responsible for ensuring that any earlier DMA transfer has -//! completed before initiating another transfer. -//! -//! During the time that DMA is enabled, none of the other LCD LIDD data -//! transfer functions may be called. When the DMA transfer is complete and -//! the application wishes to use the CPU to communicate with the display, -//! LCDIDDDMADisable() must be called to disable DMA access prior to calling -//! LCDIDDCommandWrite(), LCDIDDDataWrite(), LCDIDDStatusRead(), -//! LCDIDDIndexedWrite(), LCDIDDIndexedRead() or LCDIDDDataRead(). -//! -//! \note CS1 is not available when operating in Sync MPU68 or Sync MPU80 -//! modes. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, const uint32_t *pui32Data, - uint32_t ui32Count) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32CS == 0) || (ui32CS == 1)); - ASSERT(!((uint32_t)pui32Data & 3)); - ASSERT(!(ui32Count & 1)); - - // - // Make sure DMA is disabled so that enabling it triggers this new - // transfer. - // - HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN; - - // - // Set up the transfer. Note that the ceiling register must contain the - // address of the last word which contains data we want transfered and NOT - // the first location after the data we want written. - // - HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Data; - HWREG(ui32Base + LCD_O_DMACAFB0) = ((uint32_t)pui32Data + - (ui32Count * 2) - 4); - - // - // Tell the controller which CS to use for the DMA transaction. - // - if(!ui32CS) - { - // - // Use CS0. - // - HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMACS; - } - else - { - // - // Use CS1. - // - HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMACS; - } - - // - // Enable the DMA engine and start the transaction. - // - HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMAEN; -} - -//***************************************************************************** -// -//! Sets the LCD controller interface timing when in raster mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param ui32Config specifies properties of the raster interface and the -//! attached display panel. -//! \param ui8PalLoadDelay specifies the number of system clocks to wait -//! between each 16 halfword (16-bit) burst when loading the palette from -//! SRAM into the internal palette RAM of the controller. -//! -//! This function configures the basic operating mode of the raster interface -//! and specifies the type of panel that the controller is to drive. -//! -//! The \e ui32Config parameter must be defined as one of the following to -//! select the required target panel type and output pixel format: -//! -//! - \b RASTER_FMT_ACTIVE_24BPP_PACKED selects an active matrix display -//! and uses a packed 24-bit per pixel packet frame buffer where 4 pixels -//! are described within 3 consecutive 32-bit words. -//! - \b RASTER_FMT_ACTIVE_24BPP_UNPACKED selects an active matrix display -//! and uses an unpacked 24-bit per pixel packet frame buffer where each -//! 32-bit word contains a single pixel and 8 bits of padding. -//! - \b RASTER_FMT_ACTIVE_16BPP selects an active matrix display -//! and uses a 16-bit per pixel frame buffer with 2 pixels in each 32-bit -//! word. -//! - \b RASTER_FMT_ACTIVE_PALETTIZED_12BIT selects an active matrix display -//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup. Output color -//! data is described in 12-bit format using bits 11:0 of the data bus. The -//! frame buffer pixel format is defined by the value passed in the \e ui32Type -//! parameter to LCDRasterPaletteSet(). -//! - \b RASTER_FMT_ACTIVE_PALETTIZED_16BIT selects an active matrix display -//! and uses a 1, 2, 4 or 8bpp frame buffer with palette lookup. Output color -//! data is described in 16-bit 5:6:5 format. The frame buffer pixel format is -//! defined by the value passed in the \e ui32Type parameter to -//! LCDRasterPaletteSet(). -//! - \b RASTER_FMT_PASSIVE_MONO_4PIX selects a monochrome, passive matrix -//! display that outputs 4 pixels on each pixel clock. -//! - \b RASTER_FMT_PASSIVE_MONO_8PIX selects a monochrome, passive matrix -//! display that outputs 8 pixels on each pixel clock. -//! - \b RASTER_FMT_PASSIVE_COLOR_12BIT selects a passive matrix display -//! and uses a 12bpp frame buffer. The palette is bypassed and 12-bit pixel -//! data is sent to the grayscaler for the display. -//! - \b RASTER_FMT_PASSIVE_COLOR_16BIT selects a passive matrix display -//! and uses a 16bpp frame buffer with pixels in 5:6:5 format. Only the 4 -//! most significant bits of each color component are sent to the grayscaler -//! for the display. -//! -//! Additionally, the following flags may be ORed into \e ui32Config: -//! -//! - \b RASTER_ACTVID_DURING_BLANK sets Actvid to toggle during vertical -//! blanking. -//! - \b RASTER_NIBBLE_MODE_ENABLED enables nibble mode. This parameter works -//! with \b RASTER_READ_ORDER_REVERSED to determine how 1, 2 and 4bpp pixels -//! are extracted from words read from the frame buffer. If specified, words -//! read from the frame buffer are byte swapped prior to individual pixels -//! being parsed from them. -//! - \b RASTER_LOAD_DATA_ONLY tells the controller to read only pixel data -//! from the frame buffer and to use the last palette read. No palette load -//! is performed. -//! - \b RASTER_LOAD_PALETTE_ONLY tells the controller to read only the palette -//! data from the frame buffer. -//! - \b RASTER_READ_ORDER_REVERSED when using 1, 2, 4 and 8bpp frame buffers, -//! this option reverses the order in which frame buffer words are parsed. -//! When this option is specified, the leftmost pixel in a word is taken from -//! the most significant bits. When absent, the leftmost pixel is parsed from -//! the least significant bits. -//! -//! If the LCD controller's raster engine is enabled when this function is -//! called, it is disabled as a result of the call. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint8_t ui8PalLoadDelay) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Config & ~(RASTER_FMT_ACTIVE_24BPP_PACKED | - RASTER_FMT_ACTIVE_24BPP_UNPACKED | - RASTER_FMT_ACTIVE_PALETTIZED_12BIT | - RASTER_FMT_ACTIVE_PALETTIZED_16BIT | - RASTER_FMT_PASSIVE_MONO_4PIX | - RASTER_FMT_PASSIVE_MONO_8PIX | - RASTER_FMT_PASSIVE_PALETTIZED | - RASTER_FMT_PASSIVE_COLOR_12BIT | - RASTER_FMT_PASSIVE_COLOR_16BIT | - RASTER_ACTVID_DURING_BLANK | - RASTER_NIBBLE_MODE_ENABLED | - RASTER_LOAD_DATA_ONLY | - RASTER_LOAD_PALETTE_ONLY | - RASTER_READ_ORDER_REVERSED))); - - // - // Write the raster control register. - // - HWREG(ui32Base + LCD_O_RASTRCTL) = (ui32Config | - ((uint32_t)ui8PalLoadDelay << - LCD_RASTRCTL_REQDLY_S)); -} - -//***************************************************************************** -// -//! Sets the LCD controller interface timing when in raster mode. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param pTiming points to a structure containing the desired timing -//! parameters. -//! -//! This function is used in raster mode to set the panel size and sync timing -//! parameters. -//! -//! For a definition of the timing parameters required, see the definition of -//! tLCDRasterTiming. -//! -//! \return None -// -//***************************************************************************** -void -LCDRasterTimingSet(uint32_t ui32Base, const tLCDRasterTiming *pTiming) -{ - uint32_t ui32T0, ui32T1, ui32T2; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(pTiming); - ASSERT(!(pTiming->ui32Flags & ~(RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK | - RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK | - RASTER_TIMING_SYNCS_ON_RISING_PIXCLK | - RASTER_TIMING_ACTIVE_LOW_OE | - RASTER_TIMING_ACTIVE_LOW_PIXCLK | - RASTER_TIMING_ACTIVE_LOW_HSYNC | - RASTER_TIMING_ACTIVE_LOW_VSYNC))); - ASSERT(pTiming->ui16PanelWidth && (pTiming->ui16PanelWidth <= 2048) && - ((pTiming->ui16PanelWidth % 16) == 0)); - ASSERT(pTiming->ui16PanelHeight && (pTiming->ui16PanelHeight <= 2048)); - ASSERT(pTiming->ui16HFrontPorch && (pTiming->ui16HFrontPorch <= 1024)); - ASSERT(pTiming->ui16HBackPorch && (pTiming->ui16HBackPorch <= 1024)); - ASSERT(pTiming->ui16HSyncWidth && (pTiming->ui16HSyncWidth <= 1024)); - ASSERT(pTiming->ui8VSyncWidth && (pTiming->ui8VSyncWidth <= 64)); - - // - // Construct the values we need for the three raster timing registers. - // - ui32T0 = ((uint32_t)((pTiming->ui16HBackPorch - 1) & 0xFF) << - LCD_RASTRTIM0_HBP_S) | - ((uint32_t)((pTiming->ui16HFrontPorch - 1) & 0xFF) << - LCD_RASTRTIM0_HFP_S) | - ((uint32_t)((pTiming->ui16HSyncWidth - 1) & 0x3F) << - LCD_RASTRTIM0_HSW_S) | - (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x3F0) >> 4) << - LCD_RASTRTIM0_PPL_S) | - (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x400) >> 10) << - LCD_RASTRTIM0_MSBPPL_S); - ui32T1 = ((uint32_t)pTiming->ui8VBackPorch << LCD_RASTRTIM1_VBP_S) | - ((uint32_t)pTiming->ui8VFrontPorch << LCD_RASTRTIM1_VFP_S) | - ((uint32_t)((pTiming->ui8VSyncWidth - 1) & 0x3F) << - LCD_RASTRTIM1_VSW_S) | - ((uint32_t)(pTiming->ui16PanelHeight - 1) & 0x3FF) << - LCD_RASTRTIM1_LPP_S; - ui32T2 = pTiming->ui32Flags | - ((((pTiming->ui16HSyncWidth - 1) & 0x3C0) >> 6) << - LCD_RASTRTIM2_HSW_S) | - ((((pTiming->ui16PanelHeight - 1) & 0x400) >> 10) << - LCD_RASTRTIM2_MSBLPP_S) | - ((((pTiming->ui16HBackPorch - 1) & 0x300) >> 8) << - LCD_RASTRTIM2_MSBHBP_S) | - ((((pTiming->ui16HFrontPorch - 1) & 0x300) >> 8) << - LCD_RASTRTIM2_MSBHFP_S) | - (pTiming->ui8ACBiasLineCount << LCD_RASTRTIM2_ACBF_S); - - // - // Write the timing registers, taking care to preserve any existing value - // in the AC Bias interrupt field of RASTRTIM2. - // - HWREG(ui32Base + LCD_O_RASTRTIM0) = ui32T0; - HWREG(ui32Base + LCD_O_RASTRTIM1) = ui32T1; - HWREG(ui32Base + LCD_O_RASTRTIM2) = (HWREG(ui32Base + LCD_O_RASTRTIM2) & - LCD_RASTRTIM2_ACBI_M) | ui32T2; -} - -//***************************************************************************** -// -//! Sets the number of AC bias pin transitions per interrupt. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8Count is the number of AC bias pin transitions to count before -//! the AC bias count interrupt is asserted. Valid values are from 0 to 15. -//! -//! This function is used to set the number of AC bias transitions between -//! each AC bias count interrupt (\b LCD_INT_AC_BIAS_CNT). If \e ui8Count is -//! 0, no AC bias count interrupt is generated. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count) -{ - uint32_t ui32Val; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(ui8Count < 16); - - // - // Get the existing raster timing 2 register value and mask in the new - // AC Bias interrupt count. - // - ui32Val = HWREG(ui32Base + LCD_O_RASTRTIM2); - ui32Val &= ~LCD_RASTRTIM2_ACBI_M; - ui32Val |= ((ui8Count << LCD_RASTRTIM2_ACBI_S) & LCD_RASTRTIM2_ACBI_M); - - // - // Write the new value back to the register. - // - HWREG(ui32Base + LCD_O_RASTRTIM2) = ui32Val; -} - -//***************************************************************************** -// -//! Enables the raster output. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function enables the LCD controller raster output and starts -//! displaying the content of the current frame buffer on the attached panel. -//! Prior to enabling the raster output, LCDModeSet(), LCDRasterConfigSet(), -//! LCDDMAConfigSet(), LCDRasterTimingSet(), LCDRasterPaletteSet() and -//! LCDRasterFrameBufferSet() must have been called. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterEnable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Reset the module prior to starting the raster. This is required to - // ensure correct operation of the raster engine. - // - LCDClockReset(ui32Base, LCD_CLOCK_MAIN); - - // - // Enable the raster engine. - // - HWREG(ui32Base + LCD_O_RASTRCTL) |= LCD_RASTRCTL_LCDEN; -} - -//***************************************************************************** -// -//! Determines whether or not the raster output is currently enabled. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function may be used to query whether or not the raster output is -//! currently enabled. -//! -//! \return Returns \b true if the raster is enabled or \b false if it is -//! disabled. -// -//***************************************************************************** -bool -LCDRasterEnabled(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Return the current raster engine status. - // - return((HWREG(ui32Base + LCD_O_RASTRCTL) & LCD_RASTRCTL_LCDEN) ? - true : false); -} - -//***************************************************************************** -// -//! Disables the raster output. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function disables the LCD controller raster output and stops driving -//! the attached display. -//! -//! \note Once disabled, the raster engine continues to scan data until the -//! end of the current frame. If the display is to be re-enabled, wait until -//! after the final \b LCD_INT_RASTER_FRAME_DONE has been received, indicating -//! that the raster engine has stopped. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterDisable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable the raster engine. - // - HWREG(ui32Base + LCD_O_RASTRCTL) &= ~LCD_RASTRCTL_LCDEN; -} - -//***************************************************************************** -// -//! Sets the position and size of the subpanel on the raster display. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Flags may be either \b LCD_SUBPANEL_AT_TOP to show frame buffer -//! image data in the top portion of the display and default color in the -//! bottom portion, or \b LCD_SUBPANEL_AT_BOTTOM to show image data at the -//! bottom of the display and default color at the top. -//! \param ui32BottomLines defines the number of lines comprising the bottom -//! portion of the display. If \b LCD_SUBPANEL_AT_TOP is set in \e ui32Flags, -//! these lines contain the default pixel color when the subpanel is -//! enabled, otherwise they contain image data. -//! \param ui32DefaultPixel is the 24-bit RGB color to show in the portion of -//! the display not configured to show image data. -//! -//! The LCD controller provides a feature that allows a portion of the display -//! to be filled with a default color rather than image data from the frame -//! buffer. This feature reduces SRAM bandwidth requirements because no data -//! is fetched for lines containing the default color. This feature is only -//! available when the LCD controller is in raster mode and configured to drive -//! an active matrix display. -//! -//! The subpanel area containing image data from the frame buffer may be -//! positioned either at the top or bottom of the display as controlled by -//! the value of \e ui32Flags. The height of the bottom portion of the display -//! is defined by \e ui32BottomLines. -//! -//! When a subpanel is configured, the application must also reconfigure the -//! frame buffer to ensure that it contains the correct number of lines for -//! the subpanel size in use. This configuration can be achieved by calling -//! LCDRasterFrameBufferSet() with the \e ui32NumBytes parameter set -//! appropriately to describe the required number of active video lines in -//! the subpanel area. -//! -//! The subpanel display mode is not enabled using this function. To enable -//! the subpanel once it has been configured, call LCDRasterSubPanelEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags, - uint32_t ui32BottomLines, uint32_t ui32DefaultPixel) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT((ui32Flags == LCD_SUBPANEL_AT_TOP) || - (ui32Flags == LCD_SUBPANEL_AT_BOTTOM)); - ASSERT(ui32BottomLines && (ui32BottomLines <= 2048)); - - // - // Adjust the line count into the 0-2047 range. - // - ui32BottomLines--; - - // - // Set the first subpanel configuration register, taking care to leave the - // subpanel enabled if it already was. - // - HWREG(ui32Base + LCD_O_RASTRSUBP1) = (HWREG(ui32Base + LCD_O_RASTRSUBP1) & - LCD_RASTRSUBP1_SPEN) | ui32Flags | - ((ui32DefaultPixel & 0xFFFF) << - LCD_RASTRSUBP1_DPDLSB_S) | - ((ui32BottomLines << - LCD_RASTRSUBP1_LPPT_S) & - LCD_RASTRSUBP1_LPPT_M); - - // - // Set the second subpanel configuration register. - // - HWREG(ui32Base + LCD_O_RASTRSUBP2) = - ((ui32DefaultPixel >> 16) & LCD_RASTRSUBP2_DPDMSB_M) | - (((ui32BottomLines >> LCD_RASTRSUBP1_LPPT_S) & 1) << 8); -} - -//***************************************************************************** -// -//! Enables subpanel display mode. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function enables subpanel display mode and displays a default color -//! rather than image data in the number of lines and at the position specified -//! by a previous call to LCDRasterSubPanelConfigSet(). Prior to calling -//! LCDRasterSubPanelEnable(), the frame buffer should have been reconfigured -//! to match the desired subpanel size using a call to -//! LCDRasterFrameBufferSet(). -//! -//! Subpanel display is only possible when the LCD controller is in raster -//! mode and is configured to drive an active matrix display. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterSubPanelEnable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Enable the subpanel. - // - HWREG(ui32Base + LCD_O_RASTRSUBP1) |= LCD_RASTRSUBP1_SPEN; -} - -//***************************************************************************** -// -//! Disables subpanel display mode. -//! -//! \param ui32Base is the base address of the controller. -//! -//! This function disables subpanel display mode and reverts to showing the -//! entire frame buffer image on the display. After the subpanel is disabled, -//! the frame buffer size must be reconfigured to match the full dimensions of -//! the display area by calling LCDRasterFrameBufferSet() with an appropriate -//! value for the \e ui32NumBytes parameter. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterSubPanelDisable(uint32_t ui32Base) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable the subpanel. - // - HWREG(ui32Base + LCD_O_RASTRSUBP1) &= ~LCD_RASTRSUBP1_SPEN; -} - -//***************************************************************************** -// -//! Configures the LCD controller's internal DMA engine. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Config provides flags defining the desired DMA parameters. -//! -//! This function is used to configure the DMA engine within the LCD -//! controller. This engine is responsible for performing bulk data transfers -//! to the display when in LIDD mode or for transferring palette and pixel data -//! from SRAM to the display panel when in raster mode. -//! -//! The \e ui32Config parameter is a logical OR of various flags. It must -//! contain one value from each of the following groups. -//! -//! The first group of flags set the number of words that have to be in the -//! FIFO before it signals that it is ready: -//! -//! - \b LCD_DMA_FIFORDY_8_WORDS -//! - \b LCD_DMA_FIFORDY_16_WORDS -//! - \b LCD_DMA_FIFORDY_32_WORDS -//! - \b LCD_DMA_FIFORDY_64_WORDS -//! - \b LCD_DMA_FIFORDY_128_WORDS -//! - \b LCD_DMA_FIFORDY_256_WORDS -//! - \b LCD_DMA_FIFORDY_512_WORDS -//! -//! The second group of flags set the number of 32-bit words in each DMA burst -//! transfer: -//! -//! - \b LCD_DMA_BURST_1 -//! - \b LCD_DMA_BURST_2 -//! - \b LCD_DMA_BURST_4 -//! - \b LCD_DMA_BURST_8 -//! - \b LCD_DMA_BURST_16 -//! -//! The final group of flags set internal byte lane controls and allow byte -//! swapping within the DMA engine. The label represents the output byte order -//! for an input 32-bit word ordered ``0123''. -//! -//! - \b LCD_DMA_BYTE_ORDER_0123 -//! - \b LCD_DMA_BYTE_ORDER_1023 -//! - \b LCD_DMA_BYTE_ORDER_3210 -//! - \b LCD_DMA_BYTE_ORDER_2301 -//! -//! Additionally, \b LCD_DMA_PING_PONG may be specified. This flag configures -//! the controller to operate in double-buffered mode. When data is scanned -//! out from the first frame buffer, the DMA engine immediately moves to -//! the second frame buffer and scans from there before moving back to the -//! first. If this flag is clear, the DMA engine uses a single frame buffer, -//! restarting the scan from the beginning of the buffer each time it completes -//! a frame. -//! -//! \note DMA burst size \b LCD_DMA_BURST_16 should be set when using frame -//! buffers in external, EPI-connected memory. Using a smaller burst size in -//! this case is likely to result in occasional FIFO underflows and associated -//! display glitches. -//! -//! \return None. -// -//***************************************************************************** -void -LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32Config & ~(LCD_DMACTL_FIFORDY_M | LCD_DMACTL_BURSTSZ_M | - LCD_DMACTL_BYTESWAP | LCD_DMACTL_BIGDEND | - LCD_DMACTL_FMODE))); - - // - // Write the DMA control register. - // - HWREG(ui32Base + LCD_O_DMACTL) = ui32Config; -} - -//***************************************************************************** -// -//! Initializes the color palette in a frame buffer. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32Type specifies the type of pixel data to be held in the frame -//! buffer and also the format of the source color values passed. -//! \param pui32Addr points to the start of the frame buffer into which the -//! palette information is to be written. -//! \param pui32SrcColors points to the first color value that is to be -//! written into the frame buffer palette. -//! \param ui32Start specifies the index of the first color in the palette -//! to update. -//! \param ui32Count specifies the number of source colors to be copied into -//! the frame buffer palette. -//! -//! This function is used to initialize the color palette stored at the -//! beginning of a frame buffer. It writes the relevant pixel type into the -//! first entry of the frame buffer and copies the requested number of colors -//! from a source buffer into the palette starting at the required index, -//! optionally converting them from 24-bit color format into the 12-bit format -//! used by the LCD controller. -//! -//! \e ui32Type must be set to one of the following values to indicate the -//! type of frame buffer for which the palette is being initialized: -//! -//! - \b LCD_PALETTE_TYPE_1BPP indicates a 1 bit per pixel -//! (monochrome) frame buffer. This format requires a 2 entry palette. -//! - \b LCD_PALETTE_TYPE_2BPP indicates a 2 bit per pixel frame -//! buffer. This format requires a 4 entry palette. -//! - \b LCD_PALETTE_TYPE_4BPP indicates a 4 bit per pixel frame -//! buffer. This format requires a 4 entry palette. -//! - \b LCD_PALETTE_TYPE_8BPP indicates an 8 bit per pixel frame -//! buffer. This format requires a 256 entry palette. -//! - \b LCD_PALETTE_TYPE_DIRECT indicates a direct color (12, 16 or -//! 24 bit per pixel). The color palette is not used in these modes, but the -//! frame buffer type must still be initialized to ensure that the hardware -//! uses the correct pixel type. When this value is used, the format of the -//! pixels in the frame buffer is defined by the \e ui32Config parameter -//! previously passed to LCDRasterConfigSet(). -//! -//! Optionally, the \b LCD_PALETTE_SRC_24BIT flag may be ORed into \e ui32Type -//! to indicate that the supplied colors in the \e pui32SrcColors array are in -//! the 24-bit format as used by the TivaWare Graphics Library with one color -//! stored in each 32-bit word. In this case, the colors read from the source -//! array are converted to the 12-bit format used by the LCD controller before -//! being written into the frame buffer palette. -//! -//! If \b LCD_PALETTE_SRC_24BIT is not present, it is assumed that the -//! \e pui32SrcColors array contains 12-bit colors in the format required by -//! the LCD controller with 2 colors stored in each 32-bit word. In this case, -//! the values are copied directly into the frame buffer palette without any -//! reformatting. -//! -//! \return None. -// -//***************************************************************************** -void -LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, uint32_t *pui32Addr, - const uint32_t *pui32SrcColors, uint32_t ui32Start, - uint32_t ui32Count) -{ - uint16_t *pui16Pal; - uint16_t *pui16Src; - uint32_t ui32Loop; - - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(ui32Start < 256); - ASSERT((ui32Start + ui32Count) <= 256); - ASSERT(pui32Addr); - ASSERT((pui32SrcColors) || (ui32Count == 0)); - ASSERT(!(ui32Type & ~(LCD_PALETTE_SRC_24BIT | LCD_PALETTE_TYPE_DIRECT | - LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_4BPP | - LCD_PALETTE_TYPE_2BPP | LCD_PALETTE_TYPE_1BPP))); - - // - // Get a pointer to the start of the palette. - // - pui16Pal = (uint16_t *)pui32Addr; - - // - // Are we converting the palette color format? - // - if(ui32Type & LCD_PALETTE_SRC_24BIT) - { - // - // Yes - loop through each of the supplied 24-bit colors converting - // and storing each. - // - ui32Loop = 0; - while(ui32Count) - { - pui16Pal[ui32Start + ui32Loop] = - PAL_FROM_RGB(pui32SrcColors[ui32Loop]); - ui32Loop++; - ui32Count--; - } - } - else - { - // - // No - loop through the supplied 12-bit colors storing each. - // - - pui16Src = (uint16_t *)pui32SrcColors; - while(ui32Count) - { - pui16Pal[ui32Start] = pui16Src[ui32Start]; - ui32Start++; - ui32Count--; - } - } - - // - // Write the pixel type into the first palette entry. - // - pui16Pal[0] &= ~(LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_DIRECT); - pui16Pal[0] |= (ui32Type & ~LCD_PALETTE_SRC_24BIT); -} - -//***************************************************************************** -// -//! Sets the LCD controller frame buffer start address and size in raster mode. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui8Buffer specifies which frame buffer to configure. Valid values -//! are 0 and 1. -//! \param pui32Addr points to the first byte of the frame buffer. This -//! pointer must be aligned on a 32-bit (word) boundary. -//! \param ui32NumBytes specifies the size of the frame buffer in bytes. This -//! value must be a multiple of 4. -//! -//! This function is used to configure the position and size of one of the -//! two supported frame buffers while in raster mode. The second frame buffer -//! (configured when ui8Buffer is set to 1) is only used if the controller -//! is set to operate in ping-pong mode (by specifying the \b LCD_DMA_PING_PONG -//! configuration flag on a call to LCDDMAConfigSet()). -//! -//! The format of the frame buffer depends on the image type in use and -//! the current raster configuration settings. If \b RASTER_LOAD_DATA_ONLY -//! was specified in a previous call to LCDRasterConfigSet(), the frame buffer -//! contains only packed pixel data in the required bit depth and format. -//! In other cases, the frame buffer comprises a palette of either 8 or 128 -//! 32-bit words followed by the packed pixel data. The palette size is 8 -//! words (16 16-bit entries) for all pixel formats other than 8bpp which -//! uses a palette of 128 words (256 16-bit entries). Note that the 8 word -//! palette is still present even for 12, 16 and 24-bit formats, which do not -//! use the lookup table. -//! -//! The frame buffer size, specified using the \e ui32NumBytes parameter, must -//! be the palette size (if any) plus the size of the image bitmap required -//! for the currently configured display resolution. -//! -//! \e ui32NumBytes = (Palette Size) + ((Width * Height) * BPP) / 8) -//! -//! If \b RASTER_LOAD_DATA_ONLY is not specified, frame buffers passed to this -//! function must be initialized using a call to LCDRasterPaletteSet() prior to -//! enabling the raster output. If this is not done, the pixel format -//! identifier and color table required by the hardware is not present -//! and the results are unpredictable. -//! -//! \return None. -//***************************************************************************** -void -LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer, - uint32_t *pui32Addr, uint32_t ui32NumBytes) -{ - // - // Sanity check parameters. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!((uint32_t)pui32Addr & 3)); - ASSERT(!(ui32NumBytes & 3)); - ASSERT(ui8Buffer < 2); - - // - // Are we setting the values for frame buffer 0? - // - if(!ui8Buffer) - { - // - // Yes - set the registers for frame buffer 0. - // - HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Addr; - HWREG(ui32Base + LCD_O_DMACAFB0) = (uint32_t)pui32Addr + - ui32NumBytes - 4; - } - else - { - // - // No - set the registers for frame buffer 1. - // - HWREG(ui32Base + LCD_O_DMABAFB1) = (uint32_t)pui32Addr; - HWREG(ui32Base + LCD_O_DMACAFB1) = (uint32_t)pui32Addr + - ui32NumBytes - 4; - } -} - -//***************************************************************************** -// -//! Enables individual LCD controller interrupt sources. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated LCD controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | - LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | - LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | - LCD_INT_RASTER_FRAME_DONE))); - - // - // Enable the interrupt sources by setting the appropriate bits in the - // mask register. - // - HWREG(ui32Base + LCD_O_IM) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual LCD controller interrupt sources. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated LCD controller interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | - LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | - LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | - LCD_INT_RASTER_FRAME_DONE))); - - // - // Disable the interrupt sources by clearing the appropriate bits in the - // mask register. - // - HWREG(ui32Base + LCD_O_IENC) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current LCD controller interrupt status. -//! -//! \param ui32Base is the base address of the controller. -//! \param bMasked is false if the raw interrupt status is required and true -//! if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the LCD controller. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status as the logical OR of any of -//! the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -// -//***************************************************************************** -uint32_t -LCDIntStatus(uint32_t ui32Base, bool bMasked) -{ - ASSERT(ui32Base == LCD0_BASE); - - // - // Were we asked for the masked or raw interrupt status? - // - if(bMasked) - { - // - // Return the masked interrupt status. - // - return(HWREG(ui32Base + LCD_O_MISCLR)); - } - else - { - // - // Return the raw interrupts status. - // - return(HWREG(ui32Base + LCD_O_RISSET)); - } -} - -//***************************************************************************** -// -//! Clears LCD controller interrupt sources. -//! -//! \param ui32Base is the base address of the controller. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified LCD controller interrupt sources are cleared so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b LCD_INT_DMA_DONE - indicates that a LIDD DMA transfer is complete. -//! - \b LCD_INT_RASTER_FRAME_DONE - indicates that a raster-mode frame is -//! complete. -//! - \b LCD_INT_SYNC_LOST - indicates that frame synchronization was lost. -//! - \b LCD_INT_AC_BIAS_CNT - indicates that that AC bias transition counter -//! has decremented to zero and is is valid for passive matrix panels only. -//! The counter, set by a call to LCDRasterACBiasIntCountSet(), is reloaded -//! but remains disabled until this interrupt is cleared. -//! - \b LCD_INT_UNDERFLOW - indicates that a data underflow occurred. The -//! internal FIFO was empty when the output logic attempted to read data to -//! send to the display. -//! - \b LCD_INT_PAL_LOAD - indicates that the color palette has been loaded. -//! - \b LCD_INT_EOF0 - indicates that the raw End-of-Frame 0 has been -//! signaled. -//! - \b LCD_INT_EOF2 - indicates that the raw End-of-Frame 1 has been -//! signaled. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - ASSERT(ui32Base == LCD0_BASE); - ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST | - LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW | - LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 | - LCD_INT_RASTER_FRAME_DONE))); - - // - // Clear the requested interrupts. - // - HWREG(ui32Base + LCD_O_MISCLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the LCD controller module. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! \param pfnHandler is a pointer to the function to be called when the LCD -//! controller interrupt occurs. -//! -//! This function registers the handler to be called when the LCD controller -//! module interrupt occurs. -//! -//! \note This function need not be called if the appropriate interrupt vector -//! is statically linked into the vector table in the application startup code. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == LCD0_BASE); - ASSERT(pfnHandler); - - // - // Register the interrupt handler. - // - IntRegister(INT_LCD0_TM4C129, pfnHandler); - - // - // Enable the interrupt in the interrupt controller. - // - IntEnable(INT_LCD0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the LCD controller module. -//! -//! \param ui32Base specifies the LCD controller module base address. -//! -//! This function unregisters the interrupt handler and disables the global LCD -//! controller interrupt in the interrupt controller. -//! -//! \note This function need not be called if the appropriate interrupt vector -//! is statically linked into the vector table in the application startup code. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -LCDIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == LCD0_BASE); - - // - // Disable the interrupt in the interrupt controller. - // - IntDisable(INT_LCD0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_LCD0_TM4C129); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/lcd.h b/bsp/tm4c129x-dk/libraries/driverlib/lcd.h deleted file mode 100644 index 766cf94361..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/lcd.h +++ /dev/null @@ -1,487 +0,0 @@ -//***************************************************************************** -// -// lcd.h - Defines and Macros for the LCD Controller module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_LCD_H__ -#define __DRIVERLIB_LCD_H__ - -//***************************************************************************** -// -//! \addtogroup lcd_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! This macro can be used to convert a 24-bit RGB color value as used by the -//! TivaWare Graphics Library into a 12-bit LCD controller color palette -//! entry. -// -//***************************************************************************** -#define PAL_FROM_RGB(ui32RGBColor) (((ui32RGBColor & 0xF0) >> 4) | \ - ((ui32RGBColor & 0xF000) >> 8) | \ - ((ui32RGBColor & 0xF00000) >> 12)) - -//***************************************************************************** -// -//! This macro can be used to convert from time in microseconds to periods of -//! the supplied clock in Hertz as required when setting up the LIDD and raster -//! timing structures. The calculation will round such that the number of -//! cycles returned represents no longer a time than specified in the -//! ui32Time_uS parameter. Values of ui32Time_uS less than or equal to -//! 4294967uS (4.29 seconds) are supported by the macro. Larger values will -//! cause arithmetic overflow and yield incorrect values. It is further -//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). -// -//***************************************************************************** -#define CYCLES_FROM_TIME_US(ui32ClockFreq, ui32Time_uS) \ - (((ui32Time_uS) == 0) ? 0 : \ - (((ui32ClockFreq) / 1000000) * ((((ui32Time_uS) * 1000) - 1) / 1000)) + 1) - -//***************************************************************************** -// -//! This macro can be used to convert from time in nanoseconds to periods of -//! the supplied clock in Hertz as required when setting up the LIDD and raster -//! timing structures. The calculation will round such that the number of -//! cycles returned represents no longer a time than specified in the -//! ui32Time_nS parameter. Values of ui32Time_nS less than or equal to -//! 35791394 (35.79 milliseconds) are supported by the macro. Larger values -//! will cause arithmetic overflow and yield incorrect values. It is further -//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). -// -//***************************************************************************** -#define CYCLES_FROM_TIME_NS(ui32ClockFreq, ui32Time_nS) \ - (((ui32Time_nS) == 0) ? 0 : \ - ((((((ui32ClockFreq) / 1000000) * ((ui32Time_nS) - 1)) / 1000)) + 1)) - -//***************************************************************************** -// -//! A structure containing timing parameters for the LIDD (LCD Interface -//! Display Driver) interface. This is used with the LCDIDDTimingSet function. -// -//***************************************************************************** -typedef struct -{ - // - //! Write Strobe Set-Up cycles. When performing a write access, this - //! field defines the number of MCLK cycles that Data Bus/Pad Output - //! Enable, ALE, the Direction bit, and Chip Select have to be ready before - //! the Write Strobe is asserted. Valid values are from 0 to 31. - // - uint8_t ui8WSSetup; - - // - //! Write Strobe Duration cycles. Field value defines the number of MCLK - //! cycles for which the Write Strobe is held active when performing a - //! write access. Valid values are from 1 to 63. - // - uint8_t ui8WSDuration; - - // - //! Write Strobe Hold cycles. Field value defines the number of MCLK - //! cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit, - //! and Chip Select are held after the Write Strobe is deasserted when - //! performing a write access. Valid values are from 1 to 15. - // - uint8_t ui8WSHold; - - // - //! Read Strobe Set-Up cycles. When performing a read access, this field - //! defines the number of MCLK cycles that Data Bus/Pad Output Enable, ALE, - //! the Direction bit, and Chip Select have to be ready before the Read - //! Strobe is asserted. Valid values are from 0 to 31. - // - uint8_t ui8RSSetup; - - // - //! Read Strobe Duration cycles. Field value defines the number of MCLK - //! cycles for which the Read Strobe is held active when performing a read - //! access. Valid values are from 1 to 63. - // - uint8_t ui8RSDuration; - - // - //! Read Strobe Hold cycles. Field value defines the number of MCLK cycles - //! for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip - //! Select are held after the Read Strobe is deasserted when performing a - //! read access. Valid values are from 1 to 15. - // - uint8_t ui8RSHold; - - // - //! Field value defines the number of MCLK cycles between the end of one - //! device access and the start of another device access using the same - //! Chip Select unless the two accesses are both Reads. In this case, - //! this delay is not incurred. Valid vales are from 1 to 4. - // - uint8_t ui8DelayCycles; -} -tLCDIDDTiming; - -// -// Values which can be ORed together within the ui32Flags field of the -// tLCDRasterTiming structure. -// -#define RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK \ - 0x00000000 -#define RASTER_TIMING_SYNCS_ON_RISING_PIXCLK \ - 0x02000000 -#define RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK \ - 0x03000000 -#define RASTER_TIMING_ACTIVE_HIGH_OE \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_OE \ - 0x00800000 -#define RASTER_TIMING_ACTIVE_HIGH_PIXCLK \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_PIXCLK \ - 0x00400000 -#define RASTER_TIMING_ACTIVE_HIGH_HSYNC \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_HSYNC \ - 0x00200000 -#define RASTER_TIMING_ACTIVE_HIGH_VSYNC \ - 0x00000000 -#define RASTER_TIMING_ACTIVE_LOW_VSYNC \ - 0x00100000 - -// -//! A structure containing timing parameters for the raster interface. This is -//! used with the LCDRasterTimingSet function. -// -typedef struct -{ - // - //! Flags configuring the polarity and active edges of the various signals - //! in the raster interface. This field is comprised of a logical OR of - //! the labels with prefix ``RASTER_TIMING_''. - // - uint32_t ui32Flags; - - // - //! The number of pixels contained within each line on the LCD display. - //! Valid values are multiple of 16 less than or equal to 2048. - // - uint16_t ui16PanelWidth; - - // - //! The number of lines on the LCD display. Valid values are from 1 to - //! 2048. - // - uint16_t ui16PanelHeight; - - // - //! A value from 1 to 1024 that specifies the number of pixel clock periods - //! to add to the end of each line after active video has ended. - // - uint16_t ui16HFrontPorch; - - // - //! A value from 1 to 1024 that specifies the number of pixel clock periods - //! to add to the beginning of a line before active video is asserted. - // - uint16_t ui16HBackPorch; - - // - //! A value from 1 to 1024 that specifies the number of pixel clock periods - //! to pulse the line clock at the end of each line. - // - uint16_t ui16HSyncWidth; - - // - //! A value from 0 to 255 that specifies the number of line clock periods - //! to add to the end of each frame after the last active line. - // - uint8_t ui8VFrontPorch; - - // - //! A value from 0 to 255 that specifies the number of line clock periods - //! to add to the beginning of a frame before the first active line is - //! output to the display. - // - uint8_t ui8VBackPorch; - - // - //! In active mode, a value from 1 to 64 that specifies the number of - //! line clock periods to set the lcd_fp pin active at the end of each - //! frame after the vertical front porch period elapses. The number of - //! The frame clock is used as the VSYNC signal in active mode. - //! - //! In passive mode, a value from 1 to 64 that specifies the number of - //! extra line clock periods to insert after the vertical front porch - //! period has elapsed. Note that the width of lcd_fp is not affected by - //! this value in passive mode. - // - uint8_t ui8VSyncWidth; - - // - //! A value from 0 to 255 that specifies the number of line clocks to - //! count before transitioning the AC Bias pin. This pin is used to - //! periodically invert the polarity of the power supply to prevent DC - //! charge build-up within the display. - // - uint8_t ui8ACBiasLineCount; -} -tLCDRasterTiming; - -//***************************************************************************** -// -// Possible values for the ui8Mode parameter to LCDModeSet(). The label -// LCD_MODE_AUTO_UFLOW_RESTART may be ORed with either of the other two. -// -//***************************************************************************** -#define LCD_MODE_LIDD ((uint8_t)0x00) -#define LCD_MODE_RASTER ((uint8_t)0x01) -#define LCD_MODE_AUTO_UFLOW_RESTART \ - ((uint8_t)0x02) - -//***************************************************************************** -// -// Values used to construct the ui32Config parameter to LCDIDDConfigSet(). -// -//***************************************************************************** -#define LIDD_CONFIG_SYNC_MPU68 0x00000000 -#define LIDD_CONFIG_ASYNC_MPU68 0x00000001 -#define LIDD_CONFIG_SYNC_MPU80 0x00000002 -#define LIDD_CONFIG_ASYNC_MPU80 0x00000003 -#define LIDD_CONFIG_ASYNC_HITACHI \ - 0x00000004 -#define LIDD_CONFIG_INVERT_ALE 0x00000008 -#define LIDD_CONFIG_INVERT_RS_EN \ - 0x00000010 -#define LIDD_CONFIG_INVERT_WS_DIR \ - 0x00000020 -#define LIDD_CONFIG_INVERT_CS0 0x00000040 -#define LIDD_CONFIG_INVERT_CS1 0x00000080 - -//***************************************************************************** -// -// Values used to construct the ui32Config parameter to -// LCDRasterConfigSet(). Valid parameters contain one of the RASTER_FMT_xxx -// labels optionally ORed with the other flags. Only one of -// RASTER_LOAD_DATA_ONLY and RASTER_LOAD_PALETTE_ONLY may be specified (if -// neither is specified, the controller will load both palette and data when -// scanning out the frame buffer). -// -//***************************************************************************** -#define RASTER_FMT_ACTIVE_24BPP_PACKED \ - 0x02000080 -#define RASTER_FMT_ACTIVE_24BPP_UNPACKED \ - 0x06000080 -#define RASTER_FMT_ACTIVE_PALETTIZED_12BIT \ - 0x00000080 -#define RASTER_FMT_ACTIVE_PALETTIZED_16BIT \ - 0x00800080 -#define RASTER_FMT_PASSIVE_MONO_4PIX \ - 0x00000002 -#define RASTER_FMT_PASSIVE_MONO_8PIX \ - 0x00000202 -#define RASTER_FMT_PASSIVE_PALETTIZED \ - 0x00000000 -#define RASTER_FMT_PASSIVE_COLOR_12BIT \ - 0x00000000 -#define RASTER_FMT_PASSIVE_COLOR_16BIT \ - 0x01000000 -#define RASTER_ACTVID_DURING_BLANK \ - 0x08000000 -#define RASTER_NIBBLE_MODE_ENABLED \ - 0x00400000 -#define RASTER_LOAD_DATA_ONLY 0x00200000 -#define RASTER_LOAD_PALETTE_ONLY \ - 0x00100000 -#define RASTER_READ_ORDER_REVERSED \ - 0x00000100 - -//***************************************************************************** -// -// Interrupt sources for the LCD controller. These may be ORed together and -// passed to LCDIntEnable(), LCDIntDisable() and LCDIntClear(). They are also -// returned by LCDIntStatus(). -// -//***************************************************************************** -#define LCD_INT_DMA_DONE 0x00000001 -#define LCD_INT_RASTER_FRAME_DONE \ - 0x00000002 -#define LCD_INT_SYNC_LOST 0x00000004 -#define LCD_INT_AC_BIAS_CNT 0x00000008 -#define LCD_INT_UNDERFLOW 0x00000020 -#define LCD_INT_PAL_LOAD 0x00000040 -#define LCD_INT_EOF0 0x00000100 -#define LCD_INT_EOF1 0x00000200 - -//***************************************************************************** -// -// Configuration values used with LCDDMAConfigSet(). -// -//***************************************************************************** -#define LCD_DMA_FIFORDY_8_WORDS 0x00000000 -#define LCD_DMA_FIFORDY_16_WORDS \ - 0x00000100 -#define LCD_DMA_FIFORDY_32_WORDS \ - 0x00000200 -#define LCD_DMA_FIFORDY_64_WORDS \ - 0x00000300 -#define LCD_DMA_FIFORDY_128_WORDS \ - 0x00000400 -#define LCD_DMA_FIFORDY_256_WORDS \ - 0x00000500 -#define LCD_DMA_FIFORDY_512_WORDS \ - 0x00000600 -#define LCD_DMA_BURST_1 0x00000010 -#define LCD_DMA_BURST_2 0x00000010 -#define LCD_DMA_BURST_4 0x00000020 -#define LCD_DMA_BURST_8 0x00000030 -#define LCD_DMA_BURST_16 0x00000040 -#define LCD_DMA_BYTE_ORDER_0123 0x00000000 -#define LCD_DMA_BYTE_ORDER_1023 0x00000008 -#define LCD_DMA_BYTE_ORDER_3210 0x00000002 -#define LCD_DMA_BYTE_ORDER_2301 0x0000000A -#define LCD_DMA_PING_PONG 0x00000001 - -//***************************************************************************** -// -// Type values used with LCDRasterPaletteSet(). -// -//***************************************************************************** -#define LCD_PALETTE_TYPE_1BPP 0x00000000 -#define LCD_PALETTE_TYPE_2BPP 0x00001000 -#define LCD_PALETTE_TYPE_4BPP 0x00002000 -#define LCD_PALETTE_TYPE_8BPP 0x00003000 -#define LCD_PALETTE_TYPE_DIRECT 0x00004000 -#define LCD_PALETTE_SRC_24BIT 0x80000000 - -//***************************************************************************** -// -// Flags used in the ui32Clocks parameter to LCDClockReset(). -// -//***************************************************************************** -#define LCD_CLOCK_MAIN 0x00000008 -#define LCD_CLOCK_DMA 0x00000004 -#define LCD_CLOCK_LIDD 0x00000002 -#define LCD_CLOCK_CORE 0x00000001 - -//***************************************************************************** -// -// Flags used in with LCDSubPanelConfigSet(). -// -//***************************************************************************** -#define LCD_SUBPANEL_AT_TOP 0x20000000 -#define LCD_SUBPANEL_AT_BOTTOM 0x00000000 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Function Prototypes. -// -//***************************************************************************** -extern uint32_t LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, - uint32_t ui32PixClk, uint32_t ui32SysClk); -extern void LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks); -extern void LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS, - const tLCDIDDTiming *pTiming); -extern void LCDIDDDMADisable(uint32_t ui32Base); -extern void LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Cmd); -extern void LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Data); -extern void LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Addr, uint16_t ui16Data); -extern uint16_t LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS); -extern uint16_t LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS); -extern uint16_t LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, - uint16_t ui16Addr); -extern void LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, - const uint32_t *pui32Data, uint32_t ui32Count); -extern void LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config, - uint8_t ui8PalLoadDelay); -extern void LCDRasterTimingSet(uint32_t ui32Base, - const tLCDRasterTiming *pTiming); -extern void LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count); -extern void LCDRasterEnable(uint32_t ui32Base); -extern bool LCDRasterEnabled(uint32_t ui32Base); -extern void LCDRasterDisable(uint32_t ui32Base); -extern void LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags, - uint32_t ui32BottomLines, - uint32_t ui32DefaultPixel); -extern void LCDRasterSubPanelEnable(uint32_t ui32Base); -extern void LCDRasterSubPanelDisable(uint32_t ui32Base); -extern void LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, - uint32_t *pui32PalAddr, - const uint32_t *pui32SrcColors, - uint32_t ui32Start, - uint32_t ui32Count); -extern void LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer, - uint32_t *pui32Addr, - uint32_t ui32NumBytes); -extern void LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t LCDIntStatus(uint32_t ui32Base, bool bMasked); -extern void LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void LCDIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_LCD_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/mpu.c b/bsp/tm4c129x-dk/libraries/driverlib/mpu.c deleted file mode 100644 index 4d01f1b403..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/mpu.c +++ /dev/null @@ -1,459 +0,0 @@ -//***************************************************************************** -// -// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup mpu_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/mpu.h" - -//***************************************************************************** -// -//! Enables and configures the MPU for use. -//! -//! \param ui32MPUConfig is the logical OR of the possible configurations. -//! -//! This function enables the Cortex-M memory protection unit. It also -//! configures the default behavior when in privileged mode and while handling -//! a hard fault or NMI. Prior to enabling the MPU, at least one region must -//! be set by calling MPURegionSet() or else by enabling the default region for -//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to -//! MPUEnable(). Once the MPU is enabled, a memory management fault is -//! generated for memory access violations. -//! -//! The \e ui32MPUConfig parameter should be the logical OR of any of the -//! following: -//! -//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in -//! privileged mode and when no other regions are defined. If this option -//! is not enabled, then there must be at least one valid region already -//! defined when the MPU is enabled. -//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI -//! exception handler. If this option is not enabled, then the MPU is -//! disabled while in one of these exception handlers and the default -//! memory map is applied. -//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, -//! no default memory map is provided in privileged mode, and the MPU is not -//! enabled in the fault handlers. -//! -//! \return None. -// -//***************************************************************************** -void -MPUEnable(uint32_t ui32MPUConfig) -{ - // - // Check the arguments. - // - ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT | - MPU_CONFIG_HARDFLT_NMI))); - - // - // Set the MPU control bits according to the flags passed by the user, - // and also set the enable bit. - // - HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the MPU for use. -//! -//! This function disables the Cortex-M memory protection unit. When the -//! MPU is disabled, the default memory map is used and memory management -//! faults are not generated. -//! -//! \return None. -// -//***************************************************************************** -void -MPUDisable(void) -{ - // - // Turn off the MPU enable bit. - // - HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! Gets the count of regions supported by the MPU. -//! -//! This function is used to get the total number of regions that are supported -//! by the MPU, including regions that are already programmed. -//! -//! \return The number of memory protection regions that are available -//! for programming using MPURegionSet(). -// -//***************************************************************************** -uint32_t -MPURegionCountGet(void) -{ - // - // Read the DREGION field of the MPU type register and mask off - // the bits of interest to get the count of regions. - // - return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >> - NVIC_MPU_TYPE_DREGION_S); -} - -//***************************************************************************** -// -//! Enables a specific region. -//! -//! \param ui32Region is the region number to enable. -//! -//! This function is used to enable a memory protection region. The region -//! should already be configured with the MPURegionSet() function. Once -//! enabled, the memory protection rules of the region are applied and access -//! violations cause a memory management fault. -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionEnable(uint32_t ui32Region) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - - // - // Select the region to modify. - // - HWREG(NVIC_MPU_NUMBER) = ui32Region; - - // - // Modify the enable bit in the region attributes. - // - HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE; -} - -//***************************************************************************** -// -//! Disables a specific region. -//! -//! \param ui32Region is the region number to disable. -//! -//! This function is used to disable a previously enabled memory protection -//! region. The region remains configured if it is not overwritten with -//! another call to MPURegionSet(), and can be enabled again by calling -//! MPURegionEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionDisable(uint32_t ui32Region) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - - // - // Select the region to modify. - // - HWREG(NVIC_MPU_NUMBER) = ui32Region; - - // - // Modify the enable bit in the region attributes. - // - HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE; -} - -//***************************************************************************** -// -//! Sets up the access rules for a specific region. -//! -//! \param ui32Region is the region number to set up. -//! \param ui32Addr is the base address of the region. It must be aligned -//! according to the size of the region specified in ui32Flags. -//! \param ui32Flags is a set of flags to define the attributes of the region. -//! -//! This function sets up the protection rules for a region. The region has -//! a base address and a set of attributes including the size. The base -//! address parameter, \e ui32Addr, must be aligned according to the size, and -//! the size must be a power of 2. -//! -//! The \e ui32Flags parameter is the logical OR of all of the attributes -//! of the region. It is a combination of choices for region size, -//! execute permission, read/write permissions, disabled sub-regions, -//! and a flag to determine if the region is enabled. -//! -//! The size flag determines the size of a region and must be one of the -//! following: -//! -//! - \b MPU_RGN_SIZE_32B -//! - \b MPU_RGN_SIZE_64B -//! - \b MPU_RGN_SIZE_128B -//! - \b MPU_RGN_SIZE_256B -//! - \b MPU_RGN_SIZE_512B -//! - \b MPU_RGN_SIZE_1K -//! - \b MPU_RGN_SIZE_2K -//! - \b MPU_RGN_SIZE_4K -//! - \b MPU_RGN_SIZE_8K -//! - \b MPU_RGN_SIZE_16K -//! - \b MPU_RGN_SIZE_32K -//! - \b MPU_RGN_SIZE_64K -//! - \b MPU_RGN_SIZE_128K -//! - \b MPU_RGN_SIZE_256K -//! - \b MPU_RGN_SIZE_512K -//! - \b MPU_RGN_SIZE_1M -//! - \b MPU_RGN_SIZE_2M -//! - \b MPU_RGN_SIZE_4M -//! - \b MPU_RGN_SIZE_8M -//! - \b MPU_RGN_SIZE_16M -//! - \b MPU_RGN_SIZE_32M -//! - \b MPU_RGN_SIZE_64M -//! - \b MPU_RGN_SIZE_128M -//! - \b MPU_RGN_SIZE_256M -//! - \b MPU_RGN_SIZE_512M -//! - \b MPU_RGN_SIZE_1G -//! - \b MPU_RGN_SIZE_2G -//! - \b MPU_RGN_SIZE_4G -//! -//! The execute permission flag must be one of the following: -//! -//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code -//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code -//! -//! The read/write access permissions are applied separately for the -//! privileged and user modes. The read/write access flags must be one -//! of the following: -//! -//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode -//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access -//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only -//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write -//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access -//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only -//! -//! The region is automatically divided into 8 equally-sized sub-regions by -//! the MPU. Sub-regions can only be used in regions of size 256 bytes -//! or larger. Any of these 8 sub-regions can be disabled, allowing for -//! creation of ``holes'' in a region which can be left open, or overlaid -//! by another region with different attributes. Any of the 8 sub-regions -//! can be disabled with a logical OR of any of the following flags: -//! -//! - \b MPU_SUB_RGN_DISABLE_0 -//! - \b MPU_SUB_RGN_DISABLE_1 -//! - \b MPU_SUB_RGN_DISABLE_2 -//! - \b MPU_SUB_RGN_DISABLE_3 -//! - \b MPU_SUB_RGN_DISABLE_4 -//! - \b MPU_SUB_RGN_DISABLE_5 -//! - \b MPU_SUB_RGN_DISABLE_6 -//! - \b MPU_SUB_RGN_DISABLE_7 -//! -//! Finally, the region can be initially enabled or disabled with one of -//! the following flags: -//! -//! - \b MPU_RGN_ENABLE -//! - \b MPU_RGN_DISABLE -//! -//! As an example, to set a region with the following attributes: size of -//! 32 KB, execution enabled, read-only for both privileged and user, one -//! sub-region disabled, and initially enabled; the \e ui32Flags parameter -//! would have the following value: -//! -//! -//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO | -//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) -//! -//! -//! \note This function writes to multiple registers and is not protected -//! from interrupts. It is possible that an interrupt which accesses a -//! region may occur while that region is in the process of being changed. -//! The safest way to handle this is to disable a region before changing it. -//! Refer to the discussion of this in the API Detailed Description section. -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - ASSERT(ui32Addr == - (ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))); - - // - // Program the base address, use the region field to select the - // region at the same time. - // - HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID; - - // - // Program the region attributes. Set the TEX field and the S, C, - // and B bits to fixed values that are suitable for all Tiva C and - // E Series memory. - // - HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M | - NVIC_MPU_ATTR_CACHEABLE)) | - NVIC_MPU_ATTR_SHAREABLE | NVIC_MPU_ATTR_BUFFRABLE); -} - -//***************************************************************************** -// -//! Gets the current settings for a specific region. -//! -//! \param ui32Region is the region number to get. -//! \param pui32Addr points to storage for the base address of the region. -//! \param pui32Flags points to the attribute flags for the region. -//! -//! This function retrieves the configuration of a specific region. The -//! meanings and format of the parameters is the same as that of the -//! MPURegionSet() function. -//! -//! This function can be used to save the configuration of a region for later -//! use with the MPURegionSet() function. The region's enable state is -//! preserved in the attributes that are saved. -//! -//! \return None. -// -//***************************************************************************** -void -MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Region < 8); - ASSERT(pui32Addr); - ASSERT(pui32Flags); - - // - // Select the region to get. - // - HWREG(NVIC_MPU_NUMBER) = ui32Region; - - // - // Read and store the base address for the region. - // - *pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M; - - // - // Read and store the region attributes. - // - *pui32Flags = HWREG(NVIC_MPU_ATTR); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the memory management fault. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! memory management fault occurs. -//! -//! This function sets and enables the handler to be called when the MPU -//! generates a memory management fault due to a protection region access -//! violation. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -MPUIntRegister(void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler); - - // - // Register the interrupt handler. - // - IntRegister(FAULT_MPU, pfnHandler); - - // - // Enable the memory management fault. - // - IntEnable(FAULT_MPU); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the memory management fault. -//! -//! This function disables and clears the handler to be called when a -//! memory management fault occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -MPUIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(FAULT_MPU); - - // - // Unregister the interrupt handler. - // - IntUnregister(FAULT_MPU); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/mpu.h b/bsp/tm4c129x-dk/libraries/driverlib/mpu.h deleted file mode 100644 index 9c8377f8ce..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/mpu.h +++ /dev/null @@ -1,162 +0,0 @@ -//***************************************************************************** -// -// mpu.h - Defines and Macros for the memory protection unit. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_MPU_H__ -#define __DRIVERLIB_MPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Flags that can be passed to MPUEnable. -// -//***************************************************************************** -#define MPU_CONFIG_PRIV_DEFAULT 4 -#define MPU_CONFIG_HARDFLT_NMI 2 -#define MPU_CONFIG_NONE 0 - -//***************************************************************************** -// -// Flags for the region size to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_RGN_SIZE_32B (4 << 1) -#define MPU_RGN_SIZE_64B (5 << 1) -#define MPU_RGN_SIZE_128B (6 << 1) -#define MPU_RGN_SIZE_256B (7 << 1) -#define MPU_RGN_SIZE_512B (8 << 1) - -#define MPU_RGN_SIZE_1K (9 << 1) -#define MPU_RGN_SIZE_2K (10 << 1) -#define MPU_RGN_SIZE_4K (11 << 1) -#define MPU_RGN_SIZE_8K (12 << 1) -#define MPU_RGN_SIZE_16K (13 << 1) -#define MPU_RGN_SIZE_32K (14 << 1) -#define MPU_RGN_SIZE_64K (15 << 1) -#define MPU_RGN_SIZE_128K (16 << 1) -#define MPU_RGN_SIZE_256K (17 << 1) -#define MPU_RGN_SIZE_512K (18 << 1) - -#define MPU_RGN_SIZE_1M (19 << 1) -#define MPU_RGN_SIZE_2M (20 << 1) -#define MPU_RGN_SIZE_4M (21 << 1) -#define MPU_RGN_SIZE_8M (22 << 1) -#define MPU_RGN_SIZE_16M (23 << 1) -#define MPU_RGN_SIZE_32M (24 << 1) -#define MPU_RGN_SIZE_64M (25 << 1) -#define MPU_RGN_SIZE_128M (26 << 1) -#define MPU_RGN_SIZE_256M (27 << 1) -#define MPU_RGN_SIZE_512M (28 << 1) - -#define MPU_RGN_SIZE_1G (29 << 1) -#define MPU_RGN_SIZE_2G (30 << 1) -#define MPU_RGN_SIZE_4G (31 << 1) - -//***************************************************************************** -// -// Flags for the permissions to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_RGN_PERM_EXEC 0x00000000 -#define MPU_RGN_PERM_NOEXEC 0x10000000 -#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 -#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 -#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 -#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 -#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 -#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 - -//***************************************************************************** -// -// Flags for the sub-region to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_SUB_RGN_DISABLE_0 0x00000100 -#define MPU_SUB_RGN_DISABLE_1 0x00000200 -#define MPU_SUB_RGN_DISABLE_2 0x00000400 -#define MPU_SUB_RGN_DISABLE_3 0x00000800 -#define MPU_SUB_RGN_DISABLE_4 0x00001000 -#define MPU_SUB_RGN_DISABLE_5 0x00002000 -#define MPU_SUB_RGN_DISABLE_6 0x00004000 -#define MPU_SUB_RGN_DISABLE_7 0x00008000 - -//***************************************************************************** -// -// Flags to enable or disable a region, to be passed to MPURegionSet. -// -//***************************************************************************** -#define MPU_RGN_ENABLE 1 -#define MPU_RGN_DISABLE 0 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void MPUEnable(uint32_t ui32MPUConfig); -extern void MPUDisable(void); -extern uint32_t MPURegionCountGet(void); -extern void MPURegionEnable(uint32_t ui32Region); -extern void MPURegionDisable(uint32_t ui32Region); -extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, - uint32_t ui32Flags); -extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, - uint32_t *pui32Flags); -extern void MPUIntRegister(void (*pfnHandler)(void)); -extern void MPUIntUnregister(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_MPU_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/onewire.c b/bsp/tm4c129x-dk/libraries/driverlib/onewire.c deleted file mode 100644 index 24d671f125..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/onewire.c +++ /dev/null @@ -1,767 +0,0 @@ -//***************************************************************************** -// -// onewire.c - Driver for OneWire master module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup onewire_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_onewire.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/onewire.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -// A bit mask for all transaction related fields in the 1-Wire control -// register. -// -//***************************************************************************** -#define ONEWIRE_TXN_MASK (ONEWIRE_CS_OP_M | ONEWIRE_CS_SZ_M | \ - ONEWIRE_CS_BSIZE_M) - -//***************************************************************************** -// -// Left-shift value for the control register's transaction size. -// -//***************************************************************************** -#define ONEWIRE_TXN_SIZE_LSHIFT 3 - -//***************************************************************************** -// -// Left-shift value for the control register's last byte bit size. -// -//***************************************************************************** -#define ONEWIRE_TXN_BSIZE_LSHIFT \ - 16 - -//***************************************************************************** -// -//! Initializes the 1-Wire module. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32InitFlags provides the initialization flags. -//! -//! This function configures and initializes the 1-Wire interface for use. -//! -//! The \e ui32InitFlags parameter is a combination of the following: -//! -//! - \b ONEWIRE_INIT_SPD_STD - standard speed bus timings -//! - \b ONEWIRE_INIT_SPD_OD - overdrive speed bus timings -//! - \b ONEWIRE_INIT_READ_STD - standard read sampling timing -//! - \b ONEWIRE_INIT_READ_LATE - late read sampling timing -//! - \b ONEWIRE_INIT_ATR - standard answer-to-reset presence detect -//! - \b ONEWIRE_INIT_NO_ATR - no answer-to-reset presence detect -//! - \b ONEWIRE_INIT_STD_POL - normal signal polarity -//! - \b ONEWIRE_INIT_ALT_POL - alternate (reverse) signal polarity -//! - \b ONEWIRE_INIT_1_WIRE_CFG - standard 1-Wire (1 data pin) setup -//! - \b ONEWIRE_INIT_2_WIRE_CFG - alternate 2-Wire (2 data pin) setup -//! -//! \return None. -// -//***************************************************************************** -void -OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Initialize control register. - // - HWREG(ui32Base + ONEWIRE_O_CS) = ui32InitFlags; -} - -//***************************************************************************** -// -//! Issues a reset on the 1-Wire bus. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! -//! This function causes the 1-Wire module to generate a reset signal on the -//! 1-Wire bus. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireBusReset(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Issue a bus reset. - // - HWREG(ui32Base + ONEWIRE_O_CS) |= ONEWIRE_CS_RST; -} - -//***************************************************************************** -// -//! Retrieves the 1-Wire bus condition status. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! -//! This function returns the 1-Wire bus conditions reported by the 1-Wire -//! module. These conditions could be a logical OR of any of the following: -//! -//! - \b ONEWIRE_BUS_STATUS_BUSY - A read, write, or reset is active. -//! - \b ONEWIRE_BUS_STATUS_NO_SLAVE - No slave presence pulses detected. -//! - \b ONEWIRE_BUS_STATUS_STUCK - The bus is being held low by non-master. -//! -//! \return Returns the 1-Wire bus conditions if detected else zero. -// -//***************************************************************************** -uint32_t -OneWireBusStatus(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Return the status bits from control and status register. - // - return(HWREG(ui32Base + ONEWIRE_O_CS) & (ONEWIRE_CS_BUSY | - ONEWIRE_CS_NOATR | - ONEWIRE_CS_STUCK)); -} - -//***************************************************************************** -// -//! Retrieves data from the 1-Wire interface. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param pui32Data is a pointer to storage to hold the read data. -//! -//! This function reads data from the 1-Wire module once all active bus -//! operations are completed. By protocol definition, bit data defaults to -//! a 1. Thus if a slave did not signal any 0-bit data, this read returns -//! 0xffffffff. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(pui32Data); - - // - // Wait for any active operations to complete. - // - while(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY) - { - } - - // - // Copy the data into the provided storage. - // - *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR); -} - -//***************************************************************************** -// -//! Retrieves data from the 1-Wire interface. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param pui32Data is a pointer to storage to hold the read data. -//! -//! This function reads data from the 1-Wire module if there are no active -//! operations on the bus. Otherwise it returns without reading the data from -//! the module. -//! -//! By protocol definition, bit data defaults to a 1. Thus if a slave did -//! not signal any 0-bit data, this read returns 0xffffffff. -//! -//! \return Returns \b true if a data read was performed, or \b false if the -//! bus was not idle and no data was read. -// -//***************************************************************************** -bool -OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(pui32Data); - - // - // If the bus is busy, return without reading. - // - if(HWREG(ui32Base + ONEWIRE_O_CS) & ONEWIRE_CS_BUSY) - { - return(false); - } - - // - // Copy the data into the provided storage. - // - *pui32Data = HWREG(ui32Base + ONEWIRE_O_DATR); - - // - // Notify the caller data was read from the read register. - // - return(true); -} - -//***************************************************************************** -// -//! Clears the 1-Wire module interrupt sources. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! This function clears the specified 1-Wire interrupt sources so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupts from being triggered again immediately upon exit. The -//! \e ui32IntFlags parameter can be a logical OR of any of the following: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a -//! combined write and read operation was set up, the interrupt signals the -//! read is done. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | - ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); - - // - // Clear the requested interrupts. - // - HWREG(ui32Base + ONEWIRE_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual 1-Wire module interrupt sources. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated 1-Wire interrupt sources. The -//! \e ui32IntFlags parameter can be a logical OR of any of the following: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a -//! combined write and read operation was set up, the interrupt signals the -//! read is done. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | - ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); - - // - // Disable the requested interrupts. - // - HWREG(ui32Base + ONEWIRE_O_IM) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables individual 1-Wire module interrupt sources. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated 1-Wire interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. The \e ui32IntFlags -//! parameter can be a logical OR of any of the following: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. If a -//! combined write and read operation was set up, the interrupt signals the -//! read is done. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32IntFlags & ~(ONEWIRE_IM_RST | ONEWIRE_IM_OPC | ONEWIRE_IM_DMA | - ONEWIRE_IM_NOATR | ONEWIRE_IM_STUCK)) == 0); - - // - // Enable the requested interrupts. - // - HWREG(ui32Base + ONEWIRE_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current 1-Wire interrupt status. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param bMasked is \b false if the raw interrupt status is required or -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the 1-Wire module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the masked or raw 1-Wire interrupt status, as a bit field -//! of any of the following values: -//! -//! - \b ONEWIRE_INT_RESET_DONE - Bus reset has just completed. -//! - \b ONEWIRE_INT_OP_DONE - Read or write operation completed. -//! - \b ONEWIRE_INT_NO_SLAVE - No presence detect was signaled by a slave. -//! - \b ONEWIRE_INT_STUCK - Bus is being held low by non-master. -//! - \b ONEWIRE_INT_DMA_DONE - DMA operation has completed -// -//***************************************************************************** -uint32_t -OneWireIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + ONEWIRE_O_MIS)); - } - else - { - return(HWREG(ui32Base + ONEWIRE_O_RIS)); - } -} - -//***************************************************************************** -// -//! Returns the 1-Wire controller interrupt number. -//! -//! \param ui32Base specifies the 1-Wire module base address. -//! -//! This function returns the interrupt number for the 1-Wire module with the -//! base address passed in the \e ui32Base parameter. -//! -//! \return Returns a 1-Wire interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_OneWireIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - ASSERT(ui32Base == ONEWIRE0_BASE); - - ui32Int = 0; - - // - // Find the valid interrupt number for the 1-Wire module. - // - if(CLASS_IS_TM4C129) - { - ui32Int = INT_ONEWIRE0_TM4C129; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the 1-Wire module. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! \param pfnHandler is a pointer to the function to be called when the -//! 1-Wire interrupt occurs. -//! -//! This function sets the handler to be called when a 1-Wire interrupt occurs. -//! This function enables the global interrupt in the interrupt controller; -//! specific 1-Wire interrupts must be enabled via OneWireIntEnable(). If -//! necessary, it is the interrupt handler's responsibility to clear the -//! interrupt source via OneWireIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(pfnHandler); - - // - // Get the actual interrupt number for the 1-Wire module. - // - ui32Int = _OneWireIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the 1-Wire peripheral interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the 1-Wire module. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! -//! This function clears the handler to be called when an 1-Wire interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the argument. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - - // - // Get the actual interrupt number for the 1-Wire module. - // - ui32Int = _OneWireIntNumberGet(ui32Base); - ASSERT(ui32Int != 0); - - // - // Disable the 1-Wire peripheral interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Disables 1-Wire DMA operations. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! -//! This function is used to disable 1-Wire DMA features that were enabled -//! by OneWireDMAEnable(). The specified 1-Wire DMA features are disabled. -//! The \e ui32DMAFlags parameter is a combination of the following: -//! -//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting -//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction -//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write -//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read -//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each -//! completion -//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits -//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits -//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits -//! -//! \return None. -// -//***************************************************************************** -void -OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(ui32DMAFlags > 0); - - // - // Clear the transaction size bits - // - HWREG(ui32Base + ONEWIRE_O_CS) = (HWREG(ui32Base + ONEWIRE_O_CS) & - ~(ONEWIRE_TXN_MASK)); - - // - // Disable the DMA features as requested. - // - HWREG(ui32Base + ONEWIRE_O_DMA) &= ~(ui32DMAFlags & 0xff); -} - -//***************************************************************************** -// -//! Enables 1-Wire DMA operations. -//! -//! \param ui32Base is the base address of the 1-Wire module. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! -//! This function enables the specified 1-Wire DMA features. The 1-Wire module -//! can be configured for write operations, read operations, small write and -//! read operations, and scatter-gather support of mixed operations. -//! -//! The \e ui32DMAFlags parameter is a combination of the following: -//! -//! - \b ONEWIRE_DMA_BUS_RESET - Issue a 1-Wire bus reset before starting -//! - \b ONEWIRE_DMA_OP_READ - Read after each module transaction -//! - \b ONEWIRE_DMA_OP_MULTI_WRITE - Write after each previous write -//! - \b ONEWIRE_DMA_OP_MULTI_READ - Read after each previous read -//! - \b ONEWIRE_DMA_MODE_SG - Start DMA on enable then repeat on each -//! completion -//! - \b ONEWIRE_DMA_OP_SZ_8 - Bus read/write of 8 bits -//! - \b ONEWIRE_DMA_OP_SZ_16 - Bus read/write of 16 bits -//! - \b ONEWIRE_DMA_OP_SZ_32 - Bus read/write of 32 bits -//! -//! \note The uDMA controller must be properly configured before DMA can be -//! used with the 1-Wire module. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT(ui32DMAFlags > 0); - - // - // set up the transaction size. - // - HWREG(ui32Base + ONEWIRE_O_CS) = ((HWREG(ui32Base + ONEWIRE_O_CS) & - ~(ONEWIRE_TXN_MASK)) | - (ui32DMAFlags >> 8)); - - // - // Enable DMA with the parameters provided. - // - HWREG(ui32Base + ONEWIRE_O_DMA) = (ui32DMAFlags & 0xf); - - // - // If a read transaction was requested, seed the write data register. This - // will trigger the DMA reads to start. This should not be done for - // scatter-gather operations. - // - if((ui32DMAFlags & (ONEWIRE_DMA_DMAOP_RDSNG | ONEWIRE_DMA_DMAOP_RDMUL)) && - !(ui32DMAFlags & ONEWIRE_DMA_SG)) - { - // - // Workaround for Snowflake DMA receive trigger errata. - // - if(CLASS_IS_TM4C129) - { - SysCtlDelay(9); - } - - // - // Write DATW to trigger DMA receive start. - // - HWREG(ui32Base + ONEWIRE_O_DATW) = 0xffffffff; - } -} - -//***************************************************************************** -// -//! Performs a 1-Wire protocol transaction on the bus. -//! -//! \param ui32Base specifies the base address of the 1-Wire module. -//! \param ui32OpMode sets the transaction type. -//! \param ui32Data is the data for a write operation. -//! \param ui32BitCnt specifies the number of valid bits (1-32) for the -//! operation. -//! -//! This function performs a 1-Wire protocol transaction, read and/or write, on -//! the bus. The application should confirm the bus is idle before starting a -//! read or write transaction. -//! -//! The \e ui32OpMode defines the activity for the bus operations and is a -//! logical OR of the following: -//! -//! - \b ONEWIRE_OP_RESET - Indicates the operation should be started with -//! a bus reset. -//! - \b ONEWIRE_OP_WRITE - A write operation -//! - \b ONEWIRE_OP_READ - A read operation -//! -//! \note If both a read and write operation are requested, the write will be -//! performed prior to the read. -//! -//! \return None. -// -//***************************************************************************** -void -OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpMode, uint32_t ui32Data, - uint32_t ui32BitCnt) -{ - uint32_t ui32Transaction; - - // - // Check the arguments. - // - ASSERT(ui32Base == ONEWIRE0_BASE); - ASSERT((ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE | - ONEWIRE_OP_READ)) > 0); - ASSERT((ui32BitCnt >= 1) && (ui32BitCnt <= 32)); - - // - // Read the control register and clear any transaction related - // bit fields. - // - ui32Transaction = HWREG(ui32Base + ONEWIRE_O_CS) & ~(ONEWIRE_TXN_MASK); - - // - // Add the user specified operation flags. - // - ui32Transaction |= (ui32OpMode & (ONEWIRE_OP_RESET | ONEWIRE_OP_WRITE | - ONEWIRE_OP_READ)); - - // - // set up for a read or write transaction. - // - if(ui32Transaction & (ONEWIRE_CS_OP_WR | ONEWIRE_CS_OP_RD)) - { - // - // Configure the 1-Wire module for the transaction size. This is - // specified as 1-4 bytes and the specific bit size for the last - // byte therein. - // - ui32Transaction |= ((((ui32BitCnt % 8) ? (ui32BitCnt / 8) + 1 : - (ui32BitCnt / 8)) - 1) << - ONEWIRE_TXN_SIZE_LSHIFT); - ui32Transaction |= ((ui32BitCnt % 8) << ONEWIRE_TXN_BSIZE_LSHIFT); - - // - // Write specific setup. - // - if(ui32Transaction & ONEWIRE_CS_OP_WR) - { - // - // Load the data into the write register. - // - HWREG(ui32Base + ONEWIRE_O_DATW) = ui32Data; - } - } - - // - // Start the transaction. - // - HWREG(ui32Base + ONEWIRE_O_CS) = ui32Transaction; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/onewire.h b/bsp/tm4c129x-dk/libraries/driverlib/onewire.h deleted file mode 100644 index 731f3f99bb..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/onewire.h +++ /dev/null @@ -1,307 +0,0 @@ -//***************************************************************************** -// -// onewire.h - Prototypes for the OneWire Driver. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ONEWIRE_H__ -#define __DRIVERLIB_ONEWIRE_H__ - -//***************************************************************************** -// -//! \addtogroup onewire_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines used in the OneWireInit() function call. -// -//***************************************************************************** - -// -// This define is used in initialization to request standard speed bus -// timings. This is the default. -// -#define ONEWIRE_INIT_SPD_STD 0x00000000 - -// -// This define is used in initialization to request overdrive speed bus -// timings. -// -#define ONEWIRE_INIT_SPD_OD 0x00000020 - -// -// This define is used in initialization to request standard read sampling -// timing (2us for ONEWIRE_INIT_SPD_OD and 16us for ONEWIRE_INIT_SPD_STD). -// This is the default. -// -#define ONEWIRE_INIT_READ_STD 0x00000000 - -// -// This define is used in initialization to request late read sampling -// timing (7us for ONEWIRE_INIT_SPD_OD and 50us for ONEWIRE_INIT_SPD_STD). -// -#define ONEWIRE_INIT_READ_LATE 0x00000040 - -// -// This define is used in initialization to request a standard -// Answer-to-Reset (presence detect) monitor. This is the default. -// -#define ONEWIRE_INIT_ATR 0x00000000 - -// -// This define is used in initialization to request no Answer-to-Reset -// (presence detect) monitor. The module will delay operations after a bus -// reset for the expected presence detect period in this case. -// -#define ONEWIRE_INIT_NO_ATR 0x00000080 - -// -// This define is used in initialization to request standard signal polarity -// on the 1-Wire bus (pin is driven low to drive bus low). This is the -// default. -// -#define ONEWIRE_INIT_STD_POL 0x00000000 - -// -// This define is used in initialization to request alternate signal polarity -// on the 1-Wire bus (pin is driven high to drive bus low). -// -#define ONEWIRE_INIT_ALT_POL 0x40000000 - -// -// This define is used in initialization to request normal 1-Wire operational -// mode. This is the default. -// -#define ONEWIRE_INIT_1_WIRE_CFG 0x00000000 - -// -// This define is used in initialization to request a 2 pin operational -// mode where one pin is used exclusively for TX operations and the other -// for RX. -// -#define ONEWIRE_INIT_2_WIRE_CFG 0x80000000 - -//***************************************************************************** -// -// Defines for bus status conditions. These values can be returned by -// OneWireBusStatus(). -// -//***************************************************************************** - -// -// This will be set if the bus is busy handling a Read, Write or -// Reset activity. -// -#define ONEWIRE_BUS_STATUS_BUSY 0x00000100 - -// -// This will be set if the module did not detect any slave presence pulses -// after a bus reset. -// -#define ONEWIRE_BUS_STATUS_NO_SLAVE \ - 0x00000200 - -// -// This will be set if the bus is being held low outside of a normal Read, -// Write or Reset activity. -// -#define ONEWIRE_BUS_STATUS_STUCK \ - 0x00000400 - -//***************************************************************************** -// -// OneWire operation modes used with OneWireTransaction(). -// -//***************************************************************************** - -// -// This mode flag indicates a single reset should be issued prior to a write -// and/or read operation. -// -#define ONEWIRE_OP_RESET 0x00000001 - -// -// This mode flag indicates a read operation. -// -#define ONEWIRE_OP_READ 0x00000002 - -// -// This mode flag indicates a write operation. -// -#define ONEWIRE_OP_WRITE 0x00000004 - -//***************************************************************************** -// -// OneWire DMA used with OneWireDMAEnable(). -// -//***************************************************************************** - -// -// This indicates the DMA should issue a 1-Wire bus reset before starting. -// -#define ONEWIRE_DMA_BUS_RESET 0x00000001 - -// -// The DMA operation will be a single Read after each module transaction. -// -#define ONEWIRE_DMA_OP_READ 0x00000002 - -// -// The DMA will write values to the 1-Wire interface as each previous DMA -// write operation completes. -// -#define ONEWIRE_DMA_OP_MULTI_WRITE \ - 0x00000004 - -// -// The DMA will read values from the 1-Wire interface as each previous DMA -// read operation completes. -// -#define ONEWIRE_DMA_OP_MULTI_READ \ - 0x00000006 - -// -// This Scatter Gather DMA mode is paired with ONEWIRE_DMA_OP_READ to instruct -// the 1-Wire DMA to initiate an operation at the start of and then on each -// transition completion thereafter. -// -#define ONEWIRE_DMA_MODE_SG 0x00000008 - -// -// DMA expects a Read/Write bus operation size of 8 bits. This should match -// the uDMA channel setup. -// -#define ONEWIRE_DMA_OP_SZ_8 0x00000000 - -// -// DMA expects a Read/Write bus operation size of 16 bits. This should match -// the uDMA channel setup. -// -#define ONEWIRE_DMA_OP_SZ_16 0x00000800 - -// -// DMA expects a Read/Write bus operation size of 32 bits. This should match -// the uDMA channel setup. -// -#define ONEWIRE_DMA_OP_SZ_32 0x00001800 - -//***************************************************************************** -// -// OneWire interrupt defines. Use in calls to OneWireIntEnable(), -// OneWireIntDisable(), OneWireIntClear() and returned by OneWireIntStatus(). -// -//***************************************************************************** - -// -// This interrupt indicates a bus reset has just completed. -// -#define ONEWIRE_INT_RESET_DONE 0x00000001 - -// -// The interrupt indicates a Read or Write master initiated operation -// has just completed. -// -#define ONEWIRE_INT_OP_DONE 0x00000002 - -// -// This interrupt indicates that no presence detect was signaled by a slave -// on the bus after a reset. -// -#define ONEWIRE_INT_NO_SLAVE 0x00000004 - -// -// This interrupt indicates the bus is being held low outside of normal -// operations. -// -#define ONEWIRE_INT_STUCK 0x00000008 - -// -// This interrupt indicates a OneWire DMA operation has completed. -// -#define ONEWIRE_INT_DMA_DONE 0x00000010 - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void OneWireBusReset(uint32_t ui32Base); -extern uint32_t OneWireBusStatus(uint32_t ui32Base); -extern void OneWireDataGet(uint32_t u3i2Base, uint32_t *pui32Data); -extern bool OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); -extern void OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags); -extern void OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void OneWireIntUnregister(uint32_t ui32Base); -extern uint32_t OneWireIntStatus(uint32_t ui32Base, bool bMasked); -extern void OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpFlags, - uint32_t ui32Data, uint32_t ui32BitCnt); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_ONEWIRE_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/pin_map.h b/bsp/tm4c129x-dk/libraries/driverlib/pin_map.h deleted file mode 100644 index 9d68609861..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/pin_map.h +++ /dev/null @@ -1,20953 +0,0 @@ -//***************************************************************************** -// -// pin_map.h - Mapping of peripherals to pins for all parts. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_PIN_MAP_H__ -#define __DRIVERLIB_PIN_MAP_H__ - -//***************************************************************************** -// -// TM4C1230C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230C3PM - -//***************************************************************************** -// -// TM4C1230D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230D5PM - -//***************************************************************************** -// -// TM4C1230E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230E6PM - -//***************************************************************************** -// -// TM4C1230H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1230H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1230H6PM - -//***************************************************************************** -// -// TM4C1231C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231C3PM - -//***************************************************************************** -// -// TM4C1231D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231D5PM - -//***************************************************************************** -// -// TM4C1231D5PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231D5PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1231D5PZ - -//***************************************************************************** -// -// TM4C1231E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231E6PM - -//***************************************************************************** -// -// TM4C1231E6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231E6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1231E6PZ - -//***************************************************************************** -// -// TM4C1231H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1231H6PM - -//***************************************************************************** -// -// TM4C1231H6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231H6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1231H6PZ - -//***************************************************************************** -// -// TM4C1232C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232C3PM - -//***************************************************************************** -// -// TM4C1232D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232D5PM - -//***************************************************************************** -// -// TM4C1232E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232E6PM - -//***************************************************************************** -// -// TM4C1232H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1232H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C1232H6PM - -//***************************************************************************** -// -// TM4C1233C3PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233C3PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233C3PM - -//***************************************************************************** -// -// TM4C1233D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233D5PM - -//***************************************************************************** -// -// TM4C1233D5PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233D5PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1233D5PZ - -//***************************************************************************** -// -// TM4C1233E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233E6PM - -//***************************************************************************** -// -// TM4C1233E6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233E6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1233E6PZ - -//***************************************************************************** -// -// TM4C1233H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C1233H6PM - -//***************************************************************************** -// -// TM4C1233H6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233H6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1233H6PZ - -//***************************************************************************** -// -// TM4C1236D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1236D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C1236D5PM - -//***************************************************************************** -// -// TM4C1236E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1236E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C1236E6PM - -//***************************************************************************** -// -// TM4C1236H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1236H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C1236H6PM - -//***************************************************************************** -// -// TM4C1237D5PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237D5PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C1237D5PM - -//***************************************************************************** -// -// TM4C1237D5PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237D5PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1237D5PZ - -//***************************************************************************** -// -// TM4C1237E6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237E6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C1237E6PM - -//***************************************************************************** -// -// TM4C1237E6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237E6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1237E6PZ - -//***************************************************************************** -// -// TM4C1237H6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237H6PM - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C1237H6PM - -//***************************************************************************** -// -// TM4C1237H6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237H6PZ - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#endif // PART_TM4C1237H6PZ - -//***************************************************************************** -// -// TM4C123AE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123AE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C123AE6PM - -//***************************************************************************** -// -// TM4C123AH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123AH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#endif // PART_TM4C123AH6PM - -//***************************************************************************** -// -// TM4C123BE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C123BE6PM - -//***************************************************************************** -// -// TM4C123BE6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BE6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123BE6PZ - -//***************************************************************************** -// -// TM4C123BH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 - -#endif // PART_TM4C123BH6PM - -//***************************************************************************** -// -// TM4C123BH6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123BH6PZ - -//***************************************************************************** -// -// TM4C123FE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123FE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C123FE6PM - -//***************************************************************************** -// -// TM4C123FH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123FH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#endif // PART_TM4C123FH6PM - -//***************************************************************************** -// -// TM4C123GE6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GE6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C123GE6PM - -//***************************************************************************** -// -// TM4C123GE6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GE6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123GE6PZ - -//***************************************************************************** -// -// TM4C123GH6PM Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6PM - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 - -#endif // PART_TM4C123GH6PM - -//***************************************************************************** -// -// TM4C123GH6PZ Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6PZ - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#endif // PART_TM4C123GH6PZ - -//***************************************************************************** -// -// TM4C1231H6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1231H6PGE - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C1231H6PGE - -//***************************************************************************** -// -// TM4C1233H6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1233H6PGE - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C1233H6PGE - -//***************************************************************************** -// -// TM4C1237H6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1237H6PGE - -#define GPIO_PA0_U0RX 0x00000001 - -#define GPIO_PA1_U0TX 0x00000401 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 - -#define GPIO_PA7_I2C1SDA 0x00001C03 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE7_U1RI 0x00041C01 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 - -#define GPIO_PK1_SSI3FSS 0x00090402 - -#define GPIO_PK2_SSI3RX 0x00090802 - -#define GPIO_PK3_SSI3TX 0x00090C02 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C1237H6PGE - -//***************************************************************************** -// -// TM4C123BH6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6PGE - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C123BH6PGE - -//***************************************************************************** -// -// TM4C123BH6ZRB Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123BH6ZRB - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#define GPIO_PP3_M0PWM3 0x000D0C01 -#define GPIO_PP3_T5CCP1 0x000D0C07 - -#define GPIO_PP4_M0PWM4 0x000D1001 -#define GPIO_PP4_WT0CCP0 0x000D1007 - -#define GPIO_PP5_M0PWM5 0x000D1401 -#define GPIO_PP5_WT0CCP1 0x000D1407 - -#define GPIO_PP6_M0PWM6 0x000D1801 -#define GPIO_PP6_WT1CCP0 0x000D1807 - -#define GPIO_PP7_M0PWM7 0x000D1C01 -#define GPIO_PP7_WT1CCP1 0x000D1C07 - -#define GPIO_PQ0_M1PWM0 0x000E0001 -#define GPIO_PQ0_WT2CCP0 0x000E0007 - -#define GPIO_PQ1_M1PWM1 0x000E0401 -#define GPIO_PQ1_WT2CCP1 0x000E0407 - -#define GPIO_PQ2_M1PWM2 0x000E0801 -#define GPIO_PQ2_WT3CCP0 0x000E0807 - -#define GPIO_PQ3_M1PWM3 0x000E0C01 -#define GPIO_PQ3_WT3CCP1 0x000E0C07 - -#define GPIO_PQ4_M1PWM4 0x000E1001 -#define GPIO_PQ4_WT4CCP0 0x000E1007 - -#define GPIO_PQ5_M1PWM5 0x000E1401 -#define GPIO_PQ5_WT4CCP1 0x000E1407 - -#define GPIO_PQ6_M1PWM6 0x000E1801 -#define GPIO_PQ6_WT5CCP0 0x000E1807 - -#define GPIO_PQ7_M1PWM7 0x000E1C01 -#define GPIO_PQ7_WT5CCP1 0x000E1C07 - -#endif // PART_TM4C123BH6ZRB - -//***************************************************************************** -// -// TM4C123GH6PGE Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6PGE - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#endif // PART_TM4C123GH6PGE - -//***************************************************************************** -// -// TM4C123GH6ZRB Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6ZRB - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#define GPIO_PP3_M0PWM3 0x000D0C01 -#define GPIO_PP3_T5CCP1 0x000D0C07 - -#define GPIO_PP4_M0PWM4 0x000D1001 -#define GPIO_PP4_WT0CCP0 0x000D1007 - -#define GPIO_PP5_M0PWM5 0x000D1401 -#define GPIO_PP5_WT0CCP1 0x000D1407 - -#define GPIO_PP6_M0PWM6 0x000D1801 -#define GPIO_PP6_WT1CCP0 0x000D1807 - -#define GPIO_PP7_M0PWM7 0x000D1C01 -#define GPIO_PP7_WT1CCP1 0x000D1C07 - -#define GPIO_PQ0_M1PWM0 0x000E0001 -#define GPIO_PQ0_WT2CCP0 0x000E0007 - -#define GPIO_PQ1_M1PWM1 0x000E0401 -#define GPIO_PQ1_WT2CCP1 0x000E0407 - -#define GPIO_PQ2_M1PWM2 0x000E0801 -#define GPIO_PQ2_WT3CCP0 0x000E0807 - -#define GPIO_PQ3_M1PWM3 0x000E0C01 -#define GPIO_PQ3_WT3CCP1 0x000E0C07 - -#define GPIO_PQ4_M1PWM4 0x000E1001 -#define GPIO_PQ4_WT4CCP0 0x000E1007 - -#define GPIO_PQ5_M1PWM5 0x000E1401 -#define GPIO_PQ5_WT4CCP1 0x000E1407 - -#define GPIO_PQ6_M1PWM6 0x000E1801 -#define GPIO_PQ6_WT5CCP0 0x000E1807 - -#define GPIO_PQ7_M1PWM7 0x000E1C01 -#define GPIO_PQ7_WT5CCP1 0x000E1C07 - -#endif // PART_TM4C123GH6ZRB - -//***************************************************************************** -// -// TM4C123GH6ZXR Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C123GH6ZXR - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_CAN1RX 0x00000008 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_CAN1TX 0x00000408 - -#define GPIO_PA2_SSI0CLK 0x00000802 - -#define GPIO_PA3_SSI0FSS 0x00000C02 - -#define GPIO_PA4_SSI0RX 0x00001002 - -#define GPIO_PA5_SSI0TX 0x00001402 - -#define GPIO_PA6_I2C1SCL 0x00001803 -#define GPIO_PA6_M1PWM2 0x00001805 - -#define GPIO_PA7_I2C1SDA 0x00001C03 -#define GPIO_PA7_M1PWM3 0x00001C05 - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_T2CCP0 0x00010007 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_T2CCP1 0x00010407 - -#define GPIO_PB2_I2C0SCL 0x00010803 -#define GPIO_PB2_T3CCP0 0x00010807 - -#define GPIO_PB3_I2C0SDA 0x00010C03 -#define GPIO_PB3_T3CCP1 0x00010C07 - -#define GPIO_PB4_SSI2CLK 0x00011002 -#define GPIO_PB4_M0PWM2 0x00011004 -#define GPIO_PB4_T1CCP0 0x00011007 -#define GPIO_PB4_CAN0RX 0x00011008 - -#define GPIO_PB5_SSI2FSS 0x00011402 -#define GPIO_PB5_M0PWM3 0x00011404 -#define GPIO_PB5_T1CCP1 0x00011407 -#define GPIO_PB5_CAN0TX 0x00011408 - -#define GPIO_PB6_SSI2RX 0x00011802 -#define GPIO_PB6_I2C5SCL 0x00011803 -#define GPIO_PB6_M0PWM0 0x00011804 -#define GPIO_PB6_T0CCP0 0x00011807 - -#define GPIO_PB7_SSI2TX 0x00011C02 -#define GPIO_PB7_I2C5SDA 0x00011C03 -#define GPIO_PB7_M0PWM1 0x00011C04 -#define GPIO_PB7_T0CCP1 0x00011C07 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 -#define GPIO_PC0_T4CCP0 0x00020007 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 -#define GPIO_PC1_T4CCP1 0x00020407 - -#define GPIO_PC2_TDI 0x00020801 -#define GPIO_PC2_T5CCP0 0x00020807 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 -#define GPIO_PC3_T5CCP1 0x00020C07 - -#define GPIO_PC4_U4RX 0x00021001 -#define GPIO_PC4_U1RX 0x00021002 -#define GPIO_PC4_M0PWM6 0x00021004 -#define GPIO_PC4_IDX1 0x00021006 -#define GPIO_PC4_WT0CCP0 0x00021007 -#define GPIO_PC4_U1RTS 0x00021008 - -#define GPIO_PC5_U4TX 0x00021401 -#define GPIO_PC5_U1TX 0x00021402 -#define GPIO_PC5_M0PWM7 0x00021404 -#define GPIO_PC5_PHA1 0x00021406 -#define GPIO_PC5_WT0CCP1 0x00021407 -#define GPIO_PC5_U1CTS 0x00021408 - -#define GPIO_PC6_U3RX 0x00021801 -#define GPIO_PC6_PHB1 0x00021806 -#define GPIO_PC6_WT1CCP0 0x00021807 -#define GPIO_PC6_USB0EPEN 0x00021808 - -#define GPIO_PC7_U3TX 0x00021C01 -#define GPIO_PC7_WT1CCP1 0x00021C07 -#define GPIO_PC7_USB0PFLT 0x00021C08 - -#define GPIO_PD0_SSI3CLK 0x00030001 -#define GPIO_PD0_SSI1CLK 0x00030002 -#define GPIO_PD0_I2C3SCL 0x00030003 -#define GPIO_PD0_M0PWM6 0x00030004 -#define GPIO_PD0_M1PWM0 0x00030005 -#define GPIO_PD0_WT2CCP0 0x00030007 - -#define GPIO_PD1_SSI3FSS 0x00030401 -#define GPIO_PD1_SSI1FSS 0x00030402 -#define GPIO_PD1_I2C3SDA 0x00030403 -#define GPIO_PD1_M0PWM7 0x00030404 -#define GPIO_PD1_M1PWM1 0x00030405 -#define GPIO_PD1_WT2CCP1 0x00030407 - -#define GPIO_PD2_SSI3RX 0x00030801 -#define GPIO_PD2_SSI1RX 0x00030802 -#define GPIO_PD2_M0FAULT0 0x00030804 -#define GPIO_PD2_WT3CCP0 0x00030807 -#define GPIO_PD2_USB0EPEN 0x00030808 - -#define GPIO_PD3_SSI3TX 0x00030C01 -#define GPIO_PD3_SSI1TX 0x00030C02 -#define GPIO_PD3_IDX0 0x00030C06 -#define GPIO_PD3_WT3CCP1 0x00030C07 -#define GPIO_PD3_USB0PFLT 0x00030C08 - -#define GPIO_PD4_U6RX 0x00031001 -#define GPIO_PD4_WT4CCP0 0x00031007 - -#define GPIO_PD5_U6TX 0x00031401 -#define GPIO_PD5_WT4CCP1 0x00031407 - -#define GPIO_PD6_U2RX 0x00031801 -#define GPIO_PD6_M0FAULT0 0x00031804 -#define GPIO_PD6_PHA0 0x00031806 -#define GPIO_PD6_WT5CCP0 0x00031807 - -#define GPIO_PD7_U2TX 0x00031C01 -#define GPIO_PD7_M0FAULT1 0x00031C04 -#define GPIO_PD7_PHB0 0x00031C06 -#define GPIO_PD7_WT5CCP1 0x00031C07 -#define GPIO_PD7_NMI 0x00031C08 - -#define GPIO_PE0_U7RX 0x00040001 - -#define GPIO_PE1_U7TX 0x00040401 - -#define GPIO_PE4_U5RX 0x00041001 -#define GPIO_PE4_I2C2SCL 0x00041003 -#define GPIO_PE4_M0PWM4 0x00041004 -#define GPIO_PE4_M1PWM2 0x00041005 -#define GPIO_PE4_CAN0RX 0x00041008 - -#define GPIO_PE5_U5TX 0x00041401 -#define GPIO_PE5_I2C2SDA 0x00041403 -#define GPIO_PE5_M0PWM5 0x00041404 -#define GPIO_PE5_M1PWM3 0x00041405 -#define GPIO_PE5_CAN0TX 0x00041408 - -#define GPIO_PE6_CAN1RX 0x00041808 - -#define GPIO_PE7_U1RI 0x00041C01 -#define GPIO_PE7_CAN1TX 0x00041C08 - -#define GPIO_PF0_U1RTS 0x00050001 -#define GPIO_PF0_SSI1RX 0x00050002 -#define GPIO_PF0_CAN0RX 0x00050003 -#define GPIO_PF0_M1PWM4 0x00050005 -#define GPIO_PF0_PHA0 0x00050006 -#define GPIO_PF0_T0CCP0 0x00050007 -#define GPIO_PF0_NMI 0x00050008 -#define GPIO_PF0_C0O 0x00050009 -#define GPIO_PF0_TRD2 0x0005000E - -#define GPIO_PF1_U1CTS 0x00050401 -#define GPIO_PF1_SSI1TX 0x00050402 -#define GPIO_PF1_M1PWM5 0x00050405 -#define GPIO_PF1_PHB0 0x00050406 -#define GPIO_PF1_T0CCP1 0x00050407 -#define GPIO_PF1_C1O 0x00050409 -#define GPIO_PF1_TRD1 0x0005040E - -#define GPIO_PF2_U1DCD 0x00050801 -#define GPIO_PF2_SSI1CLK 0x00050802 -#define GPIO_PF2_M0FAULT0 0x00050804 -#define GPIO_PF2_M1PWM6 0x00050805 -#define GPIO_PF2_T1CCP0 0x00050807 -#define GPIO_PF2_C2O 0x00050809 -#define GPIO_PF2_TRD0 0x0005080E - -#define GPIO_PF3_U1DSR 0x00050C01 -#define GPIO_PF3_SSI1FSS 0x00050C02 -#define GPIO_PF3_CAN0TX 0x00050C03 -#define GPIO_PF3_M0FAULT1 0x00050C04 -#define GPIO_PF3_M1PWM7 0x00050C05 -#define GPIO_PF3_T1CCP1 0x00050C07 -#define GPIO_PF3_TRCLK 0x00050C0E - -#define GPIO_PF4_U1DTR 0x00051001 -#define GPIO_PF4_M0FAULT2 0x00051004 -#define GPIO_PF4_M1FAULT0 0x00051005 -#define GPIO_PF4_IDX0 0x00051006 -#define GPIO_PF4_T2CCP0 0x00051007 -#define GPIO_PF4_USB0EPEN 0x00051008 -#define GPIO_PF4_TRD3 0x0005100E - -#define GPIO_PF5_M0FAULT3 0x00051404 -#define GPIO_PF5_T2CCP1 0x00051407 -#define GPIO_PF5_USB0PFLT 0x00051408 - -#define GPIO_PF6_I2C2SCL 0x00051803 -#define GPIO_PF6_T3CCP0 0x00051807 - -#define GPIO_PF7_I2C2SDA 0x00051C03 -#define GPIO_PF7_M1FAULT0 0x00051C05 -#define GPIO_PF7_T3CCP1 0x00051C07 - -#define GPIO_PG0_I2C3SCL 0x00060003 -#define GPIO_PG0_M1FAULT1 0x00060005 -#define GPIO_PG0_PHA1 0x00060006 -#define GPIO_PG0_T4CCP0 0x00060007 - -#define GPIO_PG1_I2C3SDA 0x00060403 -#define GPIO_PG1_M1FAULT2 0x00060405 -#define GPIO_PG1_PHB1 0x00060406 -#define GPIO_PG1_T4CCP1 0x00060407 - -#define GPIO_PG2_I2C4SCL 0x00060803 -#define GPIO_PG2_M0FAULT1 0x00060804 -#define GPIO_PG2_M1PWM0 0x00060805 -#define GPIO_PG2_T5CCP0 0x00060807 - -#define GPIO_PG3_I2C4SDA 0x00060C03 -#define GPIO_PG3_M0FAULT2 0x00060C04 -#define GPIO_PG3_M1PWM1 0x00060C05 -#define GPIO_PG3_PHA1 0x00060C06 -#define GPIO_PG3_T5CCP1 0x00060C07 - -#define GPIO_PG4_U2RX 0x00061001 -#define GPIO_PG4_I2C1SCL 0x00061003 -#define GPIO_PG4_M0PWM4 0x00061004 -#define GPIO_PG4_M1PWM2 0x00061005 -#define GPIO_PG4_PHB1 0x00061006 -#define GPIO_PG4_WT0CCP0 0x00061007 -#define GPIO_PG4_USB0EPEN 0x00061008 - -#define GPIO_PG5_U2TX 0x00061401 -#define GPIO_PG5_I2C1SDA 0x00061403 -#define GPIO_PG5_M0PWM5 0x00061404 -#define GPIO_PG5_M1PWM3 0x00061405 -#define GPIO_PG5_IDX1 0x00061406 -#define GPIO_PG5_WT0CCP1 0x00061407 -#define GPIO_PG5_USB0PFLT 0x00061408 - -#define GPIO_PG6_I2C5SCL 0x00061803 -#define GPIO_PG6_M0PWM6 0x00061804 -#define GPIO_PG6_WT1CCP0 0x00061807 - -#define GPIO_PG7_I2C5SDA 0x00061C03 -#define GPIO_PG7_M0PWM7 0x00061C04 -#define GPIO_PG7_IDX1 0x00061C05 -#define GPIO_PG7_WT1CCP1 0x00061C07 - -#define GPIO_PH0_SSI3CLK 0x00070002 -#define GPIO_PH0_M0PWM0 0x00070004 -#define GPIO_PH0_M0FAULT0 0x00070006 -#define GPIO_PH0_WT2CCP0 0x00070007 - -#define GPIO_PH1_SSI3FSS 0x00070402 -#define GPIO_PH1_M0PWM1 0x00070404 -#define GPIO_PH1_IDX0 0x00070405 -#define GPIO_PH1_M0FAULT1 0x00070406 -#define GPIO_PH1_WT2CCP1 0x00070407 - -#define GPIO_PH2_SSI3RX 0x00070802 -#define GPIO_PH2_M0PWM2 0x00070804 -#define GPIO_PH2_M0FAULT2 0x00070806 -#define GPIO_PH2_WT5CCP0 0x00070807 - -#define GPIO_PH3_SSI3TX 0x00070C02 -#define GPIO_PH3_M0PWM3 0x00070C04 -#define GPIO_PH3_M0FAULT3 0x00070C06 -#define GPIO_PH3_WT5CCP1 0x00070C07 - -#define GPIO_PH4_SSI2CLK 0x00071002 -#define GPIO_PH4_M0PWM4 0x00071004 -#define GPIO_PH4_PHA0 0x00071005 -#define GPIO_PH4_WT3CCP0 0x00071007 - -#define GPIO_PH5_SSI2FSS 0x00071402 -#define GPIO_PH5_M0PWM5 0x00071404 -#define GPIO_PH5_PHB0 0x00071405 -#define GPIO_PH5_WT3CCP1 0x00071407 - -#define GPIO_PH6_SSI2RX 0x00071802 -#define GPIO_PH6_M0PWM6 0x00071804 -#define GPIO_PH6_WT4CCP0 0x00071807 - -#define GPIO_PH7_SSI2TX 0x00071C02 -#define GPIO_PH7_M0PWM7 0x00071C04 -#define GPIO_PH7_WT4CCP1 0x00071C07 - -#define GPIO_PJ0_U4RX 0x00080001 -#define GPIO_PJ0_T1CCP0 0x00080007 - -#define GPIO_PJ1_U4TX 0x00080401 -#define GPIO_PJ1_T1CCP1 0x00080407 - -#define GPIO_PJ2_U5RX 0x00080801 -#define GPIO_PJ2_IDX0 0x00080805 -#define GPIO_PJ2_T2CCP0 0x00080807 - -#define GPIO_PJ3_U5TX 0x00080C01 -#define GPIO_PJ3_T2CCP1 0x00080C07 - -#define GPIO_PJ4_U6RX 0x00081001 -#define GPIO_PJ4_T3CCP0 0x00081007 - -#define GPIO_PJ5_U6TX 0x00081401 -#define GPIO_PJ5_T3CCP1 0x00081407 - -#define GPIO_PK0_SSI3CLK 0x00090002 -#define GPIO_PK0_M1FAULT0 0x00090006 - -#define GPIO_PK1_SSI3FSS 0x00090402 -#define GPIO_PK1_M1FAULT1 0x00090406 - -#define GPIO_PK2_SSI3RX 0x00090802 -#define GPIO_PK2_M1FAULT2 0x00090806 - -#define GPIO_PK3_SSI3TX 0x00090C02 -#define GPIO_PK3_M1FAULT3 0x00090C06 - -#define GPIO_PK4_U7RX 0x00091001 -#define GPIO_PK4_M0FAULT0 0x00091006 -#define GPIO_PK4_RTCCLK 0x00091007 -#define GPIO_PK4_C0O 0x00091008 - -#define GPIO_PK5_U7TX 0x00091401 -#define GPIO_PK5_M0FAULT1 0x00091406 -#define GPIO_PK5_C1O 0x00091408 - -#define GPIO_PK6_M0FAULT2 0x00091806 -#define GPIO_PK6_WT1CCP0 0x00091807 -#define GPIO_PK6_C2O 0x00091808 - -#define GPIO_PK7_M0FAULT3 0x00091C06 -#define GPIO_PK7_WT1CCP1 0x00091C07 - -#define GPIO_PL0_T0CCP0 0x000A0007 -#define GPIO_PL0_WT0CCP0 0x000A0008 - -#define GPIO_PL1_T0CCP1 0x000A0407 -#define GPIO_PL1_WT0CCP1 0x000A0408 - -#define GPIO_PL2_T1CCP0 0x000A0807 -#define GPIO_PL2_WT1CCP0 0x000A0808 - -#define GPIO_PL3_T1CCP1 0x000A0C07 -#define GPIO_PL3_WT1CCP1 0x000A0C08 - -#define GPIO_PL4_T2CCP0 0x000A1007 -#define GPIO_PL4_WT2CCP0 0x000A1008 - -#define GPIO_PL5_T2CCP1 0x000A1407 -#define GPIO_PL5_WT2CCP1 0x000A1408 - -#define GPIO_PL6_T3CCP0 0x000A1807 -#define GPIO_PL6_WT3CCP0 0x000A1808 - -#define GPIO_PL7_T3CCP1 0x000A1C07 -#define GPIO_PL7_WT3CCP1 0x000A1C08 - -#define GPIO_PM0_T4CCP0 0x000B0007 -#define GPIO_PM0_WT4CCP0 0x000B0008 - -#define GPIO_PM1_T4CCP1 0x000B0407 -#define GPIO_PM1_WT4CCP1 0x000B0408 - -#define GPIO_PM2_T5CCP0 0x000B0807 -#define GPIO_PM2_WT5CCP0 0x000B0808 - -#define GPIO_PM3_T5CCP1 0x000B0C07 -#define GPIO_PM3_WT5CCP1 0x000B0C08 - -#define GPIO_PM6_M0PWM4 0x000B1802 -#define GPIO_PM6_WT0CCP0 0x000B1807 - -#define GPIO_PM7_M0PWM5 0x000B1C02 -#define GPIO_PM7_WT0CCP1 0x000B1C07 - -#define GPIO_PN0_CAN0RX 0x000C0001 - -#define GPIO_PN1_CAN0TX 0x000C0401 - -#define GPIO_PN2_M0PWM6 0x000C0802 -#define GPIO_PN2_WT2CCP0 0x000C0807 - -#define GPIO_PN3_M0PWM7 0x000C0C02 -#define GPIO_PN3_WT2CCP1 0x000C0C07 - -#define GPIO_PN4_M1PWM4 0x000C1002 -#define GPIO_PN4_WT3CCP0 0x000C1007 - -#define GPIO_PN5_M1PWM5 0x000C1402 -#define GPIO_PN5_WT3CCP1 0x000C1407 - -#define GPIO_PN6_M1PWM6 0x000C1802 -#define GPIO_PN6_WT4CCP0 0x000C1807 - -#define GPIO_PN7_M1PWM7 0x000C1C02 -#define GPIO_PN7_WT4CCP1 0x000C1C07 - -#define GPIO_PP0_M0PWM0 0x000D0001 -#define GPIO_PP0_T4CCP0 0x000D0007 - -#define GPIO_PP1_M0PWM1 0x000D0401 -#define GPIO_PP1_T4CCP1 0x000D0407 - -#define GPIO_PP2_M0PWM2 0x000D0801 -#define GPIO_PP2_T5CCP0 0x000D0807 - -#define GPIO_PP3_M0PWM3 0x000D0C01 -#define GPIO_PP3_T5CCP1 0x000D0C07 - -#define GPIO_PP4_M0PWM4 0x000D1001 -#define GPIO_PP4_WT0CCP0 0x000D1007 - -#define GPIO_PP5_M0PWM5 0x000D1401 -#define GPIO_PP5_WT0CCP1 0x000D1407 - -#define GPIO_PP6_M0PWM6 0x000D1801 -#define GPIO_PP6_WT1CCP0 0x000D1807 - -#define GPIO_PP7_M0PWM7 0x000D1C01 -#define GPIO_PP7_WT1CCP1 0x000D1C07 - -#define GPIO_PQ0_M1PWM0 0x000E0001 -#define GPIO_PQ0_WT2CCP0 0x000E0007 - -#define GPIO_PQ1_M1PWM1 0x000E0401 -#define GPIO_PQ1_WT2CCP1 0x000E0407 - -#define GPIO_PQ2_M1PWM2 0x000E0801 -#define GPIO_PQ2_WT3CCP0 0x000E0807 - -#define GPIO_PQ3_M1PWM3 0x000E0C01 -#define GPIO_PQ3_WT3CCP1 0x000E0C07 - -#define GPIO_PQ4_M1PWM4 0x000E1001 -#define GPIO_PQ4_WT4CCP0 0x000E1007 - -#define GPIO_PQ5_M1PWM5 0x000E1401 -#define GPIO_PQ5_WT4CCP1 0x000E1407 - -#define GPIO_PQ6_M1PWM6 0x000E1801 -#define GPIO_PQ6_WT5CCP0 0x000E1807 - -#define GPIO_PQ7_M1PWM7 0x000E1C01 -#define GPIO_PQ7_WT5CCP1 0x000E1C07 - -#endif // PART_TM4C123GH6ZXR - -//***************************************************************************** -// -// TM4C1290NCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1290NCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#endif // PART_TM4C1290NCPDT - -//***************************************************************************** -// -// TM4C1290NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1290NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C1290NCZAD - -//***************************************************************************** -// -// TM4C1292NCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1292NCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#endif // PART_TM4C1292NCPDT - -//***************************************************************************** -// -// TM4C1292NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1292NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C1292NCZAD - -//***************************************************************************** -// -// TM4C1294KCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1294KCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C1294KCPDT - -//***************************************************************************** -// -// TM4C1294NCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1294NCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C1294NCPDT - -//***************************************************************************** -// -// TM4C1294NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1294NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C1294NCZAD - -//***************************************************************************** -// -// TM4C1297NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1297NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C1297NCZAD - -//***************************************************************************** -// -// TM4C1299KCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1299KCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C1299KCZAD - -//***************************************************************************** -// -// TM4C1299NCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C1299NCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C1299NCZAD - -//***************************************************************************** -// -// TM4C129CNCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129CNCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#endif // PART_TM4C129CNCPDT - -//***************************************************************************** -// -// TM4C129CNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129CNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C129CNCZAD - -//***************************************************************************** -// -// TM4C129DNCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129DNCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#endif // PART_TM4C129DNCPDT - -//***************************************************************************** -// -// TM4C129DNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129DNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C129DNCZAD - -//***************************************************************************** -// -// TM4C129EKCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129EKCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C129EKCPDT - -//***************************************************************************** -// -// TM4C129ENCPDT Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129ENCPDT - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#endif // PART_TM4C129ENCPDT - -//***************************************************************************** -// -// TM4C129ENCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129ENCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 - -#define GPIO_PJ3_U2CTS 0x00080C01 - -#define GPIO_PJ4_U3RTS 0x00081001 - -#define GPIO_PJ5_U3CTS 0x00081401 - -#define GPIO_PJ6_U4RTS 0x00081801 - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 - -#define GPIO_PS7_T5CCP1 0x00101C03 - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 - -#endif // PART_TM4C129ENCZAD - -//***************************************************************************** -// -// TM4C129LNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129LNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 - -#define GPIO_PQ6_U1DTR 0x000E1801 - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C129LNCZAD - -//***************************************************************************** -// -// TM4C129XKCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129XKCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 -#define GPIO_PE3_OWIRE 0x00040C05 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_OWIRE 0x00061005 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_OWALT 0x00061405 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_OWIRE 0x00061805 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_OWIRE 0x00061C05 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_OWIRE 0x000D1004 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_OWALT 0x000D1404 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PP7_OWIRE 0x000D1C05 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C129XKCZAD - -//***************************************************************************** -// -// TM4C129XNCZAD Port/Pin Mapping Definitions -// -//***************************************************************************** -#ifdef PART_TM4C129XNCZAD - -#define GPIO_PA0_U0RX 0x00000001 -#define GPIO_PA0_I2C9SCL 0x00000002 -#define GPIO_PA0_T0CCP0 0x00000003 -#define GPIO_PA0_CAN0RX 0x00000007 - -#define GPIO_PA1_U0TX 0x00000401 -#define GPIO_PA1_I2C9SDA 0x00000402 -#define GPIO_PA1_T0CCP1 0x00000403 -#define GPIO_PA1_CAN0TX 0x00000407 - -#define GPIO_PA2_U4RX 0x00000801 -#define GPIO_PA2_I2C8SCL 0x00000802 -#define GPIO_PA2_T1CCP0 0x00000803 -#define GPIO_PA2_SSI0CLK 0x0000080F - -#define GPIO_PA3_U4TX 0x00000C01 -#define GPIO_PA3_I2C8SDA 0x00000C02 -#define GPIO_PA3_T1CCP1 0x00000C03 -#define GPIO_PA3_SSI0FSS 0x00000C0F - -#define GPIO_PA4_U3RX 0x00001001 -#define GPIO_PA4_T2CCP0 0x00001003 -#define GPIO_PA4_I2C7SCL 0x00001002 -#define GPIO_PA4_SSI0XDAT0 0x0000100F - -#define GPIO_PA5_U3TX 0x00001401 -#define GPIO_PA5_T2CCP1 0x00001403 -#define GPIO_PA5_I2C7SDA 0x00001402 -#define GPIO_PA5_SSI0XDAT1 0x0000140F - -#define GPIO_PA6_U2RX 0x00001801 -#define GPIO_PA6_I2C6SCL 0x00001802 -#define GPIO_PA6_T3CCP0 0x00001803 -#define GPIO_PA6_USB0EPEN 0x00001805 -#define GPIO_PA6_SSI0XDAT2 0x0000180D -#define GPIO_PA6_EN0RXCK 0x0000180E -#define GPIO_PA6_EPI0S8 0x0000180F - -#define GPIO_PA7_U2TX 0x00001C01 -#define GPIO_PA7_I2C6SDA 0x00001C02 -#define GPIO_PA7_T3CCP1 0x00001C03 -#define GPIO_PA7_USB0PFLT 0x00001C05 -#define GPIO_PA7_USB0EPEN 0x00001C0B -#define GPIO_PA7_SSI0XDAT3 0x00001C0D -#define GPIO_PA7_EPI0S9 0x00001C0F - -#define GPIO_PB0_U1RX 0x00010001 -#define GPIO_PB0_I2C5SCL 0x00010002 -#define GPIO_PB0_CAN1RX 0x00010007 -#define GPIO_PB0_T4CCP0 0x00010003 - -#define GPIO_PB1_U1TX 0x00010401 -#define GPIO_PB1_I2C5SDA 0x00010402 -#define GPIO_PB1_CAN1TX 0x00010407 -#define GPIO_PB1_T4CCP1 0x00010403 - -#define GPIO_PB2_T5CCP0 0x00010803 -#define GPIO_PB2_I2C0SCL 0x00010802 -#define GPIO_PB2_EN0MDC 0x00010805 -#define GPIO_PB2_USB0STP 0x0001080E -#define GPIO_PB2_EPI0S27 0x0001080F - -#define GPIO_PB3_I2C0SDA 0x00010C02 -#define GPIO_PB3_T5CCP1 0x00010C03 -#define GPIO_PB3_EN0MDIO 0x00010C05 -#define GPIO_PB3_USB0CLK 0x00010C0E -#define GPIO_PB3_EPI0S28 0x00010C0F - -#define GPIO_PB4_U0CTS 0x00011001 -#define GPIO_PB4_I2C5SCL 0x00011002 -#define GPIO_PB4_SSI1FSS 0x0001100F - -#define GPIO_PB5_U0RTS 0x00011401 -#define GPIO_PB5_I2C5SDA 0x00011402 -#define GPIO_PB5_SSI1CLK 0x0001140F - -#define GPIO_PB6_I2C6SCL 0x00011802 -#define GPIO_PB6_T6CCP0 0x00011803 - -#define GPIO_PB7_I2C6SDA 0x00011C02 -#define GPIO_PB7_T6CCP1 0x00011C03 - -#define GPIO_PC0_TCK 0x00020001 -#define GPIO_PC0_SWCLK 0x00020001 - -#define GPIO_PC1_TMS 0x00020401 -#define GPIO_PC1_SWDIO 0x00020401 - -#define GPIO_PC2_TDI 0x00020801 - -#define GPIO_PC3_SWO 0x00020C01 -#define GPIO_PC3_TDO 0x00020C01 - -#define GPIO_PC4_U7RX 0x00021001 -#define GPIO_PC4_T7CCP0 0x00021003 -#define GPIO_PC4_EPI0S7 0x0002100F - -#define GPIO_PC5_U7TX 0x00021401 -#define GPIO_PC5_T7CCP1 0x00021403 -#define GPIO_PC5_RTCCLK 0x00021407 -#define GPIO_PC5_EPI0S6 0x0002140F - -#define GPIO_PC6_U5RX 0x00021801 -#define GPIO_PC6_EPI0S5 0x0002180F - -#define GPIO_PC7_U5TX 0x00021C01 -#define GPIO_PC7_EPI0S4 0x00021C0F - -#define GPIO_PD0_I2C7SCL 0x00030002 -#define GPIO_PD0_T0CCP0 0x00030003 -#define GPIO_PD0_C0O 0x00030005 -#define GPIO_PD0_SSI2XDAT1 0x0003000F - -#define GPIO_PD1_I2C7SDA 0x00030402 -#define GPIO_PD1_T0CCP1 0x00030403 -#define GPIO_PD1_C1O 0x00030405 -#define GPIO_PD1_SSI2XDAT0 0x0003040F - -#define GPIO_PD2_I2C8SCL 0x00030802 -#define GPIO_PD2_T1CCP0 0x00030803 -#define GPIO_PD2_C2O 0x00030805 -#define GPIO_PD2_SSI2FSS 0x0003080F - -#define GPIO_PD3_I2C8SDA 0x00030C02 -#define GPIO_PD3_T1CCP1 0x00030C03 -#define GPIO_PD3_SSI2CLK 0x00030C0F - -#define GPIO_PD4_U2RX 0x00031001 -#define GPIO_PD4_T3CCP0 0x00031003 -#define GPIO_PD4_SSI1XDAT2 0x0003100F - -#define GPIO_PD5_U2TX 0x00031401 -#define GPIO_PD5_T3CCP1 0x00031403 -#define GPIO_PD5_SSI1XDAT3 0x0003140F - -#define GPIO_PD6_U2RTS 0x00031801 -#define GPIO_PD6_T4CCP0 0x00031803 -#define GPIO_PD6_USB0EPEN 0x00031805 -#define GPIO_PD6_SSI2XDAT3 0x0003180F - -#define GPIO_PD7_U2CTS 0x00031C01 -#define GPIO_PD7_T4CCP1 0x00031C03 -#define GPIO_PD7_USB0PFLT 0x00031C05 -#define GPIO_PD7_NMI 0x00031C08 -#define GPIO_PD7_SSI2XDAT2 0x00031C0F - -#define GPIO_PE0_U1RTS 0x00040001 - -#define GPIO_PE1_U1DSR 0x00040401 - -#define GPIO_PE2_U1DCD 0x00040801 - -#define GPIO_PE3_U1DTR 0x00040C01 -#define GPIO_PE3_OWIRE 0x00040C05 - -#define GPIO_PE4_U1RI 0x00041001 -#define GPIO_PE4_SSI1XDAT0 0x0004100F - -#define GPIO_PE5_SSI1XDAT1 0x0004140F - -#define GPIO_PE6_U0CTS 0x00041801 -#define GPIO_PE6_I2C9SCL 0x00041802 - -#define GPIO_PE7_U0RTS 0x00041C01 -#define GPIO_PE7_I2C9SDA 0x00041C02 -#define GPIO_PE7_NMI 0x00041C08 - -#define GPIO_PF0_EN0LED0 0x00050005 -#define GPIO_PF0_M0PWM0 0x00050006 -#define GPIO_PF0_SSI3XDAT1 0x0005000E -#define GPIO_PF0_TRD2 0x0005000F - -#define GPIO_PF1_EN0LED2 0x00050405 -#define GPIO_PF1_M0PWM1 0x00050406 -#define GPIO_PF1_SSI3XDAT0 0x0005040E -#define GPIO_PF1_TRD1 0x0005040F - -#define GPIO_PF2_EN0MDC 0x00050805 -#define GPIO_PF2_M0PWM2 0x00050806 -#define GPIO_PF2_SSI3FSS 0x0005080E -#define GPIO_PF2_TRD0 0x0005080F - -#define GPIO_PF3_EN0MDIO 0x00050C05 -#define GPIO_PF3_M0PWM3 0x00050C06 -#define GPIO_PF3_SSI3CLK 0x00050C0E -#define GPIO_PF3_TRCLK 0x00050C0F - -#define GPIO_PF4_EN0LED1 0x00051005 -#define GPIO_PF4_M0FAULT0 0x00051006 -#define GPIO_PF4_SSI3XDAT2 0x0005100E -#define GPIO_PF4_TRD3 0x0005100F - -#define GPIO_PF5_SSI3XDAT3 0x0005140E - -#define GPIO_PF6_LCDMCLK 0x0005180F - -#define GPIO_PF7_LCDDATA02 0x00051C0F - -#define GPIO_PG0_I2C1SCL 0x00060002 -#define GPIO_PG0_EN0PPS 0x00060005 -#define GPIO_PG0_M0PWM4 0x00060006 -#define GPIO_PG0_EPI0S11 0x0006000F - -#define GPIO_PG1_I2C1SDA 0x00060402 -#define GPIO_PG1_M0PWM5 0x00060406 -#define GPIO_PG1_EPI0S10 0x0006040F - -#define GPIO_PG2_I2C2SCL 0x00060802 -#define GPIO_PG2_EN0TXCK 0x0006080E -#define GPIO_PG2_SSI2XDAT3 0x0006080F - -#define GPIO_PG3_I2C2SDA 0x00060C02 -#define GPIO_PG3_EN0TXEN 0x00060C0E -#define GPIO_PG3_SSI2XDAT2 0x00060C0F - -#define GPIO_PG4_U0CTS 0x00061001 -#define GPIO_PG4_I2C3SCL 0x00061002 -#define GPIO_PG4_OWIRE 0x00061005 -#define GPIO_PG4_EN0TXD0 0x0006100E -#define GPIO_PG4_SSI2XDAT1 0x0006100F - -#define GPIO_PG5_U0RTS 0x00061401 -#define GPIO_PG5_I2C3SDA 0x00061402 -#define GPIO_PG5_OWALT 0x00061405 -#define GPIO_PG5_EN0TXD1 0x0006140E -#define GPIO_PG5_SSI2XDAT0 0x0006140F - -#define GPIO_PG6_I2C4SCL 0x00061802 -#define GPIO_PG6_OWIRE 0x00061805 -#define GPIO_PG6_EN0RXER 0x0006180E -#define GPIO_PG6_SSI2FSS 0x0006180F - -#define GPIO_PG7_I2C4SDA 0x00061C02 -#define GPIO_PG7_OWIRE 0x00061C05 -#define GPIO_PG7_EN0RXDV 0x00061C0E -#define GPIO_PG7_SSI2CLK 0x00061C0F - -#define GPIO_PH0_U0RTS 0x00070001 -#define GPIO_PH0_EPI0S0 0x0007000F - -#define GPIO_PH1_U0CTS 0x00070401 -#define GPIO_PH1_EPI0S1 0x0007040F - -#define GPIO_PH2_U0DCD 0x00070801 -#define GPIO_PH2_EPI0S2 0x0007080F - -#define GPIO_PH3_U0DSR 0x00070C01 -#define GPIO_PH3_EPI0S3 0x00070C0F - -#define GPIO_PH4_U0DTR 0x00071001 - -#define GPIO_PH5_U0RI 0x00071401 -#define GPIO_PH5_EN0PPS 0x00071405 - -#define GPIO_PH6_U5RX 0x00071801 -#define GPIO_PH6_U7RX 0x00071802 - -#define GPIO_PH7_U5TX 0x00071C01 -#define GPIO_PH7_U7TX 0x00071C02 - -#define GPIO_PJ0_U3RX 0x00080001 -#define GPIO_PJ0_EN0PPS 0x00080005 - -#define GPIO_PJ1_U3TX 0x00080401 - -#define GPIO_PJ2_U2RTS 0x00080801 -#define GPIO_PJ2_LCDDATA14 0x0008080F - -#define GPIO_PJ3_U2CTS 0x00080C01 -#define GPIO_PJ3_LCDDATA15 0x00080C0F - -#define GPIO_PJ4_U3RTS 0x00081001 -#define GPIO_PJ4_LCDDATA16 0x0008100F - -#define GPIO_PJ5_U3CTS 0x00081401 -#define GPIO_PJ5_LCDDATA17 0x0008140F - -#define GPIO_PJ6_U4RTS 0x00081801 -#define GPIO_PJ6_LCDAC 0x0008180F - -#define GPIO_PJ7_U4CTS 0x00081C01 - -#define GPIO_PK0_U4RX 0x00090001 -#define GPIO_PK0_EPI0S0 0x0009000F - -#define GPIO_PK1_U4TX 0x00090401 -#define GPIO_PK1_EPI0S1 0x0009040F - -#define GPIO_PK2_U4RTS 0x00090801 -#define GPIO_PK2_EPI0S2 0x0009080F - -#define GPIO_PK3_U4CTS 0x00090C01 -#define GPIO_PK3_EPI0S3 0x00090C0F - -#define GPIO_PK4_I2C3SCL 0x00091002 -#define GPIO_PK4_EN0LED0 0x00091005 -#define GPIO_PK4_M0PWM6 0x00091006 -#define GPIO_PK4_EN0INTRN 0x00091007 -#define GPIO_PK4_EN0RXD3 0x0009100E -#define GPIO_PK4_EPI0S32 0x0009100F - -#define GPIO_PK5_I2C3SDA 0x00091402 -#define GPIO_PK5_EN0LED2 0x00091405 -#define GPIO_PK5_M0PWM7 0x00091406 -#define GPIO_PK5_EN0RXD2 0x0009140E -#define GPIO_PK5_EPI0S31 0x0009140F - -#define GPIO_PK6_I2C4SCL 0x00091802 -#define GPIO_PK6_EN0LED1 0x00091805 -#define GPIO_PK6_M0FAULT1 0x00091806 -#define GPIO_PK6_EN0TXD2 0x0009180E -#define GPIO_PK6_EPI0S25 0x0009180F - -#define GPIO_PK7_U0RI 0x00091C01 -#define GPIO_PK7_I2C4SDA 0x00091C02 -#define GPIO_PK7_RTCCLK 0x00091C05 -#define GPIO_PK7_M0FAULT2 0x00091C06 -#define GPIO_PK7_EN0TXD3 0x00091C0E -#define GPIO_PK7_EPI0S24 0x00091C0F - -#define GPIO_PL0_I2C2SDA 0x000A0002 -#define GPIO_PL0_M0FAULT3 0x000A0006 -#define GPIO_PL0_USB0D0 0x000A000E -#define GPIO_PL0_EPI0S16 0x000A000F - -#define GPIO_PL1_I2C2SCL 0x000A0402 -#define GPIO_PL1_PHA0 0x000A0406 -#define GPIO_PL1_USB0D1 0x000A040E -#define GPIO_PL1_EPI0S17 0x000A040F - -#define GPIO_PL2_C0O 0x000A0805 -#define GPIO_PL2_PHB0 0x000A0806 -#define GPIO_PL2_USB0D2 0x000A080E -#define GPIO_PL2_EPI0S18 0x000A080F - -#define GPIO_PL3_C1O 0x000A0C05 -#define GPIO_PL3_IDX0 0x000A0C06 -#define GPIO_PL3_USB0D3 0x000A0C0E -#define GPIO_PL3_EPI0S19 0x000A0C0F - -#define GPIO_PL4_T0CCP0 0x000A1003 -#define GPIO_PL4_USB0D4 0x000A100E -#define GPIO_PL4_EPI0S26 0x000A100F - -#define GPIO_PL5_T0CCP1 0x000A1403 -#define GPIO_PL5_EPI0S33 0x000A140F -#define GPIO_PL5_USB0D5 0x000A140E - -#define GPIO_PL6_T1CCP0 0x000A1803 - -#define GPIO_PL7_T1CCP1 0x000A1C03 - -#define GPIO_PM0_T2CCP0 0x000B0003 -#define GPIO_PM0_EPI0S15 0x000B000F - -#define GPIO_PM1_T2CCP1 0x000B0403 -#define GPIO_PM1_EPI0S14 0x000B040F - -#define GPIO_PM2_T3CCP0 0x000B0803 -#define GPIO_PM2_EPI0S13 0x000B080F - -#define GPIO_PM3_T3CCP1 0x000B0C03 -#define GPIO_PM3_EPI0S12 0x000B0C0F - -#define GPIO_PM4_U0CTS 0x000B1001 -#define GPIO_PM4_T4CCP0 0x000B1003 -#define GPIO_PM4_EN0RREF_CLK 0x000B100E - -#define GPIO_PM5_U0DCD 0x000B1401 -#define GPIO_PM5_T4CCP1 0x000B1403 - -#define GPIO_PM6_U0DSR 0x000B1801 -#define GPIO_PM6_T5CCP0 0x000B1803 -#define GPIO_PM6_EN0CRS 0x000B180E - -#define GPIO_PM7_U0RI 0x000B1C01 -#define GPIO_PM7_T5CCP1 0x000B1C03 -#define GPIO_PM7_EN0COL 0x000B1C0E - -#define GPIO_PN0_U1RTS 0x000C0001 - -#define GPIO_PN1_U1CTS 0x000C0401 - -#define GPIO_PN2_U1DCD 0x000C0801 -#define GPIO_PN2_U2RTS 0x000C0802 -#define GPIO_PN2_EPI0S29 0x000C080F - -#define GPIO_PN3_U1DSR 0x000C0C01 -#define GPIO_PN3_U2CTS 0x000C0C02 -#define GPIO_PN3_EPI0S30 0x000C0C0F - -#define GPIO_PN4_U1DTR 0x000C1001 -#define GPIO_PN4_U3RTS 0x000C1002 -#define GPIO_PN4_I2C2SDA 0x000C1003 -#define GPIO_PN4_EPI0S34 0x000C100F - -#define GPIO_PN5_U1RI 0x000C1401 -#define GPIO_PN5_U3CTS 0x000C1402 -#define GPIO_PN5_I2C2SCL 0x000C1403 -#define GPIO_PN5_EPI0S35 0x000C140F - -#define GPIO_PN6_U4RTS 0x000C1802 -#define GPIO_PN6_EN0TXER 0x000C180E -#define GPIO_PN6_LCDDATA13 0x000C180F - -#define GPIO_PN7_U1RTS 0x000C1C01 -#define GPIO_PN7_U4CTS 0x000C1C02 -#define GPIO_PN7_LCDDATA12 0x000C1C0F - -#define GPIO_PP0_U6RX 0x000D0001 -#define GPIO_PP0_T6CCP0 0x000D0005 -#define GPIO_PP0_EN0INTRN 0x000D0007 -#define GPIO_PP0_SSI3XDAT2 0x000D000F - -#define GPIO_PP1_U6TX 0x000D0401 -#define GPIO_PP1_T6CCP1 0x000D0405 -#define GPIO_PP1_SSI3XDAT3 0x000D040F - -#define GPIO_PP2_U0DTR 0x000D0801 -#define GPIO_PP2_USB0NXT 0x000D080E -#define GPIO_PP2_EPI0S29 0x000D080F - -#define GPIO_PP3_U1CTS 0x000D0C01 -#define GPIO_PP3_U0DCD 0x000D0C02 -#define GPIO_PP3_RTCCLK 0x000D0C07 -#define GPIO_PP3_USB0DIR 0x000D0C0E -#define GPIO_PP3_EPI0S30 0x000D0C0F - -#define GPIO_PP4_U3RTS 0x000D1001 -#define GPIO_PP4_U0DSR 0x000D1002 -#define GPIO_PP4_OWIRE 0x000D1004 -#define GPIO_PP4_USB0D7 0x000D100E - -#define GPIO_PP5_U3CTS 0x000D1401 -#define GPIO_PP5_I2C2SCL 0x000D1402 -#define GPIO_PP5_OWALT 0x000D1404 -#define GPIO_PP5_USB0D6 0x000D140E - -#define GPIO_PP6_U1DCD 0x000D1801 -#define GPIO_PP6_I2C2SDA 0x000D1802 - -#define GPIO_PP7_OWIRE 0x000D1C05 - -#define GPIO_PQ0_T6CCP0 0x000E0003 -#define GPIO_PQ0_SSI3CLK 0x000E000E -#define GPIO_PQ0_EPI0S20 0x000E000F - -#define GPIO_PQ1_T6CCP1 0x000E0403 -#define GPIO_PQ1_SSI3FSS 0x000E040E -#define GPIO_PQ1_EPI0S21 0x000E040F - -#define GPIO_PQ2_T7CCP0 0x000E0803 -#define GPIO_PQ2_SSI3XDAT0 0x000E080E -#define GPIO_PQ2_EPI0S22 0x000E080F - -#define GPIO_PQ3_T7CCP1 0x000E0C03 -#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E -#define GPIO_PQ3_EPI0S23 0x000E0C0F - -#define GPIO_PQ4_U1RX 0x000E1001 -#define GPIO_PQ4_DIVSCLK 0x000E1007 - -#define GPIO_PQ5_U1TX 0x000E1401 -#define GPIO_PQ5_EN0RXD0 0x000E140E - -#define GPIO_PQ6_U1DTR 0x000E1801 -#define GPIO_PQ6_EN0RXD1 0x000E180E - -#define GPIO_PQ7_U1RI 0x000E1C01 - -#define GPIO_PR0_U4TX 0x000F0001 -#define GPIO_PR0_I2C1SCL 0x000F0002 -#define GPIO_PR0_M0PWM0 0x000F0006 -#define GPIO_PR0_LCDCP 0x000F000F - -#define GPIO_PR1_U4RX 0x000F0401 -#define GPIO_PR1_I2C1SDA 0x000F0402 -#define GPIO_PR1_M0PWM1 0x000F0406 -#define GPIO_PR1_LCDFP 0x000F040F - -#define GPIO_PR2_I2C2SCL 0x000F0802 -#define GPIO_PR2_M0PWM2 0x000F0806 -#define GPIO_PR2_LCDLP 0x000F080F - -#define GPIO_PR3_I2C2SDA 0x000F0C02 -#define GPIO_PR3_M0PWM3 0x000F0C06 -#define GPIO_PR3_LCDDATA03 0x000F0C0F - -#define GPIO_PR4_I2C3SCL 0x000F1002 -#define GPIO_PR4_T0CCP0 0x000F1003 -#define GPIO_PR4_M0PWM4 0x000F1006 -#define GPIO_PR4_LCDDATA00 0x000F100F - -#define GPIO_PR5_U1RX 0x000F1401 -#define GPIO_PR5_I2C3SDA 0x000F1402 -#define GPIO_PR5_T0CCP1 0x000F1403 -#define GPIO_PR5_M0PWM5 0x000F1406 -#define GPIO_PR5_LCDDATA01 0x000F140F - -#define GPIO_PR6_U1TX 0x000F1801 -#define GPIO_PR6_I2C4SCL 0x000F1802 -#define GPIO_PR6_T1CCP0 0x000F1803 -#define GPIO_PR6_M0PWM6 0x000F1806 -#define GPIO_PR6_LCDDATA04 0x000F180F - -#define GPIO_PR7_I2C4SDA 0x000F1C02 -#define GPIO_PR7_T1CCP1 0x000F1C03 -#define GPIO_PR7_M0PWM7 0x000F1C06 -#define GPIO_PR7_EN0TXEN 0x000F1C0E -#define GPIO_PR7_LCDDATA05 0x000F1C0F - -#define GPIO_PS0_T2CCP0 0x00100003 -#define GPIO_PS0_M0FAULT0 0x00100006 -#define GPIO_PS0_LCDDATA20 0x0010000F - -#define GPIO_PS1_T2CCP1 0x00100403 -#define GPIO_PS1_M0FAULT1 0x00100406 -#define GPIO_PS1_LCDDATA21 0x0010040F - -#define GPIO_PS2_U1DSR 0x00100801 -#define GPIO_PS2_T3CCP0 0x00100803 -#define GPIO_PS2_M0FAULT2 0x00100806 -#define GPIO_PS2_LCDDATA22 0x0010080F - -#define GPIO_PS3_T3CCP1 0x00100C03 -#define GPIO_PS3_M0FAULT3 0x00100C06 -#define GPIO_PS3_LCDDATA23 0x00100C0F - -#define GPIO_PS4_T4CCP0 0x00101003 -#define GPIO_PS4_PHA0 0x00101006 -#define GPIO_PS4_EN0TXD0 0x0010100E -#define GPIO_PS4_LCDDATA06 0x0010100F - -#define GPIO_PS5_T4CCP1 0x00101403 -#define GPIO_PS5_PHB0 0x00101406 -#define GPIO_PS5_EN0TXD1 0x0010140E -#define GPIO_PS5_LCDDATA07 0x0010140F - -#define GPIO_PS6_T5CCP0 0x00101803 -#define GPIO_PS6_IDX0 0x00101806 -#define GPIO_PS6_EN0RXER 0x0010180E -#define GPIO_PS6_LCDDATA08 0x0010180F - -#define GPIO_PS7_T5CCP1 0x00101C03 -#define GPIO_PS7_EN0RXDV 0x00101C0E -#define GPIO_PS7_LCDDATA09 0x00101C0F - -#define GPIO_PT0_T6CCP0 0x00110003 -#define GPIO_PT0_CAN0RX 0x00110007 -#define GPIO_PT0_EN0RXD0 0x0011000E -#define GPIO_PT0_LCDDATA10 0x0011000F - -#define GPIO_PT1_T6CCP1 0x00110403 -#define GPIO_PT1_CAN0TX 0x00110407 -#define GPIO_PT1_EN0RXD1 0x0011040E -#define GPIO_PT1_LCDDATA11 0x0011040F - -#define GPIO_PT2_T7CCP0 0x00110803 -#define GPIO_PT2_CAN1RX 0x00110807 -#define GPIO_PT2_LCDDATA18 0x0011080F - -#define GPIO_PT3_T7CCP1 0x00110C03 -#define GPIO_PT3_CAN1TX 0x00110C07 -#define GPIO_PT3_LCDDATA19 0x00110C0F - -#endif // PART_TM4C129XNCZAD - -#endif // __DRIVERLIB_PIN_MAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/pwm.c b/bsp/tm4c129x-dk/libraries/driverlib/pwm.c deleted file mode 100644 index 54fbe52e5c..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/pwm.c +++ /dev/null @@ -1,2162 +0,0 @@ -//***************************************************************************** -// -// pwm.c - API for the PWM modules -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup pwm_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_pwm.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/pwm.h" - -//***************************************************************************** -// -// Misc macros for manipulating the encoded generator and output defines used -// by the API. -// -//***************************************************************************** -#define PWM_GEN_BADDR(_mod_, _gen_) \ - ((_mod_) + (_gen_)) -#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \ - ((_mod_) + PWM_GEN_EXT_0 + \ - ((_gen_) - PWM_GEN_0) * 2) -#define PWM_OUT_BADDR(_mod_, _out_) \ - ((_mod_) + ((_out_) & 0xFFFFFFC0)) -#define PWM_IS_OUTPUT_ODD(_out_) \ - ((_out_) & 0x00000001) - -//***************************************************************************** -// -//! \internal -//! Checks a PWM generator number. -//! -//! \param ui32Gen is the generator number. -//! -//! This function determines if a PWM generator number is valid. -//! -//! \return Returnes \b true if the generator number is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_PWMGenValid(uint32_t ui32Gen) -{ - return((ui32Gen == PWM_GEN_0) || (ui32Gen == PWM_GEN_1) || - (ui32Gen == PWM_GEN_2) || (ui32Gen == PWM_GEN_3)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Checks a PWM output number. -//! -//! \param ui32PWMOut is the output number. -//! -//! This function determines if a PWM output number is valid. -//! -//! \return Returns \b true if the output number is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_PWMOutValid(uint32_t ui32PWMOut) -{ - return((ui32PWMOut == PWM_OUT_0) || (ui32PWMOut == PWM_OUT_1) || - (ui32PWMOut == PWM_OUT_2) || (ui32PWMOut == PWM_OUT_3) || - (ui32PWMOut == PWM_OUT_4) || (ui32PWMOut == PWM_OUT_5) || - (ui32PWMOut == PWM_OUT_6) || (ui32PWMOut == PWM_OUT_7)); -} -#endif - -//***************************************************************************** -// -//! Configures a PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to configure. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Config is the configuration for the PWM generator. -//! -//! This function is used to set the mode of operation for a PWM generator. -//! The counting mode, synchronization mode, and debug behavior are all -//! configured. After configuration, the generator is left in the disabled -//! state. -//! -//! A PWM generator can count in two different modes: count down mode or count -//! up/down mode. In count down mode, it counts from a value down to zero, -//! and then resets to the preset value, producing left-aligned PWM -//! signals (that is, the rising edge of the two PWM signals produced by the -//! generator occur at the same time). In count up/down mode, it counts up -//! from zero to the preset value, counts back down to zero, and then repeats -//! the process, producing center-aligned PWM signals (that is, -//! the middle of the high/low period of the PWM signals produced by the -//! generator occurs at the same time). -//! -//! When the PWM generator parameters (period and pulse width) are modified, -//! their effect on the output PWM signals can be delayed. In synchronous -//! mode, the parameter updates are not applied until a synchronization event -//! occurs. This mode allows multiple parameters to be modified and take -//! effect simultaneously, instead of one at a time. Additionally, parameters -//! to multiple PWM generators in synchronous mode can be updated -//! simultaneously, allowing them to be treated as if they were a unified -//! generator. In non-synchronous mode, the parameter updates are not delayed -//! until a synchronization event. In either mode, the parameter updates only -//! occur when the counter is at zero to help prevent oddly formed PWM signals -//! during the update (that is, a PWM pulse that is too short or too long). -//! -//! The PWM generator can either pause or continue running when the processor -//! is stopped via the debugger. If configured to pause, it continues to -//! count until it reaches zero, at which point it pauses until the -//! processor is restarted. If configured to continue running, it keeps -//! counting as if nothing had happened. -//! -//! The \e ui32Config parameter contains the desired configuration. It is the -//! logical OR of the following: -//! -//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting -//! mode -//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter -//! load and comparator update synchronization mode -//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug -//! behavior -//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or -//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization -//! mode for generator counting mode changes -//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or -//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter -//! synchronization mode -//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to -//! specify whether fault conditions are latched or not -//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to -//! specify whether minimum fault period support is required -//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify -//! whether extended fault source selection support is enabled or not -//! -//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the -//! minimum duration of a PWM fault signal. Faults are signaled for at -//! least this time even if the external fault pin deasserts earlier. Care -//! should be taken when using this mode because during the fault signal -//! period, the fault interrupt from the PWM generator remains asserted. The -//! fault interrupt handler may, therefore, reenter immediately if it exits -//! prior to expiration of the fault timer. -//! -//! \note Changes to the counter mode affect the period of the PWM signals -//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after -//! any changes to the counter mode of a generator. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Change the global configuration of the generator. - // - HWREG(ui32Gen + PWM_O_X_CTL) = ((HWREG(ui32Gen + PWM_O_X_CTL) & - ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | - PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER | - PWM_X_CTL_FLTSRC | - PWM_X_CTL_DBFALLUPD_M | - PWM_X_CTL_DBRISEUPD_M | - PWM_X_CTL_DBCTLUPD_M | - PWM_X_CTL_GENBUPD_M | - PWM_X_CTL_GENAUPD_M | - PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | - PWM_X_CTL_CMPBUPD)) | ui32Config); - - // - // Set the individual PWM generator controls. - // - if(ui32Config & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the signal high on up count comparison - // and low on down count comparison (that is, center align the - // signals). - // - HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE | - PWM_X_GENA_ACTCMPAD_ZERO); - HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE | - PWM_X_GENB_ACTCMPBD_ZERO); - } - else - { - // - // In down count mode, set the signal high on load and low on count - // comparison (that is, left align the signals). - // - HWREG(ui32Gen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE | - PWM_X_GENA_ACTCMPAD_ZERO); - HWREG(ui32Gen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE | - PWM_X_GENB_ACTCMPBD_ZERO); - } -} - -//***************************************************************************** -// -//! Sets the period of a PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to be modified. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Period specifies the period of PWM generator output, measured -//! in clock ticks. -//! -//! This function sets the period of the specified PWM generator block, where -//! the period of the generator block is defined as the number of PWM clock -//! ticks between pulses on the generator block zero signal. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Period) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Set the reload register based on the mode. - // - if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the reload register to half the requested - // period. - // - ASSERT((ui32Period / 2) < 65536); - HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period / 2; - } - else - { - // - // In down count mode, set the reload register to the requested period - // minus one. - // - ASSERT((ui32Period <= 65536) && (ui32Period != 0)); - HWREG(ui32Gen + PWM_O_X_LOAD) = ui32Period - 1; - } -} - -//***************************************************************************** -// -//! Gets the period of a PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to query. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function gets the period of the specified PWM generator block. The -//! period of the generator block is defined as the number of PWM clock ticks -//! between pulses on the generator block zero signal. -//! -//! If the update of the counter for the specified PWM generator has yet -//! to be completed, the value returned may not be the active period. The -//! value returned is the programmed period, measured in PWM clock ticks. -//! -//! \return Returns the programmed period of the specified generator block -//! in PWM clock ticks. -// -//***************************************************************************** -uint32_t -PWMGenPeriodGet(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Figure out the counter mode. - // - if(HWREG(ui32Gen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // The period is twice the reload register value. - // - return(HWREG(ui32Gen + PWM_O_X_LOAD) * 2); - } - else - { - // - // The period is the reload register value plus one. - // - return(HWREG(ui32Gen + PWM_O_X_LOAD) + 1); - } -} - -//***************************************************************************** -// -//! Enables the timer/counter for a PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to be enabled. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function allows the PWM clock to drive the timer/counter for the -//! specified generator block. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Enable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the timer/counter for a PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to be disabled. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function blocks the PWM clock from driving the timer/counter for the -//! specified generator block. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Disable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_CTL) &= - ~(PWM_X_CTL_ENABLE); -} - -//***************************************************************************** -// -//! Sets the pulse width for the specified PWM output. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOut is the PWM output to modify. This parameter must be one -//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, -//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. -//! \param ui32Width specifies the width of the positive portion of the pulse. -//! -//! This function sets the pulse width for the specified PWM output, where the -//! pulse width is defined as the number of PWM clock ticks. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -void -PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, - uint32_t ui32Width) -{ - uint32_t ui32GenBase, ui32Reg; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMOutValid(ui32PWMOut)); - - // - // Compute the generator's base address. - // - ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut); - - // - // If the counter is in up/down count mode, divide the width by two. - // - if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ui32Width /= 2; - } - - // - // Get the period. - // - ui32Reg = HWREG(ui32GenBase + PWM_O_X_LOAD); - - // - // Make sure the width is not too large. - // - ASSERT(ui32Width < ui32Reg); - - // - // Compute the compare value. - // - ui32Reg = ui32Reg - ui32Width; - - // - // Write to the appropriate registers. - // - if(PWM_IS_OUTPUT_ODD(ui32PWMOut)) - { - HWREG(ui32GenBase + PWM_O_X_CMPB) = ui32Reg; - } - else - { - HWREG(ui32GenBase + PWM_O_X_CMPA) = ui32Reg; - } -} - -//***************************************************************************** -// -//! Gets the pulse width of a PWM output. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOut is the PWM output to query. This parameter must be one -//! of \b PWM_OUT_0, \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, -//! \b PWM_OUT_5, \b PWM_OUT_6, or \b PWM_OUT_7. -//! -//! This function gets the currently programmed pulse width for the specified -//! PWM output. If the update of the comparator for the specified output has -//! yet to be completed, the value returned may not be the active pulse width. -//! The value returned is the programmed pulse width, measured in PWM clock -//! ticks. -//! -//! \return Returns the width of the pulse in PWM clock ticks. -// -//***************************************************************************** -uint32_t -PWMPulseWidthGet(uint32_t ui32Base, uint32_t ui32PWMOut) -{ - uint32_t ui32GenBase, ui32Reg, ui32Load; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMOutValid(ui32PWMOut)); - - // - // Compute the generator's base address. - // - ui32GenBase = PWM_OUT_BADDR(ui32Base, ui32PWMOut); - - // - // Then compute the pulse width. If mode is UpDown, set - // width = (load - compare) * 2. Otherwise, set width = load - compare. - // - ui32Load = HWREG(ui32GenBase + PWM_O_X_LOAD); - if(PWM_IS_OUTPUT_ODD(ui32PWMOut)) - { - ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPB); - } - else - { - ui32Reg = HWREG(ui32GenBase + PWM_O_X_CMPA); - } - ui32Reg = ui32Load - ui32Reg; - - // - // If in up/down count mode, double the pulse width. - // - if(HWREG(ui32GenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ui32Reg = ui32Reg * 2; - } - - // - // Return the pulse width. - // - return(ui32Reg); -} - -//***************************************************************************** -// -//! Enables the PWM dead band output and sets the dead band delays. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to modify. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui16Rise specifies the width of delay from the rising edge. -//! \param ui16Fall specifies the width of delay from the falling edge. -//! -//! This function sets the dead bands for the specified PWM generator, where -//! the dead bands are defined as the number of \b PWM clock ticks from the -//! rising or falling edge of the generator's \b OutA signal. Note that this -//! function causes the coupling of \b OutB to \b OutA. -//! -//! \return None. -// -//***************************************************************************** -void -PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint16_t ui16Rise, uint16_t ui16Fall) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT(ui16Rise < 4096); - ASSERT(ui16Fall < 4096); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Write the dead band delay values. - // - HWREG(ui32Gen + PWM_O_X_DBRISE) = ui16Rise; - HWREG(ui32Gen + PWM_O_X_DBFALL) = ui16Fall; - - // - // Enable the deadband functionality. - // - HWREG(ui32Gen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the PWM dead band output. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to modify. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function disables the dead band mode for the specified PWM generator. -//! Doing so decouples the \b OutA and \b OutB signals. -//! -//! \return None. -// -//***************************************************************************** -void -PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Disable the deadband functionality. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_DBCTL) &= - ~(PWM_X_DBCTL_ENABLE); -} - -//***************************************************************************** -// -//! Synchronizes all pending updates. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenBits are the PWM generator blocks to be updated. This -//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, -//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. -//! -//! For the selected PWM generators, this function causes all queued updates to -//! the period or pulse width to be applied the next time the corresponding -//! counter becomes zero. -//! -//! \return None. -// -//***************************************************************************** -void -PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | - PWM_GEN_3_BIT))); - - // - // Synchronize pending PWM register changes. - // - HWREG(ui32Base + PWM_O_CTL) = ui32GenBits; -} - -//***************************************************************************** -// -//! Synchronizes the counters in one or multiple PWM generator blocks. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenBits are the PWM generator blocks to be synchronized. This -//! parameter must be the logical OR of any of \b PWM_GEN_0_BIT, -//! \b PWM_GEN_1_BIT, \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT. -//! -//! For the selected PWM module, this function synchronizes the time base of -//! the generator blocks by causing the specified generator counters to be -//! reset to zero. -//! -//! \return None. -// -//***************************************************************************** -void -PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32GenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | - PWM_GEN_3_BIT))); - - // - // Synchronize the counters in the specified generators by writing to the - // module's synchronization register. - // - HWREG(ui32Base + PWM_O_SYNC) = ui32GenBits; -} - -//***************************************************************************** -// -//! Enables or disables PWM outputs. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bEnable determines if the signal is enabled or disabled. -//! -//! This function enables or disables the selected PWM outputs. The outputs -//! are selected using the parameter \e ui32PWMOutBits. The parameter \e -//! bEnable determines the state of the selected outputs. If \e bEnable is -//! \b true, then the selected PWM outputs are enabled, or placed in the active -//! state. If \e bEnable is \b false, then the selected outputs are disabled -//! or placed in the inactive state. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bEnable) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's ENABLE output control register and set or clear the - // requested bits. - // - if(bEnable == true) - { - HWREG(ui32Base + PWM_O_ENABLE) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_ENABLE) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Selects the inversion mode for PWM outputs. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bInvert determines if the signal is inverted or passed through. -//! -//! This function is used to select the inversion mode for the selected PWM -//! outputs. The outputs are selected using the parameter \e ui32PWMOutBits. -//! The parameter \e bInvert determines the inversion mode for the selected -//! outputs. If \e bInvert is \b true, this function causes the specified -//! PWM output signals to be inverted or made active low. If \e bInvert is -//! \b false, the specified outputs are passed through as is or made active -//! high. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bInvert) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's INVERT output control register and set or clear the - // requested bits. - // - if(bInvert == true) - { - HWREG(ui32Base + PWM_O_INVERT) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_INVERT) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Specifies the level of PWM outputs suppressed in response to a fault -//! condition. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bDriveHigh determines if the signal is driven high or low during an -//! active fault condition. -//! -//! This function determines whether a PWM output pin that is suppressed in -//! response to a fault condition is driven high or low. The affected outputs -//! are selected using the parameter \e ui32PWMOutBits. The parameter -//! \e bDriveHigh determines the output level for the pins identified by -//! \e ui32PWMOutBits. If \e bDriveHigh is \b true then the selected outputs -//! are driven high when a fault is detected. If it is \e false, the pins are -//! driven low. -//! -//! In a fault condition, pins which have not been configured to be suppressed -//! via a call to PWMOutputFault() are unaffected by this function. -//! -//! \note This function is available only on devices which support extended -//! PWM fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputFaultLevel(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bDriveHigh) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's FAULT output control register and set or clear the - // requested bits. - // - if(bDriveHigh == true) - { - HWREG(ui32Base + PWM_O_FAULTVAL) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_FAULTVAL) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Specifies the state of PWM outputs in response to a fault condition. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param bFaultSuppress determines if the signal is suppressed or passed -//! through during an active fault condition. -//! -//! This function sets the fault handling characteristics of the selected PWM -//! outputs. The outputs are selected using the parameter \e ui32PWMOutBits. -//! The parameter \e bFaultSuppress determines the fault handling -//! characteristics for the selected outputs. If \e bFaultSuppress is \b true, -//! then the selected outputs are made inactive. If \e bFaultSuppress is -//! \b false, then the selected outputs are unaffected by the detected fault. -//! -//! On devices supporting extended PWM fault handling, the state the affected -//! output pins are driven to can be configured with PWMOutputFaultLevel(). If -//! not configured, or if the device does not support extended PWM fault -//! handling, affected outputs are driven low on a fault condition. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bFaultSuppress) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - - // - // Read the module's FAULT output control register and set or clear the - // requested bits. - // - if(bFaultSuppress == true) - { - HWREG(ui32Base + PWM_O_FAULT) |= ui32PWMOutBits; - } - else - { - HWREG(ui32Base + PWM_O_FAULT) &= ~(ui32PWMOutBits); - } -} - -//***************************************************************************** -// -//! Gets the PWM generator interrupt number. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator in question. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function returns the interrupt number of the corresponding PWM -//! generator. -//! -//! \return Returns the interrupt number. -// -//***************************************************************************** -static uint32_t -_PWMGenIntNumberGet(uint32_t ui32Base, uint32_t ui32Gen) -{ - // - // Determine the generator and PWM module in question. - // - switch(ui32Base + ui32Gen) - { - // - // The first PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_0: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM0_0_TM4C123); - } - else if(CLASS_IS_TM4C129) - { - return(INT_PWM0_0_TM4C129); - } - else - { - return(0); - } - } - - // - // The second PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_1: - { - if(CLASS_IS_TM4C129) - { - return(INT_PWM0_1_TM4C129); - } - else - { - return(0); - } - } - - // - // The third PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_2: - { - if(CLASS_IS_TM4C129) - { - return(INT_PWM0_2_TM4C129); - } - else - { - return(0); - } - } - - // - // The fourth PWM generator in the first PWM module. - // - case PWM0_BASE + PWM_GEN_3: - { - if(CLASS_IS_TM4C129) - { - return(INT_PWM0_3_TM4C129); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_0: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_0_TM4C123); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_1: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_1_TM4C123); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_2: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_2_TM4C123); - } - else - { - return(0); - } - } - - // - // The first PWM generator in the second PWM module. - // - case PWM1_BASE + PWM_GEN_3: - { - if(CLASS_IS_TM4C123) - { - return(INT_PWM1_3_TM4C123); - } - else - { - return(0); - } - } - - // - // An unknown PWM module/generator was specified. - // - default: - { - return(0); - } - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator in question. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! generator interrupt occurs. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected for the specified -//! PWM generator block. This function also enables the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be enabled with PWMIntEnable() and -//! PWMGenIntTrigEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, - void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Get the interrupt number associated with the specified generator. - // - ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnIntHandler); - - // - // Enable the PWMx interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator in question. This parameter must be -//! one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! -//! This function unregisters the interrupt handler for the specified -//! PWM generator block. This function also disables the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be disabled with PWMIntDisable() and -//! PWMGenIntTrigDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Get the interrupt number associated with the specified generator. - // - ui32Int = _PWMGenIntNumberGet(ui32Base, ui32Gen); - - ASSERT(ui32Int != 0); - - // - // Disable the PWMx interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Gets the PWM fault interrupt number. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function returns the fault interrupt number of the corresponding -//! PWM module. -//! -//! \return Returns the interrupt number. -// -//***************************************************************************** -static uint32_t -_PWMFaultIntNumberGet(uint32_t ui32Base) -{ - // - // Return the fault interrupt number. - // - if(CLASS_IS_TM4C123) - { - return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C123 : - INT_PWM1_FAULT_TM4C123); - } - else if(CLASS_IS_TM4C129) - { - return((ui32Base == PWM0_BASE) ? INT_PWM0_FAULT_TM4C129 : 0); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a fault condition detected in a PWM -//! module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! fault interrupt occurs. -//! -//! This function ensures that the interrupt handler specified by -//! \e pfnIntHandler is called when a fault interrupt is detected for the -//! selected PWM module. This function also enables the PWM fault -//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the -//! module level using PWMIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntRegister(uint32_t ui32Base, void (*pfnIntHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Get the interrupt number associated with the specified module. - // - ui32Int = _PWMFaultIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if one occurs. - // - IntRegister(ui32Int, pfnIntHandler); - - // - // Enable the PWM fault interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Removes the PWM fault condition interrupt handler. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function removes the interrupt handler for a PWM fault interrupt -//! from the selected PWM module. This function also disables the PWM -//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled -//! at the module level using PWMIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Get the interrupt number associated with the specified module. - // - ui32Int = _PWMFaultIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the PWM fault interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler, returning an error if one occurs. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables interrupts and triggers for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to have interrupts and triggers -//! enabled. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32IntTrig specifies the interrupts and triggers to be enabled. -//! -//! This function unmasks the specified interrupt(s) and trigger(s) by setting -//! the specified bits of the interrupt/trigger enable register for the -//! specified PWM generator. The \e ui32IntTrig parameter is the logical OR of -//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, -//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, -//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, -//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | - PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | - PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | - PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD | - PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0); - - // - // Enable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) |= ui32IntTrig; -} - -//***************************************************************************** -// -//! Disables interrupts for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to have interrupts and triggers -//! disabled. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32IntTrig specifies the interrupts and triggers to be disabled. -//! -//! This function masks the specified interrupt(s) and trigger(s) by clearing -//! the specified bits of the interrupt/trigger enable register for the -//! specified PWM generator. The \e ui32IntTrig parameter is the logical OR of -//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, -//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD, -//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD, -//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32IntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | - PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU | - PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | - PWM_TR_CNT_LOAD | PWM_TR_CNT_AU | PWM_TR_CNT_AD | - PWM_TR_CNT_BU | PWM_TR_CNT_BD)) == 0); - - // - // Disable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_INTEN) &= ~(ui32IntTrig); -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to query. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return Returns the contents of the interrupt status register or the -//! contents of the raw interrupt status register for the specified -//! PWM generator. -// -//***************************************************************************** -uint32_t -PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - - // - // Compute the generator's base address. - // - ui32Gen = PWM_GEN_BADDR(ui32Base, ui32Gen); - - // - // Read and return the specified generator's raw or enabled interrupt - // status. - // - if(bMasked == true) - { - return(HWREG(ui32Gen + PWM_O_X_ISC)); - } - else - { - return(HWREG(ui32Gen + PWM_O_X_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the specified interrupt(s) for the specified PWM generator block. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator to query. This parameter must be one -//! of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Ints specifies the interrupts to be cleared. -//! -//! This function clears the specified interrupt(s) by writing a 1 to the -//! specified bits of the interrupt status register for the specified PWM -//! generator. The \e ui32Ints parameter is the logical OR of -//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, -//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Ints) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Ints & - ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU | - PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) == 0); - - // - // Clear the requested interrupts by writing ones to the specified bit - // of the module's interrupt enable register. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_ISC) = ui32Ints; -} - -//***************************************************************************** -// -//! Enables generator and fault interrupts for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenFault contains the interrupts to be enabled. This parameter -//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, -//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, -//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. -//! -//! This function unmasks the specified interrupt(s) by setting the specified -//! bits of the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -void -PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | - PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | - PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); - - // - // Read the module's interrupt enable register and enable interrupts - // for the specified PWM generators. - // - HWREG(ui32Base + PWM_O_INTEN) |= ui32GenFault; -} - -//***************************************************************************** -// -//! Disables generator and fault interrupts for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32GenFault contains the interrupts to be disabled. This parameter -//! must be a logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, -//! \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, -//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. -//! -//! This function masks the specified interrupt(s) by clearing the specified -//! bits of the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -void -PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32GenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 | - PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 | - PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); - - // - // Read the module's interrupt enable register and disable interrupts - // for the specified PWM generators. - // - HWREG(ui32Base + PWM_O_INTEN) &= ~(ui32GenFault); -} - -//***************************************************************************** -// -//! Clears the fault interrupt for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function clears the fault interrupt by writing to the appropriate bit -//! of the interrupt status register for the selected PWM module. -//! -//! This function clears only the FAULT0 interrupt and is retained for -//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be -//! used instead because it supports all fault interrupts supported on devices -//! with and without extended PWM fault handling support. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Write the only writeable bit in the module's interrupt register. - // - HWREG(ui32Base + PWM_O_ISC) = PWM_ISC_INTFAULT0; -} - -//***************************************************************************** -// -//! Gets the interrupt status for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status is returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3, -//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and -//! \b PWM_INT_FAULT3. -//! -//***************************************************************************** -uint32_t -PWMIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Read and return either the module's raw or enabled interrupt status. - // - if(bMasked == true) - { - return(HWREG(ui32Base + PWM_O_ISC)); - } - else - { - return(HWREG(ui32Base + PWM_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the fault interrupt for a PWM module. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32FaultInts specifies the fault interrupts to clear. -//! -//! This function clears one or more fault interrupts by writing to the -//! appropriate bit of the PWM interrupt status register. The parameter -//! \e ui32FaultInts must be the logical OR of any of \b PWM_INT_FAULT0, -//! \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3. -//! -//! The fault interrupts are derived by performing a logical OR of each of the -//! configured fault trigger signals for a given generator. Therefore, these -//! interrupts are not directly related to the four possible FAULTn inputs to -//! the device but indicate that a fault has been signaled to one of the four -//! possible PWM generators. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -PWMFaultIntClearExt(uint32_t ui32Base, uint32_t ui32FaultInts) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32FaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 | - PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0); - - // - // Clear the supplied fault bits. - // - HWREG(ui32Base + PWM_O_ISC) = ui32FaultInts; -} - -//***************************************************************************** -// -//! Configures the minimum fault period and fault pin senses for a given -//! PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault configuration is being -//! set. This function must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32MinFaultPeriod is the minimum fault active period expressed in -//! PWM clock cycles. -//! \param ui32FaultSenses indicates which sense of each FAULT input should be -//! considered the ``asserted'' state. Valid values are logical OR -//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW. -//! -//! This function configures the minimum fault period for a given generator -//! along with the sense of each of the 4 possible fault inputs. The minimum -//! fault period is expressed in PWM clock cycles and takes effect only if -//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the -//! \e ui32Config parameter. When a fault input is asserted, the minimum fault -//! period timer ensures that it remains asserted for at least the number of -//! clock cycles specified. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32MinFaultPeriod, - uint32_t ui32FaultSenses) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT(ui32MinFaultPeriod < PWM_X_MINFLTPER_M); - ASSERT((ui32FaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW | - PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW | - PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW | - PWM_FAULT3_SENSE_HIGH | - PWM_FAULT3_SENSE_LOW)) == 0); - - // - // Write the minimum fault period. - // - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_MINFLTPER) = - ui32MinFaultPeriod; - - // - // Write the fault senses. - // - HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSEN) = - ui32FaultSenses; -} - -//***************************************************************************** -// -//! Configures the set of fault triggers for a given PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault triggers are being set. -//! This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or -//! \b PWM_GEN_3. -//! \param ui32Group indicates the subset of possible faults that are to be -//! configured. This parameter must be \b PWM_FAULT_GROUP_0 or -//! \b PWM_FAULT_GROUP_1. -//! \param ui32FaultTriggers defines the set of inputs that are to contribute -//! towards generation of the fault signal to the given PWM generator. For -//! \b PWM_FAULT_GROUP_0, this is the logical OR of \b PWM_FAULT_FAULT0, -//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. For -//! \b PWM_FAULT_GROUP_1, this is the logical OR of \b PWM_FAULT_DCMP0, -//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, -//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or -//! \b PWM_FAULT_DCMP7. -//! -//! This function allows selection of the set of fault inputs that is combined -//! to generate a fault condition to a given PWM generator. By default, all -//! generators use only FAULT0 (for backwards compatibility) but if -//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the -//! \e ui32Config parameter, extended fault handling is enabled and this -//! function must be called to configure the fault triggers. -//! -//! The fault signal to the PWM generator is generated by ORing together each -//! of the signals specified in the \e ui32FaultTriggers parameter after having -//! adjusted the sense of each FAULTn input based on the configuration -//! previously set using a call to PWMGenFaultConfigure(). -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, uint32_t ui32FaultTriggers) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) && - ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | - PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == - 0)); - ASSERT((ui32Group == PWM_FAULT_GROUP_1) && - ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | - PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | - PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | - PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); - - // - // Write the fault triggers to the appropriate register. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0) = - ui32FaultTriggers; - } - else - { - HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1) = - ui32FaultTriggers; - } -} - -//***************************************************************************** -// -//! Returns the set of fault triggers currently configured for a given PWM -//! generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault triggers are being -//! queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Group indicates the subset of faults that are being queried. -//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. -//! -//! This function allows an application to query the current set of inputs that -//! contribute to the generation of a fault condition to a given PWM generator. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return Returns the current fault triggers configured for the fault group -//! provided. For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of -//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or -//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the -//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, -//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, -//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. -// -//***************************************************************************** -uint32_t -PWMGenFaultTriggerGet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - - // - // Return the current fault triggers. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC0)); - } - else - { - return(HWREG(PWM_GEN_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSRC1)); - } -} - -//***************************************************************************** -// -//! Returns the current state of the fault triggers for a given PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault trigger states are -//! being queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Group indicates the subset of faults that are being queried. -//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. -//! -//! This function allows an application to query the current state of each of -//! the fault trigger inputs to a given PWM generator. The current state of -//! each fault trigger input is returned unless PWMGenConfigure() has -//! previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in the -//! \e ui32Config parameter, in which case the returned status is the latched -//! fault trigger status. -//! -//! If latched faults are configured, the application must call -//! PWMGenFaultClear() to clear each trigger. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return Returns the current state of the fault triggers for the given PWM -//! generator. A set bit indicates that the associated trigger is active. -//! For \b PWM_FAULT_GROUP_0, the returned value is a logical OR of -//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or -//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value is the -//! logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, -//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, -//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7. -// -//***************************************************************************** -uint32_t -PWMGenFaultStatus(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - - // - // Return the current fault status. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0)); - } - else - { - return(HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1)); - } -} - -//***************************************************************************** -// -//! Clears one or more latched fault triggers for a given PWM generator. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Gen is the PWM generator for which fault trigger states are -//! being queried. This parameter must be one of \b PWM_GEN_0, \b PWM_GEN_1, -//! \b PWM_GEN_2, or \b PWM_GEN_3. -//! \param ui32Group indicates the subset of faults that are being queried. -//! This parameter must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1. -//! \param ui32FaultTriggers is the set of fault triggers which are to be -//! cleared. -//! -//! This function allows an application to clear the fault triggers for a -//! given PWM generator. This function is only required if PWMGenConfigure() -//! has previously been called with flag \b PWM_GEN_MODE_FAULT_LATCHED in -//! parameter \e ui32Config. -//! -//! \note This function is only available on devices supporting extended PWM -//! fault handling. -//! -//! \return None. -// -//***************************************************************************** -void -PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, uint32_t ui32FaultTriggers) -{ - // - // Check for valid parameters. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(_PWMGenValid(ui32Gen)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) || - (ui32Group == PWM_FAULT_GROUP_1)); - ASSERT((ui32Group == PWM_FAULT_GROUP_0) && - ((ui32FaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 | - PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == - 0)); - ASSERT((ui32Group == PWM_FAULT_GROUP_1) && - ((ui32FaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 | - PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 | - PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 | - PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0)); - - // - // Clear the given faults. - // - if(ui32Group == PWM_FAULT_GROUP_0) - { - HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT0) = - ui32FaultTriggers; - } - else - { - HWREG(PWM_GEN_EXT_BADDR(ui32Base, ui32Gen) + PWM_O_X_FLTSTAT1) = - ui32FaultTriggers; - } -} - -//***************************************************************************** -/// -//! Sets the PWM clock configuration. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32Config is the configuration for the PWM clock; it must be one of -//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4, -//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, or -//! \b PWM_SYSCLK_DIV_64. -//! -//! This function sets the PWM clock divider as the PWM clock source. It also -//! configures the clock frequency to the PWM module as a division of the -//! system clock. This clock is used by the PWM module to generate PWM -//! signals; its rate forms the basis for all PWM signals. -//! -//! \note This function should not be used with TM4C123 devices. For -//! TM4C123 devices, the SysCtlPWMClockGet() function should be used. -//! -//! \note The clocking of the PWM is dependent upon the system clock rate as -//! configured by SysCtlClockFreqSet(). -//! -//! \return None. -// -//***************************************************************************** -void -PWMClockSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT((ui32Config == PWM_SYSCLK_DIV_2) || - (ui32Config == PWM_SYSCLK_DIV_4) || - (ui32Config == PWM_SYSCLK_DIV_8) || - (ui32Config == PWM_SYSCLK_DIV_16) || - (ui32Config == PWM_SYSCLK_DIV_32) || - (ui32Config == PWM_SYSCLK_DIV_64)); - - // - // Set the PWM clock configuration into the PWM clock configuration - // register. - // - HWREG(ui32Base + PWM_O_CC) = ((HWREG(ui32Base + PWM_O_CC) & - ~(PWM_CC_USEPWM | PWM_CC_PWMDIV_M)) | - ui32Config); -} - -//***************************************************************************** -// -//! Gets the current PWM clock configuration. -//! -//! \param ui32Base is the base address of the PWM module. -//! -//! This function returns the current PWM clock configuration. -//! -//! \note This function should not be used with TM4C123 devices. For -//! TM4C123 devices, the SysCtlPWMClockGet() function should be used. -//! -//! \return Returns the current PWM clock configuration; is one of -//! \b PWM_SYSCLK_DIV_1, \b PWM_SYSCLK_DIV_2, \b PWM_SYSCLK_DIV_4, -//! \b PWM_SYSCLK_DIV_8, \b PWM_SYSCLK_DIV_16, \b PWM_SYSCLK_DIV_32, -//! or \b PWM_SYSCLK_DIV_64. -// -//***************************************************************************** -uint32_t -PWMClockGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - - // - // Return the current PWM clock configuration. Make sure that - // PWM_SYSCLK_DIV_1 is returned in all cases where the divider is disabled. - // - if(!(HWREG(ui32Base + PWM_O_CC) & PWM_CC_USEPWM)) - { - // - // The divider is not active so reflect this in the value we return. - // - return(PWM_SYSCLK_DIV_1); - } - else - { - // - // The divider is active so directly return the masked register value. - // - return(HWREG(ui32Base + PWM_O_CC) & (PWM_CC_USEPWM | PWM_CC_PWMDIV_M)); - } -} - -//***************************************************************************** -// -//! Sets the update mode or synchronization mode to the PWM outputs. -//! -//! \param ui32Base is the base address of the PWM module. -//! \param ui32PWMOutBits are the PWM outputs to be modified. This parameter -//! must be the logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, -//! \b PWM_OUT_2_BIT, \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, -//! \b PWM_OUT_6_BIT, or \b PWM_OUT_7_BIT. -//! \param ui32Mode specifies the enable update mode to use when enabling or -//! disabling PWM outputs. -//! -//! This function sets one of three possible update modes to enable or disable -//! the requested PWM outputs. The \e ui32Mode parameter controls when changes -//! made via calls to PWMOutputState() take effect. Possible values are: -//! -//! - \b PWM_OUTPUT_MODE_NO_SYNC, which enables/disables changes to take effect -//! immediately. -//! - \b PWM_OUTPUT_MODE_SYNC_LOCAL, which causes changes to take effect when -//! the local PWM generator's count next reaches 0. -//! - \b PWM_OUTPUT_MODE_SYNC_GLOBAL, which causes changes to take effect when -//! the local PWM generator's count next reaches 0 following a call to -//! PWMSyncUpdate() which specifies the same generator in its \e ui32GenBits -//! parameter. -//! -//! \note This function is only available on Snowflake class devices. -//! -//! \return None. -// -//***************************************************************************** -void -PWMOutputUpdateMode(uint32_t ui32Base, uint32_t ui32PWMOutBits, - uint32_t ui32Mode) -{ - uint_fast8_t ui8Index; - uint32_t ui32PWMOutputMask; - uint32_t ui32UpdateValueMask; - uint32_t ui32UpdateValue; - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Base == PWM0_BASE) || (ui32Base == PWM1_BASE)); - ASSERT(!(ui32PWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT | - PWM_OUT_6_BIT | PWM_OUT_7_BIT))); - ASSERT((ui32Mode == PWM_OUTPUT_MODE_NO_SYNC) || - (ui32Mode == PWM_OUTPUT_MODE_SYNC_LOCAL) || - (ui32Mode == PWM_OUTPUT_MODE_SYNC_GLOBAL)); - - // - // Initialize the local variables - // - ui8Index = 0; - ui32PWMOutputMask = 1; - ui32UpdateValue = 0; - ui32UpdateValueMask = 0; - - // - // Loop to find out which PWM outputs are to be modified. - // - while(ui8Index < 8) - { - // - // Check if this PWM output is to be modified. - // - if(ui32PWMOutputMask & ui32PWMOutBits) - { - // - // Set the update mode value for the requested PWM output by - // writing to the appropriate field. - // - ui32UpdateValue |= ui32Mode << (ui8Index * 2); - - // - // Compute the mask for the bits to be updated. - // - ui32UpdateValueMask |= 3 << (ui8Index * 2); - } - - // - // Update the PWM output to be checked and the index. - // - ui32PWMOutputMask = ui32PWMOutputMask << 1; - ui8Index++; - } - - // - // Read the Enable Update register and mask the bits that are to be - // updated. - // - ui32Temp = ~ui32UpdateValueMask & HWREG(ui32Base + PWM_O_ENUPD); - - // - // Write the updated values to Enable Update register. - // - HWREG(ui32Base + PWM_O_ENUPD) = ui32Temp | ui32UpdateValue; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/pwm.h b/bsp/tm4c129x-dk/libraries/driverlib/pwm.h deleted file mode 100644 index c18d98acb2..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/pwm.h +++ /dev/null @@ -1,326 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_PWM_H__ -#define __DRIVERLIB_PWM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ui32Config -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode -#define PWM_GEN_MODE_FAULT_LATCHED \ - 0x00040000 // Fault is latched -#define PWM_GEN_MODE_FAULT_UNLATCHED \ - 0x00000000 // Fault is not latched -#define PWM_GEN_MODE_FAULT_MINPER \ - 0x00020000 // Enable min fault period -#define PWM_GEN_MODE_FAULT_NO_MINPER \ - 0x00000000 // Disable min fault period -#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support -#define PWM_GEN_MODE_FAULT_LEGACY \ - 0x00000000 // Disable extended fault support -#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur - // immediately -#define PWM_GEN_MODE_DB_SYNC_LOCAL \ - 0x0000A800 // Deadband updates locally - // synchronized -#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ - 0x0000FC00 // Deadband updates globally - // synchronized -#define PWM_GEN_MODE_GEN_NO_SYNC \ - 0x00000000 // Generator mode updates occur - // immediately -#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ - 0x00000280 // Generator mode updates locally - // synchronized -#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ - 0x000003C0 // Generator mode updates globally - // synchronized - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt -#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt -#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt -#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt -#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt -#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 -#define PWM_GEN_3 0x00000100 // Offset address of Gen3 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 -#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 - -#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range -#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range -#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range -#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 -#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 -#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 -#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 -#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 - -//***************************************************************************** -// -// Defines to identify each of the possible fault trigger conditions in -// PWM_FAULT_GROUP_0. -// -//***************************************************************************** -#define PWM_FAULT_GROUP_0 0 - -#define PWM_FAULT_FAULT0 0x00000001 -#define PWM_FAULT_FAULT1 0x00000002 -#define PWM_FAULT_FAULT2 0x00000004 -#define PWM_FAULT_FAULT3 0x00000008 -#define PWM_FAULT_ACMP0 0x00010000 -#define PWM_FAULT_ACMP1 0x00020000 -#define PWM_FAULT_ACMP2 0x00040000 - -//***************************************************************************** -// -// Defines to identify each of the possible fault trigger conditions in -// PWM_FAULT_GROUP_1. -// -//***************************************************************************** -#define PWM_FAULT_GROUP_1 1 - -#define PWM_FAULT_DCMP0 0x00000001 -#define PWM_FAULT_DCMP1 0x00000002 -#define PWM_FAULT_DCMP2 0x00000004 -#define PWM_FAULT_DCMP3 0x00000008 -#define PWM_FAULT_DCMP4 0x00000010 -#define PWM_FAULT_DCMP5 0x00000020 -#define PWM_FAULT_DCMP6 0x00000040 -#define PWM_FAULT_DCMP7 0x00000080 - -//***************************************************************************** -// -// Defines to identify the sense of each of the external FAULTn signals -// -//***************************************************************************** -#define PWM_FAULT0_SENSE_HIGH 0x00000000 -#define PWM_FAULT0_SENSE_LOW 0x00000001 -#define PWM_FAULT1_SENSE_HIGH 0x00000000 -#define PWM_FAULT1_SENSE_LOW 0x00000002 -#define PWM_FAULT2_SENSE_HIGH 0x00000000 -#define PWM_FAULT2_SENSE_LOW 0x00000004 -#define PWM_FAULT3_SENSE_HIGH 0x00000000 -#define PWM_FAULT3_SENSE_LOW 0x00000008 - -//***************************************************************************** -// -// Defines that can be passed to the PWMClockSet() API as the ui32Config -// parameter, and can be returned by the PWMClockGet() API. -// -//***************************************************************************** -#define PWM_SYSCLK_DIV_1 0x00000000 // PWM clock is system clock -#define PWM_SYSCLK_DIV_2 0x00000100 // PWM clock is system clock /2 -#define PWM_SYSCLK_DIV_4 0x00000101 // PWM clock is system clock /4 -#define PWM_SYSCLK_DIV_8 0x00000102 // PWM clock is system clock /8 -#define PWM_SYSCLK_DIV_16 0x00000103 // PWM clock is system clock /16 -#define PWM_SYSCLK_DIV_32 0x00000104 // PWM clock is system clock /32 -#define PWM_SYSCLK_DIV_64 0x00000105 // PWM clock is system clock /64 - -//***************************************************************************** -// -// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode -// to use when enabling or disabling outputs using PWMOutputState(). -// -//***************************************************************************** -#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately -#define PWM_OUTPUT_MODE_SYNC_LOCAL \ - 0x00000002 // Updates are locally synchronized -#define PWM_OUTPUT_MODE_SYNC_GLOBAL \ - 0x00000003 // Updates are globally synchronized - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Config); -extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Period); -extern uint32_t PWMGenPeriodGet(uint32_t ui32Base, - uint32_t ui32Gen); -extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, - uint32_t ui32Width); -extern uint32_t PWMPulseWidthGet(uint32_t ui32Base, - uint32_t ui32PWMOut); -extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint16_t ui16Rise, uint16_t ui16Fall); -extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits); -extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits); -extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bEnable); -extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bInvert); -extern void PWMOutputFaultLevel(uint32_t ui32Base, - uint32_t ui32PWMOutBits, - bool bDriveHigh); -extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, - bool bFaultSuppress); -extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen); -extern void PWMFaultIntRegister(uint32_t ui32Base, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(uint32_t ui32Base); -extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig); -extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32IntTrig); -extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, - bool bMasked); -extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Ints); -extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault); -extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault); -extern void PWMFaultIntClear(uint32_t ui32Base); -extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked); -extern void PWMFaultIntClearExt(uint32_t ui32Base, - uint32_t ui32FaultInts); -extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32MinFaultPeriod, - uint32_t ui32FaultSenses); -extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, - uint32_t ui32FaultTriggers); -extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base, - uint32_t ui32Gen, - uint32_t ui32Group); -extern uint32_t PWMGenFaultStatus(uint32_t ui32Base, - uint32_t ui32Gen, - uint32_t ui32Group); -extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, - uint32_t ui32Group, - uint32_t ui32FaultTriggers); -extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config); -extern uint32_t PWMClockGet(uint32_t ui32Base); -extern void PWMOutputUpdateMode(uint32_t ui32Base, - uint32_t ui32PWMOutBits, - uint32_t ui32Mode); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_PWM_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/qei.c b/bsp/tm4c129x-dk/libraries/driverlib/qei.c deleted file mode 100644 index b4def78493..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/qei.c +++ /dev/null @@ -1,783 +0,0 @@ -//***************************************************************************** -// -// qei.c - Driver for the Quadrature Encoder with Index. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup qei_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_qei.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/qei.h" - -//***************************************************************************** -// -//! Enables the quadrature encoder. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function enables operation of the quadrature encoder module. The -//! module must be configured before it is enabled. -//! -//! \sa QEIConfigure() -//! -//! \return None. -// -//***************************************************************************** -void -QEIEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the QEI module. - // - HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the quadrature encoder. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function disables operation of the quadrature encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the QEI module. - // - HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); -} - -//***************************************************************************** -// -//! Configures the quadrature encoder. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32Config is the configuration for the quadrature encoder. See -//! below for a description of this parameter. -//! \param ui32MaxPosition specifies the maximum position value. -//! -//! This function configures the operation of the quadrature encoder. The -//! \e ui32Config parameter provides the configuration of the encoder and is -//! the logical OR of several values: -//! -//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges -//! on channel A or on both channels A and B should be counted by the -//! position integrator and velocity accumulator. -//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the -//! position integrator should be reset when the index pulse is detected. -//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if -//! quadrature signals are being provided on ChA and ChB, or if a direction -//! signal and a clock are being provided instead. -//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals -//! provided on ChA and ChB should be swapped before being processed. -//! -//! \e ui32MaxPosition is the maximum value of the position integrator and is -//! the value used to reset the position capture when in index reset mode and -//! moving in the reverse (negative) direction. -//! -//! \return None. -// -//***************************************************************************** -void -QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxPosition) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Write the new configuration to the hardware. - // - HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & - ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | - QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | - ui32Config); - - // - // Set the maximum position. - // - HWREG(ui32Base + QEI_O_MAXPOS) = ui32MaxPosition; -} - -//***************************************************************************** -// -//! Gets the current encoder position. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the current position of the encoder. Depending upon -//! the configuration of the encoder, and the incident of an index pulse, this -//! value may or may not contain the expected data (that is, if in reset on -//! index mode, if an index pulse has not been encountered, the position -//! counter is not yet aligned with the index pulse). -//! -//! \return The current position of the encoder. -// -//***************************************************************************** -uint32_t -QEIPositionGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the current position counter. - // - return(HWREG(ui32Base + QEI_O_POS)); -} - -//***************************************************************************** -// -//! Sets the current encoder position. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32Position is the new position for the encoder. -//! -//! This function sets the current position of the encoder; the encoder -//! position is then measured relative to this value. -//! -//! \return None. -// -//***************************************************************************** -void -QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Set the position counter. - // - HWREG(ui32Base + QEI_O_POS) = ui32Position; -} - -//***************************************************************************** -// -//! Gets the current direction of rotation. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the current direction of rotation. In this case, -//! current means the most recently detected direction of the encoder; it may -//! not be presently moving but this is the direction it last moved before it -//! stopped. -//! -//! \return Returns 1 if moving in the forward direction or -1 if moving in the -//! reverse direction. -// -//***************************************************************************** -int32_t -QEIDirectionGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the direction of rotation. - // - return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); -} - -//***************************************************************************** -// -//! Gets the encoder error indicator. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the error indicator for the quadrature encoder. It -//! is an error for both of the signals of the quadrature input to change at -//! the same time. -//! -//! \return Returns \b true if an error has occurred and \b false otherwise. -// -//***************************************************************************** -bool -QEIErrorGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the error indicator. - // - return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); -} - -//***************************************************************************** -// -//! Enables the input filter. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function enables operation of the input filter in the quadrature -//! encoder module. The module must be configured before input filter is -//! enabled. -//! -//! \sa QEIFilterConfigure() and QEIEnable() -//! -//! \return None. -// -//***************************************************************************** -void -QEIFilterEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the input filter. - // - HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_FILTEN; -} - -//***************************************************************************** -// -//! Disables the input filter. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function disables operation of the input filter in the quadrature -//! encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIFilterDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the input filter. - // - HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_FILTEN); -} - -//***************************************************************************** -// -//! Configures the input filter. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32FiltCnt specifies the filter count applied to the input quadrature -//! signal before it is counted; can be one of \b QEI_FILTCNT_2, -//! \b QEI_FILTCNT_3, \b QEI_FILTCNT_4, \b QEI_FILTCNT_5, \b QEI_FILTCNT_6, -//! \b QEI_FILTCNT_7, \b QEI_FILTCNT_8, \b QEI_FILTCNT_9, \b QEI_FILTCNT_10, -//! \b QEI_FILTCNT_11, \b QEI_FILTCNT_12, \b QEI_FILTCNT_13, \b QEI_FILTCNT_14, -//! \b QEI_FILTCNT_15, \b QEI_FILTCNT_16 or \b QEI_FILTCNT_17 -//! -//! This function configures the operation of the input filter prescale count. -//! as specified by \e ui32FiltCnt before the input signals are sent to the -//! quadrature encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - ASSERT(!(ui32FiltCnt & ~(QEI_CTL_FILTCNT_M))); - - // - // Set the input filter prescale count. - // - HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & - ~(QEI_CTL_FILTCNT_M)) | ui32FiltCnt); -} - -//***************************************************************************** -// -//! Enables the velocity capture. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function enables operation of the velocity capture in the quadrature -//! encoder module. The module must be configured before velocity capture is -//! enabled. -//! -//! \sa QEIVelocityConfigure() and QEIEnable() -//! -//! \return None. -// -//***************************************************************************** -void -QEIVelocityEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the velocity capture. - // - HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_VELEN; -} - -//***************************************************************************** -// -//! Disables the velocity capture. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function disables operation of the velocity capture in the quadrature -//! encoder module. -//! -//! \return None. -// -//***************************************************************************** -void -QEIVelocityDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the velocity capture. - // - HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_VELEN); -} - -//***************************************************************************** -// -//! Configures the velocity capture. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32PreDiv specifies the predivider applied to the input quadrature -//! signal before it is counted; can be one of \b QEI_VELDIV_1, -//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16, -//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128. -//! \param ui32Period specifies the number of clock ticks over which to measure -//! the velocity; must be non-zero. -//! -//! This function configures the operation of the velocity capture portion of -//! the quadrature encoder. The position increment signal is predivided as -//! specified by \e ui32PreDiv before being accumulated by the velocity -//! capture. The divided signal is accumulated over \e ui32Period system clock -//! before being saved and resetting the accumulator. -//! -//! \return None. -// -//***************************************************************************** -void -QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, - uint32_t ui32Period) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - ASSERT(!(ui32PreDiv & ~(QEI_CTL_VELDIV_M))); - ASSERT(ui32Period != 0); - - // - // Set the velocity predivider. - // - HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & - ~(QEI_CTL_VELDIV_M)) | ui32PreDiv); - - // - // Set the timer period. - // - HWREG(ui32Base + QEI_O_LOAD) = ui32Period - 1; -} - -//***************************************************************************** -// -//! Gets the current encoder speed. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function returns the current speed of the encoder. The value returned -//! is the number of pulses detected in the specified time period; this number -//! can be multiplied by the number of time periods per second and divided by -//! the number of pulses per revolution to obtain the number of revolutions per -//! second. -//! -//! \return Returns the number of pulses captured in the given time period. -// -//***************************************************************************** -uint32_t -QEIVelocityGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return the speed capture value. - // - return(HWREG(ui32Base + QEI_O_SPEED)); -} - -//***************************************************************************** -// -//! Returns the quadrature encoder interrupt number. -//! -//! \param ui32Base is the base address of the selected quadrature encoder -//! -//! This function returns the interrupt number for the quadrature encoder with -//! the base address passed in the \e ui32Base parameter. -//! -//! \return Returns a quadrature encoder interrupt number or 0 if the interrupt -//! does not exist. -// -//***************************************************************************** -static uint32_t -_QEIIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Find the valid interrupt number for this quadrature encoder. - // - if(CLASS_IS_TM4C123) - { - if(ui32Base == QEI0_BASE) - { - ui32Int = INT_QEI0_TM4C123; - } - else - { - ui32Int = INT_QEI1_TM4C123; - } - } - else if(CLASS_IS_TM4C129) - { - if(ui32Base == QEI0_BASE) - { - ui32Int = INT_QEI0_TM4C129; - } - else - { - ui32Int = 0; - } - } - else - { - ui32Int = 0; - } - - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param pfnHandler is a pointer to the function to be called when the -//! quadrature encoder interrupt occurs. -//! -//! This function registers the handler to be called when a quadrature encoder -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific quadrature encoder interrupts must be -//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility -//! to clear the interrupt source via QEIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Determine the interrupt number based on the QEI module. - // - ui32Int = _QEIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the quadrature encoder interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! -//! This function unregisters the handler to be called when a quadrature -//! encoder interrupt occurs. This function also masks off the interrupt in -//! the interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Determine the interrupt number based on the QEI module. - // - ui32Int = _QEIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual quadrature encoder interrupt sources. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or -//! \b QEI_INTINDEX values. -//! -//! This function enables the indicated quadrature encoder interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + QEI_O_INTEN) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual quadrature encoder interrupt sources. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, -//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. -//! -//! This function disables the indicated quadrature encoder interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + QEI_O_INTEN) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the quadrature encoder -//! module. Either the raw interrupt status or the status of interrupts that -//! are allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX. -// -//***************************************************************************** -uint32_t -QEIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + QEI_O_ISC)); - } - else - { - return(HWREG(ui32Base + QEI_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears quadrature encoder interrupt sources. -//! -//! \param ui32Base is the base address of the quadrature encoder module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR, -//! \b QEI_INTTIMER, or \b QEI_INTINDEX values. -//! -//! The specified quadrature encoder interrupt sources are cleared, so that -//! they no longer assert. This function must be called in the interrupt -//! handler to keep the interrupt from being triggered again immediately upon -//! exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + QEI_O_ISC) = ui32IntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/qei.h b/bsp/tm4c129x-dk/libraries/driverlib/qei.h deleted file mode 100644 index 031897ae31..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/qei.h +++ /dev/null @@ -1,154 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_QEI_H__ -#define __DRIVERLIB_QEI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ui32Config paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIFilterConfigure as the ui32PreDiv -// parameter. -// -//***************************************************************************** -#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks -#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks -#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks -#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks -#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks -#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks -#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks -#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks -#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks -#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks -#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks -#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks -#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks -#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks -#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks -#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv -// parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ui32IntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(uint32_t ui32Base); -extern void QEIDisable(uint32_t ui32Base); -extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, - uint32_t ui32MaxPosition); -extern uint32_t QEIPositionGet(uint32_t ui32Base); -extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position); -extern int32_t QEIDirectionGet(uint32_t ui32Base); -extern bool QEIErrorGet(uint32_t ui32Base); -extern void QEIFilterEnable(uint32_t ui32Base); -extern void QEIFilterDisable(uint32_t ui32Base); -extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt); -extern void QEIVelocityEnable(uint32_t ui32Base); -extern void QEIVelocityDisable(uint32_t ui32Base); -extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, - uint32_t ui32Period); -extern uint32_t QEIVelocityGet(uint32_t ui32Base); -extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void QEIIntUnregister(uint32_t ui32Base); -extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked); -extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_QEI_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/readme.txt b/bsp/tm4c129x-dk/libraries/driverlib/readme.txt deleted file mode 100644 index 1f90c23656..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/readme.txt +++ /dev/null @@ -1,36 +0,0 @@ -This project will build the TivaWare Peripheral Driver Library. - -------------------------------------------------------------------------------- - -Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -Software License Agreement - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the - distribution. - - Neither the name of Texas Instruments Incorporated nor the names of - its contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. diff --git a/bsp/tm4c129x-dk/libraries/driverlib/rom.h b/bsp/tm4c129x-dk/libraries/driverlib/rom.h deleted file mode 100644 index 2ffdab87e5..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/rom.h +++ /dev/null @@ -1,8346 +0,0 @@ -//***************************************************************************** -// -// rom.h - Macros to facilitate calling functions in the ROM. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ROM_H__ -#define __DRIVERLIB_ROM_H__ - -#ifndef DEPRECATED -//***************************************************************************** -// -// ROM selection labels changed between TivaWare 2.0.1 and 2.1. The following -// labels are intended to ensure backwards compatibility for applications -// which have not yet been updated to use the replacement labels. -// -//***************************************************************************** -#ifdef TARGET_IS_SNOWFLAKE_RA0 -#define TARGET_IS_TM4C129_RA0 -#endif -#ifdef TARGET_IS_SNOWFLAKE_RA1 -#define TARGET_IS_TM4C129_RA1 -#endif -#ifdef TARGET_IS_SNOWFLAKE_RA2 -#define TARGET_IS_TM4C129_RA2 -#endif -#ifdef TARGET_IS_BLIZZARD_RA1 -#define TARGET_IS_TM4C123_RA1 -#endif -#ifdef TARGET_IS_BLIZZARD_RA2 -#define TARGET_IS_TM4C123_RA2 -#endif -#ifdef TARGET_IS_BLIZZARD_RA3 -#define TARGET_IS_TM4C123_RA3 -#endif -#ifdef TARGET_IS_BLIZZARD_RB0 -#define TARGET_IS_TM4C123_RB0 -#endif -#ifdef TARGET_IS_BLIZZARD_RB1 -#define TARGET_IS_TM4C123_RB1 -#endif -#endif - -//***************************************************************************** -// -// Pointers to the main API tables. -// -//***************************************************************************** -#define ROM_APITABLE ((uint32_t *)0x01000010) -#define ROM_VERSION (ROM_APITABLE[0]) -#define ROM_UARTTABLE ((uint32_t *)(ROM_APITABLE[1])) -#define ROM_SSITABLE ((uint32_t *)(ROM_APITABLE[2])) -#define ROM_I2CTABLE ((uint32_t *)(ROM_APITABLE[3])) -#define ROM_GPIOTABLE ((uint32_t *)(ROM_APITABLE[4])) -#define ROM_ADCTABLE ((uint32_t *)(ROM_APITABLE[5])) -#define ROM_COMPARATORTABLE ((uint32_t *)(ROM_APITABLE[6])) -#define ROM_FLASHTABLE ((uint32_t *)(ROM_APITABLE[7])) -#define ROM_PWMTABLE ((uint32_t *)(ROM_APITABLE[8])) -#define ROM_QEITABLE ((uint32_t *)(ROM_APITABLE[9])) -#define ROM_SYSTICKTABLE ((uint32_t *)(ROM_APITABLE[10])) -#define ROM_TIMERTABLE ((uint32_t *)(ROM_APITABLE[11])) -#define ROM_WATCHDOGTABLE ((uint32_t *)(ROM_APITABLE[12])) -#define ROM_SYSCTLTABLE ((uint32_t *)(ROM_APITABLE[13])) -#define ROM_INTERRUPTTABLE ((uint32_t *)(ROM_APITABLE[14])) -#define ROM_USBTABLE ((uint32_t *)(ROM_APITABLE[16])) -#define ROM_UDMATABLE ((uint32_t *)(ROM_APITABLE[17])) -#define ROM_CANTABLE ((uint32_t *)(ROM_APITABLE[18])) -#define ROM_HIBERNATETABLE ((uint32_t *)(ROM_APITABLE[19])) -#define ROM_MPUTABLE ((uint32_t *)(ROM_APITABLE[20])) -#define ROM_SOFTWARETABLE ((uint32_t *)(ROM_APITABLE[21])) -#define ROM_EPITABLE ((uint32_t *)(ROM_APITABLE[23])) -#define ROM_EEPROMTABLE ((uint32_t *)(ROM_APITABLE[24])) -#define ROM_FPUTABLE ((uint32_t *)(ROM_APITABLE[26])) -#define ROM_SMBUSTABLE ((uint32_t *)(ROM_APITABLE[29])) -#define ROM_SYSEXCTABLE ((uint32_t *)(ROM_APITABLE[30])) -#define ROM_ONEWIRETABLE ((uint32_t *)(ROM_APITABLE[34])) -#define ROM_SPIFLASHTABLE ((uint32_t *)(ROM_APITABLE[38])) -#define ROM_LCDTABLE ((uint32_t *)(ROM_APITABLE[41])) -#define ROM_EMACTABLE ((uint32_t *)(ROM_APITABLE[42])) -#define ROM_AESTABLE ((uint32_t *)(ROM_APITABLE[43])) -#define ROM_CRCTABLE ((uint32_t *)(ROM_APITABLE[44])) -#define ROM_DESTABLE ((uint32_t *)(ROM_APITABLE[45])) -#define ROM_SHAMD5TABLE ((uint32_t *)(ROM_APITABLE[46])) - -//***************************************************************************** -// -// Macros for calling ROM functions in the ADC API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDataGet \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - uint32_t *pui32Buffer))ROM_ADCTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - bool bMasked))ROM_ADCTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - uint32_t ui32Trigger, \ - uint32_t ui32Priority))ROM_ADCTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceStepConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum, \ - uint32_t ui32Step, \ - uint32_t ui32Config))ROM_ADCTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceOverflow \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceOverflowClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceUnderflow \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceUnderflowClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCProcessorTrigger \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCHardwareOversampleConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Factor))ROM_ADCTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - uint32_t ui32Config))ROM_ADCTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorRegionSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - uint32_t ui32LowRef, \ - uint32_t ui32HighRef))ROM_ADCTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorReset \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - bool bTrigger, \ - bool bInterrupt))ROM_ADCTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCComparatorIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Status))ROM_ADCTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCReferenceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ref))ROM_ADCTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCReferenceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCPhaseDelaySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Phase))ROM_ADCTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCPhaseDelayGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ADCTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ADCTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_ADCTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCSequenceDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ADCBusy \ - ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the AES API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_AESTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESAuthLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_AESTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_AESTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataAuth \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t ui32Length, \ - uint32_t *pui32Tag))ROM_AESTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t *pui32Dest, \ - uint32_t ui32Length))ROM_AESTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataProcessAuth \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t *pui32Dest, \ - uint32_t ui32Length, \ - uint32_t *pui32AuthSrc, \ - uint32_t ui32AuthLength, \ - uint32_t *pui32Tag))ROM_AESTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_AESTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_AESTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_AESTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_AESTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIVSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32IVdata))ROM_AESTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESKey1Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESKey2Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESKey3Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key))ROM_AESTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Length))ROM_AESTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESReset \ - ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESTagRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32TagData))ROM_AESTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_AESIVRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32IVdata))ROM_AESTABLE[22]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CAN API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntClr))ROM_CANTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANInit \ - ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANEnable \ - ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANDisable \ - ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANBitTimingSet \ - ((void (*)(uint32_t ui32Base, \ - tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANBitTimingGet \ - ((void (*)(uint32_t ui32Base, \ - tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANMessageSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ObjID, \ - tCANMsgObject *psMsgObject, \ - tMsgObjType eMsgType))ROM_CANTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANMessageGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ObjID, \ - tCANMsgObject *psMsgObject, \ - bool bClrPendingInt))ROM_CANTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANStatusGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - tCANStsReg eStatusReg))ROM_CANTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANMessageClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ObjID))ROM_CANTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_CANTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_CANTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANRetryGet \ - ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANRetrySet \ - ((void (*)(uint32_t ui32Base, \ - bool bAutoRetry))ROM_CANTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANErrCntrGet \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32RxCount, \ - uint32_t *pui32TxCount))ROM_CANTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CANBitRateSet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32SourceClock, \ - uint32_t ui32BitRate))ROM_CANTABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Comparator API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - uint32_t ui32Config))ROM_COMPARATORTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorRefSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorValueGet \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_ComparatorIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t ui32Comp, \ - bool bMasked))ROM_COMPARATORTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CRC API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCDataProcess \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t *pui32DataIn, \ - uint32_t ui32DataLength, \ - bool bPPResult))ROM_CRCTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_CRCTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCResultRead \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bPPResult))ROM_CRCTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_CRCSeedSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seed))ROM_CRCTABLE[4]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the DES API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_DESTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_DESTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_DESTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_DESTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src, \ - uint32_t *pui32Dest, \ - uint32_t ui32Length))ROM_DESTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_DESTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_DESTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESIVSet \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32IVdata))ROM_DESTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key))ROM_DESTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_DESTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_DESReset \ - ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the EEPROM API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMRead \ - ((void (*)(uint32_t *pui32Data, \ - uint32_t ui32Address, \ - uint32_t ui32Count))ROM_EEPROMTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockCountGet \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockHide \ - ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockLock \ - ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockPasswordSet \ - ((uint32_t (*)(uint32_t ui32Block, \ - uint32_t *pui32Password, \ - uint32_t ui32Count))ROM_EEPROMTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockProtectGet \ - ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockProtectSet \ - ((uint32_t (*)(uint32_t ui32Block, \ - uint32_t ui32Protect))ROM_EEPROMTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMBlockUnlock \ - ((uint32_t (*)(uint32_t ui32Block, \ - uint32_t *pui32Password, \ - uint32_t ui32Count))ROM_EEPROMTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) -#define ROM_EEPROMMassErase \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMProgram \ - ((uint32_t (*)(uint32_t *pui32Data, \ - uint32_t ui32Address, \ - uint32_t ui32Count))ROM_EEPROMTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMProgramNonBlocking \ - ((uint32_t (*)(uint32_t ui32Data, \ - uint32_t ui32Address))ROM_EEPROMTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMSizeGet \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMStatusGet \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EEPROMInit \ - ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the EPI API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_EPITABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_EPITABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIDividerSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Divider))ROM_EPITABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigSDRAMSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32Refresh))ROM_EPITABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigGPModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32FrameCount, \ - uint32_t ui32MaxWait))ROM_EPITABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB8Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32MaxWait))ROM_EPITABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB16Set \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32MaxWait))ROM_EPITABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIAddressMapSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Map))ROM_EPITABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32DataSize, \ - uint32_t ui32Address))ROM_EPITABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadStart \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32Count))ROM_EPITABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadStop \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_EPITABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadCount \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_EPITABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadAvail \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadGet32 \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint32_t *pui32Buf))ROM_EPITABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadGet16 \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint16_t *pui16Buf))ROM_EPITABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPINonBlockingReadGet8 \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint8_t *pui8Buf))ROM_EPITABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIFIFOConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_EPITABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIWriteFIFOCountGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EPITABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EPITABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntErrorStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIIntErrorClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ErrFlags))ROM_EPITABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIDividerCSSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Divider))ROM_EPITABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIDMATxCount \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Count))ROM_EPITABLE[23]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB8CSSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB16CSSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB8TimingSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIConfigHB16TimingSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32Config))ROM_EPITABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t ui32CR))ROM_EPITABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_EPITABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegGetNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint32_t *pui32CR))ROM_EPITABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EPIPSRAMConfigRegGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_EPITABLE[31]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the EMAC API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_EMACTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Index, \ - uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Index, \ - const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACConfigGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Config, \ - uint32_t *pui32Mode, \ - uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32ModeFlags, \ - uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACDMAStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACFrameFilterGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACFrameFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACInit \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SysClk, \ - uint32_t ui32BusConfig, \ - uint32_t ui32RxBurst, \ - uint32_t ui32TxBurst, \ - uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EMACTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EMACTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_EMACTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_EMACTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYPowerOff \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYPowerOn \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint8_t ui8RegAddr))ROM_EMACTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint8_t ui8RegAddr, \ - uint16_t ui16Data))ROM_EMACTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACReset \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMACurrentBufferGet \ - ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMACurrentDescriptorGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMADescriptorListGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMADescriptorListSet \ - ((void (*)(uint32_t ui32Base, \ - tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxDMAPollDemand \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRxWatchdogTimerSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Timeout))ROM_EMACTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACStatusGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMACurrentBufferGet \ - ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMACurrentDescriptorGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMADescriptorListGet \ - ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMADescriptorListSet \ - ((void (*)(uint32_t ui32Base, \ - tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxDMAPollDemand \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTxFlush \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrFilterGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Index))ROM_EMACTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACAddrFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Index, \ - uint32_t ui32Config))ROM_EMACTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACHashFilterBitCalculate \ - ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACHashFilterGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32HashHi, \ - uint32_t *pui32HashLo))ROM_EMACTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACHashFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32HashHi, \ - uint32_t ui32HashLo))ROM_EMACTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACNumAddrGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYExtendedRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint16_t ui16RegAddr))ROM_EMACTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPHYExtendedWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8PhyAddr, \ - uint16_t ui16RegAddr, \ - uint16_t ui16Data))ROM_EMACTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPowerManagementControlGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPowerManagementControlSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_EMACTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACPowerManagementStatusGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRemoteWakeUpFrameFilterGet \ - ((void (*)(uint32_t ui32Base, \ - tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACRemoteWakeUpFrameFilterSet \ - ((void (*)(uint32_t ui32Base, \ - const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampAddendSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds))ROM_EMACTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampConfigGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSCommand \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Cmd))ROM_EMACTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSCommandModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_EMACTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSPeriodSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Period, \ - uint32_t ui32Width))ROM_EMACTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampPPSSimpleModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampSysTimeGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Seconds, \ - uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampSysTimeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds, \ - uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampSysTimeUpdate \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds, \ - uint32_t ui32SubSeconds, \ - bool bInc))ROM_EMACTABLE[60]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampTargetIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampTargetIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACTimestampTargetSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seconds, \ - uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANHashFilterBitCalculate \ - ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANHashFilterGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANHashFilterSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Hash))ROM_EMACTABLE[66]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANRxConfigGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint16_t *pui16Tag))ROM_EMACTABLE[67]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANRxConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint16_t ui16Tag, \ - uint32_t ui32Config))ROM_EMACTABLE[68]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANTxConfigGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint16_t *pui16Tag))ROM_EMACTABLE[69]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_EMACVLANTxConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint16_t ui16Tag, \ - uint32_t ui32Config))ROM_EMACTABLE[70]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateEMAC \ - ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Flash API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProgram \ - ((int32_t (*)(uint32_t *pui32Data, \ - uint32_t ui32Address, \ - uint32_t ui32Count))ROM_FLASHTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashErase \ - ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProtectGet \ - ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProtectSet \ - ((int32_t (*)(uint32_t ui32Address, \ - tFlashProtection eProtect))ROM_FLASHTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashProtectSave \ - ((int32_t (*)(void))ROM_FLASHTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashUserGet \ - ((int32_t (*)(uint32_t *pui32User0, \ - uint32_t *pui32User1))ROM_FLASHTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashUserSet \ - ((int32_t (*)(uint32_t ui32User0, \ - uint32_t ui32User1))ROM_FLASHTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashUserSave \ - ((int32_t (*)(void))ROM_FLASHTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FlashIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the FPU API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUEnable \ - ((void (*)(void))ROM_FPUTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUDisable \ - ((void (*)(void))ROM_FPUTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUFlushToZeroModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUHalfPrecisionModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPULazyStackingEnable \ - ((void (*)(void))ROM_FPUTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUNaNModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPURoundingModeSet \ - ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUStackingDisable \ - ((void (*)(void))ROM_FPUTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_FPUStackingEnable \ - ((void (*)(void))ROM_FPUTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the GPIO API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinWrite \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint8_t ui8Val))ROM_GPIOTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODirModeSet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint32_t ui32PinIO))ROM_GPIOTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODirModeGet \ - ((uint32_t (*)(uint32_t ui32Port, \ - uint8_t ui8Pin))ROM_GPIOTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntTypeSet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint32_t ui32IntType))ROM_GPIOTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntTypeGet \ - ((uint32_t (*)(uint32_t ui32Port, \ - uint8_t ui8Pin))ROM_GPIOTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_GPIOPadConfigSet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins, \ - uint32_t ui32Strength, \ - uint32_t ui32PadType))ROM_GPIOTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPadConfigGet \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pin, \ - uint32_t *pui32Strength, \ - uint32_t *pui32PadType))ROM_GPIOTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinRead \ - ((int32_t (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_GPIOPinTypeCAN \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeComparator \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeGPIOInput \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeGPIOOutput \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeI2C \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypePWM \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeQEI \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeSSI \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeTimer \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeUART \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeGPIOOutputOD \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeADC \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeUSBDigital \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinConfigure \ - ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeUSBAnalog \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODMATriggerEnable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIODMATriggerDisable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOADCTriggerEnable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOADCTriggerDisable \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeI2CSCL \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeOneWire \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeWakeHigh \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOPinTypeWakeLow \ - ((void (*)(uint32_t ui32Port, \ - uint8_t ui8Pins))ROM_GPIOTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntClear \ - ((void (*)(uint32_t ui32Port, \ - uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntDisable \ - ((void (*)(uint32_t ui32Port, \ - uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntEnable \ - ((void (*)(uint32_t ui32Port, \ - uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_GPIOIntStatus \ - ((uint32_t (*)(uint32_t ui32Port, \ - bool bMasked))ROM_GPIOTABLE[54]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Hibernate API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateEnableExpClk \ - ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCEnable \ - ((void (*)(void))ROM_HIBERNATETABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateWakeSet \ - ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateWakeGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateLowBatSet \ - ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateLowBatGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSet \ - ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCTrimSet \ - ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCTrimGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateDataSet \ - ((void (*)(uint32_t *pui32Data, \ - uint32_t ui32Count))ROM_HIBERNATETABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateDataGet \ - ((void (*)(uint32_t *pui32Data, \ - uint32_t ui32Count))ROM_HIBERNATETABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRequest \ - ((void (*)(void))ROM_HIBERNATETABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateIsActive \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSSGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateClockConfig \ - ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateBatCheckStart \ - ((void (*)(void))ROM_HIBERNATETABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateBatCheckDone \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateGPIORetentionEnable \ - ((void (*)(void))ROM_HIBERNATETABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateGPIORetentionDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateGPIORetentionGet \ - ((bool (*)(void))ROM_HIBERNATETABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCounterMode \ - ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarSet \ - ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarGet \ - ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarMatchSet \ - ((void (*)(uint32_t ui32Index, \ - struct tm *psTime))ROM_HIBERNATETABLE[37]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateCalendarMatchGet \ - ((void (*)(uint32_t ui32Index, \ - struct tm *psTime))ROM_HIBERNATETABLE[38]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperDisable \ - ((void (*)(void))ROM_HIBERNATETABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEnable \ - ((void (*)(void))ROM_HIBERNATETABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEventsClear \ - ((void (*)(void))ROM_HIBERNATETABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEventsConfig \ - ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperEventsGet \ - ((bool (*)(uint32_t ui32Index, \ - uint32_t *pui32RTC, \ - uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperExtOscValid \ - ((bool (*)(void))ROM_HIBERNATETABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperExtOscRecover \ - ((void (*)(void))ROM_HIBERNATETABLE[45]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperIODisable \ - ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperIOEnable \ - ((void (*)(uint32_t ui32Input, \ - uint32_t ui32Config))ROM_HIBERNATETABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateTamperStatusGet \ - ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCMatchGet \ - ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCMatchSet \ - ((void (*)(uint32_t ui32Match, \ - uint32_t ui32Value))ROM_HIBERNATETABLE[50]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSSMatchGet \ - ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_HibernateRTCSSMatchSet \ - ((void (*)(uint32_t ui32Match, \ - uint32_t ui32Value))ROM_HIBERNATETABLE[52]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2C API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32I2CClk, \ - bool bFast))ROM_I2CTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveInit \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterSlaveAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr, \ - bool bReceive))ROM_I2CTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBusBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Cmd))ROM_I2CTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateI2C \ - ((void (*)(void))ROM_I2CTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterTimeoutSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Value))ROM_I2CTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveACKOverride \ - ((void (*)(uint32_t ui32Base, \ - bool bEnable))ROM_I2CTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveACKValueSet \ - ((void (*)(uint32_t ui32Base, \ - bool bACK))ROM_I2CTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveAddressSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8AddrNum, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterLineStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CTxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CTxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CRxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CRxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFOStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataPutNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CFIFODataGetNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t *pui8Data))ROM_I2CTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBurstLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Length))ROM_I2CTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterBurstCountGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveFIFODisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CSlaveFIFOEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_I2CMasterGlitchFilterConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[54]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Interrupt API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntEnable \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntMasterEnable \ - ((bool (*)(void))ROM_INTERRUPTTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntMasterDisable \ - ((bool (*)(void))ROM_INTERRUPTTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntDisable \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityGroupingSet \ - ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityGroupingGet \ - ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPrioritySet \ - ((void (*)(uint32_t ui32Interrupt, \ - uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPendSet \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPendClear \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityMaskSet \ - ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntPriorityMaskGet \ - ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntIsEnabled \ - ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_IntTrigger \ - ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the LCD API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_LCDTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDClockReset \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Clocks))ROM_LCDTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDDMAConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_LCDTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDCommandWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Cmd))ROM_LCDTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_LCDTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDataRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_LCDTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Data))ROM_LCDTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDMADisable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDDMAWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - const uint32_t *pui32Data, \ - uint32_t ui32Count))ROM_LCDTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDIndexedRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Addr))ROM_LCDTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDIndexedWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - uint16_t ui16Addr, \ - uint16_t ui16Data))ROM_LCDTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDStatusRead \ - ((uint16_t (*)(uint32_t ui32Base, \ - uint32_t ui32CS))ROM_LCDTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIDDTimingSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CS, \ - const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_LCDTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_LCDTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_LCDTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDModeSet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t ui8Mode, \ - uint32_t ui32PixClk, \ - uint32_t ui32SysClk))ROM_LCDTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterACBiasIntCountSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Count))ROM_LCDTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterDisable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterEnable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterFrameBufferSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Buffer, \ - uint32_t *pui32Addr, \ - uint32_t ui32NumBytes))ROM_LCDTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterPaletteSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Type, \ - uint32_t *pui32PalAddr, \ - const uint32_t *pui32SrcColors, \ - uint32_t ui32Start, \ - uint32_t ui32Count))ROM_LCDTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterSubPanelConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags, \ - uint32_t ui32BottomLines, \ - uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterSubPanelDisable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterSubPanelEnable \ - ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterTimingSet \ - ((void (*)(uint32_t ui32Base, \ - const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_LCDRasterEnabled \ - ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the MPU API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPUEnable \ - ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPUDisable \ - ((void (*)(void))ROM_MPUTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionCountGet \ - ((uint32_t (*)(void))ROM_MPUTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionEnable \ - ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionDisable \ - ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionSet \ - ((void (*)(uint32_t ui32Region, \ - uint32_t ui32Addr, \ - uint32_t ui32Flags))ROM_MPUTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_MPURegionGet \ - ((void (*)(uint32_t ui32Region, \ - uint32_t *pui32Addr, \ - uint32_t *pui32Flags))ROM_MPUTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the OneWire API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_ONEWIRETABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireBusReset \ - ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireBusStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDataGet \ - ((void (*)(uint32_t u3i2Base, \ - uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDataGetNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireInit \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireTransaction \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32OpFlags, \ - uint32_t ui32Data, \ - uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_OneWireDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PWM API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMPulseWidthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOut, \ - uint32_t ui32Width))ROM_PWMTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Config))ROM_PWMTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenPeriodSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Period))ROM_PWMTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenPeriodGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMPulseWidthGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOut))ROM_PWMTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMDeadBandEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint16_t ui16Rise, \ - uint16_t ui16Fall))ROM_PWMTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMDeadBandDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen))ROM_PWMTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMSyncUpdate \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenBits))ROM_PWMTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMSyncTimeBase \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenBits))ROM_PWMTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputState \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bEnable))ROM_PWMTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputInvert \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bInvert))ROM_PWMTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputFault \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bFaultSuppress))ROM_PWMTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntTrigEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32IntTrig))ROM_PWMTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntTrigDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32IntTrig))ROM_PWMTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - bool bMasked))ROM_PWMTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Ints))ROM_PWMTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenFault))ROM_PWMTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32GenFault))ROM_PWMTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMFaultIntClear \ - ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_PWMTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputFaultLevel \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - bool bDriveHigh))ROM_PWMTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMFaultIntClearExt \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32FaultInts))ROM_PWMTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32MinFaultPeriod, \ - uint32_t ui32FaultSenses))ROM_PWMTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultTriggerSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group, \ - uint32_t ui32FaultTriggers))ROM_PWMTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultTriggerGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group))ROM_PWMTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group))ROM_PWMTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMGenFaultClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Gen, \ - uint32_t ui32Group, \ - uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMClockSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_PWMTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMClockGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_PWMOutputUpdateMode \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PWMOutBits, \ - uint32_t ui32Mode))ROM_PWMTABLE[31]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the QEI API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIPositionGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIEnable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIDisable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config, \ - uint32_t ui32MaxPosition))ROM_QEITABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIPositionSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Position))ROM_QEITABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIDirectionGet \ - ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIErrorGet \ - ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityEnable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityDisable \ - ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32PreDiv, \ - uint32_t ui32Period))ROM_QEITABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIVelocityGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_QEITABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_QEITABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_QEITABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_QEIIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_QEITABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SHAMD5 API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_SHAMD5TABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5ConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DataProcess \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32DataSrc, \ - uint32_t ui32DataLength, \ - uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DMADisable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5DMAEnable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HashLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_SHAMD5TABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACPPKeyGenerate \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Key, \ - uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACPPKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5HMACProcess \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32DataSrc, \ - uint32_t ui32DataLength, \ - uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5IntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5Reset \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SHAMD5ResultRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SMBus API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterIntProcess \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPUDIDPacketDecode \ - ((void (*)(tSMBusUDID *pUDID, \ - uint8_t *pui8Address, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusARPUDIDPacketEncode \ - ((void (*)(tSMBusUDID *pUDID, \ - uint8_t ui8Address, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPAssignAddress \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPGetUDIDDir \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPGetUDIDGen \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPNotifyMaster \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPPrepareToARP \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPResetDeviceDir \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterARPResetDeviceGen \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterBlockProcessCall \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8TxData, \ - uint8_t ui8TxSize, \ - uint8_t *pui8RxData))ROM_SMBUSTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterBlockRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterBlockWrite \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteReceive \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteSend \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Data))ROM_SMBUSTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteWordRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterByteWordWrite \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterHostNotify \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8OwnSlaveAddress, \ - uint8_t *pui8Data))ROM_SMBUSTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterI2CRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterI2CWrite \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterI2CWriteRead \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t *pui8TxData, \ - uint8_t ui8TxSize, \ - uint8_t *pui8RxData, \ - uint8_t ui8RxSize))ROM_SMBUSTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterInit \ - ((void (*)(tSMBus *psSMBus, \ - uint32_t ui32I2CBase, \ - uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterIntEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterProcessCall \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - uint8_t ui8Command, \ - uint8_t *pui8TxData, \ - uint8_t *pui8RxData))ROM_SMBUSTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusMasterQuickCommand \ - ((tSMBusStatus (*)(tSMBus *psSMBus, \ - uint8_t ui8TargetAddress, \ - bool bData))ROM_SMBUSTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusPECDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusPECEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusRxPacketSizeGet \ - ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveACKSend \ - ((void (*)(tSMBus *psSMBus, \ - bool bACK))ROM_SMBUSTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveAddressSet \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t ui8AddressNum, \ - uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagARGet \ - ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagARSet \ - ((void (*)(tSMBus *psSMBus, \ - bool bValue))ROM_SMBUSTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagAVGet \ - ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveARPFlagAVSet \ - ((void (*)(tSMBus *psSMBus, \ - bool bValue))ROM_SMBUSTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveBlockTransferDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveBlockTransferEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveCommandGet \ - ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveI2CDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveI2CEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveInit \ - ((void (*)(tSMBus *psSMBus, \ - uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveIntAddressGet \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveIntEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveIntProcess \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveManualACKDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveManualACKEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveManualACKStatusGet \ - ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveProcessCallDisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveProcessCallEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveRxBufferSet \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveTransferInit \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveTxBufferSet \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t *pui8Data, \ - uint8_t ui8Size))ROM_SMBUSTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveUDIDSet \ - ((void (*)(tSMBus *psSMBus, \ - tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusStatusGet \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusSlaveDataSend \ - ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusFIFOEnable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusFIFODisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusDMAEnable \ - ((void (*)(tSMBus *psSMBus, \ - uint8_t ui8TxChannel, \ - uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SMBusDMADisable \ - ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SPIFlash API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashIntHandler \ - ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashInit \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Clock, \ - uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashWriteStatus \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashPageProgram \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashPageProgramNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashWriteDisable \ - ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashReadStatus \ - ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashWriteEnable \ - ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashFastRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashFastReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashSectorErase \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashDualRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashDualReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashBlockErase32 \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashQuadRead \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashQuadReadNonBlocking \ - ((void (*)(tSPIFlashState *pState, \ - uint32_t ui32Base, \ - uint32_t ui32Addr, \ - uint8_t *pui8Data, \ - uint32_t ui32Count, \ - bool bUseDMA, \ - uint32_t ui32TxChannel, \ - uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashReadID \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8ManufacturerID, \ - uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashChipErase \ - ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SPIFlashBlockErase64 \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SSI API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32SSIClk, \ - uint32_t ui32Protocol, \ - uint32_t ui32Mode, \ - uint32_t ui32BitRate, \ - uint32_t ui32DataWidth))ROM_SSITABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIEnable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDisable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SSITABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SSITABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_SSITABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SSITABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32Data))ROM_SSITABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t *pui32Data))ROM_SSITABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateSSI \ - ((void (*)(void))ROM_SSITABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_SSITABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_SSITABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIBusy \ - ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIClockSourceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIClockSourceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Source))ROM_SSITABLE[16]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_SSITABLE[17]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvDataPutFrameEnd \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[18]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvDataPutFrameEndNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_SSITABLE[19]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvFrameHoldEnable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SSIAdvFrameHoldDisable \ - ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysCtl API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlSleep \ - ((void (*)(void))ROM_SYSCTLTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlSRAMSizeGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlFlashSizeGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralPresent \ - ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralReset \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralEnable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralDisable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralSleepEnable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralSleepDisable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralClockGating \ - ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntEnable \ - ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntDisable \ - ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntClear \ - ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlReset \ - ((void (*)(void))ROM_SYSCTLTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlDeepSleep \ - ((void (*)(void))ROM_SYSCTLTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetCauseGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetCauseClear \ - ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlClockSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlClockGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlPWMClockSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlPWMClockGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlUSBPLLEnable \ - ((void (*)(void))ROM_SYSCTLTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlUSBPLLDisable \ - ((void (*)(void))ROM_SYSCTLTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlDelay \ - ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralReady \ - ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralPowerOn \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPeripheralPowerOff \ - ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlMOSCConfigSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlPIOSCCalibrate \ - ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_SysCtlDeepSleepClockSet \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlDeepSleepClockConfigSet \ - ((void (*)(uint32_t ui32Div, \ - uint32_t ui32Config))ROM_SYSCTLTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetBehaviorSet \ - ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlResetBehaviorGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlFlashSectorSizeGet \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlVoltageEventConfig \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlVoltageEventStatus \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlVoltageEventClear \ - ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlNMIStatus \ - ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlNMIClear \ - ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlClockOutConfig \ - ((void (*)(uint32_t ui32Config, \ - uint32_t ui32Div))ROM_SYSCTLTABLE[60]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysCtlAltClkConfig \ - ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysExc API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntStatus \ - ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntClear \ - ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntDisable \ - ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysExcIntEnable \ - ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysTick API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickValueGet \ - ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickIntEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickIntDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickPeriodSet \ - ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_SysTickPeriodGet \ - ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Timer API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerConfigure \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_TIMERTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlLevel \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bInvert))ROM_TIMERTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA1) -#define ROM_TimerControlTrigger \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bEnable))ROM_TIMERTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlEvent \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Event))ROM_TIMERTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlStall \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bStall))ROM_TIMERTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerRTCEnable \ - ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerRTCDisable \ - ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleMatchSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerPrescaleMatchGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerLoadSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerLoadGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerValueGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerMatchSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - uint32_t ui32Value))ROM_TIMERTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerMatchGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Timer))ROM_TIMERTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_TIMERTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerControlWaitOnTrigger \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timer, \ - bool bWait))ROM_TIMERTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerLoadSet64 \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Value))ROM_TIMERTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerLoadGet64 \ - ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerValueGet64 \ - ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerMatchSet64 \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Value))ROM_TIMERTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) -#define ROM_TimerMatchGet64 \ - ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerClockSourceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerClockSourceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Source))ROM_TIMERTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerADCEventGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerADCEventSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerDMAEventGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerDMAEventSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_TimerSynchronize \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Timers))ROM_TIMERTABLE[34]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UART API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharPut \ - ((void (*)(uint32_t ui32Base, \ - unsigned char ucData))ROM_UARTTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTParityModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Parity))ROM_UARTTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTParityModeGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFOLevelSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32TxLevel, \ - uint32_t ui32RxLevel))ROM_UARTTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t *pui32TxLevel, \ - uint32_t *pui32RxLevel))ROM_UARTTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32UARTClk, \ - uint32_t ui32Baud, \ - uint32_t ui32Config))ROM_UARTTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32UARTClk, \ - uint32_t *pui32Baud, \ - uint32_t *pui32Config))ROM_UARTTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTEnableSIR \ - ((void (*)(uint32_t ui32Base, \ - bool bLowPower))ROM_UARTTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDisableSIR \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharsAvail \ - ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTSpaceAvail \ - ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTCharPutNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - unsigned char ucData))ROM_UARTTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTBreakCtl \ - ((void (*)(uint32_t ui32Base, \ - bool bBreakState))ROM_UARTTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_UARTTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_UARTTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_UARTTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_UARTTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateUART \ - ((void (*)(void))ROM_UARTTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFOEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFIFODisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTBusy \ - ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTTxIntModeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_UARTTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTTxIntModeGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTRxErrorGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTRxErrorClear \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTClockSourceSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Source))ROM_UARTTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTClockSourceGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitDisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Addr, \ - uint8_t ui8Mask))ROM_UARTTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UART9BitAddrSend \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Addr))ROM_UARTTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTSmartCardDisable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTSmartCardEnable \ - ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemControlClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Control))ROM_UARTTABLE[39]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemControlGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemControlSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Control))ROM_UARTTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTModemStatusGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFlowControlGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UARTFlowControlSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_UARTTABLE[44]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the uDMA API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelTransferSet \ - ((void (*)(uint32_t ui32ChannelStructIndex, \ - uint32_t ui32Mode, \ - void *pvSrcAddr, \ - void *pvDstAddr, \ - uint32_t ui32TransferSize))ROM_UDMATABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAEnable \ - ((void (*)(void))ROM_UDMATABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMADisable \ - ((void (*)(void))ROM_UDMATABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAErrorStatusGet \ - ((uint32_t (*)(void))ROM_UDMATABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAErrorStatusClear \ - ((void (*)(void))ROM_UDMATABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelEnable \ - ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelDisable \ - ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelIsEnabled \ - ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAControlBaseSet \ - ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAControlBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelRequest \ - ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(uint32_t ui32ChannelNum, \ - uint32_t ui32Attr))ROM_UDMATABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(uint32_t ui32ChannelNum, \ - uint32_t ui32Attr))ROM_UDMATABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelControlSet \ - ((void (*)(uint32_t ui32ChannelStructIndex, \ - uint32_t ui32Control))ROM_UDMATABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelSelectSecondary \ - ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelSelectDefault \ - ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAIntStatus \ - ((uint32_t (*)(void))ROM_UDMATABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAIntClear \ - ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAControlAlternateBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32ChannelNum, \ - uint32_t ui32TaskCount, \ - void *pvTaskList, \ - uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_uDMAChannelAssign \ - ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the USB API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevAddrGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Address))ROM_USBTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevConnect \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevDisconnect \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32MaxPacketSize, \ - uint32_t ui32Flags))ROM_USBTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointDataAck \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - bool bIsLastPacket))ROM_USBTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointStall \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointStallClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointStatusClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataGet \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint8_t *pui8Data, \ - uint32_t *pui32Size))ROM_USBTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataPut \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint8_t *pui8Data, \ - uint32_t ui32Size))ROM_USBTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataSend \ - ((int32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32TransType))ROM_USBTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataToggleClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOAddrGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[15]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOConfigGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t *pui32FIFOAddress, \ - uint32_t *pui32FIFOSize, \ - uint32_t ui32Flags))ROM_USBTABLE[16]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32FIFOAddress, \ - uint32_t ui32FIFOSize, \ - uint32_t ui32Flags))ROM_USBTABLE[17]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFIFOFlush \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[18]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBFrameNumberGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostAddrGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[20]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Addr, \ - uint32_t ui32Flags))ROM_USBTABLE[21]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32MaxPacketSize, \ - uint32_t ui32NAKPollInterval, \ - uint32_t ui32TargetEndpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[22]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointDataAck \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[23]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointDataToggle \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - bool bDataToggle, \ - uint32_t ui32Flags))ROM_USBTABLE[24]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointStatusClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[25]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostHubAddrGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[26]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostHubAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Addr, \ - uint32_t ui32Flags))ROM_USBTABLE[27]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_USBTABLE[30]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrFaultDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostPwrFaultEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostRequestIN \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[33]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostRequestStatus \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostReset \ - ((void (*)(uint32_t ui32Base, \ - bool bStart))ROM_USBTABLE[35]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostResume \ - ((void (*)(uint32_t ui32Base, \ - bool bStart))ROM_USBTABLE[36]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostSpeedGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostSuspend \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevEndpointConfigGet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t *pui32MaxPacketSize, \ - uint32_t *pui32Flags))ROM_USBTABLE[41]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[42]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[43]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDataAvail \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[44]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBModeGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMAChannel \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Channel))ROM_USBTABLE[47]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntDisableControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[48]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntEnableControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[49]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntStatusControl \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntDisableEndpoint \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[51]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntEnableEndpoint \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_USBTABLE[52]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBIntStatusEndpoint \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostMode \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevMode \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBPHYPowerOff \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBPHYPowerOn \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) -#endif -#if defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_UpdateUSB \ - ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBOTGMode \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostRequestINClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint))ROM_USBTABLE[60]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBNumEndpointsGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBClockDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBClockEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Div, \ - uint32_t ui32Flags))ROM_USBTABLE[63]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBControllerVersion \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_USBTABLE[65]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) -#endif -#if defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevLPMRemoteWake \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDevSpeedGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelAddressGet \ - ((void * (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[70]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelAddressSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - void *pvAddress))ROM_USBTABLE[71]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Config))ROM_USBTABLE[72]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[73]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[74]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[75]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[76]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelCountGet \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[77]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelCountSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Count, \ - uint32_t ui32Channel))ROM_USBTABLE[78]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint32_t ui32Channel))ROM_USBTABLE[80]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMAChannelStatusClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Channel, \ - uint32_t ui32Status))ROM_USBTABLE[81]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHighSpeed \ - ((void (*)(uint32_t ui32Base, \ - bool bEnable))ROM_USBTABLE[82]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointPing \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - bool bEnable))ROM_USBTABLE[83]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostEndpointSpeed \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Flags))ROM_USBTABLE[84]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostLPMConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32ResumeTime, \ - uint32_t ui32Config))ROM_USBTABLE[85]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostLPMResume \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBHostLPMSend \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Address, \ - uint32_t uiEndpoint))ROM_USBTABLE[87]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ints))ROM_USBTABLE[88]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Ints))ROM_USBTABLE[89]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMIntStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMLinkStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointPacketCountSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Count))ROM_USBTABLE[92]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_USBTABLE[93]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIDisable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIEnable \ - ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIRegRead \ - ((uint8_t (*)(uint32_t ui32Base, \ - uint8_t ui8Reg))ROM_USBTABLE[96]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBULPIRegWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Reg, \ - uint8_t ui8Data))ROM_USBTABLE[97]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBOTGSessionRequest \ - ((void (*)(uint32_t ui32Base, \ - bool bStart))ROM_USBTABLE[98]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBDMANumChannels \ - ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBEndpointDMAConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Endpoint, \ - uint32_t ui32Config))ROM_USBTABLE[100]) -#endif -#if defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBLPMRemoteWakeEnabled \ - ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_USBModeConfig \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_USBTABLE[103]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Watchdog API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntClear \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogRunning \ - ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogResetEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogResetDisable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogLock \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogUnlock \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogLockState \ - ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogReloadSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogReloadGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogValueGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_WATCHDOGTABLE[12]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogStallEnable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogStallDisable \ - ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_WatchdogIntTypeSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Software API. -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc16Array \ - ((uint16_t (*)(uint32_t ui32WordLen, \ - const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc16Array3 \ - ((void (*)(uint32_t ui32WordLen, \ - const uint32_t *pui32Data, \ - uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc16 \ - ((uint16_t (*)(uint16_t ui16Crc, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SOFTWARETABLE[3]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc8CCITT \ - ((uint8_t (*)(uint8_t ui8Crc, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SOFTWARETABLE[4]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_Crc32 \ - ((uint32_t (*)(uint32_t ui32Crc, \ - const uint8_t *pui8Data, \ - uint32_t ui32Count))ROM_SOFTWARETABLE[5]) -#endif -#if defined(TARGET_IS_TM4C123_RA1) || \ - defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) || \ - defined(TARGET_IS_TM4C123_RB2) || \ - defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) || \ - defined(TARGET_IS_TM4C129_RA2) -#define ROM_pvAESTable \ - ((void *)&(ROM_SOFTWARETABLE[7])) -#endif - -#endif // __DRIVERLIB_ROM_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/rom_map.h b/bsp/tm4c129x-dk/libraries/driverlib/rom_map.h deleted file mode 100644 index e45ede445f..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/rom_map.h +++ /dev/null @@ -1,6409 +0,0 @@ -//***************************************************************************** -// -// rom_map.h - Macros to facilitate calling functions in the ROM when they are -// available and in flash otherwise. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_ROM_MAP_H__ -#define __DRIVERLIB_ROM_MAP_H__ - -//***************************************************************************** -// -// Macros for the ADC API. -// -//***************************************************************************** -#ifdef ROM_ADCSequenceDataGet -#define MAP_ADCSequenceDataGet \ - ROM_ADCSequenceDataGet -#else -#define MAP_ADCSequenceDataGet \ - ADCSequenceDataGet -#endif -#ifdef ROM_ADCIntDisable -#define MAP_ADCIntDisable \ - ROM_ADCIntDisable -#else -#define MAP_ADCIntDisable \ - ADCIntDisable -#endif -#ifdef ROM_ADCIntEnable -#define MAP_ADCIntEnable \ - ROM_ADCIntEnable -#else -#define MAP_ADCIntEnable \ - ADCIntEnable -#endif -#ifdef ROM_ADCIntStatus -#define MAP_ADCIntStatus \ - ROM_ADCIntStatus -#else -#define MAP_ADCIntStatus \ - ADCIntStatus -#endif -#ifdef ROM_ADCIntClear -#define MAP_ADCIntClear \ - ROM_ADCIntClear -#else -#define MAP_ADCIntClear \ - ADCIntClear -#endif -#ifdef ROM_ADCSequenceEnable -#define MAP_ADCSequenceEnable \ - ROM_ADCSequenceEnable -#else -#define MAP_ADCSequenceEnable \ - ADCSequenceEnable -#endif -#ifdef ROM_ADCSequenceDisable -#define MAP_ADCSequenceDisable \ - ROM_ADCSequenceDisable -#else -#define MAP_ADCSequenceDisable \ - ADCSequenceDisable -#endif -#ifdef ROM_ADCSequenceConfigure -#define MAP_ADCSequenceConfigure \ - ROM_ADCSequenceConfigure -#else -#define MAP_ADCSequenceConfigure \ - ADCSequenceConfigure -#endif -#ifdef ROM_ADCSequenceStepConfigure -#define MAP_ADCSequenceStepConfigure \ - ROM_ADCSequenceStepConfigure -#else -#define MAP_ADCSequenceStepConfigure \ - ADCSequenceStepConfigure -#endif -#ifdef ROM_ADCSequenceOverflow -#define MAP_ADCSequenceOverflow \ - ROM_ADCSequenceOverflow -#else -#define MAP_ADCSequenceOverflow \ - ADCSequenceOverflow -#endif -#ifdef ROM_ADCSequenceOverflowClear -#define MAP_ADCSequenceOverflowClear \ - ROM_ADCSequenceOverflowClear -#else -#define MAP_ADCSequenceOverflowClear \ - ADCSequenceOverflowClear -#endif -#ifdef ROM_ADCSequenceUnderflow -#define MAP_ADCSequenceUnderflow \ - ROM_ADCSequenceUnderflow -#else -#define MAP_ADCSequenceUnderflow \ - ADCSequenceUnderflow -#endif -#ifdef ROM_ADCSequenceUnderflowClear -#define MAP_ADCSequenceUnderflowClear \ - ROM_ADCSequenceUnderflowClear -#else -#define MAP_ADCSequenceUnderflowClear \ - ADCSequenceUnderflowClear -#endif -#ifdef ROM_ADCProcessorTrigger -#define MAP_ADCProcessorTrigger \ - ROM_ADCProcessorTrigger -#else -#define MAP_ADCProcessorTrigger \ - ADCProcessorTrigger -#endif -#ifdef ROM_ADCHardwareOversampleConfigure -#define MAP_ADCHardwareOversampleConfigure \ - ROM_ADCHardwareOversampleConfigure -#else -#define MAP_ADCHardwareOversampleConfigure \ - ADCHardwareOversampleConfigure -#endif -#ifdef ROM_ADCComparatorConfigure -#define MAP_ADCComparatorConfigure \ - ROM_ADCComparatorConfigure -#else -#define MAP_ADCComparatorConfigure \ - ADCComparatorConfigure -#endif -#ifdef ROM_ADCComparatorRegionSet -#define MAP_ADCComparatorRegionSet \ - ROM_ADCComparatorRegionSet -#else -#define MAP_ADCComparatorRegionSet \ - ADCComparatorRegionSet -#endif -#ifdef ROM_ADCComparatorReset -#define MAP_ADCComparatorReset \ - ROM_ADCComparatorReset -#else -#define MAP_ADCComparatorReset \ - ADCComparatorReset -#endif -#ifdef ROM_ADCComparatorIntDisable -#define MAP_ADCComparatorIntDisable \ - ROM_ADCComparatorIntDisable -#else -#define MAP_ADCComparatorIntDisable \ - ADCComparatorIntDisable -#endif -#ifdef ROM_ADCComparatorIntEnable -#define MAP_ADCComparatorIntEnable \ - ROM_ADCComparatorIntEnable -#else -#define MAP_ADCComparatorIntEnable \ - ADCComparatorIntEnable -#endif -#ifdef ROM_ADCComparatorIntStatus -#define MAP_ADCComparatorIntStatus \ - ROM_ADCComparatorIntStatus -#else -#define MAP_ADCComparatorIntStatus \ - ADCComparatorIntStatus -#endif -#ifdef ROM_ADCComparatorIntClear -#define MAP_ADCComparatorIntClear \ - ROM_ADCComparatorIntClear -#else -#define MAP_ADCComparatorIntClear \ - ADCComparatorIntClear -#endif -#ifdef ROM_ADCReferenceSet -#define MAP_ADCReferenceSet \ - ROM_ADCReferenceSet -#else -#define MAP_ADCReferenceSet \ - ADCReferenceSet -#endif -#ifdef ROM_ADCReferenceGet -#define MAP_ADCReferenceGet \ - ROM_ADCReferenceGet -#else -#define MAP_ADCReferenceGet \ - ADCReferenceGet -#endif -#ifdef ROM_ADCPhaseDelaySet -#define MAP_ADCPhaseDelaySet \ - ROM_ADCPhaseDelaySet -#else -#define MAP_ADCPhaseDelaySet \ - ADCPhaseDelaySet -#endif -#ifdef ROM_ADCPhaseDelayGet -#define MAP_ADCPhaseDelayGet \ - ROM_ADCPhaseDelayGet -#else -#define MAP_ADCPhaseDelayGet \ - ADCPhaseDelayGet -#endif -#ifdef ROM_ADCIntClearEx -#define MAP_ADCIntClearEx \ - ROM_ADCIntClearEx -#else -#define MAP_ADCIntClearEx \ - ADCIntClearEx -#endif -#ifdef ROM_ADCIntDisableEx -#define MAP_ADCIntDisableEx \ - ROM_ADCIntDisableEx -#else -#define MAP_ADCIntDisableEx \ - ADCIntDisableEx -#endif -#ifdef ROM_ADCIntEnableEx -#define MAP_ADCIntEnableEx \ - ROM_ADCIntEnableEx -#else -#define MAP_ADCIntEnableEx \ - ADCIntEnableEx -#endif -#ifdef ROM_ADCIntStatusEx -#define MAP_ADCIntStatusEx \ - ROM_ADCIntStatusEx -#else -#define MAP_ADCIntStatusEx \ - ADCIntStatusEx -#endif -#ifdef ROM_ADCSequenceDMAEnable -#define MAP_ADCSequenceDMAEnable \ - ROM_ADCSequenceDMAEnable -#else -#define MAP_ADCSequenceDMAEnable \ - ADCSequenceDMAEnable -#endif -#ifdef ROM_ADCSequenceDMADisable -#define MAP_ADCSequenceDMADisable \ - ROM_ADCSequenceDMADisable -#else -#define MAP_ADCSequenceDMADisable \ - ADCSequenceDMADisable -#endif -#ifdef ROM_ADCBusy -#define MAP_ADCBusy \ - ROM_ADCBusy -#else -#define MAP_ADCBusy \ - ADCBusy -#endif - -//***************************************************************************** -// -// Macros for the AES API. -// -//***************************************************************************** -#ifdef ROM_AESIntStatus -#define MAP_AESIntStatus \ - ROM_AESIntStatus -#else -#define MAP_AESIntStatus \ - AESIntStatus -#endif -#ifdef ROM_AESAuthLengthSet -#define MAP_AESAuthLengthSet \ - ROM_AESAuthLengthSet -#else -#define MAP_AESAuthLengthSet \ - AESAuthLengthSet -#endif -#ifdef ROM_AESConfigSet -#define MAP_AESConfigSet \ - ROM_AESConfigSet -#else -#define MAP_AESConfigSet \ - AESConfigSet -#endif -#ifdef ROM_AESDataAuth -#define MAP_AESDataAuth \ - ROM_AESDataAuth -#else -#define MAP_AESDataAuth \ - AESDataAuth -#endif -#ifdef ROM_AESDataProcess -#define MAP_AESDataProcess \ - ROM_AESDataProcess -#else -#define MAP_AESDataProcess \ - AESDataProcess -#endif -#ifdef ROM_AESDataProcessAuth -#define MAP_AESDataProcessAuth \ - ROM_AESDataProcessAuth -#else -#define MAP_AESDataProcessAuth \ - AESDataProcessAuth -#endif -#ifdef ROM_AESDataRead -#define MAP_AESDataRead \ - ROM_AESDataRead -#else -#define MAP_AESDataRead \ - AESDataRead -#endif -#ifdef ROM_AESDataReadNonBlocking -#define MAP_AESDataReadNonBlocking \ - ROM_AESDataReadNonBlocking -#else -#define MAP_AESDataReadNonBlocking \ - AESDataReadNonBlocking -#endif -#ifdef ROM_AESDataWrite -#define MAP_AESDataWrite \ - ROM_AESDataWrite -#else -#define MAP_AESDataWrite \ - AESDataWrite -#endif -#ifdef ROM_AESDataWriteNonBlocking -#define MAP_AESDataWriteNonBlocking \ - ROM_AESDataWriteNonBlocking -#else -#define MAP_AESDataWriteNonBlocking \ - AESDataWriteNonBlocking -#endif -#ifdef ROM_AESDMADisable -#define MAP_AESDMADisable \ - ROM_AESDMADisable -#else -#define MAP_AESDMADisable \ - AESDMADisable -#endif -#ifdef ROM_AESDMAEnable -#define MAP_AESDMAEnable \ - ROM_AESDMAEnable -#else -#define MAP_AESDMAEnable \ - AESDMAEnable -#endif -#ifdef ROM_AESIntClear -#define MAP_AESIntClear \ - ROM_AESIntClear -#else -#define MAP_AESIntClear \ - AESIntClear -#endif -#ifdef ROM_AESIntDisable -#define MAP_AESIntDisable \ - ROM_AESIntDisable -#else -#define MAP_AESIntDisable \ - AESIntDisable -#endif -#ifdef ROM_AESIntEnable -#define MAP_AESIntEnable \ - ROM_AESIntEnable -#else -#define MAP_AESIntEnable \ - AESIntEnable -#endif -#ifdef ROM_AESIVSet -#define MAP_AESIVSet \ - ROM_AESIVSet -#else -#define MAP_AESIVSet \ - AESIVSet -#endif -#ifdef ROM_AESKey1Set -#define MAP_AESKey1Set \ - ROM_AESKey1Set -#else -#define MAP_AESKey1Set \ - AESKey1Set -#endif -#ifdef ROM_AESKey2Set -#define MAP_AESKey2Set \ - ROM_AESKey2Set -#else -#define MAP_AESKey2Set \ - AESKey2Set -#endif -#ifdef ROM_AESKey3Set -#define MAP_AESKey3Set \ - ROM_AESKey3Set -#else -#define MAP_AESKey3Set \ - AESKey3Set -#endif -#ifdef ROM_AESLengthSet -#define MAP_AESLengthSet \ - ROM_AESLengthSet -#else -#define MAP_AESLengthSet \ - AESLengthSet -#endif -#ifdef ROM_AESReset -#define MAP_AESReset \ - ROM_AESReset -#else -#define MAP_AESReset \ - AESReset -#endif -#ifdef ROM_AESTagRead -#define MAP_AESTagRead \ - ROM_AESTagRead -#else -#define MAP_AESTagRead \ - AESTagRead -#endif -#ifdef ROM_AESIVRead -#define MAP_AESIVRead \ - ROM_AESIVRead -#else -#define MAP_AESIVRead \ - AESIVRead -#endif - -//***************************************************************************** -// -// Macros for the CAN API. -// -//***************************************************************************** -#ifdef ROM_CANIntClear -#define MAP_CANIntClear \ - ROM_CANIntClear -#else -#define MAP_CANIntClear \ - CANIntClear -#endif -#ifdef ROM_CANInit -#define MAP_CANInit \ - ROM_CANInit -#else -#define MAP_CANInit \ - CANInit -#endif -#ifdef ROM_CANEnable -#define MAP_CANEnable \ - ROM_CANEnable -#else -#define MAP_CANEnable \ - CANEnable -#endif -#ifdef ROM_CANDisable -#define MAP_CANDisable \ - ROM_CANDisable -#else -#define MAP_CANDisable \ - CANDisable -#endif -#ifdef ROM_CANBitTimingSet -#define MAP_CANBitTimingSet \ - ROM_CANBitTimingSet -#else -#define MAP_CANBitTimingSet \ - CANBitTimingSet -#endif -#ifdef ROM_CANBitTimingGet -#define MAP_CANBitTimingGet \ - ROM_CANBitTimingGet -#else -#define MAP_CANBitTimingGet \ - CANBitTimingGet -#endif -#ifdef ROM_CANMessageSet -#define MAP_CANMessageSet \ - ROM_CANMessageSet -#else -#define MAP_CANMessageSet \ - CANMessageSet -#endif -#ifdef ROM_CANMessageGet -#define MAP_CANMessageGet \ - ROM_CANMessageGet -#else -#define MAP_CANMessageGet \ - CANMessageGet -#endif -#ifdef ROM_CANStatusGet -#define MAP_CANStatusGet \ - ROM_CANStatusGet -#else -#define MAP_CANStatusGet \ - CANStatusGet -#endif -#ifdef ROM_CANMessageClear -#define MAP_CANMessageClear \ - ROM_CANMessageClear -#else -#define MAP_CANMessageClear \ - CANMessageClear -#endif -#ifdef ROM_CANIntEnable -#define MAP_CANIntEnable \ - ROM_CANIntEnable -#else -#define MAP_CANIntEnable \ - CANIntEnable -#endif -#ifdef ROM_CANIntDisable -#define MAP_CANIntDisable \ - ROM_CANIntDisable -#else -#define MAP_CANIntDisable \ - CANIntDisable -#endif -#ifdef ROM_CANIntStatus -#define MAP_CANIntStatus \ - ROM_CANIntStatus -#else -#define MAP_CANIntStatus \ - CANIntStatus -#endif -#ifdef ROM_CANRetryGet -#define MAP_CANRetryGet \ - ROM_CANRetryGet -#else -#define MAP_CANRetryGet \ - CANRetryGet -#endif -#ifdef ROM_CANRetrySet -#define MAP_CANRetrySet \ - ROM_CANRetrySet -#else -#define MAP_CANRetrySet \ - CANRetrySet -#endif -#ifdef ROM_CANErrCntrGet -#define MAP_CANErrCntrGet \ - ROM_CANErrCntrGet -#else -#define MAP_CANErrCntrGet \ - CANErrCntrGet -#endif -#ifdef ROM_CANBitRateSet -#define MAP_CANBitRateSet \ - ROM_CANBitRateSet -#else -#define MAP_CANBitRateSet \ - CANBitRateSet -#endif - -//***************************************************************************** -// -// Macros for the Comparator API. -// -//***************************************************************************** -#ifdef ROM_ComparatorIntClear -#define MAP_ComparatorIntClear \ - ROM_ComparatorIntClear -#else -#define MAP_ComparatorIntClear \ - ComparatorIntClear -#endif -#ifdef ROM_ComparatorConfigure -#define MAP_ComparatorConfigure \ - ROM_ComparatorConfigure -#else -#define MAP_ComparatorConfigure \ - ComparatorConfigure -#endif -#ifdef ROM_ComparatorRefSet -#define MAP_ComparatorRefSet \ - ROM_ComparatorRefSet -#else -#define MAP_ComparatorRefSet \ - ComparatorRefSet -#endif -#ifdef ROM_ComparatorValueGet -#define MAP_ComparatorValueGet \ - ROM_ComparatorValueGet -#else -#define MAP_ComparatorValueGet \ - ComparatorValueGet -#endif -#ifdef ROM_ComparatorIntEnable -#define MAP_ComparatorIntEnable \ - ROM_ComparatorIntEnable -#else -#define MAP_ComparatorIntEnable \ - ComparatorIntEnable -#endif -#ifdef ROM_ComparatorIntDisable -#define MAP_ComparatorIntDisable \ - ROM_ComparatorIntDisable -#else -#define MAP_ComparatorIntDisable \ - ComparatorIntDisable -#endif -#ifdef ROM_ComparatorIntStatus -#define MAP_ComparatorIntStatus \ - ROM_ComparatorIntStatus -#else -#define MAP_ComparatorIntStatus \ - ComparatorIntStatus -#endif - -//***************************************************************************** -// -// Macros for the CRC API. -// -//***************************************************************************** -#ifdef ROM_CRCConfigSet -#define MAP_CRCConfigSet \ - ROM_CRCConfigSet -#else -#define MAP_CRCConfigSet \ - CRCConfigSet -#endif -#ifdef ROM_CRCDataProcess -#define MAP_CRCDataProcess \ - ROM_CRCDataProcess -#else -#define MAP_CRCDataProcess \ - CRCDataProcess -#endif -#ifdef ROM_CRCDataWrite -#define MAP_CRCDataWrite \ - ROM_CRCDataWrite -#else -#define MAP_CRCDataWrite \ - CRCDataWrite -#endif -#ifdef ROM_CRCResultRead -#define MAP_CRCResultRead \ - ROM_CRCResultRead -#else -#define MAP_CRCResultRead \ - CRCResultRead -#endif -#ifdef ROM_CRCSeedSet -#define MAP_CRCSeedSet \ - ROM_CRCSeedSet -#else -#define MAP_CRCSeedSet \ - CRCSeedSet -#endif - -//***************************************************************************** -// -// Macros for the DES API. -// -//***************************************************************************** -#ifdef ROM_DESIntStatus -#define MAP_DESIntStatus \ - ROM_DESIntStatus -#else -#define MAP_DESIntStatus \ - DESIntStatus -#endif -#ifdef ROM_DESConfigSet -#define MAP_DESConfigSet \ - ROM_DESConfigSet -#else -#define MAP_DESConfigSet \ - DESConfigSet -#endif -#ifdef ROM_DESDataRead -#define MAP_DESDataRead \ - ROM_DESDataRead -#else -#define MAP_DESDataRead \ - DESDataRead -#endif -#ifdef ROM_DESDataReadNonBlocking -#define MAP_DESDataReadNonBlocking \ - ROM_DESDataReadNonBlocking -#else -#define MAP_DESDataReadNonBlocking \ - DESDataReadNonBlocking -#endif -#ifdef ROM_DESDataProcess -#define MAP_DESDataProcess \ - ROM_DESDataProcess -#else -#define MAP_DESDataProcess \ - DESDataProcess -#endif -#ifdef ROM_DESDataWrite -#define MAP_DESDataWrite \ - ROM_DESDataWrite -#else -#define MAP_DESDataWrite \ - DESDataWrite -#endif -#ifdef ROM_DESDataWriteNonBlocking -#define MAP_DESDataWriteNonBlocking \ - ROM_DESDataWriteNonBlocking -#else -#define MAP_DESDataWriteNonBlocking \ - DESDataWriteNonBlocking -#endif -#ifdef ROM_DESDMADisable -#define MAP_DESDMADisable \ - ROM_DESDMADisable -#else -#define MAP_DESDMADisable \ - DESDMADisable -#endif -#ifdef ROM_DESDMAEnable -#define MAP_DESDMAEnable \ - ROM_DESDMAEnable -#else -#define MAP_DESDMAEnable \ - DESDMAEnable -#endif -#ifdef ROM_DESIntClear -#define MAP_DESIntClear \ - ROM_DESIntClear -#else -#define MAP_DESIntClear \ - DESIntClear -#endif -#ifdef ROM_DESIntDisable -#define MAP_DESIntDisable \ - ROM_DESIntDisable -#else -#define MAP_DESIntDisable \ - DESIntDisable -#endif -#ifdef ROM_DESIntEnable -#define MAP_DESIntEnable \ - ROM_DESIntEnable -#else -#define MAP_DESIntEnable \ - DESIntEnable -#endif -#ifdef ROM_DESIVSet -#define MAP_DESIVSet \ - ROM_DESIVSet -#else -#define MAP_DESIVSet \ - DESIVSet -#endif -#ifdef ROM_DESKeySet -#define MAP_DESKeySet \ - ROM_DESKeySet -#else -#define MAP_DESKeySet \ - DESKeySet -#endif -#ifdef ROM_DESLengthSet -#define MAP_DESLengthSet \ - ROM_DESLengthSet -#else -#define MAP_DESLengthSet \ - DESLengthSet -#endif -#ifdef ROM_DESReset -#define MAP_DESReset \ - ROM_DESReset -#else -#define MAP_DESReset \ - DESReset -#endif - -//***************************************************************************** -// -// Macros for the EEPROM API. -// -//***************************************************************************** -#ifdef ROM_EEPROMRead -#define MAP_EEPROMRead \ - ROM_EEPROMRead -#else -#define MAP_EEPROMRead \ - EEPROMRead -#endif -#ifdef ROM_EEPROMBlockCountGet -#define MAP_EEPROMBlockCountGet \ - ROM_EEPROMBlockCountGet -#else -#define MAP_EEPROMBlockCountGet \ - EEPROMBlockCountGet -#endif -#ifdef ROM_EEPROMBlockHide -#define MAP_EEPROMBlockHide \ - ROM_EEPROMBlockHide -#else -#define MAP_EEPROMBlockHide \ - EEPROMBlockHide -#endif -#ifdef ROM_EEPROMBlockLock -#define MAP_EEPROMBlockLock \ - ROM_EEPROMBlockLock -#else -#define MAP_EEPROMBlockLock \ - EEPROMBlockLock -#endif -#ifdef ROM_EEPROMBlockPasswordSet -#define MAP_EEPROMBlockPasswordSet \ - ROM_EEPROMBlockPasswordSet -#else -#define MAP_EEPROMBlockPasswordSet \ - EEPROMBlockPasswordSet -#endif -#ifdef ROM_EEPROMBlockProtectGet -#define MAP_EEPROMBlockProtectGet \ - ROM_EEPROMBlockProtectGet -#else -#define MAP_EEPROMBlockProtectGet \ - EEPROMBlockProtectGet -#endif -#ifdef ROM_EEPROMBlockProtectSet -#define MAP_EEPROMBlockProtectSet \ - ROM_EEPROMBlockProtectSet -#else -#define MAP_EEPROMBlockProtectSet \ - EEPROMBlockProtectSet -#endif -#ifdef ROM_EEPROMBlockUnlock -#define MAP_EEPROMBlockUnlock \ - ROM_EEPROMBlockUnlock -#else -#define MAP_EEPROMBlockUnlock \ - EEPROMBlockUnlock -#endif -#ifdef ROM_EEPROMIntClear -#define MAP_EEPROMIntClear \ - ROM_EEPROMIntClear -#else -#define MAP_EEPROMIntClear \ - EEPROMIntClear -#endif -#ifdef ROM_EEPROMIntDisable -#define MAP_EEPROMIntDisable \ - ROM_EEPROMIntDisable -#else -#define MAP_EEPROMIntDisable \ - EEPROMIntDisable -#endif -#ifdef ROM_EEPROMIntEnable -#define MAP_EEPROMIntEnable \ - ROM_EEPROMIntEnable -#else -#define MAP_EEPROMIntEnable \ - EEPROMIntEnable -#endif -#ifdef ROM_EEPROMIntStatus -#define MAP_EEPROMIntStatus \ - ROM_EEPROMIntStatus -#else -#define MAP_EEPROMIntStatus \ - EEPROMIntStatus -#endif -#ifdef ROM_EEPROMMassErase -#define MAP_EEPROMMassErase \ - ROM_EEPROMMassErase -#else -#define MAP_EEPROMMassErase \ - EEPROMMassErase -#endif -#ifdef ROM_EEPROMProgram -#define MAP_EEPROMProgram \ - ROM_EEPROMProgram -#else -#define MAP_EEPROMProgram \ - EEPROMProgram -#endif -#ifdef ROM_EEPROMProgramNonBlocking -#define MAP_EEPROMProgramNonBlocking \ - ROM_EEPROMProgramNonBlocking -#else -#define MAP_EEPROMProgramNonBlocking \ - EEPROMProgramNonBlocking -#endif -#ifdef ROM_EEPROMSizeGet -#define MAP_EEPROMSizeGet \ - ROM_EEPROMSizeGet -#else -#define MAP_EEPROMSizeGet \ - EEPROMSizeGet -#endif -#ifdef ROM_EEPROMStatusGet -#define MAP_EEPROMStatusGet \ - ROM_EEPROMStatusGet -#else -#define MAP_EEPROMStatusGet \ - EEPROMStatusGet -#endif -#ifdef ROM_EEPROMInit -#define MAP_EEPROMInit \ - ROM_EEPROMInit -#else -#define MAP_EEPROMInit \ - EEPROMInit -#endif - -//***************************************************************************** -// -// Macros for the EPI API. -// -//***************************************************************************** -#ifdef ROM_EPIIntStatus -#define MAP_EPIIntStatus \ - ROM_EPIIntStatus -#else -#define MAP_EPIIntStatus \ - EPIIntStatus -#endif -#ifdef ROM_EPIModeSet -#define MAP_EPIModeSet \ - ROM_EPIModeSet -#else -#define MAP_EPIModeSet \ - EPIModeSet -#endif -#ifdef ROM_EPIDividerSet -#define MAP_EPIDividerSet \ - ROM_EPIDividerSet -#else -#define MAP_EPIDividerSet \ - EPIDividerSet -#endif -#ifdef ROM_EPIConfigSDRAMSet -#define MAP_EPIConfigSDRAMSet \ - ROM_EPIConfigSDRAMSet -#else -#define MAP_EPIConfigSDRAMSet \ - EPIConfigSDRAMSet -#endif -#ifdef ROM_EPIConfigGPModeSet -#define MAP_EPIConfigGPModeSet \ - ROM_EPIConfigGPModeSet -#else -#define MAP_EPIConfigGPModeSet \ - EPIConfigGPModeSet -#endif -#ifdef ROM_EPIConfigHB8Set -#define MAP_EPIConfigHB8Set \ - ROM_EPIConfigHB8Set -#else -#define MAP_EPIConfigHB8Set \ - EPIConfigHB8Set -#endif -#ifdef ROM_EPIConfigHB16Set -#define MAP_EPIConfigHB16Set \ - ROM_EPIConfigHB16Set -#else -#define MAP_EPIConfigHB16Set \ - EPIConfigHB16Set -#endif -#ifdef ROM_EPIAddressMapSet -#define MAP_EPIAddressMapSet \ - ROM_EPIAddressMapSet -#else -#define MAP_EPIAddressMapSet \ - EPIAddressMapSet -#endif -#ifdef ROM_EPINonBlockingReadConfigure -#define MAP_EPINonBlockingReadConfigure \ - ROM_EPINonBlockingReadConfigure -#else -#define MAP_EPINonBlockingReadConfigure \ - EPINonBlockingReadConfigure -#endif -#ifdef ROM_EPINonBlockingReadStart -#define MAP_EPINonBlockingReadStart \ - ROM_EPINonBlockingReadStart -#else -#define MAP_EPINonBlockingReadStart \ - EPINonBlockingReadStart -#endif -#ifdef ROM_EPINonBlockingReadStop -#define MAP_EPINonBlockingReadStop \ - ROM_EPINonBlockingReadStop -#else -#define MAP_EPINonBlockingReadStop \ - EPINonBlockingReadStop -#endif -#ifdef ROM_EPINonBlockingReadCount -#define MAP_EPINonBlockingReadCount \ - ROM_EPINonBlockingReadCount -#else -#define MAP_EPINonBlockingReadCount \ - EPINonBlockingReadCount -#endif -#ifdef ROM_EPINonBlockingReadAvail -#define MAP_EPINonBlockingReadAvail \ - ROM_EPINonBlockingReadAvail -#else -#define MAP_EPINonBlockingReadAvail \ - EPINonBlockingReadAvail -#endif -#ifdef ROM_EPINonBlockingReadGet32 -#define MAP_EPINonBlockingReadGet32 \ - ROM_EPINonBlockingReadGet32 -#else -#define MAP_EPINonBlockingReadGet32 \ - EPINonBlockingReadGet32 -#endif -#ifdef ROM_EPINonBlockingReadGet16 -#define MAP_EPINonBlockingReadGet16 \ - ROM_EPINonBlockingReadGet16 -#else -#define MAP_EPINonBlockingReadGet16 \ - EPINonBlockingReadGet16 -#endif -#ifdef ROM_EPINonBlockingReadGet8 -#define MAP_EPINonBlockingReadGet8 \ - ROM_EPINonBlockingReadGet8 -#else -#define MAP_EPINonBlockingReadGet8 \ - EPINonBlockingReadGet8 -#endif -#ifdef ROM_EPIFIFOConfig -#define MAP_EPIFIFOConfig \ - ROM_EPIFIFOConfig -#else -#define MAP_EPIFIFOConfig \ - EPIFIFOConfig -#endif -#ifdef ROM_EPIWriteFIFOCountGet -#define MAP_EPIWriteFIFOCountGet \ - ROM_EPIWriteFIFOCountGet -#else -#define MAP_EPIWriteFIFOCountGet \ - EPIWriteFIFOCountGet -#endif -#ifdef ROM_EPIIntEnable -#define MAP_EPIIntEnable \ - ROM_EPIIntEnable -#else -#define MAP_EPIIntEnable \ - EPIIntEnable -#endif -#ifdef ROM_EPIIntDisable -#define MAP_EPIIntDisable \ - ROM_EPIIntDisable -#else -#define MAP_EPIIntDisable \ - EPIIntDisable -#endif -#ifdef ROM_EPIIntErrorStatus -#define MAP_EPIIntErrorStatus \ - ROM_EPIIntErrorStatus -#else -#define MAP_EPIIntErrorStatus \ - EPIIntErrorStatus -#endif -#ifdef ROM_EPIIntErrorClear -#define MAP_EPIIntErrorClear \ - ROM_EPIIntErrorClear -#else -#define MAP_EPIIntErrorClear \ - EPIIntErrorClear -#endif -#ifdef ROM_EPIDividerCSSet -#define MAP_EPIDividerCSSet \ - ROM_EPIDividerCSSet -#else -#define MAP_EPIDividerCSSet \ - EPIDividerCSSet -#endif -#ifdef ROM_EPIDMATxCount -#define MAP_EPIDMATxCount \ - ROM_EPIDMATxCount -#else -#define MAP_EPIDMATxCount \ - EPIDMATxCount -#endif -#ifdef ROM_EPIConfigHB8CSSet -#define MAP_EPIConfigHB8CSSet \ - ROM_EPIConfigHB8CSSet -#else -#define MAP_EPIConfigHB8CSSet \ - EPIConfigHB8CSSet -#endif -#ifdef ROM_EPIConfigHB16CSSet -#define MAP_EPIConfigHB16CSSet \ - ROM_EPIConfigHB16CSSet -#else -#define MAP_EPIConfigHB16CSSet \ - EPIConfigHB16CSSet -#endif -#ifdef ROM_EPIConfigHB8TimingSet -#define MAP_EPIConfigHB8TimingSet \ - ROM_EPIConfigHB8TimingSet -#else -#define MAP_EPIConfigHB8TimingSet \ - EPIConfigHB8TimingSet -#endif -#ifdef ROM_EPIConfigHB16TimingSet -#define MAP_EPIConfigHB16TimingSet \ - ROM_EPIConfigHB16TimingSet -#else -#define MAP_EPIConfigHB16TimingSet \ - EPIConfigHB16TimingSet -#endif -#ifdef ROM_EPIPSRAMConfigRegSet -#define MAP_EPIPSRAMConfigRegSet \ - ROM_EPIPSRAMConfigRegSet -#else -#define MAP_EPIPSRAMConfigRegSet \ - EPIPSRAMConfigRegSet -#endif -#ifdef ROM_EPIPSRAMConfigRegRead -#define MAP_EPIPSRAMConfigRegRead \ - ROM_EPIPSRAMConfigRegRead -#else -#define MAP_EPIPSRAMConfigRegRead \ - EPIPSRAMConfigRegRead -#endif -#ifdef ROM_EPIPSRAMConfigRegGetNonBlocking -#define MAP_EPIPSRAMConfigRegGetNonBlocking \ - ROM_EPIPSRAMConfigRegGetNonBlocking -#else -#define MAP_EPIPSRAMConfigRegGetNonBlocking \ - EPIPSRAMConfigRegGetNonBlocking -#endif -#ifdef ROM_EPIPSRAMConfigRegGet -#define MAP_EPIPSRAMConfigRegGet \ - ROM_EPIPSRAMConfigRegGet -#else -#define MAP_EPIPSRAMConfigRegGet \ - EPIPSRAMConfigRegGet -#endif - -//***************************************************************************** -// -// Macros for the EMAC API. -// -//***************************************************************************** -#ifdef ROM_EMACIntStatus -#define MAP_EMACIntStatus \ - ROM_EMACIntStatus -#else -#define MAP_EMACIntStatus \ - EMACIntStatus -#endif -#ifdef ROM_EMACAddrGet -#define MAP_EMACAddrGet \ - ROM_EMACAddrGet -#else -#define MAP_EMACAddrGet \ - EMACAddrGet -#endif -#ifdef ROM_EMACAddrSet -#define MAP_EMACAddrSet \ - ROM_EMACAddrSet -#else -#define MAP_EMACAddrSet \ - EMACAddrSet -#endif -#ifdef ROM_EMACConfigGet -#define MAP_EMACConfigGet \ - ROM_EMACConfigGet -#else -#define MAP_EMACConfigGet \ - EMACConfigGet -#endif -#ifdef ROM_EMACConfigSet -#define MAP_EMACConfigSet \ - ROM_EMACConfigSet -#else -#define MAP_EMACConfigSet \ - EMACConfigSet -#endif -#ifdef ROM_EMACDMAStateGet -#define MAP_EMACDMAStateGet \ - ROM_EMACDMAStateGet -#else -#define MAP_EMACDMAStateGet \ - EMACDMAStateGet -#endif -#ifdef ROM_EMACFrameFilterGet -#define MAP_EMACFrameFilterGet \ - ROM_EMACFrameFilterGet -#else -#define MAP_EMACFrameFilterGet \ - EMACFrameFilterGet -#endif -#ifdef ROM_EMACFrameFilterSet -#define MAP_EMACFrameFilterSet \ - ROM_EMACFrameFilterSet -#else -#define MAP_EMACFrameFilterSet \ - EMACFrameFilterSet -#endif -#ifdef ROM_EMACInit -#define MAP_EMACInit \ - ROM_EMACInit -#else -#define MAP_EMACInit \ - EMACInit -#endif -#ifdef ROM_EMACIntClear -#define MAP_EMACIntClear \ - ROM_EMACIntClear -#else -#define MAP_EMACIntClear \ - EMACIntClear -#endif -#ifdef ROM_EMACIntDisable -#define MAP_EMACIntDisable \ - ROM_EMACIntDisable -#else -#define MAP_EMACIntDisable \ - EMACIntDisable -#endif -#ifdef ROM_EMACIntEnable -#define MAP_EMACIntEnable \ - ROM_EMACIntEnable -#else -#define MAP_EMACIntEnable \ - EMACIntEnable -#endif -#ifdef ROM_EMACPHYConfigSet -#define MAP_EMACPHYConfigSet \ - ROM_EMACPHYConfigSet -#else -#define MAP_EMACPHYConfigSet \ - EMACPHYConfigSet -#endif -#ifdef ROM_EMACPHYPowerOff -#define MAP_EMACPHYPowerOff \ - ROM_EMACPHYPowerOff -#else -#define MAP_EMACPHYPowerOff \ - EMACPHYPowerOff -#endif -#ifdef ROM_EMACPHYPowerOn -#define MAP_EMACPHYPowerOn \ - ROM_EMACPHYPowerOn -#else -#define MAP_EMACPHYPowerOn \ - EMACPHYPowerOn -#endif -#ifdef ROM_EMACPHYRead -#define MAP_EMACPHYRead \ - ROM_EMACPHYRead -#else -#define MAP_EMACPHYRead \ - EMACPHYRead -#endif -#ifdef ROM_EMACPHYWrite -#define MAP_EMACPHYWrite \ - ROM_EMACPHYWrite -#else -#define MAP_EMACPHYWrite \ - EMACPHYWrite -#endif -#ifdef ROM_EMACReset -#define MAP_EMACReset \ - ROM_EMACReset -#else -#define MAP_EMACReset \ - EMACReset -#endif -#ifdef ROM_EMACRxDisable -#define MAP_EMACRxDisable \ - ROM_EMACRxDisable -#else -#define MAP_EMACRxDisable \ - EMACRxDisable -#endif -#ifdef ROM_EMACRxDMACurrentBufferGet -#define MAP_EMACRxDMACurrentBufferGet \ - ROM_EMACRxDMACurrentBufferGet -#else -#define MAP_EMACRxDMACurrentBufferGet \ - EMACRxDMACurrentBufferGet -#endif -#ifdef ROM_EMACRxDMACurrentDescriptorGet -#define MAP_EMACRxDMACurrentDescriptorGet \ - ROM_EMACRxDMACurrentDescriptorGet -#else -#define MAP_EMACRxDMACurrentDescriptorGet \ - EMACRxDMACurrentDescriptorGet -#endif -#ifdef ROM_EMACRxDMADescriptorListGet -#define MAP_EMACRxDMADescriptorListGet \ - ROM_EMACRxDMADescriptorListGet -#else -#define MAP_EMACRxDMADescriptorListGet \ - EMACRxDMADescriptorListGet -#endif -#ifdef ROM_EMACRxDMADescriptorListSet -#define MAP_EMACRxDMADescriptorListSet \ - ROM_EMACRxDMADescriptorListSet -#else -#define MAP_EMACRxDMADescriptorListSet \ - EMACRxDMADescriptorListSet -#endif -#ifdef ROM_EMACRxDMAPollDemand -#define MAP_EMACRxDMAPollDemand \ - ROM_EMACRxDMAPollDemand -#else -#define MAP_EMACRxDMAPollDemand \ - EMACRxDMAPollDemand -#endif -#ifdef ROM_EMACRxEnable -#define MAP_EMACRxEnable \ - ROM_EMACRxEnable -#else -#define MAP_EMACRxEnable \ - EMACRxEnable -#endif -#ifdef ROM_EMACRxWatchdogTimerSet -#define MAP_EMACRxWatchdogTimerSet \ - ROM_EMACRxWatchdogTimerSet -#else -#define MAP_EMACRxWatchdogTimerSet \ - EMACRxWatchdogTimerSet -#endif -#ifdef ROM_EMACStatusGet -#define MAP_EMACStatusGet \ - ROM_EMACStatusGet -#else -#define MAP_EMACStatusGet \ - EMACStatusGet -#endif -#ifdef ROM_EMACTxDisable -#define MAP_EMACTxDisable \ - ROM_EMACTxDisable -#else -#define MAP_EMACTxDisable \ - EMACTxDisable -#endif -#ifdef ROM_EMACTxDMACurrentBufferGet -#define MAP_EMACTxDMACurrentBufferGet \ - ROM_EMACTxDMACurrentBufferGet -#else -#define MAP_EMACTxDMACurrentBufferGet \ - EMACTxDMACurrentBufferGet -#endif -#ifdef ROM_EMACTxDMACurrentDescriptorGet -#define MAP_EMACTxDMACurrentDescriptorGet \ - ROM_EMACTxDMACurrentDescriptorGet -#else -#define MAP_EMACTxDMACurrentDescriptorGet \ - EMACTxDMACurrentDescriptorGet -#endif -#ifdef ROM_EMACTxDMADescriptorListGet -#define MAP_EMACTxDMADescriptorListGet \ - ROM_EMACTxDMADescriptorListGet -#else -#define MAP_EMACTxDMADescriptorListGet \ - EMACTxDMADescriptorListGet -#endif -#ifdef ROM_EMACTxDMADescriptorListSet -#define MAP_EMACTxDMADescriptorListSet \ - ROM_EMACTxDMADescriptorListSet -#else -#define MAP_EMACTxDMADescriptorListSet \ - EMACTxDMADescriptorListSet -#endif -#ifdef ROM_EMACTxDMAPollDemand -#define MAP_EMACTxDMAPollDemand \ - ROM_EMACTxDMAPollDemand -#else -#define MAP_EMACTxDMAPollDemand \ - EMACTxDMAPollDemand -#endif -#ifdef ROM_EMACTxEnable -#define MAP_EMACTxEnable \ - ROM_EMACTxEnable -#else -#define MAP_EMACTxEnable \ - EMACTxEnable -#endif -#ifdef ROM_EMACTxFlush -#define MAP_EMACTxFlush \ - ROM_EMACTxFlush -#else -#define MAP_EMACTxFlush \ - EMACTxFlush -#endif -#ifdef ROM_EMACAddrFilterGet -#define MAP_EMACAddrFilterGet \ - ROM_EMACAddrFilterGet -#else -#define MAP_EMACAddrFilterGet \ - EMACAddrFilterGet -#endif -#ifdef ROM_EMACAddrFilterSet -#define MAP_EMACAddrFilterSet \ - ROM_EMACAddrFilterSet -#else -#define MAP_EMACAddrFilterSet \ - EMACAddrFilterSet -#endif -#ifdef ROM_EMACHashFilterBitCalculate -#define MAP_EMACHashFilterBitCalculate \ - ROM_EMACHashFilterBitCalculate -#else -#define MAP_EMACHashFilterBitCalculate \ - EMACHashFilterBitCalculate -#endif -#ifdef ROM_EMACHashFilterGet -#define MAP_EMACHashFilterGet \ - ROM_EMACHashFilterGet -#else -#define MAP_EMACHashFilterGet \ - EMACHashFilterGet -#endif -#ifdef ROM_EMACHashFilterSet -#define MAP_EMACHashFilterSet \ - ROM_EMACHashFilterSet -#else -#define MAP_EMACHashFilterSet \ - EMACHashFilterSet -#endif -#ifdef ROM_EMACNumAddrGet -#define MAP_EMACNumAddrGet \ - ROM_EMACNumAddrGet -#else -#define MAP_EMACNumAddrGet \ - EMACNumAddrGet -#endif -#ifdef ROM_EMACPHYExtendedRead -#define MAP_EMACPHYExtendedRead \ - ROM_EMACPHYExtendedRead -#else -#define MAP_EMACPHYExtendedRead \ - EMACPHYExtendedRead -#endif -#ifdef ROM_EMACPHYExtendedWrite -#define MAP_EMACPHYExtendedWrite \ - ROM_EMACPHYExtendedWrite -#else -#define MAP_EMACPHYExtendedWrite \ - EMACPHYExtendedWrite -#endif -#ifdef ROM_EMACPowerManagementControlGet -#define MAP_EMACPowerManagementControlGet \ - ROM_EMACPowerManagementControlGet -#else -#define MAP_EMACPowerManagementControlGet \ - EMACPowerManagementControlGet -#endif -#ifdef ROM_EMACPowerManagementControlSet -#define MAP_EMACPowerManagementControlSet \ - ROM_EMACPowerManagementControlSet -#else -#define MAP_EMACPowerManagementControlSet \ - EMACPowerManagementControlSet -#endif -#ifdef ROM_EMACPowerManagementStatusGet -#define MAP_EMACPowerManagementStatusGet \ - ROM_EMACPowerManagementStatusGet -#else -#define MAP_EMACPowerManagementStatusGet \ - EMACPowerManagementStatusGet -#endif -#ifdef ROM_EMACRemoteWakeUpFrameFilterGet -#define MAP_EMACRemoteWakeUpFrameFilterGet \ - ROM_EMACRemoteWakeUpFrameFilterGet -#else -#define MAP_EMACRemoteWakeUpFrameFilterGet \ - EMACRemoteWakeUpFrameFilterGet -#endif -#ifdef ROM_EMACRemoteWakeUpFrameFilterSet -#define MAP_EMACRemoteWakeUpFrameFilterSet \ - ROM_EMACRemoteWakeUpFrameFilterSet -#else -#define MAP_EMACRemoteWakeUpFrameFilterSet \ - EMACRemoteWakeUpFrameFilterSet -#endif -#ifdef ROM_EMACTimestampAddendSet -#define MAP_EMACTimestampAddendSet \ - ROM_EMACTimestampAddendSet -#else -#define MAP_EMACTimestampAddendSet \ - EMACTimestampAddendSet -#endif -#ifdef ROM_EMACTimestampConfigGet -#define MAP_EMACTimestampConfigGet \ - ROM_EMACTimestampConfigGet -#else -#define MAP_EMACTimestampConfigGet \ - EMACTimestampConfigGet -#endif -#ifdef ROM_EMACTimestampConfigSet -#define MAP_EMACTimestampConfigSet \ - ROM_EMACTimestampConfigSet -#else -#define MAP_EMACTimestampConfigSet \ - EMACTimestampConfigSet -#endif -#ifdef ROM_EMACTimestampDisable -#define MAP_EMACTimestampDisable \ - ROM_EMACTimestampDisable -#else -#define MAP_EMACTimestampDisable \ - EMACTimestampDisable -#endif -#ifdef ROM_EMACTimestampEnable -#define MAP_EMACTimestampEnable \ - ROM_EMACTimestampEnable -#else -#define MAP_EMACTimestampEnable \ - EMACTimestampEnable -#endif -#ifdef ROM_EMACTimestampIntStatus -#define MAP_EMACTimestampIntStatus \ - ROM_EMACTimestampIntStatus -#else -#define MAP_EMACTimestampIntStatus \ - EMACTimestampIntStatus -#endif -#ifdef ROM_EMACTimestampPPSCommand -#define MAP_EMACTimestampPPSCommand \ - ROM_EMACTimestampPPSCommand -#else -#define MAP_EMACTimestampPPSCommand \ - EMACTimestampPPSCommand -#endif -#ifdef ROM_EMACTimestampPPSCommandModeSet -#define MAP_EMACTimestampPPSCommandModeSet \ - ROM_EMACTimestampPPSCommandModeSet -#else -#define MAP_EMACTimestampPPSCommandModeSet \ - EMACTimestampPPSCommandModeSet -#endif -#ifdef ROM_EMACTimestampPPSPeriodSet -#define MAP_EMACTimestampPPSPeriodSet \ - ROM_EMACTimestampPPSPeriodSet -#else -#define MAP_EMACTimestampPPSPeriodSet \ - EMACTimestampPPSPeriodSet -#endif -#ifdef ROM_EMACTimestampPPSSimpleModeSet -#define MAP_EMACTimestampPPSSimpleModeSet \ - ROM_EMACTimestampPPSSimpleModeSet -#else -#define MAP_EMACTimestampPPSSimpleModeSet \ - EMACTimestampPPSSimpleModeSet -#endif -#ifdef ROM_EMACTimestampSysTimeGet -#define MAP_EMACTimestampSysTimeGet \ - ROM_EMACTimestampSysTimeGet -#else -#define MAP_EMACTimestampSysTimeGet \ - EMACTimestampSysTimeGet -#endif -#ifdef ROM_EMACTimestampSysTimeSet -#define MAP_EMACTimestampSysTimeSet \ - ROM_EMACTimestampSysTimeSet -#else -#define MAP_EMACTimestampSysTimeSet \ - EMACTimestampSysTimeSet -#endif -#ifdef ROM_EMACTimestampSysTimeUpdate -#define MAP_EMACTimestampSysTimeUpdate \ - ROM_EMACTimestampSysTimeUpdate -#else -#define MAP_EMACTimestampSysTimeUpdate \ - EMACTimestampSysTimeUpdate -#endif -#ifdef ROM_EMACTimestampTargetIntDisable -#define MAP_EMACTimestampTargetIntDisable \ - ROM_EMACTimestampTargetIntDisable -#else -#define MAP_EMACTimestampTargetIntDisable \ - EMACTimestampTargetIntDisable -#endif -#ifdef ROM_EMACTimestampTargetIntEnable -#define MAP_EMACTimestampTargetIntEnable \ - ROM_EMACTimestampTargetIntEnable -#else -#define MAP_EMACTimestampTargetIntEnable \ - EMACTimestampTargetIntEnable -#endif -#ifdef ROM_EMACTimestampTargetSet -#define MAP_EMACTimestampTargetSet \ - ROM_EMACTimestampTargetSet -#else -#define MAP_EMACTimestampTargetSet \ - EMACTimestampTargetSet -#endif -#ifdef ROM_EMACVLANHashFilterBitCalculate -#define MAP_EMACVLANHashFilterBitCalculate \ - ROM_EMACVLANHashFilterBitCalculate -#else -#define MAP_EMACVLANHashFilterBitCalculate \ - EMACVLANHashFilterBitCalculate -#endif -#ifdef ROM_EMACVLANHashFilterGet -#define MAP_EMACVLANHashFilterGet \ - ROM_EMACVLANHashFilterGet -#else -#define MAP_EMACVLANHashFilterGet \ - EMACVLANHashFilterGet -#endif -#ifdef ROM_EMACVLANHashFilterSet -#define MAP_EMACVLANHashFilterSet \ - ROM_EMACVLANHashFilterSet -#else -#define MAP_EMACVLANHashFilterSet \ - EMACVLANHashFilterSet -#endif -#ifdef ROM_EMACVLANRxConfigGet -#define MAP_EMACVLANRxConfigGet \ - ROM_EMACVLANRxConfigGet -#else -#define MAP_EMACVLANRxConfigGet \ - EMACVLANRxConfigGet -#endif -#ifdef ROM_EMACVLANRxConfigSet -#define MAP_EMACVLANRxConfigSet \ - ROM_EMACVLANRxConfigSet -#else -#define MAP_EMACVLANRxConfigSet \ - EMACVLANRxConfigSet -#endif -#ifdef ROM_EMACVLANTxConfigGet -#define MAP_EMACVLANTxConfigGet \ - ROM_EMACVLANTxConfigGet -#else -#define MAP_EMACVLANTxConfigGet \ - EMACVLANTxConfigGet -#endif -#ifdef ROM_EMACVLANTxConfigSet -#define MAP_EMACVLANTxConfigSet \ - ROM_EMACVLANTxConfigSet -#else -#define MAP_EMACVLANTxConfigSet \ - EMACVLANTxConfigSet -#endif - -//***************************************************************************** -// -// Macros for the Flash API. -// -//***************************************************************************** -#ifdef ROM_FlashProgram -#define MAP_FlashProgram \ - ROM_FlashProgram -#else -#define MAP_FlashProgram \ - FlashProgram -#endif -#ifdef ROM_FlashErase -#define MAP_FlashErase \ - ROM_FlashErase -#else -#define MAP_FlashErase \ - FlashErase -#endif -#ifdef ROM_FlashProtectGet -#define MAP_FlashProtectGet \ - ROM_FlashProtectGet -#else -#define MAP_FlashProtectGet \ - FlashProtectGet -#endif -#ifdef ROM_FlashProtectSet -#define MAP_FlashProtectSet \ - ROM_FlashProtectSet -#else -#define MAP_FlashProtectSet \ - FlashProtectSet -#endif -#ifdef ROM_FlashProtectSave -#define MAP_FlashProtectSave \ - ROM_FlashProtectSave -#else -#define MAP_FlashProtectSave \ - FlashProtectSave -#endif -#ifdef ROM_FlashUserGet -#define MAP_FlashUserGet \ - ROM_FlashUserGet -#else -#define MAP_FlashUserGet \ - FlashUserGet -#endif -#ifdef ROM_FlashUserSet -#define MAP_FlashUserSet \ - ROM_FlashUserSet -#else -#define MAP_FlashUserSet \ - FlashUserSet -#endif -#ifdef ROM_FlashUserSave -#define MAP_FlashUserSave \ - ROM_FlashUserSave -#else -#define MAP_FlashUserSave \ - FlashUserSave -#endif -#ifdef ROM_FlashIntEnable -#define MAP_FlashIntEnable \ - ROM_FlashIntEnable -#else -#define MAP_FlashIntEnable \ - FlashIntEnable -#endif -#ifdef ROM_FlashIntDisable -#define MAP_FlashIntDisable \ - ROM_FlashIntDisable -#else -#define MAP_FlashIntDisable \ - FlashIntDisable -#endif -#ifdef ROM_FlashIntStatus -#define MAP_FlashIntStatus \ - ROM_FlashIntStatus -#else -#define MAP_FlashIntStatus \ - FlashIntStatus -#endif -#ifdef ROM_FlashIntClear -#define MAP_FlashIntClear \ - ROM_FlashIntClear -#else -#define MAP_FlashIntClear \ - FlashIntClear -#endif - -//***************************************************************************** -// -// Macros for the FPU API. -// -//***************************************************************************** -#ifdef ROM_FPUEnable -#define MAP_FPUEnable \ - ROM_FPUEnable -#else -#define MAP_FPUEnable \ - FPUEnable -#endif -#ifdef ROM_FPUDisable -#define MAP_FPUDisable \ - ROM_FPUDisable -#else -#define MAP_FPUDisable \ - FPUDisable -#endif -#ifdef ROM_FPUFlushToZeroModeSet -#define MAP_FPUFlushToZeroModeSet \ - ROM_FPUFlushToZeroModeSet -#else -#define MAP_FPUFlushToZeroModeSet \ - FPUFlushToZeroModeSet -#endif -#ifdef ROM_FPUHalfPrecisionModeSet -#define MAP_FPUHalfPrecisionModeSet \ - ROM_FPUHalfPrecisionModeSet -#else -#define MAP_FPUHalfPrecisionModeSet \ - FPUHalfPrecisionModeSet -#endif -#ifdef ROM_FPULazyStackingEnable -#define MAP_FPULazyStackingEnable \ - ROM_FPULazyStackingEnable -#else -#define MAP_FPULazyStackingEnable \ - FPULazyStackingEnable -#endif -#ifdef ROM_FPUNaNModeSet -#define MAP_FPUNaNModeSet \ - ROM_FPUNaNModeSet -#else -#define MAP_FPUNaNModeSet \ - FPUNaNModeSet -#endif -#ifdef ROM_FPURoundingModeSet -#define MAP_FPURoundingModeSet \ - ROM_FPURoundingModeSet -#else -#define MAP_FPURoundingModeSet \ - FPURoundingModeSet -#endif -#ifdef ROM_FPUStackingDisable -#define MAP_FPUStackingDisable \ - ROM_FPUStackingDisable -#else -#define MAP_FPUStackingDisable \ - FPUStackingDisable -#endif -#ifdef ROM_FPUStackingEnable -#define MAP_FPUStackingEnable \ - ROM_FPUStackingEnable -#else -#define MAP_FPUStackingEnable \ - FPUStackingEnable -#endif - -//***************************************************************************** -// -// Macros for the GPIO API. -// -//***************************************************************************** -#ifdef ROM_GPIOPinWrite -#define MAP_GPIOPinWrite \ - ROM_GPIOPinWrite -#else -#define MAP_GPIOPinWrite \ - GPIOPinWrite -#endif -#ifdef ROM_GPIODirModeSet -#define MAP_GPIODirModeSet \ - ROM_GPIODirModeSet -#else -#define MAP_GPIODirModeSet \ - GPIODirModeSet -#endif -#ifdef ROM_GPIODirModeGet -#define MAP_GPIODirModeGet \ - ROM_GPIODirModeGet -#else -#define MAP_GPIODirModeGet \ - GPIODirModeGet -#endif -#ifdef ROM_GPIOIntTypeSet -#define MAP_GPIOIntTypeSet \ - ROM_GPIOIntTypeSet -#else -#define MAP_GPIOIntTypeSet \ - GPIOIntTypeSet -#endif -#ifdef ROM_GPIOIntTypeGet -#define MAP_GPIOIntTypeGet \ - ROM_GPIOIntTypeGet -#else -#define MAP_GPIOIntTypeGet \ - GPIOIntTypeGet -#endif -#ifdef ROM_GPIOPadConfigSet -#define MAP_GPIOPadConfigSet \ - ROM_GPIOPadConfigSet -#else -#define MAP_GPIOPadConfigSet \ - GPIOPadConfigSet -#endif -#ifdef ROM_GPIOPadConfigGet -#define MAP_GPIOPadConfigGet \ - ROM_GPIOPadConfigGet -#else -#define MAP_GPIOPadConfigGet \ - GPIOPadConfigGet -#endif -#ifdef ROM_GPIOPinRead -#define MAP_GPIOPinRead \ - ROM_GPIOPinRead -#else -#define MAP_GPIOPinRead \ - GPIOPinRead -#endif -#ifdef ROM_GPIOPinTypeCAN -#define MAP_GPIOPinTypeCAN \ - ROM_GPIOPinTypeCAN -#else -#define MAP_GPIOPinTypeCAN \ - GPIOPinTypeCAN -#endif -#ifdef ROM_GPIOPinTypeComparator -#define MAP_GPIOPinTypeComparator \ - ROM_GPIOPinTypeComparator -#else -#define MAP_GPIOPinTypeComparator \ - GPIOPinTypeComparator -#endif -#ifdef ROM_GPIOPinTypeGPIOInput -#define MAP_GPIOPinTypeGPIOInput \ - ROM_GPIOPinTypeGPIOInput -#else -#define MAP_GPIOPinTypeGPIOInput \ - GPIOPinTypeGPIOInput -#endif -#ifdef ROM_GPIOPinTypeGPIOOutput -#define MAP_GPIOPinTypeGPIOOutput \ - ROM_GPIOPinTypeGPIOOutput -#else -#define MAP_GPIOPinTypeGPIOOutput \ - GPIOPinTypeGPIOOutput -#endif -#ifdef ROM_GPIOPinTypeI2C -#define MAP_GPIOPinTypeI2C \ - ROM_GPIOPinTypeI2C -#else -#define MAP_GPIOPinTypeI2C \ - GPIOPinTypeI2C -#endif -#ifdef ROM_GPIOPinTypePWM -#define MAP_GPIOPinTypePWM \ - ROM_GPIOPinTypePWM -#else -#define MAP_GPIOPinTypePWM \ - GPIOPinTypePWM -#endif -#ifdef ROM_GPIOPinTypeQEI -#define MAP_GPIOPinTypeQEI \ - ROM_GPIOPinTypeQEI -#else -#define MAP_GPIOPinTypeQEI \ - GPIOPinTypeQEI -#endif -#ifdef ROM_GPIOPinTypeSSI -#define MAP_GPIOPinTypeSSI \ - ROM_GPIOPinTypeSSI -#else -#define MAP_GPIOPinTypeSSI \ - GPIOPinTypeSSI -#endif -#ifdef ROM_GPIOPinTypeTimer -#define MAP_GPIOPinTypeTimer \ - ROM_GPIOPinTypeTimer -#else -#define MAP_GPIOPinTypeTimer \ - GPIOPinTypeTimer -#endif -#ifdef ROM_GPIOPinTypeUART -#define MAP_GPIOPinTypeUART \ - ROM_GPIOPinTypeUART -#else -#define MAP_GPIOPinTypeUART \ - GPIOPinTypeUART -#endif -#ifdef ROM_GPIOPinTypeGPIOOutputOD -#define MAP_GPIOPinTypeGPIOOutputOD \ - ROM_GPIOPinTypeGPIOOutputOD -#else -#define MAP_GPIOPinTypeGPIOOutputOD \ - GPIOPinTypeGPIOOutputOD -#endif -#ifdef ROM_GPIOPinTypeADC -#define MAP_GPIOPinTypeADC \ - ROM_GPIOPinTypeADC -#else -#define MAP_GPIOPinTypeADC \ - GPIOPinTypeADC -#endif -#ifdef ROM_GPIOPinTypeUSBDigital -#define MAP_GPIOPinTypeUSBDigital \ - ROM_GPIOPinTypeUSBDigital -#else -#define MAP_GPIOPinTypeUSBDigital \ - GPIOPinTypeUSBDigital -#endif -#ifdef ROM_GPIOPinConfigure -#define MAP_GPIOPinConfigure \ - ROM_GPIOPinConfigure -#else -#define MAP_GPIOPinConfigure \ - GPIOPinConfigure -#endif -#ifdef ROM_GPIOPinTypeUSBAnalog -#define MAP_GPIOPinTypeUSBAnalog \ - ROM_GPIOPinTypeUSBAnalog -#else -#define MAP_GPIOPinTypeUSBAnalog \ - GPIOPinTypeUSBAnalog -#endif -#ifdef ROM_GPIODMATriggerEnable -#define MAP_GPIODMATriggerEnable \ - ROM_GPIODMATriggerEnable -#else -#define MAP_GPIODMATriggerEnable \ - GPIODMATriggerEnable -#endif -#ifdef ROM_GPIODMATriggerDisable -#define MAP_GPIODMATriggerDisable \ - ROM_GPIODMATriggerDisable -#else -#define MAP_GPIODMATriggerDisable \ - GPIODMATriggerDisable -#endif -#ifdef ROM_GPIOADCTriggerEnable -#define MAP_GPIOADCTriggerEnable \ - ROM_GPIOADCTriggerEnable -#else -#define MAP_GPIOADCTriggerEnable \ - GPIOADCTriggerEnable -#endif -#ifdef ROM_GPIOADCTriggerDisable -#define MAP_GPIOADCTriggerDisable \ - ROM_GPIOADCTriggerDisable -#else -#define MAP_GPIOADCTriggerDisable \ - GPIOADCTriggerDisable -#endif -#ifdef ROM_GPIOPinTypeI2CSCL -#define MAP_GPIOPinTypeI2CSCL \ - ROM_GPIOPinTypeI2CSCL -#else -#define MAP_GPIOPinTypeI2CSCL \ - GPIOPinTypeI2CSCL -#endif -#ifdef ROM_GPIOPinTypeOneWire -#define MAP_GPIOPinTypeOneWire \ - ROM_GPIOPinTypeOneWire -#else -#define MAP_GPIOPinTypeOneWire \ - GPIOPinTypeOneWire -#endif -#ifdef ROM_GPIOPinTypeWakeHigh -#define MAP_GPIOPinTypeWakeHigh \ - ROM_GPIOPinTypeWakeHigh -#else -#define MAP_GPIOPinTypeWakeHigh \ - GPIOPinTypeWakeHigh -#endif -#ifdef ROM_GPIOPinTypeWakeLow -#define MAP_GPIOPinTypeWakeLow \ - ROM_GPIOPinTypeWakeLow -#else -#define MAP_GPIOPinTypeWakeLow \ - GPIOPinTypeWakeLow -#endif -#ifdef ROM_GPIOIntClear -#define MAP_GPIOIntClear \ - ROM_GPIOIntClear -#else -#define MAP_GPIOIntClear \ - GPIOIntClear -#endif -#ifdef ROM_GPIOIntDisable -#define MAP_GPIOIntDisable \ - ROM_GPIOIntDisable -#else -#define MAP_GPIOIntDisable \ - GPIOIntDisable -#endif -#ifdef ROM_GPIOIntEnable -#define MAP_GPIOIntEnable \ - ROM_GPIOIntEnable -#else -#define MAP_GPIOIntEnable \ - GPIOIntEnable -#endif -#ifdef ROM_GPIOIntStatus -#define MAP_GPIOIntStatus \ - ROM_GPIOIntStatus -#else -#define MAP_GPIOIntStatus \ - GPIOIntStatus -#endif -#ifdef ROM_GPIOPinWakeStatus -#define MAP_GPIOPinWakeStatus \ - ROM_GPIOPinWakeStatus -#else -#define MAP_GPIOPinWakeStatus \ - GPIOPinWakeStatus -#endif - -//***************************************************************************** -// -// Macros for the Hibernate API. -// -//***************************************************************************** -#ifdef ROM_HibernateIntClear -#define MAP_HibernateIntClear \ - ROM_HibernateIntClear -#else -#define MAP_HibernateIntClear \ - HibernateIntClear -#endif -#ifdef ROM_HibernateEnableExpClk -#define MAP_HibernateEnableExpClk \ - ROM_HibernateEnableExpClk -#else -#define MAP_HibernateEnableExpClk \ - HibernateEnableExpClk -#endif -#ifdef ROM_HibernateDisable -#define MAP_HibernateDisable \ - ROM_HibernateDisable -#else -#define MAP_HibernateDisable \ - HibernateDisable -#endif -#ifdef ROM_HibernateRTCEnable -#define MAP_HibernateRTCEnable \ - ROM_HibernateRTCEnable -#else -#define MAP_HibernateRTCEnable \ - HibernateRTCEnable -#endif -#ifdef ROM_HibernateRTCDisable -#define MAP_HibernateRTCDisable \ - ROM_HibernateRTCDisable -#else -#define MAP_HibernateRTCDisable \ - HibernateRTCDisable -#endif -#ifdef ROM_HibernateWakeSet -#define MAP_HibernateWakeSet \ - ROM_HibernateWakeSet -#else -#define MAP_HibernateWakeSet \ - HibernateWakeSet -#endif -#ifdef ROM_HibernateWakeGet -#define MAP_HibernateWakeGet \ - ROM_HibernateWakeGet -#else -#define MAP_HibernateWakeGet \ - HibernateWakeGet -#endif -#ifdef ROM_HibernateLowBatSet -#define MAP_HibernateLowBatSet \ - ROM_HibernateLowBatSet -#else -#define MAP_HibernateLowBatSet \ - HibernateLowBatSet -#endif -#ifdef ROM_HibernateLowBatGet -#define MAP_HibernateLowBatGet \ - ROM_HibernateLowBatGet -#else -#define MAP_HibernateLowBatGet \ - HibernateLowBatGet -#endif -#ifdef ROM_HibernateRTCSet -#define MAP_HibernateRTCSet \ - ROM_HibernateRTCSet -#else -#define MAP_HibernateRTCSet \ - HibernateRTCSet -#endif -#ifdef ROM_HibernateRTCGet -#define MAP_HibernateRTCGet \ - ROM_HibernateRTCGet -#else -#define MAP_HibernateRTCGet \ - HibernateRTCGet -#endif -#ifdef ROM_HibernateRTCTrimSet -#define MAP_HibernateRTCTrimSet \ - ROM_HibernateRTCTrimSet -#else -#define MAP_HibernateRTCTrimSet \ - HibernateRTCTrimSet -#endif -#ifdef ROM_HibernateRTCTrimGet -#define MAP_HibernateRTCTrimGet \ - ROM_HibernateRTCTrimGet -#else -#define MAP_HibernateRTCTrimGet \ - HibernateRTCTrimGet -#endif -#ifdef ROM_HibernateDataSet -#define MAP_HibernateDataSet \ - ROM_HibernateDataSet -#else -#define MAP_HibernateDataSet \ - HibernateDataSet -#endif -#ifdef ROM_HibernateDataGet -#define MAP_HibernateDataGet \ - ROM_HibernateDataGet -#else -#define MAP_HibernateDataGet \ - HibernateDataGet -#endif -#ifdef ROM_HibernateRequest -#define MAP_HibernateRequest \ - ROM_HibernateRequest -#else -#define MAP_HibernateRequest \ - HibernateRequest -#endif -#ifdef ROM_HibernateIntEnable -#define MAP_HibernateIntEnable \ - ROM_HibernateIntEnable -#else -#define MAP_HibernateIntEnable \ - HibernateIntEnable -#endif -#ifdef ROM_HibernateIntDisable -#define MAP_HibernateIntDisable \ - ROM_HibernateIntDisable -#else -#define MAP_HibernateIntDisable \ - HibernateIntDisable -#endif -#ifdef ROM_HibernateIntStatus -#define MAP_HibernateIntStatus \ - ROM_HibernateIntStatus -#else -#define MAP_HibernateIntStatus \ - HibernateIntStatus -#endif -#ifdef ROM_HibernateIsActive -#define MAP_HibernateIsActive \ - ROM_HibernateIsActive -#else -#define MAP_HibernateIsActive \ - HibernateIsActive -#endif -#ifdef ROM_HibernateRTCSSGet -#define MAP_HibernateRTCSSGet \ - ROM_HibernateRTCSSGet -#else -#define MAP_HibernateRTCSSGet \ - HibernateRTCSSGet -#endif -#ifdef ROM_HibernateClockConfig -#define MAP_HibernateClockConfig \ - ROM_HibernateClockConfig -#else -#define MAP_HibernateClockConfig \ - HibernateClockConfig -#endif -#ifdef ROM_HibernateBatCheckStart -#define MAP_HibernateBatCheckStart \ - ROM_HibernateBatCheckStart -#else -#define MAP_HibernateBatCheckStart \ - HibernateBatCheckStart -#endif -#ifdef ROM_HibernateBatCheckDone -#define MAP_HibernateBatCheckDone \ - ROM_HibernateBatCheckDone -#else -#define MAP_HibernateBatCheckDone \ - HibernateBatCheckDone -#endif -#ifdef ROM_HibernateGPIORetentionEnable -#define MAP_HibernateGPIORetentionEnable \ - ROM_HibernateGPIORetentionEnable -#else -#define MAP_HibernateGPIORetentionEnable \ - HibernateGPIORetentionEnable -#endif -#ifdef ROM_HibernateGPIORetentionDisable -#define MAP_HibernateGPIORetentionDisable \ - ROM_HibernateGPIORetentionDisable -#else -#define MAP_HibernateGPIORetentionDisable \ - HibernateGPIORetentionDisable -#endif -#ifdef ROM_HibernateGPIORetentionGet -#define MAP_HibernateGPIORetentionGet \ - ROM_HibernateGPIORetentionGet -#else -#define MAP_HibernateGPIORetentionGet \ - HibernateGPIORetentionGet -#endif -#ifdef ROM_HibernateCounterMode -#define MAP_HibernateCounterMode \ - ROM_HibernateCounterMode -#else -#define MAP_HibernateCounterMode \ - HibernateCounterMode -#endif -#ifdef ROM_HibernateCalendarSet -#define MAP_HibernateCalendarSet \ - ROM_HibernateCalendarSet -#else -#define MAP_HibernateCalendarSet \ - HibernateCalendarSet -#endif -#ifdef ROM_HibernateCalendarGet -#define MAP_HibernateCalendarGet \ - ROM_HibernateCalendarGet -#else -#define MAP_HibernateCalendarGet \ - HibernateCalendarGet -#endif -#ifdef ROM_HibernateCalendarMatchSet -#define MAP_HibernateCalendarMatchSet \ - ROM_HibernateCalendarMatchSet -#else -#define MAP_HibernateCalendarMatchSet \ - HibernateCalendarMatchSet -#endif -#ifdef ROM_HibernateCalendarMatchGet -#define MAP_HibernateCalendarMatchGet \ - ROM_HibernateCalendarMatchGet -#else -#define MAP_HibernateCalendarMatchGet \ - HibernateCalendarMatchGet -#endif -#ifdef ROM_HibernateTamperDisable -#define MAP_HibernateTamperDisable \ - ROM_HibernateTamperDisable -#else -#define MAP_HibernateTamperDisable \ - HibernateTamperDisable -#endif -#ifdef ROM_HibernateTamperEnable -#define MAP_HibernateTamperEnable \ - ROM_HibernateTamperEnable -#else -#define MAP_HibernateTamperEnable \ - HibernateTamperEnable -#endif -#ifdef ROM_HibernateTamperEventsClear -#define MAP_HibernateTamperEventsClear \ - ROM_HibernateTamperEventsClear -#else -#define MAP_HibernateTamperEventsClear \ - HibernateTamperEventsClear -#endif -#ifdef ROM_HibernateTamperEventsConfig -#define MAP_HibernateTamperEventsConfig \ - ROM_HibernateTamperEventsConfig -#else -#define MAP_HibernateTamperEventsConfig \ - HibernateTamperEventsConfig -#endif -#ifdef ROM_HibernateTamperEventsGet -#define MAP_HibernateTamperEventsGet \ - ROM_HibernateTamperEventsGet -#else -#define MAP_HibernateTamperEventsGet \ - HibernateTamperEventsGet -#endif -#ifdef ROM_HibernateTamperExtOscValid -#define MAP_HibernateTamperExtOscValid \ - ROM_HibernateTamperExtOscValid -#else -#define MAP_HibernateTamperExtOscValid \ - HibernateTamperExtOscValid -#endif -#ifdef ROM_HibernateTamperExtOscRecover -#define MAP_HibernateTamperExtOscRecover \ - ROM_HibernateTamperExtOscRecover -#else -#define MAP_HibernateTamperExtOscRecover \ - HibernateTamperExtOscRecover -#endif -#ifdef ROM_HibernateTamperIODisable -#define MAP_HibernateTamperIODisable \ - ROM_HibernateTamperIODisable -#else -#define MAP_HibernateTamperIODisable \ - HibernateTamperIODisable -#endif -#ifdef ROM_HibernateTamperIOEnable -#define MAP_HibernateTamperIOEnable \ - ROM_HibernateTamperIOEnable -#else -#define MAP_HibernateTamperIOEnable \ - HibernateTamperIOEnable -#endif -#ifdef ROM_HibernateTamperStatusGet -#define MAP_HibernateTamperStatusGet \ - ROM_HibernateTamperStatusGet -#else -#define MAP_HibernateTamperStatusGet \ - HibernateTamperStatusGet -#endif -#ifdef ROM_HibernateRTCMatchGet -#define MAP_HibernateRTCMatchGet \ - ROM_HibernateRTCMatchGet -#else -#define MAP_HibernateRTCMatchGet \ - HibernateRTCMatchGet -#endif -#ifdef ROM_HibernateRTCMatchSet -#define MAP_HibernateRTCMatchSet \ - ROM_HibernateRTCMatchSet -#else -#define MAP_HibernateRTCMatchSet \ - HibernateRTCMatchSet -#endif -#ifdef ROM_HibernateRTCSSMatchGet -#define MAP_HibernateRTCSSMatchGet \ - ROM_HibernateRTCSSMatchGet -#else -#define MAP_HibernateRTCSSMatchGet \ - HibernateRTCSSMatchGet -#endif -#ifdef ROM_HibernateRTCSSMatchSet -#define MAP_HibernateRTCSSMatchSet \ - ROM_HibernateRTCSSMatchSet -#else -#define MAP_HibernateRTCSSMatchSet \ - HibernateRTCSSMatchSet -#endif - -//***************************************************************************** -// -// Macros for the I2C API. -// -//***************************************************************************** -#ifdef ROM_I2CMasterDataPut -#define MAP_I2CMasterDataPut \ - ROM_I2CMasterDataPut -#else -#define MAP_I2CMasterDataPut \ - I2CMasterDataPut -#endif -#ifdef ROM_I2CMasterInitExpClk -#define MAP_I2CMasterInitExpClk \ - ROM_I2CMasterInitExpClk -#else -#define MAP_I2CMasterInitExpClk \ - I2CMasterInitExpClk -#endif -#ifdef ROM_I2CSlaveInit -#define MAP_I2CSlaveInit \ - ROM_I2CSlaveInit -#else -#define MAP_I2CSlaveInit \ - I2CSlaveInit -#endif -#ifdef ROM_I2CMasterEnable -#define MAP_I2CMasterEnable \ - ROM_I2CMasterEnable -#else -#define MAP_I2CMasterEnable \ - I2CMasterEnable -#endif -#ifdef ROM_I2CSlaveEnable -#define MAP_I2CSlaveEnable \ - ROM_I2CSlaveEnable -#else -#define MAP_I2CSlaveEnable \ - I2CSlaveEnable -#endif -#ifdef ROM_I2CMasterDisable -#define MAP_I2CMasterDisable \ - ROM_I2CMasterDisable -#else -#define MAP_I2CMasterDisable \ - I2CMasterDisable -#endif -#ifdef ROM_I2CSlaveDisable -#define MAP_I2CSlaveDisable \ - ROM_I2CSlaveDisable -#else -#define MAP_I2CSlaveDisable \ - I2CSlaveDisable -#endif -#ifdef ROM_I2CMasterIntEnable -#define MAP_I2CMasterIntEnable \ - ROM_I2CMasterIntEnable -#else -#define MAP_I2CMasterIntEnable \ - I2CMasterIntEnable -#endif -#ifdef ROM_I2CSlaveIntEnable -#define MAP_I2CSlaveIntEnable \ - ROM_I2CSlaveIntEnable -#else -#define MAP_I2CSlaveIntEnable \ - I2CSlaveIntEnable -#endif -#ifdef ROM_I2CMasterIntDisable -#define MAP_I2CMasterIntDisable \ - ROM_I2CMasterIntDisable -#else -#define MAP_I2CMasterIntDisable \ - I2CMasterIntDisable -#endif -#ifdef ROM_I2CSlaveIntDisable -#define MAP_I2CSlaveIntDisable \ - ROM_I2CSlaveIntDisable -#else -#define MAP_I2CSlaveIntDisable \ - I2CSlaveIntDisable -#endif -#ifdef ROM_I2CMasterIntStatus -#define MAP_I2CMasterIntStatus \ - ROM_I2CMasterIntStatus -#else -#define MAP_I2CMasterIntStatus \ - I2CMasterIntStatus -#endif -#ifdef ROM_I2CSlaveIntStatus -#define MAP_I2CSlaveIntStatus \ - ROM_I2CSlaveIntStatus -#else -#define MAP_I2CSlaveIntStatus \ - I2CSlaveIntStatus -#endif -#ifdef ROM_I2CMasterIntClear -#define MAP_I2CMasterIntClear \ - ROM_I2CMasterIntClear -#else -#define MAP_I2CMasterIntClear \ - I2CMasterIntClear -#endif -#ifdef ROM_I2CSlaveIntClear -#define MAP_I2CSlaveIntClear \ - ROM_I2CSlaveIntClear -#else -#define MAP_I2CSlaveIntClear \ - I2CSlaveIntClear -#endif -#ifdef ROM_I2CMasterSlaveAddrSet -#define MAP_I2CMasterSlaveAddrSet \ - ROM_I2CMasterSlaveAddrSet -#else -#define MAP_I2CMasterSlaveAddrSet \ - I2CMasterSlaveAddrSet -#endif -#ifdef ROM_I2CMasterBusy -#define MAP_I2CMasterBusy \ - ROM_I2CMasterBusy -#else -#define MAP_I2CMasterBusy \ - I2CMasterBusy -#endif -#ifdef ROM_I2CMasterBusBusy -#define MAP_I2CMasterBusBusy \ - ROM_I2CMasterBusBusy -#else -#define MAP_I2CMasterBusBusy \ - I2CMasterBusBusy -#endif -#ifdef ROM_I2CMasterControl -#define MAP_I2CMasterControl \ - ROM_I2CMasterControl -#else -#define MAP_I2CMasterControl \ - I2CMasterControl -#endif -#ifdef ROM_I2CMasterErr -#define MAP_I2CMasterErr \ - ROM_I2CMasterErr -#else -#define MAP_I2CMasterErr \ - I2CMasterErr -#endif -#ifdef ROM_I2CMasterDataGet -#define MAP_I2CMasterDataGet \ - ROM_I2CMasterDataGet -#else -#define MAP_I2CMasterDataGet \ - I2CMasterDataGet -#endif -#ifdef ROM_I2CSlaveStatus -#define MAP_I2CSlaveStatus \ - ROM_I2CSlaveStatus -#else -#define MAP_I2CSlaveStatus \ - I2CSlaveStatus -#endif -#ifdef ROM_I2CSlaveDataPut -#define MAP_I2CSlaveDataPut \ - ROM_I2CSlaveDataPut -#else -#define MAP_I2CSlaveDataPut \ - I2CSlaveDataPut -#endif -#ifdef ROM_I2CSlaveDataGet -#define MAP_I2CSlaveDataGet \ - ROM_I2CSlaveDataGet -#else -#define MAP_I2CSlaveDataGet \ - I2CSlaveDataGet -#endif -#ifdef ROM_I2CSlaveIntEnableEx -#define MAP_I2CSlaveIntEnableEx \ - ROM_I2CSlaveIntEnableEx -#else -#define MAP_I2CSlaveIntEnableEx \ - I2CSlaveIntEnableEx -#endif -#ifdef ROM_I2CSlaveIntDisableEx -#define MAP_I2CSlaveIntDisableEx \ - ROM_I2CSlaveIntDisableEx -#else -#define MAP_I2CSlaveIntDisableEx \ - I2CSlaveIntDisableEx -#endif -#ifdef ROM_I2CSlaveIntStatusEx -#define MAP_I2CSlaveIntStatusEx \ - ROM_I2CSlaveIntStatusEx -#else -#define MAP_I2CSlaveIntStatusEx \ - I2CSlaveIntStatusEx -#endif -#ifdef ROM_I2CSlaveIntClearEx -#define MAP_I2CSlaveIntClearEx \ - ROM_I2CSlaveIntClearEx -#else -#define MAP_I2CSlaveIntClearEx \ - I2CSlaveIntClearEx -#endif -#ifdef ROM_I2CMasterIntEnableEx -#define MAP_I2CMasterIntEnableEx \ - ROM_I2CMasterIntEnableEx -#else -#define MAP_I2CMasterIntEnableEx \ - I2CMasterIntEnableEx -#endif -#ifdef ROM_I2CMasterIntDisableEx -#define MAP_I2CMasterIntDisableEx \ - ROM_I2CMasterIntDisableEx -#else -#define MAP_I2CMasterIntDisableEx \ - I2CMasterIntDisableEx -#endif -#ifdef ROM_I2CMasterIntStatusEx -#define MAP_I2CMasterIntStatusEx \ - ROM_I2CMasterIntStatusEx -#else -#define MAP_I2CMasterIntStatusEx \ - I2CMasterIntStatusEx -#endif -#ifdef ROM_I2CMasterIntClearEx -#define MAP_I2CMasterIntClearEx \ - ROM_I2CMasterIntClearEx -#else -#define MAP_I2CMasterIntClearEx \ - I2CMasterIntClearEx -#endif -#ifdef ROM_I2CMasterTimeoutSet -#define MAP_I2CMasterTimeoutSet \ - ROM_I2CMasterTimeoutSet -#else -#define MAP_I2CMasterTimeoutSet \ - I2CMasterTimeoutSet -#endif -#ifdef ROM_I2CSlaveACKOverride -#define MAP_I2CSlaveACKOverride \ - ROM_I2CSlaveACKOverride -#else -#define MAP_I2CSlaveACKOverride \ - I2CSlaveACKOverride -#endif -#ifdef ROM_I2CSlaveACKValueSet -#define MAP_I2CSlaveACKValueSet \ - ROM_I2CSlaveACKValueSet -#else -#define MAP_I2CSlaveACKValueSet \ - I2CSlaveACKValueSet -#endif -#ifdef ROM_I2CSlaveAddressSet -#define MAP_I2CSlaveAddressSet \ - ROM_I2CSlaveAddressSet -#else -#define MAP_I2CSlaveAddressSet \ - I2CSlaveAddressSet -#endif -#ifdef ROM_I2CMasterLineStateGet -#define MAP_I2CMasterLineStateGet \ - ROM_I2CMasterLineStateGet -#else -#define MAP_I2CMasterLineStateGet \ - I2CMasterLineStateGet -#endif -#ifdef ROM_I2CTxFIFOConfigSet -#define MAP_I2CTxFIFOConfigSet \ - ROM_I2CTxFIFOConfigSet -#else -#define MAP_I2CTxFIFOConfigSet \ - I2CTxFIFOConfigSet -#endif -#ifdef ROM_I2CTxFIFOFlush -#define MAP_I2CTxFIFOFlush \ - ROM_I2CTxFIFOFlush -#else -#define MAP_I2CTxFIFOFlush \ - I2CTxFIFOFlush -#endif -#ifdef ROM_I2CRxFIFOConfigSet -#define MAP_I2CRxFIFOConfigSet \ - ROM_I2CRxFIFOConfigSet -#else -#define MAP_I2CRxFIFOConfigSet \ - I2CRxFIFOConfigSet -#endif -#ifdef ROM_I2CRxFIFOFlush -#define MAP_I2CRxFIFOFlush \ - ROM_I2CRxFIFOFlush -#else -#define MAP_I2CRxFIFOFlush \ - I2CRxFIFOFlush -#endif -#ifdef ROM_I2CFIFOStatus -#define MAP_I2CFIFOStatus \ - ROM_I2CFIFOStatus -#else -#define MAP_I2CFIFOStatus \ - I2CFIFOStatus -#endif -#ifdef ROM_I2CFIFODataPut -#define MAP_I2CFIFODataPut \ - ROM_I2CFIFODataPut -#else -#define MAP_I2CFIFODataPut \ - I2CFIFODataPut -#endif -#ifdef ROM_I2CFIFODataPutNonBlocking -#define MAP_I2CFIFODataPutNonBlocking \ - ROM_I2CFIFODataPutNonBlocking -#else -#define MAP_I2CFIFODataPutNonBlocking \ - I2CFIFODataPutNonBlocking -#endif -#ifdef ROM_I2CFIFODataGet -#define MAP_I2CFIFODataGet \ - ROM_I2CFIFODataGet -#else -#define MAP_I2CFIFODataGet \ - I2CFIFODataGet -#endif -#ifdef ROM_I2CFIFODataGetNonBlocking -#define MAP_I2CFIFODataGetNonBlocking \ - ROM_I2CFIFODataGetNonBlocking -#else -#define MAP_I2CFIFODataGetNonBlocking \ - I2CFIFODataGetNonBlocking -#endif -#ifdef ROM_I2CMasterBurstLengthSet -#define MAP_I2CMasterBurstLengthSet \ - ROM_I2CMasterBurstLengthSet -#else -#define MAP_I2CMasterBurstLengthSet \ - I2CMasterBurstLengthSet -#endif -#ifdef ROM_I2CMasterBurstCountGet -#define MAP_I2CMasterBurstCountGet \ - ROM_I2CMasterBurstCountGet -#else -#define MAP_I2CMasterBurstCountGet \ - I2CMasterBurstCountGet -#endif -#ifdef ROM_I2CSlaveFIFODisable -#define MAP_I2CSlaveFIFODisable \ - ROM_I2CSlaveFIFODisable -#else -#define MAP_I2CSlaveFIFODisable \ - I2CSlaveFIFODisable -#endif -#ifdef ROM_I2CSlaveFIFOEnable -#define MAP_I2CSlaveFIFOEnable \ - ROM_I2CSlaveFIFOEnable -#else -#define MAP_I2CSlaveFIFOEnable \ - I2CSlaveFIFOEnable -#endif -#ifdef ROM_I2CMasterGlitchFilterConfigSet -#define MAP_I2CMasterGlitchFilterConfigSet \ - ROM_I2CMasterGlitchFilterConfigSet -#else -#define MAP_I2CMasterGlitchFilterConfigSet \ - I2CMasterGlitchFilterConfigSet -#endif - -//***************************************************************************** -// -// Macros for the Interrupt API. -// -//***************************************************************************** -#ifdef ROM_IntEnable -#define MAP_IntEnable \ - ROM_IntEnable -#else -#define MAP_IntEnable \ - IntEnable -#endif -#ifdef ROM_IntMasterEnable -#define MAP_IntMasterEnable \ - ROM_IntMasterEnable -#else -#define MAP_IntMasterEnable \ - IntMasterEnable -#endif -#ifdef ROM_IntMasterDisable -#define MAP_IntMasterDisable \ - ROM_IntMasterDisable -#else -#define MAP_IntMasterDisable \ - IntMasterDisable -#endif -#ifdef ROM_IntDisable -#define MAP_IntDisable \ - ROM_IntDisable -#else -#define MAP_IntDisable \ - IntDisable -#endif -#ifdef ROM_IntPriorityGroupingSet -#define MAP_IntPriorityGroupingSet \ - ROM_IntPriorityGroupingSet -#else -#define MAP_IntPriorityGroupingSet \ - IntPriorityGroupingSet -#endif -#ifdef ROM_IntPriorityGroupingGet -#define MAP_IntPriorityGroupingGet \ - ROM_IntPriorityGroupingGet -#else -#define MAP_IntPriorityGroupingGet \ - IntPriorityGroupingGet -#endif -#ifdef ROM_IntPrioritySet -#define MAP_IntPrioritySet \ - ROM_IntPrioritySet -#else -#define MAP_IntPrioritySet \ - IntPrioritySet -#endif -#ifdef ROM_IntPriorityGet -#define MAP_IntPriorityGet \ - ROM_IntPriorityGet -#else -#define MAP_IntPriorityGet \ - IntPriorityGet -#endif -#ifdef ROM_IntPendSet -#define MAP_IntPendSet \ - ROM_IntPendSet -#else -#define MAP_IntPendSet \ - IntPendSet -#endif -#ifdef ROM_IntPendClear -#define MAP_IntPendClear \ - ROM_IntPendClear -#else -#define MAP_IntPendClear \ - IntPendClear -#endif -#ifdef ROM_IntPriorityMaskSet -#define MAP_IntPriorityMaskSet \ - ROM_IntPriorityMaskSet -#else -#define MAP_IntPriorityMaskSet \ - IntPriorityMaskSet -#endif -#ifdef ROM_IntPriorityMaskGet -#define MAP_IntPriorityMaskGet \ - ROM_IntPriorityMaskGet -#else -#define MAP_IntPriorityMaskGet \ - IntPriorityMaskGet -#endif -#ifdef ROM_IntIsEnabled -#define MAP_IntIsEnabled \ - ROM_IntIsEnabled -#else -#define MAP_IntIsEnabled \ - IntIsEnabled -#endif -#ifdef ROM_IntTrigger -#define MAP_IntTrigger \ - ROM_IntTrigger -#else -#define MAP_IntTrigger \ - IntTrigger -#endif - -//***************************************************************************** -// -// Macros for the LCD API. -// -//***************************************************************************** -#ifdef ROM_LCDIntStatus -#define MAP_LCDIntStatus \ - ROM_LCDIntStatus -#else -#define MAP_LCDIntStatus \ - LCDIntStatus -#endif -#ifdef ROM_LCDClockReset -#define MAP_LCDClockReset \ - ROM_LCDClockReset -#else -#define MAP_LCDClockReset \ - LCDClockReset -#endif -#ifdef ROM_LCDDMAConfigSet -#define MAP_LCDDMAConfigSet \ - ROM_LCDDMAConfigSet -#else -#define MAP_LCDDMAConfigSet \ - LCDDMAConfigSet -#endif -#ifdef ROM_LCDIDDCommandWrite -#define MAP_LCDIDDCommandWrite \ - ROM_LCDIDDCommandWrite -#else -#define MAP_LCDIDDCommandWrite \ - LCDIDDCommandWrite -#endif -#ifdef ROM_LCDIDDConfigSet -#define MAP_LCDIDDConfigSet \ - ROM_LCDIDDConfigSet -#else -#define MAP_LCDIDDConfigSet \ - LCDIDDConfigSet -#endif -#ifdef ROM_LCDIDDDataRead -#define MAP_LCDIDDDataRead \ - ROM_LCDIDDDataRead -#else -#define MAP_LCDIDDDataRead \ - LCDIDDDataRead -#endif -#ifdef ROM_LCDIDDDataWrite -#define MAP_LCDIDDDataWrite \ - ROM_LCDIDDDataWrite -#else -#define MAP_LCDIDDDataWrite \ - LCDIDDDataWrite -#endif -#ifdef ROM_LCDIDDDMADisable -#define MAP_LCDIDDDMADisable \ - ROM_LCDIDDDMADisable -#else -#define MAP_LCDIDDDMADisable \ - LCDIDDDMADisable -#endif -#ifdef ROM_LCDIDDDMAWrite -#define MAP_LCDIDDDMAWrite \ - ROM_LCDIDDDMAWrite -#else -#define MAP_LCDIDDDMAWrite \ - LCDIDDDMAWrite -#endif -#ifdef ROM_LCDIDDIndexedRead -#define MAP_LCDIDDIndexedRead \ - ROM_LCDIDDIndexedRead -#else -#define MAP_LCDIDDIndexedRead \ - LCDIDDIndexedRead -#endif -#ifdef ROM_LCDIDDIndexedWrite -#define MAP_LCDIDDIndexedWrite \ - ROM_LCDIDDIndexedWrite -#else -#define MAP_LCDIDDIndexedWrite \ - LCDIDDIndexedWrite -#endif -#ifdef ROM_LCDIDDStatusRead -#define MAP_LCDIDDStatusRead \ - ROM_LCDIDDStatusRead -#else -#define MAP_LCDIDDStatusRead \ - LCDIDDStatusRead -#endif -#ifdef ROM_LCDIDDTimingSet -#define MAP_LCDIDDTimingSet \ - ROM_LCDIDDTimingSet -#else -#define MAP_LCDIDDTimingSet \ - LCDIDDTimingSet -#endif -#ifdef ROM_LCDIntClear -#define MAP_LCDIntClear \ - ROM_LCDIntClear -#else -#define MAP_LCDIntClear \ - LCDIntClear -#endif -#ifdef ROM_LCDIntDisable -#define MAP_LCDIntDisable \ - ROM_LCDIntDisable -#else -#define MAP_LCDIntDisable \ - LCDIntDisable -#endif -#ifdef ROM_LCDIntEnable -#define MAP_LCDIntEnable \ - ROM_LCDIntEnable -#else -#define MAP_LCDIntEnable \ - LCDIntEnable -#endif -#ifdef ROM_LCDModeSet -#define MAP_LCDModeSet \ - ROM_LCDModeSet -#else -#define MAP_LCDModeSet \ - LCDModeSet -#endif -#ifdef ROM_LCDRasterACBiasIntCountSet -#define MAP_LCDRasterACBiasIntCountSet \ - ROM_LCDRasterACBiasIntCountSet -#else -#define MAP_LCDRasterACBiasIntCountSet \ - LCDRasterACBiasIntCountSet -#endif -#ifdef ROM_LCDRasterConfigSet -#define MAP_LCDRasterConfigSet \ - ROM_LCDRasterConfigSet -#else -#define MAP_LCDRasterConfigSet \ - LCDRasterConfigSet -#endif -#ifdef ROM_LCDRasterDisable -#define MAP_LCDRasterDisable \ - ROM_LCDRasterDisable -#else -#define MAP_LCDRasterDisable \ - LCDRasterDisable -#endif -#ifdef ROM_LCDRasterEnable -#define MAP_LCDRasterEnable \ - ROM_LCDRasterEnable -#else -#define MAP_LCDRasterEnable \ - LCDRasterEnable -#endif -#ifdef ROM_LCDRasterFrameBufferSet -#define MAP_LCDRasterFrameBufferSet \ - ROM_LCDRasterFrameBufferSet -#else -#define MAP_LCDRasterFrameBufferSet \ - LCDRasterFrameBufferSet -#endif -#ifdef ROM_LCDRasterPaletteSet -#define MAP_LCDRasterPaletteSet \ - ROM_LCDRasterPaletteSet -#else -#define MAP_LCDRasterPaletteSet \ - LCDRasterPaletteSet -#endif -#ifdef ROM_LCDRasterSubPanelConfigSet -#define MAP_LCDRasterSubPanelConfigSet \ - ROM_LCDRasterSubPanelConfigSet -#else -#define MAP_LCDRasterSubPanelConfigSet \ - LCDRasterSubPanelConfigSet -#endif -#ifdef ROM_LCDRasterSubPanelDisable -#define MAP_LCDRasterSubPanelDisable \ - ROM_LCDRasterSubPanelDisable -#else -#define MAP_LCDRasterSubPanelDisable \ - LCDRasterSubPanelDisable -#endif -#ifdef ROM_LCDRasterSubPanelEnable -#define MAP_LCDRasterSubPanelEnable \ - ROM_LCDRasterSubPanelEnable -#else -#define MAP_LCDRasterSubPanelEnable \ - LCDRasterSubPanelEnable -#endif -#ifdef ROM_LCDRasterTimingSet -#define MAP_LCDRasterTimingSet \ - ROM_LCDRasterTimingSet -#else -#define MAP_LCDRasterTimingSet \ - LCDRasterTimingSet -#endif -#ifdef ROM_LCDRasterEnabled -#define MAP_LCDRasterEnabled \ - ROM_LCDRasterEnabled -#else -#define MAP_LCDRasterEnabled \ - LCDRasterEnabled -#endif - -//***************************************************************************** -// -// Macros for the MPU API. -// -//***************************************************************************** -#ifdef ROM_MPUEnable -#define MAP_MPUEnable \ - ROM_MPUEnable -#else -#define MAP_MPUEnable \ - MPUEnable -#endif -#ifdef ROM_MPUDisable -#define MAP_MPUDisable \ - ROM_MPUDisable -#else -#define MAP_MPUDisable \ - MPUDisable -#endif -#ifdef ROM_MPURegionCountGet -#define MAP_MPURegionCountGet \ - ROM_MPURegionCountGet -#else -#define MAP_MPURegionCountGet \ - MPURegionCountGet -#endif -#ifdef ROM_MPURegionEnable -#define MAP_MPURegionEnable \ - ROM_MPURegionEnable -#else -#define MAP_MPURegionEnable \ - MPURegionEnable -#endif -#ifdef ROM_MPURegionDisable -#define MAP_MPURegionDisable \ - ROM_MPURegionDisable -#else -#define MAP_MPURegionDisable \ - MPURegionDisable -#endif -#ifdef ROM_MPURegionSet -#define MAP_MPURegionSet \ - ROM_MPURegionSet -#else -#define MAP_MPURegionSet \ - MPURegionSet -#endif -#ifdef ROM_MPURegionGet -#define MAP_MPURegionGet \ - ROM_MPURegionGet -#else -#define MAP_MPURegionGet \ - MPURegionGet -#endif - -//***************************************************************************** -// -// Macros for the OneWire API. -// -//***************************************************************************** -#ifdef ROM_OneWireIntStatus -#define MAP_OneWireIntStatus \ - ROM_OneWireIntStatus -#else -#define MAP_OneWireIntStatus \ - OneWireIntStatus -#endif -#ifdef ROM_OneWireBusReset -#define MAP_OneWireBusReset \ - ROM_OneWireBusReset -#else -#define MAP_OneWireBusReset \ - OneWireBusReset -#endif -#ifdef ROM_OneWireBusStatus -#define MAP_OneWireBusStatus \ - ROM_OneWireBusStatus -#else -#define MAP_OneWireBusStatus \ - OneWireBusStatus -#endif -#ifdef ROM_OneWireDataGet -#define MAP_OneWireDataGet \ - ROM_OneWireDataGet -#else -#define MAP_OneWireDataGet \ - OneWireDataGet -#endif -#ifdef ROM_OneWireDataGetNonBlocking -#define MAP_OneWireDataGetNonBlocking \ - ROM_OneWireDataGetNonBlocking -#else -#define MAP_OneWireDataGetNonBlocking \ - OneWireDataGetNonBlocking -#endif -#ifdef ROM_OneWireInit -#define MAP_OneWireInit \ - ROM_OneWireInit -#else -#define MAP_OneWireInit \ - OneWireInit -#endif -#ifdef ROM_OneWireIntClear -#define MAP_OneWireIntClear \ - ROM_OneWireIntClear -#else -#define MAP_OneWireIntClear \ - OneWireIntClear -#endif -#ifdef ROM_OneWireIntDisable -#define MAP_OneWireIntDisable \ - ROM_OneWireIntDisable -#else -#define MAP_OneWireIntDisable \ - OneWireIntDisable -#endif -#ifdef ROM_OneWireIntEnable -#define MAP_OneWireIntEnable \ - ROM_OneWireIntEnable -#else -#define MAP_OneWireIntEnable \ - OneWireIntEnable -#endif -#ifdef ROM_OneWireTransaction -#define MAP_OneWireTransaction \ - ROM_OneWireTransaction -#else -#define MAP_OneWireTransaction \ - OneWireTransaction -#endif -#ifdef ROM_OneWireDMADisable -#define MAP_OneWireDMADisable \ - ROM_OneWireDMADisable -#else -#define MAP_OneWireDMADisable \ - OneWireDMADisable -#endif -#ifdef ROM_OneWireDMAEnable -#define MAP_OneWireDMAEnable \ - ROM_OneWireDMAEnable -#else -#define MAP_OneWireDMAEnable \ - OneWireDMAEnable -#endif - -//***************************************************************************** -// -// Macros for the PWM API. -// -//***************************************************************************** -#ifdef ROM_PWMPulseWidthSet -#define MAP_PWMPulseWidthSet \ - ROM_PWMPulseWidthSet -#else -#define MAP_PWMPulseWidthSet \ - PWMPulseWidthSet -#endif -#ifdef ROM_PWMGenConfigure -#define MAP_PWMGenConfigure \ - ROM_PWMGenConfigure -#else -#define MAP_PWMGenConfigure \ - PWMGenConfigure -#endif -#ifdef ROM_PWMGenPeriodSet -#define MAP_PWMGenPeriodSet \ - ROM_PWMGenPeriodSet -#else -#define MAP_PWMGenPeriodSet \ - PWMGenPeriodSet -#endif -#ifdef ROM_PWMGenPeriodGet -#define MAP_PWMGenPeriodGet \ - ROM_PWMGenPeriodGet -#else -#define MAP_PWMGenPeriodGet \ - PWMGenPeriodGet -#endif -#ifdef ROM_PWMGenEnable -#define MAP_PWMGenEnable \ - ROM_PWMGenEnable -#else -#define MAP_PWMGenEnable \ - PWMGenEnable -#endif -#ifdef ROM_PWMGenDisable -#define MAP_PWMGenDisable \ - ROM_PWMGenDisable -#else -#define MAP_PWMGenDisable \ - PWMGenDisable -#endif -#ifdef ROM_PWMPulseWidthGet -#define MAP_PWMPulseWidthGet \ - ROM_PWMPulseWidthGet -#else -#define MAP_PWMPulseWidthGet \ - PWMPulseWidthGet -#endif -#ifdef ROM_PWMDeadBandEnable -#define MAP_PWMDeadBandEnable \ - ROM_PWMDeadBandEnable -#else -#define MAP_PWMDeadBandEnable \ - PWMDeadBandEnable -#endif -#ifdef ROM_PWMDeadBandDisable -#define MAP_PWMDeadBandDisable \ - ROM_PWMDeadBandDisable -#else -#define MAP_PWMDeadBandDisable \ - PWMDeadBandDisable -#endif -#ifdef ROM_PWMSyncUpdate -#define MAP_PWMSyncUpdate \ - ROM_PWMSyncUpdate -#else -#define MAP_PWMSyncUpdate \ - PWMSyncUpdate -#endif -#ifdef ROM_PWMSyncTimeBase -#define MAP_PWMSyncTimeBase \ - ROM_PWMSyncTimeBase -#else -#define MAP_PWMSyncTimeBase \ - PWMSyncTimeBase -#endif -#ifdef ROM_PWMOutputState -#define MAP_PWMOutputState \ - ROM_PWMOutputState -#else -#define MAP_PWMOutputState \ - PWMOutputState -#endif -#ifdef ROM_PWMOutputInvert -#define MAP_PWMOutputInvert \ - ROM_PWMOutputInvert -#else -#define MAP_PWMOutputInvert \ - PWMOutputInvert -#endif -#ifdef ROM_PWMOutputFault -#define MAP_PWMOutputFault \ - ROM_PWMOutputFault -#else -#define MAP_PWMOutputFault \ - PWMOutputFault -#endif -#ifdef ROM_PWMGenIntTrigEnable -#define MAP_PWMGenIntTrigEnable \ - ROM_PWMGenIntTrigEnable -#else -#define MAP_PWMGenIntTrigEnable \ - PWMGenIntTrigEnable -#endif -#ifdef ROM_PWMGenIntTrigDisable -#define MAP_PWMGenIntTrigDisable \ - ROM_PWMGenIntTrigDisable -#else -#define MAP_PWMGenIntTrigDisable \ - PWMGenIntTrigDisable -#endif -#ifdef ROM_PWMGenIntStatus -#define MAP_PWMGenIntStatus \ - ROM_PWMGenIntStatus -#else -#define MAP_PWMGenIntStatus \ - PWMGenIntStatus -#endif -#ifdef ROM_PWMGenIntClear -#define MAP_PWMGenIntClear \ - ROM_PWMGenIntClear -#else -#define MAP_PWMGenIntClear \ - PWMGenIntClear -#endif -#ifdef ROM_PWMIntEnable -#define MAP_PWMIntEnable \ - ROM_PWMIntEnable -#else -#define MAP_PWMIntEnable \ - PWMIntEnable -#endif -#ifdef ROM_PWMIntDisable -#define MAP_PWMIntDisable \ - ROM_PWMIntDisable -#else -#define MAP_PWMIntDisable \ - PWMIntDisable -#endif -#ifdef ROM_PWMFaultIntClear -#define MAP_PWMFaultIntClear \ - ROM_PWMFaultIntClear -#else -#define MAP_PWMFaultIntClear \ - PWMFaultIntClear -#endif -#ifdef ROM_PWMIntStatus -#define MAP_PWMIntStatus \ - ROM_PWMIntStatus -#else -#define MAP_PWMIntStatus \ - PWMIntStatus -#endif -#ifdef ROM_PWMOutputFaultLevel -#define MAP_PWMOutputFaultLevel \ - ROM_PWMOutputFaultLevel -#else -#define MAP_PWMOutputFaultLevel \ - PWMOutputFaultLevel -#endif -#ifdef ROM_PWMFaultIntClearExt -#define MAP_PWMFaultIntClearExt \ - ROM_PWMFaultIntClearExt -#else -#define MAP_PWMFaultIntClearExt \ - PWMFaultIntClearExt -#endif -#ifdef ROM_PWMGenFaultConfigure -#define MAP_PWMGenFaultConfigure \ - ROM_PWMGenFaultConfigure -#else -#define MAP_PWMGenFaultConfigure \ - PWMGenFaultConfigure -#endif -#ifdef ROM_PWMGenFaultTriggerSet -#define MAP_PWMGenFaultTriggerSet \ - ROM_PWMGenFaultTriggerSet -#else -#define MAP_PWMGenFaultTriggerSet \ - PWMGenFaultTriggerSet -#endif -#ifdef ROM_PWMGenFaultTriggerGet -#define MAP_PWMGenFaultTriggerGet \ - ROM_PWMGenFaultTriggerGet -#else -#define MAP_PWMGenFaultTriggerGet \ - PWMGenFaultTriggerGet -#endif -#ifdef ROM_PWMGenFaultStatus -#define MAP_PWMGenFaultStatus \ - ROM_PWMGenFaultStatus -#else -#define MAP_PWMGenFaultStatus \ - PWMGenFaultStatus -#endif -#ifdef ROM_PWMGenFaultClear -#define MAP_PWMGenFaultClear \ - ROM_PWMGenFaultClear -#else -#define MAP_PWMGenFaultClear \ - PWMGenFaultClear -#endif -#ifdef ROM_PWMClockSet -#define MAP_PWMClockSet \ - ROM_PWMClockSet -#else -#define MAP_PWMClockSet \ - PWMClockSet -#endif -#ifdef ROM_PWMClockGet -#define MAP_PWMClockGet \ - ROM_PWMClockGet -#else -#define MAP_PWMClockGet \ - PWMClockGet -#endif -#ifdef ROM_PWMOutputUpdateMode -#define MAP_PWMOutputUpdateMode \ - ROM_PWMOutputUpdateMode -#else -#define MAP_PWMOutputUpdateMode \ - PWMOutputUpdateMode -#endif - -//***************************************************************************** -// -// Macros for the QEI API. -// -//***************************************************************************** -#ifdef ROM_QEIPositionGet -#define MAP_QEIPositionGet \ - ROM_QEIPositionGet -#else -#define MAP_QEIPositionGet \ - QEIPositionGet -#endif -#ifdef ROM_QEIEnable -#define MAP_QEIEnable \ - ROM_QEIEnable -#else -#define MAP_QEIEnable \ - QEIEnable -#endif -#ifdef ROM_QEIDisable -#define MAP_QEIDisable \ - ROM_QEIDisable -#else -#define MAP_QEIDisable \ - QEIDisable -#endif -#ifdef ROM_QEIConfigure -#define MAP_QEIConfigure \ - ROM_QEIConfigure -#else -#define MAP_QEIConfigure \ - QEIConfigure -#endif -#ifdef ROM_QEIPositionSet -#define MAP_QEIPositionSet \ - ROM_QEIPositionSet -#else -#define MAP_QEIPositionSet \ - QEIPositionSet -#endif -#ifdef ROM_QEIDirectionGet -#define MAP_QEIDirectionGet \ - ROM_QEIDirectionGet -#else -#define MAP_QEIDirectionGet \ - QEIDirectionGet -#endif -#ifdef ROM_QEIErrorGet -#define MAP_QEIErrorGet \ - ROM_QEIErrorGet -#else -#define MAP_QEIErrorGet \ - QEIErrorGet -#endif -#ifdef ROM_QEIVelocityEnable -#define MAP_QEIVelocityEnable \ - ROM_QEIVelocityEnable -#else -#define MAP_QEIVelocityEnable \ - QEIVelocityEnable -#endif -#ifdef ROM_QEIVelocityDisable -#define MAP_QEIVelocityDisable \ - ROM_QEIVelocityDisable -#else -#define MAP_QEIVelocityDisable \ - QEIVelocityDisable -#endif -#ifdef ROM_QEIVelocityConfigure -#define MAP_QEIVelocityConfigure \ - ROM_QEIVelocityConfigure -#else -#define MAP_QEIVelocityConfigure \ - QEIVelocityConfigure -#endif -#ifdef ROM_QEIVelocityGet -#define MAP_QEIVelocityGet \ - ROM_QEIVelocityGet -#else -#define MAP_QEIVelocityGet \ - QEIVelocityGet -#endif -#ifdef ROM_QEIIntEnable -#define MAP_QEIIntEnable \ - ROM_QEIIntEnable -#else -#define MAP_QEIIntEnable \ - QEIIntEnable -#endif -#ifdef ROM_QEIIntDisable -#define MAP_QEIIntDisable \ - ROM_QEIIntDisable -#else -#define MAP_QEIIntDisable \ - QEIIntDisable -#endif -#ifdef ROM_QEIIntStatus -#define MAP_QEIIntStatus \ - ROM_QEIIntStatus -#else -#define MAP_QEIIntStatus \ - QEIIntStatus -#endif -#ifdef ROM_QEIIntClear -#define MAP_QEIIntClear \ - ROM_QEIIntClear -#else -#define MAP_QEIIntClear \ - QEIIntClear -#endif - -//***************************************************************************** -// -// Macros for the SHAMD5 API. -// -//***************************************************************************** -#ifdef ROM_SHAMD5IntStatus -#define MAP_SHAMD5IntStatus \ - ROM_SHAMD5IntStatus -#else -#define MAP_SHAMD5IntStatus \ - SHAMD5IntStatus -#endif -#ifdef ROM_SHAMD5ConfigSet -#define MAP_SHAMD5ConfigSet \ - ROM_SHAMD5ConfigSet -#else -#define MAP_SHAMD5ConfigSet \ - SHAMD5ConfigSet -#endif -#ifdef ROM_SHAMD5DataProcess -#define MAP_SHAMD5DataProcess \ - ROM_SHAMD5DataProcess -#else -#define MAP_SHAMD5DataProcess \ - SHAMD5DataProcess -#endif -#ifdef ROM_SHAMD5DataWrite -#define MAP_SHAMD5DataWrite \ - ROM_SHAMD5DataWrite -#else -#define MAP_SHAMD5DataWrite \ - SHAMD5DataWrite -#endif -#ifdef ROM_SHAMD5DataWriteNonBlocking -#define MAP_SHAMD5DataWriteNonBlocking \ - ROM_SHAMD5DataWriteNonBlocking -#else -#define MAP_SHAMD5DataWriteNonBlocking \ - SHAMD5DataWriteNonBlocking -#endif -#ifdef ROM_SHAMD5DMADisable -#define MAP_SHAMD5DMADisable \ - ROM_SHAMD5DMADisable -#else -#define MAP_SHAMD5DMADisable \ - SHAMD5DMADisable -#endif -#ifdef ROM_SHAMD5DMAEnable -#define MAP_SHAMD5DMAEnable \ - ROM_SHAMD5DMAEnable -#else -#define MAP_SHAMD5DMAEnable \ - SHAMD5DMAEnable -#endif -#ifdef ROM_SHAMD5HashLengthSet -#define MAP_SHAMD5HashLengthSet \ - ROM_SHAMD5HashLengthSet -#else -#define MAP_SHAMD5HashLengthSet \ - SHAMD5HashLengthSet -#endif -#ifdef ROM_SHAMD5HMACKeySet -#define MAP_SHAMD5HMACKeySet \ - ROM_SHAMD5HMACKeySet -#else -#define MAP_SHAMD5HMACKeySet \ - SHAMD5HMACKeySet -#endif -#ifdef ROM_SHAMD5HMACPPKeyGenerate -#define MAP_SHAMD5HMACPPKeyGenerate \ - ROM_SHAMD5HMACPPKeyGenerate -#else -#define MAP_SHAMD5HMACPPKeyGenerate \ - SHAMD5HMACPPKeyGenerate -#endif -#ifdef ROM_SHAMD5HMACPPKeySet -#define MAP_SHAMD5HMACPPKeySet \ - ROM_SHAMD5HMACPPKeySet -#else -#define MAP_SHAMD5HMACPPKeySet \ - SHAMD5HMACPPKeySet -#endif -#ifdef ROM_SHAMD5HMACProcess -#define MAP_SHAMD5HMACProcess \ - ROM_SHAMD5HMACProcess -#else -#define MAP_SHAMD5HMACProcess \ - SHAMD5HMACProcess -#endif -#ifdef ROM_SHAMD5IntClear -#define MAP_SHAMD5IntClear \ - ROM_SHAMD5IntClear -#else -#define MAP_SHAMD5IntClear \ - SHAMD5IntClear -#endif -#ifdef ROM_SHAMD5IntDisable -#define MAP_SHAMD5IntDisable \ - ROM_SHAMD5IntDisable -#else -#define MAP_SHAMD5IntDisable \ - SHAMD5IntDisable -#endif -#ifdef ROM_SHAMD5IntEnable -#define MAP_SHAMD5IntEnable \ - ROM_SHAMD5IntEnable -#else -#define MAP_SHAMD5IntEnable \ - SHAMD5IntEnable -#endif -#ifdef ROM_SHAMD5Reset -#define MAP_SHAMD5Reset \ - ROM_SHAMD5Reset -#else -#define MAP_SHAMD5Reset \ - SHAMD5Reset -#endif -#ifdef ROM_SHAMD5ResultRead -#define MAP_SHAMD5ResultRead \ - ROM_SHAMD5ResultRead -#else -#define MAP_SHAMD5ResultRead \ - SHAMD5ResultRead -#endif - -//***************************************************************************** -// -// Macros for the SMBus API. -// -//***************************************************************************** -#ifdef ROM_SMBusMasterIntProcess -#define MAP_SMBusMasterIntProcess \ - ROM_SMBusMasterIntProcess -#else -#define MAP_SMBusMasterIntProcess \ - SMBusMasterIntProcess -#endif -#ifdef ROM_SMBusARPDisable -#define MAP_SMBusARPDisable \ - ROM_SMBusARPDisable -#else -#define MAP_SMBusARPDisable \ - SMBusARPDisable -#endif -#ifdef ROM_SMBusARPEnable -#define MAP_SMBusARPEnable \ - ROM_SMBusARPEnable -#else -#define MAP_SMBusARPEnable \ - SMBusARPEnable -#endif -#ifdef ROM_SMBusARPUDIDPacketDecode -#define MAP_SMBusARPUDIDPacketDecode \ - ROM_SMBusARPUDIDPacketDecode -#else -#define MAP_SMBusARPUDIDPacketDecode \ - SMBusARPUDIDPacketDecode -#endif -#ifdef ROM_SMBusARPUDIDPacketEncode -#define MAP_SMBusARPUDIDPacketEncode \ - ROM_SMBusARPUDIDPacketEncode -#else -#define MAP_SMBusARPUDIDPacketEncode \ - SMBusARPUDIDPacketEncode -#endif -#ifdef ROM_SMBusMasterARPAssignAddress -#define MAP_SMBusMasterARPAssignAddress \ - ROM_SMBusMasterARPAssignAddress -#else -#define MAP_SMBusMasterARPAssignAddress \ - SMBusMasterARPAssignAddress -#endif -#ifdef ROM_SMBusMasterARPGetUDIDDir -#define MAP_SMBusMasterARPGetUDIDDir \ - ROM_SMBusMasterARPGetUDIDDir -#else -#define MAP_SMBusMasterARPGetUDIDDir \ - SMBusMasterARPGetUDIDDir -#endif -#ifdef ROM_SMBusMasterARPGetUDIDGen -#define MAP_SMBusMasterARPGetUDIDGen \ - ROM_SMBusMasterARPGetUDIDGen -#else -#define MAP_SMBusMasterARPGetUDIDGen \ - SMBusMasterARPGetUDIDGen -#endif -#ifdef ROM_SMBusMasterARPNotifyMaster -#define MAP_SMBusMasterARPNotifyMaster \ - ROM_SMBusMasterARPNotifyMaster -#else -#define MAP_SMBusMasterARPNotifyMaster \ - SMBusMasterARPNotifyMaster -#endif -#ifdef ROM_SMBusMasterARPPrepareToARP -#define MAP_SMBusMasterARPPrepareToARP \ - ROM_SMBusMasterARPPrepareToARP -#else -#define MAP_SMBusMasterARPPrepareToARP \ - SMBusMasterARPPrepareToARP -#endif -#ifdef ROM_SMBusMasterARPResetDeviceDir -#define MAP_SMBusMasterARPResetDeviceDir \ - ROM_SMBusMasterARPResetDeviceDir -#else -#define MAP_SMBusMasterARPResetDeviceDir \ - SMBusMasterARPResetDeviceDir -#endif -#ifdef ROM_SMBusMasterARPResetDeviceGen -#define MAP_SMBusMasterARPResetDeviceGen \ - ROM_SMBusMasterARPResetDeviceGen -#else -#define MAP_SMBusMasterARPResetDeviceGen \ - SMBusMasterARPResetDeviceGen -#endif -#ifdef ROM_SMBusMasterBlockProcessCall -#define MAP_SMBusMasterBlockProcessCall \ - ROM_SMBusMasterBlockProcessCall -#else -#define MAP_SMBusMasterBlockProcessCall \ - SMBusMasterBlockProcessCall -#endif -#ifdef ROM_SMBusMasterBlockRead -#define MAP_SMBusMasterBlockRead \ - ROM_SMBusMasterBlockRead -#else -#define MAP_SMBusMasterBlockRead \ - SMBusMasterBlockRead -#endif -#ifdef ROM_SMBusMasterBlockWrite -#define MAP_SMBusMasterBlockWrite \ - ROM_SMBusMasterBlockWrite -#else -#define MAP_SMBusMasterBlockWrite \ - SMBusMasterBlockWrite -#endif -#ifdef ROM_SMBusMasterByteReceive -#define MAP_SMBusMasterByteReceive \ - ROM_SMBusMasterByteReceive -#else -#define MAP_SMBusMasterByteReceive \ - SMBusMasterByteReceive -#endif -#ifdef ROM_SMBusMasterByteSend -#define MAP_SMBusMasterByteSend \ - ROM_SMBusMasterByteSend -#else -#define MAP_SMBusMasterByteSend \ - SMBusMasterByteSend -#endif -#ifdef ROM_SMBusMasterByteWordRead -#define MAP_SMBusMasterByteWordRead \ - ROM_SMBusMasterByteWordRead -#else -#define MAP_SMBusMasterByteWordRead \ - SMBusMasterByteWordRead -#endif -#ifdef ROM_SMBusMasterByteWordWrite -#define MAP_SMBusMasterByteWordWrite \ - ROM_SMBusMasterByteWordWrite -#else -#define MAP_SMBusMasterByteWordWrite \ - SMBusMasterByteWordWrite -#endif -#ifdef ROM_SMBusMasterHostNotify -#define MAP_SMBusMasterHostNotify \ - ROM_SMBusMasterHostNotify -#else -#define MAP_SMBusMasterHostNotify \ - SMBusMasterHostNotify -#endif -#ifdef ROM_SMBusMasterI2CRead -#define MAP_SMBusMasterI2CRead \ - ROM_SMBusMasterI2CRead -#else -#define MAP_SMBusMasterI2CRead \ - SMBusMasterI2CRead -#endif -#ifdef ROM_SMBusMasterI2CWrite -#define MAP_SMBusMasterI2CWrite \ - ROM_SMBusMasterI2CWrite -#else -#define MAP_SMBusMasterI2CWrite \ - SMBusMasterI2CWrite -#endif -#ifdef ROM_SMBusMasterI2CWriteRead -#define MAP_SMBusMasterI2CWriteRead \ - ROM_SMBusMasterI2CWriteRead -#else -#define MAP_SMBusMasterI2CWriteRead \ - SMBusMasterI2CWriteRead -#endif -#ifdef ROM_SMBusMasterInit -#define MAP_SMBusMasterInit \ - ROM_SMBusMasterInit -#else -#define MAP_SMBusMasterInit \ - SMBusMasterInit -#endif -#ifdef ROM_SMBusMasterIntEnable -#define MAP_SMBusMasterIntEnable \ - ROM_SMBusMasterIntEnable -#else -#define MAP_SMBusMasterIntEnable \ - SMBusMasterIntEnable -#endif -#ifdef ROM_SMBusMasterProcessCall -#define MAP_SMBusMasterProcessCall \ - ROM_SMBusMasterProcessCall -#else -#define MAP_SMBusMasterProcessCall \ - SMBusMasterProcessCall -#endif -#ifdef ROM_SMBusMasterQuickCommand -#define MAP_SMBusMasterQuickCommand \ - ROM_SMBusMasterQuickCommand -#else -#define MAP_SMBusMasterQuickCommand \ - SMBusMasterQuickCommand -#endif -#ifdef ROM_SMBusPECDisable -#define MAP_SMBusPECDisable \ - ROM_SMBusPECDisable -#else -#define MAP_SMBusPECDisable \ - SMBusPECDisable -#endif -#ifdef ROM_SMBusPECEnable -#define MAP_SMBusPECEnable \ - ROM_SMBusPECEnable -#else -#define MAP_SMBusPECEnable \ - SMBusPECEnable -#endif -#ifdef ROM_SMBusRxPacketSizeGet -#define MAP_SMBusRxPacketSizeGet \ - ROM_SMBusRxPacketSizeGet -#else -#define MAP_SMBusRxPacketSizeGet \ - SMBusRxPacketSizeGet -#endif -#ifdef ROM_SMBusSlaveACKSend -#define MAP_SMBusSlaveACKSend \ - ROM_SMBusSlaveACKSend -#else -#define MAP_SMBusSlaveACKSend \ - SMBusSlaveACKSend -#endif -#ifdef ROM_SMBusSlaveAddressSet -#define MAP_SMBusSlaveAddressSet \ - ROM_SMBusSlaveAddressSet -#else -#define MAP_SMBusSlaveAddressSet \ - SMBusSlaveAddressSet -#endif -#ifdef ROM_SMBusSlaveARPFlagARGet -#define MAP_SMBusSlaveARPFlagARGet \ - ROM_SMBusSlaveARPFlagARGet -#else -#define MAP_SMBusSlaveARPFlagARGet \ - SMBusSlaveARPFlagARGet -#endif -#ifdef ROM_SMBusSlaveARPFlagARSet -#define MAP_SMBusSlaveARPFlagARSet \ - ROM_SMBusSlaveARPFlagARSet -#else -#define MAP_SMBusSlaveARPFlagARSet \ - SMBusSlaveARPFlagARSet -#endif -#ifdef ROM_SMBusSlaveARPFlagAVGet -#define MAP_SMBusSlaveARPFlagAVGet \ - ROM_SMBusSlaveARPFlagAVGet -#else -#define MAP_SMBusSlaveARPFlagAVGet \ - SMBusSlaveARPFlagAVGet -#endif -#ifdef ROM_SMBusSlaveARPFlagAVSet -#define MAP_SMBusSlaveARPFlagAVSet \ - ROM_SMBusSlaveARPFlagAVSet -#else -#define MAP_SMBusSlaveARPFlagAVSet \ - SMBusSlaveARPFlagAVSet -#endif -#ifdef ROM_SMBusSlaveBlockTransferDisable -#define MAP_SMBusSlaveBlockTransferDisable \ - ROM_SMBusSlaveBlockTransferDisable -#else -#define MAP_SMBusSlaveBlockTransferDisable \ - SMBusSlaveBlockTransferDisable -#endif -#ifdef ROM_SMBusSlaveBlockTransferEnable -#define MAP_SMBusSlaveBlockTransferEnable \ - ROM_SMBusSlaveBlockTransferEnable -#else -#define MAP_SMBusSlaveBlockTransferEnable \ - SMBusSlaveBlockTransferEnable -#endif -#ifdef ROM_SMBusSlaveCommandGet -#define MAP_SMBusSlaveCommandGet \ - ROM_SMBusSlaveCommandGet -#else -#define MAP_SMBusSlaveCommandGet \ - SMBusSlaveCommandGet -#endif -#ifdef ROM_SMBusSlaveI2CDisable -#define MAP_SMBusSlaveI2CDisable \ - ROM_SMBusSlaveI2CDisable -#else -#define MAP_SMBusSlaveI2CDisable \ - SMBusSlaveI2CDisable -#endif -#ifdef ROM_SMBusSlaveI2CEnable -#define MAP_SMBusSlaveI2CEnable \ - ROM_SMBusSlaveI2CEnable -#else -#define MAP_SMBusSlaveI2CEnable \ - SMBusSlaveI2CEnable -#endif -#ifdef ROM_SMBusSlaveInit -#define MAP_SMBusSlaveInit \ - ROM_SMBusSlaveInit -#else -#define MAP_SMBusSlaveInit \ - SMBusSlaveInit -#endif -#ifdef ROM_SMBusSlaveIntAddressGet -#define MAP_SMBusSlaveIntAddressGet \ - ROM_SMBusSlaveIntAddressGet -#else -#define MAP_SMBusSlaveIntAddressGet \ - SMBusSlaveIntAddressGet -#endif -#ifdef ROM_SMBusSlaveIntEnable -#define MAP_SMBusSlaveIntEnable \ - ROM_SMBusSlaveIntEnable -#else -#define MAP_SMBusSlaveIntEnable \ - SMBusSlaveIntEnable -#endif -#ifdef ROM_SMBusSlaveIntProcess -#define MAP_SMBusSlaveIntProcess \ - ROM_SMBusSlaveIntProcess -#else -#define MAP_SMBusSlaveIntProcess \ - SMBusSlaveIntProcess -#endif -#ifdef ROM_SMBusSlaveManualACKDisable -#define MAP_SMBusSlaveManualACKDisable \ - ROM_SMBusSlaveManualACKDisable -#else -#define MAP_SMBusSlaveManualACKDisable \ - SMBusSlaveManualACKDisable -#endif -#ifdef ROM_SMBusSlaveManualACKEnable -#define MAP_SMBusSlaveManualACKEnable \ - ROM_SMBusSlaveManualACKEnable -#else -#define MAP_SMBusSlaveManualACKEnable \ - SMBusSlaveManualACKEnable -#endif -#ifdef ROM_SMBusSlaveManualACKStatusGet -#define MAP_SMBusSlaveManualACKStatusGet \ - ROM_SMBusSlaveManualACKStatusGet -#else -#define MAP_SMBusSlaveManualACKStatusGet \ - SMBusSlaveManualACKStatusGet -#endif -#ifdef ROM_SMBusSlaveProcessCallDisable -#define MAP_SMBusSlaveProcessCallDisable \ - ROM_SMBusSlaveProcessCallDisable -#else -#define MAP_SMBusSlaveProcessCallDisable \ - SMBusSlaveProcessCallDisable -#endif -#ifdef ROM_SMBusSlaveProcessCallEnable -#define MAP_SMBusSlaveProcessCallEnable \ - ROM_SMBusSlaveProcessCallEnable -#else -#define MAP_SMBusSlaveProcessCallEnable \ - SMBusSlaveProcessCallEnable -#endif -#ifdef ROM_SMBusSlaveRxBufferSet -#define MAP_SMBusSlaveRxBufferSet \ - ROM_SMBusSlaveRxBufferSet -#else -#define MAP_SMBusSlaveRxBufferSet \ - SMBusSlaveRxBufferSet -#endif -#ifdef ROM_SMBusSlaveTransferInit -#define MAP_SMBusSlaveTransferInit \ - ROM_SMBusSlaveTransferInit -#else -#define MAP_SMBusSlaveTransferInit \ - SMBusSlaveTransferInit -#endif -#ifdef ROM_SMBusSlaveTxBufferSet -#define MAP_SMBusSlaveTxBufferSet \ - ROM_SMBusSlaveTxBufferSet -#else -#define MAP_SMBusSlaveTxBufferSet \ - SMBusSlaveTxBufferSet -#endif -#ifdef ROM_SMBusSlaveUDIDSet -#define MAP_SMBusSlaveUDIDSet \ - ROM_SMBusSlaveUDIDSet -#else -#define MAP_SMBusSlaveUDIDSet \ - SMBusSlaveUDIDSet -#endif -#ifdef ROM_SMBusStatusGet -#define MAP_SMBusStatusGet \ - ROM_SMBusStatusGet -#else -#define MAP_SMBusStatusGet \ - SMBusStatusGet -#endif -#ifdef ROM_SMBusSlaveDataSend -#define MAP_SMBusSlaveDataSend \ - ROM_SMBusSlaveDataSend -#else -#define MAP_SMBusSlaveDataSend \ - SMBusSlaveDataSend -#endif -#ifdef ROM_SMBusFIFOEnable -#define MAP_SMBusFIFOEnable \ - ROM_SMBusFIFOEnable -#else -#define MAP_SMBusFIFOEnable \ - SMBusFIFOEnable -#endif -#ifdef ROM_SMBusFIFODisable -#define MAP_SMBusFIFODisable \ - ROM_SMBusFIFODisable -#else -#define MAP_SMBusFIFODisable \ - SMBusFIFODisable -#endif -#ifdef ROM_SMBusDMAEnable -#define MAP_SMBusDMAEnable \ - ROM_SMBusDMAEnable -#else -#define MAP_SMBusDMAEnable \ - SMBusDMAEnable -#endif -#ifdef ROM_SMBusDMADisable -#define MAP_SMBusDMADisable \ - ROM_SMBusDMADisable -#else -#define MAP_SMBusDMADisable \ - SMBusDMADisable -#endif - -//***************************************************************************** -// -// Macros for the SPIFlash API. -// -//***************************************************************************** -#ifdef ROM_SPIFlashIntHandler -#define MAP_SPIFlashIntHandler \ - ROM_SPIFlashIntHandler -#else -#define MAP_SPIFlashIntHandler \ - SPIFlashIntHandler -#endif -#ifdef ROM_SPIFlashInit -#define MAP_SPIFlashInit \ - ROM_SPIFlashInit -#else -#define MAP_SPIFlashInit \ - SPIFlashInit -#endif -#ifdef ROM_SPIFlashWriteStatus -#define MAP_SPIFlashWriteStatus \ - ROM_SPIFlashWriteStatus -#else -#define MAP_SPIFlashWriteStatus \ - SPIFlashWriteStatus -#endif -#ifdef ROM_SPIFlashPageProgram -#define MAP_SPIFlashPageProgram \ - ROM_SPIFlashPageProgram -#else -#define MAP_SPIFlashPageProgram \ - SPIFlashPageProgram -#endif -#ifdef ROM_SPIFlashPageProgramNonBlocking -#define MAP_SPIFlashPageProgramNonBlocking \ - ROM_SPIFlashPageProgramNonBlocking -#else -#define MAP_SPIFlashPageProgramNonBlocking \ - SPIFlashPageProgramNonBlocking -#endif -#ifdef ROM_SPIFlashRead -#define MAP_SPIFlashRead \ - ROM_SPIFlashRead -#else -#define MAP_SPIFlashRead \ - SPIFlashRead -#endif -#ifdef ROM_SPIFlashReadNonBlocking -#define MAP_SPIFlashReadNonBlocking \ - ROM_SPIFlashReadNonBlocking -#else -#define MAP_SPIFlashReadNonBlocking \ - SPIFlashReadNonBlocking -#endif -#ifdef ROM_SPIFlashWriteDisable -#define MAP_SPIFlashWriteDisable \ - ROM_SPIFlashWriteDisable -#else -#define MAP_SPIFlashWriteDisable \ - SPIFlashWriteDisable -#endif -#ifdef ROM_SPIFlashReadStatus -#define MAP_SPIFlashReadStatus \ - ROM_SPIFlashReadStatus -#else -#define MAP_SPIFlashReadStatus \ - SPIFlashReadStatus -#endif -#ifdef ROM_SPIFlashWriteEnable -#define MAP_SPIFlashWriteEnable \ - ROM_SPIFlashWriteEnable -#else -#define MAP_SPIFlashWriteEnable \ - SPIFlashWriteEnable -#endif -#ifdef ROM_SPIFlashFastRead -#define MAP_SPIFlashFastRead \ - ROM_SPIFlashFastRead -#else -#define MAP_SPIFlashFastRead \ - SPIFlashFastRead -#endif -#ifdef ROM_SPIFlashFastReadNonBlocking -#define MAP_SPIFlashFastReadNonBlocking \ - ROM_SPIFlashFastReadNonBlocking -#else -#define MAP_SPIFlashFastReadNonBlocking \ - SPIFlashFastReadNonBlocking -#endif -#ifdef ROM_SPIFlashSectorErase -#define MAP_SPIFlashSectorErase \ - ROM_SPIFlashSectorErase -#else -#define MAP_SPIFlashSectorErase \ - SPIFlashSectorErase -#endif -#ifdef ROM_SPIFlashDualRead -#define MAP_SPIFlashDualRead \ - ROM_SPIFlashDualRead -#else -#define MAP_SPIFlashDualRead \ - SPIFlashDualRead -#endif -#ifdef ROM_SPIFlashDualReadNonBlocking -#define MAP_SPIFlashDualReadNonBlocking \ - ROM_SPIFlashDualReadNonBlocking -#else -#define MAP_SPIFlashDualReadNonBlocking \ - SPIFlashDualReadNonBlocking -#endif -#ifdef ROM_SPIFlashBlockErase32 -#define MAP_SPIFlashBlockErase32 \ - ROM_SPIFlashBlockErase32 -#else -#define MAP_SPIFlashBlockErase32 \ - SPIFlashBlockErase32 -#endif -#ifdef ROM_SPIFlashQuadRead -#define MAP_SPIFlashQuadRead \ - ROM_SPIFlashQuadRead -#else -#define MAP_SPIFlashQuadRead \ - SPIFlashQuadRead -#endif -#ifdef ROM_SPIFlashQuadReadNonBlocking -#define MAP_SPIFlashQuadReadNonBlocking \ - ROM_SPIFlashQuadReadNonBlocking -#else -#define MAP_SPIFlashQuadReadNonBlocking \ - SPIFlashQuadReadNonBlocking -#endif -#ifdef ROM_SPIFlashReadID -#define MAP_SPIFlashReadID \ - ROM_SPIFlashReadID -#else -#define MAP_SPIFlashReadID \ - SPIFlashReadID -#endif -#ifdef ROM_SPIFlashChipErase -#define MAP_SPIFlashChipErase \ - ROM_SPIFlashChipErase -#else -#define MAP_SPIFlashChipErase \ - SPIFlashChipErase -#endif -#ifdef ROM_SPIFlashBlockErase64 -#define MAP_SPIFlashBlockErase64 \ - ROM_SPIFlashBlockErase64 -#else -#define MAP_SPIFlashBlockErase64 \ - SPIFlashBlockErase64 -#endif - -//***************************************************************************** -// -// Macros for the SSI API. -// -//***************************************************************************** -#ifdef ROM_SSIDataPut -#define MAP_SSIDataPut \ - ROM_SSIDataPut -#else -#define MAP_SSIDataPut \ - SSIDataPut -#endif -#ifdef ROM_SSIConfigSetExpClk -#define MAP_SSIConfigSetExpClk \ - ROM_SSIConfigSetExpClk -#else -#define MAP_SSIConfigSetExpClk \ - SSIConfigSetExpClk -#endif -#ifdef ROM_SSIEnable -#define MAP_SSIEnable \ - ROM_SSIEnable -#else -#define MAP_SSIEnable \ - SSIEnable -#endif -#ifdef ROM_SSIDisable -#define MAP_SSIDisable \ - ROM_SSIDisable -#else -#define MAP_SSIDisable \ - SSIDisable -#endif -#ifdef ROM_SSIIntEnable -#define MAP_SSIIntEnable \ - ROM_SSIIntEnable -#else -#define MAP_SSIIntEnable \ - SSIIntEnable -#endif -#ifdef ROM_SSIIntDisable -#define MAP_SSIIntDisable \ - ROM_SSIIntDisable -#else -#define MAP_SSIIntDisable \ - SSIIntDisable -#endif -#ifdef ROM_SSIIntStatus -#define MAP_SSIIntStatus \ - ROM_SSIIntStatus -#else -#define MAP_SSIIntStatus \ - SSIIntStatus -#endif -#ifdef ROM_SSIIntClear -#define MAP_SSIIntClear \ - ROM_SSIIntClear -#else -#define MAP_SSIIntClear \ - SSIIntClear -#endif -#ifdef ROM_SSIDataPutNonBlocking -#define MAP_SSIDataPutNonBlocking \ - ROM_SSIDataPutNonBlocking -#else -#define MAP_SSIDataPutNonBlocking \ - SSIDataPutNonBlocking -#endif -#ifdef ROM_SSIDataGet -#define MAP_SSIDataGet \ - ROM_SSIDataGet -#else -#define MAP_SSIDataGet \ - SSIDataGet -#endif -#ifdef ROM_SSIDataGetNonBlocking -#define MAP_SSIDataGetNonBlocking \ - ROM_SSIDataGetNonBlocking -#else -#define MAP_SSIDataGetNonBlocking \ - SSIDataGetNonBlocking -#endif -#ifdef ROM_SSIDMAEnable -#define MAP_SSIDMAEnable \ - ROM_SSIDMAEnable -#else -#define MAP_SSIDMAEnable \ - SSIDMAEnable -#endif -#ifdef ROM_SSIDMADisable -#define MAP_SSIDMADisable \ - ROM_SSIDMADisable -#else -#define MAP_SSIDMADisable \ - SSIDMADisable -#endif -#ifdef ROM_SSIBusy -#define MAP_SSIBusy \ - ROM_SSIBusy -#else -#define MAP_SSIBusy \ - SSIBusy -#endif -#ifdef ROM_SSIClockSourceGet -#define MAP_SSIClockSourceGet \ - ROM_SSIClockSourceGet -#else -#define MAP_SSIClockSourceGet \ - SSIClockSourceGet -#endif -#ifdef ROM_SSIClockSourceSet -#define MAP_SSIClockSourceSet \ - ROM_SSIClockSourceSet -#else -#define MAP_SSIClockSourceSet \ - SSIClockSourceSet -#endif -#ifdef ROM_SSIAdvModeSet -#define MAP_SSIAdvModeSet \ - ROM_SSIAdvModeSet -#else -#define MAP_SSIAdvModeSet \ - SSIAdvModeSet -#endif -#ifdef ROM_SSIAdvDataPutFrameEnd -#define MAP_SSIAdvDataPutFrameEnd \ - ROM_SSIAdvDataPutFrameEnd -#else -#define MAP_SSIAdvDataPutFrameEnd \ - SSIAdvDataPutFrameEnd -#endif -#ifdef ROM_SSIAdvDataPutFrameEndNonBlocking -#define MAP_SSIAdvDataPutFrameEndNonBlocking \ - ROM_SSIAdvDataPutFrameEndNonBlocking -#else -#define MAP_SSIAdvDataPutFrameEndNonBlocking \ - SSIAdvDataPutFrameEndNonBlocking -#endif -#ifdef ROM_SSIAdvFrameHoldEnable -#define MAP_SSIAdvFrameHoldEnable \ - ROM_SSIAdvFrameHoldEnable -#else -#define MAP_SSIAdvFrameHoldEnable \ - SSIAdvFrameHoldEnable -#endif -#ifdef ROM_SSIAdvFrameHoldDisable -#define MAP_SSIAdvFrameHoldDisable \ - ROM_SSIAdvFrameHoldDisable -#else -#define MAP_SSIAdvFrameHoldDisable \ - SSIAdvFrameHoldDisable -#endif - -//***************************************************************************** -// -// Macros for the SysCtl API. -// -//***************************************************************************** -#ifdef ROM_SysCtlSleep -#define MAP_SysCtlSleep \ - ROM_SysCtlSleep -#else -#define MAP_SysCtlSleep \ - SysCtlSleep -#endif -#ifdef ROM_SysCtlSRAMSizeGet -#define MAP_SysCtlSRAMSizeGet \ - ROM_SysCtlSRAMSizeGet -#else -#define MAP_SysCtlSRAMSizeGet \ - SysCtlSRAMSizeGet -#endif -#ifdef ROM_SysCtlFlashSizeGet -#define MAP_SysCtlFlashSizeGet \ - ROM_SysCtlFlashSizeGet -#else -#define MAP_SysCtlFlashSizeGet \ - SysCtlFlashSizeGet -#endif -#ifdef ROM_SysCtlPeripheralPresent -#define MAP_SysCtlPeripheralPresent \ - ROM_SysCtlPeripheralPresent -#else -#define MAP_SysCtlPeripheralPresent \ - SysCtlPeripheralPresent -#endif -#ifdef ROM_SysCtlPeripheralReset -#define MAP_SysCtlPeripheralReset \ - ROM_SysCtlPeripheralReset -#else -#define MAP_SysCtlPeripheralReset \ - SysCtlPeripheralReset -#endif -#ifdef ROM_SysCtlPeripheralEnable -#define MAP_SysCtlPeripheralEnable \ - ROM_SysCtlPeripheralEnable -#else -#define MAP_SysCtlPeripheralEnable \ - SysCtlPeripheralEnable -#endif -#ifdef ROM_SysCtlPeripheralDisable -#define MAP_SysCtlPeripheralDisable \ - ROM_SysCtlPeripheralDisable -#else -#define MAP_SysCtlPeripheralDisable \ - SysCtlPeripheralDisable -#endif -#ifdef ROM_SysCtlPeripheralSleepEnable -#define MAP_SysCtlPeripheralSleepEnable \ - ROM_SysCtlPeripheralSleepEnable -#else -#define MAP_SysCtlPeripheralSleepEnable \ - SysCtlPeripheralSleepEnable -#endif -#ifdef ROM_SysCtlPeripheralSleepDisable -#define MAP_SysCtlPeripheralSleepDisable \ - ROM_SysCtlPeripheralSleepDisable -#else -#define MAP_SysCtlPeripheralSleepDisable \ - SysCtlPeripheralSleepDisable -#endif -#ifdef ROM_SysCtlPeripheralDeepSleepEnable -#define MAP_SysCtlPeripheralDeepSleepEnable \ - ROM_SysCtlPeripheralDeepSleepEnable -#else -#define MAP_SysCtlPeripheralDeepSleepEnable \ - SysCtlPeripheralDeepSleepEnable -#endif -#ifdef ROM_SysCtlPeripheralDeepSleepDisable -#define MAP_SysCtlPeripheralDeepSleepDisable \ - ROM_SysCtlPeripheralDeepSleepDisable -#else -#define MAP_SysCtlPeripheralDeepSleepDisable \ - SysCtlPeripheralDeepSleepDisable -#endif -#ifdef ROM_SysCtlPeripheralClockGating -#define MAP_SysCtlPeripheralClockGating \ - ROM_SysCtlPeripheralClockGating -#else -#define MAP_SysCtlPeripheralClockGating \ - SysCtlPeripheralClockGating -#endif -#ifdef ROM_SysCtlIntEnable -#define MAP_SysCtlIntEnable \ - ROM_SysCtlIntEnable -#else -#define MAP_SysCtlIntEnable \ - SysCtlIntEnable -#endif -#ifdef ROM_SysCtlIntDisable -#define MAP_SysCtlIntDisable \ - ROM_SysCtlIntDisable -#else -#define MAP_SysCtlIntDisable \ - SysCtlIntDisable -#endif -#ifdef ROM_SysCtlIntClear -#define MAP_SysCtlIntClear \ - ROM_SysCtlIntClear -#else -#define MAP_SysCtlIntClear \ - SysCtlIntClear -#endif -#ifdef ROM_SysCtlIntStatus -#define MAP_SysCtlIntStatus \ - ROM_SysCtlIntStatus -#else -#define MAP_SysCtlIntStatus \ - SysCtlIntStatus -#endif -#ifdef ROM_SysCtlReset -#define MAP_SysCtlReset \ - ROM_SysCtlReset -#else -#define MAP_SysCtlReset \ - SysCtlReset -#endif -#ifdef ROM_SysCtlDeepSleep -#define MAP_SysCtlDeepSleep \ - ROM_SysCtlDeepSleep -#else -#define MAP_SysCtlDeepSleep \ - SysCtlDeepSleep -#endif -#ifdef ROM_SysCtlResetCauseGet -#define MAP_SysCtlResetCauseGet \ - ROM_SysCtlResetCauseGet -#else -#define MAP_SysCtlResetCauseGet \ - SysCtlResetCauseGet -#endif -#ifdef ROM_SysCtlResetCauseClear -#define MAP_SysCtlResetCauseClear \ - ROM_SysCtlResetCauseClear -#else -#define MAP_SysCtlResetCauseClear \ - SysCtlResetCauseClear -#endif -#ifdef ROM_SysCtlClockSet -#define MAP_SysCtlClockSet \ - ROM_SysCtlClockSet -#else -#define MAP_SysCtlClockSet \ - SysCtlClockSet -#endif -#ifdef ROM_SysCtlClockGet -#define MAP_SysCtlClockGet \ - ROM_SysCtlClockGet -#else -#define MAP_SysCtlClockGet \ - SysCtlClockGet -#endif -#ifdef ROM_SysCtlPWMClockSet -#define MAP_SysCtlPWMClockSet \ - ROM_SysCtlPWMClockSet -#else -#define MAP_SysCtlPWMClockSet \ - SysCtlPWMClockSet -#endif -#ifdef ROM_SysCtlPWMClockGet -#define MAP_SysCtlPWMClockGet \ - ROM_SysCtlPWMClockGet -#else -#define MAP_SysCtlPWMClockGet \ - SysCtlPWMClockGet -#endif -#ifdef ROM_SysCtlUSBPLLEnable -#define MAP_SysCtlUSBPLLEnable \ - ROM_SysCtlUSBPLLEnable -#else -#define MAP_SysCtlUSBPLLEnable \ - SysCtlUSBPLLEnable -#endif -#ifdef ROM_SysCtlUSBPLLDisable -#define MAP_SysCtlUSBPLLDisable \ - ROM_SysCtlUSBPLLDisable -#else -#define MAP_SysCtlUSBPLLDisable \ - SysCtlUSBPLLDisable -#endif -#ifdef ROM_SysCtlDelay -#define MAP_SysCtlDelay \ - ROM_SysCtlDelay -#else -#define MAP_SysCtlDelay \ - SysCtlDelay -#endif -#ifdef ROM_SysCtlPeripheralReady -#define MAP_SysCtlPeripheralReady \ - ROM_SysCtlPeripheralReady -#else -#define MAP_SysCtlPeripheralReady \ - SysCtlPeripheralReady -#endif -#ifdef ROM_SysCtlPeripheralPowerOn -#define MAP_SysCtlPeripheralPowerOn \ - ROM_SysCtlPeripheralPowerOn -#else -#define MAP_SysCtlPeripheralPowerOn \ - SysCtlPeripheralPowerOn -#endif -#ifdef ROM_SysCtlPeripheralPowerOff -#define MAP_SysCtlPeripheralPowerOff \ - ROM_SysCtlPeripheralPowerOff -#else -#define MAP_SysCtlPeripheralPowerOff \ - SysCtlPeripheralPowerOff -#endif -#ifdef ROM_SysCtlMOSCConfigSet -#define MAP_SysCtlMOSCConfigSet \ - ROM_SysCtlMOSCConfigSet -#else -#define MAP_SysCtlMOSCConfigSet \ - SysCtlMOSCConfigSet -#endif -#ifdef ROM_SysCtlPIOSCCalibrate -#define MAP_SysCtlPIOSCCalibrate \ - ROM_SysCtlPIOSCCalibrate -#else -#define MAP_SysCtlPIOSCCalibrate \ - SysCtlPIOSCCalibrate -#endif -#ifdef ROM_SysCtlDeepSleepClockSet -#define MAP_SysCtlDeepSleepClockSet \ - ROM_SysCtlDeepSleepClockSet -#else -#define MAP_SysCtlDeepSleepClockSet \ - SysCtlDeepSleepClockSet -#endif -#ifdef ROM_SysCtlDeepSleepClockConfigSet -#define MAP_SysCtlDeepSleepClockConfigSet \ - ROM_SysCtlDeepSleepClockConfigSet -#else -#define MAP_SysCtlDeepSleepClockConfigSet \ - SysCtlDeepSleepClockConfigSet -#endif -#ifdef ROM_SysCtlClockFreqSet -#define MAP_SysCtlClockFreqSet \ - ROM_SysCtlClockFreqSet -#else -#define MAP_SysCtlClockFreqSet \ - SysCtlClockFreqSet -#endif -#ifdef ROM_SysCtlResetBehaviorSet -#define MAP_SysCtlResetBehaviorSet \ - ROM_SysCtlResetBehaviorSet -#else -#define MAP_SysCtlResetBehaviorSet \ - SysCtlResetBehaviorSet -#endif -#ifdef ROM_SysCtlResetBehaviorGet -#define MAP_SysCtlResetBehaviorGet \ - ROM_SysCtlResetBehaviorGet -#else -#define MAP_SysCtlResetBehaviorGet \ - SysCtlResetBehaviorGet -#endif -#ifdef ROM_SysCtlFlashSectorSizeGet -#define MAP_SysCtlFlashSectorSizeGet \ - ROM_SysCtlFlashSectorSizeGet -#else -#define MAP_SysCtlFlashSectorSizeGet \ - SysCtlFlashSectorSizeGet -#endif -#ifdef ROM_SysCtlVoltageEventConfig -#define MAP_SysCtlVoltageEventConfig \ - ROM_SysCtlVoltageEventConfig -#else -#define MAP_SysCtlVoltageEventConfig \ - SysCtlVoltageEventConfig -#endif -#ifdef ROM_SysCtlVoltageEventStatus -#define MAP_SysCtlVoltageEventStatus \ - ROM_SysCtlVoltageEventStatus -#else -#define MAP_SysCtlVoltageEventStatus \ - SysCtlVoltageEventStatus -#endif -#ifdef ROM_SysCtlVoltageEventClear -#define MAP_SysCtlVoltageEventClear \ - ROM_SysCtlVoltageEventClear -#else -#define MAP_SysCtlVoltageEventClear \ - SysCtlVoltageEventClear -#endif -#ifdef ROM_SysCtlNMIStatus -#define MAP_SysCtlNMIStatus \ - ROM_SysCtlNMIStatus -#else -#define MAP_SysCtlNMIStatus \ - SysCtlNMIStatus -#endif -#ifdef ROM_SysCtlNMIClear -#define MAP_SysCtlNMIClear \ - ROM_SysCtlNMIClear -#else -#define MAP_SysCtlNMIClear \ - SysCtlNMIClear -#endif -#ifdef ROM_SysCtlClockOutConfig -#define MAP_SysCtlClockOutConfig \ - ROM_SysCtlClockOutConfig -#else -#define MAP_SysCtlClockOutConfig \ - SysCtlClockOutConfig -#endif -#ifdef ROM_SysCtlAltClkConfig -#define MAP_SysCtlAltClkConfig \ - ROM_SysCtlAltClkConfig -#else -#define MAP_SysCtlAltClkConfig \ - SysCtlAltClkConfig -#endif - -//***************************************************************************** -// -// Macros for the SysExc API. -// -//***************************************************************************** -#ifdef ROM_SysExcIntStatus -#define MAP_SysExcIntStatus \ - ROM_SysExcIntStatus -#else -#define MAP_SysExcIntStatus \ - SysExcIntStatus -#endif -#ifdef ROM_SysExcIntClear -#define MAP_SysExcIntClear \ - ROM_SysExcIntClear -#else -#define MAP_SysExcIntClear \ - SysExcIntClear -#endif -#ifdef ROM_SysExcIntDisable -#define MAP_SysExcIntDisable \ - ROM_SysExcIntDisable -#else -#define MAP_SysExcIntDisable \ - SysExcIntDisable -#endif -#ifdef ROM_SysExcIntEnable -#define MAP_SysExcIntEnable \ - ROM_SysExcIntEnable -#else -#define MAP_SysExcIntEnable \ - SysExcIntEnable -#endif - -//***************************************************************************** -// -// Macros for the SysTick API. -// -//***************************************************************************** -#ifdef ROM_SysTickValueGet -#define MAP_SysTickValueGet \ - ROM_SysTickValueGet -#else -#define MAP_SysTickValueGet \ - SysTickValueGet -#endif -#ifdef ROM_SysTickEnable -#define MAP_SysTickEnable \ - ROM_SysTickEnable -#else -#define MAP_SysTickEnable \ - SysTickEnable -#endif -#ifdef ROM_SysTickDisable -#define MAP_SysTickDisable \ - ROM_SysTickDisable -#else -#define MAP_SysTickDisable \ - SysTickDisable -#endif -#ifdef ROM_SysTickIntEnable -#define MAP_SysTickIntEnable \ - ROM_SysTickIntEnable -#else -#define MAP_SysTickIntEnable \ - SysTickIntEnable -#endif -#ifdef ROM_SysTickIntDisable -#define MAP_SysTickIntDisable \ - ROM_SysTickIntDisable -#else -#define MAP_SysTickIntDisable \ - SysTickIntDisable -#endif -#ifdef ROM_SysTickPeriodSet -#define MAP_SysTickPeriodSet \ - ROM_SysTickPeriodSet -#else -#define MAP_SysTickPeriodSet \ - SysTickPeriodSet -#endif -#ifdef ROM_SysTickPeriodGet -#define MAP_SysTickPeriodGet \ - ROM_SysTickPeriodGet -#else -#define MAP_SysTickPeriodGet \ - SysTickPeriodGet -#endif - -//***************************************************************************** -// -// Macros for the Timer API. -// -//***************************************************************************** -#ifdef ROM_TimerIntClear -#define MAP_TimerIntClear \ - ROM_TimerIntClear -#else -#define MAP_TimerIntClear \ - TimerIntClear -#endif -#ifdef ROM_TimerEnable -#define MAP_TimerEnable \ - ROM_TimerEnable -#else -#define MAP_TimerEnable \ - TimerEnable -#endif -#ifdef ROM_TimerDisable -#define MAP_TimerDisable \ - ROM_TimerDisable -#else -#define MAP_TimerDisable \ - TimerDisable -#endif -#ifdef ROM_TimerConfigure -#define MAP_TimerConfigure \ - ROM_TimerConfigure -#else -#define MAP_TimerConfigure \ - TimerConfigure -#endif -#ifdef ROM_TimerControlLevel -#define MAP_TimerControlLevel \ - ROM_TimerControlLevel -#else -#define MAP_TimerControlLevel \ - TimerControlLevel -#endif -#ifdef ROM_TimerControlTrigger -#define MAP_TimerControlTrigger \ - ROM_TimerControlTrigger -#else -#define MAP_TimerControlTrigger \ - TimerControlTrigger -#endif -#ifdef ROM_TimerControlEvent -#define MAP_TimerControlEvent \ - ROM_TimerControlEvent -#else -#define MAP_TimerControlEvent \ - TimerControlEvent -#endif -#ifdef ROM_TimerControlStall -#define MAP_TimerControlStall \ - ROM_TimerControlStall -#else -#define MAP_TimerControlStall \ - TimerControlStall -#endif -#ifdef ROM_TimerRTCEnable -#define MAP_TimerRTCEnable \ - ROM_TimerRTCEnable -#else -#define MAP_TimerRTCEnable \ - TimerRTCEnable -#endif -#ifdef ROM_TimerRTCDisable -#define MAP_TimerRTCDisable \ - ROM_TimerRTCDisable -#else -#define MAP_TimerRTCDisable \ - TimerRTCDisable -#endif -#ifdef ROM_TimerPrescaleSet -#define MAP_TimerPrescaleSet \ - ROM_TimerPrescaleSet -#else -#define MAP_TimerPrescaleSet \ - TimerPrescaleSet -#endif -#ifdef ROM_TimerPrescaleGet -#define MAP_TimerPrescaleGet \ - ROM_TimerPrescaleGet -#else -#define MAP_TimerPrescaleGet \ - TimerPrescaleGet -#endif -#ifdef ROM_TimerPrescaleMatchSet -#define MAP_TimerPrescaleMatchSet \ - ROM_TimerPrescaleMatchSet -#else -#define MAP_TimerPrescaleMatchSet \ - TimerPrescaleMatchSet -#endif -#ifdef ROM_TimerPrescaleMatchGet -#define MAP_TimerPrescaleMatchGet \ - ROM_TimerPrescaleMatchGet -#else -#define MAP_TimerPrescaleMatchGet \ - TimerPrescaleMatchGet -#endif -#ifdef ROM_TimerLoadSet -#define MAP_TimerLoadSet \ - ROM_TimerLoadSet -#else -#define MAP_TimerLoadSet \ - TimerLoadSet -#endif -#ifdef ROM_TimerLoadGet -#define MAP_TimerLoadGet \ - ROM_TimerLoadGet -#else -#define MAP_TimerLoadGet \ - TimerLoadGet -#endif -#ifdef ROM_TimerValueGet -#define MAP_TimerValueGet \ - ROM_TimerValueGet -#else -#define MAP_TimerValueGet \ - TimerValueGet -#endif -#ifdef ROM_TimerMatchSet -#define MAP_TimerMatchSet \ - ROM_TimerMatchSet -#else -#define MAP_TimerMatchSet \ - TimerMatchSet -#endif -#ifdef ROM_TimerMatchGet -#define MAP_TimerMatchGet \ - ROM_TimerMatchGet -#else -#define MAP_TimerMatchGet \ - TimerMatchGet -#endif -#ifdef ROM_TimerIntEnable -#define MAP_TimerIntEnable \ - ROM_TimerIntEnable -#else -#define MAP_TimerIntEnable \ - TimerIntEnable -#endif -#ifdef ROM_TimerIntDisable -#define MAP_TimerIntDisable \ - ROM_TimerIntDisable -#else -#define MAP_TimerIntDisable \ - TimerIntDisable -#endif -#ifdef ROM_TimerIntStatus -#define MAP_TimerIntStatus \ - ROM_TimerIntStatus -#else -#define MAP_TimerIntStatus \ - TimerIntStatus -#endif -#ifdef ROM_TimerControlWaitOnTrigger -#define MAP_TimerControlWaitOnTrigger \ - ROM_TimerControlWaitOnTrigger -#else -#define MAP_TimerControlWaitOnTrigger \ - TimerControlWaitOnTrigger -#endif -#ifdef ROM_TimerLoadSet64 -#define MAP_TimerLoadSet64 \ - ROM_TimerLoadSet64 -#else -#define MAP_TimerLoadSet64 \ - TimerLoadSet64 -#endif -#ifdef ROM_TimerLoadGet64 -#define MAP_TimerLoadGet64 \ - ROM_TimerLoadGet64 -#else -#define MAP_TimerLoadGet64 \ - TimerLoadGet64 -#endif -#ifdef ROM_TimerValueGet64 -#define MAP_TimerValueGet64 \ - ROM_TimerValueGet64 -#else -#define MAP_TimerValueGet64 \ - TimerValueGet64 -#endif -#ifdef ROM_TimerMatchSet64 -#define MAP_TimerMatchSet64 \ - ROM_TimerMatchSet64 -#else -#define MAP_TimerMatchSet64 \ - TimerMatchSet64 -#endif -#ifdef ROM_TimerMatchGet64 -#define MAP_TimerMatchGet64 \ - ROM_TimerMatchGet64 -#else -#define MAP_TimerMatchGet64 \ - TimerMatchGet64 -#endif -#ifdef ROM_TimerClockSourceGet -#define MAP_TimerClockSourceGet \ - ROM_TimerClockSourceGet -#else -#define MAP_TimerClockSourceGet \ - TimerClockSourceGet -#endif -#ifdef ROM_TimerClockSourceSet -#define MAP_TimerClockSourceSet \ - ROM_TimerClockSourceSet -#else -#define MAP_TimerClockSourceSet \ - TimerClockSourceSet -#endif -#ifdef ROM_TimerADCEventGet -#define MAP_TimerADCEventGet \ - ROM_TimerADCEventGet -#else -#define MAP_TimerADCEventGet \ - TimerADCEventGet -#endif -#ifdef ROM_TimerADCEventSet -#define MAP_TimerADCEventSet \ - ROM_TimerADCEventSet -#else -#define MAP_TimerADCEventSet \ - TimerADCEventSet -#endif -#ifdef ROM_TimerDMAEventGet -#define MAP_TimerDMAEventGet \ - ROM_TimerDMAEventGet -#else -#define MAP_TimerDMAEventGet \ - TimerDMAEventGet -#endif -#ifdef ROM_TimerDMAEventSet -#define MAP_TimerDMAEventSet \ - ROM_TimerDMAEventSet -#else -#define MAP_TimerDMAEventSet \ - TimerDMAEventSet -#endif -#ifdef ROM_TimerSynchronize -#define MAP_TimerSynchronize \ - ROM_TimerSynchronize -#else -#define MAP_TimerSynchronize \ - TimerSynchronize -#endif - -//***************************************************************************** -// -// Macros for the UART API. -// -//***************************************************************************** -#ifdef ROM_UARTCharPut -#define MAP_UARTCharPut \ - ROM_UARTCharPut -#else -#define MAP_UARTCharPut \ - UARTCharPut -#endif -#ifdef ROM_UARTParityModeSet -#define MAP_UARTParityModeSet \ - ROM_UARTParityModeSet -#else -#define MAP_UARTParityModeSet \ - UARTParityModeSet -#endif -#ifdef ROM_UARTParityModeGet -#define MAP_UARTParityModeGet \ - ROM_UARTParityModeGet -#else -#define MAP_UARTParityModeGet \ - UARTParityModeGet -#endif -#ifdef ROM_UARTFIFOLevelSet -#define MAP_UARTFIFOLevelSet \ - ROM_UARTFIFOLevelSet -#else -#define MAP_UARTFIFOLevelSet \ - UARTFIFOLevelSet -#endif -#ifdef ROM_UARTFIFOLevelGet -#define MAP_UARTFIFOLevelGet \ - ROM_UARTFIFOLevelGet -#else -#define MAP_UARTFIFOLevelGet \ - UARTFIFOLevelGet -#endif -#ifdef ROM_UARTConfigSetExpClk -#define MAP_UARTConfigSetExpClk \ - ROM_UARTConfigSetExpClk -#else -#define MAP_UARTConfigSetExpClk \ - UARTConfigSetExpClk -#endif -#ifdef ROM_UARTConfigGetExpClk -#define MAP_UARTConfigGetExpClk \ - ROM_UARTConfigGetExpClk -#else -#define MAP_UARTConfigGetExpClk \ - UARTConfigGetExpClk -#endif -#ifdef ROM_UARTEnable -#define MAP_UARTEnable \ - ROM_UARTEnable -#else -#define MAP_UARTEnable \ - UARTEnable -#endif -#ifdef ROM_UARTDisable -#define MAP_UARTDisable \ - ROM_UARTDisable -#else -#define MAP_UARTDisable \ - UARTDisable -#endif -#ifdef ROM_UARTEnableSIR -#define MAP_UARTEnableSIR \ - ROM_UARTEnableSIR -#else -#define MAP_UARTEnableSIR \ - UARTEnableSIR -#endif -#ifdef ROM_UARTDisableSIR -#define MAP_UARTDisableSIR \ - ROM_UARTDisableSIR -#else -#define MAP_UARTDisableSIR \ - UARTDisableSIR -#endif -#ifdef ROM_UARTCharsAvail -#define MAP_UARTCharsAvail \ - ROM_UARTCharsAvail -#else -#define MAP_UARTCharsAvail \ - UARTCharsAvail -#endif -#ifdef ROM_UARTSpaceAvail -#define MAP_UARTSpaceAvail \ - ROM_UARTSpaceAvail -#else -#define MAP_UARTSpaceAvail \ - UARTSpaceAvail -#endif -#ifdef ROM_UARTCharGetNonBlocking -#define MAP_UARTCharGetNonBlocking \ - ROM_UARTCharGetNonBlocking -#else -#define MAP_UARTCharGetNonBlocking \ - UARTCharGetNonBlocking -#endif -#ifdef ROM_UARTCharGet -#define MAP_UARTCharGet \ - ROM_UARTCharGet -#else -#define MAP_UARTCharGet \ - UARTCharGet -#endif -#ifdef ROM_UARTCharPutNonBlocking -#define MAP_UARTCharPutNonBlocking \ - ROM_UARTCharPutNonBlocking -#else -#define MAP_UARTCharPutNonBlocking \ - UARTCharPutNonBlocking -#endif -#ifdef ROM_UARTBreakCtl -#define MAP_UARTBreakCtl \ - ROM_UARTBreakCtl -#else -#define MAP_UARTBreakCtl \ - UARTBreakCtl -#endif -#ifdef ROM_UARTIntEnable -#define MAP_UARTIntEnable \ - ROM_UARTIntEnable -#else -#define MAP_UARTIntEnable \ - UARTIntEnable -#endif -#ifdef ROM_UARTIntDisable -#define MAP_UARTIntDisable \ - ROM_UARTIntDisable -#else -#define MAP_UARTIntDisable \ - UARTIntDisable -#endif -#ifdef ROM_UARTIntStatus -#define MAP_UARTIntStatus \ - ROM_UARTIntStatus -#else -#define MAP_UARTIntStatus \ - UARTIntStatus -#endif -#ifdef ROM_UARTIntClear -#define MAP_UARTIntClear \ - ROM_UARTIntClear -#else -#define MAP_UARTIntClear \ - UARTIntClear -#endif -#ifdef ROM_UARTDMAEnable -#define MAP_UARTDMAEnable \ - ROM_UARTDMAEnable -#else -#define MAP_UARTDMAEnable \ - UARTDMAEnable -#endif -#ifdef ROM_UARTDMADisable -#define MAP_UARTDMADisable \ - ROM_UARTDMADisable -#else -#define MAP_UARTDMADisable \ - UARTDMADisable -#endif -#ifdef ROM_UARTFIFOEnable -#define MAP_UARTFIFOEnable \ - ROM_UARTFIFOEnable -#else -#define MAP_UARTFIFOEnable \ - UARTFIFOEnable -#endif -#ifdef ROM_UARTFIFODisable -#define MAP_UARTFIFODisable \ - ROM_UARTFIFODisable -#else -#define MAP_UARTFIFODisable \ - UARTFIFODisable -#endif -#ifdef ROM_UARTBusy -#define MAP_UARTBusy \ - ROM_UARTBusy -#else -#define MAP_UARTBusy \ - UARTBusy -#endif -#ifdef ROM_UARTTxIntModeSet -#define MAP_UARTTxIntModeSet \ - ROM_UARTTxIntModeSet -#else -#define MAP_UARTTxIntModeSet \ - UARTTxIntModeSet -#endif -#ifdef ROM_UARTTxIntModeGet -#define MAP_UARTTxIntModeGet \ - ROM_UARTTxIntModeGet -#else -#define MAP_UARTTxIntModeGet \ - UARTTxIntModeGet -#endif -#ifdef ROM_UARTRxErrorGet -#define MAP_UARTRxErrorGet \ - ROM_UARTRxErrorGet -#else -#define MAP_UARTRxErrorGet \ - UARTRxErrorGet -#endif -#ifdef ROM_UARTRxErrorClear -#define MAP_UARTRxErrorClear \ - ROM_UARTRxErrorClear -#else -#define MAP_UARTRxErrorClear \ - UARTRxErrorClear -#endif -#ifdef ROM_UARTClockSourceSet -#define MAP_UARTClockSourceSet \ - ROM_UARTClockSourceSet -#else -#define MAP_UARTClockSourceSet \ - UARTClockSourceSet -#endif -#ifdef ROM_UARTClockSourceGet -#define MAP_UARTClockSourceGet \ - ROM_UARTClockSourceGet -#else -#define MAP_UARTClockSourceGet \ - UARTClockSourceGet -#endif -#ifdef ROM_UART9BitEnable -#define MAP_UART9BitEnable \ - ROM_UART9BitEnable -#else -#define MAP_UART9BitEnable \ - UART9BitEnable -#endif -#ifdef ROM_UART9BitDisable -#define MAP_UART9BitDisable \ - ROM_UART9BitDisable -#else -#define MAP_UART9BitDisable \ - UART9BitDisable -#endif -#ifdef ROM_UART9BitAddrSet -#define MAP_UART9BitAddrSet \ - ROM_UART9BitAddrSet -#else -#define MAP_UART9BitAddrSet \ - UART9BitAddrSet -#endif -#ifdef ROM_UART9BitAddrSend -#define MAP_UART9BitAddrSend \ - ROM_UART9BitAddrSend -#else -#define MAP_UART9BitAddrSend \ - UART9BitAddrSend -#endif -#ifdef ROM_UARTSmartCardDisable -#define MAP_UARTSmartCardDisable \ - ROM_UARTSmartCardDisable -#else -#define MAP_UARTSmartCardDisable \ - UARTSmartCardDisable -#endif -#ifdef ROM_UARTSmartCardEnable -#define MAP_UARTSmartCardEnable \ - ROM_UARTSmartCardEnable -#else -#define MAP_UARTSmartCardEnable \ - UARTSmartCardEnable -#endif -#ifdef ROM_UARTModemControlClear -#define MAP_UARTModemControlClear \ - ROM_UARTModemControlClear -#else -#define MAP_UARTModemControlClear \ - UARTModemControlClear -#endif -#ifdef ROM_UARTModemControlGet -#define MAP_UARTModemControlGet \ - ROM_UARTModemControlGet -#else -#define MAP_UARTModemControlGet \ - UARTModemControlGet -#endif -#ifdef ROM_UARTModemControlSet -#define MAP_UARTModemControlSet \ - ROM_UARTModemControlSet -#else -#define MAP_UARTModemControlSet \ - UARTModemControlSet -#endif -#ifdef ROM_UARTModemStatusGet -#define MAP_UARTModemStatusGet \ - ROM_UARTModemStatusGet -#else -#define MAP_UARTModemStatusGet \ - UARTModemStatusGet -#endif -#ifdef ROM_UARTFlowControlGet -#define MAP_UARTFlowControlGet \ - ROM_UARTFlowControlGet -#else -#define MAP_UARTFlowControlGet \ - UARTFlowControlGet -#endif -#ifdef ROM_UARTFlowControlSet -#define MAP_UARTFlowControlSet \ - ROM_UARTFlowControlSet -#else -#define MAP_UARTFlowControlSet \ - UARTFlowControlSet -#endif - -//***************************************************************************** -// -// Macros for the uDMA API. -// -//***************************************************************************** -#ifdef ROM_uDMAChannelTransferSet -#define MAP_uDMAChannelTransferSet \ - ROM_uDMAChannelTransferSet -#else -#define MAP_uDMAChannelTransferSet \ - uDMAChannelTransferSet -#endif -#ifdef ROM_uDMAEnable -#define MAP_uDMAEnable \ - ROM_uDMAEnable -#else -#define MAP_uDMAEnable \ - uDMAEnable -#endif -#ifdef ROM_uDMADisable -#define MAP_uDMADisable \ - ROM_uDMADisable -#else -#define MAP_uDMADisable \ - uDMADisable -#endif -#ifdef ROM_uDMAErrorStatusGet -#define MAP_uDMAErrorStatusGet \ - ROM_uDMAErrorStatusGet -#else -#define MAP_uDMAErrorStatusGet \ - uDMAErrorStatusGet -#endif -#ifdef ROM_uDMAErrorStatusClear -#define MAP_uDMAErrorStatusClear \ - ROM_uDMAErrorStatusClear -#else -#define MAP_uDMAErrorStatusClear \ - uDMAErrorStatusClear -#endif -#ifdef ROM_uDMAChannelEnable -#define MAP_uDMAChannelEnable \ - ROM_uDMAChannelEnable -#else -#define MAP_uDMAChannelEnable \ - uDMAChannelEnable -#endif -#ifdef ROM_uDMAChannelDisable -#define MAP_uDMAChannelDisable \ - ROM_uDMAChannelDisable -#else -#define MAP_uDMAChannelDisable \ - uDMAChannelDisable -#endif -#ifdef ROM_uDMAChannelIsEnabled -#define MAP_uDMAChannelIsEnabled \ - ROM_uDMAChannelIsEnabled -#else -#define MAP_uDMAChannelIsEnabled \ - uDMAChannelIsEnabled -#endif -#ifdef ROM_uDMAControlBaseSet -#define MAP_uDMAControlBaseSet \ - ROM_uDMAControlBaseSet -#else -#define MAP_uDMAControlBaseSet \ - uDMAControlBaseSet -#endif -#ifdef ROM_uDMAControlBaseGet -#define MAP_uDMAControlBaseGet \ - ROM_uDMAControlBaseGet -#else -#define MAP_uDMAControlBaseGet \ - uDMAControlBaseGet -#endif -#ifdef ROM_uDMAChannelRequest -#define MAP_uDMAChannelRequest \ - ROM_uDMAChannelRequest -#else -#define MAP_uDMAChannelRequest \ - uDMAChannelRequest -#endif -#ifdef ROM_uDMAChannelAttributeEnable -#define MAP_uDMAChannelAttributeEnable \ - ROM_uDMAChannelAttributeEnable -#else -#define MAP_uDMAChannelAttributeEnable \ - uDMAChannelAttributeEnable -#endif -#ifdef ROM_uDMAChannelAttributeDisable -#define MAP_uDMAChannelAttributeDisable \ - ROM_uDMAChannelAttributeDisable -#else -#define MAP_uDMAChannelAttributeDisable \ - uDMAChannelAttributeDisable -#endif -#ifdef ROM_uDMAChannelAttributeGet -#define MAP_uDMAChannelAttributeGet \ - ROM_uDMAChannelAttributeGet -#else -#define MAP_uDMAChannelAttributeGet \ - uDMAChannelAttributeGet -#endif -#ifdef ROM_uDMAChannelControlSet -#define MAP_uDMAChannelControlSet \ - ROM_uDMAChannelControlSet -#else -#define MAP_uDMAChannelControlSet \ - uDMAChannelControlSet -#endif -#ifdef ROM_uDMAChannelSizeGet -#define MAP_uDMAChannelSizeGet \ - ROM_uDMAChannelSizeGet -#else -#define MAP_uDMAChannelSizeGet \ - uDMAChannelSizeGet -#endif -#ifdef ROM_uDMAChannelModeGet -#define MAP_uDMAChannelModeGet \ - ROM_uDMAChannelModeGet -#else -#define MAP_uDMAChannelModeGet \ - uDMAChannelModeGet -#endif -#ifdef ROM_uDMAChannelSelectSecondary -#define MAP_uDMAChannelSelectSecondary \ - ROM_uDMAChannelSelectSecondary -#else -#define MAP_uDMAChannelSelectSecondary \ - uDMAChannelSelectSecondary -#endif -#ifdef ROM_uDMAChannelSelectDefault -#define MAP_uDMAChannelSelectDefault \ - ROM_uDMAChannelSelectDefault -#else -#define MAP_uDMAChannelSelectDefault \ - uDMAChannelSelectDefault -#endif -#ifdef ROM_uDMAIntStatus -#define MAP_uDMAIntStatus \ - ROM_uDMAIntStatus -#else -#define MAP_uDMAIntStatus \ - uDMAIntStatus -#endif -#ifdef ROM_uDMAIntClear -#define MAP_uDMAIntClear \ - ROM_uDMAIntClear -#else -#define MAP_uDMAIntClear \ - uDMAIntClear -#endif -#ifdef ROM_uDMAControlAlternateBaseGet -#define MAP_uDMAControlAlternateBaseGet \ - ROM_uDMAControlAlternateBaseGet -#else -#define MAP_uDMAControlAlternateBaseGet \ - uDMAControlAlternateBaseGet -#endif -#ifdef ROM_uDMAChannelScatterGatherSet -#define MAP_uDMAChannelScatterGatherSet \ - ROM_uDMAChannelScatterGatherSet -#else -#define MAP_uDMAChannelScatterGatherSet \ - uDMAChannelScatterGatherSet -#endif -#ifdef ROM_uDMAChannelAssign -#define MAP_uDMAChannelAssign \ - ROM_uDMAChannelAssign -#else -#define MAP_uDMAChannelAssign \ - uDMAChannelAssign -#endif - -//***************************************************************************** -// -// Macros for the USB API. -// -//***************************************************************************** -#ifdef ROM_USBDevAddrGet -#define MAP_USBDevAddrGet \ - ROM_USBDevAddrGet -#else -#define MAP_USBDevAddrGet \ - USBDevAddrGet -#endif -#ifdef ROM_USBDevAddrSet -#define MAP_USBDevAddrSet \ - ROM_USBDevAddrSet -#else -#define MAP_USBDevAddrSet \ - USBDevAddrSet -#endif -#ifdef ROM_USBDevConnect -#define MAP_USBDevConnect \ - ROM_USBDevConnect -#else -#define MAP_USBDevConnect \ - USBDevConnect -#endif -#ifdef ROM_USBDevDisconnect -#define MAP_USBDevDisconnect \ - ROM_USBDevDisconnect -#else -#define MAP_USBDevDisconnect \ - USBDevDisconnect -#endif -#ifdef ROM_USBDevEndpointConfigSet -#define MAP_USBDevEndpointConfigSet \ - ROM_USBDevEndpointConfigSet -#else -#define MAP_USBDevEndpointConfigSet \ - USBDevEndpointConfigSet -#endif -#ifdef ROM_USBDevEndpointDataAck -#define MAP_USBDevEndpointDataAck \ - ROM_USBDevEndpointDataAck -#else -#define MAP_USBDevEndpointDataAck \ - USBDevEndpointDataAck -#endif -#ifdef ROM_USBDevEndpointStall -#define MAP_USBDevEndpointStall \ - ROM_USBDevEndpointStall -#else -#define MAP_USBDevEndpointStall \ - USBDevEndpointStall -#endif -#ifdef ROM_USBDevEndpointStallClear -#define MAP_USBDevEndpointStallClear \ - ROM_USBDevEndpointStallClear -#else -#define MAP_USBDevEndpointStallClear \ - USBDevEndpointStallClear -#endif -#ifdef ROM_USBDevEndpointStatusClear -#define MAP_USBDevEndpointStatusClear \ - ROM_USBDevEndpointStatusClear -#else -#define MAP_USBDevEndpointStatusClear \ - USBDevEndpointStatusClear -#endif -#ifdef ROM_USBEndpointDataGet -#define MAP_USBEndpointDataGet \ - ROM_USBEndpointDataGet -#else -#define MAP_USBEndpointDataGet \ - USBEndpointDataGet -#endif -#ifdef ROM_USBEndpointDataPut -#define MAP_USBEndpointDataPut \ - ROM_USBEndpointDataPut -#else -#define MAP_USBEndpointDataPut \ - USBEndpointDataPut -#endif -#ifdef ROM_USBEndpointDataSend -#define MAP_USBEndpointDataSend \ - ROM_USBEndpointDataSend -#else -#define MAP_USBEndpointDataSend \ - USBEndpointDataSend -#endif -#ifdef ROM_USBEndpointDataToggleClear -#define MAP_USBEndpointDataToggleClear \ - ROM_USBEndpointDataToggleClear -#else -#define MAP_USBEndpointDataToggleClear \ - USBEndpointDataToggleClear -#endif -#ifdef ROM_USBEndpointStatus -#define MAP_USBEndpointStatus \ - ROM_USBEndpointStatus -#else -#define MAP_USBEndpointStatus \ - USBEndpointStatus -#endif -#ifdef ROM_USBFIFOAddrGet -#define MAP_USBFIFOAddrGet \ - ROM_USBFIFOAddrGet -#else -#define MAP_USBFIFOAddrGet \ - USBFIFOAddrGet -#endif -#ifdef ROM_USBFIFOConfigGet -#define MAP_USBFIFOConfigGet \ - ROM_USBFIFOConfigGet -#else -#define MAP_USBFIFOConfigGet \ - USBFIFOConfigGet -#endif -#ifdef ROM_USBFIFOConfigSet -#define MAP_USBFIFOConfigSet \ - ROM_USBFIFOConfigSet -#else -#define MAP_USBFIFOConfigSet \ - USBFIFOConfigSet -#endif -#ifdef ROM_USBFIFOFlush -#define MAP_USBFIFOFlush \ - ROM_USBFIFOFlush -#else -#define MAP_USBFIFOFlush \ - USBFIFOFlush -#endif -#ifdef ROM_USBFrameNumberGet -#define MAP_USBFrameNumberGet \ - ROM_USBFrameNumberGet -#else -#define MAP_USBFrameNumberGet \ - USBFrameNumberGet -#endif -#ifdef ROM_USBHostAddrGet -#define MAP_USBHostAddrGet \ - ROM_USBHostAddrGet -#else -#define MAP_USBHostAddrGet \ - USBHostAddrGet -#endif -#ifdef ROM_USBHostAddrSet -#define MAP_USBHostAddrSet \ - ROM_USBHostAddrSet -#else -#define MAP_USBHostAddrSet \ - USBHostAddrSet -#endif -#ifdef ROM_USBHostEndpointConfig -#define MAP_USBHostEndpointConfig \ - ROM_USBHostEndpointConfig -#else -#define MAP_USBHostEndpointConfig \ - USBHostEndpointConfig -#endif -#ifdef ROM_USBHostEndpointDataAck -#define MAP_USBHostEndpointDataAck \ - ROM_USBHostEndpointDataAck -#else -#define MAP_USBHostEndpointDataAck \ - USBHostEndpointDataAck -#endif -#ifdef ROM_USBHostEndpointDataToggle -#define MAP_USBHostEndpointDataToggle \ - ROM_USBHostEndpointDataToggle -#else -#define MAP_USBHostEndpointDataToggle \ - USBHostEndpointDataToggle -#endif -#ifdef ROM_USBHostEndpointStatusClear -#define MAP_USBHostEndpointStatusClear \ - ROM_USBHostEndpointStatusClear -#else -#define MAP_USBHostEndpointStatusClear \ - USBHostEndpointStatusClear -#endif -#ifdef ROM_USBHostHubAddrGet -#define MAP_USBHostHubAddrGet \ - ROM_USBHostHubAddrGet -#else -#define MAP_USBHostHubAddrGet \ - USBHostHubAddrGet -#endif -#ifdef ROM_USBHostHubAddrSet -#define MAP_USBHostHubAddrSet \ - ROM_USBHostHubAddrSet -#else -#define MAP_USBHostHubAddrSet \ - USBHostHubAddrSet -#endif -#ifdef ROM_USBHostPwrDisable -#define MAP_USBHostPwrDisable \ - ROM_USBHostPwrDisable -#else -#define MAP_USBHostPwrDisable \ - USBHostPwrDisable -#endif -#ifdef ROM_USBHostPwrEnable -#define MAP_USBHostPwrEnable \ - ROM_USBHostPwrEnable -#else -#define MAP_USBHostPwrEnable \ - USBHostPwrEnable -#endif -#ifdef ROM_USBHostPwrConfig -#define MAP_USBHostPwrConfig \ - ROM_USBHostPwrConfig -#else -#define MAP_USBHostPwrConfig \ - USBHostPwrConfig -#endif -#ifdef ROM_USBHostPwrFaultDisable -#define MAP_USBHostPwrFaultDisable \ - ROM_USBHostPwrFaultDisable -#else -#define MAP_USBHostPwrFaultDisable \ - USBHostPwrFaultDisable -#endif -#ifdef ROM_USBHostPwrFaultEnable -#define MAP_USBHostPwrFaultEnable \ - ROM_USBHostPwrFaultEnable -#else -#define MAP_USBHostPwrFaultEnable \ - USBHostPwrFaultEnable -#endif -#ifdef ROM_USBHostRequestIN -#define MAP_USBHostRequestIN \ - ROM_USBHostRequestIN -#else -#define MAP_USBHostRequestIN \ - USBHostRequestIN -#endif -#ifdef ROM_USBHostRequestStatus -#define MAP_USBHostRequestStatus \ - ROM_USBHostRequestStatus -#else -#define MAP_USBHostRequestStatus \ - USBHostRequestStatus -#endif -#ifdef ROM_USBHostReset -#define MAP_USBHostReset \ - ROM_USBHostReset -#else -#define MAP_USBHostReset \ - USBHostReset -#endif -#ifdef ROM_USBHostResume -#define MAP_USBHostResume \ - ROM_USBHostResume -#else -#define MAP_USBHostResume \ - USBHostResume -#endif -#ifdef ROM_USBHostSpeedGet -#define MAP_USBHostSpeedGet \ - ROM_USBHostSpeedGet -#else -#define MAP_USBHostSpeedGet \ - USBHostSpeedGet -#endif -#ifdef ROM_USBHostSuspend -#define MAP_USBHostSuspend \ - ROM_USBHostSuspend -#else -#define MAP_USBHostSuspend \ - USBHostSuspend -#endif -#ifdef ROM_USBDevEndpointConfigGet -#define MAP_USBDevEndpointConfigGet \ - ROM_USBDevEndpointConfigGet -#else -#define MAP_USBDevEndpointConfigGet \ - USBDevEndpointConfigGet -#endif -#ifdef ROM_USBEndpointDMAEnable -#define MAP_USBEndpointDMAEnable \ - ROM_USBEndpointDMAEnable -#else -#define MAP_USBEndpointDMAEnable \ - USBEndpointDMAEnable -#endif -#ifdef ROM_USBEndpointDMADisable -#define MAP_USBEndpointDMADisable \ - ROM_USBEndpointDMADisable -#else -#define MAP_USBEndpointDMADisable \ - USBEndpointDMADisable -#endif -#ifdef ROM_USBEndpointDataAvail -#define MAP_USBEndpointDataAvail \ - ROM_USBEndpointDataAvail -#else -#define MAP_USBEndpointDataAvail \ - USBEndpointDataAvail -#endif -#ifdef ROM_USBModeGet -#define MAP_USBModeGet \ - ROM_USBModeGet -#else -#define MAP_USBModeGet \ - USBModeGet -#endif -#ifdef ROM_USBEndpointDMAChannel -#define MAP_USBEndpointDMAChannel \ - ROM_USBEndpointDMAChannel -#else -#define MAP_USBEndpointDMAChannel \ - USBEndpointDMAChannel -#endif -#ifdef ROM_USBIntDisableControl -#define MAP_USBIntDisableControl \ - ROM_USBIntDisableControl -#else -#define MAP_USBIntDisableControl \ - USBIntDisableControl -#endif -#ifdef ROM_USBIntEnableControl -#define MAP_USBIntEnableControl \ - ROM_USBIntEnableControl -#else -#define MAP_USBIntEnableControl \ - USBIntEnableControl -#endif -#ifdef ROM_USBIntStatusControl -#define MAP_USBIntStatusControl \ - ROM_USBIntStatusControl -#else -#define MAP_USBIntStatusControl \ - USBIntStatusControl -#endif -#ifdef ROM_USBIntDisableEndpoint -#define MAP_USBIntDisableEndpoint \ - ROM_USBIntDisableEndpoint -#else -#define MAP_USBIntDisableEndpoint \ - USBIntDisableEndpoint -#endif -#ifdef ROM_USBIntEnableEndpoint -#define MAP_USBIntEnableEndpoint \ - ROM_USBIntEnableEndpoint -#else -#define MAP_USBIntEnableEndpoint \ - USBIntEnableEndpoint -#endif -#ifdef ROM_USBIntStatusEndpoint -#define MAP_USBIntStatusEndpoint \ - ROM_USBIntStatusEndpoint -#else -#define MAP_USBIntStatusEndpoint \ - USBIntStatusEndpoint -#endif -#ifdef ROM_USBHostMode -#define MAP_USBHostMode \ - ROM_USBHostMode -#else -#define MAP_USBHostMode \ - USBHostMode -#endif -#ifdef ROM_USBDevMode -#define MAP_USBDevMode \ - ROM_USBDevMode -#else -#define MAP_USBDevMode \ - USBDevMode -#endif -#ifdef ROM_USBPHYPowerOff -#define MAP_USBPHYPowerOff \ - ROM_USBPHYPowerOff -#else -#define MAP_USBPHYPowerOff \ - USBPHYPowerOff -#endif -#ifdef ROM_USBPHYPowerOn -#define MAP_USBPHYPowerOn \ - ROM_USBPHYPowerOn -#else -#define MAP_USBPHYPowerOn \ - USBPHYPowerOn -#endif -#ifdef ROM_USBOTGMode -#define MAP_USBOTGMode \ - ROM_USBOTGMode -#else -#define MAP_USBOTGMode \ - USBOTGMode -#endif -#ifdef ROM_USBHostRequestINClear -#define MAP_USBHostRequestINClear \ - ROM_USBHostRequestINClear -#else -#define MAP_USBHostRequestINClear \ - USBHostRequestINClear -#endif -#ifdef ROM_USBNumEndpointsGet -#define MAP_USBNumEndpointsGet \ - ROM_USBNumEndpointsGet -#else -#define MAP_USBNumEndpointsGet \ - USBNumEndpointsGet -#endif -#ifdef ROM_USBClockDisable -#define MAP_USBClockDisable \ - ROM_USBClockDisable -#else -#define MAP_USBClockDisable \ - USBClockDisable -#endif -#ifdef ROM_USBClockEnable -#define MAP_USBClockEnable \ - ROM_USBClockEnable -#else -#define MAP_USBClockEnable \ - USBClockEnable -#endif -#ifdef ROM_USBControllerVersion -#define MAP_USBControllerVersion \ - ROM_USBControllerVersion -#else -#define MAP_USBControllerVersion \ - USBControllerVersion -#endif -#ifdef ROM_USBDevLPMConfig -#define MAP_USBDevLPMConfig \ - ROM_USBDevLPMConfig -#else -#define MAP_USBDevLPMConfig \ - USBDevLPMConfig -#endif -#ifdef ROM_USBDevLPMDisable -#define MAP_USBDevLPMDisable \ - ROM_USBDevLPMDisable -#else -#define MAP_USBDevLPMDisable \ - USBDevLPMDisable -#endif -#ifdef ROM_USBDevLPMEnable -#define MAP_USBDevLPMEnable \ - ROM_USBDevLPMEnable -#else -#define MAP_USBDevLPMEnable \ - USBDevLPMEnable -#endif -#ifdef ROM_USBDevLPMRemoteWake -#define MAP_USBDevLPMRemoteWake \ - ROM_USBDevLPMRemoteWake -#else -#define MAP_USBDevLPMRemoteWake \ - USBDevLPMRemoteWake -#endif -#ifdef ROM_USBDevSpeedGet -#define MAP_USBDevSpeedGet \ - ROM_USBDevSpeedGet -#else -#define MAP_USBDevSpeedGet \ - USBDevSpeedGet -#endif -#ifdef ROM_USBDMAChannelAddressGet -#define MAP_USBDMAChannelAddressGet \ - ROM_USBDMAChannelAddressGet -#else -#define MAP_USBDMAChannelAddressGet \ - USBDMAChannelAddressGet -#endif -#ifdef ROM_USBDMAChannelAddressSet -#define MAP_USBDMAChannelAddressSet \ - ROM_USBDMAChannelAddressSet -#else -#define MAP_USBDMAChannelAddressSet \ - USBDMAChannelAddressSet -#endif -#ifdef ROM_USBDMAChannelConfigSet -#define MAP_USBDMAChannelConfigSet \ - ROM_USBDMAChannelConfigSet -#else -#define MAP_USBDMAChannelConfigSet \ - USBDMAChannelConfigSet -#endif -#ifdef ROM_USBDMAChannelDisable -#define MAP_USBDMAChannelDisable \ - ROM_USBDMAChannelDisable -#else -#define MAP_USBDMAChannelDisable \ - USBDMAChannelDisable -#endif -#ifdef ROM_USBDMAChannelEnable -#define MAP_USBDMAChannelEnable \ - ROM_USBDMAChannelEnable -#else -#define MAP_USBDMAChannelEnable \ - USBDMAChannelEnable -#endif -#ifdef ROM_USBDMAChannelIntDisable -#define MAP_USBDMAChannelIntDisable \ - ROM_USBDMAChannelIntDisable -#else -#define MAP_USBDMAChannelIntDisable \ - USBDMAChannelIntDisable -#endif -#ifdef ROM_USBDMAChannelIntEnable -#define MAP_USBDMAChannelIntEnable \ - ROM_USBDMAChannelIntEnable -#else -#define MAP_USBDMAChannelIntEnable \ - USBDMAChannelIntEnable -#endif -#ifdef ROM_USBDMAChannelCountGet -#define MAP_USBDMAChannelCountGet \ - ROM_USBDMAChannelCountGet -#else -#define MAP_USBDMAChannelCountGet \ - USBDMAChannelCountGet -#endif -#ifdef ROM_USBDMAChannelCountSet -#define MAP_USBDMAChannelCountSet \ - ROM_USBDMAChannelCountSet -#else -#define MAP_USBDMAChannelCountSet \ - USBDMAChannelCountSet -#endif -#ifdef ROM_USBDMAChannelIntStatus -#define MAP_USBDMAChannelIntStatus \ - ROM_USBDMAChannelIntStatus -#else -#define MAP_USBDMAChannelIntStatus \ - USBDMAChannelIntStatus -#endif -#ifdef ROM_USBDMAChannelStatus -#define MAP_USBDMAChannelStatus \ - ROM_USBDMAChannelStatus -#else -#define MAP_USBDMAChannelStatus \ - USBDMAChannelStatus -#endif -#ifdef ROM_USBDMAChannelStatusClear -#define MAP_USBDMAChannelStatusClear \ - ROM_USBDMAChannelStatusClear -#else -#define MAP_USBDMAChannelStatusClear \ - USBDMAChannelStatusClear -#endif -#ifdef ROM_USBHighSpeed -#define MAP_USBHighSpeed \ - ROM_USBHighSpeed -#else -#define MAP_USBHighSpeed \ - USBHighSpeed -#endif -#ifdef ROM_USBHostEndpointPing -#define MAP_USBHostEndpointPing \ - ROM_USBHostEndpointPing -#else -#define MAP_USBHostEndpointPing \ - USBHostEndpointPing -#endif -#ifdef ROM_USBHostEndpointSpeed -#define MAP_USBHostEndpointSpeed \ - ROM_USBHostEndpointSpeed -#else -#define MAP_USBHostEndpointSpeed \ - USBHostEndpointSpeed -#endif -#ifdef ROM_USBHostLPMConfig -#define MAP_USBHostLPMConfig \ - ROM_USBHostLPMConfig -#else -#define MAP_USBHostLPMConfig \ - USBHostLPMConfig -#endif -#ifdef ROM_USBHostLPMResume -#define MAP_USBHostLPMResume \ - ROM_USBHostLPMResume -#else -#define MAP_USBHostLPMResume \ - USBHostLPMResume -#endif -#ifdef ROM_USBHostLPMSend -#define MAP_USBHostLPMSend \ - ROM_USBHostLPMSend -#else -#define MAP_USBHostLPMSend \ - USBHostLPMSend -#endif -#ifdef ROM_USBLPMIntDisable -#define MAP_USBLPMIntDisable \ - ROM_USBLPMIntDisable -#else -#define MAP_USBLPMIntDisable \ - USBLPMIntDisable -#endif -#ifdef ROM_USBLPMIntEnable -#define MAP_USBLPMIntEnable \ - ROM_USBLPMIntEnable -#else -#define MAP_USBLPMIntEnable \ - USBLPMIntEnable -#endif -#ifdef ROM_USBLPMIntStatus -#define MAP_USBLPMIntStatus \ - ROM_USBLPMIntStatus -#else -#define MAP_USBLPMIntStatus \ - USBLPMIntStatus -#endif -#ifdef ROM_USBLPMLinkStateGet -#define MAP_USBLPMLinkStateGet \ - ROM_USBLPMLinkStateGet -#else -#define MAP_USBLPMLinkStateGet \ - USBLPMLinkStateGet -#endif -#ifdef ROM_USBEndpointPacketCountSet -#define MAP_USBEndpointPacketCountSet \ - ROM_USBEndpointPacketCountSet -#else -#define MAP_USBEndpointPacketCountSet \ - USBEndpointPacketCountSet -#endif -#ifdef ROM_USBULPIConfig -#define MAP_USBULPIConfig \ - ROM_USBULPIConfig -#else -#define MAP_USBULPIConfig \ - USBULPIConfig -#endif -#ifdef ROM_USBULPIDisable -#define MAP_USBULPIDisable \ - ROM_USBULPIDisable -#else -#define MAP_USBULPIDisable \ - USBULPIDisable -#endif -#ifdef ROM_USBULPIEnable -#define MAP_USBULPIEnable \ - ROM_USBULPIEnable -#else -#define MAP_USBULPIEnable \ - USBULPIEnable -#endif -#ifdef ROM_USBULPIRegRead -#define MAP_USBULPIRegRead \ - ROM_USBULPIRegRead -#else -#define MAP_USBULPIRegRead \ - USBULPIRegRead -#endif -#ifdef ROM_USBULPIRegWrite -#define MAP_USBULPIRegWrite \ - ROM_USBULPIRegWrite -#else -#define MAP_USBULPIRegWrite \ - USBULPIRegWrite -#endif -#ifdef ROM_USBOTGSessionRequest -#define MAP_USBOTGSessionRequest \ - ROM_USBOTGSessionRequest -#else -#define MAP_USBOTGSessionRequest \ - USBOTGSessionRequest -#endif -#ifdef ROM_USBDMANumChannels -#define MAP_USBDMANumChannels \ - ROM_USBDMANumChannels -#else -#define MAP_USBDMANumChannels \ - USBDMANumChannels -#endif -#ifdef ROM_USBEndpointDMAConfigSet -#define MAP_USBEndpointDMAConfigSet \ - ROM_USBEndpointDMAConfigSet -#else -#define MAP_USBEndpointDMAConfigSet \ - USBEndpointDMAConfigSet -#endif -#ifdef ROM_USBLPMRemoteWakeEnabled -#define MAP_USBLPMRemoteWakeEnabled \ - ROM_USBLPMRemoteWakeEnabled -#else -#define MAP_USBLPMRemoteWakeEnabled \ - USBLPMRemoteWakeEnabled -#endif -#ifdef ROM_USBModeConfig -#define MAP_USBModeConfig \ - ROM_USBModeConfig -#else -#define MAP_USBModeConfig \ - USBModeConfig -#endif - -//***************************************************************************** -// -// Macros for the Watchdog API. -// -//***************************************************************************** -#ifdef ROM_WatchdogIntClear -#define MAP_WatchdogIntClear \ - ROM_WatchdogIntClear -#else -#define MAP_WatchdogIntClear \ - WatchdogIntClear -#endif -#ifdef ROM_WatchdogRunning -#define MAP_WatchdogRunning \ - ROM_WatchdogRunning -#else -#define MAP_WatchdogRunning \ - WatchdogRunning -#endif -#ifdef ROM_WatchdogEnable -#define MAP_WatchdogEnable \ - ROM_WatchdogEnable -#else -#define MAP_WatchdogEnable \ - WatchdogEnable -#endif -#ifdef ROM_WatchdogResetEnable -#define MAP_WatchdogResetEnable \ - ROM_WatchdogResetEnable -#else -#define MAP_WatchdogResetEnable \ - WatchdogResetEnable -#endif -#ifdef ROM_WatchdogResetDisable -#define MAP_WatchdogResetDisable \ - ROM_WatchdogResetDisable -#else -#define MAP_WatchdogResetDisable \ - WatchdogResetDisable -#endif -#ifdef ROM_WatchdogLock -#define MAP_WatchdogLock \ - ROM_WatchdogLock -#else -#define MAP_WatchdogLock \ - WatchdogLock -#endif -#ifdef ROM_WatchdogUnlock -#define MAP_WatchdogUnlock \ - ROM_WatchdogUnlock -#else -#define MAP_WatchdogUnlock \ - WatchdogUnlock -#endif -#ifdef ROM_WatchdogLockState -#define MAP_WatchdogLockState \ - ROM_WatchdogLockState -#else -#define MAP_WatchdogLockState \ - WatchdogLockState -#endif -#ifdef ROM_WatchdogReloadSet -#define MAP_WatchdogReloadSet \ - ROM_WatchdogReloadSet -#else -#define MAP_WatchdogReloadSet \ - WatchdogReloadSet -#endif -#ifdef ROM_WatchdogReloadGet -#define MAP_WatchdogReloadGet \ - ROM_WatchdogReloadGet -#else -#define MAP_WatchdogReloadGet \ - WatchdogReloadGet -#endif -#ifdef ROM_WatchdogValueGet -#define MAP_WatchdogValueGet \ - ROM_WatchdogValueGet -#else -#define MAP_WatchdogValueGet \ - WatchdogValueGet -#endif -#ifdef ROM_WatchdogIntEnable -#define MAP_WatchdogIntEnable \ - ROM_WatchdogIntEnable -#else -#define MAP_WatchdogIntEnable \ - WatchdogIntEnable -#endif -#ifdef ROM_WatchdogIntStatus -#define MAP_WatchdogIntStatus \ - ROM_WatchdogIntStatus -#else -#define MAP_WatchdogIntStatus \ - WatchdogIntStatus -#endif -#ifdef ROM_WatchdogStallEnable -#define MAP_WatchdogStallEnable \ - ROM_WatchdogStallEnable -#else -#define MAP_WatchdogStallEnable \ - WatchdogStallEnable -#endif -#ifdef ROM_WatchdogStallDisable -#define MAP_WatchdogStallDisable \ - ROM_WatchdogStallDisable -#else -#define MAP_WatchdogStallDisable \ - WatchdogStallDisable -#endif -#ifdef ROM_WatchdogIntTypeSet -#define MAP_WatchdogIntTypeSet \ - ROM_WatchdogIntTypeSet -#else -#define MAP_WatchdogIntTypeSet \ - WatchdogIntTypeSet -#endif - -//***************************************************************************** -// -// Macros for the Software API. -// -//***************************************************************************** -#ifdef ROM_Crc16Array -#define MAP_Crc16Array \ - ROM_Crc16Array -#else -#define MAP_Crc16Array \ - Crc16Array -#endif -#ifdef ROM_Crc16Array3 -#define MAP_Crc16Array3 \ - ROM_Crc16Array3 -#else -#define MAP_Crc16Array3 \ - Crc16Array3 -#endif -#ifdef ROM_Crc16 -#define MAP_Crc16 \ - ROM_Crc16 -#else -#define MAP_Crc16 \ - Crc16 -#endif -#ifdef ROM_Crc8CCITT -#define MAP_Crc8CCITT \ - ROM_Crc8CCITT -#else -#define MAP_Crc8CCITT \ - Crc8CCITT -#endif -#ifdef ROM_Crc32 -#define MAP_Crc32 \ - ROM_Crc32 -#else -#define MAP_Crc32 \ - Crc32 -#endif - -#endif // __DRIVERLIB_ROM_MAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.c b/bsp/tm4c129x-dk/libraries/driverlib/shamd5.c deleted file mode 100644 index d748ac4bb5..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.c +++ /dev/null @@ -1,1092 +0,0 @@ -//***************************************************************************** -// -// shamd5.c - Driver for the SHA/MD5 module. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_shamd5.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/shamd5.h" - -//***************************************************************************** -// -//! \addtogroup shamd5_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Resets the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function performs a soft-reset of the SHA/MD5 module using the -//! SYSCONFIG register. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5Reset(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Set the soft-reset bit. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_SOFTRESET; - - // - // Wait for the reset to complete. - // - while((HWREG(ui32Base + SHAMD5_O_SYSSTATUS) & - SHAMD5_SYSSTATUS_RESETDONE) == 0) - { - } - - // - // Force idle mode. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) = - ((HWREG(ui32Base + SHAMD5_O_SYSCONFIG) & ~SHAMD5_SYSCONFIG_SIDLE_M) | - SHAMD5_SYSCONFIG_SIDLE_FORCE); -} - -//***************************************************************************** -// -//! Enables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMAEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= - SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN; -} - -//***************************************************************************** -// -//! Disables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMADisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= - ~(SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN); -} - -//***************************************************************************** -// -//! Get the interrupt status of the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the current value of the IRQSTATUS register. The -//! value will be a logical OR of the following: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return Interrupt status -// -//***************************************************************************** -uint32_t -SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Status, ui32Enable, ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Return the value of the IRQSTATUS register. - // - ui32Status = HWREG(ui32Base + SHAMD5_O_IRQSTATUS); - if(bMasked) - { - ui32Enable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); - ui32Temp = HWREG(ui32Base + SHAMD5_O_DMAMIS); - return((ui32Status & ui32Enable) | - ((ui32Temp & 0x00000001) << 19) | - ((ui32Temp & 0x00000002) << 16) | - ((ui32Temp & 0x00000004) << 14)); - } - else - { - ui32Temp = HWREG(ui32Base + SHAMD5_O_DMARIS); - return(ui32Status | - ((ui32Temp & 0x00000001) << 19) | - ((ui32Temp & 0x00000002) << 16) | - ((ui32Temp & 0x00000004) << 14)); - } -} - -//***************************************************************************** -// -//! Enable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to enable. -//! -//! This function enables interrupt sources in the SHA/MD5 module. -//! ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Enable the interrupt sources. - // - HWREG(ui32Base + SHAMD5_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 14) | - ((ui32IntFlags & 0x00020000) >> 16) | - ((ui32IntFlags & 0x00040000) >> 19)); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; - - // - // Enable all interrupts. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_IT_EN; -} - -//***************************************************************************** -// -//! Disable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(ui32Base + SHAMD5_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 14) | - ((ui32IntFlags & 0x00020000) >> 16) | - ((ui32IntFlags & 0x00040000) >> 19)); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); - - // - // If there are no interrupts enabled, then disable all interrupts. - // - if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0) - { - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_IT_EN; - } -} - -//***************************************************************************** -// -//! Clears interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(ui32Base + SHAMD5_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 14) | - ((ui32IntFlags & 0x00020000) >> 16) | - ((ui32IntFlags & 0x00040000) >> 19)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled SHA/MD5 interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables SHA/MD5 interrupts on the interrupt controller; -//! specific SHA/MD5 interrupt sources must be enabled using -//! SHAMD5IntEnable(). The interrupt handler being registered must clear -//! the source of the interrupt using SHAMD5IntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_SHA0_TM4C129, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_SHA0_TM4C129); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_SHA0_TM4C129); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SHA0_TM4C129); -} - -//***************************************************************************** -// -//! Write the hash length to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32Length is the hash length in bytes. -//! -//! This function writes the length of the hash data of the current operation -//! to the SHA/MD5 module. The value must be a multiple of 64 if the close -//! hash is not set in the mode register. -//! -//! \note When this register is written, hash processing is triggered. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Set the LENGTH register and start processing. - // - HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Writes the mode in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32Mode is the mode of the SHA/MD5 module. -//! -//! This function writes the mode register configuring the SHA/MD5 module. -//! -//! The ui32Mode parameter is a bit-wise OR of values: -//! -//! - \b SHAMD5_ALGO_MD5 - Regular hash with MD5 -//! - \b SHAMD5_ALGO_SHA1 - Regular hash with SHA-1 -//! - \b SHAMD5_ALGO_SHA224 - Regular hash with SHA-224 -//! - \b SHAMD5_ALGO_SHA256 - Regular hash with SHA-256 -//! - \b SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5 -//! - \b SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1 -//! - \b SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224 -//! - \b SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256 -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32Mode == SHAMD5_ALGO_MD5) || - (ui32Mode == SHAMD5_ALGO_SHA1) || - (ui32Mode == SHAMD5_ALGO_SHA224) || - (ui32Mode == SHAMD5_ALGO_SHA256) || - (ui32Mode == SHAMD5_ALGO_HMAC_MD5) || - (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) || - (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) || - (ui32Mode == SHAMD5_ALGO_HMAC_SHA256)); - - // - // Write the value in the MODE register. - // - HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode; -} - -//***************************************************************************** -// -//! Perform a non-blocking write of 16 words of data to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of data that will be -//! written. -//! -//! This function writes 16 words of data into the data register regardless -//! of whether or not the module is ready to accept the data. -//! -//! \return This function returns true if the write completed successfully. -//! It returns false if the module was not ready. -// -//***************************************************************************** -bool -SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Counter; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Check that the SHA/MD5 module is ready for data. If not, return false. - // - if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0) - { - return(false); - } - - // - // Write the 16 words of data. - // - for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4) - { - HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++; - } - - // - // Return true as a sign of successfully completing the function. - // - return(true); -} - -//***************************************************************************** -// -//! Perform a blocking write of 16 words of data to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of data that will be -//! written. -//! -//! This function does not return until the module is ready to accept data and -//! the data has been written. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Counter; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Wait for the module to be ready to accept data. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0) - { - } - - // - // Write the 16 words of data. - // - for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4) - { - HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++; - } -} - -//***************************************************************************** -// -//! Reads the result of a hashing operation. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Dest is the pointer to the 16-word array of data that will be -//! written. -//! -//! This function does not return until the module is ready to accept data and -//! the data has been written. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest) -{ - uint32_t ui32Idx, ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Determine the number of bytes in the result, based on the hash type. - // - switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M) - { - // - // The MD5 hash is being used. - // - case SHAMD5_MODE_ALGO_MD5: - { - // - // There are 16 bytes in the MD5 hash. - // - ui32Count = 16; - - // - // Done. - // - break; - } - - // - // The SHA-1 hash is being used. - // - case SHAMD5_MODE_ALGO_SHA1: - { - // - // There are 20 bytes in the SHA-1 hash. - // - ui32Count = 20; - - // - // Done. - // - break; - } - - // - // The SHA-224 hash is being used. - // - case SHAMD5_MODE_ALGO_SHA224: - { - // - // There are 28 bytes in the SHA-224 hash. - // - ui32Count = 28; - - // - // Done. - // - break; - } - - // - // The SHA-256 hash is being used. - // - case SHAMD5_MODE_ALGO_SHA256: - { - // - // There are 32 bytes in the SHA-256 hash. - // - ui32Count = 32; - - // - // Done. - // - break; - } - - // - // The hash type is not recognized. - // - default: - { - // - // Return without reading a result since the hardware appears to be - // misconfigured. - // - return; - } - } - - // - // Read the hash result. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4) - { - *pui32Dest++ = HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx); - } -} - -//***************************************************************************** -// -//! Writes multiple words of data into the SHA/MD5 data registers. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32DataSrc is a pointer to an array of data to be written. -//! \param ui32DataLength is the length of the data to be written in bytes. -//! -//! This function writes a variable number of words into the SHA/MD5 data -//! registers. The function waits for each block of data to be processed -//! before another is written. The \e ui32DataLength parameter must be a -//! multiple of 4 to fall on a word boundry. -//! -//! \note This function is used by SHAMD5DataProcess() and SHAMD5HMACProcess() -//! to process data. -//! -//! \return None. -// -//***************************************************************************** -static void -_SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength) -{ - uint32_t ui32Idx, ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Calculate the number of blocks of data. - // - ui32Count = ui32DataLength / 64; - - // - // Loop through all the blocks and write them into the data registers - // making sure to block additional operations until we can write the - // next 16 words. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++) - { - // - // Write the block of data. - // - SHAMD5DataWrite(ui32Base, pui32DataSrc); - - // - // Increment the pointer to next block of data. - // - pui32DataSrc += 16; - } - - // - // Calculate the remaining bytes of data that don't make up a full block. - // - ui32Count = ui32DataLength % 64; - - // - // If there are bytes that do not make up a whole block, then - // write them separately. - // - if(ui32Count) - { - // - // Wait until the engine has finished processing the previous block. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & - SHAMD5_INT_INPUT_READY) == 0) - { - } - - // - // Loop through the remaining words. - // - for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4) - { - // - // Write the word into the data register. - // - HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Idx) = *pui32DataSrc++; - } - } -} - -//***************************************************************************** -// -//! Compute a hash using the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32DataSrc is a pointer to an array of data that contains the -//! data that will be hashed. -//! \param ui32DataLength specifies the length of the data to be hashed in -//! bytes. -//! \param pui32HashResult is a pointer to an array that holds the result -//! of the hashing operation. -//! -//! This function computes the hash of an array of data using the SHA/MD5 -//! module. -//! -//! The length of the hash result is dependent on the algorithm that is in use. -//! The following table shows the correct array size for each algorithm: -//! -//! ----------------------------------------- -//! | Algorithm | Number of Words in Result | -//! ----------------------------------------- -//! | MD5 | 4 Words (128 bits) | -//! | SHA-1 | 5 Words (160 bits) | -//! | SHA-224 | 7 Words (224 bits) | -//! | SHA-256 | 8 Words (256 bits) | -//! ----------------------------------------- -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, uint32_t *pui32HashResult) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32DataLength % 64) == 0); - - // - // Wait for the context to be ready before writing the mode. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == - 0) - { - } - - // - // Write the length. - // - SHAMD5HashLengthSet(ui32Base, ui32DataLength); - - // - // Write the data. - // - _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength); - - // - // Wait for the output to be ready. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == - 0) - { - } - - // - // Read the result. - // - SHAMD5ResultRead(ui32Base, pui32HashResult); -} - -//***************************************************************************** -// -//! Compute a HMAC with key pre-processing using the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32DataSrc is a pointer to an array of data that contains the -//! data that is to be hashed. -//! \param ui32DataLength specifies the length of the data to be hashed in -//! bytes. -//! \param pui32HashResult is a pointer to an array that holds the result -//! of the hashing operation. -//! -//! This function computes a HMAC with the given data using the SHA/MD5 -//! module with a preprocessed key. -//! -//! The length of the hash result is dependent on the algorithm that is -//! selected with the \e ui32Algo argument. The following table shows the -//! correct array size for each algorithm: -//! -//! ----------------------------------------- -//! | Algorithm | Number of Words in Result | -//! ----------------------------------------- -//! | MD5 | 4 Words (128 bits) | -//! | SHA-1 | 5 Words (160 bits) | -//! | SHA-224 | 7 Words (224 bits) | -//! | SHA-256 | 8 Words (256 bits) | -//! ----------------------------------------- -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, uint32_t *pui32HashResult) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Wait for the context to be ready before writing the mode. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == - 0) - { - } - - // - // Write the length. - // - SHAMD5HashLengthSet(ui32Base, ui32DataLength); - - // - // Write the data in the registers. - // - _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength); - - // - // Wait for the output to be ready. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == - 0) - { - } - - // - // Read the result. - // - SHAMD5ResultRead(ui32Base, pui32HashResult); -} - -//***************************************************************************** -// -//! Process an HMAC key using the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Key is a pointer to an array that contains the key to be -//! processed. -//! \param pui32PPKey is the pointer to the array that contains the -//! pre-processed key. -//! -//! This function processes an HMAC key using the SHA/MD5. The resultant -//! pre-processed key can then be used with later HMAC operations to speed -//! processing time. -//! -//! The \e pui32Key array must be 16 words (512 bits) long. If the key is less -//! than 512 bits, it must be padded with zeros. The \e pui32PPKey array must -//! each be 16 words (512 bits) long. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t *pui32PPKey) -{ - uint32_t ui32Index; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Wait for the context to be ready before writing the mode. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == - 0) - { - } - - // - // Write the HMAC key. - // - for(ui32Index = 0; ui32Index < 64; ui32Index += 4) - { - HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) = *pui32Key++; - } - - // - // Set the flag to cause the HMAC key to be pre-processed. - // - HWREG(ui32Base + SHAMD5_O_MODE) |= SHAMD5_MODE_HMAC_KEY_PROC; - - // - // Set the length to zero to start the HMAC key pre-processing. - // - HWREG(ui32Base + SHAMD5_O_LENGTH) = 0; - - // - // Wait for key to be processed. - // - while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == - 0) - { - } - - // - // Read the pre-processed key from the SHA/MD5 module. - // - for(ui32Index = 0; ui32Index < 64; ui32Index += 4) - { - *pui32PPKey++ = HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index); - } -} - -//***************************************************************************** -// -//! Writes an HMAC key to the digest registers in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of the HMAC key. -//! -//! This function is used to write HMAC key to the digest registers for -//! key preprocessing. The size of pui32Src must be 512 bytes. If the key is -//! less than 512 bytes, then it must be padded with zeros. -//! -//! \note It is recommended to use the SHAMD5IntStatus() function to check -//! whether the context is ready before writing the key. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the key to the digest registers. - // - for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4) - { - HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++; - } - - // - // Configure the SHA engine for HMAC operation. - // - HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH | - SHAMD5_MODE_HMAC_KEY_PROC | - SHAMD5_MODE_CLOSE_HASH); -} - -//***************************************************************************** -// -//! Writes a pre-processed HMAC key to the digest registers in the SHA/MD5 -//! module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pui32Src is the pointer to the 16-word array of the HMAC key. -//! -//! This function is used to write HMAC key to the digest registers for -//! key preprocessing. The size of pui32Src must be 512 bytes. If the key is -//! less than 512 bytes, then it must be padded with zeros. -//! -//! \note It is recommended to use the SHAMD5IntStatus() function to check -//! whether the context is ready before writing the key. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src) -{ - uint32_t ui32Idx; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the key to the digest registers. - // - for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4) - { - HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++; - } - - // - // Configure the SHA engine to continue the HMAC. - // - HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH | - SHAMD5_MODE_CLOSE_HASH); - - // - // Write the digest count to 64 to account for the preprocessed key. - // - HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.h b/bsp/tm4c129x-dk/libraries/driverlib/shamd5.h deleted file mode 100644 index 3b0e793b4f..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/shamd5.h +++ /dev/null @@ -1,127 +0,0 @@ -//***************************************************************************** -// -// shamd5.h - Defines and Macros for the SHA/MD5. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SHAMD5_H__ -#define __DRIVERLIB_SHAMD5_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the algorithm in use in the -// SHA/MD5 module. -// -//***************************************************************************** -#define SHAMD5_ALGO_MD5 0x00000018 -#define SHAMD5_ALGO_SHA1 0x0000001a -#define SHAMD5_ALGO_SHA224 0x0000001c -#define SHAMD5_ALGO_SHA256 0x0000001e -#define SHAMD5_ALGO_HMAC_MD5 0x00000000 -#define SHAMD5_ALGO_HMAC_SHA1 0x00000002 -#define SHAMD5_ALGO_HMAC_SHA224 0x00000004 -#define SHAMD5_ALGO_HMAC_SHA256 0x00000006 - -//***************************************************************************** -// -// The following defines are used to represent the different interrupt sources -// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and -// SHAMD5BlockOnIntStatus() functions. -// -//***************************************************************************** -#define SHAMD5_INT_CONTEXT_READY \ - 0x00000008 -#define SHAMD5_INT_PARTHASH_READY \ - 0x00000004 -#define SHAMD5_INT_INPUT_READY 0x00000002 -#define SHAMD5_INT_OUTPUT_READY 0x00000001 -#define SHAMD5_INT_DMA_CONTEXT_IN \ - 0x00080000 -#define SHAMD5_INT_DMA_DATA_IN 0x00020000 -#define SHAMD5_INT_DMA_CONTEXT_OUT \ - 0x00010000 - -//***************************************************************************** -// -// Function prototypes -// -//***************************************************************************** -extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode); -extern void SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, - uint32_t *pui32HashResult); -extern void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src); -extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src); -extern void SHAMD5DMADisable(uint32_t ui32Base); -extern void SHAMD5DMAEnable(uint32_t ui32Base); -extern void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src); -extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key, - uint32_t *pui32PPKey); -extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src); -extern void SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc, - uint32_t ui32DataLength, - uint32_t *pui32HashResult); -extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked); -extern void SHAMD5IntUnregister(uint32_t ui32Base); -extern void SHAMD5Reset(uint32_t ui32Base); -extern void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SHAMD5_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/ssi.c b/bsp/tm4c129x-dk/libraries/driverlib/ssi.c deleted file mode 100644 index cf7a2d3bc2..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/ssi.c +++ /dev/null @@ -1,1150 +0,0 @@ -//***************************************************************************** -// -// ssi.c - Driver for Synchronous Serial Interface. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ssi_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ssi.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/ssi.h" - -//***************************************************************************** -// -// A mapping of timer base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32SSIIntMap[][2] = -{ - { SSI0_BASE, INT_SSI0_TM4C123 }, - { SSI1_BASE, INT_SSI1_TM4C123 }, - { SSI2_BASE, INT_SSI2_TM4C123 }, - { SSI3_BASE, INT_SSI3_TM4C123 }, -}; -static const uint_fast8_t g_ui8SSIIntMapRows = - sizeof(g_ppui32SSIIntMap) / sizeof(g_ppui32SSIIntMap[0]); - -static const uint32_t g_ppui32SSIIntMapSnowflake[][2] = -{ - { SSI0_BASE, INT_SSI0_TM4C129 }, - { SSI1_BASE, INT_SSI1_TM4C129 }, - { SSI2_BASE, INT_SSI2_TM4C129 }, - { SSI3_BASE, INT_SSI3_TM4C129 }, -}; -static const uint_fast8_t g_ui8SSIIntMapSnowflakeRows = - sizeof(g_ppui32SSIIntMapSnowflake) / sizeof(g_ppui32SSIIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks an SSI base address. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function determines if a SSI module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_SSIBaseValid(uint32_t ui32Base) -{ - return((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE) || - (ui32Base == SSI2_BASE) || (ui32Base == SSI3_BASE)); -} -#endif - -//***************************************************************************** -// -//! Returns the interrupt number of SSI module . -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function returns the interrupt number for the SSI module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns an SSI interrupt number, or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_SSIIntNumberGet(uint32_t ui32Base) -{ - uint_fast8_t ui8Idx, ui8Rows; - const uint32_t (*ppui32SSIIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - ppui32SSIIntMap = g_ppui32SSIIntMap; - ui8Rows = g_ui8SSIIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32SSIIntMap = g_ppui32SSIIntMapSnowflake; - ui8Rows = g_ui8SSIIntMapSnowflakeRows; - } - - // - // Loop through the table that maps SSI base addresses to interrupt - // numbers. - // - for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) - { - // - // See if this base address matches. - // - if(ppui32SSIIntMap[ui8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32SSIIntMap[ui8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Configures the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. -//! \param ui32Protocol specifies the data transfer protocol. -//! \param ui32Mode specifies the mode of operation. -//! \param ui32BitRate specifies the clock rate. -//! \param ui32DataWidth specifies number of bits transferred per frame. -//! -//! This function configures the synchronous serial interface. It sets -//! the SSI protocol, mode of operation, bit rate, and data width. -//! -//! The \e ui32Protocol parameter defines the data frame format. The -//! \e ui32Protocol parameter can be one of the following values: -//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2, -//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. Note that -//! the \b SSI_FRF_NMW option is only available on some devices. Refer to the -//! device data sheet to determine if the Microwire format is supported on -//! a particular device. The Motorola frame formats encode the following -//! polarity and phase configurations: -//! -//! 
-//! Polarity Phase       Mode
-//!   0       0   SSI_FRF_MOTO_MODE_0
-//!   0       1   SSI_FRF_MOTO_MODE_1
-//!   1       0   SSI_FRF_MOTO_MODE_2
-//!   1       1   SSI_FRF_MOTO_MODE_3
-//!
-//! -//! The \e ui32Mode parameter defines the operating mode of the SSI module. -//! The SSI module can operate as a master or slave; if it is a slave, the SSI -//! can be configured to disable output on its serial output line. The -//! \e ui32Mode parameter can be one of the following values: -//! \b SSI_MODE_MASTER, \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD. -//! -//! The \e ui32BitRate parameter defines the bit rate for the SSI. This bit -//! rate must satisfy the following clock ratio criteria: -//! -//! - FSSI >= 2 * bit rate (master mode) -//! - FSSI >= 12 * bit rate (slave modes) -//! -//! where FSSI is the frequency of the clock supplied to the SSI module. Note -//! that there are frequency limits for FSSI that are described in the Bit Rate -//! Generation section of the SSI chapter in the data sheet. -//! -//! The \e ui32DataWidth parameter defines the width of the data transfers and -//! can be a value between 4 and 16, inclusive. -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! \return None. -// -//***************************************************************************** -void -SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth) -{ - uint32_t ui32MaxBitRate; - uint32_t ui32RegVal; - uint32_t ui32PreDiv; - uint32_t ui32SCR; - uint32_t ui32SPH_SPO; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || - (ui32Protocol == SSI_FRF_MOTO_MODE_1) || - (ui32Protocol == SSI_FRF_MOTO_MODE_2) || - (ui32Protocol == SSI_FRF_MOTO_MODE_3) || - (ui32Protocol == SSI_FRF_TI) || - (ui32Protocol == SSI_FRF_NMW)); - ASSERT((ui32Mode == SSI_MODE_MASTER) || - (ui32Mode == SSI_MODE_SLAVE)); - ASSERT(((ui32Mode == SSI_MODE_MASTER) && - (ui32BitRate <= (ui32SSIClk / 2))) || - ((ui32Mode != SSI_MODE_MASTER) && - (ui32BitRate <= (ui32SSIClk / 12)))); - ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); - ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); - - // - // Set the mode. - // - ui32RegVal = (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; - - // - // Set the clock predivider. - // - ui32MaxBitRate = ui32SSIClk / ui32BitRate; - ui32PreDiv = 0; - do - { - ui32PreDiv += 2; - ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; - } - while(ui32SCR > 255); - HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; - - // - // Set protocol and clock rate. - // - ui32SPH_SPO = (ui32Protocol & 3) << 6; - ui32Protocol &= SSI_CR0_FRF_M; - ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | - (ui32DataWidth - 1); - HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; -} - -//***************************************************************************** -// -//! Enables the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function enables operation of the synchronous serial interface. The -//! synchronous serial interface must be configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -SSIEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Read-modify-write the enable bit. - // - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; -} - -//***************************************************************************** -// -//! Disables the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function disables operation of the synchronous serial interface. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Read-modify-write the enable bit. - // - HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial interface interrupt occurs. -//! -//! This function registers the handler to be called when an SSI interrupt -//! occurs. This function enables the global interrupt in the interrupt -//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If -//! necessary, it is the interrupt handler's responsibility to clear the -//! interrupt source via SSIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the SSI module. - // - ui32Int = _SSIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the synchronous serial interface interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the synchronous serial interface. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! This function clears the handler to be called when an SSI interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the SSI module. - // - ui32Int = _SSIIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated SSI interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. The \e ui32IntFlags -//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or -//! \b SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + SSI_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated SSI interrupt sources. The -//! \e ui32IntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, -//! \b SSI_RXTO, or \b SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + SSI_O_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param bMasked is \b false if the raw interrupt status is required or -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the SSI module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR. -// -//***************************************************************************** -uint32_t -SSIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + SSI_O_MIS)); - } - else - { - return(HWREG(ui32Base + SSI_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! This function clears the specified SSI interrupt sources so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupts from being triggered again immediately upon exit. The -//! \e ui32IntFlags parameter can consist of either or both the \b SSI_RXTO and -//! \b SSI_RXOR values. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. If there is no space available in the transmit FIFO, -//! this function waits until there is space available before returning. -//! -//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware, -//! where N is the data width as configured by SSIConfigSetExpClk(). For -//! example, if the interface is configured for 8-bit data width, the upper 24 -//! bits of \e ui32Data are discarded. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. If there is no space in the FIFO, then this function -//! returns a zero. -//! -//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware, -//! where N is the data width as configured by SSIConfigSetExpClk(). For -//! example, if the interface is configured for 8-bit data width, the upper 24 -//! bits of \e ui32Data are discarded. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -int32_t -SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // - // Check for space to write. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! This function gets received data from the receive FIFO of the specified -//! SSI module and places that data into the location specified by the -//! \e pui32Data parameter. If there is no data available, this function waits -//! until data is received before returning. -//! -//! \note Only the lower N bits of the value written to \e pui32Data contain -//! valid data, where N is the data width as configured by -//! SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to -//! \e pui32Data contain valid data. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Wait until there is data to be read. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // - // Read data from SSI. - // - *pui32Data = HWREG(ui32Base + SSI_O_DR); -} - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! This function gets received data from the receive FIFO of the specified SSI -//! module and places that data into the location specified by the \e ui32Data -//! parameter. If there is no data in the FIFO, then this function returns a -//! zero. -//! -//! \note Only the lower N bits of the value written to \e pui32Data contain -//! valid data, where N is the data width as configured by -//! SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to -//! \e pui32Data contain valid data. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -int32_t -SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Check for data to read. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) - { - *pui32Data = HWREG(ui32Base + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Enables SSI DMA operation. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! -//! This function enables the specified SSI DMA features. The SSI can be -//! configured to use DMA for transmit and/or receive data transfers. -//! The \e ui32DMAFlags parameter is the logical OR of any of the following -//! values: -//! -//! - SSI_DMA_RX - enable DMA for receive -//! - SSI_DMA_TX - enable DMA for transmit -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the SSI. -//! -//! \return None. -// -//***************************************************************************** -void -SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Set the requested bits in the SSI DMA control register. - // - HWREG(ui32Base + SSI_O_DMACTL) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! Disables SSI DMA operation. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! -//! This function is used to disable SSI DMA features that were enabled -//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The -//! \e ui32DMAFlags parameter is the logical OR of any of the following values: -//! -//! - SSI_DMA_RX - disable DMA for receive -//! - SSI_DMA_TX - disable DMA for transmit -//! -//! \return None. -// -//***************************************************************************** -void -SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Clear the requested bits in the SSI DMA control register. - // - HWREG(ui32Base + SSI_O_DMACTL) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -//! Determines whether the SSI transmitter is busy or not. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function allows the caller to determine whether all transmitted bytes -//! have cleared the transmitter hardware. If \b false is returned, then the -//! transmit FIFO is empty and all bits of the last transmitted word have left -//! the hardware shift register. -//! -//! \return Returns \b true if the SSI is transmitting or \b false if all -//! transmissions are complete. -// -//***************************************************************************** -bool -SSIBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Determine if the SSI is busy. - // - return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); -} - -//***************************************************************************** -// -//! Sets the data clock source for the specified SSI peripheral. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32Source is the baud clock source for the SSI. -//! -//! This function allows the baud clock source for the SSI to be selected. -//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b SSI_CLOCK_PIOSC). -//! -//! Changing the baud clock source changes the data rate generated by the -//! SSI. Therefore, the data rate should be reconfigured after any change to -//! the SSI clock source. -//! -//! \note The ability to specify the SSI baud clock source varies with the -//! Tiva part and SSI in use. Please consult the data sheet for the part -//! in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Source == SSI_CLOCK_SYSTEM) || - (ui32Source == SSI_CLOCK_PIOSC)); - - // - // Set the SSI clock source. - // - HWREG(ui32Base + SSI_O_CC) = ui32Source; -} - -//***************************************************************************** -// -//! Gets the data clock source for the specified SSI peripheral. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function returns the data clock source for the specified SSI. -//! -//! \note The ability to specify the SSI data clock source varies with the -//! Tiva part and SSI in use. Please consult the data sheet for the part -//! in use to determine whether this support is available. -//! -//! \return Returns the current clock source, which is either -//! \b SSI_CLOCK_SYSTEM or \b SSI_CLOCK_PIOSC. -// -//***************************************************************************** -uint32_t -SSIClockSourceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Return the SSI clock source. - // - return(HWREG(ui32Base + SSI_O_CC)); -} - -//***************************************************************************** -// -//! Selects the advanced mode of operation for the SSI module. -//! -//! \param ui32Base is the base address of the SSI module. -//! \param ui32Mode is the mode of operation to use. -//! -//! This function selects the mode of operation for the SSI module, which is -//! needed when using the advanced operation modes (Bi- or Quad-SPI). One of -//! the following modes can be selected: -//! -//! - \b SSI_ADV_MODE_LEGACY - Disables the advanced modes of operation, -//! resulting in legacy, or backwards-compatible, operation. When this mode -//! is selected, it is not valid to switch to Bi- or Quad-SPI operation. -//! This mode is the default. -//! - \b SSI_ADV_MODE_WRITE - The advanced mode of operation where data is only -//! written to the slave; any data clocked in via the \b SSIRx pin is thrown -//! away (instead of being placed into the SSI Rx FIFO). -//! - \b SSI_ADV_MODE_READ_WRITE - The advanced mode of operation where data is -//! written to and read from the slave; this mode is the same as -//! \b SSI_ADV_MODE_LEGACY but allows transitions to Bi- or Quad-SPI -//! operation. -//! - \b SSI_ADV_MODE_BI_READ - The advanced mode of operation where data is -//! read from the slave in Bi-SPI mode, with two bits of data read on every -//! SSI clock. -//! - \b SSI_ADV_MODE_BI_WRITE - The advanced mode of operation where data is -//! written to the slave in Bi-SPI mode, with two bits of data written on -//! every SSI clock. -//! - \b SSI_ADV_MODE_QUAD_READ - The advanced mode of operation where data is -//! read from the slave in Quad-SPI mode, with four bits of data read on -//! every SSI clock. -//! - \b SSI_ADV_MODE_QUAD_WRITE - The advanced mode of operation where data is -//! written to the slave in Quad-SPI mode, with four bits of data written on -//! every SSI clock. -//! -//! The following mode transitions are valid (other transitions produce -//! undefined results): -//! -//! \verbatim -//! +----------+-------------------------------------------------------------+ -//! |FROM | TO | -//! | |Legacy|Write|Read Write|Bi Read|Bi Write|Quad Read|Quad Write| -//! +----------+------+-----+----------+-------+--------+---------+----------+ -//! |Legacy | yes | yes | yes | | | | | -//! |Write | yes | yes | yes | yes | yes | yes | yes | -//! |Read/Write| yes | yes | yes | yes | yes | yes | yes | -//! |Bi Read | | yes | yes | yes | yes | | | -//! |Bi write | | yes | yes | yes | yes | | | -//! |Quad read | | yes | yes | | | yes | yes | -//! |Quad write| | yes | yes | | | yes | yes | -//! +----------+------+-----+----------+-------+--------+---------+----------+ -//! \endverbatim -//! -//! When using an advanced mode of operation, the SSI module must have been -//! configured for eight data bits and the \b SSI_FRF_MOTO_MODE_0 protocol. -//! The advanced mode operation that is selected applies only to data newly -//! written into the FIFO; the data that is already present in the FIFO is -//! handled using the advanced mode of operation in effect when that data was -//! written. -//! -//! Switching into and out of legacy mode should only occur when the FIFO is -//! empty. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Mode == SSI_ADV_MODE_LEGACY) || - (ui32Mode == SSI_ADV_MODE_WRITE) || - (ui32Mode == SSI_ADV_MODE_READ_WRITE) || - (ui32Mode == SSI_ADV_MODE_BI_READ) || - (ui32Mode == SSI_ADV_MODE_BI_WRITE) || - (ui32Mode == SSI_ADV_MODE_QUAD_READ) || - (ui32Mode == SSI_ADV_MODE_QUAD_WRITE)); - - // - // Set the SSI mode of operation. - // - HWREG(ui32Base + SSI_O_CR1) = - ((HWREG(ui32Base + SSI_O_CR1) & ~(SSI_CR1_DIR | SSI_CR1_MODE_M)) | - ui32Mode); -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO as the end of a frame. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module, marking it as the end of a frame. If there is no -//! space available in the transmit FIFO, this function waits until there is -//! space available before returning. After this byte is transmitted by the -//! SSI module, the FSS signal de-asserts for at least one SSI clock. -//! -//! \note The upper 24 bits of \e ui32Data are discarded by the hardware. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & 0xff) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM; - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO as the end of a frame. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module, marking it as the end of a frame. After this byte is -//! transmitted by the SSI module, the FSS signal de-asserts for at least one -//! SSI clock. If there is no space in the FIFO, then this function returns a -//! zero. -//! -//! \note The upper 24 bits of \e ui32Data are discarded by the hardware. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -int32_t -SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - ASSERT((ui32Data & 0xff) == 0); - - // - // Check for space to write. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_EOM; - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Configures the SSI advanced mode to hold the SSIFss signal during the full -//! transfer. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function configures the SSI module to de-assert the SSIFss signal -//! during the entire data transfer when using one of the advanced modes -//! (instead of briefly de-asserting it after every byte). When using this -//! mode, SSIFss can be directly controlled via SSIAdvDataPutFrameEnd() and -//! SSIAdvDataPutFrameEndNonBlocking(). -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvFrameHoldEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Set the hold frame bit. - // - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_FSSHLDFRM; -} - -//***************************************************************************** -// -//! Configures the SSI advanced mode to de-assert the SSIFss signal after every -//! byte transfer. -//! -//! \param ui32Base is the base address of the SSI module. -//! -//! This function configures the SSI module to de-assert the SSIFss signal -//! for one SSI clock cycle after every byte is transferred using one of the -//! advanced modes (instead of leaving it asserted for the entire transfer). -//! This mode is the default operation. -//! -//! \note The availability of the advanced mode of SSI operation varies with -//! the Tiva part and SSI in use. Please consult the data sheet for the -//! part in use to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SSIAdvFrameHoldDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_SSIBaseValid(ui32Base)); - - // - // Clear the hold frame bit. - // - HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_FSSHLDFRM); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/ssi.h b/bsp/tm4c129x-dk/libraries/driverlib/ssi.h deleted file mode 100644 index 37d928dd1b..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/ssi.h +++ /dev/null @@ -1,157 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SSI_H__ -#define __DRIVERLIB_SSI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ui32IntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXEOT 0x00000040 // Transmit FIFO is empty -#define SSI_DMATX 0x00000020 // DMA Transmit complete -#define SSI_DMARX 0x00000010 // DMA Receive complete -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfigSetExpClk. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). -// -//***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values that can be passed to SSIClockSourceSet() or returned from -// SSIClockSourceGet(). -// -//***************************************************************************** -#define SSI_CLOCK_SYSTEM 0x00000000 -#define SSI_CLOCK_PIOSC 0x00000005 - -//***************************************************************************** -// -// Values that can be passed to SSIAdvModeSet(). -// -//***************************************************************************** -#define SSI_ADV_MODE_LEGACY 0x00000000 -#define SSI_ADV_MODE_READ_WRITE 0x000001c0 -#define SSI_ADV_MODE_WRITE 0x000000c0 -#define SSI_ADV_MODE_BI_READ 0x00000140 -#define SSI_ADV_MODE_BI_WRITE 0x00000040 -#define SSI_ADV_MODE_QUAD_READ 0x00000180 -#define SSI_ADV_MODE_QUAD_WRITE 0x00000080 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, - uint32_t ui32DataWidth); -extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); -extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, - uint32_t *pui32Data); -extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); -extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); -extern void SSIDisable(uint32_t ui32Base); -extern void SSIEnable(uint32_t ui32Base); -extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked); -extern void SSIIntUnregister(uint32_t ui32Base); -extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern bool SSIBusy(uint32_t ui32Base); -extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); -extern uint32_t SSIClockSourceGet(uint32_t ui32Base); -extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode); -extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data); -extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, - uint32_t ui32Data); -extern void SSIAdvFrameHoldEnable(uint32_t ui32Base); -extern void SSIAdvFrameHoldDisable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SSI_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.c b/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.c deleted file mode 100644 index 0706c34d50..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.c +++ /dev/null @@ -1,770 +0,0 @@ -//***************************************************************************** -// -// sw_crc.c - Software CRC functions. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sw_crc_api -//! @{ -// -//***************************************************************************** - -#include -#include "driverlib/sw_crc.h" - -//***************************************************************************** -// -// The CRC table for the polynomial C(x) = x^8 + x^2 + x + 1 (CRC-8-CCITT). -// -//***************************************************************************** -static const uint8_t g_pui8Crc8CCITT[256] = -{ - 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, - 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D, - 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65, - 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D, - 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5, - 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD, - 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85, - 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD, - 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2, - 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA, - 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2, - 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A, - 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32, - 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A, - 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42, - 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A, - 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C, - 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4, - 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC, - 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4, - 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C, - 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44, - 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C, - 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34, - 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B, - 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63, - 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B, - 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13, - 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB, - 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83, - 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB, - 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3 -}; - -//***************************************************************************** -// -// The CRC-16 table for the polynomial C(x) = x^16 + x^15 + x^2 + 1 (standard -// CRC-16, also known as CRC-16-IBM and CRC-16-ANSI). -// -//***************************************************************************** -static const uint16_t g_pui16Crc16[256] = -{ - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 -}; - -//***************************************************************************** -// -// The CRC-32 table for the polynomial C(x) = x^32 + x^26 + x^23 + x^22 + -// x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 (standard -// CRC32 as used in Ethernet, MPEG-2, PNG, etc.). -// -//***************************************************************************** -static const uint32_t g_pui32Crc32[] = -{ - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, - 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, - 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, - 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, - 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, - 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, - 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, - 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, - 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, - 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, - 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, - 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, - 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, - 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, - 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, - 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, - 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, - 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, - 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, - 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, - 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, - 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, - 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, - 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, - 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, - 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, - 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, - 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, - 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, - 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, - 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, - 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, - 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, - 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, - 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, - 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, - 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, - 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, - 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, - 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, - 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, - 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, - 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, - 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, - 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, - 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, - 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, - 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, - 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, - 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, - 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, - 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, - 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, - 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, -}; - -//***************************************************************************** -// -// This macro executes one iteration of the CRC-8-CCITT. -// -//***************************************************************************** -#define CRC8_ITER(crc, data) g_pui8Crc8CCITT[(uint8_t)((crc) ^ (data))] - -//***************************************************************************** -// -// This macro executes one iteration of the CRC-16. -// -//***************************************************************************** -#define CRC16_ITER(crc, data) (((crc) >> 8) ^ \ - g_pui16Crc16[(uint8_t)((crc) ^ (data))]) - -//***************************************************************************** -// -// This macro executes one iteration of the CRC-32. -// -//***************************************************************************** -#define CRC32_ITER(crc, data) (((crc) >> 8) ^ \ - g_pui32Crc32[(uint8_t)((crc & 0xFF) ^ \ - (data))]) - -//***************************************************************************** -// -//! Calculates the CRC-8-CCITT of an array of bytes. -//! -//! \param ui8Crc is the starting CRC-8-CCITT value. -//! \param pui8Data is a pointer to the data buffer. -//! \param ui32Count is the number of bytes in the data buffer. -//! -//! This function is used to calculate the CRC-8-CCITT of the input buffer. -//! The CRC-8-CCITT is computed in a running fashion, meaning that the entire -//! data block that is to have its CRC-8-CCITT computed does not need to be -//! supplied all at once. If the input buffer contains the entire block of -//! data, then \b ui8Crc should be set to 0. If, however, the entire block of -//! data is not available, then \b ui8Crc should be set to 0 for the first -//! portion of the data, and then the returned value should be passed back in -//! as \b ui8Crc for the next portion of the data. -//! -//! For example, to compute the CRC-8-CCITT of a block that has been split into -//! three pieces, use the following: -//! -//! \verbatim -//! ui8Crc = Crc8CCITT(0, pui8Data1, ui32Len1); -//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data2, ui32Len2); -//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data3, ui32Len3); -//! \endverbatim -//! -//! Computing a CRC-8-CCITT in a running fashion is useful in cases where the -//! data is arriving via a serial link (for example) and is therefore not all -//! available at one time. -//! -//! \return The CRC-8-CCITT of the input data. -// -//***************************************************************************** -uint8_t -Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, uint32_t ui32Count) -{ - uint32_t ui32Temp; - - // - // If the data buffer is not 16 bit-aligned, then perform a single step of - // the CRC to make it 16 bit-aligned. - // - if((uint32_t)pui8Data & 1) - { - // - // Perform the CRC on this input byte. - // - ui8Crc = CRC8_ITER(ui8Crc, *pui8Data); - - // - // Skip this input byte. - // - pui8Data++; - ui32Count--; - } - - // - // If the data buffer is not word-aligned and there are at least two bytes - // of data left, then perform two steps of the CRC to make it word-aligned. - // - if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) - { - // - // Read the next 16 bits. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // While there is at least a word remaining in the data buffer, perform - // four steps of the CRC to consume a word. - // - while(ui32Count > 3) - { - // - // Read the next word. - // - ui32Temp = *(uint32_t *)pui8Data; - - // - // Perform the CRC on these four bytes. - // - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 16); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 24); - - // - // Skip these input bytes. - // - pui8Data += 4; - ui32Count -= 4; - } - - // - // If there are 16 bits left in the input buffer, then perform two steps of - // the CRC. - // - if(ui32Count > 1) - { - // - // Read the 16 bits. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp); - ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // If there is a final byte remaining in the input buffer, then perform a - // single step of the CRC. - // - if(ui32Count != 0) - { - ui8Crc = CRC8_ITER(ui8Crc, *pui8Data); - } - - // - // Return the resulting CRC-8-CCITT value. - // - return(ui8Crc); -} - -//***************************************************************************** -// -//! Calculates the CRC-16 of an array of bytes. -//! -//! \param ui16Crc is the starting CRC-16 value. -//! \param pui8Data is a pointer to the data buffer. -//! \param ui32Count is the number of bytes in the data buffer. -//! -//! This function is used to calculate the CRC-16 of the input buffer. The -//! CRC-16 is computed in a running fashion, meaning that the entire data block -//! that is to have its CRC-16 computed does not need to be supplied all at -//! once. If the input buffer contains the entire block of data, then -//! \b ui16Crc should be set to 0. If, however, the entire block of data is -//! not available, then \b ui16Crc should be set to 0 for the first portion of -//! the data, and then the returned value should be passed back in as -//! \b ui16Crc for the next portion of the data. -//! -//! For example, to compute the CRC-16 of a block that has been split into -//! three pieces, use the following: -//! -//! \verbatim -//! ui16Crc = Crc16(0, pui8Data1, ui32Len1); -//! ui16Crc = Crc16(ui16Crc, pui8Data2, ui32Len2); -//! ui16Crc = Crc16(ui16Crc, pui8Data3, ui32Len3); -//! \endverbatim -//! -//! Computing a CRC-16 in a running fashion is useful in cases where the data -//! is arriving via a serial link (for example) and is therefore not all -//! available at one time. -//! -//! \return The CRC-16 of the input data. -// -//***************************************************************************** -uint16_t -Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, uint32_t ui32Count) -{ - uint32_t ui32Temp; - - // - // If the data buffer is not 16 bit-aligned, then perform a single step of - // the CRC to make it 16 bit-aligned. - // - if((uint32_t)pui8Data & 1) - { - // - // Perform the CRC on this input byte. - // - ui16Crc = CRC16_ITER(ui16Crc, *pui8Data); - - // - // Skip this input byte. - // - pui8Data++; - ui32Count--; - } - - // - // If the data buffer is not word-aligned and there are at least two bytes - // of data left, then perform two steps of the CRC to make it word-aligned. - // - if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) - { - // - // Read the next 16 bits. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // While there is at least a word remaining in the data buffer, perform - // four steps of the CRC to consume a word. - // - while(ui32Count > 3) - { - // - // Read the next word. - // - ui32Temp = *(uint32_t *)pui8Data; - - // - // Perform the CRC on these four bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24); - - // - // Skip these input bytes. - // - pui8Data += 4; - ui32Count -= 4; - } - - // - // If there are two bytes left in the input buffer, then perform two steps - // of the CRC. - // - if(ui32Count > 1) - { - // - // Read the two bytes. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // If there is a final byte remaining in the input buffer, then perform a - // single step of the CRC. - // - if(ui32Count != 0) - { - ui16Crc = CRC16_ITER(ui16Crc, *pui8Data); - } - - // - // Return the resulting CRC-16 value. - // - return(ui16Crc); -} - -//***************************************************************************** -// -//! Calculates the CRC-16 of an array of words. -//! -//! \param ui32WordLen is the length of the array in words (the number of bytes -//! divided by 4). -//! \param pui32Data is a pointer to the data buffer. -//! -//! This function is a wrapper around the running CRC-16 function, providing -//! the CRC-16 for a single block of data. -//! -//! \return The CRC-16 of the input data. -// -//***************************************************************************** -uint16_t -Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data) -{ - // - // Calculate and return the CRC-16 of this array of words. - // - return(Crc16(0, (const uint8_t *)pui32Data, ui32WordLen * 4)); -} - -//***************************************************************************** -// -//! Calculates three CRC-16s of an array of words. -//! -//! \param ui32WordLen is the length of the array in words (the number of bytes -//! divided by 4). -//! \param pui32Data is a pointer to the data buffer. -//! \param pui16Crc3 is a pointer to an array in which to place the three -//! CRC-16 values. -//! -//! This function is used to calculate three CRC-16s of the input buffer; the -//! first uses every byte from the array, the second uses only the even-index -//! bytes from the array (in other words, bytes 0, 2, 4, etc.), and the third -//! uses only the odd-index bytes from the array (in other words, bytes 1, 3, -//! 5, etc.). -//! -//! \return None -// -//***************************************************************************** -void -Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data, - uint16_t *pui16Crc3) -{ - uint16_t ui16Crc, ui16Cri8Odd, ui16Cri8Even; - uint32_t ui32Temp; - - // - // Initialize the CRC values to zero. - // - ui16Crc = 0; - ui16Cri8Odd = 0; - ui16Cri8Even = 0; - - // - // Loop while there are more words in the data buffer. - // - while(ui32WordLen--) - { - // - // Read the next word. - // - ui32Temp = *pui32Data++; - - // - // Perform the first CRC on all four data bytes. - // - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16); - ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24); - - // - // Perform the second CRC on only the even-index data bytes. - // - ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp); - ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp >> 16); - - // - // Perform the third CRC on only the odd-index data bytes. - // - ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 8); - ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 24); - } - - // - // Return the resulting CRC-16 values. - // - pui16Crc3[0] = ui16Crc; - pui16Crc3[1] = ui16Cri8Even; - pui16Crc3[2] = ui16Cri8Odd; -} - -//***************************************************************************** -// -//! Calculates the CRC-32 of an array of bytes. -//! -//! \param ui32Crc is the starting CRC-32 value. -//! \param pui8Data is a pointer to the data buffer. -//! \param ui32Count is the number of bytes in the data buffer. -//! -//! This function is used to calculate the CRC-32 of the input buffer. The -//! CRC-32 is computed in a running fashion, meaning that the entire data block -//! that is to have its CRC-32 computed does not need to be supplied all at -//! once. If the input buffer contains the entire block of data, then -//! \b ui32Crc should be set to 0xFFFFFFFF. If, however, the entire block of -//! data is not available, then \b ui32Crc should be set to 0xFFFFFFFF for the -//! first portion of the data, and then the returned value should be passed -//! back in as \b ui32Crc for the next portion of the data. Once all data has -//! been passed to the function, the final CRC-32 can be obtained by inverting -//! the last returned value. -//! -//! For example, to compute the CRC-32 of a block that has been split into -//! three pieces, use the following: -//! -//! \verbatim -//! ui32Crc = Crc32(0xFFFFFFFF, pui8Data1, ui32Len1); -//! ui32Crc = Crc32(ui32Crc, pui8Data2, ui32Len2); -//! ui32Crc = Crc32(ui32Crc, pui8Data3, ui32Len3); -//! ui32Crc ^= 0xFFFFFFFF; -//! \endverbatim -//! -//! Computing a CRC-32 in a running fashion is useful in cases where the data -//! is arriving via a serial link (for example) and is therefore not all -//! available at one time. -//! -//! \return The accumulated CRC-32 of the input data. -// -//***************************************************************************** -uint32_t -Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, uint32_t ui32Count) -{ - uint32_t ui32Temp; - - // - // If the data buffer is not 16 bit-aligned, then perform a single step - // of the CRC to make it 16 bit-aligned. - // - if((uint32_t)pui8Data & 1) - { - // - // Perform the CRC on this input byte. - // - ui32Crc = CRC32_ITER(ui32Crc, *pui8Data); - - // - // Skip this input byte. - // - pui8Data++; - ui32Count--; - } - - // - // If the data buffer is not word-aligned and there are at least two bytes - // of data left, then perform two steps of the CRC to make it word-aligned. - // - if(((uint32_t)pui8Data & 2) && (ui32Count > 1)) - { - // - // Read the next int16_t. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // While there is at least a word remaining in the data buffer, perform - // four steps of the CRC to consume a word. - // - while(ui32Count > 3) - { - // - // Read the next word. - // - ui32Temp = *(uint32_t *)pui8Data; - - // - // Perform the CRC on these four bytes. - // - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 16); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 24); - - // - // Skip these input bytes. - // - pui8Data += 4; - ui32Count -= 4; - } - - // - // If there are 16 bits left in the input buffer, then perform two steps of - // the CRC. - // - if(ui32Count > 1) - { - // - // Read the two bytes. - // - ui32Temp = *(uint16_t *)pui8Data; - - // - // Perform the CRC on these two bytes. - // - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp); - ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8); - - // - // Skip these input bytes. - // - pui8Data += 2; - ui32Count -= 2; - } - - // - // If there is a final byte remaining in the input buffer, then perform a - // single step of the CRC. - // - if(ui32Count != 0) - { - ui32Crc = CRC32_ITER(ui32Crc, *pui8Data); - } - - // - // Return the resulting CRC-32 value. - // - return(ui32Crc); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.c b/bsp/tm4c129x-dk/libraries/driverlib/sysctl.c deleted file mode 100644 index 161b5fa6d7..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.c +++ /dev/null @@ -1,3797 +0,0 @@ -//***************************************************************************** -// -// sysctl.c - Driver for the system controller. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sysctl_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "inc/hw_flash.h" -#include "driverlib/cpu.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" - -//***************************************************************************** -// -// The flash shift used in the math to calculate the flash sector size. -// -//***************************************************************************** -#ifndef FLASH_PP_MAINSS_S -#define FLASH_PP_MAINSS_S 16 -#endif - -//***************************************************************************** -// -// This macro converts the XTAL value provided in the ui32Config parameter to -// an index to the g_pui32Xtals array. -// -//***************************************************************************** -#define SysCtlXtalCfgToIndex(a) ((a & 0x7c0) >> 6) - -//***************************************************************************** -// -// An array that maps the crystal number in RCC to a frequency. -// -//***************************************************************************** -static const uint32_t g_pui32Xtals[] = -{ - 1000000, - 1843200, - 2000000, - 2457600, - 3579545, - 3686400, - 4000000, - 4096000, - 4915200, - 5000000, - 5120000, - 6000000, - 6144000, - 7372800, - 8000000, - 8192000, - 10000000, - 12000000, - 12288000, - 13560000, - 14318180, - 16000000, - 16384000, - 18000000, - 20000000, - 24000000, - 25000000 -}; - -//***************************************************************************** -// -// Maximum number of VCO entries in the g_pui32XTALtoVCO and -// g_pui32VCOFrequencies structures for a device. -// -//***************************************************************************** -#define MAX_VCO_ENTRIES 2 -#define MAX_XTAL_ENTRIES 18 - -//***************************************************************************** -// -// These macros are used in the g_pui32XTALtoVCO table to make it more -// readable. -// -//***************************************************************************** -#define PLL_M_TO_REG(mi, mf) \ - ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S)) -#define PLL_N_TO_REG(n) \ - ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S) -#define PLL_Q_TO_REG(q) \ - ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S) - -//***************************************************************************** -// -// Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers. -// -//***************************************************************************** -static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][3] = -{ - { - // - // VCO 320 MHz - // - { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz - { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz - { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 6 MHz - { PLL_M_TO_REG(52, 85), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz - { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz - { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz - { PLL_M_TO_REG(32, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 12 MHz - { PLL_M_TO_REG(26, 43), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz - { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz - { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz - { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz - { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz - { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(9), PLL_Q_TO_REG(2) }, // 18 MHz - { PLL_M_TO_REG(16, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 24 MHz - { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz - }, - { - // - // VCO 480 MHz - // - { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz - { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6 MHz - { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz - { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz - { PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz - { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz - { PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12 MHz - { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz - { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz - { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz - { PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz - { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 18 MHz - { PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz - { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 24 MHz - { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz - }, -}; - -//***************************************************************************** -// -// The mapping of system clock frequency to flash memory timing parameters. -// -//***************************************************************************** -static const struct -{ - uint32_t ui32Frequency; - uint32_t ui32MemTiming; -} -g_sXTALtoMEMTIM[] = -{ - { 16000000, (SYSCTL_MEMTIM0_FBCHT_0_5 | SYSCTL_MEMTIM0_FBCE | - (0 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_0_5 | SYSCTL_MEMTIM0_EBCE | - (0 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 80000000, (SYSCTL_MEMTIM0_FBCHT_2_5 | (3 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_2_5 | (3 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 100000000, (SYSCTL_MEMTIM0_FBCHT_3 | (4 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_3 | (4 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, - { 120000000, (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | - SYSCTL_MEMTIM0_MB1) }, -}; - -//***************************************************************************** -// -// Get the correct memory timings for a given system clock value. -// -//***************************************************************************** -static uint32_t -_SysCtlMemTimingGet(uint32_t ui32SysClock) -{ - uint_fast8_t ui8Idx; - - // - // Loop through the flash memory timings. - // - for(ui8Idx = 0; - ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0])); - ui8Idx++) - { - // - // See if the system clock frequency is less than the maximum frequency - // for this flash memory timing. - // - if(ui32SysClock <= g_sXTALtoMEMTIM[ui8Idx].ui32Frequency) - { - // - // This flash memory timing is the best choice for the system clock - // frequency, so return it now. - // - return(g_sXTALtoMEMTIM[ui8Idx].ui32MemTiming); - } - } - - // - // An appropriate flash memory timing could not be found, so the device is - // being clocked too fast. Return the default flash memory timing. - // - return(0); -} - -//***************************************************************************** -// -// Calculate the system frequency from the register settings base on the -// oscillator input. -// -//***************************************************************************** -static uint32_t -_SysCtlFrequencyGet(uint32_t ui32Xtal) -{ - uint32_t ui32Result; - uint_fast16_t ui16F1, ui16F2; - uint_fast16_t ui16PInt, ui16PFract; - uint_fast8_t ui8Q, ui8N; - - // - // Extract all of the values from the hardware registers. - // - ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >> - SYSCTL_PLLFREQ0_MFRAC_S); - ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M; - ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >> - SYSCTL_PLLFREQ1_Q_S) + 1); - ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >> - SYSCTL_PLLFREQ1_N_S) + 1); - - // - // Divide the crystal value by N. - // - ui32Xtal /= (uint32_t)ui8N; - - // - // Calculate the multiplier for bits 9:5. - // - ui16F1 = ui16PFract / 32; - - // - // Calculate the multiplier for bits 4:0. - // - ui16F2 = ui16PFract - (ui16F1 * 32); - - // - // Get the integer portion. - // - ui32Result = ui32Xtal * (uint32_t)ui16PInt; - - // - // Add first fractional bits portion(9:0). - // - ui32Result += (ui32Xtal * (uint32_t)ui16F1) / 32; - - // - // Add the second fractional bits portion(4:0). - // - ui32Result += (ui32Xtal * (uint32_t)ui16F2) / 1024; - - // - // Divide the result by Q. - // - ui32Result = ui32Result / (uint32_t)ui8Q; - - // - // Return the resulting PLL frequency. - // - return(ui32Result); -} - -//***************************************************************************** -// -// Look up of the possible VCO frequencies. -// -//***************************************************************************** -static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] = -{ - 160000000, // VCO 320 - 240000000, // VCO 480 -}; - -//***************************************************************************** -// -// The base addresses of the various peripheral control registers. -// -//***************************************************************************** -#define SYSCTL_PPBASE 0x400fe300 -#define SYSCTL_SRBASE 0x400fe500 -#define SYSCTL_RCGCBASE 0x400fe600 -#define SYSCTL_SCGCBASE 0x400fe700 -#define SYSCTL_DCGCBASE 0x400fe800 -#define SYSCTL_PCBASE 0x400fe900 -#define SYSCTL_PRBASE 0x400fea00 - -//***************************************************************************** -// -//! \internal -//! Checks a peripheral identifier. -//! -//! \param ui32Peripheral is the peripheral identifier. -//! -//! This function determines if a peripheral identifier is valid. -//! -//! \return Returns \b true if the peripheral identifier is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_SysCtlPeripheralValid(uint32_t ui32Peripheral) -{ - return((ui32Peripheral == SYSCTL_PERIPH_ADC0) || - (ui32Peripheral == SYSCTL_PERIPH_ADC1) || - (ui32Peripheral == SYSCTL_PERIPH_CAN0) || - (ui32Peripheral == SYSCTL_PERIPH_CAN1) || - (ui32Peripheral == SYSCTL_PERIPH_COMP0) || - (ui32Peripheral == SYSCTL_PERIPH_CCM0) || - (ui32Peripheral == SYSCTL_PERIPH_EEPROM0) || - (ui32Peripheral == SYSCTL_PERIPH_EPHY0) || - (ui32Peripheral == SYSCTL_PERIPH_EMAC0) || - (ui32Peripheral == SYSCTL_PERIPH_EPI0) || - (ui32Peripheral == SYSCTL_PERIPH_FAN0) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOA) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOB) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOC) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOD) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOE) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOF) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOG) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOH) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOJ) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOK) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOL) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOM) || - (ui32Peripheral == SYSCTL_PERIPH_GPION) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOP) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOQ) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOR) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOS) || - (ui32Peripheral == SYSCTL_PERIPH_GPIOT) || - (ui32Peripheral == SYSCTL_PERIPH_HIBERNATE) || - (ui32Peripheral == SYSCTL_PERIPH_I2C0) || - (ui32Peripheral == SYSCTL_PERIPH_I2C1) || - (ui32Peripheral == SYSCTL_PERIPH_I2C2) || - (ui32Peripheral == SYSCTL_PERIPH_I2C3) || - (ui32Peripheral == SYSCTL_PERIPH_I2C4) || - (ui32Peripheral == SYSCTL_PERIPH_I2C5) || - (ui32Peripheral == SYSCTL_PERIPH_I2C6) || - (ui32Peripheral == SYSCTL_PERIPH_I2C7) || - (ui32Peripheral == SYSCTL_PERIPH_I2C8) || - (ui32Peripheral == SYSCTL_PERIPH_I2C9) || - (ui32Peripheral == SYSCTL_PERIPH_LCD0) || - (ui32Peripheral == SYSCTL_PERIPH_PWM0) || - (ui32Peripheral == SYSCTL_PERIPH_PWM1) || - (ui32Peripheral == SYSCTL_PERIPH_QEI0) || - (ui32Peripheral == SYSCTL_PERIPH_QEI1) || - (ui32Peripheral == SYSCTL_PERIPH_SSI0) || - (ui32Peripheral == SYSCTL_PERIPH_SSI1) || - (ui32Peripheral == SYSCTL_PERIPH_SSI2) || - (ui32Peripheral == SYSCTL_PERIPH_SSI3) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER0) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER1) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER2) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER3) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER4) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER5) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER6) || - (ui32Peripheral == SYSCTL_PERIPH_TIMER7) || - (ui32Peripheral == SYSCTL_PERIPH_UART0) || - (ui32Peripheral == SYSCTL_PERIPH_UART1) || - (ui32Peripheral == SYSCTL_PERIPH_UART2) || - (ui32Peripheral == SYSCTL_PERIPH_UART3) || - (ui32Peripheral == SYSCTL_PERIPH_UART4) || - (ui32Peripheral == SYSCTL_PERIPH_UART5) || - (ui32Peripheral == SYSCTL_PERIPH_UART6) || - (ui32Peripheral == SYSCTL_PERIPH_UART7) || - (ui32Peripheral == SYSCTL_PERIPH_UDMA) || - (ui32Peripheral == SYSCTL_PERIPH_USB0) || - (ui32Peripheral == SYSCTL_PERIPH_WDOG0) || - (ui32Peripheral == SYSCTL_PERIPH_WDOG1) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER0) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER1) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER2) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER3) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER4) || - (ui32Peripheral == SYSCTL_PERIPH_WTIMER5)); -} -#endif - -//***************************************************************************** -// -//! Gets the size of the SRAM. -//! -//! This function determines the size of the SRAM on the Tiva device. -//! -//! \return The total number of bytes of SRAM. -// -//***************************************************************************** -uint32_t -SysCtlSRAMSizeGet(void) -{ - return((HWREG(FLASH_SSIZE) + 1) * 256); -} - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! This function determines the size of the flash on the Tiva device. -//! -//! \return The total number of bytes of flash. -// -//***************************************************************************** -uint32_t -SysCtlFlashSizeGet(void) -{ - - // - // TM4C123 devices report the flash size in DC0. - // - if(CLASS_IS_TM4C123) - { - // - // Compute the size of the flash. - // - return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800); - } - else - { - // - // Get the flash size from the FLASH_PP register. - // - return(2048 * ((HWREG(FLASH_PP) & FLASH_PP_SIZE_M) + 1)); - } -} - -//***************************************************************************** -// -//! Gets the size of a single eraseable sector of flash. -//! -//! This function determines the flash sector size on the Tiva device. -//! This size determines the erase granularity of the device flash. -//! -//! \return The number of bytes in a single flash sector. -// -//***************************************************************************** -uint32_t -SysCtlFlashSectorSizeGet(void) -{ - // - // TM4C129 devices store the value in a different register. - // - if(CLASS_IS_TM4C129) - { - // - // Get the flash sector size from the FLASH_PP register. - // - return(1 << (10 + - ((HWREG(FLASH_PP) & - FLASH_PP_MAINSS_M) >> FLASH_PP_MAINSS_S))); - } - else - { - // - // The sector size is fixed at 1KB. - // - return(1024); - } -} - -//***************************************************************************** -// -//! Determines if a peripheral is present. -//! -//! \param ui32Peripheral is the peripheral in question. -//! -//! This function determines if a particular peripheral is present in the -//! device. Each member of the Tiva family has a different peripheral -//! set; this function determines which peripherals are present on this device. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return Returns \b true if the specified peripheral is present and \b false -//! if it is not. -// -//***************************************************************************** -bool -SysCtlPeripheralPresent(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // See if this peripheral is present. - // - return(HWREGBITW(SYSCTL_PPBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff)); -} - -//***************************************************************************** -// -//! Determines if a peripheral is ready. -//! -//! \param ui32Peripheral is the peripheral in question. -//! -//! This function determines if a particular peripheral is ready to be -//! accessed. The peripheral may be in a non-ready state if it is not enabled, -//! is being held in reset, or is in the process of becoming ready after being -//! enabled or taken out of reset. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \note The ability to check for a peripheral being ready varies based on the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine if this feature is available. -//! -//! \return Returns \b true if the specified peripheral is ready and \b false -//! if it is not. -// -//***************************************************************************** -bool -SysCtlPeripheralReady(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // See if this peripheral is ready. - // - return(HWREGBITW(SYSCTL_PRBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff)); -} - -//***************************************************************************** -// -//! Powers on a peripheral. -//! -//! \param ui32Peripheral is the peripheral to be powered on. -//! -//! This function turns on the power to a peripheral. The peripheral continues -//! to receive power even when its clock is not enabled. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC, -//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0 -//! -//! \note The ability to power off a peripheral varies based on the Tiva -//! part in use. Please consult the data sheet for the part you are using to -//! determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralPowerOn(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Power on this peripheral. - // - HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Powers off a peripheral. -//! -//! \param ui32Peripheral is the peripheral to be powered off. -//! -//! This function allows the power to a peripheral to be turned off. The -//! peripheral continues to receive power when its clock is enabled, but -//! the power is removed when its clock is disabled. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC, -//! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0 -//! -//! \note The ability to power off a peripheral varies based on the Tiva -//! part in use. Please consult the data sheet for the part you are using to -//! determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralPowerOff(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Power off this peripheral. - // - HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Performs a software reset of a peripheral. -//! -//! \param ui32Peripheral is the peripheral to reset. -//! -//! This function performs a software reset of the specified peripheral. An -//! individual peripheral reset signal is asserted for a brief period and then -//! de-asserted, returning the internal state of the peripheral to its reset -//! condition. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralReset(uint32_t ui32Peripheral) -{ - volatile uint_fast8_t ui8Delay; - - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Put the peripheral into the reset state. - // - HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; - - // - // Delay for a little bit. - // - for(ui8Delay = 0; ui8Delay < 16; ui8Delay++) - { - } - - // - // Take the peripheral out of the reset state. - // - HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Enables a peripheral. -//! -//! \param ui32Peripheral is the peripheral to enable. -//! -//! This function enables a peripheral. At power-up, all peripherals are -//! disabled; they must be enabled in order to operate or respond to register -//! reads/writes. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \note It takes five clock cycles after the write to enable a peripheral -//! before the the peripheral is actually enabled. During this time, attempts -//! to access the peripheral result in a bus fault. Care should be taken -//! to ensure that the peripheral is not accessed during this brief time -//! period. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral. - // - HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Disables a peripheral. -//! -//! \param ui32Peripheral is the peripheral to disable. -//! -//! This function disables a peripheral. Once disabled, they do not operate or -//! respond to register reads/writes. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral. - // - HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Enables a peripheral in sleep mode. -//! -//! \param ui32Peripheral is the peripheral to enable in sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Because the clocking configuration of the device -//! does not change, any peripheral can safely continue operating while the -//! processor is in sleep mode and can therefore wake the processor from sleep -//! mode. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral in sleep mode. - // - HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Disables a peripheral in sleep mode. -//! -//! \param ui32Peripheral is the peripheral to disable in sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into sleep mode. Disabling peripherals while in sleep mode helps to lower -//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), -//! the peripheral automatically resumes operation when the processor -//! leaves sleep mode, maintaining its entire state from before sleep mode was -//! entered. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral in sleep mode. - // - HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Enables a peripheral in deep-sleep mode. -//! -//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Because the clocking configuration of the -//! device may change, not all peripherals can safely continue operating while -//! the processor is in deep-sleep mode. Those that must run at a particular -//! frequency (such as a UART) do not work as expected if the clock changes. -//! It is the responsibility of the caller to make sensible choices. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral in deep-sleep mode. - // - HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 1; -} - -//***************************************************************************** -// -//! Disables a peripheral in deep-sleep mode. -//! -//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps -//! to lower the current draw of the device, and can keep peripherals that -//! require a particular clock frequency from operating when the clock changes -//! as a result of entering deep-sleep mode. If enabled (via -//! SysCtlPeripheralEnable()), the peripheral automatically resumes -//! operation when the processor leaves deep-sleep mode, maintaining its entire -//! state from before deep-sleep mode was entered. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \e ui32Peripheral parameter must be only one of the following values: -//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0, -//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY, -//! \b SYSCTL_PERIPH_EPI0, -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, -//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, -//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, -//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT, -//! \b SYSCTL_PERIPH_HIBERNATE, -//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2, -//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5, -//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8, -//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0, -//! \b SYSCTL_PERIPH_ONEWIRE0, -//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0, -//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1, -//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, -//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6, -//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, -//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, -//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, -//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, -//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1, -//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3, -//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5 -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral in deep-sleep mode. - // - HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8), - ui32Peripheral & 0xff) = 0; -} - -//***************************************************************************** -// -//! Controls peripheral clock gating in sleep and deep-sleep mode. -//! -//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep -//! peripheral configuration should be used and \b false if not. -//! -//! This function controls how peripherals are clocked when the processor goes -//! into sleep or deep-sleep mode. By default, the peripherals are clocked the -//! same as in run mode; if peripheral clock gating is enabled, they are -//! clocked according to the configuration set by -//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(), -//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPeripheralClockGating(bool bEnable) -{ - if(CLASS_IS_TM4C123) - { - // - // Enable peripheral clock gating as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); - } - } - else - { - // - // Enable peripheral clock gating as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_ACG; - } - else - { - HWREG(SYSCTL_RSCLKCFG) &= ~SYSCTL_RSCLKCFG_ACG; - } - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the system control interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the system -//! control interrupt occurs. -//! -//! This function registers the handler to be called when a system control -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific system control interrupts must be enabled -//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to -//! clear the interrupt source via SysCtlIntClear(). -//! -//! System control can generate interrupts when the PLL achieves lock, if the -//! internal LDO current limit is exceeded, if the internal oscillator fails, -//! if the main oscillator fails, if the internal LDO output voltage droops too -//! much, if the external voltage droops too much, or if the PLL fails. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note The events that cause system control interrupts vary based on the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_SYSCTL_TM4C123, pfnHandler); - - // - // Enable the system control interrupt. - // - IntEnable(INT_SYSCTL_TM4C123); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the system control interrupt. -//! -//! This function unregisters the handler to be called when a system control -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_SYSCTL_TM4C123); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SYSCTL_TM4C123); -} - -//***************************************************************************** -// -//! Enables individual system control interrupt sources. -//! -//! \param ui32Ints is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -//! -//! This function enables the indicated system control interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntEnable(uint32_t ui32Ints) -{ - // - // Enable the specified interrupts. - // - HWREG(SYSCTL_IMC) |= ui32Ints; -} - -//***************************************************************************** -// -//! Disables individual system control interrupt sources. -//! -//! \param ui32Ints is a bit mask of the interrupt sources to be disabled. -//! Must be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -//! -//! This function disables the indicated system control interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntDisable(uint32_t ui32Ints) -{ - // - // Disable the specified interrupts. - // - HWREG(SYSCTL_IMC) &= ~(ui32Ints); -} - -//***************************************************************************** -// -//! Clears system control interrupt sources. -//! -//! \param ui32Ints is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -//! -//! The specified system control interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep it from being called again immediately on exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlIntClear(uint32_t ui32Ints) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSCTL_MISC) = ui32Ints; -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the system controller. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \note The interrupt sources vary based on the Tiva part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK, -//! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK, -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or -//! \b SYSCTL_INT_BOR1. -// -//***************************************************************************** -uint32_t -SysCtlIntStatus(bool bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(SYSCTL_MISC)); - } - else - { - return(HWREG(SYSCTL_RIS)); - } -} - -//***************************************************************************** -// -//! Sets the output voltage of the LDO when the device enters sleep mode. -//! -//! \param ui32Voltage is the required output voltage from the LDO while in -//! sleep mode. -//! -//! This function sets the output voltage of the LDO while in sleep mode. -//! The \e ui32Voltage parameter must be one of the following values: -//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, -//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or -//! \b SYSCTL_LDO_1_20V. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlLDOSleepSet(uint32_t ui32Voltage) -{ - // - // Check the arguments. - // - ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) || - (ui32Voltage == SYSCTL_LDO_0_95V) || - (ui32Voltage == SYSCTL_LDO_1_00V) || - (ui32Voltage == SYSCTL_LDO_1_05V) || - (ui32Voltage == SYSCTL_LDO_1_10V) || - (ui32Voltage == SYSCTL_LDO_1_15V) || - (ui32Voltage == SYSCTL_LDO_1_20V)); - - // - // Set the sleep-mode LDO voltage to the requested value. - // - HWREG(SYSCTL_LDOSPCTL) = ui32Voltage; -} - -//***************************************************************************** -// -//! Returns the output voltage of the LDO when the device enters sleep mode. -//! -//! This function determines the output voltage of the LDO while in sleep mode, -//! as specified by the control register. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return Returns the sleep-mode voltage of the LDO and is one of -//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, -//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or -//! \b SYSCTL_LDO_1_20V. -// -//***************************************************************************** -uint32_t -SysCtlLDOSleepGet(void) -{ - // - // Return the sleep-mode LDO voltage setting. - // - return(HWREG(SYSCTL_LDOSPCTL)); -} - -//***************************************************************************** -// -//! Sets the output voltage of the LDO when the device enters deep-sleep -//! mode. -//! -//! \param ui32Voltage is the required output voltage from the LDO while in -//! deep-sleep mode. -//! -//! This function sets the output voltage of the LDO while in deep-sleep mode. -//! The \e ui32Voltage parameter specifies the output voltage of the LDO and -//! must be one of the following values: \b SYSCTL_LDO_0_90V, -//! \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, \b SYSCTL_LDO_1_05V, -//! \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or \b SYSCTL_LDO_1_20V. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlLDODeepSleepSet(uint32_t ui32Voltage) -{ - // - // Check the arguments. - // - ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) || - (ui32Voltage == SYSCTL_LDO_0_95V) || - (ui32Voltage == SYSCTL_LDO_1_00V) || - (ui32Voltage == SYSCTL_LDO_1_05V) || - (ui32Voltage == SYSCTL_LDO_1_10V) || - (ui32Voltage == SYSCTL_LDO_1_15V) || - (ui32Voltage == SYSCTL_LDO_1_20V)); - - // - // Set the deep-sleep LDO voltage to the requested value. - // - HWREG(SYSCTL_LDODPCTL) = ui32Voltage; -} - -//***************************************************************************** -// -//! Returns the output voltage of the LDO when the device enters deep-sleep -//! mode. -//! -//! This function returns the output voltage of the LDO when the device is -//! in deep-sleep mode, as specified by the control register. -//! -//! \note The availability of this feature, the default LDO voltage, and the -//! adjustment range varies with the Tiva part in use. Please consult the -//! data sheet for the part you are using to determine whether this support is -//! available. -//! -//! \return Returns the deep-sleep-mode voltage of the LDO; is one of -//! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, -//! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or -//! \b SYSCTL_LDO_1_20V. -// -//***************************************************************************** -uint32_t -SysCtlLDODeepSleepGet(void) -{ - // - // Return the deep-sleep-mode LDO voltage setting. - // - return(HWREG(SYSCTL_LDODPCTL)); -} - -//***************************************************************************** -// -//! Configures the power to the flash and SRAM while in sleep mode. -//! -//! \param ui32Config is the required flash and SRAM power configuration. -//! -//! This function allows the power configuration of the flash and SRAM while in -//! sleep mode to be set. The \e ui32Config parameter is the logical OR of the -//! flash power configuration and the SRAM power configuration. -//! -//! The flash power configuration is specified as either: -//! -//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, -//! providing fast wake-up time but higher power consumption. -//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing -//! reduced power consumption but longer wake-up time. -//! -//! The SRAM power configuration is specified as one of: -//! -//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing -//! fast wake-up time but higher power consumption. -//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, -//! providing reduced power consumption but longer wake-up time. -//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, -//! providing further reduced power consumption but longer wake-up time. -//! -//! \note The availability of this feature varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlSleepPowerSet(uint32_t ui32Config) -{ - // - // Set the sleep-mode flash and SRAM power configuration. - // - HWREG(SYSCTL_SLPPWRCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Configures the power to the flash and SRAM while in deep-sleep mode. -//! -//! \param ui32Config is the required flash and SRAM power configuration. -//! -//! This function allows the power configuration of the flash and SRAM while in -//! deep-sleep mode to be set. The \e ui32Config parameter is the logical OR -//! of the flash power configuration and the SRAM power configuration. -//! -//! The flash power configuration is specified as either: -//! -//! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode, -//! providing fast wake-up time but higher power consumption. -//! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing -//! reduced power consumption but longer wake-up time. -//! -//! The SRAM power configuration is specified as one of: -//! -//! - \b SYSCTL_LDO_SLEEP - The LDO is in sleep mode. -//! - \b SYSCTL_TEMP_LOW_POWER - The temperature sensor in low power mode. -//! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing -//! fast wake-up time but higher power consumption. -//! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode, -//! providing reduced power consumption but longer wake-up time. -//! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode, -//! providing further reduced power consumption but longer wake-up time. -//! -//! \note The availability of this feature varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleepPowerSet(uint32_t ui32Config) -{ - // - // Set the deep-sleep-mode flash and SRAM power configuration. - // - HWREG(SYSCTL_DSLPPWRCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Resets the device. -//! -//! This function performs a software reset of the entire device. The -//! processor and all peripherals are reset and all device registers are -//! returned to their default values (with the exception of the reset cause -//! register, which maintains its current value but has the software reset -//! bit set as well). -//! -//! \return This function does not return. -// -//***************************************************************************** -void -SysCtlReset(void) -{ - // - // Perform a software reset request. This request causes the device to - // reset, no further code is executed. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; - - // - // The device should have reset, so this should never be reached. Just in - // case, loop forever. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! Puts the processor into sleep mode. -//! -//! This function places the processor into sleep mode; it does not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the -//! processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlSleep(void) -{ - // - // Wait for an interrupt. - // - CPUwfi(); -} - -//***************************************************************************** -// -//! Puts the processor into deep-sleep mode. -//! -//! This function places the processor into deep-sleep mode; it does not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up -//! the processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleep(void) -{ - // - // Enable deep-sleep. - // - HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; - - // - // Wait for an interrupt. - // - CPUwfi(); - - // - // Disable deep-sleep so that a future sleep works correctly. - // - HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); -} - -//***************************************************************************** -// -//! Gets the reason for a reset. -//! -//! This function returns the reason(s) for a reset. Because the reset -//! reasons are sticky until either cleared by software or a power-on reset, -//! multiple reset reasons may be returned if multiple resets have occurred. -//! The reset reason is a logical OR of \b SYSCTL_CAUSE_HSRVREQ, -//! \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, \b SYSCTL_CAUSE_SW, -//! \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, -//! and/or \b SYSCTL_CAUSE_EXT. -//! -//! \return Returns the reason(s) for a reset. -// -//***************************************************************************** -uint32_t -SysCtlResetCauseGet(void) -{ - // - // Return the reset reasons. - // - return(HWREG(SYSCTL_RESC)); -} - -//***************************************************************************** -// -//! Clears reset reasons. -//! -//! \param ui32Causes are the reset causes to be cleared; must be a logical OR -//! of \b SYSCTL_CAUSE_HSRVREQ, \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, -//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, -//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. -//! -//! This function clears the specified sticky reset reasons. Once cleared, -//! another reset for the same reason can be detected, and a reset for a -//! different reason can be distinguished (instead of having two reset causes -//! set). If the reset reason is used by an application, all reset causes -//! should be cleared after they are retrieved with SysCtlResetCauseGet(). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlResetCauseClear(uint32_t ui32Causes) -{ - // - // Clear the given reset reasons. - // - HWREG(SYSCTL_RESC) &= ~(ui32Causes); -} - -//***************************************************************************** -// -//! Provides a small delay. -//! -//! \param ui32Count is the number of delay loop iterations to perform. -//! -//! This function provides a means of generating a delay by executing a simple -//! 3 instruction cycle loop a given number of times. It is written in -//! assembly to keep the loop instruction count consistent across tool chains. -//! -//! It is important to note that this function does NOT provide an accurate -//! timing mechanism. Although the delay loop is 3 instruction cycles long, -//! the execution time of the loop will vary dramatically depending upon the -//! application's interrupt environment (the loop will be interrupted unless -//! run with interrupts disabled and this is generally an unwise thing to do) -//! and also the current system clock rate and flash timings (wait states and -//! the operation of the prefetch buffer affect the timing). -//! -//! For better accuracy, the ROM version of this function may be used. This -//! version will not suffer from flash- and prefect buffer-related timing -//! variability but will still be delayed by interrupt service routines. -//! -//! For best accuracy, a system timer should be used with code either polling -//! for a particular timer value being exceeded or processing the timer -//! interrupt to determine when a particular time period has elapsed. -//! -//! \return None. -// -//***************************************************************************** -#if defined(ewarm) || defined(DOXYGEN) -void -SysCtlDelay(uint32_t ui32Count) -{ - __asm(" subs r0, #1\n" - " bne.n SysCtlDelay\n" - " bx lr"); -} -#endif -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -void __attribute__((naked)) -SysCtlDelay(uint32_t ui32Count) -{ - __asm(" subs r0, #1\n" - " bne SysCtlDelay\n" - " bx lr"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -SysCtlDelay(uint32_t ui32Count) -{ - subs r0, #1; - bne SysCtlDelay; - bx lr; -} -#endif -// -// For CCS implement this function in pure assembly. This prevents the TI -// compiler from doing funny things with the optimizer. -// -#if defined(ccs) -__asm(" .sect \".text:SysCtlDelay\"\n" - " .clink\n" - " .thumbfunc SysCtlDelay\n" - " .thumb\n" - " .global SysCtlDelay\n" - "SysCtlDelay:\n" - " subs r0, #1\n" - " bne.n SysCtlDelay\n" - " bx lr\n"); -#endif - -//***************************************************************************** -// -//! Sets the configuration of the main oscillator (MOSC) control. -//! -//! \param ui32Config is the required configuration of the MOSC control. -//! -//! This function configures the control of the main oscillator. The -//! \e ui32Config is specified as the logical OR of the following values: -//! -//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that -//! detects a failure of the main oscillator (such as a loss of the clock). -//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an -//! interrupt instead of resetting the processor. -//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal or oscillator -//! connected to the OSC0/OSC1 pins, allowing power consumption to be -//! reduced. -//! - \b SYSCTL_MOSC_PWR_DIS disable power to the main oscillator. If this -//! parameter is not specified, the MOSC input remains powered. -//! - \b SYSCTL_MOSC_LOWFREQ MOSC is less than 10 MHz. -//! - \b SYSCTL_MOSC_HIGHFREQ MOSC is greater than 10 MHz. -//! - \b SYSCTL_MOSC_SESRC specifies that the MOSC is a single-ended -//! oscillator connected to OSC0. If this parameter is not specified, the -//! input is assumed to be a crystal. -//! -//! \note The availability of MOSC control varies based on the Tiva part -//! in use. Please consult the data sheet for the part you are using to -//! determine whether this support is available. In addition, the capability -//! of MOSC control varies based on the Tiva part in use. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlMOSCConfigSet(uint32_t ui32Config) -{ - // - // Configure the MOSC control. - // - HWREG(SYSCTL_MOSCCTL) = ui32Config; -} - -//***************************************************************************** -// -//! Calibrates the precision internal oscillator. -//! -//! \param ui32Type is the type of calibration to perform. -//! -//! This function performs a calibration of the PIOSC. There are three types -//! of calibration available; the desired calibration type as specified in -//! \e ui32Type is one of: -//! -//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the -//! 32-kHz clock from the hibernate module as a reference. This type is -//! only possible on parts that have a hibernate module, and then only if -//! it is enabled, a 32.768-kHz clock source is attached to the XOSC0/1 -//! pins and the hibernate module's RTC is also enabled. -//! -//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory -//! provided calibration. -//! -//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied -//! value. The value to be used is ORed into the lower 7-bits of this value, -//! with 0x40 being the ``nominal'' value (in other words, if everything were -//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40 -//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC. -//! -//! \return Returns 1 if the calibration was successful and 0 if it failed. -// -//***************************************************************************** -uint32_t -SysCtlPIOSCCalibrate(uint32_t ui32Type) -{ - // - // Perform the requested calibration. If performing user calibration, the - // UTEN bit must be set with one write, then the UT field in a second - // write, and the UPDATE bit in a final write. For other calibration - // types, a single write to set UPDATE or CAL is all that is required. - // - if(ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE)) - { - HWREG(SYSCTL_PIOSCCAL) = ui32Type & SYSCTL_PIOSCCAL_UTEN; - HWREG(SYSCTL_PIOSCCAL) = - ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M); - } - HWREG(SYSCTL_PIOSCCAL) = ui32Type; - - // - // See if an automatic calibration was requested. - // - if(ui32Type & SYSCTL_PIOSCCAL_CAL) - { - // - // Wait for the automatic calibration to complete. - // - while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0) - { - } - - // - // If the automatic calibration failed, return an error. - // - if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) != - SYSCTL_PIOSCSTAT_CRPASS) - { - return(0); - } - } - - // - // The calibration was successful. - // - return(1); -} - -//***************************************************************************** -// -//! Sets the type of reset issued due to certain reset events. -//! -//! \param ui32Behavior specifies the types of resets for each of the -//! configurable reset events. -//! -//! This function sets the types of reset issued when a configurable reset -//! event occurs. The reset events that are configurable are: Watchdog 0 or 1, -//! a brown out and the external RSTn pin. The valid actions are either a -//! system reset or a full POR sequence. See the data sheet for more -//! information on the differences between a full POR and a system reset. All -//! reset behaviors can be configured with a single call using the logical OR -//! of the values defined below. Any reset option that is not specifically set -//! remains configured for its default behavior. Either POR or system reset -//! can be selected for each reset cause. -//! -//! Valid values are logical combinations of the following: -//! -//! - \b SYSCTL_ONRST_WDOG0_POR configures a Watchdog 0 reset to perform a full -//! POR. -//! - \b SYSCTL_ONRST_WDOG0_SYS configures a Watchdog 0 reset to perform a -//! system reset. -//! - \b SYSCTL_ONRST_WDOG1_POR configures a Watchdog 1 reset to perform a full -//! POR. -//! - \b SYSCTL_ONRST_WDOG1_SYS configures a Watchdog 1 reset to perform a -//! system reset. -//! - \b SYSCTL_ONRST_BOR_POR configures a brown-out reset to perform a full -//! POR. -//! - \b SYSCTL_ONRST_BOR_SYS configures a brown-out reset to perform a system -//! reset. -//! - \b SYSCTL_ONRST_EXT_POR configures an external pin reset to perform a -//! full POR. -//! - \b SYSCTL_ONRST_EXT_SYS configures an external pin reset to perform a -//! system reset. -//! -//! \b Example: Set Watchdog 0 reset to trigger a POR and a brown-out reset -//! to trigger a system reset while leaving the remaining resets with their -//! default behaviors. -//! -//! \verbatim -//! SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_POR | SYSCTL_ONRST_BOR_SYS); -//! \endverbatim -//! -//! \note This function cannot be used with TM4C123 devices. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlResetBehaviorSet(uint32_t ui32Behavior) -{ - HWREG(SYSCTL_RESBEHAVCTL) = ui32Behavior; -} - -//***************************************************************************** -// -//! Returns the current types of reset issued due to reset events. -//! -//! This function returns the types of resets issued when a configurable reset -//! occurs. The value returned is a logical OR combination of the valid values -//! that are described in the documentation for the \e ui32Behavior parameter -//! of the SysCtlResetBehaviorSet() function. -//! -//! \note This function should only be used with Flurry-class devices. -//! -//! \return The reset behaviors for all configurable resets. -// -//***************************************************************************** -uint32_t -SysCtlResetBehaviorGet(void) -{ - return(HWREG(SYSCTL_RESBEHAVCTL)); -} - -//***************************************************************************** -// -//! Configures the system clock. -//! -//! \param ui32Config is the required configuration of the device clocking. -//! \param ui32SysClock is the requested processor frequency. -//! -//! This function configures the main system clocking for the device. The -//! input frequency, oscillator source, whether or not to enable the PLL, and -//! the system clock divider are all configured with this function. This -//! function configures the system frequency to the closest available divisor -//! of one of the fixed PLL VCO settings provided in the \e ui32Config -//! parameter. The caller sets the \e ui32SysClock parameter to request the -//! system clock frequency, and this function then attempts to match this using -//! the values provided in the \e ui32Config parameter. If this function -//! cannot exactly match the requested frequency, it picks the closest -//! frequency that is lower than the requested frequency. The \e ui32Config -//! parameter provides the remaining configuration options using a set of -//! defines that are a logical OR of several different values, many of which -//! are grouped into sets where only one of the set can be chosen. This -//! function returns the current system frequency which may not match the -//! requested frequency. -//! -//! If the application is using an external crystal then the frequency is -//! set by using one of the following values: -//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_8MHZ, -//! \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, \b SYSCTL_XTAL_16MHZ, -//! \b SYSCTL_XTAL_18MHZ, \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or -//! \b SYSCTL_XTAL_25MHz. -//! -//! The oscillator source is chosen with one of the following values: -//! -//! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator. -//! - \b SYSCTL_OSC_INT to use the 16-MHz precision internal oscillator. -//! - \b SYSCTL_OSC_INT30 to use the internal low frequency oscillator. -//! - \b SYSCTL_OSC_EXT32 to use the hibernate modules 32.786-kHz oscillator. -//! This option is only available on devices that include the hibernation -//! module. -//! -//! The system clock source is chosen with one of the following values: -//! -//! - \b SYSCTL_USE_PLL is used to select the PLL output as the system clock. -//! - \b SYSCTL_USE_OSC is used to choose one of the oscillators as the -//! system clock. -//! -//! The PLL VCO frequency is chosen with one of the the following values: -//! -//! - \b SYSCTL_CFG_VCO_480 to set the PLL VCO output to 480-MHz -//! - \b SYSCTL_CFG_VCO_320 to set the PLL VCO output to 320-MHz -//! -//! Example: Configure the system clocking to be 40 MHz with a 320-MHz PLL -//! setting using the 16-MHz internal oscillator. -//! -//! \verbatim -//! SysCtlClockFreqSet(SYSCTL_OSC_INT | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320, -//! 40000000); -//! \endverbatim -//! -//! \note This function cannot be used with TM4C123 devices. For TM4C123 -//! devices use the SysCtlClockSet() function. -//! -//! \return The actual configured system clock frequency in Hz or zero if the -//! value could not be changed due to a parameter error or PLL lock failure. -// -//***************************************************************************** -uint32_t -SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) -{ - int32_t i32Timeout, i32VCOIdx, i32XtalIdx; - uint32_t ui32MOSCCTL; - uint32_t ui32Delay; - uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig; - - // - // TM4C123 devices should not use this function. - // - if(CLASS_IS_TM4C123) - { - return(0); - } - - // - // Get the index of the crystal from the ui32Config parameter. - // - i32XtalIdx = SysCtlXtalCfgToIndex(ui32Config); - - // - // Determine which non-PLL source was selected. - // - if((ui32Config & 0x38) == SYSCTL_OSC_INT) - { - // - // Use the nominal frequency for the PIOSC oscillator and set the - // crystal select. - // - ui32Osc = 16000000; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; - ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_PIOSC; - - // - // Force the crystal index to the value for 16-MHz. - // - i32XtalIdx = SysCtlXtalCfgToIndex(SYSCTL_XTAL_16MHZ); - } - else if((ui32Config & 0x38) == SYSCTL_OSC_INT30) - { - // - // Use the nominal frequency for the low frequency oscillator. - // - ui32Osc = 30000; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_LFIOSC; - } - else if((ui32Config & 0x38) == (SYSCTL_OSC_EXT32 & 0x38)) - { - // - // Use the RTC frequency. - // - ui32Osc = 32768; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_RTC; - } - else if((ui32Config & 0x38) == SYSCTL_OSC_MAIN) - { - // - // Bounds check the source frequency for the main oscillator. The is - // because the PLL tables in the g_pppui32XTALtoVCO structure range - // from 5MHz to 25MHz. - // - if((i32XtalIdx > (SysCtlXtalCfgToIndex(SYSCTL_XTAL_25MHZ))) || - (i32XtalIdx < (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ)))) - { - return(0); - } - - ui32Osc = g_pui32Xtals[i32XtalIdx]; - - // - // Set the PLL source select to MOSC. - // - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_MOSC; - ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_MOSC; - - // - // Clear MOSC power down, high oscillator range setting, and no crystal - // present setting. - // - ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) & - ~(SYSCTL_MOSCCTL_OSCRNG | SYSCTL_MOSCCTL_PWRDN | - SYSCTL_MOSCCTL_NOXTAL); - - // - // Increase the drive strength for MOSC of 10 MHz and above. - // - if(i32XtalIdx >= (SysCtlXtalCfgToIndex(SYSCTL_XTAL_10MHZ) - - (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ)))) - { - ui32MOSCCTL |= SYSCTL_MOSCCTL_OSCRNG; - } - - HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; - - // - // Timeout using the legacy delay value. - // - ui32Delay = 524288; - - while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) - { - ui32Delay--; - - if(ui32Delay == 0) - { - break; - } - } - - // - // If the main oscillator failed to start up then do not switch to - // it and return. - // - if(ui32Delay == 0) - { - return(0); - } - - - } - else - { - // - // This was an invalid request because no oscillator source was - // indicated. - // - ui32Osc = 0; - ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; - } - - // - // Check if the running with the PLL enabled was requested. - // - if((ui32Config & SYSCTL_USE_OSC) == SYSCTL_USE_PLL) - { - // - // ui32Config must be SYSCTL_OSC_MAIN or SYSCTL_OSC_INT. - // - if(((ui32Config & 0x38) != SYSCTL_OSC_MAIN) && - ((ui32Config & 0x38) != SYSCTL_OSC_INT)) - { - return(0); - } - - // - // Get the VCO index out of the ui32Config parameter. - // - i32VCOIdx = (ui32Config >> 24) & 7; - - // - // Check that the VCO index is not out of bounds. - // - ASSERT(i32VCOIdx < MAX_VCO_ENTRIES); - - // - // Set the memory timings for the maximum external frequency since - // this could be a switch to PIOSC or possibly to MOSC which can be - // up to 25MHz. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(25000000); - - // - // Clear the old PLL divider and source in case it was set. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) & - ~(SYSCTL_RSCLKCFG_PSYSDIV_M | - SYSCTL_RSCLKCFG_OSCSRC_M | - SYSCTL_RSCLKCFG_PLLSRC_M | SYSCTL_RSCLKCFG_USEPLL); - - // - // Update the memory timings to match running from PIOSC. - // - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Update clock configuration to switch back to PIOSC. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - - // - // The table starts at 5 MHz so modify the index to match this. - // - i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ); - - // - // Calculate the System divider such that we get a frequency that is - // the closest to the requested frequency without going over. - // - ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) / - ui32SysClock; - - // - // Set the oscillator source. - // - HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; - - // - // Set the M, N and Q values provided from the table and preserve - // the power state of the main PLL. - // - HWREG(SYSCTL_PLLFREQ1) = - g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]; - HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); - HWREG(SYSCTL_PLLFREQ0) = - (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] | - (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)); - - // - // Calculate the actual system clock as PSYSDIV is always div-by 2. - // - ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2; - - // - // Set the Flash and EEPROM timing values. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); - - // - // Check if the PLL is already powered up. - // - if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR) - { - // - // Trigger the PLL to lock to the new frequency. - // - HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ; - } - else - { - // - // Power up the PLL. - // - HWREG(SYSCTL_PLLFREQ0) |= SYSCTL_PLLFREQ0_PLLPWR; - } - - // - // Wait until the PLL has locked. - // - for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--) - { - if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK)) - { - break; - } - } - - // - // If the loop above did not timeout then switch over to the PLL - // - if(i32Timeout) - { - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) | - ui32OscSelect | SYSCTL_RSCLKCFG_USEPLL; - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Set the new clock configuration. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - } - else - { - ui32SysClock = 0; - } - } - else - { - // - // Set the Flash and EEPROM timing values for PIOSC. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000); - - // - // Make sure that the PLL is powered down since it is not being used. - // - HWREG(SYSCTL_PLLFREQ0) &= ~SYSCTL_PLLFREQ0_PLLPWR; - - // - // Clear the old PLL divider and source in case it was set. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M | - SYSCTL_RSCLKCFG_OSCSRC_M | - SYSCTL_RSCLKCFG_USEPLL); - - // - // Update the memory timings. - // - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Set the new clock configuration. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - - // - // If zero given as the system clock then default to divide by 1. - // - if(ui32SysClock == 0) - { - ui32SysDiv = 0; - } - else - { - // - // Calculate the System divider based on the requested - // frequency. - // - ui32SysDiv = ui32Osc / ui32SysClock; - - // - // If the system divisor is not already zero, subtract one to - // set the value in the register which requires the value to - // be n-1. - // - if(ui32SysDiv != 0) - { - ui32SysDiv -= 1; - } - - // - // Calculate the system clock. - // - ui32SysClock = ui32Osc / (ui32SysDiv + 1); - } - - // - // Set the memory timing values for the new system clock. - // - HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); - - // - // Set the new system clock values. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig |= (ui32SysDiv << SYSCTL_RSCLKCFG_OSYSDIV_S) | - ui32OscSelect; - - // - // Update the memory timings. - // - ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; - - // - // Set the new clock configuration. - // - HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; - } - - // - // Finally change the OSCSRC back to PIOSC - // - HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M); - - return(ui32SysClock); -} - -//***************************************************************************** -// -//! Sets the clocking of the device. -//! -//! \param ui32Config is the required configuration of the device clocking. -//! -//! This function configures the clocking of the device. The input crystal -//! frequency, oscillator to be used, use of the PLL, and the system clock -//! divider are all configured with this function. -//! -//! The \e ui32Config parameter is the logical OR of several different values, -//! many of which are grouped into sets where only one can be chosen. -//! -//! The system clock divider is chosen with one of the following values: -//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... -//! \b SYSCTL_SYSDIV_64. -//! -//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or -//! \b SYSCTL_USE_OSC. -//! -//! The external crystal frequency is chosen with one of the following values: -//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, -//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, -//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, -//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, -//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, -//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, -//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. -//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in -//! operation. -//! -//! The oscillator source is chosen with one of the following values: -//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, -//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only -//! available on devices with the hibernate module, and then only when the -//! hibernate module has been enabled. -//! -//! The internal and main oscillators are disabled with the -//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. -//! The external oscillator must be enabled in order to use an external clock -//! source. Note that attempts to disable the oscillator used to clock the -//! device is prevented by the hardware. -//! -//! To clock the system from an external source (such as an external crystal -//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the -//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | -//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use -//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate -//! crystal with one of the \b SYSCTL_XTAL_xxx values. -//! -//! \note This function should only be called on TM4C123 devices. For -//! all other devices use the SysCtlClockFreqSet() function. -//! -//! \note If selecting the PLL as the system clock source (that is, via -//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to -//! determine when the PLL has locked. If an interrupt handler for the -//! system control interrupt is in place, and it responds to and clears the -//! PLL lock interrupt, this function delays until its timeout has occurred -//! instead of completing as soon as PLL lock is achieved. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlClockSet(uint32_t ui32Config) -{ - uint32_t ui32Delay, ui32RCC, ui32RCC2; - - // - // Get the current value of the RCC and RCC2 registers. - // - ui32RCC = HWREG(SYSCTL_RCC); - ui32RCC2 = HWREG(SYSCTL_RCC2); - - // - // Bypass the PLL and system clock dividers for now. - // - ui32RCC |= SYSCTL_RCC_BYPASS; - ui32RCC &= ~(SYSCTL_RCC_USESYSDIV); - ui32RCC2 |= SYSCTL_RCC2_BYPASS2; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - - // - // See if the oscillator needs to be enabled. - // - if((ui32RCC & SYSCTL_RCC_MOSCDIS) && !(ui32Config & SYSCTL_MAIN_OSC_DIS)) - { - // - // Make sure that the required oscillators are enabled. For now, the - // previously enabled oscillators must be enabled along with the newly - // requested oscillators. - // - ui32RCC &= (~SYSCTL_RCC_MOSCDIS | (ui32Config & SYSCTL_MAIN_OSC_DIS)); - - // - // Clear the MOSC power up raw interrupt status to be sure it is not - // set when waiting below. - // - HWREG(SYSCTL_MISC) = SYSCTL_MISC_MOSCPUPMIS; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - - // - // Timeout using the legacy delay value. - // - ui32Delay = 524288; - - while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) - { - ui32Delay--; - - if(ui32Delay == 0) - { - break; - } - } - - // - // If the main oscillator failed to start up then do not switch to - // it and return. - // - if(ui32Delay == 0) - { - return; - } - - } - - // - // Set the new crystal value and oscillator source. Because the OSCSRC2 - // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a - // special encoding within ui32Config to avoid the overlap. - // - ui32RCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); - ui32RCC |= ui32Config & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M); - ui32RCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M); - ui32RCC2 |= ui32Config & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M); - ui32RCC2 |= (ui32Config & 0x00000008) << 3; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - - // - // Set the PLL configuration. - // - ui32RCC &= ~SYSCTL_RCC_PWRDN; - ui32RCC |= ui32Config & SYSCTL_RCC_PWRDN; - ui32RCC2 &= ~SYSCTL_RCC2_PWRDN2; - ui32RCC2 |= ui32Config & SYSCTL_RCC2_PWRDN2; - - // - // Clear the PLL lock interrupt. - // - HWREG(SYSCTL_MISC) = SYSCTL_MISC_PLLLMIS; - - // - // Write the new RCC value. - // - if(ui32RCC2 & SYSCTL_RCC2_USERCC2) - { - HWREG(SYSCTL_RCC2) = ui32RCC2; - HWREG(SYSCTL_RCC) = ui32RCC; - } - else - { - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - } - - // - // Set the requested system divider and disable the appropriate - // oscillators. This value is not written immediately. - // - ui32RCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | - SYSCTL_RCC_MOSCDIS); - ui32RCC |= ui32Config & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV | - SYSCTL_RCC_MOSCDIS); - ui32RCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M); - ui32RCC2 |= ui32Config & SYSCTL_RCC2_SYSDIV2_M; - if(ui32Config & SYSCTL_RCC2_DIV400) - { - ui32RCC |= SYSCTL_RCC_USESYSDIV; - ui32RCC2 &= ~(SYSCTL_RCC_USESYSDIV); - ui32RCC2 |= ui32Config & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB); - } - else - { - ui32RCC2 &= ~(SYSCTL_RCC2_DIV400); - } - - // - // See if the PLL output is being used to clock the system. - // - if(!(ui32Config & SYSCTL_RCC_BYPASS)) - { - // - // Wait until the PLL has locked. - // - for(ui32Delay = 32768; ui32Delay > 0; ui32Delay--) - { - if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK)) - { - break; - } - } - - // - // Enable use of the PLL. - // - ui32RCC &= ~(SYSCTL_RCC_BYPASS); - ui32RCC2 &= ~(SYSCTL_RCC2_BYPASS2); - } - - // - // Write the final RCC value. - // - HWREG(SYSCTL_RCC) = ui32RCC; - HWREG(SYSCTL_RCC2) = ui32RCC2; - - // - // Delay for a little bit so that the system divider takes effect. - // - SysCtlDelay(16); -} - -//***************************************************************************** -// -//! Gets the processor clock rate. -//! -//! This function determines the clock rate of the processor clock, which is -//! also the clock rate of the peripheral modules (with the exception of -//! PWM, which has its own clock divider; other peripherals may have different -//! clocking, see the device data sheet for details). -//! -//! \note This cannot return accurate results if SysCtlClockSet() has not -//! been called to configure the clocking of the device, or if the device is -//! directly clocked from a crystal (or a clock source) that is not one of the -//! supported crystal frequencies. In the latter case, this function should be -//! modified to directly return the correct system clock rate. -//! -//! \note This function can only be called on TM4C123 devices. For TM4C129 -//! devices, the return value from SysCtlClockFreqSet() indicates the system -//! clock frequency. -//! -//! \return The processor clock rate for TM4C123 devices only. -// -//***************************************************************************** -uint32_t -SysCtlClockGet(void) -{ - uint32_t ui32RCC, ui32RCC2, ui32PLL, ui32Clk, ui32Max; - uint32_t ui32PLL1; - - // - // This function is only valid on TM4C123 devices. - // - ASSERT(CLASS_IS_TM4C123); - - // - // Read RCC and RCC2. - // - ui32RCC = HWREG(SYSCTL_RCC); - ui32RCC2 = HWREG(SYSCTL_RCC2); - - // - // Get the base clock rate. - // - switch((ui32RCC2 & SYSCTL_RCC2_USERCC2) ? - (ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) : - (ui32RCC & SYSCTL_RCC_OSCSRC_M)) - { - // - // The main oscillator is the clock source. Determine its rate from - // the crystal setting field. - // - case SYSCTL_RCC_OSCSRC_MAIN: - { - ui32Clk = g_pui32Xtals[(ui32RCC & SYSCTL_RCC_XTAL_M) >> - SYSCTL_RCC_XTAL_S]; - break; - } - - // - // The internal oscillator is the source clock. - // - case SYSCTL_RCC_OSCSRC_INT: - { - // - // The internal oscillator on all devices is 16 MHz. - // - ui32Clk = 16000000; - break; - } - - // - // The internal oscillator divided by four is the source clock. - // - case SYSCTL_RCC_OSCSRC_INT4: - { - // - // The internal oscillator on all devices is 16 MHz. - // - ui32Clk = 16000000 / 4; - break; - } - - // - // The internal 30-KHz oscillator is the source clock. - // - case SYSCTL_RCC_OSCSRC_30: - { - // - // The internal 30-KHz oscillator has an accuracy of +/- 30%. - // - ui32Clk = 30000; - break; - } - - // - // The 32.768-KHz clock from the hibernate module is the source clock. - // - case SYSCTL_RCC2_OSCSRC2_32: - { - ui32Clk = 32768; - break; - } - - // - // An unknown setting, so return a zero clock (that is, an unknown - // clock rate). - // - default: - { - return(0); - } - } - - // - // Default the maximum frequency to the maximum 32-bit unsigned value. - // - ui32Max = 0xffffffff; - - // - // See if the PLL is being used. - // - if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) && - !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) || - (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && !(ui32RCC & SYSCTL_RCC_BYPASS))) - { - // - // Read the two PLL frequency registers. The formula for a - // TM4C123 device is "(xtal * m) / ((q + 1) * (n + 1))". - // - ui32PLL = HWREG(SYSCTL_PLLFREQ0); - ui32PLL1 = HWREG(SYSCTL_PLLFREQ1); - - // - // Divide the input clock by the dividers. - // - ui32Clk /= ((((ui32PLL1 & SYSCTL_PLLFREQ1_Q_M) >> - SYSCTL_PLLFREQ1_Q_S) + 1) * - (((ui32PLL1 & SYSCTL_PLLFREQ1_N_M) >> - SYSCTL_PLLFREQ1_N_S) + 1) * 2); - - // - // Multiply the clock by the multiplier, which is split into an - // integer part and a fractional part. - // - ui32Clk = ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MINT_M) >> - SYSCTL_PLLFREQ0_MINT_S)) + - ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MFRAC_M) >> - SYSCTL_PLLFREQ0_MFRAC_S)) >> 10)); - - // - // Force the system divider to be enabled. It is always used when - // using the PLL, but in some cases it does not read as being enabled. - // - ui32RCC |= SYSCTL_RCC_USESYSDIV; - - // - // Calculate the maximum system frequency. - // - switch(HWREG(SYSCTL_DC1) & SYSCTL_DC1_MINSYSDIV_M) - { - case SYSCTL_DC1_MINSYSDIV_80: - { - ui32Max = 80000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_50: - { - ui32Max = 50000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_40: - { - ui32Max = 40000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_25: - { - ui32Max = 25000000; - break; - } - case SYSCTL_DC1_MINSYSDIV_20: - { - ui32Max = 20000000; - break; - } - default: - { - break; - } - } - } - - // - // See if the system divider is being used. - // - if(ui32RCC & SYSCTL_RCC_USESYSDIV) - { - // - // Adjust the clock rate by the system clock divider. - // - if(ui32RCC2 & SYSCTL_RCC2_USERCC2) - { - if((ui32RCC2 & SYSCTL_RCC2_DIV400) && - (((ui32RCC2 & SYSCTL_RCC2_USERCC2) && - !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) || - (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && - !(ui32RCC & SYSCTL_RCC_BYPASS)))) - - { - ui32Clk = ((ui32Clk * 2) / (((ui32RCC2 & - (SYSCTL_RCC2_SYSDIV2_M | - SYSCTL_RCC2_SYSDIV2LSB)) >> - (SYSCTL_RCC2_SYSDIV2_S - 1)) + - 1)); - } - else - { - ui32Clk /= (((ui32RCC2 & SYSCTL_RCC2_SYSDIV2_M) >> - SYSCTL_RCC2_SYSDIV2_S) + 1); - } - } - else - { - ui32Clk /= (((ui32RCC & SYSCTL_RCC_SYSDIV_M) >> - SYSCTL_RCC_SYSDIV_S) + 1); - } - } - - // - // Limit the maximum clock to the maximum clock frequency. - // - if(ui32Max < ui32Clk) - { - ui32Clk = ui32Max; - } - - // - // Return the computed clock rate. - // - return(ui32Clk); -} - -//***************************************************************************** -// -//! Sets the clocking of the device while in deep-sleep mode. -//! -//! \param ui32Config is the required configuration of the device clocking -//! while in deep-sleep mode. -//! -//! This function configures the clocking of the device while in deep-sleep -//! mode. The oscillator to be used and the system clock divider are -//! configured with this function. -//! -//! The \e ui32Config parameter is the logical OR of the following values: -//! -//! The system clock divider is chosen from one of the following values: -//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ... -//! \b SYSCTL_DSLP_DIV_64. -//! -//! The oscillator source is chosen from one of the following values: -//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, -//! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on -//! devices with the hibernation module, and then only when the hibernation -//! module has been enabled. -//! -//! The precision internal oscillator can be powered down in deep-sleep mode by -//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is -//! not powered down if it is required for operation while in deep-sleep -//! (based on other configuration settings.) -//! -//! \note This function should only be called on TM4C123 devices. For -//! other devices use the SysCtlDeepSleepClockConfigSet() function. -//! -//! \note The availability of deep-sleep clocking configuration varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleepClockSet(uint32_t ui32Config) -{ - // - // Set the deep-sleep clock configuration. - // - HWREG(SYSCTL_DSLPCLKCFG) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the clock configuration of the device while in deep-sleep mode. -//! -//! \param ui32Div is the clock divider when in deep-sleep mode. -//! \param ui32Config is the configuration of the device clocking while -//! in deep-sleep mode. -//! -//! This function configures the clocking of the device while in deep-sleep -//! mode. The \e ui32Config parameter selects the oscillator and the -//! \e ui32Div parameter sets the clock divider used in deep-sleep mode. The -//! valid values for the \e ui32Div parameter range from 1 to 1024, however not -//! all Tiva microcontrollers support this full range. This function -//! replaces the SysCtlDeepSleepClockSet() function and can be used on -//! Tiva devices that support deep-sleep mode. -//! -//! The oscillator source is chosen from one of the following values: -//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30, -//! or \b SYSCTL_DSLP_OSC_EXT32. The \b SYSCTL_DSLP_OSC_EXT32 option is only -//! available on devices with the hibernation module, and then only when the -//! hibernation module is enabled. -//! -//! The precision internal oscillator can be powered down in deep-sleep mode by -//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is -//! not powered down if it is required for operation while in deep-sleep -//! (based on other configuration settings). -//! -//! The main oscillator can be powered down in deep-sleep mode by -//! specifying \b SYSCTL_DSLP_MOSC_PD. The main oscillator is -//! not powered down if it is required for operation while in deep-sleep -//! (based on other configuration settings). -//! -//! \note The availability of deep-sleep clocking configuration and the -//! configuration values vary with the Tiva device in use. Please consult -//! the data sheet for the device you are using to determine whether the -//! desired configuration options are available and to determine the valid -//! range for the clock divider. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, uint32_t ui32Config) -{ - uint32_t ui32Value; - - ASSERT(ui32Div != 0); - - if(CLASS_IS_TM4C123) - { - // - // Set the deep-sleep clock configuration. - // - HWREG(SYSCTL_DSLPCLKCFG) = (ui32Config & ~SYSCTL_DSLPCLKCFG_D_M) | - ((ui32Div - 1) << SYSCTL_DSLPCLKCFG_D_S); - } - else - { - // - // Initialize the value with the divider. - // - ui32Value = ui32Div - 1; - - // - // Set the clock source selection based on the defines used for - // SysCtlDeepSleepClockSet() function so that there is some backwards - // compatibility. - // - switch(ui32Config & SYSCTL_DSLPCLKCFG_O_M) - { - // - // Choose the main external oscillator. - // - case SYSCTL_DSLP_OSC_MAIN: - { - ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_MOSC; - - break; - } - - // - // Choose the low frequency oscillator. - // - case SYSCTL_DSLP_OSC_INT30: - { - ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC; - - break; - } - - // - // Choose the low frequency oscillator. - // - case SYSCTL_DSLP_OSC_EXT32: - { - ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_RTC; - - break; - } - // - // The zero value uses the PIOSC as the clock source. - // - case SYSCTL_DSLP_OSC_INT: - default: - { - break; - } - } - - // - // Set the PIOSC power down bit. - // - if(ui32Config & SYSCTL_DSLP_PIOSC_PD) - { - ui32Value |= SYSCTL_DSCLKCFG_PIOSCPD; - } - - // - // Set the PIOSC power down bit. - // - if(ui32Config & SYSCTL_DSLP_MOSC_PD) - { - ui32Value |= SYSCTL_DSCLKCFG_MOSCDPD; - } - - // - // Update the deep-sleep clock configuration. - // - HWREG(SYSCTL_DSCLKCFG) = ui32Value; - } -} - -//***************************************************************************** -// -//! Sets the PWM clock configuration. -//! -//! \param ui32Config is the configuration for the PWM clock; it must be one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -//! -//! This function configures the rate of the clock provided to the PWM module -//! as a ratio of the processor clock. This clock is used by the PWM module to -//! generate PWM signals; its rate forms the basis for all PWM signals. -//! -//! \note This function should only be used with TM4C123 devices. For -//! other TM4C devices, the PWMClockSet() function should be used. -//! -//! \note The clocking of the PWM is dependent on the system clock rate as -//! configured by SysCtlClockSet(). -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlPWMClockSet(uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT((ui32Config == SYSCTL_PWMDIV_1) || - (ui32Config == SYSCTL_PWMDIV_2) || - (ui32Config == SYSCTL_PWMDIV_4) || - (ui32Config == SYSCTL_PWMDIV_8) || - (ui32Config == SYSCTL_PWMDIV_16) || - (ui32Config == SYSCTL_PWMDIV_32) || - (ui32Config == SYSCTL_PWMDIV_64)); - - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1)); - - // - // Set the PWM clock configuration into the run-mode clock configuration - // register. - // - HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & - ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) | - ui32Config); -} - -//***************************************************************************** -// -//! Gets the current PWM clock configuration. -//! -//! This function returns the current PWM clock configuration. -//! -//! \return Returns the current PWM clock configuration; is one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -//! -//! \note This function should only be used with TM4C123 devices. For -//! other TM4C devices, the PWMClockGet() function should be used. -// -//***************************************************************************** -uint32_t -SysCtlPWMClockGet(void) -{ - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1)); - - // - // Return the current PWM clock configuration. Make sure that - // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled. - // - if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV)) - { - // - // The divider is not active so reflect this in the value we return. - // - return(SYSCTL_PWMDIV_1); - } - else - { - // - // The divider is active so directly return the masked register value. - // - return(HWREG(SYSCTL_RCC) & - (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)); - } -} - -//***************************************************************************** -// -//! Enables access to a GPIO peripheral via the AHB. -//! -//! \param ui32GPIOPeripheral is the GPIO peripheral to enable. -//! -//! This function is used to enable the specified GPIO peripheral to be -//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced -//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access, -//! the \b _AHB_BASE form of the base address should be used for GPIO -//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base -//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead. -//! -//! The \e ui32GPIOPeripheral argument must be only one of the following -//! values: -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. -//! -//! \note On some devices, all GPIO ports are only available on AHB. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); - - // - // Enable this GPIO for AHB access. - // - HWREG(SYSCTL_GPIOHBCTL) |= (1 << (ui32GPIOPeripheral & 0xF)); -} - -//***************************************************************************** -// -//! Disables access to a GPIO peripheral via the AHB. -//! -//! \param ui32GPIOPeripheral is the GPIO peripheral to disable. -//! -//! This function disables the specified GPIO peripheral for access from the -//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed -//! from the legacy Advanced Peripheral Bus (APB). -//! -//! The \b ui32GPIOPeripheral argument must be only one of the following -//! values: -//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, -//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, -//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ. -//! -//! \note Some devices allow disabling AHB access to GPIO ports that are only -//! present on the AHB. Disabling AHB access to these ports will disable -//! access to these GPIO ports. On some devices, all GPIO ports are only -//! available on AHB. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) || - (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ)); - - // - // Disable this GPIO for AHB access. - // - HWREG(SYSCTL_GPIOHBCTL) &= ~(1 << (ui32GPIOPeripheral & 0xF)); -} - -//***************************************************************************** -// -//! Powers up the USB PLL. -//! -//! This function enables the USB controller's PLL, which is used by its -//! physical layer. This call is necessary before connecting to any external -//! devices. -//! -//! \note This function should only be called on TM4C123 devices. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlUSBPLLEnable(void) -{ - // - // Turn on the USB PLL. - // - HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN; -} - -//***************************************************************************** -// -//! Powers down the USB PLL. -//! -//! This function disables the USB controller's PLL, which is used by its -//! physical layer. The USB registers are still accessible, but the physical -//! layer no longer functions. -//! -//! \note This function should only be called on TM4C123 devices. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlUSBPLLDisable(void) -{ - // - // Turn off the USB PLL. - // - HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN; -} - -//***************************************************************************** -// -//! Configures the response to system voltage events. -//! -//! \param ui32Config holds the configuration options for the voltage events. -//! -//! This function configures the response to voltage-related events. -//! These events are triggered when the voltage rails drop below certain -//! levels. The \e ui32Config parameter provides the configuration for the -//! voltage events and is a combination of the \b SYSCTL_VEVENT_* values. -//! -//! The response to a brown out on the VDDA rail is set by using one of the -//! following values: -//! - \b SYSCTL_VEVENT_VDDABO_NONE - There is no action taken on a VDDA -//! brown out. -//! - \b SYSCTL_VEVENT_VDDABO_INT - A system interrupt is generated when a -//! VDDA brown out occurs. -//! - \b SYSCTL_VEVENT_VDDABO_NMI - An NMI is generated when a VDDA brown out -//! occurs. -//! - \b SYSCTL_VEVENT_VDDABO_RST - A reset is generated when a VDDA brown out -//! occurs. The type of reset that is generated is controller by the -//! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() -//! function. -//! -//! The response to a brown out on the VDD rail is set by using one of the -//! following values: -//! - \b SYSCTL_VEVENT_VDDBO_NONE - There is no action taken on a VDD -//! brown out. -//! - \b SYSCTL_VEVENT_VDDBO_INT - A system interrupt is generated when a -//! VDD brown out occurs. -//! - \b SYSCTL_VEVENT_VDDBO_NMI - An NMI is generated when a VDD brown out -//! occurs. -//! - \b SYSCTL_VEVENT_VDDBO_RST - A reset is generated when a VDD brown out -//! occurs. The type of reset that is generated is controller by the -//! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet() -//! function. -//! -//! \b Example: Configure the voltage events to trigger an interrupt on a VDDA -//! brown out, an NMI on a VDDC brown out and a reset on a VDD brown out. -//! -//! \verbatim -//! -//! // -//! // Configure the BOR rest to trigger a full POR. This is needed because -//! // the SysCtlVoltageEventConfig() call is triggering a reset so the type -//! // of reset is specified by this call. -//! // -//! SysCtlResetBehaviorSet(SYSCTL_ONRST_BOR_POR); -//! -//! // -//! // Trigger an interrupt on a VDDA brown out and a reset on a VDD brown out. -//! // -//! SysCtlVoltageEventConfig(SYSCTL_VEVENT_VDDABO_INT | -//! SYSCTL_VEVENT_VDDBO_RST); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlVoltageEventConfig(uint32_t ui32Config) -{ - // - // Set the requested events. - // - HWREG(SYSCTL_PTBOCTL) = ui32Config; -} - -//***************************************************************************** -// -//! Returns the voltage event status. -//! -//! This function returns the voltage event status for the system controller. -//! The value returned is a logical OR of the following values: -//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail. -//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail. -//! -//! The values returned from this function can be passed to the -//! SysCtlVoltageEventClear() to clear the current voltage event status. -//! Because voltage events are not cleared due to a reset, the voltage event -//! status must be cleared by calling SysCtlVoltageEventClear(). -//! -//! \b Example: Clear the current voltage event status. -//! -//! \verbatim -//! uint32_t ui32VoltageEvents; -//! -//! // -//! // Read the current voltage event status. -//! // -//! ui32VoltageEvents = SysCtlVoltageEventStatus(); -//! -//! // -//! // Clear all the current voltage events. -//! // -//! SysCtlVoltageEventClear(ui32VoltageEvents); -//! \endverbatim -//! -//! \return The current voltage event status. -//! -//! \note The availability of voltage events varies with the Tiva part -//! in use. Please consult the data sheet for the part you are using to -//! determine which interrupt sources are available. -// -//***************************************************************************** -uint32_t -SysCtlVoltageEventStatus(void) -{ - // - // Return the current voltage event status. - // - return(HWREG(SYSCTL_PWRTC)); -} - -//***************************************************************************** -// -//! Clears the voltage event status. -//! -//! \param ui32Status is a bit mask of the voltage events to clear. -//! -//! This function clears the current voltage events status for the values -//! specified in the \e ui32Status parameter. The \e ui32Status value must be -//! a logical OR of the following values: -//! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail. -//! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail. -//! -//! \b Example: Clear the current voltage event status. -//! -//! \verbatim -//! // -//! // Clear all the current voltage events. -//! // -//! SysCtlVoltageEventClear(SysCtlVoltageEventStatus()); -//! \endverbatim -//! -//! \note The availability of voltage event status varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlVoltageEventClear(uint32_t ui32Status) -{ - // - // Clear the requested voltage events. - // - HWREG(SYSCTL_PWRTC) |= ui32Status; -} - -//***************************************************************************** -// -//! Gets the effective VCO frequency. -//! -//! \param ui32Crystal holds the crystal value used for the PLL. -//! \param pui32VCOFrequency is a pointer to the storage location which holds -//! value of the VCO computed. -//! -//! This function calculates the VCO of the PLL before the system divider is -//! applied -//! -//! \return \b true if the PLL is configured correctly and a VCO is valid or -//! \b false if the device is not TM4C129x or the PLL is not used -// -//***************************************************************************** -bool -SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) -{ - int32_t i32XtalIdx; - uint32_t ui32RSClkConfig, ui32PLLFreq0, ui32PLLFreq1, ui32Osc; - uint32_t ui32MInt, ui32MFrac, ui32NDiv, ui32QDiv, ui32TempVCO; - - // - // Check if TM4C123 device is being used. should not use this function. - // - if(CLASS_IS_TM4C123) - { - // - // Return error if TM4C123. - // - *pui32VCOFrequency = 0; - return(false); - } - - // - // Read the RSCLKCFG register to determine if PLL is being used. - // - ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - - // - // Check if PLL is used. - // - if((ui32RSClkConfig & SYSCTL_RSCLKCFG_USEPLL) != SYSCTL_RSCLKCFG_USEPLL) - { - // - // Return error if PLL is not used. - // - *pui32VCOFrequency = 0; - return(false); - } - - // - // Get the index of the crystal from the ui32Config parameter. - // - i32XtalIdx = SysCtlXtalCfgToIndex(ui32Crystal); - - // - // Get the value of the crystal frequency based on the index - // - ui32Osc = g_pui32Xtals[i32XtalIdx]; - - // - // Read the PLLFREQ0 and PLLFREQ1 registers to get information on the - // MINT, MFRAC, N and Q values of the PLL - // - ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0); - ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1); - - ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> - SYSCTL_PLLFREQ0_MINT_S; - ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> - SYSCTL_PLLFREQ0_MFRAC_S; - ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> - SYSCTL_PLLFREQ1_N_S; - ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> - SYSCTL_PLLFREQ1_Q_S; - - // - // Calculate the VCO at the output of the PLL - // - ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024); - ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1)); - - *pui32VCOFrequency = ui32TempVCO; - return(true); -} - -//***************************************************************************** -// -//! Returns the current NMI status. -//! -//! This function returns the NMI status for the system controller. The valid -//! values for the \e ui32Ints parameter are a logical OR of the following -//! values: -//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not -//! start. -//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected. -//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout. -//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout. -//! - \b SYSCTL_NMI_POWER a power event occurred. -//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted. -//! -//! \b Example: Clear all current NMI status flags. -//! -//! \verbatim -//! -//! // -//! // Clear all the current NMI sources. -//! // -//! SysCtlNMIClear(SysCtlNMIStatus()); -//! \endverbatim -//! -//! \note The availability of the NMI status varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return The current NMI status. -// -//***************************************************************************** -uint32_t -SysCtlNMIStatus(void) -{ - return(HWREG(SYSCTL_NMIC)); -} - -//***************************************************************************** -// -//! Clears NMI sources. -//! -//! \param ui32Ints is a bit mask of the non-maskable interrupt sources. -//! -//! This function clears the current NMI status specified in the \e ui32Ints -//! parameter. The valid values for the \e ui32Ints parameter are a logical OR -//! of the following values: -//! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not -//! start. -//! - \b SYSCTL_NMI_TAMPER a tamper event has been detected. -//! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout. -//! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout. -//! - \b SYSCTL_NMI_POWER a power event occurred. -//! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted. -//! -//! \b Example: Clear all current NMI status flags. -//! -//! \verbatim -//! -//! // -//! // Clear all the current NMI sources. -//! // -//! SysCtlNMIClear(SysCtlNMIStatus()); -//! \endverbatim -//! -//! \note The availability of the NMI status varies with the Tiva part in -//! use. Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlNMIClear(uint32_t ui32Ints) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSCTL_NMIC) &= ~ui32Ints; -} - -//***************************************************************************** -// -//! Configures and enables or disables the clock output on the DIVSCLK pin. -//! -//! \param ui32Config holds the configuration options including enabling or -//! disabling the clock output on the DIVSCLK pin. -//! \param ui32Div is the divisor for the clock selected in the \e ui32Config -//! parameter. -//! -//! This function selects the source for the DIVSCLK, enables or disables -//! the clock output and provides an output divider value. The \e ui32Div -//! parameter specifies the divider for the selected clock source and has a -//! valid range of 1-256. The \e ui32Config parameter configures -//! the DIVSCLK output based on the following settings: -//! -//! The first setting allows the output to be enabled or disabled. -//! - \b SYSCTL_CLKOUT_EN - enable the DIVSCLK output. -//! - \b SYSCTL_CLKOUT_DIS - disable the DIVSCLK output (default). -//! -//! The next group of settings selects the source for the DIVSCLK. -//! - \b SYSCTL_CLKOUT_SYSCLK - use the current system clock as the -//! source (default). -//! - \b SYSCTL_CLKOUT_PIOSC - use the PIOSC as the source. -//! - \b SYSCTL_CLKOUT_MOSC - use the MOSC as the source. -//! -//! \b Example: Enable the PIOSC divided by 4 as the DIVSCLK output. -//! -//! \verbatim -//! -//! // -//! // Enable the PIOSC divided by 4 as the DIVSCLK output. -//! // -//! SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4); -//! \endverbatim -//! -//! \note The availability of the DIVSCLK output varies with the Tiva part -//! in use. Please consult the data sheet for the part you are using to -//! determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div) -{ - ASSERT(ui32Div != 0); - ASSERT((ui32Config & ~(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_DIS | - SYSCTL_CLKOUT_SYSCLK | SYSCTL_CLKOUT_PIOSC | - SYSCTL_CLKOUT_MOSC)) == 0); - - // - // Set the requested configuration and divisor. - // - HWREG(SYSCTL_DIVSCLK) = ui32Config | ((ui32Div - 1) & - SYSCTL_DIVSCLK_DIV_M); -} - -//***************************************************************************** -// -//! Configures the alternate peripheral clock source. -//! -//! \param ui32Config holds the configuration options for the alternate -//! peripheral clock. -//! -//! This function configures the alternate peripheral clock. The alternate -//! peripheral clock is used to provide a known clock in all operating modes -//! to peripherals that support using the alternate peripheral clock as an -//! input clock. The \e ui32Config parameter value provides the clock input -//! source using one of the following values: -//! - \b SYSCTL_ALTCLK_PIOSC - use the PIOSC as the alternate clock -//! source (default). -//! - \b SYSCTL_ALTCLK_RTCOSC - use the Hibernate module RTC clock as the -//! alternate clock source. -//! - \b SYSCTL_ALTCLK_LFIOSC - use the low-frequency internal oscillator as -//! the alternate clock source. -//! -//! \b Example: Select the Hibernate module RTC clock as the alternate clock -//! source. -//! -//! \verbatim -//! -//! // -//! // Select the Hibernate module RTC clock as the alternate clock source. -//! // -//! SysCtlAltClkConfig(SYSCTL_ALTCLK_RTCOSC); -//! \endverbatim -//! -//! \note The availability of the alternate peripheral clock varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -void -SysCtlAltClkConfig(uint32_t ui32Config) -{ - // - // Set the requested configuration and divisor. - // - HWREG(SYSCTL_ALTCLKCFG) = ui32Config; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.h b/bsp/tm4c129x-dk/libraries/driverlib/sysctl.h deleted file mode 100644 index 0bce4852d7..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysctl.h +++ /dev/null @@ -1,656 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SYSCTL_H__ -#define __DRIVERLIB_SYSCTL_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0 -#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1 -#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0 -#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1 -#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0 -#define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0 -#define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0 -#define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0 -#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E -#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F -#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G -#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H -#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J -#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module -#define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0 -#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 -#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 -#define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1 -#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K -#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L -#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M -#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N -#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P -#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q -#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R -#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S -#define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T -#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0 -#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1 -#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 -#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 -#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 -#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 -#define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6 -#define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7 -#define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8 -#define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9 -#define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0 -#define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0 -#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0 -#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 -#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0 -#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1 -#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0 -#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1 -#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 -#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 -#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2 -#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3 -#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 -#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 -#define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6 -#define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7 -#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0 -#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1 -#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2 -#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 -#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 -#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 -#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 -#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 -#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA -#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0 -#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0 -#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1 -#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 -#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 -#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 -#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 -#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 -#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSleepSet() and -// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the -// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. -// -//***************************************************************************** -#define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V -#define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V -#define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V -#define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V -#define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V -#define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V -#define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0 -#define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK -#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt -#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1 -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request -#define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset -#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset -#ifndef DEPRECATED -#define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0 - // Watchdog reset(Deprecated) -#endif -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 -#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 -#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 -#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 -#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 -#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 -#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 -#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 -#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 -#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 -#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 -#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 -#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 -#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 -#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 -#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 -#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 -#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 -#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 -#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 -#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 -#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 -#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 -#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 -#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 -#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 -#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 -#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 -#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 -#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 -#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 -#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 -#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 -#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 -#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 -#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 -#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 -#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 -#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 -#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 -#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 -#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 -#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 -#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 -#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 -#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 -#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 -#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 -#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 -#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 -#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 -#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 -#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 -#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 -#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 -#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 -#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 -#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 -#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 -#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 -#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 -#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 -#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 -#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 -#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 -#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 -#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 -#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 -#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 -#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 -#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 -#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 -#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 -#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 -#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 -#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 -#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 -#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 -#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 -#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 -#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 -#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 -#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 -#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 -#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 -#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 -#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 -#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 -#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 -#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 -#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 -#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 -#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 -#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 -#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 -#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 -#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 -#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 -#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 -#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 -#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 -#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 -#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 -#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 -#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 -#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 -#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 -#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 -#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 -#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 -#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz -#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz -#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz -#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz -#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz -#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz -#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz -#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz -#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz -#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz -#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz -#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz -#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz -#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz -#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 -#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz -#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlDeepSleepClockSet() -// API as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 -#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 -#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 -#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 -#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 -#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 -#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 -#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 -#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 -#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 -#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 -#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 -#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 -#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 -#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 -#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 -#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 -#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 -#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 -#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 -#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 -#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 -#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 -#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 -#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 -#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 -#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 -#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 -#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 -#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 -#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 -#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 -#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 -#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 -#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 -#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 -#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 -#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 -#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 -#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 -#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 -#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 -#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 -#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 -#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 -#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 -#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 -#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 -#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 -#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 -#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 -#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 -#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 -#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 -#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 -#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 -#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 -#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 -#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 -#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 -#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 -#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 -#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 -#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 -#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc -#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc -#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz -#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz -#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep -#define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPIOSCCalibrate() -// API as the ui32Type parameter. -// -//***************************************************************************** -#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration -#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration -#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlMOSCConfigSet() API -// as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation -#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail -#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC -#define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC. -#define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz -#define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz -#define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source. - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlSleepPowerSet() and -// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. -// -//***************************************************************************** -#define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode - // (Deep Sleep Only) -#define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode - // (Deep Sleep Only) -#define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode -#define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode -#define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode -#define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode -#define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode - -//***************************************************************************** -// -// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. -// -//***************************************************************************** -#define SYSCTL_ONRST_WDOG0_POR 0x00000030 -#define SYSCTL_ONRST_WDOG0_SYS 0x00000020 -#define SYSCTL_ONRST_WDOG1_POR 0x000000C0 -#define SYSCTL_ONRST_WDOG1_SYS 0x00000080 -#define SYSCTL_ONRST_BOR_POR 0x0000000C -#define SYSCTL_ONRST_BOR_SYS 0x00000008 -#define SYSCTL_ONRST_EXT_POR 0x00000003 -#define SYSCTL_ONRST_EXT_SYS 0x00000002 - -//***************************************************************************** -// -// Values used with the SysCtlVoltageEventConfig() API. -// -//***************************************************************************** -#define SYSCTL_VEVENT_VDDABO_NONE \ - 0x00000000 -#define SYSCTL_VEVENT_VDDABO_INT \ - 0x00000100 -#define SYSCTL_VEVENT_VDDABO_NMI \ - 0x00000200 -#define SYSCTL_VEVENT_VDDABO_RST \ - 0x00000300 -#define SYSCTL_VEVENT_VDDBO_NONE \ - 0x00000000 -#define SYSCTL_VEVENT_VDDBO_INT 0x00000001 -#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002 -#define SYSCTL_VEVENT_VDDBO_RST 0x00000003 - -//***************************************************************************** -// -// Values used with the SysCtlVoltageEventStatus() and -// SysCtlVoltageEventClear() APIs. -// -//***************************************************************************** -#define SYSCTL_VESTAT_VDDBOR 0x00000040 -#define SYSCTL_VESTAT_VDDABOR 0x00000010 - -//***************************************************************************** -// -// Values used with the SysCtlNMIStatus() API. -// -//***************************************************************************** -#define SYSCTL_NMI_MOSCFAIL 0x00010000 -#define SYSCTL_NMI_TAMPER 0x00000200 -#define SYSCTL_NMI_WDT1 0x00000020 -#define SYSCTL_NMI_WDT0 0x00000008 -#define SYSCTL_NMI_POWER 0x00000004 -#define SYSCTL_NMI_EXTERNAL 0x00000001 - -//***************************************************************************** -// -// The defines for the SysCtlClockOutConfig() API. -// -//***************************************************************************** -#define SYSCTL_CLKOUT_EN 0x80000000 -#define SYSCTL_CLKOUT_DIS 0x00000000 -#define SYSCTL_CLKOUT_SYSCLK 0x00000000 -#define SYSCTL_CLKOUT_PIOSC 0x00010000 -#define SYSCTL_CLKOUT_MOSC 0x00020000 - -//***************************************************************************** -// -// The following defines are used with the SysCtlAltClkConfig() function. -// -//***************************************************************************** -#define SYSCTL_ALTCLK_PIOSC 0x00000000 -#define SYSCTL_ALTCLK_RTCOSC 0x00000003 -#define SYSCTL_ALTCLK_LFIOSC 0x00000004 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern uint32_t SysCtlSRAMSizeGet(void); -extern uint32_t SysCtlFlashSizeGet(void); -extern uint32_t SysCtlFlashSectorSizeGet(void); -extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); -extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral); -extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral); -extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral); -extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); -extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral); -extern void SysCtlPeripheralClockGating(bool bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(uint32_t ui32Ints); -extern void SysCtlIntDisable(uint32_t ui32Ints); -extern void SysCtlIntClear(uint32_t ui32Ints); -extern uint32_t SysCtlIntStatus(bool bMasked); -extern void SysCtlLDOSleepSet(uint32_t ui32Voltage); -extern uint32_t SysCtlLDOSleepGet(void); -extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage); -extern uint32_t SysCtlLDODeepSleepGet(void); -extern void SysCtlSleepPowerSet(uint32_t ui32Config); -extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern uint32_t SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(uint32_t ui32Causes); -extern void SysCtlBrownOutConfigSet(uint32_t ui32Config, - uint32_t ui32Delay); -extern void SysCtlDelay(uint32_t ui32Count); -extern void SysCtlMOSCConfigSet(uint32_t ui32Config); -extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type); -extern void SysCtlClockSet(uint32_t ui32Config); -extern uint32_t SysCtlClockGet(void); -extern void SysCtlDeepSleepClockSet(uint32_t ui32Config); -extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, - uint32_t ui32Config); -extern void SysCtlPWMClockSet(uint32_t ui32Config); -extern uint32_t SysCtlPWMClockGet(void); -extern void SysCtlIOSCVerificationSet(bool bEnable); -extern void SysCtlMOSCVerificationSet(bool bEnable); -extern void SysCtlPLLVerificationSet(bool bEnable); -extern void SysCtlClkVerificationClear(void); -extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral); -extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral); -extern void SysCtlUSBPLLEnable(void); -extern void SysCtlUSBPLLDisable(void); -extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config, - uint32_t ui32SysClock); -extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior); -extern uint32_t SysCtlResetBehaviorGet(void); -extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div); -extern void SysCtlAltClkConfig(uint32_t ui32Config); -extern uint32_t SysCtlNMIStatus(void); -extern void SysCtlNMIClear(uint32_t ui32Status); -extern void SysCtlVoltageEventConfig(uint32_t ui32Config); -extern uint32_t SysCtlVoltageEventStatus(void); -extern void SysCtlVoltageEventClear(uint32_t ui32Status); -extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SYSCTL_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.c b/bsp/tm4c129x-dk/libraries/driverlib/sysexc.c deleted file mode 100644 index d269b74bcd..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.c +++ /dev/null @@ -1,311 +0,0 @@ -//***************************************************************************** -// -// sysexc.c - Routines for the System Exception Module. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sysexc_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_sysexc.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" - -//***************************************************************************** -// -//! Returns the interrupt number for a system exception. -//! -//! This function returns the interrupt number for a system exception. -//! -//! \return Returns the system exception interrupt number. -// -//***************************************************************************** -static uint32_t -_SysExcIntNumberGet(void) -{ - uint32_t ui32Int; - - // - // Get the interrupt number based on the class. - // - if(CLASS_IS_TM4C123) - { - ui32Int = INT_SYSEXC_TM4C123; - } - else if(CLASS_IS_TM4C129) - { - ui32Int = INT_SYSEXC_TM4C129; - } - else - { - ui32Int = 0; - } - return(ui32Int); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the system exception interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the system -//! exception interrupt occurs. -//! -//! This function places the address of the system exception interrupt handler -//! into the interrupt vector table in SRAM. This function also enables the -//! global interrupt in the interrupt controller; specific system exception -//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntRegister(void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Get the system exception interrupt number. - // - ui32Int = _SysExcIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the system exception interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters the system exception interrupt handler. -//! -//! This function removes the system exception interrupt handler from the -//! vector table in SRAM. This function also masks off the system exception -//! interrupt in the interrupt controller so that the interrupt handler is no -//! longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntUnregister(void) -{ - uint32_t ui32Int; - - // - // Get the system exception interrupt number. - // - ui32Int = _SysExcIntNumberGet(); - - ASSERT(ui32Int != 0); - - // - // Disable the system exception interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the system exception interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual system exception interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated system exception interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt -//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt -//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt -//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt -//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt -//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntEnable(uint32_t ui32IntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(SYSEXC_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual system exception interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated system exception interrupt sources. -//! Only sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt -//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt -//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt -//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt -//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt -//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntDisable(uint32_t ui32IntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(SYSEXC_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current system exception interrupt status. -//! -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the system exception interrupt status. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current system exception interrupt status, enumerated -//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC, -//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and -//! \b SYSEXC_INT_FP_IDC. -// -//***************************************************************************** -uint32_t -SysExcIntStatus(bool bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(SYSEXC_MIS)); - } - else - { - return(HWREG(SYSEXC_RIS)); - } -} - -//***************************************************************************** -// -//! Clears system exception interrupt sources. -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! This function clears the specified system exception interrupt sources, so -//! that they no longer assert. This function must be called in the interrupt -//! handler to keep the interrupt from being recognized again immediately upon -//! exit. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt -//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt -//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt -//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt -//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt -//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -SysExcIntClear(uint32_t ui32IntFlags) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSEXC_IC) = ui32IntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.h b/bsp/tm4c129x-dk/libraries/driverlib/sysexc.h deleted file mode 100644 index aece4409d1..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/sysexc.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// sysexc.h - Prototypes for the System Exception Module routines. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_SYSEXC_H__ -#define __DRIVERLIB_SYSEXC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and -// SysExcIntClear as the ui32IntFlags parameter, and returned from -// SysExcIntStatus. -// -//***************************************************************************** -#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt -#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt -#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt -#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt -#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int -#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void SysExcIntRegister(void (*pfnHandler)(void)); -extern void SysExcIntUnregister(void); -extern void SysExcIntEnable(uint32_t ui32IntFlags); -extern void SysExcIntDisable(uint32_t ui32IntFlags); -extern uint32_t SysExcIntStatus(bool bMasked); -extern void SysExcIntClear(uint32_t ui32IntFlags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_SYSEXC_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.c b/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.c deleted file mode 100644 index d348849570..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.c +++ /dev/null @@ -1,1898 +0,0 @@ -//***************************************************************************** -// -// timer.c - Driver for the timer module. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup timer_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_timer.h" -#include "inc/hw_types.h" -#include "inc/hw_sysctl.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/tiva_timer.h" - -//***************************************************************************** -// -// A macro used to determine whether the target part supports new -// configuration and control options. -// -//***************************************************************************** -#define NEW_TIMER_CONFIGURATION CLASS_IS_TM4C129 - -//***************************************************************************** -// -// A mapping of timer base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32TimerIntMap[][2] = -{ - { TIMER0_BASE, INT_TIMER0A_TM4C123 }, - { TIMER1_BASE, INT_TIMER1A_TM4C123 }, - { TIMER2_BASE, INT_TIMER2A_TM4C123 }, - { TIMER3_BASE, INT_TIMER3A_TM4C123 }, - { TIMER4_BASE, INT_TIMER4A_TM4C123 }, - { TIMER5_BASE, INT_TIMER5A_TM4C123 }, - { WTIMER0_BASE, INT_WTIMER0A_TM4C123 }, - { WTIMER1_BASE, INT_WTIMER1A_TM4C123 }, - { WTIMER2_BASE, INT_WTIMER2A_TM4C123 }, - { WTIMER3_BASE, INT_WTIMER3A_TM4C123 }, - { WTIMER4_BASE, INT_WTIMER4A_TM4C123 }, - { WTIMER5_BASE, INT_WTIMER5A_TM4C123 }, -}; -static const uint_fast8_t g_ui8TimerIntMapRows = - sizeof(g_ppui32TimerIntMap) / sizeof(g_ppui32TimerIntMap[0]); - -static const uint32_t g_ppui32TimerIntMapSnowflake[][2] = -{ - { TIMER0_BASE, INT_TIMER0A_TM4C129 }, - { TIMER1_BASE, INT_TIMER1A_TM4C129 }, - { TIMER2_BASE, INT_TIMER2A_TM4C129 }, - { TIMER3_BASE, INT_TIMER3A_TM4C129 }, - { TIMER4_BASE, INT_TIMER4A_TM4C129 }, - { TIMER5_BASE, INT_TIMER5A_TM4C129 }, - { TIMER6_BASE, INT_TIMER6A_TM4C129 }, - { TIMER7_BASE, INT_TIMER7A_TM4C129 }, -}; -static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake = - sizeof(g_ppui32TimerIntMapSnowflake) / - sizeof(g_ppui32TimerIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks a timer base address. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function determines if a timer module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_TimerBaseValid(uint32_t ui32Base) -{ - return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || - (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || - (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || - (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) || - (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) || - (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) || - (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE)); -} -#endif - -//***************************************************************************** -// -//! Returns a timer modules interrupt number. -//! -//! \param ui32Base is the base address of the selected timer. -//! \param ui32Timer specifies the timer(s) to enable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function returns the interrupt number for a given timer module -//! specified by the \e ui32Base and \e ui32Timer parameter. -//! -//! \return Returns a timer module's interrupt number or 0 if the interrupt -//! does not exist. -// -//***************************************************************************** -static uint32_t -_TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - uint32_t ui32Int; - uint_fast8_t ui8Idx, ui8Rows; - const uint32_t (*ppui32SSIIntMap)[2]; - - // - // Default interrupt map. - // - ppui32SSIIntMap = g_ppui32TimerIntMap; - ui8Rows = g_ui8TimerIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32SSIIntMap = g_ppui32TimerIntMapSnowflake; - ui8Rows = g_ui8TimerIntMapRowsSnowflake; - } - - // - // Loop through the table that maps timer base addresses to interrupt - // numbers. - // - for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) - { - // - // See if this base address matches. - // - if(ppui32SSIIntMap[ui8Idx][0] == ui32Base) - { - ui32Int = ppui32SSIIntMap[ui8Idx][1]; - - if(ui32Timer == TIMER_B) - { - ui32Int += 1; - } - - // - // Return the corresponding interrupt number. - // - return(ui32Int); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Enables the timer(s). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to enable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function enables operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Enable the timer(s) module. - // - HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN | - TIMER_CTL_TBEN); -} - -//***************************************************************************** -// -//! Disables the timer(s). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to disable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function disables operation of the timer module. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Disable the timer module. - // - HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer & - (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); -} - -//***************************************************************************** -// -//! Configures the timer(s). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Config is the configuration for the timer. -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured and is left in the disabled -//! state. The timer can be configured to be a single full-width timer -//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the -//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ui32Config -//! parameter. -//! -//! The configuration is specified in \e ui32Config as one of the following -//! values: -//! -//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer -//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer -//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_RTC - Full-width real time clock timer -//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers -//! -//! When configured for a pair of half-width timers, each timer is separately -//! configured. The first timer is configured by setting \e ui32Config to -//! the result of a logical OR operation between one of the following values -//! and \e ui32Config: -//! -//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer -//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer -//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture -//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts -//! up instead of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture -//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_PWM - Half-width PWM output -//! -//! Some Tiva devices also allow configuring an action when the timers -//! reach their timeout. Please consult the data sheet for the part you are -//! using to determine whether configuring actions on timers is available. -//! -//! One of the following can be combined with the \b TIMER_CFG_* values to -//! enable an action on timer A: -//! -//! - \b TIMER_CFG_A_ACT_TOINTD - masks the timeout interrupt of timer A. -//! - \b TIMER_CFG_A_ACT_NONE - no additional action on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_TOGGLE - toggle CCP on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_SETTO - set CCP on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_CLRTO - clear CCP on timeout of timer A. -//! - \b TIMER_CFG_A_ACT_SETTOGTO - set CCP immediately and then toggle it on -//! timeout of timer A. -//! - \b TIMER_CFG_A_ACT_CLRTOGTO - clear CCP immediately and then toggle it on -//! timeout of timer A. -//! - \b TIMER_CFG_A_ACT_SETCLRTO - set CCP immediately and then clear it on -//! timeout of timer A. -//! - \b TIMER_CFG_A_ACT_CLRSETTO - clear CCP immediately and then set it on -//! timeout of timer A. -//! -//! One of the following can be combined with the \b TIMER_CFG_* values to -//! enable an action on timer B: -//! -//! - \b TIMER_CFG_B_ACT_TOINTD - masks the timeout interrupt of timer B. -//! - \b TIMER_CFG_B_ACT_NONE - no additional action on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_TOGGLE - toggle CCP on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_SETTO - set CCP on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_CLRTO - clear CCP on timeout of timer B. -//! - \b TIMER_CFG_B_ACT_SETTOGTO - set CCP immediately and then toggle it on -//! timeout of timer B. -//! - \b TIMER_CFG_B_ACT_CLRTOGTO - clear CCP immediately and then toggle it on -//! timeout of timer B. -//! - \b TIMER_CFG_B_ACT_SETCLRTO - set CCP immediately and then clear it on -//! timeout of timer B. -//! - \b TIMER_CFG_B_ACT_CLRSETTO - clear CCP immediately and then set it on -//! timeout of timer B. -//! -//! Similarly, the second timer is configured by setting \e ui32Config to -//! the result of a logical OR operation between one of the corresponding -//! \b TIMER_CFG_B_* values and \e ui32Config. -//! -//! \return None. -// -//***************************************************************************** -void -TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || - (ui32Config == TIMER_CFG_ONE_SHOT_UP) || - (ui32Config == TIMER_CFG_PERIODIC) || - (ui32Config == TIMER_CFG_PERIODIC_UP) || - (ui32Config == TIMER_CFG_RTC) || - ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR)); - ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) || - ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME_UP) || - ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) && - (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) || - ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM)))); - - // - // Disable the timers. - // - HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24; - - // - // Set the configuration of the A and B timers and set the TxPWMIE bit. - // Note that the B timer configuration is ignored by the hardware in 32-bit - // modes. - // - if(NEW_TIMER_CONFIGURATION) - { - HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | - (ui32Config & 0xff) | - TIMER_TAMR_TAPWMIE); - HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | - ((ui32Config >> 8) & 0xff) | - TIMER_TBMR_TBPWMIE); - } - else - { - HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) | - TIMER_TAMR_TAPWMIE); - HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) | - TIMER_TBMR_TBPWMIE); - } -} - -//***************************************************************************** -// -//! Controls the output level. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bInvert specifies the output level. -//! -//! This function configures the PWM output level for the specified timer. If -//! the \e bInvert parameter is \b true, then the timer's output is made active -//! low; otherwise, it is made active high. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; - HWREG(ui32Base + TIMER_O_CTL) = (bInvert ? - (HWREG(ui32Base + TIMER_O_CTL) | - ui32Timer) : - (HWREG(ui32Base + TIMER_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -//! Enables or disables the ADC trigger output. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bEnable specifies the desired ADC trigger state. -//! -//! This function controls the ADC trigger output for the specified timer. If -//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is -//! enabled; otherwise it is disabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // On newer devices the Timer time out ADC trigger enable must also - // be set. - // - if(NEW_TIMER_CONFIGURATION) - { - uint32_t ui32Val; - - // - // Determine which bits to set or clear in GPTMADCEV. - // - ui32Val = (TIMER_ADCEV_TATOADCEN | TIMER_ADCEV_TBTOADCEN); - ui32Val &= ui32Timer; - - // - // Write the GPTM ADC Event register to enable or disable the trigger - // to the ADC. - // - HWREG(ui32Base + TIMER_O_ADCEV) = (bEnable ? - (HWREG(ui32Base + TIMER_O_ADCEV) | - ui32Val) : - (HWREG(ui32Base + TIMER_O_ADCEV) & - ~(ui32Val))); - } - - // - // Set the trigger output as requested. - // Set the ADC trigger output as requested. - // - ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; - HWREG(ui32Base + TIMER_O_CTL) = (bEnable ? - (HWREG(ui32Base + TIMER_O_CTL) | - ui32Timer) : - (HWREG(ui32Base + TIMER_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -//! Controls the event type. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Event specifies the type of event; must be one of -//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or -//! \b TIMER_EVENT_BOTH_EDGES. -//! -//! This function configures the signal edge(s) that triggers the timer when -//! in capture mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Event) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the event type. - // - ui32Timer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M; - HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) & - ~ui32Timer) | (ui32Event & ui32Timer)); -} - -//***************************************************************************** -// -//! Controls the stall handling. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bStall specifies the response to a stall signal. -//! -//! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer stops counting if the -//! processor enters debug mode; otherwise the timer keeps running while in -//! debug mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, - bool bStall) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; - HWREG(ui32Base + TIMER_O_CTL) = (bStall ? - (HWREG(ui32Base + TIMER_O_CTL) | - ui32Timer) : - (HWREG(ui32Base + TIMER_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -//! Controls the wait on trigger handling. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bWait specifies if the timer should wait for a trigger input. -//! -//! This function controls whether or not a timer waits for a trigger input to -//! start counting. When enabled, the previous timer in the trigger chain must -//! count to its timeout in order for this timer to start counting. Refer to -//! the part's data sheet for a description of the trigger chain. -//! -//! \note This functionality is not available on all parts. This function -//! should not be used for Timer 0A or Wide Timer 0A. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bWait) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the wait on trigger mode for timer A. - // - if((ui32Timer & TIMER_A) != 0) - { - if(bWait) - { - HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT; - } - else - { - HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT); - } - } - - // - // Set the wait on trigger mode for timer B. - // - if((ui32Timer & TIMER_B) != 0) - { - if(bWait) - { - HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT; - } - else - { - HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT); - } - } -} - -//***************************************************************************** -// -//! Enables RTC counting. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function causes the timer to start counting when in RTC mode. If not -//! configured for RTC mode, this function does nothing. -//! -//! \return None. -// -//***************************************************************************** -void -TimerRTCEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Enable RTC counting. - // - HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN; -} - -//***************************************************************************** -// -//! Disables RTC counting. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function causes the timer to stop counting when in RTC mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerRTCDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Disable RTC counting. - // - HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); -} - -//***************************************************************************** -// -//! Sets the clock source for the specified timer module. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Source is the clock source for the timer module. -//! -//! This function sets the clock source for both timer A and timer B for the -//! given timer module. The possible clock sources are the system clock -//! (\b TIMER_CLOCK_SYSTEM) or the precision internal oscillator -//! (\b TIMER_CLOCK_PIOSC). -//! -//! \note The ability to specify the timer clock source varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Source == TIMER_CLOCK_SYSTEM) || - (ui32Source == TIMER_CLOCK_PIOSC)); - - // - // Set the timer clock source. - // - HWREG(ui32Base + TIMER_O_CC) = ui32Source; -} - -//***************************************************************************** -// -//! Returns the clock source for the specified timer module. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function returns the clock source for the specified timer module. The -//! possible clock sources are the system clock (\b TIMER_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b TIMER_CLOCK_PIOSC). -//! -//! \note The ability to specify the timer clock source varies with the -//! Tiva part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns either \b TIMER_CLOCK_SYSTEM or \b TIMER_CLOCK_PIOSC. -// -//***************************************************************************** -uint32_t -TimerClockSourceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return the timer clock source. - // - return(HWREG(ui32Base + TIMER_O_CC)); -} - -//***************************************************************************** -// -//! Sets the timer prescale value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Value is the timer prescale value which must be between 0 and -//! 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) -//! for 32/64-bit timers. -//! -//! This function configures the value of the input clock prescaler. The -//! prescaler is only operational when in half-width mode and is used to extend -//! the range of the half-width timer modes. The prescaler provides the least -//! significant bits when counting down in periodic and one-shot modes; in all -//! other modes, the prescaler provides the most significant bits. -//! -//! \note The availability of the prescaler varies with the Tiva part and -//! timer mode in use. Please consult the datasheet for the part you are using -//! to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // - // Set the timer A prescaler if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAPR) = ui32Value; - } - - // - // Set the timer B prescaler if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBPR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer prescale value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. The prescaler provides the least -//! significant bits when counting down in periodic and one-shot modes; in all -//! other modes, the prescaler provides the most significant bits. -//! -//! \note The availability of the prescaler varies with the Tiva part and -//! timer mode in use. Please consult the datasheet for the part you are using -//! to determine whether this support is available. -//! -//! \return The value of the timer prescaler. -// -//***************************************************************************** -uint32_t -TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Return the appropriate prescale value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) : - HWREG(ui32Base + TIMER_O_TBPR)); -} - -//***************************************************************************** -// -//! Sets the timer prescale match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Value is the timer prescale match value which must be between 0 -//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 -//! (inclusive) for 32/64-bit timers. -//! -//! This function configures the value of the input clock prescaler match -//! value. When in a half-width mode that uses the counter match and the -//! prescaler, the prescale match effectively extends the range of the match. -//! The prescaler provides the least significant bits when counting down in -//! periodic and one-shot modes; in all other modes, the prescaler provides the -//! most significant bits. -//! -//! \note The availability of the prescaler match varies with the Tiva -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // - // Set the timer A prescale match if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value; - } - - // - // Set the timer B prescale match if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer prescale match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. The prescaler -//! provides the least significant bits when counting down in periodic and -//! one-shot modes; in all other modes, the prescaler provides the most -//! significant bits. -//! -//! \note The availability of the prescaler match varies with the Tiva -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return The value of the timer prescale match. -// -//***************************************************************************** -uint32_t -TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Return the appropriate prescale match value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) : - HWREG(ui32Base + TIMER_O_TBPMR)); -} - -//***************************************************************************** -// -//! Sets the timer load value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used -//! when the timer is configured for full-width operation. -//! \param ui32Value is the load value. -//! -//! This function configures the timer load value; if the timer is running then -//! the value is immediately loaded into the timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerLoadSet64() for full-width modes of 32/64-bit timers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the timer A load value if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAILR) = ui32Value; - } - - // - // Set the timer B load value if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBILR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer load value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerLoadGet64() for full-width modes of 32/64-bit timers. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -uint32_t -TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // - // Return the appropriate load value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) : - HWREG(ui32Base + TIMER_O_TBILR)); -} - -//***************************************************************************** -// -//! Sets the timer load value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui64Value is the load value. -//! -//! This function configures the timer load value for a 64-bit timer; if the -//! timer is running, then the value is immediately loaded into the timer. -//! -//! \return None. -// -//***************************************************************************** -void -TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the timer load value. The upper 32-bits must be written before the - // lower 32-bits in order to adhere to the hardware interlocks on the - // 64-bit value. - // - HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32; - HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff; -} - -//***************************************************************************** -// -//! Gets the timer load value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function gets the currently programmed interval load value for the -//! specified 64-bit timer. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -uint64_t -TimerLoadGet64(uint32_t ui32Base) -{ - uint32_t ui32High1, ui32High2, ui32Low; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Read the 64-bit load value. A read of the low 32-bits is performed - // between two reads of the upper 32-bits; if the upper 32-bit values match - // then the 64-bit value is consistent. If they do not match, then the - // read is performed again until they do match (it should never execute the - // loop body more than twice). - // - do - { - ui32High1 = HWREG(ui32Base + TIMER_O_TBILR); - ui32Low = HWREG(ui32Base + TIMER_O_TAILR); - ui32High2 = HWREG(ui32Base + TIMER_O_TBILR); - } - while(ui32High1 != ui32High2); - - // - // Return the load value. - // - return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); -} - -//***************************************************************************** -// -//! Gets the current timer value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function reads the current value of the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerValueGet64() for full-width modes of 32/64-bit timers. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -uint32_t -TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // - // Return the appropriate timer value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) : - HWREG(ui32Base + TIMER_O_TBR)); -} - -//***************************************************************************** -// -//! Gets the current 64-bit timer value. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function reads the current value of the specified timer. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -uint64_t -TimerValueGet64(uint32_t ui32Base) -{ - uint32_t ui32High1, ui32High2, ui32Low; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Read the 64-bit timer value. A read of the low 32-bits is performed - // between two reads of the upper 32-bits; if the upper 32-bit values match - // then the 64-bit value is consistent. If they do not match, then the - // read is performed again until they do match (it should never execute the - // loop body more than twice). - // - do - { - ui32High1 = HWREG(ui32Base + TIMER_O_TBR); - ui32Low = HWREG(ui32Base + TIMER_O_TAR); - ui32High2 = HWREG(ui32Base + TIMER_O_TBR); - } - while(ui32High1 != ui32High2); - - // - // Return the timer value. - // - return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); -} - -//***************************************************************************** -// -//! Sets the timer match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used -//! when the timer is configured for full-width operation. -//! \param ui32Value is the match value. -//! -//! This function configures the match value for a timer. This value is used -//! in capture count mode to determine when to interrupt the processor and in -//! PWM mode to determine the duty cycle of the output signal. On some -//! Tiva devices, match interrupts can also be generated in periodic and -//! one-shot modes. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerMatchSet64() for full-width modes of 32/64-bit timers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the timer A match value if requested. - // - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value; - } - - // - // Set the timer B match value if requested. - // - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value; - } -} - -//***************************************************************************** -// -//! Gets the timer match value. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function gets the match value for the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use -//! TimerMatchGet64() for full-width modes of 32/64-bit timers. -//! -//! \return Returns the match value for the timer. -// -//***************************************************************************** -uint32_t -TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // - // Return the appropriate match value. - // - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) : - HWREG(ui32Base + TIMER_O_TBMATCHR)); -} - -//***************************************************************************** -// -//! Sets the timer match value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui64Value is the match value. -//! -//! This function configures the match value for a timer. This value is used -//! in capture count mode to determine when to interrupt the processor and in -//! PWM mode to determine the duty cycle of the output signal. -//! -//! \return None. -// -//***************************************************************************** -void -TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the timer match value. The upper 32-bits must be written before the - // lower 32-bits in order to adhere to the hardware interlocks on the - // 64-bit value. - // - HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32; - HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff; -} - -//***************************************************************************** -// -//! Gets the timer match value for a 64-bit timer. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function gets the match value for the specified timer. -//! -//! \return Returns the match value for the timer. -// -//***************************************************************************** -uint64_t -TimerMatchGet64(uint32_t ui32Base) -{ - uint32_t ui32High1, ui32High2, ui32Low; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Read the 64-bit match value. A read of the low 32-bits is performed - // between two reads of the upper 32-bits; if the upper 32-bit values match - // then the 64-bit value is consistent. If they do not match, then the - // read is performed again until they do match (it should never execute the - // loop body more than twice). - // - do - { - ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR); - ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR); - ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR); - } - while(ui32High1 != ui32High2); - - // - // Return the match value. - // - return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer interrupt. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! This function registers the handler to be called when a timer interrupt -//! occurs. In addition, this function enables the global interrupt in the -//! interrupt controller; specific timer interrupts must be enabled via -//! TimerIntEnable(). It is the interrupt handler's responsibility to clear -//! the interrupt source via TimerIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, - void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the timer interrupt. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function unregisters the handler to be called when a timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual timer interrupt sources. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter must be the logical OR of any combination of -//! the following: -//! -//! - \b TIMER_TIMB_DMA - Timer B uDMA complete -//! - \b TIMER_TIMA_DMA - Timer A uDMA complete -//! - \b TIMER_CAPB_EVENT - Capture B event interrupt -//! - \b TIMER_CAPB_MATCH - Capture B match interrupt -//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt -//! - \b TIMER_RTC_MATCH - RTC interrupt mask -//! - \b TIMER_CAPA_EVENT - Capture A event interrupt -//! - \b TIMER_CAPA_MATCH - Capture A match interrupt -//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual timer interrupt sources. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the timer module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the timer module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in TimerIntEnable(). -// -//***************************************************************************** -uint32_t -TimerIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) : - HWREG(ui32Base + TIMER_O_RIS)); -} - -//***************************************************************************** -// -//! Clears timer interrupt sources. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to TimerIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Synchronizes the counters in a set of timers. -//! -//! \param ui32Base is the base address of the timer module. This parameter -//! must be the base address of Timer0 (in other words, \b TIMER0_BASE). -//! \param ui32Timers is the set of timers to synchronize. -//! -//! This function synchronizes the counters in a specified set of timers. -//! When a timer is running in half-width mode, each half can be included or -//! excluded in the synchronization event. When a timer is running in -//! full-width mode, only the A timer can be synchronized (specifying the B -//! timer has no effect). -//! -//! The \e ui32Timers parameter is the logical OR of any of the following -//! defines: -//! -//! - \b TIMER_0A_SYNC -//! - \b TIMER_0B_SYNC -//! - \b TIMER_1A_SYNC -//! - \b TIMER_1B_SYNC -//! - \b TIMER_2A_SYNC -//! - \b TIMER_2B_SYNC -//! - \b TIMER_3A_SYNC -//! - \b TIMER_3B_SYNC -//! - \b TIMER_4A_SYNC -//! - \b TIMER_4B_SYNC -//! - \b TIMER_5A_SYNC -//! - \b TIMER_5B_SYNC -//! - \b WTIMER_0A_SYNC -//! - \b WTIMER_0B_SYNC -//! - \b WTIMER_1A_SYNC -//! - \b WTIMER_1B_SYNC -//! - \b WTIMER_2A_SYNC -//! - \b WTIMER_2B_SYNC -//! - \b WTIMER_3A_SYNC -//! - \b WTIMER_3B_SYNC -//! - \b WTIMER_4A_SYNC -//! - \b WTIMER_4B_SYNC -//! - \b WTIMER_5A_SYNC -//! - \b WTIMER_5B_SYNC -//! -//! \note This functionality is not available on all parts. -//! -//! \return None. -// -//***************************************************************************** -void -TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == TIMER0_BASE); - - // - // Synchronize the specified timers. - // - HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers; -} - -//***************************************************************************** -// -//! Enables the events that can cause an ADC trigger event. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32ADCEvent is a bit mask of the events that can cause an ADC -//! trigger event. -//! -//! This function enables the timer events that can cause an ADC trigger event. -//! The ADC trigger events are specified in the \e ui32ADCEvent parameter by -//! passing in the logical OR of any of the following values: -//! -//! - \b TIMER_ADC_MODEMATCH_B - Enables the mode match ADC trigger for timer -//! B. -//! - \b TIMER_ADC_CAPEVENT_B - Enables the capture event ADC trigger for -//! timer B. -//! - \b TIMER_ADC_CAPMATCH_B - Enables the capture match ADC trigger for -//! timer B. -//! - \b TIMER_ADC_TIMEOUT_B - Enables the timeout ADC trigger for timer B. -//! - \b TIMER_ADC_MODEMATCH_A - Enables the mode match ADC trigger for timer -//! A. -//! - \b TIMER_ADC_RTC_A - Enables the RTC ADC trigger for timer A. -//! - \b TIMER_ADC_CAPEVENT_A - Enables the capture event ADC trigger for -//! timer A. -//! - \b TIMER_ADC_CAPMATCH_A - Enables the capture match ADC trigger for -//! timer A. -//! - \b TIMER_ADC_TIMEOUT_A - Enables the timeout ADC trigger for timer A. -//! -//! \note The ability to specify ADC event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the ADC triggers. - // - HWREG(ui32Base + TIMER_O_ADCEV) = ui32ADCEvent; -} - -//***************************************************************************** -// -//! Returns the events that can cause an ADC trigger event. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function returns the timer events that can cause an ADC trigger event. -//! The ADC trigger events are the logical OR of any of the following values: -//! -//! - \b TIMER_ADC_MODEMATCH_B - The mode match ADC trigger for timer B is -//! enabled. -//! - \b TIMER_ADC_CAPEVENT_B - The capture event ADC trigger for timer B is -//! enabled. -//! - \b TIMER_ADC_CAPMATCH_B - The capture match ADC trigger for timer B is -//! enabled. -//! - \b TIMER_ADC_TIMEOUT_B - The timeout ADC trigger for timer B is enabled. -//! - \b TIMER_ADC_MODEMATCH_A - The mode match ADC trigger for timer A is -//! enabled. -//! - \b TIMER_ADC_RTC_A - The RTC ADC trigger for timer A is enabled. -//! - \b TIMER_ADC_CAPEVENT_A - The capture event ADC trigger for timer A is -//! enabled. -//! - \b TIMER_ADC_CAPMATCH_A - The capture match ADC trigger for timer A is -//! enabled. -//! - \b TIMER_ADC_TIMEOUT_A - The timeout ADC trigger for timer A is enabled. -//! -//! \note The ability to specify ADC event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return The timer events that trigger the ADC. -// -//***************************************************************************** -uint32_t -TimerADCEventGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return the current ADC triggers. - // - return(HWREG(ui32Base + TIMER_O_ADCEV)); -} - -//***************************************************************************** -// -//! Enables the events that can trigger a uDMA request. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32DMAEvent is a bit mask of the events that can trigger uDMA. -//! -//! This function enables the timer events that can trigger the start of a uDMA -//! sequence. The uDMA trigger events are specified in the \e ui32DMAEvent -//! parameter by passing in the logical OR of the following values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - The mode match uDMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPEVENT_B - The capture event uDMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_B - The capture match uDMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_B - The timeout uDMA trigger for timer B is enabled. -//! - \b TIMER_DMA_MODEMATCH_A - The mode match uDMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_RTC_A - The RTC uDMA trigger for timer A is enabled. -//! - \b TIMER_DMA_CAPEVENT_A - The capture event uDMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_A - The capture match uDMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_A - The timeout uDMA trigger for timer A is enabled. -//! -//! \note The ability to specify uDMA event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Set the uDMA triggers. - // - HWREG(ui32Base + TIMER_O_DMAEV) = ui32DMAEvent; -} - -//***************************************************************************** -// -//! Returns the events that can trigger a uDMA request. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! This function returns the timer events that can trigger the start of a uDMA -//! sequence. The uDMA trigger events are the logical OR of the following -//! values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match uDMA trigger for timer -//! B. -//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event uDMA trigger for -//! timer B. -//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match uDMA trigger for -//! timer B. -//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout uDMA trigger for timer B. -//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match uDMA trigger for timer -//! A. -//! - \b TIMER_DMA_RTC_A - Enables the RTC uDMA trigger for timer A. -//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event uDMA trigger for -//! timer A. -//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match uDMA trigger for -//! timer A. -//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout uDMA trigger for timer A. -//! -//! \note The ability to specify uDMA event triggers varies with the Tiva -//! part in use. Please consult the data sheet for the part you are -//! using to determine whether this support is available. -//! -//! \return The timer events that trigger the uDMA. -// -//***************************************************************************** -uint32_t -TimerDMAEventGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_TimerBaseValid(ui32Base)); - - // - // Return the current uDMA triggers. - // - return(HWREG(ui32Base + TIMER_O_DMAEV)); -} - -//***************************************************************************** -// -//! This function configures the update of timer load and match settings. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ui32Config is a combination of the updates methods for the timers -//! specified in the \e ui32Timer parameter. -//! -//! This function configures how the timer updates the timer load and match -//! values for the timers. The \e ui32Timer values can be \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH to apply the settings in \e ui32Config to -//! either timer or both timers. If the timer is not split then the \b TIMER_A -//! should be used. The \e ui32Config values affects when the TimerLoadSet() -//! and TimerLoadSet64() values take effect. -//! -//! - \b TIMER_UP_LOAD_IMMEDIATE is the default mode that causes the -//! TimerLoadSet() or TimerLoadSet64() to update the timer counter immediately. -//! - \b TIMER_UP_LOAD_TIMEOUT causes the TimerLoadSet() or TimerLoadSet64() to -//! update the timer when it counts down to zero. -//! -//! Similarly the \e ui32Config value affects when the TimerMatchSet() and -//! TimerMatchSet64() values take effect. -//! -//! - \b TIMER_UP_MATCH_IMMEDIATE is the default mode that causes the -//! TimerMatchSet() or TimerMatchSet64() to update the timer match value -//! immediately. -//! - \b TIMER_UP_MATCH_TIMEOUT causes the TimerMatchSet() or TimerMatchSet64() -//! to update the timer match value when it counts down to zero. -//! -//! \note These settings have no effect if the timer is not in count down mode -//! and are mostly useful when operating in PWM mode to allow for synchronous -//! update of timer match and load values. -//! -//! \return None. -// -//***************************************************************************** -void -TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Config) -{ - uint32_t ui32Value; - - if((ui32Timer & TIMER_A) == TIMER_A) - { - ui32Value = HWREG(ui32Base + TIMER_O_TAMR) & ~(0x00000500); - ui32Value |= ui32Config; - HWREG(ui32Base + TIMER_O_TAMR) = ui32Value; - } - - if((ui32Timer & TIMER_B) == TIMER_B) - { - ui32Value = HWREG(ui32Base + TIMER_O_TBMR) & ~(0x00000500); - ui32Value |= ui32Config; - HWREG(ui32Base + TIMER_O_TBMR) = ui32Value; - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.h b/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.h deleted file mode 100644 index 7eb619a7e0..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/tiva_timer.h +++ /dev/null @@ -1,301 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_TIMER_H__ -#define __DRIVERLIB_TIMER_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ui32Config parameter. -// -//***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count - // timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count - // timer -#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output -#define TIMER_CFG_A_ACT_TOINTD 0x00010000 // Timer A compare action disable - // time-out interrupt. -#define TIMER_CFG_A_ACT_NONE 0x00000000 // Timer A compare action none. -#define TIMER_CFG_A_ACT_TOGGLE 0x00020000 // Timer A compare action toggle. -#define TIMER_CFG_A_ACT_CLRTO 0x00040000 // Timer A compare action CCP - // clear on time-out. -#define TIMER_CFG_A_ACT_SETTO 0x00060000 // Timer A compare action CCP set - // on time-out. -#define TIMER_CFG_A_ACT_SETTOGTO 0x00080000 // Timer A compare action set CCP - // toggle on time-out. -#define TIMER_CFG_A_ACT_CLRTOGTO 0x000A0000 // Timer A compare action clear - // CCP toggle on time-out. -#define TIMER_CFG_A_ACT_SETCLRTO 0x000C0000 // Timer A compare action set CCP - // clear on time-out. -#define TIMER_CFG_A_ACT_CLRSETTO 0x000E0000 // Timer A compare action clear - // CCP set on time-out. -#define TIMER_CFG_B_ACT_TOINTD 0x00100000 // Timer B compare action disable - // time-out interrupt. -#define TIMER_CFG_B_ACT_NONE 0x00000000 // Timer A compare action none. -#define TIMER_CFG_B_ACT_TOGGLE 0x00200000 // Timer A compare action toggle. -#define TIMER_CFG_B_ACT_CLRTO 0x00400000 // Timer A compare action CCP - // clear on time-out. -#define TIMER_CFG_B_ACT_SETTO 0x00600000 // Timer A compare action CCP set - // on time-out. -#define TIMER_CFG_B_ACT_SETTOGTO 0x00800000 // Timer A compare action set CCP - // toggle on time-out. -#define TIMER_CFG_B_ACT_CLRTOGTO 0x00A00000 // Timer A compare action clear - // CCP toggle on time-out. -#define TIMER_CFG_B_ACT_SETCLRTO 0x00C00000 // Timer A compare action set CCP - // clear on time-out. -#define TIMER_CFG_B_ACT_CLRSETTO 0x0000E000 // Timer A compare action clear - // CCP set on time-out. - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ui32IntFlags parameter, and returned from -// TimerIntStatus. -// -//***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Complete Interrupt. -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Complete Interrupt. -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ui32Event parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ui32Timer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Values that can be passed to TimerSynchronize as the ui32Timers parameter. -// -//***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B -#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A -#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B -#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A -#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B -#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A -#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B -#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A -#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B -#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A -#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B -#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A -#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B -#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A -#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B -#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A -#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B - -//***************************************************************************** -// -// Values that can be passed to TimerClockSourceSet() or returned from -// TimerClockSourceGet(). -// -//***************************************************************************** -#define TIMER_CLOCK_SYSTEM 0x00000000 -#define TIMER_CLOCK_PIOSC 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to TimerDMAEventSet() or returned from -// TimerDMAEventGet(). -// -//***************************************************************************** -#define TIMER_DMA_MODEMATCH_B 0x00000800 -#define TIMER_DMA_CAPEVENT_B 0x00000400 -#define TIMER_DMA_CAPMATCH_B 0x00000200 -#define TIMER_DMA_TIMEOUT_B 0x00000100 -#define TIMER_DMA_MODEMATCH_A 0x00000010 -#define TIMER_DMA_RTC_A 0x00000008 -#define TIMER_DMA_CAPEVENT_A 0x00000004 -#define TIMER_DMA_CAPMATCH_A 0x00000002 -#define TIMER_DMA_TIMEOUT_A 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to TimerADCEventSet() or returned from -// TimerADCEventGet(). -// -//***************************************************************************** -#define TIMER_ADC_MODEMATCH_B 0x00000800 -#define TIMER_ADC_CAPEVENT_B 0x00000400 -#define TIMER_ADC_CAPMATCH_B 0x00000200 -#define TIMER_ADC_TIMEOUT_B 0x00000100 -#define TIMER_ADC_MODEMATCH_A 0x00000010 -#define TIMER_ADC_RTC_A 0x00000008 -#define TIMER_ADC_CAPEVENT_A 0x00000004 -#define TIMER_ADC_CAPMATCH_A 0x00000002 -#define TIMER_ADC_TIMEOUT_A 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to TimerUpdateMode(). -// -//***************************************************************************** -#define TIMER_UP_LOAD_IMMEDIATE 0x00000000 -#define TIMER_UP_LOAD_TIMEOUT 0x00000100 -#define TIMER_UP_MATCH_IMMEDIATE \ - 0x00000000 -#define TIMER_UP_MATCH_TIMEOUT 0x00000400 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); -extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, - bool bInvert); -extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bEnable); -extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Event); -extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, - bool bStall); -extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, - bool bWait); -extern void TimerRTCEnable(uint32_t ui32Base); -extern void TimerRTCDisable(uint32_t ui32Base); -extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value); -extern uint64_t TimerLoadGet64(uint32_t ui32Base); -extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer); -extern uint64_t TimerValueGet64(uint32_t ui32Base); -extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Value); -extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value); -extern uint64_t TimerMatchGet64(uint32_t ui32Base); -extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); -extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked); -extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers); -extern uint32_t TimerClockSourceGet(uint32_t ui32Base); -extern void TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); -extern uint32_t TimerADCEventGet(uint32_t ui32Base); -extern void TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent); -extern uint32_t TimerDMAEventGet(uint32_t ui32Base); -extern void TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent); -extern void TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, - uint32_t ui32Config); -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_TIMER_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/uart.c b/bsp/tm4c129x-dk/libraries/driverlib/uart.c deleted file mode 100644 index 847f464cea..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/uart.c +++ /dev/null @@ -1,1994 +0,0 @@ -//***************************************************************************** -// -// uart.c - Driver for the UART. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "inc/hw_uart.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/uart.h" - -//***************************************************************************** -// -// The system clock divider defining the maximum baud rate supported by the -// UART. -// -//***************************************************************************** -#define UART_CLK_DIVIDER 8 - -//***************************************************************************** -// -// A mapping of UART base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32UARTIntMap[][2] = -{ - { UART0_BASE, INT_UART0_TM4C123 }, - { UART1_BASE, INT_UART1_TM4C123 }, - { UART2_BASE, INT_UART2_TM4C123 }, - { UART3_BASE, INT_UART3_TM4C123 }, - { UART4_BASE, INT_UART4_TM4C123 }, - { UART5_BASE, INT_UART5_TM4C123 }, - { UART6_BASE, INT_UART6_TM4C123 }, - { UART7_BASE, INT_UART7_TM4C123 }, -}; -static const uint_fast8_t g_ui8UARTIntMapRows = - sizeof(g_ppui32UARTIntMap) / sizeof(g_ppui32UARTIntMap[0]); -static const uint32_t g_ppui32UARTIntMapSnowflake[][2] = -{ - { UART0_BASE, INT_UART0_TM4C129 }, - { UART1_BASE, INT_UART1_TM4C129 }, - { UART2_BASE, INT_UART2_TM4C129 }, - { UART3_BASE, INT_UART3_TM4C129 }, - { UART4_BASE, INT_UART4_TM4C129 }, - { UART5_BASE, INT_UART5_TM4C129 }, - { UART6_BASE, INT_UART6_TM4C129 }, - { UART7_BASE, INT_UART7_TM4C129 }, -}; -static const uint_fast8_t g_ui8UARTIntMapRowsSnowflake = - sizeof(g_ppui32UARTIntMapSnowflake) / - sizeof(g_ppui32UARTIntMapSnowflake[0]); - -//***************************************************************************** -// -//! \internal -//! Checks a UART base address. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function determines if a UART port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_UARTBaseValid(uint32_t ui32Base) -{ - return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || - (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) || - (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) || - (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the UART interrupt number. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! Given a UART base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns a UART interrupt number, or 0 if \e ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -_UARTIntNumberGet(uint32_t ui32Base) -{ - uint_fast8_t ui8Idx, ui8Rows; - const uint32_t (*ppui32UARTIntMap)[2]; - - // - // Default interrupt map. - // - ppui32UARTIntMap = g_ppui32UARTIntMap; - ui8Rows = g_ui8UARTIntMapRows; - - if(CLASS_IS_TM4C129) - { - ppui32UARTIntMap = g_ppui32UARTIntMapSnowflake; - ui8Rows = g_ui8UARTIntMapRowsSnowflake; - } - - // - // Loop through the table that maps UART base addresses to interrupt - // numbers. - // - for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++) - { - // - // See if this base address matches. - // - if(ppui32UARTIntMap[ui8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32UARTIntMap[ui8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Sets the type of parity. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Parity specifies the type of parity to use. -//! -//! This function configures the type of parity to use for transmitting and -//! expect when receiving. The \e ui32Parity parameter must be one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two -//! parameters allow direct control of the parity bit; it is always either one -//! or zero based on the mode. -//! -//! \return None. -// -//***************************************************************************** -void -UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || - (ui32Parity == UART_CONFIG_PAR_EVEN) || - (ui32Parity == UART_CONFIG_PAR_ODD) || - (ui32Parity == UART_CONFIG_PAR_ONE) || - (ui32Parity == UART_CONFIG_PAR_ZERO)); - - // - // Set the parity mode. - // - HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & - ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); -} - -//***************************************************************************** -// -//! Gets the type of parity currently being used. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function gets the type of parity used for transmitting data and -//! expected when receiving data. -//! -//! \return Returns the current parity settings, specified as one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. -// -//***************************************************************************** -uint32_t -UARTParityModeGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the current parity setting. - // - return(HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Sets the FIFO level at which interrupts are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one -//! of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, -//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of -//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, -//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function configures the FIFO level at which transmit and receive -//! interrupts are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, - uint32_t ui32RxLevel) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || - (ui32TxLevel == UART_FIFO_TX2_8) || - (ui32TxLevel == UART_FIFO_TX4_8) || - (ui32TxLevel == UART_FIFO_TX6_8) || - (ui32TxLevel == UART_FIFO_TX7_8)); - ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || - (ui32RxLevel == UART_FIFO_RX2_8) || - (ui32RxLevel == UART_FIFO_RX4_8) || - (ui32RxLevel == UART_FIFO_RX6_8) || - (ui32RxLevel == UART_FIFO_RX7_8)); - - // - // Set the FIFO interrupt levels. - // - HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; -} - -//***************************************************************************** -// -//! Gets the FIFO level at which interrupts are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, -//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, -//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, -//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, -//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function gets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Read the FIFO level register. - // - ui32Temp = HWREG(ui32Base + UART_O_IFLS); - - // - // Extract the transmit and receive FIFO levels. - // - *pui32TxLevel = ui32Temp & UART_IFLS_TX_M; - *pui32RxLevel = ui32Temp & UART_IFLS_RX_M; -} - -//***************************************************************************** -// -//! Sets the configuration of a UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param ui32Baud is the desired baud rate. -//! \param ui32Config is the data format for the port (number of data bits, -//! number of stop bits, and parity). -//! -//! This function configures the UART for operation in the specified data -//! format. The baud rate is provided in the \e ui32Baud parameter and the -//! data format in the \e ui32Config parameter. -//! -//! The \e ui32Config parameter is the logical OR of three values: the number -//! of data bits, the number of stop bits, and the parity. -//! \b UART_CONFIG_WLEN_8, \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and -//! \b UART_CONFIG_WLEN_5 select from eight to five data bits per byte -//! (respectively). \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select -//! one or two stop bits (respectively). \b UART_CONFIG_PAR_NONE, -//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, -//! and \b UART_CONFIG_PAR_ZERO select the parity mode (no parity bit, even -//! parity bit, odd parity bit, parity bit always one, and parity bit always -//! zero, respectively). -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! The function disables the UART by calling UARTDisable() before changing the -//! the parameters and enables the UART by calling UARTEnable(). -//! -//! For Tiva parts that have the ability to specify the UART baud clock -//! source (via UARTClockSourceSet()), the peripheral clock can be changed to -//! PIOSC. In this case, the peripheral clock should be specified as -//! 16,000,000 (the nominal rate of PIOSC). -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config) -{ - uint32_t ui32Div; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT(ui32Baud != 0); - ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER)); - - // - // Stop the UART. - // - UARTDisable(ui32Base); - - // - // Is the required baud rate greater than the maximum rate supported - // without the use of high speed mode? - // - if((ui32Baud * 16) > ui32UARTClk) - { - // - // Enable high speed mode. - // - HWREG(ui32Base + UART_O_CTL) |= UART_CTL_HSE; - - // - // Half the supplied baud rate to compensate for enabling high speed - // mode. This allows the following code to be common to both cases. - // - ui32Baud /= 2; - } - else - { - // - // Disable high speed mode. - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_HSE); - } - - // - // Compute the fractional baud rate divider. - // - ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; - - // - // Set the baud rate. - // - HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; - HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ui32Base + UART_O_LCRH) = ui32Config; - - // - // Clear the flags register. - // - HWREG(ui32Base + UART_O_FR) = 0; - - // - // Start the UART. - // - UARTEnable(ui32Base); -} - -//***************************************************************************** -// -//! Gets the current configuration of a UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param pui32Baud is a pointer to storage for the baud rate. -//! \param pui32Config is a pointer to storage for the data format. -//! -//! This function determines the baud rate and data format for the UART, given -//! an explicitly provided peripheral clock (hence the ExpClk suffix). The -//! returned baud rate is the actual baud rate; it may not be the exact baud -//! rate requested or an ``official'' baud rate. The data format returned in -//! \e pui32Config is enumerated the same as the \e ui32Config parameter of -//! UARTConfigSetExpClk(). -//! -//! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet() for TM4C123x -//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, -//! or it can be explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet() or fetch of the -//! variable call holding the return value of SysCtlClockFreqSet()). -//! -//! For Tiva parts that have the ability to specify the UART baud clock -//! source (via UARTClockSourceSet()), the peripheral clock can be changed to -//! PIOSC. In this case, the peripheral clock should be specified as -//! 16,000,000 (the nominal rate of PIOSC). -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config) -{ - uint32_t ui32Int, ui32Frac; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Compute the baud rate. - // - ui32Int = HWREG(ui32Base + UART_O_IBRD); - ui32Frac = HWREG(ui32Base + UART_O_FBRD); - *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); - - // - // See if high speed mode enabled. - // - if(HWREG(ui32Base + UART_O_CTL) & UART_CTL_HSE) - { - // - // High speed mode is enabled so the actual baud rate is actually - // double what was just calculated. - // - *pui32Baud *= 2; - } - - // - // Get the parity, data length, and number of stop bits. - // - *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function enables the UART and its transmit and receive FIFOs. -//! -//! \return None. -// -//***************************************************************************** -void -UARTEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; - - // - // Enable RX, TX, and the UART. - // - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Disables transmitting and receiving. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables the UART, waits for the end of transmission of the -//! current character, and flushes the transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait for end of TX. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // - // Disable the UART. - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Enables the transmit and receive FIFOs. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This functions enables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; -} - -//***************************************************************************** -// -//! Disables the transmit and receive FIFOs. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFODisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); -} - -//***************************************************************************** -// -//! Enables SIR (IrDA) mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bLowPower indicates if SIR Low Power Mode is to be used. -//! -//! This function enables SIR (IrDA) mode on the UART. If the \e bLowPower -//! flag is set, then SIR low power mode will be selected as well. This -//! function only has an effect if the UART has not been enabled by a call to -//! UARTEnable(). The call UARTEnableSIR() must be made before a call to -//! UARTConfigSetExpClk() because the UARTConfigSetExpClk() function calls the -//! UARTEnable() function. Another option is to call UARTDisable() followed by -//! UARTEnableSIR() and then enable the UART by calling UARTEnable(). -//! -//! \note The availability of SIR (IrDA) operation varies with the Tiva -//! part in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTEnableSIR(uint32_t ui32Base, bool bLowPower) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable SIR and SIRLP (if appropriate). - // - if(bLowPower) - { - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP); - } - else - { - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN); - } -} - -//***************************************************************************** -// -//! Disables SIR (IrDA) mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables SIR(IrDA) mode on the UART. This function only has -//! an effect if the UART has not been enabled by a call to UARTEnable(). The -//! call UARTEnableSIR() must be made before a call to UARTConfigSetExpClk() -//! because the UARTConfigSetExpClk() function calls the UARTEnable() function. -//! Another option is to call UARTDisable() followed by UARTEnableSIR() and -//! then enable the UART by calling UARTEnable(). -//! -//! \note The availability of SIR (IrDA) operation varies with the Tiva -//! part in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDisableSIR(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable SIR and SIRLP (if appropriate). - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP); -} - -//***************************************************************************** -// -//! Enables ISO7816 smart card mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function enables the SMART control bit for the ISO7816 smart card mode -//! on the UART. This call also sets 8-bit word length and even parity as -//! required by ISO7816. -//! -//! \note The availability of ISO7816 smart card mode varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTSmartCardEnable(uint32_t ui32Base) -{ - uint32_t ui32Val; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set 8-bit word length, even parity, 2 stop bits (note that although the - // STP2 bit is ignored when in smartcard mode, this code lets the caller - // read back the actual setting in use). - // - ui32Val = HWREG(ui32Base + UART_O_LCRH); - ui32Val &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN | - UART_LCRH_WLEN_M); - ui32Val |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | - UART_LCRH_STP2; - HWREG(ui32Base + UART_O_LCRH) = ui32Val; - - // - // Enable SMART mode. - // - HWREG(ui32Base + UART_O_CTL) |= UART_CTL_SMART; -} - -//***************************************************************************** -// -//! Disables ISO7816 smart card mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function clears the SMART (ISO7816 smart card) bit in the UART -//! control register. -//! -//! \note The availability of ISO7816 smart card mode varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTSmartCardDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable the SMART bit. - // - HWREG(ui32Base + UART_O_CTL) &= ~UART_CTL_SMART; -} - -//***************************************************************************** -// -//! Sets the states of the DTR and/or RTS modem control signals. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Control is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function configures the states of the DTR or RTS modem handshake -//! outputs from the UART. -//! -//! The \e ui32Control parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_DTR - The modem control DTR signal -//! - \b UART_OUTPUT_RTS - The modem control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); - - // - // Set the appropriate modem control output bits. - // - ui32Temp = HWREG(ui32Base + UART_O_CTL); - ui32Temp |= (ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); - HWREG(ui32Base + UART_O_CTL) = ui32Temp; -} - -//***************************************************************************** -// -//! Clears the states of the DTR and/or RTS modem control signals. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Control is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function clears the states of the DTR or RTS modem handshake outputs -//! from the UART. -//! -//! The \e ui32Control parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_DTR - The modem control DTR signal -//! - \b UART_OUTPUT_RTS - The modem control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0); - - // - // Set the appropriate modem control output bits. - // - ui32Temp = HWREG(ui32Base + UART_O_CTL); - ui32Temp &= ~(ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); - HWREG(ui32Base + UART_O_CTL) = ui32Temp; -} - -//***************************************************************************** -// -//! Gets the states of the DTR and RTS modem control signals. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current states of each of the two UART modem -//! control signals, DTR and RTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signals. This value is -//! a logical OR combination of values \b UART_OUTPUT_RTS and -//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the -//! associated signal is asserted. -// -//***************************************************************************** -uint32_t -UARTModemControlGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - - return(HWREG(ui32Base + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR)); -} - -//***************************************************************************** -// -//! Gets the states of the RI, DCD, DSR and CTS modem status signals. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current states of each of the four UART modem -//! status signals, RI, DCD, DSR and CTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! Tiva part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signals. This value -//! is a logical OR combination of values \b UART_INPUT_RI, -//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the -//! presence of each flag indicates that the associated signal is asserted. -// -//***************************************************************************** -uint32_t -UARTModemStatusGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == UART1_BASE); - - return(HWREG(ui32Base + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD | - UART_INPUT_CTS | UART_INPUT_DSR)); -} - -//***************************************************************************** -// -//! Sets the UART hardware flow control mode to be used. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Mode indicates the flow control modes to be used. This -//! parameter is a logical OR combination of values \b UART_FLOWCONTROL_TX and -//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) -//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. -//! -//! This function configures the required hardware flow control modes. If -//! \e ui32Mode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted -//! if the incoming CTS signal is asserted. If \e ui32Mode contains flag -//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is -//! asserted only when there is space available in the receive FIFO. If no -//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be -//! passed. -//! -//! \note The availability of hardware flow control varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Mode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); - - // - // Set the flow control mode as requested. - // - HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & - ~(UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)) | ui32Mode); -} - -//***************************************************************************** -// -//! Returns the UART hardware flow control mode currently in use. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current hardware flow control mode. -//! -//! \note The availability of hardware flow control varies with the Tiva -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns the current flow control mode in use. This value is a -//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit -//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) -//! flow control is in use. If hardware flow control is disabled, -//! \b UART_FLOWCONTROL_NONE is returned. -// -//***************************************************************************** -uint32_t -UARTFlowControlGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - return(HWREG(ui32Base + UART_O_CTL) & (UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)); -} - -//***************************************************************************** -// -//! Sets the operating mode for the UART transmit interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Mode is the operating mode for the transmit interrupt. It may -//! be \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is -//! idle or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit -//! FIFO level. -//! -//! This function allows the mode of the UART transmit interrupt to be set. By -//! default, the transmit interrupt is asserted when the FIFO level falls past -//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this -//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the -//! transmit interrupt is asserted once the transmitter is completely idle - -//! the transmit FIFO is empty and all bits, including any stop bits, have -//! cleared the transmitter. -//! -//! \note The availability of end-of-transmission mode varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Mode == UART_TXINT_MODE_EOT) || - (ui32Mode == UART_TXINT_MODE_FIFO)); - - // - // Set or clear the EOT bit of the UART control register as appropriate. - // - HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & - ~(UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)) | ui32Mode); -} - -//***************************************************************************** -// -//! Returns the current operating mode for the UART transmit interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current operating mode for the UART transmit -//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit -//! interrupt is currently configured to be asserted once the transmitter is -//! completely idle - the transmit FIFO is empty and all bits, including any -//! stop bits, have cleared the transmitter. The return value is -//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based -//! on the level of the transmit FIFO. -//! -//! \note The availability of end-of-transmission mode varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. -// -//***************************************************************************** -uint32_t -UARTTxIntModeGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the current transmit interrupt mode. - // - return(HWREG(ui32Base + UART_O_CTL) & (UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)); -} - -//***************************************************************************** -// -//! Determines if there are any characters in the receive FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \return Returns \b true if there is data in the receive FIFO or \b false -//! if there is no data in the receive FIFO. -// -//***************************************************************************** -bool -UARTCharsAvail(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the availability of characters. - // - return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); -} - -//***************************************************************************** -// -//! Determines if there is any space in the transmit FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \return Returns \b true if there is space available in the transmit FIFO -//! or \b false if there is no space available in the transmit FIFO. -// -//***************************************************************************** -bool -UARTSpaceAvail(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the availability of space. - // - return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); -} - -//***************************************************************************** -// -//! Receives a character from the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e int32_t. A \b -1 is returned if there are no characters present in the -//! receive FIFO. The UARTCharsAvail() function should be called before -//! attempting to call this function. -// -//***************************************************************************** -int32_t -UARTCharGetNonBlocking(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ui32Base + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} - -//***************************************************************************** -// -//! Waits for a character from the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. If there are no characters available, this function waits until a -//! character is received before returning. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e int32_t. -// -//***************************************************************************** -int32_t -UARTCharGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait until a char is available. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the char. - // - return(HWREG(ui32Base + UART_O_DR)); -} - -//***************************************************************************** -// -//! Sends a character to the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function writes the character \e ucData to the transmit FIFO for the -//! specified port. This function does not block, so if there is no space -//! available, then a \b false is returned and the application must retry the -//! function later. -//! -//! \return Returns \b true if the character was successfully placed in the -//! transmit FIFO or \b false if there was no space available in the transmit -//! FIFO. -// -//***************************************************************************** -bool -UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ui32Base + UART_O_DR) = ucData; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} - -//***************************************************************************** -// -//! Waits to send a character from the specified port. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function sends the character \e ucData to the transmit FIFO for the -//! specified port. If there is no space available in the transmit FIFO, this -//! function waits until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -UARTCharPut(uint32_t ui32Base, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait until space is available. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ui32Base + UART_O_DR) = ucData; -} - -//***************************************************************************** -// -//! Causes a BREAK to be sent. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bBreakState controls the output level. -//! -//! Calling this function with \e bBreakState set to \b true asserts a break -//! condition on the UART. Calling this function with \e bBreakState set to -//! \b false removes the break condition. For proper transmission of a break -//! command, the break must be asserted for at least two complete frames. -//! -//! \return None. -// -//***************************************************************************** -void -UARTBreakCtl(uint32_t ui32Base, bool bBreakState) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set the break condition as requested. - // - HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); -} - -//***************************************************************************** -// -//! Determines whether the UART transmitter is busy or not. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function allows the caller to determine whether all transmitted bytes -//! have cleared the transmitter hardware. If \b false is returned, the -//! transmit FIFO is empty and all bits of the last transmitted character, -//! including all stop bits, have left the hardware shift register. -//! -//! \return Returns \b true if the UART is transmitting or \b false if all -//! transmissions are complete. -// -//***************************************************************************** -bool -UARTBusy(uint32_t ui32Base) -{ - // - // Check the argument. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Determine if the UART is busy. - // - return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? true : false); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a UART interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the UART port. - // - ui32Int = _UARTIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the UART interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a UART interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a UART interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the UART port. - // - ui32Int = _UARTIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b UART_INT_9BIT - 9-bit Address Match interrupt -//! - \b UART_INT_OE - Overrun Error interrupt -//! - \b UART_INT_BE - Break Error interrupt -//! - \b UART_INT_PE - Parity Error interrupt -//! - \b UART_INT_FE - Framing Error interrupt -//! - \b UART_INT_RT - Receive Timeout interrupt -//! - \b UART_INT_TX - Transmit interrupt -//! - \b UART_INT_RX - Receive interrupt -//! - \b UART_INT_DSR - DSR interrupt -//! - \b UART_INT_DCD - DCD interrupt -//! - \b UART_INT_CTS - CTS interrupt -//! - \b UART_INT_RI - RI interrupt -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable the specified interrupts. - // - HWREG(ui32Base + UART_O_IM) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable the specified interrupts. - // - HWREG(ui32Base + UART_O_IM) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified UART. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in UARTIntEnable(). -// -//***************************************************************************** -uint32_t -UARTIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + UART_O_MIS)); - } - else - { - return(HWREG(ui32Base + UART_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to UARTIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Clear the requested interrupt sources. - // - HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Enable UART uDMA operation. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the uDMA features to enable. -//! -//! The specified UART uDMA features are enabled. The UART can be -//! configured to use uDMA for transmit or receive and to disable -//! receive if an error occurs. The \e ui32DMAFlags parameter is the -//! logical OR of any of the following values: -//! -//! - \b UART_DMA_RX - enable uDMA for receive -//! - \b UART_DMA_TX - enable uDMA for transmit -//! - \b UART_DMA_ERR_RXSTOP - disable uDMA receive on UART error -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set the requested bits in the UART uDMA control register. - // - HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! Disable UART uDMA operation. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the uDMA features to disable. -//! -//! This function is used to disable UART uDMA features that were enabled -//! by UARTDMAEnable(). The specified UART uDMA features are disabled. The -//! \e ui32DMAFlags parameter is the logical OR of any of the following values: -//! -//! - \b UART_DMA_RX - disable uDMA for receive -//! - \b UART_DMA_TX - disable uDMA for transmit -//! - \b UART_DMA_ERR_RXSTOP - do not disable uDMA receive on UART error -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Clear the requested bits in the UART uDMA control register. - // - HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -//! Gets current receiver errors. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the current state of each of the 4 receiver error -//! sources. The returned errors are equivalent to the four error bits -//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately when the -//! overrun occurs rather than when a character is next read. -//! -//! \return Returns a logical OR combination of the receiver error flags, -//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK -//! and \b UART_RXERROR_OVERRUN. -// -//***************************************************************************** -uint32_t -UARTRxErrorGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the current value of the receive status register. - // - return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); -} - -//***************************************************************************** -// -//! Clears all reported receiver errors. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function is used to clear all receiver error conditions reported via -//! UARTRxErrorGet(). If using the overrun, framing error, parity error or -//! break interrupts, this function must be called after clearing the interrupt -//! to ensure that later errors of the same type trigger another interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -UARTRxErrorClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Any write to the Error Clear Register clears all bits which are - // currently set. - // - HWREG(ui32Base + UART_O_ECR) = 0; -} - -//***************************************************************************** -// -//! Sets the baud clock source for the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Source is the baud clock source for the UART. -//! -//! This function allows the baud clock source for the UART to be selected. -//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b UART_CLOCK_PIOSC). -//! -//! Changing the baud clock source changes the baud rate generated by the -//! UART. Therefore, the baud rate should be reconfigured after any change to -//! the baud clock source. -//! -//! \note The ability to specify the UART baud clock source varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - ASSERT((ui32Source == UART_CLOCK_SYSTEM) || - (ui32Source == UART_CLOCK_PIOSC)); - - // - // Set the UART clock source. - // - HWREG(ui32Base + UART_O_CC) = ui32Source; -} - -//***************************************************************************** -// -//! Gets the baud clock source for the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function returns the baud clock source for the specified UART. The -//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or -//! the precision internal oscillator (\b UART_CLOCK_PIOSC). -//! -//! \note The ability to specify the UART baud clock source varies with the -//! Tiva part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -UARTClockSourceGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Return the UART clock source. - // - return(HWREG(ui32Base + UART_O_CC)); -} - -//***************************************************************************** -// -//! Enables 9-bit mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function enables the 9-bit operational mode of the UART. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Enable 9-bit mode. - // - HWREG(ui32Base + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN; -} - -//***************************************************************************** -// -//! Disables 9-bit mode on the specified UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function disables the 9-bit operational mode of the UART. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Disable 9-bit mode. - // - HWREG(ui32Base + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN; -} - -//***************************************************************************** -// -//! Sets the device address(es) for 9-bit mode. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Addr is the device address. -//! \param ui8Mask is the device address mask. -//! -//! This function configures the device address or range of device addresses -//! that respond to requests on the 9-bit UART port. The received address is -//! masked with the mask and then compared against the given address, allowing -//! either a single address (if \b ui8Mask is 0xff) or a set of addresses to be -//! matched. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, - uint8_t ui8Mask) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Set the address and mask. - // - HWREG(ui32Base + UART_O_9BITADDR) = ui8Addr << UART_9BITADDR_ADDR_S; - HWREG(ui32Base + UART_O_9BITAMASK) = ui8Mask << UART_9BITAMASK_MASK_S; -} - -//***************************************************************************** -// -//! Sends an address character from the specified port when operating in 9-bit -//! mode. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Addr is the address to be transmitted. -//! -//! This function waits until all data has been sent from the specified port -//! and then sends the given address as an address byte. It then waits until -//! the address byte has been transmitted before returning. -//! -//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(), -//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive -//! data characters in 9-bit mode. -//! -//! \note The availability of 9-bit mode varies with the Tiva part in use. -//! Please consult the datasheet for the part you are using to determine -//! whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr) -{ - uint32_t ui32LCRH; - - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Wait until the FIFO is empty and the UART is not busy. - // - while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) != - UART_FR_TXFE) - { - } - - // - // Force the address/data bit to 1 to indicate this is an address byte. - // - ui32LCRH = HWREG(ui32Base + UART_O_LCRH); - HWREG(ui32Base + UART_O_LCRH) = ((ui32LCRH & ~UART_LCRH_EPS) | - UART_LCRH_SPS | UART_LCRH_PEN); - - // - // Send the address. - // - HWREG(ui32Base + UART_O_DR) = ui8Addr; - - // - // Wait until the address has been sent. - // - while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) != - UART_FR_TXFE) - { - } - - // - // Restore the address/data setting. - // - HWREG(ui32Base + UART_O_LCRH) = ui32LCRH; -} - -//***************************************************************************** -// -//! Enables internal loopback mode for a UART port -//! -//! \param ui32Base is the base address of the UART port. -//! -//! This function configures a UART port in internal loopback mode to help with -//! diagnostics and debug. In this mode, the transmit and receive terminals of -//! the same UART port are internally connected. Hence, the data transmitted -//! on the UnTx output is received on the UxRx input, without having to go -//! through I/O's. UARTCharPut(), UARTCharGet() functions can be used along -//! with this function. -//! -//! \return None. -// -//***************************************************************************** -void UARTLoopbackEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_UARTBaseValid(ui32Base)); - - // - // Write the Loopback Enable bit to register. - // - HWREG(ui32Base + UART_O_CTL) |= UART_CTL_LBE; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/udma.c b/bsp/tm4c129x-dk/libraries/driverlib/udma.c deleted file mode 100644 index bb2941af92..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/udma.c +++ /dev/null @@ -1,1382 +0,0 @@ -//***************************************************************************** -// -// udma.c - Driver for the micro-DMA controller. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup udma_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_sysctl.h" -#include "inc/hw_types.h" -#include "inc/hw_udma.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/udma.h" - -//***************************************************************************** -// -//! Enables the uDMA controller for use. -//! -//! This function enables the uDMA controller. The uDMA controller must be -//! enabled before it can be configured and used. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAEnable(void) -{ - // - // Set the master enable bit in the config register. - // - HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; -} - -//***************************************************************************** -// -//! Disables the uDMA controller for use. -//! -//! This function disables the uDMA controller. Once disabled, the uDMA -//! controller cannot operate until re-enabled with uDMAEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMADisable(void) -{ - // - // Clear the master enable bit in the config register. - // - HWREG(UDMA_CFG) = 0; -} - -//***************************************************************************** -// -//! Gets the uDMA error status. -//! -//! This function returns the uDMA error status. It should be called from -//! within the uDMA error interrupt handler to determine if a uDMA error -//! occurred. -//! -//! \return Returns non-zero if a uDMA error is pending. -// -//***************************************************************************** -uint32_t -uDMAErrorStatusGet(void) -{ - // - // Return the uDMA error status. - // - return(HWREG(UDMA_ERRCLR)); -} - -//***************************************************************************** -// -//! Clears the uDMA error interrupt. -//! -//! This function clears a pending uDMA error interrupt. This function should -//! be called from within the uDMA error interrupt handler to clear the -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAErrorStatusClear(void) -{ - // - // Clear the uDMA error interrupt. - // - HWREG(UDMA_ERRCLR) = 1; -} - -//***************************************************************************** -// -//! Enables a uDMA channel for operation. -//! -//! \param ui32ChannelNum is the channel number to enable. -//! -//! This function enables a specific uDMA channel for use. This function must -//! be used to enable a channel before it can be used to perform a uDMA -//! transfer. -//! -//! When a uDMA transfer is completed, the channel is automatically disabled by -//! the uDMA controller. Therefore, this function should be called prior to -//! starting up any new transfer. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelEnable(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable set register. - // - HWREG(UDMA_ENASET) = 1 << (ui32ChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Disables a uDMA channel for operation. -//! -//! \param ui32ChannelNum is the channel number to disable. -//! -//! This function disables a specific uDMA channel. Once disabled, a channel -//! cannot respond to uDMA transfer requests until re-enabled via -//! uDMAChannelEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelDisable(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable clear register. - // - HWREG(UDMA_ENACLR) = 1 << (ui32ChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Checks if a uDMA channel is enabled for operation. -//! -//! \param ui32ChannelNum is the channel number to check. -//! -//! This function checks to see if a specific uDMA channel is enabled. This -//! function can be used to check the status of a transfer, as the channel is -//! automatically disabled at the end of a transfer. -//! -//! \return Returns \b true if the channel is enabled, \b false if disabled. -// -//***************************************************************************** -bool -uDMAChannelIsEnabled(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // AND the specified channel bit with the enable register and return the - // result. - // - return((HWREG(UDMA_ENASET) & (1 << (ui32ChannelNum & 0x1f))) ? true : - false); -} - -//***************************************************************************** -// -//! Sets the base address for the channel control table. -//! -//! \param psControlTable is a pointer to the 1024-byte-aligned base address -//! of the uDMA channel control table. -//! -//! This function configures the base address of the channel control table. -//! This table resides in system memory and holds control information for each -//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base -//! address must be configured before any of the channel functions can be used. -//! -//! The size of the channel control table depends on the number of uDMA -//! channels and the transfer modes that are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAControlBaseSet(void *psControlTable) -{ - // - // Check the arguments. - // - ASSERT(((uint32_t)psControlTable & ~0x3FF) == - (uint32_t)psControlTable); - ASSERT((uint32_t)psControlTable >= 0x20000000); - - // - // Program the base address into the register. - // - HWREG(UDMA_CTLBASE) = (uint32_t)psControlTable; -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -void * -uDMAControlBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_CTLBASE)); -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -void * -uDMAControlAlternateBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_ALTBASE)); -} - -//***************************************************************************** -// -//! Requests a uDMA channel to start a transfer. -//! -//! \param ui32ChannelNum is the channel number on which to request a uDMA -//! transfer. -//! -//! This function allows software to request a uDMA channel to begin a -//! transfer. This function could be used for performing a memory-to-memory -//! transfer, or if for some reason a transfer needs to be initiated by -//! software instead of the peripheral associated with that channel. -//! -//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then -//! the completion is signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion is signaled on the -//! peripheral's interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelRequest(uint32_t ui32ChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the software uDMA request register. - // - HWREG(UDMA_SWREQ) = 1 << (ui32ChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Enables attributes of a uDMA channel. -//! -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! -//! This function is used to enable attributes of a uDMA channel. -//! -//! The \e ui32Attr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Set the useburst bit for this channel if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_USEBURSTSET) = 1 << ui32ChannelNum; - } - - // - // Set the alternate control select bit for this channel, - // if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_ALTSET) = 1 << ui32ChannelNum; - } - - // - // Set the high priority bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_PRIOSET) = 1 << ui32ChannelNum; - } - - // - // Set the request mask bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_REQMASKSET) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -//! Disables attributes of a uDMA channel. -//! -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! -//! This function is used to disable attributes of a uDMA channel. -//! -//! The \e ui32Attr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr) -{ - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Clear the useburst bit for this channel if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_USEBURSTCLR) = 1 << ui32ChannelNum; - } - - // - // Clear the alternate control select bit for this channel, if set in - // ui32Config. - // - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum; - } - - // - // Clear the high priority bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_PRIOCLR) = 1 << ui32ChannelNum; - } - - // - // Clear the request mask bit for this channel, if set in ui32Config. - // - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_REQMASKCLR) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -//! Gets the enabled attributes of a uDMA channel. -//! -//! \param ui32ChannelNum is the channel to configure. -//! -//! This function returns a combination of flags representing the attributes of -//! the uDMA channel. -//! -//! \return Returns the logical OR of the attributes of the uDMA channel, which -//! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -uint32_t -uDMAChannelAttributeGet(uint32_t ui32ChannelNum) -{ - uint32_t ui32Attr = 0; - - // - // Check the arguments. - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Check to see if useburst bit is set for this channel. - // - if(HWREG(UDMA_USEBURSTSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_USEBURST; - } - - // - // Check to see if the alternate control bit is set for this channel. - // - if(HWREG(UDMA_ALTSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_ALTSELECT; - } - - // - // Check to see if the high priority bit is set for this channel. - // - if(HWREG(UDMA_PRIOSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // - // Check to see if the request mask bit is set for this channel. - // - if(HWREG(UDMA_REQMASKSET) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_REQMASK; - } - - // - // Return the configuration flags. - // - return(ui32Attr); -} - -//***************************************************************************** -// -//! Sets the control parameters for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ui32Control is logical OR of several control values to set the -//! control parameters for the channel. -//! -//! This function is used to set control parameters for a uDMA transfer. These -//! parameters are typically not changed often. -//! -//! The \e ui32ChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ui32Control parameter is the logical OR of five values: the data -//! size, the source address increment, the destination address increment, the -//! arbitration size, and the use burst flag. The choices available for each -//! of these values is described below. -//! -//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or -//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. -//! -//! Choose the source address increment from one of \b UDMA_SRC_INC_8, -//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or -//! to select non-incrementing. -//! -//! Choose the destination address increment from one of \b UDMA_DST_INC_8, -//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or -//! to select non-incrementing. -//! -//! The arbitration size determines how many items are transferred before -//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size -//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, -//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 -//! items, in powers of 2. -//! -//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only -//! respond to burst requests at the tail end of a scatter-gather transfer. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control) -{ - tDMAControlTable *psCtl; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - // - psCtl[ui32ChannelStructIndex].ui32Control = - ((psCtl[ui32ChannelStructIndex].ui32Control & - ~(UDMA_CHCTL_DSTINC_M | - UDMA_CHCTL_DSTSIZE_M | - UDMA_CHCTL_SRCINC_M | - UDMA_CHCTL_SRCSIZE_M | - UDMA_CHCTL_ARBSIZE_M | - UDMA_CHCTL_NXTUSEBURST)) | - ui32Control); -} - -//***************************************************************************** -// -//! Sets the transfer parameters for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ui32Mode is the type of uDMA transfer. -//! \param pvSrcAddr is the source address for the transfer. -//! \param pvDstAddr is the destination address for the transfer. -//! \param ui32TransferSize is the number of data items to transfer. -//! -//! This function is used to configure the parameters for a uDMA transfer. -//! These parameters are not typically changed often. The function -//! uDMAChannelControlSet() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \e ui32ChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ui32Mode parameter should be one of the following values: -//! -//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once -//! started even if the request is removed. -//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This mode -//! allows use of ping-pong buffering for uDMA transfers. -//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather -//! transfer. -//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather -//! transfer. -//! -//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler takes care of this alignment if -//! the pointers are pointing to storage of the appropriate data type. -//! -//! The \e ui32TransferSize parameter is the number of data items, not the -//! number of bytes. -//! -//! The two scatter-gather modes, memory and peripheral, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function looks for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and sets the -//! scatter-gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using uDMAChannelEnable() after calling -//! this function. The transfer does not begin until the channel has been -//! configured and enabled. Note that the channel is automatically disabled -//! after the transfer is completed, meaning that uDMAChannelEnable() must be -//! called again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results are unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, - void *pvSrcAddr, void *pvDstAddr, - uint32_t ui32TransferSize) -{ - tDMAControlTable *psControlTable; - uint32_t ui32Control; - uint32_t ui32Inc; - uint32_t ui32BufferBytes; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((uint32_t)pvSrcAddr >= 0x20000000); - ASSERT((uint32_t)pvDstAddr >= 0x20000000); - ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= 1024)); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off the mode and size - // fields. - // - ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // Adjust the mode if the alt control structure is selected. - // - if(ui32ChannelStructIndex & UDMA_ALT_SELECT) - { - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Mode |= UDMA_MODE_ALT_SELECT; - } - } - - // - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - // - ui32Control |= ui32Mode | ((ui32TransferSize - 1) << 4); - - // - // Get the address increment value for the source, from the control word. - // - ui32Inc = (ui32Control & UDMA_CHCTL_SRCINC_M); - - // - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - // - if(ui32Inc != UDMA_SRC_INC_NONE) - { - ui32Inc = ui32Inc >> 26; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1); - } - - // - // Load the source ending address into the control block. - // - psControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // - // Get the address increment value for the destination, from the control - // word. - // - ui32Inc = ui32Control & UDMA_CHCTL_DSTINC_M; - - // - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - // - if(ui32Inc != UDMA_DST_INC_NONE) - { - // - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer must point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - // - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&psControlTable[ui32ChannelStructIndex | - UDMA_ALT_SELECT].ui32Spare; - } - // - // Not a scatter-gather transfer, calculate end pointer normally. - // - else - { - ui32Inc = ui32Inc >> 30; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); - } - } - - // - // Load the destination ending address into the control block. - // - psControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // - // Write the new control word value. - // - psControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; -} - -//***************************************************************************** -// -//! Configures a uDMA channel for scatter-gather mode. -//! -//! \param ui32ChannelNum is the uDMA channel number. -//! \param ui32TaskCount is the number of scatter-gather tasks to execute. -//! \param pvTaskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral -//! scatter-gather transfer (else it is memory scatter-gather transfer) -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list and must pass a pointer to -//! the start of the task list as the \e pvTaskList parameter. The -//! \e ui32TaskCount parameter is the count of tasks in the task list, not the -//! size of the task list. The flag \e bIsPeriphSG should be used to indicate -//! if scatter-gather should be configured for peripheral or memory -//! operation. -//! -//! \sa uDMATaskStructEntry -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount, - void *pvTaskList, uint32_t ui32IsPeriphSG) -{ - tDMAControlTable *psControlTable; - tDMAControlTable *psTaskTable; - - // - // Check the parameters - // - ASSERT((ui32ChannelNum & 0xffff) < 32); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ui32TaskCount <= 1024); - ASSERT(ui32TaskCount != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelNum parameter, extract just the channel number - // from this parameter. - // - ui32ChannelNum &= 0x1f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get a handy pointer to the task list - // - psTaskTable = (tDMAControlTable *)pvTaskList; - - // - // Compute the ending address for the source pointer. This address is the - // last element of the last task in the task table - // - psControlTable[ui32ChannelNum].pvSrcEndAddr = - &psTaskTable[ui32TaskCount - 1].ui32Spare; - - // - // Compute the ending address for the destination pointer. This address - // is the end of the alternate structure for this channel. - // - psControlTable[ui32ChannelNum].pvDstEndAddr = - &psControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; - - // - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - // - psControlTable[ui32ChannelNum].ui32Control = - (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | - UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | - UDMA_CHCTL_ARBSIZE_4 | - (((ui32TaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | - (ui32IsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : - UDMA_CHCTL_XFERMODE_MEM_SG)); - - // - // Scatter-gather operations can leave the alt bit set. So if doing - // back to back scatter-gather transfers, the second attempt may not - // work correctly because the alt bit is set. Therefore, clear the - // alt bit here to ensure that it is always cleared before a new SG - // transfer is started. - // - HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! Gets the current transfer size for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the uDMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items is returned. If the transfer is -//! complete, then 0 is returned. -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -uint32_t -uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *psControlTable; - uint32_t ui32Control; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off all but the size field - // and the mode field. - // - ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & - (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer - // - if(ui32Control == 0) - { - return(0); - } - - // - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - // - else - { - // - // Shift the size field and add one, then return to user. - // - return((ui32Control >> 4) + 1); - } -} - -//***************************************************************************** -// -//! Gets the transfer mode for a uDMA channel control structure. -//! -//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the transfer mode for the uDMA channel and -//! to query the status of a transfer on a channel. When the transfer is -//! complete the mode is \b UDMA_MODE_STOP. -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which is one of the following values: \b UDMA_MODE_STOP, -//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. -// -//***************************************************************************** -uint32_t -uDMAChannelModeGet(uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *psControlTable; - uint32_t ui32Control; - - // - // Check the arguments. - // - ASSERT((ui32ChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the ui32ChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ui32ChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE); - - // - // Get the current control word value and mask off all but the mode field. - // - ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control & - UDMA_CHCTL_XFERMODE_M); - - // - // Check if scatter/gather mode, and if so, mask off the alt bit. - // - if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == - UDMA_MODE_MEM_SCATTER_GATHER) || - ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Control &= ~UDMA_MODE_ALT_SELECT; - } - - // - // Return the mode to the caller. - // - return(ui32Control); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the uDMA controller. -//! -//! \param ui32IntChannel identifies which uDMA interrupt is to be registered. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This function registers and enables the handler to be called when the uDMA -//! controller generates an interrupt. The \e ui32IntChannel parameter should -//! be one of the following: -//! -//! - \b INT_UDMA to register an interrupt handler to process interrupts -//! from the uDMA software channel (UDMA_CHANNEL_SW) -//! - \b INT_UDMAERR to register an interrupt handler to process uDMA error -//! interrupts -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note The interrupt handler for the uDMA is for transfer completion when -//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The -//! interrupts for each peripheral channel are handled through the individual -//! peripheral interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler); - - // - // Register the interrupt handler. - // - IntRegister(ui32IntChannel, pfnHandler); - - // - // Enable the memory management fault. - // - IntEnable(ui32IntChannel); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the uDMA controller. -//! -//! \param ui32IntChannel identifies which uDMA interrupt to unregister. -//! -//! This function disables and unregisters the handler to be called for the -//! specified uDMA interrupt. The \e ui32IntChannel parameter should be one of -//! \b INT_UDMA or \b INT_UDMAERR as documented for the function -//! uDMAIntRegister(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntUnregister(uint32_t ui32IntChannel) -{ - // - // Disable the interrupt. - // - IntDisable(ui32IntChannel); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32IntChannel); -} - -//***************************************************************************** -// -//! Gets the uDMA controller channel interrupt status. -//! -//! This function is used to get the interrupt status of the uDMA controller. -//! The returned value is a 32-bit bit mask that indicates which channels are -//! requesting an interrupt. This function can be used from within an -//! interrupt handler to determine or confirm which uDMA channel has requested -//! an interrupt. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. -//! -//! \return Returns a 32-bit mask which indicates requesting uDMA channels. -//! There is a bit for each channel and a 1 indicates that the channel -//! is requesting an interrupt. Multiple bits can be set. -// -//***************************************************************************** -uint32_t -uDMAIntStatus(void) -{ - // - // Return the value of the uDMA interrupt status register - // - return(HWREG(UDMA_CHIS)); -} - -//***************************************************************************** -// -//! Clears uDMA interrupt status. -//! -//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. -//! -//! This function clears bits in the uDMA interrupt status register according -//! to which bits are set in \e ui32ChanMask. There is one bit for each -//! channel. If a a bit is set in \e ui32ChanMask, then that corresponding -//! channel's interrupt status is cleared (if it was set). -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. Devices without the DMACHIS register have uDMA done status in -//! the interrupt registers in the peripheral memory maps. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntClear(uint32_t ui32ChanMask) -{ - // - // Clear the requested bits in the uDMA interrupt status register - // - HWREG(UDMA_CHIS) = ui32ChanMask; -} - -//***************************************************************************** -// -//! Assigns a peripheral mapping for a uDMA channel. -//! -//! \param ui32Mapping is a macro specifying the peripheral assignment for -//! a channel. -//! -//! This function assigns a peripheral mapping to a uDMA channel. It is -//! used to select which peripheral is used for a uDMA channel. The parameter -//! \e ui32Mapping should be one of the macros named \b UDMA_CHn_tttt from the -//! header file \e udma.h. For example, to assign uDMA channel 0 to the -//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX. -//! -//! Please consult the Tiva data sheet for a table showing all the -//! possible peripheral assignments for the uDMA channels for a particular -//! device. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for -//! your part. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAssign(uint32_t ui32Mapping) -{ - uint32_t ui32MapReg; - uint_fast8_t ui8MapShift; - uint_fast8_t ui8ChannelNum; - - // - // Check the parameters - // - ASSERT((ui32Mapping & 0xffffff00) < 0x00090000); - - // - // Extract the channel number and map encoding value from the parameter. - // - ui8ChannelNum = ui32Mapping & 0xff; - ui32Mapping = ui32Mapping >> 16; - - // - // Find the uDMA channel mapping register and shift value to use for this - // channel - // - ui32MapReg = UDMA_CHMAP0 + (uint32_t)((ui8ChannelNum / 8) * 4); - ui8MapShift = (ui8ChannelNum % 8) * 4; - - // - // Set the channel map encoding for this channel - // - HWREG(ui32MapReg) = (HWREG(ui32MapReg) & ~(0xf << ui8MapShift)) | - ui32Mapping << ui8MapShift; -} - -//***************************************************************************** -// -// The following functions are deprecated. Use uDMAChannelAssign() instead -// to accomplish the same end. -// -//***************************************************************************** -#ifndef DEPRECATED -//***************************************************************************** -// -//! Selects the secondary peripheral for a set of uDMA channels. -//! -//! \param ui32SecPeriphs is the logical OR of the uDMA channels for which to -//! use the secondary peripheral, instead of the default peripheral. -//! -//! This function is used to select the secondary peripheral assignment for a -//! set of uDMA channels. By selecting the secondary peripheral assignment for -//! a channel, the default peripheral assignment is no longer available for -//! that channel. -//! -//! The parameter \e ui32SecPeriphs can be the logical OR of any of the -//! following macros. If one of the macros below is in the list passed to this -//! function, then the secondary peripheral (marked as \b _SEC_) is selected. -//! -//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX -//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX -//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A -//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B -//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A -//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B -//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A -//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B -//! - \b UDMA_DEF_UART0RX_SEC_UART1RX -//! - \b UDMA_DEF_UART0TX_SEC_UART1TX -//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX -//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX -//! - \b UDMA_DEF_RESERVED_SEC_UART2RX -//! - \b UDMA_DEF_RESERVED_SEC_UART2TX -//! - \b UDMA_DEF_ADC00_SEC_TMR2A -//! - \b UDMA_DEF_ADC01_SEC_TMR2B -//! - \b UDMA_DEF_ADC02_SEC_RESERVED -//! - \b UDMA_DEF_ADC03_SEC_RESERVED -//! - \b UDMA_DEF_TMR0A_SEC_TMR1A -//! - \b UDMA_DEF_TMR0B_SEC_TMR1B -//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX -//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX -//! - \b UDMA_DEF_UART1RX_SEC_RESERVED -//! - \b UDMA_DEF_UART1TX_SEC_RESERVED -//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 -//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 -//! - \b UDMA_DEF_RESERVED_SEC_ADC12 -//! - \b UDMA_DEF_RESERVED_SEC_ADC13 -//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED -//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs) -{ - // - // Select the secondary peripheral for the specified channels. - // - HWREG(UDMA_CHASGN) |= ui32SecPeriphs; -} - -//***************************************************************************** -// -//! Selects the default peripheral for a set of uDMA channels. -//! -//! \param ui32DefPeriphs is the logical OR of the uDMA channels for which to -//! use the default peripheral, instead of the secondary peripheral. -//! -//! This function is used to select the default peripheral assignment for a set -//! of uDMA channels. -//! -//! The parameter \e ui32DefPeriphs can be the logical OR of any of the -//! following macros. If one of the macros below is in the list passed to this -//! function, then the default peripheral (marked as \b _DEF_) is selected. -//! -//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX -//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX -//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A -//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B -//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A -//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B -//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A -//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B -//! - \b UDMA_DEF_UART0RX_SEC_UART1RX -//! - \b UDMA_DEF_UART0TX_SEC_UART1TX -//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX -//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX -//! - \b UDMA_DEF_RESERVED_SEC_UART2RX -//! - \b UDMA_DEF_RESERVED_SEC_UART2TX -//! - \b UDMA_DEF_ADC00_SEC_TMR2A -//! - \b UDMA_DEF_ADC01_SEC_TMR2B -//! - \b UDMA_DEF_ADC02_SEC_RESERVED -//! - \b UDMA_DEF_ADC03_SEC_RESERVED -//! - \b UDMA_DEF_TMR0A_SEC_TMR1A -//! - \b UDMA_DEF_TMR0B_SEC_TMR1B -//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX -//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX -//! - \b UDMA_DEF_UART1RX_SEC_RESERVED -//! - \b UDMA_DEF_UART1TX_SEC_RESERVED -//! - \b UDMA_DEF_SSI1RX_SEC_ADC10 -//! - \b UDMA_DEF_SSI1TX_SEC_ADC11 -//! - \b UDMA_DEF_RESERVED_SEC_ADC12 -//! - \b UDMA_DEF_RESERVED_SEC_ADC13 -//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED -//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelSelectDefault(uint32_t ui32DefPeriphs) -{ - // - // Select the default peripheral for the specified channels. - // - HWREG(UDMA_CHASGN) &= ~ui32DefPeriphs; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/udma.h b/bsp/tm4c129x-dk/libraries/driverlib/udma.h deleted file mode 100644 index a8d3684489..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/udma.h +++ /dev/null @@ -1,890 +0,0 @@ -//***************************************************************************** -// -// udma.h - Prototypes and macros for the uDMA controller. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_UDMA_H__ -#define __DRIVERLIB_UDMA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup udma_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// A structure that defines an entry in the channel control table. These -// fields are used by the uDMA controller and normally it is not necessary for -// software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct -{ - // - // The ending source address of the data transfer. - // - volatile void *pvSrcEndAddr; - - // - // The ending destination address of the data transfer. - // - volatile void *pvDstEndAddr; - - // - // The channel control mode. - // - volatile uint32_t ui32Control; - - // - // An unused location. - // - volatile uint32_t ui32Spare; -} -tDMAControlTable; - -//***************************************************************************** -// -//! A helper macro for building scatter-gather task table entries. -//! -//! \param ui32TransferCount is the count of items to transfer for this task. -//! \param ui32ItemSize is the bit size of the items to transfer for this task. -//! \param ui32SrcIncrement is the bit size increment for source data. -//! \param pvSrcAddr is the starting address of the data to transfer. -//! \param ui32DstIncrement is the bit size increment for destination data. -//! \param pvDstAddr is the starting address of the destination data. -//! \param ui32ArbSize is the arbitration size to use for the transfer task. -//! \param ui32Mode is the transfer mode for this task. -//! -//! This macro is intended to be used to help populate a table of uDMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! The \e ui32TransferCount parameter is the number of items that will be -//! transferred by this task. It must be in the range 1-1024. -//! -//! The \e ui32ItemSize parameter is the bit size of the transfer data. It -//! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. -//! -//! The \e ui32SrcIncrement parameter is the increment size for the source -//! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, -//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. -//! -//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source -//! data. -//! -//! The \e ui32DstIncrement parameter is the increment size for the destination -//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, -//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. -//! -//! The \e pvDstAddr parameter is a void pointer to the beginning of the -//! location where the data will be transferred. -//! -//! The \e ui32ArbSize parameter is the arbitration size for the transfer, and -//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on -//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in -//! powers of 2, from 1 to 1024. -//! -//! The \e ui32Mode parameter is the mode to use for this transfer task. It -//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note -//! that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of tDMAControlTable type, like this: -//! -//! \verbatim -//! tDMAControlTable MyTaskList[] = -//! { -//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, -//! UDMA_SRC_INC_8, MySourceBuf, -//! UDMA_DST_INC_8, MyDestBuf, -//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), -//! uDMATaskStructEntry(Task2Count, ...), -//! } -//! \endverbatim -//! -//! \return Nothing; this is not a function. -// -//***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ - { \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | \ - (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ - } - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Flags that can be passed to uDMAChannelAttributeEnable(), -// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to uDMAModeSet() and returned -// uDMAModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Channel configuration values that can be passed to uDMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xc0000000 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_DST_PROT_PRIV 0x00200000 -#define UDMA_SRC_PROT_PRIV 0x00040000 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// Channel numbers to be passed to API functions that require a channel number -// ID. -// -//***************************************************************************** -#define UDMA_CHANNEL_USBEP1RX 0 -#define UDMA_CHANNEL_USBEP1TX 1 -#define UDMA_CHANNEL_USBEP2RX 2 -#define UDMA_CHANNEL_USBEP2TX 3 -#define UDMA_CHANNEL_USBEP3RX 4 -#define UDMA_CHANNEL_USBEP3TX 5 -#define UDMA_CHANNEL_ETH0RX 6 -#define UDMA_CHANNEL_ETH0TX 7 -#define UDMA_CHANNEL_UART0RX 8 -#define UDMA_CHANNEL_UART0TX 9 -#define UDMA_CHANNEL_SSI0RX 10 -#define UDMA_CHANNEL_SSI0TX 11 -#define UDMA_CHANNEL_ADC0 14 -#define UDMA_CHANNEL_ADC1 15 -#define UDMA_CHANNEL_ADC2 16 -#define UDMA_CHANNEL_ADC3 17 -#define UDMA_CHANNEL_TMR0A 18 -#define UDMA_CHANNEL_TMR0B 19 -#define UDMA_CHANNEL_TMR1A 20 -#define UDMA_CHANNEL_TMR1B 21 -#define UDMA_CHANNEL_UART1RX 22 -#define UDMA_CHANNEL_UART1TX 23 -#define UDMA_CHANNEL_SSI1RX 24 -#define UDMA_CHANNEL_SSI1TX 25 -#define UDMA_CHANNEL_I2S0RX 28 -#define UDMA_CHANNEL_I2S0TX 29 -#define UDMA_CHANNEL_SW 30 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 - -//***************************************************************************** -// -// Channel numbers to be passed to API functions that require a channel number -// ID. These are for secondary peripheral assignments. -// -//***************************************************************************** -#define UDMA_SEC_CHANNEL_UART2RX_0 \ - 0 -#define UDMA_SEC_CHANNEL_UART2TX_1 \ - 1 -#define UDMA_SEC_CHANNEL_TMR3A 2 -#define UDMA_SEC_CHANNEL_TMR3B 3 -#define UDMA_SEC_CHANNEL_TMR2A_4 \ - 4 -#define UDMA_SEC_CHANNEL_TMR2B_5 \ - 5 -#define UDMA_SEC_CHANNEL_TMR2A_6 \ - 6 -#define UDMA_SEC_CHANNEL_TMR2B_7 \ - 7 -#define UDMA_SEC_CHANNEL_UART1RX \ - 8 -#define UDMA_SEC_CHANNEL_UART1TX \ - 9 -#define UDMA_SEC_CHANNEL_SSI1RX 10 -#define UDMA_SEC_CHANNEL_SSI1TX 11 -#define UDMA_SEC_CHANNEL_UART2RX_12 \ - 12 -#define UDMA_SEC_CHANNEL_UART2TX_13 \ - 13 -#define UDMA_SEC_CHANNEL_TMR2A_14 \ - 14 -#define UDMA_SEC_CHANNEL_TMR2B_15 \ - 15 -#define UDMA_SEC_CHANNEL_TMR1A 18 -#define UDMA_SEC_CHANNEL_TMR1B 19 -#define UDMA_SEC_CHANNEL_EPI0RX 20 -#define UDMA_SEC_CHANNEL_EPI0TX 21 -#define UDMA_SEC_CHANNEL_ADC10 24 -#define UDMA_SEC_CHANNEL_ADC11 25 -#define UDMA_SEC_CHANNEL_ADC12 26 -#define UDMA_SEC_CHANNEL_ADC13 27 -#define UDMA_SEC_CHANNEL_SW 30 - -//***************************************************************************** -// -// Values that can be passed to uDMAChannelAssign() to select peripheral -// mapping for each channel. The channels named RESERVED may be assigned -// to a peripheral in future parts. -// -//***************************************************************************** -// -// Channel 0 -// -#define UDMA_CH0_USB0EP1RX 0x00000000 -#define UDMA_CH0_UART2RX 0x00010000 -#define UDMA_CH0_RESERVED2 0x00020000 -#define UDMA_CH0_TIMER4A 0x00030000 -#define UDMA_CH0_RESERVED4 0x00040000 -#define UDMA_CH0_RESERVED5 0x00050000 -#define UDMA_CH0_I2C0RX 0x00060000 -#define UDMA_CH0_RESERVED7 0x00070000 -#define UDMA_CH0_RESERVED8 0x00080000 - -// -// Channel 1 -// -#define UDMA_CH1_USB0EP1TX 0x00000001 -#define UDMA_CH1_UART2TX 0x00010001 -#define UDMA_CH1_RESERVED2 0x00020001 -#define UDMA_CH1_TIMER4B 0x00030001 -#define UDMA_CH1_RESERVED4 0x00040001 -#define UDMA_CH1_RESERVED5 0x00050001 -#define UDMA_CH1_I2C0TX 0x00060001 -#define UDMA_CH1_RESERVED7 0x00070001 -#define UDMA_CH1_RESERVED8 0x00080001 - -// -// Channel 2 -// -#define UDMA_CH2_USB0EP2RX 0x00000002 -#define UDMA_CH2_TIMER3A 0x00010002 -#define UDMA_CH2_RESERVED2 0x00020002 -#define UDMA_CH2_RESERVED3 0x00030002 -#define UDMA_CH2_RESERVED4 0x00040002 -#define UDMA_CH2_RESERVED5 0x00050002 -#define UDMA_CH2_I2C1RX 0x00060002 -#define UDMA_CH2_RESERVED7 0x00070002 -#define UDMA_CH2_RESERVED8 0x00080002 - -// -// Channel 3 -// -#define UDMA_CH3_USB0EP2TX 0x00000003 -#define UDMA_CH3_TIMER3B 0x00010003 -#define UDMA_CH3_RESERVED2 0x00020003 -#define UDMA_CH3_LPC0_3 0x00030003 -#define UDMA_CH3_RESERVED4 0x00040003 -#define UDMA_CH3_RESERVED5 0x00050003 -#define UDMA_CH3_I2C1TX 0x00060003 -#define UDMA_CH3_RESERVED7 0x00070003 -#define UDMA_CH3_RESERVED8 0x00080003 - -// -// Channel 4 -// -#define UDMA_CH4_USB0EP3RX 0x00000004 -#define UDMA_CH4_TIMER2A 0x00010004 -#define UDMA_CH4_RESERVED2 0x00020004 -#define UDMA_CH4_GPIOA 0x00030004 -#define UDMA_CH4_RESERVED4 0x00040004 -#define UDMA_CH4_SHAMD50CIN 0x00050004 -#define UDMA_CH4_I2C2RX 0x00060004 -#define UDMA_CH4_RESERVED7 0x00070004 -#define UDMA_CH4_RESERVED8 0x00080004 - -// -// Channel 5 -// -#define UDMA_CH5_USB0EP3TX 0x00000005 -#define UDMA_CH5_TIMER2B 0x00010005 -#define UDMA_CH5_RESERVED2 0x00020005 -#define UDMA_CH5_GPIOB 0x00030005 -#define UDMA_CH5_RESERVED4 0x00040005 -#define UDMA_CH5_SHAMD50DIN 0x00050005 -#define UDMA_CH5_I2C2TX 0x00060005 -#define UDMA_CH5_RESERVED7 0x00070005 -#define UDMA_CH5_RESERVED8 0x00080005 - -// -// Channel 6 -// -#define UDMA_CH6_RESERVED0 0x00000006 -#define UDMA_CH6_ETH0RX 0x00000006 -#define UDMA_CH6_TIMER2A 0x00010006 -#define UDMA_CH6_UART5RX 0x00020006 -#define UDMA_CH6_GPIOC 0x00030006 -#define UDMA_CH6_I2C0RX 0x00040006 -#define UDMA_CH6_SHAMD50COUT 0x00050006 -#define UDMA_CH6_RESERVED6 0x00060006 -#define UDMA_CH6_RESERVED7 0x00070006 -#define UDMA_CH6_RESERVED8 0x00080006 - -// -// Channel 7 -// -#define UDMA_CH7_RESERVED0 0x00000007 -#define UDMA_CH7_ETH0TX 0x00000007 -#define UDMA_CH7_TIMER2B 0x00010007 -#define UDMA_CH7_UART5TX 0x00020007 -#define UDMA_CH7_GPIOD 0x00030007 -#define UDMA_CH7_I2C0TX 0x00040007 -#define UDMA_CH7_RESERVED5 0x00050007 -#define UDMA_CH7_RESERVED6 0x00060007 -#define UDMA_CH7_RESERVED7 0x00070007 -#define UDMA_CH7_RESERVED8 0x00080007 - -// -// Channel 8 -// -#define UDMA_CH8_UART0RX 0x00000008 -#define UDMA_CH8_UART1RX 0x00010008 -#define UDMA_CH8_RESERVED2 0x00020008 -#define UDMA_CH8_TIMER5A 0x00030008 -#define UDMA_CH8_I2C1RX 0x00040008 -#define UDMA_CH8_RESERVED5 0x00050008 -#define UDMA_CH8_RESERVED6 0x00060008 -#define UDMA_CH8_RESERVED7 0x00070008 -#define UDMA_CH8_RESERVED8 0x00080008 - -// -// Channel 9 -// -#define UDMA_CH9_UART0TX 0x00000009 -#define UDMA_CH9_UART1TX 0x00010009 -#define UDMA_CH9_RESERVED2 0x00020009 -#define UDMA_CH9_TIMER5B 0x00030009 -#define UDMA_CH9_I2C1TX 0x00040009 -#define UDMA_CH9_RESERVED5 0x00050009 -#define UDMA_CH9_RESERVED6 0x00060009 -#define UDMA_CH9_RESERVED7 0x00070009 -#define UDMA_CH9_RESERVED8 0x00080009 - -// -// Channel 10 -// -#define UDMA_CH10_SSI0RX 0x0000000A -#define UDMA_CH10_SSI1RX 0x0001000A -#define UDMA_CH10_UART6RX 0x0002000A -#define UDMA_CH10_WTIMER0A 0x0003000A -#define UDMA_CH10_I2C2RX 0x0004000A -#define UDMA_CH10_RESERVED5 0x0005000A -#define UDMA_CH10_RESERVED6 0x0006000A -#define UDMA_CH10_TIMER6A 0x0007000A -#define UDMA_CH10_RESERVED8 0x0008000A - -// -// Channel 11 -// -#define UDMA_CH11_SSI0TX 0x0000000B -#define UDMA_CH11_SSI1TX 0x0001000B -#define UDMA_CH11_UART6TX 0x0002000B -#define UDMA_CH11_WTIMER0B 0x0003000B -#define UDMA_CH11_I2C2TX 0x0004000B -#define UDMA_CH11_RESERVED5 0x0005000B -#define UDMA_CH11_RESERVED6 0x0006000B -#define UDMA_CH11_TIMER6B 0x0007000B -#define UDMA_CH11_RESERVED8 0x0008000B - -// -// Channel 12 -// -#define UDMA_CH12_RESERVED0 0x0000000C -#define UDMA_CH12_UART2RX 0x0001000C -#define UDMA_CH12_SSI2RX 0x0002000C -#define UDMA_CH12_WTIMER1A 0x0003000C -#define UDMA_CH12_GPIOK 0x0004000C -#define UDMA_CH12_AES0CIN 0x0005000C -#define UDMA_CH12_RESERVED6 0x0006000C -#define UDMA_CH12_TIMER7A 0x0007000C -#define UDMA_CH12_RESERVED8 0x0008000C - -// -// Channel 13 -// -#define UDMA_CH13_RESERVED0 0x0000000D -#define UDMA_CH13_UART2TX 0x0001000D -#define UDMA_CH13_SSI2TX 0x0002000D -#define UDMA_CH13_WTIMER1B 0x0003000D -#define UDMA_CH13_GPIOL 0x0004000D -#define UDMA_CH13_AES0COUT 0x0005000D -#define UDMA_CH13_RESERVED6 0x0006000D -#define UDMA_CH13_TIMER7B 0x0007000D -#define UDMA_CH13_RESERVED8 0x0008000D - -// -// Channel 14 -// -#define UDMA_CH14_ADC0_0 0x0000000E -#define UDMA_CH14_TIMER2A 0x0001000E -#define UDMA_CH14_SSI3RX 0x0002000E -#define UDMA_CH14_GPIOE 0x0003000E -#define UDMA_CH14_GPIOM 0x0004000E -#define UDMA_CH14_AES0DIN 0x0005000E -#define UDMA_CH14_RESERVED6 0x0006000E -#define UDMA_CH14_RESERVED7 0x0007000E -#define UDMA_CH14_RESERVED8 0x0008000E - -// -// Channel 15 -// -#define UDMA_CH15_ADC0_1 0x0000000F -#define UDMA_CH15_TIMER2B 0x0001000F -#define UDMA_CH15_SSI3TX 0x0002000F -#define UDMA_CH15_GPIOF 0x0003000F -#define UDMA_CH15_GPION 0x0004000F -#define UDMA_CH15_AES0DOUT 0x0005000F -#define UDMA_CH15_RESERVED6 0x0006000F -#define UDMA_CH15_RESERVED7 0x0007000F -#define UDMA_CH15_RESERVED8 0x0008000F - -// -// Channel 16 -// -#define UDMA_CH16_ADC0_2 0x00000010 -#define UDMA_CH16_RESERVED1 0x00010010 -#define UDMA_CH16_UART3RX 0x00020010 -#define UDMA_CH16_WTIMER2A 0x00030010 -#define UDMA_CH16_GPIOP 0x00040010 -#define UDMA_CH16_RESERVED5 0x00050010 -#define UDMA_CH16_RESERVED6 0x00060010 -#define UDMA_CH16_RESERVED7 0x00070010 -#define UDMA_CH16_RESERVED8 0x00080010 - -// -// Channel 17 -// -#define UDMA_CH17_ADC0_3 0x00000011 -#define UDMA_CH17_RESERVED1 0x00010011 -#define UDMA_CH17_UART3TX 0x00020011 -#define UDMA_CH17_WTIMER2B 0x00030011 -#define UDMA_CH17_RESERVED4 0x00040011 -#define UDMA_CH17_RESERVED5 0x00050011 -#define UDMA_CH17_RESERVED6 0x00060011 -#define UDMA_CH17_RESERVED7 0x00070011 -#define UDMA_CH17_RESERVED8 0x00080011 - -// -// Channel 18 -// -#define UDMA_CH18_TIMER0A 0x00000012 -#define UDMA_CH18_TIMER1A 0x00010012 -#define UDMA_CH18_UART4RX 0x00020012 -#define UDMA_CH18_GPIOB 0x00030012 -#define UDMA_CH18_I2C3RX 0x00040012 -#define UDMA_CH18_RESERVED5 0x00050012 -#define UDMA_CH18_RESERVED6 0x00060012 -#define UDMA_CH18_RESERVED7 0x00070012 -#define UDMA_CH18_RESERVED8 0x00080012 - -// -// Channel 19 -// -#define UDMA_CH19_TIMER0B 0x00000013 -#define UDMA_CH19_TIMER1B 0x00010013 -#define UDMA_CH19_UART4TX 0x00020013 -#define UDMA_CH19_GPIOG 0x00030013 -#define UDMA_CH19_I2C3TX 0x00040013 -#define UDMA_CH19_RESERVED5 0x00050013 -#define UDMA_CH19_RESERVED6 0x00060013 -#define UDMA_CH19_RESERVED7 0x00070013 -#define UDMA_CH19_RESERVED8 0x00080013 - -// -// Channel 20 -// -#define UDMA_CH20_TIMER1A 0x00000014 -#define UDMA_CH20_RESERVED1 0x00010014 -#define UDMA_CH20_EPI0RX 0x00010014 -#define UDMA_CH20_UART7RX 0x00020014 -#define UDMA_CH20_GPIOH 0x00030014 -#define UDMA_CH20_I2C4RX 0x00040014 -#define UDMA_CH20_DES0CIN 0x00050014 -#define UDMA_CH20_RESERVED6 0x00060014 -#define UDMA_CH20_RESERVED7 0x00070014 -#define UDMA_CH20_RESERVED8 0x00080014 - -// -// Channel 21 -// -#define UDMA_CH21_TIMER1B 0x00000015 -#define UDMA_CH21_RESERVED1 0x00010015 -#define UDMA_CH21_EPI0TX 0x00010015 -#define UDMA_CH21_UART7TX 0x00020015 -#define UDMA_CH21_GPIOJ 0x00030015 -#define UDMA_CH21_I2C4TX 0x00040015 -#define UDMA_CH21_DES0DIN 0x00050015 -#define UDMA_CH21_RESERVED6 0x00060015 -#define UDMA_CH21_RESERVED7 0x00070015 -#define UDMA_CH21_RESERVED8 0x00080015 - -// -// Channel 22 -// -#define UDMA_CH22_UART1RX 0x00000016 -#define UDMA_CH22_RESERVED1 0x00010016 -#define UDMA_CH22_RESERVED2 0x00020016 -#define UDMA_CH22_LPC0_2 0x00030016 -#define UDMA_CH22_I2C5RX 0x00040016 -#define UDMA_CH22_DES0DOUT 0x00050016 -#define UDMA_CH22_RESERVED6 0x00060016 -#define UDMA_CH22_RESERVED7 0x00070016 -#define UDMA_CH22_I2C8RX 0x00080016 - -// -// Channel 23 -// -#define UDMA_CH23_UART1TX 0x00000017 -#define UDMA_CH23_RESERVED1 0x00010017 -#define UDMA_CH23_RESERVED2 0x00020017 -#define UDMA_CH23_LPC0_1 0x00030017 -#define UDMA_CH23_I2C5TX 0x00040017 -#define UDMA_CH23_RESERVED5 0x00050017 -#define UDMA_CH23_RESERVED6 0x00060017 -#define UDMA_CH23_RESERVED7 0x00070017 -#define UDMA_CH23_I2C8TX 0x00080017 - -// -// Channel 24 -// -#define UDMA_CH24_SSI1RX 0x00000018 -#define UDMA_CH24_ADC1_0 0x00010018 -#define UDMA_CH24_RESERVED2 0x00020018 -#define UDMA_CH24_WTIMER3A 0x00030018 -#define UDMA_CH24_GPIOQ 0x00040018 -#define UDMA_CH24_RESERVED5 0x00050018 -#define UDMA_CH24_RESERVED6 0x00060018 -#define UDMA_CH24_RESERVED7 0x00070018 -#define UDMA_CH24_I2C9RX 0x00080018 - -// -// Channel 25 -// -#define UDMA_CH25_SSI1TX 0x00000019 -#define UDMA_CH25_ADC1_1 0x00010019 -#define UDMA_CH25_RESERVED2 0x00020019 -#define UDMA_CH25_WTIMER3B 0x00030019 -#define UDMA_CH25_RESERVED4 0x00040019 -#define UDMA_CH25_RESERVED5 0x00050019 -#define UDMA_CH25_RESERVED6 0x00060019 -#define UDMA_CH25_RESERVED7 0x00070019 -#define UDMA_CH25_I2C9TX 0x00080019 - -// -// Channel 26 -// -#define UDMA_CH26_RESERVED0 0x0000001A -#define UDMA_CH26_ADC1_2 0x0001001A -#define UDMA_CH26_RESERVED2 0x0002001A -#define UDMA_CH26_WTIMER4A 0x0003001A -#define UDMA_CH26_RESERVED4 0x0004001A -#define UDMA_CH26_RESERVED5 0x0005001A -#define UDMA_CH26_RESERVED6 0x0006001A -#define UDMA_CH26_RESERVED7 0x0007001A -#define UDMA_CH26_I2C6RX 0x0008001A - -// -// Channel 27 -// -#define UDMA_CH27_RESERVED0 0x0000001B -#define UDMA_CH27_ADC1_3 0x0001001B -#define UDMA_CH27_RESERVED2 0x0002001B -#define UDMA_CH27_WTIMER4B 0x0003001B -#define UDMA_CH27_RESERVED4 0x0004001B -#define UDMA_CH27_RESERVED5 0x0005001B -#define UDMA_CH27_RESERVED6 0x0006001B -#define UDMA_CH27_RESERVED7 0x0007001B -#define UDMA_CH27_I2C6TX 0x0008001B - -// -// Channel 28 -// -#define UDMA_CH28_RESERVED0 0x0000001C -#define UDMA_CH28_RESERVED1 0x0001001C -#define UDMA_CH28_RESERVED2 0x0002001C -#define UDMA_CH28_WTIMER5A 0x0003001C -#define UDMA_CH28_RESERVED4 0x0004001C -#define UDMA_CH28_RESERVED5 0x0005001C -#define UDMA_CH28_RESERVED6 0x0006001C -#define UDMA_CH28_RESERVED7 0x0007001C -#define UDMA_CH28_I2C7RX 0x0008001C - -// -// Channel 29 -// -#define UDMA_CH29_RESERVED0 0x0000001D -#define UDMA_CH29_RESERVED1 0x0001001D -#define UDMA_CH29_RESERVED2 0x0002001D -#define UDMA_CH29_WTIMER5B 0x0003001D -#define UDMA_CH29_RESERVED4 0x0004001D -#define UDMA_CH29_RESERVED5 0x0005001D -#define UDMA_CH29_RESERVED6 0x0006001D -#define UDMA_CH29_RESERVED7 0x0007001D -#define UDMA_CH29_I2C7TX 0x0008001D - -// -// Channel 30 -// -#define UDMA_CH30_SW 0x0000001E -#define UDMA_CH30_RESERVED1 0x0001001E -#define UDMA_CH30_RESERVED2 0x0002001E -#define UDMA_CH30_RESERVED3 0x0003001E -#define UDMA_CH30_RESERVED4 0x0004001E -#define UDMA_CH30_RESERVED5 0x0005001E -#define UDMA_CH30_RESERVED6 0x0006001E -#define UDMA_CH30_EPI0RX 0x0007001E -#define UDMA_CH30_1WIRE0 0x0008001E - -// -// Channel 31 -// -#define UDMA_CH31_RESERVED0 0x0000001F -#define UDMA_CH31_RESERVED1 0x0001001F -#define UDMA_CH31_RESERVED2 0x0002001F -#define UDMA_CH31_LPC0_0 0x0003001F -#define UDMA_CH31_RESERVED4 0x0004001F -#define UDMA_CH31_RESERVED5 0x0005001F -#define UDMA_CH31_RESERVED6 0x0006001F -#define UDMA_CH31_EPI0RX 0x0007001F -#define UDMA_CH31_RESERVED8 0x0008001F - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void uDMAEnable(void); -extern void uDMADisable(void); -extern uint32_t uDMAErrorStatusGet(void); -extern void uDMAErrorStatusClear(void); -extern void uDMAChannelEnable(uint32_t ui32ChannelNum); -extern void uDMAChannelDisable(uint32_t ui32ChannelNum); -extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum); -extern void uDMAControlBaseSet(void *pControlTable); -extern void *uDMAControlBaseGet(void); -extern void *uDMAControlAlternateBaseGet(void); -extern void uDMAChannelRequest(uint32_t ui32ChannelNum); -extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, - uint32_t ui32Attr); -extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, - uint32_t ui32Attr); -extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum); -extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, - uint32_t ui32Control); -extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, - void *pvDstAddr, uint32_t ui32TransferSize); -extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, - void *pvTaskList, - uint32_t ui32IsPeriphSG); -extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex); -extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex); -extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)); -extern void uDMAIntUnregister(uint32_t ui32IntChannel); -extern uint32_t uDMAIntStatus(void); -extern void uDMAIntClear(uint32_t ui32ChanMask); -extern void uDMAChannelAssign(uint32_t ui32Mapping); - -//***************************************************************************** -// -// The following functions and definitions are deprecated and will be removed -// from the API in the future. Use uDMAChannelAssign() instead to accomplish -// the same end. -// -//***************************************************************************** -#ifndef DEPRECATED -//***************************************************************************** -// -// uDMA default/secondary peripheral selections, to be passed to -// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). -// -//***************************************************************************** -#define UDMA_DEF_USBEP1RX_SEC_UART2RX \ - 0x00000001 -#define UDMA_DEF_USBEP1TX_SEC_UART2TX \ - 0x00000002 -#define UDMA_DEF_USBEP2RX_SEC_TMR3A \ - 0x00000004 -#define UDMA_DEF_USBEP2TX_SEC_TMR3B \ - 0x00000008 -#define UDMA_DEF_USBEP3RX_SEC_TMR2A \ - 0x00000010 -#define UDMA_DEF_USBEP3TX_SEC_TMR2B \ - 0x00000020 -#define UDMA_DEF_ETH0RX_SEC_TMR2A \ - 0x00000040 -#define UDMA_DEF_ETH0TX_SEC_TMR2B \ - 0x00000080 -#define UDMA_DEF_UART0RX_SEC_UART1RX \ - 0x00000100 -#define UDMA_DEF_UART0TX_SEC_UART1TX \ - 0x00000200 -#define UDMA_DEF_SSI0RX_SEC_SSI1RX \ - 0x00000400 -#define UDMA_DEF_SSI0TX_SEC_SSI1TX \ - 0x00000800 -#define UDMA_DEF_RESERVED_SEC_UART2RX \ - 0x00001000 -#define UDMA_DEF_RESERVED_SEC_UART2TX \ - 0x00002000 -#define UDMA_DEF_ADC00_SEC_TMR2A \ - 0x00004000 -#define UDMA_DEF_ADC01_SEC_TMR2B \ - 0x00008000 -#define UDMA_DEF_ADC02_SEC_RESERVED \ - 0x00010000 -#define UDMA_DEF_ADC03_SEC_RESERVED \ - 0x00020000 -#define UDMA_DEF_TMR0A_SEC_TMR1A \ - 0x00040000 -#define UDMA_DEF_TMR0B_SEC_TMR1B \ - 0x00080000 -#define UDMA_DEF_TMR1A_SEC_EPI0RX \ - 0x00100000 -#define UDMA_DEF_TMR1B_SEC_EPI0TX \ - 0x00200000 -#define UDMA_DEF_UART1RX_SEC_RESERVED \ - 0x00400000 -#define UDMA_DEF_UART1TX_SEC_RESERVED \ - 0x00800000 -#define UDMA_DEF_SSI1RX_SEC_ADC10 \ - 0x01000000 -#define UDMA_DEF_SSI1TX_SEC_ADC11 \ - 0x02000000 -#define UDMA_DEF_RESERVED_SEC_ADC12 \ - 0x04000000 -#define UDMA_DEF_RESERVED_SEC_ADC13 \ - 0x08000000 -#define UDMA_DEF_I2S0RX_SEC_RESERVED \ - 0x10000000 -#define UDMA_DEF_I2S0TX_SEC_RESERVED \ - 0x20000000 - -extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs); -extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs); - -#endif -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_UDMA_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.c b/bsp/tm4c129x-dk/libraries/driverlib/watchdog.c deleted file mode 100644 index e1761ff747..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.c +++ /dev/null @@ -1,622 +0,0 @@ -//***************************************************************************** -// -// watchdog.c - Driver for the Watchdog Timer Module. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup watchdog_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_watchdog.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/watchdog.h" - -//***************************************************************************** -// -//! Determines if the watchdog timer is enabled. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function checks to see if the watchdog timer is enabled. -//! -//! \return Returns \b true if the watchdog timer is enabled and \b false -//! if it is not. -// -//***************************************************************************** -bool -WatchdogRunning(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // See if the watchdog timer module is enabled, and return. - // - return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN); -} - -//***************************************************************************** -// -//! Enables the watchdog timer. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables the watchdog timer counter and interrupt. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable the watchdog timer module. - // - HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN; -} - -//***************************************************************************** -// -//! Enables the watchdog timer reset. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables the capability of the watchdog timer to issue a reset -//! to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogResetEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable the watchdog reset. - // - HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN; -} - -//***************************************************************************** -// -//! Disables the watchdog timer reset. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function disables the capability of the watchdog timer to issue a -//! reset to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogResetDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Disable the watchdog reset. - // - HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN); -} - -//***************************************************************************** -// -//! Enables the watchdog timer lock mechanism. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function locks out write access to the watchdog timer registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogLock(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - // - HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED; -} - -//***************************************************************************** -// -//! Disables the watchdog timer lock mechanism. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables write access to the watchdog timer registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogUnlock(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Unlock watchdog register writes. - // - HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK; -} - -//***************************************************************************** -// -//! Gets the state of the watchdog timer lock mechanism. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function returns the lock state of the watchdog timer registers. -//! -//! \return Returns \b true if the watchdog timer registers are locked, and -//! \b false if they are not locked. -// -//***************************************************************************** -bool -WatchdogLockState(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Get the lock state. - // - return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); -} - -//***************************************************************************** -// -//! Sets the watchdog timer reload value. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param ui32LoadVal is the load value for the watchdog timer. -//! -//! This function configures the value to load into the watchdog timer when the -//! count reaches zero for the first time; if the watchdog timer is running -//! when this function is called, then the value is immediately loaded into the -//! watchdog timer counter. If the \e ui32LoadVal parameter is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Set the load register. - // - HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal; -} - -//***************************************************************************** -// -//! Gets the watchdog timer reload value. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -WatchdogReloadGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Get the load register. - // - return(HWREG(ui32Base + WDT_O_LOAD)); -} - -//***************************************************************************** -// -//! Gets the current watchdog timer value. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -uint32_t -WatchdogValueGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Get the current watchdog timer register value. - // - return(HWREG(ui32Base + WDT_O_VALUE)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function also enables the global interrupt in the interrupt controller; the -//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! WatchdogIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note For parts with a watchdog timer module that has the ability to -//! generate an NMI instead of a standard interrupt, this function registers -//! the standard watchdog interrupt handler. To register the NMI watchdog -//! handler, use IntRegister() to register the handler for the -//! \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Register the interrupt handler. - // - IntRegister(INT_WATCHDOG_TM4C123, pfnHandler); - - // - // Enable the watchdog timer interrupt. - // - IntEnable(INT_WATCHDOG_TM4C123); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function clears the handler to be called when a watchdog timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note For parts with a watchdog timer module that has the ability to -//! generate an NMI instead of a standard interrupt, this function unregisters -//! the standard watchdog interrupt handler. To unregister the NMI watchdog -//! handler, use IntUnregister() to unregister the handler for the -//! \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Disable the interrupt. - // - IntDisable(INT_WATCHDOG_TM4C123); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_WATCHDOG_TM4C123); -} - -//***************************************************************************** -// -//! Enables the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function enables the watchdog timer interrupt. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable the watchdog interrupt. - // - HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN; -} - -//***************************************************************************** -// -//! Gets the current watchdog timer interrupt status. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the watchdog timer module. -//! Either the raw interrupt status or the status of interrupt that is allowed -//! to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, where a 1 indicates that the -//! watchdog interrupt is active, and a 0 indicates that it is not active. -// -//***************************************************************************** -uint32_t -WatchdogIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + WDT_O_MIS)); - } - else - { - return(HWREG(ui32Base + WDT_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the watchdog timer interrupt. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). This function has no effect if the watchdog -//! timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Clear the interrupt source. - // - HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS; -} - -//***************************************************************************** -// -//! Sets the type of interrupt generated by the watchdog. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! \param ui32Type is the type of interrupt to generate. -//! -//! This function sets the type of interrupt that is generated if the watchdog -//! timer expires. \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to -//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to -//! generate a non-maskable interrupt (NMI). -//! -//! When configured to generate an NMI, the watchdog interrupt must still be -//! enabled with WatchdogIntEnable(), and it must still be cleared inside the -//! NMI handler with WatchdogIntClear(). -//! -//! \note The ability to select an NMI interrupt varies with the Tiva part -//! in use. Please consult the datasheet for the part you are using to -//! determine whether this support is available. This function has no effect if -//! the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || - (ui32Type == WATCHDOG_INT_TYPE_NMI)); - - // - // Set the interrupt type. - // - HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) & - ~WDT_CTL_INTTYPE) | ui32Type; -} - -//***************************************************************************** -// -//! Enables stalling of the watchdog timer during debug events. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog instead expires -//! after the appropriate number of processor cycles have been executed while -//! debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Enable timer stalling. - // - HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL; -} - -//***************************************************************************** -// -//! Disables stalling of the watchdog timer during debug events. -//! -//! \param ui32Base is the base address of the watchdog timer module. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); - - // - // Disable timer stalling. - // - HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.h b/bsp/tm4c129x-dk/libraries/driverlib/watchdog.h deleted file mode 100644 index a14a4fb04c..0000000000 --- a/bsp/tm4c129x-dk/libraries/driverlib/watchdog.h +++ /dev/null @@ -1,95 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_WATCHDOG_H__ -#define __DRIVERLIB_WATCHDOG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The type of interrupt that can be generated by the watchdog. -// -//***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern bool WatchdogRunning(uint32_t ui32Base); -extern void WatchdogEnable(uint32_t ui32Base); -extern void WatchdogResetEnable(uint32_t ui32Base); -extern void WatchdogResetDisable(uint32_t ui32Base); -extern void WatchdogLock(uint32_t ui32Base); -extern void WatchdogUnlock(uint32_t ui32Base); -extern bool WatchdogLockState(uint32_t ui32Base); -extern void WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal); -extern uint32_t WatchdogReloadGet(uint32_t ui32Base); -extern uint32_t WatchdogValueGet(uint32_t ui32Base); -extern void WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void WatchdogIntUnregister(uint32_t ui32Base); -extern void WatchdogIntEnable(uint32_t ui32Base); -extern uint32_t WatchdogIntStatus(uint32_t ui32Base, bool bMasked); -extern void WatchdogIntClear(uint32_t ui32Base); -extern void WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type); -extern void WatchdogStallEnable(uint32_t ui32Base); -extern void WatchdogStallDisable(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_WATCHDOG_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/asmdefs.h b/bsp/tm4c129x-dk/libraries/inc/asmdefs.h deleted file mode 100644 index b0e4cc217c..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/asmdefs.h +++ /dev/null @@ -1,227 +0,0 @@ -//***************************************************************************** -// -// asmdefs.h - Macros to allow assembly code be portable among toolchains. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for code_red. -// -//***************************************************************************** -#ifdef codered - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // codered - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef ewarm - -// -// Section headers. -// -#define __LIBRARY__ module -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) -#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) - -// -// Assembler nmenonics. -// -#define __ALIGN__ alignrom 2 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ thumb -#define __WORD__ dcd -#define __INLINE_DATA__ data - -#endif // ewarm - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#if defined(gcc) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // gcc - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#ifdef rvmdk - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __LIBRARY__ ; -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 -#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 - -// -// Assembler nmenonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd -#define __INLINE_DATA__ - -#endif // rvmdk - -//***************************************************************************** -// -// The defines required for Sourcery G++. -// -//***************************************************************************** -#if defined(sourcerygxx) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // sourcerygxx - -#endif // __ASMDEF_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_adc.h b/bsp/tm4c129x-dk/libraries/inc/hw_adc.h deleted file mode 100644 index 41f8a33e4d..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_adc.h +++ /dev/null @@ -1,1306 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following are defines for the ADC register offsets. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer -#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status -#define ADC_O_IM 0x00000008 // ADC Interrupt Mask -#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear -#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status -#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select -#define ADC_O_USTAT 0x00000018 // ADC Underflow Status -#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select -#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority -#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control -#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence - // Initiate -#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control -#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt - // Status and Clear -#define ADC_O_CTL 0x00000038 // ADC Control -#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input - // Multiplexer Select 0 -#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0 -#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO - // 0 -#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0 - // Status -#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation -#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital - // Comparator Select -#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended - // Input Multiplexer Select 0 -#define ADC_O_SSTSH0 0x0000005C // ADC Sample Sequence 0 Sample and - // Hold Time -#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input - // Multiplexer Select 1 -#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 -#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO - // 1 -#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1 - // Status -#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation -#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital - // Comparator Select -#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended - // Input Multiplexer Select 1 -#define ADC_O_SSTSH1 0x0000007C // ADC Sample Sequence 1 Sample and - // Hold Time -#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input - // Multiplexer Select 2 -#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 -#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO - // 2 -#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2 - // Status -#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation -#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital - // Comparator Select -#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended - // Input Multiplexer Select 2 -#define ADC_O_SSTSH2 0x0000009C // ADC Sample Sequence 2 Sample and - // Hold Time -#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input - // Multiplexer Select 3 -#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 -#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO - // 3 -#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3 - // Status -#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation -#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital - // Comparator Select -#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended - // Input Multiplexer Select 3 -#define ADC_O_SSTSH3 0x000000BC // ADC Sample Sequence 3 Sample and - // Hold Time -#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset - // Initial Conditions -#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 -#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 -#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 -#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 -#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 -#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 -#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 -#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 -#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 -#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 -#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 -#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 -#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 -#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 -#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 -#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 -#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties -#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration -#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy -#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable -#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable -#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable -#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable -#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt - // Status -#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status -#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_IM register. -// -//***************************************************************************** -#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on - // SS3 -#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on - // SS2 -#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on - // SS1 -#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on - // SS0 -#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask -#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask -#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask -#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask -#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ISC register. -// -//***************************************************************************** -#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt - // Status on SS3 -#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt - // Status on SS2 -#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt - // Status on SS1 -#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt - // Status on SS0 -#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and - // Clear -#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 -#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 -#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 -#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 -#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 -#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 -#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 -#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 -#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_TSSEL register. -// -//***************************************************************************** -#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger - // Select -#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its - // trigger) in PWM module 1 -#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger - // Select -#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its - // trigger) in PWM module 1 -#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger - // Select -#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its - // trigger) in PWM module 1 -#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger - // Select -#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its - // trigger) in PWM module 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority -#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority -#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority -#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SPC register. -// -//***************************************************************************** -#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference -#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 -#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 -#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 -#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 -#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 -#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 -#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 -#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 -#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 -#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 -#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 -#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 -#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 -#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 -#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 -#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize -#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait -#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCISC register. -// -//***************************************************************************** -#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CTL register. -// -//***************************************************************************** -#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select -#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage - // references -#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- - // inputs are the voltage - // references - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX0 register. -// -//***************************************************************************** -#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL0 register. -// -//***************************************************************************** -#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input - // Select -#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input - // Select -#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input - // Select -#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input - // Select -#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. -// -//***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. -// -//***************************************************************************** -#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP0 register. -// -//***************************************************************************** -#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator - // Operation -#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator - // Operation -#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator - // Operation -#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator - // Operation -#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC0 register. -// -//***************************************************************************** -#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator - // Select -#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator - // Select -#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator - // Select -#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_S 24 -#define ADC_SSDC0_S5DCSEL_S 20 -#define ADC_SSDC0_S4DCSEL_S 16 -#define ADC_SSDC0_S3DCSEL_S 12 -#define ADC_SSDC0_S2DCSEL_S 8 -#define ADC_SSDC0_S1DCSEL_S 4 -#define ADC_SSDC0_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. -// -//***************************************************************************** -#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH0 register. -// -//***************************************************************************** -#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH7_S 28 -#define ADC_SSTSH0_TSH6_S 24 -#define ADC_SSTSH0_TSH5_S 20 -#define ADC_SSTSH0_TSH4_S 16 -#define ADC_SSTSH0_TSH3_S 12 -#define ADC_SSTSH0_TSH2_S 8 -#define ADC_SSTSH0_TSH1_S 4 -#define ADC_SSTSH0_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX1 register. -// -//***************************************************************************** -#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL1 register. -// -//***************************************************************************** -#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. -// -//***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. -// -//***************************************************************************** -#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP1 register. -// -//***************************************************************************** -#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC1 register. -// -//***************************************************************************** -#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_S 8 -#define ADC_SSDC1_S1DCSEL_S 4 -#define ADC_SSDC1_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. -// -//***************************************************************************** -#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH1 register. -// -//***************************************************************************** -#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH3_S 12 -#define ADC_SSTSH1_TSH2_S 8 -#define ADC_SSTSH1_TSH1_S 4 -#define ADC_SSTSH1_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX2 register. -// -//***************************************************************************** -#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL2 register. -// -//***************************************************************************** -#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. -// -//***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. -// -//***************************************************************************** -#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP2 register. -// -//***************************************************************************** -#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC2 register. -// -//***************************************************************************** -#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_S 8 -#define ADC_SSDC2_S1DCSEL_S 4 -#define ADC_SSDC2_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. -// -//***************************************************************************** -#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH2 register. -// -//***************************************************************************** -#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH3_S 12 -#define ADC_SSTSH2_TSH2_S 8 -#define ADC_SSTSH2_TSH1_S 4 -#define ADC_SSTSH2_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX3 register. -// -//***************************************************************************** -#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL3 register. -// -//***************************************************************************** -#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 // End of Sequence -#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. -// -//***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. -// -//***************************************************************************** -#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP3 register. -// -//***************************************************************************** -#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC3 register. -// -//***************************************************************************** -#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. -// -//***************************************************************************** -#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH3 register. -// -//***************************************************************************** -#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH3_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCRIC register. -// -//***************************************************************************** -#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 -#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 -#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 -#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 -#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 -#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 -#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 -#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 -#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 -#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 -#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 -#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 -#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 -#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 -#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 -#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL0 register. -// -//***************************************************************************** -#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL1 register. -// -//***************************************************************************** -#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL2 register. -// -//***************************************************************************** -#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL3 register. -// -//***************************************************************************** -#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL4 register. -// -//***************************************************************************** -#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL5 register. -// -//***************************************************************************** -#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL6 register. -// -//***************************************************************************** -#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL7 register. -// -//***************************************************************************** -#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP0 register. -// -//***************************************************************************** -#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP0_COMP1_S 16 -#define ADC_DCCMP0_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP1 register. -// -//***************************************************************************** -#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP1_COMP1_S 16 -#define ADC_DCCMP1_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP2 register. -// -//***************************************************************************** -#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP2_COMP1_S 16 -#define ADC_DCCMP2_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP3 register. -// -//***************************************************************************** -#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP3_COMP1_S 16 -#define ADC_DCCMP3_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP4 register. -// -//***************************************************************************** -#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP4_COMP1_S 16 -#define ADC_DCCMP4_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP5 register. -// -//***************************************************************************** -#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP5_COMP1_S 16 -#define ADC_DCCMP5_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP6 register. -// -//***************************************************************************** -#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP6_COMP1_S 16 -#define ADC_DCCMP6_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP7 register. -// -//***************************************************************************** -#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP7_COMP1_S 16 -#define ADC_DCCMP7_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PP register. -// -//***************************************************************************** -#define ADC_PP_APSHT 0x01000000 // Application-Programmable - // Sample-and-Hold Time -#define ADC_PP_TS 0x00800000 // Temperature Sensor -#define ADC_PP_RSL_M 0x007C0000 // Resolution -#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture -#define ADC_PP_TYPE_SAR 0x00000000 // SAR -#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count -#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count -#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate -#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH -#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate -#define ADC_PP_MSR_125K 0x00000001 // 125 ksps -#define ADC_PP_MSR_250K 0x00000003 // 250 ksps -#define ADC_PP_MSR_500K 0x00000005 // 500 ksps -#define ADC_PP_MSR_1M 0x00000007 // 1 Msps -#define ADC_PP_RSL_S 18 -#define ADC_PP_DC_S 10 -#define ADC_PP_CH_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PC register. -// -//***************************************************************************** -#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate -#define ADC_PC_SR_125K 0x00000001 // 125 ksps -#define ADC_PC_SR_250K 0x00000003 // 250 ksps -#define ADC_PC_SR_500K 0x00000005 // 500 ksps -#define ADC_PC_SR_1M 0x00000007 // 1 Msps -#define ADC_PC_MCR_M 0x0000000F // Conversion Rate -#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a - // conversion completes, the logic - // pauses for 112 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a - // conversion completes, the logic - // pauses for 48 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a - // conversion completes, the logic - // pauses for 16 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CC register. -// -//***************************************************************************** -#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor -#define ADC_CC_CS_M 0x0000000F // ADC Clock Source -#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV -#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC -#define ADC_CC_CS_MOSC 0x00000002 // MOSC -#define ADC_CC_CLKDIV_S 4 - -#endif // __HW_ADC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_aes.h b/bsp/tm4c129x-dk/libraries/inc/hw_aes.h deleted file mode 100644 index 79d56113d6..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_aes.h +++ /dev/null @@ -1,545 +0,0 @@ -//***************************************************************************** -// -// hw_aes.h - Macros used when accessing the AES hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_AES_H__ -#define __HW_AES_H__ - -//***************************************************************************** -// -// The following are defines for the AES register offsets. -// -//***************************************************************************** -#define AES_O_KEY2_6 0x00000000 // AES Key 2_6 -#define AES_O_KEY2_7 0x00000004 // AES Key 2_7 -#define AES_O_KEY2_4 0x00000008 // AES Key 2_4 -#define AES_O_KEY2_5 0x0000000C // AES Key 2_5 -#define AES_O_KEY2_2 0x00000010 // AES Key 2_2 -#define AES_O_KEY2_3 0x00000014 // AES Key 2_3 -#define AES_O_KEY2_0 0x00000018 // AES Key 2_0 -#define AES_O_KEY2_1 0x0000001C // AES Key 2_1 -#define AES_O_KEY1_6 0x00000020 // AES Key 1_6 -#define AES_O_KEY1_7 0x00000024 // AES Key 1_7 -#define AES_O_KEY1_4 0x00000028 // AES Key 1_4 -#define AES_O_KEY1_5 0x0000002C // AES Key 1_5 -#define AES_O_KEY1_2 0x00000030 // AES Key 1_2 -#define AES_O_KEY1_3 0x00000034 // AES Key 1_3 -#define AES_O_KEY1_0 0x00000038 // AES Key 1_0 -#define AES_O_KEY1_1 0x0000003C // AES Key 1_1 -#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input - // 0 -#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input - // 1 -#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input - // 2 -#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input - // 3 -#define AES_O_CTRL 0x00000050 // AES Control -#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0 -#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1 -#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length -#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext - // 0 -#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext - // 1 -#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext - // 2 -#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext - // 3 -#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0 -#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1 -#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2 -#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3 -#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier -#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration -#define AES_O_SYSSTATUS 0x00000088 // AES System Status -#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status -#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable -#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits -#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask -#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status -#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status -#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_6 register. -// -//***************************************************************************** -#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_6_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_7 register. -// -//***************************************************************************** -#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_7_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_4 register. -// -//***************************************************************************** -#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_4_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_5 register. -// -//***************************************************************************** -#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_5_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_2 register. -// -//***************************************************************************** -#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_2_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_3 register. -// -//***************************************************************************** -#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_3_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_0 register. -// -//***************************************************************************** -#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_0_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_1 register. -// -//***************************************************************************** -#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY2_1_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_6 register. -// -//***************************************************************************** -#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_6_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_7 register. -// -//***************************************************************************** -#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_7_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_4 register. -// -//***************************************************************************** -#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_4_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_5 register. -// -//***************************************************************************** -#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_5_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_2 register. -// -//***************************************************************************** -#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_2_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_3 register. -// -//***************************************************************************** -#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_3_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_0 register. -// -//***************************************************************************** -#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_0_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_1 register. -// -//***************************************************************************** -#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data -#define AES_KEY1_1_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_0 register. -// -//***************************************************************************** -#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_1 register. -// -//***************************************************************************** -#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_2 register. -// -//***************************************************************************** -#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_3 register. -// -//***************************************************************************** -#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input -#define AES_IV_IN_3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_CTRL register. -// -//***************************************************************************** -#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready -#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready -#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save -#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM) -#define AES_CTRL_CCM_L_M 0x00380000 // L Value -#define AES_CTRL_CCM_L_2 0x00080000 // width = 2 -#define AES_CTRL_CCM_L_4 0x00180000 // width = 4 -#define AES_CTRL_CCM_L_8 0x00380000 // width = 8 -#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable -#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable -#define AES_CTRL_GCM_NOP 0x00000000 // No operation -#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and - // Y0-encrypted forced to zero -#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and - // Y0-encrypted calculated - // internally -#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and - // Y0-encrypted calculated - // internally) -#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable -#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable -#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable -#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled -#define AES_CTRL_XTS_NOP 0x00000000 // No operation -#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak - // value and j loaded (value is - // loaded via IV, j is loaded via - // the AAD length register) -#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is - // loaded via IV, j is loaded via - // the AAD length register) -#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is - // loaded via IV) -#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback - // mode (CFB128) Enable -#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM) - // Enable -#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width -#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits -#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits -#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits -#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits -#define AES_CTRL_CTR 0x00000040 // Counter Mode -#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode -#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size -#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits -#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits -#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits -#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection -#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status -#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status -#define AES_CTRL_CCM_M_S 22 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_C_LENGTH_0 -// register. -// -//***************************************************************************** -#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length -#define AES_C_LENGTH_0_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_C_LENGTH_1 -// register. -// -//***************************************************************************** -#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length -#define AES_C_LENGTH_1_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_AUTH_LENGTH -// register. -// -//***************************************************************************** -#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length -#define AES_AUTH_LENGTH_AUTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_0 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_1 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_2 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_3 -// register. -// -//***************************************************************************** -#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW - // Plaintext/Ciphertext -#define AES_DATA_IN_3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_0 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_0_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_1 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_1_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_2 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_2_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_3 -// register. -// -//***************************************************************************** -#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result -#define AES_TAG_OUT_3_HASH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_REVISION register. -// -//***************************************************************************** -#define AES_REVISION_M 0xFFFFFFFF // Revision number -#define AES_REVISION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSCONFIG -// register. -// -//***************************************************************************** -#define AES_SYSCONFIG_K3 0x00001000 // K3 Select -#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding -#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \ - 0x00000200 // Map Context Out on Data Out - // Enable -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ - 0x00000100 // DMA Request Context Out Enable -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // DMA Request Context In Enable -#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // DMA Request Data Out Enable -#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // DMA Request Data In Enable -#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSSTATUS -// register. -// -//***************************************************************************** -#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQSTATUS -// register. -// -//***************************************************************************** -#define AES_IRQSTATUS_CONTEXT_OUT \ - 0x00000008 // Context Output Interrupt Status -#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status -#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status -#define AES_IRQSTATUS_CONTEXT_IN \ - 0x00000001 // Context In Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQENABLE -// register. -// -//***************************************************************************** -#define AES_IRQENABLE_CONTEXT_OUT \ - 0x00000008 // Context Out Interrupt Enable -#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable -#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable -#define AES_IRQENABLE_CONTEXT_IN \ - 0x00000001 // Context In Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DIRTYBITS -// register. -// -//***************************************************************************** -#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit -#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMAIM register. -// -//***************************************************************************** -#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask -#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask -#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt - // Mask -#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMARIS register. -// -//***************************************************************************** -#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt - // Status -#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt - // Status -#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw - // Interrupt Status -#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMAMIS register. -// -//***************************************************************************** -#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked - // Interrupt Status -#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked - // Interrupt Status -#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked - // Interrupt Status -#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DMAIC register. -// -//***************************************************************************** -#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt - // Clear -#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear -#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked - // Interrupt Status -#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -#endif // __HW_AES_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_can.h b/bsp/tm4c129x-dk/libraries/inc/hw_can.h deleted file mode 100644 index 398a83d6cb..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_can.h +++ /dev/null @@ -1,462 +0,0 @@ -//***************************************************************************** -// -// hw_can.h - Defines and macros used when accessing the CAN controllers. -// -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_CAN_H__ -#define __HW_CAN_H__ - -//***************************************************************************** -// -// The following are defines for the CAN register offsets. -// -//***************************************************************************** -#define CAN_O_CTL 0x00000000 // CAN Control -#define CAN_O_STS 0x00000004 // CAN Status -#define CAN_O_ERR 0x00000008 // CAN Error Counter -#define CAN_O_BIT 0x0000000C // CAN Bit Timing -#define CAN_O_INT 0x00000010 // CAN Interrupt -#define CAN_O_TST 0x00000014 // CAN Test -#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler - // Extension -#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request -#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask -#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 -#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 -#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 -#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 -#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control -#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 -#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 -#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 -#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 -#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request -#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask -#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 -#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 -#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 -#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 -#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control -#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 -#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 -#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 -#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 -#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 -#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 -#define CAN_O_NWDA1 0x00000120 // CAN New Data 1 -#define CAN_O_NWDA2 0x00000124 // CAN New Data 2 -#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending -#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending -#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid -#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus-Off Status -#define CAN_STS_EWARN 0x00000040 // Warning Status -#define CAN_STS_EPASS 0x00000020 // Error Passive -#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully -#define CAN_STS_TXOK 0x00000008 // Transmitted a Message - // Successfully -#define CAN_STS_LEC_M 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No Error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error -#define CAN_STS_LEC_FORM 0x00000002 // Format Error -#define CAN_STS_LEC_ACK 0x00000003 // ACK Error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error -#define CAN_STS_LEC_CRC 0x00000006 // CRC Error -#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Received Error Passive -#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter -#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter -#define CAN_ERR_REC_S 8 -#define CAN_ERR_TEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point -#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point -#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width -#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler -#define CAN_BIT_TSEG2_S 12 -#define CAN_BIT_TSEG1_S 8 -#define CAN_BIT_SJW_S 6 -#define CAN_BIT_BRP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // Receive Observation -#define CAN_TST_TX_M 0x00000060 // Transmit Control -#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point -#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low -#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High -#define CAN_TST_LBACK 0x00000010 // Loopback Mode -#define CAN_TST_SILENT 0x00000008 // Silent Mode -#define CAN_TST_BASIC 0x00000004 // Basic Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension -#define CAN_BRPE_BRPE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CRQ register. -// -//***************************************************************************** -#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF1CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CMSK register. -// -//***************************************************************************** -#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. -// -//***************************************************************************** -#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF1MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. -// -//***************************************************************************** -#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF1MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. -// -//***************************************************************************** -#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF1ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. -// -//***************************************************************************** -#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF1ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MCTL register. -// -//***************************************************************************** -#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF1MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA1 register. -// -//***************************************************************************** -#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA2 register. -// -//***************************************************************************** -#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB1 register. -// -//***************************************************************************** -#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB2 register. -// -//***************************************************************************** -#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CRQ register. -// -//***************************************************************************** -#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF2CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CMSK register. -// -//***************************************************************************** -#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. -// -//***************************************************************************** -#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF2MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. -// -//***************************************************************************** -#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF2MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. -// -//***************************************************************************** -#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF2ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. -// -//***************************************************************************** -#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF2ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MCTL register. -// -//***************************************************************************** -#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF2MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA1 register. -// -//***************************************************************************** -#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA2 register. -// -//***************************************************************************** -#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB1 register. -// -//***************************************************************************** -#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB2 register. -// -//***************************************************************************** -#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ1_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ2_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA1_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA2_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1INT register. -// -//***************************************************************************** -#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG1INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2INT register. -// -//***************************************************************************** -#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG2INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1VAL register. -// -//***************************************************************************** -#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG1VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2VAL register. -// -//***************************************************************************** -#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG2VAL_MSGVAL_S 0 - -#endif // __HW_CAN_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_ccm.h b/bsp/tm4c129x-dk/libraries/inc/hw_ccm.h deleted file mode 100644 index 9664ceea75..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_ccm.h +++ /dev/null @@ -1,115 +0,0 @@ -//***************************************************************************** -// -// hw_ccm.h - Macros used when accessing the CCM hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_CCM_H__ -#define __HW_CCM_H__ - -//***************************************************************************** -// -// The following are defines for the EC register offsets. -// -//***************************************************************************** -#define CCM_O_CRCCTRL 0x00000400 // CRC Control -#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context -#define CCM_O_CRCDIN 0x00000414 // CRC Data Input -#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCCTRL register. -// -//***************************************************************************** -#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization -#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context - // as the starting value -#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s' -#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s' -#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size -#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable -#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable -#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable -#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control -#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3, - // B2, B1, B0) -#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words - // but half-words are not swapped - // (B2, B3, B0, B1) -#define CCM_CRCCTRL_ENDIAN_SHWNB \ - 0x00000020 // Half-words are swapped but bytes - // are not swapped in half-word. - // (B1, B0, B3, B2) -#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words - // and half-words are swapped. (B0, - // B1, B2, B3) -#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type -#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005 -#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CCM_CRCCTRL_TYPE_P4C11DB7 \ - 0x00000002 // Polynomial 0x4C11DB7 -#define CCM_CRCCTRL_TYPE_P1EDC6F41 \ - 0x00000003 // Polynomial 0x1EDC6F41 -#define CCM_CRCCTRL_TYPE_TCPCHKSUM \ - 0x00000008 // TCP checksum - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCSEED register. -// -//***************************************************************************** -#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value -#define CCM_CRCSEED_SEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCDIN register. -// -//***************************************************************************** -#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input -#define CCM_CRCDIN_DATAIN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCRSLTPP -// register. -// -//***************************************************************************** -#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result -#define CCM_CRCRSLTPP_RSLTPP_S 0 - -#endif // __HW_CCM_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_comp.h b/bsp/tm4c129x-dk/libraries/inc/hw_comp.h deleted file mode 100644 index 24616aa954..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_comp.h +++ /dev/null @@ -1,211 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following are defines for the Comparator register offsets. -// -//***************************************************************************** -#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked - // Interrupt Status -#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt - // Status -#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt - // Enable -#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference - // Voltage Control -#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0 -#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0 -#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1 -#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1 -#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2 -#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2 -#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral - // Properties - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACMIS register. -// -//***************************************************************************** -#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt - // Status -#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt - // Status -#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACRIS register. -// -//***************************************************************************** -#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status -#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status -#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACINTEN register. -// -//***************************************************************************** -#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable -#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable -#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACREFCTL -// register. -// -//***************************************************************************** -#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable -#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range -#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref -#define COMP_ACREFCTL_VREF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. -// -//***************************************************************************** -#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL0 register. -// -//***************************************************************************** -#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. -// -//***************************************************************************** -#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL1 register. -// -//***************************************************************************** -#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. -// -//***************************************************************************** -#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL2 register. -// -//***************************************************************************** -#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_PP register. -// -//***************************************************************************** -#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present -#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present -#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present -#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present -#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present -#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present - -#endif // __HW_COMP_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_des.h b/bsp/tm4c129x-dk/libraries/inc/hw_des.h deleted file mode 100644 index 775c3a745c..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_des.h +++ /dev/null @@ -1,310 +0,0 @@ -//***************************************************************************** -// -// hw_des.h - Macros used when accessing the DES hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_DES_H__ -#define __HW_DES_H__ - -//***************************************************************************** -// -// The following are defines for the DES register offsets. -// -//***************************************************************************** -#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key -#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key -#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key -#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key -#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key -#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key -#define DES_O_IV_L 0x00000018 // DES Initialization Vector -#define DES_O_IV_H 0x0000001C // DES Initialization Vector -#define DES_O_CTRL 0x00000020 // DES Control -#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length -#define DES_O_DATA_L 0x00000028 // DES LSW Data RW -#define DES_O_DATA_H 0x0000002C // DES MSW Data RW -#define DES_O_REVISION 0x00000030 // DES Revision Number -#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration -#define DES_O_SYSSTATUS 0x00000038 // DES System Status -#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status -#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable -#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits -#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask -#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status -#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status -#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_L register. -// -//***************************************************************************** -#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY3_L_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_H register. -// -//***************************************************************************** -#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY3_H_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_L register. -// -//***************************************************************************** -#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY2_L_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_H register. -// -//***************************************************************************** -#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY2_H_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_L register. -// -//***************************************************************************** -#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY1_L_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_H register. -// -//***************************************************************************** -#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data -#define DES_KEY1_H_KEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_L register. -// -//***************************************************************************** -#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC, - // CFB modes (LSW) -#define DES_IV_L_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_H register. -// -//***************************************************************************** -#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC, - // CFB modes (MSW) -#define DES_IV_H_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_CTRL register. -// -//***************************************************************************** -#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit - // indicates that the context data - // registers can be overwritten and - // the host is permitted to write - // the next context -#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0: - // ECB mode0x1: CBC mode0x2: CFB - // mode0x3: reserved -#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES - // encryption/decryption -#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption - // 0x0: decryption is selected0x1: - // Encryption is selected -#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt - // data -#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted - // ready -#define DES_CTRL_MODE_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_LENGTH register. -// -//***************************************************************************** -#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in - // bytes for all modes -#define DES_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_L register. -// -//***************************************************************************** -#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption, - // LSW -#define DES_DATA_L_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_H register. -// -//***************************************************************************** -#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption, - // MSW -#define DES_DATA_H_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_REVISION register. -// -//***************************************************************************** -#define DES_REVISION_M 0xFFFFFFFF // Revision number -#define DES_REVISION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSCONFIG -// register. -// -//***************************************************************************** -#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // DMA Request Context In Enable -#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // DMA Request Data Out Enable -#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // DMA Request Data In Enable -#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode -#define DES_SYSCONFIG_SIDLE_FORCE \ - 0x00000000 // Force-idle mode -#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSSTATUS -// register. -// -//***************************************************************************** -#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQSTATUS -// register. -// -//***************************************************************************** -#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output -#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output -#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQENABLE -// register. -// -//***************************************************************************** -#define DES_IRQENABLE_M_DATA_OUT \ - 0x00000004 // If this bit is set to 1 the data - // output interrupt is enabled -#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data - // input interrupt is enabled -#define DES_IRQENABLE_M_CONTEX_IN \ - 0x00000001 // If this bit is set to 1 the - // context interrupt is enabled - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DIRTYBITS -// register. -// -//***************************************************************************** -#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the - // module if any of the DES_* - // registers is written -#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the - // module if any of the DES_* - // registers is read - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMAIM register. -// -//***************************************************************************** -#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask -#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask -#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMARIS register. -// -//***************************************************************************** -#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt - // Status -#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt - // Status -#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMAMIS register. -// -//***************************************************************************** -#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked - // Interrupt Status -#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked - // Interrupt Status -#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DMAIC register. -// -//***************************************************************************** -#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt - // Clear -#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear -#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -#endif // __HW_DES_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_eeprom.h b/bsp/tm4c129x-dk/libraries/inc/hw_eeprom.h deleted file mode 100644 index 2118c958e6..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_eeprom.h +++ /dev/null @@ -1,251 +0,0 @@ -//***************************************************************************** -// -// hw_eeprom.h - Macros used when accessing the EEPROM controller. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_EEPROM_H__ -#define __HW_EEPROM_H__ - -//***************************************************************************** -// -// The following are defines for the EEPROM register offsets. -// -//***************************************************************************** -#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information -#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block -#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset -#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write -#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment -#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status -#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and - // Status -#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock -#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection -#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password -#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password -#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password -#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt -#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0 -#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide -#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1 -#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2 -#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase -#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESIZE register. -// -//***************************************************************************** -#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words -#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks -#define EEPROM_EESIZE_WORDCNT_S 0 -#define EEPROM_EESIZE_BLKCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEBLOCK register. -// -//***************************************************************************** -#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block -#define EEPROM_EEBLOCK_BLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEOFFSET -// register. -// -//***************************************************************************** -#define EEPROM_EEOFFSET_OFFSET_M \ - 0x0000000F // Current Address Offset -#define EEPROM_EEOFFSET_OFFSET_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWR register. -// -//***************************************************************************** -#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data -#define EEPROM_EERDWR_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWRINC -// register. -// -//***************************************************************************** -#define EEPROM_EERDWRINC_VALUE_M \ - 0xFFFFFFFF // EEPROM Read or Write Data with - // Increment -#define EEPROM_EERDWRINC_VALUE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDONE register. -// -//***************************************************************************** -#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working -#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase -#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy -#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission -#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESUPP register. -// -//***************************************************************************** -#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried -#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEUNLOCK -// register. -// -//***************************************************************************** -#define EEPROM_EEUNLOCK_UNLOCK_M \ - 0xFFFFFFFF // EEPROM Unlock - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPROT register. -// -//***************************************************************************** -#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control -#define EEPROM_EEPROT_PROT_RWNPW \ - 0x00000000 // This setting is the default. If - // there is no password, the block - // is not protected and is readable - // and writable -#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the - // block is readable or writable - // only when unlocked -#define EEPROM_EEPROT_PROT_RONPW \ - 0x00000002 // If there is no password, the - // block is readable, not writable -#define EEPROM_EEPROT_ACC 0x00000008 // Access Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS0 register. -// -//***************************************************************************** -#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS0_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS1 register. -// -//***************************************************************************** -#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS1_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS2 register. -// -//***************************************************************************** -#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS2_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEINT register. -// -//***************************************************************************** -#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE0 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE register. -// -//***************************************************************************** -#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE1 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE2 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDBGME register. -// -//***************************************************************************** -#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase -#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key -#define EEPROM_EEDBGME_KEY_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_PP register. -// -//***************************************************************************** -#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size -#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM -#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM -#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM -#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM -#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM -#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM -#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM -#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM -#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM -#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM -#define EEPROM_PP_SIZE_S 0 - -#endif // __HW_EEPROM_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_emac.h b/bsp/tm4c129x-dk/libraries/inc/hw_emac.h deleted file mode 100644 index a836da9d21..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_emac.h +++ /dev/null @@ -1,1874 +0,0 @@ -//***************************************************************************** -// -// hw_emac.h - Macros used when accessing the EMAC hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_EMAC_H__ -#define __HW_EMAC_H__ - -//***************************************************************************** -// -// The following are defines for the EMAC register offsets. -// -//***************************************************************************** -#define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration -#define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter -#define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High -#define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low -#define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address -#define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register -#define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control -#define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag -#define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status -#define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up - // Frame Filter -#define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and - // Status Register -#define EMAC_O_LPICTLSTAT 0x00000030 // Ethernet MAC Low Power Idle - // Control and Status Register -#define EMAC_O_LPITIMERCTL 0x00000034 // Ethernet MAC Low Power Idle - // Timer Control Register -#define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt - // Status -#define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask -#define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High -#define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low - // Register -#define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High -#define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low -#define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High -#define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low -#define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High -#define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low -#define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout -#define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control -#define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw - // Interrupt Status -#define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw - // Interrupt Status -#define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive - // Interrupt Mask -#define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit - // Interrupt Mask -#define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame - // Count for Good and Bad Frames -#define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame - // Count for Frames Transmitted - // after Single Collision -#define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame - // Count for Frames Transmitted - // after Multiple Collisions -#define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet - // Count Good -#define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count - // for Good and Bad Frames -#define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count - // for CRC Error Frames -#define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count - // for Alignment Error Frames -#define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count - // for Good Unicast Frames -#define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion - // or Replacement -#define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table -#define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control -#define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second - // Increment -#define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time - - // Seconds -#define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time - - // Nanoseconds -#define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time - - // Seconds Update -#define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time - - // Nanoseconds Update -#define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend -#define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds -#define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time - // Nanoseconds -#define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher - // Word Seconds -#define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status -#define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control -#define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval -#define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width -#define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode -#define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll - // Demand -#define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand -#define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor - // List Address -#define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor - // List Address -#define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt - // Status -#define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode -#define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask - // Register -#define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and - // Buffer Overflow Counter -#define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt - // Watchdog Timer -#define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host - // Transmit Descriptor -#define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host - // Receive Descriptor -#define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host - // Transmit Buffer Address -#define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host - // Receive Buffer Address -#define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property - // Register -#define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral - // Configuration Register -#define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration - // Register -#define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt - // Status -#define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask -#define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_CFG register. -// -//***************************************************************************** -#define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802 -#define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames -#define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable -#define EMAC_CFG_JD 0x00400000 // Jabber Disable -#define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable -#define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG) -#define EMAC_CFG_IFG_96 0x00000000 // 96 bit times -#define EMAC_CFG_IFG_88 0x00020000 // 88 bit times -#define EMAC_CFG_IFG_80 0x00040000 // 80 bit times -#define EMAC_CFG_IFG_72 0x00060000 // 72 bit times -#define EMAC_CFG_IFG_64 0x00080000 // 64 bit times -#define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times -#define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times -#define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times -#define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During - // Transmission -#define EMAC_CFG_PS 0x00008000 // Port Select -#define EMAC_CFG_FES 0x00004000 // Speed -#define EMAC_CFG_DRO 0x00002000 // Disable Receive Own -#define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode -#define EMAC_CFG_DUPM 0x00000800 // Duplex Mode -#define EMAC_CFG_IPC 0x00000400 // Checksum Offload -#define EMAC_CFG_DR 0x00000200 // Disable Retry -#define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping -#define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit -#define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10) -#define EMAC_CFG_BL_256 0x00000020 // k = min (n,8) -#define EMAC_CFG_BL_8 0x00000040 // k = min (n,4) -#define EMAC_CFG_BL_2 0x00000060 // k = min (n,1) -#define EMAC_CFG_DC 0x00000010 // Deferral Check -#define EMAC_CFG_TE 0x00000008 // Transmitter Enable -#define EMAC_CFG_RE 0x00000004 // Receiver Enable -#define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit - // Frames -#define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble -#define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble -#define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR -// register. -// -//***************************************************************************** -#define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All -#define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable -#define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter -#define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable -#define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse - // Filtering -#define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames -#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control - // frames from reaching application -#define EMAC_FRAMEFLTR_PCF_PAUSE \ - 0x00000040 // MAC forwards all control frames - // except PAUSE control frames to - // application even if they fail - // the address filter -#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames - // to application even if they fail - // the address Filter -#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that - // pass the address Filter -#define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames -#define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast -#define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse - // Filtering -#define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast -#define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast -#define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HASHTBLH -// register. -// -//***************************************************************************** -#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High -#define EMAC_HASHTBLH_HTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HASHTBLL -// register. -// -//***************************************************************************** -#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low -#define EMAC_HASHTBLL_HTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MIIADDR register. -// -//***************************************************************************** -#define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address -#define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register -#define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency - // Selection -#define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System - // Clock is 60 to 100 MHz providing - // a MDIO clock of SYSCLK/42 -#define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System - // Clock is 100 to 150 MHz - // providing a MDIO clock of - // SYSCLK/62 -#define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System - // Clock is 20-35 MHz providing a - // MDIO clock of System Clock/16 -#define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System - // Clock is 35 to 60 MHz providing - // a MDIO clock of System Clock/26 -#define EMAC_MIIADDR_MIIW 0x00000002 // MII Write -#define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy -#define EMAC_MIIADDR_PLA_S 11 -#define EMAC_MIIADDR_MII_S 6 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MIIDATA register. -// -//***************************************************************************** -#define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data -#define EMAC_MIIDATA_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_FLOWCTL register. -// -//***************************************************************************** -#define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time -#define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause -#define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect -#define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable -#define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable -#define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or - // Back-pressure Activate -#define EMAC_FLOWCTL_PT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_VLANTG register. -// -//***************************************************************************** -#define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable -#define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN -#define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable -#define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag - // Comparison -#define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive - // Frames -#define EMAC_VLANTG_VL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_STATUS register. -// -//***************************************************************************** -#define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full - // Status -#define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not - // Empty Status -#define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write - // Controller Active Status -#define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read - // Controller Status -#define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state -#define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to - // MAC transmitter) -#define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC - // transmitter -#define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status - // or flushing the TX FIFO -#define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE -#define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller - // Status -#define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state -#define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous - // frame or IFG or backoff period - // to be over -#define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a - // PAUSE control frame (in the - // full-duplex mode) -#define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for - // transmission -#define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine - // Status -#define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO - // Fill-level Status -#define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty -#define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the - // flow-control deactivate - // threshold -#define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the - // flow-control activate threshold -#define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full -#define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller - // State -#define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state -#define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data -#define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or - // timestamp) -#define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and - // status -#define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write - // Controller Active Status -#define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller - // FIFO Status -#define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine - // Status -#define EMAC_STATUS_RFCFC_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RWUFF register. -// -//***************************************************************************** -#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter -#define EMAC_RWUFF_WAKEUPFIL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT -// register. -// -//***************************************************************************** -#define EMAC_PMTCTLSTAT_WUPFRRST \ - 0x80000000 // Wake-Up Frame Filter Register - // Pointer Reset -#define EMAC_PMTCTLSTAT_RWKPTR_M \ - 0x07000000 // Remote Wake-Up FIFO Pointer -#define EMAC_PMTCTLSTAT_GLBLUCAST \ - 0x00000200 // Global Unicast -#define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received -#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received -#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable -#define EMAC_PMTCTLSTAT_MGKPKTEN \ - 0x00000002 // Magic Packet Enable -#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down -#define EMAC_PMTCTLSTAT_RWKPTR_S \ - 24 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_LPICTLSTAT -// register. -// -//***************************************************************************** -#define EMAC_LPICTLSTAT_LPITXA 0x00080000 // LPI TX Automate -#define EMAC_LPICTLSTAT_PLSEN 0x00040000 // PHY Link Status Enable -#define EMAC_LPICTLSTAT_PLS 0x00020000 // PHY Link Status -#define EMAC_LPICTLSTAT_LPIEN 0x00010000 // LPI Enable -#define EMAC_LPICTLSTAT_RLPIST 0x00000200 // Receive LPI State -#define EMAC_LPICTLSTAT_TLPIST 0x00000100 // Transmit LPI State -#define EMAC_LPICTLSTAT_RLPIEX 0x00000008 // Receive LPI Exit -#define EMAC_LPICTLSTAT_RLPIEN 0x00000004 // Receive LPI Entry -#define EMAC_LPICTLSTAT_TLPIEX 0x00000002 // Transmit LPI Exit -#define EMAC_LPICTLSTAT_TLPIEN 0x00000001 // Transmit LPI Entry - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_LPITIMERCTL -// register. -// -//***************************************************************************** -#define EMAC_LPITIMERCTL_LST_M 0x03FF0000 // Low Power Idle LS Timer -#define EMAC_LPITIMERCTL_LST_S 16 -#define EMAC_LPITIMERCTL_TWT_M 0x0000FFFF // Low Power Idle TW Timer -#define EMAC_LPITIMERCTL_TWT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RIS register. -// -//***************************************************************************** -#define EMAC_RIS_LPI 0x00000400 // LPI Interrupt Status -#define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status -#define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status -#define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status -#define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status -#define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_IM register. -// -//***************************************************************************** -#define EMAC_IM_LPI 0x00000400 // LPI Interrupt Mask -#define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask -#define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR0H register. -// -//***************************************************************************** -#define EMAC_ADDR0H_AE 0x80000000 // Address Enable -#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32] -#define EMAC_ADDR0H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR0L register. -// -//***************************************************************************** -#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0] -#define EMAC_ADDR0L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR1H register. -// -//***************************************************************************** -#define EMAC_ADDR1H_AE 0x80000000 // Address Enable -#define EMAC_ADDR1H_SA 0x40000000 // Source Address -#define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control -#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32] -#define EMAC_ADDR1H_MBC_S 24 -#define EMAC_ADDR1H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR1L register. -// -//***************************************************************************** -#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0] -#define EMAC_ADDR1L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR2H register. -// -//***************************************************************************** -#define EMAC_ADDR2H_AE 0x80000000 // Address Enable -#define EMAC_ADDR2H_SA 0x40000000 // Source Address -#define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control -#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32] -#define EMAC_ADDR2H_MBC_S 24 -#define EMAC_ADDR2H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR2L register. -// -//***************************************************************************** -#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0] -#define EMAC_ADDR2L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR3H register. -// -//***************************************************************************** -#define EMAC_ADDR3H_AE 0x80000000 // Address Enable -#define EMAC_ADDR3H_SA 0x40000000 // Source Address -#define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control -#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32] -#define EMAC_ADDR3H_MBC_S 24 -#define EMAC_ADDR3H_ADDRHI_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_ADDR3L register. -// -//***************************************************************************** -#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0] -#define EMAC_ADDR3L_ADDRLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_WDOGTO register. -// -//***************************************************************************** -#define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable -#define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout -#define EMAC_WDOGTO_WTO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCCTRL register. -// -//***************************************************************************** -#define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped - // Broadcast Frames -#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value -#define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset -#define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze -#define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read -#define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover -#define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCRXRIS -// register. -// -//***************************************************************************** -#define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame - // Counter Interrupt Status -#define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error - // Frame Counter Interrupt Status -#define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame - // Counter Interrupt Status -#define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame - // Counter Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCTXRIS -// register. -// -//***************************************************************************** -#define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status -#define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision - // Good Frame Counter Interrupt - // Status -#define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision - // Good Frame Counter Interrupt - // Status -#define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame - // Counter Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCRXIM register. -// -//***************************************************************************** -#define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame - // Counter Interrupt Mask -#define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error - // Frame Counter Interrupt Mask -#define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame - // Counter Interrupt Mask -#define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame - // Counter Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MMCTXIM register. -// -//***************************************************************************** -#define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter - // Interrupt Mask -#define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision - // Good Frame Counter Interrupt - // Mask -#define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision - // Good Frame Counter Interrupt - // Mask -#define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame - // Counter Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXCNTGB register. -// -//***************************************************************************** -#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number - // of good and bad frames - // transmitted, exclusive of - // retried frames -#define EMAC_TXCNTGB_TXFRMGB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL -// register. -// -//***************************************************************************** -#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \ - 0xFFFFFFFF // This field indicates the number - // of successfully transmitted - // frames after a single collision - // in the half-duplex mode -#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL -// register. -// -//***************************************************************************** -#define EMAC_TXCNTMCOL_TXMULTCOLG_M \ - 0xFFFFFFFF // This field indicates the number - // of successfully transmitted - // frames after multiple collisions - // in the half-duplex mode -#define EMAC_TXCNTMCOL_TXMULTCOLG_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG -// register. -// -//***************************************************************************** -#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number - // of bytes transmitted, exclusive - // of preamble, in good frames -#define EMAC_TXOCTCNTG_TXOCTG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTGB register. -// -//***************************************************************************** -#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number - // of received good and bad frames -#define EMAC_RXCNTGB_RXFRMGB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR -// register. -// -//***************************************************************************** -#define EMAC_RXCNTCRCERR_RXCRCERR_M \ - 0xFFFFFFFF // This field indicates the number - // of frames received with CRC - // error -#define EMAC_RXCNTCRCERR_RXCRCERR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR -// register. -// -//***************************************************************************** -#define EMAC_RXCNTALGNERR_RXALGNERR_M \ - 0xFFFFFFFF // This field indicates the number - // of frames received with - // alignment (dribble) error -#define EMAC_RXCNTALGNERR_RXALGNERR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI -// register. -// -//***************************************************************************** -#define EMAC_RXCNTGUNI_RXUCASTG_M \ - 0xFFFFFFFF // This field indicates the number - // of received good unicast frames -#define EMAC_RXCNTGUNI_RXUCASTG_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_VLNINCREP -// register. -// -//***************************************************************************** -#define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN -#define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control -#define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit - // Frames -#define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion, - // or replacement -#define EMAC_VLNINCREP_VLC_TAGDEL \ - 0x00010000 // VLAN tag deletion -#define EMAC_VLNINCREP_VLC_TAGINS \ - 0x00020000 // VLAN tag insertion -#define EMAC_VLNINCREP_VLC_TAGREP \ - 0x00030000 // VLAN tag replacement -#define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames -#define EMAC_VLNINCREP_VLT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_VLANHASH -// register. -// -//***************************************************************************** -#define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table -#define EMAC_VLANHASH_VLHT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL -// register. -// -//***************************************************************************** -#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame - // Filtering -#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking - // Snapshots -#define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages - // Relevant to Master -#define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for - // Event Messages -#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames - // Sent over IPv4-UDP -#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames - // Sent Over IPv6-UDP -#define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over - // Ethernet Frames -#define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For - // Version 2 Format -#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary - // Rollover Control -#define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames -#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update -#define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger - // Enable -#define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update -#define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize -#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update -#define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable -#define EMAC_TIMSTCTRL_SELPTP_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_SUBSECINC -// register. -// -//***************************************************************************** -#define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value -#define EMAC_SUBSECINC_SSINC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSEC register. -// -//***************************************************************************** -#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second -#define EMAC_TIMSEC_TSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMNANO register. -// -//***************************************************************************** -#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds -#define EMAC_TIMNANO_TSSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSECU register. -// -//***************************************************************************** -#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second -#define EMAC_TIMSECU_TSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMNANOU -// register. -// -//***************************************************************************** -#define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time -#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second -#define EMAC_TIMNANOU_TSSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMADD register. -// -//***************************************************************************** -#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register -#define EMAC_TIMADD_TSAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TARGSEC register. -// -//***************************************************************************** -#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register -#define EMAC_TARGSEC_TSTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TARGNANO -// register. -// -//***************************************************************************** -#define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy -#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register -#define EMAC_TARGNANO_TTSLO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HWORDSEC -// register. -// -//***************************************************************************** -#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word - // Register -#define EMAC_HWORDSEC_TSHWR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TIMSTAT register. -// -//***************************************************************************** -#define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached -#define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PPSCTRL register. -// -//***************************************************************************** -#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for - // PPS0 Output -#define EMAC_PPSCTRL_TRGMODS0_INTONLY \ - 0x00000000 // Indicates that the Target Time - // registers are programmed only - // for generating the interrupt - // event -#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \ - 0x00000040 // Indicates that the Target Time - // registers are programmed for - // generating the interrupt event - // and starting or stopping the - // generation of the EN0PPS output - // signal -#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \ - 0x00000060 // Indicates that the Target Time - // registers are programmed only - // for starting or stopping the - // generation of the EN0PPS output - // signal. No interrupt is asserted -#define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable -#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control - // (PPSCTRL) or Command Control - // (PPSCMD) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PPS0INTVL -// register. -// -//***************************************************************************** -#define EMAC_PPS0INTVL_PPS0INT_M \ - 0xFFFFFFFF // PPS0 Output Signal Interval -#define EMAC_PPS0INTVL_PPS0INT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH -// register. -// -//***************************************************************************** -#define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width -#define EMAC_PPS0WIDTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMABUSMOD -// register. -// -//***************************************************************************** -#define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst -#define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority -#define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst -#define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats -#define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length - // (PBL) Mode -#define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst - // Length (PBL) -#define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length - // (PBL) -#define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst -#define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio -#define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length -#define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size -#define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length -#define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme -#define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset -#define EMAC_DMABUSMOD_RPBL_S 17 -#define EMAC_DMABUSMOD_PR_S 14 -#define EMAC_DMABUSMOD_PBL_S 8 -#define EMAC_DMABUSMOD_DSL_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXPOLLD register. -// -//***************************************************************************** -#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand -#define EMAC_TXPOLLD_TPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXPOLLD register. -// -//***************************************************************************** -#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand -#define EMAC_RXPOLLD_RPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXDLADDR -// register. -// -//***************************************************************************** -#define EMAC_RXDLADDR_STRXLIST_M \ - 0xFFFFFFFC // Start of Receive List -#define EMAC_RXDLADDR_STRXLIST_S \ - 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_TXDLADDR -// register. -// -//***************************************************************************** -#define EMAC_TXDLADDR_TXDLADDR_M \ - 0xFFFFFFFC // Start of Transmit List Base - // Address -#define EMAC_TXDLADDR_TXDLADDR_S \ - 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMARIS register. -// -//***************************************************************************** -#define EMAC_DMARIS_LPI 0x40000000 // LPI Trigger Interrupt Status -#define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt - // Status -#define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status -#define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt -#define EMAC_DMARIS_AE_M 0x03800000 // Access Error -#define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data - // Transfer -#define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data - // Transfer -#define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor - // Write Access -#define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor - // Write Access -#define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor - // Read Access -#define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor - // Read Access -#define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State -#define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit - // command processed -#define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit - // transfer descriptor -#define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status -#define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host - // memory buffer and queuing it to - // transmit buffer (TX FIFO) -#define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp -#define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor - // unavailable or transmit buffer - // underflow -#define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit - // descriptor -#define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State -#define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive - // command issued -#define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive - // transfer descriptor -#define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive - // packet -#define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor - // unavailable -#define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive - // descriptor -#define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp -#define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the - // receive packet data from receive - // buffer to host memory -#define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary -#define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary -#define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt -#define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt -#define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt -#define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout -#define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped -#define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable -#define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt -#define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow -#define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow -#define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout -#define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable -#define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped -#define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMAOPMODE -// register. -// -//***************************************************************************** -#define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP - // Checksum Error Frames -#define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward -#define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received - // Frames -#define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward -#define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO -#define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control -#define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes -#define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes -#define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes -#define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes -#define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes -#define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes -#define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes -#define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes -#define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission - // Command -#define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames -#define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames -#define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable -#define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control -#define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes -#define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes -#define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes -#define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes -#define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame -#define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_DMAIM register. -// -//***************************************************************************** -#define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable -#define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary - // Enable -#define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable -#define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable -#define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable -#define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable -#define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable -#define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable - // Enable -#define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable -#define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable -#define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable -#define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable -#define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable - // Enable -#define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable -#define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_MFBOC register. -// -//***************************************************************************** -#define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow - // Counter -#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter -#define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame - // Counter -#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter -#define EMAC_MFBOC_OVFFRMCNT_S 17 -#define EMAC_MFBOC_MISFRMCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_RXINTWDT -// register. -// -//***************************************************************************** -#define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer - // Count -#define EMAC_RXINTWDT_RIWT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSTXDESC -// register. -// -//***************************************************************************** -#define EMAC_HOSTXDESC_CURTXDESC_M \ - 0xFFFFFFFF // Host Transmit Descriptor Address - // Pointer -#define EMAC_HOSTXDESC_CURTXDESC_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSRXDESC -// register. -// -//***************************************************************************** -#define EMAC_HOSRXDESC_CURRXDESC_M \ - 0xFFFFFFFF // Host Receive Descriptor Address - // Pointer -#define EMAC_HOSRXDESC_CURRXDESC_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSTXBA register. -// -//***************************************************************************** -#define EMAC_HOSTXBA_CURTXBUFA_M \ - 0xFFFFFFFF // Host Transmit Buffer Address - // Pointer -#define EMAC_HOSTXBA_CURTXBUFA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_HOSRXBA register. -// -//***************************************************************************** -#define EMAC_HOSRXBA_CURRXBUFA_M \ - 0xFFFFFFFF // Host Receive Buffer Address - // Pointer -#define EMAC_HOSRXBA_CURRXBUFA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PP register. -// -//***************************************************************************** -#define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type -#define EMAC_PP_MACTYPE_1 0x00000100 // Tiva TM4E129x-class MAC -#define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type -#define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY -#define EMAC_PP_PHYTYPE_1 0x00000003 // Snowflake class PHY - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_PC register. -// -//***************************************************************************** -#define EMAC_PC_PHYEXT 0x80000000 // PHY Select -#define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select -#define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal - // PHY or external PHY connected - // via MII -#define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY - // connected via RMII -#define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart -#define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection - // Disable -#define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle -#define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss -#define EMAC_PC_LRR 0x00200000 // Link Loss Recovery -#define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run -#define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode -#define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap -#define EMAC_PC_MDISWAP 0x00002000 // MDI Swap -#define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X -#define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X -#define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable -#define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection -#define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect -#define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability -#define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable -#define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select -#define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable -#define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode -#define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is - // 10Base-T, Half-Duplex -#define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is - // 10Base-T, Full-Duplex -#define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is - // 100Base-TX, Half-Duplex -#define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is - // 100Base-TX, Full-Duplex -#define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold -#define EMAC_PC_FASTLDMODE_S 15 -#define EMAC_PC_FASTANSEL_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_CC register. -// -//***************************************************************************** -#define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable -#define EMAC_CC_POL 0x00020000 // LED Polarity Control -#define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_EPHYRIS register. -// -//***************************************************************************** -#define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_EPHYIM register. -// -//***************************************************************************** -#define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EMAC_O_EPHYMISC -// register. -// -//***************************************************************************** -#define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear - // register - -//***************************************************************************** -// -// The following are defines for the EPHY register offsets. -// -//***************************************************************************** -#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control -#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status -#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register - // 1 -#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register - // 2 -#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation - // Advertisement -#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation - // Link Partner Ability -#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation - // Expansion -#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation - // Next Page TX -#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation - // Link Partner Ability Next Page -#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1 -#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2 -#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3 -#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control -#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data -#define EPHY_STS 0x00000010 // Ethernet PHY Status -#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control -#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt - // Status 1 -#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt - // Status 2 -#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense - // Counter -#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count -#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control -#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control -#define EPHY_CTL 0x00000019 // Ethernet PHY Control -#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T - // Status/Control - MR26 -#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and - // Status 1 -#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and - // Status 2 -#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic - // Control -#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control -#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BMCR register. -// -//***************************************************************************** -#define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset -#define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback -#define EPHY_BMCR_SPEED 0x00002000 // Speed Select -#define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable -#define EPHY_BMCR_PWRDWN 0x00000800 // Power Down -#define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate -#define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation -#define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode -#define EPHY_BMCR_COLLTST 0x00000080 // Collision Test - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BMSR register. -// -//***************************************************************************** -#define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable -#define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable -#define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable -#define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable -#define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable -#define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete -#define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault -#define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled -#define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status -#define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect -#define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ID1 register. -// -//***************************************************************************** -#define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits -#define EPHY_ID1_OUIMSB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ID2 register. -// -//***************************************************************************** -#define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits -#define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number -#define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number -#define EPHY_ID2_OUILSB_S 10 -#define EPHY_ID2_VNDRMDL_S 4 -#define EPHY_ID2_MDLREV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANA register. -// -//***************************************************************************** -#define EPHY_ANA_NP 0x00008000 // Next Page Indication -#define EPHY_ANA_RF 0x00002000 // Remote Fault -#define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for - // Full Duplex Links -#define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex - // Links -#define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support -#define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support -#define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support -#define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support -#define EPHY_ANA_10BT 0x00000020 // 10Base-T Support -#define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection -#define EPHY_ANA_SELECT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANLPA register. -// -//***************************************************************************** -#define EPHY_ANLPA_NP 0x00008000 // Next Page Indication -#define EPHY_ANLPA_ACK 0x00004000 // Acknowledge -#define EPHY_ANLPA_RF 0x00002000 // Remote Fault -#define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE -#define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE -#define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support -#define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support -#define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support -#define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support -#define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support -#define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection -#define EPHY_ANLPA_SELECT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANER register. -// -//***************************************************************************** -#define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault -#define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able -#define EPHY_ANER_NPABLE 0x00000004 // Next Page Able -#define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received -#define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation - // Able - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANNPTR register. -// -//***************************************************************************** -#define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication -#define EPHY_ANNPTR_MP 0x00002000 // Message Page -#define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2 -#define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle -#define EPHY_ANNPTR_CODE_M 0x000007FF // Code -#define EPHY_ANNPTR_CODE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ANLNPTR register. -// -//***************************************************************************** -#define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication -#define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge -#define EPHY_ANLNPTR_MP 0x00002000 // Message Page -#define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2 -#define EPHY_ANLNPTR_TOG 0x00000800 // Toggle -#define EPHY_ANLNPTR_CODE_M 0x000007FF // Code -#define EPHY_ANLNPTR_CODE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CFG1 register. -// -//***************************************************************************** -#define EPHY_CFG1_DONE 0x00008000 // Configuration Done -#define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down -#define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery -#define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX -#define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX -#define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable -#define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select - // Configuration -#define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms -#define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms -#define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms -#define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CFG2 register. -// -//***************************************************************************** -#define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect - // Mode -#define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability -#define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality -#define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when - // Enhanced Link is not Achievable -#define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol - // Error During IDLE State -#define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CFG3 register. -// -//***************************************************************************** -#define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap -#define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap -#define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes -#define EPHY_CFG3_FLDWNM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_REGCTL register. -// -//***************************************************************************** -#define EPHY_REGCTL_FUNC_M 0x0000C000 // Function -#define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address -#define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment -#define EPHY_REGCTL_FUNC_DATAPIRW \ - 0x00008000 // Data, post increment on read and - // write -#define EPHY_REGCTL_FUNC_DATAPIWO \ - 0x0000C000 // Data, post increment on write - // only -#define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address -#define EPHY_REGCTL_DEVAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_ADDAR register. -// -//***************************************************************************** -#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data -#define EPHY_ADDAR_ADDRDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_STS register. -// -//***************************************************************************** -#define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode -#define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch -#define EPHY_STS_POLSTAT 0x00001000 // Polarity Status -#define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch -#define EPHY_STS_SD 0x00000400 // Signal Detect -#define EPHY_STS_DL 0x00000200 // Descrambler Lock -#define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received -#define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending -#define EPHY_STS_RF 0x00000040 // Remote Fault -#define EPHY_STS_JD 0x00000020 // Jabber Detect -#define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status -#define EPHY_STS_MIILB 0x00000008 // MII Loopback Status -#define EPHY_STS_DUPLEX 0x00000004 // Duplex Status -#define EPHY_STS_SPEED 0x00000002 // Speed Status -#define EPHY_STS_LINK 0x00000001 // Link Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_SCR register. -// -//***************************************************************************** -#define EPHY_SCR_DISCLK 0x00008000 // Disable CLK -#define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable -#define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes -#define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode. - // PHY is fully functional -#define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down -#define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep -#define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep -#define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass -#define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth -#define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO -#define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO -#define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO -#define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO -#define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode -#define EPHY_SCR_TINT 0x00000004 // Test Interrupt -#define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_MISR1 register. -// -//***************************************************************************** -#define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt -#define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt -#define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status - // Interrupt -#define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete - // Interrupt -#define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full - // Interrupt -#define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full - // Interrupt -#define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable -#define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable -#define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable -#define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete - // Interrupt Enable -#define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register - // half-full Interrupt Enable -#define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register - // Half-Full Event Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_MISR2 register. -// -//***************************************************************************** -#define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt -#define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt -#define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow - // Event Interrupt -#define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status - // Changed Interrupt -#define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt -#define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt -#define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt -#define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt - // Enable -#define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable -#define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow - // Interrupt Enable -#define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status - // Changed Interrupt Enable -#define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt - // Enable -#define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt - // Enable -#define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_FCSCR register. -// -//***************************************************************************** -#define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter -#define EPHY_FCSCR_FCSCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_RXERCNT register. -// -//***************************************************************************** -#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count -#define EPHY_RXERCNT_RXERRCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BISTCR register. -// -//***************************************************************************** -#define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode -#define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets -#define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable -#define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication -#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss - // Indication -#define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status - // Indication -#define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication -#define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback - // Mode -#define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select -#define EPHY_BISTCR_LBMODE_NPCSIN \ - 0x00000001 // Near-end loopback: PCS Input - // Loopback -#define EPHY_BISTCR_LBMODE_NPCSOUT \ - 0x00000002 // Near-end loopback: PCS Output - // Loopback (In 100Base-TX only) -#define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital - // Loopback -#define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog - // Loopback (requires 100 Ohm - // termination) -#define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse - // Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_LEDCR register. -// -//***************************************************************************** -#define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF - // duration): -#define EPHY_LEDCR_BLINKRATE_20HZ \ - 0x00000000 // 20 Hz (50 ms) -#define EPHY_LEDCR_BLINKRATE_10HZ \ - 0x00000200 // 10 Hz (100 ms) -#define EPHY_LEDCR_BLINKRATE_5HZ \ - 0x00000400 // 5 Hz (200 ms) -#define EPHY_LEDCR_BLINKRATE_2HZ \ - 0x00000600 // 2 Hz (500 ms) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CTL register. -// -//***************************************************************************** -#define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable -#define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX -#define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status -#define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status -#define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status -#define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_10BTSC register. -// -//***************************************************************************** -#define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable -#define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration -#define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP) - // Transmission Control -#define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status -#define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable -#define EPHY_10BTSC_SQUELCH_S 9 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BICSR1 register. -// -//***************************************************************************** -#define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count -#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length -#define EPHY_BICSR1_ERRCNT_S 8 -#define EPHY_BICSR1_IPGLENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_BICSR2 register. -// -//***************************************************************************** -#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length -#define EPHY_BICSR2_PKTLENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_CDCR register. -// -//***************************************************************************** -#define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start -#define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication -#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication -#define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication -#define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication -#define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done -#define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_RCR register. -// -//***************************************************************************** -#define EPHY_RCR_SWRST 0x00008000 // Software Reset -#define EPHY_RCR_SWRESTART 0x00004000 // Software Restart - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPHY_LEDCFG register. -// -//***************************************************************************** -#define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration -#define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK -#define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity -#define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity -#define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity -#define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision -#define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX -#define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX -#define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex -#define EPHY_LEDCFG_LED2_LINKTXRX \ - 0x00000800 // Link OK/Blink on TX/RX Activity -#define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration -#define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK -#define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity -#define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity -#define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity -#define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision -#define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX -#define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX -#define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex -#define EPHY_LEDCFG_LED1_LINKTXRX \ - 0x00000080 // Link OK/Blink on TX/RX Activity -#define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration -#define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK -#define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity -#define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity -#define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity -#define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision -#define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX -#define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX -#define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex -#define EPHY_LEDCFG_LED0_LINKTXRX \ - 0x00000008 // Link OK/Blink on TX/RX Activity - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the -// EMAC_O_PPSCTRL register. -// -//***************************************************************************** -#define EMAC_PPSCTRL_PPSCTRL_1HZ \ - 0x00000000 // When the PPSEN0 bit = 0x0, the - // EN0PPS signal is 1 pulse of the - // PTP reference clock.(of width - // clk_ptp_i) every second -#define EMAC_PPSCTRL_PPSCTRL_2HZ \ - 0x00000001 // When the PPSEN0 bit = 0x0, the - // binary rollover is 2 Hz, and the - // digital rollover is 1 Hz -#define EMAC_PPSCTRL_PPSCTRL_4HZ \ - 0x00000002 // When the PPSEN0 bit = 0x0, the - // binary rollover is 4 Hz, and the - // digital rollover is 2 Hz -#define EMAC_PPSCTRL_PPSCTRL_8HZ \ - 0x00000003 // When thePPSEN0 bit = 0x0, the - // binary rollover is 8 Hz, and the - // digital rollover is 4 Hz, -#define EMAC_PPSCTRL_PPSCTRL_16HZ \ - 0x00000004 // When thePPSEN0 bit = 0x0, the - // binary rollover is 16 Hz, and - // the digital rollover is 8 Hz -#define EMAC_PPSCTRL_PPSCTRL_32HZ \ - 0x00000005 // When thePPSEN0 bit = 0x0, the - // binary rollover is 32 Hz, and - // the digital rollover is 16 Hz -#define EMAC_PPSCTRL_PPSCTRL_64HZ \ - 0x00000006 // When thePPSEN0 bit = 0x0, the - // binary rollover is 64 Hz, and - // the digital rollover is 32 Hz -#define EMAC_PPSCTRL_PPSCTRL_128HZ \ - 0x00000007 // When thePPSEN0 bit = 0x0, the - // binary rollover is 128 Hz, and - // the digital rollover is 64 Hz -#define EMAC_PPSCTRL_PPSCTRL_256HZ \ - 0x00000008 // When thePPSEN0 bit = 0x0, the - // binary rollover is 256 Hz, and - // the digital rollover is 128 Hz -#define EMAC_PPSCTRL_PPSCTRL_512HZ \ - 0x00000009 // When thePPSEN0 bit = 0x0, the - // binary rollover is 512 Hz, and - // the digital rollover is 256 Hz -#define EMAC_PPSCTRL_PPSCTRL_1024HZ \ - 0x0000000A // When the PPSEN0 bit = 0x0, the - // binary rollover is 1.024 kHz, - // and the digital rollover is 512 - // Hz -#define EMAC_PPSCTRL_PPSCTRL_2048HZ \ - 0x0000000B // When thePPSEN0 bit = 0x0, the - // binary rollover is 2.048 kHz, - // and the digital rollover is - // 1.024 kHz -#define EMAC_PPSCTRL_PPSCTRL_4096HZ \ - 0x0000000C // When thePPSEN0 bit = 0x0, the - // binary rollover is 4.096 kHz, - // and the digital rollover is - // 2.048 kHz -#define EMAC_PPSCTRL_PPSCTRL_8192HZ \ - 0x0000000D // When thePPSEN0 bit = 0x0, the - // binary rollover is 8.192 kHz, - // and the digital rollover is - // 4.096 kHz -#define EMAC_PPSCTRL_PPSCTRL_16384HZ \ - 0x0000000E // When thePPSEN0 bit = 0x0, the - // binary rollover is 16.384 kHz, - // and the digital rollover is - // 8.092 kHz -#define EMAC_PPSCTRL_PPSCTRL_32768HZ \ - 0x0000000F // When thePPSEN0 bit = 0x0, the - // binary rollover is 32.768 KHz, - // and the digital rollover is - // 16.384 KHz - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the EMAC_O_CC -// register. -// -//***************************************************************************** -#define EMAC_CC_CS_PA7 0x00000001 // GPIO - -#endif - -#endif // __HW_EMAC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_epi.h b/bsp/tm4c129x-dk/libraries/inc/hw_epi.h deleted file mode 100644 index ea9f065562..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_epi.h +++ /dev/null @@ -1,933 +0,0 @@ -//***************************************************************************** -// -// hw_epi.h - Macros for use in accessing the EPI registers. -// -// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_EPI_H__ -#define __HW_EPI_H__ - -//***************************************************************************** -// -// The following are defines for the External Peripheral Interface register -// offsets. -// -//***************************************************************************** -#define EPI_O_CFG 0x00000000 // EPI Configuration -#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate -#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate -#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration -#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose - // Configuration -#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration -#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration -#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 -#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 -#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map -#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 -#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 -#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 -#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 -#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 -#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 -#define EPI_O_STAT 0x00000060 // EPI Status -#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count -#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO -#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 -#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 -#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 -#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 -#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 -#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 -#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 -#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects -#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count -#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count -#define EPI_O_IM 0x00000210 // EPI Interrupt Mask -#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status -#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status -#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status - // and Clear -#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3 -#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3 -#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4 -#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4 -#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension -#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension -#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension -#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension -#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension -#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_CFG register. -// -//***************************************************************************** -#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable -#define EPI_CFG_BLKEN 0x00000010 // Block Enable -#define EPI_CFG_MODE_M 0x0000000F // Mode Select -#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose -#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM -#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) -#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD register. -// -//***************************************************************************** -#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 -#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 -#define EPI_BAUD_COUNT1_S 16 -#define EPI_BAUD_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD2 register. -// -//***************************************************************************** -#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 -#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 -#define EPI_BAUD2_COUNT1_S 16 -#define EPI_BAUD2_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG register. -// -//***************************************************************************** -#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle -#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register - // Write -#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register - // Read -#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode -#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration -#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] -#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] -#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] -#define EPI_HB16CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_GPCFG register. -// -//***************************************************************************** -#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin -#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated -#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame -#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count -#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes -#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size -#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address -#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide -#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size - // cannot be used with 24-bit data -#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size - // cannot be used with data sizes - // other than 8 -#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus -#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) -#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) -#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) -#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) -#define EPI_GPCFG_FRMCNT_S 22 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. -// -//***************************************************************************** -#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range -#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz -#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz -#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz -#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter -#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode -#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM -#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) -#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) -#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) -#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) -#define EPI_SDRAMCFG_RFSH_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG register. -// -//***************************************************************************** -#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle -#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] -#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] -#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] -#define EPI_HB8CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. -// -//***************************************************************************** -#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG2 register. -// -//***************************************************************************** -#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration - // Register Write -#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration - // Register Read -#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode -#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_ADDRMAP register. -// -//***************************************************************************** -#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size -#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: - // 0x000.0000 to 0x0FFF.FFFF -#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address -#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 -#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size -#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address -#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 -#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 -#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS2n maps to - // 0xA000.0000 and CS3n maps to - // 0xC000.0000 -#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size -#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address -#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 -#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 -#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS0n maps to - // 0x6000.0000 and CS1n maps to - // 0x8000.0000 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE0 register. -// -//***************************************************************************** -#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR0 register. -// -//***************************************************************************** -#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD0 register. -// -//***************************************************************************** -#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD0_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE1 register. -// -//***************************************************************************** -#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR1 register. -// -//***************************************************************************** -#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD1 register. -// -//***************************************************************************** -#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD1_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_STAT register. -// -//***************************************************************************** -#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full -#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty -#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence -#define EPI_STAT_WBUSY 0x00000020 // Write Busy -#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy -#define EPI_STAT_ACTIVE 0x00000001 // Register Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. -// -//***************************************************************************** -#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count -#define EPI_RFIFOCNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO0 -// register. -// -//***************************************************************************** -#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO1 -// register. -// -//***************************************************************************** -#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO2 -// register. -// -//***************************************************************************** -#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO3 -// register. -// -//***************************************************************************** -#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO4 -// register. -// -//***************************************************************************** -#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO4_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO5 -// register. -// -//***************************************************************************** -#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO5_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO6 -// register. -// -//***************************************************************************** -#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO6_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO7 -// register. -// -//***************************************************************************** -#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO7_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_FIFOLVL register. -// -//***************************************************************************** -#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error -#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error -#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO -#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while - // WRFIFO is empty. -#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until - // there are only two slots - // available. Thus, trigger is - // deasserted when there are two - // WRFIFO entries present. This - // configuration is optimized for - // bursts of 2 -#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until - // there is one WRFIFO entry - // available. This configuration - // expects only single writes -#define EPI_FIFOLVL_WRFIFO_NFULL \ - 0x00000040 // Trigger interrupt when WRFIFO is - // not full, meaning trigger will - // continue to assert until there - // are four entries in the WRFIFO -#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO -#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty -#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries - // in the NBRFIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. -// -//***************************************************************************** -#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions -#define EPI_WFIFOCNT_WTAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_DMATXCNT register. -// -//***************************************************************************** -#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count -#define EPI_DMATXCNT_TXCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_IM register. -// -//***************************************************************************** -#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask -#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask -#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask -#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask -#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RIS register. -// -//***************************************************************************** -#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status -#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status -#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status -#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status -#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_MIS register. -// -//***************************************************************************** -#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt - // Status -#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt - // Status -#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status -#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status -#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_EISC register. -// -//***************************************************************************** -#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear -#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear -#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error -#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error -#define EPI_EISC_TOUT 0x00000001 // Timeout Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG3 register. -// -//***************************************************************************** -#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG3 register. -// -//***************************************************************************** -#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration - // Register Write -#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration - // Register Read -#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode -#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG4 register. -// -//***************************************************************************** -#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity -#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration - // Register Write -#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration - // Register Read -#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode -#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG4 register. -// -//***************************************************************************** -#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME register. -// -//***************************************************************************** -#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB8TIME_IRDYDLY_S 24 -#define EPI_HB8TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME register. -// -//***************************************************************************** -#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB16TIME_IRDYDLY_S 24 -#define EPI_HB16TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME2 register. -// -//***************************************************************************** -#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB8TIME2_IRDYDLY_S 24 -#define EPI_HB8TIME2_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME2 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME2_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME2_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME2_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME2_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME2_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME2_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME2_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME2_CAPWIDTH_M \ - 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB16TIME2_IRDYDLY_S 24 -#define EPI_HB16TIME2_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME3 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME3_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME3_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME3_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME3_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME3_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME3_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME3_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME3_CAPWIDTH_M \ - 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB16TIME3_IRDYDLY_S 24 -#define EPI_HB16TIME3_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME3 register. -// -//***************************************************************************** -#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB8TIME3_IRDYDLY_S 24 -#define EPI_HB8TIME3_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME4 register. -// -//***************************************************************************** -#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB8TIME4_IRDYDLY_S 24 -#define EPI_HB8TIME4_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME4 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME4_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME4_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME4_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME4_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME4_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME4_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME4_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME4_CAPWIDTH_M \ - 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB16TIME4_IRDYDLY_S 24 -#define EPI_HB16TIME4_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HBPSRAM register. -// -//***************************************************************************** -#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register -#define EPI_HBPSRAM_CR_S 0 - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL -// register. -// -//***************************************************************************** -#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 - // spaces available in the WFIFO -#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 - // spaces available in the WFIFO -#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space - // available in the WFIFO -#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries - // in the NBRFIFO - -#endif - -#endif // __HW_EPI_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_flash.h b/bsp/tm4c129x-dk/libraries/inc/hw_flash.h deleted file mode 100644 index e38e85b59d..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_flash.h +++ /dev/null @@ -1,625 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following are defines for the FLASH register offsets. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Flash Memory Address -#define FLASH_FMD 0x400FD004 // Flash Memory Data -#define FLASH_FMC 0x400FD008 // Flash Memory Control -#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt - // Status -#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask -#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked - // Interrupt Status and Clear -#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2 -#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid -#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key -#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n -#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties -#define FLASH_FSIZE 0x400FDFC0 // Flash Size -#define FLASH_SSIZE 0x400FDFC4 // SRAM Size -#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register -#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map -#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size -#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address -#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer -#define FLASH_RMCTL 0x400FE0F0 // ROM Control -#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration -#define FLASH_USERREG0 0x400FE1E0 // User Register 0 -#define FLASH_USERREG1 0x400FE1E4 // User Register 1 -#define FLASH_USERREG2 0x400FE1E8 // User Register 2 -#define FLASH_USERREG3 0x400FE1EC // User Register 3 -#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read - // Enable 0 -#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read - // Enable 1 -#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read - // Enable 2 -#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read - // Enable 3 -#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read - // Enable 4 -#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read - // Enable 5 -#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read - // Enable 6 -#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read - // Enable 7 -#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read - // Enable 8 -#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read - // Enable 9 -#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read - // Enable 10 -#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read - // Enable 11 -#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read - // Enable 12 -#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read - // Enable 13 -#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read - // Enable 14 -#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read - // Enable 15 -#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program - // Enable 0 -#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program - // Enable 1 -#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program - // Enable 2 -#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program - // Enable 3 -#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program - // Enable 4 -#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program - // Enable 5 -#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program - // Enable 6 -#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program - // Enable 7 -#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program - // Enable 8 -#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program - // Enable 9 -#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program - // Enable 10 -#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program - // Enable 11 -#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program - // Enable 12 -#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program - // Enable 13 -#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program - // Enable 14 -#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program - // Enable 15 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMA register. -// -//***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset -#define FLASH_FMA_OFFSET_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMD register. -// -//***************************************************************************** -#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value -#define FLASH_FMD_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit Register Value -#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory -#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory -#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw - // Interrupt Status -#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt - // Status -#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt - // Status -#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt - // Status -#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status -#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status -#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask -#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask -#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask -#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask -#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask -#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCMISC register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and - // Clear -#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC2 register. -// -//***************************************************************************** -#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBVAL register. -// -//***************************************************************************** -#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FLPEKEY register. -// -//***************************************************************************** -#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value -#define FLASH_FLPEKEY_PEKEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBN register. -// -//***************************************************************************** -#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_PP register. -// -//***************************************************************************** -#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode -#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode -#define FLASH_PP_DFA 0x10000000 // DMA Flash Access -#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the - // physical bank -#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB -#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB -#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB -#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB -#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the - // physical bank -#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB -#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB -#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB -#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB -#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB -#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash -#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FSIZE register. -// -//***************************************************************************** -#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash -#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash -#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash -#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_SSIZE register. -// -//***************************************************************************** -#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size -#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM -#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM -#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM -#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CONF register. -// -//***************************************************************************** -#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable -#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable -#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags -#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On -#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_ROMSWMAP register. -// -//***************************************************************************** -#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present -#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability -#define FLASH_ROMSWMAP_SW0EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW0EN_CORE \ - 0x00000001 // Region available to core -#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability -#define FLASH_ROMSWMAP_SW1EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW1EN_CORE \ - 0x00000004 // Region available to core -#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability -#define FLASH_ROMSWMAP_SW2EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW2EN_CORE \ - 0x00000010 // Region available to core -#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability -#define FLASH_ROMSWMAP_SW3EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW3EN_CORE \ - 0x00000040 // Region available to core -#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability -#define FLASH_ROMSWMAP_SW4EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW4EN_CORE \ - 0x00000100 // Region available to core -#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability -#define FLASH_ROMSWMAP_SW5EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW5EN_CORE \ - 0x00000400 // Region available to core -#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability -#define FLASH_ROMSWMAP_SW6EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW6EN_CORE \ - 0x00001000 // Region available to core -#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability -#define FLASH_ROMSWMAP_SW7EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW7EN_CORE \ - 0x00004000 // Region available to core - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMASZ register. -// -//***************************************************************************** -#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size -#define FLASH_DMASZ_SIZE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMAST register. -// -//***************************************************************************** -#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of - // the flash region accessible by - // uDMA if the FLASHPP register DFA - // bit is set -#define FLASH_DMAST_ADDR_S 11 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RVP register. -// -//***************************************************************************** -#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address -#define FLASH_RVP_RV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RMCTL register. -// -//***************************************************************************** -#define FLASH_RMCTL_BA 0x00000001 // Boot Alias - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_BOOTCFG register. -// -//***************************************************************************** -#define FLASH_BOOTCFG_NW 0x80000000 // Not Written -#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port -#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A -#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B -#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C -#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D -#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E -#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F -#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G -#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H -#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin -#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 -#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 -#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 -#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 -#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 -#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 -#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 -#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 -#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity -#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable -#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select -#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 -#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG0 register. -// -//***************************************************************************** -#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG1 register. -// -//***************************************************************************** -#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG2 register. -// -//***************************************************************************** -#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG3 register. -// -//***************************************************************************** -#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE8 register. -// -//***************************************************************************** -#define FLASH_FMPRE8_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE8_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE9 register. -// -//***************************************************************************** -#define FLASH_FMPRE9_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE9_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE10 register. -// -//***************************************************************************** -#define FLASH_FMPRE10_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE10_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE11 register. -// -//***************************************************************************** -#define FLASH_FMPRE11_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE11_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE12 register. -// -//***************************************************************************** -#define FLASH_FMPRE12_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE12_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE13 register. -// -//***************************************************************************** -#define FLASH_FMPRE13_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE13_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE14 register. -// -//***************************************************************************** -#define FLASH_FMPRE14_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE14_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE15 register. -// -//***************************************************************************** -#define FLASH_FMPRE15_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE15_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE8 register. -// -//***************************************************************************** -#define FLASH_FMPPE8_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE8_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE9 register. -// -//***************************************************************************** -#define FLASH_FMPPE9_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE9_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE10 register. -// -//***************************************************************************** -#define FLASH_FMPPE10_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE10_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE11 register. -// -//***************************************************************************** -#define FLASH_FMPPE11_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE11_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE12 register. -// -//***************************************************************************** -#define FLASH_FMPPE12_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE12_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE13 register. -// -//***************************************************************************** -#define FLASH_FMPPE13_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE13_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE14 register. -// -//***************************************************************************** -#define FLASH_FMPPE14_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE14_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE15 register. -// -//***************************************************************************** -#define FLASH_FMPPE15_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE15_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the erase size of the FLASH block that is -// erased by an erase operation, and the protect size is the size of the FLASH -// block that is protected by each protection register. -// -//***************************************************************************** -#define FLASH_PROTECT_SIZE 0x00000800 -#define FLASH_ERASE_SIZE 0x00000400 - -#endif // __HW_FLASH_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_gpio.h b/bsp/tm4c129x-dk/libraries/inc/hw_gpio.h deleted file mode 100644 index 9e95aed435..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_gpio.h +++ /dev/null @@ -1,213 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// The following are defines for the GPIO register offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // GPIO Data -#define GPIO_O_DIR 0x00000400 // GPIO Direction -#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense -#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges -#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event -#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask -#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status -#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status -#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear -#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select -#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select -#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select -#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select -#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select -#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select -#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select -#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select -#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable -#define GPIO_O_LOCK 0x00000520 // GPIO Lock -#define GPIO_O_CR 0x00000524 // GPIO Commit -#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select -#define GPIO_O_PCTL 0x0000052C // GPIO Port Control -#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control -#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control -#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt -#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select -#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable -#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level -#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status -#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property -#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_IM register. -// -//***************************************************************************** -#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask - // Enable -#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable -#define GPIO_IM_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_RIS register. -// -//***************************************************************************** -#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw - // Status -#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status -#define GPIO_RIS_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_MIS register. -// -//***************************************************************************** -#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt - // Status -#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status -#define GPIO_MIS_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_ICR register. -// -//***************************************************************************** -#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear -#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear -#define GPIO_ICR_GPIO_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_LOCK register. -// -//***************************************************************************** -#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock -#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked - // and may be modified -#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked - // and may not be modified -#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_SI register. -// -//***************************************************************************** -#define GPIO_SI_SUM 0x00000001 // Summary Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_DR12R register. -// -//***************************************************************************** -#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable -#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has - // 12-mA drive. This encoding is - // only valid if the GPIOPP EDE bit - // is set and the appropriate - // GPIOPC EDM bit field is - // programmed to 0x3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_WAKEPEN register. -// -//***************************************************************************** -#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_WAKELVL register. -// -//***************************************************************************** -#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_WAKESTAT -// register. -// -//***************************************************************************** -#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_PP register. -// -//***************************************************************************** -#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_PC register. -// -//***************************************************************************** -#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7 -#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6 -#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5 -#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4 -#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3 -#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2 -#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1 -#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0 -#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA - // are maintained. GPIO n Drive - // Select (GPIODRnR) registers - // function as normal -#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is - // provided -#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled; - // setting the corresponding - // GPIODR4R register bit adds 2 mA - // and setting the corresponding - // GPIODR8R of GPIODR12R register - // bit adds an additional 4 mA -#define GPIO_PC_EDM7_S 14 -#define GPIO_PC_EDM6_S 12 -#define GPIO_PC_EDM5_S 10 -#define GPIO_PC_EDM4_S 8 -#define GPIO_PC_EDM3_S 6 -#define GPIO_PC_EDM2_S 4 -#define GPIO_PC_EDM1_S 2 - -#endif // __HW_GPIO_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_hibernate.h b/bsp/tm4c129x-dk/libraries/inc/hw_hibernate.h deleted file mode 100644 index ce469a20e1..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_hibernate.h +++ /dev/null @@ -1,483 +0,0 @@ -//***************************************************************************** -// -// hw_hibernate.h - Defines and Macros for the Hibernation module. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_HIBERNATE_H__ -#define __HW_HIBERNATE_H__ - -//***************************************************************************** -// -// The following are defines for the Hibernation module register addresses. -// -//***************************************************************************** -#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter -#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 -#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load -#define HIB_CTL 0x400FC010 // Hibernation Control -#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask -#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status -#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt - // Status -#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear -#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim -#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds -#define HIB_IO 0x400FC02C // Hibernation IO Configuration -#define HIB_DATA 0x400FC030 // Hibernation Data -#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control -#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0 -#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1 -#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0 -#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load -#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0 -#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1 -#define HIB_LOCK 0x400FC360 // Hibernation Lock -#define HIB_TPCTL 0x400FC400 // HIB Tamper Control -#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status -#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control -#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0 -#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1 -#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2 -#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3 -#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4 -#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5 -#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6 -#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7 -#define HIB_PP 0x400FCFC0 // Hibernation Peripheral - // Properties -#define HIB_CC 0x400FCFC8 // Hibernation Clock Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCC register. -// -//***************************************************************************** -#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter -#define HIB_RTCC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM0 register. -// -//***************************************************************************** -#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 -#define HIB_RTCM0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCLD register. -// -//***************************************************************************** -#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load -#define HIB_RTCLD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CTL register. -// -//***************************************************************************** -#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable -#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear -#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select -#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability -#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass -#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery - // Comparator -#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts -#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) -#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts -#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts -#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status -#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery -#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered -#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable -#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable -#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable -#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable -#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request -#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IM register. -// -//***************************************************************************** -#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_IM_WC 0x00000010 // External Write Complete/Capable - // Interrupt Mask -#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask -#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Mask -#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RIS register. -// -//***************************************************************************** -#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status -#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw - // Interrupt Status -#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt - // Status -#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw - // Interrupt Status -#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt - // Status -#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw - // Interrupt Status -#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_MIS register. -// -//***************************************************************************** -#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked - // Interrupt Status -#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Status -#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Status -#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IC register. -// -//***************************************************************************** -#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear -#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Clear -#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear -#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt - // Clear -#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear -#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Clear -#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCT register. -// -//***************************************************************************** -#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value -#define HIB_RTCT_TRIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCSS register. -// -//***************************************************************************** -#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match -#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count -#define HIB_RTCSS_RTCSSM_S 16 -#define HIB_RTCSS_RTCSSC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IO register. -// -//***************************************************************************** -#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete -#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable -#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_DATA register. -// -//***************************************************************************** -#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data -#define HIB_DATA_RTD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALCTL register. -// -//***************************************************************************** -#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode -#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL0 register. -// -//***************************************************************************** -#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CAL0_HR_M 0x001F0000 // Hours -#define HIB_CAL0_MIN_M 0x00003F00 // Minutes -#define HIB_CAL0_SEC_M 0x0000003F // Seconds -#define HIB_CAL0_HR_S 16 -#define HIB_CAL0_MIN_S 8 -#define HIB_CAL0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL1 register. -// -//***************************************************************************** -#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL1_DOW_M 0x07000000 // Day of Week -#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value -#define HIB_CAL1_MON_M 0x00000F00 // Month -#define HIB_CAL1_DOM_M 0x0000001F // Day of Month -#define HIB_CAL1_DOW_S 24 -#define HIB_CAL1_YEAR_S 16 -#define HIB_CAL1_MON_S 8 -#define HIB_CAL1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD0 register. -// -//***************************************************************************** -#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALLD0_HR_M 0x001F0000 // Hours -#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes -#define HIB_CALLD0_SEC_M 0x0000003F // Seconds -#define HIB_CALLD0_HR_S 16 -#define HIB_CALLD0_MIN_S 8 -#define HIB_CALLD0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD1 register. -// -//***************************************************************************** -#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week -#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value -#define HIB_CALLD1_MON_M 0x00000F00 // Month -#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month -#define HIB_CALLD1_DOW_S 24 -#define HIB_CALLD1_YEAR_S 16 -#define HIB_CALLD1_MON_S 8 -#define HIB_CALLD1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM0 register. -// -//***************************************************************************** -#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALM0_HR_M 0x001F0000 // Hours -#define HIB_CALM0_MIN_M 0x00003F00 // Minutes -#define HIB_CALM0_SEC_M 0x0000003F // Seconds -#define HIB_CALM0_HR_S 16 -#define HIB_CALM0_MIN_S 8 -#define HIB_CALM0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM1 register. -// -//***************************************************************************** -#define HIB_CALM1_DOM_M 0x0000001F // Day of Month -#define HIB_CALM1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_LOCK register. -// -//***************************************************************************** -#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock -#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key -#define HIB_LOCK_HIBLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPCTL register. -// -//***************************************************************************** -#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper - // Event -#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event -#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on - // tamper event -#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper - // event -#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear -#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPSTAT register. -// -//***************************************************************************** -#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status -#define HIB_TPSTAT_STATE_DISABLED \ - 0x00000000 // Tamper disabled -#define HIB_TPSTAT_STATE_CONFIGED \ - 0x00000004 // Tamper configured -#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred -#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status -#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPIO register. -// -//***************************************************************************** -#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering -#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level -#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable -#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering -#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level -#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable -#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering -#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level -#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable -#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering -#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level -#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG0 register. -// -//***************************************************************************** -#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG0_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG1 register. -// -//***************************************************************************** -#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG2 register. -// -//***************************************************************************** -#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG2_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG3 register. -// -//***************************************************************************** -#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG4 register. -// -//***************************************************************************** -#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG4_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG5 register. -// -//***************************************************************************** -#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG6 register. -// -//***************************************************************************** -#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG6_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG7 register. -// -//***************************************************************************** -#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_PP register. -// -//***************************************************************************** -#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence -#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CC register. -// -//***************************************************************************** -#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable - -#endif // __HW_HIBERNATE_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_i2c.h b/bsp/tm4c129x-dk/libraries/inc/hw_i2c.h deleted file mode 100644 index d9d00b5d57..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_i2c.h +++ /dev/null @@ -1,470 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following are defines for the I2C register offsets. -// -//***************************************************************************** -#define I2C_O_MSA 0x00000000 // I2C Master Slave Address -#define I2C_O_MCS 0x00000004 // I2C Master Control/Status -#define I2C_O_MDR 0x00000008 // I2C Master Data -#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period -#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask -#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status -#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt - // Status -#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear -#define I2C_O_MCR 0x00000020 // I2C Master Configuration -#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout - // Count -#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor -#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length -#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count -#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2 -#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address -#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status -#define I2C_O_SDR 0x00000808 // I2C Slave Data -#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask -#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status -#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt - // Status -#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear -#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2 -#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control -#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data -#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control -#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status -#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties -#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//***************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_RS 0x00000001 // Receive not send -#define I2C_MSA_SA_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//***************************************************************************** -#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BURST 0x00000040 // Burst Enable -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_QCMD 0x00000020 // Quick Command -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_HS 0x00000010 // High-Speed Enable -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_STOP 0x00000004 // Generate STOP -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_START 0x00000002 // Generate START -#define I2C_MCS_RUN 0x00000001 // I2C Master Enable -#define I2C_MCS_BUSY 0x00000001 // I2C Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//***************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data - // transferred during a transaction -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//***************************************************************************** -#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width -#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass -#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock -#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks -#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks -#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks -#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks -#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks -#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks -#define I2C_MTPR_HS 0x00000080 // High-Speed Enable -#define I2C_MTPR_TPR_M 0x0000007F // Timer Period -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//***************************************************************************** -#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt - // Mask -#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask -#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask -#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//***************************************************************************** -#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt - // Status -#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt - // Status -#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt - // Status -#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt - // Status -#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt - // Status -#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt - // Status -#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//***************************************************************************** -#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask -#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask -#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status -#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//***************************************************************************** -#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt - // Clear -#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt - // Clear -#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt - // Clear -#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt - // Clear -#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear -#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear -#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear -#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt - // Clear -#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear -#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//***************************************************************************** -#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//***************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//***************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBLEN register. -// -//***************************************************************************** -#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length -#define I2C_MBLEN_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBCNT register. -// -//***************************************************************************** -#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count -#define I2C_MBCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR2 register. -// -//***************************************************************************** -#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width -#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass -#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock -#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks -#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks -#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks -#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks -#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks -#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//***************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//***************************************************************************** -#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write -#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable -#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -#define I2C_SCSR_RREQ 0x00000001 // Receive Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//***************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask -#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt - // Status -#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt - // Status -#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt - // Status -#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt - // Status -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask -#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask -#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear -#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//***************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//***************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFODATA register. -// -//***************************************************************************** -#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte -#define I2C_FIFODATA_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOCTL register. -// -//***************************************************************************** -#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment -#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush -#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable -#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger -#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment -#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush -#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable -#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger -#define I2C_FIFOCTL_RXTRIG_S 16 -#define I2C_FIFOCTL_TXTRIG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOSTATUS -// register. -// -//***************************************************************************** -#define I2C_FIFOSTATUS_RXABVTRIG \ - 0x00040000 // RX FIFO Above Trigger Level -#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full -#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty -#define I2C_FIFOSTATUS_TXBLWTRIG \ - 0x00000004 // TX FIFO Below Trigger Level -#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full -#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//***************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PC register. -// -//***************************************************************************** -#define I2C_PC_HS 0x00000001 // High-Speed Capable - -#endif // __HW_I2C_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_ints.h b/bsp/tm4c129x-dk/libraries/inc/hw_ints.h deleted file mode 100644 index c75a84a6bb..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_ints.h +++ /dev/null @@ -1,491 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series -// MCUs. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following are defines for the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// TM4C123 Class Interrupts -// -//***************************************************************************** -#define INT_GPIOA_TM4C123 16 // GPIO Port A -#define INT_GPIOB_TM4C123 17 // GPIO Port B -#define INT_GPIOC_TM4C123 18 // GPIO Port C -#define INT_GPIOD_TM4C123 19 // GPIO Port D -#define INT_GPIOE_TM4C123 20 // GPIO Port E -#define INT_UART0_TM4C123 21 // UART0 -#define INT_UART1_TM4C123 22 // UART1 -#define INT_SSI0_TM4C123 23 // SSI0 -#define INT_I2C0_TM4C123 24 // I2C0 -#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault -#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 -#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 -#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 -#define INT_QEI0_TM4C123 29 // QEI0 -#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 -#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 -#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 -#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 -#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 -#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A -#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B -#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A -#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B -#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A -#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B -#define INT_COMP0_TM4C123 41 // Analog Comparator 0 -#define INT_COMP1_TM4C123 42 // Analog Comparator 1 -#define INT_COMP2_TM4C123 43 // Analog Comparator 2 -#define INT_SYSCTL_TM4C123 44 // System Control -#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM - // Control -#define INT_GPIOF_TM4C123 46 // GPIO Port F -#define INT_GPIOG_TM4C123 47 // GPIO Port G -#define INT_GPIOH_TM4C123 48 // GPIO Port H -#define INT_UART2_TM4C123 49 // UART2 -#define INT_SSI1_TM4C123 50 // SSI1 -#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A -#define INT_TIMER3B_TM4C123 52 // Timer 3B -#define INT_I2C1_TM4C123 53 // I2C1 -#define INT_QEI1_TM4C123 54 // QEI1 -#define INT_CAN0_TM4C123 55 // CAN0 -#define INT_CAN1_TM4C123 56 // CAN1 -#define INT_HIBERNATE_TM4C123 59 // Hibernation Module -#define INT_USB0_TM4C123 60 // USB -#define INT_PWM0_3_TM4C123 61 // PWM Generator 3 -#define INT_UDMA_TM4C123 62 // uDMA Software -#define INT_UDMAERR_TM4C123 63 // uDMA Error -#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 -#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 -#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 -#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 -#define INT_GPIOJ_TM4C123 70 // GPIO Port J -#define INT_GPIOK_TM4C123 71 // GPIO Port K -#define INT_GPIOL_TM4C123 72 // GPIO Port L -#define INT_SSI2_TM4C123 73 // SSI2 -#define INT_SSI3_TM4C123 74 // SSI3 -#define INT_UART3_TM4C123 75 // UART3 -#define INT_UART4_TM4C123 76 // UART4 -#define INT_UART5_TM4C123 77 // UART5 -#define INT_UART6_TM4C123 78 // UART6 -#define INT_UART7_TM4C123 79 // UART7 -#define INT_I2C2_TM4C123 84 // I2C2 -#define INT_I2C3_TM4C123 85 // I2C3 -#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A -#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B -#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A -#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B -#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A -#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B -#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A -#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B -#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A -#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B -#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A -#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B -#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A -#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B -#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A -#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B -#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) -#define INT_I2C4_TM4C123 125 // I2C4 -#define INT_I2C5_TM4C123 126 // I2C5 -#define INT_GPIOM_TM4C123 127 // GPIO Port M -#define INT_GPION_TM4C123 128 // GPIO Port N -#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) -#define INT_GPIOP1_TM4C123 133 // GPIO Port P1 -#define INT_GPIOP2_TM4C123 134 // GPIO Port P2 -#define INT_GPIOP3_TM4C123 135 // GPIO Port P3 -#define INT_GPIOP4_TM4C123 136 // GPIO Port P4 -#define INT_GPIOP5_TM4C123 137 // GPIO Port P5 -#define INT_GPIOP6_TM4C123 138 // GPIO Port P6 -#define INT_GPIOP7_TM4C123 139 // GPIO Port P7 -#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) -#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 -#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 -#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 -#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 -#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 -#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 -#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 -#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 -#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 -#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 -#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 -#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault -#define NUM_INTERRUPTS_TM4C123 155 - -//***************************************************************************** -// -// TM4C129 Class Interrupts -// -//***************************************************************************** -#define INT_GPIOA_TM4C129 16 // GPIO Port A -#define INT_GPIOB_TM4C129 17 // GPIO Port B -#define INT_GPIOC_TM4C129 18 // GPIO Port C -#define INT_GPIOD_TM4C129 19 // GPIO Port D -#define INT_GPIOE_TM4C129 20 // GPIO Port E -#define INT_UART0_TM4C129 21 // UART0 -#define INT_UART1_TM4C129 22 // UART1 -#define INT_SSI0_TM4C129 23 // SSI0 -#define INT_I2C0_TM4C129 24 // I2C0 -#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault -#define INT_PWM0_0_TM4C129 26 // PWM Generator 0 -#define INT_PWM0_1_TM4C129 27 // PWM Generator 1 -#define INT_PWM0_2_TM4C129 28 // PWM Generator 2 -#define INT_QEI0_TM4C129 29 // QEI0 -#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 -#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 -#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 -#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 -#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 -#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A -#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B -#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A -#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B -#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A -#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B -#define INT_COMP0_TM4C129 41 // Analog Comparator 0 -#define INT_COMP1_TM4C129 42 // Analog Comparator 1 -#define INT_COMP2_TM4C129 43 // Analog Comparator 2 -#define INT_SYSCTL_TM4C129 44 // System Control -#define INT_FLASH_TM4C129 45 // Flash Memory Control -#define INT_GPIOF_TM4C129 46 // GPIO Port F -#define INT_GPIOG_TM4C129 47 // GPIO Port G -#define INT_GPIOH_TM4C129 48 // GPIO Port H -#define INT_UART2_TM4C129 49 // UART2 -#define INT_SSI1_TM4C129 50 // SSI1 -#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A -#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B -#define INT_I2C1_TM4C129 53 // I2C1 -#define INT_CAN0_TM4C129 54 // CAN 0 -#define INT_CAN1_TM4C129 55 // CAN1 -#define INT_EMAC0_TM4C129 56 // Ethernet MAC -#define INT_HIBERNATE_TM4C129 57 // HIB -#define INT_USB0_TM4C129 58 // USB MAC -#define INT_PWM0_3_TM4C129 59 // PWM Generator 3 -#define INT_UDMA_TM4C129 60 // uDMA 0 Software -#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error -#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 -#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 -#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 -#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 -#define INT_EPI0_TM4C129 66 // EPI 0 -#define INT_GPIOJ_TM4C129 67 // GPIO Port J -#define INT_GPIOK_TM4C129 68 // GPIO Port K -#define INT_GPIOL_TM4C129 69 // GPIO Port L -#define INT_SSI2_TM4C129 70 // SSI 2 -#define INT_SSI3_TM4C129 71 // SSI 3 -#define INT_UART3_TM4C129 72 // UART 3 -#define INT_UART4_TM4C129 73 // UART 4 -#define INT_UART5_TM4C129 74 // UART 5 -#define INT_UART6_TM4C129 75 // UART 6 -#define INT_UART7_TM4C129 76 // UART 7 -#define INT_I2C2_TM4C129 77 // I2C 2 -#define INT_I2C3_TM4C129 78 // I2C 3 -#define INT_TIMER4A_TM4C129 79 // Timer 4A -#define INT_TIMER4B_TM4C129 80 // Timer 4B -#define INT_TIMER5A_TM4C129 81 // Timer 5A -#define INT_TIMER5B_TM4C129 82 // Timer 5B -#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception - // (imprecise) -#define INT_I2C4_TM4C129 86 // I2C 4 -#define INT_I2C5_TM4C129 87 // I2C 5 -#define INT_GPIOM_TM4C129 88 // GPIO Port M -#define INT_GPION_TM4C129 89 // GPIO Port N -#define INT_TAMPER0_TM4C129 91 // Tamper -#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) -#define INT_GPIOP1_TM4C129 93 // GPIO Port P1 -#define INT_GPIOP2_TM4C129 94 // GPIO Port P2 -#define INT_GPIOP3_TM4C129 95 // GPIO Port P3 -#define INT_GPIOP4_TM4C129 96 // GPIO Port P4 -#define INT_GPIOP5_TM4C129 97 // GPIO Port P5 -#define INT_GPIOP6_TM4C129 98 // GPIO Port P6 -#define INT_GPIOP7_TM4C129 99 // GPIO Port P7 -#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) -#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 -#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 -#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 -#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 -#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 -#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 -#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 -#define INT_GPIOR_TM4C129 108 // GPIO Port R -#define INT_GPIOS_TM4C129 109 // GPIO Port S -#define INT_SHA0_TM4C129 110 // SHA/MD5 -#define INT_AES0_TM4C129 111 // AES -#define INT_DES0_TM4C129 112 // DES -#define INT_LCD0_TM4C129 113 // LCD -#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A -#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B -#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A -#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B -#define INT_I2C6_TM4C129 118 // I2C 6 -#define INT_I2C7_TM4C129 119 // I2C 7 -#define INT_ONEWIRE0_TM4C129 121 // 1-Wire -#define INT_I2C8_TM4C129 125 // I2C 8 -#define INT_I2C9_TM4C129 126 // I2C 9 -#define INT_GPIOT_TM4C129 127 // GPIO T -#define NUM_INTERRUPTS_TM4C129 129 - -//***************************************************************************** -// -// TM4C123 Interrupt Class Definition -// -//***************************************************************************** -#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ - defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ - defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ - defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ - defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ - defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ - defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ - defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ - defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ - defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ - defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ - defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ - defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ - defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ - defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ - defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ - defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ - defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ - defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ - defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ - defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ - defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ - defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ - defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ - defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ - defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ - defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ - defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) -#define INT_RESOLVE(intname, class) intname##TM4C123 - -//***************************************************************************** -// -// TM4C129 Interrupt Class Definition -// -//***************************************************************************** -#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ - defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ - defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ - defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ - defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ - defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ - defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ - defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ - defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ - defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ - defined(PART_TM4C129XNCZAD) -#define INT_RESOLVE(intname, class) intname##TM4C129 -#else -#define INT_DEVICE_CLASS "UNKNOWN" -#endif - -//***************************************************************************** -// -// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. -// -//***************************************************************************** -#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) - -//***************************************************************************** -// -// The following are defines for the interrupt assignments. -// -//***************************************************************************** -#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) -#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) -#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) -#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) -#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) -#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) -#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) -#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) -#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) -#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) -#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) -#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) -#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) -#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) -#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) -#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) -#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) -#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) -#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) -#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) -#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) -#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) -#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) -#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) -#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) -#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) -#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) -#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) -#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) -#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) -#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) -#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) -#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) -#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) -#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) -#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) -#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) -#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) -#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) -#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) -#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) -#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) -#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) -#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) -#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) -#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) -#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) -#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) -#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) -#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) -#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) -#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) -#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) -#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) -#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) -#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) -#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) -#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) -#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) -#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) -#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) -#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) -#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) -#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) -#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) -#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) -#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) -#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) -#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) -#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) -#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) -#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) -#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) -#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) -#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) -#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) -#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) -#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) -#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) -#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) -#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) -#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) -#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) -#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) -#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) -#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) -#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) -#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) -#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) -#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) -#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) -#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) -#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) -#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) -#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) -#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) -#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) -#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) -#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) -#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) -#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) -#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) -#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) -#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) -#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) -#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) -#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) -#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) -#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) -#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) -#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) -#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) -#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) -#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) -#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) -#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) -#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) -#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) -#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) -#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) -#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) -#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) -#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) - -//***************************************************************************** -// -// The following are defines for the total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) - -//***************************************************************************** -// -// The following are defines for the total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_lcd.h b/bsp/tm4c129x-dk/libraries/inc/hw_lcd.h deleted file mode 100644 index bf0be0ae2f..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_lcd.h +++ /dev/null @@ -1,575 +0,0 @@ -//***************************************************************************** -// -// hw_lcd.h - Defines and macros used when accessing the LCD controller. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_LCD_H__ -#define __HW_LCD_H__ - -//***************************************************************************** -// -// The following are defines for the LCD register offsets. -// -//***************************************************************************** -#define LCD_O_PID 0x00000000 // LCD PID Register Format -#define LCD_O_CTL 0x00000004 // LCD Control -#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control -#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration -#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address -#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write - // Initiation -#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration -#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write - // Initiation -#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write - // Initiation -#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control -#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0 -#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1 -#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2 -#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1 -#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2 -#define LCD_O_DMACTL 0x00000040 // LCD DMA Control -#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base - // Address -#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling - // Address -#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base - // Address -#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling - // Address -#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration - // Register -#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set - // Register -#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear -#define LCD_O_IM 0x00000060 // LCD Interrupt Mask -#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear -#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable -#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_PID register. -// -//***************************************************************************** -#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number -#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number -#define LCD_PID_MAJOR_S 8 -#define LCD_PID_MINOR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_CTL register. -// -//***************************************************************************** -#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor -#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart -#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select -#define LCD_CTL_CLKDIV_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCTL register. -// -//***************************************************************************** -#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA - // Writes -#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable -#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1) - // Polarity Control -#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0 - // (E0) Polarity Control -#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction - // (DIR) Polarity Control -#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable - // (EN) Polarity Control -#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE) - // Polarity Control -#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select -#define LCD_LIDDCTL_MODE_SYNCM68 \ - 0x00000000 // Synchronous Motorola 6800 Mode -#define LCD_LIDDCTL_MODE_ASYNCM68 \ - 0x00000001 // Asynchronous Motorola 6800 Mode -#define LCD_LIDDCTL_MODE_SYNCM80 \ - 0x00000002 // Synchronous Intel 8080 mode -#define LCD_LIDDCTL_MODE_ASYNCM80 \ - 0x00000003 // Asynchronous Intel 8080 mode -#define LCD_LIDDCTL_MODE_ASYNCHIT \ - 0x00000004 // Asynchronous Hitachi mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG -// register. -// -//***************************************************************************** -#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles -#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration - // Cycles -#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles -#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles -#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles -#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles -#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number - // of LCDMCLK cycles (GAP +1) - // between the end of one CS0 - // (LCDAC) device access and the - // start of another CS0 (LCDAC) - // device access unless the two - // accesses are both reads -#define LCD_LIDDCS0CFG_WRSU_S 27 -#define LCD_LIDDCS0CFG_WRDUR_S 21 -#define LCD_LIDDCS0CFG_WRHOLD_S 17 -#define LCD_LIDDCS0CFG_RDSU_S 12 -#define LCD_LIDDCS0CFG_RDDUR_S 6 -#define LCD_LIDDCS0CFG_RDHOLD_S 2 -#define LCD_LIDDCS0CFG_GAP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR -// register. -// -//***************************************************************************** -#define LCD_LIDDCS0ADDR_CS0ADDR_M \ - 0x0000FFFF // LCD Address -#define LCD_LIDDCS0ADDR_CS0ADDR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA -// register. -// -//***************************************************************************** -#define LCD_LIDDCS0DATA_CS0DATA_M \ - 0x0000FFFF // LCD Data Read/Write -#define LCD_LIDDCS0DATA_CS0DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG -// register. -// -//***************************************************************************** -#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles -#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration - // Cycles -#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles -#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles -#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles -#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles -#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number - // of LCDMCLK cycles (GAP + 1) - // between the end of one CS1 - // (LCDAC) device access and the - // start of another CS0 (LCDAC) - // device access unless the two - // accesses are both reads -#define LCD_LIDDCS1CFG_WRSU_S 27 -#define LCD_LIDDCS1CFG_WRDUR_S 21 -#define LCD_LIDDCS1CFG_WRHOLD_S 17 -#define LCD_LIDDCS1CFG_RDSU_S 12 -#define LCD_LIDDCS1CFG_RDDUR_S 6 -#define LCD_LIDDCS1CFG_RDHOLD_S 2 -#define LCD_LIDDCS1CFG_GAP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR -// register. -// -//***************************************************************************** -#define LCD_LIDDCS1ADDR_CS1ADDR_M \ - 0x0000FFFF // LCD Address Bus -#define LCD_LIDDCS1ADDR_CS1ADDR_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA -// register. -// -//***************************************************************************** -#define LCD_LIDDCS1DATA_CS0DATA_M \ - 0x0000FFFF // LCD Data Read/Write Initiation -#define LCD_LIDDCS1DATA_CS0DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRCTL register. -// -//***************************************************************************** -#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing -#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode -#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select -#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal - // Mapping for Palettized - // Framebuffer -#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode -#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode -#define LCD_RASTRCTL_PALMODE_PALDAT \ - 0x00000000 // Palette and data loading, reset - // value -#define LCD_RASTRCTL_PALMODE_PAL \ - 0x00100000 // Palette loading only -#define LCD_RASTRCTL_PALMODE_DAT \ - 0x00200000 // Data loading only -#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay -#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit -#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select -#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT -#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome -#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster - // Operations -#define LCD_RASTRCTL_REQDLY_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRTIM0 -// register. -// -//***************************************************************************** -#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits -#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits -#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width - // Lowbits -#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4] -#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10] -#define LCD_RASTRTIM0_HBP_S 24 -#define LCD_RASTRTIM0_HFP_S 16 -#define LCD_RASTRTIM0_HSW_S 10 -#define LCD_RASTRTIM0_PPL_S 4 -#define LCD_RASTRTIM0_MSBPPL_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRTIM1 -// register. -// -//***************************************************************************** -#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch -#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch -#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse -#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel -#define LCD_RASTRTIM1_VBP_S 24 -#define LCD_RASTRTIM1_VFP_S 16 -#define LCD_RASTRTIM1_VSW_S 10 -#define LCD_RASTRTIM1_LPP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRTIM2 -// register. -// -//***************************************************************************** -#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync - // width field -#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel -#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control - // On/Off -#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall -#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable -#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock -#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync -#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync -#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per - // Interrupt -#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency -#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back - // porch field -#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front - // porch field -#define LCD_RASTRTIM2_HSW_S 27 -#define LCD_RASTRTIM2_MSBLPP_S 26 -#define LCD_RASTRTIM2_ACBI_S 16 -#define LCD_RASTRTIM2_ACBF_S 8 -#define LCD_RASTRTIM2_MSBHBP_S 4 -#define LCD_RASTRTIM2_MSBHFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRSUBP1 -// register. -// -//***************************************************************************** -#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable -#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal -#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold -#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0] -#define LCD_RASTRSUBP1_LPPT_S 16 -#define LCD_RASTRSUBP1_DPDLSB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RASTRSUBP2 -// register. -// -//***************************************************************************** -#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10 -#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16] -#define LCD_RASTRSUBP2_DPDMSB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMACTL register. -// -//***************************************************************************** -#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold -#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words -#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words -#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words -#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words -#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words -#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words -#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words -#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA - // transfers (all DMA transfers are - // 32 bits wide): -#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4 -#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8 -#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16 -#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane - // ordering of the data on the - // output of the DMA module -#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable -#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMABAFB0 register. -// -//***************************************************************************** -#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address - // pointer -#define LCD_DMABAFB0_FB0BA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMACAFB0 register. -// -//***************************************************************************** -#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address - // pointer -#define LCD_DMACAFB0_FB0CA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMABAFB1 register. -// -//***************************************************************************** -#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address - // pointer -#define LCD_DMABAFB1_FB1BA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_DMACAFB1 register. -// -//***************************************************************************** -#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address - // pointer -#define LCD_DMACAFB1_FB1CA_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_SYSCFG register. -// -//***************************************************************************** -#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode -#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local - // initiator is unconditionally - // placed in standby state. Backup - // mode, for debug only -#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator - // is unconditionally placed out of - // standby state. Backup mode, for - // debug only -#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local - // initiator standby status depends - // on local conditions, that is, - // the module's functional - // requirement from the initiator. - // IP module shall not generate - // (initiator-related) wakeup - // events -#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode -#define LCD_SYSCFG_IDLEMODE_FORCE \ - 0x00000000 // Force-idle mode: local target's - // idle state follows - // (acknowledges) the system's idle - // requests unconditionally, that - // is, regardless of the IP - // module's internal requirements. - // Backup mode, for debug only -#define LCD_SYSCFG_IDLEMODE_NONE \ - 0x00000004 // No-idle mode: local target never - // enters idle state. Backup mode, - // for debug only -#define LCD_SYSCFG_IDLEMODE_SMART \ - 0x00000008 // Smart-idle mode: local target's - // idle state eventually follows - // (acknowledges) the system's idle - // requests, depending on the IP - // module's internal requirements. - // IP module shall not generate - // (IRQ- or DMA-requestrelated) - // wakeup events - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_RISSET register. -// -//***************************************************************************** -#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt - // Status and Set -#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt - // Status and Set -#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt - // Status and Set -#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt - // Status and Set -#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt - // Status and Set -#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw - // Interrupt Status and Set -#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt -#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) Raw - // Interrupt Status and Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_MISCLR register. -// -//***************************************************************************** -#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled - // Interrupt and Clear -#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt - // and Clear -#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled - // Interrupt and Clear -#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled - // Interrupt and Clear -#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt - // and Clear -#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost - // Enabled Interrupt and Clear -#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt -#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) - // Enabled Interrupt and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_IM register. -// -//***************************************************************************** -#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt - // Enable Set -#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt - // Enable Set -#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt - // Enable Set -#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt - // Enable Set -#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable - // Set -#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost - // Interrupt Enable Set -#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt - // Enable Set -#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) - // Interrupt Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_IENC register. -// -//***************************************************************************** -#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt - // Enable Clear -#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt - // Enable Clear -#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt - // Enable Clear -#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt - // Enable Clear -#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable - // Clear -#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost - // Interrupt Enable Clear -#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt - // Enable Clear -#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done - // (shared, depends on whether - // Raster or LIDD mode enabled) - // Interrupt Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_CLKEN register. -// -//***************************************************************************** -#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable -#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable -#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the LCD_O_CLKRESET register. -// -//***************************************************************************** -#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire - // LCD module -#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA - // submodule -#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD - // submodule (character displays) -#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core, - // which encompasses the Raster - // Active Matrix and Passive Matrix - // logic - -#endif // __HW_LCD_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_memmap.h b/bsp/tm4c129x-dk/libraries/inc/hw_memmap.h deleted file mode 100644 index 87033ab823..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_memmap.h +++ /dev/null @@ -1,151 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of the device. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following are defines for the base address of the memories and -// peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG0_BASE 0x40000000 // Watchdog0 -#define WATCHDOG1_BASE 0x40001000 // Watchdog1 -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI0_BASE 0x40008000 // SSI0 -#define SSI1_BASE 0x40009000 // SSI1 -#define SSI2_BASE 0x4000A000 // SSI2 -#define SSI3_BASE 0x4000B000 // SSI3 -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define UART2_BASE 0x4000E000 // UART2 -#define UART3_BASE 0x4000F000 // UART3 -#define UART4_BASE 0x40010000 // UART4 -#define UART5_BASE 0x40011000 // UART5 -#define UART6_BASE 0x40012000 // UART6 -#define UART7_BASE 0x40013000 // UART7 -#define I2C0_BASE 0x40020000 // I2C0 -#define I2C1_BASE 0x40021000 // I2C1 -#define I2C2_BASE 0x40022000 // I2C2 -#define I2C3_BASE 0x40023000 // I2C3 -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F -#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G -#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H -#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) -#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) -#define QEI0_BASE 0x4002C000 // QEI0 -#define QEI1_BASE 0x4002D000 // QEI1 -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define TIMER3_BASE 0x40033000 // Timer3 -#define TIMER4_BASE 0x40034000 // Timer4 -#define TIMER5_BASE 0x40035000 // Timer5 -#define WTIMER0_BASE 0x40036000 // Wide Timer0 -#define WTIMER1_BASE 0x40037000 // Wide Timer1 -#define ADC0_BASE 0x40038000 // ADC0 -#define ADC1_BASE 0x40039000 // ADC1 -#define COMP_BASE 0x4003C000 // Analog comparators -#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J -#define CAN0_BASE 0x40040000 // CAN0 -#define CAN1_BASE 0x40041000 // CAN1 -#define WTIMER2_BASE 0x4004C000 // Wide Timer2 -#define WTIMER3_BASE 0x4004D000 // Wide Timer3 -#define WTIMER4_BASE 0x4004E000 // Wide Timer4 -#define WTIMER5_BASE 0x4004F000 // Wide Timer5 -#define USB0_BASE 0x40050000 // USB 0 Controller -#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) -#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) -#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) -#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) -#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) -#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) -#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) -#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) -#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) -#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K -#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L -#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M -#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N -#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P -#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q -#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs - // (GPIOs) -#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs - // (GPIOs) -#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs - // (GPIOs) -#define EEPROM_BASE 0x400AF000 // EEPROM memory -#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module -#define I2C8_BASE 0x400B8000 // I2C8 -#define I2C9_BASE 0x400B9000 // I2C9 -#define I2C4_BASE 0x400C0000 // I2C4 -#define I2C5_BASE 0x400C1000 // I2C5 -#define I2C6_BASE 0x400C2000 // I2C6 -#define I2C7_BASE 0x400C3000 // I2C7 -#define EPI0_BASE 0x400D0000 // EPI0 -#define TIMER6_BASE 0x400E0000 // General-Purpose Timers -#define TIMER7_BASE 0x400E1000 // General-Purpose Timers -#define EMAC0_BASE 0x400EC000 // Ethernet Controller -#define SYSEXC_BASE 0x400F9000 // System Exception Module -#define HIB_BASE 0x400FC000 // Hibernation Module -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define UDMA_BASE 0x400FF000 // uDMA Controller -#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC) -#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator -#define AES_BASE 0x44036000 // Advance Encryption - // Hardware-Accelerated Module -#define DES_BASE 0x44038000 // Data Encryption Standard - // Accelerator (DES) -#define LCD0_BASE 0x44050000 // LCD Controller -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_nvic.h b/bsp/tm4c129x-dk/libraries/inc/hw_nvic.h deleted file mode 100644 index be8becf0fb..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_nvic.h +++ /dev/null @@ -1,1414 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following are defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status - // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable -#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable -#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable -#define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable -#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable -#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable -#define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending -#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending -#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending -#define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending -#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending -#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending -#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit -#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit -#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit -#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority -#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority -#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority -#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority -#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority -#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority -#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority -#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority -#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority -#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority -#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority -#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority -#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority -#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority -#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority -#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority -#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority -#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority -#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority -#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority -#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset - // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size - // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size - // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size - // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt -#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control -#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address -#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating - // Point -#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN4 register. -// -//***************************************************************************** -#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS4 register. -// -//***************************************************************************** -#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND4 register. -// -//***************************************************************************** -#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND4 register. -// -//***************************************************************************** -#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE4 register. -// -//***************************************************************************** -#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI29 register. -// -//***************************************************************************** -#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask -#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask -#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask -#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask -#define NVIC_PRI29_INTD_S 29 -#define NVIC_PRI29_INTC_S 21 -#define NVIC_PRI29_INTB_S 13 -#define NVIC_PRI29_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI30 register. -// -//***************************************************************************** -#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask -#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask -#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask -#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask -#define NVIC_PRI30_INTD_S 29 -#define NVIC_PRI30_INTC_S 21 -#define NVIC_PRI30_INTB_S 13 -#define NVIC_PRI30_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI31 register. -// -//***************************************************************************** -#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask -#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask -#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask -#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask -#define NVIC_PRI31_INTD_S 29 -#define NVIC_PRI31_INTC_S 21 -#define NVIC_PRI31_INTB_S 13 -#define NVIC_PRI31_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI32 register. -// -//***************************************************************************** -#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask -#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask -#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask -#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask -#define NVIC_PRI32_INTD_S 29 -#define NVIC_PRI32_INTC_S 21 -#define NVIC_PRI32_INTB_S 13 -#define NVIC_PRI32_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI33 register. -// -//***************************************************************************** -#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt - // [4n+3] -#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt - // [4n+2] -#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt - // [4n+1] -#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt - // [4n] -#define NVIC_PRI33_INTD_S 29 -#define NVIC_PRI33_INTC_S 21 -#define NVIC_PRI33_INTB_S 13 -#define NVIC_PRI33_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI34 register. -// -//***************************************************************************** -#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt - // [4n+3] -#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt - // [4n+2] -#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt - // [4n+1] -#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt - // [4n] -#define NVIC_PRI34_INTD_S 29 -#define NVIC_PRI34_INTC_S 21 -#define NVIC_PRI34_INTB_S 13 -#define NVIC_PRI34_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPAC register. -// -//***************************************************************************** -#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only -#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access -#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only -#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access -#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none -#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only -#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw -#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none -#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable -#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable -#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable -#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable -#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable -#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable -#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable -#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes -#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes -#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes -#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes -#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes -#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes -#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes -#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes -#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes -#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes -#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes -#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes -#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes -#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes -#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes -#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes -#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes -#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes -#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes -#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes -#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes -#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes -#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes -#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes -#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes -#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes -#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes -#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCC register. -// -//***************************************************************************** -#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation - // Enable -#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable -#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready -#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready -#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready -#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready -#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode -#define NVIC_FPCC_USER 0x00000002 // User Privilege Level -#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCA register. -// -//***************************************************************************** -#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address -#define NVIC_FPCA_ADDRESS_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPDSC register. -// -//***************************************************************************** -#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default -#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default -#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default -#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default -#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode -#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) - // mode -#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity - // (RM) mode -#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode - -#endif // __HW_NVIC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_onewire.h b/bsp/tm4c129x-dk/libraries/inc/hw_onewire.h deleted file mode 100644 index bf810b7ce9..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_onewire.h +++ /dev/null @@ -1,223 +0,0 @@ -//***************************************************************************** -// -// hw_onewire.h - Macros used when accessing the One wire hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_ONEWIRE_H__ -#define __HW_ONEWIRE_H__ - -//***************************************************************************** -// -// The following are defines for the One wire register offsets. -// -//***************************************************************************** -#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status -#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override -#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write -#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read -#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask -#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status -#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status -#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear -#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control -#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_CS register. -// -//***************************************************************************** -#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable -#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable -#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size -#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte) -#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit -#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits -#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits -#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits -#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits -#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits -#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits -#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status -#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status -#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status -#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable -#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable -#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable -#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size -#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request -#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation -#define ONEWIRE_CS_OP_RD 0x00000002 // Read -#define ONEWIRE_CS_OP_WR 0x00000004 // Write -#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read -#define ONEWIRE_CS_RST 0x00000001 // Reset Request -#define ONEWIRE_CS_SZ_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_TIM register. -// -//***************************************************************************** -#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing -#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing -#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time -#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time -#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample -#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period -#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time -#define ONEWIRE_TIM_W1TIM_S 28 -#define ONEWIRE_TIM_W0TIM_S 23 -#define ONEWIRE_TIM_W0REST_S 19 -#define ONEWIRE_TIM_W1SAM_S 15 -#define ONEWIRE_TIM_ATRSAM_S 11 -#define ONEWIRE_TIM_ATRTIM_S 6 -#define ONEWIRE_TIM_RSTTIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_DATW register. -// -//***************************************************************************** -#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte -#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte -#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte -#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte -#define ONEWIRE_DATW_B3_S 24 -#define ONEWIRE_DATW_B2_S 16 -#define ONEWIRE_DATW_B1_S 8 -#define ONEWIRE_DATW_B0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_DATR register. -// -//***************************************************************************** -#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte -#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte -#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte -#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte -#define ONEWIRE_DATR_B3_S 24 -#define ONEWIRE_DATR_B2_S 16 -#define ONEWIRE_DATR_B1_S 8 -#define ONEWIRE_DATR_B0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_IM register. -// -//***************************************************************************** -#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask -#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask -#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt - // Mask -#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt - // Mask -#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_RIS register. -// -//***************************************************************************** -#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status -#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt - // Status -#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt - // Status -#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt - // Status -#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_MIS register. -// -//***************************************************************************** -#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status -#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt - // Status -#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked - // Interrupt Status -#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked - // Interrupt Status -#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_ICR register. -// -//***************************************************************************** -#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear -#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear -#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt - // Clear -#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt - // Clear -#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_DMA register. -// -//***************************************************************************** -#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable -#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation -#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled -#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire - // requests uDMA to read - // ONEWIREDATR register after each - // read transaction -#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire - // requests uDMA to load whenever - // the ONEWIREDATW register is - // empty -#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial - // read occurs and subsequent reads - // start after uDMA has read the - // ONEWIREDATR register -#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the ONEWIRE_O_PP register. -// -//***************************************************************************** -#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present -#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count -#define ONEWIRE_PP_CNT_S 0 - -#endif // __HW_ONEWIRE_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_pwm.h b/bsp/tm4c129x-dk/libraries/inc/hw_pwm.h deleted file mode 100644 index 2167aad93a..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_pwm.h +++ /dev/null @@ -1,1885 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// The following are defines for the PWM register offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion -#define PWM_O_FAULT 0x00000010 // PWM Output Fault -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable -#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear -#define PWM_O_STATUS 0x00000020 // PWM Status -#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value -#define PWM_O_ENUPD 0x00000028 // PWM Enable Update -#define PWM_O_0_CTL 0x00000040 // PWM0 Control -#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger - // Enable -#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status -#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear -#define PWM_O_0_LOAD 0x00000050 // PWM0 Load -#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter -#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A -#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B -#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control -#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control -#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control -#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay -#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band - // Falling-Edge-Delay -#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 -#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 -#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period -#define PWM_O_1_CTL 0x00000080 // PWM1 Control -#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger - // Enable -#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status -#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear -#define PWM_O_1_LOAD 0x00000090 // PWM1 Load -#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter -#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A -#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B -#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control -#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control -#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control -#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay -#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band - // Falling-Edge-Delay -#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 -#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 -#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period -#define PWM_O_2_CTL 0x000000C0 // PWM2 Control -#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger - // Enable -#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status -#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear -#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load -#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter -#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A -#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B -#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control -#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control -#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control -#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay -#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band - // Falling-Edge-Delay -#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 -#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 -#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period -#define PWM_O_3_CTL 0x00000100 // PWM3 Control -#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger - // Enable -#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status -#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear -#define PWM_O_3_LOAD 0x00000110 // PWM3 Load -#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter -#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A -#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B -#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control -#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control -#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control -#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay -#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band - // Falling-Edge-Delay -#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 -#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 -#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period -#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense -#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 -#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 -#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense -#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 -#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 -#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense -#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 -#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 -#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense -#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 -#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 -#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties -#define PWM_O_CC 0x00000FC8 // PWM Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CTL register. -// -//***************************************************************************** -#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 -#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_SYNC register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter -#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENABLE register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable -#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable -#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable -#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable -#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable -#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable -#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INVERT register. -// -//***************************************************************************** -#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal -#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal -#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal -#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal -#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal -#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal -#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal -#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULT register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault -#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault -#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault -#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault -#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault -#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault -#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault -#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INTEN register. -// -//***************************************************************************** -#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 -#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 -#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 -#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 -#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable -#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_RIS register. -// -//***************************************************************************** -#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 -#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 -#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 -#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 -#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted -#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ISC register. -// -//***************************************************************************** -#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted -#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted -#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted -#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted -#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status -#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_STATUS register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status -#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status -#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status -#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULTVAL register. -// -//***************************************************************************** -#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value -#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value -#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value -#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value -#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value -#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value -#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value -#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENUPD register. -// -//***************************************************************************** -#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode -#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized -#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized -#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode -#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized -#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized -#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode -#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized -#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized -#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode -#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized -#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized -#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode -#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized -#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized -#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode -#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized -#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized -#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode -#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized -#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized -#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode -#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized -#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CTL register. -// -//***************************************************************************** -#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_0_CTL_MODE 0x00000002 // Counter Mode -#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_INTEN register. -// -//***************************************************************************** -#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_RIS register. -// -//***************************************************************************** -#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_ISC register. -// -//***************************************************************************** -#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_LOAD register. -// -//***************************************************************************** -#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_0_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_COUNT register. -// -//***************************************************************************** -#define PWM_0_COUNT_M 0x0000FFFF // Counter Value -#define PWM_0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPA register. -// -//***************************************************************************** -#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_0_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPB register. -// -//***************************************************************************** -#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_0_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENA register. -// -//***************************************************************************** -#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_0_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_0_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_0_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_0_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENB register. -// -//***************************************************************************** -#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_0_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_0_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_0_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_0_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBCTL register. -// -//***************************************************************************** -#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBRISE register. -// -//***************************************************************************** -#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_0_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBFALL register. -// -//***************************************************************************** -#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_0_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_0_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CTL register. -// -//***************************************************************************** -#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_1_CTL_MODE 0x00000002 // Counter Mode -#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_INTEN register. -// -//***************************************************************************** -#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_RIS register. -// -//***************************************************************************** -#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_ISC register. -// -//***************************************************************************** -#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_LOAD register. -// -//***************************************************************************** -#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_1_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_COUNT register. -// -//***************************************************************************** -#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_1_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPA register. -// -//***************************************************************************** -#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_1_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPB register. -// -//***************************************************************************** -#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_1_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENA register. -// -//***************************************************************************** -#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_1_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_1_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_1_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_1_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENB register. -// -//***************************************************************************** -#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_1_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_1_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_1_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_1_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBCTL register. -// -//***************************************************************************** -#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBRISE register. -// -//***************************************************************************** -#define PWM_1_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_1_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBFALL register. -// -//***************************************************************************** -#define PWM_1_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_1_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_1_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CTL register. -// -//***************************************************************************** -#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_2_CTL_MODE 0x00000002 // Counter Mode -#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_INTEN register. -// -//***************************************************************************** -#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_RIS register. -// -//***************************************************************************** -#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_ISC register. -// -//***************************************************************************** -#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_LOAD register. -// -//***************************************************************************** -#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_2_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_COUNT register. -// -//***************************************************************************** -#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_2_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPA register. -// -//***************************************************************************** -#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_2_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPB register. -// -//***************************************************************************** -#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_2_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENA register. -// -//***************************************************************************** -#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_2_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_2_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_2_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_2_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENB register. -// -//***************************************************************************** -#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_2_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_2_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_2_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_2_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBCTL register. -// -//***************************************************************************** -#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBRISE register. -// -//***************************************************************************** -#define PWM_2_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_2_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBFALL register. -// -//***************************************************************************** -#define PWM_2_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_2_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_2_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CTL register. -// -//***************************************************************************** -#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_3_CTL_MODE 0x00000002 // Counter Mode -#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_INTEN register. -// -//***************************************************************************** -#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_RIS register. -// -//***************************************************************************** -#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_ISC register. -// -//***************************************************************************** -#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_LOAD register. -// -//***************************************************************************** -#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_3_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_COUNT register. -// -//***************************************************************************** -#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_3_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPA register. -// -//***************************************************************************** -#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_3_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPB register. -// -//***************************************************************************** -#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_3_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENA register. -// -//***************************************************************************** -#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_3_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_3_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_3_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_3_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENB register. -// -//***************************************************************************** -#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_3_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_3_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_3_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_3_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBCTL register. -// -//***************************************************************************** -#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBRISE register. -// -//***************************************************************************** -#define PWM_3_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_3_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBFALL register. -// -//***************************************************************************** -#define PWM_3_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_3_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_3_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. -// -//***************************************************************************** -#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. -// -//***************************************************************************** -#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. -// -//***************************************************************************** -#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. -// -//***************************************************************************** -#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_PP register. -// -//***************************************************************************** -#define PWM_PP_GCNT_M 0x0000000F // Generators -#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) -#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization -#define PWM_PP_EFAULT 0x00000200 // Extended Fault -#define PWM_PP_ONE 0x00000400 // One-Shot Mode -#define PWM_PP_GCNT_S 0 -#define PWM_PP_FCNT_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CC register. -// -//***************************************************************************** -#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor -#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider -#define PWM_CC_PWMDIV_2 0x00000000 // /2 -#define PWM_CC_PWMDIV_4 0x00000001 // /4 -#define PWM_CC_PWMDIV_8 0x00000002 // /8 -#define PWM_CC_PWMDIV_16 0x00000003 // /16 -#define PWM_CC_PWMDIV_32 0x00000004 // /32 -#define PWM_CC_PWMDIV_64 0x00000005 // /64 - -//***************************************************************************** -// -// The following are defines for the PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg -#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition -#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition -#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base -#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CTL register. -// -//***************************************************************************** -#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_X_CTL_MODE 0x00000002 // Counter Mode -#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_INTEN register. -// -//***************************************************************************** -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_RIS register. -// -//***************************************************************************** -#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_ISC register. -// -//***************************************************************************** -#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_LOAD register. -// -//***************************************************************************** -#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_X_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_COUNT register. -// -//***************************************************************************** -#define PWM_X_COUNT_M 0x0000FFFF // Counter Value -#define PWM_X_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPA register. -// -//***************************************************************************** -#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_X_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_CMPB register. -// -//***************************************************************************** -#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_X_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENA register. -// -//***************************************************************************** -#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_X_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_X_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_X_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_X_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_GENB register. -// -//***************************************************************************** -#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_X_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_X_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_X_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_X_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_X_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_X_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_X_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_X_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBCTL register. -// -//***************************************************************************** -#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBRISE register. -// -//***************************************************************************** -#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_X_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_DBFALL register. -// -//***************************************************************************** -#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_X_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_X_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the PWM Generator extended offsets. -// -//***************************************************************************** -#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense -#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status -#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status -#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base -#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base -#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base -#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. -// -//***************************************************************************** -#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -#endif // __HW_PWM_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_qei.h b/bsp/tm4c129x-dk/libraries/inc/hw_qei.h deleted file mode 100644 index a86f5259bd..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_qei.h +++ /dev/null @@ -1,178 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following are defines for the QEI register offsets. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // QEI Control -#define QEI_O_STAT 0x00000004 // QEI Status -#define QEI_O_POS 0x00000008 // QEI Position -#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position -#define QEI_O_LOAD 0x00000010 // QEI Timer Load -#define QEI_O_TIME 0x00000014 // QEI Timer -#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter -#define QEI_O_SPEED 0x0000001C // QEI Velocity -#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable -#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status -#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_CTL register. -// -//***************************************************************************** -#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count -#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter -#define QEI_CTL_STALLEN 0x00001000 // Stall QEI -#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse -#define QEI_CTL_INVB 0x00000400 // Invert PhB -#define QEI_CTL_INVA 0x00000200 // Invert PhA -#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity -#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 -#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 -#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 -#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 -#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 -#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 -#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 -#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 -#define QEI_CTL_VELEN 0x00000020 // Capture Velocity -#define QEI_CTL_RESMODE 0x00000010 // Reset Mode -#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode -#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode -#define QEI_CTL_SWAP 0x00000002 // Swap Signals -#define QEI_CTL_ENABLE 0x00000001 // Enable QEI -#define QEI_CTL_FILTCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation -#define QEI_STAT_ERROR 0x00000001 // Error Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator - // Value -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator - // Value -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Velocity -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable -#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt - // Enable -#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable -#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected -#define QEI_RIS_DIR 0x00000004 // Direction Change Detected -#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired -#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_ISC register. -// -//***************************************************************************** -#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt -#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt -#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt -#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt - -#endif // __HW_QEI_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_shamd5.h b/bsp/tm4c129x-dk/libraries/inc/hw_shamd5.h deleted file mode 100644 index d34c76092c..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_shamd5.h +++ /dev/null @@ -1,548 +0,0 @@ -//***************************************************************************** -// -// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. -// -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SHAMD5_H__ -#define __HW_SHAMD5_H__ - -//***************************************************************************** -// -// The following are defines for the SHA/MD5 register offsets. -// -//***************************************************************************** -#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A -#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B -#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C -#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D -#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E -#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F -#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G -#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H -#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A -#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B -#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C -#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D -#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E -#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F -#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G -#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H -#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count -#define SHAMD5_O_MODE 0x00000044 // SHA Mode -#define SHAMD5_O_LENGTH 0x00000048 // SHA Length -#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input -#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input -#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input -#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input -#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input -#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input -#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input -#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input -#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input -#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input -#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input -#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input -#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input -#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input -#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input -#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input -#define SHAMD5_O_REVISION 0x00000100 // SHA Revision -#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration -#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status -#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status -#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable -#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask -#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status -#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status -#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_A_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_B_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_C_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_D_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_E_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_F_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_G_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H -// register. -// -//***************************************************************************** -#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_ODIGEST_H_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_A_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_B_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_C_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_D_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_E_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_F_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_G_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H -// register. -// -//***************************************************************************** -#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_IDIGEST_H_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT -// register. -// -//***************************************************************************** -#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count -#define SHAMD5_DIGEST_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_MODE register. -// -//***************************************************************************** -#define SHAMD5_MODE_HMAC_OUTER_HASH \ - 0x00000080 // HMAC Outer Hash Processing - // Enable -#define SHAMD5_MODE_HMAC_KEY_PROC \ - 0x00000020 // HMAC Key Processing Enable -#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the - // Hash/HMAC will be 'closed' at - // the end of the block, as per - // MD5/SHA-1/SHA-2 specification -#define SHAMD5_MODE_ALGO_CONSTANT \ - 0x00000008 // The initial digest register will - // be overwritten with the - // algorithm constants for the - // selected algorithm when hashing - // and the initial digest count - // register will be reset to 0 -#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm -#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5 -#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1 -#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224 -#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_LENGTH -// register. -// -//***************************************************************************** -#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte - // Count -#define SHAMD5_LENGTH_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_0_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_1_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_2_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_3_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_4_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_5_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_6_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_7_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_8_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_9_IN_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_10_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_10_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_11_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_11_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_12_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_12_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_13_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_13_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_14_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_14_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN -// register. -// -//***************************************************************************** -#define SHAMD5_DATA_15_IN_DATA_M \ - 0xFFFFFFFF // Digest/Key Data -#define SHAMD5_DATA_15_IN_DATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_REVISION -// register. -// -//***************************************************************************** -#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number -#define SHAMD5_REVISION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG -// register. -// -//***************************************************************************** -#define SHAMD5_SYSCONFIG_SADVANCED \ - 0x00000080 // Advanced Mode Enable -#define SHAMD5_SYSCONFIG_SIDLE_M \ - 0x00000030 // Sidle mode -#define SHAMD5_SYSCONFIG_SIDLE_FORCE \ - 0x00000000 // Force-idle mode -#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable -#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable -#define SHAMD5_SYSCONFIG_SOFTRESET \ - 0x00000002 // Soft reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS -// register. -// -//***************************************************************************** -#define SHAMD5_SYSSTATUS_RESETDONE \ - 0x00000001 // Reset done status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS -// register. -// -//***************************************************************************** -#define SHAMD5_IRQSTATUS_CONTEXT_READY \ - 0x00000008 // Context Ready Status -#define SHAMD5_IRQSTATUS_INPUT_READY \ - 0x00000002 // Input Ready Status -#define SHAMD5_IRQSTATUS_OUTPUT_READY \ - 0x00000001 // Output Ready Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE -// register. -// -//***************************************************************************** -#define SHAMD5_IRQENABLE_CONTEXT_READY \ - 0x00000008 // Mask for context ready interrupt -#define SHAMD5_IRQENABLE_INPUT_READY \ - 0x00000002 // Mask for input ready interrupt -#define SHAMD5_IRQENABLE_OUTPUT_READY \ - 0x00000001 // Mask for output ready interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMAIM register. -// -//***************************************************************************** -#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt - // Mask -#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask -#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMARIS -// register. -// -//***************************************************************************** -#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw - // Interrupt Status -#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt - // Status -#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMAMIS -// register. -// -//***************************************************************************** -#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked - // Interrupt Status -#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked - // Interrupt Status -#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DMAIC register. -// -//***************************************************************************** -#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked - // Interrupt Status -#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear -#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw - // Interrupt Status - -#endif // __HW_SHAMD5_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_ssi.h b/bsp/tm4c129x-dk/libraries/inc/hw_ssi.h deleted file mode 100644 index 36a92cf1e4..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_ssi.h +++ /dev/null @@ -1,237 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following are defines for the SSI register offsets. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // SSI Control 0 -#define SSI_O_CR1 0x00000004 // SSI Control 1 -#define SSI_O_DR 0x00000008 // SSI Data -#define SSI_O_SR 0x0000000C // SSI Status -#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale -#define SSI_O_IM 0x00000014 // SSI Interrupt Mask -#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status -#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status -#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear -#define SSI_O_DMACTL 0x00000024 // SSI DMA Control -#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties -#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR0 register. -// -//***************************************************************************** -#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate -#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase -#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity -#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select -#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format -#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format -#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format -#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select -#define SSI_CR0_DSS_4 0x00000003 // 4-bit data -#define SSI_CR0_DSS_5 0x00000004 // 5-bit data -#define SSI_CR0_DSS_6 0x00000005 // 6-bit data -#define SSI_CR0_DSS_7 0x00000006 // 7-bit data -#define SSI_CR0_DSS_8 0x00000007 // 8-bit data -#define SSI_CR0_DSS_9 0x00000008 // 9-bit data -#define SSI_CR0_DSS_10 0x00000009 // 10-bit data -#define SSI_CR0_DSS_11 0x0000000A // 11-bit data -#define SSI_CR0_DSS_12 0x0000000B // 12-bit data -#define SSI_CR0_DSS_13 0x0000000C // 13-bit data -#define SSI_CR0_DSS_14 0x0000000D // 14-bit data -#define SSI_CR0_DSS_15 0x0000000E // 15-bit data -#define SSI_CR0_DSS_16 0x0000000F // 16-bit data -#define SSI_CR0_SCR_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR1 register. -// -//***************************************************************************** -#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) -#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame -#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable -#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation -#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode -#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode -#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode -#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit - // packet size -#define SSI_CR1_EOT 0x00000010 // End of Transmission -#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select -#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port - // Enable -#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DR register. -// -//***************************************************************************** -#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_SR register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI Busy Bit -#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full -#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty -#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full -#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CPSR register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_IM register. -// -//***************************************************************************** -#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask -#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask -#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask -#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask -#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask -#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt - // Mask -#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_RIS register. -// -//***************************************************************************** -#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt - // Status -#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt - // Status -#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt - // Status -#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt - // Status -#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt - // Status -#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw - // Interrupt Status -#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_MIS register. -// -//***************************************************************************** -#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt - // Status -#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked - // Interrupt Status -#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt - // Status -#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked - // Interrupt Status -#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked - // Interrupt Status -#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked - // Interrupt Status -#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_ICR register. -// -//***************************************************************************** -#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear -#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear -#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear -#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt - // Clear -#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DMACTL register. -// -//***************************************************************************** -#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_PP register. -// -//***************************************************************************** -#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability -#define SSI_PP_MODE_M 0x00000006 // Mode of Operation -#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode - // and Bi-SSI mode enabled -#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, - // Bi-SSI and Quad-SSI mode enabled -#define SSI_PP_HSCLK 0x00000001 // High Speed Capability - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CC register. -// -//***************************************************************************** -#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source -#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock - // source and divisor factor) -#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC - -#endif // __HW_SSI_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_sysctl.h b/bsp/tm4c129x-dk/libraries/inc/hw_sysctl.h deleted file mode 100644 index cab5049da5..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_sysctl.h +++ /dev/null @@ -1,3749 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following are defines for the System Control register addresses. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400FE000 // Device Identification 0 -#define SYSCTL_DID1 0x400FE004 // Device Identification 1 -#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0 -#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1 -#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2 -#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3 -#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4 -#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5 -#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6 -#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7 -#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 -#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control -#define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control -#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0 -#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1 -#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2 -#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status -#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control -#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and - // Clear -#define SYSCTL_RESC 0x400FE05C // Reset Cause -#define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause -#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration -#define SYSCTL_NMIC 0x400FE064 // NMI Cause Register -#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus - // Control -#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 -#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control -#define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration - // Register -#define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register - // 0 for Main Flash and EEPROM -#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control - // Register 0 -#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control - // Register 1 -#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control - // Register 2 -#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control - // Register 0 -#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control - // Register 1 -#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control - // Register 2 -#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating - // Control Register 0 -#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating - // Control Register 1 -#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating - // Control Register 2 -#define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration -#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration -#define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration - // Register -#define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock - // Configuration -#define SYSCTL_SYSPROP 0x400FE14C // System Properties -#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator - // Calibration -#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator - // Statistics -#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 -#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 -#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status -#define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration -#define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration -#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 -#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information -#define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control -#define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control -#define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register -#define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request -#define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status -#define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control -#define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status -#define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power - // Control -#define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control -#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral - // Present -#define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer - // Peripheral Present -#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output - // Peripheral Present -#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access - // Peripheral Present -#define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present -#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present -#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous - // Receiver/Transmitter Peripheral - // Present -#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface - // Peripheral Present -#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit - // Peripheral Present -#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral - // Present -#define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present -#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network - // Peripheral Present -#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter - // Peripheral Present -#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral - // Present -#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral - // Present -#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface - // Peripheral Present -#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface - // Peripheral Present -#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control - // Interface Peripheral Present -#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present -#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present -#define SYSCTL_PPWTIMER 0x400FE35C // 32/64-Bit Wide General-Purpose - // Timer Peripheral Present -#define SYSCTL_PPRTS 0x400FE370 // Remote Temperature Sensor - // Peripheral Present -#define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules - // Peripheral Present -#define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present -#define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present -#define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present -#define SYSCTL_PPHIM 0x400FE3A4 // Human Interface Master - // Peripheral Present -#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset -#define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer - // Software Reset -#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output - // Software Reset -#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access - // Software Reset -#define SYSCTL_SREPI 0x400FE510 // EPI Software Reset -#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset -#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous - // Receiver/Transmitter Software - // Reset -#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface - // Software Reset -#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit - // Software Reset -#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software - // Reset -#define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset -#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software - // Reset -#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter - // Software Reset -#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset -#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software - // Reset -#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface - // Software Reset -#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset -#define SYSCTL_SRWTIMER 0x400FE55C // 32/64-Bit Wide General-Purpose - // Timer Software Reset -#define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules - // Software Reset -#define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset -#define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset -#define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset -#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock - // Gating Control -#define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer - // Run Mode Clock Gating Control -#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run - // Mode Clock Gating Control -#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run - // Mode Clock Gating Control -#define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating - // Control -#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous - // Receiver/Transmitter Run Mode - // Clock Gating Control -#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run - // Mode Clock Gating Control -#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run - // Mode Clock Gating Control -#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode - // Clock Gating Control -#define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode - // Clock Gating Control -#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run - // Mode Clock Gating Control -#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock - // Gating Control -#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode - // Clock Gating Control -#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run - // Mode Clock Gating Control -#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER 0x400FE65C // 32/64-Bit Wide General-Purpose - // Timer Run Mode Clock Gating - // Control -#define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules - // Run Mode Clock Gating Control -#define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock - // Gating Control -#define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating - // Control -#define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock - // Gating Control -#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep - // Mode Clock Gating Control -#define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous - // Receiver/Transmitter Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep - // Mode Clock Gating Control -#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep - // Mode Clock Gating Control -#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER 0x400FE75C // 32/64-Bit Wide General-Purpose - // Timer Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules - // Sleep Mode Clock Gating Control -#define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous - // Receiver/Transmitter Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep - // Mode Clock Gating Control -#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER 0x400FE85C // 32/64-Bit Wide General-Purpose - // Timer Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules - // Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control -#define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer - // Power Control -#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output - // Power Control -#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power - // Control -#define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface - // Power Control -#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control -#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous - // Receiver/Transmitter Power - // Control -#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface - // Power Control -#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power - // Control -#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power - // Control -#define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control -#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power - // Control -#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter - // Power Control -#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control -#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power - // Control -#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface - // Power Control -#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control -#define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules - // Power Control -#define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control -#define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control -#define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control -#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready -#define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer - // Peripheral Ready -#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output - // Peripheral Ready -#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access - // Peripheral Ready -#define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready -#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready -#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous - // Receiver/Transmitter Peripheral - // Ready -#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface - // Peripheral Ready -#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit - // Peripheral Ready -#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral - // Ready -#define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready -#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network - // Peripheral Ready -#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter - // Peripheral Ready -#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral - // Ready -#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral - // Ready -#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface - // Peripheral Ready -#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready -#define SYSCTL_PRWTIMER 0x400FEA5C // 32/64-Bit Wide General-Purpose - // Timer Peripheral Ready -#define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules - // Peripheral Ready -#define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready -#define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready -#define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready -#define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0 -#define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1 -#define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2 -#define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3 -#define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock - // Gating Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version -#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 - // register format. -#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_TM4C123 \ - 0x00050000 // Tiva TM4C123x and TM4E123x - // microcontrollers -#define SYSCTL_DID0_CLASS_TM4C129 \ - 0x000A0000 // Tiva(TM) TM4C129-class - // microcontrollers -#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision -#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) -#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer - // revision) -#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer - // revision) -#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision -#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major - // revision update -#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change -#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version -#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib -#define SYSCTL_DID1_FAM_M 0x0F000000 // Family -#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers -#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number -#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \ - 0x00220000 // TM4C1230C3PM -#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \ - 0x00230000 // TM4C1230D5PM -#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \ - 0x00200000 // TM4C1230E6PM -#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \ - 0x00210000 // TM4C1230H6PM -#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \ - 0x00180000 // TM4C1231C3PM -#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \ - 0x00190000 // TM4C1231D5PM -#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \ - 0x00360000 // TM4C1231D5PZ -#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \ - 0x00100000 // TM4C1231E6PM -#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \ - 0x00300000 // TM4C1231E6PZ -#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \ - 0x00350000 // TM4C1231H6PGE -#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \ - 0x00110000 // TM4C1231H6PM -#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \ - 0x00310000 // TM4C1231H6PZ -#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \ - 0x00080000 // TM4C1232C3PM -#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \ - 0x00090000 // TM4C1232D5PM -#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \ - 0x000A0000 // TM4C1232E6PM -#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \ - 0x000B0000 // TM4C1232H6PM -#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \ - 0x00010000 // TM4C1233C3PM -#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \ - 0x00020000 // TM4C1233D5PM -#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \ - 0x00D00000 // TM4C1233D5PZ -#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \ - 0x00030000 // TM4C1233E6PM -#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \ - 0x00D10000 // TM4C1233E6PZ -#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \ - 0x00D60000 // TM4C1233H6PGE -#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \ - 0x00040000 // TM4C1233H6PM -#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \ - 0x00D20000 // TM4C1233H6PZ -#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \ - 0x00520000 // TM4C1236D5PM -#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \ - 0x00500000 // TM4C1236E6PM -#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \ - 0x00510000 // TM4C1236H6PM -#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \ - 0x00480000 // TM4C1237D5PM -#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \ - 0x00660000 // TM4C1237D5PZ -#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \ - 0x00400000 // TM4C1237E6PM -#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \ - 0x00600000 // TM4C1237E6PZ -#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \ - 0x00650000 // TM4C1237H6PGE -#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \ - 0x00410000 // TM4C1237H6PM -#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \ - 0x00610000 // TM4C1237H6PZ -#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \ - 0x00800000 // TM4C123AE6PM -#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \ - 0x00830000 // TM4C123AH6PM -#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \ - 0x00700000 // TM4C123BE6PM -#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \ - 0x00C30000 // TM4C123BE6PZ -#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \ - 0x00C60000 // TM4C123BH6PGE -#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \ - 0x00730000 // TM4C123BH6PM -#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \ - 0x00C40000 // TM4C123BH6PZ -#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \ - 0x00E90000 // TM4C123BH6ZRB -#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \ - 0x00B00000 // TM4C123FE6PM -#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \ - 0x00B10000 // TM4C123FH6PM -#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \ - 0x00A00000 // TM4C123GE6PM -#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \ - 0x00C00000 // TM4C123GE6PZ -#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \ - 0x00C50000 // TM4C123GH6PGE -#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \ - 0x00A10000 // TM4C123GH6PM -#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \ - 0x00C10000 // TM4C123GH6PZ -#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \ - 0x00E30000 // TM4C123GH6ZRB -#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \ - 0x00190000 // TM4C1290NCPDT -#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \ - 0x001B0000 // TM4C1290NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \ - 0x001C0000 // TM4C1292NCPDT -#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \ - 0x001E0000 // TM4C1292NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \ - 0x00340000 // TM4C1294KCPDT -#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \ - 0x001F0000 // TM4C1294NCPDT -#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \ - 0x00210000 // TM4C1294NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \ - 0x00220000 // TM4C1297NCZAD -#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \ - 0x00360000 // TM4C1299KCZAD -#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \ - 0x00230000 // TM4C1299NCZAD -#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \ - 0x00240000 // TM4C129CNCPDT -#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \ - 0x00260000 // TM4C129CNCZAD -#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \ - 0x00270000 // TM4C129DNCPDT -#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \ - 0x00290000 // TM4C129DNCZAD -#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \ - 0x00350000 // TM4C129EKCPDT -#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \ - 0x002D0000 // TM4C129ENCPDT -#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \ - 0x002F0000 // TM4C129ENCZAD -#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \ - 0x00300000 // TM4C129LNCZAD -#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \ - 0x00370000 // TM4C129XKCZAD -#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \ - 0x00320000 // TM4C129XNCZAD -#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package -#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package -#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package -#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package -#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package -#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range -#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range -#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial - // temperature range (-40C to 85C) - // and extended temperature range - // (-40C to 105C) devices. See -#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type -#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package -#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package -#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance -#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM -#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM -#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash -#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash -#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash -#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash -#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present -#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present -#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present -#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present -#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present -#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present -#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present -#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider -#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock - // with a PLL divider of 2.5 -#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock - // with a PLL divider of 4 -#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock - // with a PLL divider of 5 -#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a - // PLL divider of 8 -#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a - // PLL divider of 10 -#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed -#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second -#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second -#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second -#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second -#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed -#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second -#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second -#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second -#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second -#define SYSCTL_DC1_MPU 0x00000080 // MPU Present -#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present -#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present -#define SYSCTL_DC1_PLL 0x00000010 // PLL Present -#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present -#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present -#define SYSCTL_DC1_SWD 0x00000002 // SWD Present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present -#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present -#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present -#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present -#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed -#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present -#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed -#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present -#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present -#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present -#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present -#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present -#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present -#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present -#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available -#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present -#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present -#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present -#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present -#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present -#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present -#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present -#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present -#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present -#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present -#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present -#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present -#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present -#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present -#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present -#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present -#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present -#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present -#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present -#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable -#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate -#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present -#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present -#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present -#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present -#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present -#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present -#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present -#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC5 register. -// -//***************************************************************************** -#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present -#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present -#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present -#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present -#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active -#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active -#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present -#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present -#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present -#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present -#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present -#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present -#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present -#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC6 register. -// -//***************************************************************************** -#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present -#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present -#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only -#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host -#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC7 register. -// -//***************************************************************************** -#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 -#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 -#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 -#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 -#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 -#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 -#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 -#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 -#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 -#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 -#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 -#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 -#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 -#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 -#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 -#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 -#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 -#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 -#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 -#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 -#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 -#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 -#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 -#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 -#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 -#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 -#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 -#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 -#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 -#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 -#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC8 register. -// -//***************************************************************************** -#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present -#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present -#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present -#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present -#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present -#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present -#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present -#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present -#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present -#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present -#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present -#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present -#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present -#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present -#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present -#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present -#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present -#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present -#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present -#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present -#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present -#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present -#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present -#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present -#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present -#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present -#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present -#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present -#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present -#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present -#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present -#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action -#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PTBOCTL register. -// -//***************************************************************************** -#define SYSCTL_PTBOCTL_VDDA_UBOR_M \ - 0x00000300 // VDDA under BOR Event Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ - 0x00000100 // System control interrupt -#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ - 0x00000200 // NMI -#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ - 0x00000300 // Reset -#define SYSCTL_PTBOCTL_VDD_UBOR_M \ - 0x00000003 // VDD (VDDS) under BOR Event - // Action -#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ - 0x00000001 // System control interrupt -#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ - 0x00000002 // NMI -#define SYSCTL_PTBOCTL_VDD_UBOR_RST \ - 0x00000003 // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR0 register. -// -//***************************************************************************** -#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control -#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control -#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control -#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control -#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control -#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control -#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control -#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR1 register. -// -//***************************************************************************** -#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control -#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control -#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control -#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control -#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control -#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control -#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control -#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control -#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control -#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control -#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control -#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control -#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control -#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control -#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control -#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCR2 register. -// -//***************************************************************************** -#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control -#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control -#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control -#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control -#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control -#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control -#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control -#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control -#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control -#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control -#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RIS register. -// -//***************************************************************************** -#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt - // Status -#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw - // Interrupt Status -#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt - // Status -#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt - // Status -#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status -#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw - // Interrupt Status -#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt - // Status -#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_IMC register. -// -//***************************************************************************** -#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask -#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask -#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask -#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask -#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask -#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure - // Interrupt Mask -#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask -#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MISC register. -// -//***************************************************************************** -#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt - // Status -#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt - // Status -#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt - // Status -#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt - // Status -#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status -#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked - // Interrupt Status -#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status -#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset -#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset -#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset -#define SYSCTL_RESC_SW 0x00000010 // Software Reset -#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset -#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset -#define SYSCTL_RESC_EXT 0x00000001 // External Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PWRTC register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status -#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating -#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor -#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider -#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor -#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass -#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value -#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz -#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz -#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz -#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz -#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz -#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz -#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz -#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz -#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) -#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) -#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) -#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) -#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 -#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable -#define SYSCTL_RCC_SYSDIV_S 23 -#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NMIC register. -// -//***************************************************************************** -#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI -#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI -#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI -#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI -#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI -#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL -// register. -// -//***************************************************************************** -#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance - // Bus -#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance - // Bus - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCC2 register. -// -//***************************************************************************** -#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 -#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 - // MHz -#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 -#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 -#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL -#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 -#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 -#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 -#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC -#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC -#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 -#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC -#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz -#define SYSCTL_RCC2_SYSDIV2_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. -// -//***************************************************************************** -#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range -#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down -#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected -#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action -#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update -#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept -#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating -#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL -#define SYSCTL_RSCLKCFG_PLLSRC_M \ - 0x0F000000 // PLL Source -#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ - 0x00000000 // PIOSC is PLL input clock source -#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ - 0x03000000 // MOSC is the PLL input clock - // source -#define SYSCTL_RSCLKCFG_OSCSRC_M \ - 0x00F00000 // Oscillator Source -#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ - 0x00000000 // PIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ - 0x00200000 // LFIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ - 0x00300000 // MOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_RTC \ - 0x00400000 // Hibernation Module RTC - // Oscillator (RTCOSC) -#define SYSCTL_RSCLKCFG_OSYSDIV_M \ - 0x000FFC00 // Oscillator System Clock Divisor -#define SYSCTL_RSCLKCFG_PSYSDIV_M \ - 0x000003FF // PLL System Clock Divisor -#define SYSCTL_RSCLKCFG_OSYSDIV_S \ - 10 -#define SYSCTL_RSCLKCFG_PSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register. -// -//***************************************************************************** -#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time -#define SYSCTL_MEMTIM0_EBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1_5 \ - 0x00800000 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2_5 \ - 0x01000000 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3_5 \ - 0x01800000 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4_5 \ - 0x02000000 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge -#define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one -#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States -#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time -#define SYSCTL_MEMTIM0_FBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1_5 \ - 0x00000080 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2_5 \ - 0x00000100 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3_5 \ - 0x00000180 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4_5 \ - 0x00000200 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge -#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State -#define SYSCTL_MEMTIM0_EWS_S 16 -#define SYSCTL_MEMTIM0_FWS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC0 register. -// -//***************************************************************************** -#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed -#define SYSCTL_RCGC0_ADC1SPD_125K \ - 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADC1SPD_250K \ - 0x00000400 // 250K samples/second -#define SYSCTL_RCGC0_ADC1SPD_500K \ - 0x00000800 // 500K samples/second -#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second -#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed -#define SYSCTL_RCGC0_ADC0SPD_125K \ - 0x00000000 // 125K samples/second -#define SYSCTL_RCGC0_ADC0SPD_250K \ - 0x00000100 // 250K samples/second -#define SYSCTL_RCGC0_ADC0SPD_500K \ - 0x00000200 // 500K samples/second -#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second -#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC1 register. -// -//***************************************************************************** -#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGC2 register. -// -//***************************************************************************** -#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC0 register. -// -//***************************************************************************** -#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed -#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC1 register. -// -//***************************************************************************** -#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGC2 register. -// -//***************************************************************************** -#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC0 register. -// -//***************************************************************************** -#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control -#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control -#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control -#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control -#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control -#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control -#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control -#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC1 register. -// -//***************************************************************************** -#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating -#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating -#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating -#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control -#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control -#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control -#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control -#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control -#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control -#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control -#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control -#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control -#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control -#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control -#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control -#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGC2 register. -// -//***************************************************************************** -#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control -#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control -#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control -#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control -#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control -#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control -#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control -#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control -#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control -#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control -#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_ALTCLKCFG_ALTCLK_M \ - 0x0000000F // Alternate Clock Source -#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ - 0x00000003 // Hibernation Module Real-time - // clock output (RTCOSC) -#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ - 0x00000004 // Low-frequency internal - // oscillator (LFIOSC) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override -#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source -#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC -#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC -#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC -#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz -#define SYSCTL_DSLPCLKCFG_PIOSCPD \ - 0x00000002 // PIOSC Power Down Request -#define SYSCTL_DSLPCLKCFG_D_S 23 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down -#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down -#define SYSCTL_DSCLKCFG_DSOSCSRC_M \ - 0x00F00000 // Deep Sleep Oscillator Source -#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ - 0x00200000 // LFIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ - 0x00300000 // MOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ - 0x00400000 // Hibernation Module RTCOSC -#define SYSCTL_DSCLKCFG_DSSYSDIV_M \ - 0x000003FF // Deep Sleep Clock Divisor -#define SYSCTL_DSCLKCFG_DSSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DIVSCLK register. -// -//***************************************************************************** -#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable -#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source -#define SYSCTL_DIVSCLK_SRC_SYSCLK \ - 0x00000000 // System Clock -#define SYSCTL_DIVSCLK_SRC_PIOSC \ - 0x00010000 // PIOSC -#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC -#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value -#define SYSCTL_DIVSCLK_DIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SYSPROP register. -// -//***************************************************************************** -#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCCAL -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value -#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration -#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim -#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value -#define SYSCTL_PIOSCCAL_UT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value -#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result -#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been - // attempted -#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation - // completed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation - // failed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value -#define SYSCTL_PIOSCSTAT_DT_S 16 -#define SYSCTL_PIOSCSTAT_CT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power -#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value -#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value -#define SYSCTL_PLLFREQ0_MFRAC_S 10 -#define SYSCTL_PLLFREQ0_MINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value -#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value -#define SYSCTL_PLLFREQ1_Q_S 8 -#define SYSCTL_PLLFREQ1_N_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. -// -//***************************************************************************** -#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_SLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode -#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down -#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DC9 register. -// -//***************************************************************************** -#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present -#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present -#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present -#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present -#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present -#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present -#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present -#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present -#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present -#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present -#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present -#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present -#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present -#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present -#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present -#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. -// -//***************************************************************************** -#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer - // Available - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDOSPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDOSPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDOSPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDOSPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDOSPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDOSPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDOSPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDOSPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDODPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDODPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDODPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDODPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDODPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDODPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDODPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDODPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V -#define SYSCTL_LDODPCTL_VLDO_1_25V \ - 0x00000019 // 1.25 V -#define SYSCTL_LDODPCTL_VLDO_1_30V \ - 0x0000001A // 1.30 V -#define SYSCTL_LDODPCTL_VLDO_1_35V \ - 0x0000001B // 1.35 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL -// register. -// -//***************************************************************************** -#define SYSCTL_RESBEHAVCTL_WDOG1_M \ - 0x000000C0 // Watchdog 1 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ - 0x00000080 // Watchdog 1 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG1_POR \ - 0x000000C0 // Watchdog 1 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_WDOG0_M \ - 0x00000030 // Watchdog 0 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ - 0x00000020 // Watchdog 0 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG0_POR \ - 0x00000030 // Watchdog 0 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_BOR_M \ - 0x0000000C // BOR Reset operation -#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ - 0x00000008 // Brown Out Reset issues system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_BOR_POR \ - 0x0000000C // Brown Out Reset issues a - // simulated POR sequence. The - // application starts less than 500 - // us after deassertion (Default) -#define SYSCTL_RESBEHAVCTL_EXTRES_M \ - 0x00000003 // External RST Pin Operation -#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ - 0x00000002 // External RST assertion issues a - // system reset. The application - // starts within 10 us -#define SYSCTL_RESBEHAVCTL_EXTRES_POR \ - 0x00000003 // External RST assertion issues a - // simulated POR sequence. - // Application starts less than 500 - // us after deassertion (Default) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_HSSR register. -// -//***************************************************************************** -#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key -#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer -#define SYSCTL_HSSR_KEY_S 24 -#define SYSCTL_HSSR_CDOFF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBPDS register. -// -//***************************************************************************** -#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status -#define SYSCTL_USBPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBPDS_MEMSTAT_RETAIN \ - 0x00000004 // SRAM Retention -#define SYSCTL_USBPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status -#define SYSCTL_USBPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_USBPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBMPC register. -// -//***************************************************************************** -#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_USBMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBMPC_PWRCTL_RETAIN \ - 0x00000001 // SRAM Retention -#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACPDS register. -// -//***************************************************************************** -#define SYSCTL_EMACPDS_MEMSTAT_M \ - 0x0000000C // Memory Array Power Status -#define SYSCTL_EMACPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_EMACPDS_PWRSTAT_M \ - 0x00000003 // Power Domain Status -#define SYSCTL_EMACPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_EMACPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACMPC register. -// -//***************************************************************************** -#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_EMACMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACMPC_PWRCTL_ON \ - 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LCDMPC register. -// -//***************************************************************************** -#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_LCDMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWD register. -// -//***************************************************************************** -#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present -#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPTIMER register. -// -//***************************************************************************** -#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Present -#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Present -#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Present -#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Present -#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Present -#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Present -#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Present -#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPGPIO register. -// -//***************************************************************************** -#define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present -#define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present -#define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present -#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present -#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present -#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present -#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present -#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present -#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present -#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present -#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present -#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present -#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present -#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present -#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present -#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present -#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present -#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPDMA register. -// -//***************************************************************************** -#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPI register. -// -//***************************************************************************** -#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIB register. -// -//***************************************************************************** -#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUART register. -// -//***************************************************************************** -#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present -#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present -#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present -#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present -#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present -#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present -#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present -#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPSSI register. -// -//***************************************************************************** -#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present -#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present -#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present -#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPI2C register. -// -//***************************************************************************** -#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present -#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present -#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present -#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present -#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present -#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present -#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present -#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present -#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present -#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUSB register. -// -//***************************************************************************** -#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPHY register. -// -//***************************************************************************** -#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCAN register. -// -//***************************************************************************** -#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present -#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPADC register. -// -//***************************************************************************** -#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present -#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPACMP register. -// -//***************************************************************************** -#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPWM register. -// -//***************************************************************************** -#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present -#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPQEI register. -// -//***************************************************************************** -#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present -#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLPC register. -// -//***************************************************************************** -#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPECI register. -// -//***************************************************************************** -#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPFAN register. -// -//***************************************************************************** -#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Present -#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Present -#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Present -#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Present -#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Present -#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPRTS register. -// -//***************************************************************************** -#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCCM register. -// -//***************************************************************************** -#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLCD register. -// -//***************************************************************************** -#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPOWIRE register. -// -//***************************************************************************** -#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEMAC register. -// -//***************************************************************************** -#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIM register. -// -//***************************************************************************** -#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWD register. -// -//***************************************************************************** -#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset -#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRTIMER register. -// -//***************************************************************************** -#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Software Reset -#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Software Reset -#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Software Reset -#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Software Reset -#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Software Reset -#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Software Reset -#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Software Reset -#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRGPIO register. -// -//***************************************************************************** -#define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset -#define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset -#define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset -#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset -#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset -#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset -#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset -#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset -#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset -#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset -#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset -#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset -#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset -#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset -#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset -#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset -#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset -#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRDMA register. -// -//***************************************************************************** -#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPI register. -// -//***************************************************************************** -#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRHIB register. -// -//***************************************************************************** -#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUART register. -// -//***************************************************************************** -#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset -#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset -#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset -#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset -#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset -#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset -#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset -#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRSSI register. -// -//***************************************************************************** -#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset -#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset -#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset -#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRI2C register. -// -//***************************************************************************** -#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset -#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset -#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset -#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset -#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset -#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset -#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset -#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset -#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset -#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUSB register. -// -//***************************************************************************** -#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPHY register. -// -//***************************************************************************** -#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCAN register. -// -//***************************************************************************** -#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset -#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRADC register. -// -//***************************************************************************** -#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset -#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRACMP register. -// -//***************************************************************************** -#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRPWM register. -// -//***************************************************************************** -#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset -#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRQEI register. -// -//***************************************************************************** -#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset -#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Software Reset -#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Software Reset -#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Software Reset -#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Software Reset -#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Software Reset -#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCCM register. -// -//***************************************************************************** -#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRLCD register. -// -//***************************************************************************** -#define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SROWIRE register. -// -//***************************************************************************** -#define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREMAC register. -// -//***************************************************************************** -#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWD register. -// -//***************************************************************************** -#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCADC register. -// -//***************************************************************************** -#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Run Mode Clock Gating - // Control -#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCLCD register. -// -//***************************************************************************** -#define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWD register. -// -//***************************************************************************** -#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCADC register. -// -//***************************************************************************** -#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules - // Sleep Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCLCD register. -// -//***************************************************************************** -#define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWD register. -// -//***************************************************************************** -#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCADC register. -// -//***************************************************************************** -#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Deep-Sleep Mode Clock - // Gating Control -#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCLCD register. -// -//***************************************************************************** -#define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0 - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCWD register. -// -//***************************************************************************** -#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control -#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCTIMER register. -// -//***************************************************************************** -#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power - // Control -#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power - // Control -#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power - // Control -#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power - // Control -#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power - // Control -#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power - // Control -#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power - // Control -#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCGPIO register. -// -//***************************************************************************** -#define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control -#define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control -#define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control -#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control -#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control -#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control -#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control -#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control -#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control -#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control -#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control -#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control -#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control -#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control -#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control -#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control -#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control -#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCDMA register. -// -//***************************************************************************** -#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPI register. -// -//***************************************************************************** -#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCHIB register. -// -//***************************************************************************** -#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUART register. -// -//***************************************************************************** -#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control -#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control -#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control -#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control -#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control -#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control -#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control -#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCSSI register. -// -//***************************************************************************** -#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control -#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control -#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control -#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCI2C register. -// -//***************************************************************************** -#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control -#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control -#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control -#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control -#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control -#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control -#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control -#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control -#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control -#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUSB register. -// -//***************************************************************************** -#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPHY register. -// -//***************************************************************************** -#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCAN register. -// -//***************************************************************************** -#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control -#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCADC register. -// -//***************************************************************************** -#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control -#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCACMP register. -// -//***************************************************************************** -#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCPWM register. -// -//***************************************************************************** -#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCQEI register. -// -//***************************************************************************** -#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCCM register. -// -//***************************************************************************** -#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCLCD register. -// -//***************************************************************************** -#define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCOWIRE register. -// -//***************************************************************************** -#define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEMAC register. -// -//***************************************************************************** -#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWD register. -// -//***************************************************************************** -#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral - // Ready -#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRTIMER register. -// -//***************************************************************************** -#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Peripheral Ready -#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Peripheral Ready -#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Peripheral Ready -#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Peripheral Ready -#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Peripheral Ready -#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Peripheral Ready -#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Peripheral Ready -#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRGPIO register. -// -//***************************************************************************** -#define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready -#define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready -#define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready -#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready -#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready -#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready -#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready -#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready -#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready -#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready -#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready -#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready -#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready -#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready -#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready -#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready -#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready -#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRDMA register. -// -//***************************************************************************** -#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPI register. -// -//***************************************************************************** -#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRHIB register. -// -//***************************************************************************** -#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUART register. -// -//***************************************************************************** -#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready -#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready -#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready -#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready -#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready -#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready -#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready -#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRSSI register. -// -//***************************************************************************** -#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready -#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready -#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready -#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRI2C register. -// -//***************************************************************************** -#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready -#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready -#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready -#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready -#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready -#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready -#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready -#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready -#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready -#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUSB register. -// -//***************************************************************************** -#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPHY register. -// -//***************************************************************************** -#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCAN register. -// -//***************************************************************************** -#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready -#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRADC register. -// -//***************************************************************************** -#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready -#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRACMP register. -// -//***************************************************************************** -#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRPWM register. -// -//***************************************************************************** -#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready -#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRQEI register. -// -//***************************************************************************** -#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready -#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose - // Timer 5 Peripheral Ready -#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose - // Timer 4 Peripheral Ready -#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose - // Timer 3 Peripheral Ready -#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose - // Timer 2 Peripheral Ready -#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose - // Timer 1 Peripheral Ready -#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCCM register. -// -//***************************************************************************** -#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRLCD register. -// -//***************************************************************************** -#define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0 - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PROWIRE register. -// -//***************************************************************************** -#define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREMAC register. -// -//***************************************************************************** -#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID0 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID0_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID1 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID2 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_UNIQUEID3 -// register. -// -//***************************************************************************** -#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID -#define SYSCTL_UNIQUEID3_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_CCMCGREQ -// register. -// -//***************************************************************************** -#define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request -#define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request -#define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the SYSCTL_DID0 -// register. -// -//***************************************************************************** -#define SYSCTL_DID0_CLASS_BLIZZARD \ - 0x00050000 // Tiva(TM) C Series TM4C123-class - // microcontrollers -#define SYSCTL_DID0_CLASS_SNOWFLAKE \ - 0x000A0000 // Tiva(TM) C Series TM4C129-class - // microcontrollers - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the SYSCTL_RESC -// register. -// -//***************************************************************************** -#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC -// register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status -#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status - -#endif - -#endif // __HW_SYSCTL_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_sysexc.h b/bsp/tm4c129x-dk/libraries/inc/hw_sysexc.h deleted file mode 100644 index 314d17a8a1..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_sysexc.h +++ /dev/null @@ -1,132 +0,0 @@ -//***************************************************************************** -// -// hw_sysexc.h - Macros used when accessing the system exception module. -// -// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_SYSEXC_H__ -#define __HW_SYSEXC_H__ - -//***************************************************************************** -// -// The following are defines for the System Exception Module register -// addresses. -// -//***************************************************************************** -#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt - // Status -#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask -#define SYSEXC_MIS 0x400F9008 // System Exception Masked - // Interrupt Status -#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_RIS register. -// -//***************************************************************************** -#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception - // Raw Interrupt Status -#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation - // Raw Interrupt Status -#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal - // Exception Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IM register. -// -//***************************************************************************** -#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception - // Interrupt Mask -#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation - // Interrupt Mask -#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Mask -#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_MIS register. -// -//***************************************************************************** -#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception - // Masked Interrupt Status -#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation - // Masked Interrupt Status -#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal - // Exception Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IC register. -// -//***************************************************************************** -#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception - // Interrupt Clear -#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation - // Interrupt Clear -#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Clear -#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Clear - -#endif // __HW_SYSEXC_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_timer.h b/bsp/tm4c129x-dk/libraries/inc/hw_timer.h deleted file mode 100644 index 47a857567a..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_timer.h +++ /dev/null @@ -1,700 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following are defines for the Timer register offsets. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // GPTM Configuration -#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode -#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode -#define TIMER_O_CTL 0x0000000C // GPTM Control -#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize -#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask -#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status -#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status -#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear -#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load -#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load -#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match -#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match -#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale -#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale -#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match -#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match -#define TIMER_O_TAR 0x00000048 // GPTM Timer A -#define TIMER_O_TBR 0x0000004C // GPTM Timer B -#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value -#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value -#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide -#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot -#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot -#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value -#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value -#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event -#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event -#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties -#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this - // value selects the 32-bit timer - // configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this - // value selects the 32-bit - // real-time clock (RTC) counter - // configuration -#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this - // value selects the 16-bit timer - // configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TAMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt - // Disable -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TBMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt - // Disable -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer - // 5 -#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not - // affected -#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 5 is - // triggered -#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 5 is triggered -#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer - // 4 -#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not - // affected -#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 4 is - // triggered -#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 4 is triggered -#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer - // 3 -#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not - // affected -#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 3 is - // triggered -#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 3 is triggered -#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer - // 2 -#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not - // affected -#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 2 is - // triggered -#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 2 is triggered -#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7 -#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected -#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM7 is - // triggered -#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer - // 1 -#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not - // affected -#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 1 is - // triggered -#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 1 is triggered -#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer - // 0 -#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not - // affected -#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of - // GPTM 32/64-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of - // GPTM 32/64-Bit Timer 0 is - // triggered -#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM 32/64-Bit - // Timer 0 is triggered -#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6 -#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected -#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM6 is - // triggered -#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 -#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected -#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM5 is - // triggered -#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 -#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected -#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM4 is - // triggered -#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 -#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected -#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM3 is - // triggered -#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 -#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected -#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM2 is - // triggered -#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 -#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected -#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM1 is - // triggered -#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 -#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected -#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM0 is - // triggered - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Interrupt Mask -#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt - // Mask -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt - // Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt - // Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Raw Interrupt Status -#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Masked Interrupt Status -#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked - // Interrupt -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update - // Error Interrupt Clear -#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt - // Clear -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt - // Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt - // Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -#define TIMER_TAILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -#define TIMER_TAMATCHR_TAMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -#define TIMER_TBMATCHR_TBMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -#define TIMER_TAPR_TAPSRH_S 8 -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -#define TIMER_TBPR_TBPSRH_S 8 -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High - // Byte -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -#define TIMER_TAPMR_TAPSMRH_S 8 -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High - // Byte -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -#define TIMER_TBPMR_TBPSMRH_S 8 -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -#define TIMER_TAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -#define TIMER_TBR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -#define TIMER_TAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPV register. -// -//***************************************************************************** -#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TAPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPV register. -// -//***************************************************************************** -#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value -#define TIMER_TBPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_DMAEV register. -// -//***************************************************************************** -#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA - // Trigger Enable -#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ADCEV register. -// -//***************************************************************************** -#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC - // Trigger Enable -#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source -#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start -#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are - // 32 bits each with a 16-bit - // prescale counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CC register. -// -//***************************************************************************** -#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source - -#endif // __HW_TIMER_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_types.h b/bsp/tm4c129x-dk/libraries/inc/hw_types.h deleted file mode 100644 index ec493b5061..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_types.h +++ /dev/null @@ -1,147 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile uint32_t *)(x))) -#define HWREGH(x) \ - (*((volatile uint16_t *)(x))) -#define HWREGB(x) \ - (*((volatile uint8_t *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -//***************************************************************************** -// -// Helper Macros for determining silicon revisions, etc. -// -// These macros will be used by Driverlib at "run-time" to create necessary -// conditional code blocks that will allow a single version of the Driverlib -// "binary" code to support multiple(all) Tiva silicon revisions. -// -// It is expected that these macros will be used inside of a standard 'C' -// conditional block of code, e.g. -// -// if(CLASS_IS_TM4C123) -// { -// do some TM4C123-class specific code here. -// } -// -// By default, these macros will be defined as run-time checks of the -// appropriate register(s) to allow creation of run-time conditional code -// blocks for a common DriverLib across the entire Tiva family. -// -// However, if code-space optimization is required, these macros can be "hard- -// coded" for a specific version of Tiva silicon. Many compilers will then -// detect the "hard-coded" conditionals, and appropriately optimize the code -// blocks, eliminating any "unreachable" code. This would result in a smaller -// Driverlib, thus producing a smaller final application size, but at the cost -// of limiting the Driverlib binary to a specific Tiva silicon revision. -// -//***************************************************************************** -#ifndef CLASS_IS_TM4C123 -#define CLASS_IS_TM4C123 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ - (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123)) -#endif - -#ifndef CLASS_IS_TM4C129 -#define CLASS_IS_TM4C129 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ - (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129)) -#endif - -#ifndef REVISION_IS_A0 -#define REVISION_IS_A0 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) -#endif - -#ifndef REVISION_IS_A1 -#define REVISION_IS_A1 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) -#endif - -#ifndef REVISION_IS_A2 -#define REVISION_IS_A2 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) -#endif - -#ifndef REVISION_IS_B0 -#define REVISION_IS_B0 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) -#endif - -#ifndef REVISION_IS_B1 -#define REVISION_IS_B1 \ - ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ - (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) -#endif - -//***************************************************************************** -// -// For TivaWare 2.1, we removed all references to Tiva IC codenames from the -// source. To ensure that existing customer code doesn't break as a result -// of this change, make sure that the old definitions are still available at -// least for the time being. -// -//***************************************************************************** -#ifndef DEPRECATED -#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123 -#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123 -#endif - -#endif // __HW_TYPES_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_uart.h b/bsp/tm4c129x-dk/libraries/inc/hw_uart.h deleted file mode 100644 index 1c40b79f3d..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_uart.h +++ /dev/null @@ -1,367 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// The following are defines for the UART register offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // UART Data -#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear -#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear -#define UART_O_FR 0x00000018 // UART Flag -#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register -#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate - // Divisor -#define UART_O_LCRH 0x0000002C // UART Line Control -#define UART_O_CTL 0x00000030 // UART Control -#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select -#define UART_O_IM 0x00000038 // UART Interrupt Mask -#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status -#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status -#define UART_O_ICR 0x00000044 // UART Interrupt Clear -#define UART_O_DMACTL 0x00000048 // UART DMA Control -#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address -#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask -#define UART_O_PP 0x00000FC0 // UART Peripheral Properties -#define UART_O_CC 0x00000FC8 // UART Clock Configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//***************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//***************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//***************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//***************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//***************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//***************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full -#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full -#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) -#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full -#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full -#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full -#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) -#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full -#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//***************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//***************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//***************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//***************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//***************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITADDR -// register. -// -//***************************************************************************** -#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode -#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode -#define UART_9BITADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITAMASK -// register. -// -//***************************************************************************** -#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode -#define UART_9BITAMASK_MASK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//***************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//***************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source -#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock - // source and divisor factor) -#define UART_CC_CS_PIOSC 0x00000005 // PIOSC - -#endif // __HW_UART_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_udma.h b/bsp/tm4c129x-dk/libraries/inc/hw_udma.h deleted file mode 100644 index 1d52b00901..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_udma.h +++ /dev/null @@ -1,414 +0,0 @@ -//***************************************************************************** -// -// hw_udma.h - Macros for use in accessing the UDMA registers. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_UDMA_H__ -#define __HW_UDMA_H__ - -//***************************************************************************** -// -// The following are defines for the Micro Direct Memory Access register -// addresses. -// -//***************************************************************************** -#define UDMA_STAT 0x400FF000 // DMA Status -#define UDMA_CFG 0x400FF004 // DMA Configuration -#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer -#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control - // Base Pointer -#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request - // Status -#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request -#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set -#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear -#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set -#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear -#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set -#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear -#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate - // Set -#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate - // Clear -#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set -#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear -#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear -#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment -#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status -#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 -#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 -#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 -#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_STAT register. -// -//***************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status -#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle -#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data -#define UDMA_STAT_STATE_RD_SRCENDP \ - 0x00000020 // Reading source end pointer -#define UDMA_STAT_STATE_RD_DSTENDP \ - 0x00000030 // Reading destination end pointer -#define UDMA_STAT_STATE_RD_SRCDAT \ - 0x00000040 // Reading source data -#define UDMA_STAT_STATE_WR_DSTDAT \ - 0x00000050 // Writing destination data -#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to - // clear -#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data -#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled -#define UDMA_STAT_STATE_DONE 0x00000090 // Done -#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -#define UDMA_STAT_DMACHANS_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CFG register. -// -//***************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CTLBASE register. -// -//***************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTBASE register. -// -//***************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_WAITSTAT register. -// -//***************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_SWREQ register. -// -//***************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTSET -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTCLR -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKSET -// register. -// -//***************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKCLR -// register. -// -//***************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENASET register. -// -//***************************************************************************** -#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENACLR register. -// -//***************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTSET register. -// -//***************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTCLR register. -// -//***************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOSET register. -// -//***************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOCLR register. -// -//***************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ERRCLR register. -// -//***************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHASGN register. -// -//***************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel - // assignment -#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel - // assignment - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHIS register. -// -//***************************************************************************** -#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP0 register. -// -//***************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP1 register. -// -//***************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP2 register. -// -//***************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP3 register. -// -//***************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the Micro Direct Memory Access (uDMA) offsets. -// -//***************************************************************************** -#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access -#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - -#endif // __HW_UDMA_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_watchdog.h b/bsp/tm4c129x-dk/libraries/inc/hw_watchdog.h deleted file mode 100644 index 783b6f07f6..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/hw_watchdog.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following are defines for the Watchdog Timer register offsets. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Watchdog Load -#define WDT_O_VALUE 0x00000004 // Watchdog Value -#define WDT_O_CTL 0x00000008 // Watchdog Control -#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear -#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status -#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status -#define WDT_O_TEST 0x00000418 // Watchdog Test -#define WDT_O_LOCK 0x00000C00 // Watchdog Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//***************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//***************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//***************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//***************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//***************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//***************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -#endif // __HW_WATCHDOG_H__ diff --git a/bsp/tm4c129x-dk/libraries/inc/tm4c1294ncpdt.h b/bsp/tm4c129x-dk/libraries/inc/tm4c1294ncpdt.h deleted file mode 100644 index 458eaac395..0000000000 --- a/bsp/tm4c129x-dk/libraries/inc/tm4c1294ncpdt.h +++ /dev/null @@ -1,15610 +0,0 @@ -//***************************************************************************** -// -// tm4c1294ncpdt.h - TM4C1294NCPDT Register Definitions -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. -// -//***************************************************************************** - -#ifndef __TM4C1294NCPDT_H__ -#define __TM4C1294NCPDT_H__ - -//***************************************************************************** -// -// Interrupt assignments -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 -#define INT_UART1 22 // UART1 -#define INT_SSI0 23 // SSI0 -#define INT_I2C0 24 // I2C0 -#define INT_PWM0_FAULT 25 // PWM Fault -#define INT_PWM0_0 26 // PWM Generator 0 -#define INT_PWM0_1 27 // PWM Generator 1 -#define INT_PWM0_2 28 // PWM Generator 2 -#define INT_QEI0 29 // QEI0 -#define INT_ADC0SS0 30 // ADC0 Sequence 0 -#define INT_ADC0SS1 31 // ADC0 Sequence 1 -#define INT_ADC0SS2 32 // ADC0 Sequence 2 -#define INT_ADC0SS3 33 // ADC0 Sequence 3 -#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1 -#define INT_TIMER0A 35 // 16/32-Bit Timer 0A -#define INT_TIMER0B 36 // 16/32-Bit Timer 0B -#define INT_TIMER1A 37 // 16/32-Bit Timer 1A -#define INT_TIMER1B 38 // 16/32-Bit Timer 1B -#define INT_TIMER2A 39 // 16/32-Bit Timer 2A -#define INT_TIMER2B 40 // 16/32-Bit Timer 2B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control -#define INT_FLASH 45 // Flash Memory Control -#define INT_GPIOF 46 // GPIO Port F -#define INT_GPIOG 47 // GPIO Port G -#define INT_GPIOH 48 // GPIO Port H -#define INT_UART2 49 // UART2 -#define INT_SSI1 50 // SSI1 -#define INT_TIMER3A 51 // 16/32-Bit Timer 3A -#define INT_TIMER3B 52 // 16/32-Bit Timer 3B -#define INT_I2C1 53 // I2C1 -#define INT_CAN0 54 // CAN 0 -#define INT_CAN1 55 // CAN1 -#define INT_EMAC0 56 // Ethernet MAC -#define INT_HIBERNATE 57 // HIB -#define INT_USB0 58 // USB MAC -#define INT_PWM0_3 59 // PWM Generator 3 -#define INT_UDMA 60 // uDMA 0 Software -#define INT_UDMAERR 61 // uDMA 0 Error -#define INT_ADC1SS0 62 // ADC1 Sequence 0 -#define INT_ADC1SS1 63 // ADC1 Sequence 1 -#define INT_ADC1SS2 64 // ADC1 Sequence 2 -#define INT_ADC1SS3 65 // ADC1 Sequence 3 -#define INT_EPI0 66 // EPI 0 -#define INT_GPIOJ 67 // GPIO Port J -#define INT_GPIOK 68 // GPIO Port K -#define INT_GPIOL 69 // GPIO Port L -#define INT_SSI2 70 // SSI 2 -#define INT_SSI3 71 // SSI 3 -#define INT_UART3 72 // UART 3 -#define INT_UART4 73 // UART 4 -#define INT_UART5 74 // UART 5 -#define INT_UART6 75 // UART 6 -#define INT_UART7 76 // UART 7 -#define INT_I2C2 77 // I2C 2 -#define INT_I2C3 78 // I2C 3 -#define INT_TIMER4A 79 // Timer 4A -#define INT_TIMER4B 80 // Timer 4B -#define INT_TIMER5A 81 // Timer 5A -#define INT_TIMER5B 82 // Timer 5B -#define INT_SYSEXC 83 // Floating-Point Exception - // (imprecise) -#define INT_I2C4 86 // I2C 4 -#define INT_I2C5 87 // I2C 5 -#define INT_GPIOM 88 // GPIO Port M -#define INT_GPION 89 // GPIO Port N -#define INT_TAMPER0 91 // Tamper -#define INT_GPIOP0 92 // GPIO Port P (Summary or P0) -#define INT_GPIOP1 93 // GPIO Port P1 -#define INT_GPIOP2 94 // GPIO Port P2 -#define INT_GPIOP3 95 // GPIO Port P3 -#define INT_GPIOP4 96 // GPIO Port P4 -#define INT_GPIOP5 97 // GPIO Port P5 -#define INT_GPIOP6 98 // GPIO Port P6 -#define INT_GPIOP7 99 // GPIO Port P7 -#define INT_GPIOQ0 100 // GPIO Port Q (Summary or Q0) -#define INT_GPIOQ1 101 // GPIO Port Q1 -#define INT_GPIOQ2 102 // GPIO Port Q2 -#define INT_GPIOQ3 103 // GPIO Port Q3 -#define INT_GPIOQ4 104 // GPIO Port Q4 -#define INT_GPIOQ5 105 // GPIO Port Q5 -#define INT_GPIOQ6 106 // GPIO Port Q6 -#define INT_GPIOQ7 107 // GPIO Port Q7 -#define INT_TIMER6A 114 // 16/32-Bit Timer 6A -#define INT_TIMER6B 115 // 16/32-Bit Timer 6B -#define INT_TIMER7A 116 // 16/32-Bit Timer 7A -#define INT_TIMER7B 117 // 16/32-Bit Timer 7B -#define INT_I2C6 118 // I2C 6 -#define INT_I2C7 119 // I2C 7 -#define INT_I2C8 125 // I2C 8 -#define INT_I2C9 126 // I2C 9 - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG0) -// -//***************************************************************************** -#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) -#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) -#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) -#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) -#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) -#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) -#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) -#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) - -//***************************************************************************** -// -// Watchdog Timer registers (WATCHDOG1) -// -//***************************************************************************** -#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) -#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) -#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) -#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) -#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) -#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) -#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) -#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) - -//***************************************************************************** -// -// SSI registers (SSI0) -// -//***************************************************************************** -#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) -#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) -#define SSI0_DR_R (*((volatile uint32_t *)0x40008008)) -#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) -#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) -#define SSI0_IM_R (*((volatile uint32_t *)0x40008014)) -#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) -#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) -#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) -#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) -#define SSI0_PP_R (*((volatile uint32_t *)0x40008FC0)) -#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) - -//***************************************************************************** -// -// SSI registers (SSI1) -// -//***************************************************************************** -#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) -#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) -#define SSI1_DR_R (*((volatile uint32_t *)0x40009008)) -#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) -#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) -#define SSI1_IM_R (*((volatile uint32_t *)0x40009014)) -#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) -#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) -#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) -#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) -#define SSI1_PP_R (*((volatile uint32_t *)0x40009FC0)) -#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) - -//***************************************************************************** -// -// SSI registers (SSI2) -// -//***************************************************************************** -#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) -#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) -#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) -#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) -#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) -#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) -#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) -#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) -#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) -#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) -#define SSI2_PP_R (*((volatile uint32_t *)0x4000AFC0)) -#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) - -//***************************************************************************** -// -// SSI registers (SSI3) -// -//***************************************************************************** -#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) -#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) -#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) -#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) -#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) -#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) -#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) -#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) -#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) -#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) -#define SSI3_PP_R (*((volatile uint32_t *)0x4000BFC0)) -#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) - -//***************************************************************************** -// -// UART registers (UART0) -// -//***************************************************************************** -#define UART0_DR_R (*((volatile uint32_t *)0x4000C000)) -#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) -#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) -#define UART0_FR_R (*((volatile uint32_t *)0x4000C018)) -#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) -#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) -#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) -#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) -#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) -#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) -#define UART0_IM_R (*((volatile uint32_t *)0x4000C038)) -#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) -#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) -#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) -#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) -#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) -#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) -#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) -#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) - -//***************************************************************************** -// -// UART registers (UART1) -// -//***************************************************************************** -#define UART1_DR_R (*((volatile uint32_t *)0x4000D000)) -#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) -#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) -#define UART1_FR_R (*((volatile uint32_t *)0x4000D018)) -#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) -#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) -#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) -#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) -#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) -#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) -#define UART1_IM_R (*((volatile uint32_t *)0x4000D038)) -#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) -#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) -#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) -#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) -#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) -#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) -#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) -#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) - -//***************************************************************************** -// -// UART registers (UART2) -// -//***************************************************************************** -#define UART2_DR_R (*((volatile uint32_t *)0x4000E000)) -#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) -#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) -#define UART2_FR_R (*((volatile uint32_t *)0x4000E018)) -#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) -#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) -#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) -#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) -#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) -#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) -#define UART2_IM_R (*((volatile uint32_t *)0x4000E038)) -#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) -#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) -#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) -#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) -#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) -#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) -#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) -#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) - -//***************************************************************************** -// -// UART registers (UART3) -// -//***************************************************************************** -#define UART3_DR_R (*((volatile uint32_t *)0x4000F000)) -#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) -#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) -#define UART3_FR_R (*((volatile uint32_t *)0x4000F018)) -#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) -#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) -#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) -#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) -#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) -#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) -#define UART3_IM_R (*((volatile uint32_t *)0x4000F038)) -#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) -#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) -#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) -#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) -#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) -#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) -#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) -#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) - -//***************************************************************************** -// -// UART registers (UART4) -// -//***************************************************************************** -#define UART4_DR_R (*((volatile uint32_t *)0x40010000)) -#define UART4_RSR_R (*((volatile uint32_t *)0x40010004)) -#define UART4_ECR_R (*((volatile uint32_t *)0x40010004)) -#define UART4_FR_R (*((volatile uint32_t *)0x40010018)) -#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) -#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) -#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) -#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) -#define UART4_CTL_R (*((volatile uint32_t *)0x40010030)) -#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) -#define UART4_IM_R (*((volatile uint32_t *)0x40010038)) -#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) -#define UART4_MIS_R (*((volatile uint32_t *)0x40010040)) -#define UART4_ICR_R (*((volatile uint32_t *)0x40010044)) -#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) -#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) -#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) -#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) -#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) - -//***************************************************************************** -// -// UART registers (UART5) -// -//***************************************************************************** -#define UART5_DR_R (*((volatile uint32_t *)0x40011000)) -#define UART5_RSR_R (*((volatile uint32_t *)0x40011004)) -#define UART5_ECR_R (*((volatile uint32_t *)0x40011004)) -#define UART5_FR_R (*((volatile uint32_t *)0x40011018)) -#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) -#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) -#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) -#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) -#define UART5_CTL_R (*((volatile uint32_t *)0x40011030)) -#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) -#define UART5_IM_R (*((volatile uint32_t *)0x40011038)) -#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) -#define UART5_MIS_R (*((volatile uint32_t *)0x40011040)) -#define UART5_ICR_R (*((volatile uint32_t *)0x40011044)) -#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) -#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) -#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) -#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) -#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) - -//***************************************************************************** -// -// UART registers (UART6) -// -//***************************************************************************** -#define UART6_DR_R (*((volatile uint32_t *)0x40012000)) -#define UART6_RSR_R (*((volatile uint32_t *)0x40012004)) -#define UART6_ECR_R (*((volatile uint32_t *)0x40012004)) -#define UART6_FR_R (*((volatile uint32_t *)0x40012018)) -#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) -#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) -#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) -#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) -#define UART6_CTL_R (*((volatile uint32_t *)0x40012030)) -#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) -#define UART6_IM_R (*((volatile uint32_t *)0x40012038)) -#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) -#define UART6_MIS_R (*((volatile uint32_t *)0x40012040)) -#define UART6_ICR_R (*((volatile uint32_t *)0x40012044)) -#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) -#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) -#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) -#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) -#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) - -//***************************************************************************** -// -// UART registers (UART7) -// -//***************************************************************************** -#define UART7_DR_R (*((volatile uint32_t *)0x40013000)) -#define UART7_RSR_R (*((volatile uint32_t *)0x40013004)) -#define UART7_ECR_R (*((volatile uint32_t *)0x40013004)) -#define UART7_FR_R (*((volatile uint32_t *)0x40013018)) -#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) -#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) -#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) -#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) -#define UART7_CTL_R (*((volatile uint32_t *)0x40013030)) -#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) -#define UART7_IM_R (*((volatile uint32_t *)0x40013038)) -#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) -#define UART7_MIS_R (*((volatile uint32_t *)0x40013040)) -#define UART7_ICR_R (*((volatile uint32_t *)0x40013044)) -#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) -#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) -#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) -#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) -#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) - -//***************************************************************************** -// -// I2C registers (I2C0) -// -//***************************************************************************** -#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) -#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) -#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) -#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) -#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) -#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) -#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) -#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) -#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) -#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) -#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) -#define I2C0_MBLEN_R (*((volatile uint32_t *)0x40020030)) -#define I2C0_MBCNT_R (*((volatile uint32_t *)0x40020034)) -#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) -#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) -#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) -#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) -#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) -#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) -#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) -#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) -#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) -#define I2C0_FIFODATA_R (*((volatile uint32_t *)0x40020F00)) -#define I2C0_FIFOCTL_R (*((volatile uint32_t *)0x40020F04)) -#define I2C0_FIFOSTATUS_R (*((volatile uint32_t *)0x40020F08)) -#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) -#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) - -//***************************************************************************** -// -// I2C registers (I2C1) -// -//***************************************************************************** -#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) -#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) -#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) -#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) -#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) -#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) -#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) -#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) -#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) -#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) -#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) -#define I2C1_MBLEN_R (*((volatile uint32_t *)0x40021030)) -#define I2C1_MBCNT_R (*((volatile uint32_t *)0x40021034)) -#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) -#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) -#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) -#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) -#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) -#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) -#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) -#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) -#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) -#define I2C1_FIFODATA_R (*((volatile uint32_t *)0x40021F00)) -#define I2C1_FIFOCTL_R (*((volatile uint32_t *)0x40021F04)) -#define I2C1_FIFOSTATUS_R (*((volatile uint32_t *)0x40021F08)) -#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) -#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) - -//***************************************************************************** -// -// I2C registers (I2C2) -// -//***************************************************************************** -#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) -#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) -#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) -#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) -#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) -#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) -#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) -#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) -#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) -#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) -#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) -#define I2C2_MBLEN_R (*((volatile uint32_t *)0x40022030)) -#define I2C2_MBCNT_R (*((volatile uint32_t *)0x40022034)) -#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) -#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) -#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) -#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) -#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) -#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) -#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) -#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) -#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) -#define I2C2_FIFODATA_R (*((volatile uint32_t *)0x40022F00)) -#define I2C2_FIFOCTL_R (*((volatile uint32_t *)0x40022F04)) -#define I2C2_FIFOSTATUS_R (*((volatile uint32_t *)0x40022F08)) -#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) -#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) - -//***************************************************************************** -// -// I2C registers (I2C3) -// -//***************************************************************************** -#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) -#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) -#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) -#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) -#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) -#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) -#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) -#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) -#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) -#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) -#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) -#define I2C3_MBLEN_R (*((volatile uint32_t *)0x40023030)) -#define I2C3_MBCNT_R (*((volatile uint32_t *)0x40023034)) -#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) -#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) -#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) -#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) -#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) -#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) -#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) -#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) -#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) -#define I2C3_FIFODATA_R (*((volatile uint32_t *)0x40023F00)) -#define I2C3_FIFOCTL_R (*((volatile uint32_t *)0x40023F04)) -#define I2C3_FIFOSTATUS_R (*((volatile uint32_t *)0x40023F08)) -#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) -#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) - -//***************************************************************************** -// -// PWM registers (PWM0) -// -//***************************************************************************** -#define PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) -#define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) -#define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) -#define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) -#define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) -#define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) -#define PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) -#define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) -#define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) -#define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) -#define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) -#define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) -#define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) -#define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) -#define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) -#define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) -#define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) -#define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) -#define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) -#define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) -#define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) -#define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) -#define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) -#define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) -#define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) -#define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) -#define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) -#define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) -#define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) -#define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) -#define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) -#define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) -#define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) -#define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) -#define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) -#define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) -#define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) -#define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) -#define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) -#define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) -#define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) -#define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) -#define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) -#define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) -#define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) -#define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) -#define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) -#define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) -#define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) -#define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) -#define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) -#define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) -#define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) -#define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) -#define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) -#define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) -#define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) -#define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) -#define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) -#define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) -#define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) -#define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) -#define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) -#define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) -#define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) -#define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) -#define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) -#define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) -#define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) -#define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) -#define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) -#define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) -#define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) -#define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) -#define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) -#define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) -#define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) -#define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) -#define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) -#define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) -#define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) -#define PWM0_2_FLTSEN_R (*((volatile uint32_t *)0x40028900)) -#define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) -#define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) -#define PWM0_3_FLTSEN_R (*((volatile uint32_t *)0x40028980)) -#define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) -#define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) -#define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) -#define PWM0_CC_R (*((volatile uint32_t *)0x40028FC8)) - -//***************************************************************************** -// -// QEI registers (QEI0) -// -//***************************************************************************** -#define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) -#define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) -#define QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) -#define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) -#define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) -#define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) -#define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) -#define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) -#define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) -#define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) -#define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) - -//***************************************************************************** -// -// Timer registers (TIMER0) -// -//***************************************************************************** -#define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) -#define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) -#define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) -#define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) -#define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) -#define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) -#define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) -#define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) -#define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) -#define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) -#define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) -#define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) -#define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) -#define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) -#define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) -#define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) -#define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) -#define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) -#define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) -#define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) -#define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) -#define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) -#define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) -#define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) -#define TIMER0_DMAEV_R (*((volatile uint32_t *)0x4003006C)) -#define TIMER0_ADCEV_R (*((volatile uint32_t *)0x40030070)) -#define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) -#define TIMER0_CC_R (*((volatile uint32_t *)0x40030FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER1) -// -//***************************************************************************** -#define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) -#define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) -#define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) -#define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) -#define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) -#define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) -#define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) -#define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) -#define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) -#define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) -#define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) -#define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) -#define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) -#define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) -#define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) -#define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) -#define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) -#define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) -#define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) -#define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) -#define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) -#define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) -#define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) -#define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) -#define TIMER1_DMAEV_R (*((volatile uint32_t *)0x4003106C)) -#define TIMER1_ADCEV_R (*((volatile uint32_t *)0x40031070)) -#define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) -#define TIMER1_CC_R (*((volatile uint32_t *)0x40031FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER2) -// -//***************************************************************************** -#define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) -#define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) -#define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) -#define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) -#define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) -#define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) -#define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) -#define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) -#define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) -#define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) -#define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) -#define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) -#define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) -#define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) -#define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) -#define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) -#define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) -#define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) -#define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) -#define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) -#define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) -#define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) -#define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) -#define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) -#define TIMER2_DMAEV_R (*((volatile uint32_t *)0x4003206C)) -#define TIMER2_ADCEV_R (*((volatile uint32_t *)0x40032070)) -#define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) -#define TIMER2_CC_R (*((volatile uint32_t *)0x40032FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER3) -// -//***************************************************************************** -#define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) -#define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) -#define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) -#define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) -#define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) -#define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) -#define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) -#define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) -#define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) -#define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) -#define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) -#define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) -#define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) -#define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) -#define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) -#define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) -#define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) -#define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) -#define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) -#define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) -#define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) -#define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) -#define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) -#define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) -#define TIMER3_DMAEV_R (*((volatile uint32_t *)0x4003306C)) -#define TIMER3_ADCEV_R (*((volatile uint32_t *)0x40033070)) -#define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) -#define TIMER3_CC_R (*((volatile uint32_t *)0x40033FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER4) -// -//***************************************************************************** -#define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) -#define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) -#define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) -#define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) -#define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) -#define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) -#define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) -#define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) -#define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) -#define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) -#define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) -#define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) -#define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) -#define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) -#define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) -#define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) -#define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) -#define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) -#define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) -#define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) -#define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) -#define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) -#define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) -#define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) -#define TIMER4_DMAEV_R (*((volatile uint32_t *)0x4003406C)) -#define TIMER4_ADCEV_R (*((volatile uint32_t *)0x40034070)) -#define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) -#define TIMER4_CC_R (*((volatile uint32_t *)0x40034FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER5) -// -//***************************************************************************** -#define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) -#define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) -#define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) -#define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) -#define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) -#define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) -#define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) -#define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) -#define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) -#define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) -#define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) -#define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) -#define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) -#define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) -#define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) -#define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) -#define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) -#define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) -#define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) -#define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) -#define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) -#define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) -#define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) -#define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) -#define TIMER5_DMAEV_R (*((volatile uint32_t *)0x4003506C)) -#define TIMER5_ADCEV_R (*((volatile uint32_t *)0x40035070)) -#define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) -#define TIMER5_CC_R (*((volatile uint32_t *)0x40035FC8)) - -//***************************************************************************** -// -// ADC registers (ADC0) -// -//***************************************************************************** -#define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) -#define ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) -#define ADC0_IM_R (*((volatile uint32_t *)0x40038008)) -#define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) -#define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) -#define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) -#define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) -#define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) -#define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) -#define ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) -#define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) -#define ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) -#define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) -#define ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) -#define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) -#define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) -#define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) -#define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) -#define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) -#define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) -#define ADC0_SSEMUX0_R (*((volatile uint32_t *)0x40038058)) -#define ADC0_SSTSH0_R (*((volatile uint32_t *)0x4003805C)) -#define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) -#define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) -#define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) -#define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) -#define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) -#define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) -#define ADC0_SSEMUX1_R (*((volatile uint32_t *)0x40038078)) -#define ADC0_SSTSH1_R (*((volatile uint32_t *)0x4003807C)) -#define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) -#define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) -#define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) -#define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) -#define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) -#define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) -#define ADC0_SSEMUX2_R (*((volatile uint32_t *)0x40038098)) -#define ADC0_SSTSH2_R (*((volatile uint32_t *)0x4003809C)) -#define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) -#define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) -#define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) -#define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) -#define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) -#define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) -#define ADC0_SSEMUX3_R (*((volatile uint32_t *)0x400380B8)) -#define ADC0_SSTSH3_R (*((volatile uint32_t *)0x400380BC)) -#define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) -#define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) -#define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) -#define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) -#define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) -#define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) -#define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) -#define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) -#define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) -#define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) -#define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) -#define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) -#define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) -#define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) -#define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) -#define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) -#define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) -#define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) -#define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) -#define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) - -//***************************************************************************** -// -// ADC registers (ADC1) -// -//***************************************************************************** -#define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) -#define ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) -#define ADC1_IM_R (*((volatile uint32_t *)0x40039008)) -#define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) -#define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) -#define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) -#define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) -#define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) -#define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) -#define ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) -#define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) -#define ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) -#define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) -#define ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) -#define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) -#define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) -#define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) -#define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) -#define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) -#define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) -#define ADC1_SSEMUX0_R (*((volatile uint32_t *)0x40039058)) -#define ADC1_SSTSH0_R (*((volatile uint32_t *)0x4003905C)) -#define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) -#define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) -#define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) -#define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) -#define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) -#define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) -#define ADC1_SSEMUX1_R (*((volatile uint32_t *)0x40039078)) -#define ADC1_SSTSH1_R (*((volatile uint32_t *)0x4003907C)) -#define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) -#define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) -#define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) -#define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) -#define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) -#define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) -#define ADC1_SSEMUX2_R (*((volatile uint32_t *)0x40039098)) -#define ADC1_SSTSH2_R (*((volatile uint32_t *)0x4003909C)) -#define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) -#define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) -#define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) -#define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) -#define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) -#define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) -#define ADC1_SSEMUX3_R (*((volatile uint32_t *)0x400390B8)) -#define ADC1_SSTSH3_R (*((volatile uint32_t *)0x400390BC)) -#define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) -#define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) -#define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) -#define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) -#define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) -#define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) -#define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) -#define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) -#define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) -#define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) -#define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) -#define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) -#define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) -#define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) -#define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) -#define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) -#define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) -#define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) -#define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) -#define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) - -//***************************************************************************** -// -// Comparator registers (COMP) -// -//***************************************************************************** -#define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) -#define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) -#define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) -#define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) -#define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) -#define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) -#define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) -#define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) -#define COMP_ACSTAT2_R (*((volatile uint32_t *)0x4003C060)) -#define COMP_ACCTL2_R (*((volatile uint32_t *)0x4003C064)) -#define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) - -//***************************************************************************** -// -// CAN registers (CAN0) -// -//***************************************************************************** -#define CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) -#define CAN0_STS_R (*((volatile uint32_t *)0x40040004)) -#define CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) -#define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) -#define CAN0_INT_R (*((volatile uint32_t *)0x40040010)) -#define CAN0_TST_R (*((volatile uint32_t *)0x40040014)) -#define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) -#define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) -#define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) -#define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) -#define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) -#define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) -#define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) -#define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) -#define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) -#define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) -#define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) -#define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) -#define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) -#define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) -#define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) -#define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) -#define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) -#define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) -#define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) -#define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) -#define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) -#define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) -#define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) -#define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) -#define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) -#define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) -#define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) -#define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) -#define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) -#define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) -#define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) - -//***************************************************************************** -// -// CAN registers (CAN1) -// -//***************************************************************************** -#define CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) -#define CAN1_STS_R (*((volatile uint32_t *)0x40041004)) -#define CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) -#define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) -#define CAN1_INT_R (*((volatile uint32_t *)0x40041010)) -#define CAN1_TST_R (*((volatile uint32_t *)0x40041014)) -#define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) -#define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) -#define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) -#define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) -#define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) -#define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) -#define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) -#define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) -#define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) -#define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) -#define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) -#define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) -#define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) -#define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) -#define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) -#define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) -#define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) -#define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) -#define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) -#define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) -#define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) -#define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) -#define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) -#define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) -#define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) -#define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) -#define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) -#define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) -#define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) -#define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) -#define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) - -//***************************************************************************** -// -// Univeral Serial Bus registers (USB0) -// -//***************************************************************************** -#define USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) -#define USB0_POWER_R (*((volatile uint8_t *)0x40050001)) -#define USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) -#define USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) -#define USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) -#define USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) -#define USB0_IS_R (*((volatile uint8_t *)0x4005000A)) -#define USB0_IE_R (*((volatile uint8_t *)0x4005000B)) -#define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) -#define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) -#define USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) -#define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) -#define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) -#define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) -#define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) -#define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) -#define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) -#define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) -#define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) -#define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) -#define USB0_CCONF_R (*((volatile uint8_t *)0x40050061)) -#define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) -#define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) -#define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) -#define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) -#define USB0_ULPIVBUSCTL_R (*((volatile uint8_t *)0x40050070)) -#define USB0_ULPIREGDATA_R (*((volatile uint8_t *)0x40050074)) -#define USB0_ULPIREGADDR_R (*((volatile uint8_t *)0x40050075)) -#define USB0_ULPIREGCTL_R (*((volatile uint8_t *)0x40050076)) -#define USB0_EPINFO_R (*((volatile uint8_t *)0x40050078)) -#define USB0_RAMINFO_R (*((volatile uint8_t *)0x40050079)) -#define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) -#define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) -#define USB0_HSEOF_R (*((volatile uint8_t *)0x4005007C)) -#define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) -#define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) -#define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) -#define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) -#define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) -#define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) -#define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) -#define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) -#define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) -#define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) -#define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) -#define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) -#define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) -#define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) -#define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) -#define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) -#define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) -#define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) -#define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) -#define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) -#define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) -#define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) -#define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) -#define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) -#define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) -#define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) -#define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) -#define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) -#define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) -#define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) -#define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) -#define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) -#define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) -#define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) -#define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) -#define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) -#define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) -#define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) -#define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) -#define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) -#define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) -#define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) -#define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) -#define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) -#define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) -#define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) -#define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) -#define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) -#define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) -#define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) -#define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) -#define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) -#define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) -#define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) -#define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) -#define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) -#define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) -#define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) -#define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) -#define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) -#define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) -#define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) -#define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) -#define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) -#define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) -#define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) -#define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) -#define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) -#define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) -#define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) -#define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) -#define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) -#define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) -#define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) -#define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) -#define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) -#define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) -#define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) -#define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) -#define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) -#define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) -#define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) -#define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) -#define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) -#define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) -#define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) -#define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) -#define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) -#define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) -#define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) -#define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) -#define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) -#define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) -#define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) -#define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) -#define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) -#define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) -#define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) -#define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) -#define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) -#define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) -#define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) -#define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) -#define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) -#define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) -#define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) -#define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) -#define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) -#define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) -#define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) -#define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) -#define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) -#define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) -#define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) -#define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) -#define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) -#define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) -#define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) -#define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) -#define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) -#define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) -#define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) -#define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) -#define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) -#define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) -#define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) -#define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) -#define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) -#define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) -#define USB0_DMAINTR_R (*((volatile uint8_t *)0x40050200)) -#define USB0_DMACTL0_R (*((volatile uint16_t *)0x40050204)) -#define USB0_DMAADDR0_R (*((volatile uint32_t *)0x40050208)) -#define USB0_DMACOUNT0_R (*((volatile uint32_t *)0x4005020C)) -#define USB0_DMACTL1_R (*((volatile uint16_t *)0x40050214)) -#define USB0_DMAADDR1_R (*((volatile uint32_t *)0x40050218)) -#define USB0_DMACOUNT1_R (*((volatile uint32_t *)0x4005021C)) -#define USB0_DMACTL2_R (*((volatile uint16_t *)0x40050224)) -#define USB0_DMAADDR2_R (*((volatile uint32_t *)0x40050228)) -#define USB0_DMACOUNT2_R (*((volatile uint32_t *)0x4005022C)) -#define USB0_DMACTL3_R (*((volatile uint16_t *)0x40050234)) -#define USB0_DMAADDR3_R (*((volatile uint32_t *)0x40050238)) -#define USB0_DMACOUNT3_R (*((volatile uint32_t *)0x4005023C)) -#define USB0_DMACTL4_R (*((volatile uint16_t *)0x40050244)) -#define USB0_DMAADDR4_R (*((volatile uint32_t *)0x40050248)) -#define USB0_DMACOUNT4_R (*((volatile uint32_t *)0x4005024C)) -#define USB0_DMACTL5_R (*((volatile uint16_t *)0x40050254)) -#define USB0_DMAADDR5_R (*((volatile uint32_t *)0x40050258)) -#define USB0_DMACOUNT5_R (*((volatile uint32_t *)0x4005025C)) -#define USB0_DMACTL6_R (*((volatile uint16_t *)0x40050264)) -#define USB0_DMAADDR6_R (*((volatile uint32_t *)0x40050268)) -#define USB0_DMACOUNT6_R (*((volatile uint32_t *)0x4005026C)) -#define USB0_DMACTL7_R (*((volatile uint16_t *)0x40050274)) -#define USB0_DMAADDR7_R (*((volatile uint32_t *)0x40050278)) -#define USB0_DMACOUNT7_R (*((volatile uint32_t *)0x4005027C)) -#define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) -#define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) -#define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) -#define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) -#define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) -#define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) -#define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) -#define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) -#define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) -#define USB0_CTO_R (*((volatile uint16_t *)0x40050344)) -#define USB0_HHSRTN_R (*((volatile uint16_t *)0x40050346)) -#define USB0_HSBT_R (*((volatile uint16_t *)0x40050348)) -#define USB0_LPMATTR_R (*((volatile uint16_t *)0x40050360)) -#define USB0_LPMCNTRL_R (*((volatile uint8_t *)0x40050362)) -#define USB0_LPMIM_R (*((volatile uint8_t *)0x40050363)) -#define USB0_LPMRIS_R (*((volatile uint8_t *)0x40050364)) -#define USB0_LPMFADDR_R (*((volatile uint8_t *)0x40050365)) -#define USB0_EPC_R (*((volatile uint32_t *)0x40050400)) -#define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) -#define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) -#define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) -#define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) -#define USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) -#define USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) -#define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) -#define USB0_VDC_R (*((volatile uint32_t *)0x40050430)) -#define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) -#define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) -#define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) -#define USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) -#define USB0_PC_R (*((volatile uint32_t *)0x40050FC4)) -#define USB0_CC_R (*((volatile uint32_t *)0x40050FC8)) - -//***************************************************************************** -// -// GPIO registers (PORTA AHB) -// -//***************************************************************************** -#define GPIO_PORTA_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x40058000) -#define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) -#define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) -#define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) -#define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) -#define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) -#define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) -#define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) -#define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) -#define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) -#define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) -#define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) -#define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) -#define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) -#define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) -#define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) -#define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) -#define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) -#define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) -#define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) -#define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) -#define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) -#define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) -#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) -#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) -#define GPIO_PORTA_AHB_SI_R (*((volatile uint32_t *)0x40058538)) -#define GPIO_PORTA_AHB_DR12R_R (*((volatile uint32_t *)0x4005853C)) -#define GPIO_PORTA_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x40058540)) -#define GPIO_PORTA_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x40058544)) -#define GPIO_PORTA_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x40058548)) -#define GPIO_PORTA_AHB_PP_R (*((volatile uint32_t *)0x40058FC0)) -#define GPIO_PORTA_AHB_PC_R (*((volatile uint32_t *)0x40058FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTB AHB) -// -//***************************************************************************** -#define GPIO_PORTB_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x40059000) -#define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) -#define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) -#define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) -#define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) -#define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) -#define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) -#define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) -#define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) -#define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) -#define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) -#define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) -#define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) -#define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) -#define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) -#define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) -#define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) -#define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) -#define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) -#define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) -#define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) -#define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) -#define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) -#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) -#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) -#define GPIO_PORTB_AHB_SI_R (*((volatile uint32_t *)0x40059538)) -#define GPIO_PORTB_AHB_DR12R_R (*((volatile uint32_t *)0x4005953C)) -#define GPIO_PORTB_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x40059540)) -#define GPIO_PORTB_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x40059544)) -#define GPIO_PORTB_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x40059548)) -#define GPIO_PORTB_AHB_PP_R (*((volatile uint32_t *)0x40059FC0)) -#define GPIO_PORTB_AHB_PC_R (*((volatile uint32_t *)0x40059FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTC AHB) -// -//***************************************************************************** -#define GPIO_PORTC_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005A000) -#define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) -#define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) -#define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) -#define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) -#define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) -#define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) -#define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) -#define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) -#define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) -#define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) -#define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) -#define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) -#define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) -#define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) -#define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) -#define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) -#define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) -#define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) -#define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) -#define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) -#define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) -#define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) -#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) -#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) -#define GPIO_PORTC_AHB_SI_R (*((volatile uint32_t *)0x4005A538)) -#define GPIO_PORTC_AHB_DR12R_R (*((volatile uint32_t *)0x4005A53C)) -#define GPIO_PORTC_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005A540)) -#define GPIO_PORTC_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005A544)) -#define GPIO_PORTC_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005A548)) -#define GPIO_PORTC_AHB_PP_R (*((volatile uint32_t *)0x4005AFC0)) -#define GPIO_PORTC_AHB_PC_R (*((volatile uint32_t *)0x4005AFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTD AHB) -// -//***************************************************************************** -#define GPIO_PORTD_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005B000) -#define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) -#define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) -#define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) -#define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) -#define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) -#define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) -#define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) -#define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) -#define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) -#define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) -#define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) -#define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) -#define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) -#define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) -#define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) -#define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) -#define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) -#define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) -#define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) -#define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) -#define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) -#define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) -#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) -#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) -#define GPIO_PORTD_AHB_SI_R (*((volatile uint32_t *)0x4005B538)) -#define GPIO_PORTD_AHB_DR12R_R (*((volatile uint32_t *)0x4005B53C)) -#define GPIO_PORTD_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005B540)) -#define GPIO_PORTD_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005B544)) -#define GPIO_PORTD_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005B548)) -#define GPIO_PORTD_AHB_PP_R (*((volatile uint32_t *)0x4005BFC0)) -#define GPIO_PORTD_AHB_PC_R (*((volatile uint32_t *)0x4005BFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTE AHB) -// -//***************************************************************************** -#define GPIO_PORTE_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005C000) -#define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) -#define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) -#define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) -#define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) -#define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) -#define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) -#define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) -#define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) -#define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) -#define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) -#define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) -#define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) -#define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) -#define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) -#define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) -#define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) -#define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) -#define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) -#define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) -#define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) -#define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) -#define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) -#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) -#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) -#define GPIO_PORTE_AHB_SI_R (*((volatile uint32_t *)0x4005C538)) -#define GPIO_PORTE_AHB_DR12R_R (*((volatile uint32_t *)0x4005C53C)) -#define GPIO_PORTE_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005C540)) -#define GPIO_PORTE_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005C544)) -#define GPIO_PORTE_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005C548)) -#define GPIO_PORTE_AHB_PP_R (*((volatile uint32_t *)0x4005CFC0)) -#define GPIO_PORTE_AHB_PC_R (*((volatile uint32_t *)0x4005CFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTF AHB) -// -//***************************************************************************** -#define GPIO_PORTF_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005D000) -#define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) -#define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) -#define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) -#define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) -#define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) -#define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) -#define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) -#define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) -#define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) -#define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) -#define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) -#define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) -#define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) -#define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) -#define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) -#define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) -#define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) -#define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) -#define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) -#define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) -#define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) -#define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) -#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) -#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) -#define GPIO_PORTF_AHB_SI_R (*((volatile uint32_t *)0x4005D538)) -#define GPIO_PORTF_AHB_DR12R_R (*((volatile uint32_t *)0x4005D53C)) -#define GPIO_PORTF_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005D540)) -#define GPIO_PORTF_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005D544)) -#define GPIO_PORTF_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005D548)) -#define GPIO_PORTF_AHB_PP_R (*((volatile uint32_t *)0x4005DFC0)) -#define GPIO_PORTF_AHB_PC_R (*((volatile uint32_t *)0x4005DFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTG AHB) -// -//***************************************************************************** -#define GPIO_PORTG_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005E000) -#define GPIO_PORTG_AHB_DATA_R (*((volatile uint32_t *)0x4005E3FC)) -#define GPIO_PORTG_AHB_DIR_R (*((volatile uint32_t *)0x4005E400)) -#define GPIO_PORTG_AHB_IS_R (*((volatile uint32_t *)0x4005E404)) -#define GPIO_PORTG_AHB_IBE_R (*((volatile uint32_t *)0x4005E408)) -#define GPIO_PORTG_AHB_IEV_R (*((volatile uint32_t *)0x4005E40C)) -#define GPIO_PORTG_AHB_IM_R (*((volatile uint32_t *)0x4005E410)) -#define GPIO_PORTG_AHB_RIS_R (*((volatile uint32_t *)0x4005E414)) -#define GPIO_PORTG_AHB_MIS_R (*((volatile uint32_t *)0x4005E418)) -#define GPIO_PORTG_AHB_ICR_R (*((volatile uint32_t *)0x4005E41C)) -#define GPIO_PORTG_AHB_AFSEL_R (*((volatile uint32_t *)0x4005E420)) -#define GPIO_PORTG_AHB_DR2R_R (*((volatile uint32_t *)0x4005E500)) -#define GPIO_PORTG_AHB_DR4R_R (*((volatile uint32_t *)0x4005E504)) -#define GPIO_PORTG_AHB_DR8R_R (*((volatile uint32_t *)0x4005E508)) -#define GPIO_PORTG_AHB_ODR_R (*((volatile uint32_t *)0x4005E50C)) -#define GPIO_PORTG_AHB_PUR_R (*((volatile uint32_t *)0x4005E510)) -#define GPIO_PORTG_AHB_PDR_R (*((volatile uint32_t *)0x4005E514)) -#define GPIO_PORTG_AHB_SLR_R (*((volatile uint32_t *)0x4005E518)) -#define GPIO_PORTG_AHB_DEN_R (*((volatile uint32_t *)0x4005E51C)) -#define GPIO_PORTG_AHB_LOCK_R (*((volatile uint32_t *)0x4005E520)) -#define GPIO_PORTG_AHB_CR_R (*((volatile uint32_t *)0x4005E524)) -#define GPIO_PORTG_AHB_AMSEL_R (*((volatile uint32_t *)0x4005E528)) -#define GPIO_PORTG_AHB_PCTL_R (*((volatile uint32_t *)0x4005E52C)) -#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530)) -#define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534)) -#define GPIO_PORTG_AHB_SI_R (*((volatile uint32_t *)0x4005E538)) -#define GPIO_PORTG_AHB_DR12R_R (*((volatile uint32_t *)0x4005E53C)) -#define GPIO_PORTG_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005E540)) -#define GPIO_PORTG_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005E544)) -#define GPIO_PORTG_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005E548)) -#define GPIO_PORTG_AHB_PP_R (*((volatile uint32_t *)0x4005EFC0)) -#define GPIO_PORTG_AHB_PC_R (*((volatile uint32_t *)0x4005EFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTH AHB) -// -//***************************************************************************** -#define GPIO_PORTH_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x4005F000) -#define GPIO_PORTH_AHB_DATA_R (*((volatile uint32_t *)0x4005F3FC)) -#define GPIO_PORTH_AHB_DIR_R (*((volatile uint32_t *)0x4005F400)) -#define GPIO_PORTH_AHB_IS_R (*((volatile uint32_t *)0x4005F404)) -#define GPIO_PORTH_AHB_IBE_R (*((volatile uint32_t *)0x4005F408)) -#define GPIO_PORTH_AHB_IEV_R (*((volatile uint32_t *)0x4005F40C)) -#define GPIO_PORTH_AHB_IM_R (*((volatile uint32_t *)0x4005F410)) -#define GPIO_PORTH_AHB_RIS_R (*((volatile uint32_t *)0x4005F414)) -#define GPIO_PORTH_AHB_MIS_R (*((volatile uint32_t *)0x4005F418)) -#define GPIO_PORTH_AHB_ICR_R (*((volatile uint32_t *)0x4005F41C)) -#define GPIO_PORTH_AHB_AFSEL_R (*((volatile uint32_t *)0x4005F420)) -#define GPIO_PORTH_AHB_DR2R_R (*((volatile uint32_t *)0x4005F500)) -#define GPIO_PORTH_AHB_DR4R_R (*((volatile uint32_t *)0x4005F504)) -#define GPIO_PORTH_AHB_DR8R_R (*((volatile uint32_t *)0x4005F508)) -#define GPIO_PORTH_AHB_ODR_R (*((volatile uint32_t *)0x4005F50C)) -#define GPIO_PORTH_AHB_PUR_R (*((volatile uint32_t *)0x4005F510)) -#define GPIO_PORTH_AHB_PDR_R (*((volatile uint32_t *)0x4005F514)) -#define GPIO_PORTH_AHB_SLR_R (*((volatile uint32_t *)0x4005F518)) -#define GPIO_PORTH_AHB_DEN_R (*((volatile uint32_t *)0x4005F51C)) -#define GPIO_PORTH_AHB_LOCK_R (*((volatile uint32_t *)0x4005F520)) -#define GPIO_PORTH_AHB_CR_R (*((volatile uint32_t *)0x4005F524)) -#define GPIO_PORTH_AHB_AMSEL_R (*((volatile uint32_t *)0x4005F528)) -#define GPIO_PORTH_AHB_PCTL_R (*((volatile uint32_t *)0x4005F52C)) -#define GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530)) -#define GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534)) -#define GPIO_PORTH_AHB_SI_R (*((volatile uint32_t *)0x4005F538)) -#define GPIO_PORTH_AHB_DR12R_R (*((volatile uint32_t *)0x4005F53C)) -#define GPIO_PORTH_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x4005F540)) -#define GPIO_PORTH_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x4005F544)) -#define GPIO_PORTH_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x4005F548)) -#define GPIO_PORTH_AHB_PP_R (*((volatile uint32_t *)0x4005FFC0)) -#define GPIO_PORTH_AHB_PC_R (*((volatile uint32_t *)0x4005FFC4)) - -//***************************************************************************** -// -// GPIO registers (PORTJ AHB) -// -//***************************************************************************** -#define GPIO_PORTJ_AHB_DATA_BITS_R \ - ((volatile uint32_t *)0x40060000) -#define GPIO_PORTJ_AHB_DATA_R (*((volatile uint32_t *)0x400603FC)) -#define GPIO_PORTJ_AHB_DIR_R (*((volatile uint32_t *)0x40060400)) -#define GPIO_PORTJ_AHB_IS_R (*((volatile uint32_t *)0x40060404)) -#define GPIO_PORTJ_AHB_IBE_R (*((volatile uint32_t *)0x40060408)) -#define GPIO_PORTJ_AHB_IEV_R (*((volatile uint32_t *)0x4006040C)) -#define GPIO_PORTJ_AHB_IM_R (*((volatile uint32_t *)0x40060410)) -#define GPIO_PORTJ_AHB_RIS_R (*((volatile uint32_t *)0x40060414)) -#define GPIO_PORTJ_AHB_MIS_R (*((volatile uint32_t *)0x40060418)) -#define GPIO_PORTJ_AHB_ICR_R (*((volatile uint32_t *)0x4006041C)) -#define GPIO_PORTJ_AHB_AFSEL_R (*((volatile uint32_t *)0x40060420)) -#define GPIO_PORTJ_AHB_DR2R_R (*((volatile uint32_t *)0x40060500)) -#define GPIO_PORTJ_AHB_DR4R_R (*((volatile uint32_t *)0x40060504)) -#define GPIO_PORTJ_AHB_DR8R_R (*((volatile uint32_t *)0x40060508)) -#define GPIO_PORTJ_AHB_ODR_R (*((volatile uint32_t *)0x4006050C)) -#define GPIO_PORTJ_AHB_PUR_R (*((volatile uint32_t *)0x40060510)) -#define GPIO_PORTJ_AHB_PDR_R (*((volatile uint32_t *)0x40060514)) -#define GPIO_PORTJ_AHB_SLR_R (*((volatile uint32_t *)0x40060518)) -#define GPIO_PORTJ_AHB_DEN_R (*((volatile uint32_t *)0x4006051C)) -#define GPIO_PORTJ_AHB_LOCK_R (*((volatile uint32_t *)0x40060520)) -#define GPIO_PORTJ_AHB_CR_R (*((volatile uint32_t *)0x40060524)) -#define GPIO_PORTJ_AHB_AMSEL_R (*((volatile uint32_t *)0x40060528)) -#define GPIO_PORTJ_AHB_PCTL_R (*((volatile uint32_t *)0x4006052C)) -#define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530)) -#define GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534)) -#define GPIO_PORTJ_AHB_SI_R (*((volatile uint32_t *)0x40060538)) -#define GPIO_PORTJ_AHB_DR12R_R (*((volatile uint32_t *)0x4006053C)) -#define GPIO_PORTJ_AHB_WAKEPEN_R \ - (*((volatile uint32_t *)0x40060540)) -#define GPIO_PORTJ_AHB_WAKELVL_R \ - (*((volatile uint32_t *)0x40060544)) -#define GPIO_PORTJ_AHB_WAKESTAT_R \ - (*((volatile uint32_t *)0x40060548)) -#define GPIO_PORTJ_AHB_PP_R (*((volatile uint32_t *)0x40060FC0)) -#define GPIO_PORTJ_AHB_PC_R (*((volatile uint32_t *)0x40060FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTK) -// -//***************************************************************************** -#define GPIO_PORTK_DATA_BITS_R ((volatile uint32_t *)0x40061000) -#define GPIO_PORTK_DATA_R (*((volatile uint32_t *)0x400613FC)) -#define GPIO_PORTK_DIR_R (*((volatile uint32_t *)0x40061400)) -#define GPIO_PORTK_IS_R (*((volatile uint32_t *)0x40061404)) -#define GPIO_PORTK_IBE_R (*((volatile uint32_t *)0x40061408)) -#define GPIO_PORTK_IEV_R (*((volatile uint32_t *)0x4006140C)) -#define GPIO_PORTK_IM_R (*((volatile uint32_t *)0x40061410)) -#define GPIO_PORTK_RIS_R (*((volatile uint32_t *)0x40061414)) -#define GPIO_PORTK_MIS_R (*((volatile uint32_t *)0x40061418)) -#define GPIO_PORTK_ICR_R (*((volatile uint32_t *)0x4006141C)) -#define GPIO_PORTK_AFSEL_R (*((volatile uint32_t *)0x40061420)) -#define GPIO_PORTK_DR2R_R (*((volatile uint32_t *)0x40061500)) -#define GPIO_PORTK_DR4R_R (*((volatile uint32_t *)0x40061504)) -#define GPIO_PORTK_DR8R_R (*((volatile uint32_t *)0x40061508)) -#define GPIO_PORTK_ODR_R (*((volatile uint32_t *)0x4006150C)) -#define GPIO_PORTK_PUR_R (*((volatile uint32_t *)0x40061510)) -#define GPIO_PORTK_PDR_R (*((volatile uint32_t *)0x40061514)) -#define GPIO_PORTK_SLR_R (*((volatile uint32_t *)0x40061518)) -#define GPIO_PORTK_DEN_R (*((volatile uint32_t *)0x4006151C)) -#define GPIO_PORTK_LOCK_R (*((volatile uint32_t *)0x40061520)) -#define GPIO_PORTK_CR_R (*((volatile uint32_t *)0x40061524)) -#define GPIO_PORTK_AMSEL_R (*((volatile uint32_t *)0x40061528)) -#define GPIO_PORTK_PCTL_R (*((volatile uint32_t *)0x4006152C)) -#define GPIO_PORTK_ADCCTL_R (*((volatile uint32_t *)0x40061530)) -#define GPIO_PORTK_DMACTL_R (*((volatile uint32_t *)0x40061534)) -#define GPIO_PORTK_SI_R (*((volatile uint32_t *)0x40061538)) -#define GPIO_PORTK_DR12R_R (*((volatile uint32_t *)0x4006153C)) -#define GPIO_PORTK_WAKEPEN_R (*((volatile uint32_t *)0x40061540)) -#define GPIO_PORTK_WAKELVL_R (*((volatile uint32_t *)0x40061544)) -#define GPIO_PORTK_WAKESTAT_R (*((volatile uint32_t *)0x40061548)) -#define GPIO_PORTK_PP_R (*((volatile uint32_t *)0x40061FC0)) -#define GPIO_PORTK_PC_R (*((volatile uint32_t *)0x40061FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTL) -// -//***************************************************************************** -#define GPIO_PORTL_DATA_BITS_R ((volatile uint32_t *)0x40062000) -#define GPIO_PORTL_DATA_R (*((volatile uint32_t *)0x400623FC)) -#define GPIO_PORTL_DIR_R (*((volatile uint32_t *)0x40062400)) -#define GPIO_PORTL_IS_R (*((volatile uint32_t *)0x40062404)) -#define GPIO_PORTL_IBE_R (*((volatile uint32_t *)0x40062408)) -#define GPIO_PORTL_IEV_R (*((volatile uint32_t *)0x4006240C)) -#define GPIO_PORTL_IM_R (*((volatile uint32_t *)0x40062410)) -#define GPIO_PORTL_RIS_R (*((volatile uint32_t *)0x40062414)) -#define GPIO_PORTL_MIS_R (*((volatile uint32_t *)0x40062418)) -#define GPIO_PORTL_ICR_R (*((volatile uint32_t *)0x4006241C)) -#define GPIO_PORTL_AFSEL_R (*((volatile uint32_t *)0x40062420)) -#define GPIO_PORTL_DR2R_R (*((volatile uint32_t *)0x40062500)) -#define GPIO_PORTL_DR4R_R (*((volatile uint32_t *)0x40062504)) -#define GPIO_PORTL_DR8R_R (*((volatile uint32_t *)0x40062508)) -#define GPIO_PORTL_ODR_R (*((volatile uint32_t *)0x4006250C)) -#define GPIO_PORTL_PUR_R (*((volatile uint32_t *)0x40062510)) -#define GPIO_PORTL_PDR_R (*((volatile uint32_t *)0x40062514)) -#define GPIO_PORTL_SLR_R (*((volatile uint32_t *)0x40062518)) -#define GPIO_PORTL_DEN_R (*((volatile uint32_t *)0x4006251C)) -#define GPIO_PORTL_LOCK_R (*((volatile uint32_t *)0x40062520)) -#define GPIO_PORTL_CR_R (*((volatile uint32_t *)0x40062524)) -#define GPIO_PORTL_AMSEL_R (*((volatile uint32_t *)0x40062528)) -#define GPIO_PORTL_PCTL_R (*((volatile uint32_t *)0x4006252C)) -#define GPIO_PORTL_ADCCTL_R (*((volatile uint32_t *)0x40062530)) -#define GPIO_PORTL_DMACTL_R (*((volatile uint32_t *)0x40062534)) -#define GPIO_PORTL_SI_R (*((volatile uint32_t *)0x40062538)) -#define GPIO_PORTL_DR12R_R (*((volatile uint32_t *)0x4006253C)) -#define GPIO_PORTL_WAKEPEN_R (*((volatile uint32_t *)0x40062540)) -#define GPIO_PORTL_WAKELVL_R (*((volatile uint32_t *)0x40062544)) -#define GPIO_PORTL_WAKESTAT_R (*((volatile uint32_t *)0x40062548)) -#define GPIO_PORTL_PP_R (*((volatile uint32_t *)0x40062FC0)) -#define GPIO_PORTL_PC_R (*((volatile uint32_t *)0x40062FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTM) -// -//***************************************************************************** -#define GPIO_PORTM_DATA_BITS_R ((volatile uint32_t *)0x40063000) -#define GPIO_PORTM_DATA_R (*((volatile uint32_t *)0x400633FC)) -#define GPIO_PORTM_DIR_R (*((volatile uint32_t *)0x40063400)) -#define GPIO_PORTM_IS_R (*((volatile uint32_t *)0x40063404)) -#define GPIO_PORTM_IBE_R (*((volatile uint32_t *)0x40063408)) -#define GPIO_PORTM_IEV_R (*((volatile uint32_t *)0x4006340C)) -#define GPIO_PORTM_IM_R (*((volatile uint32_t *)0x40063410)) -#define GPIO_PORTM_RIS_R (*((volatile uint32_t *)0x40063414)) -#define GPIO_PORTM_MIS_R (*((volatile uint32_t *)0x40063418)) -#define GPIO_PORTM_ICR_R (*((volatile uint32_t *)0x4006341C)) -#define GPIO_PORTM_AFSEL_R (*((volatile uint32_t *)0x40063420)) -#define GPIO_PORTM_DR2R_R (*((volatile uint32_t *)0x40063500)) -#define GPIO_PORTM_DR4R_R (*((volatile uint32_t *)0x40063504)) -#define GPIO_PORTM_DR8R_R (*((volatile uint32_t *)0x40063508)) -#define GPIO_PORTM_ODR_R (*((volatile uint32_t *)0x4006350C)) -#define GPIO_PORTM_PUR_R (*((volatile uint32_t *)0x40063510)) -#define GPIO_PORTM_PDR_R (*((volatile uint32_t *)0x40063514)) -#define GPIO_PORTM_SLR_R (*((volatile uint32_t *)0x40063518)) -#define GPIO_PORTM_DEN_R (*((volatile uint32_t *)0x4006351C)) -#define GPIO_PORTM_LOCK_R (*((volatile uint32_t *)0x40063520)) -#define GPIO_PORTM_CR_R (*((volatile uint32_t *)0x40063524)) -#define GPIO_PORTM_AMSEL_R (*((volatile uint32_t *)0x40063528)) -#define GPIO_PORTM_PCTL_R (*((volatile uint32_t *)0x4006352C)) -#define GPIO_PORTM_ADCCTL_R (*((volatile uint32_t *)0x40063530)) -#define GPIO_PORTM_DMACTL_R (*((volatile uint32_t *)0x40063534)) -#define GPIO_PORTM_SI_R (*((volatile uint32_t *)0x40063538)) -#define GPIO_PORTM_DR12R_R (*((volatile uint32_t *)0x4006353C)) -#define GPIO_PORTM_WAKEPEN_R (*((volatile uint32_t *)0x40063540)) -#define GPIO_PORTM_WAKELVL_R (*((volatile uint32_t *)0x40063544)) -#define GPIO_PORTM_WAKESTAT_R (*((volatile uint32_t *)0x40063548)) -#define GPIO_PORTM_PP_R (*((volatile uint32_t *)0x40063FC0)) -#define GPIO_PORTM_PC_R (*((volatile uint32_t *)0x40063FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTN) -// -//***************************************************************************** -#define GPIO_PORTN_DATA_BITS_R ((volatile uint32_t *)0x40064000) -#define GPIO_PORTN_DATA_R (*((volatile uint32_t *)0x400643FC)) -#define GPIO_PORTN_DIR_R (*((volatile uint32_t *)0x40064400)) -#define GPIO_PORTN_IS_R (*((volatile uint32_t *)0x40064404)) -#define GPIO_PORTN_IBE_R (*((volatile uint32_t *)0x40064408)) -#define GPIO_PORTN_IEV_R (*((volatile uint32_t *)0x4006440C)) -#define GPIO_PORTN_IM_R (*((volatile uint32_t *)0x40064410)) -#define GPIO_PORTN_RIS_R (*((volatile uint32_t *)0x40064414)) -#define GPIO_PORTN_MIS_R (*((volatile uint32_t *)0x40064418)) -#define GPIO_PORTN_ICR_R (*((volatile uint32_t *)0x4006441C)) -#define GPIO_PORTN_AFSEL_R (*((volatile uint32_t *)0x40064420)) -#define GPIO_PORTN_DR2R_R (*((volatile uint32_t *)0x40064500)) -#define GPIO_PORTN_DR4R_R (*((volatile uint32_t *)0x40064504)) -#define GPIO_PORTN_DR8R_R (*((volatile uint32_t *)0x40064508)) -#define GPIO_PORTN_ODR_R (*((volatile uint32_t *)0x4006450C)) -#define GPIO_PORTN_PUR_R (*((volatile uint32_t *)0x40064510)) -#define GPIO_PORTN_PDR_R (*((volatile uint32_t *)0x40064514)) -#define GPIO_PORTN_SLR_R (*((volatile uint32_t *)0x40064518)) -#define GPIO_PORTN_DEN_R (*((volatile uint32_t *)0x4006451C)) -#define GPIO_PORTN_LOCK_R (*((volatile uint32_t *)0x40064520)) -#define GPIO_PORTN_CR_R (*((volatile uint32_t *)0x40064524)) -#define GPIO_PORTN_AMSEL_R (*((volatile uint32_t *)0x40064528)) -#define GPIO_PORTN_PCTL_R (*((volatile uint32_t *)0x4006452C)) -#define GPIO_PORTN_ADCCTL_R (*((volatile uint32_t *)0x40064530)) -#define GPIO_PORTN_DMACTL_R (*((volatile uint32_t *)0x40064534)) -#define GPIO_PORTN_SI_R (*((volatile uint32_t *)0x40064538)) -#define GPIO_PORTN_DR12R_R (*((volatile uint32_t *)0x4006453C)) -#define GPIO_PORTN_WAKEPEN_R (*((volatile uint32_t *)0x40064540)) -#define GPIO_PORTN_WAKELVL_R (*((volatile uint32_t *)0x40064544)) -#define GPIO_PORTN_WAKESTAT_R (*((volatile uint32_t *)0x40064548)) -#define GPIO_PORTN_PP_R (*((volatile uint32_t *)0x40064FC0)) -#define GPIO_PORTN_PC_R (*((volatile uint32_t *)0x40064FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTP) -// -//***************************************************************************** -#define GPIO_PORTP_DATA_BITS_R ((volatile uint32_t *)0x40065000) -#define GPIO_PORTP_DATA_R (*((volatile uint32_t *)0x400653FC)) -#define GPIO_PORTP_DIR_R (*((volatile uint32_t *)0x40065400)) -#define GPIO_PORTP_IS_R (*((volatile uint32_t *)0x40065404)) -#define GPIO_PORTP_IBE_R (*((volatile uint32_t *)0x40065408)) -#define GPIO_PORTP_IEV_R (*((volatile uint32_t *)0x4006540C)) -#define GPIO_PORTP_IM_R (*((volatile uint32_t *)0x40065410)) -#define GPIO_PORTP_RIS_R (*((volatile uint32_t *)0x40065414)) -#define GPIO_PORTP_MIS_R (*((volatile uint32_t *)0x40065418)) -#define GPIO_PORTP_ICR_R (*((volatile uint32_t *)0x4006541C)) -#define GPIO_PORTP_AFSEL_R (*((volatile uint32_t *)0x40065420)) -#define GPIO_PORTP_DR2R_R (*((volatile uint32_t *)0x40065500)) -#define GPIO_PORTP_DR4R_R (*((volatile uint32_t *)0x40065504)) -#define GPIO_PORTP_DR8R_R (*((volatile uint32_t *)0x40065508)) -#define GPIO_PORTP_ODR_R (*((volatile uint32_t *)0x4006550C)) -#define GPIO_PORTP_PUR_R (*((volatile uint32_t *)0x40065510)) -#define GPIO_PORTP_PDR_R (*((volatile uint32_t *)0x40065514)) -#define GPIO_PORTP_SLR_R (*((volatile uint32_t *)0x40065518)) -#define GPIO_PORTP_DEN_R (*((volatile uint32_t *)0x4006551C)) -#define GPIO_PORTP_LOCK_R (*((volatile uint32_t *)0x40065520)) -#define GPIO_PORTP_CR_R (*((volatile uint32_t *)0x40065524)) -#define GPIO_PORTP_AMSEL_R (*((volatile uint32_t *)0x40065528)) -#define GPIO_PORTP_PCTL_R (*((volatile uint32_t *)0x4006552C)) -#define GPIO_PORTP_ADCCTL_R (*((volatile uint32_t *)0x40065530)) -#define GPIO_PORTP_DMACTL_R (*((volatile uint32_t *)0x40065534)) -#define GPIO_PORTP_SI_R (*((volatile uint32_t *)0x40065538)) -#define GPIO_PORTP_DR12R_R (*((volatile uint32_t *)0x4006553C)) -#define GPIO_PORTP_WAKEPEN_R (*((volatile uint32_t *)0x40065540)) -#define GPIO_PORTP_WAKELVL_R (*((volatile uint32_t *)0x40065544)) -#define GPIO_PORTP_WAKESTAT_R (*((volatile uint32_t *)0x40065548)) -#define GPIO_PORTP_PP_R (*((volatile uint32_t *)0x40065FC0)) -#define GPIO_PORTP_PC_R (*((volatile uint32_t *)0x40065FC4)) - -//***************************************************************************** -// -// GPIO registers (PORTQ) -// -//***************************************************************************** -#define GPIO_PORTQ_DATA_BITS_R ((volatile uint32_t *)0x40066000) -#define GPIO_PORTQ_DATA_R (*((volatile uint32_t *)0x400663FC)) -#define GPIO_PORTQ_DIR_R (*((volatile uint32_t *)0x40066400)) -#define GPIO_PORTQ_IS_R (*((volatile uint32_t *)0x40066404)) -#define GPIO_PORTQ_IBE_R (*((volatile uint32_t *)0x40066408)) -#define GPIO_PORTQ_IEV_R (*((volatile uint32_t *)0x4006640C)) -#define GPIO_PORTQ_IM_R (*((volatile uint32_t *)0x40066410)) -#define GPIO_PORTQ_RIS_R (*((volatile uint32_t *)0x40066414)) -#define GPIO_PORTQ_MIS_R (*((volatile uint32_t *)0x40066418)) -#define GPIO_PORTQ_ICR_R (*((volatile uint32_t *)0x4006641C)) -#define GPIO_PORTQ_AFSEL_R (*((volatile uint32_t *)0x40066420)) -#define GPIO_PORTQ_DR2R_R (*((volatile uint32_t *)0x40066500)) -#define GPIO_PORTQ_DR4R_R (*((volatile uint32_t *)0x40066504)) -#define GPIO_PORTQ_DR8R_R (*((volatile uint32_t *)0x40066508)) -#define GPIO_PORTQ_ODR_R (*((volatile uint32_t *)0x4006650C)) -#define GPIO_PORTQ_PUR_R (*((volatile uint32_t *)0x40066510)) -#define GPIO_PORTQ_PDR_R (*((volatile uint32_t *)0x40066514)) -#define GPIO_PORTQ_SLR_R (*((volatile uint32_t *)0x40066518)) -#define GPIO_PORTQ_DEN_R (*((volatile uint32_t *)0x4006651C)) -#define GPIO_PORTQ_LOCK_R (*((volatile uint32_t *)0x40066520)) -#define GPIO_PORTQ_CR_R (*((volatile uint32_t *)0x40066524)) -#define GPIO_PORTQ_AMSEL_R (*((volatile uint32_t *)0x40066528)) -#define GPIO_PORTQ_PCTL_R (*((volatile uint32_t *)0x4006652C)) -#define GPIO_PORTQ_ADCCTL_R (*((volatile uint32_t *)0x40066530)) -#define GPIO_PORTQ_DMACTL_R (*((volatile uint32_t *)0x40066534)) -#define GPIO_PORTQ_SI_R (*((volatile uint32_t *)0x40066538)) -#define GPIO_PORTQ_DR12R_R (*((volatile uint32_t *)0x4006653C)) -#define GPIO_PORTQ_WAKEPEN_R (*((volatile uint32_t *)0x40066540)) -#define GPIO_PORTQ_WAKELVL_R (*((volatile uint32_t *)0x40066544)) -#define GPIO_PORTQ_WAKESTAT_R (*((volatile uint32_t *)0x40066548)) -#define GPIO_PORTQ_PP_R (*((volatile uint32_t *)0x40066FC0)) -#define GPIO_PORTQ_PC_R (*((volatile uint32_t *)0x40066FC4)) - -//***************************************************************************** -// -// EEPROM registers (EEPROM) -// -//***************************************************************************** -#define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) -#define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) -#define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) -#define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) -#define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) -#define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) -#define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) -#define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) -#define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) -#define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) -#define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) -#define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) -#define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) -#define EEPROM_EEHIDE0_R (*((volatile uint32_t *)0x400AF050)) -#define EEPROM_EEHIDE1_R (*((volatile uint32_t *)0x400AF054)) -#define EEPROM_EEHIDE2_R (*((volatile uint32_t *)0x400AF058)) -#define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) -#define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) - -//***************************************************************************** -// -// I2C registers (I2C8) -// -//***************************************************************************** -#define I2C8_MSA_R (*((volatile uint32_t *)0x400B8000)) -#define I2C8_MCS_R (*((volatile uint32_t *)0x400B8004)) -#define I2C8_MDR_R (*((volatile uint32_t *)0x400B8008)) -#define I2C8_MTPR_R (*((volatile uint32_t *)0x400B800C)) -#define I2C8_MIMR_R (*((volatile uint32_t *)0x400B8010)) -#define I2C8_MRIS_R (*((volatile uint32_t *)0x400B8014)) -#define I2C8_MMIS_R (*((volatile uint32_t *)0x400B8018)) -#define I2C8_MICR_R (*((volatile uint32_t *)0x400B801C)) -#define I2C8_MCR_R (*((volatile uint32_t *)0x400B8020)) -#define I2C8_MCLKOCNT_R (*((volatile uint32_t *)0x400B8024)) -#define I2C8_MBMON_R (*((volatile uint32_t *)0x400B802C)) -#define I2C8_MBLEN_R (*((volatile uint32_t *)0x400B8030)) -#define I2C8_MBCNT_R (*((volatile uint32_t *)0x400B8034)) -#define I2C8_SOAR_R (*((volatile uint32_t *)0x400B8800)) -#define I2C8_SCSR_R (*((volatile uint32_t *)0x400B8804)) -#define I2C8_SDR_R (*((volatile uint32_t *)0x400B8808)) -#define I2C8_SIMR_R (*((volatile uint32_t *)0x400B880C)) -#define I2C8_SRIS_R (*((volatile uint32_t *)0x400B8810)) -#define I2C8_SMIS_R (*((volatile uint32_t *)0x400B8814)) -#define I2C8_SICR_R (*((volatile uint32_t *)0x400B8818)) -#define I2C8_SOAR2_R (*((volatile uint32_t *)0x400B881C)) -#define I2C8_SACKCTL_R (*((volatile uint32_t *)0x400B8820)) -#define I2C8_FIFODATA_R (*((volatile uint32_t *)0x400B8F00)) -#define I2C8_FIFOCTL_R (*((volatile uint32_t *)0x400B8F04)) -#define I2C8_FIFOSTATUS_R (*((volatile uint32_t *)0x400B8F08)) -#define I2C8_PP_R (*((volatile uint32_t *)0x400B8FC0)) -#define I2C8_PC_R (*((volatile uint32_t *)0x400B8FC4)) - -//***************************************************************************** -// -// I2C registers (I2C9) -// -//***************************************************************************** -#define I2C9_MSA_R (*((volatile uint32_t *)0x400B9000)) -#define I2C9_MCS_R (*((volatile uint32_t *)0x400B9004)) -#define I2C9_MDR_R (*((volatile uint32_t *)0x400B9008)) -#define I2C9_MTPR_R (*((volatile uint32_t *)0x400B900C)) -#define I2C9_MIMR_R (*((volatile uint32_t *)0x400B9010)) -#define I2C9_MRIS_R (*((volatile uint32_t *)0x400B9014)) -#define I2C9_MMIS_R (*((volatile uint32_t *)0x400B9018)) -#define I2C9_MICR_R (*((volatile uint32_t *)0x400B901C)) -#define I2C9_MCR_R (*((volatile uint32_t *)0x400B9020)) -#define I2C9_MCLKOCNT_R (*((volatile uint32_t *)0x400B9024)) -#define I2C9_MBMON_R (*((volatile uint32_t *)0x400B902C)) -#define I2C9_MBLEN_R (*((volatile uint32_t *)0x400B9030)) -#define I2C9_MBCNT_R (*((volatile uint32_t *)0x400B9034)) -#define I2C9_SOAR_R (*((volatile uint32_t *)0x400B9800)) -#define I2C9_SCSR_R (*((volatile uint32_t *)0x400B9804)) -#define I2C9_SDR_R (*((volatile uint32_t *)0x400B9808)) -#define I2C9_SIMR_R (*((volatile uint32_t *)0x400B980C)) -#define I2C9_SRIS_R (*((volatile uint32_t *)0x400B9810)) -#define I2C9_SMIS_R (*((volatile uint32_t *)0x400B9814)) -#define I2C9_SICR_R (*((volatile uint32_t *)0x400B9818)) -#define I2C9_SOAR2_R (*((volatile uint32_t *)0x400B981C)) -#define I2C9_SACKCTL_R (*((volatile uint32_t *)0x400B9820)) -#define I2C9_FIFODATA_R (*((volatile uint32_t *)0x400B9F00)) -#define I2C9_FIFOCTL_R (*((volatile uint32_t *)0x400B9F04)) -#define I2C9_FIFOSTATUS_R (*((volatile uint32_t *)0x400B9F08)) -#define I2C9_PP_R (*((volatile uint32_t *)0x400B9FC0)) -#define I2C9_PC_R (*((volatile uint32_t *)0x400B9FC4)) - -//***************************************************************************** -// -// I2C registers (I2C4) -// -//***************************************************************************** -#define I2C4_MSA_R (*((volatile uint32_t *)0x400C0000)) -#define I2C4_MCS_R (*((volatile uint32_t *)0x400C0004)) -#define I2C4_MDR_R (*((volatile uint32_t *)0x400C0008)) -#define I2C4_MTPR_R (*((volatile uint32_t *)0x400C000C)) -#define I2C4_MIMR_R (*((volatile uint32_t *)0x400C0010)) -#define I2C4_MRIS_R (*((volatile uint32_t *)0x400C0014)) -#define I2C4_MMIS_R (*((volatile uint32_t *)0x400C0018)) -#define I2C4_MICR_R (*((volatile uint32_t *)0x400C001C)) -#define I2C4_MCR_R (*((volatile uint32_t *)0x400C0020)) -#define I2C4_MCLKOCNT_R (*((volatile uint32_t *)0x400C0024)) -#define I2C4_MBMON_R (*((volatile uint32_t *)0x400C002C)) -#define I2C4_MBLEN_R (*((volatile uint32_t *)0x400C0030)) -#define I2C4_MBCNT_R (*((volatile uint32_t *)0x400C0034)) -#define I2C4_SOAR_R (*((volatile uint32_t *)0x400C0800)) -#define I2C4_SCSR_R (*((volatile uint32_t *)0x400C0804)) -#define I2C4_SDR_R (*((volatile uint32_t *)0x400C0808)) -#define I2C4_SIMR_R (*((volatile uint32_t *)0x400C080C)) -#define I2C4_SRIS_R (*((volatile uint32_t *)0x400C0810)) -#define I2C4_SMIS_R (*((volatile uint32_t *)0x400C0814)) -#define I2C4_SICR_R (*((volatile uint32_t *)0x400C0818)) -#define I2C4_SOAR2_R (*((volatile uint32_t *)0x400C081C)) -#define I2C4_SACKCTL_R (*((volatile uint32_t *)0x400C0820)) -#define I2C4_FIFODATA_R (*((volatile uint32_t *)0x400C0F00)) -#define I2C4_FIFOCTL_R (*((volatile uint32_t *)0x400C0F04)) -#define I2C4_FIFOSTATUS_R (*((volatile uint32_t *)0x400C0F08)) -#define I2C4_PP_R (*((volatile uint32_t *)0x400C0FC0)) -#define I2C4_PC_R (*((volatile uint32_t *)0x400C0FC4)) - -//***************************************************************************** -// -// I2C registers (I2C5) -// -//***************************************************************************** -#define I2C5_MSA_R (*((volatile uint32_t *)0x400C1000)) -#define I2C5_MCS_R (*((volatile uint32_t *)0x400C1004)) -#define I2C5_MDR_R (*((volatile uint32_t *)0x400C1008)) -#define I2C5_MTPR_R (*((volatile uint32_t *)0x400C100C)) -#define I2C5_MIMR_R (*((volatile uint32_t *)0x400C1010)) -#define I2C5_MRIS_R (*((volatile uint32_t *)0x400C1014)) -#define I2C5_MMIS_R (*((volatile uint32_t *)0x400C1018)) -#define I2C5_MICR_R (*((volatile uint32_t *)0x400C101C)) -#define I2C5_MCR_R (*((volatile uint32_t *)0x400C1020)) -#define I2C5_MCLKOCNT_R (*((volatile uint32_t *)0x400C1024)) -#define I2C5_MBMON_R (*((volatile uint32_t *)0x400C102C)) -#define I2C5_MBLEN_R (*((volatile uint32_t *)0x400C1030)) -#define I2C5_MBCNT_R (*((volatile uint32_t *)0x400C1034)) -#define I2C5_SOAR_R (*((volatile uint32_t *)0x400C1800)) -#define I2C5_SCSR_R (*((volatile uint32_t *)0x400C1804)) -#define I2C5_SDR_R (*((volatile uint32_t *)0x400C1808)) -#define I2C5_SIMR_R (*((volatile uint32_t *)0x400C180C)) -#define I2C5_SRIS_R (*((volatile uint32_t *)0x400C1810)) -#define I2C5_SMIS_R (*((volatile uint32_t *)0x400C1814)) -#define I2C5_SICR_R (*((volatile uint32_t *)0x400C1818)) -#define I2C5_SOAR2_R (*((volatile uint32_t *)0x400C181C)) -#define I2C5_SACKCTL_R (*((volatile uint32_t *)0x400C1820)) -#define I2C5_FIFODATA_R (*((volatile uint32_t *)0x400C1F00)) -#define I2C5_FIFOCTL_R (*((volatile uint32_t *)0x400C1F04)) -#define I2C5_FIFOSTATUS_R (*((volatile uint32_t *)0x400C1F08)) -#define I2C5_PP_R (*((volatile uint32_t *)0x400C1FC0)) -#define I2C5_PC_R (*((volatile uint32_t *)0x400C1FC4)) - -//***************************************************************************** -// -// I2C registers (I2C6) -// -//***************************************************************************** -#define I2C6_MSA_R (*((volatile uint32_t *)0x400C2000)) -#define I2C6_MCS_R (*((volatile uint32_t *)0x400C2004)) -#define I2C6_MDR_R (*((volatile uint32_t *)0x400C2008)) -#define I2C6_MTPR_R (*((volatile uint32_t *)0x400C200C)) -#define I2C6_MIMR_R (*((volatile uint32_t *)0x400C2010)) -#define I2C6_MRIS_R (*((volatile uint32_t *)0x400C2014)) -#define I2C6_MMIS_R (*((volatile uint32_t *)0x400C2018)) -#define I2C6_MICR_R (*((volatile uint32_t *)0x400C201C)) -#define I2C6_MCR_R (*((volatile uint32_t *)0x400C2020)) -#define I2C6_MCLKOCNT_R (*((volatile uint32_t *)0x400C2024)) -#define I2C6_MBMON_R (*((volatile uint32_t *)0x400C202C)) -#define I2C6_MBLEN_R (*((volatile uint32_t *)0x400C2030)) -#define I2C6_MBCNT_R (*((volatile uint32_t *)0x400C2034)) -#define I2C6_SOAR_R (*((volatile uint32_t *)0x400C2800)) -#define I2C6_SCSR_R (*((volatile uint32_t *)0x400C2804)) -#define I2C6_SDR_R (*((volatile uint32_t *)0x400C2808)) -#define I2C6_SIMR_R (*((volatile uint32_t *)0x400C280C)) -#define I2C6_SRIS_R (*((volatile uint32_t *)0x400C2810)) -#define I2C6_SMIS_R (*((volatile uint32_t *)0x400C2814)) -#define I2C6_SICR_R (*((volatile uint32_t *)0x400C2818)) -#define I2C6_SOAR2_R (*((volatile uint32_t *)0x400C281C)) -#define I2C6_SACKCTL_R (*((volatile uint32_t *)0x400C2820)) -#define I2C6_FIFODATA_R (*((volatile uint32_t *)0x400C2F00)) -#define I2C6_FIFOCTL_R (*((volatile uint32_t *)0x400C2F04)) -#define I2C6_FIFOSTATUS_R (*((volatile uint32_t *)0x400C2F08)) -#define I2C6_PP_R (*((volatile uint32_t *)0x400C2FC0)) -#define I2C6_PC_R (*((volatile uint32_t *)0x400C2FC4)) - -//***************************************************************************** -// -// I2C registers (I2C7) -// -//***************************************************************************** -#define I2C7_MSA_R (*((volatile uint32_t *)0x400C3000)) -#define I2C7_MCS_R (*((volatile uint32_t *)0x400C3004)) -#define I2C7_MDR_R (*((volatile uint32_t *)0x400C3008)) -#define I2C7_MTPR_R (*((volatile uint32_t *)0x400C300C)) -#define I2C7_MIMR_R (*((volatile uint32_t *)0x400C3010)) -#define I2C7_MRIS_R (*((volatile uint32_t *)0x400C3014)) -#define I2C7_MMIS_R (*((volatile uint32_t *)0x400C3018)) -#define I2C7_MICR_R (*((volatile uint32_t *)0x400C301C)) -#define I2C7_MCR_R (*((volatile uint32_t *)0x400C3020)) -#define I2C7_MCLKOCNT_R (*((volatile uint32_t *)0x400C3024)) -#define I2C7_MBMON_R (*((volatile uint32_t *)0x400C302C)) -#define I2C7_MBLEN_R (*((volatile uint32_t *)0x400C3030)) -#define I2C7_MBCNT_R (*((volatile uint32_t *)0x400C3034)) -#define I2C7_SOAR_R (*((volatile uint32_t *)0x400C3800)) -#define I2C7_SCSR_R (*((volatile uint32_t *)0x400C3804)) -#define I2C7_SDR_R (*((volatile uint32_t *)0x400C3808)) -#define I2C7_SIMR_R (*((volatile uint32_t *)0x400C380C)) -#define I2C7_SRIS_R (*((volatile uint32_t *)0x400C3810)) -#define I2C7_SMIS_R (*((volatile uint32_t *)0x400C3814)) -#define I2C7_SICR_R (*((volatile uint32_t *)0x400C3818)) -#define I2C7_SOAR2_R (*((volatile uint32_t *)0x400C381C)) -#define I2C7_SACKCTL_R (*((volatile uint32_t *)0x400C3820)) -#define I2C7_FIFODATA_R (*((volatile uint32_t *)0x400C3F00)) -#define I2C7_FIFOCTL_R (*((volatile uint32_t *)0x400C3F04)) -#define I2C7_FIFOSTATUS_R (*((volatile uint32_t *)0x400C3F08)) -#define I2C7_PP_R (*((volatile uint32_t *)0x400C3FC0)) -#define I2C7_PC_R (*((volatile uint32_t *)0x400C3FC4)) - -//***************************************************************************** -// -// External Peripheral Interface registers (EPI0) -// -//***************************************************************************** -#define EPI0_CFG_R (*((volatile uint32_t *)0x400D0000)) -#define EPI0_BAUD_R (*((volatile uint32_t *)0x400D0004)) -#define EPI0_BAUD2_R (*((volatile uint32_t *)0x400D0008)) -#define EPI0_HB16CFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_GPCFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_SDRAMCFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_HB8CFG_R (*((volatile uint32_t *)0x400D0010)) -#define EPI0_HB8CFG2_R (*((volatile uint32_t *)0x400D0014)) -#define EPI0_HB16CFG2_R (*((volatile uint32_t *)0x400D0014)) -#define EPI0_ADDRMAP_R (*((volatile uint32_t *)0x400D001C)) -#define EPI0_RSIZE0_R (*((volatile uint32_t *)0x400D0020)) -#define EPI0_RADDR0_R (*((volatile uint32_t *)0x400D0024)) -#define EPI0_RPSTD0_R (*((volatile uint32_t *)0x400D0028)) -#define EPI0_RSIZE1_R (*((volatile uint32_t *)0x400D0030)) -#define EPI0_RADDR1_R (*((volatile uint32_t *)0x400D0034)) -#define EPI0_RPSTD1_R (*((volatile uint32_t *)0x400D0038)) -#define EPI0_STAT_R (*((volatile uint32_t *)0x400D0060)) -#define EPI0_RFIFOCNT_R (*((volatile uint32_t *)0x400D006C)) -#define EPI0_READFIFO0_R (*((volatile uint32_t *)0x400D0070)) -#define EPI0_READFIFO1_R (*((volatile uint32_t *)0x400D0074)) -#define EPI0_READFIFO2_R (*((volatile uint32_t *)0x400D0078)) -#define EPI0_READFIFO3_R (*((volatile uint32_t *)0x400D007C)) -#define EPI0_READFIFO4_R (*((volatile uint32_t *)0x400D0080)) -#define EPI0_READFIFO5_R (*((volatile uint32_t *)0x400D0084)) -#define EPI0_READFIFO6_R (*((volatile uint32_t *)0x400D0088)) -#define EPI0_READFIFO7_R (*((volatile uint32_t *)0x400D008C)) -#define EPI0_FIFOLVL_R (*((volatile uint32_t *)0x400D0200)) -#define EPI0_WFIFOCNT_R (*((volatile uint32_t *)0x400D0204)) -#define EPI0_DMATXCNT_R (*((volatile uint32_t *)0x400D0208)) -#define EPI0_IM_R (*((volatile uint32_t *)0x400D0210)) -#define EPI0_RIS_R (*((volatile uint32_t *)0x400D0214)) -#define EPI0_MIS_R (*((volatile uint32_t *)0x400D0218)) -#define EPI0_EISC_R (*((volatile uint32_t *)0x400D021C)) -#define EPI0_HB8CFG3_R (*((volatile uint32_t *)0x400D0308)) -#define EPI0_HB16CFG3_R (*((volatile uint32_t *)0x400D0308)) -#define EPI0_HB16CFG4_R (*((volatile uint32_t *)0x400D030C)) -#define EPI0_HB8CFG4_R (*((volatile uint32_t *)0x400D030C)) -#define EPI0_HB8TIME_R (*((volatile uint32_t *)0x400D0310)) -#define EPI0_HB16TIME_R (*((volatile uint32_t *)0x400D0310)) -#define EPI0_HB8TIME2_R (*((volatile uint32_t *)0x400D0314)) -#define EPI0_HB16TIME2_R (*((volatile uint32_t *)0x400D0314)) -#define EPI0_HB16TIME3_R (*((volatile uint32_t *)0x400D0318)) -#define EPI0_HB8TIME3_R (*((volatile uint32_t *)0x400D0318)) -#define EPI0_HB8TIME4_R (*((volatile uint32_t *)0x400D031C)) -#define EPI0_HB16TIME4_R (*((volatile uint32_t *)0x400D031C)) -#define EPI0_HBPSRAM_R (*((volatile uint32_t *)0x400D0360)) - -//***************************************************************************** -// -// Timer registers (TIMER6) -// -//***************************************************************************** -#define TIMER6_CFG_R (*((volatile uint32_t *)0x400E0000)) -#define TIMER6_TAMR_R (*((volatile uint32_t *)0x400E0004)) -#define TIMER6_TBMR_R (*((volatile uint32_t *)0x400E0008)) -#define TIMER6_CTL_R (*((volatile uint32_t *)0x400E000C)) -#define TIMER6_SYNC_R (*((volatile uint32_t *)0x400E0010)) -#define TIMER6_IMR_R (*((volatile uint32_t *)0x400E0018)) -#define TIMER6_RIS_R (*((volatile uint32_t *)0x400E001C)) -#define TIMER6_MIS_R (*((volatile uint32_t *)0x400E0020)) -#define TIMER6_ICR_R (*((volatile uint32_t *)0x400E0024)) -#define TIMER6_TAILR_R (*((volatile uint32_t *)0x400E0028)) -#define TIMER6_TBILR_R (*((volatile uint32_t *)0x400E002C)) -#define TIMER6_TAMATCHR_R (*((volatile uint32_t *)0x400E0030)) -#define TIMER6_TBMATCHR_R (*((volatile uint32_t *)0x400E0034)) -#define TIMER6_TAPR_R (*((volatile uint32_t *)0x400E0038)) -#define TIMER6_TBPR_R (*((volatile uint32_t *)0x400E003C)) -#define TIMER6_TAPMR_R (*((volatile uint32_t *)0x400E0040)) -#define TIMER6_TBPMR_R (*((volatile uint32_t *)0x400E0044)) -#define TIMER6_TAR_R (*((volatile uint32_t *)0x400E0048)) -#define TIMER6_TBR_R (*((volatile uint32_t *)0x400E004C)) -#define TIMER6_TAV_R (*((volatile uint32_t *)0x400E0050)) -#define TIMER6_TBV_R (*((volatile uint32_t *)0x400E0054)) -#define TIMER6_RTCPD_R (*((volatile uint32_t *)0x400E0058)) -#define TIMER6_TAPS_R (*((volatile uint32_t *)0x400E005C)) -#define TIMER6_TBPS_R (*((volatile uint32_t *)0x400E0060)) -#define TIMER6_DMAEV_R (*((volatile uint32_t *)0x400E006C)) -#define TIMER6_ADCEV_R (*((volatile uint32_t *)0x400E0070)) -#define TIMER6_PP_R (*((volatile uint32_t *)0x400E0FC0)) -#define TIMER6_CC_R (*((volatile uint32_t *)0x400E0FC8)) - -//***************************************************************************** -// -// Timer registers (TIMER7) -// -//***************************************************************************** -#define TIMER7_CFG_R (*((volatile uint32_t *)0x400E1000)) -#define TIMER7_TAMR_R (*((volatile uint32_t *)0x400E1004)) -#define TIMER7_TBMR_R (*((volatile uint32_t *)0x400E1008)) -#define TIMER7_CTL_R (*((volatile uint32_t *)0x400E100C)) -#define TIMER7_SYNC_R (*((volatile uint32_t *)0x400E1010)) -#define TIMER7_IMR_R (*((volatile uint32_t *)0x400E1018)) -#define TIMER7_RIS_R (*((volatile uint32_t *)0x400E101C)) -#define TIMER7_MIS_R (*((volatile uint32_t *)0x400E1020)) -#define TIMER7_ICR_R (*((volatile uint32_t *)0x400E1024)) -#define TIMER7_TAILR_R (*((volatile uint32_t *)0x400E1028)) -#define TIMER7_TBILR_R (*((volatile uint32_t *)0x400E102C)) -#define TIMER7_TAMATCHR_R (*((volatile uint32_t *)0x400E1030)) -#define TIMER7_TBMATCHR_R (*((volatile uint32_t *)0x400E1034)) -#define TIMER7_TAPR_R (*((volatile uint32_t *)0x400E1038)) -#define TIMER7_TBPR_R (*((volatile uint32_t *)0x400E103C)) -#define TIMER7_TAPMR_R (*((volatile uint32_t *)0x400E1040)) -#define TIMER7_TBPMR_R (*((volatile uint32_t *)0x400E1044)) -#define TIMER7_TAR_R (*((volatile uint32_t *)0x400E1048)) -#define TIMER7_TBR_R (*((volatile uint32_t *)0x400E104C)) -#define TIMER7_TAV_R (*((volatile uint32_t *)0x400E1050)) -#define TIMER7_TBV_R (*((volatile uint32_t *)0x400E1054)) -#define TIMER7_RTCPD_R (*((volatile uint32_t *)0x400E1058)) -#define TIMER7_TAPS_R (*((volatile uint32_t *)0x400E105C)) -#define TIMER7_TBPS_R (*((volatile uint32_t *)0x400E1060)) -#define TIMER7_DMAEV_R (*((volatile uint32_t *)0x400E106C)) -#define TIMER7_ADCEV_R (*((volatile uint32_t *)0x400E1070)) -#define TIMER7_PP_R (*((volatile uint32_t *)0x400E1FC0)) -#define TIMER7_CC_R (*((volatile uint32_t *)0x400E1FC8)) - -//***************************************************************************** -// -// EMAC registers (EMAC0) -// -//***************************************************************************** -#define EMAC0_CFG_R (*((volatile uint32_t *)0x400EC000)) -#define EMAC0_FRAMEFLTR_R (*((volatile uint32_t *)0x400EC004)) -#define EMAC0_HASHTBLH_R (*((volatile uint32_t *)0x400EC008)) -#define EMAC0_HASHTBLL_R (*((volatile uint32_t *)0x400EC00C)) -#define EMAC0_MIIADDR_R (*((volatile uint32_t *)0x400EC010)) -#define EMAC0_MIIDATA_R (*((volatile uint32_t *)0x400EC014)) -#define EMAC0_FLOWCTL_R (*((volatile uint32_t *)0x400EC018)) -#define EMAC0_VLANTG_R (*((volatile uint32_t *)0x400EC01C)) -#define EMAC0_STATUS_R (*((volatile uint32_t *)0x400EC024)) -#define EMAC0_RWUFF_R (*((volatile uint32_t *)0x400EC028)) -#define EMAC0_PMTCTLSTAT_R (*((volatile uint32_t *)0x400EC02C)) -#define EMAC0_RIS_R (*((volatile uint32_t *)0x400EC038)) -#define EMAC0_IM_R (*((volatile uint32_t *)0x400EC03C)) -#define EMAC0_ADDR0H_R (*((volatile uint32_t *)0x400EC040)) -#define EMAC0_ADDR0L_R (*((volatile uint32_t *)0x400EC044)) -#define EMAC0_ADDR1H_R (*((volatile uint32_t *)0x400EC048)) -#define EMAC0_ADDR1L_R (*((volatile uint32_t *)0x400EC04C)) -#define EMAC0_ADDR2H_R (*((volatile uint32_t *)0x400EC050)) -#define EMAC0_ADDR2L_R (*((volatile uint32_t *)0x400EC054)) -#define EMAC0_ADDR3H_R (*((volatile uint32_t *)0x400EC058)) -#define EMAC0_ADDR3L_R (*((volatile uint32_t *)0x400EC05C)) -#define EMAC0_WDOGTO_R (*((volatile uint32_t *)0x400EC0DC)) -#define EMAC0_MMCCTRL_R (*((volatile uint32_t *)0x400EC100)) -#define EMAC0_MMCRXRIS_R (*((volatile uint32_t *)0x400EC104)) -#define EMAC0_MMCTXRIS_R (*((volatile uint32_t *)0x400EC108)) -#define EMAC0_MMCRXIM_R (*((volatile uint32_t *)0x400EC10C)) -#define EMAC0_MMCTXIM_R (*((volatile uint32_t *)0x400EC110)) -#define EMAC0_TXCNTGB_R (*((volatile uint32_t *)0x400EC118)) -#define EMAC0_TXCNTSCOL_R (*((volatile uint32_t *)0x400EC14C)) -#define EMAC0_TXCNTMCOL_R (*((volatile uint32_t *)0x400EC150)) -#define EMAC0_TXOCTCNTG_R (*((volatile uint32_t *)0x400EC164)) -#define EMAC0_RXCNTGB_R (*((volatile uint32_t *)0x400EC180)) -#define EMAC0_RXCNTCRCERR_R (*((volatile uint32_t *)0x400EC194)) -#define EMAC0_RXCNTALGNERR_R (*((volatile uint32_t *)0x400EC198)) -#define EMAC0_RXCNTGUNI_R (*((volatile uint32_t *)0x400EC1C4)) -#define EMAC0_VLNINCREP_R (*((volatile uint32_t *)0x400EC584)) -#define EMAC0_VLANHASH_R (*((volatile uint32_t *)0x400EC588)) -#define EMAC0_TIMSTCTRL_R (*((volatile uint32_t *)0x400EC700)) -#define EMAC0_SUBSECINC_R (*((volatile uint32_t *)0x400EC704)) -#define EMAC0_TIMSEC_R (*((volatile uint32_t *)0x400EC708)) -#define EMAC0_TIMNANO_R (*((volatile uint32_t *)0x400EC70C)) -#define EMAC0_TIMSECU_R (*((volatile uint32_t *)0x400EC710)) -#define EMAC0_TIMNANOU_R (*((volatile uint32_t *)0x400EC714)) -#define EMAC0_TIMADD_R (*((volatile uint32_t *)0x400EC718)) -#define EMAC0_TARGSEC_R (*((volatile uint32_t *)0x400EC71C)) -#define EMAC0_TARGNANO_R (*((volatile uint32_t *)0x400EC720)) -#define EMAC0_HWORDSEC_R (*((volatile uint32_t *)0x400EC724)) -#define EMAC0_TIMSTAT_R (*((volatile uint32_t *)0x400EC728)) -#define EMAC0_PPSCTRL_R (*((volatile uint32_t *)0x400EC72C)) -#define EMAC0_PPS0INTVL_R (*((volatile uint32_t *)0x400EC760)) -#define EMAC0_PPS0WIDTH_R (*((volatile uint32_t *)0x400EC764)) -#define EMAC0_DMABUSMOD_R (*((volatile uint32_t *)0x400ECC00)) -#define EMAC0_TXPOLLD_R (*((volatile uint32_t *)0x400ECC04)) -#define EMAC0_RXPOLLD_R (*((volatile uint32_t *)0x400ECC08)) -#define EMAC0_RXDLADDR_R (*((volatile uint32_t *)0x400ECC0C)) -#define EMAC0_TXDLADDR_R (*((volatile uint32_t *)0x400ECC10)) -#define EMAC0_DMARIS_R (*((volatile uint32_t *)0x400ECC14)) -#define EMAC0_DMAOPMODE_R (*((volatile uint32_t *)0x400ECC18)) -#define EMAC0_DMAIM_R (*((volatile uint32_t *)0x400ECC1C)) -#define EMAC0_MFBOC_R (*((volatile uint32_t *)0x400ECC20)) -#define EMAC0_RXINTWDT_R (*((volatile uint32_t *)0x400ECC24)) -#define EMAC0_HOSTXDESC_R (*((volatile uint32_t *)0x400ECC48)) -#define EMAC0_HOSRXDESC_R (*((volatile uint32_t *)0x400ECC4C)) -#define EMAC0_HOSTXBA_R (*((volatile uint32_t *)0x400ECC50)) -#define EMAC0_HOSRXBA_R (*((volatile uint32_t *)0x400ECC54)) -#define EMAC0_PP_R (*((volatile uint32_t *)0x400ECFC0)) -#define EMAC0_PC_R (*((volatile uint32_t *)0x400ECFC4)) -#define EMAC0_CC_R (*((volatile uint32_t *)0x400ECFC8)) -#define EMAC0_EPHYRIS_R (*((volatile uint32_t *)0x400ECFD0)) -#define EMAC0_EPHYIM_R (*((volatile uint32_t *)0x400ECFD4)) -#define EMAC0_EPHYMISC_R (*((volatile uint32_t *)0x400ECFD8)) - -//***************************************************************************** -// -// EPHY registers (EMAC0) -// -//***************************************************************************** -#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control -#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status -#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register - // 1 -#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register - // 2 -#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation - // Advertisement -#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation - // Link Partner Ability -#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation - // Expansion -#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation - // Next Page TX -#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation - // Link Partner Ability Next Page -#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1 -#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2 -#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3 -#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control -#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data -#define EPHY_STS 0x00000010 // Ethernet PHY Status -#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control -#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt - // Status 1 -#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt - // Status 2 -#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense - // Counter -#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count -#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control -#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control -#define EPHY_CTL 0x00000019 // Ethernet PHY Control -#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T - // Status/Control - MR26 -#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and - // Status 1 -#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and - // Status 2 -#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic - // Control -#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control -#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration - -//***************************************************************************** -// -// System Exception Module registers (SYSEXC) -// -//***************************************************************************** -#define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) -#define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) -#define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) -#define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) - -//***************************************************************************** -// -// Hibernation module registers (HIB) -// -//***************************************************************************** -#define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) -#define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) -#define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) -#define HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) -#define HIB_IM_R (*((volatile uint32_t *)0x400FC014)) -#define HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) -#define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) -#define HIB_IC_R (*((volatile uint32_t *)0x400FC020)) -#define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) -#define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) -#define HIB_IO_R (*((volatile uint32_t *)0x400FC02C)) -#define HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) -#define HIB_CALCTL_R (*((volatile uint32_t *)0x400FC300)) -#define HIB_CAL0_R (*((volatile uint32_t *)0x400FC310)) -#define HIB_CAL1_R (*((volatile uint32_t *)0x400FC314)) -#define HIB_CALLD0_R (*((volatile uint32_t *)0x400FC320)) -#define HIB_CALLD1_R (*((volatile uint32_t *)0x400FC324)) -#define HIB_CALM0_R (*((volatile uint32_t *)0x400FC330)) -#define HIB_CALM1_R (*((volatile uint32_t *)0x400FC334)) -#define HIB_LOCK_R (*((volatile uint32_t *)0x400FC360)) -#define HIB_TPCTL_R (*((volatile uint32_t *)0x400FC400)) -#define HIB_TPSTAT_R (*((volatile uint32_t *)0x400FC404)) -#define HIB_TPIO_R (*((volatile uint32_t *)0x400FC410)) -#define HIB_TPLOG0_R (*((volatile uint32_t *)0x400FC4E0)) -#define HIB_TPLOG1_R (*((volatile uint32_t *)0x400FC4E4)) -#define HIB_TPLOG2_R (*((volatile uint32_t *)0x400FC4E8)) -#define HIB_TPLOG3_R (*((volatile uint32_t *)0x400FC4EC)) -#define HIB_TPLOG4_R (*((volatile uint32_t *)0x400FC4F0)) -#define HIB_TPLOG5_R (*((volatile uint32_t *)0x400FC4F4)) -#define HIB_TPLOG6_R (*((volatile uint32_t *)0x400FC4F8)) -#define HIB_TPLOG7_R (*((volatile uint32_t *)0x400FC4FC)) -#define HIB_PP_R (*((volatile uint32_t *)0x400FCFC0)) -#define HIB_CC_R (*((volatile uint32_t *)0x400FCFC8)) - -//***************************************************************************** -// -// FLASH registers (FLASH CTRL) -// -//***************************************************************************** -#define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) -#define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) -#define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) -#define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) -#define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) -#define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) -#define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) -#define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) -#define FLASH_FLPEKEY_R (*((volatile uint32_t *)0x400FD03C)) -#define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) -#define FLASH_PP_R (*((volatile uint32_t *)0x400FDFC0)) -#define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) -#define FLASH_CONF_R (*((volatile uint32_t *)0x400FDFC8)) -#define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) -#define FLASH_DMASZ_R (*((volatile uint32_t *)0x400FDFD0)) -#define FLASH_DMAST_R (*((volatile uint32_t *)0x400FDFD4)) -#define FLASH_RVP_R (*((volatile uint32_t *)0x400FE0D4)) -#define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) -#define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) -#define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) -#define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) -#define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) -#define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) -#define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) -#define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) -#define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) -#define FLASH_FMPRE4_R (*((volatile uint32_t *)0x400FE210)) -#define FLASH_FMPRE5_R (*((volatile uint32_t *)0x400FE214)) -#define FLASH_FMPRE6_R (*((volatile uint32_t *)0x400FE218)) -#define FLASH_FMPRE7_R (*((volatile uint32_t *)0x400FE21C)) -#define FLASH_FMPRE8_R (*((volatile uint32_t *)0x400FE220)) -#define FLASH_FMPRE9_R (*((volatile uint32_t *)0x400FE224)) -#define FLASH_FMPRE10_R (*((volatile uint32_t *)0x400FE228)) -#define FLASH_FMPRE11_R (*((volatile uint32_t *)0x400FE22C)) -#define FLASH_FMPRE12_R (*((volatile uint32_t *)0x400FE230)) -#define FLASH_FMPRE13_R (*((volatile uint32_t *)0x400FE234)) -#define FLASH_FMPRE14_R (*((volatile uint32_t *)0x400FE238)) -#define FLASH_FMPRE15_R (*((volatile uint32_t *)0x400FE23C)) -#define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) -#define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) -#define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) -#define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) -#define FLASH_FMPPE4_R (*((volatile uint32_t *)0x400FE410)) -#define FLASH_FMPPE5_R (*((volatile uint32_t *)0x400FE414)) -#define FLASH_FMPPE6_R (*((volatile uint32_t *)0x400FE418)) -#define FLASH_FMPPE7_R (*((volatile uint32_t *)0x400FE41C)) -#define FLASH_FMPPE8_R (*((volatile uint32_t *)0x400FE420)) -#define FLASH_FMPPE9_R (*((volatile uint32_t *)0x400FE424)) -#define FLASH_FMPPE10_R (*((volatile uint32_t *)0x400FE428)) -#define FLASH_FMPPE11_R (*((volatile uint32_t *)0x400FE42C)) -#define FLASH_FMPPE12_R (*((volatile uint32_t *)0x400FE430)) -#define FLASH_FMPPE13_R (*((volatile uint32_t *)0x400FE434)) -#define FLASH_FMPPE14_R (*((volatile uint32_t *)0x400FE438)) -#define FLASH_FMPPE15_R (*((volatile uint32_t *)0x400FE43C)) - -//***************************************************************************** -// -// System Control registers (SYSCTL) -// -//***************************************************************************** -#define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) -#define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) -#define SYSCTL_PTBOCTL_R (*((volatile uint32_t *)0x400FE038)) -#define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) -#define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) -#define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) -#define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) -#define SYSCTL_PWRTC_R (*((volatile uint32_t *)0x400FE060)) -#define SYSCTL_NMIC_R (*((volatile uint32_t *)0x400FE064)) -#define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) -#define SYSCTL_RSCLKCFG_R (*((volatile uint32_t *)0x400FE0B0)) -#define SYSCTL_MEMTIM0_R (*((volatile uint32_t *)0x400FE0C0)) -#define SYSCTL_ALTCLKCFG_R (*((volatile uint32_t *)0x400FE138)) -#define SYSCTL_DSCLKCFG_R (*((volatile uint32_t *)0x400FE144)) -#define SYSCTL_DIVSCLK_R (*((volatile uint32_t *)0x400FE148)) -#define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) -#define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) -#define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) -#define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) -#define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) -#define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) -#define SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) -#define SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) -#define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) -#define SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) -#define SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) -#define SYSCTL_RESBEHAVCTL_R (*((volatile uint32_t *)0x400FE1D8)) -#define SYSCTL_HSSR_R (*((volatile uint32_t *)0x400FE1F4)) -#define SYSCTL_USBPDS_R (*((volatile uint32_t *)0x400FE280)) -#define SYSCTL_USBMPC_R (*((volatile uint32_t *)0x400FE284)) -#define SYSCTL_EMACPDS_R (*((volatile uint32_t *)0x400FE288)) -#define SYSCTL_EMACMPC_R (*((volatile uint32_t *)0x400FE28C)) -#define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) -#define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) -#define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) -#define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) -#define SYSCTL_PPEPI_R (*((volatile uint32_t *)0x400FE310)) -#define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) -#define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) -#define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) -#define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) -#define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) -#define SYSCTL_PPEPHY_R (*((volatile uint32_t *)0x400FE330)) -#define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) -#define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) -#define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) -#define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) -#define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) -#define SYSCTL_PPLPC_R (*((volatile uint32_t *)0x400FE348)) -#define SYSCTL_PPPECI_R (*((volatile uint32_t *)0x400FE350)) -#define SYSCTL_PPFAN_R (*((volatile uint32_t *)0x400FE354)) -#define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) -#define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) -#define SYSCTL_PPRTS_R (*((volatile uint32_t *)0x400FE370)) -#define SYSCTL_PPCCM_R (*((volatile uint32_t *)0x400FE374)) -#define SYSCTL_PPLCD_R (*((volatile uint32_t *)0x400FE390)) -#define SYSCTL_PPOWIRE_R (*((volatile uint32_t *)0x400FE398)) -#define SYSCTL_PPEMAC_R (*((volatile uint32_t *)0x400FE39C)) -#define SYSCTL_PPHIM_R (*((volatile uint32_t *)0x400FE3A4)) -#define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) -#define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) -#define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) -#define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) -#define SYSCTL_SREPI_R (*((volatile uint32_t *)0x400FE510)) -#define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) -#define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) -#define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) -#define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) -#define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) -#define SYSCTL_SREPHY_R (*((volatile uint32_t *)0x400FE530)) -#define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) -#define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) -#define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) -#define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) -#define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) -#define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) -#define SYSCTL_SRCCM_R (*((volatile uint32_t *)0x400FE574)) -#define SYSCTL_SREMAC_R (*((volatile uint32_t *)0x400FE59C)) -#define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) -#define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) -#define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) -#define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) -#define SYSCTL_RCGCEPI_R (*((volatile uint32_t *)0x400FE610)) -#define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) -#define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) -#define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) -#define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) -#define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) -#define SYSCTL_RCGCEPHY_R (*((volatile uint32_t *)0x400FE630)) -#define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) -#define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) -#define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) -#define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) -#define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) -#define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) -#define SYSCTL_RCGCCCM_R (*((volatile uint32_t *)0x400FE674)) -#define SYSCTL_RCGCEMAC_R (*((volatile uint32_t *)0x400FE69C)) -#define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) -#define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) -#define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) -#define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) -#define SYSCTL_SCGCEPI_R (*((volatile uint32_t *)0x400FE710)) -#define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) -#define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) -#define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) -#define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) -#define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) -#define SYSCTL_SCGCEPHY_R (*((volatile uint32_t *)0x400FE730)) -#define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) -#define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) -#define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) -#define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) -#define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) -#define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) -#define SYSCTL_SCGCCCM_R (*((volatile uint32_t *)0x400FE774)) -#define SYSCTL_SCGCEMAC_R (*((volatile uint32_t *)0x400FE79C)) -#define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) -#define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) -#define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) -#define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) -#define SYSCTL_DCGCEPI_R (*((volatile uint32_t *)0x400FE810)) -#define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) -#define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) -#define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) -#define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) -#define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) -#define SYSCTL_DCGCEPHY_R (*((volatile uint32_t *)0x400FE830)) -#define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) -#define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) -#define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) -#define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) -#define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) -#define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) -#define SYSCTL_DCGCCCM_R (*((volatile uint32_t *)0x400FE874)) -#define SYSCTL_DCGCEMAC_R (*((volatile uint32_t *)0x400FE89C)) -#define SYSCTL_PCWD_R (*((volatile uint32_t *)0x400FE900)) -#define SYSCTL_PCTIMER_R (*((volatile uint32_t *)0x400FE904)) -#define SYSCTL_PCGPIO_R (*((volatile uint32_t *)0x400FE908)) -#define SYSCTL_PCDMA_R (*((volatile uint32_t *)0x400FE90C)) -#define SYSCTL_PCEPI_R (*((volatile uint32_t *)0x400FE910)) -#define SYSCTL_PCHIB_R (*((volatile uint32_t *)0x400FE914)) -#define SYSCTL_PCUART_R (*((volatile uint32_t *)0x400FE918)) -#define SYSCTL_PCSSI_R (*((volatile uint32_t *)0x400FE91C)) -#define SYSCTL_PCI2C_R (*((volatile uint32_t *)0x400FE920)) -#define SYSCTL_PCUSB_R (*((volatile uint32_t *)0x400FE928)) -#define SYSCTL_PCEPHY_R (*((volatile uint32_t *)0x400FE930)) -#define SYSCTL_PCCAN_R (*((volatile uint32_t *)0x400FE934)) -#define SYSCTL_PCADC_R (*((volatile uint32_t *)0x400FE938)) -#define SYSCTL_PCACMP_R (*((volatile uint32_t *)0x400FE93C)) -#define SYSCTL_PCPWM_R (*((volatile uint32_t *)0x400FE940)) -#define SYSCTL_PCQEI_R (*((volatile uint32_t *)0x400FE944)) -#define SYSCTL_PCEEPROM_R (*((volatile uint32_t *)0x400FE958)) -#define SYSCTL_PCCCM_R (*((volatile uint32_t *)0x400FE974)) -#define SYSCTL_PCEMAC_R (*((volatile uint32_t *)0x400FE99C)) -#define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) -#define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) -#define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) -#define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) -#define SYSCTL_PREPI_R (*((volatile uint32_t *)0x400FEA10)) -#define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) -#define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) -#define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) -#define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) -#define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) -#define SYSCTL_PREPHY_R (*((volatile uint32_t *)0x400FEA30)) -#define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) -#define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) -#define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) -#define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) -#define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) -#define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) -#define SYSCTL_PRCCM_R (*((volatile uint32_t *)0x400FEA74)) -#define SYSCTL_PREMAC_R (*((volatile uint32_t *)0x400FEA9C)) - -//***************************************************************************** -// -// Micro Direct Memory Access registers (UDMA) -// -//***************************************************************************** -#define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) -#define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) -#define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) -#define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) -#define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) -#define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) -#define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) -#define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) -#define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) -#define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) -#define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) -#define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) -#define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) -#define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) -#define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) -#define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) -#define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) -#define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) -#define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) -#define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) -#define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) -#define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) - -//***************************************************************************** -// -// Micro Direct Memory Access (uDMA) offsets (UDMA) -// -//***************************************************************************** -#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// EC registers (CCM0) -// -//***************************************************************************** -#define CCM0_CRCCTRL_R (*((volatile uint32_t *)0x44030400)) -#define CCM0_CRCSEED_R (*((volatile uint32_t *)0x44030410)) -#define CCM0_CRCDIN_R (*((volatile uint32_t *)0x44030414)) -#define CCM0_CRCRSLTPP_R (*((volatile uint32_t *)0x44030418)) - -//***************************************************************************** -// -// NVIC registers (NVIC) -// -//***************************************************************************** -#define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) -#define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) -#define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) -#define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) -#define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) -#define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) -#define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) -#define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) -#define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) -#define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) -#define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) -#define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) -#define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) -#define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) -#define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) -#define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) -#define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) -#define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) -#define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) -#define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) -#define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) -#define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) -#define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) -#define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) -#define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) -#define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) -#define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) -#define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) -#define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) -#define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) -#define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) -#define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) -#define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) -#define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) -#define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) -#define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) -#define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) -#define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) -#define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) -#define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) -#define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) -#define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) -#define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) -#define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) -#define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) -#define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) -#define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) -#define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) -#define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) -#define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) -#define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) -#define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) -#define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) -#define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) -#define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) -#define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) -#define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) -#define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) -#define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) -#define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) -#define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) -#define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) -#define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) -#define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) -#define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) -#define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) -#define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) -#define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) -#define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) -#define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) -#define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) -#define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) -#define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) -#define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) -#define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) -#define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) -#define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) -#define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) -#define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) -#define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) -#define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) -#define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) -#define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) -#define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) -#define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) -#define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) -#define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) -#define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//***************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//***************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//***************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//***************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//***************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//***************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR0 register. -// -//***************************************************************************** -#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate -#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase -#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity -#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select -#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format -#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format -#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select -#define SSI_CR0_DSS_4 0x00000003 // 4-bit data -#define SSI_CR0_DSS_5 0x00000004 // 5-bit data -#define SSI_CR0_DSS_6 0x00000005 // 6-bit data -#define SSI_CR0_DSS_7 0x00000006 // 7-bit data -#define SSI_CR0_DSS_8 0x00000007 // 8-bit data -#define SSI_CR0_DSS_9 0x00000008 // 9-bit data -#define SSI_CR0_DSS_10 0x00000009 // 10-bit data -#define SSI_CR0_DSS_11 0x0000000A // 11-bit data -#define SSI_CR0_DSS_12 0x0000000B // 12-bit data -#define SSI_CR0_DSS_13 0x0000000C // 13-bit data -#define SSI_CR0_DSS_14 0x0000000D // 14-bit data -#define SSI_CR0_DSS_15 0x0000000E // 15-bit data -#define SSI_CR0_DSS_16 0x0000000F // 16-bit data -#define SSI_CR0_SCR_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CR1 register. -// -//***************************************************************************** -#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) -#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame -#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable -#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation -#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode -#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode -#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode -#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit - // packet size -#define SSI_CR1_EOT 0x00000010 // End of Transmission -#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select -#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port - // Enable -#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DR register. -// -//***************************************************************************** -#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_SR register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI Busy Bit -#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full -#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty -#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full -#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CPSR register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_IM register. -// -//***************************************************************************** -#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask -#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask -#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask -#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask -#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask -#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt - // Mask -#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_RIS register. -// -//***************************************************************************** -#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt - // Status -#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt - // Status -#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt - // Status -#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt - // Status -#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt - // Status -#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw - // Interrupt Status -#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_MIS register. -// -//***************************************************************************** -#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt - // Status -#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked - // Interrupt Status -#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt - // Status -#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked - // Interrupt Status -#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked - // Interrupt Status -#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked - // Interrupt Status -#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_ICR register. -// -//***************************************************************************** -#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear -#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear -#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear -#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt - // Clear -#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_DMACTL register. -// -//***************************************************************************** -#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_PP register. -// -//***************************************************************************** -#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability -#define SSI_PP_MODE_M 0x00000006 // Mode of Operation -#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode -#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode - // and Bi-SSI mode enabled -#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, - // Bi-SSI and Quad-SSI mode enabled -#define SSI_PP_HSCLK 0x00000001 // High Speed Capability - -//***************************************************************************** -// -// The following are defines for the bit fields in the SSI_O_CC register. -// -//***************************************************************************** -#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source -#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock - // source and divisor factor) -#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//***************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//***************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//***************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//***************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//***************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//***************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full -#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full -#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) -#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full -#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full -#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full -#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) -#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full -#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//***************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//***************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//***************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//***************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//***************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITADDR -// register. -// -//***************************************************************************** -#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode -#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode -#define UART_9BITADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_9BITAMASK -// register. -// -//***************************************************************************** -#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode -#define UART_9BITAMASK_MASK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//***************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support - -//***************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//***************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source -#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock - // source and divisor factor) -#define UART_CC_CS_PIOSC 0x00000005 // PIOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//***************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_RS 0x00000001 // Receive not send -#define I2C_MSA_SA_S 1 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//***************************************************************************** -#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BURST 0x00000040 // Burst Enable -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_QCMD 0x00000020 // Quick Command -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_HS 0x00000010 // High-Speed Enable -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_STOP 0x00000004 // Generate STOP -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_START 0x00000002 // Generate START -#define I2C_MCS_RUN 0x00000001 // I2C Master Enable -#define I2C_MCS_BUSY 0x00000001 // I2C Busy - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//***************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data - // transferred during a transaction -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//***************************************************************************** -#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width -#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass -#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock -#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks -#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks -#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks -#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks -#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks -#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks -#define I2C_MTPR_HS 0x00000080 // High-Speed Enable -#define I2C_MTPR_TPR_M 0x0000007F // Timer Period -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//***************************************************************************** -#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt - // Mask -#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask -#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask -#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//***************************************************************************** -#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt - // Status -#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt - // Status -#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt - // Status -#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt - // Status -#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt - // Status -#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt - // Status -#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//***************************************************************************** -#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask -#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask -#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status -#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//***************************************************************************** -#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt - // Clear -#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt - // Clear -#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt - // Clear -#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt - // Clear -#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear -#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear -#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear -#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt - // Clear -#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear -#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//***************************************************************************** -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//***************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//***************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBLEN register. -// -//***************************************************************************** -#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length -#define I2C_MBLEN_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBCNT register. -// -//***************************************************************************** -#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count -#define I2C_MBCNT_CNTL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//***************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//***************************************************************************** -#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write -#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable -#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -#define I2C_SCSR_RREQ 0x00000001 // Receive Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//***************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//***************************************************************************** -#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask -#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//***************************************************************************** -#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt - // Status -#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt - // Status -#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//***************************************************************************** -#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt - // Status -#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt - // Status -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//***************************************************************************** -#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask -#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask -#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear -#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//***************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//***************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFODATA register. -// -//***************************************************************************** -#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte -#define I2C_FIFODATA_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOCTL register. -// -//***************************************************************************** -#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment -#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush -#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable -#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger -#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment -#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush -#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable -#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger -#define I2C_FIFOCTL_RXTRIG_S 16 -#define I2C_FIFOCTL_TXTRIG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOSTATUS -// register. -// -//***************************************************************************** -#define I2C_FIFOSTATUS_RXABVTRIG \ - 0x00040000 // RX FIFO Above Trigger Level -#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full -#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty -#define I2C_FIFOSTATUS_TXBLWTRIG \ - 0x00000004 // TX FIFO Below Trigger Level -#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full -#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//***************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PC register. -// -//***************************************************************************** -#define I2C_PC_HS 0x00000001 // High-Speed Capable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CTL register. -// -//***************************************************************************** -#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 -#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_SYNC register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter -#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENABLE register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable -#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable -#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable -#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable -#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable -#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable -#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INVERT register. -// -//***************************************************************************** -#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal -#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal -#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal -#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal -#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal -#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal -#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal -#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULT register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault -#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault -#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault -#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault -#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault -#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault -#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault -#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_INTEN register. -// -//***************************************************************************** -#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 -#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 -#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 -#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 -#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable -#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_RIS register. -// -//***************************************************************************** -#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 -#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 -#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 -#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 -#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted -#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ISC register. -// -//***************************************************************************** -#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted -#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted -#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted -#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted -#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status -#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_STATUS register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status -#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status -#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status -#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_FAULTVAL register. -// -//***************************************************************************** -#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value -#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value -#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value -#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value -#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value -#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value -#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value -#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_ENUPD register. -// -//***************************************************************************** -#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode -#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized -#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized -#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode -#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized -#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized -#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode -#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized -#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized -#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode -#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized -#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized -#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode -#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized -#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized -#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode -#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized -#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized -#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode -#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized -#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized -#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode -#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate -#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized -#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CTL register. -// -//***************************************************************************** -#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_0_CTL_MODE 0x00000002 // Counter Mode -#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_INTEN register. -// -//***************************************************************************** -#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_RIS register. -// -//***************************************************************************** -#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_ISC register. -// -//***************************************************************************** -#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_LOAD register. -// -//***************************************************************************** -#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_0_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_COUNT register. -// -//***************************************************************************** -#define PWM_0_COUNT_M 0x0000FFFF // Counter Value -#define PWM_0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPA register. -// -//***************************************************************************** -#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value -#define PWM_0_CMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_CMPB register. -// -//***************************************************************************** -#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value -#define PWM_0_CMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENA register. -// -//***************************************************************************** -#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_0_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_0_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_0_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_0_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_GENB register. -// -//***************************************************************************** -#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_0_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_0_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_0_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_0_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_0_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_0_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_0_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_0_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBCTL register. -// -//***************************************************************************** -#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBRISE register. -// -//***************************************************************************** -#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay -#define PWM_0_DBRISE_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_DBFALL register. -// -//***************************************************************************** -#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay -#define PWM_0_DBFALL_DELAY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period -#define PWM_0_MINFLTPER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CTL register. -// -//***************************************************************************** -#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_1_CTL_MODE 0x00000002 // Counter Mode -#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_INTEN register. -// -//***************************************************************************** -#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_RIS register. -// -//***************************************************************************** -#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_ISC register. -// -//***************************************************************************** -#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_LOAD register. -// -//***************************************************************************** -#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_1_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_COUNT register. -// -//***************************************************************************** -#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_1_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPA register. -// -//***************************************************************************** -#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_1_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_CMPB register. -// -//***************************************************************************** -#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_1_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENA register. -// -//***************************************************************************** -#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_1_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_1_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_1_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_1_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_GENB register. -// -//***************************************************************************** -#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_1_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_1_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_1_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_1_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_1_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_1_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_1_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_1_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBCTL register. -// -//***************************************************************************** -#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBRISE register. -// -//***************************************************************************** -#define PWM_1_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_1_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_DBFALL register. -// -//***************************************************************************** -#define PWM_1_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_1_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_1_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CTL register. -// -//***************************************************************************** -#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_2_CTL_MODE 0x00000002 // Counter Mode -#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_INTEN register. -// -//***************************************************************************** -#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_RIS register. -// -//***************************************************************************** -#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_ISC register. -// -//***************************************************************************** -#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_LOAD register. -// -//***************************************************************************** -#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_2_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_COUNT register. -// -//***************************************************************************** -#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_2_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPA register. -// -//***************************************************************************** -#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_2_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_CMPB register. -// -//***************************************************************************** -#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_2_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENA register. -// -//***************************************************************************** -#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_2_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_2_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_2_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_2_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_GENB register. -// -//***************************************************************************** -#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_2_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_2_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_2_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_2_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_2_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_2_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_2_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_2_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBCTL register. -// -//***************************************************************************** -#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBRISE register. -// -//***************************************************************************** -#define PWM_2_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_2_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_DBFALL register. -// -//***************************************************************************** -#define PWM_2_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_2_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_2_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CTL register. -// -//***************************************************************************** -#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input -#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period -#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source -#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode -#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized -#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized -#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode -#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized -#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized -#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode -#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized -#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized -#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode -#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized -#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized -#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode -#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate -#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized -#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized -#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode -#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode -#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode -#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode -#define PWM_3_CTL_MODE 0x00000002 // Counter Mode -#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_INTEN register. -// -//***************************************************************************** -#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up -#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up -#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD -#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 -#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB - // Down -#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB - // Up -#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA - // Down -#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA - // Up -#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD -#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_RIS register. -// -//***************************************************************************** -#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt - // Status -#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status -#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt - // Status -#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status -#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status -#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_ISC register. -// -//***************************************************************************** -#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt -#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt -#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt -#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt -#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt -#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_LOAD register. -// -//***************************************************************************** -#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value -#define PWM_3_LOAD_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_COUNT register. -// -//***************************************************************************** -#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value -#define PWM_3_COUNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPA register. -// -//***************************************************************************** -#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value -#define PWM_3_CMPA_COMPA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_CMPB register. -// -//***************************************************************************** -#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value -#define PWM_3_CMPB_COMPB_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENA register. -// -//***************************************************************************** -#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENA_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA -#define PWM_3_GENA_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High -#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENA_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA -#define PWM_3_GENA_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENA_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA -#define PWM_3_GENA_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High -#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENA_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA -#define PWM_3_GENA_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmA Low -#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High -#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA -#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low -#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High -#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA -#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low -#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_GENB register. -// -//***************************************************************************** -#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down -#define PWM_3_GENB_ACTCMPBD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB -#define PWM_3_GENB_ACTCMPBD_ZERO \ - 0x00000800 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High -#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up -#define PWM_3_GENB_ACTCMPBU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB -#define PWM_3_GENB_ACTCMPBU_ZERO \ - 0x00000200 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down -#define PWM_3_GENB_ACTCMPAD_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB -#define PWM_3_GENB_ACTCMPAD_ZERO \ - 0x00000080 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High -#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up -#define PWM_3_GENB_ACTCMPAU_NONE \ - 0x00000000 // Do nothing -#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB -#define PWM_3_GENB_ACTCMPAU_ZERO \ - 0x00000020 // Drive pwmB Low -#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High -#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD -#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB -#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low -#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High -#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 -#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing -#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB -#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low -#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBCTL register. -// -//***************************************************************************** -#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBRISE register. -// -//***************************************************************************** -#define PWM_3_DBRISE_RISEDELAY_M \ - 0x00000FFF // Dead-Band Rise Delay -#define PWM_3_DBRISE_RISEDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_DBFALL register. -// -//***************************************************************************** -#define PWM_3_DBFALL_FALLDELAY_M \ - 0x00000FFF // Dead-Band Fall Delay -#define PWM_3_DBFALL_FALLDELAY_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input -#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input -#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input -#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 -#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 -#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 -#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 -#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 -#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 -#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 -#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_MINFLTPER -// register. -// -//***************************************************************************** -#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period -#define PWM_3_MINFLTPER_MFP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. -// -//***************************************************************************** -#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. -// -//***************************************************************************** -#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. -// -//***************************************************************************** -#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. -// -//***************************************************************************** -#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense -#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense -#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense -#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 -#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 -#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 -#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 -// register. -// -//***************************************************************************** -#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger -#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger -#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger -#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger -#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger -#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger -#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger -#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_PP register. -// -//***************************************************************************** -#define PWM_PP_ONE 0x00000400 // One-Shot Mode -#define PWM_PP_EFAULT 0x00000200 // Extended Fault -#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization -#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) -#define PWM_PP_GCNT_M 0x0000000F // Generators -#define PWM_PP_FCNT_S 4 -#define PWM_PP_GCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the PWM_O_CC register. -// -//***************************************************************************** -#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor -#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider -#define PWM_CC_PWMDIV_2 0x00000000 // /2 -#define PWM_CC_PWMDIV_4 0x00000001 // /4 -#define PWM_CC_PWMDIV_8 0x00000002 // /8 -#define PWM_CC_PWMDIV_16 0x00000003 // /16 -#define PWM_CC_PWMDIV_32 0x00000004 // /32 -#define PWM_CC_PWMDIV_64 0x00000005 // /64 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_CTL register. -// -//***************************************************************************** -#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count -#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter -#define QEI_CTL_STALLEN 0x00001000 // Stall QEI -#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse -#define QEI_CTL_INVB 0x00000400 // Invert PhB -#define QEI_CTL_INVA 0x00000200 // Invert PhA -#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity -#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 -#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 -#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 -#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 -#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 -#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 -#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 -#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 -#define QEI_CTL_VELEN 0x00000020 // Capture Velocity -#define QEI_CTL_RESMODE 0x00000010 // Reset Mode -#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode -#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode -#define QEI_CTL_SWAP 0x00000002 // Swap Signals -#define QEI_CTL_ENABLE 0x00000001 // Enable QEI -#define QEI_CTL_FILTCNT_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation -#define QEI_STAT_ERROR 0x00000001 // Error Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator - // Value -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator - // Value -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Velocity -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable -#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt - // Enable -#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable -#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected -#define QEI_RIS_DIR 0x00000004 // Direction Change Detected -#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired -#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted - -//***************************************************************************** -// -// The following are defines for the bit fields in the QEI_O_ISC register. -// -//***************************************************************************** -#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt -#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt -#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt -#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this - // value selects the 32-bit timer - // configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this - // value selects the 32-bit - // real-time clock (RTC) counter - // configuration -#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this - // value selects the 16-bit timer - // configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TAMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TAMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TAMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt - // Disable -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select -#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations -#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out -#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out -#define TIMER_TBMR_TCACT_SETTOGTO \ - 0x00008000 // Set CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_CLRTOGTO \ - 0x0000A000 // Clear CCP immediately and toggle - // on Time-Out -#define TIMER_TBMR_TCACT_SETCLRTO \ - 0x0000C000 // Set CCP immediately and clear on - // Time-Out -#define TIMER_TBMR_TCACT_CLRSETTO \ - 0x0000E000 // Clear CCP immediately and set on - // Time-Out -#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt - // Disable -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7 -#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected -#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of - // GPTM7 is triggered -#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM7 is - // triggered -#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6 -#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected -#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of - // GPTM6 is triggered -#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM6 is - // triggered -#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 -#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected -#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of - // GPTM5 is triggered -#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM5 is - // triggered -#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 -#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected -#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of - // GPTM4 is triggered -#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM4 is - // triggered -#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 -#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected -#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of - // GPTM3 is triggered -#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM3 is - // triggered -#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 -#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected -#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of - // GPTM2 is triggered -#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM2 is - // triggered -#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 -#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected -#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of - // GPTM1 is triggered -#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM1 is - // triggered -#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 -#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected -#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of - // GPTM0 is triggered -#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM0 is - // triggered - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt - // Mask -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt - // Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt - // Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw - // Interrupt Status -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event - // Raw Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match - // Raw Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked - // Interrupt -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event - // Masked Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match - // Masked Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt - // Clear -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt - // Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt - // Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event - // Interrupt Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match - // Interrupt Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -#define TIMER_TAILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -#define TIMER_TAMATCHR_TAMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -#define TIMER_TBMATCHR_TBMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -#define TIMER_TAR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -#define TIMER_TBR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -#define TIMER_TAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_DMAEV register. -// -//***************************************************************************** -#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA - // Trigger Enable -#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger - // Enable -#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA - // Trigger Enable -#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ADCEV register. -// -//***************************************************************************** -#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC - // Trigger Enable -#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger - // Enable -#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC - // Trigger Enable -#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC - // Trigger Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source -#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start -#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are - // 32 bits each with a 16-bit - // prescale counter - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CC register. -// -//***************************************************************************** -#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy -#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable -#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable -#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable -#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable -#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt - // Status -#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status -#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status -#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_IM register. -// -//***************************************************************************** -#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on - // SS3 -#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on - // SS2 -#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on - // SS1 -#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on - // SS0 -#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask -#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask -#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask -#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask -#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ISC register. -// -//***************************************************************************** -#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt - // Status on SS3 -#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt - // Status on SS2 -#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt - // Status on SS1 -#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt - // Status on SS0 -#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and - // Clear -#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and - // Clear -#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 -#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 -#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 -#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 -#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 -#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 -#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 -#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 -#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_TSSEL register. -// -//***************************************************************************** -#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger - // Select -#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger - // Select -#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger - // Select -#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its - // trigger) in PWM module 0 -#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger - // Select -#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its - // trigger) in PWM module 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority -#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority -#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority -#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SPC register. -// -//***************************************************************************** -#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference -#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 -#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 -#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 -#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 -#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 -#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 -#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 -#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 -#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 -#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 -#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 -#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 -#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 -#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 -#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 -#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize -#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait -#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCISC register. -// -//***************************************************************************** -#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt - // Status and Clear -#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt - // Status and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CTL register. -// -//***************************************************************************** -#define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select -#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage - // references -#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- - // inputs are the voltage - // references - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX0 register. -// -//***************************************************************************** -#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL0 register. -// -//***************************************************************************** -#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input - // Select -#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input - // Select -#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input - // Select -#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input - // Select -#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. -// -//***************************************************************************** -#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. -// -//***************************************************************************** -#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP0 register. -// -//***************************************************************************** -#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator - // Operation -#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator - // Operation -#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator - // Operation -#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator - // Operation -#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC0 register. -// -//***************************************************************************** -#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator - // Select -#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator - // Select -#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator - // Select -#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC0_S6DCSEL_S 24 -#define ADC_SSDC0_S5DCSEL_S 20 -#define ADC_SSDC0_S4DCSEL_S 16 -#define ADC_SSDC0_S3DCSEL_S 12 -#define ADC_SSDC0_S2DCSEL_S 8 -#define ADC_SSDC0_S1DCSEL_S 4 -#define ADC_SSDC0_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. -// -//***************************************************************************** -#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH0 register. -// -//***************************************************************************** -#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH0_TSH7_S 28 -#define ADC_SSTSH0_TSH6_S 24 -#define ADC_SSTSH0_TSH5_S 20 -#define ADC_SSTSH0_TSH4_S 16 -#define ADC_SSTSH0_TSH3_S 12 -#define ADC_SSTSH0_TSH2_S 8 -#define ADC_SSTSH0_TSH1_S 4 -#define ADC_SSTSH0_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX1 register. -// -//***************************************************************************** -#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL1 register. -// -//***************************************************************************** -#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. -// -//***************************************************************************** -#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. -// -//***************************************************************************** -#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP1 register. -// -//***************************************************************************** -#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC1 register. -// -//***************************************************************************** -#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC1_S2DCSEL_S 8 -#define ADC_SSDC1_S1DCSEL_S 4 -#define ADC_SSDC1_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. -// -//***************************************************************************** -#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH1 register. -// -//***************************************************************************** -#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH1_TSH3_S 12 -#define ADC_SSTSH1_TSH2_S 8 -#define ADC_SSTSH1_TSH1_S 4 -#define ADC_SSTSH1_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX2 register. -// -//***************************************************************************** -#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL2 register. -// -//***************************************************************************** -#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input - // Select -#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input - // Select -#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input - // Select -#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. -// -//***************************************************************************** -#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. -// -//***************************************************************************** -#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP2 register. -// -//***************************************************************************** -#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator - // Operation -#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator - // Operation -#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator - // Operation -#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC2 register. -// -//***************************************************************************** -#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator - // Select -#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator - // Select -#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select -#define ADC_SSDC2_S2DCSEL_S 8 -#define ADC_SSDC2_S1DCSEL_S 4 -#define ADC_SSDC2_S0DCSEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. -// -//***************************************************************************** -#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper - // Bit) -#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH2 register. -// -//***************************************************************************** -#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH2_TSH3_S 12 -#define ADC_SSTSH2_TSH2_S 8 -#define ADC_SSTSH2_TSH1_S 4 -#define ADC_SSTSH2_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSMUX3 register. -// -//***************************************************************************** -#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSCTL3 register. -// -//***************************************************************************** -#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 // End of Sequence -#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. -// -//***************************************************************************** -#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. -// -//***************************************************************************** -#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSOP3 register. -// -//***************************************************************************** -#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator - // Operation - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSDC3 register. -// -//***************************************************************************** -#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator - // Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. -// -//***************************************************************************** -#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper - // Bit) - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_SSTSH3 register. -// -//***************************************************************************** -#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period - // Select -#define ADC_SSTSH3_TSH0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCRIC register. -// -//***************************************************************************** -#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 -#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 -#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 -#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 -#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 -#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 -#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 -#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 -#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 -#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 -#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 -#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 -#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 -#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 -#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 -#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL0 register. -// -//***************************************************************************** -#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL1 register. -// -//***************************************************************************** -#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL2 register. -// -//***************************************************************************** -#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL3 register. -// -//***************************************************************************** -#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL4 register. -// -//***************************************************************************** -#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL5 register. -// -//***************************************************************************** -#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL6 register. -// -//***************************************************************************** -#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCTL7 register. -// -//***************************************************************************** -#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable -#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition -#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band -#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band -#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode -#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once -#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always -#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once -#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable -#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition -#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band -#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band -#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band -#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode -#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always -#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once -#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always -#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP0 register. -// -//***************************************************************************** -#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP0_COMP1_S 16 -#define ADC_DCCMP0_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP1 register. -// -//***************************************************************************** -#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP1_COMP1_S 16 -#define ADC_DCCMP1_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP2 register. -// -//***************************************************************************** -#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP2_COMP1_S 16 -#define ADC_DCCMP2_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP3 register. -// -//***************************************************************************** -#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP3_COMP1_S 16 -#define ADC_DCCMP3_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP4 register. -// -//***************************************************************************** -#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP4_COMP1_S 16 -#define ADC_DCCMP4_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP5 register. -// -//***************************************************************************** -#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP5_COMP1_S 16 -#define ADC_DCCMP5_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP6 register. -// -//***************************************************************************** -#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP6_COMP1_S 16 -#define ADC_DCCMP6_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_DCCMP7 register. -// -//***************************************************************************** -#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 -#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 -#define ADC_DCCMP7_COMP1_S 16 -#define ADC_DCCMP7_COMP0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PP register. -// -//***************************************************************************** -#define ADC_PP_APSHT 0x01000000 // Application-Programmable - // Sample-and-Hold Time -#define ADC_PP_TS 0x00800000 // Temperature Sensor -#define ADC_PP_RSL_M 0x007C0000 // Resolution -#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture -#define ADC_PP_TYPE_SAR 0x00000000 // SAR -#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count -#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count -#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate -#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH -#define ADC_PP_RSL_S 18 -#define ADC_PP_DC_S 10 -#define ADC_PP_CH_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_PC register. -// -//***************************************************************************** -#define ADC_PC_MCR_M 0x0000000F // Conversion Rate -#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a - // conversion completes, the logic - // pauses for 112 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a - // conversion completes, the logic - // pauses for 48 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a - // conversion completes, the logic - // pauses for 16 TADC periods - // before starting the next - // conversion -#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as - // defined by TADC and NSH - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_CC register. -// -//***************************************************************************** -#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor -#define ADC_CC_CS_M 0x0000000F // ADC Clock Source -#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV -#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC -#define ADC_CC_CS_MOSC 0x00000002 // MOSC -#define ADC_CC_CLKDIV_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACMIS register. -// -//***************************************************************************** -#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt - // Status -#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt - // Status -#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACRIS register. -// -//***************************************************************************** -#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status -#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status -#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACINTEN register. -// -//***************************************************************************** -#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable -#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable -#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACREFCTL -// register. -// -//***************************************************************************** -#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable -#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range -#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref -#define COMP_ACREFCTL_VREF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. -// -//***************************************************************************** -#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL0 register. -// -//***************************************************************************** -#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. -// -//***************************************************************************** -#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL1 register. -// -//***************************************************************************** -#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. -// -//***************************************************************************** -#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_ACCTL2 register. -// -//***************************************************************************** -#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable -#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive -#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ -#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ -#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value -#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense -#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL -#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge -#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge -#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge -#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value -#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense -#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL -#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge -#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge -#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge -#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert - -//***************************************************************************** -// -// The following are defines for the bit fields in the COMP_O_PP register. -// -//***************************************************************************** -#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present -#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present -#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present -#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present -#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present -#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_CTL register. -// -//***************************************************************************** -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable -#define CAN_CTL_INIT 0x00000001 // Initialization - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_STS register. -// -//***************************************************************************** -#define CAN_STS_BOFF 0x00000080 // Bus-Off Status -#define CAN_STS_EWARN 0x00000040 // Warning Status -#define CAN_STS_EPASS 0x00000020 // Error Passive -#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully -#define CAN_STS_TXOK 0x00000008 // Transmitted a Message - // Successfully -#define CAN_STS_LEC_M 0x00000007 // Last Error Code -#define CAN_STS_LEC_NONE 0x00000000 // No Error -#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error -#define CAN_STS_LEC_FORM 0x00000002 // Format Error -#define CAN_STS_LEC_ACK 0x00000003 // ACK Error -#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error -#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error -#define CAN_STS_LEC_CRC 0x00000006 // CRC Error -#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_ERR register. -// -//***************************************************************************** -#define CAN_ERR_RP 0x00008000 // Received Error Passive -#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter -#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter -#define CAN_ERR_REC_S 8 -#define CAN_ERR_TEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BIT register. -// -//***************************************************************************** -#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point -#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point -#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width -#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler -#define CAN_BIT_TSEG2_S 12 -#define CAN_BIT_TSEG1_S 8 -#define CAN_BIT_SJW_S 6 -#define CAN_BIT_BRP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_INT register. -// -//***************************************************************************** -#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier -#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending -#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TST register. -// -//***************************************************************************** -#define CAN_TST_RX 0x00000080 // Receive Observation -#define CAN_TST_TX_M 0x00000060 // Transmit Control -#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control -#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point -#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low -#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High -#define CAN_TST_LBACK 0x00000010 // Loopback Mode -#define CAN_TST_SILENT 0x00000008 // Silent Mode -#define CAN_TST_BASIC 0x00000004 // Basic Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_BRPE register. -// -//***************************************************************************** -#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension -#define CAN_BRPE_BRPE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CRQ register. -// -//***************************************************************************** -#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF1CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1CMSK register. -// -//***************************************************************************** -#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. -// -//***************************************************************************** -#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF1MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. -// -//***************************************************************************** -#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF1MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. -// -//***************************************************************************** -#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF1ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. -// -//***************************************************************************** -#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF1ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1MCTL register. -// -//***************************************************************************** -#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF1MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA1 register. -// -//***************************************************************************** -#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DA2 register. -// -//***************************************************************************** -#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB1 register. -// -//***************************************************************************** -#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF1DB2 register. -// -//***************************************************************************** -#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF1DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CRQ register. -// -//***************************************************************************** -#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag -#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number -#define CAN_IF2CRQ_MNUM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2CMSK register. -// -//***************************************************************************** -#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read -#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits -#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits -#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits -#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit -#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data -#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request -#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 -#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. -// -//***************************************************************************** -#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask -#define CAN_IF2MSK1_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. -// -//***************************************************************************** -#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier -#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction -#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask -#define CAN_IF2MSK2_IDMSK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. -// -//***************************************************************************** -#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier -#define CAN_IF2ARB1_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. -// -//***************************************************************************** -#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid -#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier -#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction -#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier -#define CAN_IF2ARB2_ID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2MCTL register. -// -//***************************************************************************** -#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data -#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost -#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending -#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask -#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable -#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable -#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable -#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request -#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer -#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code -#define CAN_IF2MCTL_DLC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA1 register. -// -//***************************************************************************** -#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DA2 register. -// -//***************************************************************************** -#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DA2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB1 register. -// -//***************************************************************************** -#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_IF2DB2 register. -// -//***************************************************************************** -#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data -#define CAN_IF2DB2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ1 register. -// -//***************************************************************************** -#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ1_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_TXRQ2 register. -// -//***************************************************************************** -#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits -#define CAN_TXRQ2_TXRQST_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA1 register. -// -//***************************************************************************** -#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA1_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_NWDA2 register. -// -//***************************************************************************** -#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits -#define CAN_NWDA2_NEWDAT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1INT register. -// -//***************************************************************************** -#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG1INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2INT register. -// -//***************************************************************************** -#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits -#define CAN_MSG2INT_INTPND_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG1VAL register. -// -//***************************************************************************** -#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG1VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CAN_O_MSG2VAL register. -// -//***************************************************************************** -#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits -#define CAN_MSG2VAL_MSGVAL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FADDR register. -// -//***************************************************************************** -#define USB_FADDR_M 0x0000007F // Function Address -#define USB_FADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_POWER register. -// -//***************************************************************************** -#define USB_POWER_ISOUP 0x00000080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x00000020 // High Speed Enable -#define USB_POWER_HSMODE 0x00000010 // High Speed Enable -#define USB_POWER_RESET 0x00000008 // RESET Signaling -#define USB_POWER_RESUME 0x00000004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIS register. -// -//***************************************************************************** -#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt -#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt -#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt -#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt -#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt -#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt -#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt -#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIS register. -// -//***************************************************************************** -#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt -#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt -#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt -#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt -#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt -#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt -#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIE register. -// -//***************************************************************************** -#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable -#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable -#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable -#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable -#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable -#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable -#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable -#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIE register. -// -//***************************************************************************** -#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable -#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable -#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable -#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable -#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable -#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable -#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IS register. -// -//***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) -#define USB_IS_CONN 0x00000010 // Session Connect -#define USB_IS_SOF 0x00000008 // Start of Frame -#define USB_IS_BABBLE 0x00000004 // Babble Detected -#define USB_IS_RESET 0x00000004 // RESET Signaling Detected -#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_IE register. -// -//***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG - // only) -#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG - // only) -#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt -#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt -#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FRAME register. -// -//***************************************************************************** -#define USB_FRAME_M 0x000007FF // Frame Number -#define USB_FRAME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPIDX register. -// -//***************************************************************************** -#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index -#define USB_EPIDX_EPIDX_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TEST register. -// -//***************************************************************************** -#define USB_TEST_FORCEH 0x00000080 // Force Host Mode -#define USB_TEST_FIFOACC 0x00000040 // FIFO Access -#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO0 register. -// -//***************************************************************************** -#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO0_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO1 register. -// -//***************************************************************************** -#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO1_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO2 register. -// -//***************************************************************************** -#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO2_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO3 register. -// -//***************************************************************************** -#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO3_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO4 register. -// -//***************************************************************************** -#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO4_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO5 register. -// -//***************************************************************************** -#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO5_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO6 register. -// -//***************************************************************************** -#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO6_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO7 register. -// -//***************************************************************************** -#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO7_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DEVCTL register. -// -//***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) -#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) -#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CCONF register. -// -//***************************************************************************** -#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. -// -//***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. -// -//***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFIFOADD -// register. -// -//***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_TXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFIFOADD -// register. -// -//***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address -#define USB_RXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL -// register. -// -//***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ - 0x00000002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS \ - 0x00000001 // Use External VBUS - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGDATA -// register. -// -//***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M \ - 0x000000FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGADDR -// register. -// -//***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address -#define USB_ULPIREGADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGCTL -// register. -// -//***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPINFO register. -// -//***************************************************************************** -#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints -#define USB_EPINFO_RXEP_S 4 -#define USB_EPINFO_TXEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RAMINFO register. -// -//***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width -#define USB_RAMINFO_DMACHAN_S 4 -#define USB_RAMINFO_RAMBITS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CONTIM register. -// -//***************************************************************************** -#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x0000000F // Wait ID -#define USB_CONTIM_WTCON_S 4 -#define USB_CONTIM_WTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VPLEN register. -// -//***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length -#define USB_VPLEN_VPLEN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSEOF register. -// -//***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap -#define USB_HSEOF_HSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FSEOF register. -// -//***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap -#define USB_FSEOF_FSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LSEOF register. -// -//***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap -#define USB_LSEOF_LSEOFG_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR0 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT0 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT0_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRL0 register. -// -//***************************************************************************** -#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear -#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x00000020 // Request Packet -#define USB_CSRL0_STALL 0x00000020 // Send Stall -#define USB_CSRL0_SETEND 0x00000010 // Setup End -#define USB_CSRL0_ERROR 0x00000010 // Error -#define USB_CSRL0_DATAEND 0x00000008 // Data End -#define USB_CSRL0_SETUP 0x00000008 // Setup Packet -#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CSRH0 register. -// -//***************************************************************************** -#define USB_CSRH0_DISPING 0x00000008 // PING Disable -#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x00000002 // Data Toggle -#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_COUNT0 register. -// -//***************************************************************************** -#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count -#define USB_COUNT0_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TYPE0 register. -// -//***************************************************************************** -#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x00000040 // High -#define USB_TYPE0_SPEED_FULL 0x00000080 // Full -#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_NAKLMT register. -// -//***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit -#define USB_NAKLMT_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP1 register. -// -//***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL1 register. -// -//***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x00000010 // Send STALL -#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x00000004 // Error -#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH1 register. -// -//***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x00000020 // Mode -#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP1 register. -// -//***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP1_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL1 register. -// -//***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x00000020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x00000004 // Overrun -#define USB_RXCSRL1_ERROR 0x00000004 // Error -#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH1 register. -// -//***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x00000002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. -// -//***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT1_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE1 register. -// -//***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ - 0 -#define USB_TXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE1 register. -// -//***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE1_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL1 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ - 0 -#define USB_RXINTERVAL1_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP2 register. -// -//***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL2 register. -// -//***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL2_STALL 0x00000010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x00000004 // Error -#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH2 register. -// -//***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x00000020 // Mode -#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP2 register. -// -//***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL2 register. -// -//***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL2_STALL 0x00000020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x00000004 // Error -#define USB_RXCSRL2_OVER 0x00000004 // Overrun -#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH2 register. -// -//***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x00000002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. -// -//***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT2_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE2 register. -// -//***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ - 0 -#define USB_TXINTERVAL2_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE2 register. -// -//***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ - 0 -#define USB_RXINTERVAL2_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP3 register. -// -//***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL3 register. -// -//***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL3_STALL 0x00000010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x00000004 // Error -#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH3 register. -// -//***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x00000020 // Mode -#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP3 register. -// -//***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL3 register. -// -//***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x00000020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x00000004 // Error -#define USB_RXCSRL3_OVER 0x00000004 // Overrun -#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH3 register. -// -//***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x00000002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. -// -//***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT3_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE3 register. -// -//***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ - 0 -#define USB_TXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE3 register. -// -//***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ - 0 -#define USB_RXINTERVAL3_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP4 register. -// -//***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL4 register. -// -//***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL4_STALL 0x00000010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x00000004 // Error -#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH4 register. -// -//***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x00000020 // Mode -#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP4 register. -// -//***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL4 register. -// -//***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x00000020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL4_OVER 0x00000004 // Overrun -#define USB_RXCSRL4_ERROR 0x00000004 // Error -#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH4 register. -// -//***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x00000002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. -// -//***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE4 register. -// -//***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ - 0 -#define USB_TXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE4 register. -// -//***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ - 0 -#define USB_RXINTERVAL4_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP5 register. -// -//***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL5 register. -// -//***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL5_STALL 0x00000010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x00000004 // Error -#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH5 register. -// -//***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x00000020 // Mode -#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP5 register. -// -//***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL5 register. -// -//***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x00000020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL5_ERROR 0x00000004 // Error -#define USB_RXCSRL5_OVER 0x00000004 // Overrun -#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH5 register. -// -//***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x00000002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. -// -//***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE5 register. -// -//***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ - 0 -#define USB_TXINTERVAL5_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE5 register. -// -//***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE5_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL5 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ - 0 -#define USB_RXINTERVAL5_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP6 register. -// -//***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL6 register. -// -//***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x00000010 // Send STALL -#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x00000004 // Error -#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH6 register. -// -//***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x00000020 // Mode -#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP6 register. -// -//***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL6 register. -// -//***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL6_STALL 0x00000020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL6_ERROR 0x00000004 // Error -#define USB_RXCSRL6_OVER 0x00000004 // Overrun -#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH6 register. -// -//***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x00000002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. -// -//***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE6 register. -// -//***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ - 0 -#define USB_TXINTERVAL6_NAKLMT_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE6 register. -// -//***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ - 0 -#define USB_RXINTERVAL6_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP7 register. -// -//***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_TXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL7 register. -// -//***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x00000010 // Send STALL -#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x00000004 // Error -#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH7 register. -// -//***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x00000020 // Mode -#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x00000001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP7 register. -// -//***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload -#define USB_RXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL7 register. -// -//***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL7_STALL 0x00000020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x00000004 // Error -#define USB_RXCSRL7_OVER 0x00000004 // Overrun -#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH7 register. -// -//***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x00000002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. -// -//***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count -#define USB_RXCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE7 register. -// -//***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_TXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ - 0 -#define USB_TXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE7 register. -// -//***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number -#define USB_RXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ - 0 -#define USB_RXINTERVAL7_TXPOLL_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAINTR register. -// -//***************************************************************************** -#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL0 register. -// -//***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x00000002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL0_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR0 register. -// -//***************************************************************************** -#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR0_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT0 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT0_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL1 register. -// -//***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x00000002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL1_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR1 register. -// -//***************************************************************************** -#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR1_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT1 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT1_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL2 register. -// -//***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x00000002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL2_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR2 register. -// -//***************************************************************************** -#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR2_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT2 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT2_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL3 register. -// -//***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x00000002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL3_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR3 register. -// -//***************************************************************************** -#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR3_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT3 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT3_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL4 register. -// -//***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x00000002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL4_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR4 register. -// -//***************************************************************************** -#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR4_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT4 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT4_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL5 register. -// -//***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x00000002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL5_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR5 register. -// -//***************************************************************************** -#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR5_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT5 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT5_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL6 register. -// -//***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x00000002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL6_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR6 register. -// -//***************************************************************************** -#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR6_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT6 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT6_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL7 register. -// -//***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x00000002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL7_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR7 register. -// -//***************************************************************************** -#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR7_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT7 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT7_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT3_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CTO register. -// -//***************************************************************************** -#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value -#define USB_CTO_CCTV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HHSRTN register. -// -//***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating - // Delay -#define USB_HHSRTN_HHSRTN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSBT register. -// -//***************************************************************************** -#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder -#define USB_HSBT_HSBT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMATTR register. -// -//***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x0000000F // Link State -#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMCNTRL register. -// -//***************************************************************************** -#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions - // are not supported. In this case, - // the USB does not respond to LPM - // transactions and LPM - // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but - // extended transactions are - // supported. In this case, the USB - // does respond to an LPM - // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended - // transactions. In this case, the - // USB responds with a NYET or an - // ACK as determined by the value - // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMIM register. -// -//***************************************************************************** -#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMRIS register. -// -//***************************************************************************** -#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMFADDR register. -// -//***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address -#define USB_LPMFADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPC register. -// -//***************************************************************************** -#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x00000200 // Low -#define USB_EPC_PFLTACT_HIGH 0x00000300 // High -#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable - // Configuration -#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low - // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High - // (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCRIS register. -// -//***************************************************************************** -#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCIM register. -// -//***************************************************************************** -#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCISC register. -// -//***************************************************************************** -#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRRIS register. -// -//***************************************************************************** -#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRIM register. -// -//***************************************************************************** -#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRISC register. -// -//***************************************************************************** -#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_GPCS register. -// -//***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high -#define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x00000004 // Use USB0VBUS and force USB0ID - // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID - // high - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDC register. -// -//***************************************************************************** -#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCRIS register. -// -//***************************************************************************** -#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCIM register. -// -//***************************************************************************** -#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCISC register. -// -//***************************************************************************** -#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PP register. -// -//***************************************************************************** -#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count -#define USB_PP_USB_M 0x000000C0 // USB Capability -#define USB_PP_USB_DEVICE 0x00000040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST -#define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_ULPI 0x00000020 // ULPI Present -#define USB_PP_PHY 0x00000010 // PHY Present -#define USB_PP_TYPE_M 0x0000000F // Controller Type -#define USB_PP_TYPE_0 0x00000000 // The first-generation USB - // controller -#define USB_PP_TYPE_1 0x00000001 // Second-generation USB - // controller.The controller - // implemented in post Icestorm - // devices that use the 3.0 version - // of the Mentor controller -#define USB_PP_ECNT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PC register. -// -//***************************************************************************** -#define USB_PC_ULPIEN 0x00010000 // ULPI Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CC register. -// -//***************************************************************************** -#define USB_CC_CLKEN 0x00000200 // USB Clock Enable -#define USB_CC_CSD 0x00000100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor -#define USB_CC_CLKDIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESIZE register. -// -//***************************************************************************** -#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks -#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words -#define EEPROM_EESIZE_BLKCNT_S 16 -#define EEPROM_EESIZE_WORDCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEBLOCK register. -// -//***************************************************************************** -#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block -#define EEPROM_EEBLOCK_BLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEOFFSET -// register. -// -//***************************************************************************** -#define EEPROM_EEOFFSET_OFFSET_M \ - 0x0000000F // Current Address Offset -#define EEPROM_EEOFFSET_OFFSET_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWR register. -// -//***************************************************************************** -#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data -#define EEPROM_EERDWR_VALUE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EERDWRINC -// register. -// -//***************************************************************************** -#define EEPROM_EERDWRINC_VALUE_M \ - 0xFFFFFFFF // EEPROM Read or Write Data with - // Increment -#define EEPROM_EERDWRINC_VALUE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDONE register. -// -//***************************************************************************** -#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy -#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission -#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy -#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase -#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EESUPP register. -// -//***************************************************************************** -#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried -#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEUNLOCK -// register. -// -//***************************************************************************** -#define EEPROM_EEUNLOCK_UNLOCK_M \ - 0xFFFFFFFF // EEPROM Unlock - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPROT register. -// -//***************************************************************************** -#define EEPROM_EEPROT_ACC 0x00000008 // Access Control -#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control -#define EEPROM_EEPROT_PROT_RWNPW \ - 0x00000000 // This setting is the default. If - // there is no password, the block - // is not protected and is readable - // and writable -#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the - // block is readable or writable - // only when unlocked -#define EEPROM_EEPROT_PROT_RONPW \ - 0x00000002 // If there is no password, the - // block is readable, not writable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS0 register. -// -//***************************************************************************** -#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS0_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS1 register. -// -//***************************************************************************** -#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS1_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEPASS2 register. -// -//***************************************************************************** -#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password -#define EEPROM_EEPASS2_PASS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEINT register. -// -//***************************************************************************** -#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE0 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE1 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEHIDE2 register. -// -//***************************************************************************** -#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_EEDBGME register. -// -//***************************************************************************** -#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key -#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase -#define EEPROM_EEDBGME_KEY_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EEPROM_PP register. -// -//***************************************************************************** -#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size -#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM -#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM -#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM -#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM -#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM -#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM -#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM -#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM -#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM -#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_CFG register. -// -//***************************************************************************** -#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable -#define EPI_CFG_BLKEN 0x00000010 // Block Enable -#define EPI_CFG_MODE_M 0x0000000F // Mode Select -#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose -#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM -#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) -#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD register. -// -//***************************************************************************** -#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 -#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 -#define EPI_BAUD_COUNT1_S 16 -#define EPI_BAUD_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_BAUD2 register. -// -//***************************************************************************** -#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 -#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 -#define EPI_BAUD2_COUNT1_S 16 -#define EPI_BAUD2_COUNT0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG register. -// -//***************************************************************************** -#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle -#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register - // Write -#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register - // Read -#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode -#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration -#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] -#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] -#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] -#define EPI_HB16CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_GPCFG register. -// -//***************************************************************************** -#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin -#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated -#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame -#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count -#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes -#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size -#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address -#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide -#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size - // cannot be used with 24-bit data -#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size - // cannot be used with data sizes - // other than 8 -#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus -#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) -#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) -#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) -#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) -#define EPI_GPCFG_FRMCNT_S 22 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. -// -//***************************************************************************** -#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range -#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz -#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz -#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz -#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter -#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode -#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM -#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) -#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) -#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) -#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) -#define EPI_SDRAMCFG_RFSH_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG register. -// -//***************************************************************************** -#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated -#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle -#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable -#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable -#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert -#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable -#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable -#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity -#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity -#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity -#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait -#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States -#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States -#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode -#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] -#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] -#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] -#define EPI_HB8CFG_MAXWAIT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. -// -//***************************************************************************** -#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG2 register. -// -//***************************************************************************** -#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended - // Configuration -#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and - // Multiple Sub-Mode Configuration - // enable -#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration -#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration -#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration -#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration -#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration -#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity -#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity -#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity -#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration - // Register Write -#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration - // Register Read -#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode -#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States -#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States -#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode -#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_ADDRMAP register. -// -//***************************************************************************** -#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size -#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: - // 0x000.0000 to 0x0FFF.FFFF -#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address -#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 -#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size -#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address -#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 -#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 -#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS2n maps to - // 0xA000.0000 and CS3n maps to - // 0xC000.0000 -#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size -#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: - // 0x00 to 0xFF -#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: - // 0x0000 to 0xFFFF -#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: - // 0x00.0000 to 0xFF.FFFF -#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: - // 0x000.0000 to 0xFFF.FFFF -#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address -#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped -#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 -#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 -#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus - // quad chip select. In quad chip - // select mode, CS0n maps to - // 0x6000.0000 and CS1n maps to - // 0x8000.0000 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE0 register. -// -//***************************************************************************** -#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR0 register. -// -//***************************************************************************** -#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD0 register. -// -//***************************************************************************** -#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD0_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RSIZE1 register. -// -//***************************************************************************** -#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size -#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) -#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) -#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RADDR1 register. -// -//***************************************************************************** -#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address -#define EPI_RADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RPSTD1 register. -// -//***************************************************************************** -#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count -#define EPI_RPSTD1_POSTCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_STAT register. -// -//***************************************************************************** -#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full -#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty -#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence -#define EPI_STAT_WBUSY 0x00000020 // Write Busy -#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy -#define EPI_STAT_ACTIVE 0x00000001 // Register Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. -// -//***************************************************************************** -#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count -#define EPI_RFIFOCNT_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO0 -// register. -// -//***************************************************************************** -#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO1 -// register. -// -//***************************************************************************** -#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO2 -// register. -// -//***************************************************************************** -#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO3 -// register. -// -//***************************************************************************** -#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO4 -// register. -// -//***************************************************************************** -#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO4_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO5 -// register. -// -//***************************************************************************** -#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO5_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO6 -// register. -// -//***************************************************************************** -#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO6_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_READFIFO7 -// register. -// -//***************************************************************************** -#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data -#define EPI_READFIFO7_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_FIFOLVL register. -// -//***************************************************************************** -#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error -#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error -#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO -#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while - // WRFIFO is empty. -#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until - // there are only two slots - // available. Thus, trigger is - // deasserted when there are two - // WRFIFO entries present. This - // configuration is optimized for - // bursts of 2 -#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until - // there is one WRFIFO entry - // available. This configuration - // expects only single writes -#define EPI_FIFOLVL_WRFIFO_NFULL \ - 0x00000040 // Trigger interrupt when WRFIFO is - // not full, meaning trigger will - // continue to assert until there - // are four entries in the WRFIFO -#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO -#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more - // entries in the NBRFIFO -#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries - // in the NBRFIFO - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. -// -//***************************************************************************** -#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions -#define EPI_WFIFOCNT_WTAV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_DMATXCNT register. -// -//***************************************************************************** -#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count -#define EPI_DMATXCNT_TXCNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_IM register. -// -//***************************************************************************** -#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask -#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask -#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask -#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask -#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_RIS register. -// -//***************************************************************************** -#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status -#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status -#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status -#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status -#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_MIS register. -// -//***************************************************************************** -#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt - // Status -#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt - // Status -#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status -#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status -#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_EISC register. -// -//***************************************************************************** -#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear -#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear -#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error -#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error -#define EPI_EISC_TOUT 0x00000001 // Timeout Error - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG3 register. -// -//***************************************************************************** -#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG3 register. -// -//***************************************************************************** -#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity -#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity -#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration - // Register Write -#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration - // Register Read -#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode -#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States -#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States -#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode -#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16CFG4 register. -// -//***************************************************************************** -#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity -#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration - // Register Write -#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration - // Register Read -#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode -#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] -#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8CFG4 register. -// -//***************************************************************************** -#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity -#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity -#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity -#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States -#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks -#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks -#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks -#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks -#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States -#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks -#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks -#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks -#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks -#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode -#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] -#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME register. -// -//***************************************************************************** -#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB8TIME_IRDYDLY_S 24 -#define EPI_HB8TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME register. -// -//***************************************************************************** -#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay -#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture - // Width -#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One -#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One -#define EPI_HB16TIME_IRDYDLY_S 24 -#define EPI_HB16TIME_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME2 register. -// -//***************************************************************************** -#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB8TIME2_IRDYDLY_S 24 -#define EPI_HB8TIME2_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME2 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay -#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME2_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME2_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME2_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME2_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME2_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME2_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME2_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME2_CAPWIDTH_M \ - 0x00003000 // CS1n Inter-transfer Capture - // Width -#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One -#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One -#define EPI_HB16TIME2_IRDYDLY_S 24 -#define EPI_HB16TIME2_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME3 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME3_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME3_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME3_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME3_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME3_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME3_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME3_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME3_CAPWIDTH_M \ - 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB16TIME3_IRDYDLY_S 24 -#define EPI_HB16TIME3_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME3 register. -// -//***************************************************************************** -#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay -#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture - // Width -#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One -#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One -#define EPI_HB8TIME3_IRDYDLY_S 24 -#define EPI_HB8TIME3_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB8TIME4 register. -// -//***************************************************************************** -#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB8TIME4_IRDYDLY_S 24 -#define EPI_HB8TIME4_CAPWIDTH_S 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HB16TIME4 -// register. -// -//***************************************************************************** -#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay -#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size -#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation -#define EPI_HB16TIME4_PSRAMSZ_128B \ - 0x00010000 // 128 B -#define EPI_HB16TIME4_PSRAMSZ_256B \ - 0x00020000 // 256 B -#define EPI_HB16TIME4_PSRAMSZ_512B \ - 0x00030000 // 512 B -#define EPI_HB16TIME4_PSRAMSZ_1KB \ - 0x00040000 // 1024 B -#define EPI_HB16TIME4_PSRAMSZ_2KB \ - 0x00050000 // 2048 B -#define EPI_HB16TIME4_PSRAMSZ_4KB \ - 0x00060000 // 4096 B -#define EPI_HB16TIME4_PSRAMSZ_8KB \ - 0x00070000 // 8192 B -#define EPI_HB16TIME4_CAPWIDTH_M \ - 0x00003000 // CS3n Inter-transfer Capture - // Width -#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One -#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One -#define EPI_HB16TIME4_IRDYDLY_S 24 -#define EPI_HB16TIME4_CAPWIDTH_S \ - 12 - -//***************************************************************************** -// -// The following are defines for the bit fields in the EPI_O_HBPSRAM register. -// -//***************************************************************************** -#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register -#define EPI_HBPSRAM_CR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_RIS register. -// -//***************************************************************************** -#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception - // Raw Interrupt Status -#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation - // Raw Interrupt Status -#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 - // Exception Raw Interrupt Status -#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal - // Exception Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IM register. -// -//***************************************************************************** -#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception - // Interrupt Mask -#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow - // Exception Interrupt Mask -#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation - // Interrupt Mask -#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Mask -#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_MIS register. -// -//***************************************************************************** -#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception - // Masked Interrupt Status -#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation - // Masked Interrupt Status -#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 - // Exception Masked Interrupt - // Status -#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal - // Exception Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSEXC_IC register. -// -//***************************************************************************** -#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception - // Interrupt Clear -#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow - // Exception Interrupt Clear -#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation - // Interrupt Clear -#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 - // Exception Interrupt Clear -#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal - // Exception Interrupt Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCC register. -// -//***************************************************************************** -#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter -#define HIB_RTCC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCM0 register. -// -//***************************************************************************** -#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 -#define HIB_RTCM0_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCLD register. -// -//***************************************************************************** -#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load -#define HIB_RTCLD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CTL register. -// -//***************************************************************************** -#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable -#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear -#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select -#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability -#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass -#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery - // Comparator -#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts -#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) -#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts -#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts -#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status -#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery -#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered -#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable -#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable -#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable -#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable -#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request -#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IM register. -// -//***************************************************************************** -#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_IM_WC 0x00000010 // External Write Complete/Capable - // Interrupt Mask -#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask -#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Mask -#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RIS register. -// -//***************************************************************************** -#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status -#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw - // Interrupt Status -#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt - // Status -#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw - // Interrupt Status -#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt - // Status -#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw - // Interrupt Status -#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_MIS register. -// -//***************************************************************************** -#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask -#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Mask -#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask -#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked - // Interrupt Status -#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked - // Interrupt Status -#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked - // Interrupt Status -#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IC register. -// -//***************************************************************************** -#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear -#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt - // Clear -#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear -#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt - // Clear -#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear -#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt - // Clear -#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCT register. -// -//***************************************************************************** -#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value -#define HIB_RTCT_TRIM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_RTCSS register. -// -//***************************************************************************** -#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match -#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count -#define HIB_RTCSS_RTCSSM_S 16 -#define HIB_RTCSS_RTCSSC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_IO register. -// -//***************************************************************************** -#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete -#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable -#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration - // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_DATA register. -// -//***************************************************************************** -#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data -#define HIB_DATA_RTD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALCTL register. -// -//***************************************************************************** -#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode -#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL0 register. -// -//***************************************************************************** -#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CAL0_HR_M 0x001F0000 // Hours -#define HIB_CAL0_MIN_M 0x00003F00 // Minutes -#define HIB_CAL0_SEC_M 0x0000003F // Seconds -#define HIB_CAL0_HR_S 16 -#define HIB_CAL0_MIN_S 8 -#define HIB_CAL0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CAL1 register. -// -//***************************************************************************** -#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load -#define HIB_CAL1_DOW_M 0x07000000 // Day of Week -#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value -#define HIB_CAL1_MON_M 0x00000F00 // Month -#define HIB_CAL1_DOM_M 0x0000001F // Day of Month -#define HIB_CAL1_DOW_S 24 -#define HIB_CAL1_YEAR_S 16 -#define HIB_CAL1_MON_S 8 -#define HIB_CAL1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD0 register. -// -//***************************************************************************** -#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALLD0_HR_M 0x001F0000 // Hours -#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes -#define HIB_CALLD0_SEC_M 0x0000003F // Seconds -#define HIB_CALLD0_HR_S 16 -#define HIB_CALLD0_MIN_S 8 -#define HIB_CALLD0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALLD1 register. -// -//***************************************************************************** -#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week -#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value -#define HIB_CALLD1_MON_M 0x00000F00 // Month -#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month -#define HIB_CALLD1_DOW_S 24 -#define HIB_CALLD1_YEAR_S 16 -#define HIB_CALLD1_MON_S 8 -#define HIB_CALLD1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM0 register. -// -//***************************************************************************** -#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation -#define HIB_CALM0_HR_M 0x001F0000 // Hours -#define HIB_CALM0_MIN_M 0x00003F00 // Minutes -#define HIB_CALM0_SEC_M 0x0000003F // Seconds -#define HIB_CALM0_HR_S 16 -#define HIB_CALM0_MIN_S 8 -#define HIB_CALM0_SEC_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CALM1 register. -// -//***************************************************************************** -#define HIB_CALM1_DOM_M 0x0000001F // Day of Month -#define HIB_CALM1_DOM_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_LOCK register. -// -//***************************************************************************** -#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock -#define HIB_LOCK_HIBLOCK_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPCTL register. -// -//***************************************************************************** -#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper - // Event -#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event -#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on - // tamper event -#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB - // memory on tamper event -#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper - // event -#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear -#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPSTAT register. -// -//***************************************************************************** -#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status -#define HIB_TPSTAT_STATE_DISABLED \ - 0x00000000 // Tamper disabled -#define HIB_TPSTAT_STATE_CONFIGED \ - 0x00000004 // Tamper configured -#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred -#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status -#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPIO register. -// -//***************************************************************************** -#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering -#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level -#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable -#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering -#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level -#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable -#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering -#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level -#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable -#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering -#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up - // Enable -#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level -#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG0 register. -// -//***************************************************************************** -#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG0_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG1 register. -// -//***************************************************************************** -#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG2 register. -// -//***************************************************************************** -#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG2_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG3 register. -// -//***************************************************************************** -#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG4 register. -// -//***************************************************************************** -#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG4_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG5 register. -// -//***************************************************************************** -#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG6 register. -// -//***************************************************************************** -#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information -#define HIB_TPLOG6_TIME_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_TPLOG7 register. -// -//***************************************************************************** -#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 -#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger -#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger -#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger -#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_PP register. -// -//***************************************************************************** -#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence -#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence - -//***************************************************************************** -// -// The following are defines for the bit fields in the HIB_CC register. -// -//***************************************************************************** -#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMA register. -// -//***************************************************************************** -#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset -#define FLASH_FMA_OFFSET_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMD register. -// -//***************************************************************************** -#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value -#define FLASH_FMD_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit Register Value -#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory -#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory -#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw - // Interrupt Status -#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt - // Status -#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt - // Status -#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt - // Status -#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status -#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status -#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask -#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask -#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask -#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask -#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask -#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FCMISC register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and - // Clear -#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear -#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear -#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMC2 register. -// -//***************************************************************************** -#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBVAL register. -// -//***************************************************************************** -#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FLPEKEY register. -// -//***************************************************************************** -#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value -#define FLASH_FLPEKEY_PEKEY_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FWBN register. -// -//***************************************************************************** -#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_PP register. -// -//***************************************************************************** -#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode -#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode -#define FLASH_PP_DFA 0x10000000 // DMA Flash Access -#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the - // physical bank -#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB -#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB -#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB -#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB -#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the - // physical bank -#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB -#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB -#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB -#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB -#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB -#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size -#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_SSIZE register. -// -//***************************************************************************** -#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size -#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CONF register. -// -//***************************************************************************** -#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable -#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable -#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags -#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On -#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_ROMSWMAP register. -// -//***************************************************************************** -#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability -#define FLASH_ROMSWMAP_SW7EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW7EN_CORE \ - 0x00004000 // Region available to core -#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability -#define FLASH_ROMSWMAP_SW6EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW6EN_CORE \ - 0x00001000 // Region available to core -#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability -#define FLASH_ROMSWMAP_SW5EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW5EN_CORE \ - 0x00000400 // Region available to core -#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability -#define FLASH_ROMSWMAP_SW4EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW4EN_CORE \ - 0x00000100 // Region available to core -#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability -#define FLASH_ROMSWMAP_SW3EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW3EN_CORE \ - 0x00000040 // Region available to core -#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability -#define FLASH_ROMSWMAP_SW2EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW2EN_CORE \ - 0x00000010 // Region available to core -#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability -#define FLASH_ROMSWMAP_SW1EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW1EN_CORE \ - 0x00000004 // Region available to core -#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability -#define FLASH_ROMSWMAP_SW0EN_NOTVIS \ - 0x00000000 // Software region not available to - // the core -#define FLASH_ROMSWMAP_SW0EN_CORE \ - 0x00000001 // Region available to core - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMASZ register. -// -//***************************************************************************** -#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size -#define FLASH_DMASZ_SIZE_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_DMAST register. -// -//***************************************************************************** -#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of - // the flash region accessible by - // uDMA if the FLASHPP register DFA - // bit is set -#define FLASH_DMAST_ADDR_S 11 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_RVP register. -// -//***************************************************************************** -#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address -#define FLASH_RVP_RV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_BOOTCFG register. -// -//***************************************************************************** -#define FLASH_BOOTCFG_NW 0x80000000 // Not Written -#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port -#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A -#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B -#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C -#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D -#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E -#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F -#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G -#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H -#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin -#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 -#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 -#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 -#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 -#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 -#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 -#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 -#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 -#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity -#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable -#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select -#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 -#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG0 register. -// -//***************************************************************************** -#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG0_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG1 register. -// -//***************************************************************************** -#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG1_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG2 register. -// -//***************************************************************************** -#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG2_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_USERREG3 register. -// -//***************************************************************************** -#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data -#define FLASH_USERREG3_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE8 register. -// -//***************************************************************************** -#define FLASH_FMPRE8_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE8_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE9 register. -// -//***************************************************************************** -#define FLASH_FMPRE9_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE9_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE10 register. -// -//***************************************************************************** -#define FLASH_FMPRE10_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE10_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE11 register. -// -//***************************************************************************** -#define FLASH_FMPRE11_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE11_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE12 register. -// -//***************************************************************************** -#define FLASH_FMPRE12_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE12_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE13 register. -// -//***************************************************************************** -#define FLASH_FMPRE13_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE13_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE14 register. -// -//***************************************************************************** -#define FLASH_FMPRE14_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE14_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPRE15 register. -// -//***************************************************************************** -#define FLASH_FMPRE15_READ_ENABLE_M \ - 0xFFFFFFFF // Flash Read Enable -#define FLASH_FMPRE15_READ_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE8 register. -// -//***************************************************************************** -#define FLASH_FMPPE8_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE8_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE9 register. -// -//***************************************************************************** -#define FLASH_FMPPE9_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE9_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE10 register. -// -//***************************************************************************** -#define FLASH_FMPPE10_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE10_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE11 register. -// -//***************************************************************************** -#define FLASH_FMPPE11_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE11_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE12 register. -// -//***************************************************************************** -#define FLASH_FMPPE12_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE12_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE13 register. -// -//***************************************************************************** -#define FLASH_FMPPE13_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE13_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE14 register. -// -//***************************************************************************** -#define FLASH_FMPPE14_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE14_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the FLASH_FMPPE15 register. -// -//***************************************************************************** -#define FLASH_FMPPE15_PROG_ENABLE_M \ - 0xFFFFFFFF // Flash Programming Enable -#define FLASH_FMPPE15_PROG_ENABLE_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version -#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 - // register format. -#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class -#define SYSCTL_DID0_CLASS_TM4C129 \ - 0x000A0000 // Tiva(TM) TM4C129-class - // microcontrollers -#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision -#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) -#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer - // revision) -#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer - // revision) -#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision -#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major - // revision update -#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change -#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version -#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib -#define SYSCTL_DID1_FAM_M 0x0F000000 // Family -#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers -#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number -#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \ - 0x001F0000 // TM4C1294NCPDT -#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count -#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package -#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package -#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package -#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package -#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package -#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range -#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range -#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type -#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package -#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package -#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance -#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PTBOCTL register. -// -//***************************************************************************** -#define SYSCTL_PTBOCTL_VDDA_UBOR_M \ - 0x00000300 // VDDA under BOR Event Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ - 0x00000100 // System control interrupt -#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ - 0x00000200 // NMI -#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ - 0x00000300 // Reset -#define SYSCTL_PTBOCTL_VDD_UBOR_M \ - 0x00000003 // VDD (VDDS) under BOR Event - // Action -#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ - 0x00000000 // No Action -#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ - 0x00000001 // System control interrupt -#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ - 0x00000002 // NMI -#define SYSCTL_PTBOCTL_VDD_UBOR_RST \ - 0x00000003 // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RIS register. -// -//***************************************************************************** -#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt - // Status -#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status -#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw - // Interrupt Status -#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_IMC register. -// -//***************************************************************************** -#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask -#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask -#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure - // Interrupt Mask -#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MISC register. -// -//***************************************************************************** -#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt - // Status -#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status -#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked - // Interrupt Status -#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset -#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset -#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset -#define SYSCTL_RESC_SW 0x00000010 // Software Reset -#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset -#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset -#define SYSCTL_RESC_EXT 0x00000001 // External Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PWRTC register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status -#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NMIC register. -// -//***************************************************************************** -#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI -#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI -#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI -#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI -#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI -#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. -// -//***************************************************************************** -#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range -#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down -#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected -#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action -#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update -#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept -#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating -#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL -#define SYSCTL_RSCLKCFG_PLLSRC_M \ - 0x0F000000 // PLL Source -#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ - 0x00000000 // PIOSC is PLL input clock source -#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ - 0x03000000 // MOSC is the PLL input clock - // source -#define SYSCTL_RSCLKCFG_OSCSRC_M \ - 0x00F00000 // Oscillator Source -#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ - 0x00000000 // PIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ - 0x00200000 // LFIOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ - 0x00300000 // MOSC is oscillator source -#define SYSCTL_RSCLKCFG_OSCSRC_RTC \ - 0x00400000 // Hibernation Module RTC - // Oscillator (RTCOSC) -#define SYSCTL_RSCLKCFG_OSYSDIV_M \ - 0x000FFC00 // Oscillator System Clock Divisor -#define SYSCTL_RSCLKCFG_PSYSDIV_M \ - 0x000003FF // PLL System Clock Divisor -#define SYSCTL_RSCLKCFG_OSYSDIV_S \ - 10 -#define SYSCTL_RSCLKCFG_PSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register. -// -//***************************************************************************** -#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time -#define SYSCTL_MEMTIM0_EBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period -#define SYSCTL_MEMTIM0_EBCHT_1_5 \ - 0x00800000 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_2_5 \ - 0x01000000 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_3_5 \ - 0x01800000 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods -#define SYSCTL_MEMTIM0_EBCHT_4_5 \ - 0x02000000 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge -#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States -#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time -#define SYSCTL_MEMTIM0_FBCHT_0_5 \ - 0x00000000 // 1/2 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period -#define SYSCTL_MEMTIM0_FBCHT_1_5 \ - 0x00000080 // 1.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_2_5 \ - 0x00000100 // 2.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_3_5 \ - 0x00000180 // 3.5 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods -#define SYSCTL_MEMTIM0_FBCHT_4_5 \ - 0x00000200 // 4.5 system clock periods -#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge -#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State -#define SYSCTL_MEMTIM0_EWS_S 16 -#define SYSCTL_MEMTIM0_FWS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_ALTCLKCFG_ALTCLK_M \ - 0x0000000F // Alternate Clock Source -#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ - 0x00000003 // Hibernation Module Real-time - // clock output (RTCOSC) -#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ - 0x00000004 // Low-frequency internal - // oscillator (LFIOSC) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSCLKCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down -#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down -#define SYSCTL_DSCLKCFG_DSOSCSRC_M \ - 0x00F00000 // Deep Sleep Oscillator Source -#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ - 0x00000000 // PIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ - 0x00200000 // LFIOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ - 0x00300000 // MOSC -#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ - 0x00400000 // Hibernation Module RTCOSC -#define SYSCTL_DSCLKCFG_DSSYSDIV_M \ - 0x000003FF // Deep Sleep Clock Divisor -#define SYSCTL_DSCLKCFG_DSSYSDIV_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DIVSCLK register. -// -//***************************************************************************** -#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable -#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source -#define SYSCTL_DIVSCLK_SRC_SYSCLK \ - 0x00000000 // System Clock -#define SYSCTL_DIVSCLK_SRC_PIOSC \ - 0x00010000 // PIOSC -#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC -#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value -#define SYSCTL_DIVSCLK_DIV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SYSPROP register. -// -//***************************************************************************** -#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCCAL -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value -#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration -#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim -#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value -#define SYSCTL_PIOSCCAL_UT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT -// register. -// -//***************************************************************************** -#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value -#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result -#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been - // attempted -#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation - // completed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation - // failed to meet 1% accuracy -#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value -#define SYSCTL_PIOSCSTAT_DT_S 16 -#define SYSCTL_PIOSCSTAT_CT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power -#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value -#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value -#define SYSCTL_PLLFREQ0_MFRAC_S 10 -#define SYSCTL_PLLFREQ0_MINT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 -// register. -// -//***************************************************************************** -#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value -#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value -#define SYSCTL_PLLFREQ1_Q_S 8 -#define SYSCTL_PLLFREQ1_N_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. -// -//***************************************************************************** -#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_SLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG -// register. -// -//***************************************************************************** -#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode -#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down -#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ - 0x00000030 // Flash Power Modes -#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ - 0x00000020 // Low Power Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ - 0x00000003 // SRAM Power Modes -#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ - 0x00000000 // Active Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ - 0x00000001 // Standby Mode -#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ - 0x00000003 // Low Power Mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. -// -//***************************************************************************** -#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer - // Available - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDOSPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDOSPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDOSPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDOSPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDOSPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDOSPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDOSPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDOSPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_LDODPCTL -// register. -// -//***************************************************************************** -#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable -#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage -#define SYSCTL_LDODPCTL_VLDO_0_90V \ - 0x00000012 // 0.90 V -#define SYSCTL_LDODPCTL_VLDO_0_95V \ - 0x00000013 // 0.95 V -#define SYSCTL_LDODPCTL_VLDO_1_00V \ - 0x00000014 // 1.00 V -#define SYSCTL_LDODPCTL_VLDO_1_05V \ - 0x00000015 // 1.05 V -#define SYSCTL_LDODPCTL_VLDO_1_10V \ - 0x00000016 // 1.10 V -#define SYSCTL_LDODPCTL_VLDO_1_15V \ - 0x00000017 // 1.15 V -#define SYSCTL_LDODPCTL_VLDO_1_20V \ - 0x00000018 // 1.20 V -#define SYSCTL_LDODPCTL_VLDO_1_25V \ - 0x00000019 // 1.25 V -#define SYSCTL_LDODPCTL_VLDO_1_30V \ - 0x0000001A // 1.30 V -#define SYSCTL_LDODPCTL_VLDO_1_35V \ - 0x0000001B // 1.35 V - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL -// register. -// -//***************************************************************************** -#define SYSCTL_RESBEHAVCTL_WDOG1_M \ - 0x000000C0 // Watchdog 1 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ - 0x00000080 // Watchdog 1 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG1_POR \ - 0x000000C0 // Watchdog 1 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_WDOG0_M \ - 0x00000030 // Watchdog 0 Reset Operation -#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ - 0x00000020 // Watchdog 0 issues a system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_WDOG0_POR \ - 0x00000030 // Watchdog 0 issues a simulated - // POR sequence. Application starts - // less than 500 us after - // deassertion (Default) -#define SYSCTL_RESBEHAVCTL_BOR_M \ - 0x0000000C // BOR Reset operation -#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ - 0x00000008 // Brown Out Reset issues system - // reset. The application starts - // within 10 us -#define SYSCTL_RESBEHAVCTL_BOR_POR \ - 0x0000000C // Brown Out Reset issues a - // simulated POR sequence. The - // application starts less than 500 - // us after deassertion (Default) -#define SYSCTL_RESBEHAVCTL_EXTRES_M \ - 0x00000003 // External RST Pin Operation -#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ - 0x00000002 // External RST assertion issues a - // system reset. The application - // starts within 10 us -#define SYSCTL_RESBEHAVCTL_EXTRES_POR \ - 0x00000003 // External RST assertion issues a - // simulated POR sequence. - // Application starts less than 500 - // us after deassertion (Default) - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_HSSR register. -// -//***************************************************************************** -#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key -#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer -#define SYSCTL_HSSR_KEY_S 24 -#define SYSCTL_HSSR_CDOFF_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBPDS register. -// -//***************************************************************************** -#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status -#define SYSCTL_USBPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBPDS_MEMSTAT_RETAIN \ - 0x00000004 // SRAM Retention -#define SYSCTL_USBPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status -#define SYSCTL_USBPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_USBPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_USBMPC register. -// -//***************************************************************************** -#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_USBMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_USBMPC_PWRCTL_RETAIN \ - 0x00000001 // SRAM Retention -#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACPDS register. -// -//***************************************************************************** -#define SYSCTL_EMACPDS_MEMSTAT_M \ - 0x0000000C // Memory Array Power Status -#define SYSCTL_EMACPDS_MEMSTAT_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACPDS_MEMSTAT_ON \ - 0x0000000C // Array On -#define SYSCTL_EMACPDS_PWRSTAT_M \ - 0x00000003 // Power Domain Status -#define SYSCTL_EMACPDS_PWRSTAT_OFF \ - 0x00000000 // OFF -#define SYSCTL_EMACPDS_PWRSTAT_ON \ - 0x00000003 // ON - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_EMACMPC register. -// -//***************************************************************************** -#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control -#define SYSCTL_EMACMPC_PWRCTL_OFF \ - 0x00000000 // Array OFF -#define SYSCTL_EMACMPC_PWRCTL_ON \ - 0x00000003 // Array On - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWD register. -// -//***************************************************************************** -#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present -#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPTIMER register. -// -//***************************************************************************** -#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Present -#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Present -#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Present -#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Present -#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Present -#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Present -#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Present -#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPGPIO register. -// -//***************************************************************************** -#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present -#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present -#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present -#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present -#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present -#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present -#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present -#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present -#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present -#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present -#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present -#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present -#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present -#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present -#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPDMA register. -// -//***************************************************************************** -#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPI register. -// -//***************************************************************************** -#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIB register. -// -//***************************************************************************** -#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUART register. -// -//***************************************************************************** -#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present -#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present -#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present -#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present -#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present -#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present -#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present -#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPSSI register. -// -//***************************************************************************** -#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present -#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present -#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present -#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPI2C register. -// -//***************************************************************************** -#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present -#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present -#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present -#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present -#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present -#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present -#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present -#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present -#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present -#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPUSB register. -// -//***************************************************************************** -#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEPHY register. -// -//***************************************************************************** -#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCAN register. -// -//***************************************************************************** -#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present -#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPADC register. -// -//***************************************************************************** -#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present -#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPACMP register. -// -//***************************************************************************** -#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPWM register. -// -//***************************************************************************** -#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPQEI register. -// -//***************************************************************************** -#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLPC register. -// -//***************************************************************************** -#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPPECI register. -// -//***************************************************************************** -#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPFAN register. -// -//***************************************************************************** -#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPWTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose - // Timer 0 Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPRTS register. -// -//***************************************************************************** -#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPCCM register. -// -//***************************************************************************** -#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPLCD register. -// -//***************************************************************************** -#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPOWIRE register. -// -//***************************************************************************** -#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPEMAC register. -// -//***************************************************************************** -#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module - // Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PPHIM register. -// -//***************************************************************************** -#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRWD register. -// -//***************************************************************************** -#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset -#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRTIMER register. -// -//***************************************************************************** -#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Software Reset -#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Software Reset -#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Software Reset -#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Software Reset -#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Software Reset -#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Software Reset -#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Software Reset -#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRGPIO register. -// -//***************************************************************************** -#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset -#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset -#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset -#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset -#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset -#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset -#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset -#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset -#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset -#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset -#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset -#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset -#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset -#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset -#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRDMA register. -// -//***************************************************************************** -#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPI register. -// -//***************************************************************************** -#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRHIB register. -// -//***************************************************************************** -#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUART register. -// -//***************************************************************************** -#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset -#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset -#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset -#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset -#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset -#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset -#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset -#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRSSI register. -// -//***************************************************************************** -#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset -#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset -#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset -#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRI2C register. -// -//***************************************************************************** -#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset -#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset -#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset -#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset -#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset -#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset -#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset -#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset -#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset -#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRUSB register. -// -//***************************************************************************** -#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREPHY register. -// -//***************************************************************************** -#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software - // Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCAN register. -// -//***************************************************************************** -#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset -#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRADC register. -// -//***************************************************************************** -#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset -#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRACMP register. -// -//***************************************************************************** -#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRPWM register. -// -//***************************************************************************** -#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRQEI register. -// -//***************************************************************************** -#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SRCCM register. -// -//***************************************************************************** -#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SREMAC register. -// -//***************************************************************************** -#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 - // Software Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCWD register. -// -//***************************************************************************** -#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Run Mode Clock Gating Control -#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock - // Gating Control -#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCADC register. -// -//***************************************************************************** -#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock - // Gating Control -#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Run Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_RCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCWD register. -// -//***************************************************************************** -#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode - // Clock Gating Control -#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Sleep Mode Clock Gating - // Control -#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCADC register. -// -//***************************************************************************** -#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock - // Gating Control -#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules - // Sleep Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_SCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCWD register. -// -//***************************************************************************** -#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCTIMER -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Deep-Sleep Mode Clock Gating - // Control -#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCGPIO -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. -// -//***************************************************************************** -#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPI register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. -// -//***************************************************************************** -#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUART -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. -// -//***************************************************************************** -#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. -// -//***************************************************************************** -#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. -// -//***************************************************************************** -#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEPHY -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock - // Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. -// -//***************************************************************************** -#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCADC register. -// -//***************************************************************************** -#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode - // Clock Gating Control -#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCACMP -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. -// -//***************************************************************************** -#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. -// -//***************************************************************************** -#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode - // Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCCCM register. -// -//***************************************************************************** -#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules - // Deep-Sleep Mode Clock Gating - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_DCGCEMAC -// register. -// -//***************************************************************************** -#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep - // Mode Clock Gating Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCWD register. -// -//***************************************************************************** -#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control -#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCTIMER register. -// -//***************************************************************************** -#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power - // Control -#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power - // Control -#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power - // Control -#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power - // Control -#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power - // Control -#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power - // Control -#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power - // Control -#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCGPIO register. -// -//***************************************************************************** -#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control -#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control -#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control -#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control -#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control -#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control -#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control -#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control -#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control -#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control -#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control -#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control -#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control -#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control -#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCDMA register. -// -//***************************************************************************** -#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPI register. -// -//***************************************************************************** -#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCHIB register. -// -//***************************************************************************** -#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUART register. -// -//***************************************************************************** -#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control -#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control -#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control -#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control -#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control -#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control -#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control -#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCSSI register. -// -//***************************************************************************** -#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control -#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control -#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control -#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCI2C register. -// -//***************************************************************************** -#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control -#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control -#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control -#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control -#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control -#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control -#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control -#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control -#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control -#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCUSB register. -// -//***************************************************************************** -#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEPHY register. -// -//***************************************************************************** -#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCAN register. -// -//***************************************************************************** -#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control -#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCADC register. -// -//***************************************************************************** -#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control -#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCACMP register. -// -//***************************************************************************** -#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCPWM register. -// -//***************************************************************************** -#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCQEI register. -// -//***************************************************************************** -#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCCCM register. -// -//***************************************************************************** -#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules - // Power Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PCEMAC register. -// -//***************************************************************************** -#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power - // Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRWD register. -// -//***************************************************************************** -#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral - // Ready -#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRTIMER register. -// -//***************************************************************************** -#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer - // 7 Peripheral Ready -#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer - // 6 Peripheral Ready -#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer - // 5 Peripheral Ready -#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer - // 4 Peripheral Ready -#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer - // 3 Peripheral Ready -#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer - // 2 Peripheral Ready -#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer - // 1 Peripheral Ready -#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer - // 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRGPIO register. -// -//***************************************************************************** -#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready -#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready -#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready -#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready -#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready -#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready -#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready -#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready -#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready -#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready -#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready -#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready -#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready -#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready -#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRDMA register. -// -//***************************************************************************** -#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPI register. -// -//***************************************************************************** -#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRHIB register. -// -//***************************************************************************** -#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUART register. -// -//***************************************************************************** -#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready -#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready -#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready -#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready -#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready -#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready -#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready -#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRSSI register. -// -//***************************************************************************** -#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready -#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready -#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready -#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRI2C register. -// -//***************************************************************************** -#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready -#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready -#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready -#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready -#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready -#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready -#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready -#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready -#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready -#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRUSB register. -// -//***************************************************************************** -#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREPHY register. -// -//***************************************************************************** -#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCAN register. -// -//***************************************************************************** -#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready -#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRADC register. -// -//***************************************************************************** -#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready -#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRACMP register. -// -//***************************************************************************** -#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRPWM register. -// -//***************************************************************************** -#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRQEI register. -// -//***************************************************************************** -#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREEPROM -// register. -// -//***************************************************************************** -#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PRCCM register. -// -//***************************************************************************** -#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules - // Peripheral Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the SYSCTL_PREMAC register. -// -//***************************************************************************** -#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral - // Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_STAT register. -// -//***************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status -#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle -#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data -#define UDMA_STAT_STATE_RD_SRCENDP \ - 0x00000020 // Reading source end pointer -#define UDMA_STAT_STATE_RD_DSTENDP \ - 0x00000030 // Reading destination end pointer -#define UDMA_STAT_STATE_RD_SRCDAT \ - 0x00000040 // Reading source data -#define UDMA_STAT_STATE_WR_DSTDAT \ - 0x00000050 // Writing destination data -#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to - // clear -#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data -#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled -#define UDMA_STAT_STATE_DONE 0x00000090 // Done -#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -#define UDMA_STAT_DMACHANS_S 16 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CFG register. -// -//***************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CTLBASE register. -// -//***************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTBASE register. -// -//***************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_WAITSTAT register. -// -//***************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_SWREQ register. -// -//***************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTSET -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_USEBURSTCLR -// register. -// -//***************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKSET -// register. -// -//***************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_REQMASKCLR -// register. -// -//***************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENASET register. -// -//***************************************************************************** -#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ENACLR register. -// -//***************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTSET register. -// -//***************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ALTCLR register. -// -//***************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOSET register. -// -//***************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_PRIOCLR register. -// -//***************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_ERRCLR register. -// -//***************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHASGN register. -// -//***************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel - // assignment -#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel - // assignment - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP0 register. -// -//***************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP1 register. -// -//***************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP2 register. -// -//***************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_CHMAP3 register. -// -//***************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access -#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCCTRL register. -// -//***************************************************************************** -#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization -#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context - // as the starting value -#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s' -#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s' -#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size -#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable -#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable -#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable -#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control -#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3, - // B2, B1, B0) -#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words - // but half-words are not swapped - // (B2, B3, B0, B1) -#define CCM_CRCCTRL_ENDIAN_SHWNB \ - 0x00000020 // Half-words are swapped but bytes - // are not swapped in half-word. - // (B1, B0, B3, B2) -#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words - // and half-words are swapped. (B0, - // B1, B2, B3) -#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type -#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005 -#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CCM_CRCCTRL_TYPE_P4C11DB7 \ - 0x00000002 // Polynomial 0x4C11DB7 -#define CCM_CRCCTRL_TYPE_P1EDC6F41 \ - 0x00000003 // Polynomial 0x1EDC6F41 -#define CCM_CRCCTRL_TYPE_TCPCHKSUM \ - 0x00000008 // TCP checksum - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCSEED register. -// -//***************************************************************************** -#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value -#define CCM_CRCSEED_SEED_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCDIN register. -// -//***************************************************************************** -#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input -#define CCM_CRCDIN_DATAIN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the CCM_O_CRCRSLTPP -// register. -// -//***************************************************************************** -#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result -#define CCM_CRCRSLTPP_RSLTPP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating - // Point -#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPAC register. -// -//***************************************************************************** -#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only -#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access -#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access - // Privilege -#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied -#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only -#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCC register. -// -//***************************************************************************** -#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation - // Enable -#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable -#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready -#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready -#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready -#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready -#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode -#define NVIC_FPCC_USER 0x00000002 // User Privilege Level -#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPCA register. -// -//***************************************************************************** -#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address -#define NVIC_FPCA_ADDRESS_S 3 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FPDSC register. -// -//***************************************************************************** -#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default -#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default -#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default -#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default -#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode -#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) - // mode -#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity - // (RM) mode -#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED -#define SYSCTL_DID0_CLASS_SNOWFLAKE \ - 0x000A0000 // Tiva(TM) C Series TM4C129-class - // microcontrollers - -//***************************************************************************** -// -// Deprecated defines for the bit fields in the SYSCTL_PWRTC register. -// -//***************************************************************************** -#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status -#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status - -#endif - -#endif // __TM4C1294NCPDT_H__ diff --git a/bsp/tm4c129x-dk/libraries/startup/startup_ewarm.c b/bsp/tm4c129x-dk/libraries/startup/startup_ewarm.c deleted file mode 100644 index a5dbd78756..0000000000 --- a/bsp/tm4c129x-dk/libraries/startup/startup_ewarm.c +++ /dev/null @@ -1,302 +0,0 @@ -//***************************************************************************** -// -// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, -// version 5. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -// -//***************************************************************************** - -#include -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" - -//***************************************************************************** -// -// Enable the IAR extensions for this source file. -// -//***************************************************************************** -#pragma language=extended - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application startup code. -// -//***************************************************************************** -extern void __iar_program_start(void); -extern void PendSV_Handler(void); -extern void SysTick_Handler(void); -extern void UART0_IRQHandler(void); -extern void HardFault_Handler(void); -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -static uint32_t pui32Stack[128] @ ".noinit"; - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - uint32_t ui32Ptr; -} -uVectorEntry; - -//***************************************************************************** -// -// The vector table. Note that the proper constructs must be placed on this to -// ensure that it ends up at physical address 0x0000.0000. -// -//***************************************************************************** -__root const uVectorEntry __vector_table[] @ ".intvec" = -{ - { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) }, - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - HardFault_Handler, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, //IntDefaultHandler, // The PendSV handler - SysTick_Handler,//IntDefaultHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - UART0_IRQHandler, //IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI0 Rx and Tx - IntDefaultHandler, // I2C0 Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder 0 - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // Ethernet - IntDefaultHandler, // Hibernate - IntDefaultHandler, // USB0 - IntDefaultHandler, // PWM Generator 3 - IntDefaultHandler, // uDMA Software Transfer - IntDefaultHandler, // uDMA Error - IntDefaultHandler, // ADC1 Sequence 0 - IntDefaultHandler, // ADC1 Sequence 1 - IntDefaultHandler, // ADC1 Sequence 2 - IntDefaultHandler, // ADC1 Sequence 3 - IntDefaultHandler, // External Bus Interface 0 - IntDefaultHandler, // GPIO Port J - IntDefaultHandler, // GPIO Port K - IntDefaultHandler, // GPIO Port L - IntDefaultHandler, // SSI2 Rx and Tx - IntDefaultHandler, // SSI3 Rx and Tx - IntDefaultHandler, // UART3 Rx and Tx - IntDefaultHandler, // UART4 Rx and Tx - IntDefaultHandler, // UART5 Rx and Tx - IntDefaultHandler, // UART6 Rx and Tx - IntDefaultHandler, // UART7 Rx and Tx - IntDefaultHandler, // I2C2 Master and Slave - IntDefaultHandler, // I2C3 Master and Slave - IntDefaultHandler, // Timer 4 subtimer A - IntDefaultHandler, // Timer 4 subtimer B - IntDefaultHandler, // Timer 5 subtimer A - IntDefaultHandler, // Timer 5 subtimer B - IntDefaultHandler, // FPU - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // I2C4 Master and Slave - IntDefaultHandler, // I2C5 Master and Slave - IntDefaultHandler, // GPIO Port M - IntDefaultHandler, // GPIO Port N - 0, // Reserved - IntDefaultHandler, // Tamper - IntDefaultHandler, // GPIO Port P (Summary or P0) - IntDefaultHandler, // GPIO Port P1 - IntDefaultHandler, // GPIO Port P2 - IntDefaultHandler, // GPIO Port P3 - IntDefaultHandler, // GPIO Port P4 - IntDefaultHandler, // GPIO Port P5 - IntDefaultHandler, // GPIO Port P6 - IntDefaultHandler, // GPIO Port P7 - IntDefaultHandler, // GPIO Port Q (Summary or Q0) - IntDefaultHandler, // GPIO Port Q1 - IntDefaultHandler, // GPIO Port Q2 - IntDefaultHandler, // GPIO Port Q3 - IntDefaultHandler, // GPIO Port Q4 - IntDefaultHandler, // GPIO Port Q5 - IntDefaultHandler, // GPIO Port Q6 - IntDefaultHandler, // GPIO Port Q7 - IntDefaultHandler, // GPIO Port R - IntDefaultHandler, // GPIO Port S - IntDefaultHandler, // SHA/MD5 0 - IntDefaultHandler, // AES 0 - IntDefaultHandler, // DES3DES 0 - IntDefaultHandler, // LCD Controller 0 - IntDefaultHandler, // Timer 6 subtimer A - IntDefaultHandler, // Timer 6 subtimer B - IntDefaultHandler, // Timer 7 subtimer A - IntDefaultHandler, // Timer 7 subtimer B - IntDefaultHandler, // I2C6 Master and Slave - IntDefaultHandler, // I2C7 Master and Slave - IntDefaultHandler, // HIM Scan Matrix Keyboard 0 - IntDefaultHandler, // One Wire 0 - IntDefaultHandler, // HIM PS/2 0 - IntDefaultHandler, // HIM LED Sequencer 0 - IntDefaultHandler, // HIM Consumer IR 0 - IntDefaultHandler, // I2C8 Master and Slave - IntDefaultHandler, // I2C9 Master and Slave - IntDefaultHandler // GPIO Port T -}; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - // - // Enable the floating-point unit. This must be done here to handle the - // case where main() uses floating-point and the function prologue saves - // floating-point registers (which will fault if floating-point is not - // enabled). Any configuration of the floating-point unit using DriverLib - // APIs must be done here prior to the floating-point unit being enabled. - // - // Note that this does not use DriverLib since it might not be included in - // this project. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); - - // - // Call the application's entry point. - // - __iar_program_start(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/bsp/tm4c129x-dk/libraries/startup/startup_gcc.c b/bsp/tm4c129x-dk/libraries/startup/startup_gcc.c deleted file mode 100644 index 9f20837e51..0000000000 --- a/bsp/tm4c129x-dk/libraries/startup/startup_gcc.c +++ /dev/null @@ -1,319 +0,0 @@ -//***************************************************************************** -// -// startup_gcc.c - Startup code for use with GNU tools. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -// -//***************************************************************************** - -#include -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); - -extern void SysTick_Handler(void); -extern void PendSV_Handler(void); -extern void UART0_IRQHandler(void); -extern void HardFault_Handler(void); -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -static uint32_t pui32Stack[64]; - -//***************************************************************************** -// -// The vector table. Note that the proper constructs must be placed on this to -// ensure that it ends up at physical address 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)), - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - HardFault_Handler, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - UART0_IRQHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI0 Rx and Tx - IntDefaultHandler, // I2C0 Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder 0 - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // Ethernet - IntDefaultHandler, // Hibernate - IntDefaultHandler, // USB0 - IntDefaultHandler, // PWM Generator 3 - IntDefaultHandler, // uDMA Software Transfer - IntDefaultHandler, // uDMA Error - IntDefaultHandler, // ADC1 Sequence 0 - IntDefaultHandler, // ADC1 Sequence 1 - IntDefaultHandler, // ADC1 Sequence 2 - IntDefaultHandler, // ADC1 Sequence 3 - IntDefaultHandler, // External Bus Interface 0 - IntDefaultHandler, // GPIO Port J - IntDefaultHandler, // GPIO Port K - IntDefaultHandler, // GPIO Port L - IntDefaultHandler, // SSI2 Rx and Tx - IntDefaultHandler, // SSI3 Rx and Tx - IntDefaultHandler, // UART3 Rx and Tx - IntDefaultHandler, // UART4 Rx and Tx - IntDefaultHandler, // UART5 Rx and Tx - IntDefaultHandler, // UART6 Rx and Tx - IntDefaultHandler, // UART7 Rx and Tx - IntDefaultHandler, // I2C2 Master and Slave - IntDefaultHandler, // I2C3 Master and Slave - IntDefaultHandler, // Timer 4 subtimer A - IntDefaultHandler, // Timer 4 subtimer B - IntDefaultHandler, // Timer 5 subtimer A - IntDefaultHandler, // Timer 5 subtimer B - IntDefaultHandler, // FPU - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // I2C4 Master and Slave - IntDefaultHandler, // I2C5 Master and Slave - IntDefaultHandler, // GPIO Port M - IntDefaultHandler, // GPIO Port N - 0, // Reserved - IntDefaultHandler, // Tamper - IntDefaultHandler, // GPIO Port P (Summary or P0) - IntDefaultHandler, // GPIO Port P1 - IntDefaultHandler, // GPIO Port P2 - IntDefaultHandler, // GPIO Port P3 - IntDefaultHandler, // GPIO Port P4 - IntDefaultHandler, // GPIO Port P5 - IntDefaultHandler, // GPIO Port P6 - IntDefaultHandler, // GPIO Port P7 - IntDefaultHandler, // GPIO Port Q (Summary or Q0) - IntDefaultHandler, // GPIO Port Q1 - IntDefaultHandler, // GPIO Port Q2 - IntDefaultHandler, // GPIO Port Q3 - IntDefaultHandler, // GPIO Port Q4 - IntDefaultHandler, // GPIO Port Q5 - IntDefaultHandler, // GPIO Port Q6 - IntDefaultHandler, // GPIO Port Q7 - IntDefaultHandler, // GPIO Port R - IntDefaultHandler, // GPIO Port S - IntDefaultHandler, // SHA/MD5 0 - IntDefaultHandler, // AES 0 - IntDefaultHandler, // DES3DES 0 - IntDefaultHandler, // LCD Controller 0 - IntDefaultHandler, // Timer 6 subtimer A - IntDefaultHandler, // Timer 6 subtimer B - IntDefaultHandler, // Timer 7 subtimer A - IntDefaultHandler, // Timer 7 subtimer B - IntDefaultHandler, // I2C6 Master and Slave - IntDefaultHandler, // I2C7 Master and Slave - IntDefaultHandler, // HIM Scan Matrix Keyboard 0 - IntDefaultHandler, // One Wire 0 - IntDefaultHandler, // HIM PS/2 0 - IntDefaultHandler, // HIM LED Sequencer 0 - IntDefaultHandler, // HIM Consumer IR 0 - IntDefaultHandler, // I2C8 Master and Slave - IntDefaultHandler, // I2C9 Master and Slave - IntDefaultHandler // GPIO Port T -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern uint32_t _sidata; -extern uint32_t _sdata; -extern uint32_t _edata; -extern uint32_t _sbss; -extern uint32_t _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - uint32_t *pui32Src, *pui32Dest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pui32Src = &_sidata; - for(pui32Dest = &_sdata; pui32Dest < &_edata; ) - { - *pui32Dest++ = *pui32Src++; - } - - // - // Zero fill the bss segment. - // - __asm(" ldr r0, =_sbss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - - // - // Enable the floating-point unit. This must be done here to handle the - // case where main() uses floating-point and the function prologue saves - // floating-point registers (which will fault if floating-point is not - // enabled). Any configuration of the floating-point unit using DriverLib - // APIs must be done here prior to the floating-point unit being enabled. - // - // Note that this does not use DriverLib since it might not be included in - // this project. - // - HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) & - ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) | - NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL); - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/bsp/tm4c129x-dk/libraries/startup/startup_rvmdk.S b/bsp/tm4c129x-dk/libraries/startup/startup_rvmdk.S deleted file mode 100644 index 3554d00143..0000000000 --- a/bsp/tm4c129x-dk/libraries/startup/startup_rvmdk.S +++ /dev/null @@ -1,324 +0,0 @@ -; <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** -; -; startup_rvmdk.S - Startup code for use with Keil's uVision. -; -; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -; Software License Agreement -; -; Texas Instruments (TI) is supplying this software for use solely and -; exclusively on TI's microcontroller products. The software is owned by -; TI and/or its suppliers, and is protected under applicable copyright -; laws. You may not combine this software with "viral" open-source -; software in order to form a larger program. -; -; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -; DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -; -;****************************************************************************** - -;****************************************************************************** -; -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Stack EQU 0x00000200 - -;****************************************************************************** -; -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Heap EQU 0x00000000 - -;****************************************************************************** -; -; Allocate space for the stack. -; -;****************************************************************************** - AREA STACK, NOINIT, READWRITE, ALIGN=3 -StackMem - SPACE Stack -__initial_sp - -;****************************************************************************** -; -; Allocate space for the heap. -; -;****************************************************************************** - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -HeapMem - SPACE Heap -__heap_limit - -;****************************************************************************** -; -; Indicate that the code in this file preserves 8-byte alignment of the stack. -; -;****************************************************************************** - PRESERVE8 - -;****************************************************************************** -; -; Place code into the reset code section. -; -;****************************************************************************** - AREA RESET, CODE, READONLY - THUMB - -;****************************************************************************** -; -; The vector table. -; -;****************************************************************************** - EXPORT __Vectors -__Vectors - DCD StackMem + Stack ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NmiSR ; NMI Handler - DCD FaultISR ; Hard Fault Handler - DCD IntDefaultHandler ; The MPU fault handler - DCD IntDefaultHandler ; The bus fault handler - DCD IntDefaultHandler ; The usage fault handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; SVCall handler - DCD IntDefaultHandler ; Debug monitor handler - DCD 0 ; Reserved - DCD IntDefaultHandler ; The PendSV handler - DCD IntDefaultHandler ; The SysTick handler - DCD IntDefaultHandler ; GPIO Port A - DCD IntDefaultHandler ; GPIO Port B - DCD IntDefaultHandler ; GPIO Port C - DCD IntDefaultHandler ; GPIO Port D - DCD IntDefaultHandler ; GPIO Port E - DCD IntDefaultHandler ; UART0 Rx and Tx - DCD IntDefaultHandler ; UART1 Rx and Tx - DCD IntDefaultHandler ; SSI0 Rx and Tx - DCD IntDefaultHandler ; I2C0 Master and Slave - DCD IntDefaultHandler ; PWM Fault - DCD IntDefaultHandler ; PWM Generator 0 - DCD IntDefaultHandler ; PWM Generator 1 - DCD IntDefaultHandler ; PWM Generator 2 - DCD IntDefaultHandler ; Quadrature Encoder 0 - DCD IntDefaultHandler ; ADC Sequence 0 - DCD IntDefaultHandler ; ADC Sequence 1 - DCD IntDefaultHandler ; ADC Sequence 2 - DCD IntDefaultHandler ; ADC Sequence 3 - DCD IntDefaultHandler ; Watchdog timer - DCD IntDefaultHandler ; Timer 0 subtimer A - DCD IntDefaultHandler ; Timer 0 subtimer B - DCD IntDefaultHandler ; Timer 1 subtimer A - DCD IntDefaultHandler ; Timer 1 subtimer B - DCD IntDefaultHandler ; Timer 2 subtimer A - DCD IntDefaultHandler ; Timer 2 subtimer B - DCD IntDefaultHandler ; Analog Comparator 0 - DCD IntDefaultHandler ; Analog Comparator 1 - DCD IntDefaultHandler ; Analog Comparator 2 - DCD IntDefaultHandler ; System Control (PLL, OSC, BO) - DCD IntDefaultHandler ; FLASH Control - DCD IntDefaultHandler ; GPIO Port F - DCD IntDefaultHandler ; GPIO Port G - DCD IntDefaultHandler ; GPIO Port H - DCD IntDefaultHandler ; UART2 Rx and Tx - DCD IntDefaultHandler ; SSI1 Rx and Tx - DCD IntDefaultHandler ; Timer 3 subtimer A - DCD IntDefaultHandler ; Timer 3 subtimer B - DCD IntDefaultHandler ; I2C1 Master and Slave - DCD IntDefaultHandler ; CAN0 - DCD IntDefaultHandler ; CAN1 - DCD IntDefaultHandler ; Ethernet - DCD IntDefaultHandler ; Hibernate - DCD IntDefaultHandler ; USB0 - DCD IntDefaultHandler ; PWM Generator 3 - DCD IntDefaultHandler ; uDMA Software Transfer - DCD IntDefaultHandler ; uDMA Error - DCD IntDefaultHandler ; ADC1 Sequence 0 - DCD IntDefaultHandler ; ADC1 Sequence 1 - DCD IntDefaultHandler ; ADC1 Sequence 2 - DCD IntDefaultHandler ; ADC1 Sequence 3 - DCD IntDefaultHandler ; External Bus Interface 0 - DCD IntDefaultHandler ; GPIO Port J - DCD IntDefaultHandler ; GPIO Port K - DCD IntDefaultHandler ; GPIO Port L - DCD IntDefaultHandler ; SSI2 Rx and Tx - DCD IntDefaultHandler ; SSI3 Rx and Tx - DCD IntDefaultHandler ; UART3 Rx and Tx - DCD IntDefaultHandler ; UART4 Rx and Tx - DCD IntDefaultHandler ; UART5 Rx and Tx - DCD IntDefaultHandler ; UART6 Rx and Tx - DCD IntDefaultHandler ; UART7 Rx and Tx - DCD IntDefaultHandler ; I2C2 Master and Slave - DCD IntDefaultHandler ; I2C3 Master and Slave - DCD IntDefaultHandler ; Timer 4 subtimer A - DCD IntDefaultHandler ; Timer 4 subtimer B - DCD IntDefaultHandler ; Timer 5 subtimer A - DCD IntDefaultHandler ; Timer 5 subtimer B - DCD IntDefaultHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; I2C4 Master and Slave - DCD IntDefaultHandler ; I2C5 Master and Slave - DCD IntDefaultHandler ; GPIO Port M - DCD IntDefaultHandler ; GPIO Port N - DCD 0 ; Reserved - DCD IntDefaultHandler ; Tamper - DCD IntDefaultHandler ; GPIO Port P (Summary or P0) - DCD IntDefaultHandler ; GPIO Port P1 - DCD IntDefaultHandler ; GPIO Port P2 - DCD IntDefaultHandler ; GPIO Port P3 - DCD IntDefaultHandler ; GPIO Port P4 - DCD IntDefaultHandler ; GPIO Port P5 - DCD IntDefaultHandler ; GPIO Port P6 - DCD IntDefaultHandler ; GPIO Port P7 - DCD IntDefaultHandler ; GPIO Port Q (Summary or Q0) - DCD IntDefaultHandler ; GPIO Port Q1 - DCD IntDefaultHandler ; GPIO Port Q2 - DCD IntDefaultHandler ; GPIO Port Q3 - DCD IntDefaultHandler ; GPIO Port Q4 - DCD IntDefaultHandler ; GPIO Port Q5 - DCD IntDefaultHandler ; GPIO Port Q6 - DCD IntDefaultHandler ; GPIO Port Q7 - DCD IntDefaultHandler ; GPIO Port R - DCD IntDefaultHandler ; GPIO Port S - DCD IntDefaultHandler ; SHA/MD5 0 - DCD IntDefaultHandler ; AES 0 - DCD IntDefaultHandler ; DES3DES 0 - DCD IntDefaultHandler ; LCD Controller 0 - DCD IntDefaultHandler ; Timer 6 subtimer A - DCD IntDefaultHandler ; Timer 6 subtimer B - DCD IntDefaultHandler ; Timer 7 subtimer A - DCD IntDefaultHandler ; Timer 7 subtimer B - DCD IntDefaultHandler ; I2C6 Master and Slave - DCD IntDefaultHandler ; I2C7 Master and Slave - DCD IntDefaultHandler ; HIM Scan Matrix Keyboard 0 - DCD IntDefaultHandler ; One Wire 0 - DCD IntDefaultHandler ; HIM PS/2 0 - DCD IntDefaultHandler ; HIM LED Sequencer 0 - DCD IntDefaultHandler ; HIM Consumer IR 0 - DCD IntDefaultHandler ; I2C8 Master and Slave - DCD IntDefaultHandler ; I2C9 Master and Slave - DCD IntDefaultHandler ; GPIO Port T - -;****************************************************************************** -; -; This is the code that gets called when the processor first starts execution -; following a reset event. -; -;****************************************************************************** - EXPORT Reset_Handler -Reset_Handler - ; - ; Enable the floating-point unit. This must be done here to handle the - ; case where main() uses floating-point and the function prologue saves - ; floating-point registers (which will fault if floating-point is not - ; enabled). Any configuration of the floating-point unit using - ; DriverLib APIs must be done here prior to the floating-point unit - ; being enabled. - ; - ; Note that this does not use DriverLib since it might not be included - ; in this project. - ; - MOVW R0, #0xED88 - MOVT R0, #0xE000 - LDR R1, [R0] - ORR R1, #0x00F00000 - STR R1, [R0] - - ; - ; Call the C library enty point that handles startup. This will copy - ; the .data section initializers from flash to SRAM and zero fill the - ; .bss section. - ; - IMPORT __main - B __main - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a NMI. This -; simply enters an infinite loop, preserving the system state for examination -; by a debugger. -; -;****************************************************************************** -NmiSR - B NmiSR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a fault -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -FaultISR - B FaultISR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives an unexpected -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -IntDefaultHandler - B IntDefaultHandler - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Some code in the normal code section for initializing the heap and stack. -; -;****************************************************************************** - AREA |.text|, CODE, READONLY - -;****************************************************************************** -; -; The function expected of the C library startup code for defining the stack -; and heap memory locations. For the C library version of the startup code, -; provide this function so that the C library initialization code can find out -; the location of the stack and heap. -; -;****************************************************************************** - IF :DEF: __MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - LDR R0, =HeapMem - LDR R1, =(StackMem + Stack) - LDR R2, =(HeapMem + Heap) - LDR R3, =StackMem - BX LR - ENDIF - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Tell the assembler that we're done. -; -;****************************************************************************** - END diff --git a/bsp/tm4c129x-dk/project.uvproj b/bsp/tm4c129x-dk/project.uvproj deleted file mode 100644 index ce7d9b3c95..0000000000 --- a/bsp/tm4c129x-dk/project.uvproj +++ /dev/null @@ -1,1210 +0,0 @@ - - - 1.1 -
### uVision Project, (C) Keil Software
- - - RT-Thread TM4C129X - 0x4 - ARM-ADS - - - TM4C1294NCPDT - Texas Instruments - Keil.TM4C_DFP.1.0.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCPDT$Flash\TM4C129_1024.FLM)) - 7088 - $$Device:TM4C1294NCPDT$Device\Include\TM4C129\TM4C129.h - - - - - - - -DTM4C1294NCPDT - - - $$Device:TM4C1294NCPDT$SVD\TM4C129\TM4C1294NCPDT.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-tm4c - 1 - 0 - 0 - 1 - 1 - .\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 1 - 0x0 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - - - PART_TM4C129XNCZAD - - libraries;libraries/inc;libraries/driverlib;drivers;applications;.;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - tm4c_rom.sct - - - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - Libraries - - - adc.c - 1 - libraries/driverlib/adc.c - - - - - aes.c - 1 - libraries/driverlib/aes.c - - - - - can.c - 1 - libraries/driverlib/can.c - - - - - comp.c - 1 - libraries/driverlib/comp.c - - - - - cpu.c - 1 - libraries/driverlib/cpu.c - - - - - crc.c - 1 - libraries/driverlib/crc.c - - - - - des.c - 1 - libraries/driverlib/des.c - - - - - eeprom.c - 1 - libraries/driverlib/eeprom.c - - - - - emac.c - 1 - libraries/driverlib/emac.c - - - - - epi.c - 1 - libraries/driverlib/epi.c - - - - - flash.c - 1 - libraries/driverlib/flash.c - - - - - fpu.c - 1 - libraries/driverlib/fpu.c - - - - - gpio.c - 1 - libraries/driverlib/gpio.c - - - - - hibernate.c - 1 - libraries/driverlib/hibernate.c - - - - - i2c.c - 1 - libraries/driverlib/i2c.c - - - - - interrupt.c - 1 - libraries/driverlib/interrupt.c - - - - - lcd.c - 1 - libraries/driverlib/lcd.c - - - - - mpu.c - 1 - libraries/driverlib/mpu.c - - - - - pwm.c - 1 - libraries/driverlib/pwm.c - - - - - qei.c - 1 - libraries/driverlib/qei.c - - - - - shamd5.c - 1 - libraries/driverlib/shamd5.c - - - - - ssi.c - 1 - libraries/driverlib/ssi.c - - - - - sw_crc.c - 1 - libraries/driverlib/sw_crc.c - - - - - sysctl.c - 1 - libraries/driverlib/sysctl.c - - - - - sysexc.c - 1 - libraries/driverlib/sysexc.c - - - - - systick.c - 1 - libraries/driverlib/systick.c - - - - - tiva_timer.c - 1 - libraries/driverlib/tiva_timer.c - - - - - uart.c - 1 - libraries/driverlib/uart.c - - - - - udma.c - 1 - libraries/driverlib/udma.c - - - - - usb.c - 1 - libraries/driverlib/usb.c - - - - - watchdog.c - 1 - libraries/driverlib/watchdog.c - - - - - startup_rvmdk.S - 2 - libraries/startup/startup_rvmdk.S - - - - - Drivers - - - drv_eth.c - 1 - drivers/drv_eth.c - - - - - drv_uart.c - 1 - drivers/drv_uart.c - - - - - Applications - - - application.c - 1 - applications/application.c - - - - - board.c - 1 - applications/board.c - - - - - Kernel - - - clock.c - 1 - ../../src/clock.c - - - - - components.c - 1 - ../../src/components.c - - - - - device.c - 1 - ../../src/device.c - - - - - idle.c - 1 - ../../src/idle.c - - - - - ipc.c - 1 - ../../src/ipc.c - - - - - irq.c - 1 - ../../src/irq.c - - - - - kservice.c - 1 - ../../src/kservice.c - - - - - mem.c - 1 - ../../src/mem.c - - - - - memheap.c - 1 - ../../src/memheap.c - - - - - mempool.c - 1 - ../../src/mempool.c - - - - - object.c - 1 - ../../src/object.c - - - - - scheduler.c - 1 - ../../src/scheduler.c - - - - - signal.c - 1 - ../../src/signal.c - - - - - thread.c - 1 - ../../src/thread.c - - - - - timer.c - 1 - ../../src/timer.c - - - - - CORTEX-M4 - - - cpuport.c - 1 - ../../libcpu/arm/cortex-m4/cpuport.c - - - - - context_rvds.S - 2 - ../../libcpu/arm/cortex-m4/context_rvds.S - - - - - backtrace.c - 1 - ../../libcpu/arm/common/backtrace.c - - - - - div0.c - 1 - ../../libcpu/arm/common/div0.c - - - - - showmem.c - 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c - - - - - LwIP - - - api_lib.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - - - - - api_msg.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - - - - - err.c - 1 - ../../components/net/lwip-1.4.1/src/api/err.c - - - - - netbuf.c - 1 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - - - - - netdb.c - 1 - ../../components/net/lwip-1.4.1/src/api/netdb.c - - - - - netifapi.c - 1 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - - - - - sockets.c - 1 - ../../components/net/lwip-1.4.1/src/api/sockets.c - - - - - tcpip.c - 1 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - - - - - sys_arch.c - 1 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - - - - def.c - 1 - ../../components/net/lwip-1.4.1/src/core/def.c - - - - - dhcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - - - - - dns.c - 1 - ../../components/net/lwip-1.4.1/src/core/dns.c - - - - - init.c - 1 - ../../components/net/lwip-1.4.1/src/core/init.c - - - - - memp.c - 1 - ../../components/net/lwip-1.4.1/src/core/memp.c - - - - - netif.c - 1 - ../../components/net/lwip-1.4.1/src/core/netif.c - - - - - pbuf.c - 1 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - - - - - raw.c - 1 - ../../components/net/lwip-1.4.1/src/core/raw.c - - - - - stats.c - 1 - ../../components/net/lwip-1.4.1/src/core/stats.c - - - - - sys.c - 1 - ../../components/net/lwip-1.4.1/src/core/sys.c - - - - - tcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp.c - - - - - tcp_in.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - - - - - tcp_out.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - - - - - timers.c - 1 - ../../components/net/lwip-1.4.1/src/core/timers.c - - - - - udp.c - 1 - ../../components/net/lwip-1.4.1/src/core/udp.c - - - - - autoip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - - - - icmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - - - - igmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - - - - inet.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - - - - inet_chksum.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - - - - ip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - - - - - ip_addr.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - - - - - ip_frag.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - - - - - etharp.c - 1 - ../../components/net/lwip-1.4.1/src/netif/etharp.c - - - - - ethernetif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - - - - - slipif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/slipif.c - - - - - - - diff --git a/bsp/tm4c129x-dk/project.uvprojx b/bsp/tm4c129x-dk/project.uvprojx deleted file mode 100644 index 4e3387f6be..0000000000 --- a/bsp/tm4c129x-dk/project.uvprojx +++ /dev/null @@ -1,978 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - RT-Thread TM4C129X - 0x4 - ARM-ADS - 5060300::V5.06 update 3 (build 300)::ARMCC - - - TM4C129XNCZAD - Texas Instruments - Keil.TM4C_DFP.1.1.0 - http://www.keil.com/pack/ - IRAM(0x20000000,0x040000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C129XNCZAD$Flash\TM4C129_1024.FLM)) - 0 - $$Device:TM4C129XNCZAD$Device\Include\TM4C129\TM4C129.h - - - - - - - - - - $$Device:TM4C129XNCZAD$SVD\TM4C129\TM4C129XNCZAD.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-tm4c - 1 - 0 - 0 - 1 - 1 - .\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - 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- - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - tm4c_rom.sct - - - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - Libraries - - - adc.c - 1 - libraries/driverlib/adc.c - - - aes.c - 1 - libraries/driverlib/aes.c - - - can.c - 1 - libraries/driverlib/can.c - - - comp.c - 1 - libraries/driverlib/comp.c - - - cpu.c - 1 - libraries/driverlib/cpu.c - - - crc.c - 1 - libraries/driverlib/crc.c - - - des.c - 1 - libraries/driverlib/des.c - - - eeprom.c - 1 - libraries/driverlib/eeprom.c - - - emac.c - 1 - libraries/driverlib/emac.c - - - epi.c - 1 - libraries/driverlib/epi.c - - - flash.c - 1 - libraries/driverlib/flash.c - - - fpu.c - 1 - libraries/driverlib/fpu.c - - - gpio.c - 1 - libraries/driverlib/gpio.c - - - hibernate.c - 1 - libraries/driverlib/hibernate.c - - - i2c.c - 1 - libraries/driverlib/i2c.c - - - interrupt.c - 1 - libraries/driverlib/interrupt.c - - - lcd.c - 1 - libraries/driverlib/lcd.c - - - mpu.c - 1 - libraries/driverlib/mpu.c - - - pwm.c - 1 - libraries/driverlib/pwm.c - - - qei.c - 1 - libraries/driverlib/qei.c - - - shamd5.c - 1 - libraries/driverlib/shamd5.c - - - ssi.c - 1 - libraries/driverlib/ssi.c - - - sw_crc.c - 1 - libraries/driverlib/sw_crc.c - - - sysctl.c - 1 - libraries/driverlib/sysctl.c - - - sysexc.c - 1 - libraries/driverlib/sysexc.c - - - systick.c - 1 - libraries/driverlib/systick.c - - - tiva_timer.c - 1 - libraries/driverlib/tiva_timer.c - - - uart.c - 1 - libraries/driverlib/uart.c - - - udma.c - 1 - libraries/driverlib/udma.c - - - usb.c - 1 - libraries/driverlib/usb.c - - - watchdog.c - 1 - libraries/driverlib/watchdog.c - - - startup_rvmdk.S - 2 - libraries/startup/startup_rvmdk.S - - - - - Drivers - - - drv_eth.c - 1 - drivers/drv_eth.c - - - drv_uart.c - 1 - drivers/drv_uart.c - - - - - Applications - - - application.c - 1 - applications/application.c - - - board.c - 1 - applications/board.c - - - - - Kernel - - - clock.c - 1 - ../../src/clock.c - - - components.c - 1 - ../../src/components.c - - - device.c - 1 - ../../src/device.c - - - idle.c - 1 - ../../src/idle.c - - - ipc.c - 1 - ../../src/ipc.c - - - irq.c - 1 - ../../src/irq.c - - - kservice.c - 1 - ../../src/kservice.c - - - mem.c - 1 - ../../src/mem.c - - - memheap.c - 1 - ../../src/memheap.c - - - mempool.c - 1 - ../../src/mempool.c - - - object.c - 1 - ../../src/object.c - - - scheduler.c - 1 - ../../src/scheduler.c - - - signal.c - 1 - ../../src/signal.c - - - thread.c - 1 - ../../src/thread.c - - - timer.c - 1 - ../../src/timer.c - - - - - CORTEX-M4 - - - cpuport.c - 1 - ../../libcpu/arm/cortex-m4/cpuport.c - - - context_rvds.S - 2 - ../../libcpu/arm/cortex-m4/context_rvds.S - - - backtrace.c - 1 - ../../libcpu/arm/common/backtrace.c - - - div0.c - 1 - ../../libcpu/arm/common/div0.c - - - showmem.c - 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c - - - - - LwIP - - - api_lib.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - - - api_msg.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - - - err.c - 1 - ../../components/net/lwip-1.4.1/src/api/err.c - - - netbuf.c - 1 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - - - netdb.c - 1 - ../../components/net/lwip-1.4.1/src/api/netdb.c - - - netifapi.c - 1 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - - - sockets.c - 1 - ../../components/net/lwip-1.4.1/src/api/sockets.c - - - tcpip.c - 1 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - - - sys_arch.c - 1 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - - def.c - 1 - ../../components/net/lwip-1.4.1/src/core/def.c - - - dhcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - - - dns.c - 1 - ../../components/net/lwip-1.4.1/src/core/dns.c - - - init.c - 1 - ../../components/net/lwip-1.4.1/src/core/init.c - - - memp.c - 1 - ../../components/net/lwip-1.4.1/src/core/memp.c - - - netif.c - 1 - ../../components/net/lwip-1.4.1/src/core/netif.c - - - pbuf.c - 1 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - - - raw.c - 1 - ../../components/net/lwip-1.4.1/src/core/raw.c - - - stats.c - 1 - ../../components/net/lwip-1.4.1/src/core/stats.c - - - sys.c - 1 - ../../components/net/lwip-1.4.1/src/core/sys.c - - - tcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp.c - - - tcp_in.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - - - tcp_out.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - - - timers.c - 1 - ../../components/net/lwip-1.4.1/src/core/timers.c - - - udp.c - 1 - ../../components/net/lwip-1.4.1/src/core/udp.c - - - autoip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - - icmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - - igmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - - inet.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - - inet_chksum.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - - ip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - - - ip_addr.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - - - ip_frag.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - - - etharp.c - 1 - ../../components/net/lwip-1.4.1/src/netif/etharp.c - - - ethernetif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - - - slipif.c - 1 - ../../components/net/lwip-1.4.1/src/netif/slipif.c - - - - - - - - diff --git a/bsp/tm4c129x-dk/startup_rvmdk.lst b/bsp/tm4c129x-dk/startup_rvmdk.lst deleted file mode 100644 index 748d55a117..0000000000 --- a/bsp/tm4c129x-dk/startup_rvmdk.lst +++ /dev/null @@ -1,890 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ; <<< Use Configuration Wizard in Context Menu >>> - 2 00000000 ;******************************************************* - *********************** - 3 00000000 ; - 4 00000000 ; startup_rvmdk.S - Startup code for use with Keil's uVi - sion. - 5 00000000 ; - 6 00000000 ; Copyright (c) 2013-2017 Texas Instruments Incorporated - . All rights reserved. - 7 00000000 ; Software License Agreement - 8 00000000 ; - 9 00000000 ; Texas Instruments (TI) is supplying this software for - use solely and - 10 00000000 ; exclusively on TI's microcontroller products. The soft - ware is owned by - 11 00000000 ; TI and/or its suppliers, and is protected under applic - able copyright - 12 00000000 ; laws. You may not combine this software with "viral" o - pen-source - 13 00000000 ; software in order to form a larger program. - 14 00000000 ; - 15 00000000 ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. - - 16 00000000 ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - INCLUDING, BUT - 17 00000000 ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY - AND FITNESS FOR - 18 00000000 ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL - NOT, UNDER ANY - 19 00000000 ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR C - ONSEQUENTIAL - 20 00000000 ; DAMAGES, FOR ANY REASON WHATSOEVER. - 21 00000000 ; - 22 00000000 ; This is part of revision 2.1.4.178 of the DK-TM4C129X - Firmware Package. - 23 00000000 ; - 24 00000000 ;******************************************************* - *********************** - 25 00000000 - 26 00000000 ;******************************************************* - *********************** - 27 00000000 ; - 28 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - 29 00000000 ; - 30 00000000 ;******************************************************* - *********************** - 31 00000000 00000200 - Stack EQU 0x00000200 - 32 00000000 - 33 00000000 ;******************************************************* - *********************** - 34 00000000 ; - 35 00000000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - 36 00000000 ; - 37 00000000 ;******************************************************* - *********************** - 38 00000000 00000000 - Heap EQU 0x00000000 - 39 00000000 - - - -ARM Macro Assembler Page 2 - - - 40 00000000 ;******************************************************* - *********************** - 41 00000000 ; - 42 00000000 ; Allocate space for the stack. - 43 00000000 ; - 44 00000000 ;******************************************************* - *********************** - 45 00000000 AREA STACK, NOINIT, READWRITE, ALIGN -=3 - 46 00000000 StackMem - 47 00000000 SPACE Stack - 48 00000200 __initial_sp - 49 00000200 - 50 00000200 ;******************************************************* - *********************** - 51 00000200 ; - 52 00000200 ; Allocate space for the heap. - 53 00000200 ; - 54 00000200 ;******************************************************* - *********************** - 55 00000200 AREA HEAP, NOINIT, READWRITE, ALIGN= -3 - 56 00000000 __heap_base - 57 00000000 HeapMem - 58 00000000 SPACE Heap - 59 00000000 __heap_limit - 60 00000000 - 61 00000000 ;******************************************************* - *********************** - 62 00000000 ; - 63 00000000 ; Indicate that the code in this file preserves 8-byte a - lignment of the stack. - 64 00000000 ; - 65 00000000 ;******************************************************* - *********************** - 66 00000000 PRESERVE8 - 67 00000000 - 68 00000000 ;******************************************************* - *********************** - 69 00000000 ; - 70 00000000 ; Place code into the reset code section. - 71 00000000 ; - 72 00000000 ;******************************************************* - *********************** - 73 00000000 AREA RESET, CODE, READONLY - 74 00000000 THUMB - 75 00000000 - 76 00000000 ;******************************************************* - *********************** - 77 00000000 ; - 78 00000000 ; The vector table. - 79 00000000 ; - 80 00000000 ;******************************************************* - *********************** - 81 00000000 EXPORT __Vectors - 82 00000000 __Vectors - 83 00000000 00000200 DCD StackMem + Stack ; Top of Stack - - 84 00000004 00000000 DCD Reset_Handler ; Reset Handler - - - -ARM Macro Assembler Page 3 - - - 85 00000008 00000000 DCD NmiSR ; NMI Handler - 86 0000000C 00000000 DCD FaultISR ; Hard Fault Handle - r - 87 00000010 00000000 DCD IntDefaultHandler ; The MPU fau - lt handler - 88 00000014 00000000 DCD IntDefaultHandler ; The bus fau - lt handler - 89 00000018 00000000 DCD IntDefaultHandler ; The usage f - ault handler - 90 0000001C 00000000 DCD 0 ; Reserved - 91 00000020 00000000 DCD 0 ; Reserved - 92 00000024 00000000 DCD 0 ; Reserved - 93 00000028 00000000 DCD 0 ; Reserved - 94 0000002C 00000000 DCD IntDefaultHandler - ; SVCall handler - 95 00000030 00000000 DCD IntDefaultHandler ; Debug monit - or handler - 96 00000034 00000000 DCD 0 ; Reserved - 97 00000038 00000000 DCD IntDefaultHandler ; The PendSV - handler - 98 0000003C 00000000 DCD IntDefaultHandler ; The SysTick - handler - 99 00000040 00000000 DCD IntDefaultHandler ; GPIO Port A - - 100 00000044 00000000 DCD IntDefaultHandler ; GPIO Port B - - 101 00000048 00000000 DCD IntDefaultHandler ; GPIO Port C - - 102 0000004C 00000000 DCD IntDefaultHandler ; GPIO Port D - - 103 00000050 00000000 DCD IntDefaultHandler ; GPIO Port E - - 104 00000054 00000000 DCD IntDefaultHandler - ; UART0 Rx and Tx - 105 00000058 00000000 DCD IntDefaultHandler - ; UART1 Rx and Tx - 106 0000005C 00000000 DCD IntDefaultHandler - ; SSI0 Rx and Tx - 107 00000060 00000000 DCD IntDefaultHandler ; I2C0 Master - and Slave - 108 00000064 00000000 DCD IntDefaultHandler ; PWM Fault - 109 00000068 00000000 DCD IntDefaultHandler - ; PWM Generator 0 - 110 0000006C 00000000 DCD IntDefaultHandler - ; PWM Generator 1 - 111 00000070 00000000 DCD IntDefaultHandler - ; PWM Generator 2 - 112 00000074 00000000 DCD IntDefaultHandler ; Quadrature - Encoder 0 - 113 00000078 00000000 DCD IntDefaultHandler - ; ADC Sequence 0 - 114 0000007C 00000000 DCD IntDefaultHandler - ; ADC Sequence 1 - 115 00000080 00000000 DCD IntDefaultHandler - ; ADC Sequence 2 - 116 00000084 00000000 DCD IntDefaultHandler - ; ADC Sequence 3 - 117 00000088 00000000 DCD IntDefaultHandler - ; Watchdog timer - - - -ARM Macro Assembler Page 4 - - - 118 0000008C 00000000 DCD IntDefaultHandler ; Timer 0 sub - timer A - 119 00000090 00000000 DCD IntDefaultHandler ; Timer 0 sub - timer B - 120 00000094 00000000 DCD IntDefaultHandler ; Timer 1 sub - timer A - 121 00000098 00000000 DCD IntDefaultHandler ; Timer 1 sub - timer B - 122 0000009C 00000000 DCD IntDefaultHandler ; Timer 2 sub - timer A - 123 000000A0 00000000 DCD IntDefaultHandler ; Timer 2 sub - timer B - 124 000000A4 00000000 DCD IntDefaultHandler ; Analog Comp - arator 0 - 125 000000A8 00000000 DCD IntDefaultHandler ; Analog Comp - arator 1 - 126 000000AC 00000000 DCD IntDefaultHandler ; Analog Comp - arator 2 - 127 000000B0 00000000 DCD IntDefaultHandler ; System Cont - rol (PLL, OSC, BO) - 128 000000B4 00000000 DCD IntDefaultHandler - ; FLASH Control - 129 000000B8 00000000 DCD IntDefaultHandler ; GPIO Port F - - 130 000000BC 00000000 DCD IntDefaultHandler ; GPIO Port G - - 131 000000C0 00000000 DCD IntDefaultHandler ; GPIO Port H - - 132 000000C4 00000000 DCD IntDefaultHandler - ; UART2 Rx and Tx - 133 000000C8 00000000 DCD IntDefaultHandler - ; SSI1 Rx and Tx - 134 000000CC 00000000 DCD IntDefaultHandler ; Timer 3 sub - timer A - 135 000000D0 00000000 DCD IntDefaultHandler ; Timer 3 sub - timer B - 136 000000D4 00000000 DCD IntDefaultHandler ; I2C1 Master - and Slave - 137 000000D8 00000000 DCD IntDefaultHandler ; CAN0 - 138 000000DC 00000000 DCD IntDefaultHandler ; CAN1 - 139 000000E0 00000000 DCD IntDefaultHandler ; Ethernet - 140 000000E4 00000000 DCD IntDefaultHandler ; Hibernate - 141 000000E8 00000000 DCD IntDefaultHandler ; USB0 - 142 000000EC 00000000 DCD IntDefaultHandler - ; PWM Generator 3 - 143 000000F0 00000000 DCD IntDefaultHandler ; uDMA Softwa - re Transfer - 144 000000F4 00000000 DCD IntDefaultHandler ; uDMA Error - 145 000000F8 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 0 - 146 000000FC 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 1 - 147 00000100 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 2 - 148 00000104 00000000 DCD IntDefaultHandler - ; ADC1 Sequence 3 - 149 00000108 00000000 DCD IntDefaultHandler ; External Bu - s Interface 0 - 150 0000010C 00000000 DCD IntDefaultHandler ; GPIO Port J - - - -ARM Macro Assembler Page 5 - - - - 151 00000110 00000000 DCD IntDefaultHandler ; GPIO Port K - - 152 00000114 00000000 DCD IntDefaultHandler ; GPIO Port L - - 153 00000118 00000000 DCD IntDefaultHandler - ; SSI2 Rx and Tx - 154 0000011C 00000000 DCD IntDefaultHandler - ; SSI3 Rx and Tx - 155 00000120 00000000 DCD IntDefaultHandler - ; UART3 Rx and Tx - 156 00000124 00000000 DCD IntDefaultHandler - ; UART4 Rx and Tx - 157 00000128 00000000 DCD IntDefaultHandler - ; UART5 Rx and Tx - 158 0000012C 00000000 DCD IntDefaultHandler - ; UART6 Rx and Tx - 159 00000130 00000000 DCD IntDefaultHandler - ; UART7 Rx and Tx - 160 00000134 00000000 DCD IntDefaultHandler ; I2C2 Master - and Slave - 161 00000138 00000000 DCD IntDefaultHandler ; I2C3 Master - and Slave - 162 0000013C 00000000 DCD IntDefaultHandler ; Timer 4 sub - timer A - 163 00000140 00000000 DCD IntDefaultHandler ; Timer 4 sub - timer B - 164 00000144 00000000 DCD IntDefaultHandler ; Timer 5 sub - timer A - 165 00000148 00000000 DCD IntDefaultHandler ; Timer 5 sub - timer B - 166 0000014C 00000000 DCD IntDefaultHandler ; FPU - 167 00000150 00000000 DCD 0 ; Reserved - 168 00000154 00000000 DCD 0 ; Reserved - 169 00000158 00000000 DCD IntDefaultHandler ; I2C4 Master - and Slave - 170 0000015C 00000000 DCD IntDefaultHandler ; I2C5 Master - and Slave - 171 00000160 00000000 DCD IntDefaultHandler ; GPIO Port M - - 172 00000164 00000000 DCD IntDefaultHandler ; GPIO Port N - - 173 00000168 00000000 DCD 0 ; Reserved - 174 0000016C 00000000 DCD IntDefaultHandler ; Tamper - 175 00000170 00000000 DCD IntDefaultHandler ; GPIO Port P - (Summary or P0) - 176 00000174 00000000 DCD IntDefaultHandler - ; GPIO Port P1 - 177 00000178 00000000 DCD IntDefaultHandler - ; GPIO Port P2 - 178 0000017C 00000000 DCD IntDefaultHandler - ; GPIO Port P3 - 179 00000180 00000000 DCD IntDefaultHandler - ; GPIO Port P4 - 180 00000184 00000000 DCD IntDefaultHandler - ; GPIO Port P5 - 181 00000188 00000000 DCD IntDefaultHandler - ; GPIO Port P6 - 182 0000018C 00000000 DCD IntDefaultHandler - - - -ARM Macro Assembler Page 6 - - - ; GPIO Port P7 - 183 00000190 00000000 DCD IntDefaultHandler ; GPIO Port Q - (Summary or Q0) - 184 00000194 00000000 DCD IntDefaultHandler - ; GPIO Port Q1 - 185 00000198 00000000 DCD IntDefaultHandler - ; GPIO Port Q2 - 186 0000019C 00000000 DCD IntDefaultHandler - ; GPIO Port Q3 - 187 000001A0 00000000 DCD IntDefaultHandler - ; GPIO Port Q4 - 188 000001A4 00000000 DCD IntDefaultHandler - ; GPIO Port Q5 - 189 000001A8 00000000 DCD IntDefaultHandler - ; GPIO Port Q6 - 190 000001AC 00000000 DCD IntDefaultHandler - ; GPIO Port Q7 - 191 000001B0 00000000 DCD IntDefaultHandler ; GPIO Port R - - 192 000001B4 00000000 DCD IntDefaultHandler ; GPIO Port S - - 193 000001B8 00000000 DCD IntDefaultHandler ; SHA/MD5 0 - 194 000001BC 00000000 DCD IntDefaultHandler ; AES 0 - 195 000001C0 00000000 DCD IntDefaultHandler ; DES3DES 0 - 196 000001C4 00000000 DCD IntDefaultHandler - ; LCD Controller 0 - 197 000001C8 00000000 DCD IntDefaultHandler ; Timer 6 sub - timer A - 198 000001CC 00000000 DCD IntDefaultHandler ; Timer 6 sub - timer B - 199 000001D0 00000000 DCD IntDefaultHandler ; Timer 7 sub - timer A - 200 000001D4 00000000 DCD IntDefaultHandler ; Timer 7 sub - timer B - 201 000001D8 00000000 DCD IntDefaultHandler ; I2C6 Master - and Slave - 202 000001DC 00000000 DCD IntDefaultHandler ; I2C7 Master - and Slave - 203 000001E0 00000000 DCD IntDefaultHandler ; HIM Scan Ma - trix Keyboard 0 - 204 000001E4 00000000 DCD IntDefaultHandler ; One Wire 0 - 205 000001E8 00000000 DCD IntDefaultHandler ; HIM PS/2 0 - 206 000001EC 00000000 DCD IntDefaultHandler ; HIM LED Seq - uencer 0 - 207 000001F0 00000000 DCD IntDefaultHandler - ; HIM Consumer IR 0 - - 208 000001F4 00000000 DCD IntDefaultHandler ; I2C8 Master - and Slave - 209 000001F8 00000000 DCD IntDefaultHandler ; I2C9 Master - and Slave - 210 000001FC 00000000 DCD IntDefaultHandler ; GPIO Port T - - 211 00000200 - 212 00000200 ;******************************************************* - *********************** - 213 00000200 ; - 214 00000200 ; This is the code that gets called when the processor f - irst starts execution - - - -ARM Macro Assembler Page 7 - - - 215 00000200 ; following a reset event. - 216 00000200 ; - 217 00000200 ;******************************************************* - *********************** - 218 00000200 EXPORT Reset_Handler - 219 00000200 Reset_Handler - 220 00000200 ; - 221 00000200 ; Enable the floating-point unit. This must be done her - e to handle the - 222 00000200 ; case where main() uses floating-point and the function - prologue saves - 223 00000200 ; floating-point registers (which will fault if floating - -point is not - 224 00000200 ; enabled). Any configuration of the floating-point uni - t using - 225 00000200 ; DriverLib APIs must be done here prior to the floating - -point unit - 226 00000200 ; being enabled. - 227 00000200 ; - 228 00000200 ; Note that this does not use DriverLib since it might n - ot be included - 229 00000200 ; in this project. - 230 00000200 ; - 231 00000200 F64E 5088 MOVW R0, #0xED88 - 232 00000204 F2CE 0000 MOVT R0, #0xE000 - 233 00000208 6801 LDR R1, [R0] - 234 0000020A F441 0170 ORR R1, #0x00F00000 - 235 0000020E 6001 STR R1, [R0] - 236 00000210 - 237 00000210 ; - 238 00000210 ; Call the C library enty point that handles startup. T - his will copy - 239 00000210 ; the .data section initializers from flash to SRAM and - zero fill the - 240 00000210 ; .bss section. - 241 00000210 ; - 242 00000210 IMPORT __main - 243 00000210 F7FF BFFE B __main - 244 00000214 - 245 00000214 ;******************************************************* - *********************** - 246 00000214 ; - 247 00000214 ; This is the code that gets called when the processor r - eceives a NMI. This - 248 00000214 ; simply enters an infinite loop, preserving the system - state for examination - 249 00000214 ; by a debugger. - 250 00000214 ; - 251 00000214 ;******************************************************* - *********************** - 252 00000214 NmiSR - 253 00000214 E7FE B NmiSR - 254 00000216 - 255 00000216 ;******************************************************* - *********************** - 256 00000216 ; - 257 00000216 ; This is the code that gets called when the processor r - eceives a fault - 258 00000216 ; interrupt. This simply enters an infinite loop, prese - - - -ARM Macro Assembler Page 8 - - - rving the system state - 259 00000216 ; for examination by a debugger. - 260 00000216 ; - 261 00000216 ;******************************************************* - *********************** - 262 00000216 FaultISR - 263 00000216 E7FE B FaultISR - 264 00000218 - 265 00000218 ;******************************************************* - *********************** - 266 00000218 ; - 267 00000218 ; This is the code that gets called when the processor r - eceives an unexpected - 268 00000218 ; interrupt. This simply enters an infinite loop, prese - rving the system state - 269 00000218 ; for examination by a debugger. - 270 00000218 ; - 271 00000218 ;******************************************************* - *********************** - 272 00000218 IntDefaultHandler - 273 00000218 E7FE B IntDefaultHandler - 274 0000021A - 275 0000021A ;******************************************************* - *********************** - 276 0000021A ; - 277 0000021A ; Make sure the end of this section is aligned. - 278 0000021A ; - 279 0000021A ;******************************************************* - *********************** - 280 0000021A 00 00 ALIGN - 281 0000021C - 282 0000021C ;******************************************************* - *********************** - 283 0000021C ; - 284 0000021C ; Some code in the normal code section for initializing - the heap and stack. - 285 0000021C ; - 286 0000021C ;******************************************************* - *********************** - 287 0000021C AREA |.text|, CODE, READONLY - 288 00000000 - 289 00000000 ;******************************************************* - *********************** - 290 00000000 ; - 291 00000000 ; The function expected of the C library startup code fo - r defining the stack - 292 00000000 ; and heap memory locations. For the C library version - of the startup code, - 293 00000000 ; provide this function so that the C library initializa - tion code can find out - 294 00000000 ; the location of the stack and heap. - 295 00000000 ; - 296 00000000 ;******************************************************* - *********************** - 297 00000000 IF :DEF: __MICROLIB - 302 00000000 IMPORT __use_two_region_memory - 303 00000000 EXPORT __user_initial_stackheap - 304 00000000 __user_initial_stackheap - 305 00000000 4802 LDR R0, =HeapMem - - - -ARM Macro Assembler Page 9 - - - 306 00000002 4903 LDR R1, =(StackMem + Stack) - 307 00000004 4A01 LDR R2, =(HeapMem + Heap) - 308 00000006 4B03 LDR R3, =StackMem - 309 00000008 4770 BX LR - 310 0000000A ENDIF - 311 0000000A - 312 0000000A ;******************************************************* - *********************** - 313 0000000A ; - 314 0000000A ; Make sure the end of this section is aligned. - 315 0000000A ; - 316 0000000A ;******************************************************* - *********************** - 317 0000000A 00 00 ALIGN - 318 0000000C - 319 0000000C ;******************************************************* - *********************** - 320 0000000C ; - 321 0000000C ; Tell the assembler that we're done. - 322 0000000C ; - 323 0000000C ;******************************************************* - *********************** - 324 0000000C END - 00000000 - 00000200 - 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int -erwork --depend=.\build\startup_rvmdk.d -o.\build\startup_rvmdk.o -IC:\Users\zy -lww\Documents\Study\CodeHub\rt-thread\bsp\tm4c129x-dk\RTE -IC:\Software\Keil\AR -M\PACK\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C129 -IC:\Software\Keil\ARM\CMSIS\ -Include --predefine="__UVISION_VERSION SETA 521" --predefine="TM4C129XNCZAD SET -A 1" --list=.\startup_rvmdk.lst libraries/startup/startup_rvmdk.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -STACK 00000000 - -Symbol: STACK - Definitions - At line 45 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: STACK unused -StackMem 00000000 - -Symbol: StackMem - Definitions - At line 46 in file libraries/startup/startup_rvmdk.S - Uses - At line 83 in file libraries/startup/startup_rvmdk.S - At line 306 in file libraries/startup/startup_rvmdk.S - At line 308 in file libraries/startup/startup_rvmdk.S - -__initial_sp 00000200 - -Symbol: __initial_sp - Definitions - At line 48 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __initial_sp unused -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -HEAP 00000000 - -Symbol: HEAP - Definitions - At line 55 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: HEAP unused -HeapMem 00000000 - -Symbol: HeapMem - Definitions - At line 57 in file libraries/startup/startup_rvmdk.S - Uses - At line 305 in file libraries/startup/startup_rvmdk.S - At line 307 in file libraries/startup/startup_rvmdk.S - -__heap_base 00000000 - -Symbol: __heap_base - Definitions - At line 56 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __heap_base unused -__heap_limit 00000000 - -Symbol: __heap_limit - Definitions - At line 59 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __heap_limit unused -4 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -FaultISR 00000216 - -Symbol: FaultISR - Definitions - At line 262 in file libraries/startup/startup_rvmdk.S - Uses - At line 86 in file libraries/startup/startup_rvmdk.S - At line 263 in file libraries/startup/startup_rvmdk.S - -IntDefaultHandler 00000218 - -Symbol: IntDefaultHandler - Definitions - At line 272 in file libraries/startup/startup_rvmdk.S - Uses - At line 87 in file libraries/startup/startup_rvmdk.S - At line 88 in file libraries/startup/startup_rvmdk.S - At line 89 in file libraries/startup/startup_rvmdk.S - At line 94 in file libraries/startup/startup_rvmdk.S - At line 95 in file libraries/startup/startup_rvmdk.S - At line 97 in file libraries/startup/startup_rvmdk.S - At line 98 in file libraries/startup/startup_rvmdk.S - At line 99 in file libraries/startup/startup_rvmdk.S - At line 100 in file libraries/startup/startup_rvmdk.S - At line 101 in file libraries/startup/startup_rvmdk.S - At line 102 in file libraries/startup/startup_rvmdk.S - At line 103 in file libraries/startup/startup_rvmdk.S - At line 104 in file libraries/startup/startup_rvmdk.S - At line 105 in file libraries/startup/startup_rvmdk.S - At line 106 in file libraries/startup/startup_rvmdk.S - At line 107 in file libraries/startup/startup_rvmdk.S - At line 108 in file libraries/startup/startup_rvmdk.S - At line 109 in file libraries/startup/startup_rvmdk.S - At line 110 in file libraries/startup/startup_rvmdk.S - At line 111 in file libraries/startup/startup_rvmdk.S - At line 112 in file libraries/startup/startup_rvmdk.S - At line 113 in file libraries/startup/startup_rvmdk.S - At line 114 in file libraries/startup/startup_rvmdk.S - At line 115 in file libraries/startup/startup_rvmdk.S - At line 116 in file libraries/startup/startup_rvmdk.S - At line 117 in file libraries/startup/startup_rvmdk.S - At line 118 in file libraries/startup/startup_rvmdk.S - At line 119 in file libraries/startup/startup_rvmdk.S - At line 120 in file libraries/startup/startup_rvmdk.S - At line 121 in file libraries/startup/startup_rvmdk.S - At line 122 in file libraries/startup/startup_rvmdk.S - At line 123 in file libraries/startup/startup_rvmdk.S - At line 124 in file libraries/startup/startup_rvmdk.S - At line 125 in file libraries/startup/startup_rvmdk.S - At line 126 in file libraries/startup/startup_rvmdk.S - At line 127 in file libraries/startup/startup_rvmdk.S - At line 128 in file libraries/startup/startup_rvmdk.S - At line 129 in file libraries/startup/startup_rvmdk.S - At line 130 in file libraries/startup/startup_rvmdk.S - At line 131 in file libraries/startup/startup_rvmdk.S - At line 132 in file libraries/startup/startup_rvmdk.S - At line 133 in file libraries/startup/startup_rvmdk.S - At line 134 in file libraries/startup/startup_rvmdk.S - At line 135 in file libraries/startup/startup_rvmdk.S - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - At line 136 in file libraries/startup/startup_rvmdk.S - At line 137 in file libraries/startup/startup_rvmdk.S - At line 138 in file libraries/startup/startup_rvmdk.S - At line 139 in file libraries/startup/startup_rvmdk.S - At line 140 in file libraries/startup/startup_rvmdk.S - At line 141 in file libraries/startup/startup_rvmdk.S - At line 142 in file libraries/startup/startup_rvmdk.S - At line 143 in file libraries/startup/startup_rvmdk.S - At line 144 in file libraries/startup/startup_rvmdk.S - At line 145 in file libraries/startup/startup_rvmdk.S - At line 146 in file libraries/startup/startup_rvmdk.S - At line 147 in file libraries/startup/startup_rvmdk.S - At line 148 in file libraries/startup/startup_rvmdk.S - At line 149 in file libraries/startup/startup_rvmdk.S - At line 150 in file libraries/startup/startup_rvmdk.S - At line 151 in file libraries/startup/startup_rvmdk.S - At line 152 in file libraries/startup/startup_rvmdk.S - At line 153 in file libraries/startup/startup_rvmdk.S - At line 154 in file libraries/startup/startup_rvmdk.S - At line 155 in file libraries/startup/startup_rvmdk.S - At line 156 in file libraries/startup/startup_rvmdk.S - At line 157 in file libraries/startup/startup_rvmdk.S - At line 158 in file libraries/startup/startup_rvmdk.S - At line 159 in file libraries/startup/startup_rvmdk.S - At line 160 in file libraries/startup/startup_rvmdk.S - At line 161 in file libraries/startup/startup_rvmdk.S - At line 162 in file libraries/startup/startup_rvmdk.S - At line 163 in file libraries/startup/startup_rvmdk.S - At line 164 in file libraries/startup/startup_rvmdk.S - At line 165 in file libraries/startup/startup_rvmdk.S - At line 166 in file libraries/startup/startup_rvmdk.S - At line 169 in file libraries/startup/startup_rvmdk.S - At line 170 in file libraries/startup/startup_rvmdk.S - At line 171 in file libraries/startup/startup_rvmdk.S - At line 172 in file libraries/startup/startup_rvmdk.S - At line 174 in file libraries/startup/startup_rvmdk.S - At line 175 in file libraries/startup/startup_rvmdk.S - At line 176 in file libraries/startup/startup_rvmdk.S - At line 177 in file libraries/startup/startup_rvmdk.S - At line 178 in file libraries/startup/startup_rvmdk.S - At line 179 in file libraries/startup/startup_rvmdk.S - At line 180 in file libraries/startup/startup_rvmdk.S - At line 181 in file libraries/startup/startup_rvmdk.S - At line 182 in file libraries/startup/startup_rvmdk.S - At line 183 in file libraries/startup/startup_rvmdk.S - At line 184 in file libraries/startup/startup_rvmdk.S - At line 185 in file libraries/startup/startup_rvmdk.S - At line 186 in file libraries/startup/startup_rvmdk.S - At line 187 in file libraries/startup/startup_rvmdk.S - At line 188 in file libraries/startup/startup_rvmdk.S - At line 189 in file libraries/startup/startup_rvmdk.S - At line 190 in file libraries/startup/startup_rvmdk.S - At line 191 in file libraries/startup/startup_rvmdk.S - At line 192 in file libraries/startup/startup_rvmdk.S - At line 193 in file libraries/startup/startup_rvmdk.S - At line 194 in file libraries/startup/startup_rvmdk.S - At line 195 in file libraries/startup/startup_rvmdk.S - At line 196 in file libraries/startup/startup_rvmdk.S - At line 197 in file libraries/startup/startup_rvmdk.S - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - - At line 198 in file libraries/startup/startup_rvmdk.S - At line 199 in file libraries/startup/startup_rvmdk.S - At line 200 in file libraries/startup/startup_rvmdk.S - At line 201 in file libraries/startup/startup_rvmdk.S - At line 202 in file libraries/startup/startup_rvmdk.S - At line 203 in file libraries/startup/startup_rvmdk.S - At line 204 in file libraries/startup/startup_rvmdk.S - At line 205 in file libraries/startup/startup_rvmdk.S - At line 206 in file libraries/startup/startup_rvmdk.S - At line 207 in file libraries/startup/startup_rvmdk.S - At line 208 in file libraries/startup/startup_rvmdk.S - At line 209 in file libraries/startup/startup_rvmdk.S - At line 210 in file libraries/startup/startup_rvmdk.S - At line 273 in file libraries/startup/startup_rvmdk.S - -NmiSR 00000214 - -Symbol: NmiSR - Definitions - At line 252 in file libraries/startup/startup_rvmdk.S - Uses - At line 85 in file libraries/startup/startup_rvmdk.S - At line 253 in file libraries/startup/startup_rvmdk.S - -RESET 00000000 - -Symbol: RESET - Definitions - At line 73 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: RESET unused -Reset_Handler 00000200 - -Symbol: Reset_Handler - Definitions - At line 219 in file libraries/startup/startup_rvmdk.S - Uses - At line 84 in file libraries/startup/startup_rvmdk.S - At line 218 in file libraries/startup/startup_rvmdk.S - -__Vectors 00000000 - -Symbol: __Vectors - Definitions - At line 82 in file libraries/startup/startup_rvmdk.S - Uses - At line 81 in file libraries/startup/startup_rvmdk.S -Comment: __Vectors used once -6 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 287 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: .text unused -__user_initial_stackheap 00000000 - -Symbol: __user_initial_stackheap - Definitions - At line 304 in file libraries/startup/startup_rvmdk.S - Uses - At line 303 in file libraries/startup/startup_rvmdk.S -Comment: __user_initial_stackheap used once -2 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -Heap 00000000 - -Symbol: Heap - Definitions - At line 38 in file libraries/startup/startup_rvmdk.S - Uses - At line 58 in file libraries/startup/startup_rvmdk.S - At line 307 in file libraries/startup/startup_rvmdk.S - -Stack 00000200 - -Symbol: Stack - Definitions - At line 31 in file libraries/startup/startup_rvmdk.S - Uses - At line 47 in file libraries/startup/startup_rvmdk.S - At line 83 in file libraries/startup/startup_rvmdk.S - At line 306 in file libraries/startup/startup_rvmdk.S - -2 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -__main 00000000 - -Symbol: __main - Definitions - At line 242 in file libraries/startup/startup_rvmdk.S - Uses - At line 243 in file libraries/startup/startup_rvmdk.S -Comment: __main used once -__use_two_region_memory 00000000 - -Symbol: __use_two_region_memory - Definitions - At line 302 in file libraries/startup/startup_rvmdk.S - Uses - None -Comment: __use_two_region_memory unused -2 symbols -356 symbols in table diff --git a/bsp/tm4c129x-dk/tm4c_rom.icf b/bsp/tm4c129x-dk/tm4c_rom.icf deleted file mode 100644 index 4bda7a154a..0000000000 --- a/bsp/tm4c129x-dk/tm4c_rom.icf +++ /dev/null @@ -1,87 +0,0 @@ -//***************************************************************************** -// -// tm4c_room.icf - Linker configuration file for RT-Thread BSP. -// -// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement -// -// Texas Instruments (TI) is supplying this software for use solely and -// exclusively on TI's microcontroller products. The software is owned by -// TI and/or its suppliers, and is protected under applicable copyright -// laws. You may not combine this software with "viral" open-source -// software in order to form a larger program. -// -// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -// DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -// -//***************************************************************************** - -// -// Define a memory region that covers the entire 4 GB addressible space of the -// processor. -// -define memory mem with size = 4G; - -// -// Define a region for the on-chip flash. -// -define region FLASH = mem:[from 0x00000000 to 0x000fffff]; - -// -// Define a region for the on-chip SRAM. -// -define region SRAM = mem:[from 0x20000000 to 0x2003ffff]; - -// -// Define a block for the heap. The size should be set to something other -// than zero if things in the C library that require the heap are used. -// -define block HEAP with alignment = 8, size = 0x00000000 { }; - -// -// Define a block for RT-Thread components initialization -// -define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* }; - -// -// Indicate that the read/write values should be initialized by copying from -// flash. -// -initialize by copy { readwrite }; - -// -// Indicate that the noinit values should be left alone. This includes the -// stack, which if initialized will destroy the return address from the -// initialization code, causing the processor to branch to zero and fault. -// -do not initialize { section .noinit }; - -// -// Place the interrupt vectors at the start of flash. -// -place at start of FLASH { readonly section .intvec }; - -// -// Place the remainder of the read-only items into flash. -// -place in FLASH { readonly, block RTT_INIT_FUNC }; - -// -// Place the RAM vector table at the start of SRAM. -// -place at start of SRAM { section VTABLE }; - -// -// Place all read/write items into SRAM. -// -place in SRAM { readwrite, block HEAP }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; \ No newline at end of file diff --git a/bsp/tm4c129x-dk/tm4c_rom.sct b/bsp/tm4c129x-dk/tm4c_rom.sct deleted file mode 100644 index 9162ff8c44..0000000000 --- a/bsp/tm4c129x-dk/tm4c_rom.sct +++ /dev/null @@ -1,47 +0,0 @@ -;****************************************************************************** -; -; blinky.sct - Linker configuration file for blinky. -; -; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. -; Software License Agreement -; -; Texas Instruments (TI) is supplying this software for use solely and -; exclusively on TI's microcontroller products. The software is owned by -; TI and/or its suppliers, and is protected under applicable copyright -; laws. You may not combine this software with "viral" open-source -; software in order to form a larger program. -; -; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. -; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT -; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY -; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL -; DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. -; -;****************************************************************************** - -LR_IROM 0x00000000 0x00100000 -{ - ; - ; Specify the Execution Address of the code and the size. - ; - ER_IROM 0x00000000 0x00100000 - { - *.o (RESET, +First) - * (InRoot$$Sections, +RO) - } - - ; - ; Specify the Execution Address of the data area. - ; - RW_IRAM 0x20000000 0x00040000 - { - ; - ; Uncomment the following line in order to use IntRegister(). - ; - ;* (vtable, +First) - * (+RW, +ZI) - } -} diff --git a/bsp/tms320f28379d/.ccsproject b/bsp/tms320f28379d/.ccsproject new file mode 100644 index 0000000000..e3dbeec008 --- /dev/null +++ b/bsp/tms320f28379d/.ccsproject @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/.config b/bsp/tms320f28379d/.config new file mode 100644 index 0000000000..ddc9fd302e --- /dev/null +++ b/bsp/tms320f28379d/.config @@ -0,0 +1,303 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_TMS320F28X=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +CONFIG_RT_THREAD_PRIORITY_8=y +# CONFIG_RT_THREAD_PRIORITY_32 is not set +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=8 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_ARCH_TIDSP=y +CONFIG_ARCH_TIDSP_C28X=y +CONFIG_ARCH_CPU_STACK_GROWS_UPWARD=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +# CONFIG_RT_USING_USER_MAIN is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +# CONFIG_RT_USING_FINSH is not set + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set diff --git a/bsp/tms320f28379d/.cproject b/bsp/tms320f28379d/.cproject new file mode 100644 index 0000000000..d2f74c22d6 --- /dev/null +++ b/bsp/tms320f28379d/.cproject @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/.project b/bsp/tms320f28379d/.project new file mode 100644 index 0000000000..bab120e2b9 --- /dev/null +++ b/bsp/tms320f28379d/.project @@ -0,0 +1,39 @@ + + + rt-thread + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Kernel + 2 + PARENT-2-PROJECT_LOC/src + + + c28x + 2 + PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c28x + + + diff --git a/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs b/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000000..f653028c53 --- /dev/null +++ b/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs b/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000000..2adc7b1dde --- /dev/null +++ b/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs b/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000000..288ca292c6 --- /dev/null +++ b/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,20 @@ +eclipse.preferences.version=1 +encoding//Debug/Kernel/subdir_rules.mk=UTF-8 +encoding//Debug/Kernel/subdir_vars.mk=UTF-8 +encoding//Debug/applications/subdir_rules.mk=UTF-8 +encoding//Debug/applications/subdir_vars.mk=UTF-8 +encoding//Debug/c28x/subdir_rules.mk=UTF-8 +encoding//Debug/c28x/subdir_vars.mk=UTF-8 +encoding//Debug/drivers/subdir_rules.mk=UTF-8 +encoding//Debug/drivers/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/common/source/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/common/source/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/headers/cmd/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/headers/cmd/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/headers/source/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/headers/source/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd b/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd new file mode 100644 index 0000000000..b29ee84ff0 --- /dev/null +++ b/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd @@ -0,0 +1,135 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 + RAMGS15 : origin = 0x01B000, length = 0x001000 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 + RAMGS13 : origin = 0x019000, length = 0x001000 + + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : >> RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5 | RAMGS6 | RAMGS7 | RAMGS8 | RAMGS9 | RAMGS10 | RAMGS11 | RAMGS12 | RAMGS13 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/Kconfig b/bsp/tms320f28379d/Kconfig new file mode 100644 index 0000000000..de11cb4d79 --- /dev/null +++ b/bsp/tms320f28379d/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_TMS320F28X + bool + select ARCH_TIDSP_C28X + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" diff --git a/bsp/tms320f28379d/README.md b/bsp/tms320f28379d/README.md new file mode 100644 index 0000000000..b1d60dfd6f --- /dev/null +++ b/bsp/tms320f28379d/README.md @@ -0,0 +1,53 @@ +# TMS320F28379D + + +## 1. 简介 + +TMS320F28379D BSP 基于 C2000 Delfino MCU F28379D LaunchPad 开发套件开发。 +TMS320F28379D 是一款功能强大的 32 位浮点微控制器单元 (MCU)，针对高级闭环控制应用而设计，例如工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送以及电力线通信。包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| TMS320F28379D | +|多核 CPU| 两个 TMS320C28x 32 位 CPU +|| 两个可编程控制律加速器 (CLA) | +|主频| 200MHz | +|CLA 频率| 200MHz | +|总处理能力| 800MIPS | +|片内SRAM| 204kB | +|片内Flash| 1MB | + +## 2. 编译说明 + +编译使用 Code Composer Studio，在 Code Composer Studio 8.1.0 使用 TI v18.1.3.LTS 编译器已测试编译通过。 + +## 3. 烧写及执行 + +连接开发板电源后，使用 CCS 中的烧写功能可直接通过板载 XDS100v2 仿真器烧写并执行。 + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| CPU Timer | 支持 | | +| GPIO | 支持 | | +| SCI | 开发中 | SCIA/B，预计2018年9月底实现 | +| ePWM | | 预计2019年10月支持 | +| ADC | | 预计2019年10月支持 | +| DAC | | 预计2019/Q4支持| +| I2C | | | +| SPI | | | +| CAN | | | +| eCAP | | | + +## 5. 联系人信息 + +维护人：xuzhuoyi < xzy476386434@vip.qq.com > + +## 6. 参考 + +* [C2000 Delfino MCU F28379D LaunchPad 开发套件][1] +* TMS320F28379D [相关技术文档][2] + + [1]: http://www.ti.com.cn/tool/cn/launchxl-f28379d + [2]: http://www.ti.com.cn/product/cn/tms320f28379d/technicaldocuments diff --git a/bsp/tms320f28379d/applications/application.c b/bsp/tms320f28379d/applications/application.c new file mode 100644 index 0000000000..cecd70fa39 --- /dev/null +++ b/bsp/tms320f28379d/applications/application.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2014-04-27 Bernard make code cleanup. + */ + +#include +#include + +void rt_init_thread_entry(void* parameter) +{ + /* initialization RT-Thread Components */ + rt_components_init(); + +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + + if (tid != RT_NULL) + rt_thread_startup(tid); + + return 0; +} diff --git a/bsp/stm32f40x/applications/startup.c b/bsp/tms320f28379d/applications/startup.c similarity index 69% rename from bsp/stm32f40x/applications/startup.c rename to bsp/tms320f28379d/applications/startup.c index 6894d0f8ce..301e63a00a 100644 --- a/bsp/stm32f40x/applications/startup.c +++ b/bsp/tms320f28379d/applications/startup.c @@ -1,42 +1,25 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-08-31 Bernard first implementation - * 2011-06-05 Bernard modify for STM32F107 version + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version */ +#include #include #include -#include "stm32f4xx.h" #include "board.h" -/** - * @addtogroup STM32 - */ /*@{*/ extern int rt_application_init(void); -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define STM32_SRAM_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define STM32_SRAM_BEGIN (&__bss_end) -#endif /******************************************************************************* * Function Name : assert_failed @@ -47,7 +30,7 @@ extern int __bss_end; * Output : None * Return : None *******************************************************************************/ -void assert_failed(u8* file, u32 line) +void assert_failed(uint16_t* file, uint32_t line) { rt_kprintf("\n\r Wrong parameter value detected on\r\n"); rt_kprintf(" file %s\r\n", file); @@ -76,8 +59,6 @@ void rtthread_startup(void) /* init timer system */ rt_system_timer_init(); - rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END); - /* init scheduler system */ rt_system_scheduler_init(); diff --git a/bsp/tms320f28379d/drivers/board.c b/bsp/tms320f28379d/drivers/board.c new file mode 100644 index 0000000000..7960d80d1b --- /dev/null +++ b/bsp/tms320f28379d/drivers/board.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + */ +#include +#include "board.h" +#include "F28x_Project.h" + +extern interrupt void RTOSINT_Handler(); + + +/** + * This is the timer interrupt service routine. + * + */ +interrupt void cpu_timer2_isr (void) +{ + CpuTimer2Regs.TCR.all = 0x8000; + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + /* leave interrupt */ + rt_interrupt_leave(); +} + + +/** + * This function will initial STM32 board. + */ +void rt_hw_board_init() +{ + /* Configure the system clock @ 84 Mhz */ + InitSysCtrl(); + + DINT; + InitPieCtrl(); + + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TIMER2_INT = &cpu_timer2_isr; + PieVectTable.RTOS_INT = &RTOSINT_Handler; + EDIS; + + InitCpuTimers(); + ConfigCpuTimer(&CpuTimer2, 200, 1000000 / RT_TICK_PER_SECOND); + CpuTimer2Regs.TCR.all = 0x4000; + IER |= M_INT14; + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/tms320f28379d/drivers/board.h b/bsp/tms320f28379d/drivers/board.h new file mode 100644 index 0000000000..2a221a73f9 --- /dev/null +++ b/bsp/tms320f28379d/drivers/board.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ +#include + +#define C28X_SRAM_END 0x00020000 + + +#define HEAP_BEGIN 0x0000E000 +#define HEAP_END C28X_SRAM_END +extern void rt_hw_board_init(void); +#endif + diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd new file mode 100644 index 0000000000..9bc86fabf8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd @@ -0,0 +1,178 @@ +// The user must define CLA_C in the project linker settings if using the +// CLA C compiler +// Project Properties -> C2000 Linker -> Advanced Options -> Command File +// Preprocessing -> --define +#ifdef CLA_C +// Define a size for the CLA scratchpad area that will be used +// by the CLA compiler for local symbols and temps +// Also force references to the special symbols that mark the +// scratchpad are. +CLA_SCRATCHPAD_SIZE = 0x100; +--undef_sym=__cla_scratchpad_end +--undef_sym=__cla_scratchpad_start +#endif //CLA_C + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + /* RAMLS4 : origin = 0x00A000, length = 0x000800 */ + /* RAMLS5 : origin = 0x00A800, length = 0x000800 */ + RAMLS4_5 : origin = 0x00A000, length = 0x001000 + + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 + CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS2 PAGE = 1 + .esysmem : > RAMLS2 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + /* CLA specific sections */ + Cla1Prog : LOAD = FLASHD, + RUN = RAMLS4_5, + LOAD_START(_Cla1funcsLoadStart), + LOAD_END(_Cla1funcsLoadEnd), + RUN_START(_Cla1funcsRunStart), + LOAD_SIZE(_Cla1funcsLoadSize), + PAGE = 0, ALIGN(4) + + CLADataLS0 : > RAMLS0, PAGE=0 + CLADataLS1 : > RAMLS1, PAGE=0 + + Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 + CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMD0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMD0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + +#ifdef CLA_C + /* CLA C compiler sections */ + // + // Must be allocated to memory the CLA has write access to + // + CLAscratch : + { *.obj(CLAscratch) + . += CLA_SCRATCHPAD_SIZE; + *.obj(CLAscratch_end) } > RAMLS1, PAGE = 0 + + .scratchpad : > RAMLS1, PAGE = 0 + .bss_cla : > RAMLS1, PAGE = 0 + .const_cla : LOAD = FLASHB, + RUN = RAMLS1, + RUN_START(_Cla1ConstRunStart), + LOAD_START(_Cla1ConstLoadStart), + LOAD_SIZE(_Cla1ConstLoadSize), + PAGE = 0 +#endif //CLA_C +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd new file mode 100644 index 0000000000..afd9da2351 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd @@ -0,0 +1,134 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS5 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* Allocate IQ math areas: */ + IQmath : > FLASHB, PAGE = 0, ALIGN(4) /* Math Code */ + IQmathTables : > FLASHC, PAGE = 0, ALIGN(4) +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd new file mode 100644 index 0000000000..ffcab867e8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd @@ -0,0 +1,147 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + .cio : > RAMGS2, PAGE = 1 + + /* Sine Table */ + SINTBL : > FLASHN, PAGE = 1 + + /* Data Log */ + DLOG : > RAMGS3, PAGE = 1 + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd new file mode 100644 index 0000000000..e2d9e19e0f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd @@ -0,0 +1,136 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2_GS4 : origin = 0x00E000, length = 0x003000 + /* + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + */ + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMGS1 PAGE = 1 + .ebss : > RAMGS2_GS4 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + .sysmem : > RAMGS1, PAGE = 1 + .cio : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd new file mode 100644 index 0000000000..323926d783 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd @@ -0,0 +1,170 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x001800 + // RAMLS3 : origin = 0x009800, length = 0x000800 + // RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .cio : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + ramls2 : > RAMLS2, PAGE = 0 +// SINETABLE : > FLASHF PAGE = 0, ALIGN(4) + +fsk_corr_lib_data : > RAMGS5 PAGE = 1 /* Flash block for lib data */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 , + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 +SINETABLE : {} LOAD = FLASHF, + RUN = RAMLS2 , + LOAD_START(_SineTableLoadStart), + LOAD_SIZE(_SineTableLoadSize), + LOAD_END(_SineTableLoadEnd), + RUN_START(_SineTableRunStart), + RUN_SIZE(_SineTableRunSize), + RUN_END(_SineTableRunEnd), + PAGE = 0, ALIGN(4) + + #else +SINETABLE : LOAD = FLASHF, + RUN = RAMLS2 , + LOAD_START(_SineTableLoadStart), + LOAD_SIZE(_SineTableLoadSize), + LOAD_END(_SineTableLoadEnd), + RUN_START(_SineTableRunStart), + RUN_SIZE(_SineTableRunSize), + RUN_END(_SineTableRunEnd), + PAGE = 0, ALIGN(4) + + #endif +#endif + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd new file mode 100644 index 0000000000..b1dadb8351 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd @@ -0,0 +1,142 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .cio : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd new file mode 100644 index 0000000000..f8744f3935 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd @@ -0,0 +1,156 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .farbss : > EMIF1_CS0n, PAGE = 1 + + .em1_cs0 : > EMIF1_CS0n, PAGE = 1 + .em1_cs2 : > EMIF1_CS2n, PAGE = 1 + .em1_cs3 : > EMIF1_CS3n, PAGE = 1 + .em1_cs4 : > EMIF1_CS4n, PAGE = 1 + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .farconst : > EMIF1_CS0n, PAGE = 1 + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd new file mode 100644 index 0000000000..038dfdbed8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd @@ -0,0 +1,114 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS5 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd new file mode 100644 index 0000000000..bd7aff0faf --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd @@ -0,0 +1,120 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS5 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .farbss : > EMIF1_CS0n, PAGE = 1 + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .farconst : > EMIF1_CS0n, PAGE = 1 + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd new file mode 100644 index 0000000000..55100fcccb --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd @@ -0,0 +1,135 @@ +// The user must define CLA_C in the project linker settings if using the +// CLA C compiler +// Project Properties -> C2000 Linker -> Advanced Options -> Command File +// Preprocessing -> --define +#ifdef CLA_C +// Define a size for the CLA scratchpad area that will be used +// by the CLA compiler for local symbols and temps +// Also force references to the special symbols that mark the +// scratchpad are. +CLA_SCRATCHPAD_SIZE = 0x100; +--undef_sym=__cla_scratchpad_end +--undef_sym=__cla_scratchpad_start +#endif //CLA_C + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMD1 : origin = 0x00B800, length = 0x000800 + /* RAMLS4 : origin = 0x00A000, length = 0x000800 */ + /* RAMLS5 : origin = 0x00A800, length = 0x000800 */ + RAMLS4_5 : origin = 0x00A000, length = 0x001000 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 + CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMM0 | RAMD0 | RAMD1, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS2, PAGE = 1 + .econst : > RAMLS3, PAGE = 1 + .esysmem : > RAMLS3, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + .em1_cs0 : > EMIF1_CS0n, PAGE = 1 + .em1_cs2 : > EMIF1_CS2n, PAGE = 1 + .em1_cs3 : > EMIF1_CS3n, PAGE = 1 + .em1_cs4 : > EMIF1_CS4n, PAGE = 1 + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + /* CLA specific sections */ + Cla1Prog : > RAMLS4_5, PAGE=0 + + CLADataLS0 : > RAMLS0, PAGE=1 + CLADataLS1 : > RAMLS1, PAGE=1 + + Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 + CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + +#ifdef CLA_C + /* CLA C compiler sections */ + // + // Must be allocated to memory the CLA has write access to + // + CLAscratch : + { *.obj(CLAscratch) + . += CLA_SCRATCHPAD_SIZE; + *.obj(CLAscratch_end) } > RAMLS1, PAGE = 1 + + .scratchpad : > RAMLS1, PAGE = 1 + .bss_cla : > RAMLS1, PAGE = 1 + .const_cla : > RAMLS1, PAGE = 1 +#endif //CLA_C +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd new file mode 100644 index 0000000000..690c322d80 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd @@ -0,0 +1,38 @@ +/* Linker map for Soprano Shared Memory. */ + +MEMORY +{ +PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */ + + +PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +* =========================================================================== +* End of file. +* =========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd new file mode 100644 index 0000000000..ca157058ee --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd @@ -0,0 +1,37 @@ +/* Linker map for Soprano Shared Memory. */ + +MEMORY +{ +PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */ + +PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +* =========================================================================== +* End of file. +* =========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd new file mode 100644 index 0000000000..405efe5900 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd @@ -0,0 +1,103 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1_LS2 : origin = 0x008800, length = 0x001000 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1_LS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 + + /* Allocate IQ math areas: */ + IQmath : > RAMLS0, PAGE = 0 /* Math Code */ + IQmathTables : > RAMLS1_LS2, PAGE = 0 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd new file mode 100644 index 0000000000..0f42056151 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd @@ -0,0 +1,106 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + .cio : > RAMGS2, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* Sine Table */ + SINTBL : > RAMGS2, PAGE = 1 + + /* Data Log */ + DLOG : > RAMGS3, PAGE = 1 + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd new file mode 100644 index 0000000000..b5c4b58c78 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd @@ -0,0 +1,89 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + RAMGS0_2 : origin = 0x00C000, length = 0x003000 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMGS0_2, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd new file mode 100644 index 0000000000..22e06c6e58 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd @@ -0,0 +1,97 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMLS5 : origin = 0x00A800, length = 0x000800 + RAMGS0 : origin = 0x00C000, length = 0x001000 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2_GS4 : origin = 0x00E000, length = 0x003000 + /* + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + */ + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text :>> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMGS1, PAGE = 1 + .ebss : > RAMGS2_GS4,PAGE = 1 + .econst : > RAMGS1, PAGE = 1 + .esysmem : > RAMGS1, PAGE = 1 + Filter_RegsFile : > RAMGS1, PAGE = 1 + + .sysmem : > RAMGS1, PAGE = 1 + .cio : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd new file mode 100644 index 0000000000..5da6b7958c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd @@ -0,0 +1,99 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS234 : origin = 0x009000, length = 0x001800 + // RAMLS3 : origin = 0x009800, length = 0x000800 + // RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMLS5 : origin = 0x00A800, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMD0 | RAMLS0 | RAMLS1, PAGE = 0 + .cinit : >RAMM0 , PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : >> RAMGS0, PAGE = 1 + .econst : >> RAMLS234, PAGE = 0 + .esysmem : > RAMLS5, PAGE = 0 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS3, PAGE = 1 + + SINETABLE : > RAMLS234 PAGE = 0 /* Ram block for SINETABLE data */ + fsk_corr_lib_data : > RAMGS5, PAGE = 1 /* Ram block for lib data */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd new file mode 100644 index 0000000000..1561ba58b7 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd @@ -0,0 +1,103 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd new file mode 100644 index 0000000000..0b470f5951 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd @@ -0,0 +1,97 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x002000 + + + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS01 : origin = 0x008000, length = 0x001000 +/* RAMLS1 : origin = 0x008800, length = 0x000800 */ + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3_RAMLS4_RAMLS5 : origin = 0x009800, length = 0x001800 +/* RAMLS3 : origin = 0x009800, length = 0x000800 */ +/* RAMLS4 : origin = 0x00A000, length = 0x000800 */ +/* RAMLS5 : origin = 0x00A800, length = 0x000800 */ + + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5, PAGE = 0 + .cio : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + .sysmem : > RAMD1, PAGE = 1 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : >> RAMLS01 | RAMLS2 | RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + .econst : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + .esysmem : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd new file mode 100644 index 0000000000..709c066557 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd @@ -0,0 +1,121 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + + .farbss : > EMIF1_CS0n, PAGE = 1 + .farconst : > EMIF1_CS0n, PAGE = 1 + + .em1_cs0 : > EMIF1_CS0n, PAGE = 1 + .em1_cs2 : > EMIF1_CS2n, PAGE = 1 + .em1_cs3 : > EMIF1_CS3n, PAGE = 1 + .em1_cs4 : > EMIF1_CS4n, PAGE = 1 + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd new file mode 100644 index 0000000000..764ae4bea2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd @@ -0,0 +1,75 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd new file mode 100644 index 0000000000..976309764d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd @@ -0,0 +1,83 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + + .farbss : > EMIF1_CS0n, PAGE = 1 + .farconst : > EMIF1_CS0n, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd new file mode 100644 index 0000000000..d7f5abe0a1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd @@ -0,0 +1,92 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + SHARERAMGS3 : > RAMGS3, PAGE = 1 + SHARERAMGS4 : > RAMGS4, PAGE = 1 + SHARERAMGS5 : > RAMGS5, PAGE = 1 + SHARERAMGS6 : > RAMGS6, PAGE = 1 + SHARERAMGS7 : > RAMGS7, PAGE = 1 + SHARERAMGS8 : > RAMGS8, PAGE = 1 + SHARERAMGS9 : > RAMGS9, PAGE = 1 + SHARERAMGS10 : > RAMGS10, PAGE = 1 + SHARERAMGS11 : > RAMGS11, PAGE = 1 + SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS15 : > RAMGS15, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd new file mode 100644 index 0000000000..da95201cf9 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd @@ -0,0 +1,92 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + SHARERAMGS3 : > RAMGS3, PAGE = 1 + SHARERAMGS4 : > RAMGS4, PAGE = 1 + SHARERAMGS5 : > RAMGS5, PAGE = 1 + SHARERAMGS6 : > RAMGS6, PAGE = 1 + SHARERAMGS7 : > RAMGS7, PAGE = 1 + SHARERAMGS8 : > RAMGS8, PAGE = 1 + SHARERAMGS9 : > RAMGS9, PAGE = 1 + SHARERAMGS10 : > RAMGS10, PAGE = 1 + SHARERAMGS11 : > RAMGS11, PAGE = 1 + SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS15 : > RAMGS15, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd new file mode 100644 index 0000000000..ff0d4cb751 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd @@ -0,0 +1,68 @@ + +/* this linker command file is to be included if user wants to use the DCSM feature on the device + * DCSM means Dual Zone Code Security Module. + * This linker command file works as an addendum ot the already existing Flash/RAM linker command file + * that the project has. + * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file + * NOTE - please note fill=0xFFFF, this helps if users include this file in the project by mistake and + * doesn't provide the needed proper *_ZoneSelectBlock.asm sources . + * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this. + * + * Once users are confident that they want to program the passwords in OTP, the DSECT section type can be removed. + * +*/ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + + /* Z1 OTP. LinkPointers */ + DCSM_OTP_Z1_LINKPOINTER : origin = 0x78000, length = 0x00000C + /* Z1 OTP. PSWDLOCK/RESERVED */ + DCSM_OTP_Z1_PSWDLOCK : origin = 0x78010, length = 0x000004 + /* Z1 OTP. CRCLOCK/RESERVED */ + DCSM_OTP_Z1_CRCLOCK : origin = 0x78014, length = 0x000004 + /* Z1 OTP. RESERVED/BOOTCTRL */ + DCSM_OTP_Z1_BOOTCTRL : origin = 0x7801C, length = 0x000004 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Z1 OTP. Z1 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010 + + /* Z2 OTP. LinkPointers */ + DCSM_OTP_Z2_LINKPOINTER : origin = 0x78200, length = 0x00000C + /* Z2 OTP. GPREG1/GPREG2 */ + DCSM_OTP_Z2_GPREG : origin = 0x7820C, length = 0x000004 + /* Z2 OTP. PSWDLOCK/RESERVED */ + DCSM_OTP_Z2_PSWDLOCK : origin = 0x78210, length = 0x000004 + /* Z2 OTP. CRCLOCK/RESERVED */ + DCSM_OTP_Z2_CRCLOCK : origin = 0x78214, length = 0x000004 + /* Z2 OTP. GPREG3/BOOTCTRL */ + DCSM_OTP_Z2_BOOTCTRL : origin = 0x7821C, length = 0x000004 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Z2 OTP. Z2 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010 + +} + +SECTIONS +{ + dcsm_otp_z1_linkpointer : > DCSM_OTP_Z1_LINKPOINTER PAGE = 0, type = DSECT + dcsm_otp_z1_pswdlock : > DCSM_OTP_Z1_PSWDLOCK PAGE = 0, type = DSECT + dcsm_otp_z1_crclock : > DCSM_OTP_Z1_CRCLOCK PAGE = 0, type = DSECT + dcsm_otp_z1_bootctrl : > DCSM_OTP_Z1_BOOTCTRL PAGE = 0, type = DSECT + dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0 PAGE = 0, type = DSECT + + dcsm_otp_z2_linkpointer : > DCSM_OTP_Z2_LINKPOINTER PAGE = 0, type = DSECT + dcsm_otp_z2_pswdlock : > DCSM_OTP_Z2_PSWDLOCK PAGE = 0, type = DSECT + dcsm_otp_z2_crclock : > DCSM_OTP_Z2_CRCLOCK PAGE = 0, type = DSECT + dcsm_otp_z2_bootctrl : > DCSM_OTP_Z2_BOOTCTRL PAGE = 0, type = DSECT + dcsm_zsel_z2 : > DCSM_ZSEL_Z2_P0 PAGE = 0, type = DSECT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd new file mode 100644 index 0000000000..38111c8a18 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd @@ -0,0 +1,44 @@ + +/* this linker command file is to be included if user wants to use the DCSM feature on the device + * DCSM means Dual Zone Code Security Module. + * This linker command file works as an addendum ot the already existing Flash/RAM linker command file + * that the project has. + * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file + * NOTEG - please note fill=0xFFFF, this helps if users include this file in the project by mistake and + * doesn't provide the needed *_ZoneSelectBlock.asm sources. + * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this. +*/ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + + /* Part of Z1 OTP. LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */ + DCSM_OTP_Z1_P0 : origin = 0x78000, length = 0x000020 + /* Part of Z2 OTP. LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */ + DCSM_OTP_Z2_P0 : origin = 0x78200, length = 0x000020 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Part of Z1 OTP. Z1 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Part of Z2 OTP. Z2 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010 +} + + +SECTIONS +{ + dcsm_otp_z1 : > DCSM_OTP_Z1_P0, PAGE = 0, type = DSECT + dcsm_otp_z2 : > DCSM_OTP_Z2_P0, PAGE = 0, type = DSECT + + dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0, PAGE = 0, type = DSECT + dcsm_zsel_z2 : > DCSM_ZSEL_Z2_P0, PAGE = 0, type = DSECT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf b/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf new file mode 100644 index 0000000000..759a3d87ff Binary files /dev/null and b/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf differ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/can.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c similarity index 50% rename from bsp/tm4c129x-dk/libraries/driverlib/can.c rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c index d53584585c..72343c5094 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/can.c +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c @@ -1,139 +1,110 @@ -//***************************************************************************** +//########################################################################### // -// can.c - Driver for the CAN module. +// FILE: can.c // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// TITLE: F2837xD CAN Initialization & Support Functions. +// +// NOTE: The CAN bus bridge uses a different addressing scheme in order to +// allow byte accesses. Because of this, 32-bit reads/writes can execute +// abnormally at higher optimization levels. The CAN driver functions +// have been adjusted to explicitly use two 16-bit read/writes to access +// the full 32-bit register where HWREGH(base + offset) represents the +// lower 16-bits and HWREGH(base + offset + 2) represents the upper +// 16-bits. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### //***************************************************************************** -// //! \addtogroup can_api //! @{ -// //***************************************************************************** -#include +#include "F28x_Project.h" #include +#include #include "inc/hw_can.h" #include "inc/hw_ints.h" -#include "inc/hw_nvic.h" #include "inc/hw_memmap.h" -#include "inc/hw_sysctl.h" #include "inc/hw_types.h" #include "driverlib/can.h" #include "driverlib/debug.h" #include "driverlib/interrupt.h" //***************************************************************************** -// // This is the maximum number that can be stored as an 11bit Message // identifier. -// //***************************************************************************** -#define CAN_MAX_11BIT_MSG_ID 0x7ff +#define CAN_MAX_11BIT_MSG_ID (0x7ff) //***************************************************************************** -// -// The maximum CAN bit timing divisor is 19. -// +// This is used as the loop delay for accessing the CAN controller registers. //***************************************************************************** -#define CAN_MAX_BIT_DIVISOR 19 -//***************************************************************************** -// -// The minimum CAN bit timing divisor is 4. -// -//***************************************************************************** -#define CAN_MIN_BIT_DIVISOR 4 +// The maximum CAN bit timing divisor is 13. +#define CAN_MAX_BIT_DIVISOR (13) + +// The minimum CAN bit timing divisor is 5. +#define CAN_MIN_BIT_DIVISOR (5) -//***************************************************************************** -// // The maximum CAN pre-divisor is 1024. -// -//***************************************************************************** -#define CAN_MAX_PRE_DIVISOR 1024 +#define CAN_MAX_PRE_DIVISOR (1024) -//***************************************************************************** -// // The minimum CAN pre-divisor is 1. -// -//***************************************************************************** -#define CAN_MIN_PRE_DIVISOR 1 +#define CAN_MIN_PRE_DIVISOR (1) //***************************************************************************** -// -// Converts a set of CAN bit timing values into the value that needs to be -// programmed into the CAN_BIT register to achieve those timings. -// -//***************************************************************************** -#define CAN_BIT_VALUE(seg1, seg2, sjw) \ - ((((seg1 - 1) << CAN_BIT_TSEG1_S) & \ - CAN_BIT_TSEG1_M) | \ - (((seg2 - 1) << CAN_BIT_TSEG2_S) & \ - CAN_BIT_TSEG2_M) | \ - (((sjw - 1) << CAN_BIT_SJW_S) & \ - CAN_BIT_SJW_M)) - -//***************************************************************************** -// // This table is used by the CANBitRateSet() API as the register defaults for // the bit timing values. -// //***************************************************************************** + static const uint16_t g_ui16CANBitValues[] = { - CAN_BIT_VALUE(2, 1, 1), // 4 clocks/bit - CAN_BIT_VALUE(3, 1, 1), // 5 clocks/bit - CAN_BIT_VALUE(3, 2, 2), // 6 clocks/bit - CAN_BIT_VALUE(4, 2, 2), // 7 clocks/bit - CAN_BIT_VALUE(4, 3, 3), // 8 clocks/bit - CAN_BIT_VALUE(5, 3, 3), // 9 clocks/bit - CAN_BIT_VALUE(5, 4, 4), // 10 clocks/bit - CAN_BIT_VALUE(6, 4, 4), // 11 clocks/bit - CAN_BIT_VALUE(6, 5, 4), // 12 clocks/bit - CAN_BIT_VALUE(7, 5, 4), // 13 clocks/bit - CAN_BIT_VALUE(7, 6, 4), // 14 clocks/bit - CAN_BIT_VALUE(8, 6, 4), // 15 clocks/bit - CAN_BIT_VALUE(8, 7, 4), // 16 clocks/bit - CAN_BIT_VALUE(9, 7, 4), // 17 clocks/bit - CAN_BIT_VALUE(9, 8, 4), // 18 clocks/bit - CAN_BIT_VALUE(10, 8, 4) // 19 clocks/bit + 0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5 + 0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6 + 0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7 + 0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8 + 0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9 + 0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10 + 0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11 + 0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12 + 0x3740 // TSEG2 4, TSEG1 8, SJW 2, Divide 13 }; //***************************************************************************** -// //! \internal //! Checks a CAN base address. //! @@ -147,74 +118,106 @@ static const uint16_t g_ui16CANBitValues[] = //***************************************************************************** #ifdef DEBUG static bool -_CANBaseValid(uint32_t ui32Base) +CANBaseValid(uint32_t ui32Base) { - return((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE)); + return((ui32Base == CANA_BASE) || (ui32Base == CANB_BASE)); } + #endif //***************************************************************************** -// +//! \internal +//! //! Returns the CAN controller interrupt number. //! //! \param ui32Base is the base address of the selected CAN controller +//! \param ucNumber is the interrupt line number requested, valid values are 0 +//! or 1 //! -//! This function returns the interrupt number for the CAN module with the base -//! address passed in the \e ui32Base parameter. +//! Given a CAN controller base address and interrupt line number, returns the +//! corresponding interrupt number. //! -//! \return Returns a CAN interrupt number or 0 if the interrupt does not -//! exist. +//! \return Returns a CAN interrupt number, or -1 if \e ui32Port is invalid. // //***************************************************************************** -static uint_fast8_t -_CANIntNumberGet(uint32_t ui32Base) +static int32_t +CANIntNumberGet(uint32_t ui32Base, unsigned char ucNumber) { - uint_fast8_t ui8Int; + int32_t lIntNumber; - ASSERT((ui32Base == CAN0_BASE) || (ui32Base == CAN1_BASE)); - - ui8Int = 0; - - // - // Find the valid interrupt number for this CAN controller. - // - if(CLASS_IS_TM4C123) + // Return the interrupt number for the given CAN controller. + switch(ui32Base) { - if(ui32Base == CAN0_BASE) + // Return the interrupt number for CAN 0 + case CANA_BASE: { - ui8Int = INT_CAN0_TM4C123; + switch(ucNumber) + { + case 0: + { + lIntNumber = INT_CANA_0; + break; + } + case 1: + { + lIntNumber = INT_CANA_1; + break; + + } + default: + { + lIntNumber = -1; + break; + } + } + break; } - else if(ui32Base == CAN1_BASE) + + // Return the interrupt number for CAN 1 + case CANB_BASE: { - ui8Int = INT_CAN1_TM4C123; + switch(ucNumber) + { + case 0: + { + lIntNumber = INT_CANB_0; + break; + } + case 1: + { + lIntNumber = INT_CANB_1; + break; + + } + default: + { + lIntNumber = -1; + break; + } + } + break; + } + + // Return -1 to indicate a bad address was passed in. + default: + { + lIntNumber = -1; } } - else if(CLASS_IS_TM4C129) - { - if(ui32Base == CAN0_BASE) - { - ui8Int = INT_CAN0_TM4C129; - } - else if(ui32Base == CAN1_BASE) - { - ui8Int = INT_CAN1_TM4C129; - } - } - - return(ui8Int); + return(lIntNumber); } //***************************************************************************** -// //! \internal +//! //! Copies data from a buffer to the CAN Data registers. //! -//! \param pui8Data is a pointer to the data to be written out to the CAN +//! \param pucData is a pointer to the data to be written out to the CAN //! controller's data registers. //! \param pui32Register is an uint32_t pointer to the first register of the //! CAN controller's data registers. For example, in order to use the IF1 -//! register set on CAN controller 0, the value would be: \b CAN0_BASE \b + -//! \b CAN_O_IF1DA1. +//! register set on CAN controller A, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. //! \param iSize is the number of bytes to copy into the CAN controller. //! //! This function takes the steps necessary to copy data from a contiguous @@ -222,48 +225,38 @@ _CANIntNumberGet(uint32_t ui32Base) //! controller. This function is rarely used outside of the CANMessageSet() //! function. //! +//! This function replaces the original CANWriteDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! //! \return None. // //***************************************************************************** static void -_CANDataRegWrite(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) +CANDataRegWrite(unsigned char *pucData, uint32_t *pui32Register, int16_t iSize) { - uint32_t ui32Idx, ui32Value; + int16_t iIdx; + unsigned char * pucRegister = (unsigned char *) pui32Register; - // // Loop always copies 1 or 2 bytes per iteration. - // - for(ui32Idx = 0; ui32Idx < ui32Size; ) + for(iIdx = 0; iIdx < iSize; iIdx++ ) { - // - // Write out the data 16 bits at a time since this is how the registers - // are aligned in memory. - // - ui32Value = pui8Data[ui32Idx++]; - - // - // Only write the second byte if needed otherwise the value is zero. - // - if(ui32Idx < ui32Size) - { - ui32Value |= (pui8Data[ui32Idx++] << 8); - } - - HWREG(pui32Register++) = ui32Value; + // Write out the data 8 bits at a time. + HWREGB(pucRegister++) = pucData[iIdx]; } } //***************************************************************************** -// //! \internal +//! //! Copies data from a buffer to the CAN Data registers. //! -//! \param pui8Data is a pointer to the location to store the data read from -//! the CAN controller's data registers. +//! \param pucData is a pointer to the location to store the data read from the +//! CAN controller's data registers. //! \param pui32Register is an uint32_t pointer to the first register of the //! CAN controller's data registers. For example, in order to use the IF1 -//! register set on CAN controller 1, the value would be: \b CAN0_BASE \b + -//! \b CAN_O_IF1DA1. +//! register set on CAN controller A, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. //! \param iSize is the number of bytes to copy from the CAN controller. //! //! This function takes the steps necessary to copy data to a contiguous buffer @@ -271,37 +264,24 @@ _CANDataRegWrite(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) //! controller. This function is rarely used outside of the CANMessageGet() //! function. //! +//! This function replaces the original CANReadDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! //! \return None. // //***************************************************************************** static void -_CANDataRegRead(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) +CANDataRegRead(unsigned char *pucData, uint32_t *pui32Register, int16_t iSize) { - uint32_t ui32Idx, ui32Value; + int16_t iIdx; + unsigned char * pucRegister = (unsigned char *) pui32Register; - // // Loop always copies 1 or 2 bytes per iteration. - // - for(ui32Idx = 0; ui32Idx < ui32Size; ) + for(iIdx = 0; iIdx < iSize; iIdx++ ) { - // - // Read out the data 16 bits at a time since this is how the registers - // are aligned in memory. - // - ui32Value = HWREG(pui32Register++); - - // - // Store the first byte. - // - pui8Data[ui32Idx++] = (uint8_t)ui32Value; - - // - // Only read the second byte if needed. - // - if(ui32Idx < ui32Size) - { - pui8Data[ui32Idx++] = (uint8_t)(ui32Value >> 8); - } + // Read out the data + pucData[iIdx] = HWREGB(pucRegister++); } } @@ -324,84 +304,91 @@ _CANDataRegRead(uint8_t *pui8Data, uint32_t *pui32Register, uint32_t ui32Size) void CANInit(uint32_t ui32Base) { - uint32_t ui32Msg; + int16_t iMsg; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Place CAN controller in init state, regardless of previous state. This - // puts controller in idle, and allow the message object RAM to be + // will put controller in idle, and allow the message object RAM to be // programmed. - // - HWREG(ui32Base + CAN_O_CTL) = CAN_CTL_INIT; - // + HWREGH(ui32Base + CAN_O_CTL) = CAN_CTL_INIT; + HWREGH(ui32Base + CAN_O_CTL) = CAN_CTL_SWR; + // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } - // // Clear the message value bit in the arbitration register. This indicates // the message is not valid and is a "safe" condition to leave the message // object. The same arb reg is used to program all the message objects. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB | - CAN_IF1CMSK_CONTROL); - HWREG(ui32Base + CAN_O_IF1ARB2) = 0; - HWREG(ui32Base + CAN_O_IF1MCTL) = 0; + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_DIR | CAN_IF1CMD_ARB | + CAN_IF1CMD_CONTROL) >> 16; + HWREGH(ui32Base + CAN_O_IF1ARB) = 0; + HWREGH(ui32Base + CAN_O_IF1ARB + 2) = 0; + + HWREGH(ui32Base + CAN_O_IF1MCTL) = 0; + HWREGH(ui32Base + CAN_O_IF1MCTL + 2) = 0; + + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = (CAN_IF2CMD_DIR | CAN_IF2CMD_ARB | + CAN_IF2CMD_CONTROL) >> 16; + HWREGH(ui32Base + CAN_O_IF2ARB) = 0; + HWREGH(ui32Base + CAN_O_IF2ARB + 2) = 0; + + HWREGH(ui32Base + CAN_O_IF2MCTL) = 0; + HWREGH(ui32Base + CAN_O_IF2MCTL + 2) = 0; - // // Loop through to program all 32 message objects - // - for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++) + for(iMsg = 1; iMsg <= 32; iMsg+=2) { - // // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } - // // Initiate programming the message object - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg; + HWREGH(ui32Base + CAN_O_IF1CMD) = iMsg; + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) + { + } + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF2CMD) = iMsg + 1; } - // // Make sure that the interrupt and new data flags are updated for the // message objects. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = (CAN_IF1CMSK_NEWDAT | - CAN_IF1CMSK_CLRINTPND); + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_TXRQST | + CAN_IF1CMD_CLRINTPND) >> 16; + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = (CAN_IF2CMD_TXRQST | + CAN_IF2CMD_CLRINTPND) >> 16; - // // Loop through to program all 32 message objects - // - for(ui32Msg = 1; ui32Msg <= 32; ui32Msg++) + for(iMsg = 1; iMsg <= 32; iMsg+=2) { - // // Wait for busy bit to clear. - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } - // // Initiate programming the message object - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32Msg; + HWREGH(ui32Base + CAN_O_IF1CMD) = iMsg; + + // Wait for busy bit to clear. + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) + { + } + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF2CMD) = iMsg + 1; } - // // Acknowledge any pending status interrupts. - // - HWREG(ui32Base + CAN_O_STS); + HWREG(ui32Base + CAN_O_ES); } //***************************************************************************** @@ -411,10 +398,10 @@ CANInit(uint32_t ui32Base) //! \param ui32Base is the base address of the CAN controller to enable. //! //! Enables the CAN controller for message processing. Once enabled, the -//! controller automatically transmits any pending frames, and processes any +//! controller will automatically transmit any pending frames, and process any //! received frames. The controller can be stopped by calling CANDisable(). -//! Prior to calling CANEnable(), CANInit() must have been called to -//! initialize the controller and the CAN bus clock must be configured by +//! Prior to calling CANEnable(), CANInit() should have been called to +//! initialize the controller and the CAN bus clock should be configured by //! calling CANBitTimingSet(). //! //! \return None. @@ -423,15 +410,12 @@ CANInit(uint32_t ui32Base) void CANEnable(uint32_t ui32Base) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Clear the init bit in the control register. - // - HWREG(ui32Base + CAN_O_CTL) &= ~CAN_CTL_INIT; + HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) & + ~CAN_CTL_INIT; } //***************************************************************************** @@ -441,7 +425,7 @@ CANEnable(uint32_t ui32Base) //! \param ui32Base is the base address of the CAN controller to disable. //! //! Disables the CAN controller for message processing. When disabled, the -//! controller no longer automatically processes data on the CAN bus. The +//! controller will no longer automatically process data on the CAN bus. The //! controller can be restarted by calling CANEnable(). The state of the CAN //! controller and the message objects in the controller are left as they were //! before this call was made. @@ -452,15 +436,50 @@ CANEnable(uint32_t ui32Base) void CANDisable(uint32_t ui32Base) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Set the init bit in the control register. - // - HWREG(ui32Base + CAN_O_CTL) |= CAN_CTL_INIT; + HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) | + CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Select CAN peripheral clock source +//! +//! \param ui32Base is the base address of the CAN controller to disable. +//! \param ui16Source is the clock source to select for the given CAN +//! peripheral: \n +//! 0 - Selected CPU SYSCLKOUT (CPU1.Sysclk or CPU2.Sysclk) +//! (default at reset) \n +//! 1 - External Oscillator (OSC) clock (direct from X1/X2) \n +//! 2 - AUXCLKIN = GPIOn(GPIO19) +//! +//! Selects the desired clock source for use with a given CAN peripheral. +//! +//! \return None. +// +//***************************************************************************** +void CANClkSourceSelect(uint32_t ui32Base, uint16_t ui16Source) +{ + EALLOW; + switch(ui32Base) + { + case CANA_BASE: + { + ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = ui16Source; + } + + case CANB_BASE: + { + ClkCfgRegs.CLKSRCCTL2.bit.CANBBCLKSEL = ui16Source; + } + + default: + break; + } + EDIS; } //***************************************************************************** @@ -468,91 +487,70 @@ CANDisable(uint32_t ui32Base) //! Reads the current settings for the CAN controller bit timing. //! //! \param ui32Base is the base address of the CAN controller. -//! \param psClkParms is a pointer to a structure to hold the timing -//! parameters. +//! \param pClkParms is a pointer to a structure to hold the timing parameters. //! //! This function reads the current configuration of the CAN controller bit -//! clock timing and stores the resulting information in the structure +//! clock timing, and stores the resulting information in the structure //! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the -//! values that are returned in the structure pointed to by \e psClkParms. +//! values that are returned in the structure pointed to by \e pClkParms. +//! +//! This function replaces the original CANGetBitTiming() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. //! //! \return None. // //***************************************************************************** void -CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms) +CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms) { - uint32_t ui32BitReg; + uint32_t uBitReg; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT(psClkParms); + ASSERT(CANBaseValid(ui32Base)); + ASSERT(pClkParms != 0); - // - // Read out all the bit timing values from the CAN controller registers. - // - ui32BitReg = HWREG(ui32Base + CAN_O_BIT); + uBitReg = HWREG(ui32Base + CAN_O_BTR); - // // Set the phase 2 segment. - // - psClkParms->ui32Phase2Seg = - ((ui32BitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1; + pClkParms->uPhase2Seg = ((uBitReg & CAN_BTR_TSEG2_M) >> 12) + 1; - // // Set the phase 1 segment. - // - psClkParms->ui32SyncPropPhase1Seg = - ((ui32BitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1; + pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BTR_TSEG1_M) >> 8) + 1; - // // Set the synchronous jump width. - // - psClkParms->ui32SJW = ((ui32BitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1; + pClkParms->uSJW = ((uBitReg & CAN_BTR_SJW_M) >> 6) + 1; - // // Set the pre-divider for the CAN bus bit clock. - // - psClkParms->ui32QuantumPrescaler = - ((ui32BitReg & CAN_BIT_BRP_M) | - ((HWREG(ui32Base + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1; + pClkParms->uQuantumPrescaler = ((uBitReg & CAN_BTR_BRP_M) | + ((uBitReg & CAN_BTR_BRPE_M) >> 10)) + 1; } //***************************************************************************** // -//! Sets the CAN bit timing values to a nominal setting based on a desired -//! bit rate. +//! This function is used to set the CAN bit timing values to a nominal setting +//! based on a desired bit rate. //! //! \param ui32Base is the base address of the CAN controller. -//! \param ui32SourceClock is the system clock for the device in Hz. +//! \param ui32SourceClock is the clock frequency for the CAN peripheral in Hz. //! \param ui32BitRate is the desired bit rate. //! -//! This function sets the CAN bit timing for the bit rate passed in the -//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter. -//! Because the CAN clock is based off of the system clock, the calling -//! function must pass in the source clock rate either by retrieving it from -//! SysCtlClockGet() or using a specific value in Hz. The CAN bit timing is -//! calculated assuming a minimal amount of propagation delay, which works for -//! most cases where the network length is short. If tighter timing -//! requirements or longer network lengths are needed, then the +//! This function will set the CAN bit timing for the bit rate passed in the +//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter. The CAN +//! bit clock is calculated to be an average timing value that should work for +//! most systems. If tighter timing requirements are needed, then the //! CANBitTimingSet() function is available for full customization of all of -//! the CAN bit timing values. Because not all bit rates can be matched +//! the CAN bit timing values. Since not all bit rates can be matched //! exactly, the bit rate is set to the value closest to the desired bit rate //! without being higher than the \e ui32BitRate value. //! -//! \note On some devices the source clock is fixed at 8MHz so the -//! \e ui32SourceClock must be set to 8000000. -//! //! \return This function returns the bit rate that the CAN controller was //! configured to use or it returns 0 to indicate that the bit rate was not //! changed because the requested bit rate was not valid. -//! +// //***************************************************************************** uint32_t -CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, - uint32_t ui32BitRate) +CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, uint32_t ui32BitRate) { uint32_t ui32DesiredRatio; uint32_t ui32CANBits; @@ -560,113 +558,75 @@ CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, uint32_t ui32RegValue; uint16_t ui16CANCTL; - // - // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT(ui32SourceClock); - ASSERT(ui32BitRate); + ASSERT(ui32BitRate != 0); - // // Calculate the desired clock rate. - // ui32DesiredRatio = ui32SourceClock / ui32BitRate; - // - // Make sure that the ratio of CAN bit rate to processor clock is not too - // small or too large. - // + // If the ratio of CAN bit rate to processor clock is too small or too + // large then return 0 indicating that no bit rate was set. ASSERT(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)); ASSERT(ui32DesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)); - // // Make sure that the Desired Ratio is not too large. This enforces the // requirement that the bit rate is larger than requested. - // if((ui32SourceClock / ui32DesiredRatio) > ui32BitRate) { ui32DesiredRatio += 1; } - // // Check all possible values to find a matching value. - // - while(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)) + while(ui32DesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR) { - // // Loop through all possible CAN bit divisors. - // for(ui32CANBits = CAN_MAX_BIT_DIVISOR; - ui32CANBits >= CAN_MIN_BIT_DIVISOR; ui32CANBits--) + ui32CANBits >= CAN_MIN_BIT_DIVISOR; + ui32CANBits--) { - // // For a given CAN bit divisor save the pre divisor. - // ui32PreDivide = ui32DesiredRatio / ui32CANBits; - // // If the calculated divisors match the desired clock ratio then // return these bit rate and set the CAN bit timing. - // if((ui32PreDivide * ui32CANBits) == ui32DesiredRatio) { - // // Start building the bit timing value by adding the bit timing // in time quanta. - // - ui32RegValue = g_ui16CANBitValues[ui32CANBits - - CAN_MIN_BIT_DIVISOR]; + ui32RegValue = + g_ui16CANBitValues[ui32CANBits - CAN_MIN_BIT_DIVISOR]; - // // To set the bit timing register, the controller must be - // placed in init mode (if not already), and also configuration - // change bit enabled. The state of the register must be - // saved so it can be restored. - // - ui16CANCTL = HWREG(ui32Base + CAN_O_CTL); - HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT | - CAN_CTL_CCE; + // placed + // in init mode (if not already), and also configuration change + // bit enabled. The state of the register should be saved + // so it can be restored. + + ui16CANCTL = HWREGH(ui32Base + CAN_O_CTL); + HWREGH(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT | + CAN_CTL_CCE; - // // Now add in the pre-scalar on the bit rate. - // - ui32RegValue |= ((ui32PreDivide - 1) & CAN_BIT_BRP_M); + ui32RegValue |= ((ui32PreDivide - 1) & CAN_BTR_BRP_M) | + (((ui32PreDivide - 1) << 10) & CAN_BTR_BRPE_M); - // - // Set the clock bits in the and the lower bits of the + // Set the clock bits in the and the bits of the // pre-scalar. - // - HWREG(ui32Base + CAN_O_BIT) = ui32RegValue; + HWREGH(ui32Base + CAN_O_BTR) = (ui32RegValue & + CAN_REG_WORD_MASK); + HWREGH(ui32Base + CAN_O_BTR + 2) = (ui32RegValue >> 16); - // - // Set the divider upper bits in the extension register. - // - HWREG(ui32Base + CAN_O_BRPE) = ((ui32PreDivide - 1) >> 6) & - CAN_BRPE_BRPE_M; - - // // Restore the saved CAN Control register. - // - HWREG(ui32Base + CAN_O_CTL) = ui16CANCTL; + HWREGH(ui32Base + CAN_O_CTL) = ui16CANCTL; - // // Return the computed bit rate. - // - return(ui32SourceClock / (ui32PreDivide * ui32CANBits)); + return(ui32SourceClock / ( ui32PreDivide * ui32CANBits)); } } - // // Move the divisor up one and look again. Only in rare cases are // more than 2 loops required to find the value. - // ui32DesiredRatio++; } - - // - // A valid combination could not be found, so return 0 to indicate that the - // bit rate was not changed. - // return(0); } @@ -675,113 +635,86 @@ CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, //! Configures the CAN controller bit timing. //! //! \param ui32Base is the base address of the CAN controller. -//! \param psClkParms points to the structure with the clock parameters. +//! \param pClkParms points to the structure with the clock parameters. //! //! Configures the various timing parameters for the CAN bus bit timing: //! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and //! the Synchronization Jump Width. The values for Propagation and Phase //! Buffer 1 segments are derived from the combination -//! \e psClkParms->ui32SyncPropPhase1Seg parameter. Phase Buffer 2 is -//! determined from the \e psClkParms->ui32Phase2Seg parameter. These two -//! parameters, along with \e psClkParms->ui32SJW are based in units of bit -//! time quanta. The actual quantum time is determined by the -//! \e psClkParms->ui32QuantumPrescaler value, which specifies the divisor for -//! the CAN module clock. +//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined +//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along +//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual +//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value, +//! which specifies the divisor for the CAN module clock. //! -//! The total bit time, in quanta, is the sum of the two Seg parameters, +//! The total bit time, in quanta, will be the sum of the two Seg parameters, //! as follows: //! -//! bit_time_q = ui32SyncPropPhase1Seg + ui32Phase2Seg + 1 +//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1 //! -//! Note that the Sync_Seg is always one quantum in duration, and is added +//! Note that the Sync_Seg is always one quantum in duration, and will be added //! to derive the correct duration of Prop_Seg and Phase1_Seg. //! //! The equation to determine the actual bit rate is as follows: //! //! CAN Clock / -//! ((\e ui32SyncPropPhase1Seg + \e ui32Phase2Seg + 1) * -//! (\e ui32QuantumPrescaler)) +//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler)) //! -//! Thus with \e ui32SyncPropPhase1Seg = 4, \e ui32Phase2Seg = 1, -//! \e ui32QuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is +//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1, +//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be //! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. //! //! \return None. // //***************************************************************************** void -CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms) +CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms) { - uint32_t ui32BitReg, ui32SavedInit; + uint32_t uBitReg; + uint16_t uSavedInit; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT(psClkParms); + ASSERT(CANBaseValid(ui32Base)); + ASSERT(pClkParms != 0); - // // The phase 1 segment must be in the range from 2 to 16. - // - ASSERT((psClkParms->ui32SyncPropPhase1Seg >= 2) && - (psClkParms->ui32SyncPropPhase1Seg <= 16)); + ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) && + (pClkParms->uSyncPropPhase1Seg <= 16)); - // // The phase 2 segment must be in the range from 1 to 8. - // - ASSERT((psClkParms->ui32Phase2Seg >= 1) && - (psClkParms->ui32Phase2Seg <= 8)); + ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8)); - // // The synchronous jump windows must be in the range from 1 to 4. - // - ASSERT((psClkParms->ui32SJW >= 1) && (psClkParms->ui32SJW <= 4)); + ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4)); - // // The CAN clock pre-divider must be in the range from 1 to 1024. - // - ASSERT((psClkParms->ui32QuantumPrescaler <= 1024) && - (psClkParms->ui32QuantumPrescaler >= 1)); + ASSERT((pClkParms->uQuantumPrescaler <= 1024) && + (pClkParms->uQuantumPrescaler >= 1)); - // // To set the bit timing register, the controller must be placed in init // mode (if not already), and also configuration change bit enabled. State - // of the init bit must be saved so it can be restored at the end. - // - ui32SavedInit = HWREG(ui32Base + CAN_O_CTL); - HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit | CAN_CTL_INIT | CAN_CTL_CCE; + // of the init bit should be saved so it can be restored at the end. + uSavedInit = HWREGH(ui32Base + CAN_O_CTL); + HWREGH(ui32Base + CAN_O_CTL) = uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE; - // // Set the bit fields of the bit timing register according to the parms. - // - ui32BitReg = (((psClkParms->ui32Phase2Seg - 1) << CAN_BIT_TSEG2_S) & - CAN_BIT_TSEG2_M); - ui32BitReg |= (((psClkParms->ui32SyncPropPhase1Seg - 1) << - CAN_BIT_TSEG1_S) & CAN_BIT_TSEG1_M); - ui32BitReg |= ((psClkParms->ui32SJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M; - ui32BitReg |= (psClkParms->ui32QuantumPrescaler - 1) & CAN_BIT_BRP_M; - HWREG(ui32Base + CAN_O_BIT) = ui32BitReg; + uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BTR_TSEG2_M; + uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BTR_TSEG1_M; + uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BTR_SJW_M; + uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BTR_BRP_M; + uBitReg |= ((pClkParms->uQuantumPrescaler - 1) << 10)& CAN_BTR_BRPE_M; + HWREGH(ui32Base + CAN_O_BTR) = uBitReg & CAN_REG_WORD_MASK; + HWREGH(ui32Base + CAN_O_BTR + 2) = uBitReg >> 16; - // - // Set the divider upper bits in the extension register. - // - HWREG(ui32Base + CAN_O_BRPE) = - ((psClkParms->ui32QuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M; - - // // Clear the config change bit, and restore the init bit. - // - ui32SavedInit &= ~CAN_CTL_CCE; + uSavedInit &= ~CAN_CTL_CCE; - // // If Init was not set before, then clear it. - // - if(ui32SavedInit & CAN_CTL_INIT) + if(uSavedInit & CAN_CTL_INIT) { - ui32SavedInit &= ~CAN_CTL_INIT; + uSavedInit &= ~CAN_CTL_INIT; } - - HWREG(ui32Base + CAN_O_CTL) = ui32SavedInit; + HWREGH(ui32Base + CAN_O_CTL) = uSavedInit; } //***************************************************************************** @@ -789,6 +722,7 @@ CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms) //! Registers an interrupt handler for the CAN controller. //! //! \param ui32Base is the base address of the CAN controller. +//! \param ucIntNumber is the interrupt line to register (0 or 1). //! \param pfnHandler is a pointer to the function to be called when the //! enabled CAN interrupts occur. //! @@ -800,7 +734,7 @@ CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms) //! //! If the application is using a static interrupt vector table stored in //! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() is used to enable CAN interrupts on the +//! Instead, IntEnable() should be used to enable CAN interrupts on the //! interrupt controller. //! //! \sa IntRegister() for important information about registering interrupt @@ -810,40 +744,32 @@ CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms) // //***************************************************************************** void -CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber, + void (*pfnHandler)(void)) { - uint_fast8_t ui8IntNumber; + uint32_t ui32IntNumber; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Get the actual interrupt number for this CAN controller. - // - ui8IntNumber = _CANIntNumberGet(ui32Base); - ASSERT(ui8IntNumber != 0); + ui32IntNumber = CANIntNumberGet(ui32Base, ucIntNumber); - // // Register the interrupt handler. - // - IntRegister(ui8IntNumber, pfnHandler); + IntRegister(ui32IntNumber, pfnHandler); - // - // Enable the Ethernet interrupt. - // - IntEnable(ui8IntNumber); + // Enable the CAN interrupt. + IntEnable(ui32IntNumber); } //***************************************************************************** -// //! Unregisters an interrupt handler for the CAN controller. //! //! \param ui32Base is the base address of the controller. +//! \param ucIntNumber is the interrupt line to un-register (0 or 1). //! //! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. +//! disables the interrupt on the interrupt controller. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -852,30 +778,21 @@ CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) // //***************************************************************************** void -CANIntUnregister(uint32_t ui32Base) +CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber) { - uint_fast8_t ui8IntNumber; + uint32_t ui32IntNumber; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Get the actual interrupt number for this CAN controller. - // - ui8IntNumber = _CANIntNumberGet(ui32Base); - ASSERT(ui8IntNumber != 0); + ui32IntNumber = CANIntNumberGet(ui32Base, ucIntNumber); - // - // Disable the CAN interrupt. - // - IntDisable(ui8IntNumber); - - // // Register the interrupt handler. - // - IntUnregister(ui8IntNumber); + IntUnregister(ui32IntNumber); + + // Disable the CAN interrupt. + IntDisable(ui32IntNumber); } //***************************************************************************** @@ -885,22 +802,26 @@ CANIntUnregister(uint32_t ui32Base) //! \param ui32Base is the base address of the CAN controller. //! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. //! -//! This function enables specific interrupt sources of the CAN controller. -//! Only enabled sources cause a processor interrupt. +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. //! //! The \e ui32IntFlags parameter is the logical OR of any of the following: //! //! - \b CAN_INT_ERROR - a controller error condition has occurred //! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has -//! been detected -//! - \b CAN_INT_MASTER - allow CAN controller to generate interrupts +//! been detected +//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt +//! line 0 +//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt +//! line 1 //! -//! In order to generate any interrupts, \b CAN_INT_MASTER must be enabled. +//! In order to generate status or error interrupts, \b CAN_INT_IE0 must be +//! enabled. //! Further, for any particular transaction from a message object to generate //! an interrupt, that message object must have interrupts enabled (see -//! CANMessageSet()). \b CAN_INT_ERROR generates an interrupt if the +//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the //! controller enters the ``bus off'' condition, or if the error counters reach -//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few +//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few //! status conditions and may provide more interrupts than the application //! needs to handle. When an interrupt occurs, use CANIntStatus() to determine //! the cause. @@ -911,16 +832,17 @@ CANIntUnregister(uint32_t ui32Base) void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0); - // // Enable the specified interrupts. - // - HWREG(ui32Base + CAN_O_CTL) |= ui32IntFlags; + HWREGH(ui32Base + CAN_O_CTL) = (HWREGH(ui32Base + CAN_O_CTL) | + (ui32IntFlags & CAN_REG_WORD_MASK)); + + HWREGH(ui32Base + CAN_O_CTL + 2) = (HWREGH(ui32Base + CAN_O_CTL + 2) | + (ui32IntFlags >> 16)); } //***************************************************************************** @@ -928,8 +850,7 @@ CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) //! Disables individual CAN controller interrupt sources. //! //! \param ui32Base is the base address of the CAN controller. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. //! //! Disables the specified CAN controller interrupt sources. Only enabled //! interrupt sources can cause a processor interrupt. @@ -943,16 +864,17 @@ CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32IntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0); + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0); - // // Disable the specified interrupts. - // - HWREG(ui32Base + CAN_O_CTL) &= ~ui32IntFlags; + HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) & + ~(ui32IntFlags & CAN_REG_WORD_MASK); + + HWREGH(ui32Base + CAN_O_CTL + 2) = HWREGH(ui32Base + CAN_O_CTL + 2) & + ~(ui32IntFlags >> 16); } //***************************************************************************** @@ -962,19 +884,19 @@ CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) //! \param ui32Base is the base address of the CAN controller. //! \param eIntStsReg indicates which interrupt status register to read //! -//! This function returns the value of one of two interrupt status registers. -//! The interrupt status register read is determined by the \e eIntStsReg -//! parameter, which can have one of the following values: +//! Returns the value of one of two interrupt status registers. The interrupt +//! status register read is determined by the \e eIntStsReg parameter, which +//! can have one of the following values: //! //! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt //! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message //! objects //! //! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register -//! and indicates the cause of the interrupt. The value returned is -//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case, -//! the status register is read with the CANStatusGet() function. -//! Calling this function to read the status also clears the status +//! and indicates the cause of the interrupt. It will be a value of +//! \b CAN_INT_INT0ID_STATUS if the cause is a status interrupt. In this case, +//! the status register should be read with the CANStatusGet() function. +//! Calling this function to read the status will also clear the status //! interrupt. If the value of the interrupt register is in the range 1-32, //! then this indicates the number of the highest priority message object that //! has an interrupt pending. The message object interrupt can be cleared by @@ -984,9 +906,9 @@ CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) //! cleared before returning from the interrupt. //! //! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects -//! have pending interrupts. This value can be used to discover all of the -//! pending interrupts at once, as opposed to repeatedly reading the interrupt -//! register by using \b CAN_INT_STS_CAUSE. +//! have pending interrupts. This can be used to discover all of the pending +//! interrupts at once, as opposed to repeatedly reading the interrupt register +//! by using \b CAN_INT_STS_CAUSE. //! //! \return Returns the value of one of the interrupt status registers. // @@ -996,54 +918,37 @@ CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg) { uint32_t ui32Status; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // See which status the caller is looking for. - // switch(eIntStsReg) { - // // The caller wants the global interrupt status for the CAN controller // specified by ui32Base. - // case CAN_INT_STS_CAUSE: { ui32Status = HWREG(ui32Base + CAN_O_INT); break; } - // // The caller wants the current message status interrupt for all // messages. - // case CAN_INT_STS_OBJECT: { - // - // Read and combine both 16 bit values into one 32bit status. - // - ui32Status = (HWREG(ui32Base + CAN_O_MSG1INT) & - CAN_MSG1INT_INTPND_M); - ui32Status |= (HWREG(ui32Base + CAN_O_MSG2INT) << 16); + // Read message object interrupt status + ui32Status = HWREG(ui32Base + CAN_O_IPEN_21); break; } - // // Request was for unknown status so just return 0. - // default: { ui32Status = 0; break; } } - - // // Return the interrupt status value - // return(ui32Status); } @@ -1055,72 +960,51 @@ CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg) //! \param ui32IntClr is a value indicating which interrupt source to clear. //! //! This function can be used to clear a specific interrupt source. The -//! \e ui32IntClr parameter must be one of the following values: +//! \e ui32IntClr parameter should be one of the following values: //! //! - \b CAN_INT_INTID_STATUS - Clears a status interrupt. //! - 1-32 - Clears the specified message object interrupt //! //! It is not necessary to use this function to clear an interrupt. This -//! function is only used if the application wants to clear an interrupt -//! source without taking the normal interrupt action. +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. //! //! Normally, the status interrupt is cleared by reading the controller status //! using CANStatusGet(). A specific message object interrupt is normally //! cleared by reading the message object using CANMessageGet(). //! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! //! \return None. // //***************************************************************************** void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); - ASSERT((ui32IntClr == CAN_INT_INTID_STATUS) || - ((ui32IntClr >= 1) && (ui32IntClr <= 32))); + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntClr == CAN_INT_INT0ID_STATUS) || + ((ui32IntClr>=1) && (ui32IntClr <=32))); - if(ui32IntClr == CAN_INT_INTID_STATUS) + if(ui32IntClr == CAN_INT_INT0ID_STATUS) { - // // Simply read and discard the status to clear the interrupt. - // - HWREG(ui32Base + CAN_O_STS); + HWREG(ui32Base + CAN_O_ES); } else { - // // Wait to be sure that this interface is not busy. - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } - // // Only change the interrupt pending state by setting only the - // CAN_IF1CMSK_CLRINTPND bit. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_CLRINTPND; + // CAN_IF1CMD_CLRINTPND bit. + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = CAN_IF1CMD_CLRINTPND >> 16; - // // Send the clear pending interrupt command to the CAN controller. - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32IntClr & CAN_IF1CRQ_MNUM_M; + HWREGH(ui32Base + CAN_O_IF1CMD) = ui32IntClr & CAN_IF1CMD_MSG_NUM_M; - // // Wait to be sure that this interface is not busy. - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } } @@ -1133,9 +1017,9 @@ CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr) //! \param ui32Base is the base address of the CAN controller. //! \param bAutoRetry enables automatic retransmission. //! -//! This function enables or disables automatic retransmission of messages with -//! detected errors. If \e bAutoRetry is \b true, then automatic -//! retransmission is enabled, otherwise it is disabled. +//! Enables or disables automatic retransmission of messages with detected +//! errors. If \e bAutoRetry is \b true, then automatic retransmission is +//! enabled, otherwise it is disabled. //! //! \return None. // @@ -1143,37 +1027,29 @@ CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr) void CANRetrySet(uint32_t ui32Base, bool bAutoRetry) { - uint32_t ui32CtlReg; + uint16_t ui16CtlReg; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - ui32CtlReg = HWREG(ui32Base + CAN_O_CTL); + ui16CtlReg = HWREGH(ui32Base + CAN_O_CTL); - // // Conditionally set the DAR bit to enable/disable auto-retry. - // if(bAutoRetry) { - // // Clearing the DAR bit tells the controller to not disable the // auto-retry of messages which were not transmitted or received // correctly. - // - ui32CtlReg &= ~CAN_CTL_DAR; + ui16CtlReg &= ~CAN_CTL_DAR; } else { - // // Setting the DAR bit tells the controller to disable the auto-retry // of messages which were not transmitted or received correctly. - // - ui32CtlReg |= CAN_CTL_DAR; + ui16CtlReg |= CAN_CTL_DAR; } - HWREG(ui32Base + CAN_O_CTL) = ui32CtlReg; + HWREGH(ui32Base + CAN_O_CTL) = ui16CtlReg; } //***************************************************************************** @@ -1182,8 +1058,8 @@ CANRetrySet(uint32_t ui32Base, bool bAutoRetry) //! //! \param ui32Base is the base address of the CAN controller. //! -//! This function reads the current setting for automatic retransmission in the -//! CAN controller and returns it to the caller. +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. //! //! \return Returns \b true if automatic retransmission is enabled, \b false //! otherwise. @@ -1192,25 +1068,17 @@ CANRetrySet(uint32_t ui32Base, bool bAutoRetry) bool CANRetryGet(uint32_t ui32Base) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Read the disable automatic retry setting from the CAN controller. - // - if(HWREG(ui32Base + CAN_O_CTL) & CAN_CTL_DAR) + if(HWREGH(ui32Base + CAN_O_CTL) & CAN_CTL_DAR) { - // // Automatic data retransmission is not enabled. - // return(false); } - // // Automatic data retransmission is enabled. - // return(true); } @@ -1221,8 +1089,7 @@ CANRetryGet(uint32_t ui32Base) //! \param ui32Base is the base address of the CAN controller. //! \param eStatusReg is the status register to read. //! -//! This function reads a status register of the CAN controller and returns it -//! to the caller. +//! Reads a status register of the CAN controller and returns it to the caller. //! The different status registers are: //! //! - \b CAN_STS_CONTROL - the main controller status @@ -1231,43 +1098,44 @@ CANRetryGet(uint32_t ui32Base) //! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration //! //! When reading the main controller status register, a pending status -//! interrupt is cleared. This parameter is used in the interrupt -//! handler for the CAN controller if the cause is a status interrupt. The -//! controller status register fields are as follows: +//! interrupt will be cleared. This should be used in the interrupt handler +//! for the CAN controller if the cause is a status interrupt. The controller +//! status register fields are as follows: //! +//! - \b CAN_STATUS_PDA - controller in local power down mode +//! - \b CAN_STATUS_WAKE_UP - controller initiated system wake up +//! - \b CAN_STATUS_PERR - parity error detected //! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition //! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 //! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state //! - \b CAN_STATUS_RXOK - a message was received successfully (independent of -//! any message filtering). +//! any message filtering). //! - \b CAN_STATUS_TXOK - a message was successfully transmitted -//! - \b CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits) //! - \b CAN_STATUS_LEC_NONE - no error //! - \b CAN_STATUS_LEC_STUFF - stuffing error detected //! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part -//! of a message +//! of a message //! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged //! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in -//! recessive mode +//! recessive mode //! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in -//! dominant mode +//! dominant mode //! - \b CAN_STATUS_LEC_CRC - CRC error in received message //! -//! The remaining status registers consist of 32-bit-wide bit maps to the -//! message objects. They can be used to quickly obtain information about the -//! status of all the message objects without needing to query each one. They -//! contain the following information: +//! The remaining status registers are 32-bit bit maps to the message objects. +//! They can be used to quickly obtain information about the status of all the +//! message objects without needing to query each one. They contain the +//! following information: //! -//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a -//! transmission is pending on that object. The application can use this -//! information to determine which objects are still waiting to send a -//! message. -//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new -//! message has been received in that object, and has not yet been picked up -//! by the host application -//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object -//! has a valid configuration programmed. The host application can use this -//! information to determine which message objects are empty/unused. +//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that +//! means that a transmission is pending on that object. The application can +//! use this to determine which objects are still waiting to send a message. +//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means +//! that a new message has been received in that object, and has not yet been +//! picked up by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means +//! it has a valid configuration programmed. The host application can use this +//! to determine which message objects are empty/unused. //! //! \return Returns the value of the status register. // @@ -1277,58 +1145,41 @@ CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg) { uint32_t ui32Status; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); switch(eStatusReg) { - // // Just return the global CAN status register since that is what was // requested. - // case CAN_STS_CONTROL: { - ui32Status = HWREG(ui32Base + CAN_O_STS); - HWREG(ui32Base + CAN_O_STS) = ~(CAN_STS_RXOK | CAN_STS_TXOK | - CAN_STS_LEC_M); + ui32Status = HWREG(ui32Base + CAN_O_ES); break; } - // - // Combine the Transmit status bits into one 32bit value. - // + // Return objects with valid transmit requests case CAN_STS_TXREQUEST: { - ui32Status = HWREG(ui32Base + CAN_O_TXRQ1); - ui32Status |= HWREG(ui32Base + CAN_O_TXRQ2) << 16; + ui32Status = HWREG(ui32Base + CAN_O_TXRQ_21); break; } - // - // Combine the New Data status bits into one 32bit value. - // + // Return messages objects with new data case CAN_STS_NEWDAT: { - ui32Status = HWREG(ui32Base + CAN_O_NWDA1); - ui32Status |= HWREG(ui32Base + CAN_O_NWDA2) << 16; + ui32Status = HWREG(ui32Base + CAN_O_NDAT_21); break; } - // - // Combine the Message valid status bits into one 32bit value. - // + // Return valid message objects case CAN_STS_MSGVAL: { - ui32Status = HWREG(ui32Base + CAN_O_MSG1VAL); - ui32Status |= HWREG(ui32Base + CAN_O_MSG2VAL) << 16; + ui32Status = HWREG(ui32Base + CAN_O_MVAL_21); break; } - // // Unknown CAN status requested so return 0. - // default: { ui32Status = 0; @@ -1346,14 +1197,14 @@ CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg) //! \param pui32RxCount is a pointer to storage for the receive error counter. //! \param pui32TxCount is a pointer to storage for the transmit error counter. //! -//! This function reads the error counter register and returns the transmit and -//! receive error counts to the caller along with a flag indicating if the -//! controller receive counter has reached the error passive limit. The values -//! of the receive and transmit error counters are returned through the -//! pointers provided as parameters. +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. //! -//! After this call, \e *pui32RxCount holds the current receive error count -//! and \e *pui32TxCount holds the current transmit error count. +//! After this call, \e *pui32RxCount will hold the current receive error count +//! and \e *pui32TxCount will hold the current transmit error count. //! //! \return Returns \b true if the receive error count has reached the error //! passive limit, and \b false if the error count is below the error passive @@ -1364,28 +1215,23 @@ bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, uint32_t *pui32TxCount) { - uint32_t ui32CANError; + uint16_t ui16CANError; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); - // // Read the current count of transmit/receive errors. - // - ui32CANError = HWREG(ui32Base + CAN_O_ERR); + ui16CANError = HWREGH(ui32Base + CAN_O_ERRC); - // // Extract the error numbers from the register value. - // - *pui32RxCount = (ui32CANError & CAN_ERR_REC_M) >> CAN_ERR_REC_S; - *pui32TxCount = (ui32CANError & CAN_ERR_TEC_M) >> CAN_ERR_TEC_S; + *pui32RxCount = (ui16CANError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S; + *pui32TxCount = (ui16CANError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S; - if(ui32CANError & CAN_ERR_RP) + if(ui16CANError & CAN_ERRC_RP) { return(true); } + return(false); } @@ -1395,15 +1241,15 @@ CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, //! //! \param ui32Base is the base address of the CAN controller. //! \param ui32ObjID is the object number to configure (1-32). -//! \param psMsgObject is a pointer to a structure containing message object +//! \param pMsgObject is a pointer to a structure containing message object //! settings. //! \param eMsgType indicates the type of message for this object. //! //! This function is used to configure any one of the 32 message objects in the -//! CAN controller. A message object can be configured to be any type of CAN -//! message object as well as to use automatic transmission and reception. -//! This call also allows the message object to be configured to generate -//! interrupts on completion of message receipt or transmission. The +//! CAN controller. A message object can be configured as any type of CAN +//! message object as well as several options for automatic transmission and +//! reception. This call also allows the message object to be configured to +//! generate interrupts on completion of message receipt or transmission. The //! message object can also be configured with a filter/mask so that actions //! are only taken when a message that meets certain parameters is seen on the //! CAN bus. @@ -1415,81 +1261,76 @@ CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, //! - \b MSG_OBJ_TYPE_RX - CAN receive message object. //! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object. //! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then -//! transmit message object. +//! transmit message object. //! -//! The message object pointed to by \e psMsgObject must be populated by the +//! The message object pointed to by \e pMsgObject must be populated by the //! caller, as follows: //! //! - \e ui32MsgID - contains the message ID, either 11 or 29 bits. //! - \e ui32MsgIDMask - mask of bits from \e ui32MsgID that must match if -//! identifier filtering is enabled. +//! identifier filtering is enabled. //! - \e ui32Flags //! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission. //! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. //! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the -//! identifier mask specified by \e ui32MsgIDMask. -//! - \e ui32MsgLen - the number of bytes in the message data. This parameter -//! must be non-zero even for a remote frame; it must match the expected -//! bytes of data in the responding data frame. -//! - \e pui8MsgData - points to a buffer containing up to 8 bytes of data for -//! a data frame. +//! identifier mask specified by \e ui32MsgIDMask. +//! - \e ui32MsgLen - the number of bytes in the message data. This should be +//! non-zero even for a remote frame; it should match the expected bytes of the +//! data responding data frame. +//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a +//! data frame. //! -//! \b Example: To send a data frame or remote frame (in response to a remote +//! \b Example: To send a data frame or remote frame(in response to a remote //! request), take the following steps: //! //! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. -//! -# Set \e psMsgObject->ui32MsgID to the message ID. -//! -# Set \e psMsgObject->ui32Flags. Make sure to set -//! \b MSG_OBJ_TX_INT_ENABLE to allow an interrupt to be generated when the -//! message is sent. -//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the data frame. -//! -# Set \e psMsgObject->pui8MsgData to point to an array containing the -//! bytes to send in the message. -//! -# Call this function with \e ui32ObjID set to one of the 32 object -//! buffers. +//! -# Set \e pMsgObject->ui32MsgID to the message ID. +//! -# Set \e pMsgObject->ui32Flags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to +//! allow an interrupt to be generated when the message is sent. +//! -# Set \e pMsgObject->ui32MsgLen to the number of bytes in the data frame. +//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes +//! to send in the message. +//! -# Call this function with \e ui32ObjID set to one of the 32 object buffers. //! //! \b Example: To receive a specific data frame, take the following steps: //! //! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX. -//! -# Set \e psMsgObject->ui32MsgID to the full message ID, or a partial mask -//! to use partial ID matching. -//! -# Set \e psMsgObject->ui32MsgIDMask bits that are used for masking -//! during comparison. -//! -# Set \e psMsgObject->ui32Flags as follows: -//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data -//! frame is received. -//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based -//! filtering. -//! -# Set \e psMsgObject->ui32MsgLen to the number of bytes in the expected -//! data frame. -//! -# The buffer pointed to by \e psMsgObject->pui8MsgData is not used by this -//! call as no data is present at the time of the call. -//! -# Call this function with \e ui32ObjID set to one of the 32 object -//! buffers. +//! -# Set \e pMsgObject->ui32MsgID to the full message ID, or a partial mask to +//! use partial ID matching. +//! -# Set \e pMsgObject->ui32MsgIDMask bits that should be used for masking +//! during comparison. +//! -# Set \e pMsgObject->ui32Flags as follows: +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame +//! is received. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering. +//! -# Set \e pMsgObject->ui32MsgLen to the number of bytes in the expected data +//! frame. +//! -# The buffer pointed to by \e pMsgObject->pucMsgData and +//! \e pMsgObject->ui32MsgLen are not used by this call as no data is present at +//! the time of the call. +//! -# Call this function with \e ui32ObjID set to one of the 32 object buffers. //! //! If you specify a message object buffer that already contains a message -//! definition, it is overwritten. +//! definition, it will be overwritten. //! //! \return None. // //***************************************************************************** void -CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, tMsgObjType eMsgType) +CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject *pMsgObject, + tMsgObjType eMsgType) { - uint16_t ui16CmdMaskReg; - uint16_t ui16MaskReg0, ui16MaskReg1; - uint16_t ui16ArbReg0, ui16ArbReg1; - uint16_t ui16MsgCtrl; + uint32_t ui32CmdMaskReg; + uint32_t ui32MaskReg; + uint32_t ui32ArbReg; + uint32_t ui32MsgCtrl; bool bTransferData; bool bUseExtendedID; bTransferData = 0; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); ASSERT((eMsgType == MSG_OBJ_TYPE_TX) || (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || @@ -1498,18 +1339,14 @@ CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE)); - // // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } - // // See if we need to use an extended identifier or not. - // - if((psMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) || - (psMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID)) + if((pMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) || + (pMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID)) { bUseExtendedID = 1; } @@ -1518,284 +1355,199 @@ CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, bUseExtendedID = 0; } - // // This is always a write to the Message object as this call is setting a - // message object. This call always sets all size bits so it sets - // both data bits. The call uses the CONTROL register to set control + // message object. This call will also always set all size bits so it sets + // both data bits. The call will use the CONTROL register to set control // bits so this bit needs to be set as well. - // - ui16CmdMaskReg = (CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_DATAA | - CAN_IF1CMSK_DATAB | CAN_IF1CMSK_CONTROL); + ui32CmdMaskReg = (CAN_IF1CMD_DIR | CAN_IF1CMD_DATA_A | CAN_IF1CMD_DATA_B | + CAN_IF1CMD_CONTROL); - // // Initialize the values to a known state before filling them in based on // the type of message object that is being configured. - // - ui16ArbReg0 = 0; - ui16ArbReg1 = 0; - ui16MsgCtrl = 0; - ui16MaskReg0 = 0; - ui16MaskReg1 = 0; + ui32ArbReg = 0; + ui32MsgCtrl = 0; + ui32MaskReg = 0; switch(eMsgType) { - // - // Transmit message object. - // - case MSG_OBJ_TYPE_TX: - { - // - // Set the TXRQST bit and the reset the rest of the register. - // - ui16MsgCtrl |= CAN_IF1MCTL_TXRQST; - ui16ArbReg1 = CAN_IF1ARB2_DIR; - bTransferData = 1; - break; - } - - // - // Transmit remote request message object - // - case MSG_OBJ_TYPE_TX_REMOTE: - { - // - // Set the TXRQST bit and the reset the rest of the register. - // - ui16MsgCtrl |= CAN_IF1MCTL_TXRQST; - ui16ArbReg1 = 0; - break; - } - - // - // Receive message object. - // - case MSG_OBJ_TYPE_RX: - { - // - // This clears the DIR bit along with everything else. The TXRQST - // bit was cleared by defaulting ui16MsgCtrl to 0. - // - ui16ArbReg1 = 0; - break; - } - - // - // Receive remote request message object. - // - case MSG_OBJ_TYPE_RX_REMOTE: - { - // - // The DIR bit is set to one for remote receivers. The TXRQST bit - // was cleared by defaulting ui16MsgCtrl to 0. - // - ui16ArbReg1 = CAN_IF1ARB2_DIR; - - // - // Set this object so that it only indicates that a remote frame - // was received and allow for software to handle it by sending back - // a data frame. - // - ui16MsgCtrl = CAN_IF1MCTL_UMASK; - - // - // Use the full Identifier by default. - // - ui16MaskReg0 = 0xffff; - ui16MaskReg1 = 0x1fff; - - // - // Make sure to send the mask to the message object. - // - ui16CmdMaskReg |= CAN_IF1CMSK_MASK; - break; - } - - // - // Remote frame receive remote, with auto-transmit message object. - // - case MSG_OBJ_TYPE_RXTX_REMOTE: - { - // - // Oddly the DIR bit is set to one for remote receivers. - // - ui16ArbReg1 = CAN_IF1ARB2_DIR; - - // - // Set this object to auto answer if a matching identifier is seen. - // - ui16MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; - - // - // The data to be returned needs to be filled in. - // - bTransferData = 1; - break; - } - - // - // This case never happens due to the ASSERT statement at the - // beginning of this function. - // - default: - { - return; - } + // Transmit message object. + case MSG_OBJ_TYPE_TX: + { + // Set the TXRQST bit and the reset the rest of the register. + ui32MsgCtrl |= CAN_IF1MCTL_TXRQST; + ui32ArbReg = CAN_IF1ARB_DIR; + bTransferData = 1; + break; + } + + // Transmit remote request message object + case MSG_OBJ_TYPE_TX_REMOTE: + { + // Set the TXRQST bit and the reset the rest of the register. + ui32MsgCtrl |= CAN_IF1MCTL_TXRQST; + ui32ArbReg = 0; + break; + } + + // Receive message object. + case MSG_OBJ_TYPE_RX: + { + // This clears the DIR bit along with everything else. The TXRQST + // bit was cleared by defaulting ui32MsgCtrl to 0. + ui32ArbReg = 0; + break; + } + + // Receive remote request message object. + case MSG_OBJ_TYPE_RX_REMOTE: + { + // The DIR bit is set to one for remote receivers. The TXRQST bit + // was cleared by defaulting ui32MsgCtrl to 0. + ui32ArbReg = CAN_IF1ARB_DIR; + + // Set this object so that it only indicates that a remote frame + // was received and allow for software to handle it by sending back + // a data frame. + ui32MsgCtrl = CAN_IF1MCTL_UMASK; + + // Use the full Identifier by default. + ui32MaskReg = CAN_IF1MSK_MSK_M; + + // Make sure to send the mask to the message object. + ui32CmdMaskReg |= CAN_IF1CMD_MASK; + break; + } + + // Remote frame receive remote, with auto-transmit message object. + case MSG_OBJ_TYPE_RXTX_REMOTE: + { + // Oddly the DIR bit is set to one for remote receivers. + ui32ArbReg = CAN_IF1ARB_DIR; + + // Set this object to auto answer if a matching identifier is seen. + ui32MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; + + // The data to be returned needs to be filled in. + bTransferData = 1; + break; + } + + // This case should never happen due to the ASSERT statement at the + // beginning of this function. + default: + { + return; + } } - // // Configure the Mask Registers. - // - if(psMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER) + if(pMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER) { if(bUseExtendedID) { - // // Set the 29 bits of Identifier mask that were requested. - // - ui16MaskReg0 = psMsgObject->ui32MsgIDMask & CAN_IF1MSK1_IDMSK_M; - ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask >> 16) & - CAN_IF1MSK2_IDMSK_M); + ui32MaskReg = pMsgObject->ui32MsgIDMask & CAN_IF1MSK_MSK_M; } else { - // - // Lower 16 bit are unused so set them to zero. - // - ui16MaskReg0 = 0; - // // Put the 11 bit Mask Identifier into the upper bits of the field // in the register. - // - ui16MaskReg1 = ((psMsgObject->ui32MsgIDMask << 2) & - CAN_IF1MSK2_IDMSK_M); + ui32MaskReg = ((pMsgObject->ui32MsgIDMask << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M); } } - // // If the caller wants to filter on the extended ID bit then set it. - // - if((psMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) == + if((pMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) == MSG_OBJ_USE_EXT_FILTER) { - ui16MaskReg1 |= CAN_IF1MSK2_MXTD; + ui32MaskReg |= CAN_IF1MSK_MXTD; } - // // The caller wants to filter on the message direction field. - // - if((psMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) == + if((pMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) == MSG_OBJ_USE_DIR_FILTER) { - ui16MaskReg1 |= CAN_IF1MSK2_MDIR; + ui32MaskReg |= CAN_IF1MSK_MDIR; } - if(psMsgObject->ui32Flags & - (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | - MSG_OBJ_USE_EXT_FILTER)) + if(pMsgObject->ui32Flags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | + MSG_OBJ_USE_EXT_FILTER)) { - // // Set the UMASK bit to enable using the mask register. - // - ui16MsgCtrl |= CAN_IF1MCTL_UMASK; + ui32MsgCtrl |= CAN_IF1MCTL_UMASK; - // // Set the MASK bit so that this gets transferred to the Message // Object. - // - ui16CmdMaskReg |= CAN_IF1CMSK_MASK; + ui32CmdMaskReg |= CAN_IF1CMD_MASK; } - // // Set the Arb bit so that this gets transferred to the Message object. - // - ui16CmdMaskReg |= CAN_IF1CMSK_ARB; + ui32CmdMaskReg |= CAN_IF1CMD_ARB; - // // Configure the Arbitration registers. - // if(bUseExtendedID) { - // // Set the 29 bit version of the Identifier for this message object. - // - ui16ArbReg0 |= psMsgObject->ui32MsgID & CAN_IF1ARB1_ID_M; - ui16ArbReg1 |= (psMsgObject->ui32MsgID >> 16) & CAN_IF1ARB2_ID_M; - - // // Mark the message as valid and set the extended ID bit. - // - ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD; + ui32ArbReg |= (pMsgObject->ui32MsgID & CAN_IF1ARB_ID_M) | + CAN_IF1ARB_MSGVAL | CAN_IF1ARB_XTD; } else { - // // Set the 11 bit version of the Identifier for this message object. // The lower 18 bits are set to zero. - // - ui16ArbReg1 |= (psMsgObject->ui32MsgID << 2) & CAN_IF1ARB2_ID_M; - - // // Mark the message as valid. - // - ui16ArbReg1 |= CAN_IF1ARB2_MSGVAL; + ui32ArbReg |= ((pMsgObject->ui32MsgID << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M) | CAN_IF1ARB_MSGVAL; } - // // Set the data length since this is set for all transfers. This is also a // single transfer and not a FIFO transfer so set EOB bit. - // - ui16MsgCtrl |= (psMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M); + ui32MsgCtrl |= (pMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M); - // // Mark this as the last entry if this is not the last entry in a FIFO. - // - if((psMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0) + if((pMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0) { - ui16MsgCtrl |= CAN_IF1MCTL_EOB; + ui32MsgCtrl |= CAN_IF1MCTL_EOB; } - // // Enable transmit interrupts if they should be enabled. - // - if(psMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE) + if(pMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE) { - ui16MsgCtrl |= CAN_IF1MCTL_TXIE; + ui32MsgCtrl |= CAN_IF1MCTL_TXIE; } - // // Enable receive interrupts if they should be enabled. - // - if(psMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE) + if(pMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE) { - ui16MsgCtrl |= CAN_IF1MCTL_RXIE; + ui32MsgCtrl |= CAN_IF1MCTL_RXIE; } - // // Write the data out to the CAN Data registers if needed. - // if(bTransferData) { - _CANDataRegWrite(psMsgObject->pui8MsgData, - (uint32_t *)(ui32Base + CAN_O_IF1DA1), - psMsgObject->ui32MsgLen); + CANDataRegWrite(pMsgObject->pucMsgData, + (uint32_t *)(ui32Base + CAN_O_IF1DATA), + pMsgObject->ui32MsgLen); } - // // Write out the registers to program the message object. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = ui16CmdMaskReg; - HWREG(ui32Base + CAN_O_IF1MSK1) = ui16MaskReg0; - HWREG(ui32Base + CAN_O_IF1MSK2) = ui16MaskReg1; - HWREG(ui32Base + CAN_O_IF1ARB1) = ui16ArbReg0; - HWREG(ui32Base + CAN_O_IF1ARB2) = ui16ArbReg1; - HWREG(ui32Base + CAN_O_IF1MCTL) = ui16MsgCtrl; + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = ui32CmdMaskReg >> 16; - // - // Transfer the message object to the message object specified by - // ui32ObjID. - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; + HWREGH(ui32Base + CAN_O_IF1MSK) = ui32MaskReg & CAN_REG_WORD_MASK; + HWREGH(ui32Base + CAN_O_IF1MSK + 2) = ui32MaskReg >> 16; + + HWREGH(ui32Base + CAN_O_IF1ARB) = ui32ArbReg & CAN_REG_WORD_MASK; + HWREGH(ui32Base + CAN_O_IF1ARB + 2) = ui32ArbReg >> 16; + + HWREGH(ui32Base + CAN_O_IF1MCTL) = ui32MsgCtrl & CAN_REG_WORD_MASK; + + // Transfer the message object to the message object specific by ui32ObjID. + HWREGH(ui32Base + CAN_O_IF1CMD) = ui32ObjID & CAN_IF1CMD_MSG_NUM_M; + + return; } //***************************************************************************** @@ -1804,264 +1556,198 @@ CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, //! //! \param ui32Base is the base address of the CAN controller. //! \param ui32ObjID is the object number to read (1-32). -//! \param psMsgObject points to a structure containing message object fields. +//! \param pMsgObject points to a structure containing message object fields. //! \param bClrPendingInt indicates whether an associated interrupt should be //! cleared. //! //! This function is used to read the contents of one of the 32 message objects -//! in the CAN controller and return it to the caller. The data returned is +//! in the CAN controller, and return it to the caller. The data returned is //! stored in the fields of the caller-supplied structure pointed to by -//! \e psMsgObject. The data consists of all of the parts of a CAN message, +//! \e pMsgObject. The data consists of all of the parts of a CAN message, //! plus some control and status information. //! -//! Normally, this function is used to read a message object that has received -//! and stored a CAN message with a certain identifier. However, this function -//! could also be used to read the contents of a message object in order to -//! load the fields of the structure in case only part of the structure must -//! be changed from a previous setting. +//! Normally this is used to read a message object that has received and stored +//! a CAN message with a certain identifier. However, this could also be used +//! to read the contents of a message object in order to load the fields of the +//! structure in case only part of the structure needs to be changed from a +//! previous setting. //! -//! When using CANMessageGet(), all of the same fields of the structure are +//! When using CANMessageGet, all of the same fields of the structure are //! populated in the same way as when the CANMessageSet() function is used, //! with the following exceptions: //! -//! \e psMsgObject->ui32Flags: +//! \e pMsgObject->ui32Flags: //! -//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it -//! was read +//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it +//! was read //! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on -//! this message object and not read by the host before being overwritten. +//! this message object, and not read by the host before being overwritten. //! //! \return None. // //***************************************************************************** void -CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, - tCANMsgObject *psMsgObject, bool bClrPendingInt) +CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject *pMsgObject, + bool bClrPendingInt) { - uint16_t ui16CmdMaskReg; - uint16_t ui16MaskReg0, ui16MaskReg1; - uint16_t ui16ArbReg0, ui16ArbReg1; - uint16_t ui16MsgCtrl; + uint32_t ui32CmdMaskReg; + uint32_t ui32MaskReg; + uint32_t ui32ArbReg; + uint32_t ui32MsgCtrl; - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); - // // This is always a read to the Message object as this call is setting a // message object. - // - ui16CmdMaskReg = (CAN_IF1CMSK_DATAA | CAN_IF1CMSK_DATAB | - CAN_IF1CMSK_CONTROL | CAN_IF1CMSK_MASK | - CAN_IF1CMSK_ARB); + ui32CmdMaskReg = (CAN_IF2CMD_DATA_A | CAN_IF2CMD_DATA_B | + CAN_IF2CMD_CONTROL | CAN_IF2CMD_MASK | CAN_IF2CMD_ARB); - // // Clear a pending interrupt and new data in a message object. - // if(bClrPendingInt) { - ui16CmdMaskReg |= CAN_IF1CMSK_CLRINTPND; + ui32CmdMaskReg |= CAN_IF2CMD_CLRINTPND | CAN_IF2CMD_TXRQST; } - // // Set up the request for data from the message object. - // - HWREG(ui32Base + CAN_O_IF2CMSK) = ui16CmdMaskReg; + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = ui32CmdMaskReg >> 16; - // - // Transfer the message object to the message object specified by - // ui32ObjID. - // - HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; + // Transfer the message object to the message object specified by ui32ObjID. + HWREGH(ui32Base + CAN_O_IF2CMD) = ui32ObjID & CAN_IF2CMD_MSG_NUM_M; - // // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) { } - // // Read out the IF Registers. - // - ui16MaskReg0 = HWREG(ui32Base + CAN_O_IF2MSK1); - ui16MaskReg1 = HWREG(ui32Base + CAN_O_IF2MSK2); - ui16ArbReg0 = HWREG(ui32Base + CAN_O_IF2ARB1); - ui16ArbReg1 = HWREG(ui32Base + CAN_O_IF2ARB2); - ui16MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL); + ui32MaskReg = HWREG(ui32Base + CAN_O_IF2MSK); + ui32ArbReg = HWREG(ui32Base + CAN_O_IF2ARB); + ui32MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL); + pMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS; - psMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS; - - // // Determine if this is a remote frame by checking the TXRQST and DIR bits. - // - if((!(ui16MsgCtrl & CAN_IF1MCTL_TXRQST) && - (ui16ArbReg1 & CAN_IF1ARB2_DIR)) || - ((ui16MsgCtrl & CAN_IF1MCTL_TXRQST) && - (!(ui16ArbReg1 & CAN_IF1ARB2_DIR)))) + if((!(ui32MsgCtrl & CAN_IF2MCTL_TXRQST) && (ui32ArbReg & CAN_IF2ARB_DIR)) || + ((ui32MsgCtrl & CAN_IF2MCTL_TXRQST) && (!(ui32ArbReg & CAN_IF2ARB_DIR)))) { - psMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME; + pMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME; } - // // Get the identifier out of the register, the format depends on size of // the mask. - // - if(ui16ArbReg1 & CAN_IF1ARB2_XTD) + if(ui32ArbReg & CAN_IF2ARB_XTD) { - // // Set the 29 bit version of the Identifier for this message object. - // - psMsgObject->ui32MsgID = (((ui16ArbReg1 & CAN_IF1ARB2_ID_M) << 16) | - ui16ArbReg0); + pMsgObject->ui32MsgID = ui32ArbReg & CAN_IF2ARB_ID_M; - psMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID; + pMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID; } else { - // // The Identifier is an 11 bit value. - // - psMsgObject->ui32MsgID = (ui16ArbReg1 & CAN_IF1ARB2_ID_M) >> 2; + pMsgObject->ui32MsgID = (ui32ArbReg & + CAN_IF2ARB_STD_ID_M) >> CAN_IF2ARB_STD_ID_S; } - // // Indicate that we lost some data. - // - if(ui16MsgCtrl & CAN_IF1MCTL_MSGLST) + if(ui32MsgCtrl & CAN_IF2MCTL_MSGLST) { - psMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST; + pMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST; } - // // Set the flag to indicate if ID masking was used. - // - if(ui16MsgCtrl & CAN_IF1MCTL_UMASK) + if(ui32MsgCtrl & CAN_IF2MCTL_UMASK) { - if(ui16ArbReg1 & CAN_IF1ARB2_XTD) + if(ui32ArbReg & CAN_IF2ARB_XTD) { - // // The Identifier Mask is assumed to also be a 29 bit value. - // - psMsgObject->ui32MsgIDMask = - ((ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | ui16MaskReg0; + pMsgObject->ui32MsgIDMask = (ui32MaskReg & CAN_IF2MSK_MSK_M); - // // If this is a fully specified Mask and a remote frame then don't // set the MSG_OBJ_USE_ID_FILTER because the ID was not really // filtered. - // - if((psMsgObject->ui32MsgIDMask != 0x1fffffff) || - ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) + if((pMsgObject->ui32MsgIDMask != 0x1fffffff) || + ((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) { - psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; + pMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; } } else { - // // The Identifier Mask is assumed to also be an 11 bit value. - // - psMsgObject->ui32MsgIDMask = - (ui16MaskReg1 & CAN_IF1MSK2_IDMSK_M) >> 2; + pMsgObject->ui32MsgIDMask = ((ui32MaskReg & CAN_IF2MSK_MSK_M) >> + 18); - // // If this is a fully specified Mask and a remote frame then don't // set the MSG_OBJ_USE_ID_FILTER because the ID was not really // filtered. - // - if((psMsgObject->ui32MsgIDMask != 0x7ff) || - ((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) + if((pMsgObject->ui32MsgIDMask != 0x7ff) || + ((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) { - psMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; + pMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; } } - // // Indicate if the extended bit was used in filtering. - // - if(ui16MaskReg1 & CAN_IF1MSK2_MXTD) + if(ui32MaskReg & CAN_IF2MSK_MXTD) { - psMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER; + pMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER; } - // // Indicate if direction filtering was enabled. - // - if(ui16MaskReg1 & CAN_IF1MSK2_MDIR) + if(ui32MaskReg & CAN_IF2MSK_MDIR) { - psMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER; + pMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER; } } - // // Set the interrupt flags. - // - if(ui16MsgCtrl & CAN_IF1MCTL_TXIE) + if(ui32MsgCtrl & CAN_IF2MCTL_TXIE) { - psMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE; + pMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE; } - if(ui16MsgCtrl & CAN_IF1MCTL_RXIE) + if(ui32MsgCtrl & CAN_IF2MCTL_RXIE) { - psMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE; + pMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE; } - // // See if there is new data available. - // - if(ui16MsgCtrl & CAN_IF1MCTL_NEWDAT) + if(ui32MsgCtrl & CAN_IF2MCTL_NEWDAT) { - // // Get the amount of data needed to be read. - // - psMsgObject->ui32MsgLen = (ui16MsgCtrl & CAN_IF1MCTL_DLC_M); + pMsgObject->ui32MsgLen = (ui32MsgCtrl & CAN_IF2MCTL_DLC_M); - // // Don't read any data for a remote frame, there is nothing valid in // that buffer anyway. - // - if((psMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0) + if((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0) { - // // Read out the data from the CAN registers. - // - _CANDataRegRead(psMsgObject->pui8MsgData, - (uint32_t *)(ui32Base + CAN_O_IF2DA1), - psMsgObject->ui32MsgLen); + CANDataRegRead(pMsgObject->pucMsgData, + (uint32_t *)(ui32Base + CAN_O_IF2DATA), + pMsgObject->ui32MsgLen); } - // // Now clear out the new data flag. - // - HWREG(ui32Base + CAN_O_IF2CMSK) = CAN_IF1CMSK_NEWDAT; + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = CAN_IF2CMD_TXRQST >> 16; - // // Transfer the message object to the message object specified by // ui32ObjID. - // - HWREG(ui32Base + CAN_O_IF2CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; + HWREGH(ui32Base + CAN_O_IF2CMD) = ui32ObjID & CAN_IF2CMD_MSG_NUM_M; - // // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF2CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) { } - // // Indicate that there is new data in this message. - // - psMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA; + pMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA; } else { - // // Along with the MSG_OBJ_NEW_DATA not being set the amount of data // needs to be set to zero if none was available. - // - psMsgObject->ui32MsgLen = 0; + pMsgObject->ui32MsgLen = 0; } } @@ -2073,8 +1759,8 @@ CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, //! \param ui32ObjID is the message object number to disable (1-32). //! //! This function frees the specified message object from use. Once a message -//! object has been ``cleared,'' it no longer automatically sends or receives -//! messages, nor does it generate interrupts. +//! object has been ``cleared,'' it will no longer automatically send or +//! receive messages, or generate interrupts. //! //! \return None. // @@ -2082,36 +1768,152 @@ CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID) { - // // Check the arguments. - // - ASSERT(_CANBaseValid(ui32Base)); + ASSERT(CANBaseValid(ui32Base)); ASSERT((ui32ObjID >= 1) && (ui32ObjID <= 32)); - // // Wait for busy bit to clear - // - while(HWREG(ui32Base + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY) + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) { } - // - // Clear the message value bit in the arbitration register. This indicates + // Clear the message value bit in the arbitration register. This indicates // the message is not valid. - // - HWREG(ui32Base + CAN_O_IF1CMSK) = CAN_IF1CMSK_WRNRD | CAN_IF1CMSK_ARB; - HWREG(ui32Base + CAN_O_IF1ARB1) = 0; - HWREG(ui32Base + CAN_O_IF1ARB2) = 0; + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_DIR | + CAN_IF1CMD_ARB) >> 16; + HWREGH(ui32Base + CAN_O_IF1ARB) = 0; + HWREGH(ui32Base + CAN_O_IF1ARB + 2) = 0; - // // Initiate programming the message object - // - HWREG(ui32Base + CAN_O_IF1CRQ) = ui32ObjID & CAN_IF1CRQ_MNUM_M; + HWREGH(ui32Base + CAN_O_IF1CMD) = ui32ObjID & CAN_IF1CMD_MSG_NUM_M; } //***************************************************************************** // -// Close the Doxygen group. -//! @} +//! CAN Global interrupt Enable function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific CAN interrupt in the global interrupt enable register +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt Enable bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt Enable bit for CAN INT1 +//! +//! \return None. // //***************************************************************************** +void +CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //enable the requested interrupts + HWREGH(ui32Base + CAN_O_GLB_INT_EN) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Disable function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Disables the specific CAN interrupt in the global interrupt enable register +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +void +CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //disable the requested interrupts + HWREGH(ui32Base + CAN_O_GLB_INT_EN) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Clear function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Clear the specific CAN interrupt bit in the global interrupt flag register. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +void +CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //clear the requested interrupts + HWREGH(ui32Base + CAN_O_GLB_INT_CLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Status function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be checked. +//! +//! Get the status of the specific CAN interrupt bits in the global interrupt +//! flag register. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt bit for CAN INT1 +//! +//! \return True if any of the requested interrupt bit(s) is (are) set. +// +//***************************************************************************** +bool +CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //enable the requested interrupts + if(HWREGH(ui32Base + CAN_O_GLB_INT_FLG) & ui32IntFlags) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h new file mode 100644 index 0000000000..471d1fcc6d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h @@ -0,0 +1,415 @@ +//########################################################################### +// +// FILE: can.h +// +// TITLE: Defines and Macros for the CAN controller. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __CAN_H__ +#define __CAN_H__ + +//***************************************************************************** +//! \addtogroup can_api +//! @{ +//***************************************************************************** + +//***************************************************************************** +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + +#define CAN_INDEX_TO_BASE(idx) ((idx == 0) ? CAN_A_BASE : CAN_B_BASE) + +#define CAN_INDEX_TO_MSG_RAM_BASE(idx) ((idx == 0) ? CAN_A_MSG_RAM : CAN_B_MSG_RAM) + +#define CAN_REG_WORD_MASK (0xFFFFU) + +//**************************************************************************** +// These are the Defines to select CAN pin muxing when calling the functions +// ConfigCanPinMuxing(), ConfigGpioCanA() & ConfigGpioCanB() in F2837x_Can.c +//**************************************************************************** +#define CAN_A_GPIO4_GPIO5 1 //switch case 1 +#define CAN_A_GPIO19_GPIO18 2 //switch case 2 +#define CAN_A_GPIO31_GPIO30 3 //switch case 3 +#define CAN_A_GPIO37_GPIO36 4 //switch case 4 +#define CAN_A_GPIO63_GPIO62 5 //switch case 5 +#define CAN_A_GPIO71_GPIO70 6 //switch case 6 + +#define CAN_B_GPIO6_GPIO7 1 //switch case 1 +#define CAN_B_GPIO8_GPIO10 2 //switch case 2 +#define CAN_B_GPIO12_GPIO13 3 //switch case 3 +#define CAN_B_GPIO16_GPIO17 4 //switch case 4 +#define CAN_B_GPIO20_GPIO21 5 //switch case 5 +#define CAN_B_GPIO38_GPIO39 6 //switch case 6 +#define CAN_B_GPIO72_GPIO73 7 //switch case 7 + +//***************************************************************************** +// Miscellaneous defines for Message ID Types +//***************************************************************************** + +//***************************************************************************** +// These are the flags used by the tCANMsgObject.ui32Flags value when calling the +// CANMessageSet() and CANMessageGet() functions. +//***************************************************************************** + +//! This definition is used with the tCANMsgObject ui32Flags value and indicates +//! that transmit interrupts should be enabled, or are enabled. +#define MSG_OBJ_TX_INT_ENABLE 0x00000001 + +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +#define MSG_OBJ_RX_INT_ENABLE 0x00000002 + +//! This indicates that a message object will use or is using an extended +//! identifier. +#define MSG_OBJ_EXTENDED_ID 0x00000004 + +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +#define MSG_OBJ_USE_ID_FILTER 0x00000008 + +//! This indicates that new data was available in the message object. +#define MSG_OBJ_NEW_DATA 0x00000080 + +//! This indicates that data was lost since this message object was last +//! read. +#define MSG_OBJ_DATA_LOST 0x00000100 + +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. If the direction filtering is +//! used, then ID filtering must also be enabled. +#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER) + +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. If the extended +//! identifier filtering is used, then ID filtering must also be enabled. +#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER) + +//! This indicates that a message object is a remote frame. +#define MSG_OBJ_REMOTE_FRAME 0x00000040 + +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +#define MSG_OBJ_FIFO 0x00000200 + +//! This indicates that a message object has no flags set. +#define MSG_OBJ_NO_FLAGS 0x00000000 + +//***************************************************************************** +//! This define is used with the flag values to allow checking only status +//! flags and not configuration flags. +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +//! The structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +//***************************************************************************** +typedef struct +{ + //! The CAN message identifier used for 11 or 29 bit identifiers. + uint32_t ui32MsgID; + + //! The message identifier mask used when identifier filtering is enabled. + uint32_t ui32MsgIDMask; + + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + uint32_t ui32Flags; + + //! This value is the number of bytes of data in the message object. + uint32_t ui32MsgLen; + + //! This is a pointer to the message object's data. + unsigned char *pucMsgData; +} +tCANMsgObject; + +//***************************************************************************** +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +//***************************************************************************** +typedef struct +{ + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + uint16_t uSyncPropPhase1Seg; + + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + uint16_t uPhase2Seg; + + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + uint16_t uSJW; + + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + uint16_t uQuantumPrescaler; +} +tCANBitClkParms; + +//***************************************************************************** +//! This data type is used to identify the interrupt status register. This is +//! used when calling the CANIntStatus() function. +//***************************************************************************** +typedef enum +{ + //! Read the CAN interrupt status information. + CAN_INT_STS_CAUSE, + + //! Read a message object's interrupt status. + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +//! This data type is used to identify which of several status registers to +//! read when calling the CANStatusGet() function. +//***************************************************************************** +typedef enum +{ + //! Read the full CAN controller status. + CAN_STS_CONTROL, + + //! Read the full 32-bit mask of message objects with a transmit request + //! set. + CAN_STS_TXREQUEST, + + //! Read the full 32-bit mask of message objects with new data available. + CAN_STS_NEWDAT, + + //! Read the full 32-bit mask of message objects that are enabled. + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// These definitions are used to specify interrupt sources to CANIntEnable() +// and CANIntDisable(). +//***************************************************************************** +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +#define CAN_INT_ERROR 0x00000008 + +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +#define CAN_INT_STATUS 0x00000004 + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 0 +#define CAN_INT_IE0 0x00000002 + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 1 +#define CAN_INT_IE1 0x00020000 + +// Defined to maintain compatibility with Stellaris Examples +#define CAN_INT_MASTER CAN_INT_IE0 + +//***************************************************************************** +// These definitions are used to specify the clock source to +// CANClkSourceSelect() +//***************************************************************************** +//! This flag is used to clock the CAN controller Selected CPU SYSCLKOUT +//! (CPU1.Sysclk or CPU2.Sysclk). +#define CAN_CLK_CPU_SYSCLKOUT 0 // PERx.SYSCLK (default on reset) + +//! This flag is used to clock the CAN controller with the X1/X2 oscillator +//! clock. +#define CAN_CLK_EXT_OSC 1 // External Oscillator (XTAL) + +//! This flag is used to clock the CAN controller with the clock from +//! AUXCLKIN (from GPIO) +#define CAN_CLK_AUXCLKIN 2 // AUXCLKIN (from GPIO) + + +//***************************************************************************** +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CANMessageSet() API. +//***************************************************************************** +typedef enum +{ + //! Transmit message object. + MSG_OBJ_TYPE_TX, + + //! Transmit remote request message object + MSG_OBJ_TYPE_TX_REMOTE, + + //! Receive message object. + MSG_OBJ_TYPE_RX, + + //! Receive remote request message object. + MSG_OBJ_TYPE_RX_REMOTE, + + //! Remote frame receive remote, with auto-transmit message object. + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// The following enumeration contains all error or status indicators that can +// be returned when calling the CANStatusGet() function. +//***************************************************************************** +//! CAN controller is in local power down mode. +#define CAN_STATUS_PDA 0x00000400 + +//! CAN controller has initiated a system wakeup. +#define CAN_STATUS_WAKE_UP 0x00000200 + +//! CAN controller has detected a parity error. +#define CAN_STATUS_PERR 0x00000100 + +//! CAN controller has entered a Bus Off state. +#define CAN_STATUS_BUS_OFF 0x00000080 + +//! CAN controller error level has reached warning level. +#define CAN_STATUS_EWARN 0x00000040 + +//! CAN controller error level has reached error passive level. +#define CAN_STATUS_EPASS 0x00000020 + +//! A message was received successfully since the last read of this status. +#define CAN_STATUS_RXOK 0x00000010 + +//! A message was transmitted successfully since the last read of this +//! status. +#define CAN_STATUS_TXOK 0x00000008 + +//! This is the mask for the last error code field. +#define CAN_STATUS_LEC_MSK 0x00000007 + +//! There was no error. +#define CAN_STATUS_LEC_NONE 0x00000000 + +//! A bit stuffing error has occurred. +#define CAN_STATUS_LEC_STUFF 0x00000001 + +//! A formatting error has occurred. +#define CAN_STATUS_LEC_FORM 0x00000002 + +//! An acknowledge error has occurred. +#define CAN_STATUS_LEC_ACK 0x00000003 + +//! The bus remained a bit level of 1 for longer than is allowed. +#define CAN_STATUS_LEC_BIT1 0x00000004 + +//! The bus remained a bit level of 0 for longer than is allowed. +#define CAN_STATUS_LEC_BIT0 0x00000005 + +//! A CRC error has occurred. +#define CAN_STATUS_LEC_CRC 0x00000006 + +//***************************************************************************** +// The following macros are added for the new Global Interrupt EN/FLG/CLR +// register +//***************************************************************************** +//CANINT0 global interrupt bit +#define CAN_GLOBAL_INT_CANINT0 0x00000001 + +//CANINT1 global interrupt bit +#define CAN_GLOBAL_INT_CANINT1 0x00000002 + +//***************************************************************************** +// The following macros are missing in hw_can.h because of scripting +// but driverlib can.c needs them +//***************************************************************************** + +#define CAN_INT_INT0ID_STATUS 0x8000 + +#define CAN_IF1ARB_STD_ID_S 18 +#define CAN_IF1ARB_STD_ID_M 0x1FFC0000 // Standard Message Identifier + +#define CAN_IF2ARB_STD_ID_S 18 +#define CAN_IF2ARB_STD_ID_M 0x1FFC0000 // Standard Message Identifier + +//***************************************************************************** +// API Function prototypes +//***************************************************************************** +extern void CANClkSourceSelect(uint32_t ui32Base, uint16_t ucSource); +extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms); +extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms); +extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, + uint32_t ui32BitRate); +extern void CANDisable(uint32_t ui32Base); +extern void CANEnable(uint32_t ui32Base); +extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, + uint32_t *pui32TxCount); +extern void CANInit(uint32_t ui32Base); +extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr); +extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber, + void (*pfnHandler)(void)); +extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg); +extern void CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber); +extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID); +extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *pMsgObject, bool bClrPendingInt); +extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType); +extern bool CANRetryGet(uint32_t ui32Base); +extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry); +extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg); +extern void CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags); + +//***************************************************************************** +// Mark the end of the C bindings section for C++ compilers. +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + +#endif // __CAN_H__ + + diff --git a/bsp/tm4c129x-dk/libraries/driverlib/debug.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h similarity index 56% rename from bsp/tm4c129x-dk/libraries/driverlib/debug.h rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h index fd2e3afba1..8d018c0c7c 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/debug.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h @@ -1,44 +1,47 @@ -//***************************************************************************** +//########################################################################### // -// debug.h - Macros for assisting debug of the driver library. +// FILE: debug.h // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// TITLE: Stellaris style debug header. Included for compatability. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### -#ifndef __DRIVERLIB_DEBUG_H__ -#define __DRIVERLIB_DEBUG_H__ +#ifndef __DEBUG_H__ +#define __DEBUG_H__ //***************************************************************************** // @@ -46,7 +49,7 @@ // to an API. This is only used when doing a DEBUG build. // //***************************************************************************** -extern void __error__(char *pcFilename, uint32_t ui32Line); +extern void __error__(char *pcFilename, unsigned long ulLine); //***************************************************************************** // @@ -54,17 +57,19 @@ extern void __error__(char *pcFilename, uint32_t ui32Line); // will be for procedure arguments. // //***************************************************************************** + + #ifdef DEBUG -#define ASSERT(expr) do \ - { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } \ - while(0) +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } #else #define ASSERT(expr) #endif -#endif // __DRIVERLIB_DEBUG_H__ +#endif // __DEBUG_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c new file mode 100644 index 0000000000..5bff0345ab --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c @@ -0,0 +1,411 @@ +//########################################################################### +// +// FILE: interrupt.c +// +// TITLE: Stellaris style wrapper driver for C28x PIE Interrupt Controller. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "F28x_Project.h" + +#include "inc/hw_types.h" +#include "driverlib/interrupt.h" +#include +#include +#include + + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler. Whenever an interrupt is +//! unregisterd this handler takes it place. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void IntDefaultHandler(void) +{ + asm(" ESTOP0"); + return; +} + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! bool, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +bool +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return __enable_interrupts() & 0x1; +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! bool, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +bool +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return __disable_interrupts() & 0x1; +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +// +//! Assumes PIE is enabled +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can pre-empt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + EALLOW; + //Copy ISR address into PIE table + memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &pfnHandler, sizeof(pfnHandler)); + EDIS; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + uint32_t temp; + + temp = (uint32_t) IntDefaultHandler; + + EALLOW; + //Copy default ISR address into PIE table + memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &temp, sizeof(temp)); + EDIS; +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + uint16_t ui16IntsEnabled; + + ui32Interrupt = ui32Interrupt >> 16; + EALLOW; + //Ensure that PIE is enabled + PieCtrlRegs.PIECTRL.bit.ENPIE=1; + + ui16IntsEnabled = IntMasterDisable(); + + if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table + { + //Enable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) |= 1 << ((ui32Interrupt-0x20)%8); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x20)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8); + + //Enable PIE Group Interrupt + IER |= 1 << ((ui32Interrupt - 0x20)/8); + } + else if (ui32Interrupt >= 0x80) //Upper PIE table + { + //Enable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) |= 1 << (((ui32Interrupt-0x80)%8)+8); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x80)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8); + + //Enable PIE Group Interrupt + IER |= 1 << ((ui32Interrupt - 0x80)/8); + } + else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT + { + //Enable PIE Group Interrupt + IER |= 1 << (ui32Interrupt - 1); + } + else + { + //Other interrupts + } + + EDIS; + + //Re-enable interrupts if they were enabled + if(!ui16IntsEnabled){ + IntMasterEnable(); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + uint16_t ui16IntsEnabled; + + ui32Interrupt = ui32Interrupt >> 16; + EALLOW; + + ui16IntsEnabled = IntMasterDisable(); + + if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table + { + //Disable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) &= ~(1 << ((ui32Interrupt-0x20)%8)); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x20)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8); + } + else if (ui32Interrupt >= 0x80) //Upper PIE table + { + //Disable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) &= ~(1 << (((ui32Interrupt-0x80)%8)+8)); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x80)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8); + } + else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT //Work-around Case + { + //Disable PIE Group Interrupt + IER &= ~(1 << (ui32Interrupt - 1)); + } + else + { + //Other Interrupts + } + EDIS; + + //Re-enable interrupts if they were enabled + if(!ui16IntsEnabled){ + IntMasterEnable(); + } +} + +void IntIFRClear(uint16_t ui16Interrupts) +{ + switch(ui16Interrupts){ + case 0x0001: + IFR &= ~0x0001; + break; + case 0x0002: + IFR &= ~0x0002; + break; + case 0x0004: + IFR &= ~0x0004; + break; + case 0x0008: + IFR &= ~0x0008; + break; + case 0x0010: + IFR &= ~0x0010; + break; + case 0x0020: + IFR &= ~0x0020; + break; + case 0x0040: + IFR &= ~0x0040; + break; + case 0x0080: + IFR &= ~0x0080; + break; + case 0x0100: + IFR &= ~0x0100; + break; + case 0x0200: + IFR &= ~0x0200; + break; + case 0x0400: + IFR &= ~0x0400; + break; + case 0x0800: + IFR &= ~0x0800; + break; + case 0x1000: + IFR &= ~0x1000; + break; + case 0x2000: + IFR &= ~0x2000; + break; + case 0x4000: + IFR &= ~0x4000; + break; + case 0x8000: + IFR &= ~0x8000; + break; + default: + break; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tm4c129x-dk/libraries/driverlib/systick.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h similarity index 61% rename from bsp/tm4c129x-dk/libraries/driverlib/systick.h rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h index 35909ee3fb..d6104fba3f 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/systick.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h @@ -1,44 +1,47 @@ -//***************************************************************************** +//########################################################################### // -// systick.h - Prototypes for the SysTick driver. +// FILE: interrupt.h // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// TITLE: Stellaris style wrapper driver for C28x PIE Interrupt Controller. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### -#ifndef __DRIVERLIB_SYSTICK_H__ -#define __DRIVERLIB_SYSTICK_H__ +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ //***************************************************************************** // @@ -56,15 +59,13 @@ extern "C" // Prototypes for the APIs. // //***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(uint32_t ui32Period); -extern uint32_t SysTickPeriodGet(void); -extern uint32_t SysTickValueGet(void); + extern bool IntMasterEnable(void); + extern bool IntMasterDisable(void); + extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); + extern void IntUnregister(uint32_t ui32Interrupt); + extern void IntEnable(uint32_t ui32Interrupt); + extern void IntDisable(uint32_t ui32Interrupt); + extern void IntIFRClear(uint16_t ui16Interrupts); //***************************************************************************** // @@ -75,4 +76,6 @@ extern uint32_t SysTickValueGet(void); } #endif -#endif // __DRIVERLIB_SYSTICK_H__ +#endif // __INTERRUPT_H__ + + diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_fan.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h similarity index 77% rename from bsp/tm4c129x-dk/libraries/inc/hw_fan.h rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h index 9c191cf0af..c085a00c61 100644 --- a/bsp/tm4c129x-dk/libraries/inc/hw_fan.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h @@ -1,8 +1,8 @@ //***************************************************************************** // -// hw_fan.h - Macros used when accessing the fan control hardware. +// rom.h - Macros to facilitate calling functions in the ROM. // -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,17 +33,12 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. // //***************************************************************************** -#ifndef __HW_FAN_H__ -#define __HW_FAN_H__ +#ifndef __ROM_H__ +#define __ROM_H__ -//***************************************************************************** -// -// The following are defines for the Fan Control register offsets. -// -//***************************************************************************** -#endif // __HW_FAN_H__ +#endif //__ROM_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h new file mode 100644 index 0000000000..7794c1a9d0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h @@ -0,0 +1,5082 @@ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available and in flash otherwise. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCSequenceDataGet +#define MAP_ADCSequenceDataGet \ + ROM_ADCSequenceDataGet +#else +#define MAP_ADCSequenceDataGet \ + ADCSequenceDataGet +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCSequenceEnable +#define MAP_ADCSequenceEnable \ + ROM_ADCSequenceEnable +#else +#define MAP_ADCSequenceEnable \ + ADCSequenceEnable +#endif +#ifdef ROM_ADCSequenceDisable +#define MAP_ADCSequenceDisable \ + ROM_ADCSequenceDisable +#else +#define MAP_ADCSequenceDisable \ + ADCSequenceDisable +#endif +#ifdef ROM_ADCSequenceConfigure +#define MAP_ADCSequenceConfigure \ + ROM_ADCSequenceConfigure +#else +#define MAP_ADCSequenceConfigure \ + ADCSequenceConfigure +#endif +#ifdef ROM_ADCSequenceStepConfigure +#define MAP_ADCSequenceStepConfigure \ + ROM_ADCSequenceStepConfigure +#else +#define MAP_ADCSequenceStepConfigure \ + ADCSequenceStepConfigure +#endif +#ifdef ROM_ADCSequenceOverflow +#define MAP_ADCSequenceOverflow \ + ROM_ADCSequenceOverflow +#else +#define MAP_ADCSequenceOverflow \ + ADCSequenceOverflow +#endif +#ifdef ROM_ADCSequenceOverflowClear +#define MAP_ADCSequenceOverflowClear \ + ROM_ADCSequenceOverflowClear +#else +#define MAP_ADCSequenceOverflowClear \ + ADCSequenceOverflowClear +#endif +#ifdef ROM_ADCSequenceUnderflow +#define MAP_ADCSequenceUnderflow \ + ROM_ADCSequenceUnderflow +#else +#define MAP_ADCSequenceUnderflow \ + ADCSequenceUnderflow +#endif +#ifdef ROM_ADCSequenceUnderflowClear +#define MAP_ADCSequenceUnderflowClear \ + ROM_ADCSequenceUnderflowClear +#else +#define MAP_ADCSequenceUnderflowClear \ + ADCSequenceUnderflowClear +#endif +#ifdef ROM_ADCProcessorTrigger +#define MAP_ADCProcessorTrigger \ + ROM_ADCProcessorTrigger +#else +#define MAP_ADCProcessorTrigger \ + ADCProcessorTrigger +#endif +#ifdef ROM_ADCHardwareOversampleConfigure +#define MAP_ADCHardwareOversampleConfigure \ + ROM_ADCHardwareOversampleConfigure +#else +#define MAP_ADCHardwareOversampleConfigure \ + ADCHardwareOversampleConfigure +#endif +#ifdef ROM_ADCComparatorConfigure +#define MAP_ADCComparatorConfigure \ + ROM_ADCComparatorConfigure +#else +#define MAP_ADCComparatorConfigure \ + ADCComparatorConfigure +#endif +#ifdef ROM_ADCComparatorRegionSet +#define MAP_ADCComparatorRegionSet \ + ROM_ADCComparatorRegionSet +#else +#define MAP_ADCComparatorRegionSet \ + ADCComparatorRegionSet +#endif +#ifdef ROM_ADCComparatorReset +#define MAP_ADCComparatorReset \ + ROM_ADCComparatorReset +#else +#define MAP_ADCComparatorReset \ + ADCComparatorReset +#endif +#ifdef ROM_ADCComparatorIntDisable +#define MAP_ADCComparatorIntDisable \ + ROM_ADCComparatorIntDisable +#else +#define MAP_ADCComparatorIntDisable \ + ADCComparatorIntDisable +#endif +#ifdef ROM_ADCComparatorIntEnable +#define MAP_ADCComparatorIntEnable \ + ROM_ADCComparatorIntEnable +#else +#define MAP_ADCComparatorIntEnable \ + ADCComparatorIntEnable +#endif +#ifdef ROM_ADCComparatorIntStatus +#define MAP_ADCComparatorIntStatus \ + ROM_ADCComparatorIntStatus +#else +#define MAP_ADCComparatorIntStatus \ + ADCComparatorIntStatus +#endif +#ifdef ROM_ADCComparatorIntClear +#define MAP_ADCComparatorIntClear \ + ROM_ADCComparatorIntClear +#else +#define MAP_ADCComparatorIntClear \ + ADCComparatorIntClear +#endif +#ifdef ROM_ADCReferenceSet +#define MAP_ADCReferenceSet \ + ROM_ADCReferenceSet +#else +#define MAP_ADCReferenceSet \ + ADCReferenceSet +#endif +#ifdef ROM_ADCReferenceGet +#define MAP_ADCReferenceGet \ + ROM_ADCReferenceGet +#else +#define MAP_ADCReferenceGet \ + ADCReferenceGet +#endif +#ifdef ROM_ADCPhaseDelaySet +#define MAP_ADCPhaseDelaySet \ + ROM_ADCPhaseDelaySet +#else +#define MAP_ADCPhaseDelaySet \ + ADCPhaseDelaySet +#endif +#ifdef ROM_ADCPhaseDelayGet +#define MAP_ADCPhaseDelayGet \ + ROM_ADCPhaseDelayGet +#else +#define MAP_ADCPhaseDelayGet \ + ADCPhaseDelayGet +#endif +#ifdef ROM_ADCResolutionSet +#define MAP_ADCResolutionSet \ + ROM_ADCResolutionSet +#else +#define MAP_ADCResolutionSet \ + ADCResolutionSet +#endif +#ifdef ROM_ADCResolutionGet +#define MAP_ADCResolutionGet \ + ROM_ADCResolutionGet +#else +#define MAP_ADCResolutionGet \ + ADCResolutionGet +#endif + +//***************************************************************************** +// +// Macros for the CAN API. +// +//***************************************************************************** +#ifdef ROM_CANIntClear +#define MAP_CANIntClear \ + ROM_CANIntClear +#else +#define MAP_CANIntClear \ + CANIntClear +#endif +#ifdef ROM_CANInit +#define MAP_CANInit \ + ROM_CANInit +#else +#define MAP_CANInit \ + CANInit +#endif +#ifdef ROM_CANEnable +#define MAP_CANEnable \ + ROM_CANEnable +#else +#define MAP_CANEnable \ + CANEnable +#endif +#ifdef ROM_CANDisable +#define MAP_CANDisable \ + ROM_CANDisable +#else +#define MAP_CANDisable \ + CANDisable +#endif +#ifdef ROM_CANBitTimingSet +#define MAP_CANBitTimingSet \ + ROM_CANBitTimingSet +#else +#define MAP_CANBitTimingSet \ + CANBitTimingSet +#endif +#ifdef ROM_CANBitTimingGet +#define MAP_CANBitTimingGet \ + ROM_CANBitTimingGet +#else +#define MAP_CANBitTimingGet \ + CANBitTimingGet +#endif +#ifdef ROM_CANMessageSet +#define MAP_CANMessageSet \ + ROM_CANMessageSet +#else +#define MAP_CANMessageSet \ + CANMessageSet +#endif +#ifdef ROM_CANMessageGet +#define MAP_CANMessageGet \ + ROM_CANMessageGet +#else +#define MAP_CANMessageGet \ + CANMessageGet +#endif +#ifdef ROM_CANStatusGet +#define MAP_CANStatusGet \ + ROM_CANStatusGet +#else +#define MAP_CANStatusGet \ + CANStatusGet +#endif +#ifdef ROM_CANMessageClear +#define MAP_CANMessageClear \ + ROM_CANMessageClear +#else +#define MAP_CANMessageClear \ + CANMessageClear +#endif +#ifdef ROM_CANIntEnable +#define MAP_CANIntEnable \ + ROM_CANIntEnable +#else +#define MAP_CANIntEnable \ + CANIntEnable +#endif +#ifdef ROM_CANIntDisable +#define MAP_CANIntDisable \ + ROM_CANIntDisable +#else +#define MAP_CANIntDisable \ + CANIntDisable +#endif +#ifdef ROM_CANIntStatus +#define MAP_CANIntStatus \ + ROM_CANIntStatus +#else +#define MAP_CANIntStatus \ + CANIntStatus +#endif +#ifdef ROM_CANRetryGet +#define MAP_CANRetryGet \ + ROM_CANRetryGet +#else +#define MAP_CANRetryGet \ + CANRetryGet +#endif +#ifdef ROM_CANRetrySet +#define MAP_CANRetrySet \ + ROM_CANRetrySet +#else +#define MAP_CANRetrySet \ + CANRetrySet +#endif +#ifdef ROM_CANErrCntrGet +#define MAP_CANErrCntrGet \ + ROM_CANErrCntrGet +#else +#define MAP_CANErrCntrGet \ + CANErrCntrGet +#endif +#ifdef ROM_CANBitRateSet +#define MAP_CANBitRateSet \ + ROM_CANBitRateSet +#else +#define MAP_CANBitRateSet \ + CANBitRateSet +#endif + +//***************************************************************************** +// +// Macros for the Comparator API. +// +//***************************************************************************** +#ifdef ROM_ComparatorIntClear +#define MAP_ComparatorIntClear \ + ROM_ComparatorIntClear +#else +#define MAP_ComparatorIntClear \ + ComparatorIntClear +#endif +#ifdef ROM_ComparatorConfigure +#define MAP_ComparatorConfigure \ + ROM_ComparatorConfigure +#else +#define MAP_ComparatorConfigure \ + ComparatorConfigure +#endif +#ifdef ROM_ComparatorRefSet +#define MAP_ComparatorRefSet \ + ROM_ComparatorRefSet +#else +#define MAP_ComparatorRefSet \ + ComparatorRefSet +#endif +#ifdef ROM_ComparatorValueGet +#define MAP_ComparatorValueGet \ + ROM_ComparatorValueGet +#else +#define MAP_ComparatorValueGet \ + ComparatorValueGet +#endif +#ifdef ROM_ComparatorIntEnable +#define MAP_ComparatorIntEnable \ + ROM_ComparatorIntEnable +#else +#define MAP_ComparatorIntEnable \ + ComparatorIntEnable +#endif +#ifdef ROM_ComparatorIntDisable +#define MAP_ComparatorIntDisable \ + ROM_ComparatorIntDisable +#else +#define MAP_ComparatorIntDisable \ + ComparatorIntDisable +#endif +#ifdef ROM_ComparatorIntStatus +#define MAP_ComparatorIntStatus \ + ROM_ComparatorIntStatus +#else +#define MAP_ComparatorIntStatus \ + ComparatorIntStatus +#endif + +//***************************************************************************** +// +// Macros for the EEPROM API. +// +//***************************************************************************** +#ifdef ROM_EEPROMRead +#define MAP_EEPROMRead \ + ROM_EEPROMRead +#else +#define MAP_EEPROMRead \ + EEPROMRead +#endif +#ifdef ROM_EEPROMBlockCountGet +#define MAP_EEPROMBlockCountGet \ + ROM_EEPROMBlockCountGet +#else +#define MAP_EEPROMBlockCountGet \ + EEPROMBlockCountGet +#endif +#ifdef ROM_EEPROMBlockHide +#define MAP_EEPROMBlockHide \ + ROM_EEPROMBlockHide +#else +#define MAP_EEPROMBlockHide \ + EEPROMBlockHide +#endif +#ifdef ROM_EEPROMBlockLock +#define MAP_EEPROMBlockLock \ + ROM_EEPROMBlockLock +#else +#define MAP_EEPROMBlockLock \ + EEPROMBlockLock +#endif +#ifdef ROM_EEPROMBlockPasswordSet +#define MAP_EEPROMBlockPasswordSet \ + ROM_EEPROMBlockPasswordSet +#else +#define MAP_EEPROMBlockPasswordSet \ + EEPROMBlockPasswordSet +#endif +#ifdef ROM_EEPROMBlockProtectGet +#define MAP_EEPROMBlockProtectGet \ + ROM_EEPROMBlockProtectGet +#else +#define MAP_EEPROMBlockProtectGet \ + EEPROMBlockProtectGet +#endif +#ifdef ROM_EEPROMBlockProtectSet +#define MAP_EEPROMBlockProtectSet \ + ROM_EEPROMBlockProtectSet +#else +#define MAP_EEPROMBlockProtectSet \ + EEPROMBlockProtectSet +#endif +#ifdef ROM_EEPROMBlockUnlock +#define MAP_EEPROMBlockUnlock \ + ROM_EEPROMBlockUnlock +#else +#define MAP_EEPROMBlockUnlock \ + EEPROMBlockUnlock +#endif +#ifdef ROM_EEPROMIntClear +#define MAP_EEPROMIntClear \ + ROM_EEPROMIntClear +#else +#define MAP_EEPROMIntClear \ + EEPROMIntClear +#endif +#ifdef ROM_EEPROMIntDisable +#define MAP_EEPROMIntDisable \ + ROM_EEPROMIntDisable +#else +#define MAP_EEPROMIntDisable \ + EEPROMIntDisable +#endif +#ifdef ROM_EEPROMIntEnable +#define MAP_EEPROMIntEnable \ + ROM_EEPROMIntEnable +#else +#define MAP_EEPROMIntEnable \ + EEPROMIntEnable +#endif +#ifdef ROM_EEPROMIntStatus +#define MAP_EEPROMIntStatus \ + ROM_EEPROMIntStatus +#else +#define MAP_EEPROMIntStatus \ + EEPROMIntStatus +#endif +#ifdef ROM_EEPROMMassErase +#define MAP_EEPROMMassErase \ + ROM_EEPROMMassErase +#else +#define MAP_EEPROMMassErase \ + EEPROMMassErase +#endif +#ifdef ROM_EEPROMProgram +#define MAP_EEPROMProgram \ + ROM_EEPROMProgram +#else +#define MAP_EEPROMProgram \ + EEPROMProgram +#endif +#ifdef ROM_EEPROMProgramNonBlocking +#define MAP_EEPROMProgramNonBlocking \ + ROM_EEPROMProgramNonBlocking +#else +#define MAP_EEPROMProgramNonBlocking \ + EEPROMProgramNonBlocking +#endif +#ifdef ROM_EEPROMSizeGet +#define MAP_EEPROMSizeGet \ + ROM_EEPROMSizeGet +#else +#define MAP_EEPROMSizeGet \ + EEPROMSizeGet +#endif +#ifdef ROM_EEPROMStatusGet +#define MAP_EEPROMStatusGet \ + ROM_EEPROMStatusGet +#else +#define MAP_EEPROMStatusGet \ + EEPROMStatusGet +#endif +#ifdef ROM_EEPROMInit +#define MAP_EEPROMInit \ + ROM_EEPROMInit +#else +#define MAP_EEPROMInit \ + EEPROMInit +#endif + +//***************************************************************************** +// +// Macros for the EPI API. +// +//***************************************************************************** +#ifdef ROM_EPIIntStatus +#define MAP_EPIIntStatus \ + ROM_EPIIntStatus +#else +#define MAP_EPIIntStatus \ + EPIIntStatus +#endif +#ifdef ROM_EPIModeSet +#define MAP_EPIModeSet \ + ROM_EPIModeSet +#else +#define MAP_EPIModeSet \ + EPIModeSet +#endif +#ifdef ROM_EPIDividerSet +#define MAP_EPIDividerSet \ + ROM_EPIDividerSet +#else +#define MAP_EPIDividerSet \ + EPIDividerSet +#endif +#ifdef ROM_EPIConfigSDRAMSet +#define MAP_EPIConfigSDRAMSet \ + ROM_EPIConfigSDRAMSet +#else +#define MAP_EPIConfigSDRAMSet \ + EPIConfigSDRAMSet +#endif +#ifdef ROM_EPIConfigGPModeSet +#define MAP_EPIConfigGPModeSet \ + ROM_EPIConfigGPModeSet +#else +#define MAP_EPIConfigGPModeSet \ + EPIConfigGPModeSet +#endif +#ifdef ROM_EPIConfigHB8Set +#define MAP_EPIConfigHB8Set \ + ROM_EPIConfigHB8Set +#else +#define MAP_EPIConfigHB8Set \ + EPIConfigHB8Set +#endif +#ifdef ROM_EPIConfigHB16Set +#define MAP_EPIConfigHB16Set \ + ROM_EPIConfigHB16Set +#else +#define MAP_EPIConfigHB16Set \ + EPIConfigHB16Set +#endif +#ifdef ROM_EPIAddressMapSet +#define MAP_EPIAddressMapSet \ + ROM_EPIAddressMapSet +#else +#define MAP_EPIAddressMapSet \ + EPIAddressMapSet +#endif +#ifdef ROM_EPINonBlockingReadConfigure +#define MAP_EPINonBlockingReadConfigure \ + ROM_EPINonBlockingReadConfigure +#else +#define MAP_EPINonBlockingReadConfigure \ + EPINonBlockingReadConfigure +#endif +#ifdef ROM_EPINonBlockingReadStart +#define MAP_EPINonBlockingReadStart \ + ROM_EPINonBlockingReadStart +#else +#define MAP_EPINonBlockingReadStart \ + EPINonBlockingReadStart +#endif +#ifdef ROM_EPINonBlockingReadStop +#define MAP_EPINonBlockingReadStop \ + ROM_EPINonBlockingReadStop +#else +#define MAP_EPINonBlockingReadStop \ + EPINonBlockingReadStop +#endif +#ifdef ROM_EPINonBlockingReadCount +#define MAP_EPINonBlockingReadCount \ + ROM_EPINonBlockingReadCount +#else +#define MAP_EPINonBlockingReadCount \ + EPINonBlockingReadCount +#endif +#ifdef ROM_EPINonBlockingReadAvail +#define MAP_EPINonBlockingReadAvail \ + ROM_EPINonBlockingReadAvail +#else +#define MAP_EPINonBlockingReadAvail \ + EPINonBlockingReadAvail +#endif +#ifdef ROM_EPINonBlockingReadGet32 +#define MAP_EPINonBlockingReadGet32 \ + ROM_EPINonBlockingReadGet32 +#else +#define MAP_EPINonBlockingReadGet32 \ + EPINonBlockingReadGet32 +#endif +#ifdef ROM_EPINonBlockingReadGet16 +#define MAP_EPINonBlockingReadGet16 \ + ROM_EPINonBlockingReadGet16 +#else +#define MAP_EPINonBlockingReadGet16 \ + EPINonBlockingReadGet16 +#endif +#ifdef ROM_EPINonBlockingReadGet8 +#define MAP_EPINonBlockingReadGet8 \ + ROM_EPINonBlockingReadGet8 +#else +#define MAP_EPINonBlockingReadGet8 \ + EPINonBlockingReadGet8 +#endif +#ifdef ROM_EPIFIFOConfig +#define MAP_EPIFIFOConfig \ + ROM_EPIFIFOConfig +#else +#define MAP_EPIFIFOConfig \ + EPIFIFOConfig +#endif +#ifdef ROM_EPIWriteFIFOCountGet +#define MAP_EPIWriteFIFOCountGet \ + ROM_EPIWriteFIFOCountGet +#else +#define MAP_EPIWriteFIFOCountGet \ + EPIWriteFIFOCountGet +#endif +#ifdef ROM_EPIIntEnable +#define MAP_EPIIntEnable \ + ROM_EPIIntEnable +#else +#define MAP_EPIIntEnable \ + EPIIntEnable +#endif +#ifdef ROM_EPIIntDisable +#define MAP_EPIIntDisable \ + ROM_EPIIntDisable +#else +#define MAP_EPIIntDisable \ + EPIIntDisable +#endif +#ifdef ROM_EPIIntErrorStatus +#define MAP_EPIIntErrorStatus \ + ROM_EPIIntErrorStatus +#else +#define MAP_EPIIntErrorStatus \ + EPIIntErrorStatus +#endif +#ifdef ROM_EPIIntErrorClear +#define MAP_EPIIntErrorClear \ + ROM_EPIIntErrorClear +#else +#define MAP_EPIIntErrorClear \ + EPIIntErrorClear +#endif + +//***************************************************************************** +// +// Macros for the Ethernet API. +// +//***************************************************************************** +#ifdef ROM_EthernetIntClear +#define MAP_EthernetIntClear \ + ROM_EthernetIntClear +#else +#define MAP_EthernetIntClear \ + EthernetIntClear +#endif +#ifdef ROM_EthernetInitExpClk +#define MAP_EthernetInitExpClk \ + ROM_EthernetInitExpClk +#else +#define MAP_EthernetInitExpClk \ + EthernetInitExpClk +#endif +#ifdef ROM_EthernetConfigSet +#define MAP_EthernetConfigSet \ + ROM_EthernetConfigSet +#else +#define MAP_EthernetConfigSet \ + EthernetConfigSet +#endif +#ifdef ROM_EthernetConfigGet +#define MAP_EthernetConfigGet \ + ROM_EthernetConfigGet +#else +#define MAP_EthernetConfigGet \ + EthernetConfigGet +#endif +#ifdef ROM_EthernetMACAddrSet +#define MAP_EthernetMACAddrSet \ + ROM_EthernetMACAddrSet +#else +#define MAP_EthernetMACAddrSet \ + EthernetMACAddrSet +#endif +#ifdef ROM_EthernetMACAddrGet +#define MAP_EthernetMACAddrGet \ + ROM_EthernetMACAddrGet +#else +#define MAP_EthernetMACAddrGet \ + EthernetMACAddrGet +#endif +#ifdef ROM_EthernetEnable +#define MAP_EthernetEnable \ + ROM_EthernetEnable +#else +#define MAP_EthernetEnable \ + EthernetEnable +#endif +#ifdef ROM_EthernetDisable +#define MAP_EthernetDisable \ + ROM_EthernetDisable +#else +#define MAP_EthernetDisable \ + EthernetDisable +#endif +#ifdef ROM_EthernetPacketAvail +#define MAP_EthernetPacketAvail \ + ROM_EthernetPacketAvail +#else +#define MAP_EthernetPacketAvail \ + EthernetPacketAvail +#endif +#ifdef ROM_EthernetSpaceAvail +#define MAP_EthernetSpaceAvail \ + ROM_EthernetSpaceAvail +#else +#define MAP_EthernetSpaceAvail \ + EthernetSpaceAvail +#endif +#ifdef ROM_EthernetPacketGetNonBlocking +#define MAP_EthernetPacketGetNonBlocking \ + ROM_EthernetPacketGetNonBlocking +#else +#define MAP_EthernetPacketGetNonBlocking \ + EthernetPacketGetNonBlocking +#endif +#ifdef ROM_EthernetPacketGet +#define MAP_EthernetPacketGet \ + ROM_EthernetPacketGet +#else +#define MAP_EthernetPacketGet \ + EthernetPacketGet +#endif +#ifdef ROM_EthernetPacketPutNonBlocking +#define MAP_EthernetPacketPutNonBlocking \ + ROM_EthernetPacketPutNonBlocking +#else +#define MAP_EthernetPacketPutNonBlocking \ + EthernetPacketPutNonBlocking +#endif +#ifdef ROM_EthernetPacketPut +#define MAP_EthernetPacketPut \ + ROM_EthernetPacketPut +#else +#define MAP_EthernetPacketPut \ + EthernetPacketPut +#endif +#ifdef ROM_EthernetIntEnable +#define MAP_EthernetIntEnable \ + ROM_EthernetIntEnable +#else +#define MAP_EthernetIntEnable \ + EthernetIntEnable +#endif +#ifdef ROM_EthernetIntDisable +#define MAP_EthernetIntDisable \ + ROM_EthernetIntDisable +#else +#define MAP_EthernetIntDisable \ + EthernetIntDisable +#endif +#ifdef ROM_EthernetIntStatus +#define MAP_EthernetIntStatus \ + ROM_EthernetIntStatus +#else +#define MAP_EthernetIntStatus \ + EthernetIntStatus +#endif +#ifdef ROM_EthernetPHYWrite +#define MAP_EthernetPHYWrite \ + ROM_EthernetPHYWrite +#else +#define MAP_EthernetPHYWrite \ + EthernetPHYWrite +#endif +#ifdef ROM_EthernetPHYRead +#define MAP_EthernetPHYRead \ + ROM_EthernetPHYRead +#else +#define MAP_EthernetPHYRead \ + EthernetPHYRead +#endif +#ifdef ROM_EthernetPHYAddrSet +#define MAP_EthernetPHYAddrSet \ + ROM_EthernetPHYAddrSet +#else +#define MAP_EthernetPHYAddrSet \ + EthernetPHYAddrSet +#endif +#ifdef ROM_EthernetPHYPowerOff +#define MAP_EthernetPHYPowerOff \ + ROM_EthernetPHYPowerOff +#else +#define MAP_EthernetPHYPowerOff \ + EthernetPHYPowerOff +#endif +#ifdef ROM_EthernetPHYPowerOn +#define MAP_EthernetPHYPowerOn \ + ROM_EthernetPHYPowerOn +#else +#define MAP_EthernetPHYPowerOn \ + EthernetPHYPowerOn +#endif + +//***************************************************************************** +// +// Macros for the Fan API. +// +//***************************************************************************** +#ifdef ROM_FanIntClear +#define MAP_FanIntClear \ + ROM_FanIntClear +#else +#define MAP_FanIntClear \ + FanIntClear +#endif +#ifdef ROM_FanChannelConfigAuto +#define MAP_FanChannelConfigAuto \ + ROM_FanChannelConfigAuto +#else +#define MAP_FanChannelConfigAuto \ + FanChannelConfigAuto +#endif +#ifdef ROM_FanChannelConfigManual +#define MAP_FanChannelConfigManual \ + ROM_FanChannelConfigManual +#else +#define MAP_FanChannelConfigManual \ + FanChannelConfigManual +#endif +#ifdef ROM_FanChannelDisable +#define MAP_FanChannelDisable \ + ROM_FanChannelDisable +#else +#define MAP_FanChannelDisable \ + FanChannelDisable +#endif +#ifdef ROM_FanChannelDutyGet +#define MAP_FanChannelDutyGet \ + ROM_FanChannelDutyGet +#else +#define MAP_FanChannelDutyGet \ + FanChannelDutyGet +#endif +#ifdef ROM_FanChannelDutySet +#define MAP_FanChannelDutySet \ + ROM_FanChannelDutySet +#else +#define MAP_FanChannelDutySet \ + FanChannelDutySet +#endif +#ifdef ROM_FanChannelEnable +#define MAP_FanChannelEnable \ + ROM_FanChannelEnable +#else +#define MAP_FanChannelEnable \ + FanChannelEnable +#endif +#ifdef ROM_FanChannelRPMGet +#define MAP_FanChannelRPMGet \ + ROM_FanChannelRPMGet +#else +#define MAP_FanChannelRPMGet \ + FanChannelRPMGet +#endif +#ifdef ROM_FanChannelRPMSet +#define MAP_FanChannelRPMSet \ + ROM_FanChannelRPMSet +#else +#define MAP_FanChannelRPMSet \ + FanChannelRPMSet +#endif +#ifdef ROM_FanChannelStatus +#define MAP_FanChannelStatus \ + ROM_FanChannelStatus +#else +#define MAP_FanChannelStatus \ + FanChannelStatus +#endif +#ifdef ROM_FanChannelsGet +#define MAP_FanChannelsGet \ + ROM_FanChannelsGet +#else +#define MAP_FanChannelsGet \ + FanChannelsGet +#endif +#ifdef ROM_FanIntDisable +#define MAP_FanIntDisable \ + ROM_FanIntDisable +#else +#define MAP_FanIntDisable \ + FanIntDisable +#endif +#ifdef ROM_FanIntEnable +#define MAP_FanIntEnable \ + ROM_FanIntEnable +#else +#define MAP_FanIntEnable \ + FanIntEnable +#endif +#ifdef ROM_FanIntStatus +#define MAP_FanIntStatus \ + ROM_FanIntStatus +#else +#define MAP_FanIntStatus \ + FanIntStatus +#endif + +//***************************************************************************** +// +// Macros for the Flash API. +// +//***************************************************************************** +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashUsecGet +#define MAP_FlashUsecGet \ + ROM_FlashUsecGet +#else +#define MAP_FlashUsecGet \ + FlashUsecGet +#endif +#ifdef ROM_FlashUsecSet +#define MAP_FlashUsecSet \ + ROM_FlashUsecSet +#else +#define MAP_FlashUsecSet \ + FlashUsecSet +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif +#ifdef ROM_FlashProtectSet +#define MAP_FlashProtectSet \ + ROM_FlashProtectSet +#else +#define MAP_FlashProtectSet \ + FlashProtectSet +#endif +#ifdef ROM_FlashProtectSave +#define MAP_FlashProtectSave \ + ROM_FlashProtectSave +#else +#define MAP_FlashProtectSave \ + FlashProtectSave +#endif +#ifdef ROM_FlashUserGet +#define MAP_FlashUserGet \ + ROM_FlashUserGet +#else +#define MAP_FlashUserGet \ + FlashUserGet +#endif +#ifdef ROM_FlashUserSet +#define MAP_FlashUserSet \ + ROM_FlashUserSet +#else +#define MAP_FlashUserSet \ + FlashUserSet +#endif +#ifdef ROM_FlashUserSave +#define MAP_FlashUserSave \ + ROM_FlashUserSave +#else +#define MAP_FlashUserSave \ + FlashUserSave +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif + +//***************************************************************************** +// +// Macros for the FPU API. +// +//***************************************************************************** +#ifdef ROM_FPUEnable +#define MAP_FPUEnable \ + ROM_FPUEnable +#else +#define MAP_FPUEnable \ + FPUEnable +#endif +#ifdef ROM_FPUDisable +#define MAP_FPUDisable \ + ROM_FPUDisable +#else +#define MAP_FPUDisable \ + FPUDisable +#endif +#ifdef ROM_FPUFlushToZeroModeSet +#define MAP_FPUFlushToZeroModeSet \ + ROM_FPUFlushToZeroModeSet +#else +#define MAP_FPUFlushToZeroModeSet \ + FPUFlushToZeroModeSet +#endif +#ifdef ROM_FPUHalfPrecisionModeSet +#define MAP_FPUHalfPrecisionModeSet \ + ROM_FPUHalfPrecisionModeSet +#else +#define MAP_FPUHalfPrecisionModeSet \ + FPUHalfPrecisionModeSet +#endif +#ifdef ROM_FPULazyStackingEnable +#define MAP_FPULazyStackingEnable \ + ROM_FPULazyStackingEnable +#else +#define MAP_FPULazyStackingEnable \ + FPULazyStackingEnable +#endif +#ifdef ROM_FPUNaNModeSet +#define MAP_FPUNaNModeSet \ + ROM_FPUNaNModeSet +#else +#define MAP_FPUNaNModeSet \ + FPUNaNModeSet +#endif +#ifdef ROM_FPURoundingModeSet +#define MAP_FPURoundingModeSet \ + ROM_FPURoundingModeSet +#else +#define MAP_FPURoundingModeSet \ + FPURoundingModeSet +#endif +#ifdef ROM_FPUStackingDisable +#define MAP_FPUStackingDisable \ + ROM_FPUStackingDisable +#else +#define MAP_FPUStackingDisable \ + FPUStackingDisable +#endif +#ifdef ROM_FPUStackingEnable +#define MAP_FPUStackingEnable \ + ROM_FPUStackingEnable +#else +#define MAP_FPUStackingEnable \ + FPUStackingEnable +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOPadConfigSet +#define MAP_GPIOPadConfigSet \ + ROM_GPIOPadConfigSet +#else +#define MAP_GPIOPadConfigSet \ + GPIOPadConfigSet +#endif +#ifdef ROM_GPIOPadConfigGet +#define MAP_GPIOPadConfigGet \ + ROM_GPIOPadConfigGet +#else +#define MAP_GPIOPadConfigGet \ + GPIOPadConfigGet +#endif +#ifdef ROM_GPIOPinIntEnable +#define MAP_GPIOPinIntEnable \ + ROM_GPIOPinIntEnable +#else +#define MAP_GPIOPinIntEnable \ + GPIOPinIntEnable +#endif +#ifdef ROM_GPIOPinIntDisable +#define MAP_GPIOPinIntDisable \ + ROM_GPIOPinIntDisable +#else +#define MAP_GPIOPinIntDisable \ + GPIOPinIntDisable +#endif +#ifdef ROM_GPIOPinIntStatus +#define MAP_GPIOPinIntStatus \ + ROM_GPIOPinIntStatus +#else +#define MAP_GPIOPinIntStatus \ + GPIOPinIntStatus +#endif +#ifdef ROM_GPIOPinIntClear +#define MAP_GPIOPinIntClear \ + ROM_GPIOPinIntClear +#else +#define MAP_GPIOPinIntClear \ + GPIOPinIntClear +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinTypeCAN +#define MAP_GPIOPinTypeCAN \ + ROM_GPIOPinTypeCAN +#else +#define MAP_GPIOPinTypeCAN \ + GPIOPinTypeCAN +#endif +#ifdef ROM_GPIOPinTypeComparator +#define MAP_GPIOPinTypeComparator \ + ROM_GPIOPinTypeComparator +#else +#define MAP_GPIOPinTypeComparator \ + GPIOPinTypeComparator +#endif +#ifdef ROM_GPIOPinTypeGPIOInput +#define MAP_GPIOPinTypeGPIOInput \ + ROM_GPIOPinTypeGPIOInput +#else +#define MAP_GPIOPinTypeGPIOInput \ + GPIOPinTypeGPIOInput +#endif +#ifdef ROM_GPIOPinTypeGPIOOutput +#define MAP_GPIOPinTypeGPIOOutput \ + ROM_GPIOPinTypeGPIOOutput +#else +#define MAP_GPIOPinTypeGPIOOutput \ + GPIOPinTypeGPIOOutput +#endif +#ifdef ROM_GPIOPinTypeI2C +#define MAP_GPIOPinTypeI2C \ + ROM_GPIOPinTypeI2C +#else +#define MAP_GPIOPinTypeI2C \ + GPIOPinTypeI2C +#endif +#ifdef ROM_GPIOPinTypePWM +#define MAP_GPIOPinTypePWM \ + ROM_GPIOPinTypePWM +#else +#define MAP_GPIOPinTypePWM \ + GPIOPinTypePWM +#endif +#ifdef ROM_GPIOPinTypeQEI +#define MAP_GPIOPinTypeQEI \ + ROM_GPIOPinTypeQEI +#else +#define MAP_GPIOPinTypeQEI \ + GPIOPinTypeQEI +#endif +#ifdef ROM_GPIOPinTypeSSI +#define MAP_GPIOPinTypeSSI \ + ROM_GPIOPinTypeSSI +#else +#define MAP_GPIOPinTypeSSI \ + GPIOPinTypeSSI +#endif +#ifdef ROM_GPIOPinTypeTimer +#define MAP_GPIOPinTypeTimer \ + ROM_GPIOPinTypeTimer +#else +#define MAP_GPIOPinTypeTimer \ + GPIOPinTypeTimer +#endif +#ifdef ROM_GPIOPinTypeUART +#define MAP_GPIOPinTypeUART \ + ROM_GPIOPinTypeUART +#else +#define MAP_GPIOPinTypeUART \ + GPIOPinTypeUART +#endif +#ifdef ROM_GPIOPinTypeGPIOOutputOD +#define MAP_GPIOPinTypeGPIOOutputOD \ + ROM_GPIOPinTypeGPIOOutputOD +#else +#define MAP_GPIOPinTypeGPIOOutputOD \ + GPIOPinTypeGPIOOutputOD +#endif +#ifdef ROM_GPIOPinTypeADC +#define MAP_GPIOPinTypeADC \ + ROM_GPIOPinTypeADC +#else +#define MAP_GPIOPinTypeADC \ + GPIOPinTypeADC +#endif +#ifdef ROM_GPIOPinTypeUSBDigital +#define MAP_GPIOPinTypeUSBDigital \ + ROM_GPIOPinTypeUSBDigital +#else +#define MAP_GPIOPinTypeUSBDigital \ + GPIOPinTypeUSBDigital +#endif +#ifdef ROM_GPIOPinTypeI2S +#define MAP_GPIOPinTypeI2S \ + ROM_GPIOPinTypeI2S +#else +#define MAP_GPIOPinTypeI2S \ + GPIOPinTypeI2S +#endif +#ifdef ROM_GPIOPinConfigure +#define MAP_GPIOPinConfigure \ + ROM_GPIOPinConfigure +#else +#define MAP_GPIOPinConfigure \ + GPIOPinConfigure +#endif +#ifdef ROM_GPIOPinTypeEthernetLED +#define MAP_GPIOPinTypeEthernetLED \ + ROM_GPIOPinTypeEthernetLED +#else +#define MAP_GPIOPinTypeEthernetLED \ + GPIOPinTypeEthernetLED +#endif +#ifdef ROM_GPIOPinTypeUSBAnalog +#define MAP_GPIOPinTypeUSBAnalog \ + ROM_GPIOPinTypeUSBAnalog +#else +#define MAP_GPIOPinTypeUSBAnalog \ + GPIOPinTypeUSBAnalog +#endif +#ifdef ROM_GPIOPinTypeEPI +#define MAP_GPIOPinTypeEPI \ + ROM_GPIOPinTypeEPI +#else +#define MAP_GPIOPinTypeEPI \ + GPIOPinTypeEPI +#endif +#ifdef ROM_GPIOPinTypeEthernetMII +#define MAP_GPIOPinTypeEthernetMII \ + ROM_GPIOPinTypeEthernetMII +#else +#define MAP_GPIOPinTypeEthernetMII \ + GPIOPinTypeEthernetMII +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOADCTriggerEnable +#define MAP_GPIOADCTriggerEnable \ + ROM_GPIOADCTriggerEnable +#else +#define MAP_GPIOADCTriggerEnable \ + GPIOADCTriggerEnable +#endif +#ifdef ROM_GPIOADCTriggerDisable +#define MAP_GPIOADCTriggerDisable \ + ROM_GPIOADCTriggerDisable +#else +#define MAP_GPIOADCTriggerDisable \ + GPIOADCTriggerDisable +#endif +#ifdef ROM_GPIOPinTypeFan +#define MAP_GPIOPinTypeFan \ + ROM_GPIOPinTypeFan +#else +#define MAP_GPIOPinTypeFan \ + GPIOPinTypeFan +#endif +#ifdef ROM_GPIOPinTypeLPC +#define MAP_GPIOPinTypeLPC \ + ROM_GPIOPinTypeLPC +#else +#define MAP_GPIOPinTypeLPC \ + GPIOPinTypeLPC +#endif +#ifdef ROM_GPIOPinTypePECIRx +#define MAP_GPIOPinTypePECIRx \ + ROM_GPIOPinTypePECIRx +#else +#define MAP_GPIOPinTypePECIRx \ + GPIOPinTypePECIRx +#endif +#ifdef ROM_GPIOPinTypePECITx +#define MAP_GPIOPinTypePECITx \ + ROM_GPIOPinTypePECITx +#else +#define MAP_GPIOPinTypePECITx \ + GPIOPinTypePECITx +#endif +#ifdef ROM_GPIOPinTypeI2CSCL +#define MAP_GPIOPinTypeI2CSCL \ + ROM_GPIOPinTypeI2CSCL +#else +#define MAP_GPIOPinTypeI2CSCL \ + GPIOPinTypeI2CSCL +#endif + +//***************************************************************************** +// +// Macros for the Hibernate API. +// +//***************************************************************************** +#ifdef ROM_HibernateIntClear +#define MAP_HibernateIntClear \ + ROM_HibernateIntClear +#else +#define MAP_HibernateIntClear \ + HibernateIntClear +#endif +#ifdef ROM_HibernateEnableExpClk +#define MAP_HibernateEnableExpClk \ + ROM_HibernateEnableExpClk +#else +#define MAP_HibernateEnableExpClk \ + HibernateEnableExpClk +#endif +#ifdef ROM_HibernateDisable +#define MAP_HibernateDisable \ + ROM_HibernateDisable +#else +#define MAP_HibernateDisable \ + HibernateDisable +#endif +#ifdef ROM_HibernateClockSelect +#define MAP_HibernateClockSelect \ + ROM_HibernateClockSelect +#else +#define MAP_HibernateClockSelect \ + HibernateClockSelect +#endif +#ifdef ROM_HibernateRTCEnable +#define MAP_HibernateRTCEnable \ + ROM_HibernateRTCEnable +#else +#define MAP_HibernateRTCEnable \ + HibernateRTCEnable +#endif +#ifdef ROM_HibernateRTCDisable +#define MAP_HibernateRTCDisable \ + ROM_HibernateRTCDisable +#else +#define MAP_HibernateRTCDisable \ + HibernateRTCDisable +#endif +#ifdef ROM_HibernateWakeSet +#define MAP_HibernateWakeSet \ + ROM_HibernateWakeSet +#else +#define MAP_HibernateWakeSet \ + HibernateWakeSet +#endif +#ifdef ROM_HibernateWakeGet +#define MAP_HibernateWakeGet \ + ROM_HibernateWakeGet +#else +#define MAP_HibernateWakeGet \ + HibernateWakeGet +#endif +#ifdef ROM_HibernateLowBatSet +#define MAP_HibernateLowBatSet \ + ROM_HibernateLowBatSet +#else +#define MAP_HibernateLowBatSet \ + HibernateLowBatSet +#endif +#ifdef ROM_HibernateLowBatGet +#define MAP_HibernateLowBatGet \ + ROM_HibernateLowBatGet +#else +#define MAP_HibernateLowBatGet \ + HibernateLowBatGet +#endif +#ifdef ROM_HibernateRTCSet +#define MAP_HibernateRTCSet \ + ROM_HibernateRTCSet +#else +#define MAP_HibernateRTCSet \ + HibernateRTCSet +#endif +#ifdef ROM_HibernateRTCGet +#define MAP_HibernateRTCGet \ + ROM_HibernateRTCGet +#else +#define MAP_HibernateRTCGet \ + HibernateRTCGet +#endif +#ifdef ROM_HibernateRTCMatch0Set +#define MAP_HibernateRTCMatch0Set \ + ROM_HibernateRTCMatch0Set +#else +#define MAP_HibernateRTCMatch0Set \ + HibernateRTCMatch0Set +#endif +#ifdef ROM_HibernateRTCMatch0Get +#define MAP_HibernateRTCMatch0Get \ + ROM_HibernateRTCMatch0Get +#else +#define MAP_HibernateRTCMatch0Get \ + HibernateRTCMatch0Get +#endif +#ifdef ROM_HibernateRTCMatch1Set +#define MAP_HibernateRTCMatch1Set \ + ROM_HibernateRTCMatch1Set +#else +#define MAP_HibernateRTCMatch1Set \ + HibernateRTCMatch1Set +#endif +#ifdef ROM_HibernateRTCMatch1Get +#define MAP_HibernateRTCMatch1Get \ + ROM_HibernateRTCMatch1Get +#else +#define MAP_HibernateRTCMatch1Get \ + HibernateRTCMatch1Get +#endif +#ifdef ROM_HibernateRTCTrimSet +#define MAP_HibernateRTCTrimSet \ + ROM_HibernateRTCTrimSet +#else +#define MAP_HibernateRTCTrimSet \ + HibernateRTCTrimSet +#endif +#ifdef ROM_HibernateRTCTrimGet +#define MAP_HibernateRTCTrimGet \ + ROM_HibernateRTCTrimGet +#else +#define MAP_HibernateRTCTrimGet \ + HibernateRTCTrimGet +#endif +#ifdef ROM_HibernateDataSet +#define MAP_HibernateDataSet \ + ROM_HibernateDataSet +#else +#define MAP_HibernateDataSet \ + HibernateDataSet +#endif +#ifdef ROM_HibernateDataGet +#define MAP_HibernateDataGet \ + ROM_HibernateDataGet +#else +#define MAP_HibernateDataGet \ + HibernateDataGet +#endif +#ifdef ROM_HibernateRequest +#define MAP_HibernateRequest \ + ROM_HibernateRequest +#else +#define MAP_HibernateRequest \ + HibernateRequest +#endif +#ifdef ROM_HibernateIntEnable +#define MAP_HibernateIntEnable \ + ROM_HibernateIntEnable +#else +#define MAP_HibernateIntEnable \ + HibernateIntEnable +#endif +#ifdef ROM_HibernateIntDisable +#define MAP_HibernateIntDisable \ + ROM_HibernateIntDisable +#else +#define MAP_HibernateIntDisable \ + HibernateIntDisable +#endif +#ifdef ROM_HibernateIntStatus +#define MAP_HibernateIntStatus \ + ROM_HibernateIntStatus +#else +#define MAP_HibernateIntStatus \ + HibernateIntStatus +#endif +#ifdef ROM_HibernateIsActive +#define MAP_HibernateIsActive \ + ROM_HibernateIsActive +#else +#define MAP_HibernateIsActive \ + HibernateIsActive +#endif +#ifdef ROM_HibernateRTCSSMatch0Set +#define MAP_HibernateRTCSSMatch0Set \ + ROM_HibernateRTCSSMatch0Set +#else +#define MAP_HibernateRTCSSMatch0Set \ + HibernateRTCSSMatch0Set +#endif +#ifdef ROM_HibernateRTCSSMatch0Get +#define MAP_HibernateRTCSSMatch0Get \ + ROM_HibernateRTCSSMatch0Get +#else +#define MAP_HibernateRTCSSMatch0Get \ + HibernateRTCSSMatch0Get +#endif +#ifdef ROM_HibernateRTCSSGet +#define MAP_HibernateRTCSSGet \ + ROM_HibernateRTCSSGet +#else +#define MAP_HibernateRTCSSGet \ + HibernateRTCSSGet +#endif +#ifdef ROM_HibernateClockConfig +#define MAP_HibernateClockConfig \ + ROM_HibernateClockConfig +#else +#define MAP_HibernateClockConfig \ + HibernateClockConfig +#endif +#ifdef ROM_HibernateBatCheckStart +#define MAP_HibernateBatCheckStart \ + ROM_HibernateBatCheckStart +#else +#define MAP_HibernateBatCheckStart \ + HibernateBatCheckStart +#endif +#ifdef ROM_HibernateBatCheckDone +#define MAP_HibernateBatCheckDone \ + ROM_HibernateBatCheckDone +#else +#define MAP_HibernateBatCheckDone \ + HibernateBatCheckDone +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif + +//***************************************************************************** +// +// Macros for the I2S API. +// +//***************************************************************************** +#ifdef ROM_I2SIntStatus +#define MAP_I2SIntStatus \ + ROM_I2SIntStatus +#else +#define MAP_I2SIntStatus \ + I2SIntStatus +#endif +#ifdef ROM_I2STxEnable +#define MAP_I2STxEnable \ + ROM_I2STxEnable +#else +#define MAP_I2STxEnable \ + I2STxEnable +#endif +#ifdef ROM_I2STxDisable +#define MAP_I2STxDisable \ + ROM_I2STxDisable +#else +#define MAP_I2STxDisable \ + I2STxDisable +#endif +#ifdef ROM_I2STxDataPut +#define MAP_I2STxDataPut \ + ROM_I2STxDataPut +#else +#define MAP_I2STxDataPut \ + I2STxDataPut +#endif +#ifdef ROM_I2STxDataPutNonBlocking +#define MAP_I2STxDataPutNonBlocking \ + ROM_I2STxDataPutNonBlocking +#else +#define MAP_I2STxDataPutNonBlocking \ + I2STxDataPutNonBlocking +#endif +#ifdef ROM_I2STxConfigSet +#define MAP_I2STxConfigSet \ + ROM_I2STxConfigSet +#else +#define MAP_I2STxConfigSet \ + I2STxConfigSet +#endif +#ifdef ROM_I2STxFIFOLimitSet +#define MAP_I2STxFIFOLimitSet \ + ROM_I2STxFIFOLimitSet +#else +#define MAP_I2STxFIFOLimitSet \ + I2STxFIFOLimitSet +#endif +#ifdef ROM_I2STxFIFOLimitGet +#define MAP_I2STxFIFOLimitGet \ + ROM_I2STxFIFOLimitGet +#else +#define MAP_I2STxFIFOLimitGet \ + I2STxFIFOLimitGet +#endif +#ifdef ROM_I2STxFIFOLevelGet +#define MAP_I2STxFIFOLevelGet \ + ROM_I2STxFIFOLevelGet +#else +#define MAP_I2STxFIFOLevelGet \ + I2STxFIFOLevelGet +#endif +#ifdef ROM_I2SRxEnable +#define MAP_I2SRxEnable \ + ROM_I2SRxEnable +#else +#define MAP_I2SRxEnable \ + I2SRxEnable +#endif +#ifdef ROM_I2SRxDisable +#define MAP_I2SRxDisable \ + ROM_I2SRxDisable +#else +#define MAP_I2SRxDisable \ + I2SRxDisable +#endif +#ifdef ROM_I2SRxDataGet +#define MAP_I2SRxDataGet \ + ROM_I2SRxDataGet +#else +#define MAP_I2SRxDataGet \ + I2SRxDataGet +#endif +#ifdef ROM_I2SRxDataGetNonBlocking +#define MAP_I2SRxDataGetNonBlocking \ + ROM_I2SRxDataGetNonBlocking +#else +#define MAP_I2SRxDataGetNonBlocking \ + I2SRxDataGetNonBlocking +#endif +#ifdef ROM_I2SRxConfigSet +#define MAP_I2SRxConfigSet \ + ROM_I2SRxConfigSet +#else +#define MAP_I2SRxConfigSet \ + I2SRxConfigSet +#endif +#ifdef ROM_I2SRxFIFOLimitSet +#define MAP_I2SRxFIFOLimitSet \ + ROM_I2SRxFIFOLimitSet +#else +#define MAP_I2SRxFIFOLimitSet \ + I2SRxFIFOLimitSet +#endif +#ifdef ROM_I2SRxFIFOLimitGet +#define MAP_I2SRxFIFOLimitGet \ + ROM_I2SRxFIFOLimitGet +#else +#define MAP_I2SRxFIFOLimitGet \ + I2SRxFIFOLimitGet +#endif +#ifdef ROM_I2SRxFIFOLevelGet +#define MAP_I2SRxFIFOLevelGet \ + ROM_I2SRxFIFOLevelGet +#else +#define MAP_I2SRxFIFOLevelGet \ + I2SRxFIFOLevelGet +#endif +#ifdef ROM_I2STxRxEnable +#define MAP_I2STxRxEnable \ + ROM_I2STxRxEnable +#else +#define MAP_I2STxRxEnable \ + I2STxRxEnable +#endif +#ifdef ROM_I2STxRxDisable +#define MAP_I2STxRxDisable \ + ROM_I2STxRxDisable +#else +#define MAP_I2STxRxDisable \ + I2STxRxDisable +#endif +#ifdef ROM_I2STxRxConfigSet +#define MAP_I2STxRxConfigSet \ + ROM_I2STxRxConfigSet +#else +#define MAP_I2STxRxConfigSet \ + I2STxRxConfigSet +#endif +#ifdef ROM_I2SMasterClockSelect +#define MAP_I2SMasterClockSelect \ + ROM_I2SMasterClockSelect +#else +#define MAP_I2SMasterClockSelect \ + I2SMasterClockSelect +#endif +#ifdef ROM_I2SIntEnable +#define MAP_I2SIntEnable \ + ROM_I2SIntEnable +#else +#define MAP_I2SIntEnable \ + I2SIntEnable +#endif +#ifdef ROM_I2SIntDisable +#define MAP_I2SIntDisable \ + ROM_I2SIntDisable +#else +#define MAP_I2SIntDisable \ + I2SIntDisable +#endif +#ifdef ROM_I2SIntClear +#define MAP_I2SIntClear \ + ROM_I2SIntClear +#else +#define MAP_I2SIntClear \ + I2SIntClear +#endif + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif + +//***************************************************************************** +// +// Macros for the LPC API. +// +//***************************************************************************** +#ifdef ROM_LPCIntClear +#define MAP_LPCIntClear \ + ROM_LPCIntClear +#else +#define MAP_LPCIntClear \ + LPCIntClear +#endif +#ifdef ROM_LPCByteRead +#define MAP_LPCByteRead \ + ROM_LPCByteRead +#else +#define MAP_LPCByteRead \ + LPCByteRead +#endif +#ifdef ROM_LPCByteWrite +#define MAP_LPCByteWrite \ + ROM_LPCByteWrite +#else +#define MAP_LPCByteWrite \ + LPCByteWrite +#endif +#ifdef ROM_LPCChannelConfigCOMxSet +#define MAP_LPCChannelConfigCOMxSet \ + ROM_LPCChannelConfigCOMxSet +#else +#define MAP_LPCChannelConfigCOMxSet \ + LPCChannelConfigCOMxSet +#endif +#ifdef ROM_LPCChannelConfigGet +#define MAP_LPCChannelConfigGet \ + ROM_LPCChannelConfigGet +#else +#define MAP_LPCChannelConfigGet \ + LPCChannelConfigGet +#endif +#ifdef ROM_LPCChannelConfigEPSet +#define MAP_LPCChannelConfigEPSet \ + ROM_LPCChannelConfigEPSet +#else +#define MAP_LPCChannelConfigEPSet \ + LPCChannelConfigEPSet +#endif +#ifdef ROM_LPCChannelConfigMBSet +#define MAP_LPCChannelConfigMBSet \ + ROM_LPCChannelConfigMBSet +#else +#define MAP_LPCChannelConfigMBSet \ + LPCChannelConfigMBSet +#endif +#ifdef ROM_LPCChannelDMAConfigGet +#define MAP_LPCChannelDMAConfigGet \ + ROM_LPCChannelDMAConfigGet +#else +#define MAP_LPCChannelDMAConfigGet \ + LPCChannelDMAConfigGet +#endif +#ifdef ROM_LPCChannelDMAConfigSet +#define MAP_LPCChannelDMAConfigSet \ + ROM_LPCChannelDMAConfigSet +#else +#define MAP_LPCChannelDMAConfigSet \ + LPCChannelDMAConfigSet +#endif +#ifdef ROM_LPCChannelDisable +#define MAP_LPCChannelDisable \ + ROM_LPCChannelDisable +#else +#define MAP_LPCChannelDisable \ + LPCChannelDisable +#endif +#ifdef ROM_LPCChannelEnable +#define MAP_LPCChannelEnable \ + ROM_LPCChannelEnable +#else +#define MAP_LPCChannelEnable \ + LPCChannelEnable +#endif +#ifdef ROM_LPCChannelStatusClear +#define MAP_LPCChannelStatusClear \ + ROM_LPCChannelStatusClear +#else +#define MAP_LPCChannelStatusClear \ + LPCChannelStatusClear +#endif +#ifdef ROM_LPCChannelStatusGet +#define MAP_LPCChannelStatusGet \ + ROM_LPCChannelStatusGet +#else +#define MAP_LPCChannelStatusGet \ + LPCChannelStatusGet +#endif +#ifdef ROM_LPCChannelStatusSet +#define MAP_LPCChannelStatusSet \ + ROM_LPCChannelStatusSet +#else +#define MAP_LPCChannelStatusSet \ + LPCChannelStatusSet +#endif +#ifdef ROM_LPCCOMxIntClear +#define MAP_LPCCOMxIntClear \ + ROM_LPCCOMxIntClear +#else +#define MAP_LPCCOMxIntClear \ + LPCCOMxIntClear +#endif +#ifdef ROM_LPCCOMxIntDisable +#define MAP_LPCCOMxIntDisable \ + ROM_LPCCOMxIntDisable +#else +#define MAP_LPCCOMxIntDisable \ + LPCCOMxIntDisable +#endif +#ifdef ROM_LPCCOMxIntEnable +#define MAP_LPCCOMxIntEnable \ + ROM_LPCCOMxIntEnable +#else +#define MAP_LPCCOMxIntEnable \ + LPCCOMxIntEnable +#endif +#ifdef ROM_LPCCOMxIntStatus +#define MAP_LPCCOMxIntStatus \ + ROM_LPCCOMxIntStatus +#else +#define MAP_LPCCOMxIntStatus \ + LPCCOMxIntStatus +#endif +#ifdef ROM_LPCConfigGet +#define MAP_LPCConfigGet \ + ROM_LPCConfigGet +#else +#define MAP_LPCConfigGet \ + LPCConfigGet +#endif +#ifdef ROM_LPCConfigSet +#define MAP_LPCConfigSet \ + ROM_LPCConfigSet +#else +#define MAP_LPCConfigSet \ + LPCConfigSet +#endif +#ifdef ROM_LPCHalfWordRead +#define MAP_LPCHalfWordRead \ + ROM_LPCHalfWordRead +#else +#define MAP_LPCHalfWordRead \ + LPCHalfWordRead +#endif +#ifdef ROM_LPCHalfWordWrite +#define MAP_LPCHalfWordWrite \ + ROM_LPCHalfWordWrite +#else +#define MAP_LPCHalfWordWrite \ + LPCHalfWordWrite +#endif +#ifdef ROM_LPCIRQClear +#define MAP_LPCIRQClear \ + ROM_LPCIRQClear +#else +#define MAP_LPCIRQClear \ + LPCIRQClear +#endif +#ifdef ROM_LPCIRQConfig +#define MAP_LPCIRQConfig \ + ROM_LPCIRQConfig +#else +#define MAP_LPCIRQConfig \ + LPCIRQConfig +#endif +#ifdef ROM_LPCIRQGet +#define MAP_LPCIRQGet \ + ROM_LPCIRQGet +#else +#define MAP_LPCIRQGet \ + LPCIRQGet +#endif +#ifdef ROM_LPCIRQSend +#define MAP_LPCIRQSend \ + ROM_LPCIRQSend +#else +#define MAP_LPCIRQSend \ + LPCIRQSend +#endif +#ifdef ROM_LPCIRQSet +#define MAP_LPCIRQSet \ + ROM_LPCIRQSet +#else +#define MAP_LPCIRQSet \ + LPCIRQSet +#endif +#ifdef ROM_LPCIntDisable +#define MAP_LPCIntDisable \ + ROM_LPCIntDisable +#else +#define MAP_LPCIntDisable \ + LPCIntDisable +#endif +#ifdef ROM_LPCIntEnable +#define MAP_LPCIntEnable \ + ROM_LPCIntEnable +#else +#define MAP_LPCIntEnable \ + LPCIntEnable +#endif +#ifdef ROM_LPCIntStatus +#define MAP_LPCIntStatus \ + ROM_LPCIntStatus +#else +#define MAP_LPCIntStatus \ + LPCIntStatus +#endif +#ifdef ROM_LPCSCIAssert +#define MAP_LPCSCIAssert \ + ROM_LPCSCIAssert +#else +#define MAP_LPCSCIAssert \ + LPCSCIAssert +#endif +#ifdef ROM_LPCStatusGet +#define MAP_LPCStatusGet \ + ROM_LPCStatusGet +#else +#define MAP_LPCStatusGet \ + LPCStatusGet +#endif +#ifdef ROM_LPCWordRead +#define MAP_LPCWordRead \ + ROM_LPCWordRead +#else +#define MAP_LPCWordRead \ + LPCWordRead +#endif +#ifdef ROM_LPCWordWrite +#define MAP_LPCWordWrite \ + ROM_LPCWordWrite +#else +#define MAP_LPCWordWrite \ + LPCWordWrite +#endif +#ifdef ROM_LPCChannelPoolAddressGet +#define MAP_LPCChannelPoolAddressGet \ + ROM_LPCChannelPoolAddressGet +#else +#define MAP_LPCChannelPoolAddressGet \ + LPCChannelPoolAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressGet +#define MAP_LPCStatusBlockAddressGet \ + ROM_LPCStatusBlockAddressGet +#else +#define MAP_LPCStatusBlockAddressGet \ + LPCStatusBlockAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressSet +#define MAP_LPCStatusBlockAddressSet \ + ROM_LPCStatusBlockAddressSet +#else +#define MAP_LPCStatusBlockAddressSet \ + LPCStatusBlockAddressSet +#endif + +//***************************************************************************** +// +// Macros for the MPU API. +// +//***************************************************************************** +#ifdef ROM_MPUEnable +#define MAP_MPUEnable \ + ROM_MPUEnable +#else +#define MAP_MPUEnable \ + MPUEnable +#endif +#ifdef ROM_MPUDisable +#define MAP_MPUDisable \ + ROM_MPUDisable +#else +#define MAP_MPUDisable \ + MPUDisable +#endif +#ifdef ROM_MPURegionCountGet +#define MAP_MPURegionCountGet \ + ROM_MPURegionCountGet +#else +#define MAP_MPURegionCountGet \ + MPURegionCountGet +#endif +#ifdef ROM_MPURegionEnable +#define MAP_MPURegionEnable \ + ROM_MPURegionEnable +#else +#define MAP_MPURegionEnable \ + MPURegionEnable +#endif +#ifdef ROM_MPURegionDisable +#define MAP_MPURegionDisable \ + ROM_MPURegionDisable +#else +#define MAP_MPURegionDisable \ + MPURegionDisable +#endif +#ifdef ROM_MPURegionSet +#define MAP_MPURegionSet \ + ROM_MPURegionSet +#else +#define MAP_MPURegionSet \ + MPURegionSet +#endif +#ifdef ROM_MPURegionGet +#define MAP_MPURegionGet \ + ROM_MPURegionGet +#else +#define MAP_MPURegionGet \ + MPURegionGet +#endif + +//***************************************************************************** +// +// Macros for the PECI API. +// +//***************************************************************************** +#ifdef ROM_PECIIntClear +#define MAP_PECIIntClear \ + ROM_PECIIntClear +#else +#define MAP_PECIIntClear \ + PECIIntClear +#endif +#ifdef ROM_PECIAdvCmdSend +#define MAP_PECIAdvCmdSend \ + ROM_PECIAdvCmdSend +#else +#define MAP_PECIAdvCmdSend \ + PECIAdvCmdSend +#endif +#ifdef ROM_PECIAdvCmdSendNonBlocking +#define MAP_PECIAdvCmdSendNonBlocking \ + ROM_PECIAdvCmdSendNonBlocking +#else +#define MAP_PECIAdvCmdSendNonBlocking \ + PECIAdvCmdSendNonBlocking +#endif +#ifdef ROM_PECIAdvCmdStatusGet +#define MAP_PECIAdvCmdStatusGet \ + ROM_PECIAdvCmdStatusGet +#else +#define MAP_PECIAdvCmdStatusGet \ + PECIAdvCmdStatusGet +#endif +#ifdef ROM_PECIConfigGet +#define MAP_PECIConfigGet \ + ROM_PECIConfigGet +#else +#define MAP_PECIConfigGet \ + PECIConfigGet +#endif +#ifdef ROM_PECIConfigSet +#define MAP_PECIConfigSet \ + ROM_PECIConfigSet +#else +#define MAP_PECIConfigSet \ + PECIConfigSet +#endif +#ifdef ROM_PECIDomainMaxReadClear +#define MAP_PECIDomainMaxReadClear \ + ROM_PECIDomainMaxReadClear +#else +#define MAP_PECIDomainMaxReadClear \ + PECIDomainMaxReadClear +#endif +#ifdef ROM_PECIDomainValueClear +#define MAP_PECIDomainValueClear \ + ROM_PECIDomainValueClear +#else +#define MAP_PECIDomainValueClear \ + PECIDomainValueClear +#endif +#ifdef ROM_PECIDomainConfigGet +#define MAP_PECIDomainConfigGet \ + ROM_PECIDomainConfigGet +#else +#define MAP_PECIDomainConfigGet \ + PECIDomainConfigGet +#endif +#ifdef ROM_PECIDomainConfigSet +#define MAP_PECIDomainConfigSet \ + ROM_PECIDomainConfigSet +#else +#define MAP_PECIDomainConfigSet \ + PECIDomainConfigSet +#endif +#ifdef ROM_PECIDomainDisable +#define MAP_PECIDomainDisable \ + ROM_PECIDomainDisable +#else +#define MAP_PECIDomainDisable \ + PECIDomainDisable +#endif +#ifdef ROM_PECIDomainEnable +#define MAP_PECIDomainEnable \ + ROM_PECIDomainEnable +#else +#define MAP_PECIDomainEnable \ + PECIDomainEnable +#endif +#ifdef ROM_PECIDomainMaxReadGet +#define MAP_PECIDomainMaxReadGet \ + ROM_PECIDomainMaxReadGet +#else +#define MAP_PECIDomainMaxReadGet \ + PECIDomainMaxReadGet +#endif +#ifdef ROM_PECIDomainValueGet +#define MAP_PECIDomainValueGet \ + ROM_PECIDomainValueGet +#else +#define MAP_PECIDomainValueGet \ + PECIDomainValueGet +#endif +#ifdef ROM_PECIIntDisable +#define MAP_PECIIntDisable \ + ROM_PECIIntDisable +#else +#define MAP_PECIIntDisable \ + PECIIntDisable +#endif +#ifdef ROM_PECIIntEnable +#define MAP_PECIIntEnable \ + ROM_PECIIntEnable +#else +#define MAP_PECIIntEnable \ + PECIIntEnable +#endif +#ifdef ROM_PECIIntStatus +#define MAP_PECIIntStatus \ + ROM_PECIIntStatus +#else +#define MAP_PECIIntStatus \ + PECIIntStatus +#endif +#ifdef ROM_PECIBypassEnable +#define MAP_PECIBypassEnable \ + ROM_PECIBypassEnable +#else +#define MAP_PECIBypassEnable \ + PECIBypassEnable +#endif +#ifdef ROM_PECIBypassDisable +#define MAP_PECIBypassDisable \ + ROM_PECIBypassDisable +#else +#define MAP_PECIBypassDisable \ + PECIBypassDisable +#endif + +//***************************************************************************** +// +// Macros for the PWM API. +// +//***************************************************************************** +#ifdef ROM_PWMPulseWidthSet +#define MAP_PWMPulseWidthSet \ + ROM_PWMPulseWidthSet +#else +#define MAP_PWMPulseWidthSet \ + PWMPulseWidthSet +#endif +#ifdef ROM_PWMGenConfigure +#define MAP_PWMGenConfigure \ + ROM_PWMGenConfigure +#else +#define MAP_PWMGenConfigure \ + PWMGenConfigure +#endif +#ifdef ROM_PWMGenPeriodSet +#define MAP_PWMGenPeriodSet \ + ROM_PWMGenPeriodSet +#else +#define MAP_PWMGenPeriodSet \ + PWMGenPeriodSet +#endif +#ifdef ROM_PWMGenPeriodGet +#define MAP_PWMGenPeriodGet \ + ROM_PWMGenPeriodGet +#else +#define MAP_PWMGenPeriodGet \ + PWMGenPeriodGet +#endif +#ifdef ROM_PWMGenEnable +#define MAP_PWMGenEnable \ + ROM_PWMGenEnable +#else +#define MAP_PWMGenEnable \ + PWMGenEnable +#endif +#ifdef ROM_PWMGenDisable +#define MAP_PWMGenDisable \ + ROM_PWMGenDisable +#else +#define MAP_PWMGenDisable \ + PWMGenDisable +#endif +#ifdef ROM_PWMPulseWidthGet +#define MAP_PWMPulseWidthGet \ + ROM_PWMPulseWidthGet +#else +#define MAP_PWMPulseWidthGet \ + PWMPulseWidthGet +#endif +#ifdef ROM_PWMDeadBandEnable +#define MAP_PWMDeadBandEnable \ + ROM_PWMDeadBandEnable +#else +#define MAP_PWMDeadBandEnable \ + PWMDeadBandEnable +#endif +#ifdef ROM_PWMDeadBandDisable +#define MAP_PWMDeadBandDisable \ + ROM_PWMDeadBandDisable +#else +#define MAP_PWMDeadBandDisable \ + PWMDeadBandDisable +#endif +#ifdef ROM_PWMSyncUpdate +#define MAP_PWMSyncUpdate \ + ROM_PWMSyncUpdate +#else +#define MAP_PWMSyncUpdate \ + PWMSyncUpdate +#endif +#ifdef ROM_PWMSyncTimeBase +#define MAP_PWMSyncTimeBase \ + ROM_PWMSyncTimeBase +#else +#define MAP_PWMSyncTimeBase \ + PWMSyncTimeBase +#endif +#ifdef ROM_PWMOutputState +#define MAP_PWMOutputState \ + ROM_PWMOutputState +#else +#define MAP_PWMOutputState \ + PWMOutputState +#endif +#ifdef ROM_PWMOutputInvert +#define MAP_PWMOutputInvert \ + ROM_PWMOutputInvert +#else +#define MAP_PWMOutputInvert \ + PWMOutputInvert +#endif +#ifdef ROM_PWMOutputFault +#define MAP_PWMOutputFault \ + ROM_PWMOutputFault +#else +#define MAP_PWMOutputFault \ + PWMOutputFault +#endif +#ifdef ROM_PWMGenIntTrigEnable +#define MAP_PWMGenIntTrigEnable \ + ROM_PWMGenIntTrigEnable +#else +#define MAP_PWMGenIntTrigEnable \ + PWMGenIntTrigEnable +#endif +#ifdef ROM_PWMGenIntTrigDisable +#define MAP_PWMGenIntTrigDisable \ + ROM_PWMGenIntTrigDisable +#else +#define MAP_PWMGenIntTrigDisable \ + PWMGenIntTrigDisable +#endif +#ifdef ROM_PWMGenIntStatus +#define MAP_PWMGenIntStatus \ + ROM_PWMGenIntStatus +#else +#define MAP_PWMGenIntStatus \ + PWMGenIntStatus +#endif +#ifdef ROM_PWMGenIntClear +#define MAP_PWMGenIntClear \ + ROM_PWMGenIntClear +#else +#define MAP_PWMGenIntClear \ + PWMGenIntClear +#endif +#ifdef ROM_PWMIntEnable +#define MAP_PWMIntEnable \ + ROM_PWMIntEnable +#else +#define MAP_PWMIntEnable \ + PWMIntEnable +#endif +#ifdef ROM_PWMIntDisable +#define MAP_PWMIntDisable \ + ROM_PWMIntDisable +#else +#define MAP_PWMIntDisable \ + PWMIntDisable +#endif +#ifdef ROM_PWMFaultIntClear +#define MAP_PWMFaultIntClear \ + ROM_PWMFaultIntClear +#else +#define MAP_PWMFaultIntClear \ + PWMFaultIntClear +#endif +#ifdef ROM_PWMIntStatus +#define MAP_PWMIntStatus \ + ROM_PWMIntStatus +#else +#define MAP_PWMIntStatus \ + PWMIntStatus +#endif +#ifdef ROM_PWMOutputFaultLevel +#define MAP_PWMOutputFaultLevel \ + ROM_PWMOutputFaultLevel +#else +#define MAP_PWMOutputFaultLevel \ + PWMOutputFaultLevel +#endif +#ifdef ROM_PWMFaultIntClearExt +#define MAP_PWMFaultIntClearExt \ + ROM_PWMFaultIntClearExt +#else +#define MAP_PWMFaultIntClearExt \ + PWMFaultIntClearExt +#endif +#ifdef ROM_PWMGenFaultConfigure +#define MAP_PWMGenFaultConfigure \ + ROM_PWMGenFaultConfigure +#else +#define MAP_PWMGenFaultConfigure \ + PWMGenFaultConfigure +#endif +#ifdef ROM_PWMGenFaultTriggerSet +#define MAP_PWMGenFaultTriggerSet \ + ROM_PWMGenFaultTriggerSet +#else +#define MAP_PWMGenFaultTriggerSet \ + PWMGenFaultTriggerSet +#endif +#ifdef ROM_PWMGenFaultTriggerGet +#define MAP_PWMGenFaultTriggerGet \ + ROM_PWMGenFaultTriggerGet +#else +#define MAP_PWMGenFaultTriggerGet \ + PWMGenFaultTriggerGet +#endif +#ifdef ROM_PWMGenFaultStatus +#define MAP_PWMGenFaultStatus \ + ROM_PWMGenFaultStatus +#else +#define MAP_PWMGenFaultStatus \ + PWMGenFaultStatus +#endif +#ifdef ROM_PWMGenFaultClear +#define MAP_PWMGenFaultClear \ + ROM_PWMGenFaultClear +#else +#define MAP_PWMGenFaultClear \ + PWMGenFaultClear +#endif + +//***************************************************************************** +// +// Macros for the QEI API. +// +//***************************************************************************** +#ifdef ROM_QEIPositionGet +#define MAP_QEIPositionGet \ + ROM_QEIPositionGet +#else +#define MAP_QEIPositionGet \ + QEIPositionGet +#endif +#ifdef ROM_QEIEnable +#define MAP_QEIEnable \ + ROM_QEIEnable +#else +#define MAP_QEIEnable \ + QEIEnable +#endif +#ifdef ROM_QEIDisable +#define MAP_QEIDisable \ + ROM_QEIDisable +#else +#define MAP_QEIDisable \ + QEIDisable +#endif +#ifdef ROM_QEIConfigure +#define MAP_QEIConfigure \ + ROM_QEIConfigure +#else +#define MAP_QEIConfigure \ + QEIConfigure +#endif +#ifdef ROM_QEIPositionSet +#define MAP_QEIPositionSet \ + ROM_QEIPositionSet +#else +#define MAP_QEIPositionSet \ + QEIPositionSet +#endif +#ifdef ROM_QEIDirectionGet +#define MAP_QEIDirectionGet \ + ROM_QEIDirectionGet +#else +#define MAP_QEIDirectionGet \ + QEIDirectionGet +#endif +#ifdef ROM_QEIErrorGet +#define MAP_QEIErrorGet \ + ROM_QEIErrorGet +#else +#define MAP_QEIErrorGet \ + QEIErrorGet +#endif +#ifdef ROM_QEIVelocityEnable +#define MAP_QEIVelocityEnable \ + ROM_QEIVelocityEnable +#else +#define MAP_QEIVelocityEnable \ + QEIVelocityEnable +#endif +#ifdef ROM_QEIVelocityDisable +#define MAP_QEIVelocityDisable \ + ROM_QEIVelocityDisable +#else +#define MAP_QEIVelocityDisable \ + QEIVelocityDisable +#endif +#ifdef ROM_QEIVelocityConfigure +#define MAP_QEIVelocityConfigure \ + ROM_QEIVelocityConfigure +#else +#define MAP_QEIVelocityConfigure \ + QEIVelocityConfigure +#endif +#ifdef ROM_QEIVelocityGet +#define MAP_QEIVelocityGet \ + ROM_QEIVelocityGet +#else +#define MAP_QEIVelocityGet \ + QEIVelocityGet +#endif +#ifdef ROM_QEIIntEnable +#define MAP_QEIIntEnable \ + ROM_QEIIntEnable +#else +#define MAP_QEIIntEnable \ + QEIIntEnable +#endif +#ifdef ROM_QEIIntDisable +#define MAP_QEIIntDisable \ + ROM_QEIIntDisable +#else +#define MAP_QEIIntDisable \ + QEIIntDisable +#endif +#ifdef ROM_QEIIntStatus +#define MAP_QEIIntStatus \ + ROM_QEIIntStatus +#else +#define MAP_QEIIntStatus \ + QEIIntStatus +#endif +#ifdef ROM_QEIIntClear +#define MAP_QEIIntClear \ + ROM_QEIIntClear +#else +#define MAP_QEIIntClear \ + QEIIntClear +#endif + +//***************************************************************************** +// +// Macros for the SMBus API. +// +//***************************************************************************** +#ifdef ROM_SMBusMasterIntProcess +#define MAP_SMBusMasterIntProcess \ + ROM_SMBusMasterIntProcess +#else +#define MAP_SMBusMasterIntProcess \ + SMBusMasterIntProcess +#endif +#ifdef ROM_SMBusARPDisable +#define MAP_SMBusARPDisable \ + ROM_SMBusARPDisable +#else +#define MAP_SMBusARPDisable \ + SMBusARPDisable +#endif +#ifdef ROM_SMBusARPEnable +#define MAP_SMBusARPEnable \ + ROM_SMBusARPEnable +#else +#define MAP_SMBusARPEnable \ + SMBusARPEnable +#endif +#ifdef ROM_SMBusARPUDIDPacketDecode +#define MAP_SMBusARPUDIDPacketDecode \ + ROM_SMBusARPUDIDPacketDecode +#else +#define MAP_SMBusARPUDIDPacketDecode \ + SMBusARPUDIDPacketDecode +#endif +#ifdef ROM_SMBusARPUDIDPacketEncode +#define MAP_SMBusARPUDIDPacketEncode \ + ROM_SMBusARPUDIDPacketEncode +#else +#define MAP_SMBusARPUDIDPacketEncode \ + SMBusARPUDIDPacketEncode +#endif +#ifdef ROM_SMBusMasterARPAssignAddress +#define MAP_SMBusMasterARPAssignAddress \ + ROM_SMBusMasterARPAssignAddress +#else +#define MAP_SMBusMasterARPAssignAddress \ + SMBusMasterARPAssignAddress +#endif +#ifdef ROM_SMBusMasterARPGetUDIDDir +#define MAP_SMBusMasterARPGetUDIDDir \ + ROM_SMBusMasterARPGetUDIDDir +#else +#define MAP_SMBusMasterARPGetUDIDDir \ + SMBusMasterARPGetUDIDDir +#endif +#ifdef ROM_SMBusMasterARPGetUDIDGen +#define MAP_SMBusMasterARPGetUDIDGen \ + ROM_SMBusMasterARPGetUDIDGen +#else +#define MAP_SMBusMasterARPGetUDIDGen \ + SMBusMasterARPGetUDIDGen +#endif +#ifdef ROM_SMBusMasterARPNotifyMaster +#define MAP_SMBusMasterARPNotifyMaster \ + ROM_SMBusMasterARPNotifyMaster +#else +#define MAP_SMBusMasterARPNotifyMaster \ + SMBusMasterARPNotifyMaster +#endif +#ifdef ROM_SMBusMasterARPPrepareToARP +#define MAP_SMBusMasterARPPrepareToARP \ + ROM_SMBusMasterARPPrepareToARP +#else +#define MAP_SMBusMasterARPPrepareToARP \ + SMBusMasterARPPrepareToARP +#endif +#ifdef ROM_SMBusMasterARPResetDeviceDir +#define MAP_SMBusMasterARPResetDeviceDir \ + ROM_SMBusMasterARPResetDeviceDir +#else +#define MAP_SMBusMasterARPResetDeviceDir \ + SMBusMasterARPResetDeviceDir +#endif +#ifdef ROM_SMBusMasterARPResetDeviceGen +#define MAP_SMBusMasterARPResetDeviceGen \ + ROM_SMBusMasterARPResetDeviceGen +#else +#define MAP_SMBusMasterARPResetDeviceGen \ + SMBusMasterARPResetDeviceGen +#endif +#ifdef ROM_SMBusMasterBlockProcessCall +#define MAP_SMBusMasterBlockProcessCall \ + ROM_SMBusMasterBlockProcessCall +#else +#define MAP_SMBusMasterBlockProcessCall \ + SMBusMasterBlockProcessCall +#endif +#ifdef ROM_SMBusMasterBlockRead +#define MAP_SMBusMasterBlockRead \ + ROM_SMBusMasterBlockRead +#else +#define MAP_SMBusMasterBlockRead \ + SMBusMasterBlockRead +#endif +#ifdef ROM_SMBusMasterBlockWrite +#define MAP_SMBusMasterBlockWrite \ + ROM_SMBusMasterBlockWrite +#else +#define MAP_SMBusMasterBlockWrite \ + SMBusMasterBlockWrite +#endif +#ifdef ROM_SMBusMasterByteReceive +#define MAP_SMBusMasterByteReceive \ + ROM_SMBusMasterByteReceive +#else +#define MAP_SMBusMasterByteReceive \ + SMBusMasterByteReceive +#endif +#ifdef ROM_SMBusMasterByteSend +#define MAP_SMBusMasterByteSend \ + ROM_SMBusMasterByteSend +#else +#define MAP_SMBusMasterByteSend \ + SMBusMasterByteSend +#endif +#ifdef ROM_SMBusMasterByteWordRead +#define MAP_SMBusMasterByteWordRead \ + ROM_SMBusMasterByteWordRead +#else +#define MAP_SMBusMasterByteWordRead \ + SMBusMasterByteWordRead +#endif +#ifdef ROM_SMBusMasterByteWordWrite +#define MAP_SMBusMasterByteWordWrite \ + ROM_SMBusMasterByteWordWrite +#else +#define MAP_SMBusMasterByteWordWrite \ + SMBusMasterByteWordWrite +#endif +#ifdef ROM_SMBusMasterHostNotify +#define MAP_SMBusMasterHostNotify \ + ROM_SMBusMasterHostNotify +#else +#define MAP_SMBusMasterHostNotify \ + SMBusMasterHostNotify +#endif +#ifdef ROM_SMBusMasterI2CRead +#define MAP_SMBusMasterI2CRead \ + ROM_SMBusMasterI2CRead +#else +#define MAP_SMBusMasterI2CRead \ + SMBusMasterI2CRead +#endif +#ifdef ROM_SMBusMasterI2CWrite +#define MAP_SMBusMasterI2CWrite \ + ROM_SMBusMasterI2CWrite +#else +#define MAP_SMBusMasterI2CWrite \ + SMBusMasterI2CWrite +#endif +#ifdef ROM_SMBusMasterI2CWriteRead +#define MAP_SMBusMasterI2CWriteRead \ + ROM_SMBusMasterI2CWriteRead +#else +#define MAP_SMBusMasterI2CWriteRead \ + SMBusMasterI2CWriteRead +#endif +#ifdef ROM_SMBusMasterInit +#define MAP_SMBusMasterInit \ + ROM_SMBusMasterInit +#else +#define MAP_SMBusMasterInit \ + SMBusMasterInit +#endif +#ifdef ROM_SMBusMasterIntEnable +#define MAP_SMBusMasterIntEnable \ + ROM_SMBusMasterIntEnable +#else +#define MAP_SMBusMasterIntEnable \ + SMBusMasterIntEnable +#endif +#ifdef ROM_SMBusMasterProcessCall +#define MAP_SMBusMasterProcessCall \ + ROM_SMBusMasterProcessCall +#else +#define MAP_SMBusMasterProcessCall \ + SMBusMasterProcessCall +#endif +#ifdef ROM_SMBusMasterQuickCommand +#define MAP_SMBusMasterQuickCommand \ + ROM_SMBusMasterQuickCommand +#else +#define MAP_SMBusMasterQuickCommand \ + SMBusMasterQuickCommand +#endif +#ifdef ROM_SMBusPECDisable +#define MAP_SMBusPECDisable \ + ROM_SMBusPECDisable +#else +#define MAP_SMBusPECDisable \ + SMBusPECDisable +#endif +#ifdef ROM_SMBusPECEnable +#define MAP_SMBusPECEnable \ + ROM_SMBusPECEnable +#else +#define MAP_SMBusPECEnable \ + SMBusPECEnable +#endif +#ifdef ROM_SMBusRxPacketSizeGet +#define MAP_SMBusRxPacketSizeGet \ + ROM_SMBusRxPacketSizeGet +#else +#define MAP_SMBusRxPacketSizeGet \ + SMBusRxPacketSizeGet +#endif +#ifdef ROM_SMBusSlaveACKSend +#define MAP_SMBusSlaveACKSend \ + ROM_SMBusSlaveACKSend +#else +#define MAP_SMBusSlaveACKSend \ + SMBusSlaveACKSend +#endif +#ifdef ROM_SMBusSlaveAddressSet +#define MAP_SMBusSlaveAddressSet \ + ROM_SMBusSlaveAddressSet +#else +#define MAP_SMBusSlaveAddressSet \ + SMBusSlaveAddressSet +#endif +#ifdef ROM_SMBusSlaveARPFlagARGet +#define MAP_SMBusSlaveARPFlagARGet \ + ROM_SMBusSlaveARPFlagARGet +#else +#define MAP_SMBusSlaveARPFlagARGet \ + SMBusSlaveARPFlagARGet +#endif +#ifdef ROM_SMBusSlaveARPFlagARSet +#define MAP_SMBusSlaveARPFlagARSet \ + ROM_SMBusSlaveARPFlagARSet +#else +#define MAP_SMBusSlaveARPFlagARSet \ + SMBusSlaveARPFlagARSet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVGet +#define MAP_SMBusSlaveARPFlagAVGet \ + ROM_SMBusSlaveARPFlagAVGet +#else +#define MAP_SMBusSlaveARPFlagAVGet \ + SMBusSlaveARPFlagAVGet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVSet +#define MAP_SMBusSlaveARPFlagAVSet \ + ROM_SMBusSlaveARPFlagAVSet +#else +#define MAP_SMBusSlaveARPFlagAVSet \ + SMBusSlaveARPFlagAVSet +#endif +#ifdef ROM_SMBusSlaveBlockTransferDisable +#define MAP_SMBusSlaveBlockTransferDisable \ + ROM_SMBusSlaveBlockTransferDisable +#else +#define MAP_SMBusSlaveBlockTransferDisable \ + SMBusSlaveBlockTransferDisable +#endif +#ifdef ROM_SMBusSlaveBlockTransferEnable +#define MAP_SMBusSlaveBlockTransferEnable \ + ROM_SMBusSlaveBlockTransferEnable +#else +#define MAP_SMBusSlaveBlockTransferEnable \ + SMBusSlaveBlockTransferEnable +#endif +#ifdef ROM_SMBusSlaveCommandGet +#define MAP_SMBusSlaveCommandGet \ + ROM_SMBusSlaveCommandGet +#else +#define MAP_SMBusSlaveCommandGet \ + SMBusSlaveCommandGet +#endif +#ifdef ROM_SMBusSlaveI2CDisable +#define MAP_SMBusSlaveI2CDisable \ + ROM_SMBusSlaveI2CDisable +#else +#define MAP_SMBusSlaveI2CDisable \ + SMBusSlaveI2CDisable +#endif +#ifdef ROM_SMBusSlaveI2CEnable +#define MAP_SMBusSlaveI2CEnable \ + ROM_SMBusSlaveI2CEnable +#else +#define MAP_SMBusSlaveI2CEnable \ + SMBusSlaveI2CEnable +#endif +#ifdef ROM_SMBusSlaveInit +#define MAP_SMBusSlaveInit \ + ROM_SMBusSlaveInit +#else +#define MAP_SMBusSlaveInit \ + SMBusSlaveInit +#endif +#ifdef ROM_SMBusSlaveIntAddressGet +#define MAP_SMBusSlaveIntAddressGet \ + ROM_SMBusSlaveIntAddressGet +#else +#define MAP_SMBusSlaveIntAddressGet \ + SMBusSlaveIntAddressGet +#endif +#ifdef ROM_SMBusSlaveIntEnable +#define MAP_SMBusSlaveIntEnable \ + ROM_SMBusSlaveIntEnable +#else +#define MAP_SMBusSlaveIntEnable \ + SMBusSlaveIntEnable +#endif +#ifdef ROM_SMBusSlaveIntProcess +#define MAP_SMBusSlaveIntProcess \ + ROM_SMBusSlaveIntProcess +#else +#define MAP_SMBusSlaveIntProcess \ + SMBusSlaveIntProcess +#endif +#ifdef ROM_SMBusSlaveManualACKDisable +#define MAP_SMBusSlaveManualACKDisable \ + ROM_SMBusSlaveManualACKDisable +#else +#define MAP_SMBusSlaveManualACKDisable \ + SMBusSlaveManualACKDisable +#endif +#ifdef ROM_SMBusSlaveManualACKEnable +#define MAP_SMBusSlaveManualACKEnable \ + ROM_SMBusSlaveManualACKEnable +#else +#define MAP_SMBusSlaveManualACKEnable \ + SMBusSlaveManualACKEnable +#endif +#ifdef ROM_SMBusSlaveManualACKStatusGet +#define MAP_SMBusSlaveManualACKStatusGet \ + ROM_SMBusSlaveManualACKStatusGet +#else +#define MAP_SMBusSlaveManualACKStatusGet \ + SMBusSlaveManualACKStatusGet +#endif +#ifdef ROM_SMBusSlaveProcessCallDisable +#define MAP_SMBusSlaveProcessCallDisable \ + ROM_SMBusSlaveProcessCallDisable +#else +#define MAP_SMBusSlaveProcessCallDisable \ + SMBusSlaveProcessCallDisable +#endif +#ifdef ROM_SMBusSlaveProcessCallEnable +#define MAP_SMBusSlaveProcessCallEnable \ + ROM_SMBusSlaveProcessCallEnable +#else +#define MAP_SMBusSlaveProcessCallEnable \ + SMBusSlaveProcessCallEnable +#endif +#ifdef ROM_SMBusSlaveRxBufferSet +#define MAP_SMBusSlaveRxBufferSet \ + ROM_SMBusSlaveRxBufferSet +#else +#define MAP_SMBusSlaveRxBufferSet \ + SMBusSlaveRxBufferSet +#endif +#ifdef ROM_SMBusSlaveTransferInit +#define MAP_SMBusSlaveTransferInit \ + ROM_SMBusSlaveTransferInit +#else +#define MAP_SMBusSlaveTransferInit \ + SMBusSlaveTransferInit +#endif +#ifdef ROM_SMBusSlaveTxBufferSet +#define MAP_SMBusSlaveTxBufferSet \ + ROM_SMBusSlaveTxBufferSet +#else +#define MAP_SMBusSlaveTxBufferSet \ + SMBusSlaveTxBufferSet +#endif +#ifdef ROM_SMBusSlaveUDIDSet +#define MAP_SMBusSlaveUDIDSet \ + ROM_SMBusSlaveUDIDSet +#else +#define MAP_SMBusSlaveUDIDSet \ + SMBusSlaveUDIDSet +#endif +#ifdef ROM_SMBusStatusGet +#define MAP_SMBusStatusGet \ + ROM_SMBusStatusGet +#else +#define MAP_SMBusStatusGet \ + SMBusStatusGet +#endif +#ifdef ROM_SMBusSlaveDataSend +#define MAP_SMBusSlaveDataSend \ + ROM_SMBusSlaveDataSend +#else +#define MAP_SMBusSlaveDataSend \ + SMBusSlaveDataSend +#endif + +//***************************************************************************** +// +// Macros for the SSI API. +// +//***************************************************************************** +#ifdef ROM_SSIDataPut +#define MAP_SSIDataPut \ + ROM_SSIDataPut +#else +#define MAP_SSIDataPut \ + SSIDataPut +#endif +#ifdef ROM_SSIConfigSetExpClk +#define MAP_SSIConfigSetExpClk \ + ROM_SSIConfigSetExpClk +#else +#define MAP_SSIConfigSetExpClk \ + SSIConfigSetExpClk +#endif +#ifdef ROM_SSIEnable +#define MAP_SSIEnable \ + ROM_SSIEnable +#else +#define MAP_SSIEnable \ + SSIEnable +#endif +#ifdef ROM_SSIDisable +#define MAP_SSIDisable \ + ROM_SSIDisable +#else +#define MAP_SSIDisable \ + SSIDisable +#endif +#ifdef ROM_SSIIntEnable +#define MAP_SSIIntEnable \ + ROM_SSIIntEnable +#else +#define MAP_SSIIntEnable \ + SSIIntEnable +#endif +#ifdef ROM_SSIIntDisable +#define MAP_SSIIntDisable \ + ROM_SSIIntDisable +#else +#define MAP_SSIIntDisable \ + SSIIntDisable +#endif +#ifdef ROM_SSIIntStatus +#define MAP_SSIIntStatus \ + ROM_SSIIntStatus +#else +#define MAP_SSIIntStatus \ + SSIIntStatus +#endif +#ifdef ROM_SSIIntClear +#define MAP_SSIIntClear \ + ROM_SSIIntClear +#else +#define MAP_SSIIntClear \ + SSIIntClear +#endif +#ifdef ROM_SSIDataPutNonBlocking +#define MAP_SSIDataPutNonBlocking \ + ROM_SSIDataPutNonBlocking +#else +#define MAP_SSIDataPutNonBlocking \ + SSIDataPutNonBlocking +#endif +#ifdef ROM_SSIDataGet +#define MAP_SSIDataGet \ + ROM_SSIDataGet +#else +#define MAP_SSIDataGet \ + SSIDataGet +#endif +#ifdef ROM_SSIDataGetNonBlocking +#define MAP_SSIDataGetNonBlocking \ + ROM_SSIDataGetNonBlocking +#else +#define MAP_SSIDataGetNonBlocking \ + SSIDataGetNonBlocking +#endif +#ifdef ROM_SSIDMAEnable +#define MAP_SSIDMAEnable \ + ROM_SSIDMAEnable +#else +#define MAP_SSIDMAEnable \ + SSIDMAEnable +#endif +#ifdef ROM_SSIDMADisable +#define MAP_SSIDMADisable \ + ROM_SSIDMADisable +#else +#define MAP_SSIDMADisable \ + SSIDMADisable +#endif +#ifdef ROM_SSIBusy +#define MAP_SSIBusy \ + ROM_SSIBusy +#else +#define MAP_SSIBusy \ + SSIBusy +#endif +#ifdef ROM_SSIClockSourceGet +#define MAP_SSIClockSourceGet \ + ROM_SSIClockSourceGet +#else +#define MAP_SSIClockSourceGet \ + SSIClockSourceGet +#endif +#ifdef ROM_SSIClockSourceSet +#define MAP_SSIClockSourceSet \ + ROM_SSIClockSourceSet +#else +#define MAP_SSIClockSourceSet \ + SSIClockSourceSet +#endif + +//***************************************************************************** +// +// Macros for the SysCtl API. +// +//***************************************************************************** +#ifdef ROM_SysCtlSleep +#define MAP_SysCtlSleep \ + ROM_SysCtlSleep +#else +#define MAP_SysCtlSleep \ + SysCtlSleep +#endif +#ifdef ROM_SysCtlSRAMSizeGet +#define MAP_SysCtlSRAMSizeGet \ + ROM_SysCtlSRAMSizeGet +#else +#define MAP_SysCtlSRAMSizeGet \ + SysCtlSRAMSizeGet +#endif +#ifdef ROM_SysCtlFlashSizeGet +#define MAP_SysCtlFlashSizeGet \ + ROM_SysCtlFlashSizeGet +#else +#define MAP_SysCtlFlashSizeGet \ + SysCtlFlashSizeGet +#endif +#ifdef ROM_SysCtlPinPresent +#define MAP_SysCtlPinPresent \ + ROM_SysCtlPinPresent +#else +#define MAP_SysCtlPinPresent \ + SysCtlPinPresent +#endif +#ifdef ROM_SysCtlPeripheralPresent +#define MAP_SysCtlPeripheralPresent \ + ROM_SysCtlPeripheralPresent +#else +#define MAP_SysCtlPeripheralPresent \ + SysCtlPeripheralPresent +#endif +#ifdef ROM_SysCtlPeripheralReset +#define MAP_SysCtlPeripheralReset \ + ROM_SysCtlPeripheralReset +#else +#define MAP_SysCtlPeripheralReset \ + SysCtlPeripheralReset +#endif +#ifdef ROM_SysCtlPeripheralEnable +#define MAP_SysCtlPeripheralEnable \ + ROM_SysCtlPeripheralEnable +#else +#define MAP_SysCtlPeripheralEnable \ + SysCtlPeripheralEnable +#endif +#ifdef ROM_SysCtlPeripheralDisable +#define MAP_SysCtlPeripheralDisable \ + ROM_SysCtlPeripheralDisable +#else +#define MAP_SysCtlPeripheralDisable \ + SysCtlPeripheralDisable +#endif +#ifdef ROM_SysCtlPeripheralSleepEnable +#define MAP_SysCtlPeripheralSleepEnable \ + ROM_SysCtlPeripheralSleepEnable +#else +#define MAP_SysCtlPeripheralSleepEnable \ + SysCtlPeripheralSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralSleepDisable +#define MAP_SysCtlPeripheralSleepDisable \ + ROM_SysCtlPeripheralSleepDisable +#else +#define MAP_SysCtlPeripheralSleepDisable \ + SysCtlPeripheralSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepEnable +#define MAP_SysCtlPeripheralDeepSleepEnable \ + ROM_SysCtlPeripheralDeepSleepEnable +#else +#define MAP_SysCtlPeripheralDeepSleepEnable \ + SysCtlPeripheralDeepSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepDisable +#define MAP_SysCtlPeripheralDeepSleepDisable \ + ROM_SysCtlPeripheralDeepSleepDisable +#else +#define MAP_SysCtlPeripheralDeepSleepDisable \ + SysCtlPeripheralDeepSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralClockGating +#define MAP_SysCtlPeripheralClockGating \ + ROM_SysCtlPeripheralClockGating +#else +#define MAP_SysCtlPeripheralClockGating \ + SysCtlPeripheralClockGating +#endif +#ifdef ROM_SysCtlIntEnable +#define MAP_SysCtlIntEnable \ + ROM_SysCtlIntEnable +#else +#define MAP_SysCtlIntEnable \ + SysCtlIntEnable +#endif +#ifdef ROM_SysCtlIntDisable +#define MAP_SysCtlIntDisable \ + ROM_SysCtlIntDisable +#else +#define MAP_SysCtlIntDisable \ + SysCtlIntDisable +#endif +#ifdef ROM_SysCtlIntClear +#define MAP_SysCtlIntClear \ + ROM_SysCtlIntClear +#else +#define MAP_SysCtlIntClear \ + SysCtlIntClear +#endif +#ifdef ROM_SysCtlIntStatus +#define MAP_SysCtlIntStatus \ + ROM_SysCtlIntStatus +#else +#define MAP_SysCtlIntStatus \ + SysCtlIntStatus +#endif +#ifdef ROM_SysCtlLDOSet +#define MAP_SysCtlLDOSet \ + ROM_SysCtlLDOSet +#else +#define MAP_SysCtlLDOSet \ + SysCtlLDOSet +#endif +#ifdef ROM_SysCtlLDOGet +#define MAP_SysCtlLDOGet \ + ROM_SysCtlLDOGet +#else +#define MAP_SysCtlLDOGet \ + SysCtlLDOGet +#endif +#ifdef ROM_SysCtlReset +#define MAP_SysCtlReset \ + ROM_SysCtlReset +#else +#define MAP_SysCtlReset \ + SysCtlReset +#endif +#ifdef ROM_SysCtlDeepSleep +#define MAP_SysCtlDeepSleep \ + ROM_SysCtlDeepSleep +#else +#define MAP_SysCtlDeepSleep \ + SysCtlDeepSleep +#endif +#ifdef ROM_SysCtlResetCauseGet +#define MAP_SysCtlResetCauseGet \ + ROM_SysCtlResetCauseGet +#else +#define MAP_SysCtlResetCauseGet \ + SysCtlResetCauseGet +#endif +#ifdef ROM_SysCtlResetCauseClear +#define MAP_SysCtlResetCauseClear \ + ROM_SysCtlResetCauseClear +#else +#define MAP_SysCtlResetCauseClear \ + SysCtlResetCauseClear +#endif +#ifdef ROM_SysCtlClockSet +#define MAP_SysCtlClockSet \ + ROM_SysCtlClockSet +#else +#define MAP_SysCtlClockSet \ + SysCtlClockSet +#endif +#ifdef ROM_SysCtlClockGet +#define MAP_SysCtlClockGet \ + ROM_SysCtlClockGet +#else +#define MAP_SysCtlClockGet \ + SysCtlClockGet +#endif +#ifdef ROM_SysCtlPWMClockSet +#define MAP_SysCtlPWMClockSet \ + ROM_SysCtlPWMClockSet +#else +#define MAP_SysCtlPWMClockSet \ + SysCtlPWMClockSet +#endif +#ifdef ROM_SysCtlPWMClockGet +#define MAP_SysCtlPWMClockGet \ + ROM_SysCtlPWMClockGet +#else +#define MAP_SysCtlPWMClockGet \ + SysCtlPWMClockGet +#endif +#ifdef ROM_SysCtlADCSpeedSet +#define MAP_SysCtlADCSpeedSet \ + ROM_SysCtlADCSpeedSet +#else +#define MAP_SysCtlADCSpeedSet \ + SysCtlADCSpeedSet +#endif +#ifdef ROM_SysCtlADCSpeedGet +#define MAP_SysCtlADCSpeedGet \ + ROM_SysCtlADCSpeedGet +#else +#define MAP_SysCtlADCSpeedGet \ + SysCtlADCSpeedGet +#endif +#ifdef ROM_SysCtlGPIOAHBEnable +#define MAP_SysCtlGPIOAHBEnable \ + ROM_SysCtlGPIOAHBEnable +#else +#define MAP_SysCtlGPIOAHBEnable \ + SysCtlGPIOAHBEnable +#endif +#ifdef ROM_SysCtlGPIOAHBDisable +#define MAP_SysCtlGPIOAHBDisable \ + ROM_SysCtlGPIOAHBDisable +#else +#define MAP_SysCtlGPIOAHBDisable \ + SysCtlGPIOAHBDisable +#endif +#ifdef ROM_SysCtlUSBPLLEnable +#define MAP_SysCtlUSBPLLEnable \ + ROM_SysCtlUSBPLLEnable +#else +#define MAP_SysCtlUSBPLLEnable \ + SysCtlUSBPLLEnable +#endif +#ifdef ROM_SysCtlUSBPLLDisable +#define MAP_SysCtlUSBPLLDisable \ + ROM_SysCtlUSBPLLDisable +#else +#define MAP_SysCtlUSBPLLDisable \ + SysCtlUSBPLLDisable +#endif +#ifdef ROM_SysCtlI2SMClkSet +#define MAP_SysCtlI2SMClkSet \ + ROM_SysCtlI2SMClkSet +#else +#define MAP_SysCtlI2SMClkSet \ + SysCtlI2SMClkSet +#endif +#ifdef ROM_SysCtlDelay +#define MAP_SysCtlDelay \ + ROM_SysCtlDelay +#else +#define MAP_SysCtlDelay \ + SysCtlDelay +#endif +#ifdef ROM_SysCtlPeripheralReady +#define MAP_SysCtlPeripheralReady \ + ROM_SysCtlPeripheralReady +#else +#define MAP_SysCtlPeripheralReady \ + SysCtlPeripheralReady +#endif +#ifdef ROM_SysCtlPeripheralPowerOn +#define MAP_SysCtlPeripheralPowerOn \ + ROM_SysCtlPeripheralPowerOn +#else +#define MAP_SysCtlPeripheralPowerOn \ + SysCtlPeripheralPowerOn +#endif +#ifdef ROM_SysCtlPeripheralPowerOff +#define MAP_SysCtlPeripheralPowerOff \ + ROM_SysCtlPeripheralPowerOff +#else +#define MAP_SysCtlPeripheralPowerOff \ + SysCtlPeripheralPowerOff +#endif +#ifdef ROM_SysCtlMOSCConfigSet +#define MAP_SysCtlMOSCConfigSet \ + ROM_SysCtlMOSCConfigSet +#else +#define MAP_SysCtlMOSCConfigSet \ + SysCtlMOSCConfigSet +#endif +#ifdef ROM_SysCtlPIOSCCalibrate +#define MAP_SysCtlPIOSCCalibrate \ + ROM_SysCtlPIOSCCalibrate +#else +#define MAP_SysCtlPIOSCCalibrate \ + SysCtlPIOSCCalibrate +#endif +#ifdef ROM_SysCtlDeepSleepClockSet +#define MAP_SysCtlDeepSleepClockSet \ + ROM_SysCtlDeepSleepClockSet +#else +#define MAP_SysCtlDeepSleepClockSet \ + SysCtlDeepSleepClockSet +#endif + +//***************************************************************************** +// +// Macros for the SysExc API. +// +//***************************************************************************** +#ifdef ROM_SysExcIntStatus +#define MAP_SysExcIntStatus \ + ROM_SysExcIntStatus +#else +#define MAP_SysExcIntStatus \ + SysExcIntStatus +#endif +#ifdef ROM_SysExcIntClear +#define MAP_SysExcIntClear \ + ROM_SysExcIntClear +#else +#define MAP_SysExcIntClear \ + SysExcIntClear +#endif +#ifdef ROM_SysExcIntDisable +#define MAP_SysExcIntDisable \ + ROM_SysExcIntDisable +#else +#define MAP_SysExcIntDisable \ + SysExcIntDisable +#endif +#ifdef ROM_SysExcIntEnable +#define MAP_SysExcIntEnable \ + ROM_SysExcIntEnable +#else +#define MAP_SysExcIntEnable \ + SysExcIntEnable +#endif + +//***************************************************************************** +// +// Macros for the SysTick API. +// +//***************************************************************************** +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlTrigger +#define MAP_TimerControlTrigger \ + ROM_TimerControlTrigger +#else +#define MAP_TimerControlTrigger \ + TimerControlTrigger +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerRTCEnable +#define MAP_TimerRTCEnable \ + ROM_TimerRTCEnable +#else +#define MAP_TimerRTCEnable \ + TimerRTCEnable +#endif +#ifdef ROM_TimerRTCDisable +#define MAP_TimerRTCDisable \ + ROM_TimerRTCDisable +#else +#define MAP_TimerRTCDisable \ + TimerRTCDisable +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerControlWaitOnTrigger +#define MAP_TimerControlWaitOnTrigger \ + ROM_TimerControlWaitOnTrigger +#else +#define MAP_TimerControlWaitOnTrigger \ + TimerControlWaitOnTrigger +#endif +#ifdef ROM_TimerLoadSet64 +#define MAP_TimerLoadSet64 \ + ROM_TimerLoadSet64 +#else +#define MAP_TimerLoadSet64 \ + TimerLoadSet64 +#endif +#ifdef ROM_TimerLoadGet64 +#define MAP_TimerLoadGet64 \ + ROM_TimerLoadGet64 +#else +#define MAP_TimerLoadGet64 \ + TimerLoadGet64 +#endif +#ifdef ROM_TimerValueGet64 +#define MAP_TimerValueGet64 \ + ROM_TimerValueGet64 +#else +#define MAP_TimerValueGet64 \ + TimerValueGet64 +#endif +#ifdef ROM_TimerMatchSet64 +#define MAP_TimerMatchSet64 \ + ROM_TimerMatchSet64 +#else +#define MAP_TimerMatchSet64 \ + TimerMatchSet64 +#endif +#ifdef ROM_TimerMatchGet64 +#define MAP_TimerMatchGet64 \ + ROM_TimerMatchGet64 +#else +#define MAP_TimerMatchGet64 \ + TimerMatchGet64 +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTEnableSIR +#define MAP_UARTEnableSIR \ + ROM_UARTEnableSIR +#else +#define MAP_UARTEnableSIR \ + UARTEnableSIR +#endif +#ifdef ROM_UARTDisableSIR +#define MAP_UARTDisableSIR \ + ROM_UARTDisableSIR +#else +#define MAP_UARTDisableSIR \ + UARTDisableSIR +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTClockSourceSet +#define MAP_UARTClockSourceSet \ + ROM_UARTClockSourceSet +#else +#define MAP_UARTClockSourceSet \ + UARTClockSourceSet +#endif +#ifdef ROM_UARTClockSourceGet +#define MAP_UARTClockSourceGet \ + ROM_UARTClockSourceGet +#else +#define MAP_UARTClockSourceGet \ + UARTClockSourceGet +#endif +#ifdef ROM_UART9BitEnable +#define MAP_UART9BitEnable \ + ROM_UART9BitEnable +#else +#define MAP_UART9BitEnable \ + UART9BitEnable +#endif +#ifdef ROM_UART9BitDisable +#define MAP_UART9BitDisable \ + ROM_UART9BitDisable +#else +#define MAP_UART9BitDisable \ + UART9BitDisable +#endif +#ifdef ROM_UART9BitAddrSet +#define MAP_UART9BitAddrSet \ + ROM_UART9BitAddrSet +#else +#define MAP_UART9BitAddrSet \ + UART9BitAddrSet +#endif +#ifdef ROM_UART9BitAddrSend +#define MAP_UART9BitAddrSend \ + ROM_UART9BitAddrSend +#else +#define MAP_UART9BitAddrSend \ + UART9BitAddrSend +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAChannelSelectSecondary +#define MAP_uDMAChannelSelectSecondary \ + ROM_uDMAChannelSelectSecondary +#else +#define MAP_uDMAChannelSelectSecondary \ + uDMAChannelSelectSecondary +#endif +#ifdef ROM_uDMAChannelSelectDefault +#define MAP_uDMAChannelSelectDefault \ + ROM_uDMAChannelSelectDefault +#else +#define MAP_uDMAChannelSelectDefault \ + uDMAChannelSelectDefault +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif + +//***************************************************************************** +// +// Macros for the USB API. +// +//***************************************************************************** +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBDevAddrGet +#define MAP_USBDevAddrGet \ + ROM_USBDevAddrGet +#else +#define MAP_USBDevAddrGet \ + USBDevAddrGet +#endif +#ifdef ROM_USBDevAddrSet +#define MAP_USBDevAddrSet \ + ROM_USBDevAddrSet +#else +#define MAP_USBDevAddrSet \ + USBDevAddrSet +#endif +#ifdef ROM_USBDevConnect +#define MAP_USBDevConnect \ + ROM_USBDevConnect +#else +#define MAP_USBDevConnect \ + USBDevConnect +#endif +#ifdef ROM_USBDevDisconnect +#define MAP_USBDevDisconnect \ + ROM_USBDevDisconnect +#else +#define MAP_USBDevDisconnect \ + USBDevDisconnect +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define MAP_USBDevEndpointConfigSet \ + ROM_USBDevEndpointConfigSet +#else +#define MAP_USBDevEndpointConfigSet \ + USBDevEndpointConfigSet +#endif +#ifdef ROM_USBDevEndpointDataAck +#define MAP_USBDevEndpointDataAck \ + ROM_USBDevEndpointDataAck +#else +#define MAP_USBDevEndpointDataAck \ + USBDevEndpointDataAck +#endif +#ifdef ROM_USBDevEndpointStall +#define MAP_USBDevEndpointStall \ + ROM_USBDevEndpointStall +#else +#define MAP_USBDevEndpointStall \ + USBDevEndpointStall +#endif +#ifdef ROM_USBDevEndpointStallClear +#define MAP_USBDevEndpointStallClear \ + ROM_USBDevEndpointStallClear +#else +#define MAP_USBDevEndpointStallClear \ + USBDevEndpointStallClear +#endif +#ifdef ROM_USBDevEndpointStatusClear +#define MAP_USBDevEndpointStatusClear \ + ROM_USBDevEndpointStatusClear +#else +#define MAP_USBDevEndpointStatusClear \ + USBDevEndpointStatusClear +#endif +#ifdef ROM_USBEndpointDataGet +#define MAP_USBEndpointDataGet \ + ROM_USBEndpointDataGet +#else +#define MAP_USBEndpointDataGet \ + USBEndpointDataGet +#endif +#ifdef ROM_USBEndpointDataPut +#define MAP_USBEndpointDataPut \ + ROM_USBEndpointDataPut +#else +#define MAP_USBEndpointDataPut \ + USBEndpointDataPut +#endif +#ifdef ROM_USBEndpointDataSend +#define MAP_USBEndpointDataSend \ + ROM_USBEndpointDataSend +#else +#define MAP_USBEndpointDataSend \ + USBEndpointDataSend +#endif +#ifdef ROM_USBEndpointDataToggleClear +#define MAP_USBEndpointDataToggleClear \ + ROM_USBEndpointDataToggleClear +#else +#define MAP_USBEndpointDataToggleClear \ + USBEndpointDataToggleClear +#endif +#ifdef ROM_USBEndpointStatus +#define MAP_USBEndpointStatus \ + ROM_USBEndpointStatus +#else +#define MAP_USBEndpointStatus \ + USBEndpointStatus +#endif +#ifdef ROM_USBFIFOAddrGet +#define MAP_USBFIFOAddrGet \ + ROM_USBFIFOAddrGet +#else +#define MAP_USBFIFOAddrGet \ + USBFIFOAddrGet +#endif +#ifdef ROM_USBFIFOConfigGet +#define MAP_USBFIFOConfigGet \ + ROM_USBFIFOConfigGet +#else +#define MAP_USBFIFOConfigGet \ + USBFIFOConfigGet +#endif +#ifdef ROM_USBFIFOConfigSet +#define MAP_USBFIFOConfigSet \ + ROM_USBFIFOConfigSet +#else +#define MAP_USBFIFOConfigSet \ + USBFIFOConfigSet +#endif +#ifdef ROM_USBFIFOFlush +#define MAP_USBFIFOFlush \ + ROM_USBFIFOFlush +#else +#define MAP_USBFIFOFlush \ + USBFIFOFlush +#endif +#ifdef ROM_USBFrameNumberGet +#define MAP_USBFrameNumberGet \ + ROM_USBFrameNumberGet +#else +#define MAP_USBFrameNumberGet \ + USBFrameNumberGet +#endif +#ifdef ROM_USBHostAddrGet +#define MAP_USBHostAddrGet \ + ROM_USBHostAddrGet +#else +#define MAP_USBHostAddrGet \ + USBHostAddrGet +#endif +#ifdef ROM_USBHostAddrSet +#define MAP_USBHostAddrSet \ + ROM_USBHostAddrSet +#else +#define MAP_USBHostAddrSet \ + USBHostAddrSet +#endif +#ifdef ROM_USBHostEndpointConfig +#define MAP_USBHostEndpointConfig \ + ROM_USBHostEndpointConfig +#else +#define MAP_USBHostEndpointConfig \ + USBHostEndpointConfig +#endif +#ifdef ROM_USBHostEndpointDataAck +#define MAP_USBHostEndpointDataAck \ + ROM_USBHostEndpointDataAck +#else +#define MAP_USBHostEndpointDataAck \ + USBHostEndpointDataAck +#endif +#ifdef ROM_USBHostEndpointDataToggle +#define MAP_USBHostEndpointDataToggle \ + ROM_USBHostEndpointDataToggle +#else +#define MAP_USBHostEndpointDataToggle \ + USBHostEndpointDataToggle +#endif +#ifdef ROM_USBHostEndpointStatusClear +#define MAP_USBHostEndpointStatusClear \ + ROM_USBHostEndpointStatusClear +#else +#define MAP_USBHostEndpointStatusClear \ + USBHostEndpointStatusClear +#endif +#ifdef ROM_USBHostHubAddrGet +#define MAP_USBHostHubAddrGet \ + ROM_USBHostHubAddrGet +#else +#define MAP_USBHostHubAddrGet \ + USBHostHubAddrGet +#endif +#ifdef ROM_USBHostHubAddrSet +#define MAP_USBHostHubAddrSet \ + ROM_USBHostHubAddrSet +#else +#define MAP_USBHostHubAddrSet \ + USBHostHubAddrSet +#endif +#ifdef ROM_USBHostPwrDisable +#define MAP_USBHostPwrDisable \ + ROM_USBHostPwrDisable +#else +#define MAP_USBHostPwrDisable \ + USBHostPwrDisable +#endif +#ifdef ROM_USBHostPwrEnable +#define MAP_USBHostPwrEnable \ + ROM_USBHostPwrEnable +#else +#define MAP_USBHostPwrEnable \ + USBHostPwrEnable +#endif +#ifdef ROM_USBHostPwrConfig +#define MAP_USBHostPwrConfig \ + ROM_USBHostPwrConfig +#else +#define MAP_USBHostPwrConfig \ + USBHostPwrConfig +#endif +#ifdef ROM_USBHostPwrFaultDisable +#define MAP_USBHostPwrFaultDisable \ + ROM_USBHostPwrFaultDisable +#else +#define MAP_USBHostPwrFaultDisable \ + USBHostPwrFaultDisable +#endif +#ifdef ROM_USBHostPwrFaultEnable +#define MAP_USBHostPwrFaultEnable \ + ROM_USBHostPwrFaultEnable +#else +#define MAP_USBHostPwrFaultEnable \ + USBHostPwrFaultEnable +#endif +#ifdef ROM_USBHostRequestIN +#define MAP_USBHostRequestIN \ + ROM_USBHostRequestIN +#else +#define MAP_USBHostRequestIN \ + USBHostRequestIN +#endif +#ifdef ROM_USBHostRequestStatus +#define MAP_USBHostRequestStatus \ + ROM_USBHostRequestStatus +#else +#define MAP_USBHostRequestStatus \ + USBHostRequestStatus +#endif +#ifdef ROM_USBHostReset +#define MAP_USBHostReset \ + ROM_USBHostReset +#else +#define MAP_USBHostReset \ + USBHostReset +#endif +#ifdef ROM_USBHostResume +#define MAP_USBHostResume \ + ROM_USBHostResume +#else +#define MAP_USBHostResume \ + USBHostResume +#endif +#ifdef ROM_USBHostSpeedGet +#define MAP_USBHostSpeedGet \ + ROM_USBHostSpeedGet +#else +#define MAP_USBHostSpeedGet \ + USBHostSpeedGet +#endif +#ifdef ROM_USBHostSuspend +#define MAP_USBHostSuspend \ + ROM_USBHostSuspend +#else +#define MAP_USBHostSuspend \ + USBHostSuspend +#endif +#ifdef ROM_USBIntDisable +#define MAP_USBIntDisable \ + ROM_USBIntDisable +#else +#define MAP_USBIntDisable \ + USBIntDisable +#endif +#ifdef ROM_USBIntEnable +#define MAP_USBIntEnable \ + ROM_USBIntEnable +#else +#define MAP_USBIntEnable \ + USBIntEnable +#endif +#ifdef ROM_USBDevEndpointConfigGet +#define MAP_USBDevEndpointConfigGet \ + ROM_USBDevEndpointConfigGet +#else +#define MAP_USBDevEndpointConfigGet \ + USBDevEndpointConfigGet +#endif +#ifdef ROM_USBEndpointDMAEnable +#define MAP_USBEndpointDMAEnable \ + ROM_USBEndpointDMAEnable +#else +#define MAP_USBEndpointDMAEnable \ + USBEndpointDMAEnable +#endif +#ifdef ROM_USBEndpointDMADisable +#define MAP_USBEndpointDMADisable \ + ROM_USBEndpointDMADisable +#else +#define MAP_USBEndpointDMADisable \ + USBEndpointDMADisable +#endif +#ifdef ROM_USBEndpointDataAvail +#define MAP_USBEndpointDataAvail \ + ROM_USBEndpointDataAvail +#else +#define MAP_USBEndpointDataAvail \ + USBEndpointDataAvail +#endif +#ifdef ROM_USBOTGHostRequest +#define MAP_USBOTGHostRequest \ + ROM_USBOTGHostRequest +#else +#define MAP_USBOTGHostRequest \ + USBOTGHostRequest +#endif +#ifdef ROM_USBModeGet +#define MAP_USBModeGet \ + ROM_USBModeGet +#else +#define MAP_USBModeGet \ + USBModeGet +#endif +#ifdef ROM_USBEndpointDMAChannel +#define MAP_USBEndpointDMAChannel \ + ROM_USBEndpointDMAChannel +#else +#define MAP_USBEndpointDMAChannel \ + USBEndpointDMAChannel +#endif +#ifdef ROM_USBIntDisableControl +#define MAP_USBIntDisableControl \ + ROM_USBIntDisableControl +#else +#define MAP_USBIntDisableControl \ + USBIntDisableControl +#endif +#ifdef ROM_USBIntEnableControl +#define MAP_USBIntEnableControl \ + ROM_USBIntEnableControl +#else +#define MAP_USBIntEnableControl \ + USBIntEnableControl +#endif +#ifdef ROM_USBIntStatusControl +#define MAP_USBIntStatusControl \ + ROM_USBIntStatusControl +#else +#define MAP_USBIntStatusControl \ + USBIntStatusControl +#endif +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBIntDisableEndpoint +#define MAP_USBIntDisableEndpoint \ + ROM_USBIntDisableEndpoint +#else +#define MAP_USBIntDisableEndpoint \ + USBIntDisableEndpoint +#endif +#ifdef ROM_USBIntEnableEndpoint +#define MAP_USBIntEnableEndpoint \ + ROM_USBIntEnableEndpoint +#else +#define MAP_USBIntEnableEndpoint \ + USBIntEnableEndpoint +#endif +#ifdef ROM_USBIntStatusEndpoint +#define MAP_USBIntStatusEndpoint \ + ROM_USBIntStatusEndpoint +#else +#define MAP_USBIntStatusEndpoint \ + USBIntStatusEndpoint +#endif +#ifdef ROM_USBHostMode +#define MAP_USBHostMode \ + ROM_USBHostMode +#else +#define MAP_USBHostMode \ + USBHostMode +#endif +#ifdef ROM_USBDevMode +#define MAP_USBDevMode \ + ROM_USBDevMode +#else +#define MAP_USBDevMode \ + USBDevMode +#endif +#ifdef ROM_USBPHYPowerOff +#define MAP_USBPHYPowerOff \ + ROM_USBPHYPowerOff +#else +#define MAP_USBPHYPowerOff \ + USBPHYPowerOff +#endif +#ifdef ROM_USBPHYPowerOn +#define MAP_USBPHYPowerOn \ + ROM_USBPHYPowerOn +#else +#define MAP_USBPHYPowerOn \ + USBPHYPowerOn +#endif +#ifdef ROM_USBOTGMode +#define MAP_USBOTGMode \ + ROM_USBOTGMode +#else +#define MAP_USBOTGMode \ + USBOTGMode +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogResetEnable +#define MAP_WatchdogResetEnable \ + ROM_WatchdogResetEnable +#else +#define MAP_WatchdogResetEnable \ + WatchdogResetEnable +#endif +#ifdef ROM_WatchdogResetDisable +#define MAP_WatchdogResetDisable \ + ROM_WatchdogResetDisable +#else +#define MAP_WatchdogResetDisable \ + WatchdogResetDisable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntEnable +#define MAP_WatchdogIntEnable \ + ROM_WatchdogIntEnable +#else +#define MAP_WatchdogIntEnable \ + WatchdogIntEnable +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntTypeSet +#define MAP_WatchdogIntTypeSet \ + ROM_WatchdogIntTypeSet +#else +#define MAP_WatchdogIntTypeSet \ + WatchdogIntTypeSet +#endif + +//***************************************************************************** +// +// Macros for the Software API. +// +//***************************************************************************** +#ifdef ROM_Crc16Array +#define MAP_Crc16Array \ + ROM_Crc16Array +#else +#define MAP_Crc16Array \ + Crc16Array +#endif +#ifdef ROM_Crc16Array3 +#define MAP_Crc16Array3 \ + ROM_Crc16Array3 +#else +#define MAP_Crc16Array3 \ + Crc16Array3 +#endif +#ifdef ROM_Crc16 +#define MAP_Crc16 \ + ROM_Crc16 +#else +#define MAP_Crc16 \ + Crc16 +#endif +#ifdef ROM_Crc8CCITT +#define MAP_Crc8CCITT \ + ROM_Crc8CCITT +#else +#define MAP_Crc8CCITT \ + Crc8CCITT +#endif + +#endif // __ROM_MAP_H__ diff --git a/bsp/tm4c129x-dk/libraries/driverlib/rtos_bindings.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h similarity index 83% rename from bsp/tm4c129x-dk/libraries/driverlib/rtos_bindings.h rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h index 90762502c0..9c3df5da88 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/rtos_bindings.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h @@ -1,9 +1,9 @@ //***************************************************************************** // -// rtos_bindings.h - Macros intended to aid porting of TivaWare modules +// rtos_bindings.h - Macros ulIntIDended to aid porting of StellarisWare modules // for use with an RTOS. // -// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,27 +34,26 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. // //***************************************************************************** - -#ifndef __DRIVERLIB_RTOS_BINDINGS_H__ -#define __DRIVERLIB_RTOS_BINDINGS_H__ +#ifndef RTOS_BINDINGS_H_ +#define RTOS_BINDINGS_H_ #ifdef USE_RTOS //***************************************************************************** // -// If an RTOS is in use, implement a header file called "tiva_rtos.h" +// If an RTOS is in use, implement a header file called "stellaris_rtos.h" // which contains RTOS-specific versions of each of the macros defined below // and make sure it appears on the include path set when you build your // project. // // Note that there is no default implementation of this header file included -// in TivaWare - it is your responsibility to create it specifically for +// in StellarisWare - it is your responsibility to create it specifically for // your RTOS. // //***************************************************************************** -#include "tiva_rtos.h" +#include "stellaris_rtos.h" #else //***************************************************************************** @@ -62,8 +61,8 @@ // When no RTOS is in use, the follow macros compile to either nothing or a // minimal implementation that works in a bare-metal environment. // -// Each of these macros must be redefined in tiva_rtos.h if you are using -// TivaWare under an RTOS. +// Each of these macros must be redefined in stellaris_rtos.h if you are using +// StellarisWare under an RTOS. // //***************************************************************************** @@ -92,7 +91,7 @@ // for the DriverLib Interrupt driver. // // The macros defined here represent interrupt-control functions that may be -// called from within TivaWare code. It is expected that application +// called from within StellarisWare code. It is expected that application // code will use RTOS-specific functions to control interrupt priority, to // pend interrupts and to perform runtime vector manipulation. As a result, // no macros are defined to wrap any of these functions from interrupt.c. @@ -100,9 +99,9 @@ //***************************************************************************** #define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable() #define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable() -#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID) -#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID) +#define OS_INT_DISABLE(ulIntID) MAP_IntDisable(ulIntID) +#define OS_INT_ENABLE(ulIntID) MAP_IntEnable(ulIntID) #endif // USE_RTOS -#endif // __DRIVERLIB_RTOS_BINDINGS_H__ +#endif // RTOS_BINDINGS_H_ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c new file mode 100644 index 0000000000..00fbd65ad4 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c @@ -0,0 +1,841 @@ +//########################################################################### +// +// FILE: sysctl.c +// +// TITLE: Stellaris style wrapper driver for F2837x system control. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "F28x_Project.h" +#include +#include +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +//! \internal +//! Checks a peripheral identifier. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \return Returns \b true if the peripheral identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_SysCtlPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == SYSCTL_PERIPH_CLA1) || + (ui32Peripheral == SYSCTL_PERIPH_DMA) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER0) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER1) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER2) || + (ui32Peripheral == SYSCTL_PERIPH_HRPWM) || + (ui32Peripheral == SYSCTL_PERIPH_TBCLKSYNC) || + (ui32Peripheral == SYSCTL_PERIPH_GTBCLKSYNC) || + (ui32Peripheral == SYSCTL_PERIPH_EMIF1) || + (ui32Peripheral == SYSCTL_PERIPH_EMIF2) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM1) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM2) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM3) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM4) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM5) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM6) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM7) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM8) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM9) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM10) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM11) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM12) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP1) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP2) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP3) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP4) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP5) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP6) || + (ui32Peripheral == SYSCTL_PERIPH_EQEP1) || + (ui32Peripheral == SYSCTL_PERIPH_EQEP2) || + (ui32Peripheral == SYSCTL_PERIPH_EQEP3) || + (ui32Peripheral == SYSCTL_PERIPH_SD1) || + (ui32Peripheral == SYSCTL_PERIPH_SD2) || + (ui32Peripheral == SYSCTL_PERIPH_SCI1) || + (ui32Peripheral == SYSCTL_PERIPH_SCI2) || + (ui32Peripheral == SYSCTL_PERIPH_SCI3) || + (ui32Peripheral == SYSCTL_PERIPH_SCI4) || + (ui32Peripheral == SYSCTL_PERIPH_SPI1) || + (ui32Peripheral == SYSCTL_PERIPH_SPI2) || + (ui32Peripheral == SYSCTL_PERIPH_SPI3) || + (ui32Peripheral == SYSCTL_PERIPH_I2C1) || + (ui32Peripheral == SYSCTL_PERIPH_I2C2) || + (ui32Peripheral == SYSCTL_PERIPH_CAN1) || + (ui32Peripheral == SYSCTL_PERIPH_CAN2) || + (ui32Peripheral == SYSCTL_PERIPH_MCBSP1) || + (ui32Peripheral == SYSCTL_PERIPH_MCBSP2) || + (ui32Peripheral == SYSCTL_PERIPH_UPP1) || + (ui32Peripheral == SYSCTL_PERIPH_ADC1) || + (ui32Peripheral == SYSCTL_PERIPH_ADC2) || + (ui32Peripheral == SYSCTL_PERIPH_ADC3) || + (ui32Peripheral == SYSCTL_PERIPH_ADC4) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS1) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS2) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS3) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS4) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS5) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS6) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS7) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS8) || + (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC1) || + (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC2) || + (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC3)); +} +#endif + + + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ui32Peripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is present in the +//! device. Each member of the family has a different peripheral +//! set; this function determines which peripherals are present on this device. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +bool +SysCtlPeripheralPresent(uint32_t ui32Peripheral) +{ + + uint16_t regIndex; + uint16_t bitIndex; + + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + if(HWREG(&(DevCfgRegs.DC0.all) + (2 * regIndex)) & (1 << bitIndex)){ + return true; + }else{ + return false; + } + + +} + +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ui32Peripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! \note The ability to check for a peripheral being ready varies based on the +//! part in use. Please consult the data sheet for the part you are +//! using to determine if this feature is available. +//! +//! \return Returns \b true if the specified peripheral is ready and \b false +//! if it is not. +// +//***************************************************************************** +bool +SysCtlPeripheralReady(uint32_t ui32Peripheral) +{ + + uint16_t regIndex; + uint16_t bitIndex; + + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + // Is the peripheral there? + if(HWREG((uint32_t)&(DevCfgRegs.DC0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)){ + // Is the peripheral enabled? + if(HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)){ + // Is the peripheral in reset? + if((HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)) == 0){ + // No? Ok cool + return true; + } + } + }else{ + return false; + } + + return false; +} +//***************************************************************************** +// +//! Resets a peripheral +//! +//! \param ui32Peripheral is the peripheral to reset. +//! +//! The f2837x devices do not have a means of resetting peripherals via +//! via software. This is a dummy function that does nothing. +//! +//! +//! \return None. +// +//***************************************************************************** +void SysCtlPeripheralReset(uint32_t ui32Peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + EALLOW; + + HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) |= ((uint32_t)1 << bitIndex); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) &= ~((uint32_t)1 << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ui32Peripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_UART_A, \b SYSCTL_PERIPH_UART_B, \b SYSCTL_PERIPH_UART_C, +//! \b SYSCTL_PERIPH_UART_D, \b SYSCTL_PERIPH_SPI_A, \b SYSCTL_PERIPH_SPI_B, +//! \b SYSCTL_PERIPH_SPI_C, \b SYSCTL_PERIPH_MCBSP_A, \b SYSCTL_PERIPH_MCBSP_B, +//! \b SYSCTL_PERIPH_DMA, \b SYSCTL_PERIPH_USB_A +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralEnable(uint32_t ui32Peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + volatile uint32_t test1, test2, test3, test4; + + regIndex = (ui32Peripheral & SYSCTL_PERIPH_REG_M); + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + EALLOW; + HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) |= ((uint32_t)1 << bitIndex); + + EDIS; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_UART_A, \b SYSCTL_PERIPH_UART_B, \b SYSCTL_PERIPH_UART_C, +//! \b SYSCTL_PERIPH_UART_D, \b SYSCTL_PERIPH_SPI_A, \b SYSCTL_PERIPH_SPI_B, +//! \b SYSCTL_PERIPH_SPI_C, \b SYSCTL_PERIPH_MCBSP_A, \b SYSCTL_PERIPH_MCBSP_B, +//! \b SYSCTL_PERIPH_DMA, \b SYSCTL_PERIPH_USB_A +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDisable(uint32_t ui32Peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + EALLOW; + + HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) &= ~((uint32_t)1 << bitIndex); + + EDIS; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a software reset of the entire device. The +//! processor and all peripherals are reset and all device registers are +//! returned to their default values (with the exception of the reset cause +//! register, which maintains its current value but has the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +void +SysCtlReset(void) +{ + // + // Write an incorrect check value to the watchdog control register + // This will cause a device reset + // + EALLOW; + // Enable the watchdog + HWREG(&(WdRegs.WDCR.all)) = 0x0028; + // Write a bad check value + HWREG(&(WdRegs.WDCR.all)) = 0xFFFF; + EDIS; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} + + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! The loop takes 5 cycles/loop + 9. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + __asm(" .def _SysCtlDelay\n" + " .sect \".TI.ramfunc\"\n" + " .global _SysCtlDelay\n" + "_SysCtlDelay:\n" + " SUB ACC,#1\n" + " BF _SysCtlDelay,GEQ\n" + " LRETR\n"); + #else + __asm(" .def _SysCtlDelay\n" + " .sect \"ramfuncs\"\n" + " .global _SysCtlDelay\n" + "_SysCtlDelay:\n" + " SUB ACC,#1\n" + " BF _SysCtlDelay,GEQ\n" + " LRETR\n"); + #endif +#endif + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. +//! +//! \note Because of the many different clocking options available, this +//! function cannot determine the clock speed of the processor. This function +//! should be modified to return the actual clock speed of the processor in +//! your specific application. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +uint32_t +SysCtlClockGet(uint32_t u32ClockIn) +{ + + if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0) || + (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 2)){ + //10MHz Internal Clock + u32ClockIn = 10000000; + } + + //If the pll is enabled calculate its effect on the clock +// if((HWREG(SYSCTL_SYSPLLCTL) & +// (SYSCTL_SYSPLLCTL_SPLLEN | SYSCTL_SYSPLLCTL_SPLLCLKEN)) == 3) + if(ClkCfgRegs.SYSPLLCTL1.bit.PLLEN && ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN) + { + //Calculate integer multiplier and fixed divide by 2 +// ulClockIn = ulClockIn * +// (HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLIMULT_M); + u32ClockIn = u32ClockIn * ClkCfgRegs.SYSPLLMULT.bit.IMULT; + + + //Calculate fractional multiplier +// switch((HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLFMULT_M) >> +// SYSCTL_SYSPLLMULT_SPLLFMULT_S) + switch(ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + default: + case 0: + break; + + case 1: + u32ClockIn += u32ClockIn / 4; + break; + + case 2: + u32ClockIn += u32ClockIn / 2; + break; + + case 3: + u32ClockIn += (u32ClockIn * 3) / 4; + break; + } + } + + if(ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV != 0){ + u32ClockIn /= (2 * ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV); + } + + return u32ClockIn; + +} + +//***************************************************************************** +// +//! Gets the low speed peripheral clock rate. +//! +//! This function determines the clock rate of the low speed peripherals. +//! +//! \note Because of the many different clocking options available, this +//! function cannot determine the clock speed of the processor. This function +//! should be modified to return the actual clock speed of the processor in +//! your specific application. +//! +//! \return The low speed peripheral clock rate. +// +//***************************************************************************** +uint32_t +SysCtlLowSpeedClockGet(uint32_t u32ClockIn) +{ + + // Get the main system clock + u32ClockIn = SysCtlClockGet(u32ClockIn); + + // Apply the divider to the main clock + if(ClkCfgRegs.LOSPCP.bit.LSPCLKDIV != 0){ + u32ClockIn /= (2 * ClkCfgRegs.LOSPCP.bit.LSPCLKDIV); + } + + return u32ClockIn; + +} + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ui32Config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The oscillator to be +//! used, SYSPLL fractional and integer multiplier, and the system clock +//! divider are all configured with this function. +//! +//! The \e ui32Config parameter is the logical OR of four values: +//! Clock divider, Integer multiplier, Fractional multiplier, and oscillator +//! source. +//! +//! The system clock divider is chosen with using the following macro: +//! \b SYSCTL_SYSDIV(x) - "x" is an integer of value 1 or any even value +//! up to 126 +//! +//! The System PLL fractional multiplier is chosen with one of the following +//! values: +//! \b SYSCTL_FMULT_0, \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, +//! \b SYSCTL_FMULT_3_4 +//! +//! The System PLL integer multiplier is chosen with using the following macro: +//! \b SYSCTL_IMULT(x) - "x" is an integer from 0 to 127 +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_OSC1 +//! +//! \note The external oscillator must be enabled in order to use an external +//! clock source. Note that attempts to disable the oscillator used to clock +//! the device is prevented by the hardware. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClockSet(uint32_t ui32Config) +{ + uint32_t clock_source = (ui32Config & SYSCTL_OSCSRC_M) >> SYSCTL_OSCSRC_S; + uint32_t imult = (ui32Config & SYSCTL_IMULT_M); + uint32_t fmult = (ui32Config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S; + uint32_t divsel = (ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + + if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + //everything is set as required, so just return + return; + } + + if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) + { + //Configure Oscillator + EALLOW; + switch (clock_source) + { + case ((uint32_t)SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S): + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + + case ((uint32_t)SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S): + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL + break; + + case ((uint32_t)SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S): + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + } + EDIS; + } + + EALLOW; + // first modify the PLL multipliers + if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || + fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + // Bypass PLL and set dividers to /1 + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // Program PLL multipliers + uint32_t temp_syspllmult = ClkCfgRegs.SYSPLLMULT.all; + ClkCfgRegs.SYSPLLMULT.all = ((temp_syspllmult & ~(0x37FU)) | + ((fmult << 8U) | imult)); + + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; // Enable SYSPLL + + // Wait for the SYSPLL lock + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // Uncomment to service the watchdog + //WdRegs.WDKEY.bit.WDKEY = 0x0055; + //WdRegs.WDKEY.bit.WDKEY = 0x00AA; + } + + // Write a multiplier again to ensure proper PLL initialization + // This will force the PLL to lock a second time + ClkCfgRegs.SYSPLLMULT.bit.IMULT = imult; // Setting integer multiplier + + // Wait for the SYSPLL re-lock + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // Uncomment to service the watchdog + //WdRegs.WDKEY.bit.WDKEY = 0x0055; + //WdRegs.WDKEY.bit.WDKEY = 0x00AA; + } + } + + // Set divider to produce slower output frequency to limit current increase + if(divsel != (126/2)) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // Enable PLLSYSCLK is fed from system PLL clock + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // Small 100 cycle delay + asm(" RPT #100 || NOP"); + + // Set the divider to user value + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ui32Config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e ui32Config parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... +//! \b SYSCTL_SYSDIV_64. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, +//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, +//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, +//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, +//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. +//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in +//! operation. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, +//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only +//! available on devices with the hibernate module, and then only when the +//! hibernate module has been enabled. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device is prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (that is, via +//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function delays until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlAuxClockSet(uint32_t ui32Config) +{ + uint16_t ui16TempDivsel; + + //Bypass PLL + //Ensure the PLL is out of our clock tree + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + EDIS; + + __asm( " RPT #255 || NOP"); + + //Configure Oscillator + EALLOW; + switch (ui32Config & SYSCTL_OSCSRC_M) + { + default: + case SYSCTL_OSCSRC_OSC2: + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + + case SYSCTL_OSCSRC_XTAL: + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + break; + + case SYSCTL_OSCSRC_OSC1: + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + + } + EDIS; + + __asm( " RPT #255 || NOP"); + + //Configure PLL if enabled + if(ui32Config & SYSCTL_PLL_ENABLE) + { + EALLOW; + //modify dividers to maximum to reduce the inrush current + //set the integer fractional multipliers in one single write + ClkCfgRegs.AUXPLLMULT.all = ((ui32Config & SYSCTL_IMULT_M) >> SYSCTL_IMULT_S) | + (((ui32Config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << 8); + EDIS; + + __asm( " RPT #255 || NOP"); + + //Wait for the SYSPLL lock + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // Uncomment to service the watchdog + // ServiceDog(); + } + } + + //Configure Dividers + //increase the freq. of operation in steps to avoid any VDD fluctuations + ui16TempDivsel = 3; + while(ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV != ((ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S)) + { + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = ui16TempDivsel; + EDIS; + ui16TempDivsel -= 1; + if(ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV != ((ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S)) + { + SysCtlDelay(15); + } + } + + //Enable PLLSYSCLK is fed from system PLL clock + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + EDIS; +} + +//***************************************************************************** +// +//! Powers up the USB PLL. +//! +//! This function will enable the USB controller's PLL. +//! +//! \note Because every application is different, the user will likely have to +//! modify this function to ensure the PLL multiplier is set correctly to +//! achieve the 60 MHz required by the USB controller. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLEnable(void) +{ +// // Turn on INTOSC2 +// ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; +// //Select INTOSC2 as USB PLL Clk In +// ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; +// // Set Aux PLL divider +// ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 1; +// // Set Aux PLL multiplier +// ClkCfgRegs.AUXPLLMULT.bit.IMULT = 12; +// // Set Aux PLL fractional multiplier to 0.0 +// ClkCfgRegs.AUXPLLMULT.bit.FMULT = 0; +// //Enable AUXPLL +// ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; +// +// //Wait for the AUXPLL lock +// while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) +// { +// // Uncomment to service the watchdog +// // ServiceDog(); +// } +// // AUXPLLCLK is fed from the AUXPLL +// ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + +} + +//***************************************************************************** +// +//! Powers down the USB PLL. +//! +//! This function will disable the USB controller's PLL. The USB registers +//! are still accessible, but the physical layer will no longer function. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLDisable(void) +{ + //Disable the PLL +// ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h new file mode 100644 index 0000000000..db3c9552de --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h @@ -0,0 +1,283 @@ +//########################################################################### +// +// FILE: sysctl.h +// +// TITLE: Stellaris style wrapper driver for F2837x system control. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** +#include "inc/hw_types.h" +//***************************************************************************** +// +//! Defined system clock oscillator source speed. Adjust this to reflect your +//! actual clock speed. +// +//***************************************************************************** +#if defined(_LAUNCHXL_F28379D) || defined(_LAUNCHXL_F28377S) +#define SYSTEM_CLOCK_SPEED 10000000 +#else +#define SYSTEM_CLOCK_SPEED 20000000 +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_M 0x00001F80 +#define SYSCTL_SYSDIV_S 0x00000007 +// Only 1 or even values up to 126 are allowed +#define SYSCTL_SYSDIV(x) ((((x == 1) ? 0 : (x / 2)) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M) + +#define SYSCTL_IMULT_M 0x0000007F +#define SYSCTL_IMULT_S 0x00000000 +#define SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M) + +#define SYSCTL_FMULT_M 0x00006000 +#define SYSCTL_FMULT_S 0x0000000D +#define SYSCTL_FMULT_0 0x00000000 +#define SYSCTL_FMULT_1_4 0x00002000 +#define SYSCTL_FMULT_1_2 0x00004000 +#define SYSCTL_FMULT_3_4 0x00006000 + +#define SYSCTL_OSCSRC_M 0x00030000 +#define SYSCTL_OSCSRC_S 0x00000010 +#define SYSCTL_OSCSRC_OSC2 0x00000000 +#define SYSCTL_OSCSRC_XTAL 0x00010000 +#define SYSCTL_OSCSRC_OSC1 0x00020000 + +#define SYSCTL_LSDIV_M 0x00700000 +#define SYSCTL_LSDIV_S 0x00000014 +// Only 1 or even values up to 14 are allowed +#define SYSCTL_LSDIV(x) (((x == 1) ? 0 : (x / 2)) << SYSCTL_LSDIV_S) & SYSCTL_LSDIV_M) + +#define SYSCTL_PLL_ENABLE 0x80000000 +#define SYSCTL_PLL_DISABLE 0x00000000 + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_REG_M 0x0000001F +#define SYSCTL_PERIPH_REG_S 0x00000000 + +#define SYSCTL_PERIPH_BIT_M 0x003F0000 +#define SYSCTL_PERIPH_BIT_S 0x00000010 + +//PCLKCR0 +#define SYSCTL_PERIPH_CLA1 0x00000000 +#define SYSCTL_PERIPH_DMA 0x00020000 +#define SYSCTL_PERIPH_TIMER0 0x00030000 +#define SYSCTL_PERIPH_TIMER1 0x00040000 +#define SYSCTL_PERIPH_TIMER2 0x00050000 +#define SYSCTL_PERIPH_HRPWM 0x00100000 +#define SYSCTL_PERIPH_TBCLKSYNC 0x00120000 +#define SYSCTL_PERIPH_GTBCLKSYNC 0x00130000 + +//PCLKCR1 +#define SYSCTL_PERIPH_EMIF1 0x00000001 +#define SYSCTL_PERIPH_EMIF2 0x00010001 + +//PCLKCR2 +#define SYSCTL_PERIPH_EPWM1 0x00000002 +#define SYSCTL_PERIPH_EPWM2 0x00010002 +#define SYSCTL_PERIPH_EPWM3 0x00020002 +#define SYSCTL_PERIPH_EPWM4 0x00030002 +#define SYSCTL_PERIPH_EPWM5 0x00040002 +#define SYSCTL_PERIPH_EPWM6 0x00050002 +#define SYSCTL_PERIPH_EPWM7 0x00060002 +#define SYSCTL_PERIPH_EPWM8 0x00070002 +#define SYSCTL_PERIPH_EPWM9 0x00080002 +#define SYSCTL_PERIPH_EPWM10 0x00090002 +#define SYSCTL_PERIPH_EPWM11 0x000A0002 +#define SYSCTL_PERIPH_EPWM12 0x000B0002 + +//PCLKCR3 +#define SYSCTL_PERIPH_ECAP1 0x00000003 +#define SYSCTL_PERIPH_ECAP2 0x00010003 +#define SYSCTL_PERIPH_ECAP3 0x00020003 +#define SYSCTL_PERIPH_ECAP4 0x00030003 +#define SYSCTL_PERIPH_ECAP5 0x00040003 +#define SYSCTL_PERIPH_ECAP6 0x00050003 + +//PCLKCR4 +#define SYSCTL_PERIPH_EQEP1 0x00000004 +#define SYSCTL_PERIPH_EQEP2 0x00010004 +#define SYSCTL_PERIPH_EQEP3 0x00020004 + +//PCLKCR5 +//Reserved + +//PCLKCR6 +#define SYSCTL_PERIPH_SD1 0x00000006 +#define SYSCTL_PERIPH_SD2 0x00010006 + +//PCLKCR7 +#define SYSCTL_PERIPH_SCI1 0x00000007 +#define SYSCTL_PERIPH_SCI2 0x00010007 +#define SYSCTL_PERIPH_SCI3 0x00020007 +#define SYSCTL_PERIPH_SCI4 0x00030007 + +//PCLKCR8 +#define SYSCTL_PERIPH_SPI1 0x00000008 +#define SYSCTL_PERIPH_SPI2 0x00010008 +#define SYSCTL_PERIPH_SPI3 0x00020008 + +//PCLKCR9 +#define SYSCTL_PERIPH_I2C1 0x00000009 +#define SYSCTL_PERIPH_I2C2 0x00010009 + +//PCLKCR10 +#define SYSCTL_PERIPH_CAN1 0x0000000A +#define SYSCTL_PERIPH_CAN2 0x0001000A + +//PCLKCR11 +#define SYSCTL_PERIPH_MCBSP1 0x0000000B +#define SYSCTL_PERIPH_MCBSP2 0x0001000B +#define SYSCTL_PERIPH_USB0 0x0010000B + +//PCLKCR12 +#define SYSCTL_PERIPH_UPP1 0x0000000C + +//PCLKCR13 +#define SYSCTL_PERIPH_ADC1 0x0000000D +#define SYSCTL_PERIPH_ADC2 0x0001000D +#define SYSCTL_PERIPH_ADC3 0x0002000D +#define SYSCTL_PERIPH_ADC4 0x0003000D + +//PCLKCR14 +#define SYSCTL_PERIPH_CMPSS1 0x0000000E +#define SYSCTL_PERIPH_CMPSS2 0x0001000E +#define SYSCTL_PERIPH_CMPSS3 0x0002000E +#define SYSCTL_PERIPH_CMPSS4 0x0003000E +#define SYSCTL_PERIPH_CMPSS5 0x0004000E +#define SYSCTL_PERIPH_CMPSS6 0x0005000E +#define SYSCTL_PERIPH_CMPSS7 0x0006000E +#define SYSCTL_PERIPH_CMPSS8 0x0007000E + +//PCLKCR15 +//Reserved + +//PCLKCR16 +#define SYSCTL_PERIPH_BUFFDAC1 0x00000010 +#define SYSCTL_PERIPH_BUFFDAC2 0x00010010 +#define SYSCTL_PERIPH_BUFFDAC3 0x00020010 + + +//old +//#define SYSCTL_PERIPH_UART_A 0x1 // SCI A +//#define SYSCTL_PERIPH_UART_B 0x2 // SCI B +//#define SYSCTL_PERIPH_UART_C 0x3 // SCI C +//#define SYSCTL_PERIPH_UART_D 0x4 // SCI D +// +//#define SYSCTL_PERIPH_SPI_A 0x5 // SPI A +//#define SYSCTL_PERIPH_SPI_B 0x6 // SPI B +//#define SYSCTL_PERIPH_SPI_C 0x7 // SPI C +// +//#define SYSCTL_PERIPH_MCBSP_A 0x8 // McBSP A +//#define SYSCTL_PERIPH_MCBSP_B 0x9 // McBSP B +// +//#define SYSCTL_PERIPH_DMA 0xA // DMA +// +//#define SYSCTL_PERIPH_USB0 0xB // USBA + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +extern uint32_t SysCtlSRAMSizeGet(void); +extern uint32_t SysCtlFlashSizeGet(void); +extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); +extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); +extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); +extern void SysCtlDelay(uint32_t ulCount); +extern uint32_t SysCtlClockGet(uint32_t u32ClockIn); +extern void SysCtlClockSet(uint32_t ui32Config); +extern void SysCtlAuxClockSet(uint32_t ui32Config); +extern uint32_t SysCtlLowSpeedClockGet(uint32_t u32ClockIn); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//**************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ + + diff --git a/bsp/tm4c129x-dk/libraries/driverlib/systick.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c similarity index 67% rename from bsp/tm4c129x-dk/libraries/driverlib/systick.c rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c index 662da1729e..971715de78 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/systick.c +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c @@ -1,41 +1,44 @@ -//***************************************************************************** +//########################################################################### // -// systick.c - Driver for the SysTick timer in NVIC. +// FILE: systick.c // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### //***************************************************************************** // @@ -44,28 +47,49 @@ // //***************************************************************************** -#include -#include +#include "F28x_Project.h" #include "inc/hw_ints.h" -#include "inc/hw_nvic.h" #include "inc/hw_types.h" #include "driverlib/debug.h" #include "driverlib/interrupt.h" #include "driverlib/systick.h" + +//***************************************************************************** +// +//! Initializes the Timer0 Module to act as a system tick +//! +//! \return None. +// +//***************************************************************************** +void +SysTickInit(void) +{ + // CPU Timer 0 + // Initialize timer period to maximum: + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + // Make sure timer is stopped: + CpuTimer0Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer0Regs.TCR.bit.TRB = 1; +} + //***************************************************************************** // //! Enables the SysTick counter. //! -//! This function starts the SysTick counter. If an interrupt handler has been -//! registered, it is called when the SysTick counter rolls over. +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. //! -//! \note Calling this function causes the SysTick counter to (re)commence +//! \note Calling this function will cause the SysTick counter to (re)commence //! counting from its current value. The counter is not automatically reloaded //! with the period as specified in a previous call to SysTickPeriodSet(). If //! an immediate reload is required, the \b NVIC_ST_CURRENT register must be -//! written to force the reload. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the supplied period on the next +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next //! clock. //! //! \return None. @@ -77,15 +101,16 @@ SysTickEnable(void) // // Enable SysTick. // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; + CpuTimer0Regs.TCR.bit.TRB = 1; + CpuTimer0Regs.TCR.bit.TSS = 0; } //***************************************************************************** // //! Disables the SysTick counter. //! -//! This function stops the SysTick counter. If an interrupt handler has been -//! registered, it is not called until SysTick is restarted. +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. //! //! \return None. // @@ -96,7 +121,7 @@ SysTickDisable(void) // // Disable SysTick. // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); + StopCpuTimer0(); } //***************************************************************************** @@ -106,8 +131,7 @@ SysTickDisable(void) //! \param pfnHandler is a pointer to the function to be called when the //! SysTick interrupt occurs. //! -//! This function registers the handler to be called when a SysTick interrupt -//! occurs. +//! This sets the handler to be called when a SysTick interrupt occurs. //! //! \sa IntRegister() for important information about registering interrupt //! handlers. @@ -121,19 +145,19 @@ SysTickIntRegister(void (*pfnHandler)(void)) // // Register the interrupt handler, returning an error if an error occurs. // - IntRegister(FAULT_SYSTICK, pfnHandler); + IntRegister(INT_TINT0, pfnHandler); // // Enable the SysTick interrupt. // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + IntEnable(INT_TINT0); } //***************************************************************************** // //! Unregisters the interrupt handler for the SysTick interrupt. //! -//! This function unregisters the handler to be called when a SysTick interrupt +//! This function will clear the handler to be called when a SysTick interrupt //! occurs. //! //! \sa IntRegister() for important information about registering interrupt @@ -148,24 +172,24 @@ SysTickIntUnregister(void) // // Disable the SysTick interrupt. // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + IntDisable(INT_TINT0); // // Unregister the interrupt handler. // - IntUnregister(FAULT_SYSTICK); + IntUnregister(INT_TINT0); } //***************************************************************************** // //! Enables the SysTick interrupt. //! -//! This function enables the SysTick interrupt, allowing it to be +//! This function will enable the SysTick interrupt, allowing it to be //! reflected to the processor. //! -//! \note The SysTick interrupt handler is not required to clear the SysTick -//! interrupt source because it is cleared automatically by the NVIC when the -//! interrupt handler is called. +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically by NVIC when the interrupt +//! handler is called. //! //! \return None. // @@ -176,14 +200,15 @@ SysTickIntEnable(void) // // Enable the SysTick interrupt. // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + CpuTimer0Regs.TCR.bit.TIE = 1; + IntEnable(INT_TINT0); } //***************************************************************************** // //! Disables the SysTick interrupt. //! -//! This function disables the SysTick interrupt, preventing it from being +//! This function will disable the SysTick interrupt, preventing it from being //! reflected to the processor. //! //! \return None. @@ -195,24 +220,25 @@ SysTickIntDisable(void) // // Disable the SysTick interrupt. // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + CpuTimer0Regs.TCR.bit.TIE = 0; + IntDisable(INT_TINT0); } //***************************************************************************** // //! Sets the period of the SysTick counter. //! -//! \param ui32Period is the number of clock ticks in each period of the -//! SysTick counter and must be between 1 and 16,777,216, inclusive. +//! \param ui32Period is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. //! -//! This function sets the rate at which the SysTick counter wraps, which +//! This function sets the rate at which the SysTick counter wraps; this //! equates to the number of processor clocks between interrupts. //! //! \note Calling this function does not cause the SysTick counter to reload //! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT //! register must be written. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the \e ui32Period supplied here on -//! the next clock after SysTick is enabled. +//! counter to 0 and will cause a reload with the \e ui32Period supplied here on +//! the next clock after the SysTick is enabled. //! //! \return None. // @@ -228,14 +254,14 @@ SysTickPeriodSet(uint32_t ui32Period) // // Set the period of the SysTick counter. // - HWREG(NVIC_ST_RELOAD) = ui32Period - 1; + CpuTimer0Regs.PRD.all = ui32Period; } //***************************************************************************** // //! Gets the period of the SysTick counter. //! -//! This function returns the rate at which the SysTick counter wraps, which +//! This function returns the rate at which the SysTick counter wraps; this //! equates to the number of processor clocks between interrupts. //! //! \return Returns the period of the SysTick counter. @@ -247,15 +273,15 @@ SysTickPeriodGet(void) // // Return the period of the SysTick counter. // - return(HWREG(NVIC_ST_RELOAD) + 1); + return(CpuTimer0Regs.PRD.all); } //***************************************************************************** // //! Gets the current value of the SysTick counter. //! -//! This function returns the current value of the SysTick counter, which is -//! a value between the period - 1 and zero, inclusive. +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. //! //! \return Returns the current value of the SysTick counter. // @@ -266,7 +292,7 @@ SysTickValueGet(void) // // Return the current value of the SysTick counter. // - return(HWREG(NVIC_ST_CURRENT)); + return(CpuTimer0Regs.TIM.all); } //***************************************************************************** @@ -275,3 +301,5 @@ SysTickValueGet(void) //! @} // //***************************************************************************** + + diff --git a/bsp/tm4c129x-dk/libraries/driverlib/cpu.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h similarity index 59% rename from bsp/tm4c129x-dk/libraries/driverlib/cpu.h rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h index 11a07e88d0..e4b6e7bf6f 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/cpu.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h @@ -1,44 +1,47 @@ -//***************************************************************************** +//########################################################################### // -// cpu.h - Prototypes for the CPU instruction wrapper functions. +// FILE: systick.h // -// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### -#ifndef __DRIVERLIB_CPU_H__ -#define __DRIVERLIB_CPU_H__ +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ //***************************************************************************** // @@ -53,15 +56,19 @@ extern "C" //***************************************************************************** // -// Prototypes. +// Prototypes for the APIs. // //***************************************************************************** -extern uint32_t CPUcpsid(void); -extern uint32_t CPUcpsie(void); -extern uint32_t CPUprimask(void); -extern void CPUwfi(void); -extern uint32_t CPUbasepriGet(void); -extern void CPUbasepriSet(uint32_t ui32NewBasepri); + extern void SysTickInit(void); + extern void SysTickEnable(void); + extern void SysTickDisable(void); + extern void SysTickIntRegister(void (*pfnHandler)(void)); + extern void SysTickIntUnregister(void); + extern void SysTickIntEnable(void); + extern void SysTickIntDisable(void); + extern void SysTickPeriodSet(uint32_t ui32Period); + extern uint32_t SysTickPeriodGet(void); + extern uint32_t SysTickValueGet(void); //***************************************************************************** // @@ -72,4 +79,6 @@ extern void CPUbasepriSet(uint32_t ui32NewBasepri); } #endif -#endif // __DRIVERLIB_CPU_H__ +#endif // __SYSTICK_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c new file mode 100644 index 0000000000..29b2454261 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c @@ -0,0 +1,1352 @@ +//########################################################################### +// +// FILE: uart.c +// +// TITLE: Stellaris style wrapper driver for C28x SCI peripheral. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/uart.h" + + +//***************************************************************************** +// +//! \internal +//! Checks a UART base address. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function determines if a UART port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +UARTBaseValid(uint32_t ui32Base) +{ + return((ui32Base == UARTA_BASE) || (ui32Base == UARTB_BASE) || + (ui32Base == UARTC_BASE) || (ui32Base == UARTD_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ui32Parity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it is always either one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREGB(ui32Base + UART_O_CCR) = ((HWREGB(ui32Base + UART_O_CCR) & + ~(UART_CONFIG_PAR_MASK)) | ui32Parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the current parity setting. + // + return(HWREGB(ui32Base + UART_O_CCR) & + (UART_CONFIG_PAR_MASK)); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of +//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, +//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of +//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, +//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOIntLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(ui32Base + UART_O_FFTX) = (HWREGH(ui32Base + UART_O_FFTX)& (~UART_FFTX_TXFFIL_M)) | ui32TxLevel ; + HWREGH(ui32Base + UART_O_FFRX) = (HWREGH(ui32Base + UART_O_FFRX)& (~UART_FFRX_RXFFIL_M)) | ui32RxLevel ; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOIntLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFIL_M; + *pui32RxLevel = HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFIL_M; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = (HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFST_M) >> UART_FFTX_TXFFST_S; + *pui32RxLevel = (HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S; +} + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! \param ui32Config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ui32Baud parameter and the data +//! format in the \e ui32Config parameter. +//! +//! The \e ui32Config parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original UARTConfigSet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +//Changed for C28x +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); +// ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER)); + + // + // Stop the UART. + // + UARTDisable(ui32Base); + + // + // Is the required baud rate greater than the maximum rate supported? + // + if((ui32Baud * 16) > ui32UARTClk) + { + // + // Baud Rate Not supported with current clock + // + return; + } + + // + // Compute the baud rate divider. + // + ui32Div = ((ui32UARTClk / (ui32Baud * 8)) - 1); + + // + // Set the baud rate. + // + HWREGB(ui32Base + UART_O_HBAUD) = (ui32Div & 0xFF00) >> 8; + HWREGB(ui32Base + UART_O_LBAUD) = ui32Div & 0x00FF; + + // + // Set parity, data length, and number of stop bits. + // + HWREGB(ui32Base + UART_O_CCR) = ((HWREGB(ui32Base + UART_O_CCR) & + ~(UART_CONFIG_PAR_MASK | UART_CONFIG_STOP_MASK | UART_CONFIG_WLEN_MASK)) + | ui32Config); + + + // + // Start the UART. + // + UARTEnable(ui32Base); +} + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e pui32Config is enumerated the same as the \e ui32Config parameter of +//! UARTConfigSetExpClk(). +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original UARTConfigGet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Compute the baud rate. + // + *pui32Baud = ui32UARTClk / ((1 + (HWREGB(ui32Base + UART_O_HBAUD) << 8 ) | HWREGB(ui32Base + UART_O_LBAUD)) * 8); + + // + // Get the parity, data length, and number of stop bits. + // + *pui32Config = HWREGB(ui32Base + UART_O_CCR) & + (UART_CONFIG_PAR_MASK | UART_CONFIG_STOP_MASK | UART_CONFIG_WLEN_MASK); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Enable RX, TX, and the UART. + // + HWREGB(ui32Base + UART_O_CTL1) |= (UART_CTL1_TXENA | UART_CTL1_RXENA | UART_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait for end of TX. + // + while(!(HWREGH(ui32Base + UART_O_CTL2) & UART_CTL2_TXEMPTY)) + { + } + + // + // Disable the FIFO. + // + HWREGH(ui32Base + UART_O_FFTX) &= ~(UART_FFTX_SCIFFENA); + + // + // Disable the UART. + // + HWREGB(ui32Base + UART_O_CTL1) &= ~(UART_CTL1_TXENA | UART_CTL1_RXENA); +} + +//***************************************************************************** +// +//! Enables Loop Back Test Mode. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Sets the SCICCR.LOOPBKENA to enable +//! +//! \return None. +// +//***************************************************************************** +void UARTsetLoopBack(uint32_t ui32Base, bool enable) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + if(enable) + { + // + // Enable LoopBack. + // + + HWREGB(ui32Base + UART_O_CCR) |= UART_CCR_LOOPBKENA; + } + else + { + // + // Disable LoopBack. + // + HWREGB(ui32Base + UART_O_CCR) &= ~UART_CCR_LOOPBKENA; + } +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Enable the FIFO. + // + HWREGH(ui32Base + UART_O_FFTX) |= UART_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFODisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Disable the FIFO. + // + HWREGH(ui32Base + UART_O_FFTX) &= ~UART_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Sets the operating mode for the UART transmit interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Mode is the operating mode for the transmit interrupt. It may be +//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle +//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO +//! level. +//! +//! This function allows the mode of the UART transmit interrupt to be set. By +//! default, the transmit interrupt is asserted when the FIFO level falls past +//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this +//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the +//! transmit interrupt will only be asserted once the transmitter is completely +//! idle - the transmit FIFO is empty and all bits, including any stop bits, +//! have cleared the transmitter. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Mode == UART_TXINT_MODE_EOT) || + (ui32Mode == UART_TXINT_MODE_FIFO_M)); + + // + // Set or clear the EOT bit of the UART control register as appropriate. + // + HWREGH(ui32Base + UART_O_FFTX) = ((HWREG(ui32Base + UART_O_FFTX) & ~(UART_TXINT_MODE_FIFO_M)) | ui32Mode); +} + +//***************************************************************************** +// +//! Returns the current operating mode for the UART transmit interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current operating mode for the UART transmit +//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the +//! transmit interrupt is currently set to be asserted once the transmitter is +//! completely idle - the transmit FIFO is empty and all bits, including any +//! stop bits, have cleared the transmitter. The return value will be \b +//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the +//! level of the transmit FIFO. +//! +//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. +// +//***************************************************************************** +uint32_t +UARTTxIntModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the current transmit interrupt mode. + // + return(HWREGH(ui32Base + UART_O_FFTX) & UART_TXINT_MODE_FIFO_M); +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO or \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +bool +UARTCharsAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the availability of characters. + // + if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA) + { + return(((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S) ? true : false); + + } + else + { + return((HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXRDY) ? true : false); + } +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO +//! or \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the availability of space. + // + return((HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) ? true : false); + +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! This function replaces the original UARTCharNonBlockingGet() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there are any characters in the receive FIFO. + // + if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA) + { + if((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S) + { + // + // Read and return the next character. + // + return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } + } + else + { + if((HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXRDY)) + { + // + // Read and return the next character. + // + return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } + } +} + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until a char is available. + // + + if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA) + { + while(!((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S)) + { + } + } + else + { + while(!(HWREGH(ui32Base + UART_O_RXST) & UART_RXST_RXRDY)) + { + + } + } + // + // Now get the char. + // + return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M); +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application must retry the function later. +//! +//! This function replaces the original UARTCharNonBlockingPut() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there is space in the transmit FIFO. + // + if(HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) + { + // + // Write this character to the transmit FIFO. + // + HWREGB(ui32Base + UART_O_TXBUF) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until space is available. + // + while(!(HWREGH(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY)) + { + } + + // + // Send the char. + // + HWREGB(ui32Base + UART_O_TXBUF) = ucData; +} + +//***************************************************************************** +// +//! Determines whether the UART transmitter is busy or not. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \b false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +bool +UARTBusy(uint32_t ui32Base) +{ + // + // Check the argument. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine if the UART is busy. + // + return((HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXEMPTY) ? false : true); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART RX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRXIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCIRXINTA : INT_SCIRXINTB ); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART TX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTXIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCITXINTA : INT_SCITXINTB ); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART RX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRXIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCIRXINTA : INT_SCIRXINTB ); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART TX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTXIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCITXINTA : INT_SCITXINTB ); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b UART_INT_OE - Overrun Error interrupt +//! - \b UART_INT_BE - Break Error interrupt +//! - \b UART_INT_PE - Parity Error interrupt +//! - \b UART_INT_FE - Framing Error interrupt +//! - \b UART_INT_RT - Receive Timeout interrupt +//! - \b UART_INT_TX - Transmit interrupt +//! - \b UART_INT_RX - Receive interrupt +//! - \b UART_INT_DSR - DSR interrupt +//! - \b UART_INT_DCD - DCD interrupt +//! - \b UART_INT_CTS - CTS interrupt +//! - \b UART_INT_RI - RI interrupt +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Enable the specified interrupts. + // + if(ui32IntFlags & UART_INT_RXERR) + HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_RXERRINTENA; + + if(ui32IntFlags & UART_INT_RXRDY_BRKDT) + HWREGB(ui32Base + UART_O_CTL2) |= UART_CTL2_RXBKINTENA; + + if(ui32IntFlags & UART_INT_TXRDY) + HWREGB(ui32Base + UART_O_CTL2) |= UART_CTL2_TXINTENA; + + if(ui32IntFlags & UART_INT_TXFF) + HWREGB(ui32Base + UART_O_FFTX) |= UART_FFTX_TXFFIENA; + + if(ui32IntFlags & UART_INT_RXFF) + HWREGB(ui32Base + UART_O_FFRX) |= UART_FFRX_RXFFIENA; + + +} + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the \e ui32IntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Disable the specified interrupts. + // + if(ui32IntFlags & UART_INT_RXERR) + HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_RXERRINTENA; + + if(ui32IntFlags & UART_INT_RXRDY_BRKDT) + HWREGB(ui32Base + UART_O_CTL2) &= ~UART_CTL2_RXBKINTENA; + + if(ui32IntFlags & UART_INT_TXRDY) + HWREGB(ui32Base + UART_O_CTL2) &= ~UART_CTL2_TXINTENA; + + if(ui32IntFlags & UART_INT_TXFF) + HWREGB(ui32Base + UART_O_FFTX) &= ~UART_FFTX_TXFFIENA; + + if(ui32IntFlags & UART_INT_RXFF) + HWREGB(ui32Base + UART_O_FFRX) &= ~UART_FFRX_RXFFIENA; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + + uint32_t temp = 0; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + + + if(HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) + temp |= UART_INT_TXRDY; + + if(HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXERROR) + temp |= UART_INT_RXERR; + + if(HWREGB(ui32Base + UART_O_RXST) & (UART_RXST_RXRDY | UART_RXST_BRKDT)) + temp |= UART_INT_RXRDY_BRKDT; + + if(HWREGB(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFINT) + temp |= UART_INT_TXFF; + + if(HWREGB(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFINT) + temp |= UART_INT_RXFF; + + return temp; +} + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the \e ui32IntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Clear the requested interrupt sources. + // + if(ui32IntFlags & (UART_INT_RXERR | UART_INT_RXRDY_BRKDT)) + { + HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_SWRESET; + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_SWRESET; + } + + if(ui32IntFlags & UART_INT_TXFF) + HWREGB(ui32Base + UART_O_FFTX) |= UART_FFTX_TXFFINTCLR; + + if(ui32IntFlags & UART_INT_RXFF) + HWREGB(ui32Base + UART_O_FFRX) |= UART_FFRX_RXFFINTCLR; + +} + +//***************************************************************************** +// +//! Gets current receiver errors. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK +//! and \b UART_RXERROR_OVERRUN. +// +//***************************************************************************** +uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the current value of the receive status register. + // + return(HWREGH(ui32Base + UART_O_RXST)); +} + +//***************************************************************************** +// +//! Clears all reported receiver errors. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRxErrorClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // To clear all errors a sw reset of the module is required + // + HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_SWRESET; + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_SWRESET; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tm4c129x-dk/libraries/driverlib/uart.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h similarity index 54% rename from bsp/tm4c129x-dk/libraries/driverlib/uart.h rename to bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h index 3a9397550d..ed13d30ec2 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/uart.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h @@ -1,44 +1,47 @@ -//***************************************************************************** +//########################################################################### // -// uart.h - Defines and Macros for the UART. +// FILE: uart.h // -// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// TITLE: Stellaris style wrapper driver for C28x SCI peripheral. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### -#ifndef __DRIVERLIB_UART_H__ -#define __DRIVERLIB_UART_H__ +#ifndef __UART_H__ +#define __UART_H__ //***************************************************************************** // @@ -57,20 +60,11 @@ extern "C" // as the ui32IntFlags parameter, and returned from UARTIntStatus. // //***************************************************************************** -#define UART_INT_DMATX 0x20000 // DMA TX interrupt -#define UART_INT_DMARX 0x10000 // DMA RX interrupt -#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask -#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask -#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask -#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask -#define UART_INT_RI 0x001 // RI Modem Interrupt Mask +#define UART_INT_RXERR 0x01 +#define UART_INT_RXRDY_BRKDT 0x02 +#define UART_INT_TXRDY 0x04 +#define UART_INT_TXFF 0x08 +#define UART_INT_RXFF 0x10 //***************************************************************************** // @@ -81,44 +75,42 @@ extern "C" // UARTParityModeGet. // //***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_WLEN_MASK 0x00000007 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000007 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000006 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000005 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000004 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000080 // Mask for extracting stop bits #define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_STOP_TWO 0x00000080 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000060 // Parity Mask #define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero +#define UART_CONFIG_PAR_EVEN 0x00000060 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000020 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000020 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000060 // Parity bit is zero //***************************************************************************** // -// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter and +// returned by UARTFIFOLevelGet in the pui32TxLevel. // //***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full +#define UART_FIFO_TX1_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX2_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX4_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX6_8 0x00000004 // Transmit interrupt Full //***************************************************************************** // -// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter and +// returned by UARTFIFOLevelGet in the pui32RxLevel. // //***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full +#define UART_FIFO_RX1_8 0x00000001 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX2_8 0x00000002 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX4_8 0x00000003 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX6_8 0x00000004 // Receive interrupt at Full //***************************************************************************** // @@ -135,9 +127,9 @@ extern "C" // //***************************************************************************** #define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 +#define UART_RXERROR_BREAK 0x00000020 +#define UART_RXERROR_PARITY 0x00000004 +#define UART_RXERROR_FRAMING 0x00000010 //***************************************************************************** // @@ -158,33 +150,14 @@ extern "C" #define UART_INPUT_DSR 0x00000002 #define UART_INPUT_CTS 0x00000001 -//***************************************************************************** -// -// Values that can be passed to UARTFlowControl() or returned from -// UARTFlowControlGet(). -// -//***************************************************************************** -#define UART_FLOWCONTROL_TX 0x00008000 -#define UART_FLOWCONTROL_RX 0x00004000 -#define UART_FLOWCONTROL_NONE 0x00000000 - //***************************************************************************** // // Values that can be passed to UARTTxIntModeSet() or returned from // UARTTxIntModeGet(). // //***************************************************************************** -#define UART_TXINT_MODE_FIFO 0x00000000 -#define UART_TXINT_MODE_EOT 0x00000010 - -//***************************************************************************** -// -// Values that can be passed to UARTClockSourceSet() or returned from -// UARTClockSourceGet(). -// -//***************************************************************************** -#define UART_CLOCK_SYSTEM 0x00000000 -#define UART_CLOCK_PIOSC 0x00000005 +#define UART_TXINT_MODE_FIFO_M 0x0000001F +#define UART_TXINT_MODE_EOT 0x00000000 //***************************************************************************** // @@ -193,8 +166,10 @@ extern "C" //***************************************************************************** extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity); extern uint32_t UARTParityModeGet(uint32_t ui32Base); -extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, +extern void UARTFIFOIntLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, uint32_t ui32RxLevel); +extern void UARTFIFOIntLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel); extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, @@ -203,46 +178,29 @@ extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config); extern void UARTEnable(uint32_t ui32Base); extern void UARTDisable(uint32_t ui32Base); +extern void UARTsetLoopBack(uint32_t ui32Base, bool enable); extern void UARTFIFOEnable(uint32_t ui32Base); extern void UARTFIFODisable(uint32_t ui32Base); -extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower); -extern void UARTDisableSIR(uint32_t ui32Base); extern bool UARTCharsAvail(uint32_t ui32Base); extern bool UARTSpaceAvail(uint32_t ui32Base); extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); extern int32_t UARTCharGet(uint32_t ui32Base); extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData); extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData); -extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState); extern bool UARTBusy(uint32_t ui32Base); -extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void UARTIntUnregister(uint32_t ui32Base); +extern void UARTRXIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void UARTTXIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void UARTRXIntUnregister(uint32_t ui32Base); +extern void UARTTXIntUnregister(uint32_t ui32Base); extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked); extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); -extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); extern uint32_t UARTRxErrorGet(uint32_t ui32Base); extern void UARTRxErrorClear(uint32_t ui32Base); -extern void UARTSmartCardEnable(uint32_t ui32Base); -extern void UARTSmartCardDisable(uint32_t ui32Base); -extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control); -extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control); -extern uint32_t UARTModemControlGet(uint32_t ui32Base); -extern uint32_t UARTModemStatusGet(uint32_t ui32Base); -extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode); -extern uint32_t UARTFlowControlGet(uint32_t ui32Base); extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode); extern uint32_t UARTTxIntModeGet(uint32_t ui32Base); -extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); -extern uint32_t UARTClockSourceGet(uint32_t ui32Base); -extern void UART9BitEnable(uint32_t ui32Base); -extern void UART9BitDisable(uint32_t ui32Base); -extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, - uint8_t ui8Mask); -extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr); -extern void UARTLoopbackEnable(uint32_t ui32Base); + //***************************************************************************** // @@ -253,4 +211,4 @@ extern void UARTLoopbackEnable(uint32_t ui32Base); } #endif -#endif // __DRIVERLIB_UART_H__ +#endif // __UART_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h new file mode 100644 index 0000000000..b3a09713c6 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h @@ -0,0 +1,1227 @@ +//########################################################################### +// +// FILE: hw_adc.h +// +// TITLE: Definitions for the C28x ADC registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets +// +//***************************************************************************** +#define ADC_O_CTL1 0x0 // ADC Control 1 Register +#define ADC_O_CTL2 0x1 // ADC Control 2 Register +#define ADC_O_BURSTCTL 0x2 // ADC Burst Control Register +#define ADC_O_INTFLG 0x3 // ADC Interrupt Flag Register +#define ADC_O_INTFLGCLR 0x4 // ADC Interrupt Flag Clear + // Register +#define ADC_O_INTOVF 0x5 // ADC Interrupt Overflow Register +#define ADC_O_INTOVFCLR 0x6 // ADC Interrupt Overflow Clear + // Register +#define ADC_O_INTSEL1N2 0x7 // ADC Interrupt 1 and 2 Selection + // Register +#define ADC_O_INTSEL3N4 0x8 // ADC Interrupt 3 and 4 Selection + // Register +#define ADC_O_SOCPRICTL 0x9 // ADC SOC Priority Control + // Register +#define ADC_O_INTSOCSEL1 0xA // ADC Interrupt SOC Selection 1 + // Register +#define ADC_O_INTSOCSEL2 0xB // ADC Interrupt SOC Selection 2 + // Register +#define ADC_O_SOCFLG1 0xC // ADC SOC Flag 1 Register +#define ADC_O_SOCFRC1 0xD // ADC SOC Force 1 Register +#define ADC_O_SOCOVF1 0xE // ADC SOC Overflow 1 Register +#define ADC_O_SOCOVFCLR1 0xF // ADC SOC Overflow Clear 1 + // Register +#define ADC_O_SOC0CTL 0x10 // ADC SOC0 Control Register +#define ADC_O_SOC1CTL 0x12 // ADC SOC1 Control Register +#define ADC_O_SOC2CTL 0x14 // ADC SOC2 Control Register +#define ADC_O_SOC3CTL 0x16 // ADC SOC3 Control Register +#define ADC_O_SOC4CTL 0x18 // ADC SOC4 Control Register +#define ADC_O_SOC5CTL 0x1A // ADC SOC5 Control Register +#define ADC_O_SOC6CTL 0x1C // ADC SOC6 Control Register +#define ADC_O_SOC7CTL 0x1E // ADC SOC7 Control Register +#define ADC_O_SOC8CTL 0x20 // ADC SOC8 Control Register +#define ADC_O_SOC9CTL 0x22 // ADC SOC9 Control Register +#define ADC_O_SOC10CTL 0x24 // ADC SOC10 Control Register +#define ADC_O_SOC11CTL 0x26 // ADC SOC11 Control Register +#define ADC_O_SOC12CTL 0x28 // ADC SOC12 Control Register +#define ADC_O_SOC13CTL 0x2A // ADC SOC13 Control Register +#define ADC_O_SOC14CTL 0x2C // ADC SOC14 Control Register +#define ADC_O_SOC15CTL 0x2E // ADC SOC15 Control Register +#define ADC_O_EVTSTAT 0x30 // ADC Event Status Register +#define ADC_O_EVTCLR 0x32 // ADC Event Clear Register +#define ADC_O_EVTSEL 0x34 // ADC Event Selection Register +#define ADC_O_EVTINTSEL 0x36 // ADC Event Interrupt Selection + // Register +#define ADC_O_COUNTER 0x39 // ADC Counter Register +#define ADC_O_REV 0x3A // ADC Revision Register +#define ADC_O_OFFTRIM 0x3B // ADC Offset Trim Register +#define ADC_O_PPB1CONFIG 0x40 // ADC PPB1 Config Register +#define ADC_O_PPB1STAMP 0x41 // ADC PPB1 Sample Delay Time + // Stamp Register +#define ADC_O_PPB1OFFCAL 0x42 // ADC PPB1 Offset Calibration + // Register +#define ADC_O_PPB1OFFREF 0x43 // ADC PPB1 Offset Reference + // Register +#define ADC_O_PPB1TRIPHI 0x44 // ADC PPB1 Trip High Register +#define ADC_O_PPB1TRIPLO 0x46 // ADC PPB1 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_PPB2CONFIG 0x48 // ADC PPB2 Config Register +#define ADC_O_PPB2STAMP 0x49 // ADC PPB2 Sample Delay Time + // Stamp Register +#define ADC_O_PPB2OFFCAL 0x4A // ADC PPB2 Offset Calibration + // Register +#define ADC_O_PPB2OFFREF 0x4B // ADC PPB2 Offset Reference + // Register +#define ADC_O_PPB2TRIPHI 0x4C // ADC PPB2 Trip High Register +#define ADC_O_PPB2TRIPLO 0x4E // ADC PPB2 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_PPB3CONFIG 0x50 // ADC PPB3 Config Register +#define ADC_O_PPB3STAMP 0x51 // ADC PPB3 Sample Delay Time + // Stamp Register +#define ADC_O_PPB3OFFCAL 0x52 // ADC PPB3 Offset Calibration + // Register +#define ADC_O_PPB3OFFREF 0x53 // ADC PPB3 Offset Reference + // Register +#define ADC_O_PPB3TRIPHI 0x54 // ADC PPB3 Trip High Register +#define ADC_O_PPB3TRIPLO 0x56 // ADC PPB3 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_PPB4CONFIG 0x58 // ADC PPB4 Config Register +#define ADC_O_PPB4STAMP 0x59 // ADC PPB4 Sample Delay Time + // Stamp Register +#define ADC_O_PPB4OFFCAL 0x5A // ADC PPB4 Offset Calibration + // Register +#define ADC_O_PPB4OFFREF 0x5B // ADC PPB4 Offset Reference + // Register +#define ADC_O_PPB4TRIPHI 0x5C // ADC PPB4 Trip High Register +#define ADC_O_PPB4TRIPLO 0x5E // ADC PPB4 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_RESULT0 0x0 // ADC Result 0 Register +#define ADC_O_RESULT1 0x1 // ADC Result 1 Register +#define ADC_O_RESULT2 0x2 // ADC Result 2 Register +#define ADC_O_RESULT3 0x3 // ADC Result 3 Register +#define ADC_O_RESULT4 0x4 // ADC Result 4 Register +#define ADC_O_RESULT5 0x5 // ADC Result 5 Register +#define ADC_O_RESULT6 0x6 // ADC Result 6 Register +#define ADC_O_RESULT7 0x7 // ADC Result 7 Register +#define ADC_O_RESULT8 0x8 // ADC Result 8 Register +#define ADC_O_RESULT9 0x9 // ADC Result 9 Register +#define ADC_O_RESULT10 0xA // ADC Result 10 Register +#define ADC_O_RESULT11 0xB // ADC Result 11 Register +#define ADC_O_RESULT12 0xC // ADC Result 12 Register +#define ADC_O_RESULT13 0xD // ADC Result 13 Register +#define ADC_O_RESULT14 0xE // ADC Result 14 Register +#define ADC_O_RESULT15 0xF // ADC Result 15 Register +#define ADC_O_PPB1RESULT 0x10 // ADC Post Processing Block 1 + // Result Register +#define ADC_O_PPB2RESULT 0x12 // ADC Post Processing Block 2 + // Result Register +#define ADC_O_PPB3RESULT 0x14 // ADC Post Processing Block 3 + // Result Register +#define ADC_O_PPB4RESULT 0x16 // ADC Post Processing Block 4 + // Result Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCCTL1 register +// +//***************************************************************************** +#define ADC_CTL1_INTPULSEPOS 0x4 // ADC Interrupt Pulse Position +#define ADC_CTL1_ADCPWDNZ 0x80 // ADC Power Down +#define ADC_CTL1_ADCBSYCHN_S 8 +#define ADC_CTL1_ADCBSYCHN_M 0xF00 // ADC Busy Channel +#define ADC_CTL1_ADCBSY 0x2000 // ADC Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCCTL2 register +// +//***************************************************************************** +#define ADC_CTL2_PRESCALE_S 0 +#define ADC_CTL2_PRESCALE_M 0xF // ADC Clock Prescaler +#define ADC_CTL2_RESOLUTION 0x40 // SOC Conversion Resolution +#define ADC_CTL2_SIGNALMODE 0x80 // SOC Signaling Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCBURSTCTL register +// +//***************************************************************************** +#define ADC_BURSTCTL_BURSTTRIGSEL_S 0 +#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3F // SOC Burst Trigger Source Select +#define ADC_BURSTCTL_BURSTSIZE_S 8 +#define ADC_BURSTCTL_BURSTSIZE_M 0xF00 // SOC Burst Size Select +#define ADC_BURSTCTL_BURSTEN 0x8000 // SOC Burst Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTFLG register +// +//***************************************************************************** +#define ADC_INTFLG_ADCINT1 0x1 // ADC Interrupt 1 Flag +#define ADC_INTFLG_ADCINT2 0x2 // ADC Interrupt 2 Flag +#define ADC_INTFLG_ADCINT3 0x4 // ADC Interrupt 3 Flag +#define ADC_INTFLG_ADCINT4 0x8 // ADC Interrupt 4 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTFLGCLR register +// +//***************************************************************************** +#define ADC_INTFLGCLR_ADCINT1 0x1 // ADC Interrupt 1 Flag Clear +#define ADC_INTFLGCLR_ADCINT2 0x2 // ADC Interrupt 2 Flag Clear +#define ADC_INTFLGCLR_ADCINT3 0x4 // ADC Interrupt 3 Flag Clear +#define ADC_INTFLGCLR_ADCINT4 0x8 // ADC Interrupt 4 Flag Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTOVF register +// +//***************************************************************************** +#define ADC_INTOVF_ADCINT1 0x1 // ADC Interrupt 1 Overflow Flags +#define ADC_INTOVF_ADCINT2 0x2 // ADC Interrupt 2 Overflow Flags +#define ADC_INTOVF_ADCINT3 0x4 // ADC Interrupt 3 Overflow Flags +#define ADC_INTOVF_ADCINT4 0x8 // ADC Interrupt 4 Overflow Flags + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTOVFCLR register +// +//***************************************************************************** +#define ADC_INTOVFCLR_ADCINT1 0x1 // ADC Interrupt 1 Overflow Clear + // Bits +#define ADC_INTOVFCLR_ADCINT2 0x2 // ADC Interrupt 2 Overflow Clear + // Bits +#define ADC_INTOVFCLR_ADCINT3 0x4 // ADC Interrupt 3 Overflow Clear + // Bits +#define ADC_INTOVFCLR_ADCINT4 0x8 // ADC Interrupt 4 Overflow Clear + // Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSEL1N2 register +// +//***************************************************************************** +#define ADC_INTSEL1N2_INT1SEL_S 0 +#define ADC_INTSEL1N2_INT1SEL_M 0xF // ADCINT1 EOC Source Select +#define ADC_INTSEL1N2_INT1E 0x20 // ADCINT1 Interrupt Enable +#define ADC_INTSEL1N2_INT1CONT 0x40 // ADCINT1 Continuous Mode Enable +#define ADC_INTSEL1N2_INT2SEL_S 8 +#define ADC_INTSEL1N2_INT2SEL_M 0xF00 // ADCINT2 EOC Source Select +#define ADC_INTSEL1N2_INT2E 0x2000 // ADCINT2 Interrupt Enable +#define ADC_INTSEL1N2_INT2CONT 0x4000 // ADCINT2 Continuous Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSEL3N4 register +// +//***************************************************************************** +#define ADC_INTSEL3N4_INT3SEL_S 0 +#define ADC_INTSEL3N4_INT3SEL_M 0xF // ADCINT3 EOC Source Select +#define ADC_INTSEL3N4_INT3E 0x20 // ADCINT3 Interrupt Enable +#define ADC_INTSEL3N4_INT3CONT 0x40 // ADCINT3 Continuous Mode Enable +#define ADC_INTSEL3N4_INT4SEL_S 8 +#define ADC_INTSEL3N4_INT4SEL_M 0xF00 // ADCINT4 EOC Source Select +#define ADC_INTSEL3N4_INT4E 0x2000 // ADCINT4 Interrupt Enable +#define ADC_INTSEL3N4_INT4CONT 0x4000 // ADCINT4 Continuous Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCPRICTL register +// +//***************************************************************************** +#define ADC_SOCPRICTL_SOCPRIORITY_S 0 +#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1F // SOC Priority +#define ADC_SOCPRICTL_RRPOINTER_S 5 +#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0 // Round Robin Pointer + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSOCSEL1 register +// +//***************************************************************************** +#define ADC_INTSOCSEL1_SOC0_S 0 +#define ADC_INTSOCSEL1_SOC0_M 0x3 // SOC0 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC1_S 2 +#define ADC_INTSOCSEL1_SOC1_M 0xC // SOC1 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC2_S 4 +#define ADC_INTSOCSEL1_SOC2_M 0x30 // SOC2 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC3_S 6 +#define ADC_INTSOCSEL1_SOC3_M 0xC0 // SOC3 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC4_S 8 +#define ADC_INTSOCSEL1_SOC4_M 0x300 // SOC4 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC5_S 10 +#define ADC_INTSOCSEL1_SOC5_M 0xC00 // SOC5 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC6_S 12 +#define ADC_INTSOCSEL1_SOC6_M 0x3000 // SOC6 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC7_S 14 +#define ADC_INTSOCSEL1_SOC7_M 0xC000 // SOC7 ADC Interrupt Trigger + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSOCSEL2 register +// +//***************************************************************************** +#define ADC_INTSOCSEL2_SOC8_S 0 +#define ADC_INTSOCSEL2_SOC8_M 0x3 // SOC8 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC9_S 2 +#define ADC_INTSOCSEL2_SOC9_M 0xC // SOC9 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC10_S 4 +#define ADC_INTSOCSEL2_SOC10_M 0x30 // SOC10 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC11_S 6 +#define ADC_INTSOCSEL2_SOC11_M 0xC0 // SOC11 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC12_S 8 +#define ADC_INTSOCSEL2_SOC12_M 0x300 // SOC12 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC13_S 10 +#define ADC_INTSOCSEL2_SOC13_M 0xC00 // SOC13 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC14_S 12 +#define ADC_INTSOCSEL2_SOC14_M 0x3000 // SOC14 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC15_S 14 +#define ADC_INTSOCSEL2_SOC15_M 0xC000 // SOC15 ADC Interrupt Trigger + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCFLG1 register +// +//***************************************************************************** +#define ADC_SOCFLG1_SOC0 0x1 // SOC0 Start of Conversion Flag +#define ADC_SOCFLG1_SOC1 0x2 // SOC1 Start of Conversion Flag +#define ADC_SOCFLG1_SOC2 0x4 // SOC2 Start of Conversion Flag +#define ADC_SOCFLG1_SOC3 0x8 // SOC3 Start of Conversion Flag +#define ADC_SOCFLG1_SOC4 0x10 // SOC4 Start of Conversion Flag +#define ADC_SOCFLG1_SOC5 0x20 // SOC5 Start of Conversion Flag +#define ADC_SOCFLG1_SOC6 0x40 // SOC6 Start of Conversion Flag +#define ADC_SOCFLG1_SOC7 0x80 // SOC7 Start of Conversion Flag +#define ADC_SOCFLG1_SOC8 0x100 // SOC8 Start of Conversion Flag +#define ADC_SOCFLG1_SOC9 0x200 // SOC9 Start of Conversion Flag +#define ADC_SOCFLG1_SOC10 0x400 // SOC10 Start of Conversion Flag +#define ADC_SOCFLG1_SOC11 0x800 // SOC11 Start of Conversion Flag +#define ADC_SOCFLG1_SOC12 0x1000 // SOC12 Start of Conversion Flag +#define ADC_SOCFLG1_SOC13 0x2000 // SOC13 Start of Conversion Flag +#define ADC_SOCFLG1_SOC14 0x4000 // SOC14 Start of Conversion Flag +#define ADC_SOCFLG1_SOC15 0x8000 // SOC15 Start of Conversion Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCFRC1 register +// +//***************************************************************************** +#define ADC_SOCFRC1_SOC0 0x1 // SOC0 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC1 0x2 // SOC1 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC2 0x4 // SOC2 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC3 0x8 // SOC3 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC4 0x10 // SOC4 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC5 0x20 // SOC5 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC6 0x40 // SOC6 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC7 0x80 // SOC7 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC8 0x100 // SOC8 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC9 0x200 // SOC9 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC10 0x400 // SOC10 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC11 0x800 // SOC11 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC12 0x1000 // SOC12 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC13 0x2000 // SOC13 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC14 0x4000 // SOC14 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC15 0x8000 // SOC15 Force Start of Conversion + // Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCOVF1 register +// +//***************************************************************************** +#define ADC_SOCOVF1_SOC0 0x1 // SOC0 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC1 0x2 // SOC1 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC2 0x4 // SOC2 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC3 0x8 // SOC3 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC4 0x10 // SOC4 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC5 0x20 // SOC5 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC6 0x40 // SOC6 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC7 0x80 // SOC7 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC8 0x100 // SOC8 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC9 0x200 // SOC9 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC10 0x400 // SOC10 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC11 0x800 // SOC11 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC12 0x1000 // SOC12 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC13 0x2000 // SOC13 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC14 0x4000 // SOC14 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC15 0x8000 // SOC15 Start of Conversion + // Overflow Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCOVFCLR1 register +// +//***************************************************************************** +#define ADC_SOCOVFCLR1_SOC0 0x1 // SOC0 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC1 0x2 // SOC1 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC2 0x4 // SOC2 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC3 0x8 // SOC3 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC4 0x10 // SOC4 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC5 0x20 // SOC5 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC6 0x40 // SOC6 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC7 0x80 // SOC7 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC8 0x100 // SOC8 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC9 0x200 // SOC9 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC10 0x400 // SOC10 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC11 0x800 // SOC11 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC12 0x1000 // SOC12 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC13 0x2000 // SOC13 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC14 0x4000 // SOC14 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC15 0x8000 // SOC15 Clear Start of Conversion + // Overflow Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC0CTL register +// +//***************************************************************************** +#define ADC_SOC0CTL_ACQPS_S 0 +#define ADC_SOC0CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC0CTL_CHSEL_S 15 +#define ADC_SOC0CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC0CTL_TRIGSEL_S 20 +#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC1CTL register +// +//***************************************************************************** +#define ADC_SOC1CTL_ACQPS_S 0 +#define ADC_SOC1CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC1CTL_CHSEL_S 15 +#define ADC_SOC1CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC1CTL_TRIGSEL_S 20 +#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC2CTL register +// +//***************************************************************************** +#define ADC_SOC2CTL_ACQPS_S 0 +#define ADC_SOC2CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC2CTL_CHSEL_S 15 +#define ADC_SOC2CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC2CTL_TRIGSEL_S 20 +#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC3CTL register +// +//***************************************************************************** +#define ADC_SOC3CTL_ACQPS_S 0 +#define ADC_SOC3CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC3CTL_CHSEL_S 15 +#define ADC_SOC3CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC3CTL_TRIGSEL_S 20 +#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC4CTL register +// +//***************************************************************************** +#define ADC_SOC4CTL_ACQPS_S 0 +#define ADC_SOC4CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC4CTL_CHSEL_S 15 +#define ADC_SOC4CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC4CTL_TRIGSEL_S 20 +#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC5CTL register +// +//***************************************************************************** +#define ADC_SOC5CTL_ACQPS_S 0 +#define ADC_SOC5CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC5CTL_CHSEL_S 15 +#define ADC_SOC5CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC5CTL_TRIGSEL_S 20 +#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC6CTL register +// +//***************************************************************************** +#define ADC_SOC6CTL_ACQPS_S 0 +#define ADC_SOC6CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC6CTL_CHSEL_S 15 +#define ADC_SOC6CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC6CTL_TRIGSEL_S 20 +#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC7CTL register +// +//***************************************************************************** +#define ADC_SOC7CTL_ACQPS_S 0 +#define ADC_SOC7CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC7CTL_CHSEL_S 15 +#define ADC_SOC7CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC7CTL_TRIGSEL_S 20 +#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC8CTL register +// +//***************************************************************************** +#define ADC_SOC8CTL_ACQPS_S 0 +#define ADC_SOC8CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC8CTL_CHSEL_S 15 +#define ADC_SOC8CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC8CTL_TRIGSEL_S 20 +#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC9CTL register +// +//***************************************************************************** +#define ADC_SOC9CTL_ACQPS_S 0 +#define ADC_SOC9CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC9CTL_CHSEL_S 15 +#define ADC_SOC9CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC9CTL_TRIGSEL_S 20 +#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC10CTL register +// +//***************************************************************************** +#define ADC_SOC10CTL_ACQPS_S 0 +#define ADC_SOC10CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC10CTL_CHSEL_S 15 +#define ADC_SOC10CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC10CTL_TRIGSEL_S 20 +#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC11CTL register +// +//***************************************************************************** +#define ADC_SOC11CTL_ACQPS_S 0 +#define ADC_SOC11CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC11CTL_CHSEL_S 15 +#define ADC_SOC11CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC11CTL_TRIGSEL_S 20 +#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC12CTL register +// +//***************************************************************************** +#define ADC_SOC12CTL_ACQPS_S 0 +#define ADC_SOC12CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC12CTL_CHSEL_S 15 +#define ADC_SOC12CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC12CTL_TRIGSEL_S 20 +#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC13CTL register +// +//***************************************************************************** +#define ADC_SOC13CTL_ACQPS_S 0 +#define ADC_SOC13CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC13CTL_CHSEL_S 15 +#define ADC_SOC13CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC13CTL_TRIGSEL_S 20 +#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC14CTL register +// +//***************************************************************************** +#define ADC_SOC14CTL_ACQPS_S 0 +#define ADC_SOC14CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC14CTL_CHSEL_S 15 +#define ADC_SOC14CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC14CTL_TRIGSEL_S 20 +#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC15CTL register +// +//***************************************************************************** +#define ADC_SOC15CTL_ACQPS_S 0 +#define ADC_SOC15CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC15CTL_CHSEL_S 15 +#define ADC_SOC15CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC15CTL_TRIGSEL_S 20 +#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTSTAT register +// +//***************************************************************************** +#define ADC_EVTSTAT_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Flag +#define ADC_EVTSTAT_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Flag +#define ADC_EVTSTAT_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Flag +#define ADC_EVTSTAT_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Flag +#define ADC_EVTSTAT_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Flag +#define ADC_EVTSTAT_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Flag +#define ADC_EVTSTAT_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Flag +#define ADC_EVTSTAT_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Flag +#define ADC_EVTSTAT_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Flag +#define ADC_EVTSTAT_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Flag +#define ADC_EVTSTAT_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Flag +#define ADC_EVTSTAT_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTCLR register +// +//***************************************************************************** +#define ADC_EVTCLR_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Clear +#define ADC_EVTCLR_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Clear +#define ADC_EVTCLR_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Clear +#define ADC_EVTCLR_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Clear +#define ADC_EVTCLR_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Clear +#define ADC_EVTCLR_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Clear +#define ADC_EVTCLR_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Clear +#define ADC_EVTCLR_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Clear +#define ADC_EVTCLR_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Clear +#define ADC_EVTCLR_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Clear +#define ADC_EVTCLR_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Clear +#define ADC_EVTCLR_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTSEL register +// +//***************************************************************************** +#define ADC_EVTSEL_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Event Enable +#define ADC_EVTSEL_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Event Enable +#define ADC_EVTSEL_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Event Enable +#define ADC_EVTSEL_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Event Enable +#define ADC_EVTSEL_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Event Enable +#define ADC_EVTSEL_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Event Enable +#define ADC_EVTSEL_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Event Enable +#define ADC_EVTSEL_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Event Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTINTSEL register +// +//***************************************************************************** +#define ADC_EVTINTSEL_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCCOUNTER register +// +//***************************************************************************** +#define ADC_COUNTER_FREECOUNT_S 0 +#define ADC_COUNTER_FREECOUNT_M 0xFFF // ADC Free Running Counter Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCREV register +// +//***************************************************************************** +#define ADC_REV_TYPE_S 0 +#define ADC_REV_TYPE_M 0xFF // ADC Type +#define ADC_REV_REV_S 8 +#define ADC_REV_REV_M 0xFF00 // ADC Revision + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCOFFTRIM register +// +//***************************************************************************** +#define ADC_OFFTRIM_OFFTRIM_S 0 +#define ADC_OFFTRIM_OFFTRIM_M 0xFF // ADC Offset Trim + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1CONFIG register +// +//***************************************************************************** +#define ADC_PPB1CONFIG_CONFIG_S 0 +#define ADC_PPB1CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1STAMP register +// +//***************************************************************************** +#define ADC_PPB1STAMP_DLYSTAMP_S 0 +#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1OFFCAL register +// +//***************************************************************************** +#define ADC_PPB1OFFCAL_OFFCAL_S 0 +#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1OFFREF register +// +//***************************************************************************** +#define ADC_PPB1OFFREF_OFFREF_S 0 +#define ADC_PPB1OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1TRIPHI register +// +//***************************************************************************** +#define ADC_PPB1TRIPHI_LIMITHI_S 0 +#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB1TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1TRIPLO register +// +//***************************************************************************** +#define ADC_PPB1TRIPLO_LIMITLO_S 0 +#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB1TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB1TRIPLO_REQSTAMP_S 20 +#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2CONFIG register +// +//***************************************************************************** +#define ADC_PPB2CONFIG_CONFIG_S 0 +#define ADC_PPB2CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2STAMP register +// +//***************************************************************************** +#define ADC_PPB2STAMP_DLYSTAMP_S 0 +#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2OFFCAL register +// +//***************************************************************************** +#define ADC_PPB2OFFCAL_OFFCAL_S 0 +#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2OFFREF register +// +//***************************************************************************** +#define ADC_PPB2OFFREF_OFFREF_S 0 +#define ADC_PPB2OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2TRIPHI register +// +//***************************************************************************** +#define ADC_PPB2TRIPHI_LIMITHI_S 0 +#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB2TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2TRIPLO register +// +//***************************************************************************** +#define ADC_PPB2TRIPLO_LIMITLO_S 0 +#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB2TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB2TRIPLO_REQSTAMP_S 20 +#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3CONFIG register +// +//***************************************************************************** +#define ADC_PPB3CONFIG_CONFIG_S 0 +#define ADC_PPB3CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3STAMP register +// +//***************************************************************************** +#define ADC_PPB3STAMP_DLYSTAMP_S 0 +#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3OFFCAL register +// +//***************************************************************************** +#define ADC_PPB3OFFCAL_OFFCAL_S 0 +#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3OFFREF register +// +//***************************************************************************** +#define ADC_PPB3OFFREF_OFFREF_S 0 +#define ADC_PPB3OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3TRIPHI register +// +//***************************************************************************** +#define ADC_PPB3TRIPHI_LIMITHI_S 0 +#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB3TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3TRIPLO register +// +//***************************************************************************** +#define ADC_PPB3TRIPLO_LIMITLO_S 0 +#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB3TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB3TRIPLO_REQSTAMP_S 20 +#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4CONFIG register +// +//***************************************************************************** +#define ADC_PPB4CONFIG_CONFIG_S 0 +#define ADC_PPB4CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4STAMP register +// +//***************************************************************************** +#define ADC_PPB4STAMP_DLYSTAMP_S 0 +#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4OFFCAL register +// +//***************************************************************************** +#define ADC_PPB4OFFCAL_OFFCAL_S 0 +#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4OFFREF register +// +//***************************************************************************** +#define ADC_PPB4OFFREF_OFFREF_S 0 +#define ADC_PPB4OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4TRIPHI register +// +//***************************************************************************** +#define ADC_PPB4TRIPHI_LIMITHI_S 0 +#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB4TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4TRIPLO register +// +//***************************************************************************** +#define ADC_PPB4TRIPLO_LIMITLO_S 0 +#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB4TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB4TRIPLO_REQSTAMP_S 20 +#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT0 register +// +//***************************************************************************** +#define ADC_RESULT0_RESULT_S 0 +#define ADC_RESULT0_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT1 register +// +//***************************************************************************** +#define ADC_RESULT1_RESULT_S 0 +#define ADC_RESULT1_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT2 register +// +//***************************************************************************** +#define ADC_RESULT2_RESULT_S 0 +#define ADC_RESULT2_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT3 register +// +//***************************************************************************** +#define ADC_RESULT3_RESULT_S 0 +#define ADC_RESULT3_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT4 register +// +//***************************************************************************** +#define ADC_RESULT4_RESULT_S 0 +#define ADC_RESULT4_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT5 register +// +//***************************************************************************** +#define ADC_RESULT5_RESULT_S 0 +#define ADC_RESULT5_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT6 register +// +//***************************************************************************** +#define ADC_RESULT6_RESULT_S 0 +#define ADC_RESULT6_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT7 register +// +//***************************************************************************** +#define ADC_RESULT7_RESULT_S 0 +#define ADC_RESULT7_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT8 register +// +//***************************************************************************** +#define ADC_RESULT8_RESULT_S 0 +#define ADC_RESULT8_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT9 register +// +//***************************************************************************** +#define ADC_RESULT9_RESULT_S 0 +#define ADC_RESULT9_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT10 register +// +//***************************************************************************** +#define ADC_RESULT10_RESULT_S 0 +#define ADC_RESULT10_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT11 register +// +//***************************************************************************** +#define ADC_RESULT11_RESULT_S 0 +#define ADC_RESULT11_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT12 register +// +//***************************************************************************** +#define ADC_RESULT12_RESULT_S 0 +#define ADC_RESULT12_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT13 register +// +//***************************************************************************** +#define ADC_RESULT13_RESULT_S 0 +#define ADC_RESULT13_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT14 register +// +//***************************************************************************** +#define ADC_RESULT14_RESULT_S 0 +#define ADC_RESULT14_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT15 register +// +//***************************************************************************** +#define ADC_RESULT15_RESULT_S 0 +#define ADC_RESULT15_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1RESULT register +// +//***************************************************************************** +#define ADC_PPB1RESULT_PPBRESULT_S 0 +#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB1RESULT_SIGN_S 16 +#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2RESULT register +// +//***************************************************************************** +#define ADC_PPB2RESULT_PPBRESULT_S 0 +#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB2RESULT_SIGN_S 16 +#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3RESULT register +// +//***************************************************************************** +#define ADC_PPB3RESULT_PPBRESULT_S 0 +#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB3RESULT_SIGN_S 16 +#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4RESULT register +// +//***************************************************************************** +#define ADC_PPB4RESULT_PPBRESULT_S 0 +#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB4RESULT_SIGN_S 16 +#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h new file mode 100644 index 0000000000..f421a0caf8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h @@ -0,0 +1,612 @@ +//########################################################################### +// +// FILE: hw_can.h +// +// TITLE: Definitions for the C28x CAN registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following are defines for the CAN register offsets +// +//***************************************************************************** +#define CAN_O_CTL 0x0 // CAN Control Register +#define CAN_O_ES 0x4 // Error and Status Register +#define CAN_O_ERRC 0x8 // Error Counter Register +#define CAN_O_BTR 0xC // Bit Timing Register +#define CAN_O_INT 0x10 // Interrupt Register +#define CAN_O_TEST 0x14 // Test Register +#define CAN_O_PERR 0x1C // CAN Parity Error Code Register +#define CAN_O_REL 0x20 // CAN Core Release Register +#define CAN_O_RAM_INIT 0x40 // CAN RAM Initialization Register +#define CAN_O_GLB_INT_EN 0x50 // CAN Global Interrupt Enable + // Register +#define CAN_O_GLB_INT_FLG 0x54 // CAN Global Interrupt Flag + // Register +#define CAN_O_GLB_INT_CLR 0x58 // CAN Global Interrupt Clear + // Register +#define CAN_O_ABOTR 0x80 // Auto-Bus-On Time Register +#define CAN_O_TXRQ_X 0x84 // CAN Transmission Request X + // Register +#define CAN_O_TXRQ_21 0x88 // CAN Transmission Request 2_1 + // Register +#define CAN_O_NDAT_X 0x98 // CAN New Data X Register +#define CAN_O_NDAT_21 0x9C // CAN New Data 2_1 Register +#define CAN_O_IPEN_X 0xAC // CAN Interrupt Pending X + // Register +#define CAN_O_IPEN_21 0xB0 // CAN Interrupt Pending 2_1 + // Register +#define CAN_O_MVAL_X 0xC0 // CAN Message Valid X Register +#define CAN_O_MVAL_21 0xC4 // CAN Message Valid 2_1 Register +#define CAN_O_IP_MUX21 0xD8 // CAN Interrupt Multiplexer 2_1 + // Register +#define CAN_O_IF1CMD 0x100 // IF1 Command Register +#define CAN_O_IF1MSK 0x104 // IF1 Mask Register +#define CAN_O_IF1ARB 0x108 // IF1 Arbitration Register +#define CAN_O_IF1MCTL 0x10C // IF1 Message Control Register +#define CAN_O_IF1DATA 0x110 // IF1 Data A Register +#define CAN_O_IF1DATB 0x114 // IF1 Data B Register +#define CAN_O_IF2CMD 0x120 // IF2 Command Register +#define CAN_O_IF2MSK 0x124 // IF2 Mask Register +#define CAN_O_IF2ARB 0x128 // IF2 Arbitration Register +#define CAN_O_IF2MCTL 0x12C // IF2 Message Control Register +#define CAN_O_IF2DATA 0x130 // IF2 Data A Register +#define CAN_O_IF2DATB 0x134 // IF2 Data B Register +#define CAN_O_IF3OBS 0x140 // IF3 Observation Register +#define CAN_O_IF3MSK 0x144 // IF3 Mask Register +#define CAN_O_IF3ARB 0x148 // IF3 Arbitration Register +#define CAN_O_IF3MCTL 0x14C // IF3 Message Control Register +#define CAN_O_IF3DATA 0x150 // IF3 Data A Register +#define CAN_O_IF3DATB 0x154 // IF3 Data B Register +#define CAN_O_IF3UPD 0x160 // IF3 Update Enable Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_CTL register +// +//***************************************************************************** +#define CAN_CTL_INIT 0x1 // Initialization +#define CAN_CTL_IE0 0x2 // Interrupt line 0 Enable + // Disabled +#define CAN_CTL_SIE 0x4 // Status Change Interrupt Enable + // Disabled +#define CAN_CTL_EIE 0x8 // Error Interrupt Enable Disabled +#define CAN_CTL_DAR 0x20 // Disable Automatic + // Retransmission +#define CAN_CTL_CCE 0x40 // Configuration Change Enable +#define CAN_CTL_TEST 0x80 // Test Mode Enable +#define CAN_CTL_IDS 0x100 // Interruption Debug Support + // Enable +#define CAN_CTL_ABO 0x200 // Auto-Bus-On Enable +#define CAN_CTL_PMD_S 10 +#define CAN_CTL_PMD_M 0x3C00 // Parity on/off +#define CAN_CTL_SWR 0x8000 // SW Reset Enable +#define CAN_CTL_INITDBG 0x10000 // Debug Mode Status +#define CAN_CTL_IE1 0x20000 // Interrupt line 1 Enable + // Disabled +#define CAN_CTL_PDR 0x1000000 // Power Down Request Mode +#define CAN_CTL_WUBA 0x2000000 // Wake Up on Bus Activity + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ES register +// +//***************************************************************************** +#define CAN_ES_LEC_S 0 +#define CAN_ES_LEC_M 0x7 // Last Error Code +#define CAN_ES_TXOK 0x8 // Transmission status +#define CAN_ES_RXOK 0x10 // Reception status +#define CAN_ES_EPASS 0x20 // Error Passive State +#define CAN_ES_EWARN 0x40 // Warning State +#define CAN_ES_BOFF 0x80 // Bus-Off State +#define CAN_ES_PER 0x100 // Parity Error Detected +#define CAN_ES_WAKEUPPND 0x200 // Wake Up Pending +#define CAN_ES_PDA 0x400 // Power down mode acknowledge + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ERRC register +// +//***************************************************************************** +#define CAN_ERRC_TEC_S 0 +#define CAN_ERRC_TEC_M 0xFF // Transmit Error Counter +#define CAN_ERRC_REC_S 8 +#define CAN_ERRC_REC_M 0x7F00 // Receive Error Counter +#define CAN_ERRC_RP 0x8000 // Receive Error Passive + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_BTR register +// +//***************************************************************************** +#define CAN_BTR_BRP_S 0 +#define CAN_BTR_BRP_M 0x3F // Baud Rate Prescaler +#define CAN_BTR_SJW_S 6 +#define CAN_BTR_SJW_M 0xC0 // Synchronization Jump Width +#define CAN_BTR_TSEG1_S 8 +#define CAN_BTR_TSEG1_M 0xF00 // Time segment +#define CAN_BTR_TSEG2_S 12 +#define CAN_BTR_TSEG2_M 0x7000 // Time segment +#define CAN_BTR_BRPE_S 16 +#define CAN_BTR_BRPE_M 0xF0000 // Baud Rate Prescaler Extension + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_INT register +// +//***************************************************************************** +#define CAN_INT_INT0ID_S 0 +#define CAN_INT_INT0ID_M 0xFFFF // Interrupt Identifier +#define CAN_INT_INT1ID_S 16 +#define CAN_INT_INT1ID_M 0xFF0000 // Interrupt 1 Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TEST register +// +//***************************************************************************** +#define CAN_TEST_SILENT 0x8 // Silent Mode +#define CAN_TEST_LBACK 0x10 // Loopback Mode +#define CAN_TEST_TX_S 5 +#define CAN_TEST_TX_M 0x60 // CANTX Pin Control +#define CAN_TEST_RX 0x80 // CANRX Pin Status +#define CAN_TEST_EXL 0x100 // External Loopback Mode +#define CAN_TEST_RDA 0x200 // RAM Direct Access Enable: + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_PERR register +// +//***************************************************************************** +#define CAN_PERR_MSG_NUM_S 0 +#define CAN_PERR_MSG_NUM_M 0xFF // Message Number +#define CAN_PERR_WORD_NUM_S 8 +#define CAN_PERR_WORD_NUM_M 0x700 // Word Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_REL register +// +//***************************************************************************** +#define CAN_REL_DAY_S 0 +#define CAN_REL_DAY_M 0xFF // Day +#define CAN_REL_MON_S 8 +#define CAN_REL_MON_M 0xFF00 // Month +#define CAN_REL_YEAR_S 16 +#define CAN_REL_YEAR_M 0xF0000 // Year +#define CAN_REL_SUBSTEP_S 20 +#define CAN_REL_SUBSTEP_M 0xF00000 // Substep +#define CAN_REL_STEP_S 24 +#define CAN_REL_STEP_M 0xF000000 // Step +#define CAN_REL_REL_S 28 +#define CAN_REL_REL_M 0xF0000000 // Release + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_RAM_INIT register +// +//***************************************************************************** +#define CAN_RAM_INIT_KEY0 0x1 // KEY0 +#define CAN_RAM_INIT_KEY1 0x2 // KEY1 +#define CAN_RAM_INIT_KEY2 0x4 // KEY2 +#define CAN_RAM_INIT_KEY3 0x8 // KEY3 +#define CAN_RAM_INIT_CAN_RAM_INIT 0x10 // Initialize CAN Mailbox RAM +#define CAN_RAM_INIT_RAM_INIT_DONE 0x20 // CAN RAM initialization complete + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_GLB_INT_EN register +// +//***************************************************************************** +#define CAN_GLB_INT_CANINT0 0x1 // Global Interrupt Enable for CAN INT0 +#define CAN_GLB_INT_CANINT1 0x2 // Global Interrupt Enable for CAN INT1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_GLB_INT_FLG register +// +//***************************************************************************** +#define CAN_GLB_INT_FLG_NAME 0x1 // Global Interrupt Flag for CAN + // INT0 +#define CAN_GLB_INT_FLG_INT1_FLG 0x2 // Global Interrupt Flag for CAN + // INT1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_GLB_INT_CLR register +// +//***************************************************************************** +#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1 // Global Interrupt flag clear for + // CAN INT0 +#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2 // Global Interrupt flag clear + // for CAN INT1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ABOTR register +// +//***************************************************************************** +#define CAN_ABOTR_ABO_TIME_S 0 +#define CAN_ABOTR_ABO_TIME_M 0xFFFFFFFF // Auto-Bus-On Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ_X register +// +//***************************************************************************** +#define CAN_TXRQ_X_TXRQSTREG1_S 0 +#define CAN_TXRQ_X_TXRQSTREG1_M 0x3 // Transmit Request Register 1 +#define CAN_TXRQ_X_TXRQSTREG2_S 2 +#define CAN_TXRQ_X_TXRQSTREG2_M 0xC // Transmit Request Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ_21 register +// +//***************************************************************************** +#define CAN_TXRQ_21_TXRQST_S 0 +#define CAN_TXRQ_21_TXRQST_M 0xFFFFFFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NDAT_X register +// +//***************************************************************************** +#define CAN_NDAT_X_NEWDATREG1_S 0 +#define CAN_NDAT_X_NEWDATREG1_M 0x3 // New Data Register 1 +#define CAN_NDAT_X_NEWDATREG2_S 2 +#define CAN_NDAT_X_NEWDATREG2_M 0xC // New Data Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NDAT_21 register +// +//***************************************************************************** +#define CAN_NDAT_21_NEWDAT_S 0 +#define CAN_NDAT_21_NEWDAT_M 0xFFFFFFFF // New Data Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IPEN_X register +// +//***************************************************************************** +#define CAN_IPEN_X_INTPNDREG1_S 0 +#define CAN_IPEN_X_INTPNDREG1_M 0x3 // Interrupt Pending Register 1 +#define CAN_IPEN_X_INTPNDREG2_S 2 +#define CAN_IPEN_X_INTPNDREG2_M 0xC // Interrupt Pending Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IPEN_21 register +// +//***************************************************************************** +#define CAN_IPEN_21_INTPND_S 0 +#define CAN_IPEN_21_INTPND_M 0xFFFFFFFF // Interrupt Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_MVAL_X register +// +//***************************************************************************** +#define CAN_MVAL_X_MSGVALREG1_S 0 +#define CAN_MVAL_X_MSGVALREG1_M 0x3 // Message Valid Register 1 +#define CAN_MVAL_X_MSGVALREG2_S 2 +#define CAN_MVAL_X_MSGVALREG2_M 0xC // Message Valid Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_MVAL_21 register +// +//***************************************************************************** +#define CAN_MVAL_21_MSGVALREG_S 0 +#define CAN_MVAL_21_MSGVALREG_M 0xFFFFFFFF // Message Valid Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IP_MUX21 register +// +//***************************************************************************** +#define CAN_IP_MUX21_INTMUX_S 0 +#define CAN_IP_MUX21_INTMUX_M 0xFFFFFFFF // Interrupt Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1CMD register +// +//***************************************************************************** +#define CAN_IF1CMD_MSG_NUM_S 0 +#define CAN_IF1CMD_MSG_NUM_M 0xFF // Message Number +#define CAN_IF1CMD_BUSY 0x8000 // Busy Flag +#define CAN_IF1CMD_DATA_B 0x10000 // Access Data Bytes 4-7 +#define CAN_IF1CMD_DATA_A 0x20000 // Access Data Bytes 0-3 +#define CAN_IF1CMD_TXRQST 0x40000 // Access Transmission Request Bit +#define CAN_IF1CMD_CLRINTPND 0x80000 // Clear Interrupt Pending Bit +#define CAN_IF1CMD_CONTROL 0x100000 // Access Control Bits +#define CAN_IF1CMD_ARB 0x200000 // Access Arbitration Bits +#define CAN_IF1CMD_MASK 0x400000 // Access Mask Bits +#define CAN_IF1CMD_DIR 0x800000 // Write/Read Direction + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1MSK register +// +//***************************************************************************** +#define CAN_IF1MSK_MSK_S 0 +#define CAN_IF1MSK_MSK_M 0x1FFFFFFF // Identifier Mask +#define CAN_IF1MSK_MDIR 0x40000000 // Mask Message Direction +#define CAN_IF1MSK_MXTD 0x80000000 // Mask Extended Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1ARB register +// +//***************************************************************************** +#define CAN_IF1ARB_ID_S 0 +#define CAN_IF1ARB_ID_M 0x1FFFFFFF // ` +#define CAN_IF1ARB_DIR 0x20000000 // Message Direction +#define CAN_IF1ARB_XTD 0x40000000 // Extended Identifier +#define CAN_IF1ARB_MSGVAL 0x80000000 // Message Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1MCTL register +// +//***************************************************************************** +#define CAN_IF1MCTL_DLC_S 0 +#define CAN_IF1MCTL_DLC_M 0xF // Data length code +#define CAN_IF1MCTL_EOB 0x80 // End of Block +#define CAN_IF1MCTL_TXRQST 0x100 // Transmit Request +#define CAN_IF1MCTL_RMTEN 0x200 // Remote Enable +#define CAN_IF1MCTL_RXIE 0x400 // Receive Interrupt Enable +#define CAN_IF1MCTL_TXIE 0x800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_UMASK 0x1000 // Use Acceptance Mask +#define CAN_IF1MCTL_INTPND 0x2000 // Interrupt Pending +#define CAN_IF1MCTL_MSGLST 0x4000 // Message Lost +#define CAN_IF1MCTL_NEWDAT 0x8000 // New Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1DATA register +// +//***************************************************************************** +#define CAN_IF1DATA_DATA_0_S 0 +#define CAN_IF1DATA_DATA_0_M 0xFF // Data Byte 0 +#define CAN_IF1DATA_DATA_1_S 8 +#define CAN_IF1DATA_DATA_1_M 0xFF00 // Data Byte 1 +#define CAN_IF1DATA_DATA_2_S 16 +#define CAN_IF1DATA_DATA_2_M 0xFF0000 // Data Byte 2 +#define CAN_IF1DATA_DATA_3_S 24 +#define CAN_IF1DATA_DATA_3_M 0xFF000000 // Data Byte 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1DATB register +// +//***************************************************************************** +#define CAN_IF1DATB_DATA_4_S 0 +#define CAN_IF1DATB_DATA_4_M 0xFF // Data Byte 4 +#define CAN_IF1DATB_DATA_5_S 8 +#define CAN_IF1DATB_DATA_5_M 0xFF00 // Data Byte 5 +#define CAN_IF1DATB_DATA_6_S 16 +#define CAN_IF1DATB_DATA_6_M 0xFF0000 // Data Byte 6 +#define CAN_IF1DATB_DATA_7_S 24 +#define CAN_IF1DATB_DATA_7_M 0xFF000000 // Data Byte 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2CMD register +// +//***************************************************************************** +#define CAN_IF2CMD_MSG_NUM_S 0 +#define CAN_IF2CMD_MSG_NUM_M 0xFF // Message Number +#define CAN_IF2CMD_BUSY 0x8000 // Busy Flag +#define CAN_IF2CMD_DATA_B 0x10000 // Access Data Bytes 4-7 +#define CAN_IF2CMD_DATA_A 0x20000 // Access Data Bytes 0-3 +#define CAN_IF2CMD_TXRQST 0x40000 // Access Transmission Request Bit +#define CAN_IF2CMD_CLRINTPND 0x80000 // Clear Interrupt Pending Bit +#define CAN_IF2CMD_CONTROL 0x100000 // Access Control Bits +#define CAN_IF2CMD_ARB 0x200000 // Access Arbitration Bits +#define CAN_IF2CMD_MASK 0x400000 // Access Mask Bits +#define CAN_IF2CMD_DIR 0x800000 // Write/Read Direction + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2MSK register +// +//***************************************************************************** +#define CAN_IF2MSK_MSK_S 0 +#define CAN_IF2MSK_MSK_M 0x1FFFFFFF // Identifier Mask +#define CAN_IF2MSK_MDIR 0x40000000 // Mask Message Direction +#define CAN_IF2MSK_MXTD 0x80000000 // Mask Extended Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2ARB register +// +//***************************************************************************** +#define CAN_IF2ARB_ID_S 0 +#define CAN_IF2ARB_ID_M 0x1FFFFFFF // Message Identifier +#define CAN_IF2ARB_DIR 0x20000000 // Message Direction +#define CAN_IF2ARB_XTD 0x40000000 // Extended Identifier +#define CAN_IF2ARB_MSGVAL 0x80000000 // Message Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2MCTL register +// +//***************************************************************************** +#define CAN_IF2MCTL_DLC_S 0 +#define CAN_IF2MCTL_DLC_M 0xF // Data length code +#define CAN_IF2MCTL_EOB 0x80 // End of Block +#define CAN_IF2MCTL_TXRQST 0x100 // Transmit Request +#define CAN_IF2MCTL_RMTEN 0x200 // Remote Enable +#define CAN_IF2MCTL_RXIE 0x400 // Receive Interrupt Enable +#define CAN_IF2MCTL_TXIE 0x800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_UMASK 0x1000 // Use Acceptance Mask +#define CAN_IF2MCTL_INTPND 0x2000 // Interrupt Pending +#define CAN_IF2MCTL_MSGLST 0x4000 // Message Lost +#define CAN_IF2MCTL_NEWDAT 0x8000 // New Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2DATA register +// +//***************************************************************************** +#define CAN_IF2DATA_DATA_0_S 0 +#define CAN_IF2DATA_DATA_0_M 0xFF // Data Byte 0 +#define CAN_IF2DATA_DATA_1_S 8 +#define CAN_IF2DATA_DATA_1_M 0xFF00 // Data Byte 1 +#define CAN_IF2DATA_DATA_2_S 16 +#define CAN_IF2DATA_DATA_2_M 0xFF0000 // Data Byte 2 +#define CAN_IF2DATA_DATA_3_S 24 +#define CAN_IF2DATA_DATA_3_M 0xFF000000 // Data Byte 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2DATB register +// +//***************************************************************************** +#define CAN_IF2DATB_DATA_4_S 0 +#define CAN_IF2DATB_DATA_4_M 0xFF // Data Byte 4 +#define CAN_IF2DATB_DATA_5_S 8 +#define CAN_IF2DATB_DATA_5_M 0xFF00 // Data Byte 5 +#define CAN_IF2DATB_DATA_6_S 16 +#define CAN_IF2DATB_DATA_6_M 0xFF0000 // Data Byte 6 +#define CAN_IF2DATB_DATA_7_S 24 +#define CAN_IF2DATB_DATA_7_M 0xFF000000 // Data Byte 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3OBS register +// +//***************************************************************************** +#define CAN_IF3OBS_MASK 0x1 // Mask data read observation +#define CAN_IF3OBS_ARB 0x2 // Arbitration data read + // observation +#define CAN_IF3OBS_CTRL 0x4 // Ctrl read observation +#define CAN_IF3OBS_DATA_A 0x8 // Data A read observation +#define CAN_IF3OBS_DATA_B 0x10 // Data B read observation +#define CAN_IF3OBS_IF3SM 0x100 // IF3 Status of Mask data read + // access +#define CAN_IF3OBS_IF3SA 0x200 // IF3 Status of Arbitration data + // read access +#define CAN_IF3OBS_IF3SC 0x400 // IF3 Status of Control bits read + // access +#define CAN_IF3OBS_IF3SDA 0x800 // IF3 Status of Data A read + // access +#define CAN_IF3OBS_IF3SDB 0x1000 // IF3 Status of Data B read + // access +#define CAN_IF3OBS_IF3UPD 0x8000 // IF3 Update Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3MSK register +// +//***************************************************************************** +#define CAN_IF3MSK_MSK_S 0 +#define CAN_IF3MSK_MSK_M 0x1FFFFFFF // Mask +#define CAN_IF3MSK_MDIR 0x40000000 // Mask Message Direction +#define CAN_IF3MSK_MXTD 0x80000000 // Mask Extended Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3ARB register +// +//***************************************************************************** +#define CAN_IF3ARB_ID_S 0 +#define CAN_IF3ARB_ID_M 0x1FFFFFFF // Message Identifier +#define CAN_IF3ARB_DIR 0x20000000 // Message Direction +#define CAN_IF3ARB_XTD 0x40000000 // Extended Identifier +#define CAN_IF3ARB_MSGVAL 0x80000000 // Message Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3MCTL register +// +//***************************************************************************** +#define CAN_IF3MCTL_DLC_S 0 +#define CAN_IF3MCTL_DLC_M 0xF // Data length code +#define CAN_IF3MCTL_EOB 0x80 // End of Block +#define CAN_IF3MCTL_TXRQST 0x100 // Transmit Request +#define CAN_IF3MCTL_RMTEN 0x200 // Remote Enable +#define CAN_IF3MCTL_RXIE 0x400 // Receive Interrupt Enable +#define CAN_IF3MCTL_TXIE 0x800 // Transmit Interrupt Enable +#define CAN_IF3MCTL_UMASK 0x1000 // Use Acceptance Mask +#define CAN_IF3MCTL_INTPND 0x2000 // Interrupt Pending +#define CAN_IF3MCTL_MSGLST 0x4000 // Message Lost +#define CAN_IF3MCTL_NEWDAT 0x8000 // New Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3DATA register +// +//***************************************************************************** +#define CAN_IF3DATA_DATA_0_S 0 +#define CAN_IF3DATA_DATA_0_M 0xFF // Data Byte 0 +#define CAN_IF3DATA_DATA_1_S 8 +#define CAN_IF3DATA_DATA_1_M 0xFF00 // Data Byte 1 +#define CAN_IF3DATA_DATA_2_S 16 +#define CAN_IF3DATA_DATA_2_M 0xFF0000 // Data Byte 2 +#define CAN_IF3DATA_DATA_3_S 24 +#define CAN_IF3DATA_DATA_3_M 0xFF000000 // Data Byte 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3DATB register +// +//***************************************************************************** +#define CAN_IF3DATB_DATA_4_S 0 +#define CAN_IF3DATB_DATA_4_M 0xFF // Data Byte 4 +#define CAN_IF3DATB_DATA_5_S 8 +#define CAN_IF3DATB_DATA_5_M 0xFF00 // Data Byte 5 +#define CAN_IF3DATB_DATA_6_S 16 +#define CAN_IF3DATB_DATA_6_M 0xFF0000 // Data Byte 6 +#define CAN_IF3DATB_DATA_7_S 24 +#define CAN_IF3DATB_DATA_7_M 0xFF000000 // Data Byte 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3UPD register +// +//***************************************************************************** +#define CAN_IF3UPD_IF3UPDEN_S 0 +#define CAN_IF3UPD_IF3UPDEN_M 0xFFFFFFFF // IF3 Update Enabled +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h new file mode 100644 index 0000000000..c87a8840e8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h @@ -0,0 +1,295 @@ +//########################################################################### +// +// FILE: hw_cmpss.h +// +// TITLE: Definitions for the C28x CMPSS registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_CMPSS_H__ +#define __HW_CMPSS_H__ + +//***************************************************************************** +// +// The following are defines for the CMPSS register offsets +// +//***************************************************************************** +#define CMPSS_O_COMPCTL 0x0 // CMPSS Comparator Control + // Register +#define CMPSS_O_COMPHYSCTL 0x1 // CMPSS Comparator Hysteresis + // Control Register +#define CMPSS_O_COMPSTS 0x2 // CMPSS Comparator Status + // Register +#define CMPSS_O_COMPSTSCLR 0x3 // CMPSS Comparator Status Clear + // Register +#define CMPSS_O_COMPDACCTL 0x4 // CMPSS DAC Control Register +#define CMPSS_O_DACHVALS 0x6 // CMPSS High DAC Value Shadow + // Register +#define CMPSS_O_DACHVALA 0x7 // CMPSS High DAC Value Active + // Register +#define CMPSS_O_RAMPMAXREFA 0x8 // CMPSS Ramp Max Reference Active + // Register +#define CMPSS_O_RAMPMAXREFS 0xA // CMPSS Ramp Max Reference Shadow + // Register +#define CMPSS_O_RAMPDECVALA 0xC // CMPSS Ramp Decrement Value + // Active Register +#define CMPSS_O_RAMPDECVALS 0xE // CMPSS Ramp Decrement Value + // Shadow Register +#define CMPSS_O_RAMPSTS 0x10 // CMPSS Ramp Status Register +#define CMPSS_O_DACLVALS 0x12 // CMPSS Low DAC Value Shadow + // Register +#define CMPSS_O_DACLVALA 0x13 // CMPSS Low DAC Value Active + // Register +#define CMPSS_O_RAMPDLYA 0x14 // CMPSS Ramp Delay Active + // Register +#define CMPSS_O_RAMPDLYS 0x15 // CMPSS Ramp Delay Shadow + // Register +#define CMPSS_O_CTRIPLFILCTL 0x16 // CTRIPL Filter Control Register +#define CMPSS_O_CTRIPLFILCLKCTL 0x17 // CTRIPL Filter Clock Control + // Register +#define CMPSS_O_CTRIPHFILCTL 0x18 // CTRIPH Filter Control Register +#define CMPSS_O_CTRIPHFILCLKCTL 0x19 // CTRIPH Filter Clock Control + // Register +#define CMPSS_O_COMPLOCK 0x1A // CMPSS Lock Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPCTL register +// +//***************************************************************************** +#define CMPSS_COMPCTL_COMPHSOURCE 0x1 // High Comparator Source Select +#define CMPSS_COMPCTL_COMPHINV 0x2 // High Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPHSEL_S 2 +#define CMPSS_COMPCTL_CTRIPHSEL_M 0xC // High Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4 +#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30 // High Comparator Trip Output + // Select +#define CMPSS_COMPCTL_ASYNCHEN 0x40 // High Comparator Asynchronous + // Path Enable +#define CMPSS_COMPCTL_COMPLSOURCE 0x100 // Low Comparator Source Select +#define CMPSS_COMPCTL_COMPLINV 0x200 // Low Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPLSEL_S 10 +#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00 // Low Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12 +#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000 // Low Comparator Trip Output + // Select +#define CMPSS_COMPCTL_ASYNCLEN 0x4000 // Low Comparator Asynchronous + // Path Enable +#define CMPSS_COMPCTL_COMPDACE 0x8000 // Comparator/DAC Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPHYSCTL register +// +//***************************************************************************** +#define CMPSS_COMPHYSCTL_COMPHYS_S 0 +#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7 // Comparator Hysteresis Trim + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPSTS register +// +//***************************************************************************** +#define CMPSS_COMPSTS_COMPHSTS 0x1 // High Comparator Status +#define CMPSS_COMPSTS_COMPHLATCH 0x2 // High Comparator Latched Status +#define CMPSS_COMPSTS_COMPLSTS 0x100 // Low Comparator Status +#define CMPSS_COMPSTS_COMPLLATCH 0x200 // Low Comparator Latched Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPSTSCLR register +// +//***************************************************************************** +#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2 // High Comparator Latched Status + // Clear +#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4 // High Comparator PWMSYNC Clear + // Enable +#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200 // Low Comparator Latched Status + // Clear +#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400 // Low Comparator PWMSYNC Clear + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPDACCTL register +// +//***************************************************************************** +#define CMPSS_COMPDACCTL_DACSOURCE 0x1 // DAC Source Control +#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1 +#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1E // Ramp Generator Source Control +#define CMPSS_COMPDACCTL_SELREF 0x20 // DAC Reference Select +#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40 // Ramp Load Select +#define CMPSS_COMPDACCTL_SWLOADSEL 0x80 // Software Load Select +#define CMPSS_COMPDACCTL_FREESOFT_S 14 +#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000 // Free/Soft Emulation Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACHVALS register +// +//***************************************************************************** +#define CMPSS_DACHVALS_DACVAL_S 0 +#define CMPSS_DACHVALS_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACHVALA register +// +//***************************************************************************** +#define CMPSS_DACHVALA_DACVAL_S 0 +#define CMPSS_DACHVALA_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPMAXREFA register +// +//***************************************************************************** +#define CMPSS_RAMPMAXREFA_RAMPMAXREF_S 0 +#define CMPSS_RAMPMAXREFA_RAMPMAXREF_M 0xFFFF // Ramp Maximum Reference Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPMAXREFS register +// +//***************************************************************************** +#define CMPSS_RAMPMAXREFS_RAMPMAXREF_S 0 +#define CMPSS_RAMPMAXREFS_RAMPMAXREF_M 0xFFFF // Ramp Maximum Reference Shadow + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDECVALA register +// +//***************************************************************************** +#define CMPSS_RAMPDECVALA_RAMPDECVAL_S 0 +#define CMPSS_RAMPDECVALA_RAMPDECVAL_M 0xFFFF // Ramp Decrement Value Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDECVALS register +// +//***************************************************************************** +#define CMPSS_RAMPDECVALS_RAMPDECVAL_S 0 +#define CMPSS_RAMPDECVALS_RAMPDECVAL_M 0xFFFF // Ramp Decrement Value Shadow + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPSTS register +// +//***************************************************************************** +#define CMPSS_RAMPSTS_RAMPVALUE_S 0 +#define CMPSS_RAMPSTS_RAMPVALUE_M 0xFFFF // Ramp Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACLVALS register +// +//***************************************************************************** +#define CMPSS_DACLVALS_DACVAL_S 0 +#define CMPSS_DACLVALS_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACLVALA register +// +//***************************************************************************** +#define CMPSS_DACLVALA_DACVAL_S 0 +#define CMPSS_DACLVALA_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDLYA register +// +//***************************************************************************** +#define CMPSS_RAMPDLYA_DELAY_S 0 +#define CMPSS_RAMPDLYA_DELAY_M 0x1FFF // Ramp Delay Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDLYS register +// +//***************************************************************************** +#define CMPSS_RAMPDLYS_DELAY_S 0 +#define CMPSS_RAMPDLYS_DELAY_M 0x1FFF // Ramp Delay Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPLFILCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4 +#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0 // Sample Window +#define CMPSS_CTRIPLFILCTL_THRESH_S 9 +#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00 // Majority Voting Threshold +#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000 // Filter Initialization Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPLFILCLKCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0 +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FF // Sample Clock Prescale + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPHFILCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4 +#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0 // Sample Window +#define CMPSS_CTRIPHFILCTL_THRESH_S 9 +#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00 // Majority Voting Threshold +#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000 // Filter Initialization Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPHFILCLKCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0 +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FF // Sample Clock Prescale + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPLOCK register +// +//***************************************************************************** +#define CMPSS_COMPLOCK_COMPCTL 0x1 // COMPCTL Lock +#define CMPSS_COMPLOCK_COMPHYSCTL 0x2 // COMPHYSCTL Lock +#define CMPSS_COMPLOCK_DACCTL 0x4 // DACCTL Lock +#define CMPSS_COMPLOCK_CTRIP 0x8 // CTRIP Lock +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h new file mode 100644 index 0000000000..c29d0dbcb2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h @@ -0,0 +1,125 @@ +//########################################################################### +// +// FILE: hw_cputimer.h +// +// TITLE: Definitions for the C28x CPUTIMER registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_CPUTIMER_H__ +#define __HW_CPUTIMER_H__ + +//***************************************************************************** +// +// The following are defines for the CPUTIMER register offsets +// +//***************************************************************************** +#define CPUTIMER_O_TIM 0x0 // CPU-Timer, Counter Register +#define CPUTIMER_O_TIMH 0x1 // CPU-Timer, Counter Register + // High +#define CPUTIMER_O_PRD 0x2 // CPU-Timer, Period Register +#define CPUTIMER_O_PRDH 0x3 // CPU-Timer, Period Register High +#define CPUTIMER_O_TCR 0x4 // CPU-Timer, Control Register +#define CPUTIMER_O_TPR 0x6 // CPU-Timer, Prescale Register +#define CPUTIMER_O_TPRH 0x7 // CPU-Timer, Prescale Register + // High + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIM register +// +//***************************************************************************** +#define CPUTIMER_TIM_TIM_S 0 +#define CPUTIMER_TIM_TIM_M 0xFFFF // CPU-Timer Counter Registers + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMH register +// +//***************************************************************************** +#define CPUTIMER_TIMH_TIMH_S 0 +#define CPUTIMER_TIMH_TIMH_M 0xFFFF // CPU-Timer Counter Registers + // High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PRD register +// +//***************************************************************************** +#define CPUTIMER_PRD_PRD_S 0 +#define CPUTIMER_PRD_PRD_M 0xFFFF // CPU-Timer Period Registers + +//***************************************************************************** +// +// The following are defines for the bit fields in the PRDH register +// +//***************************************************************************** +#define CPUTIMER_PRDH_PRDH_S 0 +#define CPUTIMER_PRDH_PRDH_M 0xFFFF // CPU-Timer Period Registers High + +//***************************************************************************** +// +// The following are defines for the bit fields in the TCR register +// +//***************************************************************************** +#define CPUTIMER_TCR_TSS 0x10 // CPU-Timer stop status bit. +#define CPUTIMER_TCR_TRB 0x20 // Timer reload +#define CPUTIMER_TCR_FREE_SOFT_S 10 +#define CPUTIMER_TCR_FREE_SOFT_M 0xC00 // Emulation modes +#define CPUTIMER_TCR_TIE 0x4000 // CPU-Timer Interrupt Enable. +#define CPUTIMER_TCR_TIF 0x8000 // CPU-Timer Interrupt Flag. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TPR register +// +//***************************************************************************** +#define CPUTIMER_TPR_TDDR_S 0 +#define CPUTIMER_TPR_TDDR_M 0xFF // CPU-Timer Divide-Down. +#define CPUTIMER_TPR_PSC_S 8 +#define CPUTIMER_TPR_PSC_M 0xFF00 // CPU-Timer Prescale Counter. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TPRH register +// +//***************************************************************************** +#define CPUTIMER_TPRH_TDDRH_S 0 +#define CPUTIMER_TPRH_TDDRH_M 0xFF // CPU-Timer Divide-Down. +#define CPUTIMER_TPRH_PSCH_S 8 +#define CPUTIMER_TPRH_PSCH_M 0xFF00 // CPU-Timer Prescale Counter. +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h new file mode 100644 index 0000000000..ed45234ce1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h @@ -0,0 +1,220 @@ +//########################################################################### +// +// FILE: hw_ecap.h +// +// TITLE: Definitions for the C28x ECAP registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_ECAP_H__ +#define __HW_ECAP_H__ + +//***************************************************************************** +// +// The following are defines for the ECAP register offsets +// +//***************************************************************************** +#define ECAP_O_TSCTR 0x0 // Time-Stamp Counter +#define ECAP_O_CTRPHS 0x2 // Counter Phase Offset Value + // Register +#define ECAP_O_CAP1 0x4 // Capture 1 Register +#define ECAP_O_CAP2 0x6 // Capture 2 Register +#define ECAP_O_CAP3 0x8 // Capture 3Register +#define ECAP_O_CAP4 0xA // Capture 4 Register +#define ECAP_O_ECCTL1 0x14 // Capture Control Register 1 +#define ECAP_O_ECCTL2 0x15 // Capture Control Register 2 +#define ECAP_O_ECEINT 0x16 // Capture Interrupt Enable + // Register +#define ECAP_O_ECFLG 0x17 // Capture Interrupt Flag Register +#define ECAP_O_ECCLR 0x18 // Capture Interrupt Flag Register +#define ECAP_O_ECFRC 0x19 // Capture Interrupt Force + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TSCTR register +// +//***************************************************************************** +#define ECAP_TSCTR_TSCTR_S 0 +#define ECAP_TSCTR_TSCTR_M 0xFFFFFFFF // Time Stamp Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRPHS register +// +//***************************************************************************** +#define ECAP_CTRPHS_CTRPHS_S 0 +#define ECAP_CTRPHS_CTRPHS_M 0xFFFFFFFF // Counter phase + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP1 register +// +//***************************************************************************** +#define ECAP_CAP1_CAP1_S 0 +#define ECAP_CAP1_CAP1_M 0xFFFFFFFF // Capture 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP2 register +// +//***************************************************************************** +#define ECAP_CAP2_CAP2_S 0 +#define ECAP_CAP2_CAP2_M 0xFFFFFFFF // Capture 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP3 register +// +//***************************************************************************** +#define ECAP_CAP3_CAP3_S 0 +#define ECAP_CAP3_CAP3_M 0xFFFFFFFF // Capture 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP4 register +// +//***************************************************************************** +#define ECAP_CAP4_CAP4_S 0 +#define ECAP_CAP4_CAP4_M 0xFFFFFFFF // Capture 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECCTL1 register +// +//***************************************************************************** +#define ECAP_ECCTL1_CAP1POL 0x1 // Capture Event 1 Polarity select +#define ECAP_ECCTL1_CTRRST1 0x2 // Counter Reset on Capture Event + // 1 +#define ECAP_ECCTL1_CAP2POL 0x4 // Capture Event 2 Polarity select +#define ECAP_ECCTL1_CTRRST2 0x8 // Counter Reset on Capture Event + // 2 +#define ECAP_ECCTL1_CAP3POL 0x10 // Capture Event 3 Polarity select +#define ECAP_ECCTL1_CTRRST3 0x20 // Counter Reset on Capture Event + // 3 +#define ECAP_ECCTL1_CAP4POL 0x40 // Capture Event 4 Polarity select +#define ECAP_ECCTL1_CTRRST4 0x80 // Counter Reset on Capture Event + // 4 +#define ECAP_ECCTL1_CAPLDEN 0x100 // Enable Loading CAP1-4 regs on a + // Cap Event +#define ECAP_ECCTL1_PRESCALE_S 9 +#define ECAP_ECCTL1_PRESCALE_M 0x3E00 // Event Filter prescale select +#define ECAP_ECCTL1_FREE_SOFT_S 14 +#define ECAP_ECCTL1_FREE_SOFT_M 0xC000 // Emulation mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECCTL2 register +// +//***************************************************************************** +#define ECAP_ECCTL2_CONT_ONESHT 0x1 // Continuous or one-shot +#define ECAP_ECCTL2_STOP_WRAP_S 1 +#define ECAP_ECCTL2_STOP_WRAP_M 0x6 // Stop value for one-shot, Wrap + // for continuous +#define ECAP_ECCTL2_RE_ARM 0x8 // One-shot re-arm +#define ECAP_ECCTL2_TSCTRSTOP 0x10 // TSCNT counter stop +#define ECAP_ECCTL2_SYNCI_EN 0x20 // Counter sync-in select +#define ECAP_ECCTL2_SYNCO_SEL_S 6 +#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0 // Sync-out mode +#define ECAP_ECCTL2_SWSYNC 0x100 // SW forced counter sync +#define ECAP_ECCTL2_CAP_APWM 0x200 // CAP/APWM operating mode select +#define ECAP_ECCTL2_APWMPOL 0x400 // APWM output polarity select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECEINT register +// +//***************************************************************************** +#define ECAP_ECEINT_CEVT1 0x2 // Capture Event 1 Interrupt + // Enable +#define ECAP_ECEINT_CEVT2 0x4 // Capture Event 2 Interrupt + // Enable +#define ECAP_ECEINT_CEVT3 0x8 // Capture Event 3 Interrupt + // Enable +#define ECAP_ECEINT_CEVT4 0x10 // Capture Event 4 Interrupt + // Enable +#define ECAP_ECEINT_CTROVF 0x20 // Counter Overflow Interrupt + // Enable +#define ECAP_ECEINT_CTR_PRD 0x40 // Period Equal Interrupt Enable +#define ECAP_ECEINT_CTR_CMP 0x80 // Compare Equal Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECFLG register +// +//***************************************************************************** +#define ECAP_ECFLG_INT 0x1 // Global Flag +#define ECAP_ECFLG_CEVT1 0x2 // Capture Event 1 Interrupt Flag +#define ECAP_ECFLG_CEVT2 0x4 // Capture Event 2 Interrupt Flag +#define ECAP_ECFLG_CEVT3 0x8 // Capture Event 3 Interrupt Flag +#define ECAP_ECFLG_CEVT4 0x10 // Capture Event 4 Interrupt Flag +#define ECAP_ECFLG_CTROVF 0x20 // Counter Overflow Interrupt Flag +#define ECAP_ECFLG_CTR_PRD 0x40 // Period Equal Interrupt Flag +#define ECAP_ECFLG_CTR_CMP 0x80 // Compare Equal Interrupt Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECCLR register +// +//***************************************************************************** +#define ECAP_ECCLR_INT 0x1 // Global Flag +#define ECAP_ECCLR_CEVT1 0x2 // Capture Event 1 Interrupt Flag +#define ECAP_ECCLR_CEVT2 0x4 // Capture Event 2 Interrupt Flag +#define ECAP_ECCLR_CEVT3 0x8 // Capture Event 3 Interrupt Flag +#define ECAP_ECCLR_CEVT4 0x10 // Capture Event 4 Interrupt Flag +#define ECAP_ECCLR_CTROVF 0x20 // Counter Overflow Interrupt Flag +#define ECAP_ECCLR_CTR_PRD 0x40 // Period Equal Interrupt Flag +#define ECAP_ECCLR_CTR_CMP 0x80 // Compare Equal Interrupt Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECFRC register +// +//***************************************************************************** +#define ECAP_ECFRC_CEVT1 0x2 // Capture Event 1 Interrupt + // Enable +#define ECAP_ECFRC_CEVT2 0x4 // Capture Event 2 Interrupt + // Enable +#define ECAP_ECFRC_CEVT3 0x8 // Capture Event 3 Interrupt + // Enable +#define ECAP_ECFRC_CEVT4 0x10 // Capture Event 4 Interrupt + // Enable +#define ECAP_ECFRC_CTROVF 0x20 // Counter Overflow Interrupt + // Enable +#define ECAP_ECFRC_CTR_PRD 0x40 // Period Equal Interrupt Enable +#define ECAP_ECFRC_CTR_CMP 0x80 // Compare Equal Interrupt Enable +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h new file mode 100644 index 0000000000..f753222091 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h @@ -0,0 +1,372 @@ +//########################################################################### +// +// FILE: hw_emif.h +// +// TITLE: Definitions for the C28x EMIF registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_EMIF_H__ +#define __HW_EMIF_H__ + +//***************************************************************************** +// +// The following are defines for the EMIF register offsets +// +//***************************************************************************** +#define EMIF_O_RCSR 0x0 // Revision Code and Status + // Register +#define EMIF_O_ASYNC_WCCR 0x2 // Async Wait Cycle Config + // Register +#define EMIF_O_SDRAM_CR 0x4 // SDRAM + // (pad_cs_o_n[0]/pad_cs_o_n[1]) + // Config Register +#define EMIF_O_SDRAM_RCR 0x6 // SDRAM Refresh Control Register +#define EMIF_O_ASYNC_CS2_CR 0x8 // Async 1 (pad_cs_o_n[2]) Config + // Register +#define EMIF_O_ASYNC_CS3_CR 0xA // Async 2 (pad_cs_o_n[3]) Config + // Register +#define EMIF_O_ASYNC_CS4_CR 0xC // Async 3 (pad_cs_o_n[4]) Config + // Register +#define EMIF_O_ASYNC_CS5_CR 0xE // Async 4 (pad_cs_o_n[5]) Config + // Register +#define EMIF_O_SDRAM_TR 0x10 // SDRAM Timing Register +#define EMIF_O_TOTAL_SDRAM_AR 0x18 // Total SDRAM Accesses Register +#define EMIF_O_TOTAL_SDRAM_ACTR 0x1A // Total SDRAM Activate Register +#define EMIF_O_SDR_EXT_TMNG 0x1E // SDRAM SR/PD Exit Timing + // Register +#define EMIF_O_INT_RAW 0x20 // Interrupt Raw Register +#define EMIF_O_INT_MSK 0x22 // Interrupt Masked Register +#define EMIF_O_INT_MSK_SET 0x24 // Interrupt Mask Set Register +#define EMIF_O_INT_MSK_CLR 0x26 // Interrupt Mask Clear Register +#define EMIF_O_IO_CTRL 0x28 // IO Control Register +#define EMIF_O_IO_STAT 0x2A // IO Status Register +#define EMIF_O_MODEL_REL_NUM 0x56 // Module Release Number Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the RCSR register +// +//***************************************************************************** +#define EMIF_RCSR_MINOR_REVISION_S 0 +#define EMIF_RCSR_MINOR_REVISION_M 0xFF // Minor Revision. +#define EMIF_RCSR_MAJOR_REVISION_S 8 +#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00 // Major Revision. +#define EMIF_RCSR_MODULE_ID_S 16 +#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000 // EMIF module ID. +#define EMIF_RCSR_FR 0x40000000 // EMIF is running in full rate or + // half rate. +#define EMIF_RCSR_BE 0x80000000 // EMIF endian mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_WCCR register +// +//***************************************************************************** +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0 +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFF // Maximum Extended Wait cycles. +#define EMIF_ASYNC_WCCR_CS2_WAIT_S 16 +#define EMIF_ASYNC_WCCR_CS2_WAIT_M 0x30000 // Maps the wait signal for chip + // select 2. +#define EMIF_ASYNC_WCCR_CS3_WAIT_S 18 +#define EMIF_ASYNC_WCCR_CS3_WAIT_M 0xC0000 // Maps the wait signal for chip + // select 3. +#define EMIF_ASYNC_WCCR_CS4_WAIT_S 20 +#define EMIF_ASYNC_WCCR_CS4_WAIT_M 0x300000 // Maps the wait signal for chip + // select 4. +#define EMIF_ASYNC_WCCR_CS5_WAIT_S 22 +#define EMIF_ASYNC_WCCR_CS5_WAIT_M 0xC00000 // Maps the wait signal for chip + // select 5. +#define EMIF_ASYNC_WCCR_WP0 0x10000000 // Wait Polarity for + // pad_wait_i[0]. +#define EMIF_ASYNC_WCCR_WP1 0x20000000 // Wait Polarity for + // pad_wait_i[1]. +#define EMIF_ASYNC_WCCR_WP2 0x40000000 // Wait Polarity for + // pad_wait_i[2]. +#define EMIF_ASYNC_WCCR_WP3 0x80000000 // Wait Polarity for + // pad_wait_i[3]. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDRAM_CR register +// +//***************************************************************************** +#define EMIF_SDRAM_CR_PAGESIGE_S 0 +#define EMIF_SDRAM_CR_PAGESIGE_M 0x7 // Page Size. +#define EMIF_SDRAM_CR_EBANK 0x8 // External chip select setup. +#define EMIF_SDRAM_CR_IBANK_S 4 +#define EMIF_SDRAM_CR_IBANK_M 0x70 // Internal Bank setup of SDRAM + // devices. +#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100 // Bits 11 to 9 are writable only + // if this bit is set. +#define EMIF_SDRAM_CR_CL_S 9 +#define EMIF_SDRAM_CR_CL_M 0xE00 // CAS Latency. +#define EMIF_SDRAM_CR_BIT_13_LOCK 0x1000 // Bits 13 is writable only if + // this bit is set. +#define EMIF_SDRAM_CR_NM 0x4000 // Narrow Mode. +#define EMIF_SDRAM_CR_BIT_25_17_LOCK 0x10000 // Bits 25 to 17 are writable only + // if this bit is set +#define EMIF_SDRAM_CR_IBANK_POS 0x80000 // Internal bank position. +#define EMIF_SDRAM_CR_ROWSIZE_S 20 +#define EMIF_SDRAM_CR_ROWSIZE_M 0x700000 // Row Size. +#define EMIF_SDRAM_CR_PASR_S 23 +#define EMIF_SDRAM_CR_PASR_M 0x3800000 // Partial Array Self Refresh. +#define EMIF_SDRAM_CR_PDWR 0x20000000 // Perform refreshes during Power + // Down. +#define EMIF_SDRAM_CR_PD 0x40000000 // Power Down. +#define EMIF_SDRAM_CR_SR 0x80000000 // Self Refresh. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDRAM_RCR register +// +//***************************************************************************** +#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0 +#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFF // Refresh Rate. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS2_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS2_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS2_CR_TA_S 2 +#define EMIF_ASYNC_CS2_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS2_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS3_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS3_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS3_CR_TA_S 2 +#define EMIF_ASYNC_CS3_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS3_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS4_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS4_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS4_CR_TA_S 2 +#define EMIF_ASYNC_CS4_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS4_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS5_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS5_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS5_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS5_CR_TA_S 2 +#define EMIF_ASYNC_CS5_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS5_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS5_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS5_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS5_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS5_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS5_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS5_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS5_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS5_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS5_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS5_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS5_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS5_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS5_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDRAM_TR register +// +//***************************************************************************** +#define EMIF_SDRAM_TR_T_RRD_S 4 +#define EMIF_SDRAM_TR_T_RRD_M 0x70 // Activate to Activate timing for + // different bank. +#define EMIF_SDRAM_TR_T_RC_S 8 +#define EMIF_SDRAM_TR_T_RC_M 0xF00 // Activate to Activate timing . +#define EMIF_SDRAM_TR_T_RAS_S 12 +#define EMIF_SDRAM_TR_T_RAS_M 0xF000 // Activate to Precharge timing. +#define EMIF_SDRAM_TR_T_WR_S 16 +#define EMIF_SDRAM_TR_T_WR_M 0x70000 // Last Write to Precharge timing. +#define EMIF_SDRAM_TR_T_RCD_S 20 +#define EMIF_SDRAM_TR_T_RCD_M 0x700000 // Activate to Read/Write timing. +#define EMIF_SDRAM_TR_T_RP_S 24 +#define EMIF_SDRAM_TR_T_RP_M 0x7000000 // Precharge to Activate/Refresh + // timing. +#define EMIF_SDRAM_TR_T_RFC_S 27 +#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000 // Refresh/Load Mode to + // Refresh/Activate timing + +//***************************************************************************** +// +// The following are defines for the bit fields in the TOTAL_SDRAM_AR register +// +//***************************************************************************** +#define EMIF_TOTAL_SDRAM_AR_TOTAL_SDRAM_AR_S 0 +#define EMIF_TOTAL_SDRAM_AR_TOTAL_SDRAM_AR_M 0xFFFFFFFF // Total number of VBUSP accesses + // to SDRAM. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TOTAL_SDRAM_ACTR register +// +//***************************************************************************** +#define EMIF_TOTAL_SDRAM_ACTR_TOTAL_SDRAM_ACTR_S 0 +#define EMIF_TOTAL_SDRAM_ACTR_TOTAL_SDRAM_ACTR_M 0xFFFFFFFF // Number of SDRAM accesses which + // required an activate command. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDR_EXT_TMNG register +// +//***************************************************************************** +#define EMIF_SDR_EXT_TMNG_T_XS_S 0 +#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1F // Self Refresh exit to new + // command timing. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_RAW register +// +//***************************************************************************** +#define EMIF_INT_RAW_AT 0x1 // Asynchronous Timeout. +#define EMIF_INT_RAW_LT 0x2 // Line Trap. +#define EMIF_INT_RAW_WR_S 2 +#define EMIF_INT_RAW_WR_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_MSK register +// +//***************************************************************************** +#define EMIF_INT_MSK_AT_MASKED 0x1 // Asynchronous Timeout. +#define EMIF_INT_MSK_LT_MASKED 0x2 // Line Trap. +#define EMIF_INT_MSK_WR_MASKED_S 2 +#define EMIF_INT_MSK_WR_MASKED_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_MSK_SET register +// +//***************************************************************************** +#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1 // Asynchronous Timeout. +#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2 // Line Trap. +#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2 +#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_MSK_CLR register +// +//***************************************************************************** +#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1 // Asynchronous Timeout. +#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2 // Line Trap. +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2 +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the IO_CTRL register +// +//***************************************************************************** +#define EMIF_IO_CTRL_IO_CTRL_S 0 +#define EMIF_IO_CTRL_IO_CTRL_M 0xFFFF // VTP calibration control for the + // IOs + +//***************************************************************************** +// +// The following are defines for the bit fields in the IO_STAT register +// +//***************************************************************************** +#define EMIF_IO_STAT_IO_STAT_S 0 +#define EMIF_IO_STAT_IO_STAT_M 0xFFFF // VTP calibration status of the + // IOs + +//***************************************************************************** +// +// The following are defines for the bit fields in the MODEL_REL_NUM register +// +//***************************************************************************** +#define EMIF_MODEL_REL_NUM_RELEASE_NUM_S 0 +#define EMIF_MODEL_REL_NUM_RELEASE_NUM_M 0xFF // Release Number. +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h new file mode 100644 index 0000000000..f72a5bc5f3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h @@ -0,0 +1,1248 @@ +//########################################################################### +// +// FILE: hw_epwm.h +// +// TITLE: Definitions for the C28x EPWM registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_EPWM_H__ +#define __HW_EPWM_H__ + +//***************************************************************************** +// +// The following are defines for the EPWM register offsets +// +//***************************************************************************** +#define EPWM_O_TBCTL 0x0 // Time Base Control Register +#define EPWM_O_TBCTL2 0x1 // Time Base Control Register 2 +#define EPWM_O_TBCTR 0x4 // Time Base Counter Register +#define EPWM_O_TBSTS 0x5 // Time Base Status Register +#define EPWM_O_CMPCTL 0x8 // Counter Compare Control + // Register +#define EPWM_O_CMPCTL2 0x9 // Counter Compare Control + // Register 2 +#define EPWM_O_DBCTL 0xC // Dead-Band Generator Control + // Register +#define EPWM_O_DBCTL2 0xD // Dead-Band Generator Control + // Register 2 +#define EPWM_O_AQCTL 0x10 // Action Qualifier Control + // Register +#define EPWM_O_AQTSRCSEL 0x11 // Action Qualifier Trigger Event + // Source Select Register +#define EPWM_O_PCCTL 0x14 // PWM Chopper Control Register +#define EPWM_O_HRCNFG 0x20 // HRPWM Configuration Register +#define EPWM_O_HRPWR 0x21 // HRPWM Power Register +#define EPWM_O_HRMSTEP 0x26 // HRPWM MEP Step Register +#define EPWM_O_HRPCTL 0x2D // High Resolution Period Control + // Register +#define EPWM_O_GLDCTL 0x34 // Global PWM Load Control + // Register +#define EPWM_O_GLDCFG 0x35 // Global PWM Load Config Register +#define EPWM_O_XLINK 0x38 // EPWMx Link Register +#define EPWM_O_AQCTLA 0x40 // Action Qualifier Control + // Register For Output A +#define EPWM_O_AQCTLA2 0x41 // Additional Action Qualifier + // Control Register For Output A +#define EPWM_O_AQCTLB 0x42 // Action Qualifier Control + // Register For Output B +#define EPWM_O_AQCTLB2 0x43 // Additional Action Qualifier + // Control Register For Output B +#define EPWM_O_AQSFRC 0x47 // Action Qualifier Software Force + // Register +#define EPWM_O_AQCSFRC 0x49 // Action Qualifier Continuous S/W + // Force Register +#define EPWM_O_DBREDHR 0x50 // Dead-Band Generator Rising Edge + // Delay High Resolution Mirror + // Register +#define EPWM_O_DBRED 0x51 // Dead-Band Generator Rising Edge + // Delay High Resolution Mirror + // Register +#define EPWM_O_DBFEDHR 0x52 // Dead-Band Generator Falling + // Edge Delay High Resolution + // Register +#define EPWM_O_DBFED 0x53 // Dead-Band Generator Falling + // Edge Delay Count Register +#define EPWM_O_TBPHS 0x60 // Time Base Phase High +#define EPWM_O_TBPRDHR 0x62 // Time Base Period High + // Resolution Register +#define EPWM_O_TBPRD 0x63 // Time Base Period Register +#define EPWM_O_CMPA 0x6A // Counter Compare A Register +#define EPWM_O_CMPB 0x6C // Compare B Register +#define EPWM_O_CMPC 0x6F // Counter Compare C Register +#define EPWM_O_CMPD 0x71 // Counter Compare D Register +#define EPWM_O_GLDCTL2 0x74 // Global PWM Load Control + // Register 2 +#define EPWM_O_TZSEL 0x80 // Trip Zone Select Register +#define EPWM_O_TZDCSEL 0x82 // Trip Zone Digital Comparator + // Select Register +#define EPWM_O_TZCTL 0x84 // Trip Zone Control Register +#define EPWM_O_TZCTL2 0x85 // Additional Trip Zone Control + // Register +#define EPWM_O_TZCTLDCA 0x86 // Trip Zone Control Register + // Digital Compare A +#define EPWM_O_TZCTLDCB 0x87 // Trip Zone Control Register + // Digital Compare B +#define EPWM_O_TZEINT 0x8D // Trip Zone Enable Interrupt + // Register +#define EPWM_O_TZFLG 0x93 // Trip Zone Flag Register +#define EPWM_O_TZCBCFLG 0x94 // Trip Zone CBC Flag Register +#define EPWM_O_TZOSTFLG 0x95 // Trip Zone OST Flag Register +#define EPWM_O_TZCLR 0x97 // Trip Zone Clear Register +#define EPWM_O_TZCBCCLR 0x98 // Trip Zone CBC Clear Register +#define EPWM_O_TZOSTCLR 0x99 // Trip Zone OST Clear Register +#define EPWM_O_TZFRC 0x9B // Trip Zone Force Register +#define EPWM_O_ETSEL 0xA4 // Event Trigger Selection + // Register +#define EPWM_O_ETPS 0xA6 // Event Trigger Pre-Scale + // Register +#define EPWM_O_ETFLG 0xA8 // Event Trigger Flag Register +#define EPWM_O_ETCLR 0xAA // Event Trigger Clear Register +#define EPWM_O_ETFRC 0xAC // Event Trigger Force Register +#define EPWM_O_ETINTPS 0xAE // Event-Trigger Interrupt + // Pre-Scale Register +#define EPWM_O_ETSOCPS 0xB0 // Event-Trigger SOC Pre-Scale + // Register +#define EPWM_O_ETCNTINITCTL 0xB2 // Event-Trigger Counter + // Initialization Control + // Register +#define EPWM_O_ETCNTINIT 0xB4 // Event-Trigger Counter + // Initialization Register +#define EPWM_O_DCTRIPSEL 0xC0 // Digital Compare Trip Select + // Register +#define EPWM_O_DCACTL 0xC3 // Digital Compare A Control + // Register +#define EPWM_O_DCBCTL 0xC4 // Digital Compare B Control + // Register +#define EPWM_O_DCFCTL 0xC7 // Digital Compare Filter Control + // Register +#define EPWM_O_DCCAPCTL 0xC8 // Digital Compare Capture Control + // Register +#define EPWM_O_DCFOFFSET 0xC9 // Digital Compare Filter Offset + // Register +#define EPWM_O_DCFOFFSETCNT 0xCA // Digital Compare Filter Offset + // Counter Register +#define EPWM_O_DCFWINDOW 0xCB // Digital Compare Filter Window + // Register +#define EPWM_O_DCFWINDOWCNT 0xCC // Digital Compare Filter Window + // Counter Register +#define EPWM_O_DCCAP 0xCF // Digital Compare Counter Capture + // Register +#define EPWM_O_DCAHTRIPSEL 0xD2 // Digital Compare AH Trip Select +#define EPWM_O_DCALTRIPSEL 0xD3 // Digital Compare AL Trip Select +#define EPWM_O_DCBHTRIPSEL 0xD4 // Digital Compare BH Trip Select +#define EPWM_O_DCBLTRIPSEL 0xD5 // Digital Compare BL Trip Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBCTL register +// +//***************************************************************************** +#define EPWM_TBCTL_CTRMODE_S 0 +#define EPWM_TBCTL_CTRMODE_M 0x3 // Counter Mode +#define EPWM_TBCTL_PHSEN 0x4 // Phase Load Enable +#define EPWM_TBCTL_PRDLD 0x8 // Active Period Load +#define EPWM_TBCTL_SYNCOSEL_S 4 +#define EPWM_TBCTL_SYNCOSEL_M 0x30 // Sync Output Select +#define EPWM_TBCTL_SWFSYNC 0x40 // Software Force Sync Pulse +#define EPWM_TBCTL_HSPCLKDIV_S 7 +#define EPWM_TBCTL_HSPCLKDIV_M 0x380 // High Speed TBCLK Pre-scaler +#define EPWM_TBCTL_CLKDIV_S 10 +#define EPWM_TBCTL_CLKDIV_M 0x1C00 // Time Base Clock Pre-scaler +#define EPWM_TBCTL_PHSDIR 0x2000 // Phase Direction Bit +#define EPWM_TBCTL_FREE_SOFT_S 14 +#define EPWM_TBCTL_FREE_SOFT_M 0xC000 // Emulation Mode Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBCTL2 register +// +//***************************************************************************** +#define EPWM_TBCTL2_SELFCLRTRREM 0x20 // Self clear Translator reminder +#define EPWM_TBCTL2_OSHTSYNCMODE 0x40 // One shot sync mode +#define EPWM_TBCTL2_OSHTSYNC 0x80 // One shot sync +#define EPWM_TBCTL2_SYNCOSELX_S 12 +#define EPWM_TBCTL2_SYNCOSELX_M 0x3000 // Syncout selection +#define EPWM_TBCTL2_PRDLDSYNC_S 14 +#define EPWM_TBCTL2_PRDLDSYNC_M 0xC000 // PRD Shadow to Active Load on + // SYNC Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBCTR register +// +//***************************************************************************** +#define EPWM_TBCTR_TBCTR_S 0 +#define EPWM_TBCTR_TBCTR_M 0xFFFF // Counter Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBSTS register +// +//***************************************************************************** +#define EPWM_TBSTS_CTRDIR 0x1 // Counter Direction Status +#define EPWM_TBSTS_SYNCI 0x2 // External Input Sync Status +#define EPWM_TBSTS_CTRMAX 0x4 // Counter Max Latched Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPCTL register +// +//***************************************************************************** +#define EPWM_CMPCTL_LOADAMODE_S 0 +#define EPWM_CMPCTL_LOADAMODE_M 0x3 // Active Compare A Load +#define EPWM_CMPCTL_LOADBMODE_S 2 +#define EPWM_CMPCTL_LOADBMODE_M 0xC // Active Compare B Load +#define EPWM_CMPCTL_SHDWAMODE 0x10 // Compare A Register Block + // Operating Mode +#define EPWM_CMPCTL_SHDWBMODE 0x40 // Compare B Register Block + // Operating Mode +#define EPWM_CMPCTL_SHDWAFULL 0x100 // Compare A Shadow Register Full + // Status +#define EPWM_CMPCTL_SHDWBFULL 0x200 // Compare B Shadow Register Full + // Status +#define EPWM_CMPCTL_LOADASYNC_S 10 +#define EPWM_CMPCTL_LOADASYNC_M 0xC00 // Active Compare A Load on SYNC +#define EPWM_CMPCTL_LOADBSYNC_S 12 +#define EPWM_CMPCTL_LOADBSYNC_M 0x3000 // Active Compare B Load on SYNC + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//***************************************************************************** +#define EPWM_CMPCTL2_LOADCMODE_S 0 +#define EPWM_CMPCTL2_LOADCMODE_M 0x3 // Active Compare C Load +#define EPWM_CMPCTL2_LOADDMODE_S 2 +#define EPWM_CMPCTL2_LOADDMODE_M 0xC // Active Compare D load +#define EPWM_CMPCTL2_SHDWCMODE 0x10 // Compare C Block Operating Mode +#define EPWM_CMPCTL2_SHDWDMODE 0x40 // Compare D Block Operating Mode +#define EPWM_CMPCTL2_LOADCSYNC_S 10 +#define EPWM_CMPCTL2_LOADCSYNC_M 0xC00 // Active Compare C Load on SYNC +#define EPWM_CMPCTL2_LOADDSYNC_S 12 +#define EPWM_CMPCTL2_LOADDSYNC_M 0x3000 // Active Compare D Load on SYNC + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBCTL register +// +//***************************************************************************** +#define EPWM_DBCTL_OUT_MODE_S 0 +#define EPWM_DBCTL_OUT_MODE_M 0x3 // Dead Band Output Mode Control +#define EPWM_DBCTL_POLSEL_S 2 +#define EPWM_DBCTL_POLSEL_M 0xC // Polarity Select Control +#define EPWM_DBCTL_IN_MODE_S 4 +#define EPWM_DBCTL_IN_MODE_M 0x30 // Dead Band Input Select Mode + // Control +#define EPWM_DBCTL_LOADREDMODE_S 6 +#define EPWM_DBCTL_LOADREDMODE_M 0xC0 // Active DBRED Load Mode +#define EPWM_DBCTL_LOADFEDMODE_S 8 +#define EPWM_DBCTL_LOADFEDMODE_M 0x300 // Active DBFED Load Mode +#define EPWM_DBCTL_SHDWDBREDMODE 0x400 // DBRED Block Operating Mode +#define EPWM_DBCTL_SHDWDBFEDMODE 0x800 // DBFED Block Operating Mode +#define EPWM_DBCTL_OUTSWAP_S 12 +#define EPWM_DBCTL_OUTSWAP_M 0x3000 // Dead Band Output Swap Control +#define EPWM_DBCTL_DEDB_MODE 0x4000 // Dead Band Dual-Edge B Mode + // Control +#define EPWM_DBCTL_HALFCYCLE 0x8000 // Half Cycle Clocking Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBCTL2 register +// +//***************************************************************************** +#define EPWM_DBCTL2_LOADDBCTLMODE_S 0 +#define EPWM_DBCTL2_LOADDBCTLMODE_M 0x3 // DBCTL Load from Shadow Mode + // Select +#define EPWM_DBCTL2_SHDWDBCTLMODE 0x4 // DBCTL Load mode Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTL register +// +//***************************************************************************** +#define EPWM_AQCTL_LDAQAMODE_S 0 +#define EPWM_AQCTL_LDAQAMODE_M 0x3 // Action Qualifier A Load Select +#define EPWM_AQCTL_LDAQBMODE_S 2 +#define EPWM_AQCTL_LDAQBMODE_M 0xC // Action Qualifier B Load Select +#define EPWM_AQCTL_SHDWAQAMODE 0x10 // Action Qualifer A Operating + // Mode +#define EPWM_AQCTL_SHDWAQBMODE 0x40 // Action Qualifier B Operating + // Mode +#define EPWM_AQCTL_LDAQASYNC_S 8 +#define EPWM_AQCTL_LDAQASYNC_M 0x300 // AQCTLA Register Load on SYNC +#define EPWM_AQCTL_LDAQBSYNC_S 10 +#define EPWM_AQCTL_LDAQBSYNC_M 0xC00 // AQCTLB Register Load on SYNC + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//***************************************************************************** +#define EPWM_AQTSRCSEL_T1SEL_S 0 +#define EPWM_AQTSRCSEL_T1SEL_M 0xF // T1 Event Source Select Bits +#define EPWM_AQTSRCSEL_T2SEL_S 4 +#define EPWM_AQTSRCSEL_T2SEL_M 0xF0 // T2 Event Source Select Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the PCCTL register +// +//***************************************************************************** +#define EPWM_PCCTL_CHPEN 0x1 // PWM chopping enable +#define EPWM_PCCTL_OSHTWTH_S 1 +#define EPWM_PCCTL_OSHTWTH_M 0x1E // One-shot pulse width +#define EPWM_PCCTL_CHPFREQ_S 5 +#define EPWM_PCCTL_CHPFREQ_M 0xE0 // Chopping clock frequency +#define EPWM_PCCTL_CHPDUTY_S 8 +#define EPWM_PCCTL_CHPDUTY_M 0x700 // Chopping clock Duty cycle + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRCNFG register +// +//***************************************************************************** +#define EPWM_HRCNFG_EDGMODE_S 0 +#define EPWM_HRCNFG_EDGMODE_M 0x3 // ePWMxA Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODE 0x4 // ePWMxA Control Mode Select Bits +#define EPWM_HRCNFG_HRLOAD_S 3 +#define EPWM_HRCNFG_HRLOAD_M 0x18 // ePWMxA Shadow Mode Select Bits +#define EPWM_HRCNFG_SELOUTB 0x20 // EPWMB Output Selection Bit +#define EPWM_HRCNFG_AUTOCONV 0x40 // Autoconversion Bit +#define EPWM_HRCNFG_SWAPAB 0x80 // Swap EPWMA and EPWMB Outputs + // Bit +#define EPWM_HRCNFG_EDGMODEB_S 8 +#define EPWM_HRCNFG_EDGMODEB_M 0x300 // ePWMxB Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODEB 0x400 // ePWMxB Control Mode Select Bits +#define EPWM_HRCNFG_HRLOADB_S 11 +#define EPWM_HRCNFG_HRLOADB_M 0x1800 // ePWMxB Shadow Mode Select Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRPWR register +// +//***************************************************************************** +#define EPWM_HRPWR_CALPWRON 0x8000 // Calibration Power On + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRMSTEP register +// +//***************************************************************************** +#define EPWM_HRMSTEP_HRMSTEP_S 0 +#define EPWM_HRMSTEP_HRMSTEP_M 0xFF // High Resolution Micro Step + // Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRPCTL register +// +//***************************************************************************** +#define EPWM_HRPCTL_HRPE 0x1 // High Resolution Period Enable +#define EPWM_HRPCTL_TBPHSHRLOADE 0x4 // TBPHSHR Load Enable +#define EPWM_HRPCTL_PWMSYNCSELX_S 4 +#define EPWM_HRPCTL_PWMSYNCSELX_M 0x70 // PWMSYNCX Source Select Bit: + +//***************************************************************************** +// +// The following are defines for the bit fields in the GLDCTL register +// +//***************************************************************************** +#define EPWM_GLDCTL_GLD 0x1 // Global Shadow to Active load + // event control +#define EPWM_GLDCTL_GLDMODE_S 1 +#define EPWM_GLDCTL_GLDMODE_M 0x1E // Shadow to Active Global Load + // Pulse Selection +#define EPWM_GLDCTL_OSHTMODE 0x20 // One Shot Load mode control bit +#define EPWM_GLDCTL_GLDPRD_S 7 +#define EPWM_GLDCTL_GLDPRD_M 0x380 // Global Reload Strobe Period + // Select Register +#define EPWM_GLDCTL_GLDCNT_S 10 +#define EPWM_GLDCTL_GLDCNT_M 0x1C00 // Global Reload Strobe Counter + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GLDCFG register +// +//***************************************************************************** +#define EPWM_GLDCFG_TBPRD_TBPRDHR 0x1 // Global load event configuration + // for TBPRD:TBPRDHR +#define EPWM_GLDCFG_CMPA_CMPAHR 0x2 // Global load event configuration + // for CMPA:CMPAHR +#define EPWM_GLDCFG_CMPB_CMPBHR 0x4 // Global load event configuration + // for CMPB:CMPBHR +#define EPWM_GLDCFG_CMPC 0x8 // Global load event configuration + // for CMPC +#define EPWM_GLDCFG_CMPD 0x10 // Global load event configuration + // for CMPD +#define EPWM_GLDCFG_DBRED_DBREDHR 0x20 // Global load event configuration + // for DBRED:DBREDHR +#define EPWM_GLDCFG_DBFED_DBFEDHR 0x40 // Global load event configuration + // for DBFED:DBFEDHR +#define EPWM_GLDCFG_DBCTL 0x80 // Global load event configuration + // for DBCTL +#define EPWM_GLDCFG_AQCTLA_AQCTLA2 0x100 // Global load event configuration + // for AQCTLA/A2 +#define EPWM_GLDCFG_AQCTLB_AQCTLB2 0x200 // Global load event configuration + // for AQCTLB/B2 +#define EPWM_GLDCFG_AQCSFRC 0x400 // Global load event configuration + // for AQCSFRC + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//***************************************************************************** +#define EPWM_XLINK_TBPRDLINK_S 0 +#define EPWM_XLINK_TBPRDLINK_M 0xF // TBPRD:TBPRDHR Link +#define EPWM_XLINK_CMPALINK_S 4 +#define EPWM_XLINK_CMPALINK_M 0xF0 // CMPA:CMPAHR Link +#define EPWM_XLINK_CMPBLINK_S 8 +#define EPWM_XLINK_CMPBLINK_M 0xF00 // CMPB:CMPBHR Link +#define EPWM_XLINK_CMPCLINK_S 12 +#define EPWM_XLINK_CMPCLINK_M 0xF000 // CMPC Link +#define EPWM_XLINK_CMPDLINK_S 16 +#define EPWM_XLINK_CMPDLINK_M 0xF0000 // CMPD Link +#define EPWM_XLINK_GLDCTL2LINK_S 28 +#define EPWM_XLINK_GLDCTL2LINK_M 0xF0000000 // GLDCTL2 Link + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLA register +// +//***************************************************************************** +#define EPWM_AQCTLA_ZRO_S 0 +#define EPWM_AQCTLA_ZRO_M 0x3 // Action Counter = Zero +#define EPWM_AQCTLA_PRD_S 2 +#define EPWM_AQCTLA_PRD_M 0xC // Action Counter = Period +#define EPWM_AQCTLA_CAU_S 4 +#define EPWM_AQCTLA_CAU_M 0x30 // Action Counter = Compare A Up +#define EPWM_AQCTLA_CAD_S 6 +#define EPWM_AQCTLA_CAD_M 0xC0 // Action Counter = Compare A Down +#define EPWM_AQCTLA_CBU_S 8 +#define EPWM_AQCTLA_CBU_M 0x300 // Action Counter = Compare B Up +#define EPWM_AQCTLA_CBD_S 10 +#define EPWM_AQCTLA_CBD_M 0xC00 // Action Counter = Compare B Down + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//***************************************************************************** +#define EPWM_AQCTLA2_T1U_S 0 +#define EPWM_AQCTLA2_T1U_M 0x3 // Action when event occurs on T1 + // in UP-Count +#define EPWM_AQCTLA2_T1D_S 2 +#define EPWM_AQCTLA2_T1D_M 0xC // Action when event occurs on T1 + // in DOWN-Count +#define EPWM_AQCTLA2_T2U_S 4 +#define EPWM_AQCTLA2_T2U_M 0x30 // Action when event occurs on T2 + // in UP-Count +#define EPWM_AQCTLA2_T2D_S 6 +#define EPWM_AQCTLA2_T2D_M 0xC0 // Action when event occurs on T2 + // in DOWN-Count + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLB register +// +//***************************************************************************** +#define EPWM_AQCTLB_ZRO_S 0 +#define EPWM_AQCTLB_ZRO_M 0x3 // Action Counter = Zero +#define EPWM_AQCTLB_PRD_S 2 +#define EPWM_AQCTLB_PRD_M 0xC // Action Counter = Period +#define EPWM_AQCTLB_CAU_S 4 +#define EPWM_AQCTLB_CAU_M 0x30 // Action Counter = Compare A Up +#define EPWM_AQCTLB_CAD_S 6 +#define EPWM_AQCTLB_CAD_M 0xC0 // Action Counter = Compare A Down +#define EPWM_AQCTLB_CBU_S 8 +#define EPWM_AQCTLB_CBU_M 0x300 // Action Counter = Compare B Up +#define EPWM_AQCTLB_CBD_S 10 +#define EPWM_AQCTLB_CBD_M 0xC00 // Action Counter = Compare B Down + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//***************************************************************************** +#define EPWM_AQCTLB2_T1U_S 0 +#define EPWM_AQCTLB2_T1U_M 0x3 // Action when event occurs on T1 + // in UP-Count +#define EPWM_AQCTLB2_T1D_S 2 +#define EPWM_AQCTLB2_T1D_M 0xC // Action when event occurs on T1 + // in DOWN-Count +#define EPWM_AQCTLB2_T2U_S 4 +#define EPWM_AQCTLB2_T2U_M 0x30 // Action when event occurs on T2 + // in UP-Count +#define EPWM_AQCTLB2_T2D_S 6 +#define EPWM_AQCTLB2_T2D_M 0xC0 // Action when event occurs on T2 + // in DOWN-Count + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQSFRC register +// +//***************************************************************************** +#define EPWM_AQSFRC_ACTSFA_S 0 +#define EPWM_AQSFRC_ACTSFA_M 0x3 // Action when One-time SW Force A + // Invoked +#define EPWM_AQSFRC_OTSFA 0x4 // One-time SW Force A Output +#define EPWM_AQSFRC_ACTSFB_S 3 +#define EPWM_AQSFRC_ACTSFB_M 0x18 // Action when One-time SW Force B + // Invoked +#define EPWM_AQSFRC_OTSFB 0x20 // One-time SW Force A Output +#define EPWM_AQSFRC_RLDCSF_S 6 +#define EPWM_AQSFRC_RLDCSF_M 0xC0 // Reload from Shadow Options + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCSFRC register +// +//***************************************************************************** +#define EPWM_AQCSFRC_CSFA_S 0 +#define EPWM_AQCSFRC_CSFA_M 0x3 // Continuous Software Force on + // output A +#define EPWM_AQCSFRC_CSFB_S 2 +#define EPWM_AQCSFRC_CSFB_M 0xC // Continuous Software Force on + // output B + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBREDHR register +// +//***************************************************************************** +#define EPWM_DBREDHR_DBREDHR_S 9 +#define EPWM_DBREDHR_DBREDHR_M 0xFE00 // DBREDHR High Resolution Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBRED register +// +//***************************************************************************** +#define EPWM_DBRED_DBRED_S 0 +#define EPWM_DBRED_DBRED_M 0xFFFF // Rising edge delay value + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBFEDHR register +// +//***************************************************************************** +#define EPWM_DBFEDHR_DBFEDHR_S 9 +#define EPWM_DBFEDHR_DBFEDHR_M 0xFE00 // DBFEDHR High Resolution Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBFED register +// +//***************************************************************************** +#define EPWM_DBFED_DBFED_S 0 +#define EPWM_DBFED_DBFED_M 0xFFFF // Falling edge delay value + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBPHS register +// +//***************************************************************************** +#define EPWM_TBPHS_TBPHSHR_S 0 +#define EPWM_TBPHS_TBPHSHR_M 0xFFFF // Extension Register for HRPWM + // Phase (8-bits) +#define EPWM_TBPHS_TBPHS_S 16 +#define EPWM_TBPHS_TBPHS_M 0xFFFF0000 // Phase Offset Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBPRDHR register +// +//***************************************************************************** +#define EPWM_TBPRDHR_TBPRDHR_S 0 +#define EPWM_TBPRDHR_TBPRDHR_M 0xFFFF // High res Time base period + // register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBPRD register +// +//***************************************************************************** +#define EPWM_TBPRD_TBPRD_S 0 +#define EPWM_TBPRD_TBPRD_M 0xFFFF // Time base period register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPA register +// +//***************************************************************************** +#define EPWM_CMPA_CMPAHR_S 0 +#define EPWM_CMPA_CMPAHR_M 0xFFFF // Compare A HRPWM Extension + // Register +#define EPWM_CMPA_CMPA_S 16 +#define EPWM_CMPA_CMPA_M 0xFFFF0000 // Compare A Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPB register +// +//***************************************************************************** +#define EPWM_CMPB_CMPB_S 16 +#define EPWM_CMPB_CMPB_M 0xFFFF0000 // Compare B Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPC register +// +//***************************************************************************** +#define EPWM_CMPC_CMPC_S 0 +#define EPWM_CMPC_CMPC_M 0xFFFF // Compare C Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPD register +// +//***************************************************************************** +#define EPWM_CMPD_CMPD_S 0 +#define EPWM_CMPD_CMPD_M 0xFFFF // Compare D Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//***************************************************************************** +#define EPWM_GLDCTL2_OSHTLD 0x1 // Enable reload event in one shot + // mode +#define EPWM_GLDCTL2_GFRCLD 0x2 // Force reload event in one shot + // mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZSEL register +// +//***************************************************************************** +#define EPWM_TZSEL_CBC1 0x1 // TZ1 CBC select +#define EPWM_TZSEL_CBC2 0x2 // TZ2 CBC select +#define EPWM_TZSEL_CBC3 0x4 // TZ3 CBC select +#define EPWM_TZSEL_CBC4 0x8 // TZ4 CBC select +#define EPWM_TZSEL_CBC5 0x10 // TZ5 CBC select +#define EPWM_TZSEL_CBC6 0x20 // TZ6 CBC select +#define EPWM_TZSEL_DCAEVT2 0x40 // DCAEVT2 CBC select +#define EPWM_TZSEL_DCBEVT2 0x80 // DCBEVT2 CBC select +#define EPWM_TZSEL_OSHT1 0x100 // One-shot TZ1 select +#define EPWM_TZSEL_OSHT2 0x200 // One-shot TZ2 select +#define EPWM_TZSEL_OSHT3 0x400 // One-shot TZ3 select +#define EPWM_TZSEL_OSHT4 0x800 // One-shot TZ4 select +#define EPWM_TZSEL_OSHT5 0x1000 // One-shot TZ5 select +#define EPWM_TZSEL_OSHT6 0x2000 // One-shot TZ6 select +#define EPWM_TZSEL_DCAEVT1 0x4000 // One-shot DCAEVT1 select +#define EPWM_TZSEL_DCBEVT1 0x8000 // One-shot DCBEVT1 select + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZDCSEL register +// +//***************************************************************************** +#define EPWM_TZDCSEL_DCAEVT1_S 0 +#define EPWM_TZDCSEL_DCAEVT1_M 0x7 // Digital Compare Output A Event + // 1 +#define EPWM_TZDCSEL_DCAEVT2_S 3 +#define EPWM_TZDCSEL_DCAEVT2_M 0x38 // Digital Compare Output A Event + // 2 +#define EPWM_TZDCSEL_DCBEVT1_S 6 +#define EPWM_TZDCSEL_DCBEVT1_M 0x1C0 // Digital Compare Output B Event + // 1 +#define EPWM_TZDCSEL_DCBEVT2_S 9 +#define EPWM_TZDCSEL_DCBEVT2_M 0xE00 // Digital Compare Output B Event + // 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTL register +// +//***************************************************************************** +#define EPWM_TZCTL_TZA_S 0 +#define EPWM_TZCTL_TZA_M 0x3 // TZ1 to TZ6 Trip Action On + // EPWMxA +#define EPWM_TZCTL_TZB_S 2 +#define EPWM_TZCTL_TZB_M 0xC // TZ1 to TZ6 Trip Action On + // EPWMxB +#define EPWM_TZCTL_DCAEVT1_S 4 +#define EPWM_TZCTL_DCAEVT1_M 0x30 // EPWMxA action on DCAEVT1 +#define EPWM_TZCTL_DCAEVT2_S 6 +#define EPWM_TZCTL_DCAEVT2_M 0xC0 // EPWMxA action on DCAEVT2 +#define EPWM_TZCTL_DCBEVT1_S 8 +#define EPWM_TZCTL_DCBEVT1_M 0x300 // EPWMxB action on DCBEVT1 +#define EPWM_TZCTL_DCBEVT2_S 10 +#define EPWM_TZCTL_DCBEVT2_M 0xC00 // EPWMxB action on DCBEVT2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTL2 register +// +//***************************************************************************** +#define EPWM_TZCTL2_TZAU_S 0 +#define EPWM_TZCTL2_TZAU_M 0x7 // Trip Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTL2_TZAD_S 3 +#define EPWM_TZCTL2_TZAD_M 0x38 // Trip Action On EPWMxA while + // Count direction is DOWN +#define EPWM_TZCTL2_TZBU_S 6 +#define EPWM_TZCTL2_TZBU_M 0x1C0 // Trip Action On EPWMxB while + // Count direction is UP +#define EPWM_TZCTL2_TZBD_S 9 +#define EPWM_TZCTL2_TZBD_M 0xE00 // Trip Action On EPWMxB while + // Count direction is DOWN +#define EPWM_TZCTL2_ETZE 0x8000 // TZCTL2 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//***************************************************************************** +#define EPWM_TZCTLDCA_DCAEVT1U_S 0 +#define EPWM_TZCTLDCA_DCAEVT1U_M 0x7 // DCAEVT1 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT1D_S 3 +#define EPWM_TZCTLDCA_DCAEVT1D_M 0x38 // DCAEVT1 Action On EPWMxA while + // Count direction is DOWN +#define EPWM_TZCTLDCA_DCAEVT2U_S 6 +#define EPWM_TZCTLDCA_DCAEVT2U_M 0x1C0 // DCAEVT2 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT2D_S 9 +#define EPWM_TZCTLDCA_DCAEVT2D_M 0xE00 // DCAEVT2 Action On EPWMxA while + // Count direction is DOWN + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//***************************************************************************** +#define EPWM_TZCTLDCB_DCBEVT1U_S 0 +#define EPWM_TZCTLDCB_DCBEVT1U_M 0x7 // DCBEVT1 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT1D_S 3 +#define EPWM_TZCTLDCB_DCBEVT1D_M 0x38 // DCBEVT1 Action On EPWMxA while + // Count direction is DOWN +#define EPWM_TZCTLDCB_DCBEVT2U_S 6 +#define EPWM_TZCTLDCB_DCBEVT2U_M 0x1C0 // DCBEVT2 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT2D_S 9 +#define EPWM_TZCTLDCB_DCBEVT2D_M 0xE00 // DCBEVT2 Action On EPWMxA while + // Count direction is DOWN + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZEINT register +// +//***************************************************************************** +#define EPWM_TZEINT_CBC 0x2 // Trip Zones Cycle By Cycle Int + // Enable +#define EPWM_TZEINT_OST 0x4 // Trip Zones One Shot Int Enable +#define EPWM_TZEINT_DCAEVT1 0x8 // Digital Compare A Event 1 Int + // Enable +#define EPWM_TZEINT_DCAEVT2 0x10 // Digital Compare A Event 2 Int + // Enable +#define EPWM_TZEINT_DCBEVT1 0x20 // Digital Compare B Event 1 Int + // Enable +#define EPWM_TZEINT_DCBEVT2 0x40 // Digital Compare B Event 2 Int + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZFLG register +// +//***************************************************************************** +#define EPWM_TZFLG_INT 0x1 // Global Int Status Flag +#define EPWM_TZFLG_CBC 0x2 // Trip Zones Cycle By Cycle Flag +#define EPWM_TZFLG_OST 0x4 // Trip Zones One Shot Flag +#define EPWM_TZFLG_DCAEVT1 0x8 // Digital Compare A Event 1 Flag +#define EPWM_TZFLG_DCAEVT2 0x10 // Digital Compare A Event 2 Flag +#define EPWM_TZFLG_DCBEVT1 0x20 // Digital Compare B Event 1 Flag +#define EPWM_TZFLG_DCBEVT2 0x40 // Digital Compare B Event 2 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//***************************************************************************** +#define EPWM_TZCBCFLG_CBC1 0x1 // Latched Status Flag for CBC1 + // Trip Latch +#define EPWM_TZCBCFLG_CBC2 0x2 // Latched Status Flag for CBC2 + // Trip Latch +#define EPWM_TZCBCFLG_CBC3 0x4 // Latched Status Flag for CBC3 + // Trip Latch +#define EPWM_TZCBCFLG_CBC4 0x8 // Latched Status Flag for CBC4 + // Trip Latch +#define EPWM_TZCBCFLG_CBC5 0x10 // Latched Status Flag for CBC5 + // Trip Latch +#define EPWM_TZCBCFLG_CBC6 0x20 // Latched Status Flag for CBC6 + // Trip Latch +#define EPWM_TZCBCFLG_DCAEVT2 0x40 // Latched Status Flag for Digital + // Compare Output A Event 2 +#define EPWM_TZCBCFLG_DCBEVT2 0x80 // Latched Status Flag for Digital + // Compare Output B Event 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//***************************************************************************** +#define EPWM_TZOSTFLG_OST1 0x1 // Latched Status Flag for OST1 + // Trip Latch +#define EPWM_TZOSTFLG_OST2 0x2 // Latched Status Flag for OST2 + // Trip Latch +#define EPWM_TZOSTFLG_OST3 0x4 // Latched Status Flag for OST3 + // Trip Latch +#define EPWM_TZOSTFLG_OST4 0x8 // Latched Status Flag for OST4 + // Trip Latch +#define EPWM_TZOSTFLG_OST5 0x10 // Latched Status Flag for OST5 + // Trip Latch +#define EPWM_TZOSTFLG_OST6 0x20 // Latched Status Flag for OST6 + // Trip Latch +#define EPWM_TZOSTFLG_DCAEVT2 0x40 // Latched Status Flag for Digital + // Compare Output A Event 1 +#define EPWM_TZOSTFLG_DCBEVT2 0x80 // Latched Status Flag for Digital + // Compare Output B Event 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCLR register +// +//***************************************************************************** +#define EPWM_TZCLR_INT 0x1 // Global Interrupt Clear Flag +#define EPWM_TZCLR_CBC 0x2 // Cycle-By-Cycle Flag Clear +#define EPWM_TZCLR_OST 0x4 // One-Shot Flag Clear +#define EPWM_TZCLR_DCAEVT1 0x8 // DCAVET1 Flag Clear +#define EPWM_TZCLR_DCAEVT2 0x10 // DCAEVT2 Flag Clear +#define EPWM_TZCLR_DCBEVT1 0x20 // DCBEVT1 Flag Clear +#define EPWM_TZCLR_DCBEVT2 0x40 // DCBEVT2 Flag Clear +#define EPWM_TZCLR_CBCPULSE_S 14 +#define EPWM_TZCLR_CBCPULSE_M 0xC000 // Clear Pulse for CBC Trip Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//***************************************************************************** +#define EPWM_TZCBCCLR_CBC1 0x1 // Clear Flag for Cycle-By-Cycle + // (CBC1) Trip Latch +#define EPWM_TZCBCCLR_CBC2 0x2 // Clear Flag for Cycle-By-Cycle + // (CBC2) Trip Latch +#define EPWM_TZCBCCLR_CBC3 0x4 // Clear Flag for Cycle-By-Cycle + // (CBC3) Trip Latch +#define EPWM_TZCBCCLR_CBC4 0x8 // Clear Flag for Cycle-By-Cycle + // (CBC4) Trip Latch +#define EPWM_TZCBCCLR_CBC5 0x10 // Clear Flag for Cycle-By-Cycle + // (CBC5) Trip Latch +#define EPWM_TZCBCCLR_CBC6 0x20 // Clear Flag for Cycle-By-Cycle + // (CBC6) Trip Latch +#define EPWM_TZCBCCLR_DCAEVT2 0x40 // Clear Flag forDCAEVT2 selected + // for CBC +#define EPWM_TZCBCCLR_DCBEVT2 0x80 // Clear Flag for DCBEVT2 selected + // for CBC + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//***************************************************************************** +#define EPWM_TZOSTCLR_OST1 0x1 // Clear Flag for Oneshot (OST1) + // Trip Latch +#define EPWM_TZOSTCLR_OST2 0x2 // Clear Flag for Oneshot (OST2) + // Trip Latch +#define EPWM_TZOSTCLR_OST3 0x4 // Clear Flag for Oneshot (OST3) + // Trip Latch +#define EPWM_TZOSTCLR_OST4 0x8 // Clear Flag for Oneshot (OST4) + // Trip Latch +#define EPWM_TZOSTCLR_OST5 0x10 // Clear Flag for Oneshot (OST5) + // Trip Latch +#define EPWM_TZOSTCLR_OST6 0x20 // Clear Flag for Oneshot (OST6) + // Trip Latch +#define EPWM_TZOSTCLR_DCAEVT2 0x40 // Clear Flag for DCAEVT1 selected + // for OST +#define EPWM_TZOSTCLR_DCBEVT2 0x80 // Clear Flag for DCBEVT1 selected + // for OST + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZFRC register +// +//***************************************************************************** +#define EPWM_TZFRC_CBC 0x2 // Force Trip Zones Cycle By Cycle + // Event +#define EPWM_TZFRC_OST 0x4 // Force Trip Zones One Shot Event +#define EPWM_TZFRC_DCAEVT1 0x8 // Force Digital Compare A Event 1 +#define EPWM_TZFRC_DCAEVT2 0x10 // Force Digital Compare A Event 2 +#define EPWM_TZFRC_DCBEVT1 0x20 // Force Digital Compare B Event 1 +#define EPWM_TZFRC_DCBEVT2 0x40 // Force Digital Compare B Event 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETSEL register +// +//***************************************************************************** +#define EPWM_ETSEL_INTSEL_S 0 +#define EPWM_ETSEL_INTSEL_M 0x7 // EPWMxINTn Select +#define EPWM_ETSEL_INTEN 0x8 // EPWMxINTn Enable +#define EPWM_ETSEL_SOCASELCMP 0x10 // EPWMxSOCA Compare Select +#define EPWM_ETSEL_SOCBSELCMP 0x20 // EPWMxSOCB Compare Select +#define EPWM_ETSEL_INTSELCMP 0x40 // EPWMxINT Compare Select +#define EPWM_ETSEL_SOCASEL_S 8 +#define EPWM_ETSEL_SOCASEL_M 0x700 // Start of Conversion A Select +#define EPWM_ETSEL_SOCAEN 0x800 // Start of Conversion A Enable +#define EPWM_ETSEL_SOCBSEL_S 12 +#define EPWM_ETSEL_SOCBSEL_M 0x7000 // Start of Conversion B Select +#define EPWM_ETSEL_SOCBEN 0x8000 // Start of Conversion B Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETPS register +// +//***************************************************************************** +#define EPWM_ETPS_INTPRD_S 0 +#define EPWM_ETPS_INTPRD_M 0x3 // EPWMxINTn Period Select +#define EPWM_ETPS_INTCNT_S 2 +#define EPWM_ETPS_INTCNT_M 0xC // EPWMxINTn Counter Register +#define EPWM_ETPS_INTPSSEL 0x10 // EPWMxINTn Pre-Scale Selection + // Bits +#define EPWM_ETPS_SOCPSSEL 0x20 // EPWMxSOC A/B Pre-Scale + // Selection Bits +#define EPWM_ETPS_SOCAPRD_S 8 +#define EPWM_ETPS_SOCAPRD_M 0x300 // EPWMxSOCA Period Select +#define EPWM_ETPS_SOCACNT_S 10 +#define EPWM_ETPS_SOCACNT_M 0xC00 // EPWMxSOCA Counter Register +#define EPWM_ETPS_SOCBPRD_S 12 +#define EPWM_ETPS_SOCBPRD_M 0x3000 // EPWMxSOCB Period Select +#define EPWM_ETPS_SOCBCNT_S 14 +#define EPWM_ETPS_SOCBCNT_M 0xC000 // EPWMxSOCB Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETFLG register +// +//***************************************************************************** +#define EPWM_ETFLG_INT 0x1 // EPWMxINTn Flag +#define EPWM_ETFLG_SOCA 0x4 // EPWMxSOCA Flag +#define EPWM_ETFLG_SOCB 0x8 // EPWMxSOCB Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETCLR register +// +//***************************************************************************** +#define EPWM_ETCLR_INT 0x1 // EPWMxINTn Clear +#define EPWM_ETCLR_SOCA 0x4 // EPWMxSOCA Clear +#define EPWM_ETCLR_SOCB 0x8 // EPWMxSOCB Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETFRC register +// +//***************************************************************************** +#define EPWM_ETFRC_INT 0x1 // EPWMxINTn Force +#define EPWM_ETFRC_SOCA 0x4 // EPWMxSOCA Force +#define EPWM_ETFRC_SOCB 0x8 // EPWMxSOCB Force + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETINTPS register +// +//***************************************************************************** +#define EPWM_ETINTPS_INTPRD2_S 0 +#define EPWM_ETINTPS_INTPRD2_M 0xF // EPWMxINTn Period Select +#define EPWM_ETINTPS_INTCNT2_S 4 +#define EPWM_ETINTPS_INTCNT2_M 0xF0 // EPWMxINTn Counter Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETSOCPS register +// +//***************************************************************************** +#define EPWM_ETSOCPS_SOCAPRD2_S 0 +#define EPWM_ETSOCPS_SOCAPRD2_M 0xF // EPWMxSOCA Period Select +#define EPWM_ETSOCPS_SOCACNT2_S 4 +#define EPWM_ETSOCPS_SOCACNT2_M 0xF0 // EPWMxSOCA Counter Register +#define EPWM_ETSOCPS_SOCBPRD2_S 8 +#define EPWM_ETSOCPS_SOCBPRD2_M 0xF00 // EPWMxSOCB Period Select +#define EPWM_ETSOCPS_SOCBCNT2_S 12 +#define EPWM_ETSOCPS_SOCBCNT2_M 0xF000 // EPWMxSOCB Counter Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//***************************************************************************** +#define EPWM_ETCNTINITCTL_INTINITFRC 0x400 // EPWMxINT Counter Initialization + // Force +#define EPWM_ETCNTINITCTL_SOCAINITFRC 0x800 // EPWMxSOCA Counter + // Initialization Force +#define EPWM_ETCNTINITCTL_SOCBINITFRC 0x1000 // EPWMxSOCB Counter + // Initialization Force +#define EPWM_ETCNTINITCTL_INTINITEN 0x2000 // EPWMxINT Counter Initialization + // Enable +#define EPWM_ETCNTINITCTL_SOCAINITEN 0x4000 // EPWMxSOCA Counter + // Initialization Enable +#define EPWM_ETCNTINITCTL_SOCBINITEN 0x8000 // EPWMxSOCB Counter + // Initialization Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//***************************************************************************** +#define EPWM_ETCNTINIT_INTINIT_S 0 +#define EPWM_ETCNTINIT_INTINIT_M 0xF // EPWMxINT Counter Initialization + // Bits +#define EPWM_ETCNTINIT_SOCAINIT_S 4 +#define EPWM_ETCNTINIT_SOCAINIT_M 0xF0 // EPWMxSOCA Counter + // Initialization Bits +#define EPWM_ETCNTINIT_SOCBINIT_S 8 +#define EPWM_ETCNTINIT_SOCBINIT_M 0xF00 // EPWMxSOCB Counter + // Initialization Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S 0 +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xF // Digital Compare A High COMP + // Input Select +#define EPWM_DCTRIPSEL_DCALCOMPSEL_S 4 +#define EPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0 // Digital Compare A Low COMP + // Input Select +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S 8 +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00 // Digital Compare B High COMP + // Input Select +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S 12 +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000 // Digital Compare B Low COMP + // Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCACTL register +// +//***************************************************************************** +#define EPWM_DCACTL_EVT1SRCSEL 0x1 // DCAEVT1 Source Signal +#define EPWM_DCACTL_EVT1FRCSYNCSEL 0x2 // DCAEVT1 Force Sync Signal +#define EPWM_DCACTL_EVT1SOCE 0x4 // DCAEVT1 SOC Enable +#define EPWM_DCACTL_EVT1SYNCE 0x8 // DCAEVT1 SYNC Enable +#define EPWM_DCACTL_EVT2SRCSEL 0x100 // DCAEVT2 Source Signal +#define EPWM_DCACTL_EVT2FRCSYNCSEL 0x200 // DCAEVT2 Force Sync Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCBCTL register +// +//***************************************************************************** +#define EPWM_DCBCTL_EVT1SRCSEL 0x1 // DCBEVT1 Source Signal +#define EPWM_DCBCTL_EVT1FRCSYNCSEL 0x2 // DCBEVT1 Force Sync Signal +#define EPWM_DCBCTL_EVT1SOCE 0x4 // DCBEVT1 SOC Enable +#define EPWM_DCBCTL_EVT1SYNCE 0x8 // DCBEVT1 SYNC Enable +#define EPWM_DCBCTL_EVT2SRCSEL 0x100 // DCBEVT2 Source Signal +#define EPWM_DCBCTL_EVT2FRCSYNCSEL 0x200 // DCBEVT2 Force Sync Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFCTL register +// +//***************************************************************************** +#define EPWM_DCFCTL_SRCSEL_S 0 +#define EPWM_DCFCTL_SRCSEL_M 0x3 // Filter Block Signal Source + // Select +#define EPWM_DCFCTL_BLANKE 0x4 // Blanking Enable/Disable +#define EPWM_DCFCTL_BLANKINV 0x8 // Blanking Window Inversion +#define EPWM_DCFCTL_PULSESEL_S 4 +#define EPWM_DCFCTL_PULSESEL_M 0x30 // Pulse Select for Blanking & + // Capture Alignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//***************************************************************************** +#define EPWM_DCCAPCTL_CAPE 0x1 // Counter Capture Enable +#define EPWM_DCCAPCTL_SHDWMODE 0x2 // Counter Capture Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFOFFSET register +// +//***************************************************************************** +#define EPWM_DCFOFFSET_DCFOFFSET_S 0 +#define EPWM_DCFOFFSET_DCFOFFSET_M 0xFFFF // Blanking Offset + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFOFFSETCNT register +// +//***************************************************************************** +#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_S 0 +#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_M 0xFFFF // Blanking Offset Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFWINDOW register +// +//***************************************************************************** +#define EPWM_DCFWINDOW_DCFWINDOW_S 0 +#define EPWM_DCFWINDOW_DCFWINDOW_M 0xFFFF // Digital Compare Filter Window + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFWINDOWCNT register +// +//***************************************************************************** +#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_S 0 +#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_M 0xFFFF // Digital Compare Filter Window + // Counter Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCCAP register +// +//***************************************************************************** +#define EPWM_DCCAP_DCCAP_S 0 +#define EPWM_DCCAP_DCCAP_M 0xFFFF // Time Base Counter Capture + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCAHTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCAH + // Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCALTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCAL + // Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCBHTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCBH + // Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCBLTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCBL + // Mux +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h new file mode 100644 index 0000000000..6d5f37b5eb --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h @@ -0,0 +1,391 @@ +//########################################################################### +// +// FILE: hw_eqep.h +// +// TITLE: Definitions for the C28x EQEP registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_EQEP_H__ +#define __HW_EQEP_H__ + +//***************************************************************************** +// +// The following are defines for the EQEP register offsets +// +//***************************************************************************** +#define EQEP_O_QPOSCNT 0x0 // Position Counter +#define EQEP_O_QPOSINIT 0x2 // Position Counter Init +#define EQEP_O_QPOSMAX 0x4 // Maximum Position Count +#define EQEP_O_QPOSCMP 0x6 // Position Compare +#define EQEP_O_QPOSILAT 0x8 // Index Position Latch +#define EQEP_O_QPOSSLAT 0xA // Strobe Position Latch +#define EQEP_O_QPOSLAT 0xC // Position Latch +#define EQEP_O_QUTMR 0xE // QEP Unit Timer +#define EQEP_O_QUPRD 0x10 // QEP Unit Period +#define EQEP_O_QWDTMR 0x12 // QEP Watchdog Timer +#define EQEP_O_QWDPRD 0x13 // QEP Watchdog Period +#define EQEP_O_QDECCTL 0x14 // Quadrature Decoder Control +#define EQEP_O_QEPCTL 0x15 // QEP Control +#define EQEP_O_QCAPCTL 0x16 // Qaudrature Capture Control +#define EQEP_O_QPOSCTL 0x17 // Position Compare Control +#define EQEP_O_QEINT 0x18 // QEP Interrupt Control +#define EQEP_O_QFLG 0x19 // QEP Interrupt Flag +#define EQEP_O_QCLR 0x1A // QEP Interrupt Clear +#define EQEP_O_QFRC 0x1B // QEP Interrupt Force +#define EQEP_O_QEPSTS 0x1C // QEP Status +#define EQEP_O_QCTMR 0x1D // QEP Capture Timer +#define EQEP_O_QCPRD 0x1E // QEP Capture Period +#define EQEP_O_QCTMRLAT 0x1F // QEP Capture Latch +#define EQEP_O_QCPRDLAT 0x20 // QEP Capture Period Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSCNT register +// +//***************************************************************************** +#define EQEP_QPOSCNT_QPOSCNT_S 0 +#define EQEP_QPOSCNT_QPOSCNT_M 0xFFFFFFFF // Position Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSINIT register +// +//***************************************************************************** +#define EQEP_QPOSINIT_QPOSINIT_S 0 +#define EQEP_QPOSINIT_QPOSINIT_M 0xFFFFFFFF // Position Counter Init + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSMAX register +// +//***************************************************************************** +#define EQEP_QPOSMAX_QPOSMAX_S 0 +#define EQEP_QPOSMAX_QPOSMAX_M 0xFFFFFFFF // Maximum Position Count + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSCMP register +// +//***************************************************************************** +#define EQEP_QPOSCMP_QPOSCMP_S 0 +#define EQEP_QPOSCMP_QPOSCMP_M 0xFFFFFFFF // Position Compare + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSILAT register +// +//***************************************************************************** +#define EQEP_QPOSILAT_QPOSILAT_S 0 +#define EQEP_QPOSILAT_QPOSILAT_M 0xFFFFFFFF // Index Position Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSSLAT register +// +//***************************************************************************** +#define EQEP_QPOSSLAT_QPOSSLAT_S 0 +#define EQEP_QPOSSLAT_QPOSSLAT_M 0xFFFFFFFF // Strobe Position Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSLAT register +// +//***************************************************************************** +#define EQEP_QPOSLAT_QPOSLAT_S 0 +#define EQEP_QPOSLAT_QPOSLAT_M 0xFFFFFFFF // Position Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QUTMR register +// +//***************************************************************************** +#define EQEP_QUTMR_QUTMR_S 0 +#define EQEP_QUTMR_QUTMR_M 0xFFFFFFFF // QEP Unit Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the QUPRD register +// +//***************************************************************************** +#define EQEP_QUPRD_QUPRD_S 0 +#define EQEP_QUPRD_QUPRD_M 0xFFFFFFFF // QEP Unit Period + +//***************************************************************************** +// +// The following are defines for the bit fields in the QWDTMR register +// +//***************************************************************************** +#define EQEP_QWDTMR_QWDTMR_S 0 +#define EQEP_QWDTMR_QWDTMR_M 0xFFFF // QEP Watchdog Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the QWDPRD register +// +//***************************************************************************** +#define EQEP_QWDPRD_QWDPRD_S 0 +#define EQEP_QWDPRD_QWDPRD_M 0xFFFF // QEP Watchdog Period + +//***************************************************************************** +// +// The following are defines for the bit fields in the QDECCTL register +// +//***************************************************************************** +#define EQEP_QDECCTL_QSP 0x20 // QEPS input polarity +#define EQEP_QDECCTL_QIP 0x40 // QEPI input polarity +#define EQEP_QDECCTL_QBP 0x80 // QEPB input polarity +#define EQEP_QDECCTL_QAP 0x100 // QEPA input polarity +#define EQEP_QDECCTL_IGATE 0x200 // Index pulse gating option +#define EQEP_QDECCTL_SWAP 0x400 // CLK/DIR Signal Source for + // Position Counter +#define EQEP_QDECCTL_XCR 0x800 // External Clock Rate +#define EQEP_QDECCTL_SPSEL 0x1000 // Sync output pin selection +#define EQEP_QDECCTL_SOEN 0x2000 // Sync output-enable +#define EQEP_QDECCTL_QSRC_S 14 +#define EQEP_QDECCTL_QSRC_M 0xC000 // Position-counter source + // selection + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEPCTL register +// +//***************************************************************************** +#define EQEP_QEPCTL_WDE 0x1 // QEP watchdog enable +#define EQEP_QEPCTL_UTE 0x2 // QEP unit timer enable +#define EQEP_QEPCTL_QCLM 0x4 // QEP capture latch mode +#define EQEP_QEPCTL_QPEN 0x8 // Quadrature postotion counter + // enable +#define EQEP_QEPCTL_IEL_S 4 +#define EQEP_QEPCTL_IEL_M 0x30 // Index event latch +#define EQEP_QEPCTL_SEL 0x40 // Strobe event latch +#define EQEP_QEPCTL_SWI 0x80 // Software init position counter +#define EQEP_QEPCTL_IEI_S 8 +#define EQEP_QEPCTL_IEI_M 0x300 // Index event init of position + // count +#define EQEP_QEPCTL_SEI_S 10 +#define EQEP_QEPCTL_SEI_M 0xC00 // Strobe event init +#define EQEP_QEPCTL_PCRM_S 12 +#define EQEP_QEPCTL_PCRM_M 0x3000 // Postion counter reset +#define EQEP_QEPCTL_FREE_SOFT_S 14 +#define EQEP_QEPCTL_FREE_SOFT_M 0xC000 // Emulation mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCAPCTL register +// +//***************************************************************************** +#define EQEP_QCAPCTL_UPPS_S 0 +#define EQEP_QCAPCTL_UPPS_M 0xF // Unit position event prescaler +#define EQEP_QCAPCTL_CCPS_S 4 +#define EQEP_QCAPCTL_CCPS_M 0x70 // eQEP capture timer clock + // prescaler +#define EQEP_QCAPCTL_CEN 0x8000 // Enable eQEP capture + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSCTL register +// +//***************************************************************************** +#define EQEP_QPOSCTL_PCSPW_S 0 +#define EQEP_QPOSCTL_PCSPW_M 0xFFF // Position compare sync pulse + // width +#define EQEP_QPOSCTL_PCE 0x1000 // Position compare enable/disable +#define EQEP_QPOSCTL_PCPOL 0x2000 // Polarity of sync output +#define EQEP_QPOSCTL_PCLOAD 0x4000 // Position compare of shadow load +#define EQEP_QPOSCTL_PCSHDW 0x8000 // Position compare of shadow + // enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEINT register +// +//***************************************************************************** +#define EQEP_QEINT_PCE 0x2 // Position counter error + // interrupt enable +#define EQEP_QEINT_QPE 0x4 // Quadrature phase error + // interrupt enable +#define EQEP_QEINT_QDC 0x8 // Quadrature direction change + // interrupt enable +#define EQEP_QEINT_WTO 0x10 // Watchdog time out interrupt + // enable +#define EQEP_QEINT_PCU 0x20 // Position counter underflow + // interrupt enable +#define EQEP_QEINT_PCO 0x40 // Position counter overflow + // interrupt enable +#define EQEP_QEINT_PCR 0x80 // Position-compare ready + // interrupt enable +#define EQEP_QEINT_PCM 0x100 // Position-compare match + // interrupt enable +#define EQEP_QEINT_SEL 0x200 // Strobe event latch interrupt + // enable +#define EQEP_QEINT_IEL 0x400 // Index event latch interrupt + // enable +#define EQEP_QEINT_UTO 0x800 // Unit time out interrupt enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QFLG register +// +//***************************************************************************** +#define EQEP_QFLG_INT 0x1 // Global interrupt status flag +#define EQEP_QFLG_PCE 0x2 // Position counter error + // interrupt flag +#define EQEP_QFLG_PHE 0x4 // Quadrature phase error + // interrupt flag +#define EQEP_QFLG_QDC 0x8 // Quadrature direction change + // interrupt flag +#define EQEP_QFLG_WTO 0x10 // Watchdog timeout interrupt flag +#define EQEP_QFLG_PCU 0x20 // Position counter underflow + // interrupt flag +#define EQEP_QFLG_PCO 0x40 // Position counter overflow + // interrupt flag +#define EQEP_QFLG_PCR 0x80 // Position-compare ready + // interrupt flag +#define EQEP_QFLG_PCM 0x100 // eQEP compare match event + // interrupt flag +#define EQEP_QFLG_SEL 0x200 // Strobe event latch interrupt + // flag +#define EQEP_QFLG_IEL 0x400 // Index event latch interrupt + // flag +#define EQEP_QFLG_UTO 0x800 // Unit time out interrupt flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCLR register +// +//***************************************************************************** +#define EQEP_QCLR_INT 0x1 // Global interrupt clear flag +#define EQEP_QCLR_PCE 0x2 // Clear position counter error + // interrupt flag +#define EQEP_QCLR_PHE 0x4 // Clear quadrature phase error + // interrupt flag +#define EQEP_QCLR_QDC 0x8 // Clear quadrature direction + // change interrupt flag +#define EQEP_QCLR_WTO 0x10 // Clear watchdog timeout + // interrupt flag +#define EQEP_QCLR_PCU 0x20 // Clear position counter + // underflow interrupt flag +#define EQEP_QCLR_PCO 0x40 // Clear position counter overflow + // interrupt flag +#define EQEP_QCLR_PCR 0x80 // Clear position-compare ready + // interrupt flag +#define EQEP_QCLR_PCM 0x100 // Clear eQEP compare match event + // interrupt flag +#define EQEP_QCLR_SEL 0x200 // Clear strobe event latch + // interrupt flag +#define EQEP_QCLR_IEL 0x400 // Clear index event latch + // interrupt flag +#define EQEP_QCLR_UTO 0x800 // Clear unit time out interrupt + // flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the QFRC register +// +//***************************************************************************** +#define EQEP_QFRC_PCE 0x2 // Force position counter error + // interrupt +#define EQEP_QFRC_PHE 0x4 // Force quadrature phase error + // interrupt +#define EQEP_QFRC_QDC 0x8 // Force quadrature direction + // change interrupt +#define EQEP_QFRC_WTO 0x10 // Force watchdog time out + // interrupt +#define EQEP_QFRC_PCU 0x20 // Force position counter + // underflow interrupt +#define EQEP_QFRC_PCO 0x40 // Force position counter overflow + // interrupt +#define EQEP_QFRC_PCR 0x80 // Force position-compare ready + // interrupt +#define EQEP_QFRC_PCM 0x100 // Force position-compare match + // interrupt +#define EQEP_QFRC_SEL 0x200 // Force strobe event latch + // interrupt +#define EQEP_QFRC_IEL 0x400 // Force index event latch + // interrupt +#define EQEP_QFRC_UTO 0x800 // Force unit time out interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEPSTS register +// +//***************************************************************************** +#define EQEP_QEPSTS_PCEF 0x1 // Position counter error flag. +#define EQEP_QEPSTS_FIMF 0x2 // First index marker flag +#define EQEP_QEPSTS_CDEF 0x4 // Capture direction error flag +#define EQEP_QEPSTS_COEF 0x8 // Capture overflow error flag +#define EQEP_QEPSTS_QDLF 0x10 // eQEP direction latch flag +#define EQEP_QEPSTS_QDF 0x20 // Quadrature direction flag +#define EQEP_QEPSTS_FIDF 0x40 // The first index marker +#define EQEP_QEPSTS_UPEVNT 0x80 // Unit position event flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCTMR register +// +//***************************************************************************** +#define EQEP_QCTMR_QCTMR_S 0 +#define EQEP_QCTMR_QCTMR_M 0xFFFF // This register provides time + // base for edge capture unit. + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCPRD register +// +//***************************************************************************** +#define EQEP_QCPRD_QCPRD_S 0 +#define EQEP_QCPRD_QCPRD_M 0xFFFF // Period count value between + // eQEP position events + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCTMRLAT register +// +//***************************************************************************** +#define EQEP_QCTMRLAT_QCTMRLAT_S 0 +#define EQEP_QCTMRLAT_QCTMRLAT_M 0xFFFF // The eQEP capture timer latch + // value + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCPRDLAT register +// +//***************************************************************************** +#define EQEP_QCPRDLAT_QCPRDLAT_S 0 +#define EQEP_QCPRDLAT_QCPRDLAT_M 0xFFFF // eQEP capture period latch value +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h new file mode 100644 index 0000000000..63c4f62a1e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h @@ -0,0 +1,5662 @@ +//########################################################################### +// +// FILE: hw_gpio.h +// +// TITLE: Definitions for the C28x GPIO registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets +// +//***************************************************************************** +#define GPIO_O_GPACTRL 0x0 // GPIO A Qualification Sampling + // Period Control (GPIO0 to 31) +#define GPIO_O_GPAQSEL1 0x2 // GPIO A Qualifier Select 1 + // Register (GPIO0 to 15) +#define GPIO_O_GPAQSEL2 0x4 // GPIO A Qualifier Select 2 + // Register (GPIO16 to 31) +#define GPIO_O_GPAMUX1 0x6 // GPIO A Mux 1 Register (GPIO0 to + // 15) +#define GPIO_O_GPAMUX2 0x8 // GPIO A Mux 2 Register (GPIO16 + // to 31) +#define GPIO_O_GPADIR 0xA // GPIO A Direction Register + // (GPIO0 to 31) +#define GPIO_O_GPAPUD 0xC // GPIO A Pull Up Disable Register + // (GPIO0 to 31) +#define GPIO_O_GPAINV 0x10 // GPIO A Input Polarity Invert + // Registers (GPIO0 to 31) +#define GPIO_O_GPAODR 0x12 // GPIO A Open Drain Output + // Register (GPIO0 to GPIO31) +#define GPIO_O_GPAGMUX1 0x20 // GPIO A Peripheral Group Mux + // (GPIO0 to 15) +#define GPIO_O_GPAGMUX2 0x22 // GPIO A Peripheral Group Mux + // (GPIO16 to 31) +#define GPIO_O_GPACSEL1 0x28 // GPIO A Core Select Register + // (GPIO0 to 7) +#define GPIO_O_GPACSEL2 0x2A // GPIO A Core Select Register + // (GPIO8 to 15) +#define GPIO_O_GPACSEL3 0x2C // GPIO A Core Select Register + // (GPIO16 to 23) +#define GPIO_O_GPACSEL4 0x2E // GPIO A Core Select Register + // (GPIO24 to 31) +#define GPIO_O_GPALOCK 0x3C // GPIO A Lock Configuration + // Register (GPIO0 to 31) +#define GPIO_O_GPACR 0x3E // GPIO A Lock Commit Register + // (GPIO0 to 31) +#define GPIO_O_GPBCTRL 0x40 // GPIO B Qualification Sampling + // Period Control (GPIO32 to 63) +#define GPIO_O_GPBQSEL1 0x42 // GPIO B Qualifier Select 1 + // Register (GPIO32 to 47) +#define GPIO_O_GPBQSEL2 0x44 // GPIO B Qualifier Select 2 + // Register (GPIO48 to 63) +#define GPIO_O_GPBMUX1 0x46 // GPIO B Mux 1 Register (GPIO32 + // to 47) +#define GPIO_O_GPBMUX2 0x48 // GPIO B Mux 2 Register (GPIO48 + // to 63) +#define GPIO_O_GPBDIR 0x4A // GPIO B Direction Register + // (GPIO32 to 63) +#define GPIO_O_GPBPUD 0x4C // GPIO B Pull Up Disable Register + // (GPIO32 to 63) +#define GPIO_O_GPBINV 0x50 // GPIO B Input Polarity Invert + // Registers (GPIO32 to 63) +#define GPIO_O_GPBODR 0x52 // GPIO B Open Drain Output + // Register (GPIO32 to GPIO63) +#define GPIO_O_GPBAMSEL 0x54 // GPIO B Analog Mode Select + // register (GPIO32 to GPIO63) +#define GPIO_O_GPBGMUX1 0x60 // GPIO B Peripheral Group Mux + // (GPIO32 to 47) +#define GPIO_O_GPBGMUX2 0x62 // GPIO B Peripheral Group Mux + // (GPIO48 to 63) +#define GPIO_O_GPBCSEL1 0x68 // GPIO B Core Select Register + // (GPIO32 to 39) +#define GPIO_O_GPBCSEL2 0x6A // GPIO B Core Select Register + // (GPIO40 to 47) +#define GPIO_O_GPBCSEL3 0x6C // GPIO B Core Select Register + // (GPIO48 to 55) +#define GPIO_O_GPBCSEL4 0x6E // GPIO B Core Select Register + // (GPIO56 to 63) +#define GPIO_O_GPBLOCK 0x7C // GPIO B Lock Configuration + // Register (GPIO32 to 63) +#define GPIO_O_GPBCR 0x7E // GPIO B Lock Commit Register + // (GPIO32 to 63) +#define GPIO_O_GPCCTRL 0x80 // GPIO C Qualification Sampling + // Period Control (GPIO64 to 95) +#define GPIO_O_GPCQSEL1 0x82 // GPIO C Qualifier Select 1 + // Register (GPIO64 to 79) +#define GPIO_O_GPCQSEL2 0x84 // GPIO C Qualifier Select 2 + // Register (GPIO80 to 95) +#define GPIO_O_GPCMUX1 0x86 // GPIO C Mux 1 Register (GPIO64 + // to 79) +#define GPIO_O_GPCMUX2 0x88 // GPIO C Mux 2 Register (GPIO80 + // to 95) +#define GPIO_O_GPCDIR 0x8A // GPIO C Direction Register + // (GPIO64 to 95) +#define GPIO_O_GPCPUD 0x8C // GPIO C Pull Up Disable Register + // (GPIO64 to 95) +#define GPIO_O_GPCINV 0x90 // GPIO C Input Polarity Invert + // Registers (GPIO64 to 95) +#define GPIO_O_GPCODR 0x92 // GPIO C Open Drain Output + // Register (GPIO64 to GPIO95) +#define GPIO_O_GPCGMUX1 0xA0 // GPIO C Peripheral Group Mux + // (GPIO64 to 79) +#define GPIO_O_GPCGMUX2 0xA2 // GPIO C Peripheral Group Mux + // (GPIO80 to 95) +#define GPIO_O_GPCCSEL1 0xA8 // GPIO C Core Select Register + // (GPIO64 to 71) +#define GPIO_O_GPCCSEL2 0xAA // GPIO C Core Select Register + // (GPIO72 to 79) +#define GPIO_O_GPCCSEL3 0xAC // GPIO C Core Select Register + // (GPIO80 to 87) +#define GPIO_O_GPCCSEL4 0xAE // GPIO C Core Select Register + // (GPIO88 to 95) +#define GPIO_O_GPCLOCK 0xBC // GPIO C Lock Configuration + // Register (GPIO64 to 95) +#define GPIO_O_GPCCR 0xBE // GPIO C Lock Commit Register + // (GPIO64 to 95) +#define GPIO_O_GPDCTRL 0xC0 // GPIO D Qualification Sampling + // Period Control (GPIO96 to 127) +#define GPIO_O_GPDQSEL1 0xC2 // GPIO D Qualifier Select 1 + // Register (GPIO96 to 111) +#define GPIO_O_GPDQSEL2 0xC4 // GPIO D Qualifier Select 2 + // Register (GPIO112 to 127) +#define GPIO_O_GPDMUX1 0xC6 // GPIO D Mux 1 Register (GPIO96 + // to 111) +#define GPIO_O_GPDMUX2 0xC8 // GPIO D Mux 2 Register (GPIO112 + // to 127) +#define GPIO_O_GPDDIR 0xCA // GPIO D Direction Register + // (GPIO96 to 127) +#define GPIO_O_GPDPUD 0xCC // GPIO D Pull Up Disable Register + // (GPIO96 to 127) +#define GPIO_O_GPDINV 0xD0 // GPIO D Input Polarity Invert + // Registers (GPIO96 to 127) +#define GPIO_O_GPDODR 0xD2 // GPIO D Open Drain Output + // Register (GPIO96 to GPIO127) +#define GPIO_O_GPDGMUX1 0xE0 // GPIO D Peripheral Group Mux + // (GPIO96 to 111) +#define GPIO_O_GPDGMUX2 0xE2 // GPIO D Peripheral Group Mux + // (GPIO112 to 127) +#define GPIO_O_GPDCSEL1 0xE8 // GPIO D Core Select Register + // (GPIO96 to 103) +#define GPIO_O_GPDCSEL2 0xEA // GPIO D Core Select Register + // (GPIO104 to 111) +#define GPIO_O_GPDCSEL3 0xEC // GPIO D Core Select Register + // (GPIO112 to 119) +#define GPIO_O_GPDCSEL4 0xEE // GPIO D Core Select Register + // (GPIO120 to 127) +#define GPIO_O_GPDLOCK 0xFC // GPIO D Lock Configuration + // Register (GPIO96 to 127) +#define GPIO_O_GPDCR 0xFE // GPIO D Lock Commit Register + // (GPIO96 to 127) +#define GPIO_O_GPECTRL 0x100 // GPIO E Qualification Sampling + // Period Control (GPIO128 to + // 159) +#define GPIO_O_GPEQSEL1 0x102 // GPIO E Qualifier Select 1 + // Register (GPIO128 to 143) +#define GPIO_O_GPEQSEL2 0x104 // GPIO E Qualifier Select 2 + // Register (GPIO144 to 159) +#define GPIO_O_GPEMUX1 0x106 // GPIO E Mux 1 Register (GPIO128 + // to 143) +#define GPIO_O_GPEMUX2 0x108 // GPIO E Mux 2 Register (GPIO144 + // to 159) +#define GPIO_O_GPEDIR 0x10A // GPIO E Direction Register + // (GPIO128 to 159) +#define GPIO_O_GPEPUD 0x10C // GPIO E Pull Up Disable Register + // (GPIO128 to 159) +#define GPIO_O_GPEINV 0x110 // GPIO E Input Polarity Invert + // Registers (GPIO128 to 159) +#define GPIO_O_GPEODR 0x112 // GPIO E Open Drain Output + // Register (GPIO128 to GPIO159) +#define GPIO_O_GPEGMUX1 0x120 // GPIO E Peripheral Group Mux + // (GPIO128 to 143) +#define GPIO_O_GPEGMUX2 0x122 // GPIO E Peripheral Group Mux + // (GPIO144 to 159) +#define GPIO_O_GPECSEL1 0x128 // GPIO E Core Select Register + // (GPIO128 to 135) +#define GPIO_O_GPECSEL2 0x12A // GPIO E Core Select Register + // (GPIO136 to 143) +#define GPIO_O_GPECSEL3 0x12C // GPIO E Core Select Register + // (GPIO144 to 151) +#define GPIO_O_GPECSEL4 0x12E // GPIO E Core Select Register + // (GPIO152 to 159) +#define GPIO_O_GPELOCK 0x13C // GPIO E Lock Configuration + // Register (GPIO128 to 159) +#define GPIO_O_GPECR 0x13E // GPIO E Lock Commit Register + // (GPIO128 to 159) +#define GPIO_O_GPFCTRL 0x140 // GPIO F Qualification Sampling + // Period Control (GPIO160 to + // 168) +#define GPIO_O_GPFQSEL1 0x142 // GPIO F Qualifier Select 1 + // Register (GPIO160 to 168) +#define GPIO_O_GPFMUX1 0x146 // GPIO F Mux 1 Register (GPIO160 + // to 168) +#define GPIO_O_GPFDIR 0x14A // GPIO F Direction Register + // (GPIO160 to 168) +#define GPIO_O_GPFPUD 0x14C // GPIO F Pull Up Disable Register + // (GPIO160 to 168) +#define GPIO_O_GPFINV 0x150 // GPIO F Input Polarity Invert + // Registers (GPIO160 to 168) +#define GPIO_O_GPFODR 0x152 // GPIO F Open Drain Output + // Register (GPIO160 to GPIO168) +#define GPIO_O_GPFGMUX1 0x160 // GPIO F Peripheral Group Mux + // (GPIO160 to 168) +#define GPIO_O_GPFCSEL1 0x168 // GPIO F Core Select Register + // (GPIO160 to 167) +#define GPIO_O_GPFCSEL2 0x16A // GPIO F Core Select Register + // (GPIO168) +#define GPIO_O_GPFLOCK 0x17C // GPIO F Lock Configuration + // Register (GPIO160 to 168) +#define GPIO_O_GPFCR 0x17E // GPIO F Lock Commit Register + // (GPIO160 to 168) +#define GPIO_O_GPADAT 0x0 // GPIO A Data Register (GPIO0 to + // 31) +#define GPIO_O_GPASET 0x2 // GPIO A Data Set Register (GPIO0 + // to 31) +#define GPIO_O_GPACLEAR 0x4 // GPIO A Data Clear Register + // (GPIO0 to 31) +#define GPIO_O_GPATOGGLE 0x6 // GPIO A Data Toggle Register + // (GPIO0 to 31) +#define GPIO_O_GPBDAT 0x8 // GPIO B Data Register (GPIO32 to + // 63) +#define GPIO_O_GPBSET 0xA // GPIO B Data Set Register + // (GPIO32 to 63) +#define GPIO_O_GPBCLEAR 0xC // GPIO B Data Clear Register + // (GPIO32 to 63) +#define GPIO_O_GPBTOGGLE 0xE // GPIO B Data Toggle Register + // (GPIO32 to 63) +#define GPIO_O_GPCDAT 0x10 // GPIO C Data Register (GPIO64 to + // 95) +#define GPIO_O_GPCSET 0x12 // GPIO C Data Set Register + // (GPIO64 to 95) +#define GPIO_O_GPCCLEAR 0x14 // GPIO C Data Clear Register + // (GPIO64 to 95) +#define GPIO_O_GPCTOGGLE 0x16 // GPIO C Data Toggle Register + // (GPIO64 to 95) +#define GPIO_O_GPDDAT 0x18 // GPIO D Data Register (GPIO96 to + // 127) +#define GPIO_O_GPDSET 0x1A // GPIO D Data Set Register + // (GPIO96 to 127) +#define GPIO_O_GPDCLEAR 0x1C // GPIO D Data Clear Register + // (GPIO96 to 127) +#define GPIO_O_GPDTOGGLE 0x1E // GPIO D Data Toggle Register + // (GPIO96 to 127) +#define GPIO_O_GPEDAT 0x20 // GPIO E Data Register (GPIO128 + // to 159) +#define GPIO_O_GPESET 0x22 // GPIO E Data Set Register + // (GPIO128 to 159) +#define GPIO_O_GPECLEAR 0x24 // GPIO E Data Clear Register + // (GPIO128 to 159) +#define GPIO_O_GPETOGGLE 0x26 // GPIO E Data Toggle Register + // (GPIO128 to 159) +#define GPIO_O_GPFDAT 0x28 // GPIO F Data Register (GPIO160 + // to 168) +#define GPIO_O_GPFSET 0x2A // GPIO F Data Set Register + // (GPIO160 to 168) +#define GPIO_O_GPFCLEAR 0x2C // GPIO F Data Clear Register + // (GPIO160 to 168) +#define GPIO_O_GPFTOGGLE 0x2E // GPIO F Data Toggle Register + // (GPIO160 to 168) + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACTRL register +// +//***************************************************************************** +#define GPIO_GPACTRL_QUALPRD0_S 0 +#define GPIO_GPACTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO0 to GPIO7 +#define GPIO_GPACTRL_QUALPRD1_S 8 +#define GPIO_GPACTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO8 to GPIO15 +#define GPIO_GPACTRL_QUALPRD2_S 16 +#define GPIO_GPACTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO16 to GPIO23 +#define GPIO_GPACTRL_QUALPRD3_S 24 +#define GPIO_GPACTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO24 to GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAQSEL1 register +// +//***************************************************************************** +#define GPIO_GPAQSEL1_GPIO0_S 0 +#define GPIO_GPAQSEL1_GPIO0_M 0x3 // Select input qualification type + // for GPIO0 +#define GPIO_GPAQSEL1_GPIO1_S 2 +#define GPIO_GPAQSEL1_GPIO1_M 0xC // Select input qualification type + // for GPIO1 +#define GPIO_GPAQSEL1_GPIO2_S 4 +#define GPIO_GPAQSEL1_GPIO2_M 0x30 // Select input qualification type + // for GPIO2 +#define GPIO_GPAQSEL1_GPIO3_S 6 +#define GPIO_GPAQSEL1_GPIO3_M 0xC0 // Select input qualification type + // for GPIO3 +#define GPIO_GPAQSEL1_GPIO4_S 8 +#define GPIO_GPAQSEL1_GPIO4_M 0x300 // Select input qualification type + // for GPIO4 +#define GPIO_GPAQSEL1_GPIO5_S 10 +#define GPIO_GPAQSEL1_GPIO5_M 0xC00 // Select input qualification type + // for GPIO5 +#define GPIO_GPAQSEL1_GPIO6_S 12 +#define GPIO_GPAQSEL1_GPIO6_M 0x3000 // Select input qualification type + // for GPIO6 +#define GPIO_GPAQSEL1_GPIO7_S 14 +#define GPIO_GPAQSEL1_GPIO7_M 0xC000 // Select input qualification type + // for GPIO7 +#define GPIO_GPAQSEL1_GPIO8_S 16 +#define GPIO_GPAQSEL1_GPIO8_M 0x30000 // Select input qualification type + // for GPIO8 +#define GPIO_GPAQSEL1_GPIO9_S 18 +#define GPIO_GPAQSEL1_GPIO9_M 0xC0000 // Select input qualification type + // for GPIO9 +#define GPIO_GPAQSEL1_GPIO10_S 20 +#define GPIO_GPAQSEL1_GPIO10_M 0x300000 // Select input qualification type + // for GPIO10 +#define GPIO_GPAQSEL1_GPIO11_S 22 +#define GPIO_GPAQSEL1_GPIO11_M 0xC00000 // Select input qualification type + // for GPIO11 +#define GPIO_GPAQSEL1_GPIO12_S 24 +#define GPIO_GPAQSEL1_GPIO12_M 0x3000000 // Select input qualification type + // for GPIO12 +#define GPIO_GPAQSEL1_GPIO13_S 26 +#define GPIO_GPAQSEL1_GPIO13_M 0xC000000 // Select input qualification type + // for GPIO13 +#define GPIO_GPAQSEL1_GPIO14_S 28 +#define GPIO_GPAQSEL1_GPIO14_M 0x30000000 // Select input qualification type + // for GPIO14 +#define GPIO_GPAQSEL1_GPIO15_S 30 +#define GPIO_GPAQSEL1_GPIO15_M 0xC0000000 // Select input qualification type + // for GPIO15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAQSEL2 register +// +//***************************************************************************** +#define GPIO_GPAQSEL2_GPIO16_S 0 +#define GPIO_GPAQSEL2_GPIO16_M 0x3 // Select input qualification type + // for GPIO16 +#define GPIO_GPAQSEL2_GPIO17_S 2 +#define GPIO_GPAQSEL2_GPIO17_M 0xC // Select input qualification type + // for GPIO17 +#define GPIO_GPAQSEL2_GPIO18_S 4 +#define GPIO_GPAQSEL2_GPIO18_M 0x30 // Select input qualification type + // for GPIO18 +#define GPIO_GPAQSEL2_GPIO19_S 6 +#define GPIO_GPAQSEL2_GPIO19_M 0xC0 // Select input qualification type + // for GPIO19 +#define GPIO_GPAQSEL2_GPIO20_S 8 +#define GPIO_GPAQSEL2_GPIO20_M 0x300 // Select input qualification type + // for GPIO20 +#define GPIO_GPAQSEL2_GPIO21_S 10 +#define GPIO_GPAQSEL2_GPIO21_M 0xC00 // Select input qualification type + // for GPIO21 +#define GPIO_GPAQSEL2_GPIO22_S 12 +#define GPIO_GPAQSEL2_GPIO22_M 0x3000 // Select input qualification type + // for GPIO22 +#define GPIO_GPAQSEL2_GPIO23_S 14 +#define GPIO_GPAQSEL2_GPIO23_M 0xC000 // Select input qualification type + // for GPIO23 +#define GPIO_GPAQSEL2_GPIO24_S 16 +#define GPIO_GPAQSEL2_GPIO24_M 0x30000 // Select input qualification type + // for GPIO24 +#define GPIO_GPAQSEL2_GPIO25_S 18 +#define GPIO_GPAQSEL2_GPIO25_M 0xC0000 // Select input qualification type + // for GPIO25 +#define GPIO_GPAQSEL2_GPIO26_S 20 +#define GPIO_GPAQSEL2_GPIO26_M 0x300000 // Select input qualification type + // for GPIO26 +#define GPIO_GPAQSEL2_GPIO27_S 22 +#define GPIO_GPAQSEL2_GPIO27_M 0xC00000 // Select input qualification type + // for GPIO27 +#define GPIO_GPAQSEL2_GPIO28_S 24 +#define GPIO_GPAQSEL2_GPIO28_M 0x3000000 // Select input qualification type + // for GPIO28 +#define GPIO_GPAQSEL2_GPIO29_S 26 +#define GPIO_GPAQSEL2_GPIO29_M 0xC000000 // Select input qualification type + // for GPIO29 +#define GPIO_GPAQSEL2_GPIO30_S 28 +#define GPIO_GPAQSEL2_GPIO30_M 0x30000000 // Select input qualification type + // for GPIO30 +#define GPIO_GPAQSEL2_GPIO31_S 30 +#define GPIO_GPAQSEL2_GPIO31_M 0xC0000000 // Select input qualification type + // for GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAMUX1 register +// +//***************************************************************************** +#define GPIO_GPAMUX1_GPIO0_S 0 +#define GPIO_GPAMUX1_GPIO0_M 0x3 // Defines pin-muxing selection + // for GPIO0 +#define GPIO_GPAMUX1_GPIO1_S 2 +#define GPIO_GPAMUX1_GPIO1_M 0xC // Defines pin-muxing selection + // for GPIO1 +#define GPIO_GPAMUX1_GPIO2_S 4 +#define GPIO_GPAMUX1_GPIO2_M 0x30 // Defines pin-muxing selection + // for GPIO2 +#define GPIO_GPAMUX1_GPIO3_S 6 +#define GPIO_GPAMUX1_GPIO3_M 0xC0 // Defines pin-muxing selection + // for GPIO3 +#define GPIO_GPAMUX1_GPIO4_S 8 +#define GPIO_GPAMUX1_GPIO4_M 0x300 // Defines pin-muxing selection + // for GPIO4 +#define GPIO_GPAMUX1_GPIO5_S 10 +#define GPIO_GPAMUX1_GPIO5_M 0xC00 // Defines pin-muxing selection + // for GPIO5 +#define GPIO_GPAMUX1_GPIO6_S 12 +#define GPIO_GPAMUX1_GPIO6_M 0x3000 // Defines pin-muxing selection + // for GPIO6 +#define GPIO_GPAMUX1_GPIO7_S 14 +#define GPIO_GPAMUX1_GPIO7_M 0xC000 // Defines pin-muxing selection + // for GPIO7 +#define GPIO_GPAMUX1_GPIO8_S 16 +#define GPIO_GPAMUX1_GPIO8_M 0x30000 // Defines pin-muxing selection + // for GPIO8 +#define GPIO_GPAMUX1_GPIO9_S 18 +#define GPIO_GPAMUX1_GPIO9_M 0xC0000 // Defines pin-muxing selection + // for GPIO9 +#define GPIO_GPAMUX1_GPIO10_S 20 +#define GPIO_GPAMUX1_GPIO10_M 0x300000 // Defines pin-muxing selection + // for GPIO10 +#define GPIO_GPAMUX1_GPIO11_S 22 +#define GPIO_GPAMUX1_GPIO11_M 0xC00000 // Defines pin-muxing selection + // for GPIO11 +#define GPIO_GPAMUX1_GPIO12_S 24 +#define GPIO_GPAMUX1_GPIO12_M 0x3000000 // Defines pin-muxing selection + // for GPIO12 +#define GPIO_GPAMUX1_GPIO13_S 26 +#define GPIO_GPAMUX1_GPIO13_M 0xC000000 // Defines pin-muxing selection + // for GPIO13 +#define GPIO_GPAMUX1_GPIO14_S 28 +#define GPIO_GPAMUX1_GPIO14_M 0x30000000 // Defines pin-muxing selection + // for GPIO14 +#define GPIO_GPAMUX1_GPIO15_S 30 +#define GPIO_GPAMUX1_GPIO15_M 0xC0000000 // Defines pin-muxing selection + // for GPIO15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAMUX2 register +// +//***************************************************************************** +#define GPIO_GPAMUX2_GPIO16_S 0 +#define GPIO_GPAMUX2_GPIO16_M 0x3 // Defines pin-muxing selection + // for GPIO16 +#define GPIO_GPAMUX2_GPIO17_S 2 +#define GPIO_GPAMUX2_GPIO17_M 0xC // Defines pin-muxing selection + // for GPIO17 +#define GPIO_GPAMUX2_GPIO18_S 4 +#define GPIO_GPAMUX2_GPIO18_M 0x30 // Defines pin-muxing selection + // for GPIO18 +#define GPIO_GPAMUX2_GPIO19_S 6 +#define GPIO_GPAMUX2_GPIO19_M 0xC0 // Defines pin-muxing selection + // for GPIO19 +#define GPIO_GPAMUX2_GPIO20_S 8 +#define GPIO_GPAMUX2_GPIO20_M 0x300 // Defines pin-muxing selection + // for GPIO20 +#define GPIO_GPAMUX2_GPIO21_S 10 +#define GPIO_GPAMUX2_GPIO21_M 0xC00 // Defines pin-muxing selection + // for GPIO21 +#define GPIO_GPAMUX2_GPIO22_S 12 +#define GPIO_GPAMUX2_GPIO22_M 0x3000 // Defines pin-muxing selection + // for GPIO22 +#define GPIO_GPAMUX2_GPIO23_S 14 +#define GPIO_GPAMUX2_GPIO23_M 0xC000 // Defines pin-muxing selection + // for GPIO23 +#define GPIO_GPAMUX2_GPIO24_S 16 +#define GPIO_GPAMUX2_GPIO24_M 0x30000 // Defines pin-muxing selection + // for GPIO24 +#define GPIO_GPAMUX2_GPIO25_S 18 +#define GPIO_GPAMUX2_GPIO25_M 0xC0000 // Defines pin-muxing selection + // for GPIO25 +#define GPIO_GPAMUX2_GPIO26_S 20 +#define GPIO_GPAMUX2_GPIO26_M 0x300000 // Defines pin-muxing selection + // for GPIO26 +#define GPIO_GPAMUX2_GPIO27_S 22 +#define GPIO_GPAMUX2_GPIO27_M 0xC00000 // Defines pin-muxing selection + // for GPIO27 +#define GPIO_GPAMUX2_GPIO28_S 24 +#define GPIO_GPAMUX2_GPIO28_M 0x3000000 // Defines pin-muxing selection + // for GPIO28 +#define GPIO_GPAMUX2_GPIO29_S 26 +#define GPIO_GPAMUX2_GPIO29_M 0xC000000 // Defines pin-muxing selection + // for GPIO29 +#define GPIO_GPAMUX2_GPIO30_S 28 +#define GPIO_GPAMUX2_GPIO30_M 0x30000000 // Defines pin-muxing selection + // for GPIO30 +#define GPIO_GPAMUX2_GPIO31_S 30 +#define GPIO_GPAMUX2_GPIO31_M 0xC0000000 // Defines pin-muxing selection + // for GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPADIR register +// +//***************************************************************************** +#define GPIO_GPADIR_GPIO0 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO1 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO2 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO3 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO4 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO5 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO6 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO7 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO8 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO9 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO10 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO11 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO12 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO13 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO14 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO15 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO16 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO17 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO18 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO19 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO20 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO21 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO22 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO23 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO24 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO25 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO26 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO27 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO28 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO29 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO30 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO31 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAPUD register +// +//***************************************************************************** +#define GPIO_GPAPUD_GPIO0 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO1 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO2 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO3 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO4 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO5 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO6 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO7 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO8 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO9 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO10 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO11 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO12 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO13 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO14 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO15 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO16 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO17 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO18 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO19 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO20 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO21 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO22 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO23 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO24 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO25 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO26 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO27 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO28 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO29 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO30 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO31 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAINV register +// +//***************************************************************************** +#define GPIO_GPAINV_GPIO0 0x1 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO1 0x2 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO2 0x4 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO3 0x8 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO4 0x10 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO5 0x20 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO6 0x40 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO7 0x80 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO8 0x100 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO9 0x200 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO10 0x400 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO11 0x800 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO12 0x1000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO13 0x2000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO14 0x4000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO15 0x8000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO16 0x10000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO17 0x20000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO18 0x40000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO19 0x80000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO20 0x100000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO21 0x200000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO22 0x400000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO23 0x800000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO24 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO25 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO26 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO27 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO28 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO29 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO30 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO31 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAODR register +// +//***************************************************************************** +#define GPIO_GPAODR_GPIO0 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO1 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO2 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO3 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO4 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO5 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO6 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO7 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO8 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO9 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO10 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO11 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO12 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO13 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO14 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO15 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO16 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO17 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO18 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO19 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO20 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO21 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO22 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO23 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO24 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO25 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO26 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO27 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO28 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO29 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO30 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO31 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAGMUX1 register +// +//***************************************************************************** +#define GPIO_GPAGMUX1_GPIO0_S 0 +#define GPIO_GPAGMUX1_GPIO0_M 0x3 // Defines pin-muxing selection + // for GPIO0 +#define GPIO_GPAGMUX1_GPIO1_S 2 +#define GPIO_GPAGMUX1_GPIO1_M 0xC // Defines pin-muxing selection + // for GPIO1 +#define GPIO_GPAGMUX1_GPIO2_S 4 +#define GPIO_GPAGMUX1_GPIO2_M 0x30 // Defines pin-muxing selection + // for GPIO2 +#define GPIO_GPAGMUX1_GPIO3_S 6 +#define GPIO_GPAGMUX1_GPIO3_M 0xC0 // Defines pin-muxing selection + // for GPIO3 +#define GPIO_GPAGMUX1_GPIO4_S 8 +#define GPIO_GPAGMUX1_GPIO4_M 0x300 // Defines pin-muxing selection + // for GPIO4 +#define GPIO_GPAGMUX1_GPIO5_S 10 +#define GPIO_GPAGMUX1_GPIO5_M 0xC00 // Defines pin-muxing selection + // for GPIO5 +#define GPIO_GPAGMUX1_GPIO6_S 12 +#define GPIO_GPAGMUX1_GPIO6_M 0x3000 // Defines pin-muxing selection + // for GPIO6 +#define GPIO_GPAGMUX1_GPIO7_S 14 +#define GPIO_GPAGMUX1_GPIO7_M 0xC000 // Defines pin-muxing selection + // for GPIO7 +#define GPIO_GPAGMUX1_GPIO8_S 16 +#define GPIO_GPAGMUX1_GPIO8_M 0x30000 // Defines pin-muxing selection + // for GPIO8 +#define GPIO_GPAGMUX1_GPIO9_S 18 +#define GPIO_GPAGMUX1_GPIO9_M 0xC0000 // Defines pin-muxing selection + // for GPIO9 +#define GPIO_GPAGMUX1_GPIO10_S 20 +#define GPIO_GPAGMUX1_GPIO10_M 0x300000 // Defines pin-muxing selection + // for GPIO10 +#define GPIO_GPAGMUX1_GPIO11_S 22 +#define GPIO_GPAGMUX1_GPIO11_M 0xC00000 // Defines pin-muxing selection + // for GPIO11 +#define GPIO_GPAGMUX1_GPIO12_S 24 +#define GPIO_GPAGMUX1_GPIO12_M 0x3000000 // Defines pin-muxing selection + // for GPIO12 +#define GPIO_GPAGMUX1_GPIO13_S 26 +#define GPIO_GPAGMUX1_GPIO13_M 0xC000000 // Defines pin-muxing selection + // for GPIO13 +#define GPIO_GPAGMUX1_GPIO14_S 28 +#define GPIO_GPAGMUX1_GPIO14_M 0x30000000 // Defines pin-muxing selection + // for GPIO14 +#define GPIO_GPAGMUX1_GPIO15_S 30 +#define GPIO_GPAGMUX1_GPIO15_M 0xC0000000 // Defines pin-muxing selection + // for GPIO15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAGMUX2 register +// +//***************************************************************************** +#define GPIO_GPAGMUX2_GPIO16_S 0 +#define GPIO_GPAGMUX2_GPIO16_M 0x3 // Defines pin-muxing selection + // for GPIO16 +#define GPIO_GPAGMUX2_GPIO17_S 2 +#define GPIO_GPAGMUX2_GPIO17_M 0xC // Defines pin-muxing selection + // for GPIO17 +#define GPIO_GPAGMUX2_GPIO18_S 4 +#define GPIO_GPAGMUX2_GPIO18_M 0x30 // Defines pin-muxing selection + // for GPIO18 +#define GPIO_GPAGMUX2_GPIO19_S 6 +#define GPIO_GPAGMUX2_GPIO19_M 0xC0 // Defines pin-muxing selection + // for GPIO19 +#define GPIO_GPAGMUX2_GPIO20_S 8 +#define GPIO_GPAGMUX2_GPIO20_M 0x300 // Defines pin-muxing selection + // for GPIO20 +#define GPIO_GPAGMUX2_GPIO21_S 10 +#define GPIO_GPAGMUX2_GPIO21_M 0xC00 // Defines pin-muxing selection + // for GPIO21 +#define GPIO_GPAGMUX2_GPIO22_S 12 +#define GPIO_GPAGMUX2_GPIO22_M 0x3000 // Defines pin-muxing selection + // for GPIO22 +#define GPIO_GPAGMUX2_GPIO23_S 14 +#define GPIO_GPAGMUX2_GPIO23_M 0xC000 // Defines pin-muxing selection + // for GPIO23 +#define GPIO_GPAGMUX2_GPIO24_S 16 +#define GPIO_GPAGMUX2_GPIO24_M 0x30000 // Defines pin-muxing selection + // for GPIO24 +#define GPIO_GPAGMUX2_GPIO25_S 18 +#define GPIO_GPAGMUX2_GPIO25_M 0xC0000 // Defines pin-muxing selection + // for GPIO25 +#define GPIO_GPAGMUX2_GPIO26_S 20 +#define GPIO_GPAGMUX2_GPIO26_M 0x300000 // Defines pin-muxing selection + // for GPIO26 +#define GPIO_GPAGMUX2_GPIO27_S 22 +#define GPIO_GPAGMUX2_GPIO27_M 0xC00000 // Defines pin-muxing selection + // for GPIO27 +#define GPIO_GPAGMUX2_GPIO28_S 24 +#define GPIO_GPAGMUX2_GPIO28_M 0x3000000 // Defines pin-muxing selection + // for GPIO28 +#define GPIO_GPAGMUX2_GPIO29_S 26 +#define GPIO_GPAGMUX2_GPIO29_M 0xC000000 // Defines pin-muxing selection + // for GPIO29 +#define GPIO_GPAGMUX2_GPIO30_S 28 +#define GPIO_GPAGMUX2_GPIO30_M 0x30000000 // Defines pin-muxing selection + // for GPIO30 +#define GPIO_GPAGMUX2_GPIO31_S 30 +#define GPIO_GPAGMUX2_GPIO31_M 0xC0000000 // Defines pin-muxing selection + // for GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL1 register +// +//***************************************************************************** +#define GPIO_GPACSEL1_GPIO0_S 0 +#define GPIO_GPACSEL1_GPIO0_M 0xF // GPIO0 Master CPU Select +#define GPIO_GPACSEL1_GPIO1_S 4 +#define GPIO_GPACSEL1_GPIO1_M 0xF0 // GPIO1 Master CPU Select +#define GPIO_GPACSEL1_GPIO2_S 8 +#define GPIO_GPACSEL1_GPIO2_M 0xF00 // GPIO2 Master CPU Select +#define GPIO_GPACSEL1_GPIO3_S 12 +#define GPIO_GPACSEL1_GPIO3_M 0xF000 // GPIO3 Master CPU Select +#define GPIO_GPACSEL1_GPIO4_S 16 +#define GPIO_GPACSEL1_GPIO4_M 0xF0000 // GPIO4 Master CPU Select +#define GPIO_GPACSEL1_GPIO5_S 20 +#define GPIO_GPACSEL1_GPIO5_M 0xF00000 // GPIO5 Master CPU Select +#define GPIO_GPACSEL1_GPIO6_S 24 +#define GPIO_GPACSEL1_GPIO6_M 0xF000000 // GPIO6 Master CPU Select +#define GPIO_GPACSEL1_GPIO7_S 28 +#define GPIO_GPACSEL1_GPIO7_M 0xF0000000 // GPIO7 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL2 register +// +//***************************************************************************** +#define GPIO_GPACSEL2_GPIO8_S 0 +#define GPIO_GPACSEL2_GPIO8_M 0xF // GPIO8 Master CPU Select +#define GPIO_GPACSEL2_GPIO9_S 4 +#define GPIO_GPACSEL2_GPIO9_M 0xF0 // GPIO9 Master CPU Select +#define GPIO_GPACSEL2_GPIO10_S 8 +#define GPIO_GPACSEL2_GPIO10_M 0xF00 // GPIO10 Master CPU Select +#define GPIO_GPACSEL2_GPIO11_S 12 +#define GPIO_GPACSEL2_GPIO11_M 0xF000 // GPIO11 Master CPU Select +#define GPIO_GPACSEL2_GPIO12_S 16 +#define GPIO_GPACSEL2_GPIO12_M 0xF0000 // GPIO12 Master CPU Select +#define GPIO_GPACSEL2_GPIO13_S 20 +#define GPIO_GPACSEL2_GPIO13_M 0xF00000 // GPIO13 Master CPU Select +#define GPIO_GPACSEL2_GPIO14_S 24 +#define GPIO_GPACSEL2_GPIO14_M 0xF000000 // GPIO14 Master CPU Select +#define GPIO_GPACSEL2_GPIO15_S 28 +#define GPIO_GPACSEL2_GPIO15_M 0xF0000000 // GPIO15 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL3 register +// +//***************************************************************************** +#define GPIO_GPACSEL3_GPIO16_S 0 +#define GPIO_GPACSEL3_GPIO16_M 0xF // GPIO16 Master CPU Select +#define GPIO_GPACSEL3_GPIO17_S 4 +#define GPIO_GPACSEL3_GPIO17_M 0xF0 // GPIO17 Master CPU Select +#define GPIO_GPACSEL3_GPIO18_S 8 +#define GPIO_GPACSEL3_GPIO18_M 0xF00 // GPIO18 Master CPU Select +#define GPIO_GPACSEL3_GPIO19_S 12 +#define GPIO_GPACSEL3_GPIO19_M 0xF000 // GPIO19 Master CPU Select +#define GPIO_GPACSEL3_GPIO20_S 16 +#define GPIO_GPACSEL3_GPIO20_M 0xF0000 // GPIO20 Master CPU Select +#define GPIO_GPACSEL3_GPIO21_S 20 +#define GPIO_GPACSEL3_GPIO21_M 0xF00000 // GPIO21 Master CPU Select +#define GPIO_GPACSEL3_GPIO22_S 24 +#define GPIO_GPACSEL3_GPIO22_M 0xF000000 // GPIO22 Master CPU Select +#define GPIO_GPACSEL3_GPIO23_S 28 +#define GPIO_GPACSEL3_GPIO23_M 0xF0000000 // GPIO23 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL4 register +// +//***************************************************************************** +#define GPIO_GPACSEL4_GPIO24_S 0 +#define GPIO_GPACSEL4_GPIO24_M 0xF // GPIO24 Master CPU Select +#define GPIO_GPACSEL4_GPIO25_S 4 +#define GPIO_GPACSEL4_GPIO25_M 0xF0 // GPIO25 Master CPU Select +#define GPIO_GPACSEL4_GPIO26_S 8 +#define GPIO_GPACSEL4_GPIO26_M 0xF00 // GPIO26 Master CPU Select +#define GPIO_GPACSEL4_GPIO27_S 12 +#define GPIO_GPACSEL4_GPIO27_M 0xF000 // GPIO27 Master CPU Select +#define GPIO_GPACSEL4_GPIO28_S 16 +#define GPIO_GPACSEL4_GPIO28_M 0xF0000 // GPIO28 Master CPU Select +#define GPIO_GPACSEL4_GPIO29_S 20 +#define GPIO_GPACSEL4_GPIO29_M 0xF00000 // GPIO29 Master CPU Select +#define GPIO_GPACSEL4_GPIO30_S 24 +#define GPIO_GPACSEL4_GPIO30_M 0xF000000 // GPIO30 Master CPU Select +#define GPIO_GPACSEL4_GPIO31_S 28 +#define GPIO_GPACSEL4_GPIO31_M 0xF0000000 // GPIO31 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPALOCK register +// +//***************************************************************************** +#define GPIO_GPALOCK_GPIO0 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO1 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO2 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO3 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO4 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO5 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO6 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO7 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO8 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO9 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO10 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO11 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO12 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO13 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO14 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO15 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO16 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO17 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO18 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO19 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO20 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO21 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO22 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO23 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO24 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO25 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO26 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO27 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO28 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO29 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO30 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO31 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACR register +// +//***************************************************************************** +#define GPIO_GPACR_GPIO0 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO1 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO2 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO3 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO4 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO5 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO6 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO7 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO8 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO9 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO10 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO11 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO12 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO13 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO14 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO15 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO16 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO17 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO18 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO19 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO20 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO21 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO22 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO23 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO24 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO25 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO26 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO27 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO28 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO29 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO30 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO31 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCTRL register +// +//***************************************************************************** +#define GPIO_GPBCTRL_QUALPRD0_S 0 +#define GPIO_GPBCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO32 to GPIO39 +#define GPIO_GPBCTRL_QUALPRD1_S 8 +#define GPIO_GPBCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO40 to GPIO47 +#define GPIO_GPBCTRL_QUALPRD2_S 16 +#define GPIO_GPBCTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO48 to GPIO55 +#define GPIO_GPBCTRL_QUALPRD3_S 24 +#define GPIO_GPBCTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO56 to GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBQSEL1 register +// +//***************************************************************************** +#define GPIO_GPBQSEL1_GPIO32_S 0 +#define GPIO_GPBQSEL1_GPIO32_M 0x3 // Select input qualification type + // for GPIO32 +#define GPIO_GPBQSEL1_GPIO33_S 2 +#define GPIO_GPBQSEL1_GPIO33_M 0xC // Select input qualification type + // for GPIO33 +#define GPIO_GPBQSEL1_GPIO34_S 4 +#define GPIO_GPBQSEL1_GPIO34_M 0x30 // Select input qualification type + // for GPIO34 +#define GPIO_GPBQSEL1_GPIO35_S 6 +#define GPIO_GPBQSEL1_GPIO35_M 0xC0 // Select input qualification type + // for GPIO35 +#define GPIO_GPBQSEL1_GPIO36_S 8 +#define GPIO_GPBQSEL1_GPIO36_M 0x300 // Select input qualification type + // for GPIO36 +#define GPIO_GPBQSEL1_GPIO37_S 10 +#define GPIO_GPBQSEL1_GPIO37_M 0xC00 // Select input qualification type + // for GPIO37 +#define GPIO_GPBQSEL1_GPIO38_S 12 +#define GPIO_GPBQSEL1_GPIO38_M 0x3000 // Select input qualification type + // for GPIO38 +#define GPIO_GPBQSEL1_GPIO39_S 14 +#define GPIO_GPBQSEL1_GPIO39_M 0xC000 // Select input qualification type + // for GPIO39 +#define GPIO_GPBQSEL1_GPIO40_S 16 +#define GPIO_GPBQSEL1_GPIO40_M 0x30000 // Select input qualification type + // for GPIO40 +#define GPIO_GPBQSEL1_GPIO41_S 18 +#define GPIO_GPBQSEL1_GPIO41_M 0xC0000 // Select input qualification type + // for GPIO41 +#define GPIO_GPBQSEL1_GPIO42_S 20 +#define GPIO_GPBQSEL1_GPIO42_M 0x300000 // Select input qualification type + // for GPIO42 +#define GPIO_GPBQSEL1_GPIO43_S 22 +#define GPIO_GPBQSEL1_GPIO43_M 0xC00000 // Select input qualification type + // for GPIO43 +#define GPIO_GPBQSEL1_GPIO44_S 24 +#define GPIO_GPBQSEL1_GPIO44_M 0x3000000 // Select input qualification type + // for GPIO44 +#define GPIO_GPBQSEL1_GPIO45_S 26 +#define GPIO_GPBQSEL1_GPIO45_M 0xC000000 // Select input qualification type + // for GPIO45 +#define GPIO_GPBQSEL1_GPIO46_S 28 +#define GPIO_GPBQSEL1_GPIO46_M 0x30000000 // Select input qualification type + // for GPIO46 +#define GPIO_GPBQSEL1_GPIO47_S 30 +#define GPIO_GPBQSEL1_GPIO47_M 0xC0000000 // Select input qualification type + // for GPIO47 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBQSEL2 register +// +//***************************************************************************** +#define GPIO_GPBQSEL2_GPIO48_S 0 +#define GPIO_GPBQSEL2_GPIO48_M 0x3 // Select input qualification type + // for GPIO48 +#define GPIO_GPBQSEL2_GPIO49_S 2 +#define GPIO_GPBQSEL2_GPIO49_M 0xC // Select input qualification type + // for GPIO49 +#define GPIO_GPBQSEL2_GPIO50_S 4 +#define GPIO_GPBQSEL2_GPIO50_M 0x30 // Select input qualification type + // for GPIO50 +#define GPIO_GPBQSEL2_GPIO51_S 6 +#define GPIO_GPBQSEL2_GPIO51_M 0xC0 // Select input qualification type + // for GPIO51 +#define GPIO_GPBQSEL2_GPIO52_S 8 +#define GPIO_GPBQSEL2_GPIO52_M 0x300 // Select input qualification type + // for GPIO52 +#define GPIO_GPBQSEL2_GPIO53_S 10 +#define GPIO_GPBQSEL2_GPIO53_M 0xC00 // Select input qualification type + // for GPIO53 +#define GPIO_GPBQSEL2_GPIO54_S 12 +#define GPIO_GPBQSEL2_GPIO54_M 0x3000 // Select input qualification type + // for GPIO54 +#define GPIO_GPBQSEL2_GPIO55_S 14 +#define GPIO_GPBQSEL2_GPIO55_M 0xC000 // Select input qualification type + // for GPIO55 +#define GPIO_GPBQSEL2_GPIO56_S 16 +#define GPIO_GPBQSEL2_GPIO56_M 0x30000 // Select input qualification type + // for GPIO56 +#define GPIO_GPBQSEL2_GPIO57_S 18 +#define GPIO_GPBQSEL2_GPIO57_M 0xC0000 // Select input qualification type + // for GPIO57 +#define GPIO_GPBQSEL2_GPIO58_S 20 +#define GPIO_GPBQSEL2_GPIO58_M 0x300000 // Select input qualification type + // for GPIO58 +#define GPIO_GPBQSEL2_GPIO59_S 22 +#define GPIO_GPBQSEL2_GPIO59_M 0xC00000 // Select input qualification type + // for GPIO59 +#define GPIO_GPBQSEL2_GPIO60_S 24 +#define GPIO_GPBQSEL2_GPIO60_M 0x3000000 // Select input qualification type + // for GPIO60 +#define GPIO_GPBQSEL2_GPIO61_S 26 +#define GPIO_GPBQSEL2_GPIO61_M 0xC000000 // Select input qualification type + // for GPIO61 +#define GPIO_GPBQSEL2_GPIO62_S 28 +#define GPIO_GPBQSEL2_GPIO62_M 0x30000000 // Select input qualification type + // for GPIO62 +#define GPIO_GPBQSEL2_GPIO63_S 30 +#define GPIO_GPBQSEL2_GPIO63_M 0xC0000000 // Select input qualification type + // for GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBMUX1 register +// +//***************************************************************************** +#define GPIO_GPBMUX1_GPIO32_S 0 +#define GPIO_GPBMUX1_GPIO32_M 0x3 // Defines pin-muxing selection + // for GPIO32 +#define GPIO_GPBMUX1_GPIO33_S 2 +#define GPIO_GPBMUX1_GPIO33_M 0xC // Defines pin-muxing selection + // for GPIO33 +#define GPIO_GPBMUX1_GPIO34_S 4 +#define GPIO_GPBMUX1_GPIO34_M 0x30 // Defines pin-muxing selection + // for GPIO34 +#define GPIO_GPBMUX1_GPIO35_S 6 +#define GPIO_GPBMUX1_GPIO35_M 0xC0 // Defines pin-muxing selection + // for GPIO35 +#define GPIO_GPBMUX1_GPIO36_S 8 +#define GPIO_GPBMUX1_GPIO36_M 0x300 // Defines pin-muxing selection + // for GPIO36 +#define GPIO_GPBMUX1_GPIO37_S 10 +#define GPIO_GPBMUX1_GPIO37_M 0xC00 // Defines pin-muxing selection + // for GPIO37 +#define GPIO_GPBMUX1_GPIO38_S 12 +#define GPIO_GPBMUX1_GPIO38_M 0x3000 // Defines pin-muxing selection + // for GPIO38 +#define GPIO_GPBMUX1_GPIO39_S 14 +#define GPIO_GPBMUX1_GPIO39_M 0xC000 // Defines pin-muxing selection + // for GPIO39 +#define GPIO_GPBMUX1_GPIO40_S 16 +#define GPIO_GPBMUX1_GPIO40_M 0x30000 // Defines pin-muxing selection + // for GPIO40 +#define GPIO_GPBMUX1_GPIO41_S 18 +#define GPIO_GPBMUX1_GPIO41_M 0xC0000 // Defines pin-muxing selection + // for GPIO41 +#define GPIO_GPBMUX1_GPIO42_S 20 +#define GPIO_GPBMUX1_GPIO42_M 0x300000 // Defines pin-muxing selection + // for GPIO42 +#define GPIO_GPBMUX1_GPIO43_S 22 +#define GPIO_GPBMUX1_GPIO43_M 0xC00000 // Defines pin-muxing selection + // for GPIO43 +#define GPIO_GPBMUX1_GPIO44_S 24 +#define GPIO_GPBMUX1_GPIO44_M 0x3000000 // Defines pin-muxing selection + // for GPIO44 +#define GPIO_GPBMUX1_GPIO45_S 26 +#define GPIO_GPBMUX1_GPIO45_M 0xC000000 // Defines pin-muxing selection + // for GPIO45 +#define GPIO_GPBMUX1_GPIO46_S 28 +#define GPIO_GPBMUX1_GPIO46_M 0x30000000 // Defines pin-muxing selection + // for GPIO46 +#define GPIO_GPBMUX1_GPIO47_S 30 +#define GPIO_GPBMUX1_GPIO47_M 0xC0000000 // Defines pin-muxing selection + // for GPIO47 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBMUX2 register +// +//***************************************************************************** +#define GPIO_GPBMUX2_GPIO48_S 0 +#define GPIO_GPBMUX2_GPIO48_M 0x3 // Defines pin-muxing selection + // for GPIO48 +#define GPIO_GPBMUX2_GPIO49_S 2 +#define GPIO_GPBMUX2_GPIO49_M 0xC // Defines pin-muxing selection + // for GPIO49 +#define GPIO_GPBMUX2_GPIO50_S 4 +#define GPIO_GPBMUX2_GPIO50_M 0x30 // Defines pin-muxing selection + // for GPIO50 +#define GPIO_GPBMUX2_GPIO51_S 6 +#define GPIO_GPBMUX2_GPIO51_M 0xC0 // Defines pin-muxing selection + // for GPIO51 +#define GPIO_GPBMUX2_GPIO52_S 8 +#define GPIO_GPBMUX2_GPIO52_M 0x300 // Defines pin-muxing selection + // for GPIO52 +#define GPIO_GPBMUX2_GPIO53_S 10 +#define GPIO_GPBMUX2_GPIO53_M 0xC00 // Defines pin-muxing selection + // for GPIO53 +#define GPIO_GPBMUX2_GPIO54_S 12 +#define GPIO_GPBMUX2_GPIO54_M 0x3000 // Defines pin-muxing selection + // for GPIO54 +#define GPIO_GPBMUX2_GPIO55_S 14 +#define GPIO_GPBMUX2_GPIO55_M 0xC000 // Defines pin-muxing selection + // for GPIO55 +#define GPIO_GPBMUX2_GPIO56_S 16 +#define GPIO_GPBMUX2_GPIO56_M 0x30000 // Defines pin-muxing selection + // for GPIO56 +#define GPIO_GPBMUX2_GPIO57_S 18 +#define GPIO_GPBMUX2_GPIO57_M 0xC0000 // Defines pin-muxing selection + // for GPIO57 +#define GPIO_GPBMUX2_GPIO58_S 20 +#define GPIO_GPBMUX2_GPIO58_M 0x300000 // Defines pin-muxing selection + // for GPIO58 +#define GPIO_GPBMUX2_GPIO59_S 22 +#define GPIO_GPBMUX2_GPIO59_M 0xC00000 // Defines pin-muxing selection + // for GPIO59 +#define GPIO_GPBMUX2_GPIO60_S 24 +#define GPIO_GPBMUX2_GPIO60_M 0x3000000 // Defines pin-muxing selection + // for GPIO60 +#define GPIO_GPBMUX2_GPIO61_S 26 +#define GPIO_GPBMUX2_GPIO61_M 0xC000000 // Defines pin-muxing selection + // for GPIO61 +#define GPIO_GPBMUX2_GPIO62_S 28 +#define GPIO_GPBMUX2_GPIO62_M 0x30000000 // Defines pin-muxing selection + // for GPIO62 +#define GPIO_GPBMUX2_GPIO63_S 30 +#define GPIO_GPBMUX2_GPIO63_M 0xC0000000 // Defines pin-muxing selection + // for GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBDIR register +// +//***************************************************************************** +#define GPIO_GPBDIR_GPIO32 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO33 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO34 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO35 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO36 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO37 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO38 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO39 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO40 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO41 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO42 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO43 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO44 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO45 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO46 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO47 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO48 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO49 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO50 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO51 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO52 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO53 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO54 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO55 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO56 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO57 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO58 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO59 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO60 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO61 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO62 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO63 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBPUD register +// +//***************************************************************************** +#define GPIO_GPBPUD_GPIO32 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO33 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO34 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO35 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO36 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO37 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO38 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO39 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO40 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO41 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO42 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO43 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO44 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO45 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO46 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO47 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO48 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO49 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO50 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO51 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO52 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO53 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO54 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO55 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO56 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO57 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO58 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO59 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO60 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO61 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO62 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO63 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBINV register +// +//***************************************************************************** +#define GPIO_GPBINV_GPIO32 0x1 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO33 0x2 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO34 0x4 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO35 0x8 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO36 0x10 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO37 0x20 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO38 0x40 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO39 0x80 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO40 0x100 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO41 0x200 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO42 0x400 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO43 0x800 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO44 0x1000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO45 0x2000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO46 0x4000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO47 0x8000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO48 0x10000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO49 0x20000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO50 0x40000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO51 0x80000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO52 0x100000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO53 0x200000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO54 0x400000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO55 0x800000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO56 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO57 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO58 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO59 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO60 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO61 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO62 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO63 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBODR register +// +//***************************************************************************** +#define GPIO_GPBODR_GPIO32 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO33 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO34 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO35 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO36 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO37 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO38 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO39 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO40 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO41 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO42 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO43 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO44 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO45 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO46 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO47 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO48 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO49 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO50 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO51 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO52 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO53 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO54 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO55 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO56 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO57 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO58 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO59 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO60 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO61 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO62 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO63 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBAMSEL register +// +//***************************************************************************** +#define GPIO_GPBAMSEL_GPIO42 0x400 // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO43 0x800 // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO46 0x4000 // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO47 0x8000 // Analog Mode select for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBGMUX1 register +// +//***************************************************************************** +#define GPIO_GPBGMUX1_GPIO32_S 0 +#define GPIO_GPBGMUX1_GPIO32_M 0x3 // Defines pin-muxing selection + // for GPIO32 +#define GPIO_GPBGMUX1_GPIO33_S 2 +#define GPIO_GPBGMUX1_GPIO33_M 0xC // Defines pin-muxing selection + // for GPIO33 +#define GPIO_GPBGMUX1_GPIO34_S 4 +#define GPIO_GPBGMUX1_GPIO34_M 0x30 // Defines pin-muxing selection + // for GPIO34 +#define GPIO_GPBGMUX1_GPIO35_S 6 +#define GPIO_GPBGMUX1_GPIO35_M 0xC0 // Defines pin-muxing selection + // for GPIO35 +#define GPIO_GPBGMUX1_GPIO36_S 8 +#define GPIO_GPBGMUX1_GPIO36_M 0x300 // Defines pin-muxing selection + // for GPIO36 +#define GPIO_GPBGMUX1_GPIO37_S 10 +#define GPIO_GPBGMUX1_GPIO37_M 0xC00 // Defines pin-muxing selection + // for GPIO37 +#define GPIO_GPBGMUX1_GPIO38_S 12 +#define GPIO_GPBGMUX1_GPIO38_M 0x3000 // Defines pin-muxing selection + // for GPIO38 +#define GPIO_GPBGMUX1_GPIO39_S 14 +#define GPIO_GPBGMUX1_GPIO39_M 0xC000 // Defines pin-muxing selection + // for GPIO39 +#define GPIO_GPBGMUX1_GPIO40_S 16 +#define GPIO_GPBGMUX1_GPIO40_M 0x30000 // Defines pin-muxing selection + // for GPIO40 +#define GPIO_GPBGMUX1_GPIO41_S 18 +#define GPIO_GPBGMUX1_GPIO41_M 0xC0000 // Defines pin-muxing selection + // for GPIO41 +#define GPIO_GPBGMUX1_GPIO42_S 20 +#define GPIO_GPBGMUX1_GPIO42_M 0x300000 // Defines pin-muxing selection + // for GPIO42 +#define GPIO_GPBGMUX1_GPIO43_S 22 +#define GPIO_GPBGMUX1_GPIO43_M 0xC00000 // Defines pin-muxing selection + // for GPIO43 +#define GPIO_GPBGMUX1_GPIO44_S 24 +#define GPIO_GPBGMUX1_GPIO44_M 0x3000000 // Defines pin-muxing selection + // for GPIO44 +#define GPIO_GPBGMUX1_GPIO45_S 26 +#define GPIO_GPBGMUX1_GPIO45_M 0xC000000 // Defines pin-muxing selection + // for GPIO45 +#define GPIO_GPBGMUX1_GPIO46_S 28 +#define GPIO_GPBGMUX1_GPIO46_M 0x30000000 // Defines pin-muxing selection + // for GPIO46 +#define GPIO_GPBGMUX1_GPIO47_S 30 +#define GPIO_GPBGMUX1_GPIO47_M 0xC0000000 // Defines pin-muxing selection + // for GPIO47 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBGMUX2 register +// +//***************************************************************************** +#define GPIO_GPBGMUX2_GPIO48_S 0 +#define GPIO_GPBGMUX2_GPIO48_M 0x3 // Defines pin-muxing selection + // for GPIO48 +#define GPIO_GPBGMUX2_GPIO49_S 2 +#define GPIO_GPBGMUX2_GPIO49_M 0xC // Defines pin-muxing selection + // for GPIO49 +#define GPIO_GPBGMUX2_GPIO50_S 4 +#define GPIO_GPBGMUX2_GPIO50_M 0x30 // Defines pin-muxing selection + // for GPIO50 +#define GPIO_GPBGMUX2_GPIO51_S 6 +#define GPIO_GPBGMUX2_GPIO51_M 0xC0 // Defines pin-muxing selection + // for GPIO51 +#define GPIO_GPBGMUX2_GPIO52_S 8 +#define GPIO_GPBGMUX2_GPIO52_M 0x300 // Defines pin-muxing selection + // for GPIO52 +#define GPIO_GPBGMUX2_GPIO53_S 10 +#define GPIO_GPBGMUX2_GPIO53_M 0xC00 // Defines pin-muxing selection + // for GPIO53 +#define GPIO_GPBGMUX2_GPIO54_S 12 +#define GPIO_GPBGMUX2_GPIO54_M 0x3000 // Defines pin-muxing selection + // for GPIO54 +#define GPIO_GPBGMUX2_GPIO55_S 14 +#define GPIO_GPBGMUX2_GPIO55_M 0xC000 // Defines pin-muxing selection + // for GPIO55 +#define GPIO_GPBGMUX2_GPIO56_S 16 +#define GPIO_GPBGMUX2_GPIO56_M 0x30000 // Defines pin-muxing selection + // for GPIO56 +#define GPIO_GPBGMUX2_GPIO57_S 18 +#define GPIO_GPBGMUX2_GPIO57_M 0xC0000 // Defines pin-muxing selection + // for GPIO57 +#define GPIO_GPBGMUX2_GPIO58_S 20 +#define GPIO_GPBGMUX2_GPIO58_M 0x300000 // Defines pin-muxing selection + // for GPIO58 +#define GPIO_GPBGMUX2_GPIO59_S 22 +#define GPIO_GPBGMUX2_GPIO59_M 0xC00000 // Defines pin-muxing selection + // for GPIO59 +#define GPIO_GPBGMUX2_GPIO60_S 24 +#define GPIO_GPBGMUX2_GPIO60_M 0x3000000 // Defines pin-muxing selection + // for GPIO60 +#define GPIO_GPBGMUX2_GPIO61_S 26 +#define GPIO_GPBGMUX2_GPIO61_M 0xC000000 // Defines pin-muxing selection + // for GPIO61 +#define GPIO_GPBGMUX2_GPIO62_S 28 +#define GPIO_GPBGMUX2_GPIO62_M 0x30000000 // Defines pin-muxing selection + // for GPIO62 +#define GPIO_GPBGMUX2_GPIO63_S 30 +#define GPIO_GPBGMUX2_GPIO63_M 0xC0000000 // Defines pin-muxing selection + // for GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL1 register +// +//***************************************************************************** +#define GPIO_GPBCSEL1_GPIO32_S 0 +#define GPIO_GPBCSEL1_GPIO32_M 0xF // GPIO32 Master CPU Select +#define GPIO_GPBCSEL1_GPIO33_S 4 +#define GPIO_GPBCSEL1_GPIO33_M 0xF0 // GPIO33 Master CPU Select +#define GPIO_GPBCSEL1_GPIO34_S 8 +#define GPIO_GPBCSEL1_GPIO34_M 0xF00 // GPIO34 Master CPU Select +#define GPIO_GPBCSEL1_GPIO35_S 12 +#define GPIO_GPBCSEL1_GPIO35_M 0xF000 // GPIO35 Master CPU Select +#define GPIO_GPBCSEL1_GPIO36_S 16 +#define GPIO_GPBCSEL1_GPIO36_M 0xF0000 // GPIO36 Master CPU Select +#define GPIO_GPBCSEL1_GPIO37_S 20 +#define GPIO_GPBCSEL1_GPIO37_M 0xF00000 // GPIO37 Master CPU Select +#define GPIO_GPBCSEL1_GPIO38_S 24 +#define GPIO_GPBCSEL1_GPIO38_M 0xF000000 // GPIO38 Master CPU Select +#define GPIO_GPBCSEL1_GPIO39_S 28 +#define GPIO_GPBCSEL1_GPIO39_M 0xF0000000 // GPIO39 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL2 register +// +//***************************************************************************** +#define GPIO_GPBCSEL2_GPIO40_S 0 +#define GPIO_GPBCSEL2_GPIO40_M 0xF // GPIO40 Master CPU Select +#define GPIO_GPBCSEL2_GPIO41_S 4 +#define GPIO_GPBCSEL2_GPIO41_M 0xF0 // GPIO41 Master CPU Select +#define GPIO_GPBCSEL2_GPIO42_S 8 +#define GPIO_GPBCSEL2_GPIO42_M 0xF00 // GPIO42 Master CPU Select +#define GPIO_GPBCSEL2_GPIO43_S 12 +#define GPIO_GPBCSEL2_GPIO43_M 0xF000 // GPIO43 Master CPU Select +#define GPIO_GPBCSEL2_GPIO44_S 16 +#define GPIO_GPBCSEL2_GPIO44_M 0xF0000 // GPIO44 Master CPU Select +#define GPIO_GPBCSEL2_GPIO45_S 20 +#define GPIO_GPBCSEL2_GPIO45_M 0xF00000 // GPIO45 Master CPU Select +#define GPIO_GPBCSEL2_GPIO46_S 24 +#define GPIO_GPBCSEL2_GPIO46_M 0xF000000 // GPIO46 Master CPU Select +#define GPIO_GPBCSEL2_GPIO47_S 28 +#define GPIO_GPBCSEL2_GPIO47_M 0xF0000000 // GPIO47 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL3 register +// +//***************************************************************************** +#define GPIO_GPBCSEL3_GPIO48_S 0 +#define GPIO_GPBCSEL3_GPIO48_M 0xF // GPIO48 Master CPU Select +#define GPIO_GPBCSEL3_GPIO49_S 4 +#define GPIO_GPBCSEL3_GPIO49_M 0xF0 // GPIO49 Master CPU Select +#define GPIO_GPBCSEL3_GPIO50_S 8 +#define GPIO_GPBCSEL3_GPIO50_M 0xF00 // GPIO50 Master CPU Select +#define GPIO_GPBCSEL3_GPIO51_S 12 +#define GPIO_GPBCSEL3_GPIO51_M 0xF000 // GPIO51 Master CPU Select +#define GPIO_GPBCSEL3_GPIO52_S 16 +#define GPIO_GPBCSEL3_GPIO52_M 0xF0000 // GPIO52 Master CPU Select +#define GPIO_GPBCSEL3_GPIO53_S 20 +#define GPIO_GPBCSEL3_GPIO53_M 0xF00000 // GPIO53 Master CPU Select +#define GPIO_GPBCSEL3_GPIO54_S 24 +#define GPIO_GPBCSEL3_GPIO54_M 0xF000000 // GPIO54 Master CPU Select +#define GPIO_GPBCSEL3_GPIO55_S 28 +#define GPIO_GPBCSEL3_GPIO55_M 0xF0000000 // GPIO55 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL4 register +// +//***************************************************************************** +#define GPIO_GPBCSEL4_GPIO56_S 0 +#define GPIO_GPBCSEL4_GPIO56_M 0xF // GPIO56 Master CPU Select +#define GPIO_GPBCSEL4_GPIO57_S 4 +#define GPIO_GPBCSEL4_GPIO57_M 0xF0 // GPIO57 Master CPU Select +#define GPIO_GPBCSEL4_GPIO58_S 8 +#define GPIO_GPBCSEL4_GPIO58_M 0xF00 // GPIO58 Master CPU Select +#define GPIO_GPBCSEL4_GPIO59_S 12 +#define GPIO_GPBCSEL4_GPIO59_M 0xF000 // GPIO59 Master CPU Select +#define GPIO_GPBCSEL4_GPIO60_S 16 +#define GPIO_GPBCSEL4_GPIO60_M 0xF0000 // GPIO60 Master CPU Select +#define GPIO_GPBCSEL4_GPIO61_S 20 +#define GPIO_GPBCSEL4_GPIO61_M 0xF00000 // GPIO61 Master CPU Select +#define GPIO_GPBCSEL4_GPIO62_S 24 +#define GPIO_GPBCSEL4_GPIO62_M 0xF000000 // GPIO62 Master CPU Select +#define GPIO_GPBCSEL4_GPIO63_S 28 +#define GPIO_GPBCSEL4_GPIO63_M 0xF0000000 // GPIO63 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBLOCK register +// +//***************************************************************************** +#define GPIO_GPBLOCK_GPIO32 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO33 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO34 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO35 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO36 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO37 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO38 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO39 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO40 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO41 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO42 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO43 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO44 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO45 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO46 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO47 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO48 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO49 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO50 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO51 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO52 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO53 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO54 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO55 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO56 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO57 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO58 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO59 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO60 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO61 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO62 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO63 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCR register +// +//***************************************************************************** +#define GPIO_GPBCR_GPIO32 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO33 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO34 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO35 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO36 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO37 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO38 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO39 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO40 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO41 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO42 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO43 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO44 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO45 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO46 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO47 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO48 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO49 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO50 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO51 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO52 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO53 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO54 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO55 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO56 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO57 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO58 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO59 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO60 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO61 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO62 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO63 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCTRL register +// +//***************************************************************************** +#define GPIO_GPCCTRL_QUALPRD0_S 0 +#define GPIO_GPCCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO64 to GPIO71 +#define GPIO_GPCCTRL_QUALPRD1_S 8 +#define GPIO_GPCCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO72 to GPIO79 +#define GPIO_GPCCTRL_QUALPRD2_S 16 +#define GPIO_GPCCTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO80 to GPIO87 +#define GPIO_GPCCTRL_QUALPRD3_S 24 +#define GPIO_GPCCTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO88 to GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCQSEL1 register +// +//***************************************************************************** +#define GPIO_GPCQSEL1_GPIO64_S 0 +#define GPIO_GPCQSEL1_GPIO64_M 0x3 // Select input qualification type + // for GPIO64 +#define GPIO_GPCQSEL1_GPIO65_S 2 +#define GPIO_GPCQSEL1_GPIO65_M 0xC // Select input qualification type + // for GPIO65 +#define GPIO_GPCQSEL1_GPIO66_S 4 +#define GPIO_GPCQSEL1_GPIO66_M 0x30 // Select input qualification type + // for GPIO66 +#define GPIO_GPCQSEL1_GPIO67_S 6 +#define GPIO_GPCQSEL1_GPIO67_M 0xC0 // Select input qualification type + // for GPIO67 +#define GPIO_GPCQSEL1_GPIO68_S 8 +#define GPIO_GPCQSEL1_GPIO68_M 0x300 // Select input qualification type + // for GPIO68 +#define GPIO_GPCQSEL1_GPIO69_S 10 +#define GPIO_GPCQSEL1_GPIO69_M 0xC00 // Select input qualification type + // for GPIO69 +#define GPIO_GPCQSEL1_GPIO70_S 12 +#define GPIO_GPCQSEL1_GPIO70_M 0x3000 // Select input qualification type + // for GPIO70 +#define GPIO_GPCQSEL1_GPIO71_S 14 +#define GPIO_GPCQSEL1_GPIO71_M 0xC000 // Select input qualification type + // for GPIO71 +#define GPIO_GPCQSEL1_GPIO72_S 16 +#define GPIO_GPCQSEL1_GPIO72_M 0x30000 // Select input qualification type + // for GPIO72 +#define GPIO_GPCQSEL1_GPIO73_S 18 +#define GPIO_GPCQSEL1_GPIO73_M 0xC0000 // Select input qualification type + // for GPIO73 +#define GPIO_GPCQSEL1_GPIO74_S 20 +#define GPIO_GPCQSEL1_GPIO74_M 0x300000 // Select input qualification type + // for GPIO74 +#define GPIO_GPCQSEL1_GPIO75_S 22 +#define GPIO_GPCQSEL1_GPIO75_M 0xC00000 // Select input qualification type + // for GPIO75 +#define GPIO_GPCQSEL1_GPIO76_S 24 +#define GPIO_GPCQSEL1_GPIO76_M 0x3000000 // Select input qualification type + // for GPIO76 +#define GPIO_GPCQSEL1_GPIO77_S 26 +#define GPIO_GPCQSEL1_GPIO77_M 0xC000000 // Select input qualification type + // for GPIO77 +#define GPIO_GPCQSEL1_GPIO78_S 28 +#define GPIO_GPCQSEL1_GPIO78_M 0x30000000 // Select input qualification type + // for GPIO78 +#define GPIO_GPCQSEL1_GPIO79_S 30 +#define GPIO_GPCQSEL1_GPIO79_M 0xC0000000 // Select input qualification type + // for GPIO79 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCQSEL2 register +// +//***************************************************************************** +#define GPIO_GPCQSEL2_GPIO80_S 0 +#define GPIO_GPCQSEL2_GPIO80_M 0x3 // Select input qualification type + // for GPIO80 +#define GPIO_GPCQSEL2_GPIO81_S 2 +#define GPIO_GPCQSEL2_GPIO81_M 0xC // Select input qualification type + // for GPIO81 +#define GPIO_GPCQSEL2_GPIO82_S 4 +#define GPIO_GPCQSEL2_GPIO82_M 0x30 // Select input qualification type + // for GPIO82 +#define GPIO_GPCQSEL2_GPIO83_S 6 +#define GPIO_GPCQSEL2_GPIO83_M 0xC0 // Select input qualification type + // for GPIO83 +#define GPIO_GPCQSEL2_GPIO84_S 8 +#define GPIO_GPCQSEL2_GPIO84_M 0x300 // Select input qualification type + // for GPIO84 +#define GPIO_GPCQSEL2_GPIO85_S 10 +#define GPIO_GPCQSEL2_GPIO85_M 0xC00 // Select input qualification type + // for GPIO85 +#define GPIO_GPCQSEL2_GPIO86_S 12 +#define GPIO_GPCQSEL2_GPIO86_M 0x3000 // Select input qualification type + // for GPIO86 +#define GPIO_GPCQSEL2_GPIO87_S 14 +#define GPIO_GPCQSEL2_GPIO87_M 0xC000 // Select input qualification type + // for GPIO87 +#define GPIO_GPCQSEL2_GPIO88_S 16 +#define GPIO_GPCQSEL2_GPIO88_M 0x30000 // Select input qualification type + // for GPIO88 +#define GPIO_GPCQSEL2_GPIO89_S 18 +#define GPIO_GPCQSEL2_GPIO89_M 0xC0000 // Select input qualification type + // for GPIO89 +#define GPIO_GPCQSEL2_GPIO90_S 20 +#define GPIO_GPCQSEL2_GPIO90_M 0x300000 // Select input qualification type + // for GPIO90 +#define GPIO_GPCQSEL2_GPIO91_S 22 +#define GPIO_GPCQSEL2_GPIO91_M 0xC00000 // Select input qualification type + // for GPIO91 +#define GPIO_GPCQSEL2_GPIO92_S 24 +#define GPIO_GPCQSEL2_GPIO92_M 0x3000000 // Select input qualification type + // for GPIO92 +#define GPIO_GPCQSEL2_GPIO93_S 26 +#define GPIO_GPCQSEL2_GPIO93_M 0xC000000 // Select input qualification type + // for GPIO93 +#define GPIO_GPCQSEL2_GPIO94_S 28 +#define GPIO_GPCQSEL2_GPIO94_M 0x30000000 // Select input qualification type + // for GPIO94 +#define GPIO_GPCQSEL2_GPIO95_S 30 +#define GPIO_GPCQSEL2_GPIO95_M 0xC0000000 // Select input qualification type + // for GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCMUX1 register +// +//***************************************************************************** +#define GPIO_GPCMUX1_GPIO64_S 0 +#define GPIO_GPCMUX1_GPIO64_M 0x3 // Defines pin-muxing selection + // for GPIO64 +#define GPIO_GPCMUX1_GPIO65_S 2 +#define GPIO_GPCMUX1_GPIO65_M 0xC // Defines pin-muxing selection + // for GPIO65 +#define GPIO_GPCMUX1_GPIO66_S 4 +#define GPIO_GPCMUX1_GPIO66_M 0x30 // Defines pin-muxing selection + // for GPIO66 +#define GPIO_GPCMUX1_GPIO67_S 6 +#define GPIO_GPCMUX1_GPIO67_M 0xC0 // Defines pin-muxing selection + // for GPIO67 +#define GPIO_GPCMUX1_GPIO68_S 8 +#define GPIO_GPCMUX1_GPIO68_M 0x300 // Defines pin-muxing selection + // for GPIO68 +#define GPIO_GPCMUX1_GPIO69_S 10 +#define GPIO_GPCMUX1_GPIO69_M 0xC00 // Defines pin-muxing selection + // for GPIO69 +#define GPIO_GPCMUX1_GPIO70_S 12 +#define GPIO_GPCMUX1_GPIO70_M 0x3000 // Defines pin-muxing selection + // for GPIO70 +#define GPIO_GPCMUX1_GPIO71_S 14 +#define GPIO_GPCMUX1_GPIO71_M 0xC000 // Defines pin-muxing selection + // for GPIO71 +#define GPIO_GPCMUX1_GPIO72_S 16 +#define GPIO_GPCMUX1_GPIO72_M 0x30000 // Defines pin-muxing selection + // for GPIO72 +#define GPIO_GPCMUX1_GPIO73_S 18 +#define GPIO_GPCMUX1_GPIO73_M 0xC0000 // Defines pin-muxing selection + // for GPIO73 +#define GPIO_GPCMUX1_GPIO74_S 20 +#define GPIO_GPCMUX1_GPIO74_M 0x300000 // Defines pin-muxing selection + // for GPIO74 +#define GPIO_GPCMUX1_GPIO75_S 22 +#define GPIO_GPCMUX1_GPIO75_M 0xC00000 // Defines pin-muxing selection + // for GPIO75 +#define GPIO_GPCMUX1_GPIO76_S 24 +#define GPIO_GPCMUX1_GPIO76_M 0x3000000 // Defines pin-muxing selection + // for GPIO76 +#define GPIO_GPCMUX1_GPIO77_S 26 +#define GPIO_GPCMUX1_GPIO77_M 0xC000000 // Defines pin-muxing selection + // for GPIO77 +#define GPIO_GPCMUX1_GPIO78_S 28 +#define GPIO_GPCMUX1_GPIO78_M 0x30000000 // Defines pin-muxing selection + // for GPIO78 +#define GPIO_GPCMUX1_GPIO79_S 30 +#define GPIO_GPCMUX1_GPIO79_M 0xC0000000 // Defines pin-muxing selection + // for GPIO79 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCMUX2 register +// +//***************************************************************************** +#define GPIO_GPCMUX2_GPIO80_S 0 +#define GPIO_GPCMUX2_GPIO80_M 0x3 // Defines pin-muxing selection + // for GPIO80 +#define GPIO_GPCMUX2_GPIO81_S 2 +#define GPIO_GPCMUX2_GPIO81_M 0xC // Defines pin-muxing selection + // for GPIO81 +#define GPIO_GPCMUX2_GPIO82_S 4 +#define GPIO_GPCMUX2_GPIO82_M 0x30 // Defines pin-muxing selection + // for GPIO82 +#define GPIO_GPCMUX2_GPIO83_S 6 +#define GPIO_GPCMUX2_GPIO83_M 0xC0 // Defines pin-muxing selection + // for GPIO83 +#define GPIO_GPCMUX2_GPIO84_S 8 +#define GPIO_GPCMUX2_GPIO84_M 0x300 // Defines pin-muxing selection + // for GPIO84 +#define GPIO_GPCMUX2_GPIO85_S 10 +#define GPIO_GPCMUX2_GPIO85_M 0xC00 // Defines pin-muxing selection + // for GPIO85 +#define GPIO_GPCMUX2_GPIO86_S 12 +#define GPIO_GPCMUX2_GPIO86_M 0x3000 // Defines pin-muxing selection + // for GPIO86 +#define GPIO_GPCMUX2_GPIO87_S 14 +#define GPIO_GPCMUX2_GPIO87_M 0xC000 // Defines pin-muxing selection + // for GPIO87 +#define GPIO_GPCMUX2_GPIO88_S 16 +#define GPIO_GPCMUX2_GPIO88_M 0x30000 // Defines pin-muxing selection + // for GPIO88 +#define GPIO_GPCMUX2_GPIO89_S 18 +#define GPIO_GPCMUX2_GPIO89_M 0xC0000 // Defines pin-muxing selection + // for GPIO89 +#define GPIO_GPCMUX2_GPIO90_S 20 +#define GPIO_GPCMUX2_GPIO90_M 0x300000 // Defines pin-muxing selection + // for GPIO90 +#define GPIO_GPCMUX2_GPIO91_S 22 +#define GPIO_GPCMUX2_GPIO91_M 0xC00000 // Defines pin-muxing selection + // for GPIO91 +#define GPIO_GPCMUX2_GPIO92_S 24 +#define GPIO_GPCMUX2_GPIO92_M 0x3000000 // Defines pin-muxing selection + // for GPIO92 +#define GPIO_GPCMUX2_GPIO93_S 26 +#define GPIO_GPCMUX2_GPIO93_M 0xC000000 // Defines pin-muxing selection + // for GPIO93 +#define GPIO_GPCMUX2_GPIO94_S 28 +#define GPIO_GPCMUX2_GPIO94_M 0x30000000 // Defines pin-muxing selection + // for GPIO94 +#define GPIO_GPCMUX2_GPIO95_S 30 +#define GPIO_GPCMUX2_GPIO95_M 0xC0000000 // Defines pin-muxing selection + // for GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCDIR register +// +//***************************************************************************** +#define GPIO_GPCDIR_GPIO64 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO65 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO66 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO67 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO68 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO69 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO70 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO71 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO72 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO73 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO74 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO75 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO76 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO77 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO78 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO79 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO80 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO81 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO82 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO83 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO84 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO85 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO86 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO87 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO88 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO89 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO90 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO91 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO92 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO93 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO94 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO95 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCPUD register +// +//***************************************************************************** +#define GPIO_GPCPUD_GPIO64 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO65 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO66 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO67 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO68 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO69 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO70 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO71 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO72 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO73 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO74 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO75 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO76 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO77 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO78 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO79 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO80 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO81 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO82 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO83 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO84 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO85 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO86 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO87 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO88 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO89 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO90 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO91 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO92 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO93 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO94 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO95 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCINV register +// +//***************************************************************************** +#define GPIO_GPCINV_GPIO64 0x1 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO65 0x2 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO66 0x4 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO67 0x8 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO68 0x10 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO69 0x20 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO70 0x40 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO71 0x80 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO72 0x100 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO73 0x200 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO74 0x400 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO75 0x800 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO76 0x1000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO77 0x2000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO78 0x4000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO79 0x8000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO80 0x10000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO81 0x20000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO82 0x40000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO83 0x80000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO84 0x100000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO85 0x200000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO86 0x400000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO87 0x800000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO88 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO89 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO90 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO91 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO92 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO93 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO94 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO95 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCODR register +// +//***************************************************************************** +#define GPIO_GPCODR_GPIO64 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO65 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO66 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO67 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO68 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO69 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO70 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO71 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO72 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO73 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO74 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO75 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO76 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO77 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO78 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO79 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO80 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO81 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO82 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO83 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO84 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO85 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO86 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO87 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO88 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO89 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO90 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO91 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO92 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO93 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO94 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO95 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCGMUX1 register +// +//***************************************************************************** +#define GPIO_GPCGMUX1_GPIO64_S 0 +#define GPIO_GPCGMUX1_GPIO64_M 0x3 // Defines pin-muxing selection + // for GPIO64 +#define GPIO_GPCGMUX1_GPIO65_S 2 +#define GPIO_GPCGMUX1_GPIO65_M 0xC // Defines pin-muxing selection + // for GPIO65 +#define GPIO_GPCGMUX1_GPIO66_S 4 +#define GPIO_GPCGMUX1_GPIO66_M 0x30 // Defines pin-muxing selection + // for GPIO66 +#define GPIO_GPCGMUX1_GPIO67_S 6 +#define GPIO_GPCGMUX1_GPIO67_M 0xC0 // Defines pin-muxing selection + // for GPIO67 +#define GPIO_GPCGMUX1_GPIO68_S 8 +#define GPIO_GPCGMUX1_GPIO68_M 0x300 // Defines pin-muxing selection + // for GPIO68 +#define GPIO_GPCGMUX1_GPIO69_S 10 +#define GPIO_GPCGMUX1_GPIO69_M 0xC00 // Defines pin-muxing selection + // for GPIO69 +#define GPIO_GPCGMUX1_GPIO70_S 12 +#define GPIO_GPCGMUX1_GPIO70_M 0x3000 // Defines pin-muxing selection + // for GPIO70 +#define GPIO_GPCGMUX1_GPIO71_S 14 +#define GPIO_GPCGMUX1_GPIO71_M 0xC000 // Defines pin-muxing selection + // for GPIO71 +#define GPIO_GPCGMUX1_GPIO72_S 16 +#define GPIO_GPCGMUX1_GPIO72_M 0x30000 // Defines pin-muxing selection + // for GPIO72 +#define GPIO_GPCGMUX1_GPIO73_S 18 +#define GPIO_GPCGMUX1_GPIO73_M 0xC0000 // Defines pin-muxing selection + // for GPIO73 +#define GPIO_GPCGMUX1_GPIO74_S 20 +#define GPIO_GPCGMUX1_GPIO74_M 0x300000 // Defines pin-muxing selection + // for GPIO74 +#define GPIO_GPCGMUX1_GPIO75_S 22 +#define GPIO_GPCGMUX1_GPIO75_M 0xC00000 // Defines pin-muxing selection + // for GPIO75 +#define GPIO_GPCGMUX1_GPIO76_S 24 +#define GPIO_GPCGMUX1_GPIO76_M 0x3000000 // Defines pin-muxing selection + // for GPIO76 +#define GPIO_GPCGMUX1_GPIO77_S 26 +#define GPIO_GPCGMUX1_GPIO77_M 0xC000000 // Defines pin-muxing selection + // for GPIO77 +#define GPIO_GPCGMUX1_GPIO78_S 28 +#define GPIO_GPCGMUX1_GPIO78_M 0x30000000 // Defines pin-muxing selection + // for GPIO78 +#define GPIO_GPCGMUX1_GPIO79_S 30 +#define GPIO_GPCGMUX1_GPIO79_M 0xC0000000 // Defines pin-muxing selection + // for GPIO79 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCGMUX2 register +// +//***************************************************************************** +#define GPIO_GPCGMUX2_GPIO80_S 0 +#define GPIO_GPCGMUX2_GPIO80_M 0x3 // Defines pin-muxing selection + // for GPIO80 +#define GPIO_GPCGMUX2_GPIO81_S 2 +#define GPIO_GPCGMUX2_GPIO81_M 0xC // Defines pin-muxing selection + // for GPIO81 +#define GPIO_GPCGMUX2_GPIO82_S 4 +#define GPIO_GPCGMUX2_GPIO82_M 0x30 // Defines pin-muxing selection + // for GPIO82 +#define GPIO_GPCGMUX2_GPIO83_S 6 +#define GPIO_GPCGMUX2_GPIO83_M 0xC0 // Defines pin-muxing selection + // for GPIO83 +#define GPIO_GPCGMUX2_GPIO84_S 8 +#define GPIO_GPCGMUX2_GPIO84_M 0x300 // Defines pin-muxing selection + // for GPIO84 +#define GPIO_GPCGMUX2_GPIO85_S 10 +#define GPIO_GPCGMUX2_GPIO85_M 0xC00 // Defines pin-muxing selection + // for GPIO85 +#define GPIO_GPCGMUX2_GPIO86_S 12 +#define GPIO_GPCGMUX2_GPIO86_M 0x3000 // Defines pin-muxing selection + // for GPIO86 +#define GPIO_GPCGMUX2_GPIO87_S 14 +#define GPIO_GPCGMUX2_GPIO87_M 0xC000 // Defines pin-muxing selection + // for GPIO87 +#define GPIO_GPCGMUX2_GPIO88_S 16 +#define GPIO_GPCGMUX2_GPIO88_M 0x30000 // Defines pin-muxing selection + // for GPIO88 +#define GPIO_GPCGMUX2_GPIO89_S 18 +#define GPIO_GPCGMUX2_GPIO89_M 0xC0000 // Defines pin-muxing selection + // for GPIO89 +#define GPIO_GPCGMUX2_GPIO90_S 20 +#define GPIO_GPCGMUX2_GPIO90_M 0x300000 // Defines pin-muxing selection + // for GPIO90 +#define GPIO_GPCGMUX2_GPIO91_S 22 +#define GPIO_GPCGMUX2_GPIO91_M 0xC00000 // Defines pin-muxing selection + // for GPIO91 +#define GPIO_GPCGMUX2_GPIO92_S 24 +#define GPIO_GPCGMUX2_GPIO92_M 0x3000000 // Defines pin-muxing selection + // for GPIO92 +#define GPIO_GPCGMUX2_GPIO93_S 26 +#define GPIO_GPCGMUX2_GPIO93_M 0xC000000 // Defines pin-muxing selection + // for GPIO93 +#define GPIO_GPCGMUX2_GPIO94_S 28 +#define GPIO_GPCGMUX2_GPIO94_M 0x30000000 // Defines pin-muxing selection + // for GPIO94 +#define GPIO_GPCGMUX2_GPIO95_S 30 +#define GPIO_GPCGMUX2_GPIO95_M 0xC0000000 // Defines pin-muxing selection + // for GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL1 register +// +//***************************************************************************** +#define GPIO_GPCCSEL1_GPIO64_S 0 +#define GPIO_GPCCSEL1_GPIO64_M 0xF // GPIO64 Master CPU Select +#define GPIO_GPCCSEL1_GPIO65_S 4 +#define GPIO_GPCCSEL1_GPIO65_M 0xF0 // GPIO65 Master CPU Select +#define GPIO_GPCCSEL1_GPIO66_S 8 +#define GPIO_GPCCSEL1_GPIO66_M 0xF00 // GPIO66 Master CPU Select +#define GPIO_GPCCSEL1_GPIO67_S 12 +#define GPIO_GPCCSEL1_GPIO67_M 0xF000 // GPIO67 Master CPU Select +#define GPIO_GPCCSEL1_GPIO68_S 16 +#define GPIO_GPCCSEL1_GPIO68_M 0xF0000 // GPIO68 Master CPU Select +#define GPIO_GPCCSEL1_GPIO69_S 20 +#define GPIO_GPCCSEL1_GPIO69_M 0xF00000 // GPIO69 Master CPU Select +#define GPIO_GPCCSEL1_GPIO70_S 24 +#define GPIO_GPCCSEL1_GPIO70_M 0xF000000 // GPIO70 Master CPU Select +#define GPIO_GPCCSEL1_GPIO71_S 28 +#define GPIO_GPCCSEL1_GPIO71_M 0xF0000000 // GPIO71 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL2 register +// +//***************************************************************************** +#define GPIO_GPCCSEL2_GPIO72_S 0 +#define GPIO_GPCCSEL2_GPIO72_M 0xF // GPIO72 Master CPU Select +#define GPIO_GPCCSEL2_GPIO73_S 4 +#define GPIO_GPCCSEL2_GPIO73_M 0xF0 // GPIO73 Master CPU Select +#define GPIO_GPCCSEL2_GPIO74_S 8 +#define GPIO_GPCCSEL2_GPIO74_M 0xF00 // GPIO74 Master CPU Select +#define GPIO_GPCCSEL2_GPIO75_S 12 +#define GPIO_GPCCSEL2_GPIO75_M 0xF000 // GPIO75 Master CPU Select +#define GPIO_GPCCSEL2_GPIO76_S 16 +#define GPIO_GPCCSEL2_GPIO76_M 0xF0000 // GPIO76 Master CPU Select +#define GPIO_GPCCSEL2_GPIO77_S 20 +#define GPIO_GPCCSEL2_GPIO77_M 0xF00000 // GPIO77 Master CPU Select +#define GPIO_GPCCSEL2_GPIO78_S 24 +#define GPIO_GPCCSEL2_GPIO78_M 0xF000000 // GPIO78 Master CPU Select +#define GPIO_GPCCSEL2_GPIO79_S 28 +#define GPIO_GPCCSEL2_GPIO79_M 0xF0000000 // GPIO79 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL3 register +// +//***************************************************************************** +#define GPIO_GPCCSEL3_GPIO80_S 0 +#define GPIO_GPCCSEL3_GPIO80_M 0xF // GPIO80 Master CPU Select +#define GPIO_GPCCSEL3_GPIO81_S 4 +#define GPIO_GPCCSEL3_GPIO81_M 0xF0 // GPIO81 Master CPU Select +#define GPIO_GPCCSEL3_GPIO82_S 8 +#define GPIO_GPCCSEL3_GPIO82_M 0xF00 // GPIO82 Master CPU Select +#define GPIO_GPCCSEL3_GPIO83_S 12 +#define GPIO_GPCCSEL3_GPIO83_M 0xF000 // GPIO83 Master CPU Select +#define GPIO_GPCCSEL3_GPIO84_S 16 +#define GPIO_GPCCSEL3_GPIO84_M 0xF0000 // GPIO84 Master CPU Select +#define GPIO_GPCCSEL3_GPIO85_S 20 +#define GPIO_GPCCSEL3_GPIO85_M 0xF00000 // GPIO85 Master CPU Select +#define GPIO_GPCCSEL3_GPIO86_S 24 +#define GPIO_GPCCSEL3_GPIO86_M 0xF000000 // GPIO86 Master CPU Select +#define GPIO_GPCCSEL3_GPIO87_S 28 +#define GPIO_GPCCSEL3_GPIO87_M 0xF0000000 // GPIO87 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL4 register +// +//***************************************************************************** +#define GPIO_GPCCSEL4_GPIO88_S 0 +#define GPIO_GPCCSEL4_GPIO88_M 0xF // GPIO88 Master CPU Select +#define GPIO_GPCCSEL4_GPIO89_S 4 +#define GPIO_GPCCSEL4_GPIO89_M 0xF0 // GPIO89 Master CPU Select +#define GPIO_GPCCSEL4_GPIO90_S 8 +#define GPIO_GPCCSEL4_GPIO90_M 0xF00 // GPIO90 Master CPU Select +#define GPIO_GPCCSEL4_GPIO91_S 12 +#define GPIO_GPCCSEL4_GPIO91_M 0xF000 // GPIO91 Master CPU Select +#define GPIO_GPCCSEL4_GPIO92_S 16 +#define GPIO_GPCCSEL4_GPIO92_M 0xF0000 // GPIO92 Master CPU Select +#define GPIO_GPCCSEL4_GPIO93_S 20 +#define GPIO_GPCCSEL4_GPIO93_M 0xF00000 // GPIO93 Master CPU Select +#define GPIO_GPCCSEL4_GPIO94_S 24 +#define GPIO_GPCCSEL4_GPIO94_M 0xF000000 // GPIO94 Master CPU Select +#define GPIO_GPCCSEL4_GPIO95_S 28 +#define GPIO_GPCCSEL4_GPIO95_M 0xF0000000 // GPIO95 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCLOCK register +// +//***************************************************************************** +#define GPIO_GPCLOCK_GPIO64 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO65 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO66 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO67 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO68 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO69 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO70 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO71 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO72 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO73 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO74 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO75 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO76 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO77 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO78 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO79 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO80 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO81 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO82 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO83 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO84 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO85 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO86 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO87 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO88 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO89 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO90 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO91 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO92 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO93 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO94 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO95 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCR register +// +//***************************************************************************** +#define GPIO_GPCCR_GPIO64 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO65 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO66 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO67 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO68 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO69 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO70 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO71 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO72 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO73 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO74 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO75 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO76 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO77 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO78 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO79 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO80 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO81 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO82 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO83 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO84 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO85 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO86 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO87 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO88 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO89 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO90 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO91 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO92 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO93 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO94 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO95 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCTRL register +// +//***************************************************************************** +#define GPIO_GPDCTRL_QUALPRD0_S 0 +#define GPIO_GPDCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO96 to GPIO103 +#define GPIO_GPDCTRL_QUALPRD1_S 8 +#define GPIO_GPDCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO104 to GPIO111 +#define GPIO_GPDCTRL_QUALPRD2_S 16 +#define GPIO_GPDCTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO112 to GPIO119 +#define GPIO_GPDCTRL_QUALPRD3_S 24 +#define GPIO_GPDCTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO120 to GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDQSEL1 register +// +//***************************************************************************** +#define GPIO_GPDQSEL1_GPIO96_S 0 +#define GPIO_GPDQSEL1_GPIO96_M 0x3 // Select input qualification type + // for GPIO96 +#define GPIO_GPDQSEL1_GPIO97_S 2 +#define GPIO_GPDQSEL1_GPIO97_M 0xC // Select input qualification type + // for GPIO97 +#define GPIO_GPDQSEL1_GPIO98_S 4 +#define GPIO_GPDQSEL1_GPIO98_M 0x30 // Select input qualification type + // for GPIO98 +#define GPIO_GPDQSEL1_GPIO99_S 6 +#define GPIO_GPDQSEL1_GPIO99_M 0xC0 // Select input qualification type + // for GPIO99 +#define GPIO_GPDQSEL1_GPIO100_S 8 +#define GPIO_GPDQSEL1_GPIO100_M 0x300 // Select input qualification type + // for GPIO100 +#define GPIO_GPDQSEL1_GPIO101_S 10 +#define GPIO_GPDQSEL1_GPIO101_M 0xC00 // Select input qualification type + // for GPIO101 +#define GPIO_GPDQSEL1_GPIO102_S 12 +#define GPIO_GPDQSEL1_GPIO102_M 0x3000 // Select input qualification type + // for GPIO102 +#define GPIO_GPDQSEL1_GPIO103_S 14 +#define GPIO_GPDQSEL1_GPIO103_M 0xC000 // Select input qualification type + // for GPIO103 +#define GPIO_GPDQSEL1_GPIO104_S 16 +#define GPIO_GPDQSEL1_GPIO104_M 0x30000 // Select input qualification type + // for GPIO104 +#define GPIO_GPDQSEL1_GPIO105_S 18 +#define GPIO_GPDQSEL1_GPIO105_M 0xC0000 // Select input qualification type + // for GPIO105 +#define GPIO_GPDQSEL1_GPIO106_S 20 +#define GPIO_GPDQSEL1_GPIO106_M 0x300000 // Select input qualification type + // for GPIO106 +#define GPIO_GPDQSEL1_GPIO107_S 22 +#define GPIO_GPDQSEL1_GPIO107_M 0xC00000 // Select input qualification type + // for GPIO107 +#define GPIO_GPDQSEL1_GPIO108_S 24 +#define GPIO_GPDQSEL1_GPIO108_M 0x3000000 // Select input qualification type + // for GPIO108 +#define GPIO_GPDQSEL1_GPIO109_S 26 +#define GPIO_GPDQSEL1_GPIO109_M 0xC000000 // Select input qualification type + // for GPIO109 +#define GPIO_GPDQSEL1_GPIO110_S 28 +#define GPIO_GPDQSEL1_GPIO110_M 0x30000000 // Select input qualification type + // for GPIO110 +#define GPIO_GPDQSEL1_GPIO111_S 30 +#define GPIO_GPDQSEL1_GPIO111_M 0xC0000000 // Select input qualification type + // for GPIO111 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDQSEL2 register +// +//***************************************************************************** +#define GPIO_GPDQSEL2_GPIO112_S 0 +#define GPIO_GPDQSEL2_GPIO112_M 0x3 // Select input qualification type + // for GPIO112 +#define GPIO_GPDQSEL2_GPIO113_S 2 +#define GPIO_GPDQSEL2_GPIO113_M 0xC // Select input qualification type + // for GPIO113 +#define GPIO_GPDQSEL2_GPIO114_S 4 +#define GPIO_GPDQSEL2_GPIO114_M 0x30 // Select input qualification type + // for GPIO114 +#define GPIO_GPDQSEL2_GPIO115_S 6 +#define GPIO_GPDQSEL2_GPIO115_M 0xC0 // Select input qualification type + // for GPIO115 +#define GPIO_GPDQSEL2_GPIO116_S 8 +#define GPIO_GPDQSEL2_GPIO116_M 0x300 // Select input qualification type + // for GPIO116 +#define GPIO_GPDQSEL2_GPIO117_S 10 +#define GPIO_GPDQSEL2_GPIO117_M 0xC00 // Select input qualification type + // for GPIO117 +#define GPIO_GPDQSEL2_GPIO118_S 12 +#define GPIO_GPDQSEL2_GPIO118_M 0x3000 // Select input qualification type + // for GPIO118 +#define GPIO_GPDQSEL2_GPIO119_S 14 +#define GPIO_GPDQSEL2_GPIO119_M 0xC000 // Select input qualification type + // for GPIO119 +#define GPIO_GPDQSEL2_GPIO120_S 16 +#define GPIO_GPDQSEL2_GPIO120_M 0x30000 // Select input qualification type + // for GPIO120 +#define GPIO_GPDQSEL2_GPIO121_S 18 +#define GPIO_GPDQSEL2_GPIO121_M 0xC0000 // Select input qualification type + // for GPIO121 +#define GPIO_GPDQSEL2_GPIO122_S 20 +#define GPIO_GPDQSEL2_GPIO122_M 0x300000 // Select input qualification type + // for GPIO122 +#define GPIO_GPDQSEL2_GPIO123_S 22 +#define GPIO_GPDQSEL2_GPIO123_M 0xC00000 // Select input qualification type + // for GPIO123 +#define GPIO_GPDQSEL2_GPIO124_S 24 +#define GPIO_GPDQSEL2_GPIO124_M 0x3000000 // Select input qualification type + // for GPIO124 +#define GPIO_GPDQSEL2_GPIO125_S 26 +#define GPIO_GPDQSEL2_GPIO125_M 0xC000000 // Select input qualification type + // for GPIO125 +#define GPIO_GPDQSEL2_GPIO126_S 28 +#define GPIO_GPDQSEL2_GPIO126_M 0x30000000 // Select input qualification type + // for GPIO126 +#define GPIO_GPDQSEL2_GPIO127_S 30 +#define GPIO_GPDQSEL2_GPIO127_M 0xC0000000 // Select input qualification type + // for GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDMUX1 register +// +//***************************************************************************** +#define GPIO_GPDMUX1_GPIO96_S 0 +#define GPIO_GPDMUX1_GPIO96_M 0x3 // Defines pin-muxing selection + // for GPIO96 +#define GPIO_GPDMUX1_GPIO97_S 2 +#define GPIO_GPDMUX1_GPIO97_M 0xC // Defines pin-muxing selection + // for GPIO97 +#define GPIO_GPDMUX1_GPIO98_S 4 +#define GPIO_GPDMUX1_GPIO98_M 0x30 // Defines pin-muxing selection + // for GPIO98 +#define GPIO_GPDMUX1_GPIO99_S 6 +#define GPIO_GPDMUX1_GPIO99_M 0xC0 // Defines pin-muxing selection + // for GPIO99 +#define GPIO_GPDMUX1_GPIO100_S 8 +#define GPIO_GPDMUX1_GPIO100_M 0x300 // Defines pin-muxing selection + // for GPIO100 +#define GPIO_GPDMUX1_GPIO101_S 10 +#define GPIO_GPDMUX1_GPIO101_M 0xC00 // Defines pin-muxing selection + // for GPIO101 +#define GPIO_GPDMUX1_GPIO102_S 12 +#define GPIO_GPDMUX1_GPIO102_M 0x3000 // Defines pin-muxing selection + // for GPIO102 +#define GPIO_GPDMUX1_GPIO103_S 14 +#define GPIO_GPDMUX1_GPIO103_M 0xC000 // Defines pin-muxing selection + // for GPIO103 +#define GPIO_GPDMUX1_GPIO104_S 16 +#define GPIO_GPDMUX1_GPIO104_M 0x30000 // Defines pin-muxing selection + // for GPIO104 +#define GPIO_GPDMUX1_GPIO105_S 18 +#define GPIO_GPDMUX1_GPIO105_M 0xC0000 // Defines pin-muxing selection + // for GPIO105 +#define GPIO_GPDMUX1_GPIO106_S 20 +#define GPIO_GPDMUX1_GPIO106_M 0x300000 // Defines pin-muxing selection + // for GPIO106 +#define GPIO_GPDMUX1_GPIO107_S 22 +#define GPIO_GPDMUX1_GPIO107_M 0xC00000 // Defines pin-muxing selection + // for GPIO107 +#define GPIO_GPDMUX1_GPIO108_S 24 +#define GPIO_GPDMUX1_GPIO108_M 0x3000000 // Defines pin-muxing selection + // for GPIO108 +#define GPIO_GPDMUX1_GPIO109_S 26 +#define GPIO_GPDMUX1_GPIO109_M 0xC000000 // Defines pin-muxing selection + // for GPIO109 +#define GPIO_GPDMUX1_GPIO110_S 28 +#define GPIO_GPDMUX1_GPIO110_M 0x30000000 // Defines pin-muxing selection + // for GPIO110 +#define GPIO_GPDMUX1_GPIO111_S 30 +#define GPIO_GPDMUX1_GPIO111_M 0xC0000000 // Defines pin-muxing selection + // for GPIO111 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDMUX2 register +// +//***************************************************************************** +#define GPIO_GPDMUX2_GPIO112_S 0 +#define GPIO_GPDMUX2_GPIO112_M 0x3 // Defines pin-muxing selection + // for GPIO112 +#define GPIO_GPDMUX2_GPIO113_S 2 +#define GPIO_GPDMUX2_GPIO113_M 0xC // Defines pin-muxing selection + // for GPIO113 +#define GPIO_GPDMUX2_GPIO114_S 4 +#define GPIO_GPDMUX2_GPIO114_M 0x30 // Defines pin-muxing selection + // for GPIO114 +#define GPIO_GPDMUX2_GPIO115_S 6 +#define GPIO_GPDMUX2_GPIO115_M 0xC0 // Defines pin-muxing selection + // for GPIO115 +#define GPIO_GPDMUX2_GPIO116_S 8 +#define GPIO_GPDMUX2_GPIO116_M 0x300 // Defines pin-muxing selection + // for GPIO116 +#define GPIO_GPDMUX2_GPIO117_S 10 +#define GPIO_GPDMUX2_GPIO117_M 0xC00 // Defines pin-muxing selection + // for GPIO117 +#define GPIO_GPDMUX2_GPIO118_S 12 +#define GPIO_GPDMUX2_GPIO118_M 0x3000 // Defines pin-muxing selection + // for GPIO118 +#define GPIO_GPDMUX2_GPIO119_S 14 +#define GPIO_GPDMUX2_GPIO119_M 0xC000 // Defines pin-muxing selection + // for GPIO119 +#define GPIO_GPDMUX2_GPIO120_S 16 +#define GPIO_GPDMUX2_GPIO120_M 0x30000 // Defines pin-muxing selection + // for GPIO120 +#define GPIO_GPDMUX2_GPIO121_S 18 +#define GPIO_GPDMUX2_GPIO121_M 0xC0000 // Defines pin-muxing selection + // for GPIO121 +#define GPIO_GPDMUX2_GPIO122_S 20 +#define GPIO_GPDMUX2_GPIO122_M 0x300000 // Defines pin-muxing selection + // for GPIO122 +#define GPIO_GPDMUX2_GPIO123_S 22 +#define GPIO_GPDMUX2_GPIO123_M 0xC00000 // Defines pin-muxing selection + // for GPIO123 +#define GPIO_GPDMUX2_GPIO124_S 24 +#define GPIO_GPDMUX2_GPIO124_M 0x3000000 // Defines pin-muxing selection + // for GPIO124 +#define GPIO_GPDMUX2_GPIO125_S 26 +#define GPIO_GPDMUX2_GPIO125_M 0xC000000 // Defines pin-muxing selection + // for GPIO125 +#define GPIO_GPDMUX2_GPIO126_S 28 +#define GPIO_GPDMUX2_GPIO126_M 0x30000000 // Defines pin-muxing selection + // for GPIO126 +#define GPIO_GPDMUX2_GPIO127_S 30 +#define GPIO_GPDMUX2_GPIO127_M 0xC0000000 // Defines pin-muxing selection + // for GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDDIR register +// +//***************************************************************************** +#define GPIO_GPDDIR_GPIO96 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO97 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO98 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO99 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO100 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO101 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO102 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO103 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO104 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO105 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO106 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO107 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO108 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO109 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO110 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO111 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO112 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO113 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO114 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO115 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO116 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO117 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO118 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO119 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO120 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO121 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO122 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO123 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO124 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO125 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO126 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO127 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDPUD register +// +//***************************************************************************** +#define GPIO_GPDPUD_GPIO96 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO97 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO98 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO99 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO100 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO101 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO102 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO103 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO104 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO105 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO106 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO107 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO108 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO109 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO110 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO111 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO112 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO113 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO114 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO115 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO116 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO117 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO118 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO119 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO120 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO121 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO122 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO123 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO124 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO125 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO126 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO127 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDINV register +// +//***************************************************************************** +#define GPIO_GPDINV_GPIO96 0x1 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO97 0x2 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO98 0x4 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO99 0x8 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO100 0x10 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO101 0x20 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO102 0x40 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO103 0x80 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO104 0x100 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO105 0x200 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO106 0x400 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO107 0x800 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO108 0x1000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO109 0x2000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO110 0x4000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO111 0x8000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO112 0x10000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO113 0x20000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO114 0x40000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO115 0x80000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO116 0x100000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO117 0x200000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO118 0x400000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO119 0x800000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO120 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO121 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO122 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO123 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO124 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO125 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO126 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO127 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDODR register +// +//***************************************************************************** +#define GPIO_GPDODR_GPIO96 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO97 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO98 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO99 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO100 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO101 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO102 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO103 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO104 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO105 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO106 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO107 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO108 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO109 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO110 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO111 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO112 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO113 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO114 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO115 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO116 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO117 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO118 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO119 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO120 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO121 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO122 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO123 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO124 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO125 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO126 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO127 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDGMUX1 register +// +//***************************************************************************** +#define GPIO_GPDGMUX1_GPIO96_S 0 +#define GPIO_GPDGMUX1_GPIO96_M 0x3 // Defines pin-muxing selection + // for GPIO96 +#define GPIO_GPDGMUX1_GPIO97_S 2 +#define GPIO_GPDGMUX1_GPIO97_M 0xC // Defines pin-muxing selection + // for GPIO97 +#define GPIO_GPDGMUX1_GPIO98_S 4 +#define GPIO_GPDGMUX1_GPIO98_M 0x30 // Defines pin-muxing selection + // for GPIO98 +#define GPIO_GPDGMUX1_GPIO99_S 6 +#define GPIO_GPDGMUX1_GPIO99_M 0xC0 // Defines pin-muxing selection + // for GPIO99 +#define GPIO_GPDGMUX1_GPIO100_S 8 +#define GPIO_GPDGMUX1_GPIO100_M 0x300 // Defines pin-muxing selection + // for GPIO100 +#define GPIO_GPDGMUX1_GPIO101_S 10 +#define GPIO_GPDGMUX1_GPIO101_M 0xC00 // Defines pin-muxing selection + // for GPIO101 +#define GPIO_GPDGMUX1_GPIO102_S 12 +#define GPIO_GPDGMUX1_GPIO102_M 0x3000 // Defines pin-muxing selection + // for GPIO102 +#define GPIO_GPDGMUX1_GPIO103_S 14 +#define GPIO_GPDGMUX1_GPIO103_M 0xC000 // Defines pin-muxing selection + // for GPIO103 +#define GPIO_GPDGMUX1_GPIO104_S 16 +#define GPIO_GPDGMUX1_GPIO104_M 0x30000 // Defines pin-muxing selection + // for GPIO104 +#define GPIO_GPDGMUX1_GPIO105_S 18 +#define GPIO_GPDGMUX1_GPIO105_M 0xC0000 // Defines pin-muxing selection + // for GPIO105 +#define GPIO_GPDGMUX1_GPIO106_S 20 +#define GPIO_GPDGMUX1_GPIO106_M 0x300000 // Defines pin-muxing selection + // for GPIO106 +#define GPIO_GPDGMUX1_GPIO107_S 22 +#define GPIO_GPDGMUX1_GPIO107_M 0xC00000 // Defines pin-muxing selection + // for GPIO107 +#define GPIO_GPDGMUX1_GPIO108_S 24 +#define GPIO_GPDGMUX1_GPIO108_M 0x3000000 // Defines pin-muxing selection + // for GPIO108 +#define GPIO_GPDGMUX1_GPIO109_S 26 +#define GPIO_GPDGMUX1_GPIO109_M 0xC000000 // Defines pin-muxing selection + // for GPIO109 +#define GPIO_GPDGMUX1_GPIO110_S 28 +#define GPIO_GPDGMUX1_GPIO110_M 0x30000000 // Defines pin-muxing selection + // for GPIO110 +#define GPIO_GPDGMUX1_GPIO111_S 30 +#define GPIO_GPDGMUX1_GPIO111_M 0xC0000000 // Defines pin-muxing selection + // for GPIO111 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDGMUX2 register +// +//***************************************************************************** +#define GPIO_GPDGMUX2_GPIO112_S 0 +#define GPIO_GPDGMUX2_GPIO112_M 0x3 // Defines pin-muxing selection + // for GPIO112 +#define GPIO_GPDGMUX2_GPIO113_S 2 +#define GPIO_GPDGMUX2_GPIO113_M 0xC // Defines pin-muxing selection + // for GPIO113 +#define GPIO_GPDGMUX2_GPIO114_S 4 +#define GPIO_GPDGMUX2_GPIO114_M 0x30 // Defines pin-muxing selection + // for GPIO114 +#define GPIO_GPDGMUX2_GPIO115_S 6 +#define GPIO_GPDGMUX2_GPIO115_M 0xC0 // Defines pin-muxing selection + // for GPIO115 +#define GPIO_GPDGMUX2_GPIO116_S 8 +#define GPIO_GPDGMUX2_GPIO116_M 0x300 // Defines pin-muxing selection + // for GPIO116 +#define GPIO_GPDGMUX2_GPIO117_S 10 +#define GPIO_GPDGMUX2_GPIO117_M 0xC00 // Defines pin-muxing selection + // for GPIO117 +#define GPIO_GPDGMUX2_GPIO118_S 12 +#define GPIO_GPDGMUX2_GPIO118_M 0x3000 // Defines pin-muxing selection + // for GPIO118 +#define GPIO_GPDGMUX2_GPIO119_S 14 +#define GPIO_GPDGMUX2_GPIO119_M 0xC000 // Defines pin-muxing selection + // for GPIO119 +#define GPIO_GPDGMUX2_GPIO120_S 16 +#define GPIO_GPDGMUX2_GPIO120_M 0x30000 // Defines pin-muxing selection + // for GPIO120 +#define GPIO_GPDGMUX2_GPIO121_S 18 +#define GPIO_GPDGMUX2_GPIO121_M 0xC0000 // Defines pin-muxing selection + // for GPIO121 +#define GPIO_GPDGMUX2_GPIO122_S 20 +#define GPIO_GPDGMUX2_GPIO122_M 0x300000 // Defines pin-muxing selection + // for GPIO122 +#define GPIO_GPDGMUX2_GPIO123_S 22 +#define GPIO_GPDGMUX2_GPIO123_M 0xC00000 // Defines pin-muxing selection + // for GPIO123 +#define GPIO_GPDGMUX2_GPIO124_S 24 +#define GPIO_GPDGMUX2_GPIO124_M 0x3000000 // Defines pin-muxing selection + // for GPIO124 +#define GPIO_GPDGMUX2_GPIO125_S 26 +#define GPIO_GPDGMUX2_GPIO125_M 0xC000000 // Defines pin-muxing selection + // for GPIO125 +#define GPIO_GPDGMUX2_GPIO126_S 28 +#define GPIO_GPDGMUX2_GPIO126_M 0x30000000 // Defines pin-muxing selection + // for GPIO126 +#define GPIO_GPDGMUX2_GPIO127_S 30 +#define GPIO_GPDGMUX2_GPIO127_M 0xC0000000 // Defines pin-muxing selection + // for GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL1 register +// +//***************************************************************************** +#define GPIO_GPDCSEL1_GPIO96_S 0 +#define GPIO_GPDCSEL1_GPIO96_M 0xF // GPIO96 Master CPU Select +#define GPIO_GPDCSEL1_GPIO97_S 4 +#define GPIO_GPDCSEL1_GPIO97_M 0xF0 // GPIO97 Master CPU Select +#define GPIO_GPDCSEL1_GPIO98_S 8 +#define GPIO_GPDCSEL1_GPIO98_M 0xF00 // GPIO98 Master CPU Select +#define GPIO_GPDCSEL1_GPIO99_S 12 +#define GPIO_GPDCSEL1_GPIO99_M 0xF000 // GPIO99 Master CPU Select +#define GPIO_GPDCSEL1_GPIO100_S 16 +#define GPIO_GPDCSEL1_GPIO100_M 0xF0000 // GPIO100 Master CPU Select +#define GPIO_GPDCSEL1_GPIO101_S 20 +#define GPIO_GPDCSEL1_GPIO101_M 0xF00000 // GPIO101 Master CPU Select +#define GPIO_GPDCSEL1_GPIO102_S 24 +#define GPIO_GPDCSEL1_GPIO102_M 0xF000000 // GPIO102 Master CPU Select +#define GPIO_GPDCSEL1_GPIO103_S 28 +#define GPIO_GPDCSEL1_GPIO103_M 0xF0000000 // GPIO103 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL2 register +// +//***************************************************************************** +#define GPIO_GPDCSEL2_GPIO104_S 0 +#define GPIO_GPDCSEL2_GPIO104_M 0xF // GPIO104 Master CPU Select +#define GPIO_GPDCSEL2_GPIO105_S 4 +#define GPIO_GPDCSEL2_GPIO105_M 0xF0 // GPIO105 Master CPU Select +#define GPIO_GPDCSEL2_GPIO106_S 8 +#define GPIO_GPDCSEL2_GPIO106_M 0xF00 // GPIO106 Master CPU Select +#define GPIO_GPDCSEL2_GPIO107_S 12 +#define GPIO_GPDCSEL2_GPIO107_M 0xF000 // GPIO107 Master CPU Select +#define GPIO_GPDCSEL2_GPIO108_S 16 +#define GPIO_GPDCSEL2_GPIO108_M 0xF0000 // GPIO108 Master CPU Select +#define GPIO_GPDCSEL2_GPIO109_S 20 +#define GPIO_GPDCSEL2_GPIO109_M 0xF00000 // GPIO109 Master CPU Select +#define GPIO_GPDCSEL2_GPIO110_S 24 +#define GPIO_GPDCSEL2_GPIO110_M 0xF000000 // GPIO110 Master CPU Select +#define GPIO_GPDCSEL2_GPIO111_S 28 +#define GPIO_GPDCSEL2_GPIO111_M 0xF0000000 // GPIO111 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL3 register +// +//***************************************************************************** +#define GPIO_GPDCSEL3_GPIO112_S 0 +#define GPIO_GPDCSEL3_GPIO112_M 0xF // GPIO112 Master CPU Select +#define GPIO_GPDCSEL3_GPIO113_S 4 +#define GPIO_GPDCSEL3_GPIO113_M 0xF0 // GPIO113 Master CPU Select +#define GPIO_GPDCSEL3_GPIO114_S 8 +#define GPIO_GPDCSEL3_GPIO114_M 0xF00 // GPIO114 Master CPU Select +#define GPIO_GPDCSEL3_GPIO115_S 12 +#define GPIO_GPDCSEL3_GPIO115_M 0xF000 // GPIO115 Master CPU Select +#define GPIO_GPDCSEL3_GPIO116_S 16 +#define GPIO_GPDCSEL3_GPIO116_M 0xF0000 // GPIO116 Master CPU Select +#define GPIO_GPDCSEL3_GPIO117_S 20 +#define GPIO_GPDCSEL3_GPIO117_M 0xF00000 // GPIO117 Master CPU Select +#define GPIO_GPDCSEL3_GPIO118_S 24 +#define GPIO_GPDCSEL3_GPIO118_M 0xF000000 // GPIO118 Master CPU Select +#define GPIO_GPDCSEL3_GPIO119_S 28 +#define GPIO_GPDCSEL3_GPIO119_M 0xF0000000 // GPIO119 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL4 register +// +//***************************************************************************** +#define GPIO_GPDCSEL4_GPIO120_S 0 +#define GPIO_GPDCSEL4_GPIO120_M 0xF // GPIO120 Master CPU Select +#define GPIO_GPDCSEL4_GPIO121_S 4 +#define GPIO_GPDCSEL4_GPIO121_M 0xF0 // GPIO121 Master CPU Select +#define GPIO_GPDCSEL4_GPIO122_S 8 +#define GPIO_GPDCSEL4_GPIO122_M 0xF00 // GPIO122 Master CPU Select +#define GPIO_GPDCSEL4_GPIO123_S 12 +#define GPIO_GPDCSEL4_GPIO123_M 0xF000 // GPIO123 Master CPU Select +#define GPIO_GPDCSEL4_GPIO124_S 16 +#define GPIO_GPDCSEL4_GPIO124_M 0xF0000 // GPIO124 Master CPU Select +#define GPIO_GPDCSEL4_GPIO125_S 20 +#define GPIO_GPDCSEL4_GPIO125_M 0xF00000 // GPIO125 Master CPU Select +#define GPIO_GPDCSEL4_GPIO126_S 24 +#define GPIO_GPDCSEL4_GPIO126_M 0xF000000 // GPIO126 Master CPU Select +#define GPIO_GPDCSEL4_GPIO127_S 28 +#define GPIO_GPDCSEL4_GPIO127_M 0xF0000000 // GPIO127 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDLOCK register +// +//***************************************************************************** +#define GPIO_GPDLOCK_GPIO96 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO97 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO98 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO99 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO100 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO101 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO102 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO103 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO104 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO105 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO106 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO107 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO108 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO109 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO110 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO111 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO112 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO113 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO114 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO115 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO116 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO117 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO118 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO119 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO120 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO121 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO122 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO123 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO124 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO125 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO126 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO127 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCR register +// +//***************************************************************************** +#define GPIO_GPDCR_GPIO96 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO97 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO98 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO99 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO100 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO101 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO102 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO103 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO104 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO105 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO106 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO107 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO108 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO109 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO110 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO111 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO112 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO113 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO114 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO115 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO116 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO117 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO118 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO119 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO120 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO121 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO122 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO123 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO124 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO125 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO126 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO127 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECTRL register +// +//***************************************************************************** +#define GPIO_GPECTRL_QUALPRD0_S 0 +#define GPIO_GPECTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO128 to GPIO135 +#define GPIO_GPECTRL_QUALPRD1_S 8 +#define GPIO_GPECTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO136 to GPIO143 +#define GPIO_GPECTRL_QUALPRD2_S 16 +#define GPIO_GPECTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO144 to GPIO151 +#define GPIO_GPECTRL_QUALPRD3_S 24 +#define GPIO_GPECTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO152 to GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEQSEL1 register +// +//***************************************************************************** +#define GPIO_GPEQSEL1_GPIO128_S 0 +#define GPIO_GPEQSEL1_GPIO128_M 0x3 // Select input qualification type + // for GPIO128 +#define GPIO_GPEQSEL1_GPIO129_S 2 +#define GPIO_GPEQSEL1_GPIO129_M 0xC // Select input qualification type + // for GPIO129 +#define GPIO_GPEQSEL1_GPIO130_S 4 +#define GPIO_GPEQSEL1_GPIO130_M 0x30 // Select input qualification type + // for GPIO130 +#define GPIO_GPEQSEL1_GPIO131_S 6 +#define GPIO_GPEQSEL1_GPIO131_M 0xC0 // Select input qualification type + // for GPIO131 +#define GPIO_GPEQSEL1_GPIO132_S 8 +#define GPIO_GPEQSEL1_GPIO132_M 0x300 // Select input qualification type + // for GPIO132 +#define GPIO_GPEQSEL1_GPIO133_S 10 +#define GPIO_GPEQSEL1_GPIO133_M 0xC00 // Select input qualification type + // for GPIO133 +#define GPIO_GPEQSEL1_GPIO134_S 12 +#define GPIO_GPEQSEL1_GPIO134_M 0x3000 // Select input qualification type + // for GPIO134 +#define GPIO_GPEQSEL1_GPIO135_S 14 +#define GPIO_GPEQSEL1_GPIO135_M 0xC000 // Select input qualification type + // for GPIO135 +#define GPIO_GPEQSEL1_GPIO136_S 16 +#define GPIO_GPEQSEL1_GPIO136_M 0x30000 // Select input qualification type + // for GPIO136 +#define GPIO_GPEQSEL1_GPIO137_S 18 +#define GPIO_GPEQSEL1_GPIO137_M 0xC0000 // Select input qualification type + // for GPIO137 +#define GPIO_GPEQSEL1_GPIO138_S 20 +#define GPIO_GPEQSEL1_GPIO138_M 0x300000 // Select input qualification type + // for GPIO138 +#define GPIO_GPEQSEL1_GPIO139_S 22 +#define GPIO_GPEQSEL1_GPIO139_M 0xC00000 // Select input qualification type + // for GPIO139 +#define GPIO_GPEQSEL1_GPIO140_S 24 +#define GPIO_GPEQSEL1_GPIO140_M 0x3000000 // Select input qualification type + // for GPIO140 +#define GPIO_GPEQSEL1_GPIO141_S 26 +#define GPIO_GPEQSEL1_GPIO141_M 0xC000000 // Select input qualification type + // for GPIO141 +#define GPIO_GPEQSEL1_GPIO142_S 28 +#define GPIO_GPEQSEL1_GPIO142_M 0x30000000 // Select input qualification type + // for GPIO142 +#define GPIO_GPEQSEL1_GPIO143_S 30 +#define GPIO_GPEQSEL1_GPIO143_M 0xC0000000 // Select input qualification type + // for GPIO143 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEQSEL2 register +// +//***************************************************************************** +#define GPIO_GPEQSEL2_GPIO144_S 0 +#define GPIO_GPEQSEL2_GPIO144_M 0x3 // Select input qualification type + // for GPIO144 +#define GPIO_GPEQSEL2_GPIO145_S 2 +#define GPIO_GPEQSEL2_GPIO145_M 0xC // Select input qualification type + // for GPIO145 +#define GPIO_GPEQSEL2_GPIO146_S 4 +#define GPIO_GPEQSEL2_GPIO146_M 0x30 // Select input qualification type + // for GPIO146 +#define GPIO_GPEQSEL2_GPIO147_S 6 +#define GPIO_GPEQSEL2_GPIO147_M 0xC0 // Select input qualification type + // for GPIO147 +#define GPIO_GPEQSEL2_GPIO148_S 8 +#define GPIO_GPEQSEL2_GPIO148_M 0x300 // Select input qualification type + // for GPIO148 +#define GPIO_GPEQSEL2_GPIO149_S 10 +#define GPIO_GPEQSEL2_GPIO149_M 0xC00 // Select input qualification type + // for GPIO149 +#define GPIO_GPEQSEL2_GPIO150_S 12 +#define GPIO_GPEQSEL2_GPIO150_M 0x3000 // Select input qualification type + // for GPIO150 +#define GPIO_GPEQSEL2_GPIO151_S 14 +#define GPIO_GPEQSEL2_GPIO151_M 0xC000 // Select input qualification type + // for GPIO151 +#define GPIO_GPEQSEL2_GPIO152_S 16 +#define GPIO_GPEQSEL2_GPIO152_M 0x30000 // Select input qualification type + // for GPIO152 +#define GPIO_GPEQSEL2_GPIO153_S 18 +#define GPIO_GPEQSEL2_GPIO153_M 0xC0000 // Select input qualification type + // for GPIO153 +#define GPIO_GPEQSEL2_GPIO154_S 20 +#define GPIO_GPEQSEL2_GPIO154_M 0x300000 // Select input qualification type + // for GPIO154 +#define GPIO_GPEQSEL2_GPIO155_S 22 +#define GPIO_GPEQSEL2_GPIO155_M 0xC00000 // Select input qualification type + // for GPIO155 +#define GPIO_GPEQSEL2_GPIO156_S 24 +#define GPIO_GPEQSEL2_GPIO156_M 0x3000000 // Select input qualification type + // for GPIO156 +#define GPIO_GPEQSEL2_GPIO157_S 26 +#define GPIO_GPEQSEL2_GPIO157_M 0xC000000 // Select input qualification type + // for GPIO157 +#define GPIO_GPEQSEL2_GPIO158_S 28 +#define GPIO_GPEQSEL2_GPIO158_M 0x30000000 // Select input qualification type + // for GPIO158 +#define GPIO_GPEQSEL2_GPIO159_S 30 +#define GPIO_GPEQSEL2_GPIO159_M 0xC0000000 // Select input qualification type + // for GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEMUX1 register +// +//***************************************************************************** +#define GPIO_GPEMUX1_GPIO128_S 0 +#define GPIO_GPEMUX1_GPIO128_M 0x3 // Defines pin-muxing selection + // for GPIO128 +#define GPIO_GPEMUX1_GPIO129_S 2 +#define GPIO_GPEMUX1_GPIO129_M 0xC // Defines pin-muxing selection + // for GPIO129 +#define GPIO_GPEMUX1_GPIO130_S 4 +#define GPIO_GPEMUX1_GPIO130_M 0x30 // Defines pin-muxing selection + // for GPIO130 +#define GPIO_GPEMUX1_GPIO131_S 6 +#define GPIO_GPEMUX1_GPIO131_M 0xC0 // Defines pin-muxing selection + // for GPIO131 +#define GPIO_GPEMUX1_GPIO132_S 8 +#define GPIO_GPEMUX1_GPIO132_M 0x300 // Defines pin-muxing selection + // for GPIO132 +#define GPIO_GPEMUX1_GPIO133_S 10 +#define GPIO_GPEMUX1_GPIO133_M 0xC00 // Defines pin-muxing selection + // for GPIO133 +#define GPIO_GPEMUX1_GPIO134_S 12 +#define GPIO_GPEMUX1_GPIO134_M 0x3000 // Defines pin-muxing selection + // for GPIO134 +#define GPIO_GPEMUX1_GPIO135_S 14 +#define GPIO_GPEMUX1_GPIO135_M 0xC000 // Defines pin-muxing selection + // for GPIO135 +#define GPIO_GPEMUX1_GPIO136_S 16 +#define GPIO_GPEMUX1_GPIO136_M 0x30000 // Defines pin-muxing selection + // for GPIO136 +#define GPIO_GPEMUX1_GPIO137_S 18 +#define GPIO_GPEMUX1_GPIO137_M 0xC0000 // Defines pin-muxing selection + // for GPIO137 +#define GPIO_GPEMUX1_GPIO138_S 20 +#define GPIO_GPEMUX1_GPIO138_M 0x300000 // Defines pin-muxing selection + // for GPIO138 +#define GPIO_GPEMUX1_GPIO139_S 22 +#define GPIO_GPEMUX1_GPIO139_M 0xC00000 // Defines pin-muxing selection + // for GPIO139 +#define GPIO_GPEMUX1_GPIO140_S 24 +#define GPIO_GPEMUX1_GPIO140_M 0x3000000 // Defines pin-muxing selection + // for GPIO140 +#define GPIO_GPEMUX1_GPIO141_S 26 +#define GPIO_GPEMUX1_GPIO141_M 0xC000000 // Defines pin-muxing selection + // for GPIO141 +#define GPIO_GPEMUX1_GPIO142_S 28 +#define GPIO_GPEMUX1_GPIO142_M 0x30000000 // Defines pin-muxing selection + // for GPIO142 +#define GPIO_GPEMUX1_GPIO143_S 30 +#define GPIO_GPEMUX1_GPIO143_M 0xC0000000 // Defines pin-muxing selection + // for GPIO143 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEMUX2 register +// +//***************************************************************************** +#define GPIO_GPEMUX2_GPIO144_S 0 +#define GPIO_GPEMUX2_GPIO144_M 0x3 // Defines pin-muxing selection + // for GPIO144 +#define GPIO_GPEMUX2_GPIO145_S 2 +#define GPIO_GPEMUX2_GPIO145_M 0xC // Defines pin-muxing selection + // for GPIO145 +#define GPIO_GPEMUX2_GPIO146_S 4 +#define GPIO_GPEMUX2_GPIO146_M 0x30 // Defines pin-muxing selection + // for GPIO146 +#define GPIO_GPEMUX2_GPIO147_S 6 +#define GPIO_GPEMUX2_GPIO147_M 0xC0 // Defines pin-muxing selection + // for GPIO147 +#define GPIO_GPEMUX2_GPIO148_S 8 +#define GPIO_GPEMUX2_GPIO148_M 0x300 // Defines pin-muxing selection + // for GPIO148 +#define GPIO_GPEMUX2_GPIO149_S 10 +#define GPIO_GPEMUX2_GPIO149_M 0xC00 // Defines pin-muxing selection + // for GPIO149 +#define GPIO_GPEMUX2_GPIO150_S 12 +#define GPIO_GPEMUX2_GPIO150_M 0x3000 // Defines pin-muxing selection + // for GPIO150 +#define GPIO_GPEMUX2_GPIO151_S 14 +#define GPIO_GPEMUX2_GPIO151_M 0xC000 // Defines pin-muxing selection + // for GPIO151 +#define GPIO_GPEMUX2_GPIO152_S 16 +#define GPIO_GPEMUX2_GPIO152_M 0x30000 // Defines pin-muxing selection + // for GPIO152 +#define GPIO_GPEMUX2_GPIO153_S 18 +#define GPIO_GPEMUX2_GPIO153_M 0xC0000 // Defines pin-muxing selection + // for GPIO153 +#define GPIO_GPEMUX2_GPIO154_S 20 +#define GPIO_GPEMUX2_GPIO154_M 0x300000 // Defines pin-muxing selection + // for GPIO154 +#define GPIO_GPEMUX2_GPIO155_S 22 +#define GPIO_GPEMUX2_GPIO155_M 0xC00000 // Defines pin-muxing selection + // for GPIO155 +#define GPIO_GPEMUX2_GPIO156_S 24 +#define GPIO_GPEMUX2_GPIO156_M 0x3000000 // Defines pin-muxing selection + // for GPIO156 +#define GPIO_GPEMUX2_GPIO157_S 26 +#define GPIO_GPEMUX2_GPIO157_M 0xC000000 // Defines pin-muxing selection + // for GPIO157 +#define GPIO_GPEMUX2_GPIO158_S 28 +#define GPIO_GPEMUX2_GPIO158_M 0x30000000 // Defines pin-muxing selection + // for GPIO158 +#define GPIO_GPEMUX2_GPIO159_S 30 +#define GPIO_GPEMUX2_GPIO159_M 0xC0000000 // Defines pin-muxing selection + // for GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEDIR register +// +//***************************************************************************** +#define GPIO_GPEDIR_GPIO128 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO129 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO130 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO131 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO132 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO133 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO134 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO135 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO136 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO137 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO138 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO139 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO140 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO141 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO142 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO143 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO144 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO145 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO146 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO147 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO148 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO149 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO150 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO151 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO152 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO153 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO154 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO155 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO156 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO157 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO158 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO159 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEPUD register +// +//***************************************************************************** +#define GPIO_GPEPUD_GPIO128 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO129 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO130 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO131 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO132 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO133 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO134 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO135 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO136 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO137 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO138 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO139 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO140 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO141 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO142 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO143 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO144 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO145 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO146 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO147 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO148 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO149 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO150 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO151 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO152 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO153 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO154 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO155 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO156 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO157 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO158 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO159 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEINV register +// +//***************************************************************************** +#define GPIO_GPEINV_GPIO128 0x1 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO129 0x2 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO130 0x4 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO131 0x8 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO132 0x10 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO133 0x20 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO134 0x40 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO135 0x80 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO136 0x100 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO137 0x200 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO138 0x400 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO139 0x800 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO140 0x1000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO141 0x2000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO142 0x4000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO143 0x8000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO144 0x10000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO145 0x20000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO146 0x40000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO147 0x80000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO148 0x100000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO149 0x200000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO150 0x400000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO151 0x800000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO152 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO153 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO154 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO155 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO156 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO157 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO158 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO159 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEODR register +// +//***************************************************************************** +#define GPIO_GPEODR_GPIO128 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO129 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO130 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO131 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO132 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO133 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO134 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO135 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO136 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO137 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO138 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO139 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO140 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO141 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO142 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO143 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO144 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO145 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO146 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO147 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO148 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO149 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO150 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO151 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO152 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO153 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO154 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO155 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO156 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO157 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO158 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO159 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEGMUX1 register +// +//***************************************************************************** +#define GPIO_GPEGMUX1_GPIO128_S 0 +#define GPIO_GPEGMUX1_GPIO128_M 0x3 // Defines pin-muxing selection + // for GPIO128 +#define GPIO_GPEGMUX1_GPIO129_S 2 +#define GPIO_GPEGMUX1_GPIO129_M 0xC // Defines pin-muxing selection + // for GPIO129 +#define GPIO_GPEGMUX1_GPIO130_S 4 +#define GPIO_GPEGMUX1_GPIO130_M 0x30 // Defines pin-muxing selection + // for GPIO130 +#define GPIO_GPEGMUX1_GPIO131_S 6 +#define GPIO_GPEGMUX1_GPIO131_M 0xC0 // Defines pin-muxing selection + // for GPIO131 +#define GPIO_GPEGMUX1_GPIO132_S 8 +#define GPIO_GPEGMUX1_GPIO132_M 0x300 // Defines pin-muxing selection + // for GPIO132 +#define GPIO_GPEGMUX1_GPIO133_S 10 +#define GPIO_GPEGMUX1_GPIO133_M 0xC00 // Defines pin-muxing selection + // for GPIO133 +#define GPIO_GPEGMUX1_GPIO134_S 12 +#define GPIO_GPEGMUX1_GPIO134_M 0x3000 // Defines pin-muxing selection + // for GPIO134 +#define GPIO_GPEGMUX1_GPIO135_S 14 +#define GPIO_GPEGMUX1_GPIO135_M 0xC000 // Defines pin-muxing selection + // for GPIO135 +#define GPIO_GPEGMUX1_GPIO136_S 16 +#define GPIO_GPEGMUX1_GPIO136_M 0x30000 // Defines pin-muxing selection + // for GPIO136 +#define GPIO_GPEGMUX1_GPIO137_S 18 +#define GPIO_GPEGMUX1_GPIO137_M 0xC0000 // Defines pin-muxing selection + // for GPIO137 +#define GPIO_GPEGMUX1_GPIO138_S 20 +#define GPIO_GPEGMUX1_GPIO138_M 0x300000 // Defines pin-muxing selection + // for GPIO138 +#define GPIO_GPEGMUX1_GPIO139_S 22 +#define GPIO_GPEGMUX1_GPIO139_M 0xC00000 // Defines pin-muxing selection + // for GPIO139 +#define GPIO_GPEGMUX1_GPIO140_S 24 +#define GPIO_GPEGMUX1_GPIO140_M 0x3000000 // Defines pin-muxing selection + // for GPIO140 +#define GPIO_GPEGMUX1_GPIO141_S 26 +#define GPIO_GPEGMUX1_GPIO141_M 0xC000000 // Defines pin-muxing selection + // for GPIO141 +#define GPIO_GPEGMUX1_GPIO142_S 28 +#define GPIO_GPEGMUX1_GPIO142_M 0x30000000 // Defines pin-muxing selection + // for GPIO142 +#define GPIO_GPEGMUX1_GPIO143_S 30 +#define GPIO_GPEGMUX1_GPIO143_M 0xC0000000 // Defines pin-muxing selection + // for GPIO143 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEGMUX2 register +// +//***************************************************************************** +#define GPIO_GPEGMUX2_GPIO144_S 0 +#define GPIO_GPEGMUX2_GPIO144_M 0x3 // Defines pin-muxing selection + // for GPIO144 +#define GPIO_GPEGMUX2_GPIO145_S 2 +#define GPIO_GPEGMUX2_GPIO145_M 0xC // Defines pin-muxing selection + // for GPIO145 +#define GPIO_GPEGMUX2_GPIO146_S 4 +#define GPIO_GPEGMUX2_GPIO146_M 0x30 // Defines pin-muxing selection + // for GPIO146 +#define GPIO_GPEGMUX2_GPIO147_S 6 +#define GPIO_GPEGMUX2_GPIO147_M 0xC0 // Defines pin-muxing selection + // for GPIO147 +#define GPIO_GPEGMUX2_GPIO148_S 8 +#define GPIO_GPEGMUX2_GPIO148_M 0x300 // Defines pin-muxing selection + // for GPIO148 +#define GPIO_GPEGMUX2_GPIO149_S 10 +#define GPIO_GPEGMUX2_GPIO149_M 0xC00 // Defines pin-muxing selection + // for GPIO149 +#define GPIO_GPEGMUX2_GPIO150_S 12 +#define GPIO_GPEGMUX2_GPIO150_M 0x3000 // Defines pin-muxing selection + // for GPIO150 +#define GPIO_GPEGMUX2_GPIO151_S 14 +#define GPIO_GPEGMUX2_GPIO151_M 0xC000 // Defines pin-muxing selection + // for GPIO151 +#define GPIO_GPEGMUX2_GPIO152_S 16 +#define GPIO_GPEGMUX2_GPIO152_M 0x30000 // Defines pin-muxing selection + // for GPIO152 +#define GPIO_GPEGMUX2_GPIO153_S 18 +#define GPIO_GPEGMUX2_GPIO153_M 0xC0000 // Defines pin-muxing selection + // for GPIO153 +#define GPIO_GPEGMUX2_GPIO154_S 20 +#define GPIO_GPEGMUX2_GPIO154_M 0x300000 // Defines pin-muxing selection + // for GPIO154 +#define GPIO_GPEGMUX2_GPIO155_S 22 +#define GPIO_GPEGMUX2_GPIO155_M 0xC00000 // Defines pin-muxing selection + // for GPIO155 +#define GPIO_GPEGMUX2_GPIO156_S 24 +#define GPIO_GPEGMUX2_GPIO156_M 0x3000000 // Defines pin-muxing selection + // for GPIO156 +#define GPIO_GPEGMUX2_GPIO157_S 26 +#define GPIO_GPEGMUX2_GPIO157_M 0xC000000 // Defines pin-muxing selection + // for GPIO157 +#define GPIO_GPEGMUX2_GPIO158_S 28 +#define GPIO_GPEGMUX2_GPIO158_M 0x30000000 // Defines pin-muxing selection + // for GPIO158 +#define GPIO_GPEGMUX2_GPIO159_S 30 +#define GPIO_GPEGMUX2_GPIO159_M 0xC0000000 // Defines pin-muxing selection + // for GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL1 register +// +//***************************************************************************** +#define GPIO_GPECSEL1_GPIO128_S 0 +#define GPIO_GPECSEL1_GPIO128_M 0xF // GPIO128 Master CPU Select +#define GPIO_GPECSEL1_GPIO129_S 4 +#define GPIO_GPECSEL1_GPIO129_M 0xF0 // GPIO129 Master CPU Select +#define GPIO_GPECSEL1_GPIO130_S 8 +#define GPIO_GPECSEL1_GPIO130_M 0xF00 // GPIO130 Master CPU Select +#define GPIO_GPECSEL1_GPIO131_S 12 +#define GPIO_GPECSEL1_GPIO131_M 0xF000 // GPIO131 Master CPU Select +#define GPIO_GPECSEL1_GPIO132_S 16 +#define GPIO_GPECSEL1_GPIO132_M 0xF0000 // GPIO132 Master CPU Select +#define GPIO_GPECSEL1_GPIO133_S 20 +#define GPIO_GPECSEL1_GPIO133_M 0xF00000 // GPIO133 Master CPU Select +#define GPIO_GPECSEL1_GPIO134_S 24 +#define GPIO_GPECSEL1_GPIO134_M 0xF000000 // GPIO134 Master CPU Select +#define GPIO_GPECSEL1_GPIO135_S 28 +#define GPIO_GPECSEL1_GPIO135_M 0xF0000000 // GPIO135 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL2 register +// +//***************************************************************************** +#define GPIO_GPECSEL2_GPIO136_S 0 +#define GPIO_GPECSEL2_GPIO136_M 0xF // GPIO136 Master CPU Select +#define GPIO_GPECSEL2_GPIO137_S 4 +#define GPIO_GPECSEL2_GPIO137_M 0xF0 // GPIO137 Master CPU Select +#define GPIO_GPECSEL2_GPIO138_S 8 +#define GPIO_GPECSEL2_GPIO138_M 0xF00 // GPIO138 Master CPU Select +#define GPIO_GPECSEL2_GPIO139_S 12 +#define GPIO_GPECSEL2_GPIO139_M 0xF000 // GPIO139 Master CPU Select +#define GPIO_GPECSEL2_GPIO140_S 16 +#define GPIO_GPECSEL2_GPIO140_M 0xF0000 // GPIO140 Master CPU Select +#define GPIO_GPECSEL2_GPIO141_S 20 +#define GPIO_GPECSEL2_GPIO141_M 0xF00000 // GPIO141 Master CPU Select +#define GPIO_GPECSEL2_GPIO142_S 24 +#define GPIO_GPECSEL2_GPIO142_M 0xF000000 // GPIO142 Master CPU Select +#define GPIO_GPECSEL2_GPIO143_S 28 +#define GPIO_GPECSEL2_GPIO143_M 0xF0000000 // GPIO143 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL3 register +// +//***************************************************************************** +#define GPIO_GPECSEL3_GPIO144_S 0 +#define GPIO_GPECSEL3_GPIO144_M 0xF // GPIO144 Master CPU Select +#define GPIO_GPECSEL3_GPIO145_S 4 +#define GPIO_GPECSEL3_GPIO145_M 0xF0 // GPIO145 Master CPU Select +#define GPIO_GPECSEL3_GPIO146_S 8 +#define GPIO_GPECSEL3_GPIO146_M 0xF00 // GPIO146 Master CPU Select +#define GPIO_GPECSEL3_GPIO147_S 12 +#define GPIO_GPECSEL3_GPIO147_M 0xF000 // GPIO147 Master CPU Select +#define GPIO_GPECSEL3_GPIO148_S 16 +#define GPIO_GPECSEL3_GPIO148_M 0xF0000 // GPIO148 Master CPU Select +#define GPIO_GPECSEL3_GPIO149_S 20 +#define GPIO_GPECSEL3_GPIO149_M 0xF00000 // GPIO149 Master CPU Select +#define GPIO_GPECSEL3_GPIO150_S 24 +#define GPIO_GPECSEL3_GPIO150_M 0xF000000 // GPIO150 Master CPU Select +#define GPIO_GPECSEL3_GPIO151_S 28 +#define GPIO_GPECSEL3_GPIO151_M 0xF0000000 // GPIO151 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL4 register +// +//***************************************************************************** +#define GPIO_GPECSEL4_GPIO152_S 0 +#define GPIO_GPECSEL4_GPIO152_M 0xF // GPIO152 Master CPU Select +#define GPIO_GPECSEL4_GPIO153_S 4 +#define GPIO_GPECSEL4_GPIO153_M 0xF0 // GPIO153 Master CPU Select +#define GPIO_GPECSEL4_GPIO154_S 8 +#define GPIO_GPECSEL4_GPIO154_M 0xF00 // GPIO154 Master CPU Select +#define GPIO_GPECSEL4_GPIO155_S 12 +#define GPIO_GPECSEL4_GPIO155_M 0xF000 // GPIO155 Master CPU Select +#define GPIO_GPECSEL4_GPIO156_S 16 +#define GPIO_GPECSEL4_GPIO156_M 0xF0000 // GPIO156 Master CPU Select +#define GPIO_GPECSEL4_GPIO157_S 20 +#define GPIO_GPECSEL4_GPIO157_M 0xF00000 // GPIO157 Master CPU Select +#define GPIO_GPECSEL4_GPIO158_S 24 +#define GPIO_GPECSEL4_GPIO158_M 0xF000000 // GPIO158 Master CPU Select +#define GPIO_GPECSEL4_GPIO159_S 28 +#define GPIO_GPECSEL4_GPIO159_M 0xF0000000 // GPIO159 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPELOCK register +// +//***************************************************************************** +#define GPIO_GPELOCK_GPIO128 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO129 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO130 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO131 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO132 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO133 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO134 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO135 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO136 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO137 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO138 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO139 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO140 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO141 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO142 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO143 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO144 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO145 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO146 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO147 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO148 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO149 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO150 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO151 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO152 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO153 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO154 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO155 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO156 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO157 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO158 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO159 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECR register +// +//***************************************************************************** +#define GPIO_GPECR_GPIO128 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO129 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO130 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO131 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO132 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO133 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO134 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO135 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO136 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO137 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO138 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO139 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO140 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO141 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO142 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO143 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO144 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO145 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO146 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO147 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO148 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO149 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO150 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO151 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO152 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO153 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO154 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO155 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO156 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO157 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO158 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO159 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCTRL register +// +//***************************************************************************** +#define GPIO_GPFCTRL_QUALPRD0_S 0 +#define GPIO_GPFCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO160 to GPIO167 +#define GPIO_GPFCTRL_QUALPRD1_S 8 +#define GPIO_GPFCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFQSEL1 register +// +//***************************************************************************** +#define GPIO_GPFQSEL1_GPIO160_S 0 +#define GPIO_GPFQSEL1_GPIO160_M 0x3 // Select input qualification type + // for GPIO160 +#define GPIO_GPFQSEL1_GPIO161_S 2 +#define GPIO_GPFQSEL1_GPIO161_M 0xC // Select input qualification type + // for GPIO161 +#define GPIO_GPFQSEL1_GPIO162_S 4 +#define GPIO_GPFQSEL1_GPIO162_M 0x30 // Select input qualification type + // for GPIO162 +#define GPIO_GPFQSEL1_GPIO163_S 6 +#define GPIO_GPFQSEL1_GPIO163_M 0xC0 // Select input qualification type + // for GPIO163 +#define GPIO_GPFQSEL1_GPIO164_S 8 +#define GPIO_GPFQSEL1_GPIO164_M 0x300 // Select input qualification type + // for GPIO164 +#define GPIO_GPFQSEL1_GPIO165_S 10 +#define GPIO_GPFQSEL1_GPIO165_M 0xC00 // Select input qualification type + // for GPIO165 +#define GPIO_GPFQSEL1_GPIO166_S 12 +#define GPIO_GPFQSEL1_GPIO166_M 0x3000 // Select input qualification type + // for GPIO166 +#define GPIO_GPFQSEL1_GPIO167_S 14 +#define GPIO_GPFQSEL1_GPIO167_M 0xC000 // Select input qualification type + // for GPIO167 +#define GPIO_GPFQSEL1_GPIO168_S 16 +#define GPIO_GPFQSEL1_GPIO168_M 0x30000 // Select input qualification type + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFMUX1 register +// +//***************************************************************************** +#define GPIO_GPFMUX1_GPIO160_S 0 +#define GPIO_GPFMUX1_GPIO160_M 0x3 // Defines pin-muxing selection + // for GPIO160 +#define GPIO_GPFMUX1_GPIO161_S 2 +#define GPIO_GPFMUX1_GPIO161_M 0xC // Defines pin-muxing selection + // for GPIO161 +#define GPIO_GPFMUX1_GPIO162_S 4 +#define GPIO_GPFMUX1_GPIO162_M 0x30 // Defines pin-muxing selection + // for GPIO162 +#define GPIO_GPFMUX1_GPIO163_S 6 +#define GPIO_GPFMUX1_GPIO163_M 0xC0 // Defines pin-muxing selection + // for GPIO163 +#define GPIO_GPFMUX1_GPIO164_S 8 +#define GPIO_GPFMUX1_GPIO164_M 0x300 // Defines pin-muxing selection + // for GPIO164 +#define GPIO_GPFMUX1_GPIO165_S 10 +#define GPIO_GPFMUX1_GPIO165_M 0xC00 // Defines pin-muxing selection + // for GPIO165 +#define GPIO_GPFMUX1_GPIO166_S 12 +#define GPIO_GPFMUX1_GPIO166_M 0x3000 // Defines pin-muxing selection + // for GPIO166 +#define GPIO_GPFMUX1_GPIO167_S 14 +#define GPIO_GPFMUX1_GPIO167_M 0xC000 // Defines pin-muxing selection + // for GPIO167 +#define GPIO_GPFMUX1_GPIO168_S 16 +#define GPIO_GPFMUX1_GPIO168_M 0x30000 // Defines pin-muxing selection + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFDIR register +// +//***************************************************************************** +#define GPIO_GPFDIR_GPIO160 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO161 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO162 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO163 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO164 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO165 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO166 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO167 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO168 0x100 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFPUD register +// +//***************************************************************************** +#define GPIO_GPFPUD_GPIO160 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO161 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO162 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO163 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO164 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO165 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO166 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO167 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO168 0x100 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFINV register +// +//***************************************************************************** +#define GPIO_GPFINV_GPIO160 0x1 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO161 0x2 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO162 0x4 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO163 0x8 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO164 0x10 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO165 0x20 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO166 0x40 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO167 0x80 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO168 0x100 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFODR register +// +//***************************************************************************** +#define GPIO_GPFODR_GPIO160 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO161 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO162 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO163 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO164 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO165 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO166 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO167 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO168 0x100 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFGMUX1 register +// +//***************************************************************************** +#define GPIO_GPFGMUX1_GPIO160_S 0 +#define GPIO_GPFGMUX1_GPIO160_M 0x3 // Defines pin-muxing selection + // for GPIO160 +#define GPIO_GPFGMUX1_GPIO161_S 2 +#define GPIO_GPFGMUX1_GPIO161_M 0xC // Defines pin-muxing selection + // for GPIO161 +#define GPIO_GPFGMUX1_GPIO162_S 4 +#define GPIO_GPFGMUX1_GPIO162_M 0x30 // Defines pin-muxing selection + // for GPIO162 +#define GPIO_GPFGMUX1_GPIO163_S 6 +#define GPIO_GPFGMUX1_GPIO163_M 0xC0 // Defines pin-muxing selection + // for GPIO163 +#define GPIO_GPFGMUX1_GPIO164_S 8 +#define GPIO_GPFGMUX1_GPIO164_M 0x300 // Defines pin-muxing selection + // for GPIO164 +#define GPIO_GPFGMUX1_GPIO165_S 10 +#define GPIO_GPFGMUX1_GPIO165_M 0xC00 // Defines pin-muxing selection + // for GPIO165 +#define GPIO_GPFGMUX1_GPIO166_S 12 +#define GPIO_GPFGMUX1_GPIO166_M 0x3000 // Defines pin-muxing selection + // for GPIO166 +#define GPIO_GPFGMUX1_GPIO167_S 14 +#define GPIO_GPFGMUX1_GPIO167_M 0xC000 // Defines pin-muxing selection + // for GPIO167 +#define GPIO_GPFGMUX1_GPIO168_S 16 +#define GPIO_GPFGMUX1_GPIO168_M 0x30000 // Defines pin-muxing selection + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCSEL1 register +// +//***************************************************************************** +#define GPIO_GPFCSEL1_GPIO160_S 0 +#define GPIO_GPFCSEL1_GPIO160_M 0xF // GPIO160 Master CPU Select +#define GPIO_GPFCSEL1_GPIO161_S 4 +#define GPIO_GPFCSEL1_GPIO161_M 0xF0 // GPIO161 Master CPU Select +#define GPIO_GPFCSEL1_GPIO162_S 8 +#define GPIO_GPFCSEL1_GPIO162_M 0xF00 // GPIO162 Master CPU Select +#define GPIO_GPFCSEL1_GPIO163_S 12 +#define GPIO_GPFCSEL1_GPIO163_M 0xF000 // GPIO163 Master CPU Select +#define GPIO_GPFCSEL1_GPIO164_S 16 +#define GPIO_GPFCSEL1_GPIO164_M 0xF0000 // GPIO164 Master CPU Select +#define GPIO_GPFCSEL1_GPIO165_S 20 +#define GPIO_GPFCSEL1_GPIO165_M 0xF00000 // GPIO165 Master CPU Select +#define GPIO_GPFCSEL1_GPIO166_S 24 +#define GPIO_GPFCSEL1_GPIO166_M 0xF000000 // GPIO166 Master CPU Select +#define GPIO_GPFCSEL1_GPIO167_S 28 +#define GPIO_GPFCSEL1_GPIO167_M 0xF0000000 // GPIO167 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCSEL2 register +// +//***************************************************************************** +#define GPIO_GPFCSEL2_GPIO168_S 0 +#define GPIO_GPFCSEL2_GPIO168_M 0xF // GPIO168 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFLOCK register +// +//***************************************************************************** +#define GPIO_GPFLOCK_GPIO160 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO161 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO162 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO163 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO164 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO165 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO166 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO167 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO168 0x100 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCR register +// +//***************************************************************************** +#define GPIO_GPFCR_GPIO160 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO161 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO162 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO163 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO164 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO165 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO166 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO167 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO168 0x100 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPADAT register +// +//***************************************************************************** +#define GPIO_GPADAT_GPIO0 0x1 // Data Register for this pin +#define GPIO_GPADAT_GPIO1 0x2 // Data Register for this pin +#define GPIO_GPADAT_GPIO2 0x4 // Data Register for this pin +#define GPIO_GPADAT_GPIO3 0x8 // Data Register for this pin +#define GPIO_GPADAT_GPIO4 0x10 // Data Register for this pin +#define GPIO_GPADAT_GPIO5 0x20 // Data Register for this pin +#define GPIO_GPADAT_GPIO6 0x40 // Data Register for this pin +#define GPIO_GPADAT_GPIO7 0x80 // Data Register for this pin +#define GPIO_GPADAT_GPIO8 0x100 // Data Register for this pin +#define GPIO_GPADAT_GPIO9 0x200 // Data Register for this pin +#define GPIO_GPADAT_GPIO10 0x400 // Data Register for this pin +#define GPIO_GPADAT_GPIO11 0x800 // Data Register for this pin +#define GPIO_GPADAT_GPIO12 0x1000 // Data Register for this pin +#define GPIO_GPADAT_GPIO13 0x2000 // Data Register for this pin +#define GPIO_GPADAT_GPIO14 0x4000 // Data Register for this pin +#define GPIO_GPADAT_GPIO15 0x8000 // Data Register for this pin +#define GPIO_GPADAT_GPIO16 0x10000 // Data Register for this pin +#define GPIO_GPADAT_GPIO17 0x20000 // Data Register for this pin +#define GPIO_GPADAT_GPIO18 0x40000 // Data Register for this pin +#define GPIO_GPADAT_GPIO19 0x80000 // Data Register for this pin +#define GPIO_GPADAT_GPIO20 0x100000 // Data Register for this pin +#define GPIO_GPADAT_GPIO21 0x200000 // Data Register for this pin +#define GPIO_GPADAT_GPIO22 0x400000 // Data Register for this pin +#define GPIO_GPADAT_GPIO23 0x800000 // Data Register for this pin +#define GPIO_GPADAT_GPIO24 0x1000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO25 0x2000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO26 0x4000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO27 0x8000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO28 0x10000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO29 0x20000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO30 0x40000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO31 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPASET register +// +//***************************************************************************** +#define GPIO_GPASET_GPIO0 0x1 // Output Set bit for this pin +#define GPIO_GPASET_GPIO1 0x2 // Output Set bit for this pin +#define GPIO_GPASET_GPIO2 0x4 // Output Set bit for this pin +#define GPIO_GPASET_GPIO3 0x8 // Output Set bit for this pin +#define GPIO_GPASET_GPIO4 0x10 // Output Set bit for this pin +#define GPIO_GPASET_GPIO5 0x20 // Output Set bit for this pin +#define GPIO_GPASET_GPIO6 0x40 // Output Set bit for this pin +#define GPIO_GPASET_GPIO7 0x80 // Output Set bit for this pin +#define GPIO_GPASET_GPIO8 0x100 // Output Set bit for this pin +#define GPIO_GPASET_GPIO9 0x200 // Output Set bit for this pin +#define GPIO_GPASET_GPIO10 0x400 // Output Set bit for this pin +#define GPIO_GPASET_GPIO11 0x800 // Output Set bit for this pin +#define GPIO_GPASET_GPIO12 0x1000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO13 0x2000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO14 0x4000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO15 0x8000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO16 0x10000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO17 0x20000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO18 0x40000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO19 0x80000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO20 0x100000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO21 0x200000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO22 0x400000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO23 0x800000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO24 0x1000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO25 0x2000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO26 0x4000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO27 0x8000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO28 0x10000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO29 0x20000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO30 0x40000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO31 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACLEAR register +// +//***************************************************************************** +#define GPIO_GPACLEAR_GPIO0 0x1 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO1 0x2 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO2 0x4 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO3 0x8 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO4 0x10 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO5 0x20 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO6 0x40 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO7 0x80 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO8 0x100 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO9 0x200 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO10 0x400 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO11 0x800 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO12 0x1000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO13 0x2000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO14 0x4000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO15 0x8000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO16 0x10000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO17 0x20000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO18 0x40000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO19 0x80000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO20 0x100000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO21 0x200000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO22 0x400000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO23 0x800000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO24 0x1000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO25 0x2000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO26 0x4000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO27 0x8000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO28 0x10000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO29 0x20000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO30 0x40000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO31 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPATOGGLE register +// +//***************************************************************************** +#define GPIO_GPATOGGLE_GPIO0 0x1 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO1 0x2 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO2 0x4 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO3 0x8 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO4 0x10 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO5 0x20 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO6 0x40 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO7 0x80 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO8 0x100 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO9 0x200 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO10 0x400 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO11 0x800 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO12 0x1000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO13 0x2000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO14 0x4000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO15 0x8000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO16 0x10000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO17 0x20000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO18 0x40000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO19 0x80000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO20 0x100000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO21 0x200000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO22 0x400000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO23 0x800000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO24 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO25 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO26 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO27 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO28 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO29 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO30 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO31 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBDAT register +// +//***************************************************************************** +#define GPIO_GPBDAT_GPIO32 0x1 // Data Register for this pin +#define GPIO_GPBDAT_GPIO33 0x2 // Data Register for this pin +#define GPIO_GPBDAT_GPIO34 0x4 // Data Register for this pin +#define GPIO_GPBDAT_GPIO35 0x8 // Data Register for this pin +#define GPIO_GPBDAT_GPIO36 0x10 // Data Register for this pin +#define GPIO_GPBDAT_GPIO37 0x20 // Data Register for this pin +#define GPIO_GPBDAT_GPIO38 0x40 // Data Register for this pin +#define GPIO_GPBDAT_GPIO39 0x80 // Data Register for this pin +#define GPIO_GPBDAT_GPIO40 0x100 // Data Register for this pin +#define GPIO_GPBDAT_GPIO41 0x200 // Data Register for this pin +#define GPIO_GPBDAT_GPIO42 0x400 // Data Register for this pin +#define GPIO_GPBDAT_GPIO43 0x800 // Data Register for this pin +#define GPIO_GPBDAT_GPIO44 0x1000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO45 0x2000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO46 0x4000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO47 0x8000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO48 0x10000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO49 0x20000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO50 0x40000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO51 0x80000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO52 0x100000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO53 0x200000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO54 0x400000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO55 0x800000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO56 0x1000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO57 0x2000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO58 0x4000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO59 0x8000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO60 0x10000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO61 0x20000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO62 0x40000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO63 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBSET register +// +//***************************************************************************** +#define GPIO_GPBSET_GPIO32 0x1 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO33 0x2 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO34 0x4 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO35 0x8 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO36 0x10 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO37 0x20 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO38 0x40 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO39 0x80 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO40 0x100 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO41 0x200 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO42 0x400 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO43 0x800 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO44 0x1000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO45 0x2000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO46 0x4000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO47 0x8000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO48 0x10000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO49 0x20000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO50 0x40000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO51 0x80000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO52 0x100000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO53 0x200000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO54 0x400000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO55 0x800000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO56 0x1000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO57 0x2000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO58 0x4000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO59 0x8000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO60 0x10000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO61 0x20000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO62 0x40000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO63 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCLEAR register +// +//***************************************************************************** +#define GPIO_GPBCLEAR_GPIO32 0x1 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO33 0x2 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO34 0x4 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO35 0x8 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO36 0x10 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO37 0x20 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO38 0x40 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO39 0x80 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO40 0x100 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO41 0x200 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO42 0x400 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO43 0x800 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO44 0x1000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO45 0x2000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO46 0x4000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO47 0x8000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO48 0x10000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO49 0x20000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO50 0x40000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO51 0x80000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO52 0x100000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO53 0x200000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO54 0x400000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO55 0x800000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO56 0x1000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO57 0x2000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO58 0x4000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO59 0x8000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO60 0x10000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO61 0x20000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO62 0x40000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO63 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBTOGGLE register +// +//***************************************************************************** +#define GPIO_GPBTOGGLE_GPIO32 0x1 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO33 0x2 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO34 0x4 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO35 0x8 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO36 0x10 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO37 0x20 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO38 0x40 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO39 0x80 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO40 0x100 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO41 0x200 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO42 0x400 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO43 0x800 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO44 0x1000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO45 0x2000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO46 0x4000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO47 0x8000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO48 0x10000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO49 0x20000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO50 0x40000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO51 0x80000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO52 0x100000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO53 0x200000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO54 0x400000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO55 0x800000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO56 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO57 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO58 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO59 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO60 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO61 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO62 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO63 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCDAT register +// +//***************************************************************************** +#define GPIO_GPCDAT_GPIO64 0x1 // Data Register for this pin +#define GPIO_GPCDAT_GPIO65 0x2 // Data Register for this pin +#define GPIO_GPCDAT_GPIO66 0x4 // Data Register for this pin +#define GPIO_GPCDAT_GPIO67 0x8 // Data Register for this pin +#define GPIO_GPCDAT_GPIO68 0x10 // Data Register for this pin +#define GPIO_GPCDAT_GPIO69 0x20 // Data Register for this pin +#define GPIO_GPCDAT_GPIO70 0x40 // Data Register for this pin +#define GPIO_GPCDAT_GPIO71 0x80 // Data Register for this pin +#define GPIO_GPCDAT_GPIO72 0x100 // Data Register for this pin +#define GPIO_GPCDAT_GPIO73 0x200 // Data Register for this pin +#define GPIO_GPCDAT_GPIO74 0x400 // Data Register for this pin +#define GPIO_GPCDAT_GPIO75 0x800 // Data Register for this pin +#define GPIO_GPCDAT_GPIO76 0x1000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO77 0x2000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO78 0x4000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO79 0x8000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO80 0x10000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO81 0x20000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO82 0x40000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO83 0x80000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO84 0x100000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO85 0x200000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO86 0x400000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO87 0x800000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO88 0x1000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO89 0x2000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO90 0x4000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO91 0x8000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO92 0x10000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO93 0x20000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO94 0x40000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO95 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCSET register +// +//***************************************************************************** +#define GPIO_GPCSET_GPIO64 0x1 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO65 0x2 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO66 0x4 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO67 0x8 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO68 0x10 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO69 0x20 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO70 0x40 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO71 0x80 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO72 0x100 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO73 0x200 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO74 0x400 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO75 0x800 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO76 0x1000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO77 0x2000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO78 0x4000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO79 0x8000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO80 0x10000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO81 0x20000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO82 0x40000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO83 0x80000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO84 0x100000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO85 0x200000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO86 0x400000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO87 0x800000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO88 0x1000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO89 0x2000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO90 0x4000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO91 0x8000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO92 0x10000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO93 0x20000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO94 0x40000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO95 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCLEAR register +// +//***************************************************************************** +#define GPIO_GPCCLEAR_GPIO64 0x1 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO65 0x2 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO66 0x4 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO67 0x8 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO68 0x10 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO69 0x20 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO70 0x40 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO71 0x80 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO72 0x100 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO73 0x200 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO74 0x400 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO75 0x800 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO76 0x1000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO77 0x2000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO78 0x4000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO79 0x8000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO80 0x10000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO81 0x20000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO82 0x40000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO83 0x80000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO84 0x100000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO85 0x200000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO86 0x400000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO87 0x800000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO88 0x1000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO89 0x2000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO90 0x4000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO91 0x8000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO92 0x10000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO93 0x20000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO94 0x40000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO95 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCTOGGLE register +// +//***************************************************************************** +#define GPIO_GPCTOGGLE_GPIO64 0x1 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO65 0x2 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO66 0x4 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO67 0x8 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO68 0x10 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO69 0x20 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO70 0x40 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO71 0x80 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO72 0x100 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO73 0x200 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO74 0x400 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO75 0x800 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO76 0x1000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO77 0x2000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO78 0x4000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO79 0x8000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO80 0x10000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO81 0x20000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO82 0x40000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO83 0x80000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO84 0x100000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO85 0x200000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO86 0x400000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO87 0x800000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO88 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO89 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO90 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO91 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO92 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO93 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO94 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO95 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDDAT register +// +//***************************************************************************** +#define GPIO_GPDDAT_GPIO96 0x1 // Data Register for this pin +#define GPIO_GPDDAT_GPIO97 0x2 // Data Register for this pin +#define GPIO_GPDDAT_GPIO98 0x4 // Data Register for this pin +#define GPIO_GPDDAT_GPIO99 0x8 // Data Register for this pin +#define GPIO_GPDDAT_GPIO100 0x10 // Data Register for this pin +#define GPIO_GPDDAT_GPIO101 0x20 // Data Register for this pin +#define GPIO_GPDDAT_GPIO102 0x40 // Data Register for this pin +#define GPIO_GPDDAT_GPIO103 0x80 // Data Register for this pin +#define GPIO_GPDDAT_GPIO104 0x100 // Data Register for this pin +#define GPIO_GPDDAT_GPIO105 0x200 // Data Register for this pin +#define GPIO_GPDDAT_GPIO106 0x400 // Data Register for this pin +#define GPIO_GPDDAT_GPIO107 0x800 // Data Register for this pin +#define GPIO_GPDDAT_GPIO108 0x1000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO109 0x2000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO110 0x4000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO111 0x8000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO112 0x10000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO113 0x20000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO114 0x40000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO115 0x80000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO116 0x100000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO117 0x200000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO118 0x400000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO119 0x800000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO120 0x1000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO121 0x2000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO122 0x4000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO123 0x8000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO124 0x10000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO125 0x20000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO126 0x40000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO127 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDSET register +// +//***************************************************************************** +#define GPIO_GPDSET_GPIO96 0x1 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO97 0x2 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO98 0x4 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO99 0x8 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO100 0x10 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO101 0x20 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO102 0x40 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO103 0x80 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO104 0x100 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO105 0x200 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO106 0x400 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO107 0x800 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO108 0x1000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO109 0x2000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO110 0x4000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO111 0x8000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO112 0x10000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO113 0x20000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO114 0x40000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO115 0x80000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO116 0x100000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO117 0x200000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO118 0x400000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO119 0x800000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO120 0x1000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO121 0x2000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO122 0x4000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO123 0x8000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO124 0x10000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO125 0x20000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO126 0x40000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO127 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCLEAR register +// +//***************************************************************************** +#define GPIO_GPDCLEAR_GPIO96 0x1 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO97 0x2 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO98 0x4 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO99 0x8 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO100 0x10 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO101 0x20 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO102 0x40 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO103 0x80 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO104 0x100 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO105 0x200 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO106 0x400 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO107 0x800 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO108 0x1000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO109 0x2000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO110 0x4000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO111 0x8000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO112 0x10000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO113 0x20000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO114 0x40000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO115 0x80000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO116 0x100000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO117 0x200000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO118 0x400000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO119 0x800000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO120 0x1000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO121 0x2000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO122 0x4000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO123 0x8000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO124 0x10000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO125 0x20000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO126 0x40000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO127 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDTOGGLE register +// +//***************************************************************************** +#define GPIO_GPDTOGGLE_GPIO96 0x1 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO97 0x2 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO98 0x4 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO99 0x8 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO100 0x10 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO101 0x20 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO102 0x40 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO103 0x80 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO104 0x100 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO105 0x200 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO106 0x400 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO107 0x800 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO108 0x1000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO109 0x2000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO110 0x4000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO111 0x8000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO112 0x10000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO113 0x20000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO114 0x40000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO115 0x80000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO116 0x100000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO117 0x200000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO118 0x400000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO119 0x800000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO120 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO121 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO122 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO123 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO124 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO125 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO126 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO127 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEDAT register +// +//***************************************************************************** +#define GPIO_GPEDAT_GPIO128 0x1 // Data Register for this pin +#define GPIO_GPEDAT_GPIO129 0x2 // Data Register for this pin +#define GPIO_GPEDAT_GPIO130 0x4 // Data Register for this pin +#define GPIO_GPEDAT_GPIO131 0x8 // Data Register for this pin +#define GPIO_GPEDAT_GPIO132 0x10 // Data Register for this pin +#define GPIO_GPEDAT_GPIO133 0x20 // Data Register for this pin +#define GPIO_GPEDAT_GPIO134 0x40 // Data Register for this pin +#define GPIO_GPEDAT_GPIO135 0x80 // Data Register for this pin +#define GPIO_GPEDAT_GPIO136 0x100 // Data Register for this pin +#define GPIO_GPEDAT_GPIO137 0x200 // Data Register for this pin +#define GPIO_GPEDAT_GPIO138 0x400 // Data Register for this pin +#define GPIO_GPEDAT_GPIO139 0x800 // Data Register for this pin +#define GPIO_GPEDAT_GPIO140 0x1000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO141 0x2000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO142 0x4000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO143 0x8000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO144 0x10000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO145 0x20000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO146 0x40000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO147 0x80000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO148 0x100000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO149 0x200000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO150 0x400000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO151 0x800000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO152 0x1000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO153 0x2000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO154 0x4000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO155 0x8000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO156 0x10000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO157 0x20000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO158 0x40000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO159 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPESET register +// +//***************************************************************************** +#define GPIO_GPESET_GPIO128 0x1 // Output Set bit for this pin +#define GPIO_GPESET_GPIO129 0x2 // Output Set bit for this pin +#define GPIO_GPESET_GPIO130 0x4 // Output Set bit for this pin +#define GPIO_GPESET_GPIO131 0x8 // Output Set bit for this pin +#define GPIO_GPESET_GPIO132 0x10 // Output Set bit for this pin +#define GPIO_GPESET_GPIO133 0x20 // Output Set bit for this pin +#define GPIO_GPESET_GPIO134 0x40 // Output Set bit for this pin +#define GPIO_GPESET_GPIO135 0x80 // Output Set bit for this pin +#define GPIO_GPESET_GPIO136 0x100 // Output Set bit for this pin +#define GPIO_GPESET_GPIO137 0x200 // Output Set bit for this pin +#define GPIO_GPESET_GPIO138 0x400 // Output Set bit for this pin +#define GPIO_GPESET_GPIO139 0x800 // Output Set bit for this pin +#define GPIO_GPESET_GPIO140 0x1000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO141 0x2000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO142 0x4000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO143 0x8000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO144 0x10000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO145 0x20000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO146 0x40000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO147 0x80000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO148 0x100000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO149 0x200000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO150 0x400000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO151 0x800000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO152 0x1000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO153 0x2000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO154 0x4000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO155 0x8000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO156 0x10000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO157 0x20000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO158 0x40000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO159 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECLEAR register +// +//***************************************************************************** +#define GPIO_GPECLEAR_GPIO128 0x1 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO129 0x2 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO130 0x4 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO131 0x8 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO132 0x10 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO133 0x20 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO134 0x40 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO135 0x80 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO136 0x100 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO137 0x200 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO138 0x400 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO139 0x800 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO140 0x1000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO141 0x2000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO142 0x4000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO143 0x8000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO144 0x10000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO145 0x20000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO146 0x40000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO147 0x80000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO148 0x100000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO149 0x200000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO150 0x400000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO151 0x800000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO152 0x1000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO153 0x2000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO154 0x4000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO155 0x8000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO156 0x10000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO157 0x20000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO158 0x40000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO159 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPETOGGLE register +// +//***************************************************************************** +#define GPIO_GPETOGGLE_GPIO128 0x1 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO129 0x2 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO130 0x4 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO131 0x8 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO132 0x10 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO133 0x20 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO134 0x40 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO135 0x80 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO136 0x100 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO137 0x200 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO138 0x400 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO139 0x800 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO140 0x1000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO141 0x2000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO142 0x4000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO143 0x8000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO144 0x10000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO145 0x20000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO146 0x40000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO147 0x80000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO148 0x100000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO149 0x200000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO150 0x400000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO151 0x800000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO152 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO153 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO154 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO155 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO156 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO157 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO158 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO159 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFDAT register +// +//***************************************************************************** +#define GPIO_GPFDAT_GPIO160 0x1 // Data Register for this pin +#define GPIO_GPFDAT_GPIO161 0x2 // Data Register for this pin +#define GPIO_GPFDAT_GPIO162 0x4 // Data Register for this pin +#define GPIO_GPFDAT_GPIO163 0x8 // Data Register for this pin +#define GPIO_GPFDAT_GPIO164 0x10 // Data Register for this pin +#define GPIO_GPFDAT_GPIO165 0x20 // Data Register for this pin +#define GPIO_GPFDAT_GPIO166 0x40 // Data Register for this pin +#define GPIO_GPFDAT_GPIO167 0x80 // Data Register for this pin +#define GPIO_GPFDAT_GPIO168 0x100 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFSET register +// +//***************************************************************************** +#define GPIO_GPFSET_GPIO160 0x1 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO161 0x2 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO162 0x4 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO163 0x8 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO164 0x10 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO165 0x20 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO166 0x40 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO167 0x80 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO168 0x100 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCLEAR register +// +//***************************************************************************** +#define GPIO_GPFCLEAR_GPIO160 0x1 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO161 0x2 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO162 0x4 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO163 0x8 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO164 0x10 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO165 0x20 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO166 0x40 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO167 0x80 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO168 0x100 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFTOGGLE register +// +//***************************************************************************** +#define GPIO_GPFTOGGLE_GPIO160 0x1 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO161 0x2 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO162 0x4 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO163 0x8 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO164 0x10 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO165 0x20 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO166 0x40 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO167 0x80 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO168 0x100 // Output Toggle bit for this pin +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h new file mode 100644 index 0000000000..57a045c8f2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h @@ -0,0 +1,244 @@ +//########################################################################### +// +// FILE: hw_i2c.h +// +// TITLE: Definitions for the C28x I2C registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets +// +//***************************************************************************** +#define I2C_O_OAR 0x0 // I2C Own address +#define I2C_O_IER 0x1 // I2C Interrupt Enable +#define I2C_O_STR 0x2 // I2C Status +#define I2C_O_CLKL 0x3 // I2C Clock low-time divider +#define I2C_O_CLKH 0x4 // I2C Clock high-time divider +#define I2C_O_CNT 0x5 // I2C Data count +#define I2C_O_DRR 0x6 // I2C Data receive +#define I2C_O_SAR 0x7 // I2C Slave address +#define I2C_O_DXR 0x8 // I2C Data Transmit +#define I2C_O_MDR 0x9 // I2C Mode +#define I2C_O_ISRC 0xA // I2C Interrupt Source +#define I2C_O_EMDR 0xB // I2C Extended Mode +#define I2C_O_PSC 0xC // I2C Prescaler +#define I2C_O_FFTX 0x20 // I2C FIFO Transmit +#define I2C_O_FFRX 0x21 // I2C FIFO Receive + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2COAR register +// +//***************************************************************************** +#define I2C_OAR_OAR_S 0 +#define I2C_OAR_OAR_M 0x3FF // I2C Own address + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CIER register +// +//***************************************************************************** +#define I2C_IER_ARBL 0x1 // Arbitration-lost interrupt + // enable +#define I2C_IER_NACK 0x2 // No-acknowledgment interrupt + // enable +#define I2C_IER_ARDY 0x4 // Register-access-ready interrupt + // enable +#define I2C_IER_RRDY 0x8 // Receive-data-ready interrupt + // enable +#define I2C_IER_XRDY 0x10 // Transmit-data-ready interrupt + // enable +#define I2C_IER_SCD 0x20 // Stop condition detected + // interrupt enable +#define I2C_IER_AAS 0x40 // Addressed as slave interrupt + // enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CSTR register +// +//***************************************************************************** +#define I2C_STR_ARBL 0x1 // Arbitration-lost interrupt flag + // bit +#define I2C_STR_NACK 0x2 // No-acknowledgment interrupt + // flag bit. +#define I2C_STR_ARDY 0x4 // Register-access-ready interrupt + // flag bit +#define I2C_STR_RRDY 0x8 // Receive-data-ready interrupt + // flag bit. +#define I2C_STR_XRDY 0x10 // Transmit-data-ready interrupt + // flag bit. +#define I2C_STR_SCD 0x20 // Stop condition detected bit. +#define I2C_STR_AD0 0x100 // Address 0 bits +#define I2C_STR_AAS 0x200 // Addressed-as-slave bit +#define I2C_STR_XSMT 0x400 // Transmit shift register empty + // bit. +#define I2C_STR_RSFULL 0x800 // Receive shift register full + // bit. +#define I2C_STR_BB 0x1000 // Bus busy bit. +#define I2C_STR_NACKSNT 0x2000 // NACK sent bit. +#define I2C_STR_SDIR 0x4000 // Slave direction bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CCLKL register +// +//***************************************************************************** +#define I2C_CLKL_I2CCLKL_S 0 +#define I2C_CLKL_I2CCLKL_M 0xFFFF // Clock low-time divide-down + // value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CCLKH register +// +//***************************************************************************** +#define I2C_CLKH_I2CCLKH_S 0 +#define I2C_CLKH_I2CCLKH_M 0xFFFF // Clock high-time divide-down + // value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CCNT register +// +//***************************************************************************** +#define I2C_CNT_I2CCNT_S 0 +#define I2C_CNT_I2CCNT_M 0xFFFF // Data count value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CDRR register +// +//***************************************************************************** +#define I2C_DRR_DATA_S 0 +#define I2C_DRR_DATA_M 0xFF // Receive data + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CSAR register +// +//***************************************************************************** +#define I2C_SAR_SAR_S 0 +#define I2C_SAR_SAR_M 0x3FF // Slave Address + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CDXR register +// +//***************************************************************************** +#define I2C_DXR_DATA_S 0 +#define I2C_DXR_DATA_M 0xFF // Transmit data + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CMDR register +// +//***************************************************************************** +#define I2C_MDR_BC_S 0 +#define I2C_MDR_BC_M 0x7 // Bit count bits. +#define I2C_MDR_FDF 0x8 // Free Data Format +#define I2C_MDR_STB 0x10 // START Byte Mode +#define I2C_MDR_IRS 0x20 // I2C Module Reset +#define I2C_MDR_DLB 0x40 // Digital Loopback Mode +#define I2C_MDR_RM 0x80 // Repeat Mode +#define I2C_MDR_XA 0x100 // Expanded Address Mode +#define I2C_MDR_TRX 0x200 // Transmitter Mode +#define I2C_MDR_MST 0x400 // Master Mode +#define I2C_MDR_STP 0x800 // STOP Condition +#define I2C_MDR_STT 0x2000 // START condition bit +#define I2C_MDR_FREE 0x4000 // Debug Action +#define I2C_MDR_NACKMOD 0x8000 // NACK mode bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CISRC register +// +//***************************************************************************** +#define I2C_ISRC_INTCODE_S 0 +#define I2C_ISRC_INTCODE_M 0x7 // Interrupt code bits. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CEMDR register +// +//***************************************************************************** +#define I2C_EMDR_BC 0x1 // Backwards compatibility mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CPSC register +// +//***************************************************************************** +#define I2C_PSC_IPSC_S 0 +#define I2C_PSC_IPSC_M 0xFF // I2C Prescaler Divide Down + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CFFTX register +// +//***************************************************************************** +#define I2C_FFTX_TXFFIL_S 0 +#define I2C_FFTX_TXFFIL_M 0x1F // Transmit FIFO Interrupt Level +#define I2C_FFTX_TXFFIENA 0x20 // Transmit FIFO Interrupt Enable +#define I2C_FFTX_TXFFINTCLR 0x40 // Transmit FIFO Interrupt Flag + // Clear +#define I2C_FFTX_TXFFINT 0x80 // Transmit FIFO Interrupt Flag +#define I2C_FFTX_TXFFST_S 8 +#define I2C_FFTX_TXFFST_M 0x1F00 // Transmit FIFO Status +#define I2C_FFTX_TXFFRST 0x2000 // Transmit FIFO Reset +#define I2C_FFTX_I2CFFEN 0x4000 // Transmit FIFO Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CFFRX register +// +//***************************************************************************** +#define I2C_FFRX_RXFFIL_S 0 +#define I2C_FFRX_RXFFIL_M 0x1F // Receive FIFO Interrupt Level +#define I2C_FFRX_RXFFIENA 0x20 // Receive FIFO Interrupt Enable +#define I2C_FFRX_RXFFINTCLR 0x40 // Receive FIFO Interrupt Flag + // Clear +#define I2C_FFRX_RXFFINT 0x80 // Receive FIFO Interrupt Flag +#define I2C_FFRX_RXFFST_S 8 +#define I2C_FFRX_RXFFST_M 0x1F00 // Receive FIFO Status +#define I2C_FFRX_RXFFRST 0x2000 // Receive FIFO Reset +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h new file mode 100644 index 0000000000..8f2ca7471f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h @@ -0,0 +1,299 @@ +//########################################################################### +// +// FILE: hw_ints.h +// +// TITLE: Definitions of interrupt numbers for use with interrupt.c. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// PIE Interrupt Numbers +// +// 0x00FF = PIE Table Row # +// 0xFF00 = PIE Table Column # +// 0xFFFF0000 = PIE Vector ID +// +//***************************************************************************** + +// Lower PIE Group 1 +#define INT_ADCA_CH1 0x200101 //ADC-A Interrupt 1 +#define INT_ADCB_CH1 0x210102 //ADC-B Interrupt 1 +#define INT_ADCC_CH1 0x220103 //ADC-C Interrupt 1 +#define INT_XINT1 0x230104 //External Interrupt 1 +#define INT_XINT2 0x240105 //External Interrupt 2 +#define INT_ADCD_CH1 0x250106 //ADC-D Interrupt 1 +#define INT_TINT0 0x260107 //Timer Interrupt 0 +#define INT_WAKEINT 0x270108 //Wakeup Interrupt + +// Lower PIE Group 2 +#define INT_PWM1TZ 0x280201 //PWM TZ Interrupt 1 +#define INT_PWM2TZ 0x290202 //PWM TZ Interrupt 2 +#define INT_PWM3TZ 0x2A0203 //PWM TZ Interrupt 3 +#define INT_PWM4TZ 0x2B0204 //PWM TZ Interrupt 4 +#define INT_PWM5TZ 0x2C0205 //PWM TZ Interrupt 5 +#define INT_PWM6TZ 0x2D0206 //PWM TZ Interrupt 6 +#define INT_PWM7TZ 0x2E0207 //PWM TZ Interrupt 7 +#define INT_PWM8TZ 0x2F0208 //PWM TZ Interrupt 8 + +// Lower PIE Group 3 +#define INT_PWM1INT 0x300301 //PWM Interrupt 1 +#define INT_PWM2INT 0x310302 //PWM Interrupt 2 +#define INT_PWM3INT 0x320303 //PWM Interrupt 3 +#define INT_PWM4INT 0x330304 //PWM Interrupt 4 +#define INT_PWM5INT 0x340305 //PWM Interrupt 5 +#define INT_PWM6INT 0x350306 //PWM Interrupt 6 +#define INT_PWM7INT 0x360307 //PWM Interrupt 7 +#define INT_PWM8INT 0x370308 //PWM Interrupt 8 + +// Lower PIE Group 4 +#define INT_CAP1INT 0x380401 //Capture Interrupt 1 +#define INT_CAP2INT 0x390402 //Capture Interrupt 2 +#define INT_CAP3INT 0x3A0403 //Capture Interrupt 3 +#define INT_CAP4INT 0x3B0404 //Capture Interrupt 4 +#define INT_CAP5INT 0x3C0405 //Capture Interrupt 5 +#define INT_CAP6INT 0x3D0406 //Capture Interrupt 6 +#define INT_CAP7INT 0x3E0407 //Capture Interrupt 7 +#define INT_CAP8INT 0x3F0408 //Capture Interrupt 8 + +// Lower PIE Group 5 +#define INT_EQEP1INT 0x400501 //Quadrature Interrupt 1 +#define INT_EQEP2INT 0x410502 //Quadrature Interrupt 2 +#define INT_EQEP3INT 0x420503 //Quadrature Interrupt 3 +#define INT_EQEP4INT 0x430504 //Quadrature Interrupt 4 +#define INT_CLB1INT 0x440505 //CLB Interrupt 1 +#define INT_CLB2INT 0x450506 //CLB Interrupt 2 +#define INT_CLB3INT 0x460507 //CLB Interrupt 3 +#define INT_CLB4INT 0x470508 //CLB Interrupt 4 + +// Lower PIE Group 6 +#define INT_SPIRXINTA 0x480601 //SPI-A Receive Interrupt +#define INT_SPITXINTA 0x490602 //SPI-A Transmit Interrupt +#define INT_SPIRXINTB 0x4A0603 //SPI-B Receive Interrupt +#define INT_SPITXINTB 0x4B0604 //SPI-B Transmit Interrupt +#define INT_MRINTA 0x4C0605 //McBSP-A Receive Interrupt +#define INT_MXINTA 0x4D0606 //McBSP-A Transmit Interrupt +#define INT_MRINTB 0x4E0607 //McBSP-B Receive Interrupt +#define INT_MXINTB 0x4F0608 //McBSP-B Transmit Interrupt + +// Lower PIE Group 7 +#define INT_DMA1INT 0x500701 //DMA Channel 1 Interrupt +#define INT_DMA2INT 0x510702 //DMA Channel 2 Interrupt +#define INT_DMA3INT 0x520703 //DMA Channel 3 Interrupt +#define INT_DMA4INT 0x530704 //DMA Channel 4 Interrupt +#define INT_DMA5INT 0x540705 //DMA Channel 5 Interrupt +#define INT_DMA6INT 0x550706 //DMA Channel 6 Interrupt + +// Lower PIE Group 8 +#define INT_I2CINT1A 0x580801 //I2C-A Basic Interrupts +#define INT_I2CINT2A 0x590802 //I2C-A FIFO Interrupts +#define INT_I2CINT1B 0x5A0803 //I2C-B Basic Interrupts +#define INT_I2CINT2B 0x5B0804 //I2C-B FIFO Interrupts +#define INT_SCICRX 0x5C0805 //SCI-C Receive Interrupt +#define INT_SCICTX 0x5D0806 //SCI-C Transmit Interrupt +#define INT_SCIDRX 0x5E0807 //SCI-D Receive Interrupt +#define INT_SCIDTX 0x5F0808 //SCI-D Transmit Interrupt + +// Lower PIE Group 9 +#define INT_SCIRXINTA 0x600901 //SCI-A RX Interrupt +#define INT_SCITXINTA 0x610902 //SCI-A TX Interrupt +#define INT_SCIRXINTB 0x620903 //SCI-B RX Interrupt +#define INT_SCITXINTB 0x630904 //SCI-B TX Interrupt +#define INT_CANA_0 0x640905 //CANA 0 Interrupt +#define INT_CANA_1 0x650906 //CANA 1 Interrupt +#define INT_CANB_0 0x660907 //CANB 0 Interrupt +#define INT_CANB_1 0x670908 //CANB 1 Interrupt + +// Lower PIE Group 10 +#define INT_ADCA_EVT 0x680A01 //ADCA_EVT Interrupt +#define INT_ADCA_CH2 0x690A02 //ADCA_CH2 Interrupt 2 +#define INT_ADCA_CH3 0x6A0A03 //ADCA_CH3 Interrupt 3 +#define INT_ADCA_CH4 0x6B0A04 //ADCA_CH4 Interrupt 4 +#define INT_ADCB_EVT 0x6C0A05 //ADCB_EVT Interrupt +#define INT_ADCB_CH2 0x6D0A06 //ADCB_CH2 Interrupt 2 +#define INT_ADCB_CH3 0x6E0A07 //ADCB_CH3 Interrupt 3 +#define INT_ADCB_CH4 0x6F0A08 //ADCB_CH4 Interrupt 4 + +// Lower PIE Group 11 +#define INT_CLA1INT1 0x700B01 //CLA_1 Interrupt 1 +#define INT_CLA1INT2 0x710B02 //CLA_1 Interrupt 2 +#define INT_CLA1INT3 0x720B03 //CLA_1 Interrupt 3 +#define INT_CLA1INT4 0x730B04 //CLA_1 Interrupt 4 +#define INT_CLA1INT5 0x740B05 //CLA_1 Interrupt 5 +#define INT_CLA1INT6 0x750B06 //CLA_1 Interrupt 6 +#define INT_CLA1INT7 0x760B07 //CLA_1 Interrupt 7 +#define INT_CLA1INT8 0x770B08 //CLA_1 Interrupt 8 + +// Lower PIE Group 12 +#define INT_XINT3 0x780C01 //External Interrupt 3 +#define INT_XINT4 0x790C02 //External Interrupt 4 +#define INT_XINT5 0x7A0C03 //External Interrupt 5 +#define INT_FMC 0x7C0C05 //FMC Interrupt +#define INT_VCU 0x7D0C06 //VCU Interrupt +#define INT_LVF 0x7E0C07 //Latched Overflow +#define INT_LUF 0x7F0C08 //Latched Underflow + +// Upper PIE Group 1 +#define INT_IPC0INT 0x84010D //IPC Interrupt 1 +#define INT_IPC1INT 0x85010E //IPC Interrupt 2 +#define INT_IPC2INT 0x86010F //IPC Interrupt 3 +#define INT_IPC3INT 0x870110 //IPC Interrupt 4 + +// Upper PIE Group 2 +#define INT_PWM9TZ 0x880209 //PWM TZ Interrupt 9 +#define INT_PWM10TZ 0x89020A //PWM TZ Interrupt 10 +#define INT_PWM11TZ 0x8A020B //PWM TZ Interrupt 11 +#define INT_PWM12TZ 0x8B020C //PWM TZ Interrupt 12 + +// Upper PIE Group 3 +#define INT_PWM9INT 0x900309 //PWM Interrupt 9 +#define INT_PWM10INT 0x91030A //PWN Interrupt 10 +#define INT_PWM11INT 0x92030B //PWM Interrupt 11 +#define INT_PWM12INT 0x93030C //PWM Interrupt 12 + +// Upper PIE Group 4 +#define INT_HRCAP1INT 0x980409 //High-Res Capture Interrupt 1 +#define INT_HRCAP2INT 0x99040A //High-Res Capture Interrupt 2 +#define INT_HRCAP3INT 0x9A040B //High-Res Capture Interrupt 3 +#define INT_HRCAP4INT 0x9B040C //High-Res Capture Interrupt 4 +#define INT_HRCAP5INT 0x9C040D //High-Res Capture Interrupt 1 +#define INT_HRCAP6INT 0x9D040E //High-Res Capture Interrupt 2 +#define INT_HRCAP7INT 0x9E040F //High-Res Capture Interrupt 3 +#define INT_HRCAP8INT 0x9F0410 //High-Res Capture Interrupt 4 + +// Upper PIE Group 5 +#define INT_SDFM1INT 0xA00509 //SDFM Interrupt 1 +#define INT_SDFM2INT 0xA1050A //SDFM Interrupt 2 +#define INT_SDFM3INT 0xA2050B //SDFM Interrupt 3 +#define INT_SDFM4INT 0xA3050C //SDFM Interrupt 4 +#define INT_SDFM5INT 0xA4050D //SDFM Interrupt 5 +#define INT_SDFM6INT 0xA5050E //SDFM Interrupt 6 +#define INT_SDFM7INT 0xA6050F //SDFM Interrupt 7 +#define INT_SDFM8INT 0xA70510 //SDFM Interrupt 8 + +// Upper PIE Group 6 +#define INT_SPIRXINTC 0xA80609 //SPI-A Receive Interrupt +#define INT_SPITXINTC 0xA9060A //SPI-A Transmit Interrupt +#define INT_SPIRXINTD 0xAA060B //SPI-B Receive Interrupt +#define INT_SPITXINTD 0xAB060C //SPI-B Transmit Interrupt + +// Upper PIE Group 8 +#define INT_UPPAINT 0xBE080F //UPP-A Interrupt +#define INT_UPPBINT 0xBF0810 //UPP-B Interrupt + +// Upper PIE Group 9 +#define INT_CANCINT1 0xC00909 //CANC 1 Interrupt +#define INT_CANCINT2 0xC1090A //CANC 2 Interrupt +#define INT_CANDINT1 0xC2090B //CAND 1 Interrupt +#define INT_CANDINT2 0xC3090C //CAND 2 Interrupt +#define INT_USBAINT 0xC6090F //USBA Interrupt +#define INT_USBBINT 0xC70910 //USBB Interrupt + +// Upper PIE Group 10 +#define INT_ADCC_EVT 0xC80A09 //ADCC_EVT Interrupt +#define INT_ADCC_CH2 0xC90A0A //ADCC_CH2 Interrupt 2 +#define INT_ADCC_CH3 0xCA0A0B //ADCC_CH3 Interrupt 3 +#define INT_ADCC_CH4 0xCB0A0C //ADCC_CH4 Interrupt 4 +#define INT_ADCD_EVT 0xCC0A0D //ADCD_EVT Interrupt +#define INT_ADCD_CH2 0xCD0A0E //ADCD_CH2 Interrupt 2 +#define INT_ADCD_CH3 0xCE0A0F //ADCD_CH3 Interrupt 3 +#define INT_ADCD_CH4 0xCF0A10 //ADCD_CH4 Interrupt 4 + +// Upper PIE Group 11 +#define INT_CLA2INT1 0xD00B09 //CLA_2 Interrupt 1 +#define INT_CLA2INT2 0xD10B0A //CLA_2 Interrupt 2 +#define INT_CLA2INT3 0xD20B0B //CLA_2 Interrupt 3 +#define INT_CLA2INT4 0xD30B0C //CLA_2 Interrupt 4 +#define INT_CLA2INT5 0xD40B0D //CLA_2 Interrupt 1 +#define INT_CLA2INT6 0xD50B0E //CLA_2 Interrupt 2 +#define INT_CLA2INT7 0xD60B0F //CLA_2 Interrupt 3 +#define INT_CLA2INT8 0xD70B10 //CLA_2 Interrupt 4 + +// Upper PIE Group 12 +#define INT_EMIF_ERR 0xD80C09 //EMIF Error Interrupt +#define INT_RAM_CORR_ERR 0xD90C0A //RAM Correctable Error Interrupt +#define INT_FLASH_CORR_ERR 0xDA0C0B //Flash correctable Error Interrupt +#define INT_RAM_ACC_VIO 0xDB0C0C //RAM Access Violation Interrupt +#define INT_SYS_PLL_SLIP 0xDC0C0D //System PLL Slip Interrupt +#define INT_AUX_PLL_SLIP 0xDD0C0E //Auxillary PLL Slip Interrupt +#define INT_CLA_OF 0xDE0C0F //CLA Overflow Interrupt +#define INT_CLA_UF 0xDF0C10 //CLA Underflow Interrupt + +//Workaround for Stellaris code +#define INT_USB0 INT_USBAINT // USB 0 Controller + +//Workaround for other interrupts +#define INT_RESET 0x000000 //Reset Interrupt +#define INT_INT1 0x010000 //Not Used +#define INT_INT2 0x020000 //Not Used +#define INT_INT3 0x030000 //Not Used +#define INT_INT4 0x040000 //Not Used +#define INT_INT5 0x050000 //Not Used +#define INT_INT6 0x060000 //Not Used +#define INT_INT7 0x070000 //Not Used +#define INT_INT8 0x080000 //Not Used +#define INT_INT9 0x090000 //Not Used +#define INT_INT10 0x0A0000 //Not Used +#define INT_INT11 0x0B0000 //Not Used +#define INT_INT12 0x0C0000 //Not Used +#define INT_TINT1 0x0D0D00 //Timer Interrupt 1 +#define INT_TINT2 0x0E0E00 //Timer Interrupt 2 +#define INT_DATALOG 0x0F0F00 //CPU Data Logging Interrupt +#define INT_RTOSINT 0x101000 //CPU Real Time OS Interrupt +#define INT_EMUINT 0x110000 //CPU Emulation Interrupt +#define INT_NMI 0x120000 //External Non-Maskable Interrupt +#define INT_ILLEGAL 0x130000 //Illegal Operation +#define INT_USER1 0x140000 //User-defined +#define INT_USER2 0x150000 //User-defined +#define INT_USER3 0x160000 //User-defined +#define INT_USER4 0x170000 //User-defined +#define INT_USER5 0x180000 //User-defined +#define INT_USER6 0x190000 //User-defined +#define INT_USER7 0x1A0000 //User-defined +#define INT_USER8 0x1B0000 //User-defined +#define INT_USER9 0x1C0000 //User-defined +#define INT_USER10 0x1D0000 //User-defined +#define INT_USER11 0x1E0000 //User-defined +#define INT_USER12 0x1F0000 //User-defined + + +#endif // __HW_INTS_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h new file mode 100644 index 0000000000..94c774807a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h @@ -0,0 +1,96 @@ +//########################################################################### +// +// FILE: hw_memmap.h +// +// TITLE: Macros defining the memory map of the C28x. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** + +#define USB0_BASE 0x00040000 // USB 0 Controller + +#define ADCA_RESULT_BASE 0x00000B00 // ADC-A Result +#define ADCB_RESULT_BASE 0x00000B20 // ADC-B Result +#define ADCC_RESULT_BASE 0x00000B40 // ADC-C Result +#define ADCD_RESULT_BASE 0x00000B60 // ADC-D Result + +#define ADCA_BASE 0x00007400 // ADC-A +#define ADCB_BASE 0x00007480 // ADC-B +#define ADCC_BASE 0x00007500 // ADC-C +#define ADCD_BASE 0x00007580 // ADC-D + +#define CMPSS1_BASE 0x00005C80 // CMPSS-1 +#define CMPSS2_BASE 0x00005CA0 // CMPSS-2 +#define CMPSS3_BASE 0x00005CC0 // CMPSS-3 +#define CMPSS4_BASE 0x00005CE0 // CMPSS-4 +#define CMPSS5_BASE 0x00005D00 // CMPSS-5 +#define CMPSS6_BASE 0x00005D20 // CMPSS-6 +#define CMPSS7_BASE 0x00005D40 // CMPSS-7 +#define CMPSS8_BASE 0x00005D60 // CMPSS-8 + +#define I2CA_BASE 0x00007300 // I2C-A +#define I2CB_BASE 0x00007340 // I2C-B + +#define UARTA_BASE 0x00007200 // SCI-A +#define UARTB_BASE 0x00007210 // SCI-B +#define UARTC_BASE 0x00007220 // SCI-C +#define UARTD_BASE 0x00007230 // SCI-D + +#define EQEP1_BASE 0x00005100 // Enhanced EQEP-1 +#define EQEP2_BASE 0x00005140 // Enhanced EQEP-2 +#define EQEP3_BASE 0x00005180 // Enhanced EQEP-3 + +#define SPIA_BASE 0x00006100 // SPI-A +#define SPIB_BASE 0x00006110 // SPI-B +#define SPIC_BASE 0x00006120 // SPI-C + +#define CANA_BASE 0x00048000 // CAN-A +#define CANB_BASE 0x0004A000 // CAN-B +#define CANA_MSG_RAM 0x00049000 +#define CANB_MSG_RAM 0x0004B000 + +#endif // __HW_MEMMAP_H__ + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h new file mode 100644 index 0000000000..59edb8ce16 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h @@ -0,0 +1,88 @@ +//########################################################################### +// +// FILE: hw_types.h +// +// TITLE: Type definitions used in ALL driverlib functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define fake 8 bit types for USB related code. +// +//***************************************************************************** + +typedef uint16_t uint8_t; +typedef int16_t int8_t; + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + __byte((int *)(x),0) +//Emulated Bitbanded write +#define HWREGBITW(address, mask, value) \ + (*(volatile uint32_t *)(address)) = \ + ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \ + | ((uint32_t)value << mask) +//Emulated Bitbanded read +#define HWREGBITR(address, mask) \ + (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask) + +//Emulated Bitbanded write +#define HWREGBITHW(address, mask, value) \ + (*(volatile uint16_t *)(address)) = \ + ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \ + | ((uint16_t)value << mask) +//Emulated Bitbanded read +#define HWREGBITHR(address, mask) \ + (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask) + + + +#endif // __HW_TYPES_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h new file mode 100644 index 0000000000..c788095feb --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_uart.h +// +// TITLE: Definitions for the C28x SCI registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the SCI register offsets +// +//***************************************************************************** +#define UART_O_CCR 0x0 // Communications control register +#define UART_O_CTL1 0x1 // Control register 1 +#define UART_O_HBAUD 0x2 // Baud rate (high) register +#define UART_O_LBAUD 0x3 // Baud rate (low) register +#define UART_O_CTL2 0x4 // Control register 2 +#define UART_O_RXST 0x5 // Receive status register +#define UART_O_RXEMU 0x6 // Receive emulation buffer + // register +#define UART_O_RXBUF 0x7 // Receive data buffer +#define UART_O_TXBUF 0x9 // Transmit data buffer +#define UART_O_FFTX 0xA // FIFO transmit register +#define UART_O_FFRX 0xB // FIFO receive register +#define UART_O_FFCT 0xC // FIFO control register +#define UART_O_PRI 0xF // FIFO Priority control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCICCR register +// +//***************************************************************************** +#define UART_CCR_SCICHAR_S 0 +#define UART_CCR_SCICHAR_M 0x7 // Character length control +#define UART_CCR_ADDRIDLE_MODE 0x8 // ADDR/IDLE Mode control +#define UART_CCR_LOOPBKENA 0x10 // Loop Back enable +#define UART_CCR_PARITYENA 0x20 // Parity enable +#define UART_CCR_PARITY 0x40 // Even or Odd Parity +#define UART_CCR_STOPBITS 0x80 // Number of Stop Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCICTL1 register +// +//***************************************************************************** +#define UART_CTL1_RXENA 0x1 // SCI receiver enable +#define UART_CTL1_TXENA 0x2 // SCI transmitter enable +#define UART_CTL1_SLEEP 0x4 // SCI sleep +#define UART_CTL1_TXWAKE 0x8 // Transmitter wakeup method +#define UART_CTL1_SWRESET 0x20 // Software reset +#define UART_CTL1_RXERRINTENA 0x40 // Receive __interrupt enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIHBAUD register +// +//***************************************************************************** +#define UART_HBAUD_BAUD_S 0 +#define UART_HBAUD_BAUD_M 0xFFFF // SCI 16-bit baud selection + // Registers SCIHBAUD + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCILBAUD register +// +//***************************************************************************** +#define UART_LBAUD_BAUD_S 0 +#define UART_LBAUD_BAUD_M 0xFFFF // SCI 16-bit baud selection + // Registers SCILBAUD + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCICTL2 register +// +//***************************************************************************** +#define UART_CTL2_TXINTENA 0x1 // Transmit __interrupt enable +#define UART_CTL2_RXBKINTENA 0x2 // Receiver-buffer break enable +#define UART_CTL2_TXEMPTY 0x40 // Transmitter empty flag +#define UART_CTL2_TXRDY 0x80 // Transmitter ready flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIRXST register +// +//***************************************************************************** +#define UART_RXST_RXWAKE 0x2 // Receiver wakeup detect flag +#define UART_RXST_PE 0x4 // Parity error flag +#define UART_RXST_OE 0x8 // Overrun error flag +#define UART_RXST_FE 0x10 // Framing error flag +#define UART_RXST_BRKDT 0x20 // Break-detect flag +#define UART_RXST_RXRDY 0x40 // Receiver ready flag +#define UART_RXST_RXERROR 0x80 // Receiver error flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIRXEMU register +// +//***************************************************************************** +#define UART_RXEMU_ERXDT_S 0 +#define UART_RXEMU_ERXDT_M 0xFF // Receive emulation buffer data + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIRXBUF register +// +//***************************************************************************** +#define UART_RXBUF_SAR_S 0 +#define UART_RXBUF_SAR_M 0xFF // Receive Character bits +#define UART_RXBUF_SCIFFPE 0x4000 // Receiver error flag +#define UART_RXBUF_SCIFFFE 0x8000 // Receiver error flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCITXBUF register +// +//***************************************************************************** +#define UART_TXBUF_TXDT_S 0 +#define UART_TXBUF_TXDT_M 0xFF // Transmit data buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIFFTX register +// +//***************************************************************************** +#define UART_FFTX_TXFFIL_S 0 +#define UART_FFTX_TXFFIL_M 0x1F // Interrupt level +#define UART_FFTX_TXFFIENA 0x20 // Interrupt enable +#define UART_FFTX_TXFFINTCLR 0x40 // Clear INT flag +#define UART_FFTX_TXFFINT 0x80 // INT flag +#define UART_FFTX_TXFFST_S 8 +#define UART_FFTX_TXFFST_M 0x1F00 // FIFO status +#define UART_FFTX_TXFIFORESET 0x2000 // FIFO reset +#define UART_FFTX_SCIFFENA 0x4000 // Enhancement enable +#define UART_FFTX_SCIRST 0x8000 // SCI reset rx/tx channels + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIFFRX register +// +//***************************************************************************** +#define UART_FFRX_RXFFIL_S 0 +#define UART_FFRX_RXFFIL_M 0x1F // Interrupt level +#define UART_FFRX_RXFFIENA 0x20 // Interrupt enable +#define UART_FFRX_RXFFINTCLR 0x40 // Clear INT flag +#define UART_FFRX_RXFFINT 0x80 // INT flag +#define UART_FFRX_RXFFST_S 8 +#define UART_FFRX_RXFFST_M 0x1F00 // FIFO status +#define UART_FFRX_RXFIFORESET 0x2000 // FIFO reset +#define UART_FFRX_RXFFOVRCLR 0x4000 // Clear overflow +#define UART_FFRX_RXFFOVF 0x8000 // FIFO overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIFFCT register +// +//***************************************************************************** +#define UART_FFCT_FFTXDLY_S 0 +#define UART_FFCT_FFTXDLY_M 0xFF // FIFO transmit delay +#define UART_FFCT_CDC 0x2000 // Auto baud mode enable +#define UART_FFCT_ABDCLR 0x4000 // Auto baud clear +#define UART_FFCT_ABD 0x8000 // Auto baud detect + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIPRI register +// +//***************************************************************************** +#define UART_PRI_FREESOFT_S 3 +#define UART_PRI_FREESOFT_M 0x18 // Emulation modes +#endif diff --git a/bsp/tm4c129x-dk/libraries/inc/hw_usb.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h similarity index 55% rename from bsp/tm4c129x-dk/libraries/inc/hw_usb.h rename to bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h index 7aa3b50a29..9602cb7a15 100644 --- a/bsp/tm4c129x-dk/libraries/inc/hw_usb.h +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h @@ -2,7 +2,7 @@ // // hw_usb.h - Macros for use in accessing the USB registers. // -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// This is part of revision 9453 of the Stellaris Firmware Development Package. // //***************************************************************************** @@ -64,22 +64,21 @@ #define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 #define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 #define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 #define USB_O_DEVCTL 0x00000060 // USB Device Control -#define USB_O_CCONF 0x00000061 // USB Common Configuration #define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing #define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing #define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address #define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address -#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control -#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data -#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address -#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control -#define USB_O_EPINFO 0x00000078 // USB Endpoint Information -#define USB_O_RAMINFO 0x00000079 // USB RAM Information #define USB_O_CONTIM 0x0000007A // USB Connect Timing #define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing -#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction - // to End of Frame Timing #define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction // to End of Frame Timing #define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction @@ -159,6 +158,92 @@ #define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint // 7 #define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 #define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint // 0 Low #define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint @@ -321,31 +406,182 @@ // Endpoint 7 #define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling // Interval Endpoint 7 -#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt -#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0 -#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0 -#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0 -#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1 -#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1 -#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1 -#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2 -#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2 -#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2 -#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3 -#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3 -#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3 -#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4 -#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4 -#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4 -#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5 -#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5 -#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5 -#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6 -#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6 -#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6 -#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7 -#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7 -#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 #define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in // Block Transfer Endpoint 1 #define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in @@ -360,19 +596,26 @@ // Block Transfer Endpoint 6 #define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 #define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer // Disable #define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet // Buffer Disable -#define USB_O_CTO 0x00000344 // USB Chirp Timeout -#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating - // Delay -#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder -#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes -#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control -#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask -#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status -#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address #define USB_O_EPC 0x00000400 // USB External Power Control #define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw // Interrupt Status @@ -402,8 +645,6 @@ // Status and Clear #define USB_O_DMASEL 0x00000450 // USB DMA Select #define USB_O_PP 0x00000FC0 // USB Peripheral Properties -#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration -#define USB_O_CC 0x00000FC8 // USB Clock Configuration //***************************************************************************** // @@ -420,8 +661,6 @@ //***************************************************************************** #define USB_POWER_ISOUP 0x00000080 // Isochronous Update #define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x00000020 // High Speed Enable -#define USB_POWER_HSMODE 0x00000010 // High Speed Enable #define USB_POWER_RESET 0x00000008 // RESET Signaling #define USB_POWER_RESUME 0x00000004 // RESUME Signaling #define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode @@ -432,6 +671,14 @@ // The following are defines for the bit fields in the USB_O_TXIS register. // //***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt #define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt #define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt #define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt @@ -446,6 +693,14 @@ // The following are defines for the bit fields in the USB_O_RXIS register. // //***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt #define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt #define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt #define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt @@ -459,6 +714,14 @@ // The following are defines for the bit fields in the USB_O_TXIE register. // //***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable #define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable #define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable #define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable @@ -474,6 +737,14 @@ // The following are defines for the bit fields in the USB_O_RXIE register. // //***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable #define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable #define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable #define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable @@ -487,9 +758,9 @@ // The following are defines for the bit fields in the USB_O_IS register. // //***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_VBUSERR 0x00000080 // VBUS Error +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST +#define USB_IS_DISCON 0x00000020 // Session Disconnect #define USB_IS_CONN 0x00000010 // Session Connect #define USB_IS_SOF 0x00000008 // Start of Frame #define USB_IS_BABBLE 0x00000004 // Babble Detected @@ -502,10 +773,8 @@ // The following are defines for the bit fields in the USB_O_IE register. // //***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG - // only) -#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG - // only) +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt +#define USB_IE_SESREQ 0x00000040 // Enable Session Request #define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt #define USB_IE_CONN 0x00000010 // Enable Connect Interrupt #define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt @@ -538,11 +807,6 @@ #define USB_TEST_FORCEH 0x00000080 // Force Host Mode #define USB_TEST_FIFOACC 0x00000040 // FIFO Access #define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable //***************************************************************************** // @@ -608,30 +872,86 @@ #define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data #define USB_FIFO7_EPDATA_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO15_EPDATA_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DEVCTL register. // //***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_DEV 0x00000080 // Device Mode #define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected #define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level #define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd #define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid #define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid #define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid #define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CCONF register. -// -//***************************************************************************** -#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End //***************************************************************************** // @@ -685,67 +1005,6 @@ #define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address #define USB_RXFIFOADD_ADDR_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL -// register. -// -//***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ - 0x00000002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS \ - 0x00000001 // Use External VBUS - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGDATA -// register. -// -//***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M \ - 0x000000FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S \ - 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGADDR -// register. -// -//***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address -#define USB_ULPIREGADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_ULPIREGCTL -// register. -// -//***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPINFO register. -// -//***************************************************************************** -#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints -#define USB_EPINFO_RXEP_S 4 -#define USB_EPINFO_TXEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RAMINFO register. -// -//***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width -#define USB_RAMINFO_DMACHAN_S 4 -#define USB_RAMINFO_RAMBITS_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CONTIM register. @@ -764,14 +1023,6 @@ #define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length #define USB_VPLEN_VPLEN_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSEOF register. -// -//***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap -#define USB_HSEOF_HSEOFG_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FSEOF register. @@ -1193,6 +1444,438 @@ #define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port #define USB_RXHUBPORT7_PORT_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT15_PORT_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CSRL0 register. @@ -1217,7 +1900,6 @@ // The following are defines for the bit fields in the USB_O_CSRH0 register. // //***************************************************************************** -#define USB_CSRH0_DISPING 0x00000008 // PING Disable #define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable #define USB_CSRH0_DT 0x00000002 // Data Toggle #define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO @@ -1236,7 +1918,6 @@ // //***************************************************************************** #define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x00000040 // High #define USB_TYPE0_SPEED_FULL 0x00000080 // Full #define USB_TYPE0_SPEED_LOW 0x000000C0 // Low @@ -1325,8 +2006,6 @@ #define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH1_DT 0x00000002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -1343,7 +2022,6 @@ //***************************************************************************** #define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol @@ -1360,13 +2038,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ +#define USB_TXINTERVAL1_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ +#define USB_TXINTERVAL1_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ +#define USB_TXINTERVAL1_TXPOLL_S \ 0 -#define USB_TXINTERVAL1_NAKLMT_S \ +#define USB_TXINTERVAL1_NAKLMT_S \ 0 //***************************************************************************** @@ -1376,7 +2054,6 @@ //***************************************************************************** #define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol @@ -1393,13 +2070,13 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ +#define USB_RXINTERVAL1_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ +#define USB_RXINTERVAL1_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ +#define USB_RXINTERVAL1_TXPOLL_S \ 0 -#define USB_RXINTERVAL1_NAKLMT_S \ +#define USB_RXINTERVAL1_NAKLMT_S \ 0 //***************************************************************************** @@ -1479,8 +2156,6 @@ #define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH2_DT 0x00000002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -1497,7 +2172,6 @@ //***************************************************************************** #define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol @@ -1514,13 +2188,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ +#define USB_TXINTERVAL2_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ +#define USB_TXINTERVAL2_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ +#define USB_TXINTERVAL2_NAKLMT_S \ 0 -#define USB_TXINTERVAL2_TXPOLL_S \ +#define USB_TXINTERVAL2_TXPOLL_S \ 0 //***************************************************************************** @@ -1530,7 +2204,6 @@ //***************************************************************************** #define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol @@ -1547,13 +2220,13 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ +#define USB_RXINTERVAL2_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ +#define USB_RXINTERVAL2_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ +#define USB_RXINTERVAL2_TXPOLL_S \ 0 -#define USB_RXINTERVAL2_NAKLMT_S \ +#define USB_RXINTERVAL2_NAKLMT_S \ 0 //***************************************************************************** @@ -1633,8 +2306,6 @@ #define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH3_DT 0x00000002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -1651,7 +2322,6 @@ //***************************************************************************** #define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol @@ -1668,13 +2338,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ +#define USB_TXINTERVAL3_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ +#define USB_TXINTERVAL3_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ +#define USB_TXINTERVAL3_TXPOLL_S \ 0 -#define USB_TXINTERVAL3_NAKLMT_S \ +#define USB_TXINTERVAL3_NAKLMT_S \ 0 //***************************************************************************** @@ -1684,7 +2354,6 @@ //***************************************************************************** #define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol @@ -1701,13 +2370,13 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ +#define USB_RXINTERVAL3_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ +#define USB_RXINTERVAL3_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ +#define USB_RXINTERVAL3_TXPOLL_S \ 0 -#define USB_RXINTERVAL3_NAKLMT_S \ +#define USB_RXINTERVAL3_NAKLMT_S \ 0 //***************************************************************************** @@ -1787,8 +2456,6 @@ #define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH4_DT 0x00000002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -1805,7 +2472,6 @@ //***************************************************************************** #define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol @@ -1822,13 +2488,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ +#define USB_TXINTERVAL4_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ +#define USB_TXINTERVAL4_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ +#define USB_TXINTERVAL4_NAKLMT_S \ 0 -#define USB_TXINTERVAL4_TXPOLL_S \ +#define USB_TXINTERVAL4_TXPOLL_S \ 0 //***************************************************************************** @@ -1838,7 +2504,6 @@ //***************************************************************************** #define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol @@ -1855,13 +2520,13 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ +#define USB_RXINTERVAL4_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ +#define USB_RXINTERVAL4_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ +#define USB_RXINTERVAL4_NAKLMT_S \ 0 -#define USB_RXINTERVAL4_TXPOLL_S \ +#define USB_RXINTERVAL4_TXPOLL_S \ 0 //***************************************************************************** @@ -1941,8 +2606,6 @@ #define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH5_DT 0x00000002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -1959,7 +2622,6 @@ //***************************************************************************** #define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol @@ -1976,13 +2638,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ +#define USB_TXINTERVAL5_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ +#define USB_TXINTERVAL5_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ +#define USB_TXINTERVAL5_NAKLMT_S \ 0 -#define USB_TXINTERVAL5_TXPOLL_S \ +#define USB_TXINTERVAL5_TXPOLL_S \ 0 //***************************************************************************** @@ -1992,7 +2654,6 @@ //***************************************************************************** #define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol @@ -2009,13 +2670,13 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ +#define USB_RXINTERVAL5_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ +#define USB_RXINTERVAL5_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ +#define USB_RXINTERVAL5_TXPOLL_S \ 0 -#define USB_RXINTERVAL5_NAKLMT_S \ +#define USB_RXINTERVAL5_NAKLMT_S \ 0 //***************************************************************************** @@ -2095,8 +2756,6 @@ #define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH6_DT 0x00000002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -2113,7 +2772,6 @@ //***************************************************************************** #define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol @@ -2130,13 +2788,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ +#define USB_TXINTERVAL6_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ +#define USB_TXINTERVAL6_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ +#define USB_TXINTERVAL6_TXPOLL_S \ 0 -#define USB_TXINTERVAL6_NAKLMT_S \ +#define USB_TXINTERVAL6_NAKLMT_S \ 0 //***************************************************************************** @@ -2146,7 +2804,6 @@ //***************************************************************************** #define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol @@ -2163,13 +2820,13 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ +#define USB_RXINTERVAL6_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ +#define USB_RXINTERVAL6_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ +#define USB_RXINTERVAL6_NAKLMT_S \ 0 -#define USB_RXINTERVAL6_TXPOLL_S \ +#define USB_RXINTERVAL6_TXPOLL_S \ 0 //***************************************************************************** @@ -2249,8 +2906,6 @@ #define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode #define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable #define USB_RXCSRH7_DT 0x00000002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission - // Status //***************************************************************************** // @@ -2267,7 +2922,6 @@ //***************************************************************************** #define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed #define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High #define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full #define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low #define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol @@ -2284,13 +2938,13 @@ // register. // //***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ +#define USB_TXINTERVAL7_TXPOLL_M \ 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ +#define USB_TXINTERVAL7_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ +#define USB_TXINTERVAL7_NAKLMT_S \ 0 -#define USB_TXINTERVAL7_TXPOLL_S \ +#define USB_TXINTERVAL7_TXPOLL_S \ 0 //***************************************************************************** @@ -2300,7 +2954,6 @@ //***************************************************************************** #define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed #define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High #define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full #define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low #define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol @@ -2317,324 +2970,1220 @@ // register. // //***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ +#define USB_RXINTERVAL7_TXPOLL_M \ 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ +#define USB_RXINTERVAL7_NAKLMT_M \ 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ +#define USB_RXINTERVAL7_NAKLMT_S \ 0 -#define USB_RXINTERVAL7_TXPOLL_S \ +#define USB_RXINTERVAL7_TXPOLL_S \ 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAINTR register. +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. // //***************************************************************************** -#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP8_MAXLOAD_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. // //***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x00000002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL0_EP_S 4 +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL8_STALL 0x00000010 // Send STALL +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL8_ERROR 0x00000004 // Error +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. // //***************************************************************************** -#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR0_ADDR_S 2 +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH8_MODE 0x00000020 // Mode +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL8_STALL 0x00000020 // Send STALL +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL8_OVER 0x00000004 // Overrun +#define USB_RXCSRL8_ERROR 0x00000004 // Error +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 // register. // //***************************************************************************** -#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT0_COUNT_S 2 +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. // //***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x00000002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL1_EP_S 4 +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE8_TEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR1 register. -// -//***************************************************************************** -#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR1_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 // register. // //***************************************************************************** -#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT1_COUNT_S 2 +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. // //***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x00000002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL2_EP_S 4 +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP9_MAXLOAD_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. // //***************************************************************************** -#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR2_ADDR_S 2 +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL9_STALL 0x00000010 // Send STALL +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL9_ERROR 0x00000004 // Error +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH9_MODE 0x00000020 // Mode +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL9_STALL 0x00000020 // Send STALL +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL9_ERROR 0x00000004 // Error +#define USB_RXCSRL9_OVER 0x00000004 // Overrun +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 // register. // //***************************************************************************** -#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT2_COUNT_S 2 +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. // //***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x00000002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL3_EP_S 4 +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE9_TEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR3 register. -// -//***************************************************************************** -#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR3_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 // register. // //***************************************************************************** -#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT3_COUNT_S 2 +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. // //***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x00000002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL4_EP_S 4 +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP10_MAXLOAD_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. // //***************************************************************************** -#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR4_ADDR_S 2 +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL10_STALL 0x00000010 // Send STALL +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL10_ERROR 0x00000004 // Error +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH10_MODE 0x00000020 // Mode +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL10_STALL 0x00000020 // Send STALL +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL10_OVER 0x00000004 // Overrun +#define USB_RXCSRL10_ERROR 0x00000004 // Error +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 // register. // //***************************************************************************** -#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT4_COUNT_S 2 +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT10_COUNT_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. // //***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x00000002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL5_EP_S 4 +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE10_TEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR5 register. -// -//***************************************************************************** -#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR5_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 // register. // //***************************************************************************** -#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT5_COUNT_S 2 +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. // //***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x00000002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL6_EP_S 4 +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE10_TEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR6 register. -// -//***************************************************************************** -#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR6_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 // register. // //***************************************************************************** -#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT6_COUNT_S 2 +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. // //***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x00000002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable -#define USB_DMACTL7_EP_S 4 +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP11_MAXLOAD_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. // //***************************************************************************** -#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR7_ADDR_S 2 +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL11_STALL 0x00000010 // Send STALL +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL11_ERROR 0x00000004 // Error +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH11_MODE 0x00000020 // Mode +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL11_STALL 0x00000020 // Send STALL +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL11_OVER 0x00000004 // Overrun +#define USB_RXCSRL11_ERROR 0x00000004 // Error +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 // register. // //***************************************************************************** -#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT7_COUNT_S 2 +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL12_STALL 0x00000010 // Send STALL +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL12_ERROR 0x00000004 // Error +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH12_MODE 0x00000020 // Mode +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL12_STALL 0x00000020 // Send STALL +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL12_ERROR 0x00000004 // Error +#define USB_RXCSRL12_OVER 0x00000004 // Overrun +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL13_STALL 0x00000010 // Send STALL +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL13_ERROR 0x00000004 // Error +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH13_MODE 0x00000020 // Mode +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL13_STALL 0x00000020 // Send STALL +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL13_OVER 0x00000004 // Overrun +#define USB_RXCSRL13_ERROR 0x00000004 // Error +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL14_STALL 0x00000010 // Send STALL +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL14_ERROR 0x00000004 // Error +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH14_MODE 0x00000020 // Mode +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL14_STALL 0x00000020 // Send STALL +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL14_OVER 0x00000004 // Overrun +#define USB_RXCSRL14_ERROR 0x00000004 // Error +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL15_STALL 0x00000010 // Send STALL +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL15_ERROR 0x00000004 // Error +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH15_MODE 0x00000020 // Mode +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL15_STALL 0x00000020 // Send STALL +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL15_ERROR 0x00000004 // Error +#define USB_RXCSRL15_OVER 0x00000004 // Overrun +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 //***************************************************************************** // @@ -2699,12 +4248,112 @@ #define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT7_COUNT_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS // register. // //***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable #define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer // Disable #define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer @@ -2726,6 +4375,22 @@ // register. // //***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable #define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer // Disable #define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer @@ -2741,101 +4406,6 @@ #define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer // Disable -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CTO register. -// -//***************************************************************************** -#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value -#define USB_CTO_CCTV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HHSRTN register. -// -//***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating - // Delay -#define USB_HHSRTN_HHSRTN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSBT register. -// -//***************************************************************************** -#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder -#define USB_HSBT_HSBT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMATTR register. -// -//***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x0000000F // Link State -#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMCNTRL register. -// -//***************************************************************************** -#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions - // are not supported. In this case, - // the USB does not respond to LPM - // transactions and LPM - // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but - // extended transactions are - // supported. In this case, the USB - // does respond to an LPM - // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended - // transactions. In this case, the - // USB responds with a NYET or an - // ACK as determined by the value - // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMIM register. -// -//***************************************************************************** -#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMRIS register. -// -//***************************************************************************** -#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMFADDR register. -// -//***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address -#define USB_LPMFADDR_ADDR_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPC register. @@ -2855,9 +4425,7 @@ #define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low #define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High #define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low - // (OTG only) #define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High - // (OTG only) //***************************************************************************** // @@ -2908,15 +4476,6 @@ // The following are defines for the bit fields in the USB_O_GPCS register. // //***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high -#define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x00000004 // Use USB0VBUS and force USB0ID - // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID - // high #define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode #define USB_GPCS_DEVMOD 0x00000001 // Device Mode @@ -3000,33 +4559,53 @@ #define USB_PP_USB_DEVICE 0x00000040 // DEVICE #define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST #define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_ULPI 0x00000020 // ULPI Present #define USB_PP_PHY 0x00000010 // PHY Present #define USB_PP_TYPE_M 0x0000000F // Controller Type #define USB_PP_TYPE_0 0x00000000 // The first-generation USB // controller -#define USB_PP_TYPE_1 0x00000001 // Second-generation USB - // controller.The controller - // implemented in post Icestorm - // devices that use the 3.0 version - // of the Mentor controller #define USB_PP_ECNT_S 8 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_PC register. +// The following definitions are deprecated. // //***************************************************************************** -#define USB_PC_ULPIEN 0x00010000 // ULPI Enable +#ifndef DEPRECATED //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_CC register. +// The following are deprecated defines for the bit fields in the +// USB_O_TXFIFOADD register. // //***************************************************************************** -#define USB_CC_CLKEN 0x00000200 // USB Clock Enable -#define USB_CC_CSD 0x00000100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor -#define USB_CC_CLKDIV_S 0 +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_RXFIFOADD register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 + +#endif #endif // __HW_USB_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c new file mode 100644 index 0000000000..a58927013e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c @@ -0,0 +1,214 @@ +//########################################################################### +// +// FILE: cmdline.c +// +// TITLE: Functions to help with processing command lines. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup cmdline_api +//! @{ +// +//***************************************************************************** + +// +// Included Files +// +#include +#include +#include +#include "utils/cmdline.h" + +// +// Defines the maximum number of arguments that can be parsed. +// +#ifndef CMDLINE_MAX_ARGS +#define CMDLINE_MAX_ARGS 8 +#endif + +// +// An array to hold the pointers to the command line arguments. +// +static char *g_ppcArgv[CMDLINE_MAX_ARGS + 1]; + +//***************************************************************************** +// +//! Process a command line string into arguments and execute the command. +//! +//! \param pcCmdLine points to a string that contains a command line that was +//! obtained by an application by some means. +//! +//! This function will take the supplied command line string and break it up +//! into individual arguments. The first argument is treated as a command and +//! is searched for in the command table. If the command is found, then the +//! command function is called and all of the command line arguments are passed +//! in the normal argc, argv form. +//! +//! The command table is contained in an array named g_psCmdTable +//! containing tCmdLineEntry structures which must be provided by the +//! application. The array must be terminated with an entry whose \b pcCmd +//! field contains a NULL pointer. +//! +//! \return Returns \b CMDLINE_BAD_CMD if the command is not found, +//! \b CMDLINE_TOO_MANY_ARGS if there are more arguments than can be parsed. +//! Otherwise it returns the code that was returned by the command function. +// +//***************************************************************************** +int +CmdLineProcess(char *pcCmdLine) +{ + char *pcChar; + uint_fast8_t ui8Argc; + bool bFindArg = true; + tCmdLineEntry *psCmdEntry; + + // + // Initialize the argument counter, and point to the beginning of the + // command line string. + // + ui8Argc = 0; + pcChar = pcCmdLine; + + // + // Advance through the command line until a zero character is found. + // + while(*pcChar) + { + // + // If there is a space, then replace it with a zero, and set the flag + // to search for the next argument. + // + if(*pcChar == ' ') + { + *pcChar = 0; + bFindArg = true; + } + + // + // Otherwise it is not a space, so it must be a character that is part + // of an argument. + // + else + { + // + // If bFindArg is set, then that means we are looking for the start + // of the next argument. + // + if(bFindArg) + { + // + // As long as the maximum number of arguments has not been + // reached, then save the pointer to the start of this new arg + // in the argv array, and increment the count of args, argc. + // + if(ui8Argc < CMDLINE_MAX_ARGS) + { + g_ppcArgv[ui8Argc] = pcChar; + ui8Argc++; + bFindArg = false; + } + + // + // The maximum number of arguments has been reached so return + // the error. + // + else + { + return(CMDLINE_TOO_MANY_ARGS); + } + } + } + + // + // Advance to the next character in the command line. + // + pcChar++; + } + + // + // If one or more arguments was found, then process the command. + // + if(ui8Argc) + { + // + // Start at the beginning of the command table, to look for a matching + // command. + // + psCmdEntry = &g_psCmdTable[0]; + + // + // Search through the command table until a null command string is + // found, which marks the end of the table. + // + while(psCmdEntry->pcCmd) + { + // + // If this command entry command string matches argv[0], then call + // the function for this command, passing the command line + // arguments. + // + if(!strcmp(g_ppcArgv[0], psCmdEntry->pcCmd)) + { + return(psCmdEntry->pfnCmd(ui8Argc, g_ppcArgv)); + } + + // + // Not found, so advance to the next entry. + // + psCmdEntry++; + } + } + + // + // Fall through to here means that no matching command was found, so return + // an error. + // + return(CMDLINE_BAD_CMD); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h new file mode 100644 index 0000000000..47c3fa1b23 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h @@ -0,0 +1,143 @@ +//########################################################################### +// +// FILE: cmdline.h +// +// TITLE: Prototypes for command line processing functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __CMDLINE_H__ +#define __CMDLINE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cmdline_api +//! @{ +// +//***************************************************************************** + +// +//! Defines the value that is returned if the command is not found. +// +#define CMDLINE_BAD_CMD (-1) + +// +//! Defines the value that is returned if there are too many arguments. +// +#define CMDLINE_TOO_MANY_ARGS (-2) + +// +//! Defines the value that is returned if there are too few arguments. +// +#define CMDLINE_TOO_FEW_ARGS (-3) + +// +//! Defines the value that is returned if an argument is invalid. +// +#define CMDLINE_INVALID_ARG (-4) + +// +// Command line function callback type. +// +typedef int (*pfnCmdLine)(int argc, char *argv[]); + +// +//! Structure for an entry in the command list table. +// +typedef struct +{ + // + //! A pointer to a string containing the name of the command. + // + const char *pcCmd; + + // + //! A function pointer to the implementation of the command. + // + pfnCmdLine pfnCmd; + + // + //! A pointer to a string of brief help text for the command. + // + const char *pcHelp; +} +tCmdLineEntry; + +// +//! This is the command table that must be provided by the application. The +//! last element of the array must be a structure whose pcCmd field contains +//! a NULL pointer. +// +extern tCmdLineEntry g_psCmdTable[]; + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// Function Prototypes +// +extern int CmdLineProcess(char *pcCmdLine); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CMDLINE_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c new file mode 100644 index 0000000000..07354f184d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c @@ -0,0 +1,1773 @@ +//########################################################################### +// +// FILE: uartstdio.c +// +// TITLE: Utility driver to provide simple UART console functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/rom.h" +#include "driverlib/rom_map.h" +#include "driverlib/sysctl.h" +#include "driverlib/uart.h" +#include "utils/uartstdio.h" + +//***************************************************************************** +// +//! \addtogroup uartstdio_api +//! @{ +// +//***************************************************************************** + +// +// If buffered mode is defined, set aside RX and TX buffers and read/write +// pointers to control them. +// +#ifdef UART_BUFFERED + +// +// This global controls whether or not we are echoing characters back to the +// transmitter. By default, echo is enabled but if using this module as a +// convenient method of implementing a buffered serial interface over which +// you will be running an application protocol, you are likely to want to +// disable echo by calling UARTEchoSet(false). +// +static bool g_bDisableEcho; + +// +// Output ring buffer. Buffer is full if g_ui32UARTTxReadIndex is one ahead of +// g_ui32UARTTxWriteIndex. Buffer is empty if the two indices are the same. +// +static unsigned char g_pcUARTTxBuffer[UART_TX_BUFFER_SIZE]; +static volatile uint32_t g_ui32UARTTxWriteIndex = 0; +static volatile uint32_t g_ui32UARTTxReadIndex = 0; + +// +// Input ring buffer. Buffer is full if g_ui32UARTTxReadIndex is one ahead of +// g_ui32UARTTxWriteIndex. Buffer is empty if the two indices are the same. +// +static unsigned char g_pcUARTRxBuffer[UART_RX_BUFFER_SIZE]; +static volatile uint32_t g_ui32UARTRxWriteIndex = 0; +static volatile uint32_t g_ui32UARTRxReadIndex = 0; + +// +// Macros to determine number of free and used bytes in the transmit buffer. +// +#define TX_BUFFER_USED (GetBufferCount(&g_ui32UARTTxReadIndex, \ + &g_ui32UARTTxWriteIndex, \ + UART_TX_BUFFER_SIZE)) +#define TX_BUFFER_FREE (UART_TX_BUFFER_SIZE - TX_BUFFER_USED) +#define TX_BUFFER_EMPTY (IsBufferEmpty(&g_ui32UARTTxReadIndex, \ + &g_ui32UARTTxWriteIndex)) +#define TX_BUFFER_FULL (IsBufferFull(&g_ui32UARTTxReadIndex, \ + &g_ui32UARTTxWriteIndex, \ + UART_TX_BUFFER_SIZE)) +#define ADVANCE_TX_BUFFER_INDEX(Index) \ + (Index) = ((Index) + 1) % UART_TX_BUFFER_SIZE + +// +// Macros to determine number of free and used bytes in the receive buffer. +// +#define RX_BUFFER_USED (GetBufferCount(&g_ui32UARTRxReadIndex, \ + &g_ui32UARTRxWriteIndex, \ + UART_RX_BUFFER_SIZE)) +#define RX_BUFFER_FREE (UART_RX_BUFFER_SIZE - RX_BUFFER_USED) +#define RX_BUFFER_EMPTY (IsBufferEmpty(&g_ui32UARTRxReadIndex, \ + &g_ui32UARTRxWriteIndex)) +#define RX_BUFFER_FULL (IsBufferFull(&g_ui32UARTRxReadIndex, \ + &g_ui32UARTRxWriteIndex, \ + UART_RX_BUFFER_SIZE)) +#define ADVANCE_RX_BUFFER_INDEX(Index) \ + (Index) = ((Index) + 1) % UART_RX_BUFFER_SIZE +#endif + +// +// The base address of the chosen UART. +// +static uint32_t g_ui32Base = 0; + +// +// A mapping from an integer between 0 and 15 to its ASCII character +// equivalent. +// +static const char * const g_pcHex = "0123456789abcdef"; + +// +// The list of possible base addresses for the console UART. +// +static const uint32_t g_ui32UARTBase[4] = +{ + UARTA_BASE, UARTB_BASE, UARTC_BASE, UARTD_BASE +}; + +#ifdef UART_BUFFERED +// +// The list of possible interrupts for the console UART. +// +static const uint32_t g_ui32UARTInt[3] = +{ + INT_UART0, INT_UART1, INT_UART2 +}; + +// +// The port number in use. +// +static uint32_t g_ui32PortNum; +#endif + +// +// The list of UART peripherals. +// +static const uint32_t g_ui32UARTPeriph[3] = +{ + SYSCTL_PERIPH_SCI1, SYSCTL_PERIPH_SCI2, SYSCTL_PERIPH_SCI3 +}; + +//***************************************************************************** +// +//! Determines whether the ring buffer whose pointers and size are provided +//! is full or not. +//! +//! \param pui32Read points to the read index for the buffer. +//! \param pui32Write points to the write index for the buffer. +//! \param ui32Size is the size of the buffer in bytes. +//! +//! This function is used to determine whether or not a given ring buffer is +//! full. The structure of the code is specifically to ensure that we do not +//! see warnings from the compiler related to the order of volatile accesses +//! being undefined. +//! +//! \return Returns \b true if the buffer is full or \b false otherwise. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static bool +IsBufferFull(volatile uint32_t *pui32Read, + volatile uint32_t *pui32Write, uint32_t ui32Size) +{ + uint32_t ui32Write; + uint32_t ui32Read; + + ui32Write = *pui32Write; + ui32Read = *pui32Read; + + return((((ui32Write + 1) % ui32Size) == ui32Read) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Determines whether the ring buffer whose pointers and size are provided +//! is empty or not. +//! +//! \param pui32Read points to the read index for the buffer. +//! \param pui32Write points to the write index for the buffer. +//! +//! This function is used to determine whether or not a given ring buffer is +//! empty. The structure of the code is specifically to ensure that we do not +//! see warnings from the compiler related to the order of volatile accesses +//! being undefined. +//! +//! \return Returns \b true if the buffer is empty or \b false otherwise. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static bool +IsBufferEmpty(volatile uint32_t *pui32Read, + volatile uint32_t *pui32Write) +{ + uint32_t ui32Write; + uint32_t ui32Read; + + ui32Write = *pui32Write; + ui32Read = *pui32Read; + + return((ui32Write == ui32Read) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Determines the number of bytes of data contained in a ring buffer. +//! +//! \param pui32Read points to the read index for the buffer. +//! \param pui32Write points to the write index for the buffer. +//! \param ui32Size is the size of the buffer in bytes. +//! +//! This function is used to determine how many bytes of data a given ring +//! buffer currently contains. The structure of the code is specifically to +//! ensure that we do not see warnings from the compiler related to the order +//! of volatile accesses being undefined. +//! +//! \return Returns the number of bytes of data currently in the buffer. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static uint32_t +GetBufferCount(volatile uint32_t *pui32Read, + volatile uint32_t *pui32Write, uint32_t ui32Size) +{ + uint32_t ui32Write; + uint32_t ui32Read; + + ui32Write = *pui32Write; + ui32Read = *pui32Read; + + return((ui32Write >= ui32Read) ? (ui32Write - ui32Read) : + (ui32Size - (ui32Read - ui32Write))); +} +#endif + +//***************************************************************************** +// +// Take as many bytes from the transmit buffer as we have space for and move +// them into the UART transmit FIFO. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static void +UARTPrimeTransmit(uint32_t ui32Base) +{ + // + // Do we have any data to transmit? + // + if(!TX_BUFFER_EMPTY) + { + // + // Disable the UART interrupt. If we don't do this there is a race + // condition which can cause the read index to be corrupted. + // + MAP_IntDisable(g_ui32UARTInt[g_ui32PortNum]); + + // + // Yes - take some characters out of the transmit buffer and feed + // them to the UART transmit FIFO. + // + while(MAP_UARTSpaceAvail(ui32Base) && !TX_BUFFER_EMPTY) + { + MAP_UARTCharPutNonBlocking(ui32Base, + g_pcUARTTxBuffer[g_ui32UARTTxReadIndex]); + ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxReadIndex); + } + + // + // Reenable the UART interrupt. + // + MAP_IntEnable(g_ui32UARTInt[g_ui32PortNum]); + } +} +#endif + +//***************************************************************************** +// +//! Configures the UART console. +//! +//! \param ui32PortNum is the number of UART port to use for the serial console +//! (0-2) +//! \param ui32Baud is the bit rate that the UART is to be configured to use. +//! \param ui32SrcClock is the frequency of the source clock for the UART +//! module. +//! +//! This function will configure the specified serial port to be used as a +//! serial console. The serial parameters are set to the baud rate +//! specified by the \e ui32Baud parameter and use 8 bit, no parity, and 1 stop +//! bit. +//! +//! This function must be called prior to using any of the other UART console +//! functions: UARTprintf() or UARTgets(). This function assumes that the +//! caller has previously configured the relevant UART pins for operation as a +//! UART rather than as GPIOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTStdioConfig(uint32_t ui32PortNum, uint32_t ui32Baud, uint32_t ui32SrcClock) +{ + // + // Check the arguments. + // + ASSERT((ui32PortNum == 0) || (ui32PortNum == 1) || + (ui32PortNum == 2)); + +#ifdef UART_BUFFERED + // + // In buffered mode, we only allow a single instance to be opened. + // + ASSERT(g_ui32Base == 0); +#endif + + // + // Check to make sure the UART peripheral is present. + // + if(!MAP_SysCtlPeripheralPresent(g_ui32UARTPeriph[ui32PortNum])) + { + return; + } + + // + // Select the base address of the UART. + // + g_ui32Base = g_ui32UARTBase[ui32PortNum]; + + // + // Enable the UART peripheral for use. + // + MAP_SysCtlPeripheralEnable(g_ui32UARTPeriph[ui32PortNum]); + + // + // Configure the UART for 115200, n, 8, 1 + // + MAP_UARTConfigSetExpClk(g_ui32Base, ui32SrcClock, ui32Baud, + (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | + UART_CONFIG_WLEN_8)); + +#ifdef UART_BUFFERED + // + // Set the UART to interrupt whenever the TX FIFO is almost empty or + // when any character is received. + // + MAP_UARTFIFOLevelSet(g_ui32Base, UART_FIFO_TX1_8, UART_FIFO_RX1_8); + + // + // Flush both the buffers. + // + UARTFlushRx(); + UARTFlushTx(true); + + // + // Remember which interrupt we are dealing with. + // + g_ui32PortNum = ui32PortNum; + + // + // We are configured for buffered output so enable the master interrupt + // for this UART and the receive interrupts. We don't actually enable the + // transmit interrupt in the UART itself until some data has been placed + // in the transmit buffer. + // + MAP_UARTIntDisable(g_ui32Base, 0xFFFFFFFF); + MAP_UARTIntEnable(g_ui32Base, UART_INT_RX | UART_INT_RT); + MAP_IntEnable(g_ui32UARTInt[ui32PortNum]); +#endif + + // + // Enable the UART operation. + // + MAP_UARTEnable(g_ui32Base); +} + +//***************************************************************************** +// +//! Writes a string of characters to the UART output. +//! +//! \param pcBuf points to a buffer containing the string to transmit. +//! \param ui32Len is the length of the string to transmit. +//! +//! This function will transmit the string to the UART output. The number of +//! characters transmitted is determined by the \e ui32Len parameter. This +//! function does no interpretation or translation of any characters. Since +//! the output is sent to a UART, any LF (/n) characters encountered will be +//! replaced with a CRLF pair. +//! +//! Besides using the \e ui32Len parameter to stop transmitting the string, if +//! a null character (0) is encountered, then no more characters will be +//! transmitted and the function will return. +//! +//! In non-buffered mode, this function is blocking and will not return until +//! all the characters have been written to the output FIFO. In buffered mode, +//! the characters are written to the UART transmit buffer and the call returns +//! immediately. If insufficient space remains in the transmit buffer, +//! additional characters are discarded. +//! +//! \return Returns the count of characters written. +// +//***************************************************************************** +int +UARTwrite(const char *pcBuf, uint32_t ui32Len) +{ +#ifdef UART_BUFFERED + unsigned int uIdx; + + // + // Check for valid arguments. + // + ASSERT(pcBuf != 0); + ASSERT(g_ui32Base != 0); + + // + // Send the characters + // + for(uIdx = 0; uIdx < ui32Len; uIdx++) + { + // + // If the character to the UART is \n, then add a \r before it so that + // \n is translated to \n\r in the output. + // + if(pcBuf[uIdx] == '\n') + { + if(!TX_BUFFER_FULL) + { + g_pcUARTTxBuffer[g_ui32UARTTxWriteIndex] = '\r'; + ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxWriteIndex); + } + else + { + // + // Buffer is full - discard remaining characters and return. + // + break; + } + } + + // + // Send the character to the UART output. + // + if(!TX_BUFFER_FULL) + { + g_pcUARTTxBuffer[g_ui32UARTTxWriteIndex] = pcBuf[uIdx]; + ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxWriteIndex); + } + else + { + // + // Buffer is full - discard remaining characters and return. + // + break; + } + } + + // + // If we have anything in the buffer, make sure that the UART is set + // up to transmit it. + // + if(!TX_BUFFER_EMPTY) + { + UARTPrimeTransmit(g_ui32Base); + MAP_UARTIntEnable(g_ui32Base, UART_INT_TX); + } + + // + // Return the number of characters written. + // + return(uIdx); +#else + unsigned int uIdx; + + // + // Check for valid UART base address, and valid arguments. + // + ASSERT(g_ui32Base != 0); + ASSERT(pcBuf != 0); + + // + // Send the characters + // + for(uIdx = 0; uIdx < ui32Len; uIdx++) + { + // + // If the character to the UART is \n, then add a \r before it so that + // \n is translated to \n\r in the output. + // + if(pcBuf[uIdx] == '\n') + { + MAP_UARTCharPut(g_ui32Base, '\r'); + } + + // + // Send the character to the UART output. + // + MAP_UARTCharPut(g_ui32Base, pcBuf[uIdx]); + } + + // + // Return the number of characters written. + // + return(uIdx); +#endif +} + +//***************************************************************************** +// +//! A simple UART based get string function, with some line processing. +//! +//! \param pcBuf points to a buffer for the incoming string from the UART. +//! \param ui32Len is the length of the buffer for storage of the string, +//! including the trailing 0. +//! +//! This function will receive a string from the UART input and store the +//! characters in the buffer pointed to by \e pcBuf. The characters will +//! continue to be stored until a termination character is received. The +//! termination characters are CR, LF, or ESC. A CRLF pair is treated as a +//! single termination character. The termination characters are not stored in +//! the string. The string will be terminated with a 0 and the function will +//! return. +//! +//! In both buffered and unbuffered modes, this function will block until +//! a termination character is received. If non-blocking operation is required +//! in buffered mode, a call to UARTPeek() may be made to determine whether +//! a termination character already exists in the receive buffer prior to +//! calling UARTgets(). +//! +//! Since the string will be null terminated, the user must ensure that the +//! buffer is sized to allow for the additional null character. +//! +//! \return Returns the count of characters that were stored, not including +//! the trailing 0. +// +//***************************************************************************** +int +UARTgets(char *pcBuf, uint32_t ui32Len) +{ +#ifdef UART_BUFFERED + uint32_t ui32Count = 0; + int8_t cChar; + + // + // Check the arguments. + // + ASSERT(pcBuf != 0); + ASSERT(ui32Len != 0); + ASSERT(g_ui32Base != 0); + + // + // Adjust the length back by 1 to leave space for the trailing + // null terminator. + // + ui32Len--; + + // + // Process characters until a newline is received. + // + while(1) + { + // + // Read the next character from the receive buffer. + // + if(!RX_BUFFER_EMPTY) + { + cChar = g_pcUARTRxBuffer[g_ui32UARTRxReadIndex]; + ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxReadIndex); + + // + // See if a newline or escape character was received. + // + if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b)) + { + // + // Stop processing the input and end the line. + // + break; + } + + // + // Process the received character as long as we are not at the end + // of the buffer. If the end of the buffer has been reached then + // all additional characters are ignored until a newline is + // received. + // + if(ui32Count < ui32Len) + { + // + // Store the character in the caller supplied buffer. + // + pcBuf[ui32Count] = cChar; + + // + // Increment the count of characters received. + // + ui32Count++; + } + } + } + + // + // Add a null termination to the string. + // + pcBuf[ui32Count] = 0; + + // + // Return the count of int8_ts in the buffer, not counting the trailing 0. + // + return(ui32Count); +#else + uint32_t ui32Count = 0; + int8_t cChar; + static int8_t bLastWasCR = 0; + + // + // Check the arguments. + // + ASSERT(pcBuf != 0); + ASSERT(ui32Len != 0); + ASSERT(g_ui32Base != 0); + + // + // Adjust the length back by 1 to leave space for the trailing + // null terminator. + // + ui32Len--; + + // + // Process characters until a newline is received. + // + while(1) + { + // + // Read the next character from the console. + // + cChar = MAP_UARTCharGet(g_ui32Base); + + // + // See if the backspace key was pressed. + // + if(cChar == '\b') + { + // + // If there are any characters already in the buffer, then delete + // the last. + // + if(ui32Count) + { + // + // Rub out the previous character. + // + UARTwrite("\b \b", 3); + + // + // Decrement the number of characters in the buffer. + // + ui32Count--; + } + + // + // Skip ahead to read the next character. + // + continue; + } + + // + // If this character is LF and last was CR, then just gobble up the + // character because the EOL processing was taken care of with the CR. + // + if((cChar == '\n') && bLastWasCR) + { + bLastWasCR = 0; + continue; + } + + // + // See if a newline or escape character was received. + // + if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b)) + { + // + // If the character is a CR, then it may be followed by a LF which + // should be paired with the CR. So remember that a CR was + // received. + // + if(cChar == '\r') + { + bLastWasCR = 1; + } + + // + // Stop processing the input and end the line. + // + break; + } + + // + // Process the received character as long as we are not at the end of + // the buffer. If the end of the buffer has been reached then all + // additional characters are ignored until a newline is received. + // + if(ui32Count < ui32Len) + { + // + // Store the character in the caller supplied buffer. + // + pcBuf[ui32Count] = cChar; + + // + // Increment the count of characters received. + // + ui32Count++; + + // + // Reflect the character back to the user. + // + MAP_UARTCharPut(g_ui32Base, cChar); + } + } + + // + // Add a null termination to the string. + // + pcBuf[ui32Count] = 0; + + // + // Send a CRLF pair to the terminal to end the line. + // + UARTwrite("\r\n", 2); + + // + // Return the count of int8_ts in the buffer, not counting the trailing 0. + // + return(ui32Count); +#endif +} + +//***************************************************************************** +// +//! Read a single character from the UART, blocking if necessary. +//! +//! This function will receive a single character from the UART and store it at +//! the supplied address. +//! +//! In both buffered and unbuffered modes, this function will block until a +//! character is received. If non-blocking operation is required in buffered +//! mode, a call to UARTRxAvail() may be made to determine whether any +//! characters are currently available for reading. +//! +//! \return Returns the character read. +// +//***************************************************************************** +unsigned char +UARTgetc(void) +{ +#ifdef UART_BUFFERED + unsigned char cChar; + + // + // Wait for a character to be received. + // + while(RX_BUFFER_EMPTY) + { + // + // Block waiting for a character to be received (if the buffer is + // currently empty). + // + } + + // + // Read a character from the buffer. + // + cChar = g_pcUARTRxBuffer[g_ui32UARTRxReadIndex]; + ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxReadIndex); + + // + // Return the character to the caller. + // + return(cChar); +#else + // + // Block until a character is received by the UART then return it to + // the caller. + // + return(MAP_UARTCharGet(g_ui32Base)); +#endif +} + +//***************************************************************************** +// +//! A simple UART based vprintf function supporting \%c, \%d, \%p, \%s, \%u, +//! \%x, and \%X. +//! +//! \param pcString is the format string. +//! \param vaArgP is a variable argument list pointer whose content will depend +//! upon the format string passed in \e pcString. +//! +//! This function is very similar to the C library vprintf() function. +//! All of its output will be sent to the UART. Only the following formatting +//! characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%l to print a long decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%s, \%d, \%i, \%u, \%p, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeroes instead of spaces. +//! +//! The type of the arguments in the variable arguments list must match the +//! requirements of the format string. For example, if an integer was passed +//! where a string was expected, an error of some kind will most likely occur. +//! +//! \return None. +// +//***************************************************************************** +void +UARTvprintf(const char *pcString, va_list vaArgP) +{ + uint32_t ui32Idx, ui32Value, ui32Pos, ui32Count, ui32Base, ui32Neg; + char *pcStr, pcBuf[16], cFill; + + // + // Check the arguments. + // + ASSERT(pcString != 0); + + // + // Loop while there are more characters in the string. + // + while(*pcString) + { + // + // Find the first non-% character, or the end of the string. + // + for(ui32Idx = 0; + (pcString[ui32Idx] != '%') && (pcString[ui32Idx] != '\0'); + ui32Idx++) + { + } + + // + // Write this portion of the string. + // + UARTwrite(pcString, ui32Idx); + + // + // Skip the portion of the string that was written. + // + pcString += ui32Idx; + + // + // See if the next character is a %. + // + if(*pcString == '%') + { + // + // Skip the %. + // + pcString++; + + // + // Set the digit count to zero, and the fill character to space + // (in other words, to the defaults). + // + ui32Count = 0; + cFill = ' '; + + // + // It may be necessary to get back here to process more characters. + // Goto's aren't pretty, but effective. I feel extremely dirty for + // using not one but two of the beasts. + // +again: + + // + // Determine how to handle the next character. + // + switch(*pcString++) + { + // + // Handle the digit characters. + // + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + // + // If this is a zero, and it is the first digit, then the + // fill character is a zero instead of a space. + // + if((pcString[-1] == '0') && (ui32Count == 0)) + { + cFill = '0'; + } + + // + // Update the digit count. + // + ui32Count *= 10; + ui32Count += pcString[-1] - '0'; + + // + // Get the next character. + // + goto again; + } + + // + // Handle the %c command. + // + case 'c': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Print out the character. + // + UARTwrite((char *)&ui32Value, 1); + + // + // This command has been handled. + // + break; + } + + // + // Handle the %d and %i commands. + // + case 'd': + case 'i': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint16_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // If the value is negative, make it positive and indicate + // that a minus sign is needed. + // + if((int32_t)ui32Value < 0) + { + // + // Make the value positive. + // + ui32Value = -(int32_t)ui32Value; + + // + // Indicate that the value is negative. + // + ui32Neg = 1; + } + else + { + // + // Indicate that the value is positive so that a minus + // sign isn't inserted. + // + ui32Neg = 0; + } + + // + // Set the base to 10. + // + ui32Base = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %l command. + // + case 'l': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // If the value is negative, make it positive and indicate + // that a minus sign is needed. + // + if((int32_t)ui32Value < 0) + { + // + // Make the value positive. + // + ui32Value = -(int32_t)ui32Value; + + // + // Indicate that the value is negative. + // + ui32Neg = 1; + } + else + { + // + // Indicate that the value is positive so that a minus + // sign isn't inserted. + // + ui32Neg = 0; + } + + // + // Set the base to 10. + // + ui32Base = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %s command. + // + case 's': + { + // + // Get the string pointer from the varargs. + // + pcStr = va_arg(vaArgP, char *); + + // + // Determine the length of the string. + // + for(ui32Idx = 0; pcStr[ui32Idx] != '\0'; ui32Idx++) + { + } + + // + // Write the string. + // + UARTwrite(pcStr, ui32Idx); + + // + // Write any required padding spaces + // + if(ui32Count > ui32Idx) + { + ui32Count -= ui32Idx; + while(ui32Count--) + { + UARTwrite(" ", 1); + } + } + + // + // This command has been handled. + // + break; + } + + // + // Handle the %u command. + // + case 'u': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // Set the base to 10. + // + ui32Base = 10; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ui32Neg = 0; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %x and %X commands. Note that they are treated + // identically; in other words, %X will use lower case letters + // for a-f instead of the upper case letters it should use. We + // also alias %p to %x. + // + case 'x': + case 'X': + case 'p': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // Set the base to 16. + // + ui32Base = 16; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ui32Neg = 0; + + // + // Determine the number of digits in the string version of + // the value. + // +convert: + for(ui32Idx = 1; + (((ui32Idx * ui32Base) <= ui32Value) && + (((ui32Idx * ui32Base) / ui32Base) == ui32Idx)); + ui32Idx *= ui32Base, ui32Count--) + { + } + + // + // If the value is negative, reduce the count of padding + // characters needed. + // + if(ui32Neg) + { + ui32Count--; + } + + // + // If the value is negative and the value is padded with + // zeros, then place the minus sign before the padding. + // + if(ui32Neg && (cFill == '0')) + { + // + // Place the minus sign in the output buffer. + // + pcBuf[ui32Pos++] = '-'; + + // + // The minus sign has been placed, so turn off the + // negative flag. + // + ui32Neg = 0; + } + + // + // Provide additional padding at the beginning of the + // string conversion if needed. + // + if((ui32Count > 1) && (ui32Count < 16)) + { + for(ui32Count--; ui32Count; ui32Count--) + { + pcBuf[ui32Pos++] = cFill; + } + } + + // + // If the value is negative, then place the minus sign + // before the number. + // + if(ui32Neg) + { + // + // Place the minus sign in the output buffer. + // + pcBuf[ui32Pos++] = '-'; + } + + // + // Convert the value into a string. + // + for(; ui32Idx; ui32Idx /= ui32Base) + { + pcBuf[ui32Pos++] = + g_pcHex[(ui32Value / ui32Idx) % ui32Base]; + } + + // + // Write the string. + // + UARTwrite(pcBuf, ui32Pos); + + // + // This command has been handled. + // + break; + } + + // + // Handle the %% command. + // + case '%': + { + // + // Simply write a single %. + // + UARTwrite(pcString - 1, 1); + + // + // This command has been handled. + // + break; + } + + // + // Handle all other commands. + // + default: + { + // + // Indicate an error. + // + UARTwrite("ERROR", 5); + + // + // This command has been handled. + // + break; + } + } + } + } +} + +//***************************************************************************** +// +//! A simple UART based printf function supporting \%c, \%d, \%p, \%s, \%u, +//! \%x, and \%X. +//! +//! \param pcString is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library fprintf() function. +//! All of its output will be sent to the UART. Only the following formatting +//! characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%s, \%d, \%i, \%u, \%p, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeroes instead of spaces. +//! +//! The type of the arguments after \e pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! \return None. +// +//***************************************************************************** +void +UARTprintf(const char *pcString, ...) +{ + va_list vaArgP; + + // + // Start the varargs processing. + // + va_start(vaArgP, pcString); + + UARTvprintf(pcString, vaArgP); + + // + // We're finished with the varargs now. + // + va_end(vaArgP); +} + +//***************************************************************************** +// +//! Returns the number of bytes available in the receive buffer. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to determine the number +//! of bytes of data currently available in the receive buffer. +//! +//! \return Returns the number of available bytes. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +int +UARTRxBytesAvail(void) +{ + return(RX_BUFFER_USED); +} +#endif + +#if defined(UART_BUFFERED) || defined(DOXYGEN) +//***************************************************************************** +// +//! Returns the number of bytes free in the transmit buffer. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to determine the amount +//! of space currently available in the transmit buffer. +//! +//! \return Returns the number of free bytes. +// +//***************************************************************************** +int +UARTTxBytesFree(void) +{ + return(TX_BUFFER_FREE); +} +#endif + +//***************************************************************************** +// +//! Looks ahead in the receive buffer for a particular character. +//! +//! \param ucChar is the character that is to be searched for. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to look ahead in the +//! receive buffer for a particular character and report its position if found. +//! It is typically used to determine whether a complete line of user input is +//! available, in which case ucChar should be set to CR ('\\r') which is used +//! as the line end marker in the receive buffer. +//! +//! \return Returns -1 to indicate that the requested character does not exist +//! in the receive buffer. Returns a non-negative number if the character was +//! found in which case the value represents the position of the first instance +//! of \e ucChar relative to the receive buffer read pointer. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +int +UARTPeek(unsigned char ucChar) +{ + int iCount; + int iAvail; + uint32_t ui32ReadIndex; + + // + // How many characters are there in the receive buffer? + // + iAvail = (int)RX_BUFFER_USED; + ui32ReadIndex = g_ui32UARTRxReadIndex; + + // + // Check all the unread characters looking for the one passed. + // + for(iCount = 0; iCount < iAvail; iCount++) + { + if(g_pcUARTRxBuffer[ui32ReadIndex] == ucChar) + { + // + // We found it so return the index + // + return(iCount); + } + else + { + // + // This one didn't match so move on to the next character. + // + ADVANCE_RX_BUFFER_INDEX(ui32ReadIndex); + } + } + + // + // If we drop out of the loop, we didn't find the character in the receive + // buffer. + // + return(-1); +} +#endif + +//***************************************************************************** +// +//! Flushes the receive buffer. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to discard any data +//! received from the UART but not yet read using UARTgets(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTFlushRx(void) +{ + uint32_t ui32Int; + + // + // Temporarily turn off interrupts. + // + ui32Int = MAP_IntMasterDisable(); + + // + // Flush the receive buffer. + // + g_ui32UARTRxReadIndex = 0; + g_ui32UARTRxWriteIndex = 0; + + // + // If interrupts were enabled when we turned them off, turn them + // back on again. + // + if(!ui32Int) + { + MAP_IntMasterEnable(); + } +} +#endif + +//***************************************************************************** +// +//! Flushes the transmit buffer. +//! +//! \param bDiscard indicates whether any remaining data in the buffer should +//! be discarded (\b true) or transmitted (\b false). +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to flush the transmit +//! buffer, either discarding or transmitting any data received via calls to +//! UARTprintf() that is waiting to be transmitted. On return, the transmit +//! buffer will be empty. +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTFlushTx(bool bDiscard) +{ + uint32_t ui32Int; + + // + // Should the remaining data be discarded or transmitted? + // + if(bDiscard) + { + // + // The remaining data should be discarded, so temporarily turn off + // interrupts. + // + ui32Int = MAP_IntMasterDisable(); + + // + // Flush the transmit buffer. + // + g_ui32UARTTxReadIndex = 0; + g_ui32UARTTxWriteIndex = 0; + + // + // If interrupts were enabled when we turned them off, turn them + // back on again. + // + if(!ui32Int) + { + MAP_IntMasterEnable(); + } + } + else + { + // + // Wait for all remaining data to be transmitted before returning. + // + while(!TX_BUFFER_EMPTY) + { + } + } +} +#endif + +//***************************************************************************** +// +//! Enables or disables echoing of received characters to the transmitter. +//! +//! \param bEnable must be set to \b true to enable echo or \b false to +//! disable it. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to control whether or not +//! received characters are automatically echoed back to the transmitter. By +//! default, echo is enabled and this is typically the desired behavior if +//! the module is being used to support a serial command line. In applications +//! where this module is being used to provide a convenient, buffered serial +//! interface over which application-specific binary protocols are being run, +//! however, echo may be undesirable and this function can be used to disable +//! it. +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTEchoSet(bool bEnable) +{ + g_bDisableEcho = !bEnable; +} +#endif + +//***************************************************************************** +// +//! Handles UART interrupts. +//! +//! This function handles interrupts from the UART. It will copy data from the +//! transmit buffer to the UART transmit FIFO if space is available, and it +//! will copy data from the UART receive FIFO to the receive buffer if data is +//! available. +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTStdioIntHandler(void) +{ + uint32_t ui32Ints; + int8_t cChar; + int32_t i32Char; + static bool bLastWasCR = false; + + // + // Get and clear the current interrupt source(s) + // + ui32Ints = MAP_UARTIntStatus(g_ui32Base, true); + MAP_UARTIntClear(g_ui32Base, ui32Ints); + + // + // Are we being interrupted because the TX FIFO has space available? + // + if(ui32Ints & UART_INT_TX) + { + // + // Move as many bytes as we can into the transmit FIFO. + // + UARTPrimeTransmit(g_ui32Base); + + // + // If the output buffer is empty, turn off the transmit interrupt. + // + if(TX_BUFFER_EMPTY) + { + MAP_UARTIntDisable(g_ui32Base, UART_INT_TX); + } + } + + // + // Are we being interrupted due to a received character? + // + if(ui32Ints & (UART_INT_RX | UART_INT_RT)) + { + // + // Get all the available characters from the UART. + // + while(MAP_UARTCharsAvail(g_ui32Base)) + { + // + // Read a character + // + i32Char = MAP_UARTCharGetNonBlocking(g_ui32Base); + cChar = (unsigned char)(i32Char & 0xFF); + + // + // If echo is disabled, we skip the various text filtering + // operations that would typically be required when supporting a + // command line. + // + if(!g_bDisableEcho) + { + // + // Handle backspace by erasing the last character in the + // buffer. + // + if(cChar == '\b') + { + // + // If there are any characters already in the buffer, then + // delete the last. + // + if(!RX_BUFFER_EMPTY) + { + // + // Rub out the previous character on the users + // terminal. + // + UARTwrite("\b \b", 3); + + // + // Decrement the number of characters in the buffer. + // + if(g_ui32UARTRxWriteIndex == 0) + { + g_ui32UARTRxWriteIndex = UART_RX_BUFFER_SIZE - 1; + } + else + { + g_ui32UARTRxWriteIndex--; + } + } + + // + // Skip ahead to read the next character. + // + continue; + } + + // + // If this character is LF and last was CR, then just gobble up + // the character since we already echoed the previous CR and we + // don't want to store 2 characters in the buffer if we don't + // need to. + // + if((cChar == '\n') && bLastWasCR) + { + bLastWasCR = false; + continue; + } + + // + // See if a newline or escape character was received. + // + if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b)) + { + // + // If the character is a CR, then it may be followed by an + // LF which should be paired with the CR. So remember that + // a CR was received. + // + if(cChar == '\r') + { + bLastWasCR = 1; + } + + // + // Regardless of the line termination character received, + // put a CR in the receive buffer as a marker telling + // UARTgets() where the line ends. We also send an + // additional LF to ensure that the local terminal echo + // receives both CR and LF. + // + cChar = '\r'; + UARTwrite("\n", 1); + } + } + + // + // If there is space in the receive buffer, put the character + // there, otherwise throw it away. + // + if(!RX_BUFFER_FULL) + { + // + // Store the new character in the receive buffer + // + g_pcUARTRxBuffer[g_ui32UARTRxWriteIndex] = + (unsigned char)(i32Char & 0xFF); + ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxWriteIndex); + + // + // If echo is enabled, write the character to the transmit + // buffer so that the user gets some immediate feedback. + // + if(!g_bDisableEcho) + { + UARTwrite((const char *)&cChar, 1); + } + } + } + + // + // If we wrote anything to the transmit buffer, make sure it actually + // gets transmitted. + // + UARTPrimeTransmit(g_ui32Base); + MAP_UARTIntEnable(g_ui32Base, UART_INT_TX); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h new file mode 100644 index 0000000000..1176091bbb --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h @@ -0,0 +1,107 @@ +//########################################################################### +// +// FILE: uartstdio.h +// +// TITLE: Prototypes for the UART console functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __UARTSTDIO_H__ +#define __UARTSTDIO_H__ + +// +// Included Files +// +#include + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// If built for buffered operation, the following labels define the sizes of +// the transmit and receive buffers respectively. +// +#ifdef UART_BUFFERED +#ifndef UART_RX_BUFFER_SIZE +#define UART_RX_BUFFER_SIZE 128 +#endif +#ifndef UART_TX_BUFFER_SIZE +#define UART_TX_BUFFER_SIZE 1024 +#endif +#endif + +// +// Function Prototypes +// +extern void UARTStdioConfig(uint32_t ui32Port, uint32_t ui32Baud, + uint32_t ui32SrcClock); +extern int UARTgets(char *pcBuf, uint32_t ui32Len); +extern unsigned char UARTgetc(void); +extern void UARTprintf(const char *pcString, ...); +extern void UARTvprintf(const char *pcString, va_list vaArgP); +extern int UARTwrite(const char *pcBuf, uint32_t ui32Len); +#ifdef UART_BUFFERED +extern int UARTPeek(unsigned char ucChar); +extern void UARTFlushTx(bool bDiscard); +extern void UARTFlushRx(void); +extern int UARTRxBytesAvail(void); +extern int UARTTxBytesFree(void); +extern void UARTEchoSet(bool bEnable); +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UARTSTDIO_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c new file mode 100644 index 0000000000..05e0ce7be2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c @@ -0,0 +1,1853 @@ +//########################################################################### +// +// FILE: ustdlib.c +// +// TITLE: Simple standard library functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include +#include +#include "driverlib/debug.h" +#include "utils/ustdlib.h" + +//***************************************************************************** +// +//! \addtogroup ustdlib_api +//! @{ +// +//***************************************************************************** + +// +// Globals +// + +// +// A mapping from an integer between 0 and 15 to its ASCII character +// equivalent. +// +static const char * const g_pcHex = "0123456789abcdef"; + +// +// Functions +// + +//***************************************************************************** +// +//! Copies a certain number of characters from one string to another. +//! +//! \param s1 is a pointer to the destination buffer into which characters +//! are to be copied. +//! \param s2 is a pointer to the string from which characters are to be +//! copied. +//! \param n is the number of characters to copy to the destination buffer. +//! +//! This function copies at most \e n characters from the string pointed to +//! by \e s2 into the buffer pointed to by \e s1. If the end of \e s2 is found +//! before \e n characters have been copied, remaining characters in \e s1 +//! will be padded with zeroes until \e n characters have been written. Note +//! that the destination string will only be NULL terminated if the number of +//! characters to be copied is greater than the length of \e s2. +//! +//! \return Returns \e s1. +// +//***************************************************************************** +char * +ustrncpy(char * restrict s1, const char * restrict s2, size_t n) +{ + size_t count; + + // + // Check the arguments. + // + ASSERT(s1); + ASSERT(s2); + + // + // Start at the beginning of the source string. + // + count = 0; + + // + // Copy the source string until we run out of source characters or + // destination space. + // + while(n && s2[count]) + { + s1[count] = s2[count]; + count++; + n--; + } + + // + // Pad the destination if we are not yet done. + // + while(n) + { + s1[count++] = (char)0; + n--; + } + + // + // Pass the destination pointer back to the caller. + // + return(s1); +} + +//***************************************************************************** +// +//! A simple vsnprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and +//! \%X. +//! +//! \param s points to the buffer where the converted string is stored. +//! \param n is the size of the buffer. +//! \param format is the format string. +//! \param arg is the list of optional arguments, which depend on the +//! contents of the format string. +//! +//! This function is very similar to the C library vsnprintf() +//! function. Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeroes instead of spaces. +//! +//! The type of the arguments after \e format must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The \e n parameter limits the number of characters that will be +//! stored in the buffer pointed to by \e s to prevent the possibility of +//! a buffer overflow. The buffer size should be large enough to hold the +//! expected converted output string, including the null termination character. +//! +//! The function will return the number of characters that would be converted +//! as if there were no limit on the buffer size. Therefore it is possible for +//! the function to return a count that is greater than the specified buffer +//! size. If this happens, it means that the output was truncated. +//! +//! \return Returns the number of characters that were to be stored, not +//! including the NULL termination character, regardless of space in the +//! buffer. +// +//***************************************************************************** +int +uvsnprintf(char * restrict s, size_t n, const char * restrict format, + va_list arg) +{ + unsigned long ulIdx, ulValue, ulCount, ulBase, ulNeg; + char *pcStr, cFill; + int iConvertCount = 0; + + // + // Check the arguments. + // + ASSERT(s); + ASSERT(n); + ASSERT(format); + + // + // Adjust buffer size limit to allow one space for null termination. + // + if(n) + { + n--; + } + + // + // Initialize the count of characters converted. + // + iConvertCount = 0; + + // + // Loop while there are more characters in the format string. + // + while(*format) + { + // + // Find the first non-% character, or the end of the string. + // + for(ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); + ulIdx++) + { + } + + // + // Write this portion of the string to the output buffer. If there are + // more characters to write than there is space in the buffer, then + // only write as much as will fit in the buffer. + // + if(ulIdx > n) + { + ustrncpy(s, format, n); + s += n; + n = 0; + } + else + { + ustrncpy(s, format, ulIdx); + s += ulIdx; + n -= ulIdx; + } + + // + // Update the conversion count. This will be the number of characters + // that should have been written, even if there was not room in the + // buffer. + // + iConvertCount += ulIdx; + + // + // Skip the portion of the format string that was written. + // + format += ulIdx; + + // + // See if the next character is a %. + // + if(*format == '%') + { + // + // Skip the %. + // + format++; + + // + // Set the digit count to zero, and the fill character to space + // (that is, to the defaults). + // + ulCount = 0; + cFill = ' '; + + // + // It may be necessary to get back here to process more characters. + // Goto's aren't pretty, but effective. I feel extremely dirty for + // using not one but two of the beasts. + // +again: + + // + // Determine how to handle the next character. + // + switch(*format++) + { + // + // Handle the digit characters. + // + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + // + // If this is a zero, and it is the first digit, then the + // fill character is a zero instead of a space. + // + if((format[-1] == '0') && (ulCount == 0)) + { + cFill = '0'; + } + + // + // Update the digit count. + // + ulCount *= 10; + ulCount += format[-1] - '0'; + + // + // Get the next character. + // + goto again; + } + + // + // Handle the %c command. + // + case 'c': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // Copy the character to the output buffer, if there is + // room. Update the buffer size remaining. + // + if(n != 0) + { + *s++ = (char)ulValue; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle the %d and %i commands. + // + case 'd': + case 'i': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // If the value is negative, make it positive and indicate + // that a minus sign is needed. + // + if((long)ulValue < 0) + { + // + // Make the value positive. + // + ulValue = -(long)ulValue; + + // + // Indicate that the value is negative. + // + ulNeg = 1; + } + else + { + // + // Indicate that the value is positive so that a + // negative sign isn't inserted. + // + ulNeg = 0; + } + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %s command. + // + case 's': + { + // + // Get the string pointer from the varargs. + // + pcStr = va_arg(arg, char *); + + // + // Determine the length of the string. + // + for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) + { + } + + // + // Update the convert count to include any padding that + // should be necessary (regardless of whether we have space + // to write it or not). + // + if(ulCount > ulIdx) + { + iConvertCount += (ulCount - ulIdx); + } + + // + // Copy the string to the output buffer. Only copy as much + // as will fit in the buffer. Update the output buffer + // pointer and the space remaining. + // + if(ulIdx > n) + { + ustrncpy(s, pcStr, n); + s += n; + n = 0; + } + else + { + ustrncpy(s, pcStr, ulIdx); + s += ulIdx; + n -= ulIdx; + + // + // Write any required padding spaces assuming there is + // still space in the buffer. + // + if(ulCount > ulIdx) + { + ulCount -= ulIdx; + if(ulCount > n) + { + ulCount = n; + } + n = -ulCount; + + while(ulCount--) + { + *s++ = ' '; + } + } + } + + // + // Update the conversion count. This will be the number of + // characters that should have been written, even if there + // was not room in the buffer. + // + iConvertCount += ulIdx; + + // + // This command has been handled. + // + break; + } + + // + // Handle the %u command. + // + case 'u': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ulNeg = 0; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %x and %X commands. Note that they are treated + // identically; that is, %X will use lower case letters for a-f + // instead of the upper case letters is should use. We also + // alias %p to %x. + // + case 'x': + case 'X': + case 'p': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // Set the base to 16. + // + ulBase = 16; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ulNeg = 0; + + // + // Determine the number of digits in the string version of + // the value. + // +convert: + for(ulIdx = 1; + (((ulIdx * ulBase) <= ulValue) && + (((ulIdx * ulBase) / ulBase) == ulIdx)); + ulIdx *= ulBase, ulCount--) + { + } + + // + // If the value is negative, reduce the count of padding + // characters needed. + // + if(ulNeg) + { + ulCount--; + } + + // + // If the value is negative and the value is padded with + // zeros, then place the minus sign before the padding. + // + if(ulNeg && (n != 0) && (cFill == '0')) + { + // + // Place the minus sign in the output buffer. + // + *s++ = '-'; + n--; + + // + // Update the conversion count. + // + iConvertCount++; + + // + // The minus sign has been placed, so turn off the + // negative flag. + // + ulNeg = 0; + } + + // + // See if there are more characters in the specified field + // width than there are in the conversion of this value. + // + if((ulCount > 1) && (ulCount < 65536)) + { + // + // Loop through the required padding characters. + // + for(ulCount--; ulCount; ulCount--) + { + // + // Copy the character to the output buffer if there + // is room. + // + if(n != 0) + { + *s++ = cFill; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + } + + // + // If the value is negative, then place the minus sign + // before the number. + // + if(ulNeg && (n != 0)) + { + // + // Place the minus sign in the output buffer. + // + *s++ = '-'; + n--; + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // Convert the value into a string. + // + for(; ulIdx; ulIdx /= ulBase) + { + // + // Copy the character to the output buffer if there is + // room. + // + if(n != 0) + { + *s++ = g_pcHex[(ulValue / ulIdx) % ulBase]; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // This command has been handled. + // + break; + } + + // + // Handle the %% command. + // + case '%': + { + // + // Simply write a single %. + // + if(n != 0) + { + *s++ = format[-1]; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle all other commands. + // + default: + { + // + // Indicate an error. + // + if(n >= 5) + { + ustrncpy(s, "ERROR", 5); + s += 5; + n -= 5; + } + else + { + ustrncpy(s, "ERROR", n); + s += n; + n = 0; + } + + // + // Update the conversion count. + // + iConvertCount += 5; + + // + // This command has been handled. + // + break; + } + } + } + } + + // + // Null terminate the string in the buffer. + // + *s = 0; + + // + // Return the number of characters in the full converted string. + // + return(iConvertCount); +} + +//***************************************************************************** +// +//! A simple sprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and \%X. +//! +//! \param s is the buffer where the converted string is stored. +//! \param format is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeros instead of spaces. +//! +//! The type of the arguments after \e format must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The caller must ensure that the buffer \e s is large enough to hold the +//! entire converted string, including the null termination character. +//! +//! \return Returns the count of characters that were written to the output +//! buffer, not including the NULL termination character. +// +//***************************************************************************** +int +usprintf(char * restrict s, const char *format, ...) +{ + va_list arg; + int ret; + + // + // Start the varargs processing. + // + va_start(arg, format); + + // + // Call vsnprintf to perform the conversion. Use a large number for the + // buffer size. + // + ret = uvsnprintf(s, 0xffff, format, arg); + + // + // End the varargs processing. + // + va_end(arg); + + // + // Return the conversion count. + // + return(ret); +} + +//***************************************************************************** +// +//! A simple snprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and +//! \%X. +//! +//! \param s is the buffer where the converted string is stored. +//! \param n is the size of the buffer. +//! \param format is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeros instead of spaces. +//! +//! The type of the arguments after \e format must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The function will copy at most \e n - 1 characters into the buffer +//! \e s. One space is reserved in the buffer for the null termination +//! character. +//! +//! The function will return the number of characters that would be converted +//! as if there were no limit on the buffer size. Therefore it is possible for +//! the function to return a count that is greater than the specified buffer +//! size. If this happens, it means that the output was truncated. +//! +//! \return Returns the number of characters that were to be stored, not +//! including the NULL termination character, regardless of space in the +//! buffer. +// +//***************************************************************************** +int +usnprintf(char * restrict s, size_t n, const char * restrict format, ...) +{ + va_list arg; + int ret; + + // + // Start the varargs processing. + // + va_start(arg, format); + + // + // Call vsnprintf to perform the conversion. + // + ret = uvsnprintf(s, n, format, arg); + + // + // End the varargs processing. + // + va_end(arg); + + // + // Return the conversion count. + // + return(ret); +} + + +// +// This array contains the number of days in a year at the beginning of each +// month of the year, in a non-leap year. +// +static const time_t g_psDaysToMonth[12] = +{ + 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 +}; + +//***************************************************************************** +// +//! Converts from seconds to calendar date and time. +//! +//! \param timer is the number of seconds. +//! \param tm is a pointer to the time structure that is filled in with the +//! broken down date and time. +//! +//! This function converts a number of seconds since midnight GMT on January 1, +//! 1970 (traditional Unix epoch) into the equivalent month, day, year, hours, +//! minutes, and seconds representation. +//! +//! \return None. +// +//***************************************************************************** +void +ulocaltime(time_t timer, struct tm *tm) +{ + time_t temp, months; + + // + // Extract the number of seconds, converting time to the number of minutes. + // + temp = timer / 60; + tm->tm_sec = timer - (temp * 60); + timer = temp; + + // + // Extract the number of minutes, converting time to the number of hours. + // + temp = timer / 60; + tm->tm_min = timer - (temp * 60); + timer = temp; + + // + // Extract the number of hours, converting time to the number of days. + // + temp = timer / 24; + tm->tm_hour = timer - (temp * 24); + timer = temp; + + // + // Compute the day of the week. + // + tm->tm_wday = (timer + 4) % 7; + + // + // Compute the number of leap years that have occurred since 1968, the + // first leap year before 1970. For the beginning of a leap year, cut the + // month loop below at March so that the leap day is classified as February + // 29 followed by March 1, instead of March 1 followed by another March 1. + // + timer += 366 + 365; + temp = timer / ((4 * 365) + 1); + if((timer - (temp * ((4 * 365) + 1))) > (31 + 28)) + { + temp++; + months = 12; + } + else + { + months = 2; + } + + // + // Extract the year. + // + tm->tm_year = ((timer - temp) / 365) + 68; + timer -= ((tm->tm_year - 68) * 365) + temp; + + // + // Extract the month. + // + for(temp = 0; temp < months; temp++) + { + if(g_psDaysToMonth[temp] > timer) + { + break; + } + } + tm->tm_mon = temp - 1; + + // + // Extract the day of the month. + // + tm->tm_mday = timer - g_psDaysToMonth[temp - 1] + 1; +} + +//***************************************************************************** +// +//! Compares two time structures and determines if one is greater than, +//! less than, or equal to the other. +//! +//! \param t1 is the first time structure to compare. +//! \param t2 is the second time structure to compare. +//! +//! This function compares two time structures and returns a signed number +//! to indicate the result of the comparison. If the time represented by +//! \e t1 is greater than the time represented by \e t2 then a positive +//! number is returned. Likewise if \e t1 is less than \e t2 then a +//! negative number is returned. If the two times are equal then the function +//! returns 0. +//! +//! \return Returns 0 if the two times are equal, +1 if \e t1 is greater +//! than \e t2, and -1 if \e t1 is less than \e t2. +// +//***************************************************************************** +static int +ucmptime(struct tm *t1, struct tm *t2) +{ + // + // Compare each field in descending significance to determine if + // greater than, less than, or equal. + // + if(t1->tm_year > t2->tm_year) + { + return(1); + } + else if(t1->tm_year < t2->tm_year) + { + return(-1); + } + else if(t1->tm_mon > t2->tm_mon) + { + return(1); + } + else if(t1->tm_mon < t2->tm_mon) + { + return(-1); + } + else if(t1->tm_mday > t2->tm_mday) + { + return(1); + } + else if(t1->tm_mday < t2->tm_mday) + { + return(-1); + } + else if(t1->tm_hour > t2->tm_hour) + { + return(1); + } + else if(t1->tm_hour < t2->tm_hour) + { + return(-1); + } + else if(t1->tm_min > t2->tm_min) + { + return(1); + } + else if(t1->tm_min < t2->tm_min) + { + return(-1); + } + else if(t1->tm_sec > t2->tm_sec) + { + return(1); + } + else if(t1->tm_sec < t2->tm_sec) + { + return(-1); + } + else + { + // + // Reaching this branch of the conditional means that all of the + // fields are equal, and thus the two times are equal. + // + return(0); + } +} + +//***************************************************************************** +// +//! Converts calendar date and time to seconds. +//! +//! \param timeptr is a pointer to the time structure that is filled in with +//! the broken down date and time. +//! +//! This function converts the date and time represented by the \e timeptr +//! structure pointer to the number of seconds since midnight GMT on January 1, +//! 1970 (traditional Unix epoch). +//! +//! \return Returns the calendar time and date as seconds. If the conversion +//! was not possible then the function returns (uint32_t)(-1). +// +//***************************************************************************** +time_t +umktime(struct tm *timeptr) +{ + struct tm sTimeGuess; + unsigned long ulTimeGuess = 0x80000000; + unsigned long ulAdjust = 0x40000000; + int iSign; + + // + // Seed the binary search with the first guess. + // + ulocaltime(ulTimeGuess, &sTimeGuess); + iSign = ucmptime(timeptr, &sTimeGuess); + + // + // While the time is not yet found, execute a binary search. + // + while(iSign && ulAdjust) + { + // + // Adjust the time guess up or down depending on the result of the + // last compare. + // + ulTimeGuess = ((iSign > 0) ? (ulTimeGuess + ulAdjust) : + (ulTimeGuess - ulAdjust)); + ulAdjust /= 2; + + // + // Compare the new time guess against the time pointed at by the + // function parameters. + // + ulocaltime(ulTimeGuess, &sTimeGuess); + iSign = ucmptime(timeptr, &sTimeGuess); + } + + // + // If the above loop was exited with iSign == 0, that means that the + // time in seconds was found, so return that value to the caller. + // + if(iSign == 0) + { + return(ulTimeGuess); + } + + // + // Otherwise the time could not be converted so return an error. + // + else + { + return((unsigned long)-1); + } +} + +//***************************************************************************** +// +//! Converts a string into its numeric equivalent. +//! +//! \param nptr is a pointer to the string containing the integer. +//! \param endptr is a pointer that will be set to the first character past +//! the integer in the string. +//! \param base is the radix to use for the conversion; can be zero to +//! auto-select the radix or between 2 and 16 to explicitly specify the radix. +//! +//! This function is very similar to the C library strtoul() function. +//! It scans a string for the first token (that is, non-white space) and +//! converts the value at that location in the string into an integer value. +//! +//! \return Returns the result of the conversion. +// +//***************************************************************************** +unsigned long +ustrtoul(const char * restrict nptr, const char ** restrict endptr, int base) +{ + unsigned long ulRet, ulDigit, ulNeg, ulValid; + const char *pcPtr; + + // + // Check the arguments. + // + ASSERT(nptr); + ASSERT((base == 0) || ((base > 1) && (base <= 16))); + + // + // Initially, the result is zero. + // + ulRet = 0; + ulNeg = 0; + ulValid = 0; + + // + // Skip past any leading white space. + // + pcPtr = nptr; + while((*pcPtr == ' ') || (*pcPtr == '\t')) + { + pcPtr++; + } + + // + // Take a leading + or - from the value. + // + if(*pcPtr == '-') + { + ulNeg = 1; + pcPtr++; + } + else if(*pcPtr == '+') + { + pcPtr++; + } + + // + // See if the radix was not specified, or is 16, and the value starts with + // "0x" or "0X" (to indicate a hex value). + // + if(((base == 0) || (base == 16)) && (*pcPtr == '0') && + ((pcPtr[1] == 'x') || (pcPtr[1] == 'X'))) + { + // + // Skip the leading "0x". + // + pcPtr += 2; + + // + // Set the radix to 16. + // + base = 16; + } + + // + // See if the radix was not specified. + // + if(base == 0) + { + // + // See if the value starts with "0". + // + if(*pcPtr == '0') + { + // + // Values that start with "0" are assumed to be radix 8. + // + base = 8; + } + else + { + // + // Otherwise, the values are assumed to be radix 10. + // + base = 10; + } + } + + // + // Loop while there are more valid digits to consume. + // + while(1) + { + // + // See if this character is a number. + // + if((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Convert the character to its integer equivalent. + // + ulDigit = *pcPtr++ - '0'; + } + + // + // Otherwise, see if this character is an upper case letter. + // + else if((*pcPtr >= 'A') && (*pcPtr <= 'Z')) + { + // + // Convert the character to its integer equivalent. + // + ulDigit = *pcPtr++ - 'A' + 10; + } + + // + // Otherwise, see if this character is a lower case letter. + // + else if((*pcPtr >= 'a') && (*pcPtr <= 'z')) + { + // + // Convert the character to its integer equivalent. + // + ulDigit = *pcPtr++ - 'a' + 10; + } + + // + // Otherwise, this is not a valid character. + // + else + { + // + // Stop converting this value. + // + break; + } + + // + // See if this digit is valid for the chosen radix. + // + if(ulDigit >= base) + { + // + // Since this was not a valid digit, move the pointer back to the + // character that therefore should not have been consumed. + // + pcPtr--; + + // + // Stop converting this value. + // + break; + } + + // + // Add this digit to the converted value. + // + ulRet *= base; + ulRet += ulDigit; + + // + // Since a digit has been added, this is now a valid result. + // + ulValid = 1; + } + + // + // Set the return string pointer to the first character not consumed. + // + if(endptr) + { + *endptr = ulValid ? pcPtr : nptr; + } + + // + // Return the converted value. + // + return(ulNeg ? (0 - ulRet) : ulRet); +} + +// +// An array of the value of ten raised to the power-of-two exponents. This is +// used for converting the decimal exponent into the floating-point value of +// 10^exp. +// +static const float g_pfExponents[] = +{ + 1.0e+01, + 1.0e+02, + 1.0e+04, + 1.0e+08, + 1.0e+16, + 1.0e+32, +}; + +//***************************************************************************** +// +//! Converts a string into its floating-point equivalent. +//! +//! \param nptr is a pointer to the string containing the floating-point +//! value. +//! \param endptr is a pointer that will be set to the first character past +//! the floating-point value in the string. +//! +//! This function is very similar to the C library strtof() function. +//! It scans a string for the first token (that is, non-white space) and +//! converts the value at that location in the string into a floating-point +//! value. +//! +//! \return Returns the result of the conversion. +// +//***************************************************************************** +float +ustrtof(const char *nptr, const char **endptr) +{ + unsigned long ulNeg, ulExp, ulExpNeg, ulValid, ulIdx; + float fRet, fDigit, fExp; + const char *pcPtr; + + // + // Check the arguments. + // + ASSERT(nptr); + + // + // Initially, the result is zero. + // + fRet = 0; + ulNeg = 0; + ulValid = 0; + + // + // Skip past any leading white space. + // + pcPtr = nptr; + while((*pcPtr == ' ') || (*pcPtr == '\t')) + { + pcPtr++; + } + + // + // Take a leading + or - from the value. + // + if(*pcPtr == '-') + { + ulNeg = 1; + pcPtr++; + } + else if(*pcPtr == '+') + { + pcPtr++; + } + + // + // Loop while there are valid digits to consume. + // + while((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Add this digit to the converted value. + // + fRet *= 10; + fRet += *pcPtr++ - '0'; + + // + // Since a digit has been added, this is now a valid result. + // + ulValid = 1; + } + + // + // See if the next character is a period and the character after that is a + // digit, indicating the start of the fractional portion of the value. + // + if((*pcPtr == '.') && (pcPtr[1] >= '0') && (pcPtr[1] <= '9')) + { + // + // Skip the period. + // + pcPtr++; + + // + // Loop while there are valid fractional digits to consume. + // + fDigit = 0.1; + while((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Add this digit to the converted value. + // + fRet += (*pcPtr++ - '0') * fDigit; + fDigit /= (float)10.0; + + // + // Since a digit has been added, this is now a valid result. + // + ulValid = 1; + } + } + + // + // See if the next character is an "e" and a valid number has been + // converted, indicating the start of the exponent. + // + if(((pcPtr[0] == 'e') || (pcPtr[0] == 'E')) && (ulValid == 1) && + (((pcPtr[1] >= '0') && (pcPtr[1] <= '9')) || + (((pcPtr[1] == '+') || (pcPtr[1] == '-')) && + (pcPtr[2] >= '0') && (pcPtr[2] <= '9')))) + { + // + // Skip the "e". + // + pcPtr++; + + // + // Take a leading + or - from the exponent. + // + ulExpNeg = 0; + if(*pcPtr == '-') + { + ulExpNeg = 1; + pcPtr++; + } + else if(*pcPtr == '+') + { + pcPtr++; + } + + // + // Loop while there are valid digits in the exponent. + // + ulExp = 0; + while((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Add this digit to the converted value. + // + ulExp *= 10; + ulExp += *pcPtr++ - '0'; + } + + // + // Raise ten to the power of the exponent. Do this via binary + // decomposition; for each binary bit set in the exponent, multiply the + // floating-point representation by ten raised to that binary value + // (extracted from the table above). + // + fExp = 1; + for(ulIdx = 0; ulIdx < 7; ulIdx++) + { + if(ulExp & (1 << ulIdx)) + { + fExp *= g_pfExponents[ulIdx]; + } + } + + // + // If the exponent is negative, then the exponent needs to be inverted. + // + if(ulExpNeg == 1) + { + fExp = 1 / fExp; + } + + // + // Multiply the result by the computed exponent value. + // + fRet *= fExp; + } + + // + // Set the return string pointer to the first character not consumed. + // + if(endptr) + { + *endptr = ulValid ? pcPtr : nptr; + } + + // + // Return the converted value. + // + return(ulNeg ? (0 - fRet) : fRet); +} + +//***************************************************************************** +// +//! Returns the length of a null-terminated string. +//! +//! \param s is a pointer to the string whose length is to be found. +//! +//! This function is very similar to the C library strlen() function. +//! It determines the length of the null-terminated string passed and returns +//! this to the caller. +//! +//! This implementation assumes that single byte character strings are passed +//! and will return incorrect values if passed some UTF-8 strings. +//! +//! \return Returns the length of the string pointed to by \e s. +// +//***************************************************************************** +size_t +ustrlen(const char *s) +{ + size_t len; + + // + // Check the arguments. + // + ASSERT(s); + + // + // Initialize the length. + // + len = 0; + + // + // Step through the string looking for a zero character (marking its end). + // + while(s[len]) + { + // + // Zero not found so move on to the next character. + // + len++; + } + + return(len); +} + +//***************************************************************************** +// +//! Finds a substring within a string. +//! +//! \param s1 is a pointer to the string that will be searched. +//! \param s2 is a pointer to the substring that is to be found within +//! \e s1. +//! +//! This function is very similar to the C library strstr() function. +//! It scans a string for the first instance of a given substring and returns +//! a pointer to that substring. If the substring cannot be found, a NULL +//! pointer is returned. +//! +//! \return Returns a pointer to the first occurrence of \e s2 within +//! \e s1 or NULL if no match is found. +// +//***************************************************************************** +char * +ustrstr(const char *s1, const char *s2) +{ + size_t n; + + // + // Get the length of the string to be found. + // + n = ustrlen(s2); + + // + // Loop while we have not reached the end of the string. + // + while(*s1) + { + // + // Check to see if the substring appears at this position. + // + if(ustrncmp(s2, s1, n) == 0) + { + // + // It does so return the pointer. + // + return((char *)s1); + } + + // + // Move to the next position in the string being searched. + // + s1++; + } + + // + // We reached the end of the string without finding the substring so + // return NULL. + // + return((char *)0); +} + +//***************************************************************************** +// +//! Compares two strings without regard to case. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! \param n is the maximum number of characters to compare. +//! +//! This function is very similar to the C library strncasecmp() +//! function. It compares at most \e n characters of two strings without +//! regard to case. The comparison ends if a terminating NULL character is +//! found in either string before \e n characters are compared. In this case, +//! the shorter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrncasecmp(const char *s1, const char *s2, size_t n) +{ + char c1, c2; + + // + // Loop while there are more characters to compare. + // + while(n) + { + // + // If we reached a NULL in both strings, they must be equal so + // we end the comparison and return 0 + // + if(!*s1 && !*s2) + { + return(0); + } + + // + // Lower case the characters at the current position before we compare. + // + c1 = (((*s1 >= 'A') && (*s1 <= 'Z')) ? (*s1 + ('a' - 'A')) : *s1); + c2 = (((*s2 >= 'A') && (*s2 <= 'Z')) ? (*s2 + ('a' - 'A')) : *s2); + + // + // Compare the two characters and, if different, return the relevant + // return code. + // + if(c2 < c1) + { + return(1); + } + if(c1 < c2) + { + return(-1); + } + + // + // Move on to the next character. + // + s1++; + s2++; + n--; + } + + // + // If we fall out, the strings must be equal for at least the first n + // characters so return 0 to indicate this. + // + return(0); +} + +//***************************************************************************** +// +//! Compares two strings without regard to case. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! +//! This function is very similar to the C library strcasecmp() +//! function. It compares two strings without regard to case. The comparison +//! ends if a terminating NULL character is found in either string. In this +//! case, the int16_ter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrcasecmp(const char *s1, const char *s2) +{ + // + // Just let ustrncasecmp() handle this. + // + return(ustrncasecmp(s1, s2, (size_t)-1)); +} + +//***************************************************************************** +// +//! Compares two strings. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! \param n is the maximum number of characters to compare. +//! +//! This function is very similar to the C library strncmp() function. +//! It compares at most \e n characters of two strings taking case into +//! account. The comparison ends if a terminating NULL character is found in +//! either string before \e n characters are compared. In this case, the +//! int16_ter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrncmp(const char *s1, const char *s2, size_t n) +{ + // + // Loop while there are more characters. + // + while(n) + { + // + // If we reached a NULL in both strings, they must be equal so we end + // the comparison and return 0 + // + if(!*s1 && !*s2) + { + return(0); + } + + // + // Compare the two characters and, if different, return the relevant + // return code. + // + if(*s2 < *s1) + { + return(1); + } + if(*s1 < *s2) + { + return(-1); + } + + // + // Move on to the next character. + // + s1++; + s2++; + n--; + } + + // + // If we fall out, the strings must be equal for at least the first n + // characters so return 0 to indicate this. + // + return(0); +} + +//***************************************************************************** +// +//! Compares two strings. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! +//! This function is very similar to the C library strcmp() +//! function. It compares two strings, taking case into account. The +//! comparison ends if a terminating NULL character is found in either string. +//! In this case, the int16_ter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrcmp(const char *s1, const char *s2) +{ + // + // Pass this on to ustrncmp. + // + return(ustrncmp(s1, s2, (size_t)-1)); +} + +// +// Random Number Generator Seed Value +// +static unsigned int g_iRandomSeed = 1; + +//***************************************************************************** +// +//! Set the random number generator seed. +//! +//! \param seed is the new seed value to use for the random number +//! generator. +//! +//! This function is very similar to the C library srand() function. +//! It will set the seed value used in the urand() function. +//! +//! \return None +// +//***************************************************************************** +void +usrand(unsigned int seed) +{ + g_iRandomSeed = seed; +} + +//***************************************************************************** +// +//! Generate a new (pseudo) random number +//! +//! This function is very similar to the C library rand() function. +//! It will generate a pseudo-random number sequence based on the seed value. +//! +//! \return A pseudo-random number will be returned. +// +//***************************************************************************** +int +urand(void) +{ + // + // Generate a new pseudo-random number with a linear congruence random + // number generator. This new random number becomes the seed for the next + // random number. + // + g_iRandomSeed = (g_iRandomSeed * 1664525) + 1013904223; + + // + // Return the new random number. + // + return((int)g_iRandomSeed); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h new file mode 100644 index 0000000000..2cb92ed3a1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h @@ -0,0 +1,96 @@ +//########################################################################### +// +// FILE: ustdlib.h +// +// TITLE: Prototypes for simple standard library functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __USTDLIB_H__ +#define __USTDLIB_H__ + +// +// Included Files +// +#include +#include + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Function Prototypes +// +extern void ulocaltime(time_t timer, struct tm *tm); +extern time_t umktime(struct tm *timeptr); +extern int urand(void); +extern int usnprintf(char * restrict s, size_t n, const char * restrict format, + ...); +extern int usprintf(char * restrict s, const char * restrict format, ...); +extern void usrand(unsigned int seed); +extern int ustrcasecmp(const char *s1, const char *s2); +extern int ustrcmp(const char *s1, const char *s2); +extern size_t ustrlen(const char *s); +extern int ustrncasecmp(const char *s1, const char *s2, size_t n); +extern int ustrncmp(const char *s1, const char *s2, size_t n); +extern char *ustrncpy(char * restrict s1, const char * restrict s2, size_t n); +extern char *ustrstr(const char *s1, const char *s2); +extern float ustrtof(const char * restrict nptr, + const char ** restrict endptr); +extern unsigned long int ustrtoul(const char * restrict nptr, + const char ** restrict endptr, int base); +extern int uvsnprintf(char * restrict s, size_t n, + const char * restrict format, va_list arg); + +// +// Mark the end of the C bindings section for C++ compilers. +// +#ifdef __cplusplus +} +#endif + +#endif // __USTDLIB_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h new file mode 100644 index 0000000000..78ff34a237 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h @@ -0,0 +1,87 @@ +//########################################################################### +// +// FILE: F2837xD_Adc_defines.h +// +// TITLE: #defines used in ADC examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_ADC_DEFINES_H +#define F2837xD_ADC_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +//definitions for specifying an ADC +// +#define ADC_ADCA 0 +#define ADC_ADCB 1 +#define ADC_ADCC 2 +#define ADC_ADCD 3 + +// +//definitions for selecting ADC resolution +// +#ifndef _DUAL_HEADERS +#define ADC_RESOLUTION_12BIT 0 +#define ADC_RESOLUTION_16BIT 1 +#else +#define ADC_BITRESOLUTION_12BIT 0 +#define ADC_BITRESOLUTION_16BIT 1 +#endif +// +//definitions for selecting ADC signal mode +//(single-ended mode is only a valid mode for 12-bit resolution) +// +#define ADC_SIGNALMODE_SINGLE 0 +#define ADC_SIGNALMODE_DIFFERENTIAL 1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_ADC_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h new file mode 100644 index 0000000000..a784ef475d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h @@ -0,0 +1,129 @@ +//############################################################################# +// +// FILE: F2837xD_Can_defines.h +// +// TITLE: Common defines used in CAN Test Cases +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef F2837xD_CAN_DEFINES_H +#define F2837xD_CAN_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// Reset Values +// +#define CAN_RESET_VALUE_ZERO 0x00000000 +#define CAN_CTL_RESET_VALUE 0x00001401 +#define CAN_ES_RESET_VALUE 0x00000007 +#define CAN_BTR_RESET_VALUE 0x00002301 +#define CAN_REL_RESET_VALUE 0xA3170504 +#define CAN_RAM_INIT_RESET_VALUE 0x00000005 +#define CAN_IF_CMD_RESET_VALUE 0x00000001 +#define CAN_IF_MASK_RESET_VALUE 0xFFFFFFFF + +// +// Register value when Peripheral Clock is Disabled +// +#define CAN_MODULE_CLK_DISABLE_VALUE 0x00000000 + +// +// Bit field definition of CAN_CTL register. +// +#define CAN_CTL_INIT 0x00000001 // Initialization +#define CAN_CTL_IE0 0x00000002 // Interrupt Enable 0 +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_IDS 0x00000100 // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x00000200 // Auto-Bus On Enable +#define CAN_CTL_PMD_S 10 +#define CAN_CTL_PMD_M 0x00003C00 // Parity/SECDED Enable +#define CAN_CTL_SWR 0x00008000 // Software Reset Enable +#define CAN_CTL_INITDBG 0x00010000 // Debug Mode Status +#define CAN_CTL_IE1 0x00020000 // Interrupt Enable 1 +#define CAN_CTL_PDR 0x01000000 // Power Down Mode Request +#define CAN_CTL_WUBA 0x02000000 // Wake Up on Bus Activity + +// +// Bit field definition of CAN_IF1_CMD register. +// +#define CAN_IF1_CMD_MESSNUM_S 0 +#define CAN_IF1_CMD_MESSNUM_M 0x000000FF // Message Number +#define CAN_IF1_CMD_BUSY 0x00008000 // Busy Flag +#define CAN_IF1_CMD_DATAB 0x00010000 // Access Data B +#define CAN_IF1_CMD_DATAA 0x00020000 // Access Data A +#define CAN_IF1_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit +#define CAN_IF1_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit +#define CAN_IF1_CMD_CONTROL 0x00100000 // Access Control Bits +#define CAN_IF1_CMD_ARB 0x00200000 // Access Arbitration Bits +#define CAN_IF1_CMD_MASK 0x00400000 // Access Mask Bits +#define CAN_IF1_CMD_WR_RD 0x00800000 // Write and Read + +// +// Bit field definition of CAN_IF2_CMD register. +// +#define CAN_IF2_CMD_MESSNUM_S 0 +#define CAN_IF2_CMD_MESSNUM_M 0x000000FF // Message Number +#define CAN_IF2_CMD_BUSY 0x00008000 // Busy Flag +#define CAN_IF2_CMD_DATAB 0x00010000 // Access Data B +#define CAN_IF2_CMD_DATAA 0x00020000 // Access Data A +#define CAN_IF2_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit +#define CAN_IF2_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit +#define CAN_IF2_CMD_CONTROL 0x00100000 // Access Control Bits +#define CAN_IF2_CMD_ARB 0x00200000 // Access Arbitration Bits +#define CAN_IF2_CMD_MASK 0x00400000 // Access Mask Bits +#define CAN_IF2_CMD_WR_RD 0x00800000 // Write and Read + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_CAN_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h new file mode 100644 index 0000000000..2df82d7929 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h @@ -0,0 +1,201 @@ +//########################################################################### +// +// FILE: F2837xD_Cla_defines.h +// +// TITLE: #defines used in CLA examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CLA_DEFINES_H +#define F2837xD_CLA_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// MCTL Register +// +#define CLA_FORCE_RESET 0x1 +#define CLA_IACK_ENABLE 0x1 +#define CLA_IACK_DISABLE 0x0 + +// +// MMEMCFG Register +// +#define CLA_CLA_SPACE 0x1 +#define CLA_CPU_SPACE 0x0 + +// +// MIER Interrupt Enable Register +// +#define CLA_INT_ENABLE 0x1 +#define CLA_INT_DISABLE 0x0 + +// +// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register +// +#define CLA_TRIG_NOPERPH 0 +#define CLA_TRIG_ADCAINT1 1 +#define CLA_TRIG_ADCAINT2 2 +#define CLA_TRIG_ADCAINT3 3 +#define CLA_TRIG_ADCAINT4 4 +#define CLA_TRIG_ADCAEVT 5 +#define CLA_TRIG_ADCBINT1 6 +#define CLA_TRIG_ADCBINT2 7 +#define CLA_TRIG_ADCBINT3 8 +#define CLA_TRIG_ADCBINT4 9 +#define CLA_TRIG_ADCBEVT 10 +#define CLA_TRIG_ADCCINT1 11 +#define CLA_TRIG_ADCCINT2 12 +#define CLA_TRIG_ADCCINT3 13 +#define CLA_TRIG_ADCCINT4 14 +#define CLA_TRIG_ADCCEVT 15 +#define CLA_TRIG_ADCDINT1 16 +#define CLA_TRIG_ADCDINT2 17 +#define CLA_TRIG_ADCDINT3 18 +#define CLA_TRIG_ADCDINT4 19 +#define CLA_TRIG_ADCDEVT 20 + +#define CLA_TRIG_XINT1 29 +#define CLA_TRIG_XINT2 30 +#define CLA_TRIG_XINT3 31 +#define CLA_TRIG_XINT4 32 +#define CLA_TRIG_XINT5 33 + +#define CLA_TRIG_EPWM1INT 36 +#define CLA_TRIG_EPWM2INT 37 +#define CLA_TRIG_EPWM3INT 38 +#define CLA_TRIG_EPWM4INT 39 +#define CLA_TRIG_EPWM5INT 40 +#define CLA_TRIG_EPWM6INT 41 +#define CLA_TRIG_EPWM7INT 42 +#define CLA_TRIG_EPWM8INT 43 +#define CLA_TRIG_EPWM9INT 44 +#define CLA_TRIG_EPWM10INT 45 +#define CLA_TRIG_EPWM11INT 46 +#define CLA_TRIG_EPWM12INT 47 + +#define CLA_TRIG_TINT0 68 +#define CLA_TRIG_TINT1 69 +#define CLA_TRIG_TINT2 70 + +#define CLA_TRIG_MXEVTA 71 +#define CLA_TRIG_MREVTA 72 +#define CLA_TRIG_MXEVTB 73 +#define CLA_TRIG_MREVTB 74 + +#define CLA_TRIG_ECAP1INT 75 +#define CLA_TRIG_ECAP2INT 76 +#define CLA_TRIG_ECAP3INT 77 +#define CLA_TRIG_ECAP4INT 78 +#define CLA_TRIG_ECAP5INT 79 +#define CLA_TRIG_ECAP6INT 80 + +#define CLA_TRIG_EQEP1INT 83 +#define CLA_TRIG_EQEP2INT 84 +#define CLA_TRIG_EQEP3INT 85 + +#define CLA_TRIG_HRCAP1INT 87 +#define CLA_TRIG_HRCAP2INT 88 + +#define CLA_TRIG_SD1INT 95 +#define CLA_TRIG_SD2INT 96 + +#define CLA_TRIG_UPP1_INT 107 + +#define CLA_TRIG_SPITXINTA 109 +#define CLA_TRIG_SPIRXINTA 110 +#define CLA_TRIG_SPITXINTB 111 +#define CLA_TRIG_SPIRXINTB 112 +#define CLA_TRIG_SPITXINTC 113 +#define CLA_TRIG_SPIRXINTC 114 + +#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT1 == 1); + +#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT2 == 1); + +#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT3 == 1); + +#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT4 == 1); + +#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT5 == 1); + +#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT6 == 1); + +#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT7 == 1); + +#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT8 == 1); + +#define Cla1ForceTask1() asm(" IACK #0x0001") +#define Cla1ForceTask2() asm(" IACK #0x0002") +#define Cla1ForceTask3() asm(" IACK #0x0004") +#define Cla1ForceTask4() asm(" IACK #0x0008") +#define Cla1ForceTask5() asm(" IACK #0x0010") +#define Cla1ForceTask6() asm(" IACK #0x0020") +#define Cla1ForceTask7() asm(" IACK #0x0040") +#define Cla1ForceTask8() asm(" IACK #0x0080") + +#ifdef __cplusplus +} +#endif + +#endif // - end of F2837xD_CLA_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h new file mode 100644 index 0000000000..5a4650cbaa --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h @@ -0,0 +1,128 @@ +//########################################################################### +// +// FILE: F2837xD_Cla_typedefs.h +// +// TITLE: Variable type definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CLA_TYPEDEFS_H_ +#define F2837xD_CLA_TYPEDEFS_H_ + +// +// Macros to manipulate pre-processor to generate a header file name +// at compile time that is based on the test name and can be used as +// an argument to #include +// +#define XSTRINGIZE(s) STRINGIZE(s) +#define STRINGIZE(s) #s +#define XCONCAT(x,y) CONCAT(x,y) +#define CONCAT(x,y) x##y + +// +// Suppress warnings casting CLA pointers +// +#pragma diag_suppress 70,770,232 + +#ifdef __TMS320C28XX_CLA__ +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +// CLA does not support 64-bit types +// This definition is only to allow inclusion of the standard header files +// which do use 64-bit types +// + +#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) +#define F28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef short int16; +typedef long int32; +typedef unsigned char Uint8; +typedef unsigned short Uint16; +typedef unsigned long Uint32; +typedef float float32; +typedef long double float64; +typedef struct { Uint32 low32; Uint32 high32; } Uint64; +typedef struct { int32 low32; int32 high32; } int64; +#else +#error F2837xD_Cla_Typedefs.h must be included before F2837xD_Device.h or any other header \ +file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES +#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) + +#ifndef _TI_STD_TYPES +#define _TI_STD_TYPES +// +//These types are also defined in DSP/BIOS 5.x's and the +//SYS/BIOS 6.x's files. We need to protect their +//definition with the #ifndef/#define guard to avoid the duplicate +//definition warning. +// +//SYS/BIOS requires that the file be included before +//any other .h files. +// +#endif + +struct MSTF_SHADOW_BITS { // bits description + Uint16 LVF:1; // 0 Latched Overflow Flag + Uint16 LUF:1; // 1 Latched Underflow Flag + Uint16 NF:1; // 2 Negative Float Flag + Uint16 ZF:1; // 3 Zero Float Flag + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 TF:1; // 6 Test Flag + Uint16 rsvd2:2; // 8:7 Reserved + Uint16 RNDF32:1; // 9 Rounding Mode + Uint16 rsvd3:1; // 10 Reserved + Uint16 MEALLOW:1; // 11 MEALLOW Status + Uint16 RPCL:4; // 15:12 Return PC: Low Portion + Uint16 RPCH:8; // 23:16 Return PC: High Portion + Uint16 rsvd4:8; // 31:24 Reserved +}; +extern __cregister volatile unsigned int MSTF; + +#endif //__TMS320C28XX_CLA__ + +#ifndef __TMS320C28XX__ +#define __cregister +#endif //__TMS320C28xx__ + +#endif //F2837xD_CLA_TYPEDEFS_H_ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h new file mode 100644 index 0000000000..ef6a245b93 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: F2837xD_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DMA_DEFINES_H +#define F2837xD_DMA_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// PERINTSEL bits +// +#define DMA_ADCAINT1 1 +#define DMA_ADCAINT2 2 +#define DMA_ADCAINT3 3 +#define DMA_ADCAINT4 4 +#define DMA_ADCAEVT 5 +#define DMA_ADCBINT1 6 +#define DMA_ADCBINT2 7 +#define DMA_ADCBINT3 8 +#define DMA_ADCBINT4 9 +#define DMA_ADCBEVT 10 +#define DMA_ADCCINT1 11 +#define DMA_ADCCINT2 12 +#define DMA_ADCCINT3 13 +#define DMA_ADCCINT4 14 +#define DMA_ADCCEVT 15 +#define DMA_ADCDINT1 16 +#define DMA_ADCDINT2 17 +#define DMA_ADCDINT3 18 +#define DMA_ADCDINT4 19 +#define DMA_ADCDEVT 20 + +#define DMA_XINT1 29 +#define DMA_XINT2 30 +#define DMA_XINT3 31 +#define DMA_XINT4 32 +#define DMA_XINT5 33 + +#define DMA_EPWM1A 36 +#define DMA_EPWM1B 37 +#define DMA_EPWM2A 38 +#define DMA_EPWM2B 39 +#define DMA_EPWM3A 40 +#define DMA_EPWM3B 41 +#define DMA_EPWM4A 42 +#define DMA_EPWM4B 43 +#define DMA_EPWM5A 44 +#define DMA_EPWM5B 45 +#define DMA_EPWM6A 46 +#define DMA_EPWM6B 47 +#define DMA_EPWM7A 48 +#define DMA_EPWM7B 49 +#define DMA_EPWM8A 50 +#define DMA_EPWM8B 51 +#define DMA_EPWM9A 52 +#define DMA_EPWM9B 53 +#define DMA_EPWM10A 54 +#define DMA_EPWM10B 55 +#define DMA_EPWM11A 56 +#define DMA_EPWM11B 57 +#define DMA_EPWM12A 58 +#define DMA_EPWM12B 59 +#define DMA_EPWM13A 60 +#define DMA_EPWM13B 61 +#define DMA_EPWM14A 62 +#define DMA_EPWM14B 63 +#define DMA_EPWM15A 64 +#define DMA_EPWM15B 65 +#define DMA_EPWM16A 66 +#define DMA_EPWM16B 67 + +#define DMA_TINT0 68 +#define DMA_TINT1 69 +#define DMA_TINT2 70 + +#define DMA_MXEVTA 71 +#define DMA_MREVTA 72 +#define DMA_MXEVTB 73 +#define DMA_MREVTB 74 + +#define DMA_SD1FLT1 95 +#define DMA_SD1FLT2 96 +#define DMA_SD1FLT3 97 +#define DMA_SD1FLT4 98 + +#define DMA_SD2FLT1 99 +#define DMA_SD2FLT2 100 +#define DMA_SD2FLT3 101 +#define DMA_SD2FLT4 102 + +#define DMA_SPIATX 109 +#define DMA_SPIARX 110 +#define DMA_SPIBTX 111 +#define DMA_SPIBRX 112 +#define DMA_SPICTX 113 +#define DMA_SPICRX 114 + +#define DMA_USBRX1 131 +#define DMA_USBTX1 132 +#define DMA_USBRX2 133 +#define DMA_USBTX2 134 +#define DMA_USBRX3 135 +#define DMA_USBTX3 136 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif + +#endif // - end of F2837xD_DMA_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h new file mode 100644 index 0000000000..a45ae46f62 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: F2837xD_EPwm_defines.h +// +// TITLE: #defines used in EPwm examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EPWM_DEFINES_H +#define F2837xD_EPWM_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// TBCTL (Time-Base Control) +// + +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// + +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// + +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// + +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// + +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// + +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// + +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// TZDCSEL (Trip Zone Digital Compare) +// + +// +// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits +// +#define TZ_EVT_DISABLE 0x0 +#define TZ_DCAH_LOW 0x1 +#define TZ_DCAH_HI 0x2 +#define TZ_DCAL_LOW 0x3 +#define TZ_DCAL_HI 0x4 +#define TZ_DCAL_HI_DCAH_LOW 0x5 + +#define TZ_DCBH_LOW 0x1 +#define TZ_DCBH_HI 0x2 +#define TZ_DCBL_LOW 0x3 +#define TZ_DCBL_HI 0x4 +#define TZ_DCBL_HI_DCBH_LOW 0x5 + +// +// ETSEL (Event Trigger Select) +// +#define ET_DCAEVT1SOC 0x0 +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTR_PRDZERO 0x3 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// + +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// + +// +// HRCNFG +// +#define HR_DISABLE 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 +#define HR_CTR_ZERO_PRD 0x2 + +#define HR_NORM_B 0x0 +#define HR_INVERT_B 0x1 + +// +// DC (Digital Compare) +// + +// +// DCTRIPSEL +// +#define DC_TZ1 0x0 +#define DC_TZ2 0x1 +#define DC_TZ3 0x2 +#define DC_TRIPIN1 0x0 +#define DC_TRIPIN2 0x1 +#define DC_TRIPIN3 0x2 +#define DC_TRIPIN4 0x3 +#define DC_TRIPIN5 0x4 +#define DC_TRIPIN6 0x5 +#define DC_TRIPIN7 0x6 +#define DC_TRIPIN8 0x7 +#define DC_TRIPIN9 0x8 +#define DC_TRIPIN10 0x9 +#define DC_TRIPIN11 0xA +#define DC_TRIPIN12 0xB +// Reserved 0xC +#define DC_TRIPIN14 0xD +#define DC_TRIPIN15 0xE +#define DC_COMBINATION 0xF + +// +// DCFCTL +// +#define DC_SRC_DCAEVT1 0x0 +#define DC_SRC_DCAEVT2 0x1 +#define DC_SRC_DCBEVT1 0x2 +#define DC_SRC_DCBEVT2 0x3 + +#define DC_PULSESEL_PRD 0x0 +#define DC_PULSESEL_ZERO 0x1 +#define DC_PULSESEL_ZERO_PRD 0x2 + +#define DC_BLANK_DISABLE 0x0 +#define DC_BLANK_ENABLE 0x1 + +#define DC_BLANK_NOTINV 0x0 +#define DC_BLANK_INV 0x1 + +// +//DCACTL/DCBCTL +// +#define DC_EVT1 0x0 +#define DC_EVT2 0x0 +#define DC_EVT_FLT 0x1 +#define DC_EVT_SYNC 0x0 +#define DC_EVT_ASYNC 0x1 +#define DC_SOC_DISABLE 0x0 +#define DC_SOC_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_EPWM_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h new file mode 100644 index 0000000000..cb11472b04 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h @@ -0,0 +1,319 @@ +//########################################################################### +// +// FILE: F2837xD_Emif_defines.h +// +// TITLE: #defines used in EMIF examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EMIF_DEFINES_H +#define F2837xD_EMIF_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +//cpu1 to cpu2 message for handshaking +// +#define CPU1_CPU2_MSG 0x3fd00 + +// +//cpu2_to_cpu1 message ram for handshaking +// +#define CPU2_CPU1_MSG 0x3fb00 + +#define MSEL_EMIF1_CPU1 0x93A5CE71 +#define MSEL_EMIF1_CPU2 0x93A5CE72 +#define MSEL_DEF_3 0x93A5CE73 +#define MSEL_DEF_0 0x93A5CE70 +#define MSEL_DEF_1 0x93A5CE71 +#define MSEL_DEF_2 0x93A5CE72 + +// +//soft reset bit register +// +#define EMIF_SOFT_PRES_REG 0x5D084 + +// +//Device capability/EMIF customization register +// +#define EMIF_DEV_DC_REG 0x5D014 + +// +// Values for ASYNC_CSx_CR Registers +// +#define EMIF_ASYNC_ASIZE_8 0x0 +#define EMIF_ASYNC_ASIZE_16 0x1 +#define EMIF_ASYNC_ASIZE_32 0x2 + +#define EMIF_ASYNC_TA_1 0x0 +#define EMIF_ASYNC_TA_2 0x4 +#define EMIF_ASYNC_TA_3 0x8 +#define EMIF_ASYNC_TA_4 0xC + +#define EMIF_ASYNC_RHOLD_1 0x00 +#define EMIF_ASYNC_RHOLD_2 0x10 +#define EMIF_ASYNC_RHOLD_3 0x20 +#define EMIF_ASYNC_RHOLD_4 0x30 +#define EMIF_ASYNC_RHOLD_5 0x40 +#define EMIF_ASYNC_RHOLD_6 0x50 +#define EMIF_ASYNC_RHOLD_7 0x60 +#define EMIF_ASYNC_RHOLD_8 0x70 + +#define EMIF_ASYNC_RSTROBE_1 0x0000 +#define EMIF_ASYNC_RSTROBE_2 0x0080 +#define EMIF_ASYNC_RSTROBE_3 0x0100 +#define EMIF_ASYNC_RSTROBE_4 0x0180 +#define EMIF_ASYNC_RSTROBE_5 0x0200 +#define EMIF_ASYNC_RSTROBE_6 0x0280 +#define EMIF_ASYNC_RSTROBE_7 0x0300 +#define EMIF_ASYNC_RSTROBE_8 0x0380 +#define EMIF_ASYNC_RSTROBE_9 0x0400 +#define EMIF_ASYNC_RSTROBE_10 0x0480 +#define EMIF_ASYNC_RSTROBE_11 0x0500 +#define EMIF_ASYNC_RSTROBE_12 0x0580 +#define EMIF_ASYNC_RSTROBE_13 0x0600 +#define EMIF_ASYNC_RSTROBE_14 0x0680 +#define EMIF_ASYNC_RSTROBE_15 0x0700 +#define EMIF_ASYNC_RSTROBE_16 0x0780 +#define EMIF_ASYNC_RSTROBE_17 0x0800 +#define EMIF_ASYNC_RSTROBE_18 0x0880 +#define EMIF_ASYNC_RSTROBE_19 0x0900 +#define EMIF_ASYNC_RSTROBE_20 0x0980 +#define EMIF_ASYNC_RSTROBE_21 0x0A00 +#define EMIF_ASYNC_RSTROBE_22 0x0A80 +#define EMIF_ASYNC_RSTROBE_23 0x0B00 +#define EMIF_ASYNC_RSTROBE_24 0x0B80 +#define EMIF_ASYNC_RSTROBE_25 0x0C00 +#define EMIF_ASYNC_RSTROBE_26 0x0C80 +#define EMIF_ASYNC_RSTROBE_27 0x0D00 +#define EMIF_ASYNC_RSTROBE_28 0x0D80 +#define EMIF_ASYNC_RSTROBE_29 0x0E00 +#define EMIF_ASYNC_RSTROBE_30 0x0E80 +#define EMIF_ASYNC_RSTROBE_31 0x0F00 +#define EMIF_ASYNC_RSTROBE_32 0x0F80 +#define EMIF_ASYNC_RSTROBE_33 0x1000 +#define EMIF_ASYNC_RSTROBE_34 0x1080 +#define EMIF_ASYNC_RSTROBE_35 0x1100 +#define EMIF_ASYNC_RSTROBE_36 0x1180 +#define EMIF_ASYNC_RSTROBE_37 0x1200 +#define EMIF_ASYNC_RSTROBE_38 0x1280 +#define EMIF_ASYNC_RSTROBE_39 0x1300 +#define EMIF_ASYNC_RSTROBE_40 0x1380 +#define EMIF_ASYNC_RSTROBE_41 0x1400 +#define EMIF_ASYNC_RSTROBE_42 0x1480 +#define EMIF_ASYNC_RSTROBE_43 0x1500 +#define EMIF_ASYNC_RSTROBE_44 0x1580 +#define EMIF_ASYNC_RSTROBE_45 0x1600 +#define EMIF_ASYNC_RSTROBE_46 0x1680 +#define EMIF_ASYNC_RSTROBE_47 0x1700 +#define EMIF_ASYNC_RSTROBE_48 0x1780 +#define EMIF_ASYNC_RSTROBE_49 0x1800 +#define EMIF_ASYNC_RSTROBE_50 0x1880 +#define EMIF_ASYNC_RSTROBE_51 0x1900 +#define EMIF_ASYNC_RSTROBE_52 0x1980 +#define EMIF_ASYNC_RSTROBE_53 0x1A00 +#define EMIF_ASYNC_RSTROBE_54 0x1A80 +#define EMIF_ASYNC_RSTROBE_55 0x1B00 +#define EMIF_ASYNC_RSTROBE_56 0x1B80 +#define EMIF_ASYNC_RSTROBE_57 0x1C00 +#define EMIF_ASYNC_RSTROBE_58 0x1C80 +#define EMIF_ASYNC_RSTROBE_59 0x1D00 +#define EMIF_ASYNC_RSTROBE_60 0x1D80 +#define EMIF_ASYNC_RSTROBE_61 0x1E00 +#define EMIF_ASYNC_RSTROBE_62 0x1E80 +#define EMIF_ASYNC_RSTROBE_63 0x1F00 +#define EMIF_ASYNC_RSTROBE_64 0x1F80 + +#define EMIF_ASYNC_RSETUP_1 0x0000 +#define EMIF_ASYNC_RSETUP_2 0x2000 +#define EMIF_ASYNC_RSETUP_3 0x4000 +#define EMIF_ASYNC_RSETUP_4 0x6000 +#define EMIF_ASYNC_RSETUP_5 0x8000 +#define EMIF_ASYNC_RSETUP_6 0xA000 +#define EMIF_ASYNC_RSETUP_7 0xC000 +#define EMIF_ASYNC_RSETUP_8 0xE000 +#define EMIF_ASYNC_RSETUP_9 0x10000 +#define EMIF_ASYNC_RSETUP_10 0x12000 +#define EMIF_ASYNC_RSETUP_11 0x14000 +#define EMIF_ASYNC_RSETUP_12 0x16000 +#define EMIF_ASYNC_RSETUP_13 0x18000 +#define EMIF_ASYNC_RSETUP_14 0x1A000 +#define EMIF_ASYNC_RSETUP_15 0x1C000 +#define EMIF_ASYNC_RSETUP_16 0x1E000 + +#define EMIF_ASYNC_WHOLD_1 0x00000 +#define EMIF_ASYNC_WHOLD_2 0x20000 +#define EMIF_ASYNC_WHOLD_3 0x40000 +#define EMIF_ASYNC_WHOLD_4 0x60000 +#define EMIF_ASYNC_WHOLD_5 0x80000 +#define EMIF_ASYNC_WHOLD_6 0xA0000 +#define EMIF_ASYNC_WHOLD_7 0xC0000 +#define EMIF_ASYNC_WHOLD_8 0xE0000 + +#define EMIF_ASYNC_WSTROBE_1 0x0000000 +#define EMIF_ASYNC_WSTROBE_2 0x0100000 +#define EMIF_ASYNC_WSTROBE_3 0x0200000 +#define EMIF_ASYNC_WSTROBE_4 0x0300000 +#define EMIF_ASYNC_WSTROBE_5 0x0400000 +#define EMIF_ASYNC_WSTROBE_6 0x0500000 +#define EMIF_ASYNC_WSTROBE_7 0x0600000 +#define EMIF_ASYNC_WSTROBE_8 0x0700000 +#define EMIF_ASYNC_WSTROBE_9 0x0800000 +#define EMIF_ASYNC_WSTROBE_10 0x0900000 +#define EMIF_ASYNC_WSTROBE_11 0x0A00000 +#define EMIF_ASYNC_WSTROBE_12 0x0B00000 +#define EMIF_ASYNC_WSTROBE_13 0x0C00000 +#define EMIF_ASYNC_WSTROBE_14 0x0D00000 +#define EMIF_ASYNC_WSTROBE_15 0x0E00000 +#define EMIF_ASYNC_WSTROBE_16 0x0F00000 +#define EMIF_ASYNC_WSTROBE_17 0x1000000 +#define EMIF_ASYNC_WSTROBE_18 0x1100000 +#define EMIF_ASYNC_WSTROBE_19 0x1200000 +#define EMIF_ASYNC_WSTROBE_20 0x1300000 +#define EMIF_ASYNC_WSTROBE_21 0x1400000 +#define EMIF_ASYNC_WSTROBE_22 0x1500000 +#define EMIF_ASYNC_WSTROBE_23 0x1600000 +#define EMIF_ASYNC_WSTROBE_24 0x1700000 +#define EMIF_ASYNC_WSTROBE_25 0x1800000 +#define EMIF_ASYNC_WSTROBE_26 0x1900000 +#define EMIF_ASYNC_WSTROBE_27 0x1A00000 +#define EMIF_ASYNC_WSTROBE_28 0x1B00000 +#define EMIF_ASYNC_WSTROBE_29 0x1C00000 +#define EMIF_ASYNC_WSTROBE_30 0x1D00000 +#define EMIF_ASYNC_WSTROBE_31 0x1E00000 +#define EMIF_ASYNC_WSTROBE_32 0x1F00000 +#define EMIF_ASYNC_WSTROBE_33 0x2000000 +#define EMIF_ASYNC_WSTROBE_34 0x2100000 +#define EMIF_ASYNC_WSTROBE_35 0x2200000 +#define EMIF_ASYNC_WSTROBE_36 0x2300000 +#define EMIF_ASYNC_WSTROBE_37 0x2400000 +#define EMIF_ASYNC_WSTROBE_38 0x2500000 +#define EMIF_ASYNC_WSTROBE_39 0x2600000 +#define EMIF_ASYNC_WSTROBE_40 0x2700000 +#define EMIF_ASYNC_WSTROBE_41 0x2800000 +#define EMIF_ASYNC_WSTROBE_42 0x2900000 +#define EMIF_ASYNC_WSTROBE_43 0x2A00000 +#define EMIF_ASYNC_WSTROBE_44 0x2B00000 +#define EMIF_ASYNC_WSTROBE_45 0x2C00000 +#define EMIF_ASYNC_WSTROBE_46 0x2D00000 +#define EMIF_ASYNC_WSTROBE_47 0x2E00000 +#define EMIF_ASYNC_WSTROBE_48 0x2F00000 +#define EMIF_ASYNC_WSTROBE_49 0x3000000 +#define EMIF_ASYNC_WSTROBE_50 0x3100000 +#define EMIF_ASYNC_WSTROBE_51 0x3200000 +#define EMIF_ASYNC_WSTROBE_52 0x3300000 +#define EMIF_ASYNC_WSTROBE_53 0x3400000 +#define EMIF_ASYNC_WSTROBE_54 0x3500000 +#define EMIF_ASYNC_WSTROBE_55 0x3600000 +#define EMIF_ASYNC_WSTROBE_56 0x3700000 +#define EMIF_ASYNC_WSTROBE_57 0x3800000 +#define EMIF_ASYNC_WSTROBE_58 0x3900000 +#define EMIF_ASYNC_WSTROBE_59 0x3A00000 +#define EMIF_ASYNC_WSTROBE_60 0x3B00000 +#define EMIF_ASYNC_WSTROBE_61 0x3C00000 +#define EMIF_ASYNC_WSTROBE_62 0x3D00000 +#define EMIF_ASYNC_WSTROBE_63 0x3E00000 +#define EMIF_ASYNC_WSTROBE_64 0x3F00000 + +#define EMIF_ASYNC_WSETUP_1 0x00000000 +#define EMIF_ASYNC_WSETUP_2 0x04000000 +#define EMIF_ASYNC_WSETUP_3 0x08000000 +#define EMIF_ASYNC_WSETUP_4 0x0C000000 +#define EMIF_ASYNC_WSETUP_5 0x10000000 +#define EMIF_ASYNC_WSETUP_6 0x14000000 +#define EMIF_ASYNC_WSETUP_7 0x18000000 +#define EMIF_ASYNC_WSETUP_8 0x1C000000 +#define EMIF_ASYNC_WSETUP_9 0x20000000 +#define EMIF_ASYNC_WSETUP_10 0x24000000 +#define EMIF_ASYNC_WSETUP_11 0x28000000 +#define EMIF_ASYNC_WSETUP_12 0x2C000000 +#define EMIF_ASYNC_WSETUP_13 0x30000000 +#define EMIF_ASYNC_WSETUP_14 0x34000000 +#define EMIF_ASYNC_WSETUP_15 0x38000000 +#define EMIF_ASYNC_WSETUP_16 0x3C000000 + +#define EMIF_ASYNC_EW_DISABLE 0x00000000 +#define EMIF_ASYNC_EW_ENABLE 0x40000000 + +#define EMIF_ASYNC_SS_DISABLE 0x00000000 +#define EMIF_ASYNC_SS_ENABLE 0x80000000 + +// +// Values for ASYNC_WCCR Register +// +#define EMIF_ASYNC_WCCR_WP_LOW 0x00000000 +#define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000 + +// +// Read mask for the registers which has reserved bits. +// +#define ASYNC_WCCR_RDMASK 0xF0FF00FF +#define SDRAM_CR_RDMASK 0xE3FF7F7F +#define SDRAM_RCR_RDMASK 0x00071FFF +#define SDRAM_TR_RDMASK 0xFF77FF70 +#define SDR_EXT_TMNG_RDMASK 0x1F +#define INT_RAW_RDMASK 0x3F +#define INT_MASK_RDMASK 0x3F +#define IO_CTRL_RDMASK_RDMASK 0xFFFF +#define IO_STAT_RDMASK_RDMASK 0xF +#define NAND_FLASH_CTRL_RDMASK 0x3F3F +#define NAND_FLASH_STAT_RDMASK 0x30F0F +#define IODFT_TLECR_REG_RDMASK 0xFFFF +#define IODFT_TLGCR_REG_RDMASK 0x71FF +#define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF +#define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07 +#define MODEL_REL_NUM_REG_RDMASK 0xFF +#define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F +#define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff +#define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff +#define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_EMIF_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h new file mode 100644 index 0000000000..bd3a3994b0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h @@ -0,0 +1,448 @@ +//########################################################################### +// +// FILE: F2837xD_Examples.h +// +// TITLE: F2837xD Device Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EXAMPLES_H +#define F2837xD_EXAMPLES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier +// +#define IMULT_0 0 +#define IMULT_1 1 +#define IMULT_2 2 +#define IMULT_3 3 +#define IMULT_4 4 +#define IMULT_5 5 +#define IMULT_6 6 +#define IMULT_7 7 +#define IMULT_8 8 +#define IMULT_9 9 +#define IMULT_10 10 +#define IMULT_11 11 +#define IMULT_12 12 +#define IMULT_13 13 +#define IMULT_14 14 +#define IMULT_15 15 +#define IMULT_16 16 +#define IMULT_17 17 +#define IMULT_18 18 +#define IMULT_19 19 +#define IMULT_20 20 +#define IMULT_21 21 +#define IMULT_22 22 +#define IMULT_23 23 +#define IMULT_24 24 +#define IMULT_25 25 +#define IMULT_26 26 +#define IMULT_27 27 +#define IMULT_28 28 +#define IMULT_29 29 +#define IMULT_30 30 +#define IMULT_31 31 +#define IMULT_32 32 +#define IMULT_33 33 +#define IMULT_34 34 +#define IMULT_35 35 +#define IMULT_36 36 +#define IMULT_37 37 +#define IMULT_38 38 +#define IMULT_39 39 +#define IMULT_40 40 +#define IMULT_41 41 +#define IMULT_42 42 +#define IMULT_43 43 +#define IMULT_44 44 +#define IMULT_45 45 +#define IMULT_46 46 +#define IMULT_47 47 +#define IMULT_48 48 +#define IMULT_49 49 +#define IMULT_50 50 +#define IMULT_51 51 +#define IMULT_52 52 +#define IMULT_53 53 +#define IMULT_54 54 +#define IMULT_55 55 +#define IMULT_56 56 +#define IMULT_57 57 +#define IMULT_58 58 +#define IMULT_59 59 +#define IMULT_60 60 +#define IMULT_61 61 +#define IMULT_62 62 +#define IMULT_63 63 +#define IMULT_64 64 +#define IMULT_65 65 +#define IMULT_66 66 +#define IMULT_67 67 +#define IMULT_68 68 +#define IMULT_69 69 +#define IMULT_70 70 +#define IMULT_71 71 +#define IMULT_72 72 +#define IMULT_73 73 +#define IMULT_74 74 +#define IMULT_75 75 +#define IMULT_76 76 +#define IMULT_77 77 +#define IMULT_78 78 +#define IMULT_79 79 +#define IMULT_80 80 +#define IMULT_81 81 +#define IMULT_82 82 +#define IMULT_83 83 +#define IMULT_84 84 +#define IMULT_85 85 +#define IMULT_86 86 +#define IMULT_87 87 +#define IMULT_88 88 +#define IMULT_89 89 +#define IMULT_90 90 +#define IMULT_91 91 +#define IMULT_92 92 +#define IMULT_93 93 +#define IMULT_94 94 +#define IMULT_95 95 +#define IMULT_96 96 +#define IMULT_97 97 +#define IMULT_98 98 +#define IMULT_99 99 +#define IMULT_100 100 +#define IMULT_101 101 +#define IMULT_102 102 +#define IMULT_103 103 +#define IMULT_104 104 +#define IMULT_105 105 +#define IMULT_106 106 +#define IMULT_107 107 +#define IMULT_108 108 +#define IMULT_109 109 +#define IMULT_110 110 +#define IMULT_111 111 +#define IMULT_112 112 +#define IMULT_113 113 +#define IMULT_114 114 +#define IMULT_115 115 +#define IMULT_116 116 +#define IMULT_117 117 +#define IMULT_118 118 +#define IMULT_119 119 +#define IMULT_120 120 +#define IMULT_121 121 +#define IMULT_122 122 +#define IMULT_123 123 +#define IMULT_124 124 +#define IMULT_125 125 +#define IMULT_126 126 +#define IMULT_127 127 + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier +// +#define FMULT_0 0 +#define FMULT_0pt25 1 +#define FMULT_0pt5 2 +#define FMULT_0pt75 3 + +// +// The following are values that can be passed to the +// InitSysPll() to select divsel for SYSPLL +// +#define PLLCLK_BY_1 0 +#define PLLCLK_BY_2 1 +#define PLLCLK_BY_4 2 +#define PLLCLK_BY_6 3 +#define PLLCLK_BY_8 4 +#define PLLCLK_BY_10 5 +#define PLLCLK_BY_12 6 +#define PLLCLK_BY_14 7 +#define PLLCLK_BY_16 8 +#define PLLCLK_BY_18 9 +#define PLLCLK_BY_20 10 +#define PLLCLK_BY_22 11 +#define PLLCLK_BY_24 12 +#define PLLCLK_BY_26 13 +#define PLLCLK_BY_28 14 +#define PLLCLK_BY_30 15 +#define PLLCLK_BY_32 16 +#define PLLCLK_BY_34 17 +#define PLLCLK_BY_36 18 +#define PLLCLK_BY_38 19 +#define PLLCLK_BY_40 20 +#define PLLCLK_BY_42 21 +#define PLLCLK_BY_44 22 +#define PLLCLK_BY_46 23 +#define PLLCLK_BY_48 24 +#define PLLCLK_BY_50 25 +#define PLLCLK_BY_52 26 +#define PLLCLK_BY_54 27 +#define PLLCLK_BY_56 28 +#define PLLCLK_BY_58 29 +#define PLLCLK_BY_60 30 +#define PLLCLK_BY_62 31 +#define PLLCLK_BY_64 32 +#define PLLCLK_BY_66 33 +#define PLLCLK_BY_68 34 +#define PLLCLK_BY_70 35 +#define PLLCLK_BY_72 36 +#define PLLCLK_BY_74 37 +#define PLLCLK_BY_76 38 +#define PLLCLK_BY_78 39 +#define PLLCLK_BY_80 40 +#define PLLCLK_BY_82 41 +#define PLLCLK_BY_84 42 +#define PLLCLK_BY_86 43 +#define PLLCLK_BY_88 44 +#define PLLCLK_BY_90 45 +#define PLLCLK_BY_92 46 +#define PLLCLK_BY_94 47 +#define PLLCLK_BY_96 48 +#define PLLCLK_BY_98 49 +#define PLLCLK_BY_100 50 +#define PLLCLK_BY_102 51 +#define PLLCLK_BY_104 52 +#define PLLCLK_BY_106 53 +#define PLLCLK_BY_108 54 +#define PLLCLK_BY_110 55 +#define PLLCLK_BY_112 56 +#define PLLCLK_BY_114 57 +#define PLLCLK_BY_116 58 +#define PLLCLK_BY_118 59 +#define PLLCLK_BY_120 60 +#define PLLCLK_BY_122 61 +#define PLLCLK_BY_124 62 +#define PLLCLK_BY_126 63 + +// +// The following are values that can be passed to the +// InitAuxPll() to select divsel for AUXPLL +// +#define AUXPLLRAWCLK_BY_1 0 +#define AUXPLLRAWCLK_BY_2 1 +#define AUXPLLRAWCLK_BY_4 2 +#define AUXPLLRAWCLK_BY_8 3 + +// +// The following are values that can be passed to the +// IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL +// +#define SYSTEM_PLL (Uint16) 0 +#define AUX_PLL (Uint16) 1 + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select clock source +// +#define INT_OSC2 0 +#define XTAL_OSC 1 +#define INT_OSC1 2 +#define AUXCLKIN 4 + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example: 200 MHz devices: +// CLKIN is a 10 MHz crystal or internal 10 MHz oscillator +// +// In step 1 the user specified the PLL multiplier = 40 for a +// 200 MHz CPU clock (SYSCLKOUT = 200 MHz). +// +// In this case, the CPU_RATE will be 5.000L +// Uncomment the line: #define CPU_RATE 5.000L +// + +#define CPU_RATE 5.00L // for a 200MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) + +// +// The following pointer to a function call calibrates the ADC reference, +// DAC offset, and internal oscillators +// +#define Device_cal (void (*)(void))0x070282 + +// +// The following pointers to functions calibrate the ADC linearity. Use this +// in the AdcSetMode(...) function only +// +#define CalAdcaINL (void (*)(void))0x0703B4 +#define CalAdcbINL (void (*)(void))0x0703B2 +#define CalAdccINL (void (*)(void))0x0703B0 +#define CalAdcdINL (void (*)(void))0x0703AE + +// +// The following pointer to a function call looks up the ADC offset trim for a +// given condition. Use this in the AdcSetMode(...) function only. +// +#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC + +// +// Includes +// +#include "F2837xD_GlobalPrototypes.h" // Prototypes for global functions + // within the .c files. +#include "F2837xD_cputimervars.h" +#include "F2837xD_Cla_defines.h" // Macros used for CLA examples. +#include "F2837xD_EPwm_defines.h" // Macros used for PWM examples. +#include "F2837xD_Adc_defines.h" // Macros used for ADC examples. +#include "F2837xD_Emif_defines.h" // Macros used for EMIF examples. +#include "F2837xD_Gpio_defines.h" // Macros used for GPIO support code +#include "F2837xD_I2c_defines.h" // Macros used for I2C examples. +#include "F2837xD_Ipc_defines.h" // Macros used for IPC support code. +#include "F2837xD_Pie_defines.h" // Macros used for PIE examples. +#include "F2837xD_Dma_defines.h" // Macros used for DMA examples. +#include "F2837xD_SysCtrl_defines.h" // Macros used for LPM support code +#include "F2837xD_Upp_defines.h" // Macros used for UPP examples. + +#define PARTNO_2837xPACKAGEHERE 0x00 + +#define CPU_FRQ_200MHZ 1 +#define CPU_FRQ_150MHZ 0 +#define CPU_FRQ_120MHZ 0 + +// +// Include files not used with F/BIOS +// +#ifndef F28_BIOS +#include "F2837xD_defaultisr.h" +#endif + +extern void F28x_usDelay(long LoopCount); + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) + +// +// Timer Operations: +// + +// +// Start Timer: +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// Start Timer: +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of F2837xD_EXAMPLES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h new file mode 100644 index 0000000000..1b63dc48ee --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: F2837xD_GlobalPrototypes.h +// +// TITLE: Global prototypes for F2837xD Examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_GLOBALPROTOTYPES_H +#define F2837xD_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Function Prototypes (Shared) +// +extern void EnableInterrupts(void); +extern void InitAPwm1Gpio(void); +extern void InitCAN(void); +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(Uint16 pin); +extern void InitECap2Gpio(Uint16 pin); +extern void InitECap3Gpio(Uint16 pin); +extern void InitECap4Gpio(Uint16 pin); +extern void InitECap5Gpio(Uint16 pin); +extern void InitECap6Gpio(Uint16 pin); +extern void InitEQep1Gpio(void); +extern void InitEQep2Gpio(void); +extern void InitEQep3Gpio(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +extern void InitEPwm4Gpio(void); +extern void InitEPwm5Gpio(void); +extern void InitEPwm6Gpio(void); +extern void InitEPwm7Gpio(void); +extern void InitEPwm8Gpio(void); +extern void InitEPwm9Gpio(void); +extern void InitEPwm10Gpio(void); +extern void InitEPwm11Gpio(void); +extern void InitEPwm12Gpio(void); +extern void InitPeripheralClocks(void); +extern void DisablePeripheralClocks(void); +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, + Uint16 divsel); +extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, + Uint16 divsel); + +#define KickDog ServiceDog // For compatibility with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); + +extern Uint16 CsmUnlock(void); +extern void SysIntOsc1Sel (void); +extern void SysIntOsc2Sel (void); +extern void SysXtalOscSel (void); + +extern void AuxIntOsc2Sel (void); +extern void AuxXtalOscSel (void); +extern void AuxAuxClkSel (void); + +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); +extern void InitFlash_Bank0(void); +extern void InitFlash_Bank1(void); +extern void FlashOff(void); +extern void FlashOff_Bank0(void); +extern void FlashOff_Bank1(void); +extern void SeizeFlashPump(void); +extern void SeizeFlashPump_Bank0(void); +extern void SeizeFlashPump_Bank1(void); +extern void ReleaseFlashPump(void); + +// +//LPM functions in F2837xD_SysCtrl.c +// +void IDLE(); +void STANDBY(); +void HALT(); +void HIB(); + +// +//ADC functions +// +extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode); +extern void CalAdcINL(Uint16 adc); + +// +// DMA Functions +// +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +// +//GPIO Functions +// +extern void InitGpio(); +extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition); +extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags); +extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); +extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); +extern void GPIO_SelectIpcInt(Uint16 newFlag); +extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); +extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); +extern void GPIO_EnableUnbondedIOPullups(void); +Uint16 GPIO_ReadPin(Uint16 gpioNumber); +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); + +// +//IPC Functions +// +extern void InitIpc(); +extern Uint64 ReadIpcTimer(); +extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag); +extern void RecvIpcData(void *recv_buf, Uint16 word_length); +extern void FillIpcSendData(Uint16 fill_data); +extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, + Uint16 flag); +extern void SendIpcFlag(Uint16 flag); +extern void AckIpcFlag(Uint16 flag); +extern void CancelIpcFlag(Uint16 flag); +extern void WaitForIpcFlag(Uint16 flag); +extern void WaitForIpcAck(Uint16 flag); +extern void IpcSync(Uint16 flag); + +// +// CAN Functions +// +extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin); +extern void CanAGpioConfig(Uint16 canaTxRxPin); +extern void CanBGpioConfig(Uint16 canbTxRxPin); +extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource); + +// +// I2C Functions +// +extern void I2cAGpioConfig(Uint16 I2caDataClkPin); +extern void I2cBGpioConfig(Uint16 I2cbDataClkPin); + +// +// McBSP functions +// McBSPA +// +extern void InitMcbspa(void); +extern void InitMcbspaInt(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +extern void InitMcbspaGpio(void); +extern void delay_loop(void); + +// +// McBSPB +// +extern void InitMcbspb(void); +extern void InitMcbspbInt(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +extern void InitMcbspbGpio(void); + +// +//Temp Sensor Functions +// +extern void InitTempSensor(float32 vrefhi_voltage); +extern int16 GetTemperatureC(int16 sensorSample); +extern int16 GetTemperatureK(int16 sensorSample); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in Flash to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsLoadSize; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsRunEnd; +extern Uint16 RamfuncsRunSize; + +// +// External Boot ROM variable definitions +// +extern Uint16 EmuBMode; +extern Uint16 EmuBootPins; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_GLOBALPROTOTYPES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h new file mode 100644 index 0000000000..ecbff65618 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h @@ -0,0 +1,116 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio_defines.h +// +// TITLE: F2837xD GPIO support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_GPIO_DEFINES_H +#define F2837xD_GPIO_DEFINES_H + +// +// Defines +// + +// +//CPU pin masters for GPIO_SelectPinMux() +// +#define GPIO_MUX_CPU1 0x0 +#define GPIO_MUX_CPU1CLA 0x1 +#define GPIO_MUX_CPU2 0x2 +#define GPIO_MUX_CPU2CLA 0x3 + +// +//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, +//QUAL6, and ASYNC) take up two bits and must be in the order specified. +// +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 +#define GPIO_PUSHPULL 0 +#define GPIO_PULLUP (1 << 0) +#define GPIO_INVERT (1 << 1) +#define GPIO_OPENDRAIN (1 << 2) +#define GPIO_SYNC (0x0 << 4) +#define GPIO_QUAL3 (0x1 << 4) +#define GPIO_QUAL6 (0x2 << 4) +#define GPIO_ASYNC (0x3 << 4) + +// +//Flags for GPIO_SetupLock(). +// +#define GPIO_UNLOCK 0 +#define GPIO_LOCK 1 + +// +//Commands for the CPU2->CPU1 GPIO configuration interrupt handler +// +#define GPIO_CMD_INIT 1L +#define GPIO_CMD_PINMUX 2L +#define GPIO_CMD_PINOPTS 3L +#define GPIO_CMD_WRITE32 4L +#define GPIO_CMD_WRITE16 5L +#define GPIO_CMD_READ32 6L +#define GPIO_CMD_READ16 7L + +// +//Helpful constants for array-based access to GPIO registers +// +#define GPY_CTRL_OFFSET (0x40/2) +#define GPY_DATA_OFFSET (0x8/2) + +#define GPYQSEL (0x2/2) +#define GPYMUX (0x6/2) +#define GPYDIR (0xA/2) +#define GPYPUD (0xC/2) +#define GPYINV (0x10/2) +#define GPYODR (0x12/2) +#define GPYGMUX (0x20/2) +#define GPYCSEL (0x28/2) +#define GPYLOCK (0x3C/2) +#define GPYCR (0x3E/2) + +#define GPYDAT (0x0/2) +#define GPYSET (0x2/2) +#define GPYCLEAR (0x4/2) +#define GPYTOGGLE (0x6/2) + +#endif // end of F2837xD_GPIO_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h new file mode 100644 index 0000000000..95ed970e7f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h @@ -0,0 +1,184 @@ +//########################################################################### +// +// FILE: F2837xD_I2c_defines.h +// +// TITLE: F2837xD I2C Common Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_I2C_DEFINES_H +#define F2837xD_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + + +// +// These are the Defines to select I2C pin muxing when calling the functions +// I2cAGpioConfig() & I2cBGpioConfig() in F2837xD_I2C.c +// +#define I2C_A_GPIO0_GPIO1 1 //switch case 1 +#define I2C_A_GPIO32_GPIO33 2 //switch case 2 +#define I2C_A_GPIO42_GPIO43 3 //switch case 3 +#define I2C_A_GPIO91_GPIO92 4 //switch case 4 +#define I2C_A_GPIO63104_GPIO105 5 //switch case 5 + +#define I2C_B_GPIO2_GPIO3 1 //switch case 1 +#define I2C_B_GPIO134_GPIO35 2 //switch case 2 +#define I2C_B_GPIO40_GPIO41 3 //switch case 3 +#define I2C_B_GPIO66_GPIO69 4 //switch case 4 + +// +// Globals +// + +// +// I2C Message Structure +// +struct I2CMSG { + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a + // restart as a master receiver with a + // stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put + // in MsgBuffer) + Uint16 MemoryHighAddr; // EEPROM address of data associated with + // msg (high byte) + Uint16 MemoryLowAddr; // EEPROM address of data associated with + // msg (low byte) + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that + // MAX_BUFFER_SIZE can be is 16 due + // to the FIFO's +}; + +#endif // end of F2837xD_I2C_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h new file mode 100644 index 0000000000..404caee0b1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_defines.h +// +// TITLE: F2837xD IPC support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_IPC_DEFINES_H +#define F2837xD_IPC_DEFINES_H + +// +// Defines +// +#define C1TOC2_MSG_RAM ((void *)0x3FC00) +#define C2TOC1_MSG_RAM ((void *)0x3F800) + +#if defined(CPU1) + #define SEND_MSG_RAM C1TOC2_MSG_RAM + #define RECV_MSG_RAM C2TOC1_MSG_RAM +#elif defined(CPU2) + #define SEND_MSG_RAM C2TOC1_MSG_RAM + #define RECV_MSG_RAM C1TOC2_MSG_RAM +#endif +#define MSG_RAM_SIZE 0x400 + +// +//Used with SendIpcData() and SendIpcCommand() to avoid setting a flag +// +#define NO_IPC_FLAG 32 + +#endif // end of F2837xD_IPC_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h new file mode 100644 index 0000000000..648ad6a83a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h @@ -0,0 +1,511 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_drivers.h +// +// TITLE: Defines and Macros for the IPC Controller +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +//! \addtogroup ipc_driver_api +//! @{ +// + +#ifndef F2837xD_IPC_DRIVERS_H +#define F2837xD_IPC_DRIVERS_H + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" { +#endif + +// +// Included Files +// +#include "F2837xD_device.h" + +// +// Defines +// + +// +// The following are values that are used to define the maximum size of the +// global circular buffer variables g_asIPCCPU1toCPU2Buffers and +// g_asIPCCPU2toCPU1Buffers. They are also used in the IpcPut() and IpcGet() +// functions. IPC_BUFFER_SIZE and NUM_IPC_INTERRUPTS are user-configurable. +// +#define IPC_BUFFER_SIZE 4 // # of tIpcMessage messages in + // circular buffer + // (must be interval of 2) +#define NUM_IPC_INTERRUPTS 4 // # of IPC interrupts using circular + // buffer + // (must be same number on both CPUs +#define MAX_BUFFER_INDEX IPC_BUFFER_SIZE - 1 + +// +// The following are values that can be passed to IPCInitialize() +// as the usCPU1IpcInterrupt and usCPU2IpcInterrupt parameters +// +#define IPC_INT0 0x0001 +#define IPC_INT1 0x0002 +#define IPC_INT2 0x0003 +#define IPC_INT3 0x0004 + +// +// The following are values that are returned from all of the IPCCtoM command +// functions to determine whether the command was successfully sent or not. +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +// +// The following are values that can be passed to IPCReqMemAccess() as +// usMaster parameter to determine which processor to give master access to +// GSx blocks. +// +#define IPC_GSX_CPU1_MASTER 0x0001 +#define IPC_GSX_CPU2_MASTER 0x0000 + +// +// The following are values that can be passed to all IPC CPU1 to CPU2 or +// CPU2 to CPU1 command functions as bBlock parameter to determine whether to +// wait/block until a slot in PutBuffer is available if it is full, or to exit +// with a failure status. +// +#define ENABLE_BLOCKING 0x0001 +#define DISABLE_BLOCKING 0x0000 + +// +// The following are values that can be passed to IPCCtoMDataRead(), +// IPCCCtoMSetBits(),IPCCCtoMSetBits_Protected(), IPCCCtoMClearBits(), +// IPCCCtoMClearBits_Protected(), IPCCCtoMDataWrite(), +// IPCCtoMDataWrite_Protected() +// as usLength parameter to determine whether command applies to 16- or 32-bit +// data word. +// +#define IPC_LENGTH_16_BITS 0x00000001 +#define IPC_LENGTH_32_BITS 0x00000002 + +// +// The following are values that can be passed to IPCReqMemAccess() as +// ulMask parameter to configure GSxMSEL_REG register for master access to Sx +// RAM block. +// +#define GS0_ACCESS 0x00000001 // Master Access to GS0 +#define GS1_ACCESS 0x00000002 // Master Access to GS1 +#define GS2_ACCESS 0x00000004 // Master Access to GS2 +#define GS3_ACCESS 0x00000008 // Master Access to GS3 +#define GS4_ACCESS 0x00000010 // Master Access to GS4 +#define GS5_ACCESS 0x00000020 // Master Access to GS5 +#define GS6_ACCESS 0x00000040 // Master Access to GS6 +#define GS7_ACCESS 0x00000080 // Master Access to GS7 +#define GS8_ACCESS 0x00000100 // Master Access to GS8 +#define GS9_ACCESS 0x00000200 // Master Access to GS9 +#define GS10_ACCESS 0x00000400 // Master Access to GS10 +#define GS11_ACCESS 0x00000800 // Master Access to GS11 +#define GS12_ACCESS 0x00001000 // Master Access to GS12 +#define GS13_ACCESS 0x00002000 // Master Access to GS13 +#define GS14_ACCESS 0x00004000 // Master Access to GS14 +#define GS15_ACCESS 0x00008000 // Master Access to GS15 + +// +// The following are values that can be passed to IPCCtoMTaskBusy() as the +// ulFlags parameter. +// IPC_FLAG17 - IPC_FLAG32 can also be passed to IPCtoMDataRead() and +// IPCCtoMReadBlock() as the ulResponseFlag parameter. +// +#define NO_FLAG 0x00000000 // NO FLAG +#define IPC_FLAG0 0x00000001 // IPC FLAG 0 +#define IPC_FLAG1 0x00000002 // IPC FLAG 1 +#define IPC_FLAG2 0x00000004 // IPC FLAG 2 +#define IPC_FLAG3 0x00000008 // IPC FLAG 3 +#define IPC_FLAG4 0x00000010 // IPC FLAG 4 +#define IPC_FLAG5 0x00000020 // IPC FLAG 5 +#define IPC_FLAG6 0x00000040 // IPC FLAG 6 +#define IPC_FLAG7 0x00000080 // IPC FLAG 7 +#define IPC_FLAG8 0x00000100 // IPC FLAG 8 +#define IPC_FLAG9 0x00000200 // IPC FLAG 9 +#define IPC_FLAG10 0x00000400 // IPC FLAG 10 +#define IPC_FLAG11 0x00000800 // IPC FLAG 11 +#define IPC_FLAG12 0x00001000 // IPC FLAG 12 +#define IPC_FLAG13 0x00002000 // IPC FLAG 13 +#define IPC_FLAG14 0x00004000 // IPC FLAG 14 +#define IPC_FLAG15 0x00008000 // IPC FLAG 15 +#define IPC_FLAG16 0x00010000 // IPC FLAG 16 +#define IPC_FLAG17 0x00020000 // IPC FLAG 17 +#define IPC_FLAG18 0x00040000 // IPC FLAG 18 +#define IPC_FLAG19 0x00080000 // IPC FLAG 19 +#define IPC_FLAG20 0x00100000 // IPC FLAG 20 +#define IPC_FLAG21 0x00200000 // IPC FLAG 21 +#define IPC_FLAG22 0x00400000 // IPC FLAG 22 +#define IPC_FLAG23 0x00800000 // IPC FLAG 23 +#define IPC_FLAG24 0x01000000 // IPC FLAG 24 +#define IPC_FLAG25 0x02000000 // IPC FLAG 25 +#define IPC_FLAG26 0x04000000 // IPC FLAG 26 +#define IPC_FLAG27 0x08000000 // IPC FLAG 27 +#define IPC_FLAG28 0x10000000 // IPC FLAG 28 +#define IPC_FLAG29 0x20000000 // IPC FLAG 29 +#define IPC_FLAG30 0x40000000 // IPC FLAG 30 +#define IPC_FLAG31 0x80000000 // IPC FLAG 31 + +// +// The following are values that are used by all command functions and passed +// between processors in tIpcMessage.ulmessage or in the xTOyIPCCOM register +// to determine what command is requested by the sending processor. +// +#define IPC_SET_BITS_16 0x00000001 // Used for IPC-Lite +#define IPC_SET_BITS_32 0x00000002 // Used for IPC-Lite +#define IPC_CLEAR_BITS_16 0x00000003 // Used for IPC-Lite +#define IPC_CLEAR_BITS_32 0x00000004 // Used for IPC-Lite +#define IPC_DATA_WRITE_16 0x00000005 // Used for IPC-Lite +#define IPC_DATA_WRITE_32 0x00000006 // Used for IPC-Lite +#define IPC_DATA_READ_16 0x00000007 // Used for Boot ROM +#define IPC_DATA_READ_32 0x00000008 // Used for Boot ROM +#define IPC_DATA_READ 0x00000008 +#define IPC_SET_BITS_16_PROTECTED 0x00000009 // Used for IPC-Lite +#define IPC_SET_BITS_32_PROTECTED 0x0000000A // Used for IPC-Lite +#define IPC_CLEAR_BITS_16_PROTECTED 0x0000000B // Used for IPC-Lite +#define IPC_CLEAR_BITS_32_PROTECTED 0x0000000C // Used for IPC-Lite +#define IPC_DATA_WRITE_16_PROTECTED 0x0000000D // Used for IPC-Lite +#define IPC_DATA_WRITE_32_PROTECTED 0x0000000E // Used for IPC-Lite + +// +// 0x0000000F and 0x0000010 are reserved by boot ROM +// + +#define IPC_BRANCH 0x00000011 +#define IPC_FUNC_CALL 0x00000012 +#define IPC_MTOC_EXECUTE_BOOTMODE_CMD 0x00000013 + +#define IPC_SET_BITS 0x00010001 +#define IPC_CLEAR_BITS 0x00010002 +#define IPC_DATA_WRITE 0x00010003 +#define IPC_BLOCK_READ 0x00010004 +#define IPC_BLOCK_WRITE 0x00010005 +#define IPC_DATA_READ_PROTECTED 0x00010007 +#define IPC_SET_BITS_PROTECTED 0x00010008 +#define IPC_CLEAR_BITS_PROTECTED 0x00010009 +#define IPC_DATA_WRITE_PROTECTED 0x0001000A +#define IPC_BLOCK_WRITE_PROTECTED 0x0001000B + +// +// The following are values that can be passed into the +// IPCBootControlSystem() function in the ulBootMode parameter. +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013 + +// +// Below are the values programmed into IPCBOOTMODE register +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000A +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000B + +// +// The following value is used by the +// IPCBootControlSystem() function to limit the allowed boot mode values. +// +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000C + +// +// The following values report on the CPU02 boot ROM status at all times while +// the CPU02 is booting, and will reside in IPCBOOTSTS[11:0]. +// + +// +// CPU02 has not filled in a valid value yet +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000 + +// +// CPU02 has started to boot, but not completed +// the boot process yet +// +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001 + +// +// CPU02 has completed the boot and is ready for +// CPU01 TO CPU02 IPC commands +// +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002 + +// +// CPU02 ACKs the command in CPU01 TO CPU01 +// BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003 + +// +// CPU02 un-supported command in CPU01 TO CPU01 +// BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004 + +// +// CPU2 NAKs the current boot command in +// CPU01 TO CPU01 BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005 + +// +//! A structure that defines an IPC message. These fields are used by the +//! IPC drivers to determine handling of data passed between processors. +//! Although they have a defined naming scheme, they can also be used +//! generically +//! to pass 32-bit data words between processors. +// +typedef struct +{ + //! The command passed between processor systems. + uint32_t ulcommand; + + //! The receiving processor address the command is requesting action on. + uint32_t uladdress; + + //! A 32-bit variable, the usage of which is determined by ulcommand. + //! The most common usage is to pass length requirements + //! with the upper 16-bits storing a Response Flag for read commands. + uint32_t uldataw1; + + //! A 32-bit variable, the usage of which is determined by ulcommand. + //! For block transfers, this variable is generally the address in + //! shared memory used to pass data between processors. + uint32_t uldataw2; + +} tIpcMessage; + +// +//! A structure that defines an IPC control instance. These +//! fields are used by the IPC drivers, and normally it is not necessary for +//! user software to directly read or write fields in the table. +// +typedef struct +{ + //! The address of the PutBuffer IPC message (in MSGRAM) + tIpcMessage *psPutBuffer; + + //! The IPC INT flag to set when sending messages + //! for this IPC controller instance. + uint32_t ulPutFlag; + + //! The address of the PutBuffer Write index (in MSGRAM) + uint16_t *pusPutWriteIndex; + + //! The address of the PutBuffer Read index (in MSGRAM) + uint16_t *pusPutReadIndex; + + //! The address of the GetBuffer IPC message(in MSGRAM) + tIpcMessage *psGetBuffer; + + //! The address of the GetBuffer Write Index (in MSGRAM) + uint16_t *pusGetWriteIndex; + + //! The address of the GetBuffer Read Index (in MSGRAM) + uint16_t *pusGetReadIndex; + +} tIpcController; + +// +// A type definition for the IPC function call command. +// +typedef uint32_t (*tfIpcFuncCall)(uint32_t ulParam); + +// +// Prototypes for Circular Buffers +// +extern tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; +extern tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; + +// +// Function Prototypes +// +extern void IPCInitialize (volatile tIpcController *psController, + uint16_t usCPU2IpcInterrupt, + uint16_t usCPU1IpcInterrupt); +extern uint16_t IpcPut (volatile tIpcController *psController, + tIpcMessage *psMessage, + uint16_t bBlock); +extern uint16_t IpcGet (volatile tIpcController *psController, + tIpcMessage *psMessage, + uint16_t bBlock); +extern uint16_t IPCLtoRDataRead (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRDataRead_Protected (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRSetBits(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength,uint16_t bBlock); +extern uint16_t IPCLtoRSetBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock); +extern uint16_t IPCLtoRClearBits(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength,uint16_t bBlock); +extern uint16_t IPCLtoRClearBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock); +extern uint16_t IPCLtoRDataWrite(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRDataWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRBlockRead(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRBlockWrite(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t usWordLength, + uint16_t bBlock); +extern uint16_t IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, + uint32_t ulShareAddress, + uint16_t usLength, + uint16_t usWordLength, + uint16_t bBlock); +extern uint16_t IPCLtoRFunctionCall(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulParam, + uint16_t bBlock); +extern uint16_t IPCLtoRSendMessage(volatile tIpcController *psController, + uint32_t ulCommand, uint32_t ulAddress, + uint32_t ulDataW1, uint32_t ulDataW2, + uint16_t bBlock); +#if defined (CPU2) +uint16_t +IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, + uint16_t usMaster, uint16_t bBlock); +#endif + +extern void IPCRtoLDataWrite(tIpcMessage *psMessage); +extern void IPCRtoLDataWrite_Protected(tIpcMessage *psMessage); +extern void IPCRtoLDataRead(volatile tIpcController *psController, + tIpcMessage *psMessage, uint16_t bBlock); +extern void IPCRtoLDataRead_Protected(volatile tIpcController *psController, + tIpcMessage *psMessage,uint16_t bBlock); +extern void IPCRtoLSetBits(tIpcMessage *psMessage); +extern void IPCRtoLSetBits_Protected(tIpcMessage *psMessage); +extern void IPCRtoLClearBits(tIpcMessage *psMessage); +extern void IPCRtoLClearBits_Protected(tIpcMessage *psMessage); +extern void IPCRtoLBlockRead(tIpcMessage *psMessage); +extern void IPCRtoLBlockWrite(tIpcMessage *psMessage); +extern void IPCRtoLBlockWrite_Protected(tIpcMessage *psMessage); +extern void IPCRtoLFunctionCall(tIpcMessage *psMessage); + +// +// IPC Lite Driver Prototype Definitions +// +extern uint16_t IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, + uint16_t usLength, uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulMask, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulMask, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulData, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulParam, uint32_t ulStatusFlag); +extern uint16_t IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, + uint16_t ulMaster, uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, + uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, + uint32_t ulStatusFlag); +extern void IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag); + +// +// IPC Utility Driver Prototype Definitions +// +extern void IPCRtoLFlagAcknowledge (uint32_t ulFlags); +extern Uint16 IPCRtoLFlagBusy (uint32_t ulFlags); +extern Uint16 IPCLtoRFlagBusy (uint32_t ulFlags); +extern void IPCLtoRFlagSet (uint32_t ulFlags); +extern void IPCLtoRFlagClear (uint32_t ulFlags); +extern uint32_t IPCGetBootStatus (void); +extern uint16_t IPCBootCPU2(uint32_t ulBootMode); +#ifdef __cplusplus +} +#endif /* extern "C" */ + +// +// Close the Doxygen group. +//! @} +// + +#endif // end of F2837xD_IPC_DRIVERS_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h new file mode 100644 index 0000000000..1905d88ca8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h @@ -0,0 +1,74 @@ +//########################################################################### +// +// FILE: F2837xD_Pie_defines.h +// +// TITLE: #defines used in PIE examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_PIE_DEFINES_H +#define F2837xD_PIE_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_PIE_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h new file mode 100644 index 0000000000..6fd2700965 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h @@ -0,0 +1,20681 @@ +//########################################################################### +// +// FILE: F2837xD_SWPrioritizedIsrLevels.h +// +// TITLE: F28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SW_PRIORITZIED_ISR_H +#define F2837xD_SW_PRIORITZIED_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Interrupt Enable Register Allocation For F2837xD Devices: +// +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +// +// +// Set "Global" Interrupt Priority Level (IER register): +// +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 1 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 5 // Group7 Interrupts (PIEIER6) +#define INT8PL 5 // Group8 Interrupts (PIEIER6) +#define INT9PL 3 // Group9 Interrupts (PIEIER9) +#define INT10PL 6 // Group10 Interrupts (PIEIER6) +#define INT11PL 6 // Group11 Interrupts (PIEIER6) +#define INT12PL 8 // Group12 Interrupts (PIEIER6) +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +// +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +// +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG1_1 to MG1_16 +// MG2_1 to MG2_16 +// MG3_1 to MG3_16 +// MG4_1 to MG4_16 +// MG5_1 to MG5_16 +// MG6_1 to MG6_16 +// MG7_1 to MG7_16 +// MG8_1 to MG8_16 +// MG9_1 to MG9_16 +// MG10_1 to MG10_16 +// MG11_1 to MG11_16 +// MG12_1 to MG12_16 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define G1_1PL 5 // ADCA1_INT +#define G1_2PL 3 // ADCB1_INT +#define G1_3PL 1 // ADCC1_INT +#define G1_4PL 4 // XINT1_INT +#define G1_5PL 4 // XINT2_INT +#define G1_6PL 1 // ADCD1_INT +#define G1_7PL 12 // TIMER0_INT +#define G1_8PL 5 // WAKE_INT +#define G1_9PL 0 // Reserved +#define G1_10PL 0 // Reserved +#define G1_11PL 0 // Reserved +#define G1_12PL 0 // Reserved +#define G1_13PL 8 // IPC1_INT +#define G1_14PL 13 // IPC2_INT +#define G1_15PL 15 // IPC3_INT +#define G1_16PL 9 // IPC4_INT + +#define G2_1PL 13 // EPWM1_TZ_INT +#define G2_2PL 1 // EPWM2_TZ_INT +#define G2_3PL 1 // EPWM3_TZ_INT +#define G2_4PL 9 // EPWM4_TZ_INT +#define G2_5PL 3 // EPWM5_TZ_INT +#define G2_6PL 13 // EPWM6_TZ_INT +#define G2_7PL 9 // EPWM7_TZ_INT +#define G2_8PL 13 // EPWM8_TZ_INT +#define G2_9PL 15 // EPWM9_TZ_INT +#define G2_10PL 11 // EPWM10_TZ_INT +#define G2_11PL 7 // EPWM11_TZ_INT +#define G2_12PL 10 // EPWM12_TZ_INT +#define G2_13PL 0 // Reserved +#define G2_14PL 0 // Reserved +#define G2_15PL 0 // Reserved +#define G2_16PL 0 // Reserved + +#define G3_1PL 5 // EPWM1_INT +#define G3_2PL 9 // EPWM2_INT +#define G3_3PL 5 // EPWM3_INT +#define G3_4PL 2 // EPWM4_INT +#define G3_5PL 12 // EPWM5_INT +#define G3_6PL 4 // EPWM6_INT +#define G3_7PL 2 // EPWM7_INT +#define G3_8PL 13 // EPWM8_INT +#define G3_9PL 4 // EPWM9_INT +#define G3_10PL 12 // EPWM10_INT +#define G3_11PL 4 // EPWM11_INT +#define G3_12PL 14 // EPWM12_INT +#define G3_13PL 0 // Reserved +#define G3_14PL 0 // Reserved +#define G3_15PL 0 // Reserved +#define G3_16PL 0 // Reserved + +#define G4_1PL 3 // ECAP1_INT +#define G4_2PL 3 // ECAP2_INT +#define G4_3PL 3 // ECAP3_INT +#define G4_4PL 6 // ECAP4_INT +#define G4_5PL 7 // ECAP5_INT +#define G4_6PL 7 // ECAP6_INT +#define G4_7PL 0 // Reserved +#define G4_8PL 0 // Reserved +#define G4_9PL 0 // Reserved +#define G4_10PL 0 // Reserved +#define G4_11PL 0 // Reserved +#define G4_12PL 0 // Reserved +#define G4_13PL 0 // Reserved +#define G4_14PL 0 // Reserved +#define G4_15PL 0 // Reserved +#define G4_16PL 0 // Reserved + +#define G5_1PL 6 // EQEP1_INT +#define G5_2PL 5 // EQEP2_INT +#define G5_3PL 5 // EQEP3_INT +#define G5_4PL 1 // Reserved +#define G5_5PL 9 // CLB1_INT +#define G5_6PL 10 // CLB2_INT +#define G5_7PL 15 // CLB3_INT +#define G5_8PL 13 // CLB4_INT +#define G5_9PL 12 // SD1_INT +#define G5_10PL 9 // SD2_INT +#define G5_11PL 0 // Reserved +#define G5_12PL 0 // Reserved +#define G5_13PL 0 // Reserved +#define G5_14PL 0 // Reserved +#define G5_15PL 0 // Reserved +#define G5_16PL 0 // Reserved + +#define G6_1PL 1 // SPIA_RX_INT +#define G6_2PL 7 // SPIA_TX_INT +#define G6_3PL 3 // SPIB_RX_INT +#define G6_4PL 3 // SPIB_TX_INT +#define G6_5PL 10 // MCBSPA_RX_INT +#define G6_6PL 7 // MCBSPA_TX_INT +#define G6_7PL 6 // MCBSPB_RX_INT +#define G6_8PL 13 // MCBSPB_TX_INT +#define G6_9PL 14 // SPIC_RX_INT +#define G6_10PL 3 // SPIC_TX_INT +#define G6_11PL 0 // Reserved +#define G6_12PL 0 // Reserved +#define G6_13PL 0 // Reserved +#define G6_14PL 0 // Reserved +#define G6_15PL 0 // Reserved +#define G6_16PL 0 // Reserved + +#define G7_1PL 1 // DMA_CH1_INT +#define G7_2PL 11 // DMA_CH2_INT +#define G7_3PL 14 // DMA_CH3_INT +#define G7_4PL 3 // DMA_CH4_INT +#define G7_5PL 13 // DMA_CH5_INT +#define G7_6PL 14 // DMA_CH6_INT +#define G7_7PL 0 // Reserved +#define G7_8PL 0 // Reserved +#define G7_9PL 0 // Reserved +#define G7_10PL 0 // Reserved +#define G7_11PL 0 // Reserved +#define G7_12PL 0 // Reserved +#define G7_13PL 0 // Reserved +#define G7_14PL 0 // Reserved +#define G7_15PL 0 // Reserved +#define G7_16PL 0 // Reserved + +#define G8_1PL 14 // I2CA_INT +#define G8_2PL 10 // I2CA_FIFO_INT +#define G8_3PL 11 // I2CB_INT +#define G8_4PL 9 // I2CB_FIFO_INT +#define G8_5PL 12 // SCIC_RX_INT +#define G8_6PL 2 // SCIC_TX_INT +#define G8_7PL 8 // SCID_RX_INT +#define G8_8PL 7 // SCID_TX_INT +#define G8_9PL 0 // Reserved +#define G8_10PL 0 // Reserved +#define G8_11PL 0 // Reserved +#define G8_12PL 0 // Reserved +#define G8_13PL 0 // Reserved +#define G8_14PL 0 // Reserved +#define G8_15PL 1 // UPPA_INT +#define G8_16PL 0 // Reserved + +#define G9_1PL 12 // SCIA_RX_INT +#define G9_2PL 14 // SCIA_TX_INT +#define G9_3PL 11 // SCIB_RX_INT +#define G9_4PL 6 // SCIB_TX_INT +#define G9_5PL 14 // CANA0_INT +#define G9_6PL 10 // CANA1_INT +#define G9_7PL 10 // CANB0_INT +#define G9_8PL 5 // CANB1_INT +#define G9_9PL 0 // Reserved +#define G9_10PL 0 // Reserved +#define G9_11PL 0 // Reserved +#define G9_12PL 0 // Reserved +#define G9_13PL 0 // Reserved +#define G9_14PL 0 // Reserved +#define G9_15PL 12 // USBA_INT +#define G9_16PL 0 // Reserved + +#define G10_1PL 14 // ADCA_EVT_INT +#define G10_2PL 3 // ADCA2_INT +#define G10_3PL 1 // ADCA3_INT +#define G10_4PL 12 // ADCA4_INT +#define G10_5PL 5 // ADCB_EVT_INT +#define G10_6PL 11 // ADCB2_INT +#define G10_7PL 12 // ADCB3_INT +#define G10_8PL 13 // ADCB4_INT +#define G10_9PL 7 // ADCC_EVT_INT +#define G10_10PL 8 // ADCC2_INT +#define G10_11PL 4 // ADCC3_INT +#define G10_12PL 9 // ADCC4_INT +#define G10_13PL 2 // ADCD_EVT_INT +#define G10_14PL 10 // ADCD2_INT +#define G10_15PL 11 // ADCD3_INT +#define G10_16PL 5 // ADCD4_INT + +#define G11_1PL 9 // CLA1_1_INT +#define G11_2PL 6 // CLA1_2_INT +#define G11_3PL 9 // CLA1_3_INT +#define G11_4PL 9 // CLA1_4_INT +#define G11_5PL 6 // CLA1_5_INT +#define G11_6PL 13 // CLA1_6_INT +#define G11_7PL 10 // CLA1_7_INT +#define G11_8PL 15 // CLA1_8_INT +#define G11_9PL 0 // Reserved +#define G11_10PL 0 // Reserved +#define G11_11PL 0 // Reserved +#define G11_12PL 0 // Reserved +#define G11_13PL 0 // Reserved +#define G11_14PL 0 // Reserved +#define G11_15PL 0 // Reserved +#define G11_16PL 0 // Reserved + +#define G12_1PL 3 // XINT3_INT +#define G12_2PL 6 // XINT4_INT +#define G12_3PL 10 // XINT5_INT +#define G12_4PL 5 // Reserved +#define G12_5PL 2 // FMC_INT +#define G12_6PL 11 // VCU_INT +#define G12_7PL 14 // FPU_OVERFLOW_ISR +#define G12_8PL 14 // FPU_UNDERFLOW_ISR +#define G12_9PL 6 // EMIF_ERROR_ISR +#define G12_10PL 5 // RAM_CORRECTABLE_ERROR_ISR +#define G12_11PL 4 // FLASH_CORRECTABLE_ERROR_ISR +#define G12_12PL 12 // RAM_ACCESS_VIOLATION_INT +#define G12_13PL 8 // SYS_PLL_SLIP_INT +#define G12_14PL 2 // AUX_PLL_SLIP_INT +#define G12_15PL 12 // CLA_UNDERFLOW_INT +#define G12_16PL 2 // CLA_OVERFLOW_INT + +// +// There should be no need to modify code below this line +// +// Automatically generate IER interrupt masks MINT1 to MINT16: +// +// Beginning of MINT1: +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) +// End Of MINT1. + +// Beginning of MINT2: +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) +// End Of MINT2. + +// Beginning of MINT3: +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) +// End Of MINT3. + +// Beginning of MINT4: +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) +// End Of MINT4. + +// Beginning of MINT5: +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) +// End Of MINT5. + +// Beginning of MINT6: +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) +// End Of MINT6. + +// Beginning of MINT7: +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) +// End Of MINT7. + +// Beginning of MINT8: +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) +// End Of MINT8. + +// Beginning of MINT9: +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) +// End Of MINT9. + +// Beginning of MINT10: +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) +// End Of MINT10. + +// Beginning of MINT11: +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) +// End Of MINT11. + +// Beginning of MINT12: +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) +// End Of MINT12. + +// Beginning of MINT13: +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#if (INT12PL >= INT13PL) || (INT12PL == 0) +#define MINT13_12PL ~(1 << 11) +#else +#define MINT13_12PL 0xFFFF +#endif + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) +// End Of MINT13. + +// Beginning of MINT14: +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) +// End Of MINT14. + +// Beginning of MINT15: +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) +// End Of MINT15. + +// Beginning of MINT16: +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) +// End Of MINT16. + +// +// Automatically generate PIEIER1 interrupt masks MG11 to MG116: +// + +// Beginning of MG11: +#if (G1_2PL >= G1_1PL) || (G1_2PL == 0) +#define MG1_1_12PL ~(1 << 1) +#else +#define MG1_1_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_1PL) || (G1_3PL == 0) +#define MG1_1_13PL ~(1 << 2) +#else +#define MG1_1_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_1PL) || (G1_4PL == 0) +#define MG1_1_14PL ~(1 << 3) +#else +#define MG1_1_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_1PL) || (G1_5PL == 0) +#define MG1_1_15PL ~(1 << 4) +#else +#define MG1_1_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_1PL) || (G1_6PL == 0) +#define MG1_1_16PL ~(1 << 5) +#else +#define MG1_1_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_1PL) || (G1_7PL == 0) +#define MG1_1_17PL ~(1 << 6) +#else +#define MG1_1_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_1PL) || (G1_8PL == 0) +#define MG1_1_18PL ~(1 << 7) +#else +#define MG1_1_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_1PL) || (G1_9PL == 0) +#define MG1_1_19PL ~(1 << 8) +#else +#define MG1_1_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_1PL) || (G1_10PL == 0) +#define MG1_1_110PL ~(1 << 9) +#else +#define MG1_1_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_1PL) || (G1_11PL == 0) +#define MG1_1_111PL ~(1 << 10) +#else +#define MG1_1_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_1PL) || (G1_12PL == 0) +#define MG1_1_112PL ~(1 << 11) +#else +#define MG1_1_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_1PL) || (G1_13PL == 0) +#define MG1_1_113PL ~(1 << 12) +#else +#define MG1_1_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_1PL) || (G1_14PL == 0) +#define MG1_1_114PL ~(1 << 13) +#else +#define MG1_1_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_1PL) || (G1_15PL == 0) +#define MG1_1_115PL ~(1 << 14) +#else +#define MG1_1_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_1PL) || (G1_16PL == 0) +#define MG1_1_116PL ~(1 << 15) +#else +#define MG1_1_116PL 0xFFFF +#endif + +#define MG1_1_11PL 0xFFFE +#define MG1_1 (MG1_1_11PL & MG1_1_12PL & MG1_1_13PL & MG1_1_14PL & \ + MG1_1_15PL & MG1_1_16PL & MG1_1_17PL & MG1_1_18PL & \ + MG1_1_19PL & MG1_1_110PL & MG1_1_111PL & MG1_1_112PL & \ + MG1_1_113PL & MG1_1_114PL & MG1_1_115PL & MG1_1_116PL) +// End of MG1_1: +// Beginning of MG12: +#if (G1_1PL >= G1_2PL) || (G1_1PL == 0) +#define MG1_2_11PL ~(1 << 0) +#else +#define MG1_2_11PL 0xFFFF +#endif + +#if (G1_3PL >= G1_2PL) || (G1_3PL == 0) +#define MG1_2_13PL ~(1 << 2) +#else +#define MG1_2_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_2PL) || (G1_4PL == 0) +#define MG1_2_14PL ~(1 << 3) +#else +#define MG1_2_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_2PL) || (G1_5PL == 0) +#define MG1_2_15PL ~(1 << 4) +#else +#define MG1_2_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_2PL) || (G1_6PL == 0) +#define MG1_2_16PL ~(1 << 5) +#else +#define MG1_2_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_2PL) || (G1_7PL == 0) +#define MG1_2_17PL ~(1 << 6) +#else +#define MG1_2_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_2PL) || (G1_8PL == 0) +#define MG1_2_18PL ~(1 << 7) +#else +#define MG1_2_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_2PL) || (G1_9PL == 0) +#define MG1_2_19PL ~(1 << 8) +#else +#define MG1_2_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_2PL) || (G1_10PL == 0) +#define MG1_2_110PL ~(1 << 9) +#else +#define MG1_2_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_2PL) || (G1_11PL == 0) +#define MG1_2_111PL ~(1 << 10) +#else +#define MG1_2_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_2PL) || (G1_12PL == 0) +#define MG1_2_112PL ~(1 << 11) +#else +#define MG1_2_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_2PL) || (G1_13PL == 0) +#define MG1_2_113PL ~(1 << 12) +#else +#define MG1_2_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_2PL) || (G1_14PL == 0) +#define MG1_2_114PL ~(1 << 13) +#else +#define MG1_2_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_2PL) || (G1_15PL == 0) +#define MG1_2_115PL ~(1 << 14) +#else +#define MG1_2_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_2PL) || (G1_16PL == 0) +#define MG1_2_116PL ~(1 << 15) +#else +#define MG1_2_116PL 0xFFFF +#endif + +#define MG1_2_12PL 0xFFFD +#define MG1_2 (MG1_2_11PL & MG1_2_12PL & MG1_2_13PL & MG1_2_14PL & \ + MG1_2_15PL & MG1_2_16PL & MG1_2_17PL & MG1_2_18PL & \ + MG1_2_19PL & MG1_2_110PL & MG1_2_111PL & MG1_2_112PL & \ + MG1_2_113PL & MG1_2_114PL & MG1_2_115PL & MG1_2_116PL) +// End of MG1_2: +// Beginning of MG13: +#if (G1_1PL >= G1_3PL) || (G1_1PL == 0) +#define MG1_3_11PL ~(1 << 0) +#else +#define MG1_3_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_3PL) || (G1_2PL == 0) +#define MG1_3_12PL ~(1 << 1) +#else +#define MG1_3_12PL 0xFFFF +#endif + +#if (G1_4PL >= G1_3PL) || (G1_4PL == 0) +#define MG1_3_14PL ~(1 << 3) +#else +#define MG1_3_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_3PL) || (G1_5PL == 0) +#define MG1_3_15PL ~(1 << 4) +#else +#define MG1_3_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_3PL) || (G1_6PL == 0) +#define MG1_3_16PL ~(1 << 5) +#else +#define MG1_3_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_3PL) || (G1_7PL == 0) +#define MG1_3_17PL ~(1 << 6) +#else +#define MG1_3_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_3PL) || (G1_8PL == 0) +#define MG1_3_18PL ~(1 << 7) +#else +#define MG1_3_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_3PL) || (G1_9PL == 0) +#define MG1_3_19PL ~(1 << 8) +#else +#define MG1_3_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_3PL) || (G1_10PL == 0) +#define MG1_3_110PL ~(1 << 9) +#else +#define MG1_3_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_3PL) || (G1_11PL == 0) +#define MG1_3_111PL ~(1 << 10) +#else +#define MG1_3_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_3PL) || (G1_12PL == 0) +#define MG1_3_112PL ~(1 << 11) +#else +#define MG1_3_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_3PL) || (G1_13PL == 0) +#define MG1_3_113PL ~(1 << 12) +#else +#define MG1_3_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_3PL) || (G1_14PL == 0) +#define MG1_3_114PL ~(1 << 13) +#else +#define MG1_3_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_3PL) || (G1_15PL == 0) +#define MG1_3_115PL ~(1 << 14) +#else +#define MG1_3_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_3PL) || (G1_16PL == 0) +#define MG1_3_116PL ~(1 << 15) +#else +#define MG1_3_116PL 0xFFFF +#endif + +#define MG1_3_13PL 0xFFFB +#define MG1_3 (MG1_3_11PL & MG1_3_12PL & MG1_3_13PL & MG1_3_14PL & \ + MG1_3_15PL & MG1_3_16PL & MG1_3_17PL & MG1_3_18PL & \ + MG1_3_19PL & MG1_3_110PL & MG1_3_111PL & MG1_3_112PL & \ + MG1_3_113PL & MG1_3_114PL & MG1_3_115PL & MG1_3_116PL) +// End of MG1_3: +// Beginning of MG14: +#if (G1_1PL >= G1_4PL) || (G1_1PL == 0) +#define MG1_4_11PL ~(1 << 0) +#else +#define MG1_4_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_4PL) || (G1_2PL == 0) +#define MG1_4_12PL ~(1 << 1) +#else +#define MG1_4_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_4PL) || (G1_3PL == 0) +#define MG1_4_13PL ~(1 << 2) +#else +#define MG1_4_13PL 0xFFFF +#endif + +#if (G1_5PL >= G1_4PL) || (G1_5PL == 0) +#define MG1_4_15PL ~(1 << 4) +#else +#define MG1_4_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_4PL) || (G1_6PL == 0) +#define MG1_4_16PL ~(1 << 5) +#else +#define MG1_4_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_4PL) || (G1_7PL == 0) +#define MG1_4_17PL ~(1 << 6) +#else +#define MG1_4_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_4PL) || (G1_8PL == 0) +#define MG1_4_18PL ~(1 << 7) +#else +#define MG1_4_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_4PL) || (G1_9PL == 0) +#define MG1_4_19PL ~(1 << 8) +#else +#define MG1_4_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_4PL) || (G1_10PL == 0) +#define MG1_4_110PL ~(1 << 9) +#else +#define MG1_4_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_4PL) || (G1_11PL == 0) +#define MG1_4_111PL ~(1 << 10) +#else +#define MG1_4_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_4PL) || (G1_12PL == 0) +#define MG1_4_112PL ~(1 << 11) +#else +#define MG1_4_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_4PL) || (G1_13PL == 0) +#define MG1_4_113PL ~(1 << 12) +#else +#define MG1_4_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_4PL) || (G1_14PL == 0) +#define MG1_4_114PL ~(1 << 13) +#else +#define MG1_4_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_4PL) || (G1_15PL == 0) +#define MG1_4_115PL ~(1 << 14) +#else +#define MG1_4_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_4PL) || (G1_16PL == 0) +#define MG1_4_116PL ~(1 << 15) +#else +#define MG1_4_116PL 0xFFFF +#endif + +#define MG1_4_14PL 0xFFF7 +#define MG1_4 (MG1_4_11PL & MG1_4_12PL & MG1_4_13PL & MG1_4_14PL & \ + MG1_4_15PL & MG1_4_16PL & MG1_4_17PL & MG1_4_18PL & \ + MG1_4_19PL & MG1_4_110PL & MG1_4_111PL & MG1_4_112PL & \ + MG1_4_113PL & MG1_4_114PL & MG1_4_115PL & MG1_4_116PL) +// End of MG1_4: +// Beginning of MG15: +#if (G1_1PL >= G1_5PL) || (G1_1PL == 0) +#define MG1_5_11PL ~(1 << 0) +#else +#define MG1_5_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_5PL) || (G1_2PL == 0) +#define MG1_5_12PL ~(1 << 1) +#else +#define MG1_5_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_5PL) || (G1_3PL == 0) +#define MG1_5_13PL ~(1 << 2) +#else +#define MG1_5_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_5PL) || (G1_4PL == 0) +#define MG1_5_14PL ~(1 << 3) +#else +#define MG1_5_14PL 0xFFFF +#endif + +#if (G1_6PL >= G1_5PL) || (G1_6PL == 0) +#define MG1_5_16PL ~(1 << 5) +#else +#define MG1_5_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_5PL) || (G1_7PL == 0) +#define MG1_5_17PL ~(1 << 6) +#else +#define MG1_5_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_5PL) || (G1_8PL == 0) +#define MG1_5_18PL ~(1 << 7) +#else +#define MG1_5_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_5PL) || (G1_9PL == 0) +#define MG1_5_19PL ~(1 << 8) +#else +#define MG1_5_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_5PL) || (G1_10PL == 0) +#define MG1_5_110PL ~(1 << 9) +#else +#define MG1_5_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_5PL) || (G1_11PL == 0) +#define MG1_5_111PL ~(1 << 10) +#else +#define MG1_5_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_5PL) || (G1_12PL == 0) +#define MG1_5_112PL ~(1 << 11) +#else +#define MG1_5_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_5PL) || (G1_13PL == 0) +#define MG1_5_113PL ~(1 << 12) +#else +#define MG1_5_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_5PL) || (G1_14PL == 0) +#define MG1_5_114PL ~(1 << 13) +#else +#define MG1_5_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_5PL) || (G1_15PL == 0) +#define MG1_5_115PL ~(1 << 14) +#else +#define MG1_5_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_5PL) || (G1_16PL == 0) +#define MG1_5_116PL ~(1 << 15) +#else +#define MG1_5_116PL 0xFFFF +#endif + +#define MG1_5_15PL 0xFFEF +#define MG1_5 (MG1_5_11PL & MG1_5_12PL & MG1_5_13PL & MG1_5_14PL & \ + MG1_5_15PL & MG1_5_16PL & MG1_5_17PL & MG1_5_18PL & \ + MG1_5_19PL & MG1_5_110PL & MG1_5_111PL & MG1_5_112PL & \ + MG1_5_113PL & MG1_5_114PL & MG1_5_115PL & MG1_5_116PL) +// End of MG1_5: +// Beginning of MG16: +#if (G1_1PL >= G1_6PL) || (G1_1PL == 0) +#define MG1_6_11PL ~(1 << 0) +#else +#define MG1_6_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_6PL) || (G1_2PL == 0) +#define MG1_6_12PL ~(1 << 1) +#else +#define MG1_6_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_6PL) || (G1_3PL == 0) +#define MG1_6_13PL ~(1 << 2) +#else +#define MG1_6_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_6PL) || (G1_4PL == 0) +#define MG1_6_14PL ~(1 << 3) +#else +#define MG1_6_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_6PL) || (G1_5PL == 0) +#define MG1_6_15PL ~(1 << 4) +#else +#define MG1_6_15PL 0xFFFF +#endif + +#if (G1_7PL >= G1_6PL) || (G1_7PL == 0) +#define MG1_6_17PL ~(1 << 6) +#else +#define MG1_6_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_6PL) || (G1_8PL == 0) +#define MG1_6_18PL ~(1 << 7) +#else +#define MG1_6_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_6PL) || (G1_9PL == 0) +#define MG1_6_19PL ~(1 << 8) +#else +#define MG1_6_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_6PL) || (G1_10PL == 0) +#define MG1_6_110PL ~(1 << 9) +#else +#define MG1_6_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_6PL) || (G1_11PL == 0) +#define MG1_6_111PL ~(1 << 10) +#else +#define MG1_6_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_6PL) || (G1_12PL == 0) +#define MG1_6_112PL ~(1 << 11) +#else +#define MG1_6_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_6PL) || (G1_13PL == 0) +#define MG1_6_113PL ~(1 << 12) +#else +#define MG1_6_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_6PL) || (G1_14PL == 0) +#define MG1_6_114PL ~(1 << 13) +#else +#define MG1_6_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_6PL) || (G1_15PL == 0) +#define MG1_6_115PL ~(1 << 14) +#else +#define MG1_6_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_6PL) || (G1_16PL == 0) +#define MG1_6_116PL ~(1 << 15) +#else +#define MG1_6_116PL 0xFFFF +#endif + +#define MG1_6_16PL 0xFFDF +#define MG1_6 (MG1_6_11PL & MG1_6_12PL & MG1_6_13PL & MG1_6_14PL & \ + MG1_6_15PL & MG1_6_16PL & MG1_6_17PL & MG1_6_18PL & \ + MG1_6_19PL & MG1_6_110PL & MG1_6_111PL & MG1_6_112PL & \ + MG1_6_113PL & MG1_6_114PL & MG1_6_115PL & MG1_6_116PL) +// End of MG1_6: +// Beginning of MG17: +#if (G1_1PL >= G1_7PL) || (G1_1PL == 0) +#define MG1_7_11PL ~(1 << 0) +#else +#define MG1_7_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_7PL) || (G1_2PL == 0) +#define MG1_7_12PL ~(1 << 1) +#else +#define MG1_7_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_7PL) || (G1_3PL == 0) +#define MG1_7_13PL ~(1 << 2) +#else +#define MG1_7_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_7PL) || (G1_4PL == 0) +#define MG1_7_14PL ~(1 << 3) +#else +#define MG1_7_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_7PL) || (G1_5PL == 0) +#define MG1_7_15PL ~(1 << 4) +#else +#define MG1_7_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_7PL) || (G1_6PL == 0) +#define MG1_7_16PL ~(1 << 5) +#else +#define MG1_7_16PL 0xFFFF +#endif + +#if (G1_8PL >= G1_7PL) || (G1_8PL == 0) +#define MG1_7_18PL ~(1 << 7) +#else +#define MG1_7_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_7PL) || (G1_9PL == 0) +#define MG1_7_19PL ~(1 << 8) +#else +#define MG1_7_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_7PL) || (G1_10PL == 0) +#define MG1_7_110PL ~(1 << 9) +#else +#define MG1_7_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_7PL) || (G1_11PL == 0) +#define MG1_7_111PL ~(1 << 10) +#else +#define MG1_7_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_7PL) || (G1_12PL == 0) +#define MG1_7_112PL ~(1 << 11) +#else +#define MG1_7_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_7PL) || (G1_13PL == 0) +#define MG1_7_113PL ~(1 << 12) +#else +#define MG1_7_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_7PL) || (G1_14PL == 0) +#define MG1_7_114PL ~(1 << 13) +#else +#define MG1_7_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_7PL) || (G1_15PL == 0) +#define MG1_7_115PL ~(1 << 14) +#else +#define MG1_7_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_7PL) || (G1_16PL == 0) +#define MG1_7_116PL ~(1 << 15) +#else +#define MG1_7_116PL 0xFFFF +#endif + +#define MG1_7_17PL 0xFFBF +#define MG1_7 (MG1_7_11PL & MG1_7_12PL & MG1_7_13PL & MG1_7_14PL & \ + MG1_7_15PL & MG1_7_16PL & MG1_7_17PL & MG1_7_18PL & \ + MG1_7_19PL & MG1_7_110PL & MG1_7_111PL & MG1_7_112PL & \ + MG1_7_113PL & MG1_7_114PL & MG1_7_115PL & MG1_7_116PL) +// End of MG1_7: +// Beginning of MG18: +#if (G1_1PL >= G1_8PL) || (G1_1PL == 0) +#define MG1_8_11PL ~(1 << 0) +#else +#define MG1_8_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_8PL) || (G1_2PL == 0) +#define MG1_8_12PL ~(1 << 1) +#else +#define MG1_8_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_8PL) || (G1_3PL == 0) +#define MG1_8_13PL ~(1 << 2) +#else +#define MG1_8_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_8PL) || (G1_4PL == 0) +#define MG1_8_14PL ~(1 << 3) +#else +#define MG1_8_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_8PL) || (G1_5PL == 0) +#define MG1_8_15PL ~(1 << 4) +#else +#define MG1_8_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_8PL) || (G1_6PL == 0) +#define MG1_8_16PL ~(1 << 5) +#else +#define MG1_8_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_8PL) || (G1_7PL == 0) +#define MG1_8_17PL ~(1 << 6) +#else +#define MG1_8_17PL 0xFFFF +#endif + +#if (G1_9PL >= G1_8PL) || (G1_9PL == 0) +#define MG1_8_19PL ~(1 << 8) +#else +#define MG1_8_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_8PL) || (G1_10PL == 0) +#define MG1_8_110PL ~(1 << 9) +#else +#define MG1_8_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_8PL) || (G1_11PL == 0) +#define MG1_8_111PL ~(1 << 10) +#else +#define MG1_8_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_8PL) || (G1_12PL == 0) +#define MG1_8_112PL ~(1 << 11) +#else +#define MG1_8_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_8PL) || (G1_13PL == 0) +#define MG1_8_113PL ~(1 << 12) +#else +#define MG1_8_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_8PL) || (G1_14PL == 0) +#define MG1_8_114PL ~(1 << 13) +#else +#define MG1_8_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_8PL) || (G1_15PL == 0) +#define MG1_8_115PL ~(1 << 14) +#else +#define MG1_8_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_8PL) || (G1_16PL == 0) +#define MG1_8_116PL ~(1 << 15) +#else +#define MG1_8_116PL 0xFFFF +#endif + +#define MG1_8_18PL 0xFF7F +#define MG1_8 (MG1_8_11PL & MG1_8_12PL & MG1_8_13PL & MG1_8_14PL & \ + MG1_8_15PL & MG1_8_16PL & MG1_8_17PL & MG1_8_18PL & \ + MG1_8_19PL & MG1_8_110PL & MG1_8_111PL & MG1_8_112PL & \ + MG1_8_113PL & MG1_8_114PL & MG1_8_115PL & MG1_8_116PL) +// End of MG1_8: +// Beginning of MG19: +#if (G1_1PL >= G1_9PL) || (G1_1PL == 0) +#define MG1_9_11PL ~(1 << 0) +#else +#define MG1_9_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_9PL) || (G1_2PL == 0) +#define MG1_9_12PL ~(1 << 1) +#else +#define MG1_9_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_9PL) || (G1_3PL == 0) +#define MG1_9_13PL ~(1 << 2) +#else +#define MG1_9_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_9PL) || (G1_4PL == 0) +#define MG1_9_14PL ~(1 << 3) +#else +#define MG1_9_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_9PL) || (G1_5PL == 0) +#define MG1_9_15PL ~(1 << 4) +#else +#define MG1_9_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_9PL) || (G1_6PL == 0) +#define MG1_9_16PL ~(1 << 5) +#else +#define MG1_9_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_9PL) || (G1_7PL == 0) +#define MG1_9_17PL ~(1 << 6) +#else +#define MG1_9_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_9PL) || (G1_8PL == 0) +#define MG1_9_18PL ~(1 << 7) +#else +#define MG1_9_18PL 0xFFFF +#endif + +#if (G1_10PL >= G1_9PL) || (G1_10PL == 0) +#define MG1_9_110PL ~(1 << 9) +#else +#define MG1_9_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_9PL) || (G1_11PL == 0) +#define MG1_9_111PL ~(1 << 10) +#else +#define MG1_9_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_9PL) || (G1_12PL == 0) +#define MG1_9_112PL ~(1 << 11) +#else +#define MG1_9_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_9PL) || (G1_13PL == 0) +#define MG1_9_113PL ~(1 << 12) +#else +#define MG1_9_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_9PL) || (G1_14PL == 0) +#define MG1_9_114PL ~(1 << 13) +#else +#define MG1_9_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_9PL) || (G1_15PL == 0) +#define MG1_9_115PL ~(1 << 14) +#else +#define MG1_9_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_9PL) || (G1_16PL == 0) +#define MG1_9_116PL ~(1 << 15) +#else +#define MG1_9_116PL 0xFFFF +#endif + +#define MG1_9_19PL 0xFEFF +#define MG1_9 (MG1_9_11PL & MG1_9_12PL & MG1_9_13PL & MG1_9_14PL & \ + MG1_9_15PL & MG1_9_16PL & MG1_9_17PL & MG1_9_18PL & \ + MG1_9_19PL & MG1_9_110PL & MG1_9_111PL & MG1_9_112PL & \ + MG1_9_113PL & MG1_9_114PL & MG1_9_115PL & MG1_9_116PL) +// End of MG1_9: +// Beginning of MG110: +#if (G1_1PL >= G1_10PL) || (G1_1PL == 0) +#define MG1_10_11PL ~(1 << 0) +#else +#define MG1_10_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_10PL) || (G1_2PL == 0) +#define MG1_10_12PL ~(1 << 1) +#else +#define MG1_10_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_10PL) || (G1_3PL == 0) +#define MG1_10_13PL ~(1 << 2) +#else +#define MG1_10_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_10PL) || (G1_4PL == 0) +#define MG1_10_14PL ~(1 << 3) +#else +#define MG1_10_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_10PL) || (G1_5PL == 0) +#define MG1_10_15PL ~(1 << 4) +#else +#define MG1_10_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_10PL) || (G1_6PL == 0) +#define MG1_10_16PL ~(1 << 5) +#else +#define MG1_10_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_10PL) || (G1_7PL == 0) +#define MG1_10_17PL ~(1 << 6) +#else +#define MG1_10_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_10PL) || (G1_8PL == 0) +#define MG1_10_18PL ~(1 << 7) +#else +#define MG1_10_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_10PL) || (G1_9PL == 0) +#define MG1_10_19PL ~(1 << 8) +#else +#define MG1_10_19PL 0xFFFF +#endif + +#if (G1_11PL >= G1_10PL) || (G1_11PL == 0) +#define MG1_10_111PL ~(1 << 10) +#else +#define MG1_10_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_10PL) || (G1_12PL == 0) +#define MG1_10_112PL ~(1 << 11) +#else +#define MG1_10_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_10PL) || (G1_13PL == 0) +#define MG1_10_113PL ~(1 << 12) +#else +#define MG1_10_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_10PL) || (G1_14PL == 0) +#define MG1_10_114PL ~(1 << 13) +#else +#define MG1_10_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_10PL) || (G1_15PL == 0) +#define MG1_10_115PL ~(1 << 14) +#else +#define MG1_10_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_10PL) || (G1_16PL == 0) +#define MG1_10_116PL ~(1 << 15) +#else +#define MG1_10_116PL 0xFFFF +#endif + +#define MG1_10_110PL 0xFDFF +#define MG1_10 (MG1_10_11PL & MG1_10_12PL & MG1_10_13PL & MG1_10_14PL & \ + MG1_10_15PL & MG1_10_16PL & MG1_10_17PL & MG1_10_18PL & \ + MG1_10_19PL & MG1_10_110PL & MG1_10_111PL & MG1_10_112PL & \ + MG1_10_113PL & MG1_10_114PL & MG1_10_115PL & MG1_10_116PL) +// End of MG1_10: +// Beginning of MG111: +#if (G1_1PL >= G1_11PL) || (G1_1PL == 0) +#define MG1_11_11PL ~(1 << 0) +#else +#define MG1_11_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_11PL) || (G1_2PL == 0) +#define MG1_11_12PL ~(1 << 1) +#else +#define MG1_11_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_11PL) || (G1_3PL == 0) +#define MG1_11_13PL ~(1 << 2) +#else +#define MG1_11_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_11PL) || (G1_4PL == 0) +#define MG1_11_14PL ~(1 << 3) +#else +#define MG1_11_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_11PL) || (G1_5PL == 0) +#define MG1_11_15PL ~(1 << 4) +#else +#define MG1_11_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_11PL) || (G1_6PL == 0) +#define MG1_11_16PL ~(1 << 5) +#else +#define MG1_11_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_11PL) || (G1_7PL == 0) +#define MG1_11_17PL ~(1 << 6) +#else +#define MG1_11_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_11PL) || (G1_8PL == 0) +#define MG1_11_18PL ~(1 << 7) +#else +#define MG1_11_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_11PL) || (G1_9PL == 0) +#define MG1_11_19PL ~(1 << 8) +#else +#define MG1_11_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_11PL) || (G1_10PL == 0) +#define MG1_11_110PL ~(1 << 9) +#else +#define MG1_11_110PL 0xFFFF +#endif + +#if (G1_12PL >= G1_11PL) || (G1_12PL == 0) +#define MG1_11_112PL ~(1 << 11) +#else +#define MG1_11_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_11PL) || (G1_13PL == 0) +#define MG1_11_113PL ~(1 << 12) +#else +#define MG1_11_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_11PL) || (G1_14PL == 0) +#define MG1_11_114PL ~(1 << 13) +#else +#define MG1_11_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_11PL) || (G1_15PL == 0) +#define MG1_11_115PL ~(1 << 14) +#else +#define MG1_11_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_11PL) || (G1_16PL == 0) +#define MG1_11_116PL ~(1 << 15) +#else +#define MG1_11_116PL 0xFFFF +#endif + +#define MG1_11_111PL 0xFBFF +#define MG1_11 (MG1_11_11PL & MG1_11_12PL & MG1_11_13PL & MG1_11_14PL & \ + MG1_11_15PL & MG1_11_16PL & MG1_11_17PL & MG1_11_18PL & \ + MG1_11_19PL & MG1_11_110PL & MG1_11_111PL & MG1_11_112PL & \ + MG1_11_113PL & MG1_11_114PL & MG1_11_115PL & MG1_11_116PL) +// End of MG1_11: +// Beginning of MG112: +#if (G1_1PL >= G1_12PL) || (G1_1PL == 0) +#define MG1_12_11PL ~(1 << 0) +#else +#define MG1_12_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_12PL) || (G1_2PL == 0) +#define MG1_12_12PL ~(1 << 1) +#else +#define MG1_12_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_12PL) || (G1_3PL == 0) +#define MG1_12_13PL ~(1 << 2) +#else +#define MG1_12_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_12PL) || (G1_4PL == 0) +#define MG1_12_14PL ~(1 << 3) +#else +#define MG1_12_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_12PL) || (G1_5PL == 0) +#define MG1_12_15PL ~(1 << 4) +#else +#define MG1_12_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_12PL) || (G1_6PL == 0) +#define MG1_12_16PL ~(1 << 5) +#else +#define MG1_12_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_12PL) || (G1_7PL == 0) +#define MG1_12_17PL ~(1 << 6) +#else +#define MG1_12_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_12PL) || (G1_8PL == 0) +#define MG1_12_18PL ~(1 << 7) +#else +#define MG1_12_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_12PL) || (G1_9PL == 0) +#define MG1_12_19PL ~(1 << 8) +#else +#define MG1_12_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_12PL) || (G1_10PL == 0) +#define MG1_12_110PL ~(1 << 9) +#else +#define MG1_12_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_12PL) || (G1_11PL == 0) +#define MG1_12_111PL ~(1 << 10) +#else +#define MG1_12_111PL 0xFFFF +#endif + +#if (G1_13PL >= G1_12PL) || (G1_13PL == 0) +#define MG1_12_113PL ~(1 << 12) +#else +#define MG1_12_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_12PL) || (G1_14PL == 0) +#define MG1_12_114PL ~(1 << 13) +#else +#define MG1_12_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_12PL) || (G1_15PL == 0) +#define MG1_12_115PL ~(1 << 14) +#else +#define MG1_12_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_12PL) || (G1_16PL == 0) +#define MG1_12_116PL ~(1 << 15) +#else +#define MG1_12_116PL 0xFFFF +#endif + +#define MG1_12_112PL 0xF7FF +#define MG1_12 (MG1_12_11PL & MG1_12_12PL & MG1_12_13PL & MG1_12_14PL & \ + MG1_12_15PL & MG1_12_16PL & MG1_12_17PL & MG1_12_18PL & \ + MG1_12_19PL & MG1_12_110PL & MG1_12_111PL & MG1_12_112PL & \ + MG1_12_113PL & MG1_12_114PL & MG1_12_115PL & MG1_12_116PL) +// End of MG1_12: +// Beginning of MG113: +#if (G1_1PL >= G1_13PL) || (G1_1PL == 0) +#define MG1_13_11PL ~(1 << 0) +#else +#define MG1_13_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_13PL) || (G1_2PL == 0) +#define MG1_13_12PL ~(1 << 1) +#else +#define MG1_13_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_13PL) || (G1_3PL == 0) +#define MG1_13_13PL ~(1 << 2) +#else +#define MG1_13_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_13PL) || (G1_4PL == 0) +#define MG1_13_14PL ~(1 << 3) +#else +#define MG1_13_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_13PL) || (G1_5PL == 0) +#define MG1_13_15PL ~(1 << 4) +#else +#define MG1_13_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_13PL) || (G1_6PL == 0) +#define MG1_13_16PL ~(1 << 5) +#else +#define MG1_13_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_13PL) || (G1_7PL == 0) +#define MG1_13_17PL ~(1 << 6) +#else +#define MG1_13_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_13PL) || (G1_8PL == 0) +#define MG1_13_18PL ~(1 << 7) +#else +#define MG1_13_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_13PL) || (G1_9PL == 0) +#define MG1_13_19PL ~(1 << 8) +#else +#define MG1_13_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_13PL) || (G1_10PL == 0) +#define MG1_13_110PL ~(1 << 9) +#else +#define MG1_13_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_13PL) || (G1_11PL == 0) +#define MG1_13_111PL ~(1 << 10) +#else +#define MG1_13_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_13PL) || (G1_12PL == 0) +#define MG1_13_112PL ~(1 << 11) +#else +#define MG1_13_112PL 0xFFFF +#endif + +#if (G1_14PL >= G1_13PL) || (G1_14PL == 0) +#define MG1_13_114PL ~(1 << 13) +#else +#define MG1_13_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_13PL) || (G1_15PL == 0) +#define MG1_13_115PL ~(1 << 14) +#else +#define MG1_13_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_13PL) || (G1_16PL == 0) +#define MG1_13_116PL ~(1 << 15) +#else +#define MG1_13_116PL 0xFFFF +#endif + +#define MG1_13_113PL 0xEFFF +#define MG1_13 (MG1_13_11PL & MG1_13_12PL & MG1_13_13PL & MG1_13_14PL & \ + MG1_13_15PL & MG1_13_16PL & MG1_13_17PL & MG1_13_18PL & \ + MG1_13_19PL & MG1_13_110PL & MG1_13_111PL & MG1_13_112PL & \ + MG1_13_113PL & MG1_13_114PL & MG1_13_115PL & MG1_13_116PL) +// End of MG1_13: +// Beginning of MG114: +#if (G1_1PL >= G1_14PL) || (G1_1PL == 0) +#define MG1_14_11PL ~(1 << 0) +#else +#define MG1_14_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_14PL) || (G1_2PL == 0) +#define MG1_14_12PL ~(1 << 1) +#else +#define MG1_14_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_14PL) || (G1_3PL == 0) +#define MG1_14_13PL ~(1 << 2) +#else +#define MG1_14_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_14PL) || (G1_4PL == 0) +#define MG1_14_14PL ~(1 << 3) +#else +#define MG1_14_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_14PL) || (G1_5PL == 0) +#define MG1_14_15PL ~(1 << 4) +#else +#define MG1_14_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_14PL) || (G1_6PL == 0) +#define MG1_14_16PL ~(1 << 5) +#else +#define MG1_14_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_14PL) || (G1_7PL == 0) +#define MG1_14_17PL ~(1 << 6) +#else +#define MG1_14_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_14PL) || (G1_8PL == 0) +#define MG1_14_18PL ~(1 << 7) +#else +#define MG1_14_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_14PL) || (G1_9PL == 0) +#define MG1_14_19PL ~(1 << 8) +#else +#define MG1_14_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_14PL) || (G1_10PL == 0) +#define MG1_14_110PL ~(1 << 9) +#else +#define MG1_14_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_14PL) || (G1_11PL == 0) +#define MG1_14_111PL ~(1 << 10) +#else +#define MG1_14_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_14PL) || (G1_12PL == 0) +#define MG1_14_112PL ~(1 << 11) +#else +#define MG1_14_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_14PL) || (G1_13PL == 0) +#define MG1_14_113PL ~(1 << 12) +#else +#define MG1_14_113PL 0xFFFF +#endif + +#if (G1_15PL >= G1_14PL) || (G1_15PL == 0) +#define MG1_14_115PL ~(1 << 14) +#else +#define MG1_14_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_14PL) || (G1_16PL == 0) +#define MG1_14_116PL ~(1 << 15) +#else +#define MG1_14_116PL 0xFFFF +#endif + +#define MG1_14_114PL 0xDFFF +#define MG1_14 (MG1_14_11PL & MG1_14_12PL & MG1_14_13PL & MG1_14_14PL & \ + MG1_14_15PL & MG1_14_16PL & MG1_14_17PL & MG1_14_18PL & \ + MG1_14_19PL & MG1_14_110PL & MG1_14_111PL & MG1_14_112PL & \ + MG1_14_113PL & MG1_14_114PL & MG1_14_115PL & MG1_14_116PL) +// End of MG1_14: +// Beginning of MG115: +#if (G1_1PL >= G1_15PL) || (G1_1PL == 0) +#define MG1_15_11PL ~(1 << 0) +#else +#define MG1_15_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_15PL) || (G1_2PL == 0) +#define MG1_15_12PL ~(1 << 1) +#else +#define MG1_15_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_15PL) || (G1_3PL == 0) +#define MG1_15_13PL ~(1 << 2) +#else +#define MG1_15_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_15PL) || (G1_4PL == 0) +#define MG1_15_14PL ~(1 << 3) +#else +#define MG1_15_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_15PL) || (G1_5PL == 0) +#define MG1_15_15PL ~(1 << 4) +#else +#define MG1_15_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_15PL) || (G1_6PL == 0) +#define MG1_15_16PL ~(1 << 5) +#else +#define MG1_15_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_15PL) || (G1_7PL == 0) +#define MG1_15_17PL ~(1 << 6) +#else +#define MG1_15_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_15PL) || (G1_8PL == 0) +#define MG1_15_18PL ~(1 << 7) +#else +#define MG1_15_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_15PL) || (G1_9PL == 0) +#define MG1_15_19PL ~(1 << 8) +#else +#define MG1_15_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_15PL) || (G1_10PL == 0) +#define MG1_15_110PL ~(1 << 9) +#else +#define MG1_15_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_15PL) || (G1_11PL == 0) +#define MG1_15_111PL ~(1 << 10) +#else +#define MG1_15_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_15PL) || (G1_12PL == 0) +#define MG1_15_112PL ~(1 << 11) +#else +#define MG1_15_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_15PL) || (G1_13PL == 0) +#define MG1_15_113PL ~(1 << 12) +#else +#define MG1_15_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_15PL) || (G1_14PL == 0) +#define MG1_15_114PL ~(1 << 13) +#else +#define MG1_15_114PL 0xFFFF +#endif + +#if (G1_16PL >= G1_15PL) || (G1_16PL == 0) +#define MG1_15_116PL ~(1 << 15) +#else +#define MG1_15_116PL 0xFFFF +#endif + +#define MG1_15_115PL 0xBFFF +#define MG1_15 (MG1_15_11PL & MG1_15_12PL & MG1_15_13PL & MG1_15_14PL & \ + MG1_15_15PL & MG1_15_16PL & MG1_15_17PL & MG1_15_18PL & \ + MG1_15_19PL & MG1_15_110PL & MG1_15_111PL & MG1_15_112PL & \ + MG1_15_113PL & MG1_15_114PL & MG1_15_115PL & MG1_15_116PL) +// End of MG1_15: +// Beginning of MG116: +#if (G1_1PL >= G1_16PL) || (G1_1PL == 0) +#define MG1_16_11PL ~(1 << 0) +#else +#define MG1_16_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_16PL) || (G1_2PL == 0) +#define MG1_16_12PL ~(1 << 1) +#else +#define MG1_16_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_16PL) || (G1_3PL == 0) +#define MG1_16_13PL ~(1 << 2) +#else +#define MG1_16_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_16PL) || (G1_4PL == 0) +#define MG1_16_14PL ~(1 << 3) +#else +#define MG1_16_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_16PL) || (G1_5PL == 0) +#define MG1_16_15PL ~(1 << 4) +#else +#define MG1_16_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_16PL) || (G1_6PL == 0) +#define MG1_16_16PL ~(1 << 5) +#else +#define MG1_16_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_16PL) || (G1_7PL == 0) +#define MG1_16_17PL ~(1 << 6) +#else +#define MG1_16_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_16PL) || (G1_8PL == 0) +#define MG1_16_18PL ~(1 << 7) +#else +#define MG1_16_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_16PL) || (G1_9PL == 0) +#define MG1_16_19PL ~(1 << 8) +#else +#define MG1_16_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_16PL) || (G1_10PL == 0) +#define MG1_16_110PL ~(1 << 9) +#else +#define MG1_16_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_16PL) || (G1_11PL == 0) +#define MG1_16_111PL ~(1 << 10) +#else +#define MG1_16_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_16PL) || (G1_12PL == 0) +#define MG1_16_112PL ~(1 << 11) +#else +#define MG1_16_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_16PL) || (G1_13PL == 0) +#define MG1_16_113PL ~(1 << 12) +#else +#define MG1_16_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_16PL) || (G1_14PL == 0) +#define MG1_16_114PL ~(1 << 13) +#else +#define MG1_16_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_16PL) || (G1_15PL == 0) +#define MG1_16_115PL ~(1 << 14) +#else +#define MG1_16_115PL 0xFFFF +#endif + +#define MG1_16_116PL 0x7FFF +#define MG1_16 (MG1_16_11PL & MG1_16_12PL & MG1_16_13PL & MG1_16_14PL & \ + MG1_16_15PL & MG1_16_16PL & MG1_16_17PL & MG1_16_18PL & \ + MG1_16_19PL & MG1_16_110PL & MG1_16_111PL & MG1_16_112PL & \ + MG1_16_113PL & MG1_16_114PL & MG1_16_115PL & MG1_16_116PL) +// End of MG1_16: + + +// +// Automatically generate PIEIER2 interrupt masks MG21 to MG216: +// + +// Beginning of MG21: +#if (G2_2PL >= G2_1PL) || (G2_2PL == 0) +#define MG2_1_12PL ~(1 << 1) +#else +#define MG2_1_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_1PL) || (G2_3PL == 0) +#define MG2_1_13PL ~(1 << 2) +#else +#define MG2_1_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_1PL) || (G2_4PL == 0) +#define MG2_1_14PL ~(1 << 3) +#else +#define MG2_1_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_1PL) || (G2_5PL == 0) +#define MG2_1_15PL ~(1 << 4) +#else +#define MG2_1_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_1PL) || (G2_6PL == 0) +#define MG2_1_16PL ~(1 << 5) +#else +#define MG2_1_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_1PL) || (G2_7PL == 0) +#define MG2_1_17PL ~(1 << 6) +#else +#define MG2_1_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_1PL) || (G2_8PL == 0) +#define MG2_1_18PL ~(1 << 7) +#else +#define MG2_1_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_1PL) || (G2_9PL == 0) +#define MG2_1_19PL ~(1 << 8) +#else +#define MG2_1_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_1PL) || (G2_10PL == 0) +#define MG2_1_110PL ~(1 << 9) +#else +#define MG2_1_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_1PL) || (G2_11PL == 0) +#define MG2_1_111PL ~(1 << 10) +#else +#define MG2_1_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_1PL) || (G2_12PL == 0) +#define MG2_1_112PL ~(1 << 11) +#else +#define MG2_1_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_1PL) || (G2_13PL == 0) +#define MG2_1_113PL ~(1 << 12) +#else +#define MG2_1_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_1PL) || (G2_14PL == 0) +#define MG2_1_114PL ~(1 << 13) +#else +#define MG2_1_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_1PL) || (G2_15PL == 0) +#define MG2_1_115PL ~(1 << 14) +#else +#define MG2_1_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_1PL) || (G2_16PL == 0) +#define MG2_1_116PL ~(1 << 15) +#else +#define MG2_1_116PL 0xFFFF +#endif + +#define MG2_1_11PL 0xFFFE +#define MG2_1 (MG2_1_11PL & MG2_1_12PL & MG2_1_13PL & MG2_1_14PL & \ + MG2_1_15PL & MG2_1_16PL & MG2_1_17PL & MG2_1_18PL & \ + MG2_1_19PL & MG2_1_110PL & MG2_1_111PL & MG2_1_112PL & \ + MG2_1_113PL & MG2_1_114PL & MG2_1_115PL & MG2_1_116PL) +// End of MG2_1: +// Beginning of MG22: +#if (G2_1PL >= G2_2PL) || (G2_1PL == 0) +#define MG2_2_11PL ~(1 << 0) +#else +#define MG2_2_11PL 0xFFFF +#endif + +#if (G2_3PL >= G2_2PL) || (G2_3PL == 0) +#define MG2_2_13PL ~(1 << 2) +#else +#define MG2_2_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_2PL) || (G2_4PL == 0) +#define MG2_2_14PL ~(1 << 3) +#else +#define MG2_2_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_2PL) || (G2_5PL == 0) +#define MG2_2_15PL ~(1 << 4) +#else +#define MG2_2_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_2PL) || (G2_6PL == 0) +#define MG2_2_16PL ~(1 << 5) +#else +#define MG2_2_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_2PL) || (G2_7PL == 0) +#define MG2_2_17PL ~(1 << 6) +#else +#define MG2_2_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_2PL) || (G2_8PL == 0) +#define MG2_2_18PL ~(1 << 7) +#else +#define MG2_2_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_2PL) || (G2_9PL == 0) +#define MG2_2_19PL ~(1 << 8) +#else +#define MG2_2_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_2PL) || (G2_10PL == 0) +#define MG2_2_110PL ~(1 << 9) +#else +#define MG2_2_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_2PL) || (G2_11PL == 0) +#define MG2_2_111PL ~(1 << 10) +#else +#define MG2_2_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_2PL) || (G2_12PL == 0) +#define MG2_2_112PL ~(1 << 11) +#else +#define MG2_2_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_2PL) || (G2_13PL == 0) +#define MG2_2_113PL ~(1 << 12) +#else +#define MG2_2_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_2PL) || (G2_14PL == 0) +#define MG2_2_114PL ~(1 << 13) +#else +#define MG2_2_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_2PL) || (G2_15PL == 0) +#define MG2_2_115PL ~(1 << 14) +#else +#define MG2_2_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_2PL) || (G2_16PL == 0) +#define MG2_2_116PL ~(1 << 15) +#else +#define MG2_2_116PL 0xFFFF +#endif + +#define MG2_2_12PL 0xFFFD +#define MG2_2 (MG2_2_11PL & MG2_2_12PL & MG2_2_13PL & MG2_2_14PL & \ + MG2_2_15PL & MG2_2_16PL & MG2_2_17PL & MG2_2_18PL & \ + MG2_2_19PL & MG2_2_110PL & MG2_2_111PL & MG2_2_112PL & \ + MG2_2_113PL & MG2_2_114PL & MG2_2_115PL & MG2_2_116PL) +// End of MG2_2: +// Beginning of MG23: +#if (G2_1PL >= G2_3PL) || (G2_1PL == 0) +#define MG2_3_11PL ~(1 << 0) +#else +#define MG2_3_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_3PL) || (G2_2PL == 0) +#define MG2_3_12PL ~(1 << 1) +#else +#define MG2_3_12PL 0xFFFF +#endif + +#if (G2_4PL >= G2_3PL) || (G2_4PL == 0) +#define MG2_3_14PL ~(1 << 3) +#else +#define MG2_3_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_3PL) || (G2_5PL == 0) +#define MG2_3_15PL ~(1 << 4) +#else +#define MG2_3_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_3PL) || (G2_6PL == 0) +#define MG2_3_16PL ~(1 << 5) +#else +#define MG2_3_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_3PL) || (G2_7PL == 0) +#define MG2_3_17PL ~(1 << 6) +#else +#define MG2_3_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_3PL) || (G2_8PL == 0) +#define MG2_3_18PL ~(1 << 7) +#else +#define MG2_3_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_3PL) || (G2_9PL == 0) +#define MG2_3_19PL ~(1 << 8) +#else +#define MG2_3_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_3PL) || (G2_10PL == 0) +#define MG2_3_110PL ~(1 << 9) +#else +#define MG2_3_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_3PL) || (G2_11PL == 0) +#define MG2_3_111PL ~(1 << 10) +#else +#define MG2_3_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_3PL) || (G2_12PL == 0) +#define MG2_3_112PL ~(1 << 11) +#else +#define MG2_3_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_3PL) || (G2_13PL == 0) +#define MG2_3_113PL ~(1 << 12) +#else +#define MG2_3_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_3PL) || (G2_14PL == 0) +#define MG2_3_114PL ~(1 << 13) +#else +#define MG2_3_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_3PL) || (G2_15PL == 0) +#define MG2_3_115PL ~(1 << 14) +#else +#define MG2_3_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_3PL) || (G2_16PL == 0) +#define MG2_3_116PL ~(1 << 15) +#else +#define MG2_3_116PL 0xFFFF +#endif + +#define MG2_3_13PL 0xFFFB +#define MG2_3 (MG2_3_11PL & MG2_3_12PL & MG2_3_13PL & MG2_3_14PL & \ + MG2_3_15PL & MG2_3_16PL & MG2_3_17PL & MG2_3_18PL & \ + MG2_3_19PL & MG2_3_110PL & MG2_3_111PL & MG2_3_112PL & \ + MG2_3_113PL & MG2_3_114PL & MG2_3_115PL & MG2_3_116PL) +// End of MG2_3: +// Beginning of MG24: +#if (G2_1PL >= G2_4PL) || (G2_1PL == 0) +#define MG2_4_11PL ~(1 << 0) +#else +#define MG2_4_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_4PL) || (G2_2PL == 0) +#define MG2_4_12PL ~(1 << 1) +#else +#define MG2_4_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_4PL) || (G2_3PL == 0) +#define MG2_4_13PL ~(1 << 2) +#else +#define MG2_4_13PL 0xFFFF +#endif + +#if (G2_5PL >= G2_4PL) || (G2_5PL == 0) +#define MG2_4_15PL ~(1 << 4) +#else +#define MG2_4_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_4PL) || (G2_6PL == 0) +#define MG2_4_16PL ~(1 << 5) +#else +#define MG2_4_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_4PL) || (G2_7PL == 0) +#define MG2_4_17PL ~(1 << 6) +#else +#define MG2_4_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_4PL) || (G2_8PL == 0) +#define MG2_4_18PL ~(1 << 7) +#else +#define MG2_4_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_4PL) || (G2_9PL == 0) +#define MG2_4_19PL ~(1 << 8) +#else +#define MG2_4_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_4PL) || (G2_10PL == 0) +#define MG2_4_110PL ~(1 << 9) +#else +#define MG2_4_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_4PL) || (G2_11PL == 0) +#define MG2_4_111PL ~(1 << 10) +#else +#define MG2_4_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_4PL) || (G2_12PL == 0) +#define MG2_4_112PL ~(1 << 11) +#else +#define MG2_4_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_4PL) || (G2_13PL == 0) +#define MG2_4_113PL ~(1 << 12) +#else +#define MG2_4_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_4PL) || (G2_14PL == 0) +#define MG2_4_114PL ~(1 << 13) +#else +#define MG2_4_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_4PL) || (G2_15PL == 0) +#define MG2_4_115PL ~(1 << 14) +#else +#define MG2_4_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_4PL) || (G2_16PL == 0) +#define MG2_4_116PL ~(1 << 15) +#else +#define MG2_4_116PL 0xFFFF +#endif + +#define MG2_4_14PL 0xFFF7 +#define MG2_4 (MG2_4_11PL & MG2_4_12PL & MG2_4_13PL & MG2_4_14PL & \ + MG2_4_15PL & MG2_4_16PL & MG2_4_17PL & MG2_4_18PL & \ + MG2_4_19PL & MG2_4_110PL & MG2_4_111PL & MG2_4_112PL & \ + MG2_4_113PL & MG2_4_114PL & MG2_4_115PL & MG2_4_116PL) +// End of MG2_4: +// Beginning of MG25: +#if (G2_1PL >= G2_5PL) || (G2_1PL == 0) +#define MG2_5_11PL ~(1 << 0) +#else +#define MG2_5_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_5PL) || (G2_2PL == 0) +#define MG2_5_12PL ~(1 << 1) +#else +#define MG2_5_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_5PL) || (G2_3PL == 0) +#define MG2_5_13PL ~(1 << 2) +#else +#define MG2_5_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_5PL) || (G2_4PL == 0) +#define MG2_5_14PL ~(1 << 3) +#else +#define MG2_5_14PL 0xFFFF +#endif + +#if (G2_6PL >= G2_5PL) || (G2_6PL == 0) +#define MG2_5_16PL ~(1 << 5) +#else +#define MG2_5_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_5PL) || (G2_7PL == 0) +#define MG2_5_17PL ~(1 << 6) +#else +#define MG2_5_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_5PL) || (G2_8PL == 0) +#define MG2_5_18PL ~(1 << 7) +#else +#define MG2_5_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_5PL) || (G2_9PL == 0) +#define MG2_5_19PL ~(1 << 8) +#else +#define MG2_5_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_5PL) || (G2_10PL == 0) +#define MG2_5_110PL ~(1 << 9) +#else +#define MG2_5_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_5PL) || (G2_11PL == 0) +#define MG2_5_111PL ~(1 << 10) +#else +#define MG2_5_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_5PL) || (G2_12PL == 0) +#define MG2_5_112PL ~(1 << 11) +#else +#define MG2_5_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_5PL) || (G2_13PL == 0) +#define MG2_5_113PL ~(1 << 12) +#else +#define MG2_5_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_5PL) || (G2_14PL == 0) +#define MG2_5_114PL ~(1 << 13) +#else +#define MG2_5_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_5PL) || (G2_15PL == 0) +#define MG2_5_115PL ~(1 << 14) +#else +#define MG2_5_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_5PL) || (G2_16PL == 0) +#define MG2_5_116PL ~(1 << 15) +#else +#define MG2_5_116PL 0xFFFF +#endif + +#define MG2_5_15PL 0xFFEF +#define MG2_5 (MG2_5_11PL & MG2_5_12PL & MG2_5_13PL & MG2_5_14PL & \ + MG2_5_15PL & MG2_5_16PL & MG2_5_17PL & MG2_5_18PL & \ + MG2_5_19PL & MG2_5_110PL & MG2_5_111PL & MG2_5_112PL & \ + MG2_5_113PL & MG2_5_114PL & MG2_5_115PL & MG2_5_116PL) +// End of MG2_5: +// Beginning of MG26: +#if (G2_1PL >= G2_6PL) || (G2_1PL == 0) +#define MG2_6_11PL ~(1 << 0) +#else +#define MG2_6_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_6PL) || (G2_2PL == 0) +#define MG2_6_12PL ~(1 << 1) +#else +#define MG2_6_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_6PL) || (G2_3PL == 0) +#define MG2_6_13PL ~(1 << 2) +#else +#define MG2_6_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_6PL) || (G2_4PL == 0) +#define MG2_6_14PL ~(1 << 3) +#else +#define MG2_6_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_6PL) || (G2_5PL == 0) +#define MG2_6_15PL ~(1 << 4) +#else +#define MG2_6_15PL 0xFFFF +#endif + +#if (G2_7PL >= G2_6PL) || (G2_7PL == 0) +#define MG2_6_17PL ~(1 << 6) +#else +#define MG2_6_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_6PL) || (G2_8PL == 0) +#define MG2_6_18PL ~(1 << 7) +#else +#define MG2_6_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_6PL) || (G2_9PL == 0) +#define MG2_6_19PL ~(1 << 8) +#else +#define MG2_6_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_6PL) || (G2_10PL == 0) +#define MG2_6_110PL ~(1 << 9) +#else +#define MG2_6_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_6PL) || (G2_11PL == 0) +#define MG2_6_111PL ~(1 << 10) +#else +#define MG2_6_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_6PL) || (G2_12PL == 0) +#define MG2_6_112PL ~(1 << 11) +#else +#define MG2_6_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_6PL) || (G2_13PL == 0) +#define MG2_6_113PL ~(1 << 12) +#else +#define MG2_6_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_6PL) || (G2_14PL == 0) +#define MG2_6_114PL ~(1 << 13) +#else +#define MG2_6_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_6PL) || (G2_15PL == 0) +#define MG2_6_115PL ~(1 << 14) +#else +#define MG2_6_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_6PL) || (G2_16PL == 0) +#define MG2_6_116PL ~(1 << 15) +#else +#define MG2_6_116PL 0xFFFF +#endif + +#define MG2_6_16PL 0xFFDF +#define MG2_6 (MG2_6_11PL & MG2_6_12PL & MG2_6_13PL & MG2_6_14PL & \ + MG2_6_15PL & MG2_6_16PL & MG2_6_17PL & MG2_6_18PL & \ + MG2_6_19PL & MG2_6_110PL & MG2_6_111PL & MG2_6_112PL & \ + MG2_6_113PL & MG2_6_114PL & MG2_6_115PL & MG2_6_116PL) +// End of MG2_6: +// Beginning of MG27: +#if (G2_1PL >= G2_7PL) || (G2_1PL == 0) +#define MG2_7_11PL ~(1 << 0) +#else +#define MG2_7_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_7PL) || (G2_2PL == 0) +#define MG2_7_12PL ~(1 << 1) +#else +#define MG2_7_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_7PL) || (G2_3PL == 0) +#define MG2_7_13PL ~(1 << 2) +#else +#define MG2_7_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_7PL) || (G2_4PL == 0) +#define MG2_7_14PL ~(1 << 3) +#else +#define MG2_7_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_7PL) || (G2_5PL == 0) +#define MG2_7_15PL ~(1 << 4) +#else +#define MG2_7_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_7PL) || (G2_6PL == 0) +#define MG2_7_16PL ~(1 << 5) +#else +#define MG2_7_16PL 0xFFFF +#endif + +#if (G2_8PL >= G2_7PL) || (G2_8PL == 0) +#define MG2_7_18PL ~(1 << 7) +#else +#define MG2_7_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_7PL) || (G2_9PL == 0) +#define MG2_7_19PL ~(1 << 8) +#else +#define MG2_7_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_7PL) || (G2_10PL == 0) +#define MG2_7_110PL ~(1 << 9) +#else +#define MG2_7_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_7PL) || (G2_11PL == 0) +#define MG2_7_111PL ~(1 << 10) +#else +#define MG2_7_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_7PL) || (G2_12PL == 0) +#define MG2_7_112PL ~(1 << 11) +#else +#define MG2_7_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_7PL) || (G2_13PL == 0) +#define MG2_7_113PL ~(1 << 12) +#else +#define MG2_7_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_7PL) || (G2_14PL == 0) +#define MG2_7_114PL ~(1 << 13) +#else +#define MG2_7_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_7PL) || (G2_15PL == 0) +#define MG2_7_115PL ~(1 << 14) +#else +#define MG2_7_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_7PL) || (G2_16PL == 0) +#define MG2_7_116PL ~(1 << 15) +#else +#define MG2_7_116PL 0xFFFF +#endif + +#define MG2_7_17PL 0xFFBF +#define MG2_7 (MG2_7_11PL & MG2_7_12PL & MG2_7_13PL & MG2_7_14PL & \ + MG2_7_15PL & MG2_7_16PL & MG2_7_17PL & MG2_7_18PL & \ + MG2_7_19PL & MG2_7_110PL & MG2_7_111PL & MG2_7_112PL & \ + MG2_7_113PL & MG2_7_114PL & MG2_7_115PL & MG2_7_116PL) +// End of MG2_7: +// Beginning of MG28: +#if (G2_1PL >= G2_8PL) || (G2_1PL == 0) +#define MG2_8_11PL ~(1 << 0) +#else +#define MG2_8_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_8PL) || (G2_2PL == 0) +#define MG2_8_12PL ~(1 << 1) +#else +#define MG2_8_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_8PL) || (G2_3PL == 0) +#define MG2_8_13PL ~(1 << 2) +#else +#define MG2_8_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_8PL) || (G2_4PL == 0) +#define MG2_8_14PL ~(1 << 3) +#else +#define MG2_8_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_8PL) || (G2_5PL == 0) +#define MG2_8_15PL ~(1 << 4) +#else +#define MG2_8_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_8PL) || (G2_6PL == 0) +#define MG2_8_16PL ~(1 << 5) +#else +#define MG2_8_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_8PL) || (G2_7PL == 0) +#define MG2_8_17PL ~(1 << 6) +#else +#define MG2_8_17PL 0xFFFF +#endif + +#if (G2_9PL >= G2_8PL) || (G2_9PL == 0) +#define MG2_8_19PL ~(1 << 8) +#else +#define MG2_8_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_8PL) || (G2_10PL == 0) +#define MG2_8_110PL ~(1 << 9) +#else +#define MG2_8_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_8PL) || (G2_11PL == 0) +#define MG2_8_111PL ~(1 << 10) +#else +#define MG2_8_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_8PL) || (G2_12PL == 0) +#define MG2_8_112PL ~(1 << 11) +#else +#define MG2_8_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_8PL) || (G2_13PL == 0) +#define MG2_8_113PL ~(1 << 12) +#else +#define MG2_8_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_8PL) || (G2_14PL == 0) +#define MG2_8_114PL ~(1 << 13) +#else +#define MG2_8_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_8PL) || (G2_15PL == 0) +#define MG2_8_115PL ~(1 << 14) +#else +#define MG2_8_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_8PL) || (G2_16PL == 0) +#define MG2_8_116PL ~(1 << 15) +#else +#define MG2_8_116PL 0xFFFF +#endif + +#define MG2_8_18PL 0xFF7F +#define MG2_8 (MG2_8_11PL & MG2_8_12PL & MG2_8_13PL & MG2_8_14PL & \ + MG2_8_15PL & MG2_8_16PL & MG2_8_17PL & MG2_8_18PL & \ + MG2_8_19PL & MG2_8_110PL & MG2_8_111PL & MG2_8_112PL & \ + MG2_8_113PL & MG2_8_114PL & MG2_8_115PL & MG2_8_116PL) +// End of MG2_8: +// Beginning of MG29: +#if (G2_1PL >= G2_9PL) || (G2_1PL == 0) +#define MG2_9_11PL ~(1 << 0) +#else +#define MG2_9_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_9PL) || (G2_2PL == 0) +#define MG2_9_12PL ~(1 << 1) +#else +#define MG2_9_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_9PL) || (G2_3PL == 0) +#define MG2_9_13PL ~(1 << 2) +#else +#define MG2_9_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_9PL) || (G2_4PL == 0) +#define MG2_9_14PL ~(1 << 3) +#else +#define MG2_9_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_9PL) || (G2_5PL == 0) +#define MG2_9_15PL ~(1 << 4) +#else +#define MG2_9_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_9PL) || (G2_6PL == 0) +#define MG2_9_16PL ~(1 << 5) +#else +#define MG2_9_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_9PL) || (G2_7PL == 0) +#define MG2_9_17PL ~(1 << 6) +#else +#define MG2_9_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_9PL) || (G2_8PL == 0) +#define MG2_9_18PL ~(1 << 7) +#else +#define MG2_9_18PL 0xFFFF +#endif + +#if (G2_10PL >= G2_9PL) || (G2_10PL == 0) +#define MG2_9_110PL ~(1 << 9) +#else +#define MG2_9_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_9PL) || (G2_11PL == 0) +#define MG2_9_111PL ~(1 << 10) +#else +#define MG2_9_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_9PL) || (G2_12PL == 0) +#define MG2_9_112PL ~(1 << 11) +#else +#define MG2_9_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_9PL) || (G2_13PL == 0) +#define MG2_9_113PL ~(1 << 12) +#else +#define MG2_9_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_9PL) || (G2_14PL == 0) +#define MG2_9_114PL ~(1 << 13) +#else +#define MG2_9_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_9PL) || (G2_15PL == 0) +#define MG2_9_115PL ~(1 << 14) +#else +#define MG2_9_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_9PL) || (G2_16PL == 0) +#define MG2_9_116PL ~(1 << 15) +#else +#define MG2_9_116PL 0xFFFF +#endif + +#define MG2_9_19PL 0xFEFF +#define MG2_9 (MG2_9_11PL & MG2_9_12PL & MG2_9_13PL & MG2_9_14PL & \ + MG2_9_15PL & MG2_9_16PL & MG2_9_17PL & MG2_9_18PL & \ + MG2_9_19PL & MG2_9_110PL & MG2_9_111PL & MG2_9_112PL & \ + MG2_9_113PL & MG2_9_114PL & MG2_9_115PL & MG2_9_116PL) +// End of MG2_9: +// Beginning of MG210: +#if (G2_1PL >= G2_10PL) || (G2_1PL == 0) +#define MG2_10_11PL ~(1 << 0) +#else +#define MG2_10_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_10PL) || (G2_2PL == 0) +#define MG2_10_12PL ~(1 << 1) +#else +#define MG2_10_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_10PL) || (G2_3PL == 0) +#define MG2_10_13PL ~(1 << 2) +#else +#define MG2_10_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_10PL) || (G2_4PL == 0) +#define MG2_10_14PL ~(1 << 3) +#else +#define MG2_10_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_10PL) || (G2_5PL == 0) +#define MG2_10_15PL ~(1 << 4) +#else +#define MG2_10_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_10PL) || (G2_6PL == 0) +#define MG2_10_16PL ~(1 << 5) +#else +#define MG2_10_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_10PL) || (G2_7PL == 0) +#define MG2_10_17PL ~(1 << 6) +#else +#define MG2_10_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_10PL) || (G2_8PL == 0) +#define MG2_10_18PL ~(1 << 7) +#else +#define MG2_10_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_10PL) || (G2_9PL == 0) +#define MG2_10_19PL ~(1 << 8) +#else +#define MG2_10_19PL 0xFFFF +#endif + +#if (G2_11PL >= G2_10PL) || (G2_11PL == 0) +#define MG2_10_111PL ~(1 << 10) +#else +#define MG2_10_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_10PL) || (G2_12PL == 0) +#define MG2_10_112PL ~(1 << 11) +#else +#define MG2_10_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_10PL) || (G2_13PL == 0) +#define MG2_10_113PL ~(1 << 12) +#else +#define MG2_10_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_10PL) || (G2_14PL == 0) +#define MG2_10_114PL ~(1 << 13) +#else +#define MG2_10_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_10PL) || (G2_15PL == 0) +#define MG2_10_115PL ~(1 << 14) +#else +#define MG2_10_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_10PL) || (G2_16PL == 0) +#define MG2_10_116PL ~(1 << 15) +#else +#define MG2_10_116PL 0xFFFF +#endif + +#define MG2_10_110PL 0xFDFF +#define MG2_10 (MG2_10_11PL & MG2_10_12PL & MG2_10_13PL & MG2_10_14PL & \ + MG2_10_15PL & MG2_10_16PL & MG2_10_17PL & MG2_10_18PL & \ + MG2_10_19PL & MG2_10_110PL & MG2_10_111PL & MG2_10_112PL & \ + MG2_10_113PL & MG2_10_114PL & MG2_10_115PL & MG2_10_116PL) +// End of MG2_10: +// Beginning of MG211: +#if (G2_1PL >= G2_11PL) || (G2_1PL == 0) +#define MG2_11_11PL ~(1 << 0) +#else +#define MG2_11_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_11PL) || (G2_2PL == 0) +#define MG2_11_12PL ~(1 << 1) +#else +#define MG2_11_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_11PL) || (G2_3PL == 0) +#define MG2_11_13PL ~(1 << 2) +#else +#define MG2_11_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_11PL) || (G2_4PL == 0) +#define MG2_11_14PL ~(1 << 3) +#else +#define MG2_11_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_11PL) || (G2_5PL == 0) +#define MG2_11_15PL ~(1 << 4) +#else +#define MG2_11_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_11PL) || (G2_6PL == 0) +#define MG2_11_16PL ~(1 << 5) +#else +#define MG2_11_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_11PL) || (G2_7PL == 0) +#define MG2_11_17PL ~(1 << 6) +#else +#define MG2_11_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_11PL) || (G2_8PL == 0) +#define MG2_11_18PL ~(1 << 7) +#else +#define MG2_11_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_11PL) || (G2_9PL == 0) +#define MG2_11_19PL ~(1 << 8) +#else +#define MG2_11_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_11PL) || (G2_10PL == 0) +#define MG2_11_110PL ~(1 << 9) +#else +#define MG2_11_110PL 0xFFFF +#endif + +#if (G2_12PL >= G2_11PL) || (G2_12PL == 0) +#define MG2_11_112PL ~(1 << 11) +#else +#define MG2_11_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_11PL) || (G2_13PL == 0) +#define MG2_11_113PL ~(1 << 12) +#else +#define MG2_11_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_11PL) || (G2_14PL == 0) +#define MG2_11_114PL ~(1 << 13) +#else +#define MG2_11_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_11PL) || (G2_15PL == 0) +#define MG2_11_115PL ~(1 << 14) +#else +#define MG2_11_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_11PL) || (G2_16PL == 0) +#define MG2_11_116PL ~(1 << 15) +#else +#define MG2_11_116PL 0xFFFF +#endif + +#define MG2_11_111PL 0xFBFF +#define MG2_11 (MG2_11_11PL & MG2_11_12PL & MG2_11_13PL & MG2_11_14PL & \ + MG2_11_15PL & MG2_11_16PL & MG2_11_17PL & MG2_11_18PL & \ + MG2_11_19PL & MG2_11_110PL & MG2_11_111PL & MG2_11_112PL & \ + MG2_11_113PL & MG2_11_114PL & MG2_11_115PL & MG2_11_116PL) +// End of MG2_11: +// Beginning of MG212: +#if (G2_1PL >= G2_12PL) || (G2_1PL == 0) +#define MG2_12_11PL ~(1 << 0) +#else +#define MG2_12_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_12PL) || (G2_2PL == 0) +#define MG2_12_12PL ~(1 << 1) +#else +#define MG2_12_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_12PL) || (G2_3PL == 0) +#define MG2_12_13PL ~(1 << 2) +#else +#define MG2_12_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_12PL) || (G2_4PL == 0) +#define MG2_12_14PL ~(1 << 3) +#else +#define MG2_12_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_12PL) || (G2_5PL == 0) +#define MG2_12_15PL ~(1 << 4) +#else +#define MG2_12_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_12PL) || (G2_6PL == 0) +#define MG2_12_16PL ~(1 << 5) +#else +#define MG2_12_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_12PL) || (G2_7PL == 0) +#define MG2_12_17PL ~(1 << 6) +#else +#define MG2_12_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_12PL) || (G2_8PL == 0) +#define MG2_12_18PL ~(1 << 7) +#else +#define MG2_12_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_12PL) || (G2_9PL == 0) +#define MG2_12_19PL ~(1 << 8) +#else +#define MG2_12_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_12PL) || (G2_10PL == 0) +#define MG2_12_110PL ~(1 << 9) +#else +#define MG2_12_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_12PL) || (G2_11PL == 0) +#define MG2_12_111PL ~(1 << 10) +#else +#define MG2_12_111PL 0xFFFF +#endif + +#if (G2_13PL >= G2_12PL) || (G2_13PL == 0) +#define MG2_12_113PL ~(1 << 12) +#else +#define MG2_12_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_12PL) || (G2_14PL == 0) +#define MG2_12_114PL ~(1 << 13) +#else +#define MG2_12_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_12PL) || (G2_15PL == 0) +#define MG2_12_115PL ~(1 << 14) +#else +#define MG2_12_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_12PL) || (G2_16PL == 0) +#define MG2_12_116PL ~(1 << 15) +#else +#define MG2_12_116PL 0xFFFF +#endif + +#define MG2_12_112PL 0xF7FF +#define MG2_12 (MG2_12_11PL & MG2_12_12PL & MG2_12_13PL & MG2_12_14PL & \ + MG2_12_15PL & MG2_12_16PL & MG2_12_17PL & MG2_12_18PL & \ + MG2_12_19PL & MG2_12_110PL & MG2_12_111PL & MG2_12_112PL & \ + MG2_12_113PL & MG2_12_114PL & MG2_12_115PL & MG2_12_116PL) +// End of MG2_12: +// Beginning of MG213: +#if (G2_1PL >= G2_13PL) || (G2_1PL == 0) +#define MG2_13_11PL ~(1 << 0) +#else +#define MG2_13_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_13PL) || (G2_2PL == 0) +#define MG2_13_12PL ~(1 << 1) +#else +#define MG2_13_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_13PL) || (G2_3PL == 0) +#define MG2_13_13PL ~(1 << 2) +#else +#define MG2_13_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_13PL) || (G2_4PL == 0) +#define MG2_13_14PL ~(1 << 3) +#else +#define MG2_13_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_13PL) || (G2_5PL == 0) +#define MG2_13_15PL ~(1 << 4) +#else +#define MG2_13_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_13PL) || (G2_6PL == 0) +#define MG2_13_16PL ~(1 << 5) +#else +#define MG2_13_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_13PL) || (G2_7PL == 0) +#define MG2_13_17PL ~(1 << 6) +#else +#define MG2_13_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_13PL) || (G2_8PL == 0) +#define MG2_13_18PL ~(1 << 7) +#else +#define MG2_13_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_13PL) || (G2_9PL == 0) +#define MG2_13_19PL ~(1 << 8) +#else +#define MG2_13_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_13PL) || (G2_10PL == 0) +#define MG2_13_110PL ~(1 << 9) +#else +#define MG2_13_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_13PL) || (G2_11PL == 0) +#define MG2_13_111PL ~(1 << 10) +#else +#define MG2_13_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_13PL) || (G2_12PL == 0) +#define MG2_13_112PL ~(1 << 11) +#else +#define MG2_13_112PL 0xFFFF +#endif + +#if (G2_14PL >= G2_13PL) || (G2_14PL == 0) +#define MG2_13_114PL ~(1 << 13) +#else +#define MG2_13_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_13PL) || (G2_15PL == 0) +#define MG2_13_115PL ~(1 << 14) +#else +#define MG2_13_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_13PL) || (G2_16PL == 0) +#define MG2_13_116PL ~(1 << 15) +#else +#define MG2_13_116PL 0xFFFF +#endif + +#define MG2_13_113PL 0xEFFF +#define MG2_13 (MG2_13_11PL & MG2_13_12PL & MG2_13_13PL & MG2_13_14PL & \ + MG2_13_15PL & MG2_13_16PL & MG2_13_17PL & MG2_13_18PL & \ + MG2_13_19PL & MG2_13_110PL & MG2_13_111PL & MG2_13_112PL & \ + MG2_13_113PL & MG2_13_114PL & MG2_13_115PL & MG2_13_116PL) +// End of MG2_13: +// Beginning of MG214: +#if (G2_1PL >= G2_14PL) || (G2_1PL == 0) +#define MG2_14_11PL ~(1 << 0) +#else +#define MG2_14_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_14PL) || (G2_2PL == 0) +#define MG2_14_12PL ~(1 << 1) +#else +#define MG2_14_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_14PL) || (G2_3PL == 0) +#define MG2_14_13PL ~(1 << 2) +#else +#define MG2_14_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_14PL) || (G2_4PL == 0) +#define MG2_14_14PL ~(1 << 3) +#else +#define MG2_14_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_14PL) || (G2_5PL == 0) +#define MG2_14_15PL ~(1 << 4) +#else +#define MG2_14_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_14PL) || (G2_6PL == 0) +#define MG2_14_16PL ~(1 << 5) +#else +#define MG2_14_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_14PL) || (G2_7PL == 0) +#define MG2_14_17PL ~(1 << 6) +#else +#define MG2_14_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_14PL) || (G2_8PL == 0) +#define MG2_14_18PL ~(1 << 7) +#else +#define MG2_14_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_14PL) || (G2_9PL == 0) +#define MG2_14_19PL ~(1 << 8) +#else +#define MG2_14_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_14PL) || (G2_10PL == 0) +#define MG2_14_110PL ~(1 << 9) +#else +#define MG2_14_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_14PL) || (G2_11PL == 0) +#define MG2_14_111PL ~(1 << 10) +#else +#define MG2_14_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_14PL) || (G2_12PL == 0) +#define MG2_14_112PL ~(1 << 11) +#else +#define MG2_14_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_14PL) || (G2_13PL == 0) +#define MG2_14_113PL ~(1 << 12) +#else +#define MG2_14_113PL 0xFFFF +#endif + +#if (G2_15PL >= G2_14PL) || (G2_15PL == 0) +#define MG2_14_115PL ~(1 << 14) +#else +#define MG2_14_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_14PL) || (G2_16PL == 0) +#define MG2_14_116PL ~(1 << 15) +#else +#define MG2_14_116PL 0xFFFF +#endif + +#define MG2_14_114PL 0xDFFF +#define MG2_14 (MG2_14_11PL & MG2_14_12PL & MG2_14_13PL & MG2_14_14PL & \ + MG2_14_15PL & MG2_14_16PL & MG2_14_17PL & MG2_14_18PL & \ + MG2_14_19PL & MG2_14_110PL & MG2_14_111PL & MG2_14_112PL & \ + MG2_14_113PL & MG2_14_114PL & MG2_14_115PL & MG2_14_116PL) +// End of MG2_14: +// Beginning of MG215: +#if (G2_1PL >= G2_15PL) || (G2_1PL == 0) +#define MG2_15_11PL ~(1 << 0) +#else +#define MG2_15_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_15PL) || (G2_2PL == 0) +#define MG2_15_12PL ~(1 << 1) +#else +#define MG2_15_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_15PL) || (G2_3PL == 0) +#define MG2_15_13PL ~(1 << 2) +#else +#define MG2_15_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_15PL) || (G2_4PL == 0) +#define MG2_15_14PL ~(1 << 3) +#else +#define MG2_15_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_15PL) || (G2_5PL == 0) +#define MG2_15_15PL ~(1 << 4) +#else +#define MG2_15_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_15PL) || (G2_6PL == 0) +#define MG2_15_16PL ~(1 << 5) +#else +#define MG2_15_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_15PL) || (G2_7PL == 0) +#define MG2_15_17PL ~(1 << 6) +#else +#define MG2_15_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_15PL) || (G2_8PL == 0) +#define MG2_15_18PL ~(1 << 7) +#else +#define MG2_15_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_15PL) || (G2_9PL == 0) +#define MG2_15_19PL ~(1 << 8) +#else +#define MG2_15_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_15PL) || (G2_10PL == 0) +#define MG2_15_110PL ~(1 << 9) +#else +#define MG2_15_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_15PL) || (G2_11PL == 0) +#define MG2_15_111PL ~(1 << 10) +#else +#define MG2_15_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_15PL) || (G2_12PL == 0) +#define MG2_15_112PL ~(1 << 11) +#else +#define MG2_15_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_15PL) || (G2_13PL == 0) +#define MG2_15_113PL ~(1 << 12) +#else +#define MG2_15_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_15PL) || (G2_14PL == 0) +#define MG2_15_114PL ~(1 << 13) +#else +#define MG2_15_114PL 0xFFFF +#endif + +#if (G2_16PL >= G2_15PL) || (G2_16PL == 0) +#define MG2_15_116PL ~(1 << 15) +#else +#define MG2_15_116PL 0xFFFF +#endif + +#define MG2_15_115PL 0xBFFF +#define MG2_15 (MG2_15_11PL & MG2_15_12PL & MG2_15_13PL & MG2_15_14PL & \ + MG2_15_15PL & MG2_15_16PL & MG2_15_17PL & MG2_15_18PL & \ + MG2_15_19PL & MG2_15_110PL & MG2_15_111PL & MG2_15_112PL & \ + MG2_15_113PL & MG2_15_114PL & MG2_15_115PL & MG2_15_116PL) +// End of MG2_15: +// Beginning of MG216: +#if (G2_1PL >= G2_16PL) || (G2_1PL == 0) +#define MG2_16_11PL ~(1 << 0) +#else +#define MG2_16_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_16PL) || (G2_2PL == 0) +#define MG2_16_12PL ~(1 << 1) +#else +#define MG2_16_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_16PL) || (G2_3PL == 0) +#define MG2_16_13PL ~(1 << 2) +#else +#define MG2_16_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_16PL) || (G2_4PL == 0) +#define MG2_16_14PL ~(1 << 3) +#else +#define MG2_16_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_16PL) || (G2_5PL == 0) +#define MG2_16_15PL ~(1 << 4) +#else +#define MG2_16_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_16PL) || (G2_6PL == 0) +#define MG2_16_16PL ~(1 << 5) +#else +#define MG2_16_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_16PL) || (G2_7PL == 0) +#define MG2_16_17PL ~(1 << 6) +#else +#define MG2_16_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_16PL) || (G2_8PL == 0) +#define MG2_16_18PL ~(1 << 7) +#else +#define MG2_16_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_16PL) || (G2_9PL == 0) +#define MG2_16_19PL ~(1 << 8) +#else +#define MG2_16_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_16PL) || (G2_10PL == 0) +#define MG2_16_110PL ~(1 << 9) +#else +#define MG2_16_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_16PL) || (G2_11PL == 0) +#define MG2_16_111PL ~(1 << 10) +#else +#define MG2_16_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_16PL) || (G2_12PL == 0) +#define MG2_16_112PL ~(1 << 11) +#else +#define MG2_16_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_16PL) || (G2_13PL == 0) +#define MG2_16_113PL ~(1 << 12) +#else +#define MG2_16_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_16PL) || (G2_14PL == 0) +#define MG2_16_114PL ~(1 << 13) +#else +#define MG2_16_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_16PL) || (G2_15PL == 0) +#define MG2_16_115PL ~(1 << 14) +#else +#define MG2_16_115PL 0xFFFF +#endif + +#define MG2_16_116PL 0x7FFF +#define MG2_16 (MG2_16_11PL & MG2_16_12PL & MG2_16_13PL & MG2_16_14PL & \ + MG2_16_15PL & MG2_16_16PL & MG2_16_17PL & MG2_16_18PL & \ + MG2_16_19PL & MG2_16_110PL & MG2_16_111PL & MG2_16_112PL & \ + MG2_16_113PL & MG2_16_114PL & MG2_16_115PL & MG2_16_116PL) +// End of MG2_16: + + +// +// Automatically generate PIEIER3 interrupt masks MG31 to MG316: +// + +// Beginning of MG31: +#if (G3_2PL >= G3_1PL) || (G3_2PL == 0) +#define MG3_1_12PL ~(1 << 1) +#else +#define MG3_1_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_1PL) || (G3_3PL == 0) +#define MG3_1_13PL ~(1 << 2) +#else +#define MG3_1_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_1PL) || (G3_4PL == 0) +#define MG3_1_14PL ~(1 << 3) +#else +#define MG3_1_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_1PL) || (G3_5PL == 0) +#define MG3_1_15PL ~(1 << 4) +#else +#define MG3_1_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_1PL) || (G3_6PL == 0) +#define MG3_1_16PL ~(1 << 5) +#else +#define MG3_1_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_1PL) || (G3_7PL == 0) +#define MG3_1_17PL ~(1 << 6) +#else +#define MG3_1_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_1PL) || (G3_8PL == 0) +#define MG3_1_18PL ~(1 << 7) +#else +#define MG3_1_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_1PL) || (G3_9PL == 0) +#define MG3_1_19PL ~(1 << 8) +#else +#define MG3_1_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_1PL) || (G3_10PL == 0) +#define MG3_1_110PL ~(1 << 9) +#else +#define MG3_1_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_1PL) || (G3_11PL == 0) +#define MG3_1_111PL ~(1 << 10) +#else +#define MG3_1_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_1PL) || (G3_12PL == 0) +#define MG3_1_112PL ~(1 << 11) +#else +#define MG3_1_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_1PL) || (G3_13PL == 0) +#define MG3_1_113PL ~(1 << 12) +#else +#define MG3_1_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_1PL) || (G3_14PL == 0) +#define MG3_1_114PL ~(1 << 13) +#else +#define MG3_1_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_1PL) || (G3_15PL == 0) +#define MG3_1_115PL ~(1 << 14) +#else +#define MG3_1_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_1PL) || (G3_16PL == 0) +#define MG3_1_116PL ~(1 << 15) +#else +#define MG3_1_116PL 0xFFFF +#endif + +#define MG3_1_11PL 0xFFFE +#define MG3_1 (MG3_1_11PL & MG3_1_12PL & MG3_1_13PL & MG3_1_14PL & \ + MG3_1_15PL & MG3_1_16PL & MG3_1_17PL & MG3_1_18PL & \ + MG3_1_19PL & MG3_1_110PL & MG3_1_111PL & MG3_1_112PL & \ + MG3_1_113PL & MG3_1_114PL & MG3_1_115PL & MG3_1_116PL) +// End of MG3_1: +// Beginning of MG32: +#if (G3_1PL >= G3_2PL) || (G3_1PL == 0) +#define MG3_2_11PL ~(1 << 0) +#else +#define MG3_2_11PL 0xFFFF +#endif + +#if (G3_3PL >= G3_2PL) || (G3_3PL == 0) +#define MG3_2_13PL ~(1 << 2) +#else +#define MG3_2_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_2PL) || (G3_4PL == 0) +#define MG3_2_14PL ~(1 << 3) +#else +#define MG3_2_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_2PL) || (G3_5PL == 0) +#define MG3_2_15PL ~(1 << 4) +#else +#define MG3_2_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_2PL) || (G3_6PL == 0) +#define MG3_2_16PL ~(1 << 5) +#else +#define MG3_2_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_2PL) || (G3_7PL == 0) +#define MG3_2_17PL ~(1 << 6) +#else +#define MG3_2_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_2PL) || (G3_8PL == 0) +#define MG3_2_18PL ~(1 << 7) +#else +#define MG3_2_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_2PL) || (G3_9PL == 0) +#define MG3_2_19PL ~(1 << 8) +#else +#define MG3_2_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_2PL) || (G3_10PL == 0) +#define MG3_2_110PL ~(1 << 9) +#else +#define MG3_2_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_2PL) || (G3_11PL == 0) +#define MG3_2_111PL ~(1 << 10) +#else +#define MG3_2_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_2PL) || (G3_12PL == 0) +#define MG3_2_112PL ~(1 << 11) +#else +#define MG3_2_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_2PL) || (G3_13PL == 0) +#define MG3_2_113PL ~(1 << 12) +#else +#define MG3_2_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_2PL) || (G3_14PL == 0) +#define MG3_2_114PL ~(1 << 13) +#else +#define MG3_2_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_2PL) || (G3_15PL == 0) +#define MG3_2_115PL ~(1 << 14) +#else +#define MG3_2_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_2PL) || (G3_16PL == 0) +#define MG3_2_116PL ~(1 << 15) +#else +#define MG3_2_116PL 0xFFFF +#endif + +#define MG3_2_12PL 0xFFFD +#define MG3_2 (MG3_2_11PL & MG3_2_12PL & MG3_2_13PL & MG3_2_14PL & \ + MG3_2_15PL & MG3_2_16PL & MG3_2_17PL & MG3_2_18PL & \ + MG3_2_19PL & MG3_2_110PL & MG3_2_111PL & MG3_2_112PL & \ + MG3_2_113PL & MG3_2_114PL & MG3_2_115PL & MG3_2_116PL) +// End of MG3_2: +// Beginning of MG33: +#if (G3_1PL >= G3_3PL) || (G3_1PL == 0) +#define MG3_3_11PL ~(1 << 0) +#else +#define MG3_3_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_3PL) || (G3_2PL == 0) +#define MG3_3_12PL ~(1 << 1) +#else +#define MG3_3_12PL 0xFFFF +#endif + +#if (G3_4PL >= G3_3PL) || (G3_4PL == 0) +#define MG3_3_14PL ~(1 << 3) +#else +#define MG3_3_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_3PL) || (G3_5PL == 0) +#define MG3_3_15PL ~(1 << 4) +#else +#define MG3_3_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_3PL) || (G3_6PL == 0) +#define MG3_3_16PL ~(1 << 5) +#else +#define MG3_3_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_3PL) || (G3_7PL == 0) +#define MG3_3_17PL ~(1 << 6) +#else +#define MG3_3_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_3PL) || (G3_8PL == 0) +#define MG3_3_18PL ~(1 << 7) +#else +#define MG3_3_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_3PL) || (G3_9PL == 0) +#define MG3_3_19PL ~(1 << 8) +#else +#define MG3_3_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_3PL) || (G3_10PL == 0) +#define MG3_3_110PL ~(1 << 9) +#else +#define MG3_3_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_3PL) || (G3_11PL == 0) +#define MG3_3_111PL ~(1 << 10) +#else +#define MG3_3_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_3PL) || (G3_12PL == 0) +#define MG3_3_112PL ~(1 << 11) +#else +#define MG3_3_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_3PL) || (G3_13PL == 0) +#define MG3_3_113PL ~(1 << 12) +#else +#define MG3_3_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_3PL) || (G3_14PL == 0) +#define MG3_3_114PL ~(1 << 13) +#else +#define MG3_3_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_3PL) || (G3_15PL == 0) +#define MG3_3_115PL ~(1 << 14) +#else +#define MG3_3_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_3PL) || (G3_16PL == 0) +#define MG3_3_116PL ~(1 << 15) +#else +#define MG3_3_116PL 0xFFFF +#endif + +#define MG3_3_13PL 0xFFFB +#define MG3_3 (MG3_3_11PL & MG3_3_12PL & MG3_3_13PL & MG3_3_14PL & \ + MG3_3_15PL & MG3_3_16PL & MG3_3_17PL & MG3_3_18PL & \ + MG3_3_19PL & MG3_3_110PL & MG3_3_111PL & MG3_3_112PL & \ + MG3_3_113PL & MG3_3_114PL & MG3_3_115PL & MG3_3_116PL) +// End of MG3_3: +// Beginning of MG34: +#if (G3_1PL >= G3_4PL) || (G3_1PL == 0) +#define MG3_4_11PL ~(1 << 0) +#else +#define MG3_4_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_4PL) || (G3_2PL == 0) +#define MG3_4_12PL ~(1 << 1) +#else +#define MG3_4_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_4PL) || (G3_3PL == 0) +#define MG3_4_13PL ~(1 << 2) +#else +#define MG3_4_13PL 0xFFFF +#endif + +#if (G3_5PL >= G3_4PL) || (G3_5PL == 0) +#define MG3_4_15PL ~(1 << 4) +#else +#define MG3_4_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_4PL) || (G3_6PL == 0) +#define MG3_4_16PL ~(1 << 5) +#else +#define MG3_4_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_4PL) || (G3_7PL == 0) +#define MG3_4_17PL ~(1 << 6) +#else +#define MG3_4_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_4PL) || (G3_8PL == 0) +#define MG3_4_18PL ~(1 << 7) +#else +#define MG3_4_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_4PL) || (G3_9PL == 0) +#define MG3_4_19PL ~(1 << 8) +#else +#define MG3_4_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_4PL) || (G3_10PL == 0) +#define MG3_4_110PL ~(1 << 9) +#else +#define MG3_4_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_4PL) || (G3_11PL == 0) +#define MG3_4_111PL ~(1 << 10) +#else +#define MG3_4_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_4PL) || (G3_12PL == 0) +#define MG3_4_112PL ~(1 << 11) +#else +#define MG3_4_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_4PL) || (G3_13PL == 0) +#define MG3_4_113PL ~(1 << 12) +#else +#define MG3_4_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_4PL) || (G3_14PL == 0) +#define MG3_4_114PL ~(1 << 13) +#else +#define MG3_4_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_4PL) || (G3_15PL == 0) +#define MG3_4_115PL ~(1 << 14) +#else +#define MG3_4_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_4PL) || (G3_16PL == 0) +#define MG3_4_116PL ~(1 << 15) +#else +#define MG3_4_116PL 0xFFFF +#endif + +#define MG3_4_14PL 0xFFF7 +#define MG3_4 (MG3_4_11PL & MG3_4_12PL & MG3_4_13PL & MG3_4_14PL & \ + MG3_4_15PL & MG3_4_16PL & MG3_4_17PL & MG3_4_18PL & \ + MG3_4_19PL & MG3_4_110PL & MG3_4_111PL & MG3_4_112PL & \ + MG3_4_113PL & MG3_4_114PL & MG3_4_115PL & MG3_4_116PL) +// End of MG3_4: +// Beginning of MG35: +#if (G3_1PL >= G3_5PL) || (G3_1PL == 0) +#define MG3_5_11PL ~(1 << 0) +#else +#define MG3_5_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_5PL) || (G3_2PL == 0) +#define MG3_5_12PL ~(1 << 1) +#else +#define MG3_5_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_5PL) || (G3_3PL == 0) +#define MG3_5_13PL ~(1 << 2) +#else +#define MG3_5_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_5PL) || (G3_4PL == 0) +#define MG3_5_14PL ~(1 << 3) +#else +#define MG3_5_14PL 0xFFFF +#endif + +#if (G3_6PL >= G3_5PL) || (G3_6PL == 0) +#define MG3_5_16PL ~(1 << 5) +#else +#define MG3_5_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_5PL) || (G3_7PL == 0) +#define MG3_5_17PL ~(1 << 6) +#else +#define MG3_5_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_5PL) || (G3_8PL == 0) +#define MG3_5_18PL ~(1 << 7) +#else +#define MG3_5_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_5PL) || (G3_9PL == 0) +#define MG3_5_19PL ~(1 << 8) +#else +#define MG3_5_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_5PL) || (G3_10PL == 0) +#define MG3_5_110PL ~(1 << 9) +#else +#define MG3_5_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_5PL) || (G3_11PL == 0) +#define MG3_5_111PL ~(1 << 10) +#else +#define MG3_5_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_5PL) || (G3_12PL == 0) +#define MG3_5_112PL ~(1 << 11) +#else +#define MG3_5_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_5PL) || (G3_13PL == 0) +#define MG3_5_113PL ~(1 << 12) +#else +#define MG3_5_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_5PL) || (G3_14PL == 0) +#define MG3_5_114PL ~(1 << 13) +#else +#define MG3_5_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_5PL) || (G3_15PL == 0) +#define MG3_5_115PL ~(1 << 14) +#else +#define MG3_5_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_5PL) || (G3_16PL == 0) +#define MG3_5_116PL ~(1 << 15) +#else +#define MG3_5_116PL 0xFFFF +#endif + +#define MG3_5_15PL 0xFFEF +#define MG3_5 (MG3_5_11PL & MG3_5_12PL & MG3_5_13PL & MG3_5_14PL & \ + MG3_5_15PL & MG3_5_16PL & MG3_5_17PL & MG3_5_18PL & \ + MG3_5_19PL & MG3_5_110PL & MG3_5_111PL & MG3_5_112PL & \ + MG3_5_113PL & MG3_5_114PL & MG3_5_115PL & MG3_5_116PL) +// End of MG3_5: +// Beginning of MG36: +#if (G3_1PL >= G3_6PL) || (G3_1PL == 0) +#define MG3_6_11PL ~(1 << 0) +#else +#define MG3_6_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_6PL) || (G3_2PL == 0) +#define MG3_6_12PL ~(1 << 1) +#else +#define MG3_6_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_6PL) || (G3_3PL == 0) +#define MG3_6_13PL ~(1 << 2) +#else +#define MG3_6_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_6PL) || (G3_4PL == 0) +#define MG3_6_14PL ~(1 << 3) +#else +#define MG3_6_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_6PL) || (G3_5PL == 0) +#define MG3_6_15PL ~(1 << 4) +#else +#define MG3_6_15PL 0xFFFF +#endif + +#if (G3_7PL >= G3_6PL) || (G3_7PL == 0) +#define MG3_6_17PL ~(1 << 6) +#else +#define MG3_6_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_6PL) || (G3_8PL == 0) +#define MG3_6_18PL ~(1 << 7) +#else +#define MG3_6_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_6PL) || (G3_9PL == 0) +#define MG3_6_19PL ~(1 << 8) +#else +#define MG3_6_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_6PL) || (G3_10PL == 0) +#define MG3_6_110PL ~(1 << 9) +#else +#define MG3_6_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_6PL) || (G3_11PL == 0) +#define MG3_6_111PL ~(1 << 10) +#else +#define MG3_6_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_6PL) || (G3_12PL == 0) +#define MG3_6_112PL ~(1 << 11) +#else +#define MG3_6_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_6PL) || (G3_13PL == 0) +#define MG3_6_113PL ~(1 << 12) +#else +#define MG3_6_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_6PL) || (G3_14PL == 0) +#define MG3_6_114PL ~(1 << 13) +#else +#define MG3_6_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_6PL) || (G3_15PL == 0) +#define MG3_6_115PL ~(1 << 14) +#else +#define MG3_6_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_6PL) || (G3_16PL == 0) +#define MG3_6_116PL ~(1 << 15) +#else +#define MG3_6_116PL 0xFFFF +#endif + +#define MG3_6_16PL 0xFFDF +#define MG3_6 (MG3_6_11PL & MG3_6_12PL & MG3_6_13PL & MG3_6_14PL & \ + MG3_6_15PL & MG3_6_16PL & MG3_6_17PL & MG3_6_18PL & \ + MG3_6_19PL & MG3_6_110PL & MG3_6_111PL & MG3_6_112PL & \ + MG3_6_113PL & MG3_6_114PL & MG3_6_115PL & MG3_6_116PL) +// End of MG3_6: +// Beginning of MG37: +#if (G3_1PL >= G3_7PL) || (G3_1PL == 0) +#define MG3_7_11PL ~(1 << 0) +#else +#define MG3_7_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_7PL) || (G3_2PL == 0) +#define MG3_7_12PL ~(1 << 1) +#else +#define MG3_7_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_7PL) || (G3_3PL == 0) +#define MG3_7_13PL ~(1 << 2) +#else +#define MG3_7_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_7PL) || (G3_4PL == 0) +#define MG3_7_14PL ~(1 << 3) +#else +#define MG3_7_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_7PL) || (G3_5PL == 0) +#define MG3_7_15PL ~(1 << 4) +#else +#define MG3_7_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_7PL) || (G3_6PL == 0) +#define MG3_7_16PL ~(1 << 5) +#else +#define MG3_7_16PL 0xFFFF +#endif + +#if (G3_8PL >= G3_7PL) || (G3_8PL == 0) +#define MG3_7_18PL ~(1 << 7) +#else +#define MG3_7_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_7PL) || (G3_9PL == 0) +#define MG3_7_19PL ~(1 << 8) +#else +#define MG3_7_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_7PL) || (G3_10PL == 0) +#define MG3_7_110PL ~(1 << 9) +#else +#define MG3_7_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_7PL) || (G3_11PL == 0) +#define MG3_7_111PL ~(1 << 10) +#else +#define MG3_7_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_7PL) || (G3_12PL == 0) +#define MG3_7_112PL ~(1 << 11) +#else +#define MG3_7_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_7PL) || (G3_13PL == 0) +#define MG3_7_113PL ~(1 << 12) +#else +#define MG3_7_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_7PL) || (G3_14PL == 0) +#define MG3_7_114PL ~(1 << 13) +#else +#define MG3_7_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_7PL) || (G3_15PL == 0) +#define MG3_7_115PL ~(1 << 14) +#else +#define MG3_7_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_7PL) || (G3_16PL == 0) +#define MG3_7_116PL ~(1 << 15) +#else +#define MG3_7_116PL 0xFFFF +#endif + +#define MG3_7_17PL 0xFFBF +#define MG3_7 (MG3_7_11PL & MG3_7_12PL & MG3_7_13PL & MG3_7_14PL & \ + MG3_7_15PL & MG3_7_16PL & MG3_7_17PL & MG3_7_18PL & \ + MG3_7_19PL & MG3_7_110PL & MG3_7_111PL & MG3_7_112PL & \ + MG3_7_113PL & MG3_7_114PL & MG3_7_115PL & MG3_7_116PL) +// End of MG3_7: +// Beginning of MG38: +#if (G3_1PL >= G3_8PL) || (G3_1PL == 0) +#define MG3_8_11PL ~(1 << 0) +#else +#define MG3_8_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_8PL) || (G3_2PL == 0) +#define MG3_8_12PL ~(1 << 1) +#else +#define MG3_8_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_8PL) || (G3_3PL == 0) +#define MG3_8_13PL ~(1 << 2) +#else +#define MG3_8_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_8PL) || (G3_4PL == 0) +#define MG3_8_14PL ~(1 << 3) +#else +#define MG3_8_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_8PL) || (G3_5PL == 0) +#define MG3_8_15PL ~(1 << 4) +#else +#define MG3_8_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_8PL) || (G3_6PL == 0) +#define MG3_8_16PL ~(1 << 5) +#else +#define MG3_8_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_8PL) || (G3_7PL == 0) +#define MG3_8_17PL ~(1 << 6) +#else +#define MG3_8_17PL 0xFFFF +#endif + +#if (G3_9PL >= G3_8PL) || (G3_9PL == 0) +#define MG3_8_19PL ~(1 << 8) +#else +#define MG3_8_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_8PL) || (G3_10PL == 0) +#define MG3_8_110PL ~(1 << 9) +#else +#define MG3_8_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_8PL) || (G3_11PL == 0) +#define MG3_8_111PL ~(1 << 10) +#else +#define MG3_8_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_8PL) || (G3_12PL == 0) +#define MG3_8_112PL ~(1 << 11) +#else +#define MG3_8_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_8PL) || (G3_13PL == 0) +#define MG3_8_113PL ~(1 << 12) +#else +#define MG3_8_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_8PL) || (G3_14PL == 0) +#define MG3_8_114PL ~(1 << 13) +#else +#define MG3_8_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_8PL) || (G3_15PL == 0) +#define MG3_8_115PL ~(1 << 14) +#else +#define MG3_8_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_8PL) || (G3_16PL == 0) +#define MG3_8_116PL ~(1 << 15) +#else +#define MG3_8_116PL 0xFFFF +#endif + +#define MG3_8_18PL 0xFF7F +#define MG3_8 (MG3_8_11PL & MG3_8_12PL & MG3_8_13PL & MG3_8_14PL & \ + MG3_8_15PL & MG3_8_16PL & MG3_8_17PL & MG3_8_18PL & \ + MG3_8_19PL & MG3_8_110PL & MG3_8_111PL & MG3_8_112PL & \ + MG3_8_113PL & MG3_8_114PL & MG3_8_115PL & MG3_8_116PL) +// End of MG3_8: +// Beginning of MG39: +#if (G3_1PL >= G3_9PL) || (G3_1PL == 0) +#define MG3_9_11PL ~(1 << 0) +#else +#define MG3_9_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_9PL) || (G3_2PL == 0) +#define MG3_9_12PL ~(1 << 1) +#else +#define MG3_9_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_9PL) || (G3_3PL == 0) +#define MG3_9_13PL ~(1 << 2) +#else +#define MG3_9_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_9PL) || (G3_4PL == 0) +#define MG3_9_14PL ~(1 << 3) +#else +#define MG3_9_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_9PL) || (G3_5PL == 0) +#define MG3_9_15PL ~(1 << 4) +#else +#define MG3_9_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_9PL) || (G3_6PL == 0) +#define MG3_9_16PL ~(1 << 5) +#else +#define MG3_9_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_9PL) || (G3_7PL == 0) +#define MG3_9_17PL ~(1 << 6) +#else +#define MG3_9_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_9PL) || (G3_8PL == 0) +#define MG3_9_18PL ~(1 << 7) +#else +#define MG3_9_18PL 0xFFFF +#endif + +#if (G3_10PL >= G3_9PL) || (G3_10PL == 0) +#define MG3_9_110PL ~(1 << 9) +#else +#define MG3_9_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_9PL) || (G3_11PL == 0) +#define MG3_9_111PL ~(1 << 10) +#else +#define MG3_9_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_9PL) || (G3_12PL == 0) +#define MG3_9_112PL ~(1 << 11) +#else +#define MG3_9_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_9PL) || (G3_13PL == 0) +#define MG3_9_113PL ~(1 << 12) +#else +#define MG3_9_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_9PL) || (G3_14PL == 0) +#define MG3_9_114PL ~(1 << 13) +#else +#define MG3_9_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_9PL) || (G3_15PL == 0) +#define MG3_9_115PL ~(1 << 14) +#else +#define MG3_9_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_9PL) || (G3_16PL == 0) +#define MG3_9_116PL ~(1 << 15) +#else +#define MG3_9_116PL 0xFFFF +#endif + +#define MG3_9_19PL 0xFEFF +#define MG3_9 (MG3_9_11PL & MG3_9_12PL & MG3_9_13PL & MG3_9_14PL & \ + MG3_9_15PL & MG3_9_16PL & MG3_9_17PL & MG3_9_18PL & \ + MG3_9_19PL & MG3_9_110PL & MG3_9_111PL & MG3_9_112PL & \ + MG3_9_113PL & MG3_9_114PL & MG3_9_115PL & MG3_9_116PL) +// End of MG3_9: +// Beginning of MG310: +#if (G3_1PL >= G3_10PL) || (G3_1PL == 0) +#define MG3_10_11PL ~(1 << 0) +#else +#define MG3_10_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_10PL) || (G3_2PL == 0) +#define MG3_10_12PL ~(1 << 1) +#else +#define MG3_10_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_10PL) || (G3_3PL == 0) +#define MG3_10_13PL ~(1 << 2) +#else +#define MG3_10_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_10PL) || (G3_4PL == 0) +#define MG3_10_14PL ~(1 << 3) +#else +#define MG3_10_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_10PL) || (G3_5PL == 0) +#define MG3_10_15PL ~(1 << 4) +#else +#define MG3_10_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_10PL) || (G3_6PL == 0) +#define MG3_10_16PL ~(1 << 5) +#else +#define MG3_10_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_10PL) || (G3_7PL == 0) +#define MG3_10_17PL ~(1 << 6) +#else +#define MG3_10_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_10PL) || (G3_8PL == 0) +#define MG3_10_18PL ~(1 << 7) +#else +#define MG3_10_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_10PL) || (G3_9PL == 0) +#define MG3_10_19PL ~(1 << 8) +#else +#define MG3_10_19PL 0xFFFF +#endif + +#if (G3_11PL >= G3_10PL) || (G3_11PL == 0) +#define MG3_10_111PL ~(1 << 10) +#else +#define MG3_10_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_10PL) || (G3_12PL == 0) +#define MG3_10_112PL ~(1 << 11) +#else +#define MG3_10_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_10PL) || (G3_13PL == 0) +#define MG3_10_113PL ~(1 << 12) +#else +#define MG3_10_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_10PL) || (G3_14PL == 0) +#define MG3_10_114PL ~(1 << 13) +#else +#define MG3_10_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_10PL) || (G3_15PL == 0) +#define MG3_10_115PL ~(1 << 14) +#else +#define MG3_10_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_10PL) || (G3_16PL == 0) +#define MG3_10_116PL ~(1 << 15) +#else +#define MG3_10_116PL 0xFFFF +#endif + +#define MG3_10_110PL 0xFDFF +#define MG3_10 (MG3_10_11PL & MG3_10_12PL & MG3_10_13PL & MG3_10_14PL & \ + MG3_10_15PL & MG3_10_16PL & MG3_10_17PL & MG3_10_18PL & \ + MG3_10_19PL & MG3_10_110PL & MG3_10_111PL & MG3_10_112PL & \ + MG3_10_113PL & MG3_10_114PL & MG3_10_115PL & MG3_10_116PL) +// End of MG3_10: +// Beginning of MG311: +#if (G3_1PL >= G3_11PL) || (G3_1PL == 0) +#define MG3_11_11PL ~(1 << 0) +#else +#define MG3_11_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_11PL) || (G3_2PL == 0) +#define MG3_11_12PL ~(1 << 1) +#else +#define MG3_11_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_11PL) || (G3_3PL == 0) +#define MG3_11_13PL ~(1 << 2) +#else +#define MG3_11_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_11PL) || (G3_4PL == 0) +#define MG3_11_14PL ~(1 << 3) +#else +#define MG3_11_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_11PL) || (G3_5PL == 0) +#define MG3_11_15PL ~(1 << 4) +#else +#define MG3_11_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_11PL) || (G3_6PL == 0) +#define MG3_11_16PL ~(1 << 5) +#else +#define MG3_11_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_11PL) || (G3_7PL == 0) +#define MG3_11_17PL ~(1 << 6) +#else +#define MG3_11_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_11PL) || (G3_8PL == 0) +#define MG3_11_18PL ~(1 << 7) +#else +#define MG3_11_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_11PL) || (G3_9PL == 0) +#define MG3_11_19PL ~(1 << 8) +#else +#define MG3_11_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_11PL) || (G3_10PL == 0) +#define MG3_11_110PL ~(1 << 9) +#else +#define MG3_11_110PL 0xFFFF +#endif + +#if (G3_12PL >= G3_11PL) || (G3_12PL == 0) +#define MG3_11_112PL ~(1 << 11) +#else +#define MG3_11_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_11PL) || (G3_13PL == 0) +#define MG3_11_113PL ~(1 << 12) +#else +#define MG3_11_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_11PL) || (G3_14PL == 0) +#define MG3_11_114PL ~(1 << 13) +#else +#define MG3_11_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_11PL) || (G3_15PL == 0) +#define MG3_11_115PL ~(1 << 14) +#else +#define MG3_11_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_11PL) || (G3_16PL == 0) +#define MG3_11_116PL ~(1 << 15) +#else +#define MG3_11_116PL 0xFFFF +#endif + +#define MG3_11_111PL 0xFBFF +#define MG3_11 (MG3_11_11PL & MG3_11_12PL & MG3_11_13PL & MG3_11_14PL & \ + MG3_11_15PL & MG3_11_16PL & MG3_11_17PL & MG3_11_18PL & \ + MG3_11_19PL & MG3_11_110PL & MG3_11_111PL & MG3_11_112PL & \ + MG3_11_113PL & MG3_11_114PL & MG3_11_115PL & MG3_11_116PL) +// End of MG3_11: +// Beginning of MG312: +#if (G3_1PL >= G3_12PL) || (G3_1PL == 0) +#define MG3_12_11PL ~(1 << 0) +#else +#define MG3_12_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_12PL) || (G3_2PL == 0) +#define MG3_12_12PL ~(1 << 1) +#else +#define MG3_12_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_12PL) || (G3_3PL == 0) +#define MG3_12_13PL ~(1 << 2) +#else +#define MG3_12_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_12PL) || (G3_4PL == 0) +#define MG3_12_14PL ~(1 << 3) +#else +#define MG3_12_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_12PL) || (G3_5PL == 0) +#define MG3_12_15PL ~(1 << 4) +#else +#define MG3_12_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_12PL) || (G3_6PL == 0) +#define MG3_12_16PL ~(1 << 5) +#else +#define MG3_12_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_12PL) || (G3_7PL == 0) +#define MG3_12_17PL ~(1 << 6) +#else +#define MG3_12_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_12PL) || (G3_8PL == 0) +#define MG3_12_18PL ~(1 << 7) +#else +#define MG3_12_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_12PL) || (G3_9PL == 0) +#define MG3_12_19PL ~(1 << 8) +#else +#define MG3_12_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_12PL) || (G3_10PL == 0) +#define MG3_12_110PL ~(1 << 9) +#else +#define MG3_12_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_12PL) || (G3_11PL == 0) +#define MG3_12_111PL ~(1 << 10) +#else +#define MG3_12_111PL 0xFFFF +#endif + +#if (G3_13PL >= G3_12PL) || (G3_13PL == 0) +#define MG3_12_113PL ~(1 << 12) +#else +#define MG3_12_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_12PL) || (G3_14PL == 0) +#define MG3_12_114PL ~(1 << 13) +#else +#define MG3_12_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_12PL) || (G3_15PL == 0) +#define MG3_12_115PL ~(1 << 14) +#else +#define MG3_12_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_12PL) || (G3_16PL == 0) +#define MG3_12_116PL ~(1 << 15) +#else +#define MG3_12_116PL 0xFFFF +#endif + +#define MG3_12_112PL 0xF7FF +#define MG3_12 (MG3_12_11PL & MG3_12_12PL & MG3_12_13PL & MG3_12_14PL & \ + MG3_12_15PL & MG3_12_16PL & MG3_12_17PL & MG3_12_18PL & \ + MG3_12_19PL & MG3_12_110PL & MG3_12_111PL & MG3_12_112PL & \ + MG3_12_113PL & MG3_12_114PL & MG3_12_115PL & MG3_12_116PL) +// End of MG3_12: +// Beginning of MG313: +#if (G3_1PL >= G3_13PL) || (G3_1PL == 0) +#define MG3_13_11PL ~(1 << 0) +#else +#define MG3_13_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_13PL) || (G3_2PL == 0) +#define MG3_13_12PL ~(1 << 1) +#else +#define MG3_13_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_13PL) || (G3_3PL == 0) +#define MG3_13_13PL ~(1 << 2) +#else +#define MG3_13_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_13PL) || (G3_4PL == 0) +#define MG3_13_14PL ~(1 << 3) +#else +#define MG3_13_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_13PL) || (G3_5PL == 0) +#define MG3_13_15PL ~(1 << 4) +#else +#define MG3_13_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_13PL) || (G3_6PL == 0) +#define MG3_13_16PL ~(1 << 5) +#else +#define MG3_13_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_13PL) || (G3_7PL == 0) +#define MG3_13_17PL ~(1 << 6) +#else +#define MG3_13_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_13PL) || (G3_8PL == 0) +#define MG3_13_18PL ~(1 << 7) +#else +#define MG3_13_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_13PL) || (G3_9PL == 0) +#define MG3_13_19PL ~(1 << 8) +#else +#define MG3_13_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_13PL) || (G3_10PL == 0) +#define MG3_13_110PL ~(1 << 9) +#else +#define MG3_13_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_13PL) || (G3_11PL == 0) +#define MG3_13_111PL ~(1 << 10) +#else +#define MG3_13_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_13PL) || (G3_12PL == 0) +#define MG3_13_112PL ~(1 << 11) +#else +#define MG3_13_112PL 0xFFFF +#endif + +#if (G3_14PL >= G3_13PL) || (G3_14PL == 0) +#define MG3_13_114PL ~(1 << 13) +#else +#define MG3_13_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_13PL) || (G3_15PL == 0) +#define MG3_13_115PL ~(1 << 14) +#else +#define MG3_13_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_13PL) || (G3_16PL == 0) +#define MG3_13_116PL ~(1 << 15) +#else +#define MG3_13_116PL 0xFFFF +#endif + +#define MG3_13_113PL 0xEFFF +#define MG3_13 (MG3_13_11PL & MG3_13_12PL & MG3_13_13PL & MG3_13_14PL & \ + MG3_13_15PL & MG3_13_16PL & MG3_13_17PL & MG3_13_18PL & \ + MG3_13_19PL & MG3_13_110PL & MG3_13_111PL & MG3_13_112PL & \ + MG3_13_113PL & MG3_13_114PL & MG3_13_115PL & MG3_13_116PL) +// End of MG3_13: +// Beginning of MG314: +#if (G3_1PL >= G3_14PL) || (G3_1PL == 0) +#define MG3_14_11PL ~(1 << 0) +#else +#define MG3_14_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_14PL) || (G3_2PL == 0) +#define MG3_14_12PL ~(1 << 1) +#else +#define MG3_14_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_14PL) || (G3_3PL == 0) +#define MG3_14_13PL ~(1 << 2) +#else +#define MG3_14_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_14PL) || (G3_4PL == 0) +#define MG3_14_14PL ~(1 << 3) +#else +#define MG3_14_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_14PL) || (G3_5PL == 0) +#define MG3_14_15PL ~(1 << 4) +#else +#define MG3_14_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_14PL) || (G3_6PL == 0) +#define MG3_14_16PL ~(1 << 5) +#else +#define MG3_14_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_14PL) || (G3_7PL == 0) +#define MG3_14_17PL ~(1 << 6) +#else +#define MG3_14_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_14PL) || (G3_8PL == 0) +#define MG3_14_18PL ~(1 << 7) +#else +#define MG3_14_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_14PL) || (G3_9PL == 0) +#define MG3_14_19PL ~(1 << 8) +#else +#define MG3_14_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_14PL) || (G3_10PL == 0) +#define MG3_14_110PL ~(1 << 9) +#else +#define MG3_14_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_14PL) || (G3_11PL == 0) +#define MG3_14_111PL ~(1 << 10) +#else +#define MG3_14_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_14PL) || (G3_12PL == 0) +#define MG3_14_112PL ~(1 << 11) +#else +#define MG3_14_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_14PL) || (G3_13PL == 0) +#define MG3_14_113PL ~(1 << 12) +#else +#define MG3_14_113PL 0xFFFF +#endif + +#if (G3_15PL >= G3_14PL) || (G3_15PL == 0) +#define MG3_14_115PL ~(1 << 14) +#else +#define MG3_14_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_14PL) || (G3_16PL == 0) +#define MG3_14_116PL ~(1 << 15) +#else +#define MG3_14_116PL 0xFFFF +#endif + +#define MG3_14_114PL 0xDFFF +#define MG3_14 (MG3_14_11PL & MG3_14_12PL & MG3_14_13PL & MG3_14_14PL & \ + MG3_14_15PL & MG3_14_16PL & MG3_14_17PL & MG3_14_18PL & \ + MG3_14_19PL & MG3_14_110PL & MG3_14_111PL & MG3_14_112PL & \ + MG3_14_113PL & MG3_14_114PL & MG3_14_115PL & MG3_14_116PL) +// End of MG3_14: +// Beginning of MG315: +#if (G3_1PL >= G3_15PL) || (G3_1PL == 0) +#define MG3_15_11PL ~(1 << 0) +#else +#define MG3_15_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_15PL) || (G3_2PL == 0) +#define MG3_15_12PL ~(1 << 1) +#else +#define MG3_15_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_15PL) || (G3_3PL == 0) +#define MG3_15_13PL ~(1 << 2) +#else +#define MG3_15_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_15PL) || (G3_4PL == 0) +#define MG3_15_14PL ~(1 << 3) +#else +#define MG3_15_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_15PL) || (G3_5PL == 0) +#define MG3_15_15PL ~(1 << 4) +#else +#define MG3_15_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_15PL) || (G3_6PL == 0) +#define MG3_15_16PL ~(1 << 5) +#else +#define MG3_15_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_15PL) || (G3_7PL == 0) +#define MG3_15_17PL ~(1 << 6) +#else +#define MG3_15_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_15PL) || (G3_8PL == 0) +#define MG3_15_18PL ~(1 << 7) +#else +#define MG3_15_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_15PL) || (G3_9PL == 0) +#define MG3_15_19PL ~(1 << 8) +#else +#define MG3_15_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_15PL) || (G3_10PL == 0) +#define MG3_15_110PL ~(1 << 9) +#else +#define MG3_15_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_15PL) || (G3_11PL == 0) +#define MG3_15_111PL ~(1 << 10) +#else +#define MG3_15_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_15PL) || (G3_12PL == 0) +#define MG3_15_112PL ~(1 << 11) +#else +#define MG3_15_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_15PL) || (G3_13PL == 0) +#define MG3_15_113PL ~(1 << 12) +#else +#define MG3_15_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_15PL) || (G3_14PL == 0) +#define MG3_15_114PL ~(1 << 13) +#else +#define MG3_15_114PL 0xFFFF +#endif + +#if (G3_16PL >= G3_15PL) || (G3_16PL == 0) +#define MG3_15_116PL ~(1 << 15) +#else +#define MG3_15_116PL 0xFFFF +#endif + +#define MG3_15_115PL 0xBFFF +#define MG3_15 (MG3_15_11PL & MG3_15_12PL & MG3_15_13PL & MG3_15_14PL & \ + MG3_15_15PL & MG3_15_16PL & MG3_15_17PL & MG3_15_18PL & \ + MG3_15_19PL & MG3_15_110PL & MG3_15_111PL & MG3_15_112PL & \ + MG3_15_113PL & MG3_15_114PL & MG3_15_115PL & MG3_15_116PL) +// End of MG3_15: +// Beginning of MG316: +#if (G3_1PL >= G3_16PL) || (G3_1PL == 0) +#define MG3_16_11PL ~(1 << 0) +#else +#define MG3_16_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_16PL) || (G3_2PL == 0) +#define MG3_16_12PL ~(1 << 1) +#else +#define MG3_16_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_16PL) || (G3_3PL == 0) +#define MG3_16_13PL ~(1 << 2) +#else +#define MG3_16_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_16PL) || (G3_4PL == 0) +#define MG3_16_14PL ~(1 << 3) +#else +#define MG3_16_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_16PL) || (G3_5PL == 0) +#define MG3_16_15PL ~(1 << 4) +#else +#define MG3_16_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_16PL) || (G3_6PL == 0) +#define MG3_16_16PL ~(1 << 5) +#else +#define MG3_16_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_16PL) || (G3_7PL == 0) +#define MG3_16_17PL ~(1 << 6) +#else +#define MG3_16_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_16PL) || (G3_8PL == 0) +#define MG3_16_18PL ~(1 << 7) +#else +#define MG3_16_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_16PL) || (G3_9PL == 0) +#define MG3_16_19PL ~(1 << 8) +#else +#define MG3_16_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_16PL) || (G3_10PL == 0) +#define MG3_16_110PL ~(1 << 9) +#else +#define MG3_16_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_16PL) || (G3_11PL == 0) +#define MG3_16_111PL ~(1 << 10) +#else +#define MG3_16_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_16PL) || (G3_12PL == 0) +#define MG3_16_112PL ~(1 << 11) +#else +#define MG3_16_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_16PL) || (G3_13PL == 0) +#define MG3_16_113PL ~(1 << 12) +#else +#define MG3_16_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_16PL) || (G3_14PL == 0) +#define MG3_16_114PL ~(1 << 13) +#else +#define MG3_16_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_16PL) || (G3_15PL == 0) +#define MG3_16_115PL ~(1 << 14) +#else +#define MG3_16_115PL 0xFFFF +#endif + +#define MG3_16_116PL 0x7FFF +#define MG3_16 (MG3_16_11PL & MG3_16_12PL & MG3_16_13PL & MG3_16_14PL & \ + MG3_16_15PL & MG3_16_16PL & MG3_16_17PL & MG3_16_18PL & \ + MG3_16_19PL & MG3_16_110PL & MG3_16_111PL & MG3_16_112PL & \ + MG3_16_113PL & MG3_16_114PL & MG3_16_115PL & MG3_16_116PL) +// End of MG3_16: + + +// +// Automatically generate PIEIER4 interrupt masks MG41 to MG416: +// + +// Beginning of MG41: +#if (G4_2PL >= G4_1PL) || (G4_2PL == 0) +#define MG4_1_12PL ~(1 << 1) +#else +#define MG4_1_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_1PL) || (G4_3PL == 0) +#define MG4_1_13PL ~(1 << 2) +#else +#define MG4_1_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_1PL) || (G4_4PL == 0) +#define MG4_1_14PL ~(1 << 3) +#else +#define MG4_1_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_1PL) || (G4_5PL == 0) +#define MG4_1_15PL ~(1 << 4) +#else +#define MG4_1_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_1PL) || (G4_6PL == 0) +#define MG4_1_16PL ~(1 << 5) +#else +#define MG4_1_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_1PL) || (G4_7PL == 0) +#define MG4_1_17PL ~(1 << 6) +#else +#define MG4_1_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_1PL) || (G4_8PL == 0) +#define MG4_1_18PL ~(1 << 7) +#else +#define MG4_1_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_1PL) || (G4_9PL == 0) +#define MG4_1_19PL ~(1 << 8) +#else +#define MG4_1_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_1PL) || (G4_10PL == 0) +#define MG4_1_110PL ~(1 << 9) +#else +#define MG4_1_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_1PL) || (G4_11PL == 0) +#define MG4_1_111PL ~(1 << 10) +#else +#define MG4_1_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_1PL) || (G4_12PL == 0) +#define MG4_1_112PL ~(1 << 11) +#else +#define MG4_1_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_1PL) || (G4_13PL == 0) +#define MG4_1_113PL ~(1 << 12) +#else +#define MG4_1_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_1PL) || (G4_14PL == 0) +#define MG4_1_114PL ~(1 << 13) +#else +#define MG4_1_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_1PL) || (G4_15PL == 0) +#define MG4_1_115PL ~(1 << 14) +#else +#define MG4_1_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_1PL) || (G4_16PL == 0) +#define MG4_1_116PL ~(1 << 15) +#else +#define MG4_1_116PL 0xFFFF +#endif + +#define MG4_1_11PL 0xFFFE +#define MG4_1 (MG4_1_11PL & MG4_1_12PL & MG4_1_13PL & MG4_1_14PL & \ + MG4_1_15PL & MG4_1_16PL & MG4_1_17PL & MG4_1_18PL & \ + MG4_1_19PL & MG4_1_110PL & MG4_1_111PL & MG4_1_112PL & \ + MG4_1_113PL & MG4_1_114PL & MG4_1_115PL & MG4_1_116PL) +// End of MG4_1: +// Beginning of MG42: +#if (G4_1PL >= G4_2PL) || (G4_1PL == 0) +#define MG4_2_11PL ~(1 << 0) +#else +#define MG4_2_11PL 0xFFFF +#endif + +#if (G4_3PL >= G4_2PL) || (G4_3PL == 0) +#define MG4_2_13PL ~(1 << 2) +#else +#define MG4_2_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_2PL) || (G4_4PL == 0) +#define MG4_2_14PL ~(1 << 3) +#else +#define MG4_2_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_2PL) || (G4_5PL == 0) +#define MG4_2_15PL ~(1 << 4) +#else +#define MG4_2_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_2PL) || (G4_6PL == 0) +#define MG4_2_16PL ~(1 << 5) +#else +#define MG4_2_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_2PL) || (G4_7PL == 0) +#define MG4_2_17PL ~(1 << 6) +#else +#define MG4_2_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_2PL) || (G4_8PL == 0) +#define MG4_2_18PL ~(1 << 7) +#else +#define MG4_2_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_2PL) || (G4_9PL == 0) +#define MG4_2_19PL ~(1 << 8) +#else +#define MG4_2_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_2PL) || (G4_10PL == 0) +#define MG4_2_110PL ~(1 << 9) +#else +#define MG4_2_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_2PL) || (G4_11PL == 0) +#define MG4_2_111PL ~(1 << 10) +#else +#define MG4_2_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_2PL) || (G4_12PL == 0) +#define MG4_2_112PL ~(1 << 11) +#else +#define MG4_2_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_2PL) || (G4_13PL == 0) +#define MG4_2_113PL ~(1 << 12) +#else +#define MG4_2_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_2PL) || (G4_14PL == 0) +#define MG4_2_114PL ~(1 << 13) +#else +#define MG4_2_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_2PL) || (G4_15PL == 0) +#define MG4_2_115PL ~(1 << 14) +#else +#define MG4_2_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_2PL) || (G4_16PL == 0) +#define MG4_2_116PL ~(1 << 15) +#else +#define MG4_2_116PL 0xFFFF +#endif + +#define MG4_2_12PL 0xFFFD +#define MG4_2 (MG4_2_11PL & MG4_2_12PL & MG4_2_13PL & MG4_2_14PL & \ + MG4_2_15PL & MG4_2_16PL & MG4_2_17PL & MG4_2_18PL & \ + MG4_2_19PL & MG4_2_110PL & MG4_2_111PL & MG4_2_112PL & \ + MG4_2_113PL & MG4_2_114PL & MG4_2_115PL & MG4_2_116PL) +// End of MG4_2: +// Beginning of MG43: +#if (G4_1PL >= G4_3PL) || (G4_1PL == 0) +#define MG4_3_11PL ~(1 << 0) +#else +#define MG4_3_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_3PL) || (G4_2PL == 0) +#define MG4_3_12PL ~(1 << 1) +#else +#define MG4_3_12PL 0xFFFF +#endif + +#if (G4_4PL >= G4_3PL) || (G4_4PL == 0) +#define MG4_3_14PL ~(1 << 3) +#else +#define MG4_3_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_3PL) || (G4_5PL == 0) +#define MG4_3_15PL ~(1 << 4) +#else +#define MG4_3_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_3PL) || (G4_6PL == 0) +#define MG4_3_16PL ~(1 << 5) +#else +#define MG4_3_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_3PL) || (G4_7PL == 0) +#define MG4_3_17PL ~(1 << 6) +#else +#define MG4_3_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_3PL) || (G4_8PL == 0) +#define MG4_3_18PL ~(1 << 7) +#else +#define MG4_3_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_3PL) || (G4_9PL == 0) +#define MG4_3_19PL ~(1 << 8) +#else +#define MG4_3_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_3PL) || (G4_10PL == 0) +#define MG4_3_110PL ~(1 << 9) +#else +#define MG4_3_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_3PL) || (G4_11PL == 0) +#define MG4_3_111PL ~(1 << 10) +#else +#define MG4_3_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_3PL) || (G4_12PL == 0) +#define MG4_3_112PL ~(1 << 11) +#else +#define MG4_3_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_3PL) || (G4_13PL == 0) +#define MG4_3_113PL ~(1 << 12) +#else +#define MG4_3_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_3PL) || (G4_14PL == 0) +#define MG4_3_114PL ~(1 << 13) +#else +#define MG4_3_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_3PL) || (G4_15PL == 0) +#define MG4_3_115PL ~(1 << 14) +#else +#define MG4_3_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_3PL) || (G4_16PL == 0) +#define MG4_3_116PL ~(1 << 15) +#else +#define MG4_3_116PL 0xFFFF +#endif + +#define MG4_3_13PL 0xFFFB +#define MG4_3 (MG4_3_11PL & MG4_3_12PL & MG4_3_13PL & MG4_3_14PL & \ + MG4_3_15PL & MG4_3_16PL & MG4_3_17PL & MG4_3_18PL & \ + MG4_3_19PL & MG4_3_110PL & MG4_3_111PL & MG4_3_112PL & \ + MG4_3_113PL & MG4_3_114PL & MG4_3_115PL & MG4_3_116PL) +// End of MG4_3: +// Beginning of MG44: +#if (G4_1PL >= G4_4PL) || (G4_1PL == 0) +#define MG4_4_11PL ~(1 << 0) +#else +#define MG4_4_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_4PL) || (G4_2PL == 0) +#define MG4_4_12PL ~(1 << 1) +#else +#define MG4_4_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_4PL) || (G4_3PL == 0) +#define MG4_4_13PL ~(1 << 2) +#else +#define MG4_4_13PL 0xFFFF +#endif + +#if (G4_5PL >= G4_4PL) || (G4_5PL == 0) +#define MG4_4_15PL ~(1 << 4) +#else +#define MG4_4_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_4PL) || (G4_6PL == 0) +#define MG4_4_16PL ~(1 << 5) +#else +#define MG4_4_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_4PL) || (G4_7PL == 0) +#define MG4_4_17PL ~(1 << 6) +#else +#define MG4_4_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_4PL) || (G4_8PL == 0) +#define MG4_4_18PL ~(1 << 7) +#else +#define MG4_4_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_4PL) || (G4_9PL == 0) +#define MG4_4_19PL ~(1 << 8) +#else +#define MG4_4_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_4PL) || (G4_10PL == 0) +#define MG4_4_110PL ~(1 << 9) +#else +#define MG4_4_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_4PL) || (G4_11PL == 0) +#define MG4_4_111PL ~(1 << 10) +#else +#define MG4_4_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_4PL) || (G4_12PL == 0) +#define MG4_4_112PL ~(1 << 11) +#else +#define MG4_4_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_4PL) || (G4_13PL == 0) +#define MG4_4_113PL ~(1 << 12) +#else +#define MG4_4_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_4PL) || (G4_14PL == 0) +#define MG4_4_114PL ~(1 << 13) +#else +#define MG4_4_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_4PL) || (G4_15PL == 0) +#define MG4_4_115PL ~(1 << 14) +#else +#define MG4_4_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_4PL) || (G4_16PL == 0) +#define MG4_4_116PL ~(1 << 15) +#else +#define MG4_4_116PL 0xFFFF +#endif + +#define MG4_4_14PL 0xFFF7 +#define MG4_4 (MG4_4_11PL & MG4_4_12PL & MG4_4_13PL & MG4_4_14PL & \ + MG4_4_15PL & MG4_4_16PL & MG4_4_17PL & MG4_4_18PL & \ + MG4_4_19PL & MG4_4_110PL & MG4_4_111PL & MG4_4_112PL & \ + MG4_4_113PL & MG4_4_114PL & MG4_4_115PL & MG4_4_116PL) +// End of MG4_4: +// Beginning of MG45: +#if (G4_1PL >= G4_5PL) || (G4_1PL == 0) +#define MG4_5_11PL ~(1 << 0) +#else +#define MG4_5_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_5PL) || (G4_2PL == 0) +#define MG4_5_12PL ~(1 << 1) +#else +#define MG4_5_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_5PL) || (G4_3PL == 0) +#define MG4_5_13PL ~(1 << 2) +#else +#define MG4_5_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_5PL) || (G4_4PL == 0) +#define MG4_5_14PL ~(1 << 3) +#else +#define MG4_5_14PL 0xFFFF +#endif + +#if (G4_6PL >= G4_5PL) || (G4_6PL == 0) +#define MG4_5_16PL ~(1 << 5) +#else +#define MG4_5_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_5PL) || (G4_7PL == 0) +#define MG4_5_17PL ~(1 << 6) +#else +#define MG4_5_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_5PL) || (G4_8PL == 0) +#define MG4_5_18PL ~(1 << 7) +#else +#define MG4_5_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_5PL) || (G4_9PL == 0) +#define MG4_5_19PL ~(1 << 8) +#else +#define MG4_5_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_5PL) || (G4_10PL == 0) +#define MG4_5_110PL ~(1 << 9) +#else +#define MG4_5_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_5PL) || (G4_11PL == 0) +#define MG4_5_111PL ~(1 << 10) +#else +#define MG4_5_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_5PL) || (G4_12PL == 0) +#define MG4_5_112PL ~(1 << 11) +#else +#define MG4_5_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_5PL) || (G4_13PL == 0) +#define MG4_5_113PL ~(1 << 12) +#else +#define MG4_5_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_5PL) || (G4_14PL == 0) +#define MG4_5_114PL ~(1 << 13) +#else +#define MG4_5_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_5PL) || (G4_15PL == 0) +#define MG4_5_115PL ~(1 << 14) +#else +#define MG4_5_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_5PL) || (G4_16PL == 0) +#define MG4_5_116PL ~(1 << 15) +#else +#define MG4_5_116PL 0xFFFF +#endif + +#define MG4_5_15PL 0xFFEF +#define MG4_5 (MG4_5_11PL & MG4_5_12PL & MG4_5_13PL & MG4_5_14PL & \ + MG4_5_15PL & MG4_5_16PL & MG4_5_17PL & MG4_5_18PL & \ + MG4_5_19PL & MG4_5_110PL & MG4_5_111PL & MG4_5_112PL & \ + MG4_5_113PL & MG4_5_114PL & MG4_5_115PL & MG4_5_116PL) +// End of MG4_5: +// Beginning of MG46: +#if (G4_1PL >= G4_6PL) || (G4_1PL == 0) +#define MG4_6_11PL ~(1 << 0) +#else +#define MG4_6_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_6PL) || (G4_2PL == 0) +#define MG4_6_12PL ~(1 << 1) +#else +#define MG4_6_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_6PL) || (G4_3PL == 0) +#define MG4_6_13PL ~(1 << 2) +#else +#define MG4_6_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_6PL) || (G4_4PL == 0) +#define MG4_6_14PL ~(1 << 3) +#else +#define MG4_6_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_6PL) || (G4_5PL == 0) +#define MG4_6_15PL ~(1 << 4) +#else +#define MG4_6_15PL 0xFFFF +#endif + +#if (G4_7PL >= G4_6PL) || (G4_7PL == 0) +#define MG4_6_17PL ~(1 << 6) +#else +#define MG4_6_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_6PL) || (G4_8PL == 0) +#define MG4_6_18PL ~(1 << 7) +#else +#define MG4_6_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_6PL) || (G4_9PL == 0) +#define MG4_6_19PL ~(1 << 8) +#else +#define MG4_6_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_6PL) || (G4_10PL == 0) +#define MG4_6_110PL ~(1 << 9) +#else +#define MG4_6_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_6PL) || (G4_11PL == 0) +#define MG4_6_111PL ~(1 << 10) +#else +#define MG4_6_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_6PL) || (G4_12PL == 0) +#define MG4_6_112PL ~(1 << 11) +#else +#define MG4_6_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_6PL) || (G4_13PL == 0) +#define MG4_6_113PL ~(1 << 12) +#else +#define MG4_6_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_6PL) || (G4_14PL == 0) +#define MG4_6_114PL ~(1 << 13) +#else +#define MG4_6_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_6PL) || (G4_15PL == 0) +#define MG4_6_115PL ~(1 << 14) +#else +#define MG4_6_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_6PL) || (G4_16PL == 0) +#define MG4_6_116PL ~(1 << 15) +#else +#define MG4_6_116PL 0xFFFF +#endif + +#define MG4_6_16PL 0xFFDF +#define MG4_6 (MG4_6_11PL & MG4_6_12PL & MG4_6_13PL & MG4_6_14PL & \ + MG4_6_15PL & MG4_6_16PL & MG4_6_17PL & MG4_6_18PL & \ + MG4_6_19PL & MG4_6_110PL & MG4_6_111PL & MG4_6_112PL & \ + MG4_6_113PL & MG4_6_114PL & MG4_6_115PL & MG4_6_116PL) +// End of MG4_6: +// Beginning of MG47: +#if (G4_1PL >= G4_7PL) || (G4_1PL == 0) +#define MG4_7_11PL ~(1 << 0) +#else +#define MG4_7_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_7PL) || (G4_2PL == 0) +#define MG4_7_12PL ~(1 << 1) +#else +#define MG4_7_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_7PL) || (G4_3PL == 0) +#define MG4_7_13PL ~(1 << 2) +#else +#define MG4_7_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_7PL) || (G4_4PL == 0) +#define MG4_7_14PL ~(1 << 3) +#else +#define MG4_7_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_7PL) || (G4_5PL == 0) +#define MG4_7_15PL ~(1 << 4) +#else +#define MG4_7_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_7PL) || (G4_6PL == 0) +#define MG4_7_16PL ~(1 << 5) +#else +#define MG4_7_16PL 0xFFFF +#endif + +#if (G4_8PL >= G4_7PL) || (G4_8PL == 0) +#define MG4_7_18PL ~(1 << 7) +#else +#define MG4_7_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_7PL) || (G4_9PL == 0) +#define MG4_7_19PL ~(1 << 8) +#else +#define MG4_7_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_7PL) || (G4_10PL == 0) +#define MG4_7_110PL ~(1 << 9) +#else +#define MG4_7_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_7PL) || (G4_11PL == 0) +#define MG4_7_111PL ~(1 << 10) +#else +#define MG4_7_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_7PL) || (G4_12PL == 0) +#define MG4_7_112PL ~(1 << 11) +#else +#define MG4_7_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_7PL) || (G4_13PL == 0) +#define MG4_7_113PL ~(1 << 12) +#else +#define MG4_7_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_7PL) || (G4_14PL == 0) +#define MG4_7_114PL ~(1 << 13) +#else +#define MG4_7_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_7PL) || (G4_15PL == 0) +#define MG4_7_115PL ~(1 << 14) +#else +#define MG4_7_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_7PL) || (G4_16PL == 0) +#define MG4_7_116PL ~(1 << 15) +#else +#define MG4_7_116PL 0xFFFF +#endif + +#define MG4_7_17PL 0xFFBF +#define MG4_7 (MG4_7_11PL & MG4_7_12PL & MG4_7_13PL & MG4_7_14PL & \ + MG4_7_15PL & MG4_7_16PL & MG4_7_17PL & MG4_7_18PL & \ + MG4_7_19PL & MG4_7_110PL & MG4_7_111PL & MG4_7_112PL & \ + MG4_7_113PL & MG4_7_114PL & MG4_7_115PL & MG4_7_116PL) +// End of MG4_7: +// Beginning of MG48: +#if (G4_1PL >= G4_8PL) || (G4_1PL == 0) +#define MG4_8_11PL ~(1 << 0) +#else +#define MG4_8_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_8PL) || (G4_2PL == 0) +#define MG4_8_12PL ~(1 << 1) +#else +#define MG4_8_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_8PL) || (G4_3PL == 0) +#define MG4_8_13PL ~(1 << 2) +#else +#define MG4_8_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_8PL) || (G4_4PL == 0) +#define MG4_8_14PL ~(1 << 3) +#else +#define MG4_8_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_8PL) || (G4_5PL == 0) +#define MG4_8_15PL ~(1 << 4) +#else +#define MG4_8_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_8PL) || (G4_6PL == 0) +#define MG4_8_16PL ~(1 << 5) +#else +#define MG4_8_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_8PL) || (G4_7PL == 0) +#define MG4_8_17PL ~(1 << 6) +#else +#define MG4_8_17PL 0xFFFF +#endif + +#if (G4_9PL >= G4_8PL) || (G4_9PL == 0) +#define MG4_8_19PL ~(1 << 8) +#else +#define MG4_8_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_8PL) || (G4_10PL == 0) +#define MG4_8_110PL ~(1 << 9) +#else +#define MG4_8_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_8PL) || (G4_11PL == 0) +#define MG4_8_111PL ~(1 << 10) +#else +#define MG4_8_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_8PL) || (G4_12PL == 0) +#define MG4_8_112PL ~(1 << 11) +#else +#define MG4_8_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_8PL) || (G4_13PL == 0) +#define MG4_8_113PL ~(1 << 12) +#else +#define MG4_8_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_8PL) || (G4_14PL == 0) +#define MG4_8_114PL ~(1 << 13) +#else +#define MG4_8_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_8PL) || (G4_15PL == 0) +#define MG4_8_115PL ~(1 << 14) +#else +#define MG4_8_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_8PL) || (G4_16PL == 0) +#define MG4_8_116PL ~(1 << 15) +#else +#define MG4_8_116PL 0xFFFF +#endif + +#define MG4_8_18PL 0xFF7F +#define MG4_8 (MG4_8_11PL & MG4_8_12PL & MG4_8_13PL & MG4_8_14PL & \ + MG4_8_15PL & MG4_8_16PL & MG4_8_17PL & MG4_8_18PL & \ + MG4_8_19PL & MG4_8_110PL & MG4_8_111PL & MG4_8_112PL & \ + MG4_8_113PL & MG4_8_114PL & MG4_8_115PL & MG4_8_116PL) +// End of MG4_8: +// Beginning of MG49: +#if (G4_1PL >= G4_9PL) || (G4_1PL == 0) +#define MG4_9_11PL ~(1 << 0) +#else +#define MG4_9_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_9PL) || (G4_2PL == 0) +#define MG4_9_12PL ~(1 << 1) +#else +#define MG4_9_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_9PL) || (G4_3PL == 0) +#define MG4_9_13PL ~(1 << 2) +#else +#define MG4_9_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_9PL) || (G4_4PL == 0) +#define MG4_9_14PL ~(1 << 3) +#else +#define MG4_9_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_9PL) || (G4_5PL == 0) +#define MG4_9_15PL ~(1 << 4) +#else +#define MG4_9_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_9PL) || (G4_6PL == 0) +#define MG4_9_16PL ~(1 << 5) +#else +#define MG4_9_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_9PL) || (G4_7PL == 0) +#define MG4_9_17PL ~(1 << 6) +#else +#define MG4_9_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_9PL) || (G4_8PL == 0) +#define MG4_9_18PL ~(1 << 7) +#else +#define MG4_9_18PL 0xFFFF +#endif + +#if (G4_10PL >= G4_9PL) || (G4_10PL == 0) +#define MG4_9_110PL ~(1 << 9) +#else +#define MG4_9_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_9PL) || (G4_11PL == 0) +#define MG4_9_111PL ~(1 << 10) +#else +#define MG4_9_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_9PL) || (G4_12PL == 0) +#define MG4_9_112PL ~(1 << 11) +#else +#define MG4_9_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_9PL) || (G4_13PL == 0) +#define MG4_9_113PL ~(1 << 12) +#else +#define MG4_9_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_9PL) || (G4_14PL == 0) +#define MG4_9_114PL ~(1 << 13) +#else +#define MG4_9_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_9PL) || (G4_15PL == 0) +#define MG4_9_115PL ~(1 << 14) +#else +#define MG4_9_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_9PL) || (G4_16PL == 0) +#define MG4_9_116PL ~(1 << 15) +#else +#define MG4_9_116PL 0xFFFF +#endif + +#define MG4_9_19PL 0xFEFF +#define MG4_9 (MG4_9_11PL & MG4_9_12PL & MG4_9_13PL & MG4_9_14PL & \ + MG4_9_15PL & MG4_9_16PL & MG4_9_17PL & MG4_9_18PL & \ + MG4_9_19PL & MG4_9_110PL & MG4_9_111PL & MG4_9_112PL & \ + MG4_9_113PL & MG4_9_114PL & MG4_9_115PL & MG4_9_116PL) +// End of MG4_9: +// Beginning of MG410: +#if (G4_1PL >= G4_10PL) || (G4_1PL == 0) +#define MG4_10_11PL ~(1 << 0) +#else +#define MG4_10_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_10PL) || (G4_2PL == 0) +#define MG4_10_12PL ~(1 << 1) +#else +#define MG4_10_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_10PL) || (G4_3PL == 0) +#define MG4_10_13PL ~(1 << 2) +#else +#define MG4_10_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_10PL) || (G4_4PL == 0) +#define MG4_10_14PL ~(1 << 3) +#else +#define MG4_10_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_10PL) || (G4_5PL == 0) +#define MG4_10_15PL ~(1 << 4) +#else +#define MG4_10_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_10PL) || (G4_6PL == 0) +#define MG4_10_16PL ~(1 << 5) +#else +#define MG4_10_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_10PL) || (G4_7PL == 0) +#define MG4_10_17PL ~(1 << 6) +#else +#define MG4_10_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_10PL) || (G4_8PL == 0) +#define MG4_10_18PL ~(1 << 7) +#else +#define MG4_10_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_10PL) || (G4_9PL == 0) +#define MG4_10_19PL ~(1 << 8) +#else +#define MG4_10_19PL 0xFFFF +#endif + +#if (G4_11PL >= G4_10PL) || (G4_11PL == 0) +#define MG4_10_111PL ~(1 << 10) +#else +#define MG4_10_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_10PL) || (G4_12PL == 0) +#define MG4_10_112PL ~(1 << 11) +#else +#define MG4_10_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_10PL) || (G4_13PL == 0) +#define MG4_10_113PL ~(1 << 12) +#else +#define MG4_10_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_10PL) || (G4_14PL == 0) +#define MG4_10_114PL ~(1 << 13) +#else +#define MG4_10_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_10PL) || (G4_15PL == 0) +#define MG4_10_115PL ~(1 << 14) +#else +#define MG4_10_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_10PL) || (G4_16PL == 0) +#define MG4_10_116PL ~(1 << 15) +#else +#define MG4_10_116PL 0xFFFF +#endif + +#define MG4_10_110PL 0xFDFF +#define MG4_10 (MG4_10_11PL & MG4_10_12PL & MG4_10_13PL & MG4_10_14PL & \ + MG4_10_15PL & MG4_10_16PL & MG4_10_17PL & MG4_10_18PL & \ + MG4_10_19PL & MG4_10_110PL & MG4_10_111PL & MG4_10_112PL & \ + MG4_10_113PL & MG4_10_114PL & MG4_10_115PL & MG4_10_116PL) +// End of MG4_10: +// Beginning of MG411: +#if (G4_1PL >= G4_11PL) || (G4_1PL == 0) +#define MG4_11_11PL ~(1 << 0) +#else +#define MG4_11_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_11PL) || (G4_2PL == 0) +#define MG4_11_12PL ~(1 << 1) +#else +#define MG4_11_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_11PL) || (G4_3PL == 0) +#define MG4_11_13PL ~(1 << 2) +#else +#define MG4_11_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_11PL) || (G4_4PL == 0) +#define MG4_11_14PL ~(1 << 3) +#else +#define MG4_11_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_11PL) || (G4_5PL == 0) +#define MG4_11_15PL ~(1 << 4) +#else +#define MG4_11_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_11PL) || (G4_6PL == 0) +#define MG4_11_16PL ~(1 << 5) +#else +#define MG4_11_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_11PL) || (G4_7PL == 0) +#define MG4_11_17PL ~(1 << 6) +#else +#define MG4_11_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_11PL) || (G4_8PL == 0) +#define MG4_11_18PL ~(1 << 7) +#else +#define MG4_11_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_11PL) || (G4_9PL == 0) +#define MG4_11_19PL ~(1 << 8) +#else +#define MG4_11_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_11PL) || (G4_10PL == 0) +#define MG4_11_110PL ~(1 << 9) +#else +#define MG4_11_110PL 0xFFFF +#endif + +#if (G4_12PL >= G4_11PL) || (G4_12PL == 0) +#define MG4_11_112PL ~(1 << 11) +#else +#define MG4_11_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_11PL) || (G4_13PL == 0) +#define MG4_11_113PL ~(1 << 12) +#else +#define MG4_11_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_11PL) || (G4_14PL == 0) +#define MG4_11_114PL ~(1 << 13) +#else +#define MG4_11_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_11PL) || (G4_15PL == 0) +#define MG4_11_115PL ~(1 << 14) +#else +#define MG4_11_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_11PL) || (G4_16PL == 0) +#define MG4_11_116PL ~(1 << 15) +#else +#define MG4_11_116PL 0xFFFF +#endif + +#define MG4_11_111PL 0xFBFF +#define MG4_11 (MG4_11_11PL & MG4_11_12PL & MG4_11_13PL & MG4_11_14PL & \ + MG4_11_15PL & MG4_11_16PL & MG4_11_17PL & MG4_11_18PL & \ + MG4_11_19PL & MG4_11_110PL & MG4_11_111PL & MG4_11_112PL & \ + MG4_11_113PL & MG4_11_114PL & MG4_11_115PL & MG4_11_116PL) +// End of MG4_11: +// Beginning of MG412: +#if (G4_1PL >= G4_12PL) || (G4_1PL == 0) +#define MG4_12_11PL ~(1 << 0) +#else +#define MG4_12_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_12PL) || (G4_2PL == 0) +#define MG4_12_12PL ~(1 << 1) +#else +#define MG4_12_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_12PL) || (G4_3PL == 0) +#define MG4_12_13PL ~(1 << 2) +#else +#define MG4_12_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_12PL) || (G4_4PL == 0) +#define MG4_12_14PL ~(1 << 3) +#else +#define MG4_12_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_12PL) || (G4_5PL == 0) +#define MG4_12_15PL ~(1 << 4) +#else +#define MG4_12_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_12PL) || (G4_6PL == 0) +#define MG4_12_16PL ~(1 << 5) +#else +#define MG4_12_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_12PL) || (G4_7PL == 0) +#define MG4_12_17PL ~(1 << 6) +#else +#define MG4_12_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_12PL) || (G4_8PL == 0) +#define MG4_12_18PL ~(1 << 7) +#else +#define MG4_12_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_12PL) || (G4_9PL == 0) +#define MG4_12_19PL ~(1 << 8) +#else +#define MG4_12_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_12PL) || (G4_10PL == 0) +#define MG4_12_110PL ~(1 << 9) +#else +#define MG4_12_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_12PL) || (G4_11PL == 0) +#define MG4_12_111PL ~(1 << 10) +#else +#define MG4_12_111PL 0xFFFF +#endif + +#if (G4_13PL >= G4_12PL) || (G4_13PL == 0) +#define MG4_12_113PL ~(1 << 12) +#else +#define MG4_12_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_12PL) || (G4_14PL == 0) +#define MG4_12_114PL ~(1 << 13) +#else +#define MG4_12_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_12PL) || (G4_15PL == 0) +#define MG4_12_115PL ~(1 << 14) +#else +#define MG4_12_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_12PL) || (G4_16PL == 0) +#define MG4_12_116PL ~(1 << 15) +#else +#define MG4_12_116PL 0xFFFF +#endif + +#define MG4_12_112PL 0xF7FF +#define MG4_12 (MG4_12_11PL & MG4_12_12PL & MG4_12_13PL & MG4_12_14PL & \ + MG4_12_15PL & MG4_12_16PL & MG4_12_17PL & MG4_12_18PL & \ + MG4_12_19PL & MG4_12_110PL & MG4_12_111PL & MG4_12_112PL & \ + MG4_12_113PL & MG4_12_114PL & MG4_12_115PL & MG4_12_116PL) +// End of MG4_12: +// Beginning of MG413: +#if (G4_1PL >= G4_13PL) || (G4_1PL == 0) +#define MG4_13_11PL ~(1 << 0) +#else +#define MG4_13_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_13PL) || (G4_2PL == 0) +#define MG4_13_12PL ~(1 << 1) +#else +#define MG4_13_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_13PL) || (G4_3PL == 0) +#define MG4_13_13PL ~(1 << 2) +#else +#define MG4_13_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_13PL) || (G4_4PL == 0) +#define MG4_13_14PL ~(1 << 3) +#else +#define MG4_13_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_13PL) || (G4_5PL == 0) +#define MG4_13_15PL ~(1 << 4) +#else +#define MG4_13_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_13PL) || (G4_6PL == 0) +#define MG4_13_16PL ~(1 << 5) +#else +#define MG4_13_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_13PL) || (G4_7PL == 0) +#define MG4_13_17PL ~(1 << 6) +#else +#define MG4_13_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_13PL) || (G4_8PL == 0) +#define MG4_13_18PL ~(1 << 7) +#else +#define MG4_13_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_13PL) || (G4_9PL == 0) +#define MG4_13_19PL ~(1 << 8) +#else +#define MG4_13_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_13PL) || (G4_10PL == 0) +#define MG4_13_110PL ~(1 << 9) +#else +#define MG4_13_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_13PL) || (G4_11PL == 0) +#define MG4_13_111PL ~(1 << 10) +#else +#define MG4_13_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_13PL) || (G4_12PL == 0) +#define MG4_13_112PL ~(1 << 11) +#else +#define MG4_13_112PL 0xFFFF +#endif + +#if (G4_14PL >= G4_13PL) || (G4_14PL == 0) +#define MG4_13_114PL ~(1 << 13) +#else +#define MG4_13_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_13PL) || (G4_15PL == 0) +#define MG4_13_115PL ~(1 << 14) +#else +#define MG4_13_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_13PL) || (G4_16PL == 0) +#define MG4_13_116PL ~(1 << 15) +#else +#define MG4_13_116PL 0xFFFF +#endif + +#define MG4_13_113PL 0xEFFF +#define MG4_13 (MG4_13_11PL & MG4_13_12PL & MG4_13_13PL & MG4_13_14PL & \ + MG4_13_15PL & MG4_13_16PL & MG4_13_17PL & MG4_13_18PL & \ + MG4_13_19PL & MG4_13_110PL & MG4_13_111PL & MG4_13_112PL & \ + MG4_13_113PL & MG4_13_114PL & MG4_13_115PL & MG4_13_116PL) +// End of MG4_13: +// Beginning of MG414: +#if (G4_1PL >= G4_14PL) || (G4_1PL == 0) +#define MG4_14_11PL ~(1 << 0) +#else +#define MG4_14_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_14PL) || (G4_2PL == 0) +#define MG4_14_12PL ~(1 << 1) +#else +#define MG4_14_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_14PL) || (G4_3PL == 0) +#define MG4_14_13PL ~(1 << 2) +#else +#define MG4_14_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_14PL) || (G4_4PL == 0) +#define MG4_14_14PL ~(1 << 3) +#else +#define MG4_14_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_14PL) || (G4_5PL == 0) +#define MG4_14_15PL ~(1 << 4) +#else +#define MG4_14_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_14PL) || (G4_6PL == 0) +#define MG4_14_16PL ~(1 << 5) +#else +#define MG4_14_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_14PL) || (G4_7PL == 0) +#define MG4_14_17PL ~(1 << 6) +#else +#define MG4_14_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_14PL) || (G4_8PL == 0) +#define MG4_14_18PL ~(1 << 7) +#else +#define MG4_14_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_14PL) || (G4_9PL == 0) +#define MG4_14_19PL ~(1 << 8) +#else +#define MG4_14_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_14PL) || (G4_10PL == 0) +#define MG4_14_110PL ~(1 << 9) +#else +#define MG4_14_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_14PL) || (G4_11PL == 0) +#define MG4_14_111PL ~(1 << 10) +#else +#define MG4_14_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_14PL) || (G4_12PL == 0) +#define MG4_14_112PL ~(1 << 11) +#else +#define MG4_14_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_14PL) || (G4_13PL == 0) +#define MG4_14_113PL ~(1 << 12) +#else +#define MG4_14_113PL 0xFFFF +#endif + +#if (G4_15PL >= G4_14PL) || (G4_15PL == 0) +#define MG4_14_115PL ~(1 << 14) +#else +#define MG4_14_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_14PL) || (G4_16PL == 0) +#define MG4_14_116PL ~(1 << 15) +#else +#define MG4_14_116PL 0xFFFF +#endif + +#define MG4_14_114PL 0xDFFF +#define MG4_14 (MG4_14_11PL & MG4_14_12PL & MG4_14_13PL & MG4_14_14PL & \ + MG4_14_15PL & MG4_14_16PL & MG4_14_17PL & MG4_14_18PL & \ + MG4_14_19PL & MG4_14_110PL & MG4_14_111PL & MG4_14_112PL & \ + MG4_14_113PL & MG4_14_114PL & MG4_14_115PL & MG4_14_116PL) +// End of MG4_14: +// Beginning of MG415: +#if (G4_1PL >= G4_15PL) || (G4_1PL == 0) +#define MG4_15_11PL ~(1 << 0) +#else +#define MG4_15_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_15PL) || (G4_2PL == 0) +#define MG4_15_12PL ~(1 << 1) +#else +#define MG4_15_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_15PL) || (G4_3PL == 0) +#define MG4_15_13PL ~(1 << 2) +#else +#define MG4_15_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_15PL) || (G4_4PL == 0) +#define MG4_15_14PL ~(1 << 3) +#else +#define MG4_15_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_15PL) || (G4_5PL == 0) +#define MG4_15_15PL ~(1 << 4) +#else +#define MG4_15_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_15PL) || (G4_6PL == 0) +#define MG4_15_16PL ~(1 << 5) +#else +#define MG4_15_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_15PL) || (G4_7PL == 0) +#define MG4_15_17PL ~(1 << 6) +#else +#define MG4_15_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_15PL) || (G4_8PL == 0) +#define MG4_15_18PL ~(1 << 7) +#else +#define MG4_15_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_15PL) || (G4_9PL == 0) +#define MG4_15_19PL ~(1 << 8) +#else +#define MG4_15_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_15PL) || (G4_10PL == 0) +#define MG4_15_110PL ~(1 << 9) +#else +#define MG4_15_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_15PL) || (G4_11PL == 0) +#define MG4_15_111PL ~(1 << 10) +#else +#define MG4_15_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_15PL) || (G4_12PL == 0) +#define MG4_15_112PL ~(1 << 11) +#else +#define MG4_15_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_15PL) || (G4_13PL == 0) +#define MG4_15_113PL ~(1 << 12) +#else +#define MG4_15_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_15PL) || (G4_14PL == 0) +#define MG4_15_114PL ~(1 << 13) +#else +#define MG4_15_114PL 0xFFFF +#endif + +#if (G4_16PL >= G4_15PL) || (G4_16PL == 0) +#define MG4_15_116PL ~(1 << 15) +#else +#define MG4_15_116PL 0xFFFF +#endif + +#define MG4_15_115PL 0xBFFF +#define MG4_15 (MG4_15_11PL & MG4_15_12PL & MG4_15_13PL & MG4_15_14PL & \ + MG4_15_15PL & MG4_15_16PL & MG4_15_17PL & MG4_15_18PL & \ + MG4_15_19PL & MG4_15_110PL & MG4_15_111PL & MG4_15_112PL & \ + MG4_15_113PL & MG4_15_114PL & MG4_15_115PL & MG4_15_116PL) +// End of MG4_15: +// Beginning of MG416: +#if (G4_1PL >= G4_16PL) || (G4_1PL == 0) +#define MG4_16_11PL ~(1 << 0) +#else +#define MG4_16_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_16PL) || (G4_2PL == 0) +#define MG4_16_12PL ~(1 << 1) +#else +#define MG4_16_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_16PL) || (G4_3PL == 0) +#define MG4_16_13PL ~(1 << 2) +#else +#define MG4_16_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_16PL) || (G4_4PL == 0) +#define MG4_16_14PL ~(1 << 3) +#else +#define MG4_16_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_16PL) || (G4_5PL == 0) +#define MG4_16_15PL ~(1 << 4) +#else +#define MG4_16_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_16PL) || (G4_6PL == 0) +#define MG4_16_16PL ~(1 << 5) +#else +#define MG4_16_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_16PL) || (G4_7PL == 0) +#define MG4_16_17PL ~(1 << 6) +#else +#define MG4_16_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_16PL) || (G4_8PL == 0) +#define MG4_16_18PL ~(1 << 7) +#else +#define MG4_16_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_16PL) || (G4_9PL == 0) +#define MG4_16_19PL ~(1 << 8) +#else +#define MG4_16_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_16PL) || (G4_10PL == 0) +#define MG4_16_110PL ~(1 << 9) +#else +#define MG4_16_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_16PL) || (G4_11PL == 0) +#define MG4_16_111PL ~(1 << 10) +#else +#define MG4_16_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_16PL) || (G4_12PL == 0) +#define MG4_16_112PL ~(1 << 11) +#else +#define MG4_16_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_16PL) || (G4_13PL == 0) +#define MG4_16_113PL ~(1 << 12) +#else +#define MG4_16_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_16PL) || (G4_14PL == 0) +#define MG4_16_114PL ~(1 << 13) +#else +#define MG4_16_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_16PL) || (G4_15PL == 0) +#define MG4_16_115PL ~(1 << 14) +#else +#define MG4_16_115PL 0xFFFF +#endif + +#define MG4_16_116PL 0x7FFF +#define MG4_16 (MG4_16_11PL & MG4_16_12PL & MG4_16_13PL & MG4_16_14PL & \ + MG4_16_15PL & MG4_16_16PL & MG4_16_17PL & MG4_16_18PL & \ + MG4_16_19PL & MG4_16_110PL & MG4_16_111PL & MG4_16_112PL & \ + MG4_16_113PL & MG4_16_114PL & MG4_16_115PL & MG4_16_116PL) +// End of MG4_16: + + +// +// Automatically generate PIEIER5 interrupt masks MG51 to MG516: +// + +// Beginning of MG51: +#if (G5_2PL >= G5_1PL) || (G5_2PL == 0) +#define MG5_1_12PL ~(1 << 1) +#else +#define MG5_1_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_1PL) || (G5_3PL == 0) +#define MG5_1_13PL ~(1 << 2) +#else +#define MG5_1_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_1PL) || (G5_4PL == 0) +#define MG5_1_14PL ~(1 << 3) +#else +#define MG5_1_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_1PL) || (G5_5PL == 0) +#define MG5_1_15PL ~(1 << 4) +#else +#define MG5_1_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_1PL) || (G5_6PL == 0) +#define MG5_1_16PL ~(1 << 5) +#else +#define MG5_1_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_1PL) || (G5_7PL == 0) +#define MG5_1_17PL ~(1 << 6) +#else +#define MG5_1_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_1PL) || (G5_8PL == 0) +#define MG5_1_18PL ~(1 << 7) +#else +#define MG5_1_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_1PL) || (G5_9PL == 0) +#define MG5_1_19PL ~(1 << 8) +#else +#define MG5_1_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_1PL) || (G5_10PL == 0) +#define MG5_1_110PL ~(1 << 9) +#else +#define MG5_1_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_1PL) || (G5_11PL == 0) +#define MG5_1_111PL ~(1 << 10) +#else +#define MG5_1_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_1PL) || (G5_12PL == 0) +#define MG5_1_112PL ~(1 << 11) +#else +#define MG5_1_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_1PL) || (G5_13PL == 0) +#define MG5_1_113PL ~(1 << 12) +#else +#define MG5_1_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_1PL) || (G5_14PL == 0) +#define MG5_1_114PL ~(1 << 13) +#else +#define MG5_1_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_1PL) || (G5_15PL == 0) +#define MG5_1_115PL ~(1 << 14) +#else +#define MG5_1_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_1PL) || (G5_16PL == 0) +#define MG5_1_116PL ~(1 << 15) +#else +#define MG5_1_116PL 0xFFFF +#endif + +#define MG5_1_11PL 0xFFFE +#define MG5_1 (MG5_1_11PL & MG5_1_12PL & MG5_1_13PL & MG5_1_14PL & \ + MG5_1_15PL & MG5_1_16PL & MG5_1_17PL & MG5_1_18PL & \ + MG5_1_19PL & MG5_1_110PL & MG5_1_111PL & MG5_1_112PL & \ + MG5_1_113PL & MG5_1_114PL & MG5_1_115PL & MG5_1_116PL) +// End of MG5_1: +// Beginning of MG52: +#if (G5_1PL >= G5_2PL) || (G5_1PL == 0) +#define MG5_2_11PL ~(1 << 0) +#else +#define MG5_2_11PL 0xFFFF +#endif + +#if (G5_3PL >= G5_2PL) || (G5_3PL == 0) +#define MG5_2_13PL ~(1 << 2) +#else +#define MG5_2_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_2PL) || (G5_4PL == 0) +#define MG5_2_14PL ~(1 << 3) +#else +#define MG5_2_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_2PL) || (G5_5PL == 0) +#define MG5_2_15PL ~(1 << 4) +#else +#define MG5_2_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_2PL) || (G5_6PL == 0) +#define MG5_2_16PL ~(1 << 5) +#else +#define MG5_2_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_2PL) || (G5_7PL == 0) +#define MG5_2_17PL ~(1 << 6) +#else +#define MG5_2_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_2PL) || (G5_8PL == 0) +#define MG5_2_18PL ~(1 << 7) +#else +#define MG5_2_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_2PL) || (G5_9PL == 0) +#define MG5_2_19PL ~(1 << 8) +#else +#define MG5_2_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_2PL) || (G5_10PL == 0) +#define MG5_2_110PL ~(1 << 9) +#else +#define MG5_2_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_2PL) || (G5_11PL == 0) +#define MG5_2_111PL ~(1 << 10) +#else +#define MG5_2_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_2PL) || (G5_12PL == 0) +#define MG5_2_112PL ~(1 << 11) +#else +#define MG5_2_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_2PL) || (G5_13PL == 0) +#define MG5_2_113PL ~(1 << 12) +#else +#define MG5_2_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_2PL) || (G5_14PL == 0) +#define MG5_2_114PL ~(1 << 13) +#else +#define MG5_2_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_2PL) || (G5_15PL == 0) +#define MG5_2_115PL ~(1 << 14) +#else +#define MG5_2_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_2PL) || (G5_16PL == 0) +#define MG5_2_116PL ~(1 << 15) +#else +#define MG5_2_116PL 0xFFFF +#endif + +#define MG5_2_12PL 0xFFFD +#define MG5_2 (MG5_2_11PL & MG5_2_12PL & MG5_2_13PL & MG5_2_14PL & \ + MG5_2_15PL & MG5_2_16PL & MG5_2_17PL & MG5_2_18PL & \ + MG5_2_19PL & MG5_2_110PL & MG5_2_111PL & MG5_2_112PL & \ + MG5_2_113PL & MG5_2_114PL & MG5_2_115PL & MG5_2_116PL) +// End of MG5_2: +// Beginning of MG53: +#if (G5_1PL >= G5_3PL) || (G5_1PL == 0) +#define MG5_3_11PL ~(1 << 0) +#else +#define MG5_3_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_3PL) || (G5_2PL == 0) +#define MG5_3_12PL ~(1 << 1) +#else +#define MG5_3_12PL 0xFFFF +#endif + +#if (G5_4PL >= G5_3PL) || (G5_4PL == 0) +#define MG5_3_14PL ~(1 << 3) +#else +#define MG5_3_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_3PL) || (G5_5PL == 0) +#define MG5_3_15PL ~(1 << 4) +#else +#define MG5_3_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_3PL) || (G5_6PL == 0) +#define MG5_3_16PL ~(1 << 5) +#else +#define MG5_3_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_3PL) || (G5_7PL == 0) +#define MG5_3_17PL ~(1 << 6) +#else +#define MG5_3_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_3PL) || (G5_8PL == 0) +#define MG5_3_18PL ~(1 << 7) +#else +#define MG5_3_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_3PL) || (G5_9PL == 0) +#define MG5_3_19PL ~(1 << 8) +#else +#define MG5_3_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_3PL) || (G5_10PL == 0) +#define MG5_3_110PL ~(1 << 9) +#else +#define MG5_3_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_3PL) || (G5_11PL == 0) +#define MG5_3_111PL ~(1 << 10) +#else +#define MG5_3_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_3PL) || (G5_12PL == 0) +#define MG5_3_112PL ~(1 << 11) +#else +#define MG5_3_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_3PL) || (G5_13PL == 0) +#define MG5_3_113PL ~(1 << 12) +#else +#define MG5_3_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_3PL) || (G5_14PL == 0) +#define MG5_3_114PL ~(1 << 13) +#else +#define MG5_3_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_3PL) || (G5_15PL == 0) +#define MG5_3_115PL ~(1 << 14) +#else +#define MG5_3_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_3PL) || (G5_16PL == 0) +#define MG5_3_116PL ~(1 << 15) +#else +#define MG5_3_116PL 0xFFFF +#endif + +#define MG5_3_13PL 0xFFFB +#define MG5_3 (MG5_3_11PL & MG5_3_12PL & MG5_3_13PL & MG5_3_14PL & \ + MG5_3_15PL & MG5_3_16PL & MG5_3_17PL & MG5_3_18PL & \ + MG5_3_19PL & MG5_3_110PL & MG5_3_111PL & MG5_3_112PL & \ + MG5_3_113PL & MG5_3_114PL & MG5_3_115PL & MG5_3_116PL) +// End of MG5_3: +// Beginning of MG54: +#if (G5_1PL >= G5_4PL) || (G5_1PL == 0) +#define MG5_4_11PL ~(1 << 0) +#else +#define MG5_4_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_4PL) || (G5_2PL == 0) +#define MG5_4_12PL ~(1 << 1) +#else +#define MG5_4_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_4PL) || (G5_3PL == 0) +#define MG5_4_13PL ~(1 << 2) +#else +#define MG5_4_13PL 0xFFFF +#endif + +#if (G5_5PL >= G5_4PL) || (G5_5PL == 0) +#define MG5_4_15PL ~(1 << 4) +#else +#define MG5_4_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_4PL) || (G5_6PL == 0) +#define MG5_4_16PL ~(1 << 5) +#else +#define MG5_4_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_4PL) || (G5_7PL == 0) +#define MG5_4_17PL ~(1 << 6) +#else +#define MG5_4_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_4PL) || (G5_8PL == 0) +#define MG5_4_18PL ~(1 << 7) +#else +#define MG5_4_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_4PL) || (G5_9PL == 0) +#define MG5_4_19PL ~(1 << 8) +#else +#define MG5_4_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_4PL) || (G5_10PL == 0) +#define MG5_4_110PL ~(1 << 9) +#else +#define MG5_4_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_4PL) || (G5_11PL == 0) +#define MG5_4_111PL ~(1 << 10) +#else +#define MG5_4_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_4PL) || (G5_12PL == 0) +#define MG5_4_112PL ~(1 << 11) +#else +#define MG5_4_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_4PL) || (G5_13PL == 0) +#define MG5_4_113PL ~(1 << 12) +#else +#define MG5_4_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_4PL) || (G5_14PL == 0) +#define MG5_4_114PL ~(1 << 13) +#else +#define MG5_4_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_4PL) || (G5_15PL == 0) +#define MG5_4_115PL ~(1 << 14) +#else +#define MG5_4_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_4PL) || (G5_16PL == 0) +#define MG5_4_116PL ~(1 << 15) +#else +#define MG5_4_116PL 0xFFFF +#endif + +#define MG5_4_14PL 0xFFF7 +#define MG5_4 (MG5_4_11PL & MG5_4_12PL & MG5_4_13PL & MG5_4_14PL & \ + MG5_4_15PL & MG5_4_16PL & MG5_4_17PL & MG5_4_18PL & \ + MG5_4_19PL & MG5_4_110PL & MG5_4_111PL & MG5_4_112PL & \ + MG5_4_113PL & MG5_4_114PL & MG5_4_115PL & MG5_4_116PL) +// End of MG5_4: +// Beginning of MG55: +#if (G5_1PL >= G5_5PL) || (G5_1PL == 0) +#define MG5_5_11PL ~(1 << 0) +#else +#define MG5_5_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_5PL) || (G5_2PL == 0) +#define MG5_5_12PL ~(1 << 1) +#else +#define MG5_5_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_5PL) || (G5_3PL == 0) +#define MG5_5_13PL ~(1 << 2) +#else +#define MG5_5_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_5PL) || (G5_4PL == 0) +#define MG5_5_14PL ~(1 << 3) +#else +#define MG5_5_14PL 0xFFFF +#endif + +#if (G5_6PL >= G5_5PL) || (G5_6PL == 0) +#define MG5_5_16PL ~(1 << 5) +#else +#define MG5_5_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_5PL) || (G5_7PL == 0) +#define MG5_5_17PL ~(1 << 6) +#else +#define MG5_5_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_5PL) || (G5_8PL == 0) +#define MG5_5_18PL ~(1 << 7) +#else +#define MG5_5_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_5PL) || (G5_9PL == 0) +#define MG5_5_19PL ~(1 << 8) +#else +#define MG5_5_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_5PL) || (G5_10PL == 0) +#define MG5_5_110PL ~(1 << 9) +#else +#define MG5_5_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_5PL) || (G5_11PL == 0) +#define MG5_5_111PL ~(1 << 10) +#else +#define MG5_5_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_5PL) || (G5_12PL == 0) +#define MG5_5_112PL ~(1 << 11) +#else +#define MG5_5_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_5PL) || (G5_13PL == 0) +#define MG5_5_113PL ~(1 << 12) +#else +#define MG5_5_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_5PL) || (G5_14PL == 0) +#define MG5_5_114PL ~(1 << 13) +#else +#define MG5_5_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_5PL) || (G5_15PL == 0) +#define MG5_5_115PL ~(1 << 14) +#else +#define MG5_5_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_5PL) || (G5_16PL == 0) +#define MG5_5_116PL ~(1 << 15) +#else +#define MG5_5_116PL 0xFFFF +#endif + +#define MG5_5_15PL 0xFFEF +#define MG5_5 (MG5_5_11PL & MG5_5_12PL & MG5_5_13PL & MG5_5_14PL & \ + MG5_5_15PL & MG5_5_16PL & MG5_5_17PL & MG5_5_18PL & \ + MG5_5_19PL & MG5_5_110PL & MG5_5_111PL & MG5_5_112PL & \ + MG5_5_113PL & MG5_5_114PL & MG5_5_115PL & MG5_5_116PL) +// End of MG5_5: +// Beginning of MG56: +#if (G5_1PL >= G5_6PL) || (G5_1PL == 0) +#define MG5_6_11PL ~(1 << 0) +#else +#define MG5_6_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_6PL) || (G5_2PL == 0) +#define MG5_6_12PL ~(1 << 1) +#else +#define MG5_6_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_6PL) || (G5_3PL == 0) +#define MG5_6_13PL ~(1 << 2) +#else +#define MG5_6_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_6PL) || (G5_4PL == 0) +#define MG5_6_14PL ~(1 << 3) +#else +#define MG5_6_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_6PL) || (G5_5PL == 0) +#define MG5_6_15PL ~(1 << 4) +#else +#define MG5_6_15PL 0xFFFF +#endif + +#if (G5_7PL >= G5_6PL) || (G5_7PL == 0) +#define MG5_6_17PL ~(1 << 6) +#else +#define MG5_6_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_6PL) || (G5_8PL == 0) +#define MG5_6_18PL ~(1 << 7) +#else +#define MG5_6_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_6PL) || (G5_9PL == 0) +#define MG5_6_19PL ~(1 << 8) +#else +#define MG5_6_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_6PL) || (G5_10PL == 0) +#define MG5_6_110PL ~(1 << 9) +#else +#define MG5_6_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_6PL) || (G5_11PL == 0) +#define MG5_6_111PL ~(1 << 10) +#else +#define MG5_6_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_6PL) || (G5_12PL == 0) +#define MG5_6_112PL ~(1 << 11) +#else +#define MG5_6_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_6PL) || (G5_13PL == 0) +#define MG5_6_113PL ~(1 << 12) +#else +#define MG5_6_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_6PL) || (G5_14PL == 0) +#define MG5_6_114PL ~(1 << 13) +#else +#define MG5_6_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_6PL) || (G5_15PL == 0) +#define MG5_6_115PL ~(1 << 14) +#else +#define MG5_6_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_6PL) || (G5_16PL == 0) +#define MG5_6_116PL ~(1 << 15) +#else +#define MG5_6_116PL 0xFFFF +#endif + +#define MG5_6_16PL 0xFFDF +#define MG5_6 (MG5_6_11PL & MG5_6_12PL & MG5_6_13PL & MG5_6_14PL & \ + MG5_6_15PL & MG5_6_16PL & MG5_6_17PL & MG5_6_18PL & \ + MG5_6_19PL & MG5_6_110PL & MG5_6_111PL & MG5_6_112PL & \ + MG5_6_113PL & MG5_6_114PL & MG5_6_115PL & MG5_6_116PL) +// End of MG5_6: +// Beginning of MG57: +#if (G5_1PL >= G5_7PL) || (G5_1PL == 0) +#define MG5_7_11PL ~(1 << 0) +#else +#define MG5_7_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_7PL) || (G5_2PL == 0) +#define MG5_7_12PL ~(1 << 1) +#else +#define MG5_7_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_7PL) || (G5_3PL == 0) +#define MG5_7_13PL ~(1 << 2) +#else +#define MG5_7_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_7PL) || (G5_4PL == 0) +#define MG5_7_14PL ~(1 << 3) +#else +#define MG5_7_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_7PL) || (G5_5PL == 0) +#define MG5_7_15PL ~(1 << 4) +#else +#define MG5_7_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_7PL) || (G5_6PL == 0) +#define MG5_7_16PL ~(1 << 5) +#else +#define MG5_7_16PL 0xFFFF +#endif + +#if (G5_8PL >= G5_7PL) || (G5_8PL == 0) +#define MG5_7_18PL ~(1 << 7) +#else +#define MG5_7_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_7PL) || (G5_9PL == 0) +#define MG5_7_19PL ~(1 << 8) +#else +#define MG5_7_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_7PL) || (G5_10PL == 0) +#define MG5_7_110PL ~(1 << 9) +#else +#define MG5_7_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_7PL) || (G5_11PL == 0) +#define MG5_7_111PL ~(1 << 10) +#else +#define MG5_7_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_7PL) || (G5_12PL == 0) +#define MG5_7_112PL ~(1 << 11) +#else +#define MG5_7_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_7PL) || (G5_13PL == 0) +#define MG5_7_113PL ~(1 << 12) +#else +#define MG5_7_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_7PL) || (G5_14PL == 0) +#define MG5_7_114PL ~(1 << 13) +#else +#define MG5_7_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_7PL) || (G5_15PL == 0) +#define MG5_7_115PL ~(1 << 14) +#else +#define MG5_7_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_7PL) || (G5_16PL == 0) +#define MG5_7_116PL ~(1 << 15) +#else +#define MG5_7_116PL 0xFFFF +#endif + +#define MG5_7_17PL 0xFFBF +#define MG5_7 (MG5_7_11PL & MG5_7_12PL & MG5_7_13PL & MG5_7_14PL & \ + MG5_7_15PL & MG5_7_16PL & MG5_7_17PL & MG5_7_18PL & \ + MG5_7_19PL & MG5_7_110PL & MG5_7_111PL & MG5_7_112PL & \ + MG5_7_113PL & MG5_7_114PL & MG5_7_115PL & MG5_7_116PL) +// End of MG5_7: +// Beginning of MG58: +#if (G5_1PL >= G5_8PL) || (G5_1PL == 0) +#define MG5_8_11PL ~(1 << 0) +#else +#define MG5_8_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_8PL) || (G5_2PL == 0) +#define MG5_8_12PL ~(1 << 1) +#else +#define MG5_8_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_8PL) || (G5_3PL == 0) +#define MG5_8_13PL ~(1 << 2) +#else +#define MG5_8_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_8PL) || (G5_4PL == 0) +#define MG5_8_14PL ~(1 << 3) +#else +#define MG5_8_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_8PL) || (G5_5PL == 0) +#define MG5_8_15PL ~(1 << 4) +#else +#define MG5_8_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_8PL) || (G5_6PL == 0) +#define MG5_8_16PL ~(1 << 5) +#else +#define MG5_8_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_8PL) || (G5_7PL == 0) +#define MG5_8_17PL ~(1 << 6) +#else +#define MG5_8_17PL 0xFFFF +#endif + +#if (G5_9PL >= G5_8PL) || (G5_9PL == 0) +#define MG5_8_19PL ~(1 << 8) +#else +#define MG5_8_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_8PL) || (G5_10PL == 0) +#define MG5_8_110PL ~(1 << 9) +#else +#define MG5_8_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_8PL) || (G5_11PL == 0) +#define MG5_8_111PL ~(1 << 10) +#else +#define MG5_8_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_8PL) || (G5_12PL == 0) +#define MG5_8_112PL ~(1 << 11) +#else +#define MG5_8_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_8PL) || (G5_13PL == 0) +#define MG5_8_113PL ~(1 << 12) +#else +#define MG5_8_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_8PL) || (G5_14PL == 0) +#define MG5_8_114PL ~(1 << 13) +#else +#define MG5_8_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_8PL) || (G5_15PL == 0) +#define MG5_8_115PL ~(1 << 14) +#else +#define MG5_8_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_8PL) || (G5_16PL == 0) +#define MG5_8_116PL ~(1 << 15) +#else +#define MG5_8_116PL 0xFFFF +#endif + +#define MG5_8_18PL 0xFF7F +#define MG5_8 (MG5_8_11PL & MG5_8_12PL & MG5_8_13PL & MG5_8_14PL & \ + MG5_8_15PL & MG5_8_16PL & MG5_8_17PL & MG5_8_18PL & \ + MG5_8_19PL & MG5_8_110PL & MG5_8_111PL & MG5_8_112PL & \ + MG5_8_113PL & MG5_8_114PL & MG5_8_115PL & MG5_8_116PL) +// End of MG5_8: +// Beginning of MG59: +#if (G5_1PL >= G5_9PL) || (G5_1PL == 0) +#define MG5_9_11PL ~(1 << 0) +#else +#define MG5_9_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_9PL) || (G5_2PL == 0) +#define MG5_9_12PL ~(1 << 1) +#else +#define MG5_9_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_9PL) || (G5_3PL == 0) +#define MG5_9_13PL ~(1 << 2) +#else +#define MG5_9_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_9PL) || (G5_4PL == 0) +#define MG5_9_14PL ~(1 << 3) +#else +#define MG5_9_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_9PL) || (G5_5PL == 0) +#define MG5_9_15PL ~(1 << 4) +#else +#define MG5_9_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_9PL) || (G5_6PL == 0) +#define MG5_9_16PL ~(1 << 5) +#else +#define MG5_9_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_9PL) || (G5_7PL == 0) +#define MG5_9_17PL ~(1 << 6) +#else +#define MG5_9_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_9PL) || (G5_8PL == 0) +#define MG5_9_18PL ~(1 << 7) +#else +#define MG5_9_18PL 0xFFFF +#endif + +#if (G5_10PL >= G5_9PL) || (G5_10PL == 0) +#define MG5_9_110PL ~(1 << 9) +#else +#define MG5_9_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_9PL) || (G5_11PL == 0) +#define MG5_9_111PL ~(1 << 10) +#else +#define MG5_9_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_9PL) || (G5_12PL == 0) +#define MG5_9_112PL ~(1 << 11) +#else +#define MG5_9_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_9PL) || (G5_13PL == 0) +#define MG5_9_113PL ~(1 << 12) +#else +#define MG5_9_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_9PL) || (G5_14PL == 0) +#define MG5_9_114PL ~(1 << 13) +#else +#define MG5_9_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_9PL) || (G5_15PL == 0) +#define MG5_9_115PL ~(1 << 14) +#else +#define MG5_9_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_9PL) || (G5_16PL == 0) +#define MG5_9_116PL ~(1 << 15) +#else +#define MG5_9_116PL 0xFFFF +#endif + +#define MG5_9_19PL 0xFEFF +#define MG5_9 (MG5_9_11PL & MG5_9_12PL & MG5_9_13PL & MG5_9_14PL & \ + MG5_9_15PL & MG5_9_16PL & MG5_9_17PL & MG5_9_18PL & \ + MG5_9_19PL & MG5_9_110PL & MG5_9_111PL & MG5_9_112PL & \ + MG5_9_113PL & MG5_9_114PL & MG5_9_115PL & MG5_9_116PL) +// End of MG5_9: +// Beginning of MG510: +#if (G5_1PL >= G5_10PL) || (G5_1PL == 0) +#define MG5_10_11PL ~(1 << 0) +#else +#define MG5_10_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_10PL) || (G5_2PL == 0) +#define MG5_10_12PL ~(1 << 1) +#else +#define MG5_10_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_10PL) || (G5_3PL == 0) +#define MG5_10_13PL ~(1 << 2) +#else +#define MG5_10_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_10PL) || (G5_4PL == 0) +#define MG5_10_14PL ~(1 << 3) +#else +#define MG5_10_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_10PL) || (G5_5PL == 0) +#define MG5_10_15PL ~(1 << 4) +#else +#define MG5_10_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_10PL) || (G5_6PL == 0) +#define MG5_10_16PL ~(1 << 5) +#else +#define MG5_10_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_10PL) || (G5_7PL == 0) +#define MG5_10_17PL ~(1 << 6) +#else +#define MG5_10_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_10PL) || (G5_8PL == 0) +#define MG5_10_18PL ~(1 << 7) +#else +#define MG5_10_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_10PL) || (G5_9PL == 0) +#define MG5_10_19PL ~(1 << 8) +#else +#define MG5_10_19PL 0xFFFF +#endif + +#if (G5_11PL >= G5_10PL) || (G5_11PL == 0) +#define MG5_10_111PL ~(1 << 10) +#else +#define MG5_10_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_10PL) || (G5_12PL == 0) +#define MG5_10_112PL ~(1 << 11) +#else +#define MG5_10_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_10PL) || (G5_13PL == 0) +#define MG5_10_113PL ~(1 << 12) +#else +#define MG5_10_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_10PL) || (G5_14PL == 0) +#define MG5_10_114PL ~(1 << 13) +#else +#define MG5_10_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_10PL) || (G5_15PL == 0) +#define MG5_10_115PL ~(1 << 14) +#else +#define MG5_10_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_10PL) || (G5_16PL == 0) +#define MG5_10_116PL ~(1 << 15) +#else +#define MG5_10_116PL 0xFFFF +#endif + +#define MG5_10_110PL 0xFDFF +#define MG5_10 (MG5_10_11PL & MG5_10_12PL & MG5_10_13PL & MG5_10_14PL & \ + MG5_10_15PL & MG5_10_16PL & MG5_10_17PL & MG5_10_18PL & \ + MG5_10_19PL & MG5_10_110PL & MG5_10_111PL & MG5_10_112PL & \ + MG5_10_113PL & MG5_10_114PL & MG5_10_115PL & MG5_10_116PL) +// End of MG5_10: +// Beginning of MG511: +#if (G5_1PL >= G5_11PL) || (G5_1PL == 0) +#define MG5_11_11PL ~(1 << 0) +#else +#define MG5_11_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_11PL) || (G5_2PL == 0) +#define MG5_11_12PL ~(1 << 1) +#else +#define MG5_11_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_11PL) || (G5_3PL == 0) +#define MG5_11_13PL ~(1 << 2) +#else +#define MG5_11_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_11PL) || (G5_4PL == 0) +#define MG5_11_14PL ~(1 << 3) +#else +#define MG5_11_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_11PL) || (G5_5PL == 0) +#define MG5_11_15PL ~(1 << 4) +#else +#define MG5_11_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_11PL) || (G5_6PL == 0) +#define MG5_11_16PL ~(1 << 5) +#else +#define MG5_11_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_11PL) || (G5_7PL == 0) +#define MG5_11_17PL ~(1 << 6) +#else +#define MG5_11_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_11PL) || (G5_8PL == 0) +#define MG5_11_18PL ~(1 << 7) +#else +#define MG5_11_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_11PL) || (G5_9PL == 0) +#define MG5_11_19PL ~(1 << 8) +#else +#define MG5_11_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_11PL) || (G5_10PL == 0) +#define MG5_11_110PL ~(1 << 9) +#else +#define MG5_11_110PL 0xFFFF +#endif + +#if (G5_12PL >= G5_11PL) || (G5_12PL == 0) +#define MG5_11_112PL ~(1 << 11) +#else +#define MG5_11_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_11PL) || (G5_13PL == 0) +#define MG5_11_113PL ~(1 << 12) +#else +#define MG5_11_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_11PL) || (G5_14PL == 0) +#define MG5_11_114PL ~(1 << 13) +#else +#define MG5_11_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_11PL) || (G5_15PL == 0) +#define MG5_11_115PL ~(1 << 14) +#else +#define MG5_11_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_11PL) || (G5_16PL == 0) +#define MG5_11_116PL ~(1 << 15) +#else +#define MG5_11_116PL 0xFFFF +#endif + +#define MG5_11_111PL 0xFBFF +#define MG5_11 (MG5_11_11PL & MG5_11_12PL & MG5_11_13PL & MG5_11_14PL & \ + MG5_11_15PL & MG5_11_16PL & MG5_11_17PL & MG5_11_18PL & \ + MG5_11_19PL & MG5_11_110PL & MG5_11_111PL & MG5_11_112PL & \ + MG5_11_113PL & MG5_11_114PL & MG5_11_115PL & MG5_11_116PL) +// End of MG5_11: +// Beginning of MG512: +#if (G5_1PL >= G5_12PL) || (G5_1PL == 0) +#define MG5_12_11PL ~(1 << 0) +#else +#define MG5_12_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_12PL) || (G5_2PL == 0) +#define MG5_12_12PL ~(1 << 1) +#else +#define MG5_12_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_12PL) || (G5_3PL == 0) +#define MG5_12_13PL ~(1 << 2) +#else +#define MG5_12_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_12PL) || (G5_4PL == 0) +#define MG5_12_14PL ~(1 << 3) +#else +#define MG5_12_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_12PL) || (G5_5PL == 0) +#define MG5_12_15PL ~(1 << 4) +#else +#define MG5_12_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_12PL) || (G5_6PL == 0) +#define MG5_12_16PL ~(1 << 5) +#else +#define MG5_12_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_12PL) || (G5_7PL == 0) +#define MG5_12_17PL ~(1 << 6) +#else +#define MG5_12_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_12PL) || (G5_8PL == 0) +#define MG5_12_18PL ~(1 << 7) +#else +#define MG5_12_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_12PL) || (G5_9PL == 0) +#define MG5_12_19PL ~(1 << 8) +#else +#define MG5_12_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_12PL) || (G5_10PL == 0) +#define MG5_12_110PL ~(1 << 9) +#else +#define MG5_12_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_12PL) || (G5_11PL == 0) +#define MG5_12_111PL ~(1 << 10) +#else +#define MG5_12_111PL 0xFFFF +#endif + +#if (G5_13PL >= G5_12PL) || (G5_13PL == 0) +#define MG5_12_113PL ~(1 << 12) +#else +#define MG5_12_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_12PL) || (G5_14PL == 0) +#define MG5_12_114PL ~(1 << 13) +#else +#define MG5_12_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_12PL) || (G5_15PL == 0) +#define MG5_12_115PL ~(1 << 14) +#else +#define MG5_12_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_12PL) || (G5_16PL == 0) +#define MG5_12_116PL ~(1 << 15) +#else +#define MG5_12_116PL 0xFFFF +#endif + +#define MG5_12_112PL 0xF7FF +#define MG5_12 (MG5_12_11PL & MG5_12_12PL & MG5_12_13PL & MG5_12_14PL & \ + MG5_12_15PL & MG5_12_16PL & MG5_12_17PL & MG5_12_18PL & \ + MG5_12_19PL & MG5_12_110PL & MG5_12_111PL & MG5_12_112PL & \ + MG5_12_113PL & MG5_12_114PL & MG5_12_115PL & MG5_12_116PL) +// End of MG5_12: +// Beginning of MG513: +#if (G5_1PL >= G5_13PL) || (G5_1PL == 0) +#define MG5_13_11PL ~(1 << 0) +#else +#define MG5_13_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_13PL) || (G5_2PL == 0) +#define MG5_13_12PL ~(1 << 1) +#else +#define MG5_13_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_13PL) || (G5_3PL == 0) +#define MG5_13_13PL ~(1 << 2) +#else +#define MG5_13_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_13PL) || (G5_4PL == 0) +#define MG5_13_14PL ~(1 << 3) +#else +#define MG5_13_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_13PL) || (G5_5PL == 0) +#define MG5_13_15PL ~(1 << 4) +#else +#define MG5_13_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_13PL) || (G5_6PL == 0) +#define MG5_13_16PL ~(1 << 5) +#else +#define MG5_13_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_13PL) || (G5_7PL == 0) +#define MG5_13_17PL ~(1 << 6) +#else +#define MG5_13_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_13PL) || (G5_8PL == 0) +#define MG5_13_18PL ~(1 << 7) +#else +#define MG5_13_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_13PL) || (G5_9PL == 0) +#define MG5_13_19PL ~(1 << 8) +#else +#define MG5_13_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_13PL) || (G5_10PL == 0) +#define MG5_13_110PL ~(1 << 9) +#else +#define MG5_13_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_13PL) || (G5_11PL == 0) +#define MG5_13_111PL ~(1 << 10) +#else +#define MG5_13_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_13PL) || (G5_12PL == 0) +#define MG5_13_112PL ~(1 << 11) +#else +#define MG5_13_112PL 0xFFFF +#endif + +#if (G5_14PL >= G5_13PL) || (G5_14PL == 0) +#define MG5_13_114PL ~(1 << 13) +#else +#define MG5_13_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_13PL) || (G5_15PL == 0) +#define MG5_13_115PL ~(1 << 14) +#else +#define MG5_13_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_13PL) || (G5_16PL == 0) +#define MG5_13_116PL ~(1 << 15) +#else +#define MG5_13_116PL 0xFFFF +#endif + +#define MG5_13_113PL 0xEFFF +#define MG5_13 (MG5_13_11PL & MG5_13_12PL & MG5_13_13PL & MG5_13_14PL & \ + MG5_13_15PL & MG5_13_16PL & MG5_13_17PL & MG5_13_18PL & \ + MG5_13_19PL & MG5_13_110PL & MG5_13_111PL & MG5_13_112PL & \ + MG5_13_113PL & MG5_13_114PL & MG5_13_115PL & MG5_13_116PL) +// End of MG5_13: +// Beginning of MG514: +#if (G5_1PL >= G5_14PL) || (G5_1PL == 0) +#define MG5_14_11PL ~(1 << 0) +#else +#define MG5_14_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_14PL) || (G5_2PL == 0) +#define MG5_14_12PL ~(1 << 1) +#else +#define MG5_14_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_14PL) || (G5_3PL == 0) +#define MG5_14_13PL ~(1 << 2) +#else +#define MG5_14_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_14PL) || (G5_4PL == 0) +#define MG5_14_14PL ~(1 << 3) +#else +#define MG5_14_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_14PL) || (G5_5PL == 0) +#define MG5_14_15PL ~(1 << 4) +#else +#define MG5_14_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_14PL) || (G5_6PL == 0) +#define MG5_14_16PL ~(1 << 5) +#else +#define MG5_14_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_14PL) || (G5_7PL == 0) +#define MG5_14_17PL ~(1 << 6) +#else +#define MG5_14_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_14PL) || (G5_8PL == 0) +#define MG5_14_18PL ~(1 << 7) +#else +#define MG5_14_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_14PL) || (G5_9PL == 0) +#define MG5_14_19PL ~(1 << 8) +#else +#define MG5_14_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_14PL) || (G5_10PL == 0) +#define MG5_14_110PL ~(1 << 9) +#else +#define MG5_14_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_14PL) || (G5_11PL == 0) +#define MG5_14_111PL ~(1 << 10) +#else +#define MG5_14_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_14PL) || (G5_12PL == 0) +#define MG5_14_112PL ~(1 << 11) +#else +#define MG5_14_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_14PL) || (G5_13PL == 0) +#define MG5_14_113PL ~(1 << 12) +#else +#define MG5_14_113PL 0xFFFF +#endif + +#if (G5_15PL >= G5_14PL) || (G5_15PL == 0) +#define MG5_14_115PL ~(1 << 14) +#else +#define MG5_14_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_14PL) || (G5_16PL == 0) +#define MG5_14_116PL ~(1 << 15) +#else +#define MG5_14_116PL 0xFFFF +#endif + +#define MG5_14_114PL 0xDFFF +#define MG5_14 (MG5_14_11PL & MG5_14_12PL & MG5_14_13PL & MG5_14_14PL & \ + MG5_14_15PL & MG5_14_16PL & MG5_14_17PL & MG5_14_18PL & \ + MG5_14_19PL & MG5_14_110PL & MG5_14_111PL & MG5_14_112PL & \ + MG5_14_113PL & MG5_14_114PL & MG5_14_115PL & MG5_14_116PL) +// End of MG5_14: +// Beginning of MG515: +#if (G5_1PL >= G5_15PL) || (G5_1PL == 0) +#define MG5_15_11PL ~(1 << 0) +#else +#define MG5_15_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_15PL) || (G5_2PL == 0) +#define MG5_15_12PL ~(1 << 1) +#else +#define MG5_15_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_15PL) || (G5_3PL == 0) +#define MG5_15_13PL ~(1 << 2) +#else +#define MG5_15_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_15PL) || (G5_4PL == 0) +#define MG5_15_14PL ~(1 << 3) +#else +#define MG5_15_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_15PL) || (G5_5PL == 0) +#define MG5_15_15PL ~(1 << 4) +#else +#define MG5_15_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_15PL) || (G5_6PL == 0) +#define MG5_15_16PL ~(1 << 5) +#else +#define MG5_15_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_15PL) || (G5_7PL == 0) +#define MG5_15_17PL ~(1 << 6) +#else +#define MG5_15_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_15PL) || (G5_8PL == 0) +#define MG5_15_18PL ~(1 << 7) +#else +#define MG5_15_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_15PL) || (G5_9PL == 0) +#define MG5_15_19PL ~(1 << 8) +#else +#define MG5_15_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_15PL) || (G5_10PL == 0) +#define MG5_15_110PL ~(1 << 9) +#else +#define MG5_15_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_15PL) || (G5_11PL == 0) +#define MG5_15_111PL ~(1 << 10) +#else +#define MG5_15_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_15PL) || (G5_12PL == 0) +#define MG5_15_112PL ~(1 << 11) +#else +#define MG5_15_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_15PL) || (G5_13PL == 0) +#define MG5_15_113PL ~(1 << 12) +#else +#define MG5_15_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_15PL) || (G5_14PL == 0) +#define MG5_15_114PL ~(1 << 13) +#else +#define MG5_15_114PL 0xFFFF +#endif + +#if (G5_16PL >= G5_15PL) || (G5_16PL == 0) +#define MG5_15_116PL ~(1 << 15) +#else +#define MG5_15_116PL 0xFFFF +#endif + +#define MG5_15_115PL 0xBFFF +#define MG5_15 (MG5_15_11PL & MG5_15_12PL & MG5_15_13PL & MG5_15_14PL & \ + MG5_15_15PL & MG5_15_16PL & MG5_15_17PL & MG5_15_18PL & \ + MG5_15_19PL & MG5_15_110PL & MG5_15_111PL & MG5_15_112PL & \ + MG5_15_113PL & MG5_15_114PL & MG5_15_115PL & MG5_15_116PL) +// End of MG5_15: +// Beginning of MG516: +#if (G5_1PL >= G5_16PL) || (G5_1PL == 0) +#define MG5_16_11PL ~(1 << 0) +#else +#define MG5_16_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_16PL) || (G5_2PL == 0) +#define MG5_16_12PL ~(1 << 1) +#else +#define MG5_16_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_16PL) || (G5_3PL == 0) +#define MG5_16_13PL ~(1 << 2) +#else +#define MG5_16_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_16PL) || (G5_4PL == 0) +#define MG5_16_14PL ~(1 << 3) +#else +#define MG5_16_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_16PL) || (G5_5PL == 0) +#define MG5_16_15PL ~(1 << 4) +#else +#define MG5_16_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_16PL) || (G5_6PL == 0) +#define MG5_16_16PL ~(1 << 5) +#else +#define MG5_16_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_16PL) || (G5_7PL == 0) +#define MG5_16_17PL ~(1 << 6) +#else +#define MG5_16_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_16PL) || (G5_8PL == 0) +#define MG5_16_18PL ~(1 << 7) +#else +#define MG5_16_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_16PL) || (G5_9PL == 0) +#define MG5_16_19PL ~(1 << 8) +#else +#define MG5_16_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_16PL) || (G5_10PL == 0) +#define MG5_16_110PL ~(1 << 9) +#else +#define MG5_16_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_16PL) || (G5_11PL == 0) +#define MG5_16_111PL ~(1 << 10) +#else +#define MG5_16_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_16PL) || (G5_12PL == 0) +#define MG5_16_112PL ~(1 << 11) +#else +#define MG5_16_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_16PL) || (G5_13PL == 0) +#define MG5_16_113PL ~(1 << 12) +#else +#define MG5_16_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_16PL) || (G5_14PL == 0) +#define MG5_16_114PL ~(1 << 13) +#else +#define MG5_16_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_16PL) || (G5_15PL == 0) +#define MG5_16_115PL ~(1 << 14) +#else +#define MG5_16_115PL 0xFFFF +#endif + +#define MG5_16_116PL 0x7FFF +#define MG5_16 (MG5_16_11PL & MG5_16_12PL & MG5_16_13PL & MG5_16_14PL & \ + MG5_16_15PL & MG5_16_16PL & MG5_16_17PL & MG5_16_18PL & \ + MG5_16_19PL & MG5_16_110PL & MG5_16_111PL & MG5_16_112PL & \ + MG5_16_113PL & MG5_16_114PL & MG5_16_115PL & MG5_16_116PL) +// End of MG5_16: + + +// +// Automatically generate PIEIER6 interrupt masks MG61 to MG616: +// + +// Beginning of MG61: +#if (G6_2PL >= G6_1PL) || (G6_2PL == 0) +#define MG6_1_12PL ~(1 << 1) +#else +#define MG6_1_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_1PL) || (G6_3PL == 0) +#define MG6_1_13PL ~(1 << 2) +#else +#define MG6_1_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_1PL) || (G6_4PL == 0) +#define MG6_1_14PL ~(1 << 3) +#else +#define MG6_1_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_1PL) || (G6_5PL == 0) +#define MG6_1_15PL ~(1 << 4) +#else +#define MG6_1_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_1PL) || (G6_6PL == 0) +#define MG6_1_16PL ~(1 << 5) +#else +#define MG6_1_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_1PL) || (G6_7PL == 0) +#define MG6_1_17PL ~(1 << 6) +#else +#define MG6_1_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_1PL) || (G6_8PL == 0) +#define MG6_1_18PL ~(1 << 7) +#else +#define MG6_1_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_1PL) || (G6_9PL == 0) +#define MG6_1_19PL ~(1 << 8) +#else +#define MG6_1_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_1PL) || (G6_10PL == 0) +#define MG6_1_110PL ~(1 << 9) +#else +#define MG6_1_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_1PL) || (G6_11PL == 0) +#define MG6_1_111PL ~(1 << 10) +#else +#define MG6_1_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_1PL) || (G6_12PL == 0) +#define MG6_1_112PL ~(1 << 11) +#else +#define MG6_1_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_1PL) || (G6_13PL == 0) +#define MG6_1_113PL ~(1 << 12) +#else +#define MG6_1_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_1PL) || (G6_14PL == 0) +#define MG6_1_114PL ~(1 << 13) +#else +#define MG6_1_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_1PL) || (G6_15PL == 0) +#define MG6_1_115PL ~(1 << 14) +#else +#define MG6_1_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_1PL) || (G6_16PL == 0) +#define MG6_1_116PL ~(1 << 15) +#else +#define MG6_1_116PL 0xFFFF +#endif + +#define MG6_1_11PL 0xFFFE +#define MG6_1 (MG6_1_11PL & MG6_1_12PL & MG6_1_13PL & MG6_1_14PL & \ + MG6_1_15PL & MG6_1_16PL & MG6_1_17PL & MG6_1_18PL & \ + MG6_1_19PL & MG6_1_110PL & MG6_1_111PL & MG6_1_112PL & \ + MG6_1_113PL & MG6_1_114PL & MG6_1_115PL & MG6_1_116PL) +// End of MG6_1: +// Beginning of MG62: +#if (G6_1PL >= G6_2PL) || (G6_1PL == 0) +#define MG6_2_11PL ~(1 << 0) +#else +#define MG6_2_11PL 0xFFFF +#endif + +#if (G6_3PL >= G6_2PL) || (G6_3PL == 0) +#define MG6_2_13PL ~(1 << 2) +#else +#define MG6_2_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_2PL) || (G6_4PL == 0) +#define MG6_2_14PL ~(1 << 3) +#else +#define MG6_2_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_2PL) || (G6_5PL == 0) +#define MG6_2_15PL ~(1 << 4) +#else +#define MG6_2_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_2PL) || (G6_6PL == 0) +#define MG6_2_16PL ~(1 << 5) +#else +#define MG6_2_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_2PL) || (G6_7PL == 0) +#define MG6_2_17PL ~(1 << 6) +#else +#define MG6_2_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_2PL) || (G6_8PL == 0) +#define MG6_2_18PL ~(1 << 7) +#else +#define MG6_2_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_2PL) || (G6_9PL == 0) +#define MG6_2_19PL ~(1 << 8) +#else +#define MG6_2_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_2PL) || (G6_10PL == 0) +#define MG6_2_110PL ~(1 << 9) +#else +#define MG6_2_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_2PL) || (G6_11PL == 0) +#define MG6_2_111PL ~(1 << 10) +#else +#define MG6_2_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_2PL) || (G6_12PL == 0) +#define MG6_2_112PL ~(1 << 11) +#else +#define MG6_2_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_2PL) || (G6_13PL == 0) +#define MG6_2_113PL ~(1 << 12) +#else +#define MG6_2_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_2PL) || (G6_14PL == 0) +#define MG6_2_114PL ~(1 << 13) +#else +#define MG6_2_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_2PL) || (G6_15PL == 0) +#define MG6_2_115PL ~(1 << 14) +#else +#define MG6_2_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_2PL) || (G6_16PL == 0) +#define MG6_2_116PL ~(1 << 15) +#else +#define MG6_2_116PL 0xFFFF +#endif + +#define MG6_2_12PL 0xFFFD +#define MG6_2 (MG6_2_11PL & MG6_2_12PL & MG6_2_13PL & MG6_2_14PL & \ + MG6_2_15PL & MG6_2_16PL & MG6_2_17PL & MG6_2_18PL & \ + MG6_2_19PL & MG6_2_110PL & MG6_2_111PL & MG6_2_112PL & \ + MG6_2_113PL & MG6_2_114PL & MG6_2_115PL & MG6_2_116PL) +// End of MG6_2: +// Beginning of MG63: +#if (G6_1PL >= G6_3PL) || (G6_1PL == 0) +#define MG6_3_11PL ~(1 << 0) +#else +#define MG6_3_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_3PL) || (G6_2PL == 0) +#define MG6_3_12PL ~(1 << 1) +#else +#define MG6_3_12PL 0xFFFF +#endif + +#if (G6_4PL >= G6_3PL) || (G6_4PL == 0) +#define MG6_3_14PL ~(1 << 3) +#else +#define MG6_3_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_3PL) || (G6_5PL == 0) +#define MG6_3_15PL ~(1 << 4) +#else +#define MG6_3_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_3PL) || (G6_6PL == 0) +#define MG6_3_16PL ~(1 << 5) +#else +#define MG6_3_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_3PL) || (G6_7PL == 0) +#define MG6_3_17PL ~(1 << 6) +#else +#define MG6_3_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_3PL) || (G6_8PL == 0) +#define MG6_3_18PL ~(1 << 7) +#else +#define MG6_3_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_3PL) || (G6_9PL == 0) +#define MG6_3_19PL ~(1 << 8) +#else +#define MG6_3_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_3PL) || (G6_10PL == 0) +#define MG6_3_110PL ~(1 << 9) +#else +#define MG6_3_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_3PL) || (G6_11PL == 0) +#define MG6_3_111PL ~(1 << 10) +#else +#define MG6_3_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_3PL) || (G6_12PL == 0) +#define MG6_3_112PL ~(1 << 11) +#else +#define MG6_3_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_3PL) || (G6_13PL == 0) +#define MG6_3_113PL ~(1 << 12) +#else +#define MG6_3_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_3PL) || (G6_14PL == 0) +#define MG6_3_114PL ~(1 << 13) +#else +#define MG6_3_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_3PL) || (G6_15PL == 0) +#define MG6_3_115PL ~(1 << 14) +#else +#define MG6_3_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_3PL) || (G6_16PL == 0) +#define MG6_3_116PL ~(1 << 15) +#else +#define MG6_3_116PL 0xFFFF +#endif + +#define MG6_3_13PL 0xFFFB +#define MG6_3 (MG6_3_11PL & MG6_3_12PL & MG6_3_13PL & MG6_3_14PL & \ + MG6_3_15PL & MG6_3_16PL & MG6_3_17PL & MG6_3_18PL & \ + MG6_3_19PL & MG6_3_110PL & MG6_3_111PL & MG6_3_112PL & \ + MG6_3_113PL & MG6_3_114PL & MG6_3_115PL & MG6_3_116PL) +// End of MG6_3: +// Beginning of MG64: +#if (G6_1PL >= G6_4PL) || (G6_1PL == 0) +#define MG6_4_11PL ~(1 << 0) +#else +#define MG6_4_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_4PL) || (G6_2PL == 0) +#define MG6_4_12PL ~(1 << 1) +#else +#define MG6_4_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_4PL) || (G6_3PL == 0) +#define MG6_4_13PL ~(1 << 2) +#else +#define MG6_4_13PL 0xFFFF +#endif + +#if (G6_5PL >= G6_4PL) || (G6_5PL == 0) +#define MG6_4_15PL ~(1 << 4) +#else +#define MG6_4_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_4PL) || (G6_6PL == 0) +#define MG6_4_16PL ~(1 << 5) +#else +#define MG6_4_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_4PL) || (G6_7PL == 0) +#define MG6_4_17PL ~(1 << 6) +#else +#define MG6_4_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_4PL) || (G6_8PL == 0) +#define MG6_4_18PL ~(1 << 7) +#else +#define MG6_4_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_4PL) || (G6_9PL == 0) +#define MG6_4_19PL ~(1 << 8) +#else +#define MG6_4_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_4PL) || (G6_10PL == 0) +#define MG6_4_110PL ~(1 << 9) +#else +#define MG6_4_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_4PL) || (G6_11PL == 0) +#define MG6_4_111PL ~(1 << 10) +#else +#define MG6_4_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_4PL) || (G6_12PL == 0) +#define MG6_4_112PL ~(1 << 11) +#else +#define MG6_4_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_4PL) || (G6_13PL == 0) +#define MG6_4_113PL ~(1 << 12) +#else +#define MG6_4_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_4PL) || (G6_14PL == 0) +#define MG6_4_114PL ~(1 << 13) +#else +#define MG6_4_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_4PL) || (G6_15PL == 0) +#define MG6_4_115PL ~(1 << 14) +#else +#define MG6_4_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_4PL) || (G6_16PL == 0) +#define MG6_4_116PL ~(1 << 15) +#else +#define MG6_4_116PL 0xFFFF +#endif + +#define MG6_4_14PL 0xFFF7 +#define MG6_4 (MG6_4_11PL & MG6_4_12PL & MG6_4_13PL & MG6_4_14PL & \ + MG6_4_15PL & MG6_4_16PL & MG6_4_17PL & MG6_4_18PL & \ + MG6_4_19PL & MG6_4_110PL & MG6_4_111PL & MG6_4_112PL & \ + MG6_4_113PL & MG6_4_114PL & MG6_4_115PL & MG6_4_116PL) +// End of MG6_4: +// Beginning of MG65: +#if (G6_1PL >= G6_5PL) || (G6_1PL == 0) +#define MG6_5_11PL ~(1 << 0) +#else +#define MG6_5_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_5PL) || (G6_2PL == 0) +#define MG6_5_12PL ~(1 << 1) +#else +#define MG6_5_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_5PL) || (G6_3PL == 0) +#define MG6_5_13PL ~(1 << 2) +#else +#define MG6_5_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_5PL) || (G6_4PL == 0) +#define MG6_5_14PL ~(1 << 3) +#else +#define MG6_5_14PL 0xFFFF +#endif + +#if (G6_6PL >= G6_5PL) || (G6_6PL == 0) +#define MG6_5_16PL ~(1 << 5) +#else +#define MG6_5_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_5PL) || (G6_7PL == 0) +#define MG6_5_17PL ~(1 << 6) +#else +#define MG6_5_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_5PL) || (G6_8PL == 0) +#define MG6_5_18PL ~(1 << 7) +#else +#define MG6_5_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_5PL) || (G6_9PL == 0) +#define MG6_5_19PL ~(1 << 8) +#else +#define MG6_5_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_5PL) || (G6_10PL == 0) +#define MG6_5_110PL ~(1 << 9) +#else +#define MG6_5_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_5PL) || (G6_11PL == 0) +#define MG6_5_111PL ~(1 << 10) +#else +#define MG6_5_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_5PL) || (G6_12PL == 0) +#define MG6_5_112PL ~(1 << 11) +#else +#define MG6_5_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_5PL) || (G6_13PL == 0) +#define MG6_5_113PL ~(1 << 12) +#else +#define MG6_5_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_5PL) || (G6_14PL == 0) +#define MG6_5_114PL ~(1 << 13) +#else +#define MG6_5_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_5PL) || (G6_15PL == 0) +#define MG6_5_115PL ~(1 << 14) +#else +#define MG6_5_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_5PL) || (G6_16PL == 0) +#define MG6_5_116PL ~(1 << 15) +#else +#define MG6_5_116PL 0xFFFF +#endif + +#define MG6_5_15PL 0xFFEF +#define MG6_5 (MG6_5_11PL & MG6_5_12PL & MG6_5_13PL & MG6_5_14PL & \ + MG6_5_15PL & MG6_5_16PL & MG6_5_17PL & MG6_5_18PL & \ + MG6_5_19PL & MG6_5_110PL & MG6_5_111PL & MG6_5_112PL & \ + MG6_5_113PL & MG6_5_114PL & MG6_5_115PL & MG6_5_116PL) +// End of MG6_5: +// Beginning of MG66: +#if (G6_1PL >= G6_6PL) || (G6_1PL == 0) +#define MG6_6_11PL ~(1 << 0) +#else +#define MG6_6_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_6PL) || (G6_2PL == 0) +#define MG6_6_12PL ~(1 << 1) +#else +#define MG6_6_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_6PL) || (G6_3PL == 0) +#define MG6_6_13PL ~(1 << 2) +#else +#define MG6_6_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_6PL) || (G6_4PL == 0) +#define MG6_6_14PL ~(1 << 3) +#else +#define MG6_6_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_6PL) || (G6_5PL == 0) +#define MG6_6_15PL ~(1 << 4) +#else +#define MG6_6_15PL 0xFFFF +#endif + +#if (G6_7PL >= G6_6PL) || (G6_7PL == 0) +#define MG6_6_17PL ~(1 << 6) +#else +#define MG6_6_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_6PL) || (G6_8PL == 0) +#define MG6_6_18PL ~(1 << 7) +#else +#define MG6_6_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_6PL) || (G6_9PL == 0) +#define MG6_6_19PL ~(1 << 8) +#else +#define MG6_6_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_6PL) || (G6_10PL == 0) +#define MG6_6_110PL ~(1 << 9) +#else +#define MG6_6_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_6PL) || (G6_11PL == 0) +#define MG6_6_111PL ~(1 << 10) +#else +#define MG6_6_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_6PL) || (G6_12PL == 0) +#define MG6_6_112PL ~(1 << 11) +#else +#define MG6_6_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_6PL) || (G6_13PL == 0) +#define MG6_6_113PL ~(1 << 12) +#else +#define MG6_6_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_6PL) || (G6_14PL == 0) +#define MG6_6_114PL ~(1 << 13) +#else +#define MG6_6_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_6PL) || (G6_15PL == 0) +#define MG6_6_115PL ~(1 << 14) +#else +#define MG6_6_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_6PL) || (G6_16PL == 0) +#define MG6_6_116PL ~(1 << 15) +#else +#define MG6_6_116PL 0xFFFF +#endif + +#define MG6_6_16PL 0xFFDF +#define MG6_6 (MG6_6_11PL & MG6_6_12PL & MG6_6_13PL & MG6_6_14PL & \ + MG6_6_15PL & MG6_6_16PL & MG6_6_17PL & MG6_6_18PL & \ + MG6_6_19PL & MG6_6_110PL & MG6_6_111PL & MG6_6_112PL & \ + MG6_6_113PL & MG6_6_114PL & MG6_6_115PL & MG6_6_116PL) +// End of MG6_6: +// Beginning of MG67: +#if (G6_1PL >= G6_7PL) || (G6_1PL == 0) +#define MG6_7_11PL ~(1 << 0) +#else +#define MG6_7_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_7PL) || (G6_2PL == 0) +#define MG6_7_12PL ~(1 << 1) +#else +#define MG6_7_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_7PL) || (G6_3PL == 0) +#define MG6_7_13PL ~(1 << 2) +#else +#define MG6_7_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_7PL) || (G6_4PL == 0) +#define MG6_7_14PL ~(1 << 3) +#else +#define MG6_7_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_7PL) || (G6_5PL == 0) +#define MG6_7_15PL ~(1 << 4) +#else +#define MG6_7_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_7PL) || (G6_6PL == 0) +#define MG6_7_16PL ~(1 << 5) +#else +#define MG6_7_16PL 0xFFFF +#endif + +#if (G6_8PL >= G6_7PL) || (G6_8PL == 0) +#define MG6_7_18PL ~(1 << 7) +#else +#define MG6_7_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_7PL) || (G6_9PL == 0) +#define MG6_7_19PL ~(1 << 8) +#else +#define MG6_7_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_7PL) || (G6_10PL == 0) +#define MG6_7_110PL ~(1 << 9) +#else +#define MG6_7_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_7PL) || (G6_11PL == 0) +#define MG6_7_111PL ~(1 << 10) +#else +#define MG6_7_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_7PL) || (G6_12PL == 0) +#define MG6_7_112PL ~(1 << 11) +#else +#define MG6_7_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_7PL) || (G6_13PL == 0) +#define MG6_7_113PL ~(1 << 12) +#else +#define MG6_7_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_7PL) || (G6_14PL == 0) +#define MG6_7_114PL ~(1 << 13) +#else +#define MG6_7_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_7PL) || (G6_15PL == 0) +#define MG6_7_115PL ~(1 << 14) +#else +#define MG6_7_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_7PL) || (G6_16PL == 0) +#define MG6_7_116PL ~(1 << 15) +#else +#define MG6_7_116PL 0xFFFF +#endif + +#define MG6_7_17PL 0xFFBF +#define MG6_7 (MG6_7_11PL & MG6_7_12PL & MG6_7_13PL & MG6_7_14PL & \ + MG6_7_15PL & MG6_7_16PL & MG6_7_17PL & MG6_7_18PL & \ + MG6_7_19PL & MG6_7_110PL & MG6_7_111PL & MG6_7_112PL & \ + MG6_7_113PL & MG6_7_114PL & MG6_7_115PL & MG6_7_116PL) +// End of MG6_7: +// Beginning of MG68: +#if (G6_1PL >= G6_8PL) || (G6_1PL == 0) +#define MG6_8_11PL ~(1 << 0) +#else +#define MG6_8_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_8PL) || (G6_2PL == 0) +#define MG6_8_12PL ~(1 << 1) +#else +#define MG6_8_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_8PL) || (G6_3PL == 0) +#define MG6_8_13PL ~(1 << 2) +#else +#define MG6_8_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_8PL) || (G6_4PL == 0) +#define MG6_8_14PL ~(1 << 3) +#else +#define MG6_8_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_8PL) || (G6_5PL == 0) +#define MG6_8_15PL ~(1 << 4) +#else +#define MG6_8_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_8PL) || (G6_6PL == 0) +#define MG6_8_16PL ~(1 << 5) +#else +#define MG6_8_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_8PL) || (G6_7PL == 0) +#define MG6_8_17PL ~(1 << 6) +#else +#define MG6_8_17PL 0xFFFF +#endif + +#if (G6_9PL >= G6_8PL) || (G6_9PL == 0) +#define MG6_8_19PL ~(1 << 8) +#else +#define MG6_8_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_8PL) || (G6_10PL == 0) +#define MG6_8_110PL ~(1 << 9) +#else +#define MG6_8_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_8PL) || (G6_11PL == 0) +#define MG6_8_111PL ~(1 << 10) +#else +#define MG6_8_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_8PL) || (G6_12PL == 0) +#define MG6_8_112PL ~(1 << 11) +#else +#define MG6_8_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_8PL) || (G6_13PL == 0) +#define MG6_8_113PL ~(1 << 12) +#else +#define MG6_8_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_8PL) || (G6_14PL == 0) +#define MG6_8_114PL ~(1 << 13) +#else +#define MG6_8_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_8PL) || (G6_15PL == 0) +#define MG6_8_115PL ~(1 << 14) +#else +#define MG6_8_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_8PL) || (G6_16PL == 0) +#define MG6_8_116PL ~(1 << 15) +#else +#define MG6_8_116PL 0xFFFF +#endif + +#define MG6_8_18PL 0xFF7F +#define MG6_8 (MG6_8_11PL & MG6_8_12PL & MG6_8_13PL & MG6_8_14PL & \ + MG6_8_15PL & MG6_8_16PL & MG6_8_17PL & MG6_8_18PL & \ + MG6_8_19PL & MG6_8_110PL & MG6_8_111PL & MG6_8_112PL & \ + MG6_8_113PL & MG6_8_114PL & MG6_8_115PL & MG6_8_116PL) +// End of MG6_8: +// Beginning of MG69: +#if (G6_1PL >= G6_9PL) || (G6_1PL == 0) +#define MG6_9_11PL ~(1 << 0) +#else +#define MG6_9_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_9PL) || (G6_2PL == 0) +#define MG6_9_12PL ~(1 << 1) +#else +#define MG6_9_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_9PL) || (G6_3PL == 0) +#define MG6_9_13PL ~(1 << 2) +#else +#define MG6_9_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_9PL) || (G6_4PL == 0) +#define MG6_9_14PL ~(1 << 3) +#else +#define MG6_9_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_9PL) || (G6_5PL == 0) +#define MG6_9_15PL ~(1 << 4) +#else +#define MG6_9_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_9PL) || (G6_6PL == 0) +#define MG6_9_16PL ~(1 << 5) +#else +#define MG6_9_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_9PL) || (G6_7PL == 0) +#define MG6_9_17PL ~(1 << 6) +#else +#define MG6_9_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_9PL) || (G6_8PL == 0) +#define MG6_9_18PL ~(1 << 7) +#else +#define MG6_9_18PL 0xFFFF +#endif + +#if (G6_10PL >= G6_9PL) || (G6_10PL == 0) +#define MG6_9_110PL ~(1 << 9) +#else +#define MG6_9_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_9PL) || (G6_11PL == 0) +#define MG6_9_111PL ~(1 << 10) +#else +#define MG6_9_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_9PL) || (G6_12PL == 0) +#define MG6_9_112PL ~(1 << 11) +#else +#define MG6_9_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_9PL) || (G6_13PL == 0) +#define MG6_9_113PL ~(1 << 12) +#else +#define MG6_9_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_9PL) || (G6_14PL == 0) +#define MG6_9_114PL ~(1 << 13) +#else +#define MG6_9_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_9PL) || (G6_15PL == 0) +#define MG6_9_115PL ~(1 << 14) +#else +#define MG6_9_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_9PL) || (G6_16PL == 0) +#define MG6_9_116PL ~(1 << 15) +#else +#define MG6_9_116PL 0xFFFF +#endif + +#define MG6_9_19PL 0xFEFF +#define MG6_9 (MG6_9_11PL & MG6_9_12PL & MG6_9_13PL & MG6_9_14PL & \ + MG6_9_15PL & MG6_9_16PL & MG6_9_17PL & MG6_9_18PL & \ + MG6_9_19PL & MG6_9_110PL & MG6_9_111PL & MG6_9_112PL & \ + MG6_9_113PL & MG6_9_114PL & MG6_9_115PL & MG6_9_116PL) +// End of MG6_9: +// Beginning of MG610: +#if (G6_1PL >= G6_10PL) || (G6_1PL == 0) +#define MG6_10_11PL ~(1 << 0) +#else +#define MG6_10_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_10PL) || (G6_2PL == 0) +#define MG6_10_12PL ~(1 << 1) +#else +#define MG6_10_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_10PL) || (G6_3PL == 0) +#define MG6_10_13PL ~(1 << 2) +#else +#define MG6_10_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_10PL) || (G6_4PL == 0) +#define MG6_10_14PL ~(1 << 3) +#else +#define MG6_10_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_10PL) || (G6_5PL == 0) +#define MG6_10_15PL ~(1 << 4) +#else +#define MG6_10_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_10PL) || (G6_6PL == 0) +#define MG6_10_16PL ~(1 << 5) +#else +#define MG6_10_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_10PL) || (G6_7PL == 0) +#define MG6_10_17PL ~(1 << 6) +#else +#define MG6_10_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_10PL) || (G6_8PL == 0) +#define MG6_10_18PL ~(1 << 7) +#else +#define MG6_10_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_10PL) || (G6_9PL == 0) +#define MG6_10_19PL ~(1 << 8) +#else +#define MG6_10_19PL 0xFFFF +#endif + +#if (G6_11PL >= G6_10PL) || (G6_11PL == 0) +#define MG6_10_111PL ~(1 << 10) +#else +#define MG6_10_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_10PL) || (G6_12PL == 0) +#define MG6_10_112PL ~(1 << 11) +#else +#define MG6_10_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_10PL) || (G6_13PL == 0) +#define MG6_10_113PL ~(1 << 12) +#else +#define MG6_10_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_10PL) || (G6_14PL == 0) +#define MG6_10_114PL ~(1 << 13) +#else +#define MG6_10_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_10PL) || (G6_15PL == 0) +#define MG6_10_115PL ~(1 << 14) +#else +#define MG6_10_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_10PL) || (G6_16PL == 0) +#define MG6_10_116PL ~(1 << 15) +#else +#define MG6_10_116PL 0xFFFF +#endif + +#define MG6_10_110PL 0xFDFF +#define MG6_10 (MG6_10_11PL & MG6_10_12PL & MG6_10_13PL & MG6_10_14PL & \ + MG6_10_15PL & MG6_10_16PL & MG6_10_17PL & MG6_10_18PL & \ + MG6_10_19PL & MG6_10_110PL & MG6_10_111PL & MG6_10_112PL & \ + MG6_10_113PL & MG6_10_114PL & MG6_10_115PL & MG6_10_116PL) +// End of MG6_10: +// Beginning of MG611: +#if (G6_1PL >= G6_11PL) || (G6_1PL == 0) +#define MG6_11_11PL ~(1 << 0) +#else +#define MG6_11_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_11PL) || (G6_2PL == 0) +#define MG6_11_12PL ~(1 << 1) +#else +#define MG6_11_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_11PL) || (G6_3PL == 0) +#define MG6_11_13PL ~(1 << 2) +#else +#define MG6_11_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_11PL) || (G6_4PL == 0) +#define MG6_11_14PL ~(1 << 3) +#else +#define MG6_11_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_11PL) || (G6_5PL == 0) +#define MG6_11_15PL ~(1 << 4) +#else +#define MG6_11_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_11PL) || (G6_6PL == 0) +#define MG6_11_16PL ~(1 << 5) +#else +#define MG6_11_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_11PL) || (G6_7PL == 0) +#define MG6_11_17PL ~(1 << 6) +#else +#define MG6_11_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_11PL) || (G6_8PL == 0) +#define MG6_11_18PL ~(1 << 7) +#else +#define MG6_11_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_11PL) || (G6_9PL == 0) +#define MG6_11_19PL ~(1 << 8) +#else +#define MG6_11_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_11PL) || (G6_10PL == 0) +#define MG6_11_110PL ~(1 << 9) +#else +#define MG6_11_110PL 0xFFFF +#endif + +#if (G6_12PL >= G6_11PL) || (G6_12PL == 0) +#define MG6_11_112PL ~(1 << 11) +#else +#define MG6_11_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_11PL) || (G6_13PL == 0) +#define MG6_11_113PL ~(1 << 12) +#else +#define MG6_11_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_11PL) || (G6_14PL == 0) +#define MG6_11_114PL ~(1 << 13) +#else +#define MG6_11_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_11PL) || (G6_15PL == 0) +#define MG6_11_115PL ~(1 << 14) +#else +#define MG6_11_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_11PL) || (G6_16PL == 0) +#define MG6_11_116PL ~(1 << 15) +#else +#define MG6_11_116PL 0xFFFF +#endif + +#define MG6_11_111PL 0xFBFF +#define MG6_11 (MG6_11_11PL & MG6_11_12PL & MG6_11_13PL & MG6_11_14PL & \ + MG6_11_15PL & MG6_11_16PL & MG6_11_17PL & MG6_11_18PL & \ + MG6_11_19PL & MG6_11_110PL & MG6_11_111PL & MG6_11_112PL & \ + MG6_11_113PL & MG6_11_114PL & MG6_11_115PL & MG6_11_116PL) +// End of MG6_11: +// Beginning of MG612: +#if (G6_1PL >= G6_12PL) || (G6_1PL == 0) +#define MG6_12_11PL ~(1 << 0) +#else +#define MG6_12_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_12PL) || (G6_2PL == 0) +#define MG6_12_12PL ~(1 << 1) +#else +#define MG6_12_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_12PL) || (G6_3PL == 0) +#define MG6_12_13PL ~(1 << 2) +#else +#define MG6_12_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_12PL) || (G6_4PL == 0) +#define MG6_12_14PL ~(1 << 3) +#else +#define MG6_12_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_12PL) || (G6_5PL == 0) +#define MG6_12_15PL ~(1 << 4) +#else +#define MG6_12_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_12PL) || (G6_6PL == 0) +#define MG6_12_16PL ~(1 << 5) +#else +#define MG6_12_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_12PL) || (G6_7PL == 0) +#define MG6_12_17PL ~(1 << 6) +#else +#define MG6_12_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_12PL) || (G6_8PL == 0) +#define MG6_12_18PL ~(1 << 7) +#else +#define MG6_12_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_12PL) || (G6_9PL == 0) +#define MG6_12_19PL ~(1 << 8) +#else +#define MG6_12_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_12PL) || (G6_10PL == 0) +#define MG6_12_110PL ~(1 << 9) +#else +#define MG6_12_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_12PL) || (G6_11PL == 0) +#define MG6_12_111PL ~(1 << 10) +#else +#define MG6_12_111PL 0xFFFF +#endif + +#if (G6_13PL >= G6_12PL) || (G6_13PL == 0) +#define MG6_12_113PL ~(1 << 12) +#else +#define MG6_12_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_12PL) || (G6_14PL == 0) +#define MG6_12_114PL ~(1 << 13) +#else +#define MG6_12_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_12PL) || (G6_15PL == 0) +#define MG6_12_115PL ~(1 << 14) +#else +#define MG6_12_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_12PL) || (G6_16PL == 0) +#define MG6_12_116PL ~(1 << 15) +#else +#define MG6_12_116PL 0xFFFF +#endif + +#define MG6_12_112PL 0xF7FF +#define MG6_12 (MG6_12_11PL & MG6_12_12PL & MG6_12_13PL & MG6_12_14PL & \ + MG6_12_15PL & MG6_12_16PL & MG6_12_17PL & MG6_12_18PL & \ + MG6_12_19PL & MG6_12_110PL & MG6_12_111PL & MG6_12_112PL & \ + MG6_12_113PL & MG6_12_114PL & MG6_12_115PL & MG6_12_116PL) +// End of MG6_12: +// Beginning of MG613: +#if (G6_1PL >= G6_13PL) || (G6_1PL == 0) +#define MG6_13_11PL ~(1 << 0) +#else +#define MG6_13_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_13PL) || (G6_2PL == 0) +#define MG6_13_12PL ~(1 << 1) +#else +#define MG6_13_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_13PL) || (G6_3PL == 0) +#define MG6_13_13PL ~(1 << 2) +#else +#define MG6_13_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_13PL) || (G6_4PL == 0) +#define MG6_13_14PL ~(1 << 3) +#else +#define MG6_13_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_13PL) || (G6_5PL == 0) +#define MG6_13_15PL ~(1 << 4) +#else +#define MG6_13_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_13PL) || (G6_6PL == 0) +#define MG6_13_16PL ~(1 << 5) +#else +#define MG6_13_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_13PL) || (G6_7PL == 0) +#define MG6_13_17PL ~(1 << 6) +#else +#define MG6_13_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_13PL) || (G6_8PL == 0) +#define MG6_13_18PL ~(1 << 7) +#else +#define MG6_13_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_13PL) || (G6_9PL == 0) +#define MG6_13_19PL ~(1 << 8) +#else +#define MG6_13_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_13PL) || (G6_10PL == 0) +#define MG6_13_110PL ~(1 << 9) +#else +#define MG6_13_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_13PL) || (G6_11PL == 0) +#define MG6_13_111PL ~(1 << 10) +#else +#define MG6_13_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_13PL) || (G6_12PL == 0) +#define MG6_13_112PL ~(1 << 11) +#else +#define MG6_13_112PL 0xFFFF +#endif + +#if (G6_14PL >= G6_13PL) || (G6_14PL == 0) +#define MG6_13_114PL ~(1 << 13) +#else +#define MG6_13_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_13PL) || (G6_15PL == 0) +#define MG6_13_115PL ~(1 << 14) +#else +#define MG6_13_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_13PL) || (G6_16PL == 0) +#define MG6_13_116PL ~(1 << 15) +#else +#define MG6_13_116PL 0xFFFF +#endif + +#define MG6_13_113PL 0xEFFF +#define MG6_13 (MG6_13_11PL & MG6_13_12PL & MG6_13_13PL & MG6_13_14PL & \ + MG6_13_15PL & MG6_13_16PL & MG6_13_17PL & MG6_13_18PL & \ + MG6_13_19PL & MG6_13_110PL & MG6_13_111PL & MG6_13_112PL & \ + MG6_13_113PL & MG6_13_114PL & MG6_13_115PL & MG6_13_116PL) +// End of MG6_13: +// Beginning of MG614: +#if (G6_1PL >= G6_14PL) || (G6_1PL == 0) +#define MG6_14_11PL ~(1 << 0) +#else +#define MG6_14_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_14PL) || (G6_2PL == 0) +#define MG6_14_12PL ~(1 << 1) +#else +#define MG6_14_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_14PL) || (G6_3PL == 0) +#define MG6_14_13PL ~(1 << 2) +#else +#define MG6_14_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_14PL) || (G6_4PL == 0) +#define MG6_14_14PL ~(1 << 3) +#else +#define MG6_14_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_14PL) || (G6_5PL == 0) +#define MG6_14_15PL ~(1 << 4) +#else +#define MG6_14_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_14PL) || (G6_6PL == 0) +#define MG6_14_16PL ~(1 << 5) +#else +#define MG6_14_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_14PL) || (G6_7PL == 0) +#define MG6_14_17PL ~(1 << 6) +#else +#define MG6_14_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_14PL) || (G6_8PL == 0) +#define MG6_14_18PL ~(1 << 7) +#else +#define MG6_14_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_14PL) || (G6_9PL == 0) +#define MG6_14_19PL ~(1 << 8) +#else +#define MG6_14_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_14PL) || (G6_10PL == 0) +#define MG6_14_110PL ~(1 << 9) +#else +#define MG6_14_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_14PL) || (G6_11PL == 0) +#define MG6_14_111PL ~(1 << 10) +#else +#define MG6_14_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_14PL) || (G6_12PL == 0) +#define MG6_14_112PL ~(1 << 11) +#else +#define MG6_14_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_14PL) || (G6_13PL == 0) +#define MG6_14_113PL ~(1 << 12) +#else +#define MG6_14_113PL 0xFFFF +#endif + +#if (G6_15PL >= G6_14PL) || (G6_15PL == 0) +#define MG6_14_115PL ~(1 << 14) +#else +#define MG6_14_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_14PL) || (G6_16PL == 0) +#define MG6_14_116PL ~(1 << 15) +#else +#define MG6_14_116PL 0xFFFF +#endif + +#define MG6_14_114PL 0xDFFF +#define MG6_14 (MG6_14_11PL & MG6_14_12PL & MG6_14_13PL & MG6_14_14PL & \ + MG6_14_15PL & MG6_14_16PL & MG6_14_17PL & MG6_14_18PL & \ + MG6_14_19PL & MG6_14_110PL & MG6_14_111PL & MG6_14_112PL & \ + MG6_14_113PL & MG6_14_114PL & MG6_14_115PL & MG6_14_116PL) +// End of MG6_14: +// Beginning of MG615: +#if (G6_1PL >= G6_15PL) || (G6_1PL == 0) +#define MG6_15_11PL ~(1 << 0) +#else +#define MG6_15_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_15PL) || (G6_2PL == 0) +#define MG6_15_12PL ~(1 << 1) +#else +#define MG6_15_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_15PL) || (G6_3PL == 0) +#define MG6_15_13PL ~(1 << 2) +#else +#define MG6_15_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_15PL) || (G6_4PL == 0) +#define MG6_15_14PL ~(1 << 3) +#else +#define MG6_15_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_15PL) || (G6_5PL == 0) +#define MG6_15_15PL ~(1 << 4) +#else +#define MG6_15_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_15PL) || (G6_6PL == 0) +#define MG6_15_16PL ~(1 << 5) +#else +#define MG6_15_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_15PL) || (G6_7PL == 0) +#define MG6_15_17PL ~(1 << 6) +#else +#define MG6_15_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_15PL) || (G6_8PL == 0) +#define MG6_15_18PL ~(1 << 7) +#else +#define MG6_15_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_15PL) || (G6_9PL == 0) +#define MG6_15_19PL ~(1 << 8) +#else +#define MG6_15_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_15PL) || (G6_10PL == 0) +#define MG6_15_110PL ~(1 << 9) +#else +#define MG6_15_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_15PL) || (G6_11PL == 0) +#define MG6_15_111PL ~(1 << 10) +#else +#define MG6_15_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_15PL) || (G6_12PL == 0) +#define MG6_15_112PL ~(1 << 11) +#else +#define MG6_15_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_15PL) || (G6_13PL == 0) +#define MG6_15_113PL ~(1 << 12) +#else +#define MG6_15_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_15PL) || (G6_14PL == 0) +#define MG6_15_114PL ~(1 << 13) +#else +#define MG6_15_114PL 0xFFFF +#endif + +#if (G6_16PL >= G6_15PL) || (G6_16PL == 0) +#define MG6_15_116PL ~(1 << 15) +#else +#define MG6_15_116PL 0xFFFF +#endif + +#define MG6_15_115PL 0xBFFF +#define MG6_15 (MG6_15_11PL & MG6_15_12PL & MG6_15_13PL & MG6_15_14PL & \ + MG6_15_15PL & MG6_15_16PL & MG6_15_17PL & MG6_15_18PL & \ + MG6_15_19PL & MG6_15_110PL & MG6_15_111PL & MG6_15_112PL & \ + MG6_15_113PL & MG6_15_114PL & MG6_15_115PL & MG6_15_116PL) +// End of MG6_15: +// Beginning of MG616: +#if (G6_1PL >= G6_16PL) || (G6_1PL == 0) +#define MG6_16_11PL ~(1 << 0) +#else +#define MG6_16_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_16PL) || (G6_2PL == 0) +#define MG6_16_12PL ~(1 << 1) +#else +#define MG6_16_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_16PL) || (G6_3PL == 0) +#define MG6_16_13PL ~(1 << 2) +#else +#define MG6_16_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_16PL) || (G6_4PL == 0) +#define MG6_16_14PL ~(1 << 3) +#else +#define MG6_16_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_16PL) || (G6_5PL == 0) +#define MG6_16_15PL ~(1 << 4) +#else +#define MG6_16_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_16PL) || (G6_6PL == 0) +#define MG6_16_16PL ~(1 << 5) +#else +#define MG6_16_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_16PL) || (G6_7PL == 0) +#define MG6_16_17PL ~(1 << 6) +#else +#define MG6_16_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_16PL) || (G6_8PL == 0) +#define MG6_16_18PL ~(1 << 7) +#else +#define MG6_16_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_16PL) || (G6_9PL == 0) +#define MG6_16_19PL ~(1 << 8) +#else +#define MG6_16_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_16PL) || (G6_10PL == 0) +#define MG6_16_110PL ~(1 << 9) +#else +#define MG6_16_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_16PL) || (G6_11PL == 0) +#define MG6_16_111PL ~(1 << 10) +#else +#define MG6_16_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_16PL) || (G6_12PL == 0) +#define MG6_16_112PL ~(1 << 11) +#else +#define MG6_16_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_16PL) || (G6_13PL == 0) +#define MG6_16_113PL ~(1 << 12) +#else +#define MG6_16_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_16PL) || (G6_14PL == 0) +#define MG6_16_114PL ~(1 << 13) +#else +#define MG6_16_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_16PL) || (G6_15PL == 0) +#define MG6_16_115PL ~(1 << 14) +#else +#define MG6_16_115PL 0xFFFF +#endif + +#define MG6_16_116PL 0x7FFF +#define MG6_16 (MG6_16_11PL & MG6_16_12PL & MG6_16_13PL & MG6_16_14PL & \ + MG6_16_15PL & MG6_16_16PL & MG6_16_17PL & MG6_16_18PL & \ + MG6_16_19PL & MG6_16_110PL & MG6_16_111PL & MG6_16_112PL & \ + MG6_16_113PL & MG6_16_114PL & MG6_16_115PL & MG6_16_116PL) +// End of MG6_16: + + +// +// Automatically generate PIEIER7 interrupt masks MG71 to MG716: +// + +// Beginning of MG71: +#if (G7_2PL >= G7_1PL) || (G7_2PL == 0) +#define MG7_1_12PL ~(1 << 1) +#else +#define MG7_1_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_1PL) || (G7_3PL == 0) +#define MG7_1_13PL ~(1 << 2) +#else +#define MG7_1_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_1PL) || (G7_4PL == 0) +#define MG7_1_14PL ~(1 << 3) +#else +#define MG7_1_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_1PL) || (G7_5PL == 0) +#define MG7_1_15PL ~(1 << 4) +#else +#define MG7_1_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_1PL) || (G7_6PL == 0) +#define MG7_1_16PL ~(1 << 5) +#else +#define MG7_1_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_1PL) || (G7_7PL == 0) +#define MG7_1_17PL ~(1 << 6) +#else +#define MG7_1_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_1PL) || (G7_8PL == 0) +#define MG7_1_18PL ~(1 << 7) +#else +#define MG7_1_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_1PL) || (G7_9PL == 0) +#define MG7_1_19PL ~(1 << 8) +#else +#define MG7_1_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_1PL) || (G7_10PL == 0) +#define MG7_1_110PL ~(1 << 9) +#else +#define MG7_1_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_1PL) || (G7_11PL == 0) +#define MG7_1_111PL ~(1 << 10) +#else +#define MG7_1_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_1PL) || (G7_12PL == 0) +#define MG7_1_112PL ~(1 << 11) +#else +#define MG7_1_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_1PL) || (G7_13PL == 0) +#define MG7_1_113PL ~(1 << 12) +#else +#define MG7_1_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_1PL) || (G7_14PL == 0) +#define MG7_1_114PL ~(1 << 13) +#else +#define MG7_1_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_1PL) || (G7_15PL == 0) +#define MG7_1_115PL ~(1 << 14) +#else +#define MG7_1_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_1PL) || (G7_16PL == 0) +#define MG7_1_116PL ~(1 << 15) +#else +#define MG7_1_116PL 0xFFFF +#endif + +#define MG7_1_11PL 0xFFFE +#define MG7_1 (MG7_1_11PL & MG7_1_12PL & MG7_1_13PL & MG7_1_14PL & \ + MG7_1_15PL & MG7_1_16PL & MG7_1_17PL & MG7_1_18PL & \ + MG7_1_19PL & MG7_1_110PL & MG7_1_111PL & MG7_1_112PL & \ + MG7_1_113PL & MG7_1_114PL & MG7_1_115PL & MG7_1_116PL) +// End of MG7_1: +// Beginning of MG72: +#if (G7_1PL >= G7_2PL) || (G7_1PL == 0) +#define MG7_2_11PL ~(1 << 0) +#else +#define MG7_2_11PL 0xFFFF +#endif + +#if (G7_3PL >= G7_2PL) || (G7_3PL == 0) +#define MG7_2_13PL ~(1 << 2) +#else +#define MG7_2_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_2PL) || (G7_4PL == 0) +#define MG7_2_14PL ~(1 << 3) +#else +#define MG7_2_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_2PL) || (G7_5PL == 0) +#define MG7_2_15PL ~(1 << 4) +#else +#define MG7_2_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_2PL) || (G7_6PL == 0) +#define MG7_2_16PL ~(1 << 5) +#else +#define MG7_2_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_2PL) || (G7_7PL == 0) +#define MG7_2_17PL ~(1 << 6) +#else +#define MG7_2_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_2PL) || (G7_8PL == 0) +#define MG7_2_18PL ~(1 << 7) +#else +#define MG7_2_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_2PL) || (G7_9PL == 0) +#define MG7_2_19PL ~(1 << 8) +#else +#define MG7_2_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_2PL) || (G7_10PL == 0) +#define MG7_2_110PL ~(1 << 9) +#else +#define MG7_2_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_2PL) || (G7_11PL == 0) +#define MG7_2_111PL ~(1 << 10) +#else +#define MG7_2_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_2PL) || (G7_12PL == 0) +#define MG7_2_112PL ~(1 << 11) +#else +#define MG7_2_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_2PL) || (G7_13PL == 0) +#define MG7_2_113PL ~(1 << 12) +#else +#define MG7_2_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_2PL) || (G7_14PL == 0) +#define MG7_2_114PL ~(1 << 13) +#else +#define MG7_2_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_2PL) || (G7_15PL == 0) +#define MG7_2_115PL ~(1 << 14) +#else +#define MG7_2_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_2PL) || (G7_16PL == 0) +#define MG7_2_116PL ~(1 << 15) +#else +#define MG7_2_116PL 0xFFFF +#endif + +#define MG7_2_12PL 0xFFFD +#define MG7_2 (MG7_2_11PL & MG7_2_12PL & MG7_2_13PL & MG7_2_14PL & \ + MG7_2_15PL & MG7_2_16PL & MG7_2_17PL & MG7_2_18PL & \ + MG7_2_19PL & MG7_2_110PL & MG7_2_111PL & MG7_2_112PL & \ + MG7_2_113PL & MG7_2_114PL & MG7_2_115PL & MG7_2_116PL) +// End of MG7_2: +// Beginning of MG73: +#if (G7_1PL >= G7_3PL) || (G7_1PL == 0) +#define MG7_3_11PL ~(1 << 0) +#else +#define MG7_3_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_3PL) || (G7_2PL == 0) +#define MG7_3_12PL ~(1 << 1) +#else +#define MG7_3_12PL 0xFFFF +#endif + +#if (G7_4PL >= G7_3PL) || (G7_4PL == 0) +#define MG7_3_14PL ~(1 << 3) +#else +#define MG7_3_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_3PL) || (G7_5PL == 0) +#define MG7_3_15PL ~(1 << 4) +#else +#define MG7_3_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_3PL) || (G7_6PL == 0) +#define MG7_3_16PL ~(1 << 5) +#else +#define MG7_3_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_3PL) || (G7_7PL == 0) +#define MG7_3_17PL ~(1 << 6) +#else +#define MG7_3_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_3PL) || (G7_8PL == 0) +#define MG7_3_18PL ~(1 << 7) +#else +#define MG7_3_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_3PL) || (G7_9PL == 0) +#define MG7_3_19PL ~(1 << 8) +#else +#define MG7_3_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_3PL) || (G7_10PL == 0) +#define MG7_3_110PL ~(1 << 9) +#else +#define MG7_3_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_3PL) || (G7_11PL == 0) +#define MG7_3_111PL ~(1 << 10) +#else +#define MG7_3_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_3PL) || (G7_12PL == 0) +#define MG7_3_112PL ~(1 << 11) +#else +#define MG7_3_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_3PL) || (G7_13PL == 0) +#define MG7_3_113PL ~(1 << 12) +#else +#define MG7_3_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_3PL) || (G7_14PL == 0) +#define MG7_3_114PL ~(1 << 13) +#else +#define MG7_3_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_3PL) || (G7_15PL == 0) +#define MG7_3_115PL ~(1 << 14) +#else +#define MG7_3_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_3PL) || (G7_16PL == 0) +#define MG7_3_116PL ~(1 << 15) +#else +#define MG7_3_116PL 0xFFFF +#endif + +#define MG7_3_13PL 0xFFFB +#define MG7_3 (MG7_3_11PL & MG7_3_12PL & MG7_3_13PL & MG7_3_14PL & \ + MG7_3_15PL & MG7_3_16PL & MG7_3_17PL & MG7_3_18PL & \ + MG7_3_19PL & MG7_3_110PL & MG7_3_111PL & MG7_3_112PL & \ + MG7_3_113PL & MG7_3_114PL & MG7_3_115PL & MG7_3_116PL) +// End of MG7_3: +// Beginning of MG74: +#if (G7_1PL >= G7_4PL) || (G7_1PL == 0) +#define MG7_4_11PL ~(1 << 0) +#else +#define MG7_4_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_4PL) || (G7_2PL == 0) +#define MG7_4_12PL ~(1 << 1) +#else +#define MG7_4_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_4PL) || (G7_3PL == 0) +#define MG7_4_13PL ~(1 << 2) +#else +#define MG7_4_13PL 0xFFFF +#endif + +#if (G7_5PL >= G7_4PL) || (G7_5PL == 0) +#define MG7_4_15PL ~(1 << 4) +#else +#define MG7_4_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_4PL) || (G7_6PL == 0) +#define MG7_4_16PL ~(1 << 5) +#else +#define MG7_4_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_4PL) || (G7_7PL == 0) +#define MG7_4_17PL ~(1 << 6) +#else +#define MG7_4_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_4PL) || (G7_8PL == 0) +#define MG7_4_18PL ~(1 << 7) +#else +#define MG7_4_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_4PL) || (G7_9PL == 0) +#define MG7_4_19PL ~(1 << 8) +#else +#define MG7_4_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_4PL) || (G7_10PL == 0) +#define MG7_4_110PL ~(1 << 9) +#else +#define MG7_4_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_4PL) || (G7_11PL == 0) +#define MG7_4_111PL ~(1 << 10) +#else +#define MG7_4_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_4PL) || (G7_12PL == 0) +#define MG7_4_112PL ~(1 << 11) +#else +#define MG7_4_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_4PL) || (G7_13PL == 0) +#define MG7_4_113PL ~(1 << 12) +#else +#define MG7_4_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_4PL) || (G7_14PL == 0) +#define MG7_4_114PL ~(1 << 13) +#else +#define MG7_4_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_4PL) || (G7_15PL == 0) +#define MG7_4_115PL ~(1 << 14) +#else +#define MG7_4_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_4PL) || (G7_16PL == 0) +#define MG7_4_116PL ~(1 << 15) +#else +#define MG7_4_116PL 0xFFFF +#endif + +#define MG7_4_14PL 0xFFF7 +#define MG7_4 (MG7_4_11PL & MG7_4_12PL & MG7_4_13PL & MG7_4_14PL & \ + MG7_4_15PL & MG7_4_16PL & MG7_4_17PL & MG7_4_18PL & \ + MG7_4_19PL & MG7_4_110PL & MG7_4_111PL & MG7_4_112PL & \ + MG7_4_113PL & MG7_4_114PL & MG7_4_115PL & MG7_4_116PL) +// End of MG7_4: +// Beginning of MG75: +#if (G7_1PL >= G7_5PL) || (G7_1PL == 0) +#define MG7_5_11PL ~(1 << 0) +#else +#define MG7_5_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_5PL) || (G7_2PL == 0) +#define MG7_5_12PL ~(1 << 1) +#else +#define MG7_5_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_5PL) || (G7_3PL == 0) +#define MG7_5_13PL ~(1 << 2) +#else +#define MG7_5_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_5PL) || (G7_4PL == 0) +#define MG7_5_14PL ~(1 << 3) +#else +#define MG7_5_14PL 0xFFFF +#endif + +#if (G7_6PL >= G7_5PL) || (G7_6PL == 0) +#define MG7_5_16PL ~(1 << 5) +#else +#define MG7_5_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_5PL) || (G7_7PL == 0) +#define MG7_5_17PL ~(1 << 6) +#else +#define MG7_5_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_5PL) || (G7_8PL == 0) +#define MG7_5_18PL ~(1 << 7) +#else +#define MG7_5_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_5PL) || (G7_9PL == 0) +#define MG7_5_19PL ~(1 << 8) +#else +#define MG7_5_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_5PL) || (G7_10PL == 0) +#define MG7_5_110PL ~(1 << 9) +#else +#define MG7_5_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_5PL) || (G7_11PL == 0) +#define MG7_5_111PL ~(1 << 10) +#else +#define MG7_5_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_5PL) || (G7_12PL == 0) +#define MG7_5_112PL ~(1 << 11) +#else +#define MG7_5_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_5PL) || (G7_13PL == 0) +#define MG7_5_113PL ~(1 << 12) +#else +#define MG7_5_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_5PL) || (G7_14PL == 0) +#define MG7_5_114PL ~(1 << 13) +#else +#define MG7_5_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_5PL) || (G7_15PL == 0) +#define MG7_5_115PL ~(1 << 14) +#else +#define MG7_5_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_5PL) || (G7_16PL == 0) +#define MG7_5_116PL ~(1 << 15) +#else +#define MG7_5_116PL 0xFFFF +#endif + +#define MG7_5_15PL 0xFFEF +#define MG7_5 (MG7_5_11PL & MG7_5_12PL & MG7_5_13PL & MG7_5_14PL & \ + MG7_5_15PL & MG7_5_16PL & MG7_5_17PL & MG7_5_18PL & \ + MG7_5_19PL & MG7_5_110PL & MG7_5_111PL & MG7_5_112PL & \ + MG7_5_113PL & MG7_5_114PL & MG7_5_115PL & MG7_5_116PL) +// End of MG7_5: +// Beginning of MG76: +#if (G7_1PL >= G7_6PL) || (G7_1PL == 0) +#define MG7_6_11PL ~(1 << 0) +#else +#define MG7_6_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_6PL) || (G7_2PL == 0) +#define MG7_6_12PL ~(1 << 1) +#else +#define MG7_6_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_6PL) || (G7_3PL == 0) +#define MG7_6_13PL ~(1 << 2) +#else +#define MG7_6_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_6PL) || (G7_4PL == 0) +#define MG7_6_14PL ~(1 << 3) +#else +#define MG7_6_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_6PL) || (G7_5PL == 0) +#define MG7_6_15PL ~(1 << 4) +#else +#define MG7_6_15PL 0xFFFF +#endif + +#if (G7_7PL >= G7_6PL) || (G7_7PL == 0) +#define MG7_6_17PL ~(1 << 6) +#else +#define MG7_6_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_6PL) || (G7_8PL == 0) +#define MG7_6_18PL ~(1 << 7) +#else +#define MG7_6_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_6PL) || (G7_9PL == 0) +#define MG7_6_19PL ~(1 << 8) +#else +#define MG7_6_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_6PL) || (G7_10PL == 0) +#define MG7_6_110PL ~(1 << 9) +#else +#define MG7_6_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_6PL) || (G7_11PL == 0) +#define MG7_6_111PL ~(1 << 10) +#else +#define MG7_6_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_6PL) || (G7_12PL == 0) +#define MG7_6_112PL ~(1 << 11) +#else +#define MG7_6_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_6PL) || (G7_13PL == 0) +#define MG7_6_113PL ~(1 << 12) +#else +#define MG7_6_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_6PL) || (G7_14PL == 0) +#define MG7_6_114PL ~(1 << 13) +#else +#define MG7_6_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_6PL) || (G7_15PL == 0) +#define MG7_6_115PL ~(1 << 14) +#else +#define MG7_6_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_6PL) || (G7_16PL == 0) +#define MG7_6_116PL ~(1 << 15) +#else +#define MG7_6_116PL 0xFFFF +#endif + +#define MG7_6_16PL 0xFFDF +#define MG7_6 (MG7_6_11PL & MG7_6_12PL & MG7_6_13PL & MG7_6_14PL & \ + MG7_6_15PL & MG7_6_16PL & MG7_6_17PL & MG7_6_18PL & \ + MG7_6_19PL & MG7_6_110PL & MG7_6_111PL & MG7_6_112PL & \ + MG7_6_113PL & MG7_6_114PL & MG7_6_115PL & MG7_6_116PL) +// End of MG7_6: +// Beginning of MG77: +#if (G7_1PL >= G7_7PL) || (G7_1PL == 0) +#define MG7_7_11PL ~(1 << 0) +#else +#define MG7_7_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_7PL) || (G7_2PL == 0) +#define MG7_7_12PL ~(1 << 1) +#else +#define MG7_7_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_7PL) || (G7_3PL == 0) +#define MG7_7_13PL ~(1 << 2) +#else +#define MG7_7_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_7PL) || (G7_4PL == 0) +#define MG7_7_14PL ~(1 << 3) +#else +#define MG7_7_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_7PL) || (G7_5PL == 0) +#define MG7_7_15PL ~(1 << 4) +#else +#define MG7_7_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_7PL) || (G7_6PL == 0) +#define MG7_7_16PL ~(1 << 5) +#else +#define MG7_7_16PL 0xFFFF +#endif + +#if (G7_8PL >= G7_7PL) || (G7_8PL == 0) +#define MG7_7_18PL ~(1 << 7) +#else +#define MG7_7_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_7PL) || (G7_9PL == 0) +#define MG7_7_19PL ~(1 << 8) +#else +#define MG7_7_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_7PL) || (G7_10PL == 0) +#define MG7_7_110PL ~(1 << 9) +#else +#define MG7_7_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_7PL) || (G7_11PL == 0) +#define MG7_7_111PL ~(1 << 10) +#else +#define MG7_7_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_7PL) || (G7_12PL == 0) +#define MG7_7_112PL ~(1 << 11) +#else +#define MG7_7_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_7PL) || (G7_13PL == 0) +#define MG7_7_113PL ~(1 << 12) +#else +#define MG7_7_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_7PL) || (G7_14PL == 0) +#define MG7_7_114PL ~(1 << 13) +#else +#define MG7_7_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_7PL) || (G7_15PL == 0) +#define MG7_7_115PL ~(1 << 14) +#else +#define MG7_7_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_7PL) || (G7_16PL == 0) +#define MG7_7_116PL ~(1 << 15) +#else +#define MG7_7_116PL 0xFFFF +#endif + +#define MG7_7_17PL 0xFFBF +#define MG7_7 (MG7_7_11PL & MG7_7_12PL & MG7_7_13PL & MG7_7_14PL & \ + MG7_7_15PL & MG7_7_16PL & MG7_7_17PL & MG7_7_18PL & \ + MG7_7_19PL & MG7_7_110PL & MG7_7_111PL & MG7_7_112PL & \ + MG7_7_113PL & MG7_7_114PL & MG7_7_115PL & MG7_7_116PL) +// End of MG7_7: +// Beginning of MG78: +#if (G7_1PL >= G7_8PL) || (G7_1PL == 0) +#define MG7_8_11PL ~(1 << 0) +#else +#define MG7_8_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_8PL) || (G7_2PL == 0) +#define MG7_8_12PL ~(1 << 1) +#else +#define MG7_8_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_8PL) || (G7_3PL == 0) +#define MG7_8_13PL ~(1 << 2) +#else +#define MG7_8_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_8PL) || (G7_4PL == 0) +#define MG7_8_14PL ~(1 << 3) +#else +#define MG7_8_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_8PL) || (G7_5PL == 0) +#define MG7_8_15PL ~(1 << 4) +#else +#define MG7_8_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_8PL) || (G7_6PL == 0) +#define MG7_8_16PL ~(1 << 5) +#else +#define MG7_8_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_8PL) || (G7_7PL == 0) +#define MG7_8_17PL ~(1 << 6) +#else +#define MG7_8_17PL 0xFFFF +#endif + +#if (G7_9PL >= G7_8PL) || (G7_9PL == 0) +#define MG7_8_19PL ~(1 << 8) +#else +#define MG7_8_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_8PL) || (G7_10PL == 0) +#define MG7_8_110PL ~(1 << 9) +#else +#define MG7_8_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_8PL) || (G7_11PL == 0) +#define MG7_8_111PL ~(1 << 10) +#else +#define MG7_8_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_8PL) || (G7_12PL == 0) +#define MG7_8_112PL ~(1 << 11) +#else +#define MG7_8_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_8PL) || (G7_13PL == 0) +#define MG7_8_113PL ~(1 << 12) +#else +#define MG7_8_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_8PL) || (G7_14PL == 0) +#define MG7_8_114PL ~(1 << 13) +#else +#define MG7_8_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_8PL) || (G7_15PL == 0) +#define MG7_8_115PL ~(1 << 14) +#else +#define MG7_8_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_8PL) || (G7_16PL == 0) +#define MG7_8_116PL ~(1 << 15) +#else +#define MG7_8_116PL 0xFFFF +#endif + +#define MG7_8_18PL 0xFF7F +#define MG7_8 (MG7_8_11PL & MG7_8_12PL & MG7_8_13PL & MG7_8_14PL & \ + MG7_8_15PL & MG7_8_16PL & MG7_8_17PL & MG7_8_18PL & \ + MG7_8_19PL & MG7_8_110PL & MG7_8_111PL & MG7_8_112PL & \ + MG7_8_113PL & MG7_8_114PL & MG7_8_115PL & MG7_8_116PL) +// End of MG7_8: +// Beginning of MG79: +#if (G7_1PL >= G7_9PL) || (G7_1PL == 0) +#define MG7_9_11PL ~(1 << 0) +#else +#define MG7_9_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_9PL) || (G7_2PL == 0) +#define MG7_9_12PL ~(1 << 1) +#else +#define MG7_9_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_9PL) || (G7_3PL == 0) +#define MG7_9_13PL ~(1 << 2) +#else +#define MG7_9_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_9PL) || (G7_4PL == 0) +#define MG7_9_14PL ~(1 << 3) +#else +#define MG7_9_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_9PL) || (G7_5PL == 0) +#define MG7_9_15PL ~(1 << 4) +#else +#define MG7_9_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_9PL) || (G7_6PL == 0) +#define MG7_9_16PL ~(1 << 5) +#else +#define MG7_9_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_9PL) || (G7_7PL == 0) +#define MG7_9_17PL ~(1 << 6) +#else +#define MG7_9_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_9PL) || (G7_8PL == 0) +#define MG7_9_18PL ~(1 << 7) +#else +#define MG7_9_18PL 0xFFFF +#endif + +#if (G7_10PL >= G7_9PL) || (G7_10PL == 0) +#define MG7_9_110PL ~(1 << 9) +#else +#define MG7_9_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_9PL) || (G7_11PL == 0) +#define MG7_9_111PL ~(1 << 10) +#else +#define MG7_9_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_9PL) || (G7_12PL == 0) +#define MG7_9_112PL ~(1 << 11) +#else +#define MG7_9_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_9PL) || (G7_13PL == 0) +#define MG7_9_113PL ~(1 << 12) +#else +#define MG7_9_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_9PL) || (G7_14PL == 0) +#define MG7_9_114PL ~(1 << 13) +#else +#define MG7_9_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_9PL) || (G7_15PL == 0) +#define MG7_9_115PL ~(1 << 14) +#else +#define MG7_9_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_9PL) || (G7_16PL == 0) +#define MG7_9_116PL ~(1 << 15) +#else +#define MG7_9_116PL 0xFFFF +#endif + +#define MG7_9_19PL 0xFEFF +#define MG7_9 (MG7_9_11PL & MG7_9_12PL & MG7_9_13PL & MG7_9_14PL & \ + MG7_9_15PL & MG7_9_16PL & MG7_9_17PL & MG7_9_18PL & \ + MG7_9_19PL & MG7_9_110PL & MG7_9_111PL & MG7_9_112PL & \ + MG7_9_113PL & MG7_9_114PL & MG7_9_115PL & MG7_9_116PL) +// End of MG7_9: +// Beginning of MG710: +#if (G7_1PL >= G7_10PL) || (G7_1PL == 0) +#define MG7_10_11PL ~(1 << 0) +#else +#define MG7_10_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_10PL) || (G7_2PL == 0) +#define MG7_10_12PL ~(1 << 1) +#else +#define MG7_10_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_10PL) || (G7_3PL == 0) +#define MG7_10_13PL ~(1 << 2) +#else +#define MG7_10_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_10PL) || (G7_4PL == 0) +#define MG7_10_14PL ~(1 << 3) +#else +#define MG7_10_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_10PL) || (G7_5PL == 0) +#define MG7_10_15PL ~(1 << 4) +#else +#define MG7_10_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_10PL) || (G7_6PL == 0) +#define MG7_10_16PL ~(1 << 5) +#else +#define MG7_10_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_10PL) || (G7_7PL == 0) +#define MG7_10_17PL ~(1 << 6) +#else +#define MG7_10_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_10PL) || (G7_8PL == 0) +#define MG7_10_18PL ~(1 << 7) +#else +#define MG7_10_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_10PL) || (G7_9PL == 0) +#define MG7_10_19PL ~(1 << 8) +#else +#define MG7_10_19PL 0xFFFF +#endif + +#if (G7_11PL >= G7_10PL) || (G7_11PL == 0) +#define MG7_10_111PL ~(1 << 10) +#else +#define MG7_10_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_10PL) || (G7_12PL == 0) +#define MG7_10_112PL ~(1 << 11) +#else +#define MG7_10_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_10PL) || (G7_13PL == 0) +#define MG7_10_113PL ~(1 << 12) +#else +#define MG7_10_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_10PL) || (G7_14PL == 0) +#define MG7_10_114PL ~(1 << 13) +#else +#define MG7_10_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_10PL) || (G7_15PL == 0) +#define MG7_10_115PL ~(1 << 14) +#else +#define MG7_10_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_10PL) || (G7_16PL == 0) +#define MG7_10_116PL ~(1 << 15) +#else +#define MG7_10_116PL 0xFFFF +#endif + +#define MG7_10_110PL 0xFDFF +#define MG7_10 (MG7_10_11PL & MG7_10_12PL & MG7_10_13PL & MG7_10_14PL & \ + MG7_10_15PL & MG7_10_16PL & MG7_10_17PL & MG7_10_18PL & \ + MG7_10_19PL & MG7_10_110PL & MG7_10_111PL & MG7_10_112PL & \ + MG7_10_113PL & MG7_10_114PL & MG7_10_115PL & MG7_10_116PL) +// End of MG7_10: +// Beginning of MG711: +#if (G7_1PL >= G7_11PL) || (G7_1PL == 0) +#define MG7_11_11PL ~(1 << 0) +#else +#define MG7_11_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_11PL) || (G7_2PL == 0) +#define MG7_11_12PL ~(1 << 1) +#else +#define MG7_11_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_11PL) || (G7_3PL == 0) +#define MG7_11_13PL ~(1 << 2) +#else +#define MG7_11_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_11PL) || (G7_4PL == 0) +#define MG7_11_14PL ~(1 << 3) +#else +#define MG7_11_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_11PL) || (G7_5PL == 0) +#define MG7_11_15PL ~(1 << 4) +#else +#define MG7_11_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_11PL) || (G7_6PL == 0) +#define MG7_11_16PL ~(1 << 5) +#else +#define MG7_11_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_11PL) || (G7_7PL == 0) +#define MG7_11_17PL ~(1 << 6) +#else +#define MG7_11_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_11PL) || (G7_8PL == 0) +#define MG7_11_18PL ~(1 << 7) +#else +#define MG7_11_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_11PL) || (G7_9PL == 0) +#define MG7_11_19PL ~(1 << 8) +#else +#define MG7_11_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_11PL) || (G7_10PL == 0) +#define MG7_11_110PL ~(1 << 9) +#else +#define MG7_11_110PL 0xFFFF +#endif + +#if (G7_12PL >= G7_11PL) || (G7_12PL == 0) +#define MG7_11_112PL ~(1 << 11) +#else +#define MG7_11_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_11PL) || (G7_13PL == 0) +#define MG7_11_113PL ~(1 << 12) +#else +#define MG7_11_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_11PL) || (G7_14PL == 0) +#define MG7_11_114PL ~(1 << 13) +#else +#define MG7_11_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_11PL) || (G7_15PL == 0) +#define MG7_11_115PL ~(1 << 14) +#else +#define MG7_11_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_11PL) || (G7_16PL == 0) +#define MG7_11_116PL ~(1 << 15) +#else +#define MG7_11_116PL 0xFFFF +#endif + +#define MG7_11_111PL 0xFBFF +#define MG7_11 (MG7_11_11PL & MG7_11_12PL & MG7_11_13PL & MG7_11_14PL & \ + MG7_11_15PL & MG7_11_16PL & MG7_11_17PL & MG7_11_18PL & \ + MG7_11_19PL & MG7_11_110PL & MG7_11_111PL & MG7_11_112PL & \ + MG7_11_113PL & MG7_11_114PL & MG7_11_115PL & MG7_11_116PL) +// End of MG7_11: +// Beginning of MG712: +#if (G7_1PL >= G7_12PL) || (G7_1PL == 0) +#define MG7_12_11PL ~(1 << 0) +#else +#define MG7_12_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_12PL) || (G7_2PL == 0) +#define MG7_12_12PL ~(1 << 1) +#else +#define MG7_12_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_12PL) || (G7_3PL == 0) +#define MG7_12_13PL ~(1 << 2) +#else +#define MG7_12_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_12PL) || (G7_4PL == 0) +#define MG7_12_14PL ~(1 << 3) +#else +#define MG7_12_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_12PL) || (G7_5PL == 0) +#define MG7_12_15PL ~(1 << 4) +#else +#define MG7_12_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_12PL) || (G7_6PL == 0) +#define MG7_12_16PL ~(1 << 5) +#else +#define MG7_12_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_12PL) || (G7_7PL == 0) +#define MG7_12_17PL ~(1 << 6) +#else +#define MG7_12_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_12PL) || (G7_8PL == 0) +#define MG7_12_18PL ~(1 << 7) +#else +#define MG7_12_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_12PL) || (G7_9PL == 0) +#define MG7_12_19PL ~(1 << 8) +#else +#define MG7_12_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_12PL) || (G7_10PL == 0) +#define MG7_12_110PL ~(1 << 9) +#else +#define MG7_12_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_12PL) || (G7_11PL == 0) +#define MG7_12_111PL ~(1 << 10) +#else +#define MG7_12_111PL 0xFFFF +#endif + +#if (G7_13PL >= G7_12PL) || (G7_13PL == 0) +#define MG7_12_113PL ~(1 << 12) +#else +#define MG7_12_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_12PL) || (G7_14PL == 0) +#define MG7_12_114PL ~(1 << 13) +#else +#define MG7_12_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_12PL) || (G7_15PL == 0) +#define MG7_12_115PL ~(1 << 14) +#else +#define MG7_12_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_12PL) || (G7_16PL == 0) +#define MG7_12_116PL ~(1 << 15) +#else +#define MG7_12_116PL 0xFFFF +#endif + +#define MG7_12_112PL 0xF7FF +#define MG7_12 (MG7_12_11PL & MG7_12_12PL & MG7_12_13PL & MG7_12_14PL & \ + MG7_12_15PL & MG7_12_16PL & MG7_12_17PL & MG7_12_18PL & \ + MG7_12_19PL & MG7_12_110PL & MG7_12_111PL & MG7_12_112PL & \ + MG7_12_113PL & MG7_12_114PL & MG7_12_115PL & MG7_12_116PL) +// End of MG7_12: +// Beginning of MG713: +#if (G7_1PL >= G7_13PL) || (G7_1PL == 0) +#define MG7_13_11PL ~(1 << 0) +#else +#define MG7_13_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_13PL) || (G7_2PL == 0) +#define MG7_13_12PL ~(1 << 1) +#else +#define MG7_13_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_13PL) || (G7_3PL == 0) +#define MG7_13_13PL ~(1 << 2) +#else +#define MG7_13_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_13PL) || (G7_4PL == 0) +#define MG7_13_14PL ~(1 << 3) +#else +#define MG7_13_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_13PL) || (G7_5PL == 0) +#define MG7_13_15PL ~(1 << 4) +#else +#define MG7_13_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_13PL) || (G7_6PL == 0) +#define MG7_13_16PL ~(1 << 5) +#else +#define MG7_13_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_13PL) || (G7_7PL == 0) +#define MG7_13_17PL ~(1 << 6) +#else +#define MG7_13_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_13PL) || (G7_8PL == 0) +#define MG7_13_18PL ~(1 << 7) +#else +#define MG7_13_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_13PL) || (G7_9PL == 0) +#define MG7_13_19PL ~(1 << 8) +#else +#define MG7_13_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_13PL) || (G7_10PL == 0) +#define MG7_13_110PL ~(1 << 9) +#else +#define MG7_13_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_13PL) || (G7_11PL == 0) +#define MG7_13_111PL ~(1 << 10) +#else +#define MG7_13_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_13PL) || (G7_12PL == 0) +#define MG7_13_112PL ~(1 << 11) +#else +#define MG7_13_112PL 0xFFFF +#endif + +#if (G7_14PL >= G7_13PL) || (G7_14PL == 0) +#define MG7_13_114PL ~(1 << 13) +#else +#define MG7_13_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_13PL) || (G7_15PL == 0) +#define MG7_13_115PL ~(1 << 14) +#else +#define MG7_13_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_13PL) || (G7_16PL == 0) +#define MG7_13_116PL ~(1 << 15) +#else +#define MG7_13_116PL 0xFFFF +#endif + +#define MG7_13_113PL 0xEFFF +#define MG7_13 (MG7_13_11PL & MG7_13_12PL & MG7_13_13PL & MG7_13_14PL & \ + MG7_13_15PL & MG7_13_16PL & MG7_13_17PL & MG7_13_18PL & \ + MG7_13_19PL & MG7_13_110PL & MG7_13_111PL & MG7_13_112PL & \ + MG7_13_113PL & MG7_13_114PL & MG7_13_115PL & MG7_13_116PL) +// End of MG7_13: +// Beginning of MG714: +#if (G7_1PL >= G7_14PL) || (G7_1PL == 0) +#define MG7_14_11PL ~(1 << 0) +#else +#define MG7_14_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_14PL) || (G7_2PL == 0) +#define MG7_14_12PL ~(1 << 1) +#else +#define MG7_14_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_14PL) || (G7_3PL == 0) +#define MG7_14_13PL ~(1 << 2) +#else +#define MG7_14_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_14PL) || (G7_4PL == 0) +#define MG7_14_14PL ~(1 << 3) +#else +#define MG7_14_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_14PL) || (G7_5PL == 0) +#define MG7_14_15PL ~(1 << 4) +#else +#define MG7_14_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_14PL) || (G7_6PL == 0) +#define MG7_14_16PL ~(1 << 5) +#else +#define MG7_14_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_14PL) || (G7_7PL == 0) +#define MG7_14_17PL ~(1 << 6) +#else +#define MG7_14_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_14PL) || (G7_8PL == 0) +#define MG7_14_18PL ~(1 << 7) +#else +#define MG7_14_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_14PL) || (G7_9PL == 0) +#define MG7_14_19PL ~(1 << 8) +#else +#define MG7_14_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_14PL) || (G7_10PL == 0) +#define MG7_14_110PL ~(1 << 9) +#else +#define MG7_14_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_14PL) || (G7_11PL == 0) +#define MG7_14_111PL ~(1 << 10) +#else +#define MG7_14_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_14PL) || (G7_12PL == 0) +#define MG7_14_112PL ~(1 << 11) +#else +#define MG7_14_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_14PL) || (G7_13PL == 0) +#define MG7_14_113PL ~(1 << 12) +#else +#define MG7_14_113PL 0xFFFF +#endif + +#if (G7_15PL >= G7_14PL) || (G7_15PL == 0) +#define MG7_14_115PL ~(1 << 14) +#else +#define MG7_14_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_14PL) || (G7_16PL == 0) +#define MG7_14_116PL ~(1 << 15) +#else +#define MG7_14_116PL 0xFFFF +#endif + +#define MG7_14_114PL 0xDFFF +#define MG7_14 (MG7_14_11PL & MG7_14_12PL & MG7_14_13PL & MG7_14_14PL & \ + MG7_14_15PL & MG7_14_16PL & MG7_14_17PL & MG7_14_18PL & \ + MG7_14_19PL & MG7_14_110PL & MG7_14_111PL & MG7_14_112PL & \ + MG7_14_113PL & MG7_14_114PL & MG7_14_115PL & MG7_14_116PL) +// End of MG7_14: +// Beginning of MG715: +#if (G7_1PL >= G7_15PL) || (G7_1PL == 0) +#define MG7_15_11PL ~(1 << 0) +#else +#define MG7_15_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_15PL) || (G7_2PL == 0) +#define MG7_15_12PL ~(1 << 1) +#else +#define MG7_15_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_15PL) || (G7_3PL == 0) +#define MG7_15_13PL ~(1 << 2) +#else +#define MG7_15_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_15PL) || (G7_4PL == 0) +#define MG7_15_14PL ~(1 << 3) +#else +#define MG7_15_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_15PL) || (G7_5PL == 0) +#define MG7_15_15PL ~(1 << 4) +#else +#define MG7_15_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_15PL) || (G7_6PL == 0) +#define MG7_15_16PL ~(1 << 5) +#else +#define MG7_15_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_15PL) || (G7_7PL == 0) +#define MG7_15_17PL ~(1 << 6) +#else +#define MG7_15_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_15PL) || (G7_8PL == 0) +#define MG7_15_18PL ~(1 << 7) +#else +#define MG7_15_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_15PL) || (G7_9PL == 0) +#define MG7_15_19PL ~(1 << 8) +#else +#define MG7_15_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_15PL) || (G7_10PL == 0) +#define MG7_15_110PL ~(1 << 9) +#else +#define MG7_15_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_15PL) || (G7_11PL == 0) +#define MG7_15_111PL ~(1 << 10) +#else +#define MG7_15_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_15PL) || (G7_12PL == 0) +#define MG7_15_112PL ~(1 << 11) +#else +#define MG7_15_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_15PL) || (G7_13PL == 0) +#define MG7_15_113PL ~(1 << 12) +#else +#define MG7_15_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_15PL) || (G7_14PL == 0) +#define MG7_15_114PL ~(1 << 13) +#else +#define MG7_15_114PL 0xFFFF +#endif + +#if (G7_16PL >= G7_15PL) || (G7_16PL == 0) +#define MG7_15_116PL ~(1 << 15) +#else +#define MG7_15_116PL 0xFFFF +#endif + +#define MG7_15_115PL 0xBFFF +#define MG7_15 (MG7_15_11PL & MG7_15_12PL & MG7_15_13PL & MG7_15_14PL & \ + MG7_15_15PL & MG7_15_16PL & MG7_15_17PL & MG7_15_18PL & \ + MG7_15_19PL & MG7_15_110PL & MG7_15_111PL & MG7_15_112PL & \ + MG7_15_113PL & MG7_15_114PL & MG7_15_115PL & MG7_15_116PL) +// End of MG7_15: +// Beginning of MG716: +#if (G7_1PL >= G7_16PL) || (G7_1PL == 0) +#define MG7_16_11PL ~(1 << 0) +#else +#define MG7_16_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_16PL) || (G7_2PL == 0) +#define MG7_16_12PL ~(1 << 1) +#else +#define MG7_16_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_16PL) || (G7_3PL == 0) +#define MG7_16_13PL ~(1 << 2) +#else +#define MG7_16_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_16PL) || (G7_4PL == 0) +#define MG7_16_14PL ~(1 << 3) +#else +#define MG7_16_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_16PL) || (G7_5PL == 0) +#define MG7_16_15PL ~(1 << 4) +#else +#define MG7_16_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_16PL) || (G7_6PL == 0) +#define MG7_16_16PL ~(1 << 5) +#else +#define MG7_16_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_16PL) || (G7_7PL == 0) +#define MG7_16_17PL ~(1 << 6) +#else +#define MG7_16_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_16PL) || (G7_8PL == 0) +#define MG7_16_18PL ~(1 << 7) +#else +#define MG7_16_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_16PL) || (G7_9PL == 0) +#define MG7_16_19PL ~(1 << 8) +#else +#define MG7_16_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_16PL) || (G7_10PL == 0) +#define MG7_16_110PL ~(1 << 9) +#else +#define MG7_16_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_16PL) || (G7_11PL == 0) +#define MG7_16_111PL ~(1 << 10) +#else +#define MG7_16_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_16PL) || (G7_12PL == 0) +#define MG7_16_112PL ~(1 << 11) +#else +#define MG7_16_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_16PL) || (G7_13PL == 0) +#define MG7_16_113PL ~(1 << 12) +#else +#define MG7_16_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_16PL) || (G7_14PL == 0) +#define MG7_16_114PL ~(1 << 13) +#else +#define MG7_16_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_16PL) || (G7_15PL == 0) +#define MG7_16_115PL ~(1 << 14) +#else +#define MG7_16_115PL 0xFFFF +#endif + +#define MG7_16_116PL 0x7FFF +#define MG7_16 (MG7_16_11PL & MG7_16_12PL & MG7_16_13PL & MG7_16_14PL & \ + MG7_16_15PL & MG7_16_16PL & MG7_16_17PL & MG7_16_18PL & \ + MG7_16_19PL & MG7_16_110PL & MG7_16_111PL & MG7_16_112PL & \ + MG7_16_113PL & MG7_16_114PL & MG7_16_115PL & MG7_16_116PL) +// End of MG7_16: + + +// +// Automatically generate PIEIER8 interrupt masks MG81 to MG816: +// + +// Beginning of MG81: +#if (G8_2PL >= G8_1PL) || (G8_2PL == 0) +#define MG8_1_12PL ~(1 << 1) +#else +#define MG8_1_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_1PL) || (G8_3PL == 0) +#define MG8_1_13PL ~(1 << 2) +#else +#define MG8_1_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_1PL) || (G8_4PL == 0) +#define MG8_1_14PL ~(1 << 3) +#else +#define MG8_1_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_1PL) || (G8_5PL == 0) +#define MG8_1_15PL ~(1 << 4) +#else +#define MG8_1_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_1PL) || (G8_6PL == 0) +#define MG8_1_16PL ~(1 << 5) +#else +#define MG8_1_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_1PL) || (G8_7PL == 0) +#define MG8_1_17PL ~(1 << 6) +#else +#define MG8_1_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_1PL) || (G8_8PL == 0) +#define MG8_1_18PL ~(1 << 7) +#else +#define MG8_1_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_1PL) || (G8_9PL == 0) +#define MG8_1_19PL ~(1 << 8) +#else +#define MG8_1_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_1PL) || (G8_10PL == 0) +#define MG8_1_110PL ~(1 << 9) +#else +#define MG8_1_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_1PL) || (G8_11PL == 0) +#define MG8_1_111PL ~(1 << 10) +#else +#define MG8_1_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_1PL) || (G8_12PL == 0) +#define MG8_1_112PL ~(1 << 11) +#else +#define MG8_1_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_1PL) || (G8_13PL == 0) +#define MG8_1_113PL ~(1 << 12) +#else +#define MG8_1_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_1PL) || (G8_14PL == 0) +#define MG8_1_114PL ~(1 << 13) +#else +#define MG8_1_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_1PL) || (G8_15PL == 0) +#define MG8_1_115PL ~(1 << 14) +#else +#define MG8_1_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_1PL) || (G8_16PL == 0) +#define MG8_1_116PL ~(1 << 15) +#else +#define MG8_1_116PL 0xFFFF +#endif + +#define MG8_1_11PL 0xFFFE +#define MG8_1 (MG8_1_11PL & MG8_1_12PL & MG8_1_13PL & MG8_1_14PL & \ + MG8_1_15PL & MG8_1_16PL & MG8_1_17PL & MG8_1_18PL & \ + MG8_1_19PL & MG8_1_110PL & MG8_1_111PL & MG8_1_112PL & \ + MG8_1_113PL & MG8_1_114PL & MG8_1_115PL & MG8_1_116PL) +// End of MG8_1: +// Beginning of MG82: +#if (G8_1PL >= G8_2PL) || (G8_1PL == 0) +#define MG8_2_11PL ~(1 << 0) +#else +#define MG8_2_11PL 0xFFFF +#endif + +#if (G8_3PL >= G8_2PL) || (G8_3PL == 0) +#define MG8_2_13PL ~(1 << 2) +#else +#define MG8_2_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_2PL) || (G8_4PL == 0) +#define MG8_2_14PL ~(1 << 3) +#else +#define MG8_2_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_2PL) || (G8_5PL == 0) +#define MG8_2_15PL ~(1 << 4) +#else +#define MG8_2_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_2PL) || (G8_6PL == 0) +#define MG8_2_16PL ~(1 << 5) +#else +#define MG8_2_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_2PL) || (G8_7PL == 0) +#define MG8_2_17PL ~(1 << 6) +#else +#define MG8_2_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_2PL) || (G8_8PL == 0) +#define MG8_2_18PL ~(1 << 7) +#else +#define MG8_2_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_2PL) || (G8_9PL == 0) +#define MG8_2_19PL ~(1 << 8) +#else +#define MG8_2_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_2PL) || (G8_10PL == 0) +#define MG8_2_110PL ~(1 << 9) +#else +#define MG8_2_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_2PL) || (G8_11PL == 0) +#define MG8_2_111PL ~(1 << 10) +#else +#define MG8_2_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_2PL) || (G8_12PL == 0) +#define MG8_2_112PL ~(1 << 11) +#else +#define MG8_2_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_2PL) || (G8_13PL == 0) +#define MG8_2_113PL ~(1 << 12) +#else +#define MG8_2_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_2PL) || (G8_14PL == 0) +#define MG8_2_114PL ~(1 << 13) +#else +#define MG8_2_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_2PL) || (G8_15PL == 0) +#define MG8_2_115PL ~(1 << 14) +#else +#define MG8_2_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_2PL) || (G8_16PL == 0) +#define MG8_2_116PL ~(1 << 15) +#else +#define MG8_2_116PL 0xFFFF +#endif + +#define MG8_2_12PL 0xFFFD +#define MG8_2 (MG8_2_11PL & MG8_2_12PL & MG8_2_13PL & MG8_2_14PL & \ + MG8_2_15PL & MG8_2_16PL & MG8_2_17PL & MG8_2_18PL & \ + MG8_2_19PL & MG8_2_110PL & MG8_2_111PL & MG8_2_112PL & \ + MG8_2_113PL & MG8_2_114PL & MG8_2_115PL & MG8_2_116PL) +// End of MG8_2: +// Beginning of MG83: +#if (G8_1PL >= G8_3PL) || (G8_1PL == 0) +#define MG8_3_11PL ~(1 << 0) +#else +#define MG8_3_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_3PL) || (G8_2PL == 0) +#define MG8_3_12PL ~(1 << 1) +#else +#define MG8_3_12PL 0xFFFF +#endif + +#if (G8_4PL >= G8_3PL) || (G8_4PL == 0) +#define MG8_3_14PL ~(1 << 3) +#else +#define MG8_3_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_3PL) || (G8_5PL == 0) +#define MG8_3_15PL ~(1 << 4) +#else +#define MG8_3_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_3PL) || (G8_6PL == 0) +#define MG8_3_16PL ~(1 << 5) +#else +#define MG8_3_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_3PL) || (G8_7PL == 0) +#define MG8_3_17PL ~(1 << 6) +#else +#define MG8_3_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_3PL) || (G8_8PL == 0) +#define MG8_3_18PL ~(1 << 7) +#else +#define MG8_3_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_3PL) || (G8_9PL == 0) +#define MG8_3_19PL ~(1 << 8) +#else +#define MG8_3_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_3PL) || (G8_10PL == 0) +#define MG8_3_110PL ~(1 << 9) +#else +#define MG8_3_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_3PL) || (G8_11PL == 0) +#define MG8_3_111PL ~(1 << 10) +#else +#define MG8_3_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_3PL) || (G8_12PL == 0) +#define MG8_3_112PL ~(1 << 11) +#else +#define MG8_3_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_3PL) || (G8_13PL == 0) +#define MG8_3_113PL ~(1 << 12) +#else +#define MG8_3_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_3PL) || (G8_14PL == 0) +#define MG8_3_114PL ~(1 << 13) +#else +#define MG8_3_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_3PL) || (G8_15PL == 0) +#define MG8_3_115PL ~(1 << 14) +#else +#define MG8_3_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_3PL) || (G8_16PL == 0) +#define MG8_3_116PL ~(1 << 15) +#else +#define MG8_3_116PL 0xFFFF +#endif + +#define MG8_3_13PL 0xFFFB +#define MG8_3 (MG8_3_11PL & MG8_3_12PL & MG8_3_13PL & MG8_3_14PL & \ + MG8_3_15PL & MG8_3_16PL & MG8_3_17PL & MG8_3_18PL & \ + MG8_3_19PL & MG8_3_110PL & MG8_3_111PL & MG8_3_112PL & \ + MG8_3_113PL & MG8_3_114PL & MG8_3_115PL & MG8_3_116PL) +// End of MG8_3: +// Beginning of MG84: +#if (G8_1PL >= G8_4PL) || (G8_1PL == 0) +#define MG8_4_11PL ~(1 << 0) +#else +#define MG8_4_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_4PL) || (G8_2PL == 0) +#define MG8_4_12PL ~(1 << 1) +#else +#define MG8_4_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_4PL) || (G8_3PL == 0) +#define MG8_4_13PL ~(1 << 2) +#else +#define MG8_4_13PL 0xFFFF +#endif + +#if (G8_5PL >= G8_4PL) || (G8_5PL == 0) +#define MG8_4_15PL ~(1 << 4) +#else +#define MG8_4_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_4PL) || (G8_6PL == 0) +#define MG8_4_16PL ~(1 << 5) +#else +#define MG8_4_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_4PL) || (G8_7PL == 0) +#define MG8_4_17PL ~(1 << 6) +#else +#define MG8_4_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_4PL) || (G8_8PL == 0) +#define MG8_4_18PL ~(1 << 7) +#else +#define MG8_4_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_4PL) || (G8_9PL == 0) +#define MG8_4_19PL ~(1 << 8) +#else +#define MG8_4_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_4PL) || (G8_10PL == 0) +#define MG8_4_110PL ~(1 << 9) +#else +#define MG8_4_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_4PL) || (G8_11PL == 0) +#define MG8_4_111PL ~(1 << 10) +#else +#define MG8_4_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_4PL) || (G8_12PL == 0) +#define MG8_4_112PL ~(1 << 11) +#else +#define MG8_4_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_4PL) || (G8_13PL == 0) +#define MG8_4_113PL ~(1 << 12) +#else +#define MG8_4_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_4PL) || (G8_14PL == 0) +#define MG8_4_114PL ~(1 << 13) +#else +#define MG8_4_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_4PL) || (G8_15PL == 0) +#define MG8_4_115PL ~(1 << 14) +#else +#define MG8_4_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_4PL) || (G8_16PL == 0) +#define MG8_4_116PL ~(1 << 15) +#else +#define MG8_4_116PL 0xFFFF +#endif + +#define MG8_4_14PL 0xFFF7 +#define MG8_4 (MG8_4_11PL & MG8_4_12PL & MG8_4_13PL & MG8_4_14PL & \ + MG8_4_15PL & MG8_4_16PL & MG8_4_17PL & MG8_4_18PL & \ + MG8_4_19PL & MG8_4_110PL & MG8_4_111PL & MG8_4_112PL & \ + MG8_4_113PL & MG8_4_114PL & MG8_4_115PL & MG8_4_116PL) +// End of MG8_4: +// Beginning of MG85: +#if (G8_1PL >= G8_5PL) || (G8_1PL == 0) +#define MG8_5_11PL ~(1 << 0) +#else +#define MG8_5_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_5PL) || (G8_2PL == 0) +#define MG8_5_12PL ~(1 << 1) +#else +#define MG8_5_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_5PL) || (G8_3PL == 0) +#define MG8_5_13PL ~(1 << 2) +#else +#define MG8_5_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_5PL) || (G8_4PL == 0) +#define MG8_5_14PL ~(1 << 3) +#else +#define MG8_5_14PL 0xFFFF +#endif + +#if (G8_6PL >= G8_5PL) || (G8_6PL == 0) +#define MG8_5_16PL ~(1 << 5) +#else +#define MG8_5_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_5PL) || (G8_7PL == 0) +#define MG8_5_17PL ~(1 << 6) +#else +#define MG8_5_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_5PL) || (G8_8PL == 0) +#define MG8_5_18PL ~(1 << 7) +#else +#define MG8_5_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_5PL) || (G8_9PL == 0) +#define MG8_5_19PL ~(1 << 8) +#else +#define MG8_5_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_5PL) || (G8_10PL == 0) +#define MG8_5_110PL ~(1 << 9) +#else +#define MG8_5_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_5PL) || (G8_11PL == 0) +#define MG8_5_111PL ~(1 << 10) +#else +#define MG8_5_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_5PL) || (G8_12PL == 0) +#define MG8_5_112PL ~(1 << 11) +#else +#define MG8_5_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_5PL) || (G8_13PL == 0) +#define MG8_5_113PL ~(1 << 12) +#else +#define MG8_5_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_5PL) || (G8_14PL == 0) +#define MG8_5_114PL ~(1 << 13) +#else +#define MG8_5_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_5PL) || (G8_15PL == 0) +#define MG8_5_115PL ~(1 << 14) +#else +#define MG8_5_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_5PL) || (G8_16PL == 0) +#define MG8_5_116PL ~(1 << 15) +#else +#define MG8_5_116PL 0xFFFF +#endif + +#define MG8_5_15PL 0xFFEF +#define MG8_5 (MG8_5_11PL & MG8_5_12PL & MG8_5_13PL & MG8_5_14PL & \ + MG8_5_15PL & MG8_5_16PL & MG8_5_17PL & MG8_5_18PL & \ + MG8_5_19PL & MG8_5_110PL & MG8_5_111PL & MG8_5_112PL & \ + MG8_5_113PL & MG8_5_114PL & MG8_5_115PL & MG8_5_116PL) +// End of MG8_5: +// Beginning of MG86: +#if (G8_1PL >= G8_6PL) || (G8_1PL == 0) +#define MG8_6_11PL ~(1 << 0) +#else +#define MG8_6_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_6PL) || (G8_2PL == 0) +#define MG8_6_12PL ~(1 << 1) +#else +#define MG8_6_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_6PL) || (G8_3PL == 0) +#define MG8_6_13PL ~(1 << 2) +#else +#define MG8_6_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_6PL) || (G8_4PL == 0) +#define MG8_6_14PL ~(1 << 3) +#else +#define MG8_6_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_6PL) || (G8_5PL == 0) +#define MG8_6_15PL ~(1 << 4) +#else +#define MG8_6_15PL 0xFFFF +#endif + +#if (G8_7PL >= G8_6PL) || (G8_7PL == 0) +#define MG8_6_17PL ~(1 << 6) +#else +#define MG8_6_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_6PL) || (G8_8PL == 0) +#define MG8_6_18PL ~(1 << 7) +#else +#define MG8_6_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_6PL) || (G8_9PL == 0) +#define MG8_6_19PL ~(1 << 8) +#else +#define MG8_6_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_6PL) || (G8_10PL == 0) +#define MG8_6_110PL ~(1 << 9) +#else +#define MG8_6_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_6PL) || (G8_11PL == 0) +#define MG8_6_111PL ~(1 << 10) +#else +#define MG8_6_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_6PL) || (G8_12PL == 0) +#define MG8_6_112PL ~(1 << 11) +#else +#define MG8_6_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_6PL) || (G8_13PL == 0) +#define MG8_6_113PL ~(1 << 12) +#else +#define MG8_6_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_6PL) || (G8_14PL == 0) +#define MG8_6_114PL ~(1 << 13) +#else +#define MG8_6_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_6PL) || (G8_15PL == 0) +#define MG8_6_115PL ~(1 << 14) +#else +#define MG8_6_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_6PL) || (G8_16PL == 0) +#define MG8_6_116PL ~(1 << 15) +#else +#define MG8_6_116PL 0xFFFF +#endif + +#define MG8_6_16PL 0xFFDF +#define MG8_6 (MG8_6_11PL & MG8_6_12PL & MG8_6_13PL & MG8_6_14PL & \ + MG8_6_15PL & MG8_6_16PL & MG8_6_17PL & MG8_6_18PL & \ + MG8_6_19PL & MG8_6_110PL & MG8_6_111PL & MG8_6_112PL & \ + MG8_6_113PL & MG8_6_114PL & MG8_6_115PL & MG8_6_116PL) +// End of MG8_6: +// Beginning of MG87: +#if (G8_1PL >= G8_7PL) || (G8_1PL == 0) +#define MG8_7_11PL ~(1 << 0) +#else +#define MG8_7_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_7PL) || (G8_2PL == 0) +#define MG8_7_12PL ~(1 << 1) +#else +#define MG8_7_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_7PL) || (G8_3PL == 0) +#define MG8_7_13PL ~(1 << 2) +#else +#define MG8_7_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_7PL) || (G8_4PL == 0) +#define MG8_7_14PL ~(1 << 3) +#else +#define MG8_7_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_7PL) || (G8_5PL == 0) +#define MG8_7_15PL ~(1 << 4) +#else +#define MG8_7_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_7PL) || (G8_6PL == 0) +#define MG8_7_16PL ~(1 << 5) +#else +#define MG8_7_16PL 0xFFFF +#endif + +#if (G8_8PL >= G8_7PL) || (G8_8PL == 0) +#define MG8_7_18PL ~(1 << 7) +#else +#define MG8_7_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_7PL) || (G8_9PL == 0) +#define MG8_7_19PL ~(1 << 8) +#else +#define MG8_7_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_7PL) || (G8_10PL == 0) +#define MG8_7_110PL ~(1 << 9) +#else +#define MG8_7_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_7PL) || (G8_11PL == 0) +#define MG8_7_111PL ~(1 << 10) +#else +#define MG8_7_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_7PL) || (G8_12PL == 0) +#define MG8_7_112PL ~(1 << 11) +#else +#define MG8_7_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_7PL) || (G8_13PL == 0) +#define MG8_7_113PL ~(1 << 12) +#else +#define MG8_7_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_7PL) || (G8_14PL == 0) +#define MG8_7_114PL ~(1 << 13) +#else +#define MG8_7_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_7PL) || (G8_15PL == 0) +#define MG8_7_115PL ~(1 << 14) +#else +#define MG8_7_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_7PL) || (G8_16PL == 0) +#define MG8_7_116PL ~(1 << 15) +#else +#define MG8_7_116PL 0xFFFF +#endif + +#define MG8_7_17PL 0xFFBF +#define MG8_7 (MG8_7_11PL & MG8_7_12PL & MG8_7_13PL & MG8_7_14PL & \ + MG8_7_15PL & MG8_7_16PL & MG8_7_17PL & MG8_7_18PL & \ + MG8_7_19PL & MG8_7_110PL & MG8_7_111PL & MG8_7_112PL & \ + MG8_7_113PL & MG8_7_114PL & MG8_7_115PL & MG8_7_116PL) +// End of MG8_7: +// Beginning of MG88: +#if (G8_1PL >= G8_8PL) || (G8_1PL == 0) +#define MG8_8_11PL ~(1 << 0) +#else +#define MG8_8_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_8PL) || (G8_2PL == 0) +#define MG8_8_12PL ~(1 << 1) +#else +#define MG8_8_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_8PL) || (G8_3PL == 0) +#define MG8_8_13PL ~(1 << 2) +#else +#define MG8_8_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_8PL) || (G8_4PL == 0) +#define MG8_8_14PL ~(1 << 3) +#else +#define MG8_8_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_8PL) || (G8_5PL == 0) +#define MG8_8_15PL ~(1 << 4) +#else +#define MG8_8_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_8PL) || (G8_6PL == 0) +#define MG8_8_16PL ~(1 << 5) +#else +#define MG8_8_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_8PL) || (G8_7PL == 0) +#define MG8_8_17PL ~(1 << 6) +#else +#define MG8_8_17PL 0xFFFF +#endif + +#if (G8_9PL >= G8_8PL) || (G8_9PL == 0) +#define MG8_8_19PL ~(1 << 8) +#else +#define MG8_8_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_8PL) || (G8_10PL == 0) +#define MG8_8_110PL ~(1 << 9) +#else +#define MG8_8_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_8PL) || (G8_11PL == 0) +#define MG8_8_111PL ~(1 << 10) +#else +#define MG8_8_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_8PL) || (G8_12PL == 0) +#define MG8_8_112PL ~(1 << 11) +#else +#define MG8_8_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_8PL) || (G8_13PL == 0) +#define MG8_8_113PL ~(1 << 12) +#else +#define MG8_8_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_8PL) || (G8_14PL == 0) +#define MG8_8_114PL ~(1 << 13) +#else +#define MG8_8_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_8PL) || (G8_15PL == 0) +#define MG8_8_115PL ~(1 << 14) +#else +#define MG8_8_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_8PL) || (G8_16PL == 0) +#define MG8_8_116PL ~(1 << 15) +#else +#define MG8_8_116PL 0xFFFF +#endif + +#define MG8_8_18PL 0xFF7F +#define MG8_8 (MG8_8_11PL & MG8_8_12PL & MG8_8_13PL & MG8_8_14PL & \ + MG8_8_15PL & MG8_8_16PL & MG8_8_17PL & MG8_8_18PL & \ + MG8_8_19PL & MG8_8_110PL & MG8_8_111PL & MG8_8_112PL & \ + MG8_8_113PL & MG8_8_114PL & MG8_8_115PL & MG8_8_116PL) +// End of MG8_8: +// Beginning of MG89: +#if (G8_1PL >= G8_9PL) || (G8_1PL == 0) +#define MG8_9_11PL ~(1 << 0) +#else +#define MG8_9_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_9PL) || (G8_2PL == 0) +#define MG8_9_12PL ~(1 << 1) +#else +#define MG8_9_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_9PL) || (G8_3PL == 0) +#define MG8_9_13PL ~(1 << 2) +#else +#define MG8_9_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_9PL) || (G8_4PL == 0) +#define MG8_9_14PL ~(1 << 3) +#else +#define MG8_9_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_9PL) || (G8_5PL == 0) +#define MG8_9_15PL ~(1 << 4) +#else +#define MG8_9_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_9PL) || (G8_6PL == 0) +#define MG8_9_16PL ~(1 << 5) +#else +#define MG8_9_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_9PL) || (G8_7PL == 0) +#define MG8_9_17PL ~(1 << 6) +#else +#define MG8_9_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_9PL) || (G8_8PL == 0) +#define MG8_9_18PL ~(1 << 7) +#else +#define MG8_9_18PL 0xFFFF +#endif + +#if (G8_10PL >= G8_9PL) || (G8_10PL == 0) +#define MG8_9_110PL ~(1 << 9) +#else +#define MG8_9_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_9PL) || (G8_11PL == 0) +#define MG8_9_111PL ~(1 << 10) +#else +#define MG8_9_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_9PL) || (G8_12PL == 0) +#define MG8_9_112PL ~(1 << 11) +#else +#define MG8_9_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_9PL) || (G8_13PL == 0) +#define MG8_9_113PL ~(1 << 12) +#else +#define MG8_9_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_9PL) || (G8_14PL == 0) +#define MG8_9_114PL ~(1 << 13) +#else +#define MG8_9_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_9PL) || (G8_15PL == 0) +#define MG8_9_115PL ~(1 << 14) +#else +#define MG8_9_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_9PL) || (G8_16PL == 0) +#define MG8_9_116PL ~(1 << 15) +#else +#define MG8_9_116PL 0xFFFF +#endif + +#define MG8_9_19PL 0xFEFF +#define MG8_9 (MG8_9_11PL & MG8_9_12PL & MG8_9_13PL & MG8_9_14PL & \ + MG8_9_15PL & MG8_9_16PL & MG8_9_17PL & MG8_9_18PL & \ + MG8_9_19PL & MG8_9_110PL & MG8_9_111PL & MG8_9_112PL & \ + MG8_9_113PL & MG8_9_114PL & MG8_9_115PL & MG8_9_116PL) +// End of MG8_9: +// Beginning of MG810: +#if (G8_1PL >= G8_10PL) || (G8_1PL == 0) +#define MG8_10_11PL ~(1 << 0) +#else +#define MG8_10_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_10PL) || (G8_2PL == 0) +#define MG8_10_12PL ~(1 << 1) +#else +#define MG8_10_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_10PL) || (G8_3PL == 0) +#define MG8_10_13PL ~(1 << 2) +#else +#define MG8_10_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_10PL) || (G8_4PL == 0) +#define MG8_10_14PL ~(1 << 3) +#else +#define MG8_10_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_10PL) || (G8_5PL == 0) +#define MG8_10_15PL ~(1 << 4) +#else +#define MG8_10_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_10PL) || (G8_6PL == 0) +#define MG8_10_16PL ~(1 << 5) +#else +#define MG8_10_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_10PL) || (G8_7PL == 0) +#define MG8_10_17PL ~(1 << 6) +#else +#define MG8_10_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_10PL) || (G8_8PL == 0) +#define MG8_10_18PL ~(1 << 7) +#else +#define MG8_10_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_10PL) || (G8_9PL == 0) +#define MG8_10_19PL ~(1 << 8) +#else +#define MG8_10_19PL 0xFFFF +#endif + +#if (G8_11PL >= G8_10PL) || (G8_11PL == 0) +#define MG8_10_111PL ~(1 << 10) +#else +#define MG8_10_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_10PL) || (G8_12PL == 0) +#define MG8_10_112PL ~(1 << 11) +#else +#define MG8_10_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_10PL) || (G8_13PL == 0) +#define MG8_10_113PL ~(1 << 12) +#else +#define MG8_10_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_10PL) || (G8_14PL == 0) +#define MG8_10_114PL ~(1 << 13) +#else +#define MG8_10_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_10PL) || (G8_15PL == 0) +#define MG8_10_115PL ~(1 << 14) +#else +#define MG8_10_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_10PL) || (G8_16PL == 0) +#define MG8_10_116PL ~(1 << 15) +#else +#define MG8_10_116PL 0xFFFF +#endif + +#define MG8_10_110PL 0xFDFF +#define MG8_10 (MG8_10_11PL & MG8_10_12PL & MG8_10_13PL & MG8_10_14PL & \ + MG8_10_15PL & MG8_10_16PL & MG8_10_17PL & MG8_10_18PL & \ + MG8_10_19PL & MG8_10_110PL & MG8_10_111PL & MG8_10_112PL & \ + MG8_10_113PL & MG8_10_114PL & MG8_10_115PL & MG8_10_116PL) +// End of MG8_10: +// Beginning of MG811: +#if (G8_1PL >= G8_11PL) || (G8_1PL == 0) +#define MG8_11_11PL ~(1 << 0) +#else +#define MG8_11_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_11PL) || (G8_2PL == 0) +#define MG8_11_12PL ~(1 << 1) +#else +#define MG8_11_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_11PL) || (G8_3PL == 0) +#define MG8_11_13PL ~(1 << 2) +#else +#define MG8_11_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_11PL) || (G8_4PL == 0) +#define MG8_11_14PL ~(1 << 3) +#else +#define MG8_11_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_11PL) || (G8_5PL == 0) +#define MG8_11_15PL ~(1 << 4) +#else +#define MG8_11_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_11PL) || (G8_6PL == 0) +#define MG8_11_16PL ~(1 << 5) +#else +#define MG8_11_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_11PL) || (G8_7PL == 0) +#define MG8_11_17PL ~(1 << 6) +#else +#define MG8_11_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_11PL) || (G8_8PL == 0) +#define MG8_11_18PL ~(1 << 7) +#else +#define MG8_11_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_11PL) || (G8_9PL == 0) +#define MG8_11_19PL ~(1 << 8) +#else +#define MG8_11_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_11PL) || (G8_10PL == 0) +#define MG8_11_110PL ~(1 << 9) +#else +#define MG8_11_110PL 0xFFFF +#endif + +#if (G8_12PL >= G8_11PL) || (G8_12PL == 0) +#define MG8_11_112PL ~(1 << 11) +#else +#define MG8_11_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_11PL) || (G8_13PL == 0) +#define MG8_11_113PL ~(1 << 12) +#else +#define MG8_11_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_11PL) || (G8_14PL == 0) +#define MG8_11_114PL ~(1 << 13) +#else +#define MG8_11_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_11PL) || (G8_15PL == 0) +#define MG8_11_115PL ~(1 << 14) +#else +#define MG8_11_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_11PL) || (G8_16PL == 0) +#define MG8_11_116PL ~(1 << 15) +#else +#define MG8_11_116PL 0xFFFF +#endif + +#define MG8_11_111PL 0xFBFF +#define MG8_11 (MG8_11_11PL & MG8_11_12PL & MG8_11_13PL & MG8_11_14PL & \ + MG8_11_15PL & MG8_11_16PL & MG8_11_17PL & MG8_11_18PL & \ + MG8_11_19PL & MG8_11_110PL & MG8_11_111PL & MG8_11_112PL & \ + MG8_11_113PL & MG8_11_114PL & MG8_11_115PL & MG8_11_116PL) +// End of MG8_11: +// Beginning of MG812: +#if (G8_1PL >= G8_12PL) || (G8_1PL == 0) +#define MG8_12_11PL ~(1 << 0) +#else +#define MG8_12_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_12PL) || (G8_2PL == 0) +#define MG8_12_12PL ~(1 << 1) +#else +#define MG8_12_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_12PL) || (G8_3PL == 0) +#define MG8_12_13PL ~(1 << 2) +#else +#define MG8_12_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_12PL) || (G8_4PL == 0) +#define MG8_12_14PL ~(1 << 3) +#else +#define MG8_12_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_12PL) || (G8_5PL == 0) +#define MG8_12_15PL ~(1 << 4) +#else +#define MG8_12_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_12PL) || (G8_6PL == 0) +#define MG8_12_16PL ~(1 << 5) +#else +#define MG8_12_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_12PL) || (G8_7PL == 0) +#define MG8_12_17PL ~(1 << 6) +#else +#define MG8_12_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_12PL) || (G8_8PL == 0) +#define MG8_12_18PL ~(1 << 7) +#else +#define MG8_12_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_12PL) || (G8_9PL == 0) +#define MG8_12_19PL ~(1 << 8) +#else +#define MG8_12_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_12PL) || (G8_10PL == 0) +#define MG8_12_110PL ~(1 << 9) +#else +#define MG8_12_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_12PL) || (G8_11PL == 0) +#define MG8_12_111PL ~(1 << 10) +#else +#define MG8_12_111PL 0xFFFF +#endif + +#if (G8_13PL >= G8_12PL) || (G8_13PL == 0) +#define MG8_12_113PL ~(1 << 12) +#else +#define MG8_12_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_12PL) || (G8_14PL == 0) +#define MG8_12_114PL ~(1 << 13) +#else +#define MG8_12_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_12PL) || (G8_15PL == 0) +#define MG8_12_115PL ~(1 << 14) +#else +#define MG8_12_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_12PL) || (G8_16PL == 0) +#define MG8_12_116PL ~(1 << 15) +#else +#define MG8_12_116PL 0xFFFF +#endif + +#define MG8_12_112PL 0xF7FF +#define MG8_12 (MG8_12_11PL & MG8_12_12PL & MG8_12_13PL & MG8_12_14PL & \ + MG8_12_15PL & MG8_12_16PL & MG8_12_17PL & MG8_12_18PL & \ + MG8_12_19PL & MG8_12_110PL & MG8_12_111PL & MG8_12_112PL & \ + MG8_12_113PL & MG8_12_114PL & MG8_12_115PL & MG8_12_116PL) +// End of MG8_12: +// Beginning of MG813: +#if (G8_1PL >= G8_13PL) || (G8_1PL == 0) +#define MG8_13_11PL ~(1 << 0) +#else +#define MG8_13_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_13PL) || (G8_2PL == 0) +#define MG8_13_12PL ~(1 << 1) +#else +#define MG8_13_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_13PL) || (G8_3PL == 0) +#define MG8_13_13PL ~(1 << 2) +#else +#define MG8_13_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_13PL) || (G8_4PL == 0) +#define MG8_13_14PL ~(1 << 3) +#else +#define MG8_13_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_13PL) || (G8_5PL == 0) +#define MG8_13_15PL ~(1 << 4) +#else +#define MG8_13_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_13PL) || (G8_6PL == 0) +#define MG8_13_16PL ~(1 << 5) +#else +#define MG8_13_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_13PL) || (G8_7PL == 0) +#define MG8_13_17PL ~(1 << 6) +#else +#define MG8_13_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_13PL) || (G8_8PL == 0) +#define MG8_13_18PL ~(1 << 7) +#else +#define MG8_13_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_13PL) || (G8_9PL == 0) +#define MG8_13_19PL ~(1 << 8) +#else +#define MG8_13_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_13PL) || (G8_10PL == 0) +#define MG8_13_110PL ~(1 << 9) +#else +#define MG8_13_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_13PL) || (G8_11PL == 0) +#define MG8_13_111PL ~(1 << 10) +#else +#define MG8_13_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_13PL) || (G8_12PL == 0) +#define MG8_13_112PL ~(1 << 11) +#else +#define MG8_13_112PL 0xFFFF +#endif + +#if (G8_14PL >= G8_13PL) || (G8_14PL == 0) +#define MG8_13_114PL ~(1 << 13) +#else +#define MG8_13_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_13PL) || (G8_15PL == 0) +#define MG8_13_115PL ~(1 << 14) +#else +#define MG8_13_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_13PL) || (G8_16PL == 0) +#define MG8_13_116PL ~(1 << 15) +#else +#define MG8_13_116PL 0xFFFF +#endif + +#define MG8_13_113PL 0xEFFF +#define MG8_13 (MG8_13_11PL & MG8_13_12PL & MG8_13_13PL & MG8_13_14PL & \ + MG8_13_15PL & MG8_13_16PL & MG8_13_17PL & MG8_13_18PL & \ + MG8_13_19PL & MG8_13_110PL & MG8_13_111PL & MG8_13_112PL & \ + MG8_13_113PL & MG8_13_114PL & MG8_13_115PL & MG8_13_116PL) +// End of MG8_13: +// Beginning of MG814: +#if (G8_1PL >= G8_14PL) || (G8_1PL == 0) +#define MG8_14_11PL ~(1 << 0) +#else +#define MG8_14_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_14PL) || (G8_2PL == 0) +#define MG8_14_12PL ~(1 << 1) +#else +#define MG8_14_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_14PL) || (G8_3PL == 0) +#define MG8_14_13PL ~(1 << 2) +#else +#define MG8_14_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_14PL) || (G8_4PL == 0) +#define MG8_14_14PL ~(1 << 3) +#else +#define MG8_14_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_14PL) || (G8_5PL == 0) +#define MG8_14_15PL ~(1 << 4) +#else +#define MG8_14_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_14PL) || (G8_6PL == 0) +#define MG8_14_16PL ~(1 << 5) +#else +#define MG8_14_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_14PL) || (G8_7PL == 0) +#define MG8_14_17PL ~(1 << 6) +#else +#define MG8_14_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_14PL) || (G8_8PL == 0) +#define MG8_14_18PL ~(1 << 7) +#else +#define MG8_14_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_14PL) || (G8_9PL == 0) +#define MG8_14_19PL ~(1 << 8) +#else +#define MG8_14_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_14PL) || (G8_10PL == 0) +#define MG8_14_110PL ~(1 << 9) +#else +#define MG8_14_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_14PL) || (G8_11PL == 0) +#define MG8_14_111PL ~(1 << 10) +#else +#define MG8_14_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_14PL) || (G8_12PL == 0) +#define MG8_14_112PL ~(1 << 11) +#else +#define MG8_14_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_14PL) || (G8_13PL == 0) +#define MG8_14_113PL ~(1 << 12) +#else +#define MG8_14_113PL 0xFFFF +#endif + +#if (G8_15PL >= G8_14PL) || (G8_15PL == 0) +#define MG8_14_115PL ~(1 << 14) +#else +#define MG8_14_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_14PL) || (G8_16PL == 0) +#define MG8_14_116PL ~(1 << 15) +#else +#define MG8_14_116PL 0xFFFF +#endif + +#define MG8_14_114PL 0xDFFF +#define MG8_14 (MG8_14_11PL & MG8_14_12PL & MG8_14_13PL & MG8_14_14PL & \ + MG8_14_15PL & MG8_14_16PL & MG8_14_17PL & MG8_14_18PL & \ + MG8_14_19PL & MG8_14_110PL & MG8_14_111PL & MG8_14_112PL & \ + MG8_14_113PL & MG8_14_114PL & MG8_14_115PL & MG8_14_116PL) +// End of MG8_14: +// Beginning of MG815: +#if (G8_1PL >= G8_15PL) || (G8_1PL == 0) +#define MG8_15_11PL ~(1 << 0) +#else +#define MG8_15_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_15PL) || (G8_2PL == 0) +#define MG8_15_12PL ~(1 << 1) +#else +#define MG8_15_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_15PL) || (G8_3PL == 0) +#define MG8_15_13PL ~(1 << 2) +#else +#define MG8_15_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_15PL) || (G8_4PL == 0) +#define MG8_15_14PL ~(1 << 3) +#else +#define MG8_15_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_15PL) || (G8_5PL == 0) +#define MG8_15_15PL ~(1 << 4) +#else +#define MG8_15_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_15PL) || (G8_6PL == 0) +#define MG8_15_16PL ~(1 << 5) +#else +#define MG8_15_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_15PL) || (G8_7PL == 0) +#define MG8_15_17PL ~(1 << 6) +#else +#define MG8_15_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_15PL) || (G8_8PL == 0) +#define MG8_15_18PL ~(1 << 7) +#else +#define MG8_15_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_15PL) || (G8_9PL == 0) +#define MG8_15_19PL ~(1 << 8) +#else +#define MG8_15_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_15PL) || (G8_10PL == 0) +#define MG8_15_110PL ~(1 << 9) +#else +#define MG8_15_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_15PL) || (G8_11PL == 0) +#define MG8_15_111PL ~(1 << 10) +#else +#define MG8_15_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_15PL) || (G8_12PL == 0) +#define MG8_15_112PL ~(1 << 11) +#else +#define MG8_15_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_15PL) || (G8_13PL == 0) +#define MG8_15_113PL ~(1 << 12) +#else +#define MG8_15_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_15PL) || (G8_14PL == 0) +#define MG8_15_114PL ~(1 << 13) +#else +#define MG8_15_114PL 0xFFFF +#endif + +#if (G8_16PL >= G8_15PL) || (G8_16PL == 0) +#define MG8_15_116PL ~(1 << 15) +#else +#define MG8_15_116PL 0xFFFF +#endif + +#define MG8_15_115PL 0xBFFF +#define MG8_15 (MG8_15_11PL & MG8_15_12PL & MG8_15_13PL & MG8_15_14PL & \ + MG8_15_15PL & MG8_15_16PL & MG8_15_17PL & MG8_15_18PL & \ + MG8_15_19PL & MG8_15_110PL & MG8_15_111PL & MG8_15_112PL & \ + MG8_15_113PL & MG8_15_114PL & MG8_15_115PL & MG8_15_116PL) +// End of MG8_15: +// Beginning of MG816: +#if (G8_1PL >= G8_16PL) || (G8_1PL == 0) +#define MG8_16_11PL ~(1 << 0) +#else +#define MG8_16_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_16PL) || (G8_2PL == 0) +#define MG8_16_12PL ~(1 << 1) +#else +#define MG8_16_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_16PL) || (G8_3PL == 0) +#define MG8_16_13PL ~(1 << 2) +#else +#define MG8_16_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_16PL) || (G8_4PL == 0) +#define MG8_16_14PL ~(1 << 3) +#else +#define MG8_16_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_16PL) || (G8_5PL == 0) +#define MG8_16_15PL ~(1 << 4) +#else +#define MG8_16_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_16PL) || (G8_6PL == 0) +#define MG8_16_16PL ~(1 << 5) +#else +#define MG8_16_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_16PL) || (G8_7PL == 0) +#define MG8_16_17PL ~(1 << 6) +#else +#define MG8_16_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_16PL) || (G8_8PL == 0) +#define MG8_16_18PL ~(1 << 7) +#else +#define MG8_16_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_16PL) || (G8_9PL == 0) +#define MG8_16_19PL ~(1 << 8) +#else +#define MG8_16_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_16PL) || (G8_10PL == 0) +#define MG8_16_110PL ~(1 << 9) +#else +#define MG8_16_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_16PL) || (G8_11PL == 0) +#define MG8_16_111PL ~(1 << 10) +#else +#define MG8_16_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_16PL) || (G8_12PL == 0) +#define MG8_16_112PL ~(1 << 11) +#else +#define MG8_16_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_16PL) || (G8_13PL == 0) +#define MG8_16_113PL ~(1 << 12) +#else +#define MG8_16_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_16PL) || (G8_14PL == 0) +#define MG8_16_114PL ~(1 << 13) +#else +#define MG8_16_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_16PL) || (G8_15PL == 0) +#define MG8_16_115PL ~(1 << 14) +#else +#define MG8_16_115PL 0xFFFF +#endif + +#define MG8_16_116PL 0x7FFF +#define MG8_16 (MG8_16_11PL & MG8_16_12PL & MG8_16_13PL & MG8_16_14PL & \ + MG8_16_15PL & MG8_16_16PL & MG8_16_17PL & MG8_16_18PL & \ + MG8_16_19PL & MG8_16_110PL & MG8_16_111PL & MG8_16_112PL & \ + MG8_16_113PL & MG8_16_114PL & MG8_16_115PL & MG8_16_116PL) +// End of MG8_16: + + +// +// Automatically generate PIEIER9 interrupt masks MG91 to MG916: +// + +// Beginning of MG91: +#if (G9_2PL >= G9_1PL) || (G9_2PL == 0) +#define MG9_1_12PL ~(1 << 1) +#else +#define MG9_1_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_1PL) || (G9_3PL == 0) +#define MG9_1_13PL ~(1 << 2) +#else +#define MG9_1_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_1PL) || (G9_4PL == 0) +#define MG9_1_14PL ~(1 << 3) +#else +#define MG9_1_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_1PL) || (G9_5PL == 0) +#define MG9_1_15PL ~(1 << 4) +#else +#define MG9_1_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_1PL) || (G9_6PL == 0) +#define MG9_1_16PL ~(1 << 5) +#else +#define MG9_1_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_1PL) || (G9_7PL == 0) +#define MG9_1_17PL ~(1 << 6) +#else +#define MG9_1_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_1PL) || (G9_8PL == 0) +#define MG9_1_18PL ~(1 << 7) +#else +#define MG9_1_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_1PL) || (G9_9PL == 0) +#define MG9_1_19PL ~(1 << 8) +#else +#define MG9_1_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_1PL) || (G9_10PL == 0) +#define MG9_1_110PL ~(1 << 9) +#else +#define MG9_1_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_1PL) || (G9_11PL == 0) +#define MG9_1_111PL ~(1 << 10) +#else +#define MG9_1_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_1PL) || (G9_12PL == 0) +#define MG9_1_112PL ~(1 << 11) +#else +#define MG9_1_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_1PL) || (G9_13PL == 0) +#define MG9_1_113PL ~(1 << 12) +#else +#define MG9_1_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_1PL) || (G9_14PL == 0) +#define MG9_1_114PL ~(1 << 13) +#else +#define MG9_1_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_1PL) || (G9_15PL == 0) +#define MG9_1_115PL ~(1 << 14) +#else +#define MG9_1_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_1PL) || (G9_16PL == 0) +#define MG9_1_116PL ~(1 << 15) +#else +#define MG9_1_116PL 0xFFFF +#endif + +#define MG9_1_11PL 0xFFFE +#define MG9_1 (MG9_1_11PL & MG9_1_12PL & MG9_1_13PL & MG9_1_14PL & \ + MG9_1_15PL & MG9_1_16PL & MG9_1_17PL & MG9_1_18PL & \ + MG9_1_19PL & MG9_1_110PL & MG9_1_111PL & MG9_1_112PL & \ + MG9_1_113PL & MG9_1_114PL & MG9_1_115PL & MG9_1_116PL) +// End of MG9_1: +// Beginning of MG92: +#if (G9_1PL >= G9_2PL) || (G9_1PL == 0) +#define MG9_2_11PL ~(1 << 0) +#else +#define MG9_2_11PL 0xFFFF +#endif + +#if (G9_3PL >= G9_2PL) || (G9_3PL == 0) +#define MG9_2_13PL ~(1 << 2) +#else +#define MG9_2_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_2PL) || (G9_4PL == 0) +#define MG9_2_14PL ~(1 << 3) +#else +#define MG9_2_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_2PL) || (G9_5PL == 0) +#define MG9_2_15PL ~(1 << 4) +#else +#define MG9_2_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_2PL) || (G9_6PL == 0) +#define MG9_2_16PL ~(1 << 5) +#else +#define MG9_2_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_2PL) || (G9_7PL == 0) +#define MG9_2_17PL ~(1 << 6) +#else +#define MG9_2_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_2PL) || (G9_8PL == 0) +#define MG9_2_18PL ~(1 << 7) +#else +#define MG9_2_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_2PL) || (G9_9PL == 0) +#define MG9_2_19PL ~(1 << 8) +#else +#define MG9_2_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_2PL) || (G9_10PL == 0) +#define MG9_2_110PL ~(1 << 9) +#else +#define MG9_2_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_2PL) || (G9_11PL == 0) +#define MG9_2_111PL ~(1 << 10) +#else +#define MG9_2_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_2PL) || (G9_12PL == 0) +#define MG9_2_112PL ~(1 << 11) +#else +#define MG9_2_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_2PL) || (G9_13PL == 0) +#define MG9_2_113PL ~(1 << 12) +#else +#define MG9_2_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_2PL) || (G9_14PL == 0) +#define MG9_2_114PL ~(1 << 13) +#else +#define MG9_2_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_2PL) || (G9_15PL == 0) +#define MG9_2_115PL ~(1 << 14) +#else +#define MG9_2_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_2PL) || (G9_16PL == 0) +#define MG9_2_116PL ~(1 << 15) +#else +#define MG9_2_116PL 0xFFFF +#endif + +#define MG9_2_12PL 0xFFFD +#define MG9_2 (MG9_2_11PL & MG9_2_12PL & MG9_2_13PL & MG9_2_14PL & \ + MG9_2_15PL & MG9_2_16PL & MG9_2_17PL & MG9_2_18PL & \ + MG9_2_19PL & MG9_2_110PL & MG9_2_111PL & MG9_2_112PL & \ + MG9_2_113PL & MG9_2_114PL & MG9_2_115PL & MG9_2_116PL) +// End of MG9_2: +// Beginning of MG93: +#if (G9_1PL >= G9_3PL) || (G9_1PL == 0) +#define MG9_3_11PL ~(1 << 0) +#else +#define MG9_3_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_3PL) || (G9_2PL == 0) +#define MG9_3_12PL ~(1 << 1) +#else +#define MG9_3_12PL 0xFFFF +#endif + +#if (G9_4PL >= G9_3PL) || (G9_4PL == 0) +#define MG9_3_14PL ~(1 << 3) +#else +#define MG9_3_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_3PL) || (G9_5PL == 0) +#define MG9_3_15PL ~(1 << 4) +#else +#define MG9_3_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_3PL) || (G9_6PL == 0) +#define MG9_3_16PL ~(1 << 5) +#else +#define MG9_3_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_3PL) || (G9_7PL == 0) +#define MG9_3_17PL ~(1 << 6) +#else +#define MG9_3_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_3PL) || (G9_8PL == 0) +#define MG9_3_18PL ~(1 << 7) +#else +#define MG9_3_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_3PL) || (G9_9PL == 0) +#define MG9_3_19PL ~(1 << 8) +#else +#define MG9_3_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_3PL) || (G9_10PL == 0) +#define MG9_3_110PL ~(1 << 9) +#else +#define MG9_3_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_3PL) || (G9_11PL == 0) +#define MG9_3_111PL ~(1 << 10) +#else +#define MG9_3_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_3PL) || (G9_12PL == 0) +#define MG9_3_112PL ~(1 << 11) +#else +#define MG9_3_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_3PL) || (G9_13PL == 0) +#define MG9_3_113PL ~(1 << 12) +#else +#define MG9_3_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_3PL) || (G9_14PL == 0) +#define MG9_3_114PL ~(1 << 13) +#else +#define MG9_3_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_3PL) || (G9_15PL == 0) +#define MG9_3_115PL ~(1 << 14) +#else +#define MG9_3_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_3PL) || (G9_16PL == 0) +#define MG9_3_116PL ~(1 << 15) +#else +#define MG9_3_116PL 0xFFFF +#endif + +#define MG9_3_13PL 0xFFFB +#define MG9_3 (MG9_3_11PL & MG9_3_12PL & MG9_3_13PL & MG9_3_14PL & \ + MG9_3_15PL & MG9_3_16PL & MG9_3_17PL & MG9_3_18PL & \ + MG9_3_19PL & MG9_3_110PL & MG9_3_111PL & MG9_3_112PL & \ + MG9_3_113PL & MG9_3_114PL & MG9_3_115PL & MG9_3_116PL) +// End of MG9_3: +// Beginning of MG94: +#if (G9_1PL >= G9_4PL) || (G9_1PL == 0) +#define MG9_4_11PL ~(1 << 0) +#else +#define MG9_4_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_4PL) || (G9_2PL == 0) +#define MG9_4_12PL ~(1 << 1) +#else +#define MG9_4_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_4PL) || (G9_3PL == 0) +#define MG9_4_13PL ~(1 << 2) +#else +#define MG9_4_13PL 0xFFFF +#endif + +#if (G9_5PL >= G9_4PL) || (G9_5PL == 0) +#define MG9_4_15PL ~(1 << 4) +#else +#define MG9_4_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_4PL) || (G9_6PL == 0) +#define MG9_4_16PL ~(1 << 5) +#else +#define MG9_4_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_4PL) || (G9_7PL == 0) +#define MG9_4_17PL ~(1 << 6) +#else +#define MG9_4_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_4PL) || (G9_8PL == 0) +#define MG9_4_18PL ~(1 << 7) +#else +#define MG9_4_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_4PL) || (G9_9PL == 0) +#define MG9_4_19PL ~(1 << 8) +#else +#define MG9_4_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_4PL) || (G9_10PL == 0) +#define MG9_4_110PL ~(1 << 9) +#else +#define MG9_4_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_4PL) || (G9_11PL == 0) +#define MG9_4_111PL ~(1 << 10) +#else +#define MG9_4_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_4PL) || (G9_12PL == 0) +#define MG9_4_112PL ~(1 << 11) +#else +#define MG9_4_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_4PL) || (G9_13PL == 0) +#define MG9_4_113PL ~(1 << 12) +#else +#define MG9_4_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_4PL) || (G9_14PL == 0) +#define MG9_4_114PL ~(1 << 13) +#else +#define MG9_4_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_4PL) || (G9_15PL == 0) +#define MG9_4_115PL ~(1 << 14) +#else +#define MG9_4_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_4PL) || (G9_16PL == 0) +#define MG9_4_116PL ~(1 << 15) +#else +#define MG9_4_116PL 0xFFFF +#endif + +#define MG9_4_14PL 0xFFF7 +#define MG9_4 (MG9_4_11PL & MG9_4_12PL & MG9_4_13PL & MG9_4_14PL & \ + MG9_4_15PL & MG9_4_16PL & MG9_4_17PL & MG9_4_18PL & \ + MG9_4_19PL & MG9_4_110PL & MG9_4_111PL & MG9_4_112PL & \ + MG9_4_113PL & MG9_4_114PL & MG9_4_115PL & MG9_4_116PL) +// End of MG9_4: +// Beginning of MG95: +#if (G9_1PL >= G9_5PL) || (G9_1PL == 0) +#define MG9_5_11PL ~(1 << 0) +#else +#define MG9_5_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_5PL) || (G9_2PL == 0) +#define MG9_5_12PL ~(1 << 1) +#else +#define MG9_5_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_5PL) || (G9_3PL == 0) +#define MG9_5_13PL ~(1 << 2) +#else +#define MG9_5_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_5PL) || (G9_4PL == 0) +#define MG9_5_14PL ~(1 << 3) +#else +#define MG9_5_14PL 0xFFFF +#endif + +#if (G9_6PL >= G9_5PL) || (G9_6PL == 0) +#define MG9_5_16PL ~(1 << 5) +#else +#define MG9_5_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_5PL) || (G9_7PL == 0) +#define MG9_5_17PL ~(1 << 6) +#else +#define MG9_5_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_5PL) || (G9_8PL == 0) +#define MG9_5_18PL ~(1 << 7) +#else +#define MG9_5_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_5PL) || (G9_9PL == 0) +#define MG9_5_19PL ~(1 << 8) +#else +#define MG9_5_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_5PL) || (G9_10PL == 0) +#define MG9_5_110PL ~(1 << 9) +#else +#define MG9_5_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_5PL) || (G9_11PL == 0) +#define MG9_5_111PL ~(1 << 10) +#else +#define MG9_5_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_5PL) || (G9_12PL == 0) +#define MG9_5_112PL ~(1 << 11) +#else +#define MG9_5_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_5PL) || (G9_13PL == 0) +#define MG9_5_113PL ~(1 << 12) +#else +#define MG9_5_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_5PL) || (G9_14PL == 0) +#define MG9_5_114PL ~(1 << 13) +#else +#define MG9_5_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_5PL) || (G9_15PL == 0) +#define MG9_5_115PL ~(1 << 14) +#else +#define MG9_5_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_5PL) || (G9_16PL == 0) +#define MG9_5_116PL ~(1 << 15) +#else +#define MG9_5_116PL 0xFFFF +#endif + +#define MG9_5_15PL 0xFFEF +#define MG9_5 (MG9_5_11PL & MG9_5_12PL & MG9_5_13PL & MG9_5_14PL & \ + MG9_5_15PL & MG9_5_16PL & MG9_5_17PL & MG9_5_18PL & \ + MG9_5_19PL & MG9_5_110PL & MG9_5_111PL & MG9_5_112PL & \ + MG9_5_113PL & MG9_5_114PL & MG9_5_115PL & MG9_5_116PL) +// End of MG9_5: +// Beginning of MG96: +#if (G9_1PL >= G9_6PL) || (G9_1PL == 0) +#define MG9_6_11PL ~(1 << 0) +#else +#define MG9_6_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_6PL) || (G9_2PL == 0) +#define MG9_6_12PL ~(1 << 1) +#else +#define MG9_6_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_6PL) || (G9_3PL == 0) +#define MG9_6_13PL ~(1 << 2) +#else +#define MG9_6_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_6PL) || (G9_4PL == 0) +#define MG9_6_14PL ~(1 << 3) +#else +#define MG9_6_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_6PL) || (G9_5PL == 0) +#define MG9_6_15PL ~(1 << 4) +#else +#define MG9_6_15PL 0xFFFF +#endif + +#if (G9_7PL >= G9_6PL) || (G9_7PL == 0) +#define MG9_6_17PL ~(1 << 6) +#else +#define MG9_6_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_6PL) || (G9_8PL == 0) +#define MG9_6_18PL ~(1 << 7) +#else +#define MG9_6_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_6PL) || (G9_9PL == 0) +#define MG9_6_19PL ~(1 << 8) +#else +#define MG9_6_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_6PL) || (G9_10PL == 0) +#define MG9_6_110PL ~(1 << 9) +#else +#define MG9_6_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_6PL) || (G9_11PL == 0) +#define MG9_6_111PL ~(1 << 10) +#else +#define MG9_6_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_6PL) || (G9_12PL == 0) +#define MG9_6_112PL ~(1 << 11) +#else +#define MG9_6_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_6PL) || (G9_13PL == 0) +#define MG9_6_113PL ~(1 << 12) +#else +#define MG9_6_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_6PL) || (G9_14PL == 0) +#define MG9_6_114PL ~(1 << 13) +#else +#define MG9_6_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_6PL) || (G9_15PL == 0) +#define MG9_6_115PL ~(1 << 14) +#else +#define MG9_6_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_6PL) || (G9_16PL == 0) +#define MG9_6_116PL ~(1 << 15) +#else +#define MG9_6_116PL 0xFFFF +#endif + +#define MG9_6_16PL 0xFFDF +#define MG9_6 (MG9_6_11PL & MG9_6_12PL & MG9_6_13PL & MG9_6_14PL & \ + MG9_6_15PL & MG9_6_16PL & MG9_6_17PL & MG9_6_18PL & \ + MG9_6_19PL & MG9_6_110PL & MG9_6_111PL & MG9_6_112PL & \ + MG9_6_113PL & MG9_6_114PL & MG9_6_115PL & MG9_6_116PL) +// End of MG9_6: +// Beginning of MG97: +#if (G9_1PL >= G9_7PL) || (G9_1PL == 0) +#define MG9_7_11PL ~(1 << 0) +#else +#define MG9_7_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_7PL) || (G9_2PL == 0) +#define MG9_7_12PL ~(1 << 1) +#else +#define MG9_7_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_7PL) || (G9_3PL == 0) +#define MG9_7_13PL ~(1 << 2) +#else +#define MG9_7_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_7PL) || (G9_4PL == 0) +#define MG9_7_14PL ~(1 << 3) +#else +#define MG9_7_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_7PL) || (G9_5PL == 0) +#define MG9_7_15PL ~(1 << 4) +#else +#define MG9_7_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_7PL) || (G9_6PL == 0) +#define MG9_7_16PL ~(1 << 5) +#else +#define MG9_7_16PL 0xFFFF +#endif + +#if (G9_8PL >= G9_7PL) || (G9_8PL == 0) +#define MG9_7_18PL ~(1 << 7) +#else +#define MG9_7_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_7PL) || (G9_9PL == 0) +#define MG9_7_19PL ~(1 << 8) +#else +#define MG9_7_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_7PL) || (G9_10PL == 0) +#define MG9_7_110PL ~(1 << 9) +#else +#define MG9_7_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_7PL) || (G9_11PL == 0) +#define MG9_7_111PL ~(1 << 10) +#else +#define MG9_7_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_7PL) || (G9_12PL == 0) +#define MG9_7_112PL ~(1 << 11) +#else +#define MG9_7_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_7PL) || (G9_13PL == 0) +#define MG9_7_113PL ~(1 << 12) +#else +#define MG9_7_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_7PL) || (G9_14PL == 0) +#define MG9_7_114PL ~(1 << 13) +#else +#define MG9_7_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_7PL) || (G9_15PL == 0) +#define MG9_7_115PL ~(1 << 14) +#else +#define MG9_7_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_7PL) || (G9_16PL == 0) +#define MG9_7_116PL ~(1 << 15) +#else +#define MG9_7_116PL 0xFFFF +#endif + +#define MG9_7_17PL 0xFFBF +#define MG9_7 (MG9_7_11PL & MG9_7_12PL & MG9_7_13PL & MG9_7_14PL & \ + MG9_7_15PL & MG9_7_16PL & MG9_7_17PL & MG9_7_18PL & \ + MG9_7_19PL & MG9_7_110PL & MG9_7_111PL & MG9_7_112PL & \ + MG9_7_113PL & MG9_7_114PL & MG9_7_115PL & MG9_7_116PL) +// End of MG9_7: +// Beginning of MG98: +#if (G9_1PL >= G9_8PL) || (G9_1PL == 0) +#define MG9_8_11PL ~(1 << 0) +#else +#define MG9_8_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_8PL) || (G9_2PL == 0) +#define MG9_8_12PL ~(1 << 1) +#else +#define MG9_8_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_8PL) || (G9_3PL == 0) +#define MG9_8_13PL ~(1 << 2) +#else +#define MG9_8_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_8PL) || (G9_4PL == 0) +#define MG9_8_14PL ~(1 << 3) +#else +#define MG9_8_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_8PL) || (G9_5PL == 0) +#define MG9_8_15PL ~(1 << 4) +#else +#define MG9_8_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_8PL) || (G9_6PL == 0) +#define MG9_8_16PL ~(1 << 5) +#else +#define MG9_8_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_8PL) || (G9_7PL == 0) +#define MG9_8_17PL ~(1 << 6) +#else +#define MG9_8_17PL 0xFFFF +#endif + +#if (G9_9PL >= G9_8PL) || (G9_9PL == 0) +#define MG9_8_19PL ~(1 << 8) +#else +#define MG9_8_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_8PL) || (G9_10PL == 0) +#define MG9_8_110PL ~(1 << 9) +#else +#define MG9_8_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_8PL) || (G9_11PL == 0) +#define MG9_8_111PL ~(1 << 10) +#else +#define MG9_8_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_8PL) || (G9_12PL == 0) +#define MG9_8_112PL ~(1 << 11) +#else +#define MG9_8_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_8PL) || (G9_13PL == 0) +#define MG9_8_113PL ~(1 << 12) +#else +#define MG9_8_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_8PL) || (G9_14PL == 0) +#define MG9_8_114PL ~(1 << 13) +#else +#define MG9_8_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_8PL) || (G9_15PL == 0) +#define MG9_8_115PL ~(1 << 14) +#else +#define MG9_8_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_8PL) || (G9_16PL == 0) +#define MG9_8_116PL ~(1 << 15) +#else +#define MG9_8_116PL 0xFFFF +#endif + +#define MG9_8_18PL 0xFF7F +#define MG9_8 (MG9_8_11PL & MG9_8_12PL & MG9_8_13PL & MG9_8_14PL & \ + MG9_8_15PL & MG9_8_16PL & MG9_8_17PL & MG9_8_18PL & \ + MG9_8_19PL & MG9_8_110PL & MG9_8_111PL & MG9_8_112PL & \ + MG9_8_113PL & MG9_8_114PL & MG9_8_115PL & MG9_8_116PL) +// End of MG9_8: +// Beginning of MG99: +#if (G9_1PL >= G9_9PL) || (G9_1PL == 0) +#define MG9_9_11PL ~(1 << 0) +#else +#define MG9_9_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_9PL) || (G9_2PL == 0) +#define MG9_9_12PL ~(1 << 1) +#else +#define MG9_9_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_9PL) || (G9_3PL == 0) +#define MG9_9_13PL ~(1 << 2) +#else +#define MG9_9_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_9PL) || (G9_4PL == 0) +#define MG9_9_14PL ~(1 << 3) +#else +#define MG9_9_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_9PL) || (G9_5PL == 0) +#define MG9_9_15PL ~(1 << 4) +#else +#define MG9_9_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_9PL) || (G9_6PL == 0) +#define MG9_9_16PL ~(1 << 5) +#else +#define MG9_9_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_9PL) || (G9_7PL == 0) +#define MG9_9_17PL ~(1 << 6) +#else +#define MG9_9_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_9PL) || (G9_8PL == 0) +#define MG9_9_18PL ~(1 << 7) +#else +#define MG9_9_18PL 0xFFFF +#endif + +#if (G9_10PL >= G9_9PL) || (G9_10PL == 0) +#define MG9_9_110PL ~(1 << 9) +#else +#define MG9_9_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_9PL) || (G9_11PL == 0) +#define MG9_9_111PL ~(1 << 10) +#else +#define MG9_9_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_9PL) || (G9_12PL == 0) +#define MG9_9_112PL ~(1 << 11) +#else +#define MG9_9_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_9PL) || (G9_13PL == 0) +#define MG9_9_113PL ~(1 << 12) +#else +#define MG9_9_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_9PL) || (G9_14PL == 0) +#define MG9_9_114PL ~(1 << 13) +#else +#define MG9_9_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_9PL) || (G9_15PL == 0) +#define MG9_9_115PL ~(1 << 14) +#else +#define MG9_9_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_9PL) || (G9_16PL == 0) +#define MG9_9_116PL ~(1 << 15) +#else +#define MG9_9_116PL 0xFFFF +#endif + +#define MG9_9_19PL 0xFEFF +#define MG9_9 (MG9_9_11PL & MG9_9_12PL & MG9_9_13PL & MG9_9_14PL & \ + MG9_9_15PL & MG9_9_16PL & MG9_9_17PL & MG9_9_18PL & \ + MG9_9_19PL & MG9_9_110PL & MG9_9_111PL & MG9_9_112PL & \ + MG9_9_113PL & MG9_9_114PL & MG9_9_115PL & MG9_9_116PL) +// End of MG9_9: +// Beginning of MG910: +#if (G9_1PL >= G9_10PL) || (G9_1PL == 0) +#define MG9_10_11PL ~(1 << 0) +#else +#define MG9_10_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_10PL) || (G9_2PL == 0) +#define MG9_10_12PL ~(1 << 1) +#else +#define MG9_10_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_10PL) || (G9_3PL == 0) +#define MG9_10_13PL ~(1 << 2) +#else +#define MG9_10_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_10PL) || (G9_4PL == 0) +#define MG9_10_14PL ~(1 << 3) +#else +#define MG9_10_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_10PL) || (G9_5PL == 0) +#define MG9_10_15PL ~(1 << 4) +#else +#define MG9_10_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_10PL) || (G9_6PL == 0) +#define MG9_10_16PL ~(1 << 5) +#else +#define MG9_10_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_10PL) || (G9_7PL == 0) +#define MG9_10_17PL ~(1 << 6) +#else +#define MG9_10_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_10PL) || (G9_8PL == 0) +#define MG9_10_18PL ~(1 << 7) +#else +#define MG9_10_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_10PL) || (G9_9PL == 0) +#define MG9_10_19PL ~(1 << 8) +#else +#define MG9_10_19PL 0xFFFF +#endif + +#if (G9_11PL >= G9_10PL) || (G9_11PL == 0) +#define MG9_10_111PL ~(1 << 10) +#else +#define MG9_10_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_10PL) || (G9_12PL == 0) +#define MG9_10_112PL ~(1 << 11) +#else +#define MG9_10_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_10PL) || (G9_13PL == 0) +#define MG9_10_113PL ~(1 << 12) +#else +#define MG9_10_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_10PL) || (G9_14PL == 0) +#define MG9_10_114PL ~(1 << 13) +#else +#define MG9_10_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_10PL) || (G9_15PL == 0) +#define MG9_10_115PL ~(1 << 14) +#else +#define MG9_10_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_10PL) || (G9_16PL == 0) +#define MG9_10_116PL ~(1 << 15) +#else +#define MG9_10_116PL 0xFFFF +#endif + +#define MG9_10_110PL 0xFDFF +#define MG9_10 (MG9_10_11PL & MG9_10_12PL & MG9_10_13PL & MG9_10_14PL & \ + MG9_10_15PL & MG9_10_16PL & MG9_10_17PL & MG9_10_18PL & \ + MG9_10_19PL & MG9_10_110PL & MG9_10_111PL & MG9_10_112PL & \ + MG9_10_113PL & MG9_10_114PL & MG9_10_115PL & MG9_10_116PL) +// End of MG9_10: +// Beginning of MG911: +#if (G9_1PL >= G9_11PL) || (G9_1PL == 0) +#define MG9_11_11PL ~(1 << 0) +#else +#define MG9_11_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_11PL) || (G9_2PL == 0) +#define MG9_11_12PL ~(1 << 1) +#else +#define MG9_11_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_11PL) || (G9_3PL == 0) +#define MG9_11_13PL ~(1 << 2) +#else +#define MG9_11_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_11PL) || (G9_4PL == 0) +#define MG9_11_14PL ~(1 << 3) +#else +#define MG9_11_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_11PL) || (G9_5PL == 0) +#define MG9_11_15PL ~(1 << 4) +#else +#define MG9_11_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_11PL) || (G9_6PL == 0) +#define MG9_11_16PL ~(1 << 5) +#else +#define MG9_11_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_11PL) || (G9_7PL == 0) +#define MG9_11_17PL ~(1 << 6) +#else +#define MG9_11_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_11PL) || (G9_8PL == 0) +#define MG9_11_18PL ~(1 << 7) +#else +#define MG9_11_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_11PL) || (G9_9PL == 0) +#define MG9_11_19PL ~(1 << 8) +#else +#define MG9_11_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_11PL) || (G9_10PL == 0) +#define MG9_11_110PL ~(1 << 9) +#else +#define MG9_11_110PL 0xFFFF +#endif + +#if (G9_12PL >= G9_11PL) || (G9_12PL == 0) +#define MG9_11_112PL ~(1 << 11) +#else +#define MG9_11_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_11PL) || (G9_13PL == 0) +#define MG9_11_113PL ~(1 << 12) +#else +#define MG9_11_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_11PL) || (G9_14PL == 0) +#define MG9_11_114PL ~(1 << 13) +#else +#define MG9_11_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_11PL) || (G9_15PL == 0) +#define MG9_11_115PL ~(1 << 14) +#else +#define MG9_11_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_11PL) || (G9_16PL == 0) +#define MG9_11_116PL ~(1 << 15) +#else +#define MG9_11_116PL 0xFFFF +#endif + +#define MG9_11_111PL 0xFBFF +#define MG9_11 (MG9_11_11PL & MG9_11_12PL & MG9_11_13PL & MG9_11_14PL & \ + MG9_11_15PL & MG9_11_16PL & MG9_11_17PL & MG9_11_18PL & \ + MG9_11_19PL & MG9_11_110PL & MG9_11_111PL & MG9_11_112PL & \ + MG9_11_113PL & MG9_11_114PL & MG9_11_115PL & MG9_11_116PL) +// End of MG9_11: +// Beginning of MG912: +#if (G9_1PL >= G9_12PL) || (G9_1PL == 0) +#define MG9_12_11PL ~(1 << 0) +#else +#define MG9_12_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_12PL) || (G9_2PL == 0) +#define MG9_12_12PL ~(1 << 1) +#else +#define MG9_12_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_12PL) || (G9_3PL == 0) +#define MG9_12_13PL ~(1 << 2) +#else +#define MG9_12_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_12PL) || (G9_4PL == 0) +#define MG9_12_14PL ~(1 << 3) +#else +#define MG9_12_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_12PL) || (G9_5PL == 0) +#define MG9_12_15PL ~(1 << 4) +#else +#define MG9_12_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_12PL) || (G9_6PL == 0) +#define MG9_12_16PL ~(1 << 5) +#else +#define MG9_12_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_12PL) || (G9_7PL == 0) +#define MG9_12_17PL ~(1 << 6) +#else +#define MG9_12_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_12PL) || (G9_8PL == 0) +#define MG9_12_18PL ~(1 << 7) +#else +#define MG9_12_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_12PL) || (G9_9PL == 0) +#define MG9_12_19PL ~(1 << 8) +#else +#define MG9_12_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_12PL) || (G9_10PL == 0) +#define MG9_12_110PL ~(1 << 9) +#else +#define MG9_12_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_12PL) || (G9_11PL == 0) +#define MG9_12_111PL ~(1 << 10) +#else +#define MG9_12_111PL 0xFFFF +#endif + +#if (G9_13PL >= G9_12PL) || (G9_13PL == 0) +#define MG9_12_113PL ~(1 << 12) +#else +#define MG9_12_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_12PL) || (G9_14PL == 0) +#define MG9_12_114PL ~(1 << 13) +#else +#define MG9_12_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_12PL) || (G9_15PL == 0) +#define MG9_12_115PL ~(1 << 14) +#else +#define MG9_12_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_12PL) || (G9_16PL == 0) +#define MG9_12_116PL ~(1 << 15) +#else +#define MG9_12_116PL 0xFFFF +#endif + +#define MG9_12_112PL 0xF7FF +#define MG9_12 (MG9_12_11PL & MG9_12_12PL & MG9_12_13PL & MG9_12_14PL & \ + MG9_12_15PL & MG9_12_16PL & MG9_12_17PL & MG9_12_18PL & \ + MG9_12_19PL & MG9_12_110PL & MG9_12_111PL & MG9_12_112PL & \ + MG9_12_113PL & MG9_12_114PL & MG9_12_115PL & MG9_12_116PL) +// End of MG9_12: +// Beginning of MG913: +#if (G9_1PL >= G9_13PL) || (G9_1PL == 0) +#define MG9_13_11PL ~(1 << 0) +#else +#define MG9_13_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_13PL) || (G9_2PL == 0) +#define MG9_13_12PL ~(1 << 1) +#else +#define MG9_13_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_13PL) || (G9_3PL == 0) +#define MG9_13_13PL ~(1 << 2) +#else +#define MG9_13_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_13PL) || (G9_4PL == 0) +#define MG9_13_14PL ~(1 << 3) +#else +#define MG9_13_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_13PL) || (G9_5PL == 0) +#define MG9_13_15PL ~(1 << 4) +#else +#define MG9_13_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_13PL) || (G9_6PL == 0) +#define MG9_13_16PL ~(1 << 5) +#else +#define MG9_13_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_13PL) || (G9_7PL == 0) +#define MG9_13_17PL ~(1 << 6) +#else +#define MG9_13_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_13PL) || (G9_8PL == 0) +#define MG9_13_18PL ~(1 << 7) +#else +#define MG9_13_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_13PL) || (G9_9PL == 0) +#define MG9_13_19PL ~(1 << 8) +#else +#define MG9_13_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_13PL) || (G9_10PL == 0) +#define MG9_13_110PL ~(1 << 9) +#else +#define MG9_13_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_13PL) || (G9_11PL == 0) +#define MG9_13_111PL ~(1 << 10) +#else +#define MG9_13_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_13PL) || (G9_12PL == 0) +#define MG9_13_112PL ~(1 << 11) +#else +#define MG9_13_112PL 0xFFFF +#endif + +#if (G9_14PL >= G9_13PL) || (G9_14PL == 0) +#define MG9_13_114PL ~(1 << 13) +#else +#define MG9_13_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_13PL) || (G9_15PL == 0) +#define MG9_13_115PL ~(1 << 14) +#else +#define MG9_13_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_13PL) || (G9_16PL == 0) +#define MG9_13_116PL ~(1 << 15) +#else +#define MG9_13_116PL 0xFFFF +#endif + +#define MG9_13_113PL 0xEFFF +#define MG9_13 (MG9_13_11PL & MG9_13_12PL & MG9_13_13PL & MG9_13_14PL & \ + MG9_13_15PL & MG9_13_16PL & MG9_13_17PL & MG9_13_18PL & \ + MG9_13_19PL & MG9_13_110PL & MG9_13_111PL & MG9_13_112PL & \ + MG9_13_113PL & MG9_13_114PL & MG9_13_115PL & MG9_13_116PL) +// End of MG9_13: +// Beginning of MG914: +#if (G9_1PL >= G9_14PL) || (G9_1PL == 0) +#define MG9_14_11PL ~(1 << 0) +#else +#define MG9_14_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_14PL) || (G9_2PL == 0) +#define MG9_14_12PL ~(1 << 1) +#else +#define MG9_14_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_14PL) || (G9_3PL == 0) +#define MG9_14_13PL ~(1 << 2) +#else +#define MG9_14_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_14PL) || (G9_4PL == 0) +#define MG9_14_14PL ~(1 << 3) +#else +#define MG9_14_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_14PL) || (G9_5PL == 0) +#define MG9_14_15PL ~(1 << 4) +#else +#define MG9_14_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_14PL) || (G9_6PL == 0) +#define MG9_14_16PL ~(1 << 5) +#else +#define MG9_14_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_14PL) || (G9_7PL == 0) +#define MG9_14_17PL ~(1 << 6) +#else +#define MG9_14_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_14PL) || (G9_8PL == 0) +#define MG9_14_18PL ~(1 << 7) +#else +#define MG9_14_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_14PL) || (G9_9PL == 0) +#define MG9_14_19PL ~(1 << 8) +#else +#define MG9_14_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_14PL) || (G9_10PL == 0) +#define MG9_14_110PL ~(1 << 9) +#else +#define MG9_14_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_14PL) || (G9_11PL == 0) +#define MG9_14_111PL ~(1 << 10) +#else +#define MG9_14_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_14PL) || (G9_12PL == 0) +#define MG9_14_112PL ~(1 << 11) +#else +#define MG9_14_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_14PL) || (G9_13PL == 0) +#define MG9_14_113PL ~(1 << 12) +#else +#define MG9_14_113PL 0xFFFF +#endif + +#if (G9_15PL >= G9_14PL) || (G9_15PL == 0) +#define MG9_14_115PL ~(1 << 14) +#else +#define MG9_14_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_14PL) || (G9_16PL == 0) +#define MG9_14_116PL ~(1 << 15) +#else +#define MG9_14_116PL 0xFFFF +#endif + +#define MG9_14_114PL 0xDFFF +#define MG9_14 (MG9_14_11PL & MG9_14_12PL & MG9_14_13PL & MG9_14_14PL & \ + MG9_14_15PL & MG9_14_16PL & MG9_14_17PL & MG9_14_18PL & \ + MG9_14_19PL & MG9_14_110PL & MG9_14_111PL & MG9_14_112PL & \ + MG9_14_113PL & MG9_14_114PL & MG9_14_115PL & MG9_14_116PL) +// End of MG9_14: +// Beginning of MG915: +#if (G9_1PL >= G9_15PL) || (G9_1PL == 0) +#define MG9_15_11PL ~(1 << 0) +#else +#define MG9_15_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_15PL) || (G9_2PL == 0) +#define MG9_15_12PL ~(1 << 1) +#else +#define MG9_15_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_15PL) || (G9_3PL == 0) +#define MG9_15_13PL ~(1 << 2) +#else +#define MG9_15_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_15PL) || (G9_4PL == 0) +#define MG9_15_14PL ~(1 << 3) +#else +#define MG9_15_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_15PL) || (G9_5PL == 0) +#define MG9_15_15PL ~(1 << 4) +#else +#define MG9_15_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_15PL) || (G9_6PL == 0) +#define MG9_15_16PL ~(1 << 5) +#else +#define MG9_15_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_15PL) || (G9_7PL == 0) +#define MG9_15_17PL ~(1 << 6) +#else +#define MG9_15_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_15PL) || (G9_8PL == 0) +#define MG9_15_18PL ~(1 << 7) +#else +#define MG9_15_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_15PL) || (G9_9PL == 0) +#define MG9_15_19PL ~(1 << 8) +#else +#define MG9_15_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_15PL) || (G9_10PL == 0) +#define MG9_15_110PL ~(1 << 9) +#else +#define MG9_15_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_15PL) || (G9_11PL == 0) +#define MG9_15_111PL ~(1 << 10) +#else +#define MG9_15_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_15PL) || (G9_12PL == 0) +#define MG9_15_112PL ~(1 << 11) +#else +#define MG9_15_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_15PL) || (G9_13PL == 0) +#define MG9_15_113PL ~(1 << 12) +#else +#define MG9_15_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_15PL) || (G9_14PL == 0) +#define MG9_15_114PL ~(1 << 13) +#else +#define MG9_15_114PL 0xFFFF +#endif + +#if (G9_16PL >= G9_15PL) || (G9_16PL == 0) +#define MG9_15_116PL ~(1 << 15) +#else +#define MG9_15_116PL 0xFFFF +#endif + +#define MG9_15_115PL 0xBFFF +#define MG9_15 (MG9_15_11PL & MG9_15_12PL & MG9_15_13PL & MG9_15_14PL & \ + MG9_15_15PL & MG9_15_16PL & MG9_15_17PL & MG9_15_18PL & \ + MG9_15_19PL & MG9_15_110PL & MG9_15_111PL & MG9_15_112PL & \ + MG9_15_113PL & MG9_15_114PL & MG9_15_115PL & MG9_15_116PL) +// End of MG9_15: +// Beginning of MG916: +#if (G9_1PL >= G9_16PL) || (G9_1PL == 0) +#define MG9_16_11PL ~(1 << 0) +#else +#define MG9_16_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_16PL) || (G9_2PL == 0) +#define MG9_16_12PL ~(1 << 1) +#else +#define MG9_16_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_16PL) || (G9_3PL == 0) +#define MG9_16_13PL ~(1 << 2) +#else +#define MG9_16_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_16PL) || (G9_4PL == 0) +#define MG9_16_14PL ~(1 << 3) +#else +#define MG9_16_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_16PL) || (G9_5PL == 0) +#define MG9_16_15PL ~(1 << 4) +#else +#define MG9_16_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_16PL) || (G9_6PL == 0) +#define MG9_16_16PL ~(1 << 5) +#else +#define MG9_16_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_16PL) || (G9_7PL == 0) +#define MG9_16_17PL ~(1 << 6) +#else +#define MG9_16_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_16PL) || (G9_8PL == 0) +#define MG9_16_18PL ~(1 << 7) +#else +#define MG9_16_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_16PL) || (G9_9PL == 0) +#define MG9_16_19PL ~(1 << 8) +#else +#define MG9_16_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_16PL) || (G9_10PL == 0) +#define MG9_16_110PL ~(1 << 9) +#else +#define MG9_16_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_16PL) || (G9_11PL == 0) +#define MG9_16_111PL ~(1 << 10) +#else +#define MG9_16_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_16PL) || (G9_12PL == 0) +#define MG9_16_112PL ~(1 << 11) +#else +#define MG9_16_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_16PL) || (G9_13PL == 0) +#define MG9_16_113PL ~(1 << 12) +#else +#define MG9_16_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_16PL) || (G9_14PL == 0) +#define MG9_16_114PL ~(1 << 13) +#else +#define MG9_16_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_16PL) || (G9_15PL == 0) +#define MG9_16_115PL ~(1 << 14) +#else +#define MG9_16_115PL 0xFFFF +#endif + +#define MG9_16_116PL 0x7FFF +#define MG9_16 (MG9_16_11PL & MG9_16_12PL & MG9_16_13PL & MG9_16_14PL & \ + MG9_16_15PL & MG9_16_16PL & MG9_16_17PL & MG9_16_18PL & \ + MG9_16_19PL & MG9_16_110PL & MG9_16_111PL & MG9_16_112PL & \ + MG9_16_113PL & MG9_16_114PL & MG9_16_115PL & MG9_16_116PL) +// End of MG9_16: + + +// +// Automatically generate PIEIER10 interrupt masks MG101 to MG1016: +// + +// Beginning of MG101: +#if (G10_2PL >= G10_1PL) || (G10_2PL == 0) +#define MG10_1_12PL ~(1 << 1) +#else +#define MG10_1_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_1PL) || (G10_3PL == 0) +#define MG10_1_13PL ~(1 << 2) +#else +#define MG10_1_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_1PL) || (G10_4PL == 0) +#define MG10_1_14PL ~(1 << 3) +#else +#define MG10_1_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_1PL) || (G10_5PL == 0) +#define MG10_1_15PL ~(1 << 4) +#else +#define MG10_1_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_1PL) || (G10_6PL == 0) +#define MG10_1_16PL ~(1 << 5) +#else +#define MG10_1_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_1PL) || (G10_7PL == 0) +#define MG10_1_17PL ~(1 << 6) +#else +#define MG10_1_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_1PL) || (G10_8PL == 0) +#define MG10_1_18PL ~(1 << 7) +#else +#define MG10_1_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_1PL) || (G10_9PL == 0) +#define MG10_1_19PL ~(1 << 8) +#else +#define MG10_1_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_1PL) || (G10_10PL == 0) +#define MG10_1_110PL ~(1 << 9) +#else +#define MG10_1_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_1PL) || (G10_11PL == 0) +#define MG10_1_111PL ~(1 << 10) +#else +#define MG10_1_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_1PL) || (G10_12PL == 0) +#define MG10_1_112PL ~(1 << 11) +#else +#define MG10_1_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_1PL) || (G10_13PL == 0) +#define MG10_1_113PL ~(1 << 12) +#else +#define MG10_1_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_1PL) || (G10_14PL == 0) +#define MG10_1_114PL ~(1 << 13) +#else +#define MG10_1_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_1PL) || (G10_15PL == 0) +#define MG10_1_115PL ~(1 << 14) +#else +#define MG10_1_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_1PL) || (G10_16PL == 0) +#define MG10_1_116PL ~(1 << 15) +#else +#define MG10_1_116PL 0xFFFF +#endif + +#define MG10_1_11PL 0xFFFE +#define MG10_1 (MG10_1_11PL & MG10_1_12PL & MG10_1_13PL & MG10_1_14PL & \ + MG10_1_15PL & MG10_1_16PL & MG10_1_17PL & MG10_1_18PL & \ + MG10_1_19PL & MG10_1_110PL & MG10_1_111PL & MG10_1_112PL & \ + MG10_1_113PL & MG10_1_114PL & MG10_1_115PL & MG10_1_116PL) +// End of MG10_1: +// Beginning of MG102: +#if (G10_1PL >= G10_2PL) || (G10_1PL == 0) +#define MG10_2_11PL ~(1 << 0) +#else +#define MG10_2_11PL 0xFFFF +#endif + +#if (G10_3PL >= G10_2PL) || (G10_3PL == 0) +#define MG10_2_13PL ~(1 << 2) +#else +#define MG10_2_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_2PL) || (G10_4PL == 0) +#define MG10_2_14PL ~(1 << 3) +#else +#define MG10_2_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_2PL) || (G10_5PL == 0) +#define MG10_2_15PL ~(1 << 4) +#else +#define MG10_2_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_2PL) || (G10_6PL == 0) +#define MG10_2_16PL ~(1 << 5) +#else +#define MG10_2_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_2PL) || (G10_7PL == 0) +#define MG10_2_17PL ~(1 << 6) +#else +#define MG10_2_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_2PL) || (G10_8PL == 0) +#define MG10_2_18PL ~(1 << 7) +#else +#define MG10_2_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_2PL) || (G10_9PL == 0) +#define MG10_2_19PL ~(1 << 8) +#else +#define MG10_2_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_2PL) || (G10_10PL == 0) +#define MG10_2_110PL ~(1 << 9) +#else +#define MG10_2_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_2PL) || (G10_11PL == 0) +#define MG10_2_111PL ~(1 << 10) +#else +#define MG10_2_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_2PL) || (G10_12PL == 0) +#define MG10_2_112PL ~(1 << 11) +#else +#define MG10_2_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_2PL) || (G10_13PL == 0) +#define MG10_2_113PL ~(1 << 12) +#else +#define MG10_2_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_2PL) || (G10_14PL == 0) +#define MG10_2_114PL ~(1 << 13) +#else +#define MG10_2_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_2PL) || (G10_15PL == 0) +#define MG10_2_115PL ~(1 << 14) +#else +#define MG10_2_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_2PL) || (G10_16PL == 0) +#define MG10_2_116PL ~(1 << 15) +#else +#define MG10_2_116PL 0xFFFF +#endif + +#define MG10_2_12PL 0xFFFD +#define MG10_2 (MG10_2_11PL & MG10_2_12PL & MG10_2_13PL & MG10_2_14PL & \ + MG10_2_15PL & MG10_2_16PL & MG10_2_17PL & MG10_2_18PL & \ + MG10_2_19PL & MG10_2_110PL & MG10_2_111PL & MG10_2_112PL & \ + MG10_2_113PL & MG10_2_114PL & MG10_2_115PL & MG10_2_116PL) +// End of MG10_2: +// Beginning of MG103: +#if (G10_1PL >= G10_3PL) || (G10_1PL == 0) +#define MG10_3_11PL ~(1 << 0) +#else +#define MG10_3_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_3PL) || (G10_2PL == 0) +#define MG10_3_12PL ~(1 << 1) +#else +#define MG10_3_12PL 0xFFFF +#endif + +#if (G10_4PL >= G10_3PL) || (G10_4PL == 0) +#define MG10_3_14PL ~(1 << 3) +#else +#define MG10_3_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_3PL) || (G10_5PL == 0) +#define MG10_3_15PL ~(1 << 4) +#else +#define MG10_3_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_3PL) || (G10_6PL == 0) +#define MG10_3_16PL ~(1 << 5) +#else +#define MG10_3_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_3PL) || (G10_7PL == 0) +#define MG10_3_17PL ~(1 << 6) +#else +#define MG10_3_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_3PL) || (G10_8PL == 0) +#define MG10_3_18PL ~(1 << 7) +#else +#define MG10_3_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_3PL) || (G10_9PL == 0) +#define MG10_3_19PL ~(1 << 8) +#else +#define MG10_3_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_3PL) || (G10_10PL == 0) +#define MG10_3_110PL ~(1 << 9) +#else +#define MG10_3_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_3PL) || (G10_11PL == 0) +#define MG10_3_111PL ~(1 << 10) +#else +#define MG10_3_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_3PL) || (G10_12PL == 0) +#define MG10_3_112PL ~(1 << 11) +#else +#define MG10_3_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_3PL) || (G10_13PL == 0) +#define MG10_3_113PL ~(1 << 12) +#else +#define MG10_3_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_3PL) || (G10_14PL == 0) +#define MG10_3_114PL ~(1 << 13) +#else +#define MG10_3_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_3PL) || (G10_15PL == 0) +#define MG10_3_115PL ~(1 << 14) +#else +#define MG10_3_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_3PL) || (G10_16PL == 0) +#define MG10_3_116PL ~(1 << 15) +#else +#define MG10_3_116PL 0xFFFF +#endif + +#define MG10_3_13PL 0xFFFB +#define MG10_3 (MG10_3_11PL & MG10_3_12PL & MG10_3_13PL & MG10_3_14PL & \ + MG10_3_15PL & MG10_3_16PL & MG10_3_17PL & MG10_3_18PL & \ + MG10_3_19PL & MG10_3_110PL & MG10_3_111PL & MG10_3_112PL & \ + MG10_3_113PL & MG10_3_114PL & MG10_3_115PL & MG10_3_116PL) +// End of MG10_3: +// Beginning of MG104: +#if (G10_1PL >= G10_4PL) || (G10_1PL == 0) +#define MG10_4_11PL ~(1 << 0) +#else +#define MG10_4_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_4PL) || (G10_2PL == 0) +#define MG10_4_12PL ~(1 << 1) +#else +#define MG10_4_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_4PL) || (G10_3PL == 0) +#define MG10_4_13PL ~(1 << 2) +#else +#define MG10_4_13PL 0xFFFF +#endif + +#if (G10_5PL >= G10_4PL) || (G10_5PL == 0) +#define MG10_4_15PL ~(1 << 4) +#else +#define MG10_4_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_4PL) || (G10_6PL == 0) +#define MG10_4_16PL ~(1 << 5) +#else +#define MG10_4_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_4PL) || (G10_7PL == 0) +#define MG10_4_17PL ~(1 << 6) +#else +#define MG10_4_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_4PL) || (G10_8PL == 0) +#define MG10_4_18PL ~(1 << 7) +#else +#define MG10_4_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_4PL) || (G10_9PL == 0) +#define MG10_4_19PL ~(1 << 8) +#else +#define MG10_4_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_4PL) || (G10_10PL == 0) +#define MG10_4_110PL ~(1 << 9) +#else +#define MG10_4_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_4PL) || (G10_11PL == 0) +#define MG10_4_111PL ~(1 << 10) +#else +#define MG10_4_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_4PL) || (G10_12PL == 0) +#define MG10_4_112PL ~(1 << 11) +#else +#define MG10_4_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_4PL) || (G10_13PL == 0) +#define MG10_4_113PL ~(1 << 12) +#else +#define MG10_4_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_4PL) || (G10_14PL == 0) +#define MG10_4_114PL ~(1 << 13) +#else +#define MG10_4_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_4PL) || (G10_15PL == 0) +#define MG10_4_115PL ~(1 << 14) +#else +#define MG10_4_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_4PL) || (G10_16PL == 0) +#define MG10_4_116PL ~(1 << 15) +#else +#define MG10_4_116PL 0xFFFF +#endif + +#define MG10_4_14PL 0xFFF7 +#define MG10_4 (MG10_4_11PL & MG10_4_12PL & MG10_4_13PL & MG10_4_14PL & \ + MG10_4_15PL & MG10_4_16PL & MG10_4_17PL & MG10_4_18PL & \ + MG10_4_19PL & MG10_4_110PL & MG10_4_111PL & MG10_4_112PL & \ + MG10_4_113PL & MG10_4_114PL & MG10_4_115PL & MG10_4_116PL) +// End of MG10_4: +// Beginning of MG105: +#if (G10_1PL >= G10_5PL) || (G10_1PL == 0) +#define MG10_5_11PL ~(1 << 0) +#else +#define MG10_5_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_5PL) || (G10_2PL == 0) +#define MG10_5_12PL ~(1 << 1) +#else +#define MG10_5_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_5PL) || (G10_3PL == 0) +#define MG10_5_13PL ~(1 << 2) +#else +#define MG10_5_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_5PL) || (G10_4PL == 0) +#define MG10_5_14PL ~(1 << 3) +#else +#define MG10_5_14PL 0xFFFF +#endif + +#if (G10_6PL >= G10_5PL) || (G10_6PL == 0) +#define MG10_5_16PL ~(1 << 5) +#else +#define MG10_5_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_5PL) || (G10_7PL == 0) +#define MG10_5_17PL ~(1 << 6) +#else +#define MG10_5_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_5PL) || (G10_8PL == 0) +#define MG10_5_18PL ~(1 << 7) +#else +#define MG10_5_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_5PL) || (G10_9PL == 0) +#define MG10_5_19PL ~(1 << 8) +#else +#define MG10_5_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_5PL) || (G10_10PL == 0) +#define MG10_5_110PL ~(1 << 9) +#else +#define MG10_5_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_5PL) || (G10_11PL == 0) +#define MG10_5_111PL ~(1 << 10) +#else +#define MG10_5_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_5PL) || (G10_12PL == 0) +#define MG10_5_112PL ~(1 << 11) +#else +#define MG10_5_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_5PL) || (G10_13PL == 0) +#define MG10_5_113PL ~(1 << 12) +#else +#define MG10_5_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_5PL) || (G10_14PL == 0) +#define MG10_5_114PL ~(1 << 13) +#else +#define MG10_5_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_5PL) || (G10_15PL == 0) +#define MG10_5_115PL ~(1 << 14) +#else +#define MG10_5_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_5PL) || (G10_16PL == 0) +#define MG10_5_116PL ~(1 << 15) +#else +#define MG10_5_116PL 0xFFFF +#endif + +#define MG10_5_15PL 0xFFEF +#define MG10_5 (MG10_5_11PL & MG10_5_12PL & MG10_5_13PL & MG10_5_14PL & \ + MG10_5_15PL & MG10_5_16PL & MG10_5_17PL & MG10_5_18PL & \ + MG10_5_19PL & MG10_5_110PL & MG10_5_111PL & MG10_5_112PL & \ + MG10_5_113PL & MG10_5_114PL & MG10_5_115PL & MG10_5_116PL) +// End of MG10_5: +// Beginning of MG106: +#if (G10_1PL >= G10_6PL) || (G10_1PL == 0) +#define MG10_6_11PL ~(1 << 0) +#else +#define MG10_6_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_6PL) || (G10_2PL == 0) +#define MG10_6_12PL ~(1 << 1) +#else +#define MG10_6_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_6PL) || (G10_3PL == 0) +#define MG10_6_13PL ~(1 << 2) +#else +#define MG10_6_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_6PL) || (G10_4PL == 0) +#define MG10_6_14PL ~(1 << 3) +#else +#define MG10_6_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_6PL) || (G10_5PL == 0) +#define MG10_6_15PL ~(1 << 4) +#else +#define MG10_6_15PL 0xFFFF +#endif + +#if (G10_7PL >= G10_6PL) || (G10_7PL == 0) +#define MG10_6_17PL ~(1 << 6) +#else +#define MG10_6_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_6PL) || (G10_8PL == 0) +#define MG10_6_18PL ~(1 << 7) +#else +#define MG10_6_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_6PL) || (G10_9PL == 0) +#define MG10_6_19PL ~(1 << 8) +#else +#define MG10_6_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_6PL) || (G10_10PL == 0) +#define MG10_6_110PL ~(1 << 9) +#else +#define MG10_6_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_6PL) || (G10_11PL == 0) +#define MG10_6_111PL ~(1 << 10) +#else +#define MG10_6_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_6PL) || (G10_12PL == 0) +#define MG10_6_112PL ~(1 << 11) +#else +#define MG10_6_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_6PL) || (G10_13PL == 0) +#define MG10_6_113PL ~(1 << 12) +#else +#define MG10_6_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_6PL) || (G10_14PL == 0) +#define MG10_6_114PL ~(1 << 13) +#else +#define MG10_6_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_6PL) || (G10_15PL == 0) +#define MG10_6_115PL ~(1 << 14) +#else +#define MG10_6_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_6PL) || (G10_16PL == 0) +#define MG10_6_116PL ~(1 << 15) +#else +#define MG10_6_116PL 0xFFFF +#endif + +#define MG10_6_16PL 0xFFDF +#define MG10_6 (MG10_6_11PL & MG10_6_12PL & MG10_6_13PL & MG10_6_14PL & \ + MG10_6_15PL & MG10_6_16PL & MG10_6_17PL & MG10_6_18PL & \ + MG10_6_19PL & MG10_6_110PL & MG10_6_111PL & MG10_6_112PL & \ + MG10_6_113PL & MG10_6_114PL & MG10_6_115PL & MG10_6_116PL) +// End of MG10_6: +// Beginning of MG107: +#if (G10_1PL >= G10_7PL) || (G10_1PL == 0) +#define MG10_7_11PL ~(1 << 0) +#else +#define MG10_7_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_7PL) || (G10_2PL == 0) +#define MG10_7_12PL ~(1 << 1) +#else +#define MG10_7_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_7PL) || (G10_3PL == 0) +#define MG10_7_13PL ~(1 << 2) +#else +#define MG10_7_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_7PL) || (G10_4PL == 0) +#define MG10_7_14PL ~(1 << 3) +#else +#define MG10_7_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_7PL) || (G10_5PL == 0) +#define MG10_7_15PL ~(1 << 4) +#else +#define MG10_7_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_7PL) || (G10_6PL == 0) +#define MG10_7_16PL ~(1 << 5) +#else +#define MG10_7_16PL 0xFFFF +#endif + +#if (G10_8PL >= G10_7PL) || (G10_8PL == 0) +#define MG10_7_18PL ~(1 << 7) +#else +#define MG10_7_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_7PL) || (G10_9PL == 0) +#define MG10_7_19PL ~(1 << 8) +#else +#define MG10_7_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_7PL) || (G10_10PL == 0) +#define MG10_7_110PL ~(1 << 9) +#else +#define MG10_7_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_7PL) || (G10_11PL == 0) +#define MG10_7_111PL ~(1 << 10) +#else +#define MG10_7_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_7PL) || (G10_12PL == 0) +#define MG10_7_112PL ~(1 << 11) +#else +#define MG10_7_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_7PL) || (G10_13PL == 0) +#define MG10_7_113PL ~(1 << 12) +#else +#define MG10_7_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_7PL) || (G10_14PL == 0) +#define MG10_7_114PL ~(1 << 13) +#else +#define MG10_7_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_7PL) || (G10_15PL == 0) +#define MG10_7_115PL ~(1 << 14) +#else +#define MG10_7_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_7PL) || (G10_16PL == 0) +#define MG10_7_116PL ~(1 << 15) +#else +#define MG10_7_116PL 0xFFFF +#endif + +#define MG10_7_17PL 0xFFBF +#define MG10_7 (MG10_7_11PL & MG10_7_12PL & MG10_7_13PL & MG10_7_14PL & \ + MG10_7_15PL & MG10_7_16PL & MG10_7_17PL & MG10_7_18PL & \ + MG10_7_19PL & MG10_7_110PL & MG10_7_111PL & MG10_7_112PL & \ + MG10_7_113PL & MG10_7_114PL & MG10_7_115PL & MG10_7_116PL) +// End of MG10_7: +// Beginning of MG108: +#if (G10_1PL >= G10_8PL) || (G10_1PL == 0) +#define MG10_8_11PL ~(1 << 0) +#else +#define MG10_8_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_8PL) || (G10_2PL == 0) +#define MG10_8_12PL ~(1 << 1) +#else +#define MG10_8_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_8PL) || (G10_3PL == 0) +#define MG10_8_13PL ~(1 << 2) +#else +#define MG10_8_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_8PL) || (G10_4PL == 0) +#define MG10_8_14PL ~(1 << 3) +#else +#define MG10_8_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_8PL) || (G10_5PL == 0) +#define MG10_8_15PL ~(1 << 4) +#else +#define MG10_8_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_8PL) || (G10_6PL == 0) +#define MG10_8_16PL ~(1 << 5) +#else +#define MG10_8_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_8PL) || (G10_7PL == 0) +#define MG10_8_17PL ~(1 << 6) +#else +#define MG10_8_17PL 0xFFFF +#endif + +#if (G10_9PL >= G10_8PL) || (G10_9PL == 0) +#define MG10_8_19PL ~(1 << 8) +#else +#define MG10_8_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_8PL) || (G10_10PL == 0) +#define MG10_8_110PL ~(1 << 9) +#else +#define MG10_8_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_8PL) || (G10_11PL == 0) +#define MG10_8_111PL ~(1 << 10) +#else +#define MG10_8_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_8PL) || (G10_12PL == 0) +#define MG10_8_112PL ~(1 << 11) +#else +#define MG10_8_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_8PL) || (G10_13PL == 0) +#define MG10_8_113PL ~(1 << 12) +#else +#define MG10_8_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_8PL) || (G10_14PL == 0) +#define MG10_8_114PL ~(1 << 13) +#else +#define MG10_8_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_8PL) || (G10_15PL == 0) +#define MG10_8_115PL ~(1 << 14) +#else +#define MG10_8_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_8PL) || (G10_16PL == 0) +#define MG10_8_116PL ~(1 << 15) +#else +#define MG10_8_116PL 0xFFFF +#endif + +#define MG10_8_18PL 0xFF7F +#define MG10_8 (MG10_8_11PL & MG10_8_12PL & MG10_8_13PL & MG10_8_14PL & \ + MG10_8_15PL & MG10_8_16PL & MG10_8_17PL & MG10_8_18PL & \ + MG10_8_19PL & MG10_8_110PL & MG10_8_111PL & MG10_8_112PL & \ + MG10_8_113PL & MG10_8_114PL & MG10_8_115PL & MG10_8_116PL) +// End of MG10_8: +// Beginning of MG109: +#if (G10_1PL >= G10_9PL) || (G10_1PL == 0) +#define MG10_9_11PL ~(1 << 0) +#else +#define MG10_9_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_9PL) || (G10_2PL == 0) +#define MG10_9_12PL ~(1 << 1) +#else +#define MG10_9_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_9PL) || (G10_3PL == 0) +#define MG10_9_13PL ~(1 << 2) +#else +#define MG10_9_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_9PL) || (G10_4PL == 0) +#define MG10_9_14PL ~(1 << 3) +#else +#define MG10_9_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_9PL) || (G10_5PL == 0) +#define MG10_9_15PL ~(1 << 4) +#else +#define MG10_9_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_9PL) || (G10_6PL == 0) +#define MG10_9_16PL ~(1 << 5) +#else +#define MG10_9_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_9PL) || (G10_7PL == 0) +#define MG10_9_17PL ~(1 << 6) +#else +#define MG10_9_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_9PL) || (G10_8PL == 0) +#define MG10_9_18PL ~(1 << 7) +#else +#define MG10_9_18PL 0xFFFF +#endif + +#if (G10_10PL >= G10_9PL) || (G10_10PL == 0) +#define MG10_9_110PL ~(1 << 9) +#else +#define MG10_9_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_9PL) || (G10_11PL == 0) +#define MG10_9_111PL ~(1 << 10) +#else +#define MG10_9_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_9PL) || (G10_12PL == 0) +#define MG10_9_112PL ~(1 << 11) +#else +#define MG10_9_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_9PL) || (G10_13PL == 0) +#define MG10_9_113PL ~(1 << 12) +#else +#define MG10_9_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_9PL) || (G10_14PL == 0) +#define MG10_9_114PL ~(1 << 13) +#else +#define MG10_9_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_9PL) || (G10_15PL == 0) +#define MG10_9_115PL ~(1 << 14) +#else +#define MG10_9_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_9PL) || (G10_16PL == 0) +#define MG10_9_116PL ~(1 << 15) +#else +#define MG10_9_116PL 0xFFFF +#endif + +#define MG10_9_19PL 0xFEFF +#define MG10_9 (MG10_9_11PL & MG10_9_12PL & MG10_9_13PL & MG10_9_14PL & \ + MG10_9_15PL & MG10_9_16PL & MG10_9_17PL & MG10_9_18PL & \ + MG10_9_19PL & MG10_9_110PL & MG10_9_111PL & MG10_9_112PL & \ + MG10_9_113PL & MG10_9_114PL & MG10_9_115PL & MG10_9_116PL) +// End of MG10_9: +// Beginning of MG1010: +#if (G10_1PL >= G10_10PL) || (G10_1PL == 0) +#define MG10_10_11PL ~(1 << 0) +#else +#define MG10_10_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_10PL) || (G10_2PL == 0) +#define MG10_10_12PL ~(1 << 1) +#else +#define MG10_10_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_10PL) || (G10_3PL == 0) +#define MG10_10_13PL ~(1 << 2) +#else +#define MG10_10_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_10PL) || (G10_4PL == 0) +#define MG10_10_14PL ~(1 << 3) +#else +#define MG10_10_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_10PL) || (G10_5PL == 0) +#define MG10_10_15PL ~(1 << 4) +#else +#define MG10_10_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_10PL) || (G10_6PL == 0) +#define MG10_10_16PL ~(1 << 5) +#else +#define MG10_10_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_10PL) || (G10_7PL == 0) +#define MG10_10_17PL ~(1 << 6) +#else +#define MG10_10_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_10PL) || (G10_8PL == 0) +#define MG10_10_18PL ~(1 << 7) +#else +#define MG10_10_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_10PL) || (G10_9PL == 0) +#define MG10_10_19PL ~(1 << 8) +#else +#define MG10_10_19PL 0xFFFF +#endif + +#if (G10_11PL >= G10_10PL) || (G10_11PL == 0) +#define MG10_10_111PL ~(1 << 10) +#else +#define MG10_10_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_10PL) || (G10_12PL == 0) +#define MG10_10_112PL ~(1 << 11) +#else +#define MG10_10_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_10PL) || (G10_13PL == 0) +#define MG10_10_113PL ~(1 << 12) +#else +#define MG10_10_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_10PL) || (G10_14PL == 0) +#define MG10_10_114PL ~(1 << 13) +#else +#define MG10_10_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_10PL) || (G10_15PL == 0) +#define MG10_10_115PL ~(1 << 14) +#else +#define MG10_10_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_10PL) || (G10_16PL == 0) +#define MG10_10_116PL ~(1 << 15) +#else +#define MG10_10_116PL 0xFFFF +#endif + +#define MG10_10_110PL 0xFDFF +#define MG10_10 (MG10_10_11PL & MG10_10_12PL & MG10_10_13PL & MG10_10_14PL & \ + MG10_10_15PL & MG10_10_16PL & MG10_10_17PL & MG10_10_18PL & \ + MG10_10_19PL & MG10_10_110PL & MG10_10_111PL & MG10_10_112PL & \ + MG10_10_113PL & MG10_10_114PL & MG10_10_115PL & MG10_10_116PL) +// End of MG10_10: +// Beginning of MG1011: +#if (G10_1PL >= G10_11PL) || (G10_1PL == 0) +#define MG10_11_11PL ~(1 << 0) +#else +#define MG10_11_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_11PL) || (G10_2PL == 0) +#define MG10_11_12PL ~(1 << 1) +#else +#define MG10_11_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_11PL) || (G10_3PL == 0) +#define MG10_11_13PL ~(1 << 2) +#else +#define MG10_11_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_11PL) || (G10_4PL == 0) +#define MG10_11_14PL ~(1 << 3) +#else +#define MG10_11_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_11PL) || (G10_5PL == 0) +#define MG10_11_15PL ~(1 << 4) +#else +#define MG10_11_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_11PL) || (G10_6PL == 0) +#define MG10_11_16PL ~(1 << 5) +#else +#define MG10_11_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_11PL) || (G10_7PL == 0) +#define MG10_11_17PL ~(1 << 6) +#else +#define MG10_11_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_11PL) || (G10_8PL == 0) +#define MG10_11_18PL ~(1 << 7) +#else +#define MG10_11_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_11PL) || (G10_9PL == 0) +#define MG10_11_19PL ~(1 << 8) +#else +#define MG10_11_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_11PL) || (G10_10PL == 0) +#define MG10_11_110PL ~(1 << 9) +#else +#define MG10_11_110PL 0xFFFF +#endif + +#if (G10_12PL >= G10_11PL) || (G10_12PL == 0) +#define MG10_11_112PL ~(1 << 11) +#else +#define MG10_11_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_11PL) || (G10_13PL == 0) +#define MG10_11_113PL ~(1 << 12) +#else +#define MG10_11_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_11PL) || (G10_14PL == 0) +#define MG10_11_114PL ~(1 << 13) +#else +#define MG10_11_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_11PL) || (G10_15PL == 0) +#define MG10_11_115PL ~(1 << 14) +#else +#define MG10_11_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_11PL) || (G10_16PL == 0) +#define MG10_11_116PL ~(1 << 15) +#else +#define MG10_11_116PL 0xFFFF +#endif + +#define MG10_11_111PL 0xFBFF +#define MG10_11 (MG10_11_11PL & MG10_11_12PL & MG10_11_13PL & MG10_11_14PL & \ + MG10_11_15PL & MG10_11_16PL & MG10_11_17PL & MG10_11_18PL & \ + MG10_11_19PL & MG10_11_110PL & MG10_11_111PL & MG10_11_112PL & \ + MG10_11_113PL & MG10_11_114PL & MG10_11_115PL & MG10_11_116PL) +// End of MG10_11: +// Beginning of MG1012: +#if (G10_1PL >= G10_12PL) || (G10_1PL == 0) +#define MG10_12_11PL ~(1 << 0) +#else +#define MG10_12_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_12PL) || (G10_2PL == 0) +#define MG10_12_12PL ~(1 << 1) +#else +#define MG10_12_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_12PL) || (G10_3PL == 0) +#define MG10_12_13PL ~(1 << 2) +#else +#define MG10_12_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_12PL) || (G10_4PL == 0) +#define MG10_12_14PL ~(1 << 3) +#else +#define MG10_12_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_12PL) || (G10_5PL == 0) +#define MG10_12_15PL ~(1 << 4) +#else +#define MG10_12_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_12PL) || (G10_6PL == 0) +#define MG10_12_16PL ~(1 << 5) +#else +#define MG10_12_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_12PL) || (G10_7PL == 0) +#define MG10_12_17PL ~(1 << 6) +#else +#define MG10_12_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_12PL) || (G10_8PL == 0) +#define MG10_12_18PL ~(1 << 7) +#else +#define MG10_12_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_12PL) || (G10_9PL == 0) +#define MG10_12_19PL ~(1 << 8) +#else +#define MG10_12_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_12PL) || (G10_10PL == 0) +#define MG10_12_110PL ~(1 << 9) +#else +#define MG10_12_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_12PL) || (G10_11PL == 0) +#define MG10_12_111PL ~(1 << 10) +#else +#define MG10_12_111PL 0xFFFF +#endif + +#if (G10_13PL >= G10_12PL) || (G10_13PL == 0) +#define MG10_12_113PL ~(1 << 12) +#else +#define MG10_12_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_12PL) || (G10_14PL == 0) +#define MG10_12_114PL ~(1 << 13) +#else +#define MG10_12_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_12PL) || (G10_15PL == 0) +#define MG10_12_115PL ~(1 << 14) +#else +#define MG10_12_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_12PL) || (G10_16PL == 0) +#define MG10_12_116PL ~(1 << 15) +#else +#define MG10_12_116PL 0xFFFF +#endif + +#define MG10_12_112PL 0xF7FF +#define MG10_12 (MG10_12_11PL & MG10_12_12PL & MG10_12_13PL & MG10_12_14PL & \ + MG10_12_15PL & MG10_12_16PL & MG10_12_17PL & MG10_12_18PL & \ + MG10_12_19PL & MG10_12_110PL & MG10_12_111PL & MG10_12_112PL & \ + MG10_12_113PL & MG10_12_114PL & MG10_12_115PL & MG10_12_116PL) +// End of MG10_12: +// Beginning of MG1013: +#if (G10_1PL >= G10_13PL) || (G10_1PL == 0) +#define MG10_13_11PL ~(1 << 0) +#else +#define MG10_13_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_13PL) || (G10_2PL == 0) +#define MG10_13_12PL ~(1 << 1) +#else +#define MG10_13_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_13PL) || (G10_3PL == 0) +#define MG10_13_13PL ~(1 << 2) +#else +#define MG10_13_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_13PL) || (G10_4PL == 0) +#define MG10_13_14PL ~(1 << 3) +#else +#define MG10_13_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_13PL) || (G10_5PL == 0) +#define MG10_13_15PL ~(1 << 4) +#else +#define MG10_13_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_13PL) || (G10_6PL == 0) +#define MG10_13_16PL ~(1 << 5) +#else +#define MG10_13_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_13PL) || (G10_7PL == 0) +#define MG10_13_17PL ~(1 << 6) +#else +#define MG10_13_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_13PL) || (G10_8PL == 0) +#define MG10_13_18PL ~(1 << 7) +#else +#define MG10_13_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_13PL) || (G10_9PL == 0) +#define MG10_13_19PL ~(1 << 8) +#else +#define MG10_13_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_13PL) || (G10_10PL == 0) +#define MG10_13_110PL ~(1 << 9) +#else +#define MG10_13_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_13PL) || (G10_11PL == 0) +#define MG10_13_111PL ~(1 << 10) +#else +#define MG10_13_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_13PL) || (G10_12PL == 0) +#define MG10_13_112PL ~(1 << 11) +#else +#define MG10_13_112PL 0xFFFF +#endif + +#if (G10_14PL >= G10_13PL) || (G10_14PL == 0) +#define MG10_13_114PL ~(1 << 13) +#else +#define MG10_13_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_13PL) || (G10_15PL == 0) +#define MG10_13_115PL ~(1 << 14) +#else +#define MG10_13_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_13PL) || (G10_16PL == 0) +#define MG10_13_116PL ~(1 << 15) +#else +#define MG10_13_116PL 0xFFFF +#endif + +#define MG10_13_113PL 0xEFFF +#define MG10_13 (MG10_13_11PL & MG10_13_12PL & MG10_13_13PL & MG10_13_14PL & \ + MG10_13_15PL & MG10_13_16PL & MG10_13_17PL & MG10_13_18PL & \ + MG10_13_19PL & MG10_13_110PL & MG10_13_111PL & MG10_13_112PL & \ + MG10_13_113PL & MG10_13_114PL & MG10_13_115PL & MG10_13_116PL) +// End of MG10_13: +// Beginning of MG1014: +#if (G10_1PL >= G10_14PL) || (G10_1PL == 0) +#define MG10_14_11PL ~(1 << 0) +#else +#define MG10_14_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_14PL) || (G10_2PL == 0) +#define MG10_14_12PL ~(1 << 1) +#else +#define MG10_14_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_14PL) || (G10_3PL == 0) +#define MG10_14_13PL ~(1 << 2) +#else +#define MG10_14_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_14PL) || (G10_4PL == 0) +#define MG10_14_14PL ~(1 << 3) +#else +#define MG10_14_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_14PL) || (G10_5PL == 0) +#define MG10_14_15PL ~(1 << 4) +#else +#define MG10_14_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_14PL) || (G10_6PL == 0) +#define MG10_14_16PL ~(1 << 5) +#else +#define MG10_14_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_14PL) || (G10_7PL == 0) +#define MG10_14_17PL ~(1 << 6) +#else +#define MG10_14_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_14PL) || (G10_8PL == 0) +#define MG10_14_18PL ~(1 << 7) +#else +#define MG10_14_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_14PL) || (G10_9PL == 0) +#define MG10_14_19PL ~(1 << 8) +#else +#define MG10_14_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_14PL) || (G10_10PL == 0) +#define MG10_14_110PL ~(1 << 9) +#else +#define MG10_14_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_14PL) || (G10_11PL == 0) +#define MG10_14_111PL ~(1 << 10) +#else +#define MG10_14_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_14PL) || (G10_12PL == 0) +#define MG10_14_112PL ~(1 << 11) +#else +#define MG10_14_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_14PL) || (G10_13PL == 0) +#define MG10_14_113PL ~(1 << 12) +#else +#define MG10_14_113PL 0xFFFF +#endif + +#if (G10_15PL >= G10_14PL) || (G10_15PL == 0) +#define MG10_14_115PL ~(1 << 14) +#else +#define MG10_14_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_14PL) || (G10_16PL == 0) +#define MG10_14_116PL ~(1 << 15) +#else +#define MG10_14_116PL 0xFFFF +#endif + +#define MG10_14_114PL 0xDFFF +#define MG10_14 (MG10_14_11PL & MG10_14_12PL & MG10_14_13PL & MG10_14_14PL & \ + MG10_14_15PL & MG10_14_16PL & MG10_14_17PL & MG10_14_18PL & \ + MG10_14_19PL & MG10_14_110PL & MG10_14_111PL & MG10_14_112PL & \ + MG10_14_113PL & MG10_14_114PL & MG10_14_115PL & MG10_14_116PL) +// End of MG10_14: +// Beginning of MG1015: +#if (G10_1PL >= G10_15PL) || (G10_1PL == 0) +#define MG10_15_11PL ~(1 << 0) +#else +#define MG10_15_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_15PL) || (G10_2PL == 0) +#define MG10_15_12PL ~(1 << 1) +#else +#define MG10_15_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_15PL) || (G10_3PL == 0) +#define MG10_15_13PL ~(1 << 2) +#else +#define MG10_15_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_15PL) || (G10_4PL == 0) +#define MG10_15_14PL ~(1 << 3) +#else +#define MG10_15_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_15PL) || (G10_5PL == 0) +#define MG10_15_15PL ~(1 << 4) +#else +#define MG10_15_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_15PL) || (G10_6PL == 0) +#define MG10_15_16PL ~(1 << 5) +#else +#define MG10_15_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_15PL) || (G10_7PL == 0) +#define MG10_15_17PL ~(1 << 6) +#else +#define MG10_15_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_15PL) || (G10_8PL == 0) +#define MG10_15_18PL ~(1 << 7) +#else +#define MG10_15_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_15PL) || (G10_9PL == 0) +#define MG10_15_19PL ~(1 << 8) +#else +#define MG10_15_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_15PL) || (G10_10PL == 0) +#define MG10_15_110PL ~(1 << 9) +#else +#define MG10_15_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_15PL) || (G10_11PL == 0) +#define MG10_15_111PL ~(1 << 10) +#else +#define MG10_15_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_15PL) || (G10_12PL == 0) +#define MG10_15_112PL ~(1 << 11) +#else +#define MG10_15_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_15PL) || (G10_13PL == 0) +#define MG10_15_113PL ~(1 << 12) +#else +#define MG10_15_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_15PL) || (G10_14PL == 0) +#define MG10_15_114PL ~(1 << 13) +#else +#define MG10_15_114PL 0xFFFF +#endif + +#if (G10_16PL >= G10_15PL) || (G10_16PL == 0) +#define MG10_15_116PL ~(1 << 15) +#else +#define MG10_15_116PL 0xFFFF +#endif + +#define MG10_15_115PL 0xBFFF +#define MG10_15 (MG10_15_11PL & MG10_15_12PL & MG10_15_13PL & MG10_15_14PL & \ + MG10_15_15PL & MG10_15_16PL & MG10_15_17PL & MG10_15_18PL & \ + MG10_15_19PL & MG10_15_110PL & MG10_15_111PL & MG10_15_112PL & \ + MG10_15_113PL & MG10_15_114PL & MG10_15_115PL & MG10_15_116PL) +// End of MG10_15: +// Beginning of MG1016: +#if (G10_1PL >= G10_16PL) || (G10_1PL == 0) +#define MG10_16_11PL ~(1 << 0) +#else +#define MG10_16_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_16PL) || (G10_2PL == 0) +#define MG10_16_12PL ~(1 << 1) +#else +#define MG10_16_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_16PL) || (G10_3PL == 0) +#define MG10_16_13PL ~(1 << 2) +#else +#define MG10_16_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_16PL) || (G10_4PL == 0) +#define MG10_16_14PL ~(1 << 3) +#else +#define MG10_16_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_16PL) || (G10_5PL == 0) +#define MG10_16_15PL ~(1 << 4) +#else +#define MG10_16_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_16PL) || (G10_6PL == 0) +#define MG10_16_16PL ~(1 << 5) +#else +#define MG10_16_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_16PL) || (G10_7PL == 0) +#define MG10_16_17PL ~(1 << 6) +#else +#define MG10_16_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_16PL) || (G10_8PL == 0) +#define MG10_16_18PL ~(1 << 7) +#else +#define MG10_16_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_16PL) || (G10_9PL == 0) +#define MG10_16_19PL ~(1 << 8) +#else +#define MG10_16_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_16PL) || (G10_10PL == 0) +#define MG10_16_110PL ~(1 << 9) +#else +#define MG10_16_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_16PL) || (G10_11PL == 0) +#define MG10_16_111PL ~(1 << 10) +#else +#define MG10_16_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_16PL) || (G10_12PL == 0) +#define MG10_16_112PL ~(1 << 11) +#else +#define MG10_16_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_16PL) || (G10_13PL == 0) +#define MG10_16_113PL ~(1 << 12) +#else +#define MG10_16_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_16PL) || (G10_14PL == 0) +#define MG10_16_114PL ~(1 << 13) +#else +#define MG10_16_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_16PL) || (G10_15PL == 0) +#define MG10_16_115PL ~(1 << 14) +#else +#define MG10_16_115PL 0xFFFF +#endif + +#define MG10_16_116PL 0x7FFF +#define MG10_16 (MG10_16_11PL & MG10_16_12PL & MG10_16_13PL & MG10_16_14PL & \ + MG10_16_15PL & MG10_16_16PL & MG10_16_17PL & MG10_16_18PL & \ + MG10_16_19PL & MG10_16_110PL & MG10_16_111PL & MG10_16_112PL & \ + MG10_16_113PL & MG10_16_114PL & MG10_16_115PL & MG10_16_116PL) +// End of MG10_16: + + +// +// Automatically generate PIEIER11 interrupt masks MG111 to MG1116: +// + +// Beginning of MG111: +#if (G11_2PL >= G11_1PL) || (G11_2PL == 0) +#define MG11_1_12PL ~(1 << 1) +#else +#define MG11_1_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_1PL) || (G11_3PL == 0) +#define MG11_1_13PL ~(1 << 2) +#else +#define MG11_1_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_1PL) || (G11_4PL == 0) +#define MG11_1_14PL ~(1 << 3) +#else +#define MG11_1_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_1PL) || (G11_5PL == 0) +#define MG11_1_15PL ~(1 << 4) +#else +#define MG11_1_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_1PL) || (G11_6PL == 0) +#define MG11_1_16PL ~(1 << 5) +#else +#define MG11_1_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_1PL) || (G11_7PL == 0) +#define MG11_1_17PL ~(1 << 6) +#else +#define MG11_1_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_1PL) || (G11_8PL == 0) +#define MG11_1_18PL ~(1 << 7) +#else +#define MG11_1_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_1PL) || (G11_9PL == 0) +#define MG11_1_19PL ~(1 << 8) +#else +#define MG11_1_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_1PL) || (G11_10PL == 0) +#define MG11_1_110PL ~(1 << 9) +#else +#define MG11_1_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_1PL) || (G11_11PL == 0) +#define MG11_1_111PL ~(1 << 10) +#else +#define MG11_1_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_1PL) || (G11_12PL == 0) +#define MG11_1_112PL ~(1 << 11) +#else +#define MG11_1_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_1PL) || (G11_13PL == 0) +#define MG11_1_113PL ~(1 << 12) +#else +#define MG11_1_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_1PL) || (G11_14PL == 0) +#define MG11_1_114PL ~(1 << 13) +#else +#define MG11_1_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_1PL) || (G11_15PL == 0) +#define MG11_1_115PL ~(1 << 14) +#else +#define MG11_1_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_1PL) || (G11_16PL == 0) +#define MG11_1_116PL ~(1 << 15) +#else +#define MG11_1_116PL 0xFFFF +#endif + +#define MG11_1_11PL 0xFFFE +#define MG11_1 (MG11_1_11PL & MG11_1_12PL & MG11_1_13PL & MG11_1_14PL & \ + MG11_1_15PL & MG11_1_16PL & MG11_1_17PL & MG11_1_18PL & \ + MG11_1_19PL & MG11_1_110PL & MG11_1_111PL & MG11_1_112PL & \ + MG11_1_113PL & MG11_1_114PL & MG11_1_115PL & MG11_1_116PL) +// End of MG11_1: +// Beginning of MG112: +#if (G11_1PL >= G11_2PL) || (G11_1PL == 0) +#define MG11_2_11PL ~(1 << 0) +#else +#define MG11_2_11PL 0xFFFF +#endif + +#if (G11_3PL >= G11_2PL) || (G11_3PL == 0) +#define MG11_2_13PL ~(1 << 2) +#else +#define MG11_2_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_2PL) || (G11_4PL == 0) +#define MG11_2_14PL ~(1 << 3) +#else +#define MG11_2_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_2PL) || (G11_5PL == 0) +#define MG11_2_15PL ~(1 << 4) +#else +#define MG11_2_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_2PL) || (G11_6PL == 0) +#define MG11_2_16PL ~(1 << 5) +#else +#define MG11_2_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_2PL) || (G11_7PL == 0) +#define MG11_2_17PL ~(1 << 6) +#else +#define MG11_2_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_2PL) || (G11_8PL == 0) +#define MG11_2_18PL ~(1 << 7) +#else +#define MG11_2_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_2PL) || (G11_9PL == 0) +#define MG11_2_19PL ~(1 << 8) +#else +#define MG11_2_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_2PL) || (G11_10PL == 0) +#define MG11_2_110PL ~(1 << 9) +#else +#define MG11_2_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_2PL) || (G11_11PL == 0) +#define MG11_2_111PL ~(1 << 10) +#else +#define MG11_2_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_2PL) || (G11_12PL == 0) +#define MG11_2_112PL ~(1 << 11) +#else +#define MG11_2_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_2PL) || (G11_13PL == 0) +#define MG11_2_113PL ~(1 << 12) +#else +#define MG11_2_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_2PL) || (G11_14PL == 0) +#define MG11_2_114PL ~(1 << 13) +#else +#define MG11_2_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_2PL) || (G11_15PL == 0) +#define MG11_2_115PL ~(1 << 14) +#else +#define MG11_2_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_2PL) || (G11_16PL == 0) +#define MG11_2_116PL ~(1 << 15) +#else +#define MG11_2_116PL 0xFFFF +#endif + +#define MG11_2_12PL 0xFFFD +#define MG11_2 (MG11_2_11PL & MG11_2_12PL & MG11_2_13PL & MG11_2_14PL & \ + MG11_2_15PL & MG11_2_16PL & MG11_2_17PL & MG11_2_18PL & \ + MG11_2_19PL & MG11_2_110PL & MG11_2_111PL & MG11_2_112PL & \ + MG11_2_113PL & MG11_2_114PL & MG11_2_115PL & MG11_2_116PL) +// End of MG11_2: +// Beginning of MG113: +#if (G11_1PL >= G11_3PL) || (G11_1PL == 0) +#define MG11_3_11PL ~(1 << 0) +#else +#define MG11_3_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_3PL) || (G11_2PL == 0) +#define MG11_3_12PL ~(1 << 1) +#else +#define MG11_3_12PL 0xFFFF +#endif + +#if (G11_4PL >= G11_3PL) || (G11_4PL == 0) +#define MG11_3_14PL ~(1 << 3) +#else +#define MG11_3_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_3PL) || (G11_5PL == 0) +#define MG11_3_15PL ~(1 << 4) +#else +#define MG11_3_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_3PL) || (G11_6PL == 0) +#define MG11_3_16PL ~(1 << 5) +#else +#define MG11_3_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_3PL) || (G11_7PL == 0) +#define MG11_3_17PL ~(1 << 6) +#else +#define MG11_3_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_3PL) || (G11_8PL == 0) +#define MG11_3_18PL ~(1 << 7) +#else +#define MG11_3_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_3PL) || (G11_9PL == 0) +#define MG11_3_19PL ~(1 << 8) +#else +#define MG11_3_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_3PL) || (G11_10PL == 0) +#define MG11_3_110PL ~(1 << 9) +#else +#define MG11_3_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_3PL) || (G11_11PL == 0) +#define MG11_3_111PL ~(1 << 10) +#else +#define MG11_3_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_3PL) || (G11_12PL == 0) +#define MG11_3_112PL ~(1 << 11) +#else +#define MG11_3_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_3PL) || (G11_13PL == 0) +#define MG11_3_113PL ~(1 << 12) +#else +#define MG11_3_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_3PL) || (G11_14PL == 0) +#define MG11_3_114PL ~(1 << 13) +#else +#define MG11_3_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_3PL) || (G11_15PL == 0) +#define MG11_3_115PL ~(1 << 14) +#else +#define MG11_3_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_3PL) || (G11_16PL == 0) +#define MG11_3_116PL ~(1 << 15) +#else +#define MG11_3_116PL 0xFFFF +#endif + +#define MG11_3_13PL 0xFFFB +#define MG11_3 (MG11_3_11PL & MG11_3_12PL & MG11_3_13PL & MG11_3_14PL & \ + MG11_3_15PL & MG11_3_16PL & MG11_3_17PL & MG11_3_18PL & \ + MG11_3_19PL & MG11_3_110PL & MG11_3_111PL & MG11_3_112PL & \ + MG11_3_113PL & MG11_3_114PL & MG11_3_115PL & MG11_3_116PL) +// End of MG11_3: +// Beginning of MG114: +#if (G11_1PL >= G11_4PL) || (G11_1PL == 0) +#define MG11_4_11PL ~(1 << 0) +#else +#define MG11_4_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_4PL) || (G11_2PL == 0) +#define MG11_4_12PL ~(1 << 1) +#else +#define MG11_4_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_4PL) || (G11_3PL == 0) +#define MG11_4_13PL ~(1 << 2) +#else +#define MG11_4_13PL 0xFFFF +#endif + +#if (G11_5PL >= G11_4PL) || (G11_5PL == 0) +#define MG11_4_15PL ~(1 << 4) +#else +#define MG11_4_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_4PL) || (G11_6PL == 0) +#define MG11_4_16PL ~(1 << 5) +#else +#define MG11_4_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_4PL) || (G11_7PL == 0) +#define MG11_4_17PL ~(1 << 6) +#else +#define MG11_4_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_4PL) || (G11_8PL == 0) +#define MG11_4_18PL ~(1 << 7) +#else +#define MG11_4_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_4PL) || (G11_9PL == 0) +#define MG11_4_19PL ~(1 << 8) +#else +#define MG11_4_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_4PL) || (G11_10PL == 0) +#define MG11_4_110PL ~(1 << 9) +#else +#define MG11_4_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_4PL) || (G11_11PL == 0) +#define MG11_4_111PL ~(1 << 10) +#else +#define MG11_4_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_4PL) || (G11_12PL == 0) +#define MG11_4_112PL ~(1 << 11) +#else +#define MG11_4_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_4PL) || (G11_13PL == 0) +#define MG11_4_113PL ~(1 << 12) +#else +#define MG11_4_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_4PL) || (G11_14PL == 0) +#define MG11_4_114PL ~(1 << 13) +#else +#define MG11_4_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_4PL) || (G11_15PL == 0) +#define MG11_4_115PL ~(1 << 14) +#else +#define MG11_4_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_4PL) || (G11_16PL == 0) +#define MG11_4_116PL ~(1 << 15) +#else +#define MG11_4_116PL 0xFFFF +#endif + +#define MG11_4_14PL 0xFFF7 +#define MG11_4 (MG11_4_11PL & MG11_4_12PL & MG11_4_13PL & MG11_4_14PL & \ + MG11_4_15PL & MG11_4_16PL & MG11_4_17PL & MG11_4_18PL & \ + MG11_4_19PL & MG11_4_110PL & MG11_4_111PL & MG11_4_112PL & \ + MG11_4_113PL & MG11_4_114PL & MG11_4_115PL & MG11_4_116PL) +// End of MG11_4: +// Beginning of MG115: +#if (G11_1PL >= G11_5PL) || (G11_1PL == 0) +#define MG11_5_11PL ~(1 << 0) +#else +#define MG11_5_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_5PL) || (G11_2PL == 0) +#define MG11_5_12PL ~(1 << 1) +#else +#define MG11_5_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_5PL) || (G11_3PL == 0) +#define MG11_5_13PL ~(1 << 2) +#else +#define MG11_5_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_5PL) || (G11_4PL == 0) +#define MG11_5_14PL ~(1 << 3) +#else +#define MG11_5_14PL 0xFFFF +#endif + +#if (G11_6PL >= G11_5PL) || (G11_6PL == 0) +#define MG11_5_16PL ~(1 << 5) +#else +#define MG11_5_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_5PL) || (G11_7PL == 0) +#define MG11_5_17PL ~(1 << 6) +#else +#define MG11_5_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_5PL) || (G11_8PL == 0) +#define MG11_5_18PL ~(1 << 7) +#else +#define MG11_5_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_5PL) || (G11_9PL == 0) +#define MG11_5_19PL ~(1 << 8) +#else +#define MG11_5_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_5PL) || (G11_10PL == 0) +#define MG11_5_110PL ~(1 << 9) +#else +#define MG11_5_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_5PL) || (G11_11PL == 0) +#define MG11_5_111PL ~(1 << 10) +#else +#define MG11_5_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_5PL) || (G11_12PL == 0) +#define MG11_5_112PL ~(1 << 11) +#else +#define MG11_5_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_5PL) || (G11_13PL == 0) +#define MG11_5_113PL ~(1 << 12) +#else +#define MG11_5_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_5PL) || (G11_14PL == 0) +#define MG11_5_114PL ~(1 << 13) +#else +#define MG11_5_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_5PL) || (G11_15PL == 0) +#define MG11_5_115PL ~(1 << 14) +#else +#define MG11_5_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_5PL) || (G11_16PL == 0) +#define MG11_5_116PL ~(1 << 15) +#else +#define MG11_5_116PL 0xFFFF +#endif + +#define MG11_5_15PL 0xFFEF +#define MG11_5 (MG11_5_11PL & MG11_5_12PL & MG11_5_13PL & MG11_5_14PL & \ + MG11_5_15PL & MG11_5_16PL & MG11_5_17PL & MG11_5_18PL & \ + MG11_5_19PL & MG11_5_110PL & MG11_5_111PL & MG11_5_112PL & \ + MG11_5_113PL & MG11_5_114PL & MG11_5_115PL & MG11_5_116PL) +// End of MG11_5: +// Beginning of MG116: +#if (G11_1PL >= G11_6PL) || (G11_1PL == 0) +#define MG11_6_11PL ~(1 << 0) +#else +#define MG11_6_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_6PL) || (G11_2PL == 0) +#define MG11_6_12PL ~(1 << 1) +#else +#define MG11_6_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_6PL) || (G11_3PL == 0) +#define MG11_6_13PL ~(1 << 2) +#else +#define MG11_6_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_6PL) || (G11_4PL == 0) +#define MG11_6_14PL ~(1 << 3) +#else +#define MG11_6_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_6PL) || (G11_5PL == 0) +#define MG11_6_15PL ~(1 << 4) +#else +#define MG11_6_15PL 0xFFFF +#endif + +#if (G11_7PL >= G11_6PL) || (G11_7PL == 0) +#define MG11_6_17PL ~(1 << 6) +#else +#define MG11_6_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_6PL) || (G11_8PL == 0) +#define MG11_6_18PL ~(1 << 7) +#else +#define MG11_6_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_6PL) || (G11_9PL == 0) +#define MG11_6_19PL ~(1 << 8) +#else +#define MG11_6_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_6PL) || (G11_10PL == 0) +#define MG11_6_110PL ~(1 << 9) +#else +#define MG11_6_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_6PL) || (G11_11PL == 0) +#define MG11_6_111PL ~(1 << 10) +#else +#define MG11_6_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_6PL) || (G11_12PL == 0) +#define MG11_6_112PL ~(1 << 11) +#else +#define MG11_6_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_6PL) || (G11_13PL == 0) +#define MG11_6_113PL ~(1 << 12) +#else +#define MG11_6_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_6PL) || (G11_14PL == 0) +#define MG11_6_114PL ~(1 << 13) +#else +#define MG11_6_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_6PL) || (G11_15PL == 0) +#define MG11_6_115PL ~(1 << 14) +#else +#define MG11_6_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_6PL) || (G11_16PL == 0) +#define MG11_6_116PL ~(1 << 15) +#else +#define MG11_6_116PL 0xFFFF +#endif + +#define MG11_6_16PL 0xFFDF +#define MG11_6 (MG11_6_11PL & MG11_6_12PL & MG11_6_13PL & MG11_6_14PL & \ + MG11_6_15PL & MG11_6_16PL & MG11_6_17PL & MG11_6_18PL & \ + MG11_6_19PL & MG11_6_110PL & MG11_6_111PL & MG11_6_112PL & \ + MG11_6_113PL & MG11_6_114PL & MG11_6_115PL & MG11_6_116PL) +// End of MG11_6: +// Beginning of MG117: +#if (G11_1PL >= G11_7PL) || (G11_1PL == 0) +#define MG11_7_11PL ~(1 << 0) +#else +#define MG11_7_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_7PL) || (G11_2PL == 0) +#define MG11_7_12PL ~(1 << 1) +#else +#define MG11_7_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_7PL) || (G11_3PL == 0) +#define MG11_7_13PL ~(1 << 2) +#else +#define MG11_7_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_7PL) || (G11_4PL == 0) +#define MG11_7_14PL ~(1 << 3) +#else +#define MG11_7_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_7PL) || (G11_5PL == 0) +#define MG11_7_15PL ~(1 << 4) +#else +#define MG11_7_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_7PL) || (G11_6PL == 0) +#define MG11_7_16PL ~(1 << 5) +#else +#define MG11_7_16PL 0xFFFF +#endif + +#if (G11_8PL >= G11_7PL) || (G11_8PL == 0) +#define MG11_7_18PL ~(1 << 7) +#else +#define MG11_7_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_7PL) || (G11_9PL == 0) +#define MG11_7_19PL ~(1 << 8) +#else +#define MG11_7_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_7PL) || (G11_10PL == 0) +#define MG11_7_110PL ~(1 << 9) +#else +#define MG11_7_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_7PL) || (G11_11PL == 0) +#define MG11_7_111PL ~(1 << 10) +#else +#define MG11_7_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_7PL) || (G11_12PL == 0) +#define MG11_7_112PL ~(1 << 11) +#else +#define MG11_7_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_7PL) || (G11_13PL == 0) +#define MG11_7_113PL ~(1 << 12) +#else +#define MG11_7_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_7PL) || (G11_14PL == 0) +#define MG11_7_114PL ~(1 << 13) +#else +#define MG11_7_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_7PL) || (G11_15PL == 0) +#define MG11_7_115PL ~(1 << 14) +#else +#define MG11_7_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_7PL) || (G11_16PL == 0) +#define MG11_7_116PL ~(1 << 15) +#else +#define MG11_7_116PL 0xFFFF +#endif + +#define MG11_7_17PL 0xFFBF +#define MG11_7 (MG11_7_11PL & MG11_7_12PL & MG11_7_13PL & MG11_7_14PL & \ + MG11_7_15PL & MG11_7_16PL & MG11_7_17PL & MG11_7_18PL & \ + MG11_7_19PL & MG11_7_110PL & MG11_7_111PL & MG11_7_112PL & \ + MG11_7_113PL & MG11_7_114PL & MG11_7_115PL & MG11_7_116PL) +// End of MG11_7: +// Beginning of MG118: +#if (G11_1PL >= G11_8PL) || (G11_1PL == 0) +#define MG11_8_11PL ~(1 << 0) +#else +#define MG11_8_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_8PL) || (G11_2PL == 0) +#define MG11_8_12PL ~(1 << 1) +#else +#define MG11_8_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_8PL) || (G11_3PL == 0) +#define MG11_8_13PL ~(1 << 2) +#else +#define MG11_8_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_8PL) || (G11_4PL == 0) +#define MG11_8_14PL ~(1 << 3) +#else +#define MG11_8_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_8PL) || (G11_5PL == 0) +#define MG11_8_15PL ~(1 << 4) +#else +#define MG11_8_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_8PL) || (G11_6PL == 0) +#define MG11_8_16PL ~(1 << 5) +#else +#define MG11_8_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_8PL) || (G11_7PL == 0) +#define MG11_8_17PL ~(1 << 6) +#else +#define MG11_8_17PL 0xFFFF +#endif + +#if (G11_9PL >= G11_8PL) || (G11_9PL == 0) +#define MG11_8_19PL ~(1 << 8) +#else +#define MG11_8_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_8PL) || (G11_10PL == 0) +#define MG11_8_110PL ~(1 << 9) +#else +#define MG11_8_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_8PL) || (G11_11PL == 0) +#define MG11_8_111PL ~(1 << 10) +#else +#define MG11_8_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_8PL) || (G11_12PL == 0) +#define MG11_8_112PL ~(1 << 11) +#else +#define MG11_8_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_8PL) || (G11_13PL == 0) +#define MG11_8_113PL ~(1 << 12) +#else +#define MG11_8_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_8PL) || (G11_14PL == 0) +#define MG11_8_114PL ~(1 << 13) +#else +#define MG11_8_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_8PL) || (G11_15PL == 0) +#define MG11_8_115PL ~(1 << 14) +#else +#define MG11_8_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_8PL) || (G11_16PL == 0) +#define MG11_8_116PL ~(1 << 15) +#else +#define MG11_8_116PL 0xFFFF +#endif + +#define MG11_8_18PL 0xFF7F +#define MG11_8 (MG11_8_11PL & MG11_8_12PL & MG11_8_13PL & MG11_8_14PL & \ + MG11_8_15PL & MG11_8_16PL & MG11_8_17PL & MG11_8_18PL & \ + MG11_8_19PL & MG11_8_110PL & MG11_8_111PL & MG11_8_112PL & \ + MG11_8_113PL & MG11_8_114PL & MG11_8_115PL & MG11_8_116PL) +// End of MG11_8: +// Beginning of MG119: +#if (G11_1PL >= G11_9PL) || (G11_1PL == 0) +#define MG11_9_11PL ~(1 << 0) +#else +#define MG11_9_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_9PL) || (G11_2PL == 0) +#define MG11_9_12PL ~(1 << 1) +#else +#define MG11_9_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_9PL) || (G11_3PL == 0) +#define MG11_9_13PL ~(1 << 2) +#else +#define MG11_9_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_9PL) || (G11_4PL == 0) +#define MG11_9_14PL ~(1 << 3) +#else +#define MG11_9_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_9PL) || (G11_5PL == 0) +#define MG11_9_15PL ~(1 << 4) +#else +#define MG11_9_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_9PL) || (G11_6PL == 0) +#define MG11_9_16PL ~(1 << 5) +#else +#define MG11_9_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_9PL) || (G11_7PL == 0) +#define MG11_9_17PL ~(1 << 6) +#else +#define MG11_9_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_9PL) || (G11_8PL == 0) +#define MG11_9_18PL ~(1 << 7) +#else +#define MG11_9_18PL 0xFFFF +#endif + +#if (G11_10PL >= G11_9PL) || (G11_10PL == 0) +#define MG11_9_110PL ~(1 << 9) +#else +#define MG11_9_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_9PL) || (G11_11PL == 0) +#define MG11_9_111PL ~(1 << 10) +#else +#define MG11_9_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_9PL) || (G11_12PL == 0) +#define MG11_9_112PL ~(1 << 11) +#else +#define MG11_9_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_9PL) || (G11_13PL == 0) +#define MG11_9_113PL ~(1 << 12) +#else +#define MG11_9_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_9PL) || (G11_14PL == 0) +#define MG11_9_114PL ~(1 << 13) +#else +#define MG11_9_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_9PL) || (G11_15PL == 0) +#define MG11_9_115PL ~(1 << 14) +#else +#define MG11_9_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_9PL) || (G11_16PL == 0) +#define MG11_9_116PL ~(1 << 15) +#else +#define MG11_9_116PL 0xFFFF +#endif + +#define MG11_9_19PL 0xFEFF +#define MG11_9 (MG11_9_11PL & MG11_9_12PL & MG11_9_13PL & MG11_9_14PL & \ + MG11_9_15PL & MG11_9_16PL & MG11_9_17PL & MG11_9_18PL & \ + MG11_9_19PL & MG11_9_110PL & MG11_9_111PL & MG11_9_112PL & \ + MG11_9_113PL & MG11_9_114PL & MG11_9_115PL & MG11_9_116PL) +// End of MG11_9: +// Beginning of MG1110: +#if (G11_1PL >= G11_10PL) || (G11_1PL == 0) +#define MG11_10_11PL ~(1 << 0) +#else +#define MG11_10_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_10PL) || (G11_2PL == 0) +#define MG11_10_12PL ~(1 << 1) +#else +#define MG11_10_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_10PL) || (G11_3PL == 0) +#define MG11_10_13PL ~(1 << 2) +#else +#define MG11_10_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_10PL) || (G11_4PL == 0) +#define MG11_10_14PL ~(1 << 3) +#else +#define MG11_10_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_10PL) || (G11_5PL == 0) +#define MG11_10_15PL ~(1 << 4) +#else +#define MG11_10_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_10PL) || (G11_6PL == 0) +#define MG11_10_16PL ~(1 << 5) +#else +#define MG11_10_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_10PL) || (G11_7PL == 0) +#define MG11_10_17PL ~(1 << 6) +#else +#define MG11_10_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_10PL) || (G11_8PL == 0) +#define MG11_10_18PL ~(1 << 7) +#else +#define MG11_10_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_10PL) || (G11_9PL == 0) +#define MG11_10_19PL ~(1 << 8) +#else +#define MG11_10_19PL 0xFFFF +#endif + +#if (G11_11PL >= G11_10PL) || (G11_11PL == 0) +#define MG11_10_111PL ~(1 << 10) +#else +#define MG11_10_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_10PL) || (G11_12PL == 0) +#define MG11_10_112PL ~(1 << 11) +#else +#define MG11_10_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_10PL) || (G11_13PL == 0) +#define MG11_10_113PL ~(1 << 12) +#else +#define MG11_10_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_10PL) || (G11_14PL == 0) +#define MG11_10_114PL ~(1 << 13) +#else +#define MG11_10_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_10PL) || (G11_15PL == 0) +#define MG11_10_115PL ~(1 << 14) +#else +#define MG11_10_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_10PL) || (G11_16PL == 0) +#define MG11_10_116PL ~(1 << 15) +#else +#define MG11_10_116PL 0xFFFF +#endif + +#define MG11_10_110PL 0xFDFF +#define MG11_10 (MG11_10_11PL & MG11_10_12PL & MG11_10_13PL & MG11_10_14PL & \ + MG11_10_15PL & MG11_10_16PL & MG11_10_17PL & MG11_10_18PL & \ + MG11_10_19PL & MG11_10_110PL & MG11_10_111PL & MG11_10_112PL & \ + MG11_10_113PL & MG11_10_114PL & MG11_10_115PL & MG11_10_116PL) +// End of MG11_10: +// Beginning of MG1111: +#if (G11_1PL >= G11_11PL) || (G11_1PL == 0) +#define MG11_11_11PL ~(1 << 0) +#else +#define MG11_11_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_11PL) || (G11_2PL == 0) +#define MG11_11_12PL ~(1 << 1) +#else +#define MG11_11_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_11PL) || (G11_3PL == 0) +#define MG11_11_13PL ~(1 << 2) +#else +#define MG11_11_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_11PL) || (G11_4PL == 0) +#define MG11_11_14PL ~(1 << 3) +#else +#define MG11_11_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_11PL) || (G11_5PL == 0) +#define MG11_11_15PL ~(1 << 4) +#else +#define MG11_11_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_11PL) || (G11_6PL == 0) +#define MG11_11_16PL ~(1 << 5) +#else +#define MG11_11_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_11PL) || (G11_7PL == 0) +#define MG11_11_17PL ~(1 << 6) +#else +#define MG11_11_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_11PL) || (G11_8PL == 0) +#define MG11_11_18PL ~(1 << 7) +#else +#define MG11_11_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_11PL) || (G11_9PL == 0) +#define MG11_11_19PL ~(1 << 8) +#else +#define MG11_11_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_11PL) || (G11_10PL == 0) +#define MG11_11_110PL ~(1 << 9) +#else +#define MG11_11_110PL 0xFFFF +#endif + +#if (G11_12PL >= G11_11PL) || (G11_12PL == 0) +#define MG11_11_112PL ~(1 << 11) +#else +#define MG11_11_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_11PL) || (G11_13PL == 0) +#define MG11_11_113PL ~(1 << 12) +#else +#define MG11_11_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_11PL) || (G11_14PL == 0) +#define MG11_11_114PL ~(1 << 13) +#else +#define MG11_11_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_11PL) || (G11_15PL == 0) +#define MG11_11_115PL ~(1 << 14) +#else +#define MG11_11_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_11PL) || (G11_16PL == 0) +#define MG11_11_116PL ~(1 << 15) +#else +#define MG11_11_116PL 0xFFFF +#endif + +#define MG11_11_111PL 0xFBFF +#define MG11_11 (MG11_11_11PL & MG11_11_12PL & MG11_11_13PL & MG11_11_14PL & \ + MG11_11_15PL & MG11_11_16PL & MG11_11_17PL & MG11_11_18PL & \ + MG11_11_19PL & MG11_11_110PL & MG11_11_111PL & MG11_11_112PL & \ + MG11_11_113PL & MG11_11_114PL & MG11_11_115PL & MG11_11_116PL) +// End of MG11_11: +// Beginning of MG1112: +#if (G11_1PL >= G11_12PL) || (G11_1PL == 0) +#define MG11_12_11PL ~(1 << 0) +#else +#define MG11_12_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_12PL) || (G11_2PL == 0) +#define MG11_12_12PL ~(1 << 1) +#else +#define MG11_12_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_12PL) || (G11_3PL == 0) +#define MG11_12_13PL ~(1 << 2) +#else +#define MG11_12_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_12PL) || (G11_4PL == 0) +#define MG11_12_14PL ~(1 << 3) +#else +#define MG11_12_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_12PL) || (G11_5PL == 0) +#define MG11_12_15PL ~(1 << 4) +#else +#define MG11_12_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_12PL) || (G11_6PL == 0) +#define MG11_12_16PL ~(1 << 5) +#else +#define MG11_12_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_12PL) || (G11_7PL == 0) +#define MG11_12_17PL ~(1 << 6) +#else +#define MG11_12_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_12PL) || (G11_8PL == 0) +#define MG11_12_18PL ~(1 << 7) +#else +#define MG11_12_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_12PL) || (G11_9PL == 0) +#define MG11_12_19PL ~(1 << 8) +#else +#define MG11_12_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_12PL) || (G11_10PL == 0) +#define MG11_12_110PL ~(1 << 9) +#else +#define MG11_12_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_12PL) || (G11_11PL == 0) +#define MG11_12_111PL ~(1 << 10) +#else +#define MG11_12_111PL 0xFFFF +#endif + +#if (G11_13PL >= G11_12PL) || (G11_13PL == 0) +#define MG11_12_113PL ~(1 << 12) +#else +#define MG11_12_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_12PL) || (G11_14PL == 0) +#define MG11_12_114PL ~(1 << 13) +#else +#define MG11_12_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_12PL) || (G11_15PL == 0) +#define MG11_12_115PL ~(1 << 14) +#else +#define MG11_12_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_12PL) || (G11_16PL == 0) +#define MG11_12_116PL ~(1 << 15) +#else +#define MG11_12_116PL 0xFFFF +#endif + +#define MG11_12_112PL 0xF7FF +#define MG11_12 (MG11_12_11PL & MG11_12_12PL & MG11_12_13PL & MG11_12_14PL & \ + MG11_12_15PL & MG11_12_16PL & MG11_12_17PL & MG11_12_18PL & \ + MG11_12_19PL & MG11_12_110PL & MG11_12_111PL & MG11_12_112PL & \ + MG11_12_113PL & MG11_12_114PL & MG11_12_115PL & MG11_12_116PL) +// End of MG11_12: +// Beginning of MG1113: +#if (G11_1PL >= G11_13PL) || (G11_1PL == 0) +#define MG11_13_11PL ~(1 << 0) +#else +#define MG11_13_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_13PL) || (G11_2PL == 0) +#define MG11_13_12PL ~(1 << 1) +#else +#define MG11_13_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_13PL) || (G11_3PL == 0) +#define MG11_13_13PL ~(1 << 2) +#else +#define MG11_13_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_13PL) || (G11_4PL == 0) +#define MG11_13_14PL ~(1 << 3) +#else +#define MG11_13_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_13PL) || (G11_5PL == 0) +#define MG11_13_15PL ~(1 << 4) +#else +#define MG11_13_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_13PL) || (G11_6PL == 0) +#define MG11_13_16PL ~(1 << 5) +#else +#define MG11_13_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_13PL) || (G11_7PL == 0) +#define MG11_13_17PL ~(1 << 6) +#else +#define MG11_13_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_13PL) || (G11_8PL == 0) +#define MG11_13_18PL ~(1 << 7) +#else +#define MG11_13_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_13PL) || (G11_9PL == 0) +#define MG11_13_19PL ~(1 << 8) +#else +#define MG11_13_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_13PL) || (G11_10PL == 0) +#define MG11_13_110PL ~(1 << 9) +#else +#define MG11_13_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_13PL) || (G11_11PL == 0) +#define MG11_13_111PL ~(1 << 10) +#else +#define MG11_13_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_13PL) || (G11_12PL == 0) +#define MG11_13_112PL ~(1 << 11) +#else +#define MG11_13_112PL 0xFFFF +#endif + +#if (G11_14PL >= G11_13PL) || (G11_14PL == 0) +#define MG11_13_114PL ~(1 << 13) +#else +#define MG11_13_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_13PL) || (G11_15PL == 0) +#define MG11_13_115PL ~(1 << 14) +#else +#define MG11_13_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_13PL) || (G11_16PL == 0) +#define MG11_13_116PL ~(1 << 15) +#else +#define MG11_13_116PL 0xFFFF +#endif + +#define MG11_13_113PL 0xEFFF +#define MG11_13 (MG11_13_11PL & MG11_13_12PL & MG11_13_13PL & MG11_13_14PL & \ + MG11_13_15PL & MG11_13_16PL & MG11_13_17PL & MG11_13_18PL & \ + MG11_13_19PL & MG11_13_110PL & MG11_13_111PL & MG11_13_112PL & \ + MG11_13_113PL & MG11_13_114PL & MG11_13_115PL & MG11_13_116PL) +// End of MG11_13: +// Beginning of MG1114: +#if (G11_1PL >= G11_14PL) || (G11_1PL == 0) +#define MG11_14_11PL ~(1 << 0) +#else +#define MG11_14_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_14PL) || (G11_2PL == 0) +#define MG11_14_12PL ~(1 << 1) +#else +#define MG11_14_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_14PL) || (G11_3PL == 0) +#define MG11_14_13PL ~(1 << 2) +#else +#define MG11_14_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_14PL) || (G11_4PL == 0) +#define MG11_14_14PL ~(1 << 3) +#else +#define MG11_14_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_14PL) || (G11_5PL == 0) +#define MG11_14_15PL ~(1 << 4) +#else +#define MG11_14_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_14PL) || (G11_6PL == 0) +#define MG11_14_16PL ~(1 << 5) +#else +#define MG11_14_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_14PL) || (G11_7PL == 0) +#define MG11_14_17PL ~(1 << 6) +#else +#define MG11_14_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_14PL) || (G11_8PL == 0) +#define MG11_14_18PL ~(1 << 7) +#else +#define MG11_14_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_14PL) || (G11_9PL == 0) +#define MG11_14_19PL ~(1 << 8) +#else +#define MG11_14_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_14PL) || (G11_10PL == 0) +#define MG11_14_110PL ~(1 << 9) +#else +#define MG11_14_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_14PL) || (G11_11PL == 0) +#define MG11_14_111PL ~(1 << 10) +#else +#define MG11_14_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_14PL) || (G11_12PL == 0) +#define MG11_14_112PL ~(1 << 11) +#else +#define MG11_14_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_14PL) || (G11_13PL == 0) +#define MG11_14_113PL ~(1 << 12) +#else +#define MG11_14_113PL 0xFFFF +#endif + +#if (G11_15PL >= G11_14PL) || (G11_15PL == 0) +#define MG11_14_115PL ~(1 << 14) +#else +#define MG11_14_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_14PL) || (G11_16PL == 0) +#define MG11_14_116PL ~(1 << 15) +#else +#define MG11_14_116PL 0xFFFF +#endif + +#define MG11_14_114PL 0xDFFF +#define MG11_14 (MG11_14_11PL & MG11_14_12PL & MG11_14_13PL & MG11_14_14PL & \ + MG11_14_15PL & MG11_14_16PL & MG11_14_17PL & MG11_14_18PL & \ + MG11_14_19PL & MG11_14_110PL & MG11_14_111PL & MG11_14_112PL & \ + MG11_14_113PL & MG11_14_114PL & MG11_14_115PL & MG11_14_116PL) +// End of MG11_14: +// Beginning of MG1115: +#if (G11_1PL >= G11_15PL) || (G11_1PL == 0) +#define MG11_15_11PL ~(1 << 0) +#else +#define MG11_15_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_15PL) || (G11_2PL == 0) +#define MG11_15_12PL ~(1 << 1) +#else +#define MG11_15_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_15PL) || (G11_3PL == 0) +#define MG11_15_13PL ~(1 << 2) +#else +#define MG11_15_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_15PL) || (G11_4PL == 0) +#define MG11_15_14PL ~(1 << 3) +#else +#define MG11_15_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_15PL) || (G11_5PL == 0) +#define MG11_15_15PL ~(1 << 4) +#else +#define MG11_15_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_15PL) || (G11_6PL == 0) +#define MG11_15_16PL ~(1 << 5) +#else +#define MG11_15_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_15PL) || (G11_7PL == 0) +#define MG11_15_17PL ~(1 << 6) +#else +#define MG11_15_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_15PL) || (G11_8PL == 0) +#define MG11_15_18PL ~(1 << 7) +#else +#define MG11_15_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_15PL) || (G11_9PL == 0) +#define MG11_15_19PL ~(1 << 8) +#else +#define MG11_15_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_15PL) || (G11_10PL == 0) +#define MG11_15_110PL ~(1 << 9) +#else +#define MG11_15_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_15PL) || (G11_11PL == 0) +#define MG11_15_111PL ~(1 << 10) +#else +#define MG11_15_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_15PL) || (G11_12PL == 0) +#define MG11_15_112PL ~(1 << 11) +#else +#define MG11_15_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_15PL) || (G11_13PL == 0) +#define MG11_15_113PL ~(1 << 12) +#else +#define MG11_15_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_15PL) || (G11_14PL == 0) +#define MG11_15_114PL ~(1 << 13) +#else +#define MG11_15_114PL 0xFFFF +#endif + +#if (G11_16PL >= G11_15PL) || (G11_16PL == 0) +#define MG11_15_116PL ~(1 << 15) +#else +#define MG11_15_116PL 0xFFFF +#endif + +#define MG11_15_115PL 0xBFFF +#define MG11_15 (MG11_15_11PL & MG11_15_12PL & MG11_15_13PL & MG11_15_14PL & \ + MG11_15_15PL & MG11_15_16PL & MG11_15_17PL & MG11_15_18PL & \ + MG11_15_19PL & MG11_15_110PL & MG11_15_111PL & MG11_15_112PL & \ + MG11_15_113PL & MG11_15_114PL & MG11_15_115PL & MG11_15_116PL) +// End of MG11_15: +// Beginning of MG1116: +#if (G11_1PL >= G11_16PL) || (G11_1PL == 0) +#define MG11_16_11PL ~(1 << 0) +#else +#define MG11_16_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_16PL) || (G11_2PL == 0) +#define MG11_16_12PL ~(1 << 1) +#else +#define MG11_16_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_16PL) || (G11_3PL == 0) +#define MG11_16_13PL ~(1 << 2) +#else +#define MG11_16_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_16PL) || (G11_4PL == 0) +#define MG11_16_14PL ~(1 << 3) +#else +#define MG11_16_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_16PL) || (G11_5PL == 0) +#define MG11_16_15PL ~(1 << 4) +#else +#define MG11_16_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_16PL) || (G11_6PL == 0) +#define MG11_16_16PL ~(1 << 5) +#else +#define MG11_16_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_16PL) || (G11_7PL == 0) +#define MG11_16_17PL ~(1 << 6) +#else +#define MG11_16_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_16PL) || (G11_8PL == 0) +#define MG11_16_18PL ~(1 << 7) +#else +#define MG11_16_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_16PL) || (G11_9PL == 0) +#define MG11_16_19PL ~(1 << 8) +#else +#define MG11_16_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_16PL) || (G11_10PL == 0) +#define MG11_16_110PL ~(1 << 9) +#else +#define MG11_16_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_16PL) || (G11_11PL == 0) +#define MG11_16_111PL ~(1 << 10) +#else +#define MG11_16_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_16PL) || (G11_12PL == 0) +#define MG11_16_112PL ~(1 << 11) +#else +#define MG11_16_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_16PL) || (G11_13PL == 0) +#define MG11_16_113PL ~(1 << 12) +#else +#define MG11_16_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_16PL) || (G11_14PL == 0) +#define MG11_16_114PL ~(1 << 13) +#else +#define MG11_16_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_16PL) || (G11_15PL == 0) +#define MG11_16_115PL ~(1 << 14) +#else +#define MG11_16_115PL 0xFFFF +#endif + +#define MG11_16_116PL 0x7FFF +#define MG11_16 (MG11_16_11PL & MG11_16_12PL & MG11_16_13PL & MG11_16_14PL & \ + MG11_16_15PL & MG11_16_16PL & MG11_16_17PL & MG11_16_18PL & \ + MG11_16_19PL & MG11_16_110PL & MG11_16_111PL & MG11_16_112PL & \ + MG11_16_113PL & MG11_16_114PL & MG11_16_115PL & MG11_16_116PL) +// End of MG11_16: + + +// +// Automatically generate PIEIER12 interrupt masks MG121 to MG1216: +// + +// Beginning of MG121: +#if (G12_2PL >= G12_1PL) || (G12_2PL == 0) +#define MG12_1_12PL ~(1 << 1) +#else +#define MG12_1_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_1PL) || (G12_3PL == 0) +#define MG12_1_13PL ~(1 << 2) +#else +#define MG12_1_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_1PL) || (G12_4PL == 0) +#define MG12_1_14PL ~(1 << 3) +#else +#define MG12_1_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_1PL) || (G12_5PL == 0) +#define MG12_1_15PL ~(1 << 4) +#else +#define MG12_1_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_1PL) || (G12_6PL == 0) +#define MG12_1_16PL ~(1 << 5) +#else +#define MG12_1_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_1PL) || (G12_7PL == 0) +#define MG12_1_17PL ~(1 << 6) +#else +#define MG12_1_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_1PL) || (G12_8PL == 0) +#define MG12_1_18PL ~(1 << 7) +#else +#define MG12_1_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_1PL) || (G12_9PL == 0) +#define MG12_1_19PL ~(1 << 8) +#else +#define MG12_1_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_1PL) || (G12_10PL == 0) +#define MG12_1_110PL ~(1 << 9) +#else +#define MG12_1_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_1PL) || (G12_11PL == 0) +#define MG12_1_111PL ~(1 << 10) +#else +#define MG12_1_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_1PL) || (G12_12PL == 0) +#define MG12_1_112PL ~(1 << 11) +#else +#define MG12_1_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_1PL) || (G12_13PL == 0) +#define MG12_1_113PL ~(1 << 12) +#else +#define MG12_1_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_1PL) || (G12_14PL == 0) +#define MG12_1_114PL ~(1 << 13) +#else +#define MG12_1_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_1PL) || (G12_15PL == 0) +#define MG12_1_115PL ~(1 << 14) +#else +#define MG12_1_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_1PL) || (G12_16PL == 0) +#define MG12_1_116PL ~(1 << 15) +#else +#define MG12_1_116PL 0xFFFF +#endif + +#define MG12_1_11PL 0xFFFE +#define MG12_1 (MG12_1_11PL & MG12_1_12PL & MG12_1_13PL & MG12_1_14PL & \ + MG12_1_15PL & MG12_1_16PL & MG12_1_17PL & MG12_1_18PL & \ + MG12_1_19PL & MG12_1_110PL & MG12_1_111PL & MG12_1_112PL & \ + MG12_1_113PL & MG12_1_114PL & MG12_1_115PL & MG12_1_116PL) +// End of MG12_1: +// Beginning of MG122: +#if (G12_1PL >= G12_2PL) || (G12_1PL == 0) +#define MG12_2_11PL ~(1 << 0) +#else +#define MG12_2_11PL 0xFFFF +#endif + +#if (G12_3PL >= G12_2PL) || (G12_3PL == 0) +#define MG12_2_13PL ~(1 << 2) +#else +#define MG12_2_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_2PL) || (G12_4PL == 0) +#define MG12_2_14PL ~(1 << 3) +#else +#define MG12_2_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_2PL) || (G12_5PL == 0) +#define MG12_2_15PL ~(1 << 4) +#else +#define MG12_2_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_2PL) || (G12_6PL == 0) +#define MG12_2_16PL ~(1 << 5) +#else +#define MG12_2_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_2PL) || (G12_7PL == 0) +#define MG12_2_17PL ~(1 << 6) +#else +#define MG12_2_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_2PL) || (G12_8PL == 0) +#define MG12_2_18PL ~(1 << 7) +#else +#define MG12_2_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_2PL) || (G12_9PL == 0) +#define MG12_2_19PL ~(1 << 8) +#else +#define MG12_2_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_2PL) || (G12_10PL == 0) +#define MG12_2_110PL ~(1 << 9) +#else +#define MG12_2_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_2PL) || (G12_11PL == 0) +#define MG12_2_111PL ~(1 << 10) +#else +#define MG12_2_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_2PL) || (G12_12PL == 0) +#define MG12_2_112PL ~(1 << 11) +#else +#define MG12_2_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_2PL) || (G12_13PL == 0) +#define MG12_2_113PL ~(1 << 12) +#else +#define MG12_2_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_2PL) || (G12_14PL == 0) +#define MG12_2_114PL ~(1 << 13) +#else +#define MG12_2_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_2PL) || (G12_15PL == 0) +#define MG12_2_115PL ~(1 << 14) +#else +#define MG12_2_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_2PL) || (G12_16PL == 0) +#define MG12_2_116PL ~(1 << 15) +#else +#define MG12_2_116PL 0xFFFF +#endif + +#define MG12_2_12PL 0xFFFD +#define MG12_2 (MG12_2_11PL & MG12_2_12PL & MG12_2_13PL & MG12_2_14PL & \ + MG12_2_15PL & MG12_2_16PL & MG12_2_17PL & MG12_2_18PL & \ + MG12_2_19PL & MG12_2_110PL & MG12_2_111PL & MG12_2_112PL & \ + MG12_2_113PL & MG12_2_114PL & MG12_2_115PL & MG12_2_116PL) +// End of MG12_2: +// Beginning of MG123: +#if (G12_1PL >= G12_3PL) || (G12_1PL == 0) +#define MG12_3_11PL ~(1 << 0) +#else +#define MG12_3_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_3PL) || (G12_2PL == 0) +#define MG12_3_12PL ~(1 << 1) +#else +#define MG12_3_12PL 0xFFFF +#endif + +#if (G12_4PL >= G12_3PL) || (G12_4PL == 0) +#define MG12_3_14PL ~(1 << 3) +#else +#define MG12_3_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_3PL) || (G12_5PL == 0) +#define MG12_3_15PL ~(1 << 4) +#else +#define MG12_3_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_3PL) || (G12_6PL == 0) +#define MG12_3_16PL ~(1 << 5) +#else +#define MG12_3_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_3PL) || (G12_7PL == 0) +#define MG12_3_17PL ~(1 << 6) +#else +#define MG12_3_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_3PL) || (G12_8PL == 0) +#define MG12_3_18PL ~(1 << 7) +#else +#define MG12_3_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_3PL) || (G12_9PL == 0) +#define MG12_3_19PL ~(1 << 8) +#else +#define MG12_3_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_3PL) || (G12_10PL == 0) +#define MG12_3_110PL ~(1 << 9) +#else +#define MG12_3_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_3PL) || (G12_11PL == 0) +#define MG12_3_111PL ~(1 << 10) +#else +#define MG12_3_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_3PL) || (G12_12PL == 0) +#define MG12_3_112PL ~(1 << 11) +#else +#define MG12_3_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_3PL) || (G12_13PL == 0) +#define MG12_3_113PL ~(1 << 12) +#else +#define MG12_3_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_3PL) || (G12_14PL == 0) +#define MG12_3_114PL ~(1 << 13) +#else +#define MG12_3_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_3PL) || (G12_15PL == 0) +#define MG12_3_115PL ~(1 << 14) +#else +#define MG12_3_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_3PL) || (G12_16PL == 0) +#define MG12_3_116PL ~(1 << 15) +#else +#define MG12_3_116PL 0xFFFF +#endif + +#define MG12_3_13PL 0xFFFB +#define MG12_3 (MG12_3_11PL & MG12_3_12PL & MG12_3_13PL & MG12_3_14PL & \ + MG12_3_15PL & MG12_3_16PL & MG12_3_17PL & MG12_3_18PL & \ + MG12_3_19PL & MG12_3_110PL & MG12_3_111PL & MG12_3_112PL & \ + MG12_3_113PL & MG12_3_114PL & MG12_3_115PL & MG12_3_116PL) +// End of MG12_3: +// Beginning of MG124: +#if (G12_1PL >= G12_4PL) || (G12_1PL == 0) +#define MG12_4_11PL ~(1 << 0) +#else +#define MG12_4_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_4PL) || (G12_2PL == 0) +#define MG12_4_12PL ~(1 << 1) +#else +#define MG12_4_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_4PL) || (G12_3PL == 0) +#define MG12_4_13PL ~(1 << 2) +#else +#define MG12_4_13PL 0xFFFF +#endif + +#if (G12_5PL >= G12_4PL) || (G12_5PL == 0) +#define MG12_4_15PL ~(1 << 4) +#else +#define MG12_4_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_4PL) || (G12_6PL == 0) +#define MG12_4_16PL ~(1 << 5) +#else +#define MG12_4_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_4PL) || (G12_7PL == 0) +#define MG12_4_17PL ~(1 << 6) +#else +#define MG12_4_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_4PL) || (G12_8PL == 0) +#define MG12_4_18PL ~(1 << 7) +#else +#define MG12_4_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_4PL) || (G12_9PL == 0) +#define MG12_4_19PL ~(1 << 8) +#else +#define MG12_4_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_4PL) || (G12_10PL == 0) +#define MG12_4_110PL ~(1 << 9) +#else +#define MG12_4_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_4PL) || (G12_11PL == 0) +#define MG12_4_111PL ~(1 << 10) +#else +#define MG12_4_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_4PL) || (G12_12PL == 0) +#define MG12_4_112PL ~(1 << 11) +#else +#define MG12_4_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_4PL) || (G12_13PL == 0) +#define MG12_4_113PL ~(1 << 12) +#else +#define MG12_4_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_4PL) || (G12_14PL == 0) +#define MG12_4_114PL ~(1 << 13) +#else +#define MG12_4_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_4PL) || (G12_15PL == 0) +#define MG12_4_115PL ~(1 << 14) +#else +#define MG12_4_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_4PL) || (G12_16PL == 0) +#define MG12_4_116PL ~(1 << 15) +#else +#define MG12_4_116PL 0xFFFF +#endif + +#define MG12_4_14PL 0xFFF7 +#define MG12_4 (MG12_4_11PL & MG12_4_12PL & MG12_4_13PL & MG12_4_14PL & \ + MG12_4_15PL & MG12_4_16PL & MG12_4_17PL & MG12_4_18PL & \ + MG12_4_19PL & MG12_4_110PL & MG12_4_111PL & MG12_4_112PL & \ + MG12_4_113PL & MG12_4_114PL & MG12_4_115PL & MG12_4_116PL) +// End of MG12_4: +// Beginning of MG125: +#if (G12_1PL >= G12_5PL) || (G12_1PL == 0) +#define MG12_5_11PL ~(1 << 0) +#else +#define MG12_5_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_5PL) || (G12_2PL == 0) +#define MG12_5_12PL ~(1 << 1) +#else +#define MG12_5_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_5PL) || (G12_3PL == 0) +#define MG12_5_13PL ~(1 << 2) +#else +#define MG12_5_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_5PL) || (G12_4PL == 0) +#define MG12_5_14PL ~(1 << 3) +#else +#define MG12_5_14PL 0xFFFF +#endif + +#if (G12_6PL >= G12_5PL) || (G12_6PL == 0) +#define MG12_5_16PL ~(1 << 5) +#else +#define MG12_5_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_5PL) || (G12_7PL == 0) +#define MG12_5_17PL ~(1 << 6) +#else +#define MG12_5_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_5PL) || (G12_8PL == 0) +#define MG12_5_18PL ~(1 << 7) +#else +#define MG12_5_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_5PL) || (G12_9PL == 0) +#define MG12_5_19PL ~(1 << 8) +#else +#define MG12_5_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_5PL) || (G12_10PL == 0) +#define MG12_5_110PL ~(1 << 9) +#else +#define MG12_5_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_5PL) || (G12_11PL == 0) +#define MG12_5_111PL ~(1 << 10) +#else +#define MG12_5_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_5PL) || (G12_12PL == 0) +#define MG12_5_112PL ~(1 << 11) +#else +#define MG12_5_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_5PL) || (G12_13PL == 0) +#define MG12_5_113PL ~(1 << 12) +#else +#define MG12_5_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_5PL) || (G12_14PL == 0) +#define MG12_5_114PL ~(1 << 13) +#else +#define MG12_5_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_5PL) || (G12_15PL == 0) +#define MG12_5_115PL ~(1 << 14) +#else +#define MG12_5_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_5PL) || (G12_16PL == 0) +#define MG12_5_116PL ~(1 << 15) +#else +#define MG12_5_116PL 0xFFFF +#endif + +#define MG12_5_15PL 0xFFEF +#define MG12_5 (MG12_5_11PL & MG12_5_12PL & MG12_5_13PL & MG12_5_14PL & \ + MG12_5_15PL & MG12_5_16PL & MG12_5_17PL & MG12_5_18PL & \ + MG12_5_19PL & MG12_5_110PL & MG12_5_111PL & MG12_5_112PL & \ + MG12_5_113PL & MG12_5_114PL & MG12_5_115PL & MG12_5_116PL) +// End of MG12_5: +// Beginning of MG126: +#if (G12_1PL >= G12_6PL) || (G12_1PL == 0) +#define MG12_6_11PL ~(1 << 0) +#else +#define MG12_6_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_6PL) || (G12_2PL == 0) +#define MG12_6_12PL ~(1 << 1) +#else +#define MG12_6_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_6PL) || (G12_3PL == 0) +#define MG12_6_13PL ~(1 << 2) +#else +#define MG12_6_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_6PL) || (G12_4PL == 0) +#define MG12_6_14PL ~(1 << 3) +#else +#define MG12_6_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_6PL) || (G12_5PL == 0) +#define MG12_6_15PL ~(1 << 4) +#else +#define MG12_6_15PL 0xFFFF +#endif + +#if (G12_7PL >= G12_6PL) || (G12_7PL == 0) +#define MG12_6_17PL ~(1 << 6) +#else +#define MG12_6_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_6PL) || (G12_8PL == 0) +#define MG12_6_18PL ~(1 << 7) +#else +#define MG12_6_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_6PL) || (G12_9PL == 0) +#define MG12_6_19PL ~(1 << 8) +#else +#define MG12_6_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_6PL) || (G12_10PL == 0) +#define MG12_6_110PL ~(1 << 9) +#else +#define MG12_6_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_6PL) || (G12_11PL == 0) +#define MG12_6_111PL ~(1 << 10) +#else +#define MG12_6_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_6PL) || (G12_12PL == 0) +#define MG12_6_112PL ~(1 << 11) +#else +#define MG12_6_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_6PL) || (G12_13PL == 0) +#define MG12_6_113PL ~(1 << 12) +#else +#define MG12_6_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_6PL) || (G12_14PL == 0) +#define MG12_6_114PL ~(1 << 13) +#else +#define MG12_6_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_6PL) || (G12_15PL == 0) +#define MG12_6_115PL ~(1 << 14) +#else +#define MG12_6_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_6PL) || (G12_16PL == 0) +#define MG12_6_116PL ~(1 << 15) +#else +#define MG12_6_116PL 0xFFFF +#endif + +#define MG12_6_16PL 0xFFDF +#define MG12_6 (MG12_6_11PL & MG12_6_12PL & MG12_6_13PL & MG12_6_14PL & \ + MG12_6_15PL & MG12_6_16PL & MG12_6_17PL & MG12_6_18PL & \ + MG12_6_19PL & MG12_6_110PL & MG12_6_111PL & MG12_6_112PL & \ + MG12_6_113PL & MG12_6_114PL & MG12_6_115PL & MG12_6_116PL) +// End of MG12_6: +// Beginning of MG127: +#if (G12_1PL >= G12_7PL) || (G12_1PL == 0) +#define MG12_7_11PL ~(1 << 0) +#else +#define MG12_7_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_7PL) || (G12_2PL == 0) +#define MG12_7_12PL ~(1 << 1) +#else +#define MG12_7_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_7PL) || (G12_3PL == 0) +#define MG12_7_13PL ~(1 << 2) +#else +#define MG12_7_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_7PL) || (G12_4PL == 0) +#define MG12_7_14PL ~(1 << 3) +#else +#define MG12_7_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_7PL) || (G12_5PL == 0) +#define MG12_7_15PL ~(1 << 4) +#else +#define MG12_7_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_7PL) || (G12_6PL == 0) +#define MG12_7_16PL ~(1 << 5) +#else +#define MG12_7_16PL 0xFFFF +#endif + +#if (G12_8PL >= G12_7PL) || (G12_8PL == 0) +#define MG12_7_18PL ~(1 << 7) +#else +#define MG12_7_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_7PL) || (G12_9PL == 0) +#define MG12_7_19PL ~(1 << 8) +#else +#define MG12_7_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_7PL) || (G12_10PL == 0) +#define MG12_7_110PL ~(1 << 9) +#else +#define MG12_7_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_7PL) || (G12_11PL == 0) +#define MG12_7_111PL ~(1 << 10) +#else +#define MG12_7_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_7PL) || (G12_12PL == 0) +#define MG12_7_112PL ~(1 << 11) +#else +#define MG12_7_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_7PL) || (G12_13PL == 0) +#define MG12_7_113PL ~(1 << 12) +#else +#define MG12_7_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_7PL) || (G12_14PL == 0) +#define MG12_7_114PL ~(1 << 13) +#else +#define MG12_7_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_7PL) || (G12_15PL == 0) +#define MG12_7_115PL ~(1 << 14) +#else +#define MG12_7_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_7PL) || (G12_16PL == 0) +#define MG12_7_116PL ~(1 << 15) +#else +#define MG12_7_116PL 0xFFFF +#endif + +#define MG12_7_17PL 0xFFBF +#define MG12_7 (MG12_7_11PL & MG12_7_12PL & MG12_7_13PL & MG12_7_14PL & \ + MG12_7_15PL & MG12_7_16PL & MG12_7_17PL & MG12_7_18PL & \ + MG12_7_19PL & MG12_7_110PL & MG12_7_111PL & MG12_7_112PL & \ + MG12_7_113PL & MG12_7_114PL & MG12_7_115PL & MG12_7_116PL) +// End of MG12_7: +// Beginning of MG128: +#if (G12_1PL >= G12_8PL) || (G12_1PL == 0) +#define MG12_8_11PL ~(1 << 0) +#else +#define MG12_8_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_8PL) || (G12_2PL == 0) +#define MG12_8_12PL ~(1 << 1) +#else +#define MG12_8_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_8PL) || (G12_3PL == 0) +#define MG12_8_13PL ~(1 << 2) +#else +#define MG12_8_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_8PL) || (G12_4PL == 0) +#define MG12_8_14PL ~(1 << 3) +#else +#define MG12_8_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_8PL) || (G12_5PL == 0) +#define MG12_8_15PL ~(1 << 4) +#else +#define MG12_8_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_8PL) || (G12_6PL == 0) +#define MG12_8_16PL ~(1 << 5) +#else +#define MG12_8_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_8PL) || (G12_7PL == 0) +#define MG12_8_17PL ~(1 << 6) +#else +#define MG12_8_17PL 0xFFFF +#endif + +#if (G12_9PL >= G12_8PL) || (G12_9PL == 0) +#define MG12_8_19PL ~(1 << 8) +#else +#define MG12_8_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_8PL) || (G12_10PL == 0) +#define MG12_8_110PL ~(1 << 9) +#else +#define MG12_8_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_8PL) || (G12_11PL == 0) +#define MG12_8_111PL ~(1 << 10) +#else +#define MG12_8_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_8PL) || (G12_12PL == 0) +#define MG12_8_112PL ~(1 << 11) +#else +#define MG12_8_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_8PL) || (G12_13PL == 0) +#define MG12_8_113PL ~(1 << 12) +#else +#define MG12_8_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_8PL) || (G12_14PL == 0) +#define MG12_8_114PL ~(1 << 13) +#else +#define MG12_8_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_8PL) || (G12_15PL == 0) +#define MG12_8_115PL ~(1 << 14) +#else +#define MG12_8_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_8PL) || (G12_16PL == 0) +#define MG12_8_116PL ~(1 << 15) +#else +#define MG12_8_116PL 0xFFFF +#endif + +#define MG12_8_18PL 0xFF7F +#define MG12_8 (MG12_8_11PL & MG12_8_12PL & MG12_8_13PL & MG12_8_14PL & \ + MG12_8_15PL & MG12_8_16PL & MG12_8_17PL & MG12_8_18PL & \ + MG12_8_19PL & MG12_8_110PL & MG12_8_111PL & MG12_8_112PL & \ + MG12_8_113PL & MG12_8_114PL & MG12_8_115PL & MG12_8_116PL) +// End of MG12_8: +// Beginning of MG129: +#if (G12_1PL >= G12_9PL) || (G12_1PL == 0) +#define MG12_9_11PL ~(1 << 0) +#else +#define MG12_9_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_9PL) || (G12_2PL == 0) +#define MG12_9_12PL ~(1 << 1) +#else +#define MG12_9_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_9PL) || (G12_3PL == 0) +#define MG12_9_13PL ~(1 << 2) +#else +#define MG12_9_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_9PL) || (G12_4PL == 0) +#define MG12_9_14PL ~(1 << 3) +#else +#define MG12_9_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_9PL) || (G12_5PL == 0) +#define MG12_9_15PL ~(1 << 4) +#else +#define MG12_9_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_9PL) || (G12_6PL == 0) +#define MG12_9_16PL ~(1 << 5) +#else +#define MG12_9_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_9PL) || (G12_7PL == 0) +#define MG12_9_17PL ~(1 << 6) +#else +#define MG12_9_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_9PL) || (G12_8PL == 0) +#define MG12_9_18PL ~(1 << 7) +#else +#define MG12_9_18PL 0xFFFF +#endif + +#if (G12_10PL >= G12_9PL) || (G12_10PL == 0) +#define MG12_9_110PL ~(1 << 9) +#else +#define MG12_9_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_9PL) || (G12_11PL == 0) +#define MG12_9_111PL ~(1 << 10) +#else +#define MG12_9_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_9PL) || (G12_12PL == 0) +#define MG12_9_112PL ~(1 << 11) +#else +#define MG12_9_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_9PL) || (G12_13PL == 0) +#define MG12_9_113PL ~(1 << 12) +#else +#define MG12_9_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_9PL) || (G12_14PL == 0) +#define MG12_9_114PL ~(1 << 13) +#else +#define MG12_9_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_9PL) || (G12_15PL == 0) +#define MG12_9_115PL ~(1 << 14) +#else +#define MG12_9_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_9PL) || (G12_16PL == 0) +#define MG12_9_116PL ~(1 << 15) +#else +#define MG12_9_116PL 0xFFFF +#endif + +#define MG12_9_19PL 0xFEFF +#define MG12_9 (MG12_9_11PL & MG12_9_12PL & MG12_9_13PL & MG12_9_14PL & \ + MG12_9_15PL & MG12_9_16PL & MG12_9_17PL & MG12_9_18PL & \ + MG12_9_19PL & MG12_9_110PL & MG12_9_111PL & MG12_9_112PL & \ + MG12_9_113PL & MG12_9_114PL & MG12_9_115PL & MG12_9_116PL) +// End of MG12_9: +// Beginning of MG1210: +#if (G12_1PL >= G12_10PL) || (G12_1PL == 0) +#define MG12_10_11PL ~(1 << 0) +#else +#define MG12_10_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_10PL) || (G12_2PL == 0) +#define MG12_10_12PL ~(1 << 1) +#else +#define MG12_10_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_10PL) || (G12_3PL == 0) +#define MG12_10_13PL ~(1 << 2) +#else +#define MG12_10_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_10PL) || (G12_4PL == 0) +#define MG12_10_14PL ~(1 << 3) +#else +#define MG12_10_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_10PL) || (G12_5PL == 0) +#define MG12_10_15PL ~(1 << 4) +#else +#define MG12_10_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_10PL) || (G12_6PL == 0) +#define MG12_10_16PL ~(1 << 5) +#else +#define MG12_10_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_10PL) || (G12_7PL == 0) +#define MG12_10_17PL ~(1 << 6) +#else +#define MG12_10_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_10PL) || (G12_8PL == 0) +#define MG12_10_18PL ~(1 << 7) +#else +#define MG12_10_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_10PL) || (G12_9PL == 0) +#define MG12_10_19PL ~(1 << 8) +#else +#define MG12_10_19PL 0xFFFF +#endif + +#if (G12_11PL >= G12_10PL) || (G12_11PL == 0) +#define MG12_10_111PL ~(1 << 10) +#else +#define MG12_10_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_10PL) || (G12_12PL == 0) +#define MG12_10_112PL ~(1 << 11) +#else +#define MG12_10_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_10PL) || (G12_13PL == 0) +#define MG12_10_113PL ~(1 << 12) +#else +#define MG12_10_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_10PL) || (G12_14PL == 0) +#define MG12_10_114PL ~(1 << 13) +#else +#define MG12_10_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_10PL) || (G12_15PL == 0) +#define MG12_10_115PL ~(1 << 14) +#else +#define MG12_10_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_10PL) || (G12_16PL == 0) +#define MG12_10_116PL ~(1 << 15) +#else +#define MG12_10_116PL 0xFFFF +#endif + +#define MG12_10_110PL 0xFDFF +#define MG12_10 (MG12_10_11PL & MG12_10_12PL & MG12_10_13PL & MG12_10_14PL & \ + MG12_10_15PL & MG12_10_16PL & MG12_10_17PL & MG12_10_18PL & \ + MG12_10_19PL & MG12_10_110PL & MG12_10_111PL & MG12_10_112PL & \ + MG12_10_113PL & MG12_10_114PL & MG12_10_115PL & MG12_10_116PL) +// End of MG12_10: +// Beginning of MG1211: +#if (G12_1PL >= G12_11PL) || (G12_1PL == 0) +#define MG12_11_11PL ~(1 << 0) +#else +#define MG12_11_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_11PL) || (G12_2PL == 0) +#define MG12_11_12PL ~(1 << 1) +#else +#define MG12_11_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_11PL) || (G12_3PL == 0) +#define MG12_11_13PL ~(1 << 2) +#else +#define MG12_11_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_11PL) || (G12_4PL == 0) +#define MG12_11_14PL ~(1 << 3) +#else +#define MG12_11_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_11PL) || (G12_5PL == 0) +#define MG12_11_15PL ~(1 << 4) +#else +#define MG12_11_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_11PL) || (G12_6PL == 0) +#define MG12_11_16PL ~(1 << 5) +#else +#define MG12_11_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_11PL) || (G12_7PL == 0) +#define MG12_11_17PL ~(1 << 6) +#else +#define MG12_11_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_11PL) || (G12_8PL == 0) +#define MG12_11_18PL ~(1 << 7) +#else +#define MG12_11_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_11PL) || (G12_9PL == 0) +#define MG12_11_19PL ~(1 << 8) +#else +#define MG12_11_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_11PL) || (G12_10PL == 0) +#define MG12_11_110PL ~(1 << 9) +#else +#define MG12_11_110PL 0xFFFF +#endif + +#if (G12_12PL >= G12_11PL) || (G12_12PL == 0) +#define MG12_11_112PL ~(1 << 11) +#else +#define MG12_11_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_11PL) || (G12_13PL == 0) +#define MG12_11_113PL ~(1 << 12) +#else +#define MG12_11_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_11PL) || (G12_14PL == 0) +#define MG12_11_114PL ~(1 << 13) +#else +#define MG12_11_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_11PL) || (G12_15PL == 0) +#define MG12_11_115PL ~(1 << 14) +#else +#define MG12_11_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_11PL) || (G12_16PL == 0) +#define MG12_11_116PL ~(1 << 15) +#else +#define MG12_11_116PL 0xFFFF +#endif + +#define MG12_11_111PL 0xFBFF +#define MG12_11 (MG12_11_11PL & MG12_11_12PL & MG12_11_13PL & MG12_11_14PL & \ + MG12_11_15PL & MG12_11_16PL & MG12_11_17PL & MG12_11_18PL & \ + MG12_11_19PL & MG12_11_110PL & MG12_11_111PL & MG12_11_112PL & \ + MG12_11_113PL & MG12_11_114PL & MG12_11_115PL & MG12_11_116PL) +// End of MG12_11: +// Beginning of MG1212: +#if (G12_1PL >= G12_12PL) || (G12_1PL == 0) +#define MG12_12_11PL ~(1 << 0) +#else +#define MG12_12_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_12PL) || (G12_2PL == 0) +#define MG12_12_12PL ~(1 << 1) +#else +#define MG12_12_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_12PL) || (G12_3PL == 0) +#define MG12_12_13PL ~(1 << 2) +#else +#define MG12_12_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_12PL) || (G12_4PL == 0) +#define MG12_12_14PL ~(1 << 3) +#else +#define MG12_12_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_12PL) || (G12_5PL == 0) +#define MG12_12_15PL ~(1 << 4) +#else +#define MG12_12_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_12PL) || (G12_6PL == 0) +#define MG12_12_16PL ~(1 << 5) +#else +#define MG12_12_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_12PL) || (G12_7PL == 0) +#define MG12_12_17PL ~(1 << 6) +#else +#define MG12_12_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_12PL) || (G12_8PL == 0) +#define MG12_12_18PL ~(1 << 7) +#else +#define MG12_12_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_12PL) || (G12_9PL == 0) +#define MG12_12_19PL ~(1 << 8) +#else +#define MG12_12_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_12PL) || (G12_10PL == 0) +#define MG12_12_110PL ~(1 << 9) +#else +#define MG12_12_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_12PL) || (G12_11PL == 0) +#define MG12_12_111PL ~(1 << 10) +#else +#define MG12_12_111PL 0xFFFF +#endif + +#if (G12_13PL >= G12_12PL) || (G12_13PL == 0) +#define MG12_12_113PL ~(1 << 12) +#else +#define MG12_12_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_12PL) || (G12_14PL == 0) +#define MG12_12_114PL ~(1 << 13) +#else +#define MG12_12_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_12PL) || (G12_15PL == 0) +#define MG12_12_115PL ~(1 << 14) +#else +#define MG12_12_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_12PL) || (G12_16PL == 0) +#define MG12_12_116PL ~(1 << 15) +#else +#define MG12_12_116PL 0xFFFF +#endif + +#define MG12_12_112PL 0xF7FF +#define MG12_12 (MG12_12_11PL & MG12_12_12PL & MG12_12_13PL & MG12_12_14PL & \ + MG12_12_15PL & MG12_12_16PL & MG12_12_17PL & MG12_12_18PL & \ + MG12_12_19PL & MG12_12_110PL & MG12_12_111PL & MG12_12_112PL & \ + MG12_12_113PL & MG12_12_114PL & MG12_12_115PL & MG12_12_116PL) +// End of MG12_12: +// Beginning of MG1213: +#if (G12_1PL >= G12_13PL) || (G12_1PL == 0) +#define MG12_13_11PL ~(1 << 0) +#else +#define MG12_13_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_13PL) || (G12_2PL == 0) +#define MG12_13_12PL ~(1 << 1) +#else +#define MG12_13_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_13PL) || (G12_3PL == 0) +#define MG12_13_13PL ~(1 << 2) +#else +#define MG12_13_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_13PL) || (G12_4PL == 0) +#define MG12_13_14PL ~(1 << 3) +#else +#define MG12_13_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_13PL) || (G12_5PL == 0) +#define MG12_13_15PL ~(1 << 4) +#else +#define MG12_13_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_13PL) || (G12_6PL == 0) +#define MG12_13_16PL ~(1 << 5) +#else +#define MG12_13_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_13PL) || (G12_7PL == 0) +#define MG12_13_17PL ~(1 << 6) +#else +#define MG12_13_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_13PL) || (G12_8PL == 0) +#define MG12_13_18PL ~(1 << 7) +#else +#define MG12_13_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_13PL) || (G12_9PL == 0) +#define MG12_13_19PL ~(1 << 8) +#else +#define MG12_13_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_13PL) || (G12_10PL == 0) +#define MG12_13_110PL ~(1 << 9) +#else +#define MG12_13_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_13PL) || (G12_11PL == 0) +#define MG12_13_111PL ~(1 << 10) +#else +#define MG12_13_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_13PL) || (G12_12PL == 0) +#define MG12_13_112PL ~(1 << 11) +#else +#define MG12_13_112PL 0xFFFF +#endif + +#if (G12_14PL >= G12_13PL) || (G12_14PL == 0) +#define MG12_13_114PL ~(1 << 13) +#else +#define MG12_13_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_13PL) || (G12_15PL == 0) +#define MG12_13_115PL ~(1 << 14) +#else +#define MG12_13_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_13PL) || (G12_16PL == 0) +#define MG12_13_116PL ~(1 << 15) +#else +#define MG12_13_116PL 0xFFFF +#endif + +#define MG12_13_113PL 0xEFFF +#define MG12_13 (MG12_13_11PL & MG12_13_12PL & MG12_13_13PL & MG12_13_14PL & \ + MG12_13_15PL & MG12_13_16PL & MG12_13_17PL & MG12_13_18PL & \ + MG12_13_19PL & MG12_13_110PL & MG12_13_111PL & MG12_13_112PL & \ + MG12_13_113PL & MG12_13_114PL & MG12_13_115PL & MG12_13_116PL) +// End of MG12_13: +// Beginning of MG1214: +#if (G12_1PL >= G12_14PL) || (G12_1PL == 0) +#define MG12_14_11PL ~(1 << 0) +#else +#define MG12_14_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_14PL) || (G12_2PL == 0) +#define MG12_14_12PL ~(1 << 1) +#else +#define MG12_14_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_14PL) || (G12_3PL == 0) +#define MG12_14_13PL ~(1 << 2) +#else +#define MG12_14_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_14PL) || (G12_4PL == 0) +#define MG12_14_14PL ~(1 << 3) +#else +#define MG12_14_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_14PL) || (G12_5PL == 0) +#define MG12_14_15PL ~(1 << 4) +#else +#define MG12_14_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_14PL) || (G12_6PL == 0) +#define MG12_14_16PL ~(1 << 5) +#else +#define MG12_14_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_14PL) || (G12_7PL == 0) +#define MG12_14_17PL ~(1 << 6) +#else +#define MG12_14_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_14PL) || (G12_8PL == 0) +#define MG12_14_18PL ~(1 << 7) +#else +#define MG12_14_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_14PL) || (G12_9PL == 0) +#define MG12_14_19PL ~(1 << 8) +#else +#define MG12_14_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_14PL) || (G12_10PL == 0) +#define MG12_14_110PL ~(1 << 9) +#else +#define MG12_14_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_14PL) || (G12_11PL == 0) +#define MG12_14_111PL ~(1 << 10) +#else +#define MG12_14_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_14PL) || (G12_12PL == 0) +#define MG12_14_112PL ~(1 << 11) +#else +#define MG12_14_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_14PL) || (G12_13PL == 0) +#define MG12_14_113PL ~(1 << 12) +#else +#define MG12_14_113PL 0xFFFF +#endif + +#if (G12_15PL >= G12_14PL) || (G12_15PL == 0) +#define MG12_14_115PL ~(1 << 14) +#else +#define MG12_14_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_14PL) || (G12_16PL == 0) +#define MG12_14_116PL ~(1 << 15) +#else +#define MG12_14_116PL 0xFFFF +#endif + +#define MG12_14_114PL 0xDFFF +#define MG12_14 (MG12_14_11PL & MG12_14_12PL & MG12_14_13PL & MG12_14_14PL & \ + MG12_14_15PL & MG12_14_16PL & MG12_14_17PL & MG12_14_18PL & \ + MG12_14_19PL & MG12_14_110PL & MG12_14_111PL & MG12_14_112PL & \ + MG12_14_113PL & MG12_14_114PL & MG12_14_115PL & MG12_14_116PL) +// End of MG12_14: +// Beginning of MG1215: +#if (G12_1PL >= G12_15PL) || (G12_1PL == 0) +#define MG12_15_11PL ~(1 << 0) +#else +#define MG12_15_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_15PL) || (G12_2PL == 0) +#define MG12_15_12PL ~(1 << 1) +#else +#define MG12_15_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_15PL) || (G12_3PL == 0) +#define MG12_15_13PL ~(1 << 2) +#else +#define MG12_15_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_15PL) || (G12_4PL == 0) +#define MG12_15_14PL ~(1 << 3) +#else +#define MG12_15_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_15PL) || (G12_5PL == 0) +#define MG12_15_15PL ~(1 << 4) +#else +#define MG12_15_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_15PL) || (G12_6PL == 0) +#define MG12_15_16PL ~(1 << 5) +#else +#define MG12_15_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_15PL) || (G12_7PL == 0) +#define MG12_15_17PL ~(1 << 6) +#else +#define MG12_15_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_15PL) || (G12_8PL == 0) +#define MG12_15_18PL ~(1 << 7) +#else +#define MG12_15_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_15PL) || (G12_9PL == 0) +#define MG12_15_19PL ~(1 << 8) +#else +#define MG12_15_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_15PL) || (G12_10PL == 0) +#define MG12_15_110PL ~(1 << 9) +#else +#define MG12_15_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_15PL) || (G12_11PL == 0) +#define MG12_15_111PL ~(1 << 10) +#else +#define MG12_15_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_15PL) || (G12_12PL == 0) +#define MG12_15_112PL ~(1 << 11) +#else +#define MG12_15_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_15PL) || (G12_13PL == 0) +#define MG12_15_113PL ~(1 << 12) +#else +#define MG12_15_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_15PL) || (G12_14PL == 0) +#define MG12_15_114PL ~(1 << 13) +#else +#define MG12_15_114PL 0xFFFF +#endif + +#if (G12_16PL >= G12_15PL) || (G12_16PL == 0) +#define MG12_15_116PL ~(1 << 15) +#else +#define MG12_15_116PL 0xFFFF +#endif + +#define MG12_15_115PL 0xBFFF +#define MG12_15 (MG12_15_11PL & MG12_15_12PL & MG12_15_13PL & MG12_15_14PL & \ + MG12_15_15PL & MG12_15_16PL & MG12_15_17PL & MG12_15_18PL & \ + MG12_15_19PL & MG12_15_110PL & MG12_15_111PL & MG12_15_112PL & \ + MG12_15_113PL & MG12_15_114PL & MG12_15_115PL & MG12_15_116PL) +// End of MG12_15: +// Beginning of MG1216: +#if (G12_1PL >= G12_16PL) || (G12_1PL == 0) +#define MG12_16_11PL ~(1 << 0) +#else +#define MG12_16_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_16PL) || (G12_2PL == 0) +#define MG12_16_12PL ~(1 << 1) +#else +#define MG12_16_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_16PL) || (G12_3PL == 0) +#define MG12_16_13PL ~(1 << 2) +#else +#define MG12_16_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_16PL) || (G12_4PL == 0) +#define MG12_16_14PL ~(1 << 3) +#else +#define MG12_16_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_16PL) || (G12_5PL == 0) +#define MG12_16_15PL ~(1 << 4) +#else +#define MG12_16_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_16PL) || (G12_6PL == 0) +#define MG12_16_16PL ~(1 << 5) +#else +#define MG12_16_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_16PL) || (G12_7PL == 0) +#define MG12_16_17PL ~(1 << 6) +#else +#define MG12_16_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_16PL) || (G12_8PL == 0) +#define MG12_16_18PL ~(1 << 7) +#else +#define MG12_16_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_16PL) || (G12_9PL == 0) +#define MG12_16_19PL ~(1 << 8) +#else +#define MG12_16_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_16PL) || (G12_10PL == 0) +#define MG12_16_110PL ~(1 << 9) +#else +#define MG12_16_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_16PL) || (G12_11PL == 0) +#define MG12_16_111PL ~(1 << 10) +#else +#define MG12_16_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_16PL) || (G12_12PL == 0) +#define MG12_16_112PL ~(1 << 11) +#else +#define MG12_16_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_16PL) || (G12_13PL == 0) +#define MG12_16_113PL ~(1 << 12) +#else +#define MG12_16_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_16PL) || (G12_14PL == 0) +#define MG12_16_114PL ~(1 << 13) +#else +#define MG12_16_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_16PL) || (G12_15PL == 0) +#define MG12_16_115PL ~(1 << 14) +#else +#define MG12_16_115PL 0xFFFF +#endif + +#define MG12_16_116PL 0x7FFF +#define MG12_16 (MG12_16_11PL & MG12_16_12PL & MG12_16_13PL & MG12_16_14PL & \ + MG12_16_15PL & MG12_16_16PL & MG12_16_17PL & MG12_16_18PL & \ + MG12_16_19PL & MG12_16_110PL & MG12_16_111PL & MG12_16_112PL & \ + MG12_16_113PL & MG12_16_114PL & MG12_16_115PL & MG12_16_116PL) +// End of MG12_16: + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h new file mode 100644 index 0000000000..a0f342d14c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl_defines.h +// +// TITLE: F2837xD LPM support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SYSCTRL_DEFINES_H +#define F2837xD_SYSCTRL_DEFINES_H + +// +// Defines +// +#define LPM_IDLE 0x0 +#define LPM_STANDBY 0x1 +#define LPM_HALT 0x2 +#define LPM_HIB 0x3 + +// +//Key value used for write access to the flash pump semaphore register +// +#define IPC_PUMP_KEY 0x5a5a0000 + +#endif // end of F2837xD_SYSCTRL_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h new file mode 100644 index 0000000000..dbf45cb249 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h @@ -0,0 +1,80 @@ +//########################################################################### +// +// FILE: systick.h +// +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Function Prototypes +// +extern void SysTickInit(void); +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +// +// Mark the end of the C bindings section for C++ compilers. +// +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h new file mode 100644 index 0000000000..43d602bfb0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h @@ -0,0 +1,86 @@ +//########################################################################### +// +// FILE: F2837xD_Upp_defines.h +// +// TITLE: #defines used in Upp examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_UPP_DEFINES_H +#define F2837xD_UPP_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define uPP_TX_MSGRAM_ADDR 0x6C00 +#define uPP_TX_MSGRAM_SIZE 512 + +#define uPP_RX_MSGRAM_ADDR 0x6E00 +#define uPP_RX_MSGRAM_SIZE 512 + +#define uPP_RX_MODE 0 +#define uPP_TX_MODE 1 + +#define uPP_SDR 0 +#define uPP_DDR 1 + +#define uPP_TX_SIZE_64B 0 +#define uPP_TX_SIZE_128B 1 +#define uPP_TX_SIZE_256B 3 + +#define uPP_RX_SIZE_64B 0 +#define uPP_RX_SIZE_128B 1 +#define uPP_RX_SIZE_256B 3 + +#define uPP_INT_EOWI 0x8 +#define uPP_INT_EOLI 0x10 +#define uPP_INT_EOWQ 0x800 +#define uPP_INT_EOLQ 0x1000 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_UPP_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h new file mode 100644 index 0000000000..0f32f58aea --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h @@ -0,0 +1,138 @@ +//########################################################################### +// +// FILE: F2837xD_Cputimers.h +// +// TITLE: F2837xD Device CPUTIMERS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CPUTIMERVARS_H +#define F2837xD_CPUTIMERVARS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Globals +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +extern struct CPUTIMER_VARS CpuTimer0; +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines +// + +// +// Start Timer: +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// Start Timer: +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +// +// Function Prototypes +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of F2837xD_CPUTIMERVARS_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h new file mode 100644 index 0000000000..3f351d85b7 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h @@ -0,0 +1,216 @@ +//########################################################################### +// +// FILE: F2837xD_defaultisr.h +// +// TITLE: F2837xD Device Default Interrupt Service Routines Definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DEFAULT_ISR_H +#define F2837xD_DEFAULT_ISR_H +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the F2837xD_pievect.h +// file. +// +interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt +interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt +interrupt void DATALOG_ISR(void); // Datalogging Interrupt +interrupt void RTOS_ISR(void); // RTOS Interrupt +interrupt void EMU_ISR(void); // Emulation Interrupt +interrupt void NMI_ISR(void); // Non-Maskable Interrupt +interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap +interrupt void USER1_ISR(void); // User Defined Trap 1 +interrupt void USER2_ISR(void); // User Defined Trap 2 +interrupt void USER3_ISR(void); // User Defined Trap 3 +interrupt void USER4_ISR(void); // User Defined Trap 4 +interrupt void USER5_ISR(void); // User Defined Trap 5 +interrupt void USER6_ISR(void); // User Defined Trap 6 +interrupt void USER7_ISR(void); // User Defined Trap 7 +interrupt void USER8_ISR(void); // User Defined Trap 8 +interrupt void USER9_ISR(void); // User Defined Trap 9 +interrupt void USER10_ISR(void); // User Defined Trap 10 +interrupt void USER11_ISR(void); // User Defined Trap 11 +interrupt void USER12_ISR(void); // User Defined Trap 12 +interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 +interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 +interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 +interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt +interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt +interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1 +interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt +interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt +interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt +interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt +interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt +interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt +interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt +interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt +interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt +interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt +interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt +interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt +interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt +interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt +interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt +interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt +interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt +interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt +interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt +interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt +interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt +interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt +interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt +interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt +interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt +interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt +interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt +interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt +interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt +interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt +interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt +interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt +interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt +interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt +interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt +interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt +interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt +interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt +interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt +interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt +interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt +interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 +interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 +interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1 +interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2 +interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt +interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt +interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt +interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt +interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt +interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt +interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt +interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt +interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 +interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 +interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 +interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 +interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt +interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 +interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 +interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 +interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt +interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 +interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 +interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 +interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 +interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 +interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 +interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 +interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 +interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 +interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 +interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 +interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt +interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt +interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt +interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt +interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt +interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt +interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0 +interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1 +interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2 +interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3 +interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt +interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt +interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt +interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt +interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt +interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt +interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt +interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt +interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt +interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt +interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt +interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt +interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt +interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt +interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt +interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 +interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 +interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 +interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt +interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2 +interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3 +interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4 +interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt +interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable + // Error Interrupt +interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable + // Error Interrupt +interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access + // Violation Interrupt +interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip + // Interrupt +interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL + // Slip Interrupt +interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow + // Interrupt +interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow + // Interrupt + +// +// Catch-all for PIE Reserved Locations for testing purposes: +// +interrupt void PIE_RESERVED_ISR(void); // Reserved ISR +interrupt void EMPTY_ISR(void); // Only does a return +interrupt void NOTUSED_ISR(void); // Unused ISR +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of F2837xD_PIEVECT_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h new file mode 100644 index 0000000000..41ecacb9be --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: F2837xD_sci_io.h +// +// TITLE: Prototypes for SCI redirection to STDIO +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SCI_IO_H +#define F2837xD_SCI_IO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Function Prototypes +// +extern int SCI_open(const char * path, unsigned flags, int llv_fd); +extern int SCI_close(int dev_fd); +extern int SCI_read(int dev_fd, char * buf, unsigned count); +extern int SCI_write(int dev_fd, char * buf, unsigned count); +extern off_t SCI_lseek(int dev_fd, off_t offset, int origin); +extern int SCI_unlink(const char * path); +extern int SCI_rename(const char * old_name, const char * new_name); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h new file mode 100644 index 0000000000..0cde1ad5ae --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h @@ -0,0 +1,530 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_drivers.h +// +// TITLE: Defines and Macros for the SDFM driver Controller +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SDFM_DRIVERS_H +#define F2837xD_SDFM_DRIVERS_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// This is used to select either SDFM module 1 & SDFM module 2 +// +#define SDFM1 1 //Can be used to select SDFM module 1 +#define SDFM2 2 //Can be used to select SDFM module 2 + +// +// Max OSR values of different modules +// +#define COMPARATOR_MAX_OSR 32 //Max OSR for comparator +#define DATA_FILTER_MAX_OSR 256 //Max OSR for Data filter + +// +// Different Input Control modes +// These values can be passed as argument to Sdfm_configureInputCtrl() +// +#define MODE_0 0 //Used to select Mode0 : + //Modulator clock rate = Modulator data rate +#define MODE_1 1 //Used to select MODE1 : + //Modulator clock rate = (Modulator data rate / 2) +#define MODE_2 2 //Used to select MODE2 : + //Manchester encoded data + //(Modulator clock is encoded into data) +#define MODE_3 3 //Used to select MODE3 : + //Modulator clock rate = (2 x Modulator data rate) + +// +// The following are values that can be passed to following functions +// +// (1) Sdfm_configureInputCtrl() +// (2) Sdfm_configureComparator() +// (3) Sdfm_configureData_filter() +// (4) Sdfm_configureInterrupt() +// +#define FILTER1 0x01 //Used to select filter1 for comparator or Data filter +#define FILTER2 0x02 //Used to select filter2 for comparator or Data filter +#define FILTER3 0x04 //Used to select filter3 for comparator or Data filter +#define FILTER4 0x08 //Used to select filter4 for comparator or Data filter + +// +// The following are values that can be passed to Sdfm_configureData_filter() +// +#define FILTER_DISABLE 0 //Used to disable filter +#define FILTER_ENABLE 1 //Used to enable filter + +// +// The following are values that can be passed to following functions +// +// (1) Sdfm_configureComparator() +// (2) Sdfm_configureData_filter() +// +#define SINCFAST 0x00 //Used to select Sincfast filter type for comparator + //or Data filter +#define SINC1 0x01 //Used to select Sinc1 filter type for comparator + //or Data filter +#define SINC2 0x02 //Used to select Sinc2 filter type for comparator + //or Data filter +#define SINC3 0x03 //Used to select Sinc3 filter type for comparator + //or Data filter + +// +// Enable / Disable High-level threshold interrupt for Comparator filter output +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define IEH_DISABLE 0 //Used to disable over value interrupt to CPU +#define IEH_ENABLE 1 //Used to enable over value interrupt to CPU + +// +// Enable / Disable Low-level threshold interrupt for Comparator filter output +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define IEL_DISABLE 0 //Used to disable under value interrupt to CPU +#define IEL_ENABLE 1 //Used to enable under value interrupt to CPU + +// +//Enable / Disable modulator failure interrupt +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define MFIE_DISABLE 0 //Used to disable modulator failure interrupt to CPU +#define MFIE_ENABLE 1 //Used to enable modulator failure interrupt to CPU + +// +// Enable / Disable Acknowledge flag +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define AE_DISABLE 0 //Used to disable new filter data acknowledge + //interrupt to CPU +#define AE_ENABLE 1 //Used to enable new filter data acknowledge + //interrupt to CPU + +// +// Sinc Filter Reset enable / disable for External Reset from PWM Compare +// output +// This following value can be passed to Sdfm_configureExternalreset() +// +#define FILTER_1_EXT_RESET_DISABLE 0 +#define FILTER_1_EXT_RESET_ENABLE 1 +#define FILTER_2_EXT_RESET_DISABLE 0 +#define FILTER_2_EXT_RESET_ENABLE 1 +#define FILTER_3_EXT_RESET_DISABLE 0 +#define FILTER_3_EXT_RESET_ENABLE 1 +#define FILTER_4_EXT_RESET_DISABLE 0 +#define FILTER_4_EXT_RESET_ENABLE 1 + +// +// Filter output data can be represented in 16 bit (or) 32 bit format +// This value can be passed to Sdfm_configureData_filter() +// +#define DATA_16_BIT 0 //Data stored in 16b 2's complement +#define DATA_32_BIT 1 //Data stored in 32b 2's complement + +// +// Macro to read the SDFM1 filter data in 16 bit format +// +#define SDFM1_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E17 +#define SDFM1_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5E27 +#define SDFM1_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5E37 +#define SDFM1_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5E47 + +// +// Macro to read the SDFM1 filter data in 32 bit format +// +#define SDFM1_READ_FILTER1_DATA_32BIT *(volatile Uint32 *)0x5E16 +#define SDFM1_READ_FILTER2_DATA_32BIT *(volatile Uint32 *)0x5E26 +#define SDFM1_READ_FILTER3_DATA_32BIT *(volatile Uint32 *)0x5E36 +#define SDFM1_READ_FILTER4_DATA_32BIT *(volatile Uint32 *)0x5E46 + +// +// Macro to read the SDFM2 filter data in 16 bit format +// +#define SDFM2_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E97 +#define SDFM2_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5EA7 +#define SDFM2_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5EB7 +#define SDFM2_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5EC7 + +// +// Macro to read the SDFM2 filter data in 32 bit format +// +#define SDFM2_READ_FILTER1_DATA_32BIT *(volatile Uint16 *)0x5E96 +#define SDFM2_READ_FILTER2_DATA_32BIT *(volatile Uint16 *)0x5EA6 +#define SDFM2_READ_FILTER3_DATA_32BIT *(volatile Uint16 *)0x5EB6 +#define SDFM2_READ_FILTER4_DATA_32BIT *(volatile Uint16 *)0x5EC6 + +// +// The following are defines for different OSR values +// +#define OSR_1 0 +#define OSR_2 1 +#define OSR_3 2 +#define OSR_4 3 +#define OSR_5 4 +#define OSR_6 5 +#define OSR_7 6 +#define OSR_8 7 +#define OSR_9 8 +#define OSR_10 9 +#define OSR_11 10 +#define OSR_12 11 +#define OSR_13 12 +#define OSR_14 13 +#define OSR_15 14 +#define OSR_16 15 +#define OSR_17 16 +#define OSR_18 17 +#define OSR_19 18 +#define OSR_20 19 +#define OSR_21 20 +#define OSR_22 21 +#define OSR_23 22 +#define OSR_24 23 +#define OSR_25 24 +#define OSR_26 25 +#define OSR_27 26 +#define OSR_28 27 +#define OSR_29 28 +#define OSR_30 29 +#define OSR_31 30 +#define OSR_32 31 +#define OSR_33 32 +#define OSR_34 33 +#define OSR_35 34 +#define OSR_36 35 +#define OSR_37 36 +#define OSR_38 37 +#define OSR_39 38 +#define OSR_40 39 +#define OSR_41 40 +#define OSR_42 41 +#define OSR_43 42 +#define OSR_44 43 +#define OSR_45 44 +#define OSR_46 45 +#define OSR_47 46 +#define OSR_48 47 +#define OSR_49 48 +#define OSR_50 49 +#define OSR_51 50 +#define OSR_52 51 +#define OSR_53 52 +#define OSR_54 53 +#define OSR_55 54 +#define OSR_56 55 +#define OSR_57 56 +#define OSR_58 57 +#define OSR_59 58 +#define OSR_60 59 +#define OSR_61 60 +#define OSR_62 61 +#define OSR_63 62 +#define OSR_64 63 +#define OSR_65 64 +#define OSR_66 65 +#define OSR_67 66 +#define OSR_68 67 +#define OSR_69 68 +#define OSR_70 69 +#define OSR_71 70 +#define OSR_72 71 +#define OSR_73 72 +#define OSR_74 73 +#define OSR_75 74 +#define OSR_76 75 +#define OSR_77 76 +#define OSR_78 77 +#define OSR_79 78 +#define OSR_80 79 +#define OSR_81 80 +#define OSR_82 81 +#define OSR_83 82 +#define OSR_84 83 +#define OSR_85 84 +#define OSR_86 85 +#define OSR_87 86 +#define OSR_88 87 +#define OSR_89 88 +#define OSR_90 89 +#define OSR_91 90 +#define OSR_92 91 +#define OSR_93 92 +#define OSR_94 93 +#define OSR_95 94 +#define OSR_96 95 +#define OSR_97 96 +#define OSR_98 97 +#define OSR_99 98 +#define OSR_100 99 +#define OSR_101 100 +#define OSR_102 101 +#define OSR_103 102 +#define OSR_104 103 +#define OSR_105 104 +#define OSR_106 105 +#define OSR_107 106 +#define OSR_108 107 +#define OSR_109 108 +#define OSR_110 109 +#define OSR_111 110 +#define OSR_112 111 +#define OSR_113 112 +#define OSR_114 113 +#define OSR_115 114 +#define OSR_116 115 +#define OSR_117 116 +#define OSR_118 117 +#define OSR_119 118 +#define OSR_120 119 +#define OSR_121 120 +#define OSR_122 121 +#define OSR_123 122 +#define OSR_124 123 +#define OSR_125 124 +#define OSR_126 125 +#define OSR_127 126 +#define OSR_128 127 +#define OSR_129 128 +#define OSR_130 129 +#define OSR_131 130 +#define OSR_132 131 +#define OSR_133 132 +#define OSR_134 133 +#define OSR_135 134 +#define OSR_136 135 +#define OSR_137 136 +#define OSR_138 137 +#define OSR_139 138 +#define OSR_140 139 +#define OSR_141 140 +#define OSR_142 141 +#define OSR_143 142 +#define OSR_144 143 +#define OSR_145 144 +#define OSR_146 145 +#define OSR_147 146 +#define OSR_148 147 +#define OSR_149 148 +#define OSR_150 149 +#define OSR_151 150 +#define OSR_152 151 +#define OSR_153 152 +#define OSR_154 153 +#define OSR_155 154 +#define OSR_156 155 +#define OSR_157 156 +#define OSR_158 157 +#define OSR_159 158 +#define OSR_160 159 +#define OSR_161 160 +#define OSR_162 161 +#define OSR_163 162 +#define OSR_164 163 +#define OSR_165 164 +#define OSR_166 165 +#define OSR_167 166 +#define OSR_168 167 +#define OSR_169 168 +#define OSR_170 169 +#define OSR_171 170 +#define OSR_172 171 +#define OSR_173 172 +#define OSR_174 173 +#define OSR_175 174 +#define OSR_176 175 +#define OSR_177 176 +#define OSR_178 177 +#define OSR_179 178 +#define OSR_180 179 +#define OSR_181 180 +#define OSR_182 181 +#define OSR_183 182 +#define OSR_184 183 +#define OSR_185 184 +#define OSR_186 185 +#define OSR_187 186 +#define OSR_188 187 +#define OSR_189 188 +#define OSR_190 189 +#define OSR_191 190 +#define OSR_192 191 +#define OSR_193 192 +#define OSR_194 193 +#define OSR_195 194 +#define OSR_196 195 +#define OSR_197 196 +#define OSR_198 197 +#define OSR_199 198 +#define OSR_200 199 +#define OSR_201 200 +#define OSR_202 201 +#define OSR_203 202 +#define OSR_204 203 +#define OSR_205 204 +#define OSR_206 205 +#define OSR_207 206 +#define OSR_208 207 +#define OSR_209 208 +#define OSR_210 209 +#define OSR_211 210 +#define OSR_212 211 +#define OSR_213 212 +#define OSR_214 213 +#define OSR_215 214 +#define OSR_216 215 +#define OSR_217 216 +#define OSR_218 217 +#define OSR_219 218 +#define OSR_220 219 +#define OSR_221 220 +#define OSR_222 221 +#define OSR_223 222 +#define OSR_224 223 +#define OSR_225 224 +#define OSR_226 225 +#define OSR_227 226 +#define OSR_228 227 +#define OSR_229 228 +#define OSR_230 229 +#define OSR_231 230 +#define OSR_232 231 +#define OSR_233 232 +#define OSR_234 233 +#define OSR_235 234 +#define OSR_236 235 +#define OSR_237 236 +#define OSR_238 237 +#define OSR_239 238 +#define OSR_240 239 +#define OSR_241 240 +#define OSR_242 241 +#define OSR_243 242 +#define OSR_244 243 +#define OSR_245 244 +#define OSR_246 245 +#define OSR_247 246 +#define OSR_248 247 +#define OSR_249 248 +#define OSR_250 249 +#define OSR_251 250 +#define OSR_252 251 +#define OSR_253 252 +#define OSR_254 253 +#define OSR_255 254 +#define OSR_256 255 + +// +// The following are defines for different OSR values +// +#define SHIFT_0_BITS 0 +#define SHIFT_1_BITS 1 +#define SHIFT_2_BITS 2 +#define SHIFT_3_BITS 3 +#define SHIFT_4_BITS 4 +#define SHIFT_5_BITS 5 +#define SHIFT_6_BITS 6 +#define SHIFT_7_BITS 7 +#define SHIFT_8_BITS 8 +#define SHIFT_9_BITS 9 +#define SHIFT_10_BITS 10 +#define SHIFT_11_BITS 11 +#define SHIFT_12_BITS 12 +#define SHIFT_13_BITS 13 +#define SHIFT_14_BITS 14 +#define SHIFT_15_BITS 15 +#define SHIFT_16_BITS 16 +#define SHIFT_17_BITS 17 +#define SHIFT_18_BITS 18 +#define SHIFT_19_BITS 19 +#define SHIFT_20_BITS 20 +#define SHIFT_21_BITS 21 +#define SHIFT_22_BITS 22 +#define SHIFT_23_BITS 23 +#define SHIFT_24_BITS 24 +#define SHIFT_25_BITS 25 +#define SHIFT_26_BITS 26 +#define SHIFT_27_BITS 27 +#define SHIFT_28_BITS 28 +#define SHIFT_29_BITS 29 +#define SHIFT_30_BITS 30 +#define SHIFT_31_BITS 31 + +// +// Function prototypes +// +extern void Sdfm_configureInputCtrl(Uint16 SDFM_number, + Uint16 Filter_number, Uint16 mode); +extern void Sdfm_configureComparator(Uint16 SDFM_number, + Uint16 Filter_number, Uint16 Filter_type, + Uint16 OSR, Uint16 HLT, Uint16 LLT); +extern void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, + Uint16 shift_bits); +extern void Sdfm_enableMFE(Uint16 SDFM_number); +extern void Sdfm_disableMFE(Uint16 SDFM_number); +extern void Sdfm_configureInterrupt(Uint16 SDFM_number, Uint16 Filter_number, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch); +extern void Sdfm_enableMIE(Uint16 SDFM_number); +extern void Sdfm_disableMIE(Uint16 SDFM_number); +extern void Sdfm_configureExternalreset(Uint16 SDFM_number, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset); +extern Uint32 Sdfm_readFlagRegister(Uint16 SDFM_number); +extern void Sdfm_clearFlagRegister(Uint16 sdfmNumber, + Uint32 sdfmReadFlagRegister); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_SDFM_DRIVERS_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h new file mode 100644 index 0000000000..bd307dd782 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h @@ -0,0 +1,82 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_strut.h +// +// TITLE: contains structures used for the SDFM driver. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SDFM_STRUCT_H +#define F2837xD_SDFM_STRUCT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_CPUTIMER 4 +#define MAX_ECAP 7 +#define MAX_EPWM 13 +#define MAX_EQEP 4 +#define MAX_I2C 2 +#define MAX_MCBSP 2 +#define MAX_SCI 2 +#define MAX_SPI 4 +#define MAX_ADC 5 +#define MAX_SDFM 3 +#define MAX_TRIPSEL 15 + +extern volatile Uint16 *TRIP_SEL[MAX_TRIPSEL]; +extern volatile struct ADC_REGS *ADC[MAX_ADC]; +extern volatile struct CPUTIMER_REGS *CPUTIMER[MAX_CPUTIMER]; +extern volatile struct ECAP_REGS *ECAP[MAX_ECAP]; +extern volatile struct EPWM_REGS *EPWM[MAX_EPWM]; +extern volatile struct EQEP_REGS *EQEP[MAX_EQEP]; +extern volatile struct I2C_REGS *I2C[MAX_I2C]; +extern volatile struct McBSP_REGS *MCBSP[MAX_MCBSP]; +extern volatile struct SCI_REGS *SCI[MAX_SCI]; +extern volatile struct SPI_REGS *SPI[MAX_SPI]; +extern volatile struct SDFM_REGS *SDFM[MAX_SDFM]; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_SDFM_STRUCT_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F28x_Project.h b/bsp/tms320f28379d/libraries/common/include/F28x_Project.h new file mode 100644 index 0000000000..ffdaa6e98c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F28x_Project.h @@ -0,0 +1,58 @@ +//########################################################################### +// +// FILE: F28x_Project.h +// +// TITLE: F28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F28X_PROJECT_H +#define F28X_PROJECT_H + +// +// Included Files +// +#include "F2837xD_Cla_typedefs.h" // F2837xD CLA Type definitions +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + + +#endif // end of F28X_PROJECT_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/device.h b/bsp/tms320f28379d/libraries/common/include/device.h new file mode 100644 index 0000000000..9a8e0ad33e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/device.h @@ -0,0 +1,199 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX + +// +// CANA +// +#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA +#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA + +// +// CAN External Loopback +// +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void Device_init(void); +extern void Device_enableAllPeripherals(void); +extern void Device_initGPIO(void); +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +extern void Device_enableUnbondedGPIOPullups(void); +extern void __error__(char *filename, uint32_t line); + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/driverlib.h b/bsp/tms320f28379d/libraries/common/include/driverlib.h new file mode 100644 index 0000000000..0dd941033f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/driverlib.h @@ -0,0 +1,82 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/bsp/tm4c129x-dk/libraries/driverlib/usb.h b/bsp/tms320f28379d/libraries/common/include/usb.h similarity index 74% rename from bsp/tm4c129x-dk/libraries/driverlib/usb.h rename to bsp/tms320f28379d/libraries/common/include/usb.h index 1fed815842..1eb1f8396e 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/usb.h +++ b/bsp/tms320f28379d/libraries/common/include/usb.h @@ -1,41 +1,45 @@ -//***************************************************************************** -// -// usb.h - Prototypes for the USB Interface Driver. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +//########################################################################### // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: +// FILE: usb.h // -// Redistributions of source code must retain the above copyright +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### + #ifndef __DRIVERLIB_USB_H__ #define __DRIVERLIB_USB_H__ @@ -51,6 +55,16 @@ extern "C" { #endif +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001 +#define USB_ID_HOST 0x0002 +#define USB_ID_DEVICE 0x0000 +#define USB_PFLT_ACTIVE 0x0004 + //***************************************************************************** // // The following are values that can be passed to USBIntEnableControl() and @@ -157,7 +171,6 @@ extern "C" // //***************************************************************************** #define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined -#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed #define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed #define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed @@ -168,7 +181,7 @@ extern "C" // USB_DEV_* values are used when the USB controller is in device mode. // //***************************************************************************** -#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts #define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received #define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond #define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received @@ -180,7 +193,7 @@ extern "C" // device #define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full #define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready -#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts #define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the // specified timeout period #define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device @@ -228,9 +241,6 @@ extern "C" #define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled #define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 #define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 -#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for - // high-speed Bulk and Interrupt - // endpoints in device mode. #define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint #define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint #define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint @@ -238,7 +248,6 @@ extern "C" #define USB_EP_MODE_MASK 0x00000300 // Mode Mask #define USB_EP_SPEED_LOW 0x00000000 // Low Speed #define USB_EP_SPEED_FULL 0x00001000 // Full Speed -#define USB_EP_SPEED_HIGH 0x00004000 // High Speed #define USB_EP_HOST_IN 0x00000000 // Host IN endpoint #define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint #define USB_EP_DEV_IN 0x00002000 // Device IN endpoint @@ -262,66 +271,6 @@ extern "C" #define USB_HOST_PWREN_AUTOHIGH 0x00000003 #define USB_HOST_PWREN_FILTER 0x00010000 -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// USBHostLPMConfig() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_HOST_LPM_RMTWAKE 0x00000100 -#define USB_HOST_LPM_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// USBDevLPMConfig() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_DEV_LPM_NAK 0x00000010 -#define USB_DEV_LPM_NONE 0x00000000 -#define USB_DEV_LPM_EN 0x0000000c -#define USB_DEV_LPM_EXTONLY 0x00000004 - -//***************************************************************************** -// -// The following are the valid values that are returned from the -// USBLPMLinkStateGet() function. -// -//***************************************************************************** -#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 -#define USB_DEV_LPM_LS_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the USBLPMIntEnable() -// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus() -// function. -// -//***************************************************************************** -#define USB_INTLPM_ERROR 0x00000020 -#define USB_INTLPM_RESUME 0x00000010 -#define USB_INTLPM_INCOMPLETE 0x00000008 -#define USB_INTLPM_ACK 0x00000004 -#define USB_INTLPM_NYET 0x00000002 -#define USB_INTLPM_STALL 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the USBClockEnable() -// functions. -// -//***************************************************************************** -#define USB_CLOCK_INTERNAL 0x00000200 -#define USB_CLOCK_EXTERNAL 0x00000300 - -//***************************************************************************** -// -// The configuration options used with the USBULPIConfig() API. -// -//***************************************************************************** -#define USB_ULPI_EXTVBUS 0x00000001 -#define USB_ULPI_EXTVBUS_IND 0x00000002 - //***************************************************************************** // // The following are special values that can be passed to @@ -352,7 +301,15 @@ extern "C" #define USB_EP_5 0x00000050 // Endpoint 5 #define USB_EP_6 0x00000060 // Endpoint 6 #define USB_EP_7 0x00000070 // Endpoint 7 -#define NUM_USB_EP 8 // Number of supported endpoints +#define USB_EP_8 0x00000080 // Endpoint 8 +#define USB_EP_9 0x00000090 // Endpoint 9 +#define USB_EP_10 0x000000A0 // Endpoint 10 +#define USB_EP_11 0x000000B0 // Endpoint 11 +#define USB_EP_12 0x000000C0 // Endpoint 12 +#define USB_EP_13 0x000000D0 // Endpoint 13 +#define USB_EP_14 0x000000E0 // Endpoint 14 +#define USB_EP_15 0x000000F0 // Endpoint 15 +#define NUM_USB_EP 16 // Number of supported endpoints //***************************************************************************** // @@ -360,7 +317,7 @@ extern "C" // USB_EP_x values required when calling various USB APIs. // //***************************************************************************** -#define IndexToUSBEP(x) ((x) << 4) +#define IndexToUSBEP(x) (((uint32_t)(x) << 4) & 0xFF) #define USBEPToIndex(x) ((x) >> 4) //***************************************************************************** @@ -378,6 +335,25 @@ extern "C" #define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO #define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO #define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO + // (occupying 4096 bytes) //***************************************************************************** // @@ -385,7 +361,8 @@ extern "C" // a number of bytes // //***************************************************************************** -#define USBFIFOSizeToBytes(x) (8 << (x)) +#define USB_FIFO_SIZE_DB_FLAG 0x00000010 +#define USBFIFOSizeToBytes(x) ((uint32_t)8 << (x)) //***************************************************************************** // @@ -431,67 +408,6 @@ extern "C" // the cable. #define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. -//***************************************************************************** -// -// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus() -// APIs. -// -//***************************************************************************** -#define USB_DMA_INT_CH8 0x00000080 -#define USB_DMA_INT_CH7 0x00000040 -#define USB_DMA_INT_CH6 0x00000020 -#define USB_DMA_INT_CH5 0x00000010 -#define USB_DMA_INT_CH4 0x00000008 -#define USB_DMA_INT_CH3 0x00000004 -#define USB_DMA_INT_CH2 0x00000002 -#define USB_DMA_INT_CH1 0x00000001 - -//***************************************************************************** -// -// The values for the USBDMAChannelStatus() API. -// -//***************************************************************************** -#define USB_DMA_STATUS_ERROR 0x00000100 - -//***************************************************************************** -// -// The valid return values for the USBControllerVersion() API. -// -//***************************************************************************** -#define USB_CONTROLLER_VER_0 0x00000000 // This is for Blizzard class - // devices. -#define USB_CONTROLLER_VER_1 0x00000001 // This is for Snowflake class - // devices. - -//***************************************************************************** -// -// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or -// USBDMAChannelConfig(). -// -//***************************************************************************** -#define USB_DMA_CFG_BURST_NONE 0x00000000 -#define USB_DMA_CFG_BURST_4 0x00000200 -#define USB_DMA_CFG_BURST_8 0x00000400 -#define USB_DMA_CFG_BURST_16 0x00000600 -#define USB_DMA_CFG_INT_EN 0x00000008 -#define USB_DMA_CFG_MODE_0 0x00000000 -#define USB_DMA_CFG_MODE_1 0x00000004 -#define USB_DMA_CFG_DIR_RX 0x00000000 -#define USB_DMA_CFG_DIR_TX 0x00000002 -#define USB_DMA_CFG_EN 0x00000001 - -//***************************************************************************** -// -// The following are values that can be passed to USBModeConfig() as the -// ui3Mode parameter. -// -//***************************************************************************** -#define USB_MODE_HOST_VBUS 0x00000004 -#define USB_MODE_HOST 0x00000002 -#define USB_MODE_DEV_VBUS 0x00000005 -#define USB_MODE_DEV 0x00000003 -#define USB_MODE_OTG 0x00000000 - //***************************************************************************** // // Prototypes for the APIs. @@ -578,6 +494,7 @@ extern uint32_t USBHostSpeedGet(uint32_t ui32Base); extern void USBHostSuspend(uint32_t ui32Base); extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); extern uint32_t USBIntStatusControl(uint32_t ui32Base); extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); @@ -588,64 +505,50 @@ extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); extern uint32_t USBModeGet(uint32_t ui32Base); extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Channel); -extern uint32_t USBControllerVersion(uint32_t ui32Base); -extern uint32_t USBDMAChannelIntStatus(uint32_t ui32Base); -extern void USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Endpoint, uint32_t ui32Config); -extern void USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, - void *pvAddress); -extern void *USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Count, - uint32_t ui32Channel); -extern uint32_t USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel); -extern uint32_t USBDMANumChannels(uint32_t ui32Base); -extern void USBDMAChannelAssign(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Channel, uint32_t ui32Flags); -extern void USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel); -extern uint32_t USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel); -extern void USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Status); -extern void USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bEnable); -extern void USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, - uint32_t uiEndpoint); -extern void USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, - uint32_t ui32Config); -extern bool USBLPMRemoteWakeEnabled(uint32_t ui32Base); -extern void USBHostLPMResume(uint32_t ui32Base); -extern void USBDevLPMRemoteWake(uint32_t ui32Base); -extern void USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config); -extern void USBDevLPMEnable(uint32_t ui32Base); -extern void USBDevLPMDisable(uint32_t ui32Base); -extern uint32_t USBLPMLinkStateGet(uint32_t ui32Base); -extern uint32_t USBLPMEndpointGet(uint32_t ui32Base); -extern uint32_t USBLPMIntStatus(uint32_t ui32Base); -extern void USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints); -extern void USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints); -extern void USBHighSpeed(uint32_t ui32Base, bool bEnable); -extern uint32_t USBDevSpeedGet(uint32_t ui32Base); -extern void USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, - uint32_t ui32Flags); -extern void USBClockDisable(uint32_t ui32Base); -extern void USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config); -extern void USBULPIEnable(uint32_t ui32Base); -extern void USBULPIDisable(uint32_t ui32Base); -extern uint8_t USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg); -extern void USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, - uint8_t ui8Data); extern void USBHostMode(uint32_t ui32Base); extern void USBDevMode(uint32_t ui32Base); extern void USBOTGMode(uint32_t ui32Base); -extern void USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode); extern void USBPHYPowerOff(uint32_t ui32Base); extern void USBPHYPowerOn(uint32_t ui32Base); extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); +//***************************************************************************** +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0F // All Interrupt sources +#define USB_INT_STATUS 0xFF000000 // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error +#define USB_INT_SESSION_START 0x40000000 // Session Start Detected +#define USB_INT_SESSION_END 0x20000000 // Session End Detected +#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected +#define USB_INT_CONNECT 0x10000000 // Device Connect Detected +#define USB_INT_SOF 0x08000000 // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000 // Babble signaled +#define USB_INT_RESET 0x04000000 // Reset signaled +#define USB_INT_RESUME 0x02000000 // Resume detected +#define USB_INT_SUSPEND 0x01000000 // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt + //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. diff --git a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.h b/bsp/tms320f28379d/libraries/common/include/usb_hal.h similarity index 63% rename from bsp/tm4c129x-dk/libraries/driverlib/sw_crc.h rename to bsp/tms320f28379d/libraries/common/include/usb_hal.h index 0e60775ffc..d89577ebc3 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/sw_crc.h +++ b/bsp/tms320f28379d/libraries/common/include/usb_hal.h @@ -1,78 +1,82 @@ -//***************************************************************************** +//########################################################################### +// FILE: usb_hal.h +// TITLE: Compatability layer for ported software. +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ // -// sw_crc.h - Prototypes for the software CRC functions. -// -// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### -#ifndef __DRIVERLIB_SW_CRC_H__ -#define __DRIVERLIB_SW_CRC_H__ +#ifndef __USB_HAL_H__ +#define __USB_HAL_H__ //***************************************************************************** -// // If building with a C++ compiler, make all of the definitions in this header // have a C binding. -// //***************************************************************************** #ifdef __cplusplus extern "C" { #endif -//***************************************************************************** -// -// Prototypes for the functions. -// -//***************************************************************************** -extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, - uint32_t ui32Count); -extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, - uint32_t ui32Count); -extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data); -extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data, - uint16_t *pui16Crc3); -extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, - uint32_t ui32Count); + + +//***************************************************************************** +//! \addtogroup c2000_specific +//! @{ +//***************************************************************************** + +extern void USBGPIOEnable(void); +extern void USBGPIODisable(void); +extern void USBDelay(uint32_t ui32Delay); + +extern void f28x_USB0DeviceIntHandler(void); +extern void f28x_USB0HostIntHandler(void); +extern void f28x_USB0DualModeIntHandler(void); +extern void f28x_USB0OTGModeIntHandler(void); + //***************************************************************************** -// // Mark the end of the C bindings section for C++ compilers. -// //***************************************************************************** #ifdef __cplusplus } #endif -#endif // __DRIVERLIB_SW_CRC_H__ +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + +#endif // __F28X_USB_HAL_H__ + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c new file mode 100644 index 0000000000..3959c44698 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: F2837xD_Adc.c +// +// TITLE: F2837xD Adc Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// AdcSetMode - Set the resolution and signalmode for a given ADC. This will +// ensure that the correct trim is loaded. +// +// NOTE!!! There is no EALLOW/EDIS in this function! You need to make sure you +// perform the EALLOW before calling this function or else the ADC registers +// will not be configured. +// +void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode) +{ + Uint16 adcOffsetTrimOTPIndex; //index into OTP table of ADC offset trims + Uint16 adcOffsetTrim; //temporary ADC offset trim + + // + //re-populate INL trim + // + CalAdcINL(adc); + + if(0xFFFF != *((Uint16*)GetAdcOffsetTrimOTP)) + { + // + //offset trim function is programmed into OTP, so call it + // + + // + //calculate the index into OTP table of offset trims and call + //function to return the correct offset trim + // +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + adcOffsetTrimOTPIndex = 4*adc + 1*signalmode; + } + else + { + adcOffsetTrimOTPIndex = 4*adc + 1*signalmode + 2; + } + + adcOffsetTrim = (*GetAdcOffsetTrimOTP)(adcOffsetTrimOTPIndex); + } + else + { + // + //offset trim function is not populated, so set offset trim to 0 + // + adcOffsetTrim = 0; + } + + // + // Apply the resolution and signalmode to the specified ADC. + // Also apply the offset trim and, if needed, linearity trim correction. + // + switch(adc) + { + case ADC_ADCA: + { + AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCB: + { + AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCC: + { + AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdccRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 0; + // + //12-bit linearity trim workaround + // + AdccRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCD: + { + AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + } +} + +// +// CalAdcINL - Loads INL trim values from OTP into the trim registers of the +// specified ADC. Use only as part of AdcSetMode function, since +// linearity trim correction is needed for some modes. +// +void CalAdcINL(Uint16 adc) +{ + switch(adc) + { + case ADC_ADCA: + if(0xFFFF != *((Uint16*)CalAdcaINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcaINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCB: + if(0xFFFF != *((Uint16*)CalAdcbINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcbINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCC: + if(0xFFFF != *((Uint16*)CalAdccINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdccINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCD: + if(0xFFFF != *((Uint16*)CalAdcdINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcdINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + } +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm b/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm new file mode 100644 index 0000000000..cd08bf30c0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm @@ -0,0 +1,111 @@ +;//########################################################################### +;// +;// FILE: F2837xD_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example F2837xD projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +*********************************************************************** + +WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot._asm in RTS library + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c new file mode 100644 index 0000000000..1a0877ea6d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c @@ -0,0 +1,181 @@ +//########################################################################### +// +// FILE: F2837xD_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Globals +// +struct CPUTIMER_VARS CpuTimer0; +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void InitCpuTimers(void) +{ + // + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped: + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer0.InterruptCount = 0; + + // + // Initialize address pointers to respective timer registers: + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + + // + // Make sure timers are stopped: + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" +// is entered as "MHz" and the period in "uSeconds". The timer +// is held in the stopped state after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period: + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + + // + // Counter decrements PRD+1 times each period + // + Timer->RegsAddr->PRD.all = temp - 1; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register: + // + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart + // Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer + // Interrupt + + // + // Reset interrupt counter: + // + Timer->InterruptCount = 0; +} + + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm b/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm new file mode 100644 index 0000000000..951fe6a28a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm @@ -0,0 +1,60 @@ +;//########################################################################### +;// +;// FILE: F2837xD_DBGIER.asm +;// +;// TITLE: Set the DBGIER register +;// +;// DESCRIPTION: +;// +;// Function to set the DBGIER register (for realtime emulation). +;// Function Prototype: void SetDBGIER(Uint16) +;// Usage: SetDBGIER(value); +;// Input Parameters: Uint16 value = value to put in DBGIER register. +;// Return Value: none +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + .global _SetDBGIER + .text + +_SetDBGIER: + MOV *SP++,AL + POP DBGIER + LRETR + +;// +;// End of file +;// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c new file mode 100644 index 0000000000..bd589343b6 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c @@ -0,0 +1,3138 @@ +//########################################################################### +// +// FILE: F2837xD_DefaultISR.c +// +// TITLE: F2837xD Device Default Interrupt Service Routines +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// CPU Timer 1 Interrupt +// +interrupt void TIMER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// CPU Timer 2 Interrupt +// +interrupt void TIMER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Datalogging Interrupt +// +interrupt void DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOS Interrupt +// +interrupt void RTOS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Emulation Interrupt +// +interrupt void EMU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Non-Maskable Interrupt +// +interrupt void NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Illegal Operation Trap +// +interrupt void ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 1 +// +interrupt void USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 2 +// +interrupt void USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 3 +// +interrupt void USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 4 +// +interrupt void USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 5 +// +interrupt void USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 6 +// +interrupt void USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 7 +// +interrupt void USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 8 +// +interrupt void USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 9 +// +interrupt void USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 10 +// +interrupt void USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 11 +// +interrupt void USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 12 +// +interrupt void USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.1 - ADCA Interrupt 1 +// +interrupt void ADCA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.2 - ADCB Interrupt 1 +// +interrupt void ADCB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.3 - ADCC Interrupt 1 +// +interrupt void ADCC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.4 - XINT1 Interrupt +// +interrupt void XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.5 - XINT2 Interrupt +// +interrupt void XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.6 - ADCD Interrupt 1 +// +interrupt void ADCD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.7 - Timer 0 Interrupt +// +interrupt void TIMER0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.8 - Standby and Halt Wakeup Interrupt +// +interrupt void WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.1 - ePWM1 Trip Zone Interrupt +// +interrupt void EPWM1_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.2 - ePWM2 Trip Zone Interrupt +// +interrupt void EPWM2_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.3 - ePWM3 Trip Zone Interrupt +// +interrupt void EPWM3_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.4 - ePWM4 Trip Zone Interrupt +// +interrupt void EPWM4_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.5 - ePWM5 Trip Zone Interrupt +// +interrupt void EPWM5_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.6 - ePWM6 Trip Zone Interrupt +// +interrupt void EPWM6_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.7 - ePWM7 Trip Zone Interrupt +// +interrupt void EPWM7_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.8 - ePWM8 Trip Zone Interrupt +// +interrupt void EPWM8_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.1 - ePWM1 Interrupt +// +interrupt void EPWM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.2 - ePWM2 Interrupt +// +interrupt void EPWM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.3 - ePWM3 Interrupt +// +interrupt void EPWM3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.4 - ePWM4 Interrupt +// +interrupt void EPWM4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.5 - ePWM5 Interrupt +// +interrupt void EPWM5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.6 - ePWM6 Interrupt +// +interrupt void EPWM6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.7 - ePWM7 Interrupt +// +interrupt void EPWM7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.8 - ePWM8 Interrupt +// +interrupt void EPWM8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.1 - eCAP1 Interrupt +// +interrupt void ECAP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.2 - eCAP2 Interrupt +// +interrupt void ECAP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.3 - eCAP3 Interrupt +// +interrupt void ECAP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.4 - eCAP4 Interrupt +// +interrupt void ECAP4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.5 - eCAP5 Interrupt +// +interrupt void ECAP5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.6 - eCAP6 Interrupt +// +interrupt void ECAP6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.1 - eQEP1 Interrupt +// +interrupt void EQEP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.2 - eQEP2 Interrupt +// +interrupt void EQEP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.3 - eQEP3 Interrupt +// +interrupt void EQEP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.1 - SPIA Receive Interrupt +// +interrupt void SPIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.2 - SPIA Transmit Interrupt +// +interrupt void SPIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.3 - SPIB Receive Interrupt +// +interrupt void SPIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.4 - SPIB Transmit Interrupt +// +interrupt void SPIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.5 - McBSPA Receive Interrupt +// +interrupt void MCBSPA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.6 - McBSPA Transmit Interrupt +// +interrupt void MCBSPA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.7 - McBSPB Receive Interrupt +// +interrupt void MCBSPB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.8 - McBSPB Transmit Interrupt +// +interrupt void MCBSPB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.1 - DMA Channel 1 Interrupt +// +interrupt void DMA_CH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.2 - DMA Channel 2 Interrupt +// +interrupt void DMA_CH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.3 - DMA Channel 3 Interrupt +// +interrupt void DMA_CH3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.4 - DMA Channel 4 Interrupt +// +interrupt void DMA_CH4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.5 - DMA Channel 5 Interrupt +// +interrupt void DMA_CH5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.6 - DMA Channel 6 Interrupt +// +interrupt void DMA_CH6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.1 - I2CA Interrupt 1 +// +interrupt void I2CA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.2 - I2CA Interrupt 2 +// +interrupt void I2CA_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.3 - I2CB Interrupt 1 +// +interrupt void I2CB_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.4 - I2CB Interrupt 2 +// +interrupt void I2CB_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.5 - SCIC Receive Interrupt +// +interrupt void SCIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.6 - SCIC Transmit Interrupt +// +interrupt void SCIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.7 - SCID Receive Interrupt +// +interrupt void SCID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.8 - SCID Transmit Interrupt +// +interrupt void SCID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.1 - SCIA Receive Interrupt +// +interrupt void SCIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.2 - SCIA Transmit Interrupt +// +interrupt void SCIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.3 - SCIB Receive Interrupt +// +interrupt void SCIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.4 - SCIB Transmit Interrupt +// +interrupt void SCIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.5 - CANA Interrupt 0 +// +interrupt void CANA0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.6 - CANA Interrupt 1 +// +interrupt void CANA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.7 - CANB Interrupt 0 +// +interrupt void CANB0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.8 - CANB Interrupt 1 +// +interrupt void CANB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.1 - ADCA Event Interrupt +// +interrupt void ADCA_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.2 - ADCA Interrupt 2 +// +interrupt void ADCA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.3 - ADCA Interrupt 3 +// +interrupt void ADCA3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.4 - ADCA Interrupt 4 +// +interrupt void ADCA4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.5 - ADCB Event Interrupt +// +interrupt void ADCB_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.6 - ADCB Interrupt 2 +// +interrupt void ADCB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.7 - ADCB Interrupt 3 +// +interrupt void ADCB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.8 - ADCB Interrupt 4 +// +interrupt void ADCB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.1 - CLA1 Interrupt 1 +// +interrupt void CLA1_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.2 - CLA1 Interrupt 2 +// +interrupt void CLA1_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.3 - CLA1 Interrupt 3 +// +interrupt void CLA1_3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.4 - CLA1 Interrupt 4 +// +interrupt void CLA1_4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.5 - CLA1 Interrupt 5 +// +interrupt void CLA1_5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.6 - CLA1 Interrupt 6 +// +interrupt void CLA1_6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.7 - CLA1 Interrupt 7 +// +interrupt void CLA1_7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.8 - CLA1 Interrupt 8 +// +interrupt void CLA1_8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.1 - XINT3 Interrupt +// +interrupt void XINT3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.2 - XINT4 Interrupt +// +interrupt void XINT4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.3 - XINT5 Interrupt +// +interrupt void XINT5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.6 - VCU Interrupt +// +interrupt void VCU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.7 - FPU Overflow Interrupt +// +interrupt void FPU_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.8 - FPU Underflow Interrupt +// +interrupt void FPU_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.13 - IPC Interrupt 0 +// +interrupt void IPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.14 - IPC Interrupt 1 +// +interrupt void IPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.15 - IPC Interrupt 2 +// +interrupt void IPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.16 - IPC Interrupt 3 +// +interrupt void IPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.9 - ePWM9 Trip Zone Interrupt +// +interrupt void EPWM9_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.10 - ePWM10 Trip Zone Interrupt +// +interrupt void EPWM10_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.11 - ePWM11 Trip Zone Interrupt +// +interrupt void EPWM11_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.12 - ePWM12 Trip Zone Interrupt +// +interrupt void EPWM12_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.9 - ePWM9 Interrupt +// +interrupt void EPWM9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.10 - ePWM10 Interrupt +// +interrupt void EPWM10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.11 - ePWM11 Interrupt +// +interrupt void EPWM11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.12 - ePWM12 Interrupt +// +interrupt void EPWM12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.9 - SD1 Interrupt +// +interrupt void SD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.10 - SD2 Interrupt +// +interrupt void SD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.9 - SPIC Receive Interrupt +// +interrupt void SPIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.10 - SPIC Transmit Interrupt +// +interrupt void SPIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.15 - uPPA Interrupt +// +interrupt void UPPA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.15 - USBA Interrupt +// +interrupt void USBA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.9 - ADCC Event Interrupt +// +interrupt void ADCC_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.10 - ADCC Interrupt 2 +// +interrupt void ADCC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.11 - ADCC Interrupt 3 +// +interrupt void ADCC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.12 - ADCC Interrupt 4 +// +interrupt void ADCC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.13 - ADCD Event Interrupt +// +interrupt void ADCD_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.14 - ADCD Interrupt 2 +// +interrupt void ADCD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.15 - ADCD Interrupt 3 +// +interrupt void ADCD3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.16 - ADCD Interrupt 4 +// +interrupt void ADCD4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.9 - EMIF Error Interrupt +// +interrupt void EMIF_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.10 - RAM Correctable Error Interrupt +// +interrupt void RAM_CORRECTABLE_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.11 - Flash Correctable Error Interrupt +// +interrupt void FLASH_CORRECTABLE_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.12 - RAM Access Violation Interrupt +// +interrupt void RAM_ACCESS_VIOLATION_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.13 - System PLL Slip Interrupt +// +interrupt void SYS_PLL_SLIP_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.14 - Auxiliary PLL Slip Interrupt +// +interrupt void AUX_PLL_SLIP_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.15 - CLA Overflow Interrupt +// +interrupt void CLA_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.16 - CLA Underflow Interrupt +// +interrupt void CLA_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch-all Default ISRs: +// + +// +// PIE_RESERVED_ISR - Reserved ISR +// +interrupt void PIE_RESERVED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// EMPTY_ISR - Only does a return +// +interrupt void EMPTY_ISR(void) +{ + +} + +// +// NOTUSED_ISR - Unused ISR +// +interrupt void NOTUSED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c new file mode 100644 index 0000000000..ca5593c851 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c @@ -0,0 +1,1100 @@ +//########################################################################### +// +// FILE: F2837xD_DMA.c +// +// TITLE: F2837xD Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// DMAInitialize - This function initializes the DMA to a known state. +// +void DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + __asm (" nop"); // one NOP required after HARDRESET + + // + // Allow DMA to run free on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + +// +// DMACH1AddrConfig - DMA Channel 1 Address Configuration +// +void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to + // beginning of + // destination buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH1BurstConfig - DMA Channel 1 Burst size configuration +// +void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) + // x-ferred in a burst. + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between + // each word x-ferred. + + EDIS; +} + +// +// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration +// +void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored + // when WRAP occurs. + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored + // when WRAP occurs. + + EDIS; +} + +// +// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration +// +void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH1ModeConfig - DMA Channel 1 Mode configuration +// +void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; + DmaRegs.CH1.MODE.bit.PERINTSEL = 1; + DmaRegs.CH1.MODE.bit.PERINTE = perinte; + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH1.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt and sync error flags + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH1 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; + + EDIS; +} + +// +// StartDMACH1 - This function starts DMA Channel 1. +// +void StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH2AddrConfig - DMA Channel 2 Address Configuration +// +void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer. + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2BurstConfig - DMA Channel 2 Burst size configuration +// +void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration +// +void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration +// +void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH2ModeConfig - DMA Channel 2 Mode configuration +// +void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; + DmaRegs.CH2.MODE.bit.PERINTSEL = 2; + DmaRegs.CH2.MODE.bit.PERINTE = perinte; + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH2.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH2 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; + + EDIS; +} + +// +// StartDMACH2 - This function starts DMA Channel 2. +// +void StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH3AddrConfig - DMA Channel 3 Address configuration +// +void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3BurstConfig - DMA Channel 3 burst size configuration +// +void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH3TransferConfig - DMA channel 3 transfer size configuration +// +void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH3WrapConfig - DMA Channel 3 wrap size configuration +// +void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH3ModeConfig - DMA Channel 3 mode configuration +// +void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; + DmaRegs.CH3.MODE.bit.PERINTSEL = 3; + DmaRegs.CH3.MODE.bit.PERINTE = perinte; + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH3.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt flags and sync error flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH3 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; + + EDIS; +} + +// +// StartDMACH3 - This function starts DMA Channel 3. +// +void StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH4AddrConfig - DMA Channel 4 address configuration +// +void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4BurstConfig - DMA Channel 4 burst size configuration +// +void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH4TransferConfig - DMA channel 4 transfer size configuration +// +void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH4WrapConfig - DMA channel 4 wrap size configuration +// +void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH4ModeConfig - DMA Channel 4 mode configuration +// +void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; + DmaRegs.CH4.MODE.bit.PERINTSEL = 4; + DmaRegs.CH4.MODE.bit.PERINTE = perinte; + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH4.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH4 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; + + EDIS; +} + +// +// StartDMACH4 - This function starts DMA Channel 4. +// +void StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH5AddrConfig - DMA channel 5 address configuration +// +void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5BurstConfig - DMA Channel 5 burst size configuration +// +void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH5TransferConfig - DMA channel 5 transfer size configuration +// +void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH5WrapConfig - DMA Channel 5 wrap size configuration +// +void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH5ModeConfig - DMA Channel 5 mode configuration +// +void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; + DmaRegs.CH5.MODE.bit.PERINTSEL = 5; + DmaRegs.CH5.MODE.bit.PERINTE = perinte; + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH5.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH5 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; + + EDIS; +} + +// +// StartDMACH5 - This function starts DMA Channel 5. +// +void StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH6AddrConfig - DMA Channel 6 address configuration +// +void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6BurstConfig - DMA Channel 6 burst size configuration +// +void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH6TransferConfig - DMA channel 6 transfer size configuration +// +void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH6WrapConfig - DMA Channel 6 wrap size configuration +// +void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH6ModeConfig - DMA Channel 6 mode configuration +// +void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; + DmaRegs.CH6.MODE.bit.PERINTSEL = 6; + DmaRegs.CH6.MODE.bit.PERINTE = perinte; + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH6.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH6 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; + + EDIS; +} + +// +// StartDMACH6 - This function starts DMA Channel 6. +// +void StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// NOTE: +// Following functions are required for EMIF as the address is out of +// 22bit range +// + +// +// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit +// +void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit +// +void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit +// +void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit +// +void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit +// +void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit +// +void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c new file mode 100644 index 0000000000..d9dcfab62e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c @@ -0,0 +1,147 @@ +//########################################################################### +// +// FILE: F2837xD_ECap.c +// +// TITLE: F2837xD eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitECap - This function initializes the eCAP(s) to a known state. +// +void InitECap(void) +{ + // Initialize eCAP1/2/3/4/5/6 + + //tbd... +} + +// +// InitECapGpio - This function initializes GPIO pins to function as ECAP pins +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins +// come up as GPIO inputs after reset. +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. +// +void InitECapGpio() +{ +} + +// +// InitECap1Gpio - Initialize ECAP1 GPIOs +// +void InitECap1Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT7SELECT = pin; // Set eCAP1 source to GPIO-pin + EDIS; +} + +// +// InitECap2Gpio - Initialize ECAP2 GPIOs +// +void InitECap2Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT8SELECT = pin; // Set eCAP2 source to GPIO-pin + EDIS; +} + +// +// InitECap3Gpio - Initialize ECAP3 GPIOs +// +void InitECap3Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT9SELECT = pin; // Set eCAP3 source to GPIO-pin + EDIS; +} + +// +// InitECap4Gpio - Initialize ECAP4 GPIOs +// +void InitECap4Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT10SELECT = pin; // Set eCAP4 source to GPIO-pin + EDIS; +} + +// +// InitECap5Gpio - Initialize ECAP5 GPIOs +// +void InitECap5Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT11SELECT = pin; // Set eCAP5 source to GPIO-pin + EDIS; +} + +// +// InitECap6Gpio - Initialize ECAP6 GPIOs +// +void InitECap6Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT12SELECT = pin; // Set eCAP6 source to GPIO-pin + EDIS; +} + +// +// InitAPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitAPwm1Gpio() +{ + EALLOW; + OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 3; // Select ECAP1.OUT on Mux0 + OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1; // Enable MUX0 for ECAP1.OUT + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Select OUTPUTXBAR3 on GPIO5 + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c new file mode 100644 index 0000000000..2581fe46c9 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c @@ -0,0 +1,436 @@ +//########################################################################### +// +// FILE: F2837xD_EPwm.c +// +// TITLE: F2837xD EPwm Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitEPwmGpio - Initialize all EPWM modules' GPIOs +// +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + InitEPwm5Gpio(); + InitEPwm6Gpio(); + InitEPwm7Gpio(); + InitEPwm8Gpio(); + InitEPwm9Gpio(); + InitEPwm10Gpio(); + InitEPwm11Gpio(); + InitEPwm12Gpio(); +} + +// +// InitEPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B) + // GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A) + // GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B) + + // + // Configure EPWM-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM1 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + // GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A + // GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - Initialize EPWM2 GPIOs +// +void InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B) + // GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A) + // GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B) + + // + // Configure EPwm-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + // GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A + // GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B + + EDIS; +} + +// +// InitEPwm3Gpio - Initialize EPWM3 GPIOs +// +void InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B) + // GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A) + // GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B) + + // + // Configure EPwm-3 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM3 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + // GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A + // GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B + + EDIS; +} + +// +// InitEPwm4Gpio - Initialize EPWM4 GPIOs +// +void InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B) + // GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A) + // GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B) + + // + // Configure EPWM-4 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM4 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + // GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A + // GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B + + EDIS; +} + +// +// InitEPwm5Gpio - Initialize EPWM5 GPIOs +// +void InitEPwm5Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B) + // GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A) + // GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B) + + // + // Configure EPWM-5 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM5 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + // GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A + // GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B + + EDIS; +} + +// +// InitEPwm6Gpio - Initialize EPWM6 GPIOs +// +void InitEPwm6Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B) + // GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A) + // GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + // GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A + // GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B + + EDIS; +} + +// +// InitEPwm7Gpio - Initialize EPWM7 GPIOs +// +void InitEPwm7Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B) + // GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A) + // GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B + // GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A + // GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B + + EDIS; +} + +// +// InitEPwm8Gpio - Initialize EPWM8 GPIOs +// +void InitEPwm8Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B) +// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A) +// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B + // GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A + // GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B + + EDIS; +} + +// +// InitEPwm9Gpio - Initialize EPWM9 GPIOs +// +void InitEPwm9Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A) + GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A + GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B + + EDIS; +} + +// +// InitEPwm10Gpio - Initialize EPWM10 GPIOs +// +void InitEPwm10Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A) + GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A + GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B + + EDIS; +} + +// +// InitEPwm11Gpio - Initialize EPWM11 GPIOs +// +void InitEPwm11Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A) + GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A + GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B + + EDIS; +} + +// +// InitEPwm12Gpio - Initialize EPWM12 GPIOs +// +void InitEPwm12Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A) + GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A + GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B + + EDIS; +} diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c new file mode 100644 index 0000000000..90629e6f40 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c @@ -0,0 +1,389 @@ +//########################################################################### +// +// FILE: F2837xD_EQep.c +// +// TITLE: F2837xD eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitEQep - This function initializes the eQEP(s) to a known state. +// +void InitEQep(void) +{ + // Initialize eQEP1 + + //tbd... +} + +// +// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins +// come up as GPIO inputs after reset. +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void InitEQepGpio() +{ + InitEQep1Gpio(); + InitEQep2Gpio(); + InitEQep3Gpio(); +} + +// +// InitEQep1Gpio - Initialize EQEP-1 GPIOs +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void InitEQep1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EQEP1A) +// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EQEP1B) +// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EQEP1S) +// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EQEP1I) + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 1; // Disable pull-up on GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 1; // Disable pull-up on GPIO53 (EQEP1I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO96 = 1; // Disable pull-up on GPIO96 (EQEP1A) +// GpioCtrlRegs.GPDPUD.bit.GPIO97 = 1; // Disable pull-up on GPIO97 (EQEP1B) +// GpioCtrlRegs.GPDPUD.bit.GPIO98 = 1; // Disable pull-up on GPIO98 (EQEP1S) +// GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1; // Disable pull-up on GPIO99 (EQEP1I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0; // Sync GPIO10 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Sync GPIO11 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Sync GPIO12 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Sync GPIO13 to SYSCLK (EQEP1I) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync GPIO20 to SYSCLK (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync GPIO21 to SYSCLK (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync GPIO22 to SYSCLK (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync GPIO23 to SYSCLK (EQEP1I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync GPIO50 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync GPIO51 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync GPIO52 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync GPIO53 to SYSCLK (EQEP1I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO96 = 0; // Sync GPIO96 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO97 = 0; // Sync GPIO97 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO98 = 0; // Sync GPIO98 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO99 = 0; // Sync GPIO99 to SYSCLK (EQEP1I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP1 functional + // pins. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A +// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A +// GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B +// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B +// GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S +// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S +// GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I +// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + +// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A +// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B +// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S +// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A +// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B +// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S +// GpioCtrlRegs.GPDMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I +// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I + + EDIS; +} + +// +// InitEQep2Gpio - Initialize EQEP-2 GPIOs +// +void InitEQep2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2S) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 1; // Disable pull-up on GPIO54 (EQEP2A) +// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 1; // Disable pull-up on GPIO55 (EQEP2B) +// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 1; // Disable pull-up on GPIO56 (EQEP2S) +// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 1; // Disable pull-up on GPIO57 (EQEP2I) + +// GpioCtrlRegs.GPCPUD.bit.GPIO78 = 1; // Disable pull-up on GPIO78 (EQEP2A) +// GpioCtrlRegs.GPCPUD.bit.GPIO79 = 1; // Disable pull-up on GPIO79 (EQEP2B) +// GpioCtrlRegs.GPCPUD.bit.GPIO80 = 1; // Disable pull-up on GPIO80 (EQEP2S) +// GpioCtrlRegs.GPCPUD.bit.GPIO81 = 1; // Disable pull-up on GPIO81 (EQEP2I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 1; // Disable pull-up on GPIO100 (EQEP2A) +// GpioCtrlRegs.GPDPUD.bit.GPIO101 = 1; // Disable pull-up on GPIO101 (EQEP2B) +// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 1; // Disable pull-up on GPIO102 (EQEP2S) +// GpioCtrlRegs.GPDPUD.bit.GPIO103 = 1; // Disable pull-up on GPIO103 (EQEP2I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync GPIO24 to SYSCLK (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync GPIO25 to SYSCLK (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync GPIO26 to SYSCLK (EQEP2S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync GPIO27 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Sync GPIO54 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 0; // Sync GPIO55 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Sync GPIO56 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Sync GPIO57 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPCQSEL1.bit.GPIO78 = 0; // Sync GPIO78 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO79 = 0; // Sync GPIO79 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPCQSEL2.bit.GPIO80 = 0; // Sync GPIO80 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPCQSEL2.bit.GPIO81 = 0; // Sync GPIO81 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 0; // Sync GPIO100 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO101 = 0; // Sync GPIO101 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 0; // Sync GPIO102 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO103 = 0; // Sync GPIO103 to SYSCLK (EQEP2I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I + +// GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A +// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A +// GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B +// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B +// GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S +// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S +// GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I +// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I + +// GpioCtrlRegs.GPCGMUX1.bit.GPIO78 = 1; // Configure GPIO78 as EQEP2A +// GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // Configure GPIO78 as EQEP2A +// GpioCtrlRegs.GPCGMUX1.bit.GPIO79 = 1; // Configure GPIO79 as EQEP2B +// GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // Configure GPIO79 as EQEP2B +// GpioCtrlRegs.GPCGMUX2.bit.GPIO80 = 1; // Configure GPIO80 as EQEP2S +// GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // Configure GPIO80 as EQEP2S +// GpioCtrlRegs.GPCGMUX2.bit.GPIO81 = 1; // Configure GPIO81 as EQEP2I +// GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // Configure GPIO81 as EQEP2I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A +// GpioCtrlRegs.GPDMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B +// GpioCtrlRegs.GPDMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S +// GpioCtrlRegs.GPDMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I +// GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I + + EDIS; +} + +// +// InitEQep3Gpio - Initialize EQEP-3 GPIOs +// +void InitEQep3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EQEP3A) +// GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EQEP3B) +// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EQEP3S) +// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EQEP3I) + + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EQEP3A) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EQEP3B) + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO30 (EQEP3S) + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO31 (EQEP3I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1; // Disable pull-up on GPIO62 (EQEP3A) +// GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1; // Disable pull-up on GPIO63 (EQEP3B) +// GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1; // Disable pull-up on GPIO64 (EQEP3S) +// GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1; // Disable pull-up on GPIO65 (EQEP3I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO104 = 1; // Disable pull-up on GPIO104 (EQEP3A) +// GpioCtrlRegs.GPDPUD.bit.GPIO105 = 1; // Disable pull-up on GPIO105 (EQEP3B) +// GpioCtrlRegs.GPDPUD.bit.GPIO106 = 1; // Disable pull-up on GPIO106 (EQEP3S) +// GpioCtrlRegs.GPDPUD.bit.GPIO107 = 1; // Disable pull-up on GPIO107 (EQEP3I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Sync GPIO6 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Sync GPIO7 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Sync GPIO8 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Sync GPIO9 to SYSCLK (EQEP3I) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Sync GPIO28 to SYSCLK (EQEP3A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0; // Sync GPIO29 to SYSCLK (EQEP3B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0; // Sync GPIO30 to SYSCLK (EQEP3S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0; // Sync GPIO31 to SYSCLK (EQEP3I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 0; // Sync GPIO62 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Sync GPIO63 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 0; // Sync GPIO64 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO65 = 0; // Sync GPIO65 to SYSCLK (EQEP3I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO104 = 0; // Sync GPIO104 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO105 = 0; // Sync GPIO105 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO106 = 0; // Sync GPIO106 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO107 = 0; // Sync GPIO107 to SYSCLK (EQEP3I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP3 functional pins. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A +// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A +// GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B +// GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B +// GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S +// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S +// GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I +// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I + + GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A + GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 1; // Configure GPIO29 as EQEP3B + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 2; // Configure GPIO29 as EQEP3B + GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 1; // Configure GPIO30 as EQEP3S + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 2; // Configure GPIO30 as EQEP3S + GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 1; // Configure GPIO31 as EQEP3I + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // Configure GPIO31 as EQEP3I + +// GpioCtrlRegs.GPBGMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A +// GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A +// GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B +// GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B +// GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S +// GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S +// GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I +// GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A +// GpioCtrlRegs.GPDMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B +// GpioCtrlRegs.GPDMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S +// GpioCtrlRegs.GPDMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I +// GpioCtrlRegs.GPDMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I + + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c new file mode 100644 index 0000000000..0f8ff9d52b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c @@ -0,0 +1,458 @@ +//########################################################################### +// +// FILE: F2837xD_Emif.c +// +// TITLE: F2837xD EMIF Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Emif1Initialize - This function initializes the EMIF1 to a known state. +// +void Emif1Initialize(void) +{ + EALLOW; + // + // Perform a Module soft reset on EMIF + // +#ifdef CPU1 + DevCfgRegs.SOFTPRES1.all = 0x1; + __asm (" nop"); + DevCfgRegs.SOFTPRES1.all = 0x0; +#endif + EDIS; +} + +// +// Emif2Initialize - This function initializes the EMIF2 to a known state. +// +void Emif2Initialize(void) +{ + EALLOW; + // + // Perform a Module soft reset on EMIF + // +#ifdef CPU1 + DevCfgRegs.SOFTPRES1.all = 0x2; + __asm (" nop"); + DevCfgRegs.SOFTPRES1.all = 0x0; +#endif + EDIS; +} + +// +// ASync_wait_config - Async wait configuration function +// +void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity) +{ + if (inst == 0) + { + // + // 7:0 Maximum Extended Wait cycles. + // + Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; + + // + // 28 Wait Polarity for pad_wait_i[0]. + // + Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; + } + else + { + // + // 7:0 Maximum Extended Wait cycles. + // + Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; + + // + // 28 Wait Polarity for pad_wait_i[0]. + // + Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; + } +} + +// +// ASync_cs2_config - Async CS2 Configuration +// +void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + if (inst == 0) + { + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; + } + else + { + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; + Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; + Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; + Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; + Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; + Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait; + Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; + } +} + +// +// ASync_cs3_config - Async CS3 Configuration +// +void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel; +} + +// +// ASync_cs4_config - Async CS4 Configuration +// +void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel; +} + +#ifdef CPU1 +// +// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup +// +void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=28; i<=52; i++) + { + if ((i != 42) && (i != 43)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + for (i=63; i<=87; i++) + { + if (i != 84) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + GPIO_SetupPinMux(88,cpu_sel,3); + GPIO_SetupPinMux(89,cpu_sel,3); + GPIO_SetupPinMux(90,cpu_sel,3); + GPIO_SetupPinMux(91,cpu_sel,3); + GPIO_SetupPinMux(92,cpu_sel,3); + GPIO_SetupPinMux(93,cpu_sel,3); + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //setup async mode and enable pull-ups for Data pins + // + for (i=69; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP + } + } +} + +// +// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async +// +void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=28; i<=87; i++) + { + if ((i != 42) && (i != 43) && (i != 84)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + GPIO_SetupPinMux(88,cpu_sel,3); + GPIO_SetupPinMux(89,cpu_sel,3); + GPIO_SetupPinMux(90,cpu_sel,3); + GPIO_SetupPinMux(91,cpu_sel,3); + GPIO_SetupPinMux(92,cpu_sel,3); + GPIO_SetupPinMux(93,cpu_sel,3); + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //setup async mode for Data pins + // + for (i=53; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } +} + +// +// setup_emif2_pinmux_async_16bit - function for EMIF1 GPIO pin setup +// +void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=96; i<=121; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + for (i=53; i<=68; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //setup async mode for Data pins + // + for (i=53; i<=68; i++) + { + GPIO_SetupPinOptions(i,0,0x31); + } +} + +// +// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM +// +void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel) +{ + int i; + + for (i=29; i<=52; i++) + { + if ((i != 42) && (i != 43)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for (i=69; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for(i=86; i<=93; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //configure Data pins for Async mode + // + for (i = 69; i <= 85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } + + GPIO_SetupPinOptions(88,0,0x31); + GPIO_SetupPinOptions(89,0,0x31); + GPIO_SetupPinOptions(90,0,0x31); + GPIO_SetupPinOptions(91,0,0x31); +} + +// +// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM +// +void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel) +{ + int i; + + for (i=53; i<=68; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + for (i=96; i<=121; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //configure Data pins for Async mode + // + for (i = 53; i <= 68; i++) + { + GPIO_SetupPinOptions(i,0,0x31); + } +} + +// +// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM +// +void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel) +{ + int i; + + for (i=28; i<=85; i++) + { + if ((i != 42) && (i != 43) && (i != 84)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for(i=86; i<=93; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //configure Data pins for Async mode + // + for (i = 53; i <= 85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } + + GPIO_SetupPinOptions(88,0,0x31); + GPIO_SetupPinOptions(89,0,0x31); + GPIO_SetupPinOptions(90,0,0x31); + GPIO_SetupPinOptions(91,0,0x31); + } + +#endif // CPU1 + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c new file mode 100644 index 0000000000..0c5927b5ed --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c @@ -0,0 +1,506 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio.c +// +// TITLE: GPIO module support functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//Low-level functions for GPIO configuration (CPU1 only) +// + +#ifdef CPU1 + // + // InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups + // enabled. Also resets CPU control to CPU1 and disables open + // drain and polarity inversion and sets the qualification to + // synchronous. Also unlocks all GPIOs. Only one CPU should call + // this function. + // + void InitGpio() + { + volatile Uint32 *gpioBaseAddr; + Uint16 regOffset; + + // + //Disable pin locks + // + EALLOW; + GpioCtrlRegs.GPALOCK.all = 0x00000000; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; + GpioCtrlRegs.GPDLOCK.all = 0x00000000; + GpioCtrlRegs.GPELOCK.all = 0x00000000; + GpioCtrlRegs.GPFLOCK.all = 0x00000000; + + // + // Fill all registers with zeros. Writing to each register separately + // for six GPIO modules would make this function *very* long. + // Fortunately, we'd be writing them all with zeros anyway, so this + // saves a lot of space. + // + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; + for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) + { + // + //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset + //0x0C in each register group of 0x40 words. Since this is a + //32-bit pointer, the addresses must be divided by 2. + // + if (regOffset % (0x40/2) != (0x0C/2)) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + } + + gpioBaseAddr = (Uint32 *)&GpioDataRegs; + for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + + EDIS; + } + + // + // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The + // appropriate parameters can be found in the GPIO Muxed + // Pins table(4.4) in the datasheet. Use the GPIO index + // row (0 to 15) to select a muxing option for the GPIO. + // + void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *mux, *gmux, *csel; + Uint16 pin32, pin16, pin8; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pin8 = gpioNumber % 8; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Sanity check for valid cpu and peripheral values + // + if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) + return; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyCSEL1-4. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + mux = gpioBaseAddr + GPYMUX + pin32/16; + gmux = gpioBaseAddr + GPYGMUX + pin32/16; + csel = gpioBaseAddr + GPYCSEL + pin32/8; + + // + //Now for the actual function + // + EALLOW; + + // + //To change the muxing, set the peripheral mux to 0/GPIO first to avoid + //glitches, then change the group mux, then set the peripheral mux to + //its target value. Finally, set the CPU select. This procedure is + //described in the TRM. Unfortunately, since we don't know the pin in + //advance we can't hardcode a bitfield reference, so there's some + //tricky bit twiddling here. + // + *mux &= ~(0x3UL << (2*pin16)); + *gmux &= ~(0x3UL << (2*pin16)); + *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); + *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); + + *csel &= ~(0x3L << (4*pin8)); + *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); + + // + //WARNING: This code does not touch the analog mode select registers, + //which are needed to give the USB module control of its IOs. + // + EDIS; + } + + // + // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the + // specified pin. + // + //The flags are a 16-bit mask produced by ORing together options. + //For input pins, the valid flags are: + //GPIO_PULLUP Enable pull-up + //GPIO_INVERT Enable input polarity inversion + //GPIO_SYNC Synchronize the input latch to PLLSYSCLK + // (default -- you don't need to specify this) + //GPIO_QUAL3 Use 3-sample qualification + //GPIO_QUAL6 Use 6-sample qualification + //GPIO_ASYNC Do not use synchronization or qualification + //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) + // + //For output pins, the valid flags are: + //GPIO_OPENDRAIN Output in open drain mode + //GPIO_PULLUP If open drain enabled, also enable the pull-up + //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. + // + //With no flags, the default input state is synchronous with no + //pull-up or polarity inversion. The default output state is + //the standard digital output. + // + void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *inv, *odr, *qsel; + Uint32 pin32, pin16, pinMask, qual; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + inv = gpioBaseAddr + GPYINV; + odr = gpioBaseAddr + GPYODR; + qsel = gpioBaseAddr + GPYQSEL + pin32/16; + + EALLOW; + + // + //Set the data direction + // + *dir &= ~pinMask; + if (output == 1) + { + // + //Output, with optional open drain mode and pull-up + // + *dir |= pinMask; + + // + //Enable open drain if necessary + // + if (flags & GPIO_OPENDRAIN) + { + *odr |= pinMask; + } + else + { + *odr &= ~pinMask; + } + + // + //Enable pull-up if necessary. Open drain mode must be active. + // + if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + } + else + { + // + //Input, with optional pull-up, qualification, and polarity + //inversion + // + *dir &= ~pinMask; + + // + //Enable pull-up if necessary + // + if (flags & GPIO_PULLUP) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + + // + //Invert polarity if necessary + // + if (flags & GPIO_INVERT) + { + *inv |= pinMask; + } + else + { + *inv &= ~pinMask; + } + } + + // + //Extract the qualification parameter and load it into the register. + //This is also needed for open drain outputs, so we might as well do it + //all the time. + // + qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; + *qsel &= ~(0x3L << (2 * pin16)); + if (qual != 0x0) + { + *qsel |= qual << (2 * pin16); + } + + EDIS; + } + + // + // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the + // specified pin. + // The valid flags are: + // GPIO_UNLOCK - Unlock the pin setup register bits for + // the specified pin + // GPIO_LOCK - Lock the pin setup register bits for the + // specified pin + // + void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *lock; + Uint32 pin32, pinMask; + + pin32 = gpioNumber % 32; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + lock = gpioBaseAddr + GPYLOCK; + + EALLOW; + if(flags) + { + //Lock the pin + *lock |= pinMask; + } + else + { + //Unlock the pin + *lock &= ~pinMask; + } + EDIS; + } + + // + //External interrupt setup + // + void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin + EDIS; + } + + // + //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded + // GPIOs on the 176PTP package: + // GPIOs Grp Bits + // 95-132 C 31 + // D 31:0 + // E 4:0 + // 134-168 E 31:6 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor176Pin() + { + EALLOW; + GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded + // GPIOs on the 100PZ package: + // GPIOs Grp Bits + // 0-1 A 1:0 + // 5-9 A 9:5 + // 22-40 A 31:22 + // B 8:0 + // 44-57 B 25:12 + // 67-68 C 4:3 + // 74-77 C 13:10 + // 79-83 C 19:15 + // 93-168 C 31:29 + // D 31:0 + // E 31:0 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor100Pin() + { + EALLOW; + GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31 + GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57 + GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function + // this takes care of enabling IO pullups. + // + void GPIO_EnableUnbondedIOPullups() + { + // + //bits 8-10 have pin count + // + unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ; + + // + //5 = 100 pin + //6 = 176 pin + //7 = 337 pin + // + if(pin_count == 5) + { + GPIO_EnableUnbondedIOPullupsFor100Pin(); + } + else if (pin_count == 6) + { + GPIO_EnableUnbondedIOPullupsFor176Pin(); + } + else + { + //do nothing - this is 337 pin package + } + } + +#endif //CPU1 + +// +// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that +// this returns the actual state of the pin, not the state of +// the output latch. +// +Uint16 GPIO_ReadPin(Uint16 gpioNumber) +{ + volatile Uint32 *gpioDataReg; + Uint16 pinVal; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; + + return pinVal; +} + +// +// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. +// +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinMask = 1UL << (gpioNumber % 32); + + if (outVal == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c new file mode 100644 index 0000000000..d17266a9b0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c @@ -0,0 +1,301 @@ +//########################################################################### +// +// FILE: F2837xD_I2C.c +// +// TITLE: F2837xD I2C Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//--------------------------------------------------------------------------- +// Example: I2cAGpioConfig(), I2cBGpioConfig() +//--------------------------------------------------------------------------- +// These functions configures GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +#ifdef CPU1 +// +// I2cAGpioConfig - Configure I2CA GPIOs +// 'I2caDataClkPin' should be assign with one of the +// possible I2C_A SDA - SDL GPIO pin Use defined Macros from +// "F2837xD_I2c_defines.h" for assignment +// +void I2cAGpioConfig(Uint16 I2caDataClkPin) +{ + EALLOW; + + switch(I2caDataClkPin) + { + case I2C_A_GPIO0_GPIO1: + + // + // Enable internal pull-up for the selected I2C pins + // Enable pull-up for GPIO0 (SDAA) + // Enable pull-up for GPIO1 (SDLA) + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; + + // + // Set qualification for the selected I2C pins + // Async/no qualification (I/ps sync to SYSCLKOUT by default) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3; + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // Configure GPIO0 for SDAA operation + // Configure GPIO0 for SDAA operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 2; + + // + // Configure GPIO1 for SDLA operation + // Configure GPIO1 for SDLA operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; + + break; + + case I2C_A_GPIO32_GPIO33: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; + + break; + + case I2C_A_GPIO42_GPIO43: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + break; + + case I2C_A_GPIO91_GPIO92: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0; + GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0; + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPCQSEL2.bit.GPIO91 = 3; + GpioCtrlRegs.GPCQSEL2.bit.GPIO92 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + GpioCtrlRegs.GPCGMUX2.bit.GPIO91 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO91 = 2; + GpioCtrlRegs.GPCGMUX2.bit.GPIO92 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO92 = 2; + break; + + case I2C_A_GPIO63104_GPIO105: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + break; + + default: + + break; + + } // End of Switch + EDIS; +} + +// +// I2cBGpioConfig - Configure I2CB GPIOs +// 'I2cbDataClkPin' should be assign with one of the possible +// I2C_B SDA - SDL GPIO pin Use defined Macros from +// "F2837xD_I2c_defines.h" for assignment +// +void I2cBGpioConfig(Uint16 I2cbDataClkPin) +{ + EALLOW; + + switch(I2cbDataClkPin) + { + case I2C_B_GPIO2_GPIO3: + // + // Enable internal pull-up for the selected I2C pins + // Enable pull-up for GPIO2 (SDAB) + // Enable pull-up for GPIO3 (SDLB) + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; + + // + // Set qualification for the selected I2C pins + // Async/no qualification (I/ps sync to SYSCLKOUT by default) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 3; + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // Configure GPIO2 for SDAB operation + // Configure GPIO3 for SDAB operation + // Configure GPIO1 for SDLB operation + // Configure GPIO1 for SDLB operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2; + + GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; + + break; + + case I2C_B_GPIO134_GPIO35: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + break; + + case I2C_B_GPIO40_GPIO41: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + break; + + case I2C_B_GPIO66_GPIO69: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; //SDAB + GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; //SCLB + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO66 = 3; + GpioCtrlRegs.GPCQSEL1.bit.GPIO69 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO66 = 1; //0x6 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2; + + GpioCtrlRegs.GPCGMUX1.bit.GPIO69 = 1; //0x6 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2; + break; + + default: + break; + + } + EDIS; +} + +#endif + + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c new file mode 100644 index 0000000000..a58533c200 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c @@ -0,0 +1,216 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc.c +// +// TITLE: Inter-Processor Communication module support functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include + +// +// InitIpc - Initialize all IPC registers and clear all flags +// +void InitIpc() +{ + // + //Clear sent flags. Received flags must not be cleared locally + //to handle the case where the remote CPU starts executing first. + //In this case, a remote flag could be sent correctly and be + //incorrectly cleared by this function. Unfortunately, we're + //still left with a startup synchronization problem if the + //remote CPU has flags left over from a previous run. There's + //probably a better way of handling this. + // + IpcRegs.IPCCLR.all = 0xFFFFFFFF; + + // + //Clear commands + // + IpcRegs.IPCSENDCOM = 0; + IpcRegs.IPCSENDADDR = 0; + IpcRegs.IPCSENDDATA = 0; + IpcRegs.IPCLOCALREPLY = 0; + + // + //Clear boot status and pump semaphore + // + #if defined(CPU1) + IpcRegs.IPCBOOTMODE = 0; + #elif defined(CPU2) + IpcRegs.IPCBOOTSTS = 0; + #endif + ReleaseFlashPump(); +} + +// +// ReadIpcTimer - Read the current IPC timer value. The low register must be +// read first to latch a value in the high register. +// +unsigned long long ReadIpcTimer() +{ + Uint32 low, high; + + low = IpcRegs.IPCCOUNTERL; + high = IpcRegs.IPCCOUNTERH; + return ((unsigned long long)high << 32) | (unsigned long long)low; +} + +// +// SendIpcData - Copy data into the IPC send message RAM for this CPU and set +// a flag. If the specified 16-bit word length is greater than +// the size of the message RAM, the data is truncated. +// +void SendIpcData(void *data, Uint16 word_length, Uint16 flag) +{ + word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; + + memcpy(SEND_MSG_RAM, data, word_length); + + if (flag != NO_IPC_FLAG) + { + SendIpcFlag(flag); + } +} + +// +// RecvIpcData - Copy data out of the IPC receive message RAM for this CPU. If +// the specified 16-bit word length is greater than the size of +// the message RAM, the data is truncated. +// +void RecvIpcData(void *recv_buf, Uint16 word_length) +{ + word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; + memcpy(recv_buf, RECV_MSG_RAM, word_length); +} + +// +// FillIpcSendData - Fill the IPC send message RAM for this CPU with a constant +// value +// +void FillIpcSendData(Uint16 fill_data) +{ + memset(SEND_MSG_RAM, fill_data, MSG_RAM_SIZE); +} + +// +// SendIpcCommand - Write the send command, address, and data registers with +// the specified values, then set an IPC flag. +// +void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag) +{ + IpcRegs.IPCSENDCOM = command; + IpcRegs.IPCSENDADDR = address; + IpcRegs.IPCSENDDATA = data; + + if (flag != NO_IPC_FLAG) + { + SendIpcFlag(flag); + } +} + +// +// SendIpcFlag - Set an IPC flag bit for the other CPU. Flags 0-3 will generate +// PIE interrupts. +// +void SendIpcFlag(Uint16 flag) +{ + IpcRegs.IPCSET.all = 1UL << flag; +} + +// +// AckIpcFlag - Acknowledge/clear a received IPC flag +// +void AckIpcFlag(Uint16 flag) +{ + IpcRegs.IPCACK.all = 1UL << flag; +} + +// +// CancelIpcFlag - Clear a sent IPC flag bit before the other CPU acknowledges +// it. You will normally never use this function. To clear a +// received flag, call AckIpcFlag() instead. +// +void CancelIpcFlag(Uint16 flag) +{ + IpcRegs.IPCCLR.all = 1UL << flag; +} + +// +// WaitForIpcFlag - Wait for any IPC flag in the specified mask to be set. +// WARNING: If you use this function to wait for an IPC +// interrupt, you must not clear the IPC flag in the interrupt +// handler. Otherwise, this function will never return. +// +void WaitForIpcFlag(Uint16 flag) +{ + // + //WARNING: Don't use this function to wait for an IPC interrupt! + // + while ((IpcRegs.IPCSTS.all & (1UL << flag)) == 0x00000000) {;} +} + +// +// WaitForIpcAck - Wait for any IPC flag in the specified mask to be +// acknowledged. +// +void WaitForIpcAck(Uint16 flag) +{ + while ((IpcRegs.IPCFLG.all & (1UL << flag)) != 0x00000000) {;} +} + +// +// IpcSync - Synchronize the two CPUs. Neither CPU will return from this +// function call before the other one enters it. Must be called with +// the same flag number on both CPUs. +// +void IpcSync(Uint16 flag) +{ + SendIpcFlag(flag); + WaitForIpcFlag(flag); + AckIpcFlag(flag); + WaitForIpcAck(flag); +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c new file mode 100644 index 0000000000..9b38efc7b5 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c @@ -0,0 +1,1702 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Functions. +// +// DESCRIPTION: +// 28x API functions for inter-processor communications between the +// two CPUs. The IPC functions require the usage of the CPU1 to CPU2 +// and CPU2 to CPU1 MSG RAM's to store the circular ring +// buffer and indexes. Commands can be queued up in order on a single +// IPC interrupt channel. For those IPC commands which are not +// interdependent, multiple IPC interrupt channels may be used. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// Cores use this code. +// The active debug CPU will be referred to as Local CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup ipc_driver_api +//! @{ +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_Ipc_drivers.h" + +#if defined(CPU1) +#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "PUTBUFFER"); +#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); +#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); + +#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "GETBUFFER"); +#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); +#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); + +#elif defined(CPU2) + +#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "PUTBUFFER"); +#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); +#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); + +#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "GETBUFFER"); +#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); +#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); + +#endif + +// +// Global Circular Buffer Definitions +// +tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; +tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; + +// +// Global Circular Buffer Index Definitions +// +uint16_t g_usPutWriteIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usPutReadIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usGetWriteIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usGetReadIndexes[NUM_IPC_INTERRUPTS]; + +//***************************************************************************** +// +//! Initializes System IPC driver controller +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param usCPU2IpcInterrupt specifies the CPU2 IPC interrupt number used by +//! psController. +//! \param usCPU1IpcInterrupt specifies the CPU1 IPC interrupt number used by +//! psController. +//! +//! This function initializes the IPC driver controller with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e usCPU2IpcInterrupt and \e usCPU1IpcInterrupt parameters can be one of +//! the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e tIpcController instance, +//! that particular interrupt should not be tied to a second \e tIpcController +//! instance. +//! +//! \note For a particular usCPU2IpcInterrupt - usCPU1IpcInterrupt pair, there +//! must be an instance of tIpcController defined and initialized on both the +//! CPU1 and CPU2 systems. +//! +//! \return None. +// +//***************************************************************************** +void +IPCInitialize (volatile tIpcController *psController, + uint16_t usCPU2IpcInterrupt, uint16_t usCPU1IpcInterrupt) +{ +#if defined(CPU1) + // CPU1toCPU2PutBuffer and Index Initialization + psController->psPutBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; + psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU2IpcInterrupt-1]; + psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU1IpcInterrupt-1]; + psController->ulPutFlag = (uint32_t)(1 << (usCPU2IpcInterrupt - 1)); + + // CPU1toCPU2GetBuffer and Index Initialization + psController->psGetBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; + psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU1IpcInterrupt-1]; + psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU2IpcInterrupt-1]; +#elif defined(CPU2) + // CPU2toCPU1PutBuffer and Index Initialization + psController->psPutBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; + psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU1IpcInterrupt-1]; + psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU2IpcInterrupt-1]; + psController->ulPutFlag = (uint32_t)(1 << (usCPU1IpcInterrupt - 1)); + + // CPU1toCPU2GetBuffer and Index Initialization + psController->psGetBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; + psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU2IpcInterrupt-1]; + psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU1IpcInterrupt-1]; +#endif + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + *(psController->pusPutWriteIndex) = 0; + *(psController->pusGetReadIndex) = 0; +} + +//***************************************************************************** +// +//! Writes a message into the PutBuffer. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the address of the \e tIpcMessage instance to be +//! written to PutBuffer. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a free slot (1= wait until free spot available, 0 = exit with +//! STATUS_FAIL if no free slot). +//! +//! This function checks if there is a free slot in the PutBuffer. If so, it +//! puts the message pointed to by \e psMessage into the free slot and +//! increments the WriteIndex. Then it sets the appropriate IPC interrupt flag +//! specified by \e psController->usPutFlag. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return \b STATUS_FAIL if PutBuffer is full. \b STATUS_PASS if Put occurs +//! successfully. +// +//***************************************************************************** +uint16_t +IpcPut (volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + uint16_t writeIndex; + uint16_t readIndex; + uint16_t returnStatus = STATUS_PASS; + + writeIndex = *(psController->pusPutWriteIndex); + readIndex = *(psController->pusPutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while (((writeIndex + 1) & MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if (!bBlock) + { + returnStatus = STATUS_FAIL; + break; + } + + readIndex = *(psController->pusPutReadIndex); + } + + if (returnStatus != STATUS_FAIL) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + psController->psPutBuffer[writeIndex] = *psMessage; + + writeIndex = (writeIndex + 1) & MAX_BUFFER_INDEX; + *(psController->pusPutWriteIndex) = writeIndex; + + IpcRegs.IPCSET.all |= psController->ulPutFlag; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Reads a message from the GetBuffer. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the address of the \e tIpcMessage instance where +//! the message from GetBuffer should be written to. +//! \param bBlock specifies whether to allow function to block until GetBuffer +//! has a message (1= wait until message available, 0 = exit with STATUS_FAIL +//! if no message). +//! +//! This function checks if there is a message in the GetBuffer. If so, it gets +//! the message in the GetBuffer pointed to by the ReadIndex and writes it to +//! the address pointed to by \e psMessage. The \e bBlock parameter can be one +//! of the following +//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return \b STATUS_PASS if GetBuffer is empty. \b STATUS_FAIL if Get occurs +//! successfully. +// +//***************************************************************************** +uint16_t +IpcGet (volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + uint16_t writeIndex; + uint16_t readIndex; + uint16_t returnStatus = STATUS_PASS; + + writeIndex = *(psController->pusGetWriteIndex); + readIndex = *(psController->pusGetReadIndex); + + // + // Loop while GetBuffer is empty + // + while (writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if (!bBlock) + { + returnStatus = STATUS_FAIL; + break; + } + + writeIndex = *(psController->pusGetWriteIndex); + } + + if (returnStatus != STATUS_FAIL) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *psMessage = psController->psGetBuffer[readIndex]; + + readIndex = (readIndex + 1) & MAX_BUFFER_INDEX; + *(psController->pusGetReadIndex) = readIndex; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sends a command to read either a 16- or 32-bit data word from the remote +//! CPU +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to read from +//! \param pvData is a pointer to the 16/32-bit variable where read data will +//! be stored. +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the remote CPU to the local CPU Flag +//! number mask used to report when the read data is available at pvData. +//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) +//! +//! This function will allow the local CPU system to send a 16/32-bit data +//! read command to the remote CPU system and set a ResponseFlag to track the +//! status of the read. +//! The remote CPU will respond with a DataWrite command which will place +//! the data in the local CPU address pointed to by \e pvData. When the local +//! CPU receives the DataWrite command and writes the read data into \e *pvData location, +//! it will clear the ResponseFlag, indicating to the rest of the system that +//! the data is ready. The \e usLength parameter can be one of the +//! following values: \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e +//! bBlock parameter can be one of the following values: \b ENABLE_BLOCKING or +//! \b DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataRead (volatile tIpcController *psController, uint32_t ulAddress, + void *pvData, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + + uint16_t status; + tIpcMessage sMessage; + + // + // Set up read command, address, dataw1 = ResponseFlag | word length, + // dataw2 = address where word + // should be written to when returned. + // + sMessage.ulcommand = IPC_DATA_READ; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; + sMessage.uldataw2 = (uint32_t)pvData; + + // + // Set ResponseFlag (cleared once data is read into address at pvData) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + + // + //Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE + // sMessage.uladdress = (uint32_t) pvData + // sMessage.uldataw1 = ulStatusFlag | + // (uint32_t) usLength; + // sMessage.uldataw2 = word to be read into + // pvData address. + // +} + +//***************************************************************************** +// +//! Sends the command to read either a 16- or 32-bit data word from remote +//! CPU system address to a write-protected local CPU address. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to read from +//! \param pvData is a pointer to the 16/32-bit variable where read data will +//! be stored. +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number +//! mask used to report when the read data is available at pvData. +//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) +//! +//! This function will allow the local CPU system to send a 16/32-bit data +//! read command to the remote CPU system and set a ResponseFlag to track the +//! status of the read. +//! The remote CPU system will respond with a DataWrite command which will +//! place the data in the local CPU address pointed to by \e pvData. +//! When the local CPU receives the DataWrite command and writes the read data +//! into \e *pvData location, it will clear the ResponseFlag, indicating to +//! the rest of the system that the data is ready. The \e usLength parameter +//! can be one of the following values: \b IPC_LENGTH_16_BITS or +//! \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the following +//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataRead_Protected (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, uint16_t usLength, + uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up read command, address, dataw1 = ResponseFlag | word length, dataw2 + // = address where word should be written to when returned. + // + sMessage.ulcommand = IPC_DATA_READ_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; + sMessage.uldataw2 = (uint32_t)pvData; + + // + // Set ResponseFlag (cleared once data is read into address at pvData) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + // + // Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE + // sMessage.uladdress = (uint32_t) pvData + // sMessage.uldataw1 = ulStatusFlag | + // (uint32_t) usLength; + // sMessage.uldataw2 = word to be read into + // pvData address. + // +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit data word at the remote CPU system +//! address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! \e ulAddress. +//! 16-bit masks should fill the lower 16-bits (upper 16-bits will be all +//! 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e +//! usLength parameter can be one of the following values: \b IPC_LENGTH_16_BITS +//! or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSetBits(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up set bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_SET_BITS; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit write-protected data word at the +//! remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU +//! system. The \e usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: +//! \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSetBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up set bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_SET_BITS_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16-bit data word at the remote CPU system +//! address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to clear bits specified by +//! the \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e +//! usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRClearBits(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up clear bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_CLEAR_BITS; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16-bit write-protected data word at +//! remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the secondary CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU +//! system. The \e usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRClearBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up clear bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_CLEAR_BITS_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to the remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote cpu address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (1 = 16-bits, 2 = +//! 32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the +//! remote cpu only when this function is called in response to \e +//! IPCMtoCDataRead(). Otherwise, set to 0. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! via the \e ulData variable to an address on the remote CPU system. +//! The \e usLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataWrite(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up write command, address, dataw1 = ResponseFlag | word length, + // dataw2 = data to write + // + sMessage.ulcommand = IPC_DATA_WRITE; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; + sMessage.uldataw2 = ulData; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a write-protected remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the write-protected remote CPU address to +//! write to +//! \param ulData specifies the 16/32-bit word which will be written. For +//! 16-bit words, only the lower 16-bits of ulData will be considered by the +//! master system. +//! \param usLength is the length of the word to write (1 = 16-bits, 2 = +//! 32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the +//! remote CPU only when this function is called in response to \e +//! IPCMtoCDataRead(). Otherwise, set to 0. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! via the \e ulData variable to a write-protected address on the remote CPU +//! system. The \e usLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - +//! \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up write command, address, dataw1 = ResponseFlag | word length, + // dataw2 = data to write + // + sMessage.ulcommand = IPC_DATA_WRITE_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; + sMessage.uldataw2 = ulData; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Sends the command to read a block of data from remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU memory block starting address +//! to read from. +//! \param ulShareAddress specifies the local CPU shared memory address the +//! read block will read to. +//! \param usLength designates the block size in 16-bit words. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number +//! mask used to report when the read block data is available starting at +//! /e ulShareAddress. (\e ulResponseFlag MUST use IPC flags 17-32, and not +//! 1-16) +//! +//! This function will allow the local CPU system to send a read block +//! command to the remote CPU system and set a ResponseFlag to track the status +//! of the read. The remote CPU system will process the read and place the data +//! in shared memory at the location specified in the \e ulShareAddress +//! parameter and then clear the ResponseFlag, indicating that the block is +//! ready. The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e ulResponseFlag parameter can +//! be any single one of the flags \b IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockRead(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulShareAddress, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block read command, address, dataw1 = ResponseFlag | block length, + // dataw2 = remote CPU address in shared memory + // where block data should be read to + // (corresponding to local CPU ulShareAddress). + // + sMessage.ulcommand = IPC_BLOCK_READ; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000) |(uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Set ResponseFlag (cleared once data is read into Share Address location) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + // + // Note: Read Block Response will occur in processing of ReadBlock (since + // remote CPU has access to shared memory) + // +} + +//***************************************************************************** +// +//! Writes a block of data to remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU memory block starting address +//! to write to. +//! \param ulShareAddress specifies the local CPU shared memory address where +//! data to write from resides. +//! \param usLength designates the block size in 16- or 32-bit words (depends +//! on \e usWordLength). +//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to write a block of data to +//! the remote CPU system starting from the location specified by the +//! \e ulAdress parameter. Prior to calling this function, the local CPU +//! system code should place the data to write in shared memory starting at /e +//! ulShareAddress. +//! The \e usWordLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \note If the shared SARAM blocks are used to pass the RAM block between the +//! processors, the IPCReqMemAccess() function must be called first in order to +//! give the slave CPU write access to the shared memory block(s). +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockWrite(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulShareAddress, uint16_t usLength, + uint16_t usWordLength, uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block write command, address, dataw1 = block length, + // dataw2 = remote CPU shared mem address + // where write data resides + // + sMessage.ulcommand = IPC_BLOCK_WRITE; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a block of data to a write-protected remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the write-protected remote CPU block starting +//! address to write to. +//! \param ulShareAddress specifies the local CPU shared memory address where +//! data to write from resides. +//! \param usLength designates the block size in 16- or 32-bit words (depends +//! on \e usWordLength). +//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to write a block of data to +//! a write-protected region on the remote CPU system starting from the +//! location specified by the \e ulAdress parameter. Prior to calling this +//! function, the local CPU system code should place the data to write in +//! shared memory starting at /e ulShareAddress. +//! The \e usWordLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \note If the shared SARAM blocks are used to pass the RAM block between the +//! processors, the IPCReqMemAccess() function must be called first in order to +//! give the the slave CPU write access to the shared memory block(s). +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t usWordLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block write command, address, dataw1 = block length, + // dataw2 = remote CPU shared mem address + // where write data resides + // + sMessage.ulcommand = IPC_BLOCK_WRITE_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Calls remote CPU function with 1 optional parameter . +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU function address +//! \param ulParam specifies the 32-bit optional parameter value. If not used, +//! this can be a dummy value. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to call a function on the +//! remote CPU. The \e ulParam variable is a single optional 32-bit parameter +//! to pass to the function. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRFunctionCall(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulParam, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up function call command, address, dataw1 = 32-bit parameter + // + sMessage.ulcommand = IPC_FUNC_CALL; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulParam; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Sends generic message to remote CPU system +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulCommand specifies 32-bit command word to insert into message. +//! \param ulAddress specifies 32-bit address word to insert into message. +//! \param ulDataW1 specifies 1st 32-bit data word to insert into message. +//! \param ulDataW2 specifies 2nd 32-bit data word to insert into message. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to send a generic message to +//! the remote CPU system. Note that the user should create a corresponding +//! function on the remote CPU side to interpret/use the message or fill +//! parameters in such a way that the existing IPC drivers can recognize the +//! command and properly process the message. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSendMessage(volatile tIpcController *psController, uint32_t ulCommand, + uint32_t ulAddress, uint32_t ulDataW1, uint32_t ulDataW2, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Package message to send + // + sMessage.ulcommand = ulCommand; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulDataW1; + sMessage.uldataw2 = ulDataW2; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +#if defined (CPU2) +//***************************************************************************** +// +//! Slave CPU Configures master R/W/Exe Access to Shared SARAM. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulMask specifies the 32-bit mask for the GSxMSEL RAM control +//! register to indicate which GSx SARAM blocks the slave CPU is requesting +//! master access to. +//! \param usMaster specifies whether the CPU1 or CPU2 are given +//! master access to the GSx blocks. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the slave CPU system to configure master R/W/Exe +//! access to the GSx SARAM blocks specified by the /e ulMask parameter. The +//! function calls the \e IPCSetBits_Protected() or \e +//! IPCClearBits_Protected() functions, and therefore in the master CPU +//! application code, the corresponding functions should be called. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e usMaster parameter can be +//! either: \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulMask +//! parameter can be any of the options: \b S0_ACCESS - \b S7_ACCESS. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, + uint16_t usMaster, uint16_t bBlock) +{ + uint16_t status = STATUS_PASS; + uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); + + if (usMaster == IPC_GSX_CPU2_MASTER) + { + if ((MemCfgRegs.GSxMSEL.all & ulMask) != ulMask) + { + status = + IPCLtoRSetBits_Protected (psController, GSxMSEL_REGaddress, + ulMask, IPC_LENGTH_32_BITS, + bBlock); + } + } + else if (usMaster == IPC_GSX_CPU1_MASTER) + { + if ((MemCfgRegs.GSxMSEL.all & ulMask) != 0) + { + status = + IPCLtoRClearBits_Protected (psController, GSxMSEL_REGaddress, + ulMask, IPC_LENGTH_32_BITS, + bBlock); + } + } + + return status; +} +#endif + +//***************************************************************************** +// +//! Responds to 16/32-bit data word write command the remote CPU system +//! +//! \param psMessage specifies the pointer to the message received from remote +//! CPU system which includes the 16/32-bit data word to write to the local CPU +//! address. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! received from the remote CPU system to the address indicated in \e +//! *psMessage. In the event that the IPC_DATA_WRITE command was received as a +//! result of an IPC_DATA_READ command, this function will also clear the IPC +//! response flag tracking the read so other threads in the local CPU system +//! will be aware that the data is ready. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataWrite(tIpcMessage *psMessage) +{ + // + // Data word length = dataw1 (15:0), responseFlag = valid only for IPC + // flags 17-32 + // + uint16_t length = (uint16_t) psMessage->uldataw1; + uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; + + // + // Write 16/32-bit word to address + // + if (length == IPC_LENGTH_16_BITS) + { + *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; + } + else if (length == IPC_LENGTH_32_BITS) + { + *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; + } + + // + // If data write command is in response to a data read command from remote + // CPU to local CPU clear ResponseFlag, indicating read data from remote + // CPU is ready. + // + IpcRegs.IPCCLR.all |= responseFlag; +} + +//***************************************************************************** +// +//! Responds to 16/32-bit write-protected data word write command from +//! secondary CPU system +//! +//! \param psMessage specifies the pointer to the message received from the +//! secondary CPU system which includes the 16/32-bit data word to write to the +//! local CPU address. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! received from the secondary CPU system to the write-protected address +//! indicated in \e *psMessage. +//! In the event that the IPC_DATA_WRITE_PROTECTED command was received as a +//! result of an IPC_DATA_READ_PROTECTED command, this function will also clear +//! the IPC response flag tracking the read so other threads in the local CPU +//! will be aware that the data is ready. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataWrite_Protected(tIpcMessage *psMessage) +{ + // + // Data word length = dataw1 (15:0), responseFlag = valid only for IPC + // flags 17-32 + // + uint16_t length = (uint16_t) psMessage->uldataw1; + uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Write 16/32-bit word to EALLOW-protected address + // + if (length == IPC_LENGTH_16_BITS) + { + *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; + } + else if (length == IPC_LENGTH_32_BITS) + { + *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; + + // + // If data write command is in response to a data read command from local + // CPU to remote CPU, clear ResponseFlag, indicating read data from + // secondary CPU is ready + // + IpcRegs.IPCCLR.all |= responseFlag; +} + +//***************************************************************************** +// +//! Responds to 16/32-bit data word read command from remote CPU system. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the remote CPU system to read a 16/32-bit data +//! word at the local CPU address specified in /e psMessage, and send a Write +//! command with the read data back to the local CPU system. It will also send +//! the Response Flag used to track the read back to the remote CPU. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataRead(volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + unsigned long ulReaddata; + uint16_t usLength; + + // + // If data word length = 16-bits, read the 16-bit value at the given + // address and cast as 32-bit word to send back to remote CPU. + // If data word length = 32-bits, read the 32-bit value at the given + // address. + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + ulReaddata = *(unsigned long *)psMessage->uladdress; + } + + // + // Send a Write command to write the requested data to the remote CPU read + // into address. + // psMessage->uldataw2 contains remote CPU address where readdata will be + // written. + // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. + // + IPCLtoRDataWrite(psController, psMessage->uldataw2, ulReaddata, usLength, + bBlock,(psMessage->uldataw1 & 0xFFFF0000)); +} + +//***************************************************************************** +// +//! Responds to 16/32-bit data word read command from remote CPU system. +//! to read into a write-protected word on the remote CPU system. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the remote CPU system to read a 16/32-bit data +//! word at the local CPU address specified in /e psMessage, and send a Write +//! Protected command with the read data back to the remote CPU system at a +//! write protected address. It will also send the Response Flag used to track +//! the read back to the remote CPU. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataRead_Protected(volatile tIpcController *psController, + tIpcMessage *psMessage, uint16_t bBlock) +{ + unsigned long ulReaddata; + uint16_t usLength; + + // + // If data word length = 16-bits, read the 16-bit value at the given + // address and cast as 32-bit word to send back to remote CPU. + // If data word length = 32-bits, read the 32-bit value at the given + // address. + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + ulReaddata = *(unsigned long *)psMessage->uladdress; + } + + // + // Send a Write command to write the requested data to the remote CPU read + // into address. + // psMessage->uldataw2 contains remote CPU address where readdata will be + // written. + // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. + // + IPCLtoRDataWrite_Protected(psController, psMessage->uldataw2, ulReaddata, + usLength, bBlock, + (psMessage->uldataw1 & 0xFFFF0000)); +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at a local CPU system +//! address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to set the bits in a +//! 16/32-bit word on the local CPU system via a local CPU address and mask +//! passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLSetBits(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Determine length of word at psMessage->uladdress and then set bits based + // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress |= + (uint16_t) psMessage->uldataw2; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit write-protected data word at a +//! local CPU system address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to set the bits in a write- +//! protected 16/32-bit word on the local CPU system via a local CPU address +//! and mask passed in via the \e psMessage. +//! +//! \return None +// +//***************************************************************************** +void +IPCRtoLSetBits_Protected(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Determine length of word at psMessage->uladdress and then set bits based + // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress |= + (uint16_t) psMessage->uldataw2; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 32-bit data word at a local CPU system +//! address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to clear the bits in a +//! 16/32-bit word on the local CPU system via a local CPU address and mask +//! passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLClearBits(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Determine length of word at psMessage->uladdress and then clear bits + // based on + // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress &= + ~((uint16_t) psMessage->uldataw2); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress &= + ~(psMessage->uldataw2); + } +} + +//***************************************************************************** +// +//! Clears the designated bits in a write-protected 16/32-bit data word at a +//! local CPU system address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the secondary CPU system to clear the bits in a +//! 16/32-bit write-protected word on the local CPU system via a local +//! CPU address and mask passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLClearBits_Protected(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Determine length of word at psMessage->uladdress and then clear bits + // based on + // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress &= + ~((uint16_t) psMessage->uldataw2); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress &= + ~(psMessage->uldataw2); + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; +} + +//***************************************************************************** +// +//! Reads a block of data from a remote CPU system address and stores into +//! shared RAM +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will respond to the remote CPU system request to read a block +//! of data from the local control system, by reading the data and placing that +//! data into the shared RAM location specified in \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLBlockRead(tIpcMessage *psMessage) +{ + + uint16_t usLength; + volatile uint16_t* pusRAddress; + volatile uint16_t* pusWAddress; + uint16_t usIndex; + + pusRAddress = (volatile uint16_t *)psMessage->uladdress; + pusWAddress = (volatile uint16_t *)psMessage->uldataw2; + usLength = (uint16_t)psMessage->uldataw1; + + for (usIndex=0; usIndexuldataw1 & 0xFFFF0000); +} + +//***************************************************************************** +// +//! Writes a block of data to a local CPU system address from shared RAM +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will write a block of data to an address on the local CPU +//! system. +//! The data is first written by the remote CPU to shared RAM. This function +//! reads the shared RAM location, word size (16- or 32-bit), and block size +//! from \e psMessage and writes the block to the local address specified +//! in \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLBlockWrite(tIpcMessage *psMessage) +{ + uint16_t usLength; + uint16_t usWLength; + uint16_t usIndex; + + usLength = (uint16_t)psMessage->uldataw1; + usWLength = (uint16_t)((psMessage->uldataw1)>>16); + + // + // Determine data word access size to write to data block. + // + if (usWLength == IPC_LENGTH_16_BITS) + { + volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; + volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; + for (usIndex=0; usIndexuladdress; + volatile unsigned long *pulRAddress = + (volatile unsigned long *)psMessage->uldataw2; + + for (usIndex=0; usIndexuldataw1; + usWLength = (uint16_t)((psMessage->uldataw1)>>16); + + // + // Determine data word access size to write to data block. + // (Writes registers accessible via APB bus must be 32-bits wide) + // + if (usWLength == IPC_LENGTH_16_BITS) + { + volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; + volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; + for (usIndex=0; usIndexuladdress; + volatile unsigned long *pulRAddress = + (volatile unsigned long *)psMessage->uldataw2; + + for (usIndex=0; usIndexuladdress; + func_call(psMessage->uldataw1); +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c new file mode 100644 index 0000000000..9f8dc61c9c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c @@ -0,0 +1,1302 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver_Lite.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) Lite API Driver +// Functions. +// +// DESCRIPTION: +// API functions for inter-processor communications between +// CPU1 control system and CPU2 control system (Lite version). The IPC +// Lite functions only allow for basic functions such as data writes, +// reads, bit setting, and bit clearing. The Lite functions do not +// require the usage of the MSG RAM's or shared memories and can only +// be used with a single IPC interrupt channel. Commands can only +// be processed one at a time without queuing. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// cores use this code. +// The active debug CPU will be referred to as Local CPU and the other +// CPU will be referred to as Remote CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup ipc_lite_api IPC-Lite API Drivers +//! @{ +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_Ipc_drivers.h" + +// +// Function Prototypes +// +void DelayLoop (void); + +//***************************************************************************** +// +//! Reads single word data result of Local to Remote IPC command +//! +//! \param pvData is a pointer to the 16/32-bit variable where the result data +//! will be stored. +//! \param usLength designates 16- or 32-bit read. +//! \param ulStatusFlag indicates the Local to Remote CPU Flag number mask used +//! to report the status of the command sent back from the Remote CPU. If +//! a status flag was not used with the command call, set this parameter to 0. +//! +//! Allows the caller to read the 16/32-bit data result of non-blocking IPC +//! functions from the IPCREMOTEREPLY register if the status flag is cleared +//! indicating the IPC command was successfully interpreted. If the status flag +//! is not cleared, the command was not recognized, and the function will +//! return STATUS_FAIL. To determine what data is read from a call to this +//! function, see the descriptions of the non-blocking IPC functions. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +//! The function returns \b STATUS_PASS or \b STATUS_FAIL. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // If Remote System never acknowledged Status Task, indicates command + // failure. + // + if (IpcRegs.IPCFLG.all & ulStatusFlag) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Read data. + // + if (usLength == IPC_LENGTH_16_BITS) + { + *(uint16_t *)pvData = IpcRegs.IPCREMOTEREPLY; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(uint32_t *)pvData = IpcRegs.IPCREMOTEREPLY; + } + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Reads either a 16- or 32-bit data word from the remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the remote address to read from +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the remote system. +//! +//! This function will allow the Local CPU System to read 16/32-bit data from +//! the Remote CPU System into the IPCREMOTEREPLY register. After calling this +//! function, a call to \e IPCLiteLtoRGetResult() will read the data value in +//! the IPCREMOTEREPLY register into a 16- or 32-bit variable in the local CPU +//! application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up read command, address, and word length. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_READ_16; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_READ_32; + } + IpcRegs.IPCSENDADDR = ulAddress; + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the remote CPU system +//! address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote address to write to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! remote ulAddress. For 16-bit mask, only the lower 16-bits of ulMask are +//! considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Remote system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data +//! word at /e ulAddress after the set bits command is then read into the +//! IPCREMOTEREPLY register. After calling this function, a call to \e +//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_16; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_32; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit write-protected data word at +//! the Remote CPU system address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU write-protected address to write +//! to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask are +//! considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a write-protected 16/32-bit word on the REmote CPU +//! system. +//! The data word at /e ulAddress after the set bits command is then read into +//! the IPCREMOTEREPLY register. After calling this function, a call to +//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_16_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_32_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the remote CPU system +//! address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! the remote CPU ulAddress. (For 16-bit mask, only the lower 16-bits of +//! ulMask are considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data +//! word at /e ulAddress after the set bits command is then read into the +//! IPCREMOTEREPLY register. After calling this function, a call to \e +//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit write-protected data word at +//! Remote CPU system address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU write-protected address to write +//! to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask +//! are considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to clear bits specified by +//! the \e usMask variable in a write-protected 16/32-bit word on the Remote +//! CPU system. +//! The data word at /e ulAddress after the clear bits command is then read +//! into the IPCREMOTEREPLY register. After calling this function, a call to +//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to Remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (0 = 16-bits, 1 = +//! 32-bits) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Remote CPU system. +//! +//! This function will allow the Local CPU System to write a 16/32-bit word +//! via the \e ulData variable to an address on the Remote CPU System. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up data write command, address, and data. For 16-bit write, + // Master system will look at lower 16-bits only. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32; + } + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulData; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a protected Remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (0 = 16-bits, 1 = +//! 32-bits) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU System to write a 16/32-bit word +//! via the \e ulData variable to a write-protected address on the Remote CPU +//! System. The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up data write command, address, and data. For 16-bit write, Master + // system will look at lower 16-bits only. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16_PROTECTED; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32_PROTECTED; + } + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulData; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Calls a Remote CPU function with 1 optional parameter and an optional +//! return value. +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU function address +//! \param ulParam specifies the 32-bit optional parameter value +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Local CPU system to call a function on the +//! Remote CPU. The \e ulParam variable is a single optional 32-bit parameter +//! to pass to the function. The \e ulFlag parameter accepts any one of the +//! flag values \b IPC_FLAG1 - \b IPC_FLAG32. The \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 +//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is +//! successful or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulParam, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Remote to Local request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up function call command, address, and parameter. + // + IpcRegs.IPCSENDCOM = IPC_FUNC_CALL; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulParam; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Slave Requests Master R/W/Exe Access to Shared SARAM. +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulMask specifies the 32-bit mask for the GSxMEMSEL RAM control +//! register to indicate which GSx SARAM blocks the Slave is requesting master +//! access to. +//! \param ulMaster specifies whether CPU1 or CPU2 should be the master of the +//! GSx RAM. +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the slave CPU System to request slave or master +//! mastership of any of the GSx Shared SARAM blocks. +//! The \e ulMaster parameter accepts the following values: +//! \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulStatusFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 +//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is +//! successful or \b STATUS_FAIL if the request or status flags are unavailable. +//! \note This function calls the \e IPCLiteLtoRSetBits_Protected() or the +//! \e IPCLiteLtoRClearBits_Protected function, and therefore in order to +//! process this function, the above 2 functions should be ready to be called +//! on the master system to process this command. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, uint16_t ulMaster, + uint32_t ulStatusFlag) +{ + uint16_t status; + uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); + if (ulMaster == IPC_GSX_CPU2_MASTER) + { + status = + IPCLiteLtoRSetBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, + IPC_LENGTH_32_BITS, + ulStatusFlag); + } + else if (ulMaster == IPC_GSX_CPU1_MASTER) + { + status = + IPCLiteLtoRClearBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, + IPC_LENGTH_32_BITS, + ulStatusFlag); + } + + return status; +} + +//***************************************************************************** +// +//! Reads either a 16- or 32-bit data word from the Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to read 16/32-bit data from +//! the Local CPU system. The \e ulFlag parameter accepts any one of the +//! flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and +//! \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint32_t* pulRAddress; + uint16_t* pusRAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command and data length are correct for this function: + // Then read from requested address and write 16/32-bit data + // to IPCLOCALREPLY. Acknowledge the status flag + // and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_16) + { + // + // Perform 16-bit read. + // + pusRAddress = (uint16_t *)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = (uint32_t)(*pusRAddress); + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_32) + { + pulRAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = *pulRAddress; + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the Local CPU system +//! address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to set bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the +//! \e ulStatusFlag parameter accepts any other one of the flag values \b +//! IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then set the mask bits at the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit data word at the Local CPU system +//! write-protected address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to set bits specified by a +//! mask variable in a write-protected 16/32-bit word on the Local CPU system, +//! and then read back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // set the mask bits at the requested address. + // Write back the 16-bit data to IPCLOCALREPLY. + // Restore write-protection with EDIS. + // Acknowledge the status flag and the task flag. + // + + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16_PROTECTED) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR; + *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32_PROTECTED) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to the Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + EDIS; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit data word at Local CPU system +//! address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to clear bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then clear the mask bits at the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit data word at the Local CPU system +//! write-protected address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to clear bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // clear the mask bits at the requested address. + // Write back the 16/32-bit data to IPCLOCALREPLY. + // Restore the status of the EALLOW register. + // Acknowledge the status flag and the task flag. + // + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16_PROTECTED) + { + + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32_PROTECTED) + { + + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + EDIS; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to write a 16/32-bit word +//! to an address on the Local CPU system. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint32_t* pulAddress; + uint16_t* pusAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then write the 16/32-bit data to the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress = IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a write-protected Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to write a 16/32-bit word +//! to an address on the Local CPU system. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint32_t* pulAddress; + uint16_t* pusAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // write the 16/32-bit data to the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16_PROTECTED) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32_PROTECTED) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress = IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + // + // Restore write-protection status. + // + EDIS; +} + +//***************************************************************************** +// +//! Calls a Local CPU function with a single optional parameter and return +//! value. +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to call a Local CPU function +//! with a single optional parameter and places an optional return value in the +//! IPCLOCALREPLY register. The \e ulFlag parameter accepts any one of the flag +//! values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and +//! \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then call function at requested address + // and if there is a return value, insert into + // IPCLOCALREPLY register. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_FUNC_CALL) + { + tfIpcFuncCall func_call = (tfIpcFuncCall)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = func_call(IpcRegs.IPCRECVDATA); + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +void DelayLoop (void) +{ + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c new file mode 100644 index 0000000000..7f98a29ea1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c @@ -0,0 +1,469 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver_Util.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Utility +// Functions +// +// DESCRIPTION: +// API functions for inter-processor communications between the +// Local and Remote CPU system. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// cores use this code. +// The active debug CPU will be referred to as Local CPU and the other +// CPU will be referred to as Remote CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup ipc_util_api +//! @{ +// +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_GlobalPrototypes.h" +#include "F2837xD_Gpio_defines.h" +#include "F2837xD_Ipc_drivers.h" + +//***************************************************************************** +// +//! Local CPU Acknowledges Remote to Local IPC Flag. +//! +//! \param ulFlags specifies the IPC flag mask for flags being acknowledged. +//! +//! This function will allow the Local CPU system to acknowledge/clear the IPC +//! flag set by the Remote CPU system. The \e ulFlags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLFlagAcknowledge (uint32_t ulFlags) +{ + IpcRegs.IPCACK.all |= ulFlags; +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ulFlags specifies Remote to Local IPC Flag number masks to check the +//! status of. +//! +//! Allows the caller to determine whether the designated IPC flags are +//! pending. The \e ulFlags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated +//! IPC flags are free. +// +//***************************************************************************** +Uint16 +IPCRtoLFlagBusy (uint32_t ulFlags) +{ + Uint16 returnStatus; + + if ((IpcRegs.IPCSTS.all & ulFlags) == 0) + { + returnStatus = 0; + } + else + { + returnStatus = 1; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ulFlags specifies Local to Remote IPC Flag number masks to check the +//! status of. +//! +//! Allows the caller to determine whether the designated IPC flags are +//! available for further control to master system communication. If \b 0 is +//! returned, then all designated tasks have completed and are available. +//! The \e ulFlags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated +//! IPC flags are free. +// +//***************************************************************************** +Uint16 +IPCLtoRFlagBusy (uint32_t ulFlags) +{ + Uint16 returnStatus; + + if ((IpcRegs.IPCFLG.all & ulFlags) == 0) + { + returnStatus = 0; + } + else + { + returnStatus = 1; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Local CPU Sets Local to Remote IPC Flag +//! +//! \param ulFlags specifies the IPC flag mask for flags being set. +//! +//! This function will allow the Local CPU system to set the designated IPC +//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCLtoRFlagSet (uint32_t ulFlags) +{ + IpcRegs.IPCSET.all |= ulFlags; +} + +//***************************************************************************** +// +//! Local CPU Clears Local to Remote IPC Flag +//! +//! \param ulFlags specifies the IPC flag mask for flags being set. +//! +//! This function will allow the Local CPU system to set the designated IPC +//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCLtoRFlagClear (uint32_t ulFlags) +{ + IpcRegs.IPCCLR.all |= ulFlags; +} + +//***************************************************************************** +// +//! Local Return CPU02 BOOT status +//! +//! This function returns the value at IPCBOOTSTS register. +//! +//! \return Boot status. +// +//***************************************************************************** +uint32_t +IPCGetBootStatus (void) +{ + return(IpcRegs.IPCBOOTSTS); +} + +#if defined (CPU1) +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param ulBootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. Unlike other IPCLite driver functions, this +//! function blocks and waits until the control system boot ROM is configured +//! and ready to receive CPU01 to CPU02 IPC INT0 interrupts. It then blocks and +//! waits until IPC INT0 and IPC FLAG31 are available in the CPU02 boot ROM +//! prior to sending the command to execute the selected bootloader. The \e +//! ulBootMode parameter accepts one of the following values: \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_SCI, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_SPI, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_I2C, \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN, +//! \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH. +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +IPCBootCPU2(uint32_t ulBootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = IPCGetBootStatus() & 0x0000000F; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(IPCGetBootStatus() & 0x80000000)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = IPCGetBootStatus() & C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) || + (IPCLtoRFlagBusy(IPC_FLAG31) == 1)) + { + + } + + if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (ulBootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + EALLOW; + + // + //SCIA connected to CPU02 + // + DevCfgRegs.CPUSEL5.bit.SCI_A = 1; + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + + ClkCfgRegs.LOSPCP.all = 0x0002; + EDIS; + + GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + EALLOW; + + // + //SPI-A connected to CPU02 + // + DevCfgRegs.CPUSEL6.bit.SPI_A = 1; + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + EDIS; + + GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + EALLOW; + + // + //I2CA connected to CPU02 + // + DevCfgRegs.CPUSEL7.bit.I2C_A = 1; + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + ClkCfgRegs.LOSPCP.all = 0x0002; + EDIS; + GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1); + + break; + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0); + } + + GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0); + + GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0); + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + EALLOW; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 + + // + //Give CPU2 control just in case + // + GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2; + + // + //Set the extended mux to 0x5 + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1; + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1; + + // + //Set qualification to async just in case + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3; + + GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 + + // + //Give CPU2 control just in case + // + GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2; + + // + //Set the extended mux to bring out CANATX + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1; + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1; + + // + //Set qualification to async just in case + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3; + GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF; //Lock GPIOs 64-95 + ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0; + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + EDIS; + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + IpcRegs.IPCBOOTMODE = ulBootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + IpcRegs.IPCSET.all = 0x80000001; + + } + + + + return returnStatus; +} + + +#endif +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c new file mode 100644 index 0000000000..b93b01a4ff --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c @@ -0,0 +1,584 @@ +//########################################################################### +// +// FILE: F2837xD_McBSP.c +// +// TITLE: F2837xD Device McBSP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate +// generator (SRG) cycles required for the Mcbsp initialization routine. +// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock +// generator (CLKG) cycles required for the Mcbsp initialization routine. +// + +// +// Defines +// +#define CPU_SPD 200E6 +#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) + // for examples +#define CLKGDV_VAL 1 + +// # of CPU cycles in 2 SRG cycles-init delay +#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) + +// # of CPU cycles in 2 CLKG cycles-init delay +#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) + +// +// Function Prototypes +// +void delay_loop(void); // Delay function used for SRG initialization +void clkg_delay_loop(void); // Delay function used for CLKG initialization + +// +// InitMcbsp - This function initializes the McBSP to a known state. +// +void InitMcbspa(void) +{ + // + // Reset the McBSP + // Disable all interrupts + // Frame sync generator reset + // Sample rate generator reset + // Transmitter reset + // Receiver reset + // + McbspaRegs.SPCR2.bit.FRST = 0; + McbspaRegs.SPCR2.bit.GRST = 0; + McbspaRegs.SPCR2.bit.XRST = 0; + McbspaRegs.SPCR1.bit.RRST = 0; + + // + // Enable loop back mode + // This does not require external hardware + // + McbspaRegs.SPCR2.all = 0x0000; + McbspaRegs.SPCR1.all = 0x8000; + + // + // RX data delay is 1 bit + // TX data delay is 1 bit + // + McbspaRegs.RCR2.bit.RDATDLY = 1; + McbspaRegs.XCR2.bit.XDATDLY = 1; + + // + // No clock sync for CLKG + // Frame-synchronization period + // + McbspaRegs.SRGR2.bit.GSYNC = 0; + McbspaRegs.SRGR2.bit.FPER = 320; + + // + // Frame-synchronization pulses from + // the sample rate generator + // + McbspaRegs.SRGR2.bit.FSGM = 1; + + // + // Sample rate generator input clock is LSPCLK + // + McbspaRegs.SRGR2.bit.CLKSM = 1; + McbspaRegs.PCR.bit.SCLKME = 0; + + // + // Divide-down value for CLKG + // Frame-synchronization pulse width + // + McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + clkg_delay_loop(); + McbspaRegs.SRGR1.bit.FWID = 1; + + // + // CLKX is driven by the sample rate generator + // Transmit frame synchronization generated by internal + // sample rate generator + // + McbspaRegs.PCR.bit.CLKXM = 1; + McbspaRegs.PCR.bit.FSXM = 1; + + // + // Enable Sample rate generator and + // wait at least 2 CLKG clock cycles + // + McbspaRegs.SPCR2.bit.GRST = 1; + clkg_delay_loop(); + + // + // Release from reset + // RX, TX and frame sync generator + // + McbspaRegs.SPCR2.bit.XRST = 1; + McbspaRegs.SPCR1.bit.RRST = 1; + McbspaRegs.SPCR2.bit.FRST = 1; +} + +// +// InitMcbspaInt - Enable TX and RX interrupts +// +void InitMcbspaInt(void) +{ + // Reset TX and RX + // Enable interrupts for TX and RX + // Release TX and RX + McbspaRegs.SPCR2.bit.XRST = 0; + McbspaRegs.SPCR1.bit.RRST = 0; + McbspaRegs.MFFINT.bit.XINT = 1; + McbspaRegs.MFFINT.bit.RINT = 1; + McbspaRegs.SPCR2.bit.XRST = 1; + McbspaRegs.SPCR1.bit.RRST = 1; +} + +// +// InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX +// +void InitMcbspa8bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 0; + McbspaRegs.XCR1.bit.XWDLEN1 = 0; +} + +// +// InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX +// +void InitMcbspa12bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 1; + McbspaRegs.XCR1.bit.XWDLEN1 = 1; +} + +// +// InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX +// +void InitMcbspa16bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 2; + McbspaRegs.XCR1.bit.XWDLEN1 = 2; +} + +// +// InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX +// +void InitMcbspa20bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 3; + McbspaRegs.XCR1.bit.XWDLEN1 = 3; +} + +// +// InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX +// +void InitMcbspa24bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 4; + McbspaRegs.XCR1.bit.XWDLEN1 = 4; +} + +// +// InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX +// +void InitMcbspa32bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 5; + McbspaRegs.XCR1.bit.XWDLEN1 = 5; +} + +// +// InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral +// (Note: This function must be called from CPU1.) +// +void InitMcbspaGpio(void) +{ +#ifdef CPU1 + EALLOW; + + // + // This specifies which of the possible GPIO pins will be + // McBSPA functional pins. Comment out unwanted connections. + // Set qualification for selected input pins to asynchronous only + // This will select asynchronous (no qualification) for the selected pins. + // + + // + // MDXA + // GPIO20 + // GPIO84 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; + + // + // MDRA + // GPIO21 with asynchronous qualification + // GPIO85 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; + + // + // MCLKXA + // GPIO22 with asynchronous qualification + // GPIO86 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3; + + // + // MCLKRA + // Select one of the following + // GPIO7 with asynchronous qualification + // GPIO58 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; + //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; + //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; + + // + // MFSXA + // GPIO23 with asynchronous qualification + // GPIO87 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3; + + // + // MFSRA + // Select one of the following + // GPIO5 with asynchronous qualification + // GPIO59 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; + //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; + //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; + + EDIS; +#endif +} + +// +// InitMcbspb - McBSPB initialization routine for examples +// +void InitMcbspb(void) +{ + // + // Reset the McBSP + // Disable all interrupts + // Frame sync generator reset + // Sample rate generator reset + // Transmitter reset + // Receiver reset + // + McbspbRegs.SPCR2.bit.FRST = 0; + McbspbRegs.SPCR2.bit.GRST = 0; + McbspbRegs.SPCR2.bit.XRST = 0; + McbspbRegs.SPCR1.bit.RRST = 0; + + // + // Enable loop back mode + // This does not require external hardware + // + McbspbRegs.SPCR2.all = 0x0000; + McbspbRegs.SPCR1.all = 0x8000; + + // + // RX data delay is 1 bit + // TX data delay is 1 bit + // + McbspbRegs.RCR2.bit.RDATDLY = 1; + McbspbRegs.XCR2.bit.XDATDLY = 1; + + // + // No clock sync for CLKG + // Frame-synchronization period + // + McbspbRegs.SRGR2.bit.GSYNC = 0; + McbspbRegs.SRGR2.bit.FPER = 320; + + // + // Frame-synchronization pulses from + // the sample rate generator + // + McbspbRegs.SRGR2.bit.FSGM = 1; + + // + // Sample rate generator input clock is LSPCLK + // + McbspbRegs.SRGR2.bit.CLKSM = 1; + McbspbRegs.PCR.bit.SCLKME = 0; + + // + // Divide-down value for CLKG + // Frame-synchronization pulse width + // + McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + clkg_delay_loop(); + McbspbRegs.SRGR1.bit.FWID = 1; + + // + // CLKX is driven by the sample rate generator + // Transmit frame synchronization generated by internal + // sample rate generator + // + McbspbRegs.PCR.bit.CLKXM = 1; + McbspbRegs.PCR.bit.FSXM = 1; + + // + // Enable Sample rate generator and + // wait at least 2 CLKG clock cycles + // + McbspbRegs.SPCR2.bit.GRST = 1; + clkg_delay_loop(); + + // + // Release from reset + // RX, TX and frame sync generator + // + McbspbRegs.SPCR2.bit.XRST = 1; + McbspbRegs.SPCR1.bit.RRST = 1; + McbspbRegs.SPCR2.bit.FRST = 1; +} + +// +// InitMcbspbInt - Enable TX and RX interrupts +// +void InitMcbspbInt(void) +{ + // + // Reset TX and RX + // Enable interrupts for TX and RX + // Release TX and RX + // + McbspbRegs.SPCR2.bit.XRST = 0; + McbspbRegs.SPCR1.bit.RRST = 0; + McbspbRegs.MFFINT.bit.XINT = 1; + McbspbRegs.MFFINT.bit.RINT = 1; + McbspbRegs.SPCR2.bit.XRST = 1; + McbspbRegs.SPCR1.bit.RRST = 1; +} + +// +// InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX +// +void InitMcbspb8bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 0; + McbspbRegs.XCR1.bit.XWDLEN1 = 0; +} + +// +// IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX +// +void IniMcbspb12bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 1; + McbspbRegs.XCR1.bit.XWDLEN1 = 1; +} + +// +// InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX +// +void InitMcbspb16bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 2; + McbspbRegs.XCR1.bit.XWDLEN1 = 2; +} + +// +// InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX +// +void InitMcbspb20bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 3; + McbspbRegs.XCR1.bit.XWDLEN1 = 3; +} + +// +// InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX +// +void InitMcbspb24bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 4; + McbspbRegs.XCR1.bit.XWDLEN1 = 4; +} + +// +// InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX +// +void InitMcbspb32bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 5; + McbspbRegs.XCR1.bit.XWDLEN1 = 5; +} + +// +// InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral +// (Note: This function must be called from CPU1.) +// +void InitMcbspbGpio(void) +{ +#ifdef CPU1 + EALLOW; + + // + // This specifies which of the possible GPIO pins will be + // McBSPB functional pins. Comment out unwanted connections. + // Set qualification for selected input pins to asynchronous only + // This will select asynchronous (no qualification) for the selected pins. + // + + // + // Select one of the following for MDXB + // GPIO24 + // GPIO84 + // + //GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; + + // + // MDRB + // GPIO13 with asynchronous qualification + // GPIO25 with asynchronous qualification + // GPIO85 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; + + // + // MCLKXB + // GPIO14 with asynchronous qualification + // GPIO26 with asynchronous qualification + // GPIO86 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3; + + // + // MCLKRB + // Select one of the following + // GPIO3 with asynchronous qualification + // GPIO60 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; + + // + // MFSXB + // GPIO15 with asynchronous qualification + // GPIO27 with asynchronous qualification + // GPIO87 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3; + + // + // MFSRB + // Select one of the following + // GPIO1 with asynchronous qualification + // GPIO61 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; + + EDIS; + +#endif +} + +// +// delay_loop - Delay function (at least 2 SRG cycles) +// Required in McBSP initialization +// +void delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_INIT_DELAY; i++) {} +} + +// +// clkg_delay_loop - Delay function (at least 2 CLKG cycles) +// Required in McBSP init +// +void clkg_delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c new file mode 100644 index 0000000000..e6be2e920c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c @@ -0,0 +1,121 @@ +//########################################################################### +// +// FILE: F2837xD_PieCtrl.c +// +// TITLE: F2837xD Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a +// known state. +// +void InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level: + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers: + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers: + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU __interrupts +// +void EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c new file mode 100644 index 0000000000..20e8fbf74b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c @@ -0,0 +1,320 @@ +//########################################################################### +// +// FILE: F2837xD_PieVect.c +// +// TITLE: F2837xD Device PIE Vector Initialization Functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Globals +// +const struct PIE_VECT_TABLE PieVectTableInit = { + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + TIMER1_ISR, // CPU Timer 1 Interrupt + TIMER2_ISR, // CPU Timer 2 Interrupt + DATALOG_ISR, // Datalogging Interrupt + RTOS_ISR, // RTOS Interrupt + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + XINT1_ISR, // 1.4 - XINT1 Interrupt + XINT2_ISR, // 1.5 - XINT2 Interrupt + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + PIE_RESERVED_ISR, // 4.7 - Reserved + PIE_RESERVED_ISR, // 4.8 - Reserved + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + PIE_RESERVED_ISR, // 5.4 - Reserved + PIE_RESERVED_ISR, // 5.5 - Reserved + PIE_RESERVED_ISR, // 5.6 - Reserved + PIE_RESERVED_ISR, // 5.7 - Reserved + PIE_RESERVED_ISR, // 5.8 - Reserved + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + CANA0_ISR, // 9.5 - CANA Interrupt 0 + CANA1_ISR, // 9.6 - CANA Interrupt 1 + CANB0_ISR, // 9.7 - CANB Interrupt 0 + CANB1_ISR, // 9.8 - CANB Interrupt 1 + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + XINT3_ISR, // 12.1 - XINT3 Interrupt + XINT4_ISR, // 12.2 - XINT4 Interrupt + XINT5_ISR, // 12.3 - XINT5 Interrupt + PIE_RESERVED_ISR, // 12.4 - Reserved + PIE_RESERVED_ISR, // 12.5 - Reserved + VCU_ISR, // 12.6 - VCU Interrupt + FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt + FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt + PIE_RESERVED_ISR, // 1.9 - Reserved + PIE_RESERVED_ISR, // 1.10 - Reserved + PIE_RESERVED_ISR, // 1.11 - Reserved + PIE_RESERVED_ISR, // 1.12 - Reserved + IPC0_ISR, // 1.13 - IPC Interrupt 0 + IPC1_ISR, // 1.14 - IPC Interrupt 1 + IPC2_ISR, // 1.15 - IPC Interrupt 2 + IPC3_ISR, // 1.16 - IPC Interrupt 3 + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + PIE_RESERVED_ISR, // 2.13 - Reserved + PIE_RESERVED_ISR, // 2.14 - Reserved + PIE_RESERVED_ISR, // 2.15 - Reserved + PIE_RESERVED_ISR, // 2.16 - Reserved + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + PIE_RESERVED_ISR, // 3.13 - Reserved + PIE_RESERVED_ISR, // 3.14 - Reserved + PIE_RESERVED_ISR, // 3.15 - Reserved + PIE_RESERVED_ISR, // 3.16 - Reserved + PIE_RESERVED_ISR, // 4.9 - Reserved + PIE_RESERVED_ISR, // 4.10 - Reserved + PIE_RESERVED_ISR, // 4.11 - Reserved + PIE_RESERVED_ISR, // 4.12 - Reserved + PIE_RESERVED_ISR, // 4.13 - Reserved + PIE_RESERVED_ISR, // 4.14 - Reserved + PIE_RESERVED_ISR, // 4.15 - Reserved + PIE_RESERVED_ISR, // 4.16 - Reserved + SD1_ISR, // 5.9 - SD1 Interrupt + SD2_ISR, // 5.10 - SD2 Interrupt + PIE_RESERVED_ISR, // 5.11 - Reserved + PIE_RESERVED_ISR, // 5.12 - Reserved + PIE_RESERVED_ISR, // 5.13 - Reserved + PIE_RESERVED_ISR, // 5.14 - Reserved + PIE_RESERVED_ISR, // 5.15 - Reserved + PIE_RESERVED_ISR, // 5.16 - Reserved + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + PIE_RESERVED_ISR, // 6.11 - Reserved + PIE_RESERVED_ISR, // 6.12 - Reserved + PIE_RESERVED_ISR, // 6.13 - Reserved + PIE_RESERVED_ISR, // 6.14 - Reserved + PIE_RESERVED_ISR, // 6.15 - Reserved + PIE_RESERVED_ISR, // 6.16 - Reserved + PIE_RESERVED_ISR, // 7.9 - Reserved + PIE_RESERVED_ISR, // 7.10 - Reserved + PIE_RESERVED_ISR, // 7.11 - Reserved + PIE_RESERVED_ISR, // 7.12 - Reserved + PIE_RESERVED_ISR, // 7.13 - Reserved + PIE_RESERVED_ISR, // 7.14 - Reserved + PIE_RESERVED_ISR, // 7.15 - Reserved + PIE_RESERVED_ISR, // 7.16 - Reserved + PIE_RESERVED_ISR, // 8.9 - Reserved + PIE_RESERVED_ISR, // 8.10 - Reserved + PIE_RESERVED_ISR, // 8.11 - Reserved + PIE_RESERVED_ISR, // 8.12 - Reserved + PIE_RESERVED_ISR, // 8.13 - Reserved + PIE_RESERVED_ISR, // 8.14 - Reserved +#ifdef CPU1 + UPPA_ISR, // 8.15 - uPPA Interrupt + PIE_RESERVED_ISR, // 8.16 - Reserved +#elif defined(CPU2) + PIE_RESERVED_ISR, // 8.15 - Reserved + PIE_RESERVED_ISR, // 8.16 - Reserved +#endif + PIE_RESERVED_ISR, // 9.9 - Reserved + PIE_RESERVED_ISR, // 9.10 - Reserved + PIE_RESERVED_ISR, // 9.11 - Reserved + PIE_RESERVED_ISR, // 9.12 - Reserved + PIE_RESERVED_ISR, // 9.13 - Reserved + PIE_RESERVED_ISR, // 9.14 - Reserved +#ifdef CPU1 + USBA_ISR, // 9.15 - USBA Interrupt +#elif defined(CPU2) + PIE_RESERVED_ISR, // 9.15 - Reserved +#endif + PIE_RESERVED_ISR, // 9.16 - Reserved + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + PIE_RESERVED_ISR, // 11.9 - Reserved + PIE_RESERVED_ISR, // 11.10 - Reserved + PIE_RESERVED_ISR, // 11.11 - Reserved + PIE_RESERVED_ISR, // 11.12 - Reserved + PIE_RESERVED_ISR, // 11.13 - Reserved + PIE_RESERVED_ISR, // 11.14 - Reserved + PIE_RESERVED_ISR, // 11.15 - Reserved + PIE_RESERVED_ISR, // 11.16 - Reserved + EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt + RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt + FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt + RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt + SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt + AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a +// known state and must be executed after boot time. +// +void InitPieVectTable(void) +{ + Uint16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + // + // Do not write over first 3 32-bit locations (these locations are + // initialized by Boot ROM with boot variables) + // + Source = Source + 3; + Dest = Dest + 3; + + EALLOW; + for(i = 0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c new file mode 100644 index 0000000000..7c2b5d1f56 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c @@ -0,0 +1,967 @@ +//########################################################################### +// +// FILE: F2837xD_SWPrioritizedPieVect.c +// +// TITLE: F2837xD Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include "F2837xD_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + + // + // Non-Peripheral Interrupts: + // + #if (INT13PL != 0) + TIMER1_ISR, // CPU Timer 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + TIMER2_ISR, // CPU Timer 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOS_ISR, // RTOS Interrupt + #else + INT_NOTUSED_ISR, + #endif + + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + + // + // Group 1 PIE Vectors: + // + #if (G1_1PL != 0) + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_2PL != 0) + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_3PL != 0) + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_4PL != 0) + XINT1_ISR, // 1.4 - XINT1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_5PL != 0) + XINT2_ISR, // 1.5 - XINT2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_6PL != 0) + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_7PL != 0) + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_8PL != 0) + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 2 PIE Vectors: + // + #if (G2_1PL != 0) + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_2PL != 0) + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_3PL != 0) + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_4PL != 0) + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_5PL != 0) + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_6PL != 0) + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_7PL != 0) + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_8PL != 0) + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 3 PIE Vectors: + // + #if (G3_1PL != 0) + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_2PL != 0) + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_3PL != 0) + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_4PL != 0) + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_5PL != 0) + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_6PL != 0) + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_7PL != 0) + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_8PL != 0) + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 4 PIE Vectors: + // + #if (G4_1PL != 0) + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_2PL != 0) + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_3PL != 0) + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_4PL != 0) + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_5PL != 0) + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_6PL != 0) + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 4.7 - Reserved + PIE_RESERVED_ISR, // 4.8 - Reserved + + // + // Group 5 PIE Vectors: + // + #if (G5_1PL != 0) + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_2PL != 0) + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_3PL != 0) + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 5.4 - Reserved + PIE_RESERVED_ISR, // 5.5 - Reserved + PIE_RESERVED_ISR, // 5.6 - Reserved + PIE_RESERVED_ISR, // 5.7 - Reserved + PIE_RESERVED_ISR, // 5.8 - Reserved + + // + // Group 6 PIE Vectors: + // + #if (G6_1PL != 0) + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_2PL != 0) + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_3PL != 0) + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_4PL != 0) + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_5PL != 0) + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_6PL != 0) + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_7PL != 0) + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_8PL != 0) + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 7 PIE Vectors: + // + #if (G7_1PL != 0) + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_2PL != 0) + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_3PL != 0) + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_4PL != 0) + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_5PL != 0) + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_6PL != 0) + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + + // + // Group 8 PIE Vectors: + // + #if (G8_1PL != 0) + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_2PL != 0) + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_3PL != 0) + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_4PL != 0) + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_5PL != 0) + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_6PL != 0) + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_7PL != 0) + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_8PL != 0) + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 9 PIE Vectors: + // + #if (G9_1PL != 0) + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_2PL != 0) + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_3PL != 0) + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_4PL != 0) + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_5PL != 0) + CANA0_ISR, // 9.5 - CANA Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_6PL != 0) + CANA1_ISR, // 9.6 - CANA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_7PL != 0) + CANB0_ISR, // 9.7 - CANB Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_8PL != 0) + CANB1_ISR, // 9.8 - CANB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 10 PIE Vectors + // + #if (G10_1PL != 0) + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_2PL != 0) + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_3PL != 0) + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_4PL != 0) + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_5PL != 0) + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_6PL != 0) + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_7PL != 0) + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_8PL != 0) + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 11 PIE Vectors + // + #if (G11_1PL != 0) + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_2PL != 0) + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_3PL != 0) + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_4PL != 0) + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_5PL != 0) + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_6PL != 0) + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_7PL != 0) + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_8PL != 0) + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 12 PIE Vectors + // + #if (G12_1PL != 0) + XINT3_ISR, // 12.1 - XINT3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_2PL != 0) + XINT4_ISR, // 12.2 - XINT4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_3PL != 0) + XINT5_ISR, // 12.3 - XINT5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 12.4 - Reserved + PIE_RESERVED_ISR, // 12.5 - Reserved + + #if (G12_6PL != 0) + VCU_ISR, // 12.6 - VCU Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_7PL != 0) + FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_8PL != 0) + FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 1.9 - Reserved + PIE_RESERVED_ISR, // 1.10 - Reserved + PIE_RESERVED_ISR, // 1.11 - Reserved + PIE_RESERVED_ISR, // 1.12 - Reserved + + #if (G1_13PL != 0) + IPC0_ISR, // 1.13 - IPC Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_14PL != 0) + IPC1_ISR, // 1.14 - IPC Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_15PL != 0) + IPC2_ISR, // 1.15 - IPC Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_16PL != 0) + IPC3_ISR, // 1.16 - IPC Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_9PL != 0) + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_10PL != 0) + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_11PL != 0) + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_12PL != 0) + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 2.13 - Reserved + PIE_RESERVED_ISR, // 2.14 - Reserved + PIE_RESERVED_ISR, // 2.15 - Reserved + PIE_RESERVED_ISR, // 2.16 - Reserved + + #if (G3_9PL != 0) + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_10PL != 0) + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_11PL != 0) + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_12PL != 0) + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 3.13 - Reserved + PIE_RESERVED_ISR, // 3.14 - Reserved + PIE_RESERVED_ISR, // 3.15 - Reserved + PIE_RESERVED_ISR, // 3.16 - Reserved + PIE_RESERVED_ISR, // 4.9 - Reserved + PIE_RESERVED_ISR, // 4.10 - Reserved + PIE_RESERVED_ISR, // 4.11 - Reserved + PIE_RESERVED_ISR, // 4.12 - Reserved + PIE_RESERVED_ISR, // 4.13 - Reserved + PIE_RESERVED_ISR, // 4.14 - Reserved + PIE_RESERVED_ISR, // 4.15 - Reserved + PIE_RESERVED_ISR, // 4.16 - Reserved + + #if (G5_9PL != 0) + SD1_ISR, // 5.9 - SD1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_10PL != 0) + SD2_ISR, // 5.10 - SD2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 5.11 - Reserved + PIE_RESERVED_ISR, // 5.12 - Reserved + PIE_RESERVED_ISR, // 5.13 - Reserved + PIE_RESERVED_ISR, // 5.14 - Reserved + PIE_RESERVED_ISR, // 5.15 - Reserved + PIE_RESERVED_ISR, // 5.16 - Reserved + + #if (G6_9PL != 0) + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_10PL != 0) + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 6.11 - Reserved + PIE_RESERVED_ISR, // 6.12 - Reserved + PIE_RESERVED_ISR, // 6.13 - Reserved + PIE_RESERVED_ISR, // 6.14 - Reserved + PIE_RESERVED_ISR, // 6.15 - Reserved + PIE_RESERVED_ISR, // 6.16 - Reserved + PIE_RESERVED_ISR, // 7.9 - Reserved + PIE_RESERVED_ISR, // 7.10 - Reserved + PIE_RESERVED_ISR, // 7.11 - Reserved + PIE_RESERVED_ISR, // 7.12 - Reserved + PIE_RESERVED_ISR, // 7.13 - Reserved + PIE_RESERVED_ISR, // 7.14 - Reserved + PIE_RESERVED_ISR, // 7.15 - Reserved + PIE_RESERVED_ISR, // 7.16 - Reserved + PIE_RESERVED_ISR, // 8.9 - Reserved + PIE_RESERVED_ISR, // 8.10 - Reserved + PIE_RESERVED_ISR, // 8.11 - Reserved + PIE_RESERVED_ISR, // 8.12 - Reserved + PIE_RESERVED_ISR, // 8.13 - Reserved + PIE_RESERVED_ISR, // 8.14 - Reserved +#ifdef CPU1 + + #if (G8_15PL != 0) + UPPA_ISR, // 8.15 - uPPA Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 8.16 - Reserved +#elif defined(CPU2) + PIE_RESERVED_ISR, // 8.15 - Reserved + PIE_RESERVED_ISR, // 8.16 - Reserved +#endif + PIE_RESERVED_ISR, // 9.9 - Reserved + PIE_RESERVED_ISR, // 9.10 - Reserved + PIE_RESERVED_ISR, // 9.11 - Reserved + PIE_RESERVED_ISR, // 9.12 - Reserved + PIE_RESERVED_ISR, // 9.13 - Reserved + PIE_RESERVED_ISR, // 9.14 - Reserved +#ifdef CPU1 + + #if (G9_15PL != 0) + USBA_ISR, // 9.15 - USBA Interrupt + #else + INT_NOTUSED_ISR, + #endif +#elif defined(CPU2) + PIE_RESERVED_ISR, // 9.15 - Reserved +#endif + PIE_RESERVED_ISR, // 9.16 - Reserved + + #if (G10_9PL != 0) + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_10PL != 0) + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_11PL != 0) + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_12PL != 0) + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_13PL != 0) + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_14PL != 0) + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_15PL != 0) + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_16PL != 0) + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 11.9 - Reserved + PIE_RESERVED_ISR, // 11.10 - Reserved + PIE_RESERVED_ISR, // 11.11 - Reserved + PIE_RESERVED_ISR, // 11.12 - Reserved + PIE_RESERVED_ISR, // 11.13 - Reserved + PIE_RESERVED_ISR, // 11.14 - Reserved + PIE_RESERVED_ISR, // 11.15 - Reserved + PIE_RESERVED_ISR, // 11.16 - Reserved + + #if (G12_9PL != 0) + EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_10PL != 0) + RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_11PL != 0) + FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_12PL != 0) + RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_13PL != 0) + SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_14PL != 0) + AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_15PL != 0) + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_16PL != 0) + CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; +} + +// +// End of File +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c new file mode 100644 index 0000000000..e21b934a5e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c @@ -0,0 +1,48 @@ +//########################################################################### +// +// FILE: F2837xD_Sci.c +// +// TITLE: F2837xD SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c new file mode 100644 index 0000000000..1a82751d7e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: F2837xD_Spi.c +// +// TITLE: F2837xD SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Calculate BRR: 7-bit baud rate register value +// SPI CLK freq = 500 kHz +// LSPCLK freq = CPU freq / 4 (by default) +// BRR = (LSPCLK freq / SPI CLK freq) - 1 +// +#if CPU_FRQ_200MHZ +#define SPI_BRR ((200E6 / 4) / 500E3) - 1 +#endif + +#if CPU_FRQ_150MHZ +#define SPI_BRR ((150E6 / 4) / 500E3) - 1 +#endif + +#if CPU_FRQ_120MHZ +#define SPI_BRR ((120E6 / 4) / 500E3) - 1 +#endif + +// +// InitSPI - This function initializes the SPI to a known state +// +void InitSpi(void) +{ + // Initialize SPI-A + + // Set reset low before configuration changes + // Clock polarity (0 == rising, 1 == falling) + // 16-bit character + // Enable loop-back + SpiaRegs.SPICCR.bit.SPISWRESET = 0; + SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; + SpiaRegs.SPICCR.bit.SPICHAR = (16-1); + SpiaRegs.SPICCR.bit.SPILBK = 1; + + // Enable master (0 == slave, 1 == master) + // Enable transmission (Talk) + // Clock phase (0 == normal, 1 == delayed) + // SPI interrupts are disabled + SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; + SpiaRegs.SPICTL.bit.TALK = 1; + SpiaRegs.SPICTL.bit.CLK_PHASE = 0; + SpiaRegs.SPICTL.bit.SPIINTENA = 0; + + // Set the baud rate + SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; + + // Set FREE bit + // Halting on a breakpoint will not halt the SPI + SpiaRegs.SPIPRI.bit.FREE = 1; + + // Release the SPI from reset + SpiaRegs.SPICCR.bit.SPISWRESET = 1; +} + +// +// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins come +// up as GPIO inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLK operation. +// Only one GPIO pin should be enabled for SPISTE operation. +// Comment out other unwanted lines. +// +void InitSpiGpio() +{ + InitSpiaGpio(); +} + +// +// InitSpiaGpio - Initialize SPIA GPIOs +// +void InitSpiaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) + + // + // Set qualification for selected pins to asynch only + // + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + + // + //Configure SPI-A pins using GPIO regs + // + // This specifies which of the possible GPIO pins will be SPI functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA +// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA +// GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c new file mode 100644 index 0000000000..0971cee2d5 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c @@ -0,0 +1,1276 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl.c +// +// TITLE: F2837xD Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +#define TMR1SYSCLKCTR 0xF0000000 +#define TMR2INPCLKCTR 0x800 + +// +// Functions that will be run from RAM need to be assigned to a different +// section. This section will then be mapped to a load and run address using +// the linker cmd file. +// +// *IMPORTANT* +// +// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM +// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM +// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. +// +#ifndef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #pragma CODE_SECTION(FlashOff, "ramfuncs"); + #endif + #endif +#endif + +// +// InitSysCtrl - Initialization of system resources. +// +void InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + +#ifdef _FLASH + // + // Copy time critical code and Flash setup code to RAM. This includes the + // following functions: InitFlash() + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart + // symbols are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + InitFlash(); +#endif + + // + // *IMPORTANT* + // + // The Device_cal function, which copies the ADC & oscillator calibration + // values from TI reserved OTP into the appropriate trim registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC and + // oscillators to function according to specification. The clocks to the + // ADC MUST be enabled before calling this function. + // + // See the device data manual and/or the ADC Reference Manual for more + // information. + // +#ifdef CPU1 + EALLOW; + + // + // Enable pull-ups on unbonded IOs as soon as possible to reduce power + // consumption. + // + GPIO_EnableUnbondedIOPullups(); + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + // + // Check if device is trimmed + // + if(*((Uint16 *)0x5D1B6) == 0x0000){ + // + // Device is not trimmed--apply static calibration values + // + AnalogSubsysRegs.ANAREFTRIMA.all = 31709; + AnalogSubsysRegs.ANAREFTRIMB.all = 31709; + AnalogSubsysRegs.ANAREFTRIMC.all = 31709; + AnalogSubsysRegs.ANAREFTRIMD.all = 31709; + } + + CpuSysRegs.PCLKCR13.bit.ADC_A = 0; + CpuSysRegs.PCLKCR13.bit.ADC_B = 0; + CpuSysRegs.PCLKCR13.bit.ADC_C = 0; + CpuSysRegs.PCLKCR13.bit.ADC_D = 0; + EDIS; + + // + // Initialize the PLL control: SYSPLLMULT and SYSCLKDIVSEL. + // + // Defined options to be passed as arguments to this function are defined + // in F2837xD_Examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // PLLSYSCLK is configured to frequencies above 194 MHz. + // + // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) + // +#ifdef _LAUNCHXL_F28379D + InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2); +#else + InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2); +#endif // _LAUNCHXL_F28379D + +#endif // CPU1 + + // + // Turn on all peripherals + // + InitPeripheralClocks(); +} + +// +// InitPeripheralClocks - Initializes the clocks for the peripherals. +// +// Note: In order to reduce power consumption, turn off the clocks to any +// peripheral that is not specified for your part-number or is not used in the +// application +// +void InitPeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.bit.CLA1 = 1; + CpuSysRegs.PCLKCR0.bit.DMA = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR0.bit.HRPWM = 1; +#endif + + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; + CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; +#endif + + CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; + + CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; + + CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; + + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + CpuSysRegs.PCLKCR7.bit.SCI_D = 1; + + CpuSysRegs.PCLKCR8.bit.SPI_A = 1; + CpuSysRegs.PCLKCR8.bit.SPI_B = 1; + CpuSysRegs.PCLKCR8.bit.SPI_C = 1; + + CpuSysRegs.PCLKCR9.bit.I2C_A = 1; + CpuSysRegs.PCLKCR9.bit.I2C_B = 1; + + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + CpuSysRegs.PCLKCR10.bit.CAN_B = 1; + + CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; + CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR11.bit.USB_A = 1; + + CpuSysRegs.PCLKCR12.bit.uPP_A = 1; +#endif + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; + + CpuSysRegs.PCLKCR16.bit.DAC_A = 1; + CpuSysRegs.PCLKCR16.bit.DAC_B = 1; + CpuSysRegs.PCLKCR16.bit.DAC_C = 1; + + EDIS; +} + +// +// DisablePeripheralClocks - Gates-off all peripheral clocks. +// +void DisablePeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.all = 0; + CpuSysRegs.PCLKCR1.all = 0; + CpuSysRegs.PCLKCR2.all = 0; + CpuSysRegs.PCLKCR3.all = 0; + CpuSysRegs.PCLKCR4.all = 0; + CpuSysRegs.PCLKCR6.all = 0; + CpuSysRegs.PCLKCR7.all = 0; + CpuSysRegs.PCLKCR8.all = 0; + CpuSysRegs.PCLKCR9.all = 0; + CpuSysRegs.PCLKCR10.all = 0; + CpuSysRegs.PCLKCR11.all = 0; + CpuSysRegs.PCLKCR12.all = 0; + CpuSysRegs.PCLKCR13.all = 0; + CpuSysRegs.PCLKCR14.all = 0; + CpuSysRegs.PCLKCR16.all = 0; + + EDIS; +} + +// +// InitFlash - This function initializes the Flash Control registers. +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void InitFlash(void) +{ + EALLOW; + + // + // The default value of VREADST is good enough for the flash to power up + // properly at the INTOSC frequency. Below VREADST configuration covers up + // to the max frequency possible for this device. This is required for + // proper flash wake up at the higher frequencies if users put it to sleep + // for power saving reason. + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // At reset bank and pump are in sleep. A Flash access will power up the + // bank and pump automatically. + // + // After a Flash access, bank and pump go to low power mode (configurable + // in FBFALLBACK/FPAC1 registers) if there is no further access to flash. + // + // Power up Flash bank and pump. This also sets the fall back mode of + // flash and pump as active. + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; + + // + // Disable Cache and prefetch mechanism before changing wait states + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; + + // + // Set waitstates according to frequency + // + // *CAUTION* + // Minimum waitstates required for the flash operating at a given CPU rate + // must be characterized by TI. Refer to the datasheet for the latest + // information. + // + #if CPU_FRQ_200MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; + #endif + + #if CPU_FRQ_150MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + #if CPU_FRQ_120MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + // + // Enable Cache and prefetch mechanism to improve performance of code + // executed from Flash. + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; + + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// FlashOff - This function powers down the flash +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. Also you must seize the flash pump in +// order to power it down. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void FlashOff(void) +{ + EALLOW; + + // + // Set VREADST to the proper value for the flash banks to power up properly + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // Power down bank + // + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; + + // + // Power down pump + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; + + EDIS; +} + +// +// SeizeFlashPump - Wait until the flash pump is available. Then take control +// of it using the flash pump Semaphore. +// +void SeizeFlashPump(void) +{ + EALLOW; + #ifdef CPU1 + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x2) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x2; + } + #elif defined(CPU2) + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x1) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x1; + } + #endif + EDIS; +} + +// +// ReleaseFlashPump - Release control of the flash pump using the flash pump +// semaphore. +// +void ReleaseFlashPump(void) +{ + EALLOW; + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0; + EDIS; +} + +// +// ServiceDog - This function resets the watchdog timer. +// +// Enable this function for using ServiceDog in the application. +// +void ServiceDog(void) +{ + EALLOW; + WdRegs.WDKEY.bit.WDKEY = 0x0055; + WdRegs.WDKEY.bit.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void DisableDog(void) +{ + volatile Uint16 temp; + + // + // Grab the clock config first so we don't clobber it + // + EALLOW; + temp = WdRegs.WDCR.all & 0x0007; + WdRegs.WDCR.all = 0x0068 | temp; + EDIS; +} + +#ifdef CPU1 +// +// InitSysPll() +// This function initializes the PLL registers. +// Note: +// - The internal oscillator CANNOT be used as the PLL source if the +// PLLSYSCLK is configured to frequencies above 194 MHz. +// +// - This function uses the Watchdog as a monitor for the PLL. The user +// watchdog settings will be modified and restored upon completion. Function +// allows for a minimum re lock attempt for 5 tries. Re lock attempt is carried +// out if either SLIP condition occurs or SYSCLK to Input Clock ratio is off by 10% +// +// - This function uses the following resources to support PLL initialization: +// o Watchdog +// o CPU Timer 1 +// o CPU Timer 2 +// +void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 SCSR, WDCR, WDWCR, intStatus, t1TCR, t1TPR, t1TPRH; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale; + Uint32 t1PRD, t2PRD, ctr1; + float sysclkToInClkError, mult, div; + bool sysclkInvalidFreq=true; + + if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) + { + switch (clock_source) + { + case INT_OSC1: + SysIntOsc1Sel(); + break; + + case INT_OSC2: + SysIntOsc2Sel(); + break; + + case XTAL_OSC: + SysXtalOscSel(); + break; + } + } + + EALLOW; + if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || + fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + Uint16 i; + + // + // This bit is reset only by POR + // + if(DevCfgRegs.SYSDBGCTL.bit.BIT_0 == 1) + { + // + // The user can optionally insert handler code here. This will only + // be executed if a watchdog reset occurred after a failed system + // PLL initialization. See your device user's guide for more + // information. + // + // If the application has a watchdog reset handler, this bit should + // be checked to determine if the watchdog reset occurred because + // of the PLL. + // + // No action here will continue with retrying the PLL as normal. + // + // Failed PLL initialization is due to any of the following: + // - No PLL clock + // - SLIP condition + // - Wrong Frequency + // + } + + // + // Bypass PLL and set dividers to /1 + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase this + // number according to allotted system initialization time. + // + for(i = 0; i < 5; i++) + { + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + } + } + + // + // Set divider to produce slower output frequency to limit current increase + // + if(divsel != PLLCLK_BY_126) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the PLL + // startup sequence. If your application has already cleared the watchdog + // SCRS[WDOVERRIDE] bit this cannot be done. It is recommended not to clear + // this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + SCSR = WdRegs.SCSR.all; + WDCR = WdRegs.WDCR.all; + WDWCR = WdRegs.WDWCR.all; + + // + // Disable windowed functionality, reset counter + // + EALLOW; + WdRegs.WDWCR.all = 0x0; + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + WdRegs.SCSR.all = 0x0; + WdRegs.WDCR.all = 0x28; + + // + // This bit is reset only by power-on-reset (POR) and will not be cleared + // by a WD reset + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 1; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL prior to clearing status bit + // + asm(" RPT #20 || NOP"); + + // + // Service watchdog + // + ServiceDog(); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer counts + // are off by +/- 10%. + // At a minimum, SYSCLK check is performed. Re lock attempt is carried out + // if SLIPS bit is set. This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will be + // aborted by watchdog reset. + // + EALLOW; + while(sysclkInvalidFreq == true) + { + if(ClkCfgRegs.SYSPLLSTS.bit.SLIPS == 1) + { + // + // Bypass PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multipliers, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter to expire + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1); + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL + // + asm(" RPT #20 || NOP"); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = CpuTimer1Regs.TCR.all; + t1PRD = CpuTimer1Regs.PRD.all; + t1TPR = CpuTimer1Regs.TPR.all; + t1TPRH = CpuTimer1Regs.TPRH.all; + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer1Regs.PRD.all = TMR1SYSCLKCTR; // seed timer1 counter + CpuTimer1Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + CpuTimer1Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer1Regs.TCR.bit.TIE = 1; // enable interrupt + + // + // Configure timer2 to count Input clock cycles + // + switch(clock_source) + { + case INT_OSC1: + // Clk Src = INT_OSC1 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x1; + break; + case INT_OSC2: + // Clk Src = INT_OSC2 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x2; + break; + case XTAL_OSC: + // Clk Src = XTAL + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x3; + break; + + } + CpuTimer2Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer2Regs.TCR.bit.TIE = 1; // enable interrupt + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer2Regs.PRD.all = TMR2INPCLKCTR; // seed timer2 counter + CpuTimer2Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + + // + // Stop/Start timer counters + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer1 with value in PRD + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer2 with value in PRD + CpuTimer2Regs.TCR.bit.TIF = 1; // clear timer2 interrupt flag + CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2 + CpuTimer1Regs.TCR.bit.TSS = 0; // start timer1 + + // + // Stop timers if either timer1 or timer2 counters overflow + // + while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); + + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + + // + // Calculate elapsed counts on timer1 + // + ctr1 = TMR1SYSCLKCTR - CpuTimer1Regs.TIM.all; + + // + // Restore timer settings + // + CpuTimer1Regs.TCR.all = t1TCR; + CpuTimer1Regs.PRD.all = t1PRD; + CpuTimer1Regs.TPR.all = t1TPR; + CpuTimer1Regs.TPRH.all = t1TPRH; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float)(imult) + (float)(fmult)/4; + div = (float)((!ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV) ? 1 : (ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV << 1)); + + sysclkToInClkError = (mult/div) - ((float)ctr1/(float)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10) || (sysclkToInClkError < -0.10)); + } + + // + // Clear bit + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 0; + + // + // Restore user watchdog, first resetting counter + // + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + WDCR |= 0x28; // Setup WD key--KEY bits always read 0 + WdRegs.WDCR.all = WDCR; + WdRegs.WDWCR.all = WDWCR; + WdRegs.SCSR.all = SCSR & 0xFFFE; // Mask write to bit 0 (W1toClr) + + // + // Restore state of ST1[INTM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x1)) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x2)) + { + asm(" CLRC DBGM"); + } + + // + // 200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + asm(" RPT #200 || NOP"); + + // + // Set the divider to user value + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + + EDIS; +} +#endif // CPU1 + +// +// InitAuxPll - This function initializes the AUXPLL registers. +// +// Note: For this function to properly detect PLL startup, +// SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +// +// This function will use CPU Timer 2 to monitor a successful lock of the +// AUXPLL. +// +void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 i; + Uint16 counter = 0; + Uint16 started = 0; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale, attempts; + Uint32 t2PRD; + + if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && + (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.AUXPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + switch (clock_source) + { + case INT_OSC2: + AuxIntOsc2Sel(); + break; + + case XTAL_OSC: + AuxXtalOscSel(); + break; + + case AUXCLKIN: + AuxAuxClkSel(); + break; + } + + // + // Backup Timer 2 settings + // + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // + EALLOW; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x6; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = 0x0; // Divide by 1 + + CpuTimer2Regs.TCR.bit.TSS = 1; // Stop timer + CpuTimer2Regs.PRD.all = 10; // Small PRD value to detect overflow + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + CpuTimer2Regs.TCR.bit.TIE = 0; // Disable timer interrupts + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK/2 while using + // Timer 2 + // + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 0x3; + EDIS; + + while((counter < 5) && (started == 0)) + { + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL + asm(" RPT #20 || NOP"); // Small delay for power down + + // + // Set integer and fractional multiplier, which automatically turns on + // the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Enable AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + + // + // Enable AUXPLLCLK to be fed from AUX PLL + // + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. This is + // used to test that the PLL has successfully started. + // + CpuTimer2Regs.TCR.bit.TRB = 1; // Reload period value + CpuTimer2Regs.TCR.bit.TSS = 0; // Start Timer + + // + // Check to see timer is counting properly + // + for(i = 0; i < 1000; i++) + { + // + // Check overflow flag + // + if(CpuTimer2Regs.TCR.bit.TIF) + { + // + // Clear overflow flag + // + CpuTimer2Regs.TCR.bit.TIF = 1; + + // + // Set flag to indicate PLL started and break out of for-loop + // + started = 1; + break; + } + } + + // + // Stop timer + // + CpuTimer2Regs.TCR.bit.TSS = 1; + counter++; + EDIS; + } + + if(started == 0) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). + // + EALLOW; + ClkCfgRegs.AUXPLLMULT.all = 0; + EDIS; + + // + // The user should put some handler code here based on how this + // condition should be handled in their application. + // + asm(" ESTOP0"); + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + attempts = 0; + while(ClkCfgRegs.AUXPLLSTS.bit.SLIPS && (attempts < 10)) + { + EALLOW; + // + // Bypass AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + + // + // Turn off AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1); + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + attempts++; + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; + + // + // Restore Timer 2 configuration + // + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Reload period value + // + CpuTimer2Regs.TCR.bit.TRB = 1; + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +Uint16 CsmUnlock(void) +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; + + DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; + EDIS; + + return(0); +} + +// +// SysIntOsc1Sel - This function switches to Internal Oscillator 1. +// +void SysIntOsc1Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysIntOsc2Sel - This function switches to Internal oscillator 2. +// +void SysIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void SysXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxIntOsc2Sel - This function switches to Internal oscillator 2. +// +void AuxIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// AuxXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void AuxXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxAUXCLKOscSel - This function switches to AUXCLKIN (from a GPIO). +// +void AuxAuxClkSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL + EDIS; +} + +// +// IDLE - Enter IDLE mode (single CPU). +// +void IDLE(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; + EDIS; + asm(" IDLE"); +} + +// +// STANDBY - Enter STANDBY mode (single CPU). +// +void STANDBY(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; + EDIS; + asm(" IDLE"); +} + +// +// HALT - Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +// +void HALT(void) +{ +#if defined(CPU2) + IDLE(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; + EDIS; + + while(DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT != 0x1); + + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + +// +// HIB - Enter HIB mode (dual CPU). Puts CPU2 in STANDBY first. Alternately, +// CPU2 may be in reset. +void HIB(void) +{ +#if defined(CPU2) + STANDBY(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HIB; + EDIS; + + while((DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT == 0x0) && + (DevCfgRegs.RSTSTAT.bit.CPU2RES == 1)); + + DisablePeripheralClocks(); + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c new file mode 100644 index 0000000000..ffc70fec07 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: F2837xD_TempSensorConv.c +// +// TITLE: F2837xD Temperature Sensor Conversion Functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Defines +// +#define FP_SCALE 32768 //Scale factor for Q15 fixed point numbers (2^15) +#define FP_ROUND FP_SCALE/2 //Added to Q15 numbers before converting to + //integer to round the number. +#define KELVIN 273 // Amount to add to Q15 fixed point numbers + // to shift from Celsius to Kelvin + // (Converting guarantees number is + // positive, which makes rounding more + // efficient) +#define KELVIN_OFF FP_SCALE*KELVIN +#define getTempSlope() (*(int (*)(void))0x7036E)() //Slope of temperature sensor + //(deg. C / ADC code). + //Stored in fixed point Q15 + //format. +#define getTempOffset() (*(int (*)(void))0x70372)() //ADC code corresponding to + //temperature sensor output + //at 0 deg. C + +// +// Globals +// +float32 tempSensor_tempSlope; +float32 tempSensor_tempOffset; +float32 tempSensor_scaleFactor; + +// +// InitTempSensor - Initialize the temperature sensor by powering up the +// sensor, loading the calibration values from OTP to RAM, +// and recording the intended VREFHI voltage. +// Note: This function doesn't support VREFLO != 0.0V, +// but this could be implemented if desired. +// +void InitTempSensor(float32 vrefhi_voltage) +{ + EALLOW; + + // + //power up the the temperature sensor + // + AnalogSubsysRegs.TSNSCTL.bit.ENABLE = 1; + + // + //delay to allow the sensor to power up + // + DELAY_US(1000); + + EDIS; + + // + //need to remember VREFHI voltage so that sensor readings can be scaled + //to match 2.5V values used for calibration data. + // + tempSensor_scaleFactor = vrefhi_voltage; + + // + //check the device revision + // + if(DevCfgRegs.REVID >= 3) + { + // + //for production devices (Rev. C), pull the slope and offset from OTP + // + tempSensor_tempSlope = (int32)getTempSlope(); + tempSensor_tempOffset = getTempOffset(); + } + else + { + // + //for pre-production devices, use these static values for slope + //and offset + // + tempSensor_tempSlope = 5196; + tempSensor_tempOffset = 1788; + } +} + +// +// GetTemperatureC - This function uses the reference data stored in OTP to +// convert the raw temperature sensor reading into degrees C +// +int16 GetTemperatureC(int16 sensorSample) +{ + sensorSample = (int16)((tempSensor_scaleFactor/2.5)*(sensorSample)); + + return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + + FP_ROUND + KELVIN_OFF)/FP_SCALE - KELVIN); +} + +// +// GetTemperatureK - This function uses the reference data stored in OTP to +// convert the raw temperature sensor reading into degrees K +// +int16 GetTemperatureK(int16 sensorSample) +{ + sensorSample = (int16)((2.5/tempSensor_scaleFactor)*(sensorSample)); + + return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + + FP_ROUND + KELVIN_OFF)/FP_SCALE); +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c new file mode 100644 index 0000000000..f0432c9c8d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: F2837xD_Upp.c +// +// TITLE: F2837xD Upp Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitUpp1Gpio - Initialize UPP1 GPIOs +// +void InitUpp1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (uPP_WAIT) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (uPP_START) + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (uPP_ENA) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (uPP_D7) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (uPP_D6) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (uPP_D5) + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (uPP_D4) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (uPP_D3) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (uPP_D2) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (uPP_D1) + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (uPP_D0) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (uPP_CLK) + + // + // Disable QUAL for selected pins (ASYNC Input) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Disable pull-up on GPIO10 (uPP_WAIT) + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Disable pull-up on GPIO11 (uPP_START) + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Disable pull-up on GPIO12 (uPP_ENA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Disable pull-up on GPIO13 (uPP_D7) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Disable pull-up on GPIO14 (uPP_D6) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Disable pull-up on GPIO15 (uPP_D5) + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Disable pull-up on GPIO16 (uPP_D4) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Disable pull-up on GPIO17 (uPP_D3) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Disable pull-up on GPIO18 (uPP_D2) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Disable pull-up on GPIO19 (uPP_D1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Disable pull-up on GPIO20 (uPP_D0) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Disable pull-up on GPIO21 (uPP_CLK) + + // + // Configure uPP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM1 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT + GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START + GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA + GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 + GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 + GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 + GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 + GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 + GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 + GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 + GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 + GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK + + EDIS; +} + +// +// SoftResetUpp - Trigger an internal uPP reset +// +void SoftResetUpp(void) +{ + UppRegs.PERCTL.bit.SOFTRST = 1; // Issue uPP Internal Reset. + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + UppRegs.PERCTL.bit.SOFTRST = 0; // Release uPP Internal Reset. +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c new file mode 100644 index 0000000000..3b3cb24bea --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c @@ -0,0 +1,131 @@ +//########################################################################### +// +// FILE: F2837xD_can.c +// +// TITLE: F2837xD CAN Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitCAN - Initializes the CAN-A controller after reset. +// +void InitCAN(void) +{ + int16_t iMsg; + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + CanaRegs.CAN_CTL.bit.Init = 1; + CanaRegs.CAN_CTL.bit.SWR = 1; + + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF1CMD.bit.Busy) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + // + CanaRegs.CAN_IF1CMD.bit.DIR = 1; + CanaRegs.CAN_IF1CMD.bit.Arb = 1; + CanaRegs.CAN_IF1CMD.bit.Control = 1; + + CanaRegs.CAN_IF1ARB.all = 0; + + CanaRegs.CAN_IF1MCTL.all = 0; + + CanaRegs.CAN_IF2CMD.bit.DIR = 1; + CanaRegs.CAN_IF2CMD.bit.Arb = 1; + CanaRegs.CAN_IF2CMD.bit.Control = 1; + + CanaRegs.CAN_IF2ARB.all = 0; + + CanaRegs.CAN_IF2MCTL.all = 0; + + // + // Loop through to program all 32 message objects + // + for(iMsg = 1; iMsg <= 32; iMsg+=2) + { + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF1CMD.bit.Busy) + { + } + + // + // Initiate programming the message object + // + CanaRegs.CAN_IF1CMD.bit.MSG_NUM = iMsg; + + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF2CMD.bit.Busy) + { + } + + // + // Initiate programming the message object + // + CanaRegs.CAN_IF2CMD.bit.MSG_NUM = iMsg + 1; + } + + // + // Acknowledge any pending status interrupts. + // + volatile uint32_t discardRead = CanaRegs.CAN_ES.all; + +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c new file mode 100644 index 0000000000..28c676c18d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c @@ -0,0 +1,185 @@ +//############################################################################# +// +// File: F2837xD_sci_io.c +// +// Description: Contains the various functions related to the serial +// communications interface (SCI) object +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include +#include +#include "F28x_Project.h" +#include "F2837xD_sci_io.h" + +// +// Globals +// +uint16_t deviceOpen = 0; + +// +// SCI_open - Initialize and setup SCI +// +int SCI_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpen) + { + return (-1); + } + else + { + EALLOW; + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x2044; + SciaRegs.SCIFFCT.all=0x0; + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + + SciaRegs.SCIHBAUD.bit.BAUD =0x0000; // 9600 baud @LSPCLK = 10MHz + //(40 MHz SYSCLK). + SciaRegs.SCILBAUD.bit.BAUD =0x0081; + + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + EDIS; + + deviceOpen = 1; + return (1); + } +} + +// +// SCI_close - Set SCI to closed +// +int SCI_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpen)) + { + return (-1); + } + else + { + deviceOpen = 0; + return (0); + } +} + +// +// SCI_read - Read from the SCI RX buffer +// +int SCI_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = SciaRegs.SCIRXBUF.bit.SAR; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - Write to the SCI TX buffer +// +int SCI_write(int dev_fd, char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(SciaRegs.SCICTL2.bit.TXRDY != 1) + { + } + SciaRegs.SCITXBUF.bit.TXDT = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - Do nothing +// +off_t SCI_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - Do nothing +// +int SCI_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - Do nothing +// +int SCI_rename(const char * old_name, const char * new_name) +{ + return (0); +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c new file mode 100644 index 0000000000..4bbfdf5890 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c @@ -0,0 +1,554 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_drivers.c +// +// TITLE: SDFM Driver functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F28x_Project.h" +#include "F2837xD_struct.h" +#include "F2837xD_sdfm_drivers.h" + +// +// Sdfm_configureInputCtrl - This function configures SDFM Input control unit. +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER4) needs to be +// configured. +// mode - This parameter is used to select +// one of the modes mentioned above +// +// Input control unit can be configured in four different modes: +// MODE_0 : Modulator clock rate = Modulator data rate +// MODE_1 : Modulator clock rate = (Modulator data rate / 2) +// MODE_2 : Manchester encoded data (Modulator clock is encoded into data) +// MODE_3 : Modulator clock rate = (2 x Modulator data rate) +// +void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 mode) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: + (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode; + break; + + case FILTER2: + (*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode; + break; + + case FILTER3: + (*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode; + break; + + case FILTER4: + (*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode; + break; + } + + EDIS; +} + +// +// Sdfm_configureComparator - This function configures SDFM Comparator unit. +// Comparator unit can be configured to monitor +// input conditions with a fast settling time. +// This module can be programmed to detect over and +// under value conditions. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER3) +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1,SINC2,SINC3,SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio for +// comparator +// HLT - This parameter is used to +// configure to detect over value +// condition +// LLT - This parameter is used to +// configure to detect under value +// condition +// +void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 filterType, Uint16 OSR, Uint16 HLT, + Uint16 LLT) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: //Filter 1 + + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH1.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL1.bit.LLT = LLT; + break; + + case FILTER2: //Filter 2 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH2.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL2.bit.LLT = LLT; + break; + + case FILTER3: //Filter 3 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH3.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL3.bit.LLT = LLT; + break; + + case FILTER4: //Filter 4 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType; + + // + //Configure Comparator OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH4.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL4.bit.LLT = LLT; + break; + } + + EDIS; +} + + +// +// SDFM_configureData_filter - This function configures SDFM Data filter unit +// +// SDFM Data filter unit can be configured in any +// of four different Sinc filter types: +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// Filter_switch - This parameter is used to +// enable/disable a filter +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1 / SINC2 / SINC3 / +// SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio +// for Data filter (Upto OSR_256) +// DR_switch - This parameter selects whether +// data is represented in 16 (or) +// 32 bits +// shift_bits - When user chooses 16 bit +// representation, this variable +// allows to right shift by +// specific number of bits +// +void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits) +{ + EALLOW; + + switch(filterNumber) + { + + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + //DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits; + } + + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits; + } + + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits; + } + + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits; + } + + break; + } + + EDIS; +} + +// +// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit. +// SDFM Interrupt unit can be configured to +// enable/disable different sources of SDFM +// interrupts which should trigger CPU interrupt. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// IEH_Switch - This parameter allows over value +// condition to trigger CPU interrupt +// IEL_Switch - This parameter allows under value +// condition to trigger CPU interrupt +// MFIE_Switch - This parameter allows modulator +// failure to trigger CPU interrupt +// AE_Switch - This parameter allows new filter +// data acknowledge interrupt signal +// to trigger CPU interrupt +// +void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch) +{ + EALLOW; + + switch(filterNumber) + { + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDCPARM1.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch; + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDCPARM2.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch; + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDCPARM3.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch; + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDCPARM4.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch; + break; + } + + EDIS; +} + + +// +// SDFM_configExternalreset - This function configures SDFM module to +// enable/disable external filter reset from PWM +// +// sdfmNumber - This parameter should +// be used to select +// SDFM1 (or) SDFM2 +// filter1_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter1 +// filter2_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter2 +// filter3_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter3 +// filter4_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter4 +// +void Sdfm_configureExternalreset(Uint16 sdfmNumber, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset; + EDIS; +} + +// +// SDFM_enableMFE - This function enables Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled + EDIS; +} + +// +// SDFM_disableMFE - This function disable Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void SDFM_disableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled + EDIS; +} + +// +// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMIE(Uint16 sdfmNumber) +{ + EALLOW; + // + //Enable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1; + EDIS; +} + +// +// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_disableMIE(Uint16 sdfmNumber) +{ + + EALLOW; + // + //Disable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0; + EDIS; +} + +// +// Sdfm_readFlagRegister - This function helps user read SDFM flag +// register (SDIFLG) +// +Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber) +{ + return ((*SDFM[sdfmNumber]).SDIFLG.all); +} + +// +// Sdfm_clearFlagRegister - This function helps is used to clear +// SDIFLG register +// +void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister) +{ + (*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c new file mode 100644 index 0000000000..1a306bd1d4 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c @@ -0,0 +1,100 @@ +//########################################################################### +// +// FILE: F2837xD_struct.c +// +// TITLE: F2837xD SDFM structure +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_struct.h" + +// +// Globals +// +#if defined(CPU1) +volatile struct ADC_REGS *ADC[MAX_ADC] = +{ 0, &AdcaRegs, &AdcbRegs, + &AdccRegs, &AdcdRegs }; +#endif + +volatile struct ECAP_REGS *ECAP[MAX_ECAP] = +{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs, + &ECap4Regs, &ECap5Regs, &ECap6Regs }; + +volatile struct EPWM_REGS *EPWM[MAX_EPWM] = +{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, + &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, + &EPwm10Regs, &EPwm11Regs, &EPwm12Regs }; + +volatile struct EQEP_REGS *EQEP[MAX_EQEP] = +{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs }; + +volatile struct I2C_REGS *I2C[MAX_I2C] = +{ 0, &I2caRegs }; + +volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] = +{ 0, &McbspaRegs }; + +volatile struct SCI_REGS *SCI[MAX_SCI] = +{ 0, &SciaRegs }; + +volatile struct SPI_REGS *SPI[MAX_SPI] = +{ 0, &SpiaRegs, &SpibRegs, &SpicRegs }; + +volatile struct SDFM_REGS *SDFM[MAX_SDFM] = +{ 0, &Sdfm1Regs, &Sdfm2Regs}; + +#if defined(CPU1) +volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] = +{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT, + &InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT, + &InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT, + &InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT, + &InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT, + &InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT, + &InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT +}; +#endif + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm b/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm new file mode 100644 index 0000000000..71d3606fd0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm @@ -0,0 +1,105 @@ +;//########################################################################### +;// +;// FILE: F2837xD_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// To use this function: +;// 1 - update the CPU clock speed in the F2837xD_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the F2837xD_Device.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// extern void Delay(long LoopCount); +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// Or as follows (if count is less then 16-bits): +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .def _F28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __F28x_usDelay +_F28x_usDelay: + SUB ACC,#1 + BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +; + +;// +;// End of file +;// diff --git a/bsp/tms320f28379d/libraries/common/source/device.c b/bsp/tms320f28379d/libraries/common/source/device.c new file mode 100644 index 0000000000..171d3ac8f1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/device.c @@ -0,0 +1,328 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef _FLASH + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} diff --git a/bsp/tm4c129x-dk/libraries/driverlib/usb.c b/bsp/tms320f28379d/libraries/common/source/usb.c similarity index 62% rename from bsp/tm4c129x-dk/libraries/driverlib/usb.c rename to bsp/tms320f28379d/libraries/common/source/usb.c index 839a5575ed..db82fb7a39 100644 --- a/bsp/tm4c129x-dk/libraries/driverlib/usb.c +++ b/bsp/tms320f28379d/libraries/common/source/usb.c @@ -1,41 +1,45 @@ -//***************************************************************************** -// -// usb.c - Driver for the USB Interface. -// -// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. -// Software License Agreement +//########################################################################### // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: +// FILE: usb.c // -// Redistributions of source code must retain the above copyright +// TITLE: Driver for the USB Interface. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. -// -//***************************************************************************** +// $ +//########################################################################### + //***************************************************************************** // @@ -49,13 +53,11 @@ #include "inc/hw_ints.h" #include "inc/hw_memmap.h" #include "inc/hw_types.h" -#include "inc/hw_sysctl.h" #include "inc/hw_usb.h" #include "driverlib/debug.h" #include "driverlib/interrupt.h" #include "driverlib/sysctl.h" -#include "driverlib/udma.h" -#include "driverlib/usb.h" +#include "usb.h" //***************************************************************************** // @@ -152,7 +154,6 @@ _USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, // \param ui32Base specifies the USB module base address. // \param ui32Endpoint is the endpoint index to target for this write. // \param ui32IndexedReg is the indexed register to write to. -// \param ui32Size is a value of 1 or 2 indicating the byte size of the read. // // This function is used internally to access the indexed registers for each // endpoint. The only registers that are indexed are the FIFO configuration @@ -166,7 +167,7 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32IndexedReg, uint32_t ui32Size) { uint8_t ui8Index; - uint32_t ui32Value; + uint8_t ui8Value; // // Check the arguments. @@ -194,14 +195,14 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, // // Get the value. // - ui32Value = HWREGB(ui32Base + ui32IndexedReg); + ui8Value = HWREGB(ui32Base + ui32IndexedReg); } else { // // Get the value. // - ui32Value = HWREGH(ui32Base + ui32IndexedReg); + ui8Value = HWREGH(ui32Base + ui32IndexedReg); } // @@ -212,7 +213,7 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, // // Return the register's value. // - return(ui32Value); + return(ui8Value); } //***************************************************************************** @@ -282,63 +283,6 @@ USBHostReset(uint32_t ui32Base, bool bStart) } } -//***************************************************************************** -// -//! Enables or disables USB high-speed negotiation. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bEnable specifies whether to enable or disable high-speed -//! negotiation. -//! -//! High-speed negotiations for both host and device mode are enabled when this -//! function is called with the \e bEnable parameter set to \b true. In device -//! mode this causes the device to negotiate for high speed when the -//! USB controller receives a reset from the host. In host mode, the USB host -//! enables high-speed negotiations when resetting the connected device. If -//! \e bEnable is set to \b false the controller only operates only in -//! full-speed or low-speed. -//! -//! \b Example: Enable USB high-speed mode. -//! -//! \verbatim -//! // -//! // Enable USB high-speed mode. -//! // -//! USBHighSpeed(USB0_BASE, true); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices and should only be -//! called when the USB is connected to an external ULPI PHY. Please -//! check the data sheet to determine if the USB controller can interface with -//! a ULPI PHY. -//! -//! \return None. -// -//***************************************************************************** -void -USBHighSpeed(uint32_t ui32Base, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - if(bEnable) - { - // - // Enable high speed mode negotiations in hosts or device mode. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_HSENAB; - } - else - { - // - // Enable high speed mode negotiations in hosts or device mode. - // - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_HSENAB; - } -} - //***************************************************************************** // //! Handles the USB bus resume condition. @@ -360,8 +304,6 @@ USBHighSpeed(uint32_t ui32Base, bool bEnable) //! to \b false. This action causes the controller to complete the resume //! signaling on the USB bus. //! -//! \note This function must only be called in host mode. -//! //! \return None. // //***************************************************************************** @@ -406,7 +348,7 @@ USBHostResume(uint32_t ui32Base, bool bStart) //! \note This function must only be called in host mode. //! //! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, -//! \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. +//! or \b USB_UNDEF_SPEED. // //***************************************************************************** uint32_t @@ -417,14 +359,6 @@ USBHostSpeedGet(uint32_t ui32Base) // ASSERT(ui32Base == USB0_BASE); - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE) - { - return(USB_HIGH_SPEED); - } - // // If the Full Speed device bit is set, then this is a full speed device. // @@ -449,50 +383,7 @@ USBHostSpeedGet(uint32_t ui32Base) //***************************************************************************** // -//! Returns the current speed of the USB controller in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the operating speed of the connection to the USB host -//! controller. This function returns either \b USB_HIGH_SPEED or -//! \b USB_FULL_SPEED to indicate the connection speed in device mode. -//! -//! \b Example: Get the USB connection speed. -//! -//! \verbatim -//! // -//! // Get the connection speed of the USB controller. -//! // -//! USBDevSpeedGet(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. -//! -//! \return Returns either \b USB_HIGH_SPEED or \b USB_FULL_SPEED. -// -//***************************************************************************** -uint32_t -USBDevSpeedGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE) - { - return(USB_HIGH_SPEED); - } - - return(USB_FULL_SPEED); -} - -//***************************************************************************** -// -//! Disables control interrupts on a specified USB controller. +//! Disables control interrupts on a given USB controller. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Flags specifies which control interrupts to disable. @@ -543,7 +434,7 @@ USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) //***************************************************************************** // -//! Enables control interrupts on a specified USB controller. +//! Enables control interrupts on a given USB controller. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Flags specifies which control interrupts to enable. @@ -594,7 +485,123 @@ USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) //***************************************************************************** // -//! Returns the control interrupt status on a specified USB controller. +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0; + *pui32IntStatusEP = 0; + uint32_t usbis = 0; + uint32_t rxis = 0; + uint32_t txis = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + // + // Do-While to make sure that all status registers are cleared before continuing. + // This eliminates the race condition which can cause the USB interrupt to stay high + // and never get triggered again. + // + do + { + // Get the general interrupt status. + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + // Get the transmit interrupt status. + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + // Get the receive interrupt status. + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + ui32Status |= usbis; + // Get the transmit interrupt status. + *pui32IntStatusEP |= txis; + // Get the receive interrupt status, these bits go into the second byte of + // the returned value. + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while(usbis != 0x0000 || txis != 0x0000 || rxis != 0x0000); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. //! //! \param ui32Base specifies the USB module base address. //! @@ -648,6 +655,8 @@ USBIntStatusControl(uint32_t ui32Base) // ui32Status = HWREGB(ui32Base + USB_O_IS); + //*ui32EPStatus = USBIntStatusEndpoint(ui32Base); + // // Add the power fault status. // @@ -685,7 +694,7 @@ USBIntStatusControl(uint32_t ui32Base) //***************************************************************************** // -//! Disables endpoint interrupts on a specified USB controller. +//! Disables endpoint interrupts on a given USB controller. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Flags specifies which endpoint interrupts to disable. @@ -725,7 +734,7 @@ USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) //***************************************************************************** // -//! Enables endpoint interrupts on a specified USB controller. +//! Enables endpoint interrupts on a given USB controller. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Flags specifies which endpoint interrupts to enable. @@ -763,7 +772,7 @@ USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) //***************************************************************************** // -//! Returns the endpoint interrupt status on a specified USB controller. +//! Returns the endpoint interrupt status on a given USB controller. //! //! \param ui32Base specifies the USB module base address. //! @@ -794,7 +803,7 @@ USBIntStatusEndpoint(uint32_t ui32Base) // Get the transmit interrupt status. // ui32Status = HWREGH(ui32Base + USB_O_TXIS); - ui32Status |= (HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); // // Return the combined interrupt status. @@ -804,7 +813,7 @@ USBIntStatusEndpoint(uint32_t ui32Base) //***************************************************************************** // -//! Returns the interrupt number for a specified USB module. +//! Returns the interrupt number for a given USB module. //! //! \param ui32Base is the base address of the USB module. //! @@ -818,21 +827,7 @@ USBIntStatusEndpoint(uint32_t ui32Base) static uint32_t _USBIntNumberGet(uint32_t ui32Base) { - uint32_t ui32Int; - - if(CLASS_IS_TM4C123) - { - ui32Int = INT_USB0_TM4C123; - } - else if(CLASS_IS_TM4C129) - { - ui32Int = INT_USB0_TM4C129; - } - else - { - ui32Int = 0; - } - return(ui32Int); + return(INT_USB0); } //***************************************************************************** @@ -928,13 +923,13 @@ USBIntUnregister(uint32_t ui32Base) //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint is the endpoint to access. //! -//! This function returns the status of a specified endpoint. If any of these +//! This function returns the status of a given endpoint. If any of these //! status bits must be cleared, then the USBDevEndpointStatusClear() or the //! USBHostEndpointStatusClear() functions must be called. //! //! The following are the status flags for host mode: //! -//! - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint. +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. //! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. //! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. //! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN @@ -1014,7 +1009,7 @@ USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) // Get the RX portion of the endpoint status. // ui32Status |= - ((HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << USB_RX_EPSTATUS_SHIFT); // @@ -1293,60 +1288,6 @@ USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, } } -//***************************************************************************** -// -//! Enables or disables ping tokens for an endpoint using high-speed control -//! transfers in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to enable/disable ping tokens. -//! \param bEnable specifies whether enable or disable ping tokens. -//! -//! This function configures the USB controller to either send or not send ping -//! tokens during the data and status phase of high speed control transfers. -//! The only supported value for \e ui32Endpoint is \b USB_EP_0 because all -//! control transfers are handled using this endpoint. If the \e bEnable is -//! \b true then ping tokens are enabled, if \b false then ping tokens are -//! disabled. This must be used if the controller must support -//! communications with devices that do not support ping tokens in high speed -//! mode. -//! -//! \b Example: Disable ping transactions in host mode on endpoint 0. -//! -//! \verbatim -//! // -//! // Disable ping transaction on endpoint 0. -//! // -//! USBHostEndpointPing(USB0_BASE, USB_EP_0, false); -//! \endverbatim -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0)); - - // - // Handle the endpoint 0 case separately. - // - if(bEnable) - { - HWREGB(USB0_BASE + USB_O_CSRH0) &= ~USB_CSRH0_DISPING; - } - else - { - HWREGB(USB0_BASE + USB_O_CSRH0) |= USB_CSRH0_DISPING; - } -} - //***************************************************************************** // //! Stalls the specified endpoint in device mode. @@ -1645,12 +1586,11 @@ USBDevAddrGet(uint32_t ui32Base) //! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the //! number of NAKs. //! -//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the -//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA //! controller is configured and how it is being used. See the ``Using USB -//! with the uDMA Controller'' or the ''Using the integrated USB DMA -//! Controller'' section for more information on DMA configuration depending -//! on the type of DMA that is supported by the USB controller. +//! with the uDMA Controller'' section for more information on DMA +//! configuration. //! //! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit //! is specified to cause the transmission of data on the USB bus to start @@ -1665,13 +1605,6 @@ USBDevAddrGet(uint32_t ui32Base) //! not used, this flag must be manually cleared via a call to //! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). //! -//! For interrupt endpoints in low or full speed mode, the polling interval -//! (\e ui32NAKPollInterval) is the number of frames between interrupt IN -//! requests to an endpoint and has a range of 1 to 255. For interrupt -//! endpoints in high speed mode the polling interval is -//! 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests -//! to an endpoint and has a range of 1 to 16. -//! //! \note This function must only be called in host mode. //! //! \return None. @@ -1708,21 +1641,9 @@ USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, // // Set the transfer type information. // - // - // Set the speed of this endpoint. - // - if(ui32Flags & USB_EP_SPEED_HIGH) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH; - } - else if(ui32Flags & USB_EP_SPEED_FULL) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; - } - else - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; - } + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); } else { @@ -1734,11 +1655,7 @@ USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, // // Set the speed for the device using this endpoint. // - if(ui32Flags & USB_EP_SPEED_HIGH) - { - ui32Register |= USB_TXTYPE1_SPEED_HIGH; - } - else if(ui32Flags & USB_EP_SPEED_FULL) + if(ui32Flags & USB_EP_SPEED_FULL) { ui32Register |= USB_TXTYPE1_SPEED_FULL; } @@ -1907,99 +1824,6 @@ USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, } } -//***************************************************************************** -// -//! Changes the speed of the connection for a host endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags are used to configure other endpoint settings. -//! -//! This function sets the USB speed for an IN or OUT endpoint in host mode. -//! The \e ui32Flags parameter specifies the speed using one of the following -//! values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH. -//! The \e ui32Flags parameter also specifies which direction is set by -//! adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT. -//! All other flags are ignored. This function is typically only used for -//! endpoint 0, but could be used with other endpoints as well. -//! -//! \b Example: Set host transactions on endpoint 0 to full speed.. -//! -//! \verbatim -//! // -//! // Set host endpoint 0 transactions to full speed. -//! // -//! USBHostEndpointSpeed(USB0_BASE, USB_EP_0, USB_EP_SPEED_FULL); -//! \endverbatim -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - uint32_t ui32Reg; - uint32_t ui32Speed; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Create the register speed value. - // - if(ui32Flags & USB_EP_SPEED_HIGH) - { - ui32Speed = USB_TYPE0_SPEED_HIGH; - } - else if(ui32Flags & USB_EP_SPEED_FULL) - { - ui32Speed = USB_TYPE0_SPEED_FULL; - } - else - { - ui32Speed = USB_TYPE0_SPEED_LOW; - } - - // - // Endpoint 0 is handled differently as it is bi-directional. - // - if(ui32Endpoint == USB_EP_0) - { - HWREGB(ui32Base + USB_O_TYPE0) = ui32Speed; - } - else if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Clear the current speed and set the new speed. - // - ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) & - ~(USB_TXTYPE1_SPEED_M)); - ui32Reg |= ui32Speed; - - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) |= ui32Reg; - } - else - { - // - // Clear the current speed and set the new speed. - // - ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) & - ~(USB_RXTYPE1_SPEED_M)); - ui32Reg |= ui32Speed; - - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) |= ui32Reg; - } -} - //***************************************************************************** // //! Sets the configuration for an endpoint. @@ -2015,7 +1839,7 @@ USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, //! determines some of the configuration while the other parameters provide the //! rest. //! -//! The \b USB_EP_MODE_ flags define what the type is for the specified endpoint. +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. //! //! - \b USB_EP_MODE_CTRL is a control endpoint. //! - \b USB_EP_MODE_ISOC is an isochronous endpoint. @@ -2025,16 +1849,14 @@ USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, //! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the //! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA //! controller is configured and how it is being used. See the ``Using USB -//! with the uDMA Controller'' or the ''Using the integrated USB DMA -//! Controller'' section for more information on DMA configuration depending -//! on the type of DMA that is supported by the USB controller. +//! with the uDMA Controller'' section for more information on DMA +//! configuration. //! //! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be //! specified to cause the automatic transmission of data on the USB bus as //! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for -//! this endpoint. This option is commonly used with DMA (both on devices -//! with integrated USB DMA as well as those that use uDMA) as no interaction -//! is required to start the transmission of data. +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. //! //! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is //! specified to trigger the request for more data once the FIFO has been @@ -2043,7 +1865,7 @@ USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, //! data packet ready flag automatically once the data has been read from the //! FIFO. If this option is not used, this flag must be manually cleared via a //! call to USBDevEndpointStatusClear(). Both of these settings can be used to -//! remove the need for extra calls when using the controller with DMA. +//! remove the need for extra calls when using the controller in DMA mode. //! //! \note This function must only be called in device mode. //! @@ -2156,15 +1978,6 @@ USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, ui32Register |= USB_RXCSRH1_DMAEN; } - // - // If requested, disable NYET responses for high-speed bulk and - // interrupt endpoints. - // - if(ui32Flags & USB_EP_DIS_NYET) - { - ui32Register |= USB_RXCSRH1_DISNYET; - } - // // Enable isochronous mode if requested. // @@ -2369,12 +2182,12 @@ USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, //! \param ui32Endpoint is the endpoint to access. //! \param ui32FIFOAddress is the starting address for the FIFO. //! \param ui32FIFOSize is the size of the FIFO specified by one of the -//! \b USB_FIFO_SZ_ values. +//! USB_FIFO_SZ_ values. //! \param ui32Flags specifies what information to set in the FIFO //! configuration. //! //! This function configures the starting FIFO RAM address and size of the FIFO -//! for a specified endpoint. Endpoint zero does not have a dynamically +//! for a given endpoint. Endpoint zero does not have a dynamically //! configurable FIFO, so this function must not be called for endpoint zero. //! The \e ui32FIFOSize parameter must be one of the values in the //! \b USB_FIFO_SZ_ values. @@ -2437,12 +2250,12 @@ USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, //! \param ui32Endpoint is the endpoint to access. //! \param pui32FIFOAddress is the starting address for the FIFO. //! \param pui32FIFOSize is the size of the FIFO as specified by one of the -//! \b USB_FIFO_SZ_ values. +//! USB_FIFO_SZ_ values. //! \param ui32Flags specifies what information to retrieve from the FIFO //! configuration. //! //! This function returns the starting address and size of the FIFO for a -//! specified endpoint. Endpoint zero does not have a dynamically configurable +//! given endpoint. Endpoint zero does not have a dynamically configurable //! FIFO, so this function must not be called for endpoint zero. The //! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must //! be read. If in host mode, the \e ui32Flags parameter must be @@ -2502,7 +2315,7 @@ USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, //! \param ui32Endpoint is the endpoint to access. //! \param ui32Config specifies the configuration options for an endpoint. //! -//! This function configures the DMA settings for a specified endpoint without +//! This function configures the DMA settings for a given endpoint without //! changing other options that may already be configured. In order for the //! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be //! called before starting the DMA transfer. The configuration @@ -2625,14 +2438,14 @@ USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, //***************************************************************************** // -//! Enable DMA on a specified endpoint. +//! Enable DMA on a given endpoint. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint is the endpoint to access. //! \param ui32Flags specifies which direction and what mode to use when //! enabling DMA. //! -//! This function enables DMA on a specified endpoint and configures the mode +//! This function enables DMA on a given endpoint and configures the mode //! according to the values in the \e ui32Flags parameter. The \e ui32Flags //! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this //! function is called the only DMA or error interrupts are generated by the @@ -2671,13 +2484,13 @@ USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, //***************************************************************************** // -//! Disable DMA on a specified endpoint. +//! Disable DMA on a given endpoint. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint is the endpoint to access. //! \param ui32Flags specifies which direction to disable. //! -//! This function disables DMA on a specified endpoint to allow non-DMA USB +//! This function disables DMA on a given endpoint to allow non-DMA USB //! transactions to generate interrupts normally. The \e ui32Flags parameter //! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. //! @@ -2712,18 +2525,17 @@ USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, //***************************************************************************** // -//! Determines the number of bytes of data available in a specified endpoint's -//! FIFO. +//! Determine the number of bytes of data available in a given endpoint's FIFO. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint is the endpoint to access. //! //! This function returns the number of bytes of data currently available in -//! the FIFO for the specified receive (OUT) endpoint. It may be used prior to +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to //! calling USBEndpointDataGet() to determine the size of buffer required to //! hold the newly-received packet. //! -//! \return This call returns the number of bytes available in a specified endpoint +//! \return This call returns the number of bytes available in a given endpoint //! FIFO. // //***************************************************************************** @@ -2770,7 +2582,7 @@ USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) //***************************************************************************** // -//! Retrieves data from the specified endpoint's FIFO. +//! Retrieves data from the given endpoint's FIFO. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint is the endpoint to access. @@ -2780,7 +2592,7 @@ USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) //! via the \e pui8Data parameter. It is set to the amount of data returned in //! the buffer. //! -//! This function returns the data from the FIFO for the specified endpoint. +//! This function returns the data from the FIFO for the given endpoint. //! The \e pui32Size parameter indicates the size of the buffer passed in //! the \e pui32Data parameter. The data in the \e pui32Size parameter is //! changed to match the amount of data returned in the \e pui8Data parameter. @@ -2874,7 +2686,7 @@ USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, //***************************************************************************** // -//! Acknowledge that data was read from the specified endpoint's FIFO in device +//! Acknowledge that data was read from the given endpoint's FIFO in device //! mode. //! //! \param ui32Base specifies the USB module base address. @@ -2929,7 +2741,7 @@ USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, //***************************************************************************** // -//! Acknowledge that data was read from the specified endpoint's FIFO in host +//! Acknowledge that data was read from the given endpoint's FIFO in host //! mode. //! //! \param ui32Base specifies the USB module base address. @@ -2972,7 +2784,7 @@ USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) //***************************************************************************** // -//! Puts data into the specified endpoint's FIFO. +//! Puts data into the given endpoint's FIFO. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint is the endpoint to access. @@ -3053,7 +2865,7 @@ USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, //! \param ui32Endpoint is the endpoint to access. //! \param ui32TransType is set to indicate what type of data is being sent. //! -//! This function starts the transfer of data from the FIFO for a specified +//! This function starts the transfer of data from the FIFO for a given //! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was //! not enabled for the endpoint. Setting the \e ui32TransType parameter //! allows the appropriate signaling on the USB bus for the type of transaction @@ -3320,8 +3132,6 @@ USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) //! device and an interrupt is signaled when the status packet has been //! received. //! -//! \note This function must only be called in host mode. -//! //! \return None. // //***************************************************************************** @@ -3507,10 +3317,6 @@ USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, { HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; } - else if(ui32Flags & USB_EP_SPEED_HIGH) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH; - } else { HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; @@ -3612,15 +3418,13 @@ USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) //! USBOTGSessionRequest() has enabled a //! session. //! -//! When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be -//! addded to ignore small, short drops in VBUS level caused by high power -//! consumption. This feature is mainly used to avoid causing VBUS errors -//! caused by devices with high in-rush current. +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. //! //! \note This function must only be called on microcontrollers that support -//! host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and -//! \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that -//! support OTG operation. +//! host mode or OTG operation. //! //! \return None. // @@ -3765,7 +3569,7 @@ USBHostPwrDisable(uint32_t ui32Base) //***************************************************************************** // -//! Gets the current frame number. +//! Get the current frame number. //! //! \param ui32Base specifies the USB module base address. //! @@ -3825,7 +3629,7 @@ USBOTGSessionRequest(uint32_t ui32Base, bool bStart) //***************************************************************************** // -//! Returns the absolute FIFO address for a specified endpoint. +//! Returns the absolute FIFO address for a given endpoint. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint specifies which endpoint's FIFO address to return. @@ -3833,9 +3637,7 @@ USBOTGSessionRequest(uint32_t ui32Base, bool bStart) //! This function returns the actual physical address of the FIFO. This //! address is needed when the USB is going to be used with the uDMA //! controller and the source or destination address must be set to the -//! physical FIFO address for a specified endpoint. This function can also be -//! used to provide the physical address to manually read data from an -//! endpoints FIFO. +//! physical FIFO address for a given endpoint. //! //! \return None. // @@ -3861,6 +3663,9 @@ USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) //! For OTG controllers: //! //! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. //! //! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode //! on the A-side of the cable. @@ -3881,6 +3686,8 @@ USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) //! For Dual Mode controllers: //! //! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. //! //! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. //! @@ -3921,13 +3728,13 @@ USBModeGet(uint32_t ui32Base) //***************************************************************************** // -//! Sets the DMA channel to use for a specified endpoint. +//! Sets the DMA channel to use for a given endpoint. //! //! \param ui32Base specifies the USB module base address. //! \param ui32Endpoint specifies which endpoint's FIFO address to return. //! \param ui32Channel specifies which DMA channel to use for which endpoint. //! -//! This function is used to configure which DMA channel to use with a specified +//! This function is used to configure which DMA channel to use with a given //! endpoint. Receive DMA channels can only be used with receive endpoints //! and transmit DMA channels can only be used with transmit endpoints. As a //! result, the 3 receive and 3 transmit DMA channels can be mapped to any @@ -3955,13 +3762,13 @@ USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); +// ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); // // The input select mask must be shifted into the correct position // based on the channel. // - ui32Mask = 0xf << (ui32Channel * 4); + ui32Mask = (uint32_t)0xf << (ui32Channel * 4); // // Clear out the current selection for the channel. @@ -3972,7 +3779,7 @@ USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, // The input select is now shifted into the correct position based on the // channel. // - ui32Mask |= (USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); // // Write the value out to the register. @@ -3989,7 +3796,7 @@ USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, //! This function changes the mode of the USB controller to host mode. //! //! \note This function must only be called on microcontrollers that support -//! OTG operation. +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. //! //! \return None. // @@ -4020,7 +3827,7 @@ USBHostMode(uint32_t ui32Base) //! This function changes the mode of the USB controller to device mode. //! //! \note This function must only be called on microcontrollers that support -//! OTG operation. +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. //! //! \return None. // @@ -4041,7 +3848,7 @@ USBDevMode(uint32_t ui32Base) //***************************************************************************** // -//! Changes the mode of the USB controller to OTG. +//! Change the mode of the USB controller to OTG. //! //! \param ui32Base specifies the USB module base address. //! @@ -4068,72 +3875,13 @@ USBOTGMode(uint32_t ui32Base) //***************************************************************************** // -//! Change the operating mode of the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Mode specifies the operating mode of the USB OTG pins. -//! -//! This function changes the operating modes of the USB controller. When -//! operating in full OTG mode, the USB controller uses the VBUS and ID pins to -//! detect mode and voltage changes. While these pins are primarily used in -//! OTG mode, they can also affect the operation of host and device modes. In -//! device mode, the USB controller can be configured to monitor or ignore -//! VBUS. Monitoring VBUS allows the controller to determine if it has been -//! disconnected from the host. In host mode, the USB controller uses the -//! VBUS pin to detect loss of VBUS caused by excessive power draw due to a -//! drop in the VBUS voltage. This call takes the place of USBHostMode(), -//! USBDevMode(), and USBOTGMode(). The \e ui32Mode value should be one of -//! the following values: -//! -//! - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are -//! used by the controller. -//! - \b USB_MODE_HOST enables operating only as a host with no monitoring of -//! VBUS or ID pins. -//! - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of -//! VBUS pin. This configuration enables detection of VBUS droop while still -//! forcing host mode. -//! - \b USB_MODE_DEVICE enables operating only as a device with no monitoring -//! of VBUS or ID pins. -//! - \b USB_MODE_DEVICE_VBUS enables operating only as a device with -//! monitoring of VBUS pin. This configuration enables disconnect detection -//! while still forcing device mode. -//! -//! \note Some of the options above are not available on some Tiva devices. -//! Please check the data sheet to determine if the USB controller supports a -//! particular mode. -//! -//! \b Example: Force device mode but allow monitoring of the USB VBUS pin. -//! -//! \verbatim -//! // -//! // Force device mode but allow monitoring of VBUS for disconnect. -//! // -//! USBModeConfig(USB_MODE_DEVICE_VBUS); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - HWREG(ui32Base + USB_O_GPCS) = ui32Mode; -} - -//***************************************************************************** -// -//! Powers off the internal USB PHY. +//! Powers off the USB PHY. //! //! \param ui32Base specifies the USB module base address. //! -//! This function powers off the internal USB PHY, reducing the current -//! consumption of the device. While in the powered-off state, the USB -//! controller is unable to operate. +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. //! //! \return None. // @@ -4149,11 +3897,11 @@ USBPHYPowerOff(uint32_t ui32Base) //***************************************************************************** // -//! Powers on the internal USB PHY. +//! Powers on the USB PHY. //! //! \param ui32Base specifies the USB module base address. //! -//! This function powers on the internal USB PHY, enabling it return to normal +//! This function powers on the USB PHY, enabling it return to normal //! operation. By default, the PHY is powered on, so this function must //! only be called if USBPHYPowerOff() has previously been called. //! @@ -4219,1692 +3967,6 @@ USBNumEndpointsGet(uint32_t ui32Base) // Read the number of endpoints from the hardware. The number of TX and // RX endpoints are always the same. // - return(HWREGB(ui32Base + USB_O_EPINFO) & USB_EPINFO_TXEP_M); + return(15); } -//***************************************************************************** -// -//! Returns the version of the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the version number of the USB controller, which can -//! be be used to adjust for slight differences between the USB controllers in -//! the Tiva family. The values that are returned are -//! \b USB_CONTROLLER_VER_0 and \b USB_CONTROLLER_VER_1. -//! -//! \note The most significant difference between \b USB_CONTROLLER_VER_0 and -//! \b USB_CONTROLLER_VER_1 is that \b USB_CONTROLLER_VER_1 supports the USB -//! controller's own bus master DMA controller, while the -//! \b USB_CONTROLLER_VER_0 only supports using the uDMA controller with the -//! USB module. -//! -//! \b Example: Get the version of the Tiva USB controller. -//! -//! \verbatim -//! uint32_t ui32Version; -//! -//! // -//! // Retrieve the version of the Tiva USB controller. -//! // -//! ui32Version = USBControllerVersion(USB0_BASE); -//! \endverbatim -//! -//! \return This function returns one of the \b USB_CONTROLLER_VER_ values. -// -//***************************************************************************** -uint32_t -USBControllerVersion(uint32_t ui32Base) -{ - // - // Return the type field of the peripheral properties. This returns - // zero for all parts that did not have a peripheral property. - // - return(HWREG(ui32Base + USB_O_PP) & USB_PP_TYPE_M); -} - -//***************************************************************************** -// -//! Configures and enables the clocking to the USB controller's PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Div specifies the divider for the internal USB PHY clock. -//! \param ui32Flags configures the internal USB PHY clock and specifies the -//! clock source for a ULPI-connected PHY. -//! -//! This function configures and enables the USB PHY clock. In addition, for -//! systems that use a ULPI-connected external PHY, this function configures -//! the source for the PHY clock. The \e ui32Flags parameter specifies the -//! clock source with the following values: -//! -//! - \b USB_CLOCK_INTERNAL uses the internal PLL combined with the \e ui32Div -//! value to generate the USB clock that is used by the internal USB PHY. In -//! addition, when using an external ULPI-connected USB PHY, the specified -//! clock is output on the USB0CLK pin. -//! - \b USB_CLOCK_EXTERNAL specifies that USB0CLK is an input from the -//! ULPI-connected external PHY. -//! -//! The \e ui32Div parameter is used to specify a divider for the internal -//! clock if the \b USB_CLOCK_INTERNAL is specified and is ignored if -//! \b USB_CLOCK_EXTERNAL is specified. When the \b USB_CLOCK_INTERNAL is -//! specified, the \e ui32Div value must be set so that the PLL_VCO/\e ui32Div -//! results in a 60-MHz clock. -//! -//! \b Example: Enable the USB clock with a 480-MHz PLL setting. -//! -//! \verbatim -//! // -//! // Enable the USB clock using a 480-MHz PLL. -//! // (480-MHz/8 = 60-MHz) -//! // -//! USBClockEnable(USB0_BASE, 8, USB_CLOCK_INTERNAL); -//! \endverbatim -//! -//! \note The ability to configure the USB PHY clock is not available on -//! all Tiva devices. Please consult the data sheet for the Tiva -//! device that you are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, uint32_t ui32Flags) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Configure and enable the USB clock input. - // - HWREG(ui32Base + USB_O_CC) = (ui32Div - 1) | ui32Flags; -} - -//***************************************************************************** -// -//! Disables the clocking of the USB controller's PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USB PHY clock. This function should not be -//! called in applications where the USB controller is used. -//! -//! \b Example: Disable the USB PHY clock input. -//! -//! \verbatim -//! // -//! // Disable clocking of the USB controller's PHY. -//! // -//! USBClockDisable(USB0_BASE); -//! \endverbatim -//! -//! \note The ability to configure the USB PHY clock is not available on all -//! Tiva devices. Please consult the data sheet for the Tiva device -//! that you are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBClockDisable(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the USB clock input. - // - HWREG(ui32Base + USB_O_CC) = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** -//***************************************************************************** -// -//! \addtogroup usb_dma -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enable interrupts for a specified integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel interrupt to enable. -//! -//! This function enables the USB DMA channel interrupt based on the -//! \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel. Once enabled, the USBDMAChannelIntStatus() -//! function returns if a DMA channel has generated an interrupt. -//! -//! \b Example: Enable the USB DMA channel 3 interrupt. -//! -//! \verbatim -//! // -//! // Enable the USB DMA channel 3 interrupt -//! // -//! USBDMAChannelIntEnable(USB0_BASE, 3); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Enable the specified DMA channel interrupts. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= USB_DMACTL0_IE; -} - -//***************************************************************************** -// -//! Disable interrupts for a specified integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which USB DMA channel interrupt to disable. -//! -//! This function disables the USB DMA channel interrupt based on the -//! \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel. -//! -//! \b Example: Disable the USB DMA channel 3 interrupt. -//! -//! \verbatim -//! // -//! // Disable the USB DMA channel 3 interrupt -//! // -//! USBDMAChannelIntDisable(USB0_BASE, 3); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Enable the specified DMA channel interrupts. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~USB_DMACTL0_IE; -} - -//***************************************************************************** -// -//! Return the current status of the integrated USB DMA interrupts. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current bit-mapped interrupt status for all USB -//! DMA channel interrupt sources. Calling this function automatically clears -//! all currently pending USB DMA interrupts. -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \b Example: Get the pending USB DMA interrupts. -//! -//! \verbatim -//! uint32_t ui32Ints; -//! -//! // -//! // Get the pending USB DMA interrupts. -//! // -//! ui32Ints = USBDMAChannelIntStatus(USB0_BASE); -//! \endverbatim -//! -//! \return The bit-mapped interrupts for the DMA channels. -// -//***************************************************************************** -uint32_t -USBDMAChannelIntStatus(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - return(HWREG(ui32Base + USB_O_DMAINTR)); -} - -//***************************************************************************** -// -//! Enables integrated USB DMA for a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies the USB DMA channel to enable. -//! -//! This function enables the USB DMA channel passed in the \e ui32Channel -//! parameter. The \e ui32Channel value is a zero-based index of the USB DMA -//! channel. -//! -//! \b Example: Enable USB DMA channel 2. -//! -//! \verbatim -//! // -//! // Enable USB DMA channel 2. -//! // -//! USBDMAChannelEnable(2); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Enable the USB DMA channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= - USB_DMACTL0_ENABLE; -} - -//***************************************************************************** -// -//! Disables integrated USB DMA for a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies the USB DMA channel to disable. -//! -//! This function disables the USB DMA channel passed in the \e ui32Channel -//! parameter. The \e ui32Channel parameter is a zero-based index of the DMA -//! channel. -//! -//! \b Example: Disable USB DMA channel 2. -//! -//! \verbatim -//! // -//! // Disable USB DMA channel 2. -//! // -//! USBDMAChannelDisable(2); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Disable the USB DMA channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= - ~USB_DMACTL0_ENABLE; -} - -//***************************************************************************** -// -//! Assigns and configures an endpoint to a specified integrated USB DMA -//! channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to access. -//! \param ui32Endpoint is the endpoint to assign to the USB DMA channel. -//! \param ui32Config is used to specify the configuration of the USB DMA -//! channel. -//! -//! This function assigns an endpoint and configures the settings for a -//! USB DMA channel. The \e ui32Endpoint parameter is one of the -//! \b USB_EP_* values and the \e ui32Channel value is a zero-based index of -//! the DMA channel to configure. The \e ui32Config parameter is a combination -//! of the \b USB_DMA_CFG_* values using the following guidelines. -//! -//! Use one of the following to set the DMA burst mode: -//! - \b USB_DMA_CFG_BURST_NONE disables bursting. -//! - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words. -//! - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words. -//! - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words. -//! -//! Use one of the following to set the DMA mode: -//! - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is -//! being sent via DMA and triggers one completion interrupt per packet. -//! - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being -//! sent via DMA and triggers one completion interrupt per transfer. -//! -//! Use one of the following to set the direction of the transfer: -//! - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a -//! memory location. -//! - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a -//! memory location. -//! -//! The following two optional settings allow an application to immediately -//! enable the DMA transfer and/or DMA interrupts when configuring the DMA -//! channel: -//! - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so -//! that an added call to USBDMAChannelIntEnable() is not necessary. -//! - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added -//! call to USBDMAChannelEnable() is not necessary. -//! -//! \b Example: Assign channel 0 to endpoint 1 in DMA mode 0, 4 word burst, -//! enable interrupts and immediately enable the transfer. -//! -//! \verbatim -//! // -//! // Assign channel 0 to endpoint 1 in DMA mode 0, 4 word bursts, -//! // enable interrupts and immediately enable the transfer. -//! // -//! USBDMAChannelConfigSet(USB0_BASE, 0, USB_EP_1, -//! (USB_DMA_CFG_BURST_4 | USB_DMA_CFG_MODE0 | -//! USB_DMA_CFG_DIR_RX | USB_DMA_CFG_INT_EN | -//! USB_DMA_CFG_EN)); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Endpoint, uint32_t ui32Config) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - ASSERT((ui32Endpoint & ~USB_EP_7) == 0); - - // - // Reset this USB DMA channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = 0; - - // - // Set the configuration of the requested channel. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = - ui32Config | ui32Endpoint; -} - -//***************************************************************************** -// -//! Returns the current status for an integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to query. -//! -//! This function returns the current status for the USB DMA channel specified -//! by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel to query. -//! -//! \b Example: Get the current USB DMA status for channel 2. -//! -//! \verbatim -//! uint32_t ui32Status; -//! -//! // -//! // Get the current USB DMA status for channel 2. -//! // -//! ui32Status = USBDMAChannelStatus(USB0_BASE, 2); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return Returns zero or \b USB_DMACTL0_ERR if there is a pending error -//! condition on a DMA channel. -// -//***************************************************************************** -uint32_t -USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Return a non-zero value if there is a pending error condition. - // - return(HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) & - USB_DMACTL0_ERR); -} - -//***************************************************************************** -// -//! Clears the integrated USB DMA status for a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to clear. -//! \param ui32Status holds the status bits to clear. -//! -//! This function clears the USB DMA channel status for the channel specified -//! by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the USB DMA channel to query. The \e ui32Status parameter -//! specifies the status bits to clear and must be the valid values that are -//! returned from a call to the USBDMAChannelStatus() function. -//! -//! \b Example: Clear the current USB DMA status for channel 2. -//! -//! \verbatim -//! // -//! // Clear the any pending USB DMA status for channel 2. -//! // -//! USBDMAChannelStatusClear(USB0_BASE, 2, USBDMAChannelStatus(USB0_BASE, 2)); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Status) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // The only status is the error bit. - // - ui32Status &= USB_DMACTL0_ERR; - - // - // Clear the specified error condition. - // - HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~ui32Status; -} - -//***************************************************************************** -// -//! Sets the source or destination address for an integrated USB DMA transfer -//! on a specified channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to configure. -//! \param pvAddress specifies the source or destination address for the USB -//! DMA transfer. -//! -//! This function sets the source or destination address for the USB DMA -//! channel number specified in the \e ui32Channel parameter. The -//! \e ui32Channel value is a zero-based index of the USB DMA channel. The -//! \e pvAddress parameter is a source address if the transfer type for the DMA -//! channel is transmit and a destination address if the transfer type is -//! receive. -//! -//! \b Example: Set the transfer address for USB DMA channel 1. -//! -//! \verbatim -//! void *pvBuffer; -//! -//! // -//! // Set the address for USB DMA channel 1. -//! // -//! USBDMAChannelAddressSet(USB0_BASE, 1, pvBuffer); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, - void *pvAddress) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Set the DMA address. - // - HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)) = - (uint32_t)pvAddress; -} - -//***************************************************************************** -// -//! Returns the source or destination address for the specified integrated USB -//! DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies the USB DMA channel. -//! -//! This function returns the DMA address for the channel number specified -//! in the \e ui32Channel parameter. The \e ui32Channel value is a zero-based -//! index of the DMA channel to query. This function must not be used on -//! devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion() -//! function. -//! -//! \b Example: Get the transfer address for USB DMA channel 1. -//! -//! \verbatim -//! void *pvBuffer; -//! -//! // -//! // Retrieve the current DMA address for channel 1. -//! // -//! pvBuffer = USBDMAChannelAddressGet(USB0_BASE, 1); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return The current DMA address for a USB DMA channel. -// -//***************************************************************************** -void * -USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Return the current DMA address. - // - return((void *)HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel))); -} - -//***************************************************************************** -// -//! Sets the transfer count for an integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to access. -//! \param ui32Count specifies the number of bytes to transfer. -//! -//! This function sets the USB DMA transfer count in bytes for the channel -//! number specified in the \e ui32Channel parameter. The \e ui32Channel -//! value is a zero-based index of the DMA channel. -//! -//! \b Example: Set the transfer count to 512 bytes for USB DMA channel 1. -//! -//! \verbatim -//! // -//! // Set the transfer count to 512 bytes for USB DMA channel 1. -//! // -//! USBDMAChannelCountSet(USB0_BASE, 1, 512); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Channel, - uint32_t ui32Count) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Set the USB DMA count for the channel. - // - HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)) = ui32Count; -} - -//***************************************************************************** -// -//! Returns the transfer count for an integrated USB DMA channel. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Channel specifies which DMA channel to access. -//! -//! This function returns the USB DMA transfer count in bytes for the channel -//! number specified in the \e ui32Channel parameter. The \e ui32Channel value -//! is a zero-based index of the DMA channel to query. -//! -//! \b Example: Get the transfer count for USB DMA channel 1. -//! -//! \verbatim -//! uint32_t ui32Count; -//! -//! // -//! // Get the transfer count for USB DMA channel 1. -//! // -//! ui32Count = USBDMAChannelCountGet(USB0_BASE, 1); -//! \endverbatim -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return The current count for a USB DMA channel. -// -//***************************************************************************** -uint32_t -USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Channel < 8); - - // - // Return the current DMA count. - // - return(HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel))); -} - -//***************************************************************************** -// -//! Returns the available number of integrated USB DMA channels. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the total number of DMA channels available when using -//! the integrated USB DMA controller. This function returns 0 if the -//! integrated controller is not present. -//! -//! \b Example: Get the number of integrated DMA channels. -//! -//! \verbatim -//! uint32_t ui32Count; -//! -//! // -//! // Get the number of integrated DMA channels. -//! // -//! ui32Count = USBDMANumChannels(USB0_BASE); -//! \endverbatim -//! -//! \return The number of integrated USB DMA channels or zero if the -//! integrated USB DMA controller is not present. -// -//***************************************************************************** -uint32_t -USBDMANumChannels(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Return the number of DMA channels for the integrated DMA controller. - // - return(HWREG(ui32Base + USB_O_RAMINFO) >> USB_RAMINFO_DMACHAN_S); -} -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** -//***************************************************************************** -// -//! \addtogroup usb_ulpi -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Configures the USB controller's ULPI function. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Config contains the configuration options. -//! -//! This function is used to configure the USB controller's ULPI function. -//! The configuration options are set in the \e ui32Config parameter and are a -//! logical OR of the following values: -//! -//! - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS -//! signaling. -//! - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external -//! VBUS over-current condition. -//! -//! \b Example: Enable ULPI PHY with full VBUS control. -//! -//! \verbatim -//! // -//! // Enable ULPI PHY with full VBUS control. -//! // -//! USBULPIConfig(USB0_BASE, USB_ULPI_EXTVBUS | USB_ULPI_EXTVBUS_IND); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config) -{ - HWREGB(ui32Base + USB_O_ULPIVBUSCTL) = (uint8_t)ui32Config; -} - -//***************************************************************************** -// -//! Enables the USB controller's ULPI function. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function enables the USB controller's ULPI function and must be -//! called before attempting to access an external ULPI-connected USB PHY. -//! -//! \b Example: Enable ULPI function. -//! -//! \verbatim -//! // -//! // Enable ULPI function. -//! // -//! USBULPIEnable(USB0_BASE); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIEnable(uint32_t ui32Base) -{ - HWREG(ui32Base + USB_O_PC) |= USB_PC_ULPIEN; -} - -//***************************************************************************** -// -//! Disables the USB controller's ULPI function. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USB controller's ULPI function. Accesses to -//! the external ULPI-connected PHY cannot succeed after this function has been -//! called. -//! -//! \b Example: Disable ULPI function. -//! -//! \verbatim -//! // -//! // Disable ULPI function. -//! // -//! USBULPIDisable(USB0_BASE); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIDisable(uint32_t ui32Base) -{ - HWREG(ui32Base + USB_O_PC) &= ~USB_PC_ULPIEN; -} - -//***************************************************************************** -// -//! Reads a register from an external ULPI-connected USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui8Reg specifies the register address to read. -//! -//! This function reads the register address specified in the \e ui8Reg -//! parameter using the ULPI function. This function is blocking and only -//! returns when the read access completes. The function does not return if -//! there is not a ULPI-connected USB PHY present. -//! -//! \b Example: Read a register from the ULPI PHY. -//! -//! \verbatim -//! uint8_t ui8Value; -//! -//! // -//! // Read a register from the ULPI PHY register at 0x10. -//! // -//! ui8Value = USBULPIRegRead(USB0_BASE, 0x10); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The value of the requested ULPI register. -// -//***************************************************************************** -uint8_t -USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Set the register address and initiate a read access. - // - HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg; - HWREGB(ui32Base + USB_O_ULPIREGCTL) = - USB_ULPIREGCTL_RDWR | USB_ULPIREGCTL_REGACC; - - // - // Wait for the access to complete. - // - while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0) - { - } - - // - // Clear the register access complete flag. - // - HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0; - - return(HWREGB(ui32Base + USB_O_ULPIREGDATA)); -} - -//***************************************************************************** -// -//! Writes a value to a register on an external ULPI-connected USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui8Reg specifies the register address to write. -//! \param ui8Data specifies the data to write. -//! -//! This function writes the register address specified in the \e ui8Reg -//! parameter with the value specified in the \e ui8Data parameter using the -//! ULPI function. This function is blocking and only returns when the -//! write access completes. The function does not return if there is not a -//! ULPI-connected USB PHY present. -//! -//! \b Example: Write a register from the external ULPI PHY. -//! -//! \verbatim -//! // -//! // Write the ULPI PHY register at 0x10 with 0x20. -//! // -//! USBULPIRegWrite(USB0_BASE, 0x10, 0x20); -//! \endverbatim -//! -//! \note The USB ULPI feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, uint8_t ui8Data) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Set the register address and initiate a read access. - // - HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg; - HWREGB(ui32Base + USB_O_ULPIREGDATA) = ui8Data; - HWREGB(ui32Base + USB_O_ULPIREGCTL) = USB_ULPIREGCTL_REGACC; - - // - // Wait for the access to complete. - // - while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0) - { - } - - // - // Clear the register access complete flag. - // - HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** -//***************************************************************************** -// -//! \addtogroup usb_lpm -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Sends an LPM request to a device at a specified address and endpoint number. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Address is the target device address for the LPM request. -//! \param ui32Endpoint is the target endpoint for the LPM request. -//! -//! This function sends an LPM request to a connected device in host mode. -//! The \e ui32Address parameter specifies the device address and has a range -//! of values from 1 to 127. The \e ui32Endpoint parameter specifies the -//! endpoint on the device to which to send the LPM request and must be one of -//! the \b USB_EP_* values. The function returns before the LPM request is -//! sent, requiring the caller to poll the USBLPMIntStatus() function or wait -//! for an interrupt to signal completion of the LPM transaction. This -//! function must only be called after the USBHostLPMConfig() has configured -//! the LPM transaction settings. -//! -//! \b Example: Send an LPM request to the device at address 1 on endpoint 0. -//! -//! \verbatim -//! // -//! // Send an LPM request to the device at address 1 on endpoint 0. -//! // -//! USBHostLPMSend(USB0_BASE, 1, USB_EP_0); -//! \endverbatim -//! -//! \note This function must only be called in host mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, uint32_t ui32Endpoint) -{ - uint32_t ui32Reg; - - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32Address < 127); - - // - // Set the address and endpoint. - // - HWREGB(ui32Base + USB_O_LPMFADDR) = ui32Address; - - ui32Reg = HWREGH(ui32Base + USB_O_LPMATTR) & ~USB_LPMATTR_ENDPT_M; - ui32Reg |= (USBEPToIndex(ui32Endpoint) << USB_LPMATTR_ENDPT_S); - - HWREGH(ui32Base + USB_O_LPMATTR) = ui32Reg; - - // - // Send the LPM transaction. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_TXLPM; -} - -//***************************************************************************** -// -//! Sets the global configuration for all LPM requests. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32ResumeTime specifies the resume signaling duration in 75us -//! increments. -//! \param ui32Config specifies the combination of configuration options for -//! LPM transactions. -//! -//! This function sets the global configuration options for LPM transactions -//! and must be called at least once before ever calling USBHostLPMSend(). The -//! \e ui32ResumeTime specifies the length of time that the host drives resume -//! signaling on the bus in microseconds. The valid values -//! for \e ui32ResumeTime are from 50us to 1175us in 75us increments. The -//! remaining configuration is specified by the \e ui32Config parameter and -//! includes the following options: -//! -//! - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from -//! the LPM state. -//! - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included -//! in the configuration. -//! -//! \b Example: Set the LPM configuration to allow remote wake with a resume -//! duration of 500us. -//! -//! \verbatim -//! // -//! // Set the LPM configuration to allow remote wake with a resume -//! // duration of 500us. -//! // -//! USBHostLPMConfig(USB0_BASE, 500, USB_HOST_LPM_RMTWAKE | USB_HOST_LPM_L1); -//! \endverbatim -//! -//! \note This function must only be called in host mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, - uint32_t ui32Config) -{ - ASSERT(ui32Base == USB0_BASE); - ASSERT(ui32ResumeTime <= 1175); - ASSERT(ui32ResumeTime >= 50); - - // - // Set the Host Initiated Resume Duration, Remote wake and Suspend mode. - // - HWREGH(ui32Base + USB_O_LPMATTR) = - ui32Config | ((ui32ResumeTime - 50) / 75) << USB_LPMATTR_HIRD_S; -} - -//***************************************************************************** -// -//! Initiates resume signaling to wake a device from LPM suspend mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! In host mode, this function initiates resume signaling to wake a device -//! that has entered an LPM-triggered low power mode. This LPM-triggered low -//! power mode is entered when the USBHostLPMSend() is called to put a specific -//! device into a low power state. -//! -//! \b Example: Initiate resume signaling. -//! -//! \verbatim -//! // -//! // Initiate resume signaling. -//! // -//! USBHostLPMResume(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in host mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostLPMResume(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Send Resume signaling. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES; -} - -//***************************************************************************** -// -//! Initiates remote wake signaling to request the device to leave LPM -//! suspend mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function initiates remote wake signaling to request that the host -//! wake a device that has entered an LPM-triggered low power mode. -//! -//! \b Example: Initiate remote wake signaling. -//! -//! \verbatim -//! // -//! // Initiate remote wake signaling. -//! // -//! USBDevLPMRemoteWake(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMRemoteWake(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Send remote wake signaling. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES; -} - -//***************************************************************************** -// -//! Configures the USB device mode response to LPM requests. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Config is the combination of configuration options for LPM -//! transactions in device mode. -//! -//! This function sets the global configuration options for LPM -//! transactions in device mode and must be called before ever calling -//! USBDevLPMEnable() to set the configuration for LPM transactions. The -//! configuration options in device mode are specified in the \e ui32Config -//! parameter and include one of the following: -//! -//! - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM -//! transactions. -//! - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM -//! and extended transactions. -//! - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to -//! extended transactions, but not LPM transactions. -//! -//! The \e ui32Config option can also optionally include the -//! \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all -//! transactions other than an LPM transaction once the USB controller is in -//! LPM suspend mode. If this value is not included in the \e ui32Config -//! parameter, the USB controller does not respond in suspend mode. -//! -//! The USB controller does not enter LPM suspend mode until the application -//! calls the USBDevLPMEnable() function. -//! -//! \b Example: Enable LPM transactions and NAK while in LPM suspend mode. -//! -//! \verbatim -//! // -//! // Enable LPM transactions and NAK while in LPM suspend mode. -//! // -//! USBDevLPMConfig(USB0_BASE, USB_DEV_LPM_NAK | USB_DEV_LPM_EN); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Set the device LPM configuration. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Enables the USB controller to respond to LPM suspend requests. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function is used to automatically respond to an LPM sleep request from -//! the USB host controller. If there is no data pending in any transmit -//! FIFOs, then the USB controller acknowledges the packet and enters the -//! LPM L1 state and generates the \b USB_INTLPM_ACK interrupt. If the USB -//! controller has pending transmit data in at least one FIFO, then the USB -//! controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or -//! \b USB_INTLPM_NYET depending on if data is pending in receive or transmit -//! FIFOs. A call to USBDevLPMEnable() is required after every -//! LPM resume event to re-enable LPM mode. -//! -//! \b Example: Enable LPM suspend mode. -//! -//! \verbatim -//! // -//! // Enable LPM suspend mode. -//! // -//! USBDevLPMEnable(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMEnable(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Enable L1 mode on the next LPM transaction. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) |= - USB_LPMCNTRL_EN_LPMEXT | USB_LPMCNTRL_TXLPM; -} - -//***************************************************************************** -// -//! Disables the USB controller from responding to LPM suspend requests. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USB controller from responding to LPM -//! transactions. When the device enters LPM L1 mode, the USB controller -//! automatically disables responding to further LPM transactions. -//! -//! \note If LPM transactions were enabled before calling this function, then -//! an LPM request can still occur before this function returns. As a result, -//! the application must continue to handle LPM requests until this function -//! returns. -//! -//! \b Example: Disable LPM suspend mode. -//! -//! \verbatim -//! // -//! // Disable LPM suspend mode. -//! // -//! USBDevLPMDisable(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in device mode. The USB LPM feature -//! is not available on all Tiva devices. Please consult the data sheet for -//! the Tiva device that you are using to determine if this feature is -//! available. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevLPMDisable(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Disable auto entering L1 mode on LPM transactions. - // - HWREGB(ui32Base + USB_O_LPMCNTRL) &= ~USB_LPMCNTRL_TXLPM; -} - -//***************************************************************************** -// -//! Returns the current link state setting. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current link state setting for the USB -//! controller. When the controller is operating as a host, this link -//! state is sent with an LPM request. When the controller is acting -//! as a device, this link state was received by the last LPM transaction -//! whether it was acknowledged or stalled because the requested -//! LPM mode is not supported. -//! -//! \b Example: Get the link state for the last LPM transaction. -//! -//! \verbatim -//! uint32_t ui32LinkState; -//! -//! // -//! // Get the endpoint number that received the LPM request. -//! // -//! ui32LinkState = USBLPMLinkStateGet(USB0_BASE); -//! -//! // -//! // Check if this was a supported link state. -//! // -//! if(ui32LinkState == USB_HOST_LPM_L1) -//! { -//! // -//! // Handle the supported L1 link state. -//! // -//! } -//! else -//! { -//! // -//! // Handle the unsupported link state. -//! // -//! } -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The current LPM link state. -// -//***************************************************************************** -uint32_t -USBLPMLinkStateGet(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - return(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_LS_M); -} - -//***************************************************************************** -// -//! Returns the current LPM endpoint value. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current LPM endpoint value. The meaning of the -//! value depends on the mode of operation of the USB controller. When in -//! device mode, the value returned is the endpoint that received the last -//! LPM transaction. When in host mode this is the endpoint that was last -//! sent an LPM transaction, or the endpoint that is configured to be sent when -//! the LPM transaction is triggered. The value returned is in the -//! \b USB_EP_[0-7] value and a direct endpoint index. -//! -//! \b Example: Get the endpoint for the last LPM transaction. -//! -//! \verbatim -//! uint32_t ui32Endpoint; -//! -//! // -//! // Get the endpoint number that received the LPM request. -//! // -//! ui32LinkState = USBLPMEndpointGet(USB0_BASE); -//! -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. Please -//! consult the data sheet for the Tiva device that you are using to determine -//! if this feature is available. -//! -//! \return The last endpoint to receive an LPM request in device mode or the -//! endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7] -//! values. -// -//***************************************************************************** -uint32_t -USBLPMEndpointGet(uint32_t ui32Base) -{ - uint32_t ui32Endpoint; - - ASSERT(ui32Base == USB0_BASE); - - ui32Endpoint = (HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_ENDPT_M) >> - USB_LPMATTR_ENDPT_S; - - return(IndexToUSBEP(ui32Endpoint)); -} - -//***************************************************************************** -// -//! Returns if remote wake is currently enabled. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current state of the remote wake setting for host -//! or device mode operation. If the controller is acting as a host this -//! returns the current setting that is sent to devices when LPM requests are -//! sent to a device. If the controller is in device mode, this function -//! returns the state of the last LPM request sent from the host and indicates -//! if the host enabled remote wakeup. -//! -//! \b Example: Issue remote wake if remote wake is enabled. -//! -//! \verbatim -//! -//! if(USBLPMRemoteWakeEnabled(USB0_BASE)) -//! { -//! USBDevLPMRemoteWake(USB0_BASE); -//! } -//! -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The \b true if remote wake is enabled or \b false if it is not. -// -//***************************************************************************** -bool -USBLPMRemoteWakeEnabled(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - if(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_RMTWAK) - { - return(true); - } - return(false); -} - -//***************************************************************************** -// -//! Returns the current LPM interrupt status. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current LPM interrupt status for the USB -//! controller. -//! -//! The valid interrupt status bits when the USB controller is acting as a host -//! are the following: -//! -//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM -//! transaction. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout -//! occurred or there were bit errors in the response for three attempts. -//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. -//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM -//! transaction. -//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. -//! -//! The valid interrupt status bits when the USB controller is acting as a -//! device are the following: -//! -//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an -//! unsupported link state field. The transaction was stalled, but the -//! requested link state can still be read using the USBLPMLinkStateGet() -//! function. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM -//! transaction with a NYET because data was still in the transmit FIFOs. -//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and -//! is now in the LPM suspend mode. -//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction -//! with a NYET because LPM transactions are not yet enabled by a call to -//! USBDevLPMEnable(). -//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM -//! transaction. -//! -//! \note This call clears the source of all LPM status interrupts, so the -//! caller must take care to save the value returned because a subsequent call -//! to USBLPMIntStatus() does not return the previous value. -//! -//! \b Example: Get the current LPM interrupt status. -//! -//! \verbatim -//! uint32_t ui32LPMIntStatus; -//! -//! // -//! // Get the current LPM interrupt status. -//! // -//! ui32LPMIntStatus = USBLPMIntStatus(USB0_BASE); -//! -//! // -//! // Check if an LPM transaction was acknowledged. -//! // -//! if(ui32LPMIntStatus & USB_INTLPM_ACK) -//! { -//! // -//! // Handle entering LPM suspend mode. -//! // -//! ... -//! } -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return The current LPM interrupt status. -// -//***************************************************************************** -uint32_t -USBLPMIntStatus(uint32_t ui32Base) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Return the current raw interrupt status. - // - return(HWREGB(ui32Base + USB_O_LPMRIS)); -} - -//***************************************************************************** -// -//! Enables LPM interrupts. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Ints specifies which LPM interrupts to enable. -//! -//! This function enables a set of LPM interrupts so that they can trigger a -//! USB interrupt. The \e ui32Ints parameter specifies which of the -//! \b USB_INTLPM_* to enable. -//! -//! The valid interrupt status bits when the USB controller is acting as a host -//! are the following: -//! -//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM -//! transaction. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power -//! state. -//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout -//! occurred or there were bit errors in the response for three attempts. -//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. -//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM -//! transaction. -//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. -//! -//! The valid interrupt status bits when the USB controller is acting as a -//! device are the following: -//! -//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an -//! unsupported link state field. The transaction was stalled, but the -//! requested link state can still be read using the USBLPMLinkStateGet() -//! function. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM -//! transaction with a NYET because data was still in the transmit FIFOs. -//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and -//! is now in the LPM suspend mode. -//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction -//! with a NYET because LPM transactions are not yet enabled by a call to -//! USBDevLPMEnable(). -//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM -//! transaction. -//! -//! \b Example: Enable all LPM interrupt sources. -//! -//! \verbatim -//! // -//! // Enable all LPM interrupt sources. -//! // -//! USBLPMIntEnable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME | -//! USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK | -//! USB_INTLPM_NYET | USB_INTLPM_STALL); -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Enable the requested interrupts. - // - HWREGB(ui32Base + USB_O_LPMIM) |= ui32Ints; -} - -//***************************************************************************** -// -//! Disables LPM interrupts. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Ints specifies which LPM interrupts to disable. -//! -//! This function disables the LPM interrupts specified in the \e ui32Ints -//! parameter, preventing them from triggering a USB interrupt. -//! -//! The valid interrupt status bits when the USB controller is acting as a host -//! are the following: -//! -//! - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM -//! transaction. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power -//! state. -//! - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout -//! occurred or there were bit errors in the response for three attempts. -//! - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. -//! - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM -//! transaction. -//! - \b USB_INTLPM_STALL the device has stalled an LPM transaction. -//! -//! The valid interrupt status bits when the USB controller is acting as a -//! device are the following: -//! -//! - \b USB_INTLPM_ERROR an LPM transaction was received that has an -//! unsupported link state field. The transaction was stalled, but the -//! requested link state can still be read using the USBLPMLinkStateGet() -//! function. -//! - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low -//! power state. -//! - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM -//! transaction with a NYET because data was still in the transmit FIFOs. -//! - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and -//! is now in the LPM suspend mode. -//! - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction -//! with a NYET because LPM transactions are not yet enabled by a call to -//! USBDevLPMEnable(). -//! - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM -//! transaction. -//! -//! \b Example: Disable all LPM interrupt sources. -//! -//! \verbatim -//! // -//! // Disable all LPM interrupt sources. -//! // -//! USBLPMIntDisable(USB0_BASE, USB_INTLPM_ERROR | USB_INTLPM_RESUME | -//! USB_INTLPM_INCOMPLETE | USB_INTLPM_ACK | -//! USB_INTLPM_NYET | USB_INTLPM_STALL); -//! \endverbatim -//! -//! \note The USB LPM feature is not available on all Tiva devices. -//! Please consult the data sheet for the Tiva device that you -//! are using to determine if this feature is available. -//! -//! \return None. -// -//***************************************************************************** -void -USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints) -{ - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the requested interrupts. - // - HWREGB(ui32Base + USB_O_LPMIM) &= ~ui32Ints; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/bsp/tms320f28379d/libraries/common/source/usb_hal.c b/bsp/tms320f28379d/libraries/common/source/usb_hal.c new file mode 100644 index 0000000000..f73ff48a86 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/usb_hal.c @@ -0,0 +1,163 @@ +//########################################################################### +// +// FILE: usb_hal.c +// +// TITLE: Wrapper for interrupt functions and USB support pins. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_usb.h" +#include "usb_hal.h" +#include "usb.h" +#include "include/usblib.h" +#include "include/usblibpriv.h" +#include "include/device/usbdevice.h" +#include "include/host/usbhost.h" +#include "include/host/usbhostpriv.h" +#include "include/usblibpriv.h" + +//***************************************************************************** +// +//! \addtogroup c2000_specific +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enables USB related GPIOs to perform their USB function. +// +//***************************************************************************** +void USBGPIOEnable(void) +{ + EALLOW; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 1; + GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 1; + + //VBUS + GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; + //ID + GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; + + GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 3; + GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 3; + GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 3; + GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 3; + EDIS; +} + +//***************************************************************************** +// +//! Disables USB related GPIOs from performing their USB function. +// +//***************************************************************************** +void USBGPIODisable(void) +{ + EALLOW; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 0; + GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 0; + + GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 0; + GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 0; + GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 0; + GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 0; + EDIS; +} + + +//***************************************************************************** +// +//! Wrapper function to implement mS based delay for USB functions +// +//***************************************************************************** +void USBDelay(uint32_t ui32Delay) +{ + DELAY_US(ui32Delay*1000); +} + +//***************************************************************************** +// +//! Device interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** + +__interrupt void +f28x_USB0DeviceIntHandler(void) +{ + USB0DeviceIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} +//***************************************************************************** +// +//! Host interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** +__interrupt void +f28x_USB0HostIntHandler(void) +{ + USB0HostIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} + +//***************************************************************************** +// +//! Dual mode interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** +__interrupt void +f28x_USB0DualModeIntHandler(void) +{ + USB0DualModeIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} + +//***************************************************************************** +// +// Close the c2000_specific Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml new file mode 100644 index 0000000000..79dd5cc44e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml new file mode 100644 index 0000000000..bd5fa49893 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd new file mode 100644 index 0000000000..2f91325867 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd @@ -0,0 +1,287 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CLB_XBAR : origin = 0x007A40, length = 0x000040 + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + EPWM_XBAR : origin = 0x007A00, length = 0x000040 + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + + OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + ROMPREFETCH : origin = 0x05E608, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ + + DEV_CFG : origin = 0x05D000, length = 0x000180 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + INPUT_XBAR : origin = 0x007900, length = 0x000020 + XBAR : origin = 0x007920, length = 0x000020 + SYNC_SOC : origin = 0x007940, length = 0x000010 + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile : TYPE=DSECT + GROUP + { + EmuBModeVar : TYPE=DSECT + EmuBootPinsVar : TYPE=DSECT + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + ClbXbarRegsFile : > CLB_XBAR PAGE = 1 + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + InputXbarRegsFile : > INPUT_XBAR PAGE = 1 + XbarRegsFile : > XBAR PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + UppRegsFile : > UPP, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + SyncSocRegsFile : > SYNC_SOC, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd new file mode 100644 index 0000000000..189250ad3b --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd @@ -0,0 +1,255 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + DEV_CFG : origin = 0x05D000, length = 0x000200 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile : TYPE=DSECT + GROUP + { + EmuBModeVar : TYPE=DSECT + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd new file mode 100644 index 0000000000..c125c94918 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd @@ -0,0 +1,287 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CLB_XBAR : origin = 0x007A40, length = 0x000040 + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + EPWM_XBAR : origin = 0x007A00, length = 0x000040 + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + + OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + ROMPREFETCH : origin = 0x05E608, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ + + DEV_CFG : origin = 0x05D000, length = 0x000180 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + INPUT_XBAR : origin = 0x007900, length = 0x000020 + XBAR : origin = 0x007920, length = 0x000020 + SYNC_SOC : origin = 0x007940, length = 0x000010 + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile + GROUP + { + EmuBModeVar + EmuBootPinsVar + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + ClbXbarRegsFile : > CLB_XBAR PAGE = 1 + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + InputXbarRegsFile : > INPUT_XBAR PAGE = 1 + XbarRegsFile : > XBAR PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + UppRegsFile : > UPP, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + SyncSocRegsFile : > SYNC_SOC, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd new file mode 100644 index 0000000000..af9414a90d --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd @@ -0,0 +1,251 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile + GROUP + { + EmuBModeVar + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h new file mode 100644 index 0000000000..cdcee353fb --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h @@ -0,0 +1,1067 @@ +//########################################################################### +// +// FILE: F2837xD_adc.h +// +// TITLE: ADC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ADC_H__ +#define __F2837xD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCCTL1_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position + Uint16 rsvd2:4; // 6:3 Reserved + Uint16 ADCPWDNZ:1; // 7 ADC Power Down + Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel + Uint16 rsvd3:1; // 12 Reserved + Uint16 ADCBSY:1; // 13 ADC Busy + Uint16 rsvd4:2; // 15:14 Reserved +}; + +union ADCCTL1_REG { + Uint16 all; + struct ADCCTL1_BITS bit; +}; + +struct ADCCTL2_BITS { // bits description + Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 RESOLUTION:1; // 6 SOC Conversion Resolution + Uint16 SIGNALMODE:1; // 7 SOC Signaling Mode + Uint16 rsvd2:5; // 12:8 Reserved + Uint16 rsvd3:3; // 15:13 Reserved +}; + +union ADCCTL2_REG { + Uint16 all; + struct ADCCTL2_BITS bit; +}; + +struct ADCBURSTCTL_BITS { // bits description + Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select + Uint16 rsvd2:3; // 14:12 Reserved + Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable +}; + +union ADCBURSTCTL_REG { + Uint16 all; + struct ADCBURSTCTL_BITS bit; +}; + +struct ADCINTFLG_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTFLG_REG { + Uint16 all; + struct ADCINTFLG_BITS bit; +}; + +struct ADCINTFLGCLR_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTFLGCLR_REG { + Uint16 all; + struct ADCINTFLGCLR_BITS bit; +}; + +struct ADCINTOVF_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTOVF_REG { + Uint16 all; + struct ADCINTOVF_BITS bit; +}; + +struct ADCINTOVFCLR_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTOVFCLR_REG { + Uint16 all; + struct ADCINTOVFCLR_BITS bit; +}; + +struct ADCINTSEL1N2_BITS { // bits description + Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select + Uint16 rsvd1:1; // 4 Reserved + Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable + Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select + Uint16 rsvd3:1; // 12 Reserved + Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable + Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCINTSEL1N2_REG { + Uint16 all; + struct ADCINTSEL1N2_BITS bit; +}; + +struct ADCINTSEL3N4_BITS { // bits description + Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select + Uint16 rsvd1:1; // 4 Reserved + Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable + Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select + Uint16 rsvd3:1; // 12 Reserved + Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable + Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCINTSEL3N4_REG { + Uint16 all; + struct ADCINTSEL3N4_BITS bit; +}; + +struct ADCSOCPRICTL_BITS { // bits description + Uint16 SOCPRIORITY:5; // 4:0 SOC Priority + Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCSOCPRICTL_REG { + Uint16 all; + struct ADCSOCPRICTL_BITS bit; +}; + +struct ADCINTSOCSEL1_BITS { // bits description + Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select + Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select + Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select + Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select + Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select + Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select + Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select + Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select +}; + +union ADCINTSOCSEL1_REG { + Uint16 all; + struct ADCINTSOCSEL1_BITS bit; +}; + +struct ADCINTSOCSEL2_BITS { // bits description + Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select + Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select + Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select + Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select + Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select + Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select + Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select + Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select +}; + +union ADCINTSOCSEL2_REG { + Uint16 all; + struct ADCINTSOCSEL2_BITS bit; +}; + +struct ADCSOCFLG1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag + Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag + Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag + Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag + Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag + Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag + Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag + Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag + Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag + Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag + Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag + Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag + Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag + Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag + Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag + Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag +}; + +union ADCSOCFLG1_REG { + Uint16 all; + struct ADCSOCFLG1_BITS bit; +}; + +struct ADCSOCFRC1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit + Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit + Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit + Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit + Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit + Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit + Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit + Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit + Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit + Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit + Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit + Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit + Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit + Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit + Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit + Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit +}; + +union ADCSOCFRC1_REG { + Uint16 all; + struct ADCSOCFRC1_BITS bit; +}; + +struct ADCSOCOVF1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag + Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag + Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag + Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag + Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag + Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag + Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag + Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag + Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag + Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag + Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag + Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag + Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag + Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag + Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag + Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag +}; + +union ADCSOCOVF1_REG { + Uint16 all; + struct ADCSOCOVF1_BITS bit; +}; + +struct ADCSOCOVFCLR1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit + Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit + Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit + Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit + Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit + Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit + Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit + Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit + Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit + Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit + Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit + Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit + Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit + Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit + Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit + Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit +}; + +union ADCSOCOVFCLR1_REG { + Uint16 all; + struct ADCSOCOVFCLR1_BITS bit; +}; + +struct ADCSOC0CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC0 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC0CTL_REG { + Uint32 all; + struct ADCSOC0CTL_BITS bit; +}; + +struct ADCSOC1CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC1 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC1CTL_REG { + Uint32 all; + struct ADCSOC1CTL_BITS bit; +}; + +struct ADCSOC2CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC2 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC2CTL_REG { + Uint32 all; + struct ADCSOC2CTL_BITS bit; +}; + +struct ADCSOC3CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC3 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC3CTL_REG { + Uint32 all; + struct ADCSOC3CTL_BITS bit; +}; + +struct ADCSOC4CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC4 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC4CTL_REG { + Uint32 all; + struct ADCSOC4CTL_BITS bit; +}; + +struct ADCSOC5CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC5 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC5CTL_REG { + Uint32 all; + struct ADCSOC5CTL_BITS bit; +}; + +struct ADCSOC6CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC6 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC6CTL_REG { + Uint32 all; + struct ADCSOC6CTL_BITS bit; +}; + +struct ADCSOC7CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC7 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC7CTL_REG { + Uint32 all; + struct ADCSOC7CTL_BITS bit; +}; + +struct ADCSOC8CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC8 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC8CTL_REG { + Uint32 all; + struct ADCSOC8CTL_BITS bit; +}; + +struct ADCSOC9CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC9 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC9CTL_REG { + Uint32 all; + struct ADCSOC9CTL_BITS bit; +}; + +struct ADCSOC10CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC10 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC10CTL_REG { + Uint32 all; + struct ADCSOC10CTL_BITS bit; +}; + +struct ADCSOC11CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC11 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC11CTL_REG { + Uint32 all; + struct ADCSOC11CTL_BITS bit; +}; + +struct ADCSOC12CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC12 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC12CTL_REG { + Uint32 all; + struct ADCSOC12CTL_BITS bit; +}; + +struct ADCSOC13CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC13 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC13CTL_REG { + Uint32 all; + struct ADCSOC13CTL_BITS bit; +}; + +struct ADCSOC14CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC14 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC14CTL_REG { + Uint32 all; + struct ADCSOC14CTL_BITS bit; +}; + +struct ADCSOC15CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC15 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC15CTL_REG { + Uint32 all; + struct ADCSOC15CTL_BITS bit; +}; + +struct ADCEVTSTAT_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTSTAT_REG { + Uint16 all; + struct ADCEVTSTAT_BITS bit; +}; + +struct ADCEVTCLR_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTCLR_REG { + Uint16 all; + struct ADCEVTCLR_BITS bit; +}; + +struct ADCEVTSEL_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTSEL_REG { + Uint16 all; + struct ADCEVTSEL_BITS bit; +}; + +struct ADCEVTINTSEL_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTINTSEL_REG { + Uint16 all; + struct ADCEVTINTSEL_BITS bit; +}; + +struct ADCCOUNTER_BITS { // bits description + Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCCOUNTER_REG { + Uint16 all; + struct ADCCOUNTER_BITS bit; +}; + +struct ADCREV_BITS { // bits description + Uint16 TYPE:8; // 7:0 ADC Type + Uint16 REV:8; // 15:8 ADC Revision +}; + +union ADCREV_REG { + Uint16 all; + struct ADCREV_BITS bit; +}; + +struct ADCOFFTRIM_BITS { // bits description + Uint16 OFFTRIM:8; // 7:0 ADC Offset Trim + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ADCOFFTRIM_REG { + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADCPPB1CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB1CONFIG_REG { + Uint16 all; + struct ADCPPB1CONFIG_BITS bit; +}; + +struct ADCPPB1STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB1STAMP_REG { + Uint16 all; + struct ADCPPB1STAMP_BITS bit; +}; + +struct ADCPPB1OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB1OFFCAL_REG { + Uint16 all; + struct ADCPPB1OFFCAL_BITS bit; +}; + +struct ADCPPB1TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB1TRIPHI_REG { + Uint32 all; + struct ADCPPB1TRIPHI_BITS bit; +}; + +struct ADCPPB1TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp +}; + +union ADCPPB1TRIPLO_REG { + Uint32 all; + struct ADCPPB1TRIPLO_BITS bit; +}; + +struct ADCPPB2CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB2CONFIG_REG { + Uint16 all; + struct ADCPPB2CONFIG_BITS bit; +}; + +struct ADCPPB2STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB2STAMP_REG { + Uint16 all; + struct ADCPPB2STAMP_BITS bit; +}; + +struct ADCPPB2OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB2OFFCAL_REG { + Uint16 all; + struct ADCPPB2OFFCAL_BITS bit; +}; + +struct ADCPPB2TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB2TRIPHI_REG { + Uint32 all; + struct ADCPPB2TRIPHI_BITS bit; +}; + +struct ADCPPB2TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp +}; + +union ADCPPB2TRIPLO_REG { + Uint32 all; + struct ADCPPB2TRIPLO_BITS bit; +}; + +struct ADCPPB3CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB3CONFIG_REG { + Uint16 all; + struct ADCPPB3CONFIG_BITS bit; +}; + +struct ADCPPB3STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB3STAMP_REG { + Uint16 all; + struct ADCPPB3STAMP_BITS bit; +}; + +struct ADCPPB3OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB3OFFCAL_REG { + Uint16 all; + struct ADCPPB3OFFCAL_BITS bit; +}; + +struct ADCPPB3TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB3TRIPHI_REG { + Uint32 all; + struct ADCPPB3TRIPHI_BITS bit; +}; + +struct ADCPPB3TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp +}; + +union ADCPPB3TRIPLO_REG { + Uint32 all; + struct ADCPPB3TRIPLO_BITS bit; +}; + +struct ADCPPB4CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB4CONFIG_REG { + Uint16 all; + struct ADCPPB4CONFIG_BITS bit; +}; + +struct ADCPPB4STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB4STAMP_REG { + Uint16 all; + struct ADCPPB4STAMP_BITS bit; +}; + +struct ADCPPB4OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB4OFFCAL_REG { + Uint16 all; + struct ADCPPB4OFFCAL_BITS bit; +}; + +struct ADCPPB4TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB4TRIPHI_REG { + Uint32 all; + struct ADCPPB4TRIPHI_BITS bit; +}; + +struct ADCPPB4TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp +}; + +union ADCPPB4TRIPLO_REG { + Uint32 all; + struct ADCPPB4TRIPLO_BITS bit; +}; + +struct ADC_REGS { + union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register + union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register + union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register + union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register + union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register + union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register + union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register + union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register + union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register + union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register + union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register + union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register + union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register + union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register + union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register + union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register + union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register + union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register + union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register + union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register + union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register + union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register + union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register + union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register + union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register + union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register + union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register + union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register + union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register + union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register + union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register + union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register + union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register + Uint16 rsvd1; // Reserved + union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register + Uint16 rsvd2; // Reserved + union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register + Uint16 rsvd3; // Reserved + union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register + Uint16 rsvd4[2]; // Reserved + union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register + union ADCREV_REG ADCREV; // ADC Revision Register + union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register + Uint16 rsvd5[4]; // Reserved + union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register + union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register + union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register + Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register + union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register + union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register + union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register + union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register + union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register + Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register + union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register + union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register + union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register + union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register + union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register + Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register + union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register + union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register + union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register + union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register + union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register + Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register + union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register + union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register + Uint16 rsvd6[16]; // Reserved + Uint32 ADCINLTRIM1; // ADC Linearity Trim 1 Register + Uint32 ADCINLTRIM2; // ADC Linearity Trim 2 Register + Uint32 ADCINLTRIM3; // ADC Linearity Trim 3 Register + Uint32 ADCINLTRIM4; // ADC Linearity Trim 4 Register + Uint32 ADCINLTRIM5; // ADC Linearity Trim 5 Register + Uint32 ADCINLTRIM6; // ADC Linearity Trim 6 Register + Uint16 rsvd7[4]; // Reserved +}; + +struct ADCPPB1RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB1RESULT_REG { + Uint32 all; + struct ADCPPB1RESULT_BITS bit; +}; + +struct ADCPPB2RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB2RESULT_REG { + Uint32 all; + struct ADCPPB2RESULT_BITS bit; +}; + +struct ADCPPB3RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB3RESULT_REG { + Uint32 all; + struct ADCPPB3RESULT_BITS bit; +}; + +struct ADCPPB4RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB4RESULT_REG { + Uint32 all; + struct ADCPPB4RESULT_BITS bit; +}; + +struct ADC_RESULT_REGS { + Uint16 ADCRESULT0; // ADC Result 0 Register + Uint16 ADCRESULT1; // ADC Result 1 Register + Uint16 ADCRESULT2; // ADC Result 2 Register + Uint16 ADCRESULT3; // ADC Result 3 Register + Uint16 ADCRESULT4; // ADC Result 4 Register + Uint16 ADCRESULT5; // ADC Result 5 Register + Uint16 ADCRESULT6; // ADC Result 6 Register + Uint16 ADCRESULT7; // ADC Result 7 Register + Uint16 ADCRESULT8; // ADC Result 8 Register + Uint16 ADCRESULT9; // ADC Result 9 Register + Uint16 ADCRESULT10; // ADC Result 10 Register + Uint16 ADCRESULT11; // ADC Result 11 Register + Uint16 ADCRESULT12; // ADC Result 12 Register + Uint16 ADCRESULT13; // ADC Result 13 Register + Uint16 ADCRESULT14; // ADC Result 14 Register + Uint16 ADCRESULT15; // ADC Result 15 Register + union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register + union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register + union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register + union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ADC_RESULT_REGS AdcaResultRegs; +extern volatile struct ADC_RESULT_REGS AdcbResultRegs; +extern volatile struct ADC_RESULT_REGS AdccResultRegs; +extern volatile struct ADC_RESULT_REGS AdcdResultRegs; +extern volatile struct ADC_REGS AdcaRegs; +extern volatile struct ADC_REGS AdcbRegs; +extern volatile struct ADC_REGS AdccRegs; +extern volatile struct ADC_REGS AdcdRegs; +#endif +#ifdef CPU2 +extern volatile struct ADC_RESULT_REGS AdcaResultRegs; +extern volatile struct ADC_RESULT_REGS AdcbResultRegs; +extern volatile struct ADC_RESULT_REGS AdccResultRegs; +extern volatile struct ADC_RESULT_REGS AdcdResultRegs; +extern volatile struct ADC_REGS AdcaRegs; +extern volatile struct ADC_REGS AdcbRegs; +extern volatile struct ADC_REGS AdccRegs; +extern volatile struct ADC_REGS AdcdRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h new file mode 100644 index 0000000000..b116e47d77 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h @@ -0,0 +1,199 @@ +//########################################################################### +// +// FILE: F2837xD_analogsubsys.h +// +// TITLE: ANALOGSUBSYS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ANALOGSUBSYS_H__ +#define __F2837xD_ANALOGSUBSYS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ANALOGSUBSYS Individual Register Bit Definitions: + +struct INTOSC1TRIM_BITS { // bits description + Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:8; // 23:16 Reserved + Uint16 rsvd3:8; // 31:24 Reserved +}; + +union INTOSC1TRIM_REG { + Uint32 all; + struct INTOSC1TRIM_BITS bit; +}; + +struct INTOSC2TRIM_BITS { // bits description + Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:8; // 23:16 Reserved + Uint16 rsvd3:8; // 31:24 Reserved +}; + +union INTOSC2TRIM_REG { + Uint32 all; + struct INTOSC2TRIM_BITS bit; +}; + +struct TSNSCTL_BITS { // bits description + Uint16 ENABLE:1; // 0 Temperature Sensor Enable + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union TSNSCTL_REG { + Uint16 all; + struct TSNSCTL_BITS bit; +}; + +struct LOCK_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock + Uint16 rsvd4:1; // 4 Reserved + Uint16 rsvd5:1; // 5 Reserved + Uint16 rsvd6:1; // 6 Reserved + Uint32 rsvd7:12; // 18:7 Reserved + Uint16 rsvd8:1; // 19 Reserved + Uint16 rsvd9:1; // 20 Reserved + Uint16 rsvd10:1; // 21 Reserved + Uint16 rsvd11:1; // 22 Reserved + Uint16 rsvd12:1; // 23 Reserved + Uint16 rsvd13:1; // 24 Reserved + Uint16 rsvd14:1; // 25 Reserved + Uint16 rsvd15:1; // 26 Reserved + Uint16 rsvd16:1; // 27 Reserved + Uint16 rsvd17:1; // 28 Reserved + Uint16 rsvd18:1; // 29 Reserved + Uint16 rsvd19:1; // 30 Reserved + Uint16 rsvd20:1; // 31 Reserved +}; + +union LOCK_REG { + Uint32 all; + struct LOCK_BITS bit; +}; + +struct ANAREFTRIMA_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMA_REG { + Uint32 all; + struct ANAREFTRIMA_BITS bit; +}; + +struct ANAREFTRIMB_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMB_REG { + Uint32 all; + struct ANAREFTRIMB_BITS bit; +}; + +struct ANAREFTRIMC_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMC_REG { + Uint32 all; + struct ANAREFTRIMC_BITS bit; +}; + +struct ANAREFTRIMD_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMD_REG { + Uint32 all; + struct ANAREFTRIMD_BITS bit; +}; + +struct ANALOG_SUBSYS_REGS { + Uint16 rsvd1[32]; // Reserved + union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register + union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register + Uint16 rsvd2[2]; // Reserved + union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register + Uint16 rsvd3[7]; // Reserved + union LOCK_REG LOCK; // Lock Register + Uint16 rsvd4[6]; // Reserved + union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register + union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register + union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register + union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register + Uint16 rsvd5[10]; // Reserved +}; + +//--------------------------------------------------------------------------- +// ANALOGSUBSYS External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h new file mode 100644 index 0000000000..ad625e4554 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h @@ -0,0 +1,612 @@ +//########################################################################### +// +// FILE: F2837xD_can.h +// +// TITLE: CAN Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CAN_H__ +#define __F2837xD_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CAN Individual Register Bit Definitions: + +struct CAN_CTL_BITS { // bits description + bp_16 Init:1; // 0 Initialization + bp_16 IE0:1; // 1 Interrupt line 0 Enable + bp_16 SIE:1; // 2 Status Change Interrupt Enable + bp_16 EIE:1; // 3 Error Interrupt Enable + bp_16 rsvd1:1; // 4 Reserved + bp_16 DAR:1; // 5 Disable Automatic Retransmission + bp_16 CCE:1; // 6 Configuration Change Enable + bp_16 Test:1; // 7 Test Mode Enable + bp_16 IDS:1; // 8 Interruption Debug Support Enable + bp_16 ABO:1; // 9 Auto-Bus-On Enable + bp_16 PMD:4; // 13:10 Parity on/off + bp_16 rsvd2:1; // 14 Reserved + bp_16 SWR:1; // 15 SW Reset Enable + bp_32 INITDBG:1; // 16 Debug Mode Status + bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled + bp_32 rsvd3:1; // 18 Reserved + bp_32 rsvd4:1; // 19 Reserved + bp_32 rsvd5:1; // 20 Reserved + bp_32 rsvd6:3; // 23:21 Reserved + bp_32 rsvd7:1; // 24 Reserved + bp_32 rsvd8:1; // 25 Reserved + bp_32 rsvd9:6; // 31:26 Reserved +}; + +union CAN_CTL_REG { + bp_32 all; + struct CAN_CTL_BITS bit; +}; + +struct CAN_ES_BITS { // bits description + bp_16 LEC:3; // 2:0 Last Error Code + bp_16 TxOk:1; // 3 Transmission status + bp_16 RxOk:1; // 4 Reception status + bp_16 EPass:1; // 5 Error Passive State + bp_16 EWarn:1; // 6 Warning State + bp_16 BOff:1; // 7 Bus-Off State + bp_16 PER:1; // 8 Parity Error Detected + bp_16 rsvd1:1; // 9 Reserved + bp_16 rsvd2:1; // 10 Reserved + bp_16 rsvd3:5; // 15:11 Reserved + bp_32 rsvd4:16; // 31:16 Reserved +}; + +union CAN_ES_REG { + bp_32 all; + struct CAN_ES_BITS bit; +}; + +struct CAN_ERRC_BITS { // bits description + bp_16 TEC:8; // 7:0 Transmit Error Counter + bp_16 REC:7; // 14:8 Receive Error Counter + bp_16 RP:1; // 15 Receive Error Passive + bp_32 rsvd1:16; // 31:16 Reserved +}; + +union CAN_ERRC_REG { + bp_32 all; + struct CAN_ERRC_BITS bit; +}; + +struct CAN_BTR_BITS { // bits description + bp_16 BRP:6; // 5:0 Baud Rate Prescaler + bp_16 SJW:2; // 7:6 Synchronization Jump Width + bp_16 TSEG1:4; // 11:8 Time segment + bp_16 TSEG2:3; // 14:12 Time segment + bp_16 rsvd1:1; // 15 Reserved + bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension + bp_32 rsvd2:12; // 31:20 Reserved +}; + +union CAN_BTR_REG { + bp_32 all; + struct CAN_BTR_BITS bit; +}; + +struct CAN_INT_BITS { // bits description + bp_16 INT0ID:16; // 15:0 Interrupt Identifier + bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier + bp_32 rsvd1:8; // 31:24 Reserved +}; + +union CAN_INT_REG { + bp_32 all; + struct CAN_INT_BITS bit; +}; + +struct CAN_TEST_BITS { // bits description + bp_16 rsvd1:3; // 2:0 Reserved + bp_16 SILENT:1; // 3 Silent Mode + bp_16 LBACK:1; // 4 Loopback Mode + bp_16 TX:2; // 6:5 CANTX Pin Control + bp_16 RX:1; // 7 CANRX Pin Status + bp_16 EXL:1; // 8 External Loopback Mode + bp_16 RDA:1; // 9 RAM Direct Access Enable: + bp_16 rsvd2:6; // 15:10 Reserved + bp_32 rsvd3:16; // 31:16 Reserved +}; + +union CAN_TEST_REG { + bp_32 all; + struct CAN_TEST_BITS bit; +}; + +struct CAN_PERR_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 WORD_NUM:3; // 10:8 Word Number + bp_16 rsvd1:5; // 15:11 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_PERR_REG { + bp_32 all; + struct CAN_PERR_BITS bit; +}; + +struct CAN_RAM_INIT_BITS { // bits description + bp_16 KEY0:1; // 0 KEY0 + bp_16 KEY1:1; // 1 KEY1 + bp_16 KEY2:1; // 2 KEY2 + bp_16 KEY3:1; // 3 KEY3 + bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM + bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete + bp_16 rsvd1:10; // 15:6 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_RAM_INIT_REG { + bp_32 all; + struct CAN_RAM_INIT_BITS bit; +}; + +struct CAN_GLB_INT_EN_BITS { // bits description + bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 + bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_EN_REG { + bp_32 all; + struct CAN_GLB_INT_EN_BITS bit; +}; + +struct CAN_GLB_INT_FLG_BITS { // bits description + bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 + bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_FLG_REG { + bp_32 all; + struct CAN_GLB_INT_FLG_BITS bit; +}; + +struct CAN_GLB_INT_CLR_BITS { // bits description + bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 + bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_CLR_REG { + bp_32 all; + struct CAN_GLB_INT_CLR_BITS bit; +}; + +struct CAN_TXRQ_X_BITS { // bits description + bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 + bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_TXRQ_X_REG { + bp_32 all; + struct CAN_TXRQ_X_BITS bit; +}; + +struct CAN_NDAT_X_BITS { // bits description + bp_16 NewDatReg1:2; // 1:0 New Data Register 1 + bp_16 NewDatReg2:2; // 3:2 New Data Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_NDAT_X_REG { + bp_32 all; + struct CAN_NDAT_X_BITS bit; +}; + +struct CAN_IPEN_X_BITS { // bits description + bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 + bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IPEN_X_REG { + bp_32 all; + struct CAN_IPEN_X_BITS bit; +}; + +struct CAN_MVAL_X_BITS { // bits description + bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 + bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_MVAL_X_REG { + bp_32 all; + struct CAN_MVAL_X_BITS bit; +}; + +struct CAN_IF1CMD_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 rsvd1:6; // 13:8 Reserved + bp_16 rsvd2:1; // 14 Reserved + bp_16 Busy:1; // 15 Busy Flag + bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 + bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 + bp_32 TXRQST:1; // 18 Access Transmission Request Bit + bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit + bp_32 Control:1; // 20 Access Control Bits + bp_32 Arb:1; // 21 Access Arbitration Bits + bp_32 Mask:1; // 22 Access Mask Bits + bp_32 DIR:1; // 23 Write/Read Direction + bp_32 rsvd3:8; // 31:24 Reserved +}; + +union CAN_IF1CMD_REG { + bp_32 all; + struct CAN_IF1CMD_BITS bit; +}; + +struct CAN_IF1MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Identifier Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF1MSK_REG { + bp_32 all; + struct CAN_IF1MSK_BITS bit; +}; + +struct CAN_IF1ARB_BITS { // bits description + bp_32 ID:29; // 28:0 ` + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF1ARB_REG { + bp_32 all; + struct CAN_IF1ARB_BITS bit; +}; + +struct CAN_IF1MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF1MCTL_REG { + bp_32 all; + struct CAN_IF1MCTL_BITS bit; +}; + +struct CAN_IF1DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF1DATA_REG { + bp_32 all; + struct CAN_IF1DATA_BITS bit; +}; + +struct CAN_IF1DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF1DATB_REG { + bp_32 all; + struct CAN_IF1DATB_BITS bit; +}; + +struct CAN_IF2CMD_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 rsvd1:6; // 13:8 Reserved + bp_16 rsvd2:1; // 14 Reserved + bp_16 Busy:1; // 15 Busy Flag + bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 + bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 + bp_32 TxRqst:1; // 18 Access Transmission Request Bit + bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit + bp_32 Control:1; // 20 Access Control Bits + bp_32 Arb:1; // 21 Access Arbitration Bits + bp_32 Mask:1; // 22 Access Mask Bits + bp_32 DIR:1; // 23 Write/Read Direction + bp_32 rsvd3:8; // 31:24 Reserved +}; + +union CAN_IF2CMD_REG { + bp_32 all; + struct CAN_IF2CMD_BITS bit; +}; + +struct CAN_IF2MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Identifier Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF2MSK_REG { + bp_32 all; + struct CAN_IF2MSK_BITS bit; +}; + +struct CAN_IF2ARB_BITS { // bits description + bp_32 ID:29; // 28:0 Message Identifier + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF2ARB_REG { + bp_32 all; + struct CAN_IF2ARB_BITS bit; +}; + +struct CAN_IF2MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF2MCTL_REG { + bp_32 all; + struct CAN_IF2MCTL_BITS bit; +}; + +struct CAN_IF2DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF2DATA_REG { + bp_32 all; + struct CAN_IF2DATA_BITS bit; +}; + +struct CAN_IF2DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF2DATB_REG { + bp_32 all; + struct CAN_IF2DATB_BITS bit; +}; + +struct CAN_IF3OBS_BITS { // bits description + bp_16 Mask:1; // 0 Mask data read observation + bp_16 Arb:1; // 1 Arbitration data read observation + bp_16 Ctrl:1; // 2 Ctrl read observation + bp_16 Data_A:1; // 3 Data A read observation + bp_16 Data_B:1; // 4 Data B read observation + bp_16 rsvd1:3; // 7:5 Reserved + bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access + bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access + bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access + bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access + bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access + bp_16 rsvd2:2; // 14:13 Reserved + bp_16 IF3Upd:1; // 15 IF3 Update Data + bp_32 rsvd3:16; // 31:16 Reserved +}; + +union CAN_IF3OBS_REG { + bp_32 all; + struct CAN_IF3OBS_BITS bit; +}; + +struct CAN_IF3MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF3MSK_REG { + bp_32 all; + struct CAN_IF3MSK_BITS bit; +}; + +struct CAN_IF3ARB_BITS { // bits description + bp_32 ID:29; // 28:0 Message Identifier + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF3ARB_REG { + bp_32 all; + struct CAN_IF3ARB_BITS bit; +}; + +struct CAN_IF3MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF3MCTL_REG { + bp_32 all; + struct CAN_IF3MCTL_BITS bit; +}; + +struct CAN_IF3DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF3DATA_REG { + bp_32 all; + struct CAN_IF3DATA_BITS bit; +}; + +struct CAN_IF3DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF3DATB_REG { + bp_32 all; + struct CAN_IF3DATB_BITS bit; +}; + +struct CAN_REGS { + union CAN_CTL_REG CAN_CTL; // CAN Control Register + union CAN_ES_REG CAN_ES; // Error and Status Register + union CAN_ERRC_REG CAN_ERRC; // Error Counter Register + union CAN_BTR_REG CAN_BTR; // Bit Timing Register + union CAN_INT_REG CAN_INT; // Interrupt Register + union CAN_TEST_REG CAN_TEST; // Test Register + uint32_t rsvd1[2]; // Reserved + union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register + uint32_t rsvd2[16]; // Reserved + union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register + uint32_t rsvd3[6]; // Reserved + union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register + union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register + union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register + uint32_t rsvd4[18]; // Reserved + bp_32 CAN_ABOTR; // Auto-Bus-On Time Register + union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register + bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register + uint32_t rsvd5[6]; // Reserved + union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register + bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register + uint32_t rsvd6[6]; // Reserved + union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register + bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register + uint32_t rsvd7[6]; // Reserved + union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register + bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register + uint32_t rsvd8[8]; // Reserved + bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register + uint32_t rsvd9[18]; // Reserved + union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register + union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register + union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register + union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register + union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register + union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register + uint32_t rsvd10[4]; // Reserved + union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register + union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register + union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register + union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register + union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register + union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register + uint32_t rsvd11[4]; // Reserved + union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register + union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register + union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register + union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register + union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register + union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register + uint32_t rsvd12[4]; // Reserved + bp_32 CAN_IF3UPD; // IF3 Update Enable Register +}; + +//--------------------------------------------------------------------------- +// CAN External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CAN_REGS CanaRegs; +extern volatile struct CAN_REGS CanbRegs; +#endif +#ifdef CPU2 +extern volatile struct CAN_REGS CanaRegs; +extern volatile struct CAN_REGS CanbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h new file mode 100644 index 0000000000..683333074c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h @@ -0,0 +1,305 @@ +//########################################################################### +// +// FILE: F2837xD_cla.h +// +// TITLE: CLA Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CLA_H__ +#define __F2837xD_CLA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CLA Individual Register Bit Definitions: + +struct MCTL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset + Uint16 SOFTRESET:1; // 1 Soft Reset + Uint16 IACKE:1; // 2 IACK enable + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union MCTL_REG { + Uint16 all; + struct MCTL_BITS bit; +}; + +struct MIFR_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Flag + Uint16 INT2:1; // 1 Task 2 Interrupt Flag + Uint16 INT3:1; // 2 Task 3 Interrupt Flag + Uint16 INT4:1; // 3 Task 4 Interrupt Flag + Uint16 INT5:1; // 4 Task 5 Interrupt Flag + Uint16 INT6:1; // 5 Task 6 Interrupt Flag + Uint16 INT7:1; // 6 Task 7 Interrupt Flag + Uint16 INT8:1; // 7 Task 8 Interrupt Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIFR_REG { + Uint16 all; + struct MIFR_BITS bit; +}; + +struct MIOVF_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag + Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag + Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag + Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag + Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag + Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag + Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag + Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIOVF_REG { + Uint16 all; + struct MIOVF_BITS bit; +}; + +struct MIFRC_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Force + Uint16 INT2:1; // 1 Task 2 Interrupt Force + Uint16 INT3:1; // 2 Task 3 Interrupt Force + Uint16 INT4:1; // 3 Task 4 Interrupt Force + Uint16 INT5:1; // 4 Task 5 Interrupt Force + Uint16 INT6:1; // 5 Task 6 Interrupt Force + Uint16 INT7:1; // 6 Task 7 Interrupt Force + Uint16 INT8:1; // 7 Task 8 Interrupt Force + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIFRC_REG { + Uint16 all; + struct MIFRC_BITS bit; +}; + +struct MICLR_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear + Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear + Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear + Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear + Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear + Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear + Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear + Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MICLR_REG { + Uint16 all; + struct MICLR_BITS bit; +}; + +struct MICLROVF_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear + Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear + Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear + Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear + Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear + Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear + Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear + Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MICLROVF_REG { + Uint16 all; + struct MICLROVF_BITS bit; +}; + +struct MIER_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Enable + Uint16 INT2:1; // 1 Task 2 Interrupt Enable + Uint16 INT3:1; // 2 Task 3 Interrupt Enable + Uint16 INT4:1; // 3 Task 4 Interrupt Enable + Uint16 INT5:1; // 4 Task 5 Interrupt Enable + Uint16 INT6:1; // 5 Task 6 Interrupt Enable + Uint16 INT7:1; // 6 Task 7 Interrupt Enable + Uint16 INT8:1; // 7 Task 8 Interrupt Enable + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIER_REG { + Uint16 all; + struct MIER_BITS bit; +}; + +struct MIRUN_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Run Status + Uint16 INT2:1; // 1 Task 2 Run Status + Uint16 INT3:1; // 2 Task 3 Run Status + Uint16 INT4:1; // 3 Task 4 Run Status + Uint16 INT5:1; // 4 Task 5 Run Status + Uint16 INT6:1; // 5 Task 6 Run Status + Uint16 INT7:1; // 6 Task 7 Run Status + Uint16 INT8:1; // 7 Task 8 Run Status + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIRUN_REG { + Uint16 all; + struct MIRUN_BITS bit; +}; + +struct _MSTF_BITS { // bits description + Uint16 LVF:1; // 0 Latched Overflow Flag + Uint16 LUF:1; // 1 Latched Underflow Flag + Uint16 NF:1; // 2 Negative Float Flag + Uint16 ZF:1; // 3 Zero Float Flag + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 TF:1; // 6 Test Flag + Uint16 rsvd2:2; // 8:7 Reserved + Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode + Uint16 rsvd3:1; // 10 Reserved + Uint16 MEALLOW:1; // 11 MEALLOW Status + Uint32 _RPC:16; // 27:12 Return PC + Uint16 rsvd4:4; // 31:28 Reserved +}; + +union _MSTF_REG { + Uint32 all; + struct _MSTF_BITS bit; +}; + +union MR_REG { + Uint32 i32; + float f32; +}; + +struct CLA_REGS { + Uint16 MVECT1; // Task Interrupt Vector + Uint16 MVECT2; // Task Interrupt Vector + Uint16 MVECT3; // Task Interrupt Vector + Uint16 MVECT4; // Task Interrupt Vector + Uint16 MVECT5; // Task Interrupt Vector + Uint16 MVECT6; // Task Interrupt Vector + Uint16 MVECT7; // Task Interrupt Vector + Uint16 MVECT8; // Task Interrupt Vector + Uint16 rsvd1[8]; // Reserved + union MCTL_REG MCTL; // Control Register + Uint16 rsvd2[15]; // Reserved + union MIFR_REG MIFR; // Interrupt Flag Register + union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register + union MIFRC_REG MIFRC; // Interrupt Force Register + union MICLR_REG MICLR; // Interrupt Flag Clear Register + union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register + union MIER_REG MIER; // Interrupt Enable Register + union MIRUN_REG MIRUN; // Interrupt Run Status Register + Uint16 rsvd3; // Reserved + Uint16 _MPC; // CLA Program Counter + Uint16 rsvd4; // Reserved + Uint16 _MAR0; // CLA Auxiliary Register 0 + Uint16 _MAR1; // CLA Auxiliary Register 1 + Uint16 rsvd5[2]; // Reserved + union _MSTF_REG _MSTF; // CLA Floating-Point Status Register + union MR_REG _MR0; // CLA Floating-Point Result Register 0 + Uint16 rsvd6[2]; // Reserved + union MR_REG _MR1; // CLA Floating-Point Result Register 1 + Uint16 rsvd7[2]; // Reserved + union MR_REG _MR2; // CLA Floating-Point Result Register 2 + Uint16 rsvd8[2]; // Reserved + union MR_REG _MR3; // CLA Floating-Point Result Register 3 +}; + +struct SOFTINTEN_BITS { // bits description + Uint16 TASK1:1; // 0 Task 1 Software Interrupt Enable + Uint16 TASK2:1; // 1 Task 2 Software Interrupt Enable + Uint16 TASK3:1; // 2 Task 3 Software Interrupt Enable + Uint16 TASK4:1; // 3 Task 4 Software Interrupt Enable + Uint16 TASK5:1; // 4 Task 5 Software Interrupt Enable + Uint16 TASK6:1; // 5 Task 6 Software Interrupt Enable + Uint16 TASK7:1; // 6 Task 7 Software Interrupt Enable + Uint16 TASK8:1; // 7 Task 8 Software Interrupt Enable + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTINTEN_REG { + Uint32 all; + struct SOFTINTEN_BITS bit; +}; + +struct SOFTINTFRC_BITS { // bits description + Uint16 TASK1:1; // 0 Task 1 Software Interrupt Force + Uint16 TASK2:1; // 1 Task 2 Software Interrupt Force + Uint16 TASK3:1; // 2 Task 3 Software Interrupt Force + Uint16 TASK4:1; // 3 Task 4 Software Interrupt Force + Uint16 TASK5:1; // 4 Task 5 Software Interrupt Force + Uint16 TASK6:1; // 5 Task 6 Software Interrupt Force + Uint16 TASK7:1; // 6 Task 7 Software Interrupt Force + Uint16 TASK8:1; // 7 Task 8 Software Interrupt Force + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTINTFRC_REG { + Uint32 all; + struct SOFTINTFRC_BITS bit; +}; + +struct CLA_SOFTINT_REGS { + union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register + union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register +}; + +//--------------------------------------------------------------------------- +// CLA External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +extern volatile struct CLA_REGS Cla1Regs; +#endif +#ifdef CPU2 +extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +extern volatile struct CLA_REGS Cla1Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h new file mode 100644 index 0000000000..51b595b01c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h @@ -0,0 +1,310 @@ +//########################################################################### +// +// FILE: F2837xD_cmpss.h +// +// TITLE: CMPSS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CMPSS_H__ +#define __F2837xD_CMPSS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CMPSS Individual Register Bit Definitions: + +struct COMPCTL_BITS { // bits description + Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select + Uint16 COMPHINV:1; // 1 High Comparator Invert Select + Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select + Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select + Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable + Uint16 rsvd1:1; // 7 Reserved + Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select + Uint16 COMPLINV:1; // 9 Low Comparator Invert Select + Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select + Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select + Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable + Uint16 COMPDACE:1; // 15 Comparator/DAC Enable +}; + +union COMPCTL_REG { + Uint16 all; + struct COMPCTL_BITS bit; +}; + +struct COMPHYSCTL_BITS { // bits description + Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union COMPHYSCTL_REG { + Uint16 all; + struct COMPHYSCTL_BITS bit; +}; + +struct COMPSTS_BITS { // bits description + Uint16 COMPHSTS:1; // 0 High Comparator Status + Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 COMPLSTS:1; // 8 Low Comparator Status + Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status + Uint16 rsvd2:6; // 15:10 Reserved +}; + +union COMPSTS_REG { + Uint16 all; + struct COMPSTS_BITS bit; +}; + +struct COMPSTSCLR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear + Uint16 HSYNCCLREN:1; // 2 High Comparator PWMSYNC Clear Enable + Uint16 rsvd2:6; // 8:3 Reserved + Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear + Uint16 LSYNCCLREN:1; // 10 Low Comparator PWMSYNC Clear Enable + Uint16 rsvd3:5; // 15:11 Reserved +}; + +union COMPSTSCLR_REG { + Uint16 all; + struct COMPSTSCLR_BITS bit; +}; + +struct COMPDACCTL_BITS { // bits description + Uint16 DACSOURCE:1; // 0 DAC Source Control + Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control + Uint16 SELREF:1; // 5 DAC Reference Select + Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select + Uint16 SWLOADSEL:1; // 7 Software Load Select + Uint16 rsvd1:6; // 13:8 Reserved + Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits +}; + +union COMPDACCTL_REG { + Uint16 all; + struct COMPDACCTL_BITS bit; +}; + +struct DACHVALS_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACHVALS_REG { + Uint16 all; + struct DACHVALS_BITS bit; +}; + +struct DACHVALA_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACHVALA_REG { + Uint16 all; + struct DACHVALA_BITS bit; +}; + +struct DACLVALS_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACLVALS_REG { + Uint16 all; + struct DACLVALS_BITS bit; +}; + +struct DACLVALA_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACLVALA_REG { + Uint16 all; + struct DACLVALA_BITS bit; +}; + +struct RAMPDLYA_BITS { // bits description + Uint16 DELAY:13; // 12:0 Ramp Delay Value + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union RAMPDLYA_REG { + Uint16 all; + struct RAMPDLYA_BITS bit; +}; + +struct RAMPDLYS_BITS { // bits description + Uint16 DELAY:13; // 12:0 Ramp Delay Value + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union RAMPDLYS_REG { + Uint16 all; + struct RAMPDLYS_BITS bit; +}; + +struct CTRIPLFILCTL_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 SAMPWIN:5; // 8:4 Sample Window + Uint16 THRESH:5; // 13:9 Majority Voting Threshold + Uint16 rsvd2:1; // 14 Reserved + Uint16 FILINIT:1; // 15 Filter Initialization Bit +}; + +union CTRIPLFILCTL_REG { + Uint16 all; + struct CTRIPLFILCTL_BITS bit; +}; + +struct CTRIPLFILCLKCTL_BITS { // bits description + Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union CTRIPLFILCLKCTL_REG { + Uint16 all; + struct CTRIPLFILCLKCTL_BITS bit; +}; + +struct CTRIPHFILCTL_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 SAMPWIN:5; // 8:4 Sample Window + Uint16 THRESH:5; // 13:9 Majority Voting Threshold + Uint16 rsvd2:1; // 14 Reserved + Uint16 FILINIT:1; // 15 Filter Initialization Bit +}; + +union CTRIPHFILCTL_REG { + Uint16 all; + struct CTRIPHFILCTL_BITS bit; +}; + +struct CTRIPHFILCLKCTL_BITS { // bits description + Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union CTRIPHFILCLKCTL_REG { + Uint16 all; + struct CTRIPHFILCLKCTL_BITS bit; +}; + +struct COMPLOCK_BITS { // bits description + Uint16 COMPCTL:1; // 0 COMPCTL Lock + Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock + Uint16 DACCTL:1; // 2 DACCTL Lock + Uint16 CTRIP:1; // 3 CTRIP Lock + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:11; // 15:5 Reserved +}; + +union COMPLOCK_REG { + Uint16 all; + struct COMPLOCK_BITS bit; +}; + +struct CMPSS_REGS { + union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register + union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register + union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register + union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register + union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register + Uint16 rsvd1; // Reserved + union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register + union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register + Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register + Uint16 rsvd2; // Reserved + Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register + Uint16 rsvd3; // Reserved + Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register + Uint16 rsvd4; // Reserved + Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register + Uint16 rsvd5; // Reserved + Uint16 RAMPSTS; // CMPSS Ramp Status Register + Uint16 rsvd6; // Reserved + union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register + union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register + union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register + union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register + union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register + union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register + union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register + union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register + union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register + Uint16 rsvd7[5]; // Reserved +}; + +//--------------------------------------------------------------------------- +// CMPSS External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CMPSS_REGS Cmpss1Regs; +extern volatile struct CMPSS_REGS Cmpss2Regs; +extern volatile struct CMPSS_REGS Cmpss3Regs; +extern volatile struct CMPSS_REGS Cmpss4Regs; +extern volatile struct CMPSS_REGS Cmpss5Regs; +extern volatile struct CMPSS_REGS Cmpss6Regs; +extern volatile struct CMPSS_REGS Cmpss7Regs; +extern volatile struct CMPSS_REGS Cmpss8Regs; +#endif +#ifdef CPU2 +extern volatile struct CMPSS_REGS Cmpss1Regs; +extern volatile struct CMPSS_REGS Cmpss2Regs; +extern volatile struct CMPSS_REGS Cmpss3Regs; +extern volatile struct CMPSS_REGS Cmpss4Regs; +extern volatile struct CMPSS_REGS Cmpss5Regs; +extern volatile struct CMPSS_REGS Cmpss6Regs; +extern volatile struct CMPSS_REGS Cmpss7Regs; +extern volatile struct CMPSS_REGS Cmpss8Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h new file mode 100644 index 0000000000..f822f516e5 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h @@ -0,0 +1,141 @@ +//########################################################################### +// +// FILE: F2837xD_cputimer.h +// +// TITLE: CPUTIMER Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CPUTIMER_H__ +#define __F2837xD_CPUTIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CPUTIMER Individual Register Bit Definitions: + +struct TIM_BITS { // bits description + Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers + Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High +}; + +union TIM_REG { + Uint32 all; + struct TIM_BITS bit; +}; + +struct PRD_BITS { // bits description + Uint16 LSW:16; // 15:0 CPU-Timer Period Registers + Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High +}; + +union PRD_REG { + Uint32 all; + struct PRD_BITS bit; +}; + +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 TSS:1; // 4 CPU-Timer stop status bit. + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 Reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 Emulation modes + Uint16 rsvd3:2; // 13:12 Reserved + Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. + Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. + Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. + Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +struct CPUTIMER_REGS { + union TIM_REG TIM; // CPU-Timer, Counter Register + union PRD_REG PRD; // CPU-Timer, Period Register + union TCR_REG TCR; // CPU-Timer, Control Register + Uint16 rsvd1; // Reserved + union TPR_REG TPR; // CPU-Timer, Prescale Register + union TPRH_REG TPRH; // CPU-Timer, Prescale Register High +}; + +//--------------------------------------------------------------------------- +// CPUTIMER External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; +#endif +#ifdef CPU2 +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h new file mode 100644 index 0000000000..6594bf2334 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h @@ -0,0 +1,163 @@ +//########################################################################### +// +// FILE: F2837xD_dac.h +// +// TITLE: DAC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DAC_H__ +#define __F2837xD_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DAC Individual Register Bit Definitions: + +struct DACREV_BITS { // bits description + Uint16 REV:8; // 7:0 DAC Revision Register + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union DACREV_REG { + Uint16 all; + struct DACREV_BITS bit; +}; + +struct DACCTL_BITS { // bits description + Uint16 DACREFSEL:1; // 0 DAC Reference Select + Uint16 rsvd1:1; // 1 Reserved + Uint16 LOADMODE:1; // 2 DACVALA Load Mode + Uint16 rsvd2:1; // 3 Reserved + Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select + Uint16 rsvd3:8; // 15:8 Reserved +}; + +union DACCTL_REG { + Uint16 all; + struct DACCTL_BITS bit; +}; + +struct DACVALA_BITS { // bits description + Uint16 DACVALA:12; // 11:0 DAC Active Output Code + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACVALA_REG { + Uint16 all; + struct DACVALA_BITS bit; +}; + +struct DACVALS_BITS { // bits description + Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACVALS_REG { + Uint16 all; + struct DACVALS_BITS bit; +}; + +struct DACOUTEN_BITS { // bits description + Uint16 DACOUTEN:1; // 0 DAC Output Code + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union DACOUTEN_REG { + Uint16 all; + struct DACOUTEN_BITS bit; +}; + +struct DACLOCK_BITS { // bits description + Uint16 DACCTL:1; // 0 DAC Control Register Lock + Uint16 DACVAL:1; // 1 DAC Value Register Lock + Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union DACLOCK_REG { + Uint16 all; + struct DACLOCK_BITS bit; +}; + +struct DACTRIM_BITS { // bits description + Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim + Uint16 rsvd1:4; // 11:8 Reserved + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union DACTRIM_REG { + Uint16 all; + struct DACTRIM_BITS bit; +}; + +struct DAC_REGS { + union DACREV_REG DACREV; // DAC Revision Register + union DACCTL_REG DACCTL; // DAC Control Register + union DACVALA_REG DACVALA; // DAC Value Register - Active + union DACVALS_REG DACVALS; // DAC Value Register - Shadow + union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register + union DACLOCK_REG DACLOCK; // DAC Lock Register + union DACTRIM_REG DACTRIM; // DAC Trim Register + Uint16 rsvd1; // Reserved +}; + +//--------------------------------------------------------------------------- +// DAC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct DAC_REGS DacaRegs; +extern volatile struct DAC_REGS DacbRegs; +extern volatile struct DAC_REGS DaccRegs; +#endif +#ifdef CPU2 +extern volatile struct DAC_REGS DacaRegs; +extern volatile struct DAC_REGS DacbRegs; +extern volatile struct DAC_REGS DaccRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h new file mode 100644 index 0000000000..4ea33d6843 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h @@ -0,0 +1,449 @@ +//########################################################################### +// +// FILE: F2837xD_dcsm.h +// +// TITLE: DCSM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DCSM_H__ +#define __F2837xD_DCSM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DCSM Individual Register Bit Definitions: + +struct Z1_LINKPOINTER_BITS { // bits description + Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer. + Uint16 rsvd1:3; // 31:29 Reserved +}; + +union Z1_LINKPOINTER_REG { + Uint32 all; + struct Z1_LINKPOINTER_BITS bit; +}; + +struct Z1_OTPSECLOCK_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. + Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z1_OTPSECLOCK_REG { + Uint32 all; + struct Z1_OTPSECLOCK_BITS bit; +}; + +struct Z1_BOOTCTRL_BITS { // bits description + Uint16 KEY:8; // 7:0 OTP Boot Key + Uint16 BMODE:8; // 15:8 OTP Boot Mode + Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping + Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping +}; + +union Z1_BOOTCTRL_REG { + Uint32 all; + struct Z1_BOOTCTRL_BITS bit; +}; + +struct Z1_CR_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros + Uint16 ALLONE:1; // 4 CSMPSWD All Ones + Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY + Uint16 ARMED:1; // 6 CSM Armed + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:7; // 14:8 Reserved + Uint16 FORCESEC:1; // 15 Force Secure +}; + +union Z1_CR_REG { + Uint16 all; + struct Z1_CR_BITS bit; +}; + +struct Z1_GRABSECTR_BITS { // bits description + Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A + Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B + Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C + Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D + Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E + Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F + Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G + Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H + Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I + Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J + Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K + Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L + Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M + Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z1_GRABSECTR_REG { + Uint32 all; + struct Z1_GRABSECTR_BITS bit; +}; + +struct Z1_GRABRAMR_BITS { // bits description + Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 + Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 + Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 + Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 + Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 + Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 + Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 + Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z1_GRABRAMR_REG { + Uint32 all; + struct Z1_GRABRAMR_BITS bit; +}; + +struct Z1_EXEONLYSECTR_BITS { // bits description + Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A + Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B + Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C + Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D + Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E + Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F + Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G + Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H + Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I + Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J + Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K + Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L + Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M + Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N + Uint16 rsvd1:1; // 14 Reserved + Uint16 rsvd2:1; // 15 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z1_EXEONLYSECTR_REG { + Uint32 all; + struct Z1_EXEONLYSECTR_BITS bit; +}; + +struct Z1_EXEONLYRAMR_BITS { // bits description + Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 + Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 + Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 + Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 + Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 + Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 + Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 + Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union Z1_EXEONLYRAMR_REG { + Uint32 all; + struct Z1_EXEONLYRAMR_BITS bit; +}; + +struct DCSM_Z1_REGS { + union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer + union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock + union Z1_BOOTCTRL_REG Z1_BOOTCTRL; // Boot Mode + Uint32 Z1_LINKPOINTERERR; // Link Pointer Error + Uint16 rsvd1[8]; // Reserved + Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 + Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 + Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 + Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 + Uint16 rsvd2; // Reserved + union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register + union Z1_GRABSECTR_REG Z1_GRABSECTR; // Zone 1 Grab Flash Sectors Register + union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register + union Z1_EXEONLYSECTR_REG Z1_EXEONLYSECTR; // Zone 1 Flash Execute_Only Sector Register + union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register + Uint16 rsvd3; // Reserved +}; + +struct Z2_LINKPOINTER_BITS { // bits description + Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer. + Uint16 rsvd1:3; // 31:29 Reserved +}; + +union Z2_LINKPOINTER_REG { + Uint32 all; + struct Z2_LINKPOINTER_BITS bit; +}; + +struct Z2_OTPSECLOCK_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. + Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z2_OTPSECLOCK_REG { + Uint32 all; + struct Z2_OTPSECLOCK_BITS bit; +}; + +struct Z2_BOOTCTRL_BITS { // bits description + Uint16 KEY:8; // 7:0 OTP Boot Key + Uint16 BMODE:8; // 15:8 OTP Boot Mode + Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping + Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping +}; + +union Z2_BOOTCTRL_REG { + Uint32 all; + struct Z2_BOOTCTRL_BITS bit; +}; + +struct Z2_CR_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros + Uint16 ALLONE:1; // 4 CSMPSWD All Ones + Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY + Uint16 ARMED:1; // 6 CSM Armed + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:7; // 14:8 Reserved + Uint16 FORCESEC:1; // 15 Force Secure +}; + +union Z2_CR_REG { + Uint16 all; + struct Z2_CR_BITS bit; +}; + +struct Z2_GRABSECTR_BITS { // bits description + Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A + Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B + Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C + Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D + Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E + Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F + Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G + Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H + Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I + Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J + Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K + Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L + Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M + Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z2_GRABSECTR_REG { + Uint32 all; + struct Z2_GRABSECTR_BITS bit; +}; + +struct Z2_GRABRAMR_BITS { // bits description + Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 + Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 + Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 + Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 + Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 + Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 + Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 + Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z2_GRABRAMR_REG { + Uint32 all; + struct Z2_GRABRAMR_BITS bit; +}; + +struct Z2_EXEONLYSECTR_BITS { // bits description + Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A + Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B + Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C + Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D + Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E + Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F + Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G + Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H + Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I + Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J + Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K + Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L + Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M + Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N + Uint16 rsvd1:1; // 14 Reserved + Uint16 rsvd2:1; // 15 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z2_EXEONLYSECTR_REG { + Uint32 all; + struct Z2_EXEONLYSECTR_BITS bit; +}; + +struct Z2_EXEONLYRAMR_BITS { // bits description + Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 + Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 + Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 + Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 + Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 + Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 + Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 + Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union Z2_EXEONLYRAMR_REG { + Uint32 all; + struct Z2_EXEONLYRAMR_BITS bit; +}; + +struct DCSM_Z2_REGS { + union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer + union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock + union Z2_BOOTCTRL_REG Z2_BOOTCTRL; // Boot Mode + Uint32 Z2_LINKPOINTERERR; // Link Pointer Error + Uint16 rsvd1[8]; // Reserved + Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 + Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 + Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 + Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 + Uint16 rsvd2; // Reserved + union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register + union Z2_GRABSECTR_REG Z2_GRABSECTR; // Zone 2 Grab Flash Sectors Register + union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register + union Z2_EXEONLYSECTR_REG Z2_EXEONLYSECTR; // Zone 2 Flash Execute_Only Sector Register + union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register + Uint16 rsvd3; // Reserved +}; + +struct FLSEM_BITS { // bits description + Uint16 SEM:2; // 1:0 Flash Semaphore Bit + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 KEY:8; // 15:8 Semaphore Key + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FLSEM_REG { + Uint32 all; + struct FLSEM_BITS bit; +}; + +struct SECTSTAT_BITS { // bits description + Uint16 STATUS_SECTA:2; // 1:0 Zone Status Flash Sector A + Uint16 STATUS_SECTB:2; // 3:2 Zone Status Flash Sector B + Uint16 STATUS_SECTC:2; // 5:4 Zone Status Flash Sector C + Uint16 STATUS_SECTD:2; // 7:6 Zone Status Flash Sector D + Uint16 STATUS_SECTE:2; // 9:8 Zone Status Flash Sector E + Uint16 STATUS_SECTF:2; // 11:10 Zone Status Flash Sector F + Uint16 STATUS_SECTG:2; // 13:12 Zone Status Flash Sector G + Uint16 STATUS_SECTH:2; // 15:14 Zone Status Flash Sector H + Uint16 STATUS_SECTI:2; // 17:16 Zone Status Flash Sector I + Uint16 STATUS_SECTJ:2; // 19:18 Zone Status Flash Sector J + Uint16 STATUS_SECTK:2; // 21:20 Zone Status Flash Sector K + Uint16 STATUS_SECTL:2; // 23:22 Zone Status Flash Sector L + Uint16 STATUS_SECTM:2; // 25:24 Zone Status Flash Sector M + Uint16 STATUS_SECTN:2; // 27:26 Zone Status Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union SECTSTAT_REG { + Uint32 all; + struct SECTSTAT_BITS bit; +}; + +struct RAMSTAT_BITS { // bits description + Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 + Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 + Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 + Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 + Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 + Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 + Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM D0 + Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 STATUS_CLA1:2; // 29:28 Zone Status CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union RAMSTAT_REG { + Uint32 all; + struct RAMSTAT_BITS bit; +}; + +struct DCSM_COMMON_REGS { + union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register + union SECTSTAT_REG SECTSTAT; // Sectors Status Register + union RAMSTAT_REG RAMSTAT; // RAM Status Register + Uint16 rsvd1[2]; // Reserved +}; + +//--------------------------------------------------------------------------- +// DCSM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; +extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; +extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; +#endif +#ifdef CPU2 +extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; +extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; +extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h new file mode 100644 index 0000000000..58aee28ebb --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h @@ -0,0 +1,345 @@ +//########################################################################### +// +// FILE: F2837xD_device.h +// +// TITLE: F2837xD Device Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DEVICE_H +#define F2837xD_DEVICE_H + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only a single CPU should be defined." +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define TARGET 1 + +// +// User To Select Target Device: +// +#define F28_2837xD TARGET + +// +// Common CPU Definitions: +// +extern __cregister volatile unsigned int IFR; +extern __cregister volatile unsigned int IER; + +#define EINT __asm(" clrc INTM") +#define DINT __asm(" setc INTM") +#define ERTM __asm(" clrc DBGM") +#define DRTM __asm(" setc DBGM") +#ifndef EALLOW +#define EALLOW __asm(" EALLOW") +#endif +#ifndef EDIS +#define EDIS __asm(" EDIS") +#endif +#define ESTOP0 __asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#ifndef C28X_BIT0 +#define C28X_BIT0 0x00000001 +#endif + +#ifndef C28X_BIT1 +#define C28X_BIT1 0x00000002 +#endif + +#ifndef C28X_BIT2 +#define C28X_BIT2 0x00000004 +#endif + +#ifndef C28X_BIT3 +#define C28X_BIT3 0x00000008 +#endif + +#ifndef C28X_BIT4 +#define C28X_BIT4 0x00000010 +#endif + +#ifndef C28X_BIT5 +#define C28X_BIT5 0x00000020 +#endif + +#ifndef C28X_BIT6 +#define C28X_BIT6 0x00000040 +#endif + +#ifndef C28X_BIT7 +#define C28X_BIT7 0x00000080 +#endif + +#ifndef C28X_BIT8 +#define C28X_BIT8 0x00000100 +#endif + +#ifndef C28X_BIT9 +#define C28X_BIT9 0x00000200 +#endif + +#ifndef C28X_BIT10 +#define C28X_BIT10 0x00000400 +#endif + +#ifndef C28X_BIT11 +#define C28X_BIT11 0x00000800 +#endif + +#ifndef C28X_BIT12 +#define C28X_BIT12 0x00001000 +#endif + +#ifndef C28X_BIT13 +#define C28X_BIT13 0x00002000 +#endif + +#ifndef C28X_BIT14 +#define C28X_BIT14 0x00004000 +#endif + +#ifndef C28X_BIT15 +#define C28X_BIT15 0x00008000 +#endif + +#ifndef C28X_BIT16 +#define C28X_BIT16 0x00010000 +#endif + +#ifndef C28X_BIT17 +#define C28X_BIT17 0x00020000 +#endif + +#ifndef C28X_BIT18 +#define C28X_BIT18 0x00040000 +#endif + +#ifndef C28X_BIT19 +#define C28X_BIT19 0x00080000 +#endif + +#ifndef C28X_BIT20 +#define C28X_BIT20 0x00100000 +#endif + +#ifndef C28X_BIT21 +#define C28X_BIT21 0x00200000 +#endif + +#ifndef C28X_BIT22 +#define C28X_BIT22 0x00400000 +#endif + +#ifndef C28X_BIT23 +#define C28X_BIT23 0x00800000 +#endif + +#ifndef C28X_BIT24 +#define C28X_BIT24 0x01000000 +#endif + +#ifndef C28X_BIT25 +#define C28X_BIT25 0x02000000 +#endif + +#ifndef C28X_BIT26 +#define C28X_BIT26 0x04000000 +#endif + +#ifndef C28X_BIT27 +#define C28X_BIT27 0x08000000 +#endif + +#ifndef C28X_BIT28 +#define C28X_BIT28 0x10000000 +#endif + +#ifndef C28X_BIT29 +#define C28X_BIT29 0x20000000 +#endif + +#ifndef C28X_BIT30 +#define C28X_BIT30 0x40000000 +#endif + +#ifndef C28X_BIT31 +#define C28X_BIT31 0x80000000 +#endif + +// +// For Portability, User Is Recommended To Use the C99 Standard integer types +// +#if !defined(__TMS320C28XX_CLA__) +#include +#include +#endif //__TMS320C28XX_CLA__ +#include +#include +#include + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +// +// C99 defines boolean type to be _Bool, but this doesn't match the format of +// the other standard integer types. bool_t has been defined to fill this gap. +// +typedef _Bool bool_t; + +// +//used for a bool function return status +// +typedef _Bool status_t; + +#ifndef SUCCESS +#define SUCCESS true +#endif + +#ifndef FAIL +#define FAIL false +#endif + +// +// The following data types are included for compatibility with legacy code, +// they are not recommended for use in new software. Please use the C99 +// types included above +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// The following data types are for use with byte addressable peripherals. +// See compiler documentation on the byte_peripheral type attribute. +// +#ifndef __TMS320C28XX_CLA__ +#if __TI_COMPILER_VERSION__ >= 16006000 +typedef unsigned int bp_16 __attribute__((byte_peripheral)); +typedef unsigned long bp_32 __attribute__((byte_peripheral)); +#endif +#endif + +// +// Include All Peripheral Header Files: +// +#include "F2837xD_adc.h" +#include "F2837xD_analogsubsys.h" +#include "F2837xD_cla.h" +#include "F2837xD_cmpss.h" +#include "F2837xD_cputimer.h" +#include "F2837xD_dac.h" +#include "F2837xD_dcsm.h" +#include "F2837xD_dma.h" +#include "F2837xD_ecap.h" +#include "F2837xD_emif.h" +#include "F2837xD_epwm.h" // Enhanced PWM +#include "F2837xD_epwm_xbar.h" +#include "F2837xD_eqep.h" +#include "F2837xD_flash.h" +#include "F2837xD_gpio.h" // General Purpose I/O Registers +#include "F2837xD_i2c.h" +#include "F2837xD_input_xbar.h" +#include "F2837xD_ipc.h" +#include "F2837xD_mcbsp.h" +#include "F2837xD_memconfig.h" +#include "F2837xD_nmiintrupt.h" // NMI Interrupt Registers +#include "F2837xD_output_xbar.h" +#include "F2837xD_piectrl.h" // PIE Control Registers +#include "F2837xD_pievect.h" +#include "F2837xD_sci.h" +#include "F2837xD_sdfm.h" +#include "F2837xD_spi.h" +#include "F2837xD_sysctrl.h" // System Control/Power Modes +#include "F2837xD_upp.h" +#include "F2837xD_xbar.h" +#include "F2837xD_xint.h" // External Interrupts + +// +// byte_peripheral attribute is only supported on the C28 +// +#ifndef __TMS320C28XX_CLA__ +#if __TI_COMPILER_VERSION__ >= 16006000 +#include "F2837xD_can.h" +#endif +#endif + +#ifdef __cplusplus +} +#endif // extern "C" + +#endif // end of F2837xD_DEVICE_H definition + +// +// End of file. +// diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h new file mode 100644 index 0000000000..3de5b3ca0f --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h @@ -0,0 +1,214 @@ +//########################################################################### +// +// FILE: F2837xD_dma.h +// +// TITLE: DMA Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DMA_H__ +#define __F2837xD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DMA Individual Register Bit Definitions: + +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode + Uint16 ONESHOT:1; // 10 One Shot Mode Bit + Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit + Uint16 rsvd2:2; // 13:12 Reserved + Uint16 DATASIZE:1; // 14 Data Size Mode Bit + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit + Uint16 HALT:1; // 1 Halt Bit + Uint16 SOFTRESET:1; // 2 Soft Reset Bit + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 ERRCLR:1; // 7 Error Clear Bit + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit + Uint16 SYNCFLG:1; // 9 Sync Flag Bit + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit + Uint16 BURSTSTS:1; // 12 Burst Status Bit + Uint16 RUNSTS:1; // 13 Run Status Bit + Uint16 OVRFLG:1; // 14 Overflow Flag Bit + Uint16 rsvd1:1; // 15 Reserved +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 Reserved + Uint16 FREE:1; // 15 Debug Mode Bit +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits + Uint16 rsvd1:1; // 3 Reserved + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // Reserved + Uint16 rsvd1; // Reserved + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // Reserved + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // Reserved + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +//--------------------------------------------------------------------------- +// DMA External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h new file mode 100644 index 0000000000..1fdeb15ec3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h @@ -0,0 +1,203 @@ +//########################################################################### +// +// FILE: F2837xD_ecap.h +// +// TITLE: ECAP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ECAP_H__ +#define __F2837xD_ECAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ECAP Individual Register Bit Definitions: + +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECCLR_BITS { // bits description + Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear + Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear + Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear + Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear + Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear + Uint16 CTROVF:1; // 5 Counter Overflow Status Clear + Uint16 CTR_PRD:1; // 6 Period Equal Status Clear + Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ECCLR_REG { + Uint16 all; + struct ECCLR_BITS bit; +}; + +struct ECFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt + Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt + Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt + Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt + Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt + Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt + Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union ECFRC_REG { + Uint16 all; + struct ECFRC_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time-Stamp Counter + Uint32 CTRPHS; // Counter Phase Offset Value Register + Uint32 CAP1; // Capture 1 Register + Uint32 CAP2; // Capture 2 Register + Uint32 CAP3; // Capture 3 Register + Uint32 CAP4; // Capture 4 Register + Uint16 rsvd1[8]; // Reserved + union ECCTL1_REG ECCTL1; // Capture Control Register 1 + union ECCTL2_REG ECCTL2; // Capture Control Register 2 + union ECEINT_REG ECEINT; // Capture Interrupt Enable Register + union ECFLG_REG ECFLG; // Capture Interrupt Flag Register + union ECCLR_REG ECCLR; // Capture Interrupt Clear Register + union ECFRC_REG ECFRC; // Capture Interrupt Force Register + Uint16 rsvd2[6]; // Reserved +}; + +//--------------------------------------------------------------------------- +// ECAP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; +#endif +#ifdef CPU2 +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h new file mode 100644 index 0000000000..c3246b567c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h @@ -0,0 +1,302 @@ +//########################################################################### +// +// FILE: F2837xD_emif.h +// +// TITLE: EMIF Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EMIF_H__ +#define __F2837xD_EMIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EMIF Individual Register Bit Definitions: + +struct RCSR_BITS { // bits description + Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. + Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. + Uint16 MODULE_ID:14; // 29:16 EMIF module ID. + Uint16 FR:1; // 30 EMIF is running in full rate or half rate. + Uint16 BE:1; // 31 EMIF endian mode. +}; + +union RCSR_REG { + Uint32 all; + struct RCSR_BITS bit; +}; + +struct ASYNC_WCCR_BITS { // bits description + Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:2; // 17:16 Reserved + Uint16 rsvd3:2; // 19:18 Reserved + Uint16 rsvd4:2; // 21:20 Reserved + Uint16 rsvd5:2; // 23:22 Reserved + Uint16 rsvd6:4; // 27:24 Reserved + Uint16 WP0:1; // 28 Polarity for EMxWAIT. + Uint16 rsvd7:1; // 29 Reserved + Uint16 rsvd8:1; // 30 Reserved + Uint16 rsvd9:1; // 31 Reserved +}; + +union ASYNC_WCCR_REG { + Uint32 all; + struct ASYNC_WCCR_BITS bit; +}; + +struct SDRAM_CR_BITS { // bits description + Uint16 PAGESIGE:3; // 2:0 Page Size. + Uint16 rsvd1:1; // 3 Reserved + Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. + Uint16 rsvd2:1; // 7 Reserved + Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. + Uint16 CL:3; // 11:9 CAS Latency. + Uint16 rsvd3:1; // 12 Reserved + Uint16 rsvd4:1; // 13 Reserved + Uint16 NM:1; // 14 Narrow Mode. + Uint16 rsvd5:1; // 15 Reserved + Uint16 rsvd6:1; // 16 Reserved + Uint16 rsvd7:2; // 18:17 Reserved + Uint16 rsvd8:1; // 19 Reserved + Uint16 rsvd9:3; // 22:20 Reserved + Uint16 rsvd10:3; // 25:23 Reserved + Uint16 rsvd11:3; // 28:26 Reserved + Uint16 PDWR:1; // 29 Perform refreshes during Power Down. + Uint16 PD:1; // 30 Power Down. + Uint16 SR:1; // 31 Self Refresh. +}; + +union SDRAM_CR_REG { + Uint32 all; + struct SDRAM_CR_BITS bit; +}; + +struct SDRAM_RCR_BITS { // bits description + Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. + Uint16 rsvd1:3; // 15:13 Reserved + Uint16 rsvd2:3; // 18:16 Reserved + Uint16 rsvd3:13; // 31:19 Reserved +}; + +union SDRAM_RCR_REG { + Uint32 all; + struct SDRAM_RCR_BITS bit; +}; + +struct ASYNC_CS2_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS2_CR_REG { + Uint32 all; + struct ASYNC_CS2_CR_BITS bit; +}; + +struct ASYNC_CS3_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS3_CR_REG { + Uint32 all; + struct ASYNC_CS3_CR_BITS bit; +}; + +struct ASYNC_CS4_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS4_CR_REG { + Uint32 all; + struct ASYNC_CS4_CR_BITS bit; +}; + +struct SDRAM_TR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. + Uint16 rsvd2:1; // 7 Reserved + Uint16 T_RC:4; // 11:8 Activate to Activate timing . + Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. + Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. + Uint16 rsvd3:1; // 19 Reserved + Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. + Uint16 rsvd4:1; // 23 Reserved + Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. + Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing +}; + +union SDRAM_TR_REG { + Uint32 all; + struct SDRAM_TR_BITS bit; +}; + +struct SDR_EXT_TMNG_BITS { // bits description + Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. + Uint16 rsvd1:11; // 15:5 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SDR_EXT_TMNG_REG { + Uint32 all; + struct SDR_EXT_TMNG_BITS bit; +}; + +struct INT_RAW_BITS { // bits description + Uint16 AT:1; // 0 Asynchronous Timeout. + Uint16 LT:1; // 1 Line Trap. + Uint16 WR:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_RAW_REG { + Uint32 all; + struct INT_RAW_BITS bit; +}; + +struct INT_MSK_BITS { // bits description + Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. + Uint16 LT_MASKED:1; // 1 Line Trap. + Uint16 WR_MASKED:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_REG { + Uint32 all; + struct INT_MSK_BITS bit; +}; + +struct INT_MSK_SET_BITS { // bits description + Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. + Uint16 LT_MASK_SET:1; // 1 Line Trap. + Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_SET_REG { + Uint32 all; + struct INT_MSK_SET_BITS bit; +}; + +struct INT_MSK_CLR_BITS { // bits description + Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. + Uint16 LT_MASK_CLR:1; // 1 Line Trap. + Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_CLR_REG { + Uint32 all; + struct INT_MSK_CLR_BITS bit; +}; + +struct EMIF_REGS { + union RCSR_REG RCSR; // Revision Code and Status Register + union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register + union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register + union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register + union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register + union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register + union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register + Uint16 rsvd1[2]; // Reserved + union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register + Uint16 rsvd2[6]; // Reserved + Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register + Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register + Uint16 rsvd3[2]; // Reserved + union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register + union INT_RAW_REG INT_RAW; // Interrupt Raw Register + union INT_MSK_REG INT_MSK; // Interrupt Masked Register + union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register + union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register + Uint16 rsvd4[72]; // Reserved +}; + +//--------------------------------------------------------------------------- +// EMIF External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EMIF_REGS Emif1Regs; +extern volatile struct EMIF_REGS Emif2Regs; +#endif +#ifdef CPU2 +extern volatile struct EMIF_REGS Emif1Regs; +extern volatile struct EMIF_REGS Emif2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h new file mode 100644 index 0000000000..bd784afd49 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h @@ -0,0 +1,1240 @@ +//########################################################################### +// +// FILE: F2837xD_epwm.h +// +// TITLE: EPWM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EPWM_H__ +#define __F2837xD_EPWM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EPWM Individual Register Bit Definitions: + +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase Load Enable + Uint16 PRDLD:1; // 3 Active Period Load + Uint16 SYNCOSEL:2; // 5:4 Sync Output Select + Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse + Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler + Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler + Uint16 PHSDIR:1; // 13 Phase Direction Bit + Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +struct TBCTL2_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode + Uint16 OSHTSYNC:1; // 7 One shot sync + Uint16 rsvd3:4; // 11:8 Reserved + Uint16 SYNCOSELX:2; // 13:12 Syncout selection + Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event +}; + +union TBCTL2_REG { + Uint16 all; + struct TBCTL2_BITS bit; +}; + +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter Direction Status + Uint16 SYNCI:1; // 1 External Input Sync Status + Uint16 CTRMAX:1; // 2 Counter Max Latched Status + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 1:0 Active Compare A Load + Uint16 LOADBMODE:2; // 3:2 Active Compare B Load + Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode + Uint16 rsvd2:1; // 7 Reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status + Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC + Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC + Uint16 rsvd3:2; // 15:14 Reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +struct CMPCTL2_BITS { // bits description + Uint16 LOADCMODE:2; // 1:0 Active Compare C Load + Uint16 LOADDMODE:2; // 3:2 Active Compare D load + Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode + Uint16 rsvd2:3; // 9:7 Reserved + Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC + Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC + Uint16 rsvd3:2; // 15:14 Reserved +}; + +union CMPCTL2_REG { + Uint16 all; + struct CMPCTL2_BITS bit; +}; + +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode + Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode + Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode + Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode + Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control + Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control + Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +struct DBCTL2_BITS { // bits description + Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select + Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union DBCTL2_REG { + Uint16 all; + struct DBCTL2_BITS bit; +}; + +struct AQCTL_BITS { // bits description + Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select + Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select + Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode + Uint16 rsvd2:1; // 7 Reserved + Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC + Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC + Uint16 rsvd3:4; // 15:12 Reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +struct AQTSRCSEL_BITS { // bits description + Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits + Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQTSRCSEL_REG { + Uint16 all; + struct AQTSRCSEL_BITS bit; +}; + +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct VCAPCTL_BITS { // bits description + Uint16 VCAPE:1; // 0 Valley Capture mode + Uint16 VCAPSTART:1; // 1 Valley Capture Start + Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable + Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select + Uint16 rsvd2:5; // 15:11 Reserved +}; + +union VCAPCTL_REG { + Uint16 all; + struct VCAPCTL_BITS bit; +}; + +struct VCNTCFG_BITS { // bits description + Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection + Uint16 rsvd1:3; // 6:4 Reserved + Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit + Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection + Uint16 rsvd2:3; // 14:12 Reserved + Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit +}; + +union VCNTCFG_REG { + Uint16 all; + struct VCNTCFG_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits + Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits + Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits + Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit + Uint16 AUTOCONV:1; // 6 Autoconversion Bit + Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit + Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits + Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits + Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits + Uint16 rsvd1:1; // 13 Reserved + Uint16 rsvd2:2; // 15:14 Reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct HRPWR_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 rsvd2:1; // 2 Reserved + Uint16 rsvd3:1; // 3 Reserved + Uint16 rsvd4:1; // 4 Reserved + Uint16 rsvd5:1; // 5 Reserved + Uint16 rsvd6:4; // 9:6 Reserved + Uint16 rsvd7:5; // 14:10 Reserved + Uint16 CALPWRON:1; // 15 Calibration Power On +}; + +union HRPWR_REG { + Uint16 all; + struct HRPWR_BITS bit; +}; + +struct HRMSTEP_BITS { // bits description + Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union HRMSTEP_REG { + Uint16 all; + struct HRMSTEP_BITS bit; +}; + +struct HRCNFG2_BITS { // bits description + Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits + Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits + Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits + Uint16 rsvd1:8; // 13:6 Reserved + Uint16 rsvd2:1; // 14 Reserved + Uint16 rsvd3:1; // 15 Reserved +}; + +union HRCNFG2_REG { + Uint16 all; + struct HRCNFG2_BITS bit; +}; + +struct HRPCTL_BITS { // bits description + Uint16 HRPE:1; // 0 High Resolution Period Enable + Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select + Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union HRPCTL_REG { + Uint16 all; + struct HRPCTL_BITS bit; +}; + +struct TRREM_BITS { // bits description + Uint16 TRREM:11; // 10:0 Translator Remainder Bits + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union TRREM_REG { + Uint16 all; + struct TRREM_BITS bit; +}; + +struct GLDCTL_BITS { // bits description + Uint16 GLD:1; // 0 Global Shadow to Active load event control + Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection + Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register + Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register + Uint16 rsvd2:3; // 15:13 Reserved +}; + +union GLDCTL_REG { + Uint16 all; + struct GLDCTL_BITS bit; +}; + +struct GLDCFG_BITS { // bits description + Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR + Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR + Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR + Uint16 CMPC:1; // 3 Global load event configuration for CMPC + Uint16 CMPD:1; // 4 Global load event configuration for CMPD + Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR + Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR + Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL + Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 + Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 + Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union GLDCFG_REG { + Uint16 all; + struct GLDCFG_BITS bit; +}; + +struct EPWMXLINK_BITS { // bits description + Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link + Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link + Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link + Uint16 CMPCLINK:4; // 15:12 CMPC Link + Uint16 CMPDLINK:4; // 19:16 CMPD Link + Uint16 rsvd1:8; // 27:20 Reserved + Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link +}; + +union EPWMXLINK_REG { + Uint32 all; + struct EPWMXLINK_BITS bit; +}; + +struct EPWMREV_BITS { // bits description + Uint16 REV:8; // 7:0 EPWM Silicon Revision bits + Uint16 TYPE:8; // 15:8 EPWM Type Bits +}; + +union EPWMREV_REG { + Uint16 all; + struct EPWMREV_BITS bit; +}; + +struct AQCTLA_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A Up + Uint16 CAD:2; // 7:6 Action Counter = Compare A Down + Uint16 CBU:2; // 9:8 Action Counter = Compare B Up + Uint16 CBD:2; // 11:10 Action Counter = Compare B Down + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union AQCTLA_REG { + Uint16 all; + struct AQCTLA_BITS bit; +}; + +struct AQCTLA2_BITS { // bits description + Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count + Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count + Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count + Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQCTLA2_REG { + Uint16 all; + struct AQCTLA2_BITS bit; +}; + +struct AQCTLB_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A Up + Uint16 CAD:2; // 7:6 Action Counter = Compare A Down + Uint16 CBU:2; // 9:8 Action Counter = Compare B Up + Uint16 CBD:2; // 11:10 Action Counter = Compare B Down + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union AQCTLB_REG { + Uint16 all; + struct AQCTLB_BITS bit; +}; + +struct AQCTLB2_BITS { // bits description + Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count + Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count + Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count + Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQCTLB2_REG { + Uint16 all; + struct AQCTLB2_BITS bit; +}; + +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked + Uint16 OTSFA:1; // 2 One-time SW Force A Output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked + Uint16 OTSFB:1; // 5 One-time SW Force A Output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +struct DBREDHR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:7; // 7:1 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits +}; + +union DBREDHR_REG { + Uint16 all; + struct DBREDHR_BITS bit; +}; + +struct DBRED_BITS { // bits description + Uint16 DBRED:14; // 13:0 Rising edge delay value + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union DBRED_REG { + Uint16 all; + struct DBRED_BITS bit; +}; + +struct DBFEDHR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:7; // 7:1 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits +}; + +union DBFEDHR_REG { + Uint16 all; + struct DBFEDHR_BITS bit; +}; + +struct DBFED_BITS { // bits description + Uint16 DBFED:14; // 13:0 Falling edge delay value + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union DBFED_REG { + Uint16 all; + struct DBFED_BITS bit; +}; + +struct TBPHS_BITS { // bits description + Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) + Uint16 TBPHS:16; // 31:16 Phase Offset Register +}; + +union TBPHS_REG { + Uint32 all; + struct TBPHS_BITS bit; +}; + +struct CMPA_BITS { // bits description + Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register + Uint16 CMPA:16; // 31:16 Compare A Register +}; + +union CMPA_REG { + Uint32 all; + struct CMPA_BITS bit; +}; + +struct CMPB_BITS { // bits description + Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits + Uint16 CMPB:16; // 31:16 Compare B Register +}; + +union CMPB_REG { + Uint32 all; + struct CMPB_BITS bit; +}; + +struct GLDCTL2_BITS { // bits description + Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode + Uint16 GFRCLD:1; // 1 Force reload event in one shot mode + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union GLDCTL2_REG { + Uint16 all; + struct GLDCTL2_BITS bit; +}; + +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select + Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select + Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +struct TZDCSEL_BITS { // bits description + Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 + Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 + Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 + Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZDCSEL_REG { + Uint16 all; + struct TZDCSEL_BITS bit; +}; + +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 + Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 + Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 + Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +struct TZCTL2_BITS { // bits description + Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP + Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN + Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP + Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN + Uint16 rsvd1:3; // 14:12 Reserved + Uint16 ETZE:1; // 15 TZCTL2 Enable +}; + +union TZCTL2_REG { + Uint16 all; + struct TZCTL2_BITS bit; +}; + +struct TZCTLDCA_BITS { // bits description + Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP + Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN + Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP + Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTLDCA_REG { + Uint16 all; + struct TZCTLDCA_BITS bit; +}; + +struct TZCTLDCB_BITS { // bits description + Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP + Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN + Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP + Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTLDCB_REG { + Uint16 all; + struct TZCTLDCB_BITS bit; +}; + +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable + Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable + Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable + Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Int Status Flag + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag + Uint16 OST:1; // 2 Trip Zones One Shot Flag + Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag + Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag + Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag + Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +struct TZCBCFLG_BITS { // bits description + Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch + Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch + Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch + Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch + Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch + Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch + Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 + Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZCBCFLG_REG { + Uint16 all; + struct TZCBCFLG_BITS bit; +}; + +struct TZOSTFLG_BITS { // bits description + Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch + Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch + Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch + Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch + Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch + Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch + Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 + Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZOSTFLG_REG { + Uint16 all; + struct TZOSTFLG_BITS bit; +}; + +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global Interrupt Clear Flag + Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear + Uint16 OST:1; // 2 One-Shot Flag Clear + Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear + Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear + Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear + Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear + Uint16 rsvd1:7; // 13:7 Reserved + Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +struct TZCBCCLR_BITS { // bits description + Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch + Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch + Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch + Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch + Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch + Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch + Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC + Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZCBCCLR_REG { + Uint16 all; + struct TZCBCCLR_BITS bit; +}; + +struct TZOSTCLR_BITS { // bits description + Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch + Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch + Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch + Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch + Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch + Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch + Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST + Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZOSTCLR_REG { + Uint16 all; + struct TZOSTCLR_BITS bit; +}; + +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event + Uint16 OST:1; // 2 Force Trip Zones One Shot Event + Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 + Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 + Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 + Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select + Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select + Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select + Uint16 rsvd1:1; // 7 Reserved + Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select + Uint16 SOCAEN:1; // 11 Start of Conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select + Uint16 SOCBEN:1; // 15 Start of Conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits + Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +struct ETINTPS_BITS { // bits description + Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select + Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ETINTPS_REG { + Uint16 all; + struct ETINTPS_BITS bit; +}; + +struct ETSOCPS_BITS { // bits description + Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select + Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register + Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select + Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register +}; + +union ETSOCPS_REG { + Uint16 all; + struct ETSOCPS_BITS bit; +}; + +struct ETCNTINITCTL_BITS { // bits description + Uint16 rsvd1:10; // 9:0 Reserved + Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force + Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force + Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force + Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable + Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable + Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable +}; + +union ETCNTINITCTL_REG { + Uint16 all; + struct ETCNTINITCTL_BITS bit; +}; + +struct ETCNTINIT_BITS { // bits description + Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits + Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits + Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ETCNTINIT_REG { + Uint16 all; + struct ETCNTINIT_BITS bit; +}; + +struct DCTRIPSEL_BITS { // bits description + Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select + Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select + Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select + Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select +}; + +union DCTRIPSEL_REG { + Uint16 all; + struct DCTRIPSEL_BITS bit; +}; + +struct DCACTL_BITS { // bits description + Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal + Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal + Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable + Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 rsvd3:1; // 7 Reserved + Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal + Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:2; // 14:13 Reserved + Uint16 rsvd7:1; // 15 Reserved +}; + +union DCACTL_REG { + Uint16 all; + struct DCACTL_BITS bit; +}; + +struct DCBCTL_BITS { // bits description + Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal + Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal + Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable + Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 rsvd3:1; // 7 Reserved + Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal + Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:2; // 14:13 Reserved + Uint16 rsvd7:1; // 15 Reserved +}; + +union DCBCTL_REG { + Uint16 all; + struct DCBCTL_BITS bit; +}; + +struct DCFCTL_BITS { // bits description + Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select + Uint16 BLANKE:1; // 2 Blanking Enable/Disable + Uint16 BLANKINV:1; // 3 Blanking Window Inversion + Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment + Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select + Uint16 rsvd1:1; // 7 Reserved + Uint16 EDGEMODE:2; // 9:8 Edge Mode + Uint16 EDGECOUNT:3; // 12:10 Edge Count + Uint16 EDGESTATUS:3; // 15:13 Edge Status +}; + +union DCFCTL_REG { + Uint16 all; + struct DCFCTL_BITS bit; +}; + +struct DCCAPCTL_BITS { // bits description + Uint16 CAPE:1; // 0 Counter Capture Enable + Uint16 SHDWMODE:1; // 1 Counter Capture Mode + Uint16 rsvd1:11; // 12:2 Reserved + Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event + Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag + Uint16 CAPMODE:1; // 15 Counter Capture Mode +}; + +union DCCAPCTL_REG { + Uint16 all; + struct DCCAPCTL_BITS bit; +}; + +struct DCAHTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCAHTRIPSEL_REG { + Uint16 all; + struct DCAHTRIPSEL_BITS bit; +}; + +struct DCALTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCALTRIPSEL_REG { + Uint16 all; + struct DCALTRIPSEL_BITS bit; +}; + +struct DCBHTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCBHTRIPSEL_REG { + Uint16 all; + struct DCBHTRIPSEL_BITS bit; +}; + +struct DCBLTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCBLTRIPSEL_REG { + Uint16 all; + struct DCBLTRIPSEL_BITS bit; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // Time Base Control Register + union TBCTL2_REG TBCTL2; // Time Base Control Register 2 + Uint16 rsvd1[2]; // Reserved + Uint16 TBCTR; // Time Base Counter Register + union TBSTS_REG TBSTS; // Time Base Status Register + Uint16 rsvd2[2]; // Reserved + union CMPCTL_REG CMPCTL; // Counter Compare Control Register + union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 + Uint16 rsvd3[2]; // Reserved + union DBCTL_REG DBCTL; // Dead-Band Generator Control Register + union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 + Uint16 rsvd4[2]; // Reserved + union AQCTL_REG AQCTL; // Action Qualifier Control Register + union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register + Uint16 rsvd5[2]; // Reserved + union PCCTL_REG PCCTL; // PWM Chopper Control Register + Uint16 rsvd6[3]; // Reserved + union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register + union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register + Uint16 rsvd7[6]; // Reserved + union HRCNFG_REG HRCNFG; // HRPWM Configuration Register + union HRPWR_REG HRPWR; // HRPWM Power Register + Uint16 rsvd8[4]; // Reserved + union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register + union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register + Uint16 rsvd9[5]; // Reserved + union HRPCTL_REG HRPCTL; // High Resolution Period Control Register + union TRREM_REG TRREM; // Translator High Resolution Remainder Register + Uint16 rsvd10[5]; // Reserved + union GLDCTL_REG GLDCTL; // Global PWM Load Control Register + union GLDCFG_REG GLDCFG; // Global PWM Load Config Register + Uint16 rsvd11[2]; // Reserved + union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register + Uint16 rsvd12[4]; // Reserved + union EPWMREV_REG EPWMREV; // EPWM Revision Register + Uint16 rsvd13; // Reserved + union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A + union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A + union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B + union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B + Uint16 rsvd14[3]; // Reserved + union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register + Uint16 rsvd15; // Reserved + union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register + Uint16 rsvd16[6]; // Reserved + union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register + union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register + union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register + union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register + Uint16 rsvd17[12]; // Reserved + union TBPHS_REG TBPHS; // Time Base Phase High + Uint16 TBPRDHR; // Time Base Period High Resolution Register + Uint16 TBPRD; // Time Base Period Register + Uint16 rsvd18[6]; // Reserved + union CMPA_REG CMPA; // Counter Compare A Register + union CMPB_REG CMPB; // Compare B Register + Uint16 rsvd19; // Reserved + Uint16 CMPC; // Counter Compare C Register + Uint16 rsvd20; // Reserved + Uint16 CMPD; // Counter Compare D Register + Uint16 rsvd21[2]; // Reserved + union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 + Uint16 rsvd22[2]; // Reserved + Uint16 SWVDELVAL; // Software Valley Mode Delay Register + Uint16 rsvd23[8]; // Reserved + union TZSEL_REG TZSEL; // Trip Zone Select Register + Uint16 rsvd24; // Reserved + union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register + Uint16 rsvd25; // Reserved + union TZCTL_REG TZCTL; // Trip Zone Control Register + union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register + union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A + union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B + Uint16 rsvd26[5]; // Reserved + union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register + Uint16 rsvd27[5]; // Reserved + union TZFLG_REG TZFLG; // Trip Zone Flag Register + union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register + union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register + Uint16 rsvd28; // Reserved + union TZCLR_REG TZCLR; // Trip Zone Clear Register + union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register + union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register + Uint16 rsvd29; // Reserved + union TZFRC_REG TZFRC; // Trip Zone Force Register + Uint16 rsvd30[8]; // Reserved + union ETSEL_REG ETSEL; // Event Trigger Selection Register + Uint16 rsvd31; // Reserved + union ETPS_REG ETPS; // Event Trigger Pre-Scale Register + Uint16 rsvd32; // Reserved + union ETFLG_REG ETFLG; // Event Trigger Flag Register + Uint16 rsvd33; // Reserved + union ETCLR_REG ETCLR; // Event Trigger Clear Register + Uint16 rsvd34; // Reserved + union ETFRC_REG ETFRC; // Event Trigger Force Register + Uint16 rsvd35; // Reserved + union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register + Uint16 rsvd36; // Reserved + union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register + Uint16 rsvd37; // Reserved + union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register + Uint16 rsvd38; // Reserved + union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register + Uint16 rsvd39[11]; // Reserved + union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register + Uint16 rsvd40[2]; // Reserved + union DCACTL_REG DCACTL; // Digital Compare A Control Register + union DCBCTL_REG DCBCTL; // Digital Compare B Control Register + Uint16 rsvd41[2]; // Reserved + union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register + union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register + Uint16 DCFOFFSET; // Digital Compare Filter Offset Register + Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register + Uint16 DCFWINDOW; // Digital Compare Filter Window Register + Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register + Uint16 rsvd42[2]; // Reserved + Uint16 DCCAP; // Digital Compare Counter Capture Register + Uint16 rsvd43[2]; // Reserved + union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select + union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select + union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select + union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select + Uint16 rsvd44[39]; // Reserved + Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register + Uint16 VCNTVAL; // Hardware Valley Counter Register + Uint16 rsvd45; // Reserved +}; + +//--------------------------------------------------------------------------- +// EPWM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; +extern volatile struct EPWM_REGS EPwm7Regs; +extern volatile struct EPWM_REGS EPwm8Regs; +extern volatile struct EPWM_REGS EPwm9Regs; +extern volatile struct EPWM_REGS EPwm10Regs; +extern volatile struct EPWM_REGS EPwm11Regs; +extern volatile struct EPWM_REGS EPwm12Regs; +#endif +#ifdef CPU2 +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; +extern volatile struct EPWM_REGS EPwm7Regs; +extern volatile struct EPWM_REGS EPwm8Regs; +extern volatile struct EPWM_REGS EPwm9Regs; +extern volatile struct EPWM_REGS EPwm10Regs; +extern volatile struct EPWM_REGS EPwm11Regs; +extern volatile struct EPWM_REGS EPwm12Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h new file mode 100644 index 0000000000..47f85e18fe --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h @@ -0,0 +1,832 @@ +//########################################################################### +// +// FILE: F2837xD_epwm_xbar.h +// +// TITLE: EPWM_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EPWM_XBAR_H__ +#define __F2837xD_EPWM_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EPWM_XBAR Individual Register Bit Definitions: + +struct TRIP4MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR +}; + +union TRIP4MUX0TO15CFG_REG { + Uint32 all; + struct TRIP4MUX0TO15CFG_BITS bit; +}; + +struct TRIP4MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR +}; + +union TRIP4MUX16TO31CFG_REG { + Uint32 all; + struct TRIP4MUX16TO31CFG_BITS bit; +}; + +struct TRIP5MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR +}; + +union TRIP5MUX0TO15CFG_REG { + Uint32 all; + struct TRIP5MUX0TO15CFG_BITS bit; +}; + +struct TRIP5MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR +}; + +union TRIP5MUX16TO31CFG_REG { + Uint32 all; + struct TRIP5MUX16TO31CFG_BITS bit; +}; + +struct TRIP7MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR +}; + +union TRIP7MUX0TO15CFG_REG { + Uint32 all; + struct TRIP7MUX0TO15CFG_BITS bit; +}; + +struct TRIP7MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR +}; + +union TRIP7MUX16TO31CFG_REG { + Uint32 all; + struct TRIP7MUX16TO31CFG_BITS bit; +}; + +struct TRIP8MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR +}; + +union TRIP8MUX0TO15CFG_REG { + Uint32 all; + struct TRIP8MUX0TO15CFG_BITS bit; +}; + +struct TRIP8MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR +}; + +union TRIP8MUX16TO31CFG_REG { + Uint32 all; + struct TRIP8MUX16TO31CFG_BITS bit; +}; + +struct TRIP9MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR +}; + +union TRIP9MUX0TO15CFG_REG { + Uint32 all; + struct TRIP9MUX0TO15CFG_BITS bit; +}; + +struct TRIP9MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR +}; + +union TRIP9MUX16TO31CFG_REG { + Uint32 all; + struct TRIP9MUX16TO31CFG_BITS bit; +}; + +struct TRIP10MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR +}; + +union TRIP10MUX0TO15CFG_REG { + Uint32 all; + struct TRIP10MUX0TO15CFG_BITS bit; +}; + +struct TRIP10MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR +}; + +union TRIP10MUX16TO31CFG_REG { + Uint32 all; + struct TRIP10MUX16TO31CFG_BITS bit; +}; + +struct TRIP11MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR +}; + +union TRIP11MUX0TO15CFG_REG { + Uint32 all; + struct TRIP11MUX0TO15CFG_BITS bit; +}; + +struct TRIP11MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR +}; + +union TRIP11MUX16TO31CFG_REG { + Uint32 all; + struct TRIP11MUX16TO31CFG_BITS bit; +}; + +struct TRIP12MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR +}; + +union TRIP12MUX0TO15CFG_REG { + Uint32 all; + struct TRIP12MUX0TO15CFG_BITS bit; +}; + +struct TRIP12MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR +}; + +union TRIP12MUX16TO31CFG_REG { + Uint32 all; + struct TRIP12MUX16TO31CFG_BITS bit; +}; + +struct TRIP4MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR +}; + +union TRIP4MUXENABLE_REG { + Uint32 all; + struct TRIP4MUXENABLE_BITS bit; +}; + +struct TRIP5MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR +}; + +union TRIP5MUXENABLE_REG { + Uint32 all; + struct TRIP5MUXENABLE_BITS bit; +}; + +struct TRIP7MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR +}; + +union TRIP7MUXENABLE_REG { + Uint32 all; + struct TRIP7MUXENABLE_BITS bit; +}; + +struct TRIP8MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR +}; + +union TRIP8MUXENABLE_REG { + Uint32 all; + struct TRIP8MUXENABLE_BITS bit; +}; + +struct TRIP9MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR +}; + +union TRIP9MUXENABLE_REG { + Uint32 all; + struct TRIP9MUXENABLE_BITS bit; +}; + +struct TRIP10MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR +}; + +union TRIP10MUXENABLE_REG { + Uint32 all; + struct TRIP10MUXENABLE_BITS bit; +}; + +struct TRIP11MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR +}; + +union TRIP11MUXENABLE_REG { + Uint32 all; + struct TRIP11MUXENABLE_BITS bit; +}; + +struct TRIP12MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR +}; + +union TRIP12MUXENABLE_REG { + Uint32 all; + struct TRIP12MUXENABLE_BITS bit; +}; + +struct TRIPOUTINV_BITS { // bits description + Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR + Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR + Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR + Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR + Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR + Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR + Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR + Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union TRIPOUTINV_REG { + Uint32 all; + struct TRIPOUTINV_BITS bit; +}; + +struct TRIPLOCK_BITS { // bits description + Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Write protection KEY +}; + +union TRIPLOCK_REG { + Uint32 all; + struct TRIPLOCK_BITS bit; +}; + +struct EPWM_XBAR_REGS { + union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 + union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 + union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 + union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 + union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 + union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 + union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 + union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 + union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 + union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 + union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 + union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 + union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 + union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 + union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 + union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 + union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 + union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 + union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 + union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 + union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 + union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 + union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 + union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 + Uint16 rsvd1[8]; // Reserved + union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register + Uint16 rsvd2[4]; // Reserved + union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register +}; + +//--------------------------------------------------------------------------- +// EPWM_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h new file mode 100644 index 0000000000..f37da095a9 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h @@ -0,0 +1,267 @@ +//########################################################################### +// +// FILE: F2837xD_eqep.h +// +// TITLE: EQEP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EQEP_H__ +#define __F2837xD_EQEP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EQEP Individual Register Bit Definitions: + +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter + Uint16 XCR:1; // 11 External Clock Rate + Uint16 SPSEL:1; // 12 Sync output pin selection + Uint16 SOEN:1; // 13 Sync output-enable + Uint16 QSRC:2; // 15:14 Position-counter source selection +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature postotion counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Postion counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position event prescaler + Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler + Uint16 rsvd1:8; // 14:7 Reserved + Uint16 CEN:1; // 15 Enable eQEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare of shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error interrupt enable + Uint16 QPE:1; // 2 Quadrature phase error interrupt enable + Uint16 QDC:1; // 3 Quadrature direction change interrupt enable + Uint16 WTO:1; // 4 Watchdog time out interrupt enable + Uint16 PCU:1; // 5 Position counter underflow interrupt enable + Uint16 PCO:1; // 6 Position counter overflow interrupt enable + Uint16 PCR:1; // 7 Position-compare ready interrupt enable + Uint16 PCM:1; // 8 Position-compare match interrupt enable + Uint16 SEL:1; // 9 Strobe event latch interrupt enable + Uint16 IEL:1; // 10 Index event latch interrupt enable + Uint16 UTO:1; // 11 Unit time out interrupt enable + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt status flag + Uint16 PCE:1; // 1 Position counter error interrupt flag + Uint16 PHE:1; // 2 Quadrature phase error interrupt flag + Uint16 QDC:1; // 3 Quadrature direction change interrupt flag + Uint16 WTO:1; // 4 Watchdog timeout interrupt flag + Uint16 PCU:1; // 5 Position counter underflow interrupt flag + Uint16 PCO:1; // 6 Position counter overflow interrupt flag + Uint16 PCR:1; // 7 Position-compare ready interrupt flag + Uint16 PCM:1; // 8 eQEP compare match event interrupt flag + Uint16 SEL:1; // 9 Strobe event latch interrupt flag + Uint16 IEL:1; // 10 Index event latch interrupt flag + Uint16 UTO:1; // 11 Unit time out interrupt flag + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +struct QCLR_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt clear flag + Uint16 PCE:1; // 1 Clear position counter error interrupt flag + Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag + Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag + Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag + Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag + Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag + Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag + Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag + Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag + Uint16 IEL:1; // 10 Clear index event latch interrupt flag + Uint16 UTO:1; // 11 Clear unit time out interrupt flag + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union QCLR_REG { + Uint16 all; + struct QCLR_BITS bit; +}; + +struct QFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 PCE:1; // 1 Force position counter error interrupt + Uint16 PHE:1; // 2 Force quadrature phase error interrupt + Uint16 QDC:1; // 3 Force quadrature direction change interrupt + Uint16 WTO:1; // 4 Force watchdog time out interrupt + Uint16 PCU:1; // 5 Force position counter underflow interrupt + Uint16 PCO:1; // 6 Force position counter overflow interrupt + Uint16 PCR:1; // 7 Force position-compare ready interrupt + Uint16 PCM:1; // 8 Force position-compare match interrupt + Uint16 SEL:1; // 9 Force strobe event latch interrupt + Uint16 IEL:1; // 10 Force index event latch interrupt + Uint16 UTO:1; // 11 Force unit time out interrupt + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error flag. + Uint16 FIMF:1; // 1 First index marker flag + Uint16 CDEF:1; // 2 Capture direction error flag + Uint16 COEF:1; // 3 Capture overflow error flag + Uint16 QDLF:1; // 4 eQEP direction latch flag + Uint16 QDF:1; // 5 Quadrature direction flag + Uint16 FIDF:1; // 6 The first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position Counter + Uint32 QPOSINIT; // Position Counter Init + Uint32 QPOSMAX; // Maximum Position Count + Uint32 QPOSCMP; // Position Compare + Uint32 QPOSILAT; // Index Position Latch + Uint32 QPOSSLAT; // Strobe Position Latch + Uint32 QPOSLAT; // Position Latch + Uint32 QUTMR; // QEP Unit Timer + Uint32 QUPRD; // QEP Unit Period + Uint16 QWDTMR; // QEP Watchdog Timer + Uint16 QWDPRD; // QEP Watchdog Period + union QDECCTL_REG QDECCTL; // Quadrature Decoder Control + union QEPCTL_REG QEPCTL; // QEP Control + union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control + union QPOSCTL_REG QPOSCTL; // Position Compare Control + union QEINT_REG QEINT; // QEP Interrupt Control + union QFLG_REG QFLG; // QEP Interrupt Flag + union QCLR_REG QCLR; // QEP Interrupt Clear + union QFRC_REG QFRC; // QEP Interrupt Force + union QEPSTS_REG QEPSTS; // QEP Status + Uint16 QCTMR; // QEP Capture Timer + Uint16 QCPRD; // QEP Capture Period + Uint16 QCTMRLAT; // QEP Capture Latch + Uint16 QCPRDLAT; // QEP Capture Period Latch + Uint16 rsvd1; // Reserved +}; + +//--------------------------------------------------------------------------- +// EQEP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; +extern volatile struct EQEP_REGS EQep3Regs; +#endif +#ifdef CPU2 +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; +extern volatile struct EQEP_REGS EQep3Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h new file mode 100644 index 0000000000..2882c6a96d --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h @@ -0,0 +1,376 @@ +//########################################################################### +// +// FILE: F2837xD_flash.h +// +// TITLE: FLASH Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_FLASH_H__ +#define __F2837xD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// FLASH Individual Register Bit Definitions: + +struct FRDCNTL_BITS { // bits description + Uint16 rsvd1:8; // 7:0 Reserved + Uint16 RWAIT:4; // 11:8 Random Read Waitstate + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union FRDCNTL_REG { + Uint32 all; + struct FRDCNTL_BITS bit; +}; + +struct FBAC_BITS { // bits description + Uint16 VREADST:8; // 7:0 VREAD Setup Time Count + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBAC_REG { + Uint32 all; + struct FBAC_BITS bit; +}; + +struct FBFALLBACK_BITS { // bits description + Uint16 BNKPWR0:2; // 1:0 Bank Power Mode + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBFALLBACK_REG { + Uint32 all; + struct FBFALLBACK_BITS bit; +}; + +struct FBPRDY_BITS { // bits description + Uint16 BANKRDY:1; // 0 Flash Bank Active Power State + Uint16 rsvd1:14; // 14:1 Reserved + Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBPRDY_REG { + Uint32 all; + struct FBPRDY_BITS bit; +}; + +struct FPAC1_BITS { // bits description + Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count + Uint16 rsvd2:4; // 31:28 Reserved +}; + +union FPAC1_REG { + Uint32 all; + struct FPAC1_BITS bit; +}; + +struct FMSTAT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status + Uint16 CSTAT:1; // 4 Command Fail Status + Uint16 INVDAT:1; // 5 Invalid Data + Uint16 PGM:1; // 6 Program Operation Status + Uint16 ERS:1; // 7 Erase Operation Status + Uint16 BUSY:1; // 8 Busy Bit + Uint16 rsvd4:1; // 9 Reserved + Uint16 EV:1; // 10 Erase Verify Status + Uint16 rsvd5:1; // 11 Reserved + Uint16 PGV:1; // 12 Programming Verify Status + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 rsvd9:1; // 16 Reserved + Uint16 rsvd10:1; // 17 Reserved + Uint16 rsvd11:14; // 31:18 Reserved +}; + +union FMSTAT_REG { + Uint32 all; + struct FMSTAT_BITS bit; +}; + +struct FRD_INTF_CTRL_BITS { // bits description + Uint16 PREFETCH_EN:1; // 0 Prefetch Enable + Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FRD_INTF_CTRL_REG { + Uint32 all; + struct FRD_INTF_CTRL_BITS bit; +}; + +struct FLASH_CTRL_REGS { + union FRDCNTL_REG FRDCNTL; // Flash Read Control Register + Uint16 rsvd1[28]; // Reserved + union FBAC_REG FBAC; // Flash Bank Access Control Register + union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register + union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register + union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 + Uint16 rsvd2[4]; // Reserved + union FMSTAT_REG FMSTAT; // Flash Module Status Register + Uint16 rsvd3[340]; // Reserved + union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register +}; + +struct ECC_ENABLE_BITS { // bits description + Uint16 ENABLE:4; // 3:0 Enable ECC + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ECC_ENABLE_REG { + Uint32 all; + struct ECC_ENABLE_BITS bit; +}; + +struct ERR_STATUS_BITS { // bits description + Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 + Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 + Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 + Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 + Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred + Uint16 rsvd2:13; // 31:19 Reserved +}; + +union ERR_STATUS_REG { + Uint32 all; + struct ERR_STATUS_BITS bit; +}; + +struct ERR_POS_BITS { // bits description + Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits + Uint16 rsvd2:7; // 15:9 Reserved + Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits + Uint16 rsvd4:7; // 31:25 Reserved +}; + +union ERR_POS_REG { + Uint32 all; + struct ERR_POS_BITS bit; +}; + +struct ERR_STATUS_CLR_BITS { // bits description + Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear + Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear + Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear + Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear + Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear + Uint16 rsvd2:13; // 31:19 Reserved +}; + +union ERR_STATUS_CLR_REG { + Uint32 all; + struct ERR_STATUS_CLR_BITS bit; +}; + +struct ERR_CNT_BITS { // bits description + Uint16 ERR_CNT:16; // 15:0 Error counter + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union ERR_CNT_REG { + Uint32 all; + struct ERR_CNT_BITS bit; +}; + +struct ERR_THRESHOLD_BITS { // bits description + Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union ERR_THRESHOLD_REG { + Uint32 all; + struct ERR_THRESHOLD_BITS bit; +}; + +struct ERR_INTFLG_BITS { // bits description + Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag + Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ERR_INTFLG_REG { + Uint32 all; + struct ERR_INTFLG_BITS bit; +}; + +struct ERR_INTCLR_BITS { // bits description + Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear + Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ERR_INTCLR_REG { + Uint32 all; + struct ERR_INTCLR_BITS bit; +}; + +struct FADDR_TEST_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ADDRL:13; // 15:3 ECC Address Low + Uint16 ADDRH:6; // 21:16 ECC Address High + Uint16 rsvd2:10; // 31:22 Reserved +}; + +union FADDR_TEST_REG { + Uint32 all; + struct FADDR_TEST_BITS bit; +}; + +struct FECC_TEST_BITS { // bits description + Uint16 ECC:8; // 7:0 ECC Control Bits + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_TEST_REG { + Uint32 all; + struct FECC_TEST_BITS bit; +}; + +struct FECC_CTRL_BITS { // bits description + Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic + Uint16 ECC_SELECT:1; // 1 ECC Bit Select + Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_CTRL_REG { + Uint32 all; + struct FECC_CTRL_BITS bit; +}; + +struct FECC_STATUS_BITS { // bits description + Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error + Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error + Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error + Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error + Uint16 rsvd1:7; // 15:9 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_STATUS_REG { + Uint32 all; + struct FECC_STATUS_BITS bit; +}; + +struct FLASH_ECC_REGS { + union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable + Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low + Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High + Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low + Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High + union ERR_STATUS_REG ERR_STATUS; // Error Status + union ERR_POS_REG ERR_POS; // Error Position + union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear + union ERR_CNT_REG ERR_CNT; // Error Control + union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold + union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag + union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear + Uint32 FDATAH_TEST; // Data High Test + Uint32 FDATAL_TEST; // Data Low Test + union FADDR_TEST_REG FADDR_TEST; // ECC Test Address + union FECC_TEST_REG FECC_TEST; // ECC Test Address + union FECC_CTRL_REG FECC_CTRL; // ECC Control + Uint32 FOUTH_TEST; // Test Data Out High + Uint32 FOUTL_TEST; // Test Data Out Low + union FECC_STATUS_REG FECC_STATUS; // ECC Status +}; + +struct PUMPREQUEST_BITS { // bits description + Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union PUMPREQUEST_REG { + Uint32 all; + struct PUMPREQUEST_BITS bit; +}; + +struct FLASH_PUMP_SEMAPHORE_REGS { + union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register +}; + +//--------------------------------------------------------------------------- +// FLASH External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; +extern volatile struct FLASH_ECC_REGS Flash0EccRegs; +#endif +#ifdef CPU2 +extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; +extern volatile struct FLASH_ECC_REGS Flash0EccRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h new file mode 100644 index 0000000000..7aeb219836 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h @@ -0,0 +1,3882 @@ +//########################################################################### +// +// FILE: F2837xD_gpio.h +// +// TITLE: GPIO Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_GPIO_H__ +#define __F2837xD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// GPIO Individual Register Bit Definitions: + +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +struct GPAQSEL1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 + Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 + Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 + Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 + Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 + Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 + Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 + Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 + Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 + Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 + Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 + Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 + Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 + Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 + Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 + Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 +}; + +union GPAQSEL1_REG { + Uint32 all; + struct GPAQSEL1_BITS bit; +}; + +struct GPAQSEL2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 + Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 + Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 + Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 + Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 + Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 + Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 + Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 + Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 + Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 + Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 + Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 + Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 + Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 + Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 + Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 +}; + +union GPAQSEL2_REG { + Uint32 all; + struct GPAQSEL2_BITS bit; +}; + +struct GPAMUX1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 + Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 + Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 + Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 + Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 + Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 + Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 + Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 + Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 + Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 + Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 + Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 + Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 + Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 + Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 + Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 +}; + +union GPAMUX1_REG { + Uint32 all; + struct GPAMUX1_BITS bit; +}; + +struct GPAMUX2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 + Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 + Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 + Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 + Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 + Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 + Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 + Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 + Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 + Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 + Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 + Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 + Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 + Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 + Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 + Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 +}; + +union GPAMUX2_REG { + Uint32 all; + struct GPAMUX2_BITS bit; +}; + +struct GPADIR_BITS { // bits description + Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPADIR_REG { + Uint32 all; + struct GPADIR_BITS bit; +}; + +struct GPAPUD_BITS { // bits description + Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin +}; + +union GPAPUD_REG { + Uint32 all; + struct GPAPUD_BITS bit; +}; + +struct GPAINV_BITS { // bits description + Uint16 GPIO0:1; // 0 Input inversion control for this pin + Uint16 GPIO1:1; // 1 Input inversion control for this pin + Uint16 GPIO2:1; // 2 Input inversion control for this pin + Uint16 GPIO3:1; // 3 Input inversion control for this pin + Uint16 GPIO4:1; // 4 Input inversion control for this pin + Uint16 GPIO5:1; // 5 Input inversion control for this pin + Uint16 GPIO6:1; // 6 Input inversion control for this pin + Uint16 GPIO7:1; // 7 Input inversion control for this pin + Uint16 GPIO8:1; // 8 Input inversion control for this pin + Uint16 GPIO9:1; // 9 Input inversion control for this pin + Uint16 GPIO10:1; // 10 Input inversion control for this pin + Uint16 GPIO11:1; // 11 Input inversion control for this pin + Uint16 GPIO12:1; // 12 Input inversion control for this pin + Uint16 GPIO13:1; // 13 Input inversion control for this pin + Uint16 GPIO14:1; // 14 Input inversion control for this pin + Uint16 GPIO15:1; // 15 Input inversion control for this pin + Uint16 GPIO16:1; // 16 Input inversion control for this pin + Uint16 GPIO17:1; // 17 Input inversion control for this pin + Uint16 GPIO18:1; // 18 Input inversion control for this pin + Uint16 GPIO19:1; // 19 Input inversion control for this pin + Uint16 GPIO20:1; // 20 Input inversion control for this pin + Uint16 GPIO21:1; // 21 Input inversion control for this pin + Uint16 GPIO22:1; // 22 Input inversion control for this pin + Uint16 GPIO23:1; // 23 Input inversion control for this pin + Uint16 GPIO24:1; // 24 Input inversion control for this pin + Uint16 GPIO25:1; // 25 Input inversion control for this pin + Uint16 GPIO26:1; // 26 Input inversion control for this pin + Uint16 GPIO27:1; // 27 Input inversion control for this pin + Uint16 GPIO28:1; // 28 Input inversion control for this pin + Uint16 GPIO29:1; // 29 Input inversion control for this pin + Uint16 GPIO30:1; // 30 Input inversion control for this pin + Uint16 GPIO31:1; // 31 Input inversion control for this pin +}; + +union GPAINV_REG { + Uint32 all; + struct GPAINV_BITS bit; +}; + +struct GPAODR_BITS { // bits description + Uint16 GPIO0:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO1:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO2:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO3:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO4:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO5:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO6:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO7:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO8:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO9:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO10:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO11:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO12:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO13:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO14:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO15:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO16:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO17:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO18:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO19:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO20:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO21:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO22:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO23:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO24:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO25:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO26:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO27:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO28:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO29:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO30:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO31:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPAODR_REG { + Uint32 all; + struct GPAODR_BITS bit; +}; + +struct GPAGMUX1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 + Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 + Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 + Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 + Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 + Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 + Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 + Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 + Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 + Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 + Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 + Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 + Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 + Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 + Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 + Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 +}; + +union GPAGMUX1_REG { + Uint32 all; + struct GPAGMUX1_BITS bit; +}; + +struct GPAGMUX2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 + Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 + Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 + Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 + Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 + Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 + Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 + Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 + Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 + Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 + Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 + Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 + Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 + Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 + Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 + Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 +}; + +union GPAGMUX2_REG { + Uint32 all; + struct GPAGMUX2_BITS bit; +}; + +struct GPACSEL1_BITS { // bits description + Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select + Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select + Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select + Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select + Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select + Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select + Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select + Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select +}; + +union GPACSEL1_REG { + Uint32 all; + struct GPACSEL1_BITS bit; +}; + +struct GPACSEL2_BITS { // bits description + Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select + Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select + Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select + Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select + Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select + Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select + Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select + Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select +}; + +union GPACSEL2_REG { + Uint32 all; + struct GPACSEL2_BITS bit; +}; + +struct GPACSEL3_BITS { // bits description + Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select + Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select + Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select + Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select + Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select + Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select + Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select + Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select +}; + +union GPACSEL3_REG { + Uint32 all; + struct GPACSEL3_BITS bit; +}; + +struct GPACSEL4_BITS { // bits description + Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select + Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select + Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select + Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select + Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select + Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select + Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select + Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select +}; + +union GPACSEL4_REG { + Uint32 all; + struct GPACSEL4_BITS bit; +}; + +struct GPALOCK_BITS { // bits description + Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin +}; + +union GPALOCK_REG { + Uint32 all; + struct GPALOCK_BITS bit; +}; + +struct GPACR_BITS { // bits description + Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin +}; + +union GPACR_REG { + Uint32 all; + struct GPACR_BITS bit; +}; + +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +struct GPBQSEL1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 + Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 + Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 + Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 + Uint16 GPIO36:2; // 9:8 Select input qualification type for GPIO36 + Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 + Uint16 GPIO38:2; // 13:12 Select input qualification type for GPIO38 + Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 + Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 + Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 + Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 + Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 + Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 + Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 + Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 + Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 +}; + +union GPBQSEL1_REG { + Uint32 all; + struct GPBQSEL1_BITS bit; +}; + +struct GPBQSEL2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 + Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 + Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 + Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 + Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 + Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 + Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 + Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 + Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 + Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 + Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 + Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 + Uint16 GPIO60:2; // 25:24 Select input qualification type for GPIO60 + Uint16 GPIO61:2; // 27:26 Select input qualification type for GPIO61 + Uint16 GPIO62:2; // 29:28 Select input qualification type for GPIO62 + Uint16 GPIO63:2; // 31:30 Select input qualification type for GPIO63 +}; + +union GPBQSEL2_REG { + Uint32 all; + struct GPBQSEL2_BITS bit; +}; + +struct GPBMUX1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 + Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 + Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 + Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 + Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 + Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 + Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 + Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 + Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 + Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 + Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 + Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 + Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 + Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 + Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 + Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 +}; + +union GPBMUX1_REG { + Uint32 all; + struct GPBMUX1_BITS bit; +}; + +struct GPBMUX2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 + Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 + Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 + Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 + Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 + Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 + Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 + Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 + Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 + Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 + Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 + Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 + Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 + Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 + Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 + Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 +}; + +union GPBMUX2_REG { + Uint32 all; + struct GPBMUX2_BITS bit; +}; + +struct GPBDIR_BITS { // bits description + Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO36:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO38:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO60:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO61:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO62:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO63:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPBDIR_REG { + Uint32 all; + struct GPBDIR_BITS bit; +}; + +struct GPBPUD_BITS { // bits description + Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO36:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO38:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO60:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO61:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO62:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO63:1; // 31 Pull-Up Disable control for this pin +}; + +union GPBPUD_REG { + Uint32 all; + struct GPBPUD_BITS bit; +}; + +struct GPBINV_BITS { // bits description + Uint16 GPIO32:1; // 0 Input inversion control for this pin + Uint16 GPIO33:1; // 1 Input inversion control for this pin + Uint16 GPIO34:1; // 2 Input inversion control for this pin + Uint16 GPIO35:1; // 3 Input inversion control for this pin + Uint16 GPIO36:1; // 4 Input inversion control for this pin + Uint16 GPIO37:1; // 5 Input inversion control for this pin + Uint16 GPIO38:1; // 6 Input inversion control for this pin + Uint16 GPIO39:1; // 7 Input inversion control for this pin + Uint16 GPIO40:1; // 8 Input inversion control for this pin + Uint16 GPIO41:1; // 9 Input inversion control for this pin + Uint16 GPIO42:1; // 10 Input inversion control for this pin + Uint16 GPIO43:1; // 11 Input inversion control for this pin + Uint16 GPIO44:1; // 12 Input inversion control for this pin + Uint16 GPIO45:1; // 13 Input inversion control for this pin + Uint16 GPIO46:1; // 14 Input inversion control for this pin + Uint16 GPIO47:1; // 15 Input inversion control for this pin + Uint16 GPIO48:1; // 16 Input inversion control for this pin + Uint16 GPIO49:1; // 17 Input inversion control for this pin + Uint16 GPIO50:1; // 18 Input inversion control for this pin + Uint16 GPIO51:1; // 19 Input inversion control for this pin + Uint16 GPIO52:1; // 20 Input inversion control for this pin + Uint16 GPIO53:1; // 21 Input inversion control for this pin + Uint16 GPIO54:1; // 22 Input inversion control for this pin + Uint16 GPIO55:1; // 23 Input inversion control for this pin + Uint16 GPIO56:1; // 24 Input inversion control for this pin + Uint16 GPIO57:1; // 25 Input inversion control for this pin + Uint16 GPIO58:1; // 26 Input inversion control for this pin + Uint16 GPIO59:1; // 27 Input inversion control for this pin + Uint16 GPIO60:1; // 28 Input inversion control for this pin + Uint16 GPIO61:1; // 29 Input inversion control for this pin + Uint16 GPIO62:1; // 30 Input inversion control for this pin + Uint16 GPIO63:1; // 31 Input inversion control for this pin +}; + +union GPBINV_REG { + Uint32 all; + struct GPBINV_BITS bit; +}; + +struct GPBODR_BITS { // bits description + Uint16 GPIO32:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO33:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO34:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO35:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO36:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO37:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO38:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO39:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO40:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO41:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO42:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO43:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO44:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO45:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO46:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO47:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO48:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO49:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO50:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO51:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO52:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO53:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO54:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO55:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO56:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO57:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO58:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO59:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO60:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO61:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO62:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO63:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPBODR_REG { + Uint32 all; + struct GPBODR_BITS bit; +}; + +struct GPBAMSEL_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:1; // 4 Reserved + Uint16 rsvd6:1; // 5 Reserved + Uint16 rsvd7:1; // 6 Reserved + Uint16 rsvd8:1; // 7 Reserved + Uint16 rsvd9:1; // 8 Reserved + Uint16 rsvd10:1; // 9 Reserved + Uint16 GPIO42:1; // 10 Analog Mode select for this pin + Uint16 GPIO43:1; // 11 Analog Mode select for this pin + Uint16 rsvd11:1; // 12 Reserved + Uint16 rsvd12:1; // 13 Reserved + Uint16 rsvd13:1; // 14 Reserved + Uint16 rsvd14:1; // 15 Reserved + Uint16 rsvd15:1; // 16 Reserved + Uint16 rsvd16:1; // 17 Reserved + Uint16 rsvd17:1; // 18 Reserved + Uint16 rsvd18:1; // 19 Reserved + Uint16 rsvd19:1; // 20 Reserved + Uint16 rsvd20:1; // 21 Reserved + Uint16 rsvd21:1; // 22 Reserved + Uint16 rsvd22:1; // 23 Reserved + Uint16 rsvd23:1; // 24 Reserved + Uint16 rsvd24:1; // 25 Reserved + Uint16 rsvd25:1; // 26 Reserved + Uint16 rsvd26:1; // 27 Reserved + Uint16 rsvd27:1; // 28 Reserved + Uint16 rsvd28:1; // 29 Reserved + Uint16 rsvd29:1; // 30 Reserved + Uint16 rsvd30:1; // 31 Reserved +}; + +union GPBAMSEL_REG { + Uint32 all; + struct GPBAMSEL_BITS bit; +}; + +struct GPBGMUX1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 + Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 + Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 + Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 + Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 + Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 + Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 + Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 + Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 + Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 + Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 + Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 + Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 + Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 + Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 + Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 +}; + +union GPBGMUX1_REG { + Uint32 all; + struct GPBGMUX1_BITS bit; +}; + +struct GPBGMUX2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 + Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 + Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 + Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 + Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 + Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 + Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 + Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 + Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 + Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 + Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 + Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 + Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 + Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 + Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 + Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 +}; + +union GPBGMUX2_REG { + Uint32 all; + struct GPBGMUX2_BITS bit; +}; + +struct GPBCSEL1_BITS { // bits description + Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select + Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select + Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select + Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select + Uint16 GPIO36:4; // 19:16 GPIO36 Master CPU Select + Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select + Uint16 GPIO38:4; // 27:24 GPIO38 Master CPU Select + Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select +}; + +union GPBCSEL1_REG { + Uint32 all; + struct GPBCSEL1_BITS bit; +}; + +struct GPBCSEL2_BITS { // bits description + Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select + Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select + Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select + Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select + Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select + Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select + Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select + Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select +}; + +union GPBCSEL2_REG { + Uint32 all; + struct GPBCSEL2_BITS bit; +}; + +struct GPBCSEL3_BITS { // bits description + Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select + Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select + Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select + Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select + Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select + Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select + Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select + Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select +}; + +union GPBCSEL3_REG { + Uint32 all; + struct GPBCSEL3_BITS bit; +}; + +struct GPBCSEL4_BITS { // bits description + Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select + Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select + Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select + Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select + Uint16 GPIO60:4; // 19:16 GPIO60 Master CPU Select + Uint16 GPIO61:4; // 23:20 GPIO61 Master CPU Select + Uint16 GPIO62:4; // 27:24 GPIO62 Master CPU Select + Uint16 GPIO63:4; // 31:28 GPIO63 Master CPU Select +}; + +union GPBCSEL4_REG { + Uint32 all; + struct GPBCSEL4_BITS bit; +}; + +struct GPBLOCK_BITS { // bits description + Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO36:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO38:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO60:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO61:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO62:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO63:1; // 31 Configuration Lock bit for this pin +}; + +union GPBLOCK_REG { + Uint32 all; + struct GPBLOCK_BITS bit; +}; + +struct GPBCR_BITS { // bits description + Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO36:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO38:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO60:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO61:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO62:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO63:1; // 31 Configuration lock commit bit for this pin +}; + +union GPBCR_REG { + Uint32 all; + struct GPBCR_BITS bit; +}; + +struct GPCCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO64 to GPIO71 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO72 to GPIO79 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO80 to GPIO87 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO88 to GPIO95 +}; + +union GPCCTRL_REG { + Uint32 all; + struct GPCCTRL_BITS bit; +}; + +struct GPCQSEL1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Select input qualification type for GPIO64 + Uint16 GPIO65:2; // 3:2 Select input qualification type for GPIO65 + Uint16 GPIO66:2; // 5:4 Select input qualification type for GPIO66 + Uint16 GPIO67:2; // 7:6 Select input qualification type for GPIO67 + Uint16 GPIO68:2; // 9:8 Select input qualification type for GPIO68 + Uint16 GPIO69:2; // 11:10 Select input qualification type for GPIO69 + Uint16 GPIO70:2; // 13:12 Select input qualification type for GPIO70 + Uint16 GPIO71:2; // 15:14 Select input qualification type for GPIO71 + Uint16 GPIO72:2; // 17:16 Select input qualification type for GPIO72 + Uint16 GPIO73:2; // 19:18 Select input qualification type for GPIO73 + Uint16 GPIO74:2; // 21:20 Select input qualification type for GPIO74 + Uint16 GPIO75:2; // 23:22 Select input qualification type for GPIO75 + Uint16 GPIO76:2; // 25:24 Select input qualification type for GPIO76 + Uint16 GPIO77:2; // 27:26 Select input qualification type for GPIO77 + Uint16 GPIO78:2; // 29:28 Select input qualification type for GPIO78 + Uint16 GPIO79:2; // 31:30 Select input qualification type for GPIO79 +}; + +union GPCQSEL1_REG { + Uint32 all; + struct GPCQSEL1_BITS bit; +}; + +struct GPCQSEL2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Select input qualification type for GPIO80 + Uint16 GPIO81:2; // 3:2 Select input qualification type for GPIO81 + Uint16 GPIO82:2; // 5:4 Select input qualification type for GPIO82 + Uint16 GPIO83:2; // 7:6 Select input qualification type for GPIO83 + Uint16 GPIO84:2; // 9:8 Select input qualification type for GPIO84 + Uint16 GPIO85:2; // 11:10 Select input qualification type for GPIO85 + Uint16 GPIO86:2; // 13:12 Select input qualification type for GPIO86 + Uint16 GPIO87:2; // 15:14 Select input qualification type for GPIO87 + Uint16 GPIO88:2; // 17:16 Select input qualification type for GPIO88 + Uint16 GPIO89:2; // 19:18 Select input qualification type for GPIO89 + Uint16 GPIO90:2; // 21:20 Select input qualification type for GPIO90 + Uint16 GPIO91:2; // 23:22 Select input qualification type for GPIO91 + Uint16 GPIO92:2; // 25:24 Select input qualification type for GPIO92 + Uint16 GPIO93:2; // 27:26 Select input qualification type for GPIO93 + Uint16 GPIO94:2; // 29:28 Select input qualification type for GPIO94 + Uint16 GPIO95:2; // 31:30 Select input qualification type for GPIO95 +}; + +union GPCQSEL2_REG { + Uint32 all; + struct GPCQSEL2_BITS bit; +}; + +struct GPCMUX1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 + Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 + Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 + Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 + Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 + Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 + Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 + Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 + Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 + Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 + Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 + Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 + Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 + Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 + Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 + Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 +}; + +union GPCMUX1_REG { + Uint32 all; + struct GPCMUX1_BITS bit; +}; + +struct GPCMUX2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 + Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 + Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 + Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 + Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 + Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 + Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 + Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 + Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 + Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 + Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 + Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 + Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 + Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 + Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 + Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 +}; + +union GPCMUX2_REG { + Uint32 all; + struct GPCMUX2_BITS bit; +}; + +struct GPCDIR_BITS { // bits description + Uint16 GPIO64:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO65:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO66:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO67:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO68:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO69:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO70:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO71:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO72:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO73:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO74:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO75:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO76:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO77:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO78:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO79:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO80:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO81:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO82:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO83:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO84:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO85:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO86:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO87:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO88:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO89:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO90:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO91:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO92:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO93:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO94:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO95:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPCDIR_REG { + Uint32 all; + struct GPCDIR_BITS bit; +}; + +struct GPCPUD_BITS { // bits description + Uint16 GPIO64:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO65:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO66:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO67:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO68:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO69:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO70:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO71:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO72:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO73:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO74:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO75:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO76:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO77:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO78:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO79:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO80:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO81:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO82:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO83:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO84:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO85:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO86:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO87:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO88:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO89:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO90:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO91:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO92:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO93:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO94:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO95:1; // 31 Pull-Up Disable control for this pin +}; + +union GPCPUD_REG { + Uint32 all; + struct GPCPUD_BITS bit; +}; + +struct GPCINV_BITS { // bits description + Uint16 GPIO64:1; // 0 Input inversion control for this pin + Uint16 GPIO65:1; // 1 Input inversion control for this pin + Uint16 GPIO66:1; // 2 Input inversion control for this pin + Uint16 GPIO67:1; // 3 Input inversion control for this pin + Uint16 GPIO68:1; // 4 Input inversion control for this pin + Uint16 GPIO69:1; // 5 Input inversion control for this pin + Uint16 GPIO70:1; // 6 Input inversion control for this pin + Uint16 GPIO71:1; // 7 Input inversion control for this pin + Uint16 GPIO72:1; // 8 Input inversion control for this pin + Uint16 GPIO73:1; // 9 Input inversion control for this pin + Uint16 GPIO74:1; // 10 Input inversion control for this pin + Uint16 GPIO75:1; // 11 Input inversion control for this pin + Uint16 GPIO76:1; // 12 Input inversion control for this pin + Uint16 GPIO77:1; // 13 Input inversion control for this pin + Uint16 GPIO78:1; // 14 Input inversion control for this pin + Uint16 GPIO79:1; // 15 Input inversion control for this pin + Uint16 GPIO80:1; // 16 Input inversion control for this pin + Uint16 GPIO81:1; // 17 Input inversion control for this pin + Uint16 GPIO82:1; // 18 Input inversion control for this pin + Uint16 GPIO83:1; // 19 Input inversion control for this pin + Uint16 GPIO84:1; // 20 Input inversion control for this pin + Uint16 GPIO85:1; // 21 Input inversion control for this pin + Uint16 GPIO86:1; // 22 Input inversion control for this pin + Uint16 GPIO87:1; // 23 Input inversion control for this pin + Uint16 GPIO88:1; // 24 Input inversion control for this pin + Uint16 GPIO89:1; // 25 Input inversion control for this pin + Uint16 GPIO90:1; // 26 Input inversion control for this pin + Uint16 GPIO91:1; // 27 Input inversion control for this pin + Uint16 GPIO92:1; // 28 Input inversion control for this pin + Uint16 GPIO93:1; // 29 Input inversion control for this pin + Uint16 GPIO94:1; // 30 Input inversion control for this pin + Uint16 GPIO95:1; // 31 Input inversion control for this pin +}; + +union GPCINV_REG { + Uint32 all; + struct GPCINV_BITS bit; +}; + +struct GPCODR_BITS { // bits description + Uint16 GPIO64:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO65:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO66:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO67:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO68:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO69:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO70:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO71:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO72:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO73:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO74:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO75:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO76:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO77:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO78:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO79:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO80:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO81:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO82:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO83:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO84:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO85:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO86:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO87:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO88:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO89:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO90:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO91:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO92:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO93:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO94:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO95:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPCODR_REG { + Uint32 all; + struct GPCODR_BITS bit; +}; + +struct GPCGMUX1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 + Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 + Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 + Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 + Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 + Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 + Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 + Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 + Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 + Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 + Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 + Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 + Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 + Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 + Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 + Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 +}; + +union GPCGMUX1_REG { + Uint32 all; + struct GPCGMUX1_BITS bit; +}; + +struct GPCGMUX2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 + Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 + Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 + Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 + Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 + Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 + Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 + Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 + Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 + Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 + Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 + Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 + Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 + Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 + Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 + Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 +}; + +union GPCGMUX2_REG { + Uint32 all; + struct GPCGMUX2_BITS bit; +}; + +struct GPCCSEL1_BITS { // bits description + Uint16 GPIO64:4; // 3:0 GPIO64 Master CPU Select + Uint16 GPIO65:4; // 7:4 GPIO65 Master CPU Select + Uint16 GPIO66:4; // 11:8 GPIO66 Master CPU Select + Uint16 GPIO67:4; // 15:12 GPIO67 Master CPU Select + Uint16 GPIO68:4; // 19:16 GPIO68 Master CPU Select + Uint16 GPIO69:4; // 23:20 GPIO69 Master CPU Select + Uint16 GPIO70:4; // 27:24 GPIO70 Master CPU Select + Uint16 GPIO71:4; // 31:28 GPIO71 Master CPU Select +}; + +union GPCCSEL1_REG { + Uint32 all; + struct GPCCSEL1_BITS bit; +}; + +struct GPCCSEL2_BITS { // bits description + Uint16 GPIO72:4; // 3:0 GPIO72 Master CPU Select + Uint16 GPIO73:4; // 7:4 GPIO73 Master CPU Select + Uint16 GPIO74:4; // 11:8 GPIO74 Master CPU Select + Uint16 GPIO75:4; // 15:12 GPIO75 Master CPU Select + Uint16 GPIO76:4; // 19:16 GPIO76 Master CPU Select + Uint16 GPIO77:4; // 23:20 GPIO77 Master CPU Select + Uint16 GPIO78:4; // 27:24 GPIO78 Master CPU Select + Uint16 GPIO79:4; // 31:28 GPIO79 Master CPU Select +}; + +union GPCCSEL2_REG { + Uint32 all; + struct GPCCSEL2_BITS bit; +}; + +struct GPCCSEL3_BITS { // bits description + Uint16 GPIO80:4; // 3:0 GPIO80 Master CPU Select + Uint16 GPIO81:4; // 7:4 GPIO81 Master CPU Select + Uint16 GPIO82:4; // 11:8 GPIO82 Master CPU Select + Uint16 GPIO83:4; // 15:12 GPIO83 Master CPU Select + Uint16 GPIO84:4; // 19:16 GPIO84 Master CPU Select + Uint16 GPIO85:4; // 23:20 GPIO85 Master CPU Select + Uint16 GPIO86:4; // 27:24 GPIO86 Master CPU Select + Uint16 GPIO87:4; // 31:28 GPIO87 Master CPU Select +}; + +union GPCCSEL3_REG { + Uint32 all; + struct GPCCSEL3_BITS bit; +}; + +struct GPCCSEL4_BITS { // bits description + Uint16 GPIO88:4; // 3:0 GPIO88 Master CPU Select + Uint16 GPIO89:4; // 7:4 GPIO89 Master CPU Select + Uint16 GPIO90:4; // 11:8 GPIO90 Master CPU Select + Uint16 GPIO91:4; // 15:12 GPIO91 Master CPU Select + Uint16 GPIO92:4; // 19:16 GPIO92 Master CPU Select + Uint16 GPIO93:4; // 23:20 GPIO93 Master CPU Select + Uint16 GPIO94:4; // 27:24 GPIO94 Master CPU Select + Uint16 GPIO95:4; // 31:28 GPIO95 Master CPU Select +}; + +union GPCCSEL4_REG { + Uint32 all; + struct GPCCSEL4_BITS bit; +}; + +struct GPCLOCK_BITS { // bits description + Uint16 GPIO64:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO65:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO66:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO67:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO68:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO69:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO70:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO71:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO72:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO73:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO74:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO75:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO76:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO77:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO78:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO79:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO80:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO81:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO82:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO83:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO84:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO85:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO86:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO87:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO88:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO89:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO90:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO91:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO92:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO93:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO94:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO95:1; // 31 Configuration Lock bit for this pin +}; + +union GPCLOCK_REG { + Uint32 all; + struct GPCLOCK_BITS bit; +}; + +struct GPCCR_BITS { // bits description + Uint16 GPIO64:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO65:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO66:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO67:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO68:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO69:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO70:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO71:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO72:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO73:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO74:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO75:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO76:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO77:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO78:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO79:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO80:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO81:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO82:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO83:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO84:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO85:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO86:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO87:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO88:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO89:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO90:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO91:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO92:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO93:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO94:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO95:1; // 31 Configuration lock commit bit for this pin +}; + +union GPCCR_REG { + Uint32 all; + struct GPCCR_BITS bit; +}; + +struct GPDCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO96 to GPIO103 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO104 to GPIO111 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO112 to GPIO119 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO120 to GPIO127 +}; + +union GPDCTRL_REG { + Uint32 all; + struct GPDCTRL_BITS bit; +}; + +struct GPDQSEL1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Select input qualification type for GPIO96 + Uint16 GPIO97:2; // 3:2 Select input qualification type for GPIO97 + Uint16 GPIO98:2; // 5:4 Select input qualification type for GPIO98 + Uint16 GPIO99:2; // 7:6 Select input qualification type for GPIO99 + Uint16 GPIO100:2; // 9:8 Select input qualification type for GPIO100 + Uint16 GPIO101:2; // 11:10 Select input qualification type for GPIO101 + Uint16 GPIO102:2; // 13:12 Select input qualification type for GPIO102 + Uint16 GPIO103:2; // 15:14 Select input qualification type for GPIO103 + Uint16 GPIO104:2; // 17:16 Select input qualification type for GPIO104 + Uint16 GPIO105:2; // 19:18 Select input qualification type for GPIO105 + Uint16 GPIO106:2; // 21:20 Select input qualification type for GPIO106 + Uint16 GPIO107:2; // 23:22 Select input qualification type for GPIO107 + Uint16 GPIO108:2; // 25:24 Select input qualification type for GPIO108 + Uint16 GPIO109:2; // 27:26 Select input qualification type for GPIO109 + Uint16 GPIO110:2; // 29:28 Select input qualification type for GPIO110 + Uint16 GPIO111:2; // 31:30 Select input qualification type for GPIO111 +}; + +union GPDQSEL1_REG { + Uint32 all; + struct GPDQSEL1_BITS bit; +}; + +struct GPDQSEL2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Select input qualification type for GPIO112 + Uint16 GPIO113:2; // 3:2 Select input qualification type for GPIO113 + Uint16 GPIO114:2; // 5:4 Select input qualification type for GPIO114 + Uint16 GPIO115:2; // 7:6 Select input qualification type for GPIO115 + Uint16 GPIO116:2; // 9:8 Select input qualification type for GPIO116 + Uint16 GPIO117:2; // 11:10 Select input qualification type for GPIO117 + Uint16 GPIO118:2; // 13:12 Select input qualification type for GPIO118 + Uint16 GPIO119:2; // 15:14 Select input qualification type for GPIO119 + Uint16 GPIO120:2; // 17:16 Select input qualification type for GPIO120 + Uint16 GPIO121:2; // 19:18 Select input qualification type for GPIO121 + Uint16 GPIO122:2; // 21:20 Select input qualification type for GPIO122 + Uint16 GPIO123:2; // 23:22 Select input qualification type for GPIO123 + Uint16 GPIO124:2; // 25:24 Select input qualification type for GPIO124 + Uint16 GPIO125:2; // 27:26 Select input qualification type for GPIO125 + Uint16 GPIO126:2; // 29:28 Select input qualification type for GPIO126 + Uint16 GPIO127:2; // 31:30 Select input qualification type for GPIO127 +}; + +union GPDQSEL2_REG { + Uint32 all; + struct GPDQSEL2_BITS bit; +}; + +struct GPDMUX1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 + Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 + Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 + Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 + Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 + Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 + Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 + Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 + Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 + Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 + Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 + Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 + Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 + Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 + Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 + Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 +}; + +union GPDMUX1_REG { + Uint32 all; + struct GPDMUX1_BITS bit; +}; + +struct GPDMUX2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 + Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 + Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 + Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 + Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 + Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 + Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 + Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 + Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 + Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 + Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 + Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 + Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 + Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 + Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 + Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 +}; + +union GPDMUX2_REG { + Uint32 all; + struct GPDMUX2_BITS bit; +}; + +struct GPDDIR_BITS { // bits description + Uint16 GPIO96:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO97:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO98:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO99:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO100:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO101:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO102:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO103:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO104:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO105:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO106:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO107:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO108:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO109:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO110:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO111:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO112:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO113:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO114:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO115:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO116:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO117:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO118:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO119:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO120:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO121:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO122:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO123:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO124:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO125:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO126:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO127:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPDDIR_REG { + Uint32 all; + struct GPDDIR_BITS bit; +}; + +struct GPDPUD_BITS { // bits description + Uint16 GPIO96:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO97:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO98:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO99:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO100:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO101:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO102:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO103:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO104:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO105:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO106:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO107:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO108:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO109:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO110:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO111:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO112:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO113:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO114:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO115:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO116:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO117:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO118:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO119:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO120:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO121:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO122:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO123:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO124:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO125:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO126:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO127:1; // 31 Pull-Up Disable control for this pin +}; + +union GPDPUD_REG { + Uint32 all; + struct GPDPUD_BITS bit; +}; + +struct GPDINV_BITS { // bits description + Uint16 GPIO96:1; // 0 Input inversion control for this pin + Uint16 GPIO97:1; // 1 Input inversion control for this pin + Uint16 GPIO98:1; // 2 Input inversion control for this pin + Uint16 GPIO99:1; // 3 Input inversion control for this pin + Uint16 GPIO100:1; // 4 Input inversion control for this pin + Uint16 GPIO101:1; // 5 Input inversion control for this pin + Uint16 GPIO102:1; // 6 Input inversion control for this pin + Uint16 GPIO103:1; // 7 Input inversion control for this pin + Uint16 GPIO104:1; // 8 Input inversion control for this pin + Uint16 GPIO105:1; // 9 Input inversion control for this pin + Uint16 GPIO106:1; // 10 Input inversion control for this pin + Uint16 GPIO107:1; // 11 Input inversion control for this pin + Uint16 GPIO108:1; // 12 Input inversion control for this pin + Uint16 GPIO109:1; // 13 Input inversion control for this pin + Uint16 GPIO110:1; // 14 Input inversion control for this pin + Uint16 GPIO111:1; // 15 Input inversion control for this pin + Uint16 GPIO112:1; // 16 Input inversion control for this pin + Uint16 GPIO113:1; // 17 Input inversion control for this pin + Uint16 GPIO114:1; // 18 Input inversion control for this pin + Uint16 GPIO115:1; // 19 Input inversion control for this pin + Uint16 GPIO116:1; // 20 Input inversion control for this pin + Uint16 GPIO117:1; // 21 Input inversion control for this pin + Uint16 GPIO118:1; // 22 Input inversion control for this pin + Uint16 GPIO119:1; // 23 Input inversion control for this pin + Uint16 GPIO120:1; // 24 Input inversion control for this pin + Uint16 GPIO121:1; // 25 Input inversion control for this pin + Uint16 GPIO122:1; // 26 Input inversion control for this pin + Uint16 GPIO123:1; // 27 Input inversion control for this pin + Uint16 GPIO124:1; // 28 Input inversion control for this pin + Uint16 GPIO125:1; // 29 Input inversion control for this pin + Uint16 GPIO126:1; // 30 Input inversion control for this pin + Uint16 GPIO127:1; // 31 Input inversion control for this pin +}; + +union GPDINV_REG { + Uint32 all; + struct GPDINV_BITS bit; +}; + +struct GPDODR_BITS { // bits description + Uint16 GPIO96:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO97:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO98:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO99:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO100:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO101:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO102:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO103:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO104:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO105:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO106:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO107:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO108:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO109:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO110:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO111:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO112:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO113:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO114:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO115:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO116:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO117:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO118:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO119:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO120:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO121:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO122:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO123:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO124:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO125:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO126:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO127:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPDODR_REG { + Uint32 all; + struct GPDODR_BITS bit; +}; + +struct GPDGMUX1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 + Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 + Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 + Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 + Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 + Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 + Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 + Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 + Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 + Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 + Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 + Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 + Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 + Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 + Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 + Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 +}; + +union GPDGMUX1_REG { + Uint32 all; + struct GPDGMUX1_BITS bit; +}; + +struct GPDGMUX2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 + Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 + Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 + Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 + Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 + Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 + Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 + Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 + Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 + Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 + Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 + Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 + Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 + Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 + Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 + Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 +}; + +union GPDGMUX2_REG { + Uint32 all; + struct GPDGMUX2_BITS bit; +}; + +struct GPDCSEL1_BITS { // bits description + Uint16 GPIO96:4; // 3:0 GPIO96 Master CPU Select + Uint16 GPIO97:4; // 7:4 GPIO97 Master CPU Select + Uint16 GPIO98:4; // 11:8 GPIO98 Master CPU Select + Uint16 GPIO99:4; // 15:12 GPIO99 Master CPU Select + Uint16 GPIO100:4; // 19:16 GPIO100 Master CPU Select + Uint16 GPIO101:4; // 23:20 GPIO101 Master CPU Select + Uint16 GPIO102:4; // 27:24 GPIO102 Master CPU Select + Uint16 GPIO103:4; // 31:28 GPIO103 Master CPU Select +}; + +union GPDCSEL1_REG { + Uint32 all; + struct GPDCSEL1_BITS bit; +}; + +struct GPDCSEL2_BITS { // bits description + Uint16 GPIO104:4; // 3:0 GPIO104 Master CPU Select + Uint16 GPIO105:4; // 7:4 GPIO105 Master CPU Select + Uint16 GPIO106:4; // 11:8 GPIO106 Master CPU Select + Uint16 GPIO107:4; // 15:12 GPIO107 Master CPU Select + Uint16 GPIO108:4; // 19:16 GPIO108 Master CPU Select + Uint16 GPIO109:4; // 23:20 GPIO109 Master CPU Select + Uint16 GPIO110:4; // 27:24 GPIO110 Master CPU Select + Uint16 GPIO111:4; // 31:28 GPIO111 Master CPU Select +}; + +union GPDCSEL2_REG { + Uint32 all; + struct GPDCSEL2_BITS bit; +}; + +struct GPDCSEL3_BITS { // bits description + Uint16 GPIO112:4; // 3:0 GPIO112 Master CPU Select + Uint16 GPIO113:4; // 7:4 GPIO113 Master CPU Select + Uint16 GPIO114:4; // 11:8 GPIO114 Master CPU Select + Uint16 GPIO115:4; // 15:12 GPIO115 Master CPU Select + Uint16 GPIO116:4; // 19:16 GPIO116 Master CPU Select + Uint16 GPIO117:4; // 23:20 GPIO117 Master CPU Select + Uint16 GPIO118:4; // 27:24 GPIO118 Master CPU Select + Uint16 GPIO119:4; // 31:28 GPIO119 Master CPU Select +}; + +union GPDCSEL3_REG { + Uint32 all; + struct GPDCSEL3_BITS bit; +}; + +struct GPDCSEL4_BITS { // bits description + Uint16 GPIO120:4; // 3:0 GPIO120 Master CPU Select + Uint16 GPIO121:4; // 7:4 GPIO121 Master CPU Select + Uint16 GPIO122:4; // 11:8 GPIO122 Master CPU Select + Uint16 GPIO123:4; // 15:12 GPIO123 Master CPU Select + Uint16 GPIO124:4; // 19:16 GPIO124 Master CPU Select + Uint16 GPIO125:4; // 23:20 GPIO125 Master CPU Select + Uint16 GPIO126:4; // 27:24 GPIO126 Master CPU Select + Uint16 GPIO127:4; // 31:28 GPIO127 Master CPU Select +}; + +union GPDCSEL4_REG { + Uint32 all; + struct GPDCSEL4_BITS bit; +}; + +struct GPDLOCK_BITS { // bits description + Uint16 GPIO96:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO97:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO98:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO99:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO100:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO101:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO102:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO103:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO104:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO105:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO106:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO107:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO108:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO109:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO110:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO111:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO112:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO113:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO114:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO115:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO116:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO117:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO118:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO119:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO120:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO121:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO122:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO123:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO124:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO125:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO126:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO127:1; // 31 Configuration Lock bit for this pin +}; + +union GPDLOCK_REG { + Uint32 all; + struct GPDLOCK_BITS bit; +}; + +struct GPDCR_BITS { // bits description + Uint16 GPIO96:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO97:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO98:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO99:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO100:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO101:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO102:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO103:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO104:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO105:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO106:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO107:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO108:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO109:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO110:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO111:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO112:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO113:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO114:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO115:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO116:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO117:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO118:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO119:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO120:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO121:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO122:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO123:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO124:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO125:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO126:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO127:1; // 31 Configuration lock commit bit for this pin +}; + +union GPDCR_REG { + Uint32 all; + struct GPDCR_BITS bit; +}; + +struct GPECTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO128 to GPIO135 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO136 to GPIO143 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO144 to GPIO151 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO152 to GPIO159 +}; + +union GPECTRL_REG { + Uint32 all; + struct GPECTRL_BITS bit; +}; + +struct GPEQSEL1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Select input qualification type for GPIO128 + Uint16 GPIO129:2; // 3:2 Select input qualification type for GPIO129 + Uint16 GPIO130:2; // 5:4 Select input qualification type for GPIO130 + Uint16 GPIO131:2; // 7:6 Select input qualification type for GPIO131 + Uint16 GPIO132:2; // 9:8 Select input qualification type for GPIO132 + Uint16 GPIO133:2; // 11:10 Select input qualification type for GPIO133 + Uint16 GPIO134:2; // 13:12 Select input qualification type for GPIO134 + Uint16 GPIO135:2; // 15:14 Select input qualification type for GPIO135 + Uint16 GPIO136:2; // 17:16 Select input qualification type for GPIO136 + Uint16 GPIO137:2; // 19:18 Select input qualification type for GPIO137 + Uint16 GPIO138:2; // 21:20 Select input qualification type for GPIO138 + Uint16 GPIO139:2; // 23:22 Select input qualification type for GPIO139 + Uint16 GPIO140:2; // 25:24 Select input qualification type for GPIO140 + Uint16 GPIO141:2; // 27:26 Select input qualification type for GPIO141 + Uint16 GPIO142:2; // 29:28 Select input qualification type for GPIO142 + Uint16 GPIO143:2; // 31:30 Select input qualification type for GPIO143 +}; + +union GPEQSEL1_REG { + Uint32 all; + struct GPEQSEL1_BITS bit; +}; + +struct GPEQSEL2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Select input qualification type for GPIO144 + Uint16 GPIO145:2; // 3:2 Select input qualification type for GPIO145 + Uint16 GPIO146:2; // 5:4 Select input qualification type for GPIO146 + Uint16 GPIO147:2; // 7:6 Select input qualification type for GPIO147 + Uint16 GPIO148:2; // 9:8 Select input qualification type for GPIO148 + Uint16 GPIO149:2; // 11:10 Select input qualification type for GPIO149 + Uint16 GPIO150:2; // 13:12 Select input qualification type for GPIO150 + Uint16 GPIO151:2; // 15:14 Select input qualification type for GPIO151 + Uint16 GPIO152:2; // 17:16 Select input qualification type for GPIO152 + Uint16 GPIO153:2; // 19:18 Select input qualification type for GPIO153 + Uint16 GPIO154:2; // 21:20 Select input qualification type for GPIO154 + Uint16 GPIO155:2; // 23:22 Select input qualification type for GPIO155 + Uint16 GPIO156:2; // 25:24 Select input qualification type for GPIO156 + Uint16 GPIO157:2; // 27:26 Select input qualification type for GPIO157 + Uint16 GPIO158:2; // 29:28 Select input qualification type for GPIO158 + Uint16 GPIO159:2; // 31:30 Select input qualification type for GPIO159 +}; + +union GPEQSEL2_REG { + Uint32 all; + struct GPEQSEL2_BITS bit; +}; + +struct GPEMUX1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 + Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 + Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 + Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 + Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 + Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 + Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 + Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 + Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 + Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 + Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 + Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 + Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 + Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 + Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 + Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 +}; + +union GPEMUX1_REG { + Uint32 all; + struct GPEMUX1_BITS bit; +}; + +struct GPEMUX2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 + Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 + Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 + Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 + Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 + Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 + Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 + Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 + Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 + Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 + Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 + Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 + Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 + Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 + Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 + Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 +}; + +union GPEMUX2_REG { + Uint32 all; + struct GPEMUX2_BITS bit; +}; + +struct GPEDIR_BITS { // bits description + Uint16 GPIO128:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO129:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO130:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO131:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO132:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO133:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO134:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO135:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO136:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO137:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO138:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO139:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO140:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO141:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO142:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO143:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO144:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO145:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO146:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO147:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO148:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO149:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO150:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO151:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO152:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO153:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO154:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO155:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO156:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO157:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO158:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO159:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPEDIR_REG { + Uint32 all; + struct GPEDIR_BITS bit; +}; + +struct GPEPUD_BITS { // bits description + Uint16 GPIO128:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO129:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO130:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO131:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO132:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO133:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO134:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO135:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO136:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO137:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO138:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO139:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO140:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO141:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO142:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO143:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO144:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO145:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO146:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO147:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO148:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO149:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO150:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO151:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO152:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO153:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO154:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO155:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO156:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO157:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO158:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO159:1; // 31 Pull-Up Disable control for this pin +}; + +union GPEPUD_REG { + Uint32 all; + struct GPEPUD_BITS bit; +}; + +struct GPEINV_BITS { // bits description + Uint16 GPIO128:1; // 0 Input inversion control for this pin + Uint16 GPIO129:1; // 1 Input inversion control for this pin + Uint16 GPIO130:1; // 2 Input inversion control for this pin + Uint16 GPIO131:1; // 3 Input inversion control for this pin + Uint16 GPIO132:1; // 4 Input inversion control for this pin + Uint16 GPIO133:1; // 5 Input inversion control for this pin + Uint16 GPIO134:1; // 6 Input inversion control for this pin + Uint16 GPIO135:1; // 7 Input inversion control for this pin + Uint16 GPIO136:1; // 8 Input inversion control for this pin + Uint16 GPIO137:1; // 9 Input inversion control for this pin + Uint16 GPIO138:1; // 10 Input inversion control for this pin + Uint16 GPIO139:1; // 11 Input inversion control for this pin + Uint16 GPIO140:1; // 12 Input inversion control for this pin + Uint16 GPIO141:1; // 13 Input inversion control for this pin + Uint16 GPIO142:1; // 14 Input inversion control for this pin + Uint16 GPIO143:1; // 15 Input inversion control for this pin + Uint16 GPIO144:1; // 16 Input inversion control for this pin + Uint16 GPIO145:1; // 17 Input inversion control for this pin + Uint16 GPIO146:1; // 18 Input inversion control for this pin + Uint16 GPIO147:1; // 19 Input inversion control for this pin + Uint16 GPIO148:1; // 20 Input inversion control for this pin + Uint16 GPIO149:1; // 21 Input inversion control for this pin + Uint16 GPIO150:1; // 22 Input inversion control for this pin + Uint16 GPIO151:1; // 23 Input inversion control for this pin + Uint16 GPIO152:1; // 24 Input inversion control for this pin + Uint16 GPIO153:1; // 25 Input inversion control for this pin + Uint16 GPIO154:1; // 26 Input inversion control for this pin + Uint16 GPIO155:1; // 27 Input inversion control for this pin + Uint16 GPIO156:1; // 28 Input inversion control for this pin + Uint16 GPIO157:1; // 29 Input inversion control for this pin + Uint16 GPIO158:1; // 30 Input inversion control for this pin + Uint16 GPIO159:1; // 31 Input inversion control for this pin +}; + +union GPEINV_REG { + Uint32 all; + struct GPEINV_BITS bit; +}; + +struct GPEODR_BITS { // bits description + Uint16 GPIO128:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO129:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO130:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO131:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO132:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO133:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO134:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO135:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO136:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO137:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO138:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO139:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO140:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO141:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO142:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO143:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO144:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO145:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO146:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO147:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO148:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO149:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO150:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO151:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO152:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO153:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO154:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO155:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO156:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO157:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO158:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO159:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPEODR_REG { + Uint32 all; + struct GPEODR_BITS bit; +}; + +struct GPEGMUX1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 + Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 + Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 + Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 + Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 + Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 + Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 + Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 + Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 + Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 + Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 + Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 + Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 + Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 + Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 + Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 +}; + +union GPEGMUX1_REG { + Uint32 all; + struct GPEGMUX1_BITS bit; +}; + +struct GPEGMUX2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 + Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 + Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 + Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 + Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 + Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 + Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 + Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 + Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 + Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 + Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 + Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 + Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 + Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 + Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 + Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 +}; + +union GPEGMUX2_REG { + Uint32 all; + struct GPEGMUX2_BITS bit; +}; + +struct GPECSEL1_BITS { // bits description + Uint16 GPIO128:4; // 3:0 GPIO128 Master CPU Select + Uint16 GPIO129:4; // 7:4 GPIO129 Master CPU Select + Uint16 GPIO130:4; // 11:8 GPIO130 Master CPU Select + Uint16 GPIO131:4; // 15:12 GPIO131 Master CPU Select + Uint16 GPIO132:4; // 19:16 GPIO132 Master CPU Select + Uint16 GPIO133:4; // 23:20 GPIO133 Master CPU Select + Uint16 GPIO134:4; // 27:24 GPIO134 Master CPU Select + Uint16 GPIO135:4; // 31:28 GPIO135 Master CPU Select +}; + +union GPECSEL1_REG { + Uint32 all; + struct GPECSEL1_BITS bit; +}; + +struct GPECSEL2_BITS { // bits description + Uint16 GPIO136:4; // 3:0 GPIO136 Master CPU Select + Uint16 GPIO137:4; // 7:4 GPIO137 Master CPU Select + Uint16 GPIO138:4; // 11:8 GPIO138 Master CPU Select + Uint16 GPIO139:4; // 15:12 GPIO139 Master CPU Select + Uint16 GPIO140:4; // 19:16 GPIO140 Master CPU Select + Uint16 GPIO141:4; // 23:20 GPIO141 Master CPU Select + Uint16 GPIO142:4; // 27:24 GPIO142 Master CPU Select + Uint16 GPIO143:4; // 31:28 GPIO143 Master CPU Select +}; + +union GPECSEL2_REG { + Uint32 all; + struct GPECSEL2_BITS bit; +}; + +struct GPECSEL3_BITS { // bits description + Uint16 GPIO144:4; // 3:0 GPIO144 Master CPU Select + Uint16 GPIO145:4; // 7:4 GPIO145 Master CPU Select + Uint16 GPIO146:4; // 11:8 GPIO146 Master CPU Select + Uint16 GPIO147:4; // 15:12 GPIO147 Master CPU Select + Uint16 GPIO148:4; // 19:16 GPIO148 Master CPU Select + Uint16 GPIO149:4; // 23:20 GPIO149 Master CPU Select + Uint16 GPIO150:4; // 27:24 GPIO150 Master CPU Select + Uint16 GPIO151:4; // 31:28 GPIO151 Master CPU Select +}; + +union GPECSEL3_REG { + Uint32 all; + struct GPECSEL3_BITS bit; +}; + +struct GPECSEL4_BITS { // bits description + Uint16 GPIO152:4; // 3:0 GPIO152 Master CPU Select + Uint16 GPIO153:4; // 7:4 GPIO153 Master CPU Select + Uint16 GPIO154:4; // 11:8 GPIO154 Master CPU Select + Uint16 GPIO155:4; // 15:12 GPIO155 Master CPU Select + Uint16 GPIO156:4; // 19:16 GPIO156 Master CPU Select + Uint16 GPIO157:4; // 23:20 GPIO157 Master CPU Select + Uint16 GPIO158:4; // 27:24 GPIO158 Master CPU Select + Uint16 GPIO159:4; // 31:28 GPIO159 Master CPU Select +}; + +union GPECSEL4_REG { + Uint32 all; + struct GPECSEL4_BITS bit; +}; + +struct GPELOCK_BITS { // bits description + Uint16 GPIO128:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO129:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO130:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO131:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO132:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO133:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO134:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO135:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO136:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO137:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO138:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO139:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO140:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO141:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO142:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO143:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO144:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO145:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO146:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO147:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO148:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO149:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO150:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO151:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO152:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO153:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO154:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO155:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO156:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO157:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO158:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO159:1; // 31 Configuration Lock bit for this pin +}; + +union GPELOCK_REG { + Uint32 all; + struct GPELOCK_BITS bit; +}; + +struct GPECR_BITS { // bits description + Uint16 GPIO128:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO129:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO130:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO131:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO132:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO133:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO134:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO135:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO136:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO137:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO138:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO139:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO140:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO141:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO142:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO143:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO144:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO145:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO146:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO147:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO148:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO149:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO150:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO151:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO152:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO153:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO154:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO155:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO156:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO157:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO158:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO159:1; // 31 Configuration lock commit bit for this pin +}; + +union GPECR_REG { + Uint32 all; + struct GPECR_BITS bit; +}; + +struct GPFCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO160 to GPIO167 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO168 + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union GPFCTRL_REG { + Uint32 all; + struct GPFCTRL_BITS bit; +}; + +struct GPFQSEL1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Select input qualification type for GPIO160 + Uint16 GPIO161:2; // 3:2 Select input qualification type for GPIO161 + Uint16 GPIO162:2; // 5:4 Select input qualification type for GPIO162 + Uint16 GPIO163:2; // 7:6 Select input qualification type for GPIO163 + Uint16 GPIO164:2; // 9:8 Select input qualification type for GPIO164 + Uint16 GPIO165:2; // 11:10 Select input qualification type for GPIO165 + Uint16 GPIO166:2; // 13:12 Select input qualification type for GPIO166 + Uint16 GPIO167:2; // 15:14 Select input qualification type for GPIO167 + Uint16 GPIO168:2; // 17:16 Select input qualification type for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFQSEL1_REG { + Uint32 all; + struct GPFQSEL1_BITS bit; +}; + +struct GPFMUX1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 + Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 + Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 + Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 + Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 + Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 + Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 + Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 + Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFMUX1_REG { + Uint32 all; + struct GPFMUX1_BITS bit; +}; + +struct GPFDIR_BITS { // bits description + Uint16 GPIO160:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO161:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO162:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO163:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO164:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO165:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO166:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO167:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO168:1; // 8 Defines direction for this pin in GPIO mode + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFDIR_REG { + Uint32 all; + struct GPFDIR_BITS bit; +}; + +struct GPFPUD_BITS { // bits description + Uint16 GPIO160:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO161:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO162:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO163:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO164:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO165:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO166:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO167:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO168:1; // 8 Pull-Up Disable control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFPUD_REG { + Uint32 all; + struct GPFPUD_BITS bit; +}; + +struct GPFINV_BITS { // bits description + Uint16 GPIO160:1; // 0 Input inversion control for this pin + Uint16 GPIO161:1; // 1 Input inversion control for this pin + Uint16 GPIO162:1; // 2 Input inversion control for this pin + Uint16 GPIO163:1; // 3 Input inversion control for this pin + Uint16 GPIO164:1; // 4 Input inversion control for this pin + Uint16 GPIO165:1; // 5 Input inversion control for this pin + Uint16 GPIO166:1; // 6 Input inversion control for this pin + Uint16 GPIO167:1; // 7 Input inversion control for this pin + Uint16 GPIO168:1; // 8 Input inversion control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFINV_REG { + Uint32 all; + struct GPFINV_BITS bit; +}; + +struct GPFODR_BITS { // bits description + Uint16 GPIO160:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO161:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO162:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO163:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO164:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO165:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO166:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO167:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO168:1; // 8 Outpout Open-Drain control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFODR_REG { + Uint32 all; + struct GPFODR_BITS bit; +}; + +struct GPFGMUX1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 + Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 + Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 + Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 + Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 + Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 + Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 + Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 + Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFGMUX1_REG { + Uint32 all; + struct GPFGMUX1_BITS bit; +}; + +struct GPFCSEL1_BITS { // bits description + Uint16 GPIO160:4; // 3:0 GPIO160 Master CPU Select + Uint16 GPIO161:4; // 7:4 GPIO161 Master CPU Select + Uint16 GPIO162:4; // 11:8 GPIO162 Master CPU Select + Uint16 GPIO163:4; // 15:12 GPIO163 Master CPU Select + Uint16 GPIO164:4; // 19:16 GPIO164 Master CPU Select + Uint16 GPIO165:4; // 23:20 GPIO165 Master CPU Select + Uint16 GPIO166:4; // 27:24 GPIO166 Master CPU Select + Uint16 GPIO167:4; // 31:28 GPIO167 Master CPU Select +}; + +union GPFCSEL1_REG { + Uint32 all; + struct GPFCSEL1_BITS bit; +}; + +struct GPFCSEL2_BITS { // bits description + Uint16 GPIO168:4; // 3:0 GPIO168 Master CPU Select + Uint16 rsvd1:4; // 7:4 Reserved + Uint16 rsvd2:4; // 11:8 Reserved + Uint16 rsvd3:4; // 15:12 Reserved + Uint16 rsvd4:4; // 19:16 Reserved + Uint16 rsvd5:4; // 23:20 Reserved + Uint16 rsvd6:4; // 27:24 Reserved + Uint16 rsvd7:4; // 31:28 Reserved +}; + +union GPFCSEL2_REG { + Uint32 all; + struct GPFCSEL2_BITS bit; +}; + +struct GPFLOCK_BITS { // bits description + Uint16 GPIO160:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO161:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO162:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO163:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO164:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO165:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO166:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO167:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO168:1; // 8 Configuration Lock bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFLOCK_REG { + Uint32 all; + struct GPFLOCK_BITS bit; +}; + +struct GPFCR_BITS { // bits description + Uint16 GPIO160:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO161:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO162:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO163:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO164:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO165:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO166:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO167:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO168:1; // 8 Configuration lock commit bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFCR_REG { + Uint32 all; + struct GPFCR_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period Control (GPIO0 to 31) + union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + union GPAMUX1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) + union GPAMUX2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) + union GPADIR_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + union GPAPUD_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) + Uint16 rsvd1[2]; // Reserved + union GPAINV_REG GPAINV; // GPIO A Input Polarity Invert Registers (GPIO0 to 31) + union GPAODR_REG GPAODR; // GPIO A Open Drain Output Register (GPIO0 to GPIO31) + Uint16 rsvd2[12]; // Reserved + union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15) + union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31) + Uint16 rsvd3[4]; // Reserved + union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7) + union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15) + union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23) + union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31) + Uint16 rsvd4[12]; // Reserved + union GPALOCK_REG GPALOCK; // GPIO A Lock Configuration Register (GPIO0 to 31) + union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to 31) + union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period Control (GPIO32 to 63) + union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + union GPBMUX1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPBMUX2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDIR_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) + Uint16 rsvd5[2]; // Reserved + union GPBINV_REG GPBINV; // GPIO B Input Polarity Invert Registers (GPIO32 to 63) + union GPBODR_REG GPBODR; // GPIO B Open Drain Output Register (GPIO32 to GPIO63) + union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63) + Uint16 rsvd6[10]; // Reserved + union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47) + union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63) + Uint16 rsvd7[4]; // Reserved + union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39) + union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47) + union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55) + union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63) + Uint16 rsvd8[12]; // Reserved + union GPBLOCK_REG GPBLOCK; // GPIO B Lock Configuration Register (GPIO32 to 63) + union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to 63) + union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 95) + union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79) + union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80 to 95) + union GPCMUX1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPCMUX2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDIR_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + union GPCPUD_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) + Uint16 rsvd9[2]; // Reserved + union GPCINV_REG GPCINV; // GPIO C Input Polarity Invert Registers (GPIO64 to 95) + union GPCODR_REG GPCODR; // GPIO C Open Drain Output Register (GPIO64 to GPIO95) + Uint16 rsvd10[12]; // Reserved + union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79) + union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80 to 95) + Uint16 rsvd11[4]; // Reserved + union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71) + union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79) + union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80 to 87) + union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 95) + Uint16 rsvd12[12]; // Reserved + union GPCLOCK_REG GPCLOCK; // GPIO C Lock Configuration Register (GPIO64 to 95) + union GPCCR_REG GPCCR; // GPIO C Lock Commit Register (GPIO64 to 95) + union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO96 to 127) + union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO96 to 111) + union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register (GPIO112 to 127) + union GPDMUX1_REG GPDMUX1; // GPIO D Mux 1 Register (GPIO96 to 111) + union GPDMUX2_REG GPDMUX2; // GPIO D Mux 2 Register (GPIO112 to 127) + union GPDDIR_REG GPDDIR; // GPIO D Direction Register (GPIO96 to 127) + union GPDPUD_REG GPDPUD; // GPIO D Pull Up Disable Register (GPIO96 to 127) + Uint16 rsvd13[2]; // Reserved + union GPDINV_REG GPDINV; // GPIO D Input Polarity Invert Registers (GPIO96 to 127) + union GPDODR_REG GPDODR; // GPIO D Open Drain Output Register (GPIO96 to GPIO127) + Uint16 rsvd14[12]; // Reserved + union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO96 to 111) + union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux (GPIO112 to 127) + Uint16 rsvd15[4]; // Reserved + union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO96 to 103) + union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 111) + union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register (GPIO112 to 119) + union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register (GPIO120 to 127) + Uint16 rsvd16[12]; // Reserved + union GPDLOCK_REG GPDLOCK; // GPIO D Lock Configuration Register (GPIO96 to 127) + union GPDCR_REG GPDCR; // GPIO D Lock Commit Register (GPIO96 to 127) + union GPECTRL_REG GPECTRL; // GPIO E Qualification Sampling Period Control (GPIO128 to 159) + union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO128 to 143) + union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register (GPIO144 to 159) + union GPEMUX1_REG GPEMUX1; // GPIO E Mux 1 Register (GPIO128 to 143) + union GPEMUX2_REG GPEMUX2; // GPIO E Mux 2 Register (GPIO144 to 159) + union GPEDIR_REG GPEDIR; // GPIO E Direction Register (GPIO128 to 159) + union GPEPUD_REG GPEPUD; // GPIO E Pull Up Disable Register (GPIO128 to 159) + Uint16 rsvd17[2]; // Reserved + union GPEINV_REG GPEINV; // GPIO E Input Polarity Invert Registers (GPIO128 to 159) + union GPEODR_REG GPEODR; // GPIO E Open Drain Output Register (GPIO128 to GPIO159) + Uint16 rsvd18[12]; // Reserved + union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO128 to 143) + union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux (GPIO144 to 159) + Uint16 rsvd19[4]; // Reserved + union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO128 to 135) + union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register (GPIO136 to 143) + union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register (GPIO144 to 151) + union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register (GPIO152 to 159) + Uint16 rsvd20[12]; // Reserved + union GPELOCK_REG GPELOCK; // GPIO E Lock Configuration Register (GPIO128 to 159) + union GPECR_REG GPECR; // GPIO E Lock Commit Register (GPIO128 to 159) + union GPFCTRL_REG GPFCTRL; // GPIO F Qualification Sampling Period Control (GPIO160 to 168) + union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register (GPIO160 to 168) + Uint16 rsvd21[2]; // Reserved + union GPFMUX1_REG GPFMUX1; // GPIO F Mux 1 Register (GPIO160 to 168) + Uint16 rsvd22[2]; // Reserved + union GPFDIR_REG GPFDIR; // GPIO F Direction Register (GPIO160 to 168) + union GPFPUD_REG GPFPUD; // GPIO F Pull Up Disable Register (GPIO160 to 168) + Uint16 rsvd23[2]; // Reserved + union GPFINV_REG GPFINV; // GPIO F Input Polarity Invert Registers (GPIO160 to 168) + union GPFODR_REG GPFODR; // GPIO F Open Drain Output Register (GPIO160 to GPIO168) + Uint16 rsvd24[12]; // Reserved + union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux (GPIO160 to 168) + Uint16 rsvd25[6]; // Reserved + union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register (GPIO160 to 167) + union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register (GPIO168) + Uint16 rsvd26[16]; // Reserved + union GPFLOCK_REG GPFLOCK; // GPIO F Lock Configuration Register (GPIO160 to 168) + union GPFCR_REG GPFCR; // GPIO F Lock Commit Register (GPIO160 to 168) +}; + +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 Data Register for this pin + Uint16 GPIO1:1; // 1 Data Register for this pin + Uint16 GPIO2:1; // 2 Data Register for this pin + Uint16 GPIO3:1; // 3 Data Register for this pin + Uint16 GPIO4:1; // 4 Data Register for this pin + Uint16 GPIO5:1; // 5 Data Register for this pin + Uint16 GPIO6:1; // 6 Data Register for this pin + Uint16 GPIO7:1; // 7 Data Register for this pin + Uint16 GPIO8:1; // 8 Data Register for this pin + Uint16 GPIO9:1; // 9 Data Register for this pin + Uint16 GPIO10:1; // 10 Data Register for this pin + Uint16 GPIO11:1; // 11 Data Register for this pin + Uint16 GPIO12:1; // 12 Data Register for this pin + Uint16 GPIO13:1; // 13 Data Register for this pin + Uint16 GPIO14:1; // 14 Data Register for this pin + Uint16 GPIO15:1; // 15 Data Register for this pin + Uint16 GPIO16:1; // 16 Data Register for this pin + Uint16 GPIO17:1; // 17 Data Register for this pin + Uint16 GPIO18:1; // 18 Data Register for this pin + Uint16 GPIO19:1; // 19 Data Register for this pin + Uint16 GPIO20:1; // 20 Data Register for this pin + Uint16 GPIO21:1; // 21 Data Register for this pin + Uint16 GPIO22:1; // 22 Data Register for this pin + Uint16 GPIO23:1; // 23 Data Register for this pin + Uint16 GPIO24:1; // 24 Data Register for this pin + Uint16 GPIO25:1; // 25 Data Register for this pin + Uint16 GPIO26:1; // 26 Data Register for this pin + Uint16 GPIO27:1; // 27 Data Register for this pin + Uint16 GPIO28:1; // 28 Data Register for this pin + Uint16 GPIO29:1; // 29 Data Register for this pin + Uint16 GPIO30:1; // 30 Data Register for this pin + Uint16 GPIO31:1; // 31 Data Register for this pin +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +struct GPASET_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Set bit for this pin + Uint16 GPIO1:1; // 1 Output Set bit for this pin + Uint16 GPIO2:1; // 2 Output Set bit for this pin + Uint16 GPIO3:1; // 3 Output Set bit for this pin + Uint16 GPIO4:1; // 4 Output Set bit for this pin + Uint16 GPIO5:1; // 5 Output Set bit for this pin + Uint16 GPIO6:1; // 6 Output Set bit for this pin + Uint16 GPIO7:1; // 7 Output Set bit for this pin + Uint16 GPIO8:1; // 8 Output Set bit for this pin + Uint16 GPIO9:1; // 9 Output Set bit for this pin + Uint16 GPIO10:1; // 10 Output Set bit for this pin + Uint16 GPIO11:1; // 11 Output Set bit for this pin + Uint16 GPIO12:1; // 12 Output Set bit for this pin + Uint16 GPIO13:1; // 13 Output Set bit for this pin + Uint16 GPIO14:1; // 14 Output Set bit for this pin + Uint16 GPIO15:1; // 15 Output Set bit for this pin + Uint16 GPIO16:1; // 16 Output Set bit for this pin + Uint16 GPIO17:1; // 17 Output Set bit for this pin + Uint16 GPIO18:1; // 18 Output Set bit for this pin + Uint16 GPIO19:1; // 19 Output Set bit for this pin + Uint16 GPIO20:1; // 20 Output Set bit for this pin + Uint16 GPIO21:1; // 21 Output Set bit for this pin + Uint16 GPIO22:1; // 22 Output Set bit for this pin + Uint16 GPIO23:1; // 23 Output Set bit for this pin + Uint16 GPIO24:1; // 24 Output Set bit for this pin + Uint16 GPIO25:1; // 25 Output Set bit for this pin + Uint16 GPIO26:1; // 26 Output Set bit for this pin + Uint16 GPIO27:1; // 27 Output Set bit for this pin + Uint16 GPIO28:1; // 28 Output Set bit for this pin + Uint16 GPIO29:1; // 29 Output Set bit for this pin + Uint16 GPIO30:1; // 30 Output Set bit for this pin + Uint16 GPIO31:1; // 31 Output Set bit for this pin +}; + +union GPASET_REG { + Uint32 all; + struct GPASET_BITS bit; +}; + +struct GPACLEAR_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Clear bit for this pin + Uint16 GPIO1:1; // 1 Output Clear bit for this pin + Uint16 GPIO2:1; // 2 Output Clear bit for this pin + Uint16 GPIO3:1; // 3 Output Clear bit for this pin + Uint16 GPIO4:1; // 4 Output Clear bit for this pin + Uint16 GPIO5:1; // 5 Output Clear bit for this pin + Uint16 GPIO6:1; // 6 Output Clear bit for this pin + Uint16 GPIO7:1; // 7 Output Clear bit for this pin + Uint16 GPIO8:1; // 8 Output Clear bit for this pin + Uint16 GPIO9:1; // 9 Output Clear bit for this pin + Uint16 GPIO10:1; // 10 Output Clear bit for this pin + Uint16 GPIO11:1; // 11 Output Clear bit for this pin + Uint16 GPIO12:1; // 12 Output Clear bit for this pin + Uint16 GPIO13:1; // 13 Output Clear bit for this pin + Uint16 GPIO14:1; // 14 Output Clear bit for this pin + Uint16 GPIO15:1; // 15 Output Clear bit for this pin + Uint16 GPIO16:1; // 16 Output Clear bit for this pin + Uint16 GPIO17:1; // 17 Output Clear bit for this pin + Uint16 GPIO18:1; // 18 Output Clear bit for this pin + Uint16 GPIO19:1; // 19 Output Clear bit for this pin + Uint16 GPIO20:1; // 20 Output Clear bit for this pin + Uint16 GPIO21:1; // 21 Output Clear bit for this pin + Uint16 GPIO22:1; // 22 Output Clear bit for this pin + Uint16 GPIO23:1; // 23 Output Clear bit for this pin + Uint16 GPIO24:1; // 24 Output Clear bit for this pin + Uint16 GPIO25:1; // 25 Output Clear bit for this pin + Uint16 GPIO26:1; // 26 Output Clear bit for this pin + Uint16 GPIO27:1; // 27 Output Clear bit for this pin + Uint16 GPIO28:1; // 28 Output Clear bit for this pin + Uint16 GPIO29:1; // 29 Output Clear bit for this pin + Uint16 GPIO30:1; // 30 Output Clear bit for this pin + Uint16 GPIO31:1; // 31 Output Clear bit for this pin +}; + +union GPACLEAR_REG { + Uint32 all; + struct GPACLEAR_BITS bit; +}; + +struct GPATOGGLE_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Toggle bit for this pin + Uint16 GPIO1:1; // 1 Output Toggle bit for this pin + Uint16 GPIO2:1; // 2 Output Toggle bit for this pin + Uint16 GPIO3:1; // 3 Output Toggle bit for this pin + Uint16 GPIO4:1; // 4 Output Toggle bit for this pin + Uint16 GPIO5:1; // 5 Output Toggle bit for this pin + Uint16 GPIO6:1; // 6 Output Toggle bit for this pin + Uint16 GPIO7:1; // 7 Output Toggle bit for this pin + Uint16 GPIO8:1; // 8 Output Toggle bit for this pin + Uint16 GPIO9:1; // 9 Output Toggle bit for this pin + Uint16 GPIO10:1; // 10 Output Toggle bit for this pin + Uint16 GPIO11:1; // 11 Output Toggle bit for this pin + Uint16 GPIO12:1; // 12 Output Toggle bit for this pin + Uint16 GPIO13:1; // 13 Output Toggle bit for this pin + Uint16 GPIO14:1; // 14 Output Toggle bit for this pin + Uint16 GPIO15:1; // 15 Output Toggle bit for this pin + Uint16 GPIO16:1; // 16 Output Toggle bit for this pin + Uint16 GPIO17:1; // 17 Output Toggle bit for this pin + Uint16 GPIO18:1; // 18 Output Toggle bit for this pin + Uint16 GPIO19:1; // 19 Output Toggle bit for this pin + Uint16 GPIO20:1; // 20 Output Toggle bit for this pin + Uint16 GPIO21:1; // 21 Output Toggle bit for this pin + Uint16 GPIO22:1; // 22 Output Toggle bit for this pin + Uint16 GPIO23:1; // 23 Output Toggle bit for this pin + Uint16 GPIO24:1; // 24 Output Toggle bit for this pin + Uint16 GPIO25:1; // 25 Output Toggle bit for this pin + Uint16 GPIO26:1; // 26 Output Toggle bit for this pin + Uint16 GPIO27:1; // 27 Output Toggle bit for this pin + Uint16 GPIO28:1; // 28 Output Toggle bit for this pin + Uint16 GPIO29:1; // 29 Output Toggle bit for this pin + Uint16 GPIO30:1; // 30 Output Toggle bit for this pin + Uint16 GPIO31:1; // 31 Output Toggle bit for this pin +}; + +union GPATOGGLE_REG { + Uint32 all; + struct GPATOGGLE_BITS bit; +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 Data Register for this pin + Uint16 GPIO33:1; // 1 Data Register for this pin + Uint16 GPIO34:1; // 2 Data Register for this pin + Uint16 GPIO35:1; // 3 Data Register for this pin + Uint16 GPIO36:1; // 4 Data Register for this pin + Uint16 GPIO37:1; // 5 Data Register for this pin + Uint16 GPIO38:1; // 6 Data Register for this pin + Uint16 GPIO39:1; // 7 Data Register for this pin + Uint16 GPIO40:1; // 8 Data Register for this pin + Uint16 GPIO41:1; // 9 Data Register for this pin + Uint16 GPIO42:1; // 10 Data Register for this pin + Uint16 GPIO43:1; // 11 Data Register for this pin + Uint16 GPIO44:1; // 12 Data Register for this pin + Uint16 GPIO45:1; // 13 Data Register for this pin + Uint16 GPIO46:1; // 14 Data Register for this pin + Uint16 GPIO47:1; // 15 Data Register for this pin + Uint16 GPIO48:1; // 16 Data Register for this pin + Uint16 GPIO49:1; // 17 Data Register for this pin + Uint16 GPIO50:1; // 18 Data Register for this pin + Uint16 GPIO51:1; // 19 Data Register for this pin + Uint16 GPIO52:1; // 20 Data Register for this pin + Uint16 GPIO53:1; // 21 Data Register for this pin + Uint16 GPIO54:1; // 22 Data Register for this pin + Uint16 GPIO55:1; // 23 Data Register for this pin + Uint16 GPIO56:1; // 24 Data Register for this pin + Uint16 GPIO57:1; // 25 Data Register for this pin + Uint16 GPIO58:1; // 26 Data Register for this pin + Uint16 GPIO59:1; // 27 Data Register for this pin + Uint16 GPIO60:1; // 28 Data Register for this pin + Uint16 GPIO61:1; // 29 Data Register for this pin + Uint16 GPIO62:1; // 30 Data Register for this pin + Uint16 GPIO63:1; // 31 Data Register for this pin +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +struct GPBSET_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Set bit for this pin + Uint16 GPIO33:1; // 1 Output Set bit for this pin + Uint16 GPIO34:1; // 2 Output Set bit for this pin + Uint16 GPIO35:1; // 3 Output Set bit for this pin + Uint16 GPIO36:1; // 4 Output Set bit for this pin + Uint16 GPIO37:1; // 5 Output Set bit for this pin + Uint16 GPIO38:1; // 6 Output Set bit for this pin + Uint16 GPIO39:1; // 7 Output Set bit for this pin + Uint16 GPIO40:1; // 8 Output Set bit for this pin + Uint16 GPIO41:1; // 9 Output Set bit for this pin + Uint16 GPIO42:1; // 10 Output Set bit for this pin + Uint16 GPIO43:1; // 11 Output Set bit for this pin + Uint16 GPIO44:1; // 12 Output Set bit for this pin + Uint16 GPIO45:1; // 13 Output Set bit for this pin + Uint16 GPIO46:1; // 14 Output Set bit for this pin + Uint16 GPIO47:1; // 15 Output Set bit for this pin + Uint16 GPIO48:1; // 16 Output Set bit for this pin + Uint16 GPIO49:1; // 17 Output Set bit for this pin + Uint16 GPIO50:1; // 18 Output Set bit for this pin + Uint16 GPIO51:1; // 19 Output Set bit for this pin + Uint16 GPIO52:1; // 20 Output Set bit for this pin + Uint16 GPIO53:1; // 21 Output Set bit for this pin + Uint16 GPIO54:1; // 22 Output Set bit for this pin + Uint16 GPIO55:1; // 23 Output Set bit for this pin + Uint16 GPIO56:1; // 24 Output Set bit for this pin + Uint16 GPIO57:1; // 25 Output Set bit for this pin + Uint16 GPIO58:1; // 26 Output Set bit for this pin + Uint16 GPIO59:1; // 27 Output Set bit for this pin + Uint16 GPIO60:1; // 28 Output Set bit for this pin + Uint16 GPIO61:1; // 29 Output Set bit for this pin + Uint16 GPIO62:1; // 30 Output Set bit for this pin + Uint16 GPIO63:1; // 31 Output Set bit for this pin +}; + +union GPBSET_REG { + Uint32 all; + struct GPBSET_BITS bit; +}; + +struct GPBCLEAR_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Clear bit for this pin + Uint16 GPIO33:1; // 1 Output Clear bit for this pin + Uint16 GPIO34:1; // 2 Output Clear bit for this pin + Uint16 GPIO35:1; // 3 Output Clear bit for this pin + Uint16 GPIO36:1; // 4 Output Clear bit for this pin + Uint16 GPIO37:1; // 5 Output Clear bit for this pin + Uint16 GPIO38:1; // 6 Output Clear bit for this pin + Uint16 GPIO39:1; // 7 Output Clear bit for this pin + Uint16 GPIO40:1; // 8 Output Clear bit for this pin + Uint16 GPIO41:1; // 9 Output Clear bit for this pin + Uint16 GPIO42:1; // 10 Output Clear bit for this pin + Uint16 GPIO43:1; // 11 Output Clear bit for this pin + Uint16 GPIO44:1; // 12 Output Clear bit for this pin + Uint16 GPIO45:1; // 13 Output Clear bit for this pin + Uint16 GPIO46:1; // 14 Output Clear bit for this pin + Uint16 GPIO47:1; // 15 Output Clear bit for this pin + Uint16 GPIO48:1; // 16 Output Clear bit for this pin + Uint16 GPIO49:1; // 17 Output Clear bit for this pin + Uint16 GPIO50:1; // 18 Output Clear bit for this pin + Uint16 GPIO51:1; // 19 Output Clear bit for this pin + Uint16 GPIO52:1; // 20 Output Clear bit for this pin + Uint16 GPIO53:1; // 21 Output Clear bit for this pin + Uint16 GPIO54:1; // 22 Output Clear bit for this pin + Uint16 GPIO55:1; // 23 Output Clear bit for this pin + Uint16 GPIO56:1; // 24 Output Clear bit for this pin + Uint16 GPIO57:1; // 25 Output Clear bit for this pin + Uint16 GPIO58:1; // 26 Output Clear bit for this pin + Uint16 GPIO59:1; // 27 Output Clear bit for this pin + Uint16 GPIO60:1; // 28 Output Clear bit for this pin + Uint16 GPIO61:1; // 29 Output Clear bit for this pin + Uint16 GPIO62:1; // 30 Output Clear bit for this pin + Uint16 GPIO63:1; // 31 Output Clear bit for this pin +}; + +union GPBCLEAR_REG { + Uint32 all; + struct GPBCLEAR_BITS bit; +}; + +struct GPBTOGGLE_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Toggle bit for this pin + Uint16 GPIO33:1; // 1 Output Toggle bit for this pin + Uint16 GPIO34:1; // 2 Output Toggle bit for this pin + Uint16 GPIO35:1; // 3 Output Toggle bit for this pin + Uint16 GPIO36:1; // 4 Output Toggle bit for this pin + Uint16 GPIO37:1; // 5 Output Toggle bit for this pin + Uint16 GPIO38:1; // 6 Output Toggle bit for this pin + Uint16 GPIO39:1; // 7 Output Toggle bit for this pin + Uint16 GPIO40:1; // 8 Output Toggle bit for this pin + Uint16 GPIO41:1; // 9 Output Toggle bit for this pin + Uint16 GPIO42:1; // 10 Output Toggle bit for this pin + Uint16 GPIO43:1; // 11 Output Toggle bit for this pin + Uint16 GPIO44:1; // 12 Output Toggle bit for this pin + Uint16 GPIO45:1; // 13 Output Toggle bit for this pin + Uint16 GPIO46:1; // 14 Output Toggle bit for this pin + Uint16 GPIO47:1; // 15 Output Toggle bit for this pin + Uint16 GPIO48:1; // 16 Output Toggle bit for this pin + Uint16 GPIO49:1; // 17 Output Toggle bit for this pin + Uint16 GPIO50:1; // 18 Output Toggle bit for this pin + Uint16 GPIO51:1; // 19 Output Toggle bit for this pin + Uint16 GPIO52:1; // 20 Output Toggle bit for this pin + Uint16 GPIO53:1; // 21 Output Toggle bit for this pin + Uint16 GPIO54:1; // 22 Output Toggle bit for this pin + Uint16 GPIO55:1; // 23 Output Toggle bit for this pin + Uint16 GPIO56:1; // 24 Output Toggle bit for this pin + Uint16 GPIO57:1; // 25 Output Toggle bit for this pin + Uint16 GPIO58:1; // 26 Output Toggle bit for this pin + Uint16 GPIO59:1; // 27 Output Toggle bit for this pin + Uint16 GPIO60:1; // 28 Output Toggle bit for this pin + Uint16 GPIO61:1; // 29 Output Toggle bit for this pin + Uint16 GPIO62:1; // 30 Output Toggle bit for this pin + Uint16 GPIO63:1; // 31 Output Toggle bit for this pin +}; + +union GPBTOGGLE_REG { + Uint32 all; + struct GPBTOGGLE_BITS bit; +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 Data Register for this pin + Uint16 GPIO65:1; // 1 Data Register for this pin + Uint16 GPIO66:1; // 2 Data Register for this pin + Uint16 GPIO67:1; // 3 Data Register for this pin + Uint16 GPIO68:1; // 4 Data Register for this pin + Uint16 GPIO69:1; // 5 Data Register for this pin + Uint16 GPIO70:1; // 6 Data Register for this pin + Uint16 GPIO71:1; // 7 Data Register for this pin + Uint16 GPIO72:1; // 8 Data Register for this pin + Uint16 GPIO73:1; // 9 Data Register for this pin + Uint16 GPIO74:1; // 10 Data Register for this pin + Uint16 GPIO75:1; // 11 Data Register for this pin + Uint16 GPIO76:1; // 12 Data Register for this pin + Uint16 GPIO77:1; // 13 Data Register for this pin + Uint16 GPIO78:1; // 14 Data Register for this pin + Uint16 GPIO79:1; // 15 Data Register for this pin + Uint16 GPIO80:1; // 16 Data Register for this pin + Uint16 GPIO81:1; // 17 Data Register for this pin + Uint16 GPIO82:1; // 18 Data Register for this pin + Uint16 GPIO83:1; // 19 Data Register for this pin + Uint16 GPIO84:1; // 20 Data Register for this pin + Uint16 GPIO85:1; // 21 Data Register for this pin + Uint16 GPIO86:1; // 22 Data Register for this pin + Uint16 GPIO87:1; // 23 Data Register for this pin + Uint16 GPIO88:1; // 24 Data Register for this pin + Uint16 GPIO89:1; // 25 Data Register for this pin + Uint16 GPIO90:1; // 26 Data Register for this pin + Uint16 GPIO91:1; // 27 Data Register for this pin + Uint16 GPIO92:1; // 28 Data Register for this pin + Uint16 GPIO93:1; // 29 Data Register for this pin + Uint16 GPIO94:1; // 30 Data Register for this pin + Uint16 GPIO95:1; // 31 Data Register for this pin +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +struct GPCSET_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Set bit for this pin + Uint16 GPIO65:1; // 1 Output Set bit for this pin + Uint16 GPIO66:1; // 2 Output Set bit for this pin + Uint16 GPIO67:1; // 3 Output Set bit for this pin + Uint16 GPIO68:1; // 4 Output Set bit for this pin + Uint16 GPIO69:1; // 5 Output Set bit for this pin + Uint16 GPIO70:1; // 6 Output Set bit for this pin + Uint16 GPIO71:1; // 7 Output Set bit for this pin + Uint16 GPIO72:1; // 8 Output Set bit for this pin + Uint16 GPIO73:1; // 9 Output Set bit for this pin + Uint16 GPIO74:1; // 10 Output Set bit for this pin + Uint16 GPIO75:1; // 11 Output Set bit for this pin + Uint16 GPIO76:1; // 12 Output Set bit for this pin + Uint16 GPIO77:1; // 13 Output Set bit for this pin + Uint16 GPIO78:1; // 14 Output Set bit for this pin + Uint16 GPIO79:1; // 15 Output Set bit for this pin + Uint16 GPIO80:1; // 16 Output Set bit for this pin + Uint16 GPIO81:1; // 17 Output Set bit for this pin + Uint16 GPIO82:1; // 18 Output Set bit for this pin + Uint16 GPIO83:1; // 19 Output Set bit for this pin + Uint16 GPIO84:1; // 20 Output Set bit for this pin + Uint16 GPIO85:1; // 21 Output Set bit for this pin + Uint16 GPIO86:1; // 22 Output Set bit for this pin + Uint16 GPIO87:1; // 23 Output Set bit for this pin + Uint16 GPIO88:1; // 24 Output Set bit for this pin + Uint16 GPIO89:1; // 25 Output Set bit for this pin + Uint16 GPIO90:1; // 26 Output Set bit for this pin + Uint16 GPIO91:1; // 27 Output Set bit for this pin + Uint16 GPIO92:1; // 28 Output Set bit for this pin + Uint16 GPIO93:1; // 29 Output Set bit for this pin + Uint16 GPIO94:1; // 30 Output Set bit for this pin + Uint16 GPIO95:1; // 31 Output Set bit for this pin +}; + +union GPCSET_REG { + Uint32 all; + struct GPCSET_BITS bit; +}; + +struct GPCCLEAR_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Clear bit for this pin + Uint16 GPIO65:1; // 1 Output Clear bit for this pin + Uint16 GPIO66:1; // 2 Output Clear bit for this pin + Uint16 GPIO67:1; // 3 Output Clear bit for this pin + Uint16 GPIO68:1; // 4 Output Clear bit for this pin + Uint16 GPIO69:1; // 5 Output Clear bit for this pin + Uint16 GPIO70:1; // 6 Output Clear bit for this pin + Uint16 GPIO71:1; // 7 Output Clear bit for this pin + Uint16 GPIO72:1; // 8 Output Clear bit for this pin + Uint16 GPIO73:1; // 9 Output Clear bit for this pin + Uint16 GPIO74:1; // 10 Output Clear bit for this pin + Uint16 GPIO75:1; // 11 Output Clear bit for this pin + Uint16 GPIO76:1; // 12 Output Clear bit for this pin + Uint16 GPIO77:1; // 13 Output Clear bit for this pin + Uint16 GPIO78:1; // 14 Output Clear bit for this pin + Uint16 GPIO79:1; // 15 Output Clear bit for this pin + Uint16 GPIO80:1; // 16 Output Clear bit for this pin + Uint16 GPIO81:1; // 17 Output Clear bit for this pin + Uint16 GPIO82:1; // 18 Output Clear bit for this pin + Uint16 GPIO83:1; // 19 Output Clear bit for this pin + Uint16 GPIO84:1; // 20 Output Clear bit for this pin + Uint16 GPIO85:1; // 21 Output Clear bit for this pin + Uint16 GPIO86:1; // 22 Output Clear bit for this pin + Uint16 GPIO87:1; // 23 Output Clear bit for this pin + Uint16 GPIO88:1; // 24 Output Clear bit for this pin + Uint16 GPIO89:1; // 25 Output Clear bit for this pin + Uint16 GPIO90:1; // 26 Output Clear bit for this pin + Uint16 GPIO91:1; // 27 Output Clear bit for this pin + Uint16 GPIO92:1; // 28 Output Clear bit for this pin + Uint16 GPIO93:1; // 29 Output Clear bit for this pin + Uint16 GPIO94:1; // 30 Output Clear bit for this pin + Uint16 GPIO95:1; // 31 Output Clear bit for this pin +}; + +union GPCCLEAR_REG { + Uint32 all; + struct GPCCLEAR_BITS bit; +}; + +struct GPCTOGGLE_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Toggle bit for this pin + Uint16 GPIO65:1; // 1 Output Toggle bit for this pin + Uint16 GPIO66:1; // 2 Output Toggle bit for this pin + Uint16 GPIO67:1; // 3 Output Toggle bit for this pin + Uint16 GPIO68:1; // 4 Output Toggle bit for this pin + Uint16 GPIO69:1; // 5 Output Toggle bit for this pin + Uint16 GPIO70:1; // 6 Output Toggle bit for this pin + Uint16 GPIO71:1; // 7 Output Toggle bit for this pin + Uint16 GPIO72:1; // 8 Output Toggle bit for this pin + Uint16 GPIO73:1; // 9 Output Toggle bit for this pin + Uint16 GPIO74:1; // 10 Output Toggle bit for this pin + Uint16 GPIO75:1; // 11 Output Toggle bit for this pin + Uint16 GPIO76:1; // 12 Output Toggle bit for this pin + Uint16 GPIO77:1; // 13 Output Toggle bit for this pin + Uint16 GPIO78:1; // 14 Output Toggle bit for this pin + Uint16 GPIO79:1; // 15 Output Toggle bit for this pin + Uint16 GPIO80:1; // 16 Output Toggle bit for this pin + Uint16 GPIO81:1; // 17 Output Toggle bit for this pin + Uint16 GPIO82:1; // 18 Output Toggle bit for this pin + Uint16 GPIO83:1; // 19 Output Toggle bit for this pin + Uint16 GPIO84:1; // 20 Output Toggle bit for this pin + Uint16 GPIO85:1; // 21 Output Toggle bit for this pin + Uint16 GPIO86:1; // 22 Output Toggle bit for this pin + Uint16 GPIO87:1; // 23 Output Toggle bit for this pin + Uint16 GPIO88:1; // 24 Output Toggle bit for this pin + Uint16 GPIO89:1; // 25 Output Toggle bit for this pin + Uint16 GPIO90:1; // 26 Output Toggle bit for this pin + Uint16 GPIO91:1; // 27 Output Toggle bit for this pin + Uint16 GPIO92:1; // 28 Output Toggle bit for this pin + Uint16 GPIO93:1; // 29 Output Toggle bit for this pin + Uint16 GPIO94:1; // 30 Output Toggle bit for this pin + Uint16 GPIO95:1; // 31 Output Toggle bit for this pin +}; + +union GPCTOGGLE_REG { + Uint32 all; + struct GPCTOGGLE_BITS bit; +}; + +struct GPDDAT_BITS { // bits description + Uint16 GPIO96:1; // 0 Data Register for this pin + Uint16 GPIO97:1; // 1 Data Register for this pin + Uint16 GPIO98:1; // 2 Data Register for this pin + Uint16 GPIO99:1; // 3 Data Register for this pin + Uint16 GPIO100:1; // 4 Data Register for this pin + Uint16 GPIO101:1; // 5 Data Register for this pin + Uint16 GPIO102:1; // 6 Data Register for this pin + Uint16 GPIO103:1; // 7 Data Register for this pin + Uint16 GPIO104:1; // 8 Data Register for this pin + Uint16 GPIO105:1; // 9 Data Register for this pin + Uint16 GPIO106:1; // 10 Data Register for this pin + Uint16 GPIO107:1; // 11 Data Register for this pin + Uint16 GPIO108:1; // 12 Data Register for this pin + Uint16 GPIO109:1; // 13 Data Register for this pin + Uint16 GPIO110:1; // 14 Data Register for this pin + Uint16 GPIO111:1; // 15 Data Register for this pin + Uint16 GPIO112:1; // 16 Data Register for this pin + Uint16 GPIO113:1; // 17 Data Register for this pin + Uint16 GPIO114:1; // 18 Data Register for this pin + Uint16 GPIO115:1; // 19 Data Register for this pin + Uint16 GPIO116:1; // 20 Data Register for this pin + Uint16 GPIO117:1; // 21 Data Register for this pin + Uint16 GPIO118:1; // 22 Data Register for this pin + Uint16 GPIO119:1; // 23 Data Register for this pin + Uint16 GPIO120:1; // 24 Data Register for this pin + Uint16 GPIO121:1; // 25 Data Register for this pin + Uint16 GPIO122:1; // 26 Data Register for this pin + Uint16 GPIO123:1; // 27 Data Register for this pin + Uint16 GPIO124:1; // 28 Data Register for this pin + Uint16 GPIO125:1; // 29 Data Register for this pin + Uint16 GPIO126:1; // 30 Data Register for this pin + Uint16 GPIO127:1; // 31 Data Register for this pin +}; + +union GPDDAT_REG { + Uint32 all; + struct GPDDAT_BITS bit; +}; + +struct GPDSET_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Set bit for this pin + Uint16 GPIO97:1; // 1 Output Set bit for this pin + Uint16 GPIO98:1; // 2 Output Set bit for this pin + Uint16 GPIO99:1; // 3 Output Set bit for this pin + Uint16 GPIO100:1; // 4 Output Set bit for this pin + Uint16 GPIO101:1; // 5 Output Set bit for this pin + Uint16 GPIO102:1; // 6 Output Set bit for this pin + Uint16 GPIO103:1; // 7 Output Set bit for this pin + Uint16 GPIO104:1; // 8 Output Set bit for this pin + Uint16 GPIO105:1; // 9 Output Set bit for this pin + Uint16 GPIO106:1; // 10 Output Set bit for this pin + Uint16 GPIO107:1; // 11 Output Set bit for this pin + Uint16 GPIO108:1; // 12 Output Set bit for this pin + Uint16 GPIO109:1; // 13 Output Set bit for this pin + Uint16 GPIO110:1; // 14 Output Set bit for this pin + Uint16 GPIO111:1; // 15 Output Set bit for this pin + Uint16 GPIO112:1; // 16 Output Set bit for this pin + Uint16 GPIO113:1; // 17 Output Set bit for this pin + Uint16 GPIO114:1; // 18 Output Set bit for this pin + Uint16 GPIO115:1; // 19 Output Set bit for this pin + Uint16 GPIO116:1; // 20 Output Set bit for this pin + Uint16 GPIO117:1; // 21 Output Set bit for this pin + Uint16 GPIO118:1; // 22 Output Set bit for this pin + Uint16 GPIO119:1; // 23 Output Set bit for this pin + Uint16 GPIO120:1; // 24 Output Set bit for this pin + Uint16 GPIO121:1; // 25 Output Set bit for this pin + Uint16 GPIO122:1; // 26 Output Set bit for this pin + Uint16 GPIO123:1; // 27 Output Set bit for this pin + Uint16 GPIO124:1; // 28 Output Set bit for this pin + Uint16 GPIO125:1; // 29 Output Set bit for this pin + Uint16 GPIO126:1; // 30 Output Set bit for this pin + Uint16 GPIO127:1; // 31 Output Set bit for this pin +}; + +union GPDSET_REG { + Uint32 all; + struct GPDSET_BITS bit; +}; + +struct GPDCLEAR_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Clear bit for this pin + Uint16 GPIO97:1; // 1 Output Clear bit for this pin + Uint16 GPIO98:1; // 2 Output Clear bit for this pin + Uint16 GPIO99:1; // 3 Output Clear bit for this pin + Uint16 GPIO100:1; // 4 Output Clear bit for this pin + Uint16 GPIO101:1; // 5 Output Clear bit for this pin + Uint16 GPIO102:1; // 6 Output Clear bit for this pin + Uint16 GPIO103:1; // 7 Output Clear bit for this pin + Uint16 GPIO104:1; // 8 Output Clear bit for this pin + Uint16 GPIO105:1; // 9 Output Clear bit for this pin + Uint16 GPIO106:1; // 10 Output Clear bit for this pin + Uint16 GPIO107:1; // 11 Output Clear bit for this pin + Uint16 GPIO108:1; // 12 Output Clear bit for this pin + Uint16 GPIO109:1; // 13 Output Clear bit for this pin + Uint16 GPIO110:1; // 14 Output Clear bit for this pin + Uint16 GPIO111:1; // 15 Output Clear bit for this pin + Uint16 GPIO112:1; // 16 Output Clear bit for this pin + Uint16 GPIO113:1; // 17 Output Clear bit for this pin + Uint16 GPIO114:1; // 18 Output Clear bit for this pin + Uint16 GPIO115:1; // 19 Output Clear bit for this pin + Uint16 GPIO116:1; // 20 Output Clear bit for this pin + Uint16 GPIO117:1; // 21 Output Clear bit for this pin + Uint16 GPIO118:1; // 22 Output Clear bit for this pin + Uint16 GPIO119:1; // 23 Output Clear bit for this pin + Uint16 GPIO120:1; // 24 Output Clear bit for this pin + Uint16 GPIO121:1; // 25 Output Clear bit for this pin + Uint16 GPIO122:1; // 26 Output Clear bit for this pin + Uint16 GPIO123:1; // 27 Output Clear bit for this pin + Uint16 GPIO124:1; // 28 Output Clear bit for this pin + Uint16 GPIO125:1; // 29 Output Clear bit for this pin + Uint16 GPIO126:1; // 30 Output Clear bit for this pin + Uint16 GPIO127:1; // 31 Output Clear bit for this pin +}; + +union GPDCLEAR_REG { + Uint32 all; + struct GPDCLEAR_BITS bit; +}; + +struct GPDTOGGLE_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Toggle bit for this pin + Uint16 GPIO97:1; // 1 Output Toggle bit for this pin + Uint16 GPIO98:1; // 2 Output Toggle bit for this pin + Uint16 GPIO99:1; // 3 Output Toggle bit for this pin + Uint16 GPIO100:1; // 4 Output Toggle bit for this pin + Uint16 GPIO101:1; // 5 Output Toggle bit for this pin + Uint16 GPIO102:1; // 6 Output Toggle bit for this pin + Uint16 GPIO103:1; // 7 Output Toggle bit for this pin + Uint16 GPIO104:1; // 8 Output Toggle bit for this pin + Uint16 GPIO105:1; // 9 Output Toggle bit for this pin + Uint16 GPIO106:1; // 10 Output Toggle bit for this pin + Uint16 GPIO107:1; // 11 Output Toggle bit for this pin + Uint16 GPIO108:1; // 12 Output Toggle bit for this pin + Uint16 GPIO109:1; // 13 Output Toggle bit for this pin + Uint16 GPIO110:1; // 14 Output Toggle bit for this pin + Uint16 GPIO111:1; // 15 Output Toggle bit for this pin + Uint16 GPIO112:1; // 16 Output Toggle bit for this pin + Uint16 GPIO113:1; // 17 Output Toggle bit for this pin + Uint16 GPIO114:1; // 18 Output Toggle bit for this pin + Uint16 GPIO115:1; // 19 Output Toggle bit for this pin + Uint16 GPIO116:1; // 20 Output Toggle bit for this pin + Uint16 GPIO117:1; // 21 Output Toggle bit for this pin + Uint16 GPIO118:1; // 22 Output Toggle bit for this pin + Uint16 GPIO119:1; // 23 Output Toggle bit for this pin + Uint16 GPIO120:1; // 24 Output Toggle bit for this pin + Uint16 GPIO121:1; // 25 Output Toggle bit for this pin + Uint16 GPIO122:1; // 26 Output Toggle bit for this pin + Uint16 GPIO123:1; // 27 Output Toggle bit for this pin + Uint16 GPIO124:1; // 28 Output Toggle bit for this pin + Uint16 GPIO125:1; // 29 Output Toggle bit for this pin + Uint16 GPIO126:1; // 30 Output Toggle bit for this pin + Uint16 GPIO127:1; // 31 Output Toggle bit for this pin +}; + +union GPDTOGGLE_REG { + Uint32 all; + struct GPDTOGGLE_BITS bit; +}; + +struct GPEDAT_BITS { // bits description + Uint16 GPIO128:1; // 0 Data Register for this pin + Uint16 GPIO129:1; // 1 Data Register for this pin + Uint16 GPIO130:1; // 2 Data Register for this pin + Uint16 GPIO131:1; // 3 Data Register for this pin + Uint16 GPIO132:1; // 4 Data Register for this pin + Uint16 GPIO133:1; // 5 Data Register for this pin + Uint16 GPIO134:1; // 6 Data Register for this pin + Uint16 GPIO135:1; // 7 Data Register for this pin + Uint16 GPIO136:1; // 8 Data Register for this pin + Uint16 GPIO137:1; // 9 Data Register for this pin + Uint16 GPIO138:1; // 10 Data Register for this pin + Uint16 GPIO139:1; // 11 Data Register for this pin + Uint16 GPIO140:1; // 12 Data Register for this pin + Uint16 GPIO141:1; // 13 Data Register for this pin + Uint16 GPIO142:1; // 14 Data Register for this pin + Uint16 GPIO143:1; // 15 Data Register for this pin + Uint16 GPIO144:1; // 16 Data Register for this pin + Uint16 GPIO145:1; // 17 Data Register for this pin + Uint16 GPIO146:1; // 18 Data Register for this pin + Uint16 GPIO147:1; // 19 Data Register for this pin + Uint16 GPIO148:1; // 20 Data Register for this pin + Uint16 GPIO149:1; // 21 Data Register for this pin + Uint16 GPIO150:1; // 22 Data Register for this pin + Uint16 GPIO151:1; // 23 Data Register for this pin + Uint16 GPIO152:1; // 24 Data Register for this pin + Uint16 GPIO153:1; // 25 Data Register for this pin + Uint16 GPIO154:1; // 26 Data Register for this pin + Uint16 GPIO155:1; // 27 Data Register for this pin + Uint16 GPIO156:1; // 28 Data Register for this pin + Uint16 GPIO157:1; // 29 Data Register for this pin + Uint16 GPIO158:1; // 30 Data Register for this pin + Uint16 GPIO159:1; // 31 Data Register for this pin +}; + +union GPEDAT_REG { + Uint32 all; + struct GPEDAT_BITS bit; +}; + +struct GPESET_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Set bit for this pin + Uint16 GPIO129:1; // 1 Output Set bit for this pin + Uint16 GPIO130:1; // 2 Output Set bit for this pin + Uint16 GPIO131:1; // 3 Output Set bit for this pin + Uint16 GPIO132:1; // 4 Output Set bit for this pin + Uint16 GPIO133:1; // 5 Output Set bit for this pin + Uint16 GPIO134:1; // 6 Output Set bit for this pin + Uint16 GPIO135:1; // 7 Output Set bit for this pin + Uint16 GPIO136:1; // 8 Output Set bit for this pin + Uint16 GPIO137:1; // 9 Output Set bit for this pin + Uint16 GPIO138:1; // 10 Output Set bit for this pin + Uint16 GPIO139:1; // 11 Output Set bit for this pin + Uint16 GPIO140:1; // 12 Output Set bit for this pin + Uint16 GPIO141:1; // 13 Output Set bit for this pin + Uint16 GPIO142:1; // 14 Output Set bit for this pin + Uint16 GPIO143:1; // 15 Output Set bit for this pin + Uint16 GPIO144:1; // 16 Output Set bit for this pin + Uint16 GPIO145:1; // 17 Output Set bit for this pin + Uint16 GPIO146:1; // 18 Output Set bit for this pin + Uint16 GPIO147:1; // 19 Output Set bit for this pin + Uint16 GPIO148:1; // 20 Output Set bit for this pin + Uint16 GPIO149:1; // 21 Output Set bit for this pin + Uint16 GPIO150:1; // 22 Output Set bit for this pin + Uint16 GPIO151:1; // 23 Output Set bit for this pin + Uint16 GPIO152:1; // 24 Output Set bit for this pin + Uint16 GPIO153:1; // 25 Output Set bit for this pin + Uint16 GPIO154:1; // 26 Output Set bit for this pin + Uint16 GPIO155:1; // 27 Output Set bit for this pin + Uint16 GPIO156:1; // 28 Output Set bit for this pin + Uint16 GPIO157:1; // 29 Output Set bit for this pin + Uint16 GPIO158:1; // 30 Output Set bit for this pin + Uint16 GPIO159:1; // 31 Output Set bit for this pin +}; + +union GPESET_REG { + Uint32 all; + struct GPESET_BITS bit; +}; + +struct GPECLEAR_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Clear bit for this pin + Uint16 GPIO129:1; // 1 Output Clear bit for this pin + Uint16 GPIO130:1; // 2 Output Clear bit for this pin + Uint16 GPIO131:1; // 3 Output Clear bit for this pin + Uint16 GPIO132:1; // 4 Output Clear bit for this pin + Uint16 GPIO133:1; // 5 Output Clear bit for this pin + Uint16 GPIO134:1; // 6 Output Clear bit for this pin + Uint16 GPIO135:1; // 7 Output Clear bit for this pin + Uint16 GPIO136:1; // 8 Output Clear bit for this pin + Uint16 GPIO137:1; // 9 Output Clear bit for this pin + Uint16 GPIO138:1; // 10 Output Clear bit for this pin + Uint16 GPIO139:1; // 11 Output Clear bit for this pin + Uint16 GPIO140:1; // 12 Output Clear bit for this pin + Uint16 GPIO141:1; // 13 Output Clear bit for this pin + Uint16 GPIO142:1; // 14 Output Clear bit for this pin + Uint16 GPIO143:1; // 15 Output Clear bit for this pin + Uint16 GPIO144:1; // 16 Output Clear bit for this pin + Uint16 GPIO145:1; // 17 Output Clear bit for this pin + Uint16 GPIO146:1; // 18 Output Clear bit for this pin + Uint16 GPIO147:1; // 19 Output Clear bit for this pin + Uint16 GPIO148:1; // 20 Output Clear bit for this pin + Uint16 GPIO149:1; // 21 Output Clear bit for this pin + Uint16 GPIO150:1; // 22 Output Clear bit for this pin + Uint16 GPIO151:1; // 23 Output Clear bit for this pin + Uint16 GPIO152:1; // 24 Output Clear bit for this pin + Uint16 GPIO153:1; // 25 Output Clear bit for this pin + Uint16 GPIO154:1; // 26 Output Clear bit for this pin + Uint16 GPIO155:1; // 27 Output Clear bit for this pin + Uint16 GPIO156:1; // 28 Output Clear bit for this pin + Uint16 GPIO157:1; // 29 Output Clear bit for this pin + Uint16 GPIO158:1; // 30 Output Clear bit for this pin + Uint16 GPIO159:1; // 31 Output Clear bit for this pin +}; + +union GPECLEAR_REG { + Uint32 all; + struct GPECLEAR_BITS bit; +}; + +struct GPETOGGLE_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Toggle bit for this pin + Uint16 GPIO129:1; // 1 Output Toggle bit for this pin + Uint16 GPIO130:1; // 2 Output Toggle bit for this pin + Uint16 GPIO131:1; // 3 Output Toggle bit for this pin + Uint16 GPIO132:1; // 4 Output Toggle bit for this pin + Uint16 GPIO133:1; // 5 Output Toggle bit for this pin + Uint16 GPIO134:1; // 6 Output Toggle bit for this pin + Uint16 GPIO135:1; // 7 Output Toggle bit for this pin + Uint16 GPIO136:1; // 8 Output Toggle bit for this pin + Uint16 GPIO137:1; // 9 Output Toggle bit for this pin + Uint16 GPIO138:1; // 10 Output Toggle bit for this pin + Uint16 GPIO139:1; // 11 Output Toggle bit for this pin + Uint16 GPIO140:1; // 12 Output Toggle bit for this pin + Uint16 GPIO141:1; // 13 Output Toggle bit for this pin + Uint16 GPIO142:1; // 14 Output Toggle bit for this pin + Uint16 GPIO143:1; // 15 Output Toggle bit for this pin + Uint16 GPIO144:1; // 16 Output Toggle bit for this pin + Uint16 GPIO145:1; // 17 Output Toggle bit for this pin + Uint16 GPIO146:1; // 18 Output Toggle bit for this pin + Uint16 GPIO147:1; // 19 Output Toggle bit for this pin + Uint16 GPIO148:1; // 20 Output Toggle bit for this pin + Uint16 GPIO149:1; // 21 Output Toggle bit for this pin + Uint16 GPIO150:1; // 22 Output Toggle bit for this pin + Uint16 GPIO151:1; // 23 Output Toggle bit for this pin + Uint16 GPIO152:1; // 24 Output Toggle bit for this pin + Uint16 GPIO153:1; // 25 Output Toggle bit for this pin + Uint16 GPIO154:1; // 26 Output Toggle bit for this pin + Uint16 GPIO155:1; // 27 Output Toggle bit for this pin + Uint16 GPIO156:1; // 28 Output Toggle bit for this pin + Uint16 GPIO157:1; // 29 Output Toggle bit for this pin + Uint16 GPIO158:1; // 30 Output Toggle bit for this pin + Uint16 GPIO159:1; // 31 Output Toggle bit for this pin +}; + +union GPETOGGLE_REG { + Uint32 all; + struct GPETOGGLE_BITS bit; +}; + +struct GPFDAT_BITS { // bits description + Uint16 GPIO160:1; // 0 Data Register for this pin + Uint16 GPIO161:1; // 1 Data Register for this pin + Uint16 GPIO162:1; // 2 Data Register for this pin + Uint16 GPIO163:1; // 3 Data Register for this pin + Uint16 GPIO164:1; // 4 Data Register for this pin + Uint16 GPIO165:1; // 5 Data Register for this pin + Uint16 GPIO166:1; // 6 Data Register for this pin + Uint16 GPIO167:1; // 7 Data Register for this pin + Uint16 GPIO168:1; // 8 Data Register for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFDAT_REG { + Uint32 all; + struct GPFDAT_BITS bit; +}; + +struct GPFSET_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Set bit for this pin + Uint16 GPIO161:1; // 1 Output Set bit for this pin + Uint16 GPIO162:1; // 2 Output Set bit for this pin + Uint16 GPIO163:1; // 3 Output Set bit for this pin + Uint16 GPIO164:1; // 4 Output Set bit for this pin + Uint16 GPIO165:1; // 5 Output Set bit for this pin + Uint16 GPIO166:1; // 6 Output Set bit for this pin + Uint16 GPIO167:1; // 7 Output Set bit for this pin + Uint16 GPIO168:1; // 8 Output Set bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFSET_REG { + Uint32 all; + struct GPFSET_BITS bit; +}; + +struct GPFCLEAR_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Clear bit for this pin + Uint16 GPIO161:1; // 1 Output Clear bit for this pin + Uint16 GPIO162:1; // 2 Output Clear bit for this pin + Uint16 GPIO163:1; // 3 Output Clear bit for this pin + Uint16 GPIO164:1; // 4 Output Clear bit for this pin + Uint16 GPIO165:1; // 5 Output Clear bit for this pin + Uint16 GPIO166:1; // 6 Output Clear bit for this pin + Uint16 GPIO167:1; // 7 Output Clear bit for this pin + Uint16 GPIO168:1; // 8 Output Clear bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFCLEAR_REG { + Uint32 all; + struct GPFCLEAR_BITS bit; +}; + +struct GPFTOGGLE_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Toggle bit for this pin + Uint16 GPIO161:1; // 1 Output Toggle bit for this pin + Uint16 GPIO162:1; // 2 Output Toggle bit for this pin + Uint16 GPIO163:1; // 3 Output Toggle bit for this pin + Uint16 GPIO164:1; // 4 Output Toggle bit for this pin + Uint16 GPIO165:1; // 5 Output Toggle bit for this pin + Uint16 GPIO166:1; // 6 Output Toggle bit for this pin + Uint16 GPIO167:1; // 7 Output Toggle bit for this pin + Uint16 GPIO168:1; // 8 Output Toggle bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFTOGGLE_REG { + Uint32 all; + struct GPFTOGGLE_BITS bit; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to 31) + union GPASET_REG GPASET; // GPIO A Data Set Register (GPIO0 to 31) + union GPACLEAR_REG GPACLEAR; // GPIO A Data Clear Register (GPIO0 to 31) + union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31) + union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to 63) + union GPBSET_REG GPBSET; // GPIO B Data Set Register (GPIO32 to 63) + union GPBCLEAR_REG GPBCLEAR; // GPIO B Data Clear Register (GPIO32 to 63) + union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63) + union GPCDAT_REG GPCDAT; // GPIO C Data Register (GPIO64 to 95) + union GPCSET_REG GPCSET; // GPIO C Data Set Register (GPIO64 to 95) + union GPCCLEAR_REG GPCCLEAR; // GPIO C Data Clear Register (GPIO64 to 95) + union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 95) + union GPDDAT_REG GPDDAT; // GPIO D Data Register (GPIO96 to 127) + union GPDSET_REG GPDSET; // GPIO D Data Set Register (GPIO96 to 127) + union GPDCLEAR_REG GPDCLEAR; // GPIO D Data Clear Register (GPIO96 to 127) + union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127) + union GPEDAT_REG GPEDAT; // GPIO E Data Register (GPIO128 to 159) + union GPESET_REG GPESET; // GPIO E Data Set Register (GPIO128 to 159) + union GPECLEAR_REG GPECLEAR; // GPIO E Data Clear Register (GPIO128 to 159) + union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO128 to 159) + union GPFDAT_REG GPFDAT; // GPIO F Data Register (GPIO160 to 168) + union GPFSET_REG GPFSET; // GPIO F Data Set Register (GPIO160 to 168) + union GPFCLEAR_REG GPFCLEAR; // GPIO F Data Clear Register (GPIO160 to 168) + union GPFTOGGLE_REG GPFTOGGLE; // GPIO F Data Toggle Register (GPIO160 to 168) +}; + +//--------------------------------------------------------------------------- +// GPIO External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +#endif +#ifdef CPU2 +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h new file mode 100644 index 0000000000..470f5a398d --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h @@ -0,0 +1,256 @@ +//########################################################################### +// +// FILE: F2837xD_i2c.h +// +// TITLE: I2C Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_I2C_H__ +#define __F2837xD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// I2C Individual Register Bit Definitions: + +struct I2COAR_BITS { // bits description + Uint16 OAR:10; // 9:0 I2C Own address + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union I2COAR_REG { + Uint16 all; + struct I2COAR_BITS bit; +}; + +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable + Uint16 NACK:1; // 1 No-acknowledgment interrupt enable + Uint16 ARDY:1; // 2 Register-access-ready interrupt enable + Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable + Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable + Uint16 SCD:1; // 5 Stop condition detected interrupt enable + Uint16 AAS:1; // 6 Addressed as slave interrupt enable + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit + Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. + Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit + Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. + Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. + Uint16 SCD:1; // 5 Stop condition detected bit. + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 AD0:1; // 8 Address 0 bits + Uint16 AAS:1; // 9 Addressed-as-slave bit + Uint16 XSMT:1; // 10 Transmit shift register empty bit. + Uint16 RSFULL:1; // 11 Receive shift register full bit. + Uint16 BB:1; // 12 Bus busy bit. + Uint16 NACKSNT:1; // 13 NACK sent bit. + Uint16 SDIR:1; // 14 Slave direction bit + Uint16 rsvd2:1; // 15 Reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +struct I2CDRR_BITS { // bits description + Uint16 DATA:8; // 7:0 Receive data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CDRR_REG { + Uint16 all; + struct I2CDRR_BITS bit; +}; + +struct I2CSAR_BITS { // bits description + Uint16 SAR:10; // 9:0 Slave Address + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union I2CSAR_REG { + Uint16 all; + struct I2CSAR_BITS bit; +}; + +struct I2CDXR_BITS { // bits description + Uint16 DATA:8; // 7:0 Transmit data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CDXR_REG { + Uint16 all; + struct I2CDXR_BITS bit; +}; + +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count bits. + Uint16 FDF:1; // 3 Free Data Format + Uint16 STB:1; // 4 START Byte Mode + Uint16 IRS:1; // 5 I2C Module Reset + Uint16 DLB:1; // 6 Digital Loopback Mode + Uint16 RM:1; // 7 Repeat Mode + Uint16 XA:1; // 8 Expanded Address Mode + Uint16 TRX:1; // 9 Transmitter Mode + Uint16 MST:1; // 10 Master Mode + Uint16 STP:1; // 11 STOP Condition + Uint16 rsvd1:1; // 12 Reserved + Uint16 STT:1; // 13 START condition bit + Uint16 FREE:1; // 14 Debug Action + Uint16 NACKMOD:1; // 15 NACK mode bit +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code bits. + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 WRITE_ZEROS:4; // 11:8 Reserved + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +struct I2CEMDR_BITS { // bits description + Uint16 BC:1; // 0 Backwards compatibility mode + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level + Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable + Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear + Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag + Uint16 TXFFST:5; // 12:8 Transmit FIFO Status + Uint16 TXFFRST:1; // 13 Transmit FIFO Reset + Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable + Uint16 rsvd1:1; // 15 Reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level + Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable + Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear + Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag + Uint16 RXFFST:5; // 12:8 Receive FIFO Status + Uint16 RXFFRST:1; // 13 Receive FIFO Reset + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + union I2COAR_REG I2COAR; // I2C Own address + union I2CIER_REG I2CIER; // I2C Interrupt Enable + union I2CSTR_REG I2CSTR; // I2C Status + Uint16 I2CCLKL; // I2C Clock low-time divider + Uint16 I2CCLKH; // I2C Clock high-time divider + Uint16 I2CCNT; // I2C Data count + union I2CDRR_REG I2CDRR; // I2C Data receive + union I2CSAR_REG I2CSAR; // I2C Slave address + union I2CDXR_REG I2CDXR; // I2C Data Transmit + union I2CMDR_REG I2CMDR; // I2C Mode + union I2CISRC_REG I2CISRC; // I2C Interrupt Source + union I2CEMDR_REG I2CEMDR; // I2C Extended Mode + union I2CPSC_REG I2CPSC; // I2C Prescaler + Uint16 rsvd1[19]; // Reserved + union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit + union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive +}; + +//--------------------------------------------------------------------------- +// I2C External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct I2C_REGS I2caRegs; +extern volatile struct I2C_REGS I2cbRegs; +#endif +#ifdef CPU2 +extern volatile struct I2C_REGS I2caRegs; +extern volatile struct I2C_REGS I2cbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h new file mode 100644 index 0000000000..ef3abbe3ab --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: F2837xD_input_xbar.h +// +// TITLE: INPUT_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_INPUT_XBAR_H__ +#define __F2837xD_INPUT_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// INPUT_XBAR Individual Register Bit Definitions: + +struct INPUTSELECTLOCK_BITS { // bits description + Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register + Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register + Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register + Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register + Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register + Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register + Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register + Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register + Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register + Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register + Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register + Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register + Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register + Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register + Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register + Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union INPUTSELECTLOCK_REG { + Uint32 all; + struct INPUTSELECTLOCK_BITS bit; +}; + +struct INPUT_XBAR_REGS { + Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) + Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) + Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) + Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) + Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) + Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) + Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) + Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) + Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) + Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) + Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) + Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) + Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) + Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) + Uint16 rsvd1[16]; // Reserved + union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register +}; + +//--------------------------------------------------------------------------- +// INPUT_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h new file mode 100644 index 0000000000..411ef4c80b --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h @@ -0,0 +1,313 @@ +//########################################################################### +// +// FILE: F2837xD_ipc.h +// +// TITLE: IPC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_IPC_H__ +#define __F2837xD_IPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// IPC Individual Register Bit Definitions: + +struct IPCACK_BITS { // bits description + Uint16 IPC0:1; // 0 Local IPC Flag 0 Acknowledgement + Uint16 IPC1:1; // 1 Local IPC Flag 1 Acknowledgement + Uint16 IPC2:1; // 2 Local IPC Flag 2 Acknowledgement + Uint16 IPC3:1; // 3 Local IPC Flag 3 Acknowledgement + Uint16 IPC4:1; // 4 Local IPC Flag 4 Acknowledgement + Uint16 IPC5:1; // 5 Local IPC Flag 5 Acknowledgement + Uint16 IPC6:1; // 6 Local IPC Flag 6 Acknowledgement + Uint16 IPC7:1; // 7 Local IPC Flag 7 Acknowledgement + Uint16 IPC8:1; // 8 Local IPC Flag 8 Acknowledgement + Uint16 IPC9:1; // 9 Local IPC Flag 9 Acknowledgement + Uint16 IPC10:1; // 10 Local IPC Flag 10 Acknowledgement + Uint16 IPC11:1; // 11 Local IPC Flag 11 Acknowledgement + Uint16 IPC12:1; // 12 Local IPC Flag 12 Acknowledgement + Uint16 IPC13:1; // 13 Local IPC Flag 13 Acknowledgement + Uint16 IPC14:1; // 14 Local IPC Flag 14 Acknowledgement + Uint16 IPC15:1; // 15 Local IPC Flag 15 Acknowledgement + Uint16 IPC16:1; // 16 Local IPC Flag 16 Acknowledgement + Uint16 IPC17:1; // 17 Local IPC Flag 17 Acknowledgement + Uint16 IPC18:1; // 18 Local IPC Flag 18 Acknowledgement + Uint16 IPC19:1; // 19 Local IPC Flag 19 Acknowledgement + Uint16 IPC20:1; // 20 Local IPC Flag 20 Acknowledgement + Uint16 IPC21:1; // 21 Local IPC Flag 21 Acknowledgement + Uint16 IPC22:1; // 22 Local IPC Flag 22 Acknowledgement + Uint16 IPC23:1; // 23 Local IPC Flag 23 Acknowledgement + Uint16 IPC24:1; // 24 Local IPC Flag 24 Acknowledgement + Uint16 IPC25:1; // 25 Local IPC Flag 25 Acknowledgement + Uint16 IPC26:1; // 26 Local IPC Flag 26 Acknowledgement + Uint16 IPC27:1; // 27 Local IPC Flag 27 Acknowledgement + Uint16 IPC28:1; // 28 Local IPC Flag 28 Acknowledgement + Uint16 IPC29:1; // 29 Local IPC Flag 29 Acknowledgement + Uint16 IPC30:1; // 30 Local IPC Flag 30 Acknowledgement + Uint16 IPC31:1; // 31 Local IPC Flag 31 Acknowledgement +}; + +union IPCACK_REG { + Uint32 all; + struct IPCACK_BITS bit; +}; + +struct IPCSTS_BITS { // bits description + Uint16 IPC0:1; // 0 Local IPC Flag 0 Status + Uint16 IPC1:1; // 1 Local IPC Flag 1 Status + Uint16 IPC2:1; // 2 Local IPC Flag 2 Status + Uint16 IPC3:1; // 3 Local IPC Flag 3 Status + Uint16 IPC4:1; // 4 Local IPC Flag 4 Status + Uint16 IPC5:1; // 5 Local IPC Flag 5 Status + Uint16 IPC6:1; // 6 Local IPC Flag 6 Status + Uint16 IPC7:1; // 7 Local IPC Flag 7 Status + Uint16 IPC8:1; // 8 Local IPC Flag 8 Status + Uint16 IPC9:1; // 9 Local IPC Flag 9 Status + Uint16 IPC10:1; // 10 Local IPC Flag 10 Status + Uint16 IPC11:1; // 11 Local IPC Flag 11 Status + Uint16 IPC12:1; // 12 Local IPC Flag 12 Status + Uint16 IPC13:1; // 13 Local IPC Flag 13 Status + Uint16 IPC14:1; // 14 Local IPC Flag 14 Status + Uint16 IPC15:1; // 15 Local IPC Flag 15 Status + Uint16 IPC16:1; // 16 Local IPC Flag 16 Status + Uint16 IPC17:1; // 17 Local IPC Flag 17 Status + Uint16 IPC18:1; // 18 Local IPC Flag 18 Status + Uint16 IPC19:1; // 19 Local IPC Flag 19 Status + Uint16 IPC20:1; // 20 Local IPC Flag 20 Status + Uint16 IPC21:1; // 21 Local IPC Flag 21 Status + Uint16 IPC22:1; // 22 Local IPC Flag 22 Status + Uint16 IPC23:1; // 23 Local IPC Flag 23 Status + Uint16 IPC24:1; // 24 Local IPC Flag 24 Status + Uint16 IPC25:1; // 25 Local IPC Flag 25 Status + Uint16 IPC26:1; // 26 Local IPC Flag 26 Status + Uint16 IPC27:1; // 27 Local IPC Flag 27 Status + Uint16 IPC28:1; // 28 Local IPC Flag 28 Status + Uint16 IPC29:1; // 29 Local IPC Flag 29 Status + Uint16 IPC30:1; // 30 Local IPC Flag 30 Status + Uint16 IPC31:1; // 31 Local IPC Flag 31 Status +}; + +union IPCSTS_REG { + Uint32 all; + struct IPCSTS_BITS bit; +}; + +struct IPCSET_BITS { // bits description + Uint16 IPC0:1; // 0 Set Remote IPC0 Flag + Uint16 IPC1:1; // 1 Set Remote IPC1 Flag + Uint16 IPC2:1; // 2 Set Remote IPC2 Flag + Uint16 IPC3:1; // 3 Set Remote IPC3 Flag + Uint16 IPC4:1; // 4 Set Remote IPC4 Flag + Uint16 IPC5:1; // 5 Set Remote IPC5 Flag + Uint16 IPC6:1; // 6 Set Remote IPC6 Flag + Uint16 IPC7:1; // 7 Set Remote IPC7 Flag + Uint16 IPC8:1; // 8 Set Remote IPC8 Flag + Uint16 IPC9:1; // 9 Set Remote IPC9 Flag + Uint16 IPC10:1; // 10 Set Remote IPC10 Flag + Uint16 IPC11:1; // 11 Set Remote IPC11 Flag + Uint16 IPC12:1; // 12 Set Remote IPC12 Flag + Uint16 IPC13:1; // 13 Set Remote IPC13 Flag + Uint16 IPC14:1; // 14 Set Remote IPC14 Flag + Uint16 IPC15:1; // 15 Set Remote IPC15 Flag + Uint16 IPC16:1; // 16 Set Remote IPC16 Flag + Uint16 IPC17:1; // 17 Set Remote IPC17 Flag + Uint16 IPC18:1; // 18 Set Remote IPC18 Flag + Uint16 IPC19:1; // 19 Set Remote IPC19 Flag + Uint16 IPC20:1; // 20 Set Remote IPC20 Flag + Uint16 IPC21:1; // 21 Set Remote IPC21 Flag + Uint16 IPC22:1; // 22 Set Remote IPC22 Flag + Uint16 IPC23:1; // 23 Set Remote IPC23 Flag + Uint16 IPC24:1; // 24 Set Remote IPC24 Flag + Uint16 IPC25:1; // 25 Set Remote IPC25 Flag + Uint16 IPC26:1; // 26 Set Remote IPC26 Flag + Uint16 IPC27:1; // 27 Set Remote IPC27 Flag + Uint16 IPC28:1; // 28 Set Remote IPC28 Flag + Uint16 IPC29:1; // 29 Set Remote IPC29 Flag + Uint16 IPC30:1; // 30 Set Remote IPC30 Flag + Uint16 IPC31:1; // 31 Set Remote IPC31 Flag +}; + +union IPCSET_REG { + Uint32 all; + struct IPCSET_BITS bit; +}; + +struct IPCCLR_BITS { // bits description + Uint16 IPC0:1; // 0 Clear Remote IPC0 Flag + Uint16 IPC1:1; // 1 Clear Remote IPC1 Flag + Uint16 IPC2:1; // 2 Clear Remote IPC2 Flag + Uint16 IPC3:1; // 3 Clear Remote IPC3 Flag + Uint16 IPC4:1; // 4 Clear Remote IPC4 Flag + Uint16 IPC5:1; // 5 Clear Remote IPC5 Flag + Uint16 IPC6:1; // 6 Clear Remote IPC6 Flag + Uint16 IPC7:1; // 7 Clear Remote IPC7 Flag + Uint16 IPC8:1; // 8 Clear Remote IPC8 Flag + Uint16 IPC9:1; // 9 Clear Remote IPC9 Flag + Uint16 IPC10:1; // 10 Clear Remote IPC10 Flag + Uint16 IPC11:1; // 11 Clear Remote IPC11 Flag + Uint16 IPC12:1; // 12 Clear Remote IPC12 Flag + Uint16 IPC13:1; // 13 Clear Remote IPC13 Flag + Uint16 IPC14:1; // 14 Clear Remote IPC14 Flag + Uint16 IPC15:1; // 15 Clear Remote IPC15 Flag + Uint16 IPC16:1; // 16 Clear Remote IPC16 Flag + Uint16 IPC17:1; // 17 Clear Remote IPC17 Flag + Uint16 IPC18:1; // 18 Clear Remote IPC18 Flag + Uint16 IPC19:1; // 19 Clear Remote IPC19 Flag + Uint16 IPC20:1; // 20 Clear Remote IPC20 Flag + Uint16 IPC21:1; // 21 Clear Remote IPC21 Flag + Uint16 IPC22:1; // 22 Clear Remote IPC22 Flag + Uint16 IPC23:1; // 23 Clear Remote IPC23 Flag + Uint16 IPC24:1; // 24 Clear Remote IPC24 Flag + Uint16 IPC25:1; // 25 Clear Remote IPC25 Flag + Uint16 IPC26:1; // 26 Clear Remote IPC26 Flag + Uint16 IPC27:1; // 27 Clear Remote IPC27 Flag + Uint16 IPC28:1; // 28 Clear Remote IPC28 Flag + Uint16 IPC29:1; // 29 Clear Remote IPC29 Flag + Uint16 IPC30:1; // 30 Clear Remote IPC30 Flag + Uint16 IPC31:1; // 31 Clear Remote IPC31 Flag +}; + +union IPCCLR_REG { + Uint32 all; + struct IPCCLR_BITS bit; +}; + +struct IPCFLG_BITS { // bits description + Uint16 IPC0:1; // 0 Remote IPC0 Flag Status + Uint16 IPC1:1; // 1 Remote IPC1 Flag Status + Uint16 IPC2:1; // 2 Remote IPC2 Flag Status + Uint16 IPC3:1; // 3 Remote IPC3 Flag Status + Uint16 IPC4:1; // 4 Remote IPC4 Flag Status + Uint16 IPC5:1; // 5 Remote IPC5 Flag Status + Uint16 IPC6:1; // 6 Remote IPC6 Flag Status + Uint16 IPC7:1; // 7 Remote IPC7 Flag Status + Uint16 IPC8:1; // 8 Remote IPC8 Flag Status + Uint16 IPC9:1; // 9 Remote IPC9 Flag Status + Uint16 IPC10:1; // 10 Remote IPC10 Flag Status + Uint16 IPC11:1; // 11 Remote IPC11 Flag Status + Uint16 IPC12:1; // 12 Remote IPC12 Flag Status + Uint16 IPC13:1; // 13 Remote IPC13 Flag Status + Uint16 IPC14:1; // 14 Remote IPC14 Flag Status + Uint16 IPC15:1; // 15 Remote IPC15 Flag Status + Uint16 IPC16:1; // 16 Remote IPC16 Flag Status + Uint16 IPC17:1; // 17 Remote IPC17 Flag Status + Uint16 IPC18:1; // 18 Remote IPC18 Flag Status + Uint16 IPC19:1; // 19 Remote IPC19 Flag Status + Uint16 IPC20:1; // 20 Remote IPC20 Flag Status + Uint16 IPC21:1; // 21 Remote IPC21 Flag Status + Uint16 IPC22:1; // 22 Remote IPC22 Flag Status + Uint16 IPC23:1; // 23 Remote IPC23 Flag Status + Uint16 IPC24:1; // 24 Remote IPC24 Flag Status + Uint16 IPC25:1; // 25 Remote IPC25 Flag Status + Uint16 IPC26:1; // 26 Remote IPC26 Flag Status + Uint16 IPC27:1; // 27 Remote IPC27 Flag Status + Uint16 IPC28:1; // 28 Remote IPC28 Flag Status + Uint16 IPC29:1; // 29 Remote IPC29 Flag Status + Uint16 IPC30:1; // 30 Remote IPC30 Flag Status + Uint16 IPC31:1; // 31 Remote IPC31 Flag Status +}; + +union IPCFLG_REG { + Uint32 all; + struct IPCFLG_BITS bit; +}; + +struct IPC_REGS_CPU1 { + union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register + union IPCSTS_REG IPCSTS; // IPC incoming flag status register + union IPCSET_REG IPCSET; // IPC remote flag set register + union IPCCLR_REG IPCCLR; // IPC remote flag clear register + union IPCFLG_REG IPCFLG; // IPC remote flag status register + Uint16 rsvd1[2]; // Reserved + Uint32 IPCCOUNTERL; // IPC Counter Low Register + Uint32 IPCCOUNTERH; // IPC Counter High Register + Uint32 IPCSENDCOM; // Local to Remote IPC Command Register + Uint32 IPCSENDADDR; // Local to Remote IPC Address Register + Uint32 IPCSENDDATA; // Local to Remote IPC Data Register + Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register + Uint32 IPCRECVCOM; // Remote to Local IPC Command Register + Uint32 IPCRECVADDR; // Remote to Local IPC Address Register + Uint32 IPCRECVDATA; // Remote to Local IPC Data Register + Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register + Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register + Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register +}; + +struct IPC_REGS_CPU2 { + union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register + union IPCSTS_REG IPCSTS; // IPC incoming flag status register + union IPCSET_REG IPCSET; // IPC remote flag set register + union IPCCLR_REG IPCCLR; // IPC remote flag clear register + union IPCFLG_REG IPCFLG; // IPC remote flag status register + Uint16 rsvd1[2]; // Reserved + Uint32 IPCCOUNTERL; // IPC Counter Low Register + Uint32 IPCCOUNTERH; // IPC Counter High Register + Uint32 IPCRECVCOM; // Remote to Local IPC Command Register + Uint32 IPCRECVADDR; // Remote to Local IPC Address Register + Uint32 IPCRECVDATA; // Remote to Local IPC Data Register + Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register + Uint32 IPCSENDCOM; // Local to Remote IPC Command Register + Uint32 IPCSENDADDR; // Local to Remote IPC Address Register + Uint32 IPCSENDDATA; // Local to Remote IPC Data Register + Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register + Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register + Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register +}; + +//--------------------------------------------------------------------------- +// IPC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct IPC_REGS_CPU1 IpcRegs; +#endif +#ifdef CPU2 +extern volatile struct IPC_REGS_CPU2 IpcRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h new file mode 100644 index 0000000000..0f94e76030 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: F2837xD_mcbsp.h +// +// TITLE: MCBSP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_MCBSP_H__ +#define __F2837xD_MCBSP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// MCBSP Individual Register Bit Definitions: + +struct DRR2_BITS { // bits description + Uint16 HWLB:8; // 7:0 High word low byte + Uint16 HWHB:8; // 15:8 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +struct DRR1_BITS { // bits description + Uint16 LWLB:8; // 7:0 Low word low byte + Uint16 LWHB:8; // 15:8 Low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +struct DXR2_BITS { // bits description + Uint16 HWLB:8; // 7:0 High word low byte + Uint16 HWHB:8; // 15:8 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +struct DXR1_BITS { // bits description + Uint16 LWLB:8; // 7:0 Low word low byte + Uint16 LWHB:8; // 15:8 Low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +struct SPCR2_BITS { // bits description + Uint16 XRST:1; // 0 Transmitter reset + Uint16 XRDY:1; // 1 Transmitter ready + Uint16 XEMPTY:1; // 2 Transmitter empty + Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag + Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits + Uint16 GRST:1; // 6 Sample rate generator reset + Uint16 FRST:1; // 7 Frame sync logic reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +struct SPCR1_BITS { // bits description + Uint16 RRST:1; // 0 Receiver reset + Uint16 RRDY:1; // 1 Receiver ready + Uint16 RFULL:1; // 2 Receiver full + Uint16 RSYNCERR:1; // 3 Receive sync error INT flag + Uint16 RINTM:2; // 5:4 Receive Interupt mode bits + Uint16 rsvd1:1; // 6 Reserved + Uint16 DXENA:1; // 7 DX delay enable + Uint16 rsvd2:3; // 10:8 Reserved + Uint16 CLKSTP:2; // 12:11 Clock stop mode + Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode + Uint16 DLB:1; // 15 Digital loopback +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +struct RCR2_BITS { // bits description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length 2 + Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +struct RCR1_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length 1 + Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 + Uint16 rsvd2:1; // 15 Reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +struct XCR2_BITS { // bits description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 + Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +struct XCR1_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 + Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 + Uint16 rsvd2:1; // 15 Reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +struct SRGR2_BITS { // bits description + Uint16 FPER:12; // 11:0 Frame-sync period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd1:1; // 14 Reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +struct SRGR1_BITS { // bits description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +struct MCR2_BITS { // bits description + Uint16 XMCM:2; // 1:0 Transmit data delay + Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore + Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects + Uint16 XPBBLK:2; // 8:7 Transmit word length 2 + Uint16 XMCME:1; // 9 Transmit Frame length 2 + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +struct MCR1_BITS { // bits description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd1:1; // 1 Reserved + Uint16 RCBLK:3; // 4:2 eceive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 8:7 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd2:6; // 15:10 Reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +struct PCR_BITS { // bits description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 rsvd3:1; // 6 Reserved + Uint16 SCLKME:1; // 7 Sample clock mode selection + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmit Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 Enable for Receive Interrupt + Uint16 rsvd1:1; // 1 Reserved + Uint16 RINT:1; // 2 Enable for transmit Interrupt + Uint16 rsvd2:13; // 15:3 Reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +struct McBSP_REGS { + union DRR2_REG DRR2; // Data receive register bits 31-16 + union DRR1_REG DRR1; // Data receive register bits 15-0 + union DXR2_REG DXR2; // Data transmit register bits 31-16 + union DXR1_REG DXR1; // Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // Control register 2 + union SPCR1_REG SPCR1; // Control register 1 + union RCR2_REG RCR2; // Receive Control register 2 + union RCR1_REG RCR1; // Receive Control register 1 + union XCR2_REG XCR2; // Transmit Control register 2 + union XCR1_REG XCR1; // Transmit Control register 1 + union SRGR2_REG SRGR2; // Sample rate generator register 2 + union SRGR1_REG SRGR1; // Sample rate generator register 1 + union MCR2_REG MCR2; // Multi-channel register 2 + union MCR1_REG MCR1; // Multi-channel register 1 + Uint16 RCERA; // Receive channel enable partition A + Uint16 RCERB; // Receive channel enable partition B + Uint16 XCERA; // Transmit channel enable partition A + Uint16 XCERB; // Transmit channel enable partition B + union PCR_REG PCR; // Pin Control register + Uint16 RCERC; // Receive channel enable partition C + Uint16 RCERD; // Receive channel enable partition D + Uint16 XCERC; // Transmit channel enable partition C + Uint16 XCERD; // Transmit channel enable partition D + Uint16 RCERE; // Receive channel enable partition E + Uint16 RCERF; // Receive channel enable partition F + Uint16 XCERE; // Transmit channel enable partition E + Uint16 XCERF; // Transmit channel enable partition F + Uint16 RCERG; // Receive channel enable partition G + Uint16 RCERH; // Receive channel enable partition H + Uint16 XCERG; // Transmit channel enable partition G + Uint16 XCERH; // Transmit channel enable partition H + Uint16 rsvd1[4]; // Reserved + union MFFINT_REG MFFINT; // Interrupt enable +}; + +//--------------------------------------------------------------------------- +// MCBSP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct McBSP_REGS McbspaRegs; +extern volatile struct McBSP_REGS McbspbRegs; +#endif +#ifdef CPU2 +extern volatile struct McBSP_REGS McbspaRegs; +extern volatile struct McBSP_REGS McbspbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h new file mode 100644 index 0000000000..9dcf877d3c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h @@ -0,0 +1,1071 @@ +//########################################################################### +// +// FILE: F2837xD_memconfig.h +// +// TITLE: MEMCONFIG Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_MEMCONFIG_H__ +#define __F2837xD_MEMCONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// MEMCONFIG Individual Register Bit Definitions: + +struct DxLOCK_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 LOCK_D0:1; // 2 D0 RAM access protection and master select fields lock bit + Uint16 LOCK_D1:1; // 3 D1 RAM access protection and master select fields lock bit + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DxLOCK_REG { + Uint32 all; + struct DxLOCK_BITS bit; +}; + +struct DxCOMMIT_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 COMMIT_D0:1; // 2 D0 RAM access protection and master select permanent lock + Uint16 COMMIT_D1:1; // 3 D1 RAM access protection and master select permanent lock + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DxCOMMIT_REG { + Uint32 all; + struct DxCOMMIT_BITS bit; +}; + +struct DxACCPROT0_BITS { // bits description + Uint16 rsvd1:16; // 15:0 Reserved + Uint16 FETCHPROT_D0:1; // 16 Fetch Protection For D0 RAM + Uint16 CPUWRPROT_D0:1; // 17 CPU WR Protection For D0 RAM + Uint16 rsvd2:6; // 23:18 Reserved + Uint16 FETCHPROT_D1:1; // 24 Fetch Protection For D1 RAM + Uint16 CPUWRPROT_D1:1; // 25 CPU WR Protection For D1 RAM + Uint16 rsvd3:6; // 31:26 Reserved +}; + +union DxACCPROT0_REG { + Uint32 all; + struct DxACCPROT0_BITS bit; +}; + +struct DxTEST_BITS { // bits description + Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM + Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM + Uint16 TEST_D0:2; // 5:4 Selects the different modes for D0 RAM + Uint16 TEST_D1:2; // 7:6 Selects the different modes for D1 RAM + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxTEST_REG { + Uint32 all; + struct DxTEST_BITS bit; +}; + +struct DxINIT_BITS { // bits description + Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. + Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. + Uint16 INIT_D0:1; // 2 RAM Initialization control for D0 RAM. + Uint16 INIT_D1:1; // 3 RAM Initialization control for D1 RAM. + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxINIT_REG { + Uint32 all; + struct DxINIT_BITS bit; +}; + +struct DxINITDONE_BITS { // bits description + Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. + Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. + Uint16 INITDONE_D0:1; // 2 RAM Initialization status for D0 RAM. + Uint16 INITDONE_D1:1; // 3 RAM Initialization status for D1 RAM. + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxINITDONE_REG { + Uint32 all; + struct DxINITDONE_BITS bit; +}; + +struct LSxLOCK_BITS { // bits description + Uint16 LOCK_LS0:1; // 0 LS0 RAM access protection and master select fields lock bit + Uint16 LOCK_LS1:1; // 1 LS1 RAM access protection and master select fields lock bit + Uint16 LOCK_LS2:1; // 2 LS2 RAM access protection and master select fields lock bit + Uint16 LOCK_LS3:1; // 3 LS3 RAM access protection and master select fields lock bit + Uint16 LOCK_LS4:1; // 4 LS4 RAM access protection and master select fields lock bit + Uint16 LOCK_LS5:1; // 5 LS5 RAM access protection and master select fields lock bit + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxLOCK_REG { + Uint32 all; + struct LSxLOCK_BITS bit; +}; + +struct LSxCOMMIT_BITS { // bits description + Uint16 COMMIT_LS0:1; // 0 LS0 RAM access protection and master select permanent lock + Uint16 COMMIT_LS1:1; // 1 LS1 RAM access protection and master select permanent lock + Uint16 COMMIT_LS2:1; // 2 LS2 RAM access protection and master select permanent lock + Uint16 COMMIT_LS3:1; // 3 LS3 RAM access protection and master select permanent lock + Uint16 COMMIT_LS4:1; // 4 LS4 RAM access protection and master select permanent lock + Uint16 COMMIT_LS5:1; // 5 LS5 RAM access protection and master select permanent lock + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxCOMMIT_REG { + Uint32 all; + struct LSxCOMMIT_BITS bit; +}; + +struct LSxMSEL_BITS { // bits description + Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM + Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM + Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM + Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM + Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM + Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxMSEL_REG { + Uint32 all; + struct LSxMSEL_BITS bit; +}; + +struct LSxCLAPGM_BITS { // bits description + Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxCLAPGM_REG { + Uint32 all; + struct LSxCLAPGM_BITS bit; +}; + +struct LSxACCPROT0_BITS { // bits description + Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM + Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM + Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM + Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM + Uint16 rsvd3:6; // 23:18 Reserved + Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM + Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM + Uint16 rsvd4:6; // 31:26 Reserved +}; + +union LSxACCPROT0_REG { + Uint32 all; + struct LSxACCPROT0_BITS bit; +}; + +struct LSxACCPROT1_BITS { // bits description + Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM + Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM + Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union LSxACCPROT1_REG { + Uint32 all; + struct LSxACCPROT1_BITS bit; +}; + +struct LSxTEST_BITS { // bits description + Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM + Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM + Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM + Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM + Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM + Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxTEST_REG { + Uint32 all; + struct LSxTEST_BITS bit; +}; + +struct LSxINIT_BITS { // bits description + Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. + Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. + Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. + Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. + Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. + Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxINIT_REG { + Uint32 all; + struct LSxINIT_BITS bit; +}; + +struct LSxINITDONE_BITS { // bits description + Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. + Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. + Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. + Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. + Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. + Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxINITDONE_REG { + Uint32 all; + struct LSxINITDONE_BITS bit; +}; + +struct GSxLOCK_BITS { // bits description + Uint16 LOCK_GS0:1; // 0 GS0 RAM access protection and master select fields lock bit + Uint16 LOCK_GS1:1; // 1 GS1 RAM access protection and master select fields lock bit + Uint16 LOCK_GS2:1; // 2 GS2 RAM access protection and master select fields lock bit + Uint16 LOCK_GS3:1; // 3 GS3 RAM access protection and master select fields lock bit + Uint16 LOCK_GS4:1; // 4 GS4 RAM access protection and master select fields lock bit + Uint16 LOCK_GS5:1; // 5 GS5 RAM access protection and master select fields lock bit + Uint16 LOCK_GS6:1; // 6 GS6 RAM access protection and master select fields lock bit + Uint16 LOCK_GS7:1; // 7 GS7 RAM access protection and master select fields lock bit + Uint16 LOCK_GS8:1; // 8 GS8 RAM access protection and master select fields lock bit + Uint16 LOCK_GS9:1; // 9 GS9 RAM access protection and master select fields lock bit + Uint16 LOCK_GS10:1; // 10 GS10 RAM access protection and master select fields lock bit + Uint16 LOCK_GS11:1; // 11 GS11 RAM access protection and master select fields lock bit + Uint16 LOCK_GS12:1; // 12 GS12 RAM access protection and master select fields lock bit + Uint16 LOCK_GS13:1; // 13 GS13 RAM access protection and master select fields lock bit + Uint16 LOCK_GS14:1; // 14 GS14 RAM access protection and master select fields lock bit + Uint16 LOCK_GS15:1; // 15 GS15 RAM access protection and master select fields lock bit + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxLOCK_REG { + Uint32 all; + struct GSxLOCK_BITS bit; +}; + +struct GSxCOMMIT_BITS { // bits description + Uint16 COMMIT_GS0:1; // 0 GS0 RAM access protection and master select permanent lock + Uint16 COMMIT_GS1:1; // 1 GS1 RAM access protection and master select permanent lock + Uint16 COMMIT_GS2:1; // 2 GS2 RAM access protection and master select permanent lock + Uint16 COMMIT_GS3:1; // 3 GS3 RAM access protection and master select permanent lock + Uint16 COMMIT_GS4:1; // 4 GS4 RAM access protection and master select permanent lock + Uint16 COMMIT_GS5:1; // 5 GS5 RAM access protection and master select permanent lock + Uint16 COMMIT_GS6:1; // 6 GS6 RAM access protection and master select permanent lock + Uint16 COMMIT_GS7:1; // 7 GS7 RAM access protection and master select permanent lock + Uint16 COMMIT_GS8:1; // 8 GS8 RAM access protection and master select permanent lock + Uint16 COMMIT_GS9:1; // 9 GS9 RAM access protection and master select permanent lock + Uint16 COMMIT_GS10:1; // 10 GS10 RAM access protection and master select permanent lock + Uint16 COMMIT_GS11:1; // 11 GS11 RAM access protection and master select permanent lock + Uint16 COMMIT_GS12:1; // 12 GS12 RAM access protection and master select permanent lock + Uint16 COMMIT_GS13:1; // 13 GS13 RAM access protection and master select permanent lock + Uint16 COMMIT_GS14:1; // 14 GS14 RAM access protection and master select permanent lock + Uint16 COMMIT_GS15:1; // 15 GS15 RAM access protection and master select permanent lock + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxCOMMIT_REG { + Uint32 all; + struct GSxCOMMIT_BITS bit; +}; + +struct GSxMSEL_BITS { // bits description + Uint16 MSEL_GS0:1; // 0 Master Select for GS0 RAM + Uint16 MSEL_GS1:1; // 1 Master Select for GS1 RAM + Uint16 MSEL_GS2:1; // 2 Master Select for GS2 RAM + Uint16 MSEL_GS3:1; // 3 Master Select for GS3 RAM + Uint16 MSEL_GS4:1; // 4 Master Select for GS4 RAM + Uint16 MSEL_GS5:1; // 5 Master Select for GS5 RAM + Uint16 MSEL_GS6:1; // 6 Master Select for GS6 RAM + Uint16 MSEL_GS7:1; // 7 Master Select for GS7 RAM + Uint16 MSEL_GS8:1; // 8 Master Select for GS8 RAM + Uint16 MSEL_GS9:1; // 9 Master Select for GS9 RAM + Uint16 MSEL_GS10:1; // 10 Master Select for GS10 RAM + Uint16 MSEL_GS11:1; // 11 Master Select for GS11 RAM + Uint16 MSEL_GS12:1; // 12 Master Select for GS12 RAM + Uint16 MSEL_GS13:1; // 13 Master Select for GS13 RAM + Uint16 MSEL_GS14:1; // 14 Master Select for GS14 RAM + Uint16 MSEL_GS15:1; // 15 Master Select for GS15 RAM + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxMSEL_REG { + Uint32 all; + struct GSxMSEL_BITS bit; +}; + +struct GSxACCPROT0_BITS { // bits description + Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM + Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM + Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM + Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM + Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM + Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM + Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM + Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM + Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT0_REG { + Uint32 all; + struct GSxACCPROT0_BITS bit; +}; + +struct GSxACCPROT1_BITS { // bits description + Uint16 FETCHPROT_GS4:1; // 0 Fetch Protection For GS4 RAM + Uint16 CPUWRPROT_GS4:1; // 1 CPU WR Protection For GS4 RAM + Uint16 DMAWRPROT_GS4:1; // 2 DMA WR Protection For GS4 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS5:1; // 8 Fetch Protection For GS5 RAM + Uint16 CPUWRPROT_GS5:1; // 9 CPU WR Protection For GS5 RAM + Uint16 DMAWRPROT_GS5:1; // 10 DMA WR Protection For GS5RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS6:1; // 16 Fetch Protection For GS6 RAM + Uint16 CPUWRPROT_GS6:1; // 17 CPU WR Protection For GS6 RAM + Uint16 DMAWRPROT_GS6:1; // 18 DMA WR Protection For GS6RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS7:1; // 24 Fetch Protection For GS7 RAM + Uint16 CPUWRPROT_GS7:1; // 25 CPU WR Protection For GS7 RAM + Uint16 DMAWRPROT_GS7:1; // 26 DMA WR Protection For GS7RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT1_REG { + Uint32 all; + struct GSxACCPROT1_BITS bit; +}; + +struct GSxACCPROT2_BITS { // bits description + Uint16 FETCHPROT_GS8:1; // 0 Fetch Protection For GS8 RAM + Uint16 CPUWRPROT_GS8:1; // 1 CPU WR Protection For GS8 RAM + Uint16 DMAWRPROT_GS8:1; // 2 DMA WR Protection For GS8 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS9:1; // 8 Fetch Protection For GS9 RAM + Uint16 CPUWRPROT_GS9:1; // 9 CPU WR Protection For GS9 RAM + Uint16 DMAWRPROT_GS9:1; // 10 DMA WR Protection For GS9RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS10:1; // 16 Fetch Protection For GS10 RAM + Uint16 CPUWRPROT_GS10:1; // 17 CPU WR Protection For GS10 RAM + Uint16 DMAWRPROT_GS10:1; // 18 DMA WR Protection For GS10RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS11:1; // 24 Fetch Protection For GS11 RAM + Uint16 CPUWRPROT_GS11:1; // 25 CPU WR Protection For GS11 RAM + Uint16 DMAWRPROT_GS11:1; // 26 DMA WR Protection For GS11RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT2_REG { + Uint32 all; + struct GSxACCPROT2_BITS bit; +}; + +struct GSxACCPROT3_BITS { // bits description + Uint16 FETCHPROT_GS12:1; // 0 Fetch Protection For GS12 RAM + Uint16 CPUWRPROT_GS12:1; // 1 CPU WR Protection For GS12 RAM + Uint16 DMAWRPROT_GS12:1; // 2 DMA WR Protection For GS12 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS13:1; // 8 Fetch Protection For GS13 RAM + Uint16 CPUWRPROT_GS13:1; // 9 CPU WR Protection For GS13 RAM + Uint16 DMAWRPROT_GS13:1; // 10 DMA WR Protection For GS13RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS14:1; // 16 Fetch Protection For GS14 RAM + Uint16 CPUWRPROT_GS14:1; // 17 CPU WR Protection For GS14 RAM + Uint16 DMAWRPROT_GS14:1; // 18 DMA WR Protection For GS14RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS15:1; // 24 Fetch Protection For GS15 RAM + Uint16 CPUWRPROT_GS15:1; // 25 CPU WR Protection For GS15 RAM + Uint16 DMAWRPROT_GS15:1; // 26 DMA WR Protection For GS15RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT3_REG { + Uint32 all; + struct GSxACCPROT3_BITS bit; +}; + +struct GSxTEST_BITS { // bits description + Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM + Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM + Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM + Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM + Uint16 TEST_GS4:2; // 9:8 Selects the different modes for GS4 RAM + Uint16 TEST_GS5:2; // 11:10 Selects the different modes for GS5 RAM + Uint16 TEST_GS6:2; // 13:12 Selects the different modes for GS6 RAM + Uint16 TEST_GS7:2; // 15:14 Selects the different modes for GS7 RAM + Uint16 TEST_GS8:2; // 17:16 Selects the different modes for GS8 RAM + Uint16 TEST_GS9:2; // 19:18 Selects the different modes for GS9 RAM + Uint16 TEST_GS10:2; // 21:20 Selects the different modes for GS10 RAM + Uint16 TEST_GS11:2; // 23:22 Selects the different modes for GS11 RAM + Uint16 TEST_GS12:2; // 25:24 Selects the different modes for GS12 RAM + Uint16 TEST_GS13:2; // 27:26 Selects the different modes for GS13 RAM + Uint16 TEST_GS14:2; // 29:28 Selects the different modes for GS14 RAM + Uint16 TEST_GS15:2; // 31:30 Selects the different modes for GS15 RAM +}; + +union GSxTEST_REG { + Uint32 all; + struct GSxTEST_BITS bit; +}; + +struct GSxINIT_BITS { // bits description + Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. + Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. + Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. + Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. + Uint16 INIT_GS4:1; // 4 RAM Initialization control for GS4 RAM. + Uint16 INIT_GS5:1; // 5 RAM Initialization control for GS5 RAM. + Uint16 INIT_GS6:1; // 6 RAM Initialization control for GS6 RAM. + Uint16 INIT_GS7:1; // 7 RAM Initialization control for GS7 RAM. + Uint16 INIT_GS8:1; // 8 RAM Initialization control for GS8 RAM. + Uint16 INIT_GS9:1; // 9 RAM Initialization control for GS9 RAM. + Uint16 INIT_GS10:1; // 10 RAM Initialization control for GS10 RAM. + Uint16 INIT_GS11:1; // 11 RAM Initialization control for GS11 RAM. + Uint16 INIT_GS12:1; // 12 RAM Initialization control for GS12 RAM. + Uint16 INIT_GS13:1; // 13 RAM Initialization control for GS13 RAM. + Uint16 INIT_GS14:1; // 14 RAM Initialization control for GS14 RAM. + Uint16 INIT_GS15:1; // 15 RAM Initialization control for GS15 RAM. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxINIT_REG { + Uint32 all; + struct GSxINIT_BITS bit; +}; + +struct GSxINITDONE_BITS { // bits description + Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. + Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. + Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. + Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. + Uint16 INITDONE_GS4:1; // 4 RAM Initialization status for GS4 RAM. + Uint16 INITDONE_GS5:1; // 5 RAM Initialization status for GS5 RAM. + Uint16 INITDONE_GS6:1; // 6 RAM Initialization status for GS6 RAM. + Uint16 INITDONE_GS7:1; // 7 RAM Initialization status for GS7 RAM. + Uint16 INITDONE_GS8:1; // 8 RAM Initialization status for GS8 RAM. + Uint16 INITDONE_GS9:1; // 9 RAM Initialization status for GS9 RAM. + Uint16 INITDONE_GS10:1; // 10 RAM Initialization status for GS10 RAM. + Uint16 INITDONE_GS11:1; // 11 RAM Initialization status for GS11 RAM. + Uint16 INITDONE_GS12:1; // 12 RAM Initialization status for GS12 RAM. + Uint16 INITDONE_GS13:1; // 13 RAM Initialization status for GS13 RAM. + Uint16 INITDONE_GS14:1; // 14 RAM Initialization status for GS14 RAM. + Uint16 INITDONE_GS15:1; // 15 RAM Initialization status for GS15 RAM. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxINITDONE_REG { + Uint32 all; + struct GSxINITDONE_BITS bit; +}; + +struct MSGxTEST_BITS { // bits description + Uint16 TEST_CPUTOCPU:2; // 1:0 CPU to CPU Mode Select + Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select + Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 rsvd2:2; // 9:8 Reserved + Uint16 rsvd3:6; // 15:10 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxTEST_REG { + Uint32 all; + struct MSGxTEST_BITS bit; +}; + +struct MSGxINIT_BITS { // bits description + Uint16 INIT_CPUTOCPU:1; // 0 Initialization control for CPU to CPU MSG RAM + Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM + Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:1; // 4 Reserved + Uint16 rsvd3:11; // 15:5 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxINIT_REG { + Uint32 all; + struct MSGxINIT_BITS bit; +}; + +struct MSGxINITDONE_BITS { // bits description + Uint16 INITDONE_CPUTOCPU:1; // 0 Initialization status for CPU to CPU MSG RAM + Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM + Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:1; // 4 Reserved + Uint16 rsvd3:11; // 15:5 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxINITDONE_REG { + Uint32 all; + struct MSGxINITDONE_BITS bit; +}; + +struct MEM_CFG_REGS { + union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register + union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register + Uint16 rsvd1[4]; // Reserved + union DxACCPROT0_REG DxACCPROT0; // Dedicated RAM Config Register + Uint16 rsvd2[6]; // Reserved + union DxTEST_REG DxTEST; // Dedicated RAM TEST Register + union DxINIT_REG DxINIT; // Dedicated RAM Init Register + union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register + Uint16 rsvd3[10]; // Reserved + union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register + union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register + union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register + union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register + union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 + union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 + Uint16 rsvd4[4]; // Reserved + union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register + union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register + union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register + Uint16 rsvd5[10]; // Reserved + union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register + union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register + union GSxMSEL_REG GSxMSEL; // Global Shared RAM Master Sel Register + Uint16 rsvd6[2]; // Reserved + union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 + union GSxACCPROT1_REG GSxACCPROT1; // Global Shared RAM Config Register 1 + union GSxACCPROT2_REG GSxACCPROT2; // Global Shared RAM Config Register 2 + union GSxACCPROT3_REG GSxACCPROT3; // Global Shared RAM Config Register 3 + union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register + union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register + union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register + Uint16 rsvd7[26]; // Reserved + union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register + union MSGxINIT_REG MSGxINIT; // Message RAM Init Register + union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register + Uint16 rsvd8[10]; // Reserved +}; + +struct EMIF1LOCK_BITS { // bits description + Uint16 LOCK_EMIF1:1; // 0 EMIF1 access protection and master select fields lock bit + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1LOCK_REG { + Uint32 all; + struct EMIF1LOCK_BITS bit; +}; + +struct EMIF1COMMIT_BITS { // bits description + Uint16 COMMIT_EMIF1:1; // 0 EMIF1 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1COMMIT_REG { + Uint32 all; + struct EMIF1COMMIT_BITS bit; +}; + +struct EMIF1MSEL_BITS { // bits description + Uint16 MSEL_EMIF1:2; // 1:0 Master Select for EMIF1. + Uint16 rsvd1:2; // 3:2 Reserved + Uint32 KEY:28; // 31:4 KEY to enable the write into MSEL_EMIF1 bits +}; + +union EMIF1MSEL_REG { + Uint32 all; + struct EMIF1MSEL_BITS bit; +}; + +struct EMIF1ACCPROT0_BITS { // bits description + Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF1 + Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF1 + Uint16 DMAWRPROT_EMIF1:1; // 2 DMA WR Protection For EMIF1 + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1ACCPROT0_REG { + Uint32 all; + struct EMIF1ACCPROT0_BITS bit; +}; + +struct EMIF1_CONFIG_REGS { + union EMIF1LOCK_REG EMIF1LOCK; // EMIF1 Config Lock Register + union EMIF1COMMIT_REG EMIF1COMMIT; // EMIF1 Config Lock Commit Register + union EMIF1MSEL_REG EMIF1MSEL; // EMIF1 Master Sel Register + Uint16 rsvd1[2]; // Reserved + union EMIF1ACCPROT0_REG EMIF1ACCPROT0; // EMIF1 Config Register 0 + Uint16 rsvd2[22]; // Reserved +}; + +struct EMIF2LOCK_BITS { // bits description + Uint16 LOCK_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2LOCK_REG { + Uint32 all; + struct EMIF2LOCK_BITS bit; +}; + +struct EMIF2COMMIT_BITS { // bits description + Uint16 COMMIT_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2COMMIT_REG { + Uint32 all; + struct EMIF2COMMIT_BITS bit; +}; + +struct EMIF2ACCPROT0_BITS { // bits description + Uint16 FETCHPROT_EMIF2:1; // 0 Fetch Protection For EMIF2 + Uint16 CPUWRPROT_EMIF2:1; // 1 CPU WR Protection For EMIF2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2ACCPROT0_REG { + Uint32 all; + struct EMIF2ACCPROT0_BITS bit; +}; + +struct EMIF2_CONFIG_REGS { + union EMIF2LOCK_REG EMIF2LOCK; // EMIF2 Config Lock Register + union EMIF2COMMIT_REG EMIF2COMMIT; // EMIF2 Config Lock Commit Register + Uint16 rsvd1[4]; // Reserved + union EMIF2ACCPROT0_REG EMIF2ACCPROT0; // EMIF2 Config Register 0 + Uint16 rsvd2[22]; // Reserved +}; + +struct NMAVFLG_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVFLG_REG { + Uint32 all; + struct NMAVFLG_BITS bit; +}; + +struct NMAVSET_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVSET_REG { + Uint32 all; + struct NMAVSET_BITS bit; +}; + +struct NMAVCLR_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVCLR_REG { + Uint32 all; + struct NMAVCLR_BITS bit; +}; + +struct NMAVINTEN_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Interrupt Enable + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVINTEN_REG { + Uint32 all; + struct NMAVINTEN_BITS bit; +}; + +struct MAVFLG_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVFLG_REG { + Uint32 all; + struct MAVFLG_BITS bit; +}; + +struct MAVSET_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVSET_REG { + Uint32 all; + struct MAVSET_BITS bit; +}; + +struct MAVCLR_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVCLR_REG { + Uint32 all; + struct MAVCLR_BITS bit; +}; + +struct MAVINTEN_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVINTEN_REG { + Uint32 all; + struct MAVINTEN_BITS bit; +}; + +struct ACCESS_PROTECTION_REGS { + union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register + union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register + union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register + union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register + Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address + Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address + Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address + Uint32 NMDMAWRAVADDR; // Non-Master DMA Write Access Violation Address + Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address + Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address + Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address + Uint16 rsvd1[10]; // Reserved + union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register + union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register + union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register + union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register + Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address + Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address + Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address + Uint16 rsvd2[18]; // Reserved +}; + +struct UCERRFLG_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRFLG_REG { + Uint32 all; + struct UCERRFLG_BITS bit; +}; + +struct UCERRSET_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRSET_REG { + Uint32 all; + struct UCERRSET_BITS bit; +}; + +struct UCERRCLR_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRCLR_REG { + Uint32 all; + struct UCERRCLR_BITS bit; +}; + +struct CERRFLG_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRFLG_REG { + Uint32 all; + struct CERRFLG_BITS bit; +}; + +struct CERRSET_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRSET_REG { + Uint32 all; + struct CERRSET_BITS bit; +}; + +struct CERRCLR_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRCLR_REG { + Uint32 all; + struct CERRCLR_BITS bit; +}; + +struct CEINTFLG_BITS { // bits description + Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTFLG_REG { + Uint32 all; + struct CEINTFLG_BITS bit; +}; + +struct CEINTCLR_BITS { // bits description + Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTCLR_REG { + Uint32 all; + struct CEINTCLR_BITS bit; +}; + +struct CEINTSET_BITS { // bits description + Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTSET_REG { + Uint32 all; + struct CEINTSET_BITS bit; +}; + +struct CEINTEN_BITS { // bits description + Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTEN_REG { + Uint32 all; + struct CEINTEN_BITS bit; +}; + +struct MEMORY_ERROR_REGS { + union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register + union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register + union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register + Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address + Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address + Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address + Uint16 rsvd1[20]; // Reserved + union CERRFLG_REG CERRFLG; // Correctable Error Flag Register + union CERRSET_REG CERRSET; // Correctable Error Flag Set Register + union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register + Uint32 CCPUREADDR; // Correctable CPU Read Error Address + Uint16 rsvd2[6]; // Reserved + Uint32 CERRCNT; // Correctable Error Count Register + Uint32 CERRTHRES; // Correctable Error Threshold Value Register + union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register + union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register + union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register + union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register + Uint16 rsvd3[6]; // Reserved +}; + +struct ROMWAITSTATE_BITS { // bits description + Uint16 WSDISABLE:1; // 0 ROM Wait State Enable/Disable Control + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ROMWAITSTATE_REG { + Uint32 all; + struct ROMWAITSTATE_BITS bit; +}; + +struct ROM_WAIT_STATE_REGS { + union ROMWAITSTATE_REG ROMWAITSTATE; // ROM Wait State Configuration Register +}; + +struct ROMPREFETCH_BITS { // bits description + Uint16 PFENABLE:1; // 0 ROM Prefetch Enable/Disable Control + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ROMPREFETCH_REG { + Uint32 all; + struct ROMPREFETCH_BITS bit; +}; + +struct ROM_PREFETCH_REGS { + union ROMPREFETCH_REG ROMPREFETCH; // ROM Prefetch Configuration Register +}; + +//--------------------------------------------------------------------------- +// MEMCONFIG External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; +extern volatile struct MEM_CFG_REGS MemCfgRegs; +extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; +extern volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; +extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; +extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif +#ifdef CPU2 +extern volatile struct MEM_CFG_REGS MemCfgRegs; +extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; +extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; +extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h new file mode 100644 index 0000000000..0bbe21fe21 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: F2837xD_nmiintrupt.h +// +// TITLE: NMIINTRUPT Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_NMIINTRUPT_H__ +#define __F2837xD_NMIINTRUPT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// NMIINTRUPT Individual Register Bit Definitions: + +struct NMICFG_BITS { // bits description + Uint16 NMIE:1; // 0 Global NMI Enable + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union NMICFG_REG { + Uint16 all; + struct NMICFG_BITS bit; +}; + +struct NMIFLG_BITS { // bits description + Uint16 NMIINT:1; // 0 NMI Interrupt Flag + Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag + Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag + Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag + Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag + Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag + Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag + Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMIFLG_REG { + Uint16 all; + struct NMIFLG_BITS bit; +}; + +struct NMIFLGCLR_BITS { // bits description + Uint16 NMIINT:1; // 0 NMIINT Flag Clear + Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear + Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear + Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear + Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear + Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear + Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear + Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear + Uint16 OVF:1; // 11 OVF Flag Clear + Uint16 rsvd3:4; // 15:12 Reserved +}; + +union NMIFLGCLR_REG { + Uint16 all; + struct NMIFLGCLR_BITS bit; +}; + +struct NMIFLGFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force + Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force + Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force + Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force + Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force + Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force + Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force + Uint16 OVF:1; // 11 OVF Flag Force + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMIFLGFRC_REG { + Uint16 all; + struct NMIFLGFRC_BITS bit; +}; + +struct NMISHDFLG_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag + Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag + Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag + Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag + Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag + Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag + Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag + Uint16 OVF:1; // 11 Shadow OVF Flag + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMISHDFLG_REG { + Uint16 all; + struct NMISHDFLG_BITS bit; +}; + +struct NMI_INTRUPT_REGS { + union NMICFG_REG NMICFG; // NMI Configuration Register + union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear) + union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register + union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register + Uint16 NMIWDCNT; // NMI Watchdog Counter Register + Uint16 NMIWDPRD; // NMI Watchdog Period Register + union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register +}; + +//--------------------------------------------------------------------------- +// NMIINTRUPT External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; +#endif +#ifdef CPU2 +extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h new file mode 100644 index 0000000000..aad7cada65 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h @@ -0,0 +1,907 @@ +//########################################################################### +// +// FILE: F2837xD_output_xbar.h +// +// TITLE: OUTPUT_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_OUTPUT_XBAR_H__ +#define __F2837xD_OUTPUT_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// OUTPUT_XBAR Individual Register Bit Definitions: + +struct OUTPUT1MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT1MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT1MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT1MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT2MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT2MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT2MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT2MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT3MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT3MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT3MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT3MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT4MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT4MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT4MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT4MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT5MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT5MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT5MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT5MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT6MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT6MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT6MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT6MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT7MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT7MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT7MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT7MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT8MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT8MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT8MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT8MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT1MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUXENABLE_REG { + Uint32 all; + struct OUTPUT1MUXENABLE_BITS bit; +}; + +struct OUTPUT2MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUXENABLE_REG { + Uint32 all; + struct OUTPUT2MUXENABLE_BITS bit; +}; + +struct OUTPUT3MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUXENABLE_REG { + Uint32 all; + struct OUTPUT3MUXENABLE_BITS bit; +}; + +struct OUTPUT4MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUXENABLE_REG { + Uint32 all; + struct OUTPUT4MUXENABLE_BITS bit; +}; + +struct OUTPUT5MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUXENABLE_REG { + Uint32 all; + struct OUTPUT5MUXENABLE_BITS bit; +}; + +struct OUTPUT6MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUXENABLE_REG { + Uint32 all; + struct OUTPUT6MUXENABLE_BITS bit; +}; + +struct OUTPUT7MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUXENABLE_REG { + Uint32 all; + struct OUTPUT7MUXENABLE_BITS bit; +}; + +struct OUTPUT8MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUXENABLE_REG { + Uint32 all; + struct OUTPUT8MUXENABLE_BITS bit; +}; + +struct OUTPUTLATCH_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCH_REG { + Uint32 all; + struct OUTPUTLATCH_BITS bit; +}; + +struct OUTPUTLATCHCLR_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHCLR_REG { + Uint32 all; + struct OUTPUTLATCHCLR_BITS bit; +}; + +struct OUTPUTLATCHFRC_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHFRC_REG { + Uint32 all; + struct OUTPUTLATCHFRC_BITS bit; +}; + +struct OUTPUTLATCHENABLE_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHENABLE_REG { + Uint32 all; + struct OUTPUTLATCHENABLE_BITS bit; +}; + +struct OUTPUTINV_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTINV_REG { + Uint32 all; + struct OUTPUTINV_BITS bit; +}; + +struct OUTPUTLOCK_BITS { // bits description + Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Write Protection KEY +}; + +union OUTPUTLOCK_REG { + Uint32 all; + struct OUTPUTLOCK_BITS bit; +}; + +struct OUTPUT_XBAR_REGS { + union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 + union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 + union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 + union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 + union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 + union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 + union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 + union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 + union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 + union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 + union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 + union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 + union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 + union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 + union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 + union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 + union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 + union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 + union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 + union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 + union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 + union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 + union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 + union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 + union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch + union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear + union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear + union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable + union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion + Uint16 rsvd1[4]; // Reserved + union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register +}; + +//--------------------------------------------------------------------------- +// OUTPUT_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h new file mode 100644 index 0000000000..75f9303244 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h @@ -0,0 +1,707 @@ +//########################################################################### +// +// FILE: F2837xD_piectrl.h +// +// TITLE: PIECTRL Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_PIECTRL_H__ +#define __F2837xD_PIECTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// PIECTRL Individual Register Bit Definitions: + +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 PIE Enable + Uint16 PIEVECT:15; // 15:1 PIE Vector Address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +struct PIEIER1_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 +}; + +union PIEIER1_REG { + Uint16 all; + struct PIEIER1_BITS bit; +}; + +struct PIEIFR1_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 +}; + +union PIEIFR1_REG { + Uint16 all; + struct PIEIFR1_BITS bit; +}; + +struct PIEIER2_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 +}; + +union PIEIER2_REG { + Uint16 all; + struct PIEIER2_BITS bit; +}; + +struct PIEIFR2_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 +}; + +union PIEIFR2_REG { + Uint16 all; + struct PIEIFR2_BITS bit; +}; + +struct PIEIER3_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 +}; + +union PIEIER3_REG { + Uint16 all; + struct PIEIER3_BITS bit; +}; + +struct PIEIFR3_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 +}; + +union PIEIFR3_REG { + Uint16 all; + struct PIEIFR3_BITS bit; +}; + +struct PIEIER4_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 +}; + +union PIEIER4_REG { + Uint16 all; + struct PIEIER4_BITS bit; +}; + +struct PIEIFR4_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 +}; + +union PIEIFR4_REG { + Uint16 all; + struct PIEIFR4_BITS bit; +}; + +struct PIEIER5_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 +}; + +union PIEIER5_REG { + Uint16 all; + struct PIEIER5_BITS bit; +}; + +struct PIEIFR5_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 +}; + +union PIEIFR5_REG { + Uint16 all; + struct PIEIFR5_BITS bit; +}; + +struct PIEIER6_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 +}; + +union PIEIER6_REG { + Uint16 all; + struct PIEIER6_BITS bit; +}; + +struct PIEIFR6_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 +}; + +union PIEIFR6_REG { + Uint16 all; + struct PIEIFR6_BITS bit; +}; + +struct PIEIER7_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 +}; + +union PIEIER7_REG { + Uint16 all; + struct PIEIER7_BITS bit; +}; + +struct PIEIFR7_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 +}; + +union PIEIFR7_REG { + Uint16 all; + struct PIEIFR7_BITS bit; +}; + +struct PIEIER8_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 +}; + +union PIEIER8_REG { + Uint16 all; + struct PIEIER8_BITS bit; +}; + +struct PIEIFR8_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 +}; + +union PIEIFR8_REG { + Uint16 all; + struct PIEIFR8_BITS bit; +}; + +struct PIEIER9_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 +}; + +union PIEIER9_REG { + Uint16 all; + struct PIEIER9_BITS bit; +}; + +struct PIEIFR9_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 +}; + +union PIEIFR9_REG { + Uint16 all; + struct PIEIFR9_BITS bit; +}; + +struct PIEIER10_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 +}; + +union PIEIER10_REG { + Uint16 all; + struct PIEIER10_BITS bit; +}; + +struct PIEIFR10_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 +}; + +union PIEIFR10_REG { + Uint16 all; + struct PIEIFR10_BITS bit; +}; + +struct PIEIER11_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 +}; + +union PIEIER11_REG { + Uint16 all; + struct PIEIER11_BITS bit; +}; + +struct PIEIFR11_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 +}; + +union PIEIFR11_REG { + Uint16 all; + struct PIEIFR11_BITS bit; +}; + +struct PIEIER12_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 +}; + +union PIEIER12_REG { + Uint16 all; + struct PIEIER12_BITS bit; +}; + +struct PIEIFR12_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 +}; + +union PIEIFR12_REG { + Uint16 all; + struct PIEIFR12_BITS bit; +}; + +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // ePIE Control Register + union PIEACK_REG PIEACK; // Interrupt Acknowledge Register + union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register + union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register + union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register + union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register + union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register + union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register + union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register + union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register + union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register + union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register + union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register + union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register + union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register + union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register + union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register + union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register + union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register + union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register + union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register + union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register + union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register + union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register + union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register + union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register +}; + +//--------------------------------------------------------------------------- +// PIECTRL External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; +#endif +#ifdef CPU2 +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h new file mode 100644 index 0000000000..7772256c78 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: F2837xD_pievect.h +// +// TITLE: F2837xD Device PIE Vector Table Definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_PIE_VECT_H +#define F2837xD_PIE_VECT_H +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table Definition: +// Create a user type called PINT (pointer to interrupt): + +typedef __interrupt void (*PINT)(void); + +// Define Vector Table: +struct PIE_VECT_TABLE { + PINT PIE1_RESERVED_INT; // Reserved + PINT PIE2_RESERVED_INT; // Reserved + PINT PIE3_RESERVED_INT; // Reserved + PINT PIE4_RESERVED_INT; // Reserved + PINT PIE5_RESERVED_INT; // Reserved + PINT PIE6_RESERVED_INT; // Reserved + PINT PIE7_RESERVED_INT; // Reserved + PINT PIE8_RESERVED_INT; // Reserved + PINT PIE9_RESERVED_INT; // Reserved + PINT PIE10_RESERVED_INT; // Reserved + PINT PIE11_RESERVED_INT; // Reserved + PINT PIE12_RESERVED_INT; // Reserved + PINT PIE13_RESERVED_INT; // Reserved + PINT TIMER1_INT; // CPU Timer 1 Interrupt + PINT TIMER2_INT; // CPU Timer 2 Interrupt + PINT DATALOG_INT; // Datalogging Interrupt + PINT RTOS_INT; // RTOS Interrupt + PINT EMU_INT; // Emulation Interrupt + PINT NMI_INT; // Non-Maskable Interrupt + PINT ILLEGAL_INT; // Illegal Operation Trap + PINT USER1_INT; // User Defined Trap 1 + PINT USER2_INT; // User Defined Trap 2 + PINT USER3_INT; // User Defined Trap 3 + PINT USER4_INT; // User Defined Trap 4 + PINT USER5_INT; // User Defined Trap 5 + PINT USER6_INT; // User Defined Trap 6 + PINT USER7_INT; // User Defined Trap 7 + PINT USER8_INT; // User Defined Trap 8 + PINT USER9_INT; // User Defined Trap 9 + PINT USER10_INT; // User Defined Trap 10 + PINT USER11_INT; // User Defined Trap 11 + PINT USER12_INT; // User Defined Trap 12 + PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 + PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 + PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 + PINT XINT1_INT; // 1.4 - XINT1 Interrupt + PINT XINT2_INT; // 1.5 - XINT2 Interrupt + PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 + PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt + PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt + PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt + PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt + PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt + PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt + PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt + PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt + PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt + PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt + PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt + PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt + PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt + PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt + PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt + PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt + PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt + PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt + PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt + PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt + PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt + PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt + PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt + PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt + PINT PIE14_RESERVED_INT; // 4.7 - Reserved + PINT PIE15_RESERVED_INT; // 4.8 - Reserved + PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt + PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt + PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt + PINT PIE16_RESERVED_INT; // 5.4 - Reserved + PINT PIE17_RESERVED_INT; // 5.5 - Reserved + PINT PIE18_RESERVED_INT; // 5.6 - Reserved + PINT PIE19_RESERVED_INT; // 5.7 - Reserved + PINT PIE20_RESERVED_INT; // 5.8 - Reserved + PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt + PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt + PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt + PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt + PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt + PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt + PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt + PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt + PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt + PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt + PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt + PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt + PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt + PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt + PINT PIE21_RESERVED_INT; // 7.7 - Reserved + PINT PIE22_RESERVED_INT; // 7.8 - Reserved + PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 + PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 + PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 + PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 + PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt + PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt + PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt + PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt + PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt + PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt + PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt + PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt + PINT CANA0_INT; // 9.5 - CANA Interrupt 0 + PINT CANA1_INT; // 9.6 - CANA Interrupt 1 + PINT CANB0_INT; // 9.7 - CANB Interrupt 0 + PINT CANB1_INT; // 9.8 - CANB Interrupt 1 + PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt + PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 + PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 + PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 + PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt + PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 + PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 + PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 + PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 + PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 + PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 + PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 + PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 + PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 + PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 + PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 + PINT XINT3_INT; // 12.1 - XINT3 Interrupt + PINT XINT4_INT; // 12.2 - XINT4 Interrupt + PINT XINT5_INT; // 12.3 - XINT5 Interrupt + PINT PIE23_RESERVED_INT; // 12.4 - Reserved + PINT PIE24_RESERVED_INT; // 12.5 - Reserved + PINT VCU_INT; // 12.6 - VCU Interrupt + PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt + PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt + PINT PIE25_RESERVED_INT; // 1.9 - Reserved + PINT PIE26_RESERVED_INT; // 1.10 - Reserved + PINT PIE27_RESERVED_INT; // 1.11 - Reserved + PINT PIE28_RESERVED_INT; // 1.12 - Reserved + PINT IPC0_INT; // 1.13 - IPC Interrupt 0 + PINT IPC1_INT; // 1.14 - IPC Interrupt 1 + PINT IPC2_INT; // 1.15 - IPC Interrupt 2 + PINT IPC3_INT; // 1.16 - IPC Interrupt 3 + PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt + PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt + PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt + PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt + PINT PIE29_RESERVED_INT; // 2.13 - Reserved + PINT PIE30_RESERVED_INT; // 2.14 - Reserved + PINT PIE31_RESERVED_INT; // 2.15 - Reserved + PINT PIE32_RESERVED_INT; // 2.16 - Reserved + PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt + PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt + PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt + PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt + PINT PIE33_RESERVED_INT; // 3.13 - Reserved + PINT PIE34_RESERVED_INT; // 3.14 - Reserved + PINT PIE35_RESERVED_INT; // 3.15 - Reserved + PINT PIE36_RESERVED_INT; // 3.16 - Reserved + PINT PIE37_RESERVED_INT; // 4.9 - Reserved + PINT PIE38_RESERVED_INT; // 4.10 - Reserved + PINT PIE39_RESERVED_INT; // 4.11 - Reserved + PINT PIE40_RESERVED_INT; // 4.12 - Reserved + PINT PIE41_RESERVED_INT; // 4.13 - Reserved + PINT PIE42_RESERVED_INT; // 4.14 - Reserved + PINT PIE43_RESERVED_INT; // 4.15 - Reserved + PINT PIE44_RESERVED_INT; // 4.16 - Reserved + PINT SD1_INT; // 5.9 - SD1 Interrupt + PINT SD2_INT; // 5.10 - SD2 Interrupt + PINT PIE45_RESERVED_INT; // 5.11 - Reserved + PINT PIE46_RESERVED_INT; // 5.12 - Reserved + PINT PIE47_RESERVED_INT; // 5.13 - Reserved + PINT PIE48_RESERVED_INT; // 5.14 - Reserved + PINT PIE49_RESERVED_INT; // 5.15 - Reserved + PINT PIE50_RESERVED_INT; // 5.16 - Reserved + PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt + PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt + PINT PIE51_RESERVED_INT; // 6.11 - Reserved + PINT PIE52_RESERVED_INT; // 6.12 - Reserved + PINT PIE53_RESERVED_INT; // 6.13 - Reserved + PINT PIE54_RESERVED_INT; // 6.14 - Reserved + PINT PIE55_RESERVED_INT; // 6.15 - Reserved + PINT PIE56_RESERVED_INT; // 6.16 - Reserved + PINT PIE57_RESERVED_INT; // 7.9 - Reserved + PINT PIE58_RESERVED_INT; // 7.10 - Reserved + PINT PIE59_RESERVED_INT; // 7.11 - Reserved + PINT PIE60_RESERVED_INT; // 7.12 - Reserved + PINT PIE61_RESERVED_INT; // 7.13 - Reserved + PINT PIE62_RESERVED_INT; // 7.14 - Reserved + PINT PIE63_RESERVED_INT; // 7.15 - Reserved + PINT PIE64_RESERVED_INT; // 7.16 - Reserved + PINT PIE65_RESERVED_INT; // 8.9 - Reserved + PINT PIE66_RESERVED_INT; // 8.10 - Reserved + PINT PIE67_RESERVED_INT; // 8.11 - Reserved + PINT PIE68_RESERVED_INT; // 8.12 - Reserved + PINT PIE69_RESERVED_INT; // 8.13 - Reserved + PINT PIE70_RESERVED_INT; // 8.14 - Reserved +#ifdef CPU1 + PINT UPPA_INT; // 8.15 - uPPA Interrupt + PINT PIE72_RESERVED_INT; // 8.16 - Reserved +#elif defined(CPU2) + PINT PIE71_RESERVED_INT; // 8.15 - Reserved + PINT PIE72_RESERVED_INT; // 8.16 - Reserved +#endif + PINT PIE73_RESERVED_INT; // 9.9 - Reserved + PINT PIE74_RESERVED_INT; // 9.10 - Reserved + PINT PIE75_RESERVED_INT; // 9.11 - Reserved + PINT PIE76_RESERVED_INT; // 9.12 - Reserved + PINT PIE77_RESERVED_INT; // 9.13 - Reserved + PINT PIE78_RESERVED_INT; // 9.14 - Reserved +#ifdef CPU1 + PINT USBA_INT; // 9.15 - USBA Interrupt +#elif defined(CPU2) + PINT PIE79_RESERVED_INT; // 9.15 - Reserved +#endif + PINT PIE80_RESERVED_INT; // 9.16 - Reserved + PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt + PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 + PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 + PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 + PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt + PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 + PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 + PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 + PINT PIE81_RESERVED_INT; // 11.9 - Reserved + PINT PIE82_RESERVED_INT; // 11.10 - Reserved + PINT PIE83_RESERVED_INT; // 11.11 - Reserved + PINT PIE84_RESERVED_INT; // 11.12 - Reserved + PINT PIE85_RESERVED_INT; // 11.13 - Reserved + PINT PIE86_RESERVED_INT; // 11.14 - Reserved + PINT PIE87_RESERVED_INT; // 11.15 - Reserved + PINT PIE88_RESERVED_INT; // 11.16 - Reserved + PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt + PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt + PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt + PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt + PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt + PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt + PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt + PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt +}; + +//--------------------------------------------------------------------------- +// PieVect External References & Function Declarations: +// + +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of F2837xD_PIEVECT_H definition +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h new file mode 100644 index 0000000000..ae1cf3c422 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h @@ -0,0 +1,266 @@ +//########################################################################### +// +// FILE: F2837xD_sci.h +// +// TITLE: SCI Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SCI_H__ +#define __F2837xD_SCI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SCI Individual Register Bit Definitions: + +struct SCICCR_BITS { // bits description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +struct SCICTL1_BITS { // bits description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd1:1; // 4 Reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +struct SCIHBAUD_BITS { // bits description + Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCIHBAUD_REG { + Uint16 all; + struct SCIHBAUD_BITS bit; +}; + +struct SCILBAUD_BITS { // bits description + Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCILBAUD_REG { + Uint16 all; + struct SCILBAUD_BITS bit; +}; + +struct SCICTL2_BITS { // bits description + Uint16 TXINTENA:1; // 0 Transmit __interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd1:4; // 5:2 Reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +struct SCIRXST_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +struct SCIRXEMU_BITS { // bits description + Uint16 ERXDT:8; // 7:0 Receive emulation buffer data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCIRXEMU_REG { + Uint16 all; + struct SCIRXEMU_BITS bit; +}; + +struct SCIRXBUF_BITS { // bits description + Uint16 SAR:8; // 7:0 Receive Character bits + Uint16 rsvd1:6; // 13:8 Reserved + Uint16 SCIFFPE:1; // 14 Receiver error flag + Uint16 SCIFFFE:1; // 15 Receiver error flag +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +struct SCITXBUF_BITS { // bits description + Uint16 TXDT:8; // 7:0 Transmit data buffer + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCITXBUF_REG { + Uint16 all; + struct SCITXBUF_BITS bit; +}; + +struct SCIFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFORESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd1:5; // 12:8 Reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +struct SCIPRI_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 FREESOFT:2; // 4:3 Emulation modes + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 rsvd3:8; // 15:8 Reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register + union SCILBAUD_REG SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // Reserved + union SCITXBUF_REG SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2[2]; // Reserved + union SCIPRI_REG SCIPRI; // SCI Priority control +}; + +//--------------------------------------------------------------------------- +// SCI External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; +extern volatile struct SCI_REGS ScidRegs; +#endif +#ifdef CPU2 +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; +extern volatile struct SCI_REGS ScidRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h new file mode 100644 index 0000000000..7506115073 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h @@ -0,0 +1,534 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm.h +// +// TITLE: SDFM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SDFM_H__ +#define __F2837xD_SDFM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SDFM Individual Register Bit Definitions: + +struct SDIFLG_BITS { // bits description + Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 + Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 + Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 + Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 + Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 + Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 + Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 + Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 + Uint16 MF1:1; // 8 Modulator Failure for Filter 1 + Uint16 MF2:1; // 9 Modulator Failure for Filter 2 + Uint16 MF3:1; // 10 Modulator Failure for Filter 3 + Uint16 MF4:1; // 11 Modulator Failure for Filter 4 + Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 + Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 + Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 + Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 + Uint16 rsvd1:15; // 30:16 Reserved + Uint16 MIF:1; // 31 Master Interrupt Flag +}; + +union SDIFLG_REG { + Uint32 all; + struct SDIFLG_BITS bit; +}; + +struct SDIFLGCLR_BITS { // bits description + Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 + Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 + Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 + Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 + Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 + Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 + Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 + Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 + Uint16 MF1:1; // 8 Modulator Failure for Filter 1 + Uint16 MF2:1; // 9 Modulator Failure for Filter 2 + Uint16 MF3:1; // 10 Modulator Failure for Filter 3 + Uint16 MF4:1; // 11 Modulator Failure for Filter 4 + Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 + Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 + Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 + Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 + Uint16 rsvd1:15; // 30:16 Reserved + Uint16 MIF:1; // 31 Master Interrupt Flag +}; + +union SDIFLGCLR_REG { + Uint32 all; + struct SDIFLGCLR_BITS bit; +}; + +struct SDCTL_BITS { // bits description + Uint16 rsvd1:13; // 12:0 Reserved + Uint16 MIE:1; // 13 Master Interrupt enable + Uint16 rsvd2:1; // 14 Reserved + Uint16 rsvd3:1; // 15 Reserved +}; + +union SDCTL_REG { + Uint16 all; + struct SDCTL_BITS bit; +}; + +struct SDMFILEN_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 rsvd2:3; // 6:4 Reserved + Uint16 rsvd3:2; // 8:7 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 rsvd5:1; // 10 Reserved + Uint16 MFE:1; // 11 Master Filter Enable. + Uint16 rsvd6:1; // 12 Reserved + Uint16 rsvd7:3; // 15:13 Reserved +}; + +union SDMFILEN_REG { + Uint16 all; + struct SDMFILEN_BITS bit; +}; + +struct SDCTLPARM1_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM1_REG { + Uint16 all; + struct SDCTLPARM1_BITS bit; +}; + +struct SDDFPARM1_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM1_REG { + Uint16 all; + struct SDDFPARM1_BITS bit; +}; + +struct SDDPARM1_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM1_REG { + Uint16 all; + struct SDDPARM1_BITS bit; +}; + +struct SDCMPH1_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH1_REG { + Uint16 all; + struct SDCMPH1_BITS bit; +}; + +struct SDCMPL1_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL1_REG { + Uint16 all; + struct SDCMPL1_BITS bit; +}; + +struct SDCPARM1_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM1_REG { + Uint16 all; + struct SDCPARM1_BITS bit; +}; + +struct SDDATA1_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA1_REG { + Uint32 all; + struct SDDATA1_BITS bit; +}; + +struct SDCTLPARM2_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM2_REG { + Uint16 all; + struct SDCTLPARM2_BITS bit; +}; + +struct SDDFPARM2_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM2_REG { + Uint16 all; + struct SDDFPARM2_BITS bit; +}; + +struct SDDPARM2_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM2_REG { + Uint16 all; + struct SDDPARM2_BITS bit; +}; + +struct SDCMPH2_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH2_REG { + Uint16 all; + struct SDCMPH2_BITS bit; +}; + +struct SDCMPL2_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL2_REG { + Uint16 all; + struct SDCMPL2_BITS bit; +}; + +struct SDCPARM2_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM2_REG { + Uint16 all; + struct SDCPARM2_BITS bit; +}; + +struct SDDATA2_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA2_REG { + Uint32 all; + struct SDDATA2_BITS bit; +}; + +struct SDCTLPARM3_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM3_REG { + Uint16 all; + struct SDCTLPARM3_BITS bit; +}; + +struct SDDFPARM3_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM3_REG { + Uint16 all; + struct SDDFPARM3_BITS bit; +}; + +struct SDDPARM3_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM3_REG { + Uint16 all; + struct SDDPARM3_BITS bit; +}; + +struct SDCMPH3_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH3_REG { + Uint16 all; + struct SDCMPH3_BITS bit; +}; + +struct SDCMPL3_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL3_REG { + Uint16 all; + struct SDCMPL3_BITS bit; +}; + +struct SDCPARM3_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM3_REG { + Uint16 all; + struct SDCPARM3_BITS bit; +}; + +struct SDDATA3_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA3_REG { + Uint32 all; + struct SDDATA3_BITS bit; +}; + +struct SDCTLPARM4_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM4_REG { + Uint16 all; + struct SDCTLPARM4_BITS bit; +}; + +struct SDDFPARM4_BITS { // bits description + Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 SINC FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM4_REG { + Uint16 all; + struct SDDFPARM4_BITS bit; +}; + +struct SDDPARM4_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM4_REG { + Uint16 all; + struct SDDPARM4_BITS bit; +}; + +struct SDCMPH4_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH4_REG { + Uint16 all; + struct SDCMPH4_BITS bit; +}; + +struct SDCMPL4_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL4_REG { + Uint16 all; + struct SDCMPL4_BITS bit; +}; + +struct SDCPARM4_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM4_REG { + Uint16 all; + struct SDCPARM4_BITS bit; +}; + +struct SDDATA4_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA4_REG { + Uint32 all; + struct SDDATA4_BITS bit; +}; + +struct SDFM_REGS { + union SDIFLG_REG SDIFLG; // Interrupt Flag Register + union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register + union SDCTL_REG SDCTL; // SD Control Register + Uint16 rsvd1; // Reserved + union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable + Uint16 rsvd2[9]; // Reserved + union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 + union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 + union SDDPARM1_REG SDDPARM1; // Integer Parameter Register for Ch1 + union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 + union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 + union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1 + union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1 + Uint16 rsvd3[8]; // Reserved + union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 + union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 + union SDDPARM2_REG SDDPARM2; // Integer Parameter Register for Ch2 + union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 + union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 + union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2 + union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2 + Uint16 rsvd4[8]; // Reserved + union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 + union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 + union SDDPARM3_REG SDDPARM3; // Integer Parameter Register for Ch3 + union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 + union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 + union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3 + union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3 + Uint16 rsvd5[8]; // Reserved + union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 + union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 + union SDDPARM4_REG SDDPARM4; // Integer Parameter Register for Ch4 + union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 + union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 + union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4 + union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4 + Uint16 rsvd6[56]; // Reserved +}; + +//--------------------------------------------------------------------------- +// SDFM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SDFM_REGS Sdfm1Regs; +extern volatile struct SDFM_REGS Sdfm2Regs; +#endif +#ifdef CPU2 +extern volatile struct SDFM_REGS Sdfm1Regs; +extern volatile struct SDFM_REGS Sdfm2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h new file mode 100644 index 0000000000..30e2e6babb --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h @@ -0,0 +1,201 @@ +//########################################################################### +// +// FILE: F2837xD_spi.h +// +// TITLE: SPI Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SPI_H__ +#define __F2837xD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SPI Individual Register Bit Definitions: + +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character Length Control + Uint16 SPILBK:1; // 4 SPI Loopback + Uint16 HS_MODE:1; // 5 High Speed mode control + Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity + Uint16 SPISWRESET:1; // 7 SPI Software Reset + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 SPI Interupt Enable + Uint16 TALK:1; // 1 Master/Slave Transmit Enable + Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control + Uint16 CLK_PHASE:1; // 3 SPI Clock Phase + Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag + Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag + Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +struct SPIBRR_BITS { // bits description + Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union SPIBRR_REG { + Uint16 all; + struct SPIBRR_BITS bit; +}; + +struct SPIFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level + Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable + Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear + Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag + Uint16 TXFFST:5; // 12:8 Transmit FIFO Status + Uint16 TXFIFO:1; // 13 TXFIFO Reset + Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable + Uint16 SPIRST:1; // 15 SPI Reset +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level + Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable + Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear + Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag + Uint16 RXFFST:5; // 12:8 Receive FIFO Status + Uint16 RXFIFORESET:1; // 13 RXFIFO Reset + Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear + Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +struct SPIPRI_BITS { // bits description + Uint16 TRIWIRE:1; // 0 3-wire mode select bit + Uint16 STEINV:1; // 1 SPISTE inversion bit + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 FREE:1; // 4 Free emulation mode + Uint16 SOFT:1; // 5 Soft emulation mode + Uint16 rsvd2:1; // 6 Reserved + Uint16 rsvd3:9; // 15:7 Reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +struct SPI_REGS { + union SPICCR_REG SPICCR; // SPI Configuration Control Register + union SPICTL_REG SPICTL; // SPI Operation Control Register + union SPISTS_REG SPISTS; // SPI Status Register + Uint16 rsvd1; // Reserved + union SPIBRR_REG SPIBRR; // SPI Baud Rate Register + Uint16 rsvd2; // Reserved + Uint16 SPIRXEMU; // SPI Emulation Buffer Register + Uint16 SPIRXBUF; // SPI Serial Input Buffer Register + Uint16 SPITXBUF; // SPI Serial Output Buffer Register + Uint16 SPIDAT; // SPI Serial Data Register + union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register + union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register + union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register + Uint16 rsvd3[2]; // Reserved + union SPIPRI_REG SPIPRI; // SPI Priority Control Register +}; + +//--------------------------------------------------------------------------- +// SPI External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SPI_REGS SpiaRegs; +extern volatile struct SPI_REGS SpibRegs; +extern volatile struct SPI_REGS SpicRegs; +#endif +#ifdef CPU2 +extern volatile struct SPI_REGS SpiaRegs; +extern volatile struct SPI_REGS SpibRegs; +extern volatile struct SPI_REGS SpicRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h new file mode 100644 index 0000000000..dd438aed5f --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h @@ -0,0 +1,1964 @@ +//########################################################################### +// +// FILE: F2837xD_sysctrl.h +// +// TITLE: SYSCTRL Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SYSCTRL_H__ +#define __F2837xD_SYSCTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SYSCTRL Individual Register Bit Definitions: + +struct DEVCFGLOCK1_BITS { // bits description + Uint16 CPUSEL0:1; // 0 Lock bit for CPUSEL0 register + Uint16 CPUSEL1:1; // 1 Lock bit for CPUSEL1 register + Uint16 CPUSEL2:1; // 2 Lock bit for CPUSEL2 register + Uint16 CPUSEL3:1; // 3 Lock bit for CPUSEL3 register + Uint16 CPUSEL4:1; // 4 Lock bit for CPUSEL4 register + Uint16 CPUSEL5:1; // 5 Lock bit for CPUSEL5 register + Uint16 CPUSEL6:1; // 6 Lock bit for CPUSEL6 register + Uint16 CPUSEL7:1; // 7 Lock bit for CPUSEL7 register + Uint16 CPUSEL8:1; // 8 Lock bit for CPUSEL8 register + Uint16 CPUSEL9:1; // 9 Lock bit for CPUSEL9 register + Uint16 CPUSEL10:1; // 10 Lock bit for CPUSEL10 register + Uint16 CPUSEL11:1; // 11 Lock bit for CPUSEL11 register + Uint16 CPUSEL12:1; // 12 Lock bit for CPUSEL12 register + Uint16 CPUSEL13:1; // 13 Lock bit for CPUSEL13 register + Uint16 CPUSEL14:1; // 14 Lock bit for CPUSEL14 register + Uint16 rsvd1:1; // 15 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DEVCFGLOCK1_REG { + Uint32 all; + struct DEVCFGLOCK1_BITS bit; +}; + +struct PARTIDL_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 rsvd2:2; // 4:3 Reserved + Uint16 rsvd3:1; // 5 Reserved + Uint16 QUAL:2; // 7:6 Qualification Status + Uint16 PIN_COUNT:3; // 10:8 Device Pin Count + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 INSTASPIN:2; // 14:13 Motorware feature set + Uint16 rsvd6:1; // 15 Reserved + Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB + Uint16 rsvd7:4; // 27:24 Reserved + Uint16 PARTID_FORMAT_REVISION:4; // 31:28 Revision of the PARTID format +}; + +union PARTIDL_REG { + Uint32 all; + struct PARTIDL_BITS bit; +}; + +struct PARTIDH_BITS { // bits description + Uint16 rsvd1:8; // 7:0 Reserved + Uint16 FAMILY:8; // 15:8 Device family + Uint16 PARTNO:8; // 23:16 Device part number + Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID +}; + +union PARTIDH_REG { + Uint32 all; + struct PARTIDH_BITS bit; +}; + +struct DC0_BITS { // bits description + Uint16 SINGLE_CORE:1; // 0 Single Core vs Dual Core + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC0_REG { + Uint32 all; + struct DC0_BITS bit; +}; + +struct DC1_BITS { // bits description + Uint16 CPU1_FPU_TMU:1; // 0 CPU1's FPU1+TMU1 + Uint16 CPU2_FPU_TMU:1; // 1 CPU2's FPU2+TMU2 + Uint16 CPU1_VCU:1; // 2 CPU1's VCU + Uint16 CPU2_VCU:1; // 3 CPU2's VCU + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 CPU1_CLA1:1; // 6 CPU1.CLA1 + Uint16 rsvd2:1; // 7 Reserved + Uint16 CPU2_CLA1:1; // 8 CPU2.CLA1 + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union DC1_REG { + Uint32 all; + struct DC1_BITS bit; +}; + +struct DC2_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 + Uint16 EMIF2:1; // 1 EMIF2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC2_REG { + Uint32 all; + struct DC2_BITS bit; +}; + +struct DC3_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 + Uint16 EPWM2:1; // 1 EPWM2 + Uint16 EPWM3:1; // 2 EPWM3 + Uint16 EPWM4:1; // 3 EPWM4 + Uint16 EPWM5:1; // 4 EPWM5 + Uint16 EPWM6:1; // 5 EPWM6 + Uint16 EPWM7:1; // 6 EPWM7 + Uint16 EPWM8:1; // 7 EPWM8 + Uint16 EPWM9:1; // 8 EPWM9 + Uint16 EPWM10:1; // 9 EPWM10 + Uint16 EPWM11:1; // 10 EPWM11 + Uint16 EPWM12:1; // 11 EPWM12 + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union DC3_REG { + Uint32 all; + struct DC3_BITS bit; +}; + +struct DC4_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 + Uint16 ECAP2:1; // 1 ECAP2 + Uint16 ECAP3:1; // 2 ECAP3 + Uint16 ECAP4:1; // 3 ECAP4 + Uint16 ECAP5:1; // 4 ECAP5 + Uint16 ECAP6:1; // 5 ECAP6 + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union DC4_REG { + Uint32 all; + struct DC4_BITS bit; +}; + +struct DC5_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 + Uint16 EQEP2:1; // 1 EQEP2 + Uint16 EQEP3:1; // 2 EQEP3 + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DC5_REG { + Uint32 all; + struct DC5_BITS bit; +}; + +struct DC6_BITS { // bits description + Uint16 CLB1:1; // 0 CLB1 + Uint16 CLB2:1; // 1 CLB2 + Uint16 CLB3:1; // 2 CLB3 + Uint16 CLB4:1; // 3 CLB4 + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 rsvd3:1; // 6 Reserved + Uint16 rsvd4:1; // 7 Reserved + Uint16 rsvd5:8; // 15:8 Reserved + Uint16 rsvd6:16; // 31:16 Reserved +}; + +union DC6_REG { + Uint32 all; + struct DC6_BITS bit; +}; + +struct DC7_BITS { // bits description + Uint16 SD1:1; // 0 SD1 + Uint16 SD2:1; // 1 SD2 + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union DC7_REG { + Uint32 all; + struct DC7_BITS bit; +}; + +struct DC8_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A + Uint16 SCI_B:1; // 1 SCI_B + Uint16 SCI_C:1; // 2 SCI_C + Uint16 SCI_D:1; // 3 SCI_D + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC8_REG { + Uint32 all; + struct DC8_BITS bit; +}; + +struct DC9_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A + Uint16 SPI_B:1; // 1 SPI_B + Uint16 SPI_C:1; // 2 SPI_C + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union DC9_REG { + Uint32 all; + struct DC9_BITS bit; +}; + +struct DC10_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A + Uint16 I2C_B:1; // 1 I2C_B + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union DC10_REG { + Uint32 all; + struct DC10_BITS bit; +}; + +struct DC11_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A + Uint16 CAN_B:1; // 1 CAN_B + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union DC11_REG { + Uint32 all; + struct DC11_BITS bit; +}; + +struct DC12_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A + Uint16 McBSP_B:1; // 1 McBSP_B + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:2; // 17:16 Decides the capability of the USB_A Module + Uint16 rsvd2:2; // 19:18 Reserved + Uint16 rsvd3:12; // 31:20 Reserved +}; + +union DC12_REG { + Uint32 all; + struct DC12_BITS bit; +}; + +struct DC13_BITS { // bits description + Uint16 uPP_A:1; // 0 uPP_A + Uint16 rsvd1:1; // 1 Reserved + Uint16 rsvd2:14; // 15:2 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DC13_REG { + Uint32 all; + struct DC13_BITS bit; +}; + +struct DC14_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A + Uint16 ADC_B:1; // 1 ADC_B + Uint16 ADC_C:1; // 2 ADC_C + Uint16 ADC_D:1; // 3 ADC_D + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC14_REG { + Uint32 all; + struct DC14_BITS bit; +}; + +struct DC15_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 + Uint16 CMPSS2:1; // 1 CMPSS2 + Uint16 CMPSS3:1; // 2 CMPSS3 + Uint16 CMPSS4:1; // 3 CMPSS4 + Uint16 CMPSS5:1; // 4 CMPSS5 + Uint16 CMPSS6:1; // 5 CMPSS6 + Uint16 CMPSS7:1; // 6 CMPSS7 + Uint16 CMPSS8:1; // 7 CMPSS8 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC15_REG { + Uint32 all; + struct DC15_BITS bit; +}; + +struct DC17_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered-DAC_A + Uint16 DAC_B:1; // 17 Buffered-DAC_B + Uint16 DAC_C:1; // 18 Buffered-DAC_C + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union DC17_REG { + Uint32 all; + struct DC17_BITS bit; +}; + +struct DC18_BITS { // bits description + Uint16 LS0_1:1; // 0 LS0_1 + Uint16 LS1_1:1; // 1 LS1_1 + Uint16 LS2_1:1; // 2 LS2_1 + Uint16 LS3_1:1; // 3 LS3_1 + Uint16 LS4_1:1; // 4 LS4_1 + Uint16 LS5_1:1; // 5 LS5_1 + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC18_REG { + Uint32 all; + struct DC18_BITS bit; +}; + +struct DC19_BITS { // bits description + Uint16 LS0_2:1; // 0 LS0_2 + Uint16 LS1_2:1; // 1 LS1_2 + Uint16 LS2_2:1; // 2 LS2_2 + Uint16 LS3_2:1; // 3 LS3_2 + Uint16 LS4_2:1; // 4 LS4_2 + Uint16 LS5_2:1; // 5 LS5_2 + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC19_REG { + Uint32 all; + struct DC19_BITS bit; +}; + +struct DC20_BITS { // bits description + Uint16 GS0:1; // 0 GS0 + Uint16 GS1:1; // 1 GS1 + Uint16 GS2:1; // 2 GS2 + Uint16 GS3:1; // 3 GS3 + Uint16 GS4:1; // 4 GS4 + Uint16 GS5:1; // 5 GS5 + Uint16 GS6:1; // 6 GS6 + Uint16 GS7:1; // 7 GS7 + Uint16 GS8:1; // 8 GS8 + Uint16 GS9:1; // 9 GS9 + Uint16 GS10:1; // 10 GS10 + Uint16 GS11:1; // 11 GS11 + Uint16 GS12:1; // 12 GS12 + Uint16 GS13:1; // 13 GS13 + Uint16 GS14:1; // 14 GS14 + Uint16 GS15:1; // 15 GS15 + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union DC20_REG { + Uint32 all; + struct DC20_BITS bit; +}; + +struct PERCNF1_BITS { // bits description + Uint16 ADC_A_MODE:1; // 0 ADC_A mode setting bit + Uint16 ADC_B_MODE:1; // 1 ADC_B mode setting bit + Uint16 ADC_C_MODE:1; // 2 ADC_C mode setting bit + Uint16 ADC_D_MODE:1; // 3 ADC_D mode setting bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 USB_A_PHY:1; // 16 USB_A_PHY + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union PERCNF1_REG { + Uint32 all; + struct PERCNF1_BITS bit; +}; + +struct FUSEERR_BITS { // bits description + Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status + Uint16 ERR:1; // 5 Efuse Self Test Error Status + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FUSEERR_REG { + Uint32 all; + struct FUSEERR_BITS bit; +}; + +struct SOFTPRES0_BITS { // bits description + Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 CPU2_CLA1:1; // 2 CPU2_CLA1 software reset bit + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union SOFTPRES0_REG { + Uint32 all; + struct SOFTPRES0_BITS bit; +}; + +struct SOFTPRES1_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 software reset bit + Uint16 EMIF2:1; // 1 EMIF2 software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES1_REG { + Uint32 all; + struct SOFTPRES1_BITS bit; +}; + +struct SOFTPRES2_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 software reset bit + Uint16 EPWM2:1; // 1 EPWM2 software reset bit + Uint16 EPWM3:1; // 2 EPWM3 software reset bit + Uint16 EPWM4:1; // 3 EPWM4 software reset bit + Uint16 EPWM5:1; // 4 EPWM5 software reset bit + Uint16 EPWM6:1; // 5 EPWM6 software reset bit + Uint16 EPWM7:1; // 6 EPWM7 software reset bit + Uint16 EPWM8:1; // 7 EPWM8 software reset bit + Uint16 EPWM9:1; // 8 EPWM9 software reset bit + Uint16 EPWM10:1; // 9 EPWM10 software reset bit + Uint16 EPWM11:1; // 10 EPWM11 software reset bit + Uint16 EPWM12:1; // 11 EPWM12 software reset bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union SOFTPRES2_REG { + Uint32 all; + struct SOFTPRES2_BITS bit; +}; + +struct SOFTPRES3_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 software reset bit + Uint16 ECAP2:1; // 1 ECAP2 software reset bit + Uint16 ECAP3:1; // 2 ECAP3 software reset bit + Uint16 ECAP4:1; // 3 ECAP4 software reset bit + Uint16 ECAP5:1; // 4 ECAP5 software reset bit + Uint16 ECAP6:1; // 5 ECAP6 software reset bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union SOFTPRES3_REG { + Uint32 all; + struct SOFTPRES3_BITS bit; +}; + +struct SOFTPRES4_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 software reset bit + Uint16 EQEP2:1; // 1 EQEP2 software reset bit + Uint16 EQEP3:1; // 2 EQEP3 software reset bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union SOFTPRES4_REG { + Uint32 all; + struct SOFTPRES4_BITS bit; +}; + +struct SOFTPRES6_BITS { // bits description + Uint16 SD1:1; // 0 SD1 software reset bit + Uint16 SD2:1; // 1 SD2 software reset bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union SOFTPRES6_REG { + Uint32 all; + struct SOFTPRES6_BITS bit; +}; + +struct SOFTPRES7_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A software reset bit + Uint16 SCI_B:1; // 1 SCI_B software reset bit + Uint16 SCI_C:1; // 2 SCI_C software reset bit + Uint16 SCI_D:1; // 3 SCI_D software reset bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES7_REG { + Uint32 all; + struct SOFTPRES7_BITS bit; +}; + +struct SOFTPRES8_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A software reset bit + Uint16 SPI_B:1; // 1 SPI_B software reset bit + Uint16 SPI_C:1; // 2 SPI_C software reset bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union SOFTPRES8_REG { + Uint32 all; + struct SOFTPRES8_BITS bit; +}; + +struct SOFTPRES9_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A software reset bit + Uint16 I2C_B:1; // 1 I2C_B software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union SOFTPRES9_REG { + Uint32 all; + struct SOFTPRES9_BITS bit; +}; + +struct SOFTPRES11_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A software reset bit + Uint16 McBSP_B:1; // 1 McBSP_B software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:1; // 16 USB_A software reset bit + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union SOFTPRES11_REG { + Uint32 all; + struct SOFTPRES11_BITS bit; +}; + +struct SOFTPRES13_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A software reset bit + Uint16 ADC_B:1; // 1 ADC_B software reset bit + Uint16 ADC_C:1; // 2 ADC_C software reset bit + Uint16 ADC_D:1; // 3 ADC_D software reset bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES13_REG { + Uint32 all; + struct SOFTPRES13_BITS bit; +}; + +struct SOFTPRES14_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit + Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit + Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit + Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit + Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit + Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit + Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit + Uint16 CMPSS8:1; // 7 CMPSS8 software reset bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES14_REG { + Uint32 all; + struct SOFTPRES14_BITS bit; +}; + +struct SOFTPRES16_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C software reset bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union SOFTPRES16_REG { + Uint32 all; + struct SOFTPRES16_BITS bit; +}; + +struct CPUSEL0_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 CPU select bit + Uint16 EPWM2:1; // 1 EPWM2 CPU select bit + Uint16 EPWM3:1; // 2 EPWM3 CPU select bit + Uint16 EPWM4:1; // 3 EPWM4 CPU select bit + Uint16 EPWM5:1; // 4 EPWM5 CPU select bit + Uint16 EPWM6:1; // 5 EPWM6 CPU select bit + Uint16 EPWM7:1; // 6 EPWM7 CPU select bit + Uint16 EPWM8:1; // 7 EPWM8 CPU select bit + Uint16 EPWM9:1; // 8 EPWM9 CPU select bit + Uint16 EPWM10:1; // 9 EPWM10 CPU select bit + Uint16 EPWM11:1; // 10 EPWM11 CPU select bit + Uint16 EPWM12:1; // 11 EPWM12 CPU select bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union CPUSEL0_REG { + Uint32 all; + struct CPUSEL0_BITS bit; +}; + +struct CPUSEL1_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 CPU select bit + Uint16 ECAP2:1; // 1 ECAP2 CPU select bit + Uint16 ECAP3:1; // 2 ECAP3 CPU select bit + Uint16 ECAP4:1; // 3 ECAP4 CPU select bit + Uint16 ECAP5:1; // 4 ECAP5 CPU select bit + Uint16 ECAP6:1; // 5 ECAP6 CPU select bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CPUSEL1_REG { + Uint32 all; + struct CPUSEL1_BITS bit; +}; + +struct CPUSEL2_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 CPU select bit + Uint16 EQEP2:1; // 1 EQEP2 CPU select bit + Uint16 EQEP3:1; // 2 EQEP3 CPU select bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CPUSEL2_REG { + Uint32 all; + struct CPUSEL2_BITS bit; +}; + +struct CPUSEL4_BITS { // bits description + Uint16 SD1:1; // 0 SD1 CPU select bit + Uint16 SD2:1; // 1 SD2 CPU select bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union CPUSEL4_REG { + Uint32 all; + struct CPUSEL4_BITS bit; +}; + +struct CPUSEL5_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A CPU select bit + Uint16 SCI_B:1; // 1 SCI_B CPU select bit + Uint16 SCI_C:1; // 2 SCI_C CPU select bit + Uint16 SCI_D:1; // 3 SCI_D CPU select bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL5_REG { + Uint32 all; + struct CPUSEL5_BITS bit; +}; + +struct CPUSEL6_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A CPU select bit + Uint16 SPI_B:1; // 1 SPI_B CPU select bit + Uint16 SPI_C:1; // 2 SPI_C CPU select bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union CPUSEL6_REG { + Uint32 all; + struct CPUSEL6_BITS bit; +}; + +struct CPUSEL7_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A CPU select bit + Uint16 I2C_B:1; // 1 I2C_B CPU select bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union CPUSEL7_REG { + Uint32 all; + struct CPUSEL7_BITS bit; +}; + +struct CPUSEL8_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A CPU select bit + Uint16 CAN_B:1; // 1 CAN_B CPU select bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CPUSEL8_REG { + Uint32 all; + struct CPUSEL8_BITS bit; +}; + +struct CPUSEL9_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A CPU select bit + Uint16 McBSP_B:1; // 1 McBSP_B CPU select bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL9_REG { + Uint32 all; + struct CPUSEL9_BITS bit; +}; + +struct CPUSEL11_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A CPU select bit + Uint16 ADC_B:1; // 1 ADC_B CPU select bit + Uint16 ADC_C:1; // 2 ADC_C CPU select bit + Uint16 ADC_D:1; // 3 ADC_D CPU select bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL11_REG { + Uint32 all; + struct CPUSEL11_BITS bit; +}; + +struct CPUSEL12_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 CPU select bit + Uint16 CMPSS2:1; // 1 CMPSS2 CPU select bit + Uint16 CMPSS3:1; // 2 CMPSS3 CPU select bit + Uint16 CMPSS4:1; // 3 CMPSS4 CPU select bit + Uint16 CMPSS5:1; // 4 CMPSS5 CPU select bit + Uint16 CMPSS6:1; // 5 CMPSS6 CPU select bit + Uint16 CMPSS7:1; // 6 CMPSS7 CPU select bit + Uint16 CMPSS8:1; // 7 CMPSS8 CPU select bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL12_REG { + Uint32 all; + struct CPUSEL12_BITS bit; +}; + +struct CPUSEL14_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A CPU select bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B CPU select bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C CPU select bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union CPUSEL14_REG { + Uint32 all; + struct CPUSEL14_BITS bit; +}; + +struct CPU2RESCTL_BITS { // bits description + Uint16 RESET:1; // 0 CPU2 Reset Control bit + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union CPU2RESCTL_REG { + Uint32 all; + struct CPU2RESCTL_BITS bit; +}; + +struct RSTSTAT_BITS { // bits description + Uint16 CPU2RES:1; // 0 CPU2 Reset Status bit + Uint16 CPU2NMIWDRST:1; // 1 Indicates whether a CPU2.NMIWD reset was issued to CPU2 + Uint16 CPU2HWBISTRST0:1; // 2 Indicates whether a HWBIST reset was issued to CPU2 + Uint16 CPU2HWBISTRST1:1; // 3 Indicates whether a HWBIST reset was issued to CPU2 + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union RSTSTAT_REG { + Uint16 all; + struct RSTSTAT_BITS bit; +}; + +struct LPMSTAT_BITS { // bits description + Uint16 CPU2LPMSTAT:2; // 1:0 CPU2 LPM Status + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union LPMSTAT_REG { + Uint16 all; + struct LPMSTAT_BITS bit; +}; + +struct SYSDBGCTL_BITS { // bits description + Uint16 BIT_0:1; // 0 Used in PLL startup. Only reset by POR. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSDBGCTL_REG { + Uint32 all; + struct SYSDBGCTL_BITS bit; +}; + +struct DEV_CFG_REGS { + union DEVCFGLOCK1_REG DEVCFGLOCK1; // Lock bit for CPUSELx registers + Uint16 rsvd1[6]; // Reserved + union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number + union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number + Uint32 REVID; // Device Revision Number + Uint16 rsvd2[2]; // Reserved + union DC0_REG DC0; // Device Capability: Device Information + union DC1_REG DC1; // Device Capability: Processing Block Customization + union DC2_REG DC2; // Device Capability: EMIF Customization + union DC3_REG DC3; // Device Capability: Peripheral Customization + union DC4_REG DC4; // Device Capability: Peripheral Customization + union DC5_REG DC5; // Device Capability: Peripheral Customization + union DC6_REG DC6; // Device Capability: Peripheral Customization + union DC7_REG DC7; // Device Capability: Peripheral Customization + union DC8_REG DC8; // Device Capability: Peripheral Customization + union DC9_REG DC9; // Device Capability: Peripheral Customization + union DC10_REG DC10; // Device Capability: Peripheral Customization + union DC11_REG DC11; // Device Capability: Peripheral Customization + union DC12_REG DC12; // Device Capability: Peripheral Customization + union DC13_REG DC13; // Device Capability: Peripheral Customization + union DC14_REG DC14; // Device Capability: Analog Modules Customization + union DC15_REG DC15; // Device Capability: Analog Modules Customization + Uint16 rsvd3[2]; // Reserved + union DC17_REG DC17; // Device Capability: Analog Modules Customization + union DC18_REG DC18; // Device Capability: CPU1 Lx SRAM Customization + union DC19_REG DC19; // Device Capability: CPU2 Lx SRAM Customization + union DC20_REG DC20; // Device Capability: GSx SRAM Customization + Uint16 rsvd4[38]; // Reserved + union PERCNF1_REG PERCNF1; // Peripheral Configuration register + Uint16 rsvd5[18]; // Reserved + union FUSEERR_REG FUSEERR; // e-Fuse error Status register + Uint16 rsvd6[12]; // Reserved + union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register + union SOFTPRES1_REG SOFTPRES1; // EMIF Software Reset register + union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register + union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register + union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register + Uint16 rsvd7[2]; // Reserved + union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register + union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register + union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register + union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register + Uint16 rsvd8[2]; // Reserved + union SOFTPRES11_REG SOFTPRES11; // Peripheral Software Reset register + Uint16 rsvd9[2]; // Reserved + union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register + union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register + Uint16 rsvd10[2]; // Reserved + union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register + Uint16 rsvd11[50]; // Reserved + union CPUSEL0_REG CPUSEL0; // CPU Select register for common peripherals + union CPUSEL1_REG CPUSEL1; // CPU Select register for common peripherals + union CPUSEL2_REG CPUSEL2; // CPU Select register for common peripherals + Uint16 rsvd12[2]; // Reserved + union CPUSEL4_REG CPUSEL4; // CPU Select register for common peripherals + union CPUSEL5_REG CPUSEL5; // CPU Select register for common peripherals + union CPUSEL6_REG CPUSEL6; // CPU Select register for common peripherals + union CPUSEL7_REG CPUSEL7; // CPU Select register for common peripherals + union CPUSEL8_REG CPUSEL8; // CPU Select register for common peripherals + union CPUSEL9_REG CPUSEL9; // CPU Select register for common peripherals + Uint16 rsvd13[2]; // Reserved + union CPUSEL11_REG CPUSEL11; // CPU Select register for common peripherals + union CPUSEL12_REG CPUSEL12; // CPU Select register for common peripherals + Uint16 rsvd14[2]; // Reserved + union CPUSEL14_REG CPUSEL14; // CPU Select register for common peripherals + Uint16 rsvd15[46]; // Reserved + union CPU2RESCTL_REG CPU2RESCTL; // CPU2 Reset Control Register + union RSTSTAT_REG RSTSTAT; // Reset Status register for secondary C28x CPUs + union LPMSTAT_REG LPMSTAT; // LPM Status Register for secondary C28x CPUs + Uint16 rsvd16[6]; // Reserved + union SYSDBGCTL_REG SYSDBGCTL; // System Debug Control register +}; + +struct CLKSEM_BITS { // bits description + Uint16 SEM:2; // 1:0 Semaphore for CLKCFG Ownership by CPU1 or CPU2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union CLKSEM_REG { + Uint32 all; + struct CLKSEM_BITS bit; +}; + +struct CLKCFGLOCK1_BITS { // bits description + Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register + Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register + Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register + Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register + Uint16 SYSPLLCTL2:1; // 4 Lock bit for SYSPLLCTL2 register + Uint16 SYSPLLCTL3:1; // 5 Lock bit for SYSPLLCTL3 register + Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register + Uint16 AUXPLLCTL1:1; // 7 Lock bit for AUXPLLCTL1 register + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 AUXPLLMULT:1; // 10 Lock bit for AUXPLLMULT register + Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register + Uint16 AUXCLKDIVSEL:1; // 12 Lock bit for AUXCLKDIVSEL register + Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register + Uint16 rsvd3:1; // 14 Reserved + Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CLKCFGLOCK1_REG { + Uint32 all; + struct CLKCFGLOCK1_BITS bit; +}; + +struct CLKSRCCTL1_BITS { // bits description + Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit + Uint16 XTALOFF:1; // 4 Crystal (External) Oscillator Off Bit + Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit + Uint16 rsvd2:10; // 15:6 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CLKSRCCTL1_REG { + Uint32 all; + struct CLKSRCCTL1_BITS bit; +}; + +struct CLKSRCCTL2_BITS { // bits description + Uint16 AUXOSCCLKSRCSEL:2; // 1:0 AUXOSCCLK Source Select Bit + Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit + Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 rsvd2:2; // 9:8 Reserved + Uint16 rsvd3:6; // 15:10 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CLKSRCCTL2_REG { + Uint32 all; + struct CLKSRCCTL2_BITS bit; +}; + +struct CLKSRCCTL3_BITS { // bits description + Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CLKSRCCTL3_REG { + Uint32 all; + struct CLKSRCCTL3_BITS bit; +}; + +struct SYSPLLCTL1_BITS { // bits description + Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit + Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSPLLCTL1_REG { + Uint32 all; + struct SYSPLLCTL1_BITS bit; +}; + +struct SYSPLLMULT_BITS { // bits description + Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier + Uint16 rsvd1:1; // 7 Reserved + Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union SYSPLLMULT_REG { + Uint32 all; + struct SYSPLLMULT_BITS bit; +}; + +struct SYSPLLSTS_BITS { // bits description + Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit + Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSPLLSTS_REG { + Uint32 all; + struct SYSPLLSTS_BITS bit; +}; + +struct AUXPLLCTL1_BITS { // bits description + Uint16 PLLEN:1; // 0 AUXPLL enable/disable bit + Uint16 PLLCLKEN:1; // 1 AUXPLL bypassed or included in the AUXPLLCLK path + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXPLLCTL1_REG { + Uint32 all; + struct AUXPLLCTL1_BITS bit; +}; + +struct AUXPLLMULT_BITS { // bits description + Uint16 IMULT:7; // 6:0 AUXPLL Integer Multiplier + Uint16 rsvd1:1; // 7 Reserved + Uint16 FMULT:2; // 9:8 AUXPLL Fractional Multiplier + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union AUXPLLMULT_REG { + Uint32 all; + struct AUXPLLMULT_BITS bit; +}; + +struct AUXPLLSTS_BITS { // bits description + Uint16 LOCKS:1; // 0 AUXPLL Lock Status Bit + Uint16 SLIPS:1; // 1 AUXPLL Slip Status Bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXPLLSTS_REG { + Uint32 all; + struct AUXPLLSTS_BITS bit; +}; + +struct SYSCLKDIVSEL_BITS { // bits description + Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSCLKDIVSEL_REG { + Uint32 all; + struct SYSCLKDIVSEL_BITS bit; +}; + +struct AUXCLKDIVSEL_BITS { // bits description + Uint16 AUXPLLDIV:2; // 1:0 AUXPLLCLK Divide Select + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXCLKDIVSEL_REG { + Uint32 all; + struct AUXCLKDIVSEL_BITS bit; +}; + +struct PERCLKDIVSEL_BITS { // bits description + Uint16 EPWMCLKDIV:2; // 1:0 EPWM Clock Divide Select + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 EMIF1CLKDIV:1; // 4 EMIF1 Clock Divide Select + Uint16 rsvd2:1; // 5 Reserved + Uint16 EMIF2CLKDIV:1; // 6 EMIF2 Clock Divide Select + Uint16 rsvd3:9; // 15:7 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PERCLKDIVSEL_REG { + Uint32 all; + struct PERCLKDIVSEL_BITS bit; +}; + +struct XCLKOUTDIVSEL_BITS { // bits description + Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union XCLKOUTDIVSEL_REG { + Uint32 all; + struct XCLKOUTDIVSEL_BITS bit; +}; + +struct LOSPCP_BITS { // bits description + Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LOSPCP_REG { + Uint32 all; + struct LOSPCP_BITS bit; +}; + +struct MCDCR_BITS { // bits description + Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit + Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit + Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit + Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MCDCR_REG { + Uint32 all; + struct MCDCR_BITS bit; +}; + +struct X1CNT_BITS { // bits description + Uint16 X1CNT:10; // 9:0 X1 Counter + Uint16 rsvd1:6; // 15:10 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union X1CNT_REG { + Uint32 all; + struct X1CNT_BITS bit; +}; + +struct CLK_CFG_REGS { + union CLKSEM_REG CLKSEM; // Clock Control Semaphore Register + union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers + Uint16 rsvd1[4]; // Reserved + union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 + union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 + union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 + union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 + Uint16 rsvd2[4]; // Reserved + union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register + union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register + union AUXPLLCTL1_REG AUXPLLCTL1; // AUXPLL Control register-1 + Uint16 rsvd3[4]; // Reserved + union AUXPLLMULT_REG AUXPLLMULT; // AUXPLL Multiplier register + union AUXPLLSTS_REG AUXPLLSTS; // AUXPLL Status register + union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register + union AUXCLKDIVSEL_REG AUXCLKDIVSEL; // Auxillary Clock Divider Select register + union PERCLKDIVSEL_REG PERCLKDIVSEL; // Peripheral Clock Divider Selet register + union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register + Uint16 rsvd4[2]; // Reserved + union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar + union MCDCR_REG MCDCR; // Missing Clock Detect Control Register + union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock +}; + +struct CPUSYSLOCK1_BITS { // bits description + Uint16 HIBBOOTMODE:1; // 0 Lock bit for HIBBOOTMODE register + Uint16 IORESTOREADDR:1; // 1 Lock bit for IORESTOREADDR Register + Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register + Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register + Uint16 PCLKCR1:1; // 4 Lock bit for PCLKCR1 Register + Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register + Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register + Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register + Uint16 PCLKCR5:1; // 8 Lock bit for PCLKCR5 Register + Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register + Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register + Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register + Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register + Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register + Uint16 PCLKCR11:1; // 14 Lock bit for PCLKCR11 Register + Uint16 PCLKCR12:1; // 15 Lock bit for PCLKCR12 Register + Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register + Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register + Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register + Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register + Uint16 SECMSEL:1; // 20 Lock bit for SECMSEL Register + Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register + Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register + Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register + Uint16 rsvd1:8; // 31:24 Reserved +}; + +union CPUSYSLOCK1_REG { + Uint32 all; + struct CPUSYSLOCK1_BITS bit; +}; + +struct IORESTOREADDR_BITS { // bits description + Uint32 ADDR:22; // 21:0 restoreIO() routine address + Uint16 rsvd1:10; // 31:22 Reserved +}; + +union IORESTOREADDR_REG { + Uint32 all; + struct IORESTOREADDR_BITS bit; +}; + +struct PIEVERRADDR_BITS { // bits description + Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address + Uint16 rsvd1:10; // 31:22 Reserved +}; + +union PIEVERRADDR_REG { + Uint32 all; + struct PIEVERRADDR_BITS bit; +}; + +struct PCLKCR0_BITS { // bits description + Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 DMA:1; // 2 DMA Clock Enable bit + Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit + Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit + Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit + Uint16 rsvd2:10; // 15:6 Reserved + Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit + Uint16 rsvd3:1; // 17 Reserved + Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync + Uint16 GTBCLKSYNC:1; // 19 EPWM Time Base Clock Global sync + Uint16 rsvd4:12; // 31:20 Reserved +}; + +union PCLKCR0_REG { + Uint32 all; + struct PCLKCR0_BITS bit; +}; + +struct PCLKCR1_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 Clock Enable bit + Uint16 EMIF2:1; // 1 EMIF2 Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR1_REG { + Uint32 all; + struct PCLKCR1_BITS bit; +}; + +struct PCLKCR2_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit + Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit + Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit + Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit + Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit + Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit + Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit + Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit + Uint16 EPWM9:1; // 8 EPWM9 Clock Enable bit + Uint16 EPWM10:1; // 9 EPWM10 Clock Enable bit + Uint16 EPWM11:1; // 10 EPWM11 Clock Enable bit + Uint16 EPWM12:1; // 11 EPWM12 Clock Enable bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union PCLKCR2_REG { + Uint32 all; + struct PCLKCR2_BITS bit; +}; + +struct PCLKCR3_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit + Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit + Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit + Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit + Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit + Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PCLKCR3_REG { + Uint32 all; + struct PCLKCR3_BITS bit; +}; + +struct PCLKCR4_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit + Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit + Uint16 EQEP3:1; // 2 EQEP3 Clock Enable bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PCLKCR4_REG { + Uint32 all; + struct PCLKCR4_BITS bit; +}; + +struct PCLKCR6_BITS { // bits description + Uint16 SD1:1; // 0 SD1 Clock Enable bit + Uint16 SD2:1; // 1 SD2 Clock Enable bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union PCLKCR6_REG { + Uint32 all; + struct PCLKCR6_BITS bit; +}; + +struct PCLKCR7_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit + Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit + Uint16 SCI_C:1; // 2 SCI_C Clock Enable bit + Uint16 SCI_D:1; // 3 SCI_D Clock Enable bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR7_REG { + Uint32 all; + struct PCLKCR7_BITS bit; +}; + +struct PCLKCR8_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit + Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit + Uint16 SPI_C:1; // 2 SPI_C Clock Enable bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union PCLKCR8_REG { + Uint32 all; + struct PCLKCR8_BITS bit; +}; + +struct PCLKCR9_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit + Uint16 I2C_B:1; // 1 I2C_B Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union PCLKCR9_REG { + Uint32 all; + struct PCLKCR9_BITS bit; +}; + +struct PCLKCR10_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit + Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PCLKCR10_REG { + Uint32 all; + struct PCLKCR10_BITS bit; +}; + +struct PCLKCR11_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A Clock Enable bit + Uint16 McBSP_B:1; // 1 McBSP_B Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:1; // 16 USB_A Clock Enable bit + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union PCLKCR11_REG { + Uint32 all; + struct PCLKCR11_BITS bit; +}; + +struct PCLKCR12_BITS { // bits description + Uint16 uPP_A:1; // 0 uPP_A Clock Enable bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 rsvd2:14; // 15:2 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PCLKCR12_REG { + Uint32 all; + struct PCLKCR12_BITS bit; +}; + +struct PCLKCR13_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit + Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit + Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit + Uint16 ADC_D:1; // 3 ADC_D Clock Enable bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR13_REG { + Uint32 all; + struct PCLKCR13_BITS bit; +}; + +struct PCLKCR14_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit + Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit + Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit + Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit + Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit + Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit + Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit + Uint16 CMPSS8:1; // 7 CMPSS8 Clock Enable bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR14_REG { + Uint32 all; + struct PCLKCR14_BITS bit; +}; + +struct PCLKCR16_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C Clock Enable Bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union PCLKCR16_REG { + Uint32 all; + struct PCLKCR16_BITS bit; +}; + +struct SECMSEL_BITS { // bits description + Uint16 PF1SEL:2; // 1:0 Secondary Master Select for VBUS32_1 Bridge + Uint16 PF2SEL:2; // 3:2 Secondary Master Select for VBUS32_2 Bridge + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 rsvd2:2; // 7:6 Reserved + Uint16 rsvd3:2; // 9:8 Reserved + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:2; // 13:12 Reserved + Uint16 rsvd6:2; // 15:14 Reserved + Uint16 rsvd7:16; // 31:16 Reserved +}; + +union SECMSEL_REG { + Uint32 all; + struct SECMSEL_BITS bit; +}; + +struct LPMCR_BITS { // bits description + Uint16 LPM:2; // 1:0 Low Power Mode setting + Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting + Uint16 rsvd1:7; // 14:8 Reserved + Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY + Uint16 M0M1MODE:2; // 17:16 Configuration for M0 and M1 mode during HIB + Uint16 rsvd2:13; // 30:18 Reserved + Uint16 IOISODIS:1; // 31 IO Isolation Disable +}; + +union LPMCR_REG { + Uint32 all; + struct LPMCR_BITS bit; +}; + +struct GPIOLPMSEL0_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup + Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup + Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup + Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup + Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup + Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup + Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup + Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup + Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup + Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup + Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup + Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup + Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup + Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup + Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup + Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup + Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup + Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup + Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup + Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup + Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup + Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup + Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup + Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup + Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup + Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup + Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup + Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup + Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup + Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup + Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup + Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup +}; + +union GPIOLPMSEL0_REG { + Uint32 all; + struct GPIOLPMSEL0_BITS bit; +}; + +struct GPIOLPMSEL1_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup + Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup + Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup + Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup + Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup + Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup + Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup + Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup + Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup + Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup + Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup + Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup + Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup + Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup + Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup + Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup + Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup + Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup + Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup + Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup + Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup + Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup + Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup + Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup + Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup + Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup + Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup + Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup + Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup + Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup + Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup + Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup +}; + +union GPIOLPMSEL1_REG { + Uint32 all; + struct GPIOLPMSEL1_BITS bit; +}; + +struct TMR2CLKCTL_BITS { // bits description + Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit + Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union TMR2CLKCTL_REG { + Uint32 all; + struct TMR2CLKCTL_BITS bit; +}; + +struct RESC_BITS { // bits description + Uint16 POR:1; // 0 POR Reset Cause Indication Bit + Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit + Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit + Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit + Uint16 rsvd1:1; // 4 Reserved + Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit + Uint16 HIBRESETn:1; // 6 HIBRESETn Reset Cause Indication Bit + Uint16 rsvd2:1; // 7 Reserved + Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit + Uint16 rsvd3:7; // 15:9 Reserved + Uint16 rsvd4:14; // 29:16 Reserved + Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status + Uint16 TRSTn_pin_status:1; // 31 TRSTn Status +}; + +union RESC_REG { + Uint32 all; + struct RESC_BITS bit; +}; + +struct CPU_SYS_REGS { + union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers + Uint16 rsvd1[4]; // Reserved + Uint32 HIBBOOTMODE; // HIB Boot Mode Register + union IORESTOREADDR_REG IORESTOREADDR; // IORestore() routine Address Register + union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register + Uint16 rsvd2[22]; // Reserved + union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers + union PCLKCR1_REG PCLKCR1; // Peripheral Clock Gating Registers + union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers + union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers + union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers + Uint16 rsvd3[2]; // Reserved + union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers + union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers + union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers + union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers + union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers + union PCLKCR11_REG PCLKCR11; // Peripheral Clock Gating Registers + union PCLKCR12_REG PCLKCR12; // Peripheral Clock Gating Registers + union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers + union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers + Uint16 rsvd4[2]; // Reserved + union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers + Uint16 rsvd5[48]; // Reserved + union SECMSEL_REG SECMSEL; // Secondary Master Select register for common peripherals: Selects between CLA & DMA + union LPMCR_REG LPMCR; // LPM Control Register + union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers + union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers + union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register + Uint16 rsvd6[2]; // Reserved + union RESC_REG RESC; // Reset Cause register +}; + +struct SCSR_BITS { // bits description + Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit + Uint16 WDENINT:1; // 1 WD Interrupt Enable + Uint16 WDINTS:1; // 2 WD Interrupt Status + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union SCSR_REG { + Uint16 all; + struct SCSR_BITS bit; +}; + +struct WDCNTR_BITS { // bits description + Uint16 WDCNTR:8; // 7:0 WD Counter + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union WDCNTR_REG { + Uint16 all; + struct WDCNTR_BITS bit; +}; + +struct WDKEY_BITS { // bits description + Uint16 WDKEY:8; // 7:0 WD KEY + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union WDKEY_REG { + Uint16 all; + struct WDKEY_BITS bit; +}; + +struct WDCR_BITS { // bits description + Uint16 WDPS:3; // 2:0 WD Clock Prescalar + Uint16 WDCHK:3; // 5:3 WD Check Bits + Uint16 WDDIS:1; // 6 WD Disable + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union WDCR_REG { + Uint16 all; + struct WDCR_BITS bit; +}; + +struct WDWCR_BITS { // bits description + Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality + Uint16 FIRSTKEY:1; // 8 First Key Detect Flag + Uint16 rsvd1:7; // 15:9 Reserved +}; + +union WDWCR_REG { + Uint16 all; + struct WDWCR_BITS bit; +}; + +struct WD_REGS { + Uint16 rsvd1[34]; // Reserved + union SCSR_REG SCSR; // System Control & Status Register + union WDCNTR_REG WDCNTR; // Watchdog Counter Register + Uint16 rsvd2; // Reserved + union WDKEY_REG WDKEY; // Watchdog Reset Key Register + Uint16 rsvd3[3]; // Reserved + union WDCR_REG WDCR; // Watchdog Control Register + union WDWCR_REG WDWCR; // Watchdog Windowed Control Register +}; + +struct CLA1TASKSRCSELLOCK_BITS { // bits description + Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit + Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CLA1TASKSRCSELLOCK_REG { + Uint32 all; + struct CLA1TASKSRCSELLOCK_BITS bit; +}; + +struct DMACHSRCSELLOCK_BITS { // bits description + Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit + Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DMACHSRCSELLOCK_REG { + Uint32 all; + struct DMACHSRCSELLOCK_BITS bit; +}; + +struct CLA1TASKSRCSEL1_BITS { // bits description + Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 + Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 + Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 + Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 +}; + +union CLA1TASKSRCSEL1_REG { + Uint32 all; + struct CLA1TASKSRCSEL1_BITS bit; +}; + +struct CLA1TASKSRCSEL2_BITS { // bits description + Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 + Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 + Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 + Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 +}; + +union CLA1TASKSRCSEL2_REG { + Uint32 all; + struct CLA1TASKSRCSEL2_BITS bit; +}; + +struct DMACHSRCSEL1_BITS { // bits description + Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA + Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA + Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA + Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA +}; + +union DMACHSRCSEL1_REG { + Uint32 all; + struct DMACHSRCSEL1_BITS bit; +}; + +struct DMACHSRCSEL2_BITS { // bits description + Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA + Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union DMACHSRCSEL2_REG { + Uint32 all; + struct DMACHSRCSEL2_BITS bit; +}; + +struct DMA_CLA_SRC_SEL_REGS { + union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register + Uint16 rsvd1[2]; // Reserved + union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register + union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 + union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 + Uint16 rsvd2[12]; // Reserved + union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 + union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 +}; + +struct SYNCSELECT_BITS { // bits description + Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 + Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 + Uint16 EPWM10SYNCIN:3; // 8:6 Selects Sync Input Source for EPWM10 + Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 + Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 + Uint16 rsvd1:1; // 15 Reserved + Uint16 rsvd2:11; // 26:16 Reserved + Uint16 SYNCOUT:2; // 28:27 Select Syncout Source + Uint16 rsvd3:3; // 31:29 Reserved +}; + +union SYNCSELECT_REG { + Uint32 all; + struct SYNCSELECT_BITS bit; +}; + +struct ADCSOCOUTSELECT_BITS { // bits description + Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAO + Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAO + Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAO + Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAO + Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAO + Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAO + Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAO + Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAO + Uint16 PWM9SOCAEN:1; // 8 PWM9SOCAEN Enable for ADCSOCAO + Uint16 PWM10SOCAEN:1; // 9 PWM10SOCAEN Enable for ADCSOCAO + Uint16 PWM11SOCAEN:1; // 10 PWM11SOCAEN Enable for ADCSOCAO + Uint16 PWM12SOCAEN:1; // 11 PWM12SOCAEN Enable for ADCSOCAO + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBO + Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBO + Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBO + Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBO + Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBO + Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBO + Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBO + Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBO + Uint16 PWM9SOCBEN:1; // 24 PWM9SOCBEN Enable for ADCSOCBO + Uint16 PWM10SOCBEN:1; // 25 PWM10SOCBEN Enable for ADCSOCBO + Uint16 PWM11SOCBEN:1; // 26 PWM11SOCBEN Enable for ADCSOCBO + Uint16 PWM12SOCBEN:1; // 27 PWM12SOCBEN Enable for ADCSOCBO + Uint16 rsvd2:4; // 31:28 Reserved +}; + +union ADCSOCOUTSELECT_REG { + Uint32 all; + struct ADCSOCOUTSELECT_BITS bit; +}; + +struct SYNCSOCLOCK_BITS { // bits description + Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit + Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYNCSOCLOCK_REG { + Uint32 all; + struct SYNCSOCLOCK_BITS bit; +}; + +struct SYNC_SOC_REGS { + union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register + union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADC (Off Chip) SOC Select Register + union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register +}; + +//--------------------------------------------------------------------------- +// SYSCTRL External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct WD_REGS WdRegs; +extern volatile struct SYNC_SOC_REGS SyncSocRegs; +extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; +extern volatile struct DEV_CFG_REGS DevCfgRegs; +extern volatile struct CLK_CFG_REGS ClkCfgRegs; +extern volatile struct CPU_SYS_REGS CpuSysRegs; +#endif +#ifdef CPU2 +extern volatile struct WD_REGS WdRegs; +extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; +extern volatile struct CLK_CFG_REGS ClkCfgRegs; +extern volatile struct CPU_SYS_REGS CpuSysRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h new file mode 100644 index 0000000000..c33bcc90f2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h @@ -0,0 +1,403 @@ +//########################################################################### +// +// FILE: F2837xD_upp.h +// +// TITLE: UPP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_UPP_H__ +#define __F2837xD_UPP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// UPP Individual Register Bit Definitions: + +struct PERCTL_BITS { // bits description + Uint16 FREE:1; // 0 Emulation control. + Uint16 SOFT:1; // 1 Emulation control. + Uint16 RTEMU:1; // 2 Realtime emulation control. + Uint16 PEREN:1; // 3 Peripheral Enable + Uint16 SOFTRST:1; // 4 Software Reset + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 DMAST:1; // 7 DMA Burst transaction status + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PERCTL_REG { + Uint32 all; + struct PERCTL_BITS bit; +}; + +struct CHCTL_BITS { // bits description + Uint16 MODE:2; // 1:0 Operating mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode + Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode + Uint16 rsvd2:11; // 15:5 Reserved + Uint16 DRA:1; // 16 Data rate + Uint16 rsvd3:14; // 30:17 Reserved + Uint16 rsvd4:1; // 31 Reserved +}; + +union CHCTL_REG { + Uint32 all; + struct CHCTL_BITS bit; +}; + +struct IFCFG_BITS { // bits description + Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal + Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal + Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal. + Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal + Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal + Uint16 WAITA:1; // 5 Enable Usage of WAIT signal + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode + Uint16 CLKINVA:1; // 12 Clock inversion + Uint16 TRISENA:1; // 13 Pin Tri-state Control + Uint16 rsvd2:2; // 15:14 Reserved + Uint16 rsvd3:6; // 21:16 Reserved + Uint16 rsvd4:2; // 23:22 Reserved + Uint16 rsvd5:6; // 29:24 Reserved + Uint16 rsvd6:2; // 31:30 Reserved +}; + +union IFCFG_REG { + Uint32 all; + struct IFCFG_BITS bit; +}; + +struct IFIVAL_BITS { // bits description + Uint16 VALA:9; // 8:0 Idle Value + Uint16 rsvd1:7; // 15:9 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union IFIVAL_REG { + Uint32 all; + struct IFIVAL_BITS bit; +}; + +struct THCFG_BITS { // bits description + Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value + Uint16 rsvd3:6; // 23:18 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:6; // 31:26 Reserved +}; + +union THCFG_REG { + Uint32 all; + struct THCFG_BITS bit; +}; + +struct RAWINTST_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error + Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition + Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union RAWINTST_REG { + Uint32 all; + struct RAWINTST_BITS bit; +}; + +struct ENINTST_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error + Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition + Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union ENINTST_REG { + Uint32 all; + struct ENINTST_BITS bit; +}; + +struct INTENSET_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error + Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition + Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union INTENSET_REG { + Uint32 all; + struct INTENSET_BITS bit; +}; + +struct INTENCLR_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error + Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition + Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union INTENCLR_REG { + Uint32 all; + struct INTENCLR_BITS bit; +}; + +struct CHIDESC1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer. + Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer. +}; + +union CHIDESC1_REG { + Uint32 all; + struct CHIDESC1_BITS bit; +}; + +struct CHIDESC2_BITS { // bits description + Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union CHIDESC2_REG { + Uint32 all; + struct CHIDESC2_BITS bit; +}; + +struct CHIST1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Current byte number. + Uint16 LCNT:16; // 31:16 Current line number. +}; + +union CHIST1_REG { + Uint32 all; + struct CHIST1_BITS bit; +}; + +struct CHIST2_BITS { // bits description + Uint16 ACT:1; // 0 Status of DMA descriptor. + Uint16 PEND:1; // 1 Status of DMA. + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer. + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CHIST2_REG { + Uint32 all; + struct CHIST2_BITS bit; +}; + +struct CHQDESC1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer. + Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer. +}; + +union CHQDESC1_REG { + Uint32 all; + struct CHQDESC1_BITS bit; +}; + +struct CHQDESC2_BITS { // bits description + Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union CHQDESC2_REG { + Uint32 all; + struct CHQDESC2_BITS bit; +}; + +struct CHQST1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Current byte number. + Uint16 LCNT:16; // 31:16 Current line number. +}; + +union CHQST1_REG { + Uint32 all; + struct CHQST1_BITS bit; +}; + +struct CHQST2_BITS { // bits description + Uint16 ACT:1; // 0 Status of DMA descriptor. + Uint16 PEND:1; // 1 Status of DMA. + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer. + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CHQST2_REG { + Uint32 all; + struct CHQST2_BITS bit; +}; + +struct GINTEN_BITS { // bits description + Uint16 GINTEN:1; // 0 Global Interrupt Enable + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTEN_REG { + Uint32 all; + struct GINTEN_BITS bit; +}; + +struct GINTFLG_BITS { // bits description + Uint16 GINTFLG:1; // 0 Global Interrupt Flag + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTFLG_REG { + Uint32 all; + struct GINTFLG_BITS bit; +}; + +struct GINTCLR_BITS { // bits description + Uint16 GINTCLR:1; // 0 Global Interrupt Clear + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTCLR_REG { + Uint32 all; + struct GINTCLR_BITS bit; +}; + +struct DLYCTL_BITS { // bits description + Uint16 DLYDIS:1; // 0 IO dealy control disable. + Uint16 DLYCTL:2; // 2:1 IO delay control. + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DLYCTL_REG { + Uint32 all; + struct DLYCTL_BITS bit; +}; + +struct UPP_REGS { + Uint32 PID; // Peripheral ID Register + union PERCTL_REG PERCTL; // Peripheral Control Register + Uint16 rsvd1[4]; // Reserved + union CHCTL_REG CHCTL; // General Control Register + union IFCFG_REG IFCFG; // Interface Configuration Register + union IFIVAL_REG IFIVAL; // Interface Idle Value Register + union THCFG_REG THCFG; // Threshold Configuration Register + union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register + union ENINTST_REG ENINTST; // Enable Interrupt Status Register + union INTENSET_REG INTENSET; // Interrupt Enable Set Register + union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register + Uint16 rsvd2[8]; // Reserved + Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register + union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register + union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register + Uint16 rsvd3[2]; // Reserved + Uint32 CHIST0; // DMA Channel I Status 0 Register + union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register + union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register + Uint16 rsvd4[2]; // Reserved + Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register + union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register + union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register + Uint16 rsvd5[2]; // Reserved + Uint32 CHQST0; // DMA Channel Q Status 0 Register + union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register + union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register + Uint16 rsvd6[2]; // Reserved + union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register + union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register + union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register + union DLYCTL_REG DLYCTL; // IO clock data skew control Register +}; + +//--------------------------------------------------------------------------- +// UPP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct UPP_REGS UppRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h new file mode 100644 index 0000000000..d201fda67c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h @@ -0,0 +1,303 @@ +//########################################################################### +// +// FILE: F2837xD_xbar.h +// +// TITLE: XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_XBAR_H__ +#define __F2837xD_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// XBAR Individual Register Bit Definitions: + +struct XBARFLG1_BITS { // bits description + Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal + Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal + Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal + Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal + Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal + Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal + Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal + Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal + Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal + Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal + Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal + Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal + Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal + Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal + Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal + Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal + Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal + Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal + Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal + Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal + Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal + Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal + Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal + Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal + Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal + Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal + Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal + Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal + Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal + Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal + Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal + Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal +}; + +union XBARFLG1_REG { + Uint32 all; + struct XBARFLG1_BITS bit; +}; + +struct XBARFLG2_BITS { // bits description + Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal + Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal + Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal + Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal + Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal + Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal + Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal + Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 rsvd3:1; // 10 Reserved + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal + Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal + Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal + Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal + Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal + Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal + Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal + Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal + Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal + Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal + Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal + Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal + Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal + Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal + Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal + Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal +}; + +union XBARFLG2_REG { + Uint32 all; + struct XBARFLG2_BITS bit; +}; + +struct XBARFLG3_BITS { // bits description + Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal + Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal + Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal + Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal + Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal + Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal + Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal + Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal + Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal + Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal + Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal + Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal + Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal + Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal + Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal + Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal + Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal + Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal + Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal + Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal + Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal + Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal + Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal + Uint16 rsvd1:9; // 31:23 Reserved +}; + +union XBARFLG3_REG { + Uint32 all; + struct XBARFLG3_BITS bit; +}; + +struct XBARCLR1_BITS { // bits description + Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal + Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal + Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal + Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal + Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal + Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal + Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal + Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal + Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal + Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal + Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal + Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal + Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal + Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal + Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal + Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal + Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal + Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal + Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal + Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal + Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal + Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal + Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal + Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal + Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal + Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal + Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal + Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal + Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal + Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal + Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal + Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal +}; + +union XBARCLR1_REG { + Uint32 all; + struct XBARCLR1_BITS bit; +}; + +struct XBARCLR2_BITS { // bits description + Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal + Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal + Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal + Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal + Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal + Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal + Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal + Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 rsvd3:1; // 10 Reserved + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal + Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal + Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal + Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal + Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal + Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal + Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal + Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal + Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal + Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal + Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal + Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal + Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal + Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal + Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal + Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal +}; + +union XBARCLR2_REG { + Uint32 all; + struct XBARCLR2_BITS bit; +}; + +struct XBARCLR3_BITS { // bits description + Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal + Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal + Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal + Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal + Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal + Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal + Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal + Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal + Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal + Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal + Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal + Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal + Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal + Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal + Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal + Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal + Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal + Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal + Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal + Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal + Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal + Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal + Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal + Uint16 rsvd1:9; // 31:23 Reserved +}; + +union XBARCLR3_REG { + Uint32 all; + struct XBARCLR3_BITS bit; +}; + +struct XBAR_REGS { + union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 + union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 + union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 + Uint16 rsvd1[2]; // Reserved + union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 + union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 + union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 + Uint16 rsvd2[18]; // Reserved +}; + +//--------------------------------------------------------------------------- +// XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct XBAR_REGS XbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h new file mode 100644 index 0000000000..f647e68b06 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h @@ -0,0 +1,143 @@ +//########################################################################### +// +// FILE: F2837xD_xint.h +// +// TITLE: XINT Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_XINT_H__ +#define __F2837xD_XINT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// XINT Individual Register Bit Definitions: + +struct XINT1CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT1 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT1 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT1CR_REG { + Uint16 all; + struct XINT1CR_BITS bit; +}; + +struct XINT2CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT2 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT2 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT2CR_REG { + Uint16 all; + struct XINT2CR_BITS bit; +}; + +struct XINT3CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT3 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT3 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT3CR_REG { + Uint16 all; + struct XINT3CR_BITS bit; +}; + +struct XINT4CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT4 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT4 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT4CR_REG { + Uint16 all; + struct XINT4CR_BITS bit; +}; + +struct XINT5CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT5 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT5 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT5CR_REG { + Uint16 all; + struct XINT5CR_BITS bit; +}; + +struct XINT_REGS { + union XINT1CR_REG XINT1CR; // XINT1 configuration register + union XINT2CR_REG XINT2CR; // XINT2 configuration register + union XINT3CR_REG XINT3CR; // XINT3 configuration register + union XINT4CR_REG XINT4CR; // XINT4 configuration register + union XINT5CR_REG XINT5CR; // XINT5 configuration register + Uint16 rsvd1[3]; // Reserved + Uint16 XINT1CTR; // XINT1 counter register + Uint16 XINT2CTR; // XINT2 counter register + Uint16 XINT3CTR; // XINT3 counter register +}; + +//--------------------------------------------------------------------------- +// XINT External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct XINT_REGS XintRegs; +#endif +#ifdef CPU2 +extern volatile struct XINT_REGS XintRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c b/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c new file mode 100644 index 0000000000..270b63815a --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c @@ -0,0 +1,876 @@ +//########################################################################### +// +// FILE: F2837xD_GlobalVariableDefs.c +// +// TITLE: F2837xD Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" // F2837xD Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaRegsFile") +#else +#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); +#endif +volatile struct ADC_REGS AdcaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbRegsFile") +#else +#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); +#endif +volatile struct ADC_REGS AdcbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdccRegsFile") +#else +#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); +#endif +volatile struct ADC_REGS AdccRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdRegsFile") +#else +#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile"); +#endif +volatile struct ADC_REGS AdcdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaResultFile") +#else +#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcaResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbResultFile") +#else +#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcbResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccResultFile") +#else +#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdccResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdResultFile") +#else +#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcdResultRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("AnalogSubsysRegsFile") +#else +#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); +#endif +volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif + +#if __TI_COMPILER_VERSION__ >= 16006000 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanaRegsFile") +#else +#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); +#endif +volatile struct CAN_REGS CanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanbRegsFile") +#else +#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); +#endif +volatile struct CAN_REGS CanbRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss1RegsFile") +#else +#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss2RegsFile") +#else +#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss3RegsFile") +#else +#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss4RegsFile") +#else +#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss5RegsFile") +#else +#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss6RegsFile") +#else +#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss7RegsFile") +#else +#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss8RegsFile") +#else +#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacaRegsFile") +#else +#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); +#endif +volatile struct DAC_REGS DacaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacbRegsFile") +#else +#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); +#endif +volatile struct DAC_REGS DacbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DaccRegsFile") +#else +#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); +#endif +volatile struct DAC_REGS DaccRegs; +//---------------------------------------- + +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1RegsFile") +#else +#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); +#endif +volatile struct CLA_REGS Cla1Regs; +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1SoftIntRegsFile") +#else +#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); +#endif +volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClkCfgRegsFile") +#else +#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); +#endif +volatile struct CLK_CFG_REGS ClkCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuSysRegsFile") +#else +#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); +#endif +volatile struct CPU_SYS_REGS CpuSysRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1RegsFile") +#else +#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); +#endif +volatile struct DCSM_Z1_REGS DcsmZ1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2RegsFile") +#else +#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); +#endif +volatile struct DCSM_Z2_REGS DcsmZ2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmCommonRegsFile") +#else +#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); +#endif +volatile struct DCSM_COMMON_REGS DcsmCommonRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaClaSrcSelRegsFile") +#else +#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); +#endif +volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("DevCfgRegsFile") +#else +#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); +#endif +volatile struct DEV_CFG_REGS DevCfgRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1RegsFile") +#else +#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); +#endif +volatile struct EMIF_REGS Emif1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2RegsFile") +#else +#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); +#endif +volatile struct EMIF_REGS Emif2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep3RegsFile") +#else +#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); +#endif +volatile struct EQEP_REGS EQep3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm7RegsFile") +#else +#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); +#endif +volatile struct EPWM_REGS EPwm7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm8RegsFile") +#else +#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); +#endif +volatile struct EPWM_REGS EPwm8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm9RegsFile") +#else +#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); +#endif +volatile struct EPWM_REGS EPwm9Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm10RegsFile") +#else +#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); +#endif +volatile struct EPWM_REGS EPwm10Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm11RegsFile") +#else +#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); +#endif +volatile struct EPWM_REGS EPwm11Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm12RegsFile") +#else +#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); +#endif +volatile struct EPWM_REGS EPwm12Regs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("EPwmXbarRegsFile") +#else +#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); +#endif +volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("InputXbarRegsFile") +#else +#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("XbarRegsFile") +#else +#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); +#endif +volatile struct XBAR_REGS XbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("OutputXbarRegsFile") +#else +#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2cbRegsFile") +#else +#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); +#endif +volatile struct I2C_REGS I2cbRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU1 IpcRegs; +#endif + +//---------------------------------------- +#ifdef CPU2 +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU2 IpcRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +#endif + +//---------------------------------------- +#ifdef CPU2 +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct McBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("RomPrefetchRegsFile") +#else +#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); +#endif +volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemCfgRegsFile") +#else +#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); +#endif +volatile struct MEM_CFG_REGS MemCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); +#endif +volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); +#endif +volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("RomWaitStateRegsFile") +#else +#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); +#endif +volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AccessProtectionRegsFile") +#else +#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); +#endif +volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemoryErrorRegsFile") +#else +#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); +#endif +volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct McBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("NmiIntruptRegsFile") +#else +#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); +#endif +volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScidRegsFile") +#else +#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); +#endif +volatile struct SCI_REGS ScidRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpibRegsFile") +#else +#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); +#endif +volatile struct SPI_REGS SpibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpicRegsFile") +#else +#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); +#endif +volatile struct SPI_REGS SpicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm1RegsFile") +#else +#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm2RegsFile") +#else +#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm2Regs; + + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("SyncSocRegsFile") +#else +#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); +#endif +volatile struct SYNC_SOC_REGS SyncSocRegs; +#endif + +//---------------------------------------- +#if defined(CPU1) +#ifdef __cplusplus +#pragma DATA_SECTION("UppRegsFile") +#else +#pragma DATA_SECTION(UppRegs,"UppRegsFile"); +#endif +volatile struct UPP_REGS UppRegs; +#endif //defined(CPU1) + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("WdRegsFile") +#else +#pragma DATA_SECTION(WdRegs,"WdRegsFile"); +#endif +volatile struct WD_REGS WdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintRegsFile") +#else +#pragma DATA_SECTION(XintRegs,"XintRegsFile"); +#endif +volatile struct XINT_REGS XintRegs; + +//-------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EmuBModeVar"); +#else +#pragma DATA_SECTION(EmuBMode,"EmuBModeVar"); +#endif +Uint16 EmuBMode; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("EmuBootPinsVar"); +#else +#pragma DATA_SECTION(EmuBootPins,"EmuBootPinsVar"); +#endif +Uint16 EmuBootPins; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0EccRegsFile") +#else +#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); +#endif +volatile struct FLASH_ECC_REGS Flash0EccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0CtrlRegsFile") +#else +#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); +#endif +volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; + + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/bsp/tms320f28379d/rtconfig.h b/bsp/tms320f28379d/rtconfig.h new file mode 100644 index 0000000000..f74783569c --- /dev/null +++ b/bsp/tms320f28379d/rtconfig.h @@ -0,0 +1,147 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_TMS320F28X + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_8 +#define RT_THREAD_PRIORITY_MAX 8 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define ARCH_TIDSP +#define ARCH_TIDSP_C28X +#define ARCH_CPU_STACK_GROWS_UPWARD + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT + +/* C++ features */ + + +/* Command shell */ + + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + + +#endif diff --git a/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml b/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml new file mode 100644 index 0000000000..42eb492f1f --- /dev/null +++ b/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/targetConfigs/readme.txt b/bsp/tms320f28379d/targetConfigs/readme.txt new file mode 100644 index 0000000000..d783fef4d6 --- /dev/null +++ b/bsp/tms320f28379d/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/bsp/x1000/drivers/mmc/drv_mmc.c b/bsp/x1000/drivers/mmc/drv_mmc.c index 137c53ad92..c2fa538fbc 100644 --- a/bsp/x1000/drivers/mmc/drv_mmc.c +++ b/bsp/x1000/drivers/mmc/drv_mmc.c @@ -107,7 +107,7 @@ static inline int check_error_status(struct jzmmc_host *host, unsigned int statu { if (status & ERROR_STAT) { - dbg_log(DBG_LOG, "Error status->0x%08X: cmd=%d\n", status, host->cmd->cmd_code); + LOG_D("Error status->0x%08X: cmd=%d", status, host->cmd->cmd_code); return -1; } return 0; @@ -160,16 +160,16 @@ static int jzmmc_polling_status(struct jzmmc_host *host, unsigned int status) if (!cnt) { - dbg_log(DBG_LOG, "polling status(0x%08X) time out, " - "op=%d, status=0x%08X\n", status, + LOG_D("polling status(0x%08X) time out, " + "op=%d, status=0x%08X", status, host->cmd->cmd_code, msc_readl(host, MSC_STAT_OFFSET)); return -1; } if (msc_readl(host, MSC_STAT_OFFSET) & ERROR_STAT) { - dbg_log(DBG_LOG, "polling status(0x%08X) error, " - "op=%d, status=0x%08X\n", status, + LOG_D("polling status(0x%08X) error, " + "op=%d, status=0x%08X", status, host->cmd->cmd_code, msc_readl(host, MSC_STAT_OFFSET)); return -1; } @@ -220,7 +220,7 @@ static void jzmmc_command_done(struct jzmmc_host *host, struct rt_mmcsd_cmd *cmd cmd->resp[0] |= res & 0xff; } - dbg_log(DBG_LOG, "error:%d cmd->resp [%08X, %08X, %08X, %08X]\r\n\r\n", + LOG_D("error:%d cmd->resp [%08X, %08X, %08X, %08X]\r\n\r", cmd->err, cmd->resp[0], cmd->resp[1], @@ -244,7 +244,7 @@ static void jzmmc_data_done(struct jzmmc_host *host) { jzmmc_stop_dma(host); data->bytes_xfered = 0; - dbg_log(DBG_LOG, "error when request done\n"); + LOG_D("error when request done"); } } @@ -288,11 +288,11 @@ rt_inline void jzmmc_submit_dma(struct jzmmc_host *host, struct rt_mmcsd_data *d host->dma_desc.da = virt_to_phys(host->_dma_buffer); if (data->flags & DATA_DIR_WRITE) { - dbg_log(DBG_LOG, "%d ->", data->blks * data->blksize); + LOG_D("%d ->", data->blks * data->blksize); memcpy(host->_dma_buffer, data->buf, data->blks * data->blksize); rt_hw_dcache_flush_range((rt_ubase_t)(host->_dma_buffer), data->blks * data->blksize); - dbg_log(DBG_LOG, "| 0x%08x\n", data->buf); + LOG_D("| 0x%08x", data->buf); } } else @@ -322,7 +322,7 @@ rt_inline void jzmmc_dma_start(struct jzmmc_host *host, struct rt_mmcsd_data *da #ifndef DMA_BUFFER if ((dma_addr & (DMA_ALIGN - 1)) || (dma_len & (DMA_ALIGN - 1))) { - dbg_log(DBG_LOG, "DMA align, addr=0x%08x\n", dma_addr); + LOG_D("DMA align, addr=0x%08x", dma_addr); dmac |= DMAC_ALIGNEN; if (dma_addr & (DMA_ALIGN - 1)) { @@ -330,7 +330,7 @@ rt_inline void jzmmc_dma_start(struct jzmmc_host *host, struct rt_mmcsd_data *da } } #endif - dbg_log(DBG_LOG, "DMA start: nda 0x%08x, da 0x%08x, len 0x%04x, cmd 0x%08x\n", virt_to_phys(&(host->dma_desc)), + LOG_D("DMA start: nda 0x%08x, da 0x%08x, len 0x%04x, cmd 0x%08x", virt_to_phys(&(host->dma_desc)), host->dma_desc.da, host->dma_desc.len, host->dma_desc.dcmd); rt_hw_dcache_flush_range((rt_ubase_t)(&(host->dma_desc)), 32); @@ -366,19 +366,19 @@ static int wait_cmd_response(struct jzmmc_host *host) if(ret == RT_EOK) { - dbg_log(DBG_LOG, "wait response OK!\r\n"); + LOG_D("wait response OK!\r"); } else { uint32_t value; value = msc_readl(host, MSC_STAT_OFFSET); - dbg_log(DBG_LOG, "stat=0x%08x\n", value); + LOG_D("stat=0x%08x", value); value = msc_readl(host, MSC_IREG_OFFSET); - dbg_log(DBG_LOG, "iflag=0x%08x\n", value); + LOG_D("iflag=0x%08x", value); host->cmd->err = ret; - dbg_log(DBG_LOG, "wait END_CMD_RES timeout[uncompletion]\r\n"); + LOG_D("wait END_CMD_RES timeout[uncompletion]\r"); return -1; } @@ -570,7 +570,7 @@ static void jzmmc_data_start(struct jzmmc_host *host, struct rt_mmcsd_data *data } else { - dbg_log(DBG_LOG, "msc status: 0x%08x\n", msc_readl(host, MSC_STAT_OFFSET)); + LOG_D("msc status: 0x%08x", msc_readl(host, MSC_STAT_OFFSET)); clear_msc_irq(host, IFLG_DATA_TRAN_DONE | IFLG_DMAEND | IFLG_DMA_DATA_DONE | IFLG_TIMEOUT_RES); disable_msc_irq(host, IMASK_DMA_DATA_DONE | IMASK_CRC_READ_ERR); @@ -582,7 +582,7 @@ static void jzmmc_data_start(struct jzmmc_host *host, struct rt_mmcsd_data *data { rt_hw_dcache_invalidate_range((rt_ubase_t)(host->_dma_buffer), data->blks * data->blksize); memcpy(data->buf, host->_dma_buffer, data->blks * data->blksize); - dbg_log(DBG_LOG, "0x%08x <-| %d\n", data->buf, data->blks * data->blksize); + LOG_D("0x%08x <-| %d", data->buf, data->blks * data->blksize); } else { @@ -630,8 +630,8 @@ static void jzmmc_command_start(struct jzmmc_host *host, struct rt_mmcsd_cmd *cm enable_msc_irq(host, imsk); } - dbg_log(DBG_LOG, "dat: 0x%08x\n", host->cmdat); - dbg_log(DBG_LOG, "resp type: %d\n", cmd->flags & RESP_MASK); + LOG_D("dat: 0x%08x", host->cmdat); + LOG_D("resp type: %d", cmd->flags & RESP_MASK); writel(0xFF, host->hw_base + MSC_RESTO_OFFSET); writel(0xFFFFFFFF, host->hw_base + MSC_RDTO_OFFSET); @@ -661,7 +661,7 @@ static void jzmmc_sdio_request(struct rt_mmcsd_host *mmc, struct rt_mmcsd_req *r host->cmd = req->cmd; host->cmdat = 0; - dbg_log(DBG_LOG, "CMD: %d ARG: %08X\n", req->cmd->cmd_code, req->cmd->arg); + LOG_D("CMD: %d ARG: %08X", req->cmd->cmd_code, req->cmd->arg); if (host->data) { direction = (host->data->flags & DATA_DIR_WRITE)? 'w' : 'r'; @@ -688,10 +688,10 @@ static void jzmmc_sdio_request(struct rt_mmcsd_host *mmc, struct rt_mmcsd_req *r if(host->data) { - dbg_log(DBG_LOG, "with data, datalen = %d\n", host->data->blksize * host->data->blks); + LOG_D("with data, datalen = %d", host->data->blksize * host->data->blks); if (host->data->blksize * host->data->blks < PIO_THRESHOLD) { - dbg_log(DBG_LOG, " pio mode!\n"); + LOG_D(" pio mode!"); enable_pio_mode(host); } @@ -726,36 +726,36 @@ static void jzmmc_isr(int irqno, void* param) if(pending_ & IFLG_CRC_RES_ERR) { - dbg_log(DBG_WARNING, "RES CRC err\n"); + LOG_W("RES CRC err"); } if(pending_ & IFLG_CRC_READ_ERR) { - dbg_log(DBG_WARNING, "READ CRC err\n"); + LOG_W("READ CRC err"); } if(pending_ & IFLG_CRC_WRITE_ERR) { - dbg_log(DBG_WARNING, "WRITE CRC err\n"); + LOG_W("WRITE CRC err"); } if (pending & IFLG_TIMEOUT_RES) { host->cmd->err = -RT_ETIMEOUT; - dbg_log(DBG_LOG, "TIMEOUT\n"); + LOG_D("TIMEOUT"); } else if (pending & IFLG_CRC_READ_ERR) { host->cmd->err = -RT_EIO; - dbg_log(DBG_WARNING, "CRC READ\n"); + LOG_W("CRC READ"); } else if (pending & (IFLG_CRC_RES_ERR | IFLG_CRC_WRITE_ERR | IFLG_TIMEOUT_READ)) { - dbg_log(DBG_ERROR, "MSC ERROR, pending=0x%08x\n", pending); + LOG_E("MSC ERROR, pending=0x%08x", pending); } if (pending & (IFLG_DMA_DATA_DONE | IFLG_WR_ALL_DONE)) { - dbg_log(DBG_LOG, "msc DMA end!\n"); + LOG_D("msc DMA end!"); /* disable interrupt */ rt_hw_interrupt_mask(host->irqno); @@ -823,17 +823,17 @@ static void jzmmc_sdio_set_iocfg(struct rt_mmcsd_host *host, struct jzmmc_host * jz_sdio = host->private_data; rt_uint32_t clkdiv; - dbg_log(DBG_LOG, "set_iocfg clock: %d\n", io_cfg->clock); + LOG_D("set_iocfg clock: %d", io_cfg->clock); if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) { - dbg_log(DBG_LOG, "MMC: Setting controller bus width to 4\n"); + LOG_D("MMC: Setting controller bus width to 4"); jz_sdio->flags |= MSC_CMDAT_BUS_WIDTH_4BIT; } else { jz_sdio->flags &= ~(MSC_CMDAT_BUS_WIDTH_4BIT); - dbg_log(DBG_LOG, "MMC: Setting controller bus width to 1\n"); + LOG_D("MMC: Setting controller bus width to 1"); } if (io_cfg->clock) @@ -866,16 +866,16 @@ static void jzmmc_sdio_set_iocfg(struct rt_mmcsd_host *host, if (clkrt > 7) { - dbg_log(DBG_ERROR, "invalid value of CLKRT: " + LOG_E("invalid value of CLKRT: " "ios->clock=%d clk_want=%d " - "clk_set=%d clkrt=%X,\n", + "clk_set=%d clkrt=%X,", io_cfg->clock, clk_want, clk_set, clkrt); return; } if (!clkrt) { - dbg_log(DBG_LOG, "clk_want: %u, clk_set: %luHz\n", io_cfg->clock, clk_get_rate(jz_sdio->clock)); + LOG_D("clk_want: %u, clk_set: %luHz", io_cfg->clock, clk_get_rate(jz_sdio->clock)); } writel(clkrt, jz_sdio->hw_base + MSC_CLKRT_OFFSET); @@ -905,25 +905,25 @@ static void jzmmc_sdio_set_iocfg(struct rt_mmcsd_host *host, switch (io_cfg->power_mode) { case MMCSD_POWER_OFF: - dbg_log(DBG_LOG, "MMCSD_POWER_OFF\r\n"); + LOG_D("MMCSD_POWER_OFF\r"); break; case MMCSD_POWER_UP: - dbg_log(DBG_LOG, "MMCSD_POWER_UP\r\n"); + LOG_D("MMCSD_POWER_UP\r"); break; case MMCSD_POWER_ON: - dbg_log(DBG_LOG, "MMCSD_POWER_ON\r\n"); + LOG_D("MMCSD_POWER_ON\r"); jzmmc_hardware_init(jz_sdio); // jz_mmc_set_clock(jz_sdio, io_cfg->clock); break; default: - dbg_log(DBG_LOG, "unknown power_mode %d\n", io_cfg->power_mode); + LOG_D("unknown power_mode %d", io_cfg->power_mode); break; } } static rt_int32_t jzmmc_sdio_detect(struct rt_mmcsd_host *host) { - dbg_log(DBG_LOG, "jz47xx_SD_Detect\n"); + LOG_D("jz47xx_SD_Detect"); return 0; } @@ -931,7 +931,7 @@ static rt_int32_t jzmmc_sdio_detect(struct rt_mmcsd_host *host) static void jzmmc_sdio_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - dbg_log(DBG_LOG, "jz47xx_sdio_enable_sdio_irq, enable:%d\n", enable); + LOG_D("jz47xx_sdio_enable_sdio_irq, enable:%d", enable); } static const struct rt_mmcsd_host_ops ops = diff --git a/bsp/x86/Makefile b/bsp/x86/Makefile index cdb4f4ca8c..eb4654193b 100644 --- a/bsp/x86/Makefile +++ b/bsp/x86/Makefile @@ -7,7 +7,7 @@ all: rtthread rtsym exe dll floppy.img @sudo mount -t vfat floppy.img tmp -o loop @sudo cp -fv rtthread.elf tmp/boot/oskernel @sudo rm tmp/bin/* -fr - @sudo cp out/* tmp/bin/ -fv + @sudo cp out/*.mo tmp/bin/ -fv @sudo umount tmp rtthread: @@ -23,7 +23,8 @@ out: mkdir -p out dll: obj out - $(CC) -shared -s -fPIC -e main -Isrc src/hello.c -o out/hello.mo + $(CC) -c -fPIC -Isrc src/hello.c -o out/hello.o + $(CC) -s -Wl,-shared,-melf_i386,--entry=main -o out/hello.mo out/hello.o disasm: obj out $(CC) -shared -S -fPIC -Isrc src/hello.c -o obj/hello.s diff --git a/bsp/x86/applications/application.c b/bsp/x86/applications/application.c index 2eb4e9b8ba..8928e6357e 100644 --- a/bsp/x86/applications/application.c +++ b/bsp/x86/applications/application.c @@ -48,7 +48,7 @@ void components_init(void) #endif #ifdef RT_USING_MODULE - rt_system_module_init(); + rt_system_dlmodule_init(); #endif #endif } diff --git a/bsp/x86/drivers/board.c b/bsp/x86/drivers/board.c index 4d91604ab3..211ae1832a 100644 --- a/bsp/x86/drivers/board.c +++ b/bsp/x86/drivers/board.c @@ -71,12 +71,4 @@ void reboot(void) } FINSH_FUNCTION_EXPORT(reboot, reboot PC) #endif -#ifdef RT_USING_DFS -#include -time_t time(time_t* tm) -{ - (void)tm; - return 0; -} -#endif /*@}*/ diff --git a/bsp/x86/rtconfig.h b/bsp/x86/rtconfig.h index 4ca8423a66..2878f811d0 100644 --- a/bsp/x86/rtconfig.h +++ b/bsp/x86/rtconfig.h @@ -175,7 +175,5 @@ /* #define RTGUI_IMAGE_XPM */ /* #define RTGUI_IMAGE_BMP */ -#define RT_USING_LIBDL -#define RT_USING_MODULE -#define MODULE_USING_386 +// #define RT_USING_MODULE #endif diff --git a/components/Kconfig b/components/Kconfig index c221f12df3..327489910b 100644 --- a/components/Kconfig +++ b/components/Kconfig @@ -31,8 +31,6 @@ source "$RTT_DIR/components/drivers/Kconfig" source "$RTT_DIR/components/libc/Kconfig" -source "$RTT_DIR/components/lwp/Kconfig" - source "$RTT_DIR/components/net/Kconfig" source "$RTT_DIR/components/vbus/Kconfig" diff --git a/components/cplusplus/Lock.h b/components/cplusplus/Lock.h index 2d8cbe5895..08d57c4850 100644 --- a/components/cplusplus/Lock.h +++ b/components/cplusplus/Lock.h @@ -1,21 +1,7 @@ /* - * File : Lock.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/cplusplus/Mail.h b/components/cplusplus/Mail.h index c812aa0bd7..e6b11af9e8 100644 --- a/components/cplusplus/Mail.h +++ b/components/cplusplus/Mail.h @@ -1,21 +1,7 @@ /* - * File : Mail.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/cplusplus/Mutex.cpp b/components/cplusplus/Mutex.cpp index c8dbbe6598..229e842446 100644 --- a/components/cplusplus/Mutex.cpp +++ b/components/cplusplus/Mutex.cpp @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "Mutex.h" using namespace rtthread; diff --git a/components/cplusplus/Mutex.h b/components/cplusplus/Mutex.h index b4109751e5..4a54c41ebb 100644 --- a/components/cplusplus/Mutex.h +++ b/components/cplusplus/Mutex.h @@ -1,21 +1,7 @@ /* - * File : Mutex.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/cplusplus/Queue.h b/components/cplusplus/Queue.h index b011dd5d28..fba64bf51b 100644 --- a/components/cplusplus/Queue.h +++ b/components/cplusplus/Queue.h @@ -1,21 +1,7 @@ /* - * File : Queue.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/cplusplus/Semaphore.cpp b/components/cplusplus/Semaphore.cpp index 2579bcb041..c977a27c1a 100644 --- a/components/cplusplus/Semaphore.cpp +++ b/components/cplusplus/Semaphore.cpp @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "Semaphore.h" using namespace rtthread; diff --git a/components/cplusplus/Semaphore.h b/components/cplusplus/Semaphore.h index 6c09b198c6..cebaf91234 100644 --- a/components/cplusplus/Semaphore.h +++ b/components/cplusplus/Semaphore.h @@ -1,21 +1,7 @@ /* - * File : Semaphore.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/cplusplus/Thread.cpp b/components/cplusplus/Thread.cpp index a01bd95e4b..0f6315d178 100644 --- a/components/cplusplus/Thread.cpp +++ b/components/cplusplus/Thread.cpp @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "Thread.h" using namespace rtthread; diff --git a/components/cplusplus/Thread.h b/components/cplusplus/Thread.h index 78bbd77d1f..9b6cf30884 100644 --- a/components/cplusplus/Thread.h +++ b/components/cplusplus/Thread.h @@ -1,21 +1,7 @@ /* - * File : Thread.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/cplusplus/crt.cpp b/components/cplusplus/crt.cpp index b6455f73f4..cac1e5fa57 100644 --- a/components/cplusplus/crt.cpp +++ b/components/cplusplus/crt.cpp @@ -1,22 +1,8 @@ /* -* File : crt.cpp -* This file is part of Device File System in RT-Thread RTOS -* COPYRIGHT (C) 2008-2015, RT-Thread Development Team -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-03-07 Bernard Add copyright header. diff --git a/components/cplusplus/crt.h b/components/cplusplus/crt.h index 105aa0e4fc..6228dab2a9 100644 --- a/components/cplusplus/crt.h +++ b/components/cplusplus/crt.h @@ -1,22 +1,8 @@ /* -* File : crt.h -* This file is part of Device File System in RT-Thread RTOS -* COPYRIGHT (C) 2008-2015, RT-Thread Development Team -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-03-07 Bernard Add copyright header. diff --git a/components/cplusplus/crt_init.c b/components/cplusplus/crt_init.c index 6a05b00de9..e67939feeb 100755 --- a/components/cplusplus/crt_init.c +++ b/components/cplusplus/crt_init.c @@ -1,22 +1,8 @@ /* -* File : crt_init.c -* This file is part of Device File System in RT-Thread RTOS -* COPYRIGHT (C) 2008-2015, RT-Thread Development Team -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2014-12-03 Bernard Add copyright header. @@ -36,11 +22,11 @@ void $Sub$$__cpp_initialize__aeabi_(void) } #elif defined(__GNUC__) && !defined(__CS_SOURCERYGXX_MAJ__) /* The _init()/_fini() routines has been defined in codesourcery g++ lite */ -void _init() +RT_WEAK void _init() { } -void _fini() +RT_WEAK void _fini() { } diff --git a/components/dfs/Kconfig b/components/dfs/Kconfig index 107cee84d3..35c7cf1b02 100644 --- a/components/dfs/Kconfig +++ b/components/dfs/Kconfig @@ -154,7 +154,7 @@ if RT_USING_DFS config RT_USING_DFS_NFS bool "Using NFS v3 client file system" - select RT_USING_LWIP + depends on RT_USING_LWIP default n if RT_USING_DFS_NFS diff --git a/components/dfs/filesystems/devfs/devfs.c b/components/dfs/filesystems/devfs/devfs.c index 4694b96c85..3080312874 100644 --- a/components/dfs/filesystems/devfs/devfs.c +++ b/components/dfs/filesystems/devfs/devfs.c @@ -1,21 +1,7 @@ /* - * File : devfs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/devfs/devfs.h b/components/dfs/filesystems/devfs/devfs.h index ef320b78c8..ab2134043c 100644 --- a/components/dfs/filesystems/devfs/devfs.h +++ b/components/dfs/filesystems/devfs/devfs.h @@ -1,21 +1,7 @@ /* - * File : devfs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/elmfat/dfs_elm.c b/components/dfs/filesystems/elmfat/dfs_elm.c index 2aa8fb6522..290cf7c4bb 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.c +++ b/components/dfs/filesystems/elmfat/dfs_elm.c @@ -1,21 +1,7 @@ /* - * File : dfs_elm.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2008-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/elmfat/dfs_elm.h b/components/dfs/filesystems/elmfat/dfs_elm.h index da8a217005..1e9f577062 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.h +++ b/components/dfs/filesystems/elmfat/dfs_elm.h @@ -1,21 +1,7 @@ /* - * File : dfs_elm.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2008-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/jffs2/dfs_jffs2.c b/components/dfs/filesystems/jffs2/dfs_jffs2.c index 17e84f94c0..c082c21d73 100644 --- a/components/dfs/filesystems/jffs2/dfs_jffs2.c +++ b/components/dfs/filesystems/jffs2/dfs_jffs2.c @@ -1,21 +1,7 @@ /* - * File : dfs_jffs2.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -304,7 +290,7 @@ static int dfs_jffs2_open(struct dfs_fd* file) return jffs2_result_to_dfs(result); } - /* save this pointer, it will be used when calling read()��write(), + /* save this pointer, it will be used when calling read(), write(), flush(), lessk(), and will be rt_free when calling close()*/ file->data = jffs2_file; file->pos = jffs2_file->f_offset; diff --git a/components/dfs/filesystems/jffs2/dfs_jffs2.h b/components/dfs/filesystems/jffs2/dfs_jffs2.h index 2eee076fcb..1be403a19c 100644 --- a/components/dfs/filesystems/jffs2/dfs_jffs2.h +++ b/components/dfs/filesystems/jffs2/dfs_jffs2.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __DFS_JFFS2_H__ #define __DFS_JFFS2_H__ diff --git a/components/dfs/filesystems/nfs/dfs_nfs.c b/components/dfs/filesystems/nfs/dfs_nfs.c index 1324210007..ea055b73c1 100644 --- a/components/dfs/filesystems/nfs/dfs_nfs.c +++ b/components/dfs/filesystems/nfs/dfs_nfs.c @@ -1,21 +1,7 @@ /* - * File : dfs_nfs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/nfs/dfs_nfs.h b/components/dfs/filesystems/nfs/dfs_nfs.h index adc36f82d5..d607776ef1 100644 --- a/components/dfs/filesystems/nfs/dfs_nfs.h +++ b/components/dfs/filesystems/nfs/dfs_nfs.h @@ -1,21 +1,7 @@ /* - * File : dfs_nfs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/nfs/mount.h b/components/dfs/filesystems/nfs/mount.h index 4ce3714f98..aac0fd6bed 100644 --- a/components/dfs/filesystems/nfs/mount.h +++ b/components/dfs/filesystems/nfs/mount.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Please do not edit this file. * It was generated using rpcgen. diff --git a/components/dfs/filesystems/nfs/mount_clnt.c b/components/dfs/filesystems/nfs/mount_clnt.c index 504f1e99ae..5c65e75aa5 100644 --- a/components/dfs/filesystems/nfs/mount_clnt.c +++ b/components/dfs/filesystems/nfs/mount_clnt.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Please do not edit this file. * It was generated using rpcgen. diff --git a/components/dfs/filesystems/nfs/mount_xdr.c b/components/dfs/filesystems/nfs/mount_xdr.c index e4d2b86f47..8e191d3017 100644 --- a/components/dfs/filesystems/nfs/mount_xdr.c +++ b/components/dfs/filesystems/nfs/mount_xdr.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Please do not edit this file. * It was generated using rpcgen. diff --git a/components/dfs/filesystems/nfs/nfs.h b/components/dfs/filesystems/nfs/nfs.h index 7e3e3671af..34054b0084 100644 --- a/components/dfs/filesystems/nfs/nfs.h +++ b/components/dfs/filesystems/nfs/nfs.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Please do not edit this file. * It was generated using rpcgen. diff --git a/components/dfs/filesystems/nfs/nfs_clnt.c b/components/dfs/filesystems/nfs/nfs_clnt.c index 913ad510a6..c17fee9e80 100644 --- a/components/dfs/filesystems/nfs/nfs_clnt.c +++ b/components/dfs/filesystems/nfs/nfs_clnt.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Please do not edit this file. * It was generated using rpcgen. diff --git a/components/dfs/filesystems/nfs/nfs_xdr.c b/components/dfs/filesystems/nfs/nfs_xdr.c index 72d6edc42a..4cd69ba743 100644 --- a/components/dfs/filesystems/nfs/nfs_xdr.c +++ b/components/dfs/filesystems/nfs/nfs_xdr.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Please do not edit this file. * It was generated using rpcgen. diff --git a/components/dfs/filesystems/nfs/rpc/auth.h b/components/dfs/filesystems/nfs/rpc/auth.h index 3351fbbf95..f7dd76c237 100644 --- a/components/dfs/filesystems/nfs/rpc/auth.h +++ b/components/dfs/filesystems/nfs/rpc/auth.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __AUTH_H__ #define __AUTH_H__ diff --git a/components/dfs/filesystems/nfs/rpc/auth_none.c b/components/dfs/filesystems/nfs/rpc/auth_none.c index 92947581d2..9f5ad05002 100644 --- a/components/dfs/filesystems/nfs/rpc/auth_none.c +++ b/components/dfs/filesystems/nfs/rpc/auth_none.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)auth_none.c 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/clnt.h b/components/dfs/filesystems/nfs/rpc/clnt.h index 527075ee84..e86f8be789 100644 --- a/components/dfs/filesystems/nfs/rpc/clnt.h +++ b/components/dfs/filesystems/nfs/rpc/clnt.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)clnt.h 2.1 88/07/29 4.0 RPCSRC; from 1.31 88/02/08 SMI*/ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/clnt_generic.c b/components/dfs/filesystems/nfs/rpc/clnt_generic.c index a3de64a2f0..bd241b5835 100644 --- a/components/dfs/filesystems/nfs/rpc/clnt_generic.c +++ b/components/dfs/filesystems/nfs/rpc/clnt_generic.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)clnt_generic.c 2.2 88/08/01 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/clnt_udp.c b/components/dfs/filesystems/nfs/rpc/clnt_udp.c index a69bc0621a..6b4f7bfb13 100644 --- a/components/dfs/filesystems/nfs/rpc/clnt_udp.c +++ b/components/dfs/filesystems/nfs/rpc/clnt_udp.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)clnt_udp.c 2.2 88/08/01 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/pmap.c b/components/dfs/filesystems/nfs/rpc/pmap.c index 4f2cf50c1e..dc5a2ccb8d 100644 --- a/components/dfs/filesystems/nfs/rpc/pmap.c +++ b/components/dfs/filesystems/nfs/rpc/pmap.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "pmap.h" #include "clnt.h" #include diff --git a/components/dfs/filesystems/nfs/rpc/pmap.h b/components/dfs/filesystems/nfs/rpc/pmap.h index aaf28a331a..8ae706c0aa 100644 --- a/components/dfs/filesystems/nfs/rpc/pmap.h +++ b/components/dfs/filesystems/nfs/rpc/pmap.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __RPC_PMAP_PROT_H__ #define __RPC_PMAP_PROT_H__ diff --git a/components/dfs/filesystems/nfs/rpc/rpc.h b/components/dfs/filesystems/nfs/rpc/rpc.h index 306939e2fe..7256d336a1 100644 --- a/components/dfs/filesystems/nfs/rpc/rpc.h +++ b/components/dfs/filesystems/nfs/rpc/rpc.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)rpc.h 2.3 88/08/10 4.0 RPCSRC; from 1.9 88/02/08 SMI */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/rpc_msg.h b/components/dfs/filesystems/nfs/rpc/rpc_msg.h index bd32290990..a21ca1ce7d 100644 --- a/components/dfs/filesystems/nfs/rpc/rpc_msg.h +++ b/components/dfs/filesystems/nfs/rpc/rpc_msg.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)rpc_msg.h 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/rpc_prot.c b/components/dfs/filesystems/nfs/rpc/rpc_prot.c index 21fc1f4ea4..427d7a11e4 100644 --- a/components/dfs/filesystems/nfs/rpc/rpc_prot.c +++ b/components/dfs/filesystems/nfs/rpc/rpc_prot.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)rpc_prot.c 2.3 88/08/07 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/types.h b/components/dfs/filesystems/nfs/rpc/types.h index 310acf7f77..254fcd339c 100644 --- a/components/dfs/filesystems/nfs/rpc/types.h +++ b/components/dfs/filesystems/nfs/rpc/types.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape diff --git a/components/dfs/filesystems/nfs/rpc/xdr.c b/components/dfs/filesystems/nfs/rpc/xdr.c index ec37d6beb9..a6b1b67afb 100644 --- a/components/dfs/filesystems/nfs/rpc/xdr.c +++ b/components/dfs/filesystems/nfs/rpc/xdr.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)xdr.c 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/nfs/rpc/xdr.h b/components/dfs/filesystems/nfs/rpc/xdr.h index e4ab884465..fe38c4d120 100644 --- a/components/dfs/filesystems/nfs/rpc/xdr.h +++ b/components/dfs/filesystems/nfs/rpc/xdr.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for * unrestricted use provided that this legend is included on all tape diff --git a/components/dfs/filesystems/nfs/rpc/xdr_mem.c b/components/dfs/filesystems/nfs/rpc/xdr_mem.c index d6baf85837..ca69ed3647 100644 --- a/components/dfs/filesystems/nfs/rpc/xdr_mem.c +++ b/components/dfs/filesystems/nfs/rpc/xdr_mem.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* @(#)xdr_mem.c 2.1 88/07/29 4.0 RPCSRC */ /* * Sun RPC is a product of Sun Microsystems, Inc. and is provided for diff --git a/components/dfs/filesystems/ramfs/dfs_ramfs.c b/components/dfs/filesystems/ramfs/dfs_ramfs.c index c4b0f44d6d..e851c7ef78 100644 --- a/components/dfs/filesystems/ramfs/dfs_ramfs.c +++ b/components/dfs/filesystems/ramfs/dfs_ramfs.c @@ -1,21 +1,7 @@ /* - * File : dfs_ramfs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -453,6 +439,7 @@ struct dfs_ramfs* dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size) /* initialize ramfs object */ ramfs->magic = RAMFS_MAGIC; + ramfs->memheap.parent.type = RT_Object_Class_MemHeap | RT_Object_Class_Static; /* initialize root directory */ memset(&(ramfs->root), 0x00, sizeof(ramfs->root)); diff --git a/components/dfs/filesystems/ramfs/dfs_ramfs.h b/components/dfs/filesystems/ramfs/dfs_ramfs.h index b568706f68..9419784db9 100644 --- a/components/dfs/filesystems/ramfs/dfs_ramfs.h +++ b/components/dfs/filesystems/ramfs/dfs_ramfs.h @@ -1,21 +1,7 @@ /* - * File : dfs_ramfs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/romfs/dfs_romfs.c b/components/dfs/filesystems/romfs/dfs_romfs.c index c842601dc8..a953ac72d5 100644 --- a/components/dfs/filesystems/romfs/dfs_romfs.c +++ b/components/dfs/filesystems/romfs/dfs_romfs.c @@ -1,21 +1,7 @@ /* - * File : dfs_romfs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/romfs/dfs_romfs.h b/components/dfs/filesystems/romfs/dfs_romfs.h index d0898ecd9b..74b256c8a6 100644 --- a/components/dfs/filesystems/romfs/dfs_romfs.h +++ b/components/dfs/filesystems/romfs/dfs_romfs.h @@ -1,21 +1,7 @@ /* - * File : dfs_romfs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/romfs/romfs.c b/components/dfs/filesystems/romfs/romfs.c index 1bb885a57d..1ea9f21d8e 100644 --- a/components/dfs/filesystems/romfs/romfs.c +++ b/components/dfs/filesystems/romfs/romfs.c @@ -1,21 +1,7 @@ /* - * File : romfs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/skeleton/skeleton.c b/components/dfs/filesystems/skeleton/skeleton.c index 0d96cbffc9..30f0d4f629 100644 --- a/components/dfs/filesystems/skeleton/skeleton.c +++ b/components/dfs/filesystems/skeleton/skeleton.c @@ -1,21 +1,7 @@ /* - * File : skeleton.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/skeleton/skeleton.h b/components/dfs/filesystems/skeleton/skeleton.h index 844e91e4ae..8a783eace5 100644 --- a/components/dfs/filesystems/skeleton/skeleton.h +++ b/components/dfs/filesystems/skeleton/skeleton.h @@ -1,21 +1,7 @@ /* - * File : skeleton.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/uffs/dfs_uffs.c b/components/dfs/filesystems/uffs/dfs_uffs.c index 0256a524d5..b875d1eb00 100644 --- a/components/dfs/filesystems/uffs/dfs_uffs.c +++ b/components/dfs/filesystems/uffs/dfs_uffs.c @@ -1,21 +1,7 @@ /* - * File : dfs_uffs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -348,7 +334,7 @@ static int dfs_uffs_open(struct dfs_fd* file) return uffs_result_to_dfs(uffs_get_error()); } - /* save this pointer, it will be used when calling read()��write(), + /* save this pointer, it will be used when calling read(), write(), * flush(), seek(), and will be free when calling close()*/ file->data = (void *)fd; @@ -481,7 +467,7 @@ static int dfs_uffs_seek(struct dfs_fd* file, static int dfs_uffs_getdents( struct dfs_fd* file, struct dirent* dirp, - rt_uint32_t count) + uint32_t count) { rt_uint32_t index; char * file_path; diff --git a/components/dfs/filesystems/uffs/dfs_uffs.h b/components/dfs/filesystems/uffs/dfs_uffs.h index 810ab7ebfe..615d29036d 100644 --- a/components/dfs/filesystems/uffs/dfs_uffs.h +++ b/components/dfs/filesystems/uffs/dfs_uffs.h @@ -1,21 +1,7 @@ /* - * File : dfs_uffs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/filesystems/uffs/uffs_rtthread.c b/components/dfs/filesystems/uffs/uffs_rtthread.c index 2bafca92bc..bad456f04c 100644 --- a/components/dfs/filesystems/uffs/uffs_rtthread.c +++ b/components/dfs/filesystems/uffs/uffs_rtthread.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* This file is part of UFFS, the Ultra-low-cost Flash File System. diff --git a/components/dfs/filesystems/yaffs2/fixwarning.diff b/components/dfs/filesystems/yaffs2/fixwarning.diff deleted file mode 100644 index d0f9304924..0000000000 --- a/components/dfs/filesystems/yaffs2/fixwarning.diff +++ /dev/null @@ -1,398 +0,0 @@ -diff --git a/dfs_yaffs2.c b/dfs_yaffs2.c -index 4b056ae..e63d5d4 100644 ---- a/dfs_yaffs2.c -+++ b/dfs_yaffs2.c -@@ -39,7 +39,6 @@ static int dfs_yaffs_mount(struct dfs_filesystem* fs, - const void* data) - { - unsigned index; -- ynandif_Geometry *g; - - /*1. find a empty entry in partition table */ - for (index = 0; index < NAND_DEVICE_PART_MAX ; index ++) -diff --git a/yaffs/direct/yaffsfs.c b/yaffs/direct/yaffsfs.c -index 17fc502..1f47ea7 100644 ---- a/yaffs/direct/yaffsfs.c -+++ b/yaffs/direct/yaffsfs.c -@@ -1367,7 +1367,7 @@ off_t yaffs_lseek(int handle, off_t offset, int whence) - if(offset >= 0) - pos = offset; - } else if(whence == SEEK_CUR) { -- if( (fd->position + offset) >= 0) -+ if( ((int)fd->position + offset) >= 0) - pos = (fd->position + offset); - } else if(whence == SEEK_END) { - fSize = yaffs_get_obj_length(obj); -diff --git a/yaffs/direct/yportenv.h b/yaffs/direct/yportenv.h -index f693c16..ac0a737 100644 ---- a/yaffs/direct/yportenv.h -+++ b/yaffs/direct/yportenv.h -@@ -45,7 +45,7 @@ - #endif - - #ifndef loff_t -- typedef unsigned long loff_t; -+ typedef long loff_t; - #endif - - #ifndef dev_t -@@ -66,7 +66,7 @@ - #elif defined (__GNUC__) && !defined(__CC_ARM) - - #ifndef loff_t -- typedef unsigned long loff_t; -+ typedef long loff_t; - #endif - - #ifndef dev_t -diff --git a/yaffs/yaffs_guts.c b/yaffs/yaffs_guts.c -index d72aa5b..08db8c8 100644 ---- a/yaffs/yaffs_guts.c -+++ b/yaffs/yaffs_guts.c -@@ -280,7 +280,7 @@ static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, - - static inline int yaffs_hash_fn(int n) - { -- n = abs(n); -+ n = n > 0 ? n : -n; - return n % YAFFS_NOBJECT_BUCKETS; - } - -@@ -319,9 +319,9 @@ static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk) - int retval = YAFFS_OK; - u8 *data = yaffs_get_temp_buffer(dev); - struct yaffs_ext_tags tags; -- int result; - -- result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags); -+ -+ yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags); - - if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR) - retval = YAFFS_FAIL; -@@ -347,9 +347,9 @@ static int yaffs_verify_chunk_written(struct yaffs_dev *dev, - int retval = YAFFS_OK; - struct yaffs_ext_tags temp_tags; - u8 *buffer = yaffs_get_temp_buffer(dev); -- int result; - -- result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags); -+ -+ yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags); - if (memcmp(buffer, data, dev->data_bytes_per_chunk) || - temp_tags.obj_id != tags->obj_id || - temp_tags.chunk_id != tags->chunk_id || -@@ -1478,7 +1478,7 @@ static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) - struct yaffs_obj *the_obj; - int usage; - int i; -- int pushout; -+ /* int pushout; */ - - if (dev->param.n_caches < 1) - return NULL; -@@ -1499,7 +1499,7 @@ static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) - the_obj = dev->cache[0].object; - usage = -1; - cache = NULL; -- pushout = -1; -+ /* pushout = -1; */ - - for (i = 0; i < dev->param.n_caches; i++) { - if (dev->cache[i].object && -@@ -1509,7 +1509,7 @@ static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) - usage = dev->cache[i].last_use; - the_obj = dev->cache[i].object; - cache = &dev->cache[i]; -- pushout = i; -+ /* pushout = i; */ - } - } - -@@ -3167,7 +3167,7 @@ static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) - struct yaffs_obj_hdr *oh; - struct yaffs_dev *dev; - struct yaffs_ext_tags tags; -- int result; -+ - int alloc_failed = 0; - - if (!in || !in->lazy_loaded || in->hdr_chunk < 1) -@@ -3177,7 +3177,7 @@ static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) - in->lazy_loaded = 0; - buf = yaffs_get_temp_buffer(dev); - -- result = yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags); -+ yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags); - oh = (struct yaffs_obj_hdr *)buf; - - in->yst_mode = oh->yst_mode; -@@ -3189,6 +3189,7 @@ static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) - yaffs_clone_str(oh->alias); - if (!in->variant.symlink_variant.alias) - alloc_failed = 1; /* Not returned */ -+ alloc_failed = alloc_failed; - } - yaffs_release_temp_buffer(dev, buf); - } -@@ -3274,7 +3275,7 @@ int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force, - struct yaffs_dev *dev = in->my_dev; - int prev_chunk_id; - int ret_val = 0; -- int result = 0; -+ - int new_chunk_id; - struct yaffs_ext_tags new_tags; - struct yaffs_ext_tags old_tags; -@@ -3297,7 +3298,7 @@ int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force, - prev_chunk_id = in->hdr_chunk; - - if (prev_chunk_id > 0) { -- result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id, -+ yaffs_rd_chunk_tags_nand(dev, prev_chunk_id, - buffer, &old_tags); - - yaffs_verify_oh(in, oh, &old_tags, 0); -@@ -3921,7 +3922,7 @@ int yaffs_del_obj(struct yaffs_obj *obj) - list_del_init(&obj->variant.dir_variant.dirty); - } - return yaffs_del_dir(obj); -- break; -+ //break; - case YAFFS_OBJECT_TYPE_SYMLINK: - ret_val = yaffs_del_symlink(obj); - break; -@@ -3993,17 +3994,17 @@ static int yaffs_unlink_worker(struct yaffs_obj *obj) - switch (obj->variant_type) { - case YAFFS_OBJECT_TYPE_FILE: - return yaffs_del_file(obj); -- break; -+ //break; - case YAFFS_OBJECT_TYPE_DIRECTORY: - list_del_init(&obj->variant.dir_variant.dirty); - return yaffs_del_dir(obj); -- break; -+ //break; - case YAFFS_OBJECT_TYPE_SYMLINK: - return yaffs_del_symlink(obj); -- break; -+ //break; - case YAFFS_OBJECT_TYPE_SPECIAL: - return yaffs_generic_obj_del(obj); -- break; -+ //break; - case YAFFS_OBJECT_TYPE_HARDLINK: - case YAFFS_OBJECT_TYPE_UNKNOWN: - default: -@@ -4421,7 +4422,7 @@ int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size) - } else if (obj->short_name[0]) { - strcpy(name, obj->short_name); - } else if (obj->hdr_chunk > 0) { -- int result; -+ - u8 *buffer = yaffs_get_temp_buffer(obj->my_dev); - - struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer; -@@ -4429,7 +4430,7 @@ int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size) - memset(buffer, 0, obj->my_dev->data_bytes_per_chunk); - - if (obj->hdr_chunk > 0) { -- result = yaffs_rd_chunk_tags_nand(obj->my_dev, -+ yaffs_rd_chunk_tags_nand(obj->my_dev, - obj->hdr_chunk, - buffer, NULL); - } -@@ -4490,16 +4491,16 @@ unsigned yaffs_get_obj_type(struct yaffs_obj *obj) - switch (obj->variant_type) { - case YAFFS_OBJECT_TYPE_FILE: - return DT_REG; -- break; -+ //break; - case YAFFS_OBJECT_TYPE_DIRECTORY: - return DT_DIR; -- break; -+ //break; - case YAFFS_OBJECT_TYPE_SYMLINK: - return DT_LNK; -- break; -+ //break; - case YAFFS_OBJECT_TYPE_HARDLINK: - return DT_REG; -- break; -+ //break; - case YAFFS_OBJECT_TYPE_SPECIAL: - if (S_ISFIFO(obj->yst_mode)) - return DT_FIFO; -@@ -4510,10 +4511,10 @@ unsigned yaffs_get_obj_type(struct yaffs_obj *obj) - if (S_ISSOCK(obj->yst_mode)) - return DT_SOCK; - return DT_REG; -- break; -+ //break; - default: - return DT_REG; -- break; -+ //break; - } - } - -@@ -4837,7 +4838,7 @@ int yaffs_guts_initialise(struct yaffs_dev *dev) - dev->n_erased_blocks = 0; - dev->n_free_chunks = 0; - dev->alloc_block = -1; -- dev->alloc_page = -1; -+ dev->alloc_page = (u32)(-1); - dev->n_deleted_files = 0; - dev->n_unlinked_files = 0; - dev->n_bg_deletions = 0; -diff --git a/yaffs/yaffs_packedtags2.c b/yaffs/yaffs_packedtags2.c -index 820bc41..9306623 100644 ---- a/yaffs/yaffs_packedtags2.c -+++ b/yaffs/yaffs_packedtags2.c -@@ -35,7 +35,7 @@ - - /* Also, the top 4 bits of the object Id are set to the object type. */ - #define EXTRA_OBJECT_TYPE_SHIFT (28) --#define EXTRA_OBJECT_TYPE_MASK ((0x0f) << EXTRA_OBJECT_TYPE_SHIFT) -+#define EXTRA_OBJECT_TYPE_MASK ((0x0fUL) << EXTRA_OBJECT_TYPE_SHIFT) - - static void yaffs_dump_packed_tags2_tags_only( - const struct yaffs_packed_tags2_tags_only *ptt) -@@ -129,7 +129,7 @@ void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, - t->extra_parent_id = ptt->chunk_id & (~(ALL_EXTRA_FLAGS)); - t->extra_is_shrink = ptt->chunk_id & EXTRA_SHRINK_FLAG ? 1 : 0; - t->extra_shadows = ptt->chunk_id & EXTRA_SHADOWS_FLAG ? 1 : 0; -- t->extra_obj_type = ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT; -+ t->extra_obj_type = (enum yaffs_obj_type)(ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT); - t->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; - - if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) -diff --git a/yaffs/yaffs_verify.c b/yaffs/yaffs_verify.c -index b3e540d..1758125 100644 ---- a/yaffs/yaffs_verify.c -+++ b/yaffs/yaffs_verify.c -@@ -223,7 +223,7 @@ void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, - void yaffs_verify_file(struct yaffs_obj *obj) - { - int required_depth; -- int actual_depth; -+ //int actual_depth; - u32 last_chunk; - u32 the_chunk; - u32 x; -@@ -252,7 +252,7 @@ void yaffs_verify_file(struct yaffs_obj *obj) - required_depth++; - } - -- actual_depth = obj->variant.file_variant.top_level; -+ //actual_depth = obj->variant.file_variant.top_level; - - /* Check that the chunks in the tnode tree are all correct. - * We do this by scanning through the tnode tree and -diff --git a/yaffs/yaffs_yaffs1.c b/yaffs/yaffs_yaffs1.c -index da6a40f..8e7f4b2 100644 ---- a/yaffs/yaffs_yaffs1.c -+++ b/yaffs/yaffs_yaffs1.c -@@ -23,7 +23,7 @@ int yaffs1_scan(struct yaffs_dev *dev) - { - struct yaffs_ext_tags tags; - int blk; -- int result; -+ //int result; - int chunk; - int c; - int deleted; -@@ -84,7 +84,7 @@ int yaffs1_scan(struct yaffs_dev *dev) - cond_resched(); - - bi = yaffs_get_block_info(dev, blk); -- state = bi->block_state; -+ state = (enum yaffs_block_state)(bi->block_state); - - deleted = 0; - -@@ -95,7 +95,7 @@ int yaffs1_scan(struct yaffs_dev *dev) - /* Read the tags and decide what to do */ - chunk = blk * dev->param.chunks_per_block + c; - -- result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, -+ yaffs_rd_chunk_tags_nand(dev, chunk, NULL, - &tags); - - /* Let's have a good look at this chunk... */ -@@ -181,7 +181,7 @@ int yaffs1_scan(struct yaffs_dev *dev) - yaffs_set_chunk_bit(dev, blk, c); - bi->pages_in_use++; - -- result = yaffs_rd_chunk_tags_nand(dev, chunk, -+ yaffs_rd_chunk_tags_nand(dev, chunk, - chunk_data, - NULL); - -diff --git a/yaffs/yaffs_yaffs2.c b/yaffs/yaffs_yaffs2.c -index 5761e96..69acd20 100644 ---- a/yaffs/yaffs_yaffs2.c -+++ b/yaffs/yaffs_yaffs2.c -@@ -946,7 +946,7 @@ static inline int yaffs2_scan_chunk(struct yaffs_dev *dev, - int is_shrink; - int is_unlinked; - struct yaffs_ext_tags tags; -- int result; -+ //int result; - int alloc_failed = 0; - int chunk = blk * dev->param.chunks_per_block + chunk_in_block; - struct yaffs_file_var *file_var; -@@ -954,12 +954,12 @@ static inline int yaffs2_scan_chunk(struct yaffs_dev *dev, - struct yaffs_symlink_var *sl_var; - - if (summary_available) { -- result = yaffs_summary_fetch(dev, &tags, chunk_in_block); -+ yaffs_summary_fetch(dev, &tags, chunk_in_block); - tags.seq_number = bi->seq_number; - } - - if (!summary_available || tags.obj_id == 0) { -- result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags); -+ yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags); - dev->tags_used++; - } else { - dev->summary_used++; -@@ -1114,7 +1114,7 @@ static inline int yaffs2_scan_chunk(struct yaffs_dev *dev, - * invalid data until needed. - */ - -- result = yaffs_rd_chunk_tags_nand(dev, -+ yaffs_rd_chunk_tags_nand(dev, - chunk, - chunk_data, - NULL); -@@ -1349,7 +1349,7 @@ int yaffs2_scan_backwards(struct yaffs_dev *dev) - int n_to_scan = 0; - enum yaffs_block_state state; - int c; -- int deleted; -+ //int deleted; - LIST_HEAD(hard_list); - struct yaffs_block_info *bi; - u32 seq_number; -@@ -1467,7 +1467,7 @@ int yaffs2_scan_backwards(struct yaffs_dev *dev) - /* get the block to scan in the correct order */ - blk = block_index[block_iter].block; - bi = yaffs_get_block_info(dev, blk); -- deleted = 0; -+ //deleted = 0; - - summary_available = yaffs_summary_read(dev, dev->sum_tags, blk); - -diff --git a/yaffs_osglue.c b/yaffs_osglue.c -index 2c34f99..4f2e5db 100644 ---- a/yaffs_osglue.c -+++ b/yaffs_osglue.c -@@ -58,7 +58,6 @@ void yaffsfs_LockInit(void) - #else - - static rt_mutex_t mutex = RT_NULL; --static rt_sem_t sem = RT_NULL; - void yaffsfs_Lock(void) - { - rt_mutex_take(mutex, RT_WAITING_FOREVER); diff --git a/components/dfs/filesystems/yaffs2/readme.txt b/components/dfs/filesystems/yaffs2/readme.txt deleted file mode 100644 index e6b8d3b976..0000000000 --- a/components/dfs/filesystems/yaffs2/readme.txt +++ /dev/null @@ -1,46 +0,0 @@ -how to use yaffs under rt-thread. - -There are three steps. -1. get yaffs tarball from official repo. - the repo of official repo is here. - http://www.aleph1.co.uk/gitweb?p=yaffs2.git;a=summary - then you should find the 2011-6-28's snapshot, download the tarball - http://www.aleph1.co.uk/gitweb?p=yaffs2.git;a=snapshot;h=2df51cdb98e799c4d10b4cc7dd7e8858aa79e7d8;sf=tgz - - decompress the yaffs.tar.gz to rt-thread\components\dfs\filesystems\yaffs2\yaffs - -2. patch yaffs.diff - open an terminal. - (1) on windows - open cmd command prompt, then use [cd] command to come current path - for example - F:\Project\svn\rt-thread\components\dfs\filesystems\yaffs2> - then type command - patch -p1 < yaffs.diff - - you will get some log information as followings - F:\Project\svn\rt-thread\components\dfs\filesystems\yaffs2>patch -p1 < yaffs.diff - patching file `dfs_yaffs2.c' - patching file `yaffs/direct/yaffs_list.h' - patching file `yaffs/direct/yaffs_nandif.c' - patching file `yaffs/direct/ydirectenv.h' - patching file `yaffs/direct/yportenv.h' - patching file `yaffs_nandcfg.c' - patching file `yaffs_osglue.c' - - now you can delete yaffs.diff - there is another patch file, as the name shows, it is to fix compile - warning, so it is not necessary. If you want, you can use the - following command. - patch -p1 < fixwarning.diff - - (2) on linux - Help yourself. Since you have use linux as your os, I believe in you. - -3.add nand driver and compile - In order to use yaffs, you should provide a nand driver which is needed - by yaffs. There is an example file in rt-thread\components\dfs\filesystems\uffs\nand. - you should modify yaffs_nandcfg.c according to your nand driver. - then you can use scons or IDE like MDK or IAR to compile. - - enjoy ! diff --git a/components/dfs/filesystems/yaffs2/yaffs.diff b/components/dfs/filesystems/yaffs2/yaffs.diff deleted file mode 100644 index e487ac6a6d..0000000000 --- a/components/dfs/filesystems/yaffs2/yaffs.diff +++ /dev/null @@ -1,1014 +0,0 @@ -diff --git a/dfs_yaffs2.c b/dfs_yaffs2.c -new file mode 100644 -index 0000000..4b056ae ---- /dev/null -+++ b/dfs_yaffs2.c -@@ -0,0 +1,405 @@ -+/* -+ * File : rtthread.h -+ * This file is part of RT-Thread RTOS -+ * COPYRIGHT (C) 2006-2011, RT-Thread Development Team -+ * -+ * The license and distribution terms for this file may be -+ * found in the file LICENSE in this distribution or at -+ * http://www.rt-thread.org/license/LICENSE. -+ * -+ * Change Logs: -+ * Date Author Notes -+ * 2011-10-22 prife the first version -+ * 2012-04-14 prife use mtd device interface -+*/ -+#include -+#include -+ -+#include "yaffsfs.h" -+#include "yaffs_nandif.h" -+ -+#include -+#include -+ -+#define YAFFS_FILE_PATH_MAX 256 /* the longest file path */ -+ -+#define NAND_DEVICE_PART_MAX 4 /* the max partitions on a nand deivce*/ -+struct device_part -+{ -+ struct rt_mtd_nand_device *dev; -+ ynandif_Geometry g; -+}; -+static struct device_part nand_part[NAND_DEVICE_PART_MAX] = {0}; -+ -+extern int yaffs_start(const char * mountpath, ynandif_Geometry * g); -+extern void yaffs_config(ynandif_Geometry * g, struct rt_mtd_nand_device * dev); -+ -+static int dfs_yaffs_mount(struct dfs_filesystem* fs, -+ unsigned long rwflag, -+ const void* data) -+{ -+ unsigned index; -+ ynandif_Geometry *g; -+ -+ /*1. find a empty entry in partition table */ -+ for (index = 0; index < NAND_DEVICE_PART_MAX ; index ++) -+ { -+ if (nand_part[index].dev == RT_NULL) -+ break; -+ } -+ if (index == NAND_DEVICE_PART_MAX) -+ return -DFS_STATUS_ENOSPC; -+ -+ /*2. fill nand_part*/ -+ nand_part[index].dev = RT_MTD_NAND_DEVICE(fs->dev_id); -+ yaffs_config(&nand_part[index].g, RT_MTD_NAND_DEVICE(fs->dev_id)); -+ -+ /*3. start up yaffs2 */ -+ yaffs_start(fs->path, &nand_part[index].g); -+ if (yaffs_mount(fs->path) < 0) -+ { -+ return yaffsfs_GetLastError(); -+ } -+ return 0; -+} -+ -+static int dfs_yaffs_unmount(struct dfs_filesystem* fs) -+{ -+ unsigned index; -+ if (yaffs_unmount(fs->path) < 0) -+ return yaffsfs_GetLastError(); -+ -+ /* find device index, then umount it */ -+ for (index = 0; index < NAND_DEVICE_PART_MAX; index++) -+ { -+ if (nand_part[index].dev == RT_MTD_NAND_DEVICE(fs->dev_id)) -+ { -+ nand_part[index].dev = RT_NULL; -+ return DFS_STATUS_OK; -+ } -+ } -+ return -DFS_STATUS_ENOENT; -+} -+ -+static int dfs_yaffs_mkfs(const char* device_name) -+{ -+ /* just erase all blocks on this nand partition */ -+ return -DFS_STATUS_ENOSYS; -+} -+ -+static int dfs_yaffs_statfs(struct dfs_filesystem* fs, -+ struct statfs *buf) -+{ -+ struct rt_mtd_nand_device * mtd = RT_MTD_NAND_DEVICE(fs->dev_id); -+ -+ RT_ASSERT(mtd != RT_NULL); -+ -+ buf->f_bsize = mtd->page_size; -+ buf->f_blocks = (mtd->block_size)/(mtd->page_size)* -+ (mtd->block_start - mtd->block_end + 1); -+ buf->f_bfree = yaffs_freespace(fs->path) / mtd->page_size; -+ -+ return 0; -+} -+ -+static int dfs_yaffs_open(struct dfs_fd* file) -+{ -+ int fd; -+ int oflag; -+ int result; -+ -+ oflag = file->flags; -+ if (oflag & DFS_O_DIRECTORY) /* operations about dir */ -+ { -+ yaffs_DIR * dir; -+ if (oflag & DFS_O_CREAT) /* create a dir*/ -+ { -+ result = yaffs_mkdir(file->path, 0x777); /* the second args not supported by rtt */ -+ if (result < 0) -+ return yaffsfs_GetLastError(); -+ } -+ /* open dir */ -+ dir = yaffs_opendir(file->path); -+ if (dir == RT_NULL) -+ return yaffsfs_GetLastError(); -+ /* save this pointer,will used by dfs_yaffs_getdents*/ -+ file->data = dir; -+ return 0; -+ } -+ /* regular file operations */ -+ fd = yaffs_open(file->path, oflag, S_IREAD | S_IWRITE); -+ if (fd < 0) -+ return yaffsfs_GetLastError(); -+ -+ /* save this pointer, it will be used when calling read()write(), -+ flush(), lessk(), and will be free when calling close()*/ -+ file->data = (void *)fd; -+ file->pos = yaffs_lseek(fd,0,SEEK_CUR); -+ file->size = yaffs_lseek(fd,0,SEEK_END); -+ yaffs_lseek(fd, file->pos, SEEK_SET); -+ -+ if (oflag & DFS_O_APPEND) -+ { -+ file->pos = file->size; -+ file->size = yaffs_lseek(fd,0,SEEK_END); -+ } -+ return 0; -+} -+ -+static int dfs_yaffs_close(struct dfs_fd* file) -+{ -+ int oflag; -+ int fd; -+ -+ oflag = file->flags; -+ if (oflag & DFS_O_DIRECTORY) /* operations about dir */ -+ { -+ if (yaffs_closedir((yaffs_DIR *)(file->data)) < 0) -+ return yaffsfs_GetLastError(); -+ return 0; -+ } -+ /* regular file operations */ -+ fd = (int)(file->data); -+ -+ if (yaffs_close(fd) == 0) -+ return 0; -+ -+ /* release memory */ -+ return yaffsfs_GetLastError(); -+} -+ -+static int dfs_yaffs_ioctl(struct dfs_fd* file, int cmd, void* args) -+{ -+ return -DFS_STATUS_ENOSYS; -+} -+ -+static int dfs_yaffs_read(struct dfs_fd* file, void* buf, rt_size_t len) -+{ -+ int fd; -+ int char_read; -+ -+ fd = (int)(file->data); -+ char_read = yaffs_read(fd, buf, len); -+ if (char_read < 0) -+ return yaffsfs_GetLastError(); -+ -+ /* update position */ -+ file->pos = yaffs_lseek(fd, 0, SEEK_CUR); -+ return char_read; -+} -+ -+static int dfs_yaffs_write(struct dfs_fd* file, -+ const void* buf, -+ rt_size_t len) -+{ -+ int fd; -+ int char_write; -+ -+ fd = (int)(file->data); -+ -+ char_write = yaffs_write(fd, buf, len); -+ if (char_write < 0) -+ return yaffsfs_GetLastError(); -+ -+ /* update position */ -+ file->pos = yaffs_lseek(fd, 0, SEEK_CUR); -+ return char_write; -+} -+ -+static int dfs_yaffs_flush(struct dfs_fd* file) -+{ -+ int fd; -+ int result; -+ -+ fd = (int)(file->data); -+ -+ result = yaffs_flush(fd); -+ if (result < 0) -+ return yaffsfs_GetLastError(); -+ return 0; -+} -+ -+static int dfs_yaffs_lseek(struct dfs_fd* file, -+ rt_off_t offset) -+{ -+ int fd; -+ int result; -+ -+ fd = (int)(file->data); -+ -+ /* set offset as current offset */ -+ result = yaffs_lseek(fd, offset, SEEK_SET); -+ if (result < 0) -+ return yaffsfs_GetLastError(); -+ return result; -+} -+ -+/* return the size of struct dirent*/ -+static int dfs_yaffs_getdents(struct dfs_fd* file, -+ struct dirent* dirp, -+ rt_uint32_t count) -+{ -+ rt_uint32_t index; -+ char * file_path; -+ struct dirent* d; -+ yaffs_DIR* dir; -+ struct yaffs_dirent * yaffs_d; -+ -+ dir = (yaffs_DIR*)(file->data); -+ RT_ASSERT(dir != RT_NULL); -+ -+ /* make integer count, usually count is 1 */ -+ count = (count / sizeof(struct dirent)) * sizeof(struct dirent); -+ if (count == 0) return -DFS_STATUS_EINVAL; -+ -+ /* allocate file name */ -+ file_path = rt_malloc(YAFFS_FILE_PATH_MAX); -+ if (file_path == RT_NULL) -+ return -DFS_STATUS_ENOMEM; -+ -+ index = 0; -+ /* usually, the while loop should only be looped only once! */ -+ while (1) -+ { -+ struct yaffs_stat s; -+ -+ d = dirp + index; -+ -+ yaffs_d = yaffs_readdir(dir); -+ if (yaffs_d == RT_NULL) -+ { -+ if (yaffsfs_GetLastError() == EBADF) -+ return -DFS_STATUS_EBADF; -+ -+ rt_free(file_path); -+ return -1; /* a general error */ -+ } -+ -+ rt_snprintf(file_path, YAFFS_FILE_PATH_MAX, "%s/%s", file->path, yaffs_d->d_name); -+ -+ yaffs_lstat(file_path, &s); -+ switch(s.st_mode & S_IFMT) -+ { -+ case S_IFREG: d->d_type = DFS_DT_REG; break; -+ -+ case S_IFDIR: d->d_type = DFS_DT_DIR; break; -+ -+ case S_IFLNK: -+ default: d->d_type = DFS_DT_UNKNOWN; break; -+ } -+ -+ /* write the rest feilds of struct dirent* dirp */ -+ d->d_namlen = rt_strlen(yaffs_d->d_name); -+ d->d_reclen = (rt_uint16_t)sizeof(struct dirent); -+ rt_strncpy(d->d_name, yaffs_d->d_name, rt_strlen(yaffs_d->d_name) + 1); -+ -+ index ++; -+ if (index * sizeof(struct dirent) >= count) -+ break; -+ } -+ -+ /* free file name buf */ -+ rt_free(file_path); -+ -+ if (index == 0) -+ return yaffsfs_GetLastError(); -+ -+ return index * sizeof(struct dirent); -+} -+ -+static int dfs_yaffs_unlink(struct dfs_filesystem* fs, const char* path) -+{ -+ int result; -+ struct yaffs_stat s; -+ -+ /* judge file type, dir is to be delete by yaffs_rmdir, others by yaffs_unlink */ -+ if (yaffs_lstat(path, &s) < 0) -+ { -+ return yaffsfs_GetLastError(); -+ } -+ -+ switch(s.st_mode & S_IFMT) -+ { -+ case S_IFREG: -+ result = yaffs_unlink(path); -+ break; -+ case S_IFDIR: -+ result = yaffs_rmdir(path); -+ break; -+ default: -+ /* unknown file type */ -+ return -1; -+ } -+ if (result < 0) -+ return yaffsfs_GetLastError(); -+ return 0; -+} -+ -+static int dfs_yaffs_rename(struct dfs_filesystem* fs, -+ const char* oldpath, -+ const char* newpath) -+{ -+ int result; -+ -+ result = yaffs_rename(oldpath, newpath); -+ -+ if (result < 0) -+ return yaffsfs_GetLastError(); -+ return 0; -+} -+ -+static int dfs_yaffs_stat(struct dfs_filesystem* fs, const char *path, struct stat *st) -+{ -+ int result; -+ struct yaffs_stat s; -+ struct rt_mtd_nand_device * mtd; -+ -+ result = yaffs_stat(path, &s); -+ if (result < 0) -+ return yaffsfs_GetLastError(); -+ -+ /* convert to dfs stat structure */ -+ st->st_dev = 0; -+ st->st_mode = s.st_mode; -+ st->st_size = s.st_size; -+ st->st_mtime = s.yst_mtime; -+ -+ mtd = RT_MTD_NAND_DEVICE(fs->dev_id); -+ st->st_blksize = mtd->page_size; -+ -+ return 0; -+} -+ -+static const struct dfs_filesystem_operation dfs_yaffs_ops = -+{ -+ "yaffs2", /* file system type: yaffs2 */ -+#if RTTHREAD_VERSION >= 10100 -+ DFS_FS_FLAG_FULLPATH, -+#else -+#error "yaffs2 can only work with rtthread whose version should >= 1.01\n" -+#endif -+ dfs_yaffs_mount, -+ dfs_yaffs_unmount, -+ dfs_yaffs_mkfs, -+ dfs_yaffs_statfs, -+ -+ dfs_yaffs_open, -+ dfs_yaffs_close, -+ dfs_yaffs_ioctl, -+ dfs_yaffs_read, -+ dfs_yaffs_write, -+ dfs_yaffs_flush, -+ dfs_yaffs_lseek, -+ dfs_yaffs_getdents, -+ dfs_yaffs_unlink, -+ dfs_yaffs_stat, -+ dfs_yaffs_rename, -+}; -+ -+int dfs_yaffs_init(void) -+{ -+ /* register fatfs file system */ -+ dfs_register(&dfs_yaffs_ops); -+ -+ return 0; -+} -diff --git a/yaffs/direct/yaffs_list.h b/yaffs/direct/yaffs_list.h -index f1c5254..17044f5 100644 ---- a/yaffs/direct/yaffs_list.h -+++ b/yaffs/direct/yaffs_list.h -@@ -39,7 +39,7 @@ struct list_head { - - /* Initialise a static list */ - #define LIST_HEAD(name) \ --struct list_head name = { &(name), &(name)} -+static struct list_head name = { &(name), &(name)} - - - -diff --git a/yaffs/direct/yaffs_nandif.c b/yaffs/direct/yaffs_nandif.c -index b93b55a..3fae80e 100644 ---- a/yaffs/direct/yaffs_nandif.c -+++ b/yaffs/direct/yaffs_nandif.c -@@ -18,7 +18,6 @@ - #include "yaffs_nandif.h" - #include "yaffs_packedtags2.h" - --#include "yramsim.h" - - #include "yaffs_trace.h" - #include "yaffsfs.h" -@@ -216,8 +215,8 @@ struct yaffs_dev * - yaffs_add_dev_from_geometry(const YCHAR *name, - const ynandif_Geometry *geometry) - { -- YCHAR *clonedName = malloc(sizeof(YCHAR) * (strnlen(name,YAFFS_MAX_NAME_LENGTH)+1)); -- struct yaffs_dev *dev = malloc(sizeof(struct yaffs_dev)); -+ YCHAR *clonedName = kmalloc(sizeof(YCHAR) * (strnlen(name,YAFFS_MAX_NAME_LENGTH)+1), GFP_NOFS); -+ struct yaffs_dev *dev = kmalloc(sizeof(struct yaffs_dev), GFP_NOFS); - - if(dev && clonedName){ - memset(dev,0,sizeof(struct yaffs_dev)); -@@ -242,16 +241,17 @@ struct yaffs_dev * - dev->param.n_reserved_blocks = 5; - dev->driver_context = (void *)geometry; - -+ /* save rt_mtd_nand_device * dev*/ -+ dev->os_context = (void *)(geometry->privateData); - yaffs_add_device(dev); - - return dev; - } - - if(dev) -- free(dev); -+ kfree(dev); - if(clonedName) -- free(clonedName); -+ kfree(clonedName); - - return NULL; - } -- -diff --git a/yaffs/direct/ydirectenv.h b/yaffs/direct/ydirectenv.h -index 7860b84..5add3ec 100644 ---- a/yaffs/direct/ydirectenv.h -+++ b/yaffs/direct/ydirectenv.h -@@ -22,16 +22,13 @@ - - // Direct interface - --#include "stdlib.h" --#include "stdio.h" -+#include - #include "string.h" -+ - #include "yaffs_osglue.h" - #include "yaffs_hweight.h" - --#include "assert.h" --#define BUG() assert(0) --//#define BUG() do { *((int *)0) =1;} while(0) -- -+#define BUG() RT_ASSERT(0) - - #define YCHAR char - #define YUCHAR unsigned char -@@ -47,30 +44,24 @@ void yaffs_qsort(void *aa, size_t n, size_t es, - - #define YAFFS_PATH_DIVIDERS "/" - --#ifdef NO_inline --#define inline --#else --#define inline __inline__ --#endif -- --#define kmalloc(x,flags) yaffsfs_malloc(x) -+#define GFP_NOFS 0 -+#define kmalloc(x, y) yaffsfs_malloc(x) - #define kfree(x) yaffsfs_free(x) - #define vmalloc(x) yaffsfs_malloc(x) --#define vfree(x) yaffsfs_free(x) -+#define vfree(x) yaffsfs_free(x) -+#define printf rt_kprintf - - #define cond_resched() do {} while(0) - - #define yaffs_trace(msk, fmt, ...) do { \ - if(yaffs_trace_mask & (msk)) \ -- printf("yaffs: " fmt "\n", ##__VA_ARGS__); \ -+ rt_kprintf("yaffs: " fmt "\n", ##__VA_ARGS__); \ - } while(0) - - - #define YAFFS_LOSTNFOUND_NAME "lost+found" - #define YAFFS_LOSTNFOUND_PREFIX "obj" - --#include "yaffscfg.h" -- - #define Y_CURRENT_TIME yaffsfs_CurrentTime() - #define Y_TIME_CONVERT(x) x - -@@ -79,8 +70,6 @@ void yaffs_qsort(void *aa, size_t n, size_t es, - - #include "yaffs_list.h" - --#include "yaffsfs.h" -- - #endif - - -diff --git a/yaffs/direct/yportenv.h b/yaffs/direct/yportenv.h -index 939cd3a..f693c16 100644 ---- a/yaffs/direct/yportenv.h -+++ b/yaffs/direct/yportenv.h -@@ -17,36 +17,146 @@ - #ifndef __YPORTENV_H__ - #define __YPORTENV_H__ - -+#include -+ -+#define CONFIG_YAFFS_DIRECT -+#define CONFIG_YAFFS_PROVIDE_DEFS -+#define CONFIG_YAFFSFS_PROVIDE_VALUES -+ -+#ifdef NO_inline -+ #define inline -+#else -+ #ifdef __CC_ARM -+ #define inline __inline -+ #elif defined (__GNUC__) /* GNU GCC Compiler */ -+ #define inline __inline -+ #else -+ #error "Please set a macro inline with a valid args" -+ #endif -+#endif -+ -+#if defined(__CC_ARM) -+ #ifdef RT_USING_NEWLIB -+ #error "error: when use armcc, please Don't USE NEWLIB!!!" -+ #endif -+ -+ #ifndef off_t -+ typedef long off_t; -+ #endif -+ -+ #ifndef loff_t -+ typedef unsigned long loff_t; -+ #endif -+ -+ #ifndef dev_t -+ typedef long dev_t; -+ #endif -+ -+ #ifndef mode_t -+ typedef int mode_t; -+ #endif -+ -+ /* just like strlen(3), but cap the number of bytes we count */ -+ rt_inline size_t strnlen(const char *s, size_t max) { -+ register const char *p; -+ for(p = s; *p && max--; ++p); -+ return(p - s); -+ } -+ -+#elif defined (__GNUC__) && !defined(__CC_ARM) -+ -+ #ifndef loff_t -+ typedef unsigned long loff_t; -+ #endif -+ -+ #ifndef dev_t -+ typedef long dev_t; -+ #endif -+#endif - - /* Definition of types */ - typedef unsigned char u8; - typedef unsigned short u16; - typedef unsigned u32; -- -- --#ifndef WIN32 --#include --#endif -- -+ -+#ifndef S_ISDIR -+ #ifndef _DEV_T_DEFINED -+ typedef unsigned int _dev_t; /* device code */ -+ #if !__STDC__ -+ /* Non-ANSI name for compatibility */ -+ typedef unsigned int dev_t; -+ #endif -+ -+ #define _DEV_T_DEFINED -+ #endif -+ -+ #define __S_IFMT 0170000 /* These bits determine file type. */ -+ /* File types. */ -+ #define __S_IFDIR 0040000 /* Directory. */ -+ #define __S_IFCHR 0020000 /* Character device. */ -+ #define __S_IFBLK 0060000 /* Block device. */ -+ #define __S_IFREG 0100000 /* Regular file. */ -+ #define __S_IFIFO 0010000 /* FIFO. */ -+ #define __S_IFLNK 0120000 /* Symbolic link. */ -+ #define __S_IFSOCK 0140000 /* Socket. */ -+ -+ /* Protection bits. */ -+ #define __S_ISUID 04000 /* Set user ID on execution. */ -+ #define __S_ISGID 02000 /* Set group ID on execution. */ -+ #define __S_ISVTX 01000 /* Save swapped text after use (sticky). */ -+ #define __S_IREAD 0400 /* Read by owner. */ -+ #define __S_IWRITE 0200 /* Write by owner. */ -+ #define __S_IEXEC 0100 /* Execute by owner. */ -+ #define __S_ISTYPE(mode, mask) (((mode) & __S_IFMT) == (mask)) -+ -+ #define S_ISDIR(mode) __S_ISTYPE((mode), __S_IFDIR) -+ #define S_ISCHR(mode) __S_ISTYPE((mode), __S_IFCHR) -+ #define S_ISBLK(mode) __S_ISTYPE((mode), __S_IFBLK) -+ #define S_ISREG(mode) __S_ISTYPE((mode), __S_IFREG) -+ #define S_ISSOCK(mode) __S_ISTYPE((mode), __S_IFSOCK) -+ #define S_ISFIFO(mode) __S_ISTYPE((mode), __S_IFSOCK) -+ #define S_IRUSR __S_IREAD // Read by owner. -+ #define S_IWUSR __S_IWRITE // Write by owner. -+ #define S_IXUSR __S_IEXEC // Execute by owner. -+ #define S_IREAD S_IRUSR -+ #define S_IWRITE S_IWUSR -+ #define S_IEXEC S_IXUSR -+ #define S_IFDIR __S_IFDIR -+#endif - - #ifdef CONFIG_YAFFS_PROVIDE_DEFS - /* File types */ - -+#ifndef DT_UNKNOWN -+ #define DT_UNKNOWN 0 -+#endif -+#ifndef DT_FIFO -+ #define DT_FIFO 1 -+#endif - --#define DT_UNKNOWN 0 --#define DT_FIFO 1 --#define DT_CHR 2 --#define DT_DIR 4 --#define DT_BLK 6 --#define DT_REG 8 --#define DT_LNK 10 --#define DT_SOCK 12 --#define DT_WHT 14 -- -+#ifndef DT_CHR -+ #define DT_CHR 2 -+#endif - --#ifndef WIN32 --#include -+#ifndef DT_DIR -+ #define DT_DIR 4 -+#endif -+#ifndef DT_BLK -+ #define DT_BLK 6 -+#endif -+#ifndef DT_REG -+ #define DT_REG 8 - #endif -+#ifndef DT_LNK -+ #define DT_LNK 10 -+#endif -+#ifndef DT_SOCK -+ #define DT_SOCK 12 -+#endif -+#ifndef DT_WHT -+ #define DT_WHT 14 -+#endif -+ - - /* - * Attribute flags. -@@ -75,7 +185,6 @@ struct iattr { - #endif - - -- - #if defined CONFIG_YAFFS_WINCE - - #include "ywinceenv.h" -@@ -267,9 +376,17 @@ struct iattr { - #endif - - #else --#include --#include --#include -+//#include -+//#include -+//#include -+#ifndef XATTR_CREATE -+#define XATTR_CREATE 1 -+#endif -+ -+#ifndef XATTR_REPLACE -+#define XATTR_REPLACE 2 -+#endif -+ - #endif - - #endif -diff --git a/yaffs_nandcfg.c b/yaffs_nandcfg.c -new file mode 100644 -index 0000000..099fa38 ---- /dev/null -+++ b/yaffs_nandcfg.c -@@ -0,0 +1,149 @@ -+#include -+#include -+#include -+#include -+ -+#include "yaffsfs.h" -+#include "yaffs_nandif.h" -+#include "yaffs_trace.h" -+ -+/* -+ * RT-Thread Device Interface for yaffs -+ */ -+static int nand_init(struct yaffs_dev *dev) -+{ -+ return YAFFS_OK; -+} -+ -+static int nand_deinit(struct yaffs_dev *dev) -+{ -+ return YAFFS_OK; -+} -+ -+/* if block is good, return YAFFS_OK, else return YAFFS_FAIL */ -+static int nand_checkblock(struct yaffs_dev *dev, unsigned block) -+{ -+ rt_err_t res; -+ res = rt_mtd_nand_check_block(RT_MTD_NAND_DEVICE(dev->os_context), block); -+ return res == RT_EOK ? YAFFS_OK : YAFFS_FAIL; -+} -+static int nand_markbadblk(struct yaffs_dev *dev, unsigned block) -+{ -+ rt_err_t res; -+ res = rt_mtd_nand_mark_badblock(RT_MTD_NAND_DEVICE(dev->os_context), block); -+ return res == RT_EOK ? YAFFS_OK : YAFFS_FAIL; -+} -+ -+static int nand_eraseblock(struct yaffs_dev *dev, unsigned block) -+{ -+ int res; -+ res = rt_mtd_nand_erase_block(RT_MTD_NAND_DEVICE(dev->os_context), block); -+ return res == RT_EOK ? YAFFS_OK : YAFFS_FAIL; -+} -+ -+static int nand_readpage( -+ struct yaffs_dev *dev, -+ unsigned page, -+ unsigned char *data, unsigned data_len, /* page data */ -+ unsigned char *spare, unsigned spare_len,/* page spare */ -+ int *ecc_status) -+{ -+ int res; -+ unsigned char spare_buf[64]; -+ -+ res = rt_mtd_nand_read(RT_MTD_NAND_DEVICE(dev->os_context), -+ page, data, data_len, spare_buf, spare_len + 5); -+ rt_memcpy(spare, spare_buf + 5, spare_len); -+ if (res == 0) -+ *ecc_status = 0; -+ else if (res == -1) -+ *ecc_status = 1; -+ else -+ *ecc_status = -1; -+ -+ return YAFFS_OK; -+} -+ -+static int nand_writepage( -+ struct yaffs_dev *dev, -+ unsigned page, -+ const unsigned char *data, unsigned data_len, /* page data */ -+ const unsigned char *spare, unsigned spare_len) /* page spare */ -+{ -+ int res; -+ unsigned char spare_buf[64]; //not use malloc, this can be faster -+ rt_memset(spare_buf, 0xFF, sizeof(spare_buf)); -+ rt_memcpy(spare_buf+5, spare, spare_len); -+ -+ res = rt_mtd_nand_write(RT_MTD_NAND_DEVICE(dev->os_context), -+ page, data, data_len, spare_buf, spare_len + 5); -+ if (res != RT_EOK) -+ goto __error; -+ -+ return YAFFS_OK; -+ -+__error: -+ return YAFFS_FAIL; -+} -+ -+ -+/* -+ * yaffs2 configuration -+ */ -+#define CONFIG_YAFFS_ECC_MODE 1 //1 use ecc, 0 no ecc -+#define CONFIG_YAFFS_INBAND_TAGS 0 //1 use in band tags, 0-no in band tags -+#define CONFIG_YAFFS_USE_YAFFS2 1 //1 yaffs2, 0-yaffs1 -+ -+void yaffs_config(ynandif_Geometry * g, struct rt_mtd_nand_device * dev) -+{ -+ rt_memset(g,0,sizeof(ynandif_Geometry)); -+ -+ g->start_block = dev->block_start; -+ g->end_block = dev->block_end; -+ g->dataSize = dev->page_size; -+ g->spareSize = dev->oob_size; -+ g->pagesPerBlock = dev->block_size / dev->page_size; -+ -+ g->hasECC = CONFIG_YAFFS_ECC_MODE; -+ g->inband_tags = CONFIG_YAFFS_INBAND_TAGS; -+ g->useYaffs2 = CONFIG_YAFFS_USE_YAFFS2; -+ -+ g->privateData = dev;//will be copy to dev->os_context. -+ -+ g->initialise = nand_init; -+ g->deinitialise = nand_deinit; -+ g->readChunk = nand_readpage; -+ g->writeChunk = nand_writepage; -+ g->eraseBlock = nand_eraseblock; -+ g->checkBlockOk = nand_checkblock; -+ g->markBlockBad = nand_markbadblk; -+} -+ -+static struct yaffs_dev *ynand_CreatePart(const YCHAR *name, ynandif_Geometry * g) -+{ -+ return yaffs_add_dev_from_geometry(name, g); -+} -+ -+/* configuration for yaffs's log */ -+unsigned yaffs_trace_mask = -+ -+ YAFFS_TRACE_SCAN | -+ YAFFS_TRACE_GC | -+ YAFFS_TRACE_ERASE | -+ YAFFS_TRACE_ERROR | -+ YAFFS_TRACE_TRACING | -+ YAFFS_TRACE_ALLOCATE | -+ YAFFS_TRACE_BAD_BLOCKS | -+ YAFFS_TRACE_VERIFY | -+ -+ 0; -+ -+int yaffs_start(const char * mount_point, ynandif_Geometry * g) -+{ -+ // Stuff to configure YAFFS -+ // Stuff to initialise anything special (eg lock semaphore). -+ yaffsfs_OSInitialisation(); -+ ynand_CreatePart(mount_point, g); -+ -+ return 0; -+} -diff --git a/yaffs_osglue.c b/yaffs_osglue.c -new file mode 100644 -index 0000000..2c34f99 ---- /dev/null -+++ b/yaffs_osglue.c -@@ -0,0 +1,118 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2011 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+#include "yaffscfg.h" -+#include "yaffs_guts.h" -+#include "yaffsfs.h" -+#include "yaffs_trace.h" -+#include -+ -+//#include -+ -+ -+static int yaffsfs_lastError; -+ -+void yaffsfs_SetError(int err) -+{ -+ //Do whatever to set error -+ yaffsfs_lastError = err; -+} -+ -+int yaffsfs_GetLastError(void) -+{ -+ return yaffsfs_lastError; -+} -+ -+ -+#ifdef CONFIG_YAFFS_USE_PTHREADS -+#include -+static pthread_mutex_t mutex1; -+ -+ -+void yaffsfs_Lock(void) -+{ -+ pthread_mutex_lock( &mutex1 ); -+} -+ -+void yaffsfs_Unlock(void) -+{ -+ pthread_mutex_unlock( &mutex1 ); -+} -+ -+void yaffsfs_LockInit(void) -+{ -+ pthread_mutex_init( &mutex1, NULL); -+} -+ -+#else -+ -+static rt_mutex_t mutex = RT_NULL; -+static rt_sem_t sem = RT_NULL; -+void yaffsfs_Lock(void) -+{ -+ rt_mutex_take(mutex, RT_WAITING_FOREVER); -+} -+ -+void yaffsfs_Unlock(void) -+{ -+ rt_mutex_release(mutex); -+} -+ -+void yaffsfs_LockInit(void) -+{ -+ mutex = rt_mutex_create("mutex", RT_IPC_FLAG_FIFO); -+ if (mutex == RT_NULL) -+ { -+ yaffs_trace(YAFFS_TRACE_ERROR, -+ "**>> yaffs error :yaffs_LockInit can't get a mutex!"); -+ } -+ -+} -+#endif -+ -+u32 yaffsfs_CurrentTime(void) -+{ -+ return 0; -+} -+ -+ -+static int yaffs_kill_alloc = 0; -+static size_t total_malloced = 0; -+static size_t malloc_limit = 0 & 6000000; -+ -+void *yaffsfs_malloc(size_t size) -+{ -+ void * this; -+ if(yaffs_kill_alloc) -+ return NULL; -+ if(malloc_limit && malloc_limit <(total_malloced + size) ) -+ return NULL; -+ -+ this = rt_malloc(size); -+ if(this) -+ total_malloced += size; -+ return this; -+} -+ -+void yaffsfs_free(void *ptr) -+{ -+ rt_free(ptr); -+} -+ -+void yaffsfs_OSInitialisation(void) -+{ -+ yaffsfs_LockInit(); -+} -+ -+ diff --git a/components/dfs/include/dfs.h b/components/dfs/include/dfs.h index f17458bd69..7fdcb1cfda 100644 --- a/components/dfs/include/dfs.h +++ b/components/dfs/include/dfs.h @@ -1,21 +1,7 @@ /* - * File : dfs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/include/dfs_file.h b/components/dfs/include/dfs_file.h index 5dc3946899..7ef681a247 100644 --- a/components/dfs/include/dfs_file.h +++ b/components/dfs/include/dfs_file.h @@ -1,21 +1,7 @@ /* - * File : dfs_file.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/include/dfs_fs.h b/components/dfs/include/dfs_fs.h index 38d8766ee1..711771a137 100644 --- a/components/dfs/include/dfs_fs.h +++ b/components/dfs/include/dfs_fs.h @@ -1,21 +1,7 @@ /* - * File : dfs_fs.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/include/dfs_poll.h b/components/dfs/include/dfs_poll.h index cfdf74fbe4..d9597a4364 100644 --- a/components/dfs/include/dfs_poll.h +++ b/components/dfs/include/dfs_poll.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef DFS_POLL_H__ #define DFS_POLL_H__ @@ -6,6 +15,7 @@ #ifdef RT_USING_POSIX #include /* for struct timeval */ +#if !defined(POLLIN) && !defined(POLLOUT) #define POLLIN (0x01) #define POLLRDNORM (0x01) #define POLLRDBAND (0x01) @@ -19,8 +29,6 @@ #define POLLHUP (0x08) #define POLLNVAL (0x10) -#define POLLMASK_DEFAULT (POLLIN | POLLOUT | POLLRDNORM | POLLWRNORM) - typedef unsigned int nfds_t; struct pollfd @@ -29,9 +37,10 @@ struct pollfd short events; short revents; }; +#endif /* !defined(POLLIN) && !defined(POLLOUT) */ +#define POLLMASK_DEFAULT (POLLIN | POLLOUT | POLLRDNORM | POLLWRNORM) int poll(struct pollfd *fds, nfds_t nfds, int timeout); -#endif - -#endif +#endif /* RT_USING_POSIX */ +#endif /* DFS_POLL_H__ */ diff --git a/components/dfs/include/dfs_posix.h b/components/dfs/include/dfs_posix.h index b751f1ed17..bc8ff1c698 100644 --- a/components/dfs/include/dfs_posix.h +++ b/components/dfs/include/dfs_posix.h @@ -1,21 +1,7 @@ /* - * File : dfs_posix.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -55,13 +41,15 @@ int closedir(DIR* d); /* file api*/ int open(const char *file, int flags, ...); int close(int d); -#ifdef RT_USING_NEWLIB + +#if defined(RT_USING_NEWLIB) && defined(_EXFUN) _READ_WRITE_RETURN_TYPE _EXFUN(read, (int __fd, void *__buf, size_t __nbyte)); _READ_WRITE_RETURN_TYPE _EXFUN(write, (int __fd, const void *__buf, size_t __nbyte)); #else int read(int fd, void *buf, size_t len); int write(int fd, const void *buf, size_t len); #endif + off_t lseek(int fd, off_t offset, int whence); int rename(const char *from, const char *to); int unlink(const char *pathname); diff --git a/components/dfs/include/dfs_private.h b/components/dfs/include/dfs_private.h index 43be0db00e..e20680d9df 100644 --- a/components/dfs/include/dfs_private.h +++ b/components/dfs/include/dfs_private.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef DFS_PRIVATE_H__ #define DFS_PRIVATE_H__ diff --git a/components/dfs/include/dfs_select.h b/components/dfs/include/dfs_select.h index 1c51b1df38..3ac5817874 100644 --- a/components/dfs/include/dfs_select.h +++ b/components/dfs/include/dfs_select.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef DFS_SELECT_H__ #define DFS_SELECT_H__ diff --git a/components/dfs/src/dfs.c b/components/dfs/src/dfs.c index 5a98883549..38a1813421 100644 --- a/components/dfs/src/dfs.c +++ b/components/dfs/src/dfs.c @@ -1,21 +1,7 @@ /* - * File : dfs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -199,7 +185,7 @@ int fd_new(void) if (idx == fdt->maxfd) { idx = -(1 + DFS_FD_OFFSET); - dbg_log(DBG_ERROR, "DFS fd new is failed! Could not found an empty fd entry."); + LOG_E( "DFS fd new is failed! Could not found an empty fd entry."); goto __result; } diff --git a/components/dfs/src/dfs_file.c b/components/dfs/src/dfs_file.c index c437b43829..646ae58e36 100644 --- a/components/dfs/src/dfs_file.c +++ b/components/dfs/src/dfs_file.c @@ -1,22 +1,8 @@ /* - * File : dfs_file.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2011, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Copyright (c) 2006-2018, RT-Thread Development Team * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2005-02-22 Bernard The first version. @@ -60,7 +46,7 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) return -ENOMEM; } - dbg_log(DBG_LOG, "open file:%s\n", fullpath); + LOG_D("open file:%s", fullpath); /* Check whether file is already open */ if (fd_is_open(fullpath) == 0) @@ -79,7 +65,7 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) return -ENOENT; } - dbg_log(DBG_LOG, "open in filesystem:%s\n", fs->ops->name); + LOG_D("open in filesystem:%s", fs->ops->name); fd->fops = fs->ops->fops; /* set file ops */ /* initialize the fd item */ @@ -96,7 +82,7 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) else fd->path = rt_strdup(dfs_subdir(fs->path, fullpath)); rt_free(fullpath); - dbg_log(DBG_LOG, "Actual file path: %s\n", fd->path); + LOG_D("Actual file path: %s", fd->path); } else { @@ -119,7 +105,7 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) rt_free(fd->path); fd->path = NULL; - dbg_log(DBG_ERROR, "open failed\n"); + LOG_E("open failed"); return result; } @@ -131,7 +117,7 @@ int dfs_file_open(struct dfs_fd *fd, const char *path, int flags) fd->flags |= DFS_F_DIRECTORY; } - dbg_log(DBG_INFO, "open successful\n"); + LOG_I("open successful"); return 0; } @@ -189,7 +175,7 @@ int dfs_file_ioctl(struct dfs_fd *fd, int cmd, void *args) int mask = O_NONBLOCK | O_APPEND; flags &= mask; - fd->flags &= mask; + fd->flags &= ~mask; fd->flags |= flags; } return 0; @@ -389,8 +375,8 @@ int dfs_file_stat(const char *path, struct stat *buf) if ((fs = dfs_filesystem_lookup(fullpath)) == NULL) { - dbg_log(DBG_ERROR, - "can't find mounted filesystem on this path:%s\n", fullpath); + LOG_E( + "can't find mounted filesystem on this path:%s", fullpath); rt_free(fullpath); return -ENOENT; @@ -419,8 +405,8 @@ int dfs_file_stat(const char *path, struct stat *buf) if (fs->ops->stat == NULL) { rt_free(fullpath); - dbg_log(DBG_ERROR, - "the filesystem didn't implement this function\n"); + LOG_E( + "the filesystem didn't implement this function"); return -ENOSYS; } diff --git a/components/dfs/src/dfs_fs.c b/components/dfs/src/dfs_fs.c index 66740d647e..a183e7f124 100644 --- a/components/dfs/src/dfs_fs.c +++ b/components/dfs/src/dfs_fs.c @@ -1,21 +1,7 @@ /* - * File : dfs_fs.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -69,7 +55,7 @@ int dfs_register(const struct dfs_filesystem_ops *ops) if (empty == NULL) { rt_set_errno(-ENOSPC); - dbg_log(DBG_ERROR, "There is no space to register this file system (%d).\n", ops->name); + LOG_E("There is no space to register this file system (%d).", ops->name); ret = -1; } else if (ret == RT_EOK) @@ -318,7 +304,7 @@ int dfs_mount(const char *device_name, if ((fs == NULL) && (iter == &filesystem_table[DFS_FILESYSTEMS_MAX])) { rt_set_errno(-ENOSPC); - dbg_log(DBG_ERROR, "There is no space to mount this file system (%s).\n", filesystemtype); + LOG_E("There is no space to mount this file system (%s).", filesystemtype); goto err1; } @@ -451,7 +437,7 @@ int dfs_mkfs(const char *fs_name, const char *device_name) if (dev_id == NULL) { rt_set_errno(-ENODEV); - dbg_log(DBG_ERROR, "Device (%s) was not found\n", device_name); + LOG_E("Device (%s) was not found", device_name); return -1; } @@ -472,7 +458,7 @@ int dfs_mkfs(const char *fs_name, const char *device_name) const struct dfs_filesystem_ops *ops = filesystem_operation_table[index]; if (ops->mkfs == NULL) { - dbg_log(DBG_ERROR, "The file system (%s) mkfs function was not implement\n", fs_name); + LOG_E("The file system (%s) mkfs function was not implement", fs_name); rt_set_errno(-ENOSYS); return -1; } @@ -480,7 +466,7 @@ int dfs_mkfs(const char *fs_name, const char *device_name) return ops->mkfs(dev_id); } - dbg_log(DBG_ERROR, "File system (%s) was not found.\n", fs_name); + LOG_E("File system (%s) was not found.", fs_name); return -1; } diff --git a/components/dfs/src/dfs_posix.c b/components/dfs/src/dfs_posix.c index 3d863c4f98..f47a60ee5d 100644 --- a/components/dfs/src/dfs_posix.c +++ b/components/dfs/src/dfs_posix.c @@ -1,21 +1,7 @@ /* - * File : dfs_posix.c - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2004-2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -124,7 +110,7 @@ RTM_EXPORT(close); * @return the actual read data buffer length. If the returned value is 0, it * may be reach the end of file, please check errno. */ -#ifdef RT_USING_NEWLIB +#if defined(RT_USING_NEWLIB) && defined(_EXFUN) _READ_WRITE_RETURN_TYPE _EXFUN(read, (int fd, void *buf, size_t len)) #else int read(int fd, void *buf, size_t len) @@ -168,7 +154,7 @@ RTM_EXPORT(read); * * @return the actual written data buffer length. */ -#ifdef RT_USING_NEWLIB +#if defined(RT_USING_NEWLIB) && defined(_EXFUN) _READ_WRITE_RETURN_TYPE _EXFUN(write, (int fd, const void *buf, size_t len)) #else int write(int fd, const void *buf, size_t len) @@ -455,7 +441,7 @@ int fcntl(int fildes, int cmd, ...) ret = -1; } - return 0; + return ret; } RTM_EXPORT(fcntl); @@ -904,9 +890,9 @@ int access(const char *path, int amode) char *getcwd(char *buf, size_t size) { #ifdef DFS_USING_WORKDIR - rt_enter_critical(); + dfs_lock(); strncpy(buf, working_directory, size); - rt_exit_critical(); + dfs_unlock(); #else rt_kprintf(NO_WORKING_DIR); #endif diff --git a/components/dfs/src/poll.c b/components/dfs/src/poll.c index f2f3fc4c76..6655a8a667 100644 --- a/components/dfs/src/poll.c +++ b/components/dfs/src/poll.c @@ -1,21 +1,7 @@ /* - * File : poll.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/src/select.c b/components/dfs/src/select.c index cbbd159557..b9a444fe44 100644 --- a/components/dfs/src/select.c +++ b/components/dfs/src/select.c @@ -1,21 +1,7 @@ /* - * File : select.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index f27c70c481..9e97aac3c3 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -72,6 +72,10 @@ config RT_USING_PIN bool "Using generic GPIO device drivers" default y +config RT_USING_ADC + bool "Using ADC device drivers" + default n + config RT_USING_PWM bool "Using PWM device drivers" default n @@ -90,6 +94,24 @@ config RT_USING_MTD_NAND default n endif +config RT_USING_MTD + bool "Using Memory Technology Device (MTD)" + default n + + if RT_USING_MTD + config MTD_USING_NOR + bool "Using MTD Nor Flash device" + default n + + config MTD_USING_NAND + bool "Using MTD Nand Flash device" + default n + endif + +config RT_USING_PM + bool "Using Power Management device drivers" + default n + config RT_USING_RTC bool "Using RTC device drivers" default n @@ -100,9 +122,8 @@ config RT_USING_RTC default n config RTC_SYNC_USING_NTP bool "Using NTP auto sync RTC time" - select PKG_USING_NETUTILS - select PKG_NETUTILS_NTP - default n + depends on PKG_NETUTILS_NTP + default y if RTC_SYNC_USING_NTP config RTC_NTP_FIRST_SYNC_DELAY @@ -138,13 +159,20 @@ config RT_USING_SDIO config RT_MMCSD_MAX_PARTITION int "mmcsd max partition" default 16 + config RT_SDIO_DEBUG + bool "Enable SDIO debug log output" + default n endif config RT_USING_SPI bool "Using SPI Bus/Device device drivers" default n - if RT_USING_SPI + if RT_USING_SPI + config RT_USING_QSPI + bool "Enable QSPI mode" + default n + config RT_USING_SPI_MSD bool "Using SD/TF card driver with spi" select RT_USING_DFS @@ -161,6 +189,11 @@ config RT_USING_SPI config RT_SFUD_USING_FLASH_INFO_TABLE bool "Using defined supported flash chip information table" default y + + config RT_SFUD_USING_QSPI + bool "Using QSPI mode support" + select RT_USING_QSPI + default n config RT_DEBUG_SFUD bool "Show more SFUD debug information" @@ -190,32 +223,104 @@ config RT_USING_WDT bool "Using Watch Dog device drivers" default n -config RT_USING_WIFI - bool "Using Wi-Fi network" - default n - - if RT_USING_WIFI - config RT_USING_WLAN_STA - bool "Using station mode" - default y - - config RT_USING_WLAN_AP - bool "Using ap mode" - default n - - config WIFI_DEVICE_STA_NAME - string "the wifi device name for station" - default "w0" - - config WIFI_DEVICE_AP_NAME - string "the wifi device name for ap" - default "ap" - endif - config RT_USING_AUDIO bool "Using Audio device drivers" default n +menu "Using WiFi" + config RT_USING_WIFI + bool "Using Wi-Fi framework" + default n + + if RT_USING_WIFI + config RT_WLAN_DEVICE_STA_NAME + string "The WiFi device name for station" + default "wlan0" + + config RT_WLAN_DEVICE_AP_NAME + string "The WiFi device name for ap" + default "wlan1" + + config RT_WLAN_DEFAULT_PROT + string "Default transport protocol" + default "lwip" + + config RT_WLAN_SCAN_WAIT_MS + int "Set scan timeout time(ms)" + default 10000 + + config RT_WLAN_CONNECT_WAIT_MS + int "Set connect timeout time(ms)" + default 10000 + + config RT_WLAN_SSID_MAX_LENGTH + int "SSID name maximum length" + default 32 + + config RT_WLAN_PASSWORD_MAX_LENGTH + int "Maximum password length" + default 32 + + config RT_WLAN_SCAN_SORT + bool "Automatic sorting of scan results" + default y + + config RT_WLAN_CFG_INFO_MAX + int "Maximum number of WiFi information automatically saved" + default 3 + + config RT_WLAN_WORKQUEUE_THREAD_NAME + string "WiFi work queue thread name" + default "wlan_job" + + config RT_WLAN_WORKQUEUE_THREAD_SIZE + int "wifi work queue thread size" + default 2048 + + config RT_WLAN_WORKQUEUE_THREAD_PRIO + int "WiFi work queue thread priority" + default 22 + + config RT_WLAN_DEV_EVENT_NUM + int "Maximum number of driver events" + default 2 + + config RT_WLAN_PROT_LWIP_PBUF_FORCE + bool "Forced use of PBUF transmission" + default n + + menuconfig RT_WLAN_DEBUG + bool "Enable WLAN Debugging Options" + default n + + if RT_WLAN_DEBUG + config RT_WLAN_CMD_DEBUG + bool "Enable Debugging of wlan_cmd.c" + default n + + config RT_WLAN_MGNT_DEBUG + bool "Enable Debugging of wlan_mgnt.c" + default n + + config RT_WLAN_DEV_DEBUG + bool "Enable Debugging of wlan_dev.c" + default n + + config RT_WLAN_PROT_DEBUG + bool "Enable Debugging of wlan_prot.c" + default n + + config RT_WLAN_CFG_DEBUG + bool "Enable Debugging of wlan_cfg.c" + default n + + config RT_WLAN_LWIP_DEBUG + bool "Enable Debugging of wlan_lwip.c" + default n + endif + endif +endmenu + menu "Using USB" config RT_USING_USB_HOST bool "Using USB host" @@ -303,6 +408,23 @@ menu "Using USB" bool "Enable to use device as winusb device" default n endif + if RT_USB_DEVICE_CDC + config RT_VCOM_TASK_STK_SIZE + int "virtual com thread stack size" + default 512 + config RT_VCOM_TX_USE_DMA + bool "Enable to use dma for vcom tx" + default n + config RT_VCOM_SERNO + string "serial number of virtual com" + default "32021919830108" + config RT_VCOM_SER_LEN + int "serial number length of virtual com" + default 14 + config RT_VCOM_TX_TIMEOUT + int "tx timeout(ticks) of virtual com" + default 1000 + endif if RT_USB_DEVICE_WINUSB config RT_WINUSB_GUID string "Guid for winusb" diff --git a/components/drivers/audio/audio.c b/components/drivers/audio/audio.c index 220a000df1..14dddb38ea 100644 --- a/components/drivers/audio/audio.c +++ b/components/drivers/audio/audio.c @@ -1,21 +1,7 @@ /* - * File : audio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/audio/audio_pipe.c b/components/drivers/audio/audio_pipe.c index 9dc296831e..a372ae0625 100644 --- a/components/drivers/audio/audio_pipe.c +++ b/components/drivers/audio/audio_pipe.c @@ -1,21 +1,7 @@ /* - * File : pipe.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -202,7 +188,7 @@ static rt_err_t rt_pipe_control(rt_device_t dev, int cmd, void *args) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops audio_pipe_ops +const static struct rt_device_ops audio_pipe_ops = { RT_NULL, RT_NULL, diff --git a/components/drivers/audio/audio_pipe.h b/components/drivers/audio/audio_pipe.h index d40d4234b6..c34f72b019 100644 --- a/components/drivers/audio/audio_pipe.h +++ b/components/drivers/audio/audio_pipe.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __AUDIO_PIPE_H__ #define __AUDIO_PIPE_H__ diff --git a/components/drivers/can/can.c b/components/drivers/can/can.c index 98d76cd5b3..e20fcddcff 100644 --- a/components/drivers/can/can.c +++ b/components/drivers/can/can.c @@ -1,21 +1,7 @@ /* - * File : can.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/cputime/cputime.c b/components/drivers/cputime/cputime.c index 20f41b6dac..3ec860d5c5 100644 --- a/components/drivers/cputime/cputime.c +++ b/components/drivers/cputime/cputime.c @@ -1,21 +1,7 @@ /* - * File : cputime.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -68,7 +54,7 @@ uint32_t clock_cpu_microsecond(uint32_t cpu_tick) { float unit = clock_cpu_getres(); - return (cpu_tick * unit) / 1000; + return (uint32_t)((cpu_tick * unit) / 1000); } /** @@ -83,7 +69,7 @@ uint32_t clock_cpu_millisecond(uint32_t cpu_tick) { float unit = clock_cpu_getres(); - return (cpu_tick * unit) / (1000 * 1000); + return (uint32_t)((cpu_tick * unit) / (1000 * 1000)); } /** diff --git a/components/drivers/cputime/cputime_cortexm.c b/components/drivers/cputime/cputime_cortexm.c index 99dc8b013e..05ed6ed447 100644 --- a/components/drivers/cputime/cputime_cortexm.c +++ b/components/drivers/cputime/cputime_cortexm.c @@ -1,21 +1,7 @@ /* - * File : cputime_cortexm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/hwtimer/hwtimer.c b/components/drivers/hwtimer/hwtimer.c index c3e5076343..cd85b3baef 100644 --- a/components/drivers/hwtimer/hwtimer.c +++ b/components/drivers/hwtimer/hwtimer.c @@ -1,21 +1,7 @@ /* - * File : hwtimer.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -30,7 +16,7 @@ rt_inline rt_uint32_t timeout_calc(rt_hwtimer_t *timer, rt_hwtimerval_t *tv) float overflow; float timeout; rt_uint32_t counter; - int i, index; + int i, index = 0; float tv_sec; float devi_min = 1; float devi; diff --git a/components/drivers/i2c/fm24clxx.c b/components/drivers/i2c/fm24clxx.c index bb77d707bf..eecf3d455a 100644 --- a/components/drivers/i2c/fm24clxx.c +++ b/components/drivers/i2c/fm24clxx.c @@ -1,21 +1,7 @@ /* - * File : fm24clxx.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/i2c/fm24clxx.h b/components/drivers/i2c/fm24clxx.h index fa84dd5e29..74ee065470 100644 --- a/components/drivers/i2c/fm24clxx.h +++ b/components/drivers/i2c/fm24clxx.h @@ -1,21 +1,7 @@ /* - * File : fm24clxx.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/i2c/i2c-bit-ops.c b/components/drivers/i2c/i2c-bit-ops.c index d4a26ea72a..26479a1d68 100644 --- a/components/drivers/i2c/i2c-bit-ops.c +++ b/components/drivers/i2c/i2c-bit-ops.c @@ -1,21 +1,7 @@ /* - * File : i2c-bit-ops.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/i2c/i2c_core.c b/components/drivers/i2c/i2c_core.c index 67778ce0d3..f245abb9ca 100644 --- a/components/drivers/i2c/i2c_core.c +++ b/components/drivers/i2c/i2c_core.c @@ -1,21 +1,7 @@ /* - * File : i2c_core.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/i2c/i2c_dev.c b/components/drivers/i2c/i2c_dev.c index 042b7b743a..6c7df8e427 100644 --- a/components/drivers/i2c/i2c_dev.c +++ b/components/drivers/i2c/i2c_dev.c @@ -1,21 +1,7 @@ /* - * File : i2c_dev.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/adc.h b/components/drivers/include/drivers/adc.h new file mode 100644 index 0000000000..8e3498e791 --- /dev/null +++ b/components/drivers/include/drivers/adc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-07 aozima the first version + * 2018-11-16 Ernest Chen add finsh command and update adc function + */ + +#ifndef __ADC_H__ +#define __ADC_H__ +#include + +struct rt_adc_device; +struct rt_adc_ops +{ + rt_err_t (*enabled)(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled); + rt_err_t (*convert)(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value); +}; + +struct rt_adc_device +{ + struct rt_device parent; + const struct rt_adc_ops *ops; +}; +typedef struct rt_adc_device *rt_adc_device_t; + +typedef enum +{ + RT_ADC_CMD_ENABLE, + RT_ADC_CMD_DISABLE, +} rt_adc_cmd_t; + +rt_err_t rt_hw_adc_register(rt_adc_device_t adc,const char *name, const struct rt_adc_ops *ops, const void *user_data); + +rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_uint32_t channel); +rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_uint32_t channel); +rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_uint32_t channel); + +#endif /* __ADC_H__ */ diff --git a/components/drivers/include/drivers/alarm.h b/components/drivers/include/drivers/alarm.h index 99dd8ef9b8..b5ebbc86d9 100644 --- a/components/drivers/include/drivers/alarm.h +++ b/components/drivers/include/drivers/alarm.h @@ -1,21 +1,7 @@ /* - * File : alarm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/audio.h b/components/drivers/include/drivers/audio.h index 04821c2bc8..7d2cb36728 100644 --- a/components/drivers/include/drivers/audio.h +++ b/components/drivers/include/drivers/audio.h @@ -1,21 +1,7 @@ /* - * File : audio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -94,7 +80,7 @@ /* Support Dsp(input/output) Units controls */ #define AUDIO_DSP_PARAM 0 /* get/set all params */ -#define AUDIO_DSP_SAMPLERATE 1 /* Ƶ */ +#define AUDIO_DSP_SAMPLERATE 1 /* 采样频率 */ #define AUDIO_DSP_FMT 2 #define AUDIO_DSP_CHANNELS 3 diff --git a/components/drivers/include/drivers/can.h b/components/drivers/include/drivers/can.h index ecf3b5f51e..c61fb19eaa 100644 --- a/components/drivers/include/drivers/can.h +++ b/components/drivers/include/drivers/can.h @@ -1,21 +1,7 @@ /* - * File : can.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/cputime.h b/components/drivers/include/drivers/cputime.h index c3dd243f11..78c22fc1da 100644 --- a/components/drivers/include/drivers/cputime.h +++ b/components/drivers/include/drivers/cputime.h @@ -1,21 +1,7 @@ /* - * File : cputime.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/hwtimer.h b/components/drivers/include/drivers/hwtimer.h index 24cec74d32..cbfeec2bf8 100644 --- a/components/drivers/include/drivers/hwtimer.h +++ b/components/drivers/include/drivers/hwtimer.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __HWTIMER_H__ #define __HWTIMER_H__ diff --git a/components/drivers/include/drivers/i2c-bit-ops.h b/components/drivers/include/drivers/i2c-bit-ops.h index 6360b99a92..ddf9a36d73 100644 --- a/components/drivers/include/drivers/i2c-bit-ops.h +++ b/components/drivers/include/drivers/i2c-bit-ops.h @@ -1,21 +1,7 @@ /* - * File : i2c-bit-ops.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/i2c.h b/components/drivers/include/drivers/i2c.h index b6f5273722..e2a9e7d0b8 100644 --- a/components/drivers/include/drivers/i2c.h +++ b/components/drivers/include/drivers/i2c.h @@ -1,21 +1,7 @@ /* - * File : i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/i2c_dev.h b/components/drivers/include/drivers/i2c_dev.h index 81e9896bcf..5ef9dd1a8c 100644 --- a/components/drivers/include/drivers/i2c_dev.h +++ b/components/drivers/include/drivers/i2c_dev.h @@ -1,21 +1,7 @@ /* - * File : i2c_dev.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mmc.h b/components/drivers/include/drivers/mmc.h index 6800c2a29e..95dce7178a 100644 --- a/components/drivers/include/drivers/mmc.h +++ b/components/drivers/include/drivers/mmc.h @@ -1,21 +1,7 @@ /* - * File : mmc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mmcsd_card.h b/components/drivers/include/drivers/mmcsd_card.h index 18470a5ea9..3ee5a20465 100644 --- a/components/drivers/include/drivers/mmcsd_card.h +++ b/components/drivers/include/drivers/mmcsd_card.h @@ -1,21 +1,7 @@ /* - * File : mmcsd_card.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mmcsd_cmd.h b/components/drivers/include/drivers/mmcsd_cmd.h index 2700771531..7c2f26e892 100644 --- a/components/drivers/include/drivers/mmcsd_cmd.h +++ b/components/drivers/include/drivers/mmcsd_cmd.h @@ -1,21 +1,7 @@ /* - * File : mmcsd_cmd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mmcsd_core.h b/components/drivers/include/drivers/mmcsd_core.h index 2be758bf82..05a5af6d79 100644 --- a/components/drivers/include/drivers/mmcsd_core.h +++ b/components/drivers/include/drivers/mmcsd_core.h @@ -1,21 +1,7 @@ /* - * File : mmcsd_core.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mmcsd_host.h b/components/drivers/include/drivers/mmcsd_host.h index 877a04d8e0..1253062aef 100644 --- a/components/drivers/include/drivers/mmcsd_host.h +++ b/components/drivers/include/drivers/mmcsd_host.h @@ -1,21 +1,7 @@ /* - * File : mmcsd_host.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mtd.h b/components/drivers/include/drivers/mtd.h new file mode 100644 index 0000000000..fb7ea4389d --- /dev/null +++ b/components/drivers/include/drivers/mtd.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + 2018-09-10 heyuanjie87 first version + + */ + +#ifndef __MTD_H__ +#define __MTD_H__ + +#include +#include +#include + +#define MTD_TYPE_NOR 1 +#define MTD_TYPE_NAND 2 + + /** + * MTD operation modes + * + * @MTD_OPM_PLACE_OOB: OOB data are placed at the given offset (default) + * @MTD_OPM_AUTO_OOB: OOB data are automatically placed at the free areas + * @MTD_OPM_RAW: data are transferred as-is, with no error correction; + */ +enum mtd_opm +{ + MTD_OPM_PLACE_OOB = 0, + MTD_OPM_AUTO_OOB = 1, + MTD_OPM_RAW = 2, +}; + +#ifndef loff_t +typedef long loff_t; +#endif + +struct mtd_oob_region +{ + uint8_t offset; + uint8_t length; +}; + +typedef struct mtd_info +{ + struct rt_device parent; + + const struct mtd_ops *ops; + + uint16_t oob_size; + uint16_t sector_size; /* Minimal writable flash unit size */ + uint32_t block_size:28; /* Erase size for the device */ + uint32_t type:4; + + size_t size; /* Total size of the MTD */ + loff_t offset; /* At which this MTD starts, from the beginning of the MEMORY */ + struct mtd_info *master; + + void *priv; +}rt_mtd_t; + +struct mtd_io_desc +{ + uint8_t mode; /* operation mode(enum mtd_opm) */ + uint8_t ooblen; /* number of oob bytes to write/read */ + uint8_t oobretlen; /* number of oob bytes written/read */ + uint8_t ooboffs; /* offset in the oob area */ + uint8_t *oobbuf; + + size_t datlen; /* number of data bytes to write/read */ + size_t datretlen; /* number of data bytes written/read */ + uint8_t *datbuf; /* if NULL only oob are read/written */ +}; + +struct mtd_ops +{ + int(*erase)(rt_mtd_t *mtd, loff_t addr, size_t len); /* return 0 if success */ + int(*read) (rt_mtd_t *mtd, loff_t from, struct mtd_io_desc *ops); /* return 0 if success */ + int(*write) (rt_mtd_t *mtd, loff_t to, struct mtd_io_desc *ops); /* return 0 if success */ + int(*isbad) (rt_mtd_t *mtd, uint32_t block); /* return 1 if bad, 0 not bad */ + int(*markbad) (rt_mtd_t *mtd, uint32_t block); /* return 0 if success */ +}; + +struct mtd_part +{ + const char *name; /* name of the MTD partion */ + loff_t offset; /* start addr of partion */ + size_t size; /* size of partion */ +}; + +int rt_mtd_erase(rt_mtd_t *mtd, loff_t addr, size_t size); +int rt_mtd_block_erase(rt_mtd_t *mtd, uint32_t block); +int rt_mtd_read_oob(rt_mtd_t *mtd, loff_t from, struct mtd_io_desc *desc); +int rt_mtd_write_oob(rt_mtd_t *mtd, loff_t to, struct mtd_io_desc *desc); +int rt_mtd_read(rt_mtd_t *mtd, loff_t from, uint8_t *buf, size_t len); +int rt_mtd_write(rt_mtd_t *mtd, loff_t to, const uint8_t *buf, size_t len); +int rt_mtd_block_markbad(rt_mtd_t *mtd, uint32_t block); +int rt_mtd_block_isbad(rt_mtd_t *mtd, uint32_t block); + +rt_mtd_t* rt_mtd_get(const char *name); +int rt_mtd_register(rt_mtd_t *master, const struct mtd_part *parts, int np); + +#endif diff --git a/components/drivers/include/drivers/mtd_nand.h b/components/drivers/include/drivers/mtd_nand.h index fb14eb0dcc..8afed000dd 100644 --- a/components/drivers/include/drivers/mtd_nand.h +++ b/components/drivers/include/drivers/mtd_nand.h @@ -1,21 +1,7 @@ /* - * File : mtd_nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mtd_nor.h b/components/drivers/include/drivers/mtd_nor.h index c51ce87f41..32a952f374 100644 --- a/components/drivers/include/drivers/mtd_nor.h +++ b/components/drivers/include/drivers/mtd_nor.h @@ -1,21 +1,7 @@ /* - * File : mtd_nor.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, Shanghai Real-Thread Technology Co., Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/mtdnand.h b/components/drivers/include/drivers/mtdnand.h new file mode 100644 index 0000000000..2e836cb2fb --- /dev/null +++ b/components/drivers/include/drivers/mtdnand.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + 2018-09-10 heyuanjie87 first version + + */ + +#ifndef _MTDNAND_H_ +#define _MTDNAND_H_ + +#include "mtd.h" + + /* Status bits */ +#define NAND_STATUS_FAIL 0x01 +#define NAND_STATUS_FAIL_N1 0x02 +#define NAND_STATUS_WP 0x80 + +typedef enum +{ + NAND_CMD_PAGE_RD, /* read data to chip's page buffer,do WaitBusy after this cmd in low driver */ + NAND_CMD_PAGE_WR0, /* write data to chip's page buffer */ + NAND_CMD_PAGE_WR1, /* do flash programe */ + NAND_CMD_BLK_ERASE, /* erase block */ + NAND_CMD_ECC_EN, /* enable gen HWECC */ + NAND_CMD_ECC_DIS /* disable gen HWECC */ +} nand_cmd_t; + +typedef enum +{ + NAND_ECCM_NONE, + NAND_ECCM_HW, +} nand_eccmode_t; + +struct nand_chip; +struct nand_ops; + +/** +* struct nand_buffers - buffer structure for read/write +* @ecccalc: buffer pointer for calculated ECC, size is oobsize. +* @ecccode: buffer pointer for ECC read from flash, size is oobsize. +* +*/ +struct nand_buffers +{ + uint8_t *ecccalc; + uint8_t *ecccode; +}; + +struct nand_ecc +{ + uint8_t mode; /* nand_eccmode_t */ + uint8_t bytes; /* gen ecc bytes per ecc step(usually 3) */ + uint16_t stepsize:12; /* min 256 */ + uint16_t _step:4; /* */ + + /* driver must set the two interface if HWECC */ + void (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); + /* return max bit flips if can't correct,return -1 ECC is error(0 success) */ + int(*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); + /* ignore if NONECC */ + const struct mtd_oob_region *layout; +}; + +typedef struct nand_chip +{ + rt_mtd_t parent; + + /* driver must init these */ + const struct nand_ops *ops; + struct nand_ecc ecc; + const struct mtd_oob_region *freelayout; + + /* driver do not touch */ + struct nand_buffers buffers; + uint8_t *oob_poi; + uint8_t *pagebuf; + uint32_t size; + uint16_t oobsize; + uint8_t pages_pb; + uint16_t page_size; + int(*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); + int(*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); +}rt_nand_t; + +struct nand_ops +{ + int(*cmdfunc)(rt_nand_t *nand, int cmd, int page, int offset); /* send nand operation cmd, return Status bits(0 success), + if nand is busy please wait in low driver */ + int(*read_buf)(rt_nand_t *nand, uint8_t *buf, int len); /* read data from nand chip's page buffer */ + int(*write_buf)(rt_nand_t *nand, const uint8_t *buf, int len);/* write data to nand chip's page buffer */ + int(*isbad)(rt_nand_t *nand, uint32_t blk); /* if NULL OOB[0] used as bad mark(not 0xff is bad) */ + int(*markbad)(rt_nand_t *nand, uint32_t blk); /* if NULL OOB[0] used as bad mark(set to 0x00) */ +}; + +int rt_mtd_nand_init(rt_nand_t *nand, int blk_size, int page_size, int oob_size); + +#endif /* MTD_NAND_H_ */ diff --git a/components/drivers/include/drivers/mtdnor.h b/components/drivers/include/drivers/mtdnor.h new file mode 100644 index 0000000000..ccb7466b4b --- /dev/null +++ b/components/drivers/include/drivers/mtdnor.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + 2018-09-10 heyuanjie87 first version + + */ + +#ifndef __MTDNOR_H__ +#define __MTDNOR_H__ + +#include + +struct nor_ops; + +typedef struct +{ + rt_mtd_t parent; + + const struct nor_ops *ops; /* operations interface */ +}rt_nor_t; + +struct nor_ops +{ + int (*erase)(rt_nor_t *nor, loff_t addr, size_t len); /* return success erased len or error code */ + int (*read)(rt_nor_t *nor, loff_t addr, uint8_t *buf, size_t len); /* return success data size or error code */ + int (*write)(rt_nor_t *nor, loff_t addr, const uint8_t *buf, size_t len); /* return success data size or error code */ +}; + +int rt_mtd_nor_init(rt_nor_t *nor, int blksize); + +#endif diff --git a/components/drivers/include/drivers/pin.h b/components/drivers/include/drivers/pin.h index de8fd21acc..ca35407932 100644 --- a/components/drivers/include/drivers/pin.h +++ b/components/drivers/include/drivers/pin.h @@ -1,21 +1,7 @@ /* - * File : pin.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/pm.h b/components/drivers/include/drivers/pm.h new file mode 100644 index 0000000000..94d4c8559b --- /dev/null +++ b/components/drivers/include/drivers/pm.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-06-02 Bernard the first version + * 2018-08-02 Tanek split run and sleep modes, support custom mode + */ + +#ifndef __PM_H__ +#define __PM_H__ + +#include + +#ifndef PM_HAS_CUSTOM_CONFIG + +/* All modes used for rt_pm_request() adn rt_pm_release() */ +enum +{ + /* run modes */ + PM_RUN_MODE_NORMAL = 0, + + /* sleep modes */ + PM_SLEEP_MODE_SLEEP, + PM_SLEEP_MODE_TIMER, + PM_SLEEP_MODE_SHUTDOWN, +}; + +/* The name of all modes used in the msh command "pm_dump" */ +#define PM_MODE_NAMES \ +{ \ + "Running Mode", \ + \ + "Sleep Mode", \ + "Timer Mode", \ + "Shutdown Mode", \ +} + +/* run mode count : 1 */ +#define PM_RUN_MODE_COUNT 1 +/* sleep mode count : 3 */ +#define PM_SLEEP_MODE_COUNT 3 + +/* support redefining default run mode */ +#ifndef PM_RUN_MODE_DEFAULT +#define PM_RUN_MODE_DEFAULT 0 +#endif + +/* support redefining default sleep mode */ +#ifndef PM_SLEEP_MODE_DEFAULT +#define PM_SLEEP_MODE_DEFAULT (PM_SLEEP_MODE_START) +#endif + +/* support redefining the minimum tick into sleep mode */ +#ifndef PM_MIN_ENTER_SLEEP_TICK +#define PM_MIN_ENTER_SLEEP_TICK (1) +#endif + +#else /* PM_HAS_CUSTOM_CONFIG */ + +#include + +#ifndef PM_RUN_MODE_COUNT +#error "You must defined PM_RUN_MODE_COUNT on pm_cfg.h" +#endif + +#ifndef PM_SLEEP_MODE_COUNT +#error "You must defined PM_SLEEP_MODE_COUNT on pm_cfg.h" +#endif + +#ifndef PM_MODE_DEFAULT +#error "You must defined PM_MODE_DEFAULT on pm_cfg.h" +#endif + +#ifndef PM_MODE_NAMES +#error "You must defined PM_MODE_NAMES on pm_cfg.h" +#endif + +#ifndef PM_RUN_MODE_DEFAULT +#error "You must defined PM_RUN_MODE_DEFAULT on pm_cfg.h" +#endif + +/* The default sleep mode(PM_SLEEP_MODE_DEFAULT) are not required. + * If the default mode is defined, it is requested once in rt_system_pm_init() + */ + +#endif /* PM_HAS_CUSTOM_CONFIG */ + +/* run mode must start at 0 */ +#define PM_RUN_MODE_START 0 +/* the values of the run modes and sleep mode must be consecutive */ +#define PM_SLEEP_MODE_START PM_RUN_MODE_COUNT +/* all mode count */ +#define PM_MODE_COUNT (PM_RUN_MODE_COUNT + PM_SLEEP_MODE_COUNT) +/* The last mode, will be request in rt_system_pm_init() */ +#define PM_MODE_MAX (PM_RUN_MODE_COUNT + PM_SLEEP_MODE_COUNT - 1) + +#if PM_MODE_COUNT > 32 +#error "The number of modes cannot exceed 32" +#endif + +/** + * device control flag to request or release power + */ +#define RT_PM_DEVICE_CTRL_REQUEST 0x01 +#define RT_PM_DEVICE_CTRL_RELEASE 0x02 + +struct rt_pm; + +/** + * low power mode operations + */ +struct rt_pm_ops +{ + void (*enter)(struct rt_pm *pm); + void (*exit)(struct rt_pm *pm); + +#if PM_RUN_MODE_COUNT > 1 + void (*frequency_change)(struct rt_pm *pm, rt_uint32_t frequency); +#endif + + void (*timer_start)(struct rt_pm *pm, rt_uint32_t timeout); + void (*timer_stop)(struct rt_pm *pm); + rt_tick_t (*timer_get_tick)(struct rt_pm *pm); +}; + +struct rt_device_pm_ops +{ +#if PM_RUN_MODE_COUNT > 1 + void (*frequency_change)(const struct rt_device* device); +#endif + + void (*suspend)(const struct rt_device* device); + void (*resume) (const struct rt_device* device); +}; + +struct rt_device_pm +{ + const struct rt_device* device; + const struct rt_device_pm_ops* ops; +}; + +/** + * power management + */ +struct rt_pm +{ + struct rt_device parent; + + /* modes */ + rt_uint8_t modes[PM_MODE_COUNT]; + rt_uint8_t current_mode; /* current pm mode */ + rt_uint8_t exit_count; + + /* the list of device, which has PM feature */ + rt_uint8_t device_pm_number; + struct rt_device_pm* device_pm; + struct rt_semaphore device_lock; + + /* if the mode has timer, the corresponding bit is 1*/ + rt_uint32_t timer_mask; + + const struct rt_pm_ops *ops; +}; + +void rt_pm_enter(void); +void rt_pm_exit(void); + +void rt_pm_request(rt_ubase_t mode); +void rt_pm_release(rt_ubase_t mode); + +void rt_pm_register_device(struct rt_device* device, const struct rt_device_pm_ops* ops); +void rt_pm_unregister_device(struct rt_device* device); + +void rt_system_pm_init(const struct rt_pm_ops *ops, + rt_uint8_t timer_mask, + void *user_data); + +#endif /* __PM_H__ */ diff --git a/components/drivers/include/drivers/rt_drv_pwm.h b/components/drivers/include/drivers/rt_drv_pwm.h index ffd08edabb..16de4c6ab8 100644 --- a/components/drivers/include/drivers/rt_drv_pwm.h +++ b/components/drivers/include/drivers/rt_drv_pwm.h @@ -1,21 +1,7 @@ /* - * File : rt_drv_pwm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,6 +11,9 @@ #ifndef __DRV_PWM_H_INCLUDE__ #define __DRV_PWM_H_INCLUDE__ +#include +#include + #define PWM_CMD_ENABLE (128 + 0) #define PWM_CMD_DISABLE (128 + 1) #define PWM_CMD_SET (128 + 2) @@ -49,6 +38,10 @@ struct rt_device_pwm const struct rt_pwm_ops *ops; }; -extern rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data); +rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data); + +rt_err_t rt_pwm_enable(struct rt_device_pwm *device, int channel); +rt_err_t rt_pwm_disable(struct rt_device_pwm *device, int channel); +rt_err_t rt_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse); #endif /* __DRV_PWM_H_INCLUDE__ */ diff --git a/components/drivers/include/drivers/rtc.h b/components/drivers/include/drivers/rtc.h index 7e89bd3704..1cd88a7be3 100644 --- a/components/drivers/include/drivers/rtc.h +++ b/components/drivers/include/drivers/rtc.h @@ -1,21 +1,7 @@ /* - * File : rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/sd.h b/components/drivers/include/drivers/sd.h index 7d5fcacade..e096df9372 100644 --- a/components/drivers/include/drivers/sd.h +++ b/components/drivers/include/drivers/sd.h @@ -1,21 +1,7 @@ /* - * File : sd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/sdio.h b/components/drivers/include/drivers/sdio.h index 2cd1c7dfd1..e4bf4a048f 100644 --- a/components/drivers/include/drivers/sdio.h +++ b/components/drivers/include/drivers/sdio.h @@ -1,21 +1,7 @@ /* - * File : sdio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/sdio_func_ids.h b/components/drivers/include/drivers/sdio_func_ids.h index 9fee7c238a..79085a5933 100644 --- a/components/drivers/include/drivers/sdio_func_ids.h +++ b/components/drivers/include/drivers/sdio_func_ids.h @@ -1,21 +1,7 @@ /* - * File : sdio_func_ids.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h index 2abf925854..af5d626251 100644 --- a/components/drivers/include/drivers/serial.h +++ b/components/drivers/include/drivers/serial.h @@ -1,21 +1,7 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/spi.h b/components/drivers/include/drivers/spi.h index 0fbaabe5dd..04a65421a5 100644 --- a/components/drivers/include/drivers/spi.h +++ b/components/drivers/include/drivers/spi.h @@ -1,21 +1,7 @@ /* - * File : spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -59,6 +45,9 @@ extern "C"{ #define RT_SPI_MODE_MASK (RT_SPI_CPHA | RT_SPI_CPOL | RT_SPI_MSB) +#define RT_SPI_BUS_MODE_SPI (1<<0) +#define RT_SPI_BUS_MODE_QSPI (1<<1) + #define RT_SPI_CS_HIGH (1<<4) /* Chipselect active high */ #define RT_SPI_NO_CS (1<<5) /* No chipselect */ #define RT_SPI_3WIRE (1<<6) /* SI/SO pin shared */ @@ -94,6 +83,7 @@ struct rt_spi_ops; struct rt_spi_bus { struct rt_device parent; + rt_uint8_t mode; const struct rt_spi_ops *ops; struct rt_mutex lock; @@ -120,6 +110,55 @@ struct rt_spi_device struct rt_spi_configuration config; void *user_data; }; + +struct rt_qspi_message +{ + struct rt_spi_message parent; + + /* instruction stage */ + struct + { + rt_uint8_t content; + rt_uint8_t qspi_lines; + } instruction; + + /* address and alternate_bytes stage */ + struct + { + rt_uint32_t content; + rt_uint8_t size; + rt_uint8_t qspi_lines; + } address, alternate_bytes; + + /* dummy_cycles stage */ + rt_uint32_t dummy_cycles; + + /* number of lines in qspi data stage, the other configuration items are in parent */ + rt_uint8_t qspi_data_lines; +}; + +struct rt_qspi_configuration +{ + struct rt_spi_configuration parent; + /* The size of medium */ + rt_uint32_t medium_size; + /* double data rate mode */ + rt_uint8_t ddr_mode; + /* the data lines max width which QSPI bus supported, such as 1, 2, 4 */ + rt_uint8_t qspi_dl_width ; +}; + +struct rt_qspi_device +{ + struct rt_spi_device parent; + + struct rt_qspi_configuration config; + + void (*enter_qspi_mode)(struct rt_qspi_device *device); + + void (*exit_qspi_mode)(struct rt_qspi_device *device); +}; + #define SPI_DEVICE(dev) ((struct rt_spi_device *)(dev)) /* register a SPI bus */ @@ -269,6 +308,61 @@ rt_inline void rt_spi_message_append(struct rt_spi_message *list, message->next = RT_NULL; } +/** + * This function can set configuration on QSPI device. + * + * @param device the QSPI device attached to QSPI bus. + * @param cfg the configuration pointer. + * + * @return the actual length of transmitted. + */ +rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configuration *cfg); + +/** + * This function can register a SPI bus for QSPI mode. + * + * @param bus the SPI bus for QSPI mode. + * @param name The name of the spi bus. + * @param ops the SPI bus instance to be registered. + * + * @return the actual length of transmitted. + */ +rt_err_t rt_qspi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops); + +/** + * This function transmits data to QSPI device. + * + * @param device the QSPI device attached to QSPI bus. + * @param message the message pointer. + * + * @return the actual length of transmitted. + */ +rt_size_t rt_qspi_transfer_message(struct rt_qspi_device *device, struct rt_qspi_message *message); + +/** + * This function can send data then receive data from QSPI device + * + * @param device the QSPI device attached to QSPI bus. + * @param send_buf the buffer to be transmitted to QSPI device. + * @param send_length the number of data to be transmitted. + * @param recv_buf the buffer to be recivied from QSPI device. + * @param recv_length the data to be recivied. + * + * @return the status of transmit. + */ +rt_err_t rt_qspi_send_then_recv(struct rt_qspi_device *device, const void *send_buf, rt_size_t send_length,void *recv_buf, rt_size_t recv_length); + +/** + * This function can send data to QSPI device + * + * @param device the QSPI device attached to QSPI bus. + * @param send_buf the buffer to be transmitted to QSPI device. + * @param send_length the number of data to be transmitted. + * + * @return the status of transmit. + */ +rt_err_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_size_t length); + #ifdef __cplusplus } #endif diff --git a/components/drivers/include/drivers/usb_common.h b/components/drivers/include/drivers/usb_common.h index 922682b1af..c26d83391e 100644 --- a/components/drivers/include/drivers/usb_common.h +++ b/components/drivers/include/drivers/usb_common.h @@ -1,21 +1,7 @@ /* - * File : usb_common.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -230,6 +216,19 @@ extern "C" { #define HID_REPORT_ID_GENERAL 5 #define HID_REPORT_ID_MOUSE 6 +/* + * Time of usb timeout + */ +#ifndef USB_TIMEOUT_BASIC +#define USB_TIMEOUT_BASIC (RT_TICK_PER_SECOND) /* 1s */ +#endif +#ifndef USB_TIMEOUT_LONG +#define USB_TIMEOUT_LONG (RT_TICK_PER_SECOND * 5) /* 5s */ +#endif +#ifndef USB_DEBOUNCE_TIME +#define USB_DEBOUNCE_TIME (RT_TICK_PER_SECOND / 5) /* 0.2s */ +#endif + #define uswap_32(x) \ ((((x) & 0xff000000) >> 24) | \ (((x) & 0x00ff0000) >> 8) | \ diff --git a/components/drivers/include/drivers/usb_device.h b/components/drivers/include/drivers/usb_device.h index 572c7d0dff..26f0c4cf4a 100644 --- a/components/drivers/include/drivers/usb_device.h +++ b/components/drivers/include/drivers/usb_device.h @@ -1,21 +1,7 @@ /* - * File : usb_device.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -31,6 +17,10 @@ #include #include "drivers/usb_common.h" +#ifdef __cplusplus +extern "C" { +#endif + /* Vendor ID */ #ifdef USB_VENDOR_ID #define _VENDOR_ID USB_VENDOR_ID @@ -467,4 +457,9 @@ rt_inline void usbd_os_proerty_descriptor_send(ufunction_t func, ureq_t setup, u } rt_usbd_ep0_write(func->device, data, setup->wLength); } + +#ifdef __cplusplus +} +#endif + #endif diff --git a/components/drivers/include/drivers/usb_host.h b/components/drivers/include/drivers/usb_host.h index 92adaa3d47..2a68f4edb5 100644 --- a/components/drivers/include/drivers/usb_host.h +++ b/components/drivers/include/drivers/usb_host.h @@ -1,21 +1,7 @@ /* - * File : usb_host.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/watchdog.h b/components/drivers/include/drivers/watchdog.h index 5c74dc82be..f80ded58aa 100644 --- a/components/drivers/include/drivers/watchdog.h +++ b/components/drivers/include/drivers/watchdog.h @@ -1,21 +1,7 @@ /* - * File : watchdog.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012-2014, Shanghai Real-Thread Electronic Technology Co.,Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/drivers/wlan.h b/components/drivers/include/drivers/wlan.h new file mode 100644 index 0000000000..724e61da78 --- /dev/null +++ b/components/drivers/include/drivers/wlan.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-15 tyx the first version + */ + +#ifndef __WLAN_H__ +#define __WLAN_H__ + +#include +#include +#include +#include +#include +#include + +#endif diff --git a/components/drivers/include/ipc/completion.h b/components/drivers/include/ipc/completion.h index e3e883ba8b..acfcaa3995 100644 --- a/components/drivers/include/ipc/completion.h +++ b/components/drivers/include/ipc/completion.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef COMPLETION_H_ #define COMPLETION_H_ diff --git a/components/drivers/include/ipc/dataqueue.h b/components/drivers/include/ipc/dataqueue.h index 44ffed655e..f584c267bf 100644 --- a/components/drivers/include/ipc/dataqueue.h +++ b/components/drivers/include/ipc/dataqueue.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef DATAQUEUE_H__ #define DATAQUEUE_H__ diff --git a/components/drivers/include/ipc/pipe.h b/components/drivers/include/ipc/pipe.h index ca20c2a453..25b19f540d 100644 --- a/components/drivers/include/ipc/pipe.h +++ b/components/drivers/include/ipc/pipe.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef PIPE_H__ #define PIPE_H__ diff --git a/components/drivers/include/ipc/poll.h b/components/drivers/include/ipc/poll.h index 0279fe3b5d..8c68a96af8 100644 --- a/components/drivers/include/ipc/poll.h +++ b/components/drivers/include/ipc/poll.h @@ -1,21 +1,7 @@ /* - * File : poll.h - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2006-2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/ipc/ringblk_buf.h b/components/drivers/include/ipc/ringblk_buf.h new file mode 100644 index 0000000000..94fc2cfff3 --- /dev/null +++ b/components/drivers/include/ipc/ringblk_buf.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-25 armink the first version + */ + +#ifndef _RINGBLK_BUF_H_ +#define _RINGBLK_BUF_H_ + +/* + * Introduction: + * The rbb is the ring buffer which is composed with many blocks. It is different from the ring buffer. + * The ring buffer is only composed with chars. The rbb put and get supported zero copies. So the rbb + * is very suitable for put block and get block by a certain order. Such as DMA block transmit, + * communicate frame send/recv, and so on. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +enum rt_rbb_status +{ + /* unused status when first initialize or after blk_free() */ + RT_RBB_BLK_UNUSED, + /* initialized status after blk_alloc() */ + RT_RBB_BLK_INITED, + /* put status after blk_put() */ + RT_RBB_BLK_PUT, + /* get status after blk_get() */ + RT_RBB_BLK_GET, +}; +typedef enum rt_rbb_status rt_rbb_status_t; + +/** + * the block of rbb + */ +struct rt_rbb_blk +{ + rt_rbb_status_t status :8; + /* less then 2^24 */ + rt_size_t size :24; + rt_uint8_t *buf; + rt_slist_t list; +}; +typedef struct rt_rbb_blk *rt_rbb_blk_t; + +/** + * Rbb block queue: the blocks (from block1->buf to blockn->buf) memory which on this queue is continuous. + */ +struct rt_rbb_blk_queue +{ + rt_rbb_blk_t blocks; + rt_size_t blk_num; +}; +typedef struct rt_rbb_blk_queue *rt_rbb_blk_queue_t; + +/** + * ring block buffer + */ +struct rt_rbb +{ + rt_uint8_t *buf; + rt_size_t buf_size; + /* all of blocks */ + rt_rbb_blk_t blk_set; + rt_size_t blk_max_num; + /* saved the initialized and put status blocks */ + rt_slist_t blk_list; +}; +typedef struct rt_rbb *rt_rbb_t; + +/* rbb (ring block buffer) API */ +void rt_rbb_init(rt_rbb_t rbb, rt_uint8_t *buf, rt_size_t buf_size, rt_rbb_blk_t block_set, rt_size_t blk_max_num); +rt_rbb_t rt_rbb_create(rt_size_t buf_size, rt_size_t blk_max_num); +void rt_rbb_destroy(rt_rbb_t rbb); +rt_size_t rt_rbb_get_buf_size(rt_rbb_t rbb); + +/* rbb block API */ +rt_rbb_blk_t rt_rbb_blk_alloc(rt_rbb_t rbb, rt_size_t blk_size); +void rt_rbb_blk_put(rt_rbb_blk_t block); +rt_rbb_blk_t rt_rbb_blk_get(rt_rbb_t rbb); +rt_size_t rt_rbb_blk_size(rt_rbb_blk_t block); +rt_uint8_t *rt_rbb_blk_buf(rt_rbb_blk_t block); +void rt_rbb_blk_free(rt_rbb_t rbb, rt_rbb_blk_t block); + +/* rbb block queue API */ +rt_size_t rt_rbb_blk_queue_get(rt_rbb_t rbb, rt_size_t queue_data_len, rt_rbb_blk_queue_t blk_queue); +rt_size_t rt_rbb_blk_queue_len(rt_rbb_blk_queue_t blk_queue); +rt_uint8_t *rt_rbb_blk_queue_buf(rt_rbb_blk_queue_t blk_queue); +void rt_rbb_blk_queue_free(rt_rbb_t rbb, rt_rbb_blk_queue_t blk_queue); +rt_size_t rt_rbb_next_blk_queue_len(rt_rbb_t rbb); + + +#ifdef __cplusplus +} +#endif + +#endif /* _RINGBLK_BUF_H_ */ diff --git a/components/drivers/include/ipc/ringbuffer.h b/components/drivers/include/ipc/ringbuffer.h index 4cfab6d69c..4487d02c47 100644 --- a/components/drivers/include/ipc/ringbuffer.h +++ b/components/drivers/include/ipc/ringbuffer.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef RINGBUFFER_H__ #define RINGBUFFER_H__ diff --git a/components/drivers/include/ipc/waitqueue.h b/components/drivers/include/ipc/waitqueue.h index 8cb0989f73..e26ec1e896 100644 --- a/components/drivers/include/ipc/waitqueue.h +++ b/components/drivers/include/ipc/waitqueue.h @@ -1,21 +1,7 @@ /* - * File : waitqueue.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/include/ipc/workqueue.h b/components/drivers/include/ipc/workqueue.h index 0b044b5ad3..9e23e181b1 100644 --- a/components/drivers/include/ipc/workqueue.h +++ b/components/drivers/include/ipc/workqueue.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef WORKQUEUE_H__ #define WORKQUEUE_H__ diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index e3c826fe53..d59b40cc47 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -1,21 +1,7 @@ /* - * File : rtdevice.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -35,6 +21,7 @@ #include "ipc/waitqueue.h" #include "ipc/pipe.h" #include "ipc/poll.h" +#include "ipc/ringblk_buf.h" #ifdef __cplusplus extern "C" { @@ -112,10 +99,29 @@ extern "C" { #include "drivers/cputime.h" #endif +#ifdef RT_USING_ADC +#include "drivers/adc.h" +#endif + #ifdef RT_USING_PWM #include "drivers/rt_drv_pwm.h" #endif +#ifdef RT_USING_PM +#include "drivers/pm.h" +#endif + +#ifdef RT_USING_WIFI +#include "drivers/wlan.h" +#endif + +#ifdef MTD_USING_NOR +#include "drivers/mtdnor.h" +#endif +#ifdef MTD_USING_NAND +#include "drivers/mtdnand.h" +#endif + #ifdef __cplusplus } #endif diff --git a/components/drivers/misc/SConscript b/components/drivers/misc/SConscript index 4cc5f80084..c45ba524c5 100644 --- a/components/drivers/misc/SConscript +++ b/components/drivers/misc/SConscript @@ -7,7 +7,10 @@ group = [] if GetDepend(['RT_USING_PIN']): src = src + ['pin.c'] - + +if GetDepend(['RT_USING_ADC']): + src = src + ['adc.c'] + if GetDepend(['RT_USING_PWM']): src = src + ['rt_drv_pwm.c'] diff --git a/components/drivers/misc/adc.c b/components/drivers/misc/adc.c new file mode 100644 index 0000000000..aa3a3b7801 --- /dev/null +++ b/components/drivers/misc/adc.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-07 aozima the first version + * 2018-11-16 Ernest Chen add finsh command and update adc function + */ + +#include +#include + +#include +#include + +#define DBG_ENABLE +#define DBG_SECTION_NAME "adc" +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +static rt_size_t _adc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_err_t result = RT_EOK; + rt_size_t i; + struct rt_adc_device *adc = (struct rt_adc_device *)dev; + rt_uint32_t *value = (rt_uint32_t *)buffer; + + for (i = 0; i < size; i += sizeof(int)) + { + result = adc->ops->convert(adc, pos + i, value); + if (result != RT_EOK) + { + return 0; + } + value++; + } + + return i; +} + +static rt_err_t _adc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + rt_adc_device_t adc = (struct rt_adc_device *)dev; + + if (adc->ops->enabled != RT_NULL) + { + return -RT_ENOSYS; + } + if (cmd == RT_ADC_CMD_ENABLE) + { + result = adc->ops->enabled(adc, (rt_uint32_t)args, RT_TRUE); + } + else if (cmd == RT_ADC_CMD_DISABLE) + { + result = adc->ops->enabled(adc, (rt_uint32_t)args, RT_FALSE); + } + + return result; +} + +rt_err_t rt_hw_adc_register(rt_adc_device_t device, const char *name, const struct rt_adc_ops *ops, const void *user_data) +{ + rt_err_t result = RT_EOK; + RT_ASSERT(ops != RT_NULL && ops->convert != RT_NULL); + + device->parent.type = RT_Device_Class_Miscellaneous; + device->parent.init = RT_NULL; + device->parent.open = RT_NULL; + device->parent.close = RT_NULL; + device->parent.read = _adc_read; + device->parent.write = RT_NULL; + device->parent.control = _adc_control; + + device->ops = ops; + device->parent.user_data = (void *)user_data; + + result = rt_device_register(&device->parent, name, RT_DEVICE_FLAG_RDWR); + + return result; +} + +rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_uint32_t channel) +{ + rt_uint32_t value; + + RT_ASSERT(dev); + + dev->ops->convert(dev, channel, &value); + + return value; +} + +rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_uint32_t channel) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(dev); + if (dev->ops->enabled != RT_NULL) + { + result = dev->ops->enabled(dev, channel, RT_TRUE); + } + else + { + result = -RT_ENOSYS; + } + + return result; +} + +rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_uint32_t channel) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(dev); + if (dev->ops->enabled != RT_NULL) + { + result = dev->ops->enabled(dev, channel, RT_FALSE); + } + else + { + result = -RT_ENOSYS; + } + + return result; +} + +#ifdef FINSH_USING_MSH + +static int adc(int argc, char **argv) +{ + int value = 0; + int result = RT_EOK; + static rt_adc_device_t adc_device = RT_NULL; + char *result_str; + + if (argc > 1) + { + if (!strcmp(argv[1], "probe")) + { + if (argc == 3) + { + adc_device = (rt_adc_device_t)rt_device_find(argv[2]); + result_str = (adc_device == RT_NULL) ? "failure" : "success"; + rt_kprintf("probe %s %s \n", argv[2], result_str); + } + else + { + rt_kprintf("adc probe - probe adc by name\n"); + } + } + else + { + if (adc_device == RT_NULL) + { + rt_kprintf("Please using 'adc probe ' first\n"); + return -RT_ERROR; + } + if (!strcmp(argv[1], "enable")) + { + if (argc == 3) + { + result = rt_adc_enable(adc_device, atoi(argv[2])); + result_str = (result == RT_EOK) ? "success" : "failure"; + rt_kprintf("%s channel %d enables %s \n", adc_device->parent.parent.name, atoi(argv[2]), result_str); + } + else + { + rt_kprintf("adc enable - enable adc channel\n"); + } + } + else if (!strcmp(argv[1], "read")) + { + if (argc == 3) + { + value = rt_adc_read(adc_device, atoi(argv[2])); + rt_kprintf("%s channel %d read value is 0x%08X \n", adc_device->parent.parent.name, atoi(argv[2]), value); + } + else + { + rt_kprintf("adc read - read adc value on the channel\n"); + } + } + else if (!strcmp(argv[1], "disable")) + { + if (argc == 3) + { + result = rt_adc_disable(adc_device, atoi(argv[2])); + result_str = (result == RT_EOK) ? "success" : "failure"; + rt_kprintf("%s channel %d disable %s \n", adc_device->parent.parent.name, atoi(argv[2]), result_str); + } + else + { + rt_kprintf("adc disable - disable adc channel\n"); + } + } + else + { + rt_kprintf("Unknown command. Please enter 'adc' for help\n"); + } + } + } + else + { + rt_kprintf("Usage: \n"); + rt_kprintf("adc probe - probe adc by name\n"); + rt_kprintf("adc read - read adc value on the channel\n"); + rt_kprintf("adc disable - disable adc channel\n"); + rt_kprintf("adc enable - enable adc channel\n"); + result = -RT_ERROR; + } + return RT_EOK; +} +MSH_CMD_EXPORT(adc, adc function); + +#endif /* FINSH_USING_MSH */ diff --git a/components/drivers/misc/pin.c b/components/drivers/misc/pin.c index ce78f97f87..aca58ee21b 100644 --- a/components/drivers/misc/pin.c +++ b/components/drivers/misc/pin.c @@ -1,21 +1,7 @@ /* - * File : pin.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/misc/rt_drv_pwm.c b/components/drivers/misc/rt_drv_pwm.c index 6884f8cfe4..2b7986b4d8 100644 --- a/components/drivers/misc/rt_drv_pwm.c +++ b/components/drivers/misc/rt_drv_pwm.c @@ -1,21 +1,7 @@ /* - * File : rt_drv_pwm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,9 +10,7 @@ #include -#include -#include - +#include static rt_err_t _pwm_control(rt_device_t dev, int cmd, void *args) { @@ -99,27 +83,41 @@ static rt_size_t _pwm_write(rt_device_t dev, rt_off_t pos, const void *buffer, r { return 0; } - } return size; } +#ifdef RT_USING_DEVICE_OPS +static const struct rt_device_ops pwm_device_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + _pwm_read, + _pwm_write, + _pwm_control +}; +#endif /* RT_USING_DEVICE_OPS */ + rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data) { rt_err_t result = RT_EOK; memset(device, 0, sizeof(struct rt_device_pwm)); +#ifdef RT_USING_DEVICE_OPS + device->parent.ops = &pwm_device_ops; +#else + device->parent.init = RT_NULL; + device->parent.open = RT_NULL; + device->parent.close = RT_NULL; + device->parent.read = _pwm_read; + device->parent.write = _pwm_write; + device->parent.control = _pwm_control; +#endif /* RT_USING_DEVICE_OPS */ + device->parent.type = RT_Device_Class_Miscellaneous; - - device->parent.init = RT_NULL; - device->parent.open = RT_NULL; - device->parent.close = RT_NULL; - device->parent.read = _pwm_read; - device->parent.write = _pwm_write; - device->parent.control = _pwm_control; - device->ops = ops; device->parent.user_data = (void *)user_data; @@ -128,10 +126,9 @@ rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, return result; } -rt_err_t rt_pwm_enable(int channel) +rt_err_t rt_pwm_enable(struct rt_device_pwm *device, int channel) { rt_err_t result = RT_EOK; - struct rt_device *device = rt_device_find("pwm"); struct rt_pwm_configuration configuration = {0}; if (!device) @@ -140,15 +137,30 @@ rt_err_t rt_pwm_enable(int channel) } configuration.channel = channel; - result = rt_device_control(device, PWM_CMD_ENABLE, &configuration); + result = rt_device_control(&device->parent, PWM_CMD_ENABLE, &configuration); return result; } -rt_err_t rt_pwm_set(int channel, rt_uint32_t period, rt_uint32_t pulse) +rt_err_t rt_pwm_disable(struct rt_device_pwm *device, int channel) +{ + rt_err_t result = RT_EOK; + struct rt_pwm_configuration configuration = {0}; + + if (!device) + { + return -RT_EIO; + } + + configuration.channel = channel; + result = rt_device_control(&device->parent, PWM_CMD_DISABLE, &configuration); + + return result; +} + +rt_err_t rt_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse) { rt_err_t result = RT_EOK; - struct rt_device *device = rt_device_find("pwm"); struct rt_pwm_configuration configuration = {0}; if (!device) @@ -159,12 +171,11 @@ rt_err_t rt_pwm_set(int channel, rt_uint32_t period, rt_uint32_t pulse) configuration.channel = channel; configuration.period = period; configuration.pulse = pulse; - result = rt_device_control(device, PWM_CMD_SET, &configuration); + result = rt_device_control(&device->parent, PWM_CMD_SET, &configuration); return result; } - #ifdef RT_USING_FINSH #include @@ -175,33 +186,75 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_pwm_set, pwm_set, set pwm.); static int pwm_enable(int argc, char **argv) { int result = 0; + struct rt_device_pwm *device = RT_NULL; - if (argc != 2) + if (argc != 3) { - rt_kprintf("Usage: pwm_enable 1\n"); + rt_kprintf("Usage: pwm_enable pwm1 1\n"); result = -RT_ERROR; goto _exit; } - result = rt_pwm_enable(atoi(argv[1])); + device = (struct rt_device_pwm *)rt_device_find(argv[1]); + if (!device) + { + result = -RT_EIO; + goto _exit; + } + + result = rt_pwm_enable(device, atoi(argv[2])); _exit: return result; } -MSH_CMD_EXPORT(pwm_enable, pwm_enable 1); +MSH_CMD_EXPORT(pwm_enable, pwm_enable pwm1 1); -static int pwm_set(int argc, char **argv) +static int pwm_disable(int argc, char **argv) { int result = 0; + struct rt_device_pwm *device = RT_NULL; - if (argc != 4) + if (argc != 3) { - rt_kprintf("Usage: pwm_set 1 100 50\n"); + rt_kprintf("Usage: pwm_enable pwm1 1\n"); result = -RT_ERROR; goto _exit; } - result = rt_pwm_set(atoi(argv[1]), atoi(argv[2]), atoi(argv[3])); + device = (struct rt_device_pwm *)rt_device_find(argv[1]); + if (!device) + { + result = -RT_EIO; + goto _exit; + } + + result = rt_pwm_disable(device, atoi(argv[2])); + +_exit: + return result; +} +MSH_CMD_EXPORT(pwm_disable, pwm_disable pwm1 1); + +static int pwm_set(int argc, char **argv) +{ + int result = 0; + struct rt_device_pwm *device = RT_NULL; + + if (argc != 5) + { + rt_kprintf("Usage: pwm_set pwm1 1 100 50\n"); + result = -RT_ERROR; + goto _exit; + } + + device = (struct rt_device_pwm *)rt_device_find(argv[1]); + if (!device) + { + result = -RT_EIO; + goto _exit; + } + + result = rt_pwm_set(device, atoi(argv[2]), atoi(argv[3]), atoi(argv[4])); _exit: return result; @@ -209,6 +262,4 @@ _exit: MSH_CMD_EXPORT(pwm_set, pwm_set 1 100 50); #endif /* FINSH_USING_MSH */ - - #endif /* RT_USING_FINSH */ diff --git a/components/drivers/mtd/SConscript b/components/drivers/mtd/SConscript index bc2bd54218..462c38194c 100644 --- a/components/drivers/mtd/SConscript +++ b/components/drivers/mtd/SConscript @@ -9,6 +9,17 @@ depend = [] CPPPATH = [cwd + '/../include'] group = [] +if GetDepend(['RT_USING_MTD']): + src += ['mtd.c'] + depend += ['RT_USING_MTD'] + + if GetDepend(['MTD_USING_NOR']): + src += ['mtdnor.c'] + depend += ['MTD_USING_NOR'] + if GetDepend(['MTD_USING_NAND']): + src += ['mtdnand.c'] + depend += ['MTD_USING_NAND'] + if GetDepend(['RT_USING_MTD_NOR']): src += ['mtd_nor.c'] depend += ['RT_USING_MTD_NOR'] diff --git a/components/drivers/mtd/mtd.c b/components/drivers/mtd/mtd.c new file mode 100644 index 0000000000..3e7b4f2b54 --- /dev/null +++ b/components/drivers/mtd/mtd.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + 2018-09-10 heyuanjie87 first version + + */ + +#include + +static rt_mtd_t* mtd_part_alloc(rt_mtd_t *master, const struct mtd_part *part) +{ + rt_mtd_t *slave; + + slave = rt_malloc(sizeof(rt_mtd_t)); + if (slave == RT_NULL) + goto out; + + slave->master = master; + + *slave = *master; + slave->size = part->size; + slave->offset = part->offset; + +out: + + return slave; +} + +rt_mtd_t* rt_mtd_get(const char *name) +{ + rt_mtd_t *mtd; + + mtd = (rt_mtd_t *)rt_device_find(name); + if (mtd == RT_NULL) + return RT_NULL; + + if (mtd->parent.type != RT_Device_Class_MTD) + return RT_NULL; + + return mtd; +} + +/* + * Register MTD driver + * + * @parts partion description + * @np number of partitions + * @return number of unregistered partitions + * +*/ +int rt_mtd_register(rt_mtd_t *master, const struct mtd_part *parts, int np) +{ + int ret; + rt_mtd_t *slave; + + master->master = master; + master->parent.type = RT_Device_Class_MTD; + + if (np > 0) + { + master->offset = parts->offset; + master->size = parts->size; + + ret = rt_device_register((rt_device_t)master, parts->name, 0); + if (ret != 0) + goto _out; + + np --; + parts ++; + } + + while (np > 0) + { + slave = mtd_part_alloc(master, parts); + if (!slave) + break; + ret = rt_device_register((rt_device_t)slave, parts->name, 0); + if (ret) + break; + parts ++; + np --; + } + +_out: + return np; +} + +int rt_mtd_block_erase(rt_mtd_t *mtd, uint32_t block) +{ + uint32_t total_blks; + loff_t addr; + + total_blks = mtd->size/mtd->block_size; + if (block >= total_blks) + return -EINVAL; + addr = mtd->offset + mtd->block_size * block; + + return mtd->ops->erase(mtd->master, addr, mtd->block_size); +} + +int rt_mtd_block_isbad(rt_mtd_t *mtd, uint32_t block) +{ + uint32_t total_blks, offset_blk; + + if (!mtd->ops->isbad) + return 0; + + total_blks = mtd->size / mtd->block_size; + if (block >= total_blks) + return -EINVAL; + offset_blk = mtd->offset / mtd->block_size; + + return mtd->ops->isbad(mtd->master, block + offset_blk); +} + +int rt_mtd_block_markbad(rt_mtd_t *mtd, uint32_t block) +{ + uint32_t total_blks, offset_blk; + + if (!mtd->ops->markbad) + return -EOPNOTSUPP; + + total_blks = mtd->size / mtd->block_size; + if (block >= total_blks) + return -EINVAL; + offset_blk = mtd->offset / mtd->block_size; + + return mtd->ops->markbad(mtd->master, block + offset_blk); +} + +int rt_mtd_erase(rt_mtd_t *mtd, loff_t addr, size_t size) +{ + if (addr > mtd->size || (addr + size) > mtd->size) + return -EINVAL; + addr += mtd->offset; + + return mtd->ops->erase(mtd->master, addr, size); +} + +/* +* Read data only +* +* @from offset to read from +* @return success size or error code +*/ +int rt_mtd_read(rt_mtd_t *mtd, loff_t from, uint8_t *buf, size_t len) +{ + int ret; + struct mtd_io_desc desc = {0}; + + if (from < 0 || from >= (loff_t)mtd->size || len > mtd->size - from) + return -EINVAL; + if (!len) + return 0; + + desc.datbuf = buf; + desc.datlen = len; + ret = mtd->ops->read(mtd->master, from + mtd->offset, &desc); + if (ret) + return ret; + + return desc.datretlen; +} + +/** +* Write data only +* +* @to offset to write from +* @return success size or error code +*/ +int rt_mtd_write(rt_mtd_t *mtd, loff_t to, const uint8_t *buf, size_t len) +{ + int ret; + struct mtd_io_desc desc = {0}; + + if (to < 0 || to >= (loff_t)mtd->size || len > mtd->size - to) + return -EINVAL; + if (!mtd->ops->write) + return -EROFS; + if (!len) + return 0; + + desc.datbuf = (uint8_t*)buf; + desc.datlen = len; + ret = mtd->ops->write(mtd->master, to + mtd->offset, &desc); + if (ret) + return ret; + + return desc.datretlen; +} + +/** +* Read data and/or out-of-band +* +* @from offset to read from +* @desc sector operation description structure +* @return error code, 0 success +*/ +int rt_mtd_read_oob(rt_mtd_t *mtd, loff_t from, struct mtd_io_desc *desc) +{ + desc->datretlen = 0; + desc->oobretlen = 0; + + if (from < 0 || from >= (loff_t)mtd->size) + return -EINVAL; + + if (desc->datbuf && (desc->datlen > (mtd->size - from))) + return -EINVAL; + + return mtd->ops->read(mtd->master, from + mtd->offset, desc); +} + +/** +* Write data and/or out-of-band +* +* @to offset to read from +* @desc sector operation description structure +* @return error code, 0 success +*/ +int rt_mtd_write_oob(rt_mtd_t *mtd, loff_t to, struct mtd_io_desc *desc) +{ + desc->datretlen = 0; + desc->oobretlen = 0; + + if (to < 0 || to >= (loff_t)mtd->size) + return -EINVAL; + + if (desc->datbuf && (desc->datlen >(mtd->size - to))) + return -EINVAL; + + return mtd->ops->write(mtd->master, to + mtd->offset, desc); +} diff --git a/components/drivers/mtd/mtd_nand.c b/components/drivers/mtd/mtd_nand.c index bf22d889ce..3e4582ceaf 100644 --- a/components/drivers/mtd/mtd_nand.c +++ b/components/drivers/mtd/mtd_nand.c @@ -1,21 +1,7 @@ /* - * File : mtd_core.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/mtd/mtd_nor.c b/components/drivers/mtd/mtd_nor.c index 8f37e95f09..b941f9236d 100644 --- a/components/drivers/mtd/mtd_nor.c +++ b/components/drivers/mtd/mtd_nor.c @@ -1,21 +1,7 @@ /* - * File : mtd_nor.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, Shanghai Real-Thread Technology Co., Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/mtd/mtdnand.c b/components/drivers/mtd/mtdnand.c new file mode 100644 index 0000000000..50012219fb --- /dev/null +++ b/components/drivers/mtd/mtdnand.c @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-10 heyuanjie87 first version + */ + +#include + +#define MTDTONAND(x) ((rt_nand_t*)(x)) +#define NOTALIGNED(x) ((x & (chip->page_size - 1)) != 0) +#ifndef min +#define min(a,b) (a>b? b:a) +#endif + +static uint8_t *nand_fill_oob(rt_nand_t *chip, uint8_t *oob, size_t len, struct mtd_io_desc *desc) +{ + rt_memset(chip->oob_poi, 0xff, chip->oobsize); + + switch (desc->mode) + { + case MTD_OPM_PLACE_OOB: + case MTD_OPM_RAW: + rt_memcpy(chip->oob_poi + desc->ooboffs, oob, len); + return oob + len; + + case MTD_OPM_AUTO_OOB: + { + const struct mtd_oob_region *free = chip->freelayout; + uint32_t boffs; + size_t bytes; + + bytes = min(len, free->length); + boffs = free->offset; + + rt_memcpy(chip->oob_poi + boffs, oob, bytes); + oob += bytes; + + return oob; + } + } + + return NULL; +} + +static uint8_t *nand_transfer_oob(rt_nand_t *chip, uint8_t *oob, struct mtd_io_desc *desc, size_t len) +{ + switch (desc->mode) + { + case MTD_OPM_PLACE_OOB: + case MTD_OPM_RAW: + rt_memcpy(oob, chip->oob_poi + desc->ooboffs, len); + return oob + len; + + case MTD_OPM_AUTO_OOB: + { + struct mtd_oob_region *free = (struct mtd_oob_region *)chip->freelayout; + uint32_t boffs = 0, roffs = desc->ooboffs; + size_t bytes = 0; + + for (; free->length && len; free++, len -= bytes) + { + /* Read request not from offset 0? */ + if (roffs) + { + if (roffs >= free->length) + { + roffs -= free->length; + continue; + } + boffs = free->offset + roffs; + bytes = min(len, (free->length - roffs)); + roffs = 0; + } + else + { + bytes = min(len, free->length); + boffs = free->offset; + } + + rt_memcpy(oob, chip->oob_poi + boffs, bytes); + oob += bytes; + } + + return oob; + } + } + + return NULL; +} + +static int nand_read_page_raw(rt_nand_t *chip, uint8_t *buf, int oob_required, int page) +{ + chip->ops->read_buf(chip, buf, chip->page_size); + + if (oob_required) + chip->ops->read_buf(chip, chip->oob_poi, chip->oobsize); + + return 0; +} + +static int nand_write_page_raw(rt_nand_t *chip, const uint8_t *buf, int oob_required, int page) +{ + chip->ops->write_buf(chip, buf, chip->page_size); + + if (oob_required) + chip->ops->write_buf(chip, chip->oob_poi, chip->oobsize); + + return 0; +} + +static int nand_write_page_hwecc(rt_nand_t *chip, const uint8_t *buf, int oob_required, int page) +{ + uint16_t i; + uint16_t stepsize = chip->ecc.stepsize; + uint16_t eccbytes = chip->ecc.bytes; + uint16_t eccsteps = chip->ecc._step; + uint16_t eccpos = chip->ecc.layout->offset; + uint8_t *ecc_calc = chip->buffers.ecccalc; + const uint8_t *p = buf; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += stepsize) + { + chip->ops->cmdfunc(chip, NAND_CMD_ECC_EN, 0, 0); + chip->ops->write_buf(chip, p, stepsize); + chip->ecc.calculate(chip, p, &ecc_calc[i]); + chip->ops->cmdfunc(chip, NAND_CMD_ECC_DIS, 0, 0); + } + + rt_memcpy(&chip->oob_poi[eccpos], ecc_calc, chip->ecc.layout->length); + + chip->ops->write_buf(chip, chip->oob_poi, chip->oobsize); + + return 0; +} + +static int nand_read_page_hwecc(rt_nand_t *chip, uint8_t *buf, int oob_required, int page) +{ + uint16_t i; + uint16_t eccsize = chip->ecc.stepsize; + uint16_t eccbytes = chip->ecc.bytes; + uint16_t eccsteps = chip->ecc._step; + uint16_t eccpos = chip->ecc.layout->offset; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers.ecccalc; + uint8_t *ecc_code = chip->buffers.ecccode; + int ret = 0; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + { + chip->ops->cmdfunc(chip, NAND_CMD_ECC_EN, 0, 0); + chip->ops->read_buf(chip, p, eccsize); + chip->ecc.calculate(chip, p, &ecc_calc[i]); + chip->ops->cmdfunc(chip, NAND_CMD_ECC_DIS, 0, 0); + } + + chip->ops->read_buf(chip, chip->oob_poi, chip->oobsize); + rt_memcpy(ecc_code, &chip->oob_poi[eccpos], chip->ecc.layout->length); + + eccsteps = chip->ecc._step; + p = buf; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + { + int stat; + + stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); + if (stat != 0) + ret = -1; + } + + return ret; +} + +static int nand_write_page(rt_nand_t *chip, const uint8_t *buf, + int oob_required, int page, int raw) +{ + int status; + + chip->ops->cmdfunc(chip, NAND_CMD_PAGE_WR0, page, 0x00); + + if (raw) + { + nand_write_page_raw(chip, buf, oob_required, page); + } + else + { + chip->write_page(chip, buf, oob_required, page); + } + + status = chip->ops->cmdfunc(chip, NAND_CMD_PAGE_WR1, -1, -1); + + return status; +} + +static int nand_do_read_desc(rt_nand_t *chip, loff_t from, struct mtd_io_desc *desc) +{ + int page, bytes; + char oob_required; + char ecc_fail = 0; + int ret = 0; + uint32_t readlen = desc->datlen; + uint16_t oobreadlen = desc->ooblen; + uint16_t max_oobsize = desc->mode == MTD_OPM_AUTO_OOB ? + chip->freelayout->length : chip->oobsize; + + uint8_t *oob, *buf, *notalign = 0; + + /* Reject reads, which are not page aligned */ + if (NOTALIGNED(from)) + { + return -EINVAL; + } + + buf = desc->datbuf; + if (NOTALIGNED(desc->datlen) && !chip->pagebuf) + { + chip->pagebuf = rt_malloc(chip->page_size); + if (!chip->pagebuf) + return -ENOMEM; + } + + page = (int)(from / chip->page_size); + + oob = desc->oobbuf; + oob_required = oob ? 1 : 0; + + while (1) + { + bytes = min(chip->page_size, readlen); + + chip->ops->cmdfunc(chip, NAND_CMD_PAGE_RD, page, 0x00); + if (NOTALIGNED(bytes)) + { + notalign = buf; + buf = chip->pagebuf; + } + /* + * Now read the page into the buffer. Absent an error, + * the read methods return max bitflips per ecc step. + */ + if (desc->mode == MTD_OPM_RAW) + { + ret = nand_read_page_raw(chip, buf, oob_required, page); + } + else + { + ret = chip->read_page(chip, buf, oob_required, page); + } + + if (ret != 0) + { + ret = -EBADMSG; + break; + } + + if (oob) + { + int toread = min(oobreadlen, max_oobsize); + + if (toread) + { + oob = nand_transfer_oob(chip, oob, desc, toread); + oobreadlen -= toread; + } + } + + if (notalign) + { + rt_memcpy(notalign, buf, bytes); + } + + buf += bytes; + readlen -= bytes; + + if (!readlen) + break; + + page++; + } + + desc->datretlen = desc->datlen - (size_t)readlen; + if (oob) + desc->oobretlen = desc->ooblen - oobreadlen; + + return ret; +} + +/* + * write with ECC + * +*/ +static int nand_do_write_desc(rt_nand_t *chip, loff_t to, struct mtd_io_desc *desc) +{ + int page; + uint16_t writelen = desc->datlen; + uint16_t oob_required = desc->oobbuf ? 1 : 0; + uint16_t oobwritelen = desc->ooblen; + uint16_t oobmaxlen = desc->mode == MTD_OPM_AUTO_OOB ? + chip->freelayout->length : chip->oobsize; + + uint8_t *oob = desc->oobbuf; + uint8_t *buf = desc->datbuf; + int ret; + + if (!writelen) + return 0; + + /* Reject writes, which are not page aligned */ + if (NOTALIGNED(to)) + { + return -EINVAL; + } + + page = (int)(to / chip->page_size); + + /* Don't allow multipage oob writes with offset */ + if (oob && desc->ooboffs && (desc->ooboffs + desc->ooblen > oobmaxlen)) + { + ret = -EINVAL; + goto err_out; + } + + if (NOTALIGNED(desc->datlen) && !chip->pagebuf) + { + chip->pagebuf = rt_malloc(chip->page_size); + if (!chip->pagebuf) + return -ENOMEM; + } + + while (1) + { + uint16_t bytes = min(chip->page_size, writelen); + + if (oob) + { + size_t len = min(oobwritelen, oobmaxlen); + oob = nand_fill_oob(chip, oob, len, desc); + oobwritelen -= len; + } + else + { + /* We still need to erase leftover OOB data */ + rt_memset(chip->oob_poi, 0xff, chip->oobsize); + } + + if (NOTALIGNED(bytes)) + { + uint8_t *dbtmp = buf; + buf = chip->pagebuf; + rt_memset(&buf[bytes], 0xff, chip->page_size - bytes); + rt_memcpy(buf, dbtmp, bytes); + } + ret = nand_write_page(chip, buf, oob_required, page, (desc->mode == MTD_OPM_RAW)); + if (ret) + break; + + writelen -= bytes; + if (!writelen) + break; + + buf += bytes; + page++; + } + + desc->datretlen = desc->datlen - writelen; + if (oob) + desc->oobretlen = desc->ooblen; + +err_out: + + return ret; +} + +static int nand_read_oob_std(rt_nand_t *chip, int page) +{ + chip->ops->cmdfunc(chip, NAND_CMD_PAGE_RD, page, chip->page_size); + chip->ops->read_buf(chip, chip->oob_poi, chip->oobsize); + + return 0; +} + +/* + * read one page of OOB +*/ +static int nand_only_read_oob(rt_nand_t *chip, loff_t from, struct mtd_io_desc *desc) +{ + int page; + int readlen = desc->ooblen; + int len; + uint8_t *buf = desc->oobbuf; + int ret = 0; + + if (desc->mode == MTD_OPM_AUTO_OOB) + len = chip->freelayout->length; + else + len = chip->oobsize; + + if (desc->ooboffs >= len) //attempt to start read outside oob + { + return -EINVAL; + } + + page = (int)(from / chip->page_size); + + ret = nand_read_oob_std(chip, page); + if (ret == 0) + { + len = min(len, readlen); + buf = nand_transfer_oob(chip, buf, desc, len); + desc->oobretlen = len; + } + + return ret; +} + +static int nand_write_oob_std(rt_nand_t *chip, int page) +{ + int status; + + chip->ops->cmdfunc(chip, NAND_CMD_PAGE_WR0, page, chip->page_size); + chip->ops->write_buf(chip, chip->oob_poi, chip->oobsize); + /* Send command to program the OOB data */ + status = chip->ops->cmdfunc(chip, NAND_CMD_PAGE_WR1, -1, -1); + + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +static int nand_only_write_oob(rt_nand_t *chip, loff_t to, struct mtd_io_desc *desc) +{ + int page, ret, len; + + if (desc->mode == MTD_OPM_AUTO_OOB) + len = chip->freelayout->length; + else + len = chip->oobsize; + + /* Do not allow write past end of page */ + if ((desc->ooboffs + desc->ooblen) > len) + { + return -EINVAL; + } + + if (desc->ooblen == 0) + { + return -EINVAL; + } + + /* get page */ + page = (int)(to / chip->page_size); + + nand_fill_oob(chip, desc->oobbuf, desc->ooblen, desc); + + ret = nand_write_oob_std(chip, page); + if (ret == 0) + desc->oobretlen = len; + + return ret; +} + +static int nand_erase(rt_mtd_t *mtd, loff_t addr, size_t size) +{ + rt_nand_t *chip; + int status; + int page; + uint32_t blksize; + + chip = MTDTONAND(mtd); + blksize = mtd->block_size; + page = addr / chip->page_size; + + while (size >= blksize) + { + status = chip->ops->cmdfunc(chip, NAND_CMD_BLK_ERASE, page, 0); + if (status & NAND_STATUS_FAIL) + { + break; + } + size -= blksize; + page += chip->pages_pb; + } + + return size; +} + +static int nand_read(rt_mtd_t *mtd, loff_t from, struct mtd_io_desc *desc) +{ + int ret = -ENOTSUP; + rt_nand_t *chip; + + chip = MTDTONAND(mtd); + + switch (desc->mode) + { + case MTD_OPM_PLACE_OOB: + case MTD_OPM_AUTO_OOB: + case MTD_OPM_RAW: + break; + + default: + goto out; + } + + if (!desc->datbuf || !desc->datlen) + ret = nand_only_read_oob(chip, from, desc); + else + ret = nand_do_read_desc(chip, from, desc); + +out: + + return ret; +} + +static int nand_write(rt_mtd_t *mtd, loff_t to, struct mtd_io_desc *desc) +{ + int ret = -ENOTSUP; + rt_nand_t *chip; + + chip = MTDTONAND(mtd); + + switch (desc->mode) + { + case MTD_OPM_PLACE_OOB: + case MTD_OPM_AUTO_OOB: + case MTD_OPM_RAW: + break; + + default: + goto out; + } + + if (!desc->datbuf || !desc->datlen) + ret = nand_only_write_oob(chip, to, desc); + else + ret = nand_do_write_desc(chip, to, desc); + +out: + + return ret; +} + +static int nand_block_isbad(rt_mtd_t *mtd, uint32_t blk) +{ + int ret; + rt_nand_t *chip = MTDTONAND(mtd); + + if (chip->ops->isbad) + { + ret = chip->ops->isbad(chip, blk); + } + else + { + int page; + + page = blk * chip->pages_pb; + nand_read_oob_std(chip, page); + ret = chip->oob_poi[0] != 0xFF; + } + + return ret; +} + +static int nand_block_markbad(rt_mtd_t *mtd, uint32_t blk) +{ + int ret; + rt_nand_t *chip; + + chip = MTDTONAND(mtd); + + if (chip->ops->markbad) + { + ret = chip->ops->markbad(chip, blk); + } + else + { + int page; + + page = blk * chip->pages_pb; + rt_memset(chip->oob_poi, 0xff, chip->oobsize); + chip->oob_poi[0] = 0; + ret = nand_write_oob_std(chip, page); + } + + return ret; +} + +static const struct mtd_ops _ops = +{ + nand_erase, + nand_read, + nand_write, + nand_block_isbad, + nand_block_markbad, +}; + +int rt_mtd_nand_init(rt_nand_t *nand, int blk_size, int page_size, int oob_size) +{ + uint8_t *buf; + + buf = rt_malloc(oob_size * 3); + if (buf == RT_NULL) + return -ENOMEM; + + nand->oob_poi = buf; + buf += oob_size; + nand->buffers.ecccalc = buf; + buf += oob_size; + nand->buffers.ecccode = buf; + nand->pagebuf = 0; /* alloc when unaligen access */ + + nand->pages_pb = blk_size / page_size; + nand->ecc._step = page_size / nand->ecc.stepsize; + nand->page_size = page_size; + nand->oobsize = oob_size; + + nand->parent.type = MTD_TYPE_NAND; + nand->parent.ops = &_ops; + nand->parent.sector_size = page_size; + nand->parent.block_size = blk_size; + nand->parent.oob_size = oob_size; + + switch (nand->ecc.mode) + { + case NAND_ECCM_NONE: + { + nand->read_page = nand_read_page_raw; + nand->write_page = nand_write_page_raw; + }break; + case NAND_ECCM_HW: + { + nand->read_page = nand_read_page_hwecc; + nand->write_page = nand_write_page_hwecc; + }break; + default: + { + rt_free(buf); + return -1; + } + } + + return 0; +} diff --git a/components/drivers/mtd/mtdnor.c b/components/drivers/mtd/mtdnor.c new file mode 100644 index 0000000000..481d26167e --- /dev/null +++ b/components/drivers/mtd/mtdnor.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + 2018-09-10 heyuanjie87 first version + + */ + +#include + +#ifdef MTD_USING_NOR +static int _nor_erase(rt_mtd_t *mtd, loff_t addr, size_t len) +{ + rt_nor_t *nor; + + nor = (rt_nor_t *)mtd; + return nor->ops->erase(nor, addr, len); +} + +static int _nor_read(rt_mtd_t *mtd, loff_t from, struct mtd_io_desc *desc) +{ + rt_nor_t *nor; + int ret; + + nor = (rt_nor_t *)mtd; + ret = nor->ops->read(nor, from, desc->datbuf, desc->datlen); + if (ret > 0) + { + desc->datretlen = ret; + ret = 0; + } + + return ret; +} + +static int _nor_write(rt_mtd_t *mtd, loff_t to, struct mtd_io_desc *desc) +{ + rt_nor_t *nor; + int ret; + + nor = (rt_nor_t *)mtd; + ret = nor->ops->write(nor, to, desc->datbuf, desc->datlen); + if (ret > 0) + { + desc->datretlen = ret; + ret = 0; + } + + return ret; +} + +static const struct mtd_ops _ops = +{ + _nor_erase, + _nor_read, + _nor_write, + 0, + 0 +}; + +int rt_mtd_nor_init(rt_nor_t *nor, int blksize) +{ + nor->parent.sector_size = 1; + nor->parent.block_size = blksize; + nor->parent.ops = &_ops; + nor->parent.type = MTD_TYPE_NOR; + nor->parent.oob_size = 0; + + return 0; +} +#endif diff --git a/components/drivers/pm/SConscript b/components/drivers/pm/SConscript new file mode 100644 index 0000000000..a94fc11f57 --- /dev/null +++ b/components/drivers/pm/SConscript @@ -0,0 +1,14 @@ +from building import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd + '/../include'] +group = [] + +if GetDepend(['RT_USING_PM']): + src = src + ['pm.c'] + +if len(src): + group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/pm/pm.c b/components/drivers/pm/pm.c new file mode 100644 index 0000000000..655c4b4c02 --- /dev/null +++ b/components/drivers/pm/pm.c @@ -0,0 +1,551 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-06-02 Bernard the first version + * 2018-08-02 Tanek split run and sleep modes, support custom mode + */ + +#include +#include +#include + +#ifdef RT_USING_PM + +static struct rt_pm _pm; + +/** + * This function will suspend all registered devices + */ +static void _pm_device_suspend(void) +{ + int index; + + for (index = 0; index < _pm.device_pm_number; index++) + { + if (_pm.device_pm[index].ops->suspend != RT_NULL) + { + _pm.device_pm[index].ops->suspend(_pm.device_pm[index].device); + } + } +} + +/** + * This function will resume all registered devices + */ +static void _pm_device_resume(void) +{ + int index; + + for (index = 0; index < _pm.device_pm_number; index++) + { + if (_pm.device_pm[index].ops->resume != RT_NULL) + { + _pm.device_pm[index].ops->resume(_pm.device_pm[index].device); + } + } +} + +#if PM_RUN_MODE_COUNT > 1 +/** + * This function will update the frequency of all registered devices + */ +static void _pm_device_frequency_change(void) +{ + rt_uint32_t index; + + /* make the frequency change */ + for (index = 0; index < _pm.device_pm_number; index ++) + { + if (_pm.device_pm[index].ops->frequency_change != RT_NULL) + _pm.device_pm[index].ops->frequency_change(_pm.device_pm[index].device); + } +} +#endif + +/** + * This function will enter corresponding power mode. + */ +void rt_pm_enter(void) +{ + rt_ubase_t level; + struct rt_pm *pm; + rt_uint32_t index; + rt_tick_t timeout_tick; + + pm = &_pm; + + /* disable interrupt before check run modes */ + level = rt_hw_interrupt_disable(); + /* check each run mode, and decide to swithc to run mode or sleep mode */ + for (index = 0; index < PM_RUN_MODE_COUNT; index++) + { + if (pm->modes[index]) + { + if (index > pm->current_mode) + { + pm->ops->exit(pm); + pm->current_mode = index; + pm->ops->enter(pm); +#if PM_RUN_MODE_COUNT > 1 + pm->ops->frequency_change(pm, 0); + _pm_device_frequency_change(); +#endif + } + + rt_hw_interrupt_enable(level); + /* The current mode is run mode, no need to check sleep mode */ + return ; + } + } + /* enable interrupt after check run modes */ + rt_hw_interrupt_enable(level); + + level = rt_hw_interrupt_disable(); + /* check each sleep mode to decide which mode can system sleep. */ + for (index = PM_SLEEP_MODE_START; index < PM_SLEEP_MODE_START + PM_SLEEP_MODE_COUNT; index++) + { + if (pm->modes[index]) + { + /* let mcu sleep when system is idle */ + + /* run mode to sleep mode */ + if (pm->current_mode < PM_SLEEP_MODE_START) + { + /* exit run mode */ + pm->ops->exit(pm); + } + + /* set current power mode */ + pm->current_mode = index; + pm->exit_count = 1; + + /* suspend all of devices with PM feature */ + _pm_device_suspend(); + + /* should start pm timer */ + if (pm->timer_mask & (1 << index)) + { + /* get next os tick */ + timeout_tick = rt_timer_next_timeout_tick(); + if (timeout_tick != RT_TICK_MAX) + { + timeout_tick -= rt_tick_get(); + +#if defined(PM_MIN_ENTER_SLEEP_TICK) && PM_MIN_ENTER_SLEEP_TICK > 0 + if (timeout_tick < PM_MIN_ENTER_SLEEP_TICK) + { + rt_hw_interrupt_enable(level); + /* limit the minimum time to enter timer sleep mode */ + return ; + } +#endif + } + /* startup pm timer */ + pm->ops->timer_start(pm, timeout_tick); + } + + /* enter sleep and wait to be waken up */ + pm->ops->enter(pm); + + rt_hw_interrupt_enable(level); + + /* exit from low power mode */ + rt_pm_exit(); + + return ; + } + } + + rt_hw_interrupt_enable(level); +} + +/** + * This function exits from sleep mode. + */ +void rt_pm_exit(void) +{ + rt_ubase_t level; + struct rt_pm *pm; + rt_tick_t delta_tick; + + pm = &_pm; + + level = rt_hw_interrupt_disable(); + + if (pm->exit_count) + { + pm->exit_count = 0; + + if (pm->current_mode >= PM_SLEEP_MODE_START) + { + /* sleep mode with timer */ + if (pm->timer_mask & (1 << pm->current_mode)) + { + /* get the tick of pm timer */ + delta_tick = pm->ops->timer_get_tick(pm); + + /* stop pm timer */ + pm->ops->timer_stop(pm); + + if (delta_tick) + { + /* adjust OS tick */ + rt_tick_set(rt_tick_get() + delta_tick); + /* check system timer */ + rt_timer_check(); + } + } + + /* exit from sleep mode */ + pm->ops->exit(pm); + /* resume the device with PM feature */ + _pm_device_resume(); + } + } + + rt_hw_interrupt_enable(level); +} + +/** + * Upper application or device driver requests the system + * stall in corresponding power mode. + * + * @param parameter the parameter of run mode or sleep mode + */ +void rt_pm_request(rt_ubase_t mode) +{ + rt_ubase_t level; + struct rt_pm *pm; + + pm = &_pm; + + if (mode > PM_MODE_MAX) + return; + + level = rt_hw_interrupt_disable(); + + /* update pm modes table */ + pm->modes[mode] ++; + + /* request higter mode with a smaller mode value*/ + if (mode < pm->current_mode) + { + /* the old current mode is RUN mode, need to all pm->ops->exit(), + * if not, it has already called in rt_pm_exit() + */ + if (pm->current_mode < PM_SLEEP_MODE_START) + { + pm->ops->exit(pm); + } + else if (pm->exit_count) + { + /* call exeit when global interrupt is disable */ + pm->ops->exit(pm); + pm->exit_count = 0; + } + + /* update current mode */ + pm->current_mode = mode; + + /* current mode is higher run mode */ + if (mode < PM_SLEEP_MODE_START) + { + /* enter run mode */ + pm->ops->enter(pm); +#if PM_RUN_MODE_COUNT > 1 + /* frequency change */ + pm->ops->frequency_change(pm, 0); + _pm_device_frequency_change(); +#endif + } + else + { + /* do nothing when request higher sleep mode, + * and swithc to new sleep mode in rt_pm_enter() + */ + } + } + + rt_hw_interrupt_enable(level); +} + +/** + * Upper application or device driver releases the stall + * of corresponding power mode. + * + * @param parameter the parameter of run mode or sleep mode + * + */ +void rt_pm_release(rt_ubase_t mode) +{ + rt_ubase_t level; + struct rt_pm *pm; + + pm = &_pm; + + if (mode > PM_MODE_MAX) + return; + + level = rt_hw_interrupt_disable(); + + if (pm->modes[mode] > 0) + pm->modes[mode] --; + + rt_hw_interrupt_enable(level); +} + +/** + * Register a device with PM feature + * + * @param device the device with PM feature + * @param ops the PM ops for device + */ +void rt_pm_register_device(struct rt_device *device, const struct rt_device_pm_ops *ops) +{ + rt_ubase_t level; + struct rt_device_pm *device_pm; + + RT_DEBUG_NOT_IN_INTERRUPT; + + level = rt_hw_interrupt_disable(); + + device_pm = (struct rt_device_pm *)RT_KERNEL_REALLOC(_pm.device_pm, + (_pm.device_pm_number + 1) * sizeof(struct rt_device_pm)); + if (device_pm != RT_NULL) + { + _pm.device_pm = device_pm; + _pm.device_pm[_pm.device_pm_number].device = device; + _pm.device_pm[_pm.device_pm_number].ops = ops; + _pm.device_pm_number += 1; + } + + rt_sem_release(&(_pm.device_lock)); + + rt_hw_interrupt_enable(level); +} + +/** + * Unregister device from PM manager. + * + * @param device the device with PM feature + */ +void rt_pm_unregister_device(struct rt_device *device) +{ + rt_ubase_t level; + rt_uint32_t index; + RT_DEBUG_NOT_IN_INTERRUPT; + + level = rt_hw_interrupt_disable(); + + for (index = 0; index < _pm.device_pm_number; index ++) + { + if (_pm.device_pm[index].device == device) + { + /* remove current entry */ + for (; index < _pm.device_pm_number - 1; index ++) + { + _pm.device_pm[index] = _pm.device_pm[index + 1]; + } + + _pm.device_pm[_pm.device_pm_number - 1].device = RT_NULL; + _pm.device_pm[_pm.device_pm_number - 1].ops = RT_NULL; + + _pm.device_pm_number -= 1; + /* break out and not touch memory */ + break; + } + } + + rt_hw_interrupt_enable(level); +} + +/** + * RT-Thread device interface for PM device + */ +static rt_size_t _rt_pm_device_read(rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + struct rt_pm *pm; + rt_size_t length; + + length = 0; + pm = (struct rt_pm *)dev; + RT_ASSERT(pm != RT_NULL); + + if (pos <= PM_MODE_MAX) + { + int mode; + + mode = pm->modes[pos]; + length = rt_snprintf(buffer, size, "%d", mode); + } + + return length; +} + +static rt_size_t _rt_pm_device_write(rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + unsigned char request; + + if (size) + { + /* get request */ + request = *(unsigned char *)buffer; + if (request == '1') + { + rt_pm_request(pos); + } + else if (request == '0') + { + rt_pm_release(pos); + } + } + + return 1; +} + +static rt_err_t _rt_pm_device_control(rt_device_t dev, + int cmd, + void *args) +{ + rt_uint32_t mode; + + switch (cmd) + { + case RT_PM_DEVICE_CTRL_REQUEST: + mode = (rt_uint32_t)args; + rt_pm_request(mode); + break; + + case RT_PM_DEVICE_CTRL_RELEASE: + mode = (rt_uint32_t)args; + rt_pm_release(mode); + break; + } + + return RT_EOK; +} + +/** + * This function will initialize power management. + * + * @param ops the PM operations. + * @param timer_mask indicates which mode has timer feature. + * @param user_data user data + */ +void rt_system_pm_init(const struct rt_pm_ops *ops, + rt_uint8_t timer_mask, + void *user_data) +{ + struct rt_device *device; + struct rt_pm *pm; + + pm = &_pm; + device = &(_pm.parent); + + device->type = RT_Device_Class_PM; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = _rt_pm_device_read; + device->write = _rt_pm_device_write; + device->control = _rt_pm_device_control; + device->user_data = user_data; + + /* register PM device to the system */ + rt_device_register(device, "pm", RT_DEVICE_FLAG_RDWR); + + /* todo : add to kernel source code */ + rt_thread_idle_sethook(rt_pm_enter); + + rt_memset(pm->modes, 0, sizeof(pm->modes)); + pm->current_mode = PM_RUN_MODE_DEFAULT; + + pm->timer_mask = timer_mask; + + pm->ops = ops; + + pm->device_pm = RT_NULL; + pm->device_pm_number = 0; + + /* initialize semaphore */ + rt_sem_init(&(pm->device_lock), "pm", 1, RT_IPC_FLAG_FIFO); + + /* request in default running mode */ + rt_pm_request(PM_RUN_MODE_DEFAULT); + +#ifdef PM_SLEEP_MODE_DEFAULT + /* request in default sleep mode */ + rt_pm_request(PM_SLEEP_MODE_DEFAULT); +#endif + + /* must hold on deep shutdown mode */ + rt_pm_request(PM_MODE_MAX); +} + +#ifdef RT_USING_FINSH +#include + +static void rt_pm_release_mode(int argc, char **argv) +{ + int mode = 0; + if (argc >= 2) + { + mode = atoi(argv[1]); + } + + rt_pm_release(mode); +} +MSH_CMD_EXPORT_ALIAS(rt_pm_release_mode, pm_release, release power management mode); + +static void rt_pm_request_mode(int argc, char **argv) +{ + int mode = 0; + if (argc >= 2) + { + mode = atoi(argv[1]); + } + + rt_pm_request(mode); +} +MSH_CMD_EXPORT_ALIAS(rt_pm_request_mode, pm_request, request power management mode); + +static void rt_pm_dump_status(void) +{ + static const char *pm_str[] = PM_MODE_NAMES; + rt_uint32_t index; + struct rt_pm *pm; + + pm = &_pm; + + rt_kprintf("| Power Management Mode | Counter | Timer |\n"); + rt_kprintf("+-----------------------+---------+-------+\n"); + for (index = 0; index <= PM_MODE_MAX; index ++) + { + int has_timer = 0; + if (pm->timer_mask & (1 << index)) + has_timer = 1; + + rt_kprintf("| %021s | %7d | %5d |\n", pm_str[index], pm->modes[index], has_timer); + } + rt_kprintf("+-----------------------+---------+-------+\n"); + + rt_kprintf("pm current mode: %s\n", pm_str[pm->current_mode]); +} +FINSH_FUNCTION_EXPORT_ALIAS(rt_pm_dump_status, pm_dump, dump power management status); +MSH_CMD_EXPORT_ALIAS(rt_pm_dump_status, pm_dump, dump power management status); +#endif + +#endif /* RT_USING_PM */ diff --git a/components/drivers/rtc/alarm.c b/components/drivers/rtc/alarm.c index 6660128603..c497ebf727 100644 --- a/components/drivers/rtc/alarm.c +++ b/components/drivers/rtc/alarm.c @@ -1,21 +1,7 @@ /* - * File : alarm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/rtc/rtc.c b/components/drivers/rtc/rtc.c index 000358c111..e17c0fe7dd 100644 --- a/components/drivers/rtc/rtc.c +++ b/components/drivers/rtc/rtc.c @@ -1,21 +1,7 @@ /* - * File : rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/rtc/soft_rtc.c b/components/drivers/rtc/soft_rtc.c index c828e43ebc..adcbf81fe3 100644 --- a/components/drivers/rtc/soft_rtc.c +++ b/components/drivers/rtc/soft_rtc.c @@ -1,21 +1,7 @@ /* - * File : soft_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/sdio/block_dev.c b/components/drivers/sdio/block_dev.c index 14a01acd90..23be319fc6 100644 --- a/components/drivers/sdio/block_dev.c +++ b/components/drivers/sdio/block_dev.c @@ -1,21 +1,7 @@ /* - * File : block_dev.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -27,8 +13,20 @@ #include +#define DBG_ENABLE +#define DBG_SECTION_NAME "SDIO" +#ifdef RT_SDIO_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#define DBG_COLOR +#include + static rt_list_t blk_devices = RT_LIST_OBJECT_INIT(blk_devices); +#define BLK_MIN(a, b) ((a) < (b) ? (a) : (b)) + struct mmcsd_blk_device { struct rt_mmcsd_card *card; @@ -36,6 +34,7 @@ struct mmcsd_blk_device struct rt_device dev; struct dfs_partition part; struct rt_device_blk_geometry geometry; + rt_size_t max_req_size; }; #ifndef RT_MMCSD_MAX_PARTITION @@ -179,7 +178,7 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, err = mmcsd_send_cmd(card->host, &cmd, 5); if (err) { - rt_kprintf("error %d requesting status\n", err); + LOG_E("error %d requesting status", err); break; } /* @@ -195,8 +194,8 @@ static rt_err_t rt_mmcsd_req_blk(struct rt_mmcsd_card *card, if (cmd.err || data.err || stop.err) { - rt_kprintf("mmcsd request blocks error\n"); - rt_kprintf("%d,%d,%d, 0x%08x,0x%08x\n", + LOG_E("mmcsd request blocks error"); + LOG_E("%d,%d,%d, 0x%08x,0x%08x", cmd.err, data.err, stop.err, data.flags, sector); return -RT_ERROR; @@ -239,19 +238,31 @@ static rt_size_t rt_mmcsd_read(rt_device_t dev, void *buffer, rt_size_t size) { - rt_err_t err; + rt_err_t err = 0; + rt_size_t offset = 0; + rt_size_t req_size = 0; + rt_size_t remain_size = size; + void *rd_ptr = (void *)buffer; struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; struct dfs_partition *part = &blk_dev->part; if (dev == RT_NULL) { rt_set_errno(-EINVAL); - return 0; } rt_sem_take(part->lock, RT_WAITING_FOREVER); - err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos, buffer, size, 0); + while (remain_size) + { + req_size = (remain_size > blk_dev->max_req_size) ? blk_dev->max_req_size : remain_size; + err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos + offset, rd_ptr, req_size, 0); + if (err) + break; + offset += req_size; + rd_ptr = (void *)((rt_uint8_t *)rd_ptr + (req_size << 9)); + remain_size -= req_size; + } rt_sem_release(part->lock); /* the length of reading must align to SECTOR SIZE */ @@ -260,7 +271,7 @@ static rt_size_t rt_mmcsd_read(rt_device_t dev, rt_set_errno(-EIO); return 0; } - return size; + return size - remain_size; } static rt_size_t rt_mmcsd_write(rt_device_t dev, @@ -268,19 +279,31 @@ static rt_size_t rt_mmcsd_write(rt_device_t dev, const void *buffer, rt_size_t size) { - rt_err_t err; + rt_err_t err = 0; + rt_size_t offset = 0; + rt_size_t req_size = 0; + rt_size_t remain_size = size; + void *wr_ptr = (void *)buffer; struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data; struct dfs_partition *part = &blk_dev->part; if (dev == RT_NULL) { rt_set_errno(-EINVAL); - return 0; } rt_sem_take(part->lock, RT_WAITING_FOREVER); - err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos, (void *)buffer, size, 1); + while (remain_size) + { + req_size = (remain_size > blk_dev->max_req_size) ? blk_dev->max_req_size : remain_size; + err = rt_mmcsd_req_blk(blk_dev->card, part->offset + pos + offset, wr_ptr, req_size, 1); + if (err) + break; + offset += req_size; + wr_ptr = (void *)((rt_uint8_t *)wr_ptr + (req_size << 9)); + remain_size -= req_size; + } rt_sem_release(part->lock); /* the length of reading must align to SECTOR SIZE */ @@ -290,7 +313,7 @@ static rt_size_t rt_mmcsd_write(rt_device_t dev, return 0; } - return size; + return size - remain_size; } static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) @@ -311,7 +334,7 @@ static rt_int32_t mmcsd_set_blksize(struct rt_mmcsd_card *card) if (err) { - rt_kprintf("MMCSD: unable to set block size to %d: %d\n", cmd.arg, err); + LOG_E("MMCSD: unable to set block size to %d: %d", cmd.arg, err); return -RT_ERROR; } @@ -346,13 +369,13 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) return err; } - rt_kprintf("probe mmcsd block device!\n"); + LOG_I("probe mmcsd block device!"); /* get the first sector to read partition table */ sector = (rt_uint8_t *)rt_malloc(SECTOR_SIZE); if (sector == RT_NULL) { - rt_kprintf("allocate partition sector buffer failed\n"); + LOG_E("allocate partition sector buffer failed!"); return -RT_ENOMEM; } @@ -365,10 +388,15 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) blk_dev = rt_calloc(1, sizeof(struct mmcsd_blk_device)); if (!blk_dev) { - rt_kprintf("mmcsd:malloc memory failed!\n"); + LOG_E("mmcsd:malloc memory failed!"); break; } + blk_dev->max_req_size = BLK_MIN((card->host->max_dma_segs * + card->host->max_seg_size) >> 9, + (card->host->max_blk_count * + card->host->max_blk_size) >> 9); + /* get the first partition */ status = dfs_filesystem_get_partition(&blk_dev->part, sector, i); if (status == RT_EOK) @@ -448,7 +476,7 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) #ifdef RT_USING_DFS_MNTTABLE if (0) // if (blk_dev) { - rt_kprintf("try to mount file system!\n"); + LOG_I("try to mount file system!"); /* try to mount file system on this block device */ dfs_mount_device(&(blk_dev->dev)); } @@ -457,7 +485,7 @@ rt_int32_t rt_mmcsd_blk_probe(struct rt_mmcsd_card *card) } else { - rt_kprintf("read mmcsd first sector failed\n"); + LOG_E("read mmcsd first sector failed"); err = -RT_ERROR; } diff --git a/components/drivers/sdio/mmc.c b/components/drivers/sdio/mmc.c index 138d9565a1..bbf0ff838c 100644 --- a/components/drivers/sdio/mmc.c +++ b/components/drivers/sdio/mmc.c @@ -1,21 +1,7 @@ /* - * File : mmc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,6 +11,16 @@ #include #include +#define DBG_ENABLE +#define DBG_SECTION_NAME "SDIO" +#ifdef RT_SDIO_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#define DBG_COLOR +#include + static const rt_uint32_t tran_unit[] = { 10000, 100000, 1000000, 10000000, @@ -81,7 +77,7 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) */ csd->csd_structure = GET_BITS(resp, 126, 2); if (csd->csd_structure == 0) { - rt_kprintf("unrecognised CSD structure version %d\n", csd->csd_structure); + LOG_E("unrecognised CSD structure version %d!", csd->csd_structure); return -RT_ERROR; } @@ -137,7 +133,7 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) */ ext_csd = rt_malloc(512); if (!ext_csd) { - rt_kprintf("alloc memory failed when get ext csd\n"); + LOG_E("alloc memory failed when get ext csd!"); return -RT_ENOMEM; } @@ -188,13 +184,19 @@ static int mmc_get_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t **new_ext_csd) */ static int mmc_parse_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) { + if(card == RT_NULL || ext_csd == RT_NULL) + { + LOG_E("emmc parse ext csd fail, invaild args"); + return -1; + } + card->flags |= CARD_FLAG_HIGHSPEED; card->hs_max_data_rate = 200000000; card->card_capacity = *((rt_uint32_t *)&ext_csd[EXT_CSD_SEC_CNT]); card->card_capacity *= card->card_blksize; card->card_capacity >>= 10; /* unit:KB */ - rt_kprintf("emmc card capacity %d KB\n", card->card_capacity); + LOG_I("emmc card capacity %d KB.", card->card_capacity); return 0; } @@ -333,13 +335,13 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) } else { switch(ext_csd_bits[idx]){ case 0: - rt_kprintf("switch to bus width 1 bit failed\n"); + LOG_E("switch to bus width 1 bit failed!"); break; case 1: - rt_kprintf("switch to bus width 4 bit failed\n"); + LOG_E("switch to bus width 4 bit failed!"); break; case 2: - rt_kprintf("switch to bus width 8 bit failed\n"); + LOG_E("switch to bus width 8 bit failed!"); break; default: break; @@ -414,7 +416,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, { rt_int32_t err; rt_uint32_t resp[4]; - rt_uint32_t rocr; + rt_uint32_t rocr = 0; rt_uint32_t max_data_rate; rt_uint8_t *ext_csd = RT_NULL; struct rt_mmcsd_card *card = RT_NULL; @@ -443,7 +445,7 @@ static rt_int32_t mmcsd_mmc_init_card(struct rt_mmcsd_host *host, card = rt_malloc(sizeof(struct rt_mmcsd_card)); if (!card) { - rt_kprintf("malloc card failed\n"); + LOG_E("malloc card failed!"); err = -RT_ENOMEM; goto err; } @@ -580,7 +582,7 @@ remove_card: host->card = RT_NULL; err: - rt_kprintf("init MMC card failed\n"); + LOG_E("init MMC card failed!"); return err; } diff --git a/components/drivers/sdio/mmcsd_core.c b/components/drivers/sdio/mmcsd_core.c index edf4002ac7..d1f5978374 100644 --- a/components/drivers/sdio/mmcsd_core.c +++ b/components/drivers/sdio/mmcsd_core.c @@ -1,21 +1,7 @@ /* - * File : mmcsd_core.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,6 +14,16 @@ #include #include +#define DBG_ENABLE +#define DBG_SECTION_NAME "SDIO" +#ifdef RT_SDIO_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#define DBG_COLOR +#include + #ifndef RT_MMCSD_STACK_SIZE #define RT_MMCSD_STACK_SIZE 1024 #endif @@ -206,7 +202,7 @@ rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid) buf = (rt_uint32_t *)rt_malloc(16); if (!buf) { - rt_kprintf("allocate memory failed\n"); + LOG_E("allocate memory failed!"); return -RT_ENOMEM; } @@ -282,7 +278,7 @@ rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd) buf = (rt_uint32_t*)rt_malloc(16); if (!buf) { - rt_kprintf("allocate memory failed\n"); + LOG_E("allocate memory failed!"); return -RT_ENOMEM; } @@ -418,7 +414,7 @@ void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk) { if (clk < host->freq_min) { - rt_kprintf("clock too low\n"); + LOG_W("clock too low!"); } host->io_cfg.clock = clk; @@ -539,7 +535,7 @@ rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr) } else { - rt_kprintf("host doesn't support card's voltages\n"); + LOG_W("host doesn't support card's voltages!"); ocr = 0; } @@ -679,7 +675,7 @@ void mmcsd_detect(void *param) mmcsd_host_lock(host); if (host->card->sdio_function_num != 0) { - rt_kprintf("unsupport sdio card plug out!\n"); + LOG_W("unsupport sdio card plug out!"); } else { @@ -702,7 +698,7 @@ struct rt_mmcsd_host *mmcsd_alloc_host(void) host = rt_malloc(sizeof(struct rt_mmcsd_host)); if (!host) { - rt_kprintf("alloc host failed\n"); + LOG_E("alloc host failed"); return RT_NULL; } diff --git a/components/drivers/sdio/sd.c b/components/drivers/sdio/sd.c index a42aa17531..69a4561fb0 100644 --- a/components/drivers/sdio/sd.c +++ b/components/drivers/sdio/sd.c @@ -1,21 +1,7 @@ /* - * File : sd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,6 +11,16 @@ #include #include +#define DBG_ENABLE +#define DBG_SECTION_NAME "SDIO" +#ifdef RT_SDIO_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#define DBG_COLOR +#include + static const rt_uint32_t tran_unit[] = { 10000, 100000, 1000000, 10000000, @@ -167,11 +163,11 @@ static rt_int32_t mmcsd_parse_csd(struct rt_mmcsd_card *card) #endif break; default: - rt_kprintf("unrecognised CSD structure version %d\n", csd->csd_structure); + LOG_E("unrecognised CSD structure version %d!", csd->csd_structure); return -RT_ERROR; } - rt_kprintf("SD card capacity %d KB\n", card->card_capacity); + LOG_I("SD card capacity %d KB.", card->card_capacity); return 0; } @@ -201,7 +197,7 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card) buf = (rt_uint8_t*)rt_malloc(64); if (!buf) { - rt_kprintf("alloc memory failed\n"); + LOG_E("alloc memory failed!"); return -RT_ENOMEM; } @@ -270,7 +266,7 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card) if ((buf[16] & 0xF) != 1) { - rt_kprintf("switching card to high speed failed\n"); + LOG_E("switching card to high speed failed!"); goto err; } @@ -588,7 +584,7 @@ static rt_int32_t mmcsd_sd_init_card(struct rt_mmcsd_host *host, card = rt_malloc(sizeof(struct rt_mmcsd_card)); if (!card) { - rt_kprintf("malloc card failed\n"); + LOG_E("malloc card failed!"); err = -RT_ENOMEM; goto err; } @@ -703,9 +699,9 @@ rt_int32_t init_sd(struct rt_mmcsd_host *host, rt_uint32_t ocr) if (ocr & VDD_165_195) { - rt_kprintf(" SD card claims to support the " + LOG_I(" SD card claims to support the " "incompletely defined 'low voltage range'. This " - "will be ignored.\n"); + "will be ignored."); ocr &= ~VDD_165_195; } @@ -743,7 +739,7 @@ remove_card: host->card = RT_NULL; err: - rt_kprintf("init SD card failed\n"); + LOG_D("init SD card failed!"); return err; } diff --git a/components/drivers/sdio/sdio.c b/components/drivers/sdio/sdio.c index b105e65109..6045c4ade8 100644 --- a/components/drivers/sdio/sdio.c +++ b/components/drivers/sdio/sdio.c @@ -1,21 +1,7 @@ /* - * File : sdio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,6 +12,16 @@ #include #include +#define DBG_ENABLE +#define DBG_SECTION_NAME "SDIO" +#ifdef RT_SDIO_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif /* RT_SDIO_DEBUG */ +#define DBG_COLOR +#include + #ifndef RT_SDIO_STACK_SIZE #define RT_SDIO_STACK_SIZE 512 #endif @@ -130,6 +126,7 @@ rt_int32_t sdio_io_rw_direct(struct rt_mmcsd_card *card, RT_ASSERT(card != RT_NULL); RT_ASSERT(fn <= SDIO_MAX_FUNCTIONS); + RT_ASSERT(pdata != RT_NULL); if (reg_addr & ~SDIO_ARG_CMD53_REG_MASK) return -RT_ERROR; @@ -306,7 +303,7 @@ rt_uint8_t sdio_io_readb(struct rt_sdio_function *func, rt_uint32_t reg, rt_int32_t *err) { - rt_uint8_t data; + rt_uint8_t data = 0; rt_int32_t ret; ret = sdio_io_rw_direct(func->card, 0, func->num, reg, &data, 0); @@ -432,7 +429,7 @@ static rt_int32_t sdio_read_cccr(struct rt_mmcsd_card *card) if (cccr_version > SDIO_CCCR_REV_3_00) { - rt_kprintf("unrecognised CCCR structure version %d\n", cccr_version); + LOG_E("unrecognised CCCR structure version %d", cccr_version); return -RT_ERROR; } @@ -579,7 +576,7 @@ static rt_int32_t sdio_read_cis(struct rt_sdio_function *func) case CISTPL_MANFID: if (tpl_link < 4) { - rt_kprintf("bad CISTPL_MANFID length\n"); + LOG_D("bad CISTPL_MANFID length"); break; } if (func->num != 0) @@ -605,15 +602,15 @@ static rt_int32_t sdio_read_cis(struct rt_sdio_function *func) if (ret) { - rt_kprintf("bad CISTPL_FUNCE size %u " - "type %u\n", tpl_link, curr->data[0]); + LOG_D("bad CISTPL_FUNCE size %u " + "type %u", tpl_link, curr->data[0]); } break; case CISTPL_VERS_1: if (tpl_link < 2) { - rt_kprintf("CISTPL_VERS_1 too short\n"); + LOG_D("CISTPL_VERS_1 too short"); } break; default: @@ -623,7 +620,7 @@ static rt_int32_t sdio_read_cis(struct rt_sdio_function *func) curr->size = tpl_link; *prev = curr; prev = &curr->next; - rt_kprintf( "function %d, CIS tuple code %#x, length %d\n", + LOG_D( "function %d, CIS tuple code %#x, length %d", func->num, tpl_code, tpl_link); break; } @@ -686,7 +683,6 @@ err: return ret; } - static rt_int32_t sdio_initialize_function(struct rt_mmcsd_card *card, rt_uint32_t func_num) { @@ -698,7 +694,7 @@ static rt_int32_t sdio_initialize_function(struct rt_mmcsd_card *card, func = rt_malloc(sizeof(struct rt_sdio_function)); if (!func) { - rt_kprintf("malloc rt_sdio_function failed\n"); + LOG_E("malloc rt_sdio_function failed"); ret = -RT_ENOMEM; goto err; } @@ -788,7 +784,7 @@ static rt_int32_t sdio_register_card(struct rt_mmcsd_card *card) sc = rt_malloc(sizeof(struct sdio_card)); if (sc == RT_NULL) { - rt_kprintf("malloc sdio card failed\n"); + LOG_E("malloc sdio card failed"); return -RT_ENOMEM; } @@ -836,7 +832,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) card = rt_malloc(sizeof(struct rt_mmcsd_card)); if (!card) { - rt_kprintf("malloc card failed\n"); + LOG_E("malloc card failed"); err = -RT_ENOMEM; goto err; } @@ -850,7 +846,7 @@ static rt_int32_t sdio_init_card(struct rt_mmcsd_host *host, rt_uint32_t ocr) card->sdio_function[0] = rt_malloc(sizeof(struct rt_sdio_function)); if (!card->sdio_function[0]) { - rt_kprintf("malloc sdio_func0 failed\n"); + LOG_E("malloc sdio_func0 failed"); err = -RT_ENOMEM; goto err1; } @@ -928,6 +924,7 @@ err3: host->card->sdio_function[i] = RT_NULL; rt_free(host->card); host->card = RT_NULL; + break; } } } @@ -944,7 +941,7 @@ err1: rt_free(host->card); } err: - rt_kprintf("error %d while initialising SDIO card\n", err); + LOG_E("error %d while initialising SDIO card", err); return err; } @@ -958,13 +955,13 @@ rt_int32_t init_sdio(struct rt_mmcsd_host *host, rt_uint32_t ocr) if (ocr & 0x7F) { - rt_kprintf("Card ocr below the defined voltage rang.\n"); + LOG_W("Card ocr below the defined voltage rang."); ocr &= ~0x7F; } if (ocr & VDD_165_195) { - rt_kprintf("Can't support the low voltage SDIO card.\n"); + LOG_W("Can't support the low voltage SDIO card."); ocr &= ~VDD_165_195; } @@ -987,7 +984,7 @@ remove_card: host->card = RT_NULL; err: - rt_kprintf("init SDIO card failed\n"); + LOG_E("init SDIO card failed"); return err; } @@ -1341,7 +1338,7 @@ rt_int32_t sdio_register_driver(struct rt_sdio_driver *driver) sd = rt_malloc(sizeof(struct sdio_driver)); if (sd == RT_NULL) { - rt_kprintf("malloc sdio driver failed\n"); + LOG_E("malloc sdio driver failed"); return -RT_ENOMEM; } @@ -1378,7 +1375,7 @@ rt_int32_t sdio_unregister_driver(struct rt_sdio_driver *driver) if (sd == RT_NULL) { - rt_kprintf("SDIO driver %s not register\n", driver->name); + LOG_E("SDIO driver %s not register", driver->name); return -RT_ERROR; } diff --git a/components/drivers/sensors/bmi055_sensor.cpp b/components/drivers/sensors/bmi055_sensor.cpp index 705895f368..b6e7f99da5 100644 --- a/components/drivers/sensors/bmi055_sensor.cpp +++ b/components/drivers/sensors/bmi055_sensor.cpp @@ -1,11 +1,7 @@ /* - * File : bmi055_sensor.cpp - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -137,7 +133,7 @@ BMI055_Accelerometer::BMI055_Accelerometer(const char* iic_name, int addr) write_reg(BMI055_BGW_SOFTRESET, 0xB6); /* reset of the sensor P57 */ write_reg(BMI055_PMU_LPW, 0x00); /* PMU_LPW NORMAL mode P55 */ write_reg(BMI055_PMU_BW, 0x0A); /* 01010b 31.25 Hz P55 */ - write_reg(BMI055_PMU_RANGE, 0x05); /* 0101b ±4g range PMU_RANGE set acc +-4g/s P54 */ + write_reg(BMI055_PMU_RANGE, 0x05); /* 0101b 卤4g range PMU_RANGE set acc +-4g/s P54 */ x_offset = y_offset = z_offset = 0; diff --git a/components/drivers/sensors/bmi055_sensor.h b/components/drivers/sensors/bmi055_sensor.h index 7ec6d9e5cf..713aa74ad0 100644 --- a/components/drivers/sensors/bmi055_sensor.h +++ b/components/drivers/sensors/bmi055_sensor.h @@ -1,11 +1,7 @@ /* - * File : bmi055_sensor.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/sensors/mpu6050_sensor.cpp b/components/drivers/sensors/mpu6050_sensor.cpp index 8f6557a7ce..358796bc30 100644 --- a/components/drivers/sensors/mpu6050_sensor.cpp +++ b/components/drivers/sensors/mpu6050_sensor.cpp @@ -1,11 +1,7 @@ /* - * File : MPU6050_sensor.cpp - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/sensors/mpu6050_sensor.h b/components/drivers/sensors/mpu6050_sensor.h index c7e28ba28e..8f70c3e5ed 100644 --- a/components/drivers/sensors/mpu6050_sensor.h +++ b/components/drivers/sensors/mpu6050_sensor.h @@ -1,11 +1,7 @@ /* - * File : MPU6050_sensor.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/sensors/sensor.cpp b/components/drivers/sensors/sensor.cpp index abeecdb883..f986510f63 100644 --- a/components/drivers/sensors/sensor.cpp +++ b/components/drivers/sensors/sensor.cpp @@ -1,11 +1,7 @@ /* - * File : sensors.cpp - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index fd44611f5a..916360d34b 100644 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -1,11 +1,7 @@ /* - * File : sensors.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 856e33e979..959d8444c1 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -1,21 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -84,19 +70,19 @@ static int serial_fops_open(struct dfs_fd *fd) switch (fd->flags & O_ACCMODE) { case O_RDONLY: - dbg_log(DBG_LOG, "fops open: O_RDONLY!\n"); + LOG_D("fops open: O_RDONLY!"); flags = RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_RDONLY; break; case O_WRONLY: - dbg_log(DBG_LOG, "fops open: O_WRONLY!\n"); + LOG_D("fops open: O_WRONLY!"); flags = RT_DEVICE_FLAG_WRONLY; break; case O_RDWR: - dbg_log(DBG_LOG, "fops open: O_RDWR!\n"); + LOG_D("fops open: O_RDWR!"); flags = RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_RDWR; break; default: - dbg_log(DBG_ERROR, "fops open: unknown mode - %d!\n", fd->flags & O_ACCMODE); + LOG_E("fops open: unknown mode - %d!", fd->flags & O_ACCMODE); break; } @@ -573,7 +559,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) RT_ASSERT(dev != RT_NULL); serial = (struct rt_serial_device *)dev; - dbg_log(DBG_LOG, "open serial device: 0x%08x with open flag: 0x%04x\n", + LOG_D("open serial device: 0x%08x with open flag: 0x%04x", dev, oflag); /* check device flag with the open flag */ if ((oflag & RT_DEVICE_FLAG_DMA_RX) && !(dev->flag & RT_DEVICE_FLAG_DMA_RX)) diff --git a/components/drivers/spi/SConscript b/components/drivers/spi/SConscript index ee423c33db..b88671ebc9 100644 --- a/components/drivers/spi/SConscript +++ b/components/drivers/spi/SConscript @@ -6,6 +6,9 @@ src = ['spi_core.c', 'spi_dev.c'] CPPPATH = [cwd, cwd + '/../include'] LOCAL_CCFLAGS = '' +if GetDepend('RT_USING_QSPI'): + src += ['qspi_core.c'] + src_device = [] if GetDepend('RT_USING_SPI_WIFI'): diff --git a/components/drivers/spi/enc28j60.c b/components/drivers/spi/enc28j60.c index f579dd8fdd..a8bfe3a159 100644 --- a/components/drivers/spi/enc28j60.c +++ b/components/drivers/spi/enc28j60.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "enc28j60.h" /* #define NET_TRACE */ diff --git a/components/drivers/spi/enc28j60.h b/components/drivers/spi/enc28j60.h index 1207efdec6..adff774748 100644 --- a/components/drivers/spi/enc28j60.h +++ b/components/drivers/spi/enc28j60.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef EN28J60_H_INCLUDED #define EN28J60_H_INCLUDED diff --git a/components/drivers/spi/qspi_core.c b/components/drivers/spi/qspi_core.c new file mode 100644 index 0000000000..c9ff6a9637 --- /dev/null +++ b/components/drivers/spi/qspi_core.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 zylx first version. + */ + +#include + +rt_err_t rt_qspi_configure(struct rt_qspi_device *device, struct rt_qspi_configuration *cfg) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device; + rt_err_t result = RT_EOK; + + /* copy configuration items */ + qspi_device->config.parent.mode = cfg->parent.mode; + qspi_device->config.parent.max_hz = cfg->parent.max_hz; + qspi_device->config.parent.data_width = cfg->parent.data_width; + qspi_device->config.parent.reserved = cfg->parent.reserved; + qspi_device->config.medium_size = cfg->medium_size; + qspi_device->config.ddr_mode = cfg->ddr_mode; + qspi_device->config.qspi_dl_width = cfg->qspi_dl_width; + + result = rt_spi_configure(&device->parent, &cfg->parent); + + return result; +} + +rt_err_t rt_qspi_bus_register(struct rt_spi_bus *bus, const char *name, const struct rt_spi_ops *ops) +{ + rt_err_t result = RT_EOK; + + result = rt_spi_bus_register(bus, name, ops); + if(result == RT_EOK) + { + /* set SPI bus to qspi modes */ + bus->mode = RT_SPI_BUS_MODE_QSPI; + } + + return result; +} + +rt_size_t rt_qspi_transfer_message(struct rt_qspi_device *device, struct rt_qspi_message *message) +{ + rt_err_t result; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(message != RT_NULL); + + result = rt_mutex_take(&(device->parent.bus->lock), RT_WAITING_FOREVER); + if (result != RT_EOK) + { + rt_set_errno(-RT_EBUSY); + + return 0; + } + + /* reset errno */ + rt_set_errno(RT_EOK); + + /* configure SPI bus */ + if (device->parent.bus->owner != &device->parent) + { + /* not the same owner as current, re-configure SPI bus */ + result = device->parent.bus->ops->configure(&device->parent, &device->parent.config); + if (result == RT_EOK) + { + /* set SPI bus owner */ + device->parent.bus->owner = &device->parent; + } + else + { + /* configure SPI bus failed */ + rt_set_errno(-RT_EIO); + goto __exit; + } + } + + /* transmit each SPI message */ + + result = device->parent.bus->ops->xfer(&device->parent, &message->parent); + if (result == 0) + { + rt_set_errno(-RT_EIO); + } + +__exit: + /* release bus lock */ + rt_mutex_release(&(device->parent.bus->lock)); + + return result; +} + +rt_err_t rt_qspi_send_then_recv(struct rt_qspi_device *device, const void *send_buf, rt_size_t send_length, void *recv_buf, rt_size_t recv_length) +{ + RT_ASSERT(send_buf); + RT_ASSERT(recv_buf); + RT_ASSERT(send_length != 0); + + struct rt_qspi_message message; + unsigned char *ptr = (unsigned char *)send_buf; + rt_size_t count = 0; + rt_err_t result = 0; + + message.instruction.content = ptr[0]; + message.instruction.qspi_lines = 1; + count++; + + /* get address */ + if (send_length > 1) + { + if (device->config.medium_size > 0x1000000 && send_length >= 5) + { + /* medium size greater than 16Mb, address size is 4 Byte */ + message.address.content = (ptr[1] << 24) | (ptr[2] << 16) | (ptr[3] << 8) | (ptr[4]); + message.address.size = 32; + count += 4; + } + else if (send_length >= 4) + { + /* address size is 3 Byte */ + message.address.content = (ptr[1] << 16) | (ptr[2] << 8) | (ptr[3]); + message.address.size = 24; + count += 3; + } + else + { + return -RT_ERROR; + } + message.address.qspi_lines = 1; + } + else + { + /* no address stage */ + message.address.content = 0 ; + message.address.qspi_lines = 0; + message.address.size = 0; + } + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.qspi_lines = 0; + + /* set dummy cycles */ + if (count != send_length) + { + message.dummy_cycles = (send_length - count) * 8; + + } + else + { + message.dummy_cycles = 0; + } + + /* set recv buf and recv size */ + message.parent.recv_buf = recv_buf; + message.parent.send_buf = RT_NULL; + message.parent.length = recv_length; + message.parent.cs_take = 1; + message.parent.cs_release = 1; + + message.qspi_data_lines = 1; + + result = rt_qspi_transfer_message(device, &message); + if (result == 0) + { + result = -RT_EIO; + } + else + { + result = recv_length; + } + + return result; +} + +rt_err_t rt_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_size_t length) +{ + RT_ASSERT(send_buf); + RT_ASSERT(length != 0); + + struct rt_qspi_message message; + char *ptr = (char *)send_buf; + rt_size_t count = 0; + rt_err_t result = 0; + + message.instruction.content = ptr[0]; + message.instruction.qspi_lines = 1; + count++; + + /* get address */ + if (length > 1) + { + if (device->config.medium_size > 0x1000000 && length >= 5) + { + /* medium size greater than 16Mb, address size is 4 Byte */ + message.address.content = (ptr[1] << 24) | (ptr[2] << 16) | (ptr[3] << 8) | (ptr[4]); + message.address.size = 32; + message.address.qspi_lines = 1; + count += 4; + } + else if (length >= 4) + { + /* address size is 3 Byte */ + message.address.content = (ptr[1] << 16) | (ptr[2] << 8) | (ptr[3]); + message.address.size = 24; + message.address.qspi_lines = 1; + count += 3; + } + else + { + return -RT_ERROR; + } + + } + else + { + /* no address stage */ + message.address.content = 0 ; + message.address.qspi_lines = 0; + message.address.size = 0; + } + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.qspi_lines = 0; + + message.dummy_cycles = 0; + + /* determine if there is data to send */ + if (length - count > 0) + { + message.qspi_data_lines = 1; + } + else + { + message.qspi_data_lines = 0; + + } + + /* set send buf and send size */ + message.parent.send_buf = ptr + count; + message.parent.recv_buf = RT_NULL; + message.parent.length = length - count; + message.parent.cs_take = 1; + message.parent.cs_release = 1; + + result = rt_qspi_transfer_message(device, &message); + if (result == 0) + { + result = -RT_EIO; + } + else + { + result = length; + } + + return result; +} diff --git a/components/drivers/spi/sfud/README.md b/components/drivers/spi/sfud/README.md index 7394321243..c732d06dbe 100644 --- a/components/drivers/spi/sfud/README.md +++ b/components/drivers/spi/sfud/README.md @@ -6,11 +6,13 @@ [SFUD](https://github.com/armink/SFUD) 是一款开源的串行 SPI Flash 通用驱动库。由于现有市面的串行 Flash 种类居多，各个 Flash 的规格及命令存在差异， SFUD 就是为了解决这些 Flash 的差异现状而设计，让我们的产品能够支持不同品牌及规格的 Flash，提高了涉及到 Flash 功能的软件的可重用性及可扩展性，同时也可以规避 Flash 缺货或停产给产品所带来的风险。 -- 主要特点：面向对象（同时支持多个 Flash 对象）、可灵活裁剪、扩展性强、支持 4 字节地址 +- 主要特点：支持 SPI/QSPI 接口、面向对象（同时支持多个 Flash 对象）、可灵活裁剪、扩展性强、支持 4 字节地址 - 资源占用 - 标准占用：RAM:0.2KB ROM:5.5KB - 最小占用：RAM:0.1KB ROM:3.6KB -- 设计思路：这里要首先跟大家介绍一个标准： **SFDP** ，它是 JEDEC （固态技术协会）制定的串行 Flash 功能的参数表标准，最新版 V1.6B （[点击这里查看](https://www.jedec.org/standards-documents/docs/jesd216b)）。该标准规定了，每个 Flash 中会存在一个参数表，该表中会存放 Flash 容量、写粒度、擦除命令、地址模式等 Flash 规格参数。目前，除了部分厂家旧款 Flash 型号会不支持该标准，其他绝大多数新出厂的 Flash 均已支持 SFDP 标准。所以该库在初始化时会优先读取 SFDP 表参数，如果该 Flash 不支持 SFDP，则查询配置文件 ( [`/sfud/inc/sfud_flash_def.h`](https://github.com/armink/SFUD/blob/master/sfud/inc/sfud_flash_def.h#L110-L122) ) 中提供的 **Flash 参数信息表** 中是否支持该款 Flash。如果不支持，则可以在配置文件中添加该款 Flash 的参数信息（添加方法详细见 [2.5 添加库目前不支持的 Flash](#25-添加库目前不支持的-flash)）。获取到了 Flash 的规格参数后，就可以实现对 Flash 的全部操作。 +- 设计思路： + - **什么是 SFDP** ：它是 JEDEC （固态技术协会）制定的串行 Flash 功能的参数表标准，最新版 V1.6B （[点击这里查看](https://www.jedec.org/standards-documents/docs/jesd216b)）。该标准规定了，每个 Flash 中会存在一个参数表，该表中会存放 Flash 容量、写粒度、擦除命令、地址模式等 Flash 规格参数。目前，除了部分厂家旧款 Flash 型号会不支持该标准，其他绝大多数新出厂的 Flash 均已支持 SFDP 标准。所以该库在初始化时会优先读取 SFDP 表参数。 + - **不支持 SFDP 怎么办** ：如果该 Flash 不支持 SFDP 标准，SFUD 会查询配置文件 ( [`/sfud/inc/sfud_flash_def.h`](https://github.com/armink/SFUD/blob/4bee2d0417a7ce853cc7aa3639b03fe825611fd9/sfud/inc/sfud_flash_def.h#L116-L142) ) 中提供的 **Flash 参数信息表** 中是否支持该款 Flash。如果不支持，则可以在配置文件中添加该款 Flash 的参数信息（添加方法详细见 [2.5 添加库目前不支持的 Flash](#25-添加库目前不支持的-flash)）。获取到了 Flash 的规格参数后，就可以实现对 Flash 的全部操作。 ## 1、为什么选择 SFUD @@ -23,37 +25,43 @@ ### 2.1 已支持 Flash -下表为所有在 Demo 平台上进行过真机测试的 Flash。目前 SFUD 提供的 **Flash 参数信息表** 只包括下表中 **不支持** SFDP 标准的 Flash，其他不支持 SFDP 标准的 Flash 需要大家以后 **共同来完善和维护** **([Github](https://github.com/armink/SFUD)|[OSChina](http://git.oschina.net/armink/SFUD)|[Coding](https://coding.net/u/armink/p/SFUD/git))** 。如果觉得这个开源项目很赞，可以点击 [项目主页](https://github.com/armink/SFUD) 右上角的 **Star** ，同时把它推荐给更多有需要的朋友。 +下表为所有已在 Demo 平台上进行过真机测试过的 Flash。显示为 **不支持** SFDP 标准的 Flash 已经在 Flash 参数信息表中定义，更多不支持 SFDP 标准的 Flash 需要大家以后 **共同来完善和维护** **([Github](https://github.com/armink/SFUD)|[OSChina](http://git.oschina.net/armink/SFUD)|[Coding](https://coding.net/u/armink/p/SFUD/git))** 。 -|型号|制造商|容量|最高速度|SFDP 标准|备注| -|:--:|:----:|:--:|:--:|:--:|:--:| -|[W25Q40BV](http://microchip.ua/esp8266/W25Q40BV(EOL).pdf)|Winbond|4Mb|50Mhz|不支持|已停产| -|[W25Q80DV](http://www.winbond.com/resource-files/w25q80dv_revg_07212015.pdf)|Winbond|8Mb|104Mhz|支持|| -|[W25Q16BV](https://media.digikey.com/pdf/Data%20Sheets/Winbond%20PDFs/W25Q16BV.pdf)|Winbond|16Mb|104Mhz|不支持| by [slipperstree](https://github.com/slipperstree)| -|[W25Q16CV](http://www.winbond.com/resource-files/da00-w25q16cvf1.pdf)|Winbond|16Mb|104Mhz|支持|| -|[W25Q16DV](http://www.winbond.com/resource-files/w25q16dv%20revk%2005232016%20doc.pdf)|Winbond|16Mb|104Mhz|支持| by [slipperstree](https://github.com/slipperstree)| -|[W25Q32BV](http://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf)|Winbond|32Mb|104Mhz|支持|| -|[W25Q64CV](http://www.winbond.com/resource-files/w25q64cv_revh_052214[2].pdf)|Winbond|64Mb|80Mhz|支持|| -|[W25Q128BV](http://www.winbond.com/resource-files/w25q128bv_revh_100313_wo_automotive.pdf)|Winbond|128Mb|104Mhz|支持|| -|[W25Q256FV](http://www.winbond.com/resource-files/w25q256fv%20revi%2002262016%20kms.pdf)|Winbond|256Mb|104Mhz|支持|| -|[MX25L3206E](http://www.macronix.com/Lists/DataSheet/Attachments/3199/MX25L3206E,%203V,%2032Mb,%20v1.5.pdf)|Macronix|32Mb|86MHz|支持|| -|[KH25L4006E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/117/KH25L4006E.pdf)|Macronix|4Mb|86Mhz|支持| by [JiapengLi](https://github.com/JiapengLi)| -|[KH25L3206E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/131/KH25L3206E.pdf)|Macronix|32Mb|86Mhz|支持|| -|[SST25VF016B](http://ww1.microchip.com/downloads/en/DeviceDoc/20005044C.pdf)|Microchip|16Mb|50MHz|不支持| SST 已被 Microchip 收购| -|[M25P40](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p40.pdf)|Micron|4Mb|75Mhz|不支持| by [redocCheng](https://github.com/redocCheng)| -|[M25P80](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p80.pdf)|Micron|8Mb|75Mhz|不支持| by [redocCheng](https://github.com/redocCheng)| -|[M25P32](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p32.pdf)|Micron|32Mb|75Mhz|不支持|| -|[EN25Q32B](http://www.kean.com.au/oshw/WR703N/teardown/EN25Q32B%2032Mbit%20SPI%20Flash.pdf)|EON|32Mb|104MHz|不支持|| -|[GD25Q16B](http://www.gigadevice.com/product/detail/5/410.html)|GigaDevice|16Mb|120Mhz|不支持| by [TanekLiang](https://github.com/TanekLiang) | -|[GD25Q64B](http://www.gigadevice.com/product/detail/5/364.html)|GigaDevice|64Mb|120Mhz|不支持|| -|[S25FL216K](http://www.cypress.com/file/197346/download)|Cypress|16Mb|65Mhz|不支持|| -|[S25FL032P](http://www.cypress.com/file/196861/download)|Cypress|32Mb|104Mhz|不支持| by [yc_911](https://gitee.com/yc_911) | -|[S25FL164K](http://www.cypress.com/file/196886/download)|Cypress|64Mb|108Mhz|支持|| -|[A25L080](http://www.amictechnology.com/datasheets/A25L080.pdf)|AMIC|8Mb|100Mhz|不支持|| -|[A25LQ64](http://www.amictechnology.com/datasheets/A25LQ64.pdf)|AMIC|64Mb|104Mhz|支持|| -|[F25L004](http://www.esmt.com.tw/db/manager/upload/f25l004.pdf)|ESMT|4Mb|100Mhz|不支持|| -|[PCT25VF016B](http://pctgroup.com.tw/attachments/files/files/248_25VF016B-P.pdf)|PCT|16Mb|80Mhz|不支持|SST 授权许可，会被识别为 SST25VF016B| -|[AT45DB161E](http://www.adestotech.com/wp-content/uploads/doc8782.pdf)|ADESTO|16Mb|85MHz|不支持|ADESTO 收购 Atmel 串行闪存产品线| +如果觉得这个开源项目很赞，可以点击 [项目主页](https://github.com/armink/SFUD) 右上角的 **Star** ，同时把它推荐给更多有需要的朋友。 + +|型号|制造商|容量|最高速度|SFDP 标准|QSPI 模式|备注| +|:--:|:----:|:--:|:--:|:--:|:--:|----| +|[W25Q40BV](http://microchip.ua/esp8266/W25Q40BV(EOL).pdf)|Winbond|4Mb|50Mhz|不支持|双线|已停产| +|[W25Q80DV](http://www.winbond.com/resource-files/w25q80dv_revg_07212015.pdf)|Winbond|8Mb|104Mhz|支持|双线|| +|[W25Q16BV](https://media.digikey.com/pdf/Data%20Sheets/Winbond%20PDFs/W25Q16BV.pdf)|Winbond|16Mb|104Mhz|不支持|双线| by [slipperstree](https://github.com/slipperstree)| +|[W25Q16CV](http://www.winbond.com/resource-files/da00-w25q16cvf1.pdf)|Winbond|16Mb|104Mhz|支持|未测试|| +|[W25Q16DV](http://www.winbond.com/resource-files/w25q16dv%20revk%2005232016%20doc.pdf)|Winbond|16Mb|104Mhz|支持|未测试| by [slipperstree](https://github.com/slipperstree)| +|[W25Q32BV](http://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf)|Winbond|32Mb|104Mhz|支持|双线|| +|[W25Q64CV](http://www.winbond.com/resource-files/w25q64cv_revh_052214[2].pdf)|Winbond|64Mb|80Mhz|支持|四线|| +|[W25Q128BV](http://www.winbond.com/resource-files/w25q128bv_revh_100313_wo_automotive.pdf)|Winbond|128Mb|104Mhz|支持|四线|| +|[W25Q256FV](http://www.winbond.com/resource-files/w25q256fv%20revi%2002262016%20kms.pdf)|Winbond|256Mb|104Mhz|支持|四线|| +|[MX25L3206E](http://www.macronix.com/Lists/DataSheet/Attachments/3199/MX25L3206E,%203V,%2032Mb,%20v1.5.pdf)|Macronix|32Mb|86MHz|支持|双线|| +|[KH25L4006E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/117/KH25L4006E.pdf)|Macronix|4Mb|86Mhz|支持|未测试| by [JiapengLi](https://github.com/JiapengLi)| +|[KH25L3206E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/131/KH25L3206E.pdf)|Macronix|32Mb|86Mhz|支持|双线|| +|[SST25VF016B](http://ww1.microchip.com/downloads/en/DeviceDoc/20005044C.pdf)|Microchip|16Mb|50MHz|不支持|不支持| SST 已被 Microchip 收购| +|[M25P40](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p40.pdf)|Micron|4Mb|75Mhz|不支持|未测试| by [redocCheng](https://github.com/redocCheng)| +|[M25P80](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p80.pdf)|Micron|8Mb|75Mhz|不支持|未测试| by [redocCheng](https://github.com/redocCheng)| +|[M25P32](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p32.pdf)|Micron|32Mb|75Mhz|不支持|不支持|| +|[EN25Q32B](http://www.kean.com.au/oshw/WR703N/teardown/EN25Q32B%2032Mbit%20SPI%20Flash.pdf)|EON|32Mb|104MHz|不支持|未测试|| +|[GD25Q16B](http://www.gigadevice.com/product/detail/5/410.html)|GigaDevice|16Mb|120Mhz|不支持|未测试| by [TanekLiang](https://github.com/TanekLiang) | +|[GD25Q64B](http://www.gigadevice.com/product/detail/5/364.html)|GigaDevice|64Mb|120Mhz|不支持|双线|| +|[S25FL216K](http://www.cypress.com/file/197346/download)|Cypress|16Mb|65Mhz|不支持|双线|| +|[S25FL032P](http://www.cypress.com/file/196861/download)|Cypress|32Mb|104Mhz|不支持|未测试| by [yc_911](https://gitee.com/yc_911) | +|[S25FL164K](http://www.cypress.com/file/196886/download)|Cypress|64Mb|108Mhz|支持|未测试|| +|[A25L080](http://www.amictechnology.com/datasheets/A25L080.pdf)|AMIC|8Mb|100Mhz|不支持|双线|| +|[A25LQ64](http://www.amictechnology.com/datasheets/A25LQ64.pdf)|AMIC|64Mb|104Mhz|支持|支持|| +|[F25L004](http://www.esmt.com.tw/db/manager/upload/f25l004.pdf)|ESMT|4Mb|100Mhz|不支持|不支持|| +|[PCT25VF016B](http://pctgroup.com.tw/attachments/files/files/248_25VF016B-P.pdf)|PCT|16Mb|80Mhz|不支持|不支持|SST 授权许可，会被识别为 SST25VF016B| +|[AT45DB161E](http://www.adestotech.com/wp-content/uploads/doc8782.pdf)|ADESTO|16Mb|85MHz|不支持|不支持|ADESTO 收购 Atmel 串行闪存产品线| + +> 注：QSPI 模式中，双线表示支持双线快读，四线表示支持四线快读。 +> +> 一般情况下，支持四线快读的 FLASH 也支持两线快读。 ### 2.2 API 说明 @@ -63,7 +71,7 @@ 将会调用 `sfud_device_init` ，初始化 Flash 设备表中的全部设备。如果只有一个 Flash 也可以只使用 `sfud_device_init` 进行单一初始化。 -> 注意：初始化完的 SPI Flash 默认都 **已取消写保护** 状态，如需开启写保护，请使用 sfud_write_status 函数修改 SPI Flash 状态。 +> **注意**：初始化完的 SPI Flash 默认都 **已取消写保护** 状态，如需开启写保护，请使用 sfud_write_status 函数修改 SPI Flash 状态。 ```C sfud_err sfud_init(void) @@ -79,7 +87,24 @@ sfud_err sfud_device_init(sfud_flash *flash) |:----- |:----| |flash |待初始化的 Flash 设备| -#### 2.2.3 获取 Flash 设备对象 +#### 2.2.3 使能快速读模式（仅当 SFUD 开启 QSPI 模式后可用） + +当 SFUD 开启 QSPI 模式后，SFUD 中的 Flash 驱动支持使用 QSPI 总线进行通信。相比传统的 SPI 模式，使用 QSPI 能够加速 Flash 数据的读取，但当数据需要写入时，由于 Flash 本身的数据写入速度慢于 SPI 传输速度，所以 QSPI 模式下的数据写入速度提升并不明显。 + +所以 SFUD 对于 QSPI 模式的支持仅限于快速读命令。通过该函数可以配置 Flash 所使用的 QSPI 总线的实际支持的数据线最大宽度，例如：1 线（默认值，即传统的 SPI 模式）、2 线、4 线。 + +设置后，SFUD 会去结合当前设定的 QSPI 总线数据线宽度，去 [QSPI Flash 扩展信息表](https://github.com/armink/SFUD/blob/069d2b409ec239f84d675b2c3d37894e908829e6/sfud/inc/sfud_flash_def.h#L149-L177) 中匹配最合适的、速度最快的快速读命令，之后用户在调用 sfud_read() 时，会使用 QSPI 模式的传输函数发送该命令。 + +```C +sfud_err sfud_qspi_fast_read_enable(sfud_flash *flash, uint8_t data_line_width) +``` + +| 参数 | 描述 | +| :-------------- | :------------------------------------------- | +| flash | Flash 设备 | +| data_line_width | QSPI 总线支持的数据线最大宽度，例如：1、2、4 | + +#### 2.2.4 获取 Flash 设备对象 在 SFUD 配置文件中会定义 Flash 设备表，负责存放所有将要使用的 Flash 设备对象，所以 SFUD 支持多个 Flash 设备同时驱动。设备表的配置在 `/sfud/inc/sfud_cfg.h` 中 `SFUD_FLASH_DEVICE_TABLE` 宏定义，详细配置方法参照 [2.3 配置方法 Flash](#23-配置方法)）。本方法通过 Flash 设备位于设备表中索引值来返回 Flash 设备对象，超出设备表范围返回 `NULL` 。 @@ -91,7 +116,7 @@ sfud_flash *sfud_get_device(size_t index) |:----- |:----| |index |Flash 设备位于 FLash 设备表中的索引值| -#### 2.2.4 读取 Flash 数据 +#### 2.2.5 读取 Flash 数据 ```C sfud_err sfud_read(const sfud_flash *flash, uint32_t addr, size_t size, uint8_t *data) @@ -104,7 +129,7 @@ sfud_err sfud_read(const sfud_flash *flash, uint32_t addr, size_t size, uint8_t |size |从起始地址开始读取数据的总大小| |data |读取到的数据| -#### 2.2.5 擦除 Flash 数据 +#### 2.2.6 擦除 Flash 数据 > 注意：擦除操作将会按照 Flash 芯片的擦除粒度（详见 Flash 数据手册，一般为 block 大小。初始化完成后，可以通过 `sfud_flash->chip.erase_gran` 查看）对齐，请注意保证起始地址和擦除数据大小按照 Flash 芯片的擦除粒度对齐，否则执行擦除操作后，将会导致其他数据丢失。 @@ -118,7 +143,7 @@ sfud_err sfud_erase(const sfud_flash *flash, uint32_t addr, size_t size) |addr |起始地址| |size |从起始地址开始擦除数据的总大小| -#### 2.2.6 擦除 Flash 全部数据 +#### 2.2.7 擦除 Flash 全部数据 ```C sfud_err sfud_chip_erase(const sfud_flash *flash) @@ -128,7 +153,7 @@ sfud_err sfud_chip_erase(const sfud_flash *flash) |:----- |:----| |flash |Flash 设备对象| -#### 2.2.7 往 Flash 写数据 +#### 2.2.8 往 Flash 写数据 ```C sfud_err sfud_write(const sfud_flash *flash, uint32_t addr, size_t size, const uint8_t *data) @@ -141,7 +166,7 @@ sfud_err sfud_write(const sfud_flash *flash, uint32_t addr, size_t size, const u |size |从起始地址开始写入数据的总大小| |data |待写入的数据| -#### 2.2.8 先擦除再往 Flash 写数据 +#### 2.2.9 先擦除再往 Flash 写数据 > 注意：擦除操作将会按照 Flash 芯片的擦除粒度（详见 Flash 数据手册，一般为 block 大小。初始化完成后，可以通过 `sfud_flash->chip.erase_gran` 查看）对齐，请注意保证起始地址和擦除数据大小按照 Flash 芯片的擦除粒度对齐，否则执行擦除操作后，将会导致其他数据丢失。 @@ -156,7 +181,7 @@ sfud_err sfud_erase_write(const sfud_flash *flash, uint32_t addr, size_t size, c |size |从起始地址开始写入数据的总大小| |data |待写入的数据| -#### 2.2.9 读取 Flash 状态 +#### 2.2.10 读取 Flash 状态 ```C sfud_err sfud_read_status(const sfud_flash *flash, uint8_t *status) @@ -167,7 +192,7 @@ sfud_err sfud_read_status(const sfud_flash *flash, uint8_t *status) |flash |Flash 设备对象| |status |当前状态寄存器值| -#### 2.2.10 写（修改） Flash 状态 +#### 2.2.11 写（修改） Flash 状态 ```C sfud_err sfud_write_status(const sfud_flash *flash, bool is_volatile, uint8_t status) @@ -234,6 +259,12 @@ enum { 上面定义了两个 Flash 设备（大部分产品一个足以），两个设备的名称为 `"W25Q64CV"` 及 `"GD25Q64B"` ，分别对应 `"SPI1"` 及 `"SPI3"` 这两个 SPI 设备名称（在移植 SPI 接口时会用到，位于 `/sfud/port/sfud_port.c` ）， `SFUD_W25Q16CV_DEVICE_INDEX` 与 `SFUD_GD25Q64B_DEVICE_INDEX` 这两个枚举定义了两个设备位于设备表中的索引，可以通过 `sfud_get_device_table()` 方法获取到设备表，再配合这个索引值来访问指定的设备。 +#### 2.3.6 QSPI 模式 + +打开/关闭 `SFUD_USING_QSPI` 宏定义 + +开启后，SFUD 也将支持使用 QSPI 总线连接的 Flash。 + ### 2.4 移植说明 移植文件位于 `/sfud/port/sfud_port.c` ，文件中的 `sfud_err sfud_spi_port_init(sfud_flash *flash)` 方法是库提供的移植方法，在里面完成各个设备 SPI 读写驱动（必选）、重试次数（必选）、重试接口（可选）及 SPI 锁（可选）的配置。更加详细的移植内容，可以参考 demo 中的各个平台的移植文件。 @@ -258,6 +289,7 @@ enum { |:----- |:----| |[/demo/stm32f10x_non_os](https://github.com/armink/SFUD/tree/master/demo/stm32f10x_non_os) |STM32F10X 裸机平台| |[/demo/stm32f2xx_rtt](https://github.com/armink/SFUD/tree/master/demo/stm32f2xx_rtt) |STM32F2XX + [RT-Thread](http://www.rt-thread.org/) 操作系统平台| +|[/demo/stm32l475_non_os_qspi](https://github.com/armink/SFUD/tree/master/demo/stm32l475_non_os_qspi) |STM32L475 + QSPI 模式 裸机平台| ### 2.7 许可 diff --git a/components/drivers/spi/sfud/inc/sfud.h b/components/drivers/spi/sfud/inc/sfud.h index be1ccb208e..2b68c38216 100644 --- a/components/drivers/spi/sfud/inc/sfud.h +++ b/components/drivers/spi/sfud/inc/sfud.h @@ -1,7 +1,7 @@ /* * This file is part of the Serial Flash Universal Driver Library. * - * Copyright (c) 2016, Armink, + * Copyright (c) 2016-2018, Armink, * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -75,6 +75,23 @@ size_t sfud_get_device_num(void); */ const sfud_flash *sfud_get_device_table(void); +#ifdef SFUD_USING_QSPI +/** + * Enbale the fast read mode in QSPI flash mode. Default read mode is normal SPI mode. + * + * it will find the appropriate fast-read instruction to replace the read instruction(0x03) + * fast-read instruction @see SFUD_FLASH_EXT_INFO_TABLE + * + * @note When Flash is in QSPI mode, the method must be called after sfud_device_init(). + * + * @param flash flash device + * @param data_line_width the data lines max width which QSPI bus supported, such as 1, 2, 4 + * + * @return result + */ +sfud_err sfud_qspi_fast_read_enable(sfud_flash *flash, uint8_t data_line_width); +#endif /* SFUD_USING_QSPI */ + /** * read flash data * diff --git a/components/drivers/spi/sfud/inc/sfud_cfg.h b/components/drivers/spi/sfud/inc/sfud_cfg.h index 59189a9693..051de6d577 100644 --- a/components/drivers/spi/sfud/inc/sfud_cfg.h +++ b/components/drivers/spi/sfud/inc/sfud_cfg.h @@ -45,6 +45,13 @@ #define SFUD_USING_SFDP #endif +/** + * SFUD will support QSPI mode. + */ +#ifdef RT_SFUD_USING_QSPI +#define SFUD_USING_QSPI +#endif + /** * Using probe flash JEDEC ID then query defined supported flash chip information table. @see SFUD_FLASH_CHIP_TABLE */ diff --git a/components/drivers/spi/sfud/inc/sfud_def.h b/components/drivers/spi/sfud/inc/sfud_def.h index 1b0e8a3986..fe7876618b 100644 --- a/components/drivers/spi/sfud/inc/sfud_def.h +++ b/components/drivers/spi/sfud/inc/sfud_def.h @@ -1,7 +1,7 @@ /* * This file is part of the Serial Flash Universal Driver Library. * - * Copyright (c) 2016, Armink, + * Copyright (c) 2016-2018, Armink, * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -78,7 +78,7 @@ if (!(EXPR)) \ else {if (__delay_temp) {__delay_temp();} retry --;} /* software version number */ -#define SFUD_SW_VERSION "1.0.6" +#define SFUD_SW_VERSION "1.1.0" /* * all defined supported command */ @@ -118,6 +118,22 @@ if (!(EXPR)) \ #define SFUD_CMD_READ_DATA 0x03 #endif +#ifndef SFUD_CMD_DUAL_OUTPUT_READ_DATA +#define SFUD_CMD_DUAL_OUTPUT_READ_DATA 0x3B +#endif + +#ifndef SFUD_CMD_DUAL_IO_READ_DATA +#define SFUD_CMD_DUAL_IO_READ_DATA 0xBB +#endif + +#ifndef SFUD_CMD_QUAD_IO_READ_DATA +#define SFUD_CMD_QUAD_IO_READ_DATA 0xEB +#endif + +#ifndef SFUD_CMD_QUAD_OUTPUT_READ_DATA +#define SFUD_CMD_QUAD_OUTPUT_READ_DATA 0x6B +#endif + #ifndef SFUD_CMD_MANUFACTURER_DEVICE_ID #define SFUD_CMD_MANUFACTURER_DEVICE_ID 0x90 #endif @@ -183,6 +199,21 @@ typedef enum { SFUD_ERR_ADDR_OUT_OF_BOUND = 5, /**< address is out of flash bound */ } sfud_err; +#ifdef SFUD_USING_QSPI +/** + * QSPI flash read cmd format + */ +typedef struct { + uint8_t instruction; + uint8_t instruction_lines; + uint8_t address_size; + uint8_t address_lines; + uint8_t alternate_bytes_lines; + uint8_t dummy_cycles; + uint8_t data_lines; +} sfud_qspi_read_cmd_format; +#endif /* SFUD_USING_QSPI */ + /* SPI bus write read data function type */ typedef sfud_err (*spi_write_read_func)(const uint8_t *write_buf, size_t write_size, uint8_t *read_buf, size_t read_size); @@ -218,7 +249,12 @@ typedef struct __sfud_spi { char *name; /* SPI bus write read data function */ sfud_err (*wr)(const struct __sfud_spi *spi, const uint8_t *write_buf, size_t write_size, uint8_t *read_buf, - size_t read_size); + size_t read_size); +#ifdef SFUD_USING_QSPI + /* QSPI fast read function */ + sfud_err (*qspi_read)(const struct __sfud_spi *spi, uint32_t addr, sfud_qspi_read_cmd_format *qspi_read_cmd_format, + uint8_t *read_buf, size_t read_size); +#endif /* lock SPI bus */ void (*lock)(const struct __sfud_spi *spi); /* unlock SPI bus */ @@ -243,6 +279,10 @@ typedef struct { } retry; void *user_data; /**< some user data */ +#ifdef SFUD_USING_QSPI + sfud_qspi_read_cmd_format read_cmd_format; /**< fast read cmd format */ +#endif + #ifdef SFUD_USING_SFDP sfud_sfdp sfdp; /**< serial flash discoverable parameters by JEDEC standard */ #endif diff --git a/components/drivers/spi/sfud/inc/sfud_flash_def.h b/components/drivers/spi/sfud/inc/sfud_flash_def.h index 2022a043b2..8922375557 100644 --- a/components/drivers/spi/sfud/inc/sfud_flash_def.h +++ b/components/drivers/spi/sfud/inc/sfud_flash_def.h @@ -1,7 +1,7 @@ /* * This file is part of the Serial Flash Universal Driver Library. * - * Copyright (c) 2016-2017, Armink, + * Copyright (c) 2016-2018, Armink, * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -59,11 +59,21 @@ typedef struct { uint8_t type_id; /**< memory type ID */ uint8_t capacity_id; /**< capacity ID */ uint32_t capacity; /**< flash capacity (bytes) */ - uint16_t write_mode; /**< write mode @see sfud_write_mode */ + uint16_t write_mode; /**< write mode @see sfud_write_mode */ uint32_t erase_gran; /**< erase granularity (bytes) */ uint8_t erase_gran_cmd; /**< erase granularity size block command */ } sfud_flash_chip; +#ifdef SFUD_USING_QSPI +/* QSPI flash chip's extended information compared with SPI flash */ +typedef struct { + uint8_t mf_id; /**< manufacturer ID */ + uint8_t type_id; /**< memory type ID */ + uint8_t capacity_id; /**< capacity ID */ + uint8_t read_mode; /**< supported read mode on this qspi flash chip */ +} sfud_qspi_flash_ext_info; +#endif + /* SFUD support manufacturer JEDEC ID */ #define SFUD_MF_ID_CYPRESS 0x01 #define SFUD_MF_ID_FUJITSU 0x04 @@ -131,6 +141,42 @@ typedef struct { } #endif /* SFUD_USING_FLASH_INFO_TABLE */ +#ifdef SFUD_USING_QSPI +/* This table saves flash read-fast instructions in QSPI mode, + * SFUD can use this table to select the most appropriate read instruction for flash. + * | mf_id | type_id | capacity_id | qspi_read_mode | + */ +#define SFUD_FLASH_EXT_INFO_TABLE \ +{ \ + /* W25Q40BV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x13, NORMAL_SPI_READ|DUAL_OUTPUT}, \ + /* W25Q80JV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x14, NORMAL_SPI_READ|DUAL_OUTPUT}, \ + /* W25Q16BV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x15, NORMAL_SPI_READ|DUAL_OUTPUT}, \ + /* W25Q32BV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x16, NORMAL_SPI_READ|DUAL_OUTPUT}, \ + /* W25Q64JV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x17, NORMAL_SPI_READ|DUAL_OUTPUT|DUAL_IO|QUAD_OUTPUT|QUAD_IO}, \ + /* W25Q128JV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x18, NORMAL_SPI_READ|DUAL_OUTPUT|DUAL_IO|QUAD_OUTPUT|QUAD_IO}, \ + /* W25Q256FV */ \ + {SFUD_MF_ID_WINBOND, 0x40, 0x19, NORMAL_SPI_READ|DUAL_OUTPUT|DUAL_IO|QUAD_OUTPUT|QUAD_IO}, \ + /* EN25Q32B */ \ + {SFUD_MF_ID_EON, 0x30, 0x16, NORMAL_SPI_READ|DUAL_OUTPUT|QUAD_IO}, \ + /* S25FL216K */ \ + {SFUD_MF_ID_CYPRESS, 0x40, 0x15, NORMAL_SPI_READ|DUAL_OUTPUT}, \ + /* A25L080 */ \ + {SFUD_MF_ID_AMIC, 0x30, 0x14, NORMAL_SPI_READ|DUAL_OUTPUT|DUAL_IO}, \ + /* A25LQ64 */ \ + {SFUD_MF_ID_AMIC, 0x40, 0x17, NORMAL_SPI_READ|DUAL_OUTPUT|DUAL_IO|QUAD_IO}, \ + /* MX25L3206E and KH25L3206E */ \ + {SFUD_MF_ID_MICRONIX, 0x20, 0x16, NORMAL_SPI_READ|DUAL_OUTPUT}, \ + /* GD25Q64B */ \ + {SFUD_MF_ID_GIGADEVICE, 0x40, 0x17, NORMAL_SPI_READ|DUAL_OUTPUT}, \ +} +#endif /* SFUD_USING_QSPI */ + #ifdef __cplusplus } #endif diff --git a/components/drivers/spi/sfud/src/sfud.c b/components/drivers/spi/sfud/src/sfud.c index e3376555ca..6cfd1191ef 100644 --- a/components/drivers/spi/sfud/src/sfud.c +++ b/components/drivers/spi/sfud/src/sfud.c @@ -1,7 +1,7 @@ /* * This file is part of the Serial Flash Universal Driver Library. * - * Copyright (c) 2016, Armink, + * Copyright (c) 2016-2018, Armink, * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -46,6 +46,22 @@ static const sfud_mf mf_table[] = SFUD_MF_TABLE; static const sfud_flash_chip flash_chip_table[] = SFUD_FLASH_CHIP_TABLE; #endif +#ifdef SFUD_USING_QSPI +/** + * flash read data mode + */ +enum sfud_qspi_read_mode { + NORMAL_SPI_READ = 1 << 0, /**< mormal spi read mode */ + DUAL_OUTPUT = 1 << 1, /**< qspi fast read dual output */ + DUAL_IO = 1 << 2, /**< qspi fast read dual input/output */ + QUAD_OUTPUT = 1 << 3, /**< qspi fast read quad output */ + QUAD_IO = 1 << 4, /**< qspi fast read quad input/output */ +}; + +/* QSPI flash chip's extended information table */ +static const sfud_qspi_flash_ext_info qspi_flash_ext_info_table[] = SFUD_FLASH_EXT_INFO_TABLE; +#endif /* SFUD_USING_QSPI */ + static sfud_err software_init(const sfud_flash *flash); static sfud_err hardware_init(sfud_flash *flash); static sfud_err page256_or_1_byte_write(const sfud_flash *flash, uint32_t addr, size_t size, uint16_t write_gran, @@ -146,11 +162,89 @@ const sfud_flash *sfud_get_device_table(void) { return flash_table; } +#ifdef SFUD_USING_QSPI +static void qspi_set_read_cmd_format(sfud_flash *flash, uint8_t ins, uint8_t ins_lines, uint8_t addr_lines, + uint8_t dummy_cycles, uint8_t data_lines) { + /* if medium size greater than 16Mb, use 4-Byte address, instruction should be added one */ + if (flash->chip.capacity <= 0x1000000) { + flash->read_cmd_format.instruction = ins; + flash->read_cmd_format.address_size = 24; + } else { + flash->read_cmd_format.instruction = ins + 1; + flash->read_cmd_format.address_size = 32; + } + + flash->read_cmd_format.instruction_lines = ins_lines; + flash->read_cmd_format.address_lines = addr_lines; + flash->read_cmd_format.alternate_bytes_lines = 0; + flash->read_cmd_format.dummy_cycles = dummy_cycles; + flash->read_cmd_format.data_lines = data_lines; +} + +/** + * Enbale the fast read mode in QSPI flash mode. Default read mode is normal SPI mode. + * + * it will find the appropriate fast-read instruction to replace the read instruction(0x03) + * fast-read instruction @see SFUD_FLASH_EXT_INFO_TABLE + * + * @note When Flash is in QSPI mode, the method must be called after sfud_device_init(). + * + * @param flash flash device + * @param data_line_width the data lines max width which QSPI bus supported, such as 1, 2, 4 + * + * @return result + */ +sfud_err sfud_qspi_fast_read_enable(sfud_flash *flash, uint8_t data_line_width) { + size_t i = 0; + uint8_t read_mode = NORMAL_SPI_READ; + sfud_err result = SFUD_SUCCESS; + + SFUD_ASSERT(flash); + SFUD_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4); + + /* get read_mode, If don't found, the default is SFUD_QSPI_NORMAL_SPI_READ */ + for (i = 0; i < sizeof(qspi_flash_ext_info_table) / sizeof(sfud_qspi_flash_ext_info); i++) { + if ((qspi_flash_ext_info_table[i].mf_id == flash->chip.mf_id) + && (qspi_flash_ext_info_table[i].type_id == flash->chip.type_id) + && (qspi_flash_ext_info_table[i].capacity_id == flash->chip.capacity_id)) { + read_mode = qspi_flash_ext_info_table[i].read_mode; + } + } + + /* determine qspi supports which read mode and set read_cmd_format struct */ + switch (data_line_width) { + case 1: + qspi_set_read_cmd_format(flash, SFUD_CMD_READ_DATA, 1, 1, 0, 1); + break; + case 2: + if (read_mode & DUAL_IO) { + qspi_set_read_cmd_format(flash, SFUD_CMD_DUAL_IO_READ_DATA, 1, 2, 8, 2); + } else if (read_mode & DUAL_OUTPUT) { + qspi_set_read_cmd_format(flash, SFUD_CMD_DUAL_OUTPUT_READ_DATA, 1, 1, 8, 2); + } else { + qspi_set_read_cmd_format(flash, SFUD_CMD_READ_DATA, 1, 1, 0, 1); + } + break; + case 4: + if (read_mode & QUAD_IO) { + qspi_set_read_cmd_format(flash, SFUD_CMD_QUAD_IO_READ_DATA, 1, 4, 6, 4); + } else if (read_mode & QUAD_OUTPUT) { + qspi_set_read_cmd_format(flash, SFUD_CMD_QUAD_OUTPUT_READ_DATA, 1, 1, 8, 4); + } else { + qspi_set_read_cmd_format(flash, SFUD_CMD_READ_DATA, 1, 1, 0, 1); + } + break; + } + + return result; +} +#endif /* SFUD_USING_QSPI */ + /** * hardware initialize */ static sfud_err hardware_init(sfud_flash *flash) { - extern sfud_err sfud_spi_port_init(sfud_flash *flash); + extern sfud_err sfud_spi_port_init(sfud_flash * flash); sfud_err result = SFUD_SUCCESS; size_t i; @@ -162,6 +256,11 @@ static sfud_err hardware_init(sfud_flash *flash) { return result; } +#ifdef SFUD_USING_QSPI + /* set default read instruction */ + flash->read_cmd_format.instruction = SFUD_CMD_READ_DATA; +#endif /* SFUD_USING_QSPI */ + /* SPI write read function must be initialize */ SFUD_ASSERT(flash->spi.wr); /* if the user don't configure flash chip information then using SFDP parameter or static flash parameter table */ @@ -315,10 +414,17 @@ sfud_err sfud_read(const sfud_flash *flash, uint32_t addr, size_t size, uint8_t result = wait_busy(flash); if (result == SFUD_SUCCESS) { - cmd_data[0] = SFUD_CMD_READ_DATA; - make_adress_byte_array(flash, addr, &cmd_data[1]); - cmd_size = flash->addr_in_4_byte ? 5 : 4; - result = spi->wr(spi, cmd_data, cmd_size, data, size); +#ifdef SFUD_USING_QSPI + if (flash->read_cmd_format.instruction != SFUD_CMD_READ_DATA) { + result = spi->qspi_read(spi, addr, (sfud_qspi_read_cmd_format *)&flash->read_cmd_format, data, size); + } else +#endif + { + cmd_data[0] = SFUD_CMD_READ_DATA; + make_adress_byte_array(flash, addr, &cmd_data[1]); + cmd_size = flash->addr_in_4_byte ? 5 : 4; + result = spi->wr(spi, cmd_data, cmd_size, data, size); + } } /* unlock SPI */ if (spi->unlock) { @@ -328,7 +434,6 @@ sfud_err sfud_read(const sfud_flash *flash, uint32_t addr, size_t size, uint8_t return result; } - /** * erase all flash data * @@ -715,8 +820,16 @@ static sfud_err reset(const sfud_flash *flash) { SFUD_ASSERT(flash); cmd_data[0] = SFUD_CMD_ENABLE_RESET; + result = spi->wr(spi, cmd_data, 1, NULL, 0); + if (result == SFUD_SUCCESS) { + result = wait_busy(flash); + } else { + SFUD_INFO("Error: Flash device reset failed."); + return result; + } + cmd_data[1] = SFUD_CMD_RESET; - result = spi->wr(spi, cmd_data, 2, NULL, 0); + result = spi->wr(spi, &cmd_data[1], 1, NULL, 0); if (result == SFUD_SUCCESS) { result = wait_busy(flash); diff --git a/components/drivers/spi/spi_core.c b/components/drivers/spi/spi_core.c index 4ab843a9fd..64b0d2e496 100644 --- a/components/drivers/spi/spi_core.c +++ b/components/drivers/spi/spi_core.c @@ -1,21 +1,7 @@ /* - * File : spi_core.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -48,6 +34,8 @@ rt_err_t rt_spi_bus_register(struct rt_spi_bus *bus, bus->ops = ops; /* initialize owner */ bus->owner = RT_NULL; + /* set bus mode */ + bus->mode = RT_SPI_BUS_MODE_SPI; return RT_EOK; } @@ -360,7 +348,6 @@ struct rt_spi_message *rt_spi_transfer_message(struct rt_spi_device *device, { /* configure SPI bus failed */ rt_set_errno(-RT_EIO); - result = 0; goto __exit; } } diff --git a/components/drivers/spi/spi_dev.c b/components/drivers/spi/spi_dev.c index 1e69ebe591..e334e7aeb5 100644 --- a/components/drivers/spi/spi_dev.c +++ b/components/drivers/spi/spi_dev.c @@ -1,21 +1,7 @@ /* - * File : spi_dev.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash.h b/components/drivers/spi/spi_flash.h index d4beb57b45..30db32474a 100644 --- a/components/drivers/spi/spi_flash.h +++ b/components/drivers/spi/spi_flash.h @@ -1,21 +1,7 @@ /* - * File : spi_flash.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_at45dbxx.c b/components/drivers/spi/spi_flash_at45dbxx.c index 8798e35cf6..0a30f0a328 100644 --- a/components/drivers/spi/spi_flash_at45dbxx.c +++ b/components/drivers/spi/spi_flash_at45dbxx.c @@ -1,21 +1,7 @@ /* - * File : spi_flash_at45dbxx.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,7 +20,7 @@ #define FLASH_TRACE(...) #endif /**< #ifdef FLASH_DEBUG */ -/* JEDEC Manufacturers ID */ +/* JEDEC Manufacturer’s ID */ #define MF_ID (0x1F) /* atmel */ #define DENSITY_CODE_011D (0x02) /* AT45DB011D Density Code : 00010 = 1-Mbit */ #define DENSITY_CODE_021D (0x03) /* AT45DB021D Density Code : 00011 = 2-Mbit */ @@ -345,7 +331,7 @@ rt_err_t at45dbxx_init(const char * flash_device_name, const char * spi_device_n /**< 001 = Atmel DataFlash */ if(JEDEC_ID->manufacturer_id != 0x1F || JEDEC_ID->family_code != 0x01) { - FLASH_TRACE("Manufacturers ID or Memory Type error!\r\n"); + FLASH_TRACE("Manufacturer’s ID or Memory Type error!\r\n"); FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]); return -RT_ENOSYS; } diff --git a/components/drivers/spi/spi_flash_at45dbxx.h b/components/drivers/spi/spi_flash_at45dbxx.h index 203a1d3ba9..d1bc1a2aeb 100644 --- a/components/drivers/spi/spi_flash_at45dbxx.h +++ b/components/drivers/spi/spi_flash_at45dbxx.h @@ -1,21 +1,7 @@ /* - * File : spi_flash_at45dbxx.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_gd.c b/components/drivers/spi/spi_flash_gd.c index a8e8f9a4b8..3c52035372 100644 --- a/components/drivers/spi/spi_flash_gd.c +++ b/components/drivers/spi/spi_flash_gd.c @@ -1,22 +1,7 @@ /* - * File : spi_flash_gd.c - * This file is part of RT-Thread RTOS - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_gd.h b/components/drivers/spi/spi_flash_gd.h index 4a12100b74..904d976ed0 100644 --- a/components/drivers/spi/spi_flash_gd.h +++ b/components/drivers/spi/spi_flash_gd.h @@ -1,21 +1,7 @@ /* - * File : spi_flash_gd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_sfud.c b/components/drivers/spi/spi_flash_sfud.c index 9859cb0141..0f3cba0798 100644 --- a/components/drivers/spi/spi_flash_sfud.c +++ b/components/drivers/spi/spi_flash_sfud.c @@ -1,21 +1,7 @@ /* - * File : spi_flash_sfud.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -37,11 +23,21 @@ #ifndef RT_SFUD_DEFAULT_SPI_CFG /* read the JEDEC SFDP command must run at 50 MHz or less */ -#define RT_SFUD_DEFAULT_SPI_CFG \ -{ \ - .mode = RT_SPI_MODE_0 | RT_SPI_MSB, \ - .data_width = 8, \ - .max_hz = 50 * 1000 * 1000, \ +#define RT_SFUD_DEFAULT_SPI_CFG \ +{ \ + .mode = RT_SPI_MODE_0 | RT_SPI_MSB, \ + .data_width = 8, \ + .max_hz = 50 * 1000 * 1000, \ +} +#endif + +#ifdef SFUD_USING_QSPI +#define RT_SFUD_DEFAULT_QSPI_CFG \ +{ \ + RT_SFUD_DEFAULT_SPI_CFG, \ + .medium_size = 0x800000, \ + .ddr_mode = 0, \ + .qspi_dl_width = 4, \ } #endif @@ -130,31 +126,90 @@ static sfud_err spi_write_read(const sfud_spi *spi, const uint8_t *write_buf, si sfud_err result = SFUD_SUCCESS; sfud_flash *sfud_dev = (sfud_flash *) (spi->user_data); struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (sfud_dev->user_data); - +#ifdef SFUD_USING_QSPI + struct rt_qspi_device *qspi_dev = RT_NULL; +#endif if (write_size) { RT_ASSERT(write_buf); } if (read_size) { RT_ASSERT(read_buf); } - - if (write_size && read_size) { - if (rt_spi_send_then_recv(rtt_dev->rt_spi_device, write_buf, write_size, read_buf, read_size) != RT_EOK) { - result = SFUD_ERR_TIMEOUT; +#ifdef SFUD_USING_QSPI + if(rtt_dev->rt_spi_device->bus->mode & RT_SPI_BUS_MODE_QSPI) { + qspi_dev = (struct rt_qspi_device *) (rtt_dev->rt_spi_device); + if (write_size && read_size) { + if (rt_qspi_send_then_recv(qspi_dev, write_buf, write_size, read_buf, read_size) == 0) { + result = SFUD_ERR_TIMEOUT; + } + } else if (write_size) { + if (rt_qspi_send(qspi_dev, write_buf, write_size) == 0) { + result = SFUD_ERR_TIMEOUT; + } } - } else if (write_size) { - if (rt_spi_send(rtt_dev->rt_spi_device, write_buf, write_size) == 0) { - result = SFUD_ERR_TIMEOUT; - } - } else { - if (rt_spi_recv(rtt_dev->rt_spi_device, read_buf, read_size) == 0) { - result = SFUD_ERR_TIMEOUT; + } + else +#endif + { + if (write_size && read_size) { + if (rt_spi_send_then_recv(rtt_dev->rt_spi_device, write_buf, write_size, read_buf, read_size) != RT_EOK) { + result = SFUD_ERR_TIMEOUT; + } + } else if (write_size) { + if (rt_spi_send(rtt_dev->rt_spi_device, write_buf, write_size) == 0) { + result = SFUD_ERR_TIMEOUT; + } + } else { + if (rt_spi_recv(rtt_dev->rt_spi_device, read_buf, read_size) == 0) { + result = SFUD_ERR_TIMEOUT; + } } } return result; } +#ifdef SFUD_USING_QSPI +/** + * QSPI fast read data + */ +static sfud_err qspi_read(const struct __sfud_spi *spi, uint32_t addr, sfud_qspi_read_cmd_format *qspi_read_cmd_format, uint8_t *read_buf, size_t read_size) { + struct rt_qspi_message message; + sfud_err result = SFUD_SUCCESS; + + sfud_flash *sfud_dev = (sfud_flash *) (spi->user_data); + struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (sfud_dev->user_data); + struct rt_qspi_device *qspi_dev = (struct rt_qspi_device *) (rtt_dev->rt_spi_device); + + /* set message struct */ + message.instruction.content = qspi_read_cmd_format->instruction; + message.instruction.qspi_lines = qspi_read_cmd_format->instruction_lines; + + message.address.content = addr; + message.address.size = qspi_read_cmd_format->address_size; + message.address.qspi_lines = qspi_read_cmd_format->address_lines; + + message.alternate_bytes.content = 0; + message.alternate_bytes.size = 0; + message.alternate_bytes.qspi_lines = 0; + + message.dummy_cycles = qspi_read_cmd_format->dummy_cycles; + + message.parent.send_buf = RT_NULL; + message.parent.recv_buf = read_buf; + message.parent.length = read_size; + message.parent.cs_release = 1; + message.parent.cs_take = 1; + message.qspi_data_lines = qspi_read_cmd_format->data_lines; + + if (rt_qspi_transfer_message(qspi_dev, &message) != read_size) { + result = SFUD_ERR_TIMEOUT; + } + + return result; +} +#endif + static void spi_lock(const sfud_spi *spi) { sfud_flash *sfud_dev = (sfud_flash *) (spi->user_data); struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (sfud_dev->user_data); @@ -217,6 +272,9 @@ sfud_err sfud_spi_port_init(sfud_flash *flash) { /* port SPI device interface */ flash->spi.wr = spi_write_read; +#ifdef SFUD_USING_QSPI + flash->spi.qspi_read = qspi_read; +#endif flash->spi.lock = spi_lock; flash->spi.unlock = spi_unlock; flash->spi.user_data = flash; @@ -227,8 +285,7 @@ sfud_err sfud_spi_port_init(sfud_flash *flash) { flash->retry.delay = retry_delay_100us; /* 60 seconds timeout */ flash->retry.times = 60 * 10000; - - + return result; } @@ -260,6 +317,10 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const * @note you also can change the SPI to other configuration after initialized finish */ struct rt_spi_configuration cfg = RT_SFUD_DEFAULT_SPI_CFG; extern sfud_err sfud_device_init(sfud_flash *flash); +#ifdef SFUD_USING_QSPI + struct rt_qspi_configuration qspi_cfg = RT_SFUD_DEFAULT_QSPI_CFG; + struct rt_qspi_device *qspi_dev = RT_NULL; +#endif RT_ASSERT(spi_flash_dev_name); RT_ASSERT(spi_dev_name); @@ -291,7 +352,17 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const goto error; } sfud_dev->spi.name = spi_dev_name_bak; - rt_spi_configure(rtt_dev->rt_spi_device, &cfg); + +#ifdef SFUD_USING_QSPI + /* set the qspi line number and configure the QSPI bus */ + if(rtt_dev->rt_spi_device->bus->mode &RT_SPI_BUS_MODE_QSPI) { + qspi_dev = (struct rt_qspi_device *)rtt_dev->rt_spi_device; + qspi_cfg.qspi_dl_width = qspi_dev->config.qspi_dl_width; + rt_qspi_configure(qspi_dev, &qspi_cfg); + } + else +#endif + rt_spi_configure(rtt_dev->rt_spi_device, &cfg); } /* SFUD flash device initialize */ { @@ -310,6 +381,17 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const rtt_dev->geometry.sector_count = sfud_dev->chip.capacity / sfud_dev->chip.erase_gran; rtt_dev->geometry.bytes_per_sector = sfud_dev->chip.erase_gran; rtt_dev->geometry.block_size = sfud_dev->chip.erase_gran; +#ifdef SFUD_USING_QSPI + /* reconfigure the QSPI bus for medium size */ + if(rtt_dev->rt_spi_device->bus->mode &RT_SPI_BUS_MODE_QSPI) { + qspi_cfg.medium_size = sfud_dev->chip.capacity; + rt_qspi_configure(qspi_dev, &qspi_cfg); + if(qspi_dev->enter_qspi_mode != RT_NULL) + qspi_dev->enter_qspi_mode(qspi_dev); + } + /* set data lines width */ + sfud_qspi_fast_read_enable(sfud_dev, qspi_dev->config.qspi_dl_width); +#endif /* SFUD_USING_QSPI */ } /* register device */ @@ -416,14 +498,17 @@ static void sf(uint8_t argc, char **argv) { } else { char *spi_dev_name = argv[2]; rtt_dev_bak = rtt_dev; + + /* delete the old SPI flash device */ + if(rtt_dev_bak) { + rt_sfud_flash_delete(rtt_dev_bak); + } + rtt_dev = rt_sfud_flash_probe("sf_cmd", spi_dev_name); if (!rtt_dev) { return; } - /* already probe then delete the old SPI flash device */ - if(rtt_dev_bak) { - rt_sfud_flash_delete(rtt_dev_bak); - } + sfud_dev = (sfud_flash_t)rtt_dev->user_data; if (sfud_dev->chip.capacity < 1024 * 1024) { rt_kprintf("%d KB %s is current selected device.\n", sfud_dev->chip.capacity / 1024, sfud_dev->name); diff --git a/components/drivers/spi/spi_flash_sfud.h b/components/drivers/spi/spi_flash_sfud.h index 2c7f8e7f54..3173b9786d 100644 --- a/components/drivers/spi/spi_flash_sfud.h +++ b/components/drivers/spi/spi_flash_sfud.h @@ -1,21 +1,7 @@ /* - * File : spi_flash_sfud.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_sst25vfxx.c b/components/drivers/spi/spi_flash_sst25vfxx.c index 35dcf3fff7..bd618a8e9b 100644 --- a/components/drivers/spi/spi_flash_sst25vfxx.c +++ b/components/drivers/spi/spi_flash_sst25vfxx.c @@ -1,21 +1,7 @@ /* - * File : spi_flash_sst25vfxx.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,7 +19,7 @@ #define FLASH_TRACE(...) #endif /* #ifdef FLASH_DEBUG */ -/* JEDEC Manufacturers ID */ +/* JEDEC Manufacturer’s ID */ #define MF_ID (0xBF) /* JEDEC Device ID : Memory Type */ #define MT_ID (0x25) @@ -302,7 +288,7 @@ rt_err_t sst25vfxx_init(const char * flash_device_name, const char * spi_device_ if(id_recv[0] != MF_ID || id_recv[1] != MT_ID) { - FLASH_TRACE("Manufacturers ID or Memory Type error!\r\n"); + FLASH_TRACE("Manufacturer’s ID or Memory Type error!\r\n"); FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]); return -RT_ENOSYS; } diff --git a/components/drivers/spi/spi_flash_sst25vfxx.h b/components/drivers/spi/spi_flash_sst25vfxx.h index 2502188b91..7a7283f753 100644 --- a/components/drivers/spi/spi_flash_sst25vfxx.h +++ b/components/drivers/spi/spi_flash_sst25vfxx.h @@ -1,21 +1,7 @@ /* - * File : spi_flash_sst25vxx.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_w25qxx.c b/components/drivers/spi/spi_flash_w25qxx.c index 5a16ffbae2..bba9c0b5cc 100644 --- a/components/drivers/spi/spi_flash_w25qxx.c +++ b/components/drivers/spi/spi_flash_w25qxx.c @@ -1,21 +1,7 @@ /* - * File : spi_flash_w25qxx.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -41,7 +27,7 @@ #define PAGE_SIZE 4096 -/* JEDEC Manufacturer��s ID */ +/* JEDEC Manufacturer ID */ #define MF_ID (0xEF) /* JEDEC Device ID: Memory type and Capacity */ diff --git a/components/drivers/spi/spi_flash_w25qxx.h b/components/drivers/spi/spi_flash_w25qxx.h index 737ca70ed2..14837bc87c 100644 --- a/components/drivers/spi/spi_flash_w25qxx.h +++ b/components/drivers/spi/spi_flash_w25qxx.h @@ -1,21 +1,7 @@ /* - * File : spi_flash_w25qxx.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_flash_w25qxx_mtd.c b/components/drivers/spi/spi_flash_w25qxx_mtd.c index dd3e59f409..9f1ef802f6 100644 --- a/components/drivers/spi/spi_flash_w25qxx_mtd.c +++ b/components/drivers/spi/spi_flash_w25qxx_mtd.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include @@ -17,7 +25,7 @@ #define FLASH_TRACE(...) #endif /* #ifdef FLASH_DEBUG */ -/* JEDEC Manufacturers ID */ +/* JEDEC Manufacturer’s ID */ #define MF_ID (0xEF) /* JEDEC Device ID: Memory type and Capacity */ #define MTC_W25Q80_BV (0x4014) /* W25Q80BV */ diff --git a/components/drivers/spi/spi_flash_w25qxx_mtd.h b/components/drivers/spi/spi_flash_w25qxx_mtd.h index 9157524673..28f6828ffb 100644 --- a/components/drivers/spi/spi_flash_w25qxx_mtd.h +++ b/components/drivers/spi/spi_flash_w25qxx_mtd.h @@ -1,21 +1,7 @@ /* - * File : spi_flash_w25qxx.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_msd.c b/components/drivers/spi/spi_msd.c index a3046e14ba..a109fd9488 100644 --- a/components/drivers/spi/spi_msd.c +++ b/components/drivers/spi/spi_msd.c @@ -1,12 +1,7 @@ /* - * File : msd.c - * SPI mode SD Card Driver - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -42,8 +37,6 @@ static struct msd_device _msd_device; static rt_bool_t rt_tick_timeout(rt_tick_t tick_start, rt_tick_t tick_long); static rt_err_t MSD_take_owner(struct rt_spi_device *spi_device); -static void MSD_take_cs(struct rt_spi_device *device); -static void MSD_release_cs(struct rt_spi_device *device); static rt_err_t _wait_token(struct rt_spi_device *device, uint8_t token); static rt_err_t _wait_ready(struct rt_spi_device *device); @@ -78,36 +71,6 @@ static rt_err_t MSD_take_owner(struct rt_spi_device *spi_device) return result; } -static void MSD_take_cs(struct rt_spi_device *device) -{ - struct rt_spi_message message; - - /* initial message */ - message.send_buf = RT_NULL; - message.recv_buf = RT_NULL; - message.length = 0; - message.cs_take = 1; - message.cs_release = 0; - - /* transfer message */ - device->bus->ops->xfer(device, &message); -} - -static void MSD_release_cs(struct rt_spi_device *device) -{ - struct rt_spi_message message; - - /* initial message */ - message.send_buf = RT_NULL; - message.recv_buf = RT_NULL; - message.length = 0; - message.cs_take = 0; - message.cs_release = 1; - - /* transfer message */ - device->bus->ops->xfer(device, &message); -} - static rt_bool_t rt_tick_timeout(rt_tick_t tick_start, rt_tick_t tick_long) { rt_tick_t tick_end = tick_start + tick_long; @@ -522,7 +485,7 @@ static rt_err_t rt_msd_init(rt_device_t dev) goto _exit; } - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); /* The host shall supply power to the card so that the voltage is reached to Vdd_min within 250ms and start to supply at least 74 SD clocks to the SD card with keeping CMD line to high. @@ -547,9 +510,9 @@ static rt_err_t rt_msd_init(rt_device_t dev) while (1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, GO_IDLE_STATE, 0x00, 0x95, response_r1, response); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if ((result == RT_EOK) && (response[0] == MSD_IN_IDLE_STATE)) { @@ -573,9 +536,9 @@ static rt_err_t rt_msd_init(rt_device_t dev) do { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, SEND_IF_COND, 0x01AA, 0x87, response_r7, response); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if (result == RT_EOK) { @@ -627,23 +590,23 @@ static rt_err_t rt_msd_init(rt_device_t dev) /* try SD Ver1.x */ while (1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_OCR, 0x00, 0x00, response_r3, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[info] It maybe SD1.x or MMC But it is Not response to CMD58!\r\n"); goto _exit; } if (0 != (response[0] & 0xFE)) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[info] It look CMD58 as illegal command so it is not SD card!\r\n"); break; } - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); OCR = response[1]; OCR = (OCR << 8) + response[2]; @@ -666,24 +629,24 @@ static rt_err_t rt_msd_init(rt_device_t dev) { if (rt_tick_timeout(tick_start, rt_tick_from_millisecond(CARD_TRY_TIMES_ACMD41))) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[info] try CMD55 + ACMD41 timeout! mabey MMC card!\r\n"); break; } - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); /* CMD55 APP_CMD */ result = _send_cmd(msd->spi_device, APP_CMD, 0x00, 0x00, response_r1, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); continue; } if (0 != (response[0] & 0xFE)) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[info] Not SD card2 , may be MMC\r\n"); break; } @@ -692,20 +655,20 @@ static rt_err_t rt_msd_init(rt_device_t dev) result = _send_cmd(msd->spi_device, SD_SEND_OP_COND, 0x00, 0x00, response_r1, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); continue; } if (0 != (response[0] & 0xFE)) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[info] Not SD card4 , may be MMC\r\n"); break; } if (0 == (response[0] & 0xFF)) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); is_sd_v1_x = RT_TRUE; MSD_DEBUG("[info] It is Ver1.X SD Memory Card!!!\r\n"); break; @@ -721,7 +684,7 @@ static rt_err_t rt_msd_init(rt_device_t dev) uint32_t i; MSD_DEBUG("[info] try MMC card!\r\n"); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); /* send dummy clock */ { @@ -745,9 +708,9 @@ static rt_err_t rt_msd_init(rt_device_t dev) tick_start = rt_tick_get(); while (1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, GO_IDLE_STATE, 0x00, 0x95, response_r1, response); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if ((result == RT_EOK) && (response[0] == MSD_IN_IDLE_STATE)) { @@ -766,9 +729,9 @@ static rt_err_t rt_msd_init(rt_device_t dev) tick_start = rt_tick_get(); while (1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, SEND_OP_COND, 0x00, 0x00, response_r1, response); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if ((result == RT_EOK) && (response[0] == MSD_RESPONSE_NO_ERROR)) { @@ -788,25 +751,25 @@ static rt_err_t rt_msd_init(rt_device_t dev) } else if (msd->card_type == MSD_CARD_TYPE_SD_V2_X) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_OCR, 0x00, 0x00, response_r3, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] It maybe SD2.0 But it is Not response to CMD58!\r\n"); goto _exit; } if ((response[0] & 0xFE) != 0) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] It look CMD58 as illegal command so it is not SD card!\r\n"); result = RT_ERROR; goto _exit; } - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); OCR = response[1]; OCR = (OCR << 8) + response[2]; @@ -827,10 +790,10 @@ static rt_err_t rt_msd_init(rt_device_t dev) /* try CMD55 + ACMD41 */ do { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); if (rt_tick_timeout(tick_start, rt_tick_from_millisecond(CARD_TRY_TIMES_ACMD41))) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] SD Ver2.x or later try CMD55 + ACMD41 timeout!\r\n"); result = RT_ERROR; goto _exit; @@ -841,13 +804,13 @@ static rt_err_t rt_msd_init(rt_device_t dev) // if((result != RT_EOK) || (response[0] == 0x01)) if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); continue; } if ((response[0] & 0xFE) != 0) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] Not SD ready!\r\n"); result = RT_ERROR; goto _exit; @@ -857,7 +820,7 @@ static rt_err_t rt_msd_init(rt_device_t dev) result = _send_cmd(msd->spi_device, SD_SEND_OP_COND, 0x40000000, 0x77, response_r1, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] ACMD41 fail!\r\n"); result = RT_ERROR; goto _exit; @@ -865,33 +828,33 @@ static rt_err_t rt_msd_init(rt_device_t dev) if ((response[0] & 0xFE) != 0) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[info] Not SD card4 , response : 0x%02X\r\n", response[0]); // break; } } while (response[0] != MSD_RESPONSE_NO_ERROR); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); /* try CMD55 + ACMD41 */ /* --Read OCR again */ - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_OCR, 0x00, 0x00, response_r3, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] It maybe SD2.0 But it is Not response to 2nd CMD58!\r\n"); goto _exit; } if ((response[0] & 0xFE) != 0) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] It look 2nd CMD58 as illegal command so it is not SD card!\r\n"); result = RT_ERROR; goto _exit; } - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); OCR = response[1]; OCR = (OCR << 8) + response[2]; @@ -938,14 +901,14 @@ static rt_err_t rt_msd_init(rt_device_t dev) /* set CRC */ { - MSD_release_cs(msd->spi_device); - MSD_take_cs(msd->spi_device); + rt_spi_release(msd->spi_device); + rt_spi_take(msd->spi_device); #ifdef MSD_USE_CRC result = _send_cmd(msd->spi_device, CRC_ON_OFF, 0x01, 0x83, response_r1, response); #else result = _send_cmd(msd->spi_device, CRC_ON_OFF, 0x00, 0x91, response_r1, response); #endif - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) { MSD_DEBUG("[err] CMD59 CRC_ON_OFF fail! response : 0x%02X\r\n", response[0]); @@ -956,10 +919,10 @@ static rt_err_t rt_msd_init(rt_device_t dev) /* CMD16 SET_BLOCKLEN */ { - MSD_release_cs(msd->spi_device); - MSD_take_cs(msd->spi_device); + rt_spi_release(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, SET_BLOCKLEN, SECTOR_SIZE, 0x00, response_r1, response); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) { MSD_DEBUG("[err] CMD16 SET_BLOCKLEN fail! response : 0x%02X\r\n", response[0]); @@ -974,27 +937,27 @@ static rt_err_t rt_msd_init(rt_device_t dev) { uint8_t CSD_buffer[MSD_CSD_LEN]; - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); // result = _send_cmd(msd->spi_device, SEND_CSD, 0x00, 0xAF, response_r1, response); result = _send_cmd(msd->spi_device, SEND_CSD, 0x00, 0x00, response_r1, response); if (result != RT_EOK) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] CMD9 SEND_CSD timeout!\r\n"); goto _exit; } if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) { - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); MSD_DEBUG("[err] CMD9 SEND_CSD fail! response : 0x%02X\r\n", response[0]); result = RT_ERROR; goto _exit; } result = _read_block(msd->spi_device, CSD_buffer, MSD_CSD_LEN); - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); if (result != RT_EOK) { MSD_DEBUG("[err] read CSD fail!\r\n"); @@ -1219,12 +1182,11 @@ static rt_err_t rt_msd_init(rt_device_t dev) cfg.data_width = 8; cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */ cfg.max_hz = msd->max_clock; - rt_spi_configure(msd->spi_device, &cfg); } /* config spi */ _exit: - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); rt_mutex_release(&(msd->spi_device->bus->lock)); return result; } @@ -1254,20 +1216,10 @@ static rt_size_t rt_msd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_siz goto _exit; } - /* config spi to high speed */ - { - struct rt_spi_configuration cfg; - cfg.data_width = 8; - cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */ - cfg.max_hz = msd->max_clock; - - rt_spi_configure(msd->spi_device, &cfg); - } /* config spi */ - /* SINGLE_BLOCK? */ if (size == 1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_SINGLE_BLOCK, pos * msd->geometry.bytes_per_sector, 0x00, response_r1, response); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) @@ -1288,7 +1240,7 @@ static rt_size_t rt_msd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_siz { uint32_t i; - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_MULTIPLE_BLOCK, pos * msd->geometry.bytes_per_sector, 0x00, response_r1, response); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) @@ -1321,7 +1273,7 @@ static rt_size_t rt_msd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_siz _exit: /* release and exit */ - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); rt_mutex_release(&(msd->spi_device->bus->lock)); return size; @@ -1340,20 +1292,10 @@ static rt_size_t rt_msd_sdhc_read(rt_device_t dev, rt_off_t pos, void *buffer, r goto _exit; } - /* config spi to high speed */ - { - struct rt_spi_configuration cfg; - cfg.data_width = 8; - cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */ - cfg.max_hz = msd->max_clock; - - rt_spi_configure(msd->spi_device, &cfg); - } /* config spi */ - /* SINGLE_BLOCK? */ if (size == 1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_SINGLE_BLOCK, pos, 0x00, response_r1, response); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) @@ -1374,7 +1316,7 @@ static rt_size_t rt_msd_sdhc_read(rt_device_t dev, rt_off_t pos, void *buffer, r { uint32_t i; - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, READ_MULTIPLE_BLOCK, pos, 0x00, response_r1, response); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) @@ -1407,7 +1349,7 @@ static rt_size_t rt_msd_sdhc_read(rt_device_t dev, rt_off_t pos, void *buffer, r _exit: /* release and exit */ - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); rt_mutex_release(&(msd->spi_device->bus->lock)); return size; @@ -1427,20 +1369,11 @@ static rt_size_t rt_msd_write(rt_device_t dev, rt_off_t pos, const void *buffer, goto _exit; } - /* config spi to high speed */ - { - struct rt_spi_configuration cfg; - cfg.data_width = 8; - cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */ - cfg.max_hz = msd->max_clock; - - rt_spi_configure(msd->spi_device, &cfg); - } /* config spi */ /* SINGLE_BLOCK? */ if (size == 1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, WRITE_BLOCK, pos * msd->geometry.bytes_per_sector, 0x00, response_r1, response); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) { @@ -1461,7 +1394,7 @@ static rt_size_t rt_msd_write(rt_device_t dev, rt_off_t pos, const void *buffer, struct rt_spi_message message; uint32_t i; - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); #ifdef MSD_USE_PRE_ERASED if (msd->card_type != MSD_CARD_TYPE_MMC) @@ -1536,7 +1469,7 @@ static rt_size_t rt_msd_write(rt_device_t dev, rt_off_t pos, const void *buffer, _exit: /* release and exit */ - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); rt_mutex_release(&(msd->spi_device->bus->lock)); return size; @@ -1555,20 +1488,10 @@ static rt_size_t rt_msd_sdhc_write(rt_device_t dev, rt_off_t pos, const void *bu goto _exit; } - /* config spi to high speed */ - { - struct rt_spi_configuration cfg; - cfg.data_width = 8; - cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */ - cfg.max_hz = msd->max_clock; - - rt_spi_configure(msd->spi_device, &cfg); - } /* config spi */ - /* SINGLE_BLOCK? */ if (size == 1) { - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); result = _send_cmd(msd->spi_device, WRITE_BLOCK, pos, 0x00, response_r1, response); if ((result != RT_EOK) || (response[0] != MSD_RESPONSE_NO_ERROR)) { @@ -1589,7 +1512,7 @@ static rt_size_t rt_msd_sdhc_write(rt_device_t dev, rt_off_t pos, const void *bu struct rt_spi_message message; uint32_t i; - MSD_take_cs(msd->spi_device); + rt_spi_take(msd->spi_device); #ifdef MSD_USE_PRE_ERASED /* CMD55 APP_CMD */ @@ -1660,7 +1583,7 @@ static rt_size_t rt_msd_sdhc_write(rt_device_t dev, rt_off_t pos, const void *bu _exit: /* release and exit */ - MSD_release_cs(msd->spi_device); + rt_spi_release(msd->spi_device); rt_mutex_release(&(msd->spi_device->bus->lock)); return size; diff --git a/components/drivers/spi/spi_msd.h b/components/drivers/spi/spi_msd.h index 98722711d3..6370170923 100644 --- a/components/drivers/spi/spi_msd.h +++ b/components/drivers/spi/spi_msd.h @@ -1,12 +1,7 @@ /* - * File : msd.h - * SPI mode SD Card Driver - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_wifi_rw009.c b/components/drivers/spi/spi_wifi_rw009.c index 0b92802383..4ddd18ca12 100644 --- a/components/drivers/spi/spi_wifi_rw009.c +++ b/components/drivers/spi/spi_wifi_rw009.c @@ -1,21 +1,7 @@ /* - * File : spi_wifi_rw009.c - * This file is part of RT-Thread RTOS - * Copyright by Shanghai Real-Thread Electronic Technology Co.,Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/spi/spi_wifi_rw009.h b/components/drivers/spi/spi_wifi_rw009.h index 4b684b9b24..049b0a8486 100644 --- a/components/drivers/spi/spi_wifi_rw009.h +++ b/components/drivers/spi/spi_wifi_rw009.h @@ -1,21 +1,7 @@ /* - * File : spi_wifi_rw009.h - * This file is part of RT-Thread RTOS - * Copyright by Shanghai Real-Thread Electronic Technology Co.,Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/src/completion.c b/components/drivers/src/completion.c index ef0b2911a7..9e461e49ce 100644 --- a/components/drivers/src/completion.c +++ b/components/drivers/src/completion.c @@ -1,21 +1,7 @@ /* - * File : completion.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/src/dataqueue.c b/components/drivers/src/dataqueue.c index a10b0805b4..7553986b9f 100644 --- a/components/drivers/src/dataqueue.c +++ b/components/drivers/src/dataqueue.c @@ -1,21 +1,7 @@ /* - * File : dataqueue.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/src/pipe.c b/components/drivers/src/pipe.c index 80d74657e0..065fd21dc1 100644 --- a/components/drivers/src/pipe.c +++ b/components/drivers/src/pipe.c @@ -1,21 +1,7 @@ /* - * File : pipe.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012-2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/src/ringblk_buf.c b/components/drivers/src/ringblk_buf.c new file mode 100644 index 0000000000..74ced674fe --- /dev/null +++ b/components/drivers/src/ringblk_buf.c @@ -0,0 +1,554 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-25 armink the first version + */ + +#include +#include +#include + +/** + * ring block buffer object initialization + * + * @param rbb ring block buffer object + * @param buf buffer + * @param buf_size buffer size + * @param block_set block set + * @param blk_max_num max block number + * + * @note When your application need align access, please make the buffer address is aligned. + */ +void rt_rbb_init(rt_rbb_t rbb, rt_uint8_t *buf, rt_size_t buf_size, rt_rbb_blk_t block_set, rt_size_t blk_max_num) +{ + rt_size_t i; + + RT_ASSERT(rbb); + RT_ASSERT(buf); + RT_ASSERT(block_set); + + rbb->buf = buf; + rbb->buf_size = buf_size; + rbb->blk_set = block_set; + rbb->blk_max_num = blk_max_num; + rt_slist_init(&rbb->blk_list); + /* initialize block status */ + for (i = 0; i < blk_max_num; i++) + { + block_set[i].status = RT_RBB_BLK_UNUSED; + } +} +RTM_EXPORT(rt_rbb_init); + +/** + * ring block buffer object create + * + * @param buf_size buffer size + * @param blk_max_num max block number + * + * @return != NULL: ring block buffer object + * NULL: create failed + */ +rt_rbb_t rt_rbb_create(rt_size_t buf_size, rt_size_t blk_max_num) +{ + rt_rbb_t rbb = NULL; + rt_uint8_t *buf; + rt_rbb_blk_t blk_set; + + rbb = (rt_rbb_t)rt_malloc(sizeof(struct rt_rbb)); + if (!rbb) + { + return NULL; + } + + buf = (rt_uint8_t *)rt_malloc(buf_size); + if (!buf) + { + rt_free(rbb); + return NULL; + } + + blk_set = (rt_rbb_blk_t)rt_malloc(sizeof(struct rt_rbb_blk) * blk_max_num); + if (!blk_set) + { + rt_free(buf); + rt_free(rbb); + return NULL; + } + + rt_rbb_init(rbb, buf, buf_size, blk_set, blk_max_num); + + return rbb; +} +RTM_EXPORT(rt_rbb_create); + +/** + * ring block buffer object destroy + * + * @param rbb ring block buffer object + */ +void rt_rbb_destroy(rt_rbb_t rbb) +{ + RT_ASSERT(rbb); + + rt_free(rbb); + rt_free(rbb->buf); + rt_free(rbb->blk_set); + +} +RTM_EXPORT(rt_rbb_destroy); + +static rt_rbb_blk_t find_empty_blk_in_set(rt_rbb_t rbb) +{ + rt_size_t i; + + RT_ASSERT(rbb); + + for (i = 0; i < rbb->blk_max_num; i ++) + { + if (rbb->blk_set[i].status == RT_RBB_BLK_UNUSED) + { + return &rbb->blk_set[i]; + } + } + + return NULL; +} + +/** + * Allocate a block by given size. The block will add to blk_list when allocate success. + * + * @param rbb ring block buffer object + * @param blk_size block size + * + * @note When your application need align access, please make the blk_szie is aligned. + * + * @return != NULL: allocated block + * NULL: allocate failed + */ +rt_rbb_blk_t rt_rbb_blk_alloc(rt_rbb_t rbb, rt_size_t blk_size) +{ + rt_base_t level; + rt_size_t empty1 = 0, empty2 = 0; + rt_rbb_blk_t head, tail, new = NULL; + + RT_ASSERT(rbb); + RT_ASSERT(blk_size < (1L << 24)); + + level = rt_hw_interrupt_disable(); + + new = find_empty_blk_in_set(rbb); + + if (rt_slist_len(&rbb->blk_list) < rbb->blk_max_num && new) + { + if (rt_slist_len(&rbb->blk_list) > 0) + { + head = rt_slist_first_entry(&rbb->blk_list, struct rt_rbb_blk, list); + tail = rt_slist_tail_entry(&rbb->blk_list, struct rt_rbb_blk, list); + if (head->buf <= tail->buf) + { + /** + * head tail + * +--------------------------------------+-----------------+------------------+ + * | empty2 | block1 | block2 | block3 | empty1 | + * +--------------------------------------+-----------------+------------------+ + * rbb->buf + */ + empty1 = (rbb->buf + rbb->buf_size) - (tail->buf + tail->size); + empty2 = head->buf - rbb->buf; + + if (empty1 >= blk_size) + { + rt_slist_append(&rbb->blk_list, &new->list); + new->status = RT_RBB_BLK_INITED; + new->buf = tail->buf + tail->size; + new->size = blk_size; + } + else if (empty2 >= blk_size) + { + rt_slist_append(&rbb->blk_list, &new->list); + new->status = RT_RBB_BLK_INITED; + new->buf = rbb->buf; + new->size = blk_size; + } + else + { + /* no space */ + new = NULL; + } + } + else + { + /** + * tail head + * +----------------+-------------------------------------+--------+-----------+ + * | block3 | empty1 | block1 | block2 | + * +----------------+-------------------------------------+--------+-----------+ + * rbb->buf + */ + empty1 = head->buf - (tail->buf + tail->size); + + if (empty1 >= blk_size) + { + rt_slist_append(&rbb->blk_list, &new->list); + new->status = RT_RBB_BLK_INITED; + new->buf = tail->buf + tail->size; + new->size = blk_size; + } + else + { + /* no space */ + new = NULL; + } + } + } + else + { + /* the list is empty */ + rt_slist_append(&rbb->blk_list, &new->list); + new->status = RT_RBB_BLK_INITED; + new->buf = rbb->buf; + new->size = blk_size; + } + } + else + { + new = NULL; + } + + rt_hw_interrupt_enable(level); + + return new; +} +RTM_EXPORT(rt_rbb_blk_alloc); + +/** + * put a block to ring block buffer object + * + * @param block the block + */ +void rt_rbb_blk_put(rt_rbb_blk_t block) +{ + RT_ASSERT(block); + RT_ASSERT(block->status == RT_RBB_BLK_INITED); + + block->status = RT_RBB_BLK_PUT; +} +RTM_EXPORT(rt_rbb_blk_put); + +/** + * get a block from the ring block buffer object + * + * @param rbb ring block buffer object + * + * @return != NULL: block + * NULL: get failed + */ +rt_rbb_blk_t rt_rbb_blk_get(rt_rbb_t rbb) +{ + rt_base_t level; + rt_rbb_blk_t block = NULL; + rt_slist_t *node; + + RT_ASSERT(rbb); + + if (rt_slist_isempty(&rbb->blk_list)) + return 0; + + level = rt_hw_interrupt_disable(); + + for (node = rt_slist_first(&rbb->blk_list); node; node = rt_slist_next(node)) + { + block = rt_slist_entry(node, struct rt_rbb_blk, list); + if (block->status == RT_RBB_BLK_PUT) + { + block->status = RT_RBB_BLK_GET; + goto __exit; + } + } + /* not found */ + block = NULL; + +__exit: + + rt_hw_interrupt_enable(level); + + return block; +} +RTM_EXPORT(rt_rbb_blk_get); + +/** + * return the block size + * + * @param block the block + * + * @return block size + */ +rt_size_t rt_rbb_blk_size(rt_rbb_blk_t block) +{ + RT_ASSERT(block); + + return block->size; +} +RTM_EXPORT(rt_rbb_blk_size); + +/** + * return the block buffer + * + * @param block the block + * + * @return block buffer + */ +rt_uint8_t *rt_rbb_blk_buf(rt_rbb_blk_t block) +{ + RT_ASSERT(block); + + return block->buf; +} +RTM_EXPORT(rt_rbb_blk_buf); + +/** + * free the block + * + * @param rbb ring block buffer object + * @param block the block + */ +void rt_rbb_blk_free(rt_rbb_t rbb, rt_rbb_blk_t block) +{ + rt_base_t level; + + RT_ASSERT(rbb); + RT_ASSERT(block); + RT_ASSERT(block->status != RT_RBB_BLK_UNUSED); + + level = rt_hw_interrupt_disable(); + + /* remove it on rbb block list */ + rt_slist_remove(&rbb->blk_list, &block->list); + + block->status = RT_RBB_BLK_UNUSED; + + rt_hw_interrupt_enable(level); +} +RTM_EXPORT(rt_rbb_blk_free); + +/** + * get a continuous block to queue by given size + * + * tail head + * +------------------+---------------+--------+----------+--------+ + * | block3 | empty1 | block1 | block2 |fragment| + * +------------------+------------------------+----------+--------+ + * |<-- return_size -->| | + * |<--- queue_data_len --->| + * + * tail head + * +------------------+---------------+--------+----------+--------+ + * | block3 | empty1 | block1 | block2 |fragment| + * +------------------+------------------------+----------+--------+ + * |<-- return_size -->| out of len(b1+b2+b3) | + * |<-------------------- queue_data_len -------------------->| + * + * @param rbb ring block buffer object + * @param queue_data_len The max queue data size, and the return size must less then it. + * @param queue continuous block queue + * + * @return the block queue data total size + */ +rt_size_t rt_rbb_blk_queue_get(rt_rbb_t rbb, rt_size_t queue_data_len, rt_rbb_blk_queue_t blk_queue) +{ + rt_base_t level; + rt_size_t data_total_size = 0; + rt_slist_t *node; + rt_rbb_blk_t last_block = NULL, block; + + RT_ASSERT(rbb); + RT_ASSERT(blk_queue); + + if (rt_slist_isempty(&rbb->blk_list)) + return 0; + + level = rt_hw_interrupt_disable(); + + for (node = rt_slist_first(&rbb->blk_list); node; node = rt_slist_next(node)) + { + if (!last_block) + { + last_block = rt_slist_entry(node, struct rt_rbb_blk, list); + if (last_block->status == RT_RBB_BLK_PUT) + { + /* save the first put status block to queue */ + blk_queue->blocks = last_block; + blk_queue->blk_num = 0; + } + else + { + /* the first block must be put status */ + last_block = NULL; + continue; + } + } + else + { + block = rt_slist_entry(node, struct rt_rbb_blk, list); + /* + * these following conditions will break the loop: + * 1. the current block is not put status + * 2. the last block and current block is not continuous + * 3. the data_total_size will out of range + */ + if (block->status != RT_RBB_BLK_PUT || + last_block->buf > block->buf || + data_total_size + block->size > queue_data_len) + { + break; + } + /* backup last block */ + last_block = block; + } + /* remove current block */ + rt_slist_remove(&rbb->blk_list, &last_block->list); + data_total_size += last_block->size; + last_block->status = RT_RBB_BLK_GET; + blk_queue->blk_num++; + } + + rt_hw_interrupt_enable(level); + + return data_total_size; +} +RTM_EXPORT(rt_rbb_blk_queue_get); + +/** + * get all block length on block queue + * + * @param blk_queue the block queue + * + * @return total length + */ +rt_size_t rt_rbb_blk_queue_len(rt_rbb_blk_queue_t blk_queue) +{ + rt_size_t i, data_total_size = 0; + + RT_ASSERT(blk_queue); + + for (i = 0; i < blk_queue->blk_num; i++) + { + data_total_size += blk_queue->blocks[i].size; + } + + return data_total_size; +} +RTM_EXPORT(rt_rbb_blk_queue_len); + +/** + * return the block queue buffer + * + * @param blk_queue the block queue + * + * @return block queue buffer + */ +rt_uint8_t *rt_rbb_blk_queue_buf(rt_rbb_blk_queue_t blk_queue) +{ + RT_ASSERT(blk_queue); + + return blk_queue->blocks[0].buf; +} +RTM_EXPORT(rt_rbb_blk_queue_buf); + +/** + * free the block queue + * + * @param rbb ring block buffer object + * @param blk_queue the block queue + */ +void rt_rbb_blk_queue_free(rt_rbb_t rbb, rt_rbb_blk_queue_t blk_queue) +{ + rt_size_t i; + + RT_ASSERT(rbb); + RT_ASSERT(blk_queue); + + for (i = 0; i < blk_queue->blk_num; i++) + { + rt_rbb_blk_free(rbb, &blk_queue->blocks[i]); + } +} +RTM_EXPORT(rt_rbb_blk_queue_free); + +/** + * The put status and buffer continuous blocks can be make a block queue. + * This function will return the length which from next can be make block queue. + * + * @param rbb ring block buffer object + * + * @return the next can be make block queue's length + */ +rt_size_t rt_rbb_next_blk_queue_len(rt_rbb_t rbb) +{ + rt_base_t level; + rt_size_t data_len = 0; + rt_slist_t *node; + rt_rbb_blk_t last_block = NULL, block; + + RT_ASSERT(rbb); + + if (rt_slist_isempty(&rbb->blk_list)) + return 0; + + level = rt_hw_interrupt_disable(); + + for (node = rt_slist_first(&rbb->blk_list); node; node = rt_slist_next(node)) + { + if (!last_block) + { + last_block = rt_slist_entry(node, struct rt_rbb_blk, list); + if (last_block->status != RT_RBB_BLK_PUT) + { + /* the first block must be put status */ + last_block = NULL; + continue; + } + } + else + { + block = rt_slist_entry(node, struct rt_rbb_blk, list); + /* + * these following conditions will break the loop: + * 1. the current block is not put status + * 2. the last block and current block is not continuous + */ + if (block->status != RT_RBB_BLK_PUT || last_block->buf > block->buf) + { + break; + } + /* backup last block */ + last_block = block; + } + data_len += last_block->size; + } + + rt_hw_interrupt_enable(level); + + return data_len; +} +RTM_EXPORT(rt_rbb_next_blk_queue_len); + +/** + * get the ring block buffer object buffer size + * + * @param rbb ring block buffer object + * + * @return buffer size + */ +rt_size_t rt_rbb_get_buf_size(rt_rbb_t rbb) +{ + RT_ASSERT(rbb); + + return rbb->buf_size; +} +RTM_EXPORT(rt_rbb_get_buf_size); diff --git a/components/drivers/src/ringbuffer.c b/components/drivers/src/ringbuffer.c index 48bf590f8c..2e078ae053 100644 --- a/components/drivers/src/ringbuffer.c +++ b/components/drivers/src/ringbuffer.c @@ -1,21 +1,7 @@ /* - * File : ringbuffer.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/src/waitqueue.c b/components/drivers/src/waitqueue.c index a4c392a27c..02240edbdf 100644 --- a/components/drivers/src/waitqueue.c +++ b/components/drivers/src/waitqueue.c @@ -1,21 +1,7 @@ /* - * File : waitqueue.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/src/workqueue.c b/components/drivers/src/workqueue.c index 35aaafe133..158ea8b69b 100644 --- a/components/drivers/src/workqueue.c +++ b/components/drivers/src/workqueue.c @@ -1,21 +1,7 @@ /* - * File : workqueue.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbdevice/class/cdc.h b/components/drivers/usb/usbdevice/class/cdc.h index dd919f51fe..4e07f16266 100644 --- a/components/drivers/usb/usbdevice/class/cdc.h +++ b/components/drivers/usb/usbdevice/class/cdc.h @@ -1,21 +1,7 @@ /* - * File : cdc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbdevice/class/cdc_vcom.c b/components/drivers/usb/usbdevice/class/cdc_vcom.c index 784f968772..336cfcb152 100644 --- a/components/drivers/usb/usbdevice/class/cdc_vcom.c +++ b/components/drivers/usb/usbdevice/class/cdc_vcom.c @@ -1,21 +1,7 @@ /* - * File : cdc_vcom.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,12 @@ #ifdef RT_USB_DEVICE_CDC -#define TX_TIMEOUT 1000 +#ifdef RT_VCOM_TX_TIMEOUT +#define VCOM_TX_TIMEOUT RT_VCOM_TX_TIMEOUT +#else /*!RT_VCOM_TX_TIMEOUT*/ +#define VCOM_TX_TIMEOUT 1000 +#endif /*RT_VCOM_TX_TIMEOUT*/ + #define CDC_RX_BUFSIZE 128 #define CDC_MAX_PACKET_SIZE 64 #define VCOM_DEVICE "vcom" @@ -96,6 +87,7 @@ struct vcom_tx_msg rt_size_t size; }; +ALIGN(4) static struct udevice_descriptor dev_desc = { USB_DESC_LENGTH_DEVICE, //bLength; @@ -115,6 +107,7 @@ static struct udevice_descriptor dev_desc = }; //FS and HS needed +ALIGN(4) static struct usb_qualifier_descriptor dev_qualifier = { sizeof(dev_qualifier), //bLength @@ -129,89 +122,111 @@ static struct usb_qualifier_descriptor dev_qualifier = }; /* communcation interface descriptor */ +ALIGN(4) const static struct ucdc_comm_descriptor _comm_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ - USB_DESC_LENGTH_IAD, - USB_DESC_TYPE_IAD, - USB_DYNAMIC, - 0x02, - USB_CDC_CLASS_COMM, - USB_CDC_SUBCLASS_ACM, - USB_CDC_PROTOCOL_V25TER, - 0x00, + { + USB_DESC_LENGTH_IAD, + USB_DESC_TYPE_IAD, + USB_DYNAMIC, + 0x02, + USB_CDC_CLASS_COMM, + USB_CDC_SUBCLASS_ACM, + USB_CDC_PROTOCOL_V25TER, + 0x00, + }, #endif /* Interface Descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, - 0x00, - 0x01, - USB_CDC_CLASS_COMM, - USB_CDC_SUBCLASS_ACM, - USB_CDC_PROTOCOL_V25TER, - 0x00, + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, + 0x00, + 0x01, + USB_CDC_CLASS_COMM, + USB_CDC_SUBCLASS_ACM, + USB_CDC_PROTOCOL_V25TER, + 0x00, + }, /* Header Functional Descriptor */ - 0x05, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_HEADER, - 0x0110, + { + 0x05, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_HEADER, + 0x0110, + }, /* Call Management Functional Descriptor */ - 0x05, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_CALL_MGMT, - 0x00, - USB_DYNAMIC, + { + 0x05, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_CALL_MGMT, + 0x00, + USB_DYNAMIC, + }, /* Abstract Control Management Functional Descriptor */ - 0x04, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_ACM, - 0x02, + { + 0x04, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_ACM, + 0x02, + }, /* Union Functional Descriptor */ - 0x05, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_UNION, - USB_DYNAMIC, - USB_DYNAMIC, + { + 0x05, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_UNION, + USB_DYNAMIC, + USB_DYNAMIC, + }, /* Endpoint Descriptor */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_INT, - 0x08, - 0xFF, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_IN, + USB_EP_ATTR_INT, + 0x08, + 0xFF, + }, }; /* data interface descriptor */ +ALIGN(4) const static struct ucdc_data_descriptor _data_desc = { /* interface descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, - 0x00, - 0x02, - USB_CDC_CLASS_DATA, - 0x00, - 0x00, - 0x00, + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, + 0x00, + 0x02, + USB_CDC_CLASS_DATA, + 0x00, + 0x00, + 0x00, + }, /* endpoint, bulk out */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_OUT, - USB_EP_ATTR_BULK, - USB_CDC_BUFSIZE, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_OUT, + USB_EP_ATTR_BULK, + USB_CDC_BUFSIZE, + 0x00, + }, /* endpoint, bulk in */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_BULK, - USB_CDC_BUFSIZE, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_IN, + USB_EP_ATTR_BULK, + USB_CDC_BUFSIZE, + 0x00, + }, }; - +ALIGN(4) static char serno[_SER_NO_LEN + 1] = {'\0'}; RT_WEAK rt_err_t vcom_get_stored_serno(char *serno, int size); @@ -219,7 +234,7 @@ rt_err_t vcom_get_stored_serno(char *serno, int size) { return RT_ERROR; } - +ALIGN(4) const static char* _ustring[] = { "Language", @@ -829,7 +844,7 @@ static void vcom_tx_thread_entry(void* parameter) { continue; } - if(!res & CDC_TX_HAS_DATE) + if(!(res & CDC_TX_HAS_DATE)) { continue; } @@ -870,7 +885,7 @@ static void vcom_tx_thread_entry(void* parameter) rt_usbd_io_request(func->device, data->ep_in, &data->ep_in->request); - if (rt_completion_wait(&data->wait, TX_TIMEOUT) != RT_EOK) + if (rt_completion_wait(&data->wait, VCOM_TX_TIMEOUT) != RT_EOK) { RT_DEBUG_LOG(RT_DEBUG_USB, ("vcom tx timeout\n")); } diff --git a/components/drivers/usb/usbdevice/class/ecm.c b/components/drivers/usb/usbdevice/class/ecm.c index 6f19a0099e..cda1a8bf1b 100644 --- a/components/drivers/usb/usbdevice/class/ecm.c +++ b/components/drivers/usb/usbdevice/class/ecm.c @@ -1,11 +1,7 @@ /* - * File : ecm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -80,52 +76,64 @@ const static struct ucdc_eth_descriptor _comm_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ - USB_DESC_LENGTH_IAD, - USB_DESC_TYPE_IAD, - USB_DYNAMIC, - 0x02, - USB_CDC_CLASS_COMM, - USB_CDC_SUBCLASS_ETH, - USB_CDC_PROTOCOL_NONE, - 0x00, + { + USB_DESC_LENGTH_IAD, + USB_DESC_TYPE_IAD, + USB_DYNAMIC, + 0x02, + USB_CDC_CLASS_COMM, + USB_CDC_SUBCLASS_ETH, + USB_CDC_PROTOCOL_NONE, + 0x00, + }, #endif /* Interface Descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, - 0x00, - 0x01, - USB_CDC_CLASS_COMM, - USB_CDC_SUBCLASS_ETH, - USB_CDC_PROTOCOL_NONE, - 0x00, + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, + 0x00, + 0x01, + USB_CDC_CLASS_COMM, + USB_CDC_SUBCLASS_ETH, + USB_CDC_PROTOCOL_NONE, + 0x00, + }, /* Header Functional Descriptor */ - sizeof(struct ucdc_header_descriptor), - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_HEADER, - 0x0110, + { + sizeof(struct ucdc_header_descriptor), + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_HEADER, + 0x0110, + }, /* Union Functional Descriptor */ - sizeof(struct ucdc_union_descriptor), - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_UNION, - USB_DYNAMIC, - USB_DYNAMIC, + { + sizeof(struct ucdc_union_descriptor), + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_UNION, + USB_DYNAMIC, + USB_DYNAMIC, + }, /* Abstract Control Management Functional Descriptor */ - sizeof(struct ucdc_enet_descriptor), - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_ETH, - USB_STRING_SERIAL_INDEX, - {0,0,0,0}, - USB_ETH_MTU, - 0x00, - 0x00, + { + sizeof(struct ucdc_enet_descriptor), + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_ETH, + USB_STRING_SERIAL_INDEX, + {0,0,0,0}, + USB_ETH_MTU, + 0x00, + 0x00, + }, /* Endpoint Descriptor */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DIR_IN | USB_DYNAMIC, - USB_EP_ATTR_INT, - 0x08, - 0xFF, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DIR_IN | USB_DYNAMIC, + USB_EP_ATTR_INT, + 0x08, + 0xFF, + }, }; /* data interface descriptor */ @@ -133,29 +141,35 @@ ALIGN(4) const static struct ucdc_data_descriptor _data_desc = { /* interface descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, - 0x00, - 0x02, - USB_CDC_CLASS_DATA, - USB_CDC_SUBCLASS_ETH, - 0x00, - 0x00, + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, + 0x00, + 0x02, + USB_CDC_CLASS_DATA, + USB_CDC_SUBCLASS_ETH, + 0x00, + 0x00, + }, /* endpoint, bulk out */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DIR_OUT | USB_DYNAMIC, - USB_EP_ATTR_BULK, - USB_DYNAMIC, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DIR_OUT | USB_DYNAMIC, + USB_EP_ATTR_BULK, + USB_DYNAMIC, + 0x00, + }, /* endpoint, bulk in */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_BULK, - USB_DYNAMIC, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_IN, + USB_EP_ATTR_BULK, + USB_DYNAMIC, + 0x00, + }, }; ALIGN(4) diff --git a/components/drivers/usb/usbdevice/class/hid.c b/components/drivers/usb/usbdevice/class/hid.c index bbaf7d23ef..aea6d802d1 100644 --- a/components/drivers/usb/usbdevice/class/hid.c +++ b/components/drivers/usb/usbdevice/class/hid.c @@ -1,7 +1,9 @@ /* * File : hid.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * COPYRIGHT (C) 2008 - 2018, RT-Thread Development Team * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2017-03-13 Urey the first version @@ -33,6 +35,7 @@ struct hid_s }; /* CustomHID_ConfigDescriptor */ +ALIGN(4) const rt_uint8_t _report_desc[]= { #ifdef RT_USB_DEVICE_HID_KEYBOARD @@ -237,6 +240,7 @@ const rt_uint8_t _report_desc[]= #endif }; /* CustomHID_ReportDescriptor */ +ALIGN(4) static struct udevice_descriptor _dev_desc = { USB_DESC_LENGTH_DEVICE, //bLength; @@ -256,6 +260,7 @@ static struct udevice_descriptor _dev_desc = }; //FS and HS needed +ALIGN(4) static struct usb_qualifier_descriptor dev_qualifier = { sizeof(dev_qualifier), //bLength @@ -271,78 +276,92 @@ static struct usb_qualifier_descriptor dev_qualifier = /* hid interface descriptor */ +ALIGN(4) const static struct uhid_comm_descriptor _hid_comm_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ - USB_DESC_LENGTH_IAD, - USB_DESC_TYPE_IAD, - USB_DYNAMIC, - 0x01, - 0x03, /* bInterfaceClass: HID */ + { + USB_DESC_LENGTH_IAD, + USB_DESC_TYPE_IAD, + USB_DYNAMIC, + 0x01, + 0x03, /* bInterfaceClass: HID */ #if defined(RT_USB_DEVICE_HID_KEYBOARD)||defined(RT_USB_DEVICE_HID_MOUSE) - USB_HID_SUBCLASS_BOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + USB_HID_SUBCLASS_BOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ #else - USB_HID_SUBCLASS_NOBOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + USB_HID_SUBCLASS_NOBOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ #endif #if !defined(RT_USB_DEVICE_HID_KEYBOARD)||!defined(RT_USB_DEVICE_HID_MOUSE)||!defined(RT_USB_DEVICE_HID_MEDIA) - USB_HID_PROTOCOL_NONE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + USB_HID_PROTOCOL_NONE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ #elif !defined(RT_USB_DEVICE_HID_MOUSE) - USB_HID_PROTOCOL_KEYBOARD, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + USB_HID_PROTOCOL_KEYBOARD, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ #else - USB_HID_PROTOCOL_MOUSE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + USB_HID_PROTOCOL_MOUSE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ #endif - 0x00, + 0x00, + }, #endif - /* Interface Descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ #if defined(RT_USB_DEVICE_HID_KEYBOARD)||defined(RT_USB_DEVICE_HID_MOUSE) - USB_HID_SUBCLASS_BOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + USB_HID_SUBCLASS_BOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ #else - USB_HID_SUBCLASS_NOBOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + USB_HID_SUBCLASS_NOBOOT, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ #endif #if !defined(RT_USB_DEVICE_HID_KEYBOARD)||!defined(RT_USB_DEVICE_HID_MOUSE)||!defined(RT_USB_DEVICE_HID_MEDIA) - USB_HID_PROTOCOL_NONE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + USB_HID_PROTOCOL_NONE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ #elif !defined(RT_USB_DEVICE_HID_MOUSE) - USB_HID_PROTOCOL_KEYBOARD, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + USB_HID_PROTOCOL_KEYBOARD, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ #else - USB_HID_PROTOCOL_MOUSE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + USB_HID_PROTOCOL_MOUSE, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ #endif - 0, /* iInterface: Index of string descriptor */ + 0, /* iInterface: Index of string descriptor */ + }, /* HID Descriptor */ - HID_DESCRIPTOR_SIZE, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ - 0x0110, /* bcdHID: HID Class Spec release number */ - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - sizeof(_report_desc), /* wItemLength: Total length of Report descriptor */ + { + HID_DESCRIPTOR_SIZE, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x0110, /* bcdHID: HID Class Spec release number */ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + { + { + 0x22, /* bDescriptorType */ + sizeof(_report_desc), /* wItemLength: Total length of Report descriptor */ + }, + }, + }, /* Endpoint Descriptor IN */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_INT, - 0x40, - 0x01, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_IN, + USB_EP_ATTR_INT, + 0x40, + 0x01, + }, /* Endpoint Descriptor OUT */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_OUT, - USB_EP_ATTR_INT, - 0x40, - 0x01, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_OUT, + USB_EP_ATTR_INT, + 0x40, + 0x01, + }, }; - +ALIGN(4) const static char* _ustring[] = { "Language", @@ -480,12 +499,7 @@ static rt_err_t _interface_handler(ufunction_t func, ureq_t setup) rt_usbd_ep0_read(func->device, data->report_buf, setup->wLength, _hid_set_report_callback); break; case USB_HID_REQ_SET_IDLE: - { - int duration = (setup->wValue >> 8); - int report_id = (setup->wValue & 0xFF); - dcd_ep0_send_status(func->device->dcd); - } break; case USB_HID_REQ_SET_PROTOCOL: data->protocol = setup->wValue; diff --git a/components/drivers/usb/usbdevice/class/hid.h b/components/drivers/usb/usbdevice/class/hid.h index 4e5dac964b..4d0f314a11 100644 --- a/components/drivers/usb/usbdevice/class/hid.h +++ b/components/drivers/usb/usbdevice/class/hid.h @@ -1,6 +1,7 @@ /* - * File : hid.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbdevice/class/mstorage.c b/components/drivers/usb/usbdevice/class/mstorage.c index 63d7b0f9ad..6a6e92415b 100644 --- a/components/drivers/usb/usbdevice/class/mstorage.c +++ b/components/drivers/usb/usbdevice/class/mstorage.c @@ -1,21 +1,7 @@ /* - * File : mstorage.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -82,6 +68,7 @@ struct mstorage struct rt_device_blk_geometry geometry; }; +ALIGN(4) static struct udevice_descriptor dev_desc = { USB_DESC_LENGTH_DEVICE, //bLength; @@ -101,6 +88,7 @@ static struct udevice_descriptor dev_desc = }; //FS and HS needed +ALIGN(4) static struct usb_qualifier_descriptor dev_qualifier = { sizeof(dev_qualifier), //bLength @@ -115,45 +103,54 @@ static struct usb_qualifier_descriptor dev_qualifier = }; - +ALIGN(4) const static struct umass_descriptor _mass_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ - USB_DESC_LENGTH_IAD, - USB_DESC_TYPE_IAD, - USB_DYNAMIC, - 0x01, - USB_CLASS_MASS_STORAGE, - 0x06, - 0x50, - 0x00, + { + USB_DESC_LENGTH_IAD, + USB_DESC_TYPE_IAD, + USB_DYNAMIC, + 0x01, + USB_CLASS_MASS_STORAGE, + 0x06, + 0x50, + 0x00, + }, #endif - USB_DESC_LENGTH_INTERFACE, //bLength; - USB_DESC_TYPE_INTERFACE, //type; - USB_DYNAMIC, //bInterfaceNumber; - 0x00, //bAlternateSetting; - 0x02, //bNumEndpoints - USB_CLASS_MASS_STORAGE, //bInterfaceClass; - 0x06, //bInterfaceSubClass; - 0x50, //bInterfaceProtocol; - 0x00, //iInterface; + { + USB_DESC_LENGTH_INTERFACE, //bLength; + USB_DESC_TYPE_INTERFACE, //type; + USB_DYNAMIC, //bInterfaceNumber; + 0x00, //bAlternateSetting; + 0x02, //bNumEndpoints + USB_CLASS_MASS_STORAGE, //bInterfaceClass; + 0x06, //bInterfaceSubClass; + 0x50, //bInterfaceProtocol; + 0x00, //iInterface; + }, - USB_DESC_LENGTH_ENDPOINT, //bLength; - USB_DESC_TYPE_ENDPOINT, //type; - USB_DYNAMIC | USB_DIR_OUT, //bEndpointAddress; - USB_EP_ATTR_BULK, //bmAttributes; - USB_DYNAMIC, //wMaxPacketSize; - 0x00, //bInterval; + { + USB_DESC_LENGTH_ENDPOINT, //bLength; + USB_DESC_TYPE_ENDPOINT, //type; + USB_DYNAMIC | USB_DIR_OUT, //bEndpointAddress; + USB_EP_ATTR_BULK, //bmAttributes; + USB_DYNAMIC, //wMaxPacketSize; + 0x00, //bInterval; + }, - USB_DESC_LENGTH_ENDPOINT, //bLength; - USB_DESC_TYPE_ENDPOINT, //type; - USB_DYNAMIC | USB_DIR_IN, //bEndpointAddress; - USB_EP_ATTR_BULK, //bmAttributes; - USB_DYNAMIC, //wMaxPacketSize; - 0x00, //bInterval; + { + USB_DESC_LENGTH_ENDPOINT, //bLength; + USB_DESC_TYPE_ENDPOINT, //type; + USB_DYNAMIC | USB_DIR_IN, //bEndpointAddress; + USB_EP_ATTR_BULK, //bmAttributes; + USB_DYNAMIC, //wMaxPacketSize; + 0x00, //bInterval; + }, }; +ALIGN(4) const static char* _ustring[] = { "Language", @@ -176,6 +173,7 @@ static rt_size_t _read_10(ufunction_t func, ustorage_cbw_t cbw); static rt_size_t _write_10(ufunction_t func, ustorage_cbw_t cbw); static rt_size_t _verify_10(ufunction_t func, ustorage_cbw_t cbw); +ALIGN(4) static struct scsi_cmd cmd_data[] = { {SCSI_TEST_UNIT_READY, _test_unit_ready, 6, FIXED, 0, DIR_NONE}, @@ -751,8 +749,8 @@ static rt_bool_t _cbw_verify(ufunction_t func, struct scsi_cmd* cmd, return RT_FALSE; } - if((cbw->dflags & USB_DIR_IN) && cmd->dir == DIR_OUT || - !(cbw->dflags & USB_DIR_IN) && cmd->dir == DIR_IN) + if(((cbw->dflags & USB_DIR_IN) && (cmd->dir == DIR_OUT)) || + (!(cbw->dflags & USB_DIR_IN) && (cmd->dir == DIR_IN))) { rt_kprintf("dir error\n"); return RT_FALSE; diff --git a/components/drivers/usb/usbdevice/class/mstorage.h b/components/drivers/usb/usbdevice/class/mstorage.h index 25068270bd..254038195b 100644 --- a/components/drivers/usb/usbdevice/class/mstorage.h +++ b/components/drivers/usb/usbdevice/class/mstorage.h @@ -1,21 +1,7 @@ /* - * File : mstorage.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbdevice/class/ndis.h b/components/drivers/usb/usbdevice/class/ndis.h index 8ad16637c2..6d6943366e 100644 --- a/components/drivers/usb/usbdevice/class/ndis.h +++ b/components/drivers/usb/usbdevice/class/ndis.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * ndis.h * diff --git a/components/drivers/usb/usbdevice/class/rndis.c b/components/drivers/usb/usbdevice/class/rndis.c index 0f680e9066..8996b728e6 100644 --- a/components/drivers/usb/usbdevice/class/rndis.c +++ b/components/drivers/usb/usbdevice/class/rndis.c @@ -1,11 +1,7 @@ /* - * File : rndis.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -106,54 +102,68 @@ const static struct ucdc_comm_descriptor _comm_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ - USB_DESC_LENGTH_IAD, - USB_DESC_TYPE_IAD, - USB_DYNAMIC, - 0x02, - USB_CDC_CLASS_COMM, - USB_CDC_SUBCLASS_ACM, - USB_CDC_PROTOCOL_VENDOR, - 0x00, + { + USB_DESC_LENGTH_IAD, + USB_DESC_TYPE_IAD, + USB_DYNAMIC, + 0x02, + USB_CDC_CLASS_COMM, + USB_CDC_SUBCLASS_ACM, + USB_CDC_PROTOCOL_VENDOR, + 0x00, + }, #endif /* Interface Descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, - 0x00, - 0x01, - USB_CDC_CLASS_COMM, - USB_CDC_SUBCLASS_ACM, - USB_CDC_PROTOCOL_VENDOR, - 0x00, + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, + 0x00, + 0x01, + USB_CDC_CLASS_COMM, + USB_CDC_SUBCLASS_ACM, + USB_CDC_PROTOCOL_VENDOR, + 0x00, + }, /* Header Functional Descriptor */ - 0x05, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_HEADER, - 0x0110, + { + 0x05, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_HEADER, + 0x0110, + }, /* Call Management Functional Descriptor */ - 0x05, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_CALL_MGMT, - 0x00, - USB_DYNAMIC, + { + 0x05, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_CALL_MGMT, + 0x00, + USB_DYNAMIC, + }, /* Abstract Control Management Functional Descriptor */ - 0x04, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_ACM, - 0x02, + { + 0x04, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_ACM, + 0x02, + }, /* Union Functional Descriptor */ - 0x05, - USB_CDC_CS_INTERFACE, - USB_CDC_SCS_UNION, - USB_DYNAMIC, - USB_DYNAMIC, + { + 0x05, + USB_CDC_CS_INTERFACE, + USB_CDC_SCS_UNION, + USB_DYNAMIC, + USB_DYNAMIC, + }, /* Endpoint Descriptor */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DIR_IN | USB_DYNAMIC, - USB_EP_ATTR_INT, - 0x08, - 0x0A, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DIR_IN | USB_DYNAMIC, + USB_EP_ATTR_INT, + 0x08, + 0x0A, + }, }; /* data interface descriptor */ @@ -161,29 +171,35 @@ ALIGN(4) const static struct ucdc_data_descriptor _data_desc = { /* interface descriptor */ - USB_DESC_LENGTH_INTERFACE, - USB_DESC_TYPE_INTERFACE, - USB_DYNAMIC, - 0x00, - 0x02, - USB_CDC_CLASS_DATA, - 0x00, - 0x00, - 0x00, + { + USB_DESC_LENGTH_INTERFACE, + USB_DESC_TYPE_INTERFACE, + USB_DYNAMIC, + 0x00, + 0x02, + USB_CDC_CLASS_DATA, + 0x00, + 0x00, + 0x00, + }, /* endpoint, bulk out */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DIR_OUT | USB_DYNAMIC, - USB_EP_ATTR_BULK, - USB_DYNAMIC, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DIR_OUT | USB_DYNAMIC, + USB_EP_ATTR_BULK, + USB_DYNAMIC, + 0x00, + }, /* endpoint, bulk in */ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_BULK, - USB_DYNAMIC, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_IN, + USB_EP_ATTR_BULK, + USB_DYNAMIC, + 0x00, + }, }; ALIGN(4) @@ -198,6 +214,7 @@ const static char* _ustring[] = USB_STRING_OS }; +ALIGN(4) struct usb_os_function_comp_id_descriptor rndis_func_comp_id_desc = { .bFirstInterfaceNumber = USB_DYNAMIC, @@ -206,7 +223,9 @@ struct usb_os_function_comp_id_descriptor rndis_func_comp_id_desc = .subCompatibleID = {'5', '1', '6', '2', '0', '0', '1', 0x00}, .reserved2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }; + //FS and HS needed +ALIGN(4) static struct usb_qualifier_descriptor dev_qualifier = { sizeof(dev_qualifier), //bLength diff --git a/components/drivers/usb/usbdevice/class/rndis.h b/components/drivers/usb/usbdevice/class/rndis.h index 1374338c14..000ea62baf 100644 --- a/components/drivers/usb/usbdevice/class/rndis.h +++ b/components/drivers/usb/usbdevice/class/rndis.h @@ -1,11 +1,7 @@ /* - * File : rndis.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbdevice/class/winusb.c b/components/drivers/usb/usbdevice/class/winusb.c index 9e7c957e7c..bf4b353d73 100644 --- a/components/drivers/usb/usbdevice/class/winusb.c +++ b/components/drivers/usb/usbdevice/class/winusb.c @@ -1,6 +1,7 @@ /* - * File : winusb.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,6 +24,7 @@ struct winusb_device typedef struct winusb_device * winusb_device_t; +ALIGN(4) static struct udevice_descriptor dev_desc = { USB_DESC_LENGTH_DEVICE, //bLength; @@ -40,7 +42,9 @@ static struct udevice_descriptor dev_desc = USB_STRING_SERIAL_INDEX, //iSerialNumber; USB_DYNAMIC, //bNumConfigurations; }; + //FS and HS needed +ALIGN(4) static struct usb_qualifier_descriptor dev_qualifier = { sizeof(dev_qualifier), //bLength @@ -54,46 +58,55 @@ static struct usb_qualifier_descriptor dev_qualifier = 0, }; +ALIGN(4) struct winusb_descriptor _winusb_desc = { #ifdef RT_USB_DEVICE_COMPOSITE /* Interface Association Descriptor */ - USB_DESC_LENGTH_IAD, - USB_DESC_TYPE_IAD, - USB_DYNAMIC, - 0x01, - 0xFF, - 0x00, - 0x00, - 0x00, + { + USB_DESC_LENGTH_IAD, + USB_DESC_TYPE_IAD, + USB_DYNAMIC, + 0x01, + 0xFF, + 0x00, + 0x00, + 0x00, + }, #endif /*interface descriptor*/ - USB_DESC_LENGTH_INTERFACE, //bLength; - USB_DESC_TYPE_INTERFACE, //type; - USB_DYNAMIC, //bInterfaceNumber; - 0x00, //bAlternateSetting; - 0x02, //bNumEndpoints - 0xFF, //bInterfaceClass; - 0x00, //bInterfaceSubClass; - 0x00, //bInterfaceProtocol; - 0x00, //iInterface; + { + USB_DESC_LENGTH_INTERFACE, //bLength; + USB_DESC_TYPE_INTERFACE, //type; + USB_DYNAMIC, //bInterfaceNumber; + 0x00, //bAlternateSetting; + 0x02, //bNumEndpoints + 0xFF, //bInterfaceClass; + 0x00, //bInterfaceSubClass; + 0x00, //bInterfaceProtocol; + 0x00, //iInterface; + }, /*endpoint descriptor*/ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_OUT, - USB_EP_ATTR_BULK, - USB_DYNAMIC, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_OUT, + USB_EP_ATTR_BULK, + USB_DYNAMIC, + 0x00, + }, /*endpoint descriptor*/ - USB_DESC_LENGTH_ENDPOINT, - USB_DESC_TYPE_ENDPOINT, - USB_DYNAMIC | USB_DIR_IN, - USB_EP_ATTR_BULK, - USB_DYNAMIC, - 0x00, + { + USB_DESC_LENGTH_ENDPOINT, + USB_DESC_TYPE_ENDPOINT, + USB_DYNAMIC | USB_DIR_IN, + USB_EP_ATTR_BULK, + USB_DYNAMIC, + 0x00, + }, }; - +ALIGN(4) const static char* _ustring[] = { "Language", @@ -104,11 +117,14 @@ const static char* _ustring[] = "Interface", USB_STRING_OS//must be }; + +ALIGN(4) struct usb_os_proerty winusb_proerty[] = { USB_OS_PROERTY_DESC(USB_OS_PROERTY_TYPE_REG_SZ,"DeviceInterfaceGUID",RT_WINUSB_GUID), }; +ALIGN(4) struct usb_os_function_comp_id_descriptor winusb_func_comp_id_desc = { .bFirstInterfaceNumber = USB_DYNAMIC, diff --git a/components/drivers/usb/usbdevice/class/winusb.h b/components/drivers/usb/usbdevice/class/winusb.h index 86aa7f413c..b5f87b4e56 100644 --- a/components/drivers/usb/usbdevice/class/winusb.h +++ b/components/drivers/usb/usbdevice/class/winusb.h @@ -1,6 +1,7 @@ /* - * File : winusb.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbdevice/core/core.c b/components/drivers/usb/usbdevice/core/core.c index 297e1ab48d..fb850d6d2b 100644 --- a/components/drivers/usb/usbdevice/core/core.c +++ b/components/drivers/usb/usbdevice/core/core.c @@ -1,21 +1,7 @@ /* - * File : core.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,7 @@ static rt_list_t device_list; static rt_size_t rt_usbd_ep_write(udevice_t device, uep_t ep, void *buffer, rt_size_t size); static rt_size_t rt_usbd_ep_read_prepare(udevice_t device, uep_t ep, void *buffer, rt_size_t size); static rt_err_t rt_usbd_ep_assign(udevice_t device, uep_t ep); -static rt_err_t rt_usbd_ep_unassign(udevice_t device, uep_t ep); +rt_err_t rt_usbd_ep_unassign(udevice_t device, uep_t ep); /** * This function will handle get_device_descriptor bRequest. @@ -1865,7 +1851,7 @@ static rt_err_t rt_usbd_ep_assign(udevice_t device, uep_t ep) return -RT_ERROR; } -static rt_err_t rt_usbd_ep_unassign(udevice_t device, uep_t ep) +rt_err_t rt_usbd_ep_unassign(udevice_t device, uep_t ep) { RT_ASSERT(device != RT_NULL); RT_ASSERT(device->dcd != RT_NULL); diff --git a/components/drivers/usb/usbdevice/core/usbdevice.c b/components/drivers/usb/usbdevice/core/usbdevice.c index 72f80dc254..2455bd8017 100644 --- a/components/drivers/usb/usbdevice/core/usbdevice.c +++ b/components/drivers/usb/usbdevice/core/usbdevice.c @@ -1,21 +1,8 @@ /* - * File : usbdevice.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * File : hid.c + * COPYRIGHT (C) 2008 - 2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -78,11 +65,13 @@ static struct usb_qualifier_descriptor dev_qualifier = struct usb_os_comp_id_descriptor usb_comp_id_desc = { //head section - USB_DYNAMIC, - 0x0100, - 0x04, - USB_DYNAMIC, - {0x00,0x00,0x00,0x00,0x00,0x00,0x00}, + { + USB_DYNAMIC, + 0x0100, + 0x04, + USB_DYNAMIC, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00}, + }, }; static rt_list_t class_list; int rt_usbd_class_list_init(void) @@ -94,6 +83,13 @@ INIT_BOARD_EXPORT(rt_usbd_class_list_init); rt_err_t rt_usbd_class_register(udclass_t udclass) { +#ifndef RT_USB_DEVICE_COMPOSITE + if(!rt_list_isempty(&class_list)) + { + rt_kprintf("[D/USBD] If you want to use usb composite device please define RT_USB_DEVICE_COMPOSITE\n"); + return RT_ERROR; + } +#endif rt_list_insert_before(&class_list,&udclass->list); return RT_EOK; } @@ -107,6 +103,11 @@ rt_err_t rt_usb_device_init(void) rt_list_t *i; udclass_t udclass; + if(rt_list_isempty(&class_list)) + { + rt_kprintf("[D/USBD] No class register on usb device\n"); + return RT_ERROR; + } /* create and startup usb device thread */ rt_usbd_core_init(); diff --git a/components/drivers/usb/usbhost/class/adk.c b/components/drivers/usb/usbhost/class/adk.c index e7eed45127..2425de7bba 100644 --- a/components/drivers/usb/usbhost/class/adk.c +++ b/components/drivers/usb/usbhost/class/adk.c @@ -1,21 +1,7 @@ /* - * File : adk.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -69,7 +55,7 @@ static rt_err_t rt_usbh_adk_get_protocol(struct uintf* intf, rt_uint16_t *protoc { struct urequest setup; uinst_t device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -103,7 +89,7 @@ static rt_err_t rt_usbh_adk_send_string(struct uintf* intf, rt_uint16_t index, { struct urequest setup; uinst_t device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -136,7 +122,7 @@ static rt_err_t rt_usbh_adk_start(struct uintf* intf) { struct urequest setup; uinst_t device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); diff --git a/components/drivers/usb/usbhost/class/adk.h b/components/drivers/usb/usbhost/class/adk.h index f08bea5f59..041d47c674 100644 --- a/components/drivers/usb/usbhost/class/adk.h +++ b/components/drivers/usb/usbhost/class/adk.h @@ -1,21 +1,7 @@ /* - * File : adk.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbhost/class/hid.c b/components/drivers/usb/usbhost/class/hid.c index 2c226ca963..e16096877f 100644 --- a/components/drivers/usb/usbhost/class/hid.c +++ b/components/drivers/usb/usbhost/class/hid.c @@ -1,11 +1,7 @@ /* - * File : hid.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,7 +30,7 @@ rt_err_t rt_usbh_hid_set_idle(struct uintf* intf, int duration, int report_id) { struct urequest setup; struct uinstance* device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -68,7 +64,7 @@ rt_err_t rt_usbh_hid_get_report(struct uintf* intf, rt_uint8_t type, { struct urequest setup; struct uinstance* device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -101,7 +97,7 @@ rt_err_t rt_usbh_hid_set_report(struct uintf* intf, rt_uint8_t *buffer, rt_size_ { struct urequest setup; struct uinstance* device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -133,7 +129,7 @@ rt_err_t rt_usbh_hid_set_protocal(struct uintf* intf, int protocol) { struct urequest setup; struct uinstance* device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -168,7 +164,7 @@ rt_err_t rt_usbh_hid_get_report_descriptor(struct uintf* intf, { struct urequest setup; struct uinstance* device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(intf != RT_NULL); @@ -218,7 +214,7 @@ static void rt_usbh_hid_callback(void* context) { upipe_t pipe; struct uhid* hid; - int timeout = 300; + int timeout = USB_TIMEOUT_LONG; /* parameter check */ RT_ASSERT(context != RT_NULL); @@ -273,7 +269,7 @@ static rt_err_t rt_usbh_hid_enable(void* arg) uprotocal_t protocal; struct uhid* hid; struct uintf* intf = (struct uintf*)arg; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; upipe_t pipe; /* parameter check */ diff --git a/components/drivers/usb/usbhost/class/hid.h b/components/drivers/usb/usbhost/class/hid.h index 22dcbabde8..8e446c8cea 100644 --- a/components/drivers/usb/usbhost/class/hid.h +++ b/components/drivers/usb/usbhost/class/hid.h @@ -1,11 +1,7 @@ /* - * File : hid.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbhost/class/mass.c b/components/drivers/usb/usbhost/class/mass.c index ff52f8d6f5..20048873f5 100644 --- a/components/drivers/usb/usbhost/class/mass.c +++ b/components/drivers/usb/usbhost/class/mass.c @@ -1,11 +1,7 @@ /* - * File : mass.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -194,7 +190,7 @@ rt_err_t rt_usbh_storage_get_max_lun(struct uhintf* intf, rt_uint8_t* max_lun) { struct uinstance* device; struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; if(intf == RT_NULL) { @@ -244,7 +240,7 @@ rt_err_t rt_usbh_storage_reset(struct uhintf* intf) { struct urequest setup; struct uinstance* device; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ if(intf == RT_NULL) @@ -381,7 +377,7 @@ rt_err_t rt_usbh_storage_write10(struct uhintf* intf, rt_uint8_t *buffer, rt_err_t rt_usbh_storage_request_sense(struct uhintf* intf, rt_uint8_t* buffer) { struct ustorage_cbw cmd; - int timeout = 200; + int timeout = USB_TIMEOUT_LONG; /* parameter check */ if(intf == RT_NULL) @@ -417,7 +413,7 @@ rt_err_t rt_usbh_storage_request_sense(struct uhintf* intf, rt_uint8_t* buffer) rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf) { struct ustorage_cbw cmd; - int timeout = 200; + int timeout = USB_TIMEOUT_LONG; /* parameter check */ if(intf == RT_NULL) @@ -453,7 +449,7 @@ rt_err_t rt_usbh_storage_test_unit_ready(struct uhintf* intf) rt_err_t rt_usbh_storage_inquiry(struct uhintf* intf, rt_uint8_t* buffer) { struct ustorage_cbw cmd; - int timeout = 200; + int timeout = USB_TIMEOUT_LONG; /* parameter check */ if(intf == RT_NULL) @@ -490,7 +486,7 @@ rt_err_t rt_usbh_storage_inquiry(struct uhintf* intf, rt_uint8_t* buffer) rt_err_t rt_usbh_storage_get_capacity(struct uhintf* intf, rt_uint8_t* buffer) { struct ustorage_cbw cmd; - int timeout = 200; + int timeout = USB_TIMEOUT_LONG; /* parameter check */ if(intf == RT_NULL) diff --git a/components/drivers/usb/usbhost/class/mass.h b/components/drivers/usb/usbhost/class/mass.h index 38cdb32399..770e64a03f 100644 --- a/components/drivers/usb/usbhost/class/mass.h +++ b/components/drivers/usb/usbhost/class/mass.h @@ -1,11 +1,7 @@ /* - * File : mass.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbhost/class/udisk.c b/components/drivers/usb/usbhost/class/udisk.c index cdd2551c96..1509a26105 100644 --- a/components/drivers/usb/usbhost/class/udisk.c +++ b/components/drivers/usb/usbhost/class/udisk.c @@ -1,11 +1,7 @@ /* - * File : udisk.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -74,13 +70,13 @@ static rt_size_t rt_udisk_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_err_t ret; struct uhintf* intf; struct ustor_data* data; - int timeout = 500; + int timeout = USB_TIMEOUT_LONG; /* check parameter */ RT_ASSERT(dev != RT_NULL); RT_ASSERT(buffer != RT_NULL); - if(size > 4096) timeout = 800; + if(size > 4096) timeout *= 2; data = (struct ustor_data*)dev->user_data; intf = data->intf; @@ -112,13 +108,13 @@ static rt_size_t rt_udisk_write (rt_device_t dev, rt_off_t pos, const void* buff rt_err_t ret; struct uhintf* intf; struct ustor_data* data; - int timeout = 500; + int timeout = USB_TIMEOUT_LONG; /* check parameter */ RT_ASSERT(dev != RT_NULL); RT_ASSERT(buffer != RT_NULL); - if(size * SECTOR_SIZE > 4096) timeout = 800; + if(size * SECTOR_SIZE > 4096) timeout *= 2; data = (struct ustor_data*)dev->user_data; intf = data->intf; @@ -297,7 +293,7 @@ rt_err_t rt_udisk_run(struct uhintf* intf) RT_DEBUG_LOG(RT_DEBUG_USB, ("read partition table\n")); /* get the partition table */ - ret = rt_usbh_storage_read10(intf, sector, 0, 1, 500); + ret = rt_usbh_storage_read10(intf, sector, 0, 1, USB_TIMEOUT_LONG); if(ret != RT_EOK) { rt_kprintf("read parition table error\n"); diff --git a/components/drivers/usb/usbhost/class/ukbd.c b/components/drivers/usb/usbhost/class/ukbd.c index 9f7d4bda3a..7d608de259 100644 --- a/components/drivers/usb/usbhost/class/ukbd.c +++ b/components/drivers/usb/usbhost/class/ukbd.c @@ -1,11 +1,7 @@ /* - * File : ukbd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbhost/class/umouse.c b/components/drivers/usb/usbhost/class/umouse.c index 0fb529f598..e769475a98 100644 --- a/components/drivers/usb/usbhost/class/umouse.c +++ b/components/drivers/usb/usbhost/class/umouse.c @@ -1,11 +1,7 @@ /* - * File : umouse.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbhost/core/core.c b/components/drivers/usb/usbhost/core/core.c index 854c3815af..71341a33c3 100644 --- a/components/drivers/usb/usbhost/core/core.c +++ b/components/drivers/usb/usbhost/core/core.c @@ -1,21 +1,7 @@ /* - * File : core.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -274,18 +260,20 @@ rt_err_t rt_usbh_detach_instance(uinst_t device) } /* free configration descriptor */ - for(i=0; icfg_desc->bNumInterfaces; i++) - { - if(device->intf[i] == RT_NULL) continue; - if(device->intf[i]->drv == RT_NULL) continue; + if (device->cfg_desc) { + for (i = 0; i < device->cfg_desc->bNumInterfaces; i++) + { + if (device->intf[i] == RT_NULL) continue; + if (device->intf[i]->drv == RT_NULL) continue; - RT_ASSERT(device->intf[i]->device == device); + RT_ASSERT(device->intf[i]->device == device); - RT_DEBUG_LOG(RT_DEBUG_USB, ("free interface instance %d\n", i)); - rt_usbh_class_driver_disable(device->intf[i]->drv, (void*)device->intf[i]); - rt_free(device->intf[i]); + RT_DEBUG_LOG(RT_DEBUG_USB, ("free interface instance %d\n", i)); + rt_usbh_class_driver_disable(device->intf[i]->drv, (void*)device->intf[i]); + rt_free(device->intf[i]); + } + rt_free(device->cfg_desc); } - if(device->cfg_desc) rt_free(device->cfg_desc); rt_usb_hcd_free_pipe(device->hcd,device->pipe_ep0_out); rt_usb_hcd_free_pipe(device->hcd,device->pipe_ep0_in); @@ -315,7 +303,7 @@ rt_err_t rt_usbh_get_descriptor(uinst_t device, rt_uint8_t type, void* buffer, int nbytes) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; RT_ASSERT(device != RT_NULL); @@ -349,7 +337,7 @@ rt_err_t rt_usbh_get_descriptor(uinst_t device, rt_uint8_t type, void* buffer, rt_err_t rt_usbh_set_address(uinst_t device) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; RT_ASSERT(device != RT_NULL); @@ -385,7 +373,7 @@ rt_err_t rt_usbh_set_address(uinst_t device) rt_err_t rt_usbh_set_configure(uinst_t device, int config) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* check parameter */ RT_ASSERT(device != RT_NULL); @@ -419,7 +407,7 @@ rt_err_t rt_usbh_set_configure(uinst_t device, int config) rt_err_t rt_usbh_set_interface(uinst_t device, int intf) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* check parameter */ RT_ASSERT(device != RT_NULL); @@ -450,7 +438,7 @@ rt_err_t rt_usbh_set_interface(uinst_t device, int intf) rt_err_t rt_usbh_clear_feature(uinst_t device, int endpoint, int feature) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* check parameter */ RT_ASSERT(device != RT_NULL); diff --git a/components/drivers/usb/usbhost/core/driver.c b/components/drivers/usb/usbhost/core/driver.c index 19c8805732..37327108c1 100644 --- a/components/drivers/usb/usbhost/core/driver.c +++ b/components/drivers/usb/usbhost/core/driver.c @@ -1,21 +1,7 @@ /* - * File : driver.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/usb/usbhost/core/hub.c b/components/drivers/usb/usbhost/core/hub.c index 56e40bb0d5..80ed9b4e3f 100644 --- a/components/drivers/usb/usbhost/core/hub.c +++ b/components/drivers/usb/usbhost/core/hub.c @@ -1,21 +1,7 @@ /* - * File : hub.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -132,7 +118,7 @@ void rt_usbh_root_hub_disconnect_handler(struct uhcd *hcd, rt_uint8_t port) rt_err_t rt_usbh_hub_get_descriptor(struct uinstance* device, rt_uint8_t *buffer, rt_size_t nbytes) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(device != RT_NULL); @@ -165,7 +151,7 @@ rt_err_t rt_usbh_hub_get_descriptor(struct uinstance* device, rt_uint8_t *buffer rt_err_t rt_usbh_hub_get_status(struct uinstance* device, rt_uint32_t* buffer) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(device != RT_NULL); @@ -198,7 +184,7 @@ rt_err_t rt_usbh_hub_get_status(struct uinstance* device, rt_uint32_t* buffer) rt_err_t rt_usbh_hub_get_port_status(uhub_t hub, rt_uint16_t port, rt_uint32_t* buffer) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(hub != RT_NULL); @@ -240,7 +226,7 @@ rt_err_t rt_usbh_hub_get_port_status(uhub_t hub, rt_uint16_t port, rt_uint32_t* rt_err_t rt_usbh_hub_clear_port_feature(uhub_t hub, rt_uint16_t port, rt_uint16_t feature) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(hub != RT_NULL); @@ -249,7 +235,7 @@ rt_err_t rt_usbh_hub_clear_port_feature(uhub_t hub, rt_uint16_t port, rt_uint16_ if(hub->is_roothub) { root_hub_ctrl(hub->hcd, port, RH_CLEAR_PORT_FEATURE, - (void*)feature); + (void*)(rt_uint32_t)feature); return RT_EOK; } @@ -281,7 +267,7 @@ rt_err_t rt_usbh_hub_set_port_feature(uhub_t hub, rt_uint16_t port, rt_uint16_t feature) { struct urequest setup; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; /* parameter check */ RT_ASSERT(hub != RT_NULL); @@ -290,7 +276,7 @@ rt_err_t rt_usbh_hub_set_port_feature(uhub_t hub, rt_uint16_t port, if(hub->is_roothub) { root_hub_ctrl(hub->hcd, port, RH_SET_PORT_FEATURE, - (void*)feature); + (void*)(rt_uint32_t)feature); return RT_EOK; } @@ -359,6 +345,9 @@ rt_err_t rt_usbh_hub_port_debounce(uhub_t hub, rt_uint16_t port) int i = 0, times = 20; rt_uint32_t pstatus; rt_bool_t connect = RT_TRUE; + int delayticks = USB_DEBOUNCE_TIME / times; + if (delayticks < 1) + delayticks = 1; /* parameter check */ RT_ASSERT(hub != RT_NULL); @@ -374,7 +363,7 @@ rt_err_t rt_usbh_hub_port_debounce(uhub_t hub, rt_uint16_t port) break; } - rt_thread_delay(1); + rt_thread_delay(delayticks); } if(connect) return RT_EOK; @@ -413,7 +402,7 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) RT_DEBUG_LOG(RT_DEBUG_USB, ("port %d status 0x%x\n", i + 1, pstatus)); /* check port status change */ - if ((pstatus & PORT_CCSC)) + if (pstatus & PORT_CCSC) { /* clear port status change feature */ rt_usbh_hub_clear_port_feature(hub, i + 1, PORT_FEAT_C_CONNECTION); @@ -442,6 +431,7 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) device->speed = (pstatus & PORT_LSDA) ? 1 : 0; device->parent_hub = hub; device->hcd = hub->hcd; + device->port = i + 1; hub->child[i] = device; /* reset usb roothub port */ @@ -466,7 +456,7 @@ static void rt_usbh_hub_irq(void* context) { upipe_t pipe; uhub_t hub; - int timeout = 100; + int timeout = USB_TIMEOUT_BASIC; RT_ASSERT(context != RT_NULL); @@ -502,12 +492,12 @@ static rt_err_t rt_usbh_hub_enable(void *arg) { int i = 0; rt_err_t ret = RT_EOK; - uep_desc_t ep_desc; + uep_desc_t ep_desc = RT_NULL; uhub_t hub; struct uinstance* device; struct uhintf* intf = (struct uhintf*)arg; - upipe_t pipe_in; - int timeout = 300; + upipe_t pipe_in = RT_NULL; + int timeout = USB_TIMEOUT_LONG; /* paremeter check */ RT_ASSERT(intf != RT_NULL); diff --git a/components/drivers/usb/usbhost/core/usbhost.c b/components/drivers/usb/usbhost/core/usbhost.c index 15ac0b76cb..f0294238c4 100644 --- a/components/drivers/usb/usbhost/core/usbhost.c +++ b/components/drivers/usb/usbhost/core/usbhost.c @@ -1,21 +1,7 @@ /* - * File : usbhost.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/watchdog/watchdog.c b/components/drivers/watchdog/watchdog.c index e5453f8e43..196f02039d 100644 --- a/components/drivers/watchdog/watchdog.c +++ b/components/drivers/watchdog/watchdog.c @@ -1,21 +1,7 @@ /* - * File : watchdog.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012-2014, Shanghai Real-Thread Electronic Technology Co.,Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/drivers/wlan/wlan_cfg.c b/components/drivers/wlan/wlan_cfg.c new file mode 100644 index 0000000000..27da9bc24e --- /dev/null +++ b/components/drivers/wlan/wlan_cfg.c @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-06 tyx the first version + */ + +#include +#include + +#define DBG_ENABLE +#ifdef RT_WLAN_CFG_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif +#define DBG_SECTION_NAME "WLAN.cfg" +#define DBG_COLOR +#include + +#define WLAN_CFG_LOCK() (rt_mutex_take(&cfg_mutex, RT_WAITING_FOREVER)) +#define WLAN_CFG_UNLOCK() (rt_mutex_release(&cfg_mutex)) + +#if RT_WLAN_CFG_INFO_MAX < 1 +#error "The minimum configuration is 1" +#endif + +struct cfg_save_info_head +{ + rt_uint32_t magic; + rt_uint32_t len; + rt_uint32_t num; + rt_uint32_t crc; +}; + +struct rt_wlan_cfg_des +{ + rt_uint32_t num; + struct rt_wlan_cfg_info *cfg_info; +}; + +static struct rt_wlan_cfg_des *cfg_cache; +static const struct rt_wlan_cfg_ops *cfg_ops; +static struct rt_mutex cfg_mutex; + +/* + * CRC16_CCITT + */ +static rt_uint16_t rt_wlan_cal_crc(rt_uint8_t *buff, int len) +{ + rt_uint16_t wCRCin = 0x0000; + rt_uint16_t wCPoly = 0x1021; + rt_uint8_t wChar = 0; + + while (len--) + { + wChar = *(buff++); + wCRCin ^= (wChar << 8); + for (int i = 0; i < 8; i++) + { + if (wCRCin & 0x8000) + wCRCin = (wCRCin << 1) ^ wCPoly; + else + wCRCin = wCRCin << 1; + } + } + return wCRCin; +} + +void rt_wlan_cfg_init(void) +{ + /* init cache memory */ + if (cfg_cache == RT_NULL) + { + cfg_cache = rt_malloc(sizeof(struct rt_wlan_cfg_des)); + if (cfg_cache != RT_NULL) + { + rt_memset(cfg_cache, 0, sizeof(struct rt_wlan_cfg_des)); + } + /* init mutex lock */ + rt_mutex_init(&cfg_mutex, "wlan_cfg", RT_IPC_FLAG_FIFO); + } +} + +void rt_wlan_cfg_set_ops(const struct rt_wlan_cfg_ops *ops) +{ + rt_wlan_cfg_init(); + + WLAN_CFG_LOCK(); + /* save ops pointer */ + cfg_ops = ops; + WLAN_CFG_UNLOCK(); +} + +/* save config data */ +rt_err_t rt_wlan_cfg_cache_save(void) +{ + rt_err_t err = RT_EOK; + struct cfg_save_info_head *info_pkg; + int len = 0; + + if ((cfg_ops == RT_NULL) || (cfg_ops->write_cfg == RT_NULL)) + return RT_EOK; + + WLAN_CFG_LOCK(); + len = sizeof(struct cfg_save_info_head) + sizeof(struct rt_wlan_cfg_info) * cfg_cache->num; + info_pkg = rt_malloc(len); + if (info_pkg == RT_NULL) + { + WLAN_CFG_UNLOCK(); + return -RT_ENOMEM; + } + info_pkg->magic = RT_WLAN_CFG_MAGIC; + info_pkg->len = len; + info_pkg->num = cfg_cache->num; + /* CRC */ + info_pkg->crc = rt_wlan_cal_crc((rt_uint8_t *)cfg_cache->cfg_info, sizeof(struct rt_wlan_cfg_info) * cfg_cache->num); + rt_memcpy(((rt_uint8_t *)info_pkg) + sizeof(struct cfg_save_info_head), + cfg_cache->cfg_info, sizeof(struct rt_wlan_cfg_info) * cfg_cache->num); + if (cfg_ops->write_cfg(info_pkg, len) != len) + err = -RT_ERROR; + rt_free(info_pkg); + WLAN_CFG_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_cfg_cache_refresh(void) +{ + int len = 0, i, j; + struct cfg_save_info_head *head; + void *data; + struct rt_wlan_cfg_info *t_info, *cfg_info; + rt_uint32_t crc; + rt_bool_t equal_flag; + + /* cache is full! exit */ + if (cfg_cache == RT_NULL || cfg_cache->num >= RT_WLAN_CFG_INFO_MAX) + return -RT_ERROR; + + /* check callback */ + if ((cfg_ops == RT_NULL) || + (cfg_ops->get_len == RT_NULL) || + (cfg_ops->read_cfg == RT_NULL)) + return -RT_ERROR; + + WLAN_CFG_LOCK(); + /* get data len */ + if ((len = cfg_ops->get_len()) <= 0) + { + WLAN_CFG_UNLOCK(); + return -RT_ERROR; + } + + head = rt_malloc(len); + if (head == RT_NULL) + { + WLAN_CFG_UNLOCK(); + return -RT_ERROR; + } + /* get data */ + if (cfg_ops->read_cfg(head, len) != len) + { + rt_free(head); + WLAN_CFG_UNLOCK(); + return -RT_ERROR; + } + /* get config */ + data = ((rt_uint8_t *)head) + sizeof(struct cfg_save_info_head); + crc = rt_wlan_cal_crc((rt_uint8_t *)data, len - sizeof(struct cfg_save_info_head)); + LOG_D("head->magic:0x%08x RT_WLAN_CFG_MAGIC:0x%08x", head->magic, RT_WLAN_CFG_MAGIC); + LOG_D("head->len:%d len:%d", head->len, len); + LOG_D("head->num:%d num:%d", head->num, (len - sizeof(struct cfg_save_info_head)) / sizeof(struct rt_wlan_cfg_info)); + LOG_D("hred->crc:0x%04x crc:0x%04x", head->crc, crc); + /* check */ + if ((head->magic != RT_WLAN_CFG_MAGIC) || + (head->len != len) || + (head->num != (len - sizeof(struct cfg_save_info_head)) / sizeof(struct rt_wlan_cfg_info)) || + (head->crc != crc)) + { + rt_free(head); + WLAN_CFG_UNLOCK(); + return -RT_ERROR; + } + + /* remove duplicate config */ + cfg_info = (struct rt_wlan_cfg_info *)data; + for (i = 0; i < head->num; i++) + { + equal_flag = RT_FALSE; + for (j = 0; j < cfg_cache->num; j++) + { + if ((cfg_cache->cfg_info[j].info.ssid.len == cfg_info[i].info.ssid.len) && + (rt_memcmp(&cfg_cache->cfg_info[j].info.ssid.val[0], &cfg_info[i].info.ssid.val[0], + cfg_cache->cfg_info[j].info.ssid.len) == 0) && + (rt_memcmp(&cfg_cache->cfg_info[j].info.bssid[0], &cfg_info[i].info.bssid[0], RT_WLAN_BSSID_MAX_LENGTH) == 0)) + { + equal_flag = RT_TRUE; + break; + } + } + + if (cfg_cache->num >= RT_WLAN_CFG_INFO_MAX) + { + break; + } + + if (equal_flag == RT_FALSE) + { + t_info = rt_realloc(cfg_cache->cfg_info, sizeof(struct rt_wlan_cfg_info) * (cfg_cache->num + 1)); + if (t_info == RT_NULL) + { + rt_free(head); + WLAN_CFG_UNLOCK(); + return -RT_ERROR; + } + cfg_cache->cfg_info = t_info; + cfg_cache->cfg_info[cfg_cache->num] = cfg_info[i]; + cfg_cache->num ++; + } + } + + rt_free(head); + WLAN_CFG_UNLOCK(); + return RT_EOK; +} + +int rt_wlan_cfg_get_num(void) +{ + rt_wlan_cfg_init(); + + return cfg_cache->num; +} + +int rt_wlan_cfg_read(struct rt_wlan_cfg_info *cfg_info, int num) +{ + rt_wlan_cfg_init(); + + if ((cfg_info == RT_NULL) || (num <= 0)) + return 0; + /* copy data */ + WLAN_CFG_LOCK(); + num = cfg_cache->num > num ? num : cfg_cache->num; + rt_memcpy(&cfg_cache->cfg_info[0], cfg_info, sizeof(struct rt_wlan_cfg_info) * num); + WLAN_CFG_UNLOCK(); + + return num; +} + +rt_err_t rt_wlan_cfg_save(struct rt_wlan_cfg_info *cfg_info) +{ + rt_err_t err = RT_EOK; + struct rt_wlan_cfg_info *t_info; + int idx = -1, i = 0; + + rt_wlan_cfg_init(); + + /* parameter check */ + if ((cfg_info == RT_NULL) || (cfg_info->info.ssid.len == 0)) + { + return -RT_EINVAL; + } + /* if (iteam == cache) exit */ + WLAN_CFG_LOCK(); + for (i = 0; i < cfg_cache->num; i++) + { + if ((cfg_cache->cfg_info[i].info.ssid.len == cfg_info->info.ssid.len) && + (rt_memcmp(&cfg_cache->cfg_info[i].info.ssid.val[0], &cfg_info->info.ssid.val[0], + cfg_cache->cfg_info[i].info.ssid.len) == 0) && + (rt_memcmp(&cfg_cache->cfg_info[i].info.bssid[0], &cfg_info->info.bssid[0], RT_WLAN_BSSID_MAX_LENGTH) == 0)) + { + idx = i; + break; + } + } + + if ((idx == 0) && (cfg_cache->cfg_info[i].key.len == cfg_info->key.len) && + (rt_memcmp(&cfg_cache->cfg_info[i].key.val[0], &cfg_info->key.val[0], cfg_info->key.len) == 0)) + { + WLAN_CFG_UNLOCK(); + return RT_EOK; + } + + /* not find iteam with cache, Add iteam to the head */ + if ((idx == -1) && (cfg_cache->num < RT_WLAN_CFG_INFO_MAX)) + { + t_info = rt_realloc(cfg_cache->cfg_info, sizeof(struct rt_wlan_cfg_info) * (cfg_cache->num + 1)); + if (t_info == RT_NULL) + { + WLAN_CFG_UNLOCK(); + return -RT_ENOMEM; + } + cfg_cache->cfg_info = t_info; + cfg_cache->num ++; + } + + /* move cache info */ + i = (i >= RT_WLAN_CFG_INFO_MAX ? RT_WLAN_CFG_INFO_MAX - 1 : i); + for (; i; i--) + { + cfg_cache->cfg_info[i] = cfg_cache->cfg_info[i - 1]; + } + /* add iteam to head */ + cfg_cache->cfg_info[i] = *cfg_info; + WLAN_CFG_UNLOCK(); + + /* save info to flash */ + err = rt_wlan_cfg_cache_save(); + + return err; +} + +int rt_wlan_cfg_read_index(struct rt_wlan_cfg_info *cfg_info, int index) +{ + rt_wlan_cfg_init(); + + if ((cfg_info == RT_NULL) || (index < 0)) + return 0; + + WLAN_CFG_LOCK(); + if (index >= cfg_cache->num) + { + WLAN_CFG_UNLOCK(); + return 0; + } + /* copy data */ + *cfg_info = cfg_cache->cfg_info[index]; + WLAN_CFG_UNLOCK(); + return 1; +} + +int rt_wlan_cfg_delete_index(int index) +{ + struct rt_wlan_cfg_info *cfg_info; + int i; + + rt_wlan_cfg_init(); + + if (index < 0) + return -1; + + WLAN_CFG_LOCK(); + if (index >= cfg_cache->num) + { + WLAN_CFG_UNLOCK(); + return -1; + } + + /* malloc new mem */ + cfg_info = rt_malloc(sizeof(struct rt_wlan_cfg_info) * (cfg_cache->num - 1)); + if (cfg_info == RT_NULL) + { + WLAN_CFG_UNLOCK(); + return -1; + } + /* copy data to new mem */ + for (i = 0; i < cfg_cache->num; i++) + { + if (i < index) + { + cfg_info[i] = cfg_cache->cfg_info[i]; + } + else if (i > index) + { + cfg_info[i - 1] = cfg_cache->cfg_info[i]; + } + } + rt_free(cfg_cache->cfg_info); + cfg_cache->cfg_info = cfg_info; + cfg_cache->num --; + WLAN_CFG_UNLOCK(); + + return 0; +} + +void rt_wlan_cfg_delete_all(void) +{ + rt_wlan_cfg_init(); + + /* delete all iteam */ + WLAN_CFG_LOCK(); + cfg_cache->num = 0; + rt_free(cfg_cache->cfg_info); + cfg_cache->cfg_info = RT_NULL; + WLAN_CFG_UNLOCK(); +} + +void rt_wlan_cfg_dump(void) +{ + int index = 0; + struct rt_wlan_info *info; + struct rt_wlan_key *key; + char *security; + + rt_wlan_cfg_init(); + + rt_kprintf(" SSID PASSWORD MAC security chn\n"); + rt_kprintf("------------------------------- ------------------------------- ----------------- -------------- ---\n"); + for (index = 0; index < cfg_cache->num; index ++) + { + info = &cfg_cache->cfg_info[index].info; + key = &cfg_cache->cfg_info[index].key; + + if (info->ssid.len) + rt_kprintf("%-32.32s", &info->ssid.val[0]); + else + rt_kprintf("%-32.32s", " "); + + if (key->len) + rt_kprintf("%-32.32s", &key->val[0]); + else + rt_kprintf("%-32.32s", " "); + + rt_kprintf("%02x:%02x:%02x:%02x:%02x:%02x ", + info->bssid[0], + info->bssid[1], + info->bssid[2], + info->bssid[3], + info->bssid[4], + info->bssid[5] + ); + switch (info->security) + { + case SECURITY_OPEN: + security = "OPEN"; + break; + case SECURITY_WEP_PSK: + security = "WEP_PSK"; + break; + case SECURITY_WEP_SHARED: + security = "WEP_SHARED"; + break; + case SECURITY_WPA_TKIP_PSK: + security = "WPA_TKIP_PSK"; + break; + case SECURITY_WPA_AES_PSK: + security = "WPA_AES_PSK"; + break; + case SECURITY_WPA2_AES_PSK: + security = "WPA2_AES_PSK"; + break; + case SECURITY_WPA2_TKIP_PSK: + security = "WPA2_TKIP_PSK"; + break; + case SECURITY_WPA2_MIXED_PSK: + security = "WPA2_MIXED_PSK"; + break; + case SECURITY_WPS_OPEN: + security = "WPS_OPEN"; + break; + case SECURITY_WPS_SECURE: + security = "WPS_SECURE"; + break; + default: + security = "UNKNOWN"; + break; + } + rt_kprintf("%-14.14s ", security); + rt_kprintf("%3d \n", info->channel); + } +} diff --git a/components/drivers/wlan/wlan_cfg.h b/components/drivers/wlan/wlan_cfg.h new file mode 100644 index 0000000000..3fae3f3e98 --- /dev/null +++ b/components/drivers/wlan/wlan_cfg.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-06 tyx the first version + */ + +#ifndef __WLAN_CFG_H__ +#define __WLAN_CFG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef RT_WLAN_CFG_INFO_MAX +#define RT_WLAN_CFG_INFO_MAX (3) /* min is 1 */ +#endif + +#define RT_WLAN_CFG_MAGIC (0x426f6d62) + +struct rt_wlan_cfg_info +{ + struct rt_wlan_info info; + struct rt_wlan_key key; +}; + +typedef int (*rt_wlan_wr)(void *buff, int len); + +struct rt_wlan_cfg_ops +{ + int (*read_cfg)(void *buff, int len); + int (*get_len)(void); + int (*write_cfg)(void *buff, int len); +}; + +void rt_wlan_cfg_init(void); + +void rt_wlan_cfg_set_ops(const struct rt_wlan_cfg_ops *ops); + +int rt_wlan_cfg_get_num(void); + +int rt_wlan_cfg_read(struct rt_wlan_cfg_info *cfg_info, int num); + +int rt_wlan_cfg_read_index(struct rt_wlan_cfg_info *cfg_info, int index); + +rt_err_t rt_wlan_cfg_save(struct rt_wlan_cfg_info *cfg_info); + +rt_err_t rt_wlan_cfg_cache_refresh(void); + +rt_err_t rt_wlan_cfg_cache_save(void); + +int rt_wlan_cfg_delete_index(int index); + +void rt_wlan_cfg_delete_all(void); + +void rt_wlan_cfg_dump(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/drivers/wlan/wlan_cmd.c b/components/drivers/wlan/wlan_cmd.c index eda628a357..b962b63947 100644 --- a/components/drivers/wlan/wlan_cmd.c +++ b/components/drivers/wlan/wlan_cmd.c @@ -1,527 +1,566 @@ /* - * File : wlan_cmd.c - * Wi-Fi common commands - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016-03-12 Bernard first version + * 2018-08-13 tyx the first version */ #include -#include +#include +#include +#include -#include - -#include -#include "wlan_cmd.h" - -#ifdef LWIP_USING_DHCPD -#include -#endif - -struct rt_wlan_info info; -static char wifi_ssid[32] = {0}; -static char wifi_key[32] = {0}; -static int network_mode = WIFI_STATION; - -#define WLAN_DEBUG 1 -#if WLAN_DEBUG -#define WLAN_DBG(...) rt_kprintf("[WLAN]"),rt_kprintf(__VA_ARGS__) -#else -#define WLAN_DBG(...) -#endif - -#ifndef WIFI_SETTING_FN -#define WIFI_SETTING_FN "/appfs/setting.json" -#endif - -#ifndef WIFI_DEVICE_STA_NAME -#define WIFI_DEVICE_STA_NAME "w0" -#endif -#ifndef WIFI_DEVICE_AP_NAME -#define WIFI_DEVICE_AP_NAME "ap" -#endif - -#ifdef RT_USING_DFS -#include -#ifdef PKG_USING_CJSON -#include -#endif - -int wifi_get_mode(void) +struct wifi_cmd_des { - return network_mode; -} + const char *cmd; + int (*fun)(int argc, char *argv[]); +}; -int wifi_set_mode(int mode) +static int wifi_help(int argc, char *argv[]); +static int wifi_scan(int argc, char *argv[]); +static int wifi_status(int argc, char *argv[]); +static int wifi_join(int argc, char *argv[]); +static int wifi_ap(int argc, char *argv[]); +static int wifi_list_sta(int argc, char *argv[]); +static int wifi_disconnect(int argc, char *argv[]); +static int wifi_ap_stop(int argc, char *argv[]); + +#ifdef RT_WLAN_CMD_DEBUG +/* just for debug */ +static int wifi_debug(int argc, char *argv[]); +static int wifi_debug_save_cfg(int argc, char *argv[]); +static int wifi_debug_dump_cfg(int argc, char *argv[]); +static int wifi_debug_clear_cfg(int argc, char *argv[]); +static int wifi_debug_dump_prot(int argc, char *argv[]); +static int wifi_debug_set_mode(int argc, char *argv[]); +static int wifi_debug_set_prot(int argc, char *argv[]); +static int wifi_debug_set_autoconnect(int argc, char *argv[]); +#endif + +/* cmd table */ +static const struct wifi_cmd_des cmd_tab[] = { - network_mode = mode; + {"scan", wifi_scan}, + {"help", wifi_help}, + {"status", wifi_status}, + {"join", wifi_join}, + {"ap", wifi_ap}, + {"list_sta", wifi_list_sta}, + {"disc", wifi_disconnect}, + {"ap_stop", wifi_ap_stop}, + {"smartconfig", RT_NULL}, +#ifdef RT_WLAN_CMD_DEBUG + {"-d", wifi_debug}, +#endif +}; - return network_mode; -} - -int wifi_set_setting(const char *ssid, const char *pwd) +#ifdef RT_WLAN_CMD_DEBUG +/* debug cmd table */ +static const struct wifi_cmd_des debug_tab[] = { - if (!ssid) return -1; - - strncpy(wifi_ssid, ssid, sizeof(wifi_ssid)); - wifi_ssid[sizeof(wifi_ssid) - 1] = '\0'; - - if (pwd) - { - strncpy(wifi_key, pwd, sizeof(wifi_key)); - wifi_key[sizeof(wifi_key) - 1] = '\0'; - } - else wifi_key[0] = '\0'; + {"save_cfg", wifi_debug_save_cfg}, + {"dump_cfg", wifi_debug_dump_cfg}, + {"clear_cfg", wifi_debug_clear_cfg}, + {"dump_prot", wifi_debug_dump_prot}, + {"mode", wifi_debug_set_mode}, + {"prot", wifi_debug_set_prot}, + {"auto", wifi_debug_set_autoconnect}, +}; +#endif +static int wifi_help(int argc, char *argv[]) +{ + rt_kprintf("wifi\n"); + rt_kprintf("wifi help\n"); + rt_kprintf("wifi scan\n"); + rt_kprintf("wifi join [SSID] [PASSWORD]\n"); + rt_kprintf("wifi ap SSID [PASSWORD]\n"); + rt_kprintf("wifi disc\n"); + rt_kprintf("wifi ap_stop\n"); + rt_kprintf("wifi status\n"); + rt_kprintf("wifi smartconfig\n"); +#ifdef RT_WLAN_CMD_DEBUG + rt_kprintf("wifi -d debug command\n"); +#endif return 0; } -#ifdef PKG_USING_CJSON -int wifi_read_cfg(const char *filename) +static int wifi_status(int argc, char *argv[]) { - int fd; - cJSON *json = RT_NULL; + int rssi; + struct rt_wlan_info info; - fd = open(filename, O_RDONLY, 0); - if (fd < 0) + if (argc > 2) + return -1; + + if (rt_wlan_is_connected() == 1) + { + rssi = rt_wlan_get_rssi(); + rt_wlan_get_info(&info); + rt_kprintf("Wi-Fi STA Info\n"); + rt_kprintf("SSID : %-.32s\n", &info.ssid.val[0]); + rt_kprintf("MAC Addr: %02x:%02x:%02x:%02x:%02x:%02x\n", info.bssid[0], + info.bssid[1], + info.bssid[2], + info.bssid[3], + info.bssid[4], + info.bssid[5]); + rt_kprintf("Channel: %d\n", info.channel); + rt_kprintf("DataRate: %dMbps\n", info.datarate / 1000000); + rt_kprintf("RSSI: %d\n", rssi); + } + else + { + rt_kprintf("wifi disconnected!\n"); + } + + if (rt_wlan_ap_is_active() == 1) + { + rt_wlan_ap_get_info(&info); + rt_kprintf("Wi-Fi AP Info\n"); + rt_kprintf("SSID : %-.32s\n", &info.ssid.val[0]); + rt_kprintf("MAC Addr: %02x:%02x:%02x:%02x:%02x:%02x\n", info.bssid[0], + info.bssid[1], + info.bssid[2], + info.bssid[3], + info.bssid[4], + info.bssid[5]); + rt_kprintf("Channel: %d\n", info.channel); + rt_kprintf("DataRate: %dMbps\n", info.datarate / 1000000); + rt_kprintf("hidden: %s\n", info.hidden ? "Enable" : "Disable"); + } + else + { + rt_kprintf("wifi ap not start!\n"); + } + rt_kprintf("Auto Connect status:%s!\n", (rt_wlan_get_autoreconnect_mode() ? "Enable" : "Disable")); + return 0; +} + +static int wifi_scan(int argc, char *argv[]) +{ + struct rt_wlan_scan_result *scan_result = RT_NULL; + + if (argc > 2) + return -1; + + /* scan ap info */ + scan_result = rt_wlan_scan_sync(); + if (scan_result) + { + int index, num; + char *security; + + num = scan_result->num; + rt_kprintf(" SSID MAC security rssi chn Mbps\n"); + rt_kprintf("------------------------------- ----------------- -------------- ---- --- ----\n"); + for (index = 0; index < num; index ++) + { + rt_kprintf("%-32.32s", &scan_result->info[index].ssid.val[0]); + rt_kprintf("%02x:%02x:%02x:%02x:%02x:%02x ", + scan_result->info[index].bssid[0], + scan_result->info[index].bssid[1], + scan_result->info[index].bssid[2], + scan_result->info[index].bssid[3], + scan_result->info[index].bssid[4], + scan_result->info[index].bssid[5] + ); + switch (scan_result->info[index].security) + { + case SECURITY_OPEN: + security = "OPEN"; + break; + case SECURITY_WEP_PSK: + security = "WEP_PSK"; + break; + case SECURITY_WEP_SHARED: + security = "WEP_SHARED"; + break; + case SECURITY_WPA_TKIP_PSK: + security = "WPA_TKIP_PSK"; + break; + case SECURITY_WPA_AES_PSK: + security = "WPA_AES_PSK"; + break; + case SECURITY_WPA2_AES_PSK: + security = "WPA2_AES_PSK"; + break; + case SECURITY_WPA2_TKIP_PSK: + security = "WPA2_TKIP_PSK"; + break; + case SECURITY_WPA2_MIXED_PSK: + security = "WPA2_MIXED_PSK"; + break; + case SECURITY_WPS_OPEN: + security = "WPS_OPEN"; + break; + case SECURITY_WPS_SECURE: + security = "WPS_SECURE"; + break; + default: + security = "UNKNOWN"; + break; + } + rt_kprintf("%-14.14s ", security); + rt_kprintf("%-4d ", scan_result->info[index].rssi); + rt_kprintf("%3d ", scan_result->info[index].channel); + rt_kprintf("%4d\n", scan_result->info[index].datarate / 1000000); + } + rt_wlan_scan_result_clean(); + } + else + { + rt_kprintf("wifi scan result is null\n"); + } + return 0; +} + +static int wifi_join(int argc, char *argv[]) +{ + const char *ssid = RT_NULL; + const char *key = RT_NULL; + struct rt_wlan_cfg_info cfg_info; + + if (argc == 2) + { + /* get info to connect */ + if (rt_wlan_cfg_read_index(&cfg_info, 0) == 1) + { + ssid = (char *)(&cfg_info.info.ssid.val[0]); + if (cfg_info.key.len) + key = (char *)(&cfg_info.key.val[0]); + } + else + { + rt_kprintf("not find info\n"); + } + } + else if (argc == 3) + { + /* ssid */ + ssid = argv[2]; + } + else if (argc == 4) + { + ssid = argv[2]; + /* password */ + key = argv[3]; + } + else + { + return -1; + } + rt_wlan_connect(ssid, key); + return 0; +} + +static int wifi_ap(int argc, char *argv[]) +{ + const char *ssid = RT_NULL; + const char *key = RT_NULL; + + if (argc == 3) + { + ssid = argv[2]; + } + else if (argc == 4) + { + ssid = argv[2]; + key = argv[3]; + } + else { - /* no setting file */ return -1; } - if (fd >= 0) - { - int length; - - length = lseek(fd, 0, SEEK_END); - if (length) - { - char *json_str = (char *) rt_malloc(length); - if (json_str) - { - lseek(fd, 0, SEEK_SET); - read(fd, json_str, length); - - json = cJSON_Parse(json_str); - rt_free(json_str); - } - } - close(fd); - } - - if (json) - { - cJSON *wifi = cJSON_GetObjectItem(json, "wifi"); - cJSON *ssid = cJSON_GetObjectItem(wifi, "SSID"); - cJSON *key = cJSON_GetObjectItem(wifi, "Key"); - cJSON *mode = cJSON_GetObjectItem(wifi, "Mode"); - - if (ssid) - { - memset(wifi_ssid, 0x0, sizeof(wifi_ssid)); - rt_strncpy(wifi_ssid, ssid->valuestring, sizeof(wifi_ssid) - 1); - } - - if (key) - { - memset(wifi_key, 0x0, sizeof(wifi_key)); - rt_strncpy(wifi_key, key->valuestring, sizeof(wifi_key) - 1); - } - - if (mode) - { - network_mode = mode->valueint; - } - - cJSON_Delete(json); - } - + rt_wlan_start_ap(ssid, key); return 0; } -int wifi_save_cfg(const char *filename) +static int wifi_list_sta(int argc, char *argv[]) { - int fd; - cJSON *json = RT_NULL; + struct rt_wlan_info *sta_info; + int num, i; - fd = open(filename, O_RDONLY, 0); - if (fd >= 0) + if (argc > 2) + return -1; + num = rt_wlan_ap_get_sta_num(); + sta_info = rt_malloc(sizeof(struct rt_wlan_info) * num); + if (sta_info == RT_NULL) { - int length; - - length = lseek(fd, 0, SEEK_END); - if (length) - { - char *json_str = (char *) rt_malloc(length); - if (json_str) - { - lseek(fd, 0, SEEK_SET); - read(fd, json_str, length); - - json = cJSON_Parse(json_str); - rt_free(json_str); - } - } - close(fd); - } - else - { - /* create a new setting.json */ - fd = open(filename, O_WRONLY | O_TRUNC, 0); - if (fd >= 0) - { - json = cJSON_CreateObject(); - if (json) - { - cJSON *wifi = cJSON_CreateObject(); - - if (wifi) - { - char *json_str; - - cJSON_AddItemToObject(json, "wifi", wifi); - cJSON_AddStringToObject(wifi, "SSID", wifi_ssid); - cJSON_AddStringToObject(wifi, "Key", wifi_key); - cJSON_AddNumberToObject(wifi, "Mode", network_mode); - - json_str = cJSON_Print(json); - if (json_str) - { - write(fd, json_str, rt_strlen(json_str)); - cJSON_free(json_str); - } - } - } - } - close(fd); - + rt_kprintf("num:%d\n", num); return 0; } - - if (json) + rt_wlan_ap_get_sta_info(sta_info, num); + rt_kprintf("num:%d\n", num); + for (i = 0; i < num; i++) { - cJSON *wifi = cJSON_GetObjectItem(json, "wifi"); - if (!wifi) - { - wifi = cJSON_CreateObject(); - cJSON_AddItemToObject(json, "wifi", wifi); - } + rt_kprintf("sta mac %02x:%02x:%02x:%02x:%02x:%02x\n", + sta_info[i].bssid[0], sta_info[i].bssid[1], sta_info[i].bssid[2], + sta_info[i].bssid[3], sta_info[i].bssid[4], sta_info[i].bssid[5]); + } + rt_free(sta_info); + return 0; +} - if (cJSON_GetObjectItem(wifi, "SSID"))cJSON_ReplaceItemInObject(wifi, "SSID", cJSON_CreateString(wifi_ssid)); - else cJSON_AddStringToObject(wifi, "SSID", wifi_ssid); - if (cJSON_GetObjectItem(wifi, "Key")) cJSON_ReplaceItemInObject(wifi, "Key", cJSON_CreateString(wifi_key)); - else cJSON_AddStringToObject(wifi, "Key", wifi_key); - if (cJSON_GetObjectItem(wifi, "Mode")) cJSON_ReplaceItemInObject(wifi, "Mode", cJSON_CreateNumber(network_mode)); - else cJSON_AddNumberToObject(wifi, "Mode", network_mode); - - fd = open(filename, O_WRONLY | O_TRUNC, 0); - if (fd >= 0) - { - char *json_str = cJSON_Print(json); - if (json_str) - { - write(fd, json_str, rt_strlen(json_str)); - cJSON_free(json_str); - } - close(fd); - } - cJSON_Delete(json); +static int wifi_disconnect(int argc, char *argv[]) +{ + if (argc != 2) + { + return -1; } + rt_wlan_disconnect(); return 0; } -#endif -int wifi_save_setting(void) +static int wifi_ap_stop(int argc, char *argv[]) { -#ifdef PKG_USING_CJSON - wifi_save_cfg(WIFI_SETTING_FN); -#endif - - return 0; -} -#endif - -int wifi_softap_setup_netif(struct netif *netif) -{ - if (netif) + if (argc != 2) { -#ifdef RT_LWIP_DHCP - /* Stop DHCP Client */ - dhcp_stop(netif); -#endif - -#ifdef LWIP_USING_DHCPD - { - char name[8]; - memset(name, 0, sizeof(name)); - strncpy(name, netif->name, sizeof(name) > sizeof(netif->name) ? sizeof(netif->name) : sizeof(name)); - dhcpd_start(name); - } -#endif + return -1; } + rt_wlan_ap_stop(); return 0; } -int wifi_default(void) +#ifdef RT_WLAN_CMD_DEBUG +/* just for debug */ +static int wifi_debug_help(int argc, char *argv[]) { - int result = 0; - struct rt_wlan_device *wlan; + rt_kprintf("save_cfg ssid [password]\n"); + rt_kprintf("dump_cfg\n"); + rt_kprintf("clear_cfg\n"); + rt_kprintf("dump_prot\n"); + rt_kprintf("mode sta/ap dev_name\n"); + rt_kprintf("prot lwip dev_name\n"); + rt_kprintf("auto enable/disable\n"); + return 0; +} -#ifdef PKG_USING_CJSON - /* read default setting for wifi */ - wifi_read_cfg(WIFI_SETTING_FN); -#endif +static int wifi_debug_save_cfg(int argc, char *argv[]) +{ + struct rt_wlan_cfg_info cfg_info; + int len; + char *ssid = RT_NULL, *password = RT_NULL; - if (network_mode == WIFI_STATION) + rt_memset(&cfg_info, 0, sizeof(cfg_info)); + INVALID_INFO(&cfg_info.info); + if (argc == 2) { - /* get wlan device */ - wlan = (struct rt_wlan_device *)rt_device_find(WIFI_DEVICE_STA_NAME); - if (!wlan) - { - rt_kprintf("no wlan:%s device\n", WIFI_DEVICE_STA_NAME); - return -1; - } - - /* wifi station */ - rt_wlan_info_init(&info, WIFI_STATION, SECURITY_WPA2_MIXED_PSK, wifi_ssid); - result = rt_wlan_init(wlan, WIFI_STATION); - if (result == RT_EOK) - { - result = rt_wlan_connect(wlan, &info, wifi_key); - } + ssid = argv[1]; + } + else if (argc == 3) + { + ssid = argv[1]; + password = argv[2]; } else { - /* wifi AP */ - /* get wlan device */ - wlan = (struct rt_wlan_device *)rt_device_find(WIFI_DEVICE_AP_NAME); - if (!wlan) - { - rt_kprintf("no wlan:%s device\n", WIFI_DEVICE_AP_NAME); - return -1; - } - - rt_wlan_info_init(&info, WIFI_AP, SECURITY_WPA2_AES_PSK, wifi_ssid); - info.channel = 11; - - /* wifi soft-AP */ - result = rt_wlan_init(wlan, WIFI_AP); - if (result == RT_EOK) - { - result = rt_wlan_softap(wlan, &info, wifi_key); - } + return -1; } - return result; + if (ssid != RT_NULL) + { + len = rt_strlen(ssid); + if (len > RT_WLAN_SSID_MAX_LENGTH) + { + rt_kprintf("ssid is to long"); + return 0; + } + rt_memcpy(&cfg_info.info.ssid.val[0], ssid, len); + cfg_info.info.ssid.len = len; + } + + if (password != RT_NULL) + { + len = rt_strlen(password); + if (len > RT_WLAN_PASSWORD_MAX_LENGTH) + { + rt_kprintf("password is to long"); + return 0; + } + rt_memcpy(&cfg_info.key.val[0], password, len); + cfg_info.key.len = len; + } + + rt_wlan_cfg_save(&cfg_info); + return 0; } -static void wifi_usage(void) +static int wifi_debug_dump_cfg(int argc, char *argv[]) { - rt_kprintf("wifi help - Help information\n"); - rt_kprintf("wifi cfg SSID PASSWORD - Setting your router AP ssid and pwd\n"); - rt_kprintf("wifi - Do the default wifi action\n"); - rt_kprintf("wifi wlan_dev scan\n"); - rt_kprintf("wifi wlan_dev join SSID PASSWORD\n"); - rt_kprintf("wifi wlan_dev ap SSID [PASSWORD]\n"); - rt_kprintf("wifi wlan_dev up\n"); - rt_kprintf("wifi wlan_dev down\n"); - rt_kprintf("wifi wlan_dev rssi\n"); - rt_kprintf("wifi wlan_dev status\n"); -} - -int wifi(int argc, char **argv) -{ - struct rt_wlan_device *wlan; - if (argc == 1) { - wifi_default(); - return 0; + rt_wlan_cfg_dump(); } - - if (strcmp(argv[1], "help") == 0) + else { - wifi_usage(); - return 0; + return -1; } + return 0; +} - if (strcmp(argv[1], "cfg") == 0) +static int wifi_debug_clear_cfg(int argc, char *argv[]) +{ + if (argc == 1) { - /* configure wifi setting */ - memset(wifi_ssid, 0x0, sizeof(wifi_ssid)); - rt_strncpy(wifi_ssid, argv[2], sizeof(wifi_ssid) - 1); - - memset(wifi_key, 0x0, sizeof(wifi_key)); - rt_strncpy(wifi_key, argv[3], sizeof(wifi_key) - 1); - - network_mode = WIFI_STATION; - -#ifdef PKG_USING_CJSON - wifi_save_cfg(WIFI_SETTING_FN); -#endif - - return 0; + rt_wlan_cfg_delete_all(); + rt_wlan_cfg_cache_save(); } - - /* get wlan device */ - wlan = (struct rt_wlan_device *)rt_device_find(argv[1]); - if (!wlan) + else { - rt_kprintf("no wlan:%s device\n", argv[1]); - return 0; + return -1; } + return 0; +} + +static int wifi_debug_dump_prot(int argc, char *argv[]) +{ + if (argc == 1) + { + rt_wlan_prot_dump(); + } + else + { + return -1; + } + return 0; +} + +static int wifi_debug_set_mode(int argc, char *argv[]) +{ + rt_wlan_mode_t mode; + + if (argc != 3) + return -1; + + if (rt_strcmp("sta", argv[1]) == 0) + { + mode = RT_WLAN_STATION; + } + else if (rt_strcmp("ap", argv[1]) == 0) + { + mode = RT_WLAN_AP; + } + else + return -1; + + rt_wlan_set_mode(argv[2], mode); + return 0; +} + +static int wifi_debug_set_prot(int argc, char *argv[]) +{ + if (argc != 3) + { + return -1; + } + + rt_wlan_prot_attach(argv[2], argv[1]); + return 0; +} + +static int wifi_debug_set_autoconnect(int argc, char *argv[]) +{ + if (argc == 2) + { + if (rt_strcmp(argv[1], "enable") == 0) + rt_wlan_config_autoreconnect(RT_TRUE); + else if (rt_strcmp(argv[1], "disable") == 0) + rt_wlan_config_autoreconnect(RT_FALSE); + } + else + { + return -1; + } + return 0; +} + +static int wifi_debug(int argc, char *argv[]) +{ + int i, result = 0; + const struct wifi_cmd_des *run_cmd = RT_NULL; if (argc < 3) { - wifi_usage(); + wifi_debug_help(0, RT_NULL); return 0; } - if (strcmp(argv[2], "join") == 0) + for (i = 0; i < sizeof(debug_tab) / sizeof(debug_tab[0]); i++) { - rt_wlan_init(wlan, WIFI_STATION); - network_mode = WIFI_STATION; - - /* TODO: use easy-join to replace */ - rt_wlan_info_init(&info, WIFI_STATION, SECURITY_WPA2_MIXED_PSK, argv[3]); - rt_wlan_connect(wlan, &info, argv[4]); - rt_wlan_info_deinit(&info); - } - else if (strcmp(argv[2], "up") == 0) - { - /* the key was saved in wlan device */ - rt_wlan_connect(wlan, RT_NULL, wlan->key); - } - else if (strcmp(argv[2], "down") == 0) - { - rt_wlan_disconnect(wlan); - rt_wlan_info_deinit(&info); - } - else if (strcmp(argv[2], "scan") == 0) - { - struct rt_wlan_scan_result *scan_result = RT_NULL; - - rt_wlan_scan(wlan, &scan_result); - if (scan_result) + if (rt_strcmp(debug_tab[i].cmd, argv[2]) == 0) { - int index, num; - - num = scan_result->ap_num; - rt_kprintf(" SSID MAC rssi chn Mbps\n"); - rt_kprintf("------------------------------- ----------------- ---- --- ----\n"); - for (index = 0; index < num; index ++) - { - rt_kprintf("%-32.32s", scan_result->ap_table[index].ssid); - rt_kprintf("%02x:%02x:%02x:%02x:%02x:%02x ", - scan_result->ap_table[index].bssid[0], - scan_result->ap_table[index].bssid[1], - scan_result->ap_table[index].bssid[2], - scan_result->ap_table[index].bssid[3], - scan_result->ap_table[index].bssid[4], - scan_result->ap_table[index].bssid[5] - ); - rt_kprintf("%4d ", scan_result->ap_table[index].rssi); - rt_kprintf("%2d ", scan_result->ap_table[index].channel); - rt_kprintf("%d\n", scan_result->ap_table[index].datarate / 1000000); - } - } - rt_wlan_release_scan_result(&scan_result); - } - else if (strcmp(argv[2], "rssi") == 0) - { - int rssi; - - rssi = rt_wlan_get_rssi(wlan); - rt_kprintf("rssi=%d\n", rssi); - } - else if (strcmp(argv[2], "ap") == 0) - { - rt_err_t result = RT_EOK; - - if (argc == 4) - { - // open soft-AP - rt_wlan_info_init(&info, WIFI_AP, SECURITY_OPEN, argv[3]); - info.channel = 11; - - result = rt_wlan_init(wlan, WIFI_AP); - /* start soft ap */ - result = rt_wlan_softap(wlan, &info, NULL); - if (result == RT_EOK) - { - network_mode = WIFI_AP; - } - } - else if (argc == 5) - { - // WPA2 with password - rt_wlan_info_init(&info, WIFI_AP, SECURITY_WPA2_AES_PSK, argv[3]); - info.channel = 11; - - result = rt_wlan_init(wlan, WIFI_AP); - /* start soft ap */ - result = rt_wlan_softap(wlan, &info, argv[4]); - if (result == RT_EOK) - { - network_mode = WIFI_AP; - } - } - else - { - wifi_usage(); - } - - if (result != RT_EOK) - { - rt_kprintf("wifi start failed! result=%d\n", result); + run_cmd = &debug_tab[i]; + break; } } - else if (strcmp(argv[2], "status") == 0) + + if (run_cmd == RT_NULL) { - int rssi; - - if (netif_is_link_up(wlan->parent.netif)) - { - rssi = rt_wlan_get_rssi(wlan); - - rt_kprintf("Wi-Fi AP: %-.32s\n", wlan->info->ssid); - rt_kprintf("MAC Addr: %02x:%02x:%02x:%02x:%02x:%02x\n", wlan->info->bssid[0], - wlan->info->bssid[1], - wlan->info->bssid[2], - wlan->info->bssid[3], - wlan->info->bssid[4], - wlan->info->bssid[5]); - rt_kprintf(" Channel: %d\n", wlan->info->channel); - rt_kprintf("DataRate: %dMbps\n", wlan->info->datarate / 1000000); - rt_kprintf(" RSSI: %d\n", rssi); - } - else - { - rt_kprintf("wifi disconnected!\n"); - } - + wifi_debug_help(0, RT_NULL); return 0; } + if (run_cmd->fun != RT_NULL) + { + result = run_cmd->fun(argc - 2, &argv[2]); + } + + if (result) + { + wifi_debug_help(argc - 2, &argv[2]); + } return 0; } -MSH_CMD_EXPORT(wifi, wifi command); +#endif + +static int wifi_msh(int argc, char *argv[]) +{ + int i, result = 0; + const struct wifi_cmd_des *run_cmd = RT_NULL; + + if (argc == 1) + { + wifi_help(argc, argv); + return 0; + } + + /* find fun */ + for (i = 0; i < sizeof(cmd_tab) / sizeof(cmd_tab[0]); i++) + { + if (rt_strcmp(cmd_tab[i].cmd, argv[1]) == 0) + { + run_cmd = &cmd_tab[i]; + break; + } + } + + /* not find fun, print help */ + if (run_cmd == RT_NULL) + { + wifi_help(argc, argv); + return 0; + } + + /* run fun */ + if (run_cmd->fun != RT_NULL) + { + result = run_cmd->fun(argc, argv); + } + + if (result) + { + wifi_help(argc, argv); + } + return 0; +} + +#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) +FINSH_FUNCTION_EXPORT_ALIAS(wifi_msh, __cmd_wifi, wifi command.); +#endif diff --git a/components/drivers/wlan/wlan_dev.c b/components/drivers/wlan/wlan_dev.c index a42072692c..387f65fde2 100644 --- a/components/drivers/wlan/wlan_dev.c +++ b/components/drivers/wlan/wlan_dev.c @@ -1,328 +1,767 @@ /* - * RT-Thread Wi-Fi Device + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2014 - 2018, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2014-09-11 Bernard the first verion + * 2018-08-03 tyx the first version */ +#include #include -#include +#include +#include -#include "wlan_dev.h" -#include "wlan_cmd.h" +#define DBG_ENABLE +#ifdef RT_WLAN_DEV_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif +#define DBG_SECTION_NAME "WLAN.dev" +#define DBG_COLOR +#include -#define NIOCTL_SADDR 0x02 +#ifndef RT_DEVICE +#define RT_DEVICE(__device) ((rt_device_t)__device) +#endif -void rt_wlan_info_init(struct rt_wlan_info *info, rt_wlan_mode_t mode, rt_wlan_security_t security, - char *ssid) +#define WLAN_DEV_LOCK(_wlan) (rt_mutex_take(&(_wlan)->lock, RT_WAITING_FOREVER)) +#define WLAN_DEV_UNLOCK(_wlan) (rt_mutex_release(&(_wlan)->lock)) + +#if RT_WLAN_SSID_MAX_LENGTH < 1 +#error "SSID length is too short" +#endif + +#if RT_WLAN_BSSID_MAX_LENGTH < 1 +#error "BSSID length is too short" +#endif + +#if RT_WLAN_PASSWORD_MAX_LENGTH < 1 +#error "password length is too short" +#endif + +#if RT_WLAN_DEV_EVENT_NUM < 2 +#error "dev num Too little" +#endif + +rt_err_t rt_wlan_dev_init(struct rt_wlan_device *device, rt_wlan_mode_t mode) { - if (info == RT_NULL) return ; + rt_err_t result = RT_EOK; - memset(info, 0x0, sizeof(struct rt_wlan_info)); - info->mode = mode; - info->security = security; - if (ssid) + /* init wlan device */ + LOG_D("F:%s L:%d is run device:0x%08x mode:%d", __FUNCTION__, __LINE__, device, mode); + if ((device == RT_NULL) || (mode >= RT_WLAN_MODE_MAX)) { - info->ssid = rt_malloc(strlen((char *)ssid) + 1); - if (info->ssid) + LOG_E("F:%s L:%d Parameter Wrongful device:0x%08x mode:%d", __FUNCTION__, __LINE__, device, mode); + return -RT_ERROR; + } + + result = rt_device_init(RT_DEVICE(device)); + if (result != RT_EOK) + { + LOG_E("L:%d wlan init failed", __LINE__); + return -RT_ERROR; + } + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_MODE, (void *)&mode); + if (result != RT_EOK) + { + LOG_E("L:%d wlan config mode failed", __LINE__); + return -RT_ERROR; + } + device->mode = mode; + return result; +} + +rt_err_t rt_wlan_dev_connect(struct rt_wlan_device *device, struct rt_wlan_info *info, const char *password, int password_len) +{ + rt_err_t result = RT_EOK; + struct rt_sta_info sta_info; + + if (device == RT_NULL) + { + return -RT_EIO; + } + if (info == RT_NULL) + { + return -RT_ERROR; + } + + if ((password_len > RT_WLAN_PASSWORD_MAX_LENGTH) || + (info->ssid.len > RT_WLAN_SSID_MAX_LENGTH)) + { + LOG_E("L:%d password or ssid is to long", __LINE__); + return -RT_ERROR; + } + rt_memset(&sta_info, 0, sizeof(struct rt_sta_info)); + rt_memcpy(&sta_info.ssid, &info->ssid, sizeof(rt_wlan_ssid_t)); + rt_memcpy(sta_info.bssid, info->bssid, RT_WLAN_BSSID_MAX_LENGTH); + if (password != RT_NULL) + { + rt_memcpy(sta_info.key.val, password, password_len); + sta_info.key.len = password_len; + } + sta_info.channel = info->channel; + sta_info.security = info->security; + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_JOIN, &sta_info); + return result; +} + +rt_err_t rt_wlan_dev_disconnect(struct rt_wlan_device *device) +{ + rt_err_t result = RT_EOK; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_DISCONNECT, RT_NULL); + return result; +} + +rt_err_t rt_wlan_dev_ap_start(struct rt_wlan_device *device, struct rt_wlan_info *info, const char *password, int password_len) +{ + rt_err_t result = RT_EOK; + struct rt_ap_info ap_info; + + if (device == RT_NULL) + { + return -RT_EIO; + } + if (info == RT_NULL) + { + return -RT_ERROR; + } + + if ((password_len >= RT_WLAN_PASSWORD_MAX_LENGTH) || + (info->ssid.len >= RT_WLAN_SSID_MAX_LENGTH)) + { + LOG_E("L:%d password or ssid is to long", __LINE__); + return -RT_ERROR; + } + + rt_memset(&ap_info, 0, sizeof(struct rt_ap_info)); + rt_memcpy(&ap_info.ssid, &info->ssid, sizeof(rt_wlan_ssid_t)); + rt_memcpy(ap_info.key.val, password, password_len); + ap_info.key.len = password_len; + ap_info.hidden = info->hidden; + ap_info.channel = info->channel; + ap_info.security = info->security; + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SOFTAP, &ap_info); + return result; +} + +rt_err_t rt_wlan_dev_ap_stop(struct rt_wlan_device *device) +{ + rt_err_t result = RT_EOK; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_AP_STOP, RT_NULL); + return result; +} + +rt_err_t rt_wlan_dev_ap_deauth(struct rt_wlan_device *device, rt_uint8_t mac[6]) +{ + rt_err_t result = RT_EOK; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_AP_DEAUTH, mac); + return result; +} + +int rt_wlan_dev_get_rssi(struct rt_wlan_device *device) +{ + int rssi = 0; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_GET_RSSI, &rssi); + return rssi; +} + +rt_err_t rt_wlan_dev_get_mac(struct rt_wlan_device *device, rt_uint8_t mac[6]) +{ + rt_err_t result = RT_EOK; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_GET_MAC, &mac[0]); + return result; +} + +rt_err_t rt_wlan_dev_set_mac(struct rt_wlan_device *device, rt_uint8_t mac[6]) +{ + rt_err_t result = RT_EOK; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SET_MAC, &mac[0]); + return result; +} + +rt_err_t rt_wlan_dev_set_powersave(struct rt_wlan_device *device, int level) +{ + rt_err_t result = RT_EOK; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SET_POWERSAVE, &level); + return result; +} + +int rt_wlan_dev_get_powersave(struct rt_wlan_device *device) +{ + int level = 0; + + if (device == RT_NULL) + { + return -1; + } + + rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_GET_POWERSAVE, &level); + + return level; +} + +rt_err_t rt_wlan_dev_register_event_handler(struct rt_wlan_device *device, rt_wlan_dev_event_t event, rt_wlan_dev_event_handler handler, void *parameter) +{ + int i = 0; + rt_base_t level; + + if (device == RT_NULL) + { + return -RT_EIO; + } + if (event >= RT_WLAN_DEV_EVT_MAX) + { + return -RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + for (i = 0; i < RT_WLAN_DEV_EVENT_NUM; i++) + { + if (device->handler_table[event][i].handler == RT_NULL) { - strncpy((char *)info->ssid, (char *)ssid, strlen((char *)ssid) + 1); + device->handler_table[event][i].handler = handler; + device->handler_table[event][i].parameter = parameter; + rt_hw_interrupt_enable(level); + return RT_EOK; + } + } + rt_hw_interrupt_enable(level); + + /* No space found */ + return -RT_ERROR; +} + +rt_err_t rt_wlan_dev_unregister_event_handler(struct rt_wlan_device *device, rt_wlan_dev_event_t event, rt_wlan_dev_event_handler handler) +{ + int i = 0; + rt_base_t level; + + if (device == RT_NULL) + { + return -RT_EIO; + } + if (event >= RT_WLAN_DEV_EVT_MAX) + { + return -RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + for (i = 0; i < RT_WLAN_DEV_EVENT_NUM; i++) + { + if (device->handler_table[event][i].handler == handler) + { + rt_memset(&device->handler_table[event][i], 0, sizeof(struct rt_wlan_dev_event_desc)); + rt_hw_interrupt_enable(level); + return RT_EOK; + } + } + rt_hw_interrupt_enable(level); + /* not find iteam */ + return -RT_ERROR; +} + +void rt_wlan_dev_indicate_event_handle(struct rt_wlan_device *device, rt_wlan_dev_event_t event, struct rt_wlan_buff *buff) +{ + void *parameter[RT_WLAN_DEV_EVENT_NUM]; + rt_wlan_dev_event_handler handler[RT_WLAN_DEV_EVENT_NUM]; + int i; + rt_base_t level; + + if (device == RT_NULL) + { + return; + } + if (event >= RT_WLAN_DEV_EVT_MAX) + { + return; + } + + /* get callback handle */ + level = rt_hw_interrupt_disable(); + for (i = 0; i < RT_WLAN_DEV_EVENT_NUM; i++) + { + handler[i] = device->handler_table[event][i].handler; + parameter[i] = device->handler_table[event][i].parameter; + } + rt_hw_interrupt_enable(level); + + /* run callback */ + for (i = 0; i < RT_WLAN_DEV_EVENT_NUM; i++) + { + if (handler[i] != RT_NULL) + { + handler[i](device, event, buff, parameter[i]); } } } -void rt_wlan_info_deinit(struct rt_wlan_info *info) +rt_err_t rt_wlan_dev_enter_promisc(struct rt_wlan_device *device) { - if (info->ssid) + rt_err_t result = RT_EOK; + int enable = 1; + + if (device == RT_NULL) { - rt_free(info->ssid); - info->ssid = RT_NULL; + return -RT_EIO; } - memset(info, 0x0, sizeof(struct rt_wlan_info)); -} - -int rt_wlan_init(struct rt_wlan_device *device, rt_wlan_mode_t mode) -{ - int result; - - if (device == RT_NULL) return 0; - - if (device->info == RT_NULL) - { - struct rt_wlan_info *info; - char *ssid; - - info = rt_malloc(sizeof(struct rt_wlan_info)); - if (info) - { - ssid = rt_malloc(SSID_LENGTH_MAX_SIZE); - info->ssid = ssid; - } - device->info = info; - } - - result = rt_device_control(RT_DEVICE(device), WIFI_INIT, (void *)&mode); - + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_CFG_PROMISC, &enable); return result; } -int rt_wlan_connect(struct rt_wlan_device *device, struct rt_wlan_info *info, char *password) +rt_err_t rt_wlan_dev_exit_promisc(struct rt_wlan_device *device) { - int result = 0; + rt_err_t result = RT_EOK; + int enable = 0; - if (device == RT_NULL) return -RT_EIO; - - if (info != RT_NULL) + if (device == RT_NULL) { - rt_wlan_set_info(device, info); + return -RT_EIO; } - rt_strncpy((char *)device->key, (char *)password, sizeof(device->key) - 1); - - result = rt_device_control(RT_DEVICE(device), WIFI_EASYJOIN, (void *)password); - + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_CFG_PROMISC, &enable); return result; } -int rt_wlan_softap(struct rt_wlan_device *device, struct rt_wlan_info *info, char *password) +rt_err_t rt_wlan_dev_set_promisc_callback(struct rt_wlan_device *device, rt_wlan_pormisc_callback_t callback) { - int result = RT_EOK; - - if (device == RT_NULL) return -RT_EIO; - - if (info != RT_NULL) + if (device == RT_NULL) { - rt_wlan_set_info(device, info); + return -RT_EIO; } - - if (password == NULL) - { - memset(device->key, 0, sizeof(device->key)); - } - else - { - if (rt_strlen(password) > sizeof(device->key) - 1) - { - rt_kprintf("WARN input password is longer than %d bytes.", sizeof(device->key) - 1); - } - rt_strncpy((char *)device->key, (char *)password, sizeof(device->key) - 1); - } - - result = rt_device_control(RT_DEVICE(device), WIFI_SOFTAP, (void *)password); - - return result; -} - -int rt_wlan_disconnect(struct rt_wlan_device *device) -{ - int result = 0; - - if (device == RT_NULL) return -RT_EIO; - - /* save event handler */ - result = rt_device_control(RT_DEVICE(device), WIFI_DISCONNECT, RT_NULL); - - return result; -} - -int rt_wlan_set_info(struct rt_wlan_device *device, struct rt_wlan_info *info) -{ - if (device == RT_NULL) return -RT_EIO; - if (device->info == RT_NULL) return -RT_EIO; - - device->info->mode = info->mode; - device->info->security = info->security; - memset(device->info->ssid, 0, SSID_LENGTH_MAX_SIZE); - memcpy(device->info->ssid, info->ssid, strlen(info->ssid)); - memcpy(device->info->bssid, info->bssid, 6); - device->info->datarate = info->datarate; - device->info->channel = info->channel; - device->info->rssi = info->rssi; + device->pormisc_callback = callback; return RT_EOK; } -struct rt_wlan_info *rt_wlan_get_info(struct rt_wlan_device *device) +void rt_wlan_dev_promisc_handler(struct rt_wlan_device *device, void *data, int len) { - struct rt_wlan_info *info = RT_NULL; + rt_wlan_pormisc_callback_t callback; - if (device != RT_NULL) + if (device == RT_NULL) { - info = device->info; + return; } - return info; + callback = device->pormisc_callback; + + if (callback != RT_NULL) + { + callback(device, data, len); + } } -int rt_wlan_scan(struct rt_wlan_device *device, struct rt_wlan_scan_result **scan_result) +rt_err_t rt_wlan_dev_cfg_filter(struct rt_wlan_device *device, struct rt_wlan_filter *filter) { - int result; + rt_err_t result = RT_EOK; - result = rt_device_control(RT_DEVICE(device), WIFI_SCAN, scan_result); + if (device == RT_NULL) + { + return -RT_EIO; + } + if (filter == RT_NULL) + { + return -RT_ERROR; + } + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_CFG_FILTER, filter); return result; } -int rt_wlan_get_rssi(struct rt_wlan_device *device) +rt_err_t rt_wlan_dev_set_channel(struct rt_wlan_device *device, int channel) { - int rssi; - int result; + rt_err_t result = RT_EOK; - if (device == RT_NULL) return 0; - result = rt_device_control(RT_DEVICE(device), WIFI_GET_RSSI, (void *)&rssi); - - if (result == RT_EOK) return rssi; + if (device == RT_NULL) + { + return -RT_EIO; + } + if (channel < 0) + { + return -RT_ERROR; + } + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SET_CHANNEL, &channel); return result; } -int rt_wlan_get_mac(struct rt_wlan_device *device, rt_uint8_t hwaddr[6]) +rt_err_t rt_wlan_dev_get_channel(struct rt_wlan_device *device) { - int result; - if (device == RT_NULL) return 0; - result = rt_device_control(RT_DEVICE(device), NIOCTL_GADDR, (void *)hwaddr); - return result; -} + rt_err_t result = RT_EOK; + int channel; -int rt_wlan_set_mac(struct rt_wlan_device *device, rt_uint8_t hwaddr[6]) -{ - int result; - if (device == RT_NULL) return 0; - result = rt_device_control(RT_DEVICE(device), NIOCTL_SADDR, (void *)hwaddr); - return result; -} + if (device == RT_NULL) + { + return -RT_EIO; + } -int rt_wlan_enter_powersave(struct rt_wlan_device *device, int level) -{ - int result = 0; - - if (device == RT_NULL) return -RT_EIO; - - result = rt_device_control(RT_DEVICE(device), WIFI_ENTER_POWERSAVE, (void *)&level); - - return result; -} - -int rt_wlan_register_event_handler(struct rt_wlan_device *device, rt_wlan_event_t event, - rt_wlan_event_handler handler) -{ - if (device == RT_NULL) return -RT_EIO; - if (event >= WIFI_EVT_MAX) return -RT_EINVAL; - - device->handler[event] = handler; - - return RT_EOK; -} - -int rt_wlan_unregister_event_handler(struct rt_wlan_device *device, rt_wlan_event_t event) -{ - if (device == RT_NULL) return -RT_EIO; - if (event >= WIFI_EVT_MAX) return -RT_EINVAL; - - device->handler[event] = RT_NULL; - - return RT_EOK; -} - -int rt_wlan_indicate_event_handle(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - if (device == RT_NULL) return -RT_EIO; - if (event >= WIFI_EVT_MAX) return -RT_EINVAL; - - if (device->handler[event] != RT_NULL) - device->handler[event](device, event, user_data); - - return RT_EOK; -} - -int rt_wlan_cfg_monitor(struct rt_wlan_device *device, rt_wlan_monitor_opition_t opition) -{ - int result = 0; - - if (device == RT_NULL) return -RT_EIO; - - result = rt_device_control(RT_DEVICE(device), WIFI_CFG_MONITOR, (void *)&opition); - - return result; -} - -int rt_wlan_set_monitor_callback(struct rt_wlan_device *device, rt_wlan_monitor_callback_t callback) -{ - int result = 0; - - if (device == RT_NULL) return -RT_EIO; - - result = rt_device_control(RT_DEVICE(device), WIFI_SET_MONITOR_CALLBACK, (void *)callback); - - return result; -} - -int rt_wlan_set_channel(struct rt_wlan_device *device, int channel) -{ - int result = 0; - - if (device == RT_NULL) return -RT_EIO; - - result = rt_device_control(RT_DEVICE(device), WIFI_SET_CHANNEL, (void *)&channel); - - return result; -} - -int rt_wlan_get_channel(struct rt_wlan_device *device) -{ - int channel = 0; - - if (device == RT_NULL) return -RT_EIO; - - rt_device_control(RT_DEVICE(device), WIFI_GET_CHANNEL, &channel); + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_GET_CHANNEL, &channel); + if (result != RT_EOK) + { + return -1; + } return channel; } -void rt_wlan_release_scan_result(struct rt_wlan_scan_result **scan_result) +rt_err_t rt_wlan_dev_set_country(struct rt_wlan_device *device, rt_country_code_t country_code) { - int i, ap_num; - struct rt_wlan_scan_result *_scan_result; + int result = RT_EOK; - if (*scan_result != RT_NULL) + if (device == RT_NULL) { - _scan_result = *scan_result; - ap_num = _scan_result->ap_num; - for (i = 0; i < ap_num; i++) - { - if (_scan_result->ap_table[i].ssid != RT_NULL) - { - rt_free(_scan_result->ap_table[i].ssid); - _scan_result->ap_table[i].ssid = RT_NULL; - } - } - _scan_result->ap_num = 0; - rt_free(_scan_result->ap_table); - _scan_result->ap_table = RT_NULL; + return -RT_EIO; } - rt_free(*scan_result); - *scan_result = RT_NULL; - scan_result = RT_NULL; + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SET_COUNTRY, &country_code); + return result; +} + +rt_country_code_t rt_wlan_dev_get_country(struct rt_wlan_device *device) +{ + int result = 0; + rt_country_code_t country_code = RT_COUNTRY_UNKNOWN; + + if (device == RT_NULL) + { + return country_code; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_GET_COUNTRY, &country_code); + if (result != RT_EOK) + { + return RT_COUNTRY_UNKNOWN; + } + + return country_code; +} + +rt_err_t rt_wlan_dev_scan(struct rt_wlan_device *device, struct rt_wlan_info *info) +{ + struct rt_scan_info scan_info = { 0 }; + struct rt_scan_info *p_scan_info = RT_NULL; + rt_err_t result = 0; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + if (info != RT_NULL) + { + if (info->ssid.len >= RT_WLAN_SSID_MAX_LENGTH) + { + LOG_E("L:%d ssid is to long", __LINE__); + return -RT_EINVAL; + } + rt_memcpy(&scan_info.ssid, &info->ssid, sizeof(rt_wlan_ssid_t)); + rt_memcpy(scan_info.bssid, info->bssid, RT_WLAN_BSSID_MAX_LENGTH); + scan_info.channel_min = -1; + scan_info.channel_max = -1; + p_scan_info = &scan_info; + } + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SCAN, p_scan_info); + return result; +} + +rt_err_t rt_wlan_dev_scan_stop(struct rt_wlan_device *device) +{ + rt_err_t result = 0; + + if (device == RT_NULL) + { + return -RT_EIO; + } + + result = rt_device_control(RT_DEVICE(device), RT_WLAN_CMD_SCAN_STOP, RT_NULL); + return result; +} + +rt_err_t rt_wlan_dev_report_data(struct rt_wlan_device *device, void *buff, int len) +{ + return rt_wlan_dev_transfer_prot(device, buff, len); +} + +static rt_err_t _rt_wlan_dev_init(rt_device_t dev) +{ + struct rt_wlan_device *wlan = (struct rt_wlan_device *)dev; + rt_err_t result = RT_EOK; + + rt_mutex_init(&wlan->lock, "wlan_dev", RT_IPC_FLAG_FIFO); + + if (wlan->ops->wlan_init) + result = wlan->ops->wlan_init(wlan); + + if (result == RT_EOK) + { + LOG_I("wlan init success"); + } + else + { + LOG_I("wlan init failed"); + } + + return result; +} + +static rt_err_t _rt_wlan_dev_control(rt_device_t dev, int cmd, void *args) +{ + struct rt_wlan_device *wlan = (struct rt_wlan_device *)dev; + rt_err_t err = RT_EOK; + + RT_ASSERT(dev != RT_NULL); + + WLAN_DEV_LOCK(wlan); + + switch (cmd) + { + case RT_WLAN_CMD_MODE: + { + rt_wlan_mode_t mode = *((rt_wlan_mode_t *)args); + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_MODE, "RT_WLAN_CMD_MODE"); + if (wlan->ops->wlan_mode) + err = wlan->ops->wlan_mode(wlan, mode); + break; + } + case RT_WLAN_CMD_SCAN: + { + struct rt_scan_info *scan_info = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SCAN, "RT_WLAN_CMD_SCAN"); + if (wlan->ops->wlan_scan) + err = wlan->ops->wlan_scan(wlan, scan_info); + break; + } + case RT_WLAN_CMD_JOIN: + { + struct rt_sta_info *sta_info = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_JOIN, "RT_WLAN_CMD_JOIN"); + if (wlan->ops->wlan_join) + err = wlan->ops->wlan_join(wlan, sta_info); + break; + } + case RT_WLAN_CMD_SOFTAP: + { + struct rt_ap_info *ap_info = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SOFTAP, "RT_WLAN_CMD_SOFTAP"); + if (wlan->ops->wlan_softap) + err = wlan->ops->wlan_softap(wlan, ap_info); + break; + } + case RT_WLAN_CMD_DISCONNECT: + { + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_DISCONNECT, "RT_WLAN_CMD_DISCONNECT"); + if (wlan->ops->wlan_disconnect) + err = wlan->ops->wlan_disconnect(wlan); + break; + } + case RT_WLAN_CMD_AP_STOP: + { + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_AP_STOP, "RT_WLAN_CMD_AP_STOP"); + if (wlan->ops->wlan_ap_stop) + err = wlan->ops->wlan_ap_stop(wlan); + break; + } + case RT_WLAN_CMD_AP_DEAUTH: + { + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_AP_DEAUTH, "RT_WLAN_CMD_AP_DEAUTH"); + if (wlan->ops->wlan_ap_deauth) + err = wlan->ops->wlan_ap_deauth(wlan, args); + break; + } + case RT_WLAN_CMD_SCAN_STOP: + { + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SCAN_STOP, "RT_WLAN_CMD_SCAN_STOP"); + if (wlan->ops->wlan_scan_stop) + err = wlan->ops->wlan_scan_stop(wlan); + break; + } + case RT_WLAN_CMD_GET_RSSI: + { + int *rssi = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_RSSI, "RT_WLAN_CMD_GET_RSSI"); + if (wlan->ops->wlan_get_rssi) + *rssi = wlan->ops->wlan_get_rssi(wlan); + break; + } + case RT_WLAN_CMD_SET_POWERSAVE: + { + int level = *((int *)args); + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SET_POWERSAVE, "RT_WLAN_CMD_SET_POWERSAVE"); + if (wlan->ops->wlan_set_powersave) + wlan->ops->wlan_set_powersave(wlan, level); + break; + } + case RT_WLAN_CMD_GET_POWERSAVE: + { + int *level = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_POWERSAVE, "RT_WLAN_CMD_GET_POWERSAVE"); + if (wlan->ops->wlan_get_powersave) + *level = wlan->ops->wlan_get_powersave(wlan); + break; + } + case RT_WLAN_CMD_CFG_PROMISC: + { + rt_bool_t start = *((rt_bool_t *)args); + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_CFG_PROMISC, "RT_WLAN_CMD_CFG_PROMISC"); + if (wlan->ops->wlan_cfg_promisc) + wlan->ops->wlan_cfg_promisc(wlan, start); + break; + } + case RT_WLAN_CMD_CFG_FILTER: + { + struct rt_wlan_filter *filter = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_CFG_FILTER, "RT_WLAN_CMD_CFG_FILTER"); + if (wlan->ops->wlan_cfg_filter) + wlan->ops->wlan_cfg_filter(wlan, filter); + break; + } + case RT_WLAN_CMD_SET_CHANNEL: + { + int channel = *(int *)args; + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SET_CHANNEL, "RT_WLAN_CMD_SET_CHANNEL"); + if (wlan->ops->wlan_set_channel) + wlan->ops->wlan_set_channel(wlan, channel); + break; + } + case RT_WLAN_CMD_GET_CHANNEL: + { + int *channel = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_CHANNEL, "RT_WLAN_CMD_GET_CHANNEL"); + if (wlan->ops->wlan_get_channel) + *channel = wlan->ops->wlan_get_channel(wlan); + break; + } + case RT_WLAN_CMD_SET_COUNTRY: + { + rt_country_code_t country = *(rt_country_code_t *)args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SET_COUNTRY, "RT_WLAN_CMD_SET_COUNTRY"); + if (wlan->ops->wlan_set_country) + wlan->ops->wlan_set_country(wlan, country); + break; + } + case RT_WLAN_CMD_GET_COUNTRY: + { + rt_country_code_t *country = args; + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_COUNTRY, "RT_WLAN_CMD_GET_COUNTRY"); + if (wlan->ops->wlan_get_country) + *country = wlan->ops->wlan_get_country(wlan); + break; + } + case RT_WLAN_CMD_SET_MAC: + { + rt_uint8_t *mac = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_SET_MAC, "RT_WLAN_CMD_SET_MAC"); + if (wlan->ops->wlan_set_mac) + wlan->ops->wlan_set_mac(wlan, mac); + break; + } + case RT_WLAN_CMD_GET_MAC: + { + rt_uint8_t *mac = args; + + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_MAC, "RT_WLAN_CMD_GET_MAC"); + if (wlan->ops->wlan_get_mac) + wlan->ops->wlan_get_mac(wlan, mac); + break; + } + default: + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, -1, "UNKUOWN"); + break; + } + + WLAN_DEV_UNLOCK(wlan); + + return err; +} + +rt_err_t rt_wlan_dev_register(struct rt_wlan_device *wlan, const char *name, const struct rt_wlan_dev_ops *ops, rt_uint32_t flag, void *user_data) +{ + rt_err_t err = RT_EOK; + + if ((wlan == RT_NULL) || (name == RT_NULL) || (ops == RT_NULL)) + { + LOG_E("F:%s L:%d parameter Wrongful", __FUNCTION__, __LINE__); + return RT_NULL; + } + + rt_memset(wlan, 0, sizeof(struct rt_wlan_device)); + + wlan->device.init = _rt_wlan_dev_init; + wlan->device.open = RT_NULL; + wlan->device.close = RT_NULL; + wlan->device.read = RT_NULL; + wlan->device.write = RT_NULL; + wlan->device.control = _rt_wlan_dev_control; + wlan->device.user_data = RT_NULL; + + wlan->device.type = RT_Device_Class_NetIf; + + wlan->ops = ops; + wlan->user_data = user_data; + + wlan->flags = flag; + err = rt_device_register(&wlan->device, name, RT_DEVICE_FLAG_RDWR); + + LOG_D("F:%s L:%d run", __FUNCTION__, __LINE__); + + return err; } diff --git a/components/drivers/wlan/wlan_dev.h b/components/drivers/wlan/wlan_dev.h index df7244fd6f..e3f0d3dc61 100644 --- a/components/drivers/wlan/wlan_dev.h +++ b/components/drivers/wlan/wlan_dev.h @@ -1,72 +1,66 @@ /* - * RT-Thread Wi-Fi Device + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2014 - 2018, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2014-09-11 Bernard the first verion + * 2018-08-03 tyx the first version */ -#ifndef WIFI_DEVICE_H__ -#define WIFI_DEVICE_H__ +#ifndef __WLAN_DEVICE_H__ +#define __WLAN_DEVICE_H__ -#include -#include +#ifdef __cplusplus +extern "C" { +#endif typedef enum { - WIFI_NONE, - WIFI_STATION, - WIFI_AP, + RT_WLAN_NONE, + RT_WLAN_STATION, + RT_WLAN_AP, + RT_WLAN_MODE_MAX } rt_wlan_mode_t; typedef enum { - WIFI_INIT = 0x10, - WIFI_SCAN, /* trigger scanning (list cells) */ - WIFI_JOIN, - WIFI_EASYJOIN, /* join network with less information */ - WIFI_SOFTAP, /* start soft-AP */ - WIFI_DISCONNECT, - WIFI_GET_RSSI, /* get sensitivity (dBm) */ - WIFI_ENTER_POWERSAVE, - WIFI_CFG_MONITOR, /* start/stop minitor */ - WIFI_SET_CHANNEL, - WIFI_GET_CHANNEL, - WIFI_SET_MONITOR_CALLBACK, + RT_WLAN_CMD_MODE = 0x10, + RT_WLAN_CMD_SCAN, /* trigger scanning (list cells) */ + RT_WLAN_CMD_JOIN, + RT_WLAN_CMD_SOFTAP, /* start soft-AP */ + RT_WLAN_CMD_DISCONNECT, + RT_WLAN_CMD_AP_STOP, /* stop soft-AP */ + RT_WLAN_CMD_AP_DEAUTH, + RT_WLAN_CMD_SCAN_STOP, + RT_WLAN_CMD_GET_RSSI, /* get sensitivity (dBm) */ + RT_WLAN_CMD_SET_POWERSAVE, + RT_WLAN_CMD_GET_POWERSAVE, + RT_WLAN_CMD_CFG_PROMISC, /* start/stop minitor */ + RT_WLAN_CMD_CFG_FILTER, + RT_WLAN_CMD_SET_CHANNEL, + RT_WLAN_CMD_GET_CHANNEL, + RT_WLAN_CMD_SET_COUNTRY, + RT_WLAN_CMD_GET_COUNTRY, + RT_WLAN_CMD_SET_MAC, + RT_WLAN_CMD_GET_MAC } rt_wlan_cmd_t; typedef enum { - WIFI_PWR_OFF, - WIFI_PWR_SLEEP, - WIFI_PWR_NORMAL -} rt_wlan_powersave_t; - -typedef enum -{ - WIFI_MONITOR_START, - WIFI_MONITOR_STOP -} rt_wlan_monitor_opition_t; + RT_WLAN_DEV_EVT_INIT_DONE = 0, + RT_WLAN_DEV_EVT_CONNECT, + RT_WLAN_DEV_EVT_CONNECT_FAIL, + RT_WLAN_DEV_EVT_DISCONNECT, + RT_WLAN_DEV_EVT_AP_START, + RT_WLAN_DEV_EVT_AP_STOP, + RT_WLAN_DEV_EVT_AP_ASSOCIATED, + RT_WLAN_DEV_EVT_AP_DISASSOCIATED, + RT_WLAN_DEV_EVT_AP_ASSOCIATE_FAILED, + RT_WLAN_DEV_EVT_SCAN_REPORT, + RT_WLAN_DEV_EVT_SCAN_DONE, + RT_WLAN_DEV_EVT_MAX, +} rt_wlan_dev_event_t; #define SHARED_ENABLED 0x00008000 #define WPA_SECURITY 0x00200000 @@ -77,144 +71,516 @@ typedef enum #define AES_ENABLED 0x0004 #define WSEC_SWFLAG 0x0008 -#define KEY_ARRAY_SIZE 32 -#define SSID_LENGTH_MAX_SIZE 32 + 1 +#define RT_WLAN_FLAG_STA_ONLY (0x1 << 0) +#define RT_WLAN_FLAG_AP_ONLY (0x1 << 1) + +#ifndef RT_WLAN_SSID_MAX_LENGTH +#define RT_WLAN_SSID_MAX_LENGTH (32) /* SSID MAX LEN */ +#endif + +#ifndef RT_WLAN_BSSID_MAX_LENGTH +#define RT_WLAN_BSSID_MAX_LENGTH (6) /* BSSID MAX LEN (default is 6) */ +#endif + +#ifndef RT_WLAN_PASSWORD_MAX_LENGTH +#define RT_WLAN_PASSWORD_MAX_LENGTH (32) /* PASSWORD MAX LEN*/ +#endif + +#ifndef RT_WLAN_DEV_EVENT_NUM +#define RT_WLAN_DEV_EVENT_NUM (2) /* EVENT GROUP MAX NUM */ +#endif + /** * Enumeration of Wi-Fi security modes */ typedef enum { - SECURITY_OPEN = 0, /**< Open security */ - SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */ - SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /**< WEP Security with shared authentication */ - SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /**< WPA Security with TKIP */ - SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /**< WPA Security with AES */ - SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /**< WPA2 Security with AES */ - SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 Security with TKIP */ - SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 Security with AES & TKIP */ - SECURITY_WPS_OPEN = WPS_ENABLED, /**< WPS with open security */ - SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */ - SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. - Do not pass this to the join function! */ + SECURITY_OPEN = 0, /* Open security */ + SECURITY_WEP_PSK = WEP_ENABLED, /* WEP Security with open authentication */ + SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /* WEP Security with shared authentication */ + SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /* WPA Security with TKIP */ + SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /* WPA Security with AES */ + SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /* WPA2 Security with AES */ + SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /* WPA2 Security with TKIP */ + SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /* WPA2 Security with AES & TKIP */ + SECURITY_WPS_OPEN = WPS_ENABLED, /* WPS with open security */ + SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /* WPS with AES security */ + SECURITY_UNKNOWN = -1, /* May be returned by scan function if security is unknown. + Do not pass this to the join function! */ } rt_wlan_security_t; typedef enum { - WIFI_EVT_INIT_DONE = 0, - WIFI_EVT_LINK_DOWN, - WIFI_EVT_LINK_UP, - WIFI_EVT_CONNECT, - WIFI_EVT_DISCONNECT, - WIFI_EVT_AP_START, - WIFI_EVT_AP_STOP, - WIFI_EVENT_STA_ASSOC, - WIFI_EVENT_STA_DISASSOC, - WIFI_EVT_SCAN_DONE, - WIFI_EVT_MAX, -} rt_wlan_event_t; + RT_802_11_BAND_5GHZ = 0, /* Denotes 5GHz radio band */ + RT_802_11_BAND_2_4GHZ = 1, /* Denotes 2.4GHz radio band */ + RT_802_11_BAND_UNKNOWN = 0x7fffffff, /* unknown */ +} rt_802_11_band_t; -/* wifi network information */ -struct rt_wlan_info +typedef enum { - rt_wlan_mode_t mode; /* wifi mode */ - rt_wlan_security_t security; - - char *ssid; - uint8_t bssid[6]; - - /* maximal data rate */ - uint32_t datarate; - /* radio channel */ - uint16_t channel; - /* signal strength */ - int16_t rssi; -}; - -struct rt_wlan_info_request -{ - uint16_t req_number; /* the number of information item for request */ - uint16_t rsp_number; /* the number of information item for response */ - - struct rt_wlan_info *infos;/* the array of information to save response */ -}; - -typedef struct rt_wlan_scan_result -{ - char ap_num; - struct rt_wlan_info *ap_table; -} rt_wlan_scan_result_t; + RT_COUNTRY_AFGHANISTAN, + RT_COUNTRY_ALBANIA, + RT_COUNTRY_ALGERIA, + RT_COUNTRY_AMERICAN_SAMOA, + RT_COUNTRY_ANGOLA, + RT_COUNTRY_ANGUILLA, + RT_COUNTRY_ANTIGUA_AND_BARBUDA, + RT_COUNTRY_ARGENTINA, + RT_COUNTRY_ARMENIA, + RT_COUNTRY_ARUBA, + RT_COUNTRY_AUSTRALIA, + RT_COUNTRY_AUSTRIA, + RT_COUNTRY_AZERBAIJAN, + RT_COUNTRY_BAHAMAS, + RT_COUNTRY_BAHRAIN, + RT_COUNTRY_BAKER_ISLAND, + RT_COUNTRY_BANGLADESH, + RT_COUNTRY_BARBADOS, + RT_COUNTRY_BELARUS, + RT_COUNTRY_BELGIUM, + RT_COUNTRY_BELIZE, + RT_COUNTRY_BENIN, + RT_COUNTRY_BERMUDA, + RT_COUNTRY_BHUTAN, + RT_COUNTRY_BOLIVIA, + RT_COUNTRY_BOSNIA_AND_HERZEGOVINA, + RT_COUNTRY_BOTSWANA, + RT_COUNTRY_BRAZIL, + RT_COUNTRY_BRITISH_INDIAN_OCEAN_TERRITORY, + RT_COUNTRY_BRUNEI_DARUSSALAM, + RT_COUNTRY_BULGARIA, + RT_COUNTRY_BURKINA_FASO, + RT_COUNTRY_BURUNDI, + RT_COUNTRY_CAMBODIA, + RT_COUNTRY_CAMEROON, + RT_COUNTRY_CANADA, + RT_COUNTRY_CAPE_VERDE, + RT_COUNTRY_CAYMAN_ISLANDS, + RT_COUNTRY_CENTRAL_AFRICAN_REPUBLIC, + RT_COUNTRY_CHAD, + RT_COUNTRY_CHILE, + RT_COUNTRY_CHINA, + RT_COUNTRY_CHRISTMAS_ISLAND, + RT_COUNTRY_COLOMBIA, + RT_COUNTRY_COMOROS, + RT_COUNTRY_CONGO, + RT_COUNTRY_CONGO_THE_DEMOCRATIC_REPUBLIC_OF_THE, + RT_COUNTRY_COSTA_RICA, + RT_COUNTRY_COTE_DIVOIRE, + RT_COUNTRY_CROATIA, + RT_COUNTRY_CUBA, + RT_COUNTRY_CYPRUS, + RT_COUNTRY_CZECH_REPUBLIC, + RT_COUNTRY_DENMARK, + RT_COUNTRY_DJIBOUTI, + RT_COUNTRY_DOMINICA, + RT_COUNTRY_DOMINICAN_REPUBLIC, + RT_COUNTRY_DOWN_UNDER, + RT_COUNTRY_ECUADOR, + RT_COUNTRY_EGYPT, + RT_COUNTRY_EL_SALVADOR, + RT_COUNTRY_EQUATORIAL_GUINEA, + RT_COUNTRY_ERITREA, + RT_COUNTRY_ESTONIA, + RT_COUNTRY_ETHIOPIA, + RT_COUNTRY_FALKLAND_ISLANDS_MALVINAS, + RT_COUNTRY_FAROE_ISLANDS, + RT_COUNTRY_FIJI, + RT_COUNTRY_FINLAND, + RT_COUNTRY_FRANCE, + RT_COUNTRY_FRENCH_GUINA, + RT_COUNTRY_FRENCH_POLYNESIA, + RT_COUNTRY_FRENCH_SOUTHERN_TERRITORIES, + RT_COUNTRY_GABON, + RT_COUNTRY_GAMBIA, + RT_COUNTRY_GEORGIA, + RT_COUNTRY_GERMANY, + RT_COUNTRY_GHANA, + RT_COUNTRY_GIBRALTAR, + RT_COUNTRY_GREECE, + RT_COUNTRY_GRENADA, + RT_COUNTRY_GUADELOUPE, + RT_COUNTRY_GUAM, + RT_COUNTRY_GUATEMALA, + RT_COUNTRY_GUERNSEY, + RT_COUNTRY_GUINEA, + RT_COUNTRY_GUINEA_BISSAU, + RT_COUNTRY_GUYANA, + RT_COUNTRY_HAITI, + RT_COUNTRY_HOLY_SEE_VATICAN_CITY_STATE, + RT_COUNTRY_HONDURAS, + RT_COUNTRY_HONG_KONG, + RT_COUNTRY_HUNGARY, + RT_COUNTRY_ICELAND, + RT_COUNTRY_INDIA, + RT_COUNTRY_INDONESIA, + RT_COUNTRY_IRAN_ISLAMIC_REPUBLIC_OF, + RT_COUNTRY_IRAQ, + RT_COUNTRY_IRELAND, + RT_COUNTRY_ISRAEL, + RT_COUNTRY_ITALY, + RT_COUNTRY_JAMAICA, + RT_COUNTRY_JAPAN, + RT_COUNTRY_JERSEY, + RT_COUNTRY_JORDAN, + RT_COUNTRY_KAZAKHSTAN, + RT_COUNTRY_KENYA, + RT_COUNTRY_KIRIBATI, + RT_COUNTRY_KOREA_REPUBLIC_OF, + RT_COUNTRY_KOSOVO, + RT_COUNTRY_KUWAIT, + RT_COUNTRY_KYRGYZSTAN, + RT_COUNTRY_LAO_PEOPLES_DEMOCRATIC_REPUBIC, + RT_COUNTRY_LATVIA, + RT_COUNTRY_LEBANON, + RT_COUNTRY_LESOTHO, + RT_COUNTRY_LIBERIA, + RT_COUNTRY_LIBYAN_ARAB_JAMAHIRIYA, + RT_COUNTRY_LIECHTENSTEIN, + RT_COUNTRY_LITHUANIA, + RT_COUNTRY_LUXEMBOURG, + RT_COUNTRY_MACAO, + RT_COUNTRY_MACEDONIA_FORMER_YUGOSLAV_REPUBLIC_OF, + RT_COUNTRY_MADAGASCAR, + RT_COUNTRY_MALAWI, + RT_COUNTRY_MALAYSIA, + RT_COUNTRY_MALDIVES, + RT_COUNTRY_MALI, + RT_COUNTRY_MALTA, + RT_COUNTRY_MAN_ISLE_OF, + RT_COUNTRY_MARTINIQUE, + RT_COUNTRY_MAURITANIA, + RT_COUNTRY_MAURITIUS, + RT_COUNTRY_MAYOTTE, + RT_COUNTRY_MEXICO, + RT_COUNTRY_MICRONESIA_FEDERATED_STATES_OF, + RT_COUNTRY_MOLDOVA_REPUBLIC_OF, + RT_COUNTRY_MONACO, + RT_COUNTRY_MONGOLIA, + RT_COUNTRY_MONTENEGRO, + RT_COUNTRY_MONTSERRAT, + RT_COUNTRY_MOROCCO, + RT_COUNTRY_MOZAMBIQUE, + RT_COUNTRY_MYANMAR, + RT_COUNTRY_NAMIBIA, + RT_COUNTRY_NAURU, + RT_COUNTRY_NEPAL, + RT_COUNTRY_NETHERLANDS, + RT_COUNTRY_NETHERLANDS_ANTILLES, + RT_COUNTRY_NEW_CALEDONIA, + RT_COUNTRY_NEW_ZEALAND, + RT_COUNTRY_NICARAGUA, + RT_COUNTRY_NIGER, + RT_COUNTRY_NIGERIA, + RT_COUNTRY_NORFOLK_ISLAND, + RT_COUNTRY_NORTHERN_MARIANA_ISLANDS, + RT_COUNTRY_NORWAY, + RT_COUNTRY_OMAN, + RT_COUNTRY_PAKISTAN, + RT_COUNTRY_PALAU, + RT_COUNTRY_PANAMA, + RT_COUNTRY_PAPUA_NEW_GUINEA, + RT_COUNTRY_PARAGUAY, + RT_COUNTRY_PERU, + RT_COUNTRY_PHILIPPINES, + RT_COUNTRY_POLAND, + RT_COUNTRY_PORTUGAL, + RT_COUNTRY_PUETO_RICO, + RT_COUNTRY_QATAR, + RT_COUNTRY_REUNION, + RT_COUNTRY_ROMANIA, + RT_COUNTRY_RUSSIAN_FEDERATION, + RT_COUNTRY_RWANDA, + RT_COUNTRY_SAINT_KITTS_AND_NEVIS, + RT_COUNTRY_SAINT_LUCIA, + RT_COUNTRY_SAINT_PIERRE_AND_MIQUELON, + RT_COUNTRY_SAINT_VINCENT_AND_THE_GRENADINES, + RT_COUNTRY_SAMOA, + RT_COUNTRY_SANIT_MARTIN_SINT_MARTEEN, + RT_COUNTRY_SAO_TOME_AND_PRINCIPE, + RT_COUNTRY_SAUDI_ARABIA, + RT_COUNTRY_SENEGAL, + RT_COUNTRY_SERBIA, + RT_COUNTRY_SEYCHELLES, + RT_COUNTRY_SIERRA_LEONE, + RT_COUNTRY_SINGAPORE, + RT_COUNTRY_SLOVAKIA, + RT_COUNTRY_SLOVENIA, + RT_COUNTRY_SOLOMON_ISLANDS, + RT_COUNTRY_SOMALIA, + RT_COUNTRY_SOUTH_AFRICA, + RT_COUNTRY_SPAIN, + RT_COUNTRY_SRI_LANKA, + RT_COUNTRY_SURINAME, + RT_COUNTRY_SWAZILAND, + RT_COUNTRY_SWEDEN, + RT_COUNTRY_SWITZERLAND, + RT_COUNTRY_SYRIAN_ARAB_REPUBLIC, + RT_COUNTRY_TAIWAN_PROVINCE_OF_CHINA, + RT_COUNTRY_TAJIKISTAN, + RT_COUNTRY_TANZANIA_UNITED_REPUBLIC_OF, + RT_COUNTRY_THAILAND, + RT_COUNTRY_TOGO, + RT_COUNTRY_TONGA, + RT_COUNTRY_TRINIDAD_AND_TOBAGO, + RT_COUNTRY_TUNISIA, + RT_COUNTRY_TURKEY, + RT_COUNTRY_TURKMENISTAN, + RT_COUNTRY_TURKS_AND_CAICOS_ISLANDS, + RT_COUNTRY_TUVALU, + RT_COUNTRY_UGANDA, + RT_COUNTRY_UKRAINE, + RT_COUNTRY_UNITED_ARAB_EMIRATES, + RT_COUNTRY_UNITED_KINGDOM, + RT_COUNTRY_UNITED_STATES, + RT_COUNTRY_UNITED_STATES_REV4, + RT_COUNTRY_UNITED_STATES_NO_DFS, + RT_COUNTRY_UNITED_STATES_MINOR_OUTLYING_ISLANDS, + RT_COUNTRY_URUGUAY, + RT_COUNTRY_UZBEKISTAN, + RT_COUNTRY_VANUATU, + RT_COUNTRY_VENEZUELA, + RT_COUNTRY_VIET_NAM, + RT_COUNTRY_VIRGIN_ISLANDS_BRITISH, + RT_COUNTRY_VIRGIN_ISLANDS_US, + RT_COUNTRY_WALLIS_AND_FUTUNA, + RT_COUNTRY_WEST_BANK, + RT_COUNTRY_WESTERN_SAHARA, + RT_COUNTRY_WORLD_WIDE_XX, + RT_COUNTRY_YEMEN, + RT_COUNTRY_ZAMBIA, + RT_COUNTRY_ZIMBABWE, + RT_COUNTRY_UNKNOWN +} rt_country_code_t; struct rt_wlan_device; -typedef void (*rt_wlan_event_handler)(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data); -typedef void (*rt_wlan_monitor_callback_t)(uint8_t *data, int len, void *user_data); +struct rt_wlan_buff; + +typedef void (*rt_wlan_dev_event_handler)(struct rt_wlan_device *device, rt_wlan_dev_event_t event, struct rt_wlan_buff *buff, void *parameter); + +typedef void (*rt_wlan_pormisc_callback_t)(struct rt_wlan_device *device, void *data, int len); + +struct rt_wlan_ssid +{ + rt_uint8_t len; + rt_uint8_t val[RT_WLAN_SSID_MAX_LENGTH + 1]; +}; +typedef struct rt_wlan_ssid rt_wlan_ssid_t; + +struct rt_wlan_key +{ + rt_uint8_t len; + rt_uint8_t val[RT_WLAN_PASSWORD_MAX_LENGTH + 1]; +}; +typedef struct rt_wlan_key rt_wlan_key_t; + +#define INVALID_INFO(_info) do { \ + rt_memset((_info), 0, sizeof(struct rt_wlan_info)); \ + (_info)->band = RT_802_11_BAND_UNKNOWN; \ + (_info)->security = SECURITY_UNKNOWN; \ + (_info)->channel = -1; \ + } while(0) + +struct rt_wlan_info +{ + /* security type */ + rt_wlan_security_t security; + /* 2.4G/5G */ + rt_802_11_band_t band; + /* maximal data rate */ + rt_uint32_t datarate; + /* radio channel */ + rt_int16_t channel; + /* signal strength */ + rt_int16_t rssi; + /* ssid */ + rt_wlan_ssid_t ssid; + /* hwaddr */ + rt_uint8_t bssid[RT_WLAN_BSSID_MAX_LENGTH]; + rt_uint8_t hidden; +}; + +struct rt_wlan_buff +{ + void *data; + rt_int32_t len; +}; + +struct rt_filter_pattern +{ + rt_uint16_t offset; /* Offset in bytes to start filtering (referenced to the start of the ethernet packet) */ + rt_uint16_t mask_size; /* Size of the mask in bytes */ + rt_uint8_t *mask; /* Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */ + rt_uint8_t *pattern; /* Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */ +}; + +typedef enum +{ + RT_POSITIVE_MATCHING = 0, /* Receive the data matching with this pattern and discard the other data */ + RT_NEGATIVE_MATCHING = 1 /* Discard the data matching with this pattern and receive the other data */ +} rt_filter_rule_t; + +struct rt_wlan_filter +{ + struct rt_filter_pattern patt; + rt_filter_rule_t rule; + rt_uint8_t enable; +}; + +struct rt_wlan_dev_event_desc +{ + rt_wlan_dev_event_handler handler; + void *parameter; +}; + struct rt_wlan_device { - struct eth_device parent; - - struct rt_wlan_info *info; - char key[KEY_ARRAY_SIZE + 1]; - - rt_wlan_event_handler handler[WIFI_EVT_MAX]; + struct rt_device device; + rt_wlan_mode_t mode; + struct rt_mutex lock; + struct rt_wlan_dev_event_desc handler_table[RT_WLAN_DEV_EVT_MAX][RT_WLAN_DEV_EVENT_NUM]; + rt_wlan_pormisc_callback_t pormisc_callback; + const struct rt_wlan_dev_ops *ops; + rt_uint32_t flags; + void *prot; void *user_data; - int interface; +}; + +struct rt_sta_info +{ + rt_wlan_ssid_t ssid; + rt_wlan_key_t key; + rt_uint8_t bssid[6]; + rt_uint16_t channel; + rt_wlan_security_t security; +}; + +struct rt_ap_info +{ + rt_wlan_ssid_t ssid; + rt_wlan_key_t key; + rt_bool_t hidden; + rt_uint16_t channel; + rt_wlan_security_t security; +}; + +struct rt_scan_info +{ + rt_wlan_ssid_t ssid; + rt_uint8_t bssid[6]; + rt_int16_t channel_min; + rt_int16_t channel_max; +}; + +struct rt_wlan_dev_ops +{ + rt_err_t (*wlan_init)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_mode)(struct rt_wlan_device *wlan, rt_wlan_mode_t mode); + rt_err_t (*wlan_scan)(struct rt_wlan_device *wlan, struct rt_scan_info *scan_info); + rt_err_t (*wlan_join)(struct rt_wlan_device *wlan, struct rt_sta_info *sta_info); + rt_err_t (*wlan_softap)(struct rt_wlan_device *wlan, struct rt_ap_info *ap_info); + rt_err_t (*wlan_disconnect)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_ap_stop)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_ap_deauth)(struct rt_wlan_device *wlan, rt_uint8_t mac[]); + rt_err_t (*wlan_scan_stop)(struct rt_wlan_device *wlan); + int (*wlan_get_rssi)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_set_powersave)(struct rt_wlan_device *wlan, int level); + int (*wlan_get_powersave)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_cfg_promisc)(struct rt_wlan_device *wlan, rt_bool_t start); + rt_err_t (*wlan_cfg_filter)(struct rt_wlan_device *wlan, struct rt_wlan_filter *filter); + rt_err_t (*wlan_set_channel)(struct rt_wlan_device *wlan, int channel); + int (*wlan_get_channel)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_set_country)(struct rt_wlan_device *wlan, rt_country_code_t country_code); + rt_country_code_t (*wlan_get_country)(struct rt_wlan_device *wlan); + rt_err_t (*wlan_set_mac)(struct rt_wlan_device *wlan, rt_uint8_t mac[]); + rt_err_t (*wlan_get_mac)(struct rt_wlan_device *wlan, rt_uint8_t mac[]); + int (*wlan_recv)(struct rt_wlan_device *wlan, void *buff, int len); + int (*wlan_send)(struct rt_wlan_device *wlan, void *buff, int len); }; /* - * Wi-Fi Information APIs + * wlan device init */ -void rt_wlan_info_init(struct rt_wlan_info *info, rt_wlan_mode_t mode, rt_wlan_security_t security, - char *ssid); -void rt_wlan_info_deinit(struct rt_wlan_info *info); +rt_err_t rt_wlan_dev_init(struct rt_wlan_device *device, rt_wlan_mode_t mode); /* - * Wi-Fi Manager APIs + * wlan device station interface */ -int rt_wlan_init(struct rt_wlan_device *device, rt_wlan_mode_t mode); +rt_err_t rt_wlan_dev_connect(struct rt_wlan_device *device, struct rt_wlan_info *info, const char *password, int password_len); +rt_err_t rt_wlan_dev_disconnect(struct rt_wlan_device *device); +int rt_wlan_dev_get_rssi(struct rt_wlan_device *device); -int rt_wlan_connect(struct rt_wlan_device *device, struct rt_wlan_info *info, - char *password); -int rt_wlan_disconnect(struct rt_wlan_device *device); +/* + * wlan device ap interface + */ +rt_err_t rt_wlan_dev_ap_start(struct rt_wlan_device *device, struct rt_wlan_info *info, const char *password, int password_len); +rt_err_t rt_wlan_dev_ap_stop(struct rt_wlan_device *device); +rt_err_t rt_wlan_dev_ap_deauth(struct rt_wlan_device *device, rt_uint8_t mac[6]); -int rt_wlan_softap(struct rt_wlan_device *device, struct rt_wlan_info *info, - char *password); +/* + * wlan device scan interface + */ +rt_err_t rt_wlan_dev_scan(struct rt_wlan_device *device, struct rt_wlan_info *info); +rt_err_t rt_wlan_dev_scan_stop(struct rt_wlan_device *device); -/* set wifi information for AP */ -int rt_wlan_set_info(struct rt_wlan_device *device, struct rt_wlan_info *info); -/* get wifi information for AP */ -struct rt_wlan_info *rt_wlan_get_info(struct rt_wlan_device *device); +/* + * wlan device mac interface + */ +rt_err_t rt_wlan_dev_get_mac(struct rt_wlan_device *device, rt_uint8_t mac[6]); +rt_err_t rt_wlan_dev_set_mac(struct rt_wlan_device *device, rt_uint8_t mac[6]); -/* get the AP result which were scaned in station */ -int rt_wlan_scan(struct rt_wlan_device *device, struct rt_wlan_scan_result **scan_result); +/* + * wlan device powersave interface + */ +rt_err_t rt_wlan_dev_set_powersave(struct rt_wlan_device *device, int level); +int rt_wlan_dev_get_powersave(struct rt_wlan_device *device); -/* get rssi */ -int rt_wlan_get_rssi(struct rt_wlan_device *device); -/* Get/Set MAC */ -int rt_wlan_get_mac(struct rt_wlan_device *device, rt_uint8_t hwaddr[6]); -int rt_wlan_set_mac(struct rt_wlan_device *device, rt_uint8_t hwaddr[6]); +/* + * wlan device event interface + */ +rt_err_t rt_wlan_dev_register_event_handler(struct rt_wlan_device *device, rt_wlan_dev_event_t event, rt_wlan_dev_event_handler handler, void *parameter); +rt_err_t rt_wlan_dev_unregister_event_handler(struct rt_wlan_device *device, rt_wlan_dev_event_t event, rt_wlan_dev_event_handler handler); +void rt_wlan_dev_indicate_event_handle(struct rt_wlan_device *device, rt_wlan_dev_event_t event, struct rt_wlan_buff *buff); -/* enter power save level */ -int rt_wlan_enter_powersave(struct rt_wlan_device *device, int level); +/* + * wlan device promisc interface + */ +rt_err_t rt_wlan_dev_enter_promisc(struct rt_wlan_device *device); +rt_err_t rt_wlan_dev_exit_promisc(struct rt_wlan_device *device); +rt_err_t rt_wlan_dev_set_promisc_callback(struct rt_wlan_device *device, rt_wlan_pormisc_callback_t callback); +void rt_wlan_dev_promisc_handler(struct rt_wlan_device *device, void *data, int len); -/* register the event handler */ -int rt_wlan_register_event_handler(struct rt_wlan_device *device, rt_wlan_event_t event, - rt_wlan_event_handler handler); +/* + * wlan device filter interface + */ +rt_err_t rt_wlan_dev_cfg_filter(struct rt_wlan_device *device, struct rt_wlan_filter *filter); -/* un-register the event handler */ -int rt_wlan_unregister_event_handler(struct rt_wlan_device *device, rt_wlan_event_t event); +/* + * wlan device channel interface + */ +rt_err_t rt_wlan_dev_set_channel(struct rt_wlan_device *device, int channel); +rt_err_t rt_wlan_dev_get_channel(struct rt_wlan_device *device); -/* wlan driver indicate event to upper layer through wifi_indication. */ -int rt_wlan_indicate_event_handle(struct rt_wlan_device *device, rt_wlan_event_t event, - void *user_data); +/* + * wlan device country interface + */ +rt_err_t rt_wlan_dev_set_country(struct rt_wlan_device *device, rt_country_code_t country_code); +rt_country_code_t rt_wlan_dev_get_country(struct rt_wlan_device *device); -/* start or stop monitor */ -int rt_wlan_cfg_monitor(struct rt_wlan_device *device, rt_wlan_monitor_opition_t opition); +/* + * wlan device datat transfer interface + */ +rt_err_t rt_wlan_dev_report_data(struct rt_wlan_device *device, void *buff, int len); +// void rt_wlan_dev_data_ready(struct rt_wlan_device *device, int len); -/* set callback function for monitor mode*/ -int rt_wlan_set_monitor_callback(struct rt_wlan_device *device, rt_wlan_monitor_callback_t callback); +/* + * wlan device register interface + */ +rt_err_t rt_wlan_dev_register(struct rt_wlan_device *wlan, const char *name, + const struct rt_wlan_dev_ops *ops, rt_uint32_t flag, void *user_data); -/* Set the monitor channel */ -int rt_wlan_set_channel(struct rt_wlan_device *device, int channel); - -void rt_wlan_release_scan_result(struct rt_wlan_scan_result **scan_result); +#ifdef __cplusplus +} +#endif #endif diff --git a/components/drivers/wlan/wlan_lwip.c b/components/drivers/wlan/wlan_lwip.c new file mode 100644 index 0000000000..ec6ca23845 --- /dev/null +++ b/components/drivers/wlan/wlan_lwip.c @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-14 tyx the first version + */ + +#include +#include +#include +#include +#include + +#ifdef RT_USING_LWIP +#include +#include +#ifdef LWIP_USING_DHCPD +#include +#endif + +#define DBG_ENABLE +#ifdef RT_WLAN_LWIP_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif +#define DBG_SECTION_NAME "WLAN.lwip" +#define DBG_COLOR +#include + +#ifndef IPADDR_STRLEN_MAX +#define IPADDR_STRLEN_MAX (32) +#endif + +struct lwip_prot_des +{ + struct rt_wlan_prot prot; + struct eth_device eth; + rt_int8_t connected_flag; + struct rt_timer timer; + struct rt_work work; +}; + +static void netif_is_ready(struct rt_work *work, void *parameter) +{ + ip_addr_t ip_addr_zero = { 0 }; + struct rt_wlan_device *wlan = parameter; + struct lwip_prot_des *lwip_prot = (struct lwip_prot_des *)wlan->prot; + struct eth_device *eth_dev = &lwip_prot->eth; + rt_base_t level; + struct rt_wlan_buff buff; + rt_uint32_t ip_addr[4]; + char str[IPADDR_STRLEN_MAX]; + + rt_timer_stop(&lwip_prot->timer); + if (ip_addr_cmp(&(eth_dev->netif->ip_addr), &ip_addr_zero) != 0) + { + rt_timer_start(&lwip_prot->timer); + goto exit; + } + rt_memset(&ip_addr, 0, sizeof(ip_addr)); +#if LWIP_IPV4 && LWIP_IPV6 + if (eth_dev->netif->ip_addr.type == IPADDR_TYPE_V4) + { + ip_addr[0] = ip4_addr_get_u32(ð_dev->netif->ip_addr.u_addr.ip4); + buff.data = &ip_addr[0]; + buff.len = sizeof(ip_addr[0]); + } + else if (eth_dev->netif->ip_addr.type == IPADDR_TYPE_V6) + { + *(ip6_addr_t *)(&ip_addr[0]) = eth_dev->netif->ip_addr.u_addr.ip6; + buff.data = ip_addr; + buff.len = sizeof(ip_addr); + } + else + { + LOG_W("F:%s L:%d ip addr type not support", __FUNCTION__, __LINE__); + } +#else +#if LWIP_IPV4 + ip_addr[0] = ip4_addr_get_u32(ð_dev->netif->ip_addr); + buff.data = &ip_addr[0]; + buff.len = sizeof(ip_addr[0]); +#else + *(ip_addr_t *)(&ip_addr[0]) = eth_dev->netif->ip_addr; + buff.data = ip_addr; + buff.len = sizeof(ip_addr); +#endif +#endif + if (rt_wlan_prot_ready(wlan, &buff) != 0) + { + rt_timer_start(&lwip_prot->timer); + goto exit; + } + rt_memset(str, 0, IPADDR_STRLEN_MAX); + rt_enter_critical(); + rt_memcpy(str, ipaddr_ntoa(&(eth_dev->netif->ip_addr)), IPADDR_STRLEN_MAX); + rt_exit_critical(); + LOG_I("Got IP address : %s", str); +exit: + level = rt_hw_interrupt_disable(); + rt_memset(work, 0, sizeof(struct rt_work)); + rt_hw_interrupt_enable(level); +} + +static void timer_callback(void *parameter) +{ + struct rt_workqueue *workqueue; + struct rt_wlan_device *wlan = parameter; + struct lwip_prot_des *lwip_prot = (struct lwip_prot_des *)wlan->prot; + struct rt_work *work = &lwip_prot->work; + rt_base_t level; + + workqueue = rt_wlan_get_workqueue(); + if (workqueue != RT_NULL) + { + level = rt_hw_interrupt_disable(); + rt_work_init(work, netif_is_ready, parameter); + rt_hw_interrupt_enable(level); + if (rt_workqueue_dowork(workqueue, work) != RT_EOK) + { + level = rt_hw_interrupt_disable(); + rt_memset(work, 0, sizeof(struct rt_work)); + rt_hw_interrupt_enable(level); + } + } +} + +static void netif_set_connected(void *parameter) +{ + struct rt_wlan_device *wlan = parameter; + struct lwip_prot_des *lwip_prot = wlan->prot; + struct eth_device *eth_dev = &lwip_prot->eth; + + if (lwip_prot->connected_flag) + { + if (wlan->mode == RT_WLAN_STATION) + { + LOG_D("F:%s L:%d dhcp start run", __FUNCTION__, __LINE__); + netifapi_netif_common(eth_dev->netif, netif_set_link_up, NULL); +#ifdef RT_LWIP_DHCP + dhcp_start(eth_dev->netif); +#endif + rt_timer_start(&lwip_prot->timer); + } + else if (wlan->mode == RT_WLAN_AP) + { + LOG_D("F:%s L:%d dhcpd start run", __FUNCTION__, __LINE__); + + netifapi_netif_common(eth_dev->netif, netif_set_link_up, NULL); +#ifdef LWIP_USING_DHCPD + { + char netif_name[8]; + int i; + + rt_memset(netif_name, 0, sizeof(netif_name)); + for (i = 0; i < sizeof(eth_dev->netif->name); i++) + { + netif_name[i] = eth_dev->netif->name[i]; + } + dhcpd_start(netif_name); + } +#endif + } + } + else + { + if (wlan->mode == RT_WLAN_STATION) + { + LOG_D("F:%s L:%d dhcp stop run", __FUNCTION__, __LINE__); + netifapi_netif_common(eth_dev->netif, netif_set_link_down, NULL); +#ifdef RT_LWIP_DHCP + { + ip_addr_t ip_addr = { 0 }; + dhcp_stop(eth_dev->netif); + netif_set_addr(eth_dev->netif, &ip_addr, &ip_addr, &ip_addr); + } +#endif + rt_timer_stop(&lwip_prot->timer); + } + else if (wlan->mode == RT_WLAN_AP) + { + LOG_D("F:%s L:%d dhcpd stop run", __FUNCTION__, __LINE__); + netifapi_netif_common(eth_dev->netif, netif_set_link_down, NULL); + } + } +} + +static void rt_wlan_lwip_event_handle(struct rt_wlan_prot *port, struct rt_wlan_device *wlan, int event) +{ + struct lwip_prot_des *lwip_prot = (struct lwip_prot_des *)wlan->prot; + rt_bool_t flag_old; + + flag_old = lwip_prot->connected_flag; + + switch (event) + { + case RT_WLAN_PROT_EVT_CONNECT: + { + LOG_D("event: CONNECT"); + lwip_prot->connected_flag = RT_TRUE; + break; + } + case RT_WLAN_PROT_EVT_DISCONNECT: + { + LOG_D("event: DISCONNECT"); + lwip_prot->connected_flag = RT_FALSE; + break; + } + case RT_WLAN_PROT_EVT_AP_START: + { + LOG_D("event: AP_START"); + lwip_prot->connected_flag = RT_TRUE; + break; + } + case RT_WLAN_PROT_EVT_AP_STOP: + { + LOG_D("event: AP_STOP"); + lwip_prot->connected_flag = RT_FALSE; + break; + } + case RT_WLAN_PROT_EVT_AP_ASSOCIATED: + { + LOG_D("event: ASSOCIATED"); + break; + } + case RT_WLAN_PROT_EVT_AP_DISASSOCIATED: + { + LOG_D("event: DISASSOCIATED"); + break; + } + default : + { + LOG_D("event: UNKNOWN"); + break; + } + } + if (flag_old != lwip_prot->connected_flag) + { + rt_wlan_workqueue_dowork(netif_set_connected, wlan); + // netif_set_connected(wlan); + } +} + +static rt_err_t rt_wlan_lwip_protocol_control(rt_device_t device, int cmd, void *args) +{ + struct eth_device *eth_dev = (struct eth_device *)device; + struct rt_wlan_device *wlan; + rt_err_t err = RT_EOK; + + RT_ASSERT(eth_dev != RT_NULL); + + LOG_D("F:%s L:%d device:0x%08x user_data:0x%08x", __FUNCTION__, __LINE__, eth_dev, eth_dev->parent.user_data); + + switch (cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + wlan = eth_dev->parent.user_data; + err = rt_device_control((rt_device_t)wlan, RT_WLAN_CMD_GET_MAC, args); + break; + default : + break; + } + return err; +} + +static rt_err_t rt_wlan_lwip_protocol_recv(struct rt_wlan_device *wlan, void *buff, int len) +{ + struct eth_device *eth_dev = &((struct lwip_prot_des *)wlan->prot)->eth; + struct pbuf *p = RT_NULL; + + LOG_D("F:%s L:%d run", __FUNCTION__, __LINE__); + + if (eth_dev == RT_NULL) + { + return -RT_ERROR; + } +#ifdef RT_WLAN_PROT_LWIP_PBUF_FORCE + { + p = buff; + if ((eth_dev->netif->input(p, eth_dev->netif)) != ERR_OK) + { + return -RT_ERROR; + } + return RT_EOK; + } +#else + { + int count = 0; + + while (p == RT_NULL) + { + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + if (p != RT_NULL) + break; + + p = pbuf_alloc(PBUF_RAW, len, PBUF_RAM); + if (p != RT_NULL) + break; + + LOG_D("F:%s L:%d wait for pbuf_alloc!", __FUNCTION__, __LINE__); + rt_thread_delay(1); + count++; + + //wait for 10ms or give up!! + if (count >= 10) + { + LOG_W("F:%s L:%d pbuf allocate fail!!!", __FUNCTION__, __LINE__); + return -RT_ENOMEM; + } + } + /*copy data dat -> pbuf*/ + pbuf_take(p, buff, len); + if ((eth_dev->netif->input(p, eth_dev->netif)) != ERR_OK) + { + LOG_D("F:%s L:%d IP input error", __FUNCTION__, __LINE__); + pbuf_free(p); + p = RT_NULL; + } + LOG_D("F:%s L:%d netif iput success! len:%d", __FUNCTION__, __LINE__, len); + return RT_EOK; + } +#endif +} + +static rt_err_t rt_wlan_lwip_protocol_send(rt_device_t device, struct pbuf *p) +{ + struct rt_wlan_device *wlan = ((struct eth_device *)device)->parent.user_data; + + LOG_D("F:%s L:%d run", __FUNCTION__, __LINE__); + + if (wlan == RT_NULL) + { + return RT_EOK; + } + +#ifdef RT_WLAN_PROT_LWIP_PBUF_FORCE + { + rt_wlan_prot_transfer_dev(wlan, p, p->tot_len); + return RT_EOK; + } +#else + { + rt_uint8_t *frame; + + /* sending data directly */ + if (p->len == p->tot_len) + { + frame = (rt_uint8_t *)p->payload; + rt_wlan_prot_transfer_dev(wlan, frame, p->tot_len); + LOG_D("F:%s L:%d run len:%d", __FUNCTION__, __LINE__, p->tot_len); + return RT_EOK; + } + frame = rt_malloc(p->tot_len); + if (frame == RT_NULL) + { + LOG_E("F:%s L:%d malloc out_buf fail\n", __FUNCTION__, __LINE__); + return -RT_ENOMEM; + } + /*copy pbuf -> data dat*/ + pbuf_copy_partial(p, frame, p->tot_len, 0); + /* send data */ + rt_wlan_prot_transfer_dev(wlan, frame, p->tot_len); + LOG_D("F:%s L:%d run len:%d", __FUNCTION__, __LINE__, p->tot_len); + rt_free(frame); + return RT_EOK; + } +#endif +} + +static struct rt_wlan_prot *rt_wlan_lwip_protocol_register(struct rt_wlan_prot *prot, struct rt_wlan_device *wlan) +{ + struct eth_device *eth = RT_NULL; + static rt_uint8_t id = 0; + char eth_name[4], timer_name[16]; + rt_device_t device = RT_NULL; + struct lwip_prot_des *lwip_prot; + + if (wlan == RT_NULL || prot == RT_NULL) + return RT_NULL;; + + LOG_D("F:%s L:%d is run wlan:0x%08x", __FUNCTION__, __LINE__, wlan); + + do + { + /* find ETH device name */ + eth_name[0] = 'w'; + eth_name[1] = '0' + id++; + eth_name[2] = '\0'; + device = rt_device_find(eth_name); + } + while (device); + + if (id > 9) + { + LOG_E("F:%s L:%d not find Empty name", __FUNCTION__, __LINE__, eth_name); + return RT_NULL; + } + + if (rt_device_open((rt_device_t)wlan, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + LOG_E("F:%s L:%d open wlan failed", __FUNCTION__, __LINE__); + return RT_NULL; + } + + lwip_prot = rt_malloc(sizeof(struct lwip_prot_des)); + if (lwip_prot == RT_NULL) + { + LOG_E("F:%s L:%d malloc mem failed", __FUNCTION__, __LINE__); + rt_device_close((rt_device_t)wlan); + return RT_NULL; + } + rt_memset(lwip_prot, 0, sizeof(struct lwip_prot_des)); + + eth = &lwip_prot->eth; + eth->parent.init = RT_NULL; + eth->parent.open = RT_NULL; + eth->parent.close = RT_NULL; + eth->parent.read = RT_NULL; + eth->parent.write = RT_NULL; + eth->parent.control = rt_wlan_lwip_protocol_control; + eth->parent.user_data = wlan; + eth->eth_rx = RT_NULL; + eth->eth_tx = rt_wlan_lwip_protocol_send; + + /* register ETH device */ + if (eth_device_init(eth, eth_name) != RT_EOK) + { + LOG_E("eth device init failed"); + rt_device_close((rt_device_t)wlan); + rt_free(lwip_prot); + return RT_NULL; + } + rt_memcpy(&lwip_prot->prot, prot, sizeof(struct rt_wlan_prot)); + if (wlan->mode == RT_WLAN_STATION) + { + rt_sprintf(timer_name, "timer_%s", eth_name); + rt_timer_init(&lwip_prot->timer, timer_name, timer_callback, wlan, rt_tick_from_millisecond(1000), + RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_ONE_SHOT); + } + netif_set_up(eth->netif); + LOG_I("eth device init ok name:%s", eth_name); + + return &lwip_prot->prot; +} + +static void rt_wlan_lwip_protocol_unregister(struct rt_wlan_prot *prot, struct rt_wlan_device *wlan) +{ + /*TODO*/ + LOG_D("F:%s L:%d is run wlan:0x%08x", __FUNCTION__, __LINE__, wlan); +} + +static struct rt_wlan_prot_ops ops = +{ + rt_wlan_lwip_protocol_recv, + rt_wlan_lwip_protocol_register, + rt_wlan_lwip_protocol_unregister +}; + +int rt_wlan_lwip_init(void) +{ + static struct rt_wlan_prot prot; + rt_wlan_prot_event_t event; + + rt_memset(&prot, 0, sizeof(prot)); + rt_strncpy(&prot.name[0], RT_WLAN_PROT_LWIP, RT_WLAN_PROT_NAME_LEN); + prot.ops = &ops; + + if (rt_wlan_prot_regisetr(&prot) != RT_EOK) + { + LOG_E("F:%s L:%d protocol regisetr failed", __FUNCTION__, __LINE__); + return -1; + } + + for (event = RT_WLAN_PROT_EVT_INIT_DONE; event < RT_WLAN_PROT_EVT_MAX; event++) + { + rt_wlan_prot_event_register(&prot, event, rt_wlan_lwip_event_handle); + } + + return 0; +} +INIT_PREV_EXPORT(rt_wlan_lwip_init); + +#endif diff --git a/components/drivers/wlan/wlan_mgnt.c b/components/drivers/wlan/wlan_mgnt.c index 2a728747f2..1d0b0c4aa7 100644 --- a/components/drivers/wlan/wlan_mgnt.c +++ b/components/drivers/wlan/wlan_mgnt.c @@ -1,142 +1,1887 @@ /* - * RT-Thread Wi-Fi Device + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2014 - 2018, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-02-27 EvalZero the first verion + * 2018-08-06 tyx the first version */ +#include #include -#include +#include +#include +#include +#include +#include -#include - -#include "wlan_dev.h" -#include "wlan_cmd.h" - -#define WLAN_MGNT_DEBUG 1 - -#if WLAN_MGNT_DEBUG -#define WLAN_MGNT_DBG(...) rt_kprintf("[WLAN_MGNT]"),rt_kprintf(__VA_ARGS__) +#define DBG_ENABLE +#ifdef RT_WLAN_MGNT_DEBUG +#define DBG_LEVEL DBG_LOG #else -#define WLAN_MGNT_DBG(...) +#define DBG_LEVEL DBG_INFO +#endif +#define DBG_SECTION_NAME "WLAN.mgnt" +#define DBG_COLOR +#include + +#ifndef RT_WLAN_DEVICE +#define RT_WLAN_DEVICE(__device) ((struct rt_wlan_device *)__device) #endif -#ifndef WIFI_DEVICE_STA_NAME -#define WIFI_DEVICE_STA_NAME "w0" -#endif -#ifndef WIFI_DEVICE_AP_NAME -#define WIFI_DEVICE_AP_NAME "ap" +#define RT_WLAN_LOG_D(_fmt, ...) LOG_D("L:%d "_fmt"", __LINE__, ##__VA_ARGS__) +#define RT_WLAN_LOG_I(...) LOG_I(__VA_ARGS__) +#define RT_WLAN_LOG_W(_fmt, ...) LOG_W("F:%s L:%d "_fmt"", __FUNCTION__, __LINE__, ##__VA_ARGS__) +#define RT_WLAN_LOG_E(_fmt, ...) LOG_E("F:%s L:%d "_fmt"", __FUNCTION__, __LINE__, ##__VA_ARGS__) + +#define STA_DEVICE() (_sta_mgnt.device) +#define AP_DEVICE() (_ap_mgnt.device) + +#define SRESULT_LOCK() (rt_mutex_take(&scan_result_mutex, RT_WAITING_FOREVER)) +#define SRESULT_UNLOCK() (rt_mutex_release(&scan_result_mutex)) + +#define STAINFO_LOCK() (rt_mutex_take(&sta_info_mutex, RT_WAITING_FOREVER)) +#define STAINFO_UNLOCK() (rt_mutex_release(&sta_info_mutex)) + +#define MGNT_LOCK() (rt_mutex_take(&mgnt_mutex, RT_WAITING_FOREVER)) +#define MGNT_UNLOCK() (rt_mutex_release(&mgnt_mutex)) + +#define COMPLETE_LOCK() (rt_mutex_take(&complete_mutex, RT_WAITING_FOREVER)) +#define COMPLETE_UNLOCK() (rt_mutex_release(&complete_mutex)) + +#define TIME_STOP() (rt_timer_stop(&reconnect_time)) +#define TIME_START() (rt_timer_start(&reconnect_time)) + +#define DISCONNECT_RESPONSE_TICK (2000) + +#if RT_WLAN_EBOX_NUM < 1 +#error "event box num Too little" #endif -static void wlan_mgnt_init_done_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) +struct rt_wlan_mgnt_des { - WLAN_MGNT_DBG("wlan init done event callback \n"); + struct rt_wlan_device *device; + struct rt_wlan_info info; + struct rt_wlan_key key; + rt_uint8_t state; + rt_uint8_t flags; +}; + +struct rt_wlan_event_desc +{ + rt_wlan_event_handler handler; + void *parameter; +}; + +struct rt_wlan_sta_list +{ + struct rt_wlan_sta_list *next; + struct rt_wlan_info info; +}; + +struct rt_wlan_sta_des +{ + int num; + struct rt_wlan_sta_list *node; +}; + +struct rt_wlan_msg +{ + rt_int32_t event; + rt_int32_t len; + void *buff; +}; + +struct rt_wlan_complete_des +{ + struct rt_event complete; + rt_uint32_t event_flag; + int index; +}; + +static struct rt_mutex mgnt_mutex; + +static struct rt_wlan_mgnt_des _sta_mgnt; +static struct rt_wlan_mgnt_des _ap_mgnt; + +static struct rt_wlan_scan_result scan_result; +static struct rt_mutex scan_result_mutex; + +static struct rt_wlan_sta_des sta_info; +static struct rt_mutex sta_info_mutex; + +static struct rt_wlan_event_desc event_tab[RT_WLAN_EVT_MAX]; + +static struct rt_wlan_complete_des *complete_tab[5]; +static struct rt_mutex complete_mutex; + +static struct rt_timer reconnect_time; + +rt_inline int _sta_is_null(void) +{ + if (_sta_mgnt.device == RT_NULL) + { + return 1; + } + return 0; } -static void wlan_mgnt_link_up_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) +rt_inline int _ap_is_null(void) { - WLAN_MGNT_DBG("wlan link up event callback \n"); + if (_ap_mgnt.device == RT_NULL) + { + return 1; + } + return 0; } -static void wlan_mgnt_link_down_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) +rt_inline rt_bool_t _is_do_connect(void) { - WLAN_MGNT_DBG("wlan link down event callback \n"); + if ((rt_wlan_get_autoreconnect_mode() == RT_FALSE) || + (rt_wlan_is_connected() == RT_TRUE) || + (_sta_mgnt.state & RT_WLAN_STATE_CONNECTING)) + { + return RT_FALSE; + } + return RT_TRUE; } -static void wlan_mgnt_sta_connect_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) +static void rt_wlan_mgnt_work(void *parameter); + +static rt_err_t rt_wlan_send_msg(rt_wlan_dev_event_t event, void *buff, int len) { - WLAN_MGNT_DBG("wlan sta connect event callback \n"); - struct netif *netif = device->parent.netif; + struct rt_wlan_msg *msg; - netifapi_netif_set_up(netif); - netifapi_netif_set_link_up(netif); -#ifdef RT_LWIP_DHCP - /* start DHCP */ - dhcp_start(netif); -#endif -} + RT_WLAN_LOG_D("F:%s is run event:%d", __FUNCTION__, event); -static void wlan_mgnt_sta_disconnect_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - WLAN_MGNT_DBG("wlan sta disconnect event callback \n"); - netifapi_netif_set_down(device->parent.netif); - netifapi_netif_set_link_down(device->parent.netif); - rt_memset(&device->parent.netif->ip_addr, 0, sizeof(ip_addr_t)); - rt_memset(&device->parent.netif->netmask, 0, sizeof(ip_addr_t)); - rt_memset(&device->parent.netif->gw, 0, sizeof(ip_addr_t)); -#ifdef RT_LWIP_DHCP - dhcp_stop(device->parent.netif); -#endif -} - -static void wlan_mgnt_ap_start_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - WLAN_MGNT_DBG("wlan ap start event callback \n"); - netifapi_netif_set_up(device->parent.netif); - netifapi_netif_set_link_up(device->parent.netif); - - wifi_softap_setup_netif(device->parent.netif); -} - - -static void wlan_mgnt_ap_stop_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - WLAN_MGNT_DBG("wlan ap stop event callback \n"); - - netifapi_netif_set_down(device->parent.netif); - netifapi_netif_set_link_down(device->parent.netif); -} - -static void wlan_mgnt_ap_associate_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - WLAN_MGNT_DBG("wlan ap associate event callback \n"); -} - -static void wlan_mgnt_ap_disassociate_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - WLAN_MGNT_DBG("wlan ap disassociate event callback \n"); -} - -static void wlan_mgnt_scan_done_event(struct rt_wlan_device *device, rt_wlan_event_t event, void *user_data) -{ - WLAN_MGNT_DBG("wlan scan done event callback \n"); -} - -int rt_wlan_mgnt_attach(struct rt_wlan_device *device, void *user_data) -{ - RT_ASSERT(device != RT_NULL); - - rt_wlan_register_event_handler(device, WIFI_EVT_INIT_DONE, wlan_mgnt_init_done_event); - rt_wlan_register_event_handler(device, WIFI_EVT_LINK_DOWN, wlan_mgnt_link_up_event); - rt_wlan_register_event_handler(device, WIFI_EVT_LINK_UP, wlan_mgnt_link_down_event); - rt_wlan_register_event_handler(device, WIFI_EVT_CONNECT, wlan_mgnt_sta_connect_event); - rt_wlan_register_event_handler(device, WIFI_EVT_DISCONNECT, wlan_mgnt_sta_disconnect_event); - rt_wlan_register_event_handler(device, WIFI_EVT_AP_START, wlan_mgnt_ap_start_event); - rt_wlan_register_event_handler(device, WIFI_EVT_AP_STOP, wlan_mgnt_ap_stop_event); - rt_wlan_register_event_handler(device, WIFI_EVENT_STA_ASSOC, wlan_mgnt_ap_associate_event); - rt_wlan_register_event_handler(device, WIFI_EVENT_STA_DISASSOC, wlan_mgnt_ap_disassociate_event); - rt_wlan_register_event_handler(device, WIFI_EVT_SCAN_DONE, wlan_mgnt_scan_done_event); + /* Event packing */ + msg = rt_malloc(sizeof(struct rt_wlan_msg) + len); + if (msg == RT_NULL) + { + RT_WLAN_LOG_E("wlan mgnt send msg err! No memory"); + return -RT_ENOMEM; + } + rt_memset(msg, 0, sizeof(struct rt_wlan_msg) + len); + msg->event = event; + if (len != 0) + { + msg->buff = ((char *)msg) + sizeof(struct rt_wlan_msg); + msg->len = len; + } + /* send event to wlan thread */ + if (rt_wlan_workqueue_dowork(rt_wlan_mgnt_work, msg) != RT_EOK) + { + rt_free(msg); + RT_WLAN_LOG_E("wlan mgnt do work fail"); + return -RT_ERROR; + } return RT_EOK; } + +static rt_err_t rt_wlan_scan_result_cache(struct rt_wlan_info *info, int timeout) +{ + struct rt_wlan_info *ptable; + rt_err_t err = RT_EOK; + int i, insert = -1; + + if (_sta_is_null() || (info == RT_NULL)) return RT_EOK; + + RT_WLAN_LOG_D("ssid:%s len:%d mac:%02x:%02x:%02x:%02x:%02x:%02x", info->ssid.val, info->ssid.len, + info->bssid[0], info->bssid[1], info->bssid[2], info->bssid[3], info->bssid[4], info->bssid[5]); + + err = rt_mutex_take(&scan_result_mutex, rt_tick_from_millisecond(timeout)); + if (err != RT_EOK) + return err; + + /* de-duplicatio */ + for (i = 0; i < scan_result.num; i++) + { + if ((info->ssid.len == scan_result.info[i].ssid.len) && + (rt_memcmp(&info->bssid[0], &scan_result.info[i].bssid[0], RT_WLAN_BSSID_MAX_LENGTH) == 0)) + { + rt_mutex_release(&scan_result_mutex); + return RT_EOK; + } +#ifdef RT_WLAN_SCAN_SORT + if (insert >= 0) + { + continue; + } + /* Signal intensity comparison */ + if ((info->rssi < 0) && (scan_result.info[i].rssi < 0)) + { + if (info->rssi > scan_result.info[i].rssi) + { + insert = i; + continue; + } + else if (info->rssi < scan_result.info[i].rssi) + { + continue; + } + } + + /* Channel comparison */ + if (info->channel < scan_result.info[i].channel) + { + insert = i; + continue; + } + else if (info->channel > scan_result.info[i].channel) + { + continue; + } + + /* data rate comparison */ + if ((info->datarate > scan_result.info[i].datarate)) + { + insert = i; + continue; + } + else if (info->datarate < scan_result.info[i].datarate) + { + continue; + } +#endif + } + + /* Insert the end */ + if (insert == -1) + insert = scan_result.num; + + if (scan_result.num >= RT_WLAN_SCAN_CACHE_NUM) + return RT_EOK; + + /* malloc memory */ + ptable = rt_malloc(sizeof(struct rt_wlan_info) * (scan_result.num + 1)); + if (ptable == RT_NULL) + { + rt_mutex_release(&scan_result_mutex); + RT_WLAN_LOG_E("wlan info malloc failed!"); + return -RT_ENOMEM; + } + scan_result.num ++; + + /* copy info */ + for (i = 0; i < scan_result.num; i++) + { + if (i < insert) + { + ptable[i] = scan_result.info[i]; + } + else if (i > insert) + { + ptable[i] = scan_result.info[i - 1]; + } + else if (i == insert) + { + ptable[i] = *info; + } + } + rt_free(scan_result.info); + scan_result.info = ptable; + rt_mutex_release(&scan_result_mutex); + return err; +} + +static rt_err_t rt_wlan_sta_info_add(struct rt_wlan_info *info, int timeout) +{ + struct rt_wlan_sta_list *sta_list; + rt_err_t err = RT_EOK; + + if (_ap_is_null() || (info == RT_NULL)) return RT_EOK; + + err = rt_mutex_take(&sta_info_mutex, rt_tick_from_millisecond(timeout)); + if (err == RT_EOK) + { + /* malloc memory */ + sta_list = rt_malloc(sizeof(struct rt_wlan_sta_list)); + if (sta_list == RT_NULL) + { + rt_mutex_release(&sta_info_mutex); + RT_WLAN_LOG_E("sta list malloc failed!"); + return -RT_ENOMEM; + } + sta_list->next = RT_NULL; + sta_list->info = *info; + + /* Append sta info */ + sta_list->next = sta_info.node; + sta_info.node = sta_list; + /* num++ */ + sta_info.num ++; + rt_mutex_release(&sta_info_mutex); + RT_WLAN_LOG_I("sta associated mac:%02x:%02x:%02x:%02x:%02x:%02x", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5]); + } + return err; +} + +static rt_err_t rt_wlan_sta_info_del(struct rt_wlan_info *info, int timeout) +{ + struct rt_wlan_sta_list *sta_list, *sta_prve; + rt_err_t err = RT_EOK; + + if (_ap_is_null() || (info == RT_NULL)) return RT_EOK; + + err = rt_mutex_take(&sta_info_mutex, rt_tick_from_millisecond(timeout)); + if (err == RT_EOK) + { + /* traversing the list */ + for (sta_list = sta_info.node, sta_prve = RT_NULL; sta_list != RT_NULL; + sta_prve = sta_list, sta_list = sta_list->next) + { + /* find mac addr */ + if (rt_memcmp(&sta_list->info.bssid[0], &info->bssid[0], RT_WLAN_BSSID_MAX_LENGTH) == 0) + { + if (sta_prve == RT_NULL) + { + sta_info.node = sta_list->next; + } + else + { + sta_prve->next = sta_list->next; + } + sta_info.num --; + rt_free(sta_list); + break; + } + } + rt_mutex_release(&sta_info_mutex); + RT_WLAN_LOG_I("sta exit mac:%02x:%02x:%02x:%02x:%02x:%02x", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5]); + } + return err; +} + +static rt_err_t rt_wlan_sta_info_del_all(int timeout) +{ + struct rt_wlan_sta_list *sta_list, *sta_next; + rt_err_t err = RT_EOK; + + err = rt_mutex_take(&sta_info_mutex, rt_tick_from_millisecond(timeout)); + if (err == RT_EOK) + { + /* traversing the list */ + for (sta_list = sta_info.node; sta_list != RT_NULL; sta_list = sta_next) + { + sta_next = sta_list->next; + sta_info.num --; + rt_free(sta_list); + } + rt_mutex_release(&sta_info_mutex); + } + if (sta_info.num != 0) + { + RT_WLAN_LOG_W("\n\n!!!Program runing exception!!!\n\n"); + } + sta_info.num = 0; + sta_info.node = RT_NULL; + return err; +} + +static void rt_wlan_auto_connect_run(struct rt_work *work, void *parameter) +{ + static rt_uint32_t id = 0; + struct rt_wlan_cfg_info cfg_info; + char *password = RT_NULL; + rt_base_t level; + + RT_WLAN_LOG_D("F:%s is run", __FUNCTION__); + + if (rt_mutex_take(&mgnt_mutex, 0) != RT_EOK) + goto exit; + + /* auto connect status is disable or wifi is connect or connecting, exit */ + if (_is_do_connect() == RT_FALSE) + { + id = 0; + RT_WLAN_LOG_D("not connection"); + goto exit; + } + + /* Read the next configuration */ + rt_memset(&cfg_info, 0, sizeof(struct rt_wlan_cfg_info)); + if (rt_wlan_cfg_read_index(&cfg_info, id ++) == 0) + { + RT_WLAN_LOG_D("read cfg fail"); + id = 0; + goto exit; + } + + if (id >= rt_wlan_cfg_get_num()) id = 0; + + if ((cfg_info.key.len > 0) && (cfg_info.key.len < RT_WLAN_PASSWORD_MAX_LENGTH)) + { + cfg_info.key.val[cfg_info.key.len] = '\0'; + password = (char *)(&cfg_info.key.val[0]); + } + rt_wlan_connect_adv(&cfg_info.info, password); +exit: + rt_mutex_release(&mgnt_mutex); + level = rt_hw_interrupt_disable(); + rt_memset(work, 0, sizeof(struct rt_work)); + rt_hw_interrupt_enable(level); +} + +static void rt_wlan_cyclic_check(void *parameter) +{ + struct rt_workqueue *workqueue; + static struct rt_work work; + rt_base_t level; + + if ((_is_do_connect() == RT_TRUE) && (work.work_func == RT_NULL)) + { + workqueue = rt_wlan_get_workqueue(); + if (workqueue != RT_NULL) + { + level = rt_hw_interrupt_disable(); + rt_work_init(&work, rt_wlan_auto_connect_run, RT_NULL); + rt_hw_interrupt_enable(level); + if (rt_workqueue_dowork(workqueue, &work) != RT_EOK) + { + level = rt_hw_interrupt_disable(); + rt_memset(&work, 0, sizeof(struct rt_work)); + rt_hw_interrupt_enable(level); + } + } + } +} + +static void rt_wlan_mgnt_work(void *parameter) +{ + struct rt_wlan_msg *msg = parameter; + + switch (msg->event) + { + case RT_WLAN_DEV_EVT_CONNECT: + { + struct rt_wlan_cfg_info cfg_info; + + /* save config */ + if (rt_wlan_is_connected() == RT_TRUE) + { + rt_enter_critical(); + cfg_info.info = _sta_mgnt.info; + cfg_info.key = _sta_mgnt.key; + rt_exit_critical(); + RT_WLAN_LOG_D("run save config! ssid:%s len%d", _sta_mgnt.info.ssid.val, _sta_mgnt.info.ssid.len); + rt_wlan_cfg_save(&cfg_info); + } + break; + } + default : + break; + } + + rt_free(msg); +} + +static void rt_wlan_event_dispatch(struct rt_wlan_device *device, rt_wlan_dev_event_t event, struct rt_wlan_buff *buff, void *parameter) +{ + rt_base_t level; + void *user_parameter; + rt_wlan_event_handler handler = RT_NULL; + rt_err_t err = RT_NULL; + rt_wlan_event_t user_event = RT_WLAN_EVT_MAX; + int i; + struct rt_wlan_buff user_buff = { 0 }; + + if (buff) + { + user_buff = *buff; + } + /* Event Handle */ + switch (event) + { + case RT_WLAN_DEV_EVT_CONNECT: + { + RT_WLAN_LOG_D("event: CONNECT"); + _sta_mgnt.state |= RT_WLAN_STATE_CONNECT; + _sta_mgnt.state &= ~RT_WLAN_STATE_CONNECTING; + user_event = RT_WLAN_EVT_STA_CONNECTED; + TIME_STOP(); + rt_wlan_send_msg(event, RT_NULL, 0); + user_buff.data = &_sta_mgnt.info; + user_buff.len = sizeof(struct rt_wlan_info); + RT_WLAN_LOG_I("wifi connect success ssid:%s", &_sta_mgnt.info.ssid.val[0]); + break; + } + case RT_WLAN_DEV_EVT_CONNECT_FAIL: + { + RT_WLAN_LOG_D("event: CONNECT_FAIL"); + _sta_mgnt.state &= ~RT_WLAN_STATE_CONNECT; + _sta_mgnt.state &= ~RT_WLAN_STATE_CONNECTING; + _sta_mgnt.state &= ~RT_WLAN_STATE_READY; + user_event = RT_WLAN_EVT_STA_CONNECTED_FAIL; + user_buff.data = &_sta_mgnt.info; + user_buff.len = sizeof(struct rt_wlan_info); + TIME_START(); + break; + } + case RT_WLAN_DEV_EVT_DISCONNECT: + { + RT_WLAN_LOG_D("event: DISCONNECT"); + _sta_mgnt.state &= ~RT_WLAN_STATE_CONNECT; + _sta_mgnt.state &= ~RT_WLAN_STATE_READY; + user_event = RT_WLAN_EVT_STA_DISCONNECTED; + user_buff.data = &_sta_mgnt.info; + user_buff.len = sizeof(struct rt_wlan_info); + TIME_START(); + break; + } + case RT_WLAN_DEV_EVT_AP_START: + { + RT_WLAN_LOG_D("event: AP_START"); + _ap_mgnt.state |= RT_WLAN_STATE_ACTIVE; + user_event = RT_WLAN_EVT_AP_START; + user_buff.data = &_ap_mgnt.info; + user_buff.len = sizeof(struct rt_wlan_info); + break; + } + case RT_WLAN_DEV_EVT_AP_STOP: + { + RT_WLAN_LOG_D("event: AP_STOP"); + _ap_mgnt.state &= ~RT_WLAN_STATE_ACTIVE; + user_event = RT_WLAN_EVT_AP_STOP; + err = rt_wlan_sta_info_del_all(RT_WAITING_FOREVER); + if (err != RT_NULL) + { + RT_WLAN_LOG_W("AP_STOP event handle fail"); + } + user_buff.data = &_ap_mgnt.info; + user_buff.len = sizeof(struct rt_wlan_info); + break; + } + case RT_WLAN_DEV_EVT_AP_ASSOCIATED: + { + RT_WLAN_LOG_D("event: ASSOCIATED"); + user_event = RT_WLAN_EVT_AP_ASSOCIATED; + if (user_buff.len != sizeof(struct rt_wlan_info)) + break; + err = rt_wlan_sta_info_add(user_buff.data, RT_WAITING_FOREVER); + if (err != RT_EOK) + { + RT_WLAN_LOG_W("AP_ASSOCIATED event handle fail"); + } + break; + } + case RT_WLAN_DEV_EVT_AP_DISASSOCIATED: + { + RT_WLAN_LOG_D("event: DISASSOCIATED"); + user_event = RT_WLAN_EVT_AP_DISASSOCIATED; + if (user_buff.len != sizeof(struct rt_wlan_info)) + break; + err = rt_wlan_sta_info_del(user_buff.data, RT_WAITING_FOREVER); + if (err != RT_EOK) + { + RT_WLAN_LOG_W("AP_DISASSOCIATED event handle fail"); + } + break; + } + case RT_WLAN_DEV_EVT_AP_ASSOCIATE_FAILED: + { + RT_WLAN_LOG_D("event: AP_ASSOCIATE_FAILED"); + break; + } + case RT_WLAN_DEV_EVT_SCAN_REPORT: + { + RT_WLAN_LOG_D("event: SCAN_REPORT"); + user_event = RT_WLAN_EVT_SCAN_REPORT; + if (user_buff.len != sizeof(struct rt_wlan_info)) + break; + rt_wlan_scan_result_cache(user_buff.data, 0); + break; + } + case RT_WLAN_DEV_EVT_SCAN_DONE: + { + RT_WLAN_LOG_D("event: SCAN_DONE"); + user_buff.data = &scan_result; + user_buff.len = sizeof(scan_result); + user_event = RT_WLAN_EVT_SCAN_DONE; + break; + } + default : + { + RT_WLAN_LOG_D("event: UNKNOWN"); + return; + } + } + + /* send event */ + COMPLETE_LOCK(); + for (i = 0; i < sizeof(complete_tab) / sizeof(complete_tab[0]); i++) + { + if ((complete_tab[i] != RT_NULL)) + { + complete_tab[i]->event_flag |= 0x1 << event; + rt_event_send(&complete_tab[i]->complete, 0x1 << event); + RT_WLAN_LOG_D("&complete_tab[i]->complete:0x%08x", &complete_tab[i]->complete); + } + } + COMPLETE_UNLOCK(); + /* Get user callback */ + if (user_event < RT_WLAN_EVT_MAX) + { + level = rt_hw_interrupt_disable(); + handler = event_tab[user_event].handler; + user_parameter = event_tab[user_event].parameter; + rt_hw_interrupt_enable(level); + } + + /* run user callback fun */ + if (handler) + { + handler(user_event, &user_buff, user_parameter); + } +} + +static struct rt_wlan_complete_des *rt_wlan_complete_create(const char *name) +{ + struct rt_wlan_complete_des *complete; + int i; + + complete = rt_malloc(sizeof(struct rt_wlan_complete_des)); + if (complete == RT_NULL) + { + RT_WLAN_LOG_E("complete event create failed"); + MGNT_UNLOCK(); + return complete; + } + rt_event_init(&complete->complete, name, RT_IPC_FLAG_FIFO); + complete->event_flag = 0; + //protect + COMPLETE_LOCK(); + for (i = 0; i < sizeof(complete_tab) / sizeof(complete_tab[0]); i++) + { + if (complete_tab[i] == RT_NULL) + { + complete->index = i; + complete_tab[i] = complete; + break; + } + } + COMPLETE_UNLOCK(); + + if (i >= sizeof(complete_tab) / sizeof(complete_tab[0])) + { + rt_event_detach(&complete->complete); + rt_free(complete); + complete = RT_NULL; + } + + return complete; +} + +static rt_err_t rt_wlan_complete_wait(struct rt_wlan_complete_des *complete, rt_uint32_t event, + rt_uint32_t timeout, rt_uint32_t *recved) +{ + if (complete == RT_NULL) + { + return -RT_ERROR; + } + + /* Check whether there is a waiting event */ + if (complete->event_flag & event) + { + *recved = complete->event_flag; + return RT_EOK; + } + else + { + return rt_event_recv(&complete->complete, event, RT_EVENT_FLAG_OR, + rt_tick_from_millisecond(timeout), recved); + } +} + +static void rt_wlan_complete_delete(struct rt_wlan_complete_des *complete) +{ + if (complete == RT_NULL) + { + return; + } + COMPLETE_LOCK(); + complete_tab[complete->index] = RT_NULL; + COMPLETE_UNLOCK(); + rt_event_detach(&complete->complete); + rt_free(complete); +} + +rt_err_t rt_wlan_set_mode(const char *dev_name, rt_wlan_mode_t mode) +{ + rt_device_t device = RT_NULL; + rt_err_t err; + rt_int8_t up_event_flag = 0; + rt_wlan_dev_event_handler handler = RT_NULL; + + if ((dev_name == RT_NULL) || (mode >= RT_WLAN_MODE_MAX)) + { + RT_WLAN_LOG_E("Parameter Wrongful name:%s mode:%d", dev_name, mode); + return -RT_EINVAL; + } + + RT_WLAN_LOG_D("%s is run dev_name:%s mode:%s%s%s", __FUNCTION__, dev_name, + mode == RT_WLAN_NONE ? "NONE" : "", + mode == RT_WLAN_STATION ? "STA" : "", + mode == RT_WLAN_AP ? "AP" : "" + ); + + /* find device */ + device = rt_device_find(dev_name); + if (device == RT_NULL) + { + RT_WLAN_LOG_E("not find device, set mode failed! name:%s", dev_name); + return -RT_EIO; + } + + MGNT_LOCK(); + if (RT_WLAN_DEVICE(device)->mode == mode) + { + RT_WLAN_LOG_D("L:%d this device mode is set"); + MGNT_UNLOCK(); + return RT_EOK; + } + + if ((mode == RT_WLAN_STATION) && + (RT_WLAN_DEVICE(device)->flags & RT_WLAN_FLAG_AP_ONLY)) + { + RT_WLAN_LOG_I("this device ap mode only"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + else if ((mode == RT_WLAN_AP) && + (RT_WLAN_DEVICE(device)->flags & RT_WLAN_FLAG_STA_ONLY)) + { + RT_WLAN_LOG_I("this device sta mode only"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + + /* + * device == sta and change to ap, should deinit + * device == ap and change to sta, should deinit + */ + if (((mode == RT_WLAN_STATION) && (RT_WLAN_DEVICE(device) == AP_DEVICE())) || + ((mode == RT_WLAN_AP) && (RT_WLAN_DEVICE(device) == STA_DEVICE()))) + { + err = rt_wlan_set_mode(dev_name, RT_WLAN_NONE); + if (err != RT_EOK) + { + RT_WLAN_LOG_E("change mode failed!"); + MGNT_UNLOCK(); + return err; + } + } + + /* init device */ + err = rt_wlan_dev_init(RT_WLAN_DEVICE(device), mode); + if (err != RT_EOK) + { + RT_WLAN_LOG_E("F:%s L:%d wlan init failed", __FUNCTION__, __LINE__); + MGNT_UNLOCK(); + return err; + } + + /* the mode is none */ + if (mode == RT_WLAN_NONE) + { + if (_sta_mgnt.device == RT_WLAN_DEVICE(device)) + { + _sta_mgnt.device = RT_NULL; + _sta_mgnt.state = 0; + up_event_flag = 1; + handler = RT_NULL; + } + else if (_ap_mgnt.device == RT_WLAN_DEVICE(device)) + { + _ap_mgnt.state = 0; + _ap_mgnt.device = RT_NULL; + up_event_flag = 1; + handler = RT_NULL; + } + } + /* save sta device */ + else if (mode == RT_WLAN_STATION) + { + up_event_flag = 1; + handler = rt_wlan_event_dispatch; + _sta_mgnt.device = RT_WLAN_DEVICE(device); + } + /* save ap device */ + else if (mode == RT_WLAN_AP) + { + up_event_flag = 1; + handler = rt_wlan_event_dispatch; + _ap_mgnt.device = RT_WLAN_DEVICE(device); + } + + /* update dev event handle */ + if (up_event_flag == 1) + { + rt_wlan_dev_event_t event; + for (event = RT_WLAN_DEV_EVT_INIT_DONE; event < RT_WLAN_DEV_EVT_MAX; event++) + { + if (handler) + { + rt_wlan_dev_register_event_handler(RT_WLAN_DEVICE(device), event, handler, RT_NULL); + } + else + { + rt_wlan_dev_unregister_event_handler(RT_WLAN_DEVICE(device), event, handler); + } + } + } + MGNT_UNLOCK(); + + /* Mount protocol */ +#ifdef RT_WLAN_DEFAULT_PROT + rt_wlan_prot_attach(dev_name, RT_WLAN_DEFAULT_PROT); +#endif + return err; +} + +rt_wlan_mode_t rt_wlan_get_mode(const char *dev_name) +{ + rt_device_t device = RT_NULL; + rt_wlan_mode_t mode; + + if (dev_name == RT_NULL) + { + RT_WLAN_LOG_E("name is null"); + return RT_WLAN_NONE; + } + + /* find device */ + device = rt_device_find(dev_name); + if (device == RT_NULL) + { + RT_WLAN_LOG_E("device not find! name:%s", dev_name); + return RT_WLAN_NONE; + } + + /* get mode */ + mode = RT_WLAN_DEVICE(device)->mode; + RT_WLAN_LOG_D("%s is run dev_name:%s mode:%s%s%s", __FUNCTION__, dev_name, + mode == RT_WLAN_NONE ? "NONE" : "", + mode == RT_WLAN_STATION ? "STA" : "", + mode == RT_WLAN_AP ? "AP" : ""); + + return mode; +} + +rt_bool_t rt_wlan_find_best_by_cache(const char *ssid, struct rt_wlan_info *info) +{ + int i, ssid_len; + struct rt_wlan_info *info_best; + struct rt_wlan_scan_result *result; + + ssid_len = rt_strlen(ssid); + result = &scan_result; + info_best = RT_NULL; + + SRESULT_LOCK(); + for (i = 0; i < result->num; i++) + { + /* SSID is equal. */ + if ((result->info[i].ssid.len == ssid_len) && + (rt_memcmp((char *)&result->info[i].ssid.val[0], ssid, ssid_len) == 0)) + { + if (info_best == RT_NULL) + { + info_best = &result->info[i]; + continue; + } + /* Signal strength effective */ + if ((result->info[i].rssi < 0) && (info_best->rssi < 0)) + { + /* Find the strongest signal. */ + if (result->info[i].rssi > info_best->rssi) + { + info_best = &result->info[i]; + continue; + } + else if (result->info[i].rssi < info_best->rssi) + { + continue; + } + } + + /* Finding the fastest signal */ + if (result->info[i].datarate > info_best->datarate) + { + info_best = &result->info[i]; + continue; + } + } + } + SRESULT_UNLOCK(); + + if (info_best == RT_NULL) + return RT_FALSE; + + *info = *info_best; + return RT_TRUE; +} + +rt_err_t rt_wlan_connect(const char *ssid, const char *password) +{ + rt_err_t err = RT_EOK; + int ssid_len = 0; + struct rt_wlan_info info; + struct rt_wlan_complete_des *complete; + rt_uint32_t set = 0, recved = 0; + + /* sta dev Can't be NULL */ + if (_sta_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run ssid:%s password:%s", __FUNCTION__, ssid, password); + if (ssid == RT_NULL) + { + RT_WLAN_LOG_E("ssid is null!"); + return -RT_EINVAL; + } + ssid_len = rt_strlen(ssid); + if (ssid_len > RT_WLAN_SSID_MAX_LENGTH) + { + RT_WLAN_LOG_E("ssid is to long! ssid:%s len:%d", ssid, ssid_len); + return -RT_EINVAL; + } + + if ((rt_wlan_is_connected() == RT_TRUE) && + (rt_strcmp((char *)&_sta_mgnt.info.ssid.val[0], ssid) == 0)) + { + RT_WLAN_LOG_I("wifi is connect ssid:%s", ssid); + return RT_EOK; + } + /* get info from cache */ + INVALID_INFO(&info); + MGNT_LOCK(); + if (rt_wlan_find_best_by_cache(ssid, &info) != RT_TRUE) + { + rt_wlan_scan_sync(); + rt_wlan_find_best_by_cache(ssid, &info); + rt_wlan_scan_result_clean(); + } + + if (info.ssid.len <= 0) + { + RT_WLAN_LOG_W("not find ap! ssid:%s", ssid); + MGNT_UNLOCK(); + return -RT_ERROR; + } + + RT_WLAN_LOG_D("find best info ssid:%s mac: %02x %02x %02x %02x %02x %02x", + info.ssid.val, info.bssid[0], info.bssid[1], info.bssid[2], info.bssid[3], info.bssid[4], info.bssid[5]); + + /* create event wait complete */ + complete = rt_wlan_complete_create("join"); + if (complete == RT_NULL) + { + MGNT_UNLOCK(); + return -RT_ENOMEM; + } + /* run connect adv */ + err = rt_wlan_connect_adv(&info, password); + if (err != RT_EOK) + { + rt_wlan_complete_delete(complete); + MGNT_UNLOCK(); + return err; + } + + /* Initializing events that need to wait */ + set |= 0x1 << RT_WLAN_DEV_EVT_CONNECT; + set |= 0x1 << RT_WLAN_DEV_EVT_CONNECT_FAIL; + /* Check whether there is a waiting event */ + rt_wlan_complete_wait(complete, set, RT_WLAN_CONNECT_WAIT_MS, &recved); + rt_wlan_complete_delete(complete); + /* check event */ + set = 0x1 << RT_WLAN_DEV_EVT_CONNECT; + if (!(recved & set)) + { + RT_WLAN_LOG_I("wifi connect failed!"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_connect_adv(struct rt_wlan_info *info, const char *password) +{ + int password_len = 0; + rt_err_t err = RT_EOK; + + if (_sta_is_null()) + { + return -RT_EIO; + } + if (info == RT_NULL) + { + RT_WLAN_LOG_E("info is null!"); + return -RT_EINVAL; + } + RT_WLAN_LOG_D("%s is run ssid:%s password:%s", __FUNCTION__, info->ssid.val, password); + /* Parameter checking */ + if (password != RT_NULL) + { + password_len = rt_strlen(password); + if (password_len > RT_WLAN_PASSWORD_MAX_LENGTH) + { + RT_WLAN_LOG_E("password is to long! password:%s len:%d", password, password_len); + return -RT_EINVAL; + } + } + if (info->ssid.len == 0 || info->ssid.len > RT_WLAN_SSID_MAX_LENGTH) + { + RT_WLAN_LOG_E("ssid is zero or to long! ssid:%s len:%d", info->ssid.val, info->ssid.len); + return -RT_EINVAL; + } + /* is connect ? */ + MGNT_LOCK(); + if (rt_wlan_is_connected()) + { + if ((_sta_mgnt.info.ssid.len == info->ssid.len) && + (_sta_mgnt.key.len == password_len) && + (rt_memcmp(&_sta_mgnt.info.ssid.val[0], &info->ssid.val[0], info->ssid.len) == 0) && + (rt_memcmp(&_sta_mgnt.info.bssid[0], &info->bssid[0], RT_WLAN_BSSID_MAX_LENGTH) == 0) && + (rt_memcmp(&_sta_mgnt.key.val[0], password, password_len) == 0)) + { + RT_WLAN_LOG_I("wifi Already Connected"); + MGNT_UNLOCK(); + return RT_EOK; + } + + err = rt_wlan_disconnect(); + if (err != RT_EOK) + { + MGNT_UNLOCK(); + return err; + } + } + + /* save info */ + rt_enter_critical(); + _sta_mgnt.info = *info; + rt_memcpy(&_sta_mgnt.key.val, password, password_len); + _sta_mgnt.key.len = password_len; + _sta_mgnt.key.val[password_len] = '\0'; + rt_exit_critical(); + /* run wifi connect */ + _sta_mgnt.state |= RT_WLAN_STATE_CONNECTING; + err = rt_wlan_dev_connect(_sta_mgnt.device, info, password, password_len); + if (err != RT_EOK) + { + rt_enter_critical(); + rt_memset(&_sta_mgnt.info, 0, sizeof(struct rt_wlan_ssid)); + rt_memset(&_sta_mgnt.key, 0, sizeof(struct rt_wlan_key)); + rt_exit_critical(); + _sta_mgnt.state &= ~RT_WLAN_STATE_CONNECTING; + MGNT_UNLOCK(); + return err; + } + + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_disconnect(void) +{ + rt_err_t err; + struct rt_wlan_complete_des *complete; + rt_uint32_t recved = 0, set = 0; + + /* ap dev Can't be empty */ + if (_sta_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + + /* run disconnect */ + MGNT_LOCK(); + /* create event wait complete */ + complete = rt_wlan_complete_create("disc"); + if (complete == RT_NULL) + { + MGNT_UNLOCK(); + return -RT_ENOMEM; + } + err = rt_wlan_dev_disconnect(_sta_mgnt.device); + if (err != RT_EOK) + { + RT_WLAN_LOG_E("wifi disconnect fail"); + rt_wlan_complete_delete(complete); + MGNT_UNLOCK(); + return err; + } + /* Initializing events that need to wait */ + set |= 0x1 << RT_WLAN_DEV_EVT_DISCONNECT; + /* Check whether there is a waiting event */ + rt_wlan_complete_wait(complete, set, RT_WLAN_CONNECT_WAIT_MS, &recved); + rt_wlan_complete_delete(complete); + /* check event */ + set = 0x1 << RT_WLAN_DEV_EVT_DISCONNECT; + if (!(recved & set)) + { + RT_WLAN_LOG_E("disconnect failed!"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + RT_WLAN_LOG_I("disconnect success!"); + MGNT_UNLOCK(); + return err; +} + +rt_bool_t rt_wlan_is_connected(void) +{ + rt_bool_t _connect; + + if (_sta_is_null()) + { + return RT_FALSE; + } + _connect = _sta_mgnt.state & RT_WLAN_STATE_CONNECT ? RT_TRUE : RT_FALSE; + RT_WLAN_LOG_D("%s is run : %s", __FUNCTION__, _connect ? "connect" : "disconnect"); + return _connect; +} + +rt_bool_t rt_wlan_is_ready(void) +{ + rt_bool_t _ready; + + if (_sta_is_null()) + { + return RT_FALSE; + } + _ready = _sta_mgnt.state & RT_WLAN_STATE_READY ? RT_TRUE : RT_FALSE; + RT_WLAN_LOG_D("%s is run : %s", __FUNCTION__, _ready ? "ready" : "not ready"); + return _ready; +} + +rt_err_t rt_wlan_set_mac(rt_uint8_t mac[6]) +{ + rt_err_t err = RT_EOK; + + if (_sta_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run mac: %02x:%02x:%02x:%02x:%02x:%02x", + __FUNCTION__, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + MGNT_LOCK(); + err = rt_wlan_dev_set_mac(STA_DEVICE(), mac); + if (err != RT_EOK) + { + RT_WLAN_LOG_E("set sta mac addr fail"); + MGNT_UNLOCK(); + return err; + } + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_get_mac(rt_uint8_t mac[6]) +{ + rt_err_t err = RT_EOK; + + if (_sta_is_null()) + { + return -RT_EIO; + } + MGNT_LOCK(); + err = rt_wlan_dev_get_mac(STA_DEVICE(), mac); + if (err != RT_EOK) + { + RT_WLAN_LOG_E("get sta mac addr fail"); + MGNT_UNLOCK(); + return err; + } + RT_WLAN_LOG_D("%s is run mac: %02x:%02x:%02x:%02x:%02x:%02x", + __FUNCTION__, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_get_info(struct rt_wlan_info *info) +{ + if (_sta_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + + rt_enter_critical(); + *info = _sta_mgnt.info; + rt_exit_critical(); + return RT_EOK; +} + +int rt_wlan_get_rssi(void) +{ + int rssi = 0; + + if (_sta_is_null()) + { + return -RT_EIO; + } + + MGNT_LOCK(); + rssi = rt_wlan_dev_get_rssi(STA_DEVICE()); + RT_WLAN_LOG_D("%s is run rssi:%d", __FUNCTION__, rssi); + MGNT_UNLOCK(); + return rssi; +} + +rt_err_t rt_wlan_start_ap(const char *ssid, const char *password) +{ + rt_err_t err = RT_EOK; + int ssid_len = 0; + struct rt_wlan_info info; + struct rt_wlan_complete_des *complete; + rt_uint32_t set = 0, recved = 0; + + if (_ap_is_null()) + { + return -RT_EIO; + } + if (ssid == RT_NULL) return -RT_EINVAL; + + rt_memset(&info, 0, sizeof(struct rt_wlan_info)); + RT_WLAN_LOG_D("%s is run ssid:%s password:%s", __FUNCTION__, ssid, password); + if (password) + { + info.security = SECURITY_WPA2_AES_PSK; + } + ssid_len = rt_strlen(ssid); + if (ssid_len > RT_WLAN_SSID_MAX_LENGTH) + { + RT_WLAN_LOG_E("ssid is to long! len:%d", ssid_len); + } + + /* copy info */ + rt_memcpy(&info.ssid.val, ssid, ssid_len); + info.ssid.len = ssid_len; + info.channel = 6; + + /* Initializing events that need to wait */ + MGNT_LOCK(); + /* create event wait complete */ + complete = rt_wlan_complete_create("start_ap"); + if (complete == RT_NULL) + { + MGNT_UNLOCK(); + return -RT_ENOMEM; + } + + /* start ap */ + err = rt_wlan_start_ap_adv(&info, password); + if (err != RT_EOK) + { + rt_wlan_complete_delete(complete); + RT_WLAN_LOG_I("start ap failed!"); + MGNT_UNLOCK(); + return err; + } + + /* Initializing events that need to wait */ + set |= 0x1 << RT_WLAN_DEV_EVT_AP_START; + set |= 0x1 << RT_WLAN_DEV_EVT_AP_STOP; + /* Check whether there is a waiting event */ + rt_wlan_complete_wait(complete, set, RT_WLAN_START_AP_WAIT_MS, &recved); + rt_wlan_complete_delete(complete); + /* check event */ + set = 0x1 << RT_WLAN_DEV_EVT_AP_START; + if (!(recved & set)) + { + RT_WLAN_LOG_I("start ap failed!"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + RT_WLAN_LOG_I("start ap successs!"); + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_start_ap_adv(struct rt_wlan_info *info, const char *password) +{ + rt_err_t err = RT_EOK; + int password_len = 0; + + if (_ap_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + password_len = rt_strlen(password); + if (password_len > RT_WLAN_PASSWORD_MAX_LENGTH) + { + RT_WLAN_LOG_E("key is to long! len:%d", password_len); + return -RT_EINVAL; + } + /* is start up ? */ + MGNT_LOCK(); + if (rt_wlan_ap_is_active()) + { + if ((_ap_mgnt.info.ssid.len == info->ssid.len) && + (_ap_mgnt.info.security == info->security) && + (_ap_mgnt.info.channel == info->channel) && + (_ap_mgnt.info.hidden == info->hidden) && + (_ap_mgnt.key.len == password_len) && + (rt_memcmp(&_ap_mgnt.info.ssid.val[0], &info->ssid.val[0], info->ssid.len) == 0) && + (rt_memcmp(&_ap_mgnt.key.val[0], password, password_len))) + { + RT_WLAN_LOG_D("wifi Already Start"); + MGNT_UNLOCK(); + return RT_EOK; + } + } + + err = rt_wlan_dev_ap_start(AP_DEVICE(), info, password, password_len); + if (err != RT_EOK) + { + MGNT_UNLOCK(); + return err; + } + rt_memcpy(&_ap_mgnt.info, info, sizeof(struct rt_wlan_info)); + rt_memcpy(&_ap_mgnt.key.val, password, password_len); + _ap_mgnt.key.len = password_len; + + MGNT_UNLOCK(); + return err; +} + +int rt_wlan_ap_is_active(void) +{ + int _active = 0; + + if (_ap_is_null()) + { + return 0; + } + + _active = _ap_mgnt.state & RT_WLAN_STATE_ACTIVE ? 1 : 0; + RT_WLAN_LOG_D("%s is run active:%s", __FUNCTION__, _active ? "Active" : "Inactive"); + return _active; +} + +rt_err_t rt_wlan_ap_stop(void) +{ + rt_err_t err = RT_EOK; + struct rt_wlan_complete_des *complete; + rt_uint32_t set = 0, recved = 0; + + if (_ap_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + + MGNT_LOCK(); + /* create event wait complete */ + complete = rt_wlan_complete_create("stop_ap"); + if (complete == RT_NULL) + { + MGNT_UNLOCK(); + return -RT_ENOMEM; + } + err = rt_wlan_dev_ap_stop(AP_DEVICE()); + if (err != RT_EOK) + { + RT_WLAN_LOG_E("ap stop fail"); + rt_wlan_complete_delete(complete); + MGNT_UNLOCK(); + return err; + } + /* Initializing events that need to wait */ + set |= 0x1 << RT_WLAN_DEV_EVT_AP_STOP; + /* Check whether there is a waiting event */ + rt_wlan_complete_wait(complete, set, RT_WLAN_START_AP_WAIT_MS, &recved); + rt_wlan_complete_delete(complete); + /* check event */ + set = 0x1 << RT_WLAN_DEV_EVT_AP_STOP; + if (!(recved & set)) + { + RT_WLAN_LOG_I("ap stop failed!"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + RT_WLAN_LOG_I("ap stop success!"); + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_ap_get_info(struct rt_wlan_info *info) +{ + if (_ap_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + + *info = _ap_mgnt.info; + return RT_EOK; +} + +/* get sta number */ +int rt_wlan_ap_get_sta_num(void) +{ + int sta_num = 0; + + STAINFO_LOCK(); + sta_num = sta_info.num; + STAINFO_UNLOCK(); + RT_WLAN_LOG_D("%s is run num:%d", __FUNCTION__, sta_num); + return sta_num; +} + +/* get sta info */ +int rt_wlan_ap_get_sta_info(struct rt_wlan_info *info, int num) +{ + int sta_num = 0, i = 0; + struct rt_wlan_sta_list *sta_list; + + STAINFO_LOCK(); + /* sta_num = min(sta_info.num, num) */ + sta_num = sta_info.num > num ? num : sta_info.num; + for (sta_list = sta_info.node; sta_list != RT_NULL && i < sta_num; sta_list = sta_list->next) + { + info[i] = sta_list->info; + i ++; + } + STAINFO_UNLOCK(); + RT_WLAN_LOG_D("%s is run num:%d", __FUNCTION__, i); + return i; +} + +/* deauth sta */ +rt_err_t rt_wlan_ap_deauth_sta(rt_uint8_t *mac) +{ + rt_err_t err = RT_EOK; + struct rt_wlan_sta_list *sta_list; + rt_bool_t find_flag = RT_FALSE; + + if (_ap_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run mac: %02x:%02x:%02x:%02x:%02x:%02x:%d", + __FUNCTION__, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + if (mac == RT_NULL) + { + RT_WLAN_LOG_E("mac addr is null"); + return -RT_EINVAL; + } + + MGNT_LOCK(); + if (sta_info.node == RT_NULL || sta_info.num == 0) + { + RT_WLAN_LOG_E("No AP"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + + STAINFO_LOCK(); + /* Search for MAC address from sta list */ + for (sta_list = sta_info.node; sta_list != RT_NULL; sta_list = sta_list->next) + { + if (rt_memcmp(&sta_list->info.bssid[0], &mac[0], RT_WLAN_BSSID_MAX_LENGTH) == 0) + { + find_flag = RT_TRUE; + break; + } + } + STAINFO_UNLOCK(); + + /* No MAC address was found. return */ + if (find_flag != RT_TRUE) + { + RT_WLAN_LOG_E("Not find mac addr"); + MGNT_UNLOCK(); + return -RT_ERROR; + } + + /* Kill STA */ + err = rt_wlan_dev_ap_deauth(AP_DEVICE(), mac); + if (err != RT_NULL) + { + RT_WLAN_LOG_E("deauth sta failed"); + MGNT_UNLOCK(); + return err; + } + + MGNT_UNLOCK(); + return err; +} + +rt_err_t rt_wlan_ap_set_country(rt_country_code_t country_code) +{ + rt_err_t err = RT_EOK; + + if (_ap_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run country:%d", __FUNCTION__, country_code); + MGNT_LOCK(); + err = rt_wlan_dev_set_country(AP_DEVICE(), country_code); + MGNT_UNLOCK(); + return err; +} + +rt_country_code_t rt_wlan_ap_get_country(void) +{ + rt_country_code_t country_code = RT_COUNTRY_UNKNOWN; + + if (_ap_is_null()) + { + return country_code; + } + MGNT_LOCK(); + country_code = rt_wlan_dev_get_country(AP_DEVICE()); + RT_WLAN_LOG_D("%s is run country:%d", __FUNCTION__, country_code); + MGNT_UNLOCK(); + return country_code; +} + +void rt_wlan_config_autoreconnect(rt_bool_t enable) +{ + RT_WLAN_LOG_D("%s is run enable:%d", __FUNCTION__, enable); + + MGNT_LOCK(); + if (enable) + { + _sta_mgnt.flags |= RT_WLAN_STATE_AUTOEN; + } + else + { + _sta_mgnt.flags &= ~RT_WLAN_STATE_AUTOEN; + } + MGNT_UNLOCK(); +} + +rt_bool_t rt_wlan_get_autoreconnect_mode(void) +{ + rt_bool_t enable = 0; + + enable = _sta_mgnt.flags & RT_WLAN_STATE_AUTOEN ? 1 : 0; + RT_WLAN_LOG_D("%s is run enable:%d", __FUNCTION__, enable); + return enable; +} + +/* Call the underlying scan function, which is asynchronous. +The hotspots scanned are returned by callbacks */ +rt_err_t rt_wlan_scan(void) +{ + rt_err_t err = RT_EOK; + + if (_sta_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + + MGNT_LOCK(); + err = rt_wlan_dev_scan(STA_DEVICE(), RT_NULL); + MGNT_UNLOCK(); + return err; +} + +struct rt_wlan_scan_result *rt_wlan_scan_sync(void) +{ + struct rt_wlan_scan_result *result; + + /* Execute synchronous scan function */ + MGNT_LOCK(); + result = rt_wlan_scan_with_info(RT_NULL); + MGNT_UNLOCK(); + return result; +} + +struct rt_wlan_scan_result *rt_wlan_scan_with_info(struct rt_wlan_info *info) +{ + rt_err_t err = RT_EOK; + struct rt_wlan_complete_des *complete; + rt_uint32_t set = 0, recved = 0; + + if (_sta_is_null()) + { + return RT_NULL; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + if (info != RT_NULL && info->ssid.len > RT_WLAN_SSID_MAX_LENGTH) + { + RT_WLAN_LOG_E("ssid is to long!"); + return RT_NULL; + } + + /* Create an event that needs to wait. */ + MGNT_LOCK(); + complete = rt_wlan_complete_create("scan"); + if (complete == RT_NULL) + { + MGNT_UNLOCK(); + return &scan_result; + } + + /* run scan */ + err = rt_wlan_dev_scan(STA_DEVICE(), info); + if (err != RT_EOK) + { + rt_wlan_complete_delete(complete); + RT_WLAN_LOG_E("scan sync fail"); + MGNT_UNLOCK(); + return RT_NULL; + } + + /* Initializing events that need to wait */ + set |= 0x1 << RT_WLAN_DEV_EVT_SCAN_DONE; + /* Check whether there is a waiting event */ + rt_wlan_complete_wait(complete, set, RT_WLAN_CONNECT_WAIT_MS, &recved); + rt_wlan_complete_delete(complete); + /* check event */ + set = 0x1 << RT_WLAN_DEV_EVT_SCAN_DONE; + if (!(recved & set)) + { + RT_WLAN_LOG_E("scan wait timeout!"); + MGNT_UNLOCK(); + return &scan_result; + } + + MGNT_UNLOCK(); + return &scan_result; +} + +int rt_wlan_scan_get_info_num(void) +{ + int num = 0; + + num = scan_result.num; + RT_WLAN_LOG_D("%s is run num:%d", __FUNCTION__, num); + return num; +} + +int rt_wlan_scan_get_info(struct rt_wlan_info *info, int num) +{ + int _num = 0; + + SRESULT_LOCK(); + if (scan_result.num && num > 0) + { + _num = scan_result.num > num ? num : scan_result.num; + rt_memcpy(info, scan_result.info, _num * sizeof(struct rt_wlan_info)); + } + SRESULT_UNLOCK(); + return _num; +} + +struct rt_wlan_scan_result *rt_wlan_scan_get_result(void) +{ + return &scan_result; +} + +void rt_wlan_scan_result_clean(void) +{ + MGNT_LOCK(); + SRESULT_LOCK(); + + /* If there is data */ + if (scan_result.num) + { + scan_result.num = 0; + rt_free(scan_result.info); + scan_result.info = RT_NULL; + } + SRESULT_UNLOCK(); + MGNT_UNLOCK(); +} + +int rt_wlan_scan_find_cache(struct rt_wlan_info *info, struct rt_wlan_info *out_info, int num) +{ + int i = 0, count = 0; + struct rt_wlan_info *scan_info; + rt_bool_t is_equ = 1; + rt_uint8_t bssid_zero[RT_WLAN_BSSID_MAX_LENGTH] = { 0 }; + + if ((out_info == RT_NULL) || (info == RT_NULL) || (num <= 0)) + { + return 0; + } + SRESULT_LOCK(); + /* Traversing the cache to find a qualified hot spot information */ + for (i = 0; (i < scan_result.num) && (count < num); i++) + { + scan_info = &scan_result.info[i]; + + if (is_equ && (info->security != SECURITY_UNKNOWN)) + { + is_equ &= info->security == scan_info->security; + } + if (is_equ && ((info->ssid.len > 0) && (info->ssid.len == scan_info->ssid.len))) + { + is_equ &= rt_memcmp(&info->ssid.val[0], &scan_info->ssid.val[0], scan_info->ssid.len) == 0; + } + if (is_equ && (rt_memcmp(&info->bssid[0], bssid_zero, RT_WLAN_BSSID_MAX_LENGTH))) + { + is_equ &= rt_memcmp(&info->bssid[0], &scan_info->bssid[0], RT_WLAN_BSSID_MAX_LENGTH) == 0; + } + if (is_equ && info->datarate) + { + is_equ &= info->datarate == scan_info->datarate; + } + if (is_equ && (info->channel >= 0)) + { + is_equ &= info->channel == scan_info->channel; + } + if (is_equ && (info->rssi < 0)) + { + is_equ &= info->rssi == scan_info->rssi; + } + /* Determine whether to find */ + if (is_equ) + { + rt_memcpy(&out_info[count], scan_info, sizeof(struct rt_wlan_info)); + count ++; + } + } + SRESULT_UNLOCK(); + + return count; +} + +rt_err_t rt_wlan_set_powersave(int level) +{ + rt_err_t err = RT_EOK; + + if (_sta_is_null()) + { + return -RT_EIO; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + MGNT_LOCK(); + err = rt_wlan_dev_set_powersave(STA_DEVICE(), level); + MGNT_UNLOCK(); + return err; +} + +int rt_wlan_get_powersave(void) +{ + int level; + + if (_sta_is_null()) + { + return -1; + } + RT_WLAN_LOG_D("%s is run", __FUNCTION__); + MGNT_LOCK(); + level = rt_wlan_dev_get_powersave(STA_DEVICE()); + MGNT_UNLOCK(); + return level; +} + +rt_err_t rt_wlan_register_event_handler(rt_wlan_event_t event, rt_wlan_event_handler handler, void *parameter) +{ + rt_base_t level; + + if (event >= RT_WLAN_EVT_MAX) + { + return RT_EINVAL; + } + RT_WLAN_LOG_D("%s is run event:%d", __FUNCTION__, event); + + MGNT_UNLOCK(); + /* Registering Callbacks */ + level = rt_hw_interrupt_disable(); + event_tab[event].handler = handler; + event_tab[event].parameter = parameter; + rt_hw_interrupt_enable(level); + MGNT_UNLOCK(); + return RT_EOK; +} + +rt_err_t rt_wlan_unregister_event_handler(rt_wlan_event_t event) +{ + rt_base_t level; + + if (event >= RT_WLAN_EVT_MAX) + { + return RT_EINVAL; + } + RT_WLAN_LOG_D("%s is run event:%d", __FUNCTION__, event); + MGNT_LOCK(); + /* unregister*/ + level = rt_hw_interrupt_disable(); + event_tab[event].handler = RT_NULL; + event_tab[event].parameter = RT_NULL; + rt_hw_interrupt_enable(level); + MGNT_UNLOCK(); + return RT_EOK; +} + +void rt_wlan_mgnt_lock(void) +{ + MGNT_LOCK(); +} + +void rt_wlan_mgnt_unlock(void) +{ + MGNT_UNLOCK(); +} + +int rt_wlan_prot_ready_event(struct rt_wlan_device *wlan, struct rt_wlan_buff *buff) +{ + rt_base_t level; + void *user_parameter; + rt_wlan_event_handler handler = RT_NULL; + + if ((wlan == RT_NULL) || (_sta_mgnt.device != wlan) || + (!(_sta_mgnt.state & RT_WLAN_STATE_CONNECT))) + { + return -1; + } + if (_sta_mgnt.state & RT_WLAN_STATE_READY) + { + return 0; + } + level = rt_hw_interrupt_disable(); + _sta_mgnt.state |= RT_WLAN_STATE_READY; + handler = event_tab[RT_WLAN_EVT_READY].handler; + user_parameter = event_tab[RT_WLAN_EVT_READY].parameter; + rt_hw_interrupt_enable(level); + if (handler) + { + handler(RT_WLAN_EVT_READY, buff, user_parameter); + } + return 0; +} + +int rt_wlan_init(void) +{ + static rt_int8_t _init_flag = 0; + + /* Execute only once */ + if (_init_flag == 0) + { + rt_memset(&_sta_mgnt, 0, sizeof(struct rt_wlan_mgnt_des)); + rt_memset(&_ap_mgnt, 0, sizeof(struct rt_wlan_mgnt_des)); + rt_memset(&scan_result, 0, sizeof(struct rt_wlan_scan_result)); + rt_memset(&sta_info, 0, sizeof(struct rt_wlan_sta_des)); + rt_mutex_init(&mgnt_mutex, "mgnt", RT_IPC_FLAG_FIFO); + rt_mutex_init(&scan_result_mutex, "scan", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sta_info_mutex, "sta", RT_IPC_FLAG_FIFO); + rt_mutex_init(&complete_mutex, "complete", RT_IPC_FLAG_FIFO); + rt_timer_init(&reconnect_time, "wifi_tim", rt_wlan_cyclic_check, RT_NULL, DISCONNECT_RESPONSE_TICK, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + rt_timer_start(&reconnect_time); + _init_flag = 1; + } + return 0; +} +INIT_PREV_EXPORT(rt_wlan_init); diff --git a/components/drivers/wlan/wlan_mgnt.h b/components/drivers/wlan/wlan_mgnt.h index b00414c6e2..d11d9ee347 100644 --- a/components/drivers/wlan/wlan_mgnt.h +++ b/components/drivers/wlan/wlan_mgnt.h @@ -1,34 +1,150 @@ /* - * RT-Thread Wi-Fi Device + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2014 - 2018, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-02-27 EvalZero the first verion + * 2018-08-06 tyx the first version */ #ifndef __WLAN_MGNT_H__ #define __WLAN_MGNT_H__ -int rt_wlan_mgnt_attach(struct rt_wlan_device *device, void *user_data); +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef RT_WLAN_SCAN_WAIT_MS +#define RT_WLAN_SCAN_WAIT_MS (10 * 1000) +#endif + +#ifndef RT_WLAN_SCAN_CACHE_NUM +#define RT_WLAN_SCAN_CACHE_NUM (50) +#endif + +#ifndef RT_WLAN_CONNECT_WAIT_MS +#define RT_WLAN_CONNECT_WAIT_MS (10 * 1000) +#endif + +#ifndef RT_WLAN_START_AP_WAIT_MS +#define RT_WLAN_START_AP_WAIT_MS (10 * 1000) +#endif + +#ifndef RT_WLAN_EBOX_NUM +#define RT_WLAN_EBOX_NUM (10) +#endif + +/*state fot station*/ +#define RT_WLAN_STATE_CONNECT (1UL << 0) +#define RT_WLAN_STATE_CONNECTING (1UL << 1) +#define RT_WLAN_STATE_READY (1UL << 2) +#define RT_WLAN_STATE_POWERSAVE (1UL << 3) + +/*flags fot station*/ +#define RT_WLAN_STATE_AUTOEN (1UL << 0) + +/*state fot ap*/ +#define RT_WLAN_STATE_ACTIVE (1UL << 0) + +typedef enum +{ + RT_WLAN_EVT_READY = 0, /* connect and prot is ok, You can send data*/ + RT_WLAN_EVT_SCAN_DONE, /* Scan a info */ + RT_WLAN_EVT_SCAN_REPORT, /* Scan end */ + RT_WLAN_EVT_STA_CONNECTED, /* connect success */ + RT_WLAN_EVT_STA_CONNECTED_FAIL, /* connection failed */ + RT_WLAN_EVT_STA_DISCONNECTED, /* disconnect */ + RT_WLAN_EVT_AP_START, /* AP start */ + RT_WLAN_EVT_AP_STOP, /* AP stop */ + RT_WLAN_EVT_AP_ASSOCIATED, /* sta associated */ + RT_WLAN_EVT_AP_DISASSOCIATED, /* sta disassociated */ + RT_WLAN_EVT_MAX +} rt_wlan_event_t; + +typedef void (*rt_wlan_event_handler)(int event, struct rt_wlan_buff *buff, void *parameter); + +struct rt_wlan_scan_result +{ + rt_int32_t num; + struct rt_wlan_info *info; +}; + +/* + * wifi init interface + */ +int rt_wlan_init(void); +rt_err_t rt_wlan_set_mode(const char *dev_name, rt_wlan_mode_t mode); +rt_wlan_mode_t rt_wlan_get_mode(const char *dev_name); + +/* + * wifi station mode interface + */ +rt_err_t rt_wlan_connect(const char *ssid, const char *password); +rt_err_t rt_wlan_connect_adv(struct rt_wlan_info *info, const char *password); +rt_err_t rt_wlan_disconnect(void); +rt_bool_t rt_wlan_is_connected(void); +rt_bool_t rt_wlan_is_ready(void); +rt_err_t rt_wlan_set_mac(rt_uint8_t *mac); +rt_err_t rt_wlan_get_mac(rt_uint8_t *mac); +rt_err_t rt_wlan_get_info(struct rt_wlan_info *info); +int rt_wlan_get_rssi(void); + +/* + * wifi ap mode interface + */ +rt_err_t rt_wlan_start_ap(const char *ssid, const char *password); +rt_err_t rt_wlan_start_ap_adv(struct rt_wlan_info *info, const char *password); +int rt_wlan_ap_is_active(void); +rt_err_t rt_wlan_ap_stop(void); +rt_err_t rt_wlan_ap_get_info(struct rt_wlan_info *info); +int rt_wlan_ap_get_sta_num(void); +int rt_wlan_ap_get_sta_info(struct rt_wlan_info *info, int num); +rt_err_t rt_wlan_ap_deauth_sta(rt_uint8_t *mac); +rt_err_t rt_wlan_ap_set_country(rt_country_code_t country_code); +rt_country_code_t rt_wlan_ap_get_country(void); + +/* + * wifi scan interface + */ +rt_err_t rt_wlan_scan(void); +struct rt_wlan_scan_result *rt_wlan_scan_sync(void); +struct rt_wlan_scan_result *rt_wlan_scan_with_info(struct rt_wlan_info *info); +int rt_wlan_scan_get_info_num(void); +int rt_wlan_scan_get_info(struct rt_wlan_info *info, int num); +struct rt_wlan_scan_result *rt_wlan_scan_get_result(void); +void rt_wlan_scan_result_clean(void); +int rt_wlan_scan_find_cache(struct rt_wlan_info *info, struct rt_wlan_info *out_info, int num); +rt_bool_t rt_wlan_find_best_by_cache(const char *ssid, struct rt_wlan_info *info); + +/* + * wifi auto connect interface + */ +void rt_wlan_config_autoreconnect(rt_bool_t enable); +rt_bool_t rt_wlan_get_autoreconnect_mode(void); + +/* + * wifi power management interface + */ +rt_err_t rt_wlan_set_powersave(int level); +int rt_wlan_get_powersave(void); + +/* + * wifi event management interface + */ +rt_err_t rt_wlan_register_event_handler(rt_wlan_event_t event, rt_wlan_event_handler handler, void *parameter); +rt_err_t rt_wlan_unregister_event_handler(rt_wlan_event_t event); + +/* + * wifi management lock interface + */ +void rt_wlan_mgnt_lock(void); +void rt_wlan_mgnt_unlock(void); + +#ifdef __cplusplus +} +#endif #endif diff --git a/components/drivers/wlan/wlan_prot.c b/components/drivers/wlan/wlan_prot.c new file mode 100644 index 0000000000..ec5e419bc4 --- /dev/null +++ b/components/drivers/wlan/wlan_prot.c @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-14 tyx the first version + */ + +#include +#include +#include +#include + +#define DBG_ENABLE +#ifdef RT_WLAN_PROT_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif +#define DBG_SECTION_NAME "WLAN.prot" +#define DBG_COLOR +#include + +#if RT_WLAN_PROT_NAME_LEN < 4 +#error "The name is too short" +#endif + +struct rt_wlan_prot_event_des +{ + rt_wlan_prot_event_handler handler; + struct rt_wlan_prot *prot; +}; + +static struct rt_wlan_prot *_prot[RT_WLAN_PROT_MAX]; + +static struct rt_wlan_prot_event_des prot_event_tab[RT_WLAN_PROT_EVT_MAX][RT_WLAN_PROT_MAX]; + +static void rt_wlan_prot_event_handle(struct rt_wlan_device *wlan, rt_wlan_dev_event_t event, struct rt_wlan_buff *buff, void *parameter) +{ + int i; + struct rt_wlan_prot *wlan_prot; + struct rt_wlan_prot *prot; + rt_wlan_prot_event_handler handler; + rt_wlan_prot_event_t prot_event; + + LOG_D("F:%s L:%d event:%d", __FUNCTION__, __LINE__, event); + + wlan_prot = wlan->prot; + handler = RT_NULL; + prot = RT_NULL; + switch (event) + { + case RT_WLAN_DEV_EVT_INIT_DONE: + { + LOG_D("L%d event: INIT_DONE", __LINE__); + prot_event = RT_WLAN_PROT_EVT_INIT_DONE; + break; + } + case RT_WLAN_DEV_EVT_CONNECT: + { + LOG_D("L%d event: CONNECT", __LINE__); + prot_event = RT_WLAN_PROT_EVT_CONNECT; + break; + } + case RT_WLAN_DEV_EVT_DISCONNECT: + { + LOG_D("L%d event: DISCONNECT", __LINE__); + prot_event = RT_WLAN_PROT_EVT_DISCONNECT; + break; + } + case RT_WLAN_DEV_EVT_AP_START: + { + LOG_D("L%d event: AP_START", __LINE__); + prot_event = RT_WLAN_PROT_EVT_AP_START; + break; + } + case RT_WLAN_DEV_EVT_AP_STOP: + { + LOG_D("L%d event: AP_STOP", __LINE__); + prot_event = RT_WLAN_PROT_EVT_AP_STOP; + break; + } + case RT_WLAN_DEV_EVT_AP_ASSOCIATED: + { + LOG_D("L%d event: AP_ASSOCIATED", __LINE__); + prot_event = RT_WLAN_PROT_EVT_AP_ASSOCIATED; + break; + } + case RT_WLAN_DEV_EVT_AP_DISASSOCIATED: + { + LOG_D("L%d event: AP_DISASSOCIATED", __LINE__); + prot_event = RT_WLAN_PROT_EVT_AP_DISASSOCIATED; + break; + } + default: + { + return; + } + } + for (i = 0; i < RT_WLAN_PROT_MAX; i++) + { + if ((prot_event_tab[prot_event][i].handler != RT_NULL) && + (prot_event_tab[prot_event][i].prot->id == wlan_prot->id)) + { + handler = prot_event_tab[prot_event][i].handler; + prot = prot_event_tab[prot_event][i].prot; + break; + } + } + + if (handler != RT_NULL) + { + handler(prot, wlan, prot_event); + } +} + +static struct rt_wlan_device *rt_wlan_prot_find_by_name(const char *name) +{ + rt_device_t device; + + if (name == RT_NULL) + { + LOG_E("F:%s L:%d Parameter Wrongful", __FUNCTION__, __LINE__); + return RT_NULL; + } + device = rt_device_find(name); + if (device == RT_NULL) + { + LOG_E("F:%s L:%d not find wlan dev!! name:%s", __FUNCTION__, __LINE__, name); + return RT_NULL; + } + return (struct rt_wlan_device *)device; +} + +rt_err_t rt_wlan_prot_attach(const char *dev_name, const char *prot_name) +{ + struct rt_wlan_device *wlan; + + wlan = rt_wlan_prot_find_by_name(dev_name); + if (wlan == RT_NULL) + { + return -RT_ERROR; + } + return rt_wlan_prot_attach_dev(wlan, prot_name); +} + +rt_err_t rt_wlan_prot_detach(const char *name) +{ + struct rt_wlan_device *wlan; + + wlan = rt_wlan_prot_find_by_name(name); + if (wlan == RT_NULL) + { + return -RT_ERROR; + } + return rt_wlan_prot_detach_dev(wlan); +} + +rt_err_t rt_wlan_prot_attach_dev(struct rt_wlan_device *wlan, const char *prot_name) +{ + int i = 0; + struct rt_wlan_prot *prot = wlan->prot; + rt_wlan_dev_event_t event; + + if (wlan == RT_NULL) + { + LOG_E("F:%s L:%d wlan is null", __FUNCTION__, __LINE__); + return -RT_ERROR; + } + + if (prot != RT_NULL && + (rt_strcmp(prot->name, prot_name) == 0)) + { + LOG_D("prot is register"); + return RT_EOK; + } + + /* if prot not NULL */ + if (prot != RT_NULL) + rt_wlan_prot_detach_dev(wlan); + +#ifdef RT_WLAN_PROT_LWIP_PBUF_FORCE + if (rt_strcmp(RT_WLAN_PROT_LWIP, prot_name) != 0) + { + return -RT_ERROR; + } +#endif + /* find prot */ + for (i = 0; i < RT_WLAN_PROT_MAX; i++) + { + if ((_prot[i] != RT_NULL) && (rt_strcmp(_prot[i]->name, prot_name) == 0)) + { + /* attach prot */ + wlan->prot = _prot[i]->ops->dev_reg_callback(_prot[i], wlan); + break; + } + } + + if (i >= RT_WLAN_PROT_MAX) + { + LOG_E("F:%s L:%d not find wlan protocol", __FUNCTION__, __LINE__); + return -RT_ERROR; + } + + for (event = RT_WLAN_DEV_EVT_INIT_DONE; event < RT_WLAN_DEV_EVT_MAX; event ++) + { + if (rt_wlan_dev_register_event_handler(wlan, event, rt_wlan_prot_event_handle, RT_NULL) != RT_EOK) + { + LOG_E("prot register event filed:%d", event); + } + } + + return RT_EOK; +} + +rt_err_t rt_wlan_prot_detach_dev(struct rt_wlan_device *wlan) +{ + struct rt_wlan_prot *prot = wlan->prot; + rt_wlan_dev_event_t event; + + if (prot == RT_NULL) + return RT_EOK; + + for (event = RT_WLAN_DEV_EVT_INIT_DONE; event < RT_WLAN_DEV_EVT_MAX; event ++) + { + rt_wlan_dev_unregister_event_handler(wlan, event, rt_wlan_prot_event_handle); + } + + /* detach prot */ + prot->ops->dev_unreg_callback(prot, wlan); + wlan->prot = RT_NULL; + + return RT_EOK; +} + +rt_err_t rt_wlan_prot_regisetr(struct rt_wlan_prot *prot) +{ + int i; + rt_uint32_t id; + static rt_uint8_t num; + + /* Parameter checking */ + if ((prot == RT_NULL) || + (prot->ops->prot_recv == RT_NULL) || + (prot->ops->dev_reg_callback == RT_NULL)) + { + LOG_E("F:%s L:%d Parameter Wrongful", __FUNCTION__, __LINE__); + return -RT_EINVAL; + } + + /* save prot */ + for (i = 0; i < RT_WLAN_PROT_MAX; i++) + { + if (_prot[i] == RT_NULL) + { + id = (RT_LWAN_ID_PREFIX << 16) | num; + prot->id = id; + _prot[i] = prot; + num ++; + break; + } + else if (rt_strcmp(_prot[i]->name, prot->name) == 0) + { + break; + } + } + + /* is full */ + if (i >= RT_WLAN_PROT_MAX) + { + LOG_E("F:%s L:%d Space full", __FUNCTION__, __LINE__); + return -RT_ERROR; + } + + return RT_EOK; +} + +rt_err_t rt_wlan_prot_event_register(struct rt_wlan_prot *prot, rt_wlan_prot_event_t event, rt_wlan_prot_event_handler handler) +{ + int i; + + if ((prot == RT_NULL) || (handler == RT_NULL)) + { + return -RT_EINVAL; + } + + for (i = 0; i < RT_WLAN_PROT_MAX; i++) + { + if (prot_event_tab[event][i].handler == RT_NULL) + { + prot_event_tab[event][i].handler = handler; + prot_event_tab[event][i].prot = prot; + return RT_EOK; + } + } + + return -RT_ERROR; +} + +rt_err_t rt_wlan_prot_event_unregister(struct rt_wlan_prot *prot, rt_wlan_prot_event_t event) +{ + int i; + + if (prot == RT_NULL) + { + return -RT_EINVAL; + } + + for (i = 0; i < RT_WLAN_PROT_MAX; i++) + { + if ((prot_event_tab[event][i].handler != RT_NULL) && + (prot_event_tab[event][i].prot == prot)) + { + rt_memset(&prot_event_tab[event][i], 0, sizeof(struct rt_wlan_prot_event_des)); + return RT_EOK; + } + } + + return -RT_ERROR; +} + +rt_err_t rt_wlan_prot_transfer_dev(struct rt_wlan_device *wlan, void *buff, int len) +{ + if (wlan->ops->wlan_send != RT_NULL) + { + return wlan->ops->wlan_send(wlan, buff, len); + } + return -RT_ERROR; +} + +rt_err_t rt_wlan_dev_transfer_prot(struct rt_wlan_device *wlan, void *buff, int len) +{ + struct rt_wlan_prot *prot = wlan->prot; + + if (prot != RT_NULL) + { + return prot->ops->prot_recv(wlan, buff, len); + } + return -RT_ERROR; +} + +extern int rt_wlan_prot_ready_event(struct rt_wlan_device *wlan, struct rt_wlan_buff *buff); +int rt_wlan_prot_ready(struct rt_wlan_device *wlan, struct rt_wlan_buff *buff) +{ + return rt_wlan_prot_ready_event(wlan, buff); +} + +void rt_wlan_prot_dump(void) +{ + int i; + + rt_kprintf(" name id \n"); + rt_kprintf("-------- --------\n"); + for (i = 0; i < RT_WLAN_PROT_MAX; i++) + { + if (_prot[i] != RT_NULL) + { + rt_kprintf("%-8.8s ", _prot[i]->name); + rt_kprintf("%08x\n", _prot[i]->id); + } + } +} diff --git a/components/drivers/wlan/wlan_prot.h b/components/drivers/wlan/wlan_prot.h new file mode 100644 index 0000000000..34c5bae7fd --- /dev/null +++ b/components/drivers/wlan/wlan_prot.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-14 tyx the first version + */ + +#ifndef __WLAN_PROT_H__ +#define __WLAN_PROT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef RT_WLAN_PROT_NAME_LEN +#define RT_WLAN_PROT_NAME_LEN (8) +#endif + +#ifndef RT_WLAN_PROT_MAX +#define RT_WLAN_PROT_MAX (1) +#endif + +#define RT_LWAN_ID_PREFIX (0x5054) + +#define RT_WLAN_PROT_LWIP ("lwip") + +typedef enum +{ + RT_WLAN_PROT_EVT_INIT_DONE = 0, + RT_WLAN_PROT_EVT_CONNECT, + RT_WLAN_PROT_EVT_DISCONNECT, + RT_WLAN_PROT_EVT_AP_START, + RT_WLAN_PROT_EVT_AP_STOP, + RT_WLAN_PROT_EVT_AP_ASSOCIATED, + RT_WLAN_PROT_EVT_AP_DISASSOCIATED, + RT_WLAN_PROT_EVT_MAX, +} rt_wlan_prot_event_t; + +struct rt_wlan_prot; +struct rt_wlan_prot_ops +{ + rt_err_t (*prot_recv)(struct rt_wlan_device *wlan, void *buff, int len); + struct rt_wlan_prot *(*dev_reg_callback)(struct rt_wlan_prot *prot, struct rt_wlan_device *wlan); + void (*dev_unreg_callback)(struct rt_wlan_prot *prot, struct rt_wlan_device *wlan); +}; + +struct rt_wlan_prot +{ + char name[RT_WLAN_PROT_NAME_LEN]; + rt_uint32_t id; + const struct rt_wlan_prot_ops *ops; +}; + +typedef void (*rt_wlan_prot_event_handler)(struct rt_wlan_prot *port, struct rt_wlan_device *wlan, int event); + +rt_err_t rt_wlan_prot_attach(const char *dev_name, const char *prot_name); + +rt_err_t rt_wlan_prot_attach_dev(struct rt_wlan_device *wlan, const char *prot_name); + +rt_err_t rt_wlan_prot_detach(const char *dev_name); + +rt_err_t rt_wlan_prot_detach_dev(struct rt_wlan_device *wlan); + +rt_err_t rt_wlan_prot_regisetr(struct rt_wlan_prot *prot); + +rt_err_t rt_wlan_prot_transfer_dev(struct rt_wlan_device *wlan, void *buff, int len); + +rt_err_t rt_wlan_dev_transfer_prot(struct rt_wlan_device *wlan, void *buff, int len); + +rt_err_t rt_wlan_prot_event_register(struct rt_wlan_prot *prot, rt_wlan_prot_event_t event, rt_wlan_prot_event_handler handler); + +rt_err_t rt_wlan_prot_event_unregister(struct rt_wlan_prot *prot, rt_wlan_prot_event_t event); + +int rt_wlan_prot_ready(struct rt_wlan_device *wlan, struct rt_wlan_buff *buff); + +void rt_wlan_prot_dump(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/drivers/wlan/wlan_workqueue.c b/components/drivers/wlan/wlan_workqueue.c new file mode 100644 index 0000000000..f65ac95d08 --- /dev/null +++ b/components/drivers/wlan/wlan_workqueue.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-19 tyx the first version + */ + +#include +#include +#include +#include + +#define DBG_ENABLE +#define DBG_LEVEL DBG_INFO +#define DBG_SECTION_NAME "WLAN.work" +#define DBG_COLOR +#include + +struct rt_wlan_work +{ + struct rt_work work; + void (*fun)(void *parameter); + void *parameter; +}; + +static struct rt_workqueue *wlan_workqueue; + +static void rt_wlan_workqueue_fun(struct rt_work *work, void *work_data) +{ + struct rt_wlan_work *wlan_work = work_data; + + wlan_work->fun(wlan_work->parameter); + rt_free(wlan_work); +} + +struct rt_workqueue *rt_wlan_get_workqueue(void) +{ + return wlan_workqueue; +} + +rt_err_t rt_wlan_workqueue_dowork(void (*func)(void *parameter), void *parameter) +{ + struct rt_wlan_work *wlan_work; + rt_err_t err = RT_EOK; + + LOG_D("F:%s is run", __FUNCTION__); + if (func == RT_NULL) + { + LOG_E("F:%s L:%d func is null", __FUNCTION__, __LINE__); + return -RT_EINVAL; + } + + if (wlan_workqueue == RT_NULL) + { + LOG_E("F:%s L:%d not init wlan work queue", __FUNCTION__, __LINE__); + return -RT_ERROR; + } + + wlan_work = rt_malloc(sizeof(struct rt_wlan_work)); + if (wlan_work == RT_NULL) + { + LOG_E("F:%s L:%d create work failed", __FUNCTION__, __LINE__); + return -RT_ENOMEM; + } + wlan_work->fun = func; + wlan_work->parameter = parameter; + rt_work_init(&wlan_work->work, rt_wlan_workqueue_fun, wlan_work); + err = rt_workqueue_dowork(wlan_workqueue, &wlan_work->work); + if (err != RT_EOK) + { + LOG_E("F:%s L:%d do work failed", __FUNCTION__, __LINE__); + rt_free(wlan_work); + return err; + } + return err; +} + +int rt_wlan_workqueue_init(void) +{ + static rt_int8_t _init_flag = 0; + + if (_init_flag == 0) + { + wlan_workqueue = rt_workqueue_create(RT_WLAN_WORKQUEUE_THREAD_NAME, RT_WLAN_WORKQUEUE_THREAD_SIZE, + RT_WLAN_WORKQUEUE_THREAD_PRIO); + if (wlan_workqueue == RT_NULL) + { + LOG_E("F:%s L:%d wlan work queue create failed", __FUNCTION__, __LINE__); + return -1; + } + _init_flag = 1; + return 0; + } + return 0; +} +INIT_PREV_EXPORT(rt_wlan_workqueue_init); diff --git a/components/drivers/wlan/wlan_workqueue.h b/components/drivers/wlan/wlan_workqueue.h new file mode 100644 index 0000000000..49bc4a5f9f --- /dev/null +++ b/components/drivers/wlan/wlan_workqueue.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-19 tyx the first version + */ + +#ifndef __WLAN_WORKQUEUE_H__ +#define __WLAN_WORKQUEUE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef RT_WLAN_WORKQUEUE_THREAD_NAME +#define RT_WLAN_WORKQUEUE_THREAD_NAME ("wlan_job") +#endif + +#ifndef RT_WLAN_WORKQUEUE_THREAD_SIZE +#define RT_WLAN_WORKQUEUE_THREAD_SIZE (2048) +#endif + +#ifndef RT_WLAN_WORKQUEUE_THREAD_PRIO +#define RT_WLAN_WORKQUEUE_THREAD_PRIO (20) +#endif + +int rt_wlan_workqueue_init(void); + +rt_err_t rt_wlan_workqueue_dowork(void (*func)(void *parameter), void *parameter); + +struct rt_workqueue *rt_wlan_get_workqueue(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index 1d9156ce4b..0c06303b14 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -1,26 +1,7 @@ /* - * RT-Thread finsh shell commands + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -44,9 +25,14 @@ * 2012-06-02 lgnq add list_memheap * 2012-10-22 Bernard add MS VC++ patch. * 2016-06-02 armink beautify the list_thread command + * 2018-11-22 Jesven list_thread add smp support */ +#include #include + +#ifdef RT_USING_FINSH + #include "finsh.h" long hello(void) @@ -103,30 +89,54 @@ static long _list_thread(struct rt_list_node *list) maxlen = object_name_maxlen(item_title, list); +#ifdef RT_USING_SMP + rt_kprintf("%-*.s cpu pri status sp stack size max used left tick error\n", maxlen, item_title); object_split(maxlen); + rt_kprintf( " --- --- ------- ---------- ---------- ------ ---------- ---\n"); +#else rt_kprintf("%-*.s pri status sp stack size max used left tick error\n", maxlen, item_title); object_split(maxlen); rt_kprintf( " --- ------- ---------- ---------- ------ ---------- ---\n"); +#endif /*RT_USING_SMP*/ for (node = list->next; node != list; node = node->next) { rt_uint8_t stat; thread = rt_list_entry(node, struct rt_thread, list); - rt_kprintf("%-*.*s %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); +#ifdef RT_USING_SMP + if (thread->oncpu != RT_CPU_DETACHED) + rt_kprintf("%-*.*s %3d %3d ", maxlen, RT_NAME_MAX, thread->name, thread->oncpu, thread->current_priority); + else + rt_kprintf("%-*.*s N/A %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); +#else + rt_kprintf("%-*.*s %3d ", maxlen, RT_NAME_MAX, thread->name, thread->current_priority); +#endif /*RT_USING_SMP*/ stat = (thread->stat & RT_THREAD_STAT_MASK); if (stat == RT_THREAD_READY) rt_kprintf(" ready "); else if (stat == RT_THREAD_SUSPEND) rt_kprintf(" suspend"); else if (stat == RT_THREAD_INIT) rt_kprintf(" init "); else if (stat == RT_THREAD_CLOSE) rt_kprintf(" close "); +#if defined(ARCH_CPU_STACK_GROWS_UPWARD) + ptr = (rt_uint8_t *)thread->stack_addr + thread->stack_size; + while (*ptr == '#')ptr --; + + rt_kprintf(" 0x%08x 0x%08x %02d%% 0x%08x %03d\n", + ((rt_ubase_t)thread->sp - (rt_ubase_t)thread->stack_addr), + thread->stack_size, + ((rt_ubase_t)ptr - (rt_ubase_t)thread->stack_addr) * 100 / thread->stack_size, + thread->remaining_tick, + thread->error); +#else ptr = (rt_uint8_t *)thread->stack_addr; while (*ptr == '#')ptr ++; rt_kprintf(" 0x%08x 0x%08x %02d%% 0x%08x %03d\n", - thread->stack_size + ((rt_uint32_t)thread->stack_addr - (rt_uint32_t)thread->sp), + thread->stack_size + ((rt_ubase_t)thread->stack_addr - (rt_ubase_t)thread->sp), thread->stack_size, - (thread->stack_size - ((rt_uint32_t) ptr - (rt_uint32_t) thread->stack_addr)) * 100 + (thread->stack_size - ((rt_ubase_t) ptr - (rt_ubase_t) thread->stack_addr)) * 100 / thread->stack_size, thread->remaining_tick, thread->error); +#endif } return 0; @@ -134,10 +144,15 @@ static long _list_thread(struct rt_list_node *list) long list_thread(void) { + rt_ubase_t level; struct rt_object_information *info; + long ret; + level = rt_hw_interrupt_disable(); info = rt_object_get_information(RT_Object_Class_Thread); - return _list_thread(&info->object_list); + ret = _list_thread(&info->object_list); + rt_hw_interrupt_enable(level); + return ret; } FINSH_FUNCTION_EXPORT(list_thread, list thread); MSH_CMD_EXPORT(list_thread, list thread); @@ -584,38 +599,6 @@ FINSH_FUNCTION_EXPORT(list_device, list device in system); MSH_CMD_EXPORT(list_device, list device in system); #endif -#ifdef RT_USING_MODULE -#include - -int list_module(void) -{ - int maxlen; - struct rt_module *module; - struct rt_list_node *list, *node; - struct rt_object_information *info; - const char *item_title = "module"; - - info = rt_object_get_information(RT_Object_Class_Module); - list = &info->object_list; - - maxlen = object_name_maxlen(item_title, list); - - rt_kprintf("%-*.s ref address \n", maxlen, item_title); object_split(maxlen); - rt_kprintf( " -------- ------------\n"); - for (node = list->next; node != list; node = node->next) - { - module = (struct rt_module *)(rt_list_entry(node, struct rt_object, list)); - rt_kprintf("%-*.*s %-04d 0x%08x\n", - maxlen, RT_NAME_MAX, - module->parent.name, module->nref, module->module_space); - } - - return 0; -} -FINSH_FUNCTION_EXPORT(list_module, list module in system); -MSH_CMD_EXPORT(list_module, list module in system); -#endif - long list(void) { #ifndef FINSH_USING_MSH_ONLY @@ -882,3 +865,6 @@ void list_prefix(char *prefix) static int dummy = 0; FINSH_VAR_EXPORT(dummy, finsh_type_int, dummy variable for finsh) #endif + +#endif /* RT_USING_FINSH */ + diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h index 4452d4a0d6..eb38682c4f 100644 --- a/components/finsh/finsh.h +++ b/components/finsh/finsh.h @@ -1,20 +1,7 @@ /* - * File : finsh.h - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_api.h b/components/finsh/finsh_api.h index 6bbe410b0b..c601415d82 100644 --- a/components/finsh/finsh_api.h +++ b/components/finsh/finsh_api.h @@ -1,20 +1,7 @@ /* - * File : finsh_api.h - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -102,20 +89,20 @@ struct finsh_syscall* finsh_syscall_lookup(const char* name); }; #else - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - const char __fsym_##cmd##_name[] SECTION(".rodata.name") = #cmd; \ - const char __fsym_##cmd##_desc[] SECTION(".rodata.name") = #desc; \ - const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + const char __fsym_##cmd##_name[] SECTION(".rodata.name") = #cmd; \ + const char __fsym_##cmd##_desc[] SECTION(".rodata.name") = #desc; \ + RT_USED const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ { \ __fsym_##cmd##_name, \ __fsym_##cmd##_desc, \ (syscall_func)&name \ }; - #define FINSH_VAR_EXPORT(name, type, desc) \ - const char __vsym_##name##_name[] SECTION(".rodata.name") = #name; \ - const char __vsym_##name##_desc[] SECTION(".rodata.name") = #desc; \ - const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \ + #define FINSH_VAR_EXPORT(name, type, desc) \ + const char __vsym_##name##_name[] SECTION(".rodata.name") = #name; \ + const char __vsym_##name##_desc[] SECTION(".rodata.name") = #desc; \ + RT_USED const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \ { \ __vsym_##name##_name, \ __vsym_##name##_desc, \ @@ -139,10 +126,10 @@ struct finsh_syscall* finsh_syscall_lookup(const char* name); #define FINSH_VAR_EXPORT(name, type, desc) \ const char __vsym_##name##_name[] = #name; \ __declspec(allocate("VSymTab")) const struct finsh_sysvar __vsym_##name = \ - { \ - __vsym_##name##_name, \ - type, \ - (void*)&name \ + { \ + __vsym_##name##_name, \ + type, \ + (void*)&name \ }; #elif defined(__TI_COMPILER_VERSION__) @@ -159,28 +146,28 @@ struct finsh_syscall* finsh_syscall_lookup(const char* name); __TI_FINSH_EXPORT_VAR(__vsym_##name); \ const char __vsym_##name##_name[] = #name; \ const struct finsh_sysvar __vsym_##name = \ - { \ - __vsym_##name##_name, \ - type, \ - (void*)&name \ + { \ + __vsym_##name##_name, \ + type, \ + (void*)&name \ }; #else - #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ - const char __fsym_##cmd##_name[] = #cmd; \ - const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ - { \ - __fsym_##cmd##_name, \ - (syscall_func)&name \ + #define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) \ + const char __fsym_##cmd##_name[] = #cmd; \ + RT_USED const struct finsh_syscall __fsym_##cmd SECTION("FSymTab")= \ + { \ + __fsym_##cmd##_name, \ + (syscall_func)&name \ }; - #define FINSH_VAR_EXPORT(name, type, desc) \ - const char __vsym_##name##_name[] = #name; \ - const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \ - { \ - __vsym_##name##_name, \ - type, \ - (void*)&name \ + #define FINSH_VAR_EXPORT(name, type, desc) \ + const char __vsym_##name##_name[] = #name; \ + RT_USED const struct finsh_sysvar __vsym_##name SECTION("VSymTab")= \ + { \ + __vsym_##name##_name, \ + type, \ + (void*)&name \ }; #endif diff --git a/components/finsh/finsh_compiler.c b/components/finsh/finsh_compiler.c index cf6bb0fe43..1b1f67cb76 100644 --- a/components/finsh/finsh_compiler.c +++ b/components/finsh/finsh_compiler.c @@ -1,26 +1,7 @@ /* - * RT-Thread finsh shell compiler + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_error.c b/components/finsh/finsh_error.c index 962aee1ad3..bdd0108f98 100644 --- a/components/finsh/finsh_error.c +++ b/components/finsh/finsh_error.c @@ -1,26 +1,7 @@ /* - * error number for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_error.h b/components/finsh/finsh_error.h index bec5d85c27..614e02a350 100644 --- a/components/finsh/finsh_error.h +++ b/components/finsh/finsh_error.h @@ -1,26 +1,7 @@ /* - * error number for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_heap.c b/components/finsh/finsh_heap.c index f2f4beb08d..0d185db474 100644 --- a/components/finsh/finsh_heap.c +++ b/components/finsh/finsh_heap.c @@ -1,26 +1,7 @@ /* - * heap management in finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_heap.h b/components/finsh/finsh_heap.h index 7ea61d47eb..9c04e5c22f 100644 --- a/components/finsh/finsh_heap.h +++ b/components/finsh/finsh_heap.h @@ -1,26 +1,7 @@ /* - * heap management in finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_init.c b/components/finsh/finsh_init.c index a2852092f9..72f5aa5e9a 100644 --- a/components/finsh/finsh_init.c +++ b/components/finsh/finsh_init.c @@ -1,26 +1,7 @@ /* - * Initialization procedure for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_node.c b/components/finsh/finsh_node.c index ae28a6ac81..0de82c189d 100644 --- a/components/finsh/finsh_node.c +++ b/components/finsh/finsh_node.c @@ -1,26 +1,7 @@ /* - * node routines for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_node.h b/components/finsh/finsh_node.h index 5e0e4a300c..c7ce099636 100644 --- a/components/finsh/finsh_node.h +++ b/components/finsh/finsh_node.h @@ -1,26 +1,7 @@ /* - * node routines for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_ops.c b/components/finsh/finsh_ops.c index cefdf3c252..2eafb50c69 100644 --- a/components/finsh/finsh_ops.c +++ b/components/finsh/finsh_ops.c @@ -1,26 +1,7 @@ /* - * operations for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_ops.h b/components/finsh/finsh_ops.h index 4e4c5c976e..95a8b001fb 100644 --- a/components/finsh/finsh_ops.h +++ b/components/finsh/finsh_ops.h @@ -1,26 +1,7 @@ /* - * operations for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_parser.c b/components/finsh/finsh_parser.c index aa85509162..0e7617003c 100644 --- a/components/finsh/finsh_parser.c +++ b/components/finsh/finsh_parser.c @@ -1,26 +1,7 @@ /* - * script parser for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_parser.h b/components/finsh/finsh_parser.h index 00d440ae5f..8e149a7e00 100644 --- a/components/finsh/finsh_parser.h +++ b/components/finsh/finsh_parser.h @@ -1,26 +1,7 @@ /* - * script parser for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_token.c b/components/finsh/finsh_token.c index a9fd0ac7d0..5fb593d816 100644 --- a/components/finsh/finsh_token.c +++ b/components/finsh/finsh_token.c @@ -1,26 +1,7 @@ /* - * token lex for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_token.h b/components/finsh/finsh_token.h index fd7e2597cd..0ce98c0f14 100644 --- a/components/finsh/finsh_token.h +++ b/components/finsh/finsh_token.h @@ -1,26 +1,7 @@ /* - * token lex for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_var.c b/components/finsh/finsh_var.c index 7e39492644..6a27bf1fab 100644 --- a/components/finsh/finsh_var.c +++ b/components/finsh/finsh_var.c @@ -1,26 +1,7 @@ /* - * Variable implementation in finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_var.h b/components/finsh/finsh_var.h index f8013ac9d3..8d7ee6a201 100644 --- a/components/finsh/finsh_var.h +++ b/components/finsh/finsh_var.h @@ -1,26 +1,7 @@ /* - * Variable implementation in finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_vm.c b/components/finsh/finsh_vm.c index 8a3b8949e5..fcd58494a9 100644 --- a/components/finsh/finsh_vm.c +++ b/components/finsh/finsh_vm.c @@ -1,26 +1,7 @@ /* - * Virtual machine of finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/finsh_vm.h b/components/finsh/finsh_vm.h index 478a757146..fc515418e4 100644 --- a/components/finsh/finsh_vm.h +++ b/components/finsh/finsh_vm.h @@ -1,26 +1,7 @@ /* - * Virtual machine finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/msh.c b/components/finsh/msh.c index b036e2c02e..fd1ee1198d 100644 --- a/components/finsh/msh.c +++ b/components/finsh/msh.c @@ -1,26 +1,7 @@ /* - * RT-Thread module shell implementation. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,6 +9,9 @@ * 2014-01-03 Bernard msh can execute module. * 2017-07-19 Aubr.Cool limit argc to RT_FINSH_ARG_MAX */ +#include + +#ifdef FINSH_USING_MSH #include "msh.h" #include @@ -37,8 +21,12 @@ #include #endif +#ifdef RT_USING_MODULE +#include +#endif + #ifndef FINSH_ARG_MAX -#define FINSH_ARG_MAX 10 +#define FINSH_ARG_MAX 8 #endif typedef int (*cmd_function_t)(int argc, char **argv); @@ -64,7 +52,6 @@ static int msh_exit(int argc, char **argv) { /* return to finsh shell mode */ __msh_state = RT_FALSE; - return 0; } FINSH_FUNCTION_EXPORT_ALIAS(msh_exit, __cmd_exit, return to RT-Thread shell mode.); @@ -254,7 +241,7 @@ int msh_exec_module(const char *cmd_line, int size) { /* found program */ close(fd); - rt_module_exec_cmd(pg_name, cmd_line, size); + dlmodule_exec(pg_name, cmd_line, size); ret = 0; } else @@ -373,25 +360,27 @@ int msh_exec(char *cmd, rt_size_t length) { return cmd_ret; } -#if defined(RT_USING_MODULE) && defined(RT_USING_DFS) - if (msh_exec_module(cmd, length) == 0) - { - return 0; - } -#endif - -#if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR) +#ifdef RT_USING_DFS +#ifdef DFS_USING_WORKDIR if (msh_exec_script(cmd, length) == 0) { return 0; } #endif -#if defined(RT_USING_LWP) && defined(RT_USING_DFS) +#ifdef RT_USING_MODULE + if (msh_exec_module(cmd, length) == 0) + { + return 0; + } +#endif + +#ifdef RT_USING_LWP if (_msh_exec_lwp(cmd, length) == 0) { return 0; } +#endif #endif /* truncate the cmd at the first space. */ @@ -446,8 +435,8 @@ void msh_auto_complete_path(char *path) ptr = path; for (;;) { - if (*ptr == '/') index = ptr + 1; - if (!*ptr) break; + if (*ptr == '/') index = ptr + 1; + if (!*ptr) break; ptr ++; } @@ -624,3 +613,4 @@ void msh_auto_complete(char *prefix) } #endif +#endif /* FINSH_USING_MSH */ diff --git a/components/finsh/msh.h b/components/finsh/msh.h index df49732956..b7153107ea 100644 --- a/components/finsh/msh.h +++ b/components/finsh/msh.h @@ -1,26 +1,7 @@ /* - * RT-Thread module shell implementation. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/msh_cmd.c b/components/finsh/msh_cmd.c index 47ca031065..3c90542456 100644 --- a/components/finsh/msh_cmd.c +++ b/components/finsh/msh_cmd.c @@ -1,26 +1,7 @@ /* - * internal commands for RT-Thread module shell + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2013-2015, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,11 +10,12 @@ */ #include -#include - -#include "msh.h" #ifdef FINSH_USING_MSH + +#include +#include "msh.h" + #ifdef RT_USING_DFS #include @@ -437,5 +419,4 @@ int cmd_free(int argc, char **argv) FINSH_FUNCTION_EXPORT_ALIAS(cmd_free, __cmd_free, Show the memory usage in the system.); #endif -#endif - +#endif /* FINSH_USING_MSH */ diff --git a/components/finsh/msh_file.c b/components/finsh/msh_file.c index 80012e9bb8..d8eec0a71a 100644 --- a/components/finsh/msh_file.c +++ b/components/finsh/msh_file.c @@ -1,26 +1,7 @@ /* - * script for RT-Thread module shell + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2013-2015, Shanghai Real-Thread Technology Co., Ltd - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,11 +9,11 @@ */ #include -#include - -#include "msh.h" #if defined(FINSH_USING_MSH) && defined(RT_USING_DFS) + +#include +#include "msh.h" #include static int msh_readline(int fd, char *line_buf, int size) @@ -156,4 +137,5 @@ int msh_exec_script(const char *cmd_line, int size) return ret; } -#endif +#endif /* defined(FINSH_USING_MSH) && defined(RT_USING_DFS) */ + diff --git a/components/finsh/shell.c b/components/finsh/shell.c index ccd5b97306..f96e1f8928 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -1,26 +1,7 @@ /* - * shell implementation for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -39,6 +20,8 @@ #include +#ifdef RT_USING_FINSH + #include "finsh.h" #include "shell.h" @@ -55,7 +38,9 @@ static struct rt_thread finsh_thread; ALIGN(RT_ALIGN_SIZE) static char finsh_thread_stack[FINSH_THREAD_STACK_SIZE]; +struct finsh_shell _shell; #endif + struct finsh_shell *shell; static char *finsh_prompt_custom = RT_NULL; @@ -473,9 +458,6 @@ static void shell_push_history(struct finsh_shell *shell) } #endif -#ifndef RT_USING_HEAP -struct finsh_shell _shell; -#endif void finsh_thread_entry(void *parameter) { char ch; @@ -792,7 +774,7 @@ int finsh_system_init(void) rt_thread_t tid; #ifdef FINSH_USING_SYMTAB -#ifdef __CC_ARM /* ARM C Compiler */ +#if defined(__CC_ARM) || defined(__CLANG_ARM) /* ARM C Compiler */ extern const int FSymTab$$Base; extern const int FSymTab$$Limit; extern const int VSymTab$$Base; @@ -868,3 +850,5 @@ int finsh_system_init(void) } INIT_APP_EXPORT(finsh_system_init); +#endif /* RT_USING_FINSH */ + diff --git a/components/finsh/shell.h b/components/finsh/shell.h index d0fd66ee78..2cf2c9b833 100644 --- a/components/finsh/shell.h +++ b/components/finsh/shell.h @@ -1,26 +1,7 @@ /* - * shell implementation for finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/finsh/symbol.c b/components/finsh/symbol.c index 8e026c4a1b..e500637bdd 100644 --- a/components/finsh/symbol.c +++ b/components/finsh/symbol.c @@ -1,31 +1,17 @@ /* - * symbols in finsh shell. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team - * - * This file is part of RT-Thread (http://www.rt-thread.org) - * Maintainer: bernard.xiong - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2010-03-22 Bernard first version */ + +#include + +#ifdef RT_USING_FINSH + #include "finsh.h" long hello(void); @@ -82,3 +68,6 @@ struct finsh_syscall *_syscall_table_end = &_syscall_table[sizeof(_syscall_tab struct finsh_sysvar *_sysvar_table_begin = NULL; struct finsh_sysvar *_sysvar_table_end = NULL; #endif + +#endif /* RT_USING_FINSH */ + diff --git a/components/gdb/SConscript b/components/gdb/SConscript deleted file mode 100644 index 8893d238bc..0000000000 --- a/components/gdb/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -Import('rtconfig') -from building import * - -src = Glob('*.c') -comm = 'libcpu/' + rtconfig.ARCH -if (rtconfig.CPU == 'cortex-m4') or (rtconfig.CPU == 'cortex-m3'): - comm = 'libcpu/cortexm' - -cwd = GetCurrentDir() -if rtconfig.PLATFORM == 'armcc': - src = src + Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S') - -if rtconfig.PLATFORM == 'gcc': - src = src + Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S') - -if rtconfig.PLATFORM == 'iar': - src = src + Glob(comm + '/*.c') + Glob(comm + '/*_iar.S') - -CPPPATH = [cwd, cwd + '/' + comm] - -group = DefineGroup('gdb', src, depend = ['RT_USING_GDB'], CPPPATH = CPPPATH) - -Return('group') diff --git a/components/gdb/gdb_stub.c b/components/gdb/gdb_stub.c deleted file mode 100644 index a07c165cbb..0000000000 --- a/components/gdb/gdb_stub.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* - * GDB stub. - * - * Migarte form linux to rt-thread by Wzyy2 - * Original edition : KGDB stub - * - * File : gdb_stub.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-04 Wzyy2 first version - * - * This file incorporates work covered by the following copyright and - * permission notice: - * - * KGDB stub. - * - * Maintainer: Jason Wessel - * - * Copyright (C) 2000-2001 VERITAS Software Corporation. - * Copyright (C) 2002-2004 Timesys Corporation - * Copyright (C) 2003-2004 Amit S. Kale - * Copyright (C) 2004 Pavel Machek - * Copyright (C) 2004-2006 Tom Rini - * Copyright (C) 2004-2006 LinSysSoft Technologies Pvt. Ltd. - * Copyright (C) 2005-2008 Wind River Systems, Inc. - * Copyright (C) 2007 MontaVista Software, Inc. - * Copyright (C) 2008 Red Hat, Inc., Ingo Molnar - * - * Contributors at various stages not listed above: - * Jason Wessel ( jason.wessel@windriver.com ) - * George Anzinger - * Anurekh Saxena (anurekh.saxena@timesys.com) - * Lake Stevens Instrument Division (Glenn Engel) - * Jim Kingdon, Cygnus Support. - * - * Original KGDB stub: David Grothe , - * Tigran Aivazian - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -#include -#include -#include -#include "gdb_stub.h" - - -struct gdb_state { - int signo; - int pass_exception; -}gs; - -/** - * gdb_connected - Is a host GDB connected to us? - */ -int gdb_connected; - - - -/* - * Holds information about breakpoints in a kernel. These breakpoints are - * added and removed by gdb. - */ -#if RT_GDB_HAVE_SWBP -static struct gdb_bkpt gdb_break[GDB_MAX_BREAKPOINTS] = { - [0 ... GDB_MAX_BREAKPOINTS-1] = { .state = BP_UNDEFINED } -}; -#endif - - -/* Storage for the registers, in GDB format. */ -static unsigned long gdb_regs[(NUMREGBYTES + - sizeof(unsigned long) - 1) / -sizeof(unsigned long)]; - -char remcom_in_buffer[BUFMAX]; -char remcom_out_buffer[BUFMAX]; - - -static const char hexchars[] = "0123456789abcdef"; - - -//to call that there has been an error -void* volatile gdb_mem_fault_handler = (void *)0; -static long probe_kernel_write(void *dst, void *src, size_t size) -{ - int i = 0; - char *dst_ptr = (char *)dst; - char *src_ptr = (char *)src; - - gdb_mem_fault_handler = &&err; - - for (i = 0; i= 'a') && (ch <= 'f')) - return ch - 'a' + 10; - if ((ch >= '0') && (ch <= '9')) - return ch - '0'; - if ((ch >= 'A') && (ch <= 'F')) - return ch - 'A' + 10; - return -1; -} - -static char tohex(char c) -{ - return hexchars[c & 15]; -} - -/* - * Copy the binary array pointed to by buf into mem. Fix $, #, and - * 0x7d escaped with 0x7d. Return a pointer to the character after - * the last byte written. - */ -int gdb_ebin2mem(char *buf, char *mem, int count) -{ - int err = 0; - char c; - - while (count-- > 0) { - c = *buf++; - if (c == 0x7d) - c = *buf++ ^ 0x20; - - err = probe_kernel_write(mem, &c, 1); - if (err) - break; - - mem++; - } - - return err; -} - -/* - * Convert the hex array pointed to by buf into binary to be placed in mem. - * Return a pointer to the character AFTER the last byte written. - * May return an error. - */ -int gdb_hex2mem(char *buf, char *mem, int count) -{ - char *tmp_raw; - char *tmp_hex; - - tmp_raw = buf + count * 2; - - tmp_hex = tmp_raw - 1; - while (tmp_hex >= buf) { - tmp_raw--; - *tmp_raw = hex(*tmp_hex--); - *tmp_raw |= hex(*tmp_hex--) << 4; - } - - return probe_kernel_write(mem, tmp_raw, count); -} -/* - * Convert the memory pointed to by mem into hex, placing result in buf. - * Return a pointer to the last char put in buf (null). May return an error. - */ -int gdb_mem2hex(char *mem, char *buf, int count) -{ - char *tmp = mem; - char ch; - - gdb_mem_fault_handler = &&err; - - while (count > 0) { - ch = *(tmp++); - *(buf++) = tohex((ch >> 4) & 0xf); - *(buf++) = tohex(ch & 0xf); - - count--; - } - *buf = 0; - - gdb_mem_fault_handler = (void *)0; - return 0; -err: - gdb_mem_fault_handler = (void *)0; - return -1; -} - -/* - * While we find nice hex chars, build a long_val. - * Return number of chars processed. - */ -int gdb_hex2long(char **ptr, unsigned long *long_val) -{ - int hex_val; - int num = 0; - int negate = 0; - - *long_val = 0; - - if (**ptr == '-') { - negate = 1; - (*ptr)++; - } - while (**ptr) { - hex_val = hex(**ptr); - if (hex_val < 0) - break; - - *long_val = (*long_val << 4) | hex_val; - num++; - (*ptr)++; - } - - if (negate) - *long_val = -*long_val; - - return num; -} - -/* Write memory due to an 'M' or 'X' packet. */ -static int write_mem_msg(int binary) -{ - char *ptr = &remcom_in_buffer[1]; - unsigned long addr; - unsigned long length; - int err; - - if (gdb_hex2long(&ptr, &addr) > 0 && *(ptr++) == ',' && - gdb_hex2long(&ptr, &length) > 0 && *(ptr++) == ':') { -#ifdef GDB_DATA_ACCESS - //accesses to areas not backed can cause error - if (gdb_permit_data_access(addr, length)) - return -1; -#endif - if (binary) - err = gdb_ebin2mem(ptr, (char *)addr, length); - else - err = gdb_hex2mem(ptr, (char *)addr, length); - if (err) - return err; -#ifdef RT_GDB_ICACHE - if (CACHE_FLUSH_IS_SAFE) - gdb_flush_icache_range(addr, addr + length); -#endif - return 0; - } - - return -1; -} - -/* - * Send the packet in buffer. - * Check for gdb connection if asked for. - */ -static void put_packet(char *buffer) -{ - unsigned char checksum; - int count; - char ch; - - /* - * $#. - */ - while (1) { - gdb_io_ops.write_char('$'); - checksum = 0; - count = 0; - - while ((ch = buffer[count])) { - gdb_io_ops.write_char(ch); - checksum += ch; - count++; - } - - gdb_io_ops.write_char('#'); - gdb_io_ops.write_char(tohex((checksum >> 4) & 0xf)); - gdb_io_ops.write_char(tohex(checksum & 0xf)); - - - /* Now see what we get in reply. */ - ch = gdb_io_ops.read_char(); - - /* If we get an ACK, we are done. */ - if (ch == '+') - return; - - /* - * If we get the start of another packet, this means - * that GDB is attempting to reconnect. We will NAK - * the packet being sent, and stop trying to send this - * packet. - */ - if (ch == '$') { - gdb_io_ops.write_char('-'); - if (gdb_io_ops.flush) - gdb_io_ops.flush(); - return; - } - } -} - -/* scan for the sequence $# */ -static void get_packet(char *buffer) -{ - unsigned char checksum; - unsigned char xmitcsum; - int count; - char ch; - - do { - /* - * Spin and wait around for the start character, ignore all - * other characters: - */ - while ((ch = (gdb_io_ops.read_char())) != '$') - /* nothing */; - gdb_connected = 1; - checksum = 0; - xmitcsum = -1; - - count = 0; - - /* - * now, read until a # or end of buffer is found: - */ - while (count < (BUFMAX - 1)) { - ch = gdb_io_ops.read_char(); - if (ch == '#') - break; - checksum = checksum + ch; - buffer[count] = ch; - count = count + 1; - } - buffer[count] = 0; - - if (ch == '#') { - xmitcsum = hex(gdb_io_ops.read_char()) << 4; - xmitcsum += hex(gdb_io_ops.read_char()); - - if (checksum != xmitcsum) - /* failed checksum */ - gdb_io_ops.write_char('-'); - else - /* successful transfer */ - gdb_io_ops.write_char('+'); - if (gdb_io_ops.flush) - gdb_io_ops.flush(); - } - } while (checksum != xmitcsum); -} - -static void error_packet(char *pkt, int error) -{ - error = -error; - pkt[0] = 'E'; - pkt[1] = tohex((error / 10)); - pkt[2] = tohex((error % 10)); - pkt[3] = '\0'; -} - -#if RT_GDB_HAVE_SWBP -static int gdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) -{ - int err; - - err = probe_kernel_write((void *)saved_instr, (void *)addr, BREAK_INSTR_SIZE); - if (err) - return err; - - return probe_kernel_write((void *)addr, (void *)arch_gdb_ops.gdb_bpt_instr, - BREAK_INSTR_SIZE); -} - -static int gdb_arch_remove_breakpoint(unsigned long addr, char *bundle) -{ - return probe_kernel_write((void *)addr, - (void *)bundle, BREAK_INSTR_SIZE); -} -static int gdb_validate_break_address(unsigned long addr) -{ - char tmp_variable[BREAK_INSTR_SIZE]; - int err; - /* Validate setting the breakpoint and then removing it. In the - * remove fails, the kernel needs to emit a bad message because we - * are deep trouble not being able to put things back the way we - * found them. - */ - err = gdb_arch_set_breakpoint(addr, tmp_variable); - if (err) - return err; - err = gdb_arch_remove_breakpoint(addr, tmp_variable); - if (err) - rt_kprintf("GDB: Critical breakpoint error,memory destroyed at: %08x \n", addr); - return err; -} - -/* - * Some architectures need cache flushes when we set/clear a - * breakpoint: - */ -static void gdb_flush_swbreak_addr(unsigned long addr) -{ - if (!CACHE_FLUSH_IS_SAFE) - return; - - /* Force flush instruction cache if it was outside the mm */ - gdb_flush_icache_range(addr, addr + BREAK_INSTR_SIZE); -} - -/* - * SW breakpoint management: - */ -static int gdb_activate_sw_breakpoints(void) -{ - unsigned long addr; - int error = 0; - int i; - - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if (gdb_break[i].state != BP_SET) - continue; - - addr = gdb_break[i].bpt_addr; - error = gdb_arch_set_breakpoint(addr, - (char *)(gdb_break[i].saved_instr)); - if (error) - return error; - - gdb_flush_swbreak_addr(addr); - gdb_break[i].state = BP_ACTIVE; - } - return 0; -} - -int gdb_set_sw_break(unsigned long addr) -{ - int err = gdb_validate_break_address(addr); - int breakno = -1; - int i; - - if (err) - return err; - - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if ((gdb_break[i].state == BP_SET) && - (gdb_break[i].bpt_addr == addr)) - return -1; - } - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if (gdb_break[i].state == BP_REMOVED) { - breakno = i; - break; - } - } - - if (breakno == -1) { - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if (gdb_break[i].state == BP_UNDEFINED) { - breakno = i; - break; - } - } - } - - if (breakno == -1) - return -1; - - gdb_break[breakno].state = BP_SET; - gdb_break[breakno].type = BP_BREAKPOINT; - gdb_break[breakno].bpt_addr = addr; - - return 0; -} - -static int gdb_deactivate_sw_breakpoints(void) -{ - unsigned long addr; - int error = 0; - int i; - - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if (gdb_break[i].state != BP_ACTIVE) - continue; - addr = gdb_break[i].bpt_addr; - error = gdb_arch_remove_breakpoint(addr, - (char *)(gdb_break[i].saved_instr)); - if (error) - return error; - - gdb_flush_swbreak_addr(addr); - gdb_break[i].state = BP_SET; - } - return 0; -} - -int gdb_remove_sw_break(unsigned long addr) -{ - int i; - - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if ((gdb_break[i].state == BP_SET) && - (gdb_break[i].bpt_addr == addr)) { - gdb_break[i].state = BP_REMOVED; - return 0; - } - } - return -1; -} - -int gdb_isremovedbreak(unsigned long addr) -{ - int i; - - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if ((gdb_break[i].state == BP_REMOVED) && - (gdb_break[i].bpt_addr == addr)) - return 1; - } - return 0; -} -#endif - -static int remove_all_break() -{ -#if RT_GDB_HAVE_SWBP - unsigned long addr; - int error=0; - int i; - - /* Clear memory breakpoints. */ - for (i = 0; i < GDB_MAX_BREAKPOINTS; i++) { - if (gdb_break[i].state != BP_ACTIVE) - goto setundefined; - addr = gdb_break[i].bpt_addr; - error = gdb_arch_remove_breakpoint(addr, - (char *)gdb_break[i].saved_instr); - if (error) - rt_kprintf("GDB: breakpoint remove failed: %lx\n", - addr); -setundefined: - gdb_break[i].state = BP_UNDEFINED; - } -#endif - -#if RT_GDB_HAVE_HWBP - /* Clear hardware breakpoints. */ - arch_gdb_ops.remove_all_hw_break(); -#endif - - return 0; -} - - -static char gdbmsgbuf[BUFMAX + 1]; -static void gdb_msg_write(const char *s, int len) -{ - char *bufptr; - int wcount; - int i; - - /* 'O'utput */ - gdbmsgbuf[0] = 'O'; - - /* Fill and send buffers... */ - while (len > 0) { - bufptr = gdbmsgbuf + 1; - - /* Calculate how many this time */ - if ((len << 1) > (BUFMAX - 2)) - wcount = (BUFMAX - 2) >> 1; - else - wcount = len; - - /* Pack in hex chars */ - for (i = 0; i < wcount; i++) { - *(bufptr++) = tohex((s[i] >> 4) & 0xf); - *(bufptr++) = tohex(s[i] & 0xf); - } - *bufptr = '\0'; - - /* Move up */ - s += wcount; - len -= wcount; - - /* Write packet */ - put_packet(gdbmsgbuf); - } -} - -/* - * Return true if there is a valid gdb I/O module. Also if no - * debugger is attached a message can be printed to the console about - * waiting for the debugger to attach. - * - * The print_wait argument is only to be true when called from inside - * the core gdb_handle_exception, because it will wait for the - * debugger to attach. - */ -static int gdb_io_ready(int print_wait) -{ - if (!gdb_dev) - return 0; - if (gdb_connected) - return 1; - if (print_wait) - rt_kprintf("GDB: Waiting for remote debugger\n"); - return 1; -} - -/* Handle the '?' status packets */ -static void gdb_cmd_status(struct gdb_state *gs) -{ - /* - * We know that this packet is only sent - * during initial connect. So to be safe, - * we clear out our breakpoints now in case - * GDB is reconnecting. - */ - remove_all_break(); - - remcom_out_buffer[0] = 'S'; - remcom_out_buffer[1] = tohex((gs->signo >> 4) &0xf); - remcom_out_buffer[2] = tohex(gs->signo & 0xf); - remcom_out_buffer[3] = 0; -} - -/* Handle the 'm' memory read bytes */ -static void gdb_cmd_memread(struct gdb_state *gs) -{ - char *ptr = &remcom_in_buffer[1]; - unsigned long length; - unsigned long addr; - int err; - - if (gdb_hex2long(&ptr, &addr) > 0 && *ptr++ == ',' && - gdb_hex2long(&ptr, &length) > 0) { -#ifdef GDB_DATA_ACCESS - //accesses to areas not backed can cause error - if (gdb_permit_data_access(addr, length)) - return ; -#endif - err = gdb_mem2hex((char *)addr, remcom_out_buffer, length); - if (err) - error_packet(remcom_out_buffer, err); - } else { - error_packet(remcom_out_buffer, -1); - } -} - -/* Handle the 'M' memory write bytes */ -static void gdb_cmd_memwrite(struct gdb_state *gs) -{ - int err = write_mem_msg(0); - - if (err) - error_packet(remcom_out_buffer, err); - else - strcpy(remcom_out_buffer, "OK"); -} - -/* Handle the 'X' memory binary write bytes */ -static void gdb_cmd_binwrite(struct gdb_state *gs) -{ - int err = write_mem_msg(1); - - if (err) - error_packet(remcom_out_buffer, err); - else - strcpy(remcom_out_buffer, "OK"); -} - -/* Handle the 'q' query packets */ -static void gdb_cmd_query(struct gdb_state *gs) -{ - /* nothing,because we have no thread support */ -} - - -/* Handle the 'g' or 'p' get registers request */ -static void gdb_cmd_getregs(struct gdb_state *gs) -{ - char len = sizeof(long); - - gdb_get_register((unsigned long *)gdb_regs); - - /*get one registers*/ - if (remcom_in_buffer[0] == 'p'){ - char *p = &remcom_in_buffer[1]; - unsigned long regno = 0; - - if (gdb_hex2long(&p, ®no)){ - gdb_mem2hex(((char *)gdb_regs) + regno * len, remcom_out_buffer, len); - return; - } else { - strcpy(remcom_out_buffer, "INVALID"); - return; - } - } - - gdb_mem2hex((char *)gdb_regs, remcom_out_buffer, NUMREGBYTES); -} - -/* Handle the 'G' or 'P' set registers request */ -static void gdb_cmd_setregs(struct gdb_state *gs) -{ - char len = sizeof(long); - - /*set one registers*/ - if (remcom_in_buffer[0] == 'P'){ - char *p = &remcom_in_buffer[1]; - unsigned long regno = 0; - - if (gdb_hex2long(&p, ®no) && *p++ == '='){ - gdb_get_register((unsigned long *)gdb_regs); - gdb_hex2mem(p, ((char *)gdb_regs) + regno * len, len); - gdb_put_register(gdb_regs); - strcpy(remcom_out_buffer, "OK"); - } - - return; - } - - gdb_hex2mem(&remcom_in_buffer[1], (char *)gdb_regs, NUMREGBYTES); - - gdb_put_register(gdb_regs); - strcpy(remcom_out_buffer, "OK"); -} - -/* Handle the 'D' or 'k', detach or kill packets */ -static void gdb_cmd_detachkill(struct gdb_state *gs) -{ - int error; - - /* The detach case */ - if (remcom_in_buffer[0] == 'D') { - error = remove_all_break(); - if (error < 0) { - error_packet(remcom_out_buffer, error); - } else { - strcpy(remcom_out_buffer, "OK"); - gdb_connected = 0; - } - put_packet(remcom_out_buffer); - } else { - /* - * Assume the kill case, with no exit code checking, - * trying to force detach the debugger: - */ - remove_all_break(); - gdb_connected = 0; - } -} - -/* Handle the 'z' or 'Z' breakpoint remove or set packets */ -static void gdb_cmd_break(struct gdb_state *gs) -{ - /* - * Since GDB-5.3, it's been drafted that '0' is a software - * breakpoint, '1' is a hardware breakpoint, so let's do that. - */ - char *bpt_type = &remcom_in_buffer[1]; - char *ptr = &remcom_in_buffer[2]; - unsigned long addr; - unsigned long length; - int error = 0; - - if (arch_gdb_ops.set_hw_breakpoint && *bpt_type >= '1') { - /* Unsupported */ - if (*bpt_type > '4') - return; - } - /* - * Test if this is a hardware breakpoint, and - * if we support it: - */ - if (*bpt_type == '1' && !(arch_gdb_ops.flags)) { - /* Unsupported. */ - return; - } - if (*(ptr++) != ',') { - error_packet(remcom_out_buffer, -1); - return; - } - if (!gdb_hex2long(&ptr, &addr)) { - error_packet(remcom_out_buffer, -1); - return; - } - if (*(ptr++) != ',' || - !gdb_hex2long(&ptr, &length)) { - error_packet(remcom_out_buffer, -1); - return; - } -#if RT_GDB_HAVE_SWBP - if (remcom_in_buffer[0] == 'Z' && *bpt_type == '0') - error = gdb_set_sw_break(addr); - else if (remcom_in_buffer[0] == 'z' && *bpt_type == '0') - error = gdb_remove_sw_break(addr); -#else - if (remcom_in_buffer[0] == 'Z' && *bpt_type == '0') - error = arch_gdb_ops.set_hw_breakpoint(addr, - (int)length, BP_HARDWARE_BREAKPOINT); - else if (remcom_in_buffer[0] == 'z' && *bpt_type == '0') - error = arch_gdb_ops.remove_hw_breakpoint(addr, - (int) length, BP_HARDWARE_BREAKPOINT); -#endif - else if (remcom_in_buffer[0] == 'Z') - error = arch_gdb_ops.set_hw_breakpoint(addr, - (int)length, *bpt_type - '0'); - else if (remcom_in_buffer[0] == 'z') - error = arch_gdb_ops.remove_hw_breakpoint(addr, - (int) length, *bpt_type - '0'); - - if (error == 0) - strcpy(remcom_out_buffer, "OK"); - else - error_packet(remcom_out_buffer, error); -} - -/* Handle the 'C' signal / exception passing packets */ -static int gdb_cmd_exception_pass(struct gdb_state *gs) -{ - /* C09 == pass exception - * C15 == detach gdb, pass exception - */ - if (remcom_in_buffer[1] == '0' && remcom_in_buffer[2] == '9') { - - gs->pass_exception = 1; - remcom_in_buffer[0] = 'c'; - - } else if (remcom_in_buffer[1] == '1' && remcom_in_buffer[2] == '5') { - - gs->pass_exception = 1; - remcom_in_buffer[0] = 'D'; - remove_all_break(); - gdb_connected = 0; - return 1; - - } else { - error_packet(remcom_out_buffer, -1); - return 0; - } - - /* Indicate fall through */ - return -1; -} - - -/*more about packet in https://www.sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#Packets*/ -static int process_packet(char *pkt) -{ - int status = 0; - int tmp; - - status = gdb_arch_handle_exception(remcom_in_buffer, - remcom_out_buffer); - - remcom_out_buffer[0] = 0; - switch (pkt[0]) { - case '?':/* gdbserial status */ - gdb_cmd_status(&gs); - break; - case 'q':/* query command */ - gdb_cmd_query(&gs); - break; - case 'p': /* return the value of a single CPU register */ - case 'g': /* return the value of the CPU registers */ - gdb_cmd_getregs(&gs); - break; - case 'P': /* set the value of a single CPU registers - return OK */ - case 'G': /* set the value of the CPU registers - return OK */ - gdb_cmd_setregs(&gs); - break; - case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ - gdb_cmd_memread(&gs); - break; - case 'X':/* XAA..AA,LLLL: Write LLLL escaped binary bytes at address AA.AA*/ - gdb_cmd_binwrite(&gs); - break; - case 'M':/* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ - gdb_cmd_memwrite(&gs); - break; - case 'D': /* Debugger detach */ - case 'k': /* Debugger detach via kill */ - gdb_cmd_detachkill(&gs); - break; - case 'C':/* Exception passing */ - tmp = gdb_cmd_exception_pass(&gs); - if (tmp > 0) - process_packet(remcom_in_buffer); - if (tmp == 0) - break; - case 'z':/* Break point remove */ - case 'Z':/* Break point set */ - gdb_cmd_break(&gs); - break; - case 'H':/* task related */ - break; - case 'T':/* Query thread status */ - break; - case 'b': /* bBB... Set baud rate to BB... */ - break; - case 's': /* sAA..AA step form address AA..AA (optional) */ - case 'c': /* cAA..AA Continue at address AA..AA (optional) */ -#if RT_GDB_HAVE_SWBP - gdb_activate_sw_breakpoints(); -#endif - break; - } - - if (!status) - return -1; - -exit: - put_packet(remcom_out_buffer); - return 0; -} - - -/* - * This function does all command procesing for interfacing to gdb. - */ -int gdb_process_exception() -{ - int status; - - do { - get_packet(remcom_in_buffer); - status = process_packet(remcom_in_buffer); - } while (status == 0); - - if (status < 0) - return 0; - else - return 1; -} - - -int gdb_handle_exception(int signo, void *regs) -{ - int error; - - gs.signo = signo; - - if (!gdb_io_ready(1)) { - error = 1; - return error; /* No I/O connection, so resume the system */ - } - -#if RT_GDB_HAVE_SWBP - gdb_deactivate_sw_breakpoints(); -#endif - gdb_set_register(regs); - - /* Clear the out buffer. */ - memset(remcom_out_buffer, 0, sizeof(remcom_out_buffer)); - - if (gdb_connected) { - char *ptr; - - gdb_io_ops.write_char('\n'); - /* Reply to host that an exception has occurred */ - ptr = remcom_out_buffer; - *ptr++ = 'T'; - *ptr++ = tohex((gs.signo >> 4) &0xf); - *ptr++ = tohex(gs.signo & 0xf); - /*ptr += strlen(strcpy(ptr, "thread:"));*/ - /**ptr++ = ';';*/ - put_packet(remcom_out_buffer); - } - gs.pass_exception = 0; - - - while (gdb_process_exception()); - - error = gs.pass_exception; - - return error; -} - -void gdb_console_write(const char *s, unsigned count) -{ - /* If we're debugging, or GDB has not connected, don't try - * and print. */ - if (!gdb_connected) - return; - - gdb_msg_write(s, count); -} - diff --git a/components/gdb/gdb_stub.h b/components/gdb/gdb_stub.h deleted file mode 100644 index cb9688ee3a..0000000000 --- a/components/gdb/gdb_stub.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This provides the functions that GDB needs to share between - * different portions. - * - * GDB stub. - * - * Migarte form linux to rt-thread by Wzyy2 - * Original edition : KGDB stub - * - * File : gdb_stub.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-04 Wzyy2 first version - */ -#ifndef __GDB_STUB_H__ -#define __GDB_STUB_H__ - -#include -#include - - -#ifndef RT_GDB_MAX_BREAKPOINTS - #define GDB_MAX_BREAKPOINTS 20 -#else - #define GDB_MAX_BREAKPOINTS RT_GDB_MAX_BREAKPOINTS -#endif - - -// Signal definitions -#define SIGHUP 1 /* hangup */ -#define SIGINT 2 /* interrupt */ //irq or fiq -#define SIGQUIT 3 /* quit */ -#define SIGILL 4 /* illegal instruction (not reset when caught) */ -#define SIGTRAP 5 /* trace trap (not reset when caught) */ -#define SIGIOT 6 /* IOT instruction */ -#define SIGABRT 6 /* used by abort, replace SIGIOT in the future */ -#define SIGEMT 7 /* EMT instruction */ -#define SIGFPE 8 /* floating point exception */ -#define SIGKILL 9 /* kill (cannot be caught or ignored) */ -#define SIGBUS 10 /* bus error */ //abort or reserved -#define SIGSEGV 11 /* segmentation violation */ -#define SIGSYS 12 /* bad argument to system call */ -#define SIGPIPE 13 /* write on a pipe with no one to read it */ -#define SIGALRM 14 /* alarm clock */ -#define SIGTERM 15 /* software termination signal from kill */ - -enum gdb_bptype { - BP_BREAKPOINT = 0, - BP_HARDWARE_BREAKPOINT, - BP_WRITE_WATCHPOINT, - BP_READ_WATCHPOINT, - BP_ACCESS_WATCHPOINT, - BP_POKE_BREAKPOINT, -}; - -enum gdb_bpstate { - BP_UNDEFINED = 0, - BP_REMOVED, - BP_SET, - BP_ACTIVE -}; - -struct gdb_bkpt { - unsigned long bpt_addr; - unsigned char saved_instr[BREAK_INSTR_SIZE]; - enum gdb_bptype type; - enum gdb_bpstate state; -}; - -/** - * struct gdb_arch - Describe architecture specific values. - * @gdb_bpt_instr: The instruction to trigger a breakpoint. - * @flags: Flags for the breakpoint, currently just %GDB_HW_BREAKPOINT. - * @set_hw_breakpoint: Allow an architecture to specify how to set a hardware - * breakpoint. - * @remove_hw_breakpoint: Allow an architecture to specify how to remove a - * hardware breakpoint. - * @remove_all_hw_break: Allow an architecture to specify how to remove all - * hardware breakpoints. - */ -struct gdb_arch { - unsigned char gdb_bpt_instr[BREAK_INSTR_SIZE]; - unsigned long flags; - - int (*set_hw_breakpoint)(unsigned long, int, enum gdb_bptype); - int (*remove_hw_breakpoint)(unsigned long, int, enum gdb_bptype); - void (*remove_all_hw_break)(void); -}; -/** - * struct gdb_io - Describe the interface for an I/O driver to talk with KGDB. - * @read_char: Pointer to a function that will return one char. - * @write_char: Pointer to a function that will write one char. - * @flush: Pointer to a function that will flush any pending writes. - * @init: Pointer to a function that will initialize the device. - */ -struct gdb_io { - int (*read_char) (void); - void (*write_char) (char); - void (*flush) (void); - int (*init) (void); -}; - -extern int gdb_connected; -extern void* volatile gdb_mem_fault_handler; - -int gdb_hex2long(char **ptr, unsigned long *long_val); -int gdb_mem2hex(char *mem, char *buf, int count); -int gdb_hex2mem(char *buf, char *mem, int count); -int gdb_ebin2mem(char *buf, char *mem, int count); -int gdb_set_sw_break(unsigned long addr); -int gdb_remove_sw_break(unsigned long addr); -int gdb_isremovedbreak(unsigned long addr); -void gdb_console_write(const char *s, unsigned count); -int gdb_handle_exception(int signo, void *regs); - -/* hal */ -extern struct gdb_io gdb_io_ops; -extern rt_device_t gdb_dev; -void gdb_start(); -void gdb_set_device(const char* device_name); - - - -#endif /* __GDB_STUB_H__ */ diff --git a/components/gdb/hal_stub.c b/components/gdb/hal_stub.c deleted file mode 100644 index 8cf4a31a51..0000000000 --- a/components/gdb/hal_stub.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * I/O and interface portion of GDB stub - * - * File : hal_stub.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-04 Wzyy2 first version - */ -#include -#include -#include "gdb_stub.h" - -#ifdef RT_USING_SERIAL -#include -#endif - -rt_device_t gdb_dev = RT_NULL; -static struct rt_serial_device *gdb_serial; -char gdb_io_set; - -void gdb_uart_putc(char c); -int gdb_uart_getc(); - - -/*if you want to use something instead of the serial,change it */ -struct gdb_io gdb_io_ops = { - gdb_uart_getc, - gdb_uart_putc -}; - - -/** - * @ingroup gdb_stub - * - * This function will get GDB stubs started, with a proper environment - */ -void gdb_start() -{ - if (gdb_dev == RT_NULL) - rt_kprintf("GDB: no gdb_dev found,please set it first\n"); - else - gdb_breakpoint(); -} - - -/** - * @ingroup gdb_stub - * - * This function sets the input device of gdb_stub. - * - * @param device_name the name of new input device. - */ -void gdb_set_device(const char* device_name) -{ - rt_device_t dev = RT_NULL; - dev = rt_device_find(device_name); - if(dev == RT_NULL){ - rt_kprintf("GDB: can not find device: %s\n", device_name); - return; - } - - /* open this device and set the new device */ - if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM) == RT_EOK) - { - gdb_dev = dev; - gdb_serial = (struct rt_serial_device *)gdb_dev; - } -} - -void gdb_uart_putc(char c) -{ -#ifdef RT_GDB_DEBUG - rt_kprintf("%c",c); -#endif - rt_device_write(gdb_dev, 0, &c, 1); -} - -/* polling */ -int gdb_uart_getc() -{ - int ch; - -#ifdef RT_USING_SERIAL - ch = -1; - do { - ch = gdb_serial->ops->getc(gdb_serial); - } while (ch == -1); -#else - rt_device_read(gdb_dev, 0, &ch, 1); -#endif - -#ifdef RT_GDB_DEBUG - rt_kprintf("%c",ch); -#endif - - return ch; -} - diff --git a/components/gdb/libcpu/arm/arch_gdb.h b/components/gdb/libcpu/arm/arch_gdb.h deleted file mode 100644 index b9462499f2..0000000000 --- a/components/gdb/libcpu/arm/arch_gdb.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * ARM GDB support - * arch-specific portion of GDB stub - * - * File : arch_gdb.h(arm) - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-04 wzyy2 first version - */ -#ifndef __ARM_GDB_H__ -#define __ARM_GDB_H__ - -#include - - -#ifndef RT_GDB_HAVE_HWBP - #define RT_GDB_HAVE_HWBP 0 -#endif -#ifndef RT_GDB_HAVE_SWBP - #define RT_GDB_HAVE_SWBP 1 -#endif - - -#if RT_GDB_HAVE_HWBP - #error GDB:No hardware_breakpoint support -#endif - - -/* - * By doing this as an undefined instruction trap, we force a mode - * switch from SVC to UND mode, allowing us to save full kernel state. - * We also define a GDB_COMPILED_BREAK which can be used to compile - * in breakpoints. - */ -#define BREAK_INSTR_SIZE 4 -#define GDB_BREAKINST 0xe7ffdefe -#define GDB_COMPILED_BREAK 0xe7ffdeff -#define CACHE_FLUSH_IS_SAFE 1 - -#define ARM_GP_REGS 16 -#define ARM_FP_REGS 8 -#define ARM_EXTRA_REGS 2 -#define GDB_MAX_REGS (ARM_GP_REGS + (ARM_FP_REGS * 3) + ARM_EXTRA_REGS) -#define NUMREGBYTES (GDB_MAX_REGS << 2) - - -//#define BUFMAX ((NUMREGBYTES << 1) + 10) -#define BUFMAX 400 - -enum regnames { - GDB_R0, /*0*/ - GDB_R1, /*1*/ - GDB_R2, /*2*/ - GDB_R3, /*3*/ - GDB_R4, /*4*/ - GDB_R5, /*5*/ - GDB_R6, /*6*/ - GDB_R7, /*7*/ - GDB_R8, /*8*/ - GDB_R9, /*9*/ - GDB_R10, /*10*/ - GDB_FP, /*11*/ - GDB_IP, /*12*/ - GDB_SPT, /*13*/ - GDB_LR, /*14*/ - GDB_PC, /*15*/ - GDB_CPSR = GDB_MAX_REGS-1 -}; - -/* arch */ -extern struct gdb_arch arch_gdb_ops; -void gdb_breakpoint(); -void gdb_get_register(unsigned long *gdb_regs); -void gdb_put_register(unsigned long *gdb_regs); -void gdb_set_register(void *hw_regs); -int gdb_arch_handle_exception(char *remcom_in_buffer, - char *remcom_out_buffer); -void gdb_flush_icache_range(unsigned long start, unsigned long end); -int gdb_undef_hook(void *regs); - -int gdb_handle_exception(int signo, void *regs); - -#endif /* __ARM_GDB_H__ */ diff --git a/components/gdb/libcpu/arm/arm_stub.c b/components/gdb/libcpu/arm/arm_stub.c deleted file mode 100644 index a312d39f4a..0000000000 --- a/components/gdb/libcpu/arm/arm_stub.c +++ /dev/null @@ -1,499 +0,0 @@ -/* - * ARM GDB support - * arch-specific portion of GDB stub - * - * File : arm_stub.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-04 Wzyy2 first version - */ -#include -#include -#include -#include - -#define PS_N 0x80000000 -#define PS_Z 0x40000000 -#define PS_C 0x20000000 -#define PS_V 0x10000000 - -#define IS_THUMB_ADDR(addr) ((addr) & 1) -#define MAKE_THUMB_ADDR(addr) ((addr) | 1) -#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) - -static int compiled_break = 0; -static unsigned long step_addr = 0; -static int ins_will_execute(unsigned long ins); -static unsigned long target_ins(unsigned long *pc, unsigned long ins); - - -/*struct gdb_arch - Describe architecture specific values.*/ -struct gdb_arch arch_gdb_ops = { - .gdb_bpt_instr = {0xfe, 0xde, 0xff, 0xe7} //Little-Endian -}; - -struct rt_gdb_register -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; -}*regs; - -/** - * gdb_breakpoint - generate a compiled_breadk - * It is used to sync up with a debugger and stop progarm - */ -void gdb_breakpoint() -{ - asm(".word 0xe7ffdeff"); -} - -void gdb_set_register(void *hw_regs) -{ - regs = (struct rt_gdb_register *)hw_regs; -} -void gdb_get_register(unsigned long *gdb_regs) -{ - int regno; - /* Initialize all to zero. */ - for (regno = 0; regno < GDB_MAX_REGS; regno++) - gdb_regs[regno] = 0; - - gdb_regs[GDB_R0] = regs->r0; - gdb_regs[GDB_R1] = regs->r1; - gdb_regs[GDB_R2] = regs->r2; - gdb_regs[GDB_R3] = regs->r3; - gdb_regs[GDB_R4] = regs->r4; - gdb_regs[GDB_R5] = regs->r5; - gdb_regs[GDB_R6] = regs->r6; - gdb_regs[GDB_R7] = regs->r7; - gdb_regs[GDB_R8] = regs->r8; - gdb_regs[GDB_R9] = regs->r9; - gdb_regs[GDB_R10] = regs->r10; - gdb_regs[GDB_FP] = regs->fp; - gdb_regs[GDB_IP] = regs->ip; - gdb_regs[GDB_SPT] = regs->sp; - gdb_regs[GDB_LR] = regs->lr; - gdb_regs[GDB_PC] = regs->pc; - gdb_regs[GDB_CPSR] = regs->cpsr; - -}; - - -void gdb_put_register(unsigned long *gdb_regs) -{ - regs->r0 = gdb_regs[GDB_R0]; - regs->r1 = gdb_regs[GDB_R1]; - regs->r2 = gdb_regs[GDB_R2]; - regs->r3 = gdb_regs[GDB_R3]; - regs->r4 = gdb_regs[GDB_R4]; - regs->r5 = gdb_regs[GDB_R5]; - regs->r6 = gdb_regs[GDB_R6]; - regs->r7 = gdb_regs[GDB_R7]; - regs->r8 = gdb_regs[GDB_R8]; - regs->r9 = gdb_regs[GDB_R9]; - regs->r10 = gdb_regs[GDB_R10]; - regs->fp = gdb_regs[GDB_FP]; - regs->ip = gdb_regs[GDB_IP]; - regs->sp = gdb_regs[GDB_SPT]; - regs->lr = gdb_regs[GDB_LR]; - regs->pc = gdb_regs[GDB_PC]; - regs->cpsr = gdb_regs[GDB_CPSR]; -} - - -/* It will be called during process_packet */ -int gdb_arch_handle_exception(char *remcom_in_buffer, - char *remcom_out_buffer) -{ - unsigned long addr,curins; - char *ptr; - - /*clear single step*/ - if (step_addr) { - gdb_remove_sw_break(step_addr); - step_addr = 0; - } - - switch (remcom_in_buffer[0]) { - case 'D': - case 'k': - case 'c': - /* - * If this was a compiled breakpoint, we need to move - * to the next instruction or we will breakpoint - * over and over again - */ - ptr = &remcom_in_buffer[1]; - if (gdb_hex2long(&ptr, &addr)) - regs->pc = addr; - else if (compiled_break == 1) - regs->pc += 4; - compiled_break = 0; - return 0; - - case 's': - ptr = &remcom_in_buffer[1]; - if (gdb_hex2long(&ptr, &addr)) - regs->pc = addr; - - curins = *(unsigned long*)(regs->pc); - if (ins_will_execute(curins)) - //Decode instruction to decide what the next pc will be - step_addr = target_ins((unsigned long *)regs->pc, curins); - else - step_addr = regs->pc + 4; - -#ifdef RT_GDB_DEBUG - rt_kprintf("\n next will be %x \n",step_addr); -#endif - gdb_set_sw_break(step_addr); - - if (compiled_break == 1) - regs->pc += 4; - compiled_break = 0; - return 0; - } - - return -1; - -} - -/* flush icache to let the sw breakpoint working */ -void gdb_flush_icache_range(unsigned long start, unsigned long end) -{ -#ifdef RT_GDB_ICACHE - extern void mmu_invalidate_icache(); - mmu_invalidate_icache(); //for arm,wo can only invalidate it -#endif -} - -/* register a hook in undef*/ -int gdb_undef_hook(void *regs) -{ - struct rt_gdb_register *tmp_reg = (struct rt_gdb_register *)regs; - unsigned long *tmp_pc = (unsigned long *)tmp_reg->pc; - - /* it is a compiled break */ - if (*tmp_pc == GDB_COMPILED_BREAK) { - compiled_break = 1; - gdb_handle_exception(SIGTRAP, regs); - return 1; - - } - /* it is a sw break */ - else if (*tmp_pc == GDB_BREAKINST) { - gdb_handle_exception(SIGTRAP, regs); - return 1; - } - /*or we just go */ - return 0; - -} - -static unsigned long gdb_arch_regs[GDB_MAX_REGS]; -static int ins_will_execute(unsigned long ins) -{ - unsigned long psr = regs->cpsr; // condition codes - int res = 0; - switch ((ins & 0xF0000000) >> 28) { - case 0x0: // EQ - res = (psr & PS_Z) != 0; - break; - case 0x1: // NE - res = (psr & PS_Z) == 0; - break; - case 0x2: // CS - res = (psr & PS_C) != 0; - break; - case 0x3: // CC - res = (psr & PS_C) == 0; - break; - case 0x4: // MI - res = (psr & PS_N) != 0; - break; - case 0x5: // PL - res = (psr & PS_N) == 0; - break; - case 0x6: // VS - res = (psr & PS_V) != 0; - break; - case 0x7: // VC - res = (psr & PS_V) == 0; - break; - case 0x8: // HI - res = ((psr & PS_C) != 0) && ((psr & PS_Z) == 0); - break; - case 0x9: // LS - res = ((psr & PS_C) == 0) || ((psr & PS_Z) != 0); - break; - case 0xA: // GE - res = ((psr & (PS_N|PS_V)) == (PS_N|PS_V)) || - ((psr & (PS_N|PS_V)) == 0); - break; - case 0xB: // LT - res = ((psr & (PS_N|PS_V)) == PS_N) || - ((psr & (PS_N|PS_V)) == PS_V); - break; - case 0xC: // GT - res = ((psr & (PS_N|PS_V)) == (PS_N|PS_V)) || - ((psr & (PS_N|PS_V)) == 0); - res = ((psr & PS_Z) == 0) && res; - break; - case 0xD: // LE - res = ((psr & (PS_N|PS_V)) == PS_N) || - ((psr & (PS_N|PS_V)) == PS_V); - res = ((psr & PS_Z) == PS_Z) || res; - break; - case 0xE: // AL - res = 1; - break; - case 0xF: // NV - if (((ins & 0x0E000000) >> 24) == 0xA) - res = 1; - else - res = 0; - break; - } - return res; -} - -static unsigned long RmShifted(int shift) -{ - unsigned long Rm = gdb_arch_regs[shift & 0x00F]; - int shift_count; - if ((shift & 0x010) == 0) { - shift_count = (shift & 0xF80) >> 7; - } else { - shift_count = gdb_arch_regs[(shift & 0xF00) >> 8]; - } - switch ((shift & 0x060) >> 5) { - case 0x0: // Logical left - Rm <<= shift_count; - break; - case 0x1: // Logical right - Rm >>= shift_count; - break; - case 0x2: // Arithmetic right - Rm = (unsigned long)((long)Rm >> shift_count); - break; - case 0x3: // Rotate right - if (shift_count == 0) { - // Special case, RORx - Rm >>= 1; - if (gdb_arch_regs[GDB_CPSR] & PS_C) Rm |= 0x80000000; - } else { - Rm = (Rm >> shift_count) | (Rm << (32-shift_count)); - } - break; - } - return Rm; -} - -// Decide the next instruction to be executed for a given instruction -static unsigned long target_ins(unsigned long *pc, unsigned long ins) -{ - unsigned long new_pc, offset, op2; - unsigned long Rn; - int i, reg_count, c; - - gdb_get_register(gdb_arch_regs); - - switch ((ins & 0x0C000000) >> 26) { - case 0x0: - // BX or BLX - if ((ins & 0x0FFFFFD0) == 0x012FFF10) { - new_pc = (unsigned long)gdb_arch_regs[ins & 0x0000000F]; - return new_pc; - } - // Data processing - new_pc = (unsigned long)(pc+1); - if ((ins & 0x0000F000) == 0x0000F000) { - // Destination register is PC - if ((ins & 0x0FBF0000) != 0x010F0000) { - Rn = (unsigned long)gdb_arch_regs[(ins & 0x000F0000) >> 16]; - if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch! - if ((ins & 0x02000000) == 0) { - op2 = RmShifted(ins & 0x00000FFF); - } else { - op2 = ins & 0x000000FF; - i = (ins & 0x00000F00) >> 8; // Rotate count - op2 = (op2 >> (i*2)) | (op2 << (32-(i*2))); - } - switch ((ins & 0x01E00000) >> 21) { - case 0x0: // AND - new_pc = Rn & op2; - break; - case 0x1: // EOR - new_pc = Rn ^ op2; - break; - case 0x2: // SUB - new_pc = Rn - op2; - break; - case 0x3: // RSB - new_pc = op2 - Rn; - break; - case 0x4: // ADD - new_pc = Rn + op2; - break; - case 0x5: // ADC - c = (gdb_arch_regs[GDB_CPSR] & PS_C) != 0; - new_pc = Rn + op2 + c; - break; - case 0x6: // SBC - c = (gdb_arch_regs[GDB_CPSR] & PS_C) != 0; - new_pc = Rn - op2 + c - 1; - break; - case 0x7: // RSC - c = (gdb_arch_regs[GDB_CPSR] & PS_C) != 0; - new_pc = op2 - Rn +c - 1; - break; - case 0x8: // TST - case 0x9: // TEQ - case 0xA: // CMP - case 0xB: // CMN - break; // PC doesn't change - case 0xC: // ORR - new_pc = Rn | op2; - break; - case 0xD: // MOV - new_pc = op2; - break; - case 0xE: // BIC - new_pc = Rn & ~op2; - break; - case 0xF: // MVN - new_pc = ~op2; - break; - } - } - } - return new_pc; - case 0x1: - if ((ins & 0x02000010) == 0x02000010) { - // Undefined! - return (unsigned long)(pc+1); - } else { - if ((ins & 0x00100000) == 0) { - // STR - return (unsigned long)(pc+1); - } else { - // LDR - if ((ins & 0x0000F000) != 0x0000F000) { - // Rd not PC - return (unsigned long)(pc+1); - } else { - Rn = (unsigned long)gdb_arch_regs[(ins & 0x000F0000) >> 16]; - if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch! - if (ins & 0x01000000) { - // Add/subtract offset before - if ((ins & 0x02000000) == 0) { - // Immediate offset - if (ins & 0x00800000) { - // Add offset - Rn += (ins & 0x00000FFF); - } else { - // Subtract offset - Rn -= (ins & 0x00000FFF); - } - } else { - // Offset is in a register - if (ins & 0x00800000) { - // Add offset - Rn += RmShifted(ins & 0x00000FFF); - } else { - // Subtract offset - Rn -= RmShifted(ins & 0x00000FFF); - } - } - } - return *(unsigned long *)Rn; - } - } - } - return (unsigned long)(pc+1); - case 0x2: // Branch, LDM/STM - if ((ins & 0x02000000) == 0) { - // LDM/STM - if ((ins & 0x00100000) == 0) { - // STM - return (unsigned long)(pc+1); - } else { - // LDM - if ((ins & 0x00008000) == 0) { - // PC not in list - return (unsigned long)(pc+1); - } else { - Rn = (unsigned long)gdb_arch_regs[(ins & 0x000F0000) >> 16]; - if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch! - offset = ins & 0x0000FFFF; - reg_count = 0; - for (i = 0; i < 15; i++) { - if (offset & (1< - -#ifndef RT_GDB_HAVE_HWBP - #define RT_GDB_HAVE_HWBP 1 -#endif -#ifndef RT_GDB_HAVE_SWBP - #define RT_GDB_HAVE_SWBP 0 -#endif - -#ifndef GDB_CORTEXM_PRIORITY_MAX - #define GDB_CORTEXM_PRIORITY_MAX (1 << 6) -#endif - -#define GDB_DATA_ACCESS - -#define BREAK_INSTR_SIZE 4 -#define ARM_GP_REGS 16 -#define ARM_FP_REGS 8 -#define ARM_EXTRA_REGS 2 -#define GDB_MAX_REGS (ARM_GP_REGS + (ARM_FP_REGS * 3) + ARM_EXTRA_REGS) -#define NUMREGBYTES (GDB_MAX_REGS << 2) - -#define HBP_NUM 6 //Max hardware breakpoint -#define HWP_NUM 4 //Max hardware watchpoint - -//#define BUFMAX ((NUMREGBYTES << 1) + 10) -#define BUFMAX 400 - -#define GDB_DEBUG_REG_BASE 0xE000EDF0 -#define GDB_DEBUG_REG_DHSR 0x00 -#define GDB_DEBUG_REG_DCRSR 0x04 -#define GDB_DEBUG_REG_DCRDR 0x08 -#define GDB_DEBUG_REG_DEMCR 0x0c - -#define GDB_DEBUG_REG_DEMCR_MON_EN (1UL << 16) -#define GDB_DEBUG_REG_DEMCR_MON_PEND (1UL << 17) -#define GDB_DEBUG_REG_DEMCR_MON_STEP (1UL << 18) -#define GDB_DEBUG_REG_DEMCR_TRCENA (1UL << 24) - -#define GDB_NVIC_REG_BASE 0xE000E000 -#define GDB_NVIC_REG_SHCSR 0xD24 -#define GDB_NVIC_REG_DFSR 0xD30 - -#define GDB_NVIC_REG_SHCSR_MEMFAULTENA (1 << 16) - -#define GDB_FPB_REG_BASE 0xE0002000 -#define GDB_FPB_REG_CTRL 0x0 -#define GDB_FPB_REG_REMAP 0x4 -#define GDB_FPB_REG_COMP 0x8 - -#define GDB_FPB_REG_CTRL_KEY (1UL << 1) -#define GDB_FPB_REG_CTRL_ENABLE 1 -#define GDB_FPB_REG_COMP_ENABLE 1 -#define GDB_FPB_REG_COMP_ADDR (((1UL << 29) -1) << 2) -#define GDB_FPB_REG_COMP_REPLACE (((1UL << 32) -1) << 30) - -#define GDB_DWT_REG_BASE 0xE0001000 -#define GDB_DWT_REG_CTRL 0x0 -#define GDB_DWT_REG_COMP 0x20 -#define GDB_DWT_REG_MASK 0x24 -#define GDB_DWT_REG_FUNCTION 0x28 - -#define GDB_DWT_REG_FUNCTION_FUC (((1UL << 4) -1) << 0) - - - - -enum regnames { - GDB_R0, /*0*/ - GDB_R1, /*1*/ - GDB_R2, /*2*/ - GDB_R3, /*3*/ - GDB_R4, /*4*/ - GDB_R5, /*5*/ - GDB_R6, /*6*/ - GDB_R7, /*7*/ - GDB_R8, /*8*/ - GDB_R9, /*9*/ - GDB_R10, /*10*/ - GDB_FP, /*11*/ - GDB_IP, /*12*/ - GDB_SPT, /*13*/ - GDB_LR, /*14*/ - GDB_PC, /*15*/ - GDB_F0, /*16*/ - GDB_F1, /*17*/ - GDB_F2, /*18*/ - GDB_F3, /*19*/ - GDB_F4, /*20*/ - GDB_F5, /*21*/ - GDB_F6, /*22*/ - GDB_F7, /*23*/ - GDB_FPS, /*24*/ - GDB_CPSR = GDB_MAX_REGS-1 -}; - -typedef struct -{ - unsigned long type; // State type - unsigned long vector; // Exception vector number - unsigned long basepri; // BASEPRI - - unsigned long r4; // Remaining CPU registers - unsigned long r5; // Remaining CPU registers - unsigned long r6; // Remaining CPU registers - unsigned long r7; // Remaining CPU registers - unsigned long r8; // Remaining CPU registers - unsigned long r9; // Remaining CPU registers - unsigned long r10; // Remaining CPU registers - unsigned long r11; // Remaining CPU registers - unsigned long sp; // Remaining CPU registers - - unsigned long xlr; // Exception return LR - // The following are saved and restored automatically by the CPU - // for exceptions or interrupts. - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r12; - unsigned long lr; - unsigned long pc; - unsigned long psr; -} Gdb_SavedRegisters; - -/* arch */ -extern struct gdb_arch arch_gdb_ops; -void gdb_breakpoint(); -void gdb_get_register(unsigned long *gdb_regs); -void gdb_put_register(unsigned long *gdb_regs); -void gdb_set_register(void *hw_regs); -int gdb_arch_handle_exception(char *remcom_in_buffer, - char *remcom_out_buffer); - -int gdb_permit_data_access(unsigned long addr, unsigned long count); -void gdb_arch_exit(); -void gdb_arch_late(); - -#endif /* __CORTEXM_GDB_H__ */ diff --git a/components/gdb/libcpu/cortexm/cortexm_stub.c b/components/gdb/libcpu/cortexm/cortexm_stub.c deleted file mode 100644 index bcbdc39dd1..0000000000 --- a/components/gdb/libcpu/cortexm/cortexm_stub.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * CORTEXM GDB support - * arch-specific portion of GDB stub - * - * File : cortexm_stub.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2014-07-04 Wzyy2 first version - */ -#include -#include -#include - -static Gdb_SavedRegisters *regs; -unsigned long single_step_basepri = 0; - -void gdb_remove_all_hw_break(); -void gdb_enable_hw_debug(); -void gdb_disable_hw_debug(); -int gdb_set_hw_break(unsigned long, int, enum gdb_bptype); -int gdb_remove_hw_break(unsigned long, int, enum gdb_bptype); - -/*struct gdb_arch - Describe architecture specific values.*/ -struct gdb_arch arch_gdb_ops = { - /* Breakpoint instruction: */ - .gdb_bpt_instr = {0xfe, 0xde, 0xff, 0xe7}, //Little-Endian - .flags = RT_GDB_HAVE_HWBP, - .set_hw_breakpoint = gdb_set_hw_break, - .remove_hw_breakpoint = gdb_remove_hw_break, - .remove_all_hw_break = gdb_remove_all_hw_break -}; - -static struct hw_breakpoint { - int enabled; - unsigned long addr; -} breakinfo[HBP_NUM]; - -static struct hw_watchpoint { - int enabled; - unsigned long addr; - int len; - enum gdb_bptype type; -} watchinfo[HWP_NUM]; - -//The following table defines the memory areas that GDB is allow to touch -static const struct { - unsigned long start; - unsigned long end; -} data_access[] = -{ - { 0x20000000, 0x40000000-1}, // On-chip ram - { 0x60000000, 0xa0000000-1}, // External ram - { 0x00000000, 0x20000000-1}, // On-chip flash - { 0x60000000, 0xa0000000-1}, // External flash - { 0xE0000000, 0x00000000-1}, // cortex-M peripheral - { 0x40000000, 0x60000000-1}, // mcu peripheral -}; - - -int gdb_permit_data_access(unsigned long addr, unsigned long count) -{ - unsigned char i; - - for (i = 0; i < sizeof(data_access)/sizeof(data_access[0]); i++) { - if ((addr >= data_access[i].start) && (addr + count) <= data_access[i].end) { - return 0; - } - } - - return -1; -} - -/*we need to block all pending interrupts by swtting basepri - * before doing the steo - */ -void gdb_single_step() -{ - volatile unsigned long *base; - - //mask all interrupts - single_step_basepri = regs->basepri; - regs->basepri = GDB_CORTEXM_PRIORITY_MAX; - - //When MON_EN = 1, this steps the core - base = (unsigned long*)(GDB_DEBUG_REG_BASE + GDB_DEBUG_REG_DEMCR); - *base |= GDB_DEBUG_REG_DEMCR_MON_STEP; - - /* Clear any bits set in DFSR*/ - base = (unsigned long*)(GDB_NVIC_REG_BASE + GDB_NVIC_REG_DFSR); - *base = 0xffffffff; - -} - -void gdb_clear_single_step() -{ - volatile unsigned long *base; - - regs->basepri = single_step_basepri; - - /*clear single step*/ - base = (unsigned long*)(GDB_DEBUG_REG_BASE + GDB_DEBUG_REG_DEMCR); - *base &= ~GDB_DEBUG_REG_DEMCR_MON_STEP; - - // Clear any bits set in DFSR - base = (unsigned long*)(GDB_NVIC_REG_BASE + GDB_NVIC_REG_DFSR); - *base = 0xffffffff; - -} - -/** - * gdb_breakpoint - generate a breadk - * It is used to sync up with a debugger and stop progarm - */ -void gdb_breakpoint() -{ - volatile unsigned long *base; - - // Enable the FPB-FLASH PATCH BREAKPOINT - base = (unsigned long*)(GDB_FPB_REG_BASE + GDB_FPB_REG_CTRL); - *base |= GDB_FPB_REG_CTRL_KEY | GDB_FPB_REG_CTRL_ENABLE ; - - base = (unsigned long*)(GDB_DEBUG_REG_BASE + GDB_DEBUG_REG_DEMCR); - /* - * Enable the debug monitor. When enabled, the System handler priority - * register controls its priority level. - * If disabled, then all debug events go - * to Hard fault - */ - *base |= GDB_DEBUG_REG_DEMCR_MON_EN; - - // Enable DWT - *base |= GDB_DEBUG_REG_DEMCR_TRCENA ; - - //Fall into debug monitor - *base |= GDB_DEBUG_REG_DEMCR_MON_PEND; - -} - -void gdb_set_register(void *hw_regs) -{ - regs = hw_regs; -} - -void gdb_get_register(unsigned long *gdb_regs) -{ - int regno; - /* Initialize all to zero. */ - for (regno = 0; regno < GDB_MAX_REGS; regno++) - gdb_regs[regno] = 0; - - gdb_regs[GDB_R0] = regs->r0; - gdb_regs[GDB_R1] = regs->r1; - gdb_regs[GDB_R2] = regs->r2; - gdb_regs[GDB_R3] = regs->r3; - gdb_regs[GDB_R4] = regs->r4; - gdb_regs[GDB_R5] = regs->r5; - gdb_regs[GDB_R6] = regs->r6; - gdb_regs[GDB_R7] = regs->r7; - gdb_regs[GDB_R8] = regs->r8; - gdb_regs[GDB_R9] = regs->r9; - gdb_regs[GDB_R10] = regs->r10; - gdb_regs[GDB_FP] = regs->r11; - gdb_regs[GDB_IP] = regs->r12; - gdb_regs[GDB_SPT] = regs->sp; - gdb_regs[GDB_LR] = regs->lr; - gdb_regs[GDB_PC] = regs->pc; - gdb_regs[GDB_CPSR] = regs->psr; - -}; - - -void gdb_put_register(unsigned long *gdb_regs) -{ - regs->r0 = gdb_regs[GDB_R0]; - regs->r1 = gdb_regs[GDB_R1]; - regs->r2 = gdb_regs[GDB_R2]; - regs->r3 = gdb_regs[GDB_R3]; - - regs->r4 = gdb_regs[GDB_R4]; - regs->r5 = gdb_regs[GDB_R5]; - regs->r6 = gdb_regs[GDB_R6]; - regs->r7 = gdb_regs[GDB_R7]; - regs->r8 = gdb_regs[GDB_R8]; - regs->r9 = gdb_regs[GDB_R9]; - regs->r10 = gdb_regs[GDB_R10]; - regs->r11 = gdb_regs[GDB_FP]; - regs->r12 = gdb_regs[GDB_IP]; - regs->sp = gdb_regs[GDB_SPT]; - regs->lr = gdb_regs[GDB_LR]; - regs->pc = gdb_regs[GDB_PC]; - regs->psr = gdb_regs[GDB_CPSR]; - -} - - -/* It will be called during process_packet */ -int gdb_arch_handle_exception(char *remcom_in_buffer, - char *remcom_out_buffer) -{ - unsigned long addr; - char *ptr; - static int step = 0; - - if (step){ - gdb_clear_single_step(); - step = 0; - } - - switch (remcom_in_buffer[0]) { - case 'D': - case 'k': - case 'c': - /* - * If this was a compiled breakpoint, we need to move - * to the next instruction or we will breakpoint - * over and over again - */ - ptr = &remcom_in_buffer[1]; - if (gdb_hex2long(&ptr, &addr)) - regs->pc = addr; - - return 0; - case 's': - ptr = &remcom_in_buffer[1]; - if (gdb_hex2long(&ptr, &addr)) - regs->pc = addr; - - gdb_single_step(); - step = 1; - - return 0; - } - - return -1; - -} - -int gdb_set_hw_break(unsigned long addr, int len, enum gdb_bptype bptype) -{ - int i; - - if (bptype == BP_HARDWARE_BREAKPOINT) { - for (i = 0; i < HBP_NUM; i++) - if (!breakinfo[i].enabled) - break; - if (i == HBP_NUM) - return -1; - breakinfo[i].addr = addr; - breakinfo[i].enabled = 1; - } - else if (bptype == BP_WRITE_WATCHPOINT) { - for (i = 0; i < HWP_NUM; i++) - if (!watchinfo[i].enabled) - break; - if (i == HWP_NUM) - return -1; - watchinfo[i].addr = addr; - watchinfo[i].len = len; - watchinfo[i].type = BP_WRITE_WATCHPOINT; - watchinfo[i].enabled = 1; - } - else if (bptype == BP_READ_WATCHPOINT) { - for (i = 0; i < HWP_NUM; i++) - if (!watchinfo[i].enabled) - break; - if (i == HWP_NUM) - return -1; - watchinfo[i].addr = addr; - watchinfo[i].len = len; - watchinfo[i].type = BP_READ_WATCHPOINT; - watchinfo[i].enabled = 1; - } - else if (bptype == BP_ACCESS_WATCHPOINT) { - for (i = 0; i < HWP_NUM; i++) - if (!watchinfo[i].enabled) - break; - if (i == HWP_NUM) - return -1; - watchinfo[i].addr = addr; - watchinfo[i].len = len; - watchinfo[i].type = BP_ACCESS_WATCHPOINT; - watchinfo[i].enabled = 1; - } - - return 0; -} - -int gdb_remove_hw_break(unsigned long addr, int len, enum gdb_bptype bptype) -{ - int i; - - if (bptype == BP_HARDWARE_BREAKPOINT) { - for (i = 0; i < HBP_NUM; i++) - if (breakinfo[i].addr == addr && breakinfo[i].enabled) - break; - if (i == HBP_NUM) - return -1; - breakinfo[i].enabled = 0; - - } - else if (bptype == BP_WRITE_WATCHPOINT) { - for (i = 0; i < HWP_NUM; i++) - if (watchinfo[i].addr == addr && watchinfo[i].enabled && watchinfo[i].type == bptype) - break; - if (i == HWP_NUM) - return -1; - watchinfo[i].enabled = 0; - - } - else if (bptype == BP_READ_WATCHPOINT) { - for (i = 0; i < HWP_NUM; i++) - if (watchinfo[i].addr == addr && watchinfo[i].enabled && watchinfo[i].type == bptype) - break; - if (i == HWP_NUM) - return -1; - watchinfo[i].enabled = 0; - - } - else if (bptype == BP_ACCESS_WATCHPOINT) { - for (i = 0; i < HWP_NUM; i++) - if (watchinfo[i].addr == addr && watchinfo[i].enabled && watchinfo[i].type == bptype) - break; - if (i == HWP_NUM) - return -1; - watchinfo[i].enabled = 0; - - } - - return 0; -} - -void gdb_remove_all_hw_break() -{ - int i; - volatile unsigned long *base; - - // Disable hardware break - for (i = 0; i < HBP_NUM; i++) { - if (!breakinfo[i].enabled) - break; - base = (unsigned long*)(GDB_FPB_REG_BASE + GDB_FPB_REG_COMP + i * 4); - *base &= ~GDB_FPB_REG_COMP_ENABLE ; - } - - // Disable watchpoint - for (i = 0; i < HWP_NUM; i++) { - if (!watchinfo[i].enabled) - break; - base = (unsigned long*)(GDB_DWT_REG_BASE + GDB_DWT_REG_FUNCTION + i * 12); - *base &= ~GDB_DWT_REG_FUNCTION_FUC ; - } - -} - -void gdb_arch_late() -{ - gdb_remove_all_hw_break(); -} - -void gdb_arch_exit() -{ - volatile unsigned long *base; - char num = 1; - int i; - - // Install the hardware break - for (i = 0; i < HBP_NUM; i++) { - if (breakinfo[i].enabled) { - base = (unsigned long*)(GDB_FPB_REG_BASE + GDB_FPB_REG_COMP + i * 4); - - *base = GDB_FPB_REG_COMP_ADDR & ((unsigned long)(breakinfo[i].addr)); - - if (breakinfo[i].addr & 2) - *base |= (1UL << 31); //set BKPT on upper halfword - else - *base |= (1UL << 30); //set BKPT on lower halfword, - - *base |= GDB_FPB_REG_COMP_ENABLE ; - } - } - - // Install the watchpoint - for (i = 0; i < HWP_NUM; i++) { - if (watchinfo[i].enabled) { - base = (unsigned long*)(GDB_DWT_REG_BASE + GDB_DWT_REG_COMP + i * 12); - *base = watchinfo[i].addr; - - base = (unsigned long*)(GDB_DWT_REG_BASE + GDB_DWT_REG_MASK + i * 12); - while (watchinfo[i].len >> num) { - num++; - } - *base = num - 1; //DWT matching is performed as:(ADDR & (~0 << MASK)) == COMP - - base = (unsigned long*)(GDB_DWT_REG_BASE + GDB_DWT_REG_FUNCTION + i * 12); - - if (watchinfo[i].type == BP_WRITE_WATCHPOINT) - *base = (*base & ~GDB_DWT_REG_FUNCTION_FUC) + 0x05; - else if (watchinfo[i].type == BP_READ_WATCHPOINT) - *base = (*base & ~GDB_DWT_REG_FUNCTION_FUC) + 0x06; - else if (watchinfo[i].type == BP_ACCESS_WATCHPOINT) - *base = (*base & ~GDB_DWT_REG_FUNCTION_FUC) + 0x07; - - } - } - -} - diff --git a/components/gdb/libcpu/cortexm/gdb_gcc.S b/components/gdb/libcpu/cortexm/gdb_gcc.S deleted file mode 100644 index e6c5ab95e8..0000000000 --- a/components/gdb/libcpu/cortexm/gdb_gcc.S +++ /dev/null @@ -1,27 +0,0 @@ -.cpu cortex-m4 -.syntax unified -.thumb -.text - -.global DebugMon_Handler -.type DebugMon_Handler, %function -DebugMon_Handler: - mrs r0,psp ;// Get process stack - sub r1,r0,#(4*13) ;// Make space for saved state - msr psp,r1 ;// Ensure PSP is up to date - - mov r12,r0 ;// R12 = stack - mov r1,#1 ;// R1 = exception state type - mrs r2,ipsr ;// R2 = vector number - mrs r3,basepri ;// R3 = basepri - stmfd r0!,{r1-r12,lr} ;// Push type, vector, basepri, r4-11 - - mov r4,r0 ;// R4 = saved state pointer - bl rt_hw_debugmon_exception - - mov r0,r4 ;// R4 = saved state pointer - ldmfd r0!,{r1-r12,lr} ;// Pop type, vec, basepri, registers and LR - msr psp,r0 ;// Restore PSP - msr basepri,r3 ;// Restore basepri - - bx lr ;// Return diff --git a/components/gdb/libcpu/cortexm/gdb_handler.c b/components/gdb/libcpu/cortexm/gdb_handler.c deleted file mode 100644 index 05904224c2..0000000000 --- a/components/gdb/libcpu/cortexm/gdb_handler.c +++ /dev/null @@ -1,11 +0,0 @@ -#include -#include - -void rt_hw_debugmon_exception(void *regs) -{ -#ifdef RT_USING_GDB - gdb_arch_late(); - gdb_handle_exception(SIGTRAP, regs); - gdb_arch_exit(); -#endif -} diff --git a/components/gdb/readme-zh.txt b/components/gdb/readme-zh.txt deleted file mode 100644 index 06cdc01c76..0000000000 --- a/components/gdb/readme-zh.txt +++ /dev/null @@ -1,118 +0,0 @@ -说明: - -一 当前版本进度 - -1).分类 -考虑到arm各种版本的调试寄存器地址和种类都有很大不同 -所以分为两个版本,均只在GCC下编译 - - 1.基础ARM(软件断点(使用undef指令的办法),需要ram运行，模拟单步) - 2.cortex M系列(不支持M0,基于寄存器操作,支持硬件断点，数据观察点,硬件单步) - -理论上cortexA系列和cortexM的调式单元是一样的,有需要的话也可以在基础arm版本里单独为cortexA做出可选的数据断点,硬件单步 - -二 安装说明 - -1) 下载 - 下载最新RT-THREAD GDB STUB代码,并解压 - -2) 加入RT-Thread - 先将得到的components文件夹覆盖RTT根目录 - 然后若要使用BBB板测试GDB,就用BSP/beaglebone和libpcu/am335x覆盖RTT下的同名文件夹 - - 若要使用STM32F407测试GDB,就用BSP/stm32F4xx覆盖RTT下的同名文件夹,同时更改编译器为gcc - -3) 宏 - 打开RT_USING_GDB - -三 宏配置说明 - -1) RT_GDB_HAVE_HWBP - 1硬件断点 - -2) RT_GDB_HAVE_SWBP - 1软件断点 - -3) RT_GDB_MAX_BREAKPOINTS - 最大软件断点数量 - 不加默认20 - -4) RT_GDB_ICACHE - 是否使用ICACHE - 若使用了ICACHE则要开启此宏,保证断点覆盖后及时刷新 - -5) RT_GDB_DEBUG - 测试开发用 - 会打印GDB收发信息到默认串口上,以供获取数据 - -四 使用说明 - -1) 设置serial设备 - 首先需要调用 - void gdb_set_device(const char* device_name); (gdb_stub.h) - 设置相应的GDB通信端口 - PS: - 首先serial的驱动不能是中断 - 其次收发函数最好是poll的,要不就是9600,不然可能会出现问题 - 若出现问题,请打开 RT_GDB_DEBUG ,观察收发是否正常。 - -2) 进入GDB stub - 调用 - void gdb_start(); (gdb_stub.h) - 触发异常,即可进入等待状态 等待GDB连接 - 也可以将该函数加入按键中断中,可以实现外部打断程序的效果(条件有限,未测试) - -3) pc连接 - 确认GCC 打开-g选项后编译 - 然后arm-none-eabi-gdb xxxx.elf or axf - 进如GDB界面后 - set serial baud 115200(or 9600) - target remote /dev/ttyUSB0(linux) or COM1 (windows) - 即可实现GDB对接 - -PS: - BBB板默认uart4作为GDB通信口 - STM32F407默认uart6作GDB通信 - -五 移植说明 - -若要移植到不同架构上 -软件实现请参考gdb/libcpu/arm下的文件 -硬件实现请参考gdb/libcpu/cortexm下的文件 -需要rsp协议的话 请参考https://www.sourceware.org/gdb/current/onlinedocs/gdb/Remote-Protocol.html - -若要移植到已有架构的芯片上 -1) arm9,11以及cortexA - 修改udef和dabt的函数,在/libcpu/arm/am335x/trap.c里,加入ifdef GDB的内容 - 将libcpu/arm/am335x/start_gcc.s的相关异常向量汇编复制到自己的undef和dabt异常向量里 - 分配足够的栈空间给undef - -2) cortexM3以及M4 - 删除已有的debugmon_handler - 优先级分组有变化的话,重定义宏GDB_CORTEXM_PRIORITY_MAX,就是basepri的设置值,满足屏蔽中断的同时不屏蔽debugmon - 使用有需要的话,重定义cortexm_stub.c的data_acess数组,也就是允许GDB访问的地址空间 - 增大_system_stack_size,也就是MSP栈的大小 - - -六 易错或者bug(出错了看这里) - -编译器选项是否打开-g,是否使用GCC编译 -硬件断点使用超过(max-1)个后,单步可能会出现不正常 -检查串口通信是否正常,可以打开RT_GDB_DEBUG -堆栈大小是否设置合适(因为gdb要在handler模式下运行,所需要的栈大小比较大,大概0x200) -cm系列切记如果优先级分组不同于默认设置,就要重定义宏GDB_CORTEXM_PRIORITY_MAX,使抢占优先级等于1,不然单步可能会出现问题(被中断抢占) -cm系列在中断里设置断点会出现错误(目测程序还是正常工作,就是压栈的寄存器还是进入中断前的,所以返回的寄存器信息有误) -cm系列可能会因为访问不可访问的地址造成出错,有需求自己手动修改cortexm_stub.c的data_acess数组(没找到好的办法,falut后寄存器全乱了) - - -## - 嫌速度慢的话就把串口速度9600改成115200 - 不过如此就要把注册的驱动里的getc改成阻塞的,不然会收不到 - 类似 - while(!(UART_LSR_REG(uart->base) & 0x01)); - ch = UART_RHR_REG(uart->base) & 0xff; - 原先是 - if (UART_LSR_REG(uart->base) & 0x01) - { - ch = UART_RHR_REG(uart->base) & 0xff; - } diff --git a/components/libc/Kconfig b/components/libc/Kconfig index 2b4f6af8b0..b2abe69850 100644 --- a/components/libc/Kconfig +++ b/components/libc/Kconfig @@ -28,11 +28,9 @@ if RT_USING_LIBC && RT_USING_DFS default n endif - if RT_USING_MODULE - config RT_USING_LIBDL - bool "Enable dlopen/dlsym/dlclose feature" + config RT_USING_MODULE + bool "Enable dynamic module with dlopen/dlsym/dlclose feature" default n - endif endif endmenu diff --git a/components/libc/aio/posix_aio.c b/components/libc/aio/posix_aio.c index 03e653bdd1..75e7de9ce3 100644 --- a/components/libc/aio/posix_aio.c +++ b/components/libc/aio/posix_aio.c @@ -1,21 +1,7 @@ /* - * File : posix_aio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/aio/posix_aio.h b/components/libc/aio/posix_aio.h index 0787538aa0..f20ed48cb3 100644 --- a/components/libc/aio/posix_aio.h +++ b/components/libc/aio/posix_aio.h @@ -1,21 +1,7 @@ /* - * File : posix_aio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/armlibc/dirent.h b/components/libc/compilers/armlibc/dirent.h index 1adf952031..d3bc58cbc5 100644 --- a/components/libc/compilers/armlibc/dirent.h +++ b/components/libc/compilers/armlibc/dirent.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __RTT_DIRENT_H__ #define __RTT_DIRENT_H__ diff --git a/components/libc/compilers/armlibc/fcntl.h b/components/libc/compilers/armlibc/fcntl.h index 324b73f218..80cf1b4409 100644 --- a/components/libc/compilers/armlibc/fcntl.h +++ b/components/libc/compilers/armlibc/fcntl.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef FCNTL_H__ #define FCNTL_H__ diff --git a/components/libc/compilers/armlibc/libc.c b/components/libc/compilers/armlibc/libc.c index c3fab19fdc..fee390d4b4 100644 --- a/components/libc/compilers/armlibc/libc.c +++ b/components/libc/compilers/armlibc/libc.c @@ -1,23 +1,7 @@ /* - * File : libc.c - * Brief : armcc libc initialization + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/armlibc/libc.h b/components/libc/compilers/armlibc/libc.h index e57897f0a8..158fe06c3e 100644 --- a/components/libc/compilers/armlibc/libc.h +++ b/components/libc/compilers/armlibc/libc.h @@ -1,23 +1,7 @@ /* - * File : libc.h - * Brief : armcc libc header file + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/armlibc/libc_syms.c b/components/libc/compilers/armlibc/libc_syms.c index fc84aec77a..0e1c42d899 100644 --- a/components/libc/compilers/armlibc/libc_syms.c +++ b/components/libc/compilers/armlibc/libc_syms.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include #include diff --git a/components/libc/compilers/armlibc/mem_std.c b/components/libc/compilers/armlibc/mem_std.c index 7fa0033f9d..e160104a25 100644 --- a/components/libc/compilers/armlibc/mem_std.c +++ b/components/libc/compilers/armlibc/mem_std.c @@ -1,13 +1,7 @@ /* - * File : mem_std.c - * Brief : implement standard memory routins. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of Device File System in RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * 2014-08-03 bernard Add file header. @@ -16,22 +10,25 @@ #include "rtthread.h" #ifdef RT_USING_HEAP + +#ifdef __CC_ARM /* avoid the heap and heap-using library functions supplied by arm */ #pragma import(__use_no_heap) +#endif -void *malloc(int n) +void *malloc(size_t n) { return rt_malloc(n); } RTM_EXPORT(malloc); -void *realloc(void *rmem, rt_size_t newsize) +void *realloc(void *rmem, size_t newsize) { return rt_realloc(rmem, newsize); } RTM_EXPORT(realloc); -void *calloc(rt_size_t nelem, rt_size_t elsize) +void *calloc(size_t nelem, size_t elsize) { return rt_calloc(nelem, elsize); } diff --git a/components/libc/compilers/armlibc/stdio.c b/components/libc/compilers/armlibc/stdio.c index d1ac976568..5262a4dd92 100644 --- a/components/libc/compilers/armlibc/stdio.c +++ b/components/libc/compilers/armlibc/stdio.c @@ -1,23 +1,7 @@ /* - * File : stdio.c - * Brief : stdio/console + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -65,11 +49,27 @@ int libc_stdio_get_console(void) int libc_stdio_read(void *buffer, size_t size) { - return read(std_fd, buffer, size); + if (std_fd >= 0) + { + return read(std_fd, buffer, size); + } + else + { + rt_kprintf("Illegal stdio input!\n"); + return 0; + } } int libc_stdio_write(const void *buffer, size_t size) { - return write(std_fd, buffer, size); + if (std_fd >= 0) + { + return write(std_fd, buffer, size); + } + else + { + rt_kprintf("Illegal stdio output!\n"); + return size; + } } #endif diff --git a/components/libc/compilers/armlibc/stubs.c b/components/libc/compilers/armlibc/stubs.c index b9be260357..6e9f13d143 100644 --- a/components/libc/compilers/armlibc/stubs.c +++ b/components/libc/compilers/armlibc/stubs.c @@ -1,23 +1,7 @@ /* - * File : stubs.c - * Brief : reimplement some basic functions of arm standard c library + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -37,7 +21,11 @@ #include "dfs_posix.h" #endif +#ifdef __CLANG_ARM +__asm(".global __use_no_semihosting\n\t"); +#else #pragma import(__use_no_semihosting_swi) +#endif /* Standard IO device handles. */ #define STDIN 0 @@ -249,7 +237,7 @@ int _sys_tmpnam(char *name, int fileno, unsigned maxlength) char *_sys_command_string(char *cmd, int len) { /* no support */ - return cmd; + return RT_NULL; } /* This function writes a character to the console. */ @@ -309,17 +297,18 @@ int system(const char *string) int fputc(int c, FILE *f) { - char ch = c; + char ch[2] = {0}; - rt_kprintf(&ch); + ch[0] = c; + rt_kprintf(&ch[0]); return 1; } int fgetc(FILE *f) { +#ifdef RT_USING_POSIX char ch; -#ifdef RT_USING_POSIX if (libc_stdio_read(&ch, 1) == 1) return ch; #endif diff --git a/components/libc/compilers/armlibc/sys/errno.h b/components/libc/compilers/armlibc/sys/errno.h index 8ee115ed04..9c4307ebfb 100644 --- a/components/libc/compilers/armlibc/sys/errno.h +++ b/components/libc/compilers/armlibc/sys/errno.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef SYS_ERRNO_H__ #define SYS_ERRNO_H__ diff --git a/components/libc/compilers/armlibc/sys/mman.h b/components/libc/compilers/armlibc/sys/mman.h index 024a64e911..8c61b32b7c 100644 --- a/components/libc/compilers/armlibc/sys/mman.h +++ b/components/libc/compilers/armlibc/sys/mman.h @@ -1,21 +1,7 @@ /* - * File : mman.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/armlibc/sys/stat.h b/components/libc/compilers/armlibc/sys/stat.h index e69de29bb2..ce95230e88 100644 --- a/components/libc/compilers/armlibc/sys/stat.h +++ b/components/libc/compilers/armlibc/sys/stat.h @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ diff --git a/components/libc/compilers/armlibc/sys/time.h b/components/libc/compilers/armlibc/sys/time.h index 2d60b37317..bac122e183 100644 --- a/components/libc/compilers/armlibc/sys/time.h +++ b/components/libc/compilers/armlibc/sys/time.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _SYS_TIME_H_ #define _SYS_TIME_H_ @@ -37,6 +45,7 @@ struct timezone { }; int gettimeofday(struct timeval *tp, void *ignore); +struct tm *gmtime_r(const time_t *timep, struct tm *r); #ifdef __cplusplus } diff --git a/components/libc/compilers/armlibc/sys/types.h b/components/libc/compilers/armlibc/sys/types.h index b01d8283d4..4c76dfc429 100644 --- a/components/libc/compilers/armlibc/sys/types.h +++ b/components/libc/compilers/armlibc/sys/types.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __TYPES_H__ #define __TYPES_H__ diff --git a/components/libc/compilers/armlibc/sys/unistd.h b/components/libc/compilers/armlibc/sys/unistd.h index 56979955ba..33f0561e72 100644 --- a/components/libc/compilers/armlibc/sys/unistd.h +++ b/components/libc/compilers/armlibc/sys/unistd.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _SYS_UNISTD_H #define _SYS_UNISTD_H diff --git a/components/libc/compilers/armlibc/termios.h b/components/libc/compilers/armlibc/termios.h index 0b54066a76..1956121225 100644 --- a/components/libc/compilers/armlibc/termios.h +++ b/components/libc/compilers/armlibc/termios.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _TERMIOS_H__ #define _TERMIOS_H__ diff --git a/components/libc/compilers/armlibc/time.c b/components/libc/compilers/armlibc/time.c index e7ad19ad3c..29c5c6cdd2 100644 --- a/components/libc/compilers/armlibc/time.c +++ b/components/libc/compilers/armlibc/time.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/components/libc/compilers/armlibc/unistd.h b/components/libc/compilers/armlibc/unistd.h index 3de0eaf398..70187722d8 100644 --- a/components/libc/compilers/armlibc/unistd.h +++ b/components/libc/compilers/armlibc/unistd.h @@ -1 +1,9 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include "sys/unistd.h" diff --git a/components/libc/compilers/common/SConscript b/components/libc/compilers/common/SConscript new file mode 100644 index 0000000000..02bf49941d --- /dev/null +++ b/components/libc/compilers/common/SConscript @@ -0,0 +1,12 @@ +from building import * + +Import('rtconfig') + +src = Glob('*.c') +cwd = GetCurrentDir() +group = [] +CPPPATH = [cwd] + +group = DefineGroup('libc', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/libc/compilers/common/gmtime_r.c b/components/libc/compilers/common/gmtime_r.c new file mode 100644 index 0000000000..dff251ab6c --- /dev/null +++ b/components/libc/compilers/common/gmtime_r.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-26 zylx first version + */ + +#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined (__IAR_SYSTEMS_ICC__) +#include + +/* seconds per day */ +#define SPD 24*60*60 + +/* days per month -- nonleap! */ +const short __spm[13] = +{ + 0, + (31), + (31 + 28), + (31 + 28 + 31), + (31 + 28 + 31 + 30), + (31 + 28 + 31 + 30 + 31), + (31 + 28 + 31 + 30 + 31 + 30), + (31 + 28 + 31 + 30 + 31 + 30 + 31), + (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31), + (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30), + (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31), + (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30), + (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30 + 31), +}; + +int __isleap(int year) +{ + /* every fourth year is a leap year except for century years that are + * not divisible by 400. */ + /* return (year % 4 == 0 && (year % 100 != 0 || year % 400 == 0)); */ + return (!(year % 4) && ((year % 100) || !(year % 400))); +} + +/** + * This function will convert Time (Restartable) + * + * @param timep the timestamp + * @param the structure to stores information + * + * @return the structure to stores information + * + */ +struct tm *gmtime_r(const time_t *timep, struct tm *r) +{ + time_t i; + register time_t work = *timep % (SPD); + r->tm_sec = work % 60; + work /= 60; + r->tm_min = work % 60; + r->tm_hour = work / 60; + work = *timep / (SPD); + r->tm_wday = (4 + work) % 7; + for (i = 1970;; ++i) + { + register time_t k = __isleap(i) ? 366 : 365; + if (work >= k) + work -= k; + else + break; + } + r->tm_year = i - 1900; + r->tm_yday = work; + + r->tm_mday = 1; + if (__isleap(i) && (work > 58)) + { + if (work == 59) + r->tm_mday = 2; /* 29.2. */ + work -= 1; + } + + for (i = 11; i && (__spm[i] > work); --i) + ; + r->tm_mon = i; + r->tm_mday += work - __spm[i]; + return r; +} +#endif /* end of __CC_ARM or __CLANG_ARM or __IAR_SYSTEMS_ICC__ */ + diff --git a/components/libc/compilers/dlib/dirent.h b/components/libc/compilers/dlib/dirent.h index 61e77b9767..4c897cc550 100644 --- a/components/libc/compilers/dlib/dirent.h +++ b/components/libc/compilers/dlib/dirent.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __RTT_DIRENT_H__ #define __RTT_DIRENT_H__ diff --git a/components/libc/compilers/dlib/environ.c b/components/libc/compilers/dlib/environ.c index 1e44eb1627..ac19758838 100644 --- a/components/libc/compilers/dlib/environ.c +++ b/components/libc/compilers/dlib/environ.c @@ -1,20 +1,7 @@ -/* File: environ.c - * this file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/fcntl.h b/components/libc/compilers/dlib/fcntl.h index e69de29bb2..ce95230e88 100644 --- a/components/libc/compilers/dlib/fcntl.h +++ b/components/libc/compilers/dlib/fcntl.h @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ diff --git a/components/libc/compilers/dlib/libc.c b/components/libc/compilers/dlib/libc.c index fa977ab399..8b42411a6b 100644 --- a/components/libc/compilers/dlib/libc.c +++ b/components/libc/compilers/dlib/libc.c @@ -1,23 +1,7 @@ /* - * File : libc.c - * Brief : iar dlib initialization + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/libc.h b/components/libc/compilers/dlib/libc.h index d0a081d538..7b2665c32b 100644 --- a/components/libc/compilers/dlib/libc.h +++ b/components/libc/compilers/dlib/libc.h @@ -1,23 +1,7 @@ /* - * File : libc.h - * Brief : iar dlib header file + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/rmtx.c b/components/libc/compilers/dlib/rmtx.c index 4bf7140271..69405c8f6a 100644 --- a/components/libc/compilers/dlib/rmtx.c +++ b/components/libc/compilers/dlib/rmtx.c @@ -1,21 +1,7 @@ /* - * File : rmtx.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/stdio.c b/components/libc/compilers/dlib/stdio.c index 12c1081d8b..b35ade7a38 100644 --- a/components/libc/compilers/dlib/stdio.c +++ b/components/libc/compilers/dlib/stdio.c @@ -1,23 +1,7 @@ /* - * File : stdio.c - * Brief : stdio/console + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/sys/errno.h b/components/libc/compilers/dlib/sys/errno.h index 072892edc1..1ecb58b74c 100644 --- a/components/libc/compilers/dlib/sys/errno.h +++ b/components/libc/compilers/dlib/sys/errno.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef SYS_ERRNO_H__ #define SYS_ERRNO_H__ diff --git a/components/libc/compilers/dlib/sys/mman.h b/components/libc/compilers/dlib/sys/mman.h index 024a64e911..8c61b32b7c 100644 --- a/components/libc/compilers/dlib/sys/mman.h +++ b/components/libc/compilers/dlib/sys/mman.h @@ -1,21 +1,7 @@ /* - * File : mman.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/sys/stat.h b/components/libc/compilers/dlib/sys/stat.h index e69de29bb2..ce95230e88 100644 --- a/components/libc/compilers/dlib/sys/stat.h +++ b/components/libc/compilers/dlib/sys/stat.h @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ diff --git a/components/libc/compilers/dlib/sys/time.h b/components/libc/compilers/dlib/sys/time.h index 1acb836032..baf566936b 100644 --- a/components/libc/compilers/dlib/sys/time.h +++ b/components/libc/compilers/dlib/sys/time.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _SYS_TIME_H_ #define _SYS_TIME_H_ @@ -44,6 +52,7 @@ struct timezone { }; int gettimeofday(struct timeval *tp, void *ignore); +struct tm *gmtime_r(const time_t *timep, struct tm *r); #ifdef __cplusplus } diff --git a/components/libc/compilers/dlib/sys/types.h b/components/libc/compilers/dlib/sys/types.h index b01d8283d4..4c76dfc429 100644 --- a/components/libc/compilers/dlib/sys/types.h +++ b/components/libc/compilers/dlib/sys/types.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __TYPES_H__ #define __TYPES_H__ diff --git a/components/libc/compilers/dlib/sys/unistd.h b/components/libc/compilers/dlib/sys/unistd.h index dbe4f3010d..5985a42996 100644 --- a/components/libc/compilers/dlib/sys/unistd.h +++ b/components/libc/compilers/dlib/sys/unistd.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _SYS_UNISTD_H #define _SYS_UNISTD_H diff --git a/components/libc/compilers/dlib/syscall_close.c b/components/libc/compilers/dlib/syscall_close.c index 5792bb3806..f46162deb7 100644 --- a/components/libc/compilers/dlib/syscall_close.c +++ b/components/libc/compilers/dlib/syscall_close.c @@ -1,21 +1,7 @@ /* - * File : syscall_close.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/syscall_lseek.c b/components/libc/compilers/dlib/syscall_lseek.c index 950ba52f65..b79cc410b7 100644 --- a/components/libc/compilers/dlib/syscall_lseek.c +++ b/components/libc/compilers/dlib/syscall_lseek.c @@ -1,21 +1,7 @@ /* - * File : syscall_lseek.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/syscall_mem.c b/components/libc/compilers/dlib/syscall_mem.c index b3933ba910..236ef1c12d 100644 --- a/components/libc/compilers/dlib/syscall_mem.c +++ b/components/libc/compilers/dlib/syscall_mem.c @@ -1,21 +1,7 @@ /* - * File : syscall_mem.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/syscall_open.c b/components/libc/compilers/dlib/syscall_open.c index 6194707549..96e02dc32a 100644 --- a/components/libc/compilers/dlib/syscall_open.c +++ b/components/libc/compilers/dlib/syscall_open.c @@ -1,22 +1,8 @@ /* -* File : syscall_open.c -* This file is part of RT-Thread RTOS -* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2015-01-28 Bernard first version diff --git a/components/libc/compilers/dlib/syscall_read.c b/components/libc/compilers/dlib/syscall_read.c index e7e99629d7..e248211486 100644 --- a/components/libc/compilers/dlib/syscall_read.c +++ b/components/libc/compilers/dlib/syscall_read.c @@ -1,21 +1,7 @@ /* - * File : syscall_read.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/syscall_remove.c b/components/libc/compilers/dlib/syscall_remove.c index b7dd9477b7..e7f0268b1b 100644 --- a/components/libc/compilers/dlib/syscall_remove.c +++ b/components/libc/compilers/dlib/syscall_remove.c @@ -1,21 +1,7 @@ /* - * File : syscall_remove.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/syscall_write.c b/components/libc/compilers/dlib/syscall_write.c index 79d702339a..85c0da22c3 100644 --- a/components/libc/compilers/dlib/syscall_write.c +++ b/components/libc/compilers/dlib/syscall_write.c @@ -1,21 +1,7 @@ /* - * File : syscall_write.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/syscalls.h b/components/libc/compilers/dlib/syscalls.h index 2c38854f72..993962e8db 100644 --- a/components/libc/compilers/dlib/syscalls.h +++ b/components/libc/compilers/dlib/syscalls.h @@ -1,20 +1,7 @@ -/* File: syscalls.h - * this file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/dlib/termios.h b/components/libc/compilers/dlib/termios.h index 0b54066a76..1956121225 100644 --- a/components/libc/compilers/dlib/termios.h +++ b/components/libc/compilers/dlib/termios.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _TERMIOS_H__ #define _TERMIOS_H__ diff --git a/components/libc/compilers/dlib/time.c b/components/libc/compilers/dlib/time.c index e7ad19ad3c..87574df851 100644 --- a/components/libc/compilers/dlib/time.c +++ b/components/libc/compilers/dlib/time.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include @@ -32,43 +40,47 @@ int gettimeofday(struct timeval *tp, void *ignore) * @return time_t return timestamp current. * */ +#pragma module_name = "?time" +#if _DLIB_TIME_USES_64 +time_t __time64(time_t *t) +#else /* for IAR 6.2 later Compiler */ #if defined (__IAR_SYSTEMS_ICC__) && (__VER__) >= 6020000 -#pragma module_name = "?time" -time_t (__time32)(time_t *t) /* Only supports 32-bit timestamp */ +time_t __time32(time_t *t) #else time_t time(time_t *t) #endif +#endif { - time_t time_now = 0; - + time_t time_now = 0; + #ifdef RT_USING_RTC - static rt_device_t device = RT_NULL; - - /* optimization: find rtc device only first. */ - if (device == RT_NULL) + static rt_device_t device = RT_NULL; + + /* optimization: find rtc device only first. */ + if (device == RT_NULL) + { + device = rt_device_find("rtc"); + } + + /* read timestamp from RTC device. */ + if (device != RT_NULL) + { + if (rt_device_open(device, 0) == RT_EOK) { - device = rt_device_find("rtc"); - } - - /* read timestamp from RTC device. */ - if (device != RT_NULL) - { - if (rt_device_open(device, 0) == RT_EOK) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time_now); - rt_device_close(device); - } + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time_now); + rt_device_close(device); } + } #endif /* RT_USING_RTC */ - - /* if t is not NULL, write timestamp to *t */ - if (t != RT_NULL) - { - *t = time_now; - } - - return time_now; + + /* if t is not NULL, write timestamp to *t */ + if (t != RT_NULL) + { + *t = time_now; + } + + return time_now; } RT_WEAK clock_t clock(void) diff --git a/components/libc/compilers/dlib/unistd.h b/components/libc/compilers/dlib/unistd.h index d67f8fb6f2..a07d8409c2 100644 --- a/components/libc/compilers/dlib/unistd.h +++ b/components/libc/compilers/dlib/unistd.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _UNISTD_H_ #define _UNISTD_H_ diff --git a/components/libc/compilers/minilibc/ctype.c b/components/libc/compilers/minilibc/ctype.c index fed8f583a6..b94ff2dae8 100644 --- a/components/libc/compilers/minilibc/ctype.c +++ b/components/libc/compilers/minilibc/ctype.c @@ -1,11 +1,7 @@ /* - * File : ctype.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/ctype.h b/components/libc/compilers/minilibc/ctype.h index 6b93490d36..5f41376ed8 100644 --- a/components/libc/compilers/minilibc/ctype.h +++ b/components/libc/compilers/minilibc/ctype.h @@ -1,11 +1,7 @@ /* - * File : ctype.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/errno.h b/components/libc/compilers/minilibc/errno.h index 74b8296241..a7ee380594 100644 --- a/components/libc/compilers/minilibc/errno.h +++ b/components/libc/compilers/minilibc/errno.h @@ -1,77 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __ERRNO_H__ #define __ERRNO_H__ -#ifdef RT_USING_DFS - -#include - -/* using device error codes */ -#define ENOENT DFS_STATUS_ENOENT -#define EIO DFS_STATUS_EIO -#define ENXIO DFS_STATUS_ENXIO -#define EBADF DFS_STATUS_EBADF -#define EAGAIN DFS_STATUS_EAGAIN -#define ENOMEM DFS_STATUS_ENOMEM -#define EBUSY DFS_STATUS_EBUSY -#define EEXIST DFS_STATUS_EEXIST -#define EXDEV DFS_STATUS_EXDEV -#define ENODEV DFS_STATUS_ENODEV -#define ENOTDIR DFS_STATUS_ENOTDIR -#define EISDIR DFS_STATUS_EISDIR -#define EINVAL DFS_STATUS_EINVAL -#define ENOSPC DFS_STATUS_ENOSPC -#define EROFS DFS_STATUS_EROFS -#define ENOSYS DFS_STATUS_ENOSYS -#define ENOTEMPTY DFS_STATUS_ENOTEMPTY - -#else - -/* error codes */ -#define ENOENT 2 /* No such file or directory */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define EBADF 9 /* Bad file number */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* no memory */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENOSPC 28 /* No space left on device */ -#define EROFS 30 /* Read-only file system */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ - -#endif - -#define EPERM 1 /* Not super-user */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EFAULT 14 /* Bad address */ -#define ENFILE 23 /* Too many open files in system */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 45 /* Deadlock condition */ -#define EBADMSG 77 /* Trying to read unreadable message */ -#define EMSGSIZE 90 /* Message too long */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ETIMEDOUT 116 /* Connection timed out */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define ENOTSUP 134 /* Not supported */ +#include "libc/libc_errno.h" +/* Others defined in libc/libc_errno.h */ #define ENSRNOTFOUND 163 /* Domain name not found */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ #endif diff --git a/components/libc/compilers/minilibc/inttypes.h b/components/libc/compilers/minilibc/inttypes.h index 84e036a043..8bab743655 100644 --- a/components/libc/compilers/minilibc/inttypes.h +++ b/components/libc/compilers/minilibc/inttypes.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __INTTYPES_H__ #define __INTTYPES_H__ diff --git a/components/libc/compilers/minilibc/math.c b/components/libc/compilers/minilibc/math.c index 27315a428c..cd5770178e 100644 --- a/components/libc/compilers/minilibc/math.c +++ b/components/libc/compilers/minilibc/math.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include /* diff --git a/components/libc/compilers/minilibc/math.h b/components/libc/compilers/minilibc/math.h index b436eb08b5..9ddb9c859b 100644 --- a/components/libc/compilers/minilibc/math.h +++ b/components/libc/compilers/minilibc/math.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __MATH_H__ #define __MATH_H__ diff --git a/components/libc/compilers/minilibc/qsort.c b/components/libc/compilers/minilibc/qsort.c index f412986e1d..2b97ce763c 100644 --- a/components/libc/compilers/minilibc/qsort.c +++ b/components/libc/compilers/minilibc/qsort.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/components/libc/compilers/minilibc/rand.c b/components/libc/compilers/minilibc/rand.c index 387d605d4c..88603dc808 100644 --- a/components/libc/compilers/minilibc/rand.c +++ b/components/libc/compilers/minilibc/rand.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include #include diff --git a/components/libc/compilers/minilibc/stddef.h b/components/libc/compilers/minilibc/stddef.h index 8068277117..7353a157cb 100644 --- a/components/libc/compilers/minilibc/stddef.h +++ b/components/libc/compilers/minilibc/stddef.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __STDDEF_H__ #define __STDDEF_H__ diff --git a/components/libc/compilers/minilibc/stdint.h b/components/libc/compilers/minilibc/stdint.h index c865d43435..bd5fdc83f5 100644 --- a/components/libc/compilers/minilibc/stdint.h +++ b/components/libc/compilers/minilibc/stdint.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ /* * ISO C Standard: 7.18 Integer types */ diff --git a/components/libc/compilers/minilibc/stdio.h b/components/libc/compilers/minilibc/stdio.h index a6ecb32931..678682cf5e 100644 --- a/components/libc/compilers/minilibc/stdio.h +++ b/components/libc/compilers/minilibc/stdio.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __STDIO_H__ #define __STDIO_H__ diff --git a/components/libc/compilers/minilibc/stdlib.c b/components/libc/compilers/minilibc/stdlib.c index e29ae9bc2e..8154ec5b8b 100644 --- a/components/libc/compilers/minilibc/stdlib.c +++ b/components/libc/compilers/minilibc/stdlib.c @@ -1,11 +1,7 @@ /* - * File : stdlib.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/stdlib.h b/components/libc/compilers/minilibc/stdlib.h index 4e87537d3f..d57d95b64d 100644 --- a/components/libc/compilers/minilibc/stdlib.h +++ b/components/libc/compilers/minilibc/stdlib.h @@ -1,11 +1,7 @@ /* - * File : stdlib.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/string.c b/components/libc/compilers/minilibc/string.c index 4e90da1554..1ab7c0509f 100644 --- a/components/libc/compilers/minilibc/string.c +++ b/components/libc/compilers/minilibc/string.c @@ -1,11 +1,7 @@ /* - * File : string.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/string.h b/components/libc/compilers/minilibc/string.h index 089903e993..45524c7764 100644 --- a/components/libc/compilers/minilibc/string.h +++ b/components/libc/compilers/minilibc/string.h @@ -1,11 +1,7 @@ /* - * File : string.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/sys/mman.h b/components/libc/compilers/minilibc/sys/mman.h index 024a64e911..8c61b32b7c 100644 --- a/components/libc/compilers/minilibc/sys/mman.h +++ b/components/libc/compilers/minilibc/sys/mman.h @@ -1,21 +1,7 @@ /* - * File : mman.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/minilibc/sys/stat.h b/components/libc/compilers/minilibc/sys/stat.h index 7826cba945..65db477a4a 100644 --- a/components/libc/compilers/minilibc/sys/stat.h +++ b/components/libc/compilers/minilibc/sys/stat.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __STAT_H__ #define __STAT_H__ diff --git a/components/libc/compilers/minilibc/sys/time.h b/components/libc/compilers/minilibc/sys/time.h index 9cb330df5c..22a93f5c9d 100644 --- a/components/libc/compilers/minilibc/sys/time.h +++ b/components/libc/compilers/minilibc/sys/time.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _SYS_TIME_H_ #define _SYS_TIME_H_ diff --git a/components/libc/compilers/minilibc/sys/types.h b/components/libc/compilers/minilibc/sys/types.h index 850bafea43..0c00a79d1e 100644 --- a/components/libc/compilers/minilibc/sys/types.h +++ b/components/libc/compilers/minilibc/sys/types.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __TYPES_H__ #define __TYPES_H__ diff --git a/components/libc/compilers/minilibc/time.c b/components/libc/compilers/minilibc/time.c index 605f6f573e..508558bafc 100644 --- a/components/libc/compilers/minilibc/time.c +++ b/components/libc/compilers/minilibc/time.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/components/libc/compilers/minilibc/time.h b/components/libc/compilers/minilibc/time.h index d64feba0b8..09fc7d2e67 100644 --- a/components/libc/compilers/minilibc/time.h +++ b/components/libc/compilers/minilibc/time.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __TIME_H__ #define __TIME_H__ diff --git a/components/libc/compilers/newlib/libc.c b/components/libc/compilers/newlib/libc.c index 0b7350c30e..2234c36f98 100644 --- a/components/libc/compilers/newlib/libc.c +++ b/components/libc/compilers/newlib/libc.c @@ -1,23 +1,7 @@ /* - * File : libc.c - * Brief : gcc libc header file + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -39,7 +23,7 @@ int _EXFUN(putenv,(char *__string)); int libc_system_init(void) { -#if defined(RT_USING_DFS) & defined(RT_USING_DFS_DEVFS) +#if defined(RT_USING_DFS) & defined(RT_USING_DFS_DEVFS) & defined(RT_USING_CONSOLE) rt_device_t dev_console; dev_console = rt_console_get_device(); @@ -51,11 +35,11 @@ int libc_system_init(void) libc_stdio_set_console(dev_console->parent.name, O_WRONLY); #endif } -#endif /* set PATH and HOME */ putenv("PATH=/bin"); putenv("HOME=/home"); +#endif #if defined RT_USING_PTHREADS && !defined RT_USING_COMPONENTS_INIT pthread_system_init(); diff --git a/components/libc/compilers/newlib/libc.h b/components/libc/compilers/newlib/libc.h index d077de9656..ab9334fe26 100644 --- a/components/libc/compilers/newlib/libc.h +++ b/components/libc/compilers/newlib/libc.h @@ -1,23 +1,7 @@ /* - * File : libc.h - * Brief : gcc libc header file + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,8 +10,15 @@ #ifndef __RTT_LIBC_H__ #define __RTT_LIBC_H__ +#include +#include +#include #include +#ifndef _EXFUN +#define _EXFUN(name, proto) name proto +#endif + #define MILLISECOND_PER_SECOND 1000UL #define MICROSECOND_PER_SECOND 1000000UL #define NANOSECOND_PER_SECOND 1000000000UL diff --git a/components/libc/compilers/newlib/libc_syms.c b/components/libc/compilers/newlib/libc_syms.c index ed8686e5dd..b150c10fd6 100644 --- a/components/libc/compilers/newlib/libc_syms.c +++ b/components/libc/compilers/newlib/libc_syms.c @@ -1,23 +1,7 @@ /* - * File : libc_syms.c - * Brief : exported symbols for libc. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/newlib/stdio.c b/components/libc/compilers/newlib/stdio.c index 9f30106b72..233a447396 100644 --- a/components/libc/compilers/newlib/stdio.c +++ b/components/libc/compilers/newlib/stdio.c @@ -1,23 +1,7 @@ /* - * File : stdio.c - * Brief : stdio for newlib + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/newlib/sys/dirent.h b/components/libc/compilers/newlib/sys/dirent.h index 2efc683579..db8c0655a1 100644 --- a/components/libc/compilers/newlib/sys/dirent.h +++ b/components/libc/compilers/newlib/sys/dirent.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __RTT_DIRENT_H__ #define __RTT_DIRENT_H__ diff --git a/components/libc/compilers/newlib/sys/mman.h b/components/libc/compilers/newlib/sys/mman.h index 024a64e911..8c61b32b7c 100644 --- a/components/libc/compilers/newlib/sys/mman.h +++ b/components/libc/compilers/newlib/sys/mman.h @@ -1,21 +1,7 @@ /* - * File : mman.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/compilers/newlib/sys/statfs.h b/components/libc/compilers/newlib/sys/statfs.h index 95772b5ead..3c923a21f9 100644 --- a/components/libc/compilers/newlib/sys/statfs.h +++ b/components/libc/compilers/newlib/sys/statfs.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef __RTT_STATFS_H__ #define __RTT_STATFS_H__ diff --git a/components/libc/compilers/newlib/sys/termios.h b/components/libc/compilers/newlib/sys/termios.h index e69de29bb2..ce95230e88 100644 --- a/components/libc/compilers/newlib/sys/termios.h +++ b/components/libc/compilers/newlib/sys/termios.h @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ diff --git a/components/libc/compilers/newlib/syscalls.c b/components/libc/compilers/newlib/syscalls.c index 822182ba93..e4cda478cb 100644 --- a/components/libc/compilers/newlib/syscalls.c +++ b/components/libc/compilers/newlib/syscalls.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include #include @@ -11,6 +19,10 @@ #include #endif +#ifdef RT_USING_MODULE +#include +#endif + /* Reentrant versions of system calls. */ int @@ -379,18 +391,12 @@ _free_r (struct _reent *ptr, void *addr) } void -_exit (int status) +exit (int status) { #ifdef RT_USING_MODULE - rt_module_t module; - - module = rt_module_self(); - if (module != RT_NULL) + if (dlmodule_self()) { - rt_thread_suspend(rt_thread_self()); - - /* re-schedule */ - rt_schedule(); + dlmodule_exit(status); } #endif diff --git a/components/libc/compilers/newlib/termios.h b/components/libc/compilers/newlib/termios.h index 0b54066a76..1956121225 100644 --- a/components/libc/compilers/newlib/termios.h +++ b/components/libc/compilers/newlib/termios.h @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #ifndef _TERMIOS_H__ #define _TERMIOS_H__ diff --git a/components/libc/compilers/newlib/time.c b/components/libc/compilers/newlib/time.c index e7ad19ad3c..29c5c6cdd2 100644 --- a/components/libc/compilers/newlib/time.c +++ b/components/libc/compilers/newlib/time.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/components/libc/libdl/SConscript b/components/libc/libdl/SConscript index 493dd4b256..93636e4b7a 100644 --- a/components/libc/libdl/SConscript +++ b/components/libc/libdl/SConscript @@ -1,14 +1,14 @@ from building import * Import('rtconfig') -src = Glob('*.c') + Glob('*.cpp') +src = Glob('*.c') + Glob('*.cpp') + Glob('arch/*.c') cwd = GetCurrentDir() group = [] CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': group = DefineGroup('libc', src, - depend = ['RT_USING_MODULE', 'RT_USING_LIBDL'], + depend = ['RT_USING_MODULE'], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/libdl/arch/arm.c b/components/libc/libdl/arch/arm.c new file mode 100644 index 0000000000..a53c04f0bc --- /dev/null +++ b/components/libc/libdl/arch/arm.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/08/29 Bernard first version + */ + +#include "../dlmodule.h" +#include "../dlelf.h" + +#ifdef __arm__ +int dlmodule_relocate(struct rt_dlmodule *module, Elf32_Rel *rel, Elf32_Addr sym_val) +{ + Elf32_Addr *where, tmp; + Elf32_Sword addend, offset; + rt_uint32_t upper, lower, sign, j1, j2; + + where = (Elf32_Addr *)((rt_uint8_t *)module->mem_space + + rel->r_offset + - module->vstart_addr); + switch (ELF32_R_TYPE(rel->r_info)) + { + case R_ARM_NONE: + break; + case R_ARM_ABS32: + *where += (Elf32_Addr)sym_val; + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_ARM_ABS32: %x -> %x\n", + where, *where)); + break; + case R_ARM_PC24: + case R_ARM_PLT32: + case R_ARM_CALL: + case R_ARM_JUMP24: + addend = *where & 0x00ffffff; + if (addend & 0x00800000) + addend |= 0xff000000; + tmp = sym_val - (Elf32_Addr)where + (addend << 2); + tmp >>= 2; + *where = (*where & 0xff000000) | (tmp & 0x00ffffff); + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_ARM_PC24: %x -> %x\n", + where, *where)); + break; + case R_ARM_REL32: + *where += sym_val - (Elf32_Addr)where; + RT_DEBUG_LOG(RT_DEBUG_MODULE, + ("R_ARM_REL32: %x -> %x, sym %x, offset %x\n", + where, *where, sym_val, rel->r_offset)); + break; + case R_ARM_V4BX: + *where &= 0xf000000f; + *where |= 0x01a0f000; + break; + + case R_ARM_GLOB_DAT: + case R_ARM_JUMP_SLOT: + *where = (Elf32_Addr)sym_val; + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_ARM_JUMP_SLOT: 0x%x -> 0x%x 0x%x\n", + where, *where, sym_val)); + break; +#if 0 /* To do */ + case R_ARM_GOT_BREL: + temp = (Elf32_Addr)sym_val; + *where = (Elf32_Addr)&temp; + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_ARM_GOT_BREL: 0x%x -> 0x%x 0x%x\n", + where, *where, sym_val)); + break; +#endif + + case R_ARM_RELATIVE: + *where = (Elf32_Addr)sym_val + *where; + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_ARM_RELATIVE: 0x%x -> 0x%x 0x%x\n", + where, *where, sym_val)); + break; + case R_ARM_THM_CALL: + case R_ARM_THM_JUMP24: + upper = *(rt_uint16_t *)where; + lower = *(rt_uint16_t *)((Elf32_Addr)where + 2); + + sign = (upper >> 10) & 1; + j1 = (lower >> 13) & 1; + j2 = (lower >> 11) & 1; + offset = (sign << 24) | + ((~(j1 ^ sign) & 1) << 23) | + ((~(j2 ^ sign) & 1) << 22) | + ((upper & 0x03ff) << 12) | + ((lower & 0x07ff) << 1); + if (offset & 0x01000000) + offset -= 0x02000000; + offset += sym_val - (Elf32_Addr)where; + + if (!(offset & 1) || + offset <= (rt_int32_t)0xff000000 || + offset >= (rt_int32_t)0x01000000) + { + rt_kprintf("Module: Only Thumb addresses allowed\n"); + + return -1; + } + + sign = (offset >> 24) & 1; + j1 = sign ^ (~(offset >> 23) & 1); + j2 = sign ^ (~(offset >> 22) & 1); + *(rt_uint16_t *)where = (rt_uint16_t)((upper & 0xf800) | + (sign << 10) | + ((offset >> 12) & 0x03ff)); + *(rt_uint16_t *)(where + 2) = (rt_uint16_t)((lower & 0xd000) | + (j1 << 13) | (j2 << 11) | + ((offset >> 1) & 0x07ff)); + upper = *(rt_uint16_t *)where; + lower = *(rt_uint16_t *)((Elf32_Addr)where + 2); + break; + default: + return -1; + } + + return 0; +} +#endif diff --git a/components/libc/libdl/arch/x86.c b/components/libc/libdl/arch/x86.c new file mode 100644 index 0000000000..16f2322fb4 --- /dev/null +++ b/components/libc/libdl/arch/x86.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/09/15 parai first version + */ + +#include "../dlmodule.h" +#include "../dlelf.h" + +#ifdef __i386__ + +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +int dlmodule_relocate(struct rt_dlmodule *module, Elf32_Rel *rel, Elf32_Addr sym_val) +{ + Elf32_Addr *where, tmp; + Elf32_Sword addend, offset; + rt_uint32_t upper, lower, sign, j1, j2; + + where = (Elf32_Addr *)((rt_uint8_t *)module->mem_space + + rel->r_offset + - module->vstart_addr); + + switch (ELF32_R_TYPE(rel->r_info)) + { + case R_X86_64_GLOB_DAT: + case R_X86_64_JUMP_SLOT: + *where = (Elf32_Addr)sym_val; + + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_X86_64_JUMP_SLOT: 0x%x -> 0x%x 0x%x\n", + (uint32_t)where, *where, sym_val)); + break; + case R_X86_64_RELATIVE: + *where = (Elf32_Addr)sym_val + *where; + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("R_X86_64_RELATIVE: 0x%x -> 0x%x 0x%x\n", + (uint32_t)where, *where, sym_val)); + break; + default: + RT_DEBUG_LOG(RT_DEBUG_MODULE, ("X86ELF: invalid relocate TYPE %d\n", ELF32_R_TYPE(rel->r_info))); + return -1; + } + + return 0; +} +#endif diff --git a/components/libc/libdl/dlclose.c b/components/libc/libdl/dlclose.c index af070891fc..1202e13f2c 100644 --- a/components/libc/libdl/dlclose.c +++ b/components/libc/libdl/dlclose.c @@ -1,36 +1,39 @@ /* - * File : dlclose.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-17 yi.qiu first version + * Date Author Notes + * 2010-11-17 yi.qiu first version */ #include #include -int dlclose (void *handle) +#include "dlmodule.h" + +int dlclose(void *handle) { - rt_module_t module; - - RT_ASSERT(handle != RT_NULL); - - module = (rt_module_t)handle; - module->nref--; - - if(module->nref <= 0) - { - rt_module_unload(module); - } + struct rt_dlmodule *module; - return RT_TRUE; + RT_ASSERT(handle != RT_NULL); + + module = (struct rt_dlmodule *)handle; + + rt_enter_critical(); + module->nref--; + if (module->nref <= 0) + { + rt_exit_critical(); + + dlmodule_destroy(module); + } + else + { + rt_exit_critical(); + } + + return RT_TRUE; } - RTM_EXPORT(dlclose) - diff --git a/components/libc/libdl/dlelf.c b/components/libc/libdl/dlelf.c new file mode 100644 index 0000000000..6d83424b80 --- /dev/null +++ b/components/libc/libdl/dlelf.c @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/08/29 Bernard first version + */ + +#include "dlmodule.h" +#include "dlelf.h" + +#define DBG_SECTION_NAME "DLMD" +#define DBG_ENABLE // enable debug macro +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include // must after of DEBUG_ENABLE or some other options + +rt_err_t dlmodule_load_shared_object(struct rt_dlmodule* module, void *module_ptr) +{ + rt_bool_t linked = RT_FALSE; + rt_uint32_t index, module_size = 0; + Elf32_Addr vstart_addr, vend_addr; + rt_bool_t has_vstart; + + RT_ASSERT(module_ptr != RT_NULL); + + if (rt_memcmp(elf_module->e_ident, RTMMAG, SELFMAG) == 0) + { + /* rtmlinker finished */ + linked = RT_TRUE; + } + + /* get the ELF image size */ + has_vstart = RT_FALSE; + vstart_addr = vend_addr = RT_NULL; + for (index = 0; index < elf_module->e_phnum; index++) + { + if (phdr[index].p_type != PT_LOAD) + continue; + + LOG_D("LOAD segment: %d, 0x%p, 0x%08x", index, phdr[index].p_vaddr, phdr[index].p_memsz); + + if (phdr[index].p_memsz < phdr[index].p_filesz) + { + rt_kprintf("invalid elf: segment %d: p_memsz: %d, p_filesz: %d\n", + index, phdr[index].p_memsz, phdr[index].p_filesz); + return RT_NULL; + } + if (!has_vstart) + { + vstart_addr = phdr[index].p_vaddr; + vend_addr = phdr[index].p_vaddr + phdr[index].p_memsz; + has_vstart = RT_TRUE; + if (vend_addr < vstart_addr) + { + rt_kprintf("invalid elf: segment %d: p_vaddr: %d, p_memsz: %d\n", + index, phdr[index].p_vaddr, phdr[index].p_memsz); + return RT_NULL; + } + } + else + { + if (phdr[index].p_vaddr < vend_addr) + { + rt_kprintf("invalid elf: segment should be sorted and not overlapped\n"); + return RT_NULL; + } + if (phdr[index].p_vaddr > vend_addr + 16) + { + /* There should not be too much padding in the object files. */ + LOG_W("warning: too much padding before segment %d", index); + } + + vend_addr = phdr[index].p_vaddr + phdr[index].p_memsz; + if (vend_addr < phdr[index].p_vaddr) + { + rt_kprintf("invalid elf: " + "segment %d address overflow\n", index); + return RT_NULL; + } + } + } + + module_size = vend_addr - vstart_addr; + LOG_D("module size: %d, vstart_addr: 0x%p", module_size, vstart_addr); + if (module_size == 0) + { + rt_kprintf("Module: size error\n"); + return -RT_ERROR; + } + + module->vstart_addr = vstart_addr; + module->nref = 0; + + /* allocate module space */ + module->mem_space = rt_malloc(module_size); + if (module->mem_space == RT_NULL) + { + rt_kprintf("Module: allocate space failed.\n"); + return -RT_ERROR; + } + module->mem_size = module_size; + + /* zero all space */ + rt_memset(module->mem_space, 0, module_size); + for (index = 0; index < elf_module->e_phnum; index++) + { + if (phdr[index].p_type == PT_LOAD) + { + rt_memcpy(module->mem_space + phdr[index].p_vaddr - vstart_addr, + (rt_uint8_t *)elf_module + phdr[index].p_offset, + phdr[index].p_filesz); + } + } + + /* set module entry */ + module->entry_addr = module->mem_space + elf_module->e_entry - vstart_addr; + + /* handle relocation section */ + for (index = 0; index < elf_module->e_shnum; index ++) + { + rt_uint32_t i, nr_reloc; + Elf32_Sym *symtab; + Elf32_Rel *rel; + rt_uint8_t *strtab; + static rt_bool_t unsolved = RT_FALSE; + + if (!IS_REL(shdr[index])) + continue; + + /* get relocate item */ + rel = (Elf32_Rel *)((rt_uint8_t *)module_ptr + shdr[index].sh_offset); + + /* locate .rel.plt and .rel.dyn section */ + symtab = (Elf32_Sym *)((rt_uint8_t *)module_ptr + + shdr[shdr[index].sh_link].sh_offset); + strtab = (rt_uint8_t *)module_ptr + + shdr[shdr[shdr[index].sh_link].sh_link].sh_offset; + nr_reloc = (rt_uint32_t)(shdr[index].sh_size / sizeof(Elf32_Rel)); + + /* relocate every items */ + for (i = 0; i < nr_reloc; i ++) + { + Elf32_Sym *sym = &symtab[ELF32_R_SYM(rel->r_info)]; + + LOG_D("relocate symbol %s shndx %d", strtab + sym->st_name, sym->st_shndx); + + if ((sym->st_shndx != SHT_NULL) ||(ELF_ST_BIND(sym->st_info) == STB_LOCAL)) + { + Elf32_Addr addr; + + addr = (Elf32_Addr)(module->mem_space + sym->st_value - vstart_addr); + dlmodule_relocate(module, rel, addr); + } + else if (!linked) + { + Elf32_Addr addr; + + LOG_D("relocate symbol: %s", strtab + sym->st_name); + /* need to resolve symbol in kernel symbol table */ + addr = dlmodule_symbol_find((const char *)(strtab + sym->st_name)); + if (addr == 0) + { + LOG_E("Module: can't find %s in kernel symbol table", strtab + sym->st_name); + unsolved = RT_TRUE; + } + else + { + dlmodule_relocate(module, rel, addr); + } + } + rel ++; + } + + if (unsolved) + return -RT_ERROR; + } + + /* construct module symbol table */ + for (index = 0; index < elf_module->e_shnum; index ++) + { + /* find .dynsym section */ + rt_uint8_t *shstrab; + shstrab = (rt_uint8_t *)module_ptr + + shdr[elf_module->e_shstrndx].sh_offset; + if (rt_strcmp((const char *)(shstrab + shdr[index].sh_name), ELF_DYNSYM) == 0) + break; + } + + /* found .dynsym section */ + if (index != elf_module->e_shnum) + { + int i, count = 0; + Elf32_Sym *symtab = RT_NULL; + rt_uint8_t *strtab = RT_NULL; + + symtab = (Elf32_Sym *)((rt_uint8_t *)module_ptr + shdr[index].sh_offset); + strtab = (rt_uint8_t *)module_ptr + shdr[shdr[index].sh_link].sh_offset; + + for (i = 0; i < shdr[index].sh_size / sizeof(Elf32_Sym); i++) + { + if ((ELF_ST_BIND(symtab[i].st_info) == STB_GLOBAL) && + (ELF_ST_TYPE(symtab[i].st_info) == STT_FUNC)) + count ++; + } + + module->symtab = (struct rt_module_symtab *)rt_malloc + (count * sizeof(struct rt_module_symtab)); + module->nsym = count; + for (i = 0, count = 0; i < shdr[index].sh_size / sizeof(Elf32_Sym); i++) + { + rt_size_t length; + + if ((ELF_ST_BIND(symtab[i].st_info) != STB_GLOBAL) || + (ELF_ST_TYPE(symtab[i].st_info) != STT_FUNC)) + continue; + + length = rt_strlen((const char *)(strtab + symtab[i].st_name)) + 1; + + module->symtab[count].addr = + (void *)(module->mem_space + symtab[i].st_value - module->vstart_addr); + module->symtab[count].name = rt_malloc(length); + rt_memset((void *)module->symtab[count].name, 0, length); + rt_memcpy((void *)module->symtab[count].name, + strtab + symtab[i].st_name, + length); + count ++; + } + } + + return RT_EOK; +} + +rt_err_t dlmodule_load_relocated_object(struct rt_dlmodule* module, void *module_ptr) +{ + rt_uint32_t index, rodata_addr = 0, bss_addr = 0, data_addr = 0; + rt_uint32_t module_addr = 0, module_size = 0; + rt_uint8_t *ptr, *strtab, *shstrab; + + /* get the ELF image size */ + for (index = 0; index < elf_module->e_shnum; index ++) + { + /* text */ + if (IS_PROG(shdr[index]) && IS_AX(shdr[index])) + { + module_size += shdr[index].sh_size; + module_addr = shdr[index].sh_addr; + } + /* rodata */ + if (IS_PROG(shdr[index]) && IS_ALLOC(shdr[index])) + { + module_size += shdr[index].sh_size; + } + /* data */ + if (IS_PROG(shdr[index]) && IS_AW(shdr[index])) + { + module_size += shdr[index].sh_size; + } + /* bss */ + if (IS_NOPROG(shdr[index]) && IS_AW(shdr[index])) + { + module_size += shdr[index].sh_size; + } + } + + /* no text, data and bss on image */ + if (module_size == 0) return RT_NULL; + + module->vstart_addr = 0; + + /* allocate module space */ + module->mem_space = rt_malloc(module_size); + if (module->mem_space == RT_NULL) + { + rt_kprintf("Module: allocate space failed.\n"); + return -RT_ERROR; + } + module->mem_size = module_size; + + /* zero all space */ + ptr = module->mem_space; + rt_memset(ptr, 0, module_size); + + /* load text and data section */ + for (index = 0; index < elf_module->e_shnum; index ++) + { + /* load text section */ + if (IS_PROG(shdr[index]) && IS_AX(shdr[index])) + { + rt_memcpy(ptr, + (rt_uint8_t *)elf_module + shdr[index].sh_offset, + shdr[index].sh_size); + LOG_D("load text 0x%x, size %d", ptr, shdr[index].sh_size); + ptr += shdr[index].sh_size; + } + + /* load rodata section */ + if (IS_PROG(shdr[index]) && IS_ALLOC(shdr[index])) + { + rt_memcpy(ptr, + (rt_uint8_t *)elf_module + shdr[index].sh_offset, + shdr[index].sh_size); + rodata_addr = (rt_uint32_t)ptr; + LOG_D("load rodata 0x%x, size %d, rodata 0x%x", ptr, + shdr[index].sh_size, *(rt_uint32_t *)data_addr); + ptr += shdr[index].sh_size; + } + + /* load data section */ + if (IS_PROG(shdr[index]) && IS_AW(shdr[index])) + { + rt_memcpy(ptr, + (rt_uint8_t *)elf_module + shdr[index].sh_offset, + shdr[index].sh_size); + data_addr = (rt_uint32_t)ptr; + LOG_D("load data 0x%x, size %d, data 0x%x", ptr, + shdr[index].sh_size, *(rt_uint32_t *)data_addr); + ptr += shdr[index].sh_size; + } + + /* load bss section */ + if (IS_NOPROG(shdr[index]) && IS_AW(shdr[index])) + { + rt_memset(ptr, 0, shdr[index].sh_size); + bss_addr = (rt_uint32_t)ptr; + LOG_D("load bss 0x%x, size %d", ptr, shdr[index].sh_size); + } + } + + /* set module entry */ + module->entry_addr = (rt_dlmodule_entry_func_t)((rt_uint8_t *)module->mem_space + elf_module->e_entry - module_addr); + + /* handle relocation section */ + for (index = 0; index < elf_module->e_shnum; index ++) + { + rt_uint32_t i, nr_reloc; + Elf32_Sym *symtab; + Elf32_Rel *rel; + + if (!IS_REL(shdr[index])) + continue; + + /* get relocate item */ + rel = (Elf32_Rel *)((rt_uint8_t *)module_ptr + shdr[index].sh_offset); + + /* locate .dynsym and .dynstr */ + symtab = (Elf32_Sym *)((rt_uint8_t *)module_ptr + + shdr[shdr[index].sh_link].sh_offset); + strtab = (rt_uint8_t *)module_ptr + + shdr[shdr[shdr[index].sh_link].sh_link].sh_offset; + shstrab = (rt_uint8_t *)module_ptr + + shdr[elf_module->e_shstrndx].sh_offset; + nr_reloc = (rt_uint32_t)(shdr[index].sh_size / sizeof(Elf32_Rel)); + + /* relocate every items */ + for (i = 0; i < nr_reloc; i ++) + { + Elf32_Sym *sym = &symtab[ELF32_R_SYM(rel->r_info)]; + + LOG_D("relocate symbol: %s", strtab + sym->st_name); + + if (sym->st_shndx != STN_UNDEF) + { + Elf32_Addr addr = 0; + + if ((ELF_ST_TYPE(sym->st_info) == STT_SECTION) || + (ELF_ST_TYPE(sym->st_info) == STT_OBJECT)) + { + if (rt_strncmp((const char *)(shstrab + + shdr[sym->st_shndx].sh_name), ELF_RODATA, 8) == 0) + { + /* relocate rodata section */ + LOG_D("rodata"); + addr = (Elf32_Addr)(rodata_addr + sym->st_value); + } + else if (rt_strncmp((const char *) + (shstrab + shdr[sym->st_shndx].sh_name), ELF_BSS, 5) == 0) + { + /* relocate bss section */ + LOG_D("bss"); + addr = (Elf32_Addr)bss_addr + sym->st_value; + } + else if (rt_strncmp((const char *)(shstrab + shdr[sym->st_shndx].sh_name), + ELF_DATA, 6) == 0) + { + /* relocate data section */ + LOG_D("data"); + addr = (Elf32_Addr)data_addr + sym->st_value; + } + + if (addr != 0) dlmodule_relocate(module, rel, addr); + } + else if (ELF_ST_TYPE(sym->st_info) == STT_FUNC) + { + addr = (Elf32_Addr)((rt_uint8_t *) module->mem_space - module_addr + sym->st_value); + + /* relocate function */ + dlmodule_relocate(module, rel, addr); + } + } + else if (ELF_ST_TYPE(sym->st_info) == STT_FUNC) + { + /* relocate function */ + dlmodule_relocate(module, rel, + (Elf32_Addr)((rt_uint8_t *) + module->mem_space + - module_addr + + sym->st_value)); + } + else + { + Elf32_Addr addr; + + if (ELF32_R_TYPE(rel->r_info) != R_ARM_V4BX) + { + LOG_D("relocate symbol: %s", strtab + sym->st_name); + + /* need to resolve symbol in kernel symbol table */ + addr = dlmodule_symbol_find((const char *)(strtab + sym->st_name)); + if (addr != (Elf32_Addr)RT_NULL) + { + dlmodule_relocate(module, rel, addr); + LOG_D("symbol addr 0x%x", addr); + } + else + LOG_E("Module: can't find %s in kernel symbol table", + strtab + sym->st_name); + } + else + { + addr = (Elf32_Addr)((rt_uint8_t *) module->mem_space - module_addr + sym->st_value); + dlmodule_relocate(module, rel, addr); + } + } + + rel ++; + } + } + + return RT_EOK; +} diff --git a/src/module.h b/components/libc/libdl/dlelf.h similarity index 89% rename from src/module.h rename to components/libc/libdl/dlelf.h index 90d4dc9524..014ebe85c8 100644 --- a/src/module.h +++ b/components/libc/libdl/dlelf.h @@ -1,32 +1,15 @@ /* - * File : module.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Copyright (c) 2006-2018, RT-Thread Development Team * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: - * Date Author Notes - * 2010-01-09 Bernard first version - * 2010-04-09 yi.qiu implement based on first version + * Date Author Notes + * 2018/08/29 Bernard first version */ -#ifndef __MODULE_H__ -#define __MODULE_H__ - -#include +#ifndef DL_ELF_H__ +#define DL_ELF_H__ typedef rt_uint8_t Elf_Byte; @@ -209,11 +192,19 @@ typedef struct #define R_ARM_V4BX 40 /* - * Relocation type for arm + * Relocation type for x86 */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 #define R_386_GLOB_DAT 6 -#define R_386_JUMP_SLOT 7 +#define R_386_JMP_SLOT 7 #define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 /* Program Header */ typedef struct @@ -274,4 +265,21 @@ typedef struct #define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */ /* specific section attributes */ +#define IS_PROG(s) (s.sh_type == SHT_PROGBITS) +#define IS_NOPROG(s) (s.sh_type == SHT_NOBITS) +#define IS_REL(s) (s.sh_type == SHT_REL) +#define IS_RELA(s) (s.sh_type == SHT_RELA) +#define IS_ALLOC(s) (s.sh_flags == SHF_ALLOC) +#define IS_AX(s) ((s.sh_flags & SHF_ALLOC) && (s.sh_flags & SHF_EXECINSTR)) +#define IS_AW(s) ((s.sh_flags & SHF_ALLOC) && (s.sh_flags & SHF_WRITE)) + +#define elf_module ((Elf32_Ehdr *)module_ptr) +#define shdr ((Elf32_Shdr *)((rt_uint8_t *)module_ptr + elf_module->e_shoff)) +#define phdr ((Elf32_Phdr *)((rt_uint8_t *)module_ptr + elf_module->e_phoff)) + +rt_err_t dlmodule_load_shared_object(struct rt_dlmodule* module, void *module_ptr); +rt_err_t dlmodule_load_relocated_object(struct rt_dlmodule* module, void *module_ptr); + +int dlmodule_relocate(struct rt_dlmodule *module, Elf32_Rel *rel, Elf32_Addr sym_val); + #endif diff --git a/components/libc/libdl/dlerror.c b/components/libc/libdl/dlerror.c index dd076412fe..ad9b630e4c 100644 --- a/components/libc/libdl/dlerror.c +++ b/components/libc/libdl/dlerror.c @@ -1,15 +1,11 @@ /* - * File : dlerror.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * Copyright (c) 2006-2018, RT-Thread Development Team * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: - * Date Author Notes - * 2010-11-17 yi.qiu first version + * Date Author Notes + * 2010-11-17 yi.qiu first version */ #include @@ -19,6 +15,4 @@ const char *dlerror(void) { return "TODO"; } - RTM_EXPORT(dlerror) - diff --git a/components/libc/libdl/dlfcn.h b/components/libc/libdl/dlfcn.h index 304ba5a777..55273a41eb 100644 --- a/components/libc/libdl/dlfcn.h +++ b/components/libc/libdl/dlfcn.h @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-11-17 yi.qiu first version + */ + #ifndef __DLFCN_H_ #define __DLFCN_H_ @@ -16,4 +26,3 @@ void *dlsym(void *handle, const char *symbol); int dlclose (void *handle); #endif - diff --git a/components/libc/libdl/dlmodule.c b/components/libc/libdl/dlmodule.c new file mode 100644 index 0000000000..61ffbfc772 --- /dev/null +++ b/components/libc/libdl/dlmodule.c @@ -0,0 +1,699 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/08/29 Bernard first version + */ + +#include + +#include "dlfcn.h" +#include "dlmodule.h" +#include "dlelf.h" + +#include + +#define DBG_SECTION_NAME "DLMD" +#define DBG_ENABLE // enable debug macro +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include // must after of DEBUG_ENABLE or some other options + +static struct rt_module_symtab *_rt_module_symtab_begin = RT_NULL; +static struct rt_module_symtab *_rt_module_symtab_end = RT_NULL; + +#if defined(__IAR_SYSTEMS_ICC__) /* for IAR compiler */ + #pragma section="RTMSymTab" +#endif + +/* set the name of module */ +static void _dlmodule_set_name(struct rt_dlmodule *module, const char *path) +{ + int size; + struct rt_object *object; + const char *first, *end, *ptr; + + object = &(module->parent); + ptr = first = (char *)path; + end = path + rt_strlen(path); + + while (*ptr != '\0') + { + if (*ptr == '/') + first = ptr + 1; + if (*ptr == '.') + end = ptr - 1; + + ptr ++; + } + + size = end - first + 1; + if (size > RT_NAME_MAX) size = RT_NAME_MAX; + + rt_strncpy(object->name, first, size); + object->name[size] = '\0'; +} + +#define RT_MODULE_ARG_MAX 8 +static int _rt_module_split_arg(char *cmd, rt_size_t length, char *argv[]) +{ + int argc = 0; + char *ptr = cmd; + + while ((ptr - cmd) < length) + { + /* strip bank and tab */ + while ((*ptr == ' ' || *ptr == '\t') && (ptr - cmd) < length) + *ptr++ = '\0'; + /* check whether it's the end of line */ + if ((ptr - cmd) >= length) break; + + /* handle string with quote */ + if (*ptr == '"') + { + argv[argc++] = ++ptr; + + /* skip this string */ + while (*ptr != '"' && (ptr - cmd) < length) + if (*ptr ++ == '\\') ptr ++; + if ((ptr - cmd) >= length) break; + + /* skip '"' */ + *ptr ++ = '\0'; + } + else + { + argv[argc++] = ptr; + while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length) + ptr ++; + } + + if (argc >= RT_MODULE_ARG_MAX) break; + } + + return argc; +} + +/* invoked by main thread for exit */ +static void _dlmodule_exit(void) +{ + struct rt_dlmodule *module; + + module = dlmodule_self(); + if (!module) return; /* not a module thread */ + + rt_enter_critical(); + if (module->stat == RT_DLMODULE_STAT_RUNNING) + { + struct rt_object *object = RT_NULL; + struct rt_list_node *node = RT_NULL; + + /* set stat to closing */ + module->stat = RT_DLMODULE_STAT_CLOSING; + + /* suspend all threads in this module */ + for (node = module->object_list.next; node != &(module->object_list); node = node->next) + { + object = rt_list_entry(node, struct rt_object, list); + + if ((object->type & ~RT_Object_Class_Static) == RT_Object_Class_Thread) + { + rt_thread_t thread = (rt_thread_t)object; + + /* stop timer and suspend thread*/ + if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_CLOSE || + (thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT) + { + rt_timer_stop(&(thread->thread_timer)); + rt_thread_suspend(thread); + } + } + } + } + rt_exit_critical(); + + return; +} + +static void _dlmodule_thread_entry(void* parameter) +{ + int argc = 0; + char *argv[RT_MODULE_ARG_MAX]; + + struct rt_dlmodule *module = (struct rt_dlmodule*)parameter; + + if (module == RT_NULL || module->cmd_line == RT_NULL) + /* malloc for module_cmd_line failed. */ + return; + + if (module->cmd_line) + { + rt_memset(argv, 0x00, sizeof(argv)); + argc = _rt_module_split_arg((char *)module->cmd_line, rt_strlen(module->cmd_line), argv); + if (argc == 0) goto __exit; + } + + /* set status of module */ + module->stat = RT_DLMODULE_STAT_RUNNING; + + LOG_D("run main entry: 0x%p with %s", + module->entry_addr, + module->cmd_line); + + if (module->entry_addr) + module->entry_addr(argc, argv); + +__exit: + _dlmodule_exit(); + + return ; +} + +struct rt_dlmodule *dlmodule_create(void) +{ + struct rt_dlmodule *module = RT_NULL; + + module = (struct rt_dlmodule*) rt_object_allocate(RT_Object_Class_Module, "module"); + if (module) + { + module->stat = RT_DLMODULE_STAT_INIT; + + /* set initial priority and stack size */ + module->priority = RT_THREAD_PRIORITY_MAX - 1; + module->stack_size = 2048; + + rt_list_init(&(module->object_list)); + } + + return module; +} + +void dlmodule_destroy_subthread(struct rt_dlmodule *module, rt_thread_t thread) +{ + RT_ASSERT(thread->module_id == module); + + /* lock scheduler to prevent scheduling in cleanup function. */ + rt_enter_critical(); + + /* remove thread from thread_list (ready or defunct thread list) */ + rt_list_remove(&(thread->tlist)); + + if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_CLOSE && + (thread->thread_timer.parent.type == (RT_Object_Class_Static | RT_Object_Class_Timer))) + { + /* release thread timer */ + rt_timer_detach(&(thread->thread_timer)); + } + + /* change stat */ + thread->stat = RT_THREAD_CLOSE; + + /* invoke thread cleanup */ + if (thread->cleanup != RT_NULL) + thread->cleanup(thread); + + rt_exit_critical(); + +#ifdef RT_USING_SIGNALS + rt_thread_free_sig(thread); +#endif + + if (thread->type & RT_Object_Class_Static) + { + /* detach object */ + rt_object_detach((rt_object_t)thread); + } +#ifdef RT_USING_HEAP + else + { + /* release thread's stack */ + RT_KERNEL_FREE(thread->stack_addr); + /* delete thread object */ + rt_object_delete((rt_object_t)thread); + } +#endif +} + +rt_err_t dlmodule_destroy(struct rt_dlmodule* module) +{ + int i; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* check parameter */ + if (module == RT_NULL) + return -RT_ERROR; + + /* can not destroy a running module */ + if (module->stat == RT_DLMODULE_STAT_RUNNING) + return -RT_EBUSY; + + /* do module cleanup */ + if (module->cleanup_func) + { + rt_enter_critical(); + module->cleanup_func(module); + rt_exit_critical(); + } + + // list_object(&(module->object_list)); + + /* cleanup for all kernel objects inside module*/ + { + struct rt_object *object = RT_NULL; + struct rt_list_node *node = RT_NULL; + + /* detach/delete all threads in this module */ + for (node = module->object_list.next; node != &(module->object_list); ) + { + int object_type; + + object = rt_list_entry(node, struct rt_object, list); + object_type = object->type & ~RT_Object_Class_Static; + + /* to next node */ + node = node->next; + + if (object->type & RT_Object_Class_Static) + { + switch (object_type) + { + case RT_Object_Class_Thread: + dlmodule_destroy_subthread(module, (rt_thread_t)object); + break; +#ifdef RT_USING_SEMAPHORE + case RT_Object_Class_Semaphore: + rt_sem_detach((rt_sem_t)object); + break; +#endif +#ifdef RT_USING_MUTEX + case RT_Object_Class_Mutex: + rt_mutex_detach((rt_mutex_t)object); + break; +#endif +#ifdef RT_USING_EVENT + case RT_Object_Class_Event: + rt_event_detach((rt_event_t)object); + break; +#endif +#ifdef RT_USING_MAILBOX + case RT_Object_Class_MailBox: + rt_mb_detach((rt_mailbox_t)object); + break; +#endif +#ifdef RT_USING_MESSAGEQUEUE + case RT_Object_Class_MessageQueue: + rt_mq_detach((rt_mq_t)object); + break; +#endif +#ifdef RT_USING_MEMHEAP + case RT_Object_Class_MemHeap: + rt_memheap_detach((struct rt_memheap*)object); + break; +#endif +#ifdef RT_USING_MEMPOOL + case RT_Object_Class_MemPool: + rt_mp_detach((struct rt_mempool*)object); + break; +#endif + case RT_Object_Class_Timer: + rt_timer_detach((rt_timer_t)object); + break; + default: + LOG_E("Unsupported oject type in module."); + break; + } + } + else + { + switch (object_type) + { + case RT_Object_Class_Thread: + dlmodule_destroy_subthread(module, (rt_thread_t)object); + break; +#ifdef RT_USING_SEMAPHORE + case RT_Object_Class_Semaphore: + rt_sem_delete((rt_sem_t)object); + break; +#endif +#ifdef RT_USING_MUTEX + case RT_Object_Class_Mutex: + rt_mutex_delete((rt_mutex_t)object); + break; +#endif +#ifdef RT_USING_EVENT + case RT_Object_Class_Event: + rt_event_delete((rt_event_t)object); + break; +#endif +#ifdef RT_USING_MAILBOX + case RT_Object_Class_MailBox: + rt_mb_delete((rt_mailbox_t)object); + break; +#endif +#ifdef RT_USING_MESSAGEQUEUE + case RT_Object_Class_MessageQueue: + rt_mq_delete((rt_mq_t)object); + break; +#endif +#ifdef RT_USING_MEMHEAP + /* no delete operation */ +#endif +#ifdef RT_USING_MEMPOOL + case RT_Object_Class_MemPool: + rt_mp_delete((struct rt_mempool*)object); + break; +#endif + case RT_Object_Class_Timer: + rt_timer_delete((rt_timer_t)object); + break; + default: + LOG_E("Unsupported oject type in module."); + break; + } + } + } + } + + if (module->cmd_line) rt_free(module->cmd_line); + /* release module symbol table */ + for (i = 0; i < module->nsym; i ++) + { + rt_free((void *)module->symtab[i].name); + } + if (module->symtab != RT_NULL) + { + rt_free(module->symtab); + } + + /* destory module */ + rt_free(module->mem_space); + /* delete module object */ + rt_object_delete((rt_object_t)module); + + return RT_EOK; +} + +struct rt_dlmodule *dlmodule_self(void) +{ + rt_thread_t tid; + struct rt_dlmodule *ret = RT_NULL; + + tid = rt_thread_self(); + if (tid) + { + ret = (struct rt_dlmodule*) tid->module_id; + } + + return ret; +} + +/* + * Compatible with old API + */ +struct rt_dlmodule *rt_module_self(void) +{ + return dlmodule_self(); +} + +struct rt_dlmodule* dlmodule_load(const char* filename) +{ + int fd, length = 0; + rt_err_t ret = RT_EOK; + rt_uint8_t *module_ptr = RT_NULL; + struct rt_dlmodule *module = RT_NULL; + + fd = open(filename, O_RDONLY, 0); + if (fd >= 0) + { + length = lseek(fd, 0, SEEK_END); + lseek(fd, 0, SEEK_SET); + + if (length == 0) goto __exit; + + module_ptr = (uint8_t*) rt_malloc (length); + if (!module_ptr) goto __exit; + + if (read(fd, module_ptr, length) != length) + goto __exit; + + /* close file and release fd */ + close(fd); + fd = -1; + } + + /* check ELF header */ + if (rt_memcmp(elf_module->e_ident, RTMMAG, SELFMAG) != 0 && + rt_memcmp(elf_module->e_ident, ELFMAG, SELFMAG) != 0) + { + rt_kprintf("Module: magic error\n"); + goto __exit; + } + + /* check ELF class */ + if (elf_module->e_ident[EI_CLASS] != ELFCLASS32) + { + rt_kprintf("Module: ELF class error\n"); + goto __exit; + } + + module = dlmodule_create(); + if (!module) goto __exit; + + /* set the name of module */ + _dlmodule_set_name(module, filename); + + LOG_D("rt_module_load: %.*s", RT_NAME_MAX, module->parent.name); + + if (elf_module->e_type == ET_REL) + { + ret = dlmodule_load_relocated_object(module, module_ptr); + } + else if (elf_module->e_type == ET_DYN) + { + ret = dlmodule_load_shared_object(module, module_ptr); + } + else + { + rt_kprintf("Module: unsupported elf type\n"); + goto __exit; + } + + /* check return value */ + if (ret != RT_EOK) goto __exit; + + /* release module data */ + rt_free(module_ptr); + + /* increase module reference count */ + module->nref ++; + + /* deal with cache */ +#ifdef RT_USING_CACHE + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, module->mem_space, module->mem_size); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, module->mem_space, module->mem_size); +#endif + + /* set module initialization and cleanup function */ + module->init_func = dlsym(module, "module_init"); + module->cleanup_func = dlsym(module, "module_cleanup"); + module->stat = RT_DLMODULE_STAT_INIT; + /* do module initialization */ + if (module->init_func) + { + module->init_func(module); + } + + return module; + +__exit: + if (fd >= 0) close(fd); + if (module_ptr) rt_free(module_ptr); + if (module) dlmodule_destroy(module); + + return RT_NULL; +} + +struct rt_dlmodule* dlmodule_exec(const char* pgname, const char* cmd, int cmd_size) +{ + struct rt_dlmodule *module = RT_NULL; + + module = dlmodule_load(pgname); + if (module) + { + if (module->entry_addr) + { + /* exec this module */ + rt_thread_t tid; + + module->cmd_line = rt_strdup(cmd); + + /* check stack size and priority */ + if (module->priority > RT_THREAD_PRIORITY_MAX) module->priority = RT_THREAD_PRIORITY_MAX - 1; + if (module->stack_size < 2048 || module->stack_size > (1024 * 32)) module->stack_size = 2048; + + tid = rt_thread_create(module->parent.name, _dlmodule_thread_entry, (void*)module, + module->stack_size, module->priority, 10); + if (tid) + { + tid->module_id = module; + module->main_thread = tid; + + rt_thread_startup(tid); + } + else + { + /* destory dl module */ + dlmodule_destroy(module); + module = RT_NULL; + } + } + } + + return module; +} + +void dlmodule_exit(int ret_code) +{ + rt_thread_t thread; + struct rt_dlmodule *module; + + module = dlmodule_self(); + if (!module) return; + + /* disable scheduling */ + rt_enter_critical(); + + /* module is not running */ + if (module->stat != RT_DLMODULE_STAT_RUNNING) + { + /* restore scheduling */ + rt_exit_critical(); + + return; + } + + /* set return code */ + module->ret_code = ret_code; + + /* do exit for this module */ + _dlmodule_exit(); + /* the stat of module was changed to CLOSING in _dlmodule_exit */ + + thread = module->main_thread; + if ((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_CLOSE) + { + /* main thread already closed */ + rt_exit_critical(); + + return ; + } + + /* delete thread: insert to defunct thread list */ + rt_thread_delete(thread); + /* enable scheduling */ + rt_exit_critical(); +} + +rt_uint32_t dlmodule_symbol_find(const char *sym_str) +{ + /* find in kernel symbol table */ + struct rt_module_symtab *index; + + for (index = _rt_module_symtab_begin; index != _rt_module_symtab_end; index ++) + { + if (rt_strcmp(index->name, sym_str) == 0) + return (rt_uint32_t)index->addr; + } + + return 0; +} + +int rt_system_dlmodule_init(void) +{ +#if defined(__GNUC__) && !defined(__CC_ARM) + extern int __rtmsymtab_start; + extern int __rtmsymtab_end; + + _rt_module_symtab_begin = (struct rt_module_symtab *)&__rtmsymtab_start; + _rt_module_symtab_end = (struct rt_module_symtab *)&__rtmsymtab_end; +#elif defined (__CC_ARM) + extern int RTMSymTab$$Base; + extern int RTMSymTab$$Limit; + + _rt_module_symtab_begin = (struct rt_module_symtab *)&RTMSymTab$$Base; + _rt_module_symtab_end = (struct rt_module_symtab *)&RTMSymTab$$Limit; +#elif defined (__IAR_SYSTEMS_ICC__) + _rt_module_symtab_begin = __section_begin("RTMSymTab"); + _rt_module_symtab_end = __section_end("RTMSymTab"); +#endif + + return 0; +} +INIT_COMPONENT_EXPORT(rt_system_dlmodule_init); + +/** + * This function will find the specified module. + * + * @param name the name of module finding + * + * @return the module + */ +struct rt_dlmodule *dlmodule_find(const char *name) +{ + rt_object_t object; + struct rt_dlmodule *ret = RT_NULL; + + object = rt_object_find(name, RT_Object_Class_Module); + if (object) + { + ret = (struct rt_dlmodule*) object; + } + + return ret; +} +RTM_EXPORT(dlmodule_find); + +int list_symbols(void) +{ + extern int __rtmsymtab_start; + extern int __rtmsymtab_end; + + /* find in kernel symbol table */ + struct rt_module_symtab *index; + + for (index = _rt_module_symtab_begin; + index != _rt_module_symtab_end; + index ++) + { + rt_kprintf("%s => 0x%08x\n", index->name, index->addr); + } + + return 0; +} +MSH_CMD_EXPORT(list_symbols, list symbols information); + +int list_module(void) +{ + struct rt_dlmodule *module; + struct rt_list_node *list, *node; + struct rt_object_information *info; + + info = rt_object_get_information(RT_Object_Class_Module); + list = &info->object_list; + + rt_kprintf("module ref address \n"); + rt_kprintf("-------- -------- ------------\n"); + for (node = list->next; node != list; node = node->next) + { + module = (struct rt_dlmodule *)(rt_list_entry(node, struct rt_object, list)); + rt_kprintf("%-*.*s %-04d 0x%08x\n", + RT_NAME_MAX, RT_NAME_MAX, module->parent.name, module->nref, module->mem_space); + } + + return 0; +} +MSH_CMD_EXPORT(list_module, list modules in system); diff --git a/components/libc/libdl/dlmodule.h b/components/libc/libdl/dlmodule.h new file mode 100644 index 0000000000..4a4ead3303 --- /dev/null +++ b/components/libc/libdl/dlmodule.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/08/11 Bernard the first version + */ + +#ifndef RT_DL_MODULE_H__ +#define RT_DL_MODULE_H__ + +#include + +#define RT_DLMODULE_STAT_INIT 0x00 +#define RT_DLMODULE_STAT_RUNNING 0x01 +#define RT_DLMODULE_STAT_CLOSING 0x02 +#define RT_DLMODULE_STAT_CLOSED 0x03 + +struct rt_dlmodule; +typedef void* rt_addr_t; + +typedef void (*rt_dlmodule_init_func_t)(struct rt_dlmodule *module); +typedef void (*rt_dlmodule_cleanup_func_t)(struct rt_dlmodule *module); +typedef int (*rt_dlmodule_entry_func_t)(int argc, char** argv); + +struct rt_dlmodule +{ + struct rt_object parent; + rt_list_t object_list; /* objects inside this module */ + + rt_uint8_t stat; /* status of module */ + + /* main thread of this module */ + rt_uint16_t priority; + rt_uint32_t stack_size; + struct rt_thread *main_thread; + /* the return code */ + int ret_code; + + /* VMA base address for the first LOAD segment */ + rt_uint32_t vstart_addr; + + /* module entry, RT_NULL for dynamic library */ + rt_dlmodule_entry_func_t entry_addr; + char *cmd_line; /* command line */ + + rt_addr_t mem_space; /* memory space */ + rt_uint32_t mem_size; /* sizeof memory space */ + + /* init and clean function */ + rt_dlmodule_init_func_t init_func; + rt_dlmodule_cleanup_func_t cleanup_func; + + rt_uint16_t nref; /* reference count */ + + rt_uint16_t nsym; /* number of symbols in the module */ + struct rt_module_symtab *symtab; /* module symbol table */ +}; + +struct rt_dlmodule *dlmodule_create(void); +rt_err_t dlmodule_destroy(struct rt_dlmodule* module); + +struct rt_dlmodule *dlmodule_self(void); + +struct rt_dlmodule *dlmodule_load(const char* pgname); +struct rt_dlmodule *dlmodule_exec(const char* pgname, const char* cmd, int cmd_size); +void dlmodule_exit(int ret_code); + +struct rt_dlmodule *dlmodule_find(const char *name); + +rt_uint32_t dlmodule_symbol_find(const char *sym_str); + +#endif diff --git a/components/libc/libdl/dlopen.c b/components/libc/libdl/dlopen.c index 6c89cb03c0..a8202ec607 100644 --- a/components/libc/libdl/dlopen.c +++ b/components/libc/libdl/dlopen.c @@ -1,11 +1,7 @@ /* - * File : dlopen.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,11 +12,13 @@ #include #include +#include "dlmodule.h" + #define MODULE_ROOT_DIR "/modules" void* dlopen(const char *filename, int flags) { - rt_module_t module; + struct rt_dlmodule *module; char *fullpath; const char*def_path = MODULE_ROOT_DIR; @@ -40,11 +38,21 @@ void* dlopen(const char *filename, int flags) fullpath = (char*)filename; /* absolute path, use it directly */ } - /* find in module list */ - module = rt_module_find(fullpath); + rt_enter_critical(); - if(module != RT_NULL) module->nref++; - else module = rt_module_open(fullpath); + /* find in module list */ + module = dlmodule_find(fullpath); + + if(module != RT_NULL) + { + rt_exit_critical(); + module->nref++; + } + else + { + rt_exit_critical(); + module = dlmodule_load(fullpath); + } if(fullpath != filename) { @@ -54,4 +62,3 @@ void* dlopen(const char *filename, int flags) return (void*)module; } RTM_EXPORT(dlopen); - diff --git a/components/libc/libdl/dlsym.c b/components/libc/libdl/dlsym.c index 36c7b01fce..ed0f183d83 100644 --- a/components/libc/libdl/dlsym.c +++ b/components/libc/libdl/dlsym.c @@ -1,37 +1,33 @@ /* - * File : dlsym.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-17 yi.qiu first version + * Date Author Notes + * 2010-11-17 yi.qiu first version */ #include #include +#include "dlmodule.h" + void* dlsym(void *handle, const char* symbol) { - int i; - rt_module_t module; - - RT_ASSERT(handle != RT_NULL); + int i; + struct rt_dlmodule *module; + + RT_ASSERT(handle != RT_NULL); - module = (rt_module_t)handle; + module = (struct rt_dlmodule *)handle; - for(i=0; insym; i++) - { - if (rt_strcmp(module->symtab[i].name, symbol) == 0) - return (void*)module->symtab[i].addr; - } + for(i=0; insym; i++) + { + if (rt_strcmp(module->symtab[i].name, symbol) == 0) + return (void*)module->symtab[i].addr; + } - return RT_NULL; + return RT_NULL; } - RTM_EXPORT(dlsym) - diff --git a/components/libc/mmap/posix_mmap.c b/components/libc/mmap/posix_mmap.c index 8e70678c25..3d405aad77 100644 --- a/components/libc/mmap/posix_mmap.c +++ b/components/libc/mmap/posix_mmap.c @@ -1,21 +1,7 @@ /* - * File : posix_mmap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/mqueue.c b/components/libc/pthreads/mqueue.c index 7b669dc367..003b49b9a0 100644 --- a/components/libc/pthreads/mqueue.c +++ b/components/libc/pthreads/mqueue.c @@ -1,21 +1,7 @@ /* - * File : mqueue.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/mqueue.h b/components/libc/pthreads/mqueue.h index de2925837f..5cadde3ae8 100644 --- a/components/libc/pthreads/mqueue.h +++ b/components/libc/pthreads/mqueue.h @@ -1,21 +1,7 @@ /* - * File : mqueue.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/posix_types.h b/components/libc/pthreads/posix_types.h index 1e401e2de3..ca20464bb5 100644 --- a/components/libc/pthreads/posix_types.h +++ b/components/libc/pthreads/posix_types.h @@ -1,21 +1,7 @@ /* - * File : posix_types.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread.c b/components/libc/pthreads/pthread.c index 103b5de33d..62c110499d 100644 --- a/components/libc/pthreads/pthread.c +++ b/components/libc/pthreads/pthread.c @@ -1,21 +1,7 @@ /* - * File : pthread.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread.h b/components/libc/pthreads/pthread.h index b60aa37471..6a82375de4 100644 --- a/components/libc/pthreads/pthread.h +++ b/components/libc/pthreads/pthread.h @@ -1,21 +1,7 @@ /* - * File : pthread.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_attr.c b/components/libc/pthreads/pthread_attr.c index 3e0f7b1e4c..8eed35932f 100644 --- a/components/libc/pthreads/pthread_attr.c +++ b/components/libc/pthreads/pthread_attr.c @@ -1,21 +1,7 @@ /* - * File : pthread_attr.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_barrier.c b/components/libc/pthreads/pthread_barrier.c index c39a45586e..d76fe7f13f 100644 --- a/components/libc/pthreads/pthread_barrier.c +++ b/components/libc/pthreads/pthread_barrier.c @@ -1,21 +1,7 @@ /* - * File : pthread_barrier.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_cond.c b/components/libc/pthreads/pthread_cond.c index 1a4217310e..d3c4ac7637 100644 --- a/components/libc/pthreads/pthread_cond.c +++ b/components/libc/pthreads/pthread_cond.c @@ -1,21 +1,7 @@ /* - * File : pthread_cond.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_internal.h b/components/libc/pthreads/pthread_internal.h index ce7fb256a5..3e94e867d7 100644 --- a/components/libc/pthreads/pthread_internal.h +++ b/components/libc/pthreads/pthread_internal.h @@ -1,21 +1,7 @@ /* - * File : pthread_internal.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_mutex.c b/components/libc/pthreads/pthread_mutex.c index c7c3d38c4f..8f96531782 100644 --- a/components/libc/pthreads/pthread_mutex.c +++ b/components/libc/pthreads/pthread_mutex.c @@ -1,21 +1,7 @@ /* - * File : pthread_mutex.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_rwlock.c b/components/libc/pthreads/pthread_rwlock.c index 3e009034cc..64a0e221b4 100644 --- a/components/libc/pthreads/pthread_rwlock.c +++ b/components/libc/pthreads/pthread_rwlock.c @@ -1,21 +1,7 @@ /* - * File : pthread_rwlock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_spin.c b/components/libc/pthreads/pthread_spin.c index 4c4320dda9..b31f4f6393 100644 --- a/components/libc/pthreads/pthread_spin.c +++ b/components/libc/pthreads/pthread_spin.c @@ -1,21 +1,7 @@ /* - * File : pthread_spin.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/pthread_tls.c b/components/libc/pthreads/pthread_tls.c index d689f31e47..c6d0bca155 100644 --- a/components/libc/pthreads/pthread_tls.c +++ b/components/libc/pthreads/pthread_tls.c @@ -1,21 +1,7 @@ /* - * File : pthread_tls.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/sched.c b/components/libc/pthreads/sched.c index 6f75127bf2..a1bf50985e 100644 --- a/components/libc/pthreads/sched.c +++ b/components/libc/pthreads/sched.c @@ -1,21 +1,7 @@ /* - * File : sched.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/sched.h b/components/libc/pthreads/sched.h index f0fa17bfa1..dbaf66edc2 100644 --- a/components/libc/pthreads/sched.h +++ b/components/libc/pthreads/sched.h @@ -1,21 +1,7 @@ /* - * File : sched.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/semaphore.c b/components/libc/pthreads/semaphore.c index ea6701b1e0..2bef10022e 100644 --- a/components/libc/pthreads/semaphore.c +++ b/components/libc/pthreads/semaphore.c @@ -1,21 +1,7 @@ /* - * File : semaphore.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/pthreads/semaphore.h b/components/libc/pthreads/semaphore.h index 664c15ee2e..d135ae9261 100644 --- a/components/libc/pthreads/semaphore.h +++ b/components/libc/pthreads/semaphore.h @@ -1,21 +1,7 @@ /* - * File : semaphore.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/signal/posix_signal.c b/components/libc/signal/posix_signal.c index b950fc956c..c0dd90e637 100644 --- a/components/libc/signal/posix_signal.c +++ b/components/libc/signal/posix_signal.c @@ -1,21 +1,7 @@ /* - * File : signal.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/signal/posix_signal.h b/components/libc/signal/posix_signal.h index 5ec721c921..896d6b6da4 100644 --- a/components/libc/signal/posix_signal.h +++ b/components/libc/signal/posix_signal.h @@ -1,21 +1,7 @@ /* - * File : signals.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/termios/posix_termios.c b/components/libc/termios/posix_termios.c index 4f7417cb27..75c876dd33 100644 --- a/components/libc/termios/posix_termios.c +++ b/components/libc/termios/posix_termios.c @@ -1,21 +1,7 @@ /* - * File : termios.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/termios/posix_termios.h b/components/libc/termios/posix_termios.h index b5bd1d50f4..4f556d79d9 100644 --- a/components/libc/termios/posix_termios.h +++ b/components/libc/termios/posix_termios.h @@ -1,21 +1,7 @@ /* - * File : termios.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/time/clock_time.c b/components/libc/time/clock_time.c index 3d3cc9aed3..83b3b916ca 100644 --- a/components/libc/time/clock_time.c +++ b/components/libc/time/clock_time.c @@ -1,21 +1,7 @@ /* - * File : clock_time.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/time/clock_time.h b/components/libc/time/clock_time.h index e91e6c97fa..7feb0390a4 100644 --- a/components/libc/time/clock_time.h +++ b/components/libc/time/clock_time.h @@ -1,21 +1,7 @@ /* - * File : clock_time.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/libc/time/posix_sleep.c b/components/libc/time/posix_sleep.c index b4b33722ac..f21b0a7994 100644 --- a/components/libc/time/posix_sleep.c +++ b/components/libc/time/posix_sleep.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig deleted file mode 100644 index e3f13a3b6d..0000000000 --- a/components/lwp/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -config RT_USING_LWP - bool "Using light-weight process" - select RT_USING_DFS - depends on ARCH_ARM_CORTEX_M - default n - help - The lwP is a light weight process running in user mode. diff --git a/components/lwp/SConscript b/components/lwp/SConscript deleted file mode 100644 index f54d9422e1..0000000000 --- a/components/lwp/SConscript +++ /dev/null @@ -1,20 +0,0 @@ -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = [] -CPPPATH = [] - -support_arch = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7"]} -platform_file = {'armcc': 'rvds.S', 'gcc': 'gcc.S', 'iar': 'iar.S'} - -if rtconfig.PLATFORM in platform_file.keys(): # support platforms - if rtconfig.ARCH in support_arch.keys() and rtconfig.CPU in support_arch[rtconfig.ARCH]: - # arch/arm/cortex-m7/lwp_gcc.S - asm_path = 'arch/' + rtconfig.ARCH + '/' + rtconfig.CPU + '/*_' + platform_file[rtconfig.PLATFORM] - src = Glob('*.c') + Glob(asm_path) - CPPPATH = [cwd] - -group = DefineGroup('lwP', src, depend = ['RT_USING_LWP'], CPPPATH = CPPPATH) - -Return('group') diff --git a/components/lwp/arch/arm/cortex-m3/lwp_gcc.S b/components/lwp/arch/arm/cortex-m3/lwp_gcc.S deleted file mode 100644 index 8c866f9990..0000000000 --- a/components/lwp/arch/arm/cortex-m3/lwp_gcc.S +++ /dev/null @@ -1,176 +0,0 @@ -/* - * File : lwp_gcc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -.cpu cortex-m3 -.syntax unified -.thumb -.text - -/* - * void* lwp_get_sys_api(rt_uint32_t number); - */ -.global lwp_get_sys_api -.global lwp_get_kernel_sp -.global lwp_set_kernel_sp - - -/* - * void lwp_user_entry(u32 R0_text_addr, u32 R1_data_addr); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - PUSH {R0 - R1} /* push text&data addr. */ - - MOV R0, SP /* v1 = SP */ - BL lwp_set_kernel_sp /* lwp_set_kernel_sp(v1) */ - - POP {R0 - R1} /* pop app address to R1. */ - - /* set CPU to user-thread mode. */ - MRS R2, CONTROL - ORR R2, R2, #0x03 /* use PSP, user-thread mode. */ - MSR CONTROL, R2 - - /* set data address. */ - MOV R9, R1 - - /* run app, only Thumb-mode. */ - ORR R0, R0, #0x01 - BX R0 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - - PUSH {LR} - - /* get user SP. */ - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} /* push app SP. */ - MOV R2, R1 - - STMFD R2!, {R4 - R11} /* push app R4-R11 to app stack , and R1 not change. */ - - /* get SVC number. */ - LDR R0, [R1, #24] /* get the app LR. */ - LDRB R0, [R0, #-2] /* get the SVC No. from instruction. */ - - /* get kernel system API */ - BL lwp_get_sys_api - - /* if(api == NULL) return; */ - CMP R0, #0 - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - /* push api */ - PUSH {R0} - - /* get kernel SP to R0. */ - BL lwp_get_kernel_sp - - POP {R2} /* pop api to R2. */ - POP {R1} /* pop app SP to R1. */ - - /* copy R1(app SP) to R0(server SP). */ - LDMFD R1, {R4 - R11} /* pop exception_stack_frame to r4 - r11 register */ - STMFD R0!, {R4 - R11} /* push exception_stack_frame to server SP. */ - - POP {LR} - PUSH {LR} - - /* save app SP. */ - PUSH {R0 - R3} - SUB R0, R1, #0x20 /* keep {R4 - R11} */ - BL lwp_set_kernel_sp - POP {R0 - R3} - - /* set to thread-privilege mode. */ - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - /* call api. */ - LDR R3, = svc_exit - STR R3, [R0, #20] /* update LR */ - STR R2, [R0, #24] /* update api to PC */ - MSR PSP, R0 /* update stack pointer */ - POP {LR} /* 0xFFFFFFED */ - - ORR LR, LR, #0x10 - - BX LR - -/* -* void svc_exit(void); -*/ -.global svc_exit -.type svc_exit, % function -svc_exit: - - /* get user SP. */ - PUSH {R0} /* push result to SP. */ - BL lwp_get_kernel_sp - - LDMFD R0!, {R4 - R11} /* pop app {R4 - R11} */ - - ADD R0, R0, #16 /* skip R0-R3 */ - LDMFD R0!, {R12, LR} - LDMFD R0!, {R1} /* pop PC to R1 */ - LDMFD R0!, {R2} /* pop PSR to R2 */ - - /* align to 2 words */ - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} /* push user-SP to SP */ - - /* save server SP. */ - ADD R0, SP, #0x08 /* [user-SP, result] */ - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} /* pop user-SP to R3 */ - POP {R0} /* restore API result. */ - - MSR APSR, R2 /* restore PSR */ - MSR PSP, R3 /* restore app stack pointer */ - - /* restore to PSP & thread-unprivilege mode. */ - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - /* return to lwp. */ - ORR R1, R1, #0x01 /* only Thumb-mode. */ - BX R1 /* return to user app. */ diff --git a/components/lwp/arch/arm/cortex-m3/lwp_iar.S b/components/lwp/arch/arm/cortex-m3/lwp_iar.S deleted file mode 100644 index e00424cbec..0000000000 --- a/components/lwp/arch/arm/cortex-m3/lwp_iar.S +++ /dev/null @@ -1,176 +0,0 @@ -;/* -; * File : lwp_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; */ - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(u32 R0_text_addr, u32 R1_data_addr); -; */ - EXPORT lwp_user_entry -lwp_user_entry: - - PUSH {R0-R1} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - POP {R0-R1} ; pop app address to R1. - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - ; set data address. - MOV R9, R1 - - ; run app, only Thumb-mode. - ORR R0, R0, #0x01 - BX R0 - -;/* -; * void SVC_Handler(void); -; */ - EXPORT SVC_Handler -SVC_Handler: - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} ; push app SP. - MOV R2, R1 - - STMFD R2!, {R4 - R11} ; push app R4-R11 to app stack , and R1 not change. - - ; get SVC number. - LDR R0, [R1, #24] ; get the app LR. - LDRB R0, [R0, #-2] ; get the SVC No. from instruction. - - ; get kernel system API - BL lwp_get_sys_api - - ; if(api == NULL) return; - CMP R0, #0 - ITTT EQ - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - ; push api - PUSH {R0} - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - ; copy R1(app SP) to R0(server SP). - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - - POP {LR} - PUSH {LR} - - ; save app SP. - PUSH {R0 - R3} - SUB R0, R1, #0x20 ; keep {R4 - R11} - BL lwp_set_kernel_sp - POP {R0 - R3} - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - ; call api. - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update stack pointer - POP {LR} ; 0xFFFFFFED - - ORR LR, LR, #0x10 - - BX LR - -;/* -; * void svc_exit(void); -; */ - EXPORT svc_exit -svc_exit: - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - - LDMFD R0!, {R4 - R11} ; pop app {R4 - R11} - - ADD R0, R0, #16 ; skip R0-R3 - LDMFD R0!, {R12, LR} ; - LDMFD R0!, {R1} ; pop PC to R1 - LDMFD R0!, {R2} ; pop PSR to R2 - - ; align to 2 words - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} ; push user-SP to SP - - ; save server SP. - ADD R0, SP, #0x08 ; [user-SP, result] - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} ; pop user-SP to R3 - POP {R0} ; restore API result. - - MSR APSR, R2 ; restore PSR - MSR PSP, R3 ; restore app stack pointer - - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - END diff --git a/components/lwp/arch/arm/cortex-m3/lwp_rvds.S b/components/lwp/arch/arm/cortex-m3/lwp_rvds.S deleted file mode 100644 index 49470ea03a..0000000000 --- a/components/lwp/arch/arm/cortex-m3/lwp_rvds.S +++ /dev/null @@ -1,184 +0,0 @@ -;/* -; * File : lwp_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ -lwp_user_entry PROC - EXPORT lwp_user_entry - - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - - ; never reach here! - ENDP - - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} ; push app SP. - MOV R2, R1 - - STMFD R2!, {R4 - R11} ; push app R4-R11 to app stack , and R1 not change. - - ; get SVC number. - LDR R0, [R1, #24] ; get the app LR. - LDRB R0, [R0, #-2] ; get the SVC No. from instruction. - - ; get kernel system API - BL lwp_get_sys_api - - ; if(api == NULL) return; - CMP R0, #0 - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - ; push api - PUSH {R0} - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - ; copy R1(app SP) to R0(server SP). - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - - POP {LR} - PUSH {LR} - - ; save app SP. - PUSH {R0 - R3} - SUB R0, R1, #0x20 ; keep {R4 - R11} - BL lwp_set_kernel_sp - POP {R0 - R3} - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - ; call api. - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update stack pointer - POP {LR} ; 0xFFFFFFED - - ORR LR, LR, #0x10 - - BX LR - - ENDP - -;/* -; * void svc_exit(void); -; */ -svc_exit PROC - EXPORT svc_exit - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - - LDMFD R0!, {R4 - R11} ; pop app {R4 - R11} - - ADD R0, R0, #16 ; skip R0-R3 - LDMFD R0!, {R12, LR} ; - LDMFD R0!, {R1} ; pop PC to R1 - LDMFD R0!, {R2} ; pop PSR to R2 - - ; align to 2 words - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} ; push user-SP to SP - - ; save server SP. - ADD R0, SP, #0x08 ; [user-SP, result] - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} ; pop user-SP to R3 - POP {R0} ; restore API result. - - MSR APSR, R2 ; restore PSR - MSR PSP, R3 ; restore app stack pointer - - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - ENDP - - ALIGN - - END diff --git a/components/lwp/arch/arm/cortex-m4/lwp_gcc.S b/components/lwp/arch/arm/cortex-m4/lwp_gcc.S deleted file mode 100644 index fd46d6142d..0000000000 --- a/components/lwp/arch/arm/cortex-m4/lwp_gcc.S +++ /dev/null @@ -1,210 +0,0 @@ -/* - * File : lwp_gcc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -/* - * void* lwp_get_sys_api(rt_uint32_t number); - */ -.global lwp_get_sys_api -.global lwp_get_kernel_sp -.global lwp_set_kernel_sp - - -/* - * void lwp_user_entry(u32 R0_text_addr, u32 R1_data_addr); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - PUSH {R0 - R1} /* push text&data addr. */ - - MOV R0, SP /* v1 = SP */ - BL lwp_set_kernel_sp /* lwp_set_kernel_sp(v1) */ - - POP {R0 - R1} /* pop app address to R1. */ - - /* set CPU to user-thread mode. */ - MRS R2, CONTROL - ORR R2, R2, #0x03 /* use PSP, user-thread mode. */ - MSR CONTROL, R2 - - /* set data address. */ - MOV R9, R1 - - /* run app, only Thumb-mode. */ - ORR R0, R0, #0x01 - BX R0 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - - PUSH {LR} - - /* get user SP. */ - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} /* push app SP. */ - MOV R2, R1 - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST LR, #0x10 - VSTMDBEQ R2!, {D8 - D15} -#endif - - STMFD R2!, {R4 - R11} /* push app R4-R11 to app stack , and R1 not change. */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - MOV R4, #0x00 /* flag = 0 */ - TST LR, #0x10 /* if(!EXC_RETURN[4]) */ - MOVEQ R4, #0x01 /* flag = 1 */ - STMFD R2!, {R4} /* push flag */ -#endif - - /* get SVC number. */ - LDR R0, [R1, #24] /* get the app LR. */ - LDRB R0, [R0, #-2] /* get the SVC No. from instruction. */ - - /* get kernel system API */ - BL lwp_get_sys_api - - /* if(api == NULL) return; */ - CMP R0, #0 - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - /* push api */ - PUSH {R0} - - /* get kernel SP to R0. */ - BL lwp_get_kernel_sp - - POP {R2} /* pop api to R2. */ - POP {R1} /* pop app SP to R1. */ - - /* copy R1(app SP) to R0(server SP). */ - LDMFD R1, {R4 - R11} /* pop exception_stack_frame to r4 - r11 register */ - STMFD R0!, {R4 - R11} /* push exception_stack_frame to server SP. */ - - POP {LR} - PUSH {LR} - - /* save app SP. */ - PUSH {R0 - R3} -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST LR, #0x10 - SUBEQ R0, R1, #0x64 /* keep {R4 - R11}, {D8-D15}, FLAG */ - SUBNE R0, R1, #0x24 /* keep {R4 - R11}, FLAG */ -#else - SUB R0, R1, #0x20 /* keep {R4 - R11} */ -#endif - BL lwp_set_kernel_sp - POP {R0 - R3} - - /* set to thread-privilege mode. */ - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - /* call api. */ - LDR R3, = svc_exit - STR R3, [R0, #20] /* update LR */ - STR R2, [R0, #24] /* update api to PC */ - MSR PSP, R0 /* update stack pointer */ - POP {LR} /* 0xFFFFFFED */ - - ORR LR, LR, #0x10 - - BX LR - -/* -* void svc_exit(void); -*/ -.global svc_exit -.type svc_exit, % function -svc_exit: - - /* get user SP. */ - PUSH {R0} /* push result to SP. */ - BL lwp_get_kernel_sp - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - LDMFD R0!, {R3} /* pop flag */ -#endif - - LDMFD R0!, {R4 - R11} /* pop app {R4 - R11} */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - CMP R3, #0 /* if(flag_r3 != 0) */ - VLDMIANE R0!, {D8 - D15} /* pop FPU register s16~s31 */ -#endif - - ADD R0, R0, #16 /* skip R0-R3 */ - LDMFD R0!, {R12, LR} - LDMFD R0!, {R1} /* pop PC to R1 */ - LDMFD R0!, {R2} /* pop PSR to R2 */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - CMP R3, #0 /* if(flag_r3 != 0) */ - VLDMIANE R0!, {D0 - D7} /* pop FPU register s16~s31 */ - LDMIANE R0!, {R3} - VMSRNE FPSCR, R3 -#endif - - /* align to 2 words */ - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} /* push user-SP to SP */ - - /* save server SP. */ - ADD R0, SP, #0x08 /* [user-SP, result] */ - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} /* pop user-SP to R3 */ - POP {R0} /* restore API result. */ - - MSR APSR, R2 /* restore PSR */ - MSR PSP, R3 /* restore app stack pointer */ - - /* restore to PSP & thread-unprivilege mode. */ - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - /* return to lwp. */ - ORR R1, R1, #0x01 /* only Thumb-mode. */ - BX R1 /* return to user app. */ diff --git a/components/lwp/arch/arm/cortex-m4/lwp_iar.S b/components/lwp/arch/arm/cortex-m4/lwp_iar.S deleted file mode 100644 index 27ca8778e0..0000000000 --- a/components/lwp/arch/arm/cortex-m4/lwp_iar.S +++ /dev/null @@ -1,215 +0,0 @@ -;/* -; * File : lwp_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; */ - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(u32 R0_text_addr, u32 R1_data_addr); -; */ - EXPORT lwp_user_entry -lwp_user_entry: - - PUSH {R0-R1} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - POP {R0-R1} ; pop app address to R1. - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - ; set data address. - MOV R9, R1 - - ; run app, only Thumb-mode. - ORR R0, R0, #0x01 - BX R0 - -;/* -; * void SVC_Handler(void); -; */ - EXPORT SVC_Handler -SVC_Handler: - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} ; push app SP. - MOV R2, R1 - -#if defined ( __ARMVFP__ ) - TST LR, #0x10 - IT EQ - VSTMDBEQ R2!, {D8 - D15} -#endif - - STMFD R2!, {R4 - R11} ; push app R4-R11 to app stack , and R1 not change. - -#if defined ( __ARMVFP__ ) - MOV R4, #0x00 ; flag = 0 - TST LR, #0x10 ; if(!EXC_RETURN[4]) - IT EQ - MOVEQ R4, #0x01 ; flag = 1 - STMFD R2!, {R4} ; push flag -#endif - - ; get SVC number. - LDR R0, [R1, #24] ; get the app LR. - LDRB R0, [R0, #-2] ; get the SVC No. from instruction. - - ; get kernel system API - BL lwp_get_sys_api - - ; if(api == NULL) return; - CMP R0, #0 - ITTT EQ - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - ; push api - PUSH {R0} - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - ; copy R1(app SP) to R0(server SP). - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - - POP {LR} - PUSH {LR} - - ; save app SP. - PUSH {R0 - R3} -#if defined ( __ARMVFP__ ) - TST LR, #0x10 - ITE EQ - SUBEQ R0, R1, #0x64 ; keep {R4 - R11}, {D8-D15}, FLAG - SUBNE R0, R1, #0x24 ; keep {R4 - R11}, FLAG -#else - SUB R0, R1, #0x20 ; keep {R4 - R11} -#endif - BL lwp_set_kernel_sp - POP {R0 - R3} - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - ; call api. - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update stack pointer - POP {LR} ; 0xFFFFFFED - - ORR LR, LR, #0x10 - - BX LR - -;/* -; * void svc_exit(void); -; */ - EXPORT svc_exit -svc_exit: - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - -#if defined ( __ARMVFP__ ) - LDMFD R0!, {R3} ; pop flag -#endif - - LDMFD R0!, {R4 - R11} ; pop app {R4 - R11} - -#if defined ( __ARMVFP__ ) - CMP R3, #0 ; if(flag_r3 != 0) - IT NE - VLDMIANE R0!, {D8 - D15} ; pop FPU register s16~s31 -#endif - - ADD R0, R0, #16 ; skip R0-R3 - LDMFD R0!, {R12, LR} ; - LDMFD R0!, {R1} ; pop PC to R1 - LDMFD R0!, {R2} ; pop PSR to R2 - -#if defined ( __ARMVFP__ ) - CMP R3, #0 ; if(flag_r3 != 0) - ITTT NE - VLDMIANE R0!, {D0 - D7} ; pop FPU register s16~s31 - LDMIANE R0!, {R3} - VMSRNE FPSCR, R3 -#endif - - ; align to 2 words - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} ; push user-SP to SP - - ; save server SP. - ADD R0, SP, #0x08 ; [user-SP, result] - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} ; pop user-SP to R3 - POP {R0} ; restore API result. - - MSR APSR, R2 ; restore PSR - MSR PSP, R3 ; restore app stack pointer - - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - END diff --git a/components/lwp/arch/arm/cortex-m4/lwp_rvds.S b/components/lwp/arch/arm/cortex-m4/lwp_rvds.S deleted file mode 100644 index 42fad954ce..0000000000 --- a/components/lwp/arch/arm/cortex-m4/lwp_rvds.S +++ /dev/null @@ -1,219 +0,0 @@ -;/* -; * File : lwp_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ -lwp_user_entry PROC - EXPORT lwp_user_entry - - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - - ; never reach here! - ENDP - - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} ; push app SP. - MOV R2, R1 - - IF {FPU} != "SoftVFP" - TST LR, #0x10 - VSTMFDEQ R2!, {D8 - D15} - ENDIF - - STMFD R2!, {R4 - R11} ; push app R4-R11 to app stack , and R1 not change. - - IF {FPU} != "SoftVFP" - MOV R4, #0x00 ; flag = 0 - TST LR, #0x10 ; if(!EXC_RETURN[4]) - MOVEQ R4, #0x01 ; flag = 1 - STMFD R2!, {R4} ; push flag - ENDIF - - ; get SVC number. - LDR R0, [R1, #24] ; get the app LR. - LDRB R0, [R0, #-2] ; get the SVC No. from instruction. - - ; get kernel system API - BL lwp_get_sys_api - - ; if(api == NULL) return; - CMP R0, #0 - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - ; push api - PUSH {R0} - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - ; copy R1(app SP) to R0(server SP). - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - - POP {LR} - PUSH {LR} - - ; save app SP. - PUSH {R0 - R3} - IF {FPU} != "SoftVFP" - TST LR, #0x10 - SUBEQ R0, R1, #0x64 ; keep {R4 - R11}, {D8-D15}, FLAG - SUBNE R0, R1, #0x24 ; keep {R4 - R11}, FLAG - ELSE - SUB R0, R1, #0x20 ; keep {R4 - R11} - ENDIF - BL lwp_set_kernel_sp - POP {R0 - R3} - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - ; call api. - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update stack pointer - POP {LR} ; 0xFFFFFFED - - ORR LR, LR, #0x10 - - BX LR - - ENDP - -;/* -; * void svc_exit(void); -; */ -svc_exit PROC - EXPORT svc_exit - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - - IF {FPU} != "SoftVFP" - LDMFD R0!, {R3} ; pop flag - ENDIF - - LDMFD R0!, {R4 - R11} ; pop app {R4 - R11} - - IF {FPU} != "SoftVFP" - CMP R3, #0 ; if(flag_r3 != 0) - VLDMFDNE R0!, {D8 - D15} ; pop FPU register s16~s31 - ENDIF - - ADD R0, R0, #16 ; skip R0-R3 - LDMFD R0!, {R12, LR} ; - LDMFD R0!, {R1} ; pop PC to R1 - LDMFD R0!, {R2} ; pop PSR to R2 - - IF {FPU} != "SoftVFP" - CMP R3, #0 ; if(flag_r3 != 0) - VLDMFDNE R0!, {D0 - D7} ; pop FPU register s16~s31 - LDMFDNE R0!, {R3} - VMSRNE FPSCR, R3 - - ENDIF - - ; align to 2 words - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} ; push user-SP to SP - - ; save server SP. - ADD R0, SP, #0x08 ; [user-SP, result] - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} ; pop user-SP to R3 - POP {R0} ; restore API result. - - MSR APSR, R2 ; restore PSR - MSR PSP, R3 ; restore app stack pointer - - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - ENDP - - ALIGN - - END diff --git a/components/lwp/arch/arm/cortex-m7/lwp_gcc.S b/components/lwp/arch/arm/cortex-m7/lwp_gcc.S deleted file mode 100644 index fd46d6142d..0000000000 --- a/components/lwp/arch/arm/cortex-m7/lwp_gcc.S +++ /dev/null @@ -1,210 +0,0 @@ -/* - * File : lwp_gcc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -.cpu cortex-m4 -.syntax unified -.thumb -.text - -/* - * void* lwp_get_sys_api(rt_uint32_t number); - */ -.global lwp_get_sys_api -.global lwp_get_kernel_sp -.global lwp_set_kernel_sp - - -/* - * void lwp_user_entry(u32 R0_text_addr, u32 R1_data_addr); - */ -.global lwp_user_entry -.type lwp_user_entry, % function -lwp_user_entry: - PUSH {R0 - R1} /* push text&data addr. */ - - MOV R0, SP /* v1 = SP */ - BL lwp_set_kernel_sp /* lwp_set_kernel_sp(v1) */ - - POP {R0 - R1} /* pop app address to R1. */ - - /* set CPU to user-thread mode. */ - MRS R2, CONTROL - ORR R2, R2, #0x03 /* use PSP, user-thread mode. */ - MSR CONTROL, R2 - - /* set data address. */ - MOV R9, R1 - - /* run app, only Thumb-mode. */ - ORR R0, R0, #0x01 - BX R0 - -/* - * void SVC_Handler(void); - */ -.global SVC_Handler -.type SVC_Handler, % function -SVC_Handler: - - PUSH {LR} - - /* get user SP. */ - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} /* push app SP. */ - MOV R2, R1 - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST LR, #0x10 - VSTMDBEQ R2!, {D8 - D15} -#endif - - STMFD R2!, {R4 - R11} /* push app R4-R11 to app stack , and R1 not change. */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - MOV R4, #0x00 /* flag = 0 */ - TST LR, #0x10 /* if(!EXC_RETURN[4]) */ - MOVEQ R4, #0x01 /* flag = 1 */ - STMFD R2!, {R4} /* push flag */ -#endif - - /* get SVC number. */ - LDR R0, [R1, #24] /* get the app LR. */ - LDRB R0, [R0, #-2] /* get the SVC No. from instruction. */ - - /* get kernel system API */ - BL lwp_get_sys_api - - /* if(api == NULL) return; */ - CMP R0, #0 - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - /* push api */ - PUSH {R0} - - /* get kernel SP to R0. */ - BL lwp_get_kernel_sp - - POP {R2} /* pop api to R2. */ - POP {R1} /* pop app SP to R1. */ - - /* copy R1(app SP) to R0(server SP). */ - LDMFD R1, {R4 - R11} /* pop exception_stack_frame to r4 - r11 register */ - STMFD R0!, {R4 - R11} /* push exception_stack_frame to server SP. */ - - POP {LR} - PUSH {LR} - - /* save app SP. */ - PUSH {R0 - R3} -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - TST LR, #0x10 - SUBEQ R0, R1, #0x64 /* keep {R4 - R11}, {D8-D15}, FLAG */ - SUBNE R0, R1, #0x24 /* keep {R4 - R11}, FLAG */ -#else - SUB R0, R1, #0x20 /* keep {R4 - R11} */ -#endif - BL lwp_set_kernel_sp - POP {R0 - R3} - - /* set to thread-privilege mode. */ - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - /* call api. */ - LDR R3, = svc_exit - STR R3, [R0, #20] /* update LR */ - STR R2, [R0, #24] /* update api to PC */ - MSR PSP, R0 /* update stack pointer */ - POP {LR} /* 0xFFFFFFED */ - - ORR LR, LR, #0x10 - - BX LR - -/* -* void svc_exit(void); -*/ -.global svc_exit -.type svc_exit, % function -svc_exit: - - /* get user SP. */ - PUSH {R0} /* push result to SP. */ - BL lwp_get_kernel_sp - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - LDMFD R0!, {R3} /* pop flag */ -#endif - - LDMFD R0!, {R4 - R11} /* pop app {R4 - R11} */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - CMP R3, #0 /* if(flag_r3 != 0) */ - VLDMIANE R0!, {D8 - D15} /* pop FPU register s16~s31 */ -#endif - - ADD R0, R0, #16 /* skip R0-R3 */ - LDMFD R0!, {R12, LR} - LDMFD R0!, {R1} /* pop PC to R1 */ - LDMFD R0!, {R2} /* pop PSR to R2 */ - -#if defined (__VFP_FP__) && !defined(__SOFTFP__) - CMP R3, #0 /* if(flag_r3 != 0) */ - VLDMIANE R0!, {D0 - D7} /* pop FPU register s16~s31 */ - LDMIANE R0!, {R3} - VMSRNE FPSCR, R3 -#endif - - /* align to 2 words */ - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} /* push user-SP to SP */ - - /* save server SP. */ - ADD R0, SP, #0x08 /* [user-SP, result] */ - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} /* pop user-SP to R3 */ - POP {R0} /* restore API result. */ - - MSR APSR, R2 /* restore PSR */ - MSR PSP, R3 /* restore app stack pointer */ - - /* restore to PSP & thread-unprivilege mode. */ - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - /* return to lwp. */ - ORR R1, R1, #0x01 /* only Thumb-mode. */ - BX R1 /* return to user app. */ diff --git a/components/lwp/arch/arm/cortex-m7/lwp_iar.S b/components/lwp/arch/arm/cortex-m7/lwp_iar.S deleted file mode 100644 index 27ca8778e0..0000000000 --- a/components/lwp/arch/arm/cortex-m7/lwp_iar.S +++ /dev/null @@ -1,215 +0,0 @@ -;/* -; * File : lwp_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; */ - - SECTION .text:CODE(2) - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(u32 R0_text_addr, u32 R1_data_addr); -; */ - EXPORT lwp_user_entry -lwp_user_entry: - - PUSH {R0-R1} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - POP {R0-R1} ; pop app address to R1. - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - ; set data address. - MOV R9, R1 - - ; run app, only Thumb-mode. - ORR R0, R0, #0x01 - BX R0 - -;/* -; * void SVC_Handler(void); -; */ - EXPORT SVC_Handler -SVC_Handler: - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} ; push app SP. - MOV R2, R1 - -#if defined ( __ARMVFP__ ) - TST LR, #0x10 - IT EQ - VSTMDBEQ R2!, {D8 - D15} -#endif - - STMFD R2!, {R4 - R11} ; push app R4-R11 to app stack , and R1 not change. - -#if defined ( __ARMVFP__ ) - MOV R4, #0x00 ; flag = 0 - TST LR, #0x10 ; if(!EXC_RETURN[4]) - IT EQ - MOVEQ R4, #0x01 ; flag = 1 - STMFD R2!, {R4} ; push flag -#endif - - ; get SVC number. - LDR R0, [R1, #24] ; get the app LR. - LDRB R0, [R0, #-2] ; get the SVC No. from instruction. - - ; get kernel system API - BL lwp_get_sys_api - - ; if(api == NULL) return; - CMP R0, #0 - ITTT EQ - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - ; push api - PUSH {R0} - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - ; copy R1(app SP) to R0(server SP). - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - - POP {LR} - PUSH {LR} - - ; save app SP. - PUSH {R0 - R3} -#if defined ( __ARMVFP__ ) - TST LR, #0x10 - ITE EQ - SUBEQ R0, R1, #0x64 ; keep {R4 - R11}, {D8-D15}, FLAG - SUBNE R0, R1, #0x24 ; keep {R4 - R11}, FLAG -#else - SUB R0, R1, #0x20 ; keep {R4 - R11} -#endif - BL lwp_set_kernel_sp - POP {R0 - R3} - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - ; call api. - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update stack pointer - POP {LR} ; 0xFFFFFFED - - ORR LR, LR, #0x10 - - BX LR - -;/* -; * void svc_exit(void); -; */ - EXPORT svc_exit -svc_exit: - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - -#if defined ( __ARMVFP__ ) - LDMFD R0!, {R3} ; pop flag -#endif - - LDMFD R0!, {R4 - R11} ; pop app {R4 - R11} - -#if defined ( __ARMVFP__ ) - CMP R3, #0 ; if(flag_r3 != 0) - IT NE - VLDMIANE R0!, {D8 - D15} ; pop FPU register s16~s31 -#endif - - ADD R0, R0, #16 ; skip R0-R3 - LDMFD R0!, {R12, LR} ; - LDMFD R0!, {R1} ; pop PC to R1 - LDMFD R0!, {R2} ; pop PSR to R2 - -#if defined ( __ARMVFP__ ) - CMP R3, #0 ; if(flag_r3 != 0) - ITTT NE - VLDMIANE R0!, {D0 - D7} ; pop FPU register s16~s31 - LDMIANE R0!, {R3} - VMSRNE FPSCR, R3 -#endif - - ; align to 2 words - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} ; push user-SP to SP - - ; save server SP. - ADD R0, SP, #0x08 ; [user-SP, result] - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} ; pop user-SP to R3 - POP {R0} ; restore API result. - - MSR APSR, R2 ; restore PSR - MSR PSP, R3 ; restore app stack pointer - - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - END diff --git a/components/lwp/arch/arm/cortex-m7/lwp_rvds.S b/components/lwp/arch/arm/cortex-m7/lwp_rvds.S deleted file mode 100644 index 6c310a3632..0000000000 --- a/components/lwp/arch/arm/cortex-m7/lwp_rvds.S +++ /dev/null @@ -1,218 +0,0 @@ -;/* -; * File : lwp_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; */ - - AREA |.text|, CODE, READONLY, ALIGN=2 - THUMB - REQUIRE8 - PRESERVE8 - -;/* -; * void* lwp_get_sys_api(rt_uint32_t number); -; */ - IMPORT lwp_get_sys_api - IMPORT lwp_get_kernel_sp - IMPORT lwp_set_kernel_sp - -;/* -; * void lwp_user_entry(args, text, data); -; */ -lwp_user_entry PROC - EXPORT lwp_user_entry - - PUSH {R0-R3} ; push text&data addr. - - MOV R0, SP ; v1 = SP - BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1) - - ; set CPU to user-thread mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 ; use PSP, user-thread mode. - MSR CONTROL, R2 - - POP {R0-R3} ; pop app address to R1. - ; set data address. - MOV R9, R2 - - ; run app, only Thumb-mode. - ORR R1, R1, #0x01 - BX R1 - - ; never reach here! - ENDP - -;/* -; * void SVC_Handler(void); -; */ -SVC_Handler PROC - EXPORT SVC_Handler - - PUSH {LR} - - ; get user SP. - TST LR, #0x4 - ITE EQ - MRSEQ R1, MSP - MRSNE R1, PSP - - PUSH {R1} ; push app SP. - MOV R2, R1 - - IF {FPU} != "SoftVFP" - TST LR, #0x10 - VSTMFDEQ R2!, {D8 - D15} - ENDIF - - STMFD R2!, {R4 - R11} ; push app R4-R11 to app stack , and R1 not change. - - IF {FPU} != "SoftVFP" - MOV R4, #0x00 ; flag = 0 - TST LR, #0x10 ; if(!EXC_RETURN[4]) - MOVEQ R4, #0x01 ; flag = 1 - STMFD R2!, {R4} ; push flag - ENDIF - - ; get SVC number. - LDR R0, [R1, #24] ; get the app LR. - LDRB R0, [R0, #-2] ; get the SVC No. from instruction. - - ; get kernel system API - BL lwp_get_sys_api - - ; if(api == NULL) return; - CMP R0, #0 - POPEQ {R1} - POPEQ {LR} - BXEQ LR - - ; push api - PUSH {R0} - - ; get kernel SP to R0. - BL lwp_get_kernel_sp - - POP {R2} ; pop api to R2. - POP {R1} ; pop app SP to R1. - - ; copy R1(app SP) to R0(server SP). - LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register - STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP. - - POP {LR} - PUSH {LR} - - ; save app SP. - PUSH {R0 - R3} - IF {FPU} != "SoftVFP" - TST LR, #0x10 - SUBEQ R0, R1, #0x64 ; keep {R4 - R11}, {D8-D15}, FLAG - SUBNE R0, R1, #0x24 ; keep {R4 - R11}, FLAG - ELSE - SUB R0, R1, #0x20 ; keep {R4 - R11} - ENDIF - BL lwp_set_kernel_sp - POP {R0 - R3} - - ; set to thread-privilege mode. - MRS R3, CONTROL - BIC R3, R3, #0x01 - ORR R3, R3, #0x02 - MSR CONTROL, R3 - - ; call api. - LDR R3, =svc_exit - STR R3, [R0, #20] ; update LR - STR R2, [R0, #24] ; update api to PC - MSR PSP, R0 ; update stack pointer - POP {LR} ; 0xFFFFFFED - - ORR LR, LR, #0x10 - - BX LR - - ENDP - -;/* -; * void svc_exit(void); -; */ -svc_exit PROC - EXPORT svc_exit - - ; get user SP. - PUSH {R0} ; push result to SP. - BL lwp_get_kernel_sp - - IF {FPU} != "SoftVFP" - LDMFD R0!, {R3} ; pop flag - ENDIF - - LDMFD R0!, {R4 - R11} ; pop app {R4 - R11} - - IF {FPU} != "SoftVFP" - CMP R3, #0 ; if(flag_r3 != 0) - VLDMFDNE R0!, {D8 - D15} ; pop FPU register s16~s31 - ENDIF - - ADD R0, R0, #16 ; skip R0-R3 - LDMFD R0!, {R12, LR} ; - LDMFD R0!, {R1} ; pop PC to R1 - LDMFD R0!, {R2} ; pop PSR to R2 - - IF {FPU} != "SoftVFP" - CMP R3, #0 ; if(flag_r3 != 0) - VLDMFDNE R0!, {D0 - D7} ; pop FPU register s16~s31 - LDMFDNE R0!, {R3} - VMSRNE FPSCR, R3 - - ENDIF - - ; align to 2 words - ADD R0, R0, #0x07 - BIC R0, R0, #0x07 - PUSH {R0} ; push user-SP to SP - - ; save server SP. - ADD R0, SP, #0x08 ; [user-SP, result] - PUSH {R1 - R2, LR} - BL lwp_set_kernel_sp - POP {R1 - R2, LR} - - POP {R3} ; pop user-SP to R3 - POP {R0} ; restore API result. - - MSR APSR, R2 ; restore PSR - MSR PSP, R3 ; restore app stack pointer - - ; restore to PSP & thread-unprivilege mode. - MRS R2, CONTROL - ORR R2, R2, #0x03 - MSR CONTROL, R2 - - ; return to lwp. - ORR R1, R1, #0x01 ; only Thumb-mode. - BX R1 ; return to user app. - - ENDP - - ALIGN - - END diff --git a/components/lwp/lwp.c b/components/lwp/lwp.c deleted file mode 100644 index 0bfeb4b103..0000000000 --- a/components/lwp/lwp.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -#include -#include -#include - -#ifndef RT_USING_DFS - #error "lwp need file system(RT_USING_DFS)" -#endif - -#include "lwp.h" - -#define DBG_ENABLE -#define DBG_SECTION_NAME "LWP" -#define DBG_COLOR -#define DBG_LEVEL DBG_WARNING -#include - -extern rt_thread_t rt_current_thread; -extern void lwp_user_entry(void *args, const void *text, void *data); - -/** - * RT-Thread light-weight process - */ -void lwp_set_kernel_sp(uint32_t *sp) -{ - struct rt_lwp *user_data; - user_data = (struct rt_lwp *)rt_current_thread->lwp; - user_data->kernel_sp = sp; -} - -uint32_t *lwp_get_kernel_sp(void) -{ - struct rt_lwp *user_data; - user_data = (struct rt_lwp *)rt_current_thread->lwp; - - return user_data->kernel_sp; -} - -static int lwp_argscopy(struct rt_lwp *lwp, int argc, char **argv) -{ - int size = sizeof(int)*3; /* store argc, argv, NULL */ - int *args; - char *str; - char **new_argv; - int i; - int len; - - for (i = 0; i < argc; i ++) - { - size += (rt_strlen(argv[i]) + 1); - } - size += (sizeof(int) * argc); - - args = (int*)rt_malloc(size); - if (args == RT_NULL) - return -1; - - str = (char*)((int)args + (argc + 3) * sizeof(int)); - new_argv = (char**)&args[2]; - args[0] = argc; - args[1] = (int)new_argv; - - for (i = 0; i < argc; i ++) - { - len = rt_strlen(argv[i]) + 1; - new_argv[i] = str; - rt_memcpy(str, argv[i], len); - str += len; - } - new_argv[i] = 0; - lwp->args = args; - - return 0; -} - -static int lwp_load(const char *filename, struct rt_lwp *lwp, uint8_t *load_addr, size_t addr_size) -{ - int fd; - uint8_t *ptr; - int result = RT_EOK; - int nbytes; - struct lwp_header header; - struct lwp_chunk chunk; - - /* check file name */ - RT_ASSERT(filename != RT_NULL); - /* check lwp control block */ - RT_ASSERT(lwp != RT_NULL); - - if (load_addr != RT_NULL) - { - lwp->lwp_type = LWP_TYPE_FIX_ADDR; - ptr = load_addr; - } - else - { - lwp->lwp_type = LWP_TYPE_DYN_ADDR; - ptr = RT_NULL; - } - - /* open lwp */ - fd = open(filename, 0, O_RDONLY); - if (fd < 0) - { - dbg_log(DBG_ERROR, "open file:%s failed!\n", filename); - result = -RT_ENOSYS; - goto _exit; - } - - /* read lwp header */ - nbytes = read(fd, &header, sizeof(struct lwp_header)); - if (nbytes != sizeof(struct lwp_header)) - { - dbg_log(DBG_ERROR, "read lwp header return error size: %d!\n", nbytes); - result = -RT_EIO; - goto _exit; - } - - /* check file header */ - if (header.magic != LWP_MAGIC) - { - dbg_log(DBG_ERROR, "erro header magic number: 0x%02X\n", header.magic); - result = -RT_EINVAL; - goto _exit; - } - - /* read text chunk info */ - nbytes = read(fd, &chunk, sizeof(struct lwp_chunk)); - if (nbytes != sizeof(struct lwp_chunk)) - { - dbg_log(DBG_ERROR, "read text chunk info failed!\n"); - result = -RT_EIO; - goto _exit; - } - - dbg_log(DBG_LOG, "chunk name: %s, total len %d, data %d, need space %d!\n", - "text", /*chunk.name*/ chunk.total_len, chunk.data_len, chunk.data_len_space); - - /* load text */ - { - lwp->text_size = RT_ALIGN(chunk.data_len_space, 4); - if (load_addr) - lwp->text_entry = ptr; - else - { -#ifdef RT_USING_CACHE - lwp->text_entry = (rt_uint8_t *)rt_malloc_align(lwp->text_size, RT_CPU_CACHE_LINE_SZ); -#else - lwp->text_entry = (rt_uint8_t *)rt_malloc(lwp->text_size); -#endif - - if (lwp->text_entry == RT_NULL) - { - dbg_log(DBG_ERROR, "alloc text memory faild!\n"); - result = -RT_ENOMEM; - goto _exit; - } - else - { - dbg_log(DBG_LOG, "lwp text malloc : %p, size: %d!\n", lwp->text_entry, lwp->text_size); - } - } - dbg_log(DBG_INFO, "load text %d => (0x%08x, 0x%08x)\n", lwp->text_size, (uint32_t)lwp->text_entry, (uint32_t)lwp->text_entry + lwp->text_size); - - nbytes = read(fd, lwp->text_entry, chunk.data_len); - if (nbytes != chunk.data_len) - { - dbg_log(DBG_ERROR, "read text region from file failed!\n"); - result = -RT_EIO; - goto _exit; - } -#ifdef RT_USING_CACHE - else - { - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lwp->text_entry, lwp->text_size); - rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, lwp->text_entry, lwp->text_size); - } -#endif - - if (ptr != RT_NULL) ptr += nbytes; - - /* skip text hole */ - if ((chunk.total_len - sizeof(struct lwp_chunk) - chunk.data_len)) - { - dbg_log(DBG_LOG, "skip text hole %d!\n", (chunk.total_len - sizeof(struct lwp_chunk) - chunk.data_len)); - lseek(fd, (chunk.total_len - sizeof(struct lwp_chunk) - chunk.data_len), SEEK_CUR); - } - } - - /* load data */ - nbytes = read(fd, &chunk, sizeof(struct lwp_chunk)); - if (nbytes != sizeof(struct lwp_chunk)) - { - dbg_log(DBG_ERROR, "read data chunk info failed!\n"); - result = -RT_EIO; - goto _exit; - } - - dbg_log(DBG_LOG, "chunk name: %s, total len %d, data %d, need space %d!\n", - chunk.name, chunk.total_len, chunk.data_len, chunk.data_len_space); - - { - lwp->data_size = RT_ALIGN(chunk.data_len_space, 4); - if (load_addr) - lwp->data = ptr; - else - { - lwp->data = rt_malloc(lwp->data_size); - if (lwp->data == RT_NULL) - { - dbg_log(DBG_ERROR, "alloc data memory faild!\n"); - result = -RT_ENOMEM; - goto _exit; - } - else - { - dbg_log(DBG_LOG, "lwp data malloc : %p, size: %d!\n", lwp->data, lwp->data_size); - rt_memset(lwp->data, 0, lwp->data_size); - } - } - - dbg_log(DBG_INFO, "load data %d => (0x%08x, 0x%08x)\n", lwp->data_size, (uint32_t)lwp->data, (uint32_t)lwp->data + lwp->data_size); - nbytes = read(fd, lwp->data, chunk.data_len); - if (nbytes != chunk.data_len) - { - dbg_log(DBG_ERROR, "read data region from file failed!\n"); - result = -RT_ERROR; - goto _exit; - } - } - -_exit: - if (fd >= 0) - close(fd); - - if (result != RT_EOK) - { - if (lwp->lwp_type == LWP_TYPE_DYN_ADDR) - { - dbg_log(DBG_ERROR, "lwp dynamic load faild, %d\n", result); - if (lwp->text_entry) - { - dbg_log(DBG_LOG, "lwp text free: %p\n", lwp->text_entry); -#ifdef RT_USING_CACHE - rt_free_align(lwp->text_entry); -#else - rt_free(lwp->text_entry); -#endif - } - if (lwp->data) - { - dbg_log(DBG_LOG, "lwp data free: %p\n", lwp->data); - rt_free(lwp->data); - } - } - } - - return result; -} - -static void lwp_cleanup(struct rt_thread *tid) -{ - struct rt_lwp *lwp; - - dbg_log(DBG_INFO, "thread: %s, stack_addr: %08X\n", tid->name, tid->stack_addr); - - lwp = (struct rt_lwp *)tid->lwp; - - if (lwp->lwp_type == LWP_TYPE_DYN_ADDR) - { - dbg_log(DBG_INFO, "dynamic lwp\n"); - if (lwp->text_entry) - { - dbg_log(DBG_LOG, "lwp text free: %p\n", lwp->text_entry); -#ifdef RT_USING_CACHE - rt_free_align(lwp->text_entry); -#else - rt_free(lwp->text_entry); -#endif - } - if (lwp->data) - { - dbg_log(DBG_LOG, "lwp data free: %p\n", lwp->data); - rt_free(lwp->data); - } - } - - dbg_log(DBG_LOG, "lwp free memory pages\n"); - rt_lwp_mem_deinit(lwp); - - /* cleanup fd table */ - while (lwp->fdt.maxfd > 0) - { - lwp->fdt.maxfd --; - close(lwp->fdt.maxfd); - } - rt_free(lwp->fdt.fds); - rt_free(lwp->args); - - dbg_log(DBG_LOG, "lwp free: %p\n", lwp); - rt_free(lwp); - - /* TODO: cleanup fd table */ -} - -static void lwp_thread(void *parameter) -{ - rt_thread_t tid; - struct rt_lwp *lwp; - - lwp = (struct rt_lwp *)parameter; - rt_lwp_mem_init(lwp); - tid = rt_thread_self(); - tid->lwp = lwp; - tid->cleanup = lwp_cleanup; - - lwp_user_entry(lwp->args, lwp->text_entry, lwp->data); -} - -struct rt_lwp *rt_lwp_self(void) -{ - return (struct rt_lwp *)rt_thread_self()->lwp; -} - -int exec(char *filename, int argc, char **argv) -{ - struct rt_lwp *lwp; - int result; - - if (filename == RT_NULL) - return -RT_ERROR; - - lwp = (struct rt_lwp *)rt_malloc(sizeof(struct rt_lwp)); - if (lwp == RT_NULL) - { - dbg_log(DBG_ERROR, "lwp struct out of memory!\n"); - return -RT_ENOMEM; - } - dbg_log(DBG_INFO, "lwp malloc : %p, size: %d!\n", lwp, sizeof(struct rt_lwp)); - - rt_memset(lwp, 0, sizeof(*lwp)); - if (lwp_argscopy(lwp, argc, argv) != 0) - { - rt_free(lwp); - return -ENOMEM; - } - - result = lwp_load(filename, lwp, RT_NULL, 0); - if (result == RT_EOK) - { - rt_thread_t tid; - - tid = rt_thread_create("user", lwp_thread, (void *)lwp, - 1024 * 4, 2, 200); - if (tid != RT_NULL) - { - dbg_log(DBG_LOG, "lwp kernel => (0x%08x, 0x%08x)\n", (rt_uint32_t)tid->stack_addr, (rt_uint32_t)tid->stack_addr + tid->stack_size); - rt_thread_startup(tid); - return RT_EOK; - } - else - { -#ifdef RT_USING_CACHE - rt_free_align(lwp->text_entry); -#else - rt_free(lwp->text_entry); -#endif - rt_free(lwp->data); - } - } - - rt_free(lwp->args); - rt_free(lwp); - - return -RT_ERROR; -} diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h deleted file mode 100644 index 0b25cf6917..0000000000 --- a/components/lwp/lwp.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * File : lwp.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -#ifndef __LWP_H__ -#define __LWP_H__ - -#define LWP_MAGIC 0x5A - -#define LWP_TYPE_FIX_ADDR 0x01 -#define LWP_TYPE_DYN_ADDR 0x02 - -#define LWP_ARG_MAX 8 - -#include -#include -#include -#include - -struct rt_lwp -{ - uint8_t lwp_type; - uint8_t heap_cnt; - uint8_t reserv[2]; - - rt_list_t hlist; /**< headp list */ - - uint8_t *text_entry; - uint32_t text_size; - - uint8_t *data; - uint32_t data_size; - - uint32_t *kernel_sp; /**< kernel stack point */ - struct dfs_fdtable fdt; - void *args; -}; - -struct lwp_header -{ - uint8_t magic; - uint8_t compress_encrypt_algo; - uint16_t reserved; - - uint32_t crc32; -}; - -struct lwp_chunk -{ - uint32_t total_len; - - char name[4]; - uint32_t data_len; - uint32_t data_len_space; -}; - -extern struct rt_lwp *rt_lwp_self(void); - -extern void rt_lwp_mem_init(struct rt_lwp *lwp); -extern void rt_lwp_mem_deinit(struct rt_lwp *lwp); -extern void *rt_lwp_mem_malloc(rt_uint32_t size); -extern void rt_lwp_mem_free(void *addr); -extern void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize); - -#endif diff --git a/components/lwp/lwp_mem.c b/components/lwp/lwp_mem.c deleted file mode 100644 index 9b3dcf45a6..0000000000 --- a/components/lwp/lwp_mem.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * File : lwp_mem.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2018-03-24 Tanek the first version - */ - -#include -#include - -#define DBG_ENABLE -#define DBG_SECTION_NAME "LWPMEM" -#define DBG_COLOR -#define DBG_LEVEL DBG_WARNING -#include - -// todo: remove repleat code -#define RT_MEMHEAP_SIZE RT_ALIGN(sizeof(struct rt_lwp_memheap_item), RT_ALIGN_SIZE) -#define MEMITEM_SIZE(item) ((rt_uint32_t)item->next - (rt_uint32_t)item - RT_MEMHEAP_SIZE) - -#ifndef LWP_MEM_PAGE_SIZE - #define LWP_MEM_PAGE_SIZE (4 * 1024) -#endif - -#ifndef LWP_MEM_MAX_PAGE_COUNT - #define LWP_MEM_MAX_PAGE_COUNT (256 * 4) -#endif - -static void *rt_lwp_malloc_page(struct rt_lwp *lwp, rt_size_t npages) -{ - void *chunk; - char name[6]; - struct rt_lwp_memheap *lwp_heap; - rt_size_t page_cnt; - - RT_ASSERT(lwp != RT_NULL); - - page_cnt = lwp->heap_cnt + npages; - if (page_cnt > LWP_MEM_MAX_PAGE_COUNT) - { - dbg_log(DBG_ERROR, "alloc new page failed, lwp memory size out of limited: %d\n", page_cnt); - return RT_NULL; - } - - lwp_heap = rt_malloc(sizeof(struct rt_lwp_memheap)); - if (lwp_heap == RT_NULL) - { - dbg_log(DBG_ERROR, "alloc new page head failed, out of memory : %d\n", page_cnt); - return RT_NULL; - } - - chunk = rt_malloc(npages * LWP_MEM_PAGE_SIZE); - if (chunk == RT_NULL) - { - dbg_log(DBG_ERROR, "alloc new page buffer failed, out of memory : %d\n", page_cnt); - rt_free(lwp_heap); - return RT_NULL; - } - - dbg_log(DBG_LOG, "lwp alloc page: %d\n", npages); - - rt_sprintf(name, "lwp%02x", lwp->heap_cnt); - rt_lwp_memheap_init(lwp_heap, name, chunk, npages * LWP_MEM_PAGE_SIZE); - - rt_list_insert_before(&lwp->hlist, &lwp_heap->mlist); - - lwp->heap_cnt += npages; - - return chunk; -} - -static void rt_lwp_free_page(struct rt_lwp *lwp, struct rt_lwp_memheap *lwp_heap) -{ - rt_size_t npages; - - RT_ASSERT(lwp != RT_NULL); - RT_ASSERT(lwp_heap != RT_NULL); - RT_ASSERT(lwp_heap->start_addr != RT_NULL); - - npages = lwp_heap->pool_size / LWP_MEM_PAGE_SIZE; - lwp->heap_cnt -= npages; - - dbg_log(DBG_LOG, "lwp free page: %d\n", npages); - - rt_list_remove(&lwp_heap->mlist); - - rt_free(lwp_heap->start_addr); - rt_free(lwp_heap); -} - -void rt_lwp_mem_init(struct rt_lwp *lwp) -{ - RT_ASSERT(lwp != RT_NULL); - rt_list_init(&lwp->hlist); -} - -void rt_lwp_mem_deinit(struct rt_lwp *lwp) -{ - struct rt_list_node *node; - - RT_ASSERT(lwp != RT_NULL); - - node = lwp->hlist.next; - - while (node != &(lwp->hlist)) - { - struct rt_lwp_memheap *lwp_heap; - - lwp_heap = rt_list_entry(node, struct rt_lwp_memheap, mlist); - RT_ASSERT(lwp_heap != RT_NULL); - - /* update note before free page*/ - node = node->next; - - rt_lwp_free_page(lwp, lwp_heap); - } -} - -void *rt_lwp_mem_malloc(rt_uint32_t size) -{ - struct rt_lwp *lwp; - struct rt_list_node *node; - void *addr = RT_NULL; - rt_uint32_t npages; - - if (size == 0) - return RT_NULL; - - lwp = rt_lwp_self(); - RT_ASSERT(lwp != RT_NULL); - - for (node = lwp->hlist.next; node != &(lwp->hlist); node = node->next) - { - struct rt_lwp_memheap *lwp_heap; - lwp_heap = rt_list_entry(node, struct rt_lwp_memheap, mlist); - - addr = rt_lwp_memheap_alloc(lwp_heap, size); - if (addr != RT_NULL) - { - dbg_log(DBG_LOG, "lwp alloc 0x%x/%d\n", addr, size); - return addr; - } - } - - npages = (size + rt_lwp_memheap_unavailable_size_get() + LWP_MEM_PAGE_SIZE) / LWP_MEM_PAGE_SIZE; - if (RT_NULL != rt_lwp_malloc_page(lwp, npages)) - return rt_lwp_mem_malloc(size); - else - return RT_NULL; -} - -void rt_lwp_mem_free(void *addr) -{ - struct rt_lwp_memheap_item *header_ptr; - struct rt_lwp_memheap *lwp_heap; - - if (addr == RT_NULL) - return ; - - /* get memory item */ - header_ptr = (struct rt_lwp_memheap_item *)((rt_uint8_t *)addr - RT_MEMHEAP_SIZE); - RT_ASSERT(header_ptr); - - lwp_heap = header_ptr->pool_ptr; - RT_ASSERT(lwp_heap); - - dbg_log(DBG_LOG, "lwp free 0x%x\n", addr); - rt_lwp_memheap_free((void *)addr); - - if (rt_lwp_memheap_is_empty(lwp_heap)) - { - rt_lwp_free_page(rt_lwp_self(), lwp_heap); - } -} - -void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize) -{ - void *new_ptr; - struct rt_lwp_memheap_item *header_ptr; - - if (rmem == RT_NULL) - return rt_lwp_mem_malloc(newsize); - - if (newsize == 0) - { - rt_lwp_mem_free(rmem); - return RT_NULL; - } - - /* get old memory item */ - header_ptr = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)rmem - RT_MEMHEAP_SIZE); - - new_ptr = rt_lwp_memheap_realloc(header_ptr->pool_ptr, rmem, newsize); - if (new_ptr == RT_NULL) - { - /* allocate memory block from other memheap */ - new_ptr = rt_lwp_mem_malloc(newsize); - if (new_ptr != RT_NULL && rmem != RT_NULL) - { - rt_size_t oldsize; - - /* get the size of old memory block */ - oldsize = MEMITEM_SIZE(header_ptr); - if (newsize > oldsize) - rt_memcpy(new_ptr, rmem, oldsize); - else - rt_memcpy(new_ptr, rmem, newsize); - - dbg_log(DBG_LOG, "lwp realloc with memcpy 0x%x -> 0x%x/%d\n", rmem, new_ptr, newsize); - rt_lwp_mem_free(rmem); - - } - } - - dbg_log(DBG_LOG, "lwp realloc in same address 0x%x/%d\n", rmem, newsize); - - return new_ptr; -} diff --git a/components/lwp/lwp_memheap.c b/components/lwp/lwp_memheap.c deleted file mode 100644 index 46ba667695..0000000000 --- a/components/lwp/lwp_memheap.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - * File : lwp_memheap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2012-04-10 Bernard first implementation - * 2012-10-16 Bernard add the mutex lock for heap object. - * 2012-12-29 Bernard memheap can be used as system heap. - * change mutex lock to semaphore lock. - * 2013-04-10 Bernard add rt_lwp_memheap_realloc function. - * 2013-05-24 Bernard fix the rt_lwp_memheap_realloc issue. - * 2013-07-11 Grissiom fix the memory block splitting issue. - * 2013-07-15 Grissiom optimize rt_lwp_memheap_realloc - */ - -#include -#include -#include - -/* dynamic pool magic and mask */ -#define RT_MEMHEAP_MAGIC 0x1ea01ea0 -#define RT_MEMHEAP_MASK 0xfffffffe -#define RT_MEMHEAP_USED 0x01 -#define RT_MEMHEAP_FREED 0x00 - -#define RT_MEMHEAP_IS_USED(i) ((i)->magic & RT_MEMHEAP_USED) -#define RT_MEMHEAP_MINIALLOC 12 - -#define RT_MEMHEAP_SIZE RT_ALIGN(sizeof(struct rt_lwp_memheap_item), RT_ALIGN_SIZE) -#define MEMITEM_SIZE(item) ((rt_uint32_t)item->next - (rt_uint32_t)item - RT_MEMHEAP_SIZE) - -/* - * The initialized memory pool will be: - * +-----------------------------------+--------------------------+ - * | whole freed memory block | Used Memory Block Tailer | - * +-----------------------------------+--------------------------+ - * - * block_list --> whole freed memory block - * - * The length of Used Memory Block Tailer is 0, - * which is prevents block merging across list - */ -rt_err_t rt_lwp_memheap_init(struct rt_lwp_memheap *memheap, - const char *name, - void *start_addr, - rt_uint32_t size) -{ - struct rt_lwp_memheap_item *item; - - RT_ASSERT(memheap != RT_NULL); - - /* initialize pool object */ - memheap->start_addr = start_addr; - memheap->pool_size = RT_ALIGN_DOWN(size, RT_ALIGN_SIZE); - memheap->available_size = memheap->pool_size - (2 * RT_MEMHEAP_SIZE); - memheap->max_used_size = memheap->pool_size - memheap->available_size; - - /* initialize the free list header */ - item = &(memheap->free_header); - item->magic = RT_MEMHEAP_MAGIC; - item->pool_ptr = memheap; - item->next = RT_NULL; - item->prev = RT_NULL; - item->next_free = item; - item->prev_free = item; - - /* set the free list to free list header */ - memheap->free_list = item; - - /* initialize the first big memory block */ - item = (struct rt_lwp_memheap_item *)start_addr; - item->magic = RT_MEMHEAP_MAGIC; - item->pool_ptr = memheap; - item->next = RT_NULL; - item->prev = RT_NULL; - item->next_free = item; - item->prev_free = item; - - item->next = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)item + memheap->available_size + RT_MEMHEAP_SIZE); - item->prev = item->next; - - /* block list header */ - memheap->block_list = item; - - /* place the big memory block to free list */ - item->next_free = memheap->free_list->next_free; - item->prev_free = memheap->free_list; - memheap->free_list->next_free->prev_free = item; - memheap->free_list->next_free = item; - - /* move to the end of memory pool to build a small tailer block, - * which prevents block merging - */ - item = item->next; - /* it's a used memory block */ - item->magic = RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED; - item->pool_ptr = memheap; - item->next = (struct rt_lwp_memheap_item *)start_addr; - item->prev = (struct rt_lwp_memheap_item *)start_addr; - /* not in free list */ - item->next_free = item->prev_free = RT_NULL; - - /* initialize semaphore lock */ - rt_sem_init(&(memheap->lock), name, 1, RT_IPC_FLAG_FIFO); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("memory heap: start addr 0x%08x, size %d, free list header 0x%08x\n", - start_addr, size, &(memheap->free_header))); - - return RT_EOK; -} - -void *rt_lwp_memheap_alloc(struct rt_lwp_memheap *heap, rt_uint32_t size) -{ - rt_err_t result; - rt_uint32_t free_size; - struct rt_lwp_memheap_item *header_ptr; - - RT_ASSERT(heap != RT_NULL); - - /* align allocated size */ - size = RT_ALIGN(size, RT_ALIGN_SIZE); - if (size < RT_MEMHEAP_MINIALLOC) - size = RT_MEMHEAP_MINIALLOC; - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("allocate %d on heap:%8.*s", - size, RT_NAME_MAX, heap->parent.name)); - - if (size < heap->available_size) - { - /* search on free list */ - free_size = 0; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - - return RT_NULL; - } - - /* get the first free memory block */ - header_ptr = heap->free_list->next_free; - while (header_ptr != heap->free_list && free_size < size) - { - /* get current freed memory block size */ - free_size = MEMITEM_SIZE(header_ptr); - if (free_size < size) - { - /* move to next free memory block */ - header_ptr = header_ptr->next_free; - } - } - - /* determine if the memory is available. */ - if (free_size >= size) - { - /* a block that satisfies the request has been found. */ - - /* determine if the block needs to be split. */ - if (free_size >= (size + RT_MEMHEAP_SIZE + RT_MEMHEAP_MINIALLOC)) - { - struct rt_lwp_memheap_item *new_ptr; - - /* split the block. */ - new_ptr = (struct rt_lwp_memheap_item *) - (((rt_uint8_t *)header_ptr) + size + RT_MEMHEAP_SIZE); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("split: block[0x%08x] nextm[0x%08x] prevm[0x%08x] to new[0x%08x]\n", - header_ptr, - header_ptr->next, - header_ptr->prev, - new_ptr)); - - /* mark the new block as a memory block and freed. */ - new_ptr->magic = RT_MEMHEAP_MAGIC; - - /* put the pool pointer into the new block. */ - new_ptr->pool_ptr = heap; - - /* break down the block list */ - new_ptr->prev = header_ptr; - new_ptr->next = header_ptr->next; - header_ptr->next->prev = new_ptr; - header_ptr->next = new_ptr; - - /* remove header ptr from free list */ - header_ptr->next_free->prev_free = header_ptr->prev_free; - header_ptr->prev_free->next_free = header_ptr->next_free; - header_ptr->next_free = RT_NULL; - header_ptr->prev_free = RT_NULL; - - /* insert new_ptr to free list */ - new_ptr->next_free = heap->free_list->next_free; - new_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = new_ptr; - heap->free_list->next_free = new_ptr; - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new ptr: next_free 0x%08x, prev_free 0x%08x\n", - new_ptr->next_free, - new_ptr->prev_free)); - - /* decrement the available byte count. */ - heap->available_size = heap->available_size - - size - - RT_MEMHEAP_SIZE; - if (heap->pool_size - heap->available_size > heap->max_used_size) - heap->max_used_size = heap->pool_size - heap->available_size; - } - else - { - /* decrement the entire free size from the available bytes count. */ - heap->available_size = heap->available_size - free_size; - if (heap->pool_size - heap->available_size > heap->max_used_size) - heap->max_used_size = heap->pool_size - heap->available_size; - - /* remove header_ptr from free list */ - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("one block: block[0x%08x], next_free 0x%08x, prev_free 0x%08x\n", - header_ptr, - header_ptr->next_free, - header_ptr->prev_free)); - - header_ptr->next_free->prev_free = header_ptr->prev_free; - header_ptr->prev_free->next_free = header_ptr->next_free; - header_ptr->next_free = RT_NULL; - header_ptr->prev_free = RT_NULL; - } - - /* Mark the allocated block as not available. */ - header_ptr->magic |= RT_MEMHEAP_USED; - - /* release lock */ - rt_sem_release(&(heap->lock)); - - /* Return a memory address to the caller. */ - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("alloc mem: memory[0x%08x], heap[0x%08x], size: %d\n", - (void *)((rt_uint8_t *)header_ptr + RT_MEMHEAP_SIZE), - header_ptr, - size)); - - return (void *)((rt_uint8_t *)header_ptr + RT_MEMHEAP_SIZE); - } - - /* release lock */ - rt_sem_release(&(heap->lock)); - } - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("allocate memory: failed\n")); - - /* Return the completion status. */ - return RT_NULL; -} - -void *rt_lwp_memheap_realloc(struct rt_lwp_memheap *heap, void *ptr, rt_size_t newsize) -{ - rt_err_t result; - rt_size_t oldsize; - struct rt_lwp_memheap_item *header_ptr; - struct rt_lwp_memheap_item *new_ptr; - - if (newsize == 0) - { - rt_lwp_memheap_free(ptr); - - return RT_NULL; - } - /* align allocated size */ - newsize = RT_ALIGN(newsize, RT_ALIGN_SIZE); - if (newsize < RT_MEMHEAP_MINIALLOC) - newsize = RT_MEMHEAP_MINIALLOC; - - if (ptr == RT_NULL) - { - return rt_lwp_memheap_alloc(heap, newsize); - } - - /* get memory block header and get the size of memory block */ - header_ptr = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE); - oldsize = MEMITEM_SIZE(header_ptr); - /* re-allocate memory */ - if (newsize > oldsize) - { - void *new_ptr; - struct rt_lwp_memheap_item *next_ptr; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - return RT_NULL; - } - - next_ptr = header_ptr->next; - - /* header_ptr should not be the tail */ - RT_ASSERT(next_ptr > header_ptr); - - /* check whether the following free space is enough to expand */ - if (!RT_MEMHEAP_IS_USED(next_ptr)) - { - rt_int32_t nextsize; - - nextsize = MEMITEM_SIZE(next_ptr); - RT_ASSERT(next_ptr > 0); - - /* Here is the ASCII art of the situation that we can make use of - * the next free node without alloc/memcpy, |*| is the control - * block: - * - * oldsize free node - * |*|-----------|*|----------------------|*| - * newsize >= minialloc - * |*|----------------|*|-----------------|*| - */ - if (nextsize + oldsize > newsize + RT_MEMHEAP_MINIALLOC) - { - /* decrement the entire free size from the available bytes count. */ - heap->available_size = heap->available_size - (newsize - oldsize); - if (heap->pool_size - heap->available_size > heap->max_used_size) - heap->max_used_size = heap->pool_size - heap->available_size; - - /* remove next_ptr from free list */ - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("remove block: block[0x%08x], next_free 0x%08x, prev_free 0x%08x", - next_ptr, - next_ptr->next_free, - next_ptr->prev_free)); - - next_ptr->next_free->prev_free = next_ptr->prev_free; - next_ptr->prev_free->next_free = next_ptr->next_free; - next_ptr->next->prev = next_ptr->prev; - next_ptr->prev->next = next_ptr->next; - - /* build a new one on the right place */ - next_ptr = (struct rt_lwp_memheap_item *)((char *)ptr + newsize); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("new free block: block[0x%08x] nextm[0x%08x] prevm[0x%08x]", - next_ptr, - next_ptr->next, - next_ptr->prev)); - - /* mark the new block as a memory block and freed. */ - next_ptr->magic = RT_MEMHEAP_MAGIC; - - /* put the pool pointer into the new block. */ - next_ptr->pool_ptr = heap; - - next_ptr->prev = header_ptr; - next_ptr->next = header_ptr->next; - header_ptr->next->prev = next_ptr; - header_ptr->next = next_ptr; - - /* insert next_ptr to free list */ - next_ptr->next_free = heap->free_list->next_free; - next_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = next_ptr; - heap->free_list->next_free = next_ptr; - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new ptr: next_free 0x%08x, prev_free 0x%08x", - next_ptr->next_free, - next_ptr->prev_free)); - - /* release lock */ - rt_sem_release(&(heap->lock)); - - return ptr; - } - } - - /* release lock */ - rt_sem_release(&(heap->lock)); - - /* re-allocate a memory block */ - new_ptr = (void *)rt_lwp_memheap_alloc(heap, newsize); - if (new_ptr != RT_NULL) - { - rt_memcpy(new_ptr, ptr, oldsize < newsize ? oldsize : newsize); - rt_lwp_memheap_free(ptr); - } - - return new_ptr; - } - - /* don't split when there is less than one node space left */ - if (newsize + RT_MEMHEAP_SIZE + RT_MEMHEAP_MINIALLOC >= oldsize) - return ptr; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - - return RT_NULL; - } - - /* split the block. */ - new_ptr = (struct rt_lwp_memheap_item *) - (((rt_uint8_t *)header_ptr) + newsize + RT_MEMHEAP_SIZE); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("split: block[0x%08x] nextm[0x%08x] prevm[0x%08x] to new[0x%08x]\n", - header_ptr, - header_ptr->next, - header_ptr->prev, - new_ptr)); - - /* mark the new block as a memory block and freed. */ - new_ptr->magic = RT_MEMHEAP_MAGIC; - /* put the pool pointer into the new block. */ - new_ptr->pool_ptr = heap; - - /* break down the block list */ - new_ptr->prev = header_ptr; - new_ptr->next = header_ptr->next; - header_ptr->next->prev = new_ptr; - header_ptr->next = new_ptr; - - /* determine if the block can be merged with the next neighbor. */ - if (!RT_MEMHEAP_IS_USED(new_ptr->next)) - { - struct rt_lwp_memheap_item *free_ptr; - - /* merge block with next neighbor. */ - free_ptr = new_ptr->next; - heap->available_size = heap->available_size - MEMITEM_SIZE(free_ptr); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("merge: right node 0x%08x, next_free 0x%08x, prev_free 0x%08x\n", - header_ptr, header_ptr->next_free, header_ptr->prev_free)); - - free_ptr->next->prev = new_ptr; - new_ptr->next = free_ptr->next; - - /* remove free ptr from free list */ - free_ptr->next_free->prev_free = free_ptr->prev_free; - free_ptr->prev_free->next_free = free_ptr->next_free; - } - - /* insert the split block to free list */ - new_ptr->next_free = heap->free_list->next_free; - new_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = new_ptr; - heap->free_list->next_free = new_ptr; - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new free ptr: next_free 0x%08x, prev_free 0x%08x\n", - new_ptr->next_free, - new_ptr->prev_free)); - - /* increment the available byte count. */ - heap->available_size = heap->available_size + MEMITEM_SIZE(new_ptr); - - /* release lock */ - rt_sem_release(&(heap->lock)); - - /* return the old memory block */ - return ptr; -} - -void rt_lwp_memheap_free(void *ptr) -{ - rt_err_t result; - struct rt_lwp_memheap *heap; - struct rt_lwp_memheap_item *header_ptr, *new_ptr; - rt_uint32_t insert_header; - - /* NULL check */ - if (ptr == RT_NULL) return; - - /* set initial status as OK */ - insert_header = 1; - new_ptr = RT_NULL; - header_ptr = (struct rt_lwp_memheap_item *) - ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE); - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("free memory: memory[0x%08x], block[0x%08x]\n", - ptr, header_ptr)); - - /* check magic */ - RT_ASSERT((header_ptr->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC); - RT_ASSERT(header_ptr->magic & RT_MEMHEAP_USED); - /* check whether this block of memory has been over-written. */ - RT_ASSERT((header_ptr->next->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC); - - /* get pool ptr */ - heap = header_ptr->pool_ptr; - - /* lock memheap */ - result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); - if (result != RT_EOK) - { - rt_set_errno(result); - - return ; - } - - /* Mark the memory as available. */ - header_ptr->magic &= ~RT_MEMHEAP_USED; - /* Adjust the available number of bytes. */ - heap->available_size = heap->available_size + MEMITEM_SIZE(header_ptr); - - /* Determine if the block can be merged with the previous neighbor. */ - if (!RT_MEMHEAP_IS_USED(header_ptr->prev)) - { - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("merge: left node 0x%08x\n", - header_ptr->prev)); - - /* adjust the available number of bytes. */ - heap->available_size = heap->available_size + RT_MEMHEAP_SIZE; - - /* yes, merge block with previous neighbor. */ - (header_ptr->prev)->next = header_ptr->next; - (header_ptr->next)->prev = header_ptr->prev; - - /* move header pointer to previous. */ - header_ptr = header_ptr->prev; - /* don't insert header to free list */ - insert_header = 0; - } - - /* determine if the block can be merged with the next neighbor. */ - if (!RT_MEMHEAP_IS_USED(header_ptr->next)) - { - /* adjust the available number of bytes. */ - heap->available_size = heap->available_size + RT_MEMHEAP_SIZE; - - /* merge block with next neighbor. */ - new_ptr = header_ptr->next; - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("merge: right node 0x%08x, next_free 0x%08x, prev_free 0x%08x\n", - new_ptr, new_ptr->next_free, new_ptr->prev_free)); - - new_ptr->next->prev = header_ptr; - header_ptr->next = new_ptr->next; - - /* remove new ptr from free list */ - new_ptr->next_free->prev_free = new_ptr->prev_free; - new_ptr->prev_free->next_free = new_ptr->next_free; - } - - if (insert_header) - { - /* no left merge, insert to free list */ - header_ptr->next_free = heap->free_list->next_free; - header_ptr->prev_free = heap->free_list; - heap->free_list->next_free->prev_free = header_ptr; - heap->free_list->next_free = header_ptr; - - RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, - ("insert to free list: next_free 0x%08x, prev_free 0x%08x\n", - header_ptr->next_free, header_ptr->prev_free)); - } - - /* release lock */ - rt_sem_release(&(heap->lock)); -} - -rt_bool_t rt_lwp_memheap_is_empty(struct rt_lwp_memheap *memheap) -{ - RT_ASSERT(memheap != RT_NULL); - - return (memheap->available_size + 2 * sizeof(struct rt_lwp_memheap_item)) == memheap->pool_size; -} - -rt_bool_t rt_lwp_memheap_unavailable_size_get(void) -{ - return 2 * RT_MEMHEAP_SIZE + 3; -} diff --git a/components/lwp/lwp_memheap.h b/components/lwp/lwp_memheap.h deleted file mode 100644 index 064238585c..0000000000 --- a/components/lwp/lwp_memheap.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * File : lwp_memheap.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -#ifndef __LWP_MEMHEAP_H__ -#define __LWP_MEMHEAP_H__ - -#include -#include - -/** - * memory item on the heap - */ -struct rt_lwp_memheap_item -{ - rt_uint32_t magic; /**< magic number for memheap */ - struct rt_lwp_memheap *pool_ptr; /**< point of pool */ - - struct rt_lwp_memheap_item *next; /**< next memheap item */ - struct rt_lwp_memheap_item *prev; /**< prev memheap item */ - - struct rt_lwp_memheap_item *next_free; /**< next free memheap item */ - struct rt_lwp_memheap_item *prev_free; /**< prev free memheap item */ -}; - -/** - * Base structure of memory heap object - */ -struct rt_lwp_memheap -{ - struct rt_object parent; /**< inherit from rt_object */ - - void *start_addr; /**< pool start address and size */ - - rt_uint32_t pool_size; /**< pool size */ - rt_uint32_t available_size; /**< available size */ - rt_uint32_t max_used_size; /**< maximum allocated size */ - - struct rt_lwp_memheap_item *block_list; /**< used block list */ - struct rt_lwp_memheap_item *free_list; /**< free block list */ - struct rt_lwp_memheap_item free_header; /**< free block list header */ - - struct rt_semaphore lock; /**< semaphore lock */ - - rt_list_t mlist; -}; - -extern rt_err_t rt_lwp_memheap_init(struct rt_lwp_memheap *memheap, const char *name, void *start_addr, rt_uint32_t size); -extern void *rt_lwp_memheap_alloc(struct rt_lwp_memheap *heap, rt_uint32_t size); -extern void rt_lwp_memheap_free(void *ptr); -extern void *rt_lwp_memheap_realloc(struct rt_lwp_memheap *heap, void *ptr, rt_size_t newsize); -extern rt_bool_t rt_lwp_memheap_is_empty(struct rt_lwp_memheap *memheap); -extern rt_bool_t rt_lwp_memheap_unavailable_size_get(void); - -#endif diff --git a/components/lwp/lwp_syscall.c b/components/lwp/lwp_syscall.c deleted file mode 100644 index 0150e50b62..0000000000 --- a/components/lwp/lwp_syscall.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * File : lwp_syscall.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - */ - -/* RT-Thread System call */ -#include -#include -#include - -#include -#include - -#if (defined(RT_USING_SAL) && defined(SAL_USING_POSIX)) -#include - -#define SYSCALL_NET(f) (f) -#else -#define SYSCALL_NET(f) (sys_notimpl) -#endif - -#define DBG_ENABLE -#define DBG_SECTION_NAME "LWP_CALL" -#define DBG_COLOR -#define DBG_LEVEL DBG_WARNING -#include - -/* thread/process */ -void sys_exit(int value) -{ - /* TODO: handle the return_value */ - - dbg_log(DBG_LOG, "enter sys_exit\n"); - - rt_thread_delete(rt_thread_self()); - - rt_schedule(); - - return; -} - -/* syscall: "read" ret: "ssize_t" args: "int" "void *" "size_t" */ -ssize_t sys_read(int fd, void *buf, size_t nbyte) -{ - return read(fd, buf, nbyte); -} - -/* syscall: "write" ret: "ssize_t" args: "int" "const void *" "size_t" */ -ssize_t sys_write(int fd, const void *buf, size_t nbyte) -{ - return write(fd, buf, nbyte); -} - -/* syscall: "lseek" ret: "off_t" args: "int" "off_t" "int" */ -off_t sys_lseek(int fd, off_t offset, int whence) -{ - return lseek(fd, offset, whence); -} - -/* syscall: "open" ret: "int" args: "const char *" "int" "..." */ -int sys_open(const char *name, int mode, ...) -{ - return open(name, mode, 0); -} - -/* syscall: "close" ret: "int" args: "int" */ -int sys_close(int fd) -{ - return close(fd); -} - -/* syscall: "ioctl" ret: "int" args: "int" "u_long" "..." */ -int sys_ioctl(int fd, unsigned long cmd, void* data) -{ - return ioctl(fd, cmd, data); -} - -/* syscall: "nanosleep" ret: "int" args: "const struct timespec *" "struct timespec *" */ -int sys_nanosleep(const struct timespec *rqtp, struct timespec *rmtp) -{ - rt_tick_t tick; - - dbg_log(DBG_LOG, "sys_nanosleep\n"); - - tick = rqtp->tv_sec * RT_TICK_PER_SECOND + (rqtp->tv_nsec * RT_TICK_PER_SECOND)/ 1000000000; - rt_thread_delay(tick); - - if (rmtp) - { - tick = rt_tick_get() - tick; - /* get the passed time */ - rmtp->tv_sec = tick/RT_TICK_PER_SECOND; - rmtp->tv_nsec = (tick%RT_TICK_PER_SECOND) * (1000000000/RT_TICK_PER_SECOND); - } - - return 0; -} - -/* syscall: "getpriority" ret: "int" args: "int" "id_t" */ -int sys_getpriority(int which, id_t who) -{ - if (which == PRIO_PROCESS) - { - rt_thread_t tid; - - tid = rt_thread_self(); - if (who == (id_t)tid || who == 0xff) - { - return tid->current_priority; - } - } - - return 0xff; -} - -/* syscall: "setpriority" ret: "int" args: "int" "id_t" "int" */ -int sys_setpriority(int which, id_t who, int prio) -{ - if (which == PRIO_PROCESS) - { - rt_thread_t tid; - - tid = rt_thread_self(); - if ((who == (id_t)tid || who == 0xff) && (prio >= 0 && prio < RT_THREAD_PRIORITY_MAX)) - { - rt_thread_control(tid, RT_THREAD_CTRL_CHANGE_PRIORITY, &prio); - return 0; - } - } - - return -1; -} - -/* syscall: "gettimeofday" ret: "int" args: "struct timeval *" "struct timezone *" */ -int sys_gettimeofday(struct timeval *tp, struct timezone *tzp) -{ - if (tp) - { - tp->tv_sec = rt_tick_get() / RT_TICK_PER_SECOND; - tp->tv_usec = (rt_tick_get() % RT_TICK_PER_SECOND) * (1000000 / RT_TICK_PER_SECOND); - } - - return 0; -} - -/* syscall: "settimeofday" ret: "int" args: "const struct timeval *" "const struct timezone *" */ -int sys_settimeofday(const struct timeval *tv, const struct timezone *tzp) -{ - return 0; -} - -/* syscall: "msgget" ret: "int" args: "key_t" "int" */ -int sys_msgget(key_t key, int msgflg) -{ - return -1; -} - -/* syscall: "msgsnd" ret: "int" args: "int" "const void *" "size_t" "int" */ -int sys_msgsend(int msqid, const void *msgp, size_t msgsz, int msgflg) -{ - return -1; -} - -/* syscall: "msgrcv" ret: "int" args: "int" "void *" "size_t" "long" "int" */ -int sys_msgrcv(int msqid, void *msgp, size_t msgsz, long msgtyp, int msgflg) -{ - return -1; -} - -/* syscall: "sys_log" ret: "int" args: "const char*" "size" */ -int sys_log(const char* log, int size) -{ - rt_device_t console = rt_console_get_device(); - - if (console) rt_device_write(console, -1, log, size); - - return 0; -} - -void *sys_malloc(size_t size) -{ - return rt_lwp_mem_malloc(size); -} - -void sys_free(void *addr) -{ - rt_lwp_mem_free(addr); -} - -void *sys_realloc(void *rmem, size_t newsize) -{ - return rt_lwp_mem_realloc(rmem, newsize); -} - -int sys_fstat(int file, struct stat *buf) -{ - return fstat(file, buf); -} - -int sys_notimpl(void) -{ - return -ENOSYS; -} - -const static void* func_table[] = -{ - (void *)sys_exit, // 0x01 - (void *)sys_read, // 0x02 - (void *)sys_write, // 0x03 - (void *)sys_lseek, // 0x04 - (void *)sys_open, // 0x05 - (void *)sys_close, // 0x06 - (void *)sys_ioctl, // 0x07 - - (void *)sys_nanosleep, // 0x08 - - (void *)sys_getpriority, // 0x09 - (void *)sys_setpriority, // 0x0a - - (void *)sys_gettimeofday, // 0x0b - (void *)sys_settimeofday, // 0x0c - - (void *)sys_malloc, // 0x0d - (void *)sys_free, // 0x0e - (void *)sys_realloc, //0x0f - (void *)sys_fstat, // 0x10 - poll, // 0x11 - - SYSCALL_NET(accept), // 0x12 - SYSCALL_NET(bind), // 0x13 - SYSCALL_NET(shutdown), // 0x14 - SYSCALL_NET(getpeername),// 0x15 - SYSCALL_NET(getsockname),// 0x16 - SYSCALL_NET(getsockopt), // 0x17 - SYSCALL_NET(setsockopt), // 0x18 - SYSCALL_NET(connect), // 0x19 - SYSCALL_NET(listen), // 0x1a - SYSCALL_NET(recv), // 0x1b - SYSCALL_NET(recvfrom), // 0x1c - SYSCALL_NET(send), // 0x1d - SYSCALL_NET(sendto), // 0x1e - SYSCALL_NET(socket), // 0x1f - - select, // 0x20 -}; - -const void *lwp_get_sys_api(rt_uint32_t number) -{ - const void *func = sys_notimpl; - - if (number == 0xff) - { - func = (void *)sys_log; - } - else - { - number -= 1; - if (number < sizeof(func_table)/sizeof(func_table[0])) - { - func = func_table[number]; - } - } - - return func; -} diff --git a/components/lwp/lwp_syscall.h b/components/lwp/lwp_syscall.h deleted file mode 100644 index eba25c40e3..0000000000 --- a/components/lwp/lwp_syscall.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * File : lwp_syscall.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2006-03-18 Bernard the first version - * 2006-04-25 Bernard add rt_hw_context_switch_interrupt declaration - * 2006-09-24 Bernard add rt_hw_context_switch_to declaration - * 2012-12-29 Bernard add rt_hw_exception_install declaration - * 2017-10-17 Hichard add some micros - */ - -#ifndef __LWP_SYSCALL_H__ -#define __LWP_SYSCALL_H__ - -#include -#include -#include -#include -#include - -typedef long suseconds_t; /* microseconds (signed) */ -typedef long key_t; /* IPC key (for Sys V IPC) */ -typedef uint32_t id_t; /* may contain pid, uid or gid */ - -/* - * Process priority specifications to get/setpriority. - */ -#define PRIO_MIN (-20) -#define PRIO_MAX 20 - -#define PRIO_PROCESS 0 /* only support lwp process */ -#define PRIO_PGRP 1 -#define PRIO_USER 2 - -#define TIMEVAL_TO_TIMESPEC(tv, ts) { \ - (ts)->tv_sec = (tv)->tv_sec; \ - (ts)->tv_nsec = (tv)->tv_usec * 1000; \ -} -#define TIMESPEC_TO_TIMEVAL(tv, ts) { \ - (tv)->tv_sec = (ts)->tv_sec; \ - (tv)->tv_usec = (ts)->tv_nsec / 1000; \ -} - -void sys_exit(int value); -ssize_t sys_read(int fd, void *buf, size_t nbyte); -ssize_t sys_write(int fd, const void *buf, size_t nbyte); -off_t sys_lseek(int fd, off_t offset, int whence); -int sys_open(const char *name, int mode, ...); -int sys_close(int fd); -int sys_nanosleep(const struct timespec *rqtp, struct timespec *rmtp); -int sys_getpriority(int which, id_t who); -int sys_setpriority(int which, id_t who, int prio); -int sys_gettimeofday(struct timeval *tp, struct timezone *tzp); -int sys_settimeofday(const struct timeval *tv, const struct timezone *tzp); -int sys_msgget(key_t key, int msgflg); -int sys_msgsend(int msqid, const void *msgp, size_t msgsz, int msgflg); -int sys_msgrcv(int msqid, void *msgp, size_t msgsz, long msgtyp, int msgflg); - -int sys_log(const char* log, int size); - -#endif diff --git a/components/net/Kconfig b/components/net/Kconfig index 97e97ca4b7..cef3ceacd3 100644 --- a/components/net/Kconfig +++ b/components/net/Kconfig @@ -5,7 +5,6 @@ menu "Socket abstraction layer" config RT_USING_SAL bool "Enable socket abstraction layer" default n - select RT_USING_DFS if RT_USING_SAL @@ -22,20 +21,34 @@ config RT_USING_SAL bool "Support AT Commands stack" default y depends on AT_USING_SOCKET + + config SAL_USING_TLS + bool "Support MbedTLS protocol" + default y + depends on PKG_USING_MBEDTLS endmenu endif config SAL_USING_POSIX bool "Enable BSD socket operated by file system API" + default n + select RT_USING_DFS select RT_USING_LIBC select RT_USING_POSIX - default n help Let BSD socket operated by file system API, such as read/write and involveed in select/poll POSIX APIs. + + if !SAL_USING_POSIX + + config SAL_SOCKETS_NUM + int "the maximum number of sockets" + default 16 + + endif config SAL_PROTO_FAMILIES_NUM - int "the number of protocol family" + int "the maximum number of protocol families" default 4 endif @@ -60,9 +73,12 @@ config RT_USING_LWIP config RT_USING_LWIP202 bool "lwIP v2.0.2" + + config RT_USING_LWIP210 + bool "lwIP v2.1.0" endchoice - if RT_USING_LWIP202 + if (RT_USING_LWIP210 || RT_USING_LWIP202) config RT_USING_LWIP_IPV6 bool "IPV6 protocol" default n diff --git a/components/net/SConscript b/components/net/SConscript index b930821bd8..0c59cd1c3c 100644 --- a/components/net/SConscript +++ b/components/net/SConscript @@ -8,7 +8,7 @@ cwd = GetCurrentDir() list = os.listdir(cwd) # the default version of LWIP is 2.0.2 -if not GetDepend('RT_USING_LWIP132') and not GetDepend('RT_USING_LWIP141') and not GetDepend('RT_USING_LWIP202'): +if not GetDepend('RT_USING_LWIP141') and not GetDepend('RT_USING_LWIP202') and not GetDepend('RT_USING_LWIP210'): AddDepend('RT_USING_LWIP202') for d in list: diff --git a/components/net/at/Kconfig b/components/net/at/Kconfig index dde3dda5b3..a1f1b8199d 100644 --- a/components/net/at/Kconfig +++ b/components/net/at/Kconfig @@ -51,29 +51,38 @@ if RT_USING_AT if AT_USING_CLIENT - config AT_CLIENT_DEVICE - string "Client device name" - default "uart2" - - config AT_CLIENT_RECV_BUFF_LEN - int "The maximum length of client data accepted" - default 512 - + config AT_CLIENT_NUM_MAX + int "The maximum number of supported clients" + default 1 + range 1 65535 + config AT_USING_SOCKET - bool "Provide similar BSD Socket API by AT" + bool "Enable BSD Socket API support by AT commnads" select RT_USING_LIBC + select RT_USING_SAL default n + endif - config AT_USING_CLI - bool "Enable command-line interface for AT commands" - default y - depends on FINSH_USING_MSH - - config AT_PRINT_RAW_CMD - bool "Enable print RAW format AT command communication data" - default n + if AT_USING_SERVER || AT_USING_CLIENT + config AT_USING_CLI + bool "Enable CLI(Command-Line Interface) for AT commands" + default y + depends on FINSH_USING_MSH + + config AT_PRINT_RAW_CMD + bool "Enable print RAW format AT command communication data" + default n + + endif + + config AT_SW_VERSION_NUM + hex + default 0x10200 + help + sfotware module version number + endif endmenu diff --git a/components/net/at/SConscript b/components/net/at/SConscript index 2a25aaeb42..81df9738b8 100644 --- a/components/net/at/SConscript +++ b/components/net/at/SConscript @@ -3,10 +3,10 @@ from building import * cwd = GetCurrentDir() path = [cwd + '/include'] -src = Split(''' -src/at_cli.c -src/at_utils.c -''') +src = Glob('src/at_utils.c') + +if GetDepend(['AT_USING_CLI']): + src += Glob('src/at_cli.c') if GetDepend(['AT_USING_SERVER']): src += Split(''' diff --git a/components/net/at/at_socket/at_socket.c b/components/net/at/at_socket/at_socket.c index 3580df957b..01646f0d89 100644 --- a/components/net/at/at_socket/at_socket.c +++ b/components/net/at/at_socket/at_socket.c @@ -1,21 +1,7 @@ /* - * File : at_socket.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,11 +20,10 @@ #include #endif -#ifdef DBG_SECTION_NAME -#undef DBG_SECTION_NAME -#define DBG_SECTION_NAME "[AT_SOC] " -#endif +#define LOG_TAG "at.skt" +#include +#ifdef AT_USING_SOCKET #define HTONS_PORT(x) ((((x) & 0x00ffUL) << 8) | (((x) & 0xff00UL) >> 8)) #define NIPQUAD(addr) \ @@ -47,7 +32,7 @@ ((unsigned char *)&addr)[2], \ ((unsigned char *)&addr)[3] -#ifdef AT_DEVICE_NOT_SELECTED +#if !defined(AT_DEVICE_SOCKETS_NUM) || defined(AT_DEVICE_NOT_SELECTED) #error The AT socket device is not selected, please select it through the env menuconfig. #endif @@ -89,7 +74,7 @@ static size_t at_recvpkt_put(rt_slist_t *rlist, const char *ptr, size_t length) at_recv_pkt_t pkt; pkt = (at_recv_pkt_t) rt_calloc(1, sizeof(struct at_recv_pkt)); - if (!pkt) + if (pkt == RT_NULL) { LOG_E("No memory for receive packet table!"); return 0; @@ -201,7 +186,7 @@ static void at_do_event_changes(struct at_socket *sock, at_event_t event, rt_boo { if (is_plus) { - sock->sendevent++; + sock->sendevent = 1; #ifdef SAL_USING_POSIX rt_wqueue_wakeup(&sock->wait_head, (void*) POLLOUT); @@ -210,7 +195,7 @@ static void at_do_event_changes(struct at_socket *sock, at_event_t event, rt_boo } else if (sock->sendevent) { - sock->sendevent --; + sock->sendevent = 0; } break; } @@ -249,7 +234,31 @@ static void at_do_event_changes(struct at_socket *sock, at_event_t event, rt_boo break; } default: - LOG_E("Not supported event (%d)", event) + LOG_E("Not supported event (%d)", event); + } +} + +static void at_do_event_clean(struct at_socket *sock, at_event_t event) +{ + switch (event) + { + case AT_EVENT_SEND: + { + sock->sendevent = 0; + break; + } + case AT_EVENT_RECV: + { + sock->rcvevent = 0; + break; + } + case AT_EVENT_ERROR: + { + sock->errevent = 0; + break; + } + default: + LOG_E("Not supported event (%d)", event); } } @@ -340,7 +349,7 @@ int at_socket(int domain, int type, int protocol) /* allocate and initialize a new AT socket */ sock = alloc_socket(); - if(!sock) + if(sock == RT_NULL) { LOG_E("Allocate a new AT socket failed!"); return RT_NULL; @@ -381,14 +390,19 @@ int at_closesocket(int socket) struct at_socket *sock; enum at_socket_state last_state; - if (!at_dev_ops) + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); return -1; } - if ((sock = at_get_socket(socket)) == RT_NULL) + /* deal with TCP server actively disconnect */ + rt_thread_delay(rt_tick_from_millisecond(100)); + + sock = at_get_socket(socket); + if (sock == RT_NULL) + { return -1; + } last_state = sock->state; @@ -397,44 +411,54 @@ int at_closesocket(int socket) if (last_state == AT_SOCKET_CONNECT) { - if (at_dev_ops->close(socket) != 0) + if (at_dev_ops->at_closesocket(socket) != 0) { LOG_E("AT socket (%d) closesocket failed!", socket); + free_socket(sock); + return -1; } } - return free_socket(sock); + free_socket(sock); + return 0; } int at_shutdown(int socket, int how) { struct at_socket *sock; - if (!at_dev_ops) + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); return -1; } - if ((sock = at_get_socket(socket)) == RT_NULL) + sock = at_get_socket(socket); + if (sock == RT_NULL) + { return -1; + } if (sock->state == AT_SOCKET_CONNECT) { - if (at_dev_ops->close(socket) != 0) + if (at_dev_ops->at_closesocket(socket) != 0) { LOG_E("AT socket (%d) shutdown failed!", socket); + free_socket(sock); + return -1; } } - return free_socket(sock); + free_socket(sock); + return 0; } int at_bind(int socket, const struct sockaddr *name, socklen_t namelen) { if (at_get_socket(socket) == RT_NULL) + { return -1; + } return 0; } @@ -470,7 +494,8 @@ static void at_recv_notice_cb(int socket, at_socket_evt_t event, const char *buf RT_ASSERT(bfsz); RT_ASSERT(event == AT_SOCKET_EVT_RECV); - if ((sock = at_get_socket(socket)) == RT_NULL) + sock = at_get_socket(socket); + if (sock == RT_NULL) return ; /* put receive buffer to receiver packet list */ @@ -498,6 +523,7 @@ static void at_closed_notice_cb(int socket, at_socket_evt_t event, const char *b sock->state = AT_SOCKET_CLOSED; rt_sem_release(sock->recv_notice); } + int at_connect(int socket, const struct sockaddr *name, socklen_t namelen) { struct at_socket *sock; @@ -506,14 +532,13 @@ int at_connect(int socket, const struct sockaddr *name, socklen_t namelen) char ipstr[16] = { 0 }; int result = 0; - if (!at_dev_ops) + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); return -1; } sock = at_get_socket(socket); - if (!sock) + if (sock == RT_NULL) { result = -1; goto __exit; @@ -530,7 +555,7 @@ int at_connect(int socket, const struct sockaddr *name, socklen_t namelen) socketaddr_to_ipaddr_port(name, &remote_addr, &remote_port); ipaddr_to_ipstr(name, ipstr); - if (at_dev_ops->connect(socket, ipstr, remote_port, sock->type, RT_TRUE) < 0) + if (at_dev_ops->at_connect(socket, ipstr, remote_port, sock->type, RT_TRUE) < 0) { LOG_E("AT socket(%d) connect failed!", socket); result = -1; @@ -540,8 +565,8 @@ int at_connect(int socket, const struct sockaddr *name, socklen_t namelen) sock->state = AT_SOCKET_CONNECT; /* set AT socket receive data callback function */ - at_dev_ops->set_event_cb(AT_SOCKET_EVT_RECV, at_recv_notice_cb); - at_dev_ops->set_event_cb(AT_SOCKET_EVT_CLOSED, at_closed_notice_cb); + at_dev_ops->at_set_event_cb(AT_SOCKET_EVT_RECV, at_recv_notice_cb); + at_dev_ops->at_set_event_cb(AT_SOCKET_EVT_CLOSED, at_closed_notice_cb); __exit: @@ -550,6 +575,8 @@ __exit: at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); } + at_do_event_changes(sock, AT_EVENT_SEND, RT_TRUE); + return result; } @@ -560,21 +587,19 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f int result = 0; size_t recv_len = 0; - if (!mem || len == 0) + if (mem == RT_NULL || len == 0) { LOG_E("AT recvfrom input data or length error!"); - result = -1; - goto __exit; + return -1; } - if (!at_dev_ops) + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); return -1; } sock = at_get_socket(socket); - if (!sock) + if (sock == RT_NULL) { result = -1; goto __exit; @@ -590,7 +615,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f socketaddr_to_ipaddr_port(from, &remote_addr, &remote_port); ipaddr_to_ipstr(from, ipstr); - if (at_dev_ops->connect(socket, ipstr, remote_port, sock->type, RT_TRUE) < 0) + if (at_dev_ops->at_connect(socket, ipstr, remote_port, sock->type, RT_TRUE) < 0) { LOG_E("AT socket UDP connect failed!"); result = -1; @@ -599,7 +624,13 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f sock->state = AT_SOCKET_CONNECT; } - if (sock->state != AT_SOCKET_CONNECT) + /* socket passively closed, receive function return 0 */ + if (sock->state == AT_SOCKET_CLOSED) + { + result = 0; + goto __exit; + } + else if (sock->state != AT_SOCKET_CONNECT) { LOG_E("received data error, current socket (%d) state (%d) is error.", socket, sock->state); result = -1; @@ -626,6 +657,10 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f { timeout = RT_WAITING_FOREVER; } + else + { + timeout = rt_tick_from_millisecond(timeout); + } while (1) { @@ -633,6 +668,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f if (rt_sem_take(sock->recv_notice, timeout) < 0) { LOG_E("AT socket (%d) receive timeout (%d)!", socket, timeout); + errno = EAGAIN; result = -1; goto __exit; } @@ -652,7 +688,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f else { LOG_D("received data exit, current socket (%d) is closed by remote.", socket); - result = -1; + result = 0; goto __exit; } } @@ -660,17 +696,23 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f __exit: - if (result < 0) + if (recv_len > 0) { - at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); + result = recv_len; + at_do_event_changes(sock, AT_EVENT_RECV, RT_FALSE); + errno = 0; + if (!rt_slist_isempty(&sock->recvpkt_list)) + { + at_do_event_changes(sock, AT_EVENT_RECV, RT_TRUE); + } + else + { + at_do_event_clean(sock, AT_EVENT_RECV); + } } else { - result = recv_len; - if (recv_len) - { - at_do_event_changes(sock, AT_EVENT_RECV, RT_FALSE); - } + at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); } return result; @@ -686,14 +728,13 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct struct at_socket *sock; int len, result = 0; - if (!at_dev_ops) + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); result = -1; goto __exit; } - if (!data || size == 0) + if (data == RT_NULL || size == 0) { LOG_E("AT sendto input data or size error!"); result = -1; @@ -701,7 +742,7 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct } sock = at_get_socket(socket); - if (!sock) + if (sock == RT_NULL) { result = -1; goto __exit; @@ -717,7 +758,7 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct goto __exit; } - if ((len = at_dev_ops->send(sock->socket, (const char *) data, size, sock->type)) < 0) + if ((len = at_dev_ops->at_send(sock->socket, (const char *) data, size, sock->type)) < 0) { result = -1; goto __exit; @@ -734,16 +775,19 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct socketaddr_to_ipaddr_port(to, &remote_addr, &remote_port); ipaddr_to_ipstr(to, ipstr); - if (at_dev_ops->connect(socket, ipstr, remote_port, sock->type, RT_TRUE) < 0) + if (at_dev_ops->at_connect(socket, ipstr, remote_port, sock->type, RT_TRUE) < 0) { LOG_E("AT socket (%d) UDP connect failed!", socket); result = -1; goto __exit; } sock->state = AT_SOCKET_CONNECT; + /* set AT socket receive data callback function */ + at_dev_ops->at_set_event_cb(AT_SOCKET_EVT_RECV, at_recv_notice_cb); + at_dev_ops->at_set_event_cb(AT_SOCKET_EVT_CLOSED, at_closed_notice_cb); } - if ((len = at_dev_ops->send(sock->socket, (char *) data, size, sock->type)) < 0) + if ((len = at_dev_ops->at_send(sock->socket, (char *) data, size, sock->type)) < 0) { result = -1; goto __exit; @@ -780,14 +824,14 @@ int at_getsockopt(int socket, int level, int optname, void *optval, socklen_t *o struct at_socket *sock; int32_t timeout; - if (!optval || !optlen) + if (optval == RT_NULL || optlen == RT_NULL) { LOG_E("AT getsocketopt input option value or option length error!"); return -1; } sock = at_get_socket(socket); - if (!sock) + if (sock == RT_NULL) { return -1; } @@ -827,14 +871,14 @@ int at_setsockopt(int socket, int level, int optname, const void *optval, sockle { struct at_socket *sock; - if (!optval) + if (optval == RT_NULL) { LOG_E("AT setsockopt input option value error!"); return -1; } sock = at_get_socket(socket); - if (!sock) + if (sock == RT_NULL) { return -1; } @@ -923,15 +967,14 @@ struct hostent *at_gethostbyname(const char *name) static char s_hostname[DNS_MAX_NAME_LENGTH + 1]; size_t idx = 0; - if (!name) + if (name == RT_NULL) { LOG_E("AT gethostbyname input name error!"); return RT_NULL; } - if (!at_dev_ops) + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); return RT_NULL; } @@ -939,7 +982,7 @@ struct hostent *at_gethostbyname(const char *name) if (idx < strlen(name)) { - if (at_dev_ops->domain_resolve(name, ipstr) < 0) + if (at_dev_ops->at_domain_resolve(name, ipstr) < 0) { LOG_E("AT domain (%s) resolve error!", name); return RT_NULL; @@ -983,12 +1026,13 @@ int at_getaddrinfo(const char *nodename, const char *servname, { return EAI_FAIL; } - if (!at_dev_ops) + *res = RT_NULL; + + if (at_dev_ops == RT_NULL) { - LOG_E("Please register AT device socket options first!"); return EAI_FAIL; } - *res = RT_NULL; + if ((nodename == RT_NULL) && (servname == RT_NULL)) { return EAI_NONAME; @@ -1038,7 +1082,7 @@ int at_getaddrinfo(const char *nodename, const char *servname, if(idx < strlen(nodename)) { - if (at_dev_ops->domain_resolve((char *) nodename, ip_str) != 0) + if (at_dev_ops->at_domain_resolve((char *) nodename, ip_str) != 0) { return EAI_FAIL; } @@ -1085,10 +1129,10 @@ int at_getaddrinfo(const char *nodename, const char *servname, struct sockaddr_in *sa4 = (struct sockaddr_in *) sa; /* set up sockaddr */ sa4->sin_addr.s_addr = addr.u_addr.ip4.addr; - sa4->sin_family = AF_AT; + sa4->sin_family = AF_INET; sa4->sin_len = sizeof(struct sockaddr_in); sa4->sin_port = htons((u16_t )port_nr); - ai->ai_family = AF_AT; + ai->ai_family = AF_INET; /* set up addrinfo */ if (hints != RT_NULL) @@ -1114,19 +1158,25 @@ int at_getaddrinfo(const char *nodename, const char *servname, void at_freeaddrinfo(struct addrinfo *ai) { - if (ai != RT_NULL) + struct addrinfo *next; + + while (ai != NULL) { + next = ai->ai_next; rt_free(ai); + ai = next; } } -void at_scoket_device_register(const struct at_device_ops *ops) +void at_socket_device_register(const struct at_device_ops *ops) { RT_ASSERT(ops); - RT_ASSERT(ops->connect); - RT_ASSERT(ops->close); - RT_ASSERT(ops->send); - RT_ASSERT(ops->domain_resolve); - RT_ASSERT(ops->set_event_cb); + RT_ASSERT(ops->at_connect); + RT_ASSERT(ops->at_closesocket); + RT_ASSERT(ops->at_send); + RT_ASSERT(ops->at_domain_resolve); + RT_ASSERT(ops->at_set_event_cb); at_dev_ops = (struct at_device_ops *) ops; } + +#endif /* AT_USING_SOCKET */ diff --git a/components/net/at/at_socket/at_socket.h b/components/net/at/at_socket/at_socket.h index 612078522d..526f8d618a 100644 --- a/components/net/at/at_socket/at_socket.h +++ b/components/net/at/at_socket/at_socket.h @@ -1,21 +1,7 @@ /* - * File : at_socket.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,6 +18,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + #ifndef AT_SOCKET_RECV_BFSZ #define AT_SOCKET_RECV_BFSZ 512 #endif @@ -73,11 +63,11 @@ typedef void (* at_socket_callback)(struct at_socket *conn, int event, uint16_t /* AT device socket options function */ struct at_device_ops { - int (*connect)(int socket, char *ip, int32_t port, enum at_socket_type type, rt_bool_t is_client); - int (*close)(int socket); - int (*send)(int socket, const char *buff, size_t bfsz, enum at_socket_type type); - int (*domain_resolve)(const char *name, char ip[16]); - void (*set_event_cb)(at_socket_evt_t event, at_evt_cb_t cb); + int (*at_connect)(int socket, char *ip, int32_t port, enum at_socket_type type, rt_bool_t is_client); + int (*at_closesocket)(int socket); + int (*at_send)(int socket, const char *buff, size_t bfsz, enum at_socket_type type); + int (*at_domain_resolve)(const char *name, char ip[16]); + void (*at_set_event_cb)(at_socket_evt_t event, at_evt_cb_t cb); }; /* AT receive package list structure */ @@ -139,12 +129,12 @@ int at_getaddrinfo(const char *nodename, const char *servname, const struct addr void at_freeaddrinfo(struct addrinfo *ai); struct at_socket *at_get_socket(int socket); -void at_scoket_device_register(const struct at_device_ops *ops); +void at_socket_device_register(const struct at_device_ops *ops); #ifndef RT_USING_SAL #define socket(domain, type, protocol) at_socket(domain, type, protocol) -#define closescoket(socket) at_closesocket(socket) +#define closesocket(socket) at_closesocket(socket) #define shutdown(socket, how) at_shutdown(socket, how) #define bind(socket, name, namelen) at_bind(socket, name, namelen) #define connect(socket, name, namelen) at_connect(socket, name, namelen) @@ -160,4 +150,8 @@ void at_scoket_device_register(const struct at_device_ops *ops); #endif /* RT_USING_SAL */ +#ifdef __cplusplus +} +#endif + #endif /* AT_SOCKET_H__ */ diff --git a/components/net/at/include/at.h b/components/net/at/include/at.h index d0040f86cf..9a2630203f 100644 --- a/components/net/at/include/at.h +++ b/components/net/at/include/at.h @@ -1,25 +1,12 @@ /* - * File : at.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-03-30 chenyong first version + * 2018-08-17 chenyong multiple client support */ #ifndef __AT_H__ @@ -27,17 +14,11 @@ #include -#define AT_SW_VERSION "0.3.0" +#ifdef __cplusplus +extern "C" { +#endif -#define DBG_ENABLE -#define DBG_SECTION_NAME "AT" -#ifdef AT_DEBUG -#define DBG_LEVEL DBG_LOG -#else -#define DBG_LEVEL DBG_INFO -#endif /* AT_DEBUG */ -#define DBG_COLOR -#include +#define AT_SW_VERSION "1.2.0" #define AT_CMD_NAME_LEN 16 #define AT_END_MARK_LEN 4 @@ -46,11 +27,6 @@ #define AT_CMD_MAX_LEN 128 #endif -/* client receive idle timeout, client will wait this timeout when send data, unit: ms */ -#ifndef AT_CLIENT_RECV_IDEL -#define AT_CLIENT_RECV_IDEL 50 -#endif - /* the server AT commands new line sign */ #if defined(AT_CMD_END_MARK_CRLF) #define AT_CMD_END_MARK "\r\n" @@ -64,16 +40,13 @@ #define AT_SERVER_RECV_BUFF_LEN 256 #endif -#ifndef AT_CLIENT_RECV_BUFF_LEN -#define AT_CLIENT_RECV_BUFF_LEN 512 -#endif - #ifndef AT_SERVER_DEVICE #define AT_SERVER_DEVICE "uart2" #endif -#ifndef AT_CLIENT_DEVICE -#define AT_CLIENT_DEVICE "uart2" +/* the maximum number of supported AT clients */ +#ifndef AT_CLIENT_NUM_MAX +#define AT_CLIENT_NUM_MAX 1 #endif #define AT_CMD_EXPORT(_name_, _args_expr_, _test_, _query_, _setup_, _exec_) \ @@ -134,7 +107,6 @@ struct at_server rt_thread_t parser; void (*parser_entry)(struct at_server *server); }; - typedef struct at_server *at_server_t; #endif /* AT_USING_SERVER */ @@ -180,8 +152,10 @@ struct at_client rt_device_t device; at_status_t status; + char end_sign; - char recv_buffer[AT_CLIENT_RECV_BUFF_LEN]; + char *recv_buffer; + rt_size_t recv_bufsz; rt_size_t cur_recv_len; rt_sem_t rx_notice; rt_mutex_t lock; @@ -195,7 +169,6 @@ struct at_client rt_thread_t parser; }; - typedef struct at_client *at_client_t; #endif /* AT_USING_CLIENT */ @@ -213,20 +186,33 @@ int at_req_parse_args(const char *req_args, const char *req_expr, ...); #endif /* AT_USING_SERVER */ #ifdef AT_USING_CLIENT -/* AT client initialize and start */ -int at_client_init(void); + +/* AT client initialize and start*/ +int at_client_init(const char *dev_name, rt_size_t recv_bufsz); + +/* ========================== multiple AT client function ============================ */ + +/* get AT client object */ +at_client_t at_client_get(const char *dev_name); +at_client_t at_client_get_first(void); /* AT client wait for connection to external devices. */ -int at_client_wait_connect(rt_uint32_t timeout); +int at_client_obj_wait_connect(at_client_t client, rt_uint32_t timeout); + +/* AT client send or receive data */ +rt_size_t at_client_obj_send(at_client_t client, const char *buf, rt_size_t size); +rt_size_t at_client_obj_recv(at_client_t client, char *buf, rt_size_t size, rt_int32_t timeout); + +/* set AT client a line end sign */ +void at_obj_set_end_sign(at_client_t client, char ch); + +/* Set URC(Unsolicited Result Code) table */ +void at_obj_set_urc_table(at_client_t client, const struct at_urc * table, rt_size_t size); /* AT client send commands to AT server and waiter response */ -int at_exec_cmd(at_response_t resp, const char *cmd_expr, ...); +int at_obj_exec_cmd(at_client_t client, at_response_t resp, const char *cmd_expr, ...); -/* AT Client send or receive data */ -rt_size_t at_client_send(const char *buf, rt_size_t size); -rt_size_t at_client_recv(char *buf, rt_size_t size); - -/* AT response structure create and delete */ +/* AT response object create and delete */ at_response_t at_create_resp(rt_size_t buf_size, rt_size_t line_num, rt_int32_t timeout); void at_delete_resp(at_response_t resp); at_response_t at_resp_set_info(at_response_t resp, rt_size_t buf_size, rt_size_t line_num, rt_int32_t timeout); @@ -237,8 +223,20 @@ const char *at_resp_get_line_by_kw(at_response_t resp, const char *keyword); int at_resp_parse_line_args(at_response_t resp, rt_size_t resp_line, const char *resp_expr, ...); int at_resp_parse_line_args_by_kw(at_response_t resp, const char *keyword, const char *resp_expr, ...); -/* Set URC(Unsolicited Result Code) table */ -void at_set_urc_table(const struct at_urc * table, rt_size_t size); +/* ========================== single AT client function ============================ */ + +/** + * NOTE: These functions can be used directly when there is only one AT client. + * If there are multiple AT Client in the program, these functions can operate on the first initialized AT client. + */ + +#define at_exec_cmd(resp, ...) at_obj_exec_cmd(at_client_get_first(), resp, __VA_ARGS__) +#define at_client_wait_connect(timeout) at_client_obj_wait_connect(at_client_get_first(), timeout) +#define at_client_send(buf, size) at_client_obj_send(at_client_get_first(), buf, size) +#define at_client_recv(buf, size, timeout) at_client_obj_recv(at_client_get_first(), buf, size, timeout) +#define at_set_end_sign(ch) at_obj_set_end_sign(at_client_get_first(), ch) +#define at_set_urc_table(urc_table, table_sz) at_obj_set_urc_table(at_client_get_first(), urc_table, table_sz) + #endif /* AT_USING_CLIENT */ /* ========================== User port function ============================ */ @@ -251,4 +249,8 @@ void at_port_reset(void); void at_port_factory_reset(void); #endif +#ifdef __cplusplus +} +#endif + #endif /* __AT_H__ */ diff --git a/components/net/at/include/at_log.h b/components/net/at/include/at_log.h new file mode 100644 index 0000000000..278763d30e --- /dev/null +++ b/components/net/at/include/at_log.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-12 armink first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#define DBG_ENABLE +#define DBG_COLOR + +#ifndef LOG_TAG +#define DBG_SECTION_NAME "at" +#else +#define DBG_SECTION_NAME LOG_TAG +#endif /* LOG_TAG */ + +#ifdef AT_DEBUG +#define DBG_LEVEL DBG_LOG +#else +#define DBG_LEVEL DBG_INFO +#endif /* AT_DEBUG */ + +#include diff --git a/components/net/at/src/at_base_cmd.c b/components/net/at/src/at_base_cmd.c index b334b1dba4..b182477f9b 100644 --- a/components/net/at/src/at_base_cmd.c +++ b/components/net/at/src/at_base_cmd.c @@ -1,21 +1,7 @@ /* - * File : at_base_cmd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,6 +15,8 @@ #include +#ifdef AT_USING_SERVER + #define AT_ECHO_MODE_CLOSE 0 #define AT_ECHO_MODE_OPEN 1 @@ -129,3 +117,5 @@ static at_result_t at_uart_setup(const char *args) } AT_CMD_EXPORT("AT+UART", "=,,,,", RT_NULL, at_uart_query, at_uart_setup, RT_NULL); + +#endif /* AT_USING_SERVER */ diff --git a/components/net/at/src/at_cli.c b/components/net/at/src/at_cli.c index 804602c4dd..60e3b4d868 100644 --- a/components/net/at/src/at_cli.c +++ b/components/net/at/src/at_cli.c @@ -1,21 +1,7 @@ /* - * File : at_cli.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -76,7 +62,7 @@ void at_cli_init(void) rt_base_t int_lvl; rt_device_t console; - rt_sem_init(&console_rx_notice, "at_cli_notice", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&console_rx_notice, "cli_c", 0, RT_IPC_FLAG_FIFO); /* create RX FIFO */ console_rx_fifo = rt_ringbuffer_create(AT_CLI_FIFO_SIZE); @@ -209,14 +195,12 @@ static rt_err_t client_getchar_rx_ind(rt_device_t dev, rt_size_t size) return RT_EOK; } -static void client_cli_parser(void) +static void client_cli_parser(at_client_t client) { #define ESC_KEY 0x1B #define BACKSPACE_KEY 0x08 #define DELECT_KEY 0x7F - extern at_client_t rt_at_get_client(void); - at_client_t client = rt_at_get_client(); char ch; char cur_line[FINSH_CMD_SIZE] = { 0 }; rt_size_t cur_line_len = 0; @@ -234,10 +218,10 @@ static void client_cli_parser(void) rt_hw_interrupt_enable(int_lvl); } - rt_sem_init(&client_rx_notice, "at_cli_client_notice", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&client_rx_notice, "cli_r", 0, RT_IPC_FLAG_FIFO); client_rx_fifo = rt_ringbuffer_create(AT_CLI_FIFO_SIZE); - at_client = rt_thread_create("at_cli_client", at_client_entry, RT_NULL, 512, 8, 8); + at_client = rt_thread_create("at_cli", at_client_entry, RT_NULL, 512, 8, 8); if (client_rx_fifo && at_client) { rt_kprintf("======== Welcome to using RT-Thread AT command client cli ========\n"); @@ -261,7 +245,7 @@ static void client_cli_parser(void) if (cur_line_len) { rt_kprintf("\n"); - at_exec_cmd(RT_NULL, "%.*s", cur_line_len, cur_line); + at_obj_exec_cmd(client, RT_NULL, "%.*s", cur_line_len, cur_line); } cur_line_len = 0; } @@ -297,9 +281,10 @@ static void client_cli_parser(void) static void at(int argc, char **argv) { - if (argc < 2) + + if (argc != 2 && argc != 3) { - rt_kprintf("Please input 'at ' \n"); + rt_kprintf("Please input '' \n"); return; } @@ -311,23 +296,40 @@ static void at(int argc, char **argv) server_cli_parser(); #else rt_kprintf("Not support AT server, please check your configure!\n"); -#endif +#endif /* AT_USING_SERVER */ } else if (!strcmp(argv[1], "client")) { #ifdef AT_USING_CLIENT - client_cli_parser(); + at_client_t client = RT_NULL; + + if (argc == 2) + { + client_cli_parser(at_client_get_first()); + } + else if (argc == 3) + { + client = at_client_get(argv[2]); + if (client == RT_NULL) + { + rt_kprintf("input AT client device name(%s) error.\n", argv[2]); + } + else + { + client_cli_parser(client); + } + } #else rt_kprintf("Not support AT client, please check your configure!\n"); -#endif +#endif /* AT_USING_CLIENT */ } else { - rt_kprintf("Please input 'at ' \n"); + rt_kprintf("Please input '' \n"); } at_cli_deinit(); } -MSH_CMD_EXPORT(at, RT-Thread AT component cli: at ); +MSH_CMD_EXPORT(at, RT-Thread AT component cli: at ); #endif /* AT_USING_CLI */ diff --git a/components/net/at/src/at_client.c b/components/net/at/src/at_client.c index e2fd93e577..1f6ed66743 100644 --- a/components/net/at/src/at_client.c +++ b/components/net/at/src/at_client.c @@ -1,26 +1,13 @@ /* - * File : at_client.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-03-30 chenyong first version * 2018-04-12 chenyong add client implement + * 2018-08-17 chenyong multiple client support */ #include @@ -28,20 +15,24 @@ #include #include +#define LOG_TAG "at.clnt" +#include + +#ifdef AT_USING_CLIENT + #define AT_RESP_END_OK "OK" #define AT_RESP_END_ERROR "ERROR" #define AT_RESP_END_FAIL "FAIL" #define AT_END_CR_LF "\r\n" -static at_client_t at_client_local = RT_NULL; -static char cust_end_sign = 0; +static struct at_client at_client_table[AT_CLIENT_NUM_MAX] = { 0 }; extern rt_size_t at_vprintfln(rt_device_t device, const char *format, va_list args); extern void at_print_raw_cmd(const char *type, const char *cmd, rt_size_t size); extern const char *at_get_last_cmd(rt_size_t *cmd_size); /** - * Create response structure. + * Create response object. * * @param buf_size the maximum response buffer size * @param line_num the number of setting response lines @@ -49,7 +40,7 @@ extern const char *at_get_last_cmd(rt_size_t *cmd_size); * != 0: the response data will return when received setting lines number data * @param timeout the maximum response time * - * @return != RT_NULL: response structure + * @return != RT_NULL: response object * = RT_NULL: no memory */ at_response_t at_create_resp(rt_size_t buf_size, rt_size_t line_num, rt_int32_t timeout) @@ -57,16 +48,16 @@ at_response_t at_create_resp(rt_size_t buf_size, rt_size_t line_num, rt_int32_t at_response_t resp = RT_NULL; resp = (at_response_t) rt_calloc(1, sizeof(struct at_response)); - if (!resp) + if (resp == RT_NULL) { - LOG_E("AT create response structure failed! No memory for response structure!"); + LOG_E("AT create response object failed! No memory for response object!"); return RT_NULL; } resp->buf = (char *) rt_calloc(1, buf_size); - if (!resp->buf) + if (resp->buf == RT_NULL) { - LOG_E("AT create response structure failed! No memory for response buf structure!"); + LOG_E("AT create response object failed! No memory for response buffer!"); rt_free(resp); return RT_NULL; } @@ -80,9 +71,9 @@ at_response_t at_create_resp(rt_size_t buf_size, rt_size_t line_num, rt_int32_t } /** - * Delete and free response structure. + * Delete and free response object. * - * @param resp response structure + * @param resp response object */ void at_delete_resp(at_response_t resp) { @@ -99,28 +90,28 @@ void at_delete_resp(at_response_t resp) } /** - * Set response structure information + * Set response object information * - * @param resp response structure + * @param resp response object * @param buf_size the maximum response buffer size * @param line_num the number of setting response lines * = 0: the response data will auto return when received 'OK' or 'ERROR' * != 0: the response data will return when received setting lines number data * @param timeout the maximum response time * - * @return != RT_NULL: response structure + * @return != RT_NULL: response object * = RT_NULL: no memory */ at_response_t at_resp_set_info(at_response_t resp, rt_size_t buf_size, rt_size_t line_num, rt_int32_t timeout) { RT_ASSERT(resp); - if(resp->buf_size != buf_size) + if (resp->buf_size != buf_size) { resp->buf_size = buf_size; - resp->buf = rt_realloc(resp->buf, buf_size); - if(!resp->buf) + resp->buf = (char *) rt_realloc(resp->buf, buf_size); + if (!resp->buf) { LOG_D("No memory for realloc response buffer size(%d).", buf_size); return RT_NULL; @@ -136,7 +127,7 @@ at_response_t at_resp_set_info(at_response_t resp, rt_size_t buf_size, rt_size_t /** * Get one line AT response buffer by line number. * - * @param resp response structure + * @param resp response object * @param resp_line line number, start from '1' * * @return != RT_NULL: response line buffer @@ -174,7 +165,7 @@ const char *at_resp_get_line(at_response_t resp, rt_size_t resp_line) /** * Get one line AT response buffer by keyword * - * @param resp response structure + * @param resp response object * @param keyword query keyword * * @return != RT_NULL: response line buffer @@ -191,7 +182,7 @@ const char *at_resp_get_line_by_kw(at_response_t resp, const char *keyword) for (line_num = 1; line_num <= resp->line_counts; line_num++) { - if(strstr(resp_buf, keyword)) + if (strstr(resp_buf, keyword)) { resp_line_buf = resp_buf; @@ -207,7 +198,7 @@ const char *at_resp_get_line_by_kw(at_response_t resp, const char *keyword) /** * Get and parse AT response buffer arguments by line number. * - * @param resp response structure + * @param resp response object * @param resp_line line number, start from '1' * @param resp_expr response buffer expression * @@ -241,7 +232,7 @@ int at_resp_parse_line_args(at_response_t resp, rt_size_t resp_line, const char /** * Get and parse AT response buffer arguments by keyword. * - * @param resp response structure + * @param resp response object * @param keyword query keyword * @param resp_expr response buffer expression * @@ -275,16 +266,16 @@ int at_resp_parse_line_args_by_kw(at_response_t resp, const char *keyword, const /** * Send commands to AT server and wait response. * - * @param resp AT response structure, using RT_NULL when you don't care response + * @param client current AT client object + * @param resp AT response object, using RT_NULL when you don't care response * @param cmd_expr AT commands expression * * @return 0 : success * -1 : response status error * -2 : wait timeout */ -int at_exec_cmd(at_response_t resp, const char *cmd_expr, ...) +int at_obj_exec_cmd(at_client_t client, at_response_t resp, const char *cmd_expr, ...) { - at_client_t client = at_client_local; va_list args; rt_size_t cmd_size = 0; rt_err_t result = RT_EOK; @@ -292,6 +283,12 @@ int at_exec_cmd(at_response_t resp, const char *cmd_expr, ...) RT_ASSERT(cmd_expr); + if (client == RT_NULL) + { + LOG_E("input AT Client object is NULL, please create or get AT Client object!"); + return -RT_ERROR; + } + rt_mutex_take(client->lock, RT_WAITING_FOREVER); client->resp_status = AT_RESP_OK; @@ -301,7 +298,7 @@ int at_exec_cmd(at_response_t resp, const char *cmd_expr, ...) at_vprintfln(client->device, cmd_expr, args); va_end(args); - if (resp) + if (resp != RT_NULL) { resp->line_counts = 0; if (rt_sem_take(client->resp_notice, resp->timeout) != RT_EOK) @@ -332,23 +329,29 @@ __exit: /** * Waiting for connection to external devices. * + * @param client current AT client object * @param timeout millisecond for timeout * * @return 0 : success * -2 : timeout * -5 : no memory */ -int at_client_wait_connect(rt_uint32_t timeout) +int at_client_obj_wait_connect(at_client_t client, rt_uint32_t timeout) { rt_err_t result = RT_EOK; at_response_t resp = RT_NULL; - at_client_t client = at_client_local; rt_tick_t start_time = 0; - resp = at_create_resp(16, 0, rt_tick_from_millisecond(500)); - if (!resp) + if (client == RT_NULL) { - LOG_E("No memory for response structure!"); + LOG_E("input AT Client object is NULL, please create or get AT Client object!"); + return -RT_ERROR; + } + + resp = at_create_resp(16, 0, rt_tick_from_millisecond(500)); + if (resp == RT_NULL) + { + LOG_E("No memory for response object!"); return -RT_ENOMEM; } @@ -360,7 +363,7 @@ int at_client_wait_connect(rt_uint32_t timeout) while (1) { /* Check whether it is timeout */ - if (rt_tick_get() - start_time > timeout) + if (rt_tick_get() - start_time > rt_tick_from_millisecond(timeout)) { LOG_E("wait connect timeout (%d millisecond)!", timeout); result = -RT_ETIMEOUT; @@ -389,60 +392,85 @@ int at_client_wait_connect(rt_uint32_t timeout) /** * Send data to AT server, send data don't have end sign(eg: \r\n). * + * @param client current AT client object * @param buf send data buffer * @param size send fixed data size * - * @return send data size + * @return >0: send data size + * =0: send failed */ -rt_size_t at_client_send(const char *buf, rt_size_t size) +rt_size_t at_client_obj_send(at_client_t client, const char *buf, rt_size_t size) { - at_client_t client = at_client_local; - RT_ASSERT(buf); + if (client == RT_NULL) + { + LOG_E("input AT Client object is NULL, please create or get AT Client object!"); + return 0; + } + #ifdef AT_PRINT_RAW_CMD at_print_raw_cmd("send", buf, size); #endif return rt_device_write(client->device, 0, buf, size); - } -static char at_client_getchar(void) +static rt_err_t at_client_getchar(at_client_t client, char *ch, rt_int32_t timeout) { - char ch; + rt_err_t result = RT_EOK; - while (rt_device_read(at_client_local->device, 0, &ch, 1) == 0) + while (rt_device_read(client->device, 0, ch, 1) == 0) { - rt_sem_control(at_client_local->rx_notice, RT_IPC_CMD_RESET, RT_NULL); - rt_sem_take(at_client_local->rx_notice, RT_WAITING_FOREVER); + rt_sem_control(client->rx_notice, RT_IPC_CMD_RESET, RT_NULL); + + result = rt_sem_take(client->rx_notice, rt_tick_from_millisecond(timeout)); + if (result != RT_EOK) + { + return result; + } } - return ch; + return RT_EOK; } /** * AT client receive fixed-length data. * + * @param client current AT client object * @param buf receive data buffer * @param size receive fixed data size + * @param timeout receive data timeout (ms) * * @note this function can only be used in execution function of URC data * - * @return success receive data size + * @return >0: receive data size + * =0: receive failed */ -rt_size_t at_client_recv(char *buf, rt_size_t size) +rt_size_t at_client_obj_recv(at_client_t client, char *buf, rt_size_t size, rt_int32_t timeout) { rt_size_t read_idx = 0; + rt_err_t result = RT_EOK; char ch; RT_ASSERT(buf); + if (client == RT_NULL) + { + LOG_E("input AT Client object is NULL, please create or get AT Client object!"); + return 0; + } + while (1) { if (read_idx < size) { - ch = at_client_getchar(); + result = at_client_getchar(client, &ch, timeout); + if (result != RT_EOK) + { + LOG_E("AT Client receive failed, uart device get data error(%d)", result); + return 0; + } buf[read_idx++] = ch; } @@ -457,56 +485,115 @@ rt_size_t at_client_recv(char *buf, rt_size_t size) #endif return read_idx; - -} - -/** - * get AT client structure pointer. - * - * @return AT client structure pointer - */ -at_client_t rt_at_get_client(void) -{ - RT_ASSERT(at_client_local); - RT_ASSERT(at_client_local->status != AT_STATUS_UNINITIALIZED); - - return at_client_local; } /** * AT client set end sign. * + * @param client current AT client object * @param ch the end sign, can not be used when it is '\0' - * - * @return 0: set success */ -int at_set_end_sign(char ch) +void at_obj_set_end_sign(at_client_t client, char ch) { - cust_end_sign = ch; + if (client == RT_NULL) + { + LOG_E("input AT Client object is NULL, please create or get AT Client object!"); + return; + } - return 0; + client->end_sign = ch; } -static const struct at_urc *get_urc_obj(char *data, rt_size_t size) +/** + * set URC(Unsolicited Result Code) table + * + * @param client current AT client object + * @param table URC table + * @param size table size + */ +void at_obj_set_urc_table(at_client_t client, const struct at_urc *urc_table, rt_size_t table_sz) +{ + rt_size_t idx; + + if (client == RT_NULL) + { + LOG_E("input AT Client object is NULL, please create or get AT Client object!"); + return; + } + + for (idx = 0; idx < table_sz; idx++) + { + RT_ASSERT(urc_table[idx].cmd_prefix); + RT_ASSERT(urc_table[idx].cmd_suffix); + } + + client->urc_table = urc_table; + client->urc_table_size = table_sz; +} + +/** + * get AT client object by AT device name. + * + * @dev_name AT client device name + * + * @return AT client object + */ +at_client_t at_client_get(const char *dev_name) +{ + int idx = 0; + + RT_ASSERT(dev_name); + + for (idx = 0; idx < AT_CLIENT_NUM_MAX; idx++) + { + if (rt_strcmp(at_client_table[idx].device->parent.name, dev_name) == 0) + { + return &at_client_table[idx]; + } + } + + return RT_NULL; +} + +/** + * get first AT client object in the table. + * + * @return AT client object + */ +at_client_t at_client_get_first(void) +{ + if (at_client_table[0].device == RT_NULL) + { + return RT_NULL; + } + + return &at_client_table[0]; +} + +static const struct at_urc *get_urc_obj(at_client_t client) { rt_size_t i, prefix_len, suffix_len; - at_client_t client = at_client_local; + rt_size_t buf_sz; + char *buffer = RT_NULL; if (client->urc_table == RT_NULL) { return RT_NULL; } + buffer = client->recv_buffer; + buf_sz = client->cur_recv_len; + for (i = 0; i < client->urc_table_size; i++) { prefix_len = strlen(client->urc_table[i].cmd_prefix); suffix_len = strlen(client->urc_table[i].cmd_suffix); - if (size < prefix_len + suffix_len) + if (buf_sz < prefix_len + suffix_len) { continue; } - if ((prefix_len ? !strncmp(data, client->urc_table[i].cmd_prefix, prefix_len) : 1) - && (suffix_len ? !strncmp(data + size - suffix_len, client->urc_table[i].cmd_suffix, suffix_len) : 1)) + if ((prefix_len ? !strncmp(buffer, client->urc_table[i].cmd_prefix, prefix_len) : 1) + && (suffix_len ? !strncmp(buffer + buf_sz - suffix_len, client->urc_table[i].cmd_suffix, suffix_len) : 1)) { return &client->urc_table[i]; } @@ -515,23 +602,23 @@ static const struct at_urc *get_urc_obj(char *data, rt_size_t size) return RT_NULL; } -static int at_recv_readline(void) +static int at_recv_readline(at_client_t client) { rt_size_t read_len = 0; char ch = 0, last_ch = 0; rt_bool_t is_full = RT_FALSE; - at_client_t client = at_client_local; - memset(client->recv_buffer, 0x00, AT_CLIENT_RECV_BUFF_LEN); + memset(client->recv_buffer, 0x00, client->recv_bufsz); client->cur_recv_len = 0; while (1) { - ch = at_client_getchar(); + at_client_getchar(client, &ch, RT_WAITING_FOREVER); - if (read_len < AT_CLIENT_RECV_BUFF_LEN) + if (read_len < client->recv_bufsz) { client->recv_buffer[read_len++] = ch; + client->cur_recv_len = read_len; } else { @@ -539,17 +626,16 @@ static int at_recv_readline(void) } /* is newline or URC data */ - if ((ch == '\n' && last_ch == '\r') || (cust_end_sign != 0 && ch == cust_end_sign) - || get_urc_obj(client->recv_buffer, read_len)) + if ((ch == '\n' && last_ch == '\r') || (client->end_sign != 0 && ch == client->end_sign) + || get_urc_obj(client)) { if (is_full) { - LOG_E("read line failed. The line data length is out of buffer size(%d)!", AT_CLIENT_RECV_BUFF_LEN); - memset(client->recv_buffer, 0x00, AT_CLIENT_RECV_BUFF_LEN); + LOG_E("read line failed. The line data length is out of buffer size(%d)!", client->recv_bufsz); + memset(client->recv_buffer, 0x00, client->recv_bufsz); client->cur_recv_len = 0; return -RT_EFULL; } - client->cur_recv_len = read_len; break; } last_ch = ch; @@ -570,9 +656,9 @@ static void client_parser(at_client_t client) while(1) { - if (at_recv_readline() > 0) + if (at_recv_readline(client) > 0) { - if ((urc = get_urc_obj(client->recv_buffer, client->cur_recv_len)) != RT_NULL) + if ((urc = get_urc_obj(client)) != RT_NULL) { /* current receive is request, try to execute related operations */ if (urc->func != RT_NULL) @@ -634,149 +720,199 @@ static void client_parser(at_client_t client) static rt_err_t at_client_rx_ind(rt_device_t dev, rt_size_t size) { - if (size > 0) + int idx = 0; + + for (idx = 0; idx < AT_CLIENT_NUM_MAX; idx++) { - rt_sem_release(at_client_local->rx_notice); + if (at_client_table[idx].device == dev && size > 0) + { + rt_sem_release(at_client_table[idx].rx_notice); + } } return RT_EOK; } -/** - * Set URC(Unsolicited Result Code) table - * - * @param table URC table - * @param size table size - */ -void at_set_urc_table(const struct at_urc *table, rt_size_t size) +/* initialize the client object parameters */ +static int at_client_para_init(at_client_t client) { - rt_size_t idx; +#define AT_CLIENT_LOCK_NAME "at_c" +#define AT_CLIENT_SEM_NAME "at_cs" +#define AT_CLIENT_RESP_NAME "at_cr" +#define AT_CLIENT_THREAD_NAME "at_clnt" - for(idx = 0; idx < size; idx++) - { - RT_ASSERT(table[idx].cmd_prefix); - RT_ASSERT(table[idx].cmd_suffix); - } - - at_client_local->urc_table = table; - at_client_local->urc_table_size = size; - -} - -/** - * initialize AT client. - * - * @return 0: initialize success - * -1: initialize failed - * -5: no memory - */ -int at_client_init(void) -{ int result = RT_EOK; - rt_err_t open_result = RT_EOK; + static int at_client_num = 0; + char name[RT_NAME_MAX]; - if (at_client_local) - { - return result; - } + client->status = AT_STATUS_UNINITIALIZED; - at_client_local = (at_client_t) rt_calloc(1, sizeof(struct at_client)); - if (!at_client_local) + client->cur_recv_len = 0; + client->recv_buffer = (char *) rt_calloc(1, client->recv_bufsz); + if (client->recv_buffer == RT_NULL) { - result = -RT_ERROR; - LOG_E("AT client session initialize failed! No memory for at_client structure !"); - goto __exit; - } - - at_client_local->status = AT_STATUS_UNINITIALIZED; - at_client_local->lock = rt_mutex_create("at_lock", RT_IPC_FLAG_FIFO); - if(!at_client_local->lock) - { - LOG_E("AT client session initialize failed! at_client_recv_lock create failed!"); + LOG_E("AT client initialize failed! No memory for receive buffer."); result = -RT_ENOMEM; goto __exit; } - at_client_local->cur_recv_len = 0; - - at_client_local->rx_notice = rt_sem_create("at_client_notice", 0, RT_IPC_FLAG_FIFO); - if (!at_client_local->rx_notice) + rt_snprintf(name, RT_NAME_MAX, "%s%d", AT_CLIENT_LOCK_NAME, at_client_num); + client->lock = rt_mutex_create(name, RT_IPC_FLAG_FIFO); + if (client->lock == RT_NULL) { - LOG_E("AT client session initialize failed! at_client_notice semaphore create failed!"); + LOG_E("AT client initialize failed! at_client_recv_lock create failed!"); result = -RT_ENOMEM; goto __exit; } - at_client_local->resp_notice = rt_sem_create("at_client_resp", 0, RT_IPC_FLAG_FIFO); - if (!at_client_local->resp_notice) + rt_snprintf(name, RT_NAME_MAX, "%s%d", AT_CLIENT_SEM_NAME, at_client_num); + client->rx_notice = rt_sem_create(name, 0, RT_IPC_FLAG_FIFO); + if (client->rx_notice == RT_NULL) { - LOG_E("AT client session initialize failed! at_client_resp semaphore create failed!"); + LOG_E("AT client initialize failed! at_client_notice semaphore create failed!"); result = -RT_ENOMEM; goto __exit; } - /* Find and open command device */ - at_client_local->device = rt_device_find(AT_CLIENT_DEVICE); - if (at_client_local->device) + rt_snprintf(name, RT_NAME_MAX, "%s%d", AT_CLIENT_RESP_NAME, at_client_num); + client->resp_notice = rt_sem_create(name, 0, RT_IPC_FLAG_FIFO); + if (client->resp_notice == RT_NULL) { - RT_ASSERT(at_client_local->device->type == RT_Device_Class_Char); - - /* using DMA mode first */ - open_result = rt_device_open(at_client_local->device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_DMA_RX); - /* using interrupt mode when DMA mode not supported */ - if (open_result == -RT_EIO) - { - open_result = rt_device_open(at_client_local->device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX); - } - RT_ASSERT(open_result == RT_EOK); - - rt_device_set_rx_indicate(at_client_local->device, at_client_rx_ind); - } - else - { - LOG_E("AT client device initialize failed! Not find the device : %s.", AT_CLIENT_DEVICE); - result = -RT_ERROR; + LOG_E("AT client initialize failed! at_client_resp semaphore create failed!"); + result = -RT_ENOMEM; goto __exit; } - at_client_local->urc_table = RT_NULL; - at_client_local->urc_table_size = 0; + client->urc_table = RT_NULL; + client->urc_table_size = 0; - at_client_local->parser = rt_thread_create("at_client", - (void (*)(void *parameter))client_parser, - at_client_local, - 1024 + 512, - RT_THREAD_PRIORITY_MAX / 3 - 1, - 5); - if (at_client_local->parser == RT_NULL) + rt_snprintf(name, RT_NAME_MAX, "%s%d", AT_CLIENT_THREAD_NAME, at_client_num); + client->parser = rt_thread_create(name, + (void (*)(void *parameter))client_parser, + client, + 1024 + 512, + RT_THREAD_PRIORITY_MAX / 3 - 1, + 5); + if (client->parser == RT_NULL) { result = -RT_ENOMEM; goto __exit; } __exit: - if (!result) + if (result != RT_EOK) { - at_client_local->status = AT_STATUS_INITIALIZED; + if (client->lock) + { + rt_mutex_delete(client->lock); + } - rt_thread_startup(at_client_local->parser); + if (client->rx_notice) + { + rt_sem_delete(client->rx_notice); + } - LOG_I("RT-Thread AT client (V%s) initialize success.", AT_SW_VERSION); + if (client->resp_notice) + { + rt_sem_delete(client->resp_notice); + } + + if (client->device) + { + rt_device_close(client->device); + } + + if (client->recv_buffer) + { + rt_free(client->recv_buffer); + } + + rt_memset(client, 0x00, sizeof(struct at_client)); } else { - if (at_client_local) - { - rt_free(at_client_local); - } - - LOG_E("RT-Thread AT client (V%s) initialize failed(%d).", AT_SW_VERSION, result); + at_client_num++; } return result; } -#ifdef FINSH_USING_MSH -#include -MSH_CMD_EXPORT(at_client_init, initialize AT client); -#endif +/** + * AT client initialize. + * + * @param dev_name AT client device name + * @param recv_bufsz the maximum number of receive buffer length + * + * @return 0 : initialize success + * -1 : initialize failed + * -5 : no memory + */ +int at_client_init(const char *dev_name, rt_size_t recv_bufsz) +{ + int idx = 0; + int result = RT_EOK; + rt_err_t open_result = RT_EOK; + at_client_t client = RT_NULL; + + RT_ASSERT(dev_name); + RT_ASSERT(recv_bufsz > 0); + + for (idx = 0; idx < AT_CLIENT_NUM_MAX && at_client_table[idx].device; idx++); + + if (idx >= AT_CLIENT_NUM_MAX) + { + LOG_E("AT client initialize failed! Check the maximum number(%d) of AT client.", AT_CLIENT_NUM_MAX); + result = -RT_EFULL; + goto __exit; + } + + client = &at_client_table[idx]; + client->recv_bufsz = recv_bufsz; + + /* find and open command device */ + client->device = rt_device_find(dev_name); + if (client->device) + { + RT_ASSERT(client->device->type == RT_Device_Class_Char); + + /* using DMA mode first */ + open_result = rt_device_open(client->device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_DMA_RX); + /* using interrupt mode when DMA mode not supported */ + if (open_result == -RT_EIO) + { + open_result = rt_device_open(client->device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + } + RT_ASSERT(open_result == RT_EOK); + + rt_device_set_rx_indicate(client->device, at_client_rx_ind); + } + else + { + LOG_E("AT client initialize failed! Not find the device(%s).", dev_name); + result = -RT_ERROR; + goto __exit; + } + + result = at_client_para_init(client); + if (result != RT_EOK) + { + goto __exit; + } + +__exit: + if (result == RT_EOK) + { + client->status = AT_STATUS_INITIALIZED; + + rt_thread_startup(client->parser); + + LOG_I("AT client(V%s) on device %s initialize success.", AT_SW_VERSION, dev_name); + } + else + { + LOG_E("AT client(V%s) on device %s initialize failed(%d).", AT_SW_VERSION, dev_name, result); + } + + return result; +} +#endif /* AT_USING_CLIENT */ diff --git a/components/net/at/src/at_server.c b/components/net/at/src/at_server.c index ebb37489b0..31f1bec96f 100644 --- a/components/net/at/src/at_server.c +++ b/components/net/at/src/at_server.c @@ -1,21 +1,7 @@ /* - * File : at_server.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -30,6 +16,11 @@ #include +#define LOG_TAG "at.svr" +#include + +#ifdef AT_USING_SERVER + #define AT_CMD_CHAR_0 '0' #define AT_CMD_CHAR_9 '9' #define AT_CMD_QUESTION_MARK '?' @@ -485,7 +476,7 @@ int at_server_init(void) memset(at_server_local->recv_buffer, 0x00, AT_SERVER_RECV_BUFF_LEN); at_server_local->cur_recv_len = 0; - at_server_local->rx_notice = rt_sem_create("at_server_notice", 0, RT_IPC_FLAG_FIFO); + at_server_local->rx_notice = rt_sem_create("at_svr", 0, RT_IPC_FLAG_FIFO); if (!at_server_local->rx_notice) { LOG_E("AT server session initialize failed! at_rx_notice semaphore create failed!"); @@ -521,7 +512,7 @@ int at_server_init(void) memcpy(at_server_local->end_mark, AT_CMD_END_MARK, sizeof(AT_CMD_END_MARK)); at_server_local->parser_entry = server_parser; - at_server_local->parser = rt_thread_create("at_server", + at_server_local->parser = rt_thread_create("at_svr", (void (*)(void *parameter))server_parser, at_server_local, 2 * 1024, @@ -565,3 +556,5 @@ RT_WEAK void at_port_factory_reset(void) { LOG_E("The factory reset for AT server is not implement."); } + +#endif /* AT_USING_SERVER */ diff --git a/components/net/at/src/at_utils.c b/components/net/at/src/at_utils.c index 25ee705ee6..73a25da04e 100644 --- a/components/net/at/src/at_utils.c +++ b/components/net/at/src/at_utils.c @@ -1,21 +1,7 @@ /* - * File : at_utils.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/net/freemodbus/modbus/rtu/mbrtu_m.c b/components/net/freemodbus/modbus/rtu/mbrtu_m.c index 987c9a3156..0c024e2b09 100644 --- a/components/net/freemodbus/modbus/rtu/mbrtu_m.c +++ b/components/net/freemodbus/modbus/rtu/mbrtu_m.c @@ -160,7 +160,7 @@ eMBMasterRTUReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, USHORT * pusLengt eMBErrorCode eStatus = MB_ENOERR; ENTER_CRITICAL_SECTION( ); - assert_param( usMasterRcvBufferPos < MB_SER_PDU_SIZE_MAX ); + RT_ASSERT( usMasterRcvBufferPos < MB_SER_PDU_SIZE_MAX ); /* Length and CRC check */ if( ( usMasterRcvBufferPos >= MB_SER_PDU_SIZE_MIN ) @@ -235,7 +235,7 @@ xMBMasterRTUReceiveFSM( void ) BOOL xTaskNeedSwitch = FALSE; UCHAR ucByte; - assert_param(( eSndState == STATE_M_TX_IDLE ) || ( eSndState == STATE_M_TX_XFWR )); + RT_ASSERT(( eSndState == STATE_M_TX_IDLE ) || ( eSndState == STATE_M_TX_XFWR )); /* Always read the character. */ ( void )xMBMasterPortSerialGetByte( ( CHAR * ) & ucByte ); @@ -301,7 +301,7 @@ xMBMasterRTUTransmitFSM( void ) { BOOL xNeedPoll = FALSE; - assert_param( eRcvState == STATE_M_RX_IDLE ); + RT_ASSERT( eRcvState == STATE_M_RX_IDLE ); switch ( eSndState ) { @@ -370,7 +370,7 @@ xMBMasterRTUTimerExpired(void) /* Function called in an illegal state. */ default: - assert_param( + RT_ASSERT( ( eRcvState == STATE_M_RX_INIT ) || ( eRcvState == STATE_M_RX_RCV ) || ( eRcvState == STATE_M_RX_ERROR ) || ( eRcvState == STATE_M_RX_IDLE )); break; @@ -390,7 +390,7 @@ xMBMasterRTUTimerExpired(void) break; /* Function called in an illegal state. */ default: - assert_param( + RT_ASSERT( ( eSndState == STATE_M_TX_XFWR ) || ( eSndState == STATE_M_TX_IDLE )); break; } diff --git a/components/net/freemodbus/port/portserial_m.c b/components/net/freemodbus/port/portserial_m.c index 366dc79983..f68794a617 100644 --- a/components/net/freemodbus/port/portserial_m.c +++ b/components/net/freemodbus/port/portserial_m.c @@ -57,7 +57,9 @@ BOOL xMBMasterPortSerialInit(UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, * set 485 mode receive and transmit control IO * @note MODBUS_MASTER_RT_CONTROL_PIN_INDEX need be defined by user */ +#if defined(RT_MODBUS_MASTER_USE_CONTROL_PIN) rt_pin_mode(MODBUS_MASTER_RT_CONTROL_PIN_INDEX, PIN_MODE_OUTPUT); +#endif /* set serial name */ if (ucPORT == 1) { @@ -128,12 +130,16 @@ void vMBMasterPortSerialEnable(BOOL xRxEnable, BOOL xTxEnable) /* enable RX interrupt */ serial->ops->control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX); /* switch 485 to receive mode */ +#if defined(RT_MODBUS_MASTER_USE_CONTROL_PIN) rt_pin_write(MODBUS_MASTER_RT_CONTROL_PIN_INDEX, PIN_LOW); +#endif } else { /* switch 485 to transmit mode */ +#if defined(RT_MODBUS_MASTER_USE_CONTROL_PIN) rt_pin_write(MODBUS_MASTER_RT_CONTROL_PIN_INDEX, PIN_HIGH); +#endif /* disable RX interrupt */ serial->ops->control(serial, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_RX); } diff --git a/components/net/lwip-1.3.2/README b/components/net/lwip-1.3.2/README deleted file mode 100644 index a62cc4f38c..0000000000 --- a/components/net/lwip-1.3.2/README +++ /dev/null @@ -1,89 +0,0 @@ -INTRODUCTION - -lwIP is a small independent implementation of the TCP/IP protocol -suite that has been developed by Adam Dunkels at the Computer and -Networks Architectures (CNA) lab at the Swedish Institute of Computer -Science (SICS). - -The focus of the lwIP TCP/IP implementation is to reduce the RAM usage -while still having a full scale TCP. This making lwIP suitable for use -in embedded systems with tens of kilobytes of free RAM and room for -around 40 kilobytes of code ROM. - -FEATURES - - * IP (Internet Protocol) including packet forwarding over multiple network - interfaces - * ICMP (Internet Control Message Protocol) for network maintenance and debugging - * IGMP (Internet Group Management Protocol) for multicast traffic management - * UDP (User Datagram Protocol) including experimental UDP-lite extensions - * TCP (Transmission Control Protocol) with congestion control, RTT estimation - and fast recovery/fast retransmit - * Specialized raw/native API for enhanced performance - * Optional Berkeley-like socket API - * DNS (Domain names resolver) - * SNMP (Simple Network Management Protocol) - * DHCP (Dynamic Host Configuration Protocol) - * AUTOIP (for IPv4, conform with RFC 3927) - * PPP (Point-to-Point Protocol) - * ARP (Address Resolution Protocol) for Ethernet - -LICENSE - -lwIP is freely available under a BSD license. - -DEVELOPMENT - -lwIP has grown into an excellent TCP/IP stack for embedded devices, -and developers using the stack often submit bug fixes, improvements, -and additions to the stack to further increase its usefulness. - -Development of lwIP is hosted on Savannah, a central point for -software development, maintenance and distribution. Everyone can -help improve lwIP by use of Savannah's interface, CVS and the -mailing list. A core team of developers will commit changes to the -CVS source tree. - -The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and -contributions (such as platform ports) are in the 'contrib' module. - -See doc/savannah.txt for details on CVS server access for users and -developers. - -Last night's CVS tar ball can be downloaded from: - http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING] - -The current CVS trees are web-browsable: - http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/ - http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/ - -Submit patches and bugs via the lwIP project page: - http://savannah.nongnu.org/projects/lwip/ - - -DOCUMENTATION - -The original out-dated homepage of lwIP and Adam Dunkels' papers on -lwIP are at the official lwIP home page: - http://www.sics.se/~adam/lwip/ - -Self documentation of the source code is regularly extracted from the -current CVS sources and is available from this web page: - http://www.nongnu.org/lwip/ - -There is now a constantly growin wiki about lwIP at - http://lwip.wikia.com/wiki/LwIP_Wiki - -Also, there are mailing lists you can subscribe at - http://savannah.nongnu.org/mail/?group=lwip -plus searchable archives: - http://lists.nongnu.org/archive/html/lwip-users/ - http://lists.nongnu.org/archive/html/lwip-devel/ - -Reading Adam's papers, the files in docs/, browsing the source code -documentation and browsing the mailing list archives is a good way to -become familiar with the design of lwIP. - -Adam Dunkels -Leon Woestenberg - diff --git a/components/net/lwip-1.3.2/SConscript b/components/net/lwip-1.3.2/SConscript deleted file mode 100644 index 2cef59e3d8..0000000000 --- a/components/net/lwip-1.3.2/SConscript +++ /dev/null @@ -1,87 +0,0 @@ -Import('RTT_ROOT') -from building import * - -src = Split(""" -src/api/api_lib.c -src/api/api_msg.c -src/api/err.c -src/api/netbuf.c -src/api/netdb.c -src/api/netifapi.c -src/api/sockets.c -src/api/tcpip.c -src/arch/sys_arch.c -src/arch/sys_arch_init.c -src/core/dhcp.c -src/core/dns.c -src/core/init.c -src/core/memp.c -src/core/netif.c -src/core/pbuf.c -src/core/raw.c -src/core/stats.c -src/core/sys.c -src/core/tcp.c -src/core/tcp_in.c -src/core/tcp_out.c -src/core/udp.c -src/core/ipv4/autoip.c -src/core/ipv4/icmp.c -src/core/ipv4/igmp.c -src/core/ipv4/inet.c -src/core/ipv4/inet_chksum.c -src/core/ipv4/ip.c -src/core/ipv4/ip_addr.c -src/core/ipv4/ip_frag.c -src/netif/etharp.c -src/netif/ethernetif.c -src/netif/loopif.c -src/netif/slipif.c -""") - -snmp_src = Split(""" -src/core/snmp/asn1_dec.c -src/core/snmp/asn1_enc.c -src/core/snmp/mib2.c -src/core/snmp/mib_structs.c -src/core/snmp/msg_in.c -src/core/snmp/msg_out.c -""") - -ppp_src = Split(""" -src/netif/ppp/auth.c -src/netif/ppp/chap.c -src/netif/ppp/chpms.c -src/netif/ppp/fsm.c -src/netif/ppp/ipcp.c -src/netif/ppp/lcp.c -src/netif/ppp/magic.c -src/netif/ppp/md5.c -src/netif/ppp/pap.c -src/netif/ppp/ppp.c -src/netif/ppp/ppp_oe.c -src/netif/ppp/randm.c -src/netif/ppp/vj.c -""") - -# The set of source files associated with this SConscript file. -path = [GetCurrentDir() + '/src', - GetCurrentDir() + '/src/include', - GetCurrentDir() + '/src/include/ipv4', - GetCurrentDir() + '/src/arch/include', - GetCurrentDir() + '/src/include/netif'] - -if GetDepend(['RT_LWIP_SNMP']): - src += snmp_src - -if GetDepend(['RT_LWIP_PPP']): - src += ppp_src - path += [GetCurrentDir() + '/src/netif/ppp'] - -# For testing apps -if GetDepend(['RT_USING_NETUTILS']): - src += Glob('./apps/*.c') - -group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP132'], CPPPATH = path) - -Return('group') diff --git a/components/net/lwip-1.3.2/apps/chargen.c b/components/net/lwip-1.3.2/apps/chargen.c deleted file mode 100644 index 096401ae75..0000000000 --- a/components/net/lwip-1.3.2/apps/chargen.c +++ /dev/null @@ -1,216 +0,0 @@ -#include - -#include "lwip/sockets.h" -#define MAX_SERV 32 /* Maximum number of chargen services. Don't need too many */ -#define CHARGEN_THREAD_NAME "chargen" -#if RT_THREAD_PRIORITY_MAX == 32 -#define CHARGEN_PRIORITY 20 /* Really low priority */ -#else -#define CHARGEN_PRIORITY 200 /* Really low priority */ -#endif -#define CHARGEN_THREAD_STACKSIZE 1024 -struct charcb -{ - struct charcb *next; - int socket; - struct sockaddr_in cliaddr; - socklen_t clilen; - char nextchar; -}; - -static struct charcb *charcb_list = 0; -static int do_read(struct charcb *p_charcb); -static void close_chargen(struct charcb *p_charcb); - -/************************************************************** - * void chargen_thread(void *arg) - * - * chargen task. This server will wait for connections on well - * known TCP port number: 19. For every connection, the server will - * write as much data as possible to the tcp port. - **************************************************************/ -static void chargen_thread(void *arg) -{ - int listenfd; - struct sockaddr_in chargen_saddr; - fd_set readset; - fd_set writeset; - int i, maxfdp1; - struct charcb *p_charcb; - - /* First acquire our socket for listening for connections */ - listenfd = lwip_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); - - LWIP_ASSERT("chargen_thread(): Socket create failed.", listenfd >= 0); - memset(&chargen_saddr, 0, sizeof(chargen_saddr)); - chargen_saddr.sin_family = AF_INET; - chargen_saddr.sin_addr.s_addr = htonl(INADDR_ANY); - chargen_saddr.sin_port = htons(19); // Chargen server port - - if (lwip_bind(listenfd, (struct sockaddr *) &chargen_saddr, sizeof(chargen_saddr)) == -1) - LWIP_ASSERT("chargen_thread(): Socket bind failed.", 0); - - /* Put socket into listening mode */ - if (lwip_listen(listenfd, MAX_SERV) == -1) - LWIP_ASSERT("chargen_thread(): Listen failed.", 0); - - /* Wait forever for network input: This could be connections or data */ - for (;;) - { - maxfdp1 = listenfd+1; - - /* Determine what sockets need to be in readset */ - FD_ZERO(&readset); - FD_ZERO(&writeset); - FD_SET(listenfd, &readset); - for (p_charcb = charcb_list; p_charcb; p_charcb = p_charcb->next) - { - if (maxfdp1 < p_charcb->socket + 1) - maxfdp1 = p_charcb->socket + 1; - FD_SET(p_charcb->socket, &readset); - FD_SET(p_charcb->socket, &writeset); - } - - /* Wait for data or a new connection */ - i = lwip_select(maxfdp1, &readset, &writeset, 0, 0); - - if (i == 0) continue; - - /* At least one descriptor is ready */ - if (FD_ISSET(listenfd, &readset)) - { - /* We have a new connection request!!! */ - /* Lets create a new control block */ - p_charcb = (struct charcb *)rt_calloc(1, sizeof(struct charcb)); - if (p_charcb) - { - p_charcb->socket = lwip_accept(listenfd, - (struct sockaddr *) &p_charcb->cliaddr, - &p_charcb->clilen); - if (p_charcb->socket < 0) - rt_free(p_charcb); - else - { - /* Keep this tecb in our list */ - p_charcb->next = charcb_list; - charcb_list = p_charcb; - p_charcb->nextchar = 0x21; - } - } - else - { - /* No memory to accept connection. Just accept and then close */ - int sock; - struct sockaddr cliaddr; - socklen_t clilen; - - sock = lwip_accept(listenfd, &cliaddr, &clilen); - if (sock >= 0) - lwip_close(sock); - } - } - /* Go through list of connected clients and process data */ - for (p_charcb = charcb_list; p_charcb; p_charcb = p_charcb->next) - { - if (FD_ISSET(p_charcb->socket, &readset)) - { - /* This socket is ready for reading. This could be because someone typed - * some characters or it could be because the socket is now closed. Try reading - * some data to see. */ - if (do_read(p_charcb) < 0) - break; - } - if (FD_ISSET(p_charcb->socket, &writeset)) - { - char line[80]; - char setchar = p_charcb->nextchar; - - for( i = 0; i < 59; i++) - { - line[i] = setchar; - if (++setchar == 0x7f) - setchar = 0x21; - } - line[i] = 0; - strcat(line, "\n\r"); - if (lwip_write(p_charcb->socket, line, strlen(line)) < 0) - { - close_chargen(p_charcb); - break; - } - if (++p_charcb->nextchar == 0x7f) - p_charcb->nextchar = 0x21; - } - } - } -} - -/************************************************************** - * void close_chargen(struct charcb *p_charcb) - * - * Close the socket and remove this charcb from the list. - **************************************************************/ -static void close_chargen(struct charcb *p_charcb) -{ - struct charcb *p_search_charcb; - - /* Either an error or tcp connection closed on other - * end. Close here */ - lwip_close(p_charcb->socket); - - /* Free charcb */ - if (charcb_list == p_charcb) - charcb_list = p_charcb->next; - else - for (p_search_charcb = charcb_list; p_search_charcb; p_search_charcb = p_search_charcb->next) - { - if (p_search_charcb->next == p_charcb) - { - p_search_charcb->next = p_charcb->next; - break; - } - } - - rt_free(p_charcb); -} - -/************************************************************** - * void do_read(struct charcb *p_charcb) - * - * Socket definitely is ready for reading. Read a buffer from the socket and - * discard the data. If no data is read, then the socket is closed and the - * charcb is removed from the list and freed. - **************************************************************/ -static int do_read(struct charcb *p_charcb) -{ - char buffer[80]; - int readcount; - - /* Read some data */ - readcount = lwip_read(p_charcb->socket, &buffer, 80); - if (readcount <= 0) - { - close_chargen(p_charcb); - return -1; - } - return 0; -} - -void chargen_init(void) -{ - rt_thread_t chargen; - - chargen = rt_thread_create(CHARGEN_THREAD_NAME, - chargen_thread, RT_NULL, - CHARGEN_THREAD_STACKSIZE, - CHARGEN_PRIORITY, 5); - if (chargen != RT_NULL) rt_thread_startup(chargen); -} -#ifdef RT_USING_FINSH -#include -void chargen() -{ - chargen_init(); -} -FINSH_FUNCTION_EXPORT(chargen, start chargen server); -#endif diff --git a/components/net/lwip-1.3.2/apps/ftpd.c b/components/net/lwip-1.3.2/apps/ftpd.c deleted file mode 100644 index af07b1413a..0000000000 --- a/components/net/lwip-1.3.2/apps/ftpd.c +++ /dev/null @@ -1,791 +0,0 @@ -#include -#include - -#include -#include -#include -#include - -#define FTP_PORT 21 -#define FTP_SRV_ROOT "/" -#define FTP_MAX_CONNECTION 2 -#define FTP_USER "rtt" -#define FTP_PASSWORD "demo" -#define FTP_WELCOME_MSG "220-= welcome on RT-Thread FTP server =-\r\n220 \r\n" -#define FTP_BUFFER_SIZE 1024 - -struct ftp_session -{ - rt_bool_t is_anonymous; - - int sockfd; - struct sockaddr_in remote; - - /* pasv data */ - char pasv_active; - int pasv_sockfd; - - unsigned short pasv_port; - size_t offset; - - /* current directory */ - char currentdir[256]; - - struct ftp_session* next; -}; -static struct ftp_session* session_list = NULL; - -static int ftp_process_request(struct ftp_session* session, char * buf); -static int ftp_get_filesize(char *filename); - -static struct ftp_session* ftp_new_session() -{ - struct ftp_session* session; - - session = (struct ftp_session*)rt_malloc(sizeof(struct ftp_session)); - - session->next = session_list; - session_list = session; - - return session; -} - -static void ftp_close_session(struct ftp_session* session) -{ - struct ftp_session* list; - - if (session_list == session) - { - session_list = session_list->next; - session->next = NULL; - } - else - { - list = session_list; - while (list->next != session) list = list->next; - - list->next = session->next; - session->next = NULL; - } - - rt_free(session); -} - -static int ftp_get_filesize(char * filename) -{ - int pos; - int end; - int fd; - - fd = open(filename, O_RDONLY, 0); - if (fd < 0) return -1; - - pos = lseek(fd, 0, SEEK_CUR); - end = lseek(fd, 0, SEEK_END); - lseek (fd, pos, SEEK_SET); - close(fd); - - return end; -} - -static rt_bool_t is_absolute_path(char* path) -{ -#ifdef _WIN32 - if (path[0] == '\\' || - (path[1] == ':' && path[2] == '\\')) - return RT_TRUE; -#else - if (path[0] == '/') return RT_TRUE; -#endif - - return RT_FALSE; -} - -static int build_full_path(struct ftp_session* session, char* path, char* new_path, size_t size) -{ - if (is_absolute_path(path) == RT_TRUE) - strcpy(new_path, path); - else - { - rt_sprintf(new_path, "%s/%s", session->currentdir, path); - } - - return 0; -} - -static void ftpd_thread_entry(void* parameter) -{ - int numbytes; - int sockfd, maxfdp1; - struct sockaddr_in local; - fd_set readfds, tmpfds; - struct ftp_session* session; - rt_uint32_t addr_len = sizeof(struct sockaddr); - char * buffer = (char *) rt_malloc(FTP_BUFFER_SIZE); - - local.sin_port=htons(FTP_PORT); - local.sin_family=PF_INET; - local.sin_addr.s_addr=INADDR_ANY; - - FD_ZERO(&readfds); - FD_ZERO(&tmpfds); - - sockfd=socket(AF_INET, SOCK_STREAM, 0); - if(sockfd < 0) - { - rt_kprintf("create socket failed\n"); - return ; - } - - bind(sockfd, (struct sockaddr *)&local, addr_len); - listen(sockfd, FTP_MAX_CONNECTION); - - FD_SET(sockfd, &readfds); - for(;;) - { - /* get maximum fd */ - maxfdp1 = sockfd + 1; - session = session_list; - while (session != RT_NULL) - { - if (maxfdp1 < session->sockfd + 1) - maxfdp1 = session->sockfd + 1; - - FD_SET(session->sockfd, &readfds); - session = session->next; - } - - tmpfds=readfds; - if (select(maxfdp1, &tmpfds, 0, 0, 0) == 0) continue; - - if(FD_ISSET(sockfd, &tmpfds)) - { - int com_socket; - struct sockaddr_in remote; - - com_socket = accept(sockfd, (struct sockaddr*)&remote, &addr_len); - if(com_socket == -1) - { - rt_kprintf("Error on accept()\nContinuing...\n"); - continue; - } - else - { - rt_kprintf("Got connection from %s\n", inet_ntoa(remote.sin_addr)); - send(com_socket, FTP_WELCOME_MSG, strlen(FTP_WELCOME_MSG), 0); - FD_SET(com_socket, &readfds); - - /* new session */ - session = ftp_new_session(); - if (session != NULL) - { - strcpy(session->currentdir, FTP_SRV_ROOT); - session->sockfd = com_socket; - session->remote = remote; - } - } - } - - { - struct ftp_session* next; - - session = session_list; - while (session != NULL) - { - next = session->next; - if (FD_ISSET(session->sockfd, &tmpfds)) - { - numbytes=recv(session->sockfd, buffer, FTP_BUFFER_SIZE, 0); - if(numbytes==0 || numbytes==-1) - { - rt_kprintf("Client %s disconnected\n", inet_ntoa(session->remote.sin_addr)); - FD_CLR(session->sockfd, &readfds); - closesocket(session->sockfd); - ftp_close_session(session); - } - else - { - buffer[numbytes]=0; - if(ftp_process_request(session, buffer)==-1) - { - rt_kprintf("Client %s disconnected\r\n", inet_ntoa(session->remote.sin_addr)); - closesocket(session->sockfd); - ftp_close_session(session); - } - } - } - - session = next; - } - } - } - - // rt_free(buffer); -} - -static int do_list(char* directory, int sockfd) -{ - DIR* dirp; - struct dirent* entry; - char line_buffer[256], line_length; -#ifdef _WIN32 - struct _stat s; -#else - struct stat s; -#endif - - dirp = opendir(directory); - if (dirp == NULL) - { - line_length = rt_sprintf(line_buffer, "500 Internal Error\r\n"); - send(sockfd, line_buffer, line_length, 0); - return -1; - } - - while (1) - { - entry = readdir(dirp); - if (entry == NULL) break; - - rt_sprintf(line_buffer, "%s/%s", directory, entry->d_name); -#ifdef _WIN32 - if (_stat(line_buffer, &s) ==0) -#else - if (stat(line_buffer, &s) == 0) -#endif - { - if (s.st_mode & S_IFDIR) - line_length = rt_sprintf(line_buffer, "drw-r--r-- 1 admin admin %d Jan 1 2000 %s\r\n", 0, entry->d_name); - else - line_length = rt_sprintf(line_buffer, "-rw-r--r-- 1 admin admin %d Jan 1 2000 %s\r\n", s.st_size, entry->d_name); - - send(sockfd, line_buffer, line_length, 0); - } - else - { - rt_kprintf("Get directory entry error\n"); - break; - } - } - - closedir(dirp); - return 0; -} - -static int do_simple_list(char* directory, int sockfd) -{ - DIR* dirp; - struct dirent* entry; - char line_buffer[256], line_length; - - dirp = opendir(directory); - if (dirp == NULL) - { - line_length = rt_sprintf(line_buffer, "500 Internal Error\r\n"); - send(sockfd, line_buffer, line_length, 0); - return -1; - } - - while (1) - { - entry = readdir(dirp); - if (entry == NULL) break; - - line_length = rt_sprintf(line_buffer, "%s\r\n", entry->d_name); - send(sockfd, line_buffer, line_length, 0); - } - - closedir(dirp); - return 0; -} - -static int str_begin_with(char* src, char* match) -{ - while (*match) - { - /* check source */ - if (*src == 0) return -1; - - if (*match != *src) return -1; - match ++; src ++; - } - - return 0; -} - -static int ftp_process_request(struct ftp_session* session, char *buf) -{ - int fd; - struct timeval tv; - fd_set readfds; - char filename[256]; - int numbytes; - char *sbuf; - char *parameter_ptr, *ptr; - rt_uint32_t addr_len = sizeof(struct sockaddr_in); - struct sockaddr_in local, pasvremote; - - sbuf =(char *)rt_malloc(FTP_BUFFER_SIZE); - - tv.tv_sec=3, tv.tv_usec=0; - local.sin_family=PF_INET; - local.sin_addr.s_addr=INADDR_ANY; - - /* remove \r\n */ - ptr = buf; - while (*ptr) - { - if (*ptr == '\r' || *ptr == '\n') *ptr = 0; - ptr ++; - } - - /* get request parameter */ - parameter_ptr = strchr(buf, ' '); if (parameter_ptr != NULL) parameter_ptr ++; - - // debug: - rt_kprintf("%s requested: \"%s\"\n", inet_ntoa(session->remote.sin_addr), buf); - - // - //----------------------- - if(str_begin_with(buf, "USER")==0) - { - rt_kprintf("%s sent login \"%s\"\n", inet_ntoa(session->remote.sin_addr), parameter_ptr); - // login correct - if(strcmp(parameter_ptr, "anonymous") == 0) - { - session->is_anonymous = RT_TRUE; - rt_sprintf(sbuf, "331 Anonymous login OK send e-mail address for password.\r\n", parameter_ptr); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if (strcmp(parameter_ptr, FTP_USER) == 0) - { - session->is_anonymous = RT_FALSE; - rt_sprintf(sbuf, "331 Password required for %s\r\n", parameter_ptr); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else - { - // incorrect login - rt_sprintf(sbuf, "530 Login incorrect. Bye.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return -1; - } - return 0; - } - else if(str_begin_with(buf, "PASS")==0) - { - rt_kprintf("%s sent password \"%s\"\n", inet_ntoa(session->remote.sin_addr), parameter_ptr); - if (strcmp(parameter_ptr, FTP_PASSWORD)==0 || - session->is_anonymous == RT_TRUE) - { - // password correct - rt_sprintf(sbuf, "230 User logged in\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return 0; - } - - // incorrect password - rt_sprintf(sbuf, "530 Login or Password incorrect. Bye!\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return -1; - } - else if(str_begin_with(buf, "LIST")==0 ) - { - memset(sbuf,0,FTP_BUFFER_SIZE); - rt_sprintf(sbuf, "150 Opening Binary mode connection for file list.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - do_list(session->currentdir, session->pasv_sockfd); - closesocket(session->pasv_sockfd); - session->pasv_active = 0; - rt_sprintf(sbuf, "226 Transfert Complete.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "NLST")==0 ) - { - memset(sbuf, 0, FTP_BUFFER_SIZE); - rt_sprintf(sbuf, "150 Opening Binary mode connection for file list.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - do_simple_list(session->currentdir, session->pasv_sockfd); - closesocket(session->pasv_sockfd); - session->pasv_active = 0; - rt_sprintf(sbuf, "226 Transfert Complete.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "PWD")==0 || str_begin_with(buf, "XPWD")==0) - { - rt_sprintf(sbuf, "257 \"%s\" is current directory.\r\n", session->currentdir); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "TYPE")==0) - { - // Ignore it - if(strcmp(parameter_ptr, "I")==0) - { - rt_sprintf(sbuf, "200 Type set to binary.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else - { - rt_sprintf(sbuf, "200 Type set to ascii.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - } - else if(str_begin_with(buf, "PASV")==0) - { - int dig1, dig2; - int sockfd; - char optval='1'; - - session->pasv_port = 10000; - session->pasv_active = 1; - local.sin_port=htons(session->pasv_port); - local.sin_addr.s_addr=INADDR_ANY; - - dig1 = (int)(session->pasv_port/256); - dig2 = session->pasv_port % 256; - - FD_ZERO(&readfds); - if((sockfd=socket(PF_INET, SOCK_STREAM, 0))==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - goto err1; - } - if(setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &optval, sizeof(optval))==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - goto err1; - } - if(bind(sockfd, (struct sockaddr *)&local, addr_len)==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - goto err1; - } - if(listen(sockfd, 1)==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - goto err1; - } - rt_kprintf("Listening %d seconds @ port %d\n", tv.tv_sec, session->pasv_port); - rt_sprintf(sbuf, "227 Entering passive mode (%d,%d,%d,%d,%d,%d)\r\n", 127, 0, 0, 1, dig1, dig2); - send(session->sockfd, sbuf, strlen(sbuf), 0); - FD_SET(sockfd, &readfds); - select(0, &readfds, 0, 0, &tv); - if(FD_ISSET(sockfd, &readfds)) - { - if((session->pasv_sockfd = accept(sockfd, (struct sockaddr*)&pasvremote, &addr_len))==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - goto err1; - } - else - { - rt_kprintf("Got Data(PASV) connection from %s\n", inet_ntoa(pasvremote.sin_addr)); - session->pasv_active = 1; - closesocket(sockfd); - } - } - else - { -err1: - closesocket(session->pasv_sockfd); - session->pasv_active = 0; - rt_free(sbuf); - return 0; - } - } - else if (str_begin_with(buf, "RETR")==0) - { - int file_size; - - strcpy(filename, buf + 5); - - build_full_path(session, parameter_ptr, filename, 256); - file_size = ftp_get_filesize(filename); - if (file_size == -1) - { - rt_sprintf(sbuf, "550 \"%s\" : not a regular file\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - session->offset=0; - rt_free(sbuf); - return 0; - } - - fd = open(filename, O_RDONLY, 0); - if (fd < 0) - { - rt_free(sbuf); - return 0; - } - - if(session->offset>0 && session->offset < file_size) - { - lseek(fd, session->offset, SEEK_SET); - rt_sprintf(sbuf, "150 Opening binary mode data connection for partial \"%s\" (%d/%d bytes).\r\n", - filename, file_size - session->offset, file_size); - } - else - { - rt_sprintf(sbuf, "150 Opening binary mode data connection for \"%s\" (%d bytes).\r\n", filename, file_size); - } - send(session->sockfd, sbuf, strlen(sbuf), 0); - while((numbytes = read(fd, sbuf, FTP_BUFFER_SIZE))>0) - { - send(session->pasv_sockfd, sbuf, numbytes, 0); - } - rt_sprintf(sbuf, "226 Finished.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - close(fd); - closesocket(session->pasv_sockfd); - } - else if (str_begin_with(buf, "STOR")==0) - { - if(session->is_anonymous == RT_TRUE) - { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return 0; - } - - build_full_path(session, parameter_ptr, filename, 256); - - fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0); - if(fd < 0) - { - rt_sprintf(sbuf, "550 Cannot open \"%s\" for writing.\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return 0; - } - rt_sprintf(sbuf, "150 Opening binary mode data connection for \"%s\".\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - FD_ZERO(&readfds); - FD_SET(session->pasv_sockfd, &readfds); - rt_kprintf("Waiting %d seconds for data...\n", tv.tv_sec); - while(select(session->pasv_sockfd+1, &readfds, 0, 0, &tv)>0 ) - { - if((numbytes=recv(session->pasv_sockfd, sbuf, FTP_BUFFER_SIZE, 0))>0) - { - write(fd, sbuf, numbytes); - } - else if(numbytes==0) - { - close(fd); - closesocket(session->pasv_sockfd); - rt_sprintf(sbuf, "226 Finished.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - break; - } - else if(numbytes==-1) - { - close(fd); - closesocket(session->pasv_sockfd); - rt_free(sbuf); - return -1; - } - } - closesocket(session->pasv_sockfd); - } - else if(str_begin_with(buf, "SIZE")==0) - { - int file_size; - - build_full_path(session, parameter_ptr, filename, 256); - - file_size = ftp_get_filesize(filename); - if( file_size == -1) - { - rt_sprintf(sbuf, "550 \"%s\" : not a regular file\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else - { - rt_sprintf(sbuf, "213 %d\r\n", file_size); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - } - else if(str_begin_with(buf, "MDTM")==0) - { - rt_sprintf(sbuf, "550 \"/\" : not a regular file\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "SYST")==0) - { - rt_sprintf(sbuf, "215 %s\r\n", "RT-Thread RTOS"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "CWD")==0) - { - build_full_path(session, parameter_ptr, filename, 256); - - rt_sprintf(sbuf, "250 Changed to directory \"%s\"\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - strcpy(session->currentdir, filename); - rt_kprintf("Changed to directory %s", filename); - } - else if(str_begin_with(buf, "CDUP")==0) - { - rt_sprintf(filename, "%s/%s", session->currentdir, ".."); - - rt_sprintf(sbuf, "250 Changed to directory \"%s\"\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - strcpy(session->currentdir, filename); - rt_kprintf("Changed to directory %s", filename); - } - else if(str_begin_with(buf, "PORT")==0) - { - int i; - int portcom[6]; - char tmpip[100]; - - i=0; - portcom[i++]=atoi(strtok(parameter_ptr, ".,;()")); - for(;i<6;i++) - portcom[i]=atoi(strtok(0, ".,;()")); - rt_sprintf(tmpip, "%d.%d.%d.%d", portcom[0], portcom[1], portcom[2], portcom[3]); - - FD_ZERO(&readfds); - if((session->pasv_sockfd=socket(AF_INET, SOCK_STREAM, 0))==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - closesocket(session->pasv_sockfd); - session->pasv_active = 0; - rt_free(sbuf); - return 0; - } - pasvremote.sin_addr.s_addr=inet_addr(tmpip); - pasvremote.sin_port=htons(portcom[4] * 256 + portcom[5]); - pasvremote.sin_family=PF_INET; - if(connect(session->pasv_sockfd, (struct sockaddr *)&pasvremote, addr_len)==-1) - { - // is it only local address?try using gloal ip addr - pasvremote.sin_addr=session->remote.sin_addr; - if(connect(session->pasv_sockfd, (struct sockaddr *)&pasvremote, addr_len)==-1) - { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - closesocket(session->pasv_sockfd); - rt_free(sbuf); - return 0; - } - } - session->pasv_active=1; - session->pasv_port = portcom[4] * 256 + portcom[5]; - rt_kprintf("Connected to Data(PORT) %s @ %d\n", tmpip, portcom[4] * 256 + portcom[5]); - rt_sprintf(sbuf, "200 Port Command Successful.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "REST")==0) - { - if(atoi(parameter_ptr)>=0) - { - session->offset=atoi(parameter_ptr); - rt_sprintf(sbuf, "350 Send RETR or STOR to start transfert.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - } - else if(str_begin_with(buf, "MKD")==0) - { - if (session->is_anonymous == RT_TRUE) - { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return 0; - } - - build_full_path(session, parameter_ptr, filename, 256); - - if(mkdir(filename, 0) == -1) - { - rt_sprintf(sbuf, "550 File \"%s\" exists.\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else - { - rt_sprintf(sbuf, "257 directory \"%s\" successfully created.\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - } - else if(str_begin_with(buf, "DELE")==0) - { - if (session->is_anonymous == RT_TRUE) - { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return 0; - } - - build_full_path(session, parameter_ptr, filename, 256); - - if(unlink(filename)==0) - rt_sprintf(sbuf, "250 Successfully deleted file \"%s\".\r\n", filename); - else - { - rt_sprintf(sbuf, "550 Not such file or directory: %s.\r\n", filename); - } - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else if(str_begin_with(buf, "RMD")==0) - { - if (session->is_anonymous == RT_TRUE) - { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return 0; - } - build_full_path(session, parameter_ptr, filename, 256); - - if(unlink(filename) == -1) - { - rt_sprintf(sbuf, "550 Directory \"%s\" doesn't exist.\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - else - { - rt_sprintf(sbuf, "257 directory \"%s\" successfully deleted.\r\n", filename); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - } - - else if(str_begin_with(buf, "QUIT")==0) - { - rt_sprintf(sbuf, "221 Bye!\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); - return -1; - } - else - { - rt_sprintf(sbuf, "502 Not Implemented.\r\n"); - send(session->sockfd, sbuf, strlen(sbuf), 0); - } - rt_free(sbuf); - return 0; -} - -void ftpd_start() -{ - rt_thread_t tid; - - tid = rt_thread_create("ftpd", - ftpd_thread_entry, RT_NULL, - 4096, 30, 5); - if (tid != RT_NULL) rt_thread_startup(tid); -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(ftpd_start, start ftp server) -#endif diff --git a/components/net/lwip-1.3.2/apps/netio.c b/components/net/lwip-1.3.2/apps/netio.c deleted file mode 100644 index 0466cc5f6d..0000000000 --- a/components/net/lwip-1.3.2/apps/netio.c +++ /dev/null @@ -1,376 +0,0 @@ -/** - * @file - * MetIO Server - * - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ -#include "lwip/opt.h" - -#if LWIP_TCP -#include "lwip/tcp.h" - -/* - * This implements a netio server. - * The client sends a command word (4 bytes) then a data length word (4 bytes). - * If the command is "receive", the server is to consume "data length" bytes into - * a circular buffer until the first byte is non-zero, then it is to consume - * another command/data pair. - * If the command is "send", the server is to send "data length" bytes from a circular - * buffer with the first byte being zero, until "some time" (6 seconds in the - * current netio126.zip download) has passed and then send one final buffer with - * the first byte being non-zero. Then it is to consume another command/data pair. - */ - -/* See http://www.nwlab.net/art/netio/netio.html to get the netio tool */ - -/* implementation options */ -#define NETIO_BUF_SIZE (4 * 1024) -#define NETIO_USE_STATIC_BUF 0 - -/* NetIO server state definition */ -#define NETIO_STATE_WAIT_FOR_CMD 0 -#define NETIO_STATE_RECV_DATA 1 -#define NETIO_STATE_SEND_DATA 2 -#define NETIO_STATE_SEND_DATA_LAST 3 -#define NETIO_STATE_DONE 4 - -struct netio_state { - u32_t state; - u32_t cmd; - u32_t data_len; - u32_t cntr; - u8_t * buf_ptr; - u32_t buf_pos; - u32_t first_byte; - u32_t time_stamp; -}; - -/* NetIO command protocol definition */ -#define NETIO_CMD_QUIT 0 -#define NETIO_CMD_C2S 1 -#define NETIO_CMD_S2C 2 -#define NETIO_CMD_RES 3 - -static err_t netio_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); - -static void -netio_close(void *arg, struct tcp_pcb *pcb) -{ - err_t err; - - struct netio_state *ns = arg; - ns->state = NETIO_STATE_DONE; - tcp_recv(pcb, NULL); - err = tcp_close(pcb); - - if (err != ERR_OK) { - /* closing failed, try again later */ - tcp_recv(pcb, netio_recv); - } else { - /* closing succeeded */ -#if NETIO_USE_STATIC_BUF != 1 - if(ns->buf_ptr != NULL){ - mem_free(ns->buf_ptr); - } -#endif - tcp_arg(pcb, NULL); - tcp_poll(pcb, NULL, 0); - tcp_sent(pcb, NULL); - if (arg != NULL) { - mem_free(arg); - } - } -} - -static err_t -netio_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - struct netio_state *ns = arg; - u8_t * data_ptr; - u32_t data_cntr; - struct pbuf *q = p; - u16_t len; - - if (p != NULL) { - tcp_recved(pcb, p->tot_len); - } - - if (err == ERR_OK && q != NULL) { - - while (q != NULL) { - data_cntr = q->len; - data_ptr = q->payload; - while (data_cntr--) { - if (ns->state == NETIO_STATE_DONE){ - netio_close(ns, pcb); - break; - } else if (ns->state == NETIO_STATE_WAIT_FOR_CMD) { - if (ns->cntr < 4) { - /* build up the CMD field */ - ns->cmd <<= 8; - ns->cmd |= *data_ptr++; - ns->cntr++; - } else if (ns->cntr < 8) { - /* build up the DATA field */ - ns->data_len <<= 8; - ns->data_len |= *data_ptr++; - ns->cntr++; - - if (ns->cntr == 8) { - /* now we have full command and data words */ - ns->cntr = 0; - ns->buf_pos = 0; - ns->buf_ptr[0] = 0; - if (ns->cmd == NETIO_CMD_C2S) { - ns->state = NETIO_STATE_RECV_DATA; - } else if (ns->cmd == NETIO_CMD_S2C) { - ns->state = NETIO_STATE_SEND_DATA; - /* start timer */ - ns->time_stamp = rt_tick_get(); - /* send first round of data */ - - len = tcp_sndbuf(pcb); - len = LWIP_MIN(len, ns->data_len - ns->cntr); - len = LWIP_MIN(len, NETIO_BUF_SIZE - ns->buf_pos); - - do { - err = tcp_write(pcb, ns->buf_ptr + ns->buf_pos, len, TCP_WRITE_FLAG_COPY); - if (err == ERR_MEM) { - len /= 2; - } - } while ((err == ERR_MEM) && (len > 1)); - - ns->buf_pos += len; - ns->cntr += len; - - } else { - /* unrecognized command, punt */ - ns->cntr = 0; - ns->buf_pos = 0; - ns->buf_ptr[0] = 0; - netio_close(ns, pcb); - break; - } - } - } else { - /* in trouble... shouldn't be in this state! */ - } - - } else if (ns->state == NETIO_STATE_RECV_DATA) { - int chunk_length; - - if(ns->cntr == 0){ - /* save the first byte of this new round of data - * this will not match ns->buf_ptr[0] in the case that - * NETIO_BUF_SIZE is less than ns->data_len. - */ - ns->first_byte = *data_ptr; - } - - if (ns->cntr + (data_cntr + 1) < ns->data_len) chunk_length = data_cntr + 1; - else chunk_length = (ns->data_len - ns->cntr); - - ns->buf_pos += chunk_length; - data_ptr += chunk_length; - ns->cntr += chunk_length; - data_cntr -= (chunk_length - 1); - - if (ns->buf_pos >= NETIO_BUF_SIZE) { - /* circularize the buffer */ - ns->buf_pos %= NETIO_BUF_SIZE; - } - - if(ns->cntr == ns->data_len){ - ns->cntr = 0; - if (ns->first_byte != 0) { - /* if this last round did not start with 0, - * go look for another command */ - ns->state = NETIO_STATE_WAIT_FOR_CMD; - ns->data_len = 0; - ns->cmd = 0; - /* TODO LWIP_DEBUGF( print out some throughput calculation results... ); */ - } else { - /* stay here and wait on more data */ - } - } - - } else if (ns->state == NETIO_STATE_SEND_DATA - || ns->state == NETIO_STATE_SEND_DATA_LAST) { - /* I don't think this should happen... */ - } else { - /* done / quit */ - netio_close(ns, pcb); - break; - } /* end of ns->state condition */ - } /* end of while data still in this pbuf */ - - q = q->next; - } - - pbuf_free(p); - - } else { - - /* error or closed by other side */ - if (p != NULL) { - pbuf_free(p); - } - - /* close the connection */ - netio_close(ns, pcb); - - } - return ERR_OK; - -} - -static err_t -netio_sent(void *arg, struct tcp_pcb *pcb, u16_t len) -{ - struct netio_state *ns = arg; - err_t err = ERR_OK; - - if (ns->cntr >= ns->data_len && ns->state == NETIO_STATE_SEND_DATA) { - /* done with this round of sending */ - ns->buf_pos = 0; - ns->cntr = 0; - - /* check if timer expired */ - if (rt_tick_get() - ns->time_stamp > 600) { - ns->buf_ptr[0] = 1; - ns->state = NETIO_STATE_SEND_DATA_LAST; - } else { - ns->buf_ptr[0] = 0; - } - } - - if(ns->state == NETIO_STATE_SEND_DATA_LAST || ns->state == NETIO_STATE_SEND_DATA){ - len = tcp_sndbuf(pcb); - len = LWIP_MIN(len, ns->data_len - ns->cntr); - len = LWIP_MIN(len, NETIO_BUF_SIZE - ns->buf_pos); - - if(ns->cntr < ns->data_len){ - do { - err = tcp_write(pcb, ns->buf_ptr + ns->buf_pos, len, TCP_WRITE_FLAG_COPY); - if (err == ERR_MEM) { - len /= 2; - } - } while ((err == ERR_MEM) && (len > 1)); - - ns->buf_pos += len; - if(ns->buf_pos >= NETIO_BUF_SIZE){ - ns->buf_pos = 0; - } - - ns->cntr += len; - } - } - - if(ns->cntr >= ns->data_len && ns->state == NETIO_STATE_SEND_DATA_LAST){ - /* we have buffered up all our data to send this last round, go look for a command */ - ns->state = NETIO_STATE_WAIT_FOR_CMD; - ns->cntr = 0; - /* TODO LWIP_DEBUGF( print out some throughput calculation results... ); */ - } - - return ERR_OK; -} - -static err_t -netio_poll(void *arg, struct tcp_pcb *pcb) -{ - struct netio_state * ns = arg; - if(ns->state == NETIO_STATE_SEND_DATA){ - - } else if(ns->state == NETIO_STATE_DONE){ - netio_close(ns, pcb); - } - - return ERR_OK; - -} - -#if NETIO_USE_STATIC_BUF == 1 -static u8_t netio_buf[NETIO_BUF_SIZE]; -#endif - -static err_t -netio_accept(void *arg, struct tcp_pcb *pcb, err_t err) -{ - struct netio_state * ns; - - LWIP_UNUSED_ARG(err); - - ns = mem_malloc(sizeof(struct netio_state)); - - if(ns == NULL){ - return ERR_MEM; - } - - ns->state = NETIO_STATE_WAIT_FOR_CMD; - ns->data_len = 0; - ns->cmd = 0; - ns->cntr = 0; - ns->buf_pos = 0; -#if NETIO_USE_STATIC_BUF == 1 - ns->buf_ptr = netio_buf; -#else - ns->buf_ptr = mem_malloc(NETIO_BUF_SIZE); - - if(ns->buf_ptr == NULL){ - mem_free(ns); - return ERR_MEM; - } -#endif - - ns->buf_ptr[0] = 0; - - tcp_arg(pcb, ns); - tcp_sent(pcb, netio_sent); - tcp_recv(pcb, netio_recv); - tcp_poll(pcb, netio_poll, 4); /* every 2 seconds */ - return ERR_OK; -} - -void netio_init(void) -{ - struct tcp_pcb *pcb; - - pcb = tcp_new(); - tcp_bind(pcb, IP_ADDR_ANY, 18767); - pcb = tcp_listen(pcb); - tcp_accept(pcb, netio_accept); -} - -#endif /* LWIP_TCP */ - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(netio_init, netio server); -#endif diff --git a/components/net/lwip-1.3.2/apps/sntp.c b/components/net/lwip-1.3.2/apps/sntp.c deleted file mode 100644 index a2fe2cf967..0000000000 --- a/components/net/lwip-1.3.2/apps/sntp.c +++ /dev/null @@ -1,213 +0,0 @@ -/** - * @file - * SNTP client module - * - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/sys.h" -#include "lwip/sockets.h" - -#include -#include - -/** This is an example of a "SNTP" client (with socket API). - * - * For a list of some public NTP servers, see this link : - * http://support.ntp.org/bin/view/Servers/NTPPoolServers - * - */ - -/** - * SNTP_DEBUG: Enable debugging for SNTP. - */ -#ifndef SNTP_DEBUG -#define SNTP_DEBUG LWIP_DBG_ON -#endif - -/** SNTP server port */ -#ifndef SNTP_PORT -#define SNTP_PORT 123 -#endif - -/** SNTP server address as IPv4 address in "u32_t" format */ -#ifndef SNTP_SERVER_ADDRESS -#define SNTP_SERVER_ADDRESS inet_addr("213.161.194.93") /* pool.ntp.org */ -#endif - -/** SNTP receive timeout - in milliseconds */ -#ifndef SNTP_RECV_TIMEOUT -#define SNTP_RECV_TIMEOUT 3000 -#endif - -/** SNTP update delay - in milliseconds */ -#ifndef SNTP_UPDATE_DELAY -#define SNTP_UPDATE_DELAY 60000 -#endif - -/** SNTP macro to change system time and/or the update the RTC clock */ -#ifndef SNTP_SYSTEM_TIME -#define SNTP_SYSTEM_TIME(t) -#endif - -/* SNTP protocol defines */ -#define SNTP_MAX_DATA_LEN 48 -#define SNTP_RCV_TIME_OFS 32 -#define SNTP_LI_NO_WARNING 0x00 -#define SNTP_VERSION (4/* NTP Version 4*/<<3) -#define SNTP_MODE_CLIENT 0x03 -#define SNTP_MODE_SERVER 0x04 -#define SNTP_MODE_BROADCAST 0x05 -#define SNTP_MODE_MASK 0x07 - -/* number of seconds between 1900 and 1970 */ -#define DIFF_SEC_1900_1970 (2208988800) - -/** - * SNTP processing - */ -static void sntp_process( time_t t) -{ - /* change system time and/or the update the RTC clock */ - SNTP_SYSTEM_TIME(t); - - /* display local time from GMT time */ - LWIP_DEBUGF( SNTP_DEBUG, ("sntp_process: %s", ctime(&t))); -} - -/** - * SNTP request - */ -static void sntp_request() -{ - int sock; - struct sockaddr_in local; - struct sockaddr_in to; - int tolen; - int size; - int timeout; - u8_t sntp_request [SNTP_MAX_DATA_LEN]; - u8_t sntp_response[SNTP_MAX_DATA_LEN]; - u32_t sntp_server_address; - u32_t timestamp; - time_t t; - - /* initialize SNTP server address */ - sntp_server_address = SNTP_SERVER_ADDRESS; - - /* if we got a valid SNTP server address... */ - if (sntp_server_address!=0) - { - /* create new socket */ - sock = socket( AF_INET, SOCK_DGRAM, 0); - if (sock>=0) - { - /* prepare local address */ - memset(&local, 0, sizeof(local)); - local.sin_family = AF_INET; - local.sin_port = htons(INADDR_ANY); - local.sin_addr.s_addr = htonl(INADDR_ANY); - - /* bind to local address */ - if (bind( sock, (struct sockaddr *)&local, sizeof(local))==0) - { - /* set recv timeout */ - timeout = SNTP_RECV_TIMEOUT; - setsockopt( sock, SOL_SOCKET, SO_RCVTIMEO, (char *)&timeout, sizeof(timeout)); - - /* prepare SNTP request */ - memset( sntp_request, 0, sizeof(sntp_request)); - sntp_request[0] = SNTP_LI_NO_WARNING | SNTP_VERSION | SNTP_MODE_CLIENT; - - /* prepare SNTP server address */ - memset(&to, 0, sizeof(to)); - to.sin_family = AF_INET; - to.sin_port = htons(SNTP_PORT); - to.sin_addr.s_addr = sntp_server_address; - - /* send SNTP request to server */ - if (sendto( sock, sntp_request, sizeof(sntp_request), 0, (struct sockaddr *)&to, sizeof(to))>=0) - { - /* receive SNTP server response */ - tolen = sizeof(to); - size = recvfrom( sock, sntp_response, sizeof(sntp_response), 0, (struct sockaddr *)&to, (socklen_t *)&tolen); - - /* if the response size is good */ - if (size == SNTP_MAX_DATA_LEN) - { - /* if this is a SNTP response... */ - if (((sntp_response[0] & SNTP_MODE_MASK) == SNTP_MODE_SERVER) || ((sntp_response[0] & SNTP_MODE_MASK) == SNTP_MODE_BROADCAST)) - { - /* extract GMT time from response */ - SMEMCPY( ×tamp, (sntp_response+SNTP_RCV_TIME_OFS), sizeof(timestamp)); - t = (ntohl(timestamp) - DIFF_SEC_1900_1970); - - /* do time processing */ - sntp_process(t); - - } - else - { - LWIP_DEBUGF( SNTP_DEBUG, ("sntp_request: not response frame code\n")); - } - } - else - { - LWIP_DEBUGF( SNTP_DEBUG, ("sntp_request: not recvfrom==%i\n", errno)); - } - } - else - { - LWIP_DEBUGF( SNTP_DEBUG, ("sntp_request: not sendto==%i\n", errno)); - } - } - /* close the socket */ - closesocket(sock); - } - } -} - -/** - * SNTP thread - */ -static void -sntp_thread(void *arg) -{ - LWIP_UNUSED_ARG(arg); - while(1) - { - sntp_request(); - sys_msleep(SNTP_UPDATE_DELAY); - } -} - -void sntp_init(void) -{ - sys_thread_new("sntp_thread", sntp_thread, NULL, DEFAULT_THREAD_STACKSIZE, DEFAULT_THREAD_PRIO); -} diff --git a/components/net/lwip-1.3.2/apps/tcpecho.c b/components/net/lwip-1.3.2/apps/tcpecho.c deleted file mode 100644 index 3d5ec27de7..0000000000 --- a/components/net/lwip-1.3.2/apps/tcpecho.c +++ /dev/null @@ -1,68 +0,0 @@ -#include - -#define TCP_ECHO_PORT 7 - -void tcpecho_entry(void *parameter) -{ - struct netconn *conn, *newconn; - err_t err; - - /* Create a new connection identifier. */ - conn = netconn_new(NETCONN_TCP); - - /* Bind connection to well known port number 7. */ - netconn_bind(conn, NULL, TCP_ECHO_PORT); - - /* Tell connection to go into listening mode. */ - netconn_listen(conn); - - while(1) - { - /* Grab new connection. */ - newconn = netconn_accept(conn); - /* Process the new connection. */ - if(newconn != NULL) - { - struct netbuf *buf; - void *data; - u16_t len; - - while((buf = netconn_recv(newconn)) != NULL) - { - do - { - netbuf_data(buf, &data, &len); - err = netconn_write(newconn, data, len, NETCONN_COPY); - if(err != ERR_OK){} - } - while(netbuf_next(buf) >= 0); - netbuf_delete(buf); - } - /* Close connection and discard connection identifier. */ - netconn_delete(newconn); - } - } -} - -#ifdef RT_USING_FINSH -#include -static rt_thread_t echo_tid = RT_NULL; -void tcpecho(rt_uint32_t startup) -{ - if (startup && echo_tid == RT_NULL) - { - echo_tid = rt_thread_create("echo", - tcpecho_entry, RT_NULL, - 512, 30, 5); - if (echo_tid != RT_NULL) - rt_thread_startup(echo_tid); - } - else - { - if (echo_tid != RT_NULL) - rt_thread_delete(echo_tid); /* delete thread */ - echo_tid = RT_NULL; - } -} -FINSH_FUNCTION_EXPORT(tcpecho, startup or stop TCP echo server); -#endif diff --git a/components/net/lwip-1.3.2/apps/tftp.c b/components/net/lwip-1.3.2/apps/tftp.c deleted file mode 100644 index df5d24162f..0000000000 --- a/components/net/lwip-1.3.2/apps/tftp.c +++ /dev/null @@ -1,206 +0,0 @@ -#include -#include -#include - -#include - -#define TFTP_PORT 69 -/* opcode */ -#define TFTP_RRQ 1 /* read request */ -#define TFTP_WRQ 2 /* write request */ -#define TFTP_DATA 3 /* data */ -#define TFTP_ACK 4 /* ACK */ -#define TFTP_ERROR 5 /* error */ - -rt_uint8_t tftp_buffer[512 + 4]; -/* tftp client */ -void tftp_get(const char* host, const char* dir, const char* filename) -{ - int fd, sock_fd, sock_opt; - struct sockaddr_in tftp_addr, from_addr; - rt_uint32_t length; - socklen_t fromlen; - - /* make local file name */ - rt_snprintf((char*)tftp_buffer, sizeof(tftp_buffer), - "%s/%s", dir, filename); - - /* open local file for write */ - fd = open((char*)tftp_buffer, O_RDWR | O_CREAT, 0); - if (fd < 0) - { - rt_kprintf("can't open local filename\n"); - return; - } - - /* connect to tftp server */ - inet_aton(host, (struct in_addr*)&(tftp_addr.sin_addr)); - tftp_addr.sin_family = AF_INET; - tftp_addr.sin_port = htons(TFTP_PORT); - - sock_fd = socket(AF_INET,SOCK_DGRAM,IPPROTO_UDP); - if (sock_fd < 0) - { - close(fd); - rt_kprintf("can't create a socket\n"); - return ; - } - - /* set socket option */ - sock_opt = 5000; /* 5 seconds */ - lwip_setsockopt(sock_fd, SOL_SOCKET, SO_RCVTIMEO, &sock_opt, sizeof(sock_opt)); - - /* make tftp request */ - tftp_buffer[0] = 0; /* opcode */ - tftp_buffer[1] = TFTP_RRQ; /* RRQ */ - length = rt_sprintf((char *)&tftp_buffer[2], "%s", filename) + 2; - tftp_buffer[length] = 0; length ++; - length += rt_sprintf((char*)&tftp_buffer[length], "%s", "octet"); - tftp_buffer[length] = 0; length ++; - - fromlen = sizeof(struct sockaddr_in); - - /* send request */ - lwip_sendto(sock_fd, tftp_buffer, length, 0, - (struct sockaddr *)&tftp_addr, fromlen); - - do - { - length = lwip_recvfrom(sock_fd, tftp_buffer, sizeof(tftp_buffer), 0, - (struct sockaddr *)&from_addr, &fromlen); - - if (length > 0) - { - write(fd, (char*)&tftp_buffer[4], length - 4); - rt_kprintf("#"); - - /* make ACK */ - tftp_buffer[0] = 0; tftp_buffer[1] = TFTP_ACK; /* opcode */ - /* send ACK */ - lwip_sendto(sock_fd, tftp_buffer, 4, 0, - (struct sockaddr *)&from_addr, fromlen); - } - } while (length == 516); - - if (length == 0) rt_kprintf("timeout\n"); - else rt_kprintf("done\n"); - - close(fd); - lwip_close(sock_fd); -} -FINSH_FUNCTION_EXPORT(tftp_get, get file from tftp server); - -void tftp_put(const char* host, const char* dir, const char* filename) -{ - int fd, sock_fd, sock_opt; - struct sockaddr_in tftp_addr, from_addr; - rt_uint32_t length, block_number = 0; - socklen_t fromlen; - - /* make local file name */ - rt_snprintf((char*)tftp_buffer, sizeof(tftp_buffer), - "%s/%s", dir, filename); - - /* open local file for write */ - fd = open((char*)tftp_buffer, O_RDONLY, 0); - if (fd < 0) - { - rt_kprintf("can't open local filename\n"); - return; - } - - /* connect to tftp server */ - inet_aton(host, (struct in_addr*)&(tftp_addr.sin_addr)); - tftp_addr.sin_family = AF_INET; - tftp_addr.sin_port = htons(TFTP_PORT); - - sock_fd = socket(AF_INET,SOCK_DGRAM,IPPROTO_UDP); - if (sock_fd < 0) - { - close(fd); - rt_kprintf("can't create a socket\n"); - return ; - } - - /* set socket option */ - sock_opt = 5000; /* 5 seconds */ - lwip_setsockopt(sock_fd, SOL_SOCKET, SO_RCVTIMEO, &sock_opt, sizeof(sock_opt)); - - /* make tftp request */ - tftp_buffer[0] = 0; /* opcode */ - tftp_buffer[1] = TFTP_WRQ; /* WRQ */ - length = rt_sprintf((char *)&tftp_buffer[2], "%s", filename) + 2; - tftp_buffer[length] = 0; length ++; - length += rt_sprintf((char*)&tftp_buffer[length], "%s", "octet"); - tftp_buffer[length] = 0; length ++; - - fromlen = sizeof(struct sockaddr_in); - - /* send request */ - lwip_sendto(sock_fd, tftp_buffer, length, 0, - (struct sockaddr *)&tftp_addr, fromlen); - - /* wait ACK 0 */ - length = lwip_recvfrom(sock_fd, tftp_buffer, sizeof(tftp_buffer), 0, - (struct sockaddr *)&from_addr, &fromlen); - if (!(tftp_buffer[0] == 0 && - tftp_buffer[1] == TFTP_ACK && - tftp_buffer[2] == 0 && - tftp_buffer[3] == 0)) - { - rt_kprintf("tftp server error\n"); - close(fd); - return; - } - - block_number = 1; - - while (1) - { - length = read(fd, (char*)&tftp_buffer[4], 512); - if (length > 0) - { - /* make opcode and block number */ - tftp_buffer[0] = 0; tftp_buffer[1] = TFTP_DATA; - tftp_buffer[2] = (block_number >> 8) & 0xff; - tftp_buffer[3] = block_number & 0xff; - - lwip_sendto(sock_fd, tftp_buffer, length + 4, 0, - (struct sockaddr *)&from_addr, fromlen); - } - else - { - rt_kprintf("done\n"); - break; /* no data yet */ - } - - /* receive ack */ - length = lwip_recvfrom(sock_fd, tftp_buffer, sizeof(tftp_buffer), 0, - (struct sockaddr *)&from_addr, &fromlen); - if (length > 0) - { - if ((tftp_buffer[0] == 0 && - tftp_buffer[1] == TFTP_ACK && - tftp_buffer[2] == (block_number >> 8) & 0xff) && - tftp_buffer[3] == (block_number & 0xff)) - { - block_number ++; - rt_kprintf("#"); - } - else - { - rt_kprintf("server respondes with an error\n"); - break; - } - } - else if (length == 0) - { - rt_kprintf("server timeout\n"); - break; - } - } - - close(fd); - lwip_close(sock_fd); -} -FINSH_FUNCTION_EXPORT(tftp_put, put file to tftp server); diff --git a/components/net/lwip-1.3.2/apps/udpecho.c b/components/net/lwip-1.3.2/apps/udpecho.c deleted file mode 100644 index c9e07d099d..0000000000 --- a/components/net/lwip-1.3.2/apps/udpecho.c +++ /dev/null @@ -1,56 +0,0 @@ -#include - -#define UDP_ECHO_PORT 7 - -void udpecho_entry(void *parameter) -{ - struct netconn *conn; - struct netbuf *buf; - struct ip_addr *addr; - unsigned short port; - - conn = netconn_new(NETCONN_UDP); - netconn_bind(conn, IP_ADDR_ANY, 7); - - while(1) - { - /* received data to buffer */ - buf = netconn_recv(conn); - - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - - /* send the data to buffer */ - netconn_connect(conn, addr, port); - - /* reset address, and send to client */ - buf->addr = RT_NULL; - netconn_send(conn, buf); - - /* release buffer */ - netbuf_delete(buf); - } -} - -#ifdef RT_USING_FINSH -#include -static rt_thread_t echo_tid = RT_NULL; -void udpecho(rt_uint32_t startup) -{ - if (startup && echo_tid == RT_NULL) - { - echo_tid = rt_thread_create("uecho", - udpecho_entry, RT_NULL, - 512, 30, 5); - if (echo_tid != RT_NULL) - rt_thread_startup(echo_tid); - } - else - { - if (echo_tid != RT_NULL) - rt_thread_delete(echo_tid); /* delete thread */ - echo_tid = RT_NULL; - } -} -FINSH_FUNCTION_EXPORT(udpecho, startup or stop UDP echo server); -#endif diff --git a/components/net/lwip-1.3.2/doc/rawapi.txt b/components/net/lwip-1.3.2/doc/rawapi.txt deleted file mode 100644 index 8eec6e786c..0000000000 --- a/components/net/lwip-1.3.2/doc/rawapi.txt +++ /dev/null @@ -1,478 +0,0 @@ -Raw TCP/IP interface for lwIP - -Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons - -lwIP provides three Application Program's Interfaces (APIs) for programs -to use for communication with the TCP/IP code: -* low-level "core" / "callback" or "raw" API. -* higher-level "sequential" API. -* BSD-style socket API. - -The sequential API provides a way for ordinary, sequential, programs -to use the lwIP stack. It is quite similar to the BSD socket API. The -model of execution is based on the blocking open-read-write-close -paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP -code and the application program must reside in different execution -contexts (threads). - -The socket API is a compatibility API for existing applications, -currently it is built on top of the sequential API. It is meant to -provide all functions needed to run socket API applications running -on other platforms (e.g. unix / windows etc.). However, due to limitations -in the specification of this API, there might be incompatibilities -that require small modifications of existing programs. - -** Threading - -lwIP started targeting single-threaded environments. When adding multi- -threading support, instead of making the core thread-safe, another -approach was chosen: there is one main thread running the lwIP core -(also known as the "tcpip_thread"). The raw API may only be used from -this thread! Application threads using the sequential- or socket API -communicate with this main thread through message passing. - - As such, the list of functions that may be called from - other threads or an ISR is very limited! Only functions - from these API header files are thread-safe: - - api.h - - netbuf.h - - netdb.h - - netifapi.h - - sockets.h - - sys.h - - Additionaly, memory (de-)allocation functions may be - called from multiple threads (not ISR!) with NO_SYS=0 - since they are protected by SYS_LIGHTWEIGHT_PROT and/or - semaphores. - - Only since 1.3.0, if SYS_LIGHTWEIGHT_PROT is set to 1 - and LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT is set to 1, - pbuf_free() may also be called from another thread or - an ISR (since only then, mem_free - for PBUF_RAM - may - be called from an ISR: otherwise, the HEAP is only - protected by semaphores). - - -** The remainder of this document discusses the "raw" API. ** - -The raw TCP/IP interface allows the application program to integrate -better with the TCP/IP code. Program execution is event based by -having callback functions being called from within the TCP/IP -code. The TCP/IP code and the application program both run in the same -thread. The sequential API has a much higher overhead and is not very -well suited for small systems since it forces a multithreaded paradigm -on the application. - -The raw TCP/IP interface is not only faster in terms of code execution -time but is also less memory intensive. The drawback is that program -development is somewhat harder and application programs written for -the raw TCP/IP interface are more difficult to understand. Still, this -is the preferred way of writing applications that should be small in -code size and memory usage. - -Both APIs can be used simultaneously by different application -programs. In fact, the sequential API is implemented as an application -program using the raw TCP/IP interface. - ---- Callbacks - -Program execution is driven by callbacks. Each callback is an ordinary -C function that is called from within the TCP/IP code. Every callback -function is passed the current TCP or UDP connection state as an -argument. Also, in order to be able to keep program specific state, -the callback functions are called with a program specified argument -that is independent of the TCP/IP state. - -The function for setting the application connection state is: - -- void tcp_arg(struct tcp_pcb *pcb, void *arg) - - Specifies the program specific state that should be passed to all - other callback functions. The "pcb" argument is the current TCP - connection control block, and the "arg" argument is the argument - that will be passed to the callbacks. - - ---- TCP connection setup - -The functions used for setting up connections is similar to that of -the sequential API and of the BSD socket API. A new TCP connection -identifier (i.e., a protocol control block - PCB) is created with the -tcp_new() function. This PCB can then be either set to listen for new -incoming connections or be explicitly connected to another host. - -- struct tcp_pcb *tcp_new(void) - - Creates a new connection identifier (PCB). If memory is not - available for creating the new pcb, NULL is returned. - -- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Binds the pcb to a local IP address and port number. The IP address - can be specified as IP_ADDR_ANY in order to bind the connection to - all local IP addresses. - - If another connection is bound to the same port, the function will - return ERR_USE, otherwise ERR_OK is returned. - -- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb) - - Commands a pcb to start listening for incoming connections. When an - incoming connection is accepted, the function specified with the - tcp_accept() function will be called. The pcb will have to be bound - to a local port with the tcp_bind() function. - - The tcp_listen() function returns a new connection identifier, and - the one passed as an argument to the function will be - deallocated. The reason for this behavior is that less memory is - needed for a connection that is listening, so tcp_listen() will - reclaim the memory needed for the original connection and allocate a - new smaller memory block for the listening connection. - - tcp_listen() may return NULL if no memory was available for the - listening connection. If so, the memory associated with the pcb - passed as an argument to tcp_listen() will not be deallocated. - -- struct tcp_pcb *tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) - - Same as tcp_listen, but limits the number of outstanding connections - in the listen queue to the value specified by the backlog argument. - To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h. - -- void tcp_accepted(struct tcp_pcb *pcb) - - Inform lwIP that an incoming connection has been accepted. This would - usually be called from the accept callback. This allows lwIP to perform - housekeeping tasks, such as allowing further incoming connections to be - queued in the listen backlog. - -- void tcp_accept(struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, - err_t err)) - - Specified the callback function that should be called when a new - connection arrives on a listening connection. - -- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port, err_t (* connected)(void *arg, - struct tcp_pcb *tpcb, - err_t err)); - - Sets up the pcb to connect to the remote host and sends the - initial SYN segment which opens the connection. - - The tcp_connect() function returns immediately; it does not wait for - the connection to be properly setup. Instead, it will call the - function specified as the fourth argument (the "connected" argument) - when the connection is established. If the connection could not be - properly established, either because the other host refused the - connection or because the other host didn't answer, the "err" - callback function of this pcb (registered with tcp_err, see below) - will be called. - - The tcp_connect() function can return ERR_MEM if no memory is - available for enqueueing the SYN segment. If the SYN indeed was - enqueued successfully, the tcp_connect() function returns ERR_OK. - - ---- Sending TCP data - -TCP data is sent by enqueueing the data with a call to -tcp_write(). When the data is successfully transmitted to the remote -host, the application will be notified with a call to a specified -callback function. - -- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len, - u8_t copy) - - Enqueues the data pointed to by the argument dataptr. The length of - the data is passed as the len parameter. The copy argument is either - 0 or 1 and indicates whether the new memory should be allocated for - the data to be copied into. If the argument is 0, no new memory - should be allocated and the data should only be referenced by - pointer. - - The tcp_write() function will fail and return ERR_MEM if the length - of the data exceeds the current send buffer size or if the length of - the queue of outgoing segment is larger than the upper limit defined - in lwipopts.h. The number of bytes available in the output queue can - be retrieved with the tcp_sndbuf() function. - - The proper way to use this function is to call the function with at - most tcp_sndbuf() bytes of data. If the function returns ERR_MEM, - the application should wait until some of the currently enqueued - data has been successfully received by the other host and try again. - -- void tcp_sent(struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, - u16_t len)) - - Specifies the callback function that should be called when data has - successfully been received (i.e., acknowledged) by the remote - host. The len argument passed to the callback function gives the - amount bytes that was acknowledged by the last acknowledgment. - - ---- Receiving TCP data - -TCP data reception is callback based - an application specified -callback function is called when new data arrives. When the -application has taken the data, it has to call the tcp_recved() -function to indicate that TCP can advertise increase the receive -window. - -- void tcp_recv(struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err)) - - Sets the callback function that will be called when new data - arrives. The callback function will be passed a NULL pbuf to - indicate that the remote host has closed the connection. If - there are no errors and the callback function is to return - ERR_OK, then it must free the pbuf. Otherwise, it must not - free the pbuf so that lwIP core code can store it. - -- void tcp_recved(struct tcp_pcb *pcb, u16_t len) - - Must be called when the application has received the data. The len - argument indicates the length of the received data. - - ---- Application polling - -When a connection is idle (i.e., no data is either transmitted or -received), lwIP will repeatedly poll the application by calling a -specified callback function. This can be used either as a watchdog -timer for killing connections that have stayed idle for too long, or -as a method of waiting for memory to become available. For instance, -if a call to tcp_write() has failed because memory wasn't available, -the application may use the polling functionality to call tcp_write() -again when the connection has been idle for a while. - -- void tcp_poll(struct tcp_pcb *pcb, u8_t interval, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb)) - - Specifies the polling interval and the callback function that should - be called to poll the application. The interval is specified in - number of TCP coarse grained timer shots, which typically occurs - twice a second. An interval of 10 means that the application would - be polled every 5 seconds. - - ---- Closing and aborting connections - -- err_t tcp_close(struct tcp_pcb *pcb) - - Closes the connection. The function may return ERR_MEM if no memory - was available for closing the connection. If so, the application - should wait and try again either by using the acknowledgment - callback or the polling functionality. If the close succeeds, the - function returns ERR_OK. - - The pcb is deallocated by the TCP code after a call to tcp_close(). - -- void tcp_abort(struct tcp_pcb *pcb) - - Aborts the connection by sending a RST (reset) segment to the remote - host. The pcb is deallocated. This function never fails. - -If a connection is aborted because of an error, the application is -alerted of this event by the err callback. Errors that might abort a -connection are when there is a shortage of memory. The callback -function to be called is set using the tcp_err() function. - -- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg, - err_t err)) - - The error callback function does not get the pcb passed to it as a - parameter since the pcb may already have been deallocated. - - ---- Lower layer TCP interface - -TCP provides a simple interface to the lower layers of the -system. During system initialization, the function tcp_init() has -to be called before any other TCP function is called. When the system -is running, the two timer functions tcp_fasttmr() and tcp_slowtmr() -must be called with regular intervals. The tcp_fasttmr() should be -called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and -tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. - - ---- UDP interface - -The UDP interface is similar to that of TCP, but due to the lower -level of complexity of UDP, the interface is significantly simpler. - -- struct udp_pcb *udp_new(void) - - Creates a new UDP pcb which can be used for UDP communication. The - pcb is not active until it has either been bound to a local address - or connected to a remote address. - -- void udp_remove(struct udp_pcb *pcb) - - Removes and deallocates the pcb. - -- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Binds the pcb to a local address. The IP-address argument "ipaddr" - can be IP_ADDR_ANY to indicate that it should listen to any local IP - address. The function currently always return ERR_OK. - -- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Sets the remote end of the pcb. This function does not generate any - network traffic, but only set the remote address of the pcb. - -- err_t udp_disconnect(struct udp_pcb *pcb) - - Remove the remote end of the pcb. This function does not generate - any network traffic, but only removes the remote address of the pcb. - -- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p) - - Sends the pbuf p. The pbuf is not deallocated. - -- void udp_recv(struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, - struct pbuf *p, - struct ip_addr *addr, - u16_t port), - void *recv_arg) - - Specifies a callback function that should be called when a UDP - datagram is received. - - ---- System initalization - -A truly complete and generic sequence for initializing the lwip stack -cannot be given because it depends on the build configuration (lwipopts.h) -and additional initializations for your runtime environment (e.g. timers). - -We can give you some idea on how to proceed when using the raw API. -We assume a configuration using a single Ethernet netif and the -UDP and TCP transport layers, IPv4 and the DHCP client. - -Call these functions in the order of appearance: - -- stats_init() - - Clears the structure where runtime statistics are gathered. - -- sys_init() - - Not of much use since we set the NO_SYS 1 option in lwipopts.h, - to be called for easy configuration changes. - -- mem_init() - - Initializes the dynamic memory heap defined by MEM_SIZE. - -- memp_init() - - Initializes the memory pools defined by MEMP_NUM_x. - -- pbuf_init() - - Initializes the pbuf memory pool defined by PBUF_POOL_SIZE. - -- etharp_init() - - Initializes the ARP table and queue. - Note: you must call etharp_tmr at a ARP_TMR_INTERVAL (5 seconds) regular interval - after this initialization. - -- ip_init() - - Doesn't do much, it should be called to handle future changes. - -- udp_init() - - Clears the UDP PCB list. - -- tcp_init() - - Clears the TCP PCB list and clears some internal TCP timers. - Note: you must call tcp_fasttmr() and tcp_slowtmr() at the - predefined regular intervals after this initialization. - -- netif_add(struct netif *netif, struct ip_addr *ipaddr, - struct ip_addr *netmask, struct ip_addr *gw, - void *state, err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) - - Adds your network interface to the netif_list. Allocate a struct - netif and pass a pointer to this structure as the first argument. - Give pointers to cleared ip_addr structures when using DHCP, - or fill them with sane numbers otherwise. The state pointer may be NULL. - - The init function pointer must point to a initialization function for - your ethernet netif interface. The following code illustrates it's use. - - err_t netif_if_init(struct netif *netif) - { - u8_t i; - - for(i = 0; i < ETHARP_HWADDR_LEN; i++) netif->hwaddr[i] = some_eth_addr[i]; - init_my_eth_device(); - return ERR_OK; - } - - For ethernet drivers, the input function pointer must point to the lwip - function ethernet_input() declared in "netif/etharp.h". Other drivers - must use ip_input() declared in "lwip/ip.h". - -- netif_set_default(struct netif *netif) - - Registers the default network interface. - -- netif_set_up(struct netif *netif) - - When the netif is fully configured this function must be called. - -- dhcp_start(struct netif *netif) - - Creates a new DHCP client for this interface on the first call. - Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at - the predefined regular intervals after starting the client. - - You can peek in the netif->dhcp struct for the actual DHCP status. - - ---- Optimalization hints - -The first thing you want to optimize is the lwip_standard_checksum() -routine from src/core/inet.c. You can override this standard -function with the #define LWIP_CHKSUM . - -There are C examples given in inet.c or you might want to -craft an assembly function for this. RFC1071 is a good -introduction to this subject. - -Other significant improvements can be made by supplying -assembly or inline replacements for htons() and htonl() -if you're using a little-endian architecture. -#define LWIP_PLATFORM_BYTESWAP 1 -#define LWIP_PLATFORM_HTONS(x) -#define LWIP_PLATFORM_HTONL(x) - -Check your network interface driver if it reads at -a higher speed than the maximum wire-speed. If the -hardware isn't serviced frequently and fast enough -buffer overflows are likely to occur. - -E.g. when using the cs8900 driver, call cs8900if_service(ethif) -as frequently as possible. When using an RTOS let the cs8900 interrupt -wake a high priority task that services your driver using a binary -semaphore or event flag. Some drivers might allow additional tuning -to match your application and network. - -For a production release it is recommended to set LWIP_STATS to 0. -Note that speed performance isn't influenced much by simply setting -high values to the memory options. diff --git a/components/net/lwip-1.3.2/doc/savannah.txt b/components/net/lwip-1.3.2/doc/savannah.txt deleted file mode 100644 index 409905b10c..0000000000 --- a/components/net/lwip-1.3.2/doc/savannah.txt +++ /dev/null @@ -1,135 +0,0 @@ -Daily Use Guide for using Savannah for lwIP - -Table of Contents: - -1 - Obtaining lwIP from the CVS repository -2 - Committers/developers CVS access using SSH (to be written) -3 - Merging from DEVEL branch to main trunk (stable branch) -4 - How to release lwIP - - - -1 Obtaining lwIP from the CVS repository ----------------------------------------- - -To perform an anonymous CVS checkout of the main trunk (this is where -bug fixes and incremental enhancements occur), do this: - -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip - -Or, obtain a stable branch (updated with bug fixes only) as follows: -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_7 -d lwip-0.7 lwip - -Or, obtain a specific (fixed) release as follows: -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_7_0 -d lwip-0.7.0 lwip - -3 Committers/developers CVS access using SSH --------------------------------------------- - -The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption. -As such, CVS commits to the server occur through a SSH tunnel for project members. -To create a SSH2 key pair in UNIX-like environments, do this: - -ssh-keygen -t dsa - -Under Windows, a recommended SSH client is "PuTTY", freely available with good -documentation and a graphic user interface. Use its key generator. - -Now paste the id_dsa.pub contents into your Savannah account public key list. Wait -a while so that Savannah can update its configuration (This can take minutes). - -Try to login using SSH: - -ssh -v your_login@cvs.sv.gnu.org - -If it tells you: - -Authenticating with public key "your_key_name"... -Server refused to allocate pty - -then you could login; Savannah refuses to give you a shell - which is OK, as we -are allowed to use SSH for CVS only. Now, you should be able to do this: - -export CVS_RSH=ssh -cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip - -after which you can edit your local files with bug fixes or new features and -commit them. Make sure you know what you are doing when using CVS to make -changes on the repository. If in doubt, ask on the lwip-members mailing list. - -(If SSH asks about authenticity of the host, you can check the key - fingerprint against http://savannah.nongnu.org/cvs/?group=lwip) - - -3 Merging from DEVEL branch to main trunk (stable) --------------------------------------------------- - -Merging is a delicate process in CVS and requires the -following disciplined steps in order to prevent conflicts -in the future. Conflicts can be hard to solve! - -Merging from branch A to branch B requires that the A branch -has a tag indicating the previous merger. This tag is called -'merged_from_A_to_B'. After merging, the tag is moved in the -A branch to remember this merger for future merge actions. - -IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE -REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE -MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME). - -Merge all changes in DEVEL since our last merge to main: - -In the working copy of the main trunk: -cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL - -(This will apply the changes between 'merged_from_DEVEL_to_main' -and 'DEVEL' to your work set of files) - -We can now commit the merge result. -cvs commit -R -m "Merged from DEVEL to main." - -If this worked out OK, we now move the tag in the DEVEL branch -to this merge point, so we can use this point for future merges: - -cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip - -4 How to release lwIP ---------------------- - -First, checkout a clean copy of the branch to be released. Tag this set with -tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example). - -Login CVS using pserver authentication, then export a clean copy of the -tagged tree. Export is similar to a checkout, except that the CVS metadata -is not created locally. - -export CVS_RSH=ssh -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_6_3 -d lwip-0.6.3 lwip - -Archive this directory using tar, gzip'd, bzip2'd and zip'd. - -tar czvf lwip-0.6.3.tar.gz lwip-0.6.3 -tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3 -zip -r lwip-0.6.3.zip lwip-0.6.3 - -Now, sign the archives with a detached GPG binary signature as follows: - -gpg -b lwip-0.6.3.tar.gz -gpg -b lwip-0.6.3.tar.bz2 -gpg -b lwip-0.6.3.zip - -Upload these files using anonymous FTP: -ncftp ftp://savannah.gnu.org/incoming/savannah/lwip - -ncftp>mput *0.6.3.* - -Additionally, you may post a news item on Savannah, like this: - -A new 0.6.3 release is now available here: -http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3 - -You will have to submit this via the user News interface, then approve -this via the Administrator News interface. \ No newline at end of file diff --git a/components/net/lwip-1.3.2/doc/snmp_agent.txt b/components/net/lwip-1.3.2/doc/snmp_agent.txt deleted file mode 100644 index 9b58616a62..0000000000 --- a/components/net/lwip-1.3.2/doc/snmp_agent.txt +++ /dev/null @@ -1,181 +0,0 @@ -SNMPv1 agent for lwIP - -Author: Christiaan Simons - -This is a brief introduction how to use and configure the SNMP agent. -Note the agent uses the raw-API UDP interface so you may also want to -read rawapi.txt to gain a better understanding of the SNMP message handling. - -0 Agent Capabilities -==================== - -SNMPv1 per RFC1157 - This is an old(er) standard but is still widely supported. - For SNMPv2c and v3 have a greater complexity and need many - more lines of code. IMHO this breaks the idea of "lightweight IP". - - Note the S in SNMP stands for "Simple". Note that "Simple" is - relative. SNMP is simple compared to the complex ISO network - management protocols CMIP (Common Management Information Protocol) - and CMOT (CMip Over Tcp). - -MIB II per RFC1213 - The standard lwIP stack management information base. - This is a required MIB, so this is always enabled. - When builing lwIP without TCP, the mib-2.tcp group is omitted. - The groups EGP, CMOT and transmission are disabled by default. - - Most mib-2 objects are not writable except: - sysName, sysLocation, sysContact, snmpEnableAuthenTraps. - Writing to or changing the ARP and IP address and route - tables is not possible. - - Note lwIP has a very limited notion of IP routing. It currently - doen't have a route table and doesn't have a notion of the U,G,H flags. - Instead lwIP uses the interface list with only one default interface - acting as a single gateway interface (G) for the default route. - - The agent returns a "virtual table" with the default route 0.0.0.0 - for the default interface and network routes (no H) for each - network interface in the netif_list. - All routes are considered to be up (U). - -Loading additional MIBs - MIBs can only be added in compile-time, not in run-time. - There is no MIB compiler thus additional MIBs must be hand coded. - -Large SNMP message support - The packet decoding and encoding routines are designed - to use pbuf-chains. Larger payloads then the minimum - SNMP requirement of 484 octets are supported if the - PBUF_POOL_SIZE and IP_REASS_BUFSIZE are set to match your - local requirement. - -1 Building the Agent -==================== - -First of all you'll need to add the following define -to your local lwipopts.h: - -#define LWIP_SNMP 1 - -and add the source files in lwip/src/core/snmp -and some snmp headers in lwip/src/include/lwip to your makefile. - -Note you'll might need to adapt you network driver to update -the mib2 variables for your interface. - -2 Running the Agent -=================== - -The following function calls must be made in your program to -actually get the SNMP agent running. - -Before starting the agent you should supply pointers -to non-volatile memory for sysContact, sysLocation, -and snmpEnableAuthenTraps. You can do this by calling - -snmp_set_syscontact() -snmp_set_syslocation() -snmp_set_snmpenableauthentraps() - -Additionally you may want to set - -snmp_set_sysdescr() -snmp_set_sysobjid() (if you have a private MIB) -snmp_set_sysname() - -Also before starting the agent you need to setup -one or more trap destinations using these calls: - -snmp_trap_dst_enable(); -snmp_trap_dst_ip_set(); - -In the lwIP initialisation sequence call snmp_init() just after -the call to udp_init(). - -Exactly every 10 msec the SNMP uptime timestamp must be updated with -snmp_inc_sysuptime(). You should call this from a timer interrupt -or a timer signal handler depending on your runtime environment. - -An alternative way to update the SNMP uptime timestamp is to do a call like -snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but call to -a lower frequency). Another one is to not call snmp_inc_sysuptime() or -snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro. -This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside -snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only -when it's queried (any function which need "sysuptime" have to call -snmp_get_sysuptime). - - -3 Private MIBs -============== - -If want to extend the agent with your own private MIB you'll need to -add the following define to your local lwipopts.h: - -#define SNMP_PRIVATE_MIB 1 - -You must provide the private_mib.h and associated files yourself. -Note we don't have a "MIB compiler" that generates C source from a MIB, -so you're required to do some serious coding if you enable this! - -Note the lwIP enterprise ID (26381) is assigned to the lwIP project, -ALL OBJECT IDENTIFIERS LIVING UNDER THIS ID ARE ASSIGNED BY THE lwIP -MAINTAINERS! - -If you need to create your own private MIB you'll need -to apply for your own enterprise ID with IANA: http://www.iana.org/numbers.html - -You can set it by passing a struct snmp_obj_id to the agent -using snmp_set_sysobjid(&my_object_id), just before snmp_init(). - -Note the object identifiers for thes MIB-2 and your private MIB -tree must be kept in sorted ascending (lexicographical) order. -This to ensure correct getnext operation. - -An example for a private MIB is part of the "minimal Unix" project: -contrib/ports/unix/proj/minimal/lwip_prvmib.c - -The next chapter gives a more detailed description of the -MIB-2 tree and the optional private MIB. - -4 The Gory Details -================== - -4.0 Object identifiers and the MIB tree. - -We have three distinct parts for all object identifiers: - -The prefix - .iso.org.dod.internet - -the middle part - .mgmt.mib-2.ip.ipNetToMediaTable.ipNetToMediaEntry.ipNetToMediaPhysAddress - -and the index part - .1.192.168.0.1 - -Objects located above the .internet hierarchy aren't supported. -Currently only the .mgmt sub-tree is available and -when the SNMP_PRIVATE_MIB is enabled the .private tree -becomes available too. - -Object identifiers from incoming requests are checked -for a matching prefix, middle part and index part -or are expanded(*) for GetNext requests with short -or inexisting names in the request. -(* we call this "expansion" but this also -resembles the "auto-completion" operation) - -The middle part is usually located in ROM (const) -to preserve precious RAM on small microcontrollers. -However RAM location is possible for an dynamically -changing private tree. - -The index part is handled by functions which in -turn use dynamically allocated index trees from RAM. -These trees are updated by e.g. the etharp code -when new entries are made or removed form the ARP cache. - -/** @todo more gory details */ diff --git a/components/net/lwip-1.3.2/doc/sys_arch.txt b/components/net/lwip-1.3.2/doc/sys_arch.txt deleted file mode 100644 index 66310a91e4..0000000000 --- a/components/net/lwip-1.3.2/doc/sys_arch.txt +++ /dev/null @@ -1,228 +0,0 @@ -sys_arch interface for lwIP 0.6++ - -Author: Adam Dunkels - -The operating system emulation layer provides a common interface -between the lwIP code and the underlying operating system kernel. The -general idea is that porting lwIP to new architectures requires only -small changes to a few header files and a new sys_arch -implementation. It is also possible to do a sys_arch implementation -that does not rely on any underlying operating system. - -The sys_arch provides semaphores and mailboxes to lwIP. For the full -lwIP functionality, multiple threads support can be implemented in the -sys_arch, but this is not required for the basic lwIP -functionality. Previous versions of lwIP required the sys_arch to -implement timer scheduling as well but as of lwIP 0.5 this is -implemented in a higher layer. - -In addition to the source file providing the functionality of sys_arch, -the OS emulation layer must provide several header files defining -macros used throughout lwip. The files required and the macros they -must define are listed below the sys_arch description. - -Semaphores can be either counting or binary - lwIP works with both -kinds. Mailboxes are used for message passing and can be implemented -either as a queue which allows multiple messages to be posted to a -mailbox, or as a rendez-vous point where only one message can be -posted at a time. lwIP works with both kinds, but the former type will -be more efficient. A message in a mailbox is just a pointer, nothing -more. - -Semaphores are represented by the type "sys_sem_t" which is typedef'd -in the sys_arch.h file. Mailboxes are equivalently represented by the -type "sys_mbox_t". lwIP does not place any restrictions on how -sys_sem_t or sys_mbox_t are represented internally. - -The following functions must be implemented by the sys_arch: - -- void sys_init(void) - - Is called to initialize the sys_arch layer. - -- sys_sem_t sys_sem_new(u8_t count) - - Creates and returns a new semaphore. The "count" argument specifies - the initial state of the semaphore. - -- void sys_sem_free(sys_sem_t sem) - - Deallocates a semaphore. - -- void sys_sem_signal(sys_sem_t sem) - - Signals a semaphore. - -- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) - - Blocks the thread while waiting for the semaphore to be - signaled. If the "timeout" argument is non-zero, the thread should - only be blocked for the specified time (measured in - milliseconds). If the "timeout" argument is zero, the thread should be - blocked until the semaphore is signalled. - - If the timeout argument is non-zero, the return value is the number of - milliseconds spent waiting for the semaphore to be signaled. If the - semaphore wasn't signaled within the specified time, the return value is - SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore - (i.e., it was already signaled), the function may return zero. - - Notice that lwIP implements a function with a similar name, - sys_sem_wait(), that uses the sys_arch_sem_wait() function. - -- sys_mbox_t sys_mbox_new(int size) - - Creates an empty mailbox for maximum "size" elements. Elements stored - in mailboxes are pointers. You have to define macros "_MBOX_SIZE" - in your lwipopts.h, or ignore this parameter in your implementation - and use a default size. - -- void sys_mbox_free(sys_mbox_t mbox) - - Deallocates a mailbox. If there are messages still present in the - mailbox when the mailbox is deallocated, it is an indication of a - programming error in lwIP and the developer should be notified. - -- void sys_mbox_post(sys_mbox_t mbox, void *msg) - - Posts the "msg" to the mailbox. This function have to block until - the "msg" is really posted. - -- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg) - - Try to post the "msg" to the mailbox. Returns ERR_MEM if this one - is full, else, ERR_OK if the "msg" is posted. - -- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) - - Blocks the thread until a message arrives in the mailbox, but does - not block the thread longer than "timeout" milliseconds (similar to - the sys_arch_sem_wait() function). If "timeout" is 0, the thread should - be blocked until a message arrives. The "msg" argument is a result - parameter that is set by the function (i.e., by doing "*msg = - ptr"). The "msg" parameter maybe NULL to indicate that the message - should be dropped. - - The return values are the same as for the sys_arch_sem_wait() function: - Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a - timeout. - - Note that a function with a similar name, sys_mbox_fetch(), is - implemented by lwIP. - -- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) - - This is similar to sys_arch_mbox_fetch, however if a message is not - present in the mailbox, it immediately returns with the code - SYS_MBOX_EMPTY. On success 0 is returned. - - To allow for efficient implementations, this can be defined as a - function-like macro in sys_arch.h instead of a normal function. For - example, a naive implementation could be: - #define sys_arch_mbox_tryfetch(mbox,msg) \ - sys_arch_mbox_fetch(mbox,msg,1) - although this would introduce unnecessary delays. - -- struct sys_timeouts *sys_arch_timeouts(void) - - Returns a pointer to the per-thread sys_timeouts structure. In lwIP, - each thread has a list of timeouts which is repressented as a linked - list of sys_timeout structures. The sys_timeouts structure holds a - pointer to a linked list of timeouts. This function is called by - the lwIP timeout scheduler and must not return a NULL value. - - In a single thread sys_arch implementation, this function will - simply return a pointer to a global sys_timeouts variable stored in - the sys_arch module. - -If threads are supported by the underlying operating system and if -such functionality is needed in lwIP, the following function will have -to be implemented as well: - -- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio) - - Starts a new thread named "name" with priority "prio" that will begin its - execution in the function "thread()". The "arg" argument will be passed as an - argument to the thread() function. The stack size to used for this thread is - the "stacksize" parameter. The id of the new thread is returned. Both the id - and the priority are system dependent. - -- sys_prot_t sys_arch_protect(void) - - This optional function does a "fast" critical region protection and returns - the previous protection level. This function is only called during very short - critical regions. An embedded system which supports ISR-based drivers might - want to implement this function by disabling interrupts. Task-based systems - might want to implement this by using a mutex or disabling tasking. This - function should support recursive calls from the same task or interrupt. In - other words, sys_arch_protect() could be called while already protected. In - that case the return value indicates that it is already protected. - - sys_arch_protect() is only required if your port is supporting an operating - system. - -- void sys_arch_unprotect(sys_prot_t pval) - - This optional function does a "fast" set of critical region protection to the - value specified by pval. See the documentation for sys_arch_protect() for - more information. This function is only required if your port is supporting - an operating system. - -Note: - -Be carefull with using mem_malloc() in sys_arch. When malloc() refers to -mem_malloc() you can run into a circular function call problem. In mem.c -mem_init() tries to allcate a semaphore using mem_malloc, which of course -can't be performed when sys_arch uses mem_malloc. - -------------------------------------------------------------------------------- -Additional files required for the "OS support" emulation layer: -------------------------------------------------------------------------------- - -cc.h - Architecture environment, some compiler specific, some - environment specific (probably should move env stuff - to sys_arch.h.) - - Typedefs for the types used by lwip - - u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t - - Compiler hints for packing lwip's structures - - PACK_STRUCT_FIELD(x) - PACK_STRUCT_STRUCT - PACK_STRUCT_BEGIN - PACK_STRUCT_END - - Platform specific diagnostic output - - LWIP_PLATFORM_DIAG(x) - non-fatal, print a message. - LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution. - Portability defines for printf formatters: - U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F - - "lightweight" synchronization mechanisms - - SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable. - SYS_ARCH_PROTECT(x) - enter protection mode. - SYS_ARCH_UNPROTECT(x) - leave protection mode. - - If the compiler does not provide memset() this file must include a - definition of it, or include a file which defines it. - - This file must either include a system-local which defines - the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO - to make lwip/arch.h define the codes which are used throughout. - - -perf.h - Architecture specific performance measurement. - Measurement calls made throughout lwip, these can be defined to nothing. - PERF_START - start measuring something. - PERF_STOP(x) - stop measuring something, and record the result. - -sys_arch.h - Tied to sys_arch.c - - Arch dependent types for the following objects: - sys_sem_t, sys_mbox_t, sys_thread_t, - And, optionally: - sys_prot_t - - Defines to set vars of sys_mbox_t and sys_sem_t to NULL. - SYS_MBOX_NULL NULL - SYS_SEM_NULL NULL diff --git a/components/net/lwip-1.3.2/src/api/api_lib.c b/components/net/lwip-1.3.2/src/api/api_lib.c deleted file mode 100644 index 195a9a525e..0000000000 --- a/components/net/lwip-1.3.2/src/api/api_lib.c +++ /dev/null @@ -1,558 +0,0 @@ -/** - * @file - * Sequential API External module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* This is the part of the API that is linked with - the application */ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/api.h" -#include "lwip/tcpip.h" -#include "lwip/memp.h" - -#include "lwip/ip.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include - -/** - * Create a new netconn (of a specific type) that has a callback function. - * The corresponding pcb is also created. - * - * @param t the type of 'connection' to create (@see enum netconn_type) - * @param proto the IP protocol for RAW IP pcbs - * @param callback a function to call on status changes (RX available, TX'ed) - * @return a newly allocated struct netconn or - * NULL on memory error - */ -struct netconn* -netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback) -{ - struct netconn *conn; - struct api_msg msg; - - conn = netconn_alloc(t, callback); - if (conn != NULL ) { - msg.function = do_newconn; - msg.msg.msg.n.proto = proto; - msg.msg.conn = conn; - TCPIP_APIMSG(&msg); - - if (conn->err != ERR_OK) { - LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL); - LWIP_ASSERT("conn has no op_completed", conn->op_completed != SYS_SEM_NULL); - LWIP_ASSERT("conn has no recvmbox", conn->recvmbox != SYS_MBOX_NULL); - LWIP_ASSERT("conn->acceptmbox shouldn't exist", conn->acceptmbox == SYS_MBOX_NULL); - sys_sem_free(conn->op_completed); - sys_mbox_free(conn->recvmbox); - memp_free(MEMP_NETCONN, conn); - return NULL; - } - } - return conn; -} - -/** - * Close a netconn 'connection' and free its resources. - * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate - * after this returns. - * - * @param conn the netconn to delete - * @return ERR_OK if the connection was deleted - */ -err_t -netconn_delete(struct netconn *conn) -{ - struct api_msg msg; - - /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ - if (conn == NULL) { - return ERR_OK; - } - - msg.function = do_delconn; - msg.msg.conn = conn; - tcpip_apimsg(&msg); - - conn->pcb.tcp = NULL; - netconn_free(conn); - - return ERR_OK; -} - -/** - * Get the local or remote IP address and port of a netconn. - * For RAW netconns, this returns the protocol instead of a port! - * - * @param conn the netconn to query - * @param addr a pointer to which to save the IP address - * @param port a pointer to which to save the port (or protocol for RAW) - * @param local 1 to get the local IP address, 0 to get the remote one - * @return ERR_CONN for invalid connections - * ERR_OK if the information was retrieved - */ -err_t -netconn_getaddr(struct netconn *conn, struct ip_addr *addr, u16_t *port, u8_t local) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;); - - msg.function = do_getaddr; - msg.msg.conn = conn; - msg.msg.msg.ad.ipaddr = addr; - msg.msg.msg.ad.port = port; - msg.msg.msg.ad.local = local; - TCPIP_APIMSG(&msg); - - return conn->err; -} - -/** - * Bind a netconn to a specific local IP address and port. - * Binding one netconn twice might not always be checked correctly! - * - * @param conn the netconn to bind - * @param addr the local IP address to bind the netconn to (use IP_ADDR_ANY - * to bind to all addresses) - * @param port the local port to bind the netconn to (not used for RAW) - * @return ERR_OK if bound, any other err_t on failure - */ -err_t -netconn_bind(struct netconn *conn, struct ip_addr *addr, u16_t port) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;); - - msg.function = do_bind; - msg.msg.conn = conn; - msg.msg.msg.bc.ipaddr = addr; - msg.msg.msg.bc.port = port; - TCPIP_APIMSG(&msg); - return conn->err; -} - -/** - * Connect a netconn to a specific remote IP address and port. - * - * @param conn the netconn to connect - * @param addr the remote IP address to connect to - * @param port the remote port to connect to (no used for RAW) - * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise - */ -err_t -netconn_connect(struct netconn *conn, struct ip_addr *addr, u16_t port) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;); - - msg.function = do_connect; - msg.msg.conn = conn; - msg.msg.msg.bc.ipaddr = addr; - msg.msg.msg.bc.port = port; - /* This is the only function which need to not block tcpip_thread */ - tcpip_apimsg(&msg); - return conn->err; -} - -/** - * Disconnect a netconn from its current peer (only valid for UDP netconns). - * - * @param conn the netconn to disconnect - * @return TODO: return value is not set here... - */ -err_t -netconn_disconnect(struct netconn *conn) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;); - - msg.function = do_disconnect; - msg.msg.conn = conn; - TCPIP_APIMSG(&msg); - return conn->err; -} - -/** - * Set a TCP netconn into listen mode - * - * @param conn the tcp netconn to set to listen mode - * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1 - * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns - * don't return any error (yet?)) - */ -err_t -netconn_listen_with_backlog(struct netconn *conn, u8_t backlog) -{ - struct api_msg msg; - - /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */ - LWIP_UNUSED_ARG(backlog); - - LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;); - - msg.function = do_listen; - msg.msg.conn = conn; -#if TCP_LISTEN_BACKLOG - msg.msg.msg.lb.backlog = backlog; -#endif /* TCP_LISTEN_BACKLOG */ - TCPIP_APIMSG(&msg); - return conn->err; -} - -/** - * Accept a new connection on a TCP listening netconn. - * - * @param conn the TCP listen netconn - * @return the newly accepted netconn or NULL on timeout - */ -struct netconn * -netconn_accept(struct netconn *conn) -{ - struct netconn *newconn; - - LWIP_ERROR("netconn_accept: invalid conn", (conn != NULL), return NULL;); - LWIP_ERROR("netconn_accept: invalid acceptmbox", (conn->acceptmbox != SYS_MBOX_NULL), return NULL;); - -#if LWIP_SO_RCVTIMEO - if (sys_arch_mbox_fetch(conn->acceptmbox, (void *)&newconn, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { - newconn = NULL; - } else -#else - sys_arch_mbox_fetch(conn->acceptmbox, (void *)&newconn, 0); -#endif /* LWIP_SO_RCVTIMEO*/ - { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); - -#if TCP_LISTEN_BACKLOG - if (newconn != NULL) { - /* Let the stack know that we have accepted the connection. */ - struct api_msg msg; - msg.function = do_recv; - msg.msg.conn = conn; - TCPIP_APIMSG(&msg); - } -#endif /* TCP_LISTEN_BACKLOG */ - } - - return newconn; -} - -/** - * Receive data (in form of a netbuf containing a packet buffer) from a netconn - * - * @param conn the netconn from which to receive data - * @return a new netbuf containing received data or NULL on memory error or timeout - */ -struct netbuf * -netconn_recv(struct netconn *conn) -{ - struct api_msg msg; - struct netbuf *buf = NULL; - struct pbuf *p; - u16_t len; - - LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return NULL;); - - if (conn->recvmbox == SYS_MBOX_NULL) { - /* @todo: should calling netconn_recv on a TCP listen conn be fatal (ERR_CONN)?? */ - /* TCP listen conns don't have a recvmbox! */ - conn->err = ERR_CONN; - return NULL; - } - - if (ERR_IS_FATAL(conn->err)) { - return NULL; - } - - if (conn->type == NETCONN_TCP) { -#if LWIP_TCP - if (conn->state == NETCONN_LISTEN) { - /* @todo: should calling netconn_recv on a TCP listen conn be fatal?? */ - conn->err = ERR_CONN; - return NULL; - } - - buf = memp_malloc(MEMP_NETBUF); - - if (buf == NULL) { - conn->err = ERR_MEM; - return NULL; - } - -#if LWIP_SO_RCVTIMEO - if (sys_arch_mbox_fetch(conn->recvmbox, (void *)&p, conn->recv_timeout)==SYS_ARCH_TIMEOUT) { - memp_free(MEMP_NETBUF, buf); - conn->err = ERR_TIMEOUT; - return NULL; - } -#else - sys_arch_mbox_fetch(conn->recvmbox, (void *)&p, 0); -#endif /* LWIP_SO_RCVTIMEO*/ - - if (p != NULL) { - len = p->tot_len; - SYS_ARCH_DEC(conn->recv_avail, len); - } else { - len = 0; - } - - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVMINUS, len); - - /* If we are closed, we indicate that we no longer wish to use the socket */ - if (p == NULL) { - memp_free(MEMP_NETBUF, buf); - /* Avoid to lose any previous error code */ - if (conn->err == ERR_OK) { - conn->err = ERR_CLSD; - } - return NULL; - } - - buf->p = p; - buf->ptr = p; - buf->port = 0; - buf->addr = NULL; - - /* Let the stack know that we have taken the data. */ - msg.function = do_recv; - msg.msg.conn = conn; - if (buf != NULL) { - msg.msg.msg.r.len = buf->p->tot_len; - } else { - msg.msg.msg.r.len = 1; - } - TCPIP_APIMSG(&msg); -#endif /* LWIP_TCP */ - } else { -#if (LWIP_UDP || LWIP_RAW) -#if LWIP_SO_RCVTIMEO - if (sys_arch_mbox_fetch(conn->recvmbox, (void *)&buf, conn->recv_timeout)==SYS_ARCH_TIMEOUT) { - buf = NULL; - } -#else - sys_arch_mbox_fetch(conn->recvmbox, (void *)&buf, 0); -#endif /* LWIP_SO_RCVTIMEO*/ - if (buf!=NULL) { - SYS_ARCH_DEC(conn->recv_avail, buf->p->tot_len); - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len); - } -#endif /* (LWIP_UDP || LWIP_RAW) */ - } - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err)); - - return buf; -} - -/** - * Send data (in form of a netbuf) to a specific remote IP address and port. - * Only to be used for UDP and RAW netconns (not TCP). - * - * @param conn the netconn over which to send data - * @param buf a netbuf containing the data to send - * @param addr the remote IP address to which to send the data - * @param port the remote port to which to send the data - * @return ERR_OK if data was sent, any other err_t on error - */ -err_t -netconn_sendto(struct netconn *conn, struct netbuf *buf, struct ip_addr *addr, u16_t port) -{ - if (buf != NULL) { - buf->addr = addr; - buf->port = port; - return netconn_send(conn, buf); - } - return ERR_VAL; -} - -/** - * Send data over a UDP or RAW netconn (that is already connected). - * - * @param conn the UDP or RAW netconn over which to send data - * @param buf a netbuf containing the data to send - * @return ERR_OK if data was sent, any other err_t on error - */ -err_t -netconn_send(struct netconn *conn, struct netbuf *buf) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_send: invalid conn", (conn != NULL), return ERR_ARG;); - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len)); - msg.function = do_send; - msg.msg.conn = conn; - msg.msg.msg.b = buf; - TCPIP_APIMSG(&msg); - return conn->err; -} - -/** - * Send data over a TCP netconn. - * - * @param conn the TCP netconn over which to send data - * @param dataptr pointer to the application buffer that contains the data to send - * @param size size of the application data to send - * @param apiflags combination of following flags : - * - NETCONN_COPY (0x01) data will be copied into memory belonging to the stack - * - NETCONN_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent - * @return ERR_OK if data was sent, any other err_t on error - */ -err_t -netconn_write(struct netconn *conn, const void *dataptr, size_t size, u8_t apiflags) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_write: invalid conn", (conn != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_write: invalid conn->type", (conn->type == NETCONN_TCP), return ERR_VAL;); - - msg.function = do_write; - msg.msg.conn = conn; - msg.msg.msg.w.dataptr = dataptr; - msg.msg.msg.w.apiflags = apiflags; - msg.msg.msg.w.len = size; - /* For locking the core: this _can_ be delayed on low memory/low send buffer, - but if it is, this is done inside api_msg.c:do_write(), so we can use the - non-blocking version here. */ - TCPIP_APIMSG(&msg); - return conn->err; -} - -/** - * Close a TCP netconn (doesn't delete it). - * - * @param conn the TCP netconn to close - * @return ERR_OK if the netconn was closed, any other err_t on error - */ -err_t -netconn_close(struct netconn *conn) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_close: invalid conn", (conn != NULL), return ERR_ARG;); - - msg.function = do_close; - msg.msg.conn = conn; - tcpip_apimsg(&msg); - return conn->err; -} - -#if LWIP_IGMP -/** - * Join multicast groups for UDP netconns. - * - * @param conn the UDP netconn for which to change multicast addresses - * @param multiaddr IP address of the multicast group to join or leave - * @param interface the IP address of the network interface on which to send - * the igmp message - * @param join_or_leave flag whether to send a join- or leave-message - * @return ERR_OK if the action was taken, any err_t on error - */ -err_t -netconn_join_leave_group(struct netconn *conn, - struct ip_addr *multiaddr, - struct ip_addr *interface, - enum netconn_igmp join_or_leave) -{ - struct api_msg msg; - - LWIP_ERROR("netconn_join_leave_group: invalid conn", (conn != NULL), return ERR_ARG;); - - msg.function = do_join_leave_group; - msg.msg.conn = conn; - msg.msg.msg.jl.multiaddr = multiaddr; - msg.msg.msg.jl.interface = interface; - msg.msg.msg.jl.join_or_leave = join_or_leave; - TCPIP_APIMSG(&msg); - return conn->err; -} -#endif /* LWIP_IGMP */ - -#if LWIP_DNS -/** - * Execute a DNS query, only one IP address is returned - * - * @param name a string representation of the DNS host name to query - * @param addr a preallocated struct ip_addr where to store the resolved IP address - * @return ERR_OK: resolving succeeded - * ERR_MEM: memory error, try again later - * ERR_ARG: dns client not initialized or invalid hostname - * ERR_VAL: dns server response was invalid - */ -err_t -netconn_gethostbyname(const char *name, struct ip_addr *addr) -{ - struct dns_api_msg msg; - err_t err; - sys_sem_t sem; - - LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;); - LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;); - - sem = sys_sem_new(0); - if (sem == SYS_SEM_NULL) { - return ERR_MEM; - } - - msg.name = name; - msg.addr = addr; - msg.err = &err; - msg.sem = sem; - - tcpip_callback(do_gethostbyname, &msg); - sys_sem_wait(sem); - sys_sem_free(sem); - - return err; -} -#endif /* LWIP_DNS*/ - -#endif /* LWIP_NETCONN */ diff --git a/components/net/lwip-1.3.2/src/api/api_msg.c b/components/net/lwip-1.3.2/src/api/api_msg.c deleted file mode 100644 index c2ff5ee5e8..0000000000 --- a/components/net/lwip-1.3.2/src/api/api_msg.c +++ /dev/null @@ -1,1248 +0,0 @@ -/** - * @file - * Sequential API Internal module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/api_msg.h" - -#include "lwip/ip.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" -#include "lwip/raw.h" - -#include "lwip/memp.h" -#include "lwip/tcpip.h" -#include "lwip/igmp.h" -#include "lwip/dns.h" - -#include - -/* forward declarations */ -#if LWIP_TCP -static err_t do_writemore(struct netconn *conn); -static void do_close_internal(struct netconn *conn); -#endif - -#if LWIP_RAW -/** - * Receive callback function for RAW netconns. - * Doesn't 'eat' the packet, only references it and sends it to - * conn->recvmbox - * - * @see raw.h (struct raw_pcb.recv) for parameters and return value - */ -static u8_t -recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, - struct ip_addr *addr) -{ - struct pbuf *q; - struct netbuf *buf; - struct netconn *conn; -#if LWIP_SO_RCVBUF - int recv_avail; -#endif /* LWIP_SO_RCVBUF */ - - LWIP_UNUSED_ARG(addr); - conn = arg; - -#if LWIP_SO_RCVBUF - SYS_ARCH_GET(conn->recv_avail, recv_avail); - if ((conn != NULL) && (conn->recvmbox != SYS_MBOX_NULL) && - ((recv_avail + (int)(p->tot_len)) <= conn->recv_bufsize)) { -#else /* LWIP_SO_RCVBUF */ - if ((conn != NULL) && (conn->recvmbox != SYS_MBOX_NULL)) { -#endif /* LWIP_SO_RCVBUF */ - /* copy the whole packet into new pbufs */ - q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if(q != NULL) { - if (pbuf_copy(q, p) != ERR_OK) { - pbuf_free(q); - q = NULL; - } - } - - if(q != NULL) { - buf = memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - pbuf_free(q); - return 0; - } - - buf->p = q; - buf->ptr = q; - buf->addr = &(((struct ip_hdr*)(q->payload))->src); - buf->port = pcb->protocol; - - if (sys_mbox_trypost(conn->recvmbox, buf) != ERR_OK) { - netbuf_delete(buf); - return 0; - } else { - SYS_ARCH_INC(conn->recv_avail, q->tot_len); - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, q->tot_len); - } - } - } - - return 0; /* do not eat the packet */ -} -#endif /* LWIP_RAW*/ - -#if LWIP_UDP -/** - * Receive callback function for UDP netconns. - * Posts the packet to conn->recvmbox or deletes it on memory error. - * - * @see udp.h (struct udp_pcb.recv) for parameters - */ -static void -recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *addr, u16_t port) -{ - struct netbuf *buf; - struct netconn *conn; -#if LWIP_SO_RCVBUF - int recv_avail; -#endif /* LWIP_SO_RCVBUF */ - - LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ - LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); - LWIP_ASSERT("recv_udp must have an argument", arg != NULL); - conn = arg; - LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); - -#if LWIP_SO_RCVBUF - SYS_ARCH_GET(conn->recv_avail, recv_avail); - if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL) || - ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { -#else /* LWIP_SO_RCVBUF */ - if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL)) { -#endif /* LWIP_SO_RCVBUF */ - pbuf_free(p); - return; - } - - buf = memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - pbuf_free(p); - return; - } else { - buf->p = p; - buf->ptr = p; - buf->addr = addr; - buf->port = port; -#if LWIP_NETBUF_RECVINFO - { - const struct ip_hdr* iphdr = ip_current_header(); - /* get the UDP header - always in the first pbuf, ensured by udp_input */ - const struct udp_hdr* udphdr = (void*)(((char*)iphdr) + IPH_LEN(iphdr)); - buf->toaddr = (struct ip_addr*)&iphdr->dest; - buf->toport = udphdr->dest; - } -#endif /* LWIP_NETBUF_RECVINFO */ - } - - if (sys_mbox_trypost(conn->recvmbox, buf) != ERR_OK) { - netbuf_delete(buf); - return; - } else { - SYS_ARCH_INC(conn->recv_avail, p->tot_len); - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, p->tot_len); - } -} -#endif /* LWIP_UDP */ - -#if LWIP_TCP -/** - * Receive callback function for TCP netconns. - * Posts the packet to conn->recvmbox, but doesn't delete it on errors. - * - * @see tcp.h (struct tcp_pcb.recv) for parameters and return value - */ -static err_t -recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - struct netconn *conn; - u16_t len; - - LWIP_UNUSED_ARG(pcb); - LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); - LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); - conn = arg; - LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); - - if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL)) { - return ERR_VAL; - } - - conn->err = err; - if (p != NULL) { - len = p->tot_len; - SYS_ARCH_INC(conn->recv_avail, len); - } else { - len = 0; - } - - if (sys_mbox_trypost(conn->recvmbox, p) != ERR_OK) { - return ERR_MEM; - } else { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); - } - - return ERR_OK; -} - -/** - * Poll callback function for TCP netconns. - * Wakes up an application thread that waits for a connection to close - * or data to be sent. The application thread then takes the - * appropriate action to go on. - * - * Signals the conn->sem. - * netconn_close waits for conn->sem if closing failed. - * - * @see tcp.h (struct tcp_pcb.poll) for parameters and return value - */ -static err_t -poll_tcp(void *arg, struct tcp_pcb *pcb) -{ - struct netconn *conn = arg; - - LWIP_UNUSED_ARG(pcb); - LWIP_ASSERT("conn != NULL", (conn != NULL)); - - if (conn->state == NETCONN_WRITE) { - do_writemore(conn); - } else if (conn->state == NETCONN_CLOSE) { - do_close_internal(conn); - } - - return ERR_OK; -} - -/** - * Sent callback function for TCP netconns. - * Signals the conn->sem and calls API_EVENT. - * netconn_write waits for conn->sem if send buffer is low. - * - * @see tcp.h (struct tcp_pcb.sent) for parameters and return value - */ -static err_t -sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) -{ - struct netconn *conn = arg; - - LWIP_UNUSED_ARG(pcb); - LWIP_ASSERT("conn != NULL", (conn != NULL)); - - if (conn->state == NETCONN_WRITE) { - LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); - do_writemore(conn); - } else if (conn->state == NETCONN_CLOSE) { - do_close_internal(conn); - } - - if (conn) { - if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)) { - API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); - } - } - - return ERR_OK; -} - -/** - * Error callback function for TCP netconns. - * Signals conn->sem, posts to all conn mboxes and calls API_EVENT. - * The application thread has then to decide what to do. - * - * @see tcp.h (struct tcp_pcb.err) for parameters - */ -static void -err_tcp(void *arg, err_t err) -{ - struct netconn *conn; - - conn = arg; - LWIP_ASSERT("conn != NULL", (conn != NULL)); - - conn->pcb.tcp = NULL; - - conn->err = err; - if (conn->recvmbox != SYS_MBOX_NULL) { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - sys_mbox_post(conn->recvmbox, NULL); - } - if (conn->op_completed != SYS_SEM_NULL && conn->state == NETCONN_CONNECT) { - conn->state = NETCONN_NONE; - sys_sem_signal(conn->op_completed); - } - if (conn->acceptmbox != SYS_MBOX_NULL) { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - sys_mbox_post(conn->acceptmbox, NULL); - } - if ((conn->state == NETCONN_WRITE) || (conn->state == NETCONN_CLOSE)) { - /* calling do_writemore/do_close_internal is not necessary - since the pcb has already been deleted! */ - conn->state = NETCONN_NONE; - /* wake up the waiting task */ - sys_sem_signal(conn->op_completed); - } -} - -/** - * Setup a tcp_pcb with the correct callback function pointers - * and their arguments. - * - * @param conn the TCP netconn to setup - */ -static void -setup_tcp(struct netconn *conn) -{ - struct tcp_pcb *pcb; - - pcb = conn->pcb.tcp; - tcp_arg(pcb, conn); - tcp_recv(pcb, recv_tcp); - tcp_sent(pcb, sent_tcp); - tcp_poll(pcb, poll_tcp, 4); - tcp_err(pcb, err_tcp); -} - -/** - * Accept callback function for TCP netconns. - * Allocates a new netconn and posts that to conn->acceptmbox. - * - * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value - */ -static err_t -accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) -{ - struct netconn *newconn; - struct netconn *conn; - -#if API_MSG_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(newpcb->state); -#endif /* TCP_DEBUG */ -#endif /* API_MSG_DEBUG */ - conn = (struct netconn *)arg; - - /* check whether acceptmbox is valid */ - if (conn->acceptmbox == SYS_MBOX_NULL) - { - LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n")); - return ERR_VAL; - } - - /* We have to set the callback here even though - * the new socket is unknown. conn->socket is marked as -1. */ - newconn = netconn_alloc(conn->type, conn->callback); - if (newconn == NULL) { - return ERR_MEM; - } - newconn->pcb.tcp = newpcb; - setup_tcp(newconn); - newconn->err = err; - - if (sys_mbox_trypost(conn->acceptmbox, newconn) != ERR_OK) { - /* When returning != ERR_OK, the connection is aborted in tcp_process(), - so do nothing here! */ - newconn->pcb.tcp = NULL; - netconn_free(newconn); - return ERR_MEM; - } else { - /* Register event with callback */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - } - - return ERR_OK; -} -#endif /* LWIP_TCP */ - -/** - * Create a new pcb of a specific type. - * Called from do_newconn(). - * - * @param msg the api_msg_msg describing the connection type - * @return msg->conn->err, but the return value is currently ignored - */ -static err_t -pcb_new(struct api_msg_msg *msg) -{ - msg->conn->err = ERR_OK; - - LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); - - /* Allocate a PCB for this connection */ - switch(NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.n.proto); - if(msg->conn->pcb.raw == NULL) { - msg->conn->err = ERR_MEM; - break; - } - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } -#if LWIP_UDPLITE - if (msg->conn->type==NETCONN_UDPLITE) { - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - } -#endif /* LWIP_UDPLITE */ - if (msg->conn->type==NETCONN_UDPNOCHKSUM) { - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - } - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - if(msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - setup_tcp(msg->conn); - break; -#endif /* LWIP_TCP */ - default: - /* Unsupported netconn type, e.g. protocol disabled */ - msg->conn->err = ERR_VAL; - break; - } - - return msg->conn->err; -} - -/** - * Create a new pcb of a specific type inside a netconn. - * Called from netconn_new_with_proto_and_callback. - * - * @param msg the api_msg_msg describing the connection type - */ -void -do_newconn(struct api_msg_msg *msg) -{ - if(msg->conn->pcb.tcp == NULL) { - pcb_new(msg); - } - /* Else? This "new" connection already has a PCB allocated. */ - /* Is this an error condition? Should it be deleted? */ - /* We currently just are happy and return. */ - - TCPIP_APIMSG_ACK(msg); -} - -/** - * Create a new netconn (of a specific type) that has a callback function. - * The corresponding pcb is NOT created! - * - * @param t the type of 'connection' to create (@see enum netconn_type) - * @param proto the IP protocol for RAW IP pcbs - * @param callback a function to call on status changes (RX available, TX'ed) - * @return a newly allocated struct netconn or - * NULL on memory error - */ -struct netconn* -netconn_alloc(enum netconn_type t, netconn_callback callback) -{ - struct netconn *conn; - int size; - - conn = memp_malloc(MEMP_NETCONN); - if (conn == NULL) { - return NULL; - } - - conn->err = ERR_OK; - conn->type = t; - conn->pcb.tcp = NULL; - -#if (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_UDP_RECVMBOX_SIZE) && \ - (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_TCP_RECVMBOX_SIZE) - size = DEFAULT_RAW_RECVMBOX_SIZE; -#else - size = 0; /* skip warning */ - switch(NETCONNTYPE_GROUP(t)) { -#if LWIP_RAW - case NETCONN_RAW: - size = DEFAULT_RAW_RECVMBOX_SIZE; - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - size = DEFAULT_UDP_RECVMBOX_SIZE; - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - size = DEFAULT_TCP_RECVMBOX_SIZE; - break; -#endif /* LWIP_TCP */ - default: - LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); - break; - } -#endif - - if ((conn->op_completed = sys_sem_new(0)) == SYS_SEM_NULL) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - if ((conn->recvmbox = sys_mbox_new(size)) == SYS_MBOX_NULL) { - sys_sem_free(conn->op_completed); - memp_free(MEMP_NETCONN, conn); - return NULL; - } - - conn->acceptmbox = SYS_MBOX_NULL; - conn->state = NETCONN_NONE; - /* initialize socket to -1 since 0 is a valid socket */ - conn->socket = -1; - conn->callback = callback; - conn->recv_avail = 0; -#if LWIP_TCP - conn->write_msg = NULL; - conn->write_offset = 0; -#if LWIP_TCPIP_CORE_LOCKING - conn->write_delayed = 0; -#endif /* LWIP_TCPIP_CORE_LOCKING */ -#endif /* LWIP_TCP */ -#if LWIP_SO_RCVTIMEO - conn->recv_timeout = 0; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - conn->recv_bufsize = RECV_BUFSIZE_DEFAULT; -#endif /* LWIP_SO_RCVBUF */ - return conn; -} - -/** - * Delete a netconn and all its resources. - * The pcb is NOT freed (since we might not be in the right thread context do this). - * - * @param conn the netconn to free - */ -void -netconn_free(struct netconn *conn) -{ - void *mem; - LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); - - /* Drain the recvmbox. */ - if (conn->recvmbox != SYS_MBOX_NULL) { - while (sys_mbox_tryfetch(conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { - if (conn->type == NETCONN_TCP) { - if(mem != NULL) { - pbuf_free((struct pbuf *)mem); - } - } else { - netbuf_delete((struct netbuf *)mem); - } - } - sys_mbox_free(conn->recvmbox); - conn->recvmbox = SYS_MBOX_NULL; - } - - /* Drain the acceptmbox. */ - if (conn->acceptmbox != SYS_MBOX_NULL) { - while (sys_mbox_tryfetch(conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { - netconn_delete((struct netconn *)mem); - } - sys_mbox_free(conn->acceptmbox); - conn->acceptmbox = SYS_MBOX_NULL; - } - - sys_sem_free(conn->op_completed); - conn->op_completed = SYS_SEM_NULL; - - memp_free(MEMP_NETCONN, conn); -} - -#if LWIP_TCP -/** - * Internal helper function to close a TCP netconn: since this sometimes - * doesn't work at the first attempt, this function is called from multiple - * places. - * - * @param conn the TCP netconn to close - */ -static void -do_close_internal(struct netconn *conn) -{ - err_t err; - - LWIP_ASSERT("invalid conn", (conn != NULL)); - LWIP_ASSERT("this is for tcp netconns only", (conn->type == NETCONN_TCP)); - LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); - LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); - - /* Set back some callback pointers */ - tcp_arg(conn->pcb.tcp, NULL); - if (conn->pcb.tcp->state == LISTEN) { - tcp_accept(conn->pcb.tcp, NULL); - } else { - tcp_recv(conn->pcb.tcp, NULL); - tcp_accept(conn->pcb.tcp, NULL); - /* some callbacks have to be reset if tcp_close is not successful */ - tcp_sent(conn->pcb.tcp, NULL); - tcp_poll(conn->pcb.tcp, NULL, 4); - tcp_err(conn->pcb.tcp, NULL); - } - /* Try to close the connection */ - err = tcp_close(conn->pcb.tcp); - if (err == ERR_OK) { - /* Closing succeeded */ - conn->state = NETCONN_NONE; - /* Set back some callback pointers as conn is going away */ - conn->pcb.tcp = NULL; - conn->err = ERR_OK; - /* Trigger select() in socket layer. This send should something else so the - errorfd is set, not the read and write fd! */ - API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); - API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); - /* wake up the application task */ - sys_sem_signal(conn->op_completed); - } else { - /* Closing failed, restore some of the callbacks */ - /* Closing of listen pcb will never fail! */ - LWIP_ASSERT("Closing a listen pcb may not fail!", (conn->pcb.tcp->state != LISTEN)); - tcp_sent(conn->pcb.tcp, sent_tcp); - tcp_poll(conn->pcb.tcp, poll_tcp, 4); - tcp_err(conn->pcb.tcp, err_tcp); - tcp_arg(conn->pcb.tcp, conn); - } - /* If closing didn't succeed, we get called again either - from poll_tcp or from sent_tcp */ -} -#endif /* LWIP_TCP */ - -/** - * Delete the pcb inside a netconn. - * Called from netconn_delete. - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_delconn(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - raw_remove(msg->conn->pcb.raw); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->conn->pcb.udp->recv_arg = NULL; - udp_remove(msg->conn->pcb.udp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->state = NETCONN_CLOSE; - do_close_internal(msg->conn); - /* API_EVENT is called inside do_close_internal, before releasing - the application thread, so we can return at this point! */ - return; -#endif /* LWIP_TCP */ - default: - break; - } - } - /* tcp netconns don't come here! */ - - /* Trigger select() in socket layer. This send should something else so the - errorfd is set, not the read and write fd! */ - API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); - API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); - - if (msg->conn->op_completed != SYS_SEM_NULL) { - sys_sem_signal(msg->conn->op_completed); - } -} - -/** - * Bind a pcb contained in a netconn - * Called from netconn_bind. - * - * @param msg the api_msg_msg pointing to the connection and containing - * the IP address and port to bind to - */ -void -do_bind(struct api_msg_msg *msg) -{ - if (!ERR_IS_FATAL(msg->conn->err)) { - if (msg->conn->pcb.tcp != NULL) { - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->err = raw_bind(msg->conn->pcb.raw, msg->msg.bc.ipaddr); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->err = tcp_bind(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port); - break; -#endif /* LWIP_TCP */ - default: - break; - } - } else { - /* msg->conn->pcb is NULL */ - msg->conn->err = ERR_VAL; - } - } - TCPIP_APIMSG_ACK(msg); -} - -#if LWIP_TCP -/** - * TCP callback function if a connection (opened by tcp_connect/do_connect) has - * been established (or reset by the remote host). - * - * @see tcp.h (struct tcp_pcb.connected) for parameters and return values - */ -static err_t -do_connected(void *arg, struct tcp_pcb *pcb, err_t err) -{ - struct netconn *conn; - - LWIP_UNUSED_ARG(pcb); - - conn = arg; - - if (conn == NULL) { - return ERR_VAL; - } - - conn->err = err; - if ((conn->type == NETCONN_TCP) && (err == ERR_OK)) { - setup_tcp(conn); - } - conn->state = NETCONN_NONE; - sys_sem_signal(conn->op_completed); - return ERR_OK; -} -#endif /* LWIP_TCP */ - -/** - * Connect a pcb contained inside a netconn - * Called from netconn_connect. - * - * @param msg the api_msg_msg pointing to the connection and containing - * the IP address and port to connect to - */ -void -do_connect(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp == NULL) { - sys_sem_signal(msg->conn->op_completed); - return; - } - - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->err = raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr); - sys_sem_signal(msg->conn->op_completed); - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - msg->conn->err = udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); - sys_sem_signal(msg->conn->op_completed); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->state = NETCONN_CONNECT; - setup_tcp(msg->conn); - msg->conn->err = tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port, - do_connected); - /* sys_sem_signal() is called from do_connected (or err_tcp()), - * when the connection is established! */ - break; -#endif /* LWIP_TCP */ - default: - LWIP_ERROR("Invalid netconn type", 0, do{ msg->conn->err = ERR_VAL; - sys_sem_signal(msg->conn->op_completed); }while(0)); - break; - } -} - -/** - * Connect a pcb contained inside a netconn - * Only used for UDP netconns. - * Called from netconn_disconnect. - * - * @param msg the api_msg_msg pointing to the connection to disconnect - */ -void -do_disconnect(struct api_msg_msg *msg) -{ -#if LWIP_UDP - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { - udp_disconnect(msg->conn->pcb.udp); - } -#endif /* LWIP_UDP */ - TCPIP_APIMSG_ACK(msg); -} - -/** - * Set a TCP pcb contained in a netconn into listen mode - * Called from netconn_listen. - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_listen(struct api_msg_msg *msg) -{ -#if LWIP_TCP - if (!ERR_IS_FATAL(msg->conn->err)) { - if (msg->conn->pcb.tcp != NULL) { - if (msg->conn->type == NETCONN_TCP) { - if (msg->conn->pcb.tcp->state == CLOSED) { -#if TCP_LISTEN_BACKLOG - struct tcp_pcb* lpcb = tcp_listen_with_backlog(msg->conn->pcb.tcp, msg->msg.lb.backlog); -#else /* TCP_LISTEN_BACKLOG */ - struct tcp_pcb* lpcb = tcp_listen(msg->conn->pcb.tcp); -#endif /* TCP_LISTEN_BACKLOG */ - if (lpcb == NULL) { - msg->conn->err = ERR_MEM; - } else { - /* delete the recvmbox and allocate the acceptmbox */ - if (msg->conn->recvmbox != SYS_MBOX_NULL) { - /** @todo: should we drain the recvmbox here? */ - sys_mbox_free(msg->conn->recvmbox); - msg->conn->recvmbox = SYS_MBOX_NULL; - } - if (msg->conn->acceptmbox == SYS_MBOX_NULL) { - if ((msg->conn->acceptmbox = sys_mbox_new(DEFAULT_ACCEPTMBOX_SIZE)) == SYS_MBOX_NULL) { - msg->conn->err = ERR_MEM; - } - } - if (msg->conn->err == ERR_OK) { - msg->conn->state = NETCONN_LISTEN; - msg->conn->pcb.tcp = lpcb; - tcp_arg(msg->conn->pcb.tcp, msg->conn); - tcp_accept(msg->conn->pcb.tcp, accept_function); - } - } - } else { - msg->conn->err = ERR_CONN; - } - } - } - } -#endif /* LWIP_TCP */ - TCPIP_APIMSG_ACK(msg); -} - -/** - * Send some data on a RAW or UDP pcb contained in a netconn - * Called from netconn_send - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_send(struct api_msg_msg *msg) -{ - if (!ERR_IS_FATAL(msg->conn->err)) { - if (msg->conn->pcb.tcp != NULL) { - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - if (msg->msg.b->addr == NULL) { - msg->conn->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p); - } else { - msg->conn->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, msg->msg.b->addr); - } - break; -#endif -#if LWIP_UDP - case NETCONN_UDP: - if (msg->msg.b->addr == NULL) { - msg->conn->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p); - } else { - msg->conn->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, msg->msg.b->addr, msg->msg.b->port); - } - break; -#endif /* LWIP_UDP */ - default: - break; - } - } - } - TCPIP_APIMSG_ACK(msg); -} - -/** - * Indicate data has been received from a TCP pcb contained in a netconn - * Called from netconn_recv - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_recv(struct api_msg_msg *msg) -{ -#if LWIP_TCP - if (!ERR_IS_FATAL(msg->conn->err)) { - if (msg->conn->pcb.tcp != NULL) { - if (msg->conn->type == NETCONN_TCP) { -#if TCP_LISTEN_BACKLOG - if (msg->conn->pcb.tcp->state == LISTEN) { - tcp_accepted(msg->conn->pcb.tcp); - } else -#endif /* TCP_LISTEN_BACKLOG */ - { - tcp_recved(msg->conn->pcb.tcp, msg->msg.r.len); - } - } - } - } -#endif /* LWIP_TCP */ - TCPIP_APIMSG_ACK(msg); -} - -#if LWIP_TCP -/** - * See if more data needs to be written from a previous call to netconn_write. - * Called initially from do_write. If the first call can't send all data - * (because of low memory or empty send-buffer), this function is called again - * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the - * blocking application thread (waiting in netconn_write) is released. - * - * @param conn netconn (that is currently in state NETCONN_WRITE) to process - * @return ERR_OK - * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished - */ -static err_t -do_writemore(struct netconn *conn) -{ - err_t err; - void *dataptr; - u16_t len, available; - u8_t write_finished = 0; - size_t diff; - - LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); - - dataptr = (u8_t*)conn->write_msg->msg.w.dataptr + conn->write_offset; - diff = conn->write_msg->msg.w.len - conn->write_offset; - if (diff > 0xffffUL) { /* max_u16_t */ - len = 0xffff; -#if LWIP_TCPIP_CORE_LOCKING - conn->write_delayed = 1; -#endif - } else { - len = (u16_t)diff; - } - available = tcp_sndbuf(conn->pcb.tcp); - if (available < len) { - /* don't try to write more than sendbuf */ - len = available; -#if LWIP_TCPIP_CORE_LOCKING - conn->write_delayed = 1; -#endif - } - - err = tcp_write(conn->pcb.tcp, dataptr, len, conn->write_msg->msg.w.apiflags); - LWIP_ASSERT("do_writemore: invalid length!", ((conn->write_offset + len) <= conn->write_msg->msg.w.len)); - if (err == ERR_OK) { - conn->write_offset += len; - if (conn->write_offset == conn->write_msg->msg.w.len) { - /* everything was written */ - write_finished = 1; - conn->write_msg = NULL; - conn->write_offset = 0; - /* API_EVENT might call tcp_tmr, so reset conn->state now */ - conn->state = NETCONN_NONE; - } - err = tcp_output_nagle(conn->pcb.tcp); - conn->err = err; - if ((err == ERR_OK) && (tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT)) { - API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); - } - } else if (err == ERR_MEM) { - /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called - we do NOT return to the application thread, since ERR_MEM is - only a temporary error! */ - - /* tcp_enqueue returned ERR_MEM, try tcp_output anyway */ - err = tcp_output(conn->pcb.tcp); - -#if LWIP_TCPIP_CORE_LOCKING - conn->write_delayed = 1; -#endif - } else { - /* On errors != ERR_MEM, we don't try writing any more but return - the error to the application thread. */ - conn->err = err; - write_finished = 1; - } - - if (write_finished) { - /* everything was written: set back connection state - and back to application task */ - conn->state = NETCONN_NONE; -#if LWIP_TCPIP_CORE_LOCKING - if (conn->write_delayed != 0) -#endif - { - sys_sem_signal(conn->op_completed); - } - } -#if LWIP_TCPIP_CORE_LOCKING - else - return ERR_MEM; -#endif - return ERR_OK; -} -#endif /* LWIP_TCP */ - -/** - * Send some data on a TCP pcb contained in a netconn - * Called from netconn_write - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_write(struct api_msg_msg *msg) -{ - if (!ERR_IS_FATAL(msg->conn->err)) { - if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) { -#if LWIP_TCP - msg->conn->state = NETCONN_WRITE; - /* set all the variables used by do_writemore */ - LWIP_ASSERT("already writing", msg->conn->write_msg == NULL && - msg->conn->write_offset == 0); - msg->conn->write_msg = msg; - msg->conn->write_offset = 0; -#if LWIP_TCPIP_CORE_LOCKING - msg->conn->write_delayed = 0; - if (do_writemore(msg->conn) != ERR_OK) { - LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); - UNLOCK_TCPIP_CORE(); - sys_arch_sem_wait(msg->conn->op_completed, 0); - LOCK_TCPIP_CORE(); - LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); - } -#else - do_writemore(msg->conn); -#endif - /* for both cases: if do_writemore was called, don't ACK the APIMSG! */ - return; -#endif /* LWIP_TCP */ -#if (LWIP_UDP || LWIP_RAW) - } else { - msg->conn->err = ERR_VAL; -#endif /* (LWIP_UDP || LWIP_RAW) */ - } - } - TCPIP_APIMSG_ACK(msg); -} - -/** - * Return a connection's local or remote address - * Called from netconn_getaddr - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_getaddr(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.ip != NULL) { - *(msg->msg.ad.ipaddr) = (msg->msg.ad.local?msg->conn->pcb.ip->local_ip:msg->conn->pcb.ip->remote_ip); - - switch (NETCONNTYPE_GROUP(msg->conn->type)) { -#if LWIP_RAW - case NETCONN_RAW: - if (msg->msg.ad.local) { - *(msg->msg.ad.port) = msg->conn->pcb.raw->protocol; - } else { - /* return an error as connecting is only a helper for upper layers */ - msg->conn->err = ERR_CONN; - } - break; -#endif /* LWIP_RAW */ -#if LWIP_UDP - case NETCONN_UDP: - if (msg->msg.ad.local) { - *(msg->msg.ad.port) = msg->conn->pcb.udp->local_port; - } else { - if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) { - msg->conn->err = ERR_CONN; - } else { - *(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port; - } - } - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - *(msg->msg.ad.port) = (msg->msg.ad.local?msg->conn->pcb.tcp->local_port:msg->conn->pcb.tcp->remote_port); - break; -#endif /* LWIP_TCP */ - } - } else { - msg->conn->err = ERR_CONN; - } - TCPIP_APIMSG_ACK(msg); -} - -/** - * Close a TCP pcb contained in a netconn - * Called from netconn_close - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_close(struct api_msg_msg *msg) -{ -#if LWIP_TCP - if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) { - msg->conn->state = NETCONN_CLOSE; - do_close_internal(msg->conn); - /* for tcp netconns, do_close_internal ACKs the message */ - } else -#endif /* LWIP_TCP */ - { - msg->conn->err = ERR_VAL; - sys_sem_signal(msg->conn->op_completed); - } -} - -#if LWIP_IGMP -/** - * Join multicast groups for UDP netconns. - * Called from netconn_join_leave_group - * - * @param msg the api_msg_msg pointing to the connection - */ -void -do_join_leave_group(struct api_msg_msg *msg) -{ - if (!ERR_IS_FATAL(msg->conn->err)) { - if (msg->conn->pcb.tcp != NULL) { - if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { -#if LWIP_UDP - if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { - msg->conn->err = igmp_joingroup(msg->msg.jl.interface, msg->msg.jl.multiaddr); - } else { - msg->conn->err = igmp_leavegroup(msg->msg.jl.interface, msg->msg.jl.multiaddr); - } -#endif /* LWIP_UDP */ -#if (LWIP_TCP || LWIP_RAW) - } else { - msg->conn->err = ERR_VAL; -#endif /* (LWIP_TCP || LWIP_RAW) */ - } - } - } - TCPIP_APIMSG_ACK(msg); -} -#endif /* LWIP_IGMP */ - -#if LWIP_DNS -/** - * Callback function that is called when DNS name is resolved - * (or on timeout). A waiting application thread is waked up by - * signaling the semaphore. - */ -static void -do_dns_found(const char *name, struct ip_addr *ipaddr, void *arg) -{ - struct dns_api_msg *msg = (struct dns_api_msg*)arg; - - LWIP_ASSERT("DNS response for wrong host name", strcmp(msg->name, name) == 0); - - if (ipaddr == NULL) { - /* timeout or memory error */ - *msg->err = ERR_VAL; - } else { - /* address was resolved */ - *msg->err = ERR_OK; - *msg->addr = *ipaddr; - } - /* wake up the application task waiting in netconn_gethostbyname */ - sys_sem_signal(msg->sem); -} - -/** - * Execute a DNS query - * Called from netconn_gethostbyname - * - * @param arg the dns_api_msg pointing to the query - */ -void -do_gethostbyname(void *arg) -{ - struct dns_api_msg *msg = (struct dns_api_msg*)arg; - - *msg->err = dns_gethostbyname(msg->name, msg->addr, do_dns_found, msg); - if (*msg->err != ERR_INPROGRESS) { - /* on error or immediate success, wake up the application - * task waiting in netconn_gethostbyname */ - sys_sem_signal(msg->sem); - } -} -#endif /* LWIP_DNS */ - -#endif /* LWIP_NETCONN */ diff --git a/components/net/lwip-1.3.2/src/api/err.c b/components/net/lwip-1.3.2/src/api/err.c deleted file mode 100644 index a90cb98c82..0000000000 --- a/components/net/lwip-1.3.2/src/api/err.c +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * Error Management module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/err.h" - -#ifdef LWIP_DEBUG - -static const char *err_strerr[] = { - "Ok.", /* ERR_OK 0 */ - "Out of memory error.", /* ERR_MEM -1 */ - "Buffer error.", /* ERR_BUF -2 */ - "Timeout.", /* ERR_TIMEOUT -3 */ - "Routing problem.", /* ERR_RTE -4 */ - "Connection aborted.", /* ERR_ABRT -5 */ - "Connection reset.", /* ERR_RST -6 */ - "Connection closed.", /* ERR_CLSD -7 */ - "Not connected.", /* ERR_CONN -8 */ - "Illegal value.", /* ERR_VAL -9 */ - "Illegal argument.", /* ERR_ARG -10 */ - "Address in use.", /* ERR_USE -11 */ - "Low-level netif error.", /* ERR_IF -12 */ - "Already connected.", /* ERR_ISCONN -13 */ - "Operation in progress." /* ERR_INPROGRESS -14 */ -}; - -/** - * Convert an lwip internal error to a string representation. - * - * @param err an lwip internal err_t - * @return a string representation for err - */ -const char * -lwip_strerr(err_t err) -{ - return err_strerr[-err]; - -} - -#endif /* LWIP_DEBUG */ diff --git a/components/net/lwip-1.3.2/src/api/netifapi.c b/components/net/lwip-1.3.2/src/api/netifapi.c deleted file mode 100644 index 57089864ae..0000000000 --- a/components/net/lwip-1.3.2/src/api/netifapi.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - * @file - * Network Interface Sequential API module - * - */ - -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" - -#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/netifapi.h" -#include "lwip/tcpip.h" - -/** - * Call netif_add() inside the tcpip_thread context. - */ -void -do_netifapi_netif_add( struct netifapi_msg_msg *msg) -{ - if (!netif_add( msg->netif, - msg->msg.add.ipaddr, - msg->msg.add.netmask, - msg->msg.add.gw, - msg->msg.add.state, - msg->msg.add.init, - msg->msg.add.input)) { - msg->err = ERR_IF; - } else { - msg->err = ERR_OK; - } - TCPIP_NETIFAPI_ACK(msg); -} - -/** - * Call netif_set_addr() inside the tcpip_thread context. - */ -void -do_netifapi_netif_set_addr( struct netifapi_msg_msg *msg) -{ - netif_set_addr( msg->netif, - msg->msg.add.ipaddr, - msg->msg.add.netmask, - msg->msg.add.gw); - msg->err = ERR_OK; - TCPIP_NETIFAPI_ACK(msg); -} - -/** - * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the - * tcpip_thread context. - */ -void -do_netifapi_netif_common( struct netifapi_msg_msg *msg) -{ - if (msg->msg.common.errtfunc!=NULL) { - msg->err = - msg->msg.common.errtfunc(msg->netif); - } else { - msg->err = ERR_OK; - msg->msg.common.voidfunc(msg->netif); - } - TCPIP_NETIFAPI_ACK(msg); -} - -/** - * Call netif_add() in a thread-safe way by running that function inside the - * tcpip_thread context. - * - * @note for params @see netif_add() - */ -err_t -netifapi_netif_add(struct netif *netif, - struct ip_addr *ipaddr, - struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) -{ - struct netifapi_msg msg; - msg.function = do_netifapi_netif_add; - msg.msg.netif = netif; - msg.msg.msg.add.ipaddr = ipaddr; - msg.msg.msg.add.netmask = netmask; - msg.msg.msg.add.gw = gw; - msg.msg.msg.add.state = state; - msg.msg.msg.add.init = init; - msg.msg.msg.add.input = input; - TCPIP_NETIFAPI(&msg); - return msg.msg.err; -} - -/** - * Call netif_set_addr() in a thread-safe way by running that function inside the - * tcpip_thread context. - * - * @note for params @see netif_set_addr() - */ -err_t -netifapi_netif_set_addr(struct netif *netif, - struct ip_addr *ipaddr, - struct ip_addr *netmask, - struct ip_addr *gw) -{ - struct netifapi_msg msg; - msg.function = do_netifapi_netif_set_addr; - msg.msg.netif = netif; - msg.msg.msg.add.ipaddr = ipaddr; - msg.msg.msg.add.netmask = netmask; - msg.msg.msg.add.gw = gw; - TCPIP_NETIFAPI(&msg); - return msg.msg.err; -} - -/** - * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe - * way by running that function inside the tcpip_thread context. - * - * @note use only for functions where there is only "netif" parameter. - */ -err_t -netifapi_netif_common( struct netif *netif, - void (* voidfunc)(struct netif *netif), - err_t (* errtfunc)(struct netif *netif) ) -{ - struct netifapi_msg msg; - msg.function = do_netifapi_netif_common; - msg.msg.netif = netif; - msg.msg.msg.common.voidfunc = voidfunc; - msg.msg.msg.common.errtfunc = errtfunc; - TCPIP_NETIFAPI(&msg); - return msg.msg.err; -} - -#endif /* LWIP_NETIF_API */ diff --git a/components/net/lwip-1.3.2/src/api/sockets.c b/components/net/lwip-1.3.2/src/api/sockets.c deleted file mode 100644 index fc56fb465e..0000000000 --- a/components/net/lwip-1.3.2/src/api/sockets.c +++ /dev/null @@ -1,1988 +0,0 @@ -/** - * @file - * Sockets BSD-Like API module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * Improved by Marc Boucher and David Haas - * - */ - -#include "lwip/opt.h" - -#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sockets.h" -#include "lwip/api.h" -#include "lwip/sys.h" -#include "lwip/igmp.h" -#include "lwip/inet.h" -#include "lwip/tcp.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcpip.h" - -#include - -#define NUM_SOCKETS MEMP_NUM_NETCONN - -/** Contains all internal pointers and states used for a socket */ -struct lwip_socket { - /** sockets currently are built on netconns, each socket has one netconn */ - struct netconn *conn; - /** data that was left from the previous read */ - struct netbuf *lastdata; - /** offset in the data that was left from the previous read */ - u16_t lastoffset; - /** number of times data was received, set by event_callback(), - tested by the receive and select functions */ - s16_t rcvevent; - /** number of times data was received, set by event_callback(), - tested by select */ - u16_t sendevent; - /** socket flags (currently, only used for O_NONBLOCK) */ - u16_t flags; - /** last error that occurred on this socket */ - int err; -}; - -/** Description for a task waiting in select */ -struct lwip_select_cb { - /** Pointer to the next waiting task */ - struct lwip_select_cb *next; - /** readset passed to select */ - fd_set *readset; - /** writeset passed to select */ - fd_set *writeset; - /** unimplemented: exceptset passed to select */ - fd_set *exceptset; - /** don't signal the same semaphore twice: set to 1 when signalled */ - int sem_signalled; - /** semaphore to wake up a task waiting for select */ - sys_sem_t sem; -}; - -/** This struct is used to pass data to the set/getsockopt_internal - * functions running in tcpip_thread context (only a void* is allowed) */ -struct lwip_setgetsockopt_data { - /** socket struct for which to change options */ - struct lwip_socket *sock; - /** socket index for which to change options */ - int s; - /** level of the option to process */ - int level; - /** name of the option to process */ - int optname; - /** set: value to set the option to - * get: value of the option is stored here */ - void *optval; - /** size of *optval */ - socklen_t *optlen; - /** if an error occures, it is temporarily stored here */ - err_t err; -}; - -/** The global array of available sockets */ -static struct lwip_socket sockets[NUM_SOCKETS]; -/** The global list of tasks waiting for select */ -static struct lwip_select_cb *select_cb_list; - -/** Semaphore protecting the sockets array */ -static sys_sem_t socksem; -/** Semaphore protecting select_cb_list */ -static sys_sem_t selectsem; - -/** Table to quickly map an lwIP error (err_t) to a socket error - * by using -err as an index */ -static const int err_to_errno_table[] = { - 0, /* ERR_OK 0 No error, everything OK. */ - ENOMEM, /* ERR_MEM -1 Out of memory error. */ - ENOBUFS, /* ERR_BUF -2 Buffer error. */ - ETIMEDOUT, /* ERR_TIMEOUT -3 Timeout */ - EHOSTUNREACH, /* ERR_RTE -4 Routing problem. */ - ECONNABORTED, /* ERR_ABRT -5 Connection aborted. */ - ECONNRESET, /* ERR_RST -6 Connection reset. */ - ESHUTDOWN, /* ERR_CLSD -7 Connection closed. */ - ENOTCONN, /* ERR_CONN -8 Not connected. */ - EINVAL, /* ERR_VAL -9 Illegal value. */ - EIO, /* ERR_ARG -10 Illegal argument. */ - EADDRINUSE, /* ERR_USE -11 Address in use. */ - -1, /* ERR_IF -12 Low-level netif error */ - -1, /* ERR_ISCONN -13 Already connected. */ - EINPROGRESS /* ERR_INPROGRESS -14 Operation in progress */ -}; - -#define ERR_TO_ERRNO_TABLE_SIZE \ - (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0])) - -#define err_to_errno(err) \ - ((unsigned)(-(err)) < ERR_TO_ERRNO_TABLE_SIZE ? \ - err_to_errno_table[-(err)] : EIO) - -#ifdef ERRNO -#ifndef set_errno -#define set_errno(err) errno = (err) -#endif -#else -#define set_errno(err) -#endif - -#define sock_set_errno(sk, e) do { \ - sk->err = (e); \ - set_errno(sk->err); \ -} while (0) - -/* Forward delcaration of some functions */ -static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); -static void lwip_getsockopt_internal(void *arg); -static void lwip_setsockopt_internal(void *arg); - -/** - * Initialize this module. This function has to be called before any other - * functions in this module! - */ -void -lwip_socket_init(void) -{ - socksem = sys_sem_new(1); - selectsem = sys_sem_new(1); -} - -/** - * Map a externally used socket index to the internal socket representation. - * - * @param s externally used socket index - * @return struct lwip_socket for the socket or NULL if not found - */ -static struct lwip_socket * -get_socket(int s) -{ - struct lwip_socket *sock; - - if ((s < 0) || (s >= NUM_SOCKETS)) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s)); - set_errno(EBADF); - return NULL; - } - - sock = &sockets[s]; - - if (!sock->conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s)); - set_errno(EBADF); - return NULL; - } - - return sock; -} - -/** - * Allocate a new socket for a given netconn. - * - * @param newconn the netconn for which to allocate a socket - * @return the index of the new socket; -1 on error - */ -static int -alloc_socket(struct netconn *newconn) -{ - int i; - - /* Protect socket array */ - sys_sem_wait(socksem); - - /* allocate a new socket identifier */ - for (i = 0; i < NUM_SOCKETS; ++i) { - if (!sockets[i].conn) { - sockets[i].conn = newconn; - sockets[i].lastdata = NULL; - sockets[i].lastoffset = 0; - sockets[i].rcvevent = 0; - sockets[i].sendevent = 1; /* TCP send buf is empty */ - sockets[i].flags = 0; - sockets[i].err = 0; - sys_sem_signal(socksem); - return i; - } - } - sys_sem_signal(socksem); - return -1; -} - -int lwip_get_error(int s) -{ - struct lwip_socket *sock; - sock = get_socket(s); - - return sock->err; -} - -/* Below this, the well-known socket functions are implemented. - * Use google.com or opengroup.org to get a good description :-) - * - * Exceptions are documented! - */ - -int -lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) -{ - struct lwip_socket *sock, *nsock; - struct netconn *newconn; - struct ip_addr naddr; - u16_t port; - int newsock; - struct sockaddr_in sin; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); - sock = get_socket(s); - if (!sock) - return -1; - - if ((sock->flags & O_NONBLOCK) && (sock->rcvevent <= 0)) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s)); - sock_set_errno(sock, EWOULDBLOCK); - return -1; - } - - newconn = netconn_accept(sock->conn); - if (!newconn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) failed, err=%d\n", s, sock->conn->err)); - sock_set_errno(sock, err_to_errno(sock->conn->err)); - return -1; - } - - /* get the IP address and port of the remote host */ - err = netconn_peer(newconn, &naddr, &port); - if (err != ERR_OK) { - netconn_delete(newconn); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - /* Note that POSIX only requires us to check addr is non-NULL. addrlen must - * not be NULL if addr is valid. - */ - if (NULL != addr) { - LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL); - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_port = htons(port); - sin.sin_addr.s_addr = naddr.addr; - - if (*addrlen > sizeof(sin)) - *addrlen = sizeof(sin); - - MEMCPY(addr, &sin, *addrlen); - } - - newsock = alloc_socket(newconn); - if (newsock == -1) { - netconn_delete(newconn); - sock_set_errno(sock, ENFILE); - return -1; - } - LWIP_ASSERT("invalid socket index", (newsock >= 0) && (newsock < NUM_SOCKETS)); - newconn->callback = event_callback; - nsock = &sockets[newsock]; - LWIP_ASSERT("invalid socket pointer", nsock != NULL); - - sys_sem_wait(socksem); - /* See event_callback: If data comes in right away after an accept, even - * though the server task might not have created a new socket yet. - * In that case, newconn->socket is counted down (newconn->socket--), - * so nsock->rcvevent is >= 1 here! - */ - nsock->rcvevent += -1 - newconn->socket; - newconn->socket = newsock; - sys_sem_signal(socksem); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); - ip_addr_debug_print(SOCKETS_DEBUG, &naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port)); - - sock_set_errno(sock, 0); - return newsock; -} - -int -lwip_bind(int s, const struct sockaddr *name, socklen_t namelen) -{ - struct lwip_socket *sock; - struct ip_addr local_addr; - u16_t local_port; - err_t err; - - sock = get_socket(s); - if (!sock) - return -1; - - LWIP_ERROR("lwip_bind: invalid address", ((namelen == sizeof(struct sockaddr_in)) && - ((((const struct sockaddr_in *)name)->sin_family) == AF_INET)), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - - local_addr.addr = ((const struct sockaddr_in *)name)->sin_addr.s_addr; - local_port = ((const struct sockaddr_in *)name)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &local_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(local_port))); - - err = netconn_bind(sock->conn, &local_addr, ntohs(local_port)); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_close(int s) -{ - struct lwip_socket *sock; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); - - sock = get_socket(s); - if (!sock) { - return -1; - } - - netconn_delete(sock->conn); - - sys_sem_wait(socksem); - if (sock->lastdata) { - netbuf_delete(sock->lastdata); - } - sock->lastdata = NULL; - sock->lastoffset = 0; - sock->conn = NULL; - sock_set_errno(sock, 0); - sys_sem_signal(socksem); - return 0; -} - -int -lwip_connect(int s, const struct sockaddr *name, socklen_t namelen) -{ - struct lwip_socket *sock; - err_t err; - - sock = get_socket(s); - if (!sock) - return -1; - - LWIP_ERROR("lwip_connect: invalid address", ((namelen == sizeof(struct sockaddr_in)) && - ((((const struct sockaddr_in *)name)->sin_family) == AF_INET)), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - - if (((const struct sockaddr_in *)name)->sin_family == AF_UNSPEC) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); - err = netconn_disconnect(sock->conn); - } else { - struct ip_addr remote_addr; - u16_t remote_port; - - remote_addr.addr = ((const struct sockaddr_in *)name)->sin_addr.s_addr; - remote_port = ((const struct sockaddr_in *)name)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(remote_port))); - - err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); - } - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -/** - * Set a socket into listen mode. - * The socket may not have been used for another connection previously. - * - * @param s the socket to set to listening mode - * @param backlog (ATTENTION: need TCP_LISTEN_BACKLOG=1) - * @return 0 on success, non-zero on failure - */ -int -lwip_listen(int s, int backlog) -{ - struct lwip_socket *sock; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); - - sock = get_socket(s); - if (!sock) - return -1; - - /* limit the "backlog" parameter to fit in an u8_t */ - if (backlog < 0) { - backlog = 0; - } - if (backlog > 0xff) { - backlog = 0xff; - } - - err = netconn_listen_with_backlog(sock->conn, backlog); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_recvfrom(int s, void *mem, size_t len, int flags, - struct sockaddr *from, socklen_t *fromlen) -{ - struct lwip_socket *sock; - struct netbuf *buf; - u16_t buflen, copylen, off = 0; - struct ip_addr *addr; - u16_t port; - u8_t done = 0; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags)); - sock = get_socket(s); - if (!sock) - return -1; - - do { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", (void*)sock->lastdata)); - /* Check if there is data left from the last recv operation. */ - if (sock->lastdata) { - buf = sock->lastdata; - } else { - /* If this is non-blocking call, then check first */ - if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) && - (sock->rcvevent <= 0)) { - if (off > 0) { - /* already received data, return that */ - sock_set_errno(sock, 0); - return off; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); - sock_set_errno(sock, EWOULDBLOCK); - return -1; - } - - /* No data was left from the previous operation, so we try to get - some from the network. */ - sock->lastdata = buf = netconn_recv(sock->conn); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv netbuf=%p\n", (void*)buf)); - - if (!buf) { - if (off > 0) { - /* already received data, return that */ - sock_set_errno(sock, 0); - return off; - } - /* We should really do some error checking here. */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s)); - sock_set_errno(sock, (((sock->conn->pcb.ip != NULL) && (sock->conn->err == ERR_OK)) - ? ETIMEDOUT : err_to_errno(sock->conn->err))); - return 0; - } - } - - buflen = netbuf_len(buf); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%"U16_F" sock->lastoffset=%"U16_F"\n", - buflen, len, off, sock->lastoffset)); - - buflen -= sock->lastoffset; - - if (len > buflen) { - copylen = buflen; - } else { - copylen = (u16_t)len; - } - - /* copy the contents of the received buffer into - the supplied memory pointer mem */ - netbuf_copy_partial(buf, (u8_t*)mem + off, copylen, sock->lastoffset); - - off += copylen; - - if (netconn_type(sock->conn) == NETCONN_TCP) { - LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen); - len -= copylen; - if ( (len <= 0) || - (buf->p->flags & PBUF_FLAG_PUSH) || - (sock->rcvevent <= 0) || - ((flags & MSG_PEEK)!=0)) { - done = 1; - } - } else { - done = 1; - } - - /* Check to see from where the data was.*/ - if (done) { - if (from && fromlen) { - struct sockaddr_in sin; - - if (netconn_type(sock->conn) == NETCONN_TCP) { - addr = (struct ip_addr*)&(sin.sin_addr.s_addr); - netconn_getaddr(sock->conn, addr, &port, 0); - } else { - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - } - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_port = htons(port); - sin.sin_addr.s_addr = addr->addr; - - if (*fromlen > sizeof(sin)) { - *fromlen = sizeof(sin); - } - - MEMCPY(from, &sin, *fromlen); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%"U16_F"\n", port, off)); - } else { - #if SOCKETS_DEBUG - struct sockaddr_in sin; - - if (netconn_type(sock->conn) == NETCONN_TCP) { - addr = (struct ip_addr*)&(sin.sin_addr.s_addr); - netconn_getaddr(sock->conn, addr, &port, 0); - } else { - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%"U16_F"\n", port, off)); - #endif /* SOCKETS_DEBUG */ - } - } - - /* If we don't peek the incoming message... */ - if ((flags & MSG_PEEK)==0) { - /* If this is a TCP socket, check if there is data left in the - buffer. If so, it should be saved in the sock structure for next - time around. */ - if ((netconn_type(sock->conn) == NETCONN_TCP) && (buflen - copylen > 0)) { - sock->lastdata = buf; - sock->lastoffset += copylen; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", (void*)buf)); - } else { - sock->lastdata = NULL; - sock->lastoffset = 0; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", (void*)buf)); - netbuf_delete(buf); - } - } - } while (!done); - - sock_set_errno(sock, 0); - return off; -} - -int -lwip_read(int s, void *mem, size_t len) -{ - return lwip_recvfrom(s, mem, len, 0, NULL, NULL); -} - -int -lwip_recv(int s, void *mem, size_t len, int flags) -{ - return lwip_recvfrom(s, mem, len, flags, NULL, NULL); -} - -int -lwip_send(int s, const void *data, size_t size, int flags) -{ - struct lwip_socket *sock; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n", - s, data, size, flags)); - - sock = get_socket(s); - if (!sock) - return -1; - - if (sock->conn->type != NETCONN_TCP) { -#if (LWIP_UDP || LWIP_RAW) - return lwip_sendto(s, data, size, flags, NULL, 0); -#else - sock_set_errno(sock, err_to_errno(ERR_ARG)); - return -1; -#endif /* (LWIP_UDP || LWIP_RAW) */ - } - - err = netconn_write(sock->conn, data, size, NETCONN_COPY | ((flags & MSG_MORE)?NETCONN_MORE:0)); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d size=%"SZT_F"\n", s, err, size)); - sock_set_errno(sock, err_to_errno(err)); - return (err == ERR_OK ? (int)size : -1); -} - -int -lwip_sendto(int s, const void *data, size_t size, int flags, - const struct sockaddr *to, socklen_t tolen) -{ - struct lwip_socket *sock; - struct ip_addr remote_addr; - err_t err; - u16_t short_size; -#if !LWIP_TCPIP_CORE_LOCKING - struct netbuf buf; - u16_t remote_port; -#endif - - sock = get_socket(s); - if (!sock) - return -1; - - if (sock->conn->type == NETCONN_TCP) { -#if LWIP_TCP - return lwip_send(s, data, size, flags); -#else - sock_set_errno(sock, err_to_errno(ERR_ARG)); - return -1; -#endif /* LWIP_TCP */ - } - - LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff); - short_size = (u16_t)size; - LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) || - ((tolen == sizeof(struct sockaddr_in)) && - ((((const struct sockaddr_in *)to)->sin_family) == AF_INET))), - sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); - -#if LWIP_TCPIP_CORE_LOCKING - /* Should only be consider like a sample or a simple way to experiment this option (no check of "to" field...) */ - { struct pbuf* p; - - p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); - if (p == NULL) { - err = ERR_MEM; - } else { - p->payload = (void*)data; - p->len = p->tot_len = short_size; - - remote_addr.addr = ((const struct sockaddr_in *)to)->sin_addr.s_addr; - - LOCK_TCPIP_CORE(); - if (sock->conn->type==NETCONN_RAW) { - err = sock->conn->err = raw_sendto(sock->conn->pcb.raw, p, &remote_addr); - } else { - err = sock->conn->err = udp_sendto(sock->conn->pcb.udp, p, &remote_addr, ntohs(((const struct sockaddr_in *)to)->sin_port)); - } - UNLOCK_TCPIP_CORE(); - - pbuf_free(p); - } - } -#else - /* initialize a buffer */ - buf.p = buf.ptr = NULL; - if (to) { - remote_addr.addr = ((const struct sockaddr_in *)to)->sin_addr.s_addr; - remote_port = ntohs(((const struct sockaddr_in *)to)->sin_port); - buf.addr = &remote_addr; - buf.port = remote_port; - } else { - remote_addr.addr = 0; - remote_port = 0; - buf.addr = NULL; - buf.port = 0; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%d"U16_F", flags=0x%x to=", - s, data, short_size, flags)); - ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port)); - - /* make the buffer point to the data that should be sent */ -#if LWIP_NETIF_TX_SINGLE_PBUF - /* Allocate a new netbuf and copy the data into it. */ - if (netbuf_alloc(&buf, short_size) == NULL) { - err = ERR_MEM; - } else { - err = netbuf_take(&buf, data, short_size); - } -#else /* LWIP_NETIF_TX_SINGLE_PBUF */ - err = netbuf_ref(&buf, data, short_size); -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - if (err == ERR_OK) { - /* send the data */ - err = netconn_send(sock->conn, &buf); - } - - /* deallocated the buffer */ - netbuf_free(&buf); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - sock_set_errno(sock, err_to_errno(err)); - return (err == ERR_OK ? short_size : -1); -} - -int -lwip_socket(int domain, int type, int protocol) -{ - struct netconn *conn; - int i; - - LWIP_UNUSED_ARG(domain); - - /* create a netconn */ - switch (type) { - case SOCK_RAW: - conn = netconn_new_with_proto_and_callback(NETCONN_RAW, (u8_t)protocol, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", - domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_DGRAM: - conn = netconn_new_with_callback( (protocol == IPPROTO_UDPLITE) ? - NETCONN_UDPLITE : NETCONN_UDP, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", - domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_STREAM: - conn = netconn_new_with_callback(NETCONN_TCP, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", - domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", - domain, type, protocol)); - set_errno(EINVAL); - return -1; - } - - if (!conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); - set_errno(ENOBUFS); - return -1; - } - - i = alloc_socket(conn); - - if (i == -1) { - netconn_delete(conn); - set_errno(ENFILE); - return -1; - } - conn->socket = i; - LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); - set_errno(0); - return i; -} - -int -lwip_write(int s, const void *data, size_t size) -{ - return lwip_send(s, data, size, 0); -} - -/** - * Go through the readset and writeset lists and see which socket of the sockets - * set in the sets has events. On return, readset, writeset and exceptset have - * the sockets enabled that had events. - * - * exceptset is not used for now!!! - * - * @param maxfdp1 the highest socket index in the sets - * @param readset in: set of sockets to check for read events; - * out: set of sockets that had read events - * @param writeset in: set of sockets to check for write events; - * out: set of sockets that had write events - * @param exceptset not yet implemented - * @return number of sockets that had events (read+write) - */ -static int -lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset) -{ - int i, nready = 0; - fd_set lreadset, lwriteset, lexceptset; - struct lwip_socket *p_sock; - - FD_ZERO(&lreadset); - FD_ZERO(&lwriteset); - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - for(i = 0; i < maxfdp1; i++) { - if (FD_ISSET(i, readset)) { - /* See if netconn of this socket is ready for read */ - p_sock = get_socket(i); - if (p_sock && (p_sock->lastdata || (p_sock->rcvevent > 0))) { - FD_SET(i, &lreadset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); - nready++; - } - } - if (FD_ISSET(i, writeset)) { - /* See if netconn of this socket is ready for write */ - p_sock = get_socket(i); - if (p_sock && p_sock->sendevent) { - FD_SET(i, &lwriteset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); - nready++; - } - } - } - *readset = lreadset; - *writeset = lwriteset; - FD_ZERO(exceptset); - - return nready; -} - - -/** - * Processing exceptset is not yet implemented. - */ -int -lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout) -{ - int i; - int nready; - fd_set lreadset, lwriteset, lexceptset; - u32_t msectimeout; - struct lwip_select_cb select_cb; - struct lwip_select_cb *p_selcb; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", - maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, - timeout ? (long)timeout->tv_sec : (long)-1, - timeout ? (long)timeout->tv_usec : (long)-1)); - - select_cb.next = 0; - select_cb.readset = readset; - select_cb.writeset = writeset; - select_cb.exceptset = exceptset; - select_cb.sem_signalled = 0; - - /* Protect ourselves searching through the list */ - sys_sem_wait(selectsem); - - if (readset) - lreadset = *readset; - else - FD_ZERO(&lreadset); - if (writeset) - lwriteset = *writeset; - else - FD_ZERO(&lwriteset); - if (exceptset) - lexceptset = *exceptset; - else - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); - - /* If we don't have any current events, then suspend if we are supposed to */ - if (!nready) { - if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) { - sys_sem_signal(selectsem); - if (readset) - FD_ZERO(readset); - if (writeset) - FD_ZERO(writeset); - if (exceptset) - FD_ZERO(exceptset); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); - set_errno(0); - - return 0; - } - - /* add our semaphore to list */ - /* We don't actually need any dynamic memory. Our entry on the - * list is only valid while we are in this function, so it's ok - * to use local variables */ - - select_cb.sem = sys_sem_new(0); - /* Note that we are still protected */ - /* Put this select_cb on top of list */ - select_cb.next = select_cb_list; - select_cb_list = &select_cb; - - /* Now we can safely unprotect */ - sys_sem_signal(selectsem); - - /* Now just wait to be woken */ - if (timeout == 0) - /* Wait forever */ - msectimeout = 0; - else { - msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); - if(msectimeout == 0) - msectimeout = 1; - } - - if (sys_arch_timeouts() == NULL){ - /* it's not a lwip thread, use os semaphore with timeout to handle it */ - i = sys_arch_sem_wait(select_cb.sem, msectimeout); - if (i == SYS_ARCH_TIMEOUT) i = 0; - else i = 1; - } - else { - /* it's a lwip thread, use os semaphore with timeout to handle it */ - i = sys_sem_wait_timeout(select_cb.sem, msectimeout); - } - - /* Take us off the list */ - sys_sem_wait(selectsem); - if (select_cb_list == &select_cb) - select_cb_list = select_cb.next; - else - for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) { - if (p_selcb->next == &select_cb) { - p_selcb->next = select_cb.next; - break; - } - } - - sys_sem_signal(selectsem); - - sys_sem_free(select_cb.sem); - if (i == 0) { - /* Timeout */ - if (readset) - FD_ZERO(readset); - if (writeset) - FD_ZERO(writeset); - if (exceptset) - FD_ZERO(exceptset); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); - set_errno(0); - - return 0; - } - - if (readset) - lreadset = *readset; - else - FD_ZERO(&lreadset); - if (writeset) - lwriteset = *writeset; - else - FD_ZERO(&lwriteset); - if (exceptset) - lexceptset = *exceptset; - else - FD_ZERO(&lexceptset); - - /* See what's set */ - nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); - } else - sys_sem_signal(selectsem); - - if (readset) - *readset = lreadset; - if (writeset) - *writeset = lwriteset; - if (exceptset) - *exceptset = lexceptset; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); - set_errno(0); - - return nready; -} - -/** - * Callback registered in the netconn layer for each socket-netconn. - * Processes recvevent (data available) and wakes up tasks waiting for select. - */ -static void -event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) -{ - int s; - struct lwip_socket *sock; - struct lwip_select_cb *scb; - - LWIP_UNUSED_ARG(len); - - /* Get socket */ - if (conn) { - s = conn->socket; - if (s < 0) { - /* Data comes in right away after an accept, even though - * the server task might not have created a new socket yet. - * Just count down (or up) if that's the case and we - * will use the data later. Note that only receive events - * can happen before the new socket is set up. */ - sys_sem_wait(socksem); - if (conn->socket < 0) { - if (evt == NETCONN_EVT_RCVPLUS) { - conn->socket--; - } - sys_sem_signal(socksem); - return; - } - s = conn->socket; - sys_sem_signal(socksem); - } - - sock = get_socket(s); - if (!sock) { - return; - } - } else { - return; - } - - sys_sem_wait(selectsem); - /* Set event as required */ - switch (evt) { - case NETCONN_EVT_RCVPLUS: - sock->rcvevent++; - break; - case NETCONN_EVT_RCVMINUS: - sock->rcvevent--; - break; - case NETCONN_EVT_SENDPLUS: - sock->sendevent = 1; - break; - case NETCONN_EVT_SENDMINUS: - sock->sendevent = 0; - break; - default: - LWIP_ASSERT("unknown event", 0); - break; - } - sys_sem_signal(selectsem); - - /* Now decide if anyone is waiting for this socket */ - /* NOTE: This code is written this way to protect the select link list - but to avoid a deadlock situation by releasing socksem before - signalling for the select. This means we need to go through the list - multiple times ONLY IF a select was actually waiting. We go through - the list the number of waiting select calls + 1. This list is - expected to be small. */ - while (1) { - sys_sem_wait(selectsem); - for (scb = select_cb_list; scb; scb = scb->next) { - if (scb->sem_signalled == 0) { - /* Test this select call for our socket */ - if (scb->readset && FD_ISSET(s, scb->readset)) - if (sock->rcvevent > 0) - break; - if (scb->writeset && FD_ISSET(s, scb->writeset)) - if (sock->sendevent) - break; - } - } - if (scb) { - scb->sem_signalled = 1; - sys_sem_signal(scb->sem); - sys_sem_signal(selectsem); - } else { - sys_sem_signal(selectsem); - break; - } - } -} - -/** - * Unimplemented: Close one end of a full-duplex connection. - * Currently, the full connection is closed. - */ -int -lwip_shutdown(int s, int how) -{ - LWIP_UNUSED_ARG(how); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); - return lwip_close(s); /* XXX temporary hack until proper implementation */ -} - -static int -lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local) -{ - struct lwip_socket *sock; - struct sockaddr_in sin; - struct ip_addr naddr; - - sock = get_socket(s); - if (!sock) - return -1; - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - - /* get the IP address and port */ - netconn_getaddr(sock->conn, &naddr, &sin.sin_port, local); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", sin.sin_port)); - - sin.sin_port = htons(sin.sin_port); - sin.sin_addr.s_addr = naddr.addr; - - if (*namelen > sizeof(sin)) - *namelen = sizeof(sin); - - MEMCPY(name, &sin, *namelen); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen) -{ - return lwip_getaddrname(s, name, namelen, 0); -} - -int -lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen) -{ - return lwip_getaddrname(s, name, namelen, 1); -} - -int -lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) -{ - err_t err = ERR_OK; - struct lwip_socket *sock = get_socket(s); - struct lwip_setgetsockopt_data data; - - if (!sock) - return -1; - - if ((NULL == optval) || (NULL == optlen)) { - sock_set_errno(sock, EFAULT); - return -1; - } - - /* Do length and type checks for the various options first, to keep it readable. */ - switch (level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch (optname) { - - case SO_ACCEPTCONN: - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_ERROR: - case SO_KEEPALIVE: - /* UNIMPL case SO_CONTIMEO: */ - /* UNIMPL case SO_SNDTIMEO: */ -#if LWIP_SO_RCVTIMEO - case SO_RCVTIMEO: -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - case SO_RCVBUF: -#endif /* LWIP_SO_RCVBUF */ - /* UNIMPL case SO_OOBINLINE: */ - /* UNIMPL case SO_SNDBUF: */ - /* UNIMPL case SO_RCVLOWAT: */ - /* UNIMPL case SO_SNDLOWAT: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - case SO_TYPE: - /* UNIMPL case SO_USELOOPBACK: */ - if (*optlen < sizeof(int)) { - err = EINVAL; - } - break; - - case SO_NO_CHECK: - if (*optlen < sizeof(int)) { - err = EINVAL; - } -#if LWIP_UDP - if ((sock->conn->type != NETCONN_UDP) || - ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) { - /* this flag is only available for UDP, not for UDP lite */ - err = EAFNOSUPPORT; - } -#endif /* LWIP_UDP */ - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch (optname) { - /* UNIMPL case IP_HDRINCL: */ - /* UNIMPL case IP_RCVDSTADDR: */ - /* UNIMPL case IP_RCVIF: */ - case IP_TTL: - case IP_TOS: - if (*optlen < sizeof(int)) { - err = EINVAL; - } - break; -#if LWIP_IGMP - case IP_MULTICAST_TTL: - if (*optlen < sizeof(u8_t)) { - err = EINVAL; - } - break; - case IP_MULTICAST_IF: - if (*optlen < sizeof(struct in_addr)) { - err = EINVAL; - } - break; -#endif /* LWIP_IGMP */ - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; - -#if LWIP_TCP -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - if (*optlen < sizeof(int)) { - err = EINVAL; - break; - } - - /* If this is no TCP socket, ignore any options. */ - if (sock->conn->type != NETCONN_TCP) - return 0; - - switch (optname) { - case TCP_NODELAY: - case TCP_KEEPALIVE: -#if LWIP_TCP_KEEPALIVE - case TCP_KEEPIDLE: - case TCP_KEEPINTVL: - case TCP_KEEPCNT: -#endif /* LWIP_TCP_KEEPALIVE */ - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; -#endif /* LWIP_TCP */ -#if LWIP_UDP && LWIP_UDPLITE -/* Level: IPPROTO_UDPLITE */ - case IPPROTO_UDPLITE: - if (*optlen < sizeof(int)) { - err = EINVAL; - break; - } - - /* If this is no UDP lite socket, ignore any options. */ - if (sock->conn->type != NETCONN_UDPLITE) - return 0; - - switch (optname) { - case UDPLITE_SEND_CSCOV: - case UDPLITE_RECV_CSCOV: - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; -#endif /* LWIP_UDP && LWIP_UDPLITE*/ -/* UNDEFINED LEVEL */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", - s, level, optname)); - err = ENOPROTOOPT; - } /* switch */ - - - if (err != ERR_OK) { - sock_set_errno(sock, err); - return -1; - } - - /* Now do the actual option processing */ - data.sock = sock; - data.level = level; - data.optname = optname; - data.optval = optval; - data.optlen = optlen; - data.err = err; - tcpip_callback(lwip_getsockopt_internal, &data); - sys_arch_sem_wait(sock->conn->op_completed, 0); - /* maybe lwip_getsockopt_internal has changed err */ - err = data.err; - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -static void -lwip_getsockopt_internal(void *arg) -{ - struct lwip_socket *sock; -#ifdef LWIP_DEBUG - int s; -#endif /* LWIP_DEBUG */ - int level, optname; - void *optval; - struct lwip_setgetsockopt_data *data; - - LWIP_ASSERT("arg != NULL", arg != NULL); - - data = (struct lwip_setgetsockopt_data*)arg; - sock = data->sock; -#ifdef LWIP_DEBUG - s = data->s; -#endif /* LWIP_DEBUG */ - level = data->level; - optname = data->optname; - optval = data->optval; - - switch (level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch (optname) { - - /* The option flags */ - case SO_ACCEPTCONN: - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINCLUDE: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /*case SO_USELOOPBACK: UNIMPL */ - *(int*)optval = sock->conn->pcb.ip->so_options & optname; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", - s, optname, (*(int*)optval?"on":"off"))); - break; - - case SO_TYPE: - switch (NETCONNTYPE_GROUP(sock->conn->type)) { - case NETCONN_RAW: - *(int*)optval = SOCK_RAW; - break; - case NETCONN_TCP: - *(int*)optval = SOCK_STREAM; - break; - case NETCONN_UDP: - *(int*)optval = SOCK_DGRAM; - break; - default: /* unrecognized socket type */ - *(int*)optval = sock->conn->type; - LWIP_DEBUGF(SOCKETS_DEBUG, - ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", - s, *(int *)optval)); - } /* switch (sock->conn->type) */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", - s, *(int *)optval)); - break; - - case SO_ERROR: - if (sock->err == 0) { - sock_set_errno(sock, err_to_errno(sock->conn->err)); - } - *(int *)optval = sock->err; - sock->err = 0; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", - s, *(int *)optval)); - break; - -#if LWIP_SO_RCVTIMEO - case SO_RCVTIMEO: - *(int *)optval = sock->conn->recv_timeout; - break; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - case SO_RCVBUF: - *(int *)optval = sock->conn->recv_bufsize; - break; -#endif /* LWIP_SO_RCVBUF */ -#if LWIP_UDP - case SO_NO_CHECK: - *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0; - break; -#endif /* LWIP_UDP*/ - } /* switch (optname) */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch (optname) { - case IP_TTL: - *(int*)optval = sock->conn->pcb.ip->ttl; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", - s, *(int *)optval)); - break; - case IP_TOS: - *(int*)optval = sock->conn->pcb.ip->tos; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", - s, *(int *)optval)); - break; -#if LWIP_IGMP - case IP_MULTICAST_TTL: - *(u8_t*)optval = sock->conn->pcb.ip->ttl; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n", - s, *(int *)optval)); - break; - case IP_MULTICAST_IF: - ((struct in_addr*) optval)->s_addr = sock->conn->pcb.udp->multicast_ip.addr; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n", - s, *(u32_t *)optval)); - break; -#endif /* LWIP_IGMP */ - } /* switch (optname) */ - break; - -#if LWIP_TCP -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - switch (optname) { - case TCP_NODELAY: - *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", - s, (*(int*)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", - s, *(int *)optval)); - break; - -#if LWIP_TCP_KEEPALIVE - case TCP_KEEPIDLE: - *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPIDLE) = %d\n", - s, *(int *)optval)); - break; - case TCP_KEEPINTVL: - *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPINTVL) = %d\n", - s, *(int *)optval)); - break; - case TCP_KEEPCNT: - *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPCNT) = %d\n", - s, *(int *)optval)); - break; -#endif /* LWIP_TCP_KEEPALIVE */ - - } /* switch (optname) */ - break; -#endif /* LWIP_TCP */ -#if LWIP_UDP && LWIP_UDPLITE - /* Level: IPPROTO_UDPLITE */ - case IPPROTO_UDPLITE: - switch (optname) { - case UDPLITE_SEND_CSCOV: - *(int*)optval = sock->conn->pcb.udp->chksum_len_tx; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n", - s, (*(int*)optval)) ); - break; - case UDPLITE_RECV_CSCOV: - *(int*)optval = sock->conn->pcb.udp->chksum_len_rx; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n", - s, (*(int*)optval)) ); - break; - } /* switch (optname) */ - break; -#endif /* LWIP_UDP */ - } /* switch (level) */ - sys_sem_signal(sock->conn->op_completed); -} - -int -lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen) -{ - struct lwip_socket *sock = get_socket(s); - int err = ERR_OK; - struct lwip_setgetsockopt_data data; - - if (!sock) - return -1; - - if (NULL == optval) { - sock_set_errno(sock, EFAULT); - return -1; - } - - /* Do length and type checks for the various options first, to keep it readable. */ - switch (level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch (optname) { - - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case case SO_CONTIMEO: */ - /* UNIMPL case case SO_SNDTIMEO: */ -#if LWIP_SO_RCVTIMEO - case SO_RCVTIMEO: -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - case SO_RCVBUF: -#endif /* LWIP_SO_RCVBUF */ - /* UNIMPL case SO_OOBINLINE: */ - /* UNIMPL case SO_SNDBUF: */ - /* UNIMPL case SO_RCVLOWAT: */ - /* UNIMPL case SO_SNDLOWAT: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /* UNIMPL case SO_USELOOPBACK: */ - if (optlen < sizeof(int)) { - err = EINVAL; - } - break; - case SO_NO_CHECK: - if (optlen < sizeof(int)) { - err = EINVAL; - } -#if LWIP_UDP - if ((sock->conn->type != NETCONN_UDP) || - ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) { - /* this flag is only available for UDP, not for UDP lite */ - err = EAFNOSUPPORT; - } -#endif /* LWIP_UDP */ - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch (optname) { - /* UNIMPL case IP_HDRINCL: */ - /* UNIMPL case IP_RCVDSTADDR: */ - /* UNIMPL case IP_RCVIF: */ - case IP_TTL: - case IP_TOS: - if (optlen < sizeof(int)) { - err = EINVAL; - } - break; -#if LWIP_IGMP - case IP_MULTICAST_TTL: - if (optlen < sizeof(u8_t)) { - err = EINVAL; - } - if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { - err = EAFNOSUPPORT; - } - break; - case IP_MULTICAST_IF: - if (optlen < sizeof(struct in_addr)) { - err = EINVAL; - } - if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { - err = EAFNOSUPPORT; - } - break; - case IP_ADD_MEMBERSHIP: - case IP_DROP_MEMBERSHIP: - if (optlen < sizeof(struct ip_mreq)) { - err = EINVAL; - } - if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { - err = EAFNOSUPPORT; - } - break; -#endif /* LWIP_IGMP */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; - -#if LWIP_TCP -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - if (optlen < sizeof(int)) { - err = EINVAL; - break; - } - - /* If this is no TCP socket, ignore any options. */ - if (sock->conn->type != NETCONN_TCP) - return 0; - - switch (optname) { - case TCP_NODELAY: - case TCP_KEEPALIVE: -#if LWIP_TCP_KEEPALIVE - case TCP_KEEPIDLE: - case TCP_KEEPINTVL: - case TCP_KEEPCNT: -#endif /* LWIP_TCP_KEEPALIVE */ - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; -#endif /* LWIP_TCP */ -#if LWIP_UDP && LWIP_UDPLITE -/* Level: IPPROTO_UDPLITE */ - case IPPROTO_UDPLITE: - if (optlen < sizeof(int)) { - err = EINVAL; - break; - } - - /* If this is no UDP lite socket, ignore any options. */ - if (sock->conn->type != NETCONN_UDPLITE) - return 0; - - switch (optname) { - case UDPLITE_SEND_CSCOV: - case UDPLITE_RECV_CSCOV: - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", - s, optname)); - err = ENOPROTOOPT; - } /* switch (optname) */ - break; -#endif /* LWIP_UDP && LWIP_UDPLITE */ -/* UNDEFINED LEVEL */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", - s, level, optname)); - err = ENOPROTOOPT; - } /* switch (level) */ - - - if (err != ERR_OK) { - sock_set_errno(sock, err); - return -1; - } - - - /* Now do the actual option processing */ - data.sock = sock; - data.level = level; - data.optname = optname; - data.optval = (void*)optval; - data.optlen = &optlen; - data.err = err; - tcpip_callback(lwip_setsockopt_internal, &data); - sys_arch_sem_wait(sock->conn->op_completed, 0); - /* maybe lwip_setsockopt_internal has changed err */ - err = data.err; - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -static void -lwip_setsockopt_internal(void *arg) -{ - struct lwip_socket *sock; -#ifdef LWIP_DEBUG - int s; -#endif /* LWIP_DEBUG */ - int level, optname; - const void *optval; - struct lwip_setgetsockopt_data *data; - - LWIP_ASSERT("arg != NULL", arg != NULL); - - data = (struct lwip_setgetsockopt_data*)arg; - sock = data->sock; -#ifdef LWIP_DEBUG - s = data->s; -#endif /* LWIP_DEBUG */ - level = data->level; - optname = data->optname; - optval = data->optval; - - switch (level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch (optname) { - - /* The option flags */ - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINCLUDE: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /* UNIMPL case SO_USELOOPBACK: */ - if (*(int*)optval) { - sock->conn->pcb.ip->so_options |= optname; - } else { - sock->conn->pcb.ip->so_options &= ~optname; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", - s, optname, (*(int*)optval?"on":"off"))); - break; -#if LWIP_SO_RCVTIMEO - case SO_RCVTIMEO: - sock->conn->recv_timeout = ( *(int*)optval ); - break; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - case SO_RCVBUF: - sock->conn->recv_bufsize = ( *(int*)optval ); - break; -#endif /* LWIP_SO_RCVBUF */ -#if LWIP_UDP - case SO_NO_CHECK: - if (*(int*)optval) { - udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM); - } else { - udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM); - } - break; -#endif /* LWIP_UDP */ - } /* switch (optname) */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch (optname) { - case IP_TTL: - sock->conn->pcb.ip->ttl = (u8_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n", - s, sock->conn->pcb.ip->ttl)); - break; - case IP_TOS: - sock->conn->pcb.ip->tos = (u8_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n", - s, sock->conn->pcb.ip->tos)); - break; -#if LWIP_IGMP - case IP_MULTICAST_TTL: - sock->conn->pcb.udp->ttl = (u8_t)(*(u8_t*)optval); - break; - case IP_MULTICAST_IF: - sock->conn->pcb.udp->multicast_ip.addr = ((struct in_addr*) optval)->s_addr; - break; - case IP_ADD_MEMBERSHIP: - case IP_DROP_MEMBERSHIP: - { - /* If this is a TCP or a RAW socket, ignore these options. */ - struct ip_mreq *imr = (struct ip_mreq *)optval; - if(optname == IP_ADD_MEMBERSHIP){ - data->err = igmp_joingroup((struct ip_addr*)&(imr->imr_interface.s_addr), (struct ip_addr*)&(imr->imr_multiaddr.s_addr)); - } else { - data->err = igmp_leavegroup((struct ip_addr*)&(imr->imr_interface.s_addr), (struct ip_addr*)&(imr->imr_multiaddr.s_addr)); - } - if(data->err != ERR_OK) { - data->err = EADDRNOTAVAIL; - } - } - break; -#endif /* LWIP_IGMP */ - } /* switch (optname) */ - break; - -#if LWIP_TCP -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - switch (optname) { - case TCP_NODELAY: - if (*(int*)optval) { - tcp_nagle_disable(sock->conn->pcb.tcp); - } else { - tcp_nagle_enable(sock->conn->pcb.tcp); - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", - s, (*(int *)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - sock->conn->pcb.tcp->keep_idle = (u32_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_idle)); - break; - -#if LWIP_TCP_KEEPALIVE - case TCP_KEEPIDLE: - sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_idle)); - break; - case TCP_KEEPINTVL: - sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_intvl)); - break; - case TCP_KEEPCNT: - sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n", - s, sock->conn->pcb.tcp->keep_cnt)); - break; -#endif /* LWIP_TCP_KEEPALIVE */ - - } /* switch (optname) */ - break; -#endif /* LWIP_TCP*/ -#if LWIP_UDP && LWIP_UDPLITE - /* Level: IPPROTO_UDPLITE */ - case IPPROTO_UDPLITE: - switch (optname) { - case UDPLITE_SEND_CSCOV: - if ((*(int*)optval != 0) && (*(int*)optval < 8)) { - /* don't allow illegal values! */ - sock->conn->pcb.udp->chksum_len_tx = 8; - } else { - sock->conn->pcb.udp->chksum_len_tx = *(int*)optval; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n", - s, (*(int*)optval)) ); - break; - case UDPLITE_RECV_CSCOV: - if ((*(int*)optval != 0) && (*(int*)optval < 8)) { - /* don't allow illegal values! */ - sock->conn->pcb.udp->chksum_len_rx = 8; - } else { - sock->conn->pcb.udp->chksum_len_rx = *(int*)optval; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n", - s, (*(int*)optval)) ); - break; - } /* switch (optname) */ - break; -#endif /* LWIP_UDP */ - } /* switch (level) */ - sys_sem_signal(sock->conn->op_completed); -} - -int -lwip_ioctl(int s, long cmd, void *argp) -{ - struct lwip_socket *sock = get_socket(s); - u16_t buflen = 0; - s16_t recv_avail; - - if (!sock) - return -1; - - switch (cmd) { - case FIONREAD: - if (!argp) { - sock_set_errno(sock, EINVAL); - return -1; - } - - SYS_ARCH_GET(sock->conn->recv_avail, recv_avail); - if (recv_avail < 0) - recv_avail = 0; - *((u16_t*)argp) = (u16_t)recv_avail; - - /* Check if there is data left from the last recv operation. /maq 041215 */ - if (sock->lastdata) { - buflen = netbuf_len(sock->lastdata); - buflen -= sock->lastoffset; - - *((u16_t*)argp) += buflen; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp))); - sock_set_errno(sock, 0); - return 0; - - case FIONBIO: - if (argp && *(u32_t*)argp) - sock->flags |= O_NONBLOCK; - else - sock->flags &= ~O_NONBLOCK; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK))); - sock_set_errno(sock, 0); - return 0; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); - sock_set_errno(sock, ENOSYS); /* not yet implemented */ - return -1; - } /* switch (cmd) */ -} - -#endif /* LWIP_SOCKET */ diff --git a/components/net/lwip-1.3.2/src/api/tcpip.c b/components/net/lwip-1.3.2/src/api/tcpip.c deleted file mode 100644 index 002df90b24..0000000000 --- a/components/net/lwip-1.3.2/src/api/tcpip.c +++ /dev/null @@ -1,596 +0,0 @@ -/** - * @file - * Sequential API Main thread module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sys.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/ip_frag.h" -#include "lwip/tcp.h" -#include "lwip/autoip.h" -#include "lwip/dhcp.h" -#include "lwip/igmp.h" -#include "lwip/dns.h" -#include "lwip/tcpip.h" -#include "lwip/init.h" -#include "netif/etharp.h" -#include "netif/ppp_oe.h" - -/* global variables */ -static void (* tcpip_init_done)(void *arg); -static void *tcpip_init_done_arg; -static sys_mbox_t mbox = SYS_MBOX_NULL; - -#if LWIP_TCPIP_CORE_LOCKING -/** The global semaphore to lock the stack. */ -sys_sem_t lock_tcpip_core; -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -#if LWIP_TCP -/* global variable that shows if the tcp timer is currently scheduled or not */ -static int tcpip_tcp_timer_active; - -/** - * Timer callback function that calls tcp_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -tcpip_tcp_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - - /* call TCP timer handler */ - tcp_tmr(); - /* timer still needed? */ - if (tcp_active_pcbs || tcp_tw_pcbs) { - /* restart timer */ - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } else { - /* disable timer */ - tcpip_tcp_timer_active = 0; - } -} - -#if !NO_SYS -/** - * Called from TCP_REG when registering a new PCB: - * the reason is to have the TCP timer only running when - * there are active (or time-wait) PCBs. - */ -void -tcp_timer_needed(void) -{ - /* timer is off but needed again? */ - if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { - /* enable and start timer */ - tcpip_tcp_timer_active = 1; - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } -} -#endif /* !NO_SYS */ -#endif /* LWIP_TCP */ - -#if IP_REASSEMBLY -/** - * Timer callback function that calls ip_reass_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -ip_reass_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n")); - ip_reass_tmr(); - sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL); -} -#endif /* IP_REASSEMBLY */ - -#if LWIP_ARP -/** - * Timer callback function that calls etharp_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -arp_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: etharp_tmr()\n")); - etharp_tmr(); - sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); -} -#endif /* LWIP_ARP */ - -#if LWIP_DHCP -/** - * Timer callback function that calls dhcp_coarse_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -dhcp_timer_coarse(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dhcp_coarse_tmr()\n")); - dhcp_coarse_tmr(); - sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL); -} - -/** - * Timer callback function that calls dhcp_fine_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -dhcp_timer_fine(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dhcp_fine_tmr()\n")); - dhcp_fine_tmr(); - sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL); -} -#endif /* LWIP_DHCP */ - -#if LWIP_AUTOIP -/** - * Timer callback function that calls autoip_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -autoip_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: autoip_tmr()\n")); - autoip_tmr(); - sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL); -} -#endif /* LWIP_AUTOIP */ - -#if LWIP_IGMP -/** - * Timer callback function that calls igmp_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -igmp_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: igmp_tmr()\n")); - igmp_tmr(); - sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL); -} -#endif /* LWIP_IGMP */ - -#if LWIP_DNS -/** - * Timer callback function that calls dns_tmr() and reschedules itself. - * - * @param arg unused argument - */ -static void -dns_timer(void *arg) -{ - LWIP_UNUSED_ARG(arg); - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dns_tmr()\n")); - dns_tmr(); - sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL); -} -#endif /* LWIP_DNS */ - -/** - * The main lwIP thread. This thread has exclusive access to lwIP core functions - * (unless access to them is not locked). Other threads communicate with this - * thread using message boxes. - * - * It also starts all the timers to make sure they are running in the right - * thread context. - * - * @param arg unused argument - */ -static void -tcpip_thread(void *arg) -{ - struct tcpip_msg *msg; - LWIP_UNUSED_ARG(arg); - -#if IP_REASSEMBLY - sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL); -#endif /* IP_REASSEMBLY */ -#if LWIP_ARP - sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); -#endif /* LWIP_ARP */ -#if LWIP_DHCP - sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL); - sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL); -#endif /* LWIP_DHCP */ -#if LWIP_AUTOIP - sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL); -#endif /* LWIP_AUTOIP */ -#if LWIP_IGMP - sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL); -#endif /* LWIP_IGMP */ -#if LWIP_DNS - sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL); -#endif /* LWIP_DNS */ - - if (tcpip_init_done != NULL) { - tcpip_init_done(tcpip_init_done_arg); - } - - LOCK_TCPIP_CORE(); - while (1) { /* MAIN Loop */ - sys_mbox_fetch(mbox, (void *)&msg); - switch (msg->type) { -#if LWIP_NETCONN - case TCPIP_MSG_API: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); - msg->msg.apimsg->function(&(msg->msg.apimsg->msg)); - break; -#endif /* LWIP_NETCONN */ - - case TCPIP_MSG_INPKT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg)); -#if LWIP_ARP - if (msg->msg.inp.netif->flags & NETIF_FLAG_ETHARP) { - ethernet_input(msg->msg.inp.p, msg->msg.inp.netif); - } else -#endif /* LWIP_ARP */ - { ip_input(msg->msg.inp.p, msg->msg.inp.netif); - } - memp_free(MEMP_TCPIP_MSG_INPKT, msg); - break; - -#if LWIP_NETIF_API - case TCPIP_MSG_NETIFAPI: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: Netif API message %p\n", (void *)msg)); - msg->msg.netifapimsg->function(&(msg->msg.netifapimsg->msg)); - break; -#endif /* LWIP_NETIF_API */ - - case TCPIP_MSG_CALLBACK: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); - msg->msg.cb.f(msg->msg.cb.ctx); - memp_free(MEMP_TCPIP_MSG_API, msg); - break; - - case TCPIP_MSG_TIMEOUT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg)); - sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg); - memp_free(MEMP_TCPIP_MSG_API, msg); - break; - case TCPIP_MSG_UNTIMEOUT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg)); - sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg); - memp_free(MEMP_TCPIP_MSG_API, msg); - break; - - default: - break; - } - } -} - -/** - * Pass a received packet to tcpip_thread for input processing - * - * @param p the received packet, p->payload pointing to the Ethernet header or - * to an IP header (if netif doesn't got NETIF_FLAG_ETHARP flag) - * @param inp the network interface on which the packet was received - */ -err_t -tcpip_input(struct pbuf *p, struct netif *inp) -{ - struct tcpip_msg *msg; - - if (mbox != SYS_MBOX_NULL) { - msg = memp_malloc(MEMP_TCPIP_MSG_INPKT); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_INPKT; - msg->msg.inp.p = p; - msg->msg.inp.netif = inp; - if (sys_mbox_trypost(mbox, msg) != ERR_OK) { - memp_free(MEMP_TCPIP_MSG_INPKT, msg); - return ERR_MEM; - } - return ERR_OK; - } - return ERR_VAL; -} - -/** - * Call a specific function in the thread context of - * tcpip_thread for easy access synchronization. - * A function called in that way may access lwIP core code - * without fearing concurrent access. - * - * @param f the function to call - * @param ctx parameter passed to f - * @param block 1 to block until the request is posted, 0 to non-blocking mode - * @return ERR_OK if the function was called, another err_t if not - */ -err_t -tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block) -{ - struct tcpip_msg *msg; - - if (mbox != SYS_MBOX_NULL) { - msg = memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_CALLBACK; - msg->msg.cb.f = f; - msg->msg.cb.ctx = ctx; - if (block) { - sys_mbox_post(mbox, msg); - } else { - if (sys_mbox_trypost(mbox, msg) != ERR_OK) { - memp_free(MEMP_TCPIP_MSG_API, msg); - return ERR_MEM; - } - } - return ERR_OK; - } - return ERR_VAL; -} - -/** - * call sys_timeout in tcpip_thread - * - * @param msec time in miliseconds for timeout - * @param h function to be called on timeout - * @param arg argument to pass to timeout function h - * @return ERR_MEM on memory error, ERR_OK otherwise - */ -err_t -tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg) -{ - struct tcpip_msg *msg; - - if (mbox != SYS_MBOX_NULL) { - msg = memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_TIMEOUT; - msg->msg.tmo.msecs = msecs; - msg->msg.tmo.h = h; - msg->msg.tmo.arg = arg; - sys_mbox_post(mbox, msg); - return ERR_OK; - } - return ERR_VAL; -} - -/** - * call sys_untimeout in tcpip_thread - * - * @param msec time in miliseconds for timeout - * @param h function to be called on timeout - * @param arg argument to pass to timeout function h - * @return ERR_MEM on memory error, ERR_OK otherwise - */ -err_t -tcpip_untimeout(sys_timeout_handler h, void *arg) -{ - struct tcpip_msg *msg; - - if (mbox != SYS_MBOX_NULL) { - msg = memp_malloc(MEMP_TCPIP_MSG_API); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_UNTIMEOUT; - msg->msg.tmo.h = h; - msg->msg.tmo.arg = arg; - sys_mbox_post(mbox, msg); - return ERR_OK; - } - return ERR_VAL; -} - -#if LWIP_NETCONN -/** - * Call the lower part of a netconn_* function - * This function is then running in the thread context - * of tcpip_thread and has exclusive access to lwIP core code. - * - * @param apimsg a struct containing the function to call and its parameters - * @return ERR_OK if the function was called, another err_t if not - */ -err_t -tcpip_apimsg(struct api_msg *apimsg) -{ - struct tcpip_msg msg; - - if (mbox != SYS_MBOX_NULL) { - msg.type = TCPIP_MSG_API; - msg.msg.apimsg = apimsg; - sys_mbox_post(mbox, &msg); - sys_arch_sem_wait(apimsg->msg.conn->op_completed, 0); - return ERR_OK; - } - return ERR_VAL; -} - -#if LWIP_TCPIP_CORE_LOCKING -/** - * Call the lower part of a netconn_* function - * This function has exclusive access to lwIP core code by locking it - * before the function is called. - * - * @param apimsg a struct containing the function to call and its parameters - * @return ERR_OK (only for compatibility fo tcpip_apimsg()) - */ -err_t -tcpip_apimsg_lock(struct api_msg *apimsg) -{ - LOCK_TCPIP_CORE(); - apimsg->function(&(apimsg->msg)); - UNLOCK_TCPIP_CORE(); - return ERR_OK; - -} -#endif /* LWIP_TCPIP_CORE_LOCKING */ -#endif /* LWIP_NETCONN */ - -#if LWIP_NETIF_API -#if !LWIP_TCPIP_CORE_LOCKING -/** - * Much like tcpip_apimsg, but calls the lower part of a netifapi_* - * function. - * - * @param netifapimsg a struct containing the function to call and its parameters - * @return error code given back by the function that was called - */ -err_t -tcpip_netifapi(struct netifapi_msg* netifapimsg) -{ - struct tcpip_msg msg; - - if (mbox != SYS_MBOX_NULL) { - netifapimsg->msg.sem = sys_sem_new(0); - if (netifapimsg->msg.sem == SYS_SEM_NULL) { - netifapimsg->msg.err = ERR_MEM; - return netifapimsg->msg.err; - } - - msg.type = TCPIP_MSG_NETIFAPI; - msg.msg.netifapimsg = netifapimsg; - sys_mbox_post(mbox, &msg); - sys_sem_wait(netifapimsg->msg.sem); - sys_sem_free(netifapimsg->msg.sem); - return netifapimsg->msg.err; - } - return ERR_VAL; -} -#else /* !LWIP_TCPIP_CORE_LOCKING */ -/** - * Call the lower part of a netifapi_* function - * This function has exclusive access to lwIP core code by locking it - * before the function is called. - * - * @param netifapimsg a struct containing the function to call and its parameters - * @return ERR_OK (only for compatibility fo tcpip_netifapi()) - */ -err_t -tcpip_netifapi_lock(struct netifapi_msg* netifapimsg) -{ - LOCK_TCPIP_CORE(); - netifapimsg->function(&(netifapimsg->msg)); - UNLOCK_TCPIP_CORE(); - return netifapimsg->msg.err; -} -#endif /* !LWIP_TCPIP_CORE_LOCKING */ -#endif /* LWIP_NETIF_API */ - -/** - * Initialize this module: - * - initialize all sub modules - * - start the tcpip_thread - * - * @param initfunc a function to call when tcpip_thread is running and finished initializing - * @param arg argument to pass to initfunc - */ -void -tcpip_init(void (* initfunc)(void *), void *arg) -{ - lwip_init(); - - tcpip_init_done = initfunc; - tcpip_init_done_arg = arg; - mbox = sys_mbox_new(TCPIP_MBOX_SIZE); -#if LWIP_TCPIP_CORE_LOCKING - lock_tcpip_core = sys_sem_new(1); -#endif /* LWIP_TCPIP_CORE_LOCKING */ - - sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO); -} - -/** - * Simple callback function used with tcpip_callback to free a pbuf - * (pbuf_free has a wrong signature for tcpip_callback) - * - * @param p The pbuf (chain) to be dereferenced. - */ -static void -pbuf_free_int(void *p) -{ - struct pbuf *q = p; - pbuf_free(q); -} - -/** - * A simple wrapper function that allows you to free a pbuf from interrupt context. - * - * @param p The pbuf (chain) to be dereferenced. - * @return ERR_OK if callback could be enqueued, an err_t if not - */ -err_t -pbuf_free_callback(struct pbuf *p) -{ - return tcpip_callback_with_block(pbuf_free_int, p, 0); -} - -/** - * A simple wrapper function that allows you to free heap memory from - * interrupt context. - * - * @param m the heap memory to free - * @return ERR_OK if callback could be enqueued, an err_t if not - */ -err_t -mem_free_callback(void *m) -{ - return tcpip_callback_with_block(mem_free, m, 0); -} - -#endif /* !NO_SYS */ diff --git a/components/net/lwip-1.3.2/src/arch/include/arch/cpu.h b/components/net/lwip-1.3.2/src/arch/include/arch/cpu.h deleted file mode 100644 index e2c6c60294..0000000000 --- a/components/net/lwip-1.3.2/src/arch/include/arch/cpu.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: cpu.h,v 1.1.1.1 2004/12/16 14:17:14 bear Exp $ - */ -#ifndef __ARCH_CPU_H__ -#define __ARCH_CPU_H__ - -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif /* BYTE_ORDER */ - -#endif /* __ARCH_CPU_H__ */ diff --git a/components/net/lwip-1.3.2/src/arch/include/arch/init.h b/components/net/lwip-1.3.2/src/arch/include/arch/init.h deleted file mode 100644 index 7f1ad49977..0000000000 --- a/components/net/lwip-1.3.2/src/arch/include/arch/init.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: init.h,v 1.1.1.1 2004/12/16 14:17:13 bear Exp $ - */ -#ifndef __ARCH_INIT_H__ -#define __ARCH_INIT_H__ - -#define TCPIP_INIT_DONE(arg) sys_sem_signal(*(sys_sem_t *)arg) - -#endif /* __ARCH_INIT_H__ */ - - - - diff --git a/components/net/lwip-1.3.2/src/arch/include/arch/sys_arch_init.h b/components/net/lwip-1.3.2/src/arch/include/arch/sys_arch_init.h deleted file mode 100644 index 1a49d65c84..0000000000 --- a/components/net/lwip-1.3.2/src/arch/include/arch/sys_arch_init.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __LWIP_SYS_INIT_H__ -#define __LWIP_SYS_INIT_H__ - -void lwip_sys_init(void); -void lwip_system_init(void); - -#endif - diff --git a/components/net/lwip-1.3.2/src/arch/sys_arch.c b/components/net/lwip-1.3.2/src/arch/sys_arch.c deleted file mode 100644 index 894c6fa4e3..0000000000 --- a/components/net/lwip-1.3.2/src/arch/sys_arch.c +++ /dev/null @@ -1,259 +0,0 @@ -#include - -#include "lwip/debug.h" -#include "lwip/sys.h" -#include "lwip/opt.h" -#include "lwip/stats.h" -#include "arch/sys_arch.h" - -#include - -#define LWIP_THREAD_MAGIC 0x1919 -#define LWIP_THREAD_NAME (rt_thread_self()->name) -struct lwip_thread -{ - rt_uint32_t magic; - struct sys_timeouts timeouts; - - rt_thread_t tid; -}; - -void sys_init(void) -{ - /* nothing to do in RT-Thread */ - - return; -} - -sys_sem_t sys_sem_new(u8_t count) -{ - static unsigned short counter = 0; - char tname[RT_NAME_MAX]; - - rt_snprintf(tname, RT_NAME_MAX, "%s%d", SYS_LWIP_SEM_NAME, counter); - - LWIP_DEBUGF(SYS_DEBUG, ("%s, Create sem: %s \n", LWIP_THREAD_NAME, tname)); - - counter++; - - return rt_sem_create(tname, count, RT_IPC_FLAG_FIFO); -} - -void sys_sem_free(sys_sem_t sem) -{ - LWIP_DEBUGF(SYS_DEBUG, ("%s, Delete sem: %s \n", LWIP_THREAD_NAME, - sem->parent.parent.name)); - - rt_sem_delete(sem); - - return; -} - -void sys_sem_signal(sys_sem_t sem) -{ - LWIP_DEBUGF(SYS_DEBUG, ("%s, Release signal: %s , %d\n", LWIP_THREAD_NAME, - sem->parent.parent.name, sem->value)); - - rt_sem_release(sem); - - return; -} - -u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) -{ - rt_err_t ret; - s32_t t; - u32_t tick; - - /* get the begin tick */ - tick = rt_tick_get(); - LWIP_DEBUGF(SYS_DEBUG, ("%s, Wait sem: %s , %d\n", LWIP_THREAD_NAME, - sem->parent.parent.name, sem->value)); - - if(timeout == 0) - t = RT_WAITING_FOREVER; - else - { - /* convirt msecond to os tick */ - if (timeout < (1000/RT_TICK_PER_SECOND)) t = 1; - else t = timeout / (1000/RT_TICK_PER_SECOND); - } - - ret = rt_sem_take(sem, t); - - if (ret == -RT_ETIMEOUT) return SYS_ARCH_TIMEOUT; - else if (ret == RT_EOK) ret = 1; - - /* get elapse msecond */ - tick = rt_tick_get() - tick; - - /* convert tick to msecond */ - tick = tick * (1000/RT_TICK_PER_SECOND); - if (tick == 0) tick = 1; - - return tick; -} - -sys_mbox_t sys_mbox_new(int size) -{ - static unsigned short counter = 0; - char tname[RT_NAME_MAX]; - - rt_snprintf(tname, RT_NAME_MAX, "%s%d", SYS_LWIP_MBOX_NAME, counter); - LWIP_DEBUGF(SYS_DEBUG, ("%s, Create mbox: %s \n", LWIP_THREAD_NAME, tname)); - - counter++; - - return rt_mb_create(tname, size, RT_IPC_FLAG_FIFO); -} - -void sys_mbox_free(sys_mbox_t mbox) -{ - LWIP_DEBUGF(SYS_DEBUG, ("%s, Delete mbox: %s\n", LWIP_THREAD_NAME, - mbox->mb->parent.parent.name)); - - rt_mb_delete(mbox); - - return; -} - -void sys_mbox_post(sys_mbox_t mbox, void *msg) -{ - LWIP_DEBUGF(SYS_DEBUG, ("%s, Post mail: %s ,0x%x\n", LWIP_THREAD_NAME, - mbox->mb->parent.parent.name, (rt_uint32_t)msg)); - - rt_mb_send_wait(mbox, (rt_uint32_t)msg, RT_WAITING_FOREVER); - - return; -} - -err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg) -{ - LWIP_DEBUGF(SYS_DEBUG, ("%s, Try post mail: %s ,0x%x\n", LWIP_THREAD_NAME, - mbox->mb->parent.parent.name, (rt_uint32_t)msg)); - - if (rt_mb_send(mbox, (rt_uint32_t)msg) == RT_EOK) return ERR_OK; - - return ERR_MEM; -} - -u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) -{ - rt_err_t ret; - s32_t t; - u32_t tick; - - /* get the begin tick */ - tick = rt_tick_get(); - - if(timeout == 0) - t = RT_WAITING_FOREVER; - else - { - /* convirt msecond to os tick */ - if (timeout < (1000/RT_TICK_PER_SECOND)) t = 1; - else t = timeout / (1000/RT_TICK_PER_SECOND); - } - - ret = rt_mb_recv(mbox, (rt_uint32_t *)msg, t); - - if(ret == -RT_ETIMEOUT) - return SYS_ARCH_TIMEOUT; - else - { - LWIP_ASSERT("rt_mb_recv returned with error!", ret == RT_EOK); - } - - LWIP_DEBUGF(SYS_DEBUG, ("%s, Fetch mail: %s , 0x%x\n", LWIP_THREAD_NAME, - mbox->mb->parent.parent.name, *(rt_uint32_t **)msg)); - - /* get elapse msecond */ - tick = rt_tick_get() - tick; - - /* convert tick to msecond */ - tick = tick * (1000/RT_TICK_PER_SECOND); - if (tick == 0) tick = 1; - - return tick; -} - -u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) -{ - int ret; - - ret = rt_mb_recv(mbox, (rt_uint32_t *)msg, 0); - - if(ret == -RT_ETIMEOUT) return SYS_ARCH_TIMEOUT; - else if (ret == RT_EOK) ret = 1; - - LWIP_DEBUGF(SYS_DEBUG, ("%s, Fetch mail: %s , 0x%x\n", LWIP_THREAD_NAME, - mbox->mb->parent.parent.name, *(rt_uint32_t **)msg)); - - return ret; -} - -struct sys_timeouts *sys_arch_timeouts(void) -{ - rt_thread_t self = rt_thread_self(); - struct lwip_thread* lwip_th = (struct lwip_thread*)self->user_data; - - if ((lwip_th != RT_NULL) && (lwip_th->magic == LWIP_THREAD_MAGIC)) - return &(lwip_th->timeouts); - - return RT_NULL; -} - -sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio) -{ - rt_thread_t t; - struct lwip_thread* lwip_th; - - /* create lwip thread */ - lwip_th = (struct lwip_thread*) rt_malloc (sizeof(struct lwip_thread)); - RT_ASSERT(lwip_th != RT_NULL); - - /* create thread */ - t = rt_thread_create(name, thread, arg, stacksize, prio, 20); - RT_ASSERT(t != RT_NULL); - t->user_data = (rt_uint32_t)lwip_th; - - /* init lwip_thread */ - lwip_th->magic = LWIP_THREAD_MAGIC; - lwip_th->timeouts.next = RT_NULL; - lwip_th->tid = t; - - /* startup thread */ - rt_thread_startup(t); - - return t; -} - -sys_prot_t sys_arch_protect(void) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* must also lock scheduler */ - rt_enter_critical(); - - return level; -} - -void sys_arch_unprotect(sys_prot_t pval) -{ - /* unlock scheduler */ - rt_exit_critical(); - - /* enable interrupt */ - rt_hw_interrupt_enable(pval); - - return; -} -void sys_arch_assert(const char* file, int line) -{ - rt_kprintf("\nAssertion: %d in %s, thread %s\n", line, file, - rt_thread_self()->name); - RT_ASSERT(0); -} diff --git a/components/net/lwip-1.3.2/src/arch/sys_arch_init.c b/components/net/lwip-1.3.2/src/arch/sys_arch_init.c deleted file mode 100644 index f70de7cc0a..0000000000 --- a/components/net/lwip-1.3.2/src/arch/sys_arch_init.c +++ /dev/null @@ -1,142 +0,0 @@ -#include - -#include "lwip/debug.h" -#include "lwip/mem.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/tcpip.h" -#include "lwip/ip_addr.h" -#include "lwip/dhcp.h" - -#include "netif/ethernetif.h" -#include "netif/etharp.h" - -static err_t netif_device_init(struct netif *netif) -{ - struct eth_device *ethif; - - ethif = (struct eth_device*)netif->state; - if (ethif != RT_NULL) - { - rt_device_t device; - - /* get device object */ - device = (rt_device_t) ethif; - if (rt_device_init(device) != RT_EOK) - { - return ERR_IF; - } - return ERR_OK; - } - - return ERR_IF; -} - -static void tcpip_init_done_callback(void *arg) -{ - rt_device_t device; - struct eth_device *ethif; - struct ip_addr ipaddr, netmask, gw; - struct rt_list_node* node; - struct rt_object* object; - struct rt_object_information *information; - - LWIP_ASSERT("invalid arg.\n",arg); - - IP4_ADDR(&gw, 0,0,0,0); - IP4_ADDR(&ipaddr, 0,0,0,0); - IP4_ADDR(&netmask, 0,0,0,0); - - /* enter critical */ - rt_enter_critical(); - - /* for each network interfaces */ - information = rt_object_get_information(RT_Object_Class_Device); - RT_ASSERT(information != RT_NULL); - - for (node = information->object_list.next; node != &(information->object_list); node = node->next) - { - object = rt_list_entry(node, struct rt_object, list); - device = (rt_device_t) object; - if (device->type == RT_Device_Class_NetIf) - { - ethif = (struct eth_device*)device; - - /* leave critical */ - rt_exit_critical(); - - netif_add(ethif->netif, &ipaddr, &netmask, &gw, - ethif, netif_device_init, tcpip_input); - - if (netif_default == RT_NULL) - netif_set_default(ethif->netif); - -#if LWIP_DHCP - dhcp_start(ethif->netif); -#else - netif_set_up(ethif->netif); -#endif - -#ifdef LWIP_NETIF_LINK_CALLBACK - netif_set_link_up(ethif->netif); -#endif - - /* enter critical */ - rt_enter_critical(); - } - } - - /* leave critical */ - rt_exit_critical(); - - rt_sem_release((rt_sem_t)arg); -} - -/** - * LwIP system initialization - */ -void lwip_system_init(void) -{ - rt_err_t rc; - struct rt_semaphore done_sem; - - rc = rt_sem_init(&done_sem, "done", 0, RT_IPC_FLAG_FIFO); - - if(rc != RT_EOK) - { - LWIP_ASSERT("Failed to create semaphore", 0); - return; - } - - tcpip_init(tcpip_init_done_callback,(void *)&done_sem); - - /* waiting for initialization done */ - if (rt_sem_take(&done_sem, RT_WAITING_FOREVER) != RT_EOK) - { - rt_sem_detach(&done_sem); - return; - } - rt_sem_detach(&done_sem); - - /* set default ip address */ -#if !LWIP_DHCP - { - struct ip_addr ipaddr, netmask, gw; - - ipaddr.addr = inet_addr(RT_LWIP_IPADDR); - gw.addr = inet_addr(RT_LWIP_GWADDR); - netmask.addr = inet_addr(RT_LWIP_MSKADDR); - - netifapi_netif_set_addr(netif_default, &ipaddr, &netmask, &gw); - } -#endif -} - -/** - * Compatible with RT-Thread 0.2.x/0.3.x - */ -void lwip_sys_init(void) -{ - lwip_system_init(); -} - diff --git a/components/net/lwip-1.3.2/src/core/dhcp.c b/components/net/lwip-1.3.2/src/core/dhcp.c deleted file mode 100644 index 82068bfd53..0000000000 --- a/components/net/lwip-1.3.2/src/core/dhcp.c +++ /dev/null @@ -1,1722 +0,0 @@ -/** - * @file - * Dynamic Host Configuration Protocol client - * - */ - -/* - * - * Copyright (c) 2001-2004 Leon Woestenberg - * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. - * - * Author: Leon Woestenberg - * - * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform - * with RFC 2131 and RFC 2132. - * - * TODO: - * - Proper parsing of DHCP messages exploiting file/sname field overloading. - * - Add JavaDoc style documentation (API, internals). - * - Support for interfaces other than Ethernet (SLIP, PPP, ...) - * - * Please coordinate changes and requests with Leon Woestenberg - * - * - * Integration with your code: - * - * In lwip/dhcp.h - * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) - * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) - * - * Then have your application call dhcp_coarse_tmr() and - * dhcp_fine_tmr() on the defined intervals. - * - * dhcp_start(struct netif *netif); - * starts a DHCP client instance which configures the interface by - * obtaining an IP address lease and maintaining it. - * - * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif) - * to remove the DHCP client. - * - */ - -#include "lwip/opt.h" - -#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet.h" -#include "lwip/sys.h" -#include "lwip/dhcp.h" -#include "lwip/autoip.h" -#include "lwip/dns.h" -#include "netif/etharp.h" - -#include - -/** Default for DHCP_GLOBAL_XID is 0xABCD0000 - * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g. - * #define DHCP_GLOBAL_XID_HEADER "stdlib.h" - * #define DHCP_GLOBAL_XID rand() - */ -#ifdef DHCP_GLOBAL_XID_HEADER -#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */ -#endif - -/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU - * MTU is checked to be big enough in dhcp_start */ -#define DHCP_MAX_MSG_LEN(netif) (netif->mtu) -#define DHCP_MAX_MSG_LEN_MIN_REQUIRED 576 -/** Minimum length for reply before packet is parsed */ -#define DHCP_MIN_REPLY_LEN 44 - -#define REBOOT_TRIES 2 - -/* DHCP client state machine functions */ -static void dhcp_handle_ack(struct netif *netif); -static void dhcp_handle_nak(struct netif *netif); -static void dhcp_handle_offer(struct netif *netif); - -static err_t dhcp_discover(struct netif *netif); -static err_t dhcp_select(struct netif *netif); -static void dhcp_bind(struct netif *netif); -#if DHCP_DOES_ARP_CHECK -static void dhcp_check(struct netif *netif); -static err_t dhcp_decline(struct netif *netif); -#endif /* DHCP_DOES_ARP_CHECK */ -static err_t dhcp_rebind(struct netif *netif); -static err_t dhcp_reboot(struct netif *netif); -static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); - -/* receive, unfold, parse and free incoming messages */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); -static err_t dhcp_unfold_reply(struct dhcp *dhcp, struct pbuf *p); -static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type); -static u8_t dhcp_get_option_byte(u8_t *ptr); -#if 0 -static u16_t dhcp_get_option_short(u8_t *ptr); -#endif -static u32_t dhcp_get_option_long(u8_t *ptr); -static void dhcp_free_reply(struct dhcp *dhcp); - -/* set the DHCP timers */ -static void dhcp_timeout(struct netif *netif); -static void dhcp_t1_timeout(struct netif *netif); -static void dhcp_t2_timeout(struct netif *netif); - -/* build outgoing messages */ -/* create a DHCP request, fill in common headers */ -static err_t dhcp_create_request(struct netif *netif); -/* free a DHCP request */ -static void dhcp_delete_request(struct netif *netif); -/* add a DHCP option (type, then length in bytes) */ -static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); -/* add option values */ -static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); -static void dhcp_option_short(struct dhcp *dhcp, u16_t value); -static void dhcp_option_long(struct dhcp *dhcp, u32_t value); -/* always add the DHCP options trailer to end and pad */ -static void dhcp_option_trailer(struct dhcp *dhcp); - -/** - * Back-off the DHCP client (because of a received NAK response). - * - * Back-off the DHCP client because of a received NAK. Receiving a - * NAK means the client asked for something non-sensible, for - * example when it tries to renew a lease obtained on another network. - * - * We clear any existing set IP address and restart DHCP negotiation - * afresh (as per RFC2131 3.2.3). - * - * @param netif the netif under DHCP control - */ -static void -dhcp_handle_nak(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - /* Set the interface down since the address must no longer be used, as per RFC2131 */ - netif_set_down(netif); - /* remove IP address from interface */ - netif_set_ipaddr(netif, IP_ADDR_ANY); - netif_set_gw(netif, IP_ADDR_ANY); - netif_set_netmask(netif, IP_ADDR_ANY); - /* Change to a defined state */ - dhcp_set_state(dhcp, DHCP_BACKING_OFF); - /* We can immediately restart discovery */ - dhcp_discover(netif); -} - -#if DHCP_DOES_ARP_CHECK -/** - * Checks if the offered IP address is already in use. - * - * It does so by sending an ARP request for the offered address and - * entering CHECKING state. If no ARP reply is received within a small - * interval, the address is assumed to be free for use by us. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_check(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], - (s16_t)netif->name[1])); - dhcp_set_state(dhcp, DHCP_CHECKING); - /* create an ARP query for the offered IP address, expecting that no host - responds, as the IP address should not be in use. */ - result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); - if (result != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n")); - } - dhcp->tries++; - msecs = 500; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); -} -#endif /* DHCP_DOES_ARP_CHECK */ - -/** - * Remember the configuration offered by a DHCP server. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_handle_offer(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - /* obtain the server address */ - u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - if (option_ptr != NULL) { - dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr)); - /* remember offered address */ - ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); - - dhcp_select(netif); - } -} - -/** - * Select a DHCP server offer out of all offers. - * - * Simply select the first offer received. - * - * @param netif the netif under DHCP control - * @return lwIP specific error (see error.h) - */ -static err_t -dhcp_select(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; -#if LWIP_NETIF_HOSTNAME - const char *p; -#endif /* LWIP_NETIF_HOSTNAME */ - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - dhcp_set_state(dhcp, DHCP_REQUESTING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - /* MUST request the offered IP address */ - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); - dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); - dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); - dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); - dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); - -#if LWIP_NETIF_HOSTNAME - p = (const char*)netif->hostname; - if (p != NULL) { - dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p)); - while (*p) { - dhcp_option_byte(dhcp, *p++); - } - } -#endif /* LWIP_NETIF_HOSTNAME */ - - dhcp_option_trailer(dhcp); - /* shrink the pbuf to the actual content length */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* send broadcast to any DHCP server */ - udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * The DHCP timer that checks for lease renewal/rebind timeouts. - * - */ -void -dhcp_coarse_tmr() -{ - struct netif *netif = netif_list; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n")); - /* iterate through all network interfaces */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - if (netif->dhcp != NULL) { - /* timer is active (non zero), and triggers (zeroes) now? */ - if (netif->dhcp->t2_timeout-- == 1) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); - /* this clients' rebind timeout triggered */ - dhcp_t2_timeout(netif); - /* timer is active (non zero), and triggers (zeroes) now */ - } else if (netif->dhcp->t1_timeout-- == 1) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); - /* this clients' renewal timeout triggered */ - dhcp_t1_timeout(netif); - } - } - /* proceed to next netif */ - netif = netif->next; - } -} - -/** - * DHCP transaction timeout handling - * - * A DHCP server is expected to respond within a short period of time. - * This timer checks whether an outstanding DHCP request is timed out. - * - */ -void -dhcp_fine_tmr() -{ - struct netif *netif = netif_list; - /* loop through netif's */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - if (netif->dhcp != NULL) { - /* timer is active (non zero), and is about to trigger now */ - if (netif->dhcp->request_timeout > 1) { - netif->dhcp->request_timeout--; - } - else if (netif->dhcp->request_timeout == 1) { - netif->dhcp->request_timeout--; - /* { netif->dhcp->request_timeout == 0 } */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); - /* this clients' request timeout triggered */ - dhcp_timeout(netif); - } - } - /* proceed to next network interface */ - netif = netif->next; - } -} - -/** - * A DHCP negotiation transaction, or ARP request, has timed out. - * - * The timer that was started with the DHCP or ARP request has - * timed out, indicating no response was received in time. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n")); - /* back-off period has passed, or server selection timed out */ - if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); - dhcp_discover(netif); - /* receiving the requested lease timed out */ - } else if (dhcp->state == DHCP_REQUESTING) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); - if (dhcp->tries <= 5) { - dhcp_select(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); - dhcp_release(netif); - dhcp_discover(netif); - } -#if DHCP_DOES_ARP_CHECK - /* received no ARP reply for the offered address (which is good) */ - } else if (dhcp->state == DHCP_CHECKING) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); - if (dhcp->tries <= 1) { - dhcp_check(netif); - /* no ARP replies on the offered address, - looks like the IP address is indeed free */ - } else { - /* bind the interface to the offered address */ - dhcp_bind(netif); - } -#endif /* DHCP_DOES_ARP_CHECK */ - } - /* did not get response to renew request? */ - else if (dhcp->state == DHCP_RENEWING) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n")); - /* just retry renewal */ - /* note that the rebind timer will eventually time-out if renew does not work */ - dhcp_renew(netif); - /* did not get response to rebind request? */ - } else if (dhcp->state == DHCP_REBINDING) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n")); - if (dhcp->tries <= 8) { - dhcp_rebind(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n")); - dhcp_release(netif); - dhcp_discover(netif); - } - } else if (dhcp->state == DHCP_REBOOTING) { - if (dhcp->tries < REBOOT_TRIES) { - dhcp_reboot(netif); - } else { - dhcp_discover(netif); - } - } -} - -/** - * The renewal period has timed out. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_t1_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n")); - if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { - /* just retry to renew - note that the rebind timer (t2) will - * eventually time-out if renew tries fail. */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t1_timeout(): must renew\n")); - dhcp_renew(netif); - } -} - -/** - * The rebind period has timed out. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_t2_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n")); - if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { - /* just retry to rebind */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout(): must rebind\n")); - dhcp_rebind(netif); - } -} - -/** - * Handle a DHCP ACK packet - * - * @param netif the netif under DHCP control - */ -static void -dhcp_handle_ack(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - u8_t *option_ptr; - /* clear options we might not get from the ACK */ - dhcp->offered_sn_mask.addr = 0; - dhcp->offered_gw_addr.addr = 0; - dhcp->offered_bc_addr.addr = 0; - - /* lease time given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME); - if (option_ptr != NULL) { - /* remember offered lease time */ - dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2); - } - /* renewal period given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1); - if (option_ptr != NULL) { - /* remember given renewal period */ - dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2); - } else { - /* calculate safe periods for renewal */ - dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; - } - - /* renewal period given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2); - if (option_ptr != NULL) { - /* remember given rebind period */ - dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2); - } else { - /* calculate safe periods for rebinding */ - dhcp->offered_t2_rebind = dhcp->offered_t0_lease; - } - - /* (y)our internet address */ - ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr); - -/** - * Patch #1308 - * TODO: we must check if the file field is not overloaded by DHCP options! - */ -#if 0 - /* boot server address */ - ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr); - /* boot file name */ - if (dhcp->msg_in->file[0]) { - dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1); - strcpy(dhcp->boot_file_name, dhcp->msg_in->file); - } -#endif - - /* subnet mask */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK); - /* subnet mask given? */ - if (option_ptr != NULL) { - dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* gateway router */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER); - if (option_ptr != NULL) { - dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* broadcast address */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST); - if (option_ptr != NULL) { - dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* DNS servers */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER); - if (option_ptr != NULL) { - u8_t n; - dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]) / (u32_t)sizeof(struct ip_addr); - /* limit to at most DHCP_MAX_DNS DNS servers */ - if (dhcp->dns_count > DHCP_MAX_DNS) - dhcp->dns_count = DHCP_MAX_DNS; - for (n = 0; n < dhcp->dns_count; n++) { - dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2 + n * 4])); -#if LWIP_DNS - dns_setserver( n, (struct ip_addr *)(&(dhcp->offered_dns_addr[n].addr))); -#endif /* LWIP_DNS */ - } -#if LWIP_DNS - dns_setserver( n, (struct ip_addr *)(&ip_addr_any)); -#endif /* LWIP_DNS */ - } -} - -/** - * Start DHCP negotiation for a network interface. - * - * If no DHCP client instance was attached to this interface, - * a new client is created first. If a DHCP client instance - * was already present, it restarts negotiation. - * - * @param netif The lwIP network interface - * @return lwIP error code - * - ERR_OK - No error - * - ERR_MEM - Out of memory - */ -err_t -dhcp_start(struct netif *netif) -{ - struct dhcp *dhcp; - err_t result = ERR_OK; - - LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;); - dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - /* Remove the flag that says this netif is handled by DHCP, - it is set when we succeeded starting. */ - netif->flags &= ~NETIF_FLAG_DHCP; - - /* check MTU of the netif */ - if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n")); - return ERR_MEM; - } - - /* no DHCP client attached yet? */ - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); - dhcp = mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); - return ERR_MEM; - } - /* store this dhcp client in the netif */ - netif->dhcp = dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp")); - /* already has DHCP client attached */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n")); - if (dhcp->pcb != NULL) { - udp_remove(dhcp->pcb); - } - LWIP_ASSERT("pbuf p_out wasn't freed", dhcp->p_out == NULL); - LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL && - dhcp->options_in == NULL && dhcp->options_in_len == 0); - } - - /* clear data structure */ - memset(dhcp, 0, sizeof(struct dhcp)); - /* allocate UDP PCB */ - dhcp->pcb = udp_new(); - if (dhcp->pcb == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); - mem_free((void *)dhcp); - netif->dhcp = dhcp = NULL; - return ERR_MEM; - } -#if IP_SOF_BROADCAST - dhcp->pcb->so_options|=SOF_BROADCAST; -#endif /* IP_SOF_BROADCAST */ - /* set up local and remote port for the pcb */ - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - /* set up the recv callback and argument */ - udp_recv(dhcp->pcb, dhcp_recv, netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); - /* (re)start the DHCP negotiation */ - result = dhcp_discover(netif); - if (result != ERR_OK) { - /* free resources allocated above */ - dhcp_stop(netif); - return ERR_MEM; - } - /* Set the flag that says this netif is handled by DHCP. */ - netif->flags |= NETIF_FLAG_DHCP; - return result; -} - -/** - * Inform a DHCP server of our manual configuration. - * - * This informs DHCP servers of our fixed IP address configuration - * by sending an INFORM message. It does not involve DHCP address - * configuration, it is just here to be nice to the network. - * - * @param netif The lwIP network interface - */ -void -dhcp_inform(struct netif *netif) -{ - struct dhcp *dhcp, *old_dhcp; - err_t result = ERR_OK; - dhcp = mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not allocate dhcp\n")); - return; - } - memset(dhcp, 0, sizeof(struct dhcp)); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): allocated dhcp\n")); - dhcp->pcb = udp_new(); - if (dhcp->pcb == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not obtain pcb")); - goto free_dhcp_and_return; - } - old_dhcp = netif->dhcp; - netif->dhcp = dhcp; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): created new udp pcb\n")); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_INFORM); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - -#if IP_SOF_BROADCAST - dhcp->pcb->so_options|=SOF_BROADCAST; -#endif /* IP_SOF_BROADCAST */ - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n")); - udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n")); - } - - udp_remove(dhcp->pcb); - dhcp->pcb = NULL; - netif->dhcp = old_dhcp; -free_dhcp_and_return: - mem_free((void *)dhcp); -} - -/** Handle a possible change in the network configuration. - * - * This enters the REBOOTING state to verify that the currently bound - * address is still valid. - */ -void -dhcp_network_changed(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - if (!dhcp) - return; - switch (dhcp->state) { - case DHCP_REBINDING: - case DHCP_RENEWING: - case DHCP_BOUND: - case DHCP_REBOOTING: - netif_set_down(netif); - dhcp->tries = 0; - dhcp_reboot(netif); - break; - case DHCP_OFF: - /* stay off */ - break; - default: - dhcp->tries = 0; - dhcp_discover(netif); - break; - } -} - -#if DHCP_DOES_ARP_CHECK -/** - * Match an ARP reply with the offered IP address. - * - * @param netif the network interface on which the reply was received - * @param addr The IP address we received a reply from - */ -void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr) -{ - LWIP_ERROR("netif != NULL", (netif != NULL), return;); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n")); - /* is a DHCP client doing an ARP check? */ - if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr)); - /* did a host respond with the address we - were offered by the DHCP server? */ - if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { - /* we will not accept the offered address */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, - ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); - dhcp_decline(netif); - } - } -} - -/** - * Decline an offered lease. - * - * Tell the DHCP server we do not accept the offered address. - * One reason to decline the lease is when we find out the address - * is already in use by another host (through ARP). - * - * @param netif the netif under DHCP control - */ -static err_t -dhcp_decline(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n")); - dhcp_set_state(dhcp, DHCP_BACKING_OFF); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_DECLINE); - - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option_trailer(dhcp); - /* resize pbuf to reflect true size of options */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* per section 4.4.4, broadcast DECLINE messages */ - udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_decline: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = 10*1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} -#endif - - -/** - * Start the DHCP process, discover a DHCP server. - * - * @param netif the netif under DHCP control - */ -static err_t -dhcp_discover(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n")); - ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY); - dhcp_set_state(dhcp, DHCP_SELECTING); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n")); - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_DISCOVER); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); - dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); - dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); - dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); - dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); - - dhcp_option_trailer(dhcp); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n")); - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); - udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n")); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n")); - } - dhcp->tries++; -#if LWIP_DHCP_AUTOIP_COOP - if(dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) { - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON; - autoip_start(netif); - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - - -/** - * Bind the interface to the offered IP address. - * - * @param netif network interface to bind to the offered address - */ -static void -dhcp_bind(struct netif *netif) -{ - u32_t timeout; - struct dhcp *dhcp; - struct ip_addr sn_mask, gw_addr; - LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;); - dhcp = netif->dhcp; - LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* temporary DHCP lease? */ - if (dhcp->offered_t1_renew != 0xffffffffUL) { - /* set renewal period timer */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); - timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if(timeout > 0xffff) { - timeout = 0xffff; - } - dhcp->t1_timeout = (u16_t)timeout; - if (dhcp->t1_timeout == 0) { - dhcp->t1_timeout = 1; - } - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); - } - /* set renewal period timer */ - if (dhcp->offered_t2_rebind != 0xffffffffUL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); - timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if(timeout > 0xffff) { - timeout = 0xffff; - } - dhcp->t2_timeout = (u16_t)timeout; - if (dhcp->t2_timeout == 0) { - dhcp->t2_timeout = 1; - } - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); - } - /* copy offered network mask */ - ip_addr_set(&sn_mask, &dhcp->offered_sn_mask); - - /* subnet mask not given? */ - /* TODO: this is not a valid check. what if the network mask is 0? */ - if (sn_mask.addr == 0) { - /* choose a safe subnet mask given the network class */ - u8_t first_octet = ip4_addr1(&sn_mask); - if (first_octet <= 127) { - sn_mask.addr = htonl(0xff000000); - } else if (first_octet >= 192) { - sn_mask.addr = htonl(0xffffff00); - } else { - sn_mask.addr = htonl(0xffff0000); - } - } - - ip_addr_set(&gw_addr, &dhcp->offered_gw_addr); - /* gateway address not given? */ - if (gw_addr.addr == 0) { - /* copy network address */ - gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr); - /* use first host address on network as gateway */ - gw_addr.addr |= htonl(0x00000001); - } - -#if LWIP_DHCP_AUTOIP_COOP - if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { - autoip_stop(netif); - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); - netif_set_ipaddr(netif, &dhcp->offered_ip_addr); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr)); - netif_set_netmask(netif, &sn_mask); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr)); - netif_set_gw(netif, &gw_addr); - /* bring the interface up */ - netif_set_up(netif); - /* netif is now bound to DHCP leased address */ - dhcp_set_state(dhcp, DHCP_BOUND); -} - -/** - * Renew an existing DHCP lease at the involved DHCP server. - * - * @param netif network interface which must renew its lease - */ -err_t -dhcp_renew(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; -#if LWIP_NETIF_HOSTNAME - const char *p; -#endif /* LWIP_NETIF_HOSTNAME */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n")); - dhcp_set_state(dhcp, DHCP_RENEWING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - -#if LWIP_NETIF_HOSTNAME - p = (const char*)netif->hostname; - if (p != NULL) { - dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p)); - while (*p) { - dhcp_option_byte(dhcp, *p++); - } - } -#endif /* LWIP_NETIF_HOSTNAME */ - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); -#endif - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); -#endif - /* append DHCP message trailer */ - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n")); - } - dhcp->tries++; - /* back-off on retries, but to a maximum of 20 seconds */ - msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Rebind with a DHCP server for an existing DHCP lease. - * - * @param netif network interface which must rebind with a DHCP server - */ -static err_t -dhcp_rebind(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; -#if LWIP_NETIF_HOSTNAME - const char *p; -#endif /* LWIP_NETIF_HOSTNAME */ - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n")); - dhcp_set_state(dhcp, DHCP_REBINDING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); - -#if LWIP_NETIF_HOSTNAME - p = (const char*)netif->hostname; - if (p != NULL) { - dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p)); - while (*p) { - dhcp_option_byte(dhcp, *p++); - } - } -#endif /* LWIP_NETIF_HOSTNAME */ - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); -#endif - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* broadcast to server */ - udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Enter REBOOTING state to verify an existing lease - * - * @param netif network interface which must reboot - */ -static err_t -dhcp_reboot(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n")); - dhcp_set_state(dhcp, DHCP_REBOOTING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* broadcast to server */ - udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - - -/** - * Release a DHCP lease. - * - * @param netif network interface which must release its lease - */ -err_t -dhcp_release(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release()\n")); - - /* idle DHCP client */ - dhcp_set_state(dhcp, DHCP_OFF); - /* clean old DHCP offer */ - dhcp->server_ip_addr.addr = 0; - dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0; - dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0; - dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; - dhcp->dns_count = 0; - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_RELEASE); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); - /* bring the interface down */ - netif_set_down(netif); - /* remove IP address from interface */ - netif_set_ipaddr(netif, IP_ADDR_ANY); - netif_set_gw(netif, IP_ADDR_ANY); - netif_set_netmask(netif, IP_ADDR_ANY); - - /* TODO: netif_down(netif); */ - return result; -} - -/** - * Remove the DHCP client from the interface. - * - * @param netif The network interface to stop DHCP on - */ -void -dhcp_stop(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;); - /* Remove the flag that says this netif is handled by DHCP. */ - netif->flags &= ~NETIF_FLAG_DHCP; - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_stop()\n")); - /* netif is DHCP configured? */ - if (dhcp != NULL) { -#if LWIP_DHCP_AUTOIP_COOP - if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { - autoip_stop(netif); - dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; - } -#endif /* LWIP_DHCP_AUTOIP_COOP */ - - if (dhcp->pcb != NULL) { - udp_remove(dhcp->pcb); - dhcp->pcb = NULL; - } - LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL && - dhcp->options_in == NULL && dhcp->options_in_len == 0); - mem_free((void *)dhcp); - netif->dhcp = NULL; - } -} - -/* - * Set the DHCP state of a DHCP client. - * - * If the state changed, reset the number of tries. - * - * TODO: we might also want to reset the timeout here? - */ -static void -dhcp_set_state(struct dhcp *dhcp, u8_t new_state) -{ - if (new_state != dhcp->state) { - dhcp->state = new_state; - dhcp->tries = 0; - } -} - -/* - * Concatenate an option type and length field to the outgoing - * DHCP message. - * - */ -static void -dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) -{ - LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = option_type; - dhcp->msg_out->options[dhcp->options_out_len++] = option_len; -} -/* - * Concatenate a single byte to the outgoing DHCP message. - * - */ -static void -dhcp_option_byte(struct dhcp *dhcp, u8_t value) -{ - LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = value; -} - -static void -dhcp_option_short(struct dhcp *dhcp, u16_t value) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU); -} - -static void -dhcp_option_long(struct dhcp *dhcp, u32_t value) -{ - LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8); - dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL)); -} - -/** - * Extract the DHCP message and the DHCP options. - * - * Extract the DHCP message and the DHCP options, each into a contiguous - * piece of memory. As a DHCP message is variable sized by its options, - * and also allows overriding some fields for options, the easy approach - * is to first unfold the options into a conitguous piece of memory, and - * use that further on. - * - */ -static err_t -dhcp_unfold_reply(struct dhcp *dhcp, struct pbuf *p) -{ - u16_t ret; - LWIP_ERROR("dhcp != NULL", (dhcp != NULL), return ERR_ARG;); - /* free any left-overs from previous unfolds */ - dhcp_free_reply(dhcp); - /* options present? */ - if (p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) { - dhcp->options_in_len = p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - dhcp->options_in = mem_malloc(dhcp->options_in_len); - if (dhcp->options_in == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_unfold_reply(): could not allocate dhcp->options\n")); - dhcp->options_in_len = 0; - return ERR_MEM; - } - } - dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - if (dhcp->msg_in == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n")); - if (dhcp->options_in != NULL) { - mem_free(dhcp->options_in); - dhcp->options_in = NULL; - dhcp->options_in_len = 0; - } - return ERR_MEM; - } - - /** copy the DHCP message without options */ - ret = pbuf_copy_partial(p, dhcp->msg_in, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN, 0); - LWIP_ASSERT("ret == sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN", ret == sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", - sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)); - - if (dhcp->options_in != NULL) { - /** copy the DHCP options */ - ret = pbuf_copy_partial(p, dhcp->options_in, dhcp->options_in_len, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - LWIP_ASSERT("ret == dhcp->options_in_len", ret == dhcp->options_in_len); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", - dhcp->options_in_len)); - } - LWIP_UNUSED_ARG(ret); - return ERR_OK; -} - -/** - * Free the incoming DHCP message including contiguous copy of - * its DHCP options. - */ -static void dhcp_free_reply(struct dhcp *dhcp) -{ - if (dhcp->msg_in != NULL) { - mem_free((void *)dhcp->msg_in); - dhcp->msg_in = NULL; - } - if (dhcp->options_in) { - mem_free(dhcp->options_in); - dhcp->options_in = NULL; - dhcp->options_in_len = 0; - } - LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n")); -} - -/** - * If an incoming DHCP message is in response to us, then trigger the state machine - */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) -{ - struct netif *netif = (struct netif *)arg; - struct dhcp *dhcp = netif->dhcp; - struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; - u8_t *options_ptr; - u8_t msg_type; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, - (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff), - (u16_t)(ntohl(addr->addr) >> 8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port)); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); - /* prevent warnings about unused arguments */ - LWIP_UNUSED_ARG(pcb); - LWIP_UNUSED_ARG(addr); - LWIP_UNUSED_ARG(port); - - LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL && - dhcp->options_in == NULL && dhcp->options_in_len == 0); - - if (p->len < DHCP_MIN_REPLY_LEN) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message too short\n")); - goto free_pbuf_and_return; - } - - if (reply_msg->op != DHCP_BOOTREPLY) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); - goto free_pbuf_and_return; - } - /* iterate through hardware address and match against DHCP message */ - for (i = 0; i < netif->hwaddr_len; i++) { - if (netif->hwaddr[i] != reply_msg->chaddr[i]) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", - (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); - goto free_pbuf_and_return; - } - } - /* match transaction ID against what we expected */ - if (ntohl(reply_msg->xid) != dhcp->xid) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid)); - goto free_pbuf_and_return; - } - /* option fields could be unfold? */ - if (dhcp_unfold_reply(dhcp, p) != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("problem unfolding DHCP message - too short on memory?\n")); - goto free_pbuf_and_return; - } - - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); - /* obtain pointer to DHCP message type */ - options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE); - if (options_ptr == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); - goto free_pbuf_and_return; - } - - /* read DHCP message type */ - msg_type = dhcp_get_option_byte(options_ptr + 2); - /* message type is DHCP ACK? */ - if (msg_type == DHCP_ACK) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n")); - /* in requesting state? */ - if (dhcp->state == DHCP_REQUESTING) { - dhcp_handle_ack(netif); - dhcp->request_timeout = 0; -#if DHCP_DOES_ARP_CHECK - /* check if the acknowledged lease address is already in use */ - dhcp_check(netif); -#else - /* bind interface to the acknowledged lease address */ - dhcp_bind(netif); -#endif - } - /* already bound to the given lease address? */ - else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) { - dhcp->request_timeout = 0; - dhcp_bind(netif); - } - } - /* received a DHCP_NAK in appropriate state? */ - else if ((msg_type == DHCP_NAK) && - ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) || - (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n")); - dhcp->request_timeout = 0; - dhcp_handle_nak(netif); - } - /* received a DHCP_OFFER in DHCP_SELECTING state? */ - else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_SELECTING state\n")); - dhcp->request_timeout = 0; - /* remember offered lease */ - dhcp_handle_offer(netif); - } -free_pbuf_and_return: - dhcp_free_reply(dhcp); - pbuf_free(p); -} - -/** - * Create a DHCP request, fill in common headers - * - * @param netif the netif under DHCP control - */ -static err_t -dhcp_create_request(struct netif *netif) -{ - struct dhcp *dhcp; - u16_t i; -#ifndef DHCP_GLOBAL_XID - /** default global transaction identifier starting value (easy to match - * with a packet analyser). We simply increment for each new request. - * Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one - * at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */ - static u32_t xid = 0xABCD0000; -#else - static u32_t xid; - static u8_t xid_initialised = 0; - if (!xid_initialised) { - xid = DHCP_GLOBAL_XID; - xid_initialised = !xid_initialised; - } -#endif - LWIP_ERROR("dhcp_create_request: netif != NULL", (netif != NULL), return ERR_ARG;); - dhcp = netif->dhcp; - LWIP_ERROR("dhcp_create_request: dhcp != NULL", (dhcp != NULL), return ERR_VAL;); - LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL); - LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL); - dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); - if (dhcp->p_out == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("dhcp_create_request(): could not allocate pbuf\n")); - return ERR_MEM; - } - LWIP_ASSERT("dhcp_create_request: check that first pbuf can hold struct dhcp_msg", - (dhcp->p_out->len >= sizeof(struct dhcp_msg))); - - /* reuse transaction identifier in retransmissions */ - if (dhcp->tries==0) - xid++; - dhcp->xid = xid; - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, - ("transaction id xid(%"X32_F")\n", xid)); - - dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; - - dhcp->msg_out->op = DHCP_BOOTREQUEST; - /* TODO: make link layer independent */ - dhcp->msg_out->htype = DHCP_HTYPE_ETH; - /* TODO: make link layer independent */ - dhcp->msg_out->hlen = DHCP_HLEN_ETH; - dhcp->msg_out->hops = 0; - dhcp->msg_out->xid = htonl(dhcp->xid); - dhcp->msg_out->secs = 0; - dhcp->msg_out->flags = 0; - dhcp->msg_out->ciaddr.addr = 0; - if (dhcp->state==DHCP_BOUND || dhcp->state==DHCP_RENEWING || dhcp->state==DHCP_REBINDING) { - dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr; - } - dhcp->msg_out->yiaddr.addr = 0; - dhcp->msg_out->siaddr.addr = 0; - dhcp->msg_out->giaddr.addr = 0; - for (i = 0; i < DHCP_CHADDR_LEN; i++) { - /* copy netif hardware address, pad with zeroes */ - dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/; - } - for (i = 0; i < DHCP_SNAME_LEN; i++) { - dhcp->msg_out->sname[i] = 0; - } - for (i = 0; i < DHCP_FILE_LEN; i++) { - dhcp->msg_out->file[i] = 0; - } - dhcp->msg_out->cookie = htonl(0x63825363UL); - dhcp->options_out_len = 0; - /* fill options field with an incrementing array (for debugging purposes) */ - for (i = 0; i < DHCP_OPTIONS_LEN; i++) { - dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */ - } - return ERR_OK; -} - -/** - * Free previously allocated memory used to send a DHCP request. - * - * @param netif the netif under DHCP control - */ -static void -dhcp_delete_request(struct netif *netif) -{ - struct dhcp *dhcp; - LWIP_ERROR("dhcp_delete_request: netif != NULL", (netif != NULL), return;); - dhcp = netif->dhcp; - LWIP_ERROR("dhcp_delete_request: dhcp != NULL", (dhcp != NULL), return;); - LWIP_ASSERT("dhcp_delete_request: dhcp->p_out != NULL", dhcp->p_out != NULL); - LWIP_ASSERT("dhcp_delete_request: dhcp->msg_out != NULL", dhcp->msg_out != NULL); - if (dhcp->p_out != NULL) { - pbuf_free(dhcp->p_out); - } - dhcp->p_out = NULL; - dhcp->msg_out = NULL; -} - -/** - * Add a DHCP message trailer - * - * Adds the END option to the DHCP message, and if - * necessary, up to three padding bytes. - * - * @param dhcp DHCP state structure - */ -static void -dhcp_option_trailer(struct dhcp *dhcp) -{ - LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;); - LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; - /* packet is too small, or not 4 byte aligned? */ - while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { - /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - /* add a fill/padding byte */ - dhcp->msg_out->options[dhcp->options_out_len++] = 0; - } -} - -/** - * Find the offset of a DHCP option inside the DHCP message. - * - * @param dhcp DHCP client - * @param option_type - * - * @return a byte offset into the UDP message where the option was found, or - * zero if the given option was not found. - */ -static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type) -{ - u8_t overload = DHCP_OVERLOAD_NONE; - - /* options available? */ - if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) { - /* start with options field */ - u8_t *options = (u8_t *)dhcp->options_in; - u16_t offset = 0; - /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ - while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) { - /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ - /* are the sname and/or file field overloaded with options? */ - if (options[offset] == DHCP_OPTION_OVERLOAD) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded message detected\n")); - /* skip option type and length */ - offset += 2; - overload = options[offset++]; - } - /* requested option found */ - else if (options[offset] == option_type) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset)); - return &options[offset]; - /* skip option */ - } else { - LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset])); - /* skip option type */ - offset++; - /* skip option length, and then length bytes */ - offset += 1 + options[offset]; - } - } - /* is this an overloaded message? */ - if (overload != DHCP_OVERLOAD_NONE) { - u16_t field_len; - if (overload == DHCP_OVERLOAD_FILE) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n")); - options = (u8_t *)&dhcp->msg_in->file; - field_len = DHCP_FILE_LEN; - } else if (overload == DHCP_OVERLOAD_SNAME) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n")); - options = (u8_t *)&dhcp->msg_in->sname; - field_len = DHCP_SNAME_LEN; - /* TODO: check if else if () is necessary */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n")); - options = (u8_t *)&dhcp->msg_in->sname; - field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN; - } - offset = 0; - - /* at least 1 byte to read and no end marker */ - while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) { - if (options[offset] == option_type) { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("option found at offset=%"U16_F"\n", offset)); - return &options[offset]; - /* skip option */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("skipping option %"U16_F"\n", options[offset])); - /* skip option type */ - offset++; - offset += 1 + options[offset]; - } - } - } - } - return NULL; -} - -/** - * Return the byte of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u8_t -dhcp_get_option_byte(u8_t *ptr) -{ - LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr))); - return *ptr; -} - -#if 0 /* currently unused */ -/** - * Return the 16-bit value of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u16_t -dhcp_get_option_short(u8_t *ptr) -{ - u16_t value; - value = *ptr++ << 8; - value |= *ptr; - LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value)); - return value; -} -#endif - -/** - * Return the 32-bit value of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u32_t dhcp_get_option_long(u8_t *ptr) -{ - u32_t value; - value = (u32_t)(*ptr++) << 24; - value |= (u32_t)(*ptr++) << 16; - value |= (u32_t)(*ptr++) << 8; - value |= (u32_t)(*ptr++); - LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value)); - return value; -} - -#endif /* LWIP_DHCP */ diff --git a/components/net/lwip-1.3.2/src/core/dns.c b/components/net/lwip-1.3.2/src/core/dns.c deleted file mode 100644 index b955538c94..0000000000 --- a/components/net/lwip-1.3.2/src/core/dns.c +++ /dev/null @@ -1,980 +0,0 @@ -/** - * @file - * DNS - host name to IP address resolver. - * - */ - -/** - - * This file implements a DNS host name to IP address resolver. - - * Port to lwIP from uIP - * by Jim Pettinato April 2007 - - * uIP version Copyright (c) 2002-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - * DNS.C - * - * The lwIP DNS resolver functions are used to lookup a host name and - * map it to a numerical IP address. It maintains a list of resolved - * hostnames that can be queried with the dns_lookup() function. - * New hostnames can be resolved using the dns_query() function. - * - * The lwIP version of the resolver also adds a non-blocking version of - * gethostbyname() that will work with a raw API application. This function - * checks for an IP address string first and converts it if it is valid. - * gethostbyname() then does a dns_lookup() to see if the name is - * already in the table. If so, the IP is returned. If not, a query is - * issued and the function returns with a ERR_INPROGRESS status. The app - * using the dns client must then go into a waiting state. - * - * Once a hostname has been resolved (or found to be non-existent), - * the resolver code calls a specified callback function (which - * must be implemented by the module that uses the resolver). - */ - -/*----------------------------------------------------------------------------- - * RFC 1035 - Domain names - implementation and specification - * RFC 2181 - Clarifications to the DNS Specification - *----------------------------------------------------------------------------*/ - -/** @todo: define good default values (rfc compliance) */ -/** @todo: improve answer parsing, more checkings... */ -/** @todo: check RFC1035 - 7.3. Processing responses */ - -/*----------------------------------------------------------------------------- - * Includes - *----------------------------------------------------------------------------*/ - -#include "lwip/opt.h" - -#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/udp.h" -#include "lwip/mem.h" -#include "lwip/dns.h" - -#include - -/** DNS server IP address */ -#ifndef DNS_SERVER_ADDRESS -#define DNS_SERVER_ADDRESS inet_addr("208.67.222.222") /* resolver1.opendns.com */ -#endif - -/** DNS server port address */ -#ifndef DNS_SERVER_PORT -#define DNS_SERVER_PORT 53 -#endif - -/** DNS maximum number of retries when asking for a name, before "timeout". */ -#ifndef DNS_MAX_RETRIES -#define DNS_MAX_RETRIES 4 -#endif - -/** DNS resource record max. TTL (one week as default) */ -#ifndef DNS_MAX_TTL -#define DNS_MAX_TTL 604800 -#endif - -/* DNS protocol flags */ -#define DNS_FLAG1_RESPONSE 0x80 -#define DNS_FLAG1_OPCODE_STATUS 0x10 -#define DNS_FLAG1_OPCODE_INVERSE 0x08 -#define DNS_FLAG1_OPCODE_STANDARD 0x00 -#define DNS_FLAG1_AUTHORATIVE 0x04 -#define DNS_FLAG1_TRUNC 0x02 -#define DNS_FLAG1_RD 0x01 -#define DNS_FLAG2_RA 0x80 -#define DNS_FLAG2_ERR_MASK 0x0f -#define DNS_FLAG2_ERR_NONE 0x00 -#define DNS_FLAG2_ERR_NAME 0x03 - -/* DNS protocol states */ -#define DNS_STATE_UNUSED 0 -#define DNS_STATE_NEW 1 -#define DNS_STATE_ASKING 2 -#define DNS_STATE_DONE 3 - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** DNS message header */ -struct dns_hdr { - PACK_STRUCT_FIELD(u16_t id); - PACK_STRUCT_FIELD(u8_t flags1); - PACK_STRUCT_FIELD(u8_t flags2); - PACK_STRUCT_FIELD(u16_t numquestions); - PACK_STRUCT_FIELD(u16_t numanswers); - PACK_STRUCT_FIELD(u16_t numauthrr); - PACK_STRUCT_FIELD(u16_t numextrarr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -#define SIZEOF_DNS_HDR 12 - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** DNS query message structure */ -struct dns_query { - /* DNS query record starts with either a domain name or a pointer - to a name already present somewhere in the packet. */ - PACK_STRUCT_FIELD(u16_t type); - PACK_STRUCT_FIELD(u16_t class); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -#define SIZEOF_DNS_QUERY 4 - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** DNS answer message structure */ -struct dns_answer { - /* DNS answer record starts with either a domain name or a pointer - to a name already present somewhere in the packet. */ - PACK_STRUCT_FIELD(u16_t type); - PACK_STRUCT_FIELD(u16_t class); - PACK_STRUCT_FIELD(u32_t ttl); - PACK_STRUCT_FIELD(u16_t len); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif -#define SIZEOF_DNS_ANSWER 10 - -/** DNS table entry */ -struct dns_table_entry { - u8_t state; - u8_t numdns; - u8_t tmr; - u8_t retries; - u8_t seqno; - u8_t err; - u32_t ttl; - char name[DNS_MAX_NAME_LENGTH]; - struct ip_addr ipaddr; - /* pointer to callback on DNS query done */ - dns_found_callback found; - void *arg; -}; - -#if DNS_LOCAL_HOSTLIST -/** struct used for local host-list */ -struct local_hostlist_entry { - /** static hostname */ - const char *name; - /** static host address in network byteorder */ - u32_t addr; - struct local_hostlist_entry *next; -}; - -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC -/** Local host-list. For hostnames in this list, no - * external name resolution is performed */ -static struct local_hostlist_entry *local_hostlist_dynamic; -#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -/** Defining this allows the local_hostlist_static to be placed in a different - * linker section (e.g. FLASH) */ -#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE -#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static -#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */ -/** Defining this allows the local_hostlist_static to be placed in a different - * linker section (e.g. FLASH) */ -#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST -#define DNS_LOCAL_HOSTLIST_STORAGE_POST -#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */ -DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[] - DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT; - -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -static void dns_init_local(); -#endif /* DNS_LOCAL_HOSTLIST */ - - -/* forward declarations */ -static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); -static void dns_check_entries(void); - -/*----------------------------------------------------------------------------- - * Globales - *----------------------------------------------------------------------------*/ - -/* DNS variables */ -static struct udp_pcb *dns_pcb; -static u8_t dns_seqno; -static struct dns_table_entry dns_table[DNS_TABLE_SIZE]; -static struct ip_addr dns_servers[DNS_MAX_SERVERS]; - -#if (DNS_USES_STATIC_BUF == 1) -static u8_t dns_payload[DNS_MSG_SIZE]; -#endif /* (DNS_USES_STATIC_BUF == 1) */ - -/** - * Initialize the resolver: set up the UDP pcb and configure the default server - * (DNS_SERVER_ADDRESS). - */ -void -dns_init() -{ - struct ip_addr dnsserver; - - /* initialize default DNS server address */ - dnsserver.addr = DNS_SERVER_ADDRESS; - - LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n")); - - /* if dns client not yet initialized... */ - if (dns_pcb == NULL) { - dns_pcb = udp_new(); - - if (dns_pcb != NULL) { - /* initialize DNS table not needed (initialized to zero since it is a - * global variable) */ - LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0", - DNS_STATE_UNUSED == 0); - - /* initialize DNS client */ - udp_bind(dns_pcb, IP_ADDR_ANY, 0); - udp_recv(dns_pcb, dns_recv, NULL); - - /* initialize default DNS primary server */ - dns_setserver(0, &dnsserver); - } - } -#if DNS_LOCAL_HOSTLIST - dns_init_local(); -#endif -} - -/** - * Initialize one of the DNS servers. - * - * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS - * @param dnsserver IP address of the DNS server to set - */ -void -dns_setserver(u8_t numdns, struct ip_addr *dnsserver) -{ - if ((numdns < DNS_MAX_SERVERS) && (dns_pcb != NULL) && - (dnsserver != NULL) && (dnsserver->addr !=0 )) { - dns_servers[numdns] = (*dnsserver); - } -} - -/** - * Obtain one of the currently configured DNS server. - * - * @param numdns the index of the DNS server - * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS - * server has not been configured. - */ -struct ip_addr -dns_getserver(u8_t numdns) -{ - if (numdns < DNS_MAX_SERVERS) { - return dns_servers[numdns]; - } else { - return *IP_ADDR_ANY; - } -} - -/** - * The DNS resolver client timer - handle retries and timeouts and should - * be called every DNS_TMR_INTERVAL milliseconds (every second by default). - */ -void -dns_tmr(void) -{ - if (dns_pcb != NULL) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n")); - dns_check_entries(); - } -} - -#if DNS_LOCAL_HOSTLIST -static void -dns_init_local() -{ -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) - int i; - struct local_hostlist_entry *entry; - /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */ - struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT; - for (i = 0; i < sizeof(local_hostlist_init) / sizeof(struct local_hostlist_entry); i++) { - entry = mem_malloc(sizeof(struct local_hostlist_entry)); - LWIP_ASSERT("mem-error in dns_init_local", entry != NULL); - if (entry != NULL) { - struct local_hostlist_entry *init_entry = &local_hostlist_init[i]; - entry->name = init_entry->name; - entry->addr = init_entry->addr; - entry->next = local_hostlist_dynamic; - local_hostlist_dynamic = entry; - } - } -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */ -} - -/** - * Scans the local host-list for a hostname. - * - * @param hostname Hostname to look for in the local host-list - * @return The first IP address for the hostname in the local host-list or - * INADDR_NONE if not found. - */ -static u32_t -dns_lookup_local(const char *hostname) -{ -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC - struct local_hostlist_entry *entry = local_hostlist_dynamic; - while(entry != NULL) { - if(strcmp(entry->name, hostname) == 0) { - return entry->addr; - } - entry = entry->next; - } -#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - int i; - for (i = 0; i < sizeof(local_hostlist_static) / sizeof(struct local_hostlist_entry); i++) { - if(strcmp(local_hostlist_static[i].name, hostname) == 0) { - return local_hostlist_static[i].addr; - } - } -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - return INADDR_NONE; -} - -#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC -/** Remove all entries from the local host-list for a specific hostname - * and/or IP addess - * - * @param hostname hostname for which entries shall be removed from the local - * host-list - * @param addr address for which entries shall be removed from the local host-list - * @return the number of removed entries - */ -int -dns_local_removehost(const char *hostname, const struct ip_addr *addr) -{ - int removed = 0; - struct local_hostlist_entry *entry = local_hostlist_dynamic; - struct local_hostlist_entry *last_entry = NULL; - while (entry != NULL) { - if (((hostname == NULL) || !strcmp(entry->name, hostname)) && - ((addr == NULL) || (entry->addr == addr->addr))) { - struct local_hostlist_entry *free_entry; - if (last_entry != NULL) { - last_entry->next = entry->next; - } else { - local_hostlist_dynamic = entry->next; - } - free_entry = entry; - entry = entry->next; - mem_free(free_entry); - removed++; - } else { - last_entry = entry; - entry = entry->next; - } - } - return removed; -} - -/** - * Add a hostname/IP address pair to the local host-list. - * Duplicates are not checked. - * - * @param hostname hostname of the new entry - * @param addr IP address of the new entry - * @return ERR_OK if succeeded or ERR_MEM on memory error - */ -err_t -dns_local_addhost(const char *hostname, const struct ip_addr *addr) -{ - struct local_hostlist_entry *entry; - entry = mem_malloc(sizeof(struct local_hostlist_entry)); - if (entry == NULL) { - return ERR_MEM; - } - entry->name = hostname; - entry->addr = addr->addr; - entry->next = local_hostlist_dynamic; - local_hostlist_dynamic = entry; - return ERR_OK; -} -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/ -#endif /* DNS_LOCAL_HOSTLIST */ - -/** - * Look up a hostname in the array of known hostnames. - * - * @note This function only looks in the internal array of known - * hostnames, it does not send out a query for the hostname if none - * was found. The function dns_enqueue() can be used to send a query - * for a hostname. - * - * @param name the hostname to look up - * @return the hostname's IP address, as u32_t (instead of struct ip_addr to - * better check for failure: != INADDR_NONE) or INADDR_NONE if the hostname - * was not found in the cached dns_table. - */ -static u32_t -dns_lookup(const char *name) -{ - u8_t i; -#if DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) - u32_t addr; -#endif /* DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) */ -#if DNS_LOCAL_HOSTLIST - if ((addr = dns_lookup_local(name)) != INADDR_NONE) { - return addr; - } -#endif /* DNS_LOCAL_HOSTLIST */ -#ifdef DNS_LOOKUP_LOCAL_EXTERN - if((addr = DNS_LOOKUP_LOCAL_EXTERN(name)) != INADDR_NONE) { - return addr; - } -#endif /* DNS_LOOKUP_LOCAL_EXTERN */ - - /* Walk through name list, return entry if found. If not, return NULL. */ - for (i = 0; i < DNS_TABLE_SIZE; ++i) { - if ((dns_table[i].state == DNS_STATE_DONE) && - (strcmp(name, dns_table[i].name) == 0)) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name)); - ip_addr_debug_print(DNS_DEBUG, &(dns_table[i].ipaddr)); - LWIP_DEBUGF(DNS_DEBUG, ("\n")); - return dns_table[i].ipaddr.addr; - } - } - - return INADDR_NONE; -} - -#if DNS_DOES_NAME_CHECK -/** - * Compare the "dotted" name "query" with the encoded name "response" - * to make sure an answer from the DNS server matches the current dns_table - * entry (otherwise, answers might arrive late for hostname not on the list - * any more). - * - * @param query hostname (not encoded) from the dns_table - * @param response encoded hostname in the DNS response - * @return 0: names equal; 1: names differ - */ -static u8_t -dns_compare_name(unsigned char *query, unsigned char *response) -{ - unsigned char n; - - do { - n = *response++; - /** @see RFC 1035 - 4.1.4. Message compression */ - if ((n & 0xc0) == 0xc0) { - /* Compressed name */ - break; - } else { - /* Not compressed name */ - while (n > 0) { - if ((*query) != (*response)) { - return 1; - } - ++response; - ++query; - --n; - }; - ++query; - } - } while (*response != 0); - - return 0; -} -#endif /* DNS_DOES_NAME_CHECK */ - -/** - * Walk through a compact encoded DNS name and return the end of the name. - * - * @param query encoded DNS name in the DNS server response - * @return end of the name - */ -static unsigned char * -dns_parse_name(unsigned char *query) -{ - unsigned char n; - - do { - n = *query++; - /** @see RFC 1035 - 4.1.4. Message compression */ - if ((n & 0xc0) == 0xc0) { - /* Compressed name */ - break; - } else { - /* Not compressed name */ - while (n > 0) { - ++query; - --n; - }; - } - } while (*query != 0); - - return query + 1; -} - -/** - * Send a DNS query packet. - * - * @param numdns index of the DNS server in the dns_servers table - * @param name hostname to query - * @param id index of the hostname in dns_table, used as transaction ID in the - * DNS query packet - * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise - */ -static err_t -dns_send(u8_t numdns, const char* name, u8_t id) -{ - err_t err; - struct dns_hdr *hdr; - struct dns_query qry; - struct pbuf *p; - char *query, *nptr; - const char *pHostname; - u8_t n; - - LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n", - (u16_t)(numdns), name)); - LWIP_ASSERT("dns server out of array", numdns < DNS_MAX_SERVERS); - LWIP_ASSERT("dns server has no IP address set", dns_servers[numdns].addr != 0); - - /* if here, we have either a new query or a retry on a previous query to process */ - p = pbuf_alloc(PBUF_TRANSPORT, SIZEOF_DNS_HDR + DNS_MAX_NAME_LENGTH + - SIZEOF_DNS_QUERY, PBUF_RAM); - if (p != NULL) { - LWIP_ASSERT("pbuf must be in one piece", p->next == NULL); - /* fill dns header */ - hdr = (struct dns_hdr*)p->payload; - memset(hdr, 0, SIZEOF_DNS_HDR); - hdr->id = htons(id); - hdr->flags1 = DNS_FLAG1_RD; - hdr->numquestions = htons(1); - query = (char*)hdr + SIZEOF_DNS_HDR; - pHostname = name; - --pHostname; - - /* convert hostname into suitable query format. */ - do { - ++pHostname; - nptr = query; - ++query; - for(n = 0; *pHostname != '.' && *pHostname != 0; ++pHostname) { - *query = *pHostname; - ++query; - ++n; - } - *nptr = n; - } while(*pHostname != 0); - *query++='\0'; - - /* fill dns query */ - qry.type = htons(DNS_RRTYPE_A); - qry.class = htons(DNS_RRCLASS_IN); - MEMCPY( query, &qry, SIZEOF_DNS_QUERY); - - /* resize pbuf to the exact dns query */ - pbuf_realloc(p, (query + SIZEOF_DNS_QUERY) - ((char*)(p->payload))); - - /* connect to the server for faster receiving */ - udp_connect(dns_pcb, &dns_servers[numdns], DNS_SERVER_PORT); - /* send dns packet */ - err = udp_sendto(dns_pcb, p, &dns_servers[numdns], DNS_SERVER_PORT); - - /* free pbuf */ - pbuf_free(p); - } else { - err = ERR_MEM; - } - - return err; -} - -/** - * dns_check_entry() - see if pEntry has not yet been queried and, if so, sends out a query. - * Check an entry in the dns_table: - * - send out query for new entries - * - retry old pending entries on timeout (also with different servers) - * - remove completed entries from the table if their TTL has expired - * - * @param i index of the dns_table entry to check - */ -static void -dns_check_entry(u8_t i) -{ - struct dns_table_entry *pEntry = &dns_table[i]; - - LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE); - - switch(pEntry->state) { - - case DNS_STATE_NEW: { - /* initialize new entry */ - pEntry->state = DNS_STATE_ASKING; - pEntry->numdns = 0; - pEntry->tmr = 1; - pEntry->retries = 0; - - /* send DNS packet for this entry */ - dns_send(pEntry->numdns, pEntry->name, i); - break; - } - - case DNS_STATE_ASKING: { - if (--pEntry->tmr == 0) { - if (++pEntry->retries == DNS_MAX_RETRIES) { - if ((pEntry->numdns+1numdns+1].addr!=0)) { - /* change of server */ - pEntry->numdns++; - pEntry->tmr = 1; - pEntry->retries = 0; - break; - } else { - LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", pEntry->name)); - /* call specified callback function if provided */ - if (pEntry->found) - (*pEntry->found)(pEntry->name, NULL, pEntry->arg); - /* flush this entry */ - pEntry->state = DNS_STATE_UNUSED; - pEntry->found = NULL; - break; - } - } - - /* wait longer for the next retry */ - pEntry->tmr = pEntry->retries; - - /* send DNS packet for this entry */ - dns_send(pEntry->numdns, pEntry->name, i); - } - break; - } - - case DNS_STATE_DONE: { - /* if the time to live is nul */ - if (--pEntry->ttl == 0) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", pEntry->name)); - /* flush this entry */ - pEntry->state = DNS_STATE_UNUSED; - pEntry->found = NULL; - } - break; - } - case DNS_STATE_UNUSED: - /* nothing to do */ - break; - default: - LWIP_ASSERT("unknown dns_table entry state:", 0); - break; - } -} - -/** - * Call dns_check_entry for each entry in dns_table - check all entries. - */ -static void -dns_check_entries(void) -{ - u8_t i; - - for (i = 0; i < DNS_TABLE_SIZE; ++i) { - dns_check_entry(i); - } -} - -/** - * Receive input function for DNS response packets arriving for the dns UDP pcb. - * - * @params see udp.h - */ -static void -dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) -{ - u8_t i; - char *pHostname; - struct dns_hdr *hdr; - struct dns_answer ans; - struct dns_table_entry *pEntry; - u8_t nquestions, nanswers; -#if (DNS_USES_STATIC_BUF == 0) - u8_t dns_payload[DNS_MSG_SIZE]; -#endif /* (DNS_USES_STATIC_BUF == 0) */ -#if (DNS_USES_STATIC_BUF == 2) - u8_t* dns_payload; -#endif /* (DNS_USES_STATIC_BUF == 2) */ - - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(pcb); - LWIP_UNUSED_ARG(addr); - LWIP_UNUSED_ARG(port); - - /* is the dns message too big ? */ - if (p->tot_len > DNS_MSG_SIZE) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too big\n")); - /* free pbuf and return */ - goto memerr1; - } - - /* is the dns message big enough ? */ - if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY + SIZEOF_DNS_ANSWER)) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n")); - /* free pbuf and return */ - goto memerr1; - } - -#if (DNS_USES_STATIC_BUF == 2) - dns_payload = mem_malloc(p->tot_len); - if (dns_payload == NULL) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: mem_malloc error\n")); - /* free pbuf and return */ - goto memerr1; - } -#endif /* (DNS_USES_STATIC_BUF == 2) */ - - /* copy dns payload inside static buffer for processing */ - if (pbuf_copy_partial(p, dns_payload, p->tot_len, 0) == p->tot_len) { - /* The ID in the DNS header should be our entry into the name table. */ - hdr = (struct dns_hdr*)dns_payload; - i = htons(hdr->id); - if (i < DNS_TABLE_SIZE) { - pEntry = &dns_table[i]; - if(pEntry->state == DNS_STATE_ASKING) { - /* This entry is now completed. */ - pEntry->state = DNS_STATE_DONE; - pEntry->err = hdr->flags2 & DNS_FLAG2_ERR_MASK; - - /* We only care about the question(s) and the answers. The authrr - and the extrarr are simply discarded. */ - nquestions = htons(hdr->numquestions); - nanswers = htons(hdr->numanswers); - - /* Check for error. If so, call callback to inform. */ - if (((hdr->flags1 & DNS_FLAG1_RESPONSE) == 0) || (pEntry->err != 0) || (nquestions != 1)) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", pEntry->name)); - /* call callback to indicate error, clean up memory and return */ - goto responseerr; - } - -#if DNS_DOES_NAME_CHECK - /* Check if the name in the "question" part match with the name in the entry. */ - if (dns_compare_name((unsigned char *)(pEntry->name), (unsigned char *)dns_payload + SIZEOF_DNS_HDR) != 0) { - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", pEntry->name)); - /* call callback to indicate error, clean up memory and return */ - goto responseerr; - } -#endif /* DNS_DOES_NAME_CHECK */ - - /* Skip the name in the "question" part */ - pHostname = (char *) dns_parse_name((unsigned char *)dns_payload + SIZEOF_DNS_HDR) + SIZEOF_DNS_QUERY; - - while(nanswers > 0) { - /* skip answer resource record's host name */ - pHostname = (char *) dns_parse_name((unsigned char *)pHostname); - - /* Check for IP address type and Internet class. Others are discarded. */ - MEMCPY(&ans, pHostname, SIZEOF_DNS_ANSWER); - if((ntohs(ans.type) == DNS_RRTYPE_A) && (ntohs(ans.class) == DNS_RRCLASS_IN) && (ntohs(ans.len) == sizeof(struct ip_addr)) ) { - /* read the answer resource record's TTL, and maximize it if needed */ - pEntry->ttl = ntohl(ans.ttl); - if (pEntry->ttl > DNS_MAX_TTL) { - pEntry->ttl = DNS_MAX_TTL; - } - /* read the IP address after answer resource record's header */ - MEMCPY( &(pEntry->ipaddr), (pHostname+SIZEOF_DNS_ANSWER), sizeof(struct ip_addr)); - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", pEntry->name)); - ip_addr_debug_print(DNS_DEBUG, (&(pEntry->ipaddr))); - LWIP_DEBUGF(DNS_DEBUG, ("\n")); - /* call specified callback function if provided */ - if (pEntry->found) { - (*pEntry->found)(pEntry->name, &pEntry->ipaddr, pEntry->arg); - } - /* deallocate memory and return */ - goto memerr2; - } else { - pHostname = pHostname + SIZEOF_DNS_ANSWER + htons(ans.len); - } - --nanswers; - } - LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", pEntry->name)); - /* call callback to indicate error, clean up memory and return */ - goto responseerr; - } - } - } - - /* deallocate memory and return */ - goto memerr2; - -responseerr: - /* ERROR: call specified callback function with NULL as name to indicate an error */ - if (pEntry->found) { - (*pEntry->found)(pEntry->name, NULL, pEntry->arg); - } - /* flush this entry */ - pEntry->state = DNS_STATE_UNUSED; - pEntry->found = NULL; - -memerr2: -#if (DNS_USES_STATIC_BUF == 2) - /* free dns buffer */ - mem_free(dns_payload); -#endif /* (DNS_USES_STATIC_BUF == 2) */ - -memerr1: - /* free pbuf */ - pbuf_free(p); - return; -} - -/** - * Queues a new hostname to resolve and sends out a DNS query for that hostname - * - * @param name the hostname that is to be queried - * @param found a callback founction to be called on success, failure or timeout - * @param callback_arg argument to pass to the callback function - * @return @return a err_t return code. - */ -static err_t -dns_enqueue(const char *name, dns_found_callback found, void *callback_arg) -{ - u8_t i; - u8_t lseq, lseqi; - struct dns_table_entry *pEntry = NULL; - - /* search an unused entry, or the oldest one */ - lseq = lseqi = 0; - for (i = 0; i < DNS_TABLE_SIZE; ++i) { - pEntry = &dns_table[i]; - /* is it an unused entry ? */ - if (pEntry->state == DNS_STATE_UNUSED) - break; - - /* check if this is the oldest completed entry */ - if (pEntry->state == DNS_STATE_DONE) { - if ((dns_seqno - pEntry->seqno) > lseq) { - lseq = dns_seqno - pEntry->seqno; - lseqi = i; - } - } - } - - /* if we don't have found an unused entry, use the oldest completed one */ - if (i == DNS_TABLE_SIZE) { - if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) { - /* no entry can't be used now, table is full */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name)); - return ERR_MEM; - } else { - /* use the oldest completed one */ - i = lseqi; - pEntry = &dns_table[i]; - } - } - - /* use this entry */ - LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i))); - - /* fill the entry */ - pEntry->state = DNS_STATE_NEW; - pEntry->seqno = dns_seqno++; - pEntry->found = found; - pEntry->arg = callback_arg; - strcpy(pEntry->name, name); - - /* force to send query without waiting timer */ - dns_check_entry(i); - - /* dns query is enqueued */ - return ERR_INPROGRESS; -} - -/** - * Resolve a hostname (string) into an IP address. - * NON-BLOCKING callback version for use with raw API!!! - * - * Returns immediately with one of err_t return codes: - * - ERR_OK if hostname is a valid IP address string or the host - * name is already in the local names table. - * - ERR_INPROGRESS enqueue a request to be sent to the DNS server - * for resolution if no errors are present. - * - * @param hostname the hostname that is to be queried - * @param addr pointer to a struct ip_addr where to store the address if it is already - * cached in the dns_table (only valid if ERR_OK is returned!) - * @param found a callback function to be called on success, failure or timeout (only if - * ERR_INPROGRESS is returned!) - * @param callback_arg argument to pass to the callback function - * @return a err_t return code. - */ -err_t -dns_gethostbyname(const char *hostname, struct ip_addr *addr, dns_found_callback found, - void *callback_arg) -{ - /* not initialized or no valid server yet, or invalid addr pointer - * or invalid hostname or invalid hostname length */ - if ((dns_pcb == NULL) || (addr == NULL) || - (!hostname) || (!hostname[0]) || - (strlen(hostname) >= DNS_MAX_NAME_LENGTH)) { - return ERR_VAL; - } - -#if LWIP_HAVE_LOOPIF - if (strcmp(hostname,"localhost")==0) { - addr->addr = htonl(INADDR_LOOPBACK); - return ERR_OK; - } -#endif /* LWIP_HAVE_LOOPIF */ - - /* host name already in octet notation? set ip addr and return ERR_OK - * already have this address cached? */ - if (((addr->addr = inet_addr(hostname)) != INADDR_NONE) || - ((addr->addr = dns_lookup(hostname)) != INADDR_NONE)) { - return ERR_OK; - } - - /* queue query with specified callback */ - return dns_enqueue(hostname, found, callback_arg); -} - -#endif /* LWIP_DNS */ diff --git a/components/net/lwip-1.3.2/src/core/init.c b/components/net/lwip-1.3.2/src/core/init.c deleted file mode 100644 index be0e358216..0000000000 --- a/components/net/lwip-1.3.2/src/core/init.c +++ /dev/null @@ -1,274 +0,0 @@ -/** - * @file - * Modules initialization - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/init.h" -#include "lwip/stats.h" -#include "lwip/sys.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/sockets.h" -#include "lwip/ip.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" -#include "lwip/snmp_msg.h" -#include "lwip/autoip.h" -#include "lwip/igmp.h" -#include "lwip/dns.h" -#include "netif/etharp.h" - -/* Compile-time sanity checks for configuration errors. - * These can be done independently of LWIP_DEBUG, without penalty. - */ -#ifndef BYTE_ORDER - #error "BYTE_ORDER is not defined, you have to define it in your cc.h" -#endif -#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV) - #error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h" -#endif -#if (!LWIP_ARP && ARP_QUEUEING) - #error "If you want to use ARP Queueing, you have to define LWIP_ARP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_UDPLITE) - #error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_SNMP) - #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_DHCP) - #error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_IGMP) - #error "If you want to use IGMP, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (!LWIP_UDP && LWIP_DNS) - #error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h" -#endif -#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) - #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h" -#endif -#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0)) - #error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h" -#endif -#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0)) - #error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h" -#endif -#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0)) - #error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h" -#endif -#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0)) - #error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h" -#endif -#if (LWIP_TCP && (TCP_WND > 0xffff)) - #error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h" -#endif -#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff)) - #error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h" -#endif -#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12))) - #error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h" -#endif -#if (LWIP_TCP && TCP_LISTEN_BACKLOG && (TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff)) - #error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t" -#endif -#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1)) - #error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h" -#endif -#if (PPP_SUPPORT && (NO_SYS==1)) - #error "If you want to use PPP, you have to define NO_SYS=0 in your lwipopts.h" -#endif -#if (LWIP_NETIF_API && (NO_SYS==1)) - #error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h" -#endif -#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1)) - #error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h" -#endif -#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0)) - #error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h" -#endif -#if (!LWIP_NETCONN && LWIP_SOCKET) - #error "If you want to use Socket API, you have to define LWIP_NETCONN=1 in your lwipopts.h" -#endif -#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP) - #error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h" -#endif -#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK) - #error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h" -#endif -#if (!LWIP_ARP && LWIP_AUTOIP) - #error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h" -#endif -#if (LWIP_SNMP && (SNMP_CONCURRENT_REQUESTS<=0)) - #error "If you want to use SNMP, you have to define SNMP_CONCURRENT_REQUESTS>=1 in your lwipopts.h" -#endif -#if (LWIP_SNMP && (SNMP_TRAP_DESTINATIONS<=0)) - #error "If you want to use SNMP, you have to define SNMP_TRAP_DESTINATIONS>=1 in your lwipopts.h" -#endif -#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API))) - #error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h" -#endif -/* There must be sufficient timeouts, taking into account requirements of the subsystems. */ -#if ((NO_SYS==0) && (MEMP_NUM_SYS_TIMEOUT < (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT))) - #error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts" -#endif -#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS)) - #error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!" -#endif -#if (MEM_LIBC_MALLOC && MEM_USE_POOLS) - #error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h" -#endif -#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS) - #error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h" -#endif -#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT) - #error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf" -#endif -#if (TCP_QUEUE_OOSEQ && !LWIP_TCP) - #error "TCP_QUEUE_OOSEQ requires LWIP_TCP" -#endif -#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT))) - #error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST" -#endif -#if PPP_SUPPORT && !PPPOS_SUPPORT & !PPPOE_SUPPORT - #error "PPP_SUPPORT needs either PPPOS_SUPPORT or PPPOE_SUPPORT turned on" -#endif - - -/* Compile-time checks for deprecated options. - */ -#ifdef MEMP_NUM_TCPIP_MSG - #error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef MEMP_NUM_API_MSG - #error "MEMP_NUM_API_MSG option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef TCP_REXMIT_DEBUG - #error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef RAW_STATS - #error "RAW_STATS option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef ETHARP_QUEUE_FIRST - #error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h." -#endif -#ifdef ETHARP_ALWAYS_INSERT - #error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h." -#endif -#if SO_REUSE -/* I removed the lot since this was an ugly hack. It broke the raw-API. - It also came with many ugly goto's, Christiaan Simons. */ - #error "SO_REUSE currently unavailable, this was a hack" -#endif - -#ifdef LWIP_DEBUG -static void -lwip_sanity_check(void) -{ - /* Warnings */ -#if LWIP_NETCONN - if (MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB)) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN\n")); -#endif /* LWIP_NETCONN */ -#if LWIP_TCP - if (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN\n")); - if (TCP_SND_BUF < 2 * TCP_MSS) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly\n")); - if (TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF/TCP_MSS))) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work\n")); - if (TCP_SNDLOWAT > TCP_SND_BUF) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than or equal to TCP_SND_BUF.\n")); - if (TCP_WND > (PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE)) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE\n")); - if (TCP_WND < TCP_MSS) - LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is smaller than MSS\n")); -#endif /* LWIP_TCP */ -} -#else /* LWIP_DEBUG */ -#define lwip_sanity_check() -#endif /* LWIP_DEBUG */ - -/** - * Perform Sanity check of user-configurable values, and initialize all modules. - */ -void -lwip_init(void) -{ - /* Sanity check user-configurable values */ - lwip_sanity_check(); - - /* Modules initialization */ - stats_init(); - sys_init(); - mem_init(); - memp_init(); - pbuf_init(); - netif_init(); -#if LWIP_SOCKET - lwip_socket_init(); -#endif /* LWIP_SOCKET */ - ip_init(); -#if LWIP_ARP - etharp_init(); -#endif /* LWIP_ARP */ -#if LWIP_RAW - raw_init(); -#endif /* LWIP_RAW */ -#if LWIP_UDP - udp_init(); -#endif /* LWIP_UDP */ -#if LWIP_TCP - tcp_init(); -#endif /* LWIP_TCP */ -#if LWIP_SNMP - snmp_init(); -#endif /* LWIP_SNMP */ -#if LWIP_AUTOIP - autoip_init(); -#endif /* LWIP_AUTOIP */ -#if LWIP_IGMP - igmp_init(); -#endif /* LWIP_IGMP */ -#if LWIP_DNS - dns_init(); -#endif /* LWIP_DNS */ -} diff --git a/components/net/lwip-1.3.2/src/core/ipv4/autoip.c b/components/net/lwip-1.3.2/src/core/ipv4/autoip.c deleted file mode 100644 index 7aa7cea53f..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/autoip.c +++ /dev/null @@ -1,497 +0,0 @@ -/** - * @file - * AutoIP Automatic LinkLocal IP Configuration - * - */ - -/* - * - * Copyright (c) 2007 Dominik Spies - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dominik Spies - * - * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform - * with RFC 3927. - * - * - * Please coordinate changes and requests with Dominik Spies - * - */ - -/******************************************************************************* - * USAGE: - * - * define LWIP_AUTOIP 1 in your lwipopts.h - * - * If you don't use tcpip.c (so, don't call, you don't call tcpip_init): - * - First, call autoip_init(). - * - call autoip_tmr() all AUTOIP_TMR_INTERVAL msces, - * that should be defined in autoip.h. - * I recommend a value of 100. The value must divide 1000 with a remainder almost 0. - * Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 .... - * - * Without DHCP: - * - Call autoip_start() after netif_add(). - * - * With DHCP: - * - define LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h. - * - Configure your DHCP Client. - * - */ - -#include "lwip/opt.h" - -#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/autoip.h" -#include "netif/etharp.h" - -#include -#include - -/* 169.254.0.0 */ -#define AUTOIP_NET 0xA9FE0000 -/* 169.254.1.0 */ -#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100) -/* 169.254.254.255 */ -#define AUTOIP_RANGE_END (AUTOIP_NET | 0xFEFF) - - -/** Pseudo random macro based on netif informations. - * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */ -#ifndef LWIP_AUTOIP_RAND -#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \ - ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \ - ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \ - ((u32_t)((netif->hwaddr[4]) & 0xff))) + \ - (netif->autoip?netif->autoip->tried_llipaddr:0)) -#endif /* LWIP_AUTOIP_RAND */ - -/** - * Macro that generates the initial IP address to be tried by AUTOIP. - * If you want to override this, define it to something else in lwipopts.h. - */ -#ifndef LWIP_AUTOIP_CREATE_SEED_ADDR -#define LWIP_AUTOIP_CREATE_SEED_ADDR(netif) \ - htonl(AUTOIP_RANGE_START + ((u32_t)(((u8_t)(netif->hwaddr[4])) | \ - ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8))) -#endif /* LWIP_AUTOIP_CREATE_SEED_ADDR */ - -/* static functions */ -static void autoip_handle_arp_conflict(struct netif *netif); - -/* creates a pseudo random LL IP-Address for a network interface */ -static void autoip_create_addr(struct netif *netif, struct ip_addr *ipaddr); - -/* sends an ARP probe */ -static err_t autoip_arp_probe(struct netif *netif); - -/* sends an ARP announce */ -static err_t autoip_arp_announce(struct netif *netif); - -/* configure interface for use with current LL IP-Address */ -static err_t autoip_bind(struct netif *netif); - -/* start sending probes for llipaddr */ -static void autoip_start_probing(struct netif *netif); - -/** - * Initialize this module - */ -void -autoip_init(void) -{ - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_init()\n")); -} - -/** - * Handle a IP address conflict after an ARP conflict detection - */ -static void -autoip_handle_arp_conflict(struct netif *netif) -{ - /* Somehow detect if we are defending or retreating */ - unsigned char defend = 1; /* tbd */ - - if(defend) { - if(netif->autoip->lastconflict > 0) { - /* retreat, there was a conflicting ARP in the last - * DEFEND_INTERVAL seconds - */ - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n")); - - /* TODO: close all TCP sessions */ - autoip_start(netif); - } else { - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n")); - autoip_arp_announce(netif); - netif->autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND; - } - } else { - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("autoip_handle_arp_conflict(): we do not defend, retreating\n")); - /* TODO: close all TCP sessions */ - autoip_start(netif); - } -} - -/** - * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255 - * - * @param netif network interface on which create the IP-Address - * @param ipaddr ip address to initialize - */ -static void -autoip_create_addr(struct netif *netif, struct ip_addr *ipaddr) -{ - /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255 - * compliant to RFC 3927 Section 2.1 - * We have 254 * 256 possibilities */ - - u32_t addr = ntohl(LWIP_AUTOIP_CREATE_SEED_ADDR(netif)); - addr += netif->autoip->tried_llipaddr; - addr = AUTOIP_NET | (addr & 0xffff); - /* Now, 169.254.0.0 <= addr <= 169.254.255.255 */ - - if (addr < AUTOIP_RANGE_START) { - addr += AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1; - } - if (addr > AUTOIP_RANGE_END) { - addr -= AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1; - } - LWIP_ASSERT("AUTOIP address not in range", (addr >= AUTOIP_RANGE_START) && - (addr <= AUTOIP_RANGE_END)); - ipaddr->addr = htonl(addr); - - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("autoip_create_addr(): tried_llipaddr=%"U16_F", 0x%08"X32_F"\n", - (u16_t)(netif->autoip->tried_llipaddr), (u32_t)(ipaddr->addr))); -} - -/** - * Sends an ARP probe from a network interface - * - * @param netif network interface used to send the probe - */ -static err_t -autoip_arp_probe(struct netif *netif) -{ - return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, - (struct eth_addr *)netif->hwaddr, IP_ADDR_ANY, ðzero, - &netif->autoip->llipaddr, ARP_REQUEST); -} - -/** - * Sends an ARP announce from a network interface - * - * @param netif network interface used to send the announce - */ -static err_t -autoip_arp_announce(struct netif *netif) -{ - return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, - (struct eth_addr *)netif->hwaddr, &netif->autoip->llipaddr, ðzero, - &netif->autoip->llipaddr, ARP_REQUEST); -} - -/** - * Configure interface for use with current LL IP-Address - * - * @param netif network interface to configure with current LL IP-Address - */ -static err_t -autoip_bind(struct netif *netif) -{ - struct autoip *autoip = netif->autoip; - struct ip_addr sn_mask, gw_addr; - - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, - ("autoip_bind(netif=%p) %c%c%"U16_F" 0x%08"X32_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num, autoip->llipaddr.addr)); - - IP4_ADDR(&sn_mask, 255, 255, 0, 0); - IP4_ADDR(&gw_addr, 0, 0, 0, 0); - - netif_set_ipaddr(netif, &autoip->llipaddr); - netif_set_netmask(netif, &sn_mask); - netif_set_gw(netif, &gw_addr); - - /* bring the interface up */ - netif_set_up(netif); - - return ERR_OK; -} - -/** - * Start AutoIP client - * - * @param netif network interface on which start the AutoIP client - */ -err_t -autoip_start(struct netif *netif) -{ - struct autoip *autoip = netif->autoip; - err_t result = ERR_OK; - - if(netif_is_up(netif)) { - netif_set_down(netif); - } - - /* Set IP-Address, Netmask and Gateway to 0 to make sure that - * ARP Packets are formed correctly - */ - netif->ip_addr.addr = 0; - netif->netmask.addr = 0; - netif->gw.addr = 0; - - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], - netif->name[1], (u16_t)netif->num)); - if(autoip == NULL) { - /* no AutoIP client attached yet? */ - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, - ("autoip_start(): starting new AUTOIP client\n")); - autoip = mem_malloc(sizeof(struct autoip)); - if(autoip == NULL) { - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, - ("autoip_start(): could not allocate autoip\n")); - return ERR_MEM; - } - memset( autoip, 0, sizeof(struct autoip)); - /* store this AutoIP client in the netif */ - netif->autoip = autoip; - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip")); - } else { - autoip->state = AUTOIP_STATE_OFF; - autoip->ttw = 0; - autoip->sent_num = 0; - memset(&autoip->llipaddr, 0, sizeof(struct ip_addr)); - autoip->lastconflict = 0; - } - - autoip_create_addr(netif, &(autoip->llipaddr)); - autoip->tried_llipaddr++; - autoip_start_probing(netif); - - return result; -} - -static void -autoip_start_probing(struct netif *netif) -{ - struct autoip *autoip = netif->autoip; - - autoip->state = AUTOIP_STATE_PROBING; - autoip->sent_num = 0; - - /* time to wait to first probe, this is randomly - * choosen out of 0 to PROBE_WAIT seconds. - * compliant to RFC 3927 Section 2.2.1 - */ - autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND)); - - /* - * if we tried more then MAX_CONFLICTS we must limit our rate for - * accquiring and probing address - * compliant to RFC 3927 Section 2.2.1 - */ - if(autoip->tried_llipaddr > MAX_CONFLICTS) { - autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND; - } -} - -/** - * Handle a possible change in the network configuration. - * - * If there is an AutoIP address configured, take the interface down - * and begin probing with the same address. - */ -void -autoip_network_changed(struct netif *netif) -{ - if (netif->autoip && netif->autoip->state != AUTOIP_STATE_OFF) { - netif_set_down(netif); - autoip_start_probing(netif); - } -} - -/** - * Stop AutoIP client - * - * @param netif network interface on which stop the AutoIP client - */ -err_t -autoip_stop(struct netif *netif) -{ - netif->autoip->state = AUTOIP_STATE_OFF; - netif_set_down(netif); - return ERR_OK; -} - -/** - * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds - */ -void -autoip_tmr() -{ - struct netif *netif = netif_list; - /* loop through netif's */ - while (netif != NULL) { - /* only act on AutoIP configured interfaces */ - if (netif->autoip != NULL) { - if(netif->autoip->lastconflict > 0) { - netif->autoip->lastconflict--; - } - - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, - ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n", - (u16_t)(netif->autoip->state), netif->autoip->ttw)); - - switch(netif->autoip->state) { - case AUTOIP_STATE_PROBING: - if(netif->autoip->ttw > 0) { - netif->autoip->ttw--; - } else { - if(netif->autoip->sent_num >= PROBE_NUM) { - netif->autoip->state = AUTOIP_STATE_ANNOUNCING; - netif->autoip->sent_num = 0; - netif->autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND; - } else { - autoip_arp_probe(netif); - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, - ("autoip_tmr() PROBING Sent Probe\n")); - netif->autoip->sent_num++; - /* calculate time to wait to next probe */ - netif->autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) % - ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) + - PROBE_MIN * AUTOIP_TICKS_PER_SECOND); - } - } - break; - - case AUTOIP_STATE_ANNOUNCING: - if(netif->autoip->ttw > 0) { - netif->autoip->ttw--; - } else { - if(netif->autoip->sent_num == 0) { - /* We are here the first time, so we waited ANNOUNCE_WAIT seconds - * Now we can bind to an IP address and use it. - * - * autoip_bind calls netif_set_up. This triggers a gratuitous ARP - * which counts as an announcement. - */ - autoip_bind(netif); - } else { - autoip_arp_announce(netif); - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, - ("autoip_tmr() ANNOUNCING Sent Announce\n")); - } - netif->autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND; - netif->autoip->sent_num++; - - if(netif->autoip->sent_num >= ANNOUNCE_NUM) { - netif->autoip->state = AUTOIP_STATE_BOUND; - netif->autoip->sent_num = 0; - netif->autoip->ttw = 0; - } - } - break; - } - } - /* proceed to next network interface */ - netif = netif->next; - } -} - -/** - * Handles every incoming ARP Packet, called by etharp_arp_input. - * - * @param netif network interface to use for autoip processing - * @param hdr Incoming ARP packet - */ -void -autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr) -{ - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_arp_reply()\n")); - if ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) { - /* when ip.src == llipaddr && hw.src != netif->hwaddr - * - * when probing ip.dst == llipaddr && hw.src != netif->hwaddr - * we have a conflict and must solve it - */ - struct ip_addr sipaddr, dipaddr; - struct eth_addr netifaddr; - netifaddr.addr[0] = netif->hwaddr[0]; - netifaddr.addr[1] = netif->hwaddr[1]; - netifaddr.addr[2] = netif->hwaddr[2]; - netifaddr.addr[3] = netif->hwaddr[3]; - netifaddr.addr[4] = netif->hwaddr[4]; - netifaddr.addr[5] = netif->hwaddr[5]; - - /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without - * structure packing (not using structure copy which breaks strict-aliasing rules). - */ - SMEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr)); - SMEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr)); - - if ((netif->autoip->state == AUTOIP_STATE_PROBING) || - ((netif->autoip->state == AUTOIP_STATE_ANNOUNCING) && - (netif->autoip->sent_num == 0))) { - /* RFC 3927 Section 2.2.1: - * from beginning to after ANNOUNCE_WAIT - * seconds we have a conflict if - * ip.src == llipaddr OR - * ip.dst == llipaddr && hw.src != own hwaddr - */ - if ((ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr)) || - (ip_addr_cmp(&dipaddr, &netif->autoip->llipaddr) && - !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) { - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, - ("autoip_arp_reply(): Probe Conflict detected\n")); - autoip_start(netif); - } - } else { - /* RFC 3927 Section 2.5: - * in any state we have a conflict if - * ip.src == llipaddr && hw.src != own hwaddr - */ - if (ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr) && - !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) { - LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, - ("autoip_arp_reply(): Conflicting ARP-Packet detected\n")); - autoip_handle_arp_conflict(netif); - } - } - } -} - -#endif /* LWIP_AUTOIP */ diff --git a/components/net/lwip-1.3.2/src/core/ipv4/icmp.c b/components/net/lwip-1.3.2/src/core/ipv4/icmp.c deleted file mode 100644 index b97a587a7f..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/icmp.c +++ /dev/null @@ -1,331 +0,0 @@ -/** - * @file - * ICMP - Internet Control Message Protocol - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include "lwip/opt.h" - -#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/icmp.h" -#include "lwip/inet.h" -#include "lwip/inet_chksum.h" -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" - -#include - -/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be - * used to modify and send a response packet (and to 1 if this is not the case, - * e.g. when link header is stripped of when receiving) */ -#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN -#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1 -#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ - -/* The amount of data from the original packet to return in a dest-unreachable */ -#define ICMP_DEST_UNREACH_DATASIZE 8 - -static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code); - -/** - * Processes ICMP input packets, called from ip_input(). - * - * Currently only processes icmp echo requests and sends - * out the echo response. - * - * @param p the icmp echo request packet, p->payload pointing to the ip header - * @param inp the netif on which this packet was received - */ -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; -#ifdef LWIP_DEBUG - u8_t code; -#endif /* LWIP_DEBUG */ - struct icmp_echo_hdr *iecho; - struct ip_hdr *iphdr; - struct ip_addr tmpaddr; - s16_t hlen; - - ICMP_STATS_INC(icmp.recv); - snmp_inc_icmpinmsgs(); - - - iphdr = p->payload; - hlen = IPH_HL(iphdr) * 4; - if (pbuf_header(p, -hlen) || (p->tot_len < sizeof(u16_t)*2)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); - goto lenerr; - } - - type = *((u8_t *)p->payload); -#ifdef LWIP_DEBUG - code = *(((u8_t *)p->payload)+1); -#endif /* LWIP_DEBUG */ - switch (type) { - case ICMP_ECHO: -#if !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING - { - int accepted = 1; -#if !LWIP_MULTICAST_PING - /* multicast destination address? */ - if (ip_addr_ismulticast(&iphdr->dest)) { - accepted = 0; - } -#endif /* LWIP_MULTICAST_PING */ -#if !LWIP_BROADCAST_PING - /* broadcast destination address? */ - if (ip_addr_isbroadcast(&iphdr->dest, inp)) { - accepted = 0; - } -#endif /* LWIP_BROADCAST_PING */ - /* broadcast or multicast destination address not acceptd? */ - if (!accepted) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); - ICMP_STATS_INC(icmp.err); - pbuf_free(p); - return; - } - } -#endif /* !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - goto lenerr; - } - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); - pbuf_free(p); - ICMP_STATS_INC(icmp.chkerr); - snmp_inc_icmpinerrors(); - return; - } -#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN - if (pbuf_header(p, (PBUF_IP_HLEN + PBUF_LINK_HLEN))) { - /* p is not big enough to contain link headers - * allocate a new one and copy p into it - */ - struct pbuf *r; - /* switch p->payload to ip header */ - if (pbuf_header(p, hlen)) { - LWIP_ASSERT("icmp_input: moving p->payload to ip header failed\n", 0); - goto memerr; - } - /* allocate new packet buffer with space for link headers */ - r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); - if (r == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); - goto memerr; - } - LWIP_ASSERT("check that first pbuf can hold struct the ICMP header", - (r->len >= hlen + sizeof(struct icmp_echo_hdr))); - /* copy the whole packet including ip header */ - if (pbuf_copy(r, p) != ERR_OK) { - LWIP_ASSERT("icmp_input: copying to new pbuf failed\n", 0); - goto memerr; - } - iphdr = r->payload; - /* switch r->payload back to icmp header */ - if (pbuf_header(r, -hlen)) { - LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); - goto memerr; - } - /* free the original p */ - pbuf_free(p); - /* we now have an identical copy of p that has room for link headers */ - p = r; - } else { - /* restore p->payload to point to icmp header */ - if (pbuf_header(p, -(s16_t)(PBUF_IP_HLEN + PBUF_LINK_HLEN))) { - LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); - goto memerr; - } - } -#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ - /* At this point, all checks are OK. */ - /* We generate an answer by switching the dest and src ip addresses, - * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ - iecho = p->payload; - tmpaddr.addr = iphdr->src.addr; - iphdr->src.addr = iphdr->dest.addr; - iphdr->dest.addr = tmpaddr.addr; - ICMPH_TYPE_SET(iecho, ICMP_ER); - /* adjust the checksum */ - if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) { - iecho->chksum += htons(ICMP_ECHO << 8) + 1; - } else { - iecho->chksum += htons(ICMP_ECHO << 8); - } - - /* Set the correct TTL and recalculate the header checksum. */ - IPH_TTL_SET(iphdr, ICMP_TTL); - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); -#endif /* CHECKSUM_GEN_IP */ - - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of echo replies attempted to send */ - snmp_inc_icmpoutechoreps(); - - if(pbuf_header(p, hlen)) { - LWIP_ASSERT("Can't move over header in packet", 0); - } else { - err_t ret; - ret = ip_output_if(p, &(iphdr->src), IP_HDRINCL, - ICMP_TTL, 0, IP_PROTO_ICMP, inp); - if (ret != ERR_OK) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %c.\n", ret)); - } - } - break; - default: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", - (s16_t)type, (s16_t)code)); - ICMP_STATS_INC(icmp.proterr); - ICMP_STATS_INC(icmp.drop); - } - pbuf_free(p); - return; -lenerr: - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - snmp_inc_icmpinerrors(); - return; -#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN -memerr: - pbuf_free(p); - ICMP_STATS_INC(icmp.err); - snmp_inc_icmpinerrors(); - return; -#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ -} - -/** - * Send an icmp 'destination unreachable' packet, called from ip_input() if - * the transport layer protocol is unknown and from udp_input() if the local - * port is not bound. - * - * @param p the input packet for which the 'unreachable' should be sent, - * p->payload pointing to the IP header - * @param t type of the 'unreachable' packet - */ -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - icmp_send_response(p, ICMP_DUR, t); -} - -#if IP_FORWARD || IP_REASSEMBLY -/** - * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0. - * - * @param p the input packet for which the 'time exceeded' should be sent, - * p->payload pointing to the IP header - * @param t type of the 'time exceeded' packet - */ -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - icmp_send_response(p, ICMP_TE, t); -} - -#endif /* IP_FORWARD || IP_REASSEMBLY */ - -/** - * Send an icmp packet in response to an incoming packet. - * - * @param p the input packet for which the 'unreachable' should be sent, - * p->payload pointing to the IP header - * @param type Type of the ICMP header - * @param code Code of the ICMP header - */ -static void -icmp_send_response(struct pbuf *p, u8_t type, u8_t code) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - /* we can use the echo header here */ - struct icmp_echo_hdr *icmphdr; - - /* ICMP header + IP header + 8 bytes of data */ - q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, - PBUF_RAM); - if (q == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); - return; - } - LWIP_ASSERT("check that first pbuf can hold icmp message", - (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); - - iphdr = p->payload; - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); - ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src)); - LWIP_DEBUGF(ICMP_DEBUG, (" to ")); - ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest)); - LWIP_DEBUGF(ICMP_DEBUG, ("\n")); - - icmphdr = q->payload; - icmphdr->type = type; - icmphdr->code = code; - icmphdr->id = 0; - icmphdr->seqno = 0; - - /* copy fields from original packet */ - SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, - IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); - - /* calculate checksum */ - icmphdr->chksum = 0; - icmphdr->chksum = inet_chksum(icmphdr, q->len); - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of destination unreachable messages attempted to send */ - snmp_inc_icmpouttimeexcds(); - ip_output(q, NULL, &(iphdr->src), ICMP_TTL, 0, IP_PROTO_ICMP); - pbuf_free(q); -} - -#endif /* LWIP_ICMP */ diff --git a/components/net/lwip-1.3.2/src/core/ipv4/igmp.c b/components/net/lwip-1.3.2/src/core/ipv4/igmp.c deleted file mode 100644 index 7c07bc4657..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/igmp.c +++ /dev/null @@ -1,757 +0,0 @@ -/** - * @file - * IGMP - Internet Group Management Protocol - * - */ - -/* - * Copyright (c) 2002 CITEL Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. -*/ - -/*------------------------------------------------------------- -Note 1) -Although the rfc requires V1 AND V2 capability -we will only support v2 since now V1 is very old (August 1989) -V1 can be added if required - -a debug print and statistic have been implemented to -show this up. -------------------------------------------------------------- -------------------------------------------------------------- -Note 2) -A query for a specific group address (as opposed to ALLHOSTS) -has now been implemented as I am unsure if it is required - -a debug print and statistic have been implemented to -show this up. -------------------------------------------------------------- -------------------------------------------------------------- -Note 3) -The router alert rfc 2113 is implemented in outgoing packets -but not checked rigorously incoming -------------------------------------------------------------- -Steve Reynolds -------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * RFC 988 - Host extensions for IP multicasting - V0 - * RFC 1054 - Host extensions for IP multicasting - - * RFC 1112 - Host extensions for IP multicasting - V1 - * RFC 2236 - Internet Group Management Protocol, Version 2 - V2 <- this code is based on this RFC (it's the "de facto" standard) - * RFC 3376 - Internet Group Management Protocol, Version 3 - V3 - * RFC 4604 - Using Internet Group Management Protocol Version 3... - V3+ - * RFC 2113 - IP Router Alert Option - - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Includes - *----------------------------------------------------------------------------*/ - -#include "lwip/opt.h" - -#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/igmp.h" -#include "lwip/debug.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/inet.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" -#include "lwip/stats.h" - -#include "string.h" - -/*----------------------------------------------------------------------------- - * Globales - *----------------------------------------------------------------------------*/ - -static struct igmp_group* igmp_group_list; -static struct ip_addr allsystems; -static struct ip_addr allrouters; - -/** - * Initialize the IGMP module - */ -void -igmp_init(void) -{ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n")); - - IP4_ADDR(&allsystems, 224, 0, 0, 1); - IP4_ADDR(&allrouters, 224, 0, 0, 2); -} - -#ifdef LWIP_DEBUG -/** - * Dump global IGMP groups list - */ -void -igmp_dump_group_list() -{ - struct igmp_group *group = igmp_group_list; - - while (group != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_dump_group_list: [%"U32_F"] ", (u32_t)(group->group_state))); - ip_addr_debug_print(IGMP_DEBUG, &group->group_address); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->interface)); - group = group->next; - } - LWIP_DEBUGF(IGMP_DEBUG, ("\n")); -} -#else -#define igmp_dump_group_list() -#endif /* LWIP_DEBUG */ - -/** - * Start IGMP processing on interface - * - * @param netif network interface on which start IGMP processing - */ -err_t -igmp_start(struct netif *netif) -{ - struct igmp_group* group; - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", netif)); - - group = igmp_lookup_group(netif, &allsystems); - - if (group != NULL) { - group->group_state = IGMP_GROUP_IDLE_MEMBER; - group->use++; - - /* Allow the igmp messages at the MAC level */ - if (netif->igmp_mac_filter != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD ")); - ip_addr_debug_print(IGMP_DEBUG, &allsystems); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); - netif->igmp_mac_filter( netif, &allsystems, IGMP_ADD_MAC_FILTER); - } - - return ERR_OK; - } - - return ERR_MEM; -} - -/** - * Stop IGMP processing on interface - * - * @param netif network interface on which stop IGMP processing - */ -err_t -igmp_stop(struct netif *netif) -{ - struct igmp_group *group = igmp_group_list; - struct igmp_group *prev = NULL; - struct igmp_group *next; - - /* look for groups joined on this interface further down the list */ - while (group != NULL) { - next = group->next; - /* is it a group joined on this interface? */ - if (group->interface == netif) { - /* is it the first group of the list? */ - if (group == igmp_group_list) { - igmp_group_list = next; - } - /* is there a "previous" group defined? */ - if (prev != NULL) { - prev->next = next; - } - /* disable the group at the MAC level */ - if (netif->igmp_mac_filter != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL ")); - ip_addr_debug_print(IGMP_DEBUG, &group->group_address); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); - netif->igmp_mac_filter(netif, &(group->group_address), IGMP_DEL_MAC_FILTER); - } - /* free group */ - memp_free(MEMP_IGMP_GROUP, group); - } else { - /* change the "previous" */ - prev = group; - } - /* move to "next" */ - group = next; - } - return ERR_OK; -} - -/** - * Report IGMP memberships for this interface - * - * @param netif network interface on which report IGMP memberships - */ -void -igmp_report_groups( struct netif *netif) -{ - struct igmp_group *group = igmp_group_list; - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", netif)); - - while (group != NULL) { - if (group->interface == netif) { - igmp_delaying_member( group, IGMP_JOIN_DELAYING_MEMBER_TMR); - } - group = group->next; - } -} - -/** - * Search for a group in the global igmp_group_list - * - * @param ifp the network interface for which to look - * @param addr the group ip address to search for - * @return a struct igmp_group* if the group has been found, - * NULL if the group wasn't found. - */ -struct igmp_group * -igmp_lookfor_group(struct netif *ifp, struct ip_addr *addr) -{ - struct igmp_group *group = igmp_group_list; - - while (group != NULL) { - if ((group->interface == ifp) && (ip_addr_cmp(&(group->group_address), addr))) { - return group; - } - group = group->next; - } - - /* to be clearer, we return NULL here instead of - * 'group' (which is also NULL at this point). - */ - return NULL; -} - -/** - * Search for a specific igmp group and create a new one if not found- - * - * @param ifp the network interface for which to look - * @param addr the group ip address to search - * @return a struct igmp_group*, - * NULL on memory error. - */ -struct igmp_group * -igmp_lookup_group(struct netif *ifp, struct ip_addr *addr) -{ - struct igmp_group *group = igmp_group_list; - - /* Search if the group already exists */ - group = igmp_lookfor_group(ifp, addr); - if (group != NULL) { - /* Group already exists. */ - return group; - } - - /* Group doesn't exist yet, create a new one */ - group = memp_malloc(MEMP_IGMP_GROUP); - if (group != NULL) { - group->interface = ifp; - ip_addr_set(&(group->group_address), addr); - group->timer = 0; /* Not running */ - group->group_state = IGMP_GROUP_NON_MEMBER; - group->last_reporter_flag = 0; - group->use = 0; - group->next = igmp_group_list; - - igmp_group_list = group; - } - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group?"":"impossible to "))); - ip_addr_debug_print(IGMP_DEBUG, addr); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", ifp)); - - return group; -} - -/** - * Remove a group in the global igmp_group_list - * - * @param group the group to remove from the global igmp_group_list - * @return ERR_OK if group was removed from the list, an err_t otherwise - */ -err_t -igmp_remove_group(struct igmp_group *group) -{ - err_t err = ERR_OK; - - /* Is it the first group? */ - if (igmp_group_list == group) { - igmp_group_list = group->next; - } else { - /* look for group further down the list */ - struct igmp_group *tmpGroup; - for (tmpGroup = igmp_group_list; tmpGroup != NULL; tmpGroup = tmpGroup->next) { - if (tmpGroup->next == group) { - tmpGroup->next = group->next; - break; - } - } - /* Group not found in the global igmp_group_list */ - if (tmpGroup == NULL) - err = ERR_ARG; - } - /* free group */ - memp_free(MEMP_IGMP_GROUP, group); - - return err; -} - -/** - * Called from ip_input() if a new IGMP packet is received. - * - * @param p received igmp packet, p->payload pointing to the ip header - * @param inp network interface on which the packet was received - * @param dest destination ip address of the igmp packet - */ -void -igmp_input(struct pbuf *p, struct netif *inp, struct ip_addr *dest) -{ - struct ip_hdr * iphdr; - struct igmp_msg* igmp; - struct igmp_group* group; - struct igmp_group* groupref; - - /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */ - iphdr = p->payload; - if (pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4)) || (p->len < IGMP_MINLEN)) { - pbuf_free(p); - IGMP_STATS_INC(igmp.lenerr); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n")); - return; - } - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from ")); - ip_addr_debug_print(IGMP_DEBUG, &(iphdr->src)); - LWIP_DEBUGF(IGMP_DEBUG, (" to address ")); - ip_addr_debug_print(IGMP_DEBUG, &(iphdr->dest)); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", inp)); - - /* Now calculate and check the checksum */ - igmp = (struct igmp_msg *)p->payload; - if (inet_chksum(igmp, p->len)) { - pbuf_free(p); - IGMP_STATS_INC(igmp.chkerr); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n")); - return; - } - - /* Packet is ok so find an existing group */ - group = igmp_lookfor_group(inp, dest); /* use the incoming IP address! */ - - /* If group can be found or create... */ - if (!group) { - pbuf_free(p); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n")); - return; - } - - /* NOW ACT ON THE INCOMING MESSAGE TYPE... */ - switch (igmp->igmp_msgtype) { - case IGMP_MEMB_QUERY: { - /* IGMP_MEMB_QUERY to the "all systems" address ? */ - if ((ip_addr_cmp(dest, &allsystems)) && (igmp->igmp_group_address.addr == 0)) { - /* THIS IS THE GENERAL QUERY */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); - - if (igmp->igmp_maxresp == 0) { - IGMP_STATS_INC(igmp.v1_rxed); - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n")); - igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR; - } - - IGMP_STATS_INC(igmp.group_query_rxed); - groupref = igmp_group_list; - while (groupref) { - /* Do not send messages on the all systems group address! */ - if ((groupref->interface == inp) && (!(ip_addr_cmp(&(groupref->group_address), &allsystems)))) { - igmp_delaying_member( groupref, igmp->igmp_maxresp); - } - groupref = groupref->next; - } - } else { - /* IGMP_MEMB_QUERY to a specific group ? */ - if (group->group_address.addr != 0) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group ")); - ip_addr_debug_print(IGMP_DEBUG, &group->group_address); - if (ip_addr_cmp (dest, &allsystems)) { - LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); - /* we first need to re-lookfor the group since we used dest last time */ - group = igmp_lookfor_group(inp, &igmp->igmp_group_address); - } else { - LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); - } - - if (group != NULL) { - IGMP_STATS_INC(igmp.unicast_query); - igmp_delaying_member( group, igmp->igmp_maxresp); - } - } - } - break; - } - case IGMP_V2_MEMB_REPORT: { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n")); - - IGMP_STATS_INC(igmp.report_rxed); - if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) { - /* This is on a specific group we have already looked up */ - group->timer = 0; /* stopped */ - group->group_state = IGMP_GROUP_IDLE_MEMBER; - group->last_reporter_flag = 0; - } - break; - } - default: { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n", - igmp->igmp_msgtype, group->group_state, &group, group->interface)); - break; - } - } - - pbuf_free(p); - return; -} - -/** - * Join a group on one network interface. - * - * @param ifaddr ip address of the network interface which should join a new group - * @param groupaddr the ip address of the group which to join - * @return ERR_OK if group was joined on the netif(s), an err_t otherwise - */ -err_t -igmp_joingroup(struct ip_addr *ifaddr, struct ip_addr *groupaddr) -{ - err_t err = ERR_VAL; /* no matching interface */ - struct igmp_group *group; - struct netif *netif; - - /* make sure it is multicast address */ - LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;); - LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); - - /* loop through netif's */ - netif = netif_list; - while (netif != NULL) { - /* Should we join this interface ? */ - if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) { - /* find group or create a new one if not found */ - group = igmp_lookup_group(netif, groupaddr); - - if (group != NULL) { - /* This should create a new group, check the state to make sure */ - if (group->group_state != IGMP_GROUP_NON_MEMBER) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to group not in state IGMP_GROUP_NON_MEMBER\n")); - } else { - /* OK - it was new group */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to new group: ")); - ip_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, ("\n")); - - /* If first use of the group, allow the group at the MAC level */ - if ((group->use==0) && (netif->igmp_mac_filter != NULL)) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: igmp_mac_filter(ADD ")); - ip_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); - netif->igmp_mac_filter(netif, groupaddr, IGMP_ADD_MAC_FILTER); - } - - IGMP_STATS_INC(igmp.join_sent); - igmp_send(group, IGMP_V2_MEMB_REPORT); - - igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR); - - /* Need to work out where this timer comes from */ - group->group_state = IGMP_GROUP_DELAYING_MEMBER; - } - /* Increment group use */ - group->use++; - /* Join on this interface */ - err = ERR_OK; - } else { - /* Return an error even if some network interfaces are joined */ - /** @todo undo any other netif already joined */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: Not enought memory to join to group\n")); - return ERR_MEM; - } - } - /* proceed to next network interface */ - netif = netif->next; - } - - return err; -} - -/** - * Leave a group on one network interface. - * - * @param ifaddr ip address of the network interface which should leave a group - * @param groupaddr the ip address of the group which to leave - * @return ERR_OK if group was left on the netif(s), an err_t otherwise - */ -err_t -igmp_leavegroup(struct ip_addr *ifaddr, struct ip_addr *groupaddr) -{ - err_t err = ERR_VAL; /* no matching interface */ - struct igmp_group *group; - struct netif *netif; - - /* make sure it is multicast address */ - LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;); - LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); - - /* loop through netif's */ - netif = netif_list; - while (netif != NULL) { - /* Should we leave this interface ? */ - if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) { - /* find group */ - group = igmp_lookfor_group(netif, groupaddr); - - if (group != NULL) { - /* Only send a leave if the flag is set according to the state diagram */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: Leaving group: ")); - ip_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, ("\n")); - - /* If there is no other use of the group */ - if (group->use <= 1) { - /* If we are the last reporter for this group */ - if (group->last_reporter_flag) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: sending leaving group\n")); - IGMP_STATS_INC(igmp.leave_sent); - igmp_send(group, IGMP_LEAVE_GROUP); - } - - /* Disable the group at the MAC level */ - if (netif->igmp_mac_filter != NULL) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: igmp_mac_filter(DEL ")); - ip_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); - netif->igmp_mac_filter(netif, groupaddr, IGMP_DEL_MAC_FILTER); - } - - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: remove group: ")); - ip_addr_debug_print(IGMP_DEBUG, groupaddr); - LWIP_DEBUGF(IGMP_DEBUG, ("\n")); - - /* Free the group */ - igmp_remove_group(group); - } else { - /* Decrement group use */ - group->use--; - } - /* Leave on this interface */ - err = ERR_OK; - } else { - /* It's not a fatal error on "leavegroup" */ - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: not member of group\n")); - } - } - /* proceed to next network interface */ - netif = netif->next; - } - - return err; -} - -/** - * The igmp timer function (both for NO_SYS=1 and =0) - * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default). - */ -void -igmp_tmr(void) -{ - struct igmp_group *group = igmp_group_list; - - while (group != NULL) { - if (group->timer != 0) { - group->timer -= 1; - if (group->timer == 0) { - igmp_timeout(group); - } - } - group = group->next; - } -} - -/** - * Called if a timeout for one group is reached. - * Sends a report for this group. - * - * @param group an igmp_group for which a timeout is reached - */ -void -igmp_timeout(struct igmp_group *group) -{ - /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group */ - if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address ")); - ip_addr_debug_print(IGMP_DEBUG, &(group->group_address)); - LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->interface)); - - igmp_send(group, IGMP_V2_MEMB_REPORT); - } -} - -/** - * Start a timer for an igmp group - * - * @param group the igmp_group for which to start a timer - * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with - * every call to igmp_tmr()) - */ -void -igmp_start_timer(struct igmp_group *group, u8_t max_time) -{ - /** - * @todo Important !! this should be random 0 -> max_time. Find out how to do this - */ - group->timer = max_time; -} - -/** - * Stop a timer for an igmp_group - * - * @param group the igmp_group for which to stop the timer - */ -void -igmp_stop_timer(struct igmp_group *group) -{ - group->timer = 0; -} - -/** - * Delaying membership report for a group if necessary - * - * @param group the igmp_group for which "delaying" membership report - * @param maxresp query delay - */ -void -igmp_delaying_member( struct igmp_group *group, u8_t maxresp) -{ - if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) || - ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && (maxresp > group->timer))) { - igmp_start_timer(group, (maxresp)/2); - group->group_state = IGMP_GROUP_DELAYING_MEMBER; - } -} - - -/** - * Sends an IP packet on a network interface. This function constructs the IP header - * and calculates the IP header checksum. If the source IP address is NULL, - * the IP address of the outgoing network interface is filled in as source address. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == IP_HDRINCL, p already includes an IP - header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * @param netif the netif on which to send this packet - * @return ERR_OK if the packet was sent OK - * ERR_BUF if p doesn't have enough space for IP/LINK headers - * returns errors returned by netif->output - */ -err_t -igmp_ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto, struct netif *netif) -{ - /* This is the "router alert" option */ - u16_t ra[2]; - ra[0] = htons (ROUTER_ALERT); - ra[1] = 0x0000; /* Router shall examine packet */ - return ip_output_if_opt(p, src, dest, ttl, 0, proto, netif, ra, ROUTER_ALERTLEN); -} - -/** - * Send an igmp packet to a specific group. - * - * @param group the group to which to send the packet - * @param type the type of igmp packet to send - */ -void -igmp_send(struct igmp_group *group, u8_t type) -{ - struct pbuf* p = NULL; - struct igmp_msg* igmp = NULL; - struct ip_addr src = {0}; - struct ip_addr* dest = NULL; - - /* IP header + "router alert" option + IGMP header */ - p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM); - - if (p) { - igmp = p->payload; - LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg", - (p->len >= sizeof(struct igmp_msg))); - ip_addr_set(&src, &((group->interface)->ip_addr)); - - if (type == IGMP_V2_MEMB_REPORT) { - dest = &(group->group_address); - IGMP_STATS_INC(igmp.report_sent); - ip_addr_set(&(igmp->igmp_group_address), &(group->group_address)); - group->last_reporter_flag = 1; /* Remember we were the last to report */ - } else { - if (type == IGMP_LEAVE_GROUP) { - dest = &allrouters; - ip_addr_set(&(igmp->igmp_group_address), &(group->group_address)); - } - } - - if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) { - igmp->igmp_msgtype = type; - igmp->igmp_maxresp = 0; - igmp->igmp_checksum = 0; - igmp->igmp_checksum = inet_chksum( igmp, IGMP_MINLEN); - - igmp_ip_output_if(p, &src, dest, IGMP_TTL, IP_PROTO_IGMP, group->interface); - } - - pbuf_free(p); - } else { - LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n")); - } -} - -#endif /* LWIP_IGMP */ diff --git a/components/net/lwip-1.3.2/src/core/ipv4/inet.c b/components/net/lwip-1.3.2/src/core/ipv4/inet.c deleted file mode 100644 index 69baf1d508..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/inet.c +++ /dev/null @@ -1,278 +0,0 @@ -/** - * @file - * Functions common to all TCP/IPv4 modules, such as the byte order functions. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/inet.h" - -/* Here for now until needed in other places in lwIP */ -#ifndef isprint -#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) -#define isprint(c) in_range(c, 0x20, 0x7f) -#define isdigit(c) in_range(c, '0', '9') -#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) -#define islower(c) in_range(c, 'a', 'z') -#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') -#endif - -/** - * Ascii internet address interpretation routine. - * The value returned is in network order. - * - * @param cp IP address in ascii represenation (e.g. "127.0.0.1") - * @return ip address in network order - */ -u32_t -inet_addr(const char *cp) -{ - struct in_addr val; - - if (inet_aton(cp, &val)) { - return (val.s_addr); - } - return (INADDR_NONE); -} - -/** - * Check whether "cp" is a valid ascii representation - * of an Internet address and convert to a binary address. - * Returns 1 if the address is valid, 0 if not. - * This replaces inet_addr, the return value from which - * cannot distinguish between failure and a local broadcast address. - * - * @param cp IP address in ascii represenation (e.g. "127.0.0.1") - * @param addr pointer to which to save the ip address in network order - * @return 1 if cp could be converted to addr, 0 on failure - */ -int -inet_aton(const char *cp, struct in_addr *addr) -{ - u32_t val; - u8_t base; - char c; - u32_t parts[4]; - u32_t *pp = parts; - - c = *cp; - for (;;) { - /* - * Collect number up to ``.''. - * Values are specified as for C: - * 0x=hex, 0=octal, 1-9=decimal. - */ - if (!isdigit(c)) - return (0); - val = 0; - base = 10; - if (c == '0') { - c = *++cp; - if (c == 'x' || c == 'X') { - base = 16; - c = *++cp; - } else - base = 8; - } - for (;;) { - if (isdigit(c)) { - val = (val * base) + (int)(c - '0'); - c = *++cp; - } else if (base == 16 && isxdigit(c)) { - val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A')); - c = *++cp; - } else - break; - } - if (c == '.') { - /* - * Internet format: - * a.b.c.d - * a.b.c (with c treated as 16 bits) - * a.b (with b treated as 24 bits) - */ - if (pp >= parts + 3) - return (0); - *pp++ = val; - c = *++cp; - } else - break; - } - /* - * Check for trailing characters. - */ - if (c != '\0' && !isspace(c)) - return (0); - /* - * Concoct the address according to - * the number of parts specified. - */ - switch (pp - parts + 1) { - - case 0: - return (0); /* initial nondigit */ - - case 1: /* a -- 32 bits */ - break; - - case 2: /* a.b -- 8.24 bits */ - if (val > 0xffffffUL) - return (0); - val |= parts[0] << 24; - break; - - case 3: /* a.b.c -- 8.8.16 bits */ - if (val > 0xffff) - return (0); - val |= (parts[0] << 24) | (parts[1] << 16); - break; - - case 4: /* a.b.c.d -- 8.8.8.8 bits */ - if (val > 0xff) - return (0); - val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); - break; - } - if (addr) - addr->s_addr = htonl(val); - return (1); -} - -/** - * Convert numeric IP address into decimal dotted ASCII representation. - * returns ptr to static buffer; not reentrant! - * - * @param addr ip address in network order to convert - * @return pointer to a global static (!) buffer that holds the ASCII - * represenation of addr - */ -char * -inet_ntoa(struct in_addr addr) -{ - static char str[16]; - u32_t s_addr = addr.s_addr; - char inv[3]; - char *rp; - u8_t *ap; - u8_t rem; - u8_t n; - u8_t i; - - rp = str; - ap = (u8_t *)&s_addr; - for(n = 0; n < 4; n++) { - i = 0; - do { - rem = *ap % (u8_t)10; - *ap /= (u8_t)10; - inv[i++] = '0' + rem; - } while(*ap); - while(i--) - *rp++ = inv[i]; - *rp++ = '.'; - ap++; - } - *--rp = 0; - return str; -} - -/** - * These are reference implementations of the byte swapping functions. - * Again with the aim of being simple, correct and fully portable. - * Byte swapping is the second thing you would want to optimize. You will - * need to port it to your architecture and in your cc.h: - * - * #define LWIP_PLATFORM_BYTESWAP 1 - * #define LWIP_PLATFORM_HTONS(x) - * #define LWIP_PLATFORM_HTONL(x) - * - * Note ntohs() and ntohl() are merely references to the htonx counterparts. - */ - -#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) - -/** - * Convert an u16_t from host- to network byte order. - * - * @param n u16_t in host byte order - * @return n in network byte order - */ -u16_t -htons(u16_t n) -{ - return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); -} - -/** - * Convert an u16_t from network- to host byte order. - * - * @param n u16_t in network byte order - * @return n in host byte order - */ -u16_t -ntohs(u16_t n) -{ - return htons(n); -} - -/** - * Convert an u32_t from host- to network byte order. - * - * @param n u32_t in host byte order - * @return n in network byte order - */ -u32_t -htonl(u32_t n) -{ - return ((n & 0xff) << 24) | - ((n & 0xff00) << 8) | - ((n & 0xff0000UL) >> 8) | - ((n & 0xff000000UL) >> 24); -} - -/** - * Convert an u32_t from network- to host byte order. - * - * @param n u32_t in network byte order - * @return n in host byte order - */ -u32_t -ntohl(u32_t n) -{ - return htonl(n); -} - -#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */ diff --git a/components/net/lwip-1.3.2/src/core/ipv4/inet_chksum.c b/components/net/lwip-1.3.2/src/core/ipv4/inet_chksum.c deleted file mode 100644 index 185881efd8..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/inet_chksum.c +++ /dev/null @@ -1,438 +0,0 @@ -/** - * @file - * Incluse internet checksum functions. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/inet_chksum.h" -#include "lwip/inet.h" - -#include - -/* These are some reference implementations of the checksum algorithm, with the - * aim of being simple, correct and fully portable. Checksumming is the - * first thing you would want to optimize for your platform. If you create - * your own version, link it in and in your cc.h put: - * - * #define LWIP_CHKSUM - * - * Or you can select from the implementations below by defining - * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3. - */ - -#ifndef LWIP_CHKSUM -# define LWIP_CHKSUM lwip_standard_chksum -# ifndef LWIP_CHKSUM_ALGORITHM -# define LWIP_CHKSUM_ALGORITHM 1 -# endif -#endif -/* If none set: */ -#ifndef LWIP_CHKSUM_ALGORITHM -# define LWIP_CHKSUM_ALGORITHM 0 -#endif - -/** Like the name says... */ -#if LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) -/* little endian and PLATFORM_BYTESWAP defined */ -#define SWAP_BYTES_IN_WORD(w) LWIP_PLATFORM_HTONS(w) -#else -/* can't use htons on big endian (or PLATFORM_BYTESWAP not defined)... */ -#define SWAP_BYTES_IN_WORD(w) ((w & 0xff) << 8) | ((w & 0xff00) >> 8) -#endif - -/** Split an u32_t in two u16_ts and add them up */ -#define FOLD_U32T(u) ((u >> 16) + (u & 0x0000ffffUL)) - -#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */ -/** - * lwip checksum - * - * @param dataptr points to start of data to be summed at any boundary - * @param len length of data to be summed - * @return host order (!) lwip checksum (non-inverted Internet sum) - * - * @note accumulator size limits summable length to 64k - * @note host endianess is irrelevant (p3 RFC1071) - */ -static u16_t -lwip_standard_chksum(void *dataptr, u16_t len) -{ - u32_t acc; - u16_t src; - u8_t *octetptr; - - acc = 0; - /* dataptr may be at odd or even addresses */ - octetptr = (u8_t*)dataptr; - while (len > 1) { - /* declare first octet as most significant - thus assume network order, ignoring host order */ - src = (*octetptr) << 8; - octetptr++; - /* declare second octet as least significant */ - src |= (*octetptr); - octetptr++; - acc += src; - len -= 2; - } - if (len > 0) { - /* accumulate remaining octet */ - src = (*octetptr) << 8; - acc += src; - } - /* add deferred carry bits */ - acc = (acc >> 16) + (acc & 0x0000ffffUL); - if ((acc & 0xffff0000UL) != 0) { - acc = (acc >> 16) + (acc & 0x0000ffffUL); - } - /* This maybe a little confusing: reorder sum using htons() - instead of ntohs() since it has a little less call overhead. - The caller must invert bits for Internet sum ! */ - return htons((u16_t)acc); -} -#endif - -#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */ -/* - * Curt McDowell - * Broadcom Corp. - * csm@broadcom.com - * - * IP checksum two bytes at a time with support for - * unaligned buffer. - * Works for len up to and including 0x20000. - * by Curt McDowell, Broadcom Corp. 12/08/2005 - * - * @param dataptr points to start of data to be summed at any boundary - * @param len length of data to be summed - * @return host order (!) lwip checksum (non-inverted Internet sum) - */ - -static u16_t -lwip_standard_chksum(void *dataptr, int len) -{ - u8_t *pb = dataptr; - u16_t *ps, t = 0; - u32_t sum = 0; - int odd = ((u32_t)pb & 1); - - /* Get aligned to u16_t */ - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - /* Add the bulk of the data */ - ps = (u16_t *)pb; - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* Consume left-over byte, if any */ - if (len > 0) { - ((u8_t *)&t)[0] = *(u8_t *)ps;; - } - - /* Add end bytes */ - sum += t; - - /* Fold 32-bit sum to 16 bits - calling this twice is propably faster than if statements... */ - sum = FOLD_U32T(sum); - sum = FOLD_U32T(sum); - - /* Swap if alignment was odd */ - if (odd) { - sum = SWAP_BYTES_IN_WORD(sum); - } - - return sum; -} -#endif - -#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */ -/** - * An optimized checksum routine. Basically, it uses loop-unrolling on - * the checksum loop, treating the head and tail bytes specially, whereas - * the inner loop acts on 8 bytes at a time. - * - * @arg start of buffer to be checksummed. May be an odd byte address. - * @len number of bytes in the buffer to be checksummed. - * @return host order (!) lwip checksum (non-inverted Internet sum) - * - * by Curt McDowell, Broadcom Corp. December 8th, 2005 - */ - -static u16_t -lwip_standard_chksum(void *dataptr, int len) -{ - u8_t *pb = dataptr; - u16_t *ps, t = 0; - u32_t *pl; - u32_t sum = 0, tmp; - /* starts at odd byte address? */ - int odd = ((u32_t)pb & 1); - - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - ps = (u16_t *)pb; - - if (((u32_t)ps & 3) && len > 1) { - sum += *ps++; - len -= 2; - } - - pl = (u32_t *)ps; - - while (len > 7) { - tmp = sum + *pl++; /* ping */ - if (tmp < sum) { - tmp++; /* add back carry */ - } - - sum = tmp + *pl++; /* pong */ - if (sum < tmp) { - sum++; /* add back carry */ - } - - len -= 8; - } - - /* make room in upper bits */ - sum = FOLD_U32T(sum); - - ps = (u16_t *)pl; - - /* 16-bit aligned word remaining? */ - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* dangling tail byte remaining? */ - if (len > 0) { /* include odd byte */ - ((u8_t *)&t)[0] = *(u8_t *)ps; - } - - sum += t; /* add end bytes */ - - /* Fold 32-bit sum to 16 bits - calling this twice is propably faster than if statements... */ - sum = FOLD_U32T(sum); - sum = FOLD_U32T(sum); - - if (odd) { - sum = SWAP_BYTES_IN_WORD(sum); - } - - return sum; -} -#endif - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - * IP addresses are expected to be in network byte order. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param src source ip address (used for checksum of pseudo header) - * @param dst destination ip address (used for checksum of pseudo header) - * @param proto ip protocol (used for checksum of pseudo header) - * @param proto_len length of the ip data part (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u16_t proto_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - /* iterate through all pbuf in chain */ - for(q = p; q != NULL; q = q->next) { - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", - (void *)q, (void *)q->next)); - acc += LWIP_CHKSUM(q->payload, q->len); - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ - /* just executing this next line is probably faster that the if statement needed - to check whether we really need to execute it, and does no harm */ - acc = FOLD_U32T(acc); - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = SWAP_BYTES_IN_WORD(acc); - } - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ - } - - if (swapped) { - acc = SWAP_BYTES_IN_WORD(acc); - } - acc += (src->addr & 0xffffUL); - acc += ((src->addr >> 16) & 0xffffUL); - acc += (dest->addr & 0xffffUL); - acc += ((dest->addr >> 16) & 0xffffUL); - acc += (u32_t)htons((u16_t)proto); - acc += (u32_t)htons(proto_len); - - /* Fold 32-bit sum to 16 bits - calling this twice is propably faster than if statements... */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); - return (u16_t)~(acc & 0xffffUL); -} - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - * IP addresses are expected to be in network byte order. - * - * @param p chain of pbufs over that a checksum should be calculated (ip data part) - * @param src source ip address (used for checksum of pseudo header) - * @param dst destination ip address (used for checksum of pseudo header) - * @param proto ip protocol (used for checksum of pseudo header) - * @param proto_len length of the ip data part (used for checksum of pseudo header) - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -/* Currently only used by UDPLITE, although this could change in the future. */ -#if LWIP_UDPLITE -u16_t -inet_chksum_pseudo_partial(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u16_t proto_len, u16_t chksum_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - u16_t chklen; - - acc = 0; - swapped = 0; - /* iterate through all pbuf in chain */ - for(q = p; (q != NULL) && (chksum_len > 0); q = q->next) { - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", - (void *)q, (void *)q->next)); - chklen = q->len; - if (chklen > chksum_len) { - chklen = chksum_len; - } - acc += LWIP_CHKSUM(q->payload, chklen); - chksum_len -= chklen; - LWIP_ASSERT("delete me", chksum_len < 0x7fff); - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ - /* fold the upper bit down */ - acc = FOLD_U32T(acc); - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = SWAP_BYTES_IN_WORD(acc); - } - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ - } - - if (swapped) { - acc = SWAP_BYTES_IN_WORD(acc); - } - acc += (src->addr & 0xffffUL); - acc += ((src->addr >> 16) & 0xffffUL); - acc += (dest->addr & 0xffffUL); - acc += ((dest->addr >> 16) & 0xffffUL); - acc += (u32_t)htons((u16_t)proto); - acc += (u32_t)htons(proto_len); - - /* Fold 32-bit sum to 16 bits - calling this twice is propably faster than if statements... */ - acc = FOLD_U32T(acc); - acc = FOLD_U32T(acc); - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); - return (u16_t)~(acc & 0xffffUL); -} -#endif /* LWIP_UDPLITE */ - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarily for IP - * and ICMP. - * - * @param dataptr start of the buffer to calculate the checksum (no alignment needed) - * @param len length of the buffer to calculate the checksum - * @return checksum (as u16_t) to be saved directly in the protocol header - */ - -u16_t -inet_chksum(void *dataptr, u16_t len) -{ - return ~LWIP_CHKSUM(dataptr, len); -} - -/** - * Calculate a checksum over a chain of pbufs (without pseudo-header, much like - * inet_chksum only pbufs are used). - * - * @param p pbuf chain over that the checksum should be calculated - * @return checksum (as u16_t) to be saved directly in the protocol header - */ -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += LWIP_CHKSUM(q->payload, q->len); - acc = FOLD_U32T(acc); - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = SWAP_BYTES_IN_WORD(acc); - } - } - - if (swapped) { - acc = SWAP_BYTES_IN_WORD(acc); - } - return (u16_t)~(acc & 0xffffUL); -} diff --git a/components/net/lwip-1.3.2/src/core/ipv4/ip.c b/components/net/lwip-1.3.2/src/core/ipv4/ip.c deleted file mode 100644 index b1e98f33ca..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/ip.c +++ /dev/null @@ -1,723 +0,0 @@ -/** - * @file - * This is the IPv4 layer implementation for incoming and outgoing IP traffic. - * - * @see ip_frag.c - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip_frag.h" -#include "lwip/inet.h" -#include "lwip/inet_chksum.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/igmp.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" -#include "lwip/snmp.h" -#include "lwip/dhcp.h" -#include "lwip/stats.h" -#include "arch/perf.h" - -#include - -/** - * The interface that provided the packet for the current callback - * invocation. - */ -struct netif *current_netif; - -/** - * Header of the input packet currently being processed. - */ -const struct ip_hdr *current_header; - -/** - * Finds the appropriate network interface for a given IP address. It - * searches the list of network interfaces linearly. A match is found - * if the masked IP address of the network interface equals the masked - * IP address given to the function. - * - * @param dest the destination IP address for which to find the route - * @return the netif on which to send to reach dest - */ -struct netif * -ip_route(struct ip_addr *dest) -{ - struct netif *netif; - - /* iterate through netifs */ - for(netif = netif_list; netif != NULL; netif = netif->next) { - /* network mask matches? */ - if (netif_is_up(netif)) { - if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { - /* return netif on which to forward IP packet */ - return netif; - } - } - } - if ((netif_default == NULL) || (!netif_is_up(netif_default))) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_route: No route to 0x%"X32_F"\n", dest->addr)); - IP_STATS_INC(ip.rterr); - snmp_inc_ipoutnoroutes(); - return NULL; - } - /* no matching netif found, use default netif */ - return netif_default; -} - -#if IP_FORWARD -/** - * Forwards an IP packet. It finds an appropriate route for the - * packet, decrements the TTL value of the packet, adjusts the - * checksum and outputs the packet on the appropriate interface. - * - * @param p the packet to forward (p->payload points to IP header) - * @param iphdr the IP header of the input packet - * @param inp the netif on which this packet was received - * @return the netif on which the packet was sent (NULL if it wasn't sent) - */ -static struct netif * -ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) -{ - struct netif *netif; - - PERF_START; - /* Find network interface where to forward this IP packet to. */ - netif = ip_route((struct ip_addr *)&(iphdr->dest)); - if (netif == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n", - iphdr->dest.addr)); - snmp_inc_ipoutnoroutes(); - return (struct netif *)NULL; - } - /* Do not forward packets onto the same network interface on which - * they arrived. */ - if (netif == inp) { - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); - snmp_inc_ipoutnoroutes(); - return (struct netif *)NULL; - } - - /* decrement TTL */ - IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); - /* send ICMP if TTL == 0 */ - if (IPH_TTL(iphdr) == 0) { - snmp_inc_ipinhdrerrors(); -#if LWIP_ICMP - /* Don't send ICMP messages in response to ICMP messages */ - if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - } -#endif /* LWIP_ICMP */ - return (struct netif *)NULL; - } - - /* Incrementally update the IP checksum. */ - if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1); - } else { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100)); - } - - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n", - iphdr->dest.addr)); - - IP_STATS_INC(ip.fw); - IP_STATS_INC(ip.xmit); - snmp_inc_ipforwdatagrams(); - - PERF_STOP("ip_forward"); - /* transmit pbuf on chosen interface */ - netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); - return netif; -} -#endif /* IP_FORWARD */ - -/** - * This function is called by the network interface device driver when - * an IP packet is received. The function does the basic checks of the - * IP header such as packet size being at least larger than the header - * size etc. If the packet was not destined for us, the packet is - * forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - * - * @param p the received IP packet (p->payload points to IP header) - * @param inp the netif on which this packet was received - * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't - * processed, but currently always returns ERR_OK) - */ -err_t -ip_input(struct pbuf *p, struct netif *inp) -{ - struct ip_hdr *iphdr; - struct netif *netif; - u16_t iphdr_hlen; - u16_t iphdr_len; -#if LWIP_DHCP - int check_ip_src=1; -#endif /* LWIP_DHCP */ - - IP_STATS_INC(ip.recv); - snmp_inc_ipinreceives(); - - /* identify the IP header */ - iphdr = p->payload; - if (IPH_V(iphdr) != 4) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); - ip_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.err); - IP_STATS_INC(ip.drop); - snmp_inc_ipinhdrerrors(); - return ERR_OK; - } - - /* obtain IP header length in number of 32-bit words */ - iphdr_hlen = IPH_HL(iphdr); - /* calculate IP header length in bytes */ - iphdr_hlen *= 4; - /* obtain ip length in bytes */ - iphdr_len = ntohs(IPH_LEN(iphdr)); - - /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ - if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len)) { - if (iphdr_hlen > p->len) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n", - iphdr_hlen, p->len)); - } - if (iphdr_len > p->tot_len) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", - iphdr_len, p->tot_len)); - } - /* free (drop) packet pbufs */ - pbuf_free(p); - IP_STATS_INC(ip.lenerr); - IP_STATS_INC(ip.drop); - snmp_inc_ipindiscards(); - return ERR_OK; - } - - /* verify checksum */ -#if CHECKSUM_CHECK_IP - if (inet_chksum(iphdr, iphdr_hlen) != 0) { - - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen))); - ip_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.chkerr); - IP_STATS_INC(ip.drop); - snmp_inc_ipinhdrerrors(); - return ERR_OK; - } -#endif - - /* Trim pbuf. This should have been done at the netif layer, - * but we'll do it anyway just to be sure that its done. */ - pbuf_realloc(p, iphdr_len); - - /* match packet against an interface, i.e. is this packet for us? */ -#if LWIP_IGMP - if (ip_addr_ismulticast(&(iphdr->dest))) { - if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, &(iphdr->dest)))) { - netif = inp; - } else { - netif = NULL; - } - } else -#endif /* LWIP_IGMP */ - { - /* start trying with inp. if that's not acceptable, start walking the - list of configured netifs. - 'first' is used as a boolean to mark whether we started walking the list */ - int first = 1; - netif = inp; - do { - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", - iphdr->dest.addr, netif->ip_addr.addr, - iphdr->dest.addr & netif->netmask.addr, - netif->ip_addr.addr & netif->netmask.addr, - iphdr->dest.addr & ~(netif->netmask.addr))); - - /* interface is up and configured? */ - if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) { - /* unicast to this interface address? */ - if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) || - /* or broadcast on this interface network address? */ - ip_addr_isbroadcast(&(iphdr->dest), netif)) { - LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", - netif->name[0], netif->name[1])); - /* break out of for loop */ - break; - } - } - if (first) { - first = 0; - netif = netif_list; - } else { - netif = netif->next; - } - if (netif == inp) { - netif = netif->next; - } - } while(netif != NULL); - } - -#if LWIP_DHCP - /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed - * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. - * According to RFC 1542 section 3.1.1, referred by RFC 2131). - */ - if (netif == NULL) { - /* remote port is DHCP server? */ - if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", - ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen))->dest))); - if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen))->dest) == DHCP_CLIENT_PORT) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: DHCP packet accepted.\n")); - netif = inp; - check_ip_src = 0; - } - } - } -#endif /* LWIP_DHCP */ - - /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */ -#if LWIP_DHCP - /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */ - if (check_ip_src && (iphdr->src.addr != 0)) -#endif /* LWIP_DHCP */ - { if ((ip_addr_isbroadcast(&(iphdr->src), inp)) || - (ip_addr_ismulticast(&(iphdr->src)))) { - /* packet source is not valid */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip_input: packet source is not valid.\n")); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP_STATS_INC(ip.drop); - snmp_inc_ipinaddrerrors(); - snmp_inc_ipindiscards(); - return ERR_OK; - } - } - - /* packet not for us? */ - if (netif == NULL) { - /* packet not for us, route or discard */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: packet not for us.\n")); -#if IP_FORWARD - /* non-broadcast packet? */ - if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) { - /* try to forward IP packet on (other) interfaces */ - ip_forward(p, iphdr, inp); - } else -#endif /* IP_FORWARD */ - { - snmp_inc_ipinaddrerrors(); - snmp_inc_ipindiscards(); - } - pbuf_free(p); - return ERR_OK; - } - /* packet consists of multiple fragments? */ - if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { -#if IP_REASSEMBLY /* packet fragment reassembly code present? */ - LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", - ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); - /* reassemble the packet*/ - p = ip_reass(p); - /* packet not fully reassembled yet? */ - if (p == NULL) { - return ERR_OK; - } - iphdr = p->payload; -#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", - ntohs(IPH_OFFSET(iphdr)))); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - /* unsupported protocol feature */ - snmp_inc_ipinunknownprotos(); - return ERR_OK; -#endif /* IP_REASSEMBLY */ - } - -#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */ - -#if LWIP_IGMP - /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */ - if((iphdr_hlen > IP_HLEN && (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) { -#else - if (iphdr_hlen > IP_HLEN) { -#endif /* LWIP_IGMP */ - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n")); - pbuf_free(p); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - /* unsupported protocol feature */ - snmp_inc_ipinunknownprotos(); - return ERR_OK; - } -#endif /* IP_OPTIONS_ALLOWED == 0 */ - - /* send to upper layers */ - LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); - ip_debug_print(p); - LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); - - current_netif = inp; - current_header = iphdr; - -#if LWIP_RAW - /* raw input did not eat the packet? */ - if (raw_input(p, inp) == 0) -#endif /* LWIP_RAW */ - { - - switch (IPH_PROTO(iphdr)) { -#if LWIP_UDP - case IP_PROTO_UDP: -#if LWIP_UDPLITE - case IP_PROTO_UDPLITE: -#endif /* LWIP_UDPLITE */ - snmp_inc_ipindelivers(); - udp_input(p, inp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case IP_PROTO_TCP: - snmp_inc_ipindelivers(); - tcp_input(p, inp); - break; -#endif /* LWIP_TCP */ -#if LWIP_ICMP - case IP_PROTO_ICMP: - snmp_inc_ipindelivers(); - icmp_input(p, inp); - break; -#endif /* LWIP_ICMP */ -#if LWIP_IGMP - case IP_PROTO_IGMP: - igmp_input(p,inp,&(iphdr->dest)); - break; -#endif /* LWIP_IGMP */ - default: -#if LWIP_ICMP - /* send ICMP destination protocol unreachable unless is was a broadcast */ - if (!ip_addr_isbroadcast(&(iphdr->dest), inp) && - !ip_addr_ismulticast(&(iphdr->dest))) { - p->payload = iphdr; - icmp_dest_unreach(p, ICMP_DUR_PROTO); - } -#endif /* LWIP_ICMP */ - pbuf_free(p); - - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); - - IP_STATS_INC(ip.proterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipinunknownprotos(); - } - } - - current_netif = NULL; - current_header = NULL; - - return ERR_OK; -} - -/** - * Sends an IP packet on a network interface. This function constructs - * the IP header and calculates the IP header checksum. If the source - * IP address is NULL, the IP address of the outgoing network - * interface is filled in as source address. - * If the destination IP address is IP_HDRINCL, p is assumed to already - * include an IP header and p->payload points to it instead of the data. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == IP_HDRINCL, p already includes an IP - header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param tos the TOS value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * @param netif the netif on which to send this packet - * @return ERR_OK if the packet was sent OK - * ERR_BUF if p doesn't have enough space for IP/LINK headers - * returns errors returned by netif->output - * - * @note ip_id: RFC791 "some host may be able to simply use - * unique identifiers independent of destination" - */ -err_t -ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, - u8_t proto, struct netif *netif) -{ -#if IP_OPTIONS_SEND - return ip_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0); -} - -/** - * Same as ip_output_if() but with the possibility to include IP options: - * - * @ param ip_options pointer to the IP options, copied into the IP header - * @ param optlen length of ip_options - */ -err_t ip_output_if_opt(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, - u16_t optlen) -{ -#endif /* IP_OPTIONS_SEND */ - struct ip_hdr *iphdr; - static u16_t ip_id = 0; - - snmp_inc_ipoutrequests(); - - /* Should the IP header be generated or is it already included in p? */ - if (dest != IP_HDRINCL) { - u16_t ip_hlen = IP_HLEN; -#if IP_OPTIONS_SEND - u16_t optlen_aligned = 0; - if (optlen != 0) { - /* round up to a multiple of 4 */ - optlen_aligned = ((optlen + 3) & ~3); - ip_hlen += optlen_aligned; - /* First write in the IP options */ - if (pbuf_header(p, optlen_aligned)) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output_if_opt: not enough room for IP options in pbuf\n")); - IP_STATS_INC(ip.err); - snmp_inc_ipoutdiscards(); - return ERR_BUF; - } - MEMCPY(p->payload, ip_options, optlen); - if (optlen < optlen_aligned) { - /* zero the remaining bytes */ - memset(((char*)p->payload) + optlen, 0, optlen_aligned - optlen); - } - } -#endif /* IP_OPTIONS_SEND */ - /* generate IP header */ - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output: not enough room for IP header in pbuf\n")); - - IP_STATS_INC(ip.err); - snmp_inc_ipoutdiscards(); - return ERR_BUF; - } - - iphdr = p->payload; - LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", - (p->len >= sizeof(struct ip_hdr))); - - IPH_TTL_SET(iphdr, ttl); - IPH_PROTO_SET(iphdr, proto); - - ip_addr_set(&(iphdr->dest), dest); - - IPH_VHLTOS_SET(iphdr, 4, ip_hlen / 4, tos); - IPH_LEN_SET(iphdr, htons(p->tot_len)); - IPH_OFFSET_SET(iphdr, 0); - IPH_ID_SET(iphdr, htons(ip_id)); - ++ip_id; - - if (ip_addr_isany(src)) { - ip_addr_set(&(iphdr->src), &(netif->ip_addr)); - } else { - ip_addr_set(&(iphdr->src), src); - } - - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen)); -#endif - } else { - /* IP header already included in p */ - iphdr = p->payload; - dest = &(iphdr->dest); - } - - IP_STATS_INC(ip.xmit); - - LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); - ip_debug_print(p); - -#if ENABLE_LOOPBACK - if (ip_addr_cmp(dest, &netif->ip_addr)) { - /* Packet to self, enqueue it for loopback */ - LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()")); - return netif_loop_output(netif, p, dest); - } -#endif /* ENABLE_LOOPBACK */ -#if IP_FRAG - /* don't fragment if interface has mtu set to 0 [loopif] */ - if (netif->mtu && (p->tot_len > netif->mtu)) { - return ip_frag(p,netif,dest); - } -#endif - - LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); - return netif->output(netif, p, dest); -} - -/** - * Simple interface to ip_output_if. It finds the outgoing network - * interface and calls upon ip_output_if to do the actual work. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == IP_HDRINCL, p already includes an IP - header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param tos the TOS value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * - * @return ERR_RTE if no route is found - * see ip_output_if() for more return values - */ -err_t -ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto) -{ - struct netif *netif; - - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); - IP_STATS_INC(ip.rterr); - return ERR_RTE; - } - - return ip_output_if(p, src, dest, ttl, tos, proto, netif); -} - -#if LWIP_NETIF_HWADDRHINT -/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint - * before calling ip_output_if. - * - * @param p the packet to send (p->payload points to the data, e.g. next - protocol header; if dest == IP_HDRINCL, p already includes an IP - header and p->payload points to that IP header) - * @param src the source IP address to send from (if src == IP_ADDR_ANY, the - * IP address of the netif used to send is used as source address) - * @param dest the destination IP address to send the packet to - * @param ttl the TTL value to be set in the IP header - * @param tos the TOS value to be set in the IP header - * @param proto the PROTOCOL to be set in the IP header - * @param addr_hint address hint pointer set to netif->addr_hint before - * calling ip_output_if() - * - * @return ERR_RTE if no route is found - * see ip_output_if() for more return values - */ -err_t -ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint) -{ - struct netif *netif; - err_t err; - - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); - IP_STATS_INC(ip.rterr); - return ERR_RTE; - } - - netif->addr_hint = addr_hint; - err = ip_output_if(p, src, dest, ttl, tos, proto, netif); - netif->addr_hint = NULL; - - return err; -} -#endif /* LWIP_NETIF_HWADDRHINT*/ - -#if IP_DEBUG -/* Print an IP header by using LWIP_DEBUGF - * @param p an IP packet, p->payload pointing to the IP header - */ -void -ip_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = p->payload; - u8_t *payload; - - payload = (u8_t *)iphdr + IP_HLEN; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", - IPH_V(iphdr), - IPH_HL(iphdr), - IPH_TOS(iphdr), - ntohs(IPH_LEN(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", - ntohs(IPH_ID(iphdr)), - ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, - ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, - ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, - ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", - IPH_TTL(iphdr), - IPH_PROTO(iphdr), - ntohs(IPH_CHKSUM(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", - ip4_addr1(&iphdr->src), - ip4_addr2(&iphdr->src), - ip4_addr3(&iphdr->src), - ip4_addr4(&iphdr->src))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", - ip4_addr1(&iphdr->dest), - ip4_addr2(&iphdr->dest), - ip4_addr3(&iphdr->dest), - ip4_addr4(&iphdr->dest))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ diff --git a/components/net/lwip-1.3.2/src/core/ipv4/ip_addr.c b/components/net/lwip-1.3.2/src/core/ipv4/ip_addr.c deleted file mode 100644 index 94bf4678a5..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv4/ip_addr.c +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * This is the IPv4 address tools implementation. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" -#include "lwip/ip_addr.h" -#include "lwip/inet.h" -#include "lwip/netif.h" - -#define IP_ADDR_ANY_VALUE 0x00000000UL -#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL - -/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ -const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE }; -const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE }; - -/** - * Determine if an address is a broadcast address on a network interface - * - * @param addr address to be checked - * @param netif the network interface against which the address is checked - * @return returns non-zero if the address is a broadcast address - */ -u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif) -{ - u32_t addr2test; - - addr2test = addr->addr; - /* all ones (broadcast) or all zeroes (old skool broadcast) */ - if ((~addr2test == IP_ADDR_ANY_VALUE) || - (addr2test == IP_ADDR_ANY_VALUE)) - return 1; - /* no broadcast support on this network interface? */ - else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) - /* the given address cannot be a broadcast address - * nor can we check against any broadcast addresses */ - return 0; - /* address matches network interface address exactly? => no broadcast */ - else if (addr2test == netif->ip_addr.addr) - return 0; - /* on the same (sub) network... */ - else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask)) - /* ...and host identifier bits are all ones? =>... */ - && ((addr2test & ~netif->netmask.addr) == - (IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr))) - /* => network broadcast address */ - return 1; - else - return 0; -} diff --git a/components/net/lwip-1.3.2/src/core/ipv6/README b/components/net/lwip-1.3.2/src/core/ipv6/README deleted file mode 100644 index 362000486e..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv6/README +++ /dev/null @@ -1 +0,0 @@ -IPv6 support in lwIP is very experimental. diff --git a/components/net/lwip-1.3.2/src/core/ipv6/icmp6.c b/components/net/lwip-1.3.2/src/core/ipv6/icmp6.c deleted file mode 100644 index 4fcc895511..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv6/icmp6.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include "lwip/opt.h" - -#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/icmp.h" -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/stats.h" - -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; - struct icmp_echo_hdr *iecho; - struct ip_hdr *iphdr; - struct ip_addr tmpaddr; - - ICMP_STATS_INC(icmp.recv); - - /* TODO: check length before accessing payload! */ - - type = ((u8_t *)p->payload)[0]; - - switch (type) { - case ICMP6_ECHO: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - return; - } - iecho = p->payload; - iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN); - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); - ICMP_STATS_INC(icmp.chkerr); - /* return;*/ - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len)); - ip_addr_set(&tmpaddr, &(iphdr->src)); - ip_addr_set(&(iphdr->src), &(iphdr->dest)); - ip_addr_set(&(iphdr->dest), &tmpaddr); - iecho->type = ICMP6_ER; - /* adjust the checksum */ - if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) { - iecho->chksum += htons(ICMP6_ECHO << 8) + 1; - } else { - iecho->chksum += htons(ICMP6_ECHO << 8); - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); - ICMP_STATS_INC(icmp.xmit); - - /* LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ - ip_output_if (p, &(iphdr->src), IP_HDRINCL, - iphdr->hoplim, IP_PROTO_ICMP, inp); - break; - default: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type)); - ICMP_STATS_INC(icmp.proterr); - ICMP_STATS_INC(icmp.drop); - } - - pbuf_free(p); -} - -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_dur_hdr *idur; - - /* @todo: can this be PBUF_LINK instead of PBUF_IP? */ - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - /* ICMP header + IP header + 8 bytes of data */ - if (q == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n")); - pbuf_free(p); - return; - } - LWIP_ASSERT("check that first pbuf can hold icmp message", - (q->len >= (8 + IP_HLEN + 8))); - - iphdr = p->payload; - - idur = q->payload; - idur->type = (u8_t)ICMP6_DUR; - idur->icode = (u8_t)t; - - SMEMCPY((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); - - /* calculate checksum */ - idur->chksum = 0; - idur->chksum = inet_chksum(idur, q->len); - ICMP_STATS_INC(icmp.xmit); - - ip_output(q, NULL, - (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); - pbuf_free(q); -} - -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_te_hdr *tehdr; - - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n")); - - /* @todo: can this be PBUF_LINK instead of PBUF_IP? */ - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - /* ICMP header + IP header + 8 bytes of data */ - if (q == NULL) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n")); - pbuf_free(p); - return; - } - LWIP_ASSERT("check that first pbuf can hold icmp message", - (q->len >= (8 + IP_HLEN + 8))); - - iphdr = p->payload; - - tehdr = q->payload; - tehdr->type = (u8_t)ICMP6_TE; - tehdr->icode = (u8_t)t; - - /* copy fields from original packet */ - SMEMCPY((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); - - /* calculate checksum */ - tehdr->chksum = 0; - tehdr->chksum = inet_chksum(tehdr, q->len); - ICMP_STATS_INC(icmp.xmit); - ip_output(q, NULL, - (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); - pbuf_free(q); -} - -#endif /* LWIP_ICMP */ diff --git a/components/net/lwip-1.3.2/src/core/ipv6/inet6.c b/components/net/lwip-1.3.2/src/core/ipv6/inet6.c deleted file mode 100644 index c3de85c093..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv6/inet6.c +++ /dev/null @@ -1,163 +0,0 @@ -/** - * @file - * Functions common to all TCP/IPv6 modules, such as the Internet checksum and the - * byte order functions. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/inet.h" - -/* chksum: - * - * Sums up all 16 bit words in a memory portion. Also includes any odd byte. - * This function is used by the other checksum functions. - * - * For now, this is not optimized. Must be optimized for the particular processor - * arcitecture on which it is to run. Preferebly coded in assembler. - */ - -static u32_t -chksum(void *dataptr, u16_t len) -{ - u16_t *sdataptr = dataptr; - u32_t acc; - - - for(acc = 0; len > 1; len -= 2) { - acc += *sdataptr++; - } - - /* add up any odd byte */ - if (len == 1) { - acc += htons((u16_t)(*(u8_t *)dataptr) << 8); - } - - return acc; - -} - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - */ - -u16_t -inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u32_t proto_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped, i; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += chksum(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - - for(i = 0; i < 8; i++) { - acc += ((u16_t *)src->addr)[i] & 0xffff; - acc += ((u16_t *)dest->addr)[i] & 0xffff; - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - } - acc += (u16_t)htons((u16_t)proto); - acc += ((u16_t *)&proto_len)[0] & 0xffff; - acc += ((u16_t *)&proto_len)[1] & 0xffff; - - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - return ~(acc & 0xffff); -} - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarely for IP - * and ICMP. - */ - -u16_t -inet_chksum(void *dataptr, u16_t len) -{ - u32_t acc, sum; - - acc = chksum(dataptr, len); - sum = (acc & 0xffff) + (acc >> 16); - sum += (sum >> 16); - return ~(sum & 0xffff); -} - -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += chksum(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8); - } - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - return ~(acc & 0xffff); -} diff --git a/components/net/lwip-1.3.2/src/core/ipv6/ip6.c b/components/net/lwip-1.3.2/src/core/ipv6/ip6.c deleted file mode 100644 index 7e43420011..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv6/ip6.c +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - - -/* ip.c - * - * This is the code for the IP layer for IPv6. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/inet.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" - -/* ip_init: - * - * Initializes the IP layer. - */ - -void -ip_init(void) -{ -} - -/* ip_route: - * - * Finds the appropriate network interface for a given IP address. It searches the - * list of network interfaces linearly. A match is found if the masked IP address of - * the network interface equals the masked IP address given to the function. - */ - -struct netif * -ip_route(struct ip_addr *dest) -{ - struct netif *netif; - - for(netif = netif_list; netif != NULL; netif = netif->next) { - if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { - return netif; - } - } - - return netif_default; -} - -/* ip_forward: - * - * Forwards an IP packet. It finds an appropriate route for the packet, decrements - * the TTL value of the packet, adjusts the checksum and outputs the packet on the - * appropriate interface. - */ - -static void -ip_forward(struct pbuf *p, struct ip_hdr *iphdr) -{ - struct netif *netif; - - PERF_START; - - if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) { - - LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for ")); -#if IP_DEBUG - ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); -#endif /* IP_DEBUG */ - LWIP_DEBUGF(IP_DEBUG, ("\n")); - pbuf_free(p); - return; - } - /* Decrement TTL and send ICMP if ttl == 0. */ - if (--iphdr->hoplim == 0) { -#if LWIP_ICMP - /* Don't send ICMP messages in response to ICMP messages */ - if (iphdr->nexthdr != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - } -#endif /* LWIP_ICMP */ - pbuf_free(p); - return; - } - - /* Incremental update of the IP checksum. */ - /* if (iphdr->chksum >= htons(0xffff - 0x100)) { - iphdr->chksum += htons(0x100) + 1; - } else { - iphdr->chksum += htons(0x100); - }*/ - - - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to ")); -#if IP_DEBUG - ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); -#endif /* IP_DEBUG */ - LWIP_DEBUGF(IP_DEBUG, ("\n")); - - IP_STATS_INC(ip.fw); - IP_STATS_INC(ip.xmit); - - PERF_STOP("ip_forward"); - - netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); -} - -/* ip_input: - * - * This function is called by the network interface device driver when an IP packet is - * received. The function does the basic checks of the IP header such as packet size - * being at least larger than the header size etc. If the packet was not destined for - * us, the packet is forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - */ - -void -ip_input(struct pbuf *p, struct netif *inp) { - struct ip_hdr *iphdr; - struct netif *netif; - - - PERF_START; - -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - - - IP_STATS_INC(ip.recv); - - /* identify the IP header */ - iphdr = p->payload; - - - if (iphdr->v != 6) { - LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n")); -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - pbuf_free(p); - IP_STATS_INC(ip.err); - IP_STATS_INC(ip.drop); - return; - } - - /* is this packet for us? */ - for(netif = netif_list; netif != NULL; netif = netif->next) { -#if IP_DEBUG - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest ")); - ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); - LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr ")); - ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); - LWIP_DEBUGF(IP_DEBUG, ("\n")); -#endif /* IP_DEBUG */ - if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) { - break; - } - } - - - if (netif == NULL) { - /* packet not for us, route or discard */ -#if IP_FORWARD - ip_forward(p, iphdr); -#endif - pbuf_free(p); - return; - } - - pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len)); - - /* send to upper layers */ -#if IP_DEBUG - /* LWIP_DEBUGF("ip_input: \n"); - ip_debug_print(p); - LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ -#endif /* IP_DEBUG */ - - if(pbuf_header(p, -IP_HLEN)) { - LWIP_ASSERT("Can't move over header in packet", 0); - return; - } - - switch (iphdr->nexthdr) { - case IP_PROTO_UDP: - udp_input(p, inp); - break; - case IP_PROTO_TCP: - tcp_input(p, inp); - break; -#if LWIP_ICMP - case IP_PROTO_ICMP: - icmp_input(p, inp); - break; -#endif /* LWIP_ICMP */ - default: -#if LWIP_ICMP - /* send ICMP destination protocol unreachable */ - icmp_dest_unreach(p, ICMP_DUR_PROTO); -#endif /* LWIP_ICMP */ - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n", - iphdr->nexthdr)); - - IP_STATS_INC(ip.proterr); - IP_STATS_INC(ip.drop); - } - PERF_STOP("ip_input"); -} - - -/* ip_output_if: - * - * Sends an IP packet on a network interface. This function constructs the IP header - * and calculates the IP header checksum. If the source IP address is NULL, - * the IP address of the outgoing network interface is filled in as source address. - */ - -err_t -ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, - u8_t proto, struct netif *netif) -{ - struct ip_hdr *iphdr; - - PERF_START; - - LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len)); - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n")); - IP_STATS_INC(ip.err); - - return ERR_BUF; - } - LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len)); - - iphdr = p->payload; - - - if (dest != IP_HDRINCL) { - LWIP_DEBUGF(IP_DEBUG, ("!IP_HDRLINCL\n")); - iphdr->hoplim = ttl; - iphdr->nexthdr = proto; - iphdr->len = htons(p->tot_len - IP_HLEN); - ip_addr_set(&(iphdr->dest), dest); - - iphdr->v = 6; - - if (ip_addr_isany(src)) { - ip_addr_set(&(iphdr->src), &(netif->ip_addr)); - } else { - ip_addr_set(&(iphdr->src), src); - } - - } else { - dest = &(iphdr->dest); - } - - IP_STATS_INC(ip.xmit); - - LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len)); -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - - PERF_STOP("ip_output_if"); - return netif->output(netif, p, dest); -} - -/* ip_output: - * - * Simple interface to ip_output_if. It finds the outgoing network interface and - * calls upon ip_output_if to do the actual work. - */ - -err_t -ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto) -{ - struct netif *netif; - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); - IP_STATS_INC(ip.rterr); - return ERR_RTE; - } - - return ip_output_if (p, src, dest, ttl, proto, netif); -} - -#if LWIP_NETIF_HWADDRHINT -err_t -ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint) -{ - struct netif *netif; - err_t err; - - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); - IP_STATS_INC(ip.rterr); - return ERR_RTE; - } - - netif->addr_hint = addr_hint; - err = ip_output_if(p, src, dest, ttl, tos, proto, netif); - netif->addr_hint = NULL; - - return err; -} -#endif /* LWIP_NETIF_HWADDRHINT*/ - -#if IP_DEBUG -void -ip_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = p->payload; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" | %"X16_F"%"X16_F" | %"X16_F"%"X16_F" | (v, traffic class, flow label)\n", - iphdr->v, - iphdr->tclass1, iphdr->tclass2, - iphdr->flow1, iphdr->flow2)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" | %2"U16_F" | %2"U16_F" | (len, nexthdr, hoplim)\n", - ntohs(iphdr->len), - iphdr->nexthdr, - iphdr->hoplim)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - (ntohl(iphdr->src.addr[0]) >> 16) & 0xffff, - ntohl(iphdr->src.addr[0]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - (ntohl(iphdr->src.addr[1]) >> 16) & 0xffff, - ntohl(iphdr->src.addr[1]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - (ntohl(iphdr->src.addr[2]) >> 16) & 0xffff, - ntohl(iphdr->src.addr[2]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - (ntohl(iphdr->src.addr[3]) >> 16) & 0xffff, - ntohl(iphdr->src.addr[3]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - (ntohl(iphdr->dest.addr[0]) >> 16) & 0xffff, - ntohl(iphdr->dest.addr[0]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - (ntohl(iphdr->dest.addr[1]) >> 16) & 0xffff, - ntohl(iphdr->dest.addr[1]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - (ntohl(iphdr->dest.addr[2]) >> 16) & 0xffff, - ntohl(iphdr->dest.addr[2]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - (ntohl(iphdr->dest.addr[3]) >> 16) & 0xffff, - ntohl(iphdr->dest.addr[3]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ diff --git a/components/net/lwip-1.3.2/src/core/ipv6/ip6_addr.c b/components/net/lwip-1.3.2/src/core/ipv6/ip6_addr.c deleted file mode 100644 index 2da6cea427..0000000000 --- a/components/net/lwip-1.3.2/src/core/ipv6/ip6_addr.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" -#include "lwip/ip_addr.h" -#include "lwip/inet.h" - -u8_t -ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, - struct ip_addr *mask) -{ - return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) && - (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) && - (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) && - (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3])); - -} - -u8_t -ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2) -{ - return(addr1->addr[0] == addr2->addr[0] && - addr1->addr[1] == addr2->addr[1] && - addr1->addr[2] == addr2->addr[2] && - addr1->addr[3] == addr2->addr[3]); -} - -void -ip_addr_set(struct ip_addr *dest, struct ip_addr *src) -{ - SMEMCPY(dest, src, sizeof(struct ip_addr)); - /* dest->addr[0] = src->addr[0]; - dest->addr[1] = src->addr[1]; - dest->addr[2] = src->addr[2]; - dest->addr[3] = src->addr[3];*/ -} - -u8_t -ip_addr_isany(struct ip_addr *addr) -{ - if (addr == NULL) return 1; - return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0); -} diff --git a/components/net/lwip-1.3.2/src/core/mem.c b/components/net/lwip-1.3.2/src/core/mem.c deleted file mode 100644 index 7928e3bf0b..0000000000 --- a/components/net/lwip-1.3.2/src/core/mem.c +++ /dev/null @@ -1,633 +0,0 @@ -/** - * @file - * Dynamic memory manager - * - * This is a lightweight replacement for the standard C library malloc(). - * - * If you want to use the standard C library malloc() instead, define - * MEM_LIBC_MALLOC to 1 in your lwipopts.h - * - * To let mem_malloc() use pools (prevents fragmentation and is much faster than - * a heap but might waste some memory), define MEM_USE_POOLS to 1, define - * MEM_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list - * of pools like this (more pools can be added between _START and _END): - * - * Define three pools with sizes 256, 512, and 1512 bytes - * LWIP_MALLOC_MEMPOOL_START - * LWIP_MALLOC_MEMPOOL(20, 256) - * LWIP_MALLOC_MEMPOOL(10, 512) - * LWIP_MALLOC_MEMPOOL(5, 1512) - * LWIP_MALLOC_MEMPOOL_END - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Simon Goldschmidt - * - */ - -#include "lwip/opt.h" - -#if !MEM_LIBC_MALLOC /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/sys.h" -#include "lwip/stats.h" - -#include - -#if MEM_USE_POOLS -/* lwIP head implemented with different sized pools */ - -/** - * Allocate memory: determine the smallest pool that is big enough - * to contain an element of 'size' and get an element from that pool. - * - * @param size the size in bytes of the memory needed - * @return a pointer to the allocated memory or NULL if the pool is empty - */ -void * -mem_malloc(mem_size_t size) -{ - struct memp_malloc_helper *element; - memp_t poolnr; - mem_size_t required_size = size + sizeof(struct memp_malloc_helper); - - for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr++) { -#if MEM_USE_POOLS_TRY_BIGGER_POOL -again: -#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */ - /* is this pool big enough to hold an element of the required size - plus a struct memp_malloc_helper that saves the pool this element came from? */ - if (required_size <= memp_sizes[poolnr]) { - break; - } - } - if (poolnr > MEMP_POOL_LAST) { - LWIP_ASSERT("mem_malloc(): no pool is that big!", 0); - return NULL; - } - element = (struct memp_malloc_helper*)memp_malloc(poolnr); - if (element == NULL) { - /* No need to DEBUGF or ASSERT: This error is already - taken care of in memp.c */ -#if MEM_USE_POOLS_TRY_BIGGER_POOL - /** Try a bigger pool if this one is empty! */ - if (poolnr < MEMP_POOL_LAST) { - poolnr++; - goto again; - } -#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */ - return NULL; - } - - /* save the pool number this element came from */ - element->poolnr = poolnr; - /* and return a pointer to the memory directly after the struct memp_malloc_helper */ - element++; - - return element; -} - -/** - * Free memory previously allocated by mem_malloc. Loads the pool number - * and calls memp_free with that pool number to put the element back into - * its pool - * - * @param rmem the memory element to free - */ -void -mem_free(void *rmem) -{ - struct memp_malloc_helper *hmem = (struct memp_malloc_helper*)rmem; - - LWIP_ASSERT("rmem != NULL", (rmem != NULL)); - LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem))); - - /* get the original struct memp_malloc_helper */ - hmem--; - - LWIP_ASSERT("hmem != NULL", (hmem != NULL)); - LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem))); - LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX)); - - /* and put it in the pool we saved earlier */ - memp_free(hmem->poolnr, hmem); -} - -#else /* MEM_USE_POOLS */ -/* lwIP replacement for your libc malloc() */ - -/** - * The heap is made up as a list of structs of this type. - * This does not have to be aligned since for getting its size, - * we only use the macro SIZEOF_STRUCT_MEM, which automatically alignes. - */ -struct mem { - /** index (-> ram[next]) of the next struct */ - mem_size_t next; - /** index (-> ram[next]) of the next struct */ - mem_size_t prev; - /** 1: this area is used; 0: this area is unused */ - u8_t used; -}; - -/** All allocated blocks will be MIN_SIZE bytes big, at least! - * MIN_SIZE can be overridden to suit your needs. Smaller values save space, - * larger values could prevent too small blocks to fragment the RAM too much. */ -#ifndef MIN_SIZE -#define MIN_SIZE 12 -#endif /* MIN_SIZE */ -/* some alignment macros: we define them here for better source code layout */ -#define MIN_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MIN_SIZE) -#define SIZEOF_STRUCT_MEM LWIP_MEM_ALIGN_SIZE(sizeof(struct mem)) -#define MEM_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SIZE) - -/** the heap. we need one struct mem at the end and some room for alignment */ -static u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT]; -/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */ -static u8_t *ram; -/** the last entry, always unused! */ -static struct mem *ram_end; -/** pointer to the lowest free block, this is used for faster search */ -static struct mem *lfree; - -/** concurrent access protection */ -static sys_sem_t mem_sem; - -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - -static volatile u8_t mem_free_count; - -/* Allow mem_free from other (e.g. interrupt) context */ -#define LWIP_MEM_FREE_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_free) -#define LWIP_MEM_FREE_PROTECT() SYS_ARCH_PROTECT(lev_free) -#define LWIP_MEM_FREE_UNPROTECT() SYS_ARCH_UNPROTECT(lev_free) -#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc) -#define LWIP_MEM_ALLOC_PROTECT() SYS_ARCH_PROTECT(lev_alloc) -#define LWIP_MEM_ALLOC_UNPROTECT() SYS_ARCH_UNPROTECT(lev_alloc) - -#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - -/* Protect the heap only by using a semaphore */ -#define LWIP_MEM_FREE_DECL_PROTECT() -#define LWIP_MEM_FREE_PROTECT() sys_arch_sem_wait(mem_sem, 0) -#define LWIP_MEM_FREE_UNPROTECT() sys_sem_signal(mem_sem) -/* mem_malloc is protected using semaphore AND LWIP_MEM_ALLOC_PROTECT */ -#define LWIP_MEM_ALLOC_DECL_PROTECT() -#define LWIP_MEM_ALLOC_PROTECT() -#define LWIP_MEM_ALLOC_UNPROTECT() - -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - - -/** - * "Plug holes" by combining adjacent empty struct mems. - * After this function is through, there should not exist - * one empty struct mem pointing to another empty struct mem. - * - * @param mem this points to a struct mem which just has been freed - * @internal this function is only called by mem_free() and mem_realloc() - * - * This assumes access to the heap is protected by the calling function - * already. - */ -static void -plug_holes(struct mem *mem) -{ - struct mem *nmem; - struct mem *pmem; - - LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); - LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); - LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); - - /* plug hole forward */ - LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); - - nmem = (struct mem *)&ram[mem->next]; - if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { - /* if mem->next is unused and not end of ram, combine mem and mem->next */ - if (lfree == nmem) { - lfree = mem; - } - mem->next = nmem->next; - ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram; - } - - /* plug hole backward */ - pmem = (struct mem *)&ram[mem->prev]; - if (pmem != mem && pmem->used == 0) { - /* if mem->prev is unused, combine mem and mem->prev */ - if (lfree == mem) { - lfree = pmem; - } - pmem->next = mem->next; - ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram; - } -} - -/** - * Zero the heap and initialize start, end and lowest-free - */ -void -mem_init(void) -{ - struct mem *mem; - - LWIP_ASSERT("Sanity check alignment", - (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT-1)) == 0); - - /* align the heap */ - ram = LWIP_MEM_ALIGN(ram_heap); - /* initialize the start of the heap */ - mem = (struct mem *)ram; - mem->next = MEM_SIZE_ALIGNED; - mem->prev = 0; - mem->used = 0; - /* initialize the end of the heap */ - ram_end = (struct mem *)&ram[MEM_SIZE_ALIGNED]; - ram_end->used = 1; - ram_end->next = MEM_SIZE_ALIGNED; - ram_end->prev = MEM_SIZE_ALIGNED; - - mem_sem = sys_sem_new(1); - - /* initialize the lowest-free pointer to the start of the heap */ - lfree = (struct mem *)ram; - - MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); -} - -/** - * Put a struct mem back on the heap - * - * @param rmem is the data portion of a struct mem as returned by a previous - * call to mem_malloc() - */ -void -mem_free(void *rmem) -{ - struct mem *mem; - LWIP_MEM_FREE_DECL_PROTECT(); - - if (rmem == NULL) { - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); - return; - } - LWIP_ASSERT("mem_free: sanity check alignment", (((mem_ptr_t)rmem) & (MEM_ALIGNMENT-1)) == 0); - - LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - SYS_ARCH_DECL_PROTECT(lev); - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); - /* protect mem stats from concurrent access */ - SYS_ARCH_PROTECT(lev); - MEM_STATS_INC(illegal); - SYS_ARCH_UNPROTECT(lev); - return; - } - /* protect the heap from concurrent access */ - LWIP_MEM_FREE_PROTECT(); - /* Get the corresponding struct mem ... */ - mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - /* ... which has to be in a used state ... */ - LWIP_ASSERT("mem_free: mem->used", mem->used); - /* ... and is now unused. */ - mem->used = 0; - - if (mem < lfree) { - /* the newly freed struct is now the lowest */ - lfree = mem; - } - - MEM_STATS_DEC_USED(used, mem->next - ((u8_t *)mem - ram)); - - /* finally, see if prev or next are free also */ - plug_holes(mem); -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 1; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_MEM_FREE_UNPROTECT(); -} - -/** - * In contrast to its name, mem_realloc can only shrink memory, not expand it. - * Since the only use (for now) is in pbuf_realloc (which also can only shrink), - * this shouldn't be a problem! - * - * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked - * @param newsize required size after shrinking (needs to be smaller than or - * equal to the previous size) - * @return for compatibility reasons: is always == rmem, at the moment - * or NULL if newsize is > old size, in which case rmem is NOT touched - * or freed! - */ -void * -mem_realloc(void *rmem, mem_size_t newsize) -{ - mem_size_t size; - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; - /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ - LWIP_MEM_FREE_DECL_PROTECT(); - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - newsize = LWIP_MEM_ALIGN_SIZE(newsize); - - if(newsize < MIN_SIZE_ALIGNED) { - /* every data block must be at least MIN_SIZE_ALIGNED long */ - newsize = MIN_SIZE_ALIGNED; - } - - if (newsize > MEM_SIZE_ALIGNED) { - return NULL; - } - - LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - SYS_ARCH_DECL_PROTECT(lev); - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_realloc: illegal memory\n")); - /* protect mem stats from concurrent access */ - SYS_ARCH_PROTECT(lev); - MEM_STATS_INC(illegal); - SYS_ARCH_UNPROTECT(lev); - return rmem; - } - /* Get the corresponding struct mem ... */ - mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - /* ... and its offset pointer */ - ptr = (u8_t *)mem - ram; - - size = mem->next - ptr - SIZEOF_STRUCT_MEM; - LWIP_ASSERT("mem_realloc can only shrink memory", newsize <= size); - if (newsize > size) { - /* not supported */ - return NULL; - } - if (newsize == size) { - /* No change in size, simply return */ - return rmem; - } - - /* protect the heap from concurrent access */ - LWIP_MEM_FREE_PROTECT(); - - MEM_STATS_DEC_USED(used, (size - newsize)); - - mem2 = (struct mem *)&ram[mem->next]; - if(mem2->used == 0) { - /* The next struct is unused, we can simply move it at little */ - mem_size_t next; - /* remember the old next pointer */ - next = mem2->next; - /* create new struct mem which is moved directly after the shrinked mem */ - ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; - if (lfree == mem2) { - lfree = (struct mem *)&ram[ptr2]; - } - mem2 = (struct mem *)&ram[ptr2]; - mem2->used = 0; - /* restore the next pointer */ - mem2->next = next; - /* link it back to mem */ - mem2->prev = ptr; - /* link mem to it */ - mem->next = ptr2; - /* last thing to restore linked list: as we have moved mem2, - * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not - * the end of the heap */ - if (mem2->next != MEM_SIZE_ALIGNED) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - /* no need to plug holes, we've already done that */ - } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { - /* Next struct is used but there's room for another struct mem with - * at least MIN_SIZE_ALIGNED of data. - * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem - * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). - * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty - * region that couldn't hold data, but when mem->next gets freed, - * the 2 regions would be combined, resulting in more free memory */ - ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; - mem2 = (struct mem *)&ram[ptr2]; - if (mem2 < lfree) { - lfree = mem2; - } - mem2->used = 0; - mem2->next = mem->next; - mem2->prev = ptr; - mem->next = ptr2; - if (mem2->next != MEM_SIZE_ALIGNED) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - /* the original mem->next is used, so no need to plug holes! */ - } - /* else { - next struct mem is used but size between mem and mem2 is not big enough - to create another struct mem - -> don't do anyhting. - -> the remaining space stays unused since it is too small - } */ -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 1; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_MEM_FREE_UNPROTECT(); - return rmem; -} - -/** - * Adam's mem_malloc() plus solution for bug #17922 - * Allocate a block of memory with a minimum of 'size' bytes. - * - * @param size is the minimum size of the requested block in bytes. - * @return pointer to allocated memory or NULL if no free memory was found. - * - * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). - */ -void * -mem_malloc(mem_size_t size) -{ - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - u8_t local_mem_free_count = 0; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_MEM_ALLOC_DECL_PROTECT(); - - if (size == 0) { - return NULL; - } - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - size = LWIP_MEM_ALIGN_SIZE(size); - - if(size < MIN_SIZE_ALIGNED) { - /* every data block must be at least MIN_SIZE_ALIGNED long */ - size = MIN_SIZE_ALIGNED; - } - - if (size > MEM_SIZE_ALIGNED) { - return NULL; - } - - /* protect the heap from concurrent access */ - sys_arch_sem_wait(mem_sem, 0); - LWIP_MEM_ALLOC_PROTECT(); -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - /* run as long as a mem_free disturbed mem_malloc */ - do { - local_mem_free_count = 0; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - - /* Scan through the heap searching for a free block that is big enough, - * beginning with the lowest free block. - */ - for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE_ALIGNED - size; - ptr = ((struct mem *)&ram[ptr])->next) { - mem = (struct mem *)&ram[ptr]; -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - mem_free_count = 0; - LWIP_MEM_ALLOC_UNPROTECT(); - /* allow mem_free to run */ - LWIP_MEM_ALLOC_PROTECT(); - if (mem_free_count != 0) { - local_mem_free_count = mem_free_count; - } - mem_free_count = 0; -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - - if ((!mem->used) && - (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { - /* mem is not used and at least perfect fit is possible: - * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ - - if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { - /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing - * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem') - * -> split large block, create empty remainder, - * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if - * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size, - * struct mem would fit in but no data between mem2 and mem2->next - * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty - * region that couldn't hold data, but when mem->next gets freed, - * the 2 regions would be combined, resulting in more free memory - */ - ptr2 = ptr + SIZEOF_STRUCT_MEM + size; - /* create mem2 struct */ - mem2 = (struct mem *)&ram[ptr2]; - mem2->used = 0; - mem2->next = mem->next; - mem2->prev = ptr; - /* and insert it between mem and mem->next */ - mem->next = ptr2; - mem->used = 1; - - if (mem2->next != MEM_SIZE_ALIGNED) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM)); - } else { - /* (a mem2 struct does no fit into the user data space of mem and mem->next will always - * be used at this point: if not we have 2 unused structs in a row, plug_holes should have - * take care of this). - * -> near fit or excact fit: do not split, no mem2 creation - * also can't move mem->next directly behind mem, since mem->next - * will always be used at this point! - */ - mem->used = 1; - MEM_STATS_INC_USED(used, mem->next - ((u8_t *)mem - ram)); - } - - if (mem == lfree) { - /* Find next free block after mem and update lowest free pointer */ - while (lfree->used && lfree != ram_end) { - LWIP_MEM_ALLOC_UNPROTECT(); - /* prevent high interrupt latency... */ - LWIP_MEM_ALLOC_PROTECT(); - lfree = (struct mem *)&ram[lfree->next]; - } - LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); - } - LWIP_MEM_ALLOC_UNPROTECT(); - sys_sem_signal(mem_sem); - LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", - (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); - LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", - ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); - LWIP_ASSERT("mem_malloc: sanity check alignment", - (((mem_ptr_t)mem) & (MEM_ALIGNMENT-1)) == 0); - - return (u8_t *)mem + SIZEOF_STRUCT_MEM; - } - } -#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT - /* if we got interrupted by a mem_free, try again */ - } while(local_mem_free_count != 0); -#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ - LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); - MEM_STATS_INC(err); - LWIP_MEM_ALLOC_UNPROTECT(); - sys_sem_signal(mem_sem); - return NULL; -} - -#endif /* MEM_USE_POOLS */ -/** - * Contiguously allocates enough space for count objects that are size bytes - * of memory each and returns a pointer to the allocated memory. - * - * The allocated memory is filled with bytes of value zero. - * - * @param count number of objects to allocate - * @param size size of the objects to allocate - * @return pointer to allocated memory / NULL pointer if there is an error - */ -void *mem_calloc(mem_size_t count, mem_size_t size) -{ - void *p; - - /* allocate 'count' objects of size 'size' */ - p = mem_malloc(count * size); - if (p) { - /* zero the memory */ - memset(p, 0, count * size); - } - return p; -} - -#endif /* !MEM_LIBC_MALLOC */ diff --git a/components/net/lwip-1.3.2/src/core/memp.c b/components/net/lwip-1.3.2/src/core/memp.c deleted file mode 100644 index a7506a810e..0000000000 --- a/components/net/lwip-1.3.2/src/core/memp.c +++ /dev/null @@ -1,433 +0,0 @@ -/** - * @file - * Dynamic pool memory manager - * - * lwIP has dedicated pools for many structures (netconn, protocol control blocks, - * packet buffers, ...). All these pools are managed here. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/udp.h" -#include "lwip/raw.h" -#include "lwip/tcp.h" -#include "lwip/igmp.h" -#include "lwip/api.h" -#include "lwip/api_msg.h" -#include "lwip/tcpip.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "netif/etharp.h" -#include "lwip/ip_frag.h" - -#include - -#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */ - -struct memp { - struct memp *next; -#if MEMP_OVERFLOW_CHECK - const char *file; - int line; -#endif /* MEMP_OVERFLOW_CHECK */ -}; - -#if MEMP_OVERFLOW_CHECK -/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning - * and at the end of each element, initialize them as 0xcd and check - * them later. */ -/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free, - * every single element in each pool is checked! - * This is VERY SLOW but also very helpful. */ -/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in - * lwipopts.h to change the amount reserved for checking. */ -#ifndef MEMP_SANITY_REGION_BEFORE -#define MEMP_SANITY_REGION_BEFORE 16 -#endif /* MEMP_SANITY_REGION_BEFORE*/ -#if MEMP_SANITY_REGION_BEFORE > 0 -#define MEMP_SANITY_REGION_BEFORE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE) -#else -#define MEMP_SANITY_REGION_BEFORE_ALIGNED 0 -#endif /* MEMP_SANITY_REGION_BEFORE*/ -#ifndef MEMP_SANITY_REGION_AFTER -#define MEMP_SANITY_REGION_AFTER 16 -#endif /* MEMP_SANITY_REGION_AFTER*/ -#if MEMP_SANITY_REGION_AFTER > 0 -#define MEMP_SANITY_REGION_AFTER_ALIGNED LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER) -#else -#define MEMP_SANITY_REGION_AFTER_ALIGNED 0 -#endif /* MEMP_SANITY_REGION_AFTER*/ - -/* MEMP_SIZE: save space for struct memp and for sanity check */ -#define MEMP_SIZE (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED) -#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED) - -#else /* MEMP_OVERFLOW_CHECK */ - -/* No sanity checks - * We don't need to preserve the struct memp while not allocated, so we - * can save a little space and set MEMP_SIZE to 0. - */ -#define MEMP_SIZE 0 -#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x)) - -#endif /* MEMP_OVERFLOW_CHECK */ - -/** This array holds the first free element of each pool. - * Elements form a linked list. */ -static struct memp *memp_tab[MEMP_MAX]; - -#else /* MEMP_MEM_MALLOC */ - -#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x)) - -#endif /* MEMP_MEM_MALLOC */ - -/** This array holds the element sizes of each pool. */ -#if !MEM_USE_POOLS && !MEMP_MEM_MALLOC -static -#endif -const u16_t memp_sizes[MEMP_MAX] = { -#define LWIP_MEMPOOL(name,num,size,desc) LWIP_MEM_ALIGN_SIZE(size), -#include "lwip/memp_std.h" -}; - -/** This array holds a textual description of each pool. */ -#ifdef LWIP_DEBUG -static const char *memp_desc[MEMP_MAX] = { -#define LWIP_MEMPOOL(name,num,size,desc) (desc), -#include "lwip/memp_std.h" -}; -#endif /* LWIP_DEBUG */ - -#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */ - -/** This array holds the number of elements in each pool. */ -static const u16_t memp_num[MEMP_MAX] = { -#define LWIP_MEMPOOL(name,num,size,desc) (num), -#include "lwip/memp_std.h" -}; - -/** This is the actual memory used by the pools. */ -static u8_t memp_memory[MEM_ALIGNMENT - 1 -#define LWIP_MEMPOOL(name,num,size,desc) + ( (num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size) ) ) -#include "lwip/memp_std.h" -]; - -#if MEMP_SANITY_CHECK -/** - * Check that memp-lists don't form a circle - */ -static int -memp_sanity(void) -{ - s16_t i, c; - struct memp *m, *n; - - for (i = 0; i < MEMP_MAX; i++) { - for (m = memp_tab[i]; m != NULL; m = m->next) { - c = 1; - for (n = memp_tab[i]; n != NULL; n = n->next) { - if (n == m && --c < 0) { - return 0; - } - } - } - } - return 1; -} -#endif /* MEMP_SANITY_CHECK*/ -#if MEMP_OVERFLOW_CHECK -/** - * Check if a memp element was victim of an overflow - * (e.g. the restricted area after it has been altered) - * - * @param p the memp element to check - * @param memp_size the element size of the pool p comes from - */ -static void -memp_overflow_check_element(struct memp *p, u16_t memp_size) -{ - u16_t k; - u8_t *m; -#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 - m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED; - for (k = 0; k < MEMP_SANITY_REGION_BEFORE_ALIGNED; k++) { - if (m[k] != 0xcd) { - LWIP_ASSERT("detected memp underflow!", 0); - } - } -#endif -#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0 - m = (u8_t*)p + MEMP_SIZE + memp_size; - for (k = 0; k < MEMP_SANITY_REGION_AFTER_ALIGNED; k++) { - if (m[k] != 0xcd) { - LWIP_ASSERT("detected memp overflow!", 0); - } - } -#endif -} - -/** - * Do an overflow check for all elements in every pool. - * - * @see memp_overflow_check_element for a description of the check - */ -static void -memp_overflow_check_all(void) -{ - u16_t i, j; - struct memp *p; - - p = LWIP_MEM_ALIGN(memp_memory); - for (i = 0; i < MEMP_MAX; ++i) { - p = p; - for (j = 0; j < memp_num[i]; ++j) { - memp_overflow_check_element(p, memp_sizes[i]); - p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED); - } - } -} - -/** - * Initialize the restricted areas of all memp elements in every pool. - */ -static void -memp_overflow_init(void) -{ - u16_t i, j; - struct memp *p; - u8_t *m; - - p = LWIP_MEM_ALIGN(memp_memory); - for (i = 0; i < MEMP_MAX; ++i) { - p = p; - for (j = 0; j < memp_num[i]; ++j) { -#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 - m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED; - memset(m, 0xcd, MEMP_SANITY_REGION_BEFORE_ALIGNED); -#endif -#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0 - m = (u8_t*)p + MEMP_SIZE + memp_sizes[i]; - memset(m, 0xcd, MEMP_SANITY_REGION_AFTER_ALIGNED); -#endif - p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED); - } - } -} -#endif /* MEMP_OVERFLOW_CHECK */ - -/** - * Initialize this module. - * - * Carves out memp_memory into linked lists for each pool-type. - */ -void -memp_init(void) -{ - struct memp *memp; - u16_t i, j; - - for (i = 0; i < MEMP_MAX; ++i) { - MEMP_STATS_AVAIL(used, i, 0); - MEMP_STATS_AVAIL(max, i, 0); - MEMP_STATS_AVAIL(err, i, 0); - MEMP_STATS_AVAIL(avail, i, memp_num[i]); - } - - memp = LWIP_MEM_ALIGN(memp_memory); - /* for every pool: */ - for (i = 0; i < MEMP_MAX; ++i) { - memp_tab[i] = NULL; - /* create a linked list of memp elements */ - for (j = 0; j < memp_num[i]; ++j) { - memp->next = memp_tab[i]; - memp_tab[i] = memp; - memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i] -#if MEMP_OVERFLOW_CHECK - + MEMP_SANITY_REGION_AFTER_ALIGNED -#endif - ); - } - } -#if MEMP_OVERFLOW_CHECK - memp_overflow_init(); - /* check everything a first time to see if it worked */ - memp_overflow_check_all(); -#endif /* MEMP_OVERFLOW_CHECK */ -} -#else -/* fix time-wait tcp pcb issue */ -static rt_uint16_t tcp_pcbs = 0; -#endif /* MEMP_MEM_MALLOC */ - -/** - * Get an element from a specific pool. - * - * @param type the pool to get an element from - * - * the debug version has two more parameters: - * @param file file name calling this function - * @param line number of line where this function is called - * - * @return a pointer to the allocated memory or a NULL pointer on error - */ -void * -#if !MEMP_OVERFLOW_CHECK -memp_malloc(memp_t type) -#else -memp_malloc_fn(memp_t type, const char* file, const int line) -#endif -{ -#if !MEMP_MEM_MALLOC - struct memp *memp; - SYS_ARCH_DECL_PROTECT(old_level); - - LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); - - SYS_ARCH_PROTECT(old_level); -#if MEMP_OVERFLOW_CHECK >= 2 - memp_overflow_check_all(); -#endif /* MEMP_OVERFLOW_CHECK >= 2 */ - - memp = memp_tab[type]; - - if (memp != NULL) { - memp_tab[type] = memp->next; -#if MEMP_OVERFLOW_CHECK - memp->next = NULL; - memp->file = file; - memp->line = line; -#endif /* MEMP_OVERFLOW_CHECK */ - MEMP_STATS_INC_USED(used, type); - LWIP_ASSERT("memp_malloc: memp properly aligned", - ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0); - memp = (struct memp*)((u8_t*)memp + MEMP_SIZE); - } else { - LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", memp_desc[type])); - MEMP_STATS_INC(err, type); - } - SYS_ARCH_UNPROTECT(old_level); - - return memp; -#else - void* ptr; - rt_uint32_t size; - SYS_ARCH_DECL_PROTECT(old_level); - - size = memp_sizes[type]; - LWIP_DEBUGF(MEMP_DEBUG, ("memp malloc %s, size %d, ", memp_desc[type], memp_sizes[type])); - - SYS_ARCH_PROTECT(old_level); - if (type == MEMP_TCP_PCB) - { - if (tcp_pcbs >= MEMP_NUM_TCP_PCB) - { - SYS_ARCH_UNPROTECT(old_level); - return NULL; - } - else - { - /* increased tcp pcb allocated number */ - tcp_pcbs ++; - } - } - SYS_ARCH_UNPROTECT(old_level); - - ptr = mem_malloc(size); - LWIP_DEBUGF(MEMP_DEBUG, ("mem 0x%x\n", ptr)); - - return ptr; -#endif /* MEMP_MEM_MALLOC */ -} - -/** - * Put an element back into its pool. - * - * @param type the pool where to put mem - * @param mem the memp element to free - */ -void -memp_free(memp_t type, void *mem) -{ -#if !MEMP_MEM_MALLOC - struct memp *memp; - SYS_ARCH_DECL_PROTECT(old_level); - - if (mem == NULL) { - return; - } - LWIP_ASSERT("memp_free: mem properly aligned", - ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); - - memp = (struct memp *)((u8_t*)mem - MEMP_SIZE); - - SYS_ARCH_PROTECT(old_level); -#if MEMP_OVERFLOW_CHECK -#if MEMP_OVERFLOW_CHECK >= 2 - memp_overflow_check_all(); -#else - memp_overflow_check_element(memp, memp_sizes[type]); -#endif /* MEMP_OVERFLOW_CHECK >= 2 */ -#endif /* MEMP_OVERFLOW_CHECK */ - - MEMP_STATS_DEC(used, type); - - memp->next = memp_tab[type]; - memp_tab[type] = memp; - -#if MEMP_SANITY_CHECK - LWIP_ASSERT("memp sanity", memp_sanity()); -#endif /* MEMP_SANITY_CHECK */ - - SYS_ARCH_UNPROTECT(old_level); -#else - SYS_ARCH_DECL_PROTECT(old_level); - - SYS_ARCH_PROTECT(old_level); - if (type == MEMP_TCP_PCB && mem) - { - tcp_pcbs --; - } - SYS_ARCH_UNPROTECT(old_level); - - LWIP_DEBUGF(MEMP_DEBUG, ("memp free %s, mem 0x%x\n", memp_desc[type], mem)); - /* release this memory */ - mem_free(mem); -#endif /* MEMP_MEM_MALLOC */ -} - diff --git a/components/net/lwip-1.3.2/src/core/netif.c b/components/net/lwip-1.3.2/src/core/netif.c deleted file mode 100644 index df6b6faf38..0000000000 --- a/components/net/lwip-1.3.2/src/core/netif.c +++ /dev/null @@ -1,685 +0,0 @@ -/** - * @file - * lwIP network interface abstraction - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/tcp.h" -#include "lwip/snmp.h" -#include "lwip/igmp.h" -#include "netif/etharp.h" -#if ENABLE_LOOPBACK -#include "lwip/sys.h" -#if LWIP_NETIF_LOOPBACK_MULTITHREADING -#include "lwip/tcpip.h" -#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ -#endif /* ENABLE_LOOPBACK */ - -#if LWIP_AUTOIP -#include "lwip/autoip.h" -#endif /* LWIP_AUTOIP */ -#if LWIP_DHCP -#include "lwip/dhcp.h" -#endif /* LWIP_DHCP */ - -#if LWIP_NETIF_STATUS_CALLBACK -#define NETIF_STATUS_CALLBACK(n) { if (n->status_callback) (n->status_callback)(n); } -#else -#define NETIF_STATUS_CALLBACK(n) { /* NOP */ } -#endif /* LWIP_NETIF_STATUS_CALLBACK */ - -#if LWIP_NETIF_LINK_CALLBACK -#define NETIF_LINK_CALLBACK(n) { if (n->link_callback) (n->link_callback)(n); } -#else -#define NETIF_LINK_CALLBACK(n) { /* NOP */ } -#endif /* LWIP_NETIF_LINK_CALLBACK */ - -struct netif *netif_list; -struct netif *netif_default; - -/** - * Add a network interface to the list of lwIP netifs. - * - * @param netif a pre-allocated netif structure - * @param ipaddr IP address for the new netif - * @param netmask network mask for the new netif - * @param gw default gateway IP address for the new netif - * @param state opaque data passed to the new netif - * @param init callback function that initializes the interface - * @param input callback function that is called to pass - * ingress packets up in the protocol layer stack. - * - * @return netif, or NULL if failed. - */ -struct netif * -netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) -{ - static u8_t netifnum = 0; - - /* reset new interface configuration state */ - netif->ip_addr.addr = 0; - netif->netmask.addr = 0; - netif->gw.addr = 0; - /* netif->flags = 0; */ - -#if LWIP_DHCP - /* netif not under DHCP control by default */ - netif->dhcp = NULL; -#endif /* LWIP_DHCP */ -#if LWIP_AUTOIP - /* netif not under AutoIP control by default */ - netif->autoip = NULL; -#endif /* LWIP_AUTOIP */ -#if LWIP_NETIF_STATUS_CALLBACK - netif->status_callback = NULL; -#endif /* LWIP_NETIF_STATUS_CALLBACK */ -#if LWIP_NETIF_LINK_CALLBACK - netif->link_callback = NULL; -#endif /* LWIP_NETIF_LINK_CALLBACK */ -#if LWIP_IGMP - netif->igmp_mac_filter = NULL; -#endif /* LWIP_IGMP */ -#if ENABLE_LOOPBACK - netif->loop_first = NULL; - netif->loop_last = NULL; -#endif /* ENABLE_LOOPBACK */ - - /* remember netif specific state information data */ - netif->state = state; - netif->num = netifnum++; - netif->input = input; -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = NULL; -#endif /* LWIP_NETIF_HWADDRHINT*/ -#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS - netif->loop_cnt_current = 0; -#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ - - netif_set_addr(netif, ipaddr, netmask, gw); - - /* call user specified initialization function for netif */ - if (init(netif) != ERR_OK) { - return NULL; - } - - /* add this netif to the list */ - netif->next = netif_list; - netif_list = netif; - snmp_inc_iflist(); - -#if LWIP_IGMP - /* start IGMP processing */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_start( netif); - } -#endif /* LWIP_IGMP */ - - LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ", - netif->name[0], netif->name[1])); - ip_addr_debug_print(NETIF_DEBUG, ipaddr); - LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); - ip_addr_debug_print(NETIF_DEBUG, netmask); - LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); - ip_addr_debug_print(NETIF_DEBUG, gw); - LWIP_DEBUGF(NETIF_DEBUG, ("\n")); - return netif; -} - -/** - * Change IP address configuration for a network interface (including netmask - * and default gateway). - * - * @param netif the network interface to change - * @param ipaddr the new IP address - * @param netmask the new netmask - * @param gw the new default gateway - */ -void -netif_set_addr(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw) -{ - netif_set_ipaddr(netif, ipaddr); - netif_set_netmask(netif, netmask); - netif_set_gw(netif, gw); -} - -/** - * Remove a network interface from the list of lwIP netifs. - * - * @param netif the network interface to remove - */ -void netif_remove(struct netif * netif) -{ - if ( netif == NULL ) return; - -#if LWIP_IGMP - /* stop IGMP processing */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_stop( netif); - } -#endif /* LWIP_IGMP */ - - snmp_delete_ipaddridx_tree(netif); - - /* is it the first netif? */ - if (netif_list == netif) { - netif_list = netif->next; - snmp_dec_iflist(); - } - else { - /* look for netif further down the list */ - struct netif * tmpNetif; - for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) { - if (tmpNetif->next == netif) { - tmpNetif->next = netif->next; - snmp_dec_iflist(); - break; - } - } - if (tmpNetif == NULL) - return; /* we didn't find any netif today */ - } - /* this netif is default? */ - if (netif_default == netif) - /* reset default netif */ - netif_set_default(NULL); - LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); -} - -/** - * Find a network interface by searching for its name - * - * @param name the name of the netif (like netif->name) plus concatenated number - * in ascii representation (e.g. 'en0') - */ -struct netif * -netif_find(char *name) -{ - struct netif *netif; - u8_t num; - - if (name == NULL) { - return NULL; - } - - num = name[2] - '0'; - - for(netif = netif_list; netif != NULL; netif = netif->next) { - if (num == netif->num && - name[0] == netif->name[0] && - name[1] == netif->name[1]) { - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); - return netif; - } - } - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); - return NULL; -} - -/** - * Change the IP address of a network interface - * - * @param netif the network interface to change - * @param ipaddr the new IP address - * - * @note call netif_set_addr() if you also want to change netmask and - * default gateway - */ -void -netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr) -{ - /* TODO: Handling of obsolete pcbs */ - /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */ -#if LWIP_TCP - struct tcp_pcb *pcb; - struct tcp_pcb_listen *lpcb; - - /* address is actually being changed? */ - if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) - { - /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */ - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); - pcb = tcp_active_pcbs; - while (pcb != NULL) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { - /* this connection must be aborted */ - struct tcp_pcb *next = pcb->next; - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); - tcp_abort(pcb); - pcb = next; - } else { - pcb = pcb->next; - } - } - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - /* PCB bound to current local interface address? */ - if ((!(ip_addr_isany(&(lpcb->local_ip)))) && - (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr)))) { - /* The PCB is listening to the old ipaddr and - * is set to listen to the new one instead */ - ip_addr_set(&(lpcb->local_ip), ipaddr); - } - } - } -#endif - snmp_delete_ipaddridx_tree(netif); - snmp_delete_iprteidx_tree(0,netif); - /* set new IP address to netif */ - ip_addr_set(&(netif->ip_addr), ipaddr); - snmp_insert_ipaddridx_tree(netif); - snmp_insert_iprteidx_tree(0,netif); - - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->ip_addr), - ip4_addr2(&netif->ip_addr), - ip4_addr3(&netif->ip_addr), - ip4_addr4(&netif->ip_addr))); -} - -/** - * Change the default gateway for a network interface - * - * @param netif the network interface to change - * @param gw the new default gateway - * - * @note call netif_set_addr() if you also want to change ip address and netmask - */ -void -netif_set_gw(struct netif *netif, struct ip_addr *gw) -{ - ip_addr_set(&(netif->gw), gw); - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->gw), - ip4_addr2(&netif->gw), - ip4_addr3(&netif->gw), - ip4_addr4(&netif->gw))); -} - -/** - * Change the netmask of a network interface - * - * @param netif the network interface to change - * @param netmask the new netmask - * - * @note call netif_set_addr() if you also want to change ip address and - * default gateway - */ -void -netif_set_netmask(struct netif *netif, struct ip_addr *netmask) -{ - snmp_delete_iprteidx_tree(0, netif); - /* set new netmask to netif */ - ip_addr_set(&(netif->netmask), netmask); - snmp_insert_iprteidx_tree(0, netif); - LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->netmask), - ip4_addr2(&netif->netmask), - ip4_addr3(&netif->netmask), - ip4_addr4(&netif->netmask))); -} - -/** - * Set a network interface as the default network interface - * (used to output all packets for which no specific route is found) - * - * @param netif the default network interface - */ -void -netif_set_default(struct netif *netif) -{ - if (netif == NULL) - { - /* remove default route */ - snmp_delete_iprteidx_tree(1, netif); - } - else - { - /* install default route */ - snmp_insert_iprteidx_tree(1, netif); - } - netif_default = netif; - LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", - netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); -} - -/** - * Bring an interface up, available for processing - * traffic. - * - * @note: Enabling DHCP on a down interface will make it come - * up once configured. - * - * @see dhcp_start() - */ -void netif_set_up(struct netif *netif) -{ - if ( !(netif->flags & NETIF_FLAG_UP )) { - netif->flags |= NETIF_FLAG_UP; - -#if LWIP_SNMP - snmp_get_sysuptime(&netif->ts); -#endif /* LWIP_SNMP */ - - NETIF_LINK_CALLBACK(netif); - NETIF_STATUS_CALLBACK(netif); - -#if LWIP_ARP - /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ - if (netif->flags & NETIF_FLAG_ETHARP) { - etharp_gratuitous(netif); - } -#endif /* LWIP_ARP */ - -#if LWIP_IGMP - /* resend IGMP memberships */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_report_groups( netif); - } -#endif /* LWIP_IGMP */ - } -} - -/** - * Bring an interface down, disabling any traffic processing. - * - * @note: Enabling DHCP on a down interface will make it come - * up once configured. - * - * @see dhcp_start() - */ -void netif_set_down(struct netif *netif) -{ - if ( netif->flags & NETIF_FLAG_UP ) - { - netif->flags &= ~NETIF_FLAG_UP; -#if LWIP_SNMP - snmp_get_sysuptime(&netif->ts); -#endif - - NETIF_LINK_CALLBACK(netif); - NETIF_STATUS_CALLBACK(netif); - } -} - -/** - * Ask if an interface is up - */ -u8_t netif_is_up(struct netif *netif) -{ - return (netif->flags & NETIF_FLAG_UP)?1:0; -} - -#if LWIP_NETIF_STATUS_CALLBACK -/** - * Set callback to be called when interface is brought up/down - */ -void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif )) -{ - if ( netif ) - netif->status_callback = status_callback; -} -#endif /* LWIP_NETIF_STATUS_CALLBACK */ - -#if LWIP_NETIF_LINK_CALLBACK -/** - * Called by a driver when its link goes up - */ -void netif_set_link_up(struct netif *netif ) -{ - /* not notify link up anymore */ - if (netif->flags & NETIF_FLAG_LINK_UP) return; - - netif->flags |= NETIF_FLAG_LINK_UP; - -#if LWIP_DHCP - if (netif->dhcp) { - dhcp_network_changed(netif); - } -#endif /* LWIP_DHCP */ - -#if LWIP_AUTOIP - if (netif->autoip) { - autoip_network_changed(netif); - } -#endif /* LWIP_AUTOIP */ - - if (netif->flags & NETIF_FLAG_UP) { -#if LWIP_ARP - /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ - if (netif->flags & NETIF_FLAG_ETHARP) { - etharp_gratuitous(netif); - } -#endif /* LWIP_ARP */ - -#if LWIP_IGMP - /* resend IGMP memberships */ - if (netif->flags & NETIF_FLAG_IGMP) { - igmp_report_groups( netif); - } -#endif /* LWIP_IGMP */ - } - NETIF_LINK_CALLBACK(netif); -} - -/** - * Called by a driver when its link goes down - */ -void netif_set_link_down(struct netif *netif ) -{ - netif->flags &= ~NETIF_FLAG_LINK_UP; - NETIF_LINK_CALLBACK(netif); -} - -/** - * Ask if a link is up - */ -u8_t netif_is_link_up(struct netif *netif) -{ - return (netif->flags & NETIF_FLAG_LINK_UP) ? 1 : 0; -} - -/** - * Set callback to be called when link is brought up/down - */ -void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif )) -{ - if (netif) { - netif->link_callback = link_callback; - } -} -#endif /* LWIP_NETIF_LINK_CALLBACK */ - -#if ENABLE_LOOPBACK -/** - * Send an IP packet to be received on the same netif (loopif-like). - * The pbuf is simply copied and handed back to netif->input. - * In multithreaded mode, this is done directly since netif->input must put - * the packet on a queue. - * In callback mode, the packet is put on an internal queue and is fed to - * netif->input by netif_poll(). - * - * @param netif the lwip network interface structure - * @param p the (IP) packet to 'send' - * @param ipaddr the ip address to send the packet to (not used) - * @return ERR_OK if the packet has been sent - * ERR_MEM if the pbuf used to copy the packet couldn't be allocated - */ -err_t -netif_loop_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr) -{ - struct pbuf *r; - err_t err; - struct pbuf *last; -#if LWIP_LOOPBACK_MAX_PBUFS - u8_t clen = 0; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - SYS_ARCH_DECL_PROTECT(lev); - LWIP_UNUSED_ARG(ipaddr); - - /* Allocate a new pbuf */ - r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); - if (r == NULL) { - return ERR_MEM; - } -#if LWIP_LOOPBACK_MAX_PBUFS - clen = pbuf_clen(r); - /* check for overflow or too many pbuf on queue */ - if(((netif->loop_cnt_current + clen) < netif->loop_cnt_current) || - ((netif->loop_cnt_current + clen) > LWIP_LOOPBACK_MAX_PBUFS)) { - pbuf_free(r); - r = NULL; - return ERR_MEM; - } - netif->loop_cnt_current += clen; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - - /* Copy the whole pbuf queue p into the single pbuf r */ - if ((err = pbuf_copy(r, p)) != ERR_OK) { - pbuf_free(r); - r = NULL; - return err; - } - - /* Put the packet on a linked list which gets emptied through calling - netif_poll(). */ - - /* let last point to the last pbuf in chain r */ - for (last = r; last->next != NULL; last = last->next); - - SYS_ARCH_PROTECT(lev); - if(netif->loop_first != NULL) { - LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL); - netif->loop_last->next = r; - netif->loop_last = last; - } else { - netif->loop_first = r; - netif->loop_last = last; - } - SYS_ARCH_UNPROTECT(lev); - -#if LWIP_NETIF_LOOPBACK_MULTITHREADING - /* For multithreading environment, schedule a call to netif_poll */ - tcpip_callback((void (*)(void *))(netif_poll), netif); -#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ - - return ERR_OK; -} - -/** - * Call netif_poll() in the main loop of your application. This is to prevent - * reentering non-reentrant functions like tcp_input(). Packets passed to - * netif_loop_output() are put on a list that is passed to netif->input() by - * netif_poll(). - */ -void -netif_poll(struct netif *netif) -{ - struct pbuf *in; - SYS_ARCH_DECL_PROTECT(lev); - - do { - /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */ - SYS_ARCH_PROTECT(lev); - in = netif->loop_first; - if(in != NULL) { - struct pbuf *in_end = in; -#if LWIP_LOOPBACK_MAX_PBUFS - u8_t clen = pbuf_clen(in); - /* adjust the number of pbufs on queue */ - LWIP_ASSERT("netif->loop_cnt_current underflow", - ((netif->loop_cnt_current - clen) < netif->loop_cnt_current)); - netif->loop_cnt_current -= clen; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ - while(in_end->len != in_end->tot_len) { - LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL); - in_end = in_end->next; - } - /* 'in_end' now points to the last pbuf from 'in' */ - if(in_end == netif->loop_last) { - /* this was the last pbuf in the list */ - netif->loop_first = netif->loop_last = NULL; - } else { - /* pop the pbuf off the list */ - netif->loop_first = in_end->next; - LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL); - } - /* De-queue the pbuf from its successors on the 'loop_' list. */ - in_end->next = NULL; - } - SYS_ARCH_UNPROTECT(lev); - - if(in != NULL) { - /* loopback packets are always IP packets! */ - if(ip_input(in, netif) != ERR_OK) { - pbuf_free(in); - } - /* Don't reference the packet any more! */ - in = NULL; - } - /* go on while there is a packet on the list */ - } while(netif->loop_first != NULL); -} - -#if !LWIP_NETIF_LOOPBACK_MULTITHREADING -/** - * Calls netif_poll() for every netif on the netif_list. - */ -void -netif_poll_all(void) -{ - struct netif *netif = netif_list; - /* loop through netifs */ - while (netif != NULL) { - netif_poll(netif); - /* proceed to next network interface */ - netif = netif->next; - } -} -#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ -#endif /* ENABLE_LOOPBACK */ diff --git a/components/net/lwip-1.3.2/src/core/pbuf.c b/components/net/lwip-1.3.2/src/core/pbuf.c deleted file mode 100644 index 11cc2e67fd..0000000000 --- a/components/net/lwip-1.3.2/src/core/pbuf.c +++ /dev/null @@ -1,929 +0,0 @@ -/** - * @file - * Packet buffer management - * - * Packets are built from the pbuf data structure. It supports dynamic - * memory allocation for packet contents or can reference externally - * managed packet contents both in RAM and ROM. Quick allocation for - * incoming packets is provided through pools with fixed sized pbufs. - * - * A packet may span over multiple pbufs, chained as a singly linked - * list. This is called a "pbuf chain". - * - * Multiple packets may be queued, also using this singly linked list. - * This is called a "packet queue". - * - * So, a packet queue consists of one or more pbuf chains, each of - * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE - * NOT SUPPORTED!!! Use helper structs to queue multiple packets. - * - * The differences between a pbuf chain and a packet queue are very - * precise but subtle. - * - * The last pbuf of a packet has a ->tot_len field that equals the - * ->len field. It can be found by traversing the list. If the last - * pbuf of a packet has a ->next field other than NULL, more packets - * are on the queue. - * - * Therefore, looping through a pbuf of a single packet, has an - * loop end condition (tot_len == p->len), NOT (next == NULL). - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/stats.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "arch/perf.h" -#if TCP_QUEUE_OOSEQ -#include "lwip/tcp.h" -#endif - -#include - -#define SIZEOF_STRUCT_PBUF LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) -/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically - aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */ -#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE) - -#if !TCP_QUEUE_OOSEQ || NO_SYS -#define PBUF_POOL_IS_EMPTY() -#else /* !TCP_QUEUE_OOSEQ || NO_SYS */ -/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */ -#ifndef PBUF_POOL_FREE_OOSEQ -#define PBUF_POOL_FREE_OOSEQ 1 -#endif /* PBUF_POOL_FREE_OOSEQ */ - -#if PBUF_POOL_FREE_OOSEQ -#include "lwip/tcpip.h" -#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty() -static u8_t pbuf_free_ooseq_queued; -/** - * Attempt to reclaim some memory from queued out-of-sequence TCP segments - * if we run out of pool pbufs. It's better to give priority to new packets - * if we're running out. - * - * This must be done in the correct thread context therefore this function - * can only be used with NO_SYS=0 and through tcpip_callback. - */ -static void -pbuf_free_ooseq(void* arg) -{ - struct tcp_pcb* pcb; - SYS_ARCH_DECL_PROTECT(old_level); - LWIP_UNUSED_ARG(arg); - - SYS_ARCH_PROTECT(old_level); - pbuf_free_ooseq_queued = 0; - SYS_ARCH_UNPROTECT(old_level); - - for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { - if (NULL != pcb->ooseq) { - /** Free the ooseq pbufs of one PCB only */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; - return; - } - } -} - -/** Queue a call to pbuf_free_ooseq if not already queued. */ -static void -pbuf_pool_is_empty(void) -{ - u8_t queued; - SYS_ARCH_DECL_PROTECT(old_level); - - SYS_ARCH_PROTECT(old_level); - queued = pbuf_free_ooseq_queued; - pbuf_free_ooseq_queued = 1; - SYS_ARCH_UNPROTECT(old_level); - - if(!queued) { - /* queue a call to pbuf_free_ooseq if not already queued */ - if(tcpip_callback_with_block(pbuf_free_ooseq, NULL, 0) != ERR_OK) { - SYS_ARCH_PROTECT(old_level); - pbuf_free_ooseq_queued = 0; - SYS_ARCH_UNPROTECT(old_level); - } - } -} -#endif /* PBUF_POOL_FREE_OOSEQ */ -#endif /* !TCP_QUEUE_OOSEQ || NO_SYS */ - -/** - * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). - * - * The actual memory allocated for the pbuf is determined by the - * layer at which the pbuf is allocated and the requested size - * (from the size parameter). - * - * @param layer flag to define header size - * @param length size of the pbuf's payload - * @param type this parameter decides how and where the pbuf - * should be allocated as follows: - * - * - PBUF_RAM: buffer memory for pbuf is allocated as one large - * chunk. This includes protocol headers as well. - * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for - * protocol headers. Additional headers must be prepended - * by allocating another pbuf and chain in to the front of - * the ROM pbuf. It is assumed that the memory used is really - * similar to ROM in that it is immutable and will not be - * changed. Memory which is dynamic should generally not - * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. - * - PBUF_REF: no buffer memory is allocated for the pbuf, even for - * protocol headers. It is assumed that the pbuf is only - * being used in a single thread. If the pbuf gets queued, - * then pbuf_take should be called to copy the buffer. - * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from - * the pbuf pool that is allocated during pbuf_init(). - * - * @return the allocated pbuf. If multiple pbufs where allocated, this - * is the first pbuf of a pbuf chain. - */ -struct pbuf * -pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) -{ - struct pbuf *p, *q, *r; - u16_t offset; - s32_t rem_len; /* remaining length */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); - - /* determine header offset */ - offset = 0; - switch (layer) { - case PBUF_TRANSPORT: - /* add room for transport (often TCP) layer header */ - offset += PBUF_TRANSPORT_HLEN; - /* FALLTHROUGH */ - case PBUF_IP: - /* add room for IP layer header */ - offset += PBUF_IP_HLEN; - /* FALLTHROUGH */ - case PBUF_LINK: - /* add room for link layer header */ - offset += PBUF_LINK_HLEN; - break; - case PBUF_RAW: - break; - default: - LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); - return NULL; - } - - switch (type) { - case PBUF_POOL: - /* allocate head of pbuf chain into p */ - p = memp_malloc(MEMP_PBUF_POOL); - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); - if (p == NULL) { - PBUF_POOL_IS_EMPTY(); - return NULL; - } - p->type = type; - p->next = NULL; - - /* make the payload pointer point 'offset' bytes into pbuf data memory */ - p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset))); - LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - /* the total length of the pbuf chain is the requested size */ - p->tot_len = length; - /* set the length of the first pbuf in the chain */ - p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)); - LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", - ((u8_t*)p->payload + p->len <= - (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); - LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", - (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); - /* set reference count (needed here in case we fail) */ - p->ref = 1; - - /* now allocate the tail of the pbuf chain */ - - /* remember first pbuf for linkage in next iteration */ - r = p; - /* remaining length to be allocated */ - rem_len = length - p->len; - /* any remaining pbufs to be allocated? */ - while (rem_len > 0) { - q = memp_malloc(MEMP_PBUF_POOL); - if (q == NULL) { - PBUF_POOL_IS_EMPTY(); - /* free chain so far allocated */ - pbuf_free(p); - /* bail out unsuccesfully */ - return NULL; - } - q->type = type; - q->flags = 0; - q->next = NULL; - /* make previous pbuf point to this pbuf */ - r->next = q; - /* set total length of this pbuf and next in chain */ - LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff); - q->tot_len = (u16_t)rem_len; - /* this pbuf length is pool size, unless smaller sized tail */ - q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED); - q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF); - LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", - ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); - LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", - ((u8_t*)p->payload + p->len <= - (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); - q->ref = 1; - /* calculate remaining length to be allocated */ - rem_len -= q->len; - /* remember this pbuf for linkage in next iteration */ - r = q; - } - /* end of chain */ - /*r->next = NULL;*/ - - break; - case PBUF_RAM: - /* If pbuf is to be allocated in RAM, allocate memory for it. */ - p = (struct pbuf*)mem_malloc(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length)); - if (p == NULL) { - return NULL; - } - /* Set up internal structure of the pbuf. */ - p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)); - p->len = p->tot_len = length; - p->next = NULL; - p->type = type; - - LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - break; - /* pbuf references existing (non-volatile static constant) ROM payload? */ - case PBUF_ROM: - /* pbuf references existing (externally allocated) RAM payload? */ - case PBUF_REF: - /* only allocate memory for the pbuf structure */ - p = memp_malloc(MEMP_PBUF); - if (p == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", - (type == PBUF_ROM) ? "ROM" : "REF")); - return NULL; - } - /* caller must set this field properly, afterwards */ - p->payload = NULL; - p->len = p->tot_len = length; - p->next = NULL; - p->type = type; - break; - default: - LWIP_ASSERT("pbuf_alloc: erroneous type", 0); - return NULL; - } - /* set reference count */ - p->ref = 1; - /* set flags */ - p->flags = 0; - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); - return p; -} - - -/** - * Shrink a pbuf chain to a desired length. - * - * @param p pbuf to shrink. - * @param new_len desired new length of pbuf chain - * - * Depending on the desired length, the first few pbufs in a chain might - * be skipped and left unchanged. The new last pbuf in the chain will be - * resized, and any remaining pbufs will be freed. - * - * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. - * @note May not be called on a packet queue. - * - * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). - */ -void -pbuf_realloc(struct pbuf *p, u16_t new_len) -{ - struct pbuf *q; - u16_t rem_len; /* remaining length */ - s32_t grow; - - LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); - LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL || - p->type == PBUF_ROM || - p->type == PBUF_RAM || - p->type == PBUF_REF); - - /* desired length larger than current length? */ - if (new_len >= p->tot_len) { - /* enlarging not yet supported */ - return; - } - - /* the pbuf chain grows by (new_len - p->tot_len) bytes - * (which may be negative in case of shrinking) */ - grow = new_len - p->tot_len; - - /* first, step over any pbufs that should remain in the chain */ - rem_len = new_len; - q = p; - /* should this pbuf be kept? */ - while (rem_len > q->len) { - /* decrease remaining length by pbuf length */ - rem_len -= q->len; - /* decrease total length indicator */ - LWIP_ASSERT("grow < max_u16_t", grow < 0xffff); - q->tot_len += (u16_t)grow; - /* proceed to next pbuf in chain */ - q = q->next; - LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); - } - /* we have now reached the new last pbuf (in q) */ - /* rem_len == desired length for pbuf q */ - - /* shrink allocated memory for PBUF_RAM */ - /* (other types merely adjust their length fields */ - if ((q->type == PBUF_RAM) && (rem_len != q->len)) { - /* reallocate and adjust the length of the pbuf that will be split */ - q = mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len); - LWIP_ASSERT("mem_realloc give q == NULL", q != NULL); - } - /* adjust length fields for new last pbuf */ - q->len = rem_len; - q->tot_len = q->len; - - /* any remaining pbufs in chain? */ - if (q->next != NULL) { - /* free remaining pbufs in chain */ - pbuf_free(q->next); - } - /* q is last packet in chain */ - q->next = NULL; - -} - -/** - * Adjusts the payload pointer to hide or reveal headers in the payload. - * - * Adjusts the ->payload pointer so that space for a header - * (dis)appears in the pbuf payload. - * - * The ->payload, ->tot_len and ->len fields are adjusted. - * - * @param p pbuf to change the header size. - * @param header_size_increment Number of bytes to increment header size which - * increases the size of the pbuf. New space is on the front. - * (Using a negative value decreases the header size.) - * If hdr_size_inc is 0, this function does nothing and returns succesful. - * - * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so - * the call will fail. A check is made that the increase in header size does - * not move the payload pointer in front of the start of the buffer. - * @return non-zero on failure, zero on success. - * - */ -u8_t -pbuf_header(struct pbuf *p, s16_t header_size_increment) -{ - u16_t type; - void *payload; - u16_t increment_magnitude; - - LWIP_ASSERT("p != NULL", p != NULL); - if ((header_size_increment == 0) || (p == NULL)) - return 0; - - if (header_size_increment < 0){ - increment_magnitude = -header_size_increment; - /* Check that we aren't going to move off the end of the pbuf */ - LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); - } else { - increment_magnitude = header_size_increment; -#if 0 - /* Can't assert these as some callers speculatively call - pbuf_header() to see if it's OK. Will return 1 below instead. */ - /* Check that we've got the correct type of pbuf to work with */ - LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL", - p->type == PBUF_RAM || p->type == PBUF_POOL); - /* Check that we aren't going to move off the beginning of the pbuf */ - LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF", - (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF); -#endif - } - - type = p->type; - /* remember current payload pointer */ - payload = p->payload; - - /* pbuf types containing payloads? */ - if (type == PBUF_RAM || type == PBUF_POOL) { - /* set new payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - /* boundary check fails? */ - if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { - LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", - (void *)p->payload, (void *)(p + 1))); - /* restore old payload pointer */ - p->payload = payload; - /* bail out unsuccesfully */ - return 1; - } - /* pbuf types refering to external payloads? */ - } else if (type == PBUF_REF || type == PBUF_ROM) { - /* hide a header in the payload? */ - if ((header_size_increment < 0) && (increment_magnitude <= p->len)) { - /* increase payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - } else { - /* cannot expand payload to front (yet!) - * bail out unsuccesfully */ - return 1; - } - } - else { - /* Unknown type */ - LWIP_ASSERT("bad pbuf type", 0); - return 1; - } - /* modify pbuf length fields */ - p->len += header_size_increment; - p->tot_len += header_size_increment; - - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_header: old %p new %p (%"S16_F")\n", - (void *)payload, (void *)p->payload, header_size_increment)); - - return 0; -} - -/** - * Dereference a pbuf chain or queue and deallocate any no-longer-used - * pbufs at the head of this chain or queue. - * - * Decrements the pbuf reference count. If it reaches zero, the pbuf is - * deallocated. - * - * For a pbuf chain, this is repeated for each pbuf in the chain, - * up to the first pbuf which has a non-zero reference count after - * decrementing. So, when all reference counts are one, the whole - * chain is free'd. - * - * @param p The pbuf (chain) to be dereferenced. - * - * @return the number of pbufs that were de-allocated - * from the head of the chain. - * - * @note MUST NOT be called on a packet queue (Not verified to work yet). - * @note the reference counter of a pbuf equals the number of pointers - * that refer to the pbuf (or into the pbuf). - * - * @internal examples: - * - * Assuming existing chains a->b->c with the following reference - * counts, calling pbuf_free(a) results in: - * - * 1->2->3 becomes ...1->3 - * 3->3->3 becomes 2->3->3 - * 1->1->2 becomes ......1 - * 2->1->1 becomes 1->1->1 - * 1->1->1 becomes ....... - * - */ -u8_t -pbuf_free(struct pbuf *p) -{ - u16_t type; - struct pbuf *q; - u8_t count; - - if (p == NULL) { - LWIP_ASSERT("p != NULL", p != NULL); - /* if assertions are disabled, proceed with debug output */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("pbuf_free(p == NULL) was called.\n")); - return 0; - } - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); - - PERF_START; - - LWIP_ASSERT("pbuf_free: sane type", - p->type == PBUF_RAM || p->type == PBUF_ROM || - p->type == PBUF_REF || p->type == PBUF_POOL); - - count = 0; - /* de-allocate all consecutive pbufs from the head of the chain that - * obtain a zero reference count after decrementing*/ - while (p != NULL) { - u16_t ref; - SYS_ARCH_DECL_PROTECT(old_level); - /* Since decrementing ref cannot be guaranteed to be a single machine operation - * we must protect it. We put the new ref into a local variable to prevent - * further protection. */ - SYS_ARCH_PROTECT(old_level); - /* all pbufs in a chain are referenced at least once */ - LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); - /* decrease reference count (number of pointers to pbuf) */ - ref = --(p->ref); - SYS_ARCH_UNPROTECT(old_level); - /* this pbuf is no longer referenced to? */ - if (ref == 0) { - /* remember next pbuf in chain for next iteration */ - q = p->next; - LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); - type = p->type; - /* is this a pbuf from the pool? */ - if (type == PBUF_POOL) { - memp_free(MEMP_PBUF_POOL, p); - /* is this a ROM or RAM referencing pbuf? */ - } else if (type == PBUF_ROM || type == PBUF_REF) { - memp_free(MEMP_PBUF, p); - /* type == PBUF_RAM */ - } else { - mem_free(p); - } - count++; - /* proceed to next pbuf */ - p = q; - /* p->ref > 0, this pbuf is still referenced to */ - /* (and so the remaining pbufs in chain as well) */ - } else { - LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref)); - /* stop walking through the chain */ - p = NULL; - } - } - PERF_STOP("pbuf_free"); - /* return number of de-allocated pbufs */ - return count; -} - -/** - * Count number of pbufs in a chain - * - * @param p first pbuf of chain - * @return the number of pbufs in a chain - */ - -u8_t -pbuf_clen(struct pbuf *p) -{ - u8_t len; - - len = 0; - while (p != NULL) { - ++len; - p = p->next; - } - return len; -} - -/** - * Increment the reference count of the pbuf. - * - * @param p pbuf to increase reference counter of - * - */ -void -pbuf_ref(struct pbuf *p) -{ - SYS_ARCH_DECL_PROTECT(old_level); - /* pbuf given? */ - if (p != NULL) { - SYS_ARCH_PROTECT(old_level); - ++(p->ref); - SYS_ARCH_UNPROTECT(old_level); - } -} - -/** - * Concatenate two pbufs (each may be a pbuf chain) and take over - * the caller's reference of the tail pbuf. - * - * @note The caller MAY NOT reference the tail pbuf afterwards. - * Use pbuf_chain() for that purpose. - * - * @see pbuf_chain() - */ - -void -pbuf_cat(struct pbuf *h, struct pbuf *t) -{ - struct pbuf *p; - - LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", - ((h != NULL) && (t != NULL)), return;); - - /* proceed to last pbuf of chain */ - for (p = h; p->next != NULL; p = p->next) { - /* add total length of second chain to all totals of first chain */ - p->tot_len += t->tot_len; - } - /* { p is last pbuf of first h chain, p->next == NULL } */ - LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); - LWIP_ASSERT("p->next == NULL", p->next == NULL); - /* add total length of second chain to last pbuf total of first chain */ - p->tot_len += t->tot_len; - /* chain last pbuf of head (p) with first of tail (t) */ - p->next = t; - /* p->next now references t, but the caller will drop its reference to t, - * so netto there is no change to the reference count of t. - */ -} - -/** - * Chain two pbufs (or pbuf chains) together. - * - * The caller MUST call pbuf_free(t) once it has stopped - * using it. Use pbuf_cat() instead if you no longer use t. - * - * @param h head pbuf (chain) - * @param t tail pbuf (chain) - * @note The pbufs MUST belong to the same packet. - * @note MAY NOT be called on a packet queue. - * - * The ->tot_len fields of all pbufs of the head chain are adjusted. - * The ->next field of the last pbuf of the head chain is adjusted. - * The ->ref field of the first pbuf of the tail chain is adjusted. - * - */ -void -pbuf_chain(struct pbuf *h, struct pbuf *t) -{ - pbuf_cat(h, t); - /* t is now referenced by h */ - pbuf_ref(t); - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); -} - -/** - * Dechains the first pbuf from its succeeding pbufs in the chain. - * - * Makes p->tot_len field equal to p->len. - * @param p pbuf to dechain - * @return remainder of the pbuf chain, or NULL if it was de-allocated. - * @note May not be called on a packet queue. - */ -struct pbuf * -pbuf_dechain(struct pbuf *p) -{ - struct pbuf *q; - u8_t tail_gone = 1; - /* tail */ - q = p->next; - /* pbuf has successor in chain? */ - if (q != NULL) { - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); - /* enforce invariant if assertion is disabled */ - q->tot_len = p->tot_len - p->len; - /* decouple pbuf from remainder */ - p->next = NULL; - /* total length of pbuf p is its own length only */ - p->tot_len = p->len; - /* q is no longer referenced by p, free it */ - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); - tail_gone = pbuf_free(q); - if (tail_gone > 0) { - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, - ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); - } - /* return remaining tail or NULL if deallocated */ - } - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); - return ((tail_gone > 0) ? NULL : q); -} - -/** - * - * Create PBUF_RAM copies of pbufs. - * - * Used to queue packets on behalf of the lwIP stack, such as - * ARP based queueing. - * - * @note You MUST explicitly use p = pbuf_take(p); - * - * @note Only one packet is copied, no packet queue! - * - * @param p_to pbuf destination of the copy - * @param p_from pbuf source of the copy - * - * @return ERR_OK if pbuf was copied - * ERR_ARG if one of the pbufs is NULL or p_to is not big - * enough to hold p_from - */ -err_t -pbuf_copy(struct pbuf *p_to, struct pbuf *p_from) -{ - u16_t offset_to=0, offset_from=0, len; - - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", - (void*)p_to, (void*)p_from)); - - /* is the target big enough to hold the source? */ - LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && - (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); - - /* iterate through pbuf chain */ - do - { - LWIP_ASSERT("p_to != NULL", p_to != NULL); - /* copy one part of the original chain */ - if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { - /* complete current p_from fits into current p_to */ - len = p_from->len - offset_from; - } else { - /* current p_from does not fit into current p_to */ - len = p_to->len - offset_to; - } - MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len); - offset_to += len; - offset_from += len; - LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); - if (offset_to == p_to->len) { - /* on to next p_to (if any) */ - offset_to = 0; - p_to = p_to->next; - } - LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); - if (offset_from >= p_from->len) { - /* on to next p_from (if any) */ - offset_from = 0; - p_from = p_from->next; - } - - if((p_from != NULL) && (p_from->len == p_from->tot_len)) { - /* don't copy more than one packet! */ - LWIP_ERROR("pbuf_copy() does not allow packet queues!\n", - (p_from->next == NULL), return ERR_VAL;); - } - if((p_to != NULL) && (p_to->len == p_to->tot_len)) { - /* don't copy more than one packet! */ - LWIP_ERROR("pbuf_copy() does not allow packet queues!\n", - (p_to->next == NULL), return ERR_VAL;); - } - } while (p_from); - LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); - return ERR_OK; -} - -/** - * Copy (part of) the contents of a packet buffer - * to an application supplied buffer. - * - * @param buf the pbuf from which to copy data - * @param dataptr the application supplied buffer - * @param len length of data to copy (dataptr must be big enough). No more - * than buf->tot_len will be copied, irrespective of len - * @param offset offset into the packet buffer from where to begin copying len bytes - * @return the number of bytes copied, or 0 on failure - */ -u16_t -pbuf_copy_partial(struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) -{ - struct pbuf *p; - u16_t left; - u16_t buf_copy_len; - u16_t copied_total = 0; - - LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); - LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); - - left = 0; - - if((buf == NULL) || (dataptr == NULL)) { - return 0; - } - - /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ - for(p = buf; len != 0 && p != NULL; p = p->next) { - if ((offset != 0) && (offset >= p->len)) { - /* don't copy from this buffer -> on to the next */ - offset -= p->len; - } else { - /* copy from this buffer. maybe only partially. */ - buf_copy_len = p->len - offset; - if (buf_copy_len > len) - buf_copy_len = len; - /* copy the necessary parts of the buffer */ - MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len); - copied_total += buf_copy_len; - left += buf_copy_len; - len -= buf_copy_len; - offset = 0; - } - } - return copied_total; -} - -/** - * Copy application supplied data into a pbuf. - * This function can only be used to copy the equivalent of buf->tot_len data. - * - * @param buf pbuf to fill with data - * @param dataptr application supplied data buffer - * @param len length of the application supplied data buffer - * - * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough - */ -err_t -pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len) -{ - struct pbuf *p; - u16_t buf_copy_len; - u16_t total_copy_len = len; - u16_t copied_total = 0; - - LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return 0;); - LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return 0;); - - if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) { - return ERR_ARG; - } - - /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ - for(p = buf; total_copy_len != 0; p = p->next) { - LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL); - buf_copy_len = total_copy_len; - if (buf_copy_len > p->len) { - /* this pbuf cannot hold all remaining data */ - buf_copy_len = p->len; - } - /* copy the necessary parts of the buffer */ - MEMCPY(p->payload, &((char*)dataptr)[copied_total], buf_copy_len); - total_copy_len -= buf_copy_len; - copied_total += buf_copy_len; - } - LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len); - return ERR_OK; -} - -/** - * Creates a single pbuf out of a queue of pbufs. - * - * @remark: The source pbuf 'p' is not freed by this function because that can - * be illegal in some places! - * - * @param p the source pbuf - * @param layer pbuf_layer of the new pbuf - * - * @return a new, single pbuf (p->next is NULL) - * or the old pbuf if allocation fails - */ -struct pbuf* -pbuf_coalesce(struct pbuf *p, pbuf_layer layer) -{ - struct pbuf *q; - err_t err; - if (p->next == NULL) { - return p; - } - q = pbuf_alloc(layer, p->tot_len, PBUF_RAM); - if (q == NULL) { - /* @todo: what do we do now? */ - return p; - } - err = pbuf_copy(q, p); - LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); - pbuf_free(p); - return q; -} diff --git a/components/net/lwip-1.3.2/src/core/raw.c b/components/net/lwip-1.3.2/src/core/raw.c deleted file mode 100644 index 2f105fe6bf..0000000000 --- a/components/net/lwip-1.3.2/src/core/raw.c +++ /dev/null @@ -1,353 +0,0 @@ -/** - * @file - * Implementation of raw protocol PCBs for low-level handling of - * different types of protocols besides (or overriding) those - * already available in lwIP. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/raw.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "arch/perf.h" - -#include - -/** The list of RAW PCBs */ -static struct raw_pcb *raw_pcbs; - -/** - * Determine if in incoming IP packet is covered by a RAW PCB - * and if so, pass it to a user-provided receive callback function. - * - * Given an incoming IP datagram (as a chain of pbufs) this function - * finds a corresponding RAW PCB and calls the corresponding receive - * callback function. - * - * @param p pbuf to be demultiplexed to a RAW PCB. - * @param inp network interface on which the datagram was received. - * @return - 1 if the packet has been eaten by a RAW PCB receive - * callback function. The caller MAY NOT not reference the - * packet any longer, and MAY NOT call pbuf_free(). - * @return - 0 if packet is not eaten (pbuf is still referenced by the - * caller). - * - */ -u8_t -raw_input(struct pbuf *p, struct netif *inp) -{ - struct raw_pcb *pcb, *prev; - struct ip_hdr *iphdr; - s16_t proto; - u8_t eaten = 0; - - LWIP_UNUSED_ARG(inp); - - iphdr = p->payload; - proto = IPH_PROTO(iphdr); - - prev = NULL; - pcb = raw_pcbs; - /* loop through all raw pcbs until the packet is eaten by one */ - /* this allows multiple pcbs to match against the packet by design */ - while ((eaten == 0) && (pcb != NULL)) { - if (pcb->protocol == proto) { -#if IP_SOF_BROADCAST_RECV - /* broadcast filter? */ - if ((pcb->so_options & SOF_BROADCAST) || !ip_addr_isbroadcast(&(iphdr->dest), inp)) -#endif /* IP_SOF_BROADCAST_RECV */ - { - /* receive callback function available? */ - if (pcb->recv != NULL) { - /* the receive callback function did not eat the packet? */ - if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) { - /* receive function ate the packet */ - p = NULL; - eaten = 1; - if (prev != NULL) { - /* move the pcb to the front of raw_pcbs so that is - found faster next time */ - prev->next = pcb->next; - pcb->next = raw_pcbs; - raw_pcbs = pcb; - } - } - } - /* no receive callback function was set for this raw PCB */ - } - /* drop the packet */ - } - prev = pcb; - pcb = pcb->next; - } - return eaten; -} - -/** - * Bind a RAW PCB. - * - * @param pcb RAW PCB to be bound with a local address ipaddr. - * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to - * bind to all local interfaces. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_USE. The specified IP address is already bound to by - * another RAW PCB. - * - * @see raw_disconnect() - */ -err_t -raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr) -{ - ip_addr_set(&pcb->local_ip, ipaddr); - return ERR_OK; -} - -/** - * Connect an RAW PCB. This function is required by upper layers - * of lwip. Using the raw api you could use raw_sendto() instead - * - * This will associate the RAW PCB with the remote address. - * - * @param pcb RAW PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * - * @return lwIP error code - * - * @see raw_disconnect() and raw_sendto() - */ -err_t -raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) -{ - ip_addr_set(&pcb->remote_ip, ipaddr); - return ERR_OK; -} - - -/** - * Set the callback function for received packets that match the - * raw PCB's protocol and binding. - * - * The callback function MUST either - * - eat the packet by calling pbuf_free() and returning non-zero. The - * packet will not be passed to other raw PCBs or other protocol layers. - * - not free the packet, and return zero. The packet will be matched - * against further PCBs and/or forwarded to another protocol layers. - * - * @return non-zero if the packet was free()d, zero if the packet remains - * available for others. - */ -void -raw_recv(struct raw_pcb *pcb, - u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, - struct ip_addr *addr), - void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} - -/** - * Send the raw IP packet to the given address. Note that actually you cannot - * modify the IP headers (this is inconsistent with the receive callback where - * you actually get the IP headers), you can only specify the IP payload here. - * It requires some more changes in lwIP. (there will be a raw_send() function - * then.) - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * @param ipaddr the destination address of the IP packet - * - */ -err_t -raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) -{ - err_t err; - struct netif *netif; - struct ip_addr *src_ip; - struct pbuf *q; /* q will be sent down the stack */ - - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n")); - - /* not enough space to add an IP header to first pbuf in given p chain? */ - if (pbuf_header(p, IP_HLEN)) { - /* allocate header in new pbuf */ - q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n")); - return ERR_MEM; - } - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - /* { first pbuf q points to header pbuf } */ - LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - } else { - /* first pbuf q equals given pbuf */ - q = p; - if(pbuf_header(q, -IP_HLEN)) { - LWIP_ASSERT("Can't restore header we just removed!", 0); - return ERR_MEM; - } - } - - if ((netif = ip_route(ipaddr)) == NULL) { - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); - /* free any temporary header pbuf allocated by pbuf_header() */ - if (q != p) { - pbuf_free(q); - } - return ERR_RTE; - } - -#if IP_SOF_BROADCAST - /* broadcast filter? */ - if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(ipaddr, netif) ) { - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); - /* free any temporary header pbuf allocated by pbuf_header() */ - if (q != p) { - pbuf_free(q); - } - return ERR_VAL; - } -#endif /* IP_SOF_BROADCAST */ - - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = &(netif->ip_addr); - } else { - /* use RAW PCB local IP address as source address */ - src_ip = &(pcb->local_ip); - } - -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = &(pcb->addr_hint); -#endif /* LWIP_NETIF_HWADDRHINT*/ - err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = NULL; -#endif /* LWIP_NETIF_HWADDRHINT*/ - - /* did we chain a header earlier? */ - if (q != p) { - /* free the header */ - pbuf_free(q); - } - return err; -} - -/** - * Send the raw IP packet to the address given by raw_connect() - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * - */ -err_t -raw_send(struct raw_pcb *pcb, struct pbuf *p) -{ - return raw_sendto(pcb, p, &pcb->remote_ip); -} - -/** - * Remove an RAW PCB. - * - * @param pcb RAW PCB to be removed. The PCB is removed from the list of - * RAW PCB's and the data structure is freed from memory. - * - * @see raw_new() - */ -void -raw_remove(struct raw_pcb *pcb) -{ - struct raw_pcb *pcb2; - /* pcb to be removed is first in list? */ - if (raw_pcbs == pcb) { - /* make list start at 2nd pcb */ - raw_pcbs = raw_pcbs->next; - /* pcb not 1st in list */ - } else { - for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in raw_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - } - } - } - memp_free(MEMP_RAW_PCB, pcb); -} - -/** - * Create a RAW PCB. - * - * @return The RAW PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) - * - * @see raw_remove() - */ -struct raw_pcb * -raw_new(u8_t proto) { - struct raw_pcb *pcb; - - LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n")); - - pcb = memp_malloc(MEMP_RAW_PCB); - /* could allocate RAW PCB? */ - if (pcb != NULL) { - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct raw_pcb)); - pcb->protocol = proto; - pcb->ttl = RAW_TTL; - pcb->next = raw_pcbs; - raw_pcbs = pcb; - } - return pcb; -} - -#endif /* LWIP_RAW */ diff --git a/components/net/lwip-1.3.2/src/core/snmp/asn1_dec.c b/components/net/lwip-1.3.2/src/core/snmp/asn1_dec.c deleted file mode 100644 index 650fb4037f..0000000000 --- a/components/net/lwip-1.3.2/src/core/snmp/asn1_dec.c +++ /dev/null @@ -1,657 +0,0 @@ -/** - * @file - * Abstract Syntax Notation One (ISO 8824, 8825) decoding - * - * @todo not optimised (yet), favor correctness over speed, favor speed over size - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/snmp_asn1.h" - -/** - * Retrieves type field from incoming pbuf chain. - * - * @param p points to a pbuf holding an ASN1 coded type field - * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field - * @param type return ASN1 type - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode - */ -err_t -snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - *type = *msg_ptr; - return ERR_OK; - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Decodes length field from incoming pbuf chain into host length. - * - * @param p points to a pbuf holding an ASN1 coded length - * @param ofs points to the offset within the pbuf chain of the ASN1 coded length - * @param octets_used returns number of octets used by the length code - * @param length return host order length, upto 64k - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode - */ -err_t -snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - if (*msg_ptr < 0x80) - { - /* primitive definite length format */ - *octets_used = 1; - *length = *msg_ptr; - return ERR_OK; - } - else if (*msg_ptr == 0x80) - { - /* constructed indefinite length format, termination with two zero octets */ - u8_t zeros; - u8_t i; - - *length = 0; - zeros = 0; - while (zeros != 2) - { - i = 2; - while (i > 0) - { - i--; - (*length) += 1; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - if (*msg_ptr == 0) - { - zeros++; - if (zeros == 2) - { - /* stop while (i > 0) */ - i = 0; - } - } - else - { - zeros = 0; - } - } - } - *octets_used = 1; - return ERR_OK; - } - else if (*msg_ptr == 0x81) - { - /* constructed definite length format, one octet */ - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - *length = *msg_ptr; - *octets_used = 2; - return ERR_OK; - } - else if (*msg_ptr == 0x82) - { - u8_t i; - - /* constructed definite length format, two octets */ - i = 2; - while (i > 0) - { - i--; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - if (i == 0) - { - /* least significant length octet */ - *length |= *msg_ptr; - } - else - { - /* most significant length octet */ - *length = (*msg_ptr) << 8; - } - } - *octets_used = 3; - return ERR_OK; - } - else - { - /* constructed definite length format 3..127 octets, this is too big (>64k) */ - /** @todo: do we need to accept inefficient codings with many leading zero's? */ - *octets_used = 1 + ((*msg_ptr) & 0x7f); - return ERR_ARG; - } - } - p = p->next; - } - - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Decodes positive integer (counter, gauge, timeticks) into u32_t. - * - * @param p points to a pbuf holding an ASN1 coded integer - * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer - * @param len length of the coded integer field - * @param value return host order integer - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode - * - * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded - * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value - * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! - */ -err_t -snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - if ((len > 0) && (len < 6)) - { - /* start from zero */ - *value = 0; - if (*msg_ptr & 0x80) - { - /* negative, expecting zero sign bit! */ - return ERR_ARG; - } - else - { - /* positive */ - if ((len > 1) && (*msg_ptr == 0)) - { - /* skip leading "sign byte" octet 0x00 */ - len--; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - } - /* OR octets with value */ - while (len > 1) - { - len--; - *value |= *msg_ptr; - *value <<= 8; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - *value |= *msg_ptr; - return ERR_OK; - } - else - { - return ERR_ARG; - } - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Decodes integer into s32_t. - * - * @param p points to a pbuf holding an ASN1 coded integer - * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer - * @param len length of the coded integer field - * @param value return host order integer - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode - * - * @note ASN coded integers are _always_ signed! - */ -err_t -snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value) -{ - u16_t plen, base; - u8_t *msg_ptr; -#if BYTE_ORDER == LITTLE_ENDIAN - u8_t *lsb_ptr = (u8_t*)value; -#endif -#if BYTE_ORDER == BIG_ENDIAN - u8_t *lsb_ptr = (u8_t*)value + sizeof(s32_t) - 1; -#endif - u8_t sign; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - if ((len > 0) && (len < 5)) - { - if (*msg_ptr & 0x80) - { - /* negative, start from -1 */ - *value = -1; - sign = 1; - } - else - { - /* positive, start from 0 */ - *value = 0; - sign = 0; - } - /* OR/AND octets with value */ - while (len > 1) - { - len--; - if (sign) - { - *lsb_ptr &= *msg_ptr; - *value <<= 8; - *lsb_ptr |= 255; - } - else - { - *lsb_ptr |= *msg_ptr; - *value <<= 8; - } - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - if (sign) - { - *lsb_ptr &= *msg_ptr; - } - else - { - *lsb_ptr |= *msg_ptr; - } - return ERR_OK; - } - else - { - return ERR_ARG; - } - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Decodes object identifier from incoming message into array of s32_t. - * - * @param p points to a pbuf holding an ASN1 coded object identifier - * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier - * @param len length of the coded object identifier - * @param oid return object identifier struct - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode - */ -err_t -snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid) -{ - u16_t plen, base; - u8_t *msg_ptr; - s32_t *oid_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - oid->len = 0; - oid_ptr = &oid->id[0]; - if (len > 0) - { - /* first compressed octet */ - if (*msg_ptr == 0x2B) - { - /* (most) common case 1.3 (iso.org) */ - *oid_ptr = 1; - oid_ptr++; - *oid_ptr = 3; - oid_ptr++; - } - else if (*msg_ptr < 40) - { - *oid_ptr = 0; - oid_ptr++; - *oid_ptr = *msg_ptr; - oid_ptr++; - } - else if (*msg_ptr < 80) - { - *oid_ptr = 1; - oid_ptr++; - *oid_ptr = (*msg_ptr) - 40; - oid_ptr++; - } - else - { - *oid_ptr = 2; - oid_ptr++; - *oid_ptr = (*msg_ptr) - 80; - oid_ptr++; - } - oid->len = 2; - } - else - { - /* accepting zero length identifiers e.g. for - getnext operation. uncommon but valid */ - return ERR_OK; - } - len--; - if (len > 0) - { - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN)) - { - /* sub-identifier uses multiple octets */ - if (*msg_ptr & 0x80) - { - s32_t sub_id = 0; - - while ((*msg_ptr & 0x80) && (len > 1)) - { - len--; - sub_id = (sub_id << 7) + (*msg_ptr & ~0x80); - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - if (!(*msg_ptr & 0x80) && (len > 0)) - { - /* last octet sub-identifier */ - len--; - sub_id = (sub_id << 7) + *msg_ptr; - *oid_ptr = sub_id; - } - } - else - { - /* !(*msg_ptr & 0x80) sub-identifier uses single octet */ - len--; - *oid_ptr = *msg_ptr; - } - if (len > 0) - { - /* remaining oid bytes available ... */ - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - oid_ptr++; - oid->len++; - } - if (len == 0) - { - /* len == 0, end of oid */ - return ERR_OK; - } - else - { - /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */ - return ERR_ARG; - } - - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding) - * from incoming message into array. - * - * @param p points to a pbuf holding an ASN1 coded raw data - * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data - * @param len length of the coded raw data (zero is valid, e.g. empty string!) - * @param raw_len length of the raw return value - * @param raw return raw bytes - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode - */ -err_t -snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw) -{ - u16_t plen, base; - u8_t *msg_ptr; - - if (len > 0) - { - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - if (raw_len >= len) - { - while (len > 1) - { - /* copy len - 1 octets */ - len--; - *raw = *msg_ptr; - raw++; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - /* copy last octet */ - *raw = *msg_ptr; - return ERR_OK; - } - else - { - /* raw_len < len, not enough dst space */ - return ERR_ARG; - } - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; - } - else - { - /* len == 0, empty string */ - return ERR_OK; - } -} - -#endif /* LWIP_SNMP */ diff --git a/components/net/lwip-1.3.2/src/core/snmp/asn1_enc.c b/components/net/lwip-1.3.2/src/core/snmp/asn1_enc.c deleted file mode 100644 index 77af6b4bad..0000000000 --- a/components/net/lwip-1.3.2/src/core/snmp/asn1_enc.c +++ /dev/null @@ -1,611 +0,0 @@ -/** - * @file - * Abstract Syntax Notation One (ISO 8824, 8825) encoding - * - * @todo not optimised (yet), favor correctness over speed, favor speed over size - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/snmp_asn1.h" - -/** - * Returns octet count for length. - * - * @param length - * @param octets_needed points to the return value - */ -void -snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed) -{ - if (length < 0x80U) - { - *octets_needed = 1; - } - else if (length < 0x100U) - { - *octets_needed = 2; - } - else - { - *octets_needed = 3; - } -} - -/** - * Returns octet count for an u32_t. - * - * @param value - * @param octets_needed points to the return value - * - * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded - * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value - * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! - */ -void -snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed) -{ - if (value < 0x80UL) - { - *octets_needed = 1; - } - else if (value < 0x8000UL) - { - *octets_needed = 2; - } - else if (value < 0x800000UL) - { - *octets_needed = 3; - } - else if (value < 0x80000000UL) - { - *octets_needed = 4; - } - else - { - *octets_needed = 5; - } -} - -/** - * Returns octet count for an s32_t. - * - * @param value - * @param octets_needed points to the return value - * - * @note ASN coded integers are _always_ signed. - */ -void -snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed) -{ - if (value < 0) - { - value = ~value; - } - if (value < 0x80L) - { - *octets_needed = 1; - } - else if (value < 0x8000L) - { - *octets_needed = 2; - } - else if (value < 0x800000L) - { - *octets_needed = 3; - } - else - { - *octets_needed = 4; - } -} - -/** - * Returns octet count for an object identifier. - * - * @param ident_len object identifier array length - * @param ident points to object identifier array - * @param octets_needed points to the return value - */ -void -snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed) -{ - s32_t sub_id; - u8_t cnt; - - cnt = 0; - if (ident_len > 1) - { - /* compressed prefix in one octet */ - cnt++; - ident_len -= 2; - ident += 2; - } - while(ident_len > 0) - { - ident_len--; - sub_id = *ident; - - sub_id >>= 7; - cnt++; - while(sub_id > 0) - { - sub_id >>= 7; - cnt++; - } - ident++; - } - *octets_needed = cnt; -} - -/** - * Encodes ASN type field into a pbuf chained ASN1 msg. - * - * @param p points to output pbuf to encode value into - * @param ofs points to the offset within the pbuf chain - * @param type input ASN1 type - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - *msg_ptr = type; - return ERR_OK; - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Encodes host order length field into a pbuf chained ASN1 msg. - * - * @param p points to output pbuf to encode length into - * @param ofs points to the offset within the pbuf chain - * @param length is the host order length to be encoded - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - if (length < 0x80) - { - *msg_ptr = length; - return ERR_OK; - } - else if (length < 0x100) - { - *msg_ptr = 0x81; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - *msg_ptr = length; - return ERR_OK; - } - else - { - u8_t i; - - /* length >= 0x100 && length <= 0xFFFF */ - *msg_ptr = 0x82; - i = 2; - while (i > 0) - { - i--; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - if (i == 0) - { - /* least significant length octet */ - *msg_ptr = length; - } - else - { - /* most significant length octet */ - *msg_ptr = length >> 8; - } - } - return ERR_OK; - } - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg. - * - * @param p points to output pbuf to encode value into - * @param ofs points to the offset within the pbuf chain - * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt()) - * @param value is the host order u32_t value to be encoded - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode - * - * @see snmp_asn1_enc_u32t_cnt() - */ -err_t -snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - if (octets_needed == 5) - { - /* not enough bits in 'value' add leading 0x00 */ - octets_needed--; - *msg_ptr = 0x00; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - while (octets_needed > 1) - { - octets_needed--; - *msg_ptr = value >> (octets_needed << 3); - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - /* (only) one least significant octet */ - *msg_ptr = value; - return ERR_OK; - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Encodes s32_t integer into a pbuf chained ASN1 msg. - * - * @param p points to output pbuf to encode value into - * @param ofs points to the offset within the pbuf chain - * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt()) - * @param value is the host order s32_t value to be encoded - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode - * - * @see snmp_asn1_enc_s32t_cnt() - */ -err_t -snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - while (octets_needed > 1) - { - octets_needed--; - *msg_ptr = value >> (octets_needed << 3); - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - /* (only) one least significant octet */ - *msg_ptr = value; - return ERR_OK; - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Encodes object identifier into a pbuf chained ASN1 msg. - * - * @param p points to output pbuf to encode oid into - * @param ofs points to the offset within the pbuf chain - * @param ident_len object identifier array length - * @param ident points to object identifier array - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - if (ident_len > 1) - { - if ((ident[0] == 1) && (ident[1] == 3)) - { - /* compressed (most common) prefix .iso.org */ - *msg_ptr = 0x2b; - } - else - { - /* calculate prefix */ - *msg_ptr = (ident[0] * 40) + ident[1]; - } - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - ident_len -= 2; - ident += 2; - } - else - { -/* @bug: allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression?? */ - /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */ - return ERR_ARG; - } - while (ident_len > 0) - { - s32_t sub_id; - u8_t shift, tail; - - ident_len--; - sub_id = *ident; - tail = 0; - shift = 28; - while(shift > 0) - { - u8_t code; - - code = sub_id >> shift; - if ((code != 0) || (tail != 0)) - { - tail = 1; - *msg_ptr = code | 0x80; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - shift -= 7; - } - *msg_ptr = (u8_t)sub_id & 0x7F; - if (ident_len > 0) - { - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - /* proceed to next sub-identifier */ - ident++; - } - return ERR_OK; - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -/** - * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg. - * - * @param p points to output pbuf to encode raw data into - * @param ofs points to the offset within the pbuf chain - * @param raw_len raw data length - * @param raw points raw data - * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode - */ -err_t -snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw) -{ - u16_t plen, base; - u8_t *msg_ptr; - - plen = 0; - while (p != NULL) - { - base = plen; - plen += p->len; - if (ofs < plen) - { - msg_ptr = p->payload; - msg_ptr += ofs - base; - - while (raw_len > 1) - { - /* copy raw_len - 1 octets */ - raw_len--; - *msg_ptr = *raw; - raw++; - ofs += 1; - if (ofs >= plen) - { - /* next octet in next pbuf */ - p = p->next; - if (p == NULL) { return ERR_ARG; } - msg_ptr = p->payload; - plen += p->len; - } - else - { - /* next octet in same pbuf */ - msg_ptr++; - } - } - if (raw_len > 0) - { - /* copy last or single octet */ - *msg_ptr = *raw; - } - return ERR_OK; - } - p = p->next; - } - /* p == NULL, ofs >= plen */ - return ERR_ARG; -} - -#endif /* LWIP_SNMP */ diff --git a/components/net/lwip-1.3.2/src/core/snmp/mib2.c b/components/net/lwip-1.3.2/src/core/snmp/mib2.c deleted file mode 100644 index 8520e49415..0000000000 --- a/components/net/lwip-1.3.2/src/core/snmp/mib2.c +++ /dev/null @@ -1,4128 +0,0 @@ -/** - * @file - * Management Information Base II (RFC1213) objects and functions. - * - * @note the object identifiers for this MIB-2 and private MIB tree - * must be kept in sorted ascending order. This to ensure correct getnext operation. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/snmp.h" -#include "lwip/netif.h" -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/tcp.h" -#include "lwip/udp.h" -#include "lwip/snmp_asn1.h" -#include "lwip/snmp_structs.h" -#include "netif/etharp.h" - -/** - * IANA assigned enterprise ID for lwIP is 26381 - * @see http://www.iana.org/assignments/enterprise-numbers - * - * @note this enterprise ID is assigned to the lwIP project, - * all object identifiers living under this ID are assigned - * by the lwIP maintainers (contact Christiaan Simons)! - * @note don't change this define, use snmp_set_sysobjid() - * - * If you need to create your own private MIB you'll need - * to apply for your own enterprise ID with IANA: - * http://www.iana.org/numbers.html - */ -#define SNMP_ENTERPRISE_ID 26381 -#define SNMP_SYSOBJID_LEN 7 -#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID} - -#ifndef SNMP_SYSSERVICES -#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2)) -#endif - -#ifndef SNMP_GET_SYSUPTIME -#define SNMP_GET_SYSUPTIME(sysuptime) -#endif - -static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void system_get_value(struct obj_def *od, u16_t len, void *value); -static u8_t system_set_test(struct obj_def *od, u16_t len, void *value); -static void system_set_value(struct obj_def *od, u16_t len, void *value); -static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void interfaces_get_value(struct obj_def *od, u16_t len, void *value); -static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void ifentry_get_value(struct obj_def *od, u16_t len, void *value); -#if !SNMP_SAFE_REQUESTS -static u8_t ifentry_set_test (struct obj_def *od, u16_t len, void *value); -static void ifentry_set_value (struct obj_def *od, u16_t len, void *value); -#endif /* SNMP_SAFE_REQUESTS */ -static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void atentry_get_value(struct obj_def *od, u16_t len, void *value); -static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void ip_get_value(struct obj_def *od, u16_t len, void *value); -static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value); -static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value); -static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value); -static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value); -static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void icmp_get_value(struct obj_def *od, u16_t len, void *value); -#if LWIP_TCP -static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void tcp_get_value(struct obj_def *od, u16_t len, void *value); -#ifdef THIS_SEEMS_UNUSED -static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value); -#endif -#endif -static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void udp_get_value(struct obj_def *od, u16_t len, void *value); -static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void udpentry_get_value(struct obj_def *od, u16_t len, void *value); -static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -static void snmp_get_value(struct obj_def *od, u16_t len, void *value); -static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value); -static void snmp_set_value(struct obj_def *od, u16_t len, void *value); - - -/* snmp .1.3.6.1.2.1.11 */ -const mib_scalar_node snmp_scalar = { - &snmp_get_object_def, - &snmp_get_value, - &snmp_set_test, - &snmp_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t snmp_ids[28] = { - 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, - 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30 -}; -struct mib_node* const snmp_nodes[28] = { - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, - (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar -}; -const struct mib_array_node snmp = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 28, - snmp_ids, - snmp_nodes -}; - -/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */ -/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */ -/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */ - -/* udp .1.3.6.1.2.1.7 */ -/** index root node for udpTable */ -struct mib_list_rootnode udp_root = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t udpentry_ids[2] = { 1, 2 }; -struct mib_node* const udpentry_nodes[2] = { - (struct mib_node*)&udp_root, (struct mib_node*)&udp_root, -}; -const struct mib_array_node udpentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 2, - udpentry_ids, - udpentry_nodes -}; - -s32_t udptable_id = 1; -struct mib_node* udptable_node = (struct mib_node*)&udpentry; -struct mib_ram_array_node udptable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, - 0, - &udptable_id, - &udptable_node -}; - -const mib_scalar_node udp_scalar = { - &udp_get_object_def, - &udp_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 }; -struct mib_node* const udp_nodes[5] = { - (struct mib_node*)&udp_scalar, (struct mib_node*)&udp_scalar, - (struct mib_node*)&udp_scalar, (struct mib_node*)&udp_scalar, - (struct mib_node*)&udptable -}; -const struct mib_array_node udp = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 5, - udp_ids, - udp_nodes -}; - -/* tcp .1.3.6.1.2.1.6 */ -#if LWIP_TCP -/* only if the TCP protocol is available may implement this group */ -/** index root node for tcpConnTable */ -struct mib_list_rootnode tcpconntree_root = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 }; -struct mib_node* const tcpconnentry_nodes[5] = { - (struct mib_node*)&tcpconntree_root, (struct mib_node*)&tcpconntree_root, - (struct mib_node*)&tcpconntree_root, (struct mib_node*)&tcpconntree_root, - (struct mib_node*)&tcpconntree_root -}; -const struct mib_array_node tcpconnentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 5, - tcpconnentry_ids, - tcpconnentry_nodes -}; - -s32_t tcpconntable_id = 1; -struct mib_node* tcpconntable_node = (struct mib_node*)&tcpconnentry; -struct mib_ram_array_node tcpconntable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, -/** @todo update maxlength when inserting / deleting from table - 0 when table is empty, 1 when more than one entry */ - 0, - &tcpconntable_id, - &tcpconntable_node -}; - -const mib_scalar_node tcp_scalar = { - &tcp_get_object_def, - &tcp_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; -struct mib_node* const tcp_nodes[15] = { - (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcpconntable, (struct mib_node*)&tcp_scalar, - (struct mib_node*)&tcp_scalar -}; -const struct mib_array_node tcp = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 15, - tcp_ids, - tcp_nodes -}; -#endif - -/* icmp .1.3.6.1.2.1.5 */ -const mib_scalar_node icmp_scalar = { - &icmp_get_object_def, - &icmp_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; -struct mib_node* const icmp_nodes[26] = { - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, - (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar -}; -const struct mib_array_node icmp = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 26, - icmp_ids, - icmp_nodes -}; - -/** index root node for ipNetToMediaTable */ -struct mib_list_rootnode ipntomtree_root = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 }; -struct mib_node* const ipntomentry_nodes[4] = { - (struct mib_node*)&ipntomtree_root, (struct mib_node*)&ipntomtree_root, - (struct mib_node*)&ipntomtree_root, (struct mib_node*)&ipntomtree_root -}; -const struct mib_array_node ipntomentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 4, - ipntomentry_ids, - ipntomentry_nodes -}; - -s32_t ipntomtable_id = 1; -struct mib_node* ipntomtable_node = (struct mib_node*)&ipntomentry; -struct mib_ram_array_node ipntomtable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, - 0, - &ipntomtable_id, - &ipntomtable_node -}; - -/** index root node for ipRouteTable */ -struct mib_list_rootnode iprtetree_root = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }; -struct mib_node* const iprteentry_nodes[13] = { - (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, - (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, - (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, - (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, - (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, - (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, - (struct mib_node*)&iprtetree_root -}; -const struct mib_array_node iprteentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 13, - iprteentry_ids, - iprteentry_nodes -}; - -s32_t iprtetable_id = 1; -struct mib_node* iprtetable_node = (struct mib_node*)&iprteentry; -struct mib_ram_array_node iprtetable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, - 0, - &iprtetable_id, - &iprtetable_node -}; - -/** index root node for ipAddrTable */ -struct mib_list_rootnode ipaddrtree_root = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 }; -struct mib_node* const ipaddrentry_nodes[5] = { - (struct mib_node*)&ipaddrtree_root, - (struct mib_node*)&ipaddrtree_root, - (struct mib_node*)&ipaddrtree_root, - (struct mib_node*)&ipaddrtree_root, - (struct mib_node*)&ipaddrtree_root -}; -const struct mib_array_node ipaddrentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 5, - ipaddrentry_ids, - ipaddrentry_nodes -}; - -s32_t ipaddrtable_id = 1; -struct mib_node* ipaddrtable_node = (struct mib_node*)&ipaddrentry; -struct mib_ram_array_node ipaddrtable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, - 0, - &ipaddrtable_id, - &ipaddrtable_node -}; - -/* ip .1.3.6.1.2.1.4 */ -const mib_scalar_node ip_scalar = { - &ip_get_object_def, - &ip_get_value, - &ip_set_test, - &noleafs_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; -struct mib_node* const ip_nodes[23] = { - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, - (struct mib_node*)&ip_scalar, (struct mib_node*)&ipaddrtable, - (struct mib_node*)&iprtetable, (struct mib_node*)&ipntomtable, - (struct mib_node*)&ip_scalar -}; -const struct mib_array_node mib2_ip = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 23, - ip_ids, - ip_nodes -}; - -/** index root node for atTable */ -struct mib_list_rootnode arptree_root = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t atentry_ids[3] = { 1, 2, 3 }; -struct mib_node* const atentry_nodes[3] = { - (struct mib_node*)&arptree_root, - (struct mib_node*)&arptree_root, - (struct mib_node*)&arptree_root -}; -const struct mib_array_node atentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 3, - atentry_ids, - atentry_nodes -}; - -const s32_t attable_id = 1; -struct mib_node* const attable_node = (struct mib_node*)&atentry; -const struct mib_array_node attable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 1, - &attable_id, - &attable_node -}; - -/* at .1.3.6.1.2.1.3 */ -s32_t at_id = 1; -struct mib_node* mib2_at_node = (struct mib_node*)&attable; -struct mib_ram_array_node at = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, - 0, - &at_id, - &mib2_at_node -}; - -/** index root node for ifTable */ -struct mib_list_rootnode iflist_root = { - &ifentry_get_object_def, - &ifentry_get_value, -#if SNMP_SAFE_REQUESTS - &noleafs_set_test, - &noleafs_set_value, -#else /* SNMP_SAFE_REQUESTS */ - &ifentry_set_test, - &ifentry_set_value, -#endif /* SNMP_SAFE_REQUESTS */ - MIB_NODE_LR, - 0, - NULL, - NULL, - 0 -}; -const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }; -struct mib_node* const ifentry_nodes[22] = { - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, - (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root -}; -const struct mib_array_node ifentry = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 22, - ifentry_ids, - ifentry_nodes -}; - -s32_t iftable_id = 1; -struct mib_node* iftable_node = (struct mib_node*)&ifentry; -struct mib_ram_array_node iftable = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_RA, - 0, - &iftable_id, - &iftable_node -}; - -/* interfaces .1.3.6.1.2.1.2 */ -const mib_scalar_node interfaces_scalar = { - &interfaces_get_object_def, - &interfaces_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t interfaces_ids[2] = { 1, 2 }; -struct mib_node* const interfaces_nodes[2] = { - (struct mib_node*)&interfaces_scalar, (struct mib_node*)&iftable -}; -const struct mib_array_node interfaces = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 2, - interfaces_ids, - interfaces_nodes -}; - - -/* 0 1 2 3 4 5 6 */ -/* system .1.3.6.1.2.1.1 */ -const mib_scalar_node sys_tem_scalar = { - &system_get_object_def, - &system_get_value, - &system_set_test, - &system_set_value, - MIB_NODE_SC, - 0 -}; -const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 }; -struct mib_node* const sys_tem_nodes[7] = { - (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar, - (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar, - (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar, - (struct mib_node*)&sys_tem_scalar -}; -/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */ -const struct mib_array_node sys_tem = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 7, - sys_tem_ids, - sys_tem_nodes -}; - -/* mib-2 .1.3.6.1.2.1 */ -#if LWIP_TCP -#define MIB2_GROUPS 8 -#else -#define MIB2_GROUPS 7 -#endif -const s32_t mib2_ids[MIB2_GROUPS] = -{ - 1, - 2, - 3, - 4, - 5, -#if LWIP_TCP - 6, -#endif - 7, - 11 -}; -struct mib_node* const mib2_nodes[MIB2_GROUPS] = { - (struct mib_node*)&sys_tem, - (struct mib_node*)&interfaces, - (struct mib_node*)&at, - (struct mib_node*)&mib2_ip, - (struct mib_node*)&icmp, -#if LWIP_TCP - (struct mib_node*)&tcp, -#endif - (struct mib_node*)&udp, - (struct mib_node*)&snmp -}; - -const struct mib_array_node mib2 = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - MIB2_GROUPS, - mib2_ids, - mib2_nodes -}; - -/* mgmt .1.3.6.1.2 */ -const s32_t mgmt_ids[1] = { 1 }; -struct mib_node* const mgmt_nodes[1] = { (struct mib_node*)&mib2 }; -const struct mib_array_node mgmt = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 1, - mgmt_ids, - mgmt_nodes -}; - -/* internet .1.3.6.1 */ -#if SNMP_PRIVATE_MIB -s32_t internet_ids[2] = { 2, 4 }; -struct mib_node* const internet_nodes[2] = { (struct mib_node*)&mgmt, (struct mib_node*)&mib_private }; -const struct mib_array_node internet = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 2, - internet_ids, - internet_nodes -}; -#else -const s32_t internet_ids[1] = { 2 }; -struct mib_node* const internet_nodes[1] = { (struct mib_node*)&mgmt }; -const struct mib_array_node internet = { - &noleafs_get_object_def, - &noleafs_get_value, - &noleafs_set_test, - &noleafs_set_value, - MIB_NODE_AR, - 1, - internet_ids, - internet_nodes -}; -#endif - -/** mib-2.system.sysObjectID */ -static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID}; -/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */ -static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}}; -/** mib-2.system.sysServices */ -static const s32_t sysservices = SNMP_SYSSERVICES; - -/** mib-2.system.sysDescr */ -static const u8_t sysdescr_len_default = 4; -static const u8_t sysdescr_default[] = "lwIP"; -static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default; -static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0]; -/** mib-2.system.sysContact */ -static const u8_t syscontact_len_default = 0; -static const u8_t syscontact_default[] = ""; -static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default; -static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0]; -/** mib-2.system.sysName */ -static const u8_t sysname_len_default = 8; -static const u8_t sysname_default[] = "FQDN-unk"; -static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default; -static u8_t* sysname_ptr = (u8_t*)&sysname_default[0]; -/** mib-2.system.sysLocation */ -static const u8_t syslocation_len_default = 0; -static const u8_t syslocation_default[] = ""; -static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default; -static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0]; -/** mib-2.snmp.snmpEnableAuthenTraps */ -static const u8_t snmpenableauthentraps_default = 2; /* disabled */ -static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default; - -/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */ -static const struct snmp_obj_id ifspecific = {2, {0, 0}}; -/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */ -static const struct snmp_obj_id iprouteinfo = {2, {0, 0}}; - - - -/* mib-2.system counter(s) */ -static u32_t sysuptime = 0; - -/* mib-2.ip counter(s) */ -static u32_t ipinreceives = 0, - ipinhdrerrors = 0, - ipinaddrerrors = 0, - ipforwdatagrams = 0, - ipinunknownprotos = 0, - ipindiscards = 0, - ipindelivers = 0, - ipoutrequests = 0, - ipoutdiscards = 0, - ipoutnoroutes = 0, - ipreasmreqds = 0, - ipreasmoks = 0, - ipreasmfails = 0, - ipfragoks = 0, - ipfragfails = 0, - ipfragcreates = 0, - iproutingdiscards = 0; -/* mib-2.icmp counter(s) */ -static u32_t icmpinmsgs = 0, - icmpinerrors = 0, - icmpindestunreachs = 0, - icmpintimeexcds = 0, - icmpinparmprobs = 0, - icmpinsrcquenchs = 0, - icmpinredirects = 0, - icmpinechos = 0, - icmpinechoreps = 0, - icmpintimestamps = 0, - icmpintimestampreps = 0, - icmpinaddrmasks = 0, - icmpinaddrmaskreps = 0, - icmpoutmsgs = 0, - icmpouterrors = 0, - icmpoutdestunreachs = 0, - icmpouttimeexcds = 0, - icmpoutparmprobs = 0, - icmpoutsrcquenchs = 0, - icmpoutredirects = 0, - icmpoutechos = 0, - icmpoutechoreps = 0, - icmpouttimestamps = 0, - icmpouttimestampreps = 0, - icmpoutaddrmasks = 0, - icmpoutaddrmaskreps = 0; -/* mib-2.tcp counter(s) */ -static u32_t tcpactiveopens = 0, - tcppassiveopens = 0, - tcpattemptfails = 0, - tcpestabresets = 0, - tcpinsegs = 0, - tcpoutsegs = 0, - tcpretranssegs = 0, - tcpinerrs = 0, - tcpoutrsts = 0; -/* mib-2.udp counter(s) */ -static u32_t udpindatagrams = 0, - udpnoports = 0, - udpinerrors = 0, - udpoutdatagrams = 0; -/* mib-2.snmp counter(s) */ -static u32_t snmpinpkts = 0, - snmpoutpkts = 0, - snmpinbadversions = 0, - snmpinbadcommunitynames = 0, - snmpinbadcommunityuses = 0, - snmpinasnparseerrs = 0, - snmpintoobigs = 0, - snmpinnosuchnames = 0, - snmpinbadvalues = 0, - snmpinreadonlys = 0, - snmpingenerrs = 0, - snmpintotalreqvars = 0, - snmpintotalsetvars = 0, - snmpingetrequests = 0, - snmpingetnexts = 0, - snmpinsetrequests = 0, - snmpingetresponses = 0, - snmpintraps = 0, - snmpouttoobigs = 0, - snmpoutnosuchnames = 0, - snmpoutbadvalues = 0, - snmpoutgenerrs = 0, - snmpoutgetrequests = 0, - snmpoutgetnexts = 0, - snmpoutsetrequests = 0, - snmpoutgetresponses = 0, - snmpouttraps = 0; - - - -/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */ -/** - * Copy octet string. - * - * @param dst points to destination - * @param src points to source - * @param n number of octets to copy. - */ -void ocstrncpy(u8_t *dst, u8_t *src, u8_t n) -{ - while (n > 0) - { - n--; - *dst++ = *src++; - } -} - -/** - * Copy object identifier (s32_t) array. - * - * @param dst points to destination - * @param src points to source - * @param n number of sub identifiers to copy. - */ -void objectidncpy(s32_t *dst, s32_t *src, u8_t n) -{ - while(n > 0) - { - n--; - *dst++ = *src++; - } -} - -/** - * Initializes sysDescr pointers. - * - * @param str if non-NULL then copy str pointer - * @param len points to string length, excluding zero terminator - */ -void snmp_set_sysdesr(u8_t *str, u8_t *len) -{ - if (str != NULL) - { - sysdescr_ptr = str; - sysdescr_len_ptr = len; - } -} - -void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid) -{ - *oid = &sysobjid; -} - -/** - * Initializes sysObjectID value. - * - * @param oid points to stuct snmp_obj_id to copy - */ -void snmp_set_sysobjid(struct snmp_obj_id *oid) -{ - sysobjid = *oid; -} - -/** - * Must be called at regular 10 msec interval from a timer interrupt - * or signal handler depending on your runtime environment. - */ -void snmp_inc_sysuptime(void) -{ - sysuptime++; -} - -void snmp_add_sysuptime(u32_t value) -{ - sysuptime+=value; -} - -void snmp_get_sysuptime(u32_t *value) -{ - SNMP_GET_SYSUPTIME(sysuptime); - *value = sysuptime; -} - -/** - * Initializes sysContact pointers, - * e.g. ptrs to non-volatile memory external to lwIP. - * - * @param ocstr if non-NULL then copy str pointer - * @param ocstrlen points to string length, excluding zero terminator - */ -void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen) -{ - if (ocstr != NULL) - { - syscontact_ptr = ocstr; - syscontact_len_ptr = ocstrlen; - } -} - -/** - * Initializes sysName pointers, - * e.g. ptrs to non-volatile memory external to lwIP. - * - * @param ocstr if non-NULL then copy str pointer - * @param ocstrlen points to string length, excluding zero terminator - */ -void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen) -{ - if (ocstr != NULL) - { - sysname_ptr = ocstr; - sysname_len_ptr = ocstrlen; - } -} - -/** - * Initializes sysLocation pointers, - * e.g. ptrs to non-volatile memory external to lwIP. - * - * @param ocstr if non-NULL then copy str pointer - * @param ocstrlen points to string length, excluding zero terminator - */ -void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen) -{ - if (ocstr != NULL) - { - syslocation_ptr = ocstr; - syslocation_len_ptr = ocstrlen; - } -} - - -void snmp_add_ifinoctets(struct netif *ni, u32_t value) -{ - ni->ifinoctets += value; -} - -void snmp_inc_ifinucastpkts(struct netif *ni) -{ - (ni->ifinucastpkts)++; -} - -void snmp_inc_ifinnucastpkts(struct netif *ni) -{ - (ni->ifinnucastpkts)++; -} - -void snmp_inc_ifindiscards(struct netif *ni) -{ - (ni->ifindiscards)++; -} - -void snmp_add_ifoutoctets(struct netif *ni, u32_t value) -{ - ni->ifoutoctets += value; -} - -void snmp_inc_ifoutucastpkts(struct netif *ni) -{ - (ni->ifoutucastpkts)++; -} - -void snmp_inc_ifoutnucastpkts(struct netif *ni) -{ - (ni->ifoutnucastpkts)++; -} - -void snmp_inc_ifoutdiscards(struct netif *ni) -{ - (ni->ifoutdiscards)++; -} - -void snmp_inc_iflist(void) -{ - struct mib_list_node *if_node = NULL; - - snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node); - /* enable getnext traversal on filled table */ - iftable.maxlength = 1; -} - -void snmp_dec_iflist(void) -{ - snmp_mib_node_delete(&iflist_root, iflist_root.tail); - /* disable getnext traversal on empty table */ - if(iflist_root.count == 0) iftable.maxlength = 0; -} - -/** - * Inserts ARP table indexes (.xIfIndex.xNetAddress) - * into arp table index trees (both atTable and ipNetToMediaTable). - */ -void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip) -{ - struct mib_list_rootnode *at_rn; - struct mib_list_node *at_node; - struct ip_addr hip; - s32_t arpidx[5]; - u8_t level, tree; - - LWIP_ASSERT("ni != NULL", ni != NULL); - snmp_netiftoifindex(ni, &arpidx[0]); - hip.addr = ntohl(ip->addr); - snmp_iptooid(&hip, &arpidx[1]); - - for (tree = 0; tree < 2; tree++) - { - if (tree == 0) - { - at_rn = &arptree_root; - } - else - { - at_rn = &ipntomtree_root; - } - for (level = 0; level < 5; level++) - { - at_node = NULL; - snmp_mib_node_insert(at_rn, arpidx[level], &at_node); - if ((level != 4) && (at_node != NULL)) - { - if (at_node->nptr == NULL) - { - at_rn = snmp_mib_lrn_alloc(); - at_node->nptr = (struct mib_node*)at_rn; - if (at_rn != NULL) - { - if (level == 3) - { - if (tree == 0) - { - at_rn->get_object_def = atentry_get_object_def; - at_rn->get_value = atentry_get_value; - } - else - { - at_rn->get_object_def = ip_ntomentry_get_object_def; - at_rn->get_value = ip_ntomentry_get_value; - } - at_rn->set_test = noleafs_set_test; - at_rn->set_value = noleafs_set_value; - } - } - else - { - /* at_rn == NULL, malloc failure */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full")); - break; - } - } - else - { - at_rn = (struct mib_list_rootnode*)at_node->nptr; - } - } - } - } - /* enable getnext traversal on filled tables */ - at.maxlength = 1; - ipntomtable.maxlength = 1; -} - -/** - * Removes ARP table indexes (.xIfIndex.xNetAddress) - * from arp table index trees. - */ -void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip) -{ - struct mib_list_rootnode *at_rn, *next, *del_rn[5]; - struct mib_list_node *at_n, *del_n[5]; - struct ip_addr hip; - s32_t arpidx[5]; - u8_t fc, tree, level, del_cnt; - - snmp_netiftoifindex(ni, &arpidx[0]); - hip.addr = ntohl(ip->addr); - snmp_iptooid(&hip, &arpidx[1]); - - for (tree = 0; tree < 2; tree++) - { - /* mark nodes for deletion */ - if (tree == 0) - { - at_rn = &arptree_root; - } - else - { - at_rn = &ipntomtree_root; - } - level = 0; - del_cnt = 0; - while ((level < 5) && (at_rn != NULL)) - { - fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n); - if (fc == 0) - { - /* arpidx[level] does not exist */ - del_cnt = 0; - at_rn = NULL; - } - else if (fc == 1) - { - del_rn[del_cnt] = at_rn; - del_n[del_cnt] = at_n; - del_cnt++; - at_rn = (struct mib_list_rootnode*)(at_n->nptr); - } - else if (fc == 2) - { - /* reset delete (2 or more childs) */ - del_cnt = 0; - at_rn = (struct mib_list_rootnode*)(at_n->nptr); - } - level++; - } - /* delete marked index nodes */ - while (del_cnt > 0) - { - del_cnt--; - - at_rn = del_rn[del_cnt]; - at_n = del_n[del_cnt]; - - next = snmp_mib_node_delete(at_rn, at_n); - if (next != NULL) - { - LWIP_ASSERT("next_count == 0",next->count == 0); - snmp_mib_lrn_free(next); - } - } - } - /* disable getnext traversal on empty tables */ - if(arptree_root.count == 0) at.maxlength = 0; - if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0; -} - -void snmp_inc_ipinreceives(void) -{ - ipinreceives++; -} - -void snmp_inc_ipinhdrerrors(void) -{ - ipinhdrerrors++; -} - -void snmp_inc_ipinaddrerrors(void) -{ - ipinaddrerrors++; -} - -void snmp_inc_ipforwdatagrams(void) -{ - ipforwdatagrams++; -} - -void snmp_inc_ipinunknownprotos(void) -{ - ipinunknownprotos++; -} - -void snmp_inc_ipindiscards(void) -{ - ipindiscards++; -} - -void snmp_inc_ipindelivers(void) -{ - ipindelivers++; -} - -void snmp_inc_ipoutrequests(void) -{ - ipoutrequests++; -} - -void snmp_inc_ipoutdiscards(void) -{ - ipoutdiscards++; -} - -void snmp_inc_ipoutnoroutes(void) -{ - ipoutnoroutes++; -} - -void snmp_inc_ipreasmreqds(void) -{ - ipreasmreqds++; -} - -void snmp_inc_ipreasmoks(void) -{ - ipreasmoks++; -} - -void snmp_inc_ipreasmfails(void) -{ - ipreasmfails++; -} - -void snmp_inc_ipfragoks(void) -{ - ipfragoks++; -} - -void snmp_inc_ipfragfails(void) -{ - ipfragfails++; -} - -void snmp_inc_ipfragcreates(void) -{ - ipfragcreates++; -} - -void snmp_inc_iproutingdiscards(void) -{ - iproutingdiscards++; -} - -/** - * Inserts ipAddrTable indexes (.ipAdEntAddr) - * into index tree. - */ -void snmp_insert_ipaddridx_tree(struct netif *ni) -{ - struct mib_list_rootnode *ipa_rn; - struct mib_list_node *ipa_node; - struct ip_addr ip; - s32_t ipaddridx[4]; - u8_t level; - - LWIP_ASSERT("ni != NULL", ni != NULL); - ip.addr = ntohl(ni->ip_addr.addr); - snmp_iptooid(&ip, &ipaddridx[0]); - - level = 0; - ipa_rn = &ipaddrtree_root; - while (level < 4) - { - ipa_node = NULL; - snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node); - if ((level != 3) && (ipa_node != NULL)) - { - if (ipa_node->nptr == NULL) - { - ipa_rn = snmp_mib_lrn_alloc(); - ipa_node->nptr = (struct mib_node*)ipa_rn; - if (ipa_rn != NULL) - { - if (level == 2) - { - ipa_rn->get_object_def = ip_addrentry_get_object_def; - ipa_rn->get_value = ip_addrentry_get_value; - ipa_rn->set_test = noleafs_set_test; - ipa_rn->set_value = noleafs_set_value; - } - } - else - { - /* ipa_rn == NULL, malloc failure */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full")); - break; - } - } - else - { - ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr; - } - } - level++; - } - /* enable getnext traversal on filled table */ - ipaddrtable.maxlength = 1; -} - -/** - * Removes ipAddrTable indexes (.ipAdEntAddr) - * from index tree. - */ -void snmp_delete_ipaddridx_tree(struct netif *ni) -{ - struct mib_list_rootnode *ipa_rn, *next, *del_rn[4]; - struct mib_list_node *ipa_n, *del_n[4]; - struct ip_addr ip; - s32_t ipaddridx[4]; - u8_t fc, level, del_cnt; - - LWIP_ASSERT("ni != NULL", ni != NULL); - ip.addr = ntohl(ni->ip_addr.addr); - snmp_iptooid(&ip, &ipaddridx[0]); - - /* mark nodes for deletion */ - level = 0; - del_cnt = 0; - ipa_rn = &ipaddrtree_root; - while ((level < 4) && (ipa_rn != NULL)) - { - fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n); - if (fc == 0) - { - /* ipaddridx[level] does not exist */ - del_cnt = 0; - ipa_rn = NULL; - } - else if (fc == 1) - { - del_rn[del_cnt] = ipa_rn; - del_n[del_cnt] = ipa_n; - del_cnt++; - ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); - } - else if (fc == 2) - { - /* reset delete (2 or more childs) */ - del_cnt = 0; - ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); - } - level++; - } - /* delete marked index nodes */ - while (del_cnt > 0) - { - del_cnt--; - - ipa_rn = del_rn[del_cnt]; - ipa_n = del_n[del_cnt]; - - next = snmp_mib_node_delete(ipa_rn, ipa_n); - if (next != NULL) - { - LWIP_ASSERT("next_count == 0",next->count == 0); - snmp_mib_lrn_free(next); - } - } - /* disable getnext traversal on empty table */ - if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0; -} - -/** - * Inserts ipRouteTable indexes (.ipRouteDest) - * into index tree. - * - * @param dflt non-zero for the default rte, zero for network rte - * @param ni points to network interface for this rte - * - * @todo record sysuptime for _this_ route when it is installed - * (needed for ipRouteAge) in the netif. - */ -void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni) -{ - u8_t insert = 0; - struct ip_addr dst; - - if (dflt != 0) - { - /* the default route 0.0.0.0 */ - dst.addr = 0; - insert = 1; - } - else - { - /* route to the network address */ - dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr); - /* exclude 0.0.0.0 network (reserved for default rte) */ - if (dst.addr != 0) insert = 1; - } - if (insert) - { - struct mib_list_rootnode *iprte_rn; - struct mib_list_node *iprte_node; - s32_t iprteidx[4]; - u8_t level; - - snmp_iptooid(&dst, &iprteidx[0]); - level = 0; - iprte_rn = &iprtetree_root; - while (level < 4) - { - iprte_node = NULL; - snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node); - if ((level != 3) && (iprte_node != NULL)) - { - if (iprte_node->nptr == NULL) - { - iprte_rn = snmp_mib_lrn_alloc(); - iprte_node->nptr = (struct mib_node*)iprte_rn; - if (iprte_rn != NULL) - { - if (level == 2) - { - iprte_rn->get_object_def = ip_rteentry_get_object_def; - iprte_rn->get_value = ip_rteentry_get_value; - iprte_rn->set_test = noleafs_set_test; - iprte_rn->set_value = noleafs_set_value; - } - } - else - { - /* iprte_rn == NULL, malloc failure */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full")); - break; - } - } - else - { - iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr; - } - } - level++; - } - } - /* enable getnext traversal on filled table */ - iprtetable.maxlength = 1; -} - -/** - * Removes ipRouteTable indexes (.ipRouteDest) - * from index tree. - * - * @param dflt non-zero for the default rte, zero for network rte - * @param ni points to network interface for this rte or NULL - * for default route to be removed. - */ -void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni) -{ - u8_t delete = 0; - struct ip_addr dst; - - if (dflt != 0) - { - /* the default route 0.0.0.0 */ - dst.addr = 0; - delete = 1; - } - else - { - /* route to the network address */ - dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr); - /* exclude 0.0.0.0 network (reserved for default rte) */ - if (dst.addr != 0) delete = 1; - } - if (delete) - { - struct mib_list_rootnode *iprte_rn, *next, *del_rn[4]; - struct mib_list_node *iprte_n, *del_n[4]; - s32_t iprteidx[4]; - u8_t fc, level, del_cnt; - - snmp_iptooid(&dst, &iprteidx[0]); - /* mark nodes for deletion */ - level = 0; - del_cnt = 0; - iprte_rn = &iprtetree_root; - while ((level < 4) && (iprte_rn != NULL)) - { - fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n); - if (fc == 0) - { - /* iprteidx[level] does not exist */ - del_cnt = 0; - iprte_rn = NULL; - } - else if (fc == 1) - { - del_rn[del_cnt] = iprte_rn; - del_n[del_cnt] = iprte_n; - del_cnt++; - iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); - } - else if (fc == 2) - { - /* reset delete (2 or more childs) */ - del_cnt = 0; - iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); - } - level++; - } - /* delete marked index nodes */ - while (del_cnt > 0) - { - del_cnt--; - - iprte_rn = del_rn[del_cnt]; - iprte_n = del_n[del_cnt]; - - next = snmp_mib_node_delete(iprte_rn, iprte_n); - if (next != NULL) - { - LWIP_ASSERT("next_count == 0",next->count == 0); - snmp_mib_lrn_free(next); - } - } - } - /* disable getnext traversal on empty table */ - if (iprtetree_root.count == 0) iprtetable.maxlength = 0; -} - - -void snmp_inc_icmpinmsgs(void) -{ - icmpinmsgs++; -} - -void snmp_inc_icmpinerrors(void) -{ - icmpinerrors++; -} - -void snmp_inc_icmpindestunreachs(void) -{ - icmpindestunreachs++; -} - -void snmp_inc_icmpintimeexcds(void) -{ - icmpintimeexcds++; -} - -void snmp_inc_icmpinparmprobs(void) -{ - icmpinparmprobs++; -} - -void snmp_inc_icmpinsrcquenchs(void) -{ - icmpinsrcquenchs++; -} - -void snmp_inc_icmpinredirects(void) -{ - icmpinredirects++; -} - -void snmp_inc_icmpinechos(void) -{ - icmpinechos++; -} - -void snmp_inc_icmpinechoreps(void) -{ - icmpinechoreps++; -} - -void snmp_inc_icmpintimestamps(void) -{ - icmpintimestamps++; -} - -void snmp_inc_icmpintimestampreps(void) -{ - icmpintimestampreps++; -} - -void snmp_inc_icmpinaddrmasks(void) -{ - icmpinaddrmasks++; -} - -void snmp_inc_icmpinaddrmaskreps(void) -{ - icmpinaddrmaskreps++; -} - -void snmp_inc_icmpoutmsgs(void) -{ - icmpoutmsgs++; -} - -void snmp_inc_icmpouterrors(void) -{ - icmpouterrors++; -} - -void snmp_inc_icmpoutdestunreachs(void) -{ - icmpoutdestunreachs++; -} - -void snmp_inc_icmpouttimeexcds(void) -{ - icmpouttimeexcds++; -} - -void snmp_inc_icmpoutparmprobs(void) -{ - icmpoutparmprobs++; -} - -void snmp_inc_icmpoutsrcquenchs(void) -{ - icmpoutsrcquenchs++; -} - -void snmp_inc_icmpoutredirects(void) -{ - icmpoutredirects++; -} - -void snmp_inc_icmpoutechos(void) -{ - icmpoutechos++; -} - -void snmp_inc_icmpoutechoreps(void) -{ - icmpoutechoreps++; -} - -void snmp_inc_icmpouttimestamps(void) -{ - icmpouttimestamps++; -} - -void snmp_inc_icmpouttimestampreps(void) -{ - icmpouttimestampreps++; -} - -void snmp_inc_icmpoutaddrmasks(void) -{ - icmpoutaddrmasks++; -} - -void snmp_inc_icmpoutaddrmaskreps(void) -{ - icmpoutaddrmaskreps++; -} - -void snmp_inc_tcpactiveopens(void) -{ - tcpactiveopens++; -} - -void snmp_inc_tcppassiveopens(void) -{ - tcppassiveopens++; -} - -void snmp_inc_tcpattemptfails(void) -{ - tcpattemptfails++; -} - -void snmp_inc_tcpestabresets(void) -{ - tcpestabresets++; -} - -void snmp_inc_tcpinsegs(void) -{ - tcpinsegs++; -} - -void snmp_inc_tcpoutsegs(void) -{ - tcpoutsegs++; -} - -void snmp_inc_tcpretranssegs(void) -{ - tcpretranssegs++; -} - -void snmp_inc_tcpinerrs(void) -{ - tcpinerrs++; -} - -void snmp_inc_tcpoutrsts(void) -{ - tcpoutrsts++; -} - -void snmp_inc_udpindatagrams(void) -{ - udpindatagrams++; -} - -void snmp_inc_udpnoports(void) -{ - udpnoports++; -} - -void snmp_inc_udpinerrors(void) -{ - udpinerrors++; -} - -void snmp_inc_udpoutdatagrams(void) -{ - udpoutdatagrams++; -} - -/** - * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort) - * into index tree. - */ -void snmp_insert_udpidx_tree(struct udp_pcb *pcb) -{ - struct mib_list_rootnode *udp_rn; - struct mib_list_node *udp_node; - struct ip_addr ip; - s32_t udpidx[5]; - u8_t level; - - LWIP_ASSERT("pcb != NULL", pcb != NULL); - ip.addr = ntohl(pcb->local_ip.addr); - snmp_iptooid(&ip, &udpidx[0]); - udpidx[4] = pcb->local_port; - - udp_rn = &udp_root; - for (level = 0; level < 5; level++) - { - udp_node = NULL; - snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node); - if ((level != 4) && (udp_node != NULL)) - { - if (udp_node->nptr == NULL) - { - udp_rn = snmp_mib_lrn_alloc(); - udp_node->nptr = (struct mib_node*)udp_rn; - if (udp_rn != NULL) - { - if (level == 3) - { - udp_rn->get_object_def = udpentry_get_object_def; - udp_rn->get_value = udpentry_get_value; - udp_rn->set_test = noleafs_set_test; - udp_rn->set_value = noleafs_set_value; - } - } - else - { - /* udp_rn == NULL, malloc failure */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full")); - break; - } - } - else - { - udp_rn = (struct mib_list_rootnode*)udp_node->nptr; - } - } - } - udptable.maxlength = 1; -} - -/** - * Removes udpTable indexes (.udpLocalAddress.udpLocalPort) - * from index tree. - */ -void snmp_delete_udpidx_tree(struct udp_pcb *pcb) -{ - struct mib_list_rootnode *udp_rn, *next, *del_rn[5]; - struct mib_list_node *udp_n, *del_n[5]; - struct ip_addr ip; - s32_t udpidx[5]; - u8_t bindings, fc, level, del_cnt; - - LWIP_ASSERT("pcb != NULL", pcb != NULL); - ip.addr = ntohl(pcb->local_ip.addr); - snmp_iptooid(&ip, &udpidx[0]); - udpidx[4] = pcb->local_port; - - /* count PCBs for a given binding - (e.g. when reusing ports or for temp output PCBs) */ - bindings = 0; - pcb = udp_pcbs; - while ((pcb != NULL)) - { - if ((pcb->local_ip.addr == ip.addr) && - (pcb->local_port == udpidx[4])) - { - bindings++; - } - pcb = pcb->next; - } - if (bindings == 1) - { - /* selectively remove */ - /* mark nodes for deletion */ - level = 0; - del_cnt = 0; - udp_rn = &udp_root; - while ((level < 5) && (udp_rn != NULL)) - { - fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n); - if (fc == 0) - { - /* udpidx[level] does not exist */ - del_cnt = 0; - udp_rn = NULL; - } - else if (fc == 1) - { - del_rn[del_cnt] = udp_rn; - del_n[del_cnt] = udp_n; - del_cnt++; - udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); - } - else if (fc == 2) - { - /* reset delete (2 or more childs) */ - del_cnt = 0; - udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); - } - level++; - } - /* delete marked index nodes */ - while (del_cnt > 0) - { - del_cnt--; - - udp_rn = del_rn[del_cnt]; - udp_n = del_n[del_cnt]; - - next = snmp_mib_node_delete(udp_rn, udp_n); - if (next != NULL) - { - LWIP_ASSERT("next_count == 0",next->count == 0); - snmp_mib_lrn_free(next); - } - } - } - /* disable getnext traversal on empty table */ - if (udp_root.count == 0) udptable.maxlength = 0; -} - - -void snmp_inc_snmpinpkts(void) -{ - snmpinpkts++; -} - -void snmp_inc_snmpoutpkts(void) -{ - snmpoutpkts++; -} - -void snmp_inc_snmpinbadversions(void) -{ - snmpinbadversions++; -} - -void snmp_inc_snmpinbadcommunitynames(void) -{ - snmpinbadcommunitynames++; -} - -void snmp_inc_snmpinbadcommunityuses(void) -{ - snmpinbadcommunityuses++; -} - -void snmp_inc_snmpinasnparseerrs(void) -{ - snmpinasnparseerrs++; -} - -void snmp_inc_snmpintoobigs(void) -{ - snmpintoobigs++; -} - -void snmp_inc_snmpinnosuchnames(void) -{ - snmpinnosuchnames++; -} - -void snmp_inc_snmpinbadvalues(void) -{ - snmpinbadvalues++; -} - -void snmp_inc_snmpinreadonlys(void) -{ - snmpinreadonlys++; -} - -void snmp_inc_snmpingenerrs(void) -{ - snmpingenerrs++; -} - -void snmp_add_snmpintotalreqvars(u8_t value) -{ - snmpintotalreqvars += value; -} - -void snmp_add_snmpintotalsetvars(u8_t value) -{ - snmpintotalsetvars += value; -} - -void snmp_inc_snmpingetrequests(void) -{ - snmpingetrequests++; -} - -void snmp_inc_snmpingetnexts(void) -{ - snmpingetnexts++; -} - -void snmp_inc_snmpinsetrequests(void) -{ - snmpinsetrequests++; -} - -void snmp_inc_snmpingetresponses(void) -{ - snmpingetresponses++; -} - -void snmp_inc_snmpintraps(void) -{ - snmpintraps++; -} - -void snmp_inc_snmpouttoobigs(void) -{ - snmpouttoobigs++; -} - -void snmp_inc_snmpoutnosuchnames(void) -{ - snmpoutnosuchnames++; -} - -void snmp_inc_snmpoutbadvalues(void) -{ - snmpoutbadvalues++; -} - -void snmp_inc_snmpoutgenerrs(void) -{ - snmpoutgenerrs++; -} - -void snmp_inc_snmpoutgetrequests(void) -{ - snmpoutgetrequests++; -} - -void snmp_inc_snmpoutgetnexts(void) -{ - snmpoutgetnexts++; -} - -void snmp_inc_snmpoutsetrequests(void) -{ - snmpoutsetrequests++; -} - -void snmp_inc_snmpoutgetresponses(void) -{ - snmpoutgetresponses++; -} - -void snmp_inc_snmpouttraps(void) -{ - snmpouttraps++; -} - -void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid) -{ - *oid = &snmpgrp_id; -} - -void snmp_set_snmpenableauthentraps(u8_t *value) -{ - if (value != NULL) - { - snmpenableauthentraps_ptr = value; - } -} - -void snmp_get_snmpenableauthentraps(u8_t *value) -{ - *value = *snmpenableauthentraps_ptr; -} - -void -noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - LWIP_UNUSED_ARG(ident_len); - LWIP_UNUSED_ARG(ident); - od->instance = MIB_OBJECT_NONE; -} - -void -noleafs_get_value(struct obj_def *od, u16_t len, void *value) -{ - LWIP_UNUSED_ARG(od); - LWIP_UNUSED_ARG(len); - LWIP_UNUSED_ARG(value); -} - -u8_t -noleafs_set_test(struct obj_def *od, u16_t len, void *value) -{ - LWIP_UNUSED_ARG(od); - LWIP_UNUSED_ARG(len); - LWIP_UNUSED_ARG(value); - /* can't set */ - return 0; -} - -void -noleafs_set_value(struct obj_def *od, u16_t len, void *value) -{ - LWIP_UNUSED_ARG(od); - LWIP_UNUSED_ARG(len); - LWIP_UNUSED_ARG(value); -} - - -/** - * Returns systems object definitions. - * - * @param ident_len the address length (2) - * @param ident points to objectname.0 (object id trailer) - * @param od points to object definition. - */ -static void -system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - u8_t id; - - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if (ident_len == 2) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id)); - switch (id) - { - case 1: /* sysDescr */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = *sysdescr_len_ptr; - break; - case 2: /* sysObjectID */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); - od->v_len = sysobjid.len * sizeof(s32_t); - break; - case 3: /* sysUpTime */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); - od->v_len = sizeof(u32_t); - break; - case 4: /* sysContact */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = *syscontact_len_ptr; - break; - case 5: /* sysName */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = *sysname_len_ptr; - break; - case 6: /* sysLocation */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = *syslocation_len_ptr; - break; - case 7: /* sysServices */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - }; - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -/** - * Returns system object value. - * - * @param ident_len the address length (2) - * @param ident points to objectname.0 (object id trailer) - * @param len return value space (in bytes) - * @param value points to (varbind) space to copy value into. - */ -static void -system_get_value(struct obj_def *od, u16_t len, void *value) -{ - u8_t id; - - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* sysDescr */ - ocstrncpy(value,sysdescr_ptr, len); - break; - case 2: /* sysObjectID */ - objectidncpy((s32_t*)value, (s32_t*)sysobjid.id, (u8_t)(len / sizeof(s32_t))); - break; - case 3: /* sysUpTime */ - { - snmp_get_sysuptime(value); - } - break; - case 4: /* sysContact */ - ocstrncpy(value,syscontact_ptr,len); - break; - case 5: /* sysName */ - ocstrncpy(value,sysname_ptr,len); - break; - case 6: /* sysLocation */ - ocstrncpy(value,syslocation_ptr,len); - break; - case 7: /* sysServices */ - { - s32_t *sint_ptr = value; - *sint_ptr = sysservices; - } - break; - }; -} - -static u8_t -system_set_test(struct obj_def *od, u16_t len, void *value) -{ - u8_t id, set_ok; - - LWIP_UNUSED_ARG(value); - set_ok = 0; - id = od->id_inst_ptr[0]; - switch (id) - { - case 4: /* sysContact */ - if ((syscontact_ptr != syscontact_default) && - (len <= 255)) - { - set_ok = 1; - } - break; - case 5: /* sysName */ - if ((sysname_ptr != sysname_default) && - (len <= 255)) - { - set_ok = 1; - } - break; - case 6: /* sysLocation */ - if ((syslocation_ptr != syslocation_default) && - (len <= 255)) - { - set_ok = 1; - } - break; - }; - return set_ok; -} - -static void -system_set_value(struct obj_def *od, u16_t len, void *value) -{ - u8_t id; - - id = od->id_inst_ptr[0]; - switch (id) - { - case 4: /* sysContact */ - ocstrncpy(syscontact_ptr,value,len); - *syscontact_len_ptr = len; - break; - case 5: /* sysName */ - ocstrncpy(sysname_ptr,value,len); - *sysname_len_ptr = len; - break; - case 6: /* sysLocation */ - ocstrncpy(syslocation_ptr,value,len); - *syslocation_len_ptr = len; - break; - }; -} - -/** - * Returns interfaces.ifnumber object definition. - * - * @param ident_len the address length (2) - * @param ident points to objectname.index - * @param od points to object definition. - */ -static void -interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if (ident_len == 2) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -/** - * Returns interfaces.ifnumber object value. - * - * @param ident_len the address length (2) - * @param ident points to objectname.0 (object id trailer) - * @param len return value space (in bytes) - * @param value points to (varbind) space to copy value into. - */ -static void -interfaces_get_value(struct obj_def *od, u16_t len, void *value) -{ - LWIP_UNUSED_ARG(len); - if (od->id_inst_ptr[0] == 1) - { - s32_t *sint_ptr = value; - *sint_ptr = iflist_root.count; - } -} - -/** - * Returns ifentry object definitions. - * - * @param ident_len the address length (2) - * @param ident points to objectname.index - * @param od points to object definition. - */ -static void -ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - u8_t id; - - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if (ident_len == 2) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id)); - switch (id) - { - case 1: /* ifIndex */ - case 3: /* ifType */ - case 4: /* ifMtu */ - case 8: /* ifOperStatus */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 2: /* ifDescr */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - /** @todo this should be some sort of sizeof(struct netif.name) */ - od->v_len = 2; - break; - case 5: /* ifSpeed */ - case 21: /* ifOutQLen */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); - od->v_len = sizeof(u32_t); - break; - case 6: /* ifPhysAddress */ - { - struct netif *netif; - - snmp_ifindextonetif(ident[1], &netif); - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = netif->hwaddr_len; - } - break; - case 7: /* ifAdminStatus */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 9: /* ifLastChange */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); - od->v_len = sizeof(u32_t); - break; - case 10: /* ifInOctets */ - case 11: /* ifInUcastPkts */ - case 12: /* ifInNUcastPkts */ - case 13: /* ifInDiscarts */ - case 14: /* ifInErrors */ - case 15: /* ifInUnkownProtos */ - case 16: /* ifOutOctets */ - case 17: /* ifOutUcastPkts */ - case 18: /* ifOutNUcastPkts */ - case 19: /* ifOutDiscarts */ - case 20: /* ifOutErrors */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); - od->v_len = sizeof(u32_t); - break; - case 22: /* ifSpecific */ - /** @note returning zeroDotZero (0.0) no media specific MIB support */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); - od->v_len = ifspecific.len * sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - }; - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -/** - * Returns ifentry object value. - * - * @param ident_len the address length (2) - * @param ident points to objectname.0 (object id trailer) - * @param len return value space (in bytes) - * @param value points to (varbind) space to copy value into. - */ -static void -ifentry_get_value(struct obj_def *od, u16_t len, void *value) -{ - struct netif *netif; - u8_t id; - - snmp_ifindextonetif(od->id_inst_ptr[1], &netif); - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* ifIndex */ - { - s32_t *sint_ptr = value; - *sint_ptr = od->id_inst_ptr[1]; - } - break; - case 2: /* ifDescr */ - ocstrncpy(value,(u8_t*)netif->name,len); - break; - case 3: /* ifType */ - { - s32_t *sint_ptr = value; - *sint_ptr = netif->link_type; - } - break; - case 4: /* ifMtu */ - { - s32_t *sint_ptr = value; - *sint_ptr = netif->mtu; - } - break; - case 5: /* ifSpeed */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->link_speed; - } - break; - case 6: /* ifPhysAddress */ - ocstrncpy(value,netif->hwaddr,len); - break; - case 7: /* ifAdminStatus */ -#if LWIP_NETIF_LINK_CALLBACK - { - s32_t *sint_ptr = value; - if (netif_is_up(netif)) - { - if (netif_is_link_up(netif)) - { - *sint_ptr = 1; /* up */ - } - else - { - *sint_ptr = 7; /* lowerLayerDown */ - } - } - else - { - *sint_ptr = 2; /* down */ - } - } - break; -#endif - case 8: /* ifOperStatus */ - { - s32_t *sint_ptr = value; - if (netif_is_up(netif)) - { - *sint_ptr = 1; - } - else - { - *sint_ptr = 2; - } - } - break; - case 9: /* ifLastChange */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ts; - } - break; - case 10: /* ifInOctets */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifinoctets; - } - break; - case 11: /* ifInUcastPkts */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifinucastpkts; - } - break; - case 12: /* ifInNUcastPkts */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifinnucastpkts; - } - break; - case 13: /* ifInDiscarts */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifindiscards; - } - break; - case 14: /* ifInErrors */ - case 15: /* ifInUnkownProtos */ - /** @todo add these counters! */ - { - u32_t *uint_ptr = value; - *uint_ptr = 0; - } - break; - case 16: /* ifOutOctets */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifoutoctets; - } - break; - case 17: /* ifOutUcastPkts */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifoutucastpkts; - } - break; - case 18: /* ifOutNUcastPkts */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifoutnucastpkts; - } - break; - case 19: /* ifOutDiscarts */ - { - u32_t *uint_ptr = value; - *uint_ptr = netif->ifoutdiscards; - } - break; - case 20: /* ifOutErrors */ - /** @todo add this counter! */ - { - u32_t *uint_ptr = value; - *uint_ptr = 0; - } - break; - case 21: /* ifOutQLen */ - /** @todo figure out if this must be 0 (no queue) or 1? */ - { - u32_t *uint_ptr = value; - *uint_ptr = 0; - } - break; - case 22: /* ifSpecific */ - objectidncpy((s32_t*)value, (s32_t*)ifspecific.id, (u8_t)(len / sizeof(s32_t))); - break; - }; -} - -#if !SNMP_SAFE_REQUESTS -static u8_t -ifentry_set_test (struct obj_def *od, u16_t len, void *value) -{ - struct netif *netif; - u8_t id, set_ok; - - set_ok = 0; - snmp_ifindextonetif(od->id_inst_ptr[1], &netif); - id = od->id_inst_ptr[0]; - switch (id) - { - case 7: /* ifAdminStatus */ - { - s32_t *sint_ptr = value; - if (*sint_ptr == 1 || *sint_ptr == 2) - set_ok = 1; - } - break; - } - return set_ok; -} - -static void -ifentry_set_value (struct obj_def *od, u16_t len, void *value) -{ - struct netif *netif; - u8_t id; - - snmp_ifindextonetif(od->id_inst_ptr[1], &netif); - id = od->id_inst_ptr[0]; - switch (id) - { - case 7: /* ifAdminStatus */ - { - s32_t *sint_ptr = value; - if (*sint_ptr == 1) - { - netif_set_up(netif); - } - else if (*sint_ptr == 2) - { - netif_set_down(netif); - } - } - break; - } -} -#endif /* SNMP_SAFE_REQUESTS */ - -/** - * Returns atentry object definitions. - * - * @param ident_len the address length (6) - * @param ident points to objectname.atifindex.atnetaddress - * @param od points to object definition. - */ -static void -atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (5) */ - ident_len += 5; - ident -= 5; - - if (ident_len == 6) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - switch (ident[0]) - { - case 1: /* atIfIndex */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 2: /* atPhysAddress */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = 6; /** @todo try to use netif::hwaddr_len */ - break; - case 3: /* atNetAddress */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); - od->v_len = 4; - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - } - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -atentry_get_value(struct obj_def *od, u16_t len, void *value) -{ -#if LWIP_ARP - u8_t id; - struct eth_addr* ethaddr_ret; - struct ip_addr* ipaddr_ret; -#endif /* LWIP_ARP */ - struct ip_addr ip; - struct netif *netif; - - LWIP_UNUSED_ARG(len); - LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */ - - snmp_ifindextonetif(od->id_inst_ptr[1], &netif); - snmp_oidtoip(&od->id_inst_ptr[2], &ip); - ip.addr = htonl(ip.addr); - -#if LWIP_ARP /** @todo implement a netif_find_addr */ - if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) - { - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* atIfIndex */ - { - s32_t *sint_ptr = value; - *sint_ptr = od->id_inst_ptr[1]; - } - break; - case 2: /* atPhysAddress */ - { - struct eth_addr *dst = value; - - *dst = *ethaddr_ret; - } - break; - case 3: /* atNetAddress */ - { - struct ip_addr *dst = value; - - *dst = *ipaddr_ret; - } - break; - } - } -#endif /* LWIP_ARP */ -} - -static void -ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - u8_t id; - - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if (ident_len == 2) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id)); - switch (id) - { - case 1: /* ipForwarding */ - case 2: /* ipDefaultTTL */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 3: /* ipInReceives */ - case 4: /* ipInHdrErrors */ - case 5: /* ipInAddrErrors */ - case 6: /* ipForwDatagrams */ - case 7: /* ipInUnknownProtos */ - case 8: /* ipInDiscards */ - case 9: /* ipInDelivers */ - case 10: /* ipOutRequests */ - case 11: /* ipOutDiscards */ - case 12: /* ipOutNoRoutes */ - case 14: /* ipReasmReqds */ - case 15: /* ipReasmOKs */ - case 16: /* ipReasmFails */ - case 17: /* ipFragOKs */ - case 18: /* ipFragFails */ - case 19: /* ipFragCreates */ - case 23: /* ipRoutingDiscards */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); - od->v_len = sizeof(u32_t); - break; - case 13: /* ipReasmTimeout */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - }; - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -ip_get_value(struct obj_def *od, u16_t len, void *value) -{ - u8_t id; - - LWIP_UNUSED_ARG(len); - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* ipForwarding */ - { - s32_t *sint_ptr = value; -#if IP_FORWARD - /* forwarding */ - *sint_ptr = 1; -#else - /* not-forwarding */ - *sint_ptr = 2; -#endif - } - break; - case 2: /* ipDefaultTTL */ - { - s32_t *sint_ptr = value; - *sint_ptr = IP_DEFAULT_TTL; - } - break; - case 3: /* ipInReceives */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipinreceives; - } - break; - case 4: /* ipInHdrErrors */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipinhdrerrors; - } - break; - case 5: /* ipInAddrErrors */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipinaddrerrors; - } - break; - case 6: /* ipForwDatagrams */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipforwdatagrams; - } - break; - case 7: /* ipInUnknownProtos */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipinunknownprotos; - } - break; - case 8: /* ipInDiscards */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipindiscards; - } - break; - case 9: /* ipInDelivers */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipindelivers; - } - break; - case 10: /* ipOutRequests */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipoutrequests; - } - break; - case 11: /* ipOutDiscards */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipoutdiscards; - } - break; - case 12: /* ipOutNoRoutes */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipoutnoroutes; - } - break; - case 13: /* ipReasmTimeout */ - { - s32_t *sint_ptr = value; -#if IP_REASSEMBLY - *sint_ptr = IP_REASS_MAXAGE; -#else - *sint_ptr = 0; -#endif - } - break; - case 14: /* ipReasmReqds */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipreasmreqds; - } - break; - case 15: /* ipReasmOKs */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipreasmoks; - } - break; - case 16: /* ipReasmFails */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipreasmfails; - } - break; - case 17: /* ipFragOKs */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipfragoks; - } - break; - case 18: /* ipFragFails */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipfragfails; - } - break; - case 19: /* ipFragCreates */ - { - u32_t *uint_ptr = value; - *uint_ptr = ipfragcreates; - } - break; - case 23: /* ipRoutingDiscards */ - /** @todo can lwIP discard routes at all?? hardwire this to 0?? */ - { - u32_t *uint_ptr = value; - *uint_ptr = iproutingdiscards; - } - break; - }; -} - -/** - * Test ip object value before setting. - * - * @param od is the object definition - * @param len return value space (in bytes) - * @param value points to (varbind) space to copy value from. - * - * @note we allow set if the value matches the hardwired value, - * otherwise return badvalue. - */ -static u8_t -ip_set_test(struct obj_def *od, u16_t len, void *value) -{ - u8_t id, set_ok; - s32_t *sint_ptr = value; - - LWIP_UNUSED_ARG(len); - set_ok = 0; - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* ipForwarding */ -#if IP_FORWARD - /* forwarding */ - if (*sint_ptr == 1) -#else - /* not-forwarding */ - if (*sint_ptr == 2) -#endif - { - set_ok = 1; - } - break; - case 2: /* ipDefaultTTL */ - if (*sint_ptr == IP_DEFAULT_TTL) - { - set_ok = 1; - } - break; - }; - return set_ok; -} - -static void -ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (4) */ - ident_len += 4; - ident -= 4; - - if (ident_len == 5) - { - u8_t id; - - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - switch (id) - { - case 1: /* ipAdEntAddr */ - case 3: /* ipAdEntNetMask */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); - od->v_len = 4; - break; - case 2: /* ipAdEntIfIndex */ - case 4: /* ipAdEntBcastAddr */ - case 5: /* ipAdEntReasmMaxSize */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - } - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value) -{ - u8_t id; - u16_t ifidx; - struct ip_addr ip; - struct netif *netif = netif_list; - - LWIP_UNUSED_ARG(len); - snmp_oidtoip(&od->id_inst_ptr[1], &ip); - ip.addr = htonl(ip.addr); - ifidx = 0; - while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr)) - { - netif = netif->next; - ifidx++; - } - - if (netif != NULL) - { - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* ipAdEntAddr */ - { - struct ip_addr *dst = value; - *dst = netif->ip_addr; - } - break; - case 2: /* ipAdEntIfIndex */ - { - s32_t *sint_ptr = value; - *sint_ptr = ifidx + 1; - } - break; - case 3: /* ipAdEntNetMask */ - { - struct ip_addr *dst = value; - *dst = netif->netmask; - } - break; - case 4: /* ipAdEntBcastAddr */ - { - s32_t *sint_ptr = value; - - /* lwIP oddity, there's no broadcast - address in the netif we can rely on */ - *sint_ptr = ip_addr_broadcast.addr & 1; - } - break; - case 5: /* ipAdEntReasmMaxSize */ - { - s32_t *sint_ptr = value; -#if IP_REASSEMBLY - /* @todo The theoretical maximum is IP_REASS_MAX_PBUFS * size of the pbufs, - * but only if receiving one fragmented packet at a time. - * The current solution is to calculate for 2 simultaneous packets... - */ - *sint_ptr = (IP_HLEN + ((IP_REASS_MAX_PBUFS/2) * - (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - IP_HLEN))); -#else - /** @todo returning MTU would be a bad thing and - returning a wild guess like '576' isn't good either */ - *sint_ptr = 0; -#endif - } - break; - } - } -} - -/** - * @note - * lwIP IP routing is currently using the network addresses in netif_list. - * if no suitable network IP is found in netif_list, the default_netif is used. - */ -static void -ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - u8_t id; - - /* return to object name, adding index depth (4) */ - ident_len += 4; - ident -= 4; - - if (ident_len == 5) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - switch (id) - { - case 1: /* ipRouteDest */ - case 7: /* ipRouteNextHop */ - case 11: /* ipRouteMask */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); - od->v_len = 4; - break; - case 2: /* ipRouteIfIndex */ - case 3: /* ipRouteMetric1 */ - case 4: /* ipRouteMetric2 */ - case 5: /* ipRouteMetric3 */ - case 6: /* ipRouteMetric4 */ - case 8: /* ipRouteType */ - case 10: /* ipRouteAge */ - case 12: /* ipRouteMetric5 */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 9: /* ipRouteProto */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 13: /* ipRouteInfo */ - /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); - od->v_len = iprouteinfo.len * sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - } - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value) -{ - struct netif *netif; - struct ip_addr dest; - s32_t *ident; - u8_t id; - - ident = od->id_inst_ptr; - snmp_oidtoip(&ident[1], &dest); - dest.addr = htonl(dest.addr); - - if (dest.addr == 0) - { - /* ip_route() uses default netif for default route */ - netif = netif_default; - } - else - { - /* not using ip_route(), need exact match! */ - netif = netif_list; - while ((netif != NULL) && - !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) ) - { - netif = netif->next; - } - } - if (netif != NULL) - { - id = ident[0]; - switch (id) - { - case 1: /* ipRouteDest */ - { - struct ip_addr *dst = value; - - if (dest.addr == 0) - { - /* default rte has 0.0.0.0 dest */ - dst->addr = 0; - } - else - { - /* netifs have netaddress dest */ - dst->addr = netif->ip_addr.addr & netif->netmask.addr; - } - } - break; - case 2: /* ipRouteIfIndex */ - { - s32_t *sint_ptr = value; - - snmp_netiftoifindex(netif, sint_ptr); - } - break; - case 3: /* ipRouteMetric1 */ - { - s32_t *sint_ptr = value; - - if (dest.addr == 0) - { - /* default rte has metric 1 */ - *sint_ptr = 1; - } - else - { - /* other rtes have metric 0 */ - *sint_ptr = 0; - } - } - break; - case 4: /* ipRouteMetric2 */ - case 5: /* ipRouteMetric3 */ - case 6: /* ipRouteMetric4 */ - case 12: /* ipRouteMetric5 */ - { - s32_t *sint_ptr = value; - /* not used */ - *sint_ptr = -1; - } - break; - case 7: /* ipRouteNextHop */ - { - struct ip_addr *dst = value; - - if (dest.addr == 0) - { - /* default rte: gateway */ - *dst = netif->gw; - } - else - { - /* other rtes: netif ip_addr */ - *dst = netif->ip_addr; - } - } - break; - case 8: /* ipRouteType */ - { - s32_t *sint_ptr = value; - - if (dest.addr == 0) - { - /* default rte is indirect */ - *sint_ptr = 4; - } - else - { - /* other rtes are direct */ - *sint_ptr = 3; - } - } - break; - case 9: /* ipRouteProto */ - { - s32_t *sint_ptr = value; - /* locally defined routes */ - *sint_ptr = 2; - } - break; - case 10: /* ipRouteAge */ - { - s32_t *sint_ptr = value; - /** @todo (sysuptime - timestamp last change) / 100 - @see snmp_insert_iprteidx_tree() */ - *sint_ptr = 0; - } - break; - case 11: /* ipRouteMask */ - { - struct ip_addr *dst = value; - - if (dest.addr == 0) - { - /* default rte use 0.0.0.0 mask */ - dst->addr = 0; - } - else - { - /* other rtes use netmask */ - *dst = netif->netmask; - } - } - break; - case 13: /* ipRouteInfo */ - objectidncpy((s32_t*)value, (s32_t*)iprouteinfo.id, (u8_t)(len / sizeof(s32_t))); - break; - } - } -} - -static void -ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (5) */ - ident_len += 5; - ident -= 5; - - if (ident_len == 6) - { - u8_t id; - - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - switch (id) - { - case 1: /* ipNetToMediaIfIndex */ - case 4: /* ipNetToMediaType */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 2: /* ipNetToMediaPhysAddress */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); - od->v_len = 6; /** @todo try to use netif::hwaddr_len */ - break; - case 3: /* ipNetToMediaNetAddress */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); - od->v_len = 4; - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - } - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value) -{ -#if LWIP_ARP - u8_t id; - struct eth_addr* ethaddr_ret; - struct ip_addr* ipaddr_ret; -#endif /* LWIP_ARP */ - struct ip_addr ip; - struct netif *netif; - - LWIP_UNUSED_ARG(len); - LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */ - - snmp_ifindextonetif(od->id_inst_ptr[1], &netif); - snmp_oidtoip(&od->id_inst_ptr[2], &ip); - ip.addr = htonl(ip.addr); - -#if LWIP_ARP /** @todo implement a netif_find_addr */ - if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) - { - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* ipNetToMediaIfIndex */ - { - s32_t *sint_ptr = value; - *sint_ptr = od->id_inst_ptr[1]; - } - break; - case 2: /* ipNetToMediaPhysAddress */ - { - struct eth_addr *dst = value; - - *dst = *ethaddr_ret; - } - break; - case 3: /* ipNetToMediaNetAddress */ - { - struct ip_addr *dst = value; - - *dst = *ipaddr_ret; - } - break; - case 4: /* ipNetToMediaType */ - { - s32_t *sint_ptr = value; - /* dynamic (?) */ - *sint_ptr = 3; - } - break; - } - } -#endif /* LWIP_ARP */ -} - -static void -icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if ((ident_len == 2) && - (ident[0] > 0) && (ident[0] < 27)) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); - od->v_len = sizeof(u32_t); - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -icmp_get_value(struct obj_def *od, u16_t len, void *value) -{ - u32_t *uint_ptr = value; - u8_t id; - - LWIP_UNUSED_ARG(len); - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* icmpInMsgs */ - *uint_ptr = icmpinmsgs; - break; - case 2: /* icmpInErrors */ - *uint_ptr = icmpinerrors; - break; - case 3: /* icmpInDestUnreachs */ - *uint_ptr = icmpindestunreachs; - break; - case 4: /* icmpInTimeExcds */ - *uint_ptr = icmpintimeexcds; - break; - case 5: /* icmpInParmProbs */ - *uint_ptr = icmpinparmprobs; - break; - case 6: /* icmpInSrcQuenchs */ - *uint_ptr = icmpinsrcquenchs; - break; - case 7: /* icmpInRedirects */ - *uint_ptr = icmpinredirects; - break; - case 8: /* icmpInEchos */ - *uint_ptr = icmpinechos; - break; - case 9: /* icmpInEchoReps */ - *uint_ptr = icmpinechoreps; - break; - case 10: /* icmpInTimestamps */ - *uint_ptr = icmpintimestamps; - break; - case 11: /* icmpInTimestampReps */ - *uint_ptr = icmpintimestampreps; - break; - case 12: /* icmpInAddrMasks */ - *uint_ptr = icmpinaddrmasks; - break; - case 13: /* icmpInAddrMaskReps */ - *uint_ptr = icmpinaddrmaskreps; - break; - case 14: /* icmpOutMsgs */ - *uint_ptr = icmpoutmsgs; - break; - case 15: /* icmpOutErrors */ - *uint_ptr = icmpouterrors; - break; - case 16: /* icmpOutDestUnreachs */ - *uint_ptr = icmpoutdestunreachs; - break; - case 17: /* icmpOutTimeExcds */ - *uint_ptr = icmpouttimeexcds; - break; - case 18: /* icmpOutParmProbs */ - *uint_ptr = icmpoutparmprobs; - break; - case 19: /* icmpOutSrcQuenchs */ - *uint_ptr = icmpoutsrcquenchs; - break; - case 20: /* icmpOutRedirects */ - *uint_ptr = icmpoutredirects; - break; - case 21: /* icmpOutEchos */ - *uint_ptr = icmpoutechos; - break; - case 22: /* icmpOutEchoReps */ - *uint_ptr = icmpoutechoreps; - break; - case 23: /* icmpOutTimestamps */ - *uint_ptr = icmpouttimestamps; - break; - case 24: /* icmpOutTimestampReps */ - *uint_ptr = icmpouttimestampreps; - break; - case 25: /* icmpOutAddrMasks */ - *uint_ptr = icmpoutaddrmasks; - break; - case 26: /* icmpOutAddrMaskReps */ - *uint_ptr = icmpoutaddrmaskreps; - break; - } -} - -#if LWIP_TCP -/** @todo tcp grp */ -static void -tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - u8_t id; - - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if (ident_len == 2) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); - - switch (id) - { - case 1: /* tcpRtoAlgorithm */ - case 2: /* tcpRtoMin */ - case 3: /* tcpRtoMax */ - case 4: /* tcpMaxConn */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 5: /* tcpActiveOpens */ - case 6: /* tcpPassiveOpens */ - case 7: /* tcpAttemptFails */ - case 8: /* tcpEstabResets */ - case 10: /* tcpInSegs */ - case 11: /* tcpOutSegs */ - case 12: /* tcpRetransSegs */ - case 14: /* tcpInErrs */ - case 15: /* tcpOutRsts */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); - od->v_len = sizeof(u32_t); - break; - case 9: /* tcpCurrEstab */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); - od->v_len = sizeof(u32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - }; - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -tcp_get_value(struct obj_def *od, u16_t len, void *value) -{ - u32_t *uint_ptr = value; - s32_t *sint_ptr = value; - u8_t id; - - LWIP_UNUSED_ARG(len); - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* tcpRtoAlgorithm, vanj(4) */ - *sint_ptr = 4; - break; - case 2: /* tcpRtoMin */ - /* @todo not the actual value, a guess, - needs to be calculated */ - *sint_ptr = 1000; - break; - case 3: /* tcpRtoMax */ - /* @todo not the actual value, a guess, - needs to be calculated */ - *sint_ptr = 60000; - break; - case 4: /* tcpMaxConn */ - *sint_ptr = MEMP_NUM_TCP_PCB; - break; - case 5: /* tcpActiveOpens */ - *uint_ptr = tcpactiveopens; - break; - case 6: /* tcpPassiveOpens */ - *uint_ptr = tcppassiveopens; - break; - case 7: /* tcpAttemptFails */ - *uint_ptr = tcpattemptfails; - break; - case 8: /* tcpEstabResets */ - *uint_ptr = tcpestabresets; - break; - case 9: /* tcpCurrEstab */ - { - u16_t tcpcurrestab = 0; - struct tcp_pcb *pcb = tcp_active_pcbs; - while (pcb != NULL) - { - if ((pcb->state == ESTABLISHED) || - (pcb->state == CLOSE_WAIT)) - { - tcpcurrestab++; - } - pcb = pcb->next; - } - *uint_ptr = tcpcurrestab; - } - break; - case 10: /* tcpInSegs */ - *uint_ptr = tcpinsegs; - break; - case 11: /* tcpOutSegs */ - *uint_ptr = tcpoutsegs; - break; - case 12: /* tcpRetransSegs */ - *uint_ptr = tcpretranssegs; - break; - case 14: /* tcpInErrs */ - *uint_ptr = tcpinerrs; - break; - case 15: /* tcpOutRsts */ - *uint_ptr = tcpoutrsts; - break; - } -} -#ifdef THIS_SEEMS_UNUSED -static void -tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (10) */ - ident_len += 10; - ident -= 10; - - if (ident_len == 11) - { - u8_t id; - - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); - - switch (id) - { - case 1: /* tcpConnState */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - case 2: /* tcpConnLocalAddress */ - case 4: /* tcpConnRemAddress */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); - od->v_len = 4; - break; - case 3: /* tcpConnLocalPort */ - case 5: /* tcpConnRemPort */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - }; - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value) -{ - struct ip_addr lip, rip; - u16_t lport, rport; - s32_t *ident; - - ident = od->id_inst_ptr; - snmp_oidtoip(&ident[1], &lip); - lip.addr = htonl(lip.addr); - lport = ident[5]; - snmp_oidtoip(&ident[6], &rip); - rip.addr = htonl(rip.addr); - rport = ident[10]; - - /** @todo find matching PCB */ -} -#endif /* if 0 */ -#endif - -static void -udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if ((ident_len == 2) && - (ident[0] > 0) && (ident[0] < 6)) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); - od->v_len = sizeof(u32_t); - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -udp_get_value(struct obj_def *od, u16_t len, void *value) -{ - u32_t *uint_ptr = value; - u8_t id; - - LWIP_UNUSED_ARG(len); - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* udpInDatagrams */ - *uint_ptr = udpindatagrams; - break; - case 2: /* udpNoPorts */ - *uint_ptr = udpnoports; - break; - case 3: /* udpInErrors */ - *uint_ptr = udpinerrors; - break; - case 4: /* udpOutDatagrams */ - *uint_ptr = udpoutdatagrams; - break; - } -} - -static void -udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (5) */ - ident_len += 5; - ident -= 5; - - if (ident_len == 6) - { - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - switch (ident[0]) - { - case 1: /* udpLocalAddress */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); - od->v_len = 4; - break; - case 2: /* udpLocalPort */ - od->instance = MIB_OBJECT_TAB; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - } - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -udpentry_get_value(struct obj_def *od, u16_t len, void *value) -{ - u8_t id; - struct udp_pcb *pcb; - struct ip_addr ip; - u16_t port; - - LWIP_UNUSED_ARG(len); - snmp_oidtoip(&od->id_inst_ptr[1], &ip); - ip.addr = htonl(ip.addr); - port = od->id_inst_ptr[5]; - - pcb = udp_pcbs; - while ((pcb != NULL) && - !((pcb->local_ip.addr == ip.addr) && - (pcb->local_port == port))) - { - pcb = pcb->next; - } - - if (pcb != NULL) - { - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* udpLocalAddress */ - { - struct ip_addr *dst = value; - *dst = pcb->local_ip; - } - break; - case 2: /* udpLocalPort */ - { - s32_t *sint_ptr = value; - *sint_ptr = pcb->local_port; - } - break; - } - } -} - -static void -snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) -{ - /* return to object name, adding index depth (1) */ - ident_len += 1; - ident -= 1; - if (ident_len == 2) - { - u8_t id; - - od->id_inst_len = ident_len; - od->id_inst_ptr = ident; - - id = ident[0]; - switch (id) - { - case 1: /* snmpInPkts */ - case 2: /* snmpOutPkts */ - case 3: /* snmpInBadVersions */ - case 4: /* snmpInBadCommunityNames */ - case 5: /* snmpInBadCommunityUses */ - case 6: /* snmpInASNParseErrs */ - case 8: /* snmpInTooBigs */ - case 9: /* snmpInNoSuchNames */ - case 10: /* snmpInBadValues */ - case 11: /* snmpInReadOnlys */ - case 12: /* snmpInGenErrs */ - case 13: /* snmpInTotalReqVars */ - case 14: /* snmpInTotalSetVars */ - case 15: /* snmpInGetRequests */ - case 16: /* snmpInGetNexts */ - case 17: /* snmpInSetRequests */ - case 18: /* snmpInGetResponses */ - case 19: /* snmpInTraps */ - case 20: /* snmpOutTooBigs */ - case 21: /* snmpOutNoSuchNames */ - case 22: /* snmpOutBadValues */ - case 24: /* snmpOutGenErrs */ - case 25: /* snmpOutGetRequests */ - case 26: /* snmpOutGetNexts */ - case 27: /* snmpOutSetRequests */ - case 28: /* snmpOutGetResponses */ - case 29: /* snmpOutTraps */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_ONLY; - od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); - od->v_len = sizeof(u32_t); - break; - case 30: /* snmpEnableAuthenTraps */ - od->instance = MIB_OBJECT_SCALAR; - od->access = MIB_OBJECT_READ_WRITE; - od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); - od->v_len = sizeof(s32_t); - break; - default: - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n")); - od->instance = MIB_OBJECT_NONE; - break; - }; - } - else - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n")); - od->instance = MIB_OBJECT_NONE; - } -} - -static void -snmp_get_value(struct obj_def *od, u16_t len, void *value) -{ - u32_t *uint_ptr = value; - u8_t id; - - LWIP_UNUSED_ARG(len); - id = od->id_inst_ptr[0]; - switch (id) - { - case 1: /* snmpInPkts */ - *uint_ptr = snmpinpkts; - break; - case 2: /* snmpOutPkts */ - *uint_ptr = snmpoutpkts; - break; - case 3: /* snmpInBadVersions */ - *uint_ptr = snmpinbadversions; - break; - case 4: /* snmpInBadCommunityNames */ - *uint_ptr = snmpinbadcommunitynames; - break; - case 5: /* snmpInBadCommunityUses */ - *uint_ptr = snmpinbadcommunityuses; - break; - case 6: /* snmpInASNParseErrs */ - *uint_ptr = snmpinasnparseerrs; - break; - case 8: /* snmpInTooBigs */ - *uint_ptr = snmpintoobigs; - break; - case 9: /* snmpInNoSuchNames */ - *uint_ptr = snmpinnosuchnames; - break; - case 10: /* snmpInBadValues */ - *uint_ptr = snmpinbadvalues; - break; - case 11: /* snmpInReadOnlys */ - *uint_ptr = snmpinreadonlys; - break; - case 12: /* snmpInGenErrs */ - *uint_ptr = snmpingenerrs; - break; - case 13: /* snmpInTotalReqVars */ - *uint_ptr = snmpintotalreqvars; - break; - case 14: /* snmpInTotalSetVars */ - *uint_ptr = snmpintotalsetvars; - break; - case 15: /* snmpInGetRequests */ - *uint_ptr = snmpingetrequests; - break; - case 16: /* snmpInGetNexts */ - *uint_ptr = snmpingetnexts; - break; - case 17: /* snmpInSetRequests */ - *uint_ptr = snmpinsetrequests; - break; - case 18: /* snmpInGetResponses */ - *uint_ptr = snmpingetresponses; - break; - case 19: /* snmpInTraps */ - *uint_ptr = snmpintraps; - break; - case 20: /* snmpOutTooBigs */ - *uint_ptr = snmpouttoobigs; - break; - case 21: /* snmpOutNoSuchNames */ - *uint_ptr = snmpoutnosuchnames; - break; - case 22: /* snmpOutBadValues */ - *uint_ptr = snmpoutbadvalues; - break; - case 24: /* snmpOutGenErrs */ - *uint_ptr = snmpoutgenerrs; - break; - case 25: /* snmpOutGetRequests */ - *uint_ptr = snmpoutgetrequests; - break; - case 26: /* snmpOutGetNexts */ - *uint_ptr = snmpoutgetnexts; - break; - case 27: /* snmpOutSetRequests */ - *uint_ptr = snmpoutsetrequests; - break; - case 28: /* snmpOutGetResponses */ - *uint_ptr = snmpoutgetresponses; - break; - case 29: /* snmpOutTraps */ - *uint_ptr = snmpouttraps; - break; - case 30: /* snmpEnableAuthenTraps */ - *uint_ptr = *snmpenableauthentraps_ptr; - break; - }; -} - -/** - * Test snmp object value before setting. - * - * @param od is the object definition - * @param len return value space (in bytes) - * @param value points to (varbind) space to copy value from. - */ -static u8_t -snmp_set_test(struct obj_def *od, u16_t len, void *value) -{ - u8_t id, set_ok; - - LWIP_UNUSED_ARG(len); - set_ok = 0; - id = od->id_inst_ptr[0]; - if (id == 30) - { - /* snmpEnableAuthenTraps */ - s32_t *sint_ptr = value; - - if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default) - { - /* we should have writable non-volatile mem here */ - if ((*sint_ptr == 1) || (*sint_ptr == 2)) - { - set_ok = 1; - } - } - else - { - /* const or hardwired value */ - if (*sint_ptr == snmpenableauthentraps_default) - { - set_ok = 1; - } - } - } - return set_ok; -} - -static void -snmp_set_value(struct obj_def *od, u16_t len, void *value) -{ - u8_t id; - - LWIP_UNUSED_ARG(len); - id = od->id_inst_ptr[0]; - if (id == 30) - { - /* snmpEnableAuthenTraps */ - s32_t *sint_ptr = value; - *snmpenableauthentraps_ptr = *sint_ptr; - } -} - -#endif /* LWIP_SNMP */ diff --git a/components/net/lwip-1.3.2/src/core/snmp/mib_structs.c b/components/net/lwip-1.3.2/src/core/snmp/mib_structs.c deleted file mode 100644 index 39a2949675..0000000000 --- a/components/net/lwip-1.3.2/src/core/snmp/mib_structs.c +++ /dev/null @@ -1,1183 +0,0 @@ -/** - * @file - * MIB tree access/construction functions. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/snmp_structs.h" -#include "lwip/mem.h" - -/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */ -const s32_t prefix[4] = {1, 3, 6, 1}; - -#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN) -/** node stack entry (old news?) */ -struct nse -{ - /** right child */ - struct mib_node* r_ptr; - /** right child identifier */ - s32_t r_id; - /** right child next level */ - u8_t r_nl; -}; -static u8_t node_stack_cnt; -static struct nse node_stack[NODE_STACK_SIZE]; - -/** - * Pushes nse struct onto stack. - */ -static void -push_node(struct nse* node) -{ - LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE); - LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id)); - if (node_stack_cnt < NODE_STACK_SIZE) - { - node_stack[node_stack_cnt] = *node; - node_stack_cnt++; - } -} - -/** - * Pops nse struct from stack. - */ -static void -pop_node(struct nse* node) -{ - if (node_stack_cnt > 0) - { - node_stack_cnt--; - *node = node_stack[node_stack_cnt]; - } - LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id)); -} - -/** - * Conversion from ifIndex to lwIP netif - * @param ifindex is a s32_t object sub-identifier - * @param netif points to returned netif struct pointer - */ -void -snmp_ifindextonetif(s32_t ifindex, struct netif **netif) -{ - struct netif *nif = netif_list; - u16_t i, ifidx; - - ifidx = ifindex - 1; - i = 0; - while ((nif != NULL) && (i < ifidx)) - { - nif = nif->next; - i++; - } - *netif = nif; -} - -/** - * Conversion from lwIP netif to ifIndex - * @param netif points to a netif struct - * @param ifidx points to s32_t object sub-identifier - */ -void -snmp_netiftoifindex(struct netif *netif, s32_t *ifidx) -{ - struct netif *nif = netif_list; - u16_t i; - - i = 0; - while ((nif != NULL) && (nif != netif)) - { - nif = nif->next; - i++; - } - *ifidx = i+1; -} - -/** - * Conversion from oid to lwIP ip_addr - * @param ident points to s32_t ident[4] input - * @param ip points to output struct - */ -void -snmp_oidtoip(s32_t *ident, struct ip_addr *ip) -{ - u32_t ipa; - - ipa = ident[0]; - ipa <<= 8; - ipa |= ident[1]; - ipa <<= 8; - ipa |= ident[2]; - ipa <<= 8; - ipa |= ident[3]; - ip->addr = ipa; -} - -/** - * Conversion from lwIP ip_addr to oid - * @param ip points to input struct - * @param ident points to s32_t ident[4] output - */ -void -snmp_iptooid(struct ip_addr *ip, s32_t *ident) -{ - u32_t ipa; - - ipa = ip->addr; - ident[0] = (ipa >> 24) & 0xff; - ident[1] = (ipa >> 16) & 0xff; - ident[2] = (ipa >> 8) & 0xff; - ident[3] = ipa & 0xff; -} - -struct mib_list_node * -snmp_mib_ln_alloc(s32_t id) -{ - struct mib_list_node *ln; - - ln = (struct mib_list_node *)mem_malloc(sizeof(struct mib_list_node)); - if (ln != NULL) - { - ln->prev = NULL; - ln->next = NULL; - ln->objid = id; - ln->nptr = NULL; - } - return ln; -} - -void -snmp_mib_ln_free(struct mib_list_node *ln) -{ - mem_free(ln); -} - -struct mib_list_rootnode * -snmp_mib_lrn_alloc(void) -{ - struct mib_list_rootnode *lrn; - - lrn = (struct mib_list_rootnode*)mem_malloc(sizeof(struct mib_list_rootnode)); - if (lrn != NULL) - { - lrn->get_object_def = noleafs_get_object_def; - lrn->get_value = noleafs_get_value; - lrn->set_test = noleafs_set_test; - lrn->set_value = noleafs_set_value; - lrn->node_type = MIB_NODE_LR; - lrn->maxlength = 0; - lrn->head = NULL; - lrn->tail = NULL; - lrn->count = 0; - } - return lrn; -} - -void -snmp_mib_lrn_free(struct mib_list_rootnode *lrn) -{ - mem_free(lrn); -} - -/** - * Inserts node in idx list in a sorted - * (ascending order) fashion and - * allocates the node if needed. - * - * @param rn points to the root node - * @param objid is the object sub identifier - * @param insn points to a pointer to the inserted node - * used for constructing the tree. - * @return -1 if failed, 1 if inserted, 2 if present. - */ -s8_t -snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn) -{ - struct mib_list_node *nn; - s8_t insert; - - LWIP_ASSERT("rn != NULL",rn != NULL); - - /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */ - insert = 0; - if (rn->head == NULL) - { - /* empty list, add first node */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid)); - nn = snmp_mib_ln_alloc(objid); - if (nn != NULL) - { - rn->head = nn; - rn->tail = nn; - *insn = nn; - insert = 1; - } - else - { - insert = -1; - } - } - else - { - struct mib_list_node *n; - /* at least one node is present */ - n = rn->head; - while ((n != NULL) && (insert == 0)) - { - if (n->objid == objid) - { - /* node is already there */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid)); - *insn = n; - insert = 2; - } - else if (n->objid < objid) - { - if (n->next == NULL) - { - /* alloc and insert at the tail */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid)); - nn = snmp_mib_ln_alloc(objid); - if (nn != NULL) - { - nn->next = NULL; - nn->prev = n; - n->next = nn; - rn->tail = nn; - *insn = nn; - insert = 1; - } - else - { - /* insertion failure */ - insert = -1; - } - } - else - { - /* there's more to explore: traverse list */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n")); - n = n->next; - } - } - else - { - /* n->objid > objid */ - /* alloc and insert between n->prev and n */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid)); - nn = snmp_mib_ln_alloc(objid); - if (nn != NULL) - { - if (n->prev == NULL) - { - /* insert at the head */ - nn->next = n; - nn->prev = NULL; - rn->head = nn; - n->prev = nn; - } - else - { - /* insert in the middle */ - nn->next = n; - nn->prev = n->prev; - n->prev->next = nn; - n->prev = nn; - } - *insn = nn; - insert = 1; - } - else - { - /* insertion failure */ - insert = -1; - } - } - } - } - if (insert == 1) - { - rn->count += 1; - } - LWIP_ASSERT("insert != 0",insert != 0); - return insert; -} - -/** - * Finds node in idx list and returns deletion mark. - * - * @param rn points to the root node - * @param objid is the object sub identifier - * @param fn returns pointer to found node - * @return 0 if not found, 1 if deletable, - * 2 can't delete (2 or more children), 3 not a list_node - */ -s8_t -snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn) -{ - s8_t fc; - struct mib_list_node *n; - - LWIP_ASSERT("rn != NULL",rn != NULL); - n = rn->head; - while ((n != NULL) && (n->objid != objid)) - { - n = n->next; - } - if (n == NULL) - { - fc = 0; - } - else if (n->nptr == NULL) - { - /* leaf, can delete node */ - fc = 1; - } - else - { - struct mib_list_rootnode *r; - - if (n->nptr->node_type == MIB_NODE_LR) - { - r = (struct mib_list_rootnode *)n->nptr; - if (r->count > 1) - { - /* can't delete node */ - fc = 2; - } - else - { - /* count <= 1, can delete node */ - fc = 1; - } - } - else - { - /* other node type */ - fc = 3; - } - } - *fn = n; - return fc; -} - -/** - * Removes node from idx list - * if it has a single child left. - * - * @param rn points to the root node - * @param n points to the node to delete - * @return the nptr to be freed by caller - */ -struct mib_list_rootnode * -snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n) -{ - struct mib_list_rootnode *next; - - LWIP_ASSERT("rn != NULL",rn != NULL); - LWIP_ASSERT("n != NULL",n != NULL); - - /* caller must remove this sub-tree */ - next = (struct mib_list_rootnode*)(n->nptr); - rn->count -= 1; - - if (n == rn->head) - { - rn->head = n->next; - if (n->next != NULL) - { - /* not last node, new list begin */ - n->next->prev = NULL; - } - } - else if (n == rn->tail) - { - rn->tail = n->prev; - if (n->prev != NULL) - { - /* not last node, new list end */ - n->prev->next = NULL; - } - } - else - { - /* node must be in the middle */ - n->prev->next = n->next; - n->next->prev = n->prev; - } - LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid)); - snmp_mib_ln_free(n); - if (rn->count == 0) - { - rn->head = NULL; - rn->tail = NULL; - } - return next; -} - - - -/** - * Searches tree for the supplied (scalar?) object identifier. - * - * @param node points to the root of the tree ('.internet') - * @param ident_len the length of the supplied object identifier - * @param ident points to the array of sub identifiers - * @param np points to the found object instance (rerurn) - * @return pointer to the requested parent (!) node if success, NULL otherwise - */ -struct mib_node * -snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np) -{ - u8_t node_type, ext_level; - - ext_level = 0; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident)); - while (node != NULL) - { - node_type = node->node_type; - if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) - { - struct mib_array_node *an; - u16_t i; - - if (ident_len > 0) - { - /* array node (internal ROM or RAM, fixed length) */ - an = (struct mib_array_node *)node; - i = 0; - while ((i < an->maxlength) && (an->objid[i] != *ident)) - { - i++; - } - if (i < an->maxlength) - { - /* found it, if available proceed to child, otherwise inspect leaf */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); - if (an->nptr[i] == NULL) - { - /* a scalar leaf OR table, - inspect remaining instance number / table index */ - np->ident_len = ident_len; - np->ident = ident; - return (struct mib_node*)an; - } - else - { - /* follow next child pointer */ - ident++; - ident_len--; - node = an->nptr[i]; - } - } - else - { - /* search failed, identifier mismatch (nosuchname) */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident)); - return NULL; - } - } - else - { - /* search failed, short object identifier (nosuchname) */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n")); - return NULL; - } - } - else if(node_type == MIB_NODE_LR) - { - struct mib_list_rootnode *lrn; - struct mib_list_node *ln; - - if (ident_len > 0) - { - /* list root node (internal 'RAM', variable length) */ - lrn = (struct mib_list_rootnode *)node; - ln = lrn->head; - /* iterate over list, head to tail */ - while ((ln != NULL) && (ln->objid != *ident)) - { - ln = ln->next; - } - if (ln != NULL) - { - /* found it, proceed to child */; - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); - if (ln->nptr == NULL) - { - np->ident_len = ident_len; - np->ident = ident; - return (struct mib_node*)lrn; - } - else - { - /* follow next child pointer */ - ident_len--; - ident++; - node = ln->nptr; - } - } - else - { - /* search failed */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident)); - return NULL; - } - } - else - { - /* search failed, short object identifier (nosuchname) */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n")); - return NULL; - } - } - else if(node_type == MIB_NODE_EX) - { - struct mib_external_node *en; - u16_t i, len; - - if (ident_len > 0) - { - /* external node (addressing and access via functions) */ - en = (struct mib_external_node *)node; - - i = 0; - len = en->level_length(en->addr_inf,ext_level); - while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0)) - { - i++; - } - if (i < len) - { - s32_t debug_id; - - en->get_objid(en->addr_inf,ext_level,i,&debug_id); - LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident)); - if ((ext_level + 1) == en->tree_levels) - { - np->ident_len = ident_len; - np->ident = ident; - return (struct mib_node*)en; - } - else - { - /* found it, proceed to child */ - ident_len--; - ident++; - ext_level++; - } - } - else - { - /* search failed */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident)); - return NULL; - } - } - else - { - /* search failed, short object identifier (nosuchname) */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n")); - return NULL; - } - } - else if (node_type == MIB_NODE_SC) - { - mib_scalar_node *sn; - - sn = (mib_scalar_node *)node; - if ((ident_len == 1) && (*ident == 0)) - { - np->ident_len = ident_len; - np->ident = ident; - return (struct mib_node*)sn; - } - else - { - /* search failed, short object identifier (nosuchname) */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n")); - return NULL; - } - } - else - { - /* unknown node_type */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type)); - return NULL; - } - } - /* done, found nothing */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node)); - return NULL; -} - -/** - * Test table for presence of at least one table entry. - */ -static u8_t -empty_table(struct mib_node *node) -{ - u8_t node_type; - u8_t empty = 0; - - if (node != NULL) - { - node_type = node->node_type; - if (node_type == MIB_NODE_LR) - { - struct mib_list_rootnode *lrn; - lrn = (struct mib_list_rootnode *)node; - if ((lrn->count == 0) || (lrn->head == NULL)) - { - empty = 1; - } - } - else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) - { - struct mib_array_node *an; - an = (struct mib_array_node *)node; - if ((an->maxlength == 0) || (an->nptr == NULL)) - { - empty = 1; - } - } - else if (node_type == MIB_NODE_EX) - { - struct mib_external_node *en; - en = (struct mib_external_node *)node; - if (en->tree_levels == 0) - { - empty = 1; - } - } - } - return empty; -} - -/** - * Tree expansion. - */ -struct mib_node * -snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) -{ - u8_t node_type, ext_level, climb_tree; - - ext_level = 0; - /* reset node stack */ - node_stack_cnt = 0; - while (node != NULL) - { - climb_tree = 0; - node_type = node->node_type; - if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) - { - struct mib_array_node *an; - u16_t i; - - /* array node (internal ROM or RAM, fixed length) */ - an = (struct mib_array_node *)node; - if (ident_len > 0) - { - i = 0; - while ((i < an->maxlength) && (an->objid[i] < *ident)) - { - i++; - } - if (i < an->maxlength) - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); - /* add identifier to oidret */ - oidret->id[oidret->len] = an->objid[i]; - (oidret->len)++; - - if (an->nptr[i] == NULL) - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); - /* leaf node (e.g. in a fixed size table) */ - if (an->objid[i] > *ident) - { - return (struct mib_node*)an; - } - else if ((i + 1) < an->maxlength) - { - /* an->objid[i] == *ident */ - (oidret->len)--; - oidret->id[oidret->len] = an->objid[i + 1]; - (oidret->len)++; - return (struct mib_node*)an; - } - else - { - /* (i + 1) == an->maxlength */ - (oidret->len)--; - climb_tree = 1; - } - } - else - { - u8_t j; - struct nse cur_node; - - LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); - /* non-leaf, store right child ptr and id */ - j = i + 1; - while ((j < an->maxlength) && (empty_table(an->nptr[j]))) - { - j++; - } - if (j < an->maxlength) - { - cur_node.r_ptr = an->nptr[j]; - cur_node.r_id = an->objid[j]; - cur_node.r_nl = 0; - } - else - { - cur_node.r_ptr = NULL; - } - push_node(&cur_node); - if (an->objid[i] == *ident) - { - ident_len--; - ident++; - } - else - { - /* an->objid[i] < *ident */ - ident_len = 0; - } - /* follow next child pointer */ - node = an->nptr[i]; - } - } - else - { - /* i == an->maxlength */ - climb_tree = 1; - } - } - else - { - u8_t j; - /* ident_len == 0, complete with leftmost '.thing' */ - j = 0; - while ((j < an->maxlength) && empty_table(an->nptr[j])) - { - j++; - } - if (j < an->maxlength) - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j])); - oidret->id[oidret->len] = an->objid[j]; - (oidret->len)++; - if (an->nptr[j] == NULL) - { - /* leaf node */ - return (struct mib_node*)an; - } - else - { - /* no leaf, continue */ - node = an->nptr[j]; - } - } - else - { - /* j == an->maxlength */ - climb_tree = 1; - } - } - } - else if(node_type == MIB_NODE_LR) - { - struct mib_list_rootnode *lrn; - struct mib_list_node *ln; - - /* list root node (internal 'RAM', variable length) */ - lrn = (struct mib_list_rootnode *)node; - if (ident_len > 0) - { - ln = lrn->head; - /* iterate over list, head to tail */ - while ((ln != NULL) && (ln->objid < *ident)) - { - ln = ln->next; - } - if (ln != NULL) - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); - oidret->id[oidret->len] = ln->objid; - (oidret->len)++; - if (ln->nptr == NULL) - { - /* leaf node */ - if (ln->objid > *ident) - { - return (struct mib_node*)lrn; - } - else if (ln->next != NULL) - { - /* ln->objid == *ident */ - (oidret->len)--; - oidret->id[oidret->len] = ln->next->objid; - (oidret->len)++; - return (struct mib_node*)lrn; - } - else - { - /* ln->next == NULL */ - (oidret->len)--; - climb_tree = 1; - } - } - else - { - struct mib_list_node *jn; - struct nse cur_node; - - /* non-leaf, store right child ptr and id */ - jn = ln->next; - while ((jn != NULL) && empty_table(jn->nptr)) - { - jn = jn->next; - } - if (jn != NULL) - { - cur_node.r_ptr = jn->nptr; - cur_node.r_id = jn->objid; - cur_node.r_nl = 0; - } - else - { - cur_node.r_ptr = NULL; - } - push_node(&cur_node); - if (ln->objid == *ident) - { - ident_len--; - ident++; - } - else - { - /* ln->objid < *ident */ - ident_len = 0; - } - /* follow next child pointer */ - node = ln->nptr; - } - - } - else - { - /* ln == NULL */ - climb_tree = 1; - } - } - else - { - struct mib_list_node *jn; - /* ident_len == 0, complete with leftmost '.thing' */ - jn = lrn->head; - while ((jn != NULL) && empty_table(jn->nptr)) - { - jn = jn->next; - } - if (jn != NULL) - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid)); - oidret->id[oidret->len] = jn->objid; - (oidret->len)++; - if (jn->nptr == NULL) - { - /* leaf node */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n")); - return (struct mib_node*)lrn; - } - else - { - /* no leaf, continue */ - node = jn->nptr; - } - } - else - { - /* jn == NULL */ - climb_tree = 1; - } - } - } - else if(node_type == MIB_NODE_EX) - { - struct mib_external_node *en; - s32_t ex_id; - - /* external node (addressing and access via functions) */ - en = (struct mib_external_node *)node; - if (ident_len > 0) - { - u16_t i, len; - - i = 0; - len = en->level_length(en->addr_inf,ext_level); - while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0)) - { - i++; - } - if (i < len) - { - /* add identifier to oidret */ - en->get_objid(en->addr_inf,ext_level,i,&ex_id); - LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident)); - oidret->id[oidret->len] = ex_id; - (oidret->len)++; - - if ((ext_level + 1) == en->tree_levels) - { - LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); - /* leaf node */ - if (ex_id > *ident) - { - return (struct mib_node*)en; - } - else if ((i + 1) < len) - { - /* ex_id == *ident */ - en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id); - (oidret->len)--; - oidret->id[oidret->len] = ex_id; - (oidret->len)++; - return (struct mib_node*)en; - } - else - { - /* (i + 1) == len */ - (oidret->len)--; - climb_tree = 1; - } - } - else - { - u8_t j; - struct nse cur_node; - - LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); - /* non-leaf, store right child ptr and id */ - j = i + 1; - if (j < len) - { - /* right node is the current external node */ - cur_node.r_ptr = node; - en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id); - cur_node.r_nl = ext_level + 1; - } - else - { - cur_node.r_ptr = NULL; - } - push_node(&cur_node); - if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0) - { - ident_len--; - ident++; - } - else - { - /* external id < *ident */ - ident_len = 0; - } - /* proceed to child */ - ext_level++; - } - } - else - { - /* i == len (en->level_len()) */ - climb_tree = 1; - } - } - else - { - /* ident_len == 0, complete with leftmost '.thing' */ - en->get_objid(en->addr_inf,ext_level,0,&ex_id); - LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id)); - oidret->id[oidret->len] = ex_id; - (oidret->len)++; - if ((ext_level + 1) == en->tree_levels) - { - /* leaf node */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n")); - return (struct mib_node*)en; - } - else - { - /* no leaf, proceed to child */ - ext_level++; - } - } - } - else if(node_type == MIB_NODE_SC) - { - mib_scalar_node *sn; - - /* scalar node */ - sn = (mib_scalar_node *)node; - if (ident_len > 0) - { - /* at .0 */ - climb_tree = 1; - } - else - { - /* ident_len == 0, complete object identifier */ - oidret->id[oidret->len] = 0; - (oidret->len)++; - /* leaf node */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n")); - return (struct mib_node*)sn; - } - } - else - { - /* unknown/unhandled node_type */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type)); - return NULL; - } - - if (climb_tree) - { - struct nse child; - - /* find right child ptr */ - child.r_ptr = NULL; - child.r_id = 0; - child.r_nl = 0; - while ((node_stack_cnt > 0) && (child.r_ptr == NULL)) - { - pop_node(&child); - /* trim returned oid */ - (oidret->len)--; - } - if (child.r_ptr != NULL) - { - /* incoming ident is useless beyond this point */ - ident_len = 0; - oidret->id[oidret->len] = child.r_id; - oidret->len++; - node = child.r_ptr; - ext_level = child.r_nl; - } - else - { - /* tree ends here ... */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n")); - return NULL; - } - } - } - /* done, found nothing */ - LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node)); - return NULL; -} - -/** - * Test object identifier for the iso.org.dod.internet prefix. - * - * @param ident_len the length of the supplied object identifier - * @param ident points to the array of sub identifiers - * @return 1 if it matches, 0 otherwise - */ -u8_t -snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident) -{ - if ((ident_len > 3) && - (ident[0] == 1) && (ident[1] == 3) && - (ident[2] == 6) && (ident[3] == 1)) - { - return 1; - } - else - { - return 0; - } -} - -/** - * Expands object identifier to the iso.org.dod.internet - * prefix for use in getnext operation. - * - * @param ident_len the length of the supplied object identifier - * @param ident points to the array of sub identifiers - * @param oidret points to returned expanded object identifier - * @return 1 if it matches, 0 otherwise - * - * @note ident_len 0 is allowed, expanding to the first known object id!! - */ -u8_t -snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) -{ - const s32_t *prefix_ptr; - s32_t *ret_ptr; - u8_t i; - - i = 0; - prefix_ptr = &prefix[0]; - ret_ptr = &oidret->id[0]; - ident_len = ((ident_len < 4)?ident_len:4); - while ((i < ident_len) && ((*ident) <= (*prefix_ptr))) - { - *ret_ptr++ = *prefix_ptr++; - ident++; - i++; - } - if (i == ident_len) - { - /* match, complete missing bits */ - while (i < 4) - { - *ret_ptr++ = *prefix_ptr++; - i++; - } - oidret->len = i; - return 1; - } - else - { - /* i != ident_len */ - return 0; - } -} - -#endif /* LWIP_SNMP */ diff --git a/components/net/lwip-1.3.2/src/core/snmp/msg_in.c b/components/net/lwip-1.3.2/src/core/snmp/msg_in.c deleted file mode 100644 index d0c3c75345..0000000000 --- a/components/net/lwip-1.3.2/src/core/snmp/msg_in.c +++ /dev/null @@ -1,1454 +0,0 @@ -/** - * @file - * SNMP input message processing (RFC1157). - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip_addr.h" -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "lwip/snmp_asn1.h" -#include "lwip/snmp_msg.h" -#include "lwip/snmp_structs.h" - -#include - -/* public (non-static) constants */ -/** SNMP v1 == 0 */ -const s32_t snmp_version = 0; -/** default SNMP community string */ -const char snmp_publiccommunity[7] = "public"; - -/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */ -struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS]; -/* UDP Protocol Control Block */ -struct udp_pcb *snmp1_pcb; - -static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); -static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); -static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); - - -/** - * Starts SNMP Agent. - * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161. - */ -void -snmp_init(void) -{ - struct snmp_msg_pstat *msg_ps; - u8_t i; - - snmp1_pcb = udp_new(); - if (snmp1_pcb != NULL) - { - udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT); - udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT); - } - msg_ps = &msg_input_list[0]; - for (i=0; istate = SNMP_MSG_EMPTY; - msg_ps->error_index = 0; - msg_ps->error_status = SNMP_ES_NOERROR; - msg_ps++; - } - trap_msg.pcb = snmp1_pcb; - /* The coldstart trap will only be output - if our outgoing interface is up & configured */ - snmp_coldstart_trap(); -} - -static void -snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error) -{ - snmp_varbind_list_free(&msg_ps->outvb); - msg_ps->outvb = msg_ps->invb; - msg_ps->invb.head = NULL; - msg_ps->invb.tail = NULL; - msg_ps->invb.count = 0; - msg_ps->error_status = error; - msg_ps->error_index = 1 + msg_ps->vb_idx; - snmp_send_response(msg_ps); - snmp_varbind_list_free(&msg_ps->outvb); - msg_ps->state = SNMP_MSG_EMPTY; -} - -static void -snmp_ok_response(struct snmp_msg_pstat *msg_ps) -{ - err_t err_ret; - - err_ret = snmp_send_response(msg_ps); - if (err_ret == ERR_MEM) - { - /* serious memory problem, can't return tooBig */ - } - else - { - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status)); - } - /* free varbinds (if available) */ - snmp_varbind_list_free(&msg_ps->invb); - snmp_varbind_list_free(&msg_ps->outvb); - msg_ps->state = SNMP_MSG_EMPTY; -} - -/** - * Service an internal or external event for SNMP GET. - * - * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) - * @param msg_ps points to the assosicated message process state - */ -static void -snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) -{ - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); - - if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) - { - struct mib_external_node *en; - struct snmp_name_ptr np; - - /* get_object_def() answer*/ - en = msg_ps->ext_mib_node; - np = msg_ps->ext_name_ptr; - - /* translate answer into a known lifeform */ - en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); - if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) - { - msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; - en->get_value_q(request_id, &msg_ps->ext_object_def); - } - else - { - en->get_object_def_pc(request_id, np.ident_len, np.ident); - /* search failed, object id points to unknown object (nosuchname) */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) - { - struct mib_external_node *en; - struct snmp_varbind *vb; - - /* get_value() answer */ - en = msg_ps->ext_mib_node; - - /* allocate output varbind */ - vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); - LWIP_ASSERT("vb != NULL",vb != NULL); - if (vb != NULL) - { - vb->next = NULL; - vb->prev = NULL; - - /* move name from invb to outvb */ - vb->ident = msg_ps->vb_ptr->ident; - vb->ident_len = msg_ps->vb_ptr->ident_len; - /* ensure this memory is refereced once only */ - msg_ps->vb_ptr->ident = NULL; - msg_ps->vb_ptr->ident_len = 0; - - vb->value_type = msg_ps->ext_object_def.asn_type; - vb->value_len = msg_ps->ext_object_def.v_len; - if (vb->value_len > 0) - { - vb->value = mem_malloc(vb->value_len); - LWIP_ASSERT("vb->value != NULL",vb->value != NULL); - if (vb->value != NULL) - { - en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); - snmp_varbind_tail_add(&msg_ps->outvb, vb); - /* search again (if vb_idx < msg_ps->invb.count) */ - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - else - { - en->get_value_pc(request_id, &msg_ps->ext_object_def); - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n")); - msg_ps->vb_ptr->ident = vb->ident; - msg_ps->vb_ptr->ident_len = vb->ident_len; - mem_free(vb); - snmp_error_response(msg_ps,SNMP_ES_TOOBIG); - } - } - else - { - /* vb->value_len == 0, empty value (e.g. empty string) */ - en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL); - vb->value = NULL; - snmp_varbind_tail_add(&msg_ps->outvb, vb); - /* search again (if vb_idx < msg_ps->invb.count) */ - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - } - else - { - en->get_value_pc(request_id, &msg_ps->ext_object_def); - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n")); - snmp_error_response(msg_ps,SNMP_ES_TOOBIG); - } - } - - while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && - (msg_ps->vb_idx < msg_ps->invb.count)) - { - struct mib_node *mn; - struct snmp_name_ptr np; - - if (msg_ps->vb_idx == 0) - { - msg_ps->vb_ptr = msg_ps->invb.head; - } - else - { - msg_ps->vb_ptr = msg_ps->vb_ptr->next; - } - /** test object identifier for .iso.org.dod.internet prefix */ - if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) - { - mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, - msg_ps->vb_ptr->ident + 4, &np); - if (mn != NULL) - { - if (mn->node_type == MIB_NODE_EX) - { - /* external object */ - struct mib_external_node *en = (struct mib_external_node*)mn; - - msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; - /* save en && args in msg_ps!! */ - msg_ps->ext_mib_node = en; - msg_ps->ext_name_ptr = np; - - en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); - } - else - { - /* internal object */ - struct obj_def object_def; - - msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; - mn->get_object_def(np.ident_len, np.ident, &object_def); - if (object_def.instance != MIB_OBJECT_NONE) - { - mn = mn; - } - else - { - /* search failed, object id points to unknown object (nosuchname) */ - mn = NULL; - } - if (mn != NULL) - { - struct snmp_varbind *vb; - - msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; - /* allocate output varbind */ - vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); - LWIP_ASSERT("vb != NULL",vb != NULL); - if (vb != NULL) - { - vb->next = NULL; - vb->prev = NULL; - - /* move name from invb to outvb */ - vb->ident = msg_ps->vb_ptr->ident; - vb->ident_len = msg_ps->vb_ptr->ident_len; - /* ensure this memory is refereced once only */ - msg_ps->vb_ptr->ident = NULL; - msg_ps->vb_ptr->ident_len = 0; - - vb->value_type = object_def.asn_type; - vb->value_len = object_def.v_len; - if (vb->value_len > 0) - { - vb->value = mem_malloc(vb->value_len); - LWIP_ASSERT("vb->value != NULL",vb->value != NULL); - if (vb->value != NULL) - { - mn->get_value(&object_def, vb->value_len, vb->value); - snmp_varbind_tail_add(&msg_ps->outvb, vb); - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - else - { - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n")); - msg_ps->vb_ptr->ident = vb->ident; - msg_ps->vb_ptr->ident_len = vb->ident_len; - mem_free(vb); - snmp_error_response(msg_ps,SNMP_ES_TOOBIG); - } - } - else - { - /* vb->value_len == 0, empty value (e.g. empty string) */ - vb->value = NULL; - snmp_varbind_tail_add(&msg_ps->outvb, vb); - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - } - else - { - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n")); - snmp_error_response(msg_ps,SNMP_ES_TOOBIG); - } - } - } - } - } - else - { - mn = NULL; - } - if (mn == NULL) - { - /* mn == NULL, noSuchName */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && - (msg_ps->vb_idx == msg_ps->invb.count)) - { - snmp_ok_response(msg_ps); - } -} - -/** - * Service an internal or external event for SNMP GETNEXT. - * - * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) - * @param msg_ps points to the assosicated message process state - */ -static void -snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) -{ - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); - - if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) - { - struct mib_external_node *en; - - /* get_object_def() answer*/ - en = msg_ps->ext_mib_node; - - /* translate answer into a known lifeform */ - en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def); - if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) - { - msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; - en->get_value_q(request_id, &msg_ps->ext_object_def); - } - else - { - en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]); - /* search failed, object id points to unknown object (nosuchname) */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) - { - struct mib_external_node *en; - struct snmp_varbind *vb; - - /* get_value() answer */ - en = msg_ps->ext_mib_node; - - vb = snmp_varbind_alloc(&msg_ps->ext_oid, - msg_ps->ext_object_def.asn_type, - msg_ps->ext_object_def.v_len); - if (vb != NULL) - { - en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); - snmp_varbind_tail_add(&msg_ps->outvb, vb); - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - else - { - en->get_value_pc(request_id, &msg_ps->ext_object_def); - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n")); - snmp_error_response(msg_ps,SNMP_ES_TOOBIG); - } - } - - while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && - (msg_ps->vb_idx < msg_ps->invb.count)) - { - struct mib_node *mn; - struct snmp_obj_id oid; - - if (msg_ps->vb_idx == 0) - { - msg_ps->vb_ptr = msg_ps->invb.head; - } - else - { - msg_ps->vb_ptr = msg_ps->vb_ptr->next; - } - if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid)) - { - if (msg_ps->vb_ptr->ident_len > 3) - { - /* can offset ident_len and ident */ - mn = snmp_expand_tree((struct mib_node*)&internet, - msg_ps->vb_ptr->ident_len - 4, - msg_ps->vb_ptr->ident + 4, &oid); - } - else - { - /* can't offset ident_len -4, ident + 4 */ - mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid); - } - } - else - { - mn = NULL; - } - if (mn != NULL) - { - if (mn->node_type == MIB_NODE_EX) - { - /* external object */ - struct mib_external_node *en = (struct mib_external_node*)mn; - - msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; - /* save en && args in msg_ps!! */ - msg_ps->ext_mib_node = en; - msg_ps->ext_oid = oid; - - en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]); - } - else - { - /* internal object */ - struct obj_def object_def; - struct snmp_varbind *vb; - - msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; - mn->get_object_def(1, &oid.id[oid.len - 1], &object_def); - - vb = snmp_varbind_alloc(&oid, object_def.asn_type, object_def.v_len); - if (vb != NULL) - { - msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; - mn->get_value(&object_def, object_def.v_len, vb->value); - snmp_varbind_tail_add(&msg_ps->outvb, vb); - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - else - { - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n")); - snmp_error_response(msg_ps,SNMP_ES_TOOBIG); - } - } - } - if (mn == NULL) - { - /* mn == NULL, noSuchName */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && - (msg_ps->vb_idx == msg_ps->invb.count)) - { - snmp_ok_response(msg_ps); - } -} - -/** - * Service an internal or external event for SNMP SET. - * - * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) - * @param msg_ps points to the assosicated message process state - */ -static void -snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) -{ - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); - - if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) - { - struct mib_external_node *en; - struct snmp_name_ptr np; - - /* get_object_def() answer*/ - en = msg_ps->ext_mib_node; - np = msg_ps->ext_name_ptr; - - /* translate answer into a known lifeform */ - en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); - if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) - { - msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST; - en->set_test_q(request_id, &msg_ps->ext_object_def); - } - else - { - en->get_object_def_pc(request_id, np.ident_len, np.ident); - /* search failed, object id points to unknown object (nosuchname) */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST) - { - struct mib_external_node *en; - - /* set_test() answer*/ - en = msg_ps->ext_mib_node; - - if (msg_ps->ext_object_def.access == MIB_OBJECT_READ_WRITE) - { - if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) && - (en->set_test_a(request_id,&msg_ps->ext_object_def, - msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) - { - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - else - { - en->set_test_pc(request_id,&msg_ps->ext_object_def); - /* bad value */ - snmp_error_response(msg_ps,SNMP_ES_BADVALUE); - } - } - else - { - en->set_test_pc(request_id,&msg_ps->ext_object_def); - /* object not available for set */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S) - { - struct mib_external_node *en; - struct snmp_name_ptr np; - - /* get_object_def() answer*/ - en = msg_ps->ext_mib_node; - np = msg_ps->ext_name_ptr; - - /* translate answer into a known lifeform */ - en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); - if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) - { - msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE; - en->set_value_q(request_id, &msg_ps->ext_object_def, - msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); - } - else - { - en->get_object_def_pc(request_id, np.ident_len, np.ident); - /* set_value failed, object has disappeared for some odd reason?? */ - snmp_error_response(msg_ps,SNMP_ES_GENERROR); - } - } - else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE) - { - struct mib_external_node *en; - - /** set_value_a() */ - en = msg_ps->ext_mib_node; - en->set_value_a(request_id, &msg_ps->ext_object_def, - msg_ps->vb_ptr->value_len, msg_ps->vb_ptr->value); - - /** @todo use set_value_pc() if toobig */ - msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; - msg_ps->vb_idx += 1; - } - - /* test all values before setting */ - while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && - (msg_ps->vb_idx < msg_ps->invb.count)) - { - struct mib_node *mn; - struct snmp_name_ptr np; - - if (msg_ps->vb_idx == 0) - { - msg_ps->vb_ptr = msg_ps->invb.head; - } - else - { - msg_ps->vb_ptr = msg_ps->vb_ptr->next; - } - /** test object identifier for .iso.org.dod.internet prefix */ - if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) - { - mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, - msg_ps->vb_ptr->ident + 4, &np); - if (mn != NULL) - { - if (mn->node_type == MIB_NODE_EX) - { - /* external object */ - struct mib_external_node *en = (struct mib_external_node*)mn; - - msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; - /* save en && args in msg_ps!! */ - msg_ps->ext_mib_node = en; - msg_ps->ext_name_ptr = np; - - en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); - } - else - { - /* internal object */ - struct obj_def object_def; - - msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; - mn->get_object_def(np.ident_len, np.ident, &object_def); - if (object_def.instance != MIB_OBJECT_NONE) - { - mn = mn; - } - else - { - /* search failed, object id points to unknown object (nosuchname) */ - mn = NULL; - } - if (mn != NULL) - { - msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST; - - if (object_def.access == MIB_OBJECT_READ_WRITE) - { - if ((object_def.asn_type == msg_ps->vb_ptr->value_type) && - (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) - { - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - msg_ps->vb_idx += 1; - } - else - { - /* bad value */ - snmp_error_response(msg_ps,SNMP_ES_BADVALUE); - } - } - else - { - /* object not available for set */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - } - } - } - else - { - mn = NULL; - } - if (mn == NULL) - { - /* mn == NULL, noSuchName */ - snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); - } - } - - if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && - (msg_ps->vb_idx == msg_ps->invb.count)) - { - msg_ps->vb_idx = 0; - msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; - } - - /* set all values "atomically" (be as "atomic" as possible) */ - while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && - (msg_ps->vb_idx < msg_ps->invb.count)) - { - struct mib_node *mn; - struct snmp_name_ptr np; - - if (msg_ps->vb_idx == 0) - { - msg_ps->vb_ptr = msg_ps->invb.head; - } - else - { - msg_ps->vb_ptr = msg_ps->vb_ptr->next; - } - /* skip iso prefix test, was done previously while settesting() */ - mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, - msg_ps->vb_ptr->ident + 4, &np); - /* check if object is still available - (e.g. external hot-plug thingy present?) */ - if (mn != NULL) - { - if (mn->node_type == MIB_NODE_EX) - { - /* external object */ - struct mib_external_node *en = (struct mib_external_node*)mn; - - msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S; - /* save en && args in msg_ps!! */ - msg_ps->ext_mib_node = en; - msg_ps->ext_name_ptr = np; - - en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); - } - else - { - /* internal object */ - struct obj_def object_def; - - msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S; - mn->get_object_def(np.ident_len, np.ident, &object_def); - msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; - mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); - msg_ps->vb_idx += 1; - } - } - } - if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && - (msg_ps->vb_idx == msg_ps->invb.count)) - { - /* simply echo the input if we can set it - @todo do we need to return the actual value? - e.g. if value is silently modified or behaves sticky? */ - msg_ps->outvb = msg_ps->invb; - msg_ps->invb.head = NULL; - msg_ps->invb.tail = NULL; - msg_ps->invb.count = 0; - snmp_ok_response(msg_ps); - } -} - - -/** - * Handle one internal or external event. - * Called for one async event. (recv external/private answer) - * - * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) - */ -void -snmp_msg_event(u8_t request_id) -{ - struct snmp_msg_pstat *msg_ps; - - if (request_id < SNMP_CONCURRENT_REQUESTS) - { - msg_ps = &msg_input_list[request_id]; - if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) - { - snmp_msg_getnext_event(request_id, msg_ps); - } - else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) - { - snmp_msg_get_event(request_id, msg_ps); - } - else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ) - { - snmp_msg_set_event(request_id, msg_ps); - } - } -} - - -/* lwIP UDP receive callback function */ -static void -snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) -{ - struct udp_hdr *udphdr; - - /* suppress unused argument warning */ - LWIP_UNUSED_ARG(arg); - /* peek in the UDP header (goto IP payload) */ - if(pbuf_header(p, UDP_HLEN)){ - LWIP_ASSERT("Can't move to UDP header", 0); - pbuf_free(p); - return; - } - udphdr = p->payload; - - /* check if datagram is really directed at us (including broadcast requests) */ - if ((pcb == snmp1_pcb) && (ntohs(udphdr->dest) == SNMP_IN_PORT)) - { - struct snmp_msg_pstat *msg_ps; - u8_t req_idx; - - /* traverse input message process list, look for SNMP_MSG_EMPTY */ - msg_ps = &msg_input_list[0]; - req_idx = 0; - while ((req_idxstate != SNMP_MSG_EMPTY)) - { - req_idx++; - msg_ps++; - } - if (req_idx != SNMP_CONCURRENT_REQUESTS) - { - err_t err_ret; - u16_t payload_len; - u16_t payload_ofs; - u16_t varbind_ofs = 0; - - /* accepting request */ - snmp_inc_snmpinpkts(); - /* record used 'protocol control block' */ - msg_ps->pcb = pcb; - /* source address (network order) */ - msg_ps->sip = *addr; - /* source port (host order (lwIP oddity)) */ - msg_ps->sp = port; - /* read UDP payload length from UDP header */ - payload_len = ntohs(udphdr->len) - UDP_HLEN; - - /* adjust to UDP payload */ - payload_ofs = UDP_HLEN; - - /* check total length, version, community, pdu type */ - err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps); - if (((msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) || - (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) || - (msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)) && - ((msg_ps->error_status == SNMP_ES_NOERROR) && - (msg_ps->error_index == 0)) ) - { - /* Only accept requests and requests without error (be robust) */ - err_ret = err_ret; - } - else - { - /* Reject response and trap headers or error requests as input! */ - err_ret = ERR_ARG; - } - if (err_ret == ERR_OK) - { - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community)); - - /* Builds a list of variable bindings. Copy the varbinds from the pbuf - chain to glue them when these are divided over two or more pbuf's. */ - err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps); - if ((err_ret == ERR_OK) && (msg_ps->invb.count > 0)) - { - /* we've decoded the incoming message, release input msg now */ - pbuf_free(p); - - msg_ps->error_status = SNMP_ES_NOERROR; - msg_ps->error_index = 0; - /* find object for each variable binding */ - msg_ps->state = SNMP_MSG_SEARCH_OBJ; - /* first variable binding from list to inspect */ - msg_ps->vb_idx = 0; - - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count)); - - /* handle input event and as much objects as possible in one go */ - snmp_msg_event(req_idx); - } - else - { - /* varbind-list decode failed, or varbind list empty. - drop request silently, do not return error! - (errors are only returned for a specific varbind failure) */ - pbuf_free(p); - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n")); - } - } - else - { - /* header check failed - drop request silently, do not return error! */ - pbuf_free(p); - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n")); - } - } - else - { - /* exceeding number of concurrent requests */ - pbuf_free(p); - } - } - else - { - /* datagram not for us */ - pbuf_free(p); - } -} - -/** - * Checks and decodes incoming SNMP message header, logs header errors. - * - * @param p points to pbuf chain of SNMP message (UDP payload) - * @param ofs points to first octet of SNMP message - * @param pdu_len the length of the UDP payload - * @param ofs_ret returns the ofset of the variable bindings - * @param m_stat points to the current message request state return - * @return - * - ERR_OK SNMP header is sane and accepted - * - ERR_ARG SNMP header is either malformed or rejected - */ -static err_t -snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) -{ - err_t derr; - u16_t len, ofs_base; - u8_t len_octets; - u8_t type; - s32_t version; - - ofs_base = ofs; - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || - (pdu_len != (1 + len_octets + len)) || - (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) - { - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - ofs += (1 + len_octets); - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) - { - /* can't decode or no integer (version) */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version); - if (derr != ERR_OK) - { - /* can't decode */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - if (version != 0) - { - /* not version 1 */ - snmp_inc_snmpinbadversions(); - return ERR_ARG; - } - ofs += (1 + len_octets + len); - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR))) - { - /* can't decode or no octet string (community) */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community); - if (derr != ERR_OK) - { - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - /* add zero terminator */ - len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN)); - m_stat->community[len] = 0; - m_stat->com_strlen = len; - if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0) - { - /** @todo: move this if we need to check more names */ - snmp_inc_snmpinbadcommunitynames(); - snmp_authfail_trap(); - return ERR_ARG; - } - ofs += (1 + len_octets + len); - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if (derr != ERR_OK) - { - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - switch(type) - { - case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ): - /* GetRequest PDU */ - snmp_inc_snmpingetrequests(); - derr = ERR_OK; - break; - case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ): - /* GetNextRequest PDU */ - snmp_inc_snmpingetnexts(); - derr = ERR_OK; - break; - case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP): - /* GetResponse PDU */ - snmp_inc_snmpingetresponses(); - derr = ERR_ARG; - break; - case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ): - /* SetRequest PDU */ - snmp_inc_snmpinsetrequests(); - derr = ERR_OK; - break; - case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP): - /* Trap PDU */ - snmp_inc_snmpintraps(); - derr = ERR_ARG; - break; - default: - snmp_inc_snmpinasnparseerrs(); - derr = ERR_ARG; - break; - } - if (derr != ERR_OK) - { - /* unsupported input PDU for this agent (no parse error) */ - return ERR_ARG; - } - m_stat->rt = type & 0x1F; - ofs += (1 + len_octets); - if (len != (pdu_len - (ofs - ofs_base))) - { - /* decoded PDU length does not equal actual payload length */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) - { - /* can't decode or no integer (request ID) */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid); - if (derr != ERR_OK) - { - /* can't decode */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - ofs += (1 + len_octets + len); - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) - { - /* can't decode or no integer (error-status) */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - /* must be noError (0) for incoming requests. - log errors for mib-2 completeness and for debug purposes */ - derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status); - if (derr != ERR_OK) - { - /* can't decode */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - switch (m_stat->error_status) - { - case SNMP_ES_TOOBIG: - snmp_inc_snmpintoobigs(); - break; - case SNMP_ES_NOSUCHNAME: - snmp_inc_snmpinnosuchnames(); - break; - case SNMP_ES_BADVALUE: - snmp_inc_snmpinbadvalues(); - break; - case SNMP_ES_READONLY: - snmp_inc_snmpinreadonlys(); - break; - case SNMP_ES_GENERROR: - snmp_inc_snmpingenerrs(); - break; - } - ofs += (1 + len_octets + len); - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) - { - /* can't decode or no integer (error-index) */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - /* must be 0 for incoming requests. - decode anyway to catch bad integers (and dirty tricks) */ - derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index); - if (derr != ERR_OK) - { - /* can't decode */ - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - ofs += (1 + len_octets + len); - *ofs_ret = ofs; - return ERR_OK; -} - -static err_t -snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) -{ - err_t derr; - u16_t len, vb_len; - u8_t len_octets; - u8_t type; - - /* variable binding list */ - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len); - if ((derr != ERR_OK) || - (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) - { - snmp_inc_snmpinasnparseerrs(); - return ERR_ARG; - } - ofs += (1 + len_octets); - - /* start with empty list */ - m_stat->invb.count = 0; - m_stat->invb.head = NULL; - m_stat->invb.tail = NULL; - - while (vb_len > 0) - { - struct snmp_obj_id oid, oid_value; - struct snmp_varbind *vb; - - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || - (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) || - (len == 0) || (len > vb_len)) - { - snmp_inc_snmpinasnparseerrs(); - /* free varbinds (if available) */ - snmp_varbind_list_free(&m_stat->invb); - return ERR_ARG; - } - ofs += (1 + len_octets); - vb_len -= (1 + len_octets); - - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID))) - { - /* can't decode object name length */ - snmp_inc_snmpinasnparseerrs(); - /* free varbinds (if available) */ - snmp_varbind_list_free(&m_stat->invb); - return ERR_ARG; - } - derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid); - if (derr != ERR_OK) - { - /* can't decode object name */ - snmp_inc_snmpinasnparseerrs(); - /* free varbinds (if available) */ - snmp_varbind_list_free(&m_stat->invb); - return ERR_ARG; - } - ofs += (1 + len_octets + len); - vb_len -= (1 + len_octets + len); - - snmp_asn1_dec_type(p, ofs, &type); - derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); - if (derr != ERR_OK) - { - /* can't decode object value length */ - snmp_inc_snmpinasnparseerrs(); - /* free varbinds (if available) */ - snmp_varbind_list_free(&m_stat->invb); - return ERR_ARG; - } - - switch (type) - { - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): - vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t)); - if (vb != NULL) - { - s32_t *vptr = vb->value; - - derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr); - snmp_varbind_tail_add(&m_stat->invb, vb); - } - else - { - derr = ERR_ARG; - } - break; - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): - vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t)); - if (vb != NULL) - { - u32_t *vptr = vb->value; - - derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr); - snmp_varbind_tail_add(&m_stat->invb, vb); - } - else - { - derr = ERR_ARG; - } - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): - vb = snmp_varbind_alloc(&oid, type, len); - if (vb != NULL) - { - derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value); - snmp_varbind_tail_add(&m_stat->invb, vb); - } - else - { - derr = ERR_ARG; - } - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): - vb = snmp_varbind_alloc(&oid, type, 0); - if (vb != NULL) - { - snmp_varbind_tail_add(&m_stat->invb, vb); - derr = ERR_OK; - } - else - { - derr = ERR_ARG; - } - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): - derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value); - if (derr == ERR_OK) - { - vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t)); - if (vb != NULL) - { - u8_t i = oid_value.len; - s32_t *vptr = vb->value; - - while(i > 0) - { - i--; - vptr[i] = oid_value.id[i]; - } - snmp_varbind_tail_add(&m_stat->invb, vb); - derr = ERR_OK; - } - else - { - derr = ERR_ARG; - } - } - break; - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): - if (len == 4) - { - /* must be exactly 4 octets! */ - vb = snmp_varbind_alloc(&oid, type, 4); - if (vb != NULL) - { - derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value); - snmp_varbind_tail_add(&m_stat->invb, vb); - } - else - { - derr = ERR_ARG; - } - } - else - { - derr = ERR_ARG; - } - break; - default: - derr = ERR_ARG; - break; - } - if (derr != ERR_OK) - { - snmp_inc_snmpinasnparseerrs(); - /* free varbinds (if available) */ - snmp_varbind_list_free(&m_stat->invb); - return ERR_ARG; - } - ofs += (1 + len_octets + len); - vb_len -= (1 + len_octets + len); - } - - if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ) - { - snmp_add_snmpintotalsetvars(m_stat->invb.count); - } - else - { - snmp_add_snmpintotalreqvars(m_stat->invb.count); - } - - *ofs_ret = ofs; - return ERR_OK; -} - -struct snmp_varbind* -snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len) -{ - struct snmp_varbind *vb; - - vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); - LWIP_ASSERT("vb != NULL",vb != NULL); - if (vb != NULL) - { - u8_t i; - - vb->next = NULL; - vb->prev = NULL; - i = oid->len; - vb->ident_len = i; - if (i > 0) - { - /* allocate array of s32_t for our object identifier */ - vb->ident = (s32_t*)mem_malloc(sizeof(s32_t) * i); - LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL); - if (vb->ident == NULL) - { - mem_free(vb); - return NULL; - } - while(i > 0) - { - i--; - vb->ident[i] = oid->id[i]; - } - } - else - { - /* i == 0, pass zero length object identifier */ - vb->ident = NULL; - } - vb->value_type = type; - vb->value_len = len; - if (len > 0) - { - /* allocate raw bytes for our object value */ - vb->value = mem_malloc(len); - LWIP_ASSERT("vb->value != NULL",vb->value != NULL); - if (vb->value == NULL) - { - if (vb->ident != NULL) - { - mem_free(vb->ident); - } - mem_free(vb); - return NULL; - } - } - else - { - /* ASN1_NUL type, or zero length ASN1_OC_STR */ - vb->value = NULL; - } - } - return vb; -} - -void -snmp_varbind_free(struct snmp_varbind *vb) -{ - if (vb->value != NULL ) - { - mem_free(vb->value); - } - if (vb->ident != NULL ) - { - mem_free(vb->ident); - } - mem_free(vb); -} - -void -snmp_varbind_list_free(struct snmp_varbind_root *root) -{ - struct snmp_varbind *vb, *prev; - - vb = root->tail; - while ( vb != NULL ) - { - prev = vb->prev; - snmp_varbind_free(vb); - vb = prev; - } - root->count = 0; - root->head = NULL; - root->tail = NULL; -} - -void -snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb) -{ - if (root->count == 0) - { - /* add first varbind to list */ - root->head = vb; - root->tail = vb; - } - else - { - /* add nth varbind to list tail */ - root->tail->next = vb; - vb->prev = root->tail; - root->tail = vb; - } - root->count += 1; -} - -struct snmp_varbind* -snmp_varbind_tail_remove(struct snmp_varbind_root *root) -{ - struct snmp_varbind* vb; - - if (root->count > 0) - { - /* remove tail varbind */ - vb = root->tail; - root->tail = vb->prev; - vb->prev->next = NULL; - root->count -= 1; - } - else - { - /* nothing to remove */ - vb = NULL; - } - return vb; -} - -#endif /* LWIP_SNMP */ diff --git a/components/net/lwip-1.3.2/src/core/snmp/msg_out.c b/components/net/lwip-1.3.2/src/core/snmp/msg_out.c deleted file mode 100644 index b705aaca78..0000000000 --- a/components/net/lwip-1.3.2/src/core/snmp/msg_out.c +++ /dev/null @@ -1,683 +0,0 @@ -/** - * @file - * SNMP output message processing (RFC1157). - * - * Output responses and traps are build in two passes: - * - * Pass 0: iterate over the output message backwards to determine encoding lengths - * Pass 1: the actual forward encoding of internal form into ASN1 - * - * The single-pass encoding method described by Comer & Stevens - * requires extra buffer space and copying for reversal of the packet. - * The buffer requirement can be prohibitively large for big payloads - * (>= 484) therefore we use the two encoding passes. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/udp.h" -#include "lwip/netif.h" -#include "lwip/snmp.h" -#include "lwip/snmp_asn1.h" -#include "lwip/snmp_msg.h" - -struct snmp_trap_dst -{ - /* destination IP address in network order */ - struct ip_addr dip; - /* set to 0 when disabled, >0 when enabled */ - u8_t enable; -}; -struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS]; - -/** TRAP message structure */ -struct snmp_msg_trap trap_msg; - -static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len); -static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len); -static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root); - -static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p); -static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p); -static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs); - -/** - * Sets enable switch for this trap destination. - * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 - * @param enable switch if 0 destination is disabled >0 enabled. - */ -void -snmp_trap_dst_enable(u8_t dst_idx, u8_t enable) -{ - if (dst_idx < SNMP_TRAP_DESTINATIONS) - { - trap_dst[dst_idx].enable = enable; - } -} - -/** - * Sets IPv4 address for this trap destination. - * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 - * @param dst IPv4 address in host order. - */ -void -snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst) -{ - if (dst_idx < SNMP_TRAP_DESTINATIONS) - { - trap_dst[dst_idx].dip.addr = htonl(dst->addr); - } -} - -/** - * Sends a 'getresponse' message to the request originator. - * - * @param m_stat points to the current message request state source - * @return ERR_OK when success, ERR_MEM if we're out of memory - * - * @note the caller is responsible for filling in outvb in the m_stat - * and provide error-status and index (except for tooBig errors) ... - */ -err_t -snmp_send_response(struct snmp_msg_pstat *m_stat) -{ - struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0}; - struct pbuf *p; - u16_t tot_len; - err_t err; - - /* pass 0, calculate length fields */ - tot_len = snmp_varbind_list_sum(&m_stat->outvb); - tot_len = snmp_resp_header_sum(m_stat, tot_len); - - /* try allocating pbuf(s) for complete response */ - p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); - if (p == NULL) - { - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n")); - - /* can't construct reply, return error-status tooBig */ - m_stat->error_status = SNMP_ES_TOOBIG; - m_stat->error_index = 0; - /* pass 0, recalculate lengths, for empty varbind-list */ - tot_len = snmp_varbind_list_sum(&emptyvb); - tot_len = snmp_resp_header_sum(m_stat, tot_len); - /* retry allocation once for header and empty varbind-list */ - p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); - } - if (p != NULL) - { - /* first pbuf alloc try or retry alloc success */ - u16_t ofs; - - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n")); - - /* pass 1, size error, encode packet ino the pbuf(s) */ - ofs = snmp_resp_header_enc(m_stat, p); - if (m_stat->error_status == SNMP_ES_TOOBIG) - { - snmp_varbind_list_enc(&emptyvb, p, ofs); - } - else - { - snmp_varbind_list_enc(&m_stat->outvb, p, ofs); - } - - switch (m_stat->error_status) - { - case SNMP_ES_TOOBIG: - snmp_inc_snmpouttoobigs(); - break; - case SNMP_ES_NOSUCHNAME: - snmp_inc_snmpoutnosuchnames(); - break; - case SNMP_ES_BADVALUE: - snmp_inc_snmpoutbadvalues(); - break; - case SNMP_ES_GENERROR: - snmp_inc_snmpoutgenerrs(); - break; - } - snmp_inc_snmpoutgetresponses(); - snmp_inc_snmpoutpkts(); - - /** @todo do we need separate rx and tx pcbs for threaded case? */ - /** connect to the originating source */ - udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp); - err = udp_send(m_stat->pcb, p); - if (err == ERR_MEM) - { - /** @todo release some memory, retry and return tooBig? tooMuchHassle? */ - err = ERR_MEM; - } - else - { - err = ERR_OK; - } - /** disassociate remote address and port with this pcb */ - udp_disconnect(m_stat->pcb); - - pbuf_free(p); - LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n")); - return err; - } - else - { - /* first pbuf alloc try or retry alloc failed - very low on memory, couldn't return tooBig */ - return ERR_MEM; - } -} - - -/** - * Sends an generic or enterprise specific trap message. - * - * @param generic_trap is the trap code - * @param eoid points to enterprise object identifier - * @param specific_trap used for enterprise traps when generic_trap == 6 - * @return ERR_OK when success, ERR_MEM if we're out of memory - * - * @note the caller is responsible for filling in outvb in the trap_msg - * @note the use of the enterpise identifier field - * is per RFC1215. - * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps - * and .iso.org.dod.internet.private.enterprises.yourenterprise - * (sysObjectID) for specific traps. - */ -err_t -snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap) -{ - struct snmp_trap_dst *td; - struct netif *dst_if; - struct ip_addr dst_ip; - struct pbuf *p; - u16_t i,tot_len; - - for (i=0, td = &trap_dst[0]; ienable != 0) && (td->dip.addr != 0)) - { - /* network order trap destination */ - trap_msg.dip.addr = td->dip.addr; - /* lookup current source address for this dst */ - dst_if = ip_route(&td->dip); - dst_ip.addr = ntohl(dst_if->ip_addr.addr); - trap_msg.sip_raw[0] = dst_ip.addr >> 24; - trap_msg.sip_raw[1] = dst_ip.addr >> 16; - trap_msg.sip_raw[2] = dst_ip.addr >> 8; - trap_msg.sip_raw[3] = dst_ip.addr; - trap_msg.gen_trap = generic_trap; - trap_msg.spc_trap = specific_trap; - if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC) - { - /* enterprise-Specific trap */ - trap_msg.enterprise = eoid; - } - else - { - /* generic (MIB-II) trap */ - snmp_get_snmpgrpid_ptr(&trap_msg.enterprise); - } - snmp_get_sysuptime(&trap_msg.ts); - - /* pass 0, calculate length fields */ - tot_len = snmp_varbind_list_sum(&trap_msg.outvb); - tot_len = snmp_trap_header_sum(&trap_msg, tot_len); - - /* allocate pbuf(s) */ - p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); - if (p != NULL) - { - u16_t ofs; - - /* pass 1, encode packet ino the pbuf(s) */ - ofs = snmp_trap_header_enc(&trap_msg, p); - snmp_varbind_list_enc(&trap_msg.outvb, p, ofs); - - snmp_inc_snmpouttraps(); - snmp_inc_snmpoutpkts(); - - /** connect to the TRAP destination */ - udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT); - udp_send(trap_msg.pcb, p); - /** disassociate remote address and port with this pcb */ - udp_disconnect(trap_msg.pcb); - - pbuf_free(p); - } - else - { - return ERR_MEM; - } - } - } - return ERR_OK; -} - -void -snmp_coldstart_trap(void) -{ - trap_msg.outvb.head = NULL; - trap_msg.outvb.tail = NULL; - trap_msg.outvb.count = 0; - snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0); -} - -void -snmp_authfail_trap(void) -{ - u8_t enable; - snmp_get_snmpenableauthentraps(&enable); - if (enable == 1) - { - trap_msg.outvb.head = NULL; - trap_msg.outvb.tail = NULL; - trap_msg.outvb.count = 0; - snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0); - } -} - -/** - * Sums response header field lengths from tail to head and - * returns resp_header_lengths for second encoding pass. - * - * @param vb_len varbind-list length - * @param rhl points to returned header lengths - * @return the required lenght for encoding the response header - */ -static u16_t -snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len) -{ - u16_t tot_len; - struct snmp_resp_header_lengths *rhl; - - rhl = &m_stat->rhl; - tot_len = vb_len; - snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen); - snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen); - tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen; - - snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen); - snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen); - tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen; - - snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen); - snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen); - tot_len += 1 + rhl->ridlenlen + rhl->ridlen; - - rhl->pdulen = tot_len; - snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen); - tot_len += 1 + rhl->pdulenlen; - - rhl->comlen = m_stat->com_strlen; - snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen); - tot_len += 1 + rhl->comlenlen + rhl->comlen; - - snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen); - snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen); - tot_len += 1 + rhl->verlen + rhl->verlenlen; - - rhl->seqlen = tot_len; - snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen); - tot_len += 1 + rhl->seqlenlen; - - return tot_len; -} - -/** - * Sums trap header field lengths from tail to head and - * returns trap_header_lengths for second encoding pass. - * - * @param vb_len varbind-list length - * @param thl points to returned header lengths - * @return the required lenght for encoding the trap header - */ -static u16_t -snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len) -{ - u16_t tot_len; - struct snmp_trap_header_lengths *thl; - - thl = &m_trap->thl; - tot_len = vb_len; - - snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen); - snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen); - tot_len += 1 + thl->tslen + thl->tslenlen; - - snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen); - snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen); - tot_len += 1 + thl->strplen + thl->strplenlen; - - snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen); - snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen); - tot_len += 1 + thl->gtrplen + thl->gtrplenlen; - - thl->aaddrlen = 4; - snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen); - tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen; - - snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen); - snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen); - tot_len += 1 + thl->eidlen + thl->eidlenlen; - - thl->pdulen = tot_len; - snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen); - tot_len += 1 + thl->pdulenlen; - - thl->comlen = sizeof(snmp_publiccommunity) - 1; - snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen); - tot_len += 1 + thl->comlenlen + thl->comlen; - - snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen); - snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen); - tot_len += 1 + thl->verlen + thl->verlenlen; - - thl->seqlen = tot_len; - snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen); - tot_len += 1 + thl->seqlenlen; - - return tot_len; -} - -/** - * Sums varbind lengths from tail to head and - * annotates lengths in varbind for second encoding pass. - * - * @param root points to the root of the variable binding list - * @return the required lenght for encoding the variable bindings - */ -static u16_t -snmp_varbind_list_sum(struct snmp_varbind_root *root) -{ - struct snmp_varbind *vb; - u32_t *uint_ptr; - s32_t *sint_ptr; - u16_t tot_len; - - tot_len = 0; - vb = root->tail; - while ( vb != NULL ) - { - /* encoded value lenght depends on type */ - switch (vb->value_type) - { - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): - sint_ptr = vb->value; - snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen); - break; - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): - uint_ptr = vb->value; - snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen); - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): - vb->vlen = vb->value_len; - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): - sint_ptr = vb->value; - snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen); - break; - default: - /* unsupported type */ - vb->vlen = 0; - break; - }; - /* encoding length of value length field */ - snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen); - snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen); - snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen); - - vb->seqlen = 1 + vb->vlenlen + vb->vlen; - vb->seqlen += 1 + vb->olenlen + vb->olen; - snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen); - - /* varbind seq */ - tot_len += 1 + vb->seqlenlen + vb->seqlen; - - vb = vb->prev; - } - - /* varbind-list seq */ - root->seqlen = tot_len; - snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen); - tot_len += 1 + root->seqlenlen; - - return tot_len; -} - -/** - * Encodes response header from head to tail. - */ -static u16_t -snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p) -{ - u16_t ofs; - - ofs = 0; - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen); - ofs += m_stat->rhl.seqlenlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen); - ofs += m_stat->rhl.verlenlen; - snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version); - ofs += m_stat->rhl.verlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen); - ofs += m_stat->rhl.comlenlen; - snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community); - ofs += m_stat->rhl.comlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen); - ofs += m_stat->rhl.pdulenlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen); - ofs += m_stat->rhl.ridlenlen; - snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid); - ofs += m_stat->rhl.ridlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen); - ofs += m_stat->rhl.errstatlenlen; - snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status); - ofs += m_stat->rhl.errstatlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen); - ofs += m_stat->rhl.erridxlenlen; - snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index); - ofs += m_stat->rhl.erridxlen; - - return ofs; -} - -/** - * Encodes trap header from head to tail. - */ -static u16_t -snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p) -{ - u16_t ofs; - - ofs = 0; - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen); - ofs += m_trap->thl.seqlenlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen); - ofs += m_trap->thl.verlenlen; - snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version); - ofs += m_trap->thl.verlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen); - ofs += m_trap->thl.comlenlen; - snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]); - ofs += m_trap->thl.comlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen); - ofs += m_trap->thl.pdulenlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen); - ofs += m_trap->thl.eidlenlen; - snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]); - ofs += m_trap->thl.eidlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen); - ofs += m_trap->thl.aaddrlenlen; - snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]); - ofs += m_trap->thl.aaddrlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen); - ofs += m_trap->thl.gtrplenlen; - snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap); - ofs += m_trap->thl.gtrplen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen); - ofs += m_trap->thl.strplenlen; - snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap); - ofs += m_trap->thl.strplen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen); - ofs += m_trap->thl.tslenlen; - snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts); - ofs += m_trap->thl.tslen; - - return ofs; -} - -/** - * Encodes varbind list from head to tail. - */ -static u16_t -snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs) -{ - struct snmp_varbind *vb; - s32_t *sint_ptr; - u32_t *uint_ptr; - u8_t *raw_ptr; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, root->seqlen); - ofs += root->seqlenlen; - - vb = root->head; - while ( vb != NULL ) - { - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, vb->seqlen); - ofs += vb->seqlenlen; - - snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); - ofs += 1; - snmp_asn1_enc_length(p, ofs, vb->olen); - ofs += vb->olenlen; - snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]); - ofs += vb->olen; - - snmp_asn1_enc_type(p, ofs, vb->value_type); - ofs += 1; - snmp_asn1_enc_length(p, ofs, vb->vlen); - ofs += vb->vlenlen; - - switch (vb->value_type) - { - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): - sint_ptr = vb->value; - snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr); - break; - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): - uint_ptr = vb->value; - snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr); - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): - case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): - raw_ptr = vb->value; - snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr); - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): - break; - case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): - sint_ptr = vb->value; - snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr); - break; - default: - /* unsupported type */ - break; - }; - ofs += vb->vlen; - vb = vb->next; - } - return ofs; -} - -#endif /* LWIP_SNMP */ diff --git a/components/net/lwip-1.3.2/src/core/sys.c b/components/net/lwip-1.3.2/src/core/sys.c deleted file mode 100644 index cb5e86a7e6..0000000000 --- a/components/net/lwip-1.3.2/src/core/sys.c +++ /dev/null @@ -1,346 +0,0 @@ -/** - * @file - * lwIP Operating System abstraction - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if (NO_SYS == 0) /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sys.h" -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/tcpip.h" - -/** - * Struct used for sys_sem_wait_timeout() to tell wether the time - * has run out or the semaphore has really become available. - */ -struct sswt_cb -{ - s16_t timeflag; - sys_sem_t *psem; -}; - -/** - * Wait (forever) for a message to arrive in an mbox. - * While waiting, timeouts (for this thread) are processed. - * - * @param mbox the mbox to fetch the message from - * @param msg the place to store the message - */ -void -sys_mbox_fetch(sys_mbox_t mbox, void **msg) -{ - u32_t time_needed; - struct sys_timeouts *timeouts; - struct sys_timeo *tmptimeout; - sys_timeout_handler h; - void *arg; - - again: - timeouts = sys_arch_timeouts(); - - if (!timeouts || !timeouts->next) { - UNLOCK_TCPIP_CORE(); - time_needed = sys_arch_mbox_fetch(mbox, msg, 0); - LOCK_TCPIP_CORE(); - } else { - if (timeouts->next->time > 0) { - UNLOCK_TCPIP_CORE(); - time_needed = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time); - LOCK_TCPIP_CORE(); - } else { - time_needed = SYS_ARCH_TIMEOUT; - } - - if (time_needed == SYS_ARCH_TIMEOUT) { - /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message - could be fetched. We should now call the timeout handler and - deallocate the memory allocated for the timeout. */ - tmptimeout = timeouts->next; - timeouts->next = tmptimeout->next; - h = tmptimeout->h; - arg = tmptimeout->arg; - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (h != NULL) { - LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", *(void**)&h, arg)); - h(arg); - } - - /* We try again to fetch a message from the mbox. */ - goto again; - } else { - /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout - occured. The time variable is set to the number of - milliseconds we waited for the message. */ - if (time_needed < timeouts->next->time) { - timeouts->next->time -= time_needed; - } else { - timeouts->next->time = 0; - } - } - } -} - -/** - * Wait (forever) for a semaphore to become available. - * While waiting, timeouts (for this thread) are processed. - * - * @param sem semaphore to wait for - */ -void -sys_sem_wait(sys_sem_t sem) -{ - u32_t time_needed; - struct sys_timeouts *timeouts; - struct sys_timeo *tmptimeout; - sys_timeout_handler h; - void *arg; - - again: - - timeouts = sys_arch_timeouts(); - - if (!timeouts || !timeouts->next) { - sys_arch_sem_wait(sem, 0); - } else { - if (timeouts->next->time > 0) { - time_needed = sys_arch_sem_wait(sem, timeouts->next->time); - } else { - time_needed = SYS_ARCH_TIMEOUT; - } - - if (time_needed == SYS_ARCH_TIMEOUT) { - /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message - could be fetched. We should now call the timeout handler and - deallocate the memory allocated for the timeout. */ - tmptimeout = timeouts->next; - timeouts->next = tmptimeout->next; - h = tmptimeout->h; - arg = tmptimeout->arg; - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (h != NULL) { - LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", *(void**)&h, (void *)arg)); - h(arg); - } - - /* We try again to fetch a message from the mbox. */ - goto again; - } else { - /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout - occured. The time variable is set to the number of - milliseconds we waited for the message. */ - if (time_needed < timeouts->next->time) { - timeouts->next->time -= time_needed; - } else { - timeouts->next->time = 0; - } - } - } -} - -/** - * Create a one-shot timer (aka timeout). Timeouts are processed in the - * following cases: - * - while waiting for a message using sys_mbox_fetch() - * - while waiting for a semaphore using sys_sem_wait() or sys_sem_wait_timeout() - * - while sleeping using the inbuilt sys_msleep() - * - * @param msecs time in milliseconds after that the timer should expire - * @param h callback function to call when msecs have elapsed - * @param arg argument to pass to the callback function - */ -void -sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg) -{ - struct sys_timeouts *timeouts; - struct sys_timeo *timeout, *t; - - timeout = memp_malloc(MEMP_SYS_TIMEOUT); - if (timeout == NULL) { - LWIP_ASSERT("sys_timeout: timeout != NULL", timeout != NULL); - return; - } - timeout->next = NULL; - timeout->h = h; - timeout->arg = arg; - timeout->time = msecs; - - timeouts = sys_arch_timeouts(); - - LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n", - (void *)timeout, msecs, *(void**)&h, (void *)arg)); - - if (timeouts == NULL) { - LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL); - return; - } - - if (timeouts->next == NULL) { - timeouts->next = timeout; - return; - } - - if (timeouts->next->time > msecs) { - timeouts->next->time -= msecs; - timeout->next = timeouts->next; - timeouts->next = timeout; - } else { - for(t = timeouts->next; t != NULL; t = t->next) { - timeout->time -= t->time; - if (t->next == NULL || t->next->time > timeout->time) { - if (t->next != NULL) { - t->next->time -= timeout->time; - } - timeout->next = t->next; - t->next = timeout; - break; - } - } - } -} - -/** - * Go through timeout list (for this task only) and remove the first matching - * entry, even though the timeout has not triggered yet. - * - * @note This function only works as expected if there is only one timeout - * calling 'h' in the list of timeouts. - * - * @param h callback function that would be called by the timeout - * @param arg callback argument that would be passed to h -*/ -void -sys_untimeout(sys_timeout_handler h, void *arg) -{ - struct sys_timeouts *timeouts; - struct sys_timeo *prev_t, *t; - - timeouts = sys_arch_timeouts(); - - if (timeouts == NULL) { - LWIP_ASSERT("sys_untimeout: timeouts != NULL", timeouts != NULL); - return; - } - if (timeouts->next == NULL) { - return; - } - - for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) { - if ((t->h == h) && (t->arg == arg)) { - /* We have a match */ - /* Unlink from previous in list */ - if (prev_t == NULL) { - timeouts->next = t->next; - } else { - prev_t->next = t->next; - } - /* If not the last one, add time of this one back to next */ - if (t->next != NULL) { - t->next->time += t->time; - } - memp_free(MEMP_SYS_TIMEOUT, t); - return; - } - } - return; -} - -/** - * Timeout handler function for sys_sem_wait_timeout() - * - * @param arg struct sswt_cb* used to signal a semaphore and end waiting. - */ -static void -sswt_handler(void *arg) -{ - struct sswt_cb *sswt_cb = (struct sswt_cb *) arg; - - /* Timeout. Set flag to TRUE and signal semaphore */ - sswt_cb->timeflag = 1; - sys_sem_signal(*(sswt_cb->psem)); -} - -/** - * Wait for a semaphore with timeout (specified in ms) - * - * @param sem semaphore to wait - * @param timeout timeout in ms (0: wait forever) - * @return 0 on timeout, 1 otherwise - */ -int -sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout) -{ - struct sswt_cb sswt_cb; - - sswt_cb.psem = &sem; - sswt_cb.timeflag = 0; - - /* If timeout is zero, then just wait forever */ - if (timeout > 0) { - /* Create a timer and pass it the address of our flag */ - sys_timeout(timeout, sswt_handler, &sswt_cb); - } - sys_sem_wait(sem); - /* Was it a timeout? */ - if (sswt_cb.timeflag) { - /* timeout */ - return 0; - } else { - /* Not a timeout. Remove timeout entry */ - sys_untimeout(sswt_handler, &sswt_cb); - return 1; - } -} - -/** - * Sleep for some ms. Timeouts are processed while sleeping. - * - * @param ms number of milliseconds to sleep - */ -void -sys_msleep(u32_t ms) -{ - sys_sem_t delaysem = sys_sem_new(0); - - sys_sem_wait_timeout(delaysem, ms); - - sys_sem_free(delaysem); -} - - -#endif /* NO_SYS */ diff --git a/components/net/lwip-1.3.2/src/core/tcp.c b/components/net/lwip-1.3.2/src/core/tcp.c deleted file mode 100644 index 29cdf185d4..0000000000 --- a/components/net/lwip-1.3.2/src/core/tcp.c +++ /dev/null @@ -1,1461 +0,0 @@ -/** - * @file - * Transmission Control Protocol for IP - * - * This file contains common functions for the TCP implementation, such as functinos - * for manipulating the data structures and the TCP timer functions. TCP functions - * related to input and output is found in tcp_in.c and tcp_out.c respectively. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/snmp.h" -#include "lwip/tcp.h" -#include "lwip/debug.h" -#include "lwip/stats.h" - -#include - -const char *tcp_state_str[] = { - "CLOSED", - "LISTEN", - "SYN_SENT", - "SYN_RCVD", - "ESTABLISHED", - "FIN_WAIT_1", - "FIN_WAIT_2", - "CLOSE_WAIT", - "CLOSING", - "LAST_ACK", - "TIME_WAIT" -}; - -/* Incremented every coarse grained timer shot (typically every 500 ms). */ -u32_t tcp_ticks; -const u8_t tcp_backoff[13] = - { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; - /* Times per slowtmr hits */ -const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 }; - -/* The TCP PCB lists. */ - -/** List of all TCP PCBs bound but not yet (connected || listening) */ -struct tcp_pcb *tcp_bound_pcbs; -/** List of all TCP PCBs in LISTEN state */ -union tcp_listen_pcbs_t tcp_listen_pcbs; -/** List of all TCP PCBs that are in a state in which - * they accept or send data. */ -struct tcp_pcb *tcp_active_pcbs; -/** List of all TCP PCBs in TIME-WAIT state */ -struct tcp_pcb *tcp_tw_pcbs; - -struct tcp_pcb *tcp_tmp_pcb; - -static u8_t tcp_timer; -static u16_t tcp_new_port(void); - -/** - * Called periodically to dispatch TCP timers. - * - */ -void -tcp_tmr(void) -{ - /* Call tcp_fasttmr() every 250 ms */ - tcp_fasttmr(); - - if (++tcp_timer & 1) { - /* Call tcp_tmr() every 500 ms, i.e., every other timer - tcp_tmr() is called. */ - tcp_slowtmr(); - } -} - -/** - * Closes the connection held by the PCB. - * - * Listening pcbs are freed and may not be referenced any more. - * Connection pcbs are freed if not yet connected and may not be referenced - * any more. If a connection is established (at least SYN received or in - * a closing state), the connection is closed, and put in a closing state. - * The pcb is then automatically freed in tcp_slowtmr(). It is therefore - * unsafe to reference it. - * - * @param pcb the tcp_pcb to close - * @return ERR_OK if connection has been closed - * another err_t if closing failed and pcb is not freed - */ -err_t -tcp_close(struct tcp_pcb *pcb) -{ - err_t err; - -#if TCP_DEBUG - LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ - - switch (pcb->state) { - case CLOSED: - /* Closing a pcb in the CLOSED state might seem erroneous, - * however, it is in this state once allocated and as yet unused - * and the user needs some way to free it should the need arise. - * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) - * or for a pcb that has been used and then entered the CLOSED state - * is erroneous, but this should never happen as the pcb has in those cases - * been freed, and so any remaining handles are bogus. */ - err = ERR_OK; - TCP_RMV(&tcp_bound_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - pcb = NULL; - break; - case LISTEN: - err = ERR_OK; - tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); - memp_free(MEMP_TCP_PCB_LISTEN, pcb); - pcb = NULL; - break; - case SYN_SENT: - err = ERR_OK; - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - pcb = NULL; - snmp_inc_tcpattemptfails(); - break; - case SYN_RCVD: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - snmp_inc_tcpattemptfails(); - pcb->state = FIN_WAIT_1; - } - break; - case ESTABLISHED: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - snmp_inc_tcpestabresets(); - pcb->state = FIN_WAIT_1; - } - break; - case CLOSE_WAIT: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - snmp_inc_tcpestabresets(); - pcb->state = LAST_ACK; - } - break; - default: - /* Has already been closed, do nothing. */ - err = ERR_OK; - pcb = NULL; - break; - } - - if (pcb != NULL && err == ERR_OK) { - /* To ensure all data has been sent when tcp_close returns, we have - to make sure tcp_output doesn't fail. - Since we don't really have to ensure all data has been sent when tcp_close - returns (unsent data is sent from tcp timer functions, also), we don't care - for the return value of tcp_output for now. */ - /* @todo: When implementing SO_LINGER, this must be changed somehow: - If SOF_LINGER is set, the data should be sent when tcp_close returns. */ - tcp_output(pcb); - } - return err; -} - -/** - * Abandons a connection and optionally sends a RST to the remote - * host. Deletes the local protocol control block. This is done when - * a connection is killed because of shortage of memory. - * - * @param pcb the tcp_pcb to abort - * @param reset boolean to indicate whether a reset should be sent - */ -void -tcp_abandon(struct tcp_pcb *pcb, int reset) -{ - u32_t seqno, ackno; - u16_t remote_port, local_port; - struct ip_addr remote_ip, local_ip; -#if LWIP_CALLBACK_API - void (* errf)(void *arg, err_t err); -#endif /* LWIP_CALLBACK_API */ - void *errf_arg; - - - /* Figure out on which TCP PCB list we are, and remove us. If we - are in an active state, call the receive function associated with - the PCB with a NULL argument, and send an RST to the remote end. */ - if (pcb->state == TIME_WAIT) { - tcp_pcb_remove(&tcp_tw_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - seqno = pcb->snd_nxt; - ackno = pcb->rcv_nxt; - ip_addr_set(&local_ip, &(pcb->local_ip)); - ip_addr_set(&remote_ip, &(pcb->remote_ip)); - local_port = pcb->local_port; - remote_port = pcb->remote_port; -#if LWIP_CALLBACK_API - errf = pcb->errf; -#endif /* LWIP_CALLBACK_API */ - errf_arg = pcb->callback_arg; - tcp_pcb_remove(&tcp_active_pcbs, pcb); - if (pcb->unacked != NULL) { - tcp_segs_free(pcb->unacked); - } - if (pcb->unsent != NULL) { - tcp_segs_free(pcb->unsent); - } -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL) { - tcp_segs_free(pcb->ooseq); - } -#endif /* TCP_QUEUE_OOSEQ */ - memp_free(MEMP_TCP_PCB, pcb); - TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); - if (reset) { - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); - tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); - } - } -} - -/** - * Binds the connection to a local portnumber and IP address. If the - * IP address is not given (i.e., ipaddr == NULL), the IP address of - * the outgoing network interface is used instead. - * - * @param pcb the tcp_pcb to bind (no check is done whether this pcb is - * already bound!) - * @param ipaddr the local ip address to bind to (use IP_ADDR_ANY to bind - * to any local address - * @param port the local port to bind to - * @return ERR_USE if the port is already in use - * ERR_OK if bound - */ -err_t -tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct tcp_pcb *cpcb; - - LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); - - if (port == 0) { - port = tcp_new_port(); - } - /* Check if the address already is in use. */ - /* Check the listen pcbs. */ - for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; - cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - /* Check the connected pcbs. */ - for(cpcb = tcp_active_pcbs; - cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - /* Check the bound, not yet connected pcbs. */ - for(cpcb = tcp_bound_pcbs; cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - /* @todo: until SO_REUSEADDR is implemented (see task #6995 on savannah), - * we have to check the pcbs in TIME-WAIT state, also: */ - for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - - if (!ip_addr_isany(ipaddr)) { - pcb->local_ip = *ipaddr; - } - pcb->local_port = port; - TCP_REG(&tcp_bound_pcbs, pcb); - LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); - return ERR_OK; -} -#if LWIP_CALLBACK_API -/** - * Default accept callback if no accept callback is specified by the user. - */ -static err_t -tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) -{ - LWIP_UNUSED_ARG(arg); - LWIP_UNUSED_ARG(pcb); - LWIP_UNUSED_ARG(err); - - return ERR_ABRT; -} -#endif /* LWIP_CALLBACK_API */ - -/** - * Set the state of the connection to be LISTEN, which means that it - * is able to accept incoming connections. The protocol control block - * is reallocated in order to consume less memory. Setting the - * connection to LISTEN is an irreversible process. - * - * @param pcb the original tcp_pcb - * @param backlog the incoming connections queue limit - * @return tcp_pcb used for listening, consumes less memory. - * - * @note The original tcp_pcb is freed. This function therefore has to be - * called like this: - * tpcb = tcp_listen(tpcb); - */ -struct tcp_pcb * -tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) -{ - struct tcp_pcb_listen *lpcb; - - LWIP_UNUSED_ARG(backlog); - LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, return NULL); - - /* already listening? */ - if (pcb->state == LISTEN) { - return pcb; - } - lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN); - if (lpcb == NULL) { - return NULL; - } - lpcb->callback_arg = pcb->callback_arg; - lpcb->local_port = pcb->local_port; - lpcb->state = LISTEN; - lpcb->so_options = pcb->so_options; - lpcb->so_options |= SOF_ACCEPTCONN; - lpcb->ttl = pcb->ttl; - lpcb->tos = pcb->tos; - ip_addr_set(&lpcb->local_ip, &pcb->local_ip); - TCP_RMV(&tcp_bound_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); -#if LWIP_CALLBACK_API - lpcb->accept = tcp_accept_null; -#endif /* LWIP_CALLBACK_API */ -#if TCP_LISTEN_BACKLOG - lpcb->accepts_pending = 0; - lpcb->backlog = (backlog ? backlog : 1); -#endif /* TCP_LISTEN_BACKLOG */ - TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb); - return (struct tcp_pcb *)lpcb; -} - -/** - * Update the state that tracks the available window space to advertise. - * - * Returns how much extra window would be advertised if we sent an - * update now. - */ -u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) -{ - u32_t new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; - - if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { - /* we can advertise more window */ - pcb->rcv_ann_wnd = pcb->rcv_wnd; - return new_right_edge - pcb->rcv_ann_right_edge; - } else { - if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { - /* Can happen due to other end sending out of advertised window, - * but within actual available (but not yet advertised) window */ - pcb->rcv_ann_wnd = 0; - } else { - /* keep the right edge of window constant */ - pcb->rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; - } - return 0; - } -} - -/** - * This function should be called by the application when it has - * processed the data. The purpose is to advertise a larger window - * when the data has been processed. - * - * @param pcb the tcp_pcb for which data is read - * @param len the amount of bytes that have been read by the application - */ -void -tcp_recved(struct tcp_pcb *pcb, u16_t len) -{ - int wnd_inflation; - - LWIP_ASSERT("tcp_recved: len would wrap rcv_wnd\n", - len <= 0xffff - pcb->rcv_wnd ); - - pcb->rcv_wnd += len; - if (pcb->rcv_wnd > TCP_WND) - pcb->rcv_wnd = TCP_WND; - - wnd_inflation = tcp_update_rcv_ann_wnd(pcb); - - /* If the change in the right edge of window is significant (default - * watermark is TCP_WND/2), then send an explicit update now. - * Otherwise wait for a packet to be sent in the normal course of - * events (or more window to be available later) */ - if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) - tcp_ack_now(pcb); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", - len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); -} - -/** - * A nastly hack featuring 'goto' statements that allocates a - * new TCP local port. - * - * @return a new (free) local TCP port number - */ -static u16_t -tcp_new_port(void) -{ - struct tcp_pcb *pcb; -#ifndef TCP_LOCAL_PORT_RANGE_START -#define TCP_LOCAL_PORT_RANGE_START 4096 -#define TCP_LOCAL_PORT_RANGE_END 0x7fff -#endif - static u16_t port = TCP_LOCAL_PORT_RANGE_START; - - again: - if (++port > TCP_LOCAL_PORT_RANGE_END) { - port = TCP_LOCAL_PORT_RANGE_START; - } - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - return port; -} - -/** - * Connects to another host. The function given as the "connected" - * argument will be called when the connection has been established. - * - * @param pcb the tcp_pcb used to establish the connection - * @param ipaddr the remote ip address to connect to - * @param port the remote tcp port to connect to - * @param connected callback function to call when connected (or on error) - * @return ERR_VAL if invalid arguments are given - * ERR_OK if connect request has been sent - * other err_t values if connect request couldn't be sent - */ -err_t -tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port, - err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err)) -{ - err_t ret; - u32_t iss; - - LWIP_ERROR("tcp_connect: can only connected from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); - if (ipaddr != NULL) { - pcb->remote_ip = *ipaddr; - } else { - return ERR_VAL; - } - pcb->remote_port = port; - if (pcb->local_port == 0) { - pcb->local_port = tcp_new_port(); - } - iss = tcp_next_iss(); - pcb->rcv_nxt = 0; - pcb->snd_nxt = iss; - pcb->lastack = iss - 1; - pcb->snd_lbb = iss - 1; - pcb->rcv_wnd = TCP_WND; - pcb->rcv_ann_wnd = TCP_WND; - pcb->rcv_ann_right_edge = pcb->rcv_nxt; - pcb->snd_wnd = TCP_WND; - /* As initial send MSS, we use TCP_MSS but limit it to 536. - The send MSS is updated when an MSS option is received. */ - pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS; -#if TCP_CALCULATE_EFF_SEND_MSS - pcb->mss = tcp_eff_send_mss(pcb->mss, ipaddr); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - pcb->cwnd = 1; - pcb->ssthresh = pcb->mss * 10; - pcb->state = SYN_SENT; -#if LWIP_CALLBACK_API - pcb->connected = connected; -#endif /* LWIP_CALLBACK_API */ - TCP_RMV(&tcp_bound_pcbs, pcb); - TCP_REG(&tcp_active_pcbs, pcb); - - snmp_inc_tcpactiveopens(); - - ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, TF_SEG_OPTS_MSS -#if LWIP_TCP_TIMESTAMPS - | TF_SEG_OPTS_TS -#endif - ); - if (ret == ERR_OK) { - tcp_output(pcb); - } - return ret; -} - -/** - * Called every 500 ms and implements the retransmission timer and the timer that - * removes PCBs that have been in TIME-WAIT for enough time. It also increments - * various timers such as the inactivity timer in each PCB. - * - * Automatically called from tcp_tmr(). - */ -void -tcp_slowtmr(void) -{ - struct tcp_pcb *pcb, *pcb2, *prev; - u16_t eff_wnd; - u8_t pcb_remove; /* flag if a PCB should be removed */ - u8_t pcb_reset; /* flag if a RST should be sent when removing */ - err_t err; - - err = ERR_OK; - - ++tcp_ticks; - - /* Steps through all of the active PCBs. */ - prev = NULL; - pcb = tcp_active_pcbs; - if (pcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); - } - while (pcb != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); - - pcb_remove = 0; - pcb_reset = 0; - - if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); - } - else if (pcb->nrtx == TCP_MAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); - } else { - if (pcb->persist_backoff > 0) { - /* If snd_wnd is zero, use persist timer to send 1 byte probes - * instead of using the standard retransmission mechanism. */ - pcb->persist_cnt++; - if (pcb->persist_cnt >= tcp_persist_backoff[pcb->persist_backoff-1]) { - pcb->persist_cnt = 0; - if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { - pcb->persist_backoff++; - } - tcp_zero_window_probe(pcb); - } - } else { - /* Increase the retransmission timer if it is running */ - if(pcb->rtime >= 0) - ++pcb->rtime; - - if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { - /* Time for a retransmission. */ - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F - " pcb->rto %"S16_F"\n", - pcb->rtime, pcb->rto)); - - /* Double retransmission time-out unless we are trying to - * connect to somebody (i.e., we are in SYN_SENT). */ - if (pcb->state != SYN_SENT) { - pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; - } - - /* Reset the retransmission timer. */ - pcb->rtime = 0; - - /* Reduce congestion window and ssthresh. */ - eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); - pcb->ssthresh = eff_wnd >> 1; - if (pcb->ssthresh < pcb->mss) { - pcb->ssthresh = pcb->mss * 2; - } - pcb->cwnd = pcb->mss; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F - " ssthresh %"U16_F"\n", - pcb->cwnd, pcb->ssthresh)); - - /* The following needs to be called AFTER cwnd is set to one - mss - STJ */ - tcp_rexmit_rto(pcb); - } - } - } - /* Check if this PCB has stayed too long in FIN-WAIT-2 */ - if (pcb->state == FIN_WAIT_2) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); - } - } - - /* Check if KEEPALIVE should be sent */ - if((pcb->so_options & SOF_KEEPALIVE) && - ((pcb->state == ESTABLISHED) || - (pcb->state == CLOSE_WAIT))) { -#if LWIP_TCP_KEEPALIVE - if((u32_t)(tcp_ticks - pcb->tmr) > - (pcb->keep_idle + (pcb->keep_cnt*pcb->keep_intvl)) - / TCP_SLOW_INTERVAL) -#else - if((u32_t)(tcp_ticks - pcb->tmr) > - (pcb->keep_idle + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) -#endif /* LWIP_TCP_KEEPALIVE */ - { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - ++pcb_remove; - ++pcb_reset; - } -#if LWIP_TCP_KEEPALIVE - else if((u32_t)(tcp_ticks - pcb->tmr) > - (pcb->keep_idle + pcb->keep_cnt_sent * pcb->keep_intvl) - / TCP_SLOW_INTERVAL) -#else - else if((u32_t)(tcp_ticks - pcb->tmr) > - (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEPINTVL_DEFAULT) - / TCP_SLOW_INTERVAL) -#endif /* LWIP_TCP_KEEPALIVE */ - { - tcp_keepalive(pcb); - pcb->keep_cnt_sent++; - } - } - - /* If this PCB has queued out of sequence data, but has been - inactive for too long, will drop the data (it will eventually - be retransmitted). */ -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL && - (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) { - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); - } -#endif /* TCP_QUEUE_OOSEQ */ - - /* Check if this PCB has stayed too long in SYN-RCVD */ - if (pcb->state == SYN_RCVD) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); - } - } - - /* Check if this PCB has stayed too long in LAST-ACK */ - if (pcb->state == LAST_ACK) { - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); - } - } - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_active_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); - tcp_active_pcbs = pcb->next; - } - - TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); - if (pcb_reset) { - tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, - pcb->local_port, pcb->remote_port); - } - - pcb2 = pcb->next; - memp_free(MEMP_TCP_PCB, pcb); - pcb = pcb2; - } else { - - /* We check if we should poll the connection. */ - ++pcb->polltmr; - if (pcb->polltmr >= pcb->pollinterval) { - pcb->polltmr = 0; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); - TCP_EVENT_POLL(pcb, err); - if (err == ERR_OK) { - tcp_output(pcb); - } - } - - prev = pcb; - pcb = pcb->next; - } - } - - - /* Steps through all of the TIME-WAIT PCBs. */ - prev = NULL; - pcb = tcp_tw_pcbs; - while (pcb != NULL) { - LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - pcb_remove = 0; - - /* Check if this PCB has stayed long enough in TIME-WAIT */ - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - } - - - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_tw_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); - tcp_tw_pcbs = pcb->next; - } - pcb2 = pcb->next; - memp_free(MEMP_TCP_PCB, pcb); - pcb = pcb2; - } else { - prev = pcb; - pcb = pcb->next; - } - } -} - -/** - * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously - * "refused" by upper layer (application) and sends delayed ACKs. - * - * Automatically called from tcp_tmr(). - */ -void -tcp_fasttmr(void) -{ - struct tcp_pcb *pcb; - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - /* If there is data which was previously "refused" by upper layer */ - if (pcb->refused_data != NULL) { - /* Notify again application with data previously received. */ - err_t err; - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_fasttmr: notify kept packet\n")); - TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err); - if (err == ERR_OK) { - pcb->refused_data = NULL; - } - } - - /* send delayed ACKs */ - if (pcb->flags & TF_ACK_DELAY) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); - tcp_ack_now(pcb); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - } -} - -/** - * Deallocates a list of TCP segments (tcp_seg structures). - * - * @param seg tcp_seg list of TCP segments to free - * @return the number of pbufs that were deallocated - */ -u8_t -tcp_segs_free(struct tcp_seg *seg) -{ - u8_t count = 0; - struct tcp_seg *next; - while (seg != NULL) { - next = seg->next; - count += tcp_seg_free(seg); - seg = next; - } - return count; -} - -/** - * Frees a TCP segment (tcp_seg structure). - * - * @param seg single tcp_seg to free - * @return the number of pbufs that were deallocated - */ -u8_t -tcp_seg_free(struct tcp_seg *seg) -{ - u8_t count = 0; - - if (seg != NULL) { - if (seg->p != NULL) { - count = pbuf_free(seg->p); -#if TCP_DEBUG - seg->p = NULL; -#endif /* TCP_DEBUG */ - } - memp_free(MEMP_TCP_SEG, seg); - } - return count; -} - -/** - * Sets the priority of a connection. - * - * @param pcb the tcp_pcb to manipulate - * @param prio new priority - */ -void -tcp_setprio(struct tcp_pcb *pcb, u8_t prio) -{ - pcb->prio = prio; -} -#if TCP_QUEUE_OOSEQ - -/** - * Returns a copy of the given TCP segment. - * The pbuf and data are not copied, only the pointers - * - * @param seg the old tcp_seg - * @return a copy of seg - */ -struct tcp_seg * -tcp_seg_copy(struct tcp_seg *seg) -{ - struct tcp_seg *cseg; - - cseg = memp_malloc(MEMP_TCP_SEG); - if (cseg == NULL) { - return NULL; - } - SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); - pbuf_ref(cseg->p); - return cseg; -} -#endif - -#if LWIP_CALLBACK_API -/** - * Default receive callback that is called if the user didn't register - * a recv callback for the pcb. - */ -err_t -tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - LWIP_UNUSED_ARG(arg); - if (p != NULL) { - tcp_recved(pcb, p->tot_len); - pbuf_free(p); - } else if (err == ERR_OK) { - return tcp_close(pcb); - } - return ERR_OK; -} -#endif /* LWIP_CALLBACK_API */ - -/** - * Kills the oldest active connection that has lower priority than prio. - * - * @param prio minimum priority - */ -static void -tcp_kill_prio(u8_t prio) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - u8_t mprio; - - - mprio = TCP_PRIO_MAX; - - /* We kill the oldest active connection that has lower priority than prio. */ - inactivity = 0; - inactive = NULL; - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->prio <= prio && - pcb->prio <= mprio && - (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - mprio = pcb->prio; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - -/** - * Kills the oldest connection that is in TIME_WAIT state. - * Called from tcp_alloc() if no more connections are available. - */ -static void -tcp_kill_timewait(void) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - - inactivity = 0; - inactive = NULL; - /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - -/** - * Allocate a new tcp_pcb structure. - * - * @param prio priority for the new pcb - * @return a new tcp_pcb that initially is in state CLOSED - */ -struct tcp_pcb * -tcp_alloc(u8_t prio) -{ - struct tcp_pcb *pcb; - u32_t iss; - - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing oldest connection in TIME-WAIT. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); - tcp_kill_timewait(); - /* Try to allocate a tcp_pcb again. */ - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing active connections with lower priority than the new one. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing connection with prio lower than %d\n", prio)); - tcp_kill_prio(prio); - /* Try to allocate a tcp_pcb again. */ - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb != NULL) { - /* adjust err stats: memp_malloc failed twice before */ - MEMP_STATS_DEC(err, MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - /* adjust err stats: timewait PCB was freed above */ - MEMP_STATS_DEC(err, MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - memset(pcb, 0, sizeof(struct tcp_pcb)); - pcb->prio = TCP_PRIO_NORMAL; - pcb->snd_buf = TCP_SND_BUF; - pcb->snd_queuelen = 0; - pcb->rcv_wnd = TCP_WND; - pcb->rcv_ann_wnd = TCP_WND; - pcb->tos = 0; - pcb->ttl = TCP_TTL; - /* As initial send MSS, we use TCP_MSS but limit it to 536. - The send MSS is updated when an MSS option is received. */ - pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS; - pcb->rto = 3000 / TCP_SLOW_INTERVAL; - pcb->sa = 0; - pcb->sv = 3000 / TCP_SLOW_INTERVAL; - pcb->rtime = -1; - pcb->cwnd = 1; - iss = tcp_next_iss(); - pcb->snd_wl2 = iss; - pcb->snd_nxt = iss; - pcb->lastack = iss; - pcb->snd_lbb = iss; - pcb->tmr = tcp_ticks; - - pcb->polltmr = 0; - -#if LWIP_CALLBACK_API - pcb->recv = tcp_recv_null; -#endif /* LWIP_CALLBACK_API */ - - /* Init KEEPALIVE timer */ - pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; - -#if LWIP_TCP_KEEPALIVE - pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; - pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; -#endif /* LWIP_TCP_KEEPALIVE */ - - pcb->keep_cnt_sent = 0; - } - return pcb; -} - -/** - * Creates a new TCP protocol control block but doesn't place it on - * any of the TCP PCB lists. - * The pcb is not put on any list until binding using tcp_bind(). - * - * @internal: Maybe there should be a idle TCP PCB list where these - * PCBs are put on. Port reservation using tcp_bind() is implemented but - * allocated pcbs that are not bound can't be killed automatically if wanting - * to allocate a pcb with higher prio (@see tcp_kill_prio()) - * - * @return a new tcp_pcb that initially is in state CLOSED - */ -struct tcp_pcb * -tcp_new(void) -{ - return tcp_alloc(TCP_PRIO_NORMAL); -} - -/** - * Used to specify the argument that should be passed callback - * functions. - * - * @param pcb tcp_pcb to set the callback argument - * @param arg void pointer argument to pass to callback functions - */ -void -tcp_arg(struct tcp_pcb *pcb, void *arg) -{ - pcb->callback_arg = arg; -} -#if LWIP_CALLBACK_API - -/** - * Used to specify the function that should be called when a TCP - * connection receives data. - * - * @param pcb tcp_pcb to set the recv callback - * @param recv callback function to call for this pcb when data is received - */ -void -tcp_recv(struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)) -{ - pcb->recv = recv; -} - -/** - * Used to specify the function that should be called when TCP data - * has been successfully delivered to the remote host. - * - * @param pcb tcp_pcb to set the sent callback - * @param sent callback function to call for this pcb when data is successfully sent - */ -void -tcp_sent(struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len)) -{ - pcb->sent = sent; -} - -/** - * Used to specify the function that should be called when a fatal error - * has occured on the connection. - * - * @param pcb tcp_pcb to set the err callback - * @param errf callback function to call for this pcb when a fatal error - * has occured on the connection - */ -void -tcp_err(struct tcp_pcb *pcb, - void (* errf)(void *arg, err_t err)) -{ - pcb->errf = errf; -} - -/** - * Used for specifying the function that should be called when a - * LISTENing connection has been connected to another host. - * - * @param pcb tcp_pcb to set the accept callback - * @param accept callback function to call for this pcb when LISTENing - * connection has been connected to another host - */ -void -tcp_accept(struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)) -{ - pcb->accept = accept; -} -#endif /* LWIP_CALLBACK_API */ - - -/** - * Used to specify the function that should be called periodically - * from TCP. The interval is specified in terms of the TCP coarse - * timer interval, which is called twice a second. - * - */ -void -tcp_poll(struct tcp_pcb *pcb, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval) -{ -#if LWIP_CALLBACK_API - pcb->poll = poll; -#endif /* LWIP_CALLBACK_API */ - pcb->pollinterval = interval; -} - -/** - * Purges a TCP PCB. Removes any buffered data and frees the buffer memory - * (pcb->ooseq, pcb->unsent and pcb->unacked are freed). - * - * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! - */ -void -tcp_pcb_purge(struct tcp_pcb *pcb) -{ - if (pcb->state != CLOSED && - pcb->state != TIME_WAIT && - pcb->state != LISTEN) { - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); - -#if TCP_LISTEN_BACKLOG - if (pcb->state == SYN_RCVD) { - /* Need to find the corresponding listen_pcb and decrease its accepts_pending */ - struct tcp_pcb_listen *lpcb; - LWIP_ASSERT("tcp_pcb_purge: pcb->state == SYN_RCVD but tcp_listen_pcbs is NULL", - tcp_listen_pcbs.listen_pcbs != NULL); - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - if ((lpcb->local_port == pcb->local_port) && - (ip_addr_isany(&lpcb->local_ip) || - ip_addr_cmp(&pcb->local_ip, &lpcb->local_ip))) { - /* port and address of the listen pcb match the timed-out pcb */ - LWIP_ASSERT("tcp_pcb_purge: listen pcb does not have accepts pending", - lpcb->accepts_pending > 0); - lpcb->accepts_pending--; - break; - } - } - } -#endif /* TCP_LISTEN_BACKLOG */ - - - if (pcb->refused_data != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); - pbuf_free(pcb->refused_data); - pcb->refused_data = NULL; - } - if (pcb->unsent != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); - } - if (pcb->unacked != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); - } -#if TCP_QUEUE_OOSEQ /* LW */ - if (pcb->ooseq != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); - } - - /* Stop the retransmission timer as it will expect data on unacked - queue if it fires */ - pcb->rtime = -1; - - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; -#endif /* TCP_QUEUE_OOSEQ */ - tcp_segs_free(pcb->unsent); - tcp_segs_free(pcb->unacked); - pcb->unacked = pcb->unsent = NULL; - } -} - -/** - * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. - * - * @param pcblist PCB list to purge. - * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! - */ -void -tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) -{ - TCP_RMV(pcblist, pcb); - - tcp_pcb_purge(pcb); - - /* if there is an outstanding delayed ACKs, send it */ - if (pcb->state != TIME_WAIT && - pcb->state != LISTEN && - pcb->flags & TF_ACK_DELAY) { - pcb->flags |= TF_ACK_NOW; - tcp_output(pcb); - } - - if (pcb->state != LISTEN) { - LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); - LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); -#if TCP_QUEUE_OOSEQ - LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); -#endif /* TCP_QUEUE_OOSEQ */ - } - - pcb->state = CLOSED; - - LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); -} - -/** - * Calculates a new initial sequence number for new connections. - * - * @return u32_t pseudo random sequence number - */ -u32_t -tcp_next_iss(void) -{ - static u32_t iss = 6510; - - iss += tcp_ticks; /* XXX */ - return iss; -} - -#if TCP_CALCULATE_EFF_SEND_MSS -/** - * Calcluates the effective send mss that can be used for a specific IP address - * by using ip_route to determin the netif used to send to the address and - * calculating the minimum of TCP_MSS and that netif's mtu (if set). - */ -u16_t -tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr) -{ - u16_t mss_s; - struct netif *outif; - - outif = ip_route(addr); - if ((outif != NULL) && (outif->mtu != 0)) { - mss_s = outif->mtu - IP_HLEN - TCP_HLEN; - /* RFC 1122, chap 4.2.2.6: - * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize - * We correct for TCP options in tcp_enqueue(), and don't support - * IP options - */ - sendmss = LWIP_MIN(sendmss, mss_s); - } - return sendmss; -} -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - -const char* -tcp_debug_state_str(enum tcp_state s) -{ - return tcp_state_str[s]; -} - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -/** - * Print a tcp header for debugging purposes. - * - * @param tcphdr pointer to a struct tcp_hdr - */ -void -tcp_debug_print(struct tcp_hdr *tcphdr) -{ - LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - ntohs(tcphdr->src), ntohs(tcphdr->dest))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", - ntohl(tcphdr->seqno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", - ntohl(tcphdr->ackno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", - TCPH_HDRLEN(tcphdr), - TCPH_FLAGS(tcphdr) >> 5 & 1, - TCPH_FLAGS(tcphdr) >> 4 & 1, - TCPH_FLAGS(tcphdr) >> 3 & 1, - TCPH_FLAGS(tcphdr) >> 2 & 1, - TCPH_FLAGS(tcphdr) >> 1 & 1, - TCPH_FLAGS(tcphdr) & 1, - ntohs(tcphdr->wnd))); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", - ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); -} - -/** - * Print a tcp state for debugging purposes. - * - * @param s enum tcp_state to print - */ -void -tcp_debug_print_state(enum tcp_state s) -{ - LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s])); -} - -/** - * Print tcp flags for debugging purposes. - * - * @param flags tcp flags, all active flags are printed - */ -void -tcp_debug_print_flags(u8_t flags) -{ - if (flags & TCP_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); - } - if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); - } - if (flags & TCP_RST) { - LWIP_DEBUGF(TCP_DEBUG, ("RST ")); - } - if (flags & TCP_PSH) { - LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); - } - if (flags & TCP_ACK) { - LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); - } - if (flags & TCP_URG) { - LWIP_DEBUGF(TCP_DEBUG, ("URG ")); - } - if (flags & TCP_ECE) { - LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); - } - if (flags & TCP_CWR) { - LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); - } - LWIP_DEBUGF(TCP_DEBUG, ("\n")); -} - -/** - * Print all tcp_pcbs in every list for debugging purposes. - */ -void -tcp_debug_print_pcbs(void) -{ - struct tcp_pcb *pcb; - LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } -} - -/** - * Check state consistency of the tcp_pcb lists. - */ -s16_t -tcp_pcbs_sane(void) -{ - struct tcp_pcb *pcb; - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - } - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - } - return 1; -} -#endif /* TCP_DEBUG */ - -#endif /* LWIP_TCP */ diff --git a/components/net/lwip-1.3.2/src/core/tcp_in.c b/components/net/lwip-1.3.2/src/core/tcp_in.c deleted file mode 100644 index 51e8775901..0000000000 --- a/components/net/lwip-1.3.2/src/core/tcp_in.c +++ /dev/null @@ -1,1506 +0,0 @@ -/** - * @file - * Transmission Control Protocol, incoming traffic - * - * The input processing functions of the TCP layer. - * - * These functions are generally called in the order (ip_input() ->) - * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/tcp.h" -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/inet_chksum.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "arch/perf.h" - -/* These variables are global to all functions involved in the input - processing of TCP segments. They are set by the tcp_input() - function. */ -static struct tcp_seg inseg; -static struct tcp_hdr *tcphdr; -static struct ip_hdr *iphdr; -static u32_t seqno, ackno; -static u8_t flags; -static u16_t tcplen; - -static u8_t recv_flags; -static struct pbuf *recv_data; - -struct tcp_pcb *tcp_input_pcb; - -/* Forward declarations. */ -static err_t tcp_process(struct tcp_pcb *pcb); -static void tcp_receive(struct tcp_pcb *pcb); -static void tcp_parseopt(struct tcp_pcb *pcb); - -static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); -static err_t tcp_timewait_input(struct tcp_pcb *pcb); - -/** - * The initial input processing of TCP. It verifies the TCP header, demultiplexes - * the segment between the PCBs and passes it on to tcp_process(), which implements - * the TCP finite state machine. This function is called by the IP layer (in - * ip_input()). - * - * @param p received TCP segment to process (p->payload pointing to the IP header) - * @param inp network interface on which this segment was received - */ -void -tcp_input(struct pbuf *p, struct netif *inp) -{ - struct tcp_pcb *pcb, *prev; - struct tcp_pcb_listen *lpcb; - u8_t hdrlen; - err_t err; - - PERF_START; - - TCP_STATS_INC(tcp.recv); - snmp_inc_tcpinsegs(); - - iphdr = p->payload; - tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); - -#if TCP_INPUT_DEBUG - tcp_debug_print(tcphdr); -#endif - - /* remove header from payload */ - if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { - /* drop short packets */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); - TCP_STATS_INC(tcp.lenerr); - TCP_STATS_INC(tcp.drop); - snmp_inc_tcpinerrs(); - pbuf_free(p); - return; - } - - /* Don't even process incoming broadcasts/multicasts. */ - if (ip_addr_isbroadcast(&(iphdr->dest), inp) || - ip_addr_ismulticast(&(iphdr->dest))) { - TCP_STATS_INC(tcp.proterr); - TCP_STATS_INC(tcp.drop); - snmp_inc_tcpinerrs(); - pbuf_free(p); - return; - } - -#if CHECKSUM_CHECK_TCP - /* Verify TCP checksum. */ - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_TCP, p->tot_len) != 0) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", - inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), - IP_PROTO_TCP, p->tot_len))); -#if TCP_DEBUG - tcp_debug_print(tcphdr); -#endif /* TCP_DEBUG */ - TCP_STATS_INC(tcp.chkerr); - TCP_STATS_INC(tcp.drop); - snmp_inc_tcpinerrs(); - pbuf_free(p); - return; - } -#endif - - /* Move the payload pointer in the pbuf so that it points to the - TCP data instead of the TCP header. */ - hdrlen = TCPH_HDRLEN(tcphdr); - if(pbuf_header(p, -(hdrlen * 4))){ - /* drop short packets */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet\n")); - TCP_STATS_INC(tcp.lenerr); - TCP_STATS_INC(tcp.drop); - snmp_inc_tcpinerrs(); - pbuf_free(p); - return; - } - - /* Convert fields in TCP header to host byte order. */ - tcphdr->src = ntohs(tcphdr->src); - tcphdr->dest = ntohs(tcphdr->dest); - seqno = tcphdr->seqno = ntohl(tcphdr->seqno); - ackno = tcphdr->ackno = ntohl(tcphdr->ackno); - tcphdr->wnd = ntohs(tcphdr->wnd); - - flags = TCPH_FLAGS(tcphdr); - tcplen = p->tot_len + ((flags & (TCP_FIN | TCP_SYN)) ? 1 : 0); - - /* Demultiplex an incoming segment. First, we check if it is destined - for an active connection. */ - prev = NULL; - - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { - - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); - if (prev != NULL) { - prev->next = pcb->next; - pcb->next = tcp_active_pcbs; - tcp_active_pcbs = pcb; - } - LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); - break; - } - prev = pcb; - } - - if (pcb == NULL) { - /* If it did not go to an active connection, we check the connections - in the TIME-WAIT state. */ - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { - /* We don't really care enough to move this PCB to the front - of the list since we are not very likely to receive that - many segments for connections in TIME-WAIT. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); - tcp_timewait_input(pcb); - pbuf_free(p); - return; - } - } - - /* Finally, if we still did not get a match, we check all PCBs that - are LISTENing for incoming connections. */ - prev = NULL; - for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - if ((ip_addr_isany(&(lpcb->local_ip)) || - ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) && - lpcb->local_port == tcphdr->dest) { - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - if (prev != NULL) { - ((struct tcp_pcb_listen *)prev)->next = lpcb->next; - /* our successor is the remainder of the listening list */ - lpcb->next = tcp_listen_pcbs.listen_pcbs; - /* put this listening pcb at the head of the listening list */ - tcp_listen_pcbs.listen_pcbs = lpcb; - } - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); - tcp_listen_input(lpcb); - pbuf_free(p); - return; - } - prev = (struct tcp_pcb *)lpcb; - } - } - -#if TCP_INPUT_DEBUG - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); -#endif /* TCP_INPUT_DEBUG */ - - - if (pcb != NULL) { - /* The incoming segment belongs to a connection. */ -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - - /* Set up a tcp_seg structure. */ - inseg.next = NULL; - inseg.len = p->tot_len; - inseg.dataptr = p->payload; - inseg.p = p; - inseg.tcphdr = tcphdr; - - recv_data = NULL; - recv_flags = 0; - - /* If there is data which was previously "refused" by upper layer */ - if (pcb->refused_data != NULL) { - /* Notify again application with data previously received. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); - TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err); - if (err == ERR_OK) { - pcb->refused_data = NULL; - } else { - /* drop incoming packets, because pcb is "full" */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); - TCP_STATS_INC(tcp.drop); - snmp_inc_tcpinerrs(); - pbuf_free(p); - return; - } - } - tcp_input_pcb = pcb; - err = tcp_process(pcb); - /* A return value of ERR_ABRT means that tcp_abort() was called - and that the pcb has been freed. If so, we don't do anything. */ - if (err != ERR_ABRT) { - if (recv_flags & TF_RESET) { - /* TF_RESET means that the connection was reset by the other - end. We then call the error callback to inform the - application that the connection is dead before we - deallocate the PCB. */ - TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else if (recv_flags & TF_CLOSED) { - /* The connection has been closed and we will deallocate the - PCB. */ - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - err = ERR_OK; - /* If the application has registered a "sent" function to be - called when new send buffer space is available, we call it - now. */ - if (pcb->acked > 0) { - TCP_EVENT_SENT(pcb, pcb->acked, err); - } - - if (recv_data != NULL) { - if(flags & TCP_PSH) { - recv_data->flags |= PBUF_FLAG_PUSH; - } - - /* Notify application that data has been received. */ - TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); - - /* If the upper layer can't receive this data, store it */ - if (err != ERR_OK) { - pcb->refused_data = recv_data; - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n")); - } - } - - /* If a FIN segment was received, we call the callback - function with a NULL buffer to indicate EOF. */ - if (recv_flags & TF_GOT_FIN) { - TCP_EVENT_RECV(pcb, NULL, ERR_OK, err); - } - - tcp_input_pcb = NULL; - /* Try to send something out. */ - tcp_output(pcb); -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - } - } - tcp_input_pcb = NULL; - - - /* give up our reference to inseg.p */ - if (inseg.p != NULL) - { - pbuf_free(inseg.p); - inseg.p = NULL; - } - } else { - - /* If no matching PCB was found, send a TCP RST (reset) to the - sender. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); - if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { - TCP_STATS_INC(tcp.proterr); - TCP_STATS_INC(tcp.drop); - tcp_rst(ackno, seqno + tcplen, - &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - pbuf_free(p); - } - - LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); - PERF_STOP("tcp_input"); -} - -/** - * Called by tcp_input() when a segment arrives for a listening - * connection (from tcp_input()). - * - * @param pcb the tcp_pcb_listen for which a segment arrived - * @return ERR_OK if the segment was processed - * another err_t on error - * - * @note the return value is not (yet?) used in tcp_input() - * @note the segment which arrived is saved in global variables, therefore only the pcb - * involved is passed as a parameter to this function - */ -static err_t -tcp_listen_input(struct tcp_pcb_listen *pcb) -{ - struct tcp_pcb *npcb; - err_t rc; - - /* In the LISTEN state, we check for incoming SYN segments, - creates a new PCB, and responds with a SYN|ACK. */ - if (flags & TCP_ACK) { - /* For incoming segments with the ACK flag set, respond with a - RST. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); - tcp_rst(ackno + 1, seqno + tcplen, - &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } else if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); -#if TCP_LISTEN_BACKLOG - if (pcb->accepts_pending >= pcb->backlog) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest)); - return ERR_ABRT; - } -#endif /* TCP_LISTEN_BACKLOG */ - npcb = tcp_alloc(pcb->prio); - /* If a new PCB could not be created (probably due to lack of memory), - we don't do anything, but rely on the sender will retransmit the - SYN at a time when we have more memory available. */ - if (npcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } -#if TCP_LISTEN_BACKLOG - pcb->accepts_pending++; -#endif /* TCP_LISTEN_BACKLOG */ - /* Set up the new PCB. */ - ip_addr_set(&(npcb->local_ip), &(iphdr->dest)); - npcb->local_port = pcb->local_port; - ip_addr_set(&(npcb->remote_ip), &(iphdr->src)); - npcb->remote_port = tcphdr->src; - npcb->state = SYN_RCVD; - npcb->rcv_nxt = seqno + 1; - npcb->rcv_ann_right_edge = npcb->rcv_nxt; - npcb->snd_wnd = tcphdr->wnd; - npcb->ssthresh = npcb->snd_wnd; - npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ - npcb->callback_arg = pcb->callback_arg; -#if LWIP_CALLBACK_API - npcb->accept = pcb->accept; -#endif /* LWIP_CALLBACK_API */ - /* inherit socket options */ - npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER); - /* Register the new PCB so that we can begin receiving segments - for it. */ - TCP_REG(&tcp_active_pcbs, npcb); - - /* Parse any options in the SYN. */ - tcp_parseopt(npcb); -#if TCP_CALCULATE_EFF_SEND_MSS - npcb->mss = tcp_eff_send_mss(npcb->mss, &(npcb->remote_ip)); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - - snmp_inc_tcppassiveopens(); - - /* Send a SYN|ACK together with the MSS option. */ - rc = tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, TF_SEG_OPTS_MSS -#if LWIP_TCP_TIMESTAMPS - /* and maybe include the TIMESTAMP option */ - | (npcb->flags & TF_TIMESTAMP ? TF_SEG_OPTS_TS : 0) -#endif - ); - if (rc != ERR_OK) { - tcp_abandon(npcb, 0); - return rc; - } - return tcp_output(npcb); - } - return ERR_OK; -} - -/** - * Called by tcp_input() when a segment arrives for a connection in - * TIME_WAIT. - * - * @param pcb the tcp_pcb for which a segment arrived - * - * @note the segment which arrived is saved in global variables, therefore only the pcb - * involved is passed as a parameter to this function - */ -static err_t -tcp_timewait_input(struct tcp_pcb *pcb) -{ - /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ - /* RFC 793 3.9 Event Processing - Segment Arrives: - * - first check sequence number - we skip that one in TIME_WAIT (always - * acceptable since we only send ACKs) - * - second check the RST bit (... return) */ - if (flags & TCP_RST) { - return ERR_OK; - } - /* - fourth, check the SYN bit, */ - if (flags & TCP_SYN) { - /* If an incoming segment is not acceptable, an acknowledgment - should be sent in reply */ - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { - /* If the SYN is in the window it is an error, send a reset */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - return ERR_OK; - } - } else if (flags & TCP_FIN) { - /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. - Restart the 2 MSL time-wait timeout.*/ - pcb->tmr = tcp_ticks; - } - - if ((tcplen > 0)) { - /* Acknowledge data, FIN or out-of-window SYN */ - pcb->flags |= TF_ACK_NOW; - return tcp_output(pcb); - } - return ERR_OK; -} - -/** - * Implements the TCP state machine. Called by tcp_input. In some - * states tcp_receive() is called to receive data. The tcp_seg - * argument will be freed by the caller (tcp_input()) unless the - * recv_data pointer in the pcb is set. - * - * @param pcb the tcp_pcb for which a segment arrived - * - * @note the segment which arrived is saved in global variables, therefore only the pcb - * involved is passed as a parameter to this function - */ -static err_t -tcp_process(struct tcp_pcb *pcb) -{ - struct tcp_seg *rseg; - u8_t acceptable = 0; - err_t err; - - err = ERR_OK; - - /* Process incoming RST segments. */ - if (flags & TCP_RST) { - /* First, determine if the reset is acceptable. */ - if (pcb->state == SYN_SENT) { - if (ackno == pcb->snd_nxt) { - acceptable = 1; - } - } else { - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, - pcb->rcv_nxt+pcb->rcv_wnd)) { - acceptable = 1; - } - } - - if (acceptable) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); - LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); - recv_flags |= TF_RESET; - pcb->flags &= ~TF_ACK_DELAY; - return ERR_RST; - } else { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - return ERR_OK; - } - } - - if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { - /* Cope with new connection attempt after remote end crashed */ - tcp_ack_now(pcb); - return ERR_OK; - } - - /* Update the PCB (in)activity timer. */ - pcb->tmr = tcp_ticks; - pcb->keep_cnt_sent = 0; - - tcp_parseopt(pcb); - - /* Do different things depending on the TCP state. */ - switch (pcb->state) { - case SYN_SENT: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, - pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); - /* received SYN ACK with expected sequence number? */ - if ((flags & TCP_ACK) && (flags & TCP_SYN) - && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { - pcb->snd_buf++; - pcb->rcv_nxt = seqno + 1; - pcb->rcv_ann_right_edge = pcb->rcv_nxt; - pcb->lastack = ackno; - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ - pcb->state = ESTABLISHED; - -#if TCP_CALCULATE_EFF_SEND_MSS - pcb->mss = tcp_eff_send_mss(pcb->mss, &(pcb->remote_ip)); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - - /* Set ssthresh again after changing pcb->mss (already set in tcp_connect - * but for the default value of pcb->mss) */ - pcb->ssthresh = pcb->mss * 10; - - pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss); - LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); - --pcb->snd_queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - rseg = pcb->unacked; - pcb->unacked = rseg->next; - - /* If there's nothing left to acknowledge, stop the retransmit - timer, otherwise reset it to start again */ - if(pcb->unacked == NULL) - pcb->rtime = -1; - else { - pcb->rtime = 0; - pcb->nrtx = 0; - } - - tcp_seg_free(rseg); - - /* Call the user specified function to call when sucessfully - * connected. */ - TCP_EVENT_CONNECTED(pcb, ERR_OK, err); - tcp_ack_now(pcb); - } - /* received ACK? possibly a half-open connection */ - else if (flags & TCP_ACK) { - /* send a RST to bring the other side in a non-synchronized state. */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - break; - case SYN_RCVD: - if (flags & TCP_ACK) { - /* expected ACK number? */ - if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { - u16_t old_cwnd; - pcb->state = ESTABLISHED; - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); -#if LWIP_CALLBACK_API - LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); -#endif - /* Call the accept function. */ - TCP_EVENT_ACCEPT(pcb, ERR_OK, err); - if (err != ERR_OK) { - /* If the accept function returns with an error, we abort - * the connection. */ - tcp_abort(pcb); - return ERR_ABRT; - } - old_cwnd = pcb->cwnd; - /* If there was any data contained within this ACK, - * we'd better pass it on to the application as well. */ - tcp_receive(pcb); - - /* Prevent ACK for SYN to generate a sent event */ - if (pcb->acked != 0) { - pcb->acked--; - } - - pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss); - - if (recv_flags & TF_GOT_FIN) { - tcp_ack_now(pcb); - pcb->state = CLOSE_WAIT; - } - } - /* incorrect ACK number */ - else { - /* send RST */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { - /* Looks like another copy of the SYN - retransmit our SYN-ACK */ - tcp_rexmit(pcb); - } - break; - case CLOSE_WAIT: - /* FALLTHROUGH */ - case ESTABLISHED: - tcp_receive(pcb); - if (recv_flags & TF_GOT_FIN) { /* passive close */ - tcp_ack_now(pcb); - pcb->state = CLOSE_WAIT; - } - break; - case FIN_WAIT_1: - tcp_receive(pcb); - if (recv_flags & TF_GOT_FIN) { - if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) { - LWIP_DEBUGF(TCP_DEBUG, - ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } else { - tcp_ack_now(pcb); - pcb->state = CLOSING; - } - } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) { - pcb->state = FIN_WAIT_2; - } - break; - case FIN_WAIT_2: - tcp_receive(pcb); - if (recv_flags & TF_GOT_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case CLOSING: - tcp_receive(pcb); - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case LAST_ACK: - tcp_receive(pcb); - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ - recv_flags |= TF_CLOSED; - } - break; - default: - break; - } - return ERR_OK; -} - -#if TCP_QUEUE_OOSEQ -/** - * Insert segment into the list (segments covered with new one will be deleted) - * - * Called from tcp_receive() - */ -static void -tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) -{ - struct tcp_seg *old_seg; - - if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { - /* received segment overlaps all following segments */ - tcp_segs_free(next); - next = NULL; - } - else { - /* delete some following segments - oos queue may have segments with FIN flag */ - while (next && - TCP_SEQ_GEQ((seqno + cseg->len), - (next->tcphdr->seqno + next->len))) { - /* cseg with FIN already processed */ - if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { - TCPH_FLAGS_SET(cseg->tcphdr, TCPH_FLAGS(cseg->tcphdr) | TCP_FIN); - } - old_seg = next; - next = next->next; - tcp_seg_free(old_seg); - } - if (next && - TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { - /* We need to trim the incoming segment. */ - cseg->len = (u16_t)(next->tcphdr->seqno - seqno); - pbuf_realloc(cseg->p, cseg->len); - } - } - cseg->next = next; -} -#endif - -/** - * Called by tcp_process. Checks if the given segment is an ACK for outstanding - * data, and if so frees the memory of the buffered data. Next, is places the - * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment - * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until - * i it has been removed from the buffer. - * - * If the incoming segment constitutes an ACK for a segment that was used for RTT - * estimation, the RTT is estimated here as well. - * - * Called from tcp_process(). - */ -static void -tcp_receive(struct tcp_pcb *pcb) -{ - struct tcp_seg *next; -#if TCP_QUEUE_OOSEQ - struct tcp_seg *prev, *cseg; -#endif - struct pbuf *p; - s32_t off; - s16_t m; - u32_t right_wnd_edge; - u16_t new_tot_len; - int found_dupack = 0; - - if (flags & TCP_ACK) { - right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; - - /* Update window. */ - if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || - (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || - (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wl1 = seqno; - pcb->snd_wl2 = ackno; - if (pcb->snd_wnd > 0 && pcb->persist_backoff > 0) { - pcb->persist_backoff = 0; - } - LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U16_F"\n", pcb->snd_wnd)); -#if TCP_WND_DEBUG - } else { - if (pcb->snd_wnd != tcphdr->wnd) { - LWIP_DEBUGF(TCP_WND_DEBUG, - ("tcp_receive: no window update lastack %"U32_F" ackno %" - U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", - pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); - } -#endif /* TCP_WND_DEBUG */ - } - - /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a - * duplicate ack if: - * 1) It doesn't ACK new data - * 2) length of received packet is zero (i.e. no payload) - * 3) the advertised window hasn't changed - * 4) There is outstanding unacknowledged data (retransmission timer running) - * 5) The ACK is == biggest ACK sequence number so far seen (snd_una) - * - * If it passes all five, should process as a dupack: - * a) dupacks < 3: do nothing - * b) dupacks == 3: fast retransmit - * c) dupacks > 3: increase cwnd - * - * If it only passes 1-3, should reset dupack counter (and add to - * stats, which we don't do in lwIP) - * - * If it only passes 1, should reset dupack counter - * - */ - - /* Clause 1 */ - if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { - pcb->acked = 0; - /* Clause 2 */ - if (tcplen == 0) { - /* Clause 3 */ - if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge){ - /* Clause 4 */ - if (pcb->rtime >= 0) { - /* Clause 5 */ - if (pcb->lastack == ackno) { - found_dupack = 1; - if (pcb->dupacks + 1 > pcb->dupacks) - ++pcb->dupacks; - if (pcb->dupacks > 3) { - /* Inflate the congestion window, but not if it means that - the value overflows. */ - if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - } else if (pcb->dupacks == 3) { - /* Do fast retransmit */ - tcp_rexmit_fast(pcb); - } - } - } - } - } - /* If Clause (1) or more is true, but not a duplicate ack, reset - * count of consecutive duplicate acks */ - if (!found_dupack) { - pcb->dupacks = 0; - } - } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){ - /* We come here when the ACK acknowledges new data. */ - - /* Reset the "IN Fast Retransmit" flag, since we are no longer - in fast retransmit. Also reset the congestion window to the - slow start threshold. */ - if (pcb->flags & TF_INFR) { - pcb->flags &= ~TF_INFR; - pcb->cwnd = pcb->ssthresh; - } - - /* Reset the number of retransmissions. */ - pcb->nrtx = 0; - - /* Reset the retransmission time-out. */ - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - /* Update the send buffer space. Diff between the two can never exceed 64K? */ - pcb->acked = (u16_t)(ackno - pcb->lastack); - - pcb->snd_buf += pcb->acked; - - /* Reset the fast retransmit variables. */ - pcb->dupacks = 0; - pcb->lastack = ackno; - - /* Update the congestion control variables (cwnd and - ssthresh). */ - if (pcb->state >= ESTABLISHED) { - if (pcb->cwnd < pcb->ssthresh) { - if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); - } else { - u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); - if (new_cwnd > pcb->cwnd) { - pcb->cwnd = new_cwnd; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); - } - } - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", - ackno, - pcb->unacked != NULL? - ntohl(pcb->unacked->tcphdr->seqno): 0, - pcb->unacked != NULL? - ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); - - /* Remove segment from the unacknowledged list if the incoming - ACK acknowlegdes them. */ - while (pcb->unacked != NULL && - TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked), ackno)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", - ntohl(pcb->unacked->tcphdr->seqno), - ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked))); - - next = pcb->unacked; - pcb->unacked = pcb->unacked->next; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); - LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); - /* Prevent ACK for FIN to generate a sent event */ - if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) { - pcb->acked--; - } - - pcb->snd_queuelen -= pbuf_clen(next->p); - tcp_seg_free(next); - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - } - - /* If there's nothing left to acknowledge, stop the retransmit - timer, otherwise reset it to start again */ - if(pcb->unacked == NULL) - pcb->rtime = -1; - else - pcb->rtime = 0; - - pcb->polltmr = 0; - } else { - /* Fix bug bug #21582: out of sequence ACK, didn't really ack anything */ - pcb->acked = 0; - } - - /* We go through the ->unsent list to see if any of the segments - on the list are acknowledged by the ACK. This may seem - strange since an "unsent" segment shouldn't be acked. The - rationale is that lwIP puts all outstanding segments on the - ->unsent list after a retransmission, so these segments may - in fact have been sent once. */ - while (pcb->unsent != NULL && - TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + - TCP_TCPLEN(pcb->unsent), pcb->snd_nxt)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", - ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + - TCP_TCPLEN(pcb->unsent))); - - next = pcb->unsent; - pcb->unsent = pcb->unsent->next; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); - LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); - /* Prevent ACK for FIN to generate a sent event */ - if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) { - pcb->acked--; - } - pcb->snd_queuelen -= pbuf_clen(next->p); - tcp_seg_free(next); - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - } - /* End of ACK for new data processing. */ - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", - pcb->rttest, pcb->rtseq, ackno)); - - /* RTT estimation calculations. This is done by checking if the - incoming segment acknowledges the segment we use to take a - round-trip time measurement. */ - if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { - /* diff between this shouldn't exceed 32K since this are tcp timer ticks - and a round-trip shouldn't be that long... */ - m = (s16_t)(tcp_ticks - pcb->rttest); - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", - m, m * TCP_SLOW_INTERVAL)); - - /* This is taken directly from VJs original code in his paper */ - m = m - (pcb->sa >> 3); - pcb->sa += m; - if (m < 0) { - m = -m; - } - m = m - (pcb->sv >> 2); - pcb->sv += m; - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", - pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); - - pcb->rttest = 0; - } - } - - /* If the incoming segment contains data, we must process it - further. */ - if (tcplen > 0) { - /* This code basically does three things: - - +) If the incoming segment contains data that is the next - in-sequence data, this data is passed to the application. This - might involve trimming the first edge of the data. The rcv_nxt - variable and the advertised window are adjusted. - - +) If the incoming segment has data that is above the next - sequence number expected (->rcv_nxt), the segment is placed on - the ->ooseq queue. This is done by finding the appropriate - place in the ->ooseq queue (which is ordered by sequence - number) and trim the segment in both ends if needed. An - immediate ACK is sent to indicate that we received an - out-of-sequence segment. - - +) Finally, we check if the first segment on the ->ooseq queue - now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If - rcv_nxt > ooseq->seqno, we must trim the first edge of the - segment on ->ooseq before we adjust rcv_nxt. The data in the - segments that are now on sequence are chained onto the - incoming segment so that we only need to call the application - once. - */ - - /* First, we check if we must trim the first edge. We have to do - this if the sequence number of the incoming segment is less - than rcv_nxt, and the sequence number plus the length of the - segment is larger than rcv_nxt. */ - /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ - if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ - if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){ - /* Trimming the first edge is done by pushing the payload - pointer in the pbuf downwards. This is somewhat tricky since - we do not want to discard the full contents of the pbuf up to - the new starting point of the data since we have to keep the - TCP header which is present in the first pbuf in the chain. - - What is done is really quite a nasty hack: the first pbuf in - the pbuf chain is pointed to by inseg.p. Since we need to be - able to deallocate the whole pbuf, we cannot change this - inseg.p pointer to point to any of the later pbufs in the - chain. Instead, we point the ->payload pointer in the first - pbuf to data in one of the later pbufs. We also set the - inseg.data pointer to point to the right place. This way, the - ->p pointer will still point to the first pbuf, but the - ->p->payload pointer will point to data in another pbuf. - - After we are done with adjusting the pbuf pointers we must - adjust the ->data pointer in the seg and the segment - length.*/ - - off = pcb->rcv_nxt - seqno; - p = inseg.p; - LWIP_ASSERT("inseg.p != NULL", inseg.p); - LWIP_ASSERT("insane offset!", (off < 0x7fff)); - if (inseg.p->len < off) { - LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); - new_tot_len = (u16_t)(inseg.p->tot_len - off); - while (p->len < off) { - off -= p->len; - /* KJM following line changed (with addition of new_tot_len var) - to fix bug #9076 - inseg.p->tot_len -= p->len; */ - p->tot_len = new_tot_len; - p->len = 0; - p = p->next; - } - if(pbuf_header(p, (s16_t)-off)) { - /* Do we need to cope with this failing? Assert for now */ - LWIP_ASSERT("pbuf_header failed", 0); - } - } else { - if(pbuf_header(inseg.p, (s16_t)-off)) { - /* Do we need to cope with this failing? Assert for now */ - LWIP_ASSERT("pbuf_header failed", 0); - } - } - /* KJM following line changed to use p->payload rather than inseg->p->payload - to fix bug #9076 */ - inseg.dataptr = p->payload; - inseg.len -= (u16_t)(pcb->rcv_nxt - seqno); - inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; - } - else { - if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ - /* the whole segment is < rcv_nxt */ - /* must be a duplicate of a packet that has already been correctly handled */ - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); - tcp_ack_now(pcb); - } - } - - /* The sequence number must be within the window (above rcv_nxt - and below rcv_nxt + rcv_wnd) in order to be further - processed. */ - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, - pcb->rcv_nxt + pcb->rcv_wnd - 1)){ - if (pcb->rcv_nxt == seqno) { - /* The incoming segment is the next in sequence. We check if - we have to trim the end of the segment and update rcv_nxt - and pass the data to the application. */ - tcplen = TCP_TCPLEN(&inseg); - - if (tcplen > pcb->rcv_wnd) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, - ("tcp_receive: other end overran receive window" - "seqno %"U32_F" len %"U32_F" right edge %"U32_F"\n", - seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - /* Must remove the FIN from the header as we're trimming - * that byte of sequence-space from the packet */ - TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) &~ TCP_FIN); - } - /* Adjust length of segment to fit in the window. */ - inseg.len = pcb->rcv_wnd; - if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { - inseg.len -= 1; - } - pbuf_realloc(inseg.p, inseg.len); - tcplen = TCP_TCPLEN(&inseg); - LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", - (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); - } -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL) { - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, - ("tcp_receive: received in-order FIN, binning ooseq queue\n")); - /* Received in-order FIN means anything that was received - * out of order must now have been received in-order, so - * bin the ooseq queue - * rcv_nxt - * . |--ooseq--| - * .==seg============|FIN - */ - while (pcb->ooseq != NULL) { - struct tcp_seg *old_ooseq = pcb->ooseq; - pcb->ooseq = pcb->ooseq->next; - tcp_seg_free(old_ooseq); - } - } - else { - struct tcp_seg* next = pcb->ooseq; - struct tcp_seg *old_seg; - /* rcv_nxt - * . |--ooseq--| - * .==seg============| - */ - while (next && - TCP_SEQ_GEQ(seqno + tcplen, - next->tcphdr->seqno + next->len)) { - /* inseg doesn't have FIN (already processed) */ - if (TCPH_FLAGS(next->tcphdr) & TCP_FIN && - (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { - TCPH_FLAGS_SET(inseg.tcphdr, - TCPH_FLAGS(inseg.tcphdr) | TCP_FIN); - tcplen = TCP_TCPLEN(&inseg); - } - old_seg = next; - next = next->next; - tcp_seg_free(old_seg); - } - /* rcv_nxt - * . |--ooseq--| - * .==seg============| - */ - if (next && - TCP_SEQ_GT(seqno + tcplen, - next->tcphdr->seqno)) { - /* FIN in inseg already handled by dropping whole ooseq queue */ - inseg.len = (u16_t)(pcb->ooseq->tcphdr->seqno - seqno); - if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { - inseg.len -= 1; - } - pbuf_realloc(inseg.p, inseg.len); - tcplen = TCP_TCPLEN(&inseg); - LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", - (seqno + tcplen) == pcb->ooseq->tcphdr->seqno); - } - pcb->ooseq = next; - } - } -#endif /* TCP_QUEUE_OOSEQ */ - - pcb->rcv_nxt = seqno + tcplen; - - /* Update the receiver's (our) window. */ - LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); - pcb->rcv_wnd -= tcplen; - - tcp_update_rcv_ann_wnd(pcb); - - /* If there is data in the segment, we make preparations to - pass this up to the application. The ->recv_data variable - is used for holding the pbuf that goes to the - application. The code for reassembling out-of-sequence data - chains its data on this pbuf as well. - - If the segment was a FIN, we set the TF_GOT_FIN flag that will - be used to indicate to the application that the remote side has - closed its end of the connection. */ - if (inseg.p->tot_len > 0) { - recv_data = inseg.p; - /* Since this pbuf now is the responsibility of the - application, we delete our reference to it so that we won't - (mistakingly) deallocate it. */ - inseg.p = NULL; - } - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); - recv_flags |= TF_GOT_FIN; - } - -#if TCP_QUEUE_OOSEQ - /* We now check if we have segments on the ->ooseq queue that - is now in sequence. */ - while (pcb->ooseq != NULL && - pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { - - cseg = pcb->ooseq; - seqno = pcb->ooseq->tcphdr->seqno; - - pcb->rcv_nxt += TCP_TCPLEN(cseg); - LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", - pcb->rcv_wnd >= TCP_TCPLEN(cseg)); - pcb->rcv_wnd -= TCP_TCPLEN(cseg); - - tcp_update_rcv_ann_wnd(pcb); - - if (cseg->p->tot_len > 0) { - /* Chain this pbuf onto the pbuf that we will pass to - the application. */ - if (recv_data) { - pbuf_cat(recv_data, cseg->p); - } else { - recv_data = cseg->p; - } - cseg->p = NULL; - } - if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); - recv_flags |= TF_GOT_FIN; - if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ - pcb->state = CLOSE_WAIT; - } - } - - pcb->ooseq = cseg->next; - tcp_seg_free(cseg); - } -#endif /* TCP_QUEUE_OOSEQ */ - - - /* Acknowledge the segment(s). */ - tcp_ack(pcb); - - } else { - /* We get here if the incoming segment is out-of-sequence. */ - tcp_send_empty_ack(pcb); -#if TCP_QUEUE_OOSEQ - /* We queue the segment on the ->ooseq queue. */ - if (pcb->ooseq == NULL) { - pcb->ooseq = tcp_seg_copy(&inseg); - } else { - /* If the queue is not empty, we walk through the queue and - try to find a place where the sequence number of the - incoming segment is between the sequence numbers of the - previous and the next segment on the ->ooseq queue. That is - the place where we put the incoming segment. If needed, we - trim the second edges of the previous and the incoming - segment so that it will fit into the sequence. - - If the incoming segment has the same sequence number as a - segment on the ->ooseq queue, we discard the segment that - contains less data. */ - - prev = NULL; - for(next = pcb->ooseq; next != NULL; next = next->next) { - if (seqno == next->tcphdr->seqno) { - /* The sequence number of the incoming segment is the - same as the sequence number of the segment on - ->ooseq. We check the lengths to see which one to - discard. */ - if (inseg.len > next->len) { - /* The incoming segment is larger than the old - segment. We replace some segments with the new - one. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - if (prev != NULL) { - prev->next = cseg; - } else { - pcb->ooseq = cseg; - } - tcp_oos_insert_segment(cseg, next); - } - break; - } else { - /* Either the lenghts are the same or the incoming - segment was smaller than the old one; in either - case, we ditch the incoming segment. */ - break; - } - } else { - if (prev == NULL) { - if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { - /* The sequence number of the incoming segment is lower - than the sequence number of the first segment on the - queue. We put the incoming segment first on the - queue. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - pcb->ooseq = cseg; - tcp_oos_insert_segment(cseg, next); - } - break; - } - } else { - /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && - TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ - if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)) { - /* The sequence number of the incoming segment is in - between the sequence numbers of the previous and - the next segment on ->ooseq. We trim trim the previous - segment, delete next segments that included in received segment - and trim received, if needed. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { - /* We need to trim the prev segment. */ - prev->len = (u16_t)(seqno - prev->tcphdr->seqno); - pbuf_realloc(prev->p, prev->len); - } - prev->next = cseg; - tcp_oos_insert_segment(cseg, next); - } - break; - } - } - /* If the "next" segment is the last segment on the - ooseq queue, we add the incoming segment to the end - of the list. */ - if (next->next == NULL && - TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { - if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { - /* segment "next" already contains all data */ - break; - } - next->next = tcp_seg_copy(&inseg); - if (next->next != NULL) { - if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { - /* We need to trim the last segment. */ - next->len = (u16_t)(seqno - next->tcphdr->seqno); - pbuf_realloc(next->p, next->len); - } - } - break; - } - } - prev = next; - } - } -#endif /* TCP_QUEUE_OOSEQ */ - - } - } else { - /* The incoming segment is not withing the window. */ - tcp_send_empty_ack(pcb); - } - } else { - /* Segments with length 0 is taken care of here. Segments that - fall out of the window are ACKed. */ - /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || - TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ - tcp_ack_now(pcb); - } - } -} - -/** - * Parses the options contained in the incoming segment. - * - * Called from tcp_listen_input() and tcp_process(). - * Currently, only the MSS option is supported! - * - * @param pcb the tcp_pcb for which a segment arrived - */ -static void -tcp_parseopt(struct tcp_pcb *pcb) -{ - u16_t c, max_c; - u16_t mss; - u8_t *opts, opt; -#if LWIP_TCP_TIMESTAMPS - u32_t tsval; -#endif - - opts = (u8_t *)tcphdr + TCP_HLEN; - - /* Parse the TCP MSS option, if present. */ - if(TCPH_HDRLEN(tcphdr) > 0x5) { - max_c = (TCPH_HDRLEN(tcphdr) - 5) << 2; - for (c = 0; c < max_c; ) { - opt = opts[c]; - switch (opt) { - case 0x00: - /* End of options. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); - return; - case 0x01: - /* NOP option. */ - ++c; - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); - break; - case 0x02: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); - if (opts[c + 1] != 0x04 || c + 0x04 > max_c) { - /* Bad length */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - return; - } - /* An MSS option with the right option length. */ - mss = (opts[c + 2] << 8) | opts[c + 3]; - /* Limit the mss to the configured TCP_MSS and prevent division by zero */ - pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; - /* Advance to next option */ - c += 0x04; - break; -#if LWIP_TCP_TIMESTAMPS - case 0x08: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n")); - if (opts[c + 1] != 0x0A || c + 0x0A > max_c) { - /* Bad length */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - return; - } - /* TCP timestamp option with valid length */ - tsval = (opts[c+2]) | (opts[c+3] << 8) | - (opts[c+4] << 16) | (opts[c+5] << 24); - if (flags & TCP_SYN) { - pcb->ts_recent = ntohl(tsval); - pcb->flags |= TF_TIMESTAMP; - } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno+tcplen)) { - pcb->ts_recent = ntohl(tsval); - } - /* Advance to next option */ - c += 0x0A; - break; -#endif - default: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); - if (opts[c + 1] == 0) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); - /* If the length field is zero, the options are malformed - and we don't process them further. */ - return; - } - /* All other options have a length field, so that we easily - can skip past them. */ - c += opts[c + 1]; - } - } - } -} - -#endif /* LWIP_TCP */ diff --git a/components/net/lwip-1.3.2/src/core/tcp_out.c b/components/net/lwip-1.3.2/src/core/tcp_out.c deleted file mode 100644 index ddada4204a..0000000000 --- a/components/net/lwip-1.3.2/src/core/tcp_out.c +++ /dev/null @@ -1,1054 +0,0 @@ -/** - * @file - * Transmission Control Protocol, outgoing traffic - * - * The output functions of TCP. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/tcp.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/sys.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet.h" -#include "lwip/inet_chksum.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" - -#include - -/* Forward declarations.*/ -static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); - -static struct tcp_hdr * -tcp_output_set_header(struct tcp_pcb *pcb, struct pbuf *p, int optlen, - u32_t seqno_be /* already in network byte order */) -{ - struct tcp_hdr *tcphdr = p->payload; - tcphdr->src = htons(pcb->local_port); - tcphdr->dest = htons(pcb->remote_port); - tcphdr->seqno = seqno_be; - tcphdr->ackno = htonl(pcb->rcv_nxt); - TCPH_FLAGS_SET(tcphdr, TCP_ACK); - tcphdr->wnd = htons(pcb->rcv_ann_wnd); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, (5 + optlen / 4)); - tcphdr->chksum = 0; - - /* If we're sending a packet, update the announced right window edge */ - pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; - - return tcphdr; -} - -/** - * Called by tcp_close() to send a segment including flags but not data. - * - * @param pcb the tcp_pcb over which to send a segment - * @param flags the flags to set in the segment header - * @return ERR_OK if sent, another err_t otherwise - */ -err_t -tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) -{ - /* no data, no length, flags, copy=1, no optdata */ - return tcp_enqueue(pcb, NULL, 0, flags, TCP_WRITE_FLAG_COPY, 0); -} - -/** - * Write data for sending (but does not send it immediately). - * - * It waits in the expectation of more data being sent soon (as - * it can send them more efficiently by combining them together). - * To prompt the system to send data now, call tcp_output() after - * calling tcp_write(). - * - * @param pcb Protocol control block of the TCP connection to enqueue data for. - * @param data pointer to the data to send - * @param len length (in bytes) of the data to send - * @param apiflags combination of following flags : - * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack - * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent, - * @return ERR_OK if enqueued, another err_t on error - * - * @see tcp_write() - */ -err_t -tcp_write(struct tcp_pcb *pcb, const void *data, u16_t len, u8_t apiflags) -{ - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", (void *)pcb, - data, len, (u16_t)apiflags)); - /* connection is in valid state for data transmission? */ - if (pcb->state == ESTABLISHED || - pcb->state == CLOSE_WAIT || - pcb->state == SYN_SENT || - pcb->state == SYN_RCVD) { - if (len > 0) { -#if LWIP_TCP_TIMESTAMPS - return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, - pcb->flags & TF_TIMESTAMP ? TF_SEG_OPTS_TS : 0); -#else - return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, 0); -#endif - } - return ERR_OK; - } else { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); - return ERR_CONN; - } -} - -/** - * Enqueue data and/or TCP options for transmission - * - * Called by tcp_connect(), tcp_listen_input(), tcp_send_ctrl() and tcp_write(). - * - * @param pcb Protocol control block for the TCP connection to enqueue data for. - * @param arg Pointer to the data to be enqueued for sending. - * @param len Data length in bytes - * @param flags tcp header flags to set in the outgoing segment - * @param apiflags combination of following flags : - * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack - * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent, - * @param optflags options to include in segment later on (see definition of struct tcp_seg) - */ -err_t -tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, - u8_t flags, u8_t apiflags, u8_t optflags) -{ - struct pbuf *p; - struct tcp_seg *seg, *useg, *queue; - u32_t seqno; - u16_t left, seglen; - void *ptr; - u16_t queuelen; - u8_t optlen; - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, - ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", apiflags=%"U16_F")\n", - (void *)pcb, arg, len, (u16_t)flags, (u16_t)apiflags)); - LWIP_ERROR("tcp_enqueue: packet needs payload, options, or SYN/FIN (programmer violates API)", - ((len != 0) || (optflags != 0) || ((flags & (TCP_SYN | TCP_FIN)) != 0)), - return ERR_ARG;); - LWIP_ERROR("tcp_enqueue: len != 0 || arg == NULL (programmer violates API)", - ((len != 0) || (arg == NULL)), return ERR_ARG;); - - /* fail on too much data */ - if (len > pcb->snd_buf) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_WARNING, - ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); - pcb->flags |= TF_NAGLEMEMERR; - return ERR_MEM; - } - left = len; - ptr = arg; - - optlen = LWIP_TCP_OPT_LENGTH(optflags); - - /* seqno will be the sequence number of the first segment enqueued - * by the call to this function. */ - seqno = pcb->snd_lbb; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - - /* If total number of pbufs on the unsent/unacked queues exceeds the - * configured maximum, return an error */ - queuelen = pcb->snd_queuelen; - /* check for configured max queuelen and possible overflow */ - if ((queuelen >= TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_WARNING, - ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); - TCP_STATS_INC(tcp.memerr); - pcb->flags |= TF_NAGLEMEMERR; - return ERR_MEM; - } - if (queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", - pcb->unacked != NULL || pcb->unsent != NULL); - } else { - LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", - pcb->unacked == NULL && pcb->unsent == NULL); - } - - /* First, break up the data into segments and tuck them together in - * the local "queue" variable. */ - useg = queue = seg = NULL; - seglen = 0; - while (queue == NULL || left > 0) { - /* The segment length (including options) should be at most the MSS */ - seglen = left > (pcb->mss - optlen) ? (pcb->mss - optlen) : left; - - /* Allocate memory for tcp_seg, and fill in fields. */ - seg = memp_malloc(MEMP_TCP_SEG); - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_enqueue: could not allocate memory for tcp_seg\n")); - goto memerr; - } - seg->next = NULL; - seg->p = NULL; - - /* first segment of to-be-queued data? */ - if (queue == NULL) { - queue = seg; - } - /* subsequent segments of to-be-queued data */ - else { - /* Attach the segment to the end of the queued segments */ - LWIP_ASSERT("useg != NULL", useg != NULL); - useg->next = seg; - } - /* remember last segment of to-be-queued data for next iteration */ - useg = seg; - - /* If copy is set, memory should be allocated - * and data copied into pbuf, otherwise data comes from - * ROM or other static memory, and need not be copied. */ - if (apiflags & TCP_WRITE_FLAG_COPY) { - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen + optlen, PBUF_RAM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); - goto memerr; - } - LWIP_ASSERT("check that first pbuf can hold the complete seglen", - (seg->p->len >= seglen + optlen)); - queuelen += pbuf_clen(seg->p); - if (arg != NULL) { - MEMCPY((char *)seg->p->payload + optlen, ptr, seglen); - } - seg->dataptr = seg->p->payload; - } - /* do not copy data */ - else { - /* First, allocate a pbuf for the headers. */ - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_enqueue: could not allocate memory for header pbuf\n")); - goto memerr; - } - queuelen += pbuf_clen(seg->p); - - /* Second, allocate a pbuf for holding the data. - * since the referenced data is available at least until it is sent out on the - * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM - * instead of PBUF_REF here. - */ - if (left > 0) { - if ((p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { - /* If allocation fails, we have to deallocate the header pbuf as well. */ - pbuf_free(seg->p); - seg->p = NULL; - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n")); - goto memerr; - } - ++queuelen; - /* reference the non-volatile payload data */ - p->payload = ptr; - seg->dataptr = ptr; - - /* Concatenate the headers and data pbufs together. */ - pbuf_cat(seg->p/*header*/, p/*data*/); - p = NULL; - } - } - - /* Now that there are more segments queued, we check again if the - length of the queue exceeds the configured maximum or overflows. */ - if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); - goto memerr; - } - - seg->len = seglen; - - /* build TCP header */ - if (pbuf_header(seg->p, TCP_HLEN)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_enqueue: no room for TCP header in pbuf.\n")); - TCP_STATS_INC(tcp.err); - goto memerr; - } - seg->tcphdr = seg->p->payload; - seg->tcphdr->src = htons(pcb->local_port); - seg->tcphdr->dest = htons(pcb->remote_port); - seg->tcphdr->seqno = htonl(seqno); - seg->tcphdr->urgp = 0; - TCPH_FLAGS_SET(seg->tcphdr, flags); - /* don't fill in tcphdr->ackno and tcphdr->wnd until later */ - - seg->flags = optflags; - - /* Set the length of the header */ - TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4)); - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", - ntohl(seg->tcphdr->seqno), - ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), - (u16_t)flags)); - - left -= seglen; - seqno += seglen; - ptr = (void *)((u8_t *)ptr + seglen); - } - - /* Now that the data to be enqueued has been broken up into TCP - segments in the queue variable, we add them to the end of the - pcb->unsent queue. */ - if (pcb->unsent == NULL) { - useg = NULL; - } - else { - for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); - } - /* { useg is last segment on the unsent queue, NULL if list is empty } */ - - /* If there is room in the last pbuf on the unsent queue, - chain the first pbuf on the queue together with that. */ - if (useg != NULL && - TCP_TCPLEN(useg) != 0 && - !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && - (!(flags & (TCP_SYN | TCP_FIN)) || (flags == TCP_FIN)) && - /* fit within max seg size */ - (useg->len + queue->len <= pcb->mss) && - /* only concatenate segments with the same options */ - (useg->flags == queue->flags) && - /* segments are consecutive */ - (ntohl(useg->tcphdr->seqno) + useg->len == ntohl(queue->tcphdr->seqno)) ) { - /* Remove TCP header from first segment of our to-be-queued list */ - if(pbuf_header(queue->p, -(TCP_HLEN + optlen))) { - /* Can we cope with this failing? Just assert for now */ - LWIP_ASSERT("pbuf_header failed\n", 0); - TCP_STATS_INC(tcp.err); - goto memerr; - } - if (queue->p->len == 0) { - /* free the first (header-only) pbuf if it is now empty (contained only headers) */ - struct pbuf *old_q = queue->p; - queue->p = queue->p->next; - old_q->next = NULL; - queuelen--; - pbuf_free(old_q); - } - if (flags & TCP_FIN) { - /* the new segment contains only FIN, no data -> put the FIN into the last segment */ - LWIP_ASSERT("FIN enqueued together with data", queue->p == NULL && queue->len == 0); - TCPH_SET_FLAG(useg->tcphdr, TCP_FIN); - } else { - LWIP_ASSERT("zero-length pbuf", (queue->p != NULL) && (queue->p->len > 0)); - pbuf_cat(useg->p, queue->p); - useg->len += queue->len; - useg->next = queue->next; - } - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); - if (seg == queue) { - seg = useg; - seglen = useg->len; - } - memp_free(MEMP_TCP_SEG, queue); - } - else { - /* empty list */ - if (useg == NULL) { - /* initialize list with this segment */ - pcb->unsent = queue; - } - /* enqueue segment */ - else { - useg->next = queue; - } - } - if ((flags & TCP_SYN) || (flags & TCP_FIN)) { - ++len; - } - if (flags & TCP_FIN) { - pcb->flags |= TF_FIN; - } - pcb->snd_lbb += len; - - pcb->snd_buf -= len; - - /* update number of segments on the queues */ - pcb->snd_queuelen = queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - /* Set the PSH flag in the last segment that we enqueued, but only - if the segment has data (indicated by seglen > 0). */ - if (seg != NULL && seglen > 0 && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) { - TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); - } - - return ERR_OK; -memerr: - pcb->flags |= TF_NAGLEMEMERR; - TCP_STATS_INC(tcp.memerr); - - if (queue != NULL) { - tcp_segs_free(queue); - } - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); - return ERR_MEM; -} - - -#if LWIP_TCP_TIMESTAMPS -/* Build a timestamp option (12 bytes long) at the specified options pointer) - * - * @param pcb tcp_pcb - * @param opts option pointer where to store the timestamp option - */ -static void -tcp_build_timestamp_option(struct tcp_pcb *pcb, u32_t *opts) -{ - /* Pad with two NOP options to make everything nicely aligned */ - opts[0] = htonl(0x0101080A); - opts[1] = htonl(sys_now()); - opts[2] = htonl(pcb->ts_recent); -} -#endif - -/** Send an ACK without data. - * - * @param pcb Protocol control block for the TCP connection to send the ACK - */ -err_t -tcp_send_empty_ack(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - u8_t optlen = 0; - -#if LWIP_TCP_TIMESTAMPS - if (pcb->flags & TF_TIMESTAMP) { - optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS); - } -#endif - p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); - return ERR_BUF; - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, - ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); - /* remove ACK flags from the PCB, as we send an empty ACK now */ - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - - tcphdr = tcp_output_set_header(pcb, p, optlen, htonl(pcb->snd_nxt)); - - /* NB. MSS option is only sent on SYNs, so ignore it here */ -#if LWIP_TCP_TIMESTAMPS - pcb->ts_lastacksent = pcb->rcv_nxt; - - if (pcb->flags & TF_TIMESTAMP) { - tcp_build_timestamp_option(pcb, (u32_t *)(tcphdr + 1)); - } -#endif - -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), - IP_PROTO_TCP, p->tot_len); -#endif -#if LWIP_NETIF_HWADDRHINT - ip_output_hinted(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP, &(pcb->addr_hint)); -#else /* LWIP_NETIF_HWADDRHINT*/ - ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP); -#endif /* LWIP_NETIF_HWADDRHINT*/ - pbuf_free(p); - - return ERR_OK; -} - -/** - * Find out what we can send and send it - * - * @param pcb Protocol control block for the TCP connection to send data - * @return ERR_OK if data has been sent or nothing to send - * another err_t on error - */ -err_t -tcp_output(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg, *useg; - u32_t wnd, snd_nxt; -#if TCP_CWND_DEBUG - s16_t i = 0; -#endif /* TCP_CWND_DEBUG */ - - /* First, check if we are invoked by the TCP input processing - code. If so, we do not output anything. Instead, we rely on the - input processing code to call us when input processing is done - with. */ - if (tcp_input_pcb == pcb) { - return ERR_OK; - } - - wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); - - seg = pcb->unsent; - - /* If the TF_ACK_NOW flag is set and no data will be sent (either - * because the ->unsent queue is empty or because the window does - * not allow it), construct an empty ACK segment and send it. - * - * If data is to be sent, we will just piggyback the ACK (see below). - */ - if (pcb->flags & TF_ACK_NOW && - (seg == NULL || - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { - return tcp_send_empty_ack(pcb); - } - - /* useg should point to last segment on unacked queue */ - useg = pcb->unacked; - if (useg != NULL) { - for (; useg->next != NULL; useg = useg->next); - } - -#if TCP_OUTPUT_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", - (void*)pcb->unsent)); - } -#endif /* TCP_OUTPUT_DEBUG */ -#if TCP_CWND_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F - ", cwnd %"U16_F", wnd %"U32_F - ", seg == NULL, ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); - } else { - LWIP_DEBUGF(TCP_CWND_DEBUG, - ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F - ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, - ntohl(seg->tcphdr->seqno), pcb->lastack)); - } -#endif /* TCP_CWND_DEBUG */ - /* data available and window allows it to be sent? */ - while (seg != NULL && - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { - LWIP_ASSERT("RST not expected here!", - (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0); - /* Stop sending if the nagle algorithm would prevent it - * Don't stop: - * - if tcp_enqueue had a memory error before (prevent delayed ACK timeout) or - * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - - * either seg->next != NULL or pcb->unacked == NULL; - * RST is no sent using tcp_enqueue/tcp_output. - */ - if((tcp_do_output_nagle(pcb) == 0) && - ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)){ - break; - } -#if TCP_CWND_DEBUG - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - ntohl(seg->tcphdr->seqno) + seg->len - - pcb->lastack, - ntohl(seg->tcphdr->seqno), pcb->lastack, i)); - ++i; -#endif /* TCP_CWND_DEBUG */ - - pcb->unsent = seg->next; - - if (pcb->state != SYN_SENT) { - TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - - tcp_output_segment(seg, pcb); - snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); - if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { - pcb->snd_nxt = snd_nxt; - } - /* put segment on unacknowledged list if length > 0 */ - if (TCP_TCPLEN(seg) > 0) { - seg->next = NULL; - /* unacked list is empty? */ - if (pcb->unacked == NULL) { - pcb->unacked = seg; - useg = seg; - /* unacked list is not empty? */ - } else { - /* In the case of fast retransmit, the packet should not go to the tail - * of the unacked queue, but rather somewhere before it. We need to check for - * this case. -STJ Jul 27, 2004 */ - if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ - /* add segment to before tail of unacked list, keeping the list sorted */ - struct tcp_seg **cur_seg = &(pcb->unacked); - while (*cur_seg && - TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) { - cur_seg = &((*cur_seg)->next ); - } - seg->next = (*cur_seg); - (*cur_seg) = seg; - } else { - /* add segment to tail of unacked list */ - useg->next = seg; - useg = useg->next; - } - } - /* do not queue empty segments on the unacked list */ - } else { - tcp_seg_free(seg); - } - seg = pcb->unsent; - } - - if (seg != NULL && pcb->persist_backoff == 0 && - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > pcb->snd_wnd) { - /* prepare for persist timer */ - pcb->persist_cnt = 0; - pcb->persist_backoff = 1; - } - - pcb->flags &= ~TF_NAGLEMEMERR; - return ERR_OK; -} - -/** - * Called by tcp_output() to actually send a TCP segment over IP. - * - * @param seg the tcp_seg to send - * @param pcb the tcp_pcb for the TCP connection used to send the segment - */ -static void -tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) -{ - u16_t len; - struct netif *netif; - u32_t *opts; - - /** @bug Exclude retransmitted segments from this count. */ - snmp_inc_tcpoutsegs(); - - /* The TCP header has already been constructed, but the ackno and - wnd fields remain. */ - seg->tcphdr->ackno = htonl(pcb->rcv_nxt); - - /* advertise our receive window size in this TCP segment */ - seg->tcphdr->wnd = htons(pcb->rcv_ann_wnd); - - pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; - - /* Add any requested options. NB MSS option is only set on SYN - packets, so ignore it here */ - opts = (u32_t *)(seg->tcphdr + 1); - if (seg->flags & TF_SEG_OPTS_MSS) { - TCP_BUILD_MSS_OPTION(*opts); - opts += 1; - } -#if LWIP_TCP_TIMESTAMPS - pcb->ts_lastacksent = pcb->rcv_nxt; - - if (seg->flags & TF_SEG_OPTS_TS) { - tcp_build_timestamp_option(pcb, opts); - opts += 3; - } -#endif - - /* If we don't have a local IP address, we get one by - calling ip_route(). */ - if (ip_addr_isany(&(pcb->local_ip))) { - netif = ip_route(&(pcb->remote_ip)); - if (netif == NULL) { - return; - } - ip_addr_set(&(pcb->local_ip), &(netif->ip_addr)); - } - - /* Set retransmission timer running if it is not currently enabled */ - if(pcb->rtime == -1) - pcb->rtime = 0; - - if (pcb->rttest == 0) { - pcb->rttest = tcp_ticks; - pcb->rtseq = ntohl(seg->tcphdr->seqno); - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", - htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + - seg->len)); - - len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); - - seg->p->len -= len; - seg->p->tot_len -= len; - - seg->p->payload = seg->tcphdr; - - seg->tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, - &(pcb->local_ip), - &(pcb->remote_ip), - IP_PROTO_TCP, seg->p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - -#if LWIP_NETIF_HWADDRHINT - ip_output_hinted(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP, &(pcb->addr_hint)); -#else /* LWIP_NETIF_HWADDRHINT*/ - ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP); -#endif /* LWIP_NETIF_HWADDRHINT*/ -} - -/** - * Send a TCP RESET packet (empty segment with RST flag set) either to - * abort a connection or to show that there is no matching local connection - * for a received segment. - * - * Called by tcp_abort() (to abort a local connection), tcp_input() (if no - * matching local pcb was found), tcp_listen_input() (if incoming segment - * has ACK flag set) and tcp_process() (received segment in the wrong state) - * - * Since a RST segment is in most cases not sent for an active connection, - * tcp_rst() has a number of arguments that are taken from a tcp_pcb for - * most other segment output functions. - * - * @param seqno the sequence number to use for the outgoing segment - * @param ackno the acknowledge number to use for the outgoing segment - * @param local_ip the local IP address to send the segment from - * @param remote_ip the remote IP address to send the segment to - * @param local_port the local TCP port to send the segment from - * @param remote_port the remote TCP port to send the segment to - */ -void -tcp_rst(u32_t seqno, u32_t ackno, - struct ip_addr *local_ip, struct ip_addr *remote_ip, - u16_t local_port, u16_t remote_port) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); - return; - } - LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", - (p->len >= sizeof(struct tcp_hdr))); - - tcphdr = p->payload; - tcphdr->src = htons(local_port); - tcphdr->dest = htons(remote_port); - tcphdr->seqno = htonl(seqno); - tcphdr->ackno = htonl(ackno); - TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK); - tcphdr->wnd = htons(TCP_WND); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, - IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - snmp_inc_tcpoutrsts(); - /* Send output with hardcoded TTL since we have no access to the pcb */ - ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); - pbuf_free(p); - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); -} - -/** - * Requeue all unacked segments for retransmission - * - * Called by tcp_slowtmr() for slow retransmission. - * - * @param pcb the tcp_pcb for which to re-enqueue all unacked segments - */ -void -tcp_rexmit_rto(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move all unacked segments to the head of the unsent queue */ - for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); - /* concatenate unsent queue after unacked queue */ - seg->next = pcb->unsent; - /* unsent queue is the concatenated queue (of unacked, unsent) */ - pcb->unsent = pcb->unacked; - /* unacked queue is now empty */ - pcb->unacked = NULL; - - /* increment number of retransmissions */ - ++pcb->nrtx; - - /* Don't take any RTT measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission */ - tcp_output(pcb); -} - -/** - * Requeue the first unacked segment for retransmission - * - * Called by tcp_receive() for fast retramsmit. - * - * @param pcb the tcp_pcb for which to retransmit the first unacked segment - */ -void -tcp_rexmit(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - struct tcp_seg **cur_seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move the first unacked segment to the unsent queue */ - /* Keep the unsent queue sorted. */ - seg = pcb->unacked; - pcb->unacked = seg->next; - - cur_seg = &(pcb->unsent); - while (*cur_seg && - TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) { - cur_seg = &((*cur_seg)->next ); - } - seg->next = *cur_seg; - *cur_seg = seg; - - ++pcb->nrtx; - - /* Don't take any rtt measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission. */ - snmp_inc_tcpretranssegs(); - /* No need to call tcp_output: we are always called from tcp_input() - and thus tcp_output directly returns. */ -} - - -/** - * Handle retransmission after three dupacks received - * - * @param pcb the tcp_pcb for which to retransmit the first unacked segment - */ -void -tcp_rexmit_fast(struct tcp_pcb *pcb) -{ - if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { - /* This is fast retransmit. Retransmit the first unacked segment. */ - LWIP_DEBUGF(TCP_FR_DEBUG, - ("tcp_receive: dupacks %"U16_F" (%"U32_F - "), fast retransmit %"U32_F"\n", - (u16_t)pcb->dupacks, pcb->lastack, - ntohl(pcb->unacked->tcphdr->seqno))); - tcp_rexmit(pcb); - - /* Set ssthresh to half of the minimum of the current - * cwnd and the advertised window */ - if (pcb->cwnd > pcb->snd_wnd) - pcb->ssthresh = pcb->snd_wnd / 2; - else - pcb->ssthresh = pcb->cwnd / 2; - - /* The minimum value for ssthresh should be 2 MSS */ - if (pcb->ssthresh < 2*pcb->mss) { - LWIP_DEBUGF(TCP_FR_DEBUG, - ("tcp_receive: The minimum value for ssthresh %"U16_F - " should be min 2 mss %"U16_F"...\n", - pcb->ssthresh, 2*pcb->mss)); - pcb->ssthresh = 2*pcb->mss; - } - - pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; - pcb->flags |= TF_INFR; - } -} - - -/** - * Send keepalive packets to keep a connection active although - * no data is sent over it. - * - * Called by tcp_slowtmr() - * - * @param pcb the tcp_pcb for which to send a keepalive packet - */ -void -tcp_keepalive(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", - tcp_ticks, pcb->tmr, pcb->keep_cnt_sent)); - - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - - if(p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, - ("tcp_keepalive: could not allocate memory for pbuf\n")); - return; - } - LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", - (p->len >= sizeof(struct tcp_hdr))); - - tcphdr = tcp_output_set_header(pcb, p, 0, htonl(pcb->snd_nxt - 1)); - -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, - IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - - /* Send output to IP */ -#if LWIP_NETIF_HWADDRHINT - ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, - &(pcb->addr_hint)); -#else /* LWIP_NETIF_HWADDRHINT*/ - ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); -#endif /* LWIP_NETIF_HWADDRHINT*/ - - pbuf_free(p); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", - pcb->snd_nxt - 1, pcb->rcv_nxt)); -} - - -/** - * Send persist timer zero-window probes to keep a connection active - * when a window update is lost. - * - * Called by tcp_slowtmr() - * - * @param pcb the tcp_pcb for which to send a zero-window probe packet - */ -void -tcp_zero_window_probe(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - struct tcp_seg *seg; - u16_t len; - u8_t is_fin; - - LWIP_DEBUGF(TCP_DEBUG, - ("tcp_zero_window_probe: sending ZERO WINDOW probe to %" - U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - LWIP_DEBUGF(TCP_DEBUG, - ("tcp_zero_window_probe: tcp_ticks %"U32_F - " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", - tcp_ticks, pcb->tmr, pcb->keep_cnt_sent)); - - seg = pcb->unacked; - - if(seg == NULL) - seg = pcb->unsent; - - if(seg == NULL) - return; - - is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); - len = is_fin ? TCP_HLEN : TCP_HLEN + 1; - - p = pbuf_alloc(PBUF_IP, len, PBUF_RAM); - if(p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); - return; - } - LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", - (p->len >= sizeof(struct tcp_hdr))); - - tcphdr = tcp_output_set_header(pcb, p, 0, seg->tcphdr->seqno); - - if (is_fin) { - /* FIN segment, no data */ - TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); - } else { - /* Data segment, copy in one byte from the head of the unacked queue */ - *((char *)p->payload + sizeof(struct tcp_hdr)) = *(char *)seg->dataptr; - } - -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, - IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - - /* Send output to IP */ -#if LWIP_NETIF_HWADDRHINT - ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, - &(pcb->addr_hint)); -#else /* LWIP_NETIF_HWADDRHINT*/ - ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); -#endif /* LWIP_NETIF_HWADDRHINT*/ - - pbuf_free(p); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F - " ackno %"U32_F".\n", - pcb->snd_nxt - 1, pcb->rcv_nxt)); -} -#endif /* LWIP_TCP */ diff --git a/components/net/lwip-1.3.2/src/core/udp.c b/components/net/lwip-1.3.2/src/core/udp.c deleted file mode 100644 index 96dab41b95..0000000000 --- a/components/net/lwip-1.3.2/src/core/udp.c +++ /dev/null @@ -1,841 +0,0 @@ -/** - * @file - * User Datagram Protocol module - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* udp.c - * - * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828). - * - */ - -/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'! - */ - -#include "lwip/opt.h" - -#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/udp.h" -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/inet_chksum.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "arch/perf.h" -#include "lwip/dhcp.h" - -#include - -/* The list of UDP PCBs */ -/* exported in udp.h (was static) */ -struct udp_pcb *udp_pcbs; - -/** - * Process an incoming UDP datagram. - * - * Given an incoming UDP datagram (as a chain of pbufs) this function - * finds a corresponding UDP PCB and hands over the pbuf to the pcbs - * recv function. If no pcb is found or the datagram is incorrect, the - * pbuf is freed. - * - * @param p pbuf to be demultiplexed to a UDP PCB. - * @param inp network interface on which the datagram was received. - * - */ -void -udp_input(struct pbuf *p, struct netif *inp) -{ - struct udp_hdr *udphdr; - struct udp_pcb *pcb, *prev; - struct udp_pcb *uncon_pcb; - struct ip_hdr *iphdr; - u16_t src, dest; - u8_t local_match; - u8_t broadcast; - - PERF_START; - - UDP_STATS_INC(udp.recv); - - iphdr = p->payload; - - /* Check minimum length (IP header + UDP header) - * and move payload pointer to UDP header */ - if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN) || pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4))) { - /* drop short packets */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); - UDP_STATS_INC(udp.lenerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - - udphdr = (struct udp_hdr *)p->payload; - - /* is broadcast packet ? */ - broadcast = ip_addr_isbroadcast(&(iphdr->dest), inp); - - LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); - - /* convert src and dest ports to host byte order */ - src = ntohs(udphdr->src); - dest = ntohs(udphdr->dest); - - udp_debug_print(udphdr); - - /* print the UDP source and destination */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- " - "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", - ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), - ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), - ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), - ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); - -#if LWIP_DHCP - pcb = NULL; - /* when LWIP_DHCP is active, packets to DHCP_CLIENT_PORT may only be processed by - the dhcp module, no other UDP pcb may use the local UDP port DHCP_CLIENT_PORT */ - if (dest == DHCP_CLIENT_PORT) { - /* all packets for DHCP_CLIENT_PORT not coming from DHCP_SERVER_PORT are dropped! */ - if (src == DHCP_SERVER_PORT) { - if ((inp->dhcp != NULL) && (inp->dhcp->pcb != NULL)) { - /* accept the packe if - (- broadcast or directed to us) -> DHCP is link-layer-addressed, local ip is always ANY! - - inp->dhcp->pcb->remote == ANY or iphdr->src */ - if ((ip_addr_isany(&inp->dhcp->pcb->remote_ip) || - ip_addr_cmp(&(inp->dhcp->pcb->remote_ip), &(iphdr->src)))) { - pcb = inp->dhcp->pcb; - } - } - } - } else -#endif /* LWIP_DHCP */ - { - prev = NULL; - local_match = 0; - uncon_pcb = NULL; - /* Iterate through the UDP pcb list for a matching pcb. - * 'Perfect match' pcbs (connected to the remote port & ip address) are - * preferred. If no perfect match is found, the first unconnected pcb that - * matches the local port and ip address gets the datagram. */ - for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { - local_match = 0; - /* print the PCB local and remote address */ - LWIP_DEBUGF(UDP_DEBUG, - ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- " - "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", - ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), - ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); - - /* compare PCB local addr+port to UDP destination addr+port */ - if ((pcb->local_port == dest) && - ((!broadcast && ip_addr_isany(&pcb->local_ip)) || - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) || -#if LWIP_IGMP - ip_addr_ismulticast(&(iphdr->dest)) || -#endif /* LWIP_IGMP */ -#if IP_SOF_BROADCAST_RECV - (broadcast && (pcb->so_options & SOF_BROADCAST)))) { -#else /* IP_SOF_BROADCAST_RECV */ - (broadcast))) { -#endif /* IP_SOF_BROADCAST_RECV */ - local_match = 1; - if ((uncon_pcb == NULL) && - ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { - /* the first unconnected matching PCB */ - uncon_pcb = pcb; - } - } - /* compare PCB remote addr+port to UDP source addr+port */ - if ((local_match != 0) && - (pcb->remote_port == src) && - (ip_addr_isany(&pcb->remote_ip) || - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { - /* the first fully matching PCB */ - if (prev != NULL) { - /* move the pcb to the front of udp_pcbs so that is - found faster next time */ - prev->next = pcb->next; - pcb->next = udp_pcbs; - udp_pcbs = pcb; - } else { - UDP_STATS_INC(udp.cachehit); - } - break; - } - prev = pcb; - } - /* no fully matching pcb found? then look for an unconnected pcb */ - if (pcb == NULL) { - pcb = uncon_pcb; - } - } - - /* Check checksum if this is a match or if it was directed at us. */ - if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n")); -#if LWIP_UDPLITE - if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { - /* Do the UDP Lite checksum */ -#if CHECKSUM_CHECK_UDP - u16_t chklen = ntohs(udphdr->len); - if (chklen < sizeof(struct udp_hdr)) { - if (chklen == 0) { - /* For UDP-Lite, checksum length of 0 means checksum - over the complete packet (See RFC 3828 chap. 3.1) */ - chklen = p->tot_len; - } else { - /* At least the UDP-Lite header must be covered by the - checksum! (Again, see RFC 3828 chap. 3.1) */ - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - } - if (inet_chksum_pseudo_partial(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_UDPLITE, p->tot_len, chklen) != 0) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } -#endif /* CHECKSUM_CHECK_UDP */ - } else -#endif /* LWIP_UDPLITE */ - { -#if CHECKSUM_CHECK_UDP - if (udphdr->chksum != 0) { - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_UDP, p->tot_len) != 0) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("udp_input: UDP datagram discarded due to failing checksum\n")); - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - } -#endif /* CHECKSUM_CHECK_UDP */ - } - if(pbuf_header(p, -UDP_HLEN)) { - /* Can we cope with this failing? Just assert for now */ - LWIP_ASSERT("pbuf_header failed\n", 0); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - if (pcb != NULL) { - snmp_inc_udpindatagrams(); - /* callback */ - if (pcb->recv != NULL) { - /* now the recv function is responsible for freeing p */ - pcb->recv(pcb->recv_arg, pcb, p, &iphdr->src, src); - } else { - /* no recv function registered? then we have to free the pbuf! */ - pbuf_free(p); - goto end; - } - } else { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n")); - -#if LWIP_ICMP - /* No match was found, send ICMP destination port unreachable unless - destination address was broadcast/multicast. */ - if (!broadcast && - !ip_addr_ismulticast(&iphdr->dest)) { - /* move payload pointer back to ip header */ - pbuf_header(p, (IPH_HL(iphdr) * 4) + UDP_HLEN); - LWIP_ASSERT("p->payload == iphdr", (p->payload == iphdr)); - icmp_dest_unreach(p, ICMP_DUR_PORT); - } -#endif /* LWIP_ICMP */ - UDP_STATS_INC(udp.proterr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpnoports(); - pbuf_free(p); - } - } else { - pbuf_free(p); - } -end: - PERF_STOP("udp_input"); -} - -/** - * Send data using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param p chain of pbuf's to be sent. - * - * The datagram will be sent to the current remote_ip & remote_port - * stored in pcb. If the pcb is not bound to a port, it will - * automatically be bound to a random port. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_MEM. Out of memory. - * - ERR_RTE. Could not find route to destination address. - * - More errors could be returned by lower protocol layers. - * - * @see udp_disconnect() udp_sendto() - */ -err_t -udp_send(struct udp_pcb *pcb, struct pbuf *p) -{ - /* send to the packet using remote ip and port stored in the pcb */ - return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port); -} - -/** - * Send data to a specified address using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param p chain of pbuf's to be sent. - * @param dst_ip Destination IP address. - * @param dst_port Destination UDP port. - * - * dst_ip & dst_port are expected to be in the same byte order as in the pcb. - * - * If the PCB already has a remote address association, it will - * be restored after the data is sent. - * - * @return lwIP error code (@see udp_send for possible error codes) - * - * @see udp_disconnect() udp_send() - */ -err_t -udp_sendto(struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *dst_ip, u16_t dst_port) -{ - struct netif *netif; - - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n")); - - /* find the outgoing network interface for this packet */ -#if LWIP_IGMP - netif = ip_route((ip_addr_ismulticast(dst_ip))?(&(pcb->multicast_ip)):(dst_ip)); -#else - netif = ip_route(dst_ip); -#endif /* LWIP_IGMP */ - - /* no outgoing network interface could be found? */ - if (netif == NULL) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to 0x%"X32_F"\n", dst_ip->addr)); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } - return udp_sendto_if(pcb, p, dst_ip, dst_port, netif); -} - -/** - * Send data to a specified address using UDP. - * The netif used for sending can be specified. - * - * This function exists mainly for DHCP, to be able to send UDP packets - * on a netif that is still down. - * - * @param pcb UDP PCB used to send the data. - * @param p chain of pbuf's to be sent. - * @param dst_ip Destination IP address. - * @param dst_port Destination UDP port. - * @param netif the netif used for sending. - * - * dst_ip & dst_port are expected to be in the same byte order as in the pcb. - * - * @return lwIP error code (@see udp_send for possible error codes) - * - * @see udp_disconnect() udp_send() - */ -err_t -udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif) -{ - struct udp_hdr *udphdr; - struct ip_addr *src_ip; - err_t err; - struct pbuf *q; /* q will be sent down the stack */ - -#if IP_SOF_BROADCAST - /* broadcast filter? */ - if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(dst_ip, netif) ) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, - ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); - return ERR_VAL; - } -#endif /* IP_SOF_BROADCAST */ - - /* if the PCB is not yet bound to a port, bind it here */ - if (pcb->local_port == 0) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n")); - err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n")); - return err; - } - } - - /* not enough space to add an UDP header to first pbuf in given p chain? */ - if (pbuf_header(p, UDP_HLEN)) { - /* allocate header in a separate new pbuf */ - q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n")); - return ERR_MEM; - } - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - /* first pbuf q points to header pbuf */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - } else { - /* adding space for header within p succeeded */ - /* first pbuf q equals given pbuf */ - q = p; - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); - } - LWIP_ASSERT("check that first pbuf can hold struct udp_hdr", - (q->len >= sizeof(struct udp_hdr))); - /* q now represents the packet to be sent */ - udphdr = q->payload; - udphdr->src = htons(pcb->local_port); - udphdr->dest = htons(dst_port); - /* in UDP, 0 checksum means 'no checksum' */ - udphdr->chksum = 0x0000; - - /* PCB local address is IP_ANY_ADDR? */ - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = &(netif->ip_addr); - } else { - /* check if UDP PCB local IP address is correct - * this could be an old address if netif->ip_addr has changed */ - if (!ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { - /* local_ip doesn't match, drop the packet */ - if (q != p) { - /* free the header pbuf */ - pbuf_free(q); - q = NULL; - /* p is still referenced by the caller, and will live on */ - } - return ERR_VAL; - } - /* use UDP PCB local IP address as source address */ - src_ip = &(pcb->local_ip); - } - - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); - -#if LWIP_UDPLITE - /* UDP Lite protocol? */ - if (pcb->flags & UDP_FLAGS_UDPLITE) { - u16_t chklen, chklen_hdr; - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); - /* set UDP message length in UDP header */ - chklen_hdr = chklen = pcb->chksum_len_tx; - if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) { - if (chklen != 0) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen)); - } - /* For UDP-Lite, checksum length of 0 means checksum - over the complete packet. (See RFC 3828 chap. 3.1) - At least the UDP-Lite header must be covered by the - checksum, therefore, if chksum_len has an illegal - value, we generate the checksum over the complete - packet to be safe. */ - chklen_hdr = 0; - chklen = q->tot_len; - } - udphdr->len = htons(chklen_hdr); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - udphdr->chksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip, - IP_PROTO_UDPLITE, q->tot_len, chklen); - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) - udphdr->chksum = 0xffff; -#endif /* CHECKSUM_CHECK_UDP */ - /* output to IP */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = &(pcb->addr_hint); -#endif /* LWIP_NETIF_HWADDRHINT*/ - err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = NULL; -#endif /* LWIP_NETIF_HWADDRHINT*/ - } else -#endif /* LWIP_UDPLITE */ - { /* UDP */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); - udphdr->len = htons(q->tot_len); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { - udphdr->chksum = inet_chksum_pseudo(q, src_ip, dst_ip, IP_PROTO_UDP, q->tot_len); - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; - } -#endif /* CHECKSUM_CHECK_UDP */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); - /* output to IP */ -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = &(pcb->addr_hint); -#endif /* LWIP_NETIF_HWADDRHINT*/ - err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); -#if LWIP_NETIF_HWADDRHINT - netif->addr_hint = NULL; -#endif /* LWIP_NETIF_HWADDRHINT*/ - } - /* TODO: must this be increased even if error occured? */ - snmp_inc_udpoutdatagrams(); - - /* did we chain a separate header pbuf earlier? */ - if (q != p) { - /* free the header pbuf */ - pbuf_free(q); - q = NULL; - /* p is still referenced by the caller, and will live on */ - } - - UDP_STATS_INC(udp.xmit); - return err; -} - -/** - * Bind an UDP PCB. - * - * @param pcb UDP PCB to be bound with a local address ipaddr and port. - * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to - * bind to all local interfaces. - * @param port local UDP port to bind with. Use 0 to automatically bind - * to a random port between UDP_LOCAL_PORT_RANGE_START and - * UDP_LOCAL_PORT_RANGE_END. - * - * ipaddr & port are expected to be in the same byte order as in the pcb. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_USE. The specified ipaddr and port are already bound to by - * another UDP PCB. - * - * @see udp_disconnect() - */ -err_t -udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - u8_t rebind; - - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); - ip_addr_debug_print(UDP_DEBUG, ipaddr); - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); - - rebind = 0; - /* Check for double bind and rebind of the same pcb */ - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - /* is this UDP PCB already on active list? */ - if (pcb == ipcb) { - /* pcb may occur at most once in active list */ - LWIP_ASSERT("rebind == 0", rebind == 0); - /* pcb already in list, just rebind */ - rebind = 1; - } - - /* this code does not allow upper layer to share a UDP port for - listening to broadcast or multicast traffic (See SO_REUSE_ADDR and - SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR - combine with implementation of UDP PCB flags. Leon Woestenberg. */ -#ifdef LWIP_UDP_TODO - /* port matches that of PCB in list? */ - else - if ((ipcb->local_port == port) && - /* IP address matches, or one is IP_ADDR_ANY? */ - (ip_addr_isany(&(ipcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { - /* other PCB already binds to this local IP and port */ - LWIP_DEBUGF(UDP_DEBUG, - ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); - return ERR_USE; - } -#endif - } - - ip_addr_set(&pcb->local_ip, ipaddr); - - /* no port specified? */ - if (port == 0) { -#ifndef UDP_LOCAL_PORT_RANGE_START -#define UDP_LOCAL_PORT_RANGE_START 4096 -#define UDP_LOCAL_PORT_RANGE_END 0x7fff -#endif - port = UDP_LOCAL_PORT_RANGE_START; - ipcb = udp_pcbs; - while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { - if (ipcb->local_port == port) { - /* port is already used by another udp_pcb */ - port++; - /* restart scanning all udp pcbs */ - ipcb = udp_pcbs; - } else - /* go on with next udp pcb */ - ipcb = ipcb->next; - } - if (ipcb != NULL) { - /* no more ports available in local range */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); - return ERR_USE; - } - } - pcb->local_port = port; - snmp_insert_udpidx_tree(pcb); - /* pcb not active yet? */ - if (rebind == 0) { - /* place the PCB on the active list if not already there */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - } - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", - (u16_t)((ntohl(pcb->local_ip.addr) >> 24) & 0xff), - (u16_t)((ntohl(pcb->local_ip.addr) >> 16) & 0xff), - (u16_t)((ntohl(pcb->local_ip.addr) >> 8) & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); - return ERR_OK; -} -/** - * Connect an UDP PCB. - * - * This will associate the UDP PCB with the remote address. - * - * @param pcb UDP PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * @param port remote UDP port to connect with. - * - * @return lwIP error code - * - * ipaddr & port are expected to be in the same byte order as in the pcb. - * - * The udp pcb is bound to a random local port if not already bound. - * - * @see udp_disconnect() - */ -err_t -udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - - if (pcb->local_port == 0) { - err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) - return err; - } - - ip_addr_set(&pcb->remote_ip, ipaddr); - pcb->remote_port = port; - pcb->flags |= UDP_FLAGS_CONNECTED; -/** TODO: this functionality belongs in upper layers */ -#ifdef LWIP_UDP_TODO - /* Nail down local IP for netconn_addr()/getsockname() */ - if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { - struct netif *netif; - - if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } - /** TODO: this will bind the udp pcb locally, to the interface which - is used to route output packets to the remote address. However, we - might want to accept incoming packets on any interface! */ - pcb->local_ip = netif->ip_addr; - } else if (ip_addr_isany(&pcb->remote_ip)) { - pcb->local_ip.addr = 0; - } -#endif - LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, - ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", - (u16_t)((ntohl(pcb->remote_ip.addr) >> 24) & 0xff), - (u16_t)((ntohl(pcb->remote_ip.addr) >> 16) & 0xff), - (u16_t)((ntohl(pcb->remote_ip.addr) >> 8) & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); - - /* Insert UDP PCB into the list of active UDP PCBs. */ - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - if (pcb == ipcb) { - /* already on the list, just return */ - return ERR_OK; - } - } - /* PCB not yet on the list, add PCB now */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - return ERR_OK; -} - -/** - * Disconnect a UDP PCB - * - * @param pcb the udp pcb to disconnect. - */ -void -udp_disconnect(struct udp_pcb *pcb) -{ - /* reset remote address association */ - ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY); - pcb->remote_port = 0; - /* mark PCB as unconnected */ - pcb->flags &= ~UDP_FLAGS_CONNECTED; -} - -/** - * Set a receive callback for a UDP PCB - * - * This callback will be called when receiving a datagram for the pcb. - * - * @param pcb the pcb for wich to set the recv callback - * @param recv function pointer of the callback function - * @param recv_arg additional argument to pass to the callback function - */ -void -udp_recv(struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p, - struct ip_addr *addr, u16_t port), - void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} - -/** - * Remove an UDP PCB. - * - * @param pcb UDP PCB to be removed. The PCB is removed from the list of - * UDP PCB's and the data structure is freed from memory. - * - * @see udp_new() - */ -void -udp_remove(struct udp_pcb *pcb) -{ - struct udp_pcb *pcb2; - - snmp_delete_udpidx_tree(pcb); - /* pcb to be removed is first in list? */ - if (udp_pcbs == pcb) { - /* make list start at 2nd pcb */ - udp_pcbs = udp_pcbs->next; - /* pcb not 1st in list */ - } else - for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in udp_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - } - } - memp_free(MEMP_UDP_PCB, pcb); -} - -/** - * Create a UDP PCB. - * - * @return The UDP PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @see udp_remove() - */ -struct udp_pcb * -udp_new(void) -{ - struct udp_pcb *pcb; - pcb = memp_malloc(MEMP_UDP_PCB); - /* could allocate UDP PCB? */ - if (pcb != NULL) { - /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 - * which means checksum is generated over the whole datagram per default - * (recommended as default by RFC 3828). */ - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct udp_pcb)); - pcb->ttl = UDP_TTL; - } - return pcb; -} - -#if UDP_DEBUG -/** - * Print UDP header information for debug purposes. - * - * @param udphdr pointer to the udp header in memory. - */ -void -udp_debug_print(struct udp_hdr *udphdr) -{ - LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - ntohs(udphdr->src), ntohs(udphdr->dest))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", - ntohs(udphdr->len), ntohs(udphdr->chksum))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* UDP_DEBUG */ - -#endif /* LWIP_UDP */ diff --git a/components/net/lwip-1.3.2/src/include/ipv4/lwip/autoip.h b/components/net/lwip-1.3.2/src/include/ipv4/lwip/autoip.h deleted file mode 100644 index f2621658db..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv4/lwip/autoip.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file - * - * AutoIP Automatic LinkLocal IP Configuration - */ - -/* - * - * Copyright (c) 2007 Dominik Spies - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Dominik Spies - * - * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform - * with RFC 3927. - * - * - * Please coordinate changes and requests with Dominik Spies - * - */ - -#ifndef __LWIP_AUTOIP_H__ -#define __LWIP_AUTOIP_H__ - -#include "lwip/opt.h" - -#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/netif.h" -#include "lwip/udp.h" -#include "netif/etharp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* AutoIP Timing */ -#define AUTOIP_TMR_INTERVAL 100 -#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL) - -/* RFC 3927 Constants */ -#define PROBE_WAIT 1 /* second (initial random delay) */ -#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ -#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ -#define PROBE_NUM 3 /* (number of probe packets) */ -#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ -#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ -#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ -#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ -#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ -#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ - -/* AutoIP client states */ -#define AUTOIP_STATE_OFF 0 -#define AUTOIP_STATE_PROBING 1 -#define AUTOIP_STATE_ANNOUNCING 2 -#define AUTOIP_STATE_BOUND 3 - -struct autoip -{ - struct ip_addr llipaddr; /* the currently selected, probed, announced or used LL IP-Address */ - u8_t state; /* current AutoIP state machine state */ - u8_t sent_num; /* sent number of probes or announces, dependent on state */ - u16_t ttw; /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */ - u8_t lastconflict; /* ticks until a conflict can be solved by defending */ - u8_t tried_llipaddr; /* total number of probed/used Link Local IP-Addresses */ -}; - - -/** Init srand, has to be called before entering mainloop */ -void autoip_init(void); - -/** Start AutoIP client */ -err_t autoip_start(struct netif *netif); - -/** Stop AutoIP client */ -err_t autoip_stop(struct netif *netif); - -/** Handles every incoming ARP Packet, called by etharp_arp_input */ -void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr); - -/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */ -void autoip_tmr(void); - -/** Handle a possible change in the network configuration */ -void autoip_network_changed(struct netif *netif); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_AUTOIP */ - -#endif /* __LWIP_AUTOIP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/ipv4/lwip/igmp.h b/components/net/lwip-1.3.2/src/include/ipv4/lwip/igmp.h deleted file mode 100644 index 59c933f35c..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv4/lwip/igmp.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2002 CITEL Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. -*/ - -#ifndef __LWIP_IGMP_H__ -#define __LWIP_IGMP_H__ - -#include "lwip/opt.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/pbuf.h" - -#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * IGMP constants - */ -#define IP_PROTO_IGMP 2 -#define IGMP_TTL 1 -#define IGMP_MINLEN 8 -#define ROUTER_ALERT 0x9404 -#define ROUTER_ALERTLEN 4 - -/* - * IGMP message types, including version number. - */ -#define IGMP_MEMB_QUERY 0x11 /* Membership query */ -#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */ -#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */ -#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */ - -/* IGMP timer */ -#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ -#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) -#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) - -/* MAC Filter Actions */ -#define IGMP_DEL_MAC_FILTER 0 -#define IGMP_ADD_MAC_FILTER 1 - -/* Group membership states */ -#define IGMP_GROUP_NON_MEMBER 0 -#define IGMP_GROUP_DELAYING_MEMBER 1 -#define IGMP_GROUP_IDLE_MEMBER 2 - -/* - * IGMP packet format. - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct igmp_msg { - PACK_STRUCT_FIELD(u8_t igmp_msgtype); - PACK_STRUCT_FIELD(u8_t igmp_maxresp); - PACK_STRUCT_FIELD(u16_t igmp_checksum); - PACK_STRUCT_FIELD(struct ip_addr igmp_group_address); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* - * now a group structure - there is - * a list of groups for each interface - * these should really be linked from the interface, but - * if we keep them separate we will not affect the lwip original code - * too much - * - * There will be a group for the all systems group address but this - * will not run the state machine as it is used to kick off reports - * from all the other groups - */ - -struct igmp_group { - struct igmp_group *next; - struct netif *interface; - struct ip_addr group_address; - u8_t last_reporter_flag; /* signifies we were the last person to report */ - u8_t group_state; - u16_t timer; - u8_t use; /* counter of simultaneous uses */ -}; - - -/* Prototypes */ -void igmp_init(void); - -err_t igmp_start( struct netif *netif); - -err_t igmp_stop( struct netif *netif); - -void igmp_report_groups( struct netif *netif); - -struct igmp_group *igmp_lookfor_group( struct netif *ifp, struct ip_addr *addr); - -struct igmp_group *igmp_lookup_group( struct netif *ifp, struct ip_addr *addr); - -err_t igmp_remove_group( struct igmp_group *group); - -void igmp_input( struct pbuf *p, struct netif *inp, struct ip_addr *dest); - -err_t igmp_joingroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr); - -err_t igmp_leavegroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr); - -void igmp_tmr(void); - -void igmp_timeout( struct igmp_group *group); - -void igmp_start_timer( struct igmp_group *group, u8_t max_time); - -void igmp_stop_timer( struct igmp_group *group); - -void igmp_delaying_member( struct igmp_group *group, u8_t maxresp); - -err_t igmp_ip_output_if( struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, u8_t ttl, u8_t proto, struct netif *netif); - -void igmp_send( struct igmp_group *group, u8_t type); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_IGMP */ - -#endif /* __LWIP_IGMP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/ipv4/lwip/inet.h b/components/net/lwip-1.3.2/src/include/ipv4/lwip/inet.h deleted file mode 100644 index 6f30d0d12a..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv4/lwip/inet.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_INET_H__ -#define __LWIP_INET_H__ - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* For compatibility with BSD code */ -struct in_addr { - u32_t s_addr; -}; - -#define INADDR_NONE ((u32_t)0xffffffffUL) /* 255.255.255.255 */ -#define INADDR_LOOPBACK ((u32_t)0x7f000001UL) /* 127.0.0.1 */ -#define INADDR_ANY ((u32_t)0x00000000UL) /* 0.0.0.0 */ -#define INADDR_BROADCAST ((u32_t)0xffffffffUL) /* 255.255.255.255 */ - -u32_t inet_addr(const char *cp); -int inet_aton(const char *cp, struct in_addr *addr); -char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ - -#ifdef htons -#undef htons -#endif /* htons */ -#ifdef htonl -#undef htonl -#endif /* htonl */ -#ifdef ntohs -#undef ntohs -#endif /* ntohs */ -#ifdef ntohl -#undef ntohl -#endif /* ntohl */ - -#ifndef LWIP_PLATFORM_BYTESWAP -#define LWIP_PLATFORM_BYTESWAP 0 -#endif - -#if BYTE_ORDER == BIG_ENDIAN -#define htons(x) (x) -#define ntohs(x) (x) -#define htonl(x) (x) -#define ntohl(x) (x) -#else /* BYTE_ORDER != BIG_ENDIAN */ -#ifdef LWIP_PREFIX_BYTEORDER_FUNCS -/* workaround for naming collisions on some platforms */ -#define htons lwip_htons -#define ntohs lwip_ntohs -#define htonl lwip_htonl -#define ntohl lwip_ntohl -#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */ -#if LWIP_PLATFORM_BYTESWAP -#define htons(x) LWIP_PLATFORM_HTONS(x) -#define ntohs(x) LWIP_PLATFORM_HTONS(x) -#define htonl(x) LWIP_PLATFORM_HTONL(x) -#define ntohl(x) LWIP_PLATFORM_HTONL(x) -#else /* LWIP_PLATFORM_BYTESWAP */ -u16_t htons(u16_t x); -u16_t ntohs(u16_t x); -u32_t htonl(u32_t x); -u32_t ntohl(u32_t x); -#endif /* LWIP_PLATFORM_BYTESWAP */ - -#endif /* BYTE_ORDER == BIG_ENDIAN */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_INET_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/ipv4/lwip/ip.h b/components/net/lwip-1.3.2/src/include/ipv4/lwip/ip.h deleted file mode 100644 index fd84f3043c..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv4/lwip/ip.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_H__ -#define __LWIP_IP_H__ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/err.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Currently, the function ip_output_if_opt() is only used with IGMP */ -#define IP_OPTIONS_SEND LWIP_IGMP - -#define IP_HLEN 20 - -#define IP_PROTO_ICMP 1 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 136 -#define IP_PROTO_TCP 6 - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#ifdef IP_HDRINCL -#undef IP_HDRINCL -#endif /* IP_HDRINCL */ -#define IP_HDRINCL NULL - -#if LWIP_NETIF_HWADDRHINT -#define IP_PCB_ADDRHINT ;u8_t addr_hint -#else -#define IP_PCB_ADDRHINT -#endif /* LWIP_NETIF_HWADDRHINT */ - -/* This is the common part of all PCB types. It needs to be at the - beginning of a PCB type definition. It is located here so that - changes to this common part are made in one location instead of - having to change all PCB structs. */ -#define IP_PCB \ - /* ip addresses in network byte order */ \ - struct ip_addr local_ip; \ - struct ip_addr remote_ip; \ - /* Socket options */ \ - u16_t so_options; \ - /* Type Of Service */ \ - u8_t tos; \ - /* Time To Live */ \ - u8_t ttl \ - /* link layer address resolution hint */ \ - IP_PCB_ADDRHINT - -struct ip_pcb { -/* Common members of all PCB types */ - IP_PCB; -}; - -/* - * Option flags per-socket. These are the same like SO_XXX. - */ -#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ -#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ -#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ -#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ -#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ -#define SOF_BROADCAST (u16_t)0x0020U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ -#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ -#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ -#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ -#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ - - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_hdr { - /* version / header length / type of service */ - PACK_STRUCT_FIELD(u16_t _v_hl_tos); - /* total length */ - PACK_STRUCT_FIELD(u16_t _len); - /* identification */ - PACK_STRUCT_FIELD(u16_t _id); - /* fragment offset field */ - PACK_STRUCT_FIELD(u16_t _offset); -#define IP_RF 0x8000 /* reserved fragment flag */ -#define IP_DF 0x4000 /* dont fragment flag */ -#define IP_MF 0x2000 /* more fragments flag */ -#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ - /* time to live / protocol*/ - PACK_STRUCT_FIELD(u16_t _ttl_proto); - /* checksum */ - PACK_STRUCT_FIELD(u16_t _chksum); - /* source and destination IP addresses */ - PACK_STRUCT_FIELD(struct ip_addr src); - PACK_STRUCT_FIELD(struct ip_addr dest); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) -#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) -#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) -#define IPH_LEN(hdr) ((hdr)->_len) -#define IPH_ID(hdr) ((hdr)->_id) -#define IPH_OFFSET(hdr) ((hdr)->_offset) -#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) -#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) -#define IPH_CHKSUM(hdr) ((hdr)->_chksum) - -#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) -#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) -#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) -#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) -#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8))) -#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) -#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) - -/** The interface that provided the packet for the current callback invocation. */ -extern struct netif *current_netif; -/** Header of the input packet currently being processed. */ -extern const struct ip_hdr *current_header; - -#define ip_init() /* Compatibility define, not init needed. */ -struct netif *ip_route(struct ip_addr *dest); -err_t ip_input(struct pbuf *p, struct netif *inp); -err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto); -err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, - struct netif *netif); -#if LWIP_NETIF_HWADDRHINT -err_t ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint); -#endif /* LWIP_NETIF_HWADDRHINT */ -#if IP_OPTIONS_SEND -err_t ip_output_if_opt(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, - u16_t optlen); -#endif /* IP_OPTIONS_SEND */ -/** Get the interface that received the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip_current_netif() (current_netif) -/** Get the IP header of the current packet. - * This function must only be called from a receive callback (udp_recv, - * raw_recv, tcp_accept). It will return NULL otherwise. */ -#define ip_current_header() (current_header) -#if IP_DEBUG -void ip_debug_print(struct pbuf *p); -#else -#define ip_debug_print(p) -#endif /* IP_DEBUG */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_IP_H__ */ - - diff --git a/components/net/lwip-1.3.2/src/include/ipv4/lwip/ip_addr.h b/components/net/lwip-1.3.2/src/include/ipv4/lwip/ip_addr.h deleted file mode 100644 index 298e65768c..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv4/lwip/ip_addr.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_ADDR_H__ -#define __LWIP_IP_ADDR_H__ - -#include "lwip/opt.h" - -#include "lwip/inet.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_addr { - PACK_STRUCT_FIELD(u32_t addr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* - * struct ipaddr2 is used in the definition of the ARP packet format in - * order to support compilers that don't have structure packing. - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_addr2 { - PACK_STRUCT_FIELD(u16_t addrw[2]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -struct netif; - -extern const struct ip_addr ip_addr_any; -extern const struct ip_addr ip_addr_broadcast; - -/** IP_ADDR_ can be used as a fixed IP address - * for the wildcard and the broadcast address - */ -#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) -#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) - -/* Definitions of the bits in an Internet address integer. - - On subnets, host and network parts are found according to - the subnet mask, not these masks. */ - -#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) -#define IN_CLASSA_NET 0xff000000 -#define IN_CLASSA_NSHIFT 24 -#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) -#define IN_CLASSA_MAX 128 - -#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) -#define IN_CLASSB_NET 0xffff0000 -#define IN_CLASSB_NSHIFT 16 -#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) -#define IN_CLASSB_MAX 65536 - -#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) -#define IN_CLASSC_NET 0xffffff00 -#define IN_CLASSC_NSHIFT 8 -#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) - -#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) -#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ -#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ -#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ -#define IN_MULTICAST(a) IN_CLASSD(a) - -#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) -#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) - -#define IN_LOOPBACKNET 127 /* official! */ - -#define IP4_ADDR(ipaddr, a,b,c,d) \ - (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \ - ((u32_t)((b) & 0xff) << 16) | \ - ((u32_t)((c) & 0xff) << 8) | \ - (u32_t)((d) & 0xff)) - -#define ip_addr_set(dest, src) (dest)->addr = \ - ((src) == NULL? 0:\ - (src)->addr) -/** - * Determine if two address are on the same network. - * - * @arg addr1 IP address 1 - * @arg addr2 IP address 2 - * @arg mask network identifier mask - * @return !0 if the network identifiers of both address match - */ -#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ - (mask)->addr) == \ - ((addr2)->addr & \ - (mask)->addr)) -#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) - -#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) - -u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); - -#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000UL)) == ntohl(0xe0000000UL)) - -#define ip_addr_islinklocal(addr1) (((addr1)->addr & ntohl(0xffff0000UL)) == ntohl(0xa9fe0000UL)) - -#define ip_addr_debug_print(debug, ipaddr) \ - LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ - ipaddr != NULL ? \ - (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \ - ipaddr != NULL ? \ - (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \ - ipaddr != NULL ? \ - (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \ - ipaddr != NULL ? \ - (u16_t)ntohl((ipaddr)->addr) & 0xff : 0)) - -/* These are cast to u16_t, with the intent that they are often arguments - * to printf using the U16_F format from cc.h. */ -#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) -#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) -#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) -#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) - -/** - * Same as inet_ntoa() but takes a struct ip_addr* - */ -#define ip_ntoa(addr) ((addr != NULL) ? inet_ntoa(*((struct in_addr*)(addr))) : "NULL") - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/ipv6/lwip/icmp.h b/components/net/lwip-1.3.2/src/include/ipv6/lwip/icmp.h deleted file mode 100644 index 87e9ffd964..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv6/lwip/icmp.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ICMP_H__ -#define __LWIP_ICMP_H__ - -#include "lwip/opt.h" - -#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ICMP6_DUR 1 -#define ICMP6_TE 3 -#define ICMP6_ECHO 128 /* echo */ -#define ICMP6_ER 129 /* echo reply */ - - -enum icmp_dur_type { - ICMP_DUR_NET = 0, /* net unreachable */ - ICMP_DUR_HOST = 1, /* host unreachable */ - ICMP_DUR_PROTO = 2, /* protocol unreachable */ - ICMP_DUR_PORT = 3, /* port unreachable */ - ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ - ICMP_DUR_SR = 5 /* source route failed */ -}; - -enum icmp_te_type { - ICMP_TE_TTL = 0, /* time to live exceeded in transit */ - ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ -}; - -void icmp_input(struct pbuf *p, struct netif *inp); - -void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); -void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); - -struct icmp_echo_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u16_t id; - u16_t seqno; -}; - -struct icmp_dur_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u32_t unused; -}; - -struct icmp_te_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u32_t unused; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_ICMP */ - -#endif /* __LWIP_ICMP_H__ */ - diff --git a/components/net/lwip-1.3.2/src/include/ipv6/lwip/ip.h b/components/net/lwip-1.3.2/src/include/ipv6/lwip/ip.h deleted file mode 100644 index a01cfc65b3..0000000000 --- a/components/net/lwip-1.3.2/src/include/ipv6/lwip/ip.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_H__ -#define __LWIP_IP_H__ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define IP_HLEN 40 - -#define IP_PROTO_ICMP 58 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 136 -#define IP_PROTO_TCP 6 - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#ifdef IP_HDRINCL -#undef IP_HDRINCL -#endif /* IP_HDRINCL */ -#define IP_HDRINCL NULL - -#if LWIP_NETIF_HWADDRHINT -#define IP_PCB_ADDRHINT ;u8_t addr_hint -#else -#define IP_PCB_ADDRHINT -#endif /* LWIP_NETIF_HWADDRHINT */ - -/* This is the common part of all PCB types. It needs to be at the - beginning of a PCB type definition. It is located here so that - changes to this common part are made in one location instead of - having to change all PCB structs. */ -#define IP_PCB struct ip_addr local_ip; \ - struct ip_addr remote_ip; \ - /* Socket options */ \ - u16_t so_options; \ - /* Type Of Service */ \ - u8_t tos; \ - /* Time To Live */ \ - u8_t ttl; \ - /* link layer address resolution hint */ \ - IP_PCB_ADDRHINT - - -/* The IPv6 header. */ -struct ip_hdr { -#if BYTE_ORDER == LITTLE_ENDIAN - u8_t tclass1:4, v:4; - u8_t flow1:4, tclass2:4; -#else - u8_t v:4, tclass1:4; - u8_t tclass2:8, flow1:4; -#endif - u16_t flow2; - u16_t len; /* payload length */ - u8_t nexthdr; /* next header */ - u8_t hoplim; /* hop limit (TTL) */ - struct ip_addr src, dest; /* source and destination IP addresses */ -}; - -#define IPH_PROTO(hdr) (iphdr->nexthdr) - -void ip_init(void); - -#include "lwip/netif.h" - -struct netif *ip_route(struct ip_addr *dest); - -void ip_input(struct pbuf *p, struct netif *inp); - -/* source and destination addresses in network byte order, please */ -err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto); - -err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto, - struct netif *netif); - -#define ip_current_netif() NULL -#define ip_current_header() NULL - -#if IP_DEBUG -void ip_debug_print(struct pbuf *p); -#endif /* IP_DEBUG */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_IP_H__ */ - - diff --git a/components/net/lwip-1.3.2/src/include/lwip/api.h b/components/net/lwip-1.3.2/src/include/lwip/api.h deleted file mode 100644 index f6b1f74343..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/api.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_API_H__ -#define __LWIP_API_H__ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include /* for size_t */ - -#include "lwip/netbuf.h" -#include "lwip/sys.h" -#include "lwip/ip_addr.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Throughout this file, IP addresses and port numbers are expected to be in - * the same byte order as in the corresponding pcb. - */ - -/* Flags for netconn_write */ -#define NETCONN_NOFLAG 0x00 -#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ -#define NETCONN_COPY 0x01 -#define NETCONN_MORE 0x02 - -/* Helpers to process several netconn_types by the same code */ -#define NETCONNTYPE_GROUP(t) (t&0xF0) -#define NETCONNTYPE_DATAGRAM(t) (t&0xE0) - -enum netconn_type { - NETCONN_INVALID = 0, - /* NETCONN_TCP Group */ - NETCONN_TCP = 0x10, - /* NETCONN_UDP Group */ - NETCONN_UDP = 0x20, - NETCONN_UDPLITE = 0x21, - NETCONN_UDPNOCHKSUM= 0x22, - /* NETCONN_RAW Group */ - NETCONN_RAW = 0x40 -}; - -enum netconn_state { - NETCONN_NONE, - NETCONN_WRITE, - NETCONN_LISTEN, - NETCONN_CONNECT, - NETCONN_CLOSE -}; - -enum netconn_evt { - NETCONN_EVT_RCVPLUS, - NETCONN_EVT_RCVMINUS, - NETCONN_EVT_SENDPLUS, - NETCONN_EVT_SENDMINUS -}; - -#if LWIP_IGMP -enum netconn_igmp { - NETCONN_JOIN, - NETCONN_LEAVE -}; -#endif /* LWIP_IGMP */ - -/* forward-declare some structs to avoid to include their headers */ -struct ip_pcb; -struct tcp_pcb; -struct udp_pcb; -struct raw_pcb; -struct netconn; - -/** A callback prototype to inform about events for a netconn */ -typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); - -/** A netconn descriptor */ -struct netconn { - /** type of the netconn (TCP, UDP or RAW) */ - enum netconn_type type; - /** current state of the netconn */ - enum netconn_state state; - /** the lwIP internal protocol control block */ - union { - struct ip_pcb *ip; - struct tcp_pcb *tcp; - struct udp_pcb *udp; - struct raw_pcb *raw; - } pcb; - /** the last error this netconn had */ - err_t err; - /** sem that is used to synchroneously execute functions in the core context */ - sys_sem_t op_completed; - /** mbox where received packets are stored until they are fetched - by the netconn application thread (can grow quite big) */ - sys_mbox_t recvmbox; - /** mbox where new connections are stored until processed - by the application thread */ - sys_mbox_t acceptmbox; - /** only used for socket layer */ - int socket; -#if LWIP_SO_RCVTIMEO - /** timeout to wait for new data to be received - (or connections to arrive for listening netconns) */ - int recv_timeout; -#endif /* LWIP_SO_RCVTIMEO */ -#if LWIP_SO_RCVBUF - /** maximum amount of bytes queued in recvmbox */ - int recv_bufsize; -#endif /* LWIP_SO_RCVBUF */ - s16_t recv_avail; -#if LWIP_TCP - /** TCP: when data passed to netconn_write doesn't fit into the send buffer, - this temporarily stores the message. */ - struct api_msg_msg *write_msg; - /** TCP: when data passed to netconn_write doesn't fit into the send buffer, - this temporarily stores how much is already sent. */ - size_t write_offset; -#if LWIP_TCPIP_CORE_LOCKING - /** TCP: when data passed to netconn_write doesn't fit into the send buffer, - this temporarily stores whether to wake up the original application task - if data couldn't be sent in the first try. */ - u8_t write_delayed; -#endif /* LWIP_TCPIP_CORE_LOCKING */ -#endif /* LWIP_TCP */ - /** A callback function that is informed about events for this netconn */ - netconn_callback callback; -}; - -/* Register an Network connection event */ -#define API_EVENT(c,e,l) if (c->callback) { \ - (*c->callback)(c, e, l); \ - } - -/* Network connection functions: */ -#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) -#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) -struct -netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, - netconn_callback callback); -err_t netconn_delete (struct netconn *conn); -/** Get the type of a netconn (as enum netconn_type). */ -#define netconn_type(conn) (conn->type) - -err_t netconn_getaddr (struct netconn *conn, - struct ip_addr *addr, - u16_t *port, - u8_t local); -#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) -#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) - -err_t netconn_bind (struct netconn *conn, - struct ip_addr *addr, - u16_t port); -err_t netconn_connect (struct netconn *conn, - struct ip_addr *addr, - u16_t port); -err_t netconn_disconnect (struct netconn *conn); -err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); -#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) -struct netconn * netconn_accept (struct netconn *conn); -struct netbuf * netconn_recv (struct netconn *conn); -err_t netconn_sendto (struct netconn *conn, - struct netbuf *buf, struct ip_addr *addr, u16_t port); -err_t netconn_send (struct netconn *conn, - struct netbuf *buf); -err_t netconn_write (struct netconn *conn, - const void *dataptr, size_t size, - u8_t apiflags); -err_t netconn_close (struct netconn *conn); - -#if LWIP_IGMP -err_t netconn_join_leave_group (struct netconn *conn, - struct ip_addr *multiaddr, - struct ip_addr *interface, - enum netconn_igmp join_or_leave); -#endif /* LWIP_IGMP */ -#if LWIP_DNS -err_t netconn_gethostbyname(const char *name, struct ip_addr *addr); -#endif /* LWIP_DNS */ - -#define netconn_err(conn) ((conn)->err) -#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETCONN */ - -#endif /* __LWIP_API_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/api_msg.h b/components/net/lwip-1.3.2/src/include/lwip/api_msg.h deleted file mode 100644 index d3b0456838..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/api_msg.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_API_MSG_H__ -#define __LWIP_API_MSG_H__ - -#include "lwip/opt.h" - -#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ - -#include /* for size_t */ - -#include "lwip/ip_addr.h" -#include "lwip/err.h" -#include "lwip/sys.h" -#include "lwip/igmp.h" -#include "lwip/api.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* IP addresses and port numbers are expected to be in - * the same byte order as in the corresponding pcb. - */ -/** This struct includes everything that is necessary to execute a function - for a netconn in another thread context (mainly used to process netconns - in the tcpip_thread context to be thread safe). */ -struct api_msg_msg { - /** The netconn which to process - always needed: it includes the semaphore - which is used to block the application thread until the function finished. */ - struct netconn *conn; - /** Depending on the executed function, one of these union members is used */ - union { - /** used for do_send */ - struct netbuf *b; - /** used for do_newconn */ - struct { - u8_t proto; - } n; - /** used for do_bind and do_connect */ - struct { - struct ip_addr *ipaddr; - u16_t port; - } bc; - /** used for do_getaddr */ - struct { - struct ip_addr *ipaddr; - u16_t *port; - u8_t local; - } ad; - /** used for do_write */ - struct { - const void *dataptr; - size_t len; - u8_t apiflags; - } w; - /** used for do_recv */ - struct { - u16_t len; - } r; -#if LWIP_IGMP - /** used for do_join_leave_group */ - struct { - struct ip_addr *multiaddr; - struct ip_addr *interface; - enum netconn_igmp join_or_leave; - } jl; -#endif /* LWIP_IGMP */ -#if TCP_LISTEN_BACKLOG - struct { - u8_t backlog; - } lb; -#endif /* TCP_LISTEN_BACKLOG */ - } msg; -}; - -/** This struct contains a function to execute in another thread context and - a struct api_msg_msg that serves as an argument for this function. - This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */ -struct api_msg { - /** function to execute in tcpip_thread context */ - void (* function)(struct api_msg_msg *msg); - /** arguments for this function */ - struct api_msg_msg msg; -}; - -#if LWIP_DNS -/** As do_gethostbyname requires more arguments but doesn't require a netconn, - it has its own struct (to avoid struct api_msg getting bigger than necessary). - do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg - (see netconn_gethostbyname). */ -struct dns_api_msg { - /** Hostname to query or dotted IP address string */ - const char *name; - /** Rhe resolved address is stored here */ - struct ip_addr *addr; - /** This semaphore is posted when the name is resolved, the application thread - should wait on it. */ - sys_sem_t sem; - /** Errors are given back here */ - err_t *err; -}; -#endif /* LWIP_DNS */ - -void do_newconn ( struct api_msg_msg *msg); -void do_delconn ( struct api_msg_msg *msg); -void do_bind ( struct api_msg_msg *msg); -void do_connect ( struct api_msg_msg *msg); -void do_disconnect ( struct api_msg_msg *msg); -void do_listen ( struct api_msg_msg *msg); -void do_send ( struct api_msg_msg *msg); -void do_recv ( struct api_msg_msg *msg); -void do_write ( struct api_msg_msg *msg); -void do_getaddr ( struct api_msg_msg *msg); -void do_close ( struct api_msg_msg *msg); -#if LWIP_IGMP -void do_join_leave_group( struct api_msg_msg *msg); -#endif /* LWIP_IGMP */ - -#if LWIP_DNS -void do_gethostbyname(void *arg); -#endif /* LWIP_DNS */ - -struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); -void netconn_free(struct netconn *conn); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETCONN */ - -#endif /* __LWIP_API_MSG_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/arch.h b/components/net/lwip-1.3.2/src/include/lwip/arch.h deleted file mode 100644 index 3a5a0e4f20..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/arch.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ARCH_H__ -#define __LWIP_ARCH_H__ - -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 1234 -#endif - -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 4321 -#endif - -#include "arch/cc.h" - -/** Temporary: define format string for size_t if not defined in cc.h */ -#ifndef SZT_F -#define SZT_F U32_F -#endif /* SZT_F */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef PACK_STRUCT_BEGIN -#define PACK_STRUCT_BEGIN -#endif /* PACK_STRUCT_BEGIN */ - -#ifndef PACK_STRUCT_END -#define PACK_STRUCT_END -#endif /* PACK_STRUCT_END */ - -#ifndef PACK_STRUCT_FIELD -#define PACK_STRUCT_FIELD(x) x -#endif /* PACK_STRUCT_FIELD */ - - -#ifndef LWIP_UNUSED_ARG -#define LWIP_UNUSED_ARG(x) (void)x -#endif /* LWIP_UNUSED_ARG */ - - -#ifdef LWIP_PROVIDE_ERRNO - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ - -#define EDEADLOCK EDEADLK - -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - - -#define ENSROK 0 /* DNS server returned answer with no data */ -#define ENSRNODATA 160 /* DNS server returned answer with no data */ -#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ -#define ENSRSERVFAIL 162 /* DNS server returned general failure */ -#define ENSRNOTFOUND 163 /* Domain name not found */ -#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ -#define ENSRREFUSED 165 /* DNS server refused query */ -#define ENSRBADQUERY 166 /* Misformatted DNS query */ -#define ENSRBADNAME 167 /* Misformatted domain name */ -#define ENSRBADFAMILY 168 /* Unsupported address family */ -#define ENSRBADRESP 169 /* Misformatted DNS reply */ -#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ -#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ -#define ENSROF 172 /* End of file */ -#define ENSRFILE 173 /* Error reading file */ -#define ENSRNOMEM 174 /* Out of memory */ -#define ENSRDESTRUCTION 175 /* Application terminated lookup */ -#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ -#define ENSRCNAMELOOP 177 /* Domain name is too long */ - -#ifndef errno -extern int errno; -#endif - -#endif /* LWIP_PROVIDE_ERRNO */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_ARCH_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/dhcp.h b/components/net/lwip-1.3.2/src/include/lwip/dhcp.h deleted file mode 100644 index db37e88493..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/dhcp.h +++ /dev/null @@ -1,246 +0,0 @@ -/** @file - */ - -#ifndef __LWIP_DHCP_H__ -#define __LWIP_DHCP_H__ - -#include "lwip/opt.h" - -#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/netif.h" -#include "lwip/udp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** period (in seconds) of the application calling dhcp_coarse_tmr() */ -#define DHCP_COARSE_TIMER_SECS 60 -/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ -#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) -/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ -#define DHCP_FINE_TIMER_MSECS 500 - -struct dhcp -{ - /** transaction identifier of last sent request */ - u32_t xid; - /** our connection to the DHCP server */ - struct udp_pcb *pcb; - /** incoming msg */ - struct dhcp_msg *msg_in; - /** incoming msg options */ - void *options_in; - /** ingoing msg options length */ - u16_t options_in_len; - /** current DHCP state machine state */ - u8_t state; - /** retries of current request */ - u8_t tries; - - struct pbuf *p_out; /* pbuf of outcoming msg */ - struct dhcp_msg *msg_out; /* outgoing msg */ - u16_t options_out_len; /* outgoing msg options length */ - u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ - u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ - u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ - struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ - struct ip_addr offered_ip_addr; - struct ip_addr offered_sn_mask; - struct ip_addr offered_gw_addr; - struct ip_addr offered_bc_addr; -#define DHCP_MAX_DNS 2 - u32_t dns_count; /* actual number of DNS servers obtained */ - struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ - - u32_t offered_t0_lease; /* lease period (in seconds) */ - u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ - u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ -#if LWIP_DHCP_AUTOIP_COOP - u8_t autoip_coop_state; -#endif -/** Patch #1308 - * TODO: See dhcp.c "TODO"s - */ -#if 0 - struct ip_addr offered_si_addr; - u8_t *boot_file_name; -#endif -}; - -/* MUST be compiled with "pack structs" or equivalent! */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** minimum set of fields of any DHCP message */ -struct dhcp_msg -{ - PACK_STRUCT_FIELD(u8_t op); - PACK_STRUCT_FIELD(u8_t htype); - PACK_STRUCT_FIELD(u8_t hlen); - PACK_STRUCT_FIELD(u8_t hops); - PACK_STRUCT_FIELD(u32_t xid); - PACK_STRUCT_FIELD(u16_t secs); - PACK_STRUCT_FIELD(u16_t flags); - PACK_STRUCT_FIELD(struct ip_addr ciaddr); - PACK_STRUCT_FIELD(struct ip_addr yiaddr); - PACK_STRUCT_FIELD(struct ip_addr siaddr); - PACK_STRUCT_FIELD(struct ip_addr giaddr); -#define DHCP_CHADDR_LEN 16U - PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); -#define DHCP_SNAME_LEN 64U - PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); -#define DHCP_FILE_LEN 128U - PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); - PACK_STRUCT_FIELD(u32_t cookie); -#define DHCP_MIN_OPTIONS_LEN 68U -/** make sure user does not configure this too small */ -#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) -# undef DHCP_OPTIONS_LEN -#endif -/** allow this to be configured in lwipopts.h, but not too small */ -#if (!defined(DHCP_OPTIONS_LEN)) -/** set this to be sufficient for your options in outgoing DHCP msgs */ -# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN -#endif - PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** start DHCP configuration */ -err_t dhcp_start(struct netif *netif); -/** enforce early lease renewal (not needed normally)*/ -err_t dhcp_renew(struct netif *netif); -/** release the DHCP lease, usually called before dhcp_stop()*/ -err_t dhcp_release(struct netif *netif); -/** stop DHCP configuration */ -void dhcp_stop(struct netif *netif); -/** inform server of our manual IP address */ -void dhcp_inform(struct netif *netif); -/** Handle a possible change in the network configuration */ -void dhcp_network_changed(struct netif *netif); - -/** if enabled, check whether the offered IP address is not in use, using ARP */ -#if DHCP_DOES_ARP_CHECK -void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); -#endif - -/** to be called every minute */ -void dhcp_coarse_tmr(void); -/** to be called every half second */ -void dhcp_fine_tmr(void); - -/** DHCP message item offsets and length */ -#define DHCP_MSG_OFS (UDP_DATA_OFS) - #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) - #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) - #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) - #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) - #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) - #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) - #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) - #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) - #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) - #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) - #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) - #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) - #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) - #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) -#define DHCP_MSG_LEN 236 - -#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) -#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) - -#define DHCP_CLIENT_PORT 68 -#define DHCP_SERVER_PORT 67 - -/** DHCP client states */ -#define DHCP_REQUESTING 1 -#define DHCP_INIT 2 -#define DHCP_REBOOTING 3 -#define DHCP_REBINDING 4 -#define DHCP_RENEWING 5 -#define DHCP_SELECTING 6 -#define DHCP_INFORMING 7 -#define DHCP_CHECKING 8 -#define DHCP_PERMANENT 9 -#define DHCP_BOUND 10 -/** not yet implemented #define DHCP_RELEASING 11 */ -#define DHCP_BACKING_OFF 12 -#define DHCP_OFF 13 - -/** AUTOIP cooperatation flags */ -#define DHCP_AUTOIP_COOP_STATE_OFF 0 -#define DHCP_AUTOIP_COOP_STATE_ON 1 - -#define DHCP_BOOTREQUEST 1 -#define DHCP_BOOTREPLY 2 - -#define DHCP_DISCOVER 1 -#define DHCP_OFFER 2 -#define DHCP_REQUEST 3 -#define DHCP_DECLINE 4 -#define DHCP_ACK 5 -#define DHCP_NAK 6 -#define DHCP_RELEASE 7 -#define DHCP_INFORM 8 - -#define DHCP_HTYPE_ETH 1 - -#define DHCP_HLEN_ETH 6 - -#define DHCP_BROADCAST_FLAG 15 -#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) - -/** BootP options */ -#define DHCP_OPTION_PAD 0 -#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ -#define DHCP_OPTION_ROUTER 3 -#define DHCP_OPTION_DNS_SERVER 6 -#define DHCP_OPTION_HOSTNAME 12 -#define DHCP_OPTION_IP_TTL 23 -#define DHCP_OPTION_MTU 26 -#define DHCP_OPTION_BROADCAST 28 -#define DHCP_OPTION_TCP_TTL 37 -#define DHCP_OPTION_END 255 - -/** DHCP options */ -#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ -#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ -#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ - -#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ -#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 - - -#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ -#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ - -#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ -#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 - -#define DHCP_OPTION_T1 58 /* T1 renewal time */ -#define DHCP_OPTION_T2 59 /* T2 rebinding time */ -#define DHCP_OPTION_US 60 -#define DHCP_OPTION_CLIENT_ID 61 -#define DHCP_OPTION_TFTP_SERVERNAME 66 -#define DHCP_OPTION_BOOTFILE 67 - -/** possible combinations of overloading the file and sname fields with options */ -#define DHCP_OVERLOAD_NONE 0 -#define DHCP_OVERLOAD_FILE 1 -#define DHCP_OVERLOAD_SNAME 2 -#define DHCP_OVERLOAD_SNAME_FILE 3 - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_DHCP */ - -#endif /*__LWIP_DHCP_H__*/ diff --git a/components/net/lwip-1.3.2/src/include/lwip/mem.h b/components/net/lwip-1.3.2/src/include/lwip/mem.h deleted file mode 100644 index 327c2049ff..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/mem.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_MEM_H__ -#define __LWIP_MEM_H__ - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if MEM_LIBC_MALLOC - -#include /* for size_t */ - -typedef size_t mem_size_t; - -/* aliases for C library malloc() */ -#define mem_init() -/* in case C library malloc() needs extra protection, - * allow these defines to be overridden. - */ -#ifndef mem_free -#define mem_free free -#endif -#ifndef mem_malloc -#define mem_malloc malloc -#endif -#ifndef mem_calloc -#define mem_calloc calloc -#endif -#ifndef mem_realloc -static void *mem_realloc(void *mem, mem_size_t size) -{ - LWIP_UNUSED_ARG(size); - return mem; -} -#endif -#else /* MEM_LIBC_MALLOC */ - -/* MEM_SIZE would have to be aligned, but using 64000 here instead of - * 65535 leaves some room for alignment... - */ -#if MEM_SIZE > 64000l -typedef u32_t mem_size_t; -#else -typedef u16_t mem_size_t; -#endif /* MEM_SIZE > 64000 */ - -#if MEM_USE_POOLS -/** mem_init is not used when using pools instead of a heap */ -#define mem_init() -/** mem_realloc is not used when using pools instead of a heap: - we can't free part of a pool element and don't want to copy the rest */ -#define mem_realloc(mem, size) (mem) -#else /* MEM_USE_POOLS */ -/* lwIP alternative malloc */ -void mem_init(void); -void *mem_realloc(void *mem, mem_size_t size); -#endif /* MEM_USE_POOLS */ -void *mem_malloc(mem_size_t size); -void *mem_calloc(mem_size_t count, mem_size_t size); -void mem_free(void *mem); -#endif /* MEM_LIBC_MALLOC */ - -#ifndef LWIP_MEM_ALIGN_SIZE -#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) -#endif - -#ifndef LWIP_MEM_ALIGN -#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_MEM_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/memp.h b/components/net/lwip-1.3.2/src/include/lwip/memp.h deleted file mode 100644 index 702b57662d..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/memp.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __LWIP_MEMP_H__ -#define __LWIP_MEMP_H__ - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ -typedef enum { -#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, -#include "lwip/memp_std.h" - MEMP_MAX -} memp_t; - -#if MEM_USE_POOLS -/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ -typedef enum { - /* Get the first (via: - MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ - MEMP_POOL_HELPER_FIRST = ((u8_t) -#define LWIP_MEMPOOL(name,num,size,desc) -#define LWIP_MALLOC_MEMPOOL_START 1 -#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 -#define LWIP_MALLOC_MEMPOOL_END -#include "lwip/memp_std.h" - ) , - /* Get the last (via: - MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ - MEMP_POOL_HELPER_LAST = ((u8_t) -#define LWIP_MEMPOOL(name,num,size,desc) -#define LWIP_MALLOC_MEMPOOL_START -#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * -#define LWIP_MALLOC_MEMPOOL_END 1 -#include "lwip/memp_std.h" - ) -} memp_pool_helper_t; - -/* The actual start and stop values are here (cast them over) - We use this helper type and these defines so we can avoid using const memp_t values */ -#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) -#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) -#endif /* MEM_USE_POOLS */ - -#if MEMP_MEM_MALLOC || MEM_USE_POOLS -extern const u16_t memp_sizes[MEMP_MAX]; -#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */ - -#if MEMP_MEM_MALLOC - -#include "mem.h" - -#define memp_init() - -#else /* MEMP_MEM_MALLOC */ - -#if MEM_USE_POOLS -/** This structure is used to save the pool one element came from. */ -struct memp_malloc_helper -{ - memp_t poolnr; -}; -#endif /* MEM_USE_POOLS */ - -void memp_init(void); -#endif /* MEMP_MEM_MALLOC */ - -#if MEMP_OVERFLOW_CHECK -void *memp_malloc_fn(memp_t type, const char* file, const int line); -#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) -#else -void *memp_malloc(memp_t type); -#endif -void memp_free(memp_t type, void *mem); - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_MEMP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/netif.h b/components/net/lwip-1.3.2/src/include/lwip/netif.h deleted file mode 100644 index c50a6da895..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/netif.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_NETIF_H__ -#define __LWIP_NETIF_H__ - -#include "lwip/opt.h" - -#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) - -#include "lwip/err.h" - -#include "lwip/ip_addr.h" - -#include "lwip/inet.h" -#include "lwip/pbuf.h" -#if LWIP_DHCP -struct dhcp; -#endif -#if LWIP_AUTOIP -struct autoip; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* Throughout this file, IP addresses are expected to be in - * the same byte order as in IP_PCB. */ - -/** must be the maximum of all used hardware address lengths - across all types of interfaces in use */ -#define NETIF_MAX_HWADDR_LEN 6U - -/** TODO: define the use (where, when, whom) of netif flags */ - -/** whether the network interface is 'up'. this is - * a software flag used to control whether this network - * interface is enabled and processes traffic. - */ -#define NETIF_FLAG_UP 0x01U -/** if set, the netif has broadcast capability */ -#define NETIF_FLAG_BROADCAST 0x02U -/** if set, the netif is one end of a point-to-point connection */ -#define NETIF_FLAG_POINTTOPOINT 0x04U -/** if set, the interface is configured using DHCP */ -#define NETIF_FLAG_DHCP 0x08U -/** if set, the interface has an active link - * (set by the network interface driver) */ -#define NETIF_FLAG_LINK_UP 0x10U -/** if set, the netif is an device using ARP */ -#define NETIF_FLAG_ETHARP 0x20U -/** if set, the netif has IGMP capability */ -#define NETIF_FLAG_IGMP 0x40U - -/** Generic data structure used for all lwIP network interfaces. - * The following fields should be filled in by the initialization - * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ - -struct netif { - /** pointer to next in linked list */ - struct netif *next; - - /** IP address configuration in network byte order */ - struct ip_addr ip_addr; - struct ip_addr netmask; - struct ip_addr gw; - - /** This function is called by the network device driver - * to pass a packet up the TCP/IP stack. */ - err_t (* input)(struct pbuf *p, struct netif *inp); - /** This function is called by the IP module when it wants - * to send a packet on the interface. This function typically - * first resolves the hardware address, then sends the packet. */ - err_t (* output)(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr); - /** This function is called by the ARP module when it wants - * to send a packet on the interface. This function outputs - * the pbuf as-is on the link medium. */ - err_t (* linkoutput)(struct netif *netif, struct pbuf *p); -#if LWIP_NETIF_STATUS_CALLBACK - /** This function is called when the netif state is set to up or down - */ - void (* status_callback)(struct netif *netif); -#endif /* LWIP_NETIF_STATUS_CALLBACK */ -#if LWIP_NETIF_LINK_CALLBACK - /** This function is called when the netif link is set to up or down - */ - void (* link_callback)(struct netif *netif); -#endif /* LWIP_NETIF_LINK_CALLBACK */ - /** This field can be set by the device driver and could point - * to state information for the device. */ - void *state; -#if LWIP_DHCP - /** the DHCP client state information for this netif */ - struct dhcp *dhcp; -#endif /* LWIP_DHCP */ -#if LWIP_AUTOIP - /** the AutoIP client state information for this netif */ - struct autoip *autoip; -#endif -#if LWIP_NETIF_HOSTNAME - /* the hostname for this netif, NULL is a valid value */ - char* hostname; -#endif /* LWIP_NETIF_HOSTNAME */ - /** maximum transfer unit (in bytes) */ - u16_t mtu; - /** number of bytes used in hwaddr */ - u8_t hwaddr_len; - /** link level hardware address of this interface */ - u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; - /** flags (see NETIF_FLAG_ above) */ - u8_t flags; - /** descriptive abbreviation */ - char name[2]; - /** number of this interface */ - u8_t num; -#if LWIP_SNMP - /** link type (from "snmp_ifType" enum from snmp.h) */ - u8_t link_type; - /** (estimate) link speed */ - u32_t link_speed; - /** timestamp at last change made (up/down) */ - u32_t ts; - /** counters */ - u32_t ifinoctets; - u32_t ifinucastpkts; - u32_t ifinnucastpkts; - u32_t ifindiscards; - u32_t ifoutoctets; - u32_t ifoutucastpkts; - u32_t ifoutnucastpkts; - u32_t ifoutdiscards; -#endif /* LWIP_SNMP */ -#if LWIP_IGMP - /* This function could be called to add or delete a entry in the multicast filter table of the ethernet MAC.*/ - err_t (*igmp_mac_filter)( struct netif *netif, struct ip_addr *group, u8_t action); -#endif /* LWIP_IGMP */ -#if LWIP_NETIF_HWADDRHINT - u8_t *addr_hint; -#endif /* LWIP_NETIF_HWADDRHINT */ -#if ENABLE_LOOPBACK - /* List of packets to be queued for ourselves. */ - struct pbuf *loop_first; - struct pbuf *loop_last; -#if LWIP_LOOPBACK_MAX_PBUFS - u16_t loop_cnt_current; -#endif /* LWIP_LOOPBACK_MAX_PBUFS */ -#endif /* ENABLE_LOOPBACK */ -}; - -#if LWIP_SNMP -#define NETIF_INIT_SNMP(netif, type, speed) \ - /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \ - netif->link_type = type; \ - /* your link speed here (units: bits per second) */ \ - netif->link_speed = speed; \ - netif->ts = 0; \ - netif->ifinoctets = 0; \ - netif->ifinucastpkts = 0; \ - netif->ifinnucastpkts = 0; \ - netif->ifindiscards = 0; \ - netif->ifoutoctets = 0; \ - netif->ifoutucastpkts = 0; \ - netif->ifoutnucastpkts = 0; \ - netif->ifoutdiscards = 0 -#else /* LWIP_SNMP */ -#define NETIF_INIT_SNMP(netif, type, speed) -#endif /* LWIP_SNMP */ - - -/** The list of network interfaces. */ -extern struct netif *netif_list; -/** The default network interface. */ -extern struct netif *netif_default; - -#define netif_init() /* Compatibility define, not init needed. */ - -struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)); - -void -netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw); -void netif_remove(struct netif * netif); - -/* Returns a network interface given its name. The name is of the form - "et0", where the first two letters are the "name" field in the - netif structure, and the digit is in the num field in the same - structure. */ -struct netif *netif_find(char *name); - -void netif_set_default(struct netif *netif); - -void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); -void netif_set_netmask(struct netif *netif, struct ip_addr *netmask); -void netif_set_gw(struct netif *netif, struct ip_addr *gw); - -void netif_set_up(struct netif *netif); -void netif_set_down(struct netif *netif); -u8_t netif_is_up(struct netif *netif); - -#if LWIP_NETIF_STATUS_CALLBACK -/* - * Set callback to be called when interface is brought up/down - */ -void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif)); -#endif /* LWIP_NETIF_STATUS_CALLBACK */ - -#if LWIP_NETIF_LINK_CALLBACK -void netif_set_link_up(struct netif *netif); -void netif_set_link_down(struct netif *netif); -u8_t netif_is_link_up(struct netif *netif); -/* - * Set callback to be called when link is brought up/down - */ -void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif)); -#endif /* LWIP_NETIF_LINK_CALLBACK */ - -#ifdef __cplusplus -} -#endif - -#if ENABLE_LOOPBACK -err_t netif_loop_output(struct netif *netif, struct pbuf *p, struct ip_addr *dest_ip); -void netif_poll(struct netif *netif); -#if !LWIP_NETIF_LOOPBACK_MULTITHREADING -void netif_poll_all(void); -#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ -#endif /* ENABLE_LOOPBACK */ - -#endif /* __LWIP_NETIF_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/netifapi.h b/components/net/lwip-1.3.2/src/include/lwip/netifapi.h deleted file mode 100644 index a9f63651c6..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/netifapi.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#ifndef __LWIP_NETIFAPI_H__ -#define __LWIP_NETIFAPI_H__ - -#include "lwip/opt.h" - -#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sys.h" -#include "lwip/netif.h" -#include "lwip/dhcp.h" -#include "lwip/autoip.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct netifapi_msg_msg { -#if !LWIP_TCPIP_CORE_LOCKING - sys_sem_t sem; -#endif /* !LWIP_TCPIP_CORE_LOCKING */ - err_t err; - struct netif *netif; - union { - struct { - struct ip_addr *ipaddr; - struct ip_addr *netmask; - struct ip_addr *gw; - void *state; - err_t (* init) (struct netif *netif); - err_t (* input)(struct pbuf *p, struct netif *netif); - } add; - struct { - void (* voidfunc)(struct netif *netif); - err_t (* errtfunc)(struct netif *netif); - } common; - } msg; -}; - -struct netifapi_msg { - void (* function)(struct netifapi_msg_msg *msg); - struct netifapi_msg_msg msg; -}; - - -/* API for application */ -err_t netifapi_netif_add ( struct netif *netif, - struct ip_addr *ipaddr, - struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif) ); - -err_t netifapi_netif_set_addr ( struct netif *netif, - struct ip_addr *ipaddr, - struct ip_addr *netmask, - struct ip_addr *gw ); - -err_t netifapi_netif_common ( struct netif *netif, - void (* voidfunc)(struct netif *netif), - err_t (* errtfunc)(struct netif *netif) ); - -#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) -#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) -#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) -#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) -#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) -#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) -#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) -#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) - -#define netifapi_netif_set_link_up(n) netifapi_netif_common(n, netif_set_link_up, NULL) -#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL) - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_NETIF_API */ - -#endif /* __LWIP_NETIFAPI_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/opt.h b/components/net/lwip-1.3.2/src/include/lwip/opt.h deleted file mode 100644 index eb99a77846..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/opt.h +++ /dev/null @@ -1,1840 +0,0 @@ -/** - * @file - * - * lwIP Options Configuration - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_OPT_H__ -#define __LWIP_OPT_H__ - -/* - * Include user defined options first. Anything not defined in these files - * will be set to standard values. Override anything you dont like! - */ -#include "lwipopts.h" -#include "lwip/debug.h" - -/* - ----------------------------------------------- - ---------- Platform specific locking ---------- - ----------------------------------------------- -*/ - -/** - * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain - * critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#ifndef SYS_LIGHTWEIGHT_PROT -#define SYS_LIGHTWEIGHT_PROT 0 -#endif - -/** - * NO_SYS==1: Provides VERY minimal functionality. Otherwise, - * use lwIP facilities. - */ -#ifndef NO_SYS -#define NO_SYS 0 -#endif - -/** - * MEMCPY: override this if you have a faster implementation at hand than the - * one included in your C library - */ -#ifndef MEMCPY -#define MEMCPY(dst,src,len) memcpy(dst,src,len) -#endif - -/** - * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a - * call to memcpy() if the length is known at compile time and is small. - */ -#ifndef SMEMCPY -#define SMEMCPY(dst,src,len) memcpy(dst,src,len) -#endif - -/* - ------------------------------------ - ---------- Memory options ---------- - ------------------------------------ -*/ -/** - * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library - * instead of the lwip internal allocator. Can save code size if you - * already use it. - */ -#ifndef MEM_LIBC_MALLOC -#define MEM_LIBC_MALLOC 0 -#endif - -/** -* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. -* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution -* speed and usage from interrupts! -*/ -#ifndef MEMP_MEM_MALLOC -#define MEMP_MEM_MALLOC 0 -#endif - -/** - * MEM_ALIGNMENT: should be set to the alignment of the CPU - * 4 byte alignment -> #define MEM_ALIGNMENT 4 - * 2 byte alignment -> #define MEM_ALIGNMENT 2 - */ -#ifndef MEM_ALIGNMENT -#define MEM_ALIGNMENT 1 -#endif - -/** - * MEM_SIZE: the size of the heap memory. If the application will send - * a lot of data that needs to be copied, this should be set high. - */ -#ifndef MEM_SIZE -#define MEM_SIZE 1600 -#endif - -/** - * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable - * amount of bytes before and after each memp element in every pool and fills - * it with a prominent default value. - * MEMP_OVERFLOW_CHECK == 0 no checking - * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed - * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time - * memp_malloc() or memp_free() is called (useful but slow!) - */ -#ifndef MEMP_OVERFLOW_CHECK -#define MEMP_OVERFLOW_CHECK 0 -#endif - -/** - * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make - * sure that there are no cycles in the linked lists. - */ -#ifndef MEMP_SANITY_CHECK -#define MEMP_SANITY_CHECK 0 -#endif - -/** - * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set - * of memory pools of various sizes. When mem_malloc is called, an element of - * the smallest pool that can provide the length needed is returned. - * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. - */ -#ifndef MEM_USE_POOLS -#define MEM_USE_POOLS 0 -#endif - -/** - * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next - * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more - * reliable. */ -#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL -#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 -#endif - -/** - * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h - * that defines additional pools beyond the "standard" ones required - * by lwIP. If you set this to 1, you must have lwippools.h in your - * inlude path somewhere. - */ -#ifndef MEMP_USE_CUSTOM_POOLS -#define MEMP_USE_CUSTOM_POOLS 0 -#endif - -/** - * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from - * interrupt context (or another context that doesn't allow waiting for a - * semaphore). - * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, - * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs - * with each loop so that mem_free can run. - * - * ATTENTION: As you can see from the above description, this leads to dis-/ - * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc - * can need longer. - * - * If you don't want that, at least for NO_SYS=0, you can still use the following - * functions to enqueue a deallocation call which then runs in the tcpip_thread - * context: - * - pbuf_free_callback(p); - * - mem_free_callback(m); - */ -#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT -#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 -#endif - -/* - ------------------------------------------------ - ---------- Internal Memory Pool Sizes ---------- - ------------------------------------------------ -*/ -/** - * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). - * If the application sends a lot of data out of ROM (or other static memory), - * this should be set high. - */ -#ifndef MEMP_NUM_PBUF -#define MEMP_NUM_PBUF 16 -#endif - -/** - * MEMP_NUM_RAW_PCB: Number of raw connection PCBs - * (requires the LWIP_RAW option) - */ -#ifndef MEMP_NUM_RAW_PCB -#define MEMP_NUM_RAW_PCB 4 -#endif - -/** - * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - * per active UDP "connection". - * (requires the LWIP_UDP option) - */ -#ifndef MEMP_NUM_UDP_PCB -#define MEMP_NUM_UDP_PCB 4 -#endif - -/** - * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. - * (requires the LWIP_TCP option) - */ -#ifndef MEMP_NUM_TCP_PCB -#define MEMP_NUM_TCP_PCB 5 -#endif - -/** - * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. - * (requires the LWIP_TCP option) - */ -#ifndef MEMP_NUM_TCP_PCB_LISTEN -#define MEMP_NUM_TCP_PCB_LISTEN 8 -#endif - -/** - * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. - * (requires the LWIP_TCP option) - */ -#ifndef MEMP_NUM_TCP_SEG -#define MEMP_NUM_TCP_SEG 16 -#endif - -/** - * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for - * reassembly (whole packets, not fragments!) - */ -#ifndef MEMP_NUM_REASSDATA -#define MEMP_NUM_REASSDATA 5 -#endif - -/** - * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing - * packets (pbufs) that are waiting for an ARP request (to resolve - * their destination address) to finish. - * (requires the ARP_QUEUEING option) - */ -#ifndef MEMP_NUM_ARP_QUEUE -#define MEMP_NUM_ARP_QUEUE 30 -#endif - -/** - * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces - * can be members et the same time (one per netif - allsystems group -, plus one - * per netif membership). - * (requires the LWIP_IGMP option) - */ -#ifndef MEMP_NUM_IGMP_GROUP -#define MEMP_NUM_IGMP_GROUP 8 -#endif - -/** - * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. - * (requires NO_SYS==0) - */ -#ifndef MEMP_NUM_SYS_TIMEOUT -#define MEMP_NUM_SYS_TIMEOUT 3 -#endif - -/** - * MEMP_NUM_NETBUF: the number of struct netbufs. - * (only needed if you use the sequential API, like api_lib.c) - */ -#ifndef MEMP_NUM_NETBUF -#define MEMP_NUM_NETBUF 2 -#endif - -/** - * MEMP_NUM_NETCONN: the number of struct netconns. - * (only needed if you use the sequential API, like api_lib.c) - */ -#ifndef MEMP_NUM_NETCONN -#define MEMP_NUM_NETCONN 4 -#endif - -/** - * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used - * for callback/timeout API communication. - * (only needed if you use tcpip.c) - */ -#ifndef MEMP_NUM_TCPIP_MSG_API -#define MEMP_NUM_TCPIP_MSG_API 8 -#endif - -/** - * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used - * for incoming packets. - * (only needed if you use tcpip.c) - */ -#ifndef MEMP_NUM_TCPIP_MSG_INPKT -#define MEMP_NUM_TCPIP_MSG_INPKT 8 -#endif - -/** - * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. - */ -#ifndef PBUF_POOL_SIZE -#define PBUF_POOL_SIZE 16 -#endif - -/* - --------------------------------- - ---------- ARP options ---------- - --------------------------------- -*/ -/** - * LWIP_ARP==1: Enable ARP functionality. - */ -#ifndef LWIP_ARP -#define LWIP_ARP 1 -#endif - -/** - * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. - */ -#ifndef ARP_TABLE_SIZE -#define ARP_TABLE_SIZE 10 -#endif - -/** - * ARP_QUEUEING==1: Outgoing packets are queued during hardware address - * resolution. - */ -#ifndef ARP_QUEUEING -#define ARP_QUEUEING 1 -#endif - -/** - * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be - * updated with the source MAC and IP addresses supplied in the packet. - * You may want to disable this if you do not trust LAN peers to have the - * correct addresses, or as a limited approach to attempt to handle - * spoofing. If disabled, lwIP will need to make a new ARP request if - * the peer is not already in the ARP table, adding a little latency. - */ -#ifndef ETHARP_TRUST_IP_MAC -#define ETHARP_TRUST_IP_MAC 1 -#endif - -/** - * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. - * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. - * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. - * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. - */ -#ifndef ETHARP_SUPPORT_VLAN -#define ETHARP_SUPPORT_VLAN 0 -#endif - -/* - -------------------------------- - ---------- IP options ---------- - -------------------------------- -*/ -/** - * IP_FORWARD==1: Enables the ability to forward IP packets across network - * interfaces. If you are going to run lwIP on a device with only one network - * interface, define this to 0. - */ -#ifndef IP_FORWARD -#define IP_FORWARD 0 -#endif - -/** - * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. - * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. - * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). - */ -#ifndef IP_OPTIONS_ALLOWED -#define IP_OPTIONS_ALLOWED 1 -#endif - -/** - * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that - * this option does not affect outgoing packet sizes, which can be controlled - * via IP_FRAG. - */ -#ifndef IP_REASSEMBLY -#define IP_REASSEMBLY 1 -#endif - -/** - * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note - * that this option does not affect incoming packet sizes, which can be - * controlled via IP_REASSEMBLY. - */ -#ifndef IP_FRAG -#define IP_FRAG 1 -#endif - -/** - * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) - * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived - * in this time, the whole packet is discarded. - */ -#ifndef IP_REASS_MAXAGE -#define IP_REASS_MAXAGE 3 -#endif - -/** - * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. - * Since the received pbufs are enqueued, be sure to configure - * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive - * packets even if the maximum amount of fragments is enqueued for reassembly! - */ -#ifndef IP_REASS_MAX_PBUFS -#define IP_REASS_MAX_PBUFS 10 -#endif - -/** - * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP - * fragmentation. Otherwise pbufs are allocated and reference the original - * packet data to be fragmented. - */ -#ifndef IP_FRAG_USES_STATIC_BUF -#define IP_FRAG_USES_STATIC_BUF 1 -#endif - -/** - * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer - * (requires IP_FRAG_USES_STATIC_BUF==1) - */ -#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) -#define IP_FRAG_MAX_MTU 1500 -#endif - -/** - * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. - */ -#ifndef IP_DEFAULT_TTL -#define IP_DEFAULT_TTL 255 -#endif - -/** - * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast - * filter per pcb on udp and raw send operations. To enable broadcast filter - * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. - */ -#ifndef IP_SOF_BROADCAST -#define IP_SOF_BROADCAST 0 -#endif - -/** - * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast - * filter on recv operations. - */ -#ifndef IP_SOF_BROADCAST_RECV -#define IP_SOF_BROADCAST_RECV 0 -#endif - -/* - ---------------------------------- - ---------- ICMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_ICMP==1: Enable ICMP module inside the IP stack. - * Be careful, disable that make your product non-compliant to RFC1122 - */ -#ifndef LWIP_ICMP -#define LWIP_ICMP 1 -#endif - -/** - * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. - */ -#ifndef ICMP_TTL -#define ICMP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) - */ -#ifndef LWIP_BROADCAST_PING -#define LWIP_BROADCAST_PING 0 -#endif - -/** - * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) - */ -#ifndef LWIP_MULTICAST_PING -#define LWIP_MULTICAST_PING 0 -#endif - -/* - --------------------------------- - ---------- RAW options ---------- - --------------------------------- -*/ -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#ifndef LWIP_RAW -#define LWIP_RAW 1 -#endif - -/** - * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. - */ -#ifndef RAW_TTL -#define RAW_TTL (IP_DEFAULT_TTL) -#endif - -/* - ---------------------------------- - ---------- DHCP options ---------- - ---------------------------------- -*/ -/** - * LWIP_DHCP==1: Enable DHCP module. - */ -#ifndef LWIP_DHCP -#define LWIP_DHCP 0 -#endif - -/** - * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. - */ -#ifndef DHCP_DOES_ARP_CHECK -#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) -#endif - -/* - ------------------------------------ - ---------- AUTOIP options ---------- - ------------------------------------ -*/ -/** - * LWIP_AUTOIP==1: Enable AUTOIP module. - */ -#ifndef LWIP_AUTOIP -#define LWIP_AUTOIP 0 -#endif - -/** - * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on - * the same interface at the same time. - */ -#ifndef LWIP_DHCP_AUTOIP_COOP -#define LWIP_DHCP_AUTOIP_COOP 0 -#endif - -/** - * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes - * that should be sent before falling back on AUTOIP. This can be set - * as low as 1 to get an AutoIP address very quickly, but you should - * be prepared to handle a changing IP address when DHCP overrides - * AutoIP. - */ -#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES -#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 -#endif - -/* - ---------------------------------- - ---------- SNMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP - * transport. - */ -#ifndef LWIP_SNMP -#define LWIP_SNMP 0 -#endif - -/** - * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will - * allow. At least one request buffer is required. - */ -#ifndef SNMP_CONCURRENT_REQUESTS -#define SNMP_CONCURRENT_REQUESTS 1 -#endif - -/** - * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap - * destination is required - */ -#ifndef SNMP_TRAP_DESTINATIONS -#define SNMP_TRAP_DESTINATIONS 1 -#endif - -/** - * SNMP_PRIVATE_MIB: - */ -#ifndef SNMP_PRIVATE_MIB -#define SNMP_PRIVATE_MIB 0 -#endif - -/** - * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not - * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). - * Unsafe requests are disabled by default! - */ -#ifndef SNMP_SAFE_REQUESTS -#define SNMP_SAFE_REQUESTS 1 -#endif - -/* - ---------------------------------- - ---------- IGMP options ---------- - ---------------------------------- -*/ -/** - * LWIP_IGMP==1: Turn on IGMP module. - */ -#ifndef LWIP_IGMP -#define LWIP_IGMP 0 -#endif - -/* - ---------------------------------- - ---------- DNS options ----------- - ---------------------------------- -*/ -/** - * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS - * transport. - */ -#ifndef LWIP_DNS -#define LWIP_DNS 0 -#endif - -/** DNS maximum number of entries to maintain locally. */ -#ifndef DNS_TABLE_SIZE -#define DNS_TABLE_SIZE 4 -#endif - -/** DNS maximum host name length supported in the name table. */ -#ifndef DNS_MAX_NAME_LENGTH -#define DNS_MAX_NAME_LENGTH 256 -#endif - -/** The maximum of DNS servers */ -#ifndef DNS_MAX_SERVERS -#define DNS_MAX_SERVERS 2 -#endif - -/** DNS do a name checking between the query and the response. */ -#ifndef DNS_DOES_NAME_CHECK -#define DNS_DOES_NAME_CHECK 1 -#endif - -/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if - DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2. - The buffer will be of size DNS_MSG_SIZE */ -#ifndef DNS_USES_STATIC_BUF -#define DNS_USES_STATIC_BUF 1 -#endif - -/** DNS message max. size. Default value is RFC compliant. */ -#ifndef DNS_MSG_SIZE -#define DNS_MSG_SIZE 512 -#endif - -/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, - * you have to define - * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} - * (an array of structs name/address, where address is an u32_t in network - * byte order). - * - * Instead, you can also use an external function: - * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) - * that returns the IP address or INADDR_NONE if not found. - */ -#ifndef DNS_LOCAL_HOSTLIST -#define DNS_LOCAL_HOSTLIST 0 -#endif /* DNS_LOCAL_HOSTLIST */ - -/** If this is turned on, the local host-list can be dynamically changed - * at runtime. */ -#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC -#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 -#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ - -/* - --------------------------------- - ---------- UDP options ---------- - --------------------------------- -*/ -/** - * LWIP_UDP==1: Turn on UDP. - */ -#ifndef LWIP_UDP -#define LWIP_UDP 1 -#endif - -/** - * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) - */ -#ifndef LWIP_UDPLITE -#define LWIP_UDPLITE 0 -#endif - -/** - * UDP_TTL: Default Time-To-Live value. - */ -#ifndef UDP_TTL -#define UDP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. - */ -#ifndef LWIP_NETBUF_RECVINFO -#define LWIP_NETBUF_RECVINFO 0 -#endif - -/* - --------------------------------- - ---------- TCP options ---------- - --------------------------------- -*/ -/** - * LWIP_TCP==1: Turn on TCP. - */ -#ifndef LWIP_TCP -#define LWIP_TCP 1 -#endif - -/** - * TCP_TTL: Default Time-To-Live value. - */ -#ifndef TCP_TTL -#define TCP_TTL (IP_DEFAULT_TTL) -#endif - -/** - * TCP_WND: The size of a TCP window. This must be at least - * (2 * TCP_MSS) for things to work well - */ -#ifndef TCP_WND -#define TCP_WND (4 * TCP_MSS) -#endif - -/** - * TCP_MAXRTX: Maximum number of retransmissions of data segments. - */ -#ifndef TCP_MAXRTX -#define TCP_MAXRTX 12 -#endif - -/** - * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. - */ -#ifndef TCP_SYNMAXRTX -#define TCP_SYNMAXRTX 6 -#endif - -/** - * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. - * Define to 0 if your device is low on memory. - */ -#ifndef TCP_QUEUE_OOSEQ -#define TCP_QUEUE_OOSEQ (LWIP_TCP) -#endif - -/** - * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, - * you might want to increase this.) - * For the receive side, this MSS is advertised to the remote side - * when opening a connection. For the transmit size, this MSS sets - * an upper limit on the MSS advertised by the remote host. - */ -#ifndef TCP_MSS -#define TCP_MSS 536 -#endif - -/** - * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really - * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which - * reflects the available reassembly buffer size at the remote host) and the - * largest size permitted by the IP layer" (RFC 1122) - * Setting this to 1 enables code that checks TCP_MSS against the MTU of the - * netif used for a connection and limits the MSS if it would be too big otherwise. - */ -#ifndef TCP_CALCULATE_EFF_SEND_MSS -#define TCP_CALCULATE_EFF_SEND_MSS 1 -#endif - - -/** - * TCP_SND_BUF: TCP sender buffer space (bytes). - */ -#ifndef TCP_SND_BUF -#define TCP_SND_BUF 256 -#endif - -/** - * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least - * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. - */ -#ifndef TCP_SND_QUEUELEN -#define TCP_SND_QUEUELEN (4 * (TCP_SND_BUF)/(TCP_MSS)) -#endif - -/** - * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal - * to TCP_SND_BUF. It is the amount of space which must be available in the - * TCP snd_buf for select to return writable. - */ -#ifndef TCP_SNDLOWAT -#define TCP_SNDLOWAT ((TCP_SND_BUF)/2) -#endif - -/** - * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. - */ -#ifndef TCP_LISTEN_BACKLOG -#define TCP_LISTEN_BACKLOG 0 -#endif - -/** - * The maximum allowed backlog for TCP listen netconns. - * This backlog is used unless another is explicitly specified. - * 0xff is the maximum (u8_t). - */ -#ifndef TCP_DEFAULT_LISTEN_BACKLOG -#define TCP_DEFAULT_LISTEN_BACKLOG 0xff -#endif - -/** - * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. - */ -#ifndef LWIP_TCP_TIMESTAMPS -#define LWIP_TCP_TIMESTAMPS 0 -#endif - -/** - * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an - * explicit window update - */ -#ifndef TCP_WND_UPDATE_THRESHOLD -#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) -#endif - -/** - * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. - * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all - * events (accept, sent, etc) that happen in the system. - * LWIP_CALLBACK_API==1: The PCB callback function is called directly - * for the event. - */ -#ifndef LWIP_EVENT_API -#define LWIP_EVENT_API 0 -#define LWIP_CALLBACK_API 1 -#else -#define LWIP_EVENT_API 1 -#define LWIP_CALLBACK_API 0 -#endif - - -/* - ---------------------------------- - ---------- Pbuf options ---------- - ---------------------------------- -*/ -/** - * PBUF_LINK_HLEN: the number of bytes that should be allocated for a - * link level header. The default is 14, the standard value for - * Ethernet. - */ -#ifndef PBUF_LINK_HLEN -#define PBUF_LINK_HLEN 14 -#endif - -/** - * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is - * designed to accomodate single full size TCP frame in one pbuf, including - * TCP_MSS, IP header, and link header. - */ -#ifndef PBUF_POOL_BUFSIZE -#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) -#endif - -/* - ------------------------------------------------ - ---------- Network Interfaces options ---------- - ------------------------------------------------ -*/ -/** - * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname - * field. - */ -#ifndef LWIP_NETIF_HOSTNAME -#define LWIP_NETIF_HOSTNAME 0 -#endif - -/** - * LWIP_NETIF_API==1: Support netif api (in netifapi.c) - */ -#ifndef LWIP_NETIF_API -#define LWIP_NETIF_API 0 -#endif - -/** - * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface - * changes its up/down status (i.e., due to DHCP IP acquistion) - */ -#ifndef LWIP_NETIF_STATUS_CALLBACK -#define LWIP_NETIF_STATUS_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface - * whenever the link changes (i.e., link down) - */ -#ifndef LWIP_NETIF_LINK_CALLBACK -#define LWIP_NETIF_LINK_CALLBACK 0 -#endif - -/** - * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table - * indices) in struct netif. TCP and UDP can make use of this to prevent - * scanning the ARP table for every sent packet. While this is faster for big - * ARP tables or many concurrent connections, it might be counterproductive - * if you have a tiny ARP table or if there never are concurrent connections. - */ -#ifndef LWIP_NETIF_HWADDRHINT -#define LWIP_NETIF_HWADDRHINT 0 -#endif - -/** - * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP - * address equal to the netif IP address, looping them back up the stack. - */ -#ifndef LWIP_NETIF_LOOPBACK -#define LWIP_NETIF_LOOPBACK 0 -#endif - -/** - * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback - * sending for each netif (0 = disabled) - */ -#ifndef LWIP_LOOPBACK_MAX_PBUFS -#define LWIP_LOOPBACK_MAX_PBUFS 0 -#endif - -/** - * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in - * the system, as netifs must change how they behave depending on this setting - * for the LWIP_NETIF_LOOPBACK option to work. - * Setting this is needed to avoid reentering non-reentrant functions like - * tcp_input(). - * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a - * multithreaded environment like tcpip.c. In this case, netif->input() - * is called directly. - * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. - * The packets are put on a list and netif_poll() must be called in - * the main application loop. - */ -#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING -#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) -#endif - -/** - * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data - * to be sent into one single pbuf. This is for compatibility with DMA-enabled - * MACs that do not support scatter-gather. - * Beware that this might involve CPU-memcpy before transmitting that would not - * be needed without this flag! Use this only if you need to! - * - * @todo: TCP and IP-frag do not work with this, yet: - */ -#ifndef LWIP_NETIF_TX_SINGLE_PBUF -#define LWIP_NETIF_TX_SINGLE_PBUF 0 -#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ - -/* - ------------------------------------ - ---------- LOOPIF options ---------- - ------------------------------------ -*/ -/** - * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c - */ -#ifndef LWIP_HAVE_LOOPIF -#define LWIP_HAVE_LOOPIF 0 -#endif - -/* - ------------------------------------ - ---------- SLIPIF options ---------- - ------------------------------------ -*/ -/** - * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c - */ -#ifndef LWIP_HAVE_SLIPIF -#define LWIP_HAVE_SLIPIF 0 -#endif - -/* - ------------------------------------ - ---------- Thread options ---------- - ------------------------------------ -*/ -/** - * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. - */ -#ifndef TCPIP_THREAD_NAME -#define TCPIP_THREAD_NAME "tcpip_thread" -#endif - -/** - * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef TCPIP_THREAD_STACKSIZE -#define TCPIP_THREAD_STACKSIZE 0 -#endif - -/** - * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef TCPIP_THREAD_PRIO -#define TCPIP_THREAD_PRIO 1 -#endif - -/** - * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages - * The queue size value itself is platform-dependent, but is passed to - * sys_mbox_new() when tcpip_init is called. - */ -#ifndef TCPIP_MBOX_SIZE -#define TCPIP_MBOX_SIZE 0 -#endif - -/** - * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. - */ -#ifndef SLIPIF_THREAD_NAME -#define SLIPIF_THREAD_NAME "slipif_loop" -#endif - -/** - * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef SLIPIF_THREAD_STACKSIZE -#define SLIPIF_THREAD_STACKSIZE 0 -#endif - -/** - * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef SLIPIF_THREAD_PRIO -#define SLIPIF_THREAD_PRIO 1 -#endif - -/** - * PPP_THREAD_NAME: The name assigned to the pppMain thread. - */ -#ifndef PPP_THREAD_NAME -#define PPP_THREAD_NAME "pppMain" -#endif - -/** - * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef PPP_THREAD_STACKSIZE -#define PPP_THREAD_STACKSIZE 0 -#endif - -/** - * PPP_THREAD_PRIO: The priority assigned to the pppMain thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef PPP_THREAD_PRIO -#define PPP_THREAD_PRIO 1 -#endif - -/** - * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. - */ -#ifndef DEFAULT_THREAD_NAME -#define DEFAULT_THREAD_NAME "lwIP" -#endif - -/** - * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. - * The stack size value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef DEFAULT_THREAD_STACKSIZE -#define DEFAULT_THREAD_STACKSIZE 0 -#endif - -/** - * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. - * The priority value itself is platform-dependent, but is passed to - * sys_thread_new() when the thread is created. - */ -#ifndef DEFAULT_THREAD_PRIO -#define DEFAULT_THREAD_PRIO 1 -#endif - -/** - * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#ifndef DEFAULT_RAW_RECVMBOX_SIZE -#define DEFAULT_RAW_RECVMBOX_SIZE 0 -#endif - -/** - * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#ifndef DEFAULT_UDP_RECVMBOX_SIZE -#define DEFAULT_UDP_RECVMBOX_SIZE 0 -#endif - -/** - * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a - * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed - * to sys_mbox_new() when the recvmbox is created. - */ -#ifndef DEFAULT_TCP_RECVMBOX_SIZE -#define DEFAULT_TCP_RECVMBOX_SIZE 0 -#endif - -/** - * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. - * The queue size value itself is platform-dependent, but is passed to - * sys_mbox_new() when the acceptmbox is created. - */ -#ifndef DEFAULT_ACCEPTMBOX_SIZE -#define DEFAULT_ACCEPTMBOX_SIZE 0 -#endif - -/* - ---------------------------------------------- - ---------- Sequential layer options ---------- - ---------------------------------------------- -*/ -/** - * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) - * Don't use it if you're not an active lwIP project member - */ -#ifndef LWIP_TCPIP_CORE_LOCKING -#define LWIP_TCPIP_CORE_LOCKING 0 -#endif - -/** - * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) - */ -#ifndef LWIP_NETCONN -#define LWIP_NETCONN 1 -#endif - -/* - ------------------------------------ - ---------- Socket options ---------- - ------------------------------------ -*/ -/** - * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) - */ -#ifndef LWIP_SOCKET -#define LWIP_SOCKET 1 -#endif - -/** - * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. - * (only used if you use sockets.c) - */ -#ifndef LWIP_COMPAT_SOCKETS -#define LWIP_COMPAT_SOCKETS 1 -#endif - -/** - * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. - * Disable this option if you use a POSIX operating system that uses the same - * names (read, write & close). (only used if you use sockets.c) - */ -#ifndef LWIP_POSIX_SOCKETS_IO_NAMES -#define LWIP_POSIX_SOCKETS_IO_NAMES 1 -#endif - -/** - * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT - * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set - * in seconds. (does not require sockets.c, and will affect tcp.c) - */ -#ifndef LWIP_TCP_KEEPALIVE -#define LWIP_TCP_KEEPALIVE 0 -#endif - -/** - * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. - */ -#ifndef LWIP_SO_RCVTIMEO -#define LWIP_SO_RCVTIMEO 0 -#endif - -/** - * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. - */ -#ifndef LWIP_SO_RCVBUF -#define LWIP_SO_RCVBUF 0 -#endif - -/** - * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. - */ -#ifndef RECV_BUFSIZE_DEFAULT -#define RECV_BUFSIZE_DEFAULT INT_MAX -#endif - -/** - * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE! - */ -#ifndef SO_REUSE -#define SO_REUSE 0 -#endif - -/* - ---------------------------------------- - ---------- Statistics options ---------- - ---------------------------------------- -*/ -/** - * LWIP_STATS==1: Enable statistics collection in lwip_stats. - */ -#ifndef LWIP_STATS -#define LWIP_STATS 1 -#endif - -#if LWIP_STATS - -/** - * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. - */ -#ifndef LWIP_STATS_DISPLAY -#define LWIP_STATS_DISPLAY 0 -#endif - -/** - * LINK_STATS==1: Enable link stats. - */ -#ifndef LINK_STATS -#define LINK_STATS 1 -#endif - -/** - * ETHARP_STATS==1: Enable etharp stats. - */ -#ifndef ETHARP_STATS -#define ETHARP_STATS (LWIP_ARP) -#endif - -/** - * IP_STATS==1: Enable IP stats. - */ -#ifndef IP_STATS -#define IP_STATS 1 -#endif - -/** - * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is - * on if using either frag or reass. - */ -#ifndef IPFRAG_STATS -#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) -#endif - -/** - * ICMP_STATS==1: Enable ICMP stats. - */ -#ifndef ICMP_STATS -#define ICMP_STATS 1 -#endif - -/** - * IGMP_STATS==1: Enable IGMP stats. - */ -#ifndef IGMP_STATS -#define IGMP_STATS (LWIP_IGMP) -#endif - -/** - * UDP_STATS==1: Enable UDP stats. Default is on if - * UDP enabled, otherwise off. - */ -#ifndef UDP_STATS -#define UDP_STATS (LWIP_UDP) -#endif - -/** - * TCP_STATS==1: Enable TCP stats. Default is on if TCP - * enabled, otherwise off. - */ -#ifndef TCP_STATS -#define TCP_STATS (LWIP_TCP) -#endif - -/** - * MEM_STATS==1: Enable mem.c stats. - */ -#ifndef MEM_STATS -#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) -#endif - -/** - * MEMP_STATS==1: Enable memp.c pool stats. - */ -#ifndef MEMP_STATS -#define MEMP_STATS (MEMP_MEM_MALLOC == 0) -#endif - -/** - * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). - */ -#ifndef SYS_STATS -#define SYS_STATS (NO_SYS == 0) -#endif - -#else - -#define LINK_STATS 0 -#define IP_STATS 0 -#define IPFRAG_STATS 0 -#define ICMP_STATS 0 -#define IGMP_STATS 0 -#define UDP_STATS 0 -#define TCP_STATS 0 -#define MEM_STATS 0 -#define MEMP_STATS 0 -#define SYS_STATS 0 -#define LWIP_STATS_DISPLAY 0 - -#endif /* LWIP_STATS */ - -/* - --------------------------------- - ---------- PPP options ---------- - --------------------------------- -*/ -/** - * PPP_SUPPORT==1: Enable PPP. - */ -#ifndef PPP_SUPPORT -#define PPP_SUPPORT 0 -#endif - -/** - * PPPOE_SUPPORT==1: Enable PPP Over Ethernet - */ -#ifndef PPPOE_SUPPORT -#define PPPOE_SUPPORT 0 -#endif - -/** - * PPPOS_SUPPORT==1: Enable PPP Over Serial - */ -#ifndef PPPOS_SUPPORT -#define PPPOS_SUPPORT PPP_SUPPORT -#endif - -#if PPP_SUPPORT - -/** - * NUM_PPP: Max PPP sessions. - */ -#ifndef NUM_PPP -#define NUM_PPP 1 -#endif - -/** - * PAP_SUPPORT==1: Support PAP. - */ -#ifndef PAP_SUPPORT -#define PAP_SUPPORT 0 -#endif - -/** - * CHAP_SUPPORT==1: Support CHAP. - */ -#ifndef CHAP_SUPPORT -#define CHAP_SUPPORT 0 -#endif - -/** - * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! - */ -#ifndef MSCHAP_SUPPORT -#define MSCHAP_SUPPORT 0 -#endif - -/** - * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! - */ -#ifndef CBCP_SUPPORT -#define CBCP_SUPPORT 0 -#endif - -/** - * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! - */ -#ifndef CCP_SUPPORT -#define CCP_SUPPORT 0 -#endif - -/** - * VJ_SUPPORT==1: Support VJ header compression. - */ -#ifndef VJ_SUPPORT -#define VJ_SUPPORT 0 -#endif - -/** - * MD5_SUPPORT==1: Support MD5 (see also CHAP). - */ -#ifndef MD5_SUPPORT -#define MD5_SUPPORT 0 -#endif - -/* - * Timeouts - */ -#ifndef FSM_DEFTIMEOUT -#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ -#endif - -#ifndef FSM_DEFMAXTERMREQS -#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ -#endif - -#ifndef FSM_DEFMAXCONFREQS -#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ -#endif - -#ifndef FSM_DEFMAXNAKLOOPS -#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ -#endif - -#ifndef UPAP_DEFTIMEOUT -#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ -#endif - -#ifndef UPAP_DEFREQTIME -#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ -#endif - -#ifndef CHAP_DEFTIMEOUT -#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ -#endif - -#ifndef CHAP_DEFTRANSMITS -#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ -#endif - -/* Interval in seconds between keepalive echo requests, 0 to disable. */ -#ifndef LCP_ECHOINTERVAL -#define LCP_ECHOINTERVAL 0 -#endif - -/* Number of unanswered echo requests before failure. */ -#ifndef LCP_MAXECHOFAILS -#define LCP_MAXECHOFAILS 3 -#endif - -/* Max Xmit idle time (in jiffies) before resend flag char. */ -#ifndef PPP_MAXIDLEFLAG -#define PPP_MAXIDLEFLAG 100 -#endif - -/* - * Packet sizes - * - * Note - lcp shouldn't be allowed to negotiate stuff outside these - * limits. See lcp.h in the pppd directory. - * (XXX - these constants should simply be shared by lcp.c instead - * of living in lcp.h) - */ -#define PPP_MTU 1500 /* Default MTU (size of Info field) */ -#ifndef PPP_MAXMTU -/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ -#define PPP_MAXMTU 1500 /* Largest MTU we allow */ -#endif -#define PPP_MINMTU 64 -#define PPP_MRU 1500 /* default MRU = max length of info field */ -#define PPP_MAXMRU 1500 /* Largest MRU we allow */ -#ifndef PPP_DEFMRU -#define PPP_DEFMRU 296 /* Try for this */ -#endif -#define PPP_MINMRU 128 /* No MRUs below this */ - -#ifndef MAXNAMELEN -#define MAXNAMELEN 256 /* max length of hostname or name for auth */ -#endif -#ifndef MAXSECRETLEN -#define MAXSECRETLEN 256 /* max length of password or secret */ -#endif - -#endif /* PPP_SUPPORT */ - -/* - -------------------------------------- - ---------- Checksum options ---------- - -------------------------------------- -*/ -/** - * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. - */ -#ifndef CHECKSUM_GEN_IP -#define CHECKSUM_GEN_IP 1 -#endif - -/** - * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. - */ -#ifndef CHECKSUM_GEN_UDP -#define CHECKSUM_GEN_UDP 1 -#endif - -/** - * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. - */ -#ifndef CHECKSUM_GEN_TCP -#define CHECKSUM_GEN_TCP 1 -#endif - -/** - * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. - */ -#ifndef CHECKSUM_CHECK_IP -#define CHECKSUM_CHECK_IP 1 -#endif - -/** - * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. - */ -#ifndef CHECKSUM_CHECK_UDP -#define CHECKSUM_CHECK_UDP 1 -#endif - -/** - * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. - */ -#ifndef CHECKSUM_CHECK_TCP -#define CHECKSUM_CHECK_TCP 1 -#endif - -/* - --------------------------------------- - ---------- Debugging options ---------- - --------------------------------------- -*/ -/** - * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is - * compared against this value. If it is smaller, then debugging - * messages are written. - */ -#ifndef LWIP_DBG_MIN_LEVEL -#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL -#endif - -/** - * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable - * debug messages of certain types. - */ -#ifndef LWIP_DBG_TYPES_ON -#define LWIP_DBG_TYPES_ON LWIP_DBG_ON -#endif - -/** - * ETHARP_DEBUG: Enable debugging in etharp.c. - */ -#ifndef ETHARP_DEBUG -#define ETHARP_DEBUG LWIP_DBG_OFF -#endif - -/** - * NETIF_DEBUG: Enable debugging in netif.c. - */ -#ifndef NETIF_DEBUG -#define NETIF_DEBUG LWIP_DBG_OFF -#endif - -/** - * PBUF_DEBUG: Enable debugging in pbuf.c. - */ -#ifndef PBUF_DEBUG -#define PBUF_DEBUG LWIP_DBG_OFF -#endif - -/** - * API_LIB_DEBUG: Enable debugging in api_lib.c. - */ -#ifndef API_LIB_DEBUG -#define API_LIB_DEBUG LWIP_DBG_OFF -#endif - -/** - * API_MSG_DEBUG: Enable debugging in api_msg.c. - */ -#ifndef API_MSG_DEBUG -#define API_MSG_DEBUG LWIP_DBG_OFF -#endif - -/** - * SOCKETS_DEBUG: Enable debugging in sockets.c. - */ -#ifndef SOCKETS_DEBUG -#define SOCKETS_DEBUG LWIP_DBG_OFF -#endif - -/** - * ICMP_DEBUG: Enable debugging in icmp.c. - */ -#ifndef ICMP_DEBUG -#define ICMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * IGMP_DEBUG: Enable debugging in igmp.c. - */ -#ifndef IGMP_DEBUG -#define IGMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * INET_DEBUG: Enable debugging in inet.c. - */ -#ifndef INET_DEBUG -#define INET_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP_DEBUG: Enable debugging for IP. - */ -#ifndef IP_DEBUG -#define IP_DEBUG LWIP_DBG_OFF -#endif - -/** - * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. - */ -#ifndef IP_REASS_DEBUG -#define IP_REASS_DEBUG LWIP_DBG_OFF -#endif - -/** - * RAW_DEBUG: Enable debugging in raw.c. - */ -#ifndef RAW_DEBUG -#define RAW_DEBUG LWIP_DBG_OFF -#endif - -/** - * MEM_DEBUG: Enable debugging in mem.c. - */ -#ifndef MEM_DEBUG -#define MEM_DEBUG LWIP_DBG_OFF -#endif - -/** - * MEMP_DEBUG: Enable debugging in memp.c. - */ -#ifndef MEMP_DEBUG -#define MEMP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SYS_DEBUG: Enable debugging in sys.c. - */ -#ifndef SYS_DEBUG -#define SYS_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_DEBUG: Enable debugging for TCP. - */ -#ifndef TCP_DEBUG -#define TCP_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. - */ -#ifndef TCP_INPUT_DEBUG -#define TCP_INPUT_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. - */ -#ifndef TCP_FR_DEBUG -#define TCP_FR_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit - * timeout. - */ -#ifndef TCP_RTO_DEBUG -#define TCP_RTO_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. - */ -#ifndef TCP_CWND_DEBUG -#define TCP_CWND_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. - */ -#ifndef TCP_WND_DEBUG -#define TCP_WND_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. - */ -#ifndef TCP_OUTPUT_DEBUG -#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. - */ -#ifndef TCP_RST_DEBUG -#define TCP_RST_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. - */ -#ifndef TCP_QLEN_DEBUG -#define TCP_QLEN_DEBUG LWIP_DBG_OFF -#endif - -/** - * UDP_DEBUG: Enable debugging in UDP. - */ -#ifndef UDP_DEBUG -#define UDP_DEBUG LWIP_DBG_OFF -#endif - -/** - * TCPIP_DEBUG: Enable debugging in tcpip.c. - */ -#ifndef TCPIP_DEBUG -#define TCPIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * PPP_DEBUG: Enable debugging for PPP. - */ -#ifndef PPP_DEBUG -#define PPP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SLIP_DEBUG: Enable debugging in slipif.c. - */ -#ifndef SLIP_DEBUG -#define SLIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * DHCP_DEBUG: Enable debugging in dhcp.c. - */ -#ifndef DHCP_DEBUG -#define DHCP_DEBUG LWIP_DBG_OFF -#endif - -/** - * AUTOIP_DEBUG: Enable debugging in autoip.c. - */ -#ifndef AUTOIP_DEBUG -#define AUTOIP_DEBUG LWIP_DBG_OFF -#endif - -/** - * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. - */ -#ifndef SNMP_MSG_DEBUG -#define SNMP_MSG_DEBUG LWIP_DBG_OFF -#endif - -/** - * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. - */ -#ifndef SNMP_MIB_DEBUG -#define SNMP_MIB_DEBUG LWIP_DBG_OFF -#endif - -/** - * DNS_DEBUG: Enable debugging for DNS. - */ -#ifndef DNS_DEBUG -#define DNS_DEBUG LWIP_DBG_OFF -#endif - -#endif /* __LWIP_OPT_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/pbuf.h b/components/net/lwip-1.3.2/src/include/lwip/pbuf.h deleted file mode 100644 index 8380f65da7..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/pbuf.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __LWIP_PBUF_H__ -#define __LWIP_PBUF_H__ - -#include "lwip/opt.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PBUF_TRANSPORT_HLEN 20 -#define PBUF_IP_HLEN 20 - -typedef enum { - PBUF_TRANSPORT, - PBUF_IP, - PBUF_LINK, - PBUF_RAW -} pbuf_layer; - -typedef enum { - PBUF_RAM, /* pbuf data is stored in RAM */ - PBUF_ROM, /* pbuf data is stored in ROM */ - PBUF_REF, /* pbuf comes from the pbuf pool */ - PBUF_POOL /* pbuf payload refers to RAM */ -} pbuf_type; - - -/** indicates this packet's data should be immediately passed to the application */ -#define PBUF_FLAG_PUSH 0x01U - -struct pbuf { - /** next pbuf in singly linked pbuf chain */ - struct pbuf *next; - - /** pointer to the actual data in the buffer */ - void *payload; - - /** - * total length of this buffer and all next buffers in chain - * belonging to the same packet. - * - * For non-queue packet chains this is the invariant: - * p->tot_len == p->len + (p->next? p->next->tot_len: 0) - */ - u16_t tot_len; - - /** length of this buffer */ - u16_t len; - - /** pbuf_type as u8_t instead of enum to save space */ - u8_t /*pbuf_type*/ type; - - /** misc flags */ - u8_t flags; - - /** - * the reference count always equals the number of pointers - * that refer to this pbuf. This can be pointers from an application, - * the stack itself, or pbuf->next pointers from a chain. - */ - u16_t ref; - -}; - -/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ -#define pbuf_init() - -struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_type type); -void pbuf_realloc(struct pbuf *p, u16_t size); -u8_t pbuf_header(struct pbuf *p, s16_t header_size); -void pbuf_ref(struct pbuf *p); -void pbuf_ref_chain(struct pbuf *p); -u8_t pbuf_free(struct pbuf *p); -u8_t pbuf_clen(struct pbuf *p); -void pbuf_cat(struct pbuf *head, struct pbuf *tail); -void pbuf_chain(struct pbuf *head, struct pbuf *tail); -struct pbuf *pbuf_dechain(struct pbuf *p); -err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from); -u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset); -err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); -struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_PBUF_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/raw.h b/components/net/lwip-1.3.2/src/include/lwip/raw.h deleted file mode 100644 index 20b0a11bbe..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/raw.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_RAW_H__ -#define __LWIP_RAW_H__ - -#include "lwip/opt.h" - -#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/ip_addr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct raw_pcb { -/* Common members of all PCB types */ - IP_PCB; - - struct raw_pcb *next; - - u8_t protocol; - - /* receive callback function - * @param arg user supplied argument (raw_pcb.recv_arg) - * @param pcb the raw_pcb which received data - * @param p the packet buffer that was received - * @param addr the remote IP address from which the packet was received - * @return 1 if the packet was 'eaten' (aka. deleted), - * 0 if the packet lives on - * If returning 1, the callback is responsible for freeing the pbuf - * if it's not used any more. - */ - u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, - struct ip_addr *addr); - /* user-supplied argument for the recv callback */ - void *recv_arg; -}; - -/* The following functions is the application layer interface to the - RAW code. */ -struct raw_pcb * raw_new (u8_t proto); -void raw_remove (struct raw_pcb *pcb); -err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); -err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); - -void raw_recv (struct raw_pcb *pcb, - u8_t (* recv)(void *arg, struct raw_pcb *pcb, - struct pbuf *p, - struct ip_addr *addr), - void *recv_arg); -err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); -err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); - -/* The following functions are the lower layer interface to RAW. */ -u8_t raw_input (struct pbuf *p, struct netif *inp); -#define raw_init() /* Compatibility define, not init needed. */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_RAW */ - -#endif /* __LWIP_RAW_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/snmp.h b/components/net/lwip-1.3.2/src/include/lwip/snmp.h deleted file mode 100644 index dd03d5d70e..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/snmp.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (c) 2001, 2002 Leon Woestenberg - * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Leon Woestenberg - * - */ -#ifndef __LWIP_SNMP_H__ -#define __LWIP_SNMP_H__ - -#include "lwip/opt.h" -#include "lwip/netif.h" -#include "lwip/udp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @see RFC1213, "MIB-II, 6. Definitions" - */ -enum snmp_ifType { - snmp_ifType_other=1, /* none of the following */ - snmp_ifType_regular1822, - snmp_ifType_hdh1822, - snmp_ifType_ddn_x25, - snmp_ifType_rfc877_x25, - snmp_ifType_ethernet_csmacd, - snmp_ifType_iso88023_csmacd, - snmp_ifType_iso88024_tokenBus, - snmp_ifType_iso88025_tokenRing, - snmp_ifType_iso88026_man, - snmp_ifType_starLan, - snmp_ifType_proteon_10Mbit, - snmp_ifType_proteon_80Mbit, - snmp_ifType_hyperchannel, - snmp_ifType_fddi, - snmp_ifType_lapb, - snmp_ifType_sdlc, - snmp_ifType_ds1, /* T-1 */ - snmp_ifType_e1, /* european equiv. of T-1 */ - snmp_ifType_basicISDN, - snmp_ifType_primaryISDN, /* proprietary serial */ - snmp_ifType_propPointToPointSerial, - snmp_ifType_ppp, - snmp_ifType_softwareLoopback, - snmp_ifType_eon, /* CLNP over IP [11] */ - snmp_ifType_ethernet_3Mbit, - snmp_ifType_nsip, /* XNS over IP */ - snmp_ifType_slip, /* generic SLIP */ - snmp_ifType_ultra, /* ULTRA technologies */ - snmp_ifType_ds3, /* T-3 */ - snmp_ifType_sip, /* SMDS */ - snmp_ifType_frame_relay -}; - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -/** SNMP "sysuptime" Interval */ -#define SNMP_SYSUPTIME_INTERVAL 10 - -/** fixed maximum length for object identifier type */ -#define LWIP_SNMP_OBJ_ID_LEN 32 - -/** internal object identifier representation */ -struct snmp_obj_id -{ - u8_t len; - s32_t id[LWIP_SNMP_OBJ_ID_LEN]; -}; - -/* system */ -void snmp_set_sysdesr(u8_t* str, u8_t* len); -void snmp_set_sysobjid(struct snmp_obj_id *oid); -void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); -void snmp_inc_sysuptime(void); -void snmp_add_sysuptime(u32_t value); -void snmp_get_sysuptime(u32_t *value); -void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); -void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); -void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); - -/* network interface */ -void snmp_add_ifinoctets(struct netif *ni, u32_t value); -void snmp_inc_ifinucastpkts(struct netif *ni); -void snmp_inc_ifinnucastpkts(struct netif *ni); -void snmp_inc_ifindiscards(struct netif *ni); -void snmp_add_ifoutoctets(struct netif *ni, u32_t value); -void snmp_inc_ifoutucastpkts(struct netif *ni); -void snmp_inc_ifoutnucastpkts(struct netif *ni); -void snmp_inc_ifoutdiscards(struct netif *ni); -void snmp_inc_iflist(void); -void snmp_dec_iflist(void); - -/* ARP (for atTable and ipNetToMediaTable) */ -void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip); -void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip); - -/* IP */ -void snmp_inc_ipinreceives(void); -void snmp_inc_ipinhdrerrors(void); -void snmp_inc_ipinaddrerrors(void); -void snmp_inc_ipforwdatagrams(void); -void snmp_inc_ipinunknownprotos(void); -void snmp_inc_ipindiscards(void); -void snmp_inc_ipindelivers(void); -void snmp_inc_ipoutrequests(void); -void snmp_inc_ipoutdiscards(void); -void snmp_inc_ipoutnoroutes(void); -void snmp_inc_ipreasmreqds(void); -void snmp_inc_ipreasmoks(void); -void snmp_inc_ipreasmfails(void); -void snmp_inc_ipfragoks(void); -void snmp_inc_ipfragfails(void); -void snmp_inc_ipfragcreates(void); -void snmp_inc_iproutingdiscards(void); -void snmp_insert_ipaddridx_tree(struct netif *ni); -void snmp_delete_ipaddridx_tree(struct netif *ni); -void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); -void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); - -/* ICMP */ -void snmp_inc_icmpinmsgs(void); -void snmp_inc_icmpinerrors(void); -void snmp_inc_icmpindestunreachs(void); -void snmp_inc_icmpintimeexcds(void); -void snmp_inc_icmpinparmprobs(void); -void snmp_inc_icmpinsrcquenchs(void); -void snmp_inc_icmpinredirects(void); -void snmp_inc_icmpinechos(void); -void snmp_inc_icmpinechoreps(void); -void snmp_inc_icmpintimestamps(void); -void snmp_inc_icmpintimestampreps(void); -void snmp_inc_icmpinaddrmasks(void); -void snmp_inc_icmpinaddrmaskreps(void); -void snmp_inc_icmpoutmsgs(void); -void snmp_inc_icmpouterrors(void); -void snmp_inc_icmpoutdestunreachs(void); -void snmp_inc_icmpouttimeexcds(void); -void snmp_inc_icmpoutparmprobs(void); -void snmp_inc_icmpoutsrcquenchs(void); -void snmp_inc_icmpoutredirects(void); -void snmp_inc_icmpoutechos(void); -void snmp_inc_icmpoutechoreps(void); -void snmp_inc_icmpouttimestamps(void); -void snmp_inc_icmpouttimestampreps(void); -void snmp_inc_icmpoutaddrmasks(void); -void snmp_inc_icmpoutaddrmaskreps(void); - -/* TCP */ -void snmp_inc_tcpactiveopens(void); -void snmp_inc_tcppassiveopens(void); -void snmp_inc_tcpattemptfails(void); -void snmp_inc_tcpestabresets(void); -void snmp_inc_tcpinsegs(void); -void snmp_inc_tcpoutsegs(void); -void snmp_inc_tcpretranssegs(void); -void snmp_inc_tcpinerrs(void); -void snmp_inc_tcpoutrsts(void); - -/* UDP */ -void snmp_inc_udpindatagrams(void); -void snmp_inc_udpnoports(void); -void snmp_inc_udpinerrors(void); -void snmp_inc_udpoutdatagrams(void); -void snmp_insert_udpidx_tree(struct udp_pcb *pcb); -void snmp_delete_udpidx_tree(struct udp_pcb *pcb); - -/* SNMP */ -void snmp_inc_snmpinpkts(void); -void snmp_inc_snmpoutpkts(void); -void snmp_inc_snmpinbadversions(void); -void snmp_inc_snmpinbadcommunitynames(void); -void snmp_inc_snmpinbadcommunityuses(void); -void snmp_inc_snmpinasnparseerrs(void); -void snmp_inc_snmpintoobigs(void); -void snmp_inc_snmpinnosuchnames(void); -void snmp_inc_snmpinbadvalues(void); -void snmp_inc_snmpinreadonlys(void); -void snmp_inc_snmpingenerrs(void); -void snmp_add_snmpintotalreqvars(u8_t value); -void snmp_add_snmpintotalsetvars(u8_t value); -void snmp_inc_snmpingetrequests(void); -void snmp_inc_snmpingetnexts(void); -void snmp_inc_snmpinsetrequests(void); -void snmp_inc_snmpingetresponses(void); -void snmp_inc_snmpintraps(void); -void snmp_inc_snmpouttoobigs(void); -void snmp_inc_snmpoutnosuchnames(void); -void snmp_inc_snmpoutbadvalues(void); -void snmp_inc_snmpoutgenerrs(void); -void snmp_inc_snmpoutgetrequests(void); -void snmp_inc_snmpoutgetnexts(void); -void snmp_inc_snmpoutsetrequests(void); -void snmp_inc_snmpoutgetresponses(void); -void snmp_inc_snmpouttraps(void); -void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); -void snmp_set_snmpenableauthentraps(u8_t *value); -void snmp_get_snmpenableauthentraps(u8_t *value); - -/* LWIP_SNMP support not available */ -/* define everything to be empty */ -#else - -/* system */ -#define snmp_set_sysdesr(str, len) -#define snmp_set_sysobjid(oid); -#define snmp_get_sysobjid_ptr(oid) -#define snmp_inc_sysuptime() -#define snmp_add_sysuptime(value) -#define snmp_get_sysuptime(value) -#define snmp_set_syscontact(ocstr, ocstrlen); -#define snmp_set_sysname(ocstr, ocstrlen); -#define snmp_set_syslocation(ocstr, ocstrlen); - -/* network interface */ -#define snmp_add_ifinoctets(ni,value) -#define snmp_inc_ifinucastpkts(ni) -#define snmp_inc_ifinnucastpkts(ni) -#define snmp_inc_ifindiscards(ni) -#define snmp_add_ifoutoctets(ni,value) -#define snmp_inc_ifoutucastpkts(ni) -#define snmp_inc_ifoutnucastpkts(ni) -#define snmp_inc_ifoutdiscards(ni) -#define snmp_inc_iflist() -#define snmp_dec_iflist() - -/* ARP */ -#define snmp_insert_arpidx_tree(ni,ip) -#define snmp_delete_arpidx_tree(ni,ip) - -/* IP */ -#define snmp_inc_ipinreceives() -#define snmp_inc_ipinhdrerrors() -#define snmp_inc_ipinaddrerrors() -#define snmp_inc_ipforwdatagrams() -#define snmp_inc_ipinunknownprotos() -#define snmp_inc_ipindiscards() -#define snmp_inc_ipindelivers() -#define snmp_inc_ipoutrequests() -#define snmp_inc_ipoutdiscards() -#define snmp_inc_ipoutnoroutes() -#define snmp_inc_ipreasmreqds() -#define snmp_inc_ipreasmoks() -#define snmp_inc_ipreasmfails() -#define snmp_inc_ipfragoks() -#define snmp_inc_ipfragfails() -#define snmp_inc_ipfragcreates() -#define snmp_inc_iproutingdiscards() -#define snmp_insert_ipaddridx_tree(ni) -#define snmp_delete_ipaddridx_tree(ni) -#define snmp_insert_iprteidx_tree(dflt, ni) -#define snmp_delete_iprteidx_tree(dflt, ni) - -/* ICMP */ -#define snmp_inc_icmpinmsgs() -#define snmp_inc_icmpinerrors() -#define snmp_inc_icmpindestunreachs() -#define snmp_inc_icmpintimeexcds() -#define snmp_inc_icmpinparmprobs() -#define snmp_inc_icmpinsrcquenchs() -#define snmp_inc_icmpinredirects() -#define snmp_inc_icmpinechos() -#define snmp_inc_icmpinechoreps() -#define snmp_inc_icmpintimestamps() -#define snmp_inc_icmpintimestampreps() -#define snmp_inc_icmpinaddrmasks() -#define snmp_inc_icmpinaddrmaskreps() -#define snmp_inc_icmpoutmsgs() -#define snmp_inc_icmpouterrors() -#define snmp_inc_icmpoutdestunreachs() -#define snmp_inc_icmpouttimeexcds() -#define snmp_inc_icmpoutparmprobs() -#define snmp_inc_icmpoutsrcquenchs() -#define snmp_inc_icmpoutredirects() -#define snmp_inc_icmpoutechos() -#define snmp_inc_icmpoutechoreps() -#define snmp_inc_icmpouttimestamps() -#define snmp_inc_icmpouttimestampreps() -#define snmp_inc_icmpoutaddrmasks() -#define snmp_inc_icmpoutaddrmaskreps() -/* TCP */ -#define snmp_inc_tcpactiveopens() -#define snmp_inc_tcppassiveopens() -#define snmp_inc_tcpattemptfails() -#define snmp_inc_tcpestabresets() -#define snmp_inc_tcpinsegs() -#define snmp_inc_tcpoutsegs() -#define snmp_inc_tcpretranssegs() -#define snmp_inc_tcpinerrs() -#define snmp_inc_tcpoutrsts() - -/* UDP */ -#define snmp_inc_udpindatagrams() -#define snmp_inc_udpnoports() -#define snmp_inc_udpinerrors() -#define snmp_inc_udpoutdatagrams() -#define snmp_insert_udpidx_tree(pcb) -#define snmp_delete_udpidx_tree(pcb) - -/* SNMP */ -#define snmp_inc_snmpinpkts() -#define snmp_inc_snmpoutpkts() -#define snmp_inc_snmpinbadversions() -#define snmp_inc_snmpinbadcommunitynames() -#define snmp_inc_snmpinbadcommunityuses() -#define snmp_inc_snmpinasnparseerrs() -#define snmp_inc_snmpintoobigs() -#define snmp_inc_snmpinnosuchnames() -#define snmp_inc_snmpinbadvalues() -#define snmp_inc_snmpinreadonlys() -#define snmp_inc_snmpingenerrs() -#define snmp_add_snmpintotalreqvars(value) -#define snmp_add_snmpintotalsetvars(value) -#define snmp_inc_snmpingetrequests() -#define snmp_inc_snmpingetnexts() -#define snmp_inc_snmpinsetrequests() -#define snmp_inc_snmpingetresponses() -#define snmp_inc_snmpintraps() -#define snmp_inc_snmpouttoobigs() -#define snmp_inc_snmpoutnosuchnames() -#define snmp_inc_snmpoutbadvalues() -#define snmp_inc_snmpoutgenerrs() -#define snmp_inc_snmpoutgetrequests() -#define snmp_inc_snmpoutgetnexts() -#define snmp_inc_snmpoutsetrequests() -#define snmp_inc_snmpoutgetresponses() -#define snmp_inc_snmpouttraps() -#define snmp_get_snmpgrpid_ptr(oid) -#define snmp_set_snmpenableauthentraps(value) -#define snmp_get_snmpenableauthentraps(value) - -#endif /* LWIP_SNMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_SNMP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/snmp_asn1.h b/components/net/lwip-1.3.2/src/include/lwip/snmp_asn1.h deleted file mode 100644 index 8a602881fe..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/snmp_asn1.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * @file - * Abstract Syntax Notation One (ISO 8824, 8825) codec. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#ifndef __LWIP_SNMP_ASN1_H__ -#define __LWIP_SNMP_ASN1_H__ - -#include "lwip/opt.h" -#include "lwip/err.h" -#include "lwip/pbuf.h" -#include "lwip/snmp.h" - -#if LWIP_SNMP - -#ifdef __cplusplus -extern "C" { -#endif - -#define SNMP_ASN1_UNIV (!0x80 | !0x40) -#define SNMP_ASN1_APPLIC (!0x80 | 0x40) -#define SNMP_ASN1_CONTXT ( 0x80 | !0x40) - -#define SNMP_ASN1_CONSTR (0x20) -#define SNMP_ASN1_PRIMIT (!0x20) - -/* universal tags */ -#define SNMP_ASN1_INTEG 2 -#define SNMP_ASN1_OC_STR 4 -#define SNMP_ASN1_NUL 5 -#define SNMP_ASN1_OBJ_ID 6 -#define SNMP_ASN1_SEQ 16 - -/* application specific (SNMP) tags */ -#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ -#define SNMP_ASN1_COUNTER 1 /* u32_t */ -#define SNMP_ASN1_GAUGE 2 /* u32_t */ -#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ -#define SNMP_ASN1_OPAQUE 4 /* octet string */ - -/* context specific (SNMP) tags */ -#define SNMP_ASN1_PDU_GET_REQ 0 -#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 -#define SNMP_ASN1_PDU_GET_RESP 2 -#define SNMP_ASN1_PDU_SET_REQ 3 -#define SNMP_ASN1_PDU_TRAP 4 - -err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); -err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); -err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); -err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); -err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); -err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); - -void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); -void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); -void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); -void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); -err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); -err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); -err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value); -err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value); -err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); -err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* __LWIP_SNMP_ASN1_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/snmp_msg.h b/components/net/lwip-1.3.2/src/include/lwip/snmp_msg.h deleted file mode 100644 index b2f69c4be2..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/snmp_msg.h +++ /dev/null @@ -1,311 +0,0 @@ -/** - * @file - * SNMP Agent message handling structures. - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#ifndef __LWIP_SNMP_MSG_H__ -#define __LWIP_SNMP_MSG_H__ - -#include "lwip/opt.h" -#include "lwip/snmp.h" -#include "lwip/snmp_structs.h" - -#if LWIP_SNMP - -#if SNMP_PRIVATE_MIB -#include "private_mib.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* The listen port of the SNMP agent. Clients have to make their requests to - this port. Most standard clients won't work if you change this! */ -#ifndef SNMP_IN_PORT -#define SNMP_IN_PORT 161 -#endif -/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't - work if you change this! */ -#ifndef SNMP_TRAP_PORT -#define SNMP_TRAP_PORT 162 -#endif - -#define SNMP_ES_NOERROR 0 -#define SNMP_ES_TOOBIG 1 -#define SNMP_ES_NOSUCHNAME 2 -#define SNMP_ES_BADVALUE 3 -#define SNMP_ES_READONLY 4 -#define SNMP_ES_GENERROR 5 - -#define SNMP_GENTRAP_COLDSTART 0 -#define SNMP_GENTRAP_WARMSTART 1 -#define SNMP_GENTRAP_AUTHFAIL 4 -#define SNMP_GENTRAP_ENTERPRISESPC 6 - -struct snmp_varbind -{ - /* next pointer, NULL for last in list */ - struct snmp_varbind *next; - /* previous pointer, NULL for first in list */ - struct snmp_varbind *prev; - - /* object identifier length (in s32_t) */ - u8_t ident_len; - /* object identifier array */ - s32_t *ident; - - /* object value ASN1 type */ - u8_t value_type; - /* object value length (in u8_t) */ - u8_t value_len; - /* object value */ - void *value; - - /* encoding varbind seq length length */ - u8_t seqlenlen; - /* encoding object identifier length length */ - u8_t olenlen; - /* encoding object value length length */ - u8_t vlenlen; - /* encoding varbind seq length */ - u16_t seqlen; - /* encoding object identifier length */ - u16_t olen; - /* encoding object value length */ - u16_t vlen; -}; - -struct snmp_varbind_root -{ - struct snmp_varbind *head; - struct snmp_varbind *tail; - /* number of variable bindings in list */ - u8_t count; - /* encoding varbind-list seq length length */ - u8_t seqlenlen; - /* encoding varbind-list seq length */ - u16_t seqlen; -}; - -/** output response message header length fields */ -struct snmp_resp_header_lengths -{ - /* encoding error-index length length */ - u8_t erridxlenlen; - /* encoding error-status length length */ - u8_t errstatlenlen; - /* encoding request id length length */ - u8_t ridlenlen; - /* encoding pdu length length */ - u8_t pdulenlen; - /* encoding community length length */ - u8_t comlenlen; - /* encoding version length length */ - u8_t verlenlen; - /* encoding sequence length length */ - u8_t seqlenlen; - - /* encoding error-index length */ - u16_t erridxlen; - /* encoding error-status length */ - u16_t errstatlen; - /* encoding request id length */ - u16_t ridlen; - /* encoding pdu length */ - u16_t pdulen; - /* encoding community length */ - u16_t comlen; - /* encoding version length */ - u16_t verlen; - /* encoding sequence length */ - u16_t seqlen; -}; - -/** output response message header length fields */ -struct snmp_trap_header_lengths -{ - /* encoding timestamp length length */ - u8_t tslenlen; - /* encoding specific-trap length length */ - u8_t strplenlen; - /* encoding generic-trap length length */ - u8_t gtrplenlen; - /* encoding agent-addr length length */ - u8_t aaddrlenlen; - /* encoding enterprise-id length length */ - u8_t eidlenlen; - /* encoding pdu length length */ - u8_t pdulenlen; - /* encoding community length length */ - u8_t comlenlen; - /* encoding version length length */ - u8_t verlenlen; - /* encoding sequence length length */ - u8_t seqlenlen; - - /* encoding timestamp length */ - u16_t tslen; - /* encoding specific-trap length */ - u16_t strplen; - /* encoding generic-trap length */ - u16_t gtrplen; - /* encoding agent-addr length */ - u16_t aaddrlen; - /* encoding enterprise-id length */ - u16_t eidlen; - /* encoding pdu length */ - u16_t pdulen; - /* encoding community length */ - u16_t comlen; - /* encoding version length */ - u16_t verlen; - /* encoding sequence length */ - u16_t seqlen; -}; - -/* Accepting new SNMP messages. */ -#define SNMP_MSG_EMPTY 0 -/* Search for matching object for variable binding. */ -#define SNMP_MSG_SEARCH_OBJ 1 -/* Perform SNMP operation on in-memory object. - Pass-through states, for symmetry only. */ -#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 -#define SNMP_MSG_INTERNAL_GET_VALUE 3 -#define SNMP_MSG_INTERNAL_SET_TEST 4 -#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 -#define SNMP_MSG_INTERNAL_SET_VALUE 6 -/* Perform SNMP operation on object located externally. - In theory this could be used for building a proxy agent. - Practical use is for an enterprise spc. app. gateway. */ -#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 -#define SNMP_MSG_EXTERNAL_GET_VALUE 8 -#define SNMP_MSG_EXTERNAL_SET_TEST 9 -#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 -#define SNMP_MSG_EXTERNAL_SET_VALUE 11 - -#define SNMP_COMMUNITY_STR_LEN 64 -struct snmp_msg_pstat -{ - /* lwIP local port (161) binding */ - struct udp_pcb *pcb; - /* source IP address */ - struct ip_addr sip; - /* source UDP port */ - u16_t sp; - /* request type */ - u8_t rt; - /* request ID */ - s32_t rid; - /* error status */ - s32_t error_status; - /* error index */ - s32_t error_index; - /* community name (zero terminated) */ - u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; - /* community string length (exclusive zero term) */ - u8_t com_strlen; - /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ - u8_t state; - /* saved arguments for MSG_EXTERNAL_x */ - struct mib_external_node *ext_mib_node; - struct snmp_name_ptr ext_name_ptr; - struct obj_def ext_object_def; - struct snmp_obj_id ext_oid; - /* index into input variable binding list */ - u8_t vb_idx; - /* ptr into input variable binding list */ - struct snmp_varbind *vb_ptr; - /* list of variable bindings from input */ - struct snmp_varbind_root invb; - /* list of variable bindings to output */ - struct snmp_varbind_root outvb; - /* output response lengths used in ASN encoding */ - struct snmp_resp_header_lengths rhl; -}; - -struct snmp_msg_trap -{ - /* lwIP local port (161) binding */ - struct udp_pcb *pcb; - /* destination IP address in network order */ - struct ip_addr dip; - - /* source enterprise ID (sysObjectID) */ - struct snmp_obj_id *enterprise; - /* source IP address, raw network order format */ - u8_t sip_raw[4]; - /* generic trap code */ - u32_t gen_trap; - /* specific trap code */ - u32_t spc_trap; - /* timestamp */ - u32_t ts; - /* list of variable bindings to output */ - struct snmp_varbind_root outvb; - /* output trap lengths used in ASN encoding */ - struct snmp_trap_header_lengths thl; -}; - -/** Agent Version constant, 0 = v1 oddity */ -extern const s32_t snmp_version; -/** Agent default "public" community string */ -extern const char snmp_publiccommunity[7]; - -extern struct snmp_msg_trap trap_msg; - -/** Agent setup, start listening to port 161. */ -void snmp_init(void); -void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); -void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst); - -/** Varbind-list functions. */ -struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); -void snmp_varbind_free(struct snmp_varbind *vb); -void snmp_varbind_list_free(struct snmp_varbind_root *root); -void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); -struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); - -/** Handle an internal (recv) or external (private response) event. */ -void snmp_msg_event(u8_t request_id); -err_t snmp_send_response(struct snmp_msg_pstat *m_stat); -err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); -void snmp_coldstart_trap(void); -void snmp_authfail_trap(void); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* __LWIP_SNMP_MSG_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/snmp_structs.h b/components/net/lwip-1.3.2/src/include/lwip/snmp_structs.h deleted file mode 100644 index 9f3f8a94e5..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/snmp_structs.h +++ /dev/null @@ -1,262 +0,0 @@ -/** - * @file - * Generic MIB tree structures. - * - * @todo namespace prefixes - */ - -/* - * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christiaan Simons - */ - -#ifndef __LWIP_SNMP_STRUCTS_H__ -#define __LWIP_SNMP_STRUCTS_H__ - -#include "lwip/opt.h" - -#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/snmp.h" - -#if SNMP_PRIVATE_MIB -#include "private_mib.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* MIB object instance */ -#define MIB_OBJECT_NONE 0 -#define MIB_OBJECT_SCALAR 1 -#define MIB_OBJECT_TAB 2 - -/* MIB object access */ -#define MIB_OBJECT_READ_ONLY 0 -#define MIB_OBJECT_READ_WRITE 1 -#define MIB_OBJECT_WRITE_ONLY 2 -#define MIB_OBJECT_NOT_ACCESSIBLE 3 - -/** object definition returned by (get_object_def)() */ -struct obj_def -{ - /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ - u8_t instance; - /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ - u8_t access; - /* ASN type for this object */ - u8_t asn_type; - /* value length (host length) */ - u16_t v_len; - /* length of instance part of supplied object identifier */ - u8_t id_inst_len; - /* instance part of supplied object identifier */ - s32_t *id_inst_ptr; -}; - -struct snmp_name_ptr -{ - u8_t ident_len; - s32_t *ident; -}; - -/** MIB const scalar (.0) node */ -#define MIB_NODE_SC 0x01 -/** MIB const array node */ -#define MIB_NODE_AR 0x02 -/** MIB array node (mem_malloced from RAM) */ -#define MIB_NODE_RA 0x03 -/** MIB list root node (mem_malloced from RAM) */ -#define MIB_NODE_LR 0x04 -/** MIB node for external objects */ -#define MIB_NODE_EX 0x05 - -/** node "base class" layout, the mandatory fields for a node */ -struct mib_node -{ - /** returns struct obj_def for the given object identifier */ - void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); - /** returns object value for the given object identifier, - @note the caller must allocate at least len bytes for the value */ - void (*get_value)(struct obj_def *od, u16_t len, void *value); - /** tests length and/or range BEFORE setting */ - u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); - /** sets object value, only to be called when set_test() */ - void (*set_value)(struct obj_def *od, u16_t len, void *value); - /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ - const u8_t node_type; - /* array or max list length */ - const u16_t maxlength; -}; - -/** derived node for scalars .0 index */ -typedef struct mib_node mib_scalar_node; - -/** derived node, points to a fixed size const array - of sub-identifiers plus a 'child' pointer */ -struct mib_array_node -{ - /* inherited "base class" members */ - void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); - void (* const get_value)(struct obj_def *od, u16_t len, void *value); - u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); - void (*set_value)(struct obj_def *od, u16_t len, void *value); - - const u8_t node_type; - const u16_t maxlength; - - /* aditional struct members */ - const s32_t *objid; - struct mib_node* const *nptr; -}; - -/** derived node, points to a fixed size mem_malloced array - of sub-identifiers plus a 'child' pointer */ -struct mib_ram_array_node -{ - /* inherited "base class" members */ - void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); - void (*get_value)(struct obj_def *od, u16_t len, void *value); - u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); - void (*set_value)(struct obj_def *od, u16_t len, void *value); - - u8_t node_type; - u16_t maxlength; - - /* aditional struct members */ - s32_t *objid; - struct mib_node **nptr; -}; - -struct mib_list_node -{ - struct mib_list_node *prev; - struct mib_list_node *next; - s32_t objid; - struct mib_node *nptr; -}; - -/** derived node, points to a doubly linked list - of sub-identifiers plus a 'child' pointer */ -struct mib_list_rootnode -{ - /* inherited "base class" members */ - void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); - void (*get_value)(struct obj_def *od, u16_t len, void *value); - u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); - void (*set_value)(struct obj_def *od, u16_t len, void *value); - - u8_t node_type; - u16_t maxlength; - - /* aditional struct members */ - struct mib_list_node *head; - struct mib_list_node *tail; - /* counts list nodes in list */ - u16_t count; -}; - -/** derived node, has access functions for mib object in external memory or device - using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ -struct mib_external_node -{ - /* inherited "base class" members */ - void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); - void (*get_value)(struct obj_def *od, u16_t len, void *value); - u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); - void (*set_value)(struct obj_def *od, u16_t len, void *value); - - u8_t node_type; - u16_t maxlength; - - /* aditional struct members */ - /** points to an extenal (in memory) record of some sort of addressing - information, passed to and interpreted by the funtions below */ - void* addr_inf; - /** tree levels under this node */ - u8_t tree_levels; - /** number of objects at this level */ - u16_t (*level_length)(void* addr_inf, u8_t level); - /** compares object sub identifier with external id - return zero when equal, nonzero when unequal */ - s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); - void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); - - /** async Questions */ - void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); - void (*get_value_q)(u8_t rid, struct obj_def *od); - void (*set_test_q)(u8_t rid, struct obj_def *od); - void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); - /** async Answers */ - void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); - void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); - u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); - void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); - /** async Panic Close (agent returns error reply, - e.g. used for external transaction cleanup) */ - void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); - void (*get_value_pc)(u8_t rid, struct obj_def *od); - void (*set_test_pc)(u8_t rid, struct obj_def *od); - void (*set_value_pc)(u8_t rid, struct obj_def *od); -}; - -/** export MIB tree from mib2.c */ -extern const struct mib_array_node internet; - -/** dummy function pointers for non-leaf MIB nodes from mib2.c */ -void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); -void noleafs_get_value(struct obj_def *od, u16_t len, void *value); -u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); -void noleafs_set_value(struct obj_def *od, u16_t len, void *value); - -void snmp_oidtoip(s32_t *ident, struct ip_addr *ip); -void snmp_iptooid(struct ip_addr *ip, s32_t *ident); -void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); -void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); - -struct mib_list_node* snmp_mib_ln_alloc(s32_t id); -void snmp_mib_ln_free(struct mib_list_node *ln); -struct mib_list_rootnode* snmp_mib_lrn_alloc(void); -void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); - -s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); -s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); -struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); - -struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); -struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); -u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); -u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SNMP */ - -#endif /* __LWIP_SNMP_STRUCTS_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/sockets.h b/components/net/lwip-1.3.2/src/include/lwip/sockets.h deleted file mode 100644 index 7b52e151c1..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/sockets.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -#ifndef __LWIP_SOCKETS_H__ -#define __LWIP_SOCKETS_H__ - -#include "lwip/opt.h" - -#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ - -#include /* for size_t */ - -#include "lwip/ip_addr.h" -#include "lwip/inet.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* members are in network byte order */ -struct sockaddr_in { - u8_t sin_len; - u8_t sin_family; - u16_t sin_port; - struct in_addr sin_addr; - char sin_zero[8]; -}; - -struct sockaddr { - u8_t sa_len; - u8_t sa_family; - char sa_data[14]; -}; - -#ifndef socklen_t -# define socklen_t u32_t -#endif - -/* Socket protocol types (TCP/UDP/RAW) */ -#define SOCK_STREAM 1 -#define SOCK_DGRAM 2 -#define SOCK_RAW 3 - -/* - * Option flags per-socket. These must match the SOF_ flags in ip.h! - */ -#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ -#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ -#define SO_REUSEADDR 0x0004 /* Unimplemented: allow local address reuse */ -#define SO_KEEPALIVE 0x0008 /* keep connections alive */ -#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ -#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ -#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ -#define SO_LINGER 0x0080 /* linger on close if data present */ -#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ -#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ - -#define SO_DONTLINGER ((int)(~SO_LINGER)) - -/* - * Additional options, not kept in so_options. - */ -#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ -#define SO_RCVBUF 0x1002 /* receive buffer size */ -#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ -#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ -#define SO_SNDTIMEO 0x1005 /* Unimplemented: send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ -#define SO_ERROR 0x1007 /* get error status and clear */ -#define SO_TYPE 0x1008 /* get socket type */ -#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ -#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ - - -/* - * Structure used for manipulating linger option. - */ -struct linger { - int l_onoff; /* option on/off */ - int l_linger; /* linger time */ -}; - -/* - * Level number for (get/set)sockopt() to apply to socket itself. - */ -#define SOL_SOCKET 0xfff /* options for socket level */ - - -#define AF_UNSPEC 0 -#define AF_INET 2 -#define PF_INET AF_INET -#define PF_UNSPEC AF_UNSPEC - -#define IPPROTO_IP 0 -#define IPPROTO_TCP 6 -#define IPPROTO_UDP 17 -#define IPPROTO_UDPLITE 136 - -/* Flags we can use with send and recv. */ -#define MSG_PEEK 0x01 /* Peeks at an incoming message */ -#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ -#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ -#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ -#define MSG_MORE 0x10 /* Sender will send more */ - - -/* - * Options for level IPPROTO_IP - */ -#define IP_TOS 1 -#define IP_TTL 2 - -#if LWIP_TCP -/* - * Options for level IPPROTO_TCP - */ -#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ -#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ -#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ -#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ -#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ -#endif /* LWIP_TCP */ - -#if LWIP_UDP && LWIP_UDPLITE -/* - * Options for level IPPROTO_UDPLITE - */ -#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ -#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ -#endif /* LWIP_UDP && LWIP_UDPLITE*/ - - -#if LWIP_IGMP -/* - * Options and types for UDP multicast traffic handling - */ -#define IP_ADD_MEMBERSHIP 3 -#define IP_DROP_MEMBERSHIP 4 -#define IP_MULTICAST_TTL 5 -#define IP_MULTICAST_IF 6 -#define IP_MULTICAST_LOOP 7 - -typedef struct ip_mreq { - struct in_addr imr_multiaddr; /* IP multicast address of group */ - struct in_addr imr_interface; /* local IP address of interface */ -} ip_mreq; -#endif /* LWIP_IGMP */ - -/* - * The Type of Service provides an indication of the abstract - * parameters of the quality of service desired. These parameters are - * to be used to guide the selection of the actual service parameters - * when transmitting a datagram through a particular network. Several - * networks offer service precedence, which somehow treats high - * precedence traffic as more important than other traffic (generally - * by accepting only traffic above a certain precedence at time of high - * load). The major choice is a three way tradeoff between low-delay, - * high-reliability, and high-throughput. - * The use of the Delay, Throughput, and Reliability indications may - * increase the cost (in some sense) of the service. In many networks - * better performance for one of these parameters is coupled with worse - * performance on another. Except for very unusual cases at most two - * of these three indications should be set. - */ -#define IPTOS_TOS_MASK 0x1E -#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) -#define IPTOS_LOWDELAY 0x10 -#define IPTOS_THROUGHPUT 0x08 -#define IPTOS_RELIABILITY 0x04 -#define IPTOS_LOWCOST 0x02 -#define IPTOS_MINCOST IPTOS_LOWCOST - -/* - * The Network Control precedence designation is intended to be used - * within a network only. The actual use and control of that - * designation is up to each network. The Internetwork Control - * designation is intended for use by gateway control originators only. - * If the actual use of these precedence designations is of concern to - * a particular network, it is the responsibility of that network to - * control the access to, and use of, those precedence designations. - */ -#define IPTOS_PREC_MASK 0xe0 -#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) -#define IPTOS_PREC_NETCONTROL 0xe0 -#define IPTOS_PREC_INTERNETCONTROL 0xc0 -#define IPTOS_PREC_CRITIC_ECP 0xa0 -#define IPTOS_PREC_FLASHOVERRIDE 0x80 -#define IPTOS_PREC_FLASH 0x60 -#define IPTOS_PREC_IMMEDIATE 0x40 -#define IPTOS_PREC_PRIORITY 0x20 -#define IPTOS_PREC_ROUTINE 0x00 - - -/* - * Commands for ioctlsocket(), taken from the BSD file fcntl.h. - * lwip_ioctl only supports FIONREAD and FIONBIO, for now - * - * Ioctl's have the command encoded in the lower word, - * and the size of any in or out parameters in the upper - * word. The high 2 bits of the upper word are used - * to encode the in/out status of the parameter; for now - * we restrict parameters to at most 128 bytes. - */ -#if !defined(FIONREAD) || !defined(FIONBIO) -#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ -#define IOC_VOID 0x20000000UL /* no parameters */ -#define IOC_OUT 0x40000000UL /* copy out parameters */ -#define IOC_IN 0x80000000UL /* copy in parameters */ -#define IOC_INOUT (IOC_IN|IOC_OUT) - /* 0x20000000 distinguishes new & - old ioctl's */ -#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) - -#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) - -#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) -#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ - -#ifndef FIONREAD -#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ -#endif -#ifndef FIONBIO -#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ -#endif - -/* Socket I/O Controls: unimplemented */ -#ifndef SIOCSHIWAT -#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ -#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ -#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ -#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ -#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ -#endif - -/* Socket flags: */ -#ifndef O_NONBLOCK -#define O_NONBLOCK 04000U -#endif - -/* FD_SET used for lwip_select */ -#ifndef FD_SET - #undef FD_SETSIZE - /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ - #define FD_SETSIZE MEMP_NUM_NETCONN - #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) - #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) - #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) - #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) - - typedef struct fd_set { - unsigned char fd_bits [(FD_SETSIZE+7)/8]; - } fd_set; - -#endif /* FD_SET */ - -/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided - * by your system, set this to 0 and include in cc.h */ -#ifndef LWIP_TIMEVAL_PRIVATE -#define LWIP_TIMEVAL_PRIVATE 1 -#endif - -#if LWIP_TIMEVAL_PRIVATE -struct timeval { - long tv_sec; /* seconds */ - long tv_usec; /* and microseconds */ -}; -#endif /* LWIP_TIMEVAL_PRIVATE */ - -void lwip_socket_init(void); - -int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); -int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); -int lwip_shutdown(int s, int how); -int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); -int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); -int lwip_close(int s); -int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); -int lwip_listen(int s, int backlog); -int lwip_recv(int s, void *mem, size_t len, int flags); -int lwip_read(int s, void *mem, size_t len); -int lwip_recvfrom(int s, void *mem, size_t len, int flags, - struct sockaddr *from, socklen_t *fromlen); -int lwip_send(int s, const void *dataptr, size_t size, int flags); -int lwip_sendto(int s, const void *dataptr, size_t size, int flags, - const struct sockaddr *to, socklen_t tolen); -int lwip_socket(int domain, int type, int protocol); -int lwip_write(int s, const void *dataptr, size_t size); -int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout); -int lwip_ioctl(int s, long cmd, void *argp); - -#if LWIP_COMPAT_SOCKETS -#define accept(a,b,c) lwip_accept(a,b,c) -#define bind(a,b,c) lwip_bind(a,b,c) -#define shutdown(a,b) lwip_shutdown(a,b) -#define closesocket(s) lwip_close(s) -#define connect(a,b,c) lwip_connect(a,b,c) -#define getsockname(a,b,c) lwip_getsockname(a,b,c) -#define getpeername(a,b,c) lwip_getpeername(a,b,c) -#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) -#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) -#define listen(a,b) lwip_listen(a,b) -#define recv(a,b,c,d) lwip_recv(a,b,c,d) -#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) -#define send(a,b,c,d) lwip_send(a,b,c,d) -#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) -#define socket(a,b,c) lwip_socket(a,b,c) -#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) -#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) - -#if LWIP_POSIX_SOCKETS_IO_NAMES -#define read(a,b,c) lwip_read(a,b,c) -#define write(a,b,c) lwip_write(a,b,c) -#define close(s) lwip_close(s) -#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ - -#endif /* LWIP_COMPAT_SOCKETS */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_SOCKET */ - -#endif /* __LWIP_SOCKETS_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/stats.h b/components/net/lwip-1.3.2/src/include/lwip/stats.h deleted file mode 100644 index aa179f5c00..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/stats.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_STATS_H__ -#define __LWIP_STATS_H__ - -#include "lwip/opt.h" - -#include "lwip/mem.h" -#include "lwip/memp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_STATS - -#ifndef LWIP_STATS_LARGE -#define LWIP_STATS_LARGE 0 -#endif - -#if LWIP_STATS_LARGE -#define STAT_COUNTER u32_t -#define STAT_COUNTER_F U32_F -#else -#define STAT_COUNTER u16_t -#define STAT_COUNTER_F U16_F -#endif - -struct stats_proto { - STAT_COUNTER xmit; /* Transmitted packets. */ - STAT_COUNTER recv; /* Received packets. */ - STAT_COUNTER fw; /* Forwarded packets. */ - STAT_COUNTER drop; /* Dropped packets. */ - STAT_COUNTER chkerr; /* Checksum error. */ - STAT_COUNTER lenerr; /* Invalid length error. */ - STAT_COUNTER memerr; /* Out of memory error. */ - STAT_COUNTER rterr; /* Routing error. */ - STAT_COUNTER proterr; /* Protocol error. */ - STAT_COUNTER opterr; /* Error in options. */ - STAT_COUNTER err; /* Misc error. */ - STAT_COUNTER cachehit; -}; - -struct stats_igmp { - STAT_COUNTER lenerr; /* Invalid length error. */ - STAT_COUNTER chkerr; /* Checksum error. */ - STAT_COUNTER v1_rxed; /* */ - STAT_COUNTER join_sent; /* */ - STAT_COUNTER leave_sent; /* */ - STAT_COUNTER unicast_query; /* */ - STAT_COUNTER report_sent; /* */ - STAT_COUNTER report_rxed; /* */ - STAT_COUNTER group_query_rxed; /* */ -}; - -struct stats_mem { - mem_size_t avail; - mem_size_t used; - mem_size_t max; - STAT_COUNTER err; - STAT_COUNTER illegal; -}; - -struct stats_syselem { - STAT_COUNTER used; - STAT_COUNTER max; - STAT_COUNTER err; -}; - -struct stats_sys { - struct stats_syselem sem; - struct stats_syselem mbox; -}; - -struct stats_ { -#if LINK_STATS - struct stats_proto link; -#endif -#if ETHARP_STATS - struct stats_proto etharp; -#endif -#if IPFRAG_STATS - struct stats_proto ip_frag; -#endif -#if IP_STATS - struct stats_proto ip; -#endif -#if ICMP_STATS - struct stats_proto icmp; -#endif -#if IGMP_STATS - struct stats_igmp igmp; -#endif -#if UDP_STATS - struct stats_proto udp; -#endif -#if TCP_STATS - struct stats_proto tcp; -#endif -#if MEM_STATS - struct stats_mem mem; -#endif -#if MEMP_STATS - struct stats_mem memp[MEMP_MAX]; -#endif -#if SYS_STATS - struct stats_sys sys; -#endif -}; - -extern struct stats_ lwip_stats; - -#define stats_init() /* Compatibility define, not init needed. */ - -#define STATS_INC(x) ++lwip_stats.x -#define STATS_DEC(x) --lwip_stats.x -#else -#define stats_init() -#define STATS_INC(x) -#define STATS_DEC(x) -#endif /* LWIP_STATS */ - -#if TCP_STATS -#define TCP_STATS_INC(x) STATS_INC(x) -#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") -#else -#define TCP_STATS_INC(x) -#define TCP_STATS_DISPLAY() -#endif - -#if UDP_STATS -#define UDP_STATS_INC(x) STATS_INC(x) -#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") -#else -#define UDP_STATS_INC(x) -#define UDP_STATS_DISPLAY() -#endif - -#if ICMP_STATS -#define ICMP_STATS_INC(x) STATS_INC(x) -#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") -#else -#define ICMP_STATS_INC(x) -#define ICMP_STATS_DISPLAY() -#endif - -#if IGMP_STATS -#define IGMP_STATS_INC(x) STATS_INC(x) -#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp) -#else -#define IGMP_STATS_INC(x) -#define IGMP_STATS_DISPLAY() -#endif - -#if IP_STATS -#define IP_STATS_INC(x) STATS_INC(x) -#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") -#else -#define IP_STATS_INC(x) -#define IP_STATS_DISPLAY() -#endif - -#if IPFRAG_STATS -#define IPFRAG_STATS_INC(x) STATS_INC(x) -#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") -#else -#define IPFRAG_STATS_INC(x) -#define IPFRAG_STATS_DISPLAY() -#endif - -#if ETHARP_STATS -#define ETHARP_STATS_INC(x) STATS_INC(x) -#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") -#else -#define ETHARP_STATS_INC(x) -#define ETHARP_STATS_DISPLAY() -#endif - -#if LINK_STATS -#define LINK_STATS_INC(x) STATS_INC(x) -#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") -#else -#define LINK_STATS_INC(x) -#define LINK_STATS_DISPLAY() -#endif - -#if MEM_STATS -#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y -#define MEM_STATS_INC(x) STATS_INC(mem.x) -#define MEM_STATS_INC_USED(x, y) do { lwip_stats.mem.used += y; \ - if (lwip_stats.mem.max < lwip_stats.mem.used) { \ - lwip_stats.mem.max = lwip_stats.mem.used; \ - } \ - } while(0) -#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y -#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") -#else -#define MEM_STATS_AVAIL(x, y) -#define MEM_STATS_INC(x) -#define MEM_STATS_INC_USED(x, y) -#define MEM_STATS_DEC_USED(x, y) -#define MEM_STATS_DISPLAY() -#endif - -#if MEMP_STATS -#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y -#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x) -#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x) -#define MEMP_STATS_INC_USED(x, i) do { ++lwip_stats.memp[i].used; \ - if (lwip_stats.memp[i].max < lwip_stats.memp[i].used) { \ - lwip_stats.memp[i].max = lwip_stats.memp[i].used; \ - } \ - } while(0) -#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i) -#else -#define MEMP_STATS_AVAIL(x, i, y) -#define MEMP_STATS_INC(x, i) -#define MEMP_STATS_DEC(x, i) -#define MEMP_STATS_INC_USED(x, i) -#define MEMP_STATS_DISPLAY(i) -#endif - -#if SYS_STATS -#define SYS_STATS_INC(x) STATS_INC(sys.x) -#define SYS_STATS_DEC(x) STATS_DEC(sys.x) -#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) -#else -#define SYS_STATS_INC(x) -#define SYS_STATS_DEC(x) -#define SYS_STATS_DISPLAY() -#endif - -/* Display of statistics */ -#if LWIP_STATS_DISPLAY -void stats_display(void); -void stats_display_proto(struct stats_proto *proto, char *name); -void stats_display_igmp(struct stats_igmp *igmp); -void stats_display_mem(struct stats_mem *mem, char *name); -void stats_display_memp(struct stats_mem *mem, int index); -void stats_display_sys(struct stats_sys *sys); -#else -#define stats_display() -#define stats_display_proto(proto, name) -#define stats_display_igmp(igmp) -#define stats_display_mem(mem, name) -#define stats_display_memp(mem, index) -#define stats_display_sys(sys) -#endif /* LWIP_STATS_DISPLAY */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_STATS_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/sys.h b/components/net/lwip-1.3.2/src/include/lwip/sys.h deleted file mode 100644 index 0cc84ddf1d..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/sys.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_SYS_H__ -#define __LWIP_SYS_H__ - -#include "lwip/opt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if NO_SYS - -/* For a totally minimal and standalone system, we provide null - definitions of the sys_ functions. */ -typedef u8_t sys_sem_t; -typedef u8_t sys_mbox_t; -struct sys_timeo {u8_t dummy;}; - -#define sys_init() -#define sys_timeout(m,h,a) -#define sys_untimeout(m,a) -#define sys_sem_new(c) c -#define sys_sem_signal(s) -#define sys_sem_wait(s) -#define sys_sem_wait_timeout(s,t) -#define sys_arch_sem_wait(s,t) -#define sys_sem_free(s) -#define sys_mbox_new(s) 0 -#define sys_mbox_fetch(m,d) -#define sys_mbox_tryfetch(m,d) -#define sys_mbox_post(m,d) -#define sys_mbox_trypost(m,d) -#define sys_mbox_free(m) - -#define sys_thread_new(n,t,a,s,p) - -#else /* NO_SYS */ - -/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ -#define SYS_ARCH_TIMEOUT 0xffffffffUL - -/* sys_mbox_tryfetch returns SYS_MBOX_EMPTY if appropriate. - * For now we use the same magic value, but we allow this to change in future. - */ -#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT - -#include "lwip/err.h" -#include "arch/sys_arch.h" - -typedef void (* sys_timeout_handler)(void *arg); - -struct sys_timeo { - struct sys_timeo *next; - u32_t time; - sys_timeout_handler h; - void *arg; -}; - -struct sys_timeouts { - struct sys_timeo *next; -}; - -/* sys_init() must be called before anthing else. */ -void sys_init(void); - -/* - * sys_timeout(): - * - * Schedule a timeout a specified amount of milliseconds in the - * future. When the timeout occurs, the specified timeout handler will - * be called. The handler will be passed the "arg" argument when - * called. - * - */ -void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); -void sys_untimeout(sys_timeout_handler h, void *arg); -struct sys_timeouts *sys_arch_timeouts(void); - -/* Semaphore functions. */ -sys_sem_t sys_sem_new(u8_t count); -void sys_sem_signal(sys_sem_t sem); -u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); -void sys_sem_free(sys_sem_t sem); -void sys_sem_wait(sys_sem_t sem); -int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); - -/* Time functions. */ -#ifndef sys_msleep -void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ -#endif -#ifndef sys_jiffies -u32_t sys_jiffies(void); /* since power up. */ -#endif - -/* Mailbox functions. */ -sys_mbox_t sys_mbox_new(int size); -void sys_mbox_post(sys_mbox_t mbox, void *msg); -err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg); -u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); -#ifndef sys_arch_mbox_tryfetch /* Allow port to override with a macro */ -u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg); -#endif -/* For now, we map straight to sys_arch implementation. */ -#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) -void sys_mbox_free(sys_mbox_t mbox); -void sys_mbox_fetch(sys_mbox_t mbox, void **msg); - -/* Thread functions. */ -sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio); - -#endif /* NO_SYS */ - -/** Returns the current time in milliseconds. */ -u32_t sys_now(void); - -/* Critical Region Protection */ -/* These functions must be implemented in the sys_arch.c file. - In some implementations they can provide a more light-weight protection - mechanism than using semaphores. Otherwise semaphores can be used for - implementation */ -#ifndef SYS_ARCH_PROTECT -/** SYS_LIGHTWEIGHT_PROT - * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection - * for certain critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#if SYS_LIGHTWEIGHT_PROT - -/** SYS_ARCH_DECL_PROTECT - * declare a protection variable. This macro will default to defining a variable of - * type sys_prot_t. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h. - */ -#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev -/** SYS_ARCH_PROTECT - * Perform a "fast" protect. This could be implemented by - * disabling interrupts for an embedded system or by using a semaphore or - * mutex. The implementation should allow calling SYS_ARCH_PROTECT when - * already protected. The old protection level is returned in the variable - * "lev". This macro will default to calling the sys_arch_protect() function - * which should be implemented in sys_arch.c. If a particular port needs a - * different implementation, then this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() -/** SYS_ARCH_UNPROTECT - * Perform a "fast" set of the protection level to "lev". This could be - * implemented by setting the interrupt level to "lev" within the MACRO or by - * using a semaphore or mutex. This macro will default to calling the - * sys_arch_unprotect() function which should be implemented in - * sys_arch.c. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) -sys_prot_t sys_arch_protect(void); -void sys_arch_unprotect(sys_prot_t pval); - -#else - -#define SYS_ARCH_DECL_PROTECT(lev) -#define SYS_ARCH_PROTECT(lev) -#define SYS_ARCH_UNPROTECT(lev) - -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#endif /* SYS_ARCH_PROTECT */ - -/* - * Macros to set/get and increase/decrease variables in a thread-safe way. - * Use these for accessing variable that are used from more than one thread. - */ - -#ifndef SYS_ARCH_INC -#define SYS_ARCH_INC(var, val) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - var += val; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_INC */ - -#ifndef SYS_ARCH_DEC -#define SYS_ARCH_DEC(var, val) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - var -= val; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_DEC */ - -#ifndef SYS_ARCH_GET -#define SYS_ARCH_GET(var, ret) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - ret = var; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_GET */ - -#ifndef SYS_ARCH_SET -#define SYS_ARCH_SET(var, val) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - var = val; \ - SYS_ARCH_UNPROTECT(old_level); \ - } while(0) -#endif /* SYS_ARCH_SET */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __LWIP_SYS_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/tcp.h b/components/net/lwip-1.3.2/src/include/lwip/tcp.h deleted file mode 100644 index c88d25d7ae..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/tcp.h +++ /dev/null @@ -1,707 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_TCP_H__ -#define __LWIP_TCP_H__ - -#include "lwip/opt.h" - -#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/sys.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/ip.h" -#include "lwip/icmp.h" -#include "lwip/err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct tcp_pcb; - -/* Functions for interfacing with TCP: */ - -/* Lower layer interface to TCP: */ -#define tcp_init() /* Compatibility define, not init needed. */ -void tcp_tmr (void); /* Must be called every - TCP_TMR_INTERVAL - ms. (Typically 250 ms). */ -/* Application program's interface: */ -struct tcp_pcb * tcp_new (void); -struct tcp_pcb * tcp_alloc (u8_t prio); - -void tcp_arg (struct tcp_pcb *pcb, void *arg); -void tcp_accept (struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, - err_t err)); -void tcp_recv (struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err)); -void tcp_sent (struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, - u16_t len)); -void tcp_poll (struct tcp_pcb *pcb, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb), - u8_t interval); -void tcp_err (struct tcp_pcb *pcb, - void (* err)(void *arg, err_t err)); - -#define tcp_mss(pcb) ((pcb)->mss) -#define tcp_sndbuf(pcb) ((pcb)->snd_buf) -#define tcp_nagle_disable(pcb) ((pcb)->flags |= TF_NODELAY) -#define tcp_nagle_enable(pcb) ((pcb)->flags &= ~TF_NODELAY) -#define tcp_nagle_disabled(pcb) (((pcb)->flags & TF_NODELAY) != 0) - -#if TCP_LISTEN_BACKLOG -#define tcp_accepted(pcb) (((struct tcp_pcb_listen *)(pcb))->accepts_pending--) -#else /* TCP_LISTEN_BACKLOG */ -#define tcp_accepted(pcb) -#endif /* TCP_LISTEN_BACKLOG */ - -void tcp_recved (struct tcp_pcb *pcb, u16_t len); -err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port, err_t (* connected)(void *arg, - struct tcp_pcb *tpcb, - err_t err)); - -struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); -#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) - -void tcp_abandon (struct tcp_pcb *pcb, int reset); -#define tcp_abort(pcb) tcp_abandon((pcb), 1) -err_t tcp_close (struct tcp_pcb *pcb); - -/* Flags for "apiflags" parameter in tcp_write and tcp_enqueue */ -#define TCP_WRITE_FLAG_COPY 0x01 -#define TCP_WRITE_FLAG_MORE 0x02 - -err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, - u8_t apiflags); - -void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); - -#define TCP_PRIO_MIN 1 -#define TCP_PRIO_NORMAL 64 -#define TCP_PRIO_MAX 127 - -/* It is also possible to call these two functions at the right - intervals (instead of calling tcp_tmr()). */ -void tcp_slowtmr (void); -void tcp_fasttmr (void); - - -/* Only used by IP to pass a TCP segment to TCP: */ -void tcp_input (struct pbuf *p, struct netif *inp); -/* Used within the TCP code only: */ -err_t tcp_send_empty_ack(struct tcp_pcb *pcb); -err_t tcp_output (struct tcp_pcb *pcb); -void tcp_rexmit (struct tcp_pcb *pcb); -void tcp_rexmit_rto (struct tcp_pcb *pcb); -void tcp_rexmit_fast (struct tcp_pcb *pcb); -u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); - -/** - * This is the Nagle algorithm: try to combine user data to send as few TCP - * segments as possible. Only send if - * - no previously transmitted data on the connection remains unacknowledged or - * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or - * - the only unsent segment is at least pcb->mss bytes long (or there is more - * than one unsent segment - with lwIP, this can happen although unsent->len < mss) - * - or if we are in fast-retransmit (TF_INFR) - */ -#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ - ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \ - (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ - ((tpcb)->unsent->len >= (tpcb)->mss))) \ - ) ? 1 : 0) -#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) - - -#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) -#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) -#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) -#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) -/* is b<=a<=c? */ -#if 0 /* see bug #10548 */ -#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) -#endif -#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) -#define TCP_FIN 0x01U -#define TCP_SYN 0x02U -#define TCP_RST 0x04U -#define TCP_PSH 0x08U -#define TCP_ACK 0x10U -#define TCP_URG 0x20U -#define TCP_ECE 0x40U -#define TCP_CWR 0x80U - -#define TCP_FLAGS 0x3fU - -/* Length of the TCP header, excluding options. */ -#define TCP_HLEN 20 - -#ifndef TCP_TMR_INTERVAL -#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */ -#endif /* TCP_TMR_INTERVAL */ - -#ifndef TCP_FAST_INTERVAL -#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ -#endif /* TCP_FAST_INTERVAL */ - -#ifndef TCP_SLOW_INTERVAL -#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ -#endif /* TCP_SLOW_INTERVAL */ - -#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ -#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ - -#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ - -#ifndef TCP_MSL -#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ -#endif - -/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ -#ifndef TCP_KEEPIDLE_DEFAULT -#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ -#endif - -#ifndef TCP_KEEPINTVL_DEFAULT -#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ -#endif - -#ifndef TCP_KEEPCNT_DEFAULT -#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ -#endif - -#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ - -/* Fields are (of course) in network byte order. - * Some fields are converted to host byte order in tcp_input(). - */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct tcp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); - PACK_STRUCT_FIELD(u32_t seqno); - PACK_STRUCT_FIELD(u32_t ackno); - PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); - PACK_STRUCT_FIELD(u16_t wnd); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t urgp); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) -#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) -#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) - -#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) -#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) -#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & htons((u16_t)(~(u16_t)(TCP_FLAGS)))) | htons(flags)) -#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags)) -#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) - -#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0)) - -enum tcp_state { - CLOSED = 0, - LISTEN = 1, - SYN_SENT = 2, - SYN_RCVD = 3, - ESTABLISHED = 4, - FIN_WAIT_1 = 5, - FIN_WAIT_2 = 6, - CLOSE_WAIT = 7, - CLOSING = 8, - LAST_ACK = 9, - TIME_WAIT = 10 -}; - -/** Flags used on input processing, not on pcb->flags -*/ -#define TF_RESET (u8_t)0x08U /* Connection was reset. */ -#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ -#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ - - -#if LWIP_CALLBACK_API - /* Function to call when a listener has been connected. - * @param arg user-supplied argument (tcp_pcb.callback_arg) - * @param pcb a new tcp_pcb that now is connected - * @param err an error argument (TODO: that is current always ERR_OK?) - * @return ERR_OK: accept the new connection, - * any other err_t abortsthe new connection - */ -#define DEF_ACCEPT_CALLBACK err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err) -#else /* LWIP_CALLBACK_API */ -#define DEF_ACCEPT_CALLBACK -#endif /* LWIP_CALLBACK_API */ - -/** - * members common to struct tcp_pcb and struct tcp_listen_pcb - */ -#define TCP_PCB_COMMON(type) \ - type *next; /* for the linked list */ \ - enum tcp_state state; /* TCP state */ \ - u8_t prio; \ - void *callback_arg; \ - /* ports are in host byte order */ \ - u16_t local_port; \ - /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \ - DEF_ACCEPT_CALLBACK - - -/* the TCP protocol control block */ -struct tcp_pcb { -/** common PCB members */ - IP_PCB; -/** protocol specific PCB members */ - TCP_PCB_COMMON(struct tcp_pcb); - - /* ports are in host byte order */ - u16_t remote_port; - - u8_t flags; -#define TF_ACK_DELAY ((u8_t)0x01U) /* Delayed ACK. */ -#define TF_ACK_NOW ((u8_t)0x02U) /* Immediate ACK. */ -#define TF_INFR ((u8_t)0x04U) /* In fast recovery. */ -#define TF_TIMESTAMP ((u8_t)0x08U) /* Timestamp option enabled */ -#define TF_FIN ((u8_t)0x20U) /* Connection was closed locally (FIN segment enqueued). */ -#define TF_NODELAY ((u8_t)0x40U) /* Disable Nagle algorithm */ -#define TF_NAGLEMEMERR ((u8_t)0x80U) /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ - - /* the rest of the fields are in host byte order - as we have to do some math with them */ - /* receiver variables */ - u32_t rcv_nxt; /* next seqno expected */ - u16_t rcv_wnd; /* receiver window available */ - u16_t rcv_ann_wnd; /* receiver window to announce */ - u32_t rcv_ann_right_edge; /* announced right edge of window */ - - /* Timers */ - u32_t tmr; - u8_t polltmr, pollinterval; - - /* Retransmission timer. */ - s16_t rtime; - - u16_t mss; /* maximum segment size */ - - /* RTT (round trip time) estimation variables */ - u32_t rttest; /* RTT estimate in 500ms ticks */ - u32_t rtseq; /* sequence number being timed */ - s16_t sa, sv; /* @todo document this */ - - s16_t rto; /* retransmission time-out */ - u8_t nrtx; /* number of retransmissions */ - - /* fast retransmit/recovery */ - u32_t lastack; /* Highest acknowledged seqno. */ - u8_t dupacks; - - /* congestion avoidance/control variables */ - u16_t cwnd; - u16_t ssthresh; - - /* sender variables */ - u32_t snd_nxt; /* next new seqno to be sent */ - u16_t snd_wnd; /* sender window */ - u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last - window update. */ - u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ - - u16_t acked; - - u16_t snd_buf; /* Available buffer space for sending (in bytes). */ -#define TCP_SNDQUEUELEN_OVERFLOW (0xffff-3) - u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ - - - /* These are ordered by sequence number: */ - struct tcp_seg *unsent; /* Unsent (queued) segments. */ - struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ -#if TCP_QUEUE_OOSEQ - struct tcp_seg *ooseq; /* Received out of sequence segments. */ -#endif /* TCP_QUEUE_OOSEQ */ - - struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ - -#if LWIP_CALLBACK_API - /* Function to be called when more send buffer space is available. - * @param arg user-supplied argument (tcp_pcb.callback_arg) - * @param pcb the tcp_pcb which has send buffer space available - * @param space the amount of bytes available - * @return ERR_OK: try to send some data by calling tcp_output - */ - err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); - - /* Function to be called when (in-sequence) data has arrived. - * @param arg user-supplied argument (tcp_pcb.callback_arg) - * @param pcb the tcp_pcb for which data has arrived - * @param p the packet buffer which arrived - * @param err an error argument (TODO: that is current always ERR_OK?) - * @return ERR_OK: try to send some data by calling tcp_output - */ - err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); - - /* Function to be called when a connection has been set up. - * @param arg user-supplied argument (tcp_pcb.callback_arg) - * @param pcb the tcp_pcb that now is connected - * @param err an error argument (TODO: that is current always ERR_OK?) - * @return value is currently ignored - */ - err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); - - /* Function which is called periodically. - * The period can be adjusted in multiples of the TCP slow timer interval - * by changing tcp_pcb.polltmr. - * @param arg user-supplied argument (tcp_pcb.callback_arg) - * @param pcb the tcp_pcb to poll for - * @return ERR_OK: try to send some data by calling tcp_output - */ - err_t (* poll)(void *arg, struct tcp_pcb *pcb); - - /* Function to be called whenever a fatal error occurs. - * There is no pcb parameter since most of the times, the pcb is - * already deallocated (or there is no pcb) when this function is called. - * @param arg user-supplied argument (tcp_pcb.callback_arg) - * @param err an indication why the error callback is called: - * ERR_ABRT: aborted through tcp_abort or by a TCP timer - * ERR_RST: the connection was reset by the remote host - */ - void (* errf)(void *arg, err_t err); -#endif /* LWIP_CALLBACK_API */ - -#if LWIP_TCP_TIMESTAMPS - u32_t ts_lastacksent; - u32_t ts_recent; -#endif /* LWIP_TCP_TIMESTAMPS */ - - /* idle time before KEEPALIVE is sent */ - u32_t keep_idle; -#if LWIP_TCP_KEEPALIVE - u32_t keep_intvl; - u32_t keep_cnt; -#endif /* LWIP_TCP_KEEPALIVE */ - - /* Persist timer counter */ - u32_t persist_cnt; - /* Persist timer back-off */ - u8_t persist_backoff; - - /* KEEPALIVE counter */ - u8_t keep_cnt_sent; -}; - -struct tcp_pcb_listen { -/* Common members of all PCB types */ - IP_PCB; -/* Protocol specific PCB members */ - TCP_PCB_COMMON(struct tcp_pcb_listen); - -#if TCP_LISTEN_BACKLOG - u8_t backlog; - u8_t accepts_pending; -#endif /* TCP_LISTEN_BACKLOG */ -}; - -#if LWIP_EVENT_API - -enum lwip_event { - LWIP_EVENT_ACCEPT, - LWIP_EVENT_SENT, - LWIP_EVENT_RECV, - LWIP_EVENT_CONNECTED, - LWIP_EVENT_POLL, - LWIP_EVENT_ERR -}; - -err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, - enum lwip_event, - struct pbuf *p, - u16_t size, - err_t err); - -#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_ACCEPT, NULL, 0, err) -#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_SENT, NULL, space, ERR_OK) -#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_RECV, (p), 0, (err)) -#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_CONNECTED, NULL, 0, (err)) -#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_POLL, NULL, 0, ERR_OK) -#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ - LWIP_EVENT_ERR, NULL, 0, (err)) -#else /* LWIP_EVENT_API */ - -#define TCP_EVENT_ACCEPT(pcb,err,ret) \ - do { \ - if((pcb)->accept != NULL) \ - (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_SENT(pcb,space,ret) \ - do { \ - if((pcb)->sent != NULL) \ - (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_RECV(pcb,p,err,ret) \ - do { \ - if((pcb)->recv != NULL) { \ - (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); \ - } else { \ - (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \ - } \ - } while (0) - -#define TCP_EVENT_CONNECTED(pcb,err,ret) \ - do { \ - if((pcb)->connected != NULL) \ - (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_POLL(pcb,ret) \ - do { \ - if((pcb)->poll != NULL) \ - (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ - else (ret) = ERR_OK; \ - } while (0) - -#define TCP_EVENT_ERR(errf,arg,err) \ - do { \ - if((errf) != NULL) \ - (errf)((arg),(err)); \ - } while (0) - -#endif /* LWIP_EVENT_API */ - -/* This structure represents a TCP segment on the unsent and unacked queues */ -struct tcp_seg { - struct tcp_seg *next; /* used when putting segements on a queue */ - struct pbuf *p; /* buffer containing data + TCP header */ - void *dataptr; /* pointer to the TCP data in the pbuf */ - u16_t len; /* the TCP length of this segment */ - u8_t flags; -#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option. */ -#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ - struct tcp_hdr *tcphdr; /* the TCP header */ -}; - -#define LWIP_TCP_OPT_LENGTH(flags) \ - (flags & TF_SEG_OPTS_MSS ? 4 : 0) + \ - (flags & TF_SEG_OPTS_TS ? 12 : 0) - -/** This returns a TCP header option for MSS in an u32_t */ -#define TCP_BUILD_MSS_OPTION(x) (x) = htonl(((u32_t)2 << 24) | \ - ((u32_t)4 << 16) | \ - (((u32_t)TCP_MSS / 256) << 8) | \ - (TCP_MSS & 255)) - -/* Internal functions and global variables: */ -struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); -void tcp_pcb_purge(struct tcp_pcb *pcb); -void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); - -u8_t tcp_segs_free(struct tcp_seg *seg); -u8_t tcp_seg_free(struct tcp_seg *seg); -struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); - -#define tcp_ack(pcb) \ - do { \ - if((pcb)->flags & TF_ACK_DELAY) { \ - (pcb)->flags &= ~TF_ACK_DELAY; \ - (pcb)->flags |= TF_ACK_NOW; \ - tcp_output(pcb); \ - } \ - else { \ - (pcb)->flags |= TF_ACK_DELAY; \ - } \ - } while (0) - -#define tcp_ack_now(pcb) \ - do { \ - (pcb)->flags |= TF_ACK_NOW; \ - tcp_output(pcb); \ - } while (0) - -err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); -err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, - u8_t flags, u8_t apiflags, u8_t optflags); - -void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); - -void tcp_rst(u32_t seqno, u32_t ackno, - struct ip_addr *local_ip, struct ip_addr *remote_ip, - u16_t local_port, u16_t remote_port); - -u32_t tcp_next_iss(void); - -void tcp_keepalive(struct tcp_pcb *pcb); -void tcp_zero_window_probe(struct tcp_pcb *pcb); - -#if TCP_CALCULATE_EFF_SEND_MSS -u16_t tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr); -#endif /* TCP_CALCULATE_EFF_SEND_MSS */ - -#if LWIP_CALLBACK_API -err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); -#endif /* LWIP_CALLBACK_API */ - -extern struct tcp_pcb *tcp_input_pcb; -extern u32_t tcp_ticks; - -const char* tcp_debug_state_str(enum tcp_state s); -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -void tcp_debug_print(struct tcp_hdr *tcphdr); -void tcp_debug_print_flags(u8_t flags); -void tcp_debug_print_state(enum tcp_state s); -void tcp_debug_print_pcbs(void); -s16_t tcp_pcbs_sane(void); -#else -# define tcp_debug_print(tcphdr) -# define tcp_debug_print_flags(flags) -# define tcp_debug_print_state(s) -# define tcp_debug_print_pcbs() -# define tcp_pcbs_sane() 1 -#endif /* TCP_DEBUG */ - -#if NO_SYS -#define tcp_timer_needed() -#else -void tcp_timer_needed(void); -#endif - -/* The TCP PCB lists. */ -union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ - struct tcp_pcb_listen *listen_pcbs; - struct tcp_pcb *pcbs; -}; -extern union tcp_listen_pcbs_t tcp_listen_pcbs; -extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a - state in which they accept or send - data. */ -extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ - -extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ - -/* Axioms about the above lists: - 1) Every TCP PCB that is not CLOSED is in one of the lists. - 2) A PCB is only in one of the lists. - 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. - 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. -*/ - -/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB - with a PCB list or removes a PCB from a list, respectively. */ -#if 0 -#define TCP_REG(pcbs, npcb) do {\ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ - for(tcp_tmp_pcb = *pcbs; \ - tcp_tmp_pcb != NULL; \ - tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ - } \ - LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ - npcb->next = *pcbs; \ - LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ - *(pcbs) = npcb; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - tcp_timer_needed(); \ - } while(0) -#define TCP_RMV(pcbs, npcb) do { \ - LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ - if(*pcbs == npcb) { \ - *pcbs = (*pcbs)->next; \ - } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next == npcb) { \ - tcp_tmp_pcb->next = npcb->next; \ - break; \ - } \ - } \ - npcb->next = NULL; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ - } while(0) - -#else /* LWIP_DEBUG */ - -#define TCP_REG(pcbs, npcb) \ - do { \ - npcb->next = *pcbs; \ - *(pcbs) = npcb; \ - tcp_timer_needed(); \ - } while (0) - -#define TCP_RMV(pcbs, npcb) \ - do { \ - if(*(pcbs) == npcb) { \ - (*(pcbs)) = (*pcbs)->next; \ - } \ - else { \ - for(tcp_tmp_pcb = *pcbs; \ - tcp_tmp_pcb != NULL; \ - tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next == npcb) { \ - tcp_tmp_pcb->next = npcb->next; \ - break; \ - } \ - } \ - } \ - npcb->next = NULL; \ - } while(0) - -#endif /* LWIP_DEBUG */ - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_TCP */ - -#endif /* __LWIP_TCP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/tcpip.h b/components/net/lwip-1.3.2/src/include/lwip/tcpip.h deleted file mode 100644 index 75393ee911..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/tcpip.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_TCPIP_H__ -#define __LWIP_TCPIP_H__ - -#include "lwip/opt.h" - -#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/api_msg.h" -#include "lwip/netifapi.h" -#include "lwip/pbuf.h" -#include "lwip/api.h" -#include "lwip/sys.h" -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if LWIP_TCPIP_CORE_LOCKING -/** The global semaphore to lock the stack. */ -extern sys_sem_t lock_tcpip_core; -#define LOCK_TCPIP_CORE() sys_sem_wait(lock_tcpip_core) -#define UNLOCK_TCPIP_CORE() sys_sem_signal(lock_tcpip_core) -#define TCPIP_APIMSG(m) tcpip_apimsg_lock(m) -#define TCPIP_APIMSG_ACK(m) -#define TCPIP_NETIFAPI(m) tcpip_netifapi_lock(m) -#define TCPIP_NETIFAPI_ACK(m) -#else -#define LOCK_TCPIP_CORE() -#define UNLOCK_TCPIP_CORE() -#define TCPIP_APIMSG(m) tcpip_apimsg(m) -#define TCPIP_APIMSG_ACK(m) sys_sem_signal(m->conn->op_completed) -#define TCPIP_NETIFAPI(m) tcpip_netifapi(m) -#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(m->sem) -#endif /* LWIP_TCPIP_CORE_LOCKING */ - -void tcpip_init(void (* tcpip_init_done)(void *), void *arg); - -#if LWIP_NETCONN -err_t tcpip_apimsg(struct api_msg *apimsg); -#if LWIP_TCPIP_CORE_LOCKING -err_t tcpip_apimsg_lock(struct api_msg *apimsg); -#endif /* LWIP_TCPIP_CORE_LOCKING */ -#endif /* LWIP_NETCONN */ - -err_t tcpip_input(struct pbuf *p, struct netif *inp); - -#if LWIP_NETIF_API -err_t tcpip_netifapi(struct netifapi_msg *netifapimsg); -#if LWIP_TCPIP_CORE_LOCKING -err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg); -#endif /* LWIP_TCPIP_CORE_LOCKING */ -#endif /* LWIP_NETIF_API */ - -err_t tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block); -#define tcpip_callback(f, ctx) tcpip_callback_with_block(f, ctx, 1) - -/* free pbufs or heap memory from another context without blocking */ -err_t pbuf_free_callback(struct pbuf *p); -err_t mem_free_callback(void *m); - -err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); -err_t tcpip_untimeout(sys_timeout_handler h, void *arg); - -enum tcpip_msg_type { -#if LWIP_NETCONN - TCPIP_MSG_API, -#endif /* LWIP_NETCONN */ - TCPIP_MSG_INPKT, -#if LWIP_NETIF_API - TCPIP_MSG_NETIFAPI, -#endif /* LWIP_NETIF_API */ - TCPIP_MSG_CALLBACK, - TCPIP_MSG_TIMEOUT, - TCPIP_MSG_UNTIMEOUT -}; - -struct tcpip_msg { - enum tcpip_msg_type type; - sys_sem_t *sem; - union { -#if LWIP_NETCONN - struct api_msg *apimsg; -#endif /* LWIP_NETCONN */ -#if LWIP_NETIF_API - struct netifapi_msg *netifapimsg; -#endif /* LWIP_NETIF_API */ - struct { - struct pbuf *p; - struct netif *netif; - } inp; - struct { - void (*f)(void *ctx); - void *ctx; - } cb; - struct { - u32_t msecs; - sys_timeout_handler h; - void *arg; - } tmo; - } msg; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* !NO_SYS */ - -#endif /* __LWIP_TCPIP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/lwip/udp.h b/components/net/lwip-1.3.2/src/include/lwip/udp.h deleted file mode 100644 index 08d1817b30..0000000000 --- a/components/net/lwip-1.3.2/src/include/lwip/udp.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_UDP_H__ -#define __LWIP_UDP_H__ - -#include "lwip/opt.h" - -#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/ip_addr.h" -#include "lwip/ip.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UDP_HLEN 8 - -/* Fields are (of course) in network byte order. */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct udp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ - PACK_STRUCT_FIELD(u16_t len); - PACK_STRUCT_FIELD(u16_t chksum); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define UDP_FLAGS_NOCHKSUM 0x01U -#define UDP_FLAGS_UDPLITE 0x02U -#define UDP_FLAGS_CONNECTED 0x04U - -struct udp_pcb { -/* Common members of all PCB types */ - IP_PCB; - -/* Protocol specific PCB members */ - - struct udp_pcb *next; - - u8_t flags; - /* ports are in host byte order */ - u16_t local_port, remote_port; - -#if LWIP_IGMP - /* outgoing network interface for multicast packets */ - struct ip_addr multicast_ip; -#endif /* LWIP_IGMP */ - -#if LWIP_UDPLITE - /* used for UDP_LITE only */ - u16_t chksum_len_rx, chksum_len_tx; -#endif /* LWIP_UDPLITE */ - - /* receive callback function - * addr and port are in same byte order as in the pcb - * The callback is responsible for freeing the pbuf - * if it's not used any more. - * - * ATTENTION: Be aware that 'addr' points into the pbuf 'p' so freeing this pbuf - * makes 'addr' invalid, too. - * - * @param arg user supplied argument (udp_pcb.recv_arg) - * @param pcb the udp_pcb which received data - * @param p the packet buffer that was received - * @param addr the remote IP address from which the packet was received - * @param port the remote port from which the packet was received - */ - void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *addr, u16_t port); - /* user-supplied argument for the recv callback */ - void *recv_arg; -}; -/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ -extern struct udp_pcb *udp_pcbs; - -/* The following functions is the application layer interface to the - UDP code. */ -struct udp_pcb * udp_new (void); -void udp_remove (struct udp_pcb *pcb); -err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -void udp_disconnect (struct udp_pcb *pcb); -void udp_recv (struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, - struct pbuf *p, - struct ip_addr *addr, - u16_t port), - void *recv_arg); -err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif); -err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); -err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); - -#define udp_flags(pcb) ((pcb)->flags) -#define udp_setflags(pcb, f) ((pcb)->flags = (f)) - -/* The following functions are the lower layer interface to UDP. */ -void udp_input (struct pbuf *p, struct netif *inp); - -#define udp_init() /* Compatibility define, not init needed. */ - -#if UDP_DEBUG -void udp_debug_print(struct udp_hdr *udphdr); -#else -#define udp_debug_print(udphdr) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_UDP */ - -#endif /* __LWIP_UDP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/netif/etharp.h b/components/net/lwip-1.3.2/src/include/netif/etharp.h deleted file mode 100644 index 72b8d79f08..0000000000 --- a/components/net/lwip-1.3.2/src/include/netif/etharp.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __NETIF_ETHARP_H__ -#define __NETIF_ETHARP_H__ - -#include "lwip/opt.h" - -#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/ip.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ETH_PAD_SIZE -#define ETH_PAD_SIZE 0 -#endif - -#ifndef ETHARP_HWADDR_LEN -#define ETHARP_HWADDR_LEN 6 -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_addr { - PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_hdr { -#if ETH_PAD_SIZE - PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); -#endif - PACK_STRUCT_FIELD(struct eth_addr dest); - PACK_STRUCT_FIELD(struct eth_addr src); - PACK_STRUCT_FIELD(u16_t type); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE) - -#if ETHARP_SUPPORT_VLAN - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_vlan_hdr { - PACK_STRUCT_FIELD(u16_t tpid); - PACK_STRUCT_FIELD(u16_t prio_vid); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define SIZEOF_VLAN_HDR 4 -#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF) - -#endif /* ETHARP_SUPPORT_VLAN */ - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** the ARP message */ -struct etharp_hdr { - PACK_STRUCT_FIELD(u16_t hwtype); - PACK_STRUCT_FIELD(u16_t proto); - PACK_STRUCT_FIELD(u16_t _hwlen_protolen); - PACK_STRUCT_FIELD(u16_t opcode); - PACK_STRUCT_FIELD(struct eth_addr shwaddr); - PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); - PACK_STRUCT_FIELD(struct eth_addr dhwaddr); - PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define SIZEOF_ETHARP_HDR 28 -#define SIZEOF_ETHARP_PACKET (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR) - -/** 5 seconds period */ -#define ARP_TMR_INTERVAL 5000 - -#define ETHTYPE_ARP 0x0806 -#define ETHTYPE_IP 0x0800 -#define ETHTYPE_VLAN 0x8100 -#define ETHTYPE_PPPOEDISC 0x8863 /* PPP Over Ethernet Discovery Stage */ -#define ETHTYPE_PPPOE 0x8864 /* PPP Over Ethernet Session Stage */ - -/** ARP message types (opcodes) */ -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#if ARP_QUEUEING -/** struct for queueing outgoing packets for unknown address - * defined here to be accessed by memp.h - */ -struct etharp_q_entry { - struct etharp_q_entry *next; - struct pbuf *p; -}; -#endif /* ARP_QUEUEING */ - -#define etharp_init() /* Compatibility define, not init needed. */ -void etharp_tmr(void); -s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, - struct eth_addr **eth_ret, struct ip_addr **ip_ret); -void etharp_ip_input(struct netif *netif, struct pbuf *p); -void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, - struct pbuf *p); -err_t etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr); -err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q); -err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr); -/** For Ethernet network interfaces, we might want to send "gratuitous ARP"; - * this is an ARP packet sent by a node in order to spontaneously cause other - * nodes to update an entry in their ARP cache. - * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */ -#define etharp_gratuitous(netif) etharp_request((netif), &(netif)->ip_addr) - -err_t ethernet_input(struct pbuf *p, struct netif *netif); - -#if LWIP_AUTOIP -err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, - const struct eth_addr *ethdst_addr, - const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr, - const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr, - const u16_t opcode); -#endif /* LWIP_AUTOIP */ - -#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0) - -extern const struct eth_addr ethbroadcast, ethzero; - -#ifdef __cplusplus -} -#endif - -#endif /* LWIP_ARP */ - -#endif /* __NETIF_ARP_H__ */ diff --git a/components/net/lwip-1.3.2/src/include/netif/slipif.h b/components/net/lwip-1.3.2/src/include/netif/slipif.h deleted file mode 100644 index ccd03c8a16..0000000000 --- a/components/net/lwip-1.3.2/src/include/netif/slipif.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __NETIF_SLIPIF_H__ -#define __NETIF_SLIPIF_H__ - -#include "lwip/netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -err_t slipif_init(struct netif * netif); -void slipif_poll(struct netif *netif); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/components/net/lwip-1.3.2/src/netif/FILES b/components/net/lwip-1.3.2/src/netif/FILES deleted file mode 100644 index 099dbf3ec2..0000000000 --- a/components/net/lwip-1.3.2/src/netif/FILES +++ /dev/null @@ -1,29 +0,0 @@ -This directory contains generic network interface device drivers that -do not contain any hardware or architecture specific code. The files -are: - -etharp.c - Implements the ARP (Address Resolution Protocol) over - Ethernet. The code in this file should be used together with - Ethernet device drivers. Note that this module has been - largely made Ethernet independent so you should be able to - adapt this for other link layers (such as Firewire). - -ethernetif.c - An example of how an Ethernet device driver could look. This - file can be used as a "skeleton" for developing new Ethernet - network device drivers. It uses the etharp.c ARP code. - -loopif.c - A "loopback" network interface driver. It requires configuration - through the define LWIP_LOOPIF_MULTITHREADING (see opt.h). - -slipif.c - A generic implementation of the SLIP (Serial Line IP) - protocol. It requires a sio (serial I/O) module to work. - -ppp/ Point-to-Point Protocol stack - The PPP stack has been ported from ucip (http://ucip.sourceforge.net). - It matches quite well to pppd 2.3.1 (http://ppp.samba.org), although - compared to that, it has some modifications for embedded systems and - the source code has been reordered a bit. \ No newline at end of file diff --git a/components/net/lwip-1.3.2/src/netif/etharp.c b/components/net/lwip-1.3.2/src/netif/etharp.c deleted file mode 100644 index 8f6872fa2c..0000000000 --- a/components/net/lwip-1.3.2/src/netif/etharp.c +++ /dev/null @@ -1,1222 +0,0 @@ -/** - * @file - * Address Resolution Protocol module for IP over Ethernet - * - * Functionally, ARP is divided into two parts. The first maps an IP address - * to a physical address when sending a packet, and the second part answers - * requests from other machines for our physical address. - * - * This implementation complies with RFC 826 (Ethernet ARP). It supports - * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 - * if an interface calls etharp_gratuitous(our_netif) upon address change. - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" - -#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "lwip/dhcp.h" -#include "lwip/autoip.h" -#include "netif/etharp.h" - -#if PPPOE_SUPPORT -#include "netif/ppp_oe.h" -#endif /* PPPOE_SUPPORT */ - -#include - -/** the time an ARP entry stays valid after its last update, - * for ARP_TMR_INTERVAL = 5000, this is - * (240 * 5) seconds = 20 minutes. - */ -#define ARP_MAXAGE 240 -/** the time an ARP entry stays pending after first request, - * for ARP_TMR_INTERVAL = 5000, this is - * (2 * 5) seconds = 10 seconds. - * - * @internal Keep this number at least 2, otherwise it might - * run out instantly if the timeout occurs directly after a request. - */ -#define ARP_MAXPENDING 2 - -#define HWTYPE_ETHERNET 1 - -#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8) -#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff) - -#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8)) -#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8)) - -enum etharp_state { - ETHARP_STATE_EMPTY = 0, - ETHARP_STATE_PENDING, - ETHARP_STATE_STABLE -}; - -struct etharp_entry { -#if ARP_QUEUEING - /** - * Pointer to queue of pending outgoing packets on this ARP entry. - */ - struct etharp_q_entry *q; -#endif - struct ip_addr ipaddr; - struct eth_addr ethaddr; - enum etharp_state state; - u8_t ctime; - struct netif *netif; -}; - -const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; -const struct eth_addr ethzero = {{0,0,0,0,0,0}}; -static struct etharp_entry arp_table[ARP_TABLE_SIZE]; -#if !LWIP_NETIF_HWADDRHINT -static u8_t etharp_cached_entry; -#endif - -/** - * Try hard to create a new entry - we want the IP address to appear in - * the cache (even if this means removing an active entry or so). */ -#define ETHARP_TRY_HARD 1 -#define ETHARP_FIND_ONLY 2 - -#if LWIP_NETIF_HWADDRHINT -#define NETIF_SET_HINT(netif, hint) if (((netif) != NULL) && ((netif)->addr_hint != NULL)) \ - *((netif)->addr_hint) = (hint); -static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif); -#else /* LWIP_NETIF_HWADDRHINT */ -static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags); -#endif /* LWIP_NETIF_HWADDRHINT */ - -static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags); - - -/* Some checks, instead of etharp_init(): */ -#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) - #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h" -#endif - - -#if ARP_QUEUEING -/** - * Free a complete queue of etharp entries - * - * @param q a qeueue of etharp_q_entry's to free - */ -static void -free_etharp_q(struct etharp_q_entry *q) -{ - struct etharp_q_entry *r; - LWIP_ASSERT("q != NULL", q != NULL); - LWIP_ASSERT("q->p != NULL", q->p != NULL); - while (q) { - r = q; - q = q->next; - LWIP_ASSERT("r->p != NULL", (r->p != NULL)); - pbuf_free(r->p); - memp_free(MEMP_ARP_QUEUE, r); - } -} -#endif - -/** - * Clears expired entries in the ARP table. - * - * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds), - * in order to expire entries in the ARP table. - */ -void -etharp_tmr(void) -{ - u8_t i; - - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); - /* remove expired entries from the ARP table */ - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - arp_table[i].ctime++; - if (((arp_table[i].state == ETHARP_STATE_STABLE) && - (arp_table[i].ctime >= ARP_MAXAGE)) || - ((arp_table[i].state == ETHARP_STATE_PENDING) && - (arp_table[i].ctime >= ARP_MAXPENDING))) { - /* pending or stable entry has become old! */ - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n", - arp_table[i].state == ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i)); - /* clean up entries that have just been expired */ - /* remove from SNMP ARP index tree */ - snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); -#if ARP_QUEUEING - /* and empty packet queue */ - if (arp_table[i].q != NULL) { - /* remove all queued packets */ - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); - free_etharp_q(arp_table[i].q); - arp_table[i].q = NULL; - } -#endif - /* recycle entry for re-use */ - arp_table[i].state = ETHARP_STATE_EMPTY; - } -#if ARP_QUEUEING - /* still pending entry? (not expired) */ - if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* resend an ARP query here? */ - } -#endif - } -} - -/** - * Search the ARP table for a matching or new entry. - * - * If an IP address is given, return a pending or stable ARP entry that matches - * the address. If no match is found, create a new entry with this address set, - * but in state ETHARP_EMPTY. The caller must check and possibly change the - * state of the returned entry. - * - * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. - * - * In all cases, attempt to create new entries from an empty entry. If no - * empty entries are available and ETHARP_TRY_HARD flag is set, recycle - * old entries. Heuristic choose the least important entry for recycling. - * - * @param ipaddr IP address to find in ARP cache, or to add if not found. - * @param flags - * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of - * active (stable or pending) entries. - * - * @return The ARP entry index that matched or is created, ERR_MEM if no - * entry is found or could be recycled. - */ -static s8_t -#if LWIP_NETIF_HWADDRHINT -find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif) -#else /* LWIP_NETIF_HWADDRHINT */ -find_entry(struct ip_addr *ipaddr, u8_t flags) -#endif /* LWIP_NETIF_HWADDRHINT */ -{ - s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; - s8_t empty = ARP_TABLE_SIZE; - u8_t i = 0, age_pending = 0, age_stable = 0; -#if ARP_QUEUEING - /* oldest entry with packets on queue */ - s8_t old_queue = ARP_TABLE_SIZE; - /* its age */ - u8_t age_queue = 0; -#endif - - /* First, test if the last call to this function asked for the - * same address. If so, we're really fast! */ - if (ipaddr) { - /* ipaddr to search for was given */ -#if LWIP_NETIF_HWADDRHINT - if ((netif != NULL) && (netif->addr_hint != NULL)) { - /* per-pcb cached entry was given */ - u8_t per_pcb_cache = *(netif->addr_hint); - if ((per_pcb_cache < ARP_TABLE_SIZE) && arp_table[per_pcb_cache].state == ETHARP_STATE_STABLE) { - /* the per-pcb-cached entry is stable */ - if (ip_addr_cmp(ipaddr, &arp_table[per_pcb_cache].ipaddr)) { - /* per-pcb cached entry was the right one! */ - ETHARP_STATS_INC(etharp.cachehit); - return per_pcb_cache; - } - } - } -#else /* #if LWIP_NETIF_HWADDRHINT */ - if (arp_table[etharp_cached_entry].state == ETHARP_STATE_STABLE) { - /* the cached entry is stable */ - if (ip_addr_cmp(ipaddr, &arp_table[etharp_cached_entry].ipaddr)) { - /* cached entry was the right one! */ - ETHARP_STATS_INC(etharp.cachehit); - return etharp_cached_entry; - } - } -#endif /* #if LWIP_NETIF_HWADDRHINT */ - } - - /** - * a) do a search through the cache, remember candidates - * b) select candidate entry - * c) create new entry - */ - - /* a) in a single search sweep, do all of this - * 1) remember the first empty entry (if any) - * 2) remember the oldest stable entry (if any) - * 3) remember the oldest pending entry without queued packets (if any) - * 4) remember the oldest pending entry with queued packets (if any) - * 5) search for a matching IP entry, either pending or stable - * until 5 matches, or all entries are searched for. - */ - - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - /* no empty entry found yet and now we do find one? */ - if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) { - LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); - /* remember first empty entry */ - empty = i; - } - /* pending entry? */ - else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ -#if LWIP_NETIF_HWADDRHINT - NETIF_SET_HINT(netif, i); -#else /* #if LWIP_NETIF_HWADDRHINT */ - etharp_cached_entry = i; -#endif /* #if LWIP_NETIF_HWADDRHINT */ - return i; -#if ARP_QUEUEING - /* pending with queued packets? */ - } else if (arp_table[i].q != NULL) { - if (arp_table[i].ctime >= age_queue) { - old_queue = i; - age_queue = arp_table[i].ctime; - } -#endif - /* pending without queued packets? */ - } else { - if (arp_table[i].ctime >= age_pending) { - old_pending = i; - age_pending = arp_table[i].ctime; - } - } - } - /* stable entry? */ - else if (arp_table[i].state == ETHARP_STATE_STABLE) { - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ -#if LWIP_NETIF_HWADDRHINT - NETIF_SET_HINT(netif, i); -#else /* #if LWIP_NETIF_HWADDRHINT */ - etharp_cached_entry = i; -#endif /* #if LWIP_NETIF_HWADDRHINT */ - return i; - /* remember entry with oldest stable entry in oldest, its age in maxtime */ - } else if (arp_table[i].ctime >= age_stable) { - old_stable = i; - age_stable = arp_table[i].ctime; - } - } - } - /* { we have no match } => try to create a new entry */ - - /* no empty entry found and not allowed to recycle? */ - if (((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0)) - /* or don't create new entry, only search? */ - || ((flags & ETHARP_FIND_ONLY) != 0)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty entry found and not allowed to recycle\n")); - return (s8_t)ERR_MEM; - } - - /* b) choose the least destructive entry to recycle: - * 1) empty entry - * 2) oldest stable entry - * 3) oldest pending entry without queued packets - * 4) oldest pending entry with queued packets - * - * { ETHARP_TRY_HARD is set at this point } - */ - - /* 1) empty entry available? */ - if (empty < ARP_TABLE_SIZE) { - i = empty; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); - } - /* 2) found recyclable stable entry? */ - else if (old_stable < ARP_TABLE_SIZE) { - /* recycle oldest stable*/ - i = old_stable; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); -#if ARP_QUEUEING - /* no queued packets should exist on stable entries */ - LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); -#endif - /* 3) found recyclable pending entry without queued packets? */ - } else if (old_pending < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_pending; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); -#if ARP_QUEUEING - /* 4) found recyclable pending entry with queued packets? */ - } else if (old_queue < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_queue; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q))); - free_etharp_q(arp_table[i].q); - arp_table[i].q = NULL; -#endif - /* no empty or recyclable entries found */ - } else { - return (s8_t)ERR_MEM; - } - - /* { empty or recyclable entry found } */ - LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); - - if (arp_table[i].state != ETHARP_STATE_EMPTY) - { - snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); - } - /* recycle entry (no-op for an already empty entry) */ - arp_table[i].state = ETHARP_STATE_EMPTY; - - /* IP address given? */ - if (ipaddr != NULL) { - /* set IP address */ - ip_addr_set(&arp_table[i].ipaddr, ipaddr); - } - arp_table[i].ctime = 0; -#if LWIP_NETIF_HWADDRHINT - NETIF_SET_HINT(netif, i); -#else /* #if LWIP_NETIF_HWADDRHINT */ - etharp_cached_entry = i; -#endif /* #if LWIP_NETIF_HWADDRHINT */ - return (err_t)i; -} - -/** - * Send an IP packet on the network using netif->linkoutput - * The ethernet header is filled in before sending. - * - * @params netif the lwIP network interface on which to send the packet - * @params p the packet to send, p->payload pointing to the (uninitialized) ethernet header - * @params src the source MAC address to be copied into the ethernet header - * @params dst the destination MAC address to be copied into the ethernet header - * @return ERR_OK if the packet was sent, any other err_t on failure - */ -static err_t -etharp_send_ip(struct netif *netif, struct pbuf *p, struct eth_addr *src, struct eth_addr *dst) -{ - struct eth_hdr *ethhdr = p->payload; - u8_t k; - - LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", - (netif->hwaddr_len == ETHARP_HWADDR_LEN)); - k = ETHARP_HWADDR_LEN; - while(k > 0) { - k--; - ethhdr->dest.addr[k] = dst->addr[k]; - ethhdr->src.addr[k] = src->addr[k]; - } - ethhdr->type = htons(ETHTYPE_IP); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_send_ip: sending packet %p\n", (void *)p)); - /* send the packet */ - return netif->linkoutput(netif, p); -} - -/** - * Update (or insert) a IP/MAC address pair in the ARP cache. - * - * If a pending entry is resolved, any queued packets will be sent - * at this point. - * - * @param ipaddr IP address of the inserted ARP entry. - * @param ethaddr Ethernet address of the inserted ARP entry. - * @param flags Defines behaviour: - * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified, - * only existing ARP entries will be updated. - * - * @return - * - ERR_OK Succesfully updated ARP cache. - * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set. - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - * @see pbuf_free() - */ -static err_t -update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags) -{ - s8_t i; - u8_t k; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry()\n")); - LWIP_ASSERT("netif->hwaddr_len == ETHARP_HWADDR_LEN", netif->hwaddr_len == ETHARP_HWADDR_LEN); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", - ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), - ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], - ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); - /* non-unicast address? */ - if (ip_addr_isany(ipaddr) || - ip_addr_isbroadcast(ipaddr, netif) || - ip_addr_ismulticast(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - /* find or create ARP entry */ -#if LWIP_NETIF_HWADDRHINT - i = find_entry(ipaddr, flags, netif); -#else /* LWIP_NETIF_HWADDRHINT */ - i = find_entry(ipaddr, flags); -#endif /* LWIP_NETIF_HWADDRHINT */ - /* bail out if no entry could be found */ - if (i < 0) - return (err_t)i; - - /* mark it stable */ - arp_table[i].state = ETHARP_STATE_STABLE; - /* record network interface */ - arp_table[i].netif = netif; - - /* insert in SNMP ARP index tree */ - snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr); - - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); - /* update address */ - k = ETHARP_HWADDR_LEN; - while (k > 0) { - k--; - arp_table[i].ethaddr.addr[k] = ethaddr->addr[k]; - } - /* reset time stamp */ - arp_table[i].ctime = 0; -#if ARP_QUEUEING - /* this is where we will send out queued packets! */ - while (arp_table[i].q != NULL) { - struct pbuf *p; - /* remember remainder of queue */ - struct etharp_q_entry *q = arp_table[i].q; - /* pop first item off the queue */ - arp_table[i].q = q->next; - /* get the packet pointer */ - p = q->p; - /* now queue entry can be freed */ - memp_free(MEMP_ARP_QUEUE, q); - /* send the queued IP packet */ - etharp_send_ip(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr); - /* free the queued IP packet */ - pbuf_free(p); - } -#endif - return ERR_OK; -} - -/** - * Finds (stable) ethernet/IP address pair from ARP table - * using interface and IP address index. - * @note the addresses in the ARP table are in network order! - * - * @param netif points to interface index - * @param ipaddr points to the (network order) IP address index - * @param eth_ret points to return pointer - * @param ip_ret points to return pointer - * @return table index if found, -1 otherwise - */ -s8_t -etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, - struct eth_addr **eth_ret, struct ip_addr **ip_ret) -{ - s8_t i; - - LWIP_UNUSED_ARG(netif); - -#if LWIP_NETIF_HWADDRHINT - i = find_entry(ipaddr, ETHARP_FIND_ONLY, NULL); -#else /* LWIP_NETIF_HWADDRHINT */ - i = find_entry(ipaddr, ETHARP_FIND_ONLY); -#endif /* LWIP_NETIF_HWADDRHINT */ - if((i >= 0) && arp_table[i].state == ETHARP_STATE_STABLE) { - *eth_ret = &arp_table[i].ethaddr; - *ip_ret = &arp_table[i].ipaddr; - return i; - } - return -1; -} - -/** - * Updates the ARP table using the given IP packet. - * - * Uses the incoming IP packet's source address to update the - * ARP cache for the local network. The function does not alter - * or free the packet. This function must be called before the - * packet p is passed to the IP layer. - * - * @param netif The lwIP network interface on which the IP packet pbuf arrived. - * @param p The IP packet that arrived on netif. - * - * @return NULL - * - * @see pbuf_free() - */ -void -etharp_ip_input(struct netif *netif, struct pbuf *p) -{ - struct eth_hdr *ethhdr; - struct ip_hdr *iphdr; - LWIP_ERROR("netif != NULL", (netif != NULL), return;); - /* Only insert an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - ethhdr = p->payload; - iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); -#if ETHARP_SUPPORT_VLAN - if (ethhdr->type == ETHTYPE_VLAN) { - iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR); - } -#endif /* ETHARP_SUPPORT_VLAN */ - - /* source is not on the local network? */ - if (!ip_addr_netcmp(&(iphdr->src), &(netif->ip_addr), &(netif->netmask))) { - /* do nothing */ - return; - } - - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); - /* update ARP table */ - /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk - * back soon (for example, if the destination IP address is ours. */ - update_arp_entry(netif, &(iphdr->src), &(ethhdr->src), 0); -} - - -/** - * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache - * send out queued IP packets. Updates cache with snooped address pairs. - * - * Should be called for incoming ARP packets. The pbuf in the argument - * is freed by this function. - * - * @param netif The lwIP network interface on which the ARP packet pbuf arrived. - * @param ethaddr Ethernet address of netif. - * @param p The ARP packet that arrived on netif. Is freed by this function. - * - * @return NULL - * - * @see pbuf_free() - */ -void -etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) -{ - struct etharp_hdr *hdr; - struct eth_hdr *ethhdr; - /* these are aligned properly, whereas the ARP header fields might not be */ - struct ip_addr sipaddr, dipaddr; - u8_t i; - u8_t for_us; -#if LWIP_AUTOIP - const u8_t * ethdst_hwaddr; -#endif /* LWIP_AUTOIP */ - - LWIP_ERROR("netif != NULL", (netif != NULL), return;); - - /* drop short ARP packets: we have to check for p->len instead of p->tot_len here - since a struct etharp_hdr is pointed to p->payload, so it musn't be chained! */ - if (p->len < SIZEOF_ETHARP_PACKET) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, - (s16_t)SIZEOF_ETHARP_PACKET)); - ETHARP_STATS_INC(etharp.lenerr); - ETHARP_STATS_INC(etharp.drop); - pbuf_free(p); - return; - } - - ethhdr = p->payload; - hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); -#if ETHARP_SUPPORT_VLAN - if (ethhdr->type == ETHTYPE_VLAN) { - hdr = (struct etharp_hdr *)(((u8_t*)ethhdr) + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR); - } -#endif /* ETHARP_SUPPORT_VLAN */ - - /* RFC 826 "Packet Reception": */ - if ((hdr->hwtype != htons(HWTYPE_ETHERNET)) || - (hdr->_hwlen_protolen != htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr))) || - (hdr->proto != htons(ETHTYPE_IP)) || - (ethhdr->type != htons(ETHTYPE_ARP))) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, - ("etharp_arp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", - hdr->hwtype, ARPH_HWLEN(hdr), hdr->proto, ARPH_PROTOLEN(hdr), ethhdr->type)); - ETHARP_STATS_INC(etharp.proterr); - ETHARP_STATS_INC(etharp.drop); - pbuf_free(p); - return; - } - ETHARP_STATS_INC(etharp.recv); - -#if LWIP_AUTOIP - /* We have to check if a host already has configured our random - * created link local address and continously check if there is - * a host with this IP-address so we can detect collisions */ - autoip_arp_reply(netif, hdr); -#endif /* LWIP_AUTOIP */ - - /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without - * structure packing (not using structure copy which breaks strict-aliasing rules). */ - SMEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr)); - SMEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr)); - - /* this interface is not configured? */ - if (netif->ip_addr.addr == 0) { - for_us = 0; - } else { - /* ARP packet directed to us? */ - for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr)); - } - - /* ARP message directed to us? */ - if (for_us) { - /* add IP address in ARP cache; assume requester wants to talk to us. - * can result in directly sending the queued packets for this host. */ - update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD); - /* ARP message not directed to us? */ - } else { - /* update the source IP address in the cache, if present */ - update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0); - } - - /* now act on the message itself */ - switch (htons(hdr->opcode)) { - /* ARP request? */ - case ARP_REQUEST: - /* ARP request. If it asked for our address, we send out a - * reply. In any case, we time-stamp any existing ARP entry, - * and possiby send out an IP packet that was queued on it. */ - - LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); - /* ARP request for our address? */ - if (for_us) { - - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); - /* Re-use pbuf to send ARP reply. - Since we are re-using an existing pbuf, we can't call etharp_raw since - that would allocate a new pbuf. */ - hdr->opcode = htons(ARP_REPLY); - - hdr->dipaddr = hdr->sipaddr; - SMEMCPY(&hdr->sipaddr, &netif->ip_addr, sizeof(hdr->sipaddr)); - - LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", - (netif->hwaddr_len == ETHARP_HWADDR_LEN)); - i = ETHARP_HWADDR_LEN; -#if LWIP_AUTOIP - /* If we are using Link-Local, ARP packets must be broadcast on the - * link layer. (See RFC3927 Section 2.5) */ - ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : hdr->shwaddr.addr; -#endif /* LWIP_AUTOIP */ - - while(i > 0) { - i--; - hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i]; -#if LWIP_AUTOIP - ethhdr->dest.addr[i] = ethdst_hwaddr[i]; -#else /* LWIP_AUTOIP */ - ethhdr->dest.addr[i] = hdr->shwaddr.addr[i]; -#endif /* LWIP_AUTOIP */ - hdr->shwaddr.addr[i] = ethaddr->addr[i]; - ethhdr->src.addr[i] = ethaddr->addr[i]; - } - - /* hwtype, hwaddr_len, proto, protolen and the type in the ethernet header - are already correct, we tested that before */ - - /* return ARP reply */ - netif->linkoutput(netif, p); - /* we are not configured? */ - } else if (netif->ip_addr.addr == 0) { - /* { for_us == 0 and netif->ip_addr.addr == 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); - /* request was not directed to us */ - } else { - /* { for_us == 0 and netif->ip_addr.addr != 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); - } - break; - case ARP_REPLY: - /* ARP reply. We already updated the ARP cache earlier. */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); -#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) - /* DHCP wants to know about ARP replies from any host with an - * IP address also offered to us by the DHCP server. We do not - * want to take a duplicate IP address on a single network. - * @todo How should we handle redundant (fail-over) interfaces? */ - dhcp_arp_reply(netif, &sipaddr); -#endif - break; - default: - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); - ETHARP_STATS_INC(etharp.err); - break; - } - /* free ARP packet */ - pbuf_free(p); -} - -/** - * Resolve and fill-in Ethernet address header for outgoing IP packet. - * - * For IP multicast and broadcast, corresponding Ethernet addresses - * are selected and the packet is transmitted on the link. - * - * For unicast addresses, the packet is submitted to etharp_query(). In - * case the IP address is outside the local network, the IP address of - * the gateway is used. - * - * @param netif The lwIP network interface which the IP packet will be sent on. - * @param q The pbuf(s) containing the IP packet to be sent. - * @param ipaddr The IP address of the packet destination. - * - * @return - * - ERR_RTE No route to destination (no gateway to external networks), - * or the return type of either etharp_query() or etharp_send_ip(). - */ -err_t -etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr) -{ - struct eth_addr *dest, mcastaddr; - - /* make room for Ethernet header - should not fail */ - if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { - /* bail out */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("etharp_output: could not allocate room for header.\n")); - LINK_STATS_INC(link.lenerr); - return ERR_BUF; - } - - /* assume unresolved Ethernet address */ - dest = NULL; - /* Determine on destination hardware address. Broadcasts and multicasts - * are special, other IP addresses are looked up in the ARP table. */ - - /* broadcast destination IP address? */ - if (ip_addr_isbroadcast(ipaddr, netif)) { - /* broadcast on Ethernet also */ - dest = (struct eth_addr *)ðbroadcast; - /* multicast destination IP address? */ - } else if (ip_addr_ismulticast(ipaddr)) { - /* Hash IP multicast address to MAC address.*/ - mcastaddr.addr[0] = 0x01; - mcastaddr.addr[1] = 0x00; - mcastaddr.addr[2] = 0x5e; - mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; - mcastaddr.addr[4] = ip4_addr3(ipaddr); - mcastaddr.addr[5] = ip4_addr4(ipaddr); - /* destination Ethernet address is multicast */ - dest = &mcastaddr; - /* unicast destination IP address? */ - } else { - /* outside local network? */ - if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { - /* interface has default gateway? */ - if (netif->gw.addr != 0) { - /* send to hardware address of default gateway IP address */ - ipaddr = &(netif->gw); - /* no default gateway available */ - } else { - /* no route to destination error (default gateway missing) */ - return ERR_RTE; - } - } - /* queue on destination Ethernet address belonging to ipaddr */ - return etharp_query(netif, ipaddr, q); - } - - /* continuation for multicast/broadcast destinations */ - /* obtain source Ethernet address of the given interface */ - /* send packet directly on the link */ - return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), dest); -} - -/** - * Send an ARP request for the given IP address and/or queue a packet. - * - * If the IP address was not yet in the cache, a pending ARP cache entry - * is added and an ARP request is sent for the given address. The packet - * is queued on this entry. - * - * If the IP address was already pending in the cache, a new ARP request - * is sent for the given address. The packet is queued on this entry. - * - * If the IP address was already stable in the cache, and a packet is - * given, it is directly sent and no ARP request is sent out. - * - * If the IP address was already stable in the cache, and no packet is - * given, an ARP request is sent out. - * - * @param netif The lwIP network interface on which ipaddr - * must be queried for. - * @param ipaddr The IP address to be resolved. - * @param q If non-NULL, a pbuf that must be delivered to the IP address. - * q is not freed by this function. - * - * @note q must only be ONE packet, not a packet queue! - * - * @return - * - ERR_BUF Could not make room for Ethernet header. - * - ERR_MEM Hardware address unknown, and no more ARP entries available - * to query for address or queue the packet. - * - ERR_MEM Could not queue packet due to memory shortage. - * - ERR_RTE No route to destination (no gateway to external networks). - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - */ -err_t -etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) -{ - struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; - err_t result = ERR_MEM; - s8_t i; /* ARP entry index */ - - /* non-unicast address? */ - if (ip_addr_isbroadcast(ipaddr, netif) || - ip_addr_ismulticast(ipaddr) || - ip_addr_isany(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - - /* find entry in ARP cache, ask to create entry if queueing packet */ -#if LWIP_NETIF_HWADDRHINT - i = find_entry(ipaddr, ETHARP_TRY_HARD, netif); -#else /* LWIP_NETIF_HWADDRHINT */ - i = find_entry(ipaddr, ETHARP_TRY_HARD); -#endif /* LWIP_NETIF_HWADDRHINT */ - - /* could not find or create entry? */ - if (i < 0) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); - if (q) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); - ETHARP_STATS_INC(etharp.memerr); - } - return (err_t)i; - } - - /* mark a fresh entry as pending (we just sent a request) */ - if (arp_table[i].state == ETHARP_STATE_EMPTY) { - arp_table[i].state = ETHARP_STATE_PENDING; - } - - /* { i is either a STABLE or (new or existing) PENDING entry } */ - LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", - ((arp_table[i].state == ETHARP_STATE_PENDING) || - (arp_table[i].state == ETHARP_STATE_STABLE))); - - /* do we have a pending entry? or an implicit query request? */ - if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { - /* try to resolve it; send out ARP request */ - result = etharp_request(netif, ipaddr); - if (result != ERR_OK) { - /* ARP request couldn't be sent */ - /* We don't re-send arp request in etharp_tmr, but we still queue packets, - since this failure could be temporary, and the next packet calling - etharp_query again could lead to sending the queued packets. */ - } - } - - /* packet given? */ - if (q != NULL) { - /* stable entry? */ - if (arp_table[i].state == ETHARP_STATE_STABLE) { - /* we have a valid IP->Ethernet address mapping */ - /* send the packet */ - result = etharp_send_ip(netif, q, srcaddr, &(arp_table[i].ethaddr)); - /* pending entry? (either just created or already pending */ - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { -#if ARP_QUEUEING /* queue the given q packet */ - struct pbuf *p; - int copy_needed = 0; - /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but - * to copy the whole queue into a new PBUF_RAM (see bug #11400) - * PBUF_ROMs can be left as they are, since ROM must not get changed. */ - p = q; - while (p) { - LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); - if(p->type != PBUF_ROM) { - copy_needed = 1; - break; - } - p = p->next; - } - if(copy_needed) { - /* copy the whole packet into new pbufs */ - p = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if(p != NULL) { - if (pbuf_copy(p, q) != ERR_OK) { - pbuf_free(p); - p = NULL; - } - } - } else { - /* referencing the old pbuf is enough */ - p = q; - pbuf_ref(p); - } - /* packet could be taken over? */ - if (p != NULL) { - /* queue packet ... */ - struct etharp_q_entry *new_entry; - /* allocate a new arp queue entry */ - new_entry = memp_malloc(MEMP_ARP_QUEUE); - if (new_entry != NULL) { - new_entry->next = 0; - new_entry->p = p; - if(arp_table[i].q != NULL) { - /* queue was already existent, append the new entry to the end */ - struct etharp_q_entry *r; - r = arp_table[i].q; - while (r->next != NULL) { - r = r->next; - } - r->next = new_entry; - } else { - /* queue did not exist, first item in queue */ - arp_table[i].q = new_entry; - } - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); - result = ERR_OK; - } else { - /* the pool MEMP_ARP_QUEUE is empty */ - pbuf_free(p); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); - /* { result == ERR_MEM } through initialization */ - } - } else { - ETHARP_STATS_INC(etharp.memerr); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); - /* { result == ERR_MEM } through initialization */ - } -#else /* ARP_QUEUEING == 0 */ - /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */ - /* { result == ERR_MEM } through initialization */ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q)); -#endif - } - } - return result; -} - -/** - * Send a raw ARP packet (opcode and all addresses can be modified) - * - * @param netif the lwip network interface on which to send the ARP packet - * @param ethsrc_addr the source MAC address for the ethernet header - * @param ethdst_addr the destination MAC address for the ethernet header - * @param hwsrc_addr the source MAC address for the ARP protocol header - * @param ipsrc_addr the source IP address for the ARP protocol header - * @param hwdst_addr the destination MAC address for the ARP protocol header - * @param ipdst_addr the destination IP address for the ARP protocol header - * @param opcode the type of the ARP packet - * @return ERR_OK if the ARP packet has been sent - * ERR_MEM if the ARP packet couldn't be allocated - * any other err_t on failure - */ -#if !LWIP_AUTOIP -static -#endif /* LWIP_AUTOIP */ -err_t -etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, - const struct eth_addr *ethdst_addr, - const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr, - const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr, - const u16_t opcode) -{ - struct pbuf *p; - err_t result = ERR_OK; - u8_t k; /* ARP entry index */ - struct eth_hdr *ethhdr; - struct etharp_hdr *hdr; -#if LWIP_AUTOIP - const u8_t * ethdst_hwaddr; -#endif /* LWIP_AUTOIP */ - - /* allocate a pbuf for the outgoing ARP request packet */ - p = pbuf_alloc(PBUF_RAW, SIZEOF_ETHARP_PACKET, PBUF_RAM); - /* could allocate a pbuf for an ARP request? */ - if (p == NULL) { - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, - ("etharp_raw: could not allocate pbuf for ARP request.\n")); - ETHARP_STATS_INC(etharp.memerr); - return ERR_MEM; - } - LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", - (p->len >= SIZEOF_ETHARP_PACKET)); - - ethhdr = p->payload; - hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); - hdr->opcode = htons(opcode); - - LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", - (netif->hwaddr_len == ETHARP_HWADDR_LEN)); - k = ETHARP_HWADDR_LEN; -#if LWIP_AUTOIP - /* If we are using Link-Local, ARP packets must be broadcast on the - * link layer. (See RFC3927 Section 2.5) */ - ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : ethdst_addr->addr; -#endif /* LWIP_AUTOIP */ - /* Write MAC-Addresses (combined loop for both headers) */ - while(k > 0) { - k--; - /* Write the ARP MAC-Addresses */ - hdr->shwaddr.addr[k] = hwsrc_addr->addr[k]; - hdr->dhwaddr.addr[k] = hwdst_addr->addr[k]; - /* Write the Ethernet MAC-Addresses */ -#if LWIP_AUTOIP - ethhdr->dest.addr[k] = ethdst_hwaddr[k]; -#else /* LWIP_AUTOIP */ - ethhdr->dest.addr[k] = ethdst_addr->addr[k]; -#endif /* LWIP_AUTOIP */ - ethhdr->src.addr[k] = ethsrc_addr->addr[k]; - } - hdr->sipaddr = *(struct ip_addr2 *)ipsrc_addr; - hdr->dipaddr = *(struct ip_addr2 *)ipdst_addr; - - hdr->hwtype = htons(HWTYPE_ETHERNET); - hdr->proto = htons(ETHTYPE_IP); - /* set hwlen and protolen together */ - hdr->_hwlen_protolen = htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr)); - - ethhdr->type = htons(ETHTYPE_ARP); - /* send ARP query */ - result = netif->linkoutput(netif, p); - ETHARP_STATS_INC(etharp.xmit); - /* free ARP query packet */ - pbuf_free(p); - p = NULL; - /* could not allocate pbuf for ARP request */ - - return result; -} - -/** - * Send an ARP request packet asking for ipaddr. - * - * @param netif the lwip network interface on which to send the request - * @param ipaddr the IP address for which to ask - * @return ERR_OK if the request has been sent - * ERR_MEM if the ARP packet couldn't be allocated - * any other err_t on failure - */ -err_t -etharp_request(struct netif *netif, struct ip_addr *ipaddr) -{ - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); - return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, - (struct eth_addr *)netif->hwaddr, &netif->ip_addr, ðzero, - ipaddr, ARP_REQUEST); -} - -/** - * Process received ethernet frames. Using this function instead of directly - * calling ip_input and passing ARP frames through etharp in ethernetif_input, - * the ARP cache is protected from concurrent access. - * - * @param p the recevied packet, p->payload pointing to the ethernet header - * @param netif the network interface on which the packet was received - */ -err_t -ethernet_input(struct pbuf *p, struct netif *netif) -{ - struct eth_hdr* ethhdr; - u16_t type; - - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, - ("ethernet_input: dest:%02x:%02x:%02x:%02x:%02x:%02x, src:%02x:%02x:%02x:%02x:%02x:%02x, type:%2hx\n", - (unsigned)ethhdr->dest.addr[0], (unsigned)ethhdr->dest.addr[1], (unsigned)ethhdr->dest.addr[2], - (unsigned)ethhdr->dest.addr[3], (unsigned)ethhdr->dest.addr[4], (unsigned)ethhdr->dest.addr[5], - (unsigned)ethhdr->src.addr[0], (unsigned)ethhdr->src.addr[1], (unsigned)ethhdr->src.addr[2], - (unsigned)ethhdr->src.addr[3], (unsigned)ethhdr->src.addr[4], (unsigned)ethhdr->src.addr[5], - (unsigned)htons(ethhdr->type))); - - type = htons(ethhdr->type); -#if ETHARP_SUPPORT_VLAN - if (type == ETHTYPE_VLAN) { - struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr*)(((char*)ethhdr) + SIZEOF_ETH_HDR); -#ifdef ETHARP_VLAN_CHECK /* if not, allow all VLANs */ - if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) { - /* silently ignore this packet: not for our VLAN */ - pbuf_free(p); - return ERR_OK; - } -#endif /* ETHARP_VLAN_CHECK */ - type = htons(vlan->tpid); - } -#endif /* ETHARP_SUPPORT_VLAN */ - - switch (type) { - /* IP packet? */ - case ETHTYPE_IP: -#if ETHARP_TRUST_IP_MAC - /* update ARP table */ - etharp_ip_input(netif, p); -#endif /* ETHARP_TRUST_IP_MAC */ - /* skip Ethernet header */ - if(pbuf_header(p, -(s16_t)SIZEOF_ETH_HDR)) { - LWIP_ASSERT("Can't move over header in packet", 0); - pbuf_free(p); - p = NULL; - } else { - /* pass to IP layer */ - ip_input(p, netif); - } - break; - - case ETHTYPE_ARP: - /* pass p to ARP module */ - etharp_arp_input(netif, (struct eth_addr*)(netif->hwaddr), p); - break; - -#if PPPOE_SUPPORT - case ETHTYPE_PPPOEDISC: /* PPP Over Ethernet Discovery Stage */ - pppoe_disc_input(netif, p); - break; - - case ETHTYPE_PPPOE: /* PPP Over Ethernet Session Stage */ - pppoe_data_input(netif, p); - break; -#endif /* PPPOE_SUPPORT */ - - default: - ETHARP_STATS_INC(etharp.proterr); - ETHARP_STATS_INC(etharp.drop); - pbuf_free(p); - p = NULL; - break; - } - - /* This means the pbuf is freed or consumed, - so the caller doesn't have to free it again */ - return ERR_OK; -} -#endif /* LWIP_ARP */ diff --git a/components/net/lwip-1.3.2/src/netif/ethernetif.c b/components/net/lwip-1.3.2/src/netif/ethernetif.c deleted file mode 100644 index 9ca59a377c..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ethernetif.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * File : ethernetif.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-07 Bernard fix send mail to mailbox issue. - * 2011-12-11 aozima list_if and set_if support multiple interface. - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/debug.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "lwip/netif.h" -#include "lwip/stats.h" -#include "lwip/tcpip.h" - -#include "netif/etharp.h" -#include "netif/ethernetif.h" - -/* eth rx/tx thread */ -static struct rt_mailbox eth_rx_thread_mb; -static struct rt_thread eth_rx_thread; -#ifndef RT_LWIP_ETHTHREAD_PRIORITY -#define RT_ETHERNETIF_THREAD_PREORITY 0x90 -static char eth_rx_thread_mb_pool[48 * 4]; -static char eth_rx_thread_stack[1024]; -#else -#define RT_ETHERNETIF_THREAD_PREORITY RT_LWIP_ETHTHREAD_PRIORITY -static char eth_rx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4]; -static char eth_rx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; -#endif - -struct eth_tx_msg -{ - struct netif *netif; - struct pbuf *buf; -}; -static struct rt_mailbox eth_tx_thread_mb; -static struct rt_thread eth_tx_thread; -#ifndef RT_LWIP_ETHTHREAD_PRIORITY -static char eth_tx_thread_mb_pool[32 * 4]; -static char eth_tx_thread_stack[512]; -#else -static char eth_tx_thread_mb_pool[RT_LWIP_ETHTHREAD_MBOX_SIZE * 4]; -static char eth_tx_thread_stack[RT_LWIP_ETHTHREAD_STACKSIZE]; -#endif - -err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) -{ - struct eth_tx_msg msg; - struct eth_device* enetif; - - enetif = (struct eth_device*)netif->state; - - /* send a message to eth tx thread */ - msg.netif = netif; - msg.buf = p; - if (rt_mb_send(ð_tx_thread_mb, (rt_uint32_t) &msg) == RT_EOK) - { - /* waiting for ack */ - rt_sem_take(&(enetif->tx_ack), RT_WAITING_FOREVER); - } - - return ERR_OK; -} - -/* ethernetif APIs */ -rt_err_t eth_device_init(struct eth_device* dev, const char* name) -{ - struct netif* netif; - - netif = (struct netif*) rt_malloc (sizeof(struct netif)); - if (netif == RT_NULL) - { - rt_kprintf("malloc netif failed\n"); - return -RT_ERROR; - } - rt_memset(netif, 0, sizeof(struct netif)); - - /* set netif */ - dev->netif = netif; - /* register to rt-thread device manager */ - rt_device_register(&(dev->parent), name, RT_DEVICE_FLAG_RDWR); - dev->parent.type = RT_Device_Class_NetIf; - rt_sem_init(&(dev->tx_ack), name, 0, RT_IPC_FLAG_FIFO); - - /* set name */ - netif->name[0] = name[0]; - netif->name[1] = name[1]; - - /* set hw address to 6 */ - netif->hwaddr_len = 6; - /* maximum transfer unit */ - netif->mtu = ETHERNET_MTU; - /* broadcast capability */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - -#if LWIP_IGMP - /* igmp support */ - netif->flags |= NETIF_FLAG_IGMP; -#endif - - /* get hardware address */ - rt_device_control(&(dev->parent), NIOCTL_GADDR, netif->hwaddr); - - /* set output */ - netif->output = etharp_output; - netif->linkoutput = ethernetif_linkoutput; - - return RT_EOK; -} - -/* ethernet buffer */ -void eth_tx_thread_entry(void* parameter) -{ - struct eth_tx_msg* msg; - - while (1) - { - if (rt_mb_recv(ð_tx_thread_mb, (rt_uint32_t*)&msg, RT_WAITING_FOREVER) == RT_EOK) - { - struct eth_device* enetif; - - RT_ASSERT(msg->netif != RT_NULL); - RT_ASSERT(msg->buf != RT_NULL); - - enetif = (struct eth_device*)msg->netif->state; - if (enetif != RT_NULL) - { - /* call driver's interface */ - if (enetif->eth_tx(&(enetif->parent), msg->buf) != RT_EOK) - { - rt_kprintf("transmit eth packet failed\n"); - } - } - - /* send ack */ - rt_sem_release(&(enetif->tx_ack)); - } - } -} - -/* ethernet buffer */ -void eth_rx_thread_entry(void* parameter) -{ - struct eth_device* device; - - while (1) - { - if (rt_mb_recv(ð_rx_thread_mb, (rt_uint32_t*)&device, RT_WAITING_FOREVER) == RT_EOK) - { - struct pbuf *p; - - /* check link status */ - if (device->link_changed) - { - int status; - rt_uint32_t level; - - level = rt_hw_interrupt_disable(); - status = device->link_status; - device->link_changed = 0x00; - rt_hw_interrupt_enable(level); - - if (status) - netifapi_netif_set_link_up(device->netif); - else - netifapi_netif_set_link_down(device->netif); - } - - /* receive all of buffer */ - while (1) - { - p = device->eth_rx(&(device->parent)); - if (p != RT_NULL) - { - /* notify to upper layer */ - if( device->netif->input(p, device->netif) != ERR_OK ) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: Input error\n")); - pbuf_free(p); - p = NULL; - } - } - else break; - } - } - } -} - -rt_err_t eth_rx_ready(struct eth_device* dev) -{ - /* post message to ethernet thread */ - return rt_mb_send(ð_rx_thread_mb, (rt_uint32_t)dev); -} - -rt_err_t eth_device_ready(struct eth_device* dev) -{ - return eth_rx_ready(dev); -} - -rt_err_t eth_device_linkchange(struct eth_device* dev, rt_bool_t up) -{ - rt_uint32_t level; - - RT_ASSERT(dev != RT_NULL); - - level = rt_hw_interrupt_disable(); - dev->link_changed = 0x01; - if (up == RT_TRUE) - dev->link_status = 0x01; - else - dev->link_status = 0x00; - rt_hw_interrupt_enable(level); - - /* post message to ethernet thread */ - return rt_mb_send(ð_rx_thread_mb, (rt_uint32_t)dev); -} - -rt_err_t eth_system_device_init() -{ - rt_err_t result = RT_EOK; - - /* init rx thread */ - /* init mailbox and create ethernet thread */ - result = rt_mb_init(ð_rx_thread_mb, "erxmb", - ð_rx_thread_mb_pool[0], sizeof(eth_rx_thread_mb_pool)/4, - RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_init(ð_rx_thread, "erx", eth_rx_thread_entry, RT_NULL, - ð_rx_thread_stack[0], sizeof(eth_rx_thread_stack), - RT_ETHERNETIF_THREAD_PREORITY, 16); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_startup(ð_rx_thread); - RT_ASSERT(result == RT_EOK); - - /* init tx thread */ - /* init mailbox and create ethernet thread */ - result = rt_mb_init(ð_tx_thread_mb, "etxmb", - ð_tx_thread_mb_pool[0], sizeof(eth_tx_thread_mb_pool)/4, - RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_init(ð_tx_thread, "etx", eth_tx_thread_entry, RT_NULL, - ð_tx_thread_stack[0], sizeof(eth_tx_thread_stack), - RT_ETHERNETIF_THREAD_PREORITY, 16); - RT_ASSERT(result == RT_EOK); - - result = rt_thread_startup(ð_tx_thread); - RT_ASSERT(result == RT_EOK); - - return result; -} - -#ifdef RT_USING_FINSH -#include -void set_if(char* netif_name, char* ip_addr, char* gw_addr, char* nm_addr) -{ - struct ip_addr *ip; - struct in_addr addr; - struct netif * netif = netif_list; - - if(strlen(netif_name) > sizeof(netif->name)) - { - rt_kprintf("network interface name too long!\r\n"); - return; - } - - while(netif != RT_NULL) - { - if(strncmp(netif_name, netif->name, sizeof(netif->name)) == 0) - break; - - netif = netif->next; - if( netif == RT_NULL ) - { - rt_kprintf("network interface: %s not found!\r\n", netif_name); - return; - } - } - - ip = (struct ip_addr *)&addr; - - /* set ip address */ - if ((ip_addr != RT_NULL) && inet_aton(ip_addr, &addr)) - { - netif_set_ipaddr(netif, ip); - } - - /* set gateway address */ - if ((gw_addr != RT_NULL) && inet_aton(gw_addr, &addr)) - { - netif_set_gw(netif, ip); - } - - /* set netmask address */ - if ((nm_addr != RT_NULL) && inet_aton(nm_addr, &addr)) - { - netif_set_netmask(netif, ip); - } -} -FINSH_FUNCTION_EXPORT(set_if, set network interface address); - -#if LWIP_DNS -#include -void set_dns(char* dns_server) -{ - struct in_addr addr; - - if ((dns_server != RT_NULL) && inet_aton(dns_server, &addr)) - { - dns_setserver(0, (struct ip_addr *)&addr); - } -} -FINSH_FUNCTION_EXPORT(set_dns, set DNS server address); -#endif - -void list_if(void) -{ - rt_ubase_t index; - struct netif * netif; - - netif = netif_list; - - while( netif != RT_NULL ) - { - rt_kprintf("network interface: %c%c%s\n", netif->name[0], netif->name[1], (netif == netif_default)?" (Default)":""); - rt_kprintf("MTU: %d\n", netif->mtu); - rt_kprintf("MAC: "); - for (index = 0; index < netif->hwaddr_len; index ++) - rt_kprintf("%02x ", netif->hwaddr[index]); - rt_kprintf("\nFLAGS:"); - if (netif->flags & NETIF_FLAG_UP) rt_kprintf(" UP"); - else rt_kprintf(" DOWN"); - if (netif->flags & NETIF_FLAG_LINK_UP) rt_kprintf(" LINK_UP"); - else rt_kprintf(" LINK_DOWN"); - if (netif->flags & NETIF_FLAG_DHCP) rt_kprintf(" DHCP"); - if (netif->flags & NETIF_FLAG_POINTTOPOINT) rt_kprintf(" PPP"); - if (netif->flags & NETIF_FLAG_ETHARP) rt_kprintf(" ETHARP"); - if (netif->flags & NETIF_FLAG_IGMP) rt_kprintf(" IGMP"); - rt_kprintf("\n"); - rt_kprintf("ip address: %s\n", inet_ntoa(*((struct in_addr*)&(netif->ip_addr)))); - rt_kprintf("gw address: %s\n", inet_ntoa(*((struct in_addr*)&(netif->gw)))); - rt_kprintf("net mask : %s\n", inet_ntoa(*((struct in_addr*)&(netif->netmask)))); - rt_kprintf("\r\n"); - - netif = netif->next; - } - -#if LWIP_DNS - { - struct ip_addr ip_addr; - - for(index=0; index -void list_tcps() -{ - struct tcp_pcb *pcb; - extern struct tcp_pcb *tcp_active_pcbs; - extern union tcp_listen_pcbs_t tcp_listen_pcbs; - extern struct tcp_pcb *tcp_tw_pcbs; - extern const char *tcp_state_str[]; - - rt_enter_critical(); - rt_kprintf("Active PCB states:\n"); - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) - { - rt_kprintf("%s:%d <==> %s:%d snd_nxt %d rcv_nxt %d ", - inet_ntoa(*((struct in_addr*)&(pcb->local_ip))), pcb->local_port, - inet_ntoa(*((struct in_addr*)&(pcb->remote_ip))), pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt); - rt_kprintf("state: %s\n", tcp_state_str[pcb->state]); - } - - rt_kprintf("Listen PCB states:\n"); - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) - { - rt_kprintf("local port %d ", pcb->local_port); - rt_kprintf("state: %s\n", tcp_state_str[pcb->state]); - } - - rt_kprintf("TIME-WAIT PCB states:\n"); - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) - { - rt_kprintf("%s:%d <==> %s:%d snd_nxt %d rcv_nxt %d ", - inet_ntoa(*((struct in_addr*)&(pcb->local_ip))), pcb->local_port, - inet_ntoa(*((struct in_addr*)&(pcb->remote_ip))), pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt); - rt_kprintf("state: %s\n", tcp_state_str[pcb->state]); - } - rt_exit_critical(); -} -FINSH_FUNCTION_EXPORT(list_tcps, list all of tcp pcb); - -#endif diff --git a/components/net/lwip-1.3.2/src/netif/ppp/auth.c b/components/net/lwip-1.3.2/src/netif/ppp/auth.c deleted file mode 100644 index cbd3eb21b0..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/auth.c +++ /dev/null @@ -1,990 +0,0 @@ -/***************************************************************************** -* auth.c - Network Authentication and Phase Control program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Ported from public pppd code. -*****************************************************************************/ -/* - * auth.c - PPP authentication and phase control. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "fsm.h" -#include "lcp.h" -#include "pap.h" -#include "chap.h" -#include "auth.h" -#include "ipcp.h" - -#if CBCP_SUPPORT -#include "cbcp.h" -#endif /* CBCP_SUPPORT */ - -#include - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -/* Bits in auth_pending[] */ -#define PAP_WITHPEER 1 -#define PAP_PEER 2 -#define CHAP_WITHPEER 4 -#define CHAP_PEER 8 - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -/* Used for storing a sequence of words. Usually malloced. */ -struct wordlist { - struct wordlist *next; - char word[1]; -}; - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -extern char *crypt (const char *, const char *); - -/* Prototypes for procedures local to this file. */ - -static void network_phase (int); -static void check_idle (void *); -static void connect_time_expired (void *); -#if 0 -static int login (char *, char *, char **, int *); -#endif -static void logout (void); -static int null_login (int); -static int get_pap_passwd (int, char *, char *); -static int have_pap_secret (void); -static int have_chap_secret (char *, char *, u32_t); -static int ip_addr_check (u32_t, struct wordlist *); -#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */ -static void set_allowed_addrs(int unit, struct wordlist *addrs); -static void free_wordlist (struct wordlist *); -#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */ -#if CBCP_SUPPORT -static void callback_phase (int); -#endif /* CBCP_SUPPORT */ - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -#if PAP_SUPPORT || CHAP_SUPPORT -/* The name by which the peer authenticated itself to us. */ -static char peer_authname[MAXNAMELEN]; -#endif /* PAP_SUPPORT || CHAP_SUPPORT */ - -/* Records which authentication operations haven't completed yet. */ -static int auth_pending[NUM_PPP]; - -/* Set if we have successfully called login() */ -static int logged_in; - -/* Set if we have run the /etc/ppp/auth-up script. */ -static int did_authup; - -/* List of addresses which the peer may use. */ -static struct wordlist *addresses[NUM_PPP]; - -/* Number of network protocols which we have opened. */ -static int num_np_open; - -/* Number of network protocols which have come up. */ -static int num_np_up; - -#if PAP_SUPPORT || CHAP_SUPPORT -/* Set if we got the contents of passwd[] from the pap-secrets file. */ -static int passwd_from_file; -#endif /* PAP_SUPPORT || CHAP_SUPPORT */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * An Open on LCP has requested a change from Dead to Establish phase. - * Do what's necessary to bring the physical layer up. - */ -void -link_required(int unit) -{ - LWIP_UNUSED_ARG(unit); - - AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit)); -} - -/* - * LCP has terminated the link; go to the Dead phase and take the - * physical layer down. - */ -void -link_terminated(int unit) -{ - AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit)); - if (lcp_phase[unit] == PHASE_DEAD) { - return; - } - if (logged_in) { - logout(); - } - lcp_phase[unit] = PHASE_DEAD; - AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n")); - pppLinkTerminated(unit); -} - -/* - * LCP has gone down; it will either die or try to re-establish. - */ -void -link_down(int unit) -{ - int i; - struct protent *protp; - - AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit)); - if (did_authup) { - /* XXX Do link down processing. */ - did_authup = 0; - } - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (!protp->enabled_flag) { - continue; - } - if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) { - (*protp->lowerdown)(unit); - } - if (protp->protocol < 0xC000 && protp->close != NULL) { - (*protp->close)(unit, "LCP down"); - } - } - num_np_open = 0; - num_np_up = 0; - if (lcp_phase[unit] != PHASE_DEAD) { - lcp_phase[unit] = PHASE_TERMINATE; - } - pppLinkDown(unit); -} - -/* - * The link is established. - * Proceed to the Dead, Authenticate or Network phase as appropriate. - */ -void -link_established(int unit) -{ - int auth; - int i; - struct protent *protp; - lcp_options *wo = &lcp_wantoptions[unit]; - lcp_options *go = &lcp_gotoptions[unit]; -#if PAP_SUPPORT || CHAP_SUPPORT - lcp_options *ho = &lcp_hisoptions[unit]; -#endif /* PAP_SUPPORT || CHAP_SUPPORT */ - - AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit)); - /* - * Tell higher-level protocols that LCP is up. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (protp->protocol != PPP_LCP && protp->enabled_flag && protp->lowerup != NULL) { - (*protp->lowerup)(unit); - } - } - if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) { - /* - * We wanted the peer to authenticate itself, and it refused: - * treat it as though it authenticated with PAP using a username - * of "" and a password of "". If that's not OK, boot it out. - */ - if (!wo->neg_upap || !null_login(unit)) { - AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n")); - lcp_close(unit, "peer refused to authenticate"); - return; - } - } - - lcp_phase[unit] = PHASE_AUTHENTICATE; - auth = 0; -#if CHAP_SUPPORT - if (go->neg_chap) { - ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype); - auth |= CHAP_PEER; - } -#endif /* CHAP_SUPPORT */ -#if PAP_SUPPORT && CHAP_SUPPORT - else -#endif /* PAP_SUPPORT && CHAP_SUPPORT */ -#if PAP_SUPPORT - if (go->neg_upap) { - upap_authpeer(unit); - auth |= PAP_PEER; - } -#endif /* PAP_SUPPORT */ -#if CHAP_SUPPORT - if (ho->neg_chap) { - ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype); - auth |= CHAP_WITHPEER; - } -#endif /* CHAP_SUPPORT */ -#if PAP_SUPPORT && CHAP_SUPPORT - else -#endif /* PAP_SUPPORT && CHAP_SUPPORT */ -#if PAP_SUPPORT - if (ho->neg_upap) { - if (ppp_settings.passwd[0] == 0) { - passwd_from_file = 1; - if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) { - AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n")); - } - } - upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd); - auth |= PAP_WITHPEER; - } -#endif /* PAP_SUPPORT */ - auth_pending[unit] = auth; - - if (!auth) { - network_phase(unit); - } -} - -/* - * The peer has failed to authenticate himself using `protocol'. - */ -void -auth_peer_fail(int unit, u16_t protocol) -{ - LWIP_UNUSED_ARG(protocol); - - AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol)); - /* - * Authentication failure: take the link down - */ - lcp_close(unit, "Authentication failed"); -} - - -#if PAP_SUPPORT || CHAP_SUPPORT -/* - * The peer has been successfully authenticated using `protocol'. - */ -void -auth_peer_success(int unit, u16_t protocol, char *name, int namelen) -{ - int pbit; - - AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol)); - switch (protocol) { - case PPP_CHAP: - pbit = CHAP_PEER; - break; - case PPP_PAP: - pbit = PAP_PEER; - break; - default: - AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", protocol)); - return; - } - - /* - * Save the authenticated name of the peer for later. - */ - if (namelen > sizeof(peer_authname) - 1) { - namelen = sizeof(peer_authname) - 1; - } - BCOPY(name, peer_authname, namelen); - peer_authname[namelen] = 0; - - /* - * If there is no more authentication still to be done, - * proceed to the network (or callback) phase. - */ - if ((auth_pending[unit] &= ~pbit) == 0) { - network_phase(unit); - } -} - -/* - * We have failed to authenticate ourselves to the peer using `protocol'. - */ -void -auth_withpeer_fail(int unit, u16_t protocol) -{ - int errCode = PPPERR_AUTHFAIL; - - LWIP_UNUSED_ARG(protocol); - - AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol)); - if (passwd_from_file) { - BZERO(ppp_settings.passwd, MAXSECRETLEN); - } - /* - * XXX Warning: the unit number indicates the interface which is - * not necessarily the PPP connection. It works here as long - * as we are only supporting PPP interfaces. - */ - pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode); - - /* - * We've failed to authenticate ourselves to our peer. - * He'll probably take the link down, and there's not much - * we can do except wait for that. - */ -} - -/* - * We have successfully authenticated ourselves with the peer using `protocol'. - */ -void -auth_withpeer_success(int unit, u16_t protocol) -{ - int pbit; - - AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol)); - switch (protocol) { - case PPP_CHAP: - pbit = CHAP_WITHPEER; - break; - case PPP_PAP: - if (passwd_from_file) { - BZERO(ppp_settings.passwd, MAXSECRETLEN); - } - pbit = PAP_WITHPEER; - break; - default: - AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", protocol)); - pbit = 0; - } - - /* - * If there is no more authentication still being done, - * proceed to the network (or callback) phase. - */ - if ((auth_pending[unit] &= ~pbit) == 0) { - network_phase(unit); - } -} -#endif /* PAP_SUPPORT || CHAP_SUPPORT */ - - -/* - * np_up - a network protocol has come up. - */ -void -np_up(int unit, u16_t proto) -{ - LWIP_UNUSED_ARG(unit); - LWIP_UNUSED_ARG(proto); - - AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto)); - if (num_np_up == 0) { - AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit)); - /* - * At this point we consider that the link has come up successfully. - */ - if (ppp_settings.idle_time_limit > 0) { - TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit); - } - - /* - * Set a timeout to close the connection once the maximum - * connect time has expired. - */ - if (ppp_settings.maxconnect > 0) { - TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect); - } - } - ++num_np_up; -} - -/* - * np_down - a network protocol has gone down. - */ -void -np_down(int unit, u16_t proto) -{ - LWIP_UNUSED_ARG(unit); - LWIP_UNUSED_ARG(proto); - - AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto)); - if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) { - UNTIMEOUT(check_idle, NULL); - } -} - -/* - * np_finished - a network protocol has finished using the link. - */ -void -np_finished(int unit, u16_t proto) -{ - LWIP_UNUSED_ARG(unit); - LWIP_UNUSED_ARG(proto); - - AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto)); - if (--num_np_open <= 0) { - /* no further use for the link: shut up shop. */ - lcp_close(0, "No network protocols running"); - } -} - -/* - * auth_reset - called when LCP is starting negotiations to recheck - * authentication options, i.e. whether we have appropriate secrets - * to use for authenticating ourselves and/or the peer. - */ -void -auth_reset(int unit) -{ - lcp_options *go = &lcp_gotoptions[unit]; - lcp_options *ao = &lcp_allowoptions[0]; - ipcp_options *ipwo = &ipcp_wantoptions[0]; - u32_t remote; - - AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit)); - ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL)); - ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/; - - if (go->neg_upap && !have_pap_secret()) { - go->neg_upap = 0; - } - if (go->neg_chap) { - remote = ipwo->accept_remote? 0: ipwo->hisaddr; - if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) { - go->neg_chap = 0; - } - } -} - -#if PAP_SUPPORT -/* - * check_passwd - Check the user name and passwd against the PAP secrets - * file. If requested, also check against the system password database, - * and login the user if OK. - * - * returns: - * UPAP_AUTHNAK: Authentication failed. - * UPAP_AUTHACK: Authentication succeeded. - * In either case, msg points to an appropriate message. - */ -int -check_passwd( int unit, char *auser, int userlen, char *apasswd, int passwdlen, char **msg, int *msglen) -{ -#if 1 - LWIP_UNUSED_ARG(unit); - LWIP_UNUSED_ARG(auser); - LWIP_UNUSED_ARG(userlen); - LWIP_UNUSED_ARG(apasswd); - LWIP_UNUSED_ARG(passwdlen); - LWIP_UNUSED_ARG(msglen); - *msg = (char *) 0; - return UPAP_AUTHACK; /* XXX Assume all entries OK. */ -#else - int ret = 0; - struct wordlist *addrs = NULL; - char passwd[256], user[256]; - char secret[MAXWORDLEN]; - static u_short attempts = 0; - - /* - * Make copies of apasswd and auser, then null-terminate them. - */ - BCOPY(apasswd, passwd, passwdlen); - passwd[passwdlen] = '\0'; - BCOPY(auser, user, userlen); - user[userlen] = '\0'; - *msg = (char *) 0; - - /* XXX Validate user name and password. */ - ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */ - - if (ret == UPAP_AUTHNAK) { - if (*msg == (char *) 0) { - *msg = "Login incorrect"; - } - *msglen = strlen(*msg); - /* - * Frustrate passwd stealer programs. - * Allow 10 tries, but start backing off after 3 (stolen from login). - * On 10'th, drop the connection. - */ - if (attempts++ >= 10) { - AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user)); - /*ppp_panic("Excess Bad Logins");*/ - } - if (attempts > 3) { - sys_msleep((attempts - 3) * 5); - } - if (addrs != NULL) { - free_wordlist(addrs); - } - } else { - attempts = 0; /* Reset count */ - if (*msg == (char *) 0) { - *msg = "Login ok"; - } - *msglen = strlen(*msg); - set_allowed_addrs(unit, addrs); - } - - BZERO(passwd, sizeof(passwd)); - BZERO(secret, sizeof(secret)); - - return ret; -#endif -} -#endif /* PAP_SUPPORT */ - - -/* - * auth_ip_addr - check whether the peer is authorized to use - * a given IP address. Returns 1 if authorized, 0 otherwise. - */ -int -auth_ip_addr(int unit, u32_t addr) -{ - return ip_addr_check(addr, addresses[unit]); -} - -/* - * bad_ip_adrs - return 1 if the IP address is one we don't want - * to use, such as an address in the loopback net or a multicast address. - * addr is in network byte order. - */ -int -bad_ip_adrs(u32_t addr) -{ - addr = ntohl(addr); - return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET - || IN_MULTICAST(addr) || IN_BADCLASS(addr); -} - - -#if CHAP_SUPPORT -/* - * get_secret - open the CHAP secret file and return the secret - * for authenticating the given client on the given server. - * (We could be either client or server). - */ -int get_secret( int unit, char *client, char *server, char *secret, int *secret_len, int save_addrs) -{ -#if 1 - int len; - struct wordlist *addrs; - - LWIP_UNUSED_ARG(unit); - LWIP_UNUSED_ARG(server); - LWIP_UNUSED_ARG(save_addrs); - - addrs = NULL; - - if(!client || !client[0] || strcmp(client, ppp_settings.user)) { - return 0; - } - - len = strlen(ppp_settings.passwd); - if (len > MAXSECRETLEN) { - AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); - len = MAXSECRETLEN; - } - - BCOPY(ppp_settings.passwd, secret, len); - *secret_len = len; - - return 1; -#else - int ret = 0, len; - struct wordlist *addrs; - char secbuf[MAXWORDLEN]; - - addrs = NULL; - secbuf[0] = 0; - - /* XXX Find secret. */ - if (ret < 0) { - return 0; - } - - if (save_addrs) { - set_allowed_addrs(unit, addrs); - } - - len = strlen(secbuf); - if (len > MAXSECRETLEN) { - AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); - len = MAXSECRETLEN; - } - - BCOPY(secbuf, secret, len); - BZERO(secbuf, sizeof(secbuf)); - *secret_len = len; - - return 1; -#endif -} -#endif /* CHAP_SUPPORT */ - - -#if 0 /* UNUSED */ -/* - * auth_check_options - called to check authentication options. - */ -void -auth_check_options(void) -{ - lcp_options *wo = &lcp_wantoptions[0]; - int can_auth; - ipcp_options *ipwo = &ipcp_wantoptions[0]; - u32_t remote; - - /* Default our_name to hostname, and user to our_name */ - if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) { - strcpy(ppp_settings.our_name, ppp_settings.hostname); - } - - if (ppp_settings.user[0] == 0) { - strcpy(ppp_settings.user, ppp_settings.our_name); - } - - /* If authentication is required, ask peer for CHAP or PAP. */ - if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) { - wo->neg_chap = 1; - wo->neg_upap = 1; - } - - /* - * Check whether we have appropriate secrets to use - * to authenticate the peer. - */ - can_auth = wo->neg_upap && have_pap_secret(); - if (!can_auth && wo->neg_chap) { - remote = ipwo->accept_remote? 0: ipwo->hisaddr; - can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote); - } - - if (ppp_settings.auth_required && !can_auth) { - ppp_panic("No auth secret"); - } -} -#endif - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * Proceed to the network phase. - */ -static void -network_phase(int unit) -{ - int i; - struct protent *protp; - lcp_options *go = &lcp_gotoptions[unit]; - - /* - * If the peer had to authenticate, run the auth-up script now. - */ - if ((go->neg_chap || go->neg_upap) && !did_authup) { - /* XXX Do setup for peer authentication. */ - did_authup = 1; - } - -#if CBCP_SUPPORT - /* - * If we negotiated callback, do it now. - */ - if (go->neg_cbcp) { - lcp_phase[unit] = PHASE_CALLBACK; - (*cbcp_protent.open)(unit); - return; - } -#endif /* CBCP_SUPPORT */ - - lcp_phase[unit] = PHASE_NETWORK; - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (protp->protocol < 0xC000 && protp->enabled_flag && protp->open != NULL) { - (*protp->open)(unit); - if (protp->protocol != PPP_CCP) { - ++num_np_open; - } - } - } - - if (num_np_open == 0) { - /* nothing to do */ - lcp_close(0, "No network protocols running"); - } -} - -/* - * check_idle - check whether the link has been idle for long - * enough that we can shut it down. - */ -static void -check_idle(void *arg) -{ - struct ppp_idle idle; - u_short itime; - - LWIP_UNUSED_ARG(arg); - if (!get_idle_time(0, &idle)) { - return; - } - itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); - if (itime >= ppp_settings.idle_time_limit) { - /* link is idle: shut it down. */ - AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n")); - lcp_close(0, "Link inactive"); - } else { - TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime); - } -} - -/* - * connect_time_expired - log a message and close the connection. - */ -static void -connect_time_expired(void *arg) -{ - LWIP_UNUSED_ARG(arg); - - AUTHDEBUG((LOG_INFO, "Connect time expired\n")); - lcp_close(0, "Connect time expired"); /* Close connection */ -} - -#if 0 -/* - * login - Check the user name and password against the system - * password database, and login the user if OK. - * - * returns: - * UPAP_AUTHNAK: Login failed. - * UPAP_AUTHACK: Login succeeded. - * In either case, msg points to an appropriate message. - */ -static int -login(char *user, char *passwd, char **msg, int *msglen) -{ - /* XXX Fail until we decide that we want to support logins. */ - return (UPAP_AUTHNAK); -} -#endif - -/* - * logout - Logout the user. - */ -static void -logout(void) -{ - logged_in = 0; -} - -/* - * null_login - Check if a username of "" and a password of "" are - * acceptable, and iff so, set the list of acceptable IP addresses - * and return 1. - */ -static int -null_login(int unit) -{ - LWIP_UNUSED_ARG(unit); - /* XXX Fail until we decide that we want to support logins. */ - return 0; -} - -/* - * get_pap_passwd - get a password for authenticating ourselves with - * our peer using PAP. Returns 1 on success, 0 if no suitable password - * could be found. - */ -static int -get_pap_passwd(int unit, char *user, char *passwd) -{ - LWIP_UNUSED_ARG(unit); -/* normally we would reject PAP if no password is provided, - but this causes problems with some providers (like CHT in Taiwan) - who incorrectly request PAP and expect a bogus/empty password, so - always provide a default user/passwd of "none"/"none" -*/ - if(user) { - strcpy(user, "none"); - } - if(passwd) { - strcpy(passwd, "none"); - } - return 1; -} - -/* - * have_pap_secret - check whether we have a PAP file with any - * secrets that we could possibly use for authenticating the peer. - */ -static int -have_pap_secret(void) -{ - /* XXX Fail until we set up our passwords. */ - return 0; -} - -/* - * have_chap_secret - check whether we have a CHAP file with a - * secret that we could possibly use for authenticating `client' - * on `server'. Either can be the null string, meaning we don't - * know the identity yet. - */ -static int -have_chap_secret(char *client, char *server, u32_t remote) -{ - LWIP_UNUSED_ARG(client); - LWIP_UNUSED_ARG(server); - LWIP_UNUSED_ARG(remote); - /* XXX Fail until we set up our passwords. */ - return 0; -} - -#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */ -/* - * set_allowed_addrs() - set the list of allowed addresses. - */ -static void -set_allowed_addrs(int unit, struct wordlist *addrs) -{ - if (addresses[unit] != NULL) { - free_wordlist(addresses[unit]); - } - addresses[unit] = addrs; - -#if 0 - /* - * If there's only one authorized address we might as well - * ask our peer for that one right away - */ - if (addrs != NULL && addrs->next == NULL) { - char *p = addrs->word; - struct ipcp_options *wo = &ipcp_wantoptions[unit]; - u32_t a; - struct hostent *hp; - - if (wo->hisaddr == 0 && *p != '!' && *p != '-' && strchr(p, '/') == NULL) { - hp = gethostbyname(p); - if (hp != NULL && hp->h_addrtype == AF_INET) { - a = *(u32_t *)hp->h_addr; - } else { - a = inet_addr(p); - } - if (a != (u32_t) -1) { - wo->hisaddr = a; - } - } - } -#endif -} -#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */ - -static int -ip_addr_check(u32_t addr, struct wordlist *addrs) -{ - /* don't allow loopback or multicast address */ - if (bad_ip_adrs(addr)) { - return 0; - } - - if (addrs == NULL) { - return !ppp_settings.auth_required; /* no addresses authorized */ - } - - /* XXX All other addresses allowed. */ - return 1; -} - -#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */ -/* - * free_wordlist - release memory allocated for a wordlist. - */ -static void -free_wordlist(struct wordlist *wp) -{ - struct wordlist *next; - - while (wp != NULL) { - next = wp->next; - free(wp); - wp = next; - } -} -#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/auth.h b/components/net/lwip-1.3.2/src/netif/ppp/auth.h deleted file mode 100644 index 86ff04945a..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/auth.h +++ /dev/null @@ -1,111 +0,0 @@ -/***************************************************************************** -* auth.h - PPP Authentication and phase control header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD pppd.h. -*****************************************************************************/ -/* - * pppd.h - PPP daemon global declarations. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - */ - -#ifndef AUTH_H -#define AUTH_H - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -/* we are starting to use the link */ -void link_required (int); - -/* we are finished with the link */ -void link_terminated (int); - -/* the LCP layer has left the Opened state */ -void link_down (int); - -/* the link is up; authenticate now */ -void link_established (int); - -/* a network protocol has come up */ -void np_up (int, u16_t); - -/* a network protocol has gone down */ -void np_down (int, u16_t); - -/* a network protocol no longer needs link */ -void np_finished (int, u16_t); - -/* peer failed to authenticate itself */ -void auth_peer_fail (int, u16_t); - -/* peer successfully authenticated itself */ -void auth_peer_success (int, u16_t, char *, int); - -/* we failed to authenticate ourselves */ -void auth_withpeer_fail (int, u16_t); - -/* we successfully authenticated ourselves */ -void auth_withpeer_success (int, u16_t); - -/* check authentication options supplied */ -void auth_check_options (void); - -/* check what secrets we have */ -void auth_reset (int); - -/* Check peer-supplied username/password */ -int check_passwd (int, char *, int, char *, int, char **, int *); - -/* get "secret" for chap */ -int get_secret (int, char *, char *, char *, int *, int); - -/* check if IP address is authorized */ -int auth_ip_addr (int, u32_t); - -/* check if IP address is unreasonable */ -int bad_ip_adrs (u32_t); - -#endif /* AUTH_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/chap.c b/components/net/lwip-1.3.2/src/netif/ppp/chap.c deleted file mode 100644 index b3ea6b2220..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/chap.c +++ /dev/null @@ -1,903 +0,0 @@ -/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/ -/***************************************************************************** -* chap.c - Network Challenge Handshake Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD chap.c. -*****************************************************************************/ -/* - * chap.c - Challenge Handshake Authentication Protocol. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1991 Gregory M. Christy. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Gregory M. Christy. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#if CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "magic.h" -#include "randm.h" -#include "auth.h" -#include "md5.h" -#include "chap.h" -#include "chpms.h" - -#include - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Protocol entry points. - */ -static void ChapInit (int); -static void ChapLowerUp (int); -static void ChapLowerDown (int); -static void ChapInput (int, u_char *, int); -static void ChapProtocolReject (int); -#if 0 -static int ChapPrintPkt (u_char *, int, void (*) (void *, char *, ...), void *); -#endif - -static void ChapChallengeTimeout (void *); -static void ChapResponseTimeout (void *); -static void ChapReceiveChallenge (chap_state *, u_char *, int, int); -static void ChapRechallenge (void *); -static void ChapReceiveResponse (chap_state *, u_char *, int, int); -static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len); -static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len); -static void ChapSendStatus (chap_state *, int); -static void ChapSendChallenge (chap_state *); -static void ChapSendResponse (chap_state *); -static void ChapGenChallenge (chap_state *); - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */ - -struct protent chap_protent = { - PPP_CHAP, - ChapInit, - ChapInput, - ChapProtocolReject, - ChapLowerUp, - ChapLowerDown, - NULL, - NULL, -#if 0 - ChapPrintPkt, - NULL, -#endif - 1, - "CHAP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * ChapAuthWithPeer - Authenticate us with our peer (start client). - * - */ -void -ChapAuthWithPeer(int unit, char *our_name, int digest) -{ - chap_state *cstate = &chap[unit]; - - cstate->resp_name = our_name; - cstate->resp_type = digest; - - if (cstate->clientstate == CHAPCS_INITIAL || - cstate->clientstate == CHAPCS_PENDING) { - /* lower layer isn't up - wait until later */ - cstate->clientstate = CHAPCS_PENDING; - return; - } - - /* - * We get here as a result of LCP coming up. - * So even if CHAP was open before, we will - * have to re-authenticate ourselves. - */ - cstate->clientstate = CHAPCS_LISTEN; -} - - -/* - * ChapAuthPeer - Authenticate our peer (start server). - */ -void -ChapAuthPeer(int unit, char *our_name, int digest) -{ - chap_state *cstate = &chap[unit]; - - cstate->chal_name = our_name; - cstate->chal_type = digest; - - if (cstate->serverstate == CHAPSS_INITIAL || - cstate->serverstate == CHAPSS_PENDING) { - /* lower layer isn't up - wait until later */ - cstate->serverstate = CHAPSS_PENDING; - return; - } - - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); /* crank it up dude! */ - cstate->serverstate = CHAPSS_INITIAL_CHAL; -} - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * ChapInit - Initialize a CHAP unit. - */ -static void -ChapInit(int unit) -{ - chap_state *cstate = &chap[unit]; - - BZERO(cstate, sizeof(*cstate)); - cstate->unit = unit; - cstate->clientstate = CHAPCS_INITIAL; - cstate->serverstate = CHAPSS_INITIAL; - cstate->timeouttime = CHAP_DEFTIMEOUT; - cstate->max_transmits = CHAP_DEFTRANSMITS; - /* random number generator is initialized in magic_init */ -} - - -/* - * ChapChallengeTimeout - Timeout expired on sending challenge. - */ -static void -ChapChallengeTimeout(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending challenges, don't worry. then again we */ - /* probably shouldn't be here either */ - if (cstate->serverstate != CHAPSS_INITIAL_CHAL && - cstate->serverstate != CHAPSS_RECHALLENGE) { - return; - } - - if (cstate->chal_transmits >= cstate->max_transmits) { - /* give up on peer */ - CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n")); - cstate->serverstate = CHAPSS_BADAUTH; - auth_peer_fail(cstate->unit, PPP_CHAP); - return; - } - - ChapSendChallenge(cstate); /* Re-send challenge */ -} - - -/* - * ChapResponseTimeout - Timeout expired on sending response. - */ -static void -ChapResponseTimeout(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending a response, don't worry. */ - if (cstate->clientstate != CHAPCS_RESPONSE) { - return; - } - - ChapSendResponse(cstate); /* re-send response */ -} - - -/* - * ChapRechallenge - Time to challenge the peer again. - */ -static void -ChapRechallenge(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending a response, don't worry. */ - if (cstate->serverstate != CHAPSS_OPEN) { - return; - } - - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); - cstate->serverstate = CHAPSS_RECHALLENGE; -} - - -/* - * ChapLowerUp - The lower layer is up. - * - * Start up if we have pending requests. - */ -static void -ChapLowerUp(int unit) -{ - chap_state *cstate = &chap[unit]; - - if (cstate->clientstate == CHAPCS_INITIAL) { - cstate->clientstate = CHAPCS_CLOSED; - } else if (cstate->clientstate == CHAPCS_PENDING) { - cstate->clientstate = CHAPCS_LISTEN; - } - - if (cstate->serverstate == CHAPSS_INITIAL) { - cstate->serverstate = CHAPSS_CLOSED; - } else if (cstate->serverstate == CHAPSS_PENDING) { - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); - cstate->serverstate = CHAPSS_INITIAL_CHAL; - } -} - - -/* - * ChapLowerDown - The lower layer is down. - * - * Cancel all timeouts. - */ -static void -ChapLowerDown(int unit) -{ - chap_state *cstate = &chap[unit]; - - /* Timeout(s) pending? Cancel if so. */ - if (cstate->serverstate == CHAPSS_INITIAL_CHAL || - cstate->serverstate == CHAPSS_RECHALLENGE) { - UNTIMEOUT(ChapChallengeTimeout, cstate); - } else if (cstate->serverstate == CHAPSS_OPEN - && cstate->chal_interval != 0) { - UNTIMEOUT(ChapRechallenge, cstate); - } - if (cstate->clientstate == CHAPCS_RESPONSE) { - UNTIMEOUT(ChapResponseTimeout, cstate); - } - cstate->clientstate = CHAPCS_INITIAL; - cstate->serverstate = CHAPSS_INITIAL; -} - - -/* - * ChapProtocolReject - Peer doesn't grok CHAP. - */ -static void -ChapProtocolReject(int unit) -{ - chap_state *cstate = &chap[unit]; - - if (cstate->serverstate != CHAPSS_INITIAL && - cstate->serverstate != CHAPSS_CLOSED) { - auth_peer_fail(unit, PPP_CHAP); - } - if (cstate->clientstate != CHAPCS_INITIAL && - cstate->clientstate != CHAPCS_CLOSED) { - auth_withpeer_fail(unit, PPP_CHAP); - } - ChapLowerDown(unit); /* shutdown chap */ -} - - -/* - * ChapInput - Input CHAP packet. - */ -static void -ChapInput(int unit, u_char *inpacket, int packet_len) -{ - chap_state *cstate = &chap[unit]; - u_char *inp; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - inp = inpacket; - if (packet_len < CHAP_HEADERLEN) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < CHAP_HEADERLEN) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n")); - return; - } - if (len > packet_len) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n")); - return; - } - len -= CHAP_HEADERLEN; - - /* - * Action depends on code (as in fact it usually does :-). - */ - switch (code) { - case CHAP_CHALLENGE: - ChapReceiveChallenge(cstate, inp, id, len); - break; - - case CHAP_RESPONSE: - ChapReceiveResponse(cstate, inp, id, len); - break; - - case CHAP_FAILURE: - ChapReceiveFailure(cstate, inp, id, len); - break; - - case CHAP_SUCCESS: - ChapReceiveSuccess(cstate, inp, id, len); - break; - - default: /* Need code reject? */ - CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code)); - break; - } -} - - -/* - * ChapReceiveChallenge - Receive Challenge and send Response. - */ -static void -ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len) -{ - int rchallenge_len; - u_char *rchallenge; - int secret_len; - char secret[MAXSECRETLEN]; - char rhostname[256]; - MD5_CTX mdContext; - u_char hash[MD5_SIGNATURE_SIZE]; - - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id)); - if (cstate->clientstate == CHAPCS_CLOSED || - cstate->clientstate == CHAPCS_PENDING) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n", - cstate->clientstate)); - return; - } - - if (len < 2) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); - return; - } - - GETCHAR(rchallenge_len, inp); - len -= sizeof (u_char) + rchallenge_len; /* now name field length */ - if (len < 0) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); - return; - } - rchallenge = inp; - INCPTR(rchallenge_len, inp); - - if (len >= sizeof(rhostname)) { - len = sizeof(rhostname) - 1; - } - BCOPY(inp, rhostname, len); - rhostname[len] = '\000'; - - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", rhostname)); - - /* Microsoft doesn't send their name back in the PPP packet */ - if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) { - strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname)); - rhostname[sizeof(rhostname) - 1] = 0; - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", rhostname)); - } - - /* get secret for authenticating ourselves with the specified host */ - if (!get_secret(cstate->unit, cstate->resp_name, rhostname, secret, &secret_len, 0)) { - secret_len = 0; /* assume null secret if can't find one */ - CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname)); - } - - /* cancel response send timeout if necessary */ - if (cstate->clientstate == CHAPCS_RESPONSE) { - UNTIMEOUT(ChapResponseTimeout, cstate); - } - - cstate->resp_id = id; - cstate->resp_transmits = 0; - - /* generate MD based on negotiated type */ - switch (cstate->resp_type) { - - case CHAP_DIGEST_MD5: - MD5Init(&mdContext); - MD5Update(&mdContext, &cstate->resp_id, 1); - MD5Update(&mdContext, (u_char*)secret, secret_len); - MD5Update(&mdContext, rchallenge, rchallenge_len); - MD5Final(hash, &mdContext); - BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE); - cstate->resp_length = MD5_SIGNATURE_SIZE; - break; - -#ifdef CHAPMS - case CHAP_MICROSOFT: - ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len); - break; -#endif - - default: - CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type)); - return; - } - - BZERO(secret, sizeof(secret)); - ChapSendResponse(cstate); -} - - -/* - * ChapReceiveResponse - Receive and process response. - */ -static void -ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len) -{ - u_char *remmd, remmd_len; - int secret_len, old_state; - int code; - char rhostname[256]; - MD5_CTX mdContext; - char secret[MAXSECRETLEN]; - u_char hash[MD5_SIGNATURE_SIZE]; - - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id)); - - if (cstate->serverstate == CHAPSS_CLOSED || - cstate->serverstate == CHAPSS_PENDING) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n", - cstate->serverstate)); - return; - } - - if (id != cstate->chal_id) { - return; /* doesn't match ID of last challenge */ - } - - /* - * If we have received a duplicate or bogus Response, - * we have to send the same answer (Success/Failure) - * as we did for the first Response we saw. - */ - if (cstate->serverstate == CHAPSS_OPEN) { - ChapSendStatus(cstate, CHAP_SUCCESS); - return; - } - if (cstate->serverstate == CHAPSS_BADAUTH) { - ChapSendStatus(cstate, CHAP_FAILURE); - return; - } - - if (len < 2) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); - return; - } - GETCHAR(remmd_len, inp); /* get length of MD */ - remmd = inp; /* get pointer to MD */ - INCPTR(remmd_len, inp); - - len -= sizeof (u_char) + remmd_len; - if (len < 0) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); - return; - } - - UNTIMEOUT(ChapChallengeTimeout, cstate); - - if (len >= sizeof(rhostname)) { - len = sizeof(rhostname) - 1; - } - BCOPY(inp, rhostname, len); - rhostname[len] = '\000'; - - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", rhostname)); - - /* - * Get secret for authenticating them with us, - * do the hash ourselves, and compare the result. - */ - code = CHAP_FAILURE; - if (!get_secret(cstate->unit, rhostname, cstate->chal_name, secret, &secret_len, 1)) { - /* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */ - CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n", - rhostname)); - } else { - /* generate MD based on negotiated type */ - switch (cstate->chal_type) { - - case CHAP_DIGEST_MD5: /* only MD5 is defined for now */ - if (remmd_len != MD5_SIGNATURE_SIZE) { - break; /* it's not even the right length */ - } - MD5Init(&mdContext); - MD5Update(&mdContext, &cstate->chal_id, 1); - MD5Update(&mdContext, (u_char*)secret, secret_len); - MD5Update(&mdContext, cstate->challenge, cstate->chal_len); - MD5Final(hash, &mdContext); - - /* compare local and remote MDs and send the appropriate status */ - if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) { - code = CHAP_SUCCESS; /* they are the same! */ - } - break; - - default: - CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type)); - } - } - - BZERO(secret, sizeof(secret)); - ChapSendStatus(cstate, code); - - if (code == CHAP_SUCCESS) { - old_state = cstate->serverstate; - cstate->serverstate = CHAPSS_OPEN; - if (old_state == CHAPSS_INITIAL_CHAL) { - auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len); - } - if (cstate->chal_interval != 0) { - TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval); - } - } else { - CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n")); - cstate->serverstate = CHAPSS_BADAUTH; - auth_peer_fail(cstate->unit, PPP_CHAP); - } -} - -/* - * ChapReceiveSuccess - Receive Success - */ -static void -ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len) -{ - LWIP_UNUSED_ARG(id); - LWIP_UNUSED_ARG(inp); - - CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id)); - - if (cstate->clientstate == CHAPCS_OPEN) { - /* presumably an answer to a duplicate response */ - return; - } - - if (cstate->clientstate != CHAPCS_RESPONSE) { - /* don't know what this is */ - CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", cstate->clientstate)); - return; - } - - UNTIMEOUT(ChapResponseTimeout, cstate); - - /* - * Print message. - */ - if (len > 0) { - PRINTMSG(inp, len); - } - - cstate->clientstate = CHAPCS_OPEN; - - auth_withpeer_success(cstate->unit, PPP_CHAP); -} - - -/* - * ChapReceiveFailure - Receive failure. - */ -static void -ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len) -{ - LWIP_UNUSED_ARG(id); - LWIP_UNUSED_ARG(inp); - - CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id)); - - if (cstate->clientstate != CHAPCS_RESPONSE) { - /* don't know what this is */ - CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", cstate->clientstate)); - return; - } - - UNTIMEOUT(ChapResponseTimeout, cstate); - - /* - * Print message. - */ - if (len > 0) { - PRINTMSG(inp, len); - } - - CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n")); - auth_withpeer_fail(cstate->unit, PPP_CHAP); -} - - -/* - * ChapSendChallenge - Send an Authenticate challenge. - */ -static void -ChapSendChallenge(chap_state *cstate) -{ - u_char *outp; - int chal_len, name_len; - int outlen; - - chal_len = cstate->chal_len; - name_len = strlen(cstate->chal_name); - outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */ - - PUTCHAR(CHAP_CHALLENGE, outp); - PUTCHAR(cstate->chal_id, outp); - PUTSHORT(outlen, outp); - - PUTCHAR(chal_len, outp); /* put length of challenge */ - BCOPY(cstate->challenge, outp, chal_len); - INCPTR(chal_len, outp); - - BCOPY(cstate->chal_name, outp, name_len); /* append hostname */ - - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id)); - - TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime); - ++cstate->chal_transmits; -} - - -/* - * ChapSendStatus - Send a status response (ack or nak). - */ -static void -ChapSendStatus(chap_state *cstate, int code) -{ - u_char *outp; - int outlen, msglen; - char msg[256]; - - if (code == CHAP_SUCCESS) { - strcpy(msg, "Welcome!"); - } else { - strcpy(msg, "I don't like you. Go 'way."); - } - msglen = strlen(msg); - - outlen = CHAP_HEADERLEN + msglen; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); /* paste in a header */ - - PUTCHAR(code, outp); - PUTCHAR(cstate->chal_id, outp); - PUTSHORT(outlen, outp); - BCOPY(msg, outp, msglen); - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, cstate->chal_id)); -} - -/* - * ChapGenChallenge is used to generate a pseudo-random challenge string of - * a pseudo-random length between min_len and max_len. The challenge - * string and its length are stored in *cstate, and various other fields of - * *cstate are initialized. - */ - -static void -ChapGenChallenge(chap_state *cstate) -{ - int chal_len; - u_char *ptr = cstate->challenge; - int i; - - /* pick a random challenge length between MIN_CHALLENGE_LENGTH and - MAX_CHALLENGE_LENGTH */ - chal_len = (unsigned) - ((((magic() >> 16) * - (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16) - + MIN_CHALLENGE_LENGTH); - cstate->chal_len = chal_len; - cstate->chal_id = ++cstate->id; - cstate->chal_transmits = 0; - - /* generate a random string */ - for (i = 0; i < chal_len; i++ ) { - *ptr++ = (char) (magic() & 0xff); - } -} - -/* - * ChapSendResponse - send a response packet with values as specified - * in *cstate. - */ -/* ARGSUSED */ -static void -ChapSendResponse(chap_state *cstate) -{ - u_char *outp; - int outlen, md_len, name_len; - - md_len = cstate->resp_length; - name_len = strlen(cstate->resp_name); - outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); - - PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */ - PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */ - PUTSHORT(outlen, outp); /* packet length */ - - PUTCHAR(md_len, outp); /* length of MD */ - BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */ - INCPTR(md_len, outp); - - BCOPY(cstate->resp_name, outp, name_len); /* append our name */ - - /* send the packet */ - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - cstate->clientstate = CHAPCS_RESPONSE; - TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime); - ++cstate->resp_transmits; -} - -#if 0 -static char *ChapCodenames[] = { - "Challenge", "Response", "Success", "Failure" -}; -/* - * ChapPrintPkt - print the contents of a CHAP packet. - */ -static int -ChapPrintPkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg) -{ - int code, id, len; - int clen, nlen; - u_char x; - - if (plen < CHAP_HEADERLEN) { - return 0; - } - GETCHAR(code, p); - GETCHAR(id, p); - GETSHORT(len, p); - if (len < CHAP_HEADERLEN || len > plen) { - return 0; - } - if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) { - printer(arg, " %s", ChapCodenames[code-1]); - } else { - printer(arg, " code=0x%x", code); - } - printer(arg, " id=0x%x", id); - len -= CHAP_HEADERLEN; - switch (code) { - case CHAP_CHALLENGE: - case CHAP_RESPONSE: - if (len < 1) { - break; - } - clen = p[0]; - if (len < clen + 1) { - break; - } - ++p; - nlen = len - clen - 1; - printer(arg, " <"); - for (; clen > 0; --clen) { - GETCHAR(x, p); - printer(arg, "%.2x", x); - } - printer(arg, ">, name = %.*Z", nlen, p); - break; - case CHAP_FAILURE: - case CHAP_SUCCESS: - printer(arg, " %.*Z", len, p); - break; - default: - for (clen = len; clen > 0; --clen) { - GETCHAR(x, p); - printer(arg, " %.2x", x); - } - } - - return len + CHAP_HEADERLEN; -} -#endif - -#endif /* CHAP_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/chap.h b/components/net/lwip-1.3.2/src/netif/ppp/chap.h deleted file mode 100644 index 83dafd734f..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/chap.h +++ /dev/null @@ -1,166 +0,0 @@ -/***************************************************************************** -* chap.h - Network Challenge Handshake Authentication Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-03 Guy Lancaster , Global Election Systems Inc. -* Original built from BSD network code. -******************************************************************************/ -/* - * chap.h - Challenge Handshake Authentication Protocol definitions. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1991 Gregory M. Christy - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the author. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id: chap.h,v 1.4 2007/12/19 20:47:22 fbernon Exp $ - */ - -#ifndef CHAP_H -#define CHAP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ - -/* Code + ID + length */ -#define CHAP_HEADERLEN 4 - -/* - * CHAP codes. - */ - -#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */ -#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */ -#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */ -#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ - -#define CHAP_CHALLENGE 1 -#define CHAP_RESPONSE 2 -#define CHAP_SUCCESS 3 -#define CHAP_FAILURE 4 - -/* - * Challenge lengths (for challenges we send) and other limits. - */ -#define MIN_CHALLENGE_LENGTH 32 -#define MAX_CHALLENGE_LENGTH 64 -#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */ - -/* - * Client (peer) states. - */ -#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */ -#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */ -#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */ -#define CHAPCS_LISTEN 3 /* Listening for a challenge */ -#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */ -#define CHAPCS_OPEN 5 /* We've received Success */ - -/* - * Server (authenticator) states. - */ -#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */ -#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */ -#define CHAPSS_PENDING 2 /* Auth peer when lower up */ -#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */ -#define CHAPSS_OPEN 4 /* We've sent a Success msg */ -#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */ -#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */ - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * Each interface is described by a chap structure. - */ - -typedef struct chap_state { - int unit; /* Interface unit number */ - int clientstate; /* Client state */ - int serverstate; /* Server state */ - u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */ - u_char chal_len; /* challenge length */ - u_char chal_id; /* ID of last challenge */ - u_char chal_type; /* hash algorithm for challenges */ - u_char id; /* Current id */ - char *chal_name; /* Our name to use with challenge */ - int chal_interval; /* Time until we challenge peer again */ - int timeouttime; /* Timeout time in seconds */ - int max_transmits; /* Maximum # of challenge transmissions */ - int chal_transmits; /* Number of transmissions of challenge */ - int resp_transmits; /* Number of transmissions of response */ - u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */ - u_char resp_length; /* length of response */ - u_char resp_id; /* ID for response messages */ - u_char resp_type; /* hash algorithm for responses */ - char *resp_name; /* Our name to send with response */ -} chap_state; - - -/****************** -*** PUBLIC DATA *** -******************/ -extern chap_state chap[]; - -extern struct protent chap_protent; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -void ChapAuthWithPeer (int, char *, int); -void ChapAuthPeer (int, char *, int); - -#endif /* CHAP_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/chpms.c b/components/net/lwip-1.3.2/src/netif/ppp/chpms.c deleted file mode 100644 index 582cfd2dd7..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/chpms.c +++ /dev/null @@ -1,399 +0,0 @@ -/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/ -/*** The original PPPD code is written in a way to require either the UNIX DES - encryption functions encrypt(3) and setkey(3) or the DES library libdes. - Since both is not included in lwIP, MSCHAP currently does not work! */ -/***************************************************************************** -* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD chap_ms.c. -*****************************************************************************/ -/* - * chap_ms.c - Microsoft MS-CHAP compatible implementation. - * - * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. - * http://www.strataware.com/ - * - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Eric Rosenquist. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* - * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 - * - * Implemented LANManager type password response to MS-CHAP challenges. - * Now pppd provides both NT style and LANMan style blocks, and the - * prefered is set by option "ms-lanman". Default is to use NT. - * The hash text (StdText) was taken from Win95 RASAPI32.DLL. - * - * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 - */ - -#define USE_CRYPT - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#if MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "md4.h" -#ifndef USE_CRYPT -#include "des.h" -#endif -#include "chap.h" -#include "chpms.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -typedef struct { - u_char LANManResp[24]; - u_char NTResp[24]; - u_char UseNT; /* If 1, ignore the LANMan response field */ -} MS_ChapResponse; -/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse), - in case this struct gets padded. */ - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ - -/* XXX Don't know what to do with these. */ -extern void setkey(const char *); -extern void encrypt(char *, int); - -static void DesEncrypt (u_char *, u_char *, u_char *); -static void MakeKey (u_char *, u_char *); - -#ifdef USE_CRYPT -static void Expand (u_char *, u_char *); -static void Collapse (u_char *, u_char *); -#endif - -static void ChallengeResponse( - u_char *challenge, /* IN 8 octets */ - u_char *pwHash, /* IN 16 octets */ - u_char *response /* OUT 24 octets */ -); -static void ChapMS_NT( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -); -static u_char Get7Bits( - u_char *input, - int startBit -); - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -void -ChapMS( chap_state *cstate, char *rchallenge, int rchallenge_len, char *secret, int secret_len) -{ - MS_ChapResponse response; -#ifdef MSLANMAN - extern int ms_lanman; -#endif - -#if 0 - CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret)); -#endif - BZERO(&response, sizeof(response)); - - /* Calculate both always */ - ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response); - -#ifdef MSLANMAN - ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response); - - /* prefered method is set by option */ - response.UseNT = !ms_lanman; -#else - response.UseNT = 1; -#endif - - BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN); - cstate->resp_length = MS_CHAP_RESPONSE_LEN; -} - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -static void -ChallengeResponse( u_char *challenge, /* IN 8 octets */ - u_char *pwHash, /* IN 16 octets */ - u_char *response /* OUT 24 octets */) -{ - char ZPasswordHash[21]; - - BZERO(ZPasswordHash, sizeof(ZPasswordHash)); - BCOPY(pwHash, ZPasswordHash, 16); - -#if 0 - log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG); -#endif - - DesEncrypt(challenge, ZPasswordHash + 0, response + 0); - DesEncrypt(challenge, ZPasswordHash + 7, response + 8); - DesEncrypt(challenge, ZPasswordHash + 14, response + 16); - -#if 0 - log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG); -#endif -} - - -#ifdef USE_CRYPT -static void -DesEncrypt( u_char *clear, /* IN 8 octets */ - u_char *key, /* IN 7 octets */ - u_char *cipher /* OUT 8 octets */) -{ - u_char des_key[8]; - u_char crypt_key[66]; - u_char des_input[66]; - - MakeKey(key, des_key); - - Expand(des_key, crypt_key); - setkey(crypt_key); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", - clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); -#endif - - Expand(clear, des_input); - encrypt(des_input, 0); - Collapse(des_input, cipher); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); -#endif -} - -#else /* USE_CRYPT */ - -static void -DesEncrypt( u_char *clear, /* IN 8 octets */ - u_char *key, /* IN 7 octets */ - u_char *cipher /* OUT 8 octets */) -{ - des_cblock des_key; - des_key_schedule key_schedule; - - MakeKey(key, des_key); - - des_set_key(&des_key, key_schedule); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", - clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); -#endif - - des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); -#endif -} - -#endif /* USE_CRYPT */ - - -static u_char -Get7Bits( u_char *input, int startBit) -{ - register unsigned int word; - - word = (unsigned)input[startBit / 8] << 8; - word |= (unsigned)input[startBit / 8 + 1]; - - word >>= 15 - (startBit % 8 + 7); - - return word & 0xFE; -} - -#ifdef USE_CRYPT - -/* in == 8-byte string (expanded version of the 56-bit key) - * out == 64-byte string where each byte is either 1 or 0 - * Note that the low-order "bit" is always ignored by by setkey() - */ -static void -Expand(u_char *in, u_char *out) -{ - int j, c; - int i; - - for(i = 0; i < 64; in++){ - c = *in; - for(j = 7; j >= 0; j--) { - *out++ = (c >> j) & 01; - } - i += 8; - } -} - -/* The inverse of Expand - */ -static void -Collapse(u_char *in, u_char *out) -{ - int j; - int i; - unsigned int c; - - for (i = 0; i < 64; i += 8, out++) { - c = 0; - for (j = 7; j >= 0; j--, in++) { - c |= *in << j; - } - *out = c & 0xff; - } -} -#endif - -static void -MakeKey( u_char *key, /* IN 56 bit DES key missing parity bits */ - u_char *des_key /* OUT 64 bit DES key with parity bits added */) -{ - des_key[0] = Get7Bits(key, 0); - des_key[1] = Get7Bits(key, 7); - des_key[2] = Get7Bits(key, 14); - des_key[3] = Get7Bits(key, 21); - des_key[4] = Get7Bits(key, 28); - des_key[5] = Get7Bits(key, 35); - des_key[6] = Get7Bits(key, 42); - des_key[7] = Get7Bits(key, 49); - -#ifndef USE_CRYPT - des_set_odd_parity((des_cblock *)des_key); -#endif - -#if 0 - CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n", - key[0], key[1], key[2], key[3], key[4], key[5], key[6])); - CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7])); -#endif -} - -static void -ChapMS_NT( char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response) -{ - int i; - MDstruct md4Context; - u_char unicodePassword[MAX_NT_PASSWORD * 2]; - static int low_byte_first = -1; - - /* Initialize the Unicode version of the secret (== password). */ - /* This implicitly supports 8-bit ISO8859/1 characters. */ - BZERO(unicodePassword, sizeof(unicodePassword)); - for (i = 0; i < secret_len; i++) { - unicodePassword[i * 2] = (u_char)secret[i]; - } - MDbegin(&md4Context); - MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */ - - if (low_byte_first == -1) { - low_byte_first = (htons((unsigned short int)1) != 1); - } - if (low_byte_first == 0) { - MDreverse((u_long *)&md4Context); /* sfb 961105 */ - } - - MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */ - - ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp); -} - -#ifdef MSLANMAN -static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ - -static void -ChapMS_LANMan( char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response) -{ - int i; - u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ - u_char PasswordHash[16]; - - /* LANMan password is case insensitive */ - BZERO(UcasePassword, sizeof(UcasePassword)); - for (i = 0; i < secret_len; i++) { - UcasePassword[i] = (u_char)toupper(secret[i]); - } - DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 ); - DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 ); - ChallengeResponse(rchallenge, PasswordHash, response->LANManResp); -} -#endif - -#endif /* MSCHAP_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/chpms.h b/components/net/lwip-1.3.2/src/netif/ppp/chpms.h deleted file mode 100644 index df070fb356..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/chpms.h +++ /dev/null @@ -1,64 +0,0 @@ -/***************************************************************************** -* chpms.h - Network Microsoft Challenge Handshake Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-01-30 Guy Lancaster , Global Election Systems Inc. -* Original built from BSD network code. -******************************************************************************/ -/* - * chap.h - Challenge Handshake Authentication Protocol definitions. - * - * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. - * http://www.strataware.com/ - * - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Eric Rosenquist. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id: chpms.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $ - */ - -#ifndef CHPMS_H -#define CHPMS_H - -#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */ - -void ChapMS (chap_state *, char *, int, char *, int); - -#endif /* CHPMS_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/fsm.c b/components/net/lwip-1.3.2/src/netif/ppp/fsm.c deleted file mode 100644 index ee549f230d..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/fsm.c +++ /dev/null @@ -1,908 +0,0 @@ -/***************************************************************************** -* fsm.c - Network Control Protocol Finite State Machine program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-01 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD fsm.c. -*****************************************************************************/ -/* - * fsm.c - {Link, IP} Control Protocol Finite State Machine. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* - * TODO: - * Randomize fsm id on link/init. - * Deal with variable outgoing MTU. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "fsm.h" - -#include - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -#if PPP_DEBUG - -static const char *ppperr_strerr[] = { - "LS_INITIAL", /* LS_INITIAL 0 */ - "LS_STARTING", /* LS_STARTING 1 */ - "LS_CLOSED", /* LS_CLOSED 2 */ - "LS_STOPPED", /* LS_STOPPED 3 */ - "LS_CLOSING", /* LS_CLOSING 4 */ - "LS_STOPPING", /* LS_STOPPING 5 */ - "LS_REQSENT", /* LS_REQSENT 6 */ - "LS_ACKRCVD", /* LS_ACKRCVD 7 */ - "LS_ACKSENT", /* LS_ACKSENT 8 */ - "LS_OPENED" /* LS_OPENED 9 */ -}; - -#endif /* PPP_DEBUG */ - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -static void fsm_timeout (void *); -static void fsm_rconfreq (fsm *, u_char, u_char *, int); -static void fsm_rconfack (fsm *, int, u_char *, int); -static void fsm_rconfnakrej (fsm *, int, int, u_char *, int); -static void fsm_rtermreq (fsm *, int, u_char *, int); -static void fsm_rtermack (fsm *); -static void fsm_rcoderej (fsm *, u_char *, int); -static void fsm_sconfreq (fsm *, int); - -#define PROTO_NAME(f) ((f)->callbacks->proto_name) - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -int peer_mru[NUM_PPP]; - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ - -/* - * fsm_init - Initialize fsm. - * - * Initialize fsm state. - */ -void -fsm_init(fsm *f) -{ - f->state = LS_INITIAL; - f->flags = 0; - f->id = 0; /* XXX Start with random id? */ - f->timeouttime = FSM_DEFTIMEOUT; - f->maxconfreqtransmits = FSM_DEFMAXCONFREQS; - f->maxtermtransmits = FSM_DEFMAXTERMREQS; - f->maxnakloops = FSM_DEFMAXNAKLOOPS; - f->term_reason_len = 0; -} - - -/* - * fsm_lowerup - The lower layer is up. - */ -void -fsm_lowerup(fsm *f) -{ - int oldState = f->state; - - LWIP_UNUSED_ARG(oldState); - - switch( f->state ) { - case LS_INITIAL: - f->state = LS_CLOSED; - break; - - case LS_STARTING: - if( f->flags & OPT_SILENT ) { - f->state = LS_STOPPED; - } else { - /* Send an initial configure-request */ - fsm_sconfreq(f, 0); - f->state = LS_REQSENT; - } - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Up event in state %d (%s)!\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - } - - FSMDEBUG((LOG_INFO, "%s: lowerup state %d (%s) -> %d (%s)\n", - PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); -} - - -/* - * fsm_lowerdown - The lower layer is down. - * - * Cancel all timeouts and inform upper layers. - */ -void -fsm_lowerdown(fsm *f) -{ - int oldState = f->state; - - LWIP_UNUSED_ARG(oldState); - - switch( f->state ) { - case LS_CLOSED: - f->state = LS_INITIAL; - break; - - case LS_STOPPED: - f->state = LS_STARTING; - if( f->callbacks->starting ) { - (*f->callbacks->starting)(f); - } - break; - - case LS_CLOSING: - f->state = LS_INITIAL; - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - break; - - case LS_STOPPING: - case LS_REQSENT: - case LS_ACKRCVD: - case LS_ACKSENT: - f->state = LS_STARTING; - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - break; - - case LS_OPENED: - if( f->callbacks->down ) { - (*f->callbacks->down)(f); - } - f->state = LS_STARTING; - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Down event in state %d (%s)!\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - } - - FSMDEBUG((LOG_INFO, "%s: lowerdown state %d (%s) -> %d (%s)\n", - PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); -} - - -/* - * fsm_open - Link is allowed to come up. - */ -void -fsm_open(fsm *f) -{ - int oldState = f->state; - - LWIP_UNUSED_ARG(oldState); - - switch( f->state ) { - case LS_INITIAL: - f->state = LS_STARTING; - if( f->callbacks->starting ) { - (*f->callbacks->starting)(f); - } - break; - - case LS_CLOSED: - if( f->flags & OPT_SILENT ) { - f->state = LS_STOPPED; - } else { - /* Send an initial configure-request */ - fsm_sconfreq(f, 0); - f->state = LS_REQSENT; - } - break; - - case LS_CLOSING: - f->state = LS_STOPPING; - /* fall through */ - case LS_STOPPED: - case LS_OPENED: - if( f->flags & OPT_RESTART ) { - fsm_lowerdown(f); - fsm_lowerup(f); - } - break; - } - - FSMDEBUG((LOG_INFO, "%s: open state %d (%s) -> %d (%s)\n", - PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); -} - - -/* - * fsm_close - Start closing connection. - * - * Cancel timeouts and either initiate close or possibly go directly to - * the LS_CLOSED state. - */ -void -fsm_close(fsm *f, char *reason) -{ - int oldState = f->state; - - LWIP_UNUSED_ARG(oldState); - - f->term_reason = reason; - f->term_reason_len = (reason == NULL? 0: strlen(reason)); - switch( f->state ) { - case LS_STARTING: - f->state = LS_INITIAL; - break; - case LS_STOPPED: - f->state = LS_CLOSED; - break; - case LS_STOPPING: - f->state = LS_CLOSING; - break; - - case LS_REQSENT: - case LS_ACKRCVD: - case LS_ACKSENT: - case LS_OPENED: - if( f->state != LS_OPENED ) { - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - } else if( f->callbacks->down ) { - (*f->callbacks->down)(f); /* Inform upper layers we're down */ - } - /* Init restart counter, send Terminate-Request */ - f->retransmits = f->maxtermtransmits; - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - - f->state = LS_CLOSING; - break; - } - - FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d (%s) -> %d (%s)\n", - PROTO_NAME(f), reason, oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); -} - - -/* - * fsm_sdata - Send some data. - * - * Used for all packets sent to our peer by this module. - */ -void -fsm_sdata( fsm *f, u_char code, u_char id, u_char *data, int datalen) -{ - u_char *outp; - int outlen; - - /* Adjust length to be smaller than MTU */ - outp = outpacket_buf[f->unit]; - if (datalen > peer_mru[f->unit] - (int)HEADERLEN) { - datalen = peer_mru[f->unit] - HEADERLEN; - } - if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) { - BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen); - } - outlen = datalen + HEADERLEN; - MAKEHEADER(outp, f->protocol); - PUTCHAR(code, outp); - PUTCHAR(id, outp); - PUTSHORT(outlen, outp); - pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN); - FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n", - PROTO_NAME(f), code, id, outlen)); -} - - -/* - * fsm_input - Input packet. - */ -void -fsm_input(fsm *f, u_char *inpacket, int l) -{ - u_char *inp = inpacket; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - if (l < HEADERLEN) { - FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n", - f->protocol)); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < HEADERLEN) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n", - f->protocol)); - return; - } - if (len > l) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n", - f->protocol)); - return; - } - len -= HEADERLEN; /* subtract header length */ - - if( f->state == LS_INITIAL || f->state == LS_STARTING ) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d (%s).\n", - f->protocol, f->state, ppperr_strerr[f->state])); - return; - } - FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l)); - /* - * Action depends on code. - */ - switch (code) { - case CONFREQ: - fsm_rconfreq(f, id, inp, len); - break; - - case CONFACK: - fsm_rconfack(f, id, inp, len); - break; - - case CONFNAK: - case CONFREJ: - fsm_rconfnakrej(f, code, id, inp, len); - break; - - case TERMREQ: - fsm_rtermreq(f, id, inp, len); - break; - - case TERMACK: - fsm_rtermack(f); - break; - - case CODEREJ: - fsm_rcoderej(f, inp, len); - break; - - default: - if( !f->callbacks->extcode || - !(*f->callbacks->extcode)(f, code, id, inp, len) ) { - fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); - } - break; - } -} - - -/* - * fsm_protreject - Peer doesn't speak this protocol. - * - * Treat this as a catastrophic error (RXJ-). - */ -void -fsm_protreject(fsm *f) -{ - switch( f->state ) { - case LS_CLOSING: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - /* fall through */ - case LS_CLOSED: - f->state = LS_CLOSED; - if( f->callbacks->finished ) { - (*f->callbacks->finished)(f); - } - break; - - case LS_STOPPING: - case LS_REQSENT: - case LS_ACKRCVD: - case LS_ACKSENT: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - /* fall through */ - case LS_STOPPED: - f->state = LS_STOPPED; - if( f->callbacks->finished ) { - (*f->callbacks->finished)(f); - } - break; - - case LS_OPENED: - if( f->callbacks->down ) { - (*f->callbacks->down)(f); - } - /* Init restart counter, send Terminate-Request */ - f->retransmits = f->maxtermtransmits; - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - - f->state = LS_STOPPING; - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d (%s)!\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - } -} - - - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -/* - * fsm_timeout - Timeout expired. - */ -static void -fsm_timeout(void *arg) -{ - fsm *f = (fsm *) arg; - - switch (f->state) { - case LS_CLOSING: - case LS_STOPPING: - if( f->retransmits <= 0 ) { - FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d (%s)\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - /* - * We've waited for an ack long enough. Peer probably heard us. - */ - f->state = (f->state == LS_CLOSING)? LS_CLOSED: LS_STOPPED; - if( f->callbacks->finished ) { - (*f->callbacks->finished)(f); - } - } else { - FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d (%s)\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - /* Send Terminate-Request */ - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - } - break; - - case LS_REQSENT: - case LS_ACKRCVD: - case LS_ACKSENT: - if (f->retransmits <= 0) { - FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d (%s)\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - f->state = LS_STOPPED; - if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) { - (*f->callbacks->finished)(f); - } - } else { - FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d (%s)\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - /* Retransmit the configure-request */ - if (f->callbacks->retransmit) { - (*f->callbacks->retransmit)(f); - } - fsm_sconfreq(f, 1); /* Re-send Configure-Request */ - if( f->state == LS_ACKRCVD ) { - f->state = LS_REQSENT; - } - } - break; - - default: - FSMDEBUG((LOG_INFO, "%s: UNHANDLED timeout event in state %d (%s)!\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - } -} - - -/* - * fsm_rconfreq - Receive Configure-Request. - */ -static void -fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) -{ - int code, reject_if_disagree; - - FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d (%s)\n", - PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); - switch( f->state ) { - case LS_CLOSED: - /* Go away, we're closed */ - fsm_sdata(f, TERMACK, id, NULL, 0); - return; - case LS_CLOSING: - case LS_STOPPING: - return; - - case LS_OPENED: - /* Go down and restart negotiation */ - if( f->callbacks->down ) { - (*f->callbacks->down)(f); /* Inform upper layers */ - } - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - break; - - case LS_STOPPED: - /* Negotiation started by our peer */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = LS_REQSENT; - break; - } - - /* - * Pass the requested configuration options - * to protocol-specific code for checking. - */ - if (f->callbacks->reqci) { /* Check CI */ - reject_if_disagree = (f->nakloops >= f->maxnakloops); - code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); - } else if (len) { - code = CONFREJ; /* Reject all CI */ - } else { - code = CONFACK; - } - - /* send the Ack, Nak or Rej to the peer */ - fsm_sdata(f, (u_char)code, id, inp, len); - - if (code == CONFACK) { - if (f->state == LS_ACKRCVD) { - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - f->state = LS_OPENED; - if (f->callbacks->up) { - (*f->callbacks->up)(f); /* Inform upper layers */ - } - } else { - f->state = LS_ACKSENT; - } - f->nakloops = 0; - } else { - /* we sent CONFACK or CONFREJ */ - if (f->state != LS_ACKRCVD) { - f->state = LS_REQSENT; - } - if( code == CONFNAK ) { - ++f->nakloops; - } - } -} - - -/* - * fsm_rconfack - Receive Configure-Ack. - */ -static void -fsm_rconfack(fsm *f, int id, u_char *inp, int len) -{ - FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d (%s)\n", - PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); - - if (id != f->reqid || f->seen_ack) { /* Expected id? */ - return; /* Nope, toss... */ - } - if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): (len == 0)) ) { - /* Ack is bad - ignore it */ - FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n", - PROTO_NAME(f), len)); - return; - } - f->seen_ack = 1; - - switch (f->state) { - case LS_CLOSED: - case LS_STOPPED: - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); - break; - - case LS_REQSENT: - f->state = LS_ACKRCVD; - f->retransmits = f->maxconfreqtransmits; - break; - - case LS_ACKRCVD: - /* Huh? an extra valid Ack? oh well... */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - fsm_sconfreq(f, 0); - f->state = LS_REQSENT; - break; - - case LS_ACKSENT: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - f->state = LS_OPENED; - f->retransmits = f->maxconfreqtransmits; - if (f->callbacks->up) { - (*f->callbacks->up)(f); /* Inform upper layers */ - } - break; - - case LS_OPENED: - /* Go down and restart negotiation */ - if (f->callbacks->down) { - (*f->callbacks->down)(f); /* Inform upper layers */ - } - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = LS_REQSENT; - break; - } -} - - -/* - * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. - */ -static void -fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) -{ - int (*proc) (fsm *, u_char *, int); - int ret; - - FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d (%s)\n", - PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); - - if (id != f->reqid || f->seen_ack) { /* Expected id? */ - return; /* Nope, toss... */ - } - proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci; - if (!proc || !((ret = proc(f, inp, len)))) { - /* Nak/reject is bad - ignore it */ - FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n", - PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len)); - return; - } - f->seen_ack = 1; - - switch (f->state) { - case LS_CLOSED: - case LS_STOPPED: - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); - break; - - case LS_REQSENT: - case LS_ACKSENT: - /* They didn't agree to what we wanted - try another request */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - if (ret < 0) { - f->state = LS_STOPPED; /* kludge for stopping CCP */ - } else { - fsm_sconfreq(f, 0); /* Send Configure-Request */ - } - break; - - case LS_ACKRCVD: - /* Got a Nak/reject when we had already had an Ack?? oh well... */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - fsm_sconfreq(f, 0); - f->state = LS_REQSENT; - break; - - case LS_OPENED: - /* Go down and restart negotiation */ - if (f->callbacks->down) { - (*f->callbacks->down)(f); /* Inform upper layers */ - } - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = LS_REQSENT; - break; - } -} - - -/* - * fsm_rtermreq - Receive Terminate-Req. - */ -static void -fsm_rtermreq(fsm *f, int id, u_char *p, int len) -{ - LWIP_UNUSED_ARG(p); - - FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d (%s)\n", - PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); - - switch (f->state) { - case LS_ACKRCVD: - case LS_ACKSENT: - f->state = LS_REQSENT; /* Start over but keep trying */ - break; - - case LS_OPENED: - if (len > 0) { - FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p)); - } else { - FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f))); - } - if (f->callbacks->down) { - (*f->callbacks->down)(f); /* Inform upper layers */ - } - f->retransmits = 0; - f->state = LS_STOPPING; - TIMEOUT(fsm_timeout, f, f->timeouttime); - break; - } - - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); -} - - -/* - * fsm_rtermack - Receive Terminate-Ack. - */ -static void -fsm_rtermack(fsm *f) -{ - FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d (%s)\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - - switch (f->state) { - case LS_CLOSING: - UNTIMEOUT(fsm_timeout, f); - f->state = LS_CLOSED; - if( f->callbacks->finished ) { - (*f->callbacks->finished)(f); - } - break; - - case LS_STOPPING: - UNTIMEOUT(fsm_timeout, f); - f->state = LS_STOPPED; - if( f->callbacks->finished ) { - (*f->callbacks->finished)(f); - } - break; - - case LS_ACKRCVD: - f->state = LS_REQSENT; - break; - - case LS_OPENED: - if (f->callbacks->down) { - (*f->callbacks->down)(f); /* Inform upper layers */ - } - fsm_sconfreq(f, 0); - break; - } -} - - -/* - * fsm_rcoderej - Receive an Code-Reject. - */ -static void -fsm_rcoderej(fsm *f, u_char *inp, int len) -{ - u_char code, id; - - FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d (%s)\n", - PROTO_NAME(f), f->state, ppperr_strerr[f->state])); - - if (len < HEADERLEN) { - FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n", - PROTO_NAME(f), code, id)); - - if( f->state == LS_ACKRCVD ) { - f->state = LS_REQSENT; - } -} - - -/* - * fsm_sconfreq - Send a Configure-Request. - */ -static void -fsm_sconfreq(fsm *f, int retransmit) -{ - u_char *outp; - int cilen; - - if( f->state != LS_REQSENT && f->state != LS_ACKRCVD && f->state != LS_ACKSENT ) { - /* Not currently negotiating - reset options */ - if( f->callbacks->resetci ) { - (*f->callbacks->resetci)(f); - } - f->nakloops = 0; - } - - if( !retransmit ) { - /* New request - reset retransmission counter, use new ID */ - f->retransmits = f->maxconfreqtransmits; - f->reqid = ++f->id; - } - - f->seen_ack = 0; - - /* - * Make up the request packet - */ - outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN; - if( f->callbacks->cilen && f->callbacks->addci ) { - cilen = (*f->callbacks->cilen)(f); - if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) { - cilen = peer_mru[f->unit] - HEADERLEN; - } - if (f->callbacks->addci) { - (*f->callbacks->addci)(f, outp, &cilen); - } - } else { - cilen = 0; - } - - /* send the request to our peer */ - fsm_sdata(f, CONFREQ, f->reqid, outp, cilen); - - /* start the retransmit timer */ - --f->retransmits; - TIMEOUT(fsm_timeout, f, f->timeouttime); - - FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n", - PROTO_NAME(f), f->reqid)); -} - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/fsm.h b/components/net/lwip-1.3.2/src/netif/ppp/fsm.h deleted file mode 100644 index 14034ec7fd..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/fsm.h +++ /dev/null @@ -1,169 +0,0 @@ -/***************************************************************************** -* fsm.h - Network Control Protocol Finite State Machine header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD code. -*****************************************************************************/ -/* - * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id: fsm.h,v 1.4 2007/12/19 20:47:23 fbernon Exp $ - */ - -#ifndef FSM_H -#define FSM_H - -/***************************************************************************** -************************* PUBLIC DEFINITIONS ********************************* -*****************************************************************************/ -/* - * LCP Packet header = Code, id, length. - */ -#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) - - -/* - * CP (LCP, IPCP, etc.) codes. - */ -#define CONFREQ 1 /* Configuration Request */ -#define CONFACK 2 /* Configuration Ack */ -#define CONFNAK 3 /* Configuration Nak */ -#define CONFREJ 4 /* Configuration Reject */ -#define TERMREQ 5 /* Termination Request */ -#define TERMACK 6 /* Termination Ack */ -#define CODEREJ 7 /* Code Reject */ - -/* - * Link states. - */ -#define LS_INITIAL 0 /* Down, hasn't been opened */ -#define LS_STARTING 1 /* Down, been opened */ -#define LS_CLOSED 2 /* Up, hasn't been opened */ -#define LS_STOPPED 3 /* Open, waiting for down event */ -#define LS_CLOSING 4 /* Terminating the connection, not open */ -#define LS_STOPPING 5 /* Terminating, but open */ -#define LS_REQSENT 6 /* We've sent a Config Request */ -#define LS_ACKRCVD 7 /* We've received a Config Ack */ -#define LS_ACKSENT 8 /* We've sent a Config Ack */ -#define LS_OPENED 9 /* Connection available */ - -/* - * Flags - indicate options controlling FSM operation - */ -#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ -#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ -#define OPT_SILENT 4 /* Wait for peer to speak first */ - - -/***************************************************************************** -************************* PUBLIC DATA TYPES ********************************** -*****************************************************************************/ -/* - * Each FSM is described by an fsm structure and fsm callbacks. - */ -typedef struct fsm { - int unit; /* Interface unit number */ - u_short protocol; /* Data Link Layer Protocol field value */ - int state; /* State */ - int flags; /* Contains option bits */ - u_char id; /* Current id */ - u_char reqid; /* Current request id */ - u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */ - int timeouttime; /* Timeout time in milliseconds */ - int maxconfreqtransmits; /* Maximum Configure-Request transmissions */ - int retransmits; /* Number of retransmissions left */ - int maxtermtransmits; /* Maximum Terminate-Request transmissions */ - int nakloops; /* Number of nak loops since last ack */ - int maxnakloops; /* Maximum number of nak loops tolerated */ - struct fsm_callbacks* callbacks; /* Callback routines */ - char* term_reason; /* Reason for closing protocol */ - int term_reason_len; /* Length of term_reason */ -} fsm; - - -typedef struct fsm_callbacks { - void (*resetci)(fsm*); /* Reset our Configuration Information */ - int (*cilen)(fsm*); /* Length of our Configuration Information */ - void (*addci)(fsm*, u_char*, int*); /* Add our Configuration Information */ - int (*ackci)(fsm*, u_char*, int); /* ACK our Configuration Information */ - int (*nakci)(fsm*, u_char*, int); /* NAK our Configuration Information */ - int (*rejci)(fsm*, u_char*, int); /* Reject our Configuration Information */ - int (*reqci)(fsm*, u_char*, int*, int); /* Request peer's Configuration Information */ - void (*up)(fsm*); /* Called when fsm reaches LS_OPENED state */ - void (*down)(fsm*); /* Called when fsm leaves LS_OPENED state */ - void (*starting)(fsm*); /* Called when we want the lower layer */ - void (*finished)(fsm*); /* Called when we don't want the lower layer */ - void (*protreject)(int); /* Called when Protocol-Reject received */ - void (*retransmit)(fsm*); /* Retransmission is necessary */ - int (*extcode)(fsm*, int, u_char, u_char*, int); /* Called when unknown code received */ - char *proto_name; /* String name for protocol (for messages) */ -} fsm_callbacks; - - -/***************************************************************************** -*********************** PUBLIC DATA STRUCTURES ******************************* -*****************************************************************************/ -/* - * Variables - */ -extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */ - - -/***************************************************************************** -************************** PUBLIC FUNCTIONS ********************************** -*****************************************************************************/ - -/* - * Prototypes - */ -void fsm_init (fsm*); -void fsm_lowerup (fsm*); -void fsm_lowerdown (fsm*); -void fsm_open (fsm*); -void fsm_close (fsm*, char*); -void fsm_input (fsm*, u_char*, int); -void fsm_protreject (fsm*); -void fsm_sdata (fsm*, u_char, u_char, u_char*, int); - -#endif /* FSM_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/ipcp.c b/components/net/lwip-1.3.2/src/netif/ppp/ipcp.c deleted file mode 100644 index 0ff4ce3fff..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/ipcp.c +++ /dev/null @@ -1,1427 +0,0 @@ -/***************************************************************************** -* ipcp.c - Network PPP IP Control Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ -/* - * ipcp.c - PPP IP Control Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "auth.h" -#include "fsm.h" -#include "vj.h" -#include "ipcp.h" - -#include - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ -/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */ - -/* - * Lengths of configuration options. - */ -#define CILEN_VOID 2 -#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ -#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ -#define CILEN_ADDR 6 /* new-style single address option */ -#define CILEN_ADDRS 10 /* old-style dual address option */ - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Callbacks for fsm code. (CI = Configuration Information) - */ -static void ipcp_resetci (fsm *); /* Reset our CI */ -static int ipcp_cilen (fsm *); /* Return length of our CI */ -static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */ -static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */ -static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */ -static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */ -static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */ -static void ipcp_up (fsm *); /* We're UP */ -static void ipcp_down (fsm *); /* We're DOWN */ -#if 0 -static void ipcp_script (fsm *, char *); /* Run an up/down script */ -#endif -static void ipcp_finished (fsm *); /* Don't need lower layer */ - -/* - * Protocol entry points from main code. - */ -static void ipcp_init (int); -static void ipcp_open (int); -static void ipcp_close (int, char *); -static void ipcp_lowerup (int); -static void ipcp_lowerdown (int); -static void ipcp_input (int, u_char *, int); -static void ipcp_protrej (int); - -static void ipcp_clear_addrs (int); - -#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ - (x) == CONFNAK ? "NAK" : "REJ") - - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -/* global vars */ -ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */ -ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ -ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ -ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ - -fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */ - -struct protent ipcp_protent = { - PPP_IPCP, - ipcp_init, - ipcp_input, - ipcp_protrej, - ipcp_lowerup, - ipcp_lowerdown, - ipcp_open, - ipcp_close, -#if 0 - ipcp_printpkt, - NULL, -#endif - 1, - "IPCP", -#if 0 - ip_check_options, - NULL, - ip_active_pkt -#endif -}; - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -/* local vars */ -static int cis_received[NUM_PPP]; /* # Conf-Reqs received */ -static int default_route_set[NUM_PPP]; /* Have set up a default route */ - -static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ - ipcp_resetci, /* Reset our Configuration Information */ - ipcp_cilen, /* Length of our Configuration Information */ - ipcp_addci, /* Add our Configuration Information */ - ipcp_ackci, /* ACK our Configuration Information */ - ipcp_nakci, /* NAK our Configuration Information */ - ipcp_rejci, /* Reject our Configuration Information */ - ipcp_reqci, /* Request peer's Configuration Information */ - ipcp_up, /* Called when fsm reaches LS_OPENED state */ - ipcp_down, /* Called when fsm leaves LS_OPENED state */ - NULL, /* Called when we want the lower layer up */ - ipcp_finished, /* Called when we want the lower layer down */ - NULL, /* Called when Protocol-Reject received */ - NULL, /* Retransmission is necessary */ - NULL, /* Called to handle protocol-specific codes */ - "IPCP" /* String name of protocol */ -}; - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -#define inet_ntoa(addr) ip_ntoa(((struct ip_addr*)&(addr))) - -/* - * ipcp_init - Initialize IPCP. - */ -static void -ipcp_init(int unit) -{ - fsm *f = &ipcp_fsm[unit]; - ipcp_options *wo = &ipcp_wantoptions[unit]; - ipcp_options *ao = &ipcp_allowoptions[unit]; - - f->unit = unit; - f->protocol = PPP_IPCP; - f->callbacks = &ipcp_callbacks; - fsm_init(&ipcp_fsm[unit]); - - memset(wo, 0, sizeof(*wo)); - memset(ao, 0, sizeof(*ao)); - - wo->neg_addr = 1; - wo->ouraddr = 0; -#if VJ_SUPPORT - wo->neg_vj = 1; -#else /* VJ_SUPPORT */ - wo->neg_vj = 0; -#endif /* VJ_SUPPORT */ - wo->vj_protocol = IPCP_VJ_COMP; - wo->maxslotindex = MAX_SLOTS - 1; - wo->cflag = 0; - wo->default_route = 1; - - ao->neg_addr = 1; -#if VJ_SUPPORT - ao->neg_vj = 1; -#else /* VJ_SUPPORT */ - ao->neg_vj = 0; -#endif /* VJ_SUPPORT */ - ao->maxslotindex = MAX_SLOTS - 1; - ao->cflag = 1; - ao->default_route = 1; -} - - -/* - * ipcp_open - IPCP is allowed to come up. - */ -static void -ipcp_open(int unit) -{ - fsm_open(&ipcp_fsm[unit]); -} - - -/* - * ipcp_close - Take IPCP down. - */ -static void -ipcp_close(int unit, char *reason) -{ - fsm_close(&ipcp_fsm[unit], reason); -} - - -/* - * ipcp_lowerup - The lower layer is up. - */ -static void -ipcp_lowerup(int unit) -{ - fsm_lowerup(&ipcp_fsm[unit]); -} - - -/* - * ipcp_lowerdown - The lower layer is down. - */ -static void -ipcp_lowerdown(int unit) -{ - fsm_lowerdown(&ipcp_fsm[unit]); -} - - -/* - * ipcp_input - Input IPCP packet. - */ -static void -ipcp_input(int unit, u_char *p, int len) -{ - fsm_input(&ipcp_fsm[unit], p, len); -} - - -/* - * ipcp_protrej - A Protocol-Reject was received for IPCP. - * - * Pretend the lower layer went down, so we shut up. - */ -static void -ipcp_protrej(int unit) -{ - fsm_lowerdown(&ipcp_fsm[unit]); -} - - -/* - * ipcp_resetci - Reset our CI. - */ -static void -ipcp_resetci(fsm *f) -{ - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - - wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr; - if (wo->ouraddr == 0) { - wo->accept_local = 1; - } - if (wo->hisaddr == 0) { - wo->accept_remote = 1; - } - /* Request DNS addresses from the peer */ - wo->req_dns1 = ppp_settings.usepeerdns; - wo->req_dns2 = ppp_settings.usepeerdns; - ipcp_gotoptions[f->unit] = *wo; - cis_received[f->unit] = 0; -} - - -/* - * ipcp_cilen - Return length of our CI. - */ -static int -ipcp_cilen(fsm *f) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - -#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) -#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0) -#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0) - - /* - * First see if we want to change our options to the old - * forms because we have received old forms from the peer. - */ - if (wo->neg_addr && !go->neg_addr && !go->old_addrs) { - /* use the old style of address negotiation */ - go->neg_addr = 1; - go->old_addrs = 1; - } - if (wo->neg_vj && !go->neg_vj && !go->old_vj) { - /* try an older style of VJ negotiation */ - if (cis_received[f->unit] == 0) { - /* keep trying the new style until we see some CI from the peer */ - go->neg_vj = 1; - } else { - /* use the old style only if the peer did */ - if (ho->neg_vj && ho->old_vj) { - go->neg_vj = 1; - go->old_vj = 1; - go->vj_protocol = ho->vj_protocol; - } - } - } - - return (LENCIADDR(go->neg_addr, go->old_addrs) + - LENCIVJ(go->neg_vj, go->old_vj) + - LENCIDNS(go->req_dns1) + - LENCIDNS(go->req_dns2)); -} - - -/* - * ipcp_addci - Add our desired CIs to a packet. - */ -static void -ipcp_addci(fsm *f, u_char *ucp, int *lenp) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - int len = *lenp; - -#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ - if (neg) { \ - int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ - if (len >= vjlen) { \ - PUTCHAR(opt, ucp); \ - PUTCHAR(vjlen, ucp); \ - PUTSHORT(val, ucp); \ - if (!old) { \ - PUTCHAR(maxslotindex, ucp); \ - PUTCHAR(cflag, ucp); \ - } \ - len -= vjlen; \ - } else { \ - neg = 0; \ - } \ - } - -#define ADDCIADDR(opt, neg, old, val1, val2) \ - if (neg) { \ - int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ - if (len >= addrlen) { \ - u32_t l; \ - PUTCHAR(opt, ucp); \ - PUTCHAR(addrlen, ucp); \ - l = ntohl(val1); \ - PUTLONG(l, ucp); \ - if (old) { \ - l = ntohl(val2); \ - PUTLONG(l, ucp); \ - } \ - len -= addrlen; \ - } else { \ - neg = 0; \ - } \ - } - -#define ADDCIDNS(opt, neg, addr) \ - if (neg) { \ - if (len >= CILEN_ADDR) { \ - u32_t l; \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_ADDR, ucp); \ - l = ntohl(addr); \ - PUTLONG(l, ucp); \ - len -= CILEN_ADDR; \ - } else { \ - neg = 0; \ - } \ - } - - ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); - - ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); - - *lenp -= len; -} - - -/* - * ipcp_ackci - Ack our CIs. - * - * Returns: - * 0 - Ack was bad. - * 1 - Ack was good. - */ -static int -ipcp_ackci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_short cilen, citype, cishort; - u32_t cilong; - u_char cimaxslotindex, cicflag; - - /* - * CIs must be in exactly the same order that we sent... - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ - -#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ - if (neg) { \ - int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ - if ((len -= vjlen) < 0) { \ - goto bad; \ - } \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != vjlen || \ - citype != opt) { \ - goto bad; \ - } \ - GETSHORT(cishort, p); \ - if (cishort != val) { \ - goto bad; \ - } \ - if (!old) { \ - GETCHAR(cimaxslotindex, p); \ - if (cimaxslotindex != maxslotindex) { \ - goto bad; \ - } \ - GETCHAR(cicflag, p); \ - if (cicflag != cflag) { \ - goto bad; \ - } \ - } \ - } - -#define ACKCIADDR(opt, neg, old, val1, val2) \ - if (neg) { \ - int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ - u32_t l; \ - if ((len -= addrlen) < 0) { \ - goto bad; \ - } \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != addrlen || \ - citype != opt) { \ - goto bad; \ - } \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (val1 != cilong) { \ - goto bad; \ - } \ - if (old) { \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (val2 != cilong) { \ - goto bad; \ - } \ - } \ - } - -#define ACKCIDNS(opt, neg, addr) \ - if (neg) { \ - u32_t l; \ - if ((len -= CILEN_ADDR) < 0) { \ - goto bad; \ - } \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_ADDR || \ - citype != opt) { \ - goto bad; \ - } \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (addr != cilong) { \ - goto bad; \ - } \ - } - - ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); - - ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) { - goto bad; - } - return (1); - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n")); - return (0); -} - -/* - * ipcp_nakci - Peer has sent a NAK for some of our CIs. - * This should not modify any state if the Nak is bad - * or if IPCP is in the LS_OPENED state. - * - * Returns: - * 0 - Nak was bad. - * 1 - Nak was good. - */ -static int -ipcp_nakci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_char cimaxslotindex, cicflag; - u_char citype, cilen, *next; - u_short cishort; - u32_t ciaddr1, ciaddr2, l, cidnsaddr; - ipcp_options no; /* options we've seen Naks for */ - ipcp_options try; /* options to request next time */ - - BZERO(&no, sizeof(no)); - try = *go; - - /* - * Any Nak'd CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define NAKCIADDR(opt, neg, old, code) \ - if (go->neg && \ - len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \ - p[1] == cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - ciaddr1 = htonl(l); \ - if (old) { \ - GETLONG(l, p); \ - ciaddr2 = htonl(l); \ - no.old_addrs = 1; \ - } else { \ - ciaddr2 = 0; \ - } \ - no.neg = 1; \ - code \ - } - -#define NAKCIVJ(opt, neg, code) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ - len >= cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - no.neg = 1; \ - code \ - } - -#define NAKCIDNS(opt, neg, code) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_ADDR) && \ - len >= cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cidnsaddr = htonl(l); \ - no.neg = 1; \ - code \ - } - - /* - * Accept the peer's idea of {our,his} address, if different - * from our idea, only if the accept_{local,remote} flag is set. - */ - NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs, - if (go->accept_local && ciaddr1) { /* Do we know our address? */ - try.ouraddr = ciaddr1; - IPCPDEBUG((LOG_INFO, "local IP address %s\n", - inet_ntoa(ciaddr1))); - } - if (go->accept_remote && ciaddr2) { /* Does he know his? */ - try.hisaddr = ciaddr2; - IPCPDEBUG((LOG_INFO, "remote IP address %s\n", - inet_ntoa(ciaddr2))); - } - ); - - /* - * Accept the peer's value of maxslotindex provided that it - * is less than what we asked for. Turn off slot-ID compression - * if the peer wants. Send old-style compress-type option if - * the peer wants. - */ - NAKCIVJ(CI_COMPRESSTYPE, neg_vj, - if (cilen == CILEN_VJ) { - GETCHAR(cimaxslotindex, p); - GETCHAR(cicflag, p); - if (cishort == IPCP_VJ_COMP) { - try.old_vj = 0; - if (cimaxslotindex < go->maxslotindex) { - try.maxslotindex = cimaxslotindex; - } - if (!cicflag) { - try.cflag = 0; - } - } else { - try.neg_vj = 0; - } - } else { - if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { - try.old_vj = 1; - try.vj_protocol = cishort; - } else { - try.neg_vj = 0; - } - } - ); - - NAKCIDNS(CI_MS_DNS1, req_dns1, - try.dnsaddr[0] = cidnsaddr; - IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr))); - ); - - NAKCIDNS(CI_MS_DNS2, req_dns2, - try.dnsaddr[1] = cidnsaddr; - IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr))); - ); - - /* - * There may be remaining CIs, if the peer is requesting negotiation - * on an option that we didn't include in our request packet. - * If they want to negotiate about IP addresses, we comply. - * If they want us to ask for compression, we refuse. - */ - while (len > CILEN_VOID) { - GETCHAR(citype, p); - GETCHAR(cilen, p); - if( (len -= cilen) < 0 ) { - goto bad; - } - next = p + cilen - 2; - - switch (citype) { - case CI_COMPRESSTYPE: - if (go->neg_vj || no.neg_vj || - (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) { - goto bad; - } - no.neg_vj = 1; - break; - case CI_ADDRS: - if ((go->neg_addr && go->old_addrs) || no.old_addrs - || cilen != CILEN_ADDRS) { - goto bad; - } - try.neg_addr = 1; - try.old_addrs = 1; - GETLONG(l, p); - ciaddr1 = htonl(l); - if (ciaddr1 && go->accept_local) { - try.ouraddr = ciaddr1; - } - GETLONG(l, p); - ciaddr2 = htonl(l); - if (ciaddr2 && go->accept_remote) { - try.hisaddr = ciaddr2; - } - no.old_addrs = 1; - break; - case CI_ADDR: - if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) { - goto bad; - } - try.old_addrs = 0; - GETLONG(l, p); - ciaddr1 = htonl(l); - if (ciaddr1 && go->accept_local) { - try.ouraddr = ciaddr1; - } - if (try.ouraddr != 0) { - try.neg_addr = 1; - } - no.neg_addr = 1; - break; - } - p = next; - } - - /* If there is still anything left, this packet is bad. */ - if (len != 0) { - goto bad; - } - - /* - * OK, the Nak is good. Now we can update state. - */ - if (f->state != LS_OPENED) { - *go = try; - } - - return 1; - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n")); - return 0; -} - - -/* - * ipcp_rejci - Reject some of our CIs. - */ -static int -ipcp_rejci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_char cimaxslotindex, ciflag, cilen; - u_short cishort; - u32_t cilong; - ipcp_options try; /* options to request next time */ - - try = *go; - /* - * Any Rejected CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define REJCIADDR(opt, neg, old, val1, val2) \ - if (go->neg && \ - len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \ - p[1] == cilen && \ - p[0] == opt) { \ - u32_t l; \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != val1) { \ - goto bad; \ - } \ - if (old) { \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != val2) { \ - goto bad; \ - } \ - } \ - try.neg = 0; \ - } - -#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ - if (go->neg && \ - p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ - len >= p[1] && \ - p[0] == opt) { \ - len -= p[1]; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - /* Check rejected value. */ \ - if (cishort != val) { \ - goto bad; \ - } \ - if (!old) { \ - GETCHAR(cimaxslotindex, p); \ - if (cimaxslotindex != maxslot) { \ - goto bad; \ - } \ - GETCHAR(ciflag, p); \ - if (ciflag != cflag) { \ - goto bad; \ - } \ - } \ - try.neg = 0; \ - } - -#define REJCIDNS(opt, neg, dnsaddr) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_ADDR) && \ - len >= cilen && \ - p[0] == opt) { \ - u32_t l; \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != dnsaddr) { \ - goto bad; \ - } \ - try.neg = 0; \ - } - - REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); - - REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) { - goto bad; - } - /* - * Now we can update state. - */ - if (f->state != LS_OPENED) { - *go = try; - } - return 1; - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n")); - return 0; -} - - -/* - * ipcp_reqci - Check the peer's requested CIs and send appropriate response. - * - * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified - * appropriately. If reject_if_disagree is non-zero, doesn't return - * CONFNAK; returns CONFREJ if it can't return CONFACK. - */ -static int -ipcp_reqci(fsm *f, u_char *inp/* Requested CIs */,int *len/* Length of requested CIs */,int reject_if_disagree) -{ - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - ipcp_options *ao = &ipcp_allowoptions[f->unit]; -#ifdef OLD_CI_ADDRS - ipcp_options *go = &ipcp_gotoptions[f->unit]; -#endif - u_char *cip, *next; /* Pointer to current and next CIs */ - u_short cilen, citype; /* Parsed len, type */ - u_short cishort; /* Parsed short value */ - u32_t tl, ciaddr1; /* Parsed address values */ -#ifdef OLD_CI_ADDRS - u32_t ciaddr2; /* Parsed address values */ -#endif - int rc = CONFACK; /* Final packet return code */ - int orc; /* Individual option return code */ - u_char *p; /* Pointer to next char to parse */ - u_char *ucp = inp; /* Pointer to current output char */ - int l = *len; /* Length left */ - u_char maxslotindex, cflag; - int d; - - cis_received[f->unit] = 1; - - /* - * Reset all his options. - */ - BZERO(ho, sizeof(*ho)); - - /* - * Process all his options. - */ - next = inp; - while (l) { - orc = CONFACK; /* Assume success */ - cip = p = next; /* Remember begining of CI */ - if (l < 2 || /* Not enough data for CI header or */ - p[1] < 2 || /* CI length too small or */ - p[1] > l) { /* CI length too big? */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n")); - orc = CONFREJ; /* Reject bad CI */ - cilen = l; /* Reject till end of packet */ - l = 0; /* Don't loop again */ - goto endswitch; - } - GETCHAR(citype, p); /* Parse CI type */ - GETCHAR(cilen, p); /* Parse CI length */ - l -= cilen; /* Adjust remaining length */ - next += cilen; /* Step to next CI */ - - switch (citype) { /* Check CI type */ -#ifdef OLD_CI_ADDRS /* Need to save space... */ - case CI_ADDRS: - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n")); - if (!ao->neg_addr || - cilen != CILEN_ADDRS) { /* Check CI length */ - orc = CONFREJ; /* Reject CI */ - break; - } - - /* - * If he has no address, or if we both have his address but - * disagree about it, then NAK it with our idea. - * In particular, if we don't know his address, but he does, - * then accept it. - */ - GETLONG(tl, p); /* Parse source address (his) */ - ciaddr1 = htonl(tl); - IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1))); - if (ciaddr1 != wo->hisaddr - && (ciaddr1 == 0 || !wo->accept_remote)) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, p); - } - } else if (ciaddr1 == 0 && wo->hisaddr == 0) { - /* - * If neither we nor he knows his address, reject the option. - */ - orc = CONFREJ; - wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ - break; - } - - /* - * If he doesn't know our address, or if we both have our address - * but disagree about it, then NAK it with our idea. - */ - GETLONG(tl, p); /* Parse desination address (ours) */ - ciaddr2 = htonl(tl); - IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2))); - if (ciaddr2 != wo->ouraddr) { - if (ciaddr2 == 0 || !wo->accept_local) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->ouraddr); - PUTLONG(tl, p); - } - } else { - go->ouraddr = ciaddr2; /* accept peer's idea */ - } - } - - ho->neg_addr = 1; - ho->old_addrs = 1; - ho->hisaddr = ciaddr1; - ho->ouraddr = ciaddr2; - break; -#endif - - case CI_ADDR: - if (!ao->neg_addr) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n")); - orc = CONFREJ; /* Reject CI */ - break; - } else if (cilen != CILEN_ADDR) { /* Check CI length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n")); - orc = CONFREJ; /* Reject CI */ - break; - } - - /* - * If he has no address, or if we both have his address but - * disagree about it, then NAK it with our idea. - * In particular, if we don't know his address, but he does, - * then accept it. - */ - GETLONG(tl, p); /* Parse source address (his) */ - ciaddr1 = htonl(tl); - if (ciaddr1 != wo->hisaddr - && (ciaddr1 == 0 || !wo->accept_remote)) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, p); - } - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1))); - } else if (ciaddr1 == 0 && wo->hisaddr == 0) { - /* - * Don't ACK an address of 0.0.0.0 - reject it instead. - */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1))); - orc = CONFREJ; - wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ - break; - } - - ho->neg_addr = 1; - ho->hisaddr = ciaddr1; - IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1))); - break; - - case CI_MS_DNS1: - case CI_MS_DNS2: - /* Microsoft primary or secondary DNS request */ - d = citype == CI_MS_DNS2; - - /* If we do not have a DNS address then we cannot send it */ - if (ao->dnsaddr[d] == 0 || - cilen != CILEN_ADDR) { /* Check CI length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1)); - orc = CONFREJ; /* Reject CI */ - break; - } - GETLONG(tl, p); - if (htonl(tl) != ao->dnsaddr[d]) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n", - d+1, inet_ntoa(tl))); - DECPTR(sizeof(u32_t), p); - tl = ntohl(ao->dnsaddr[d]); - PUTLONG(tl, p); - orc = CONFNAK; - } - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1)); - break; - - case CI_MS_WINS1: - case CI_MS_WINS2: - /* Microsoft primary or secondary WINS request */ - d = citype == CI_MS_WINS2; - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1)); - - /* If we do not have a DNS address then we cannot send it */ - if (ao->winsaddr[d] == 0 || - cilen != CILEN_ADDR) { /* Check CI length */ - orc = CONFREJ; /* Reject CI */ - break; - } - GETLONG(tl, p); - if (htonl(tl) != ao->winsaddr[d]) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(ao->winsaddr[d]); - PUTLONG(tl, p); - orc = CONFNAK; - } - break; - - case CI_COMPRESSTYPE: - if (!ao->neg_vj) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen)); - orc = CONFREJ; - break; - } - GETSHORT(cishort, p); - - if (!(cishort == IPCP_VJ_COMP || - (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort)); - orc = CONFREJ; - break; - } - - ho->neg_vj = 1; - ho->vj_protocol = cishort; - if (cilen == CILEN_VJ) { - GETCHAR(maxslotindex, p); - if (maxslotindex > ao->maxslotindex) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex)); - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(1, p); - PUTCHAR(ao->maxslotindex, p); - } - } - GETCHAR(cflag, p); - if (cflag && !ao->cflag) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag)); - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(1, p); - PUTCHAR(wo->cflag, p); - } - } - ho->maxslotindex = maxslotindex; - ho->cflag = cflag; - } else { - ho->old_vj = 1; - ho->maxslotindex = MAX_SLOTS - 1; - ho->cflag = 1; - } - IPCPDEBUG((LOG_INFO, - "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n", - ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag)); - break; - - default: - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype)); - orc = CONFREJ; - break; - } - -endswitch: - if (orc == CONFACK && /* Good CI */ - rc != CONFACK) { /* but prior CI wasnt? */ - continue; /* Don't send this one */ - } - - if (orc == CONFNAK) { /* Nak this CI? */ - if (reject_if_disagree) { /* Getting fed up with sending NAKs? */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n")); - orc = CONFREJ; /* Get tough if so */ - } else { - if (rc == CONFREJ) { /* Rejecting prior CI? */ - continue; /* Don't send this one */ - } - if (rc == CONFACK) { /* Ack'd all prior CIs? */ - rc = CONFNAK; /* Not anymore... */ - ucp = inp; /* Backup */ - } - } - } - - if (orc == CONFREJ && /* Reject this CI */ - rc != CONFREJ) { /* but no prior ones? */ - rc = CONFREJ; - ucp = inp; /* Backup */ - } - - /* Need to move CI? */ - if (ucp != cip) { - BCOPY(cip, ucp, cilen); /* Move it */ - } - - /* Update output pointer */ - INCPTR(cilen, ucp); - } - - /* - * If we aren't rejecting this packet, and we want to negotiate - * their address, and they didn't send their address, then we - * send a NAK with a CI_ADDR option appended. We assume the - * input buffer is long enough that we can append the extra - * option safely. - */ - if (rc != CONFREJ && !ho->neg_addr && - wo->req_addr && !reject_if_disagree) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n")); - if (rc == CONFACK) { - rc = CONFNAK; - ucp = inp; /* reset pointer */ - wo->req_addr = 0; /* don't ask again */ - } - PUTCHAR(CI_ADDR, ucp); - PUTCHAR(CILEN_ADDR, ucp); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, ucp); - } - - *len = (int)(ucp - inp); /* Compute output length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc))); - return (rc); /* Return final code */ -} - - -#if 0 -/* - * ip_check_options - check that any IP-related options are OK, - * and assign appropriate defaults. - */ -static void -ip_check_options(u_long localAddr) -{ - ipcp_options *wo = &ipcp_wantoptions[0]; - - /* - * Load our default IP address but allow the remote host to give us - * a new address. - */ - if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) { - wo->accept_local = 1; /* don't insist on this default value */ - wo->ouraddr = htonl(localAddr); - } -} -#endif - - -/* - * ipcp_up - IPCP has come UP. - * - * Configure the IP network interface appropriately and bring it up. - */ -static void -ipcp_up(fsm *f) -{ - u32_t mask; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - ipcp_options *go = &ipcp_gotoptions[f->unit]; - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - - np_up(f->unit, PPP_IP); - IPCPDEBUG((LOG_INFO, "ipcp: up\n")); - - /* - * We must have a non-zero IP address for both ends of the link. - */ - if (!ho->neg_addr) { - ho->hisaddr = wo->hisaddr; - } - - if (ho->hisaddr == 0) { - IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n")); - ipcp_close(f->unit, "Could not determine remote IP address"); - return; - } - if (go->ouraddr == 0) { - IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n")); - ipcp_close(f->unit, "Could not determine local IP address"); - return; - } - - if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { - /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/ - } - - /* - * Check that the peer is allowed to use the IP address it wants. - */ - if (!auth_ip_addr(f->unit, ho->hisaddr)) { - IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n", - inet_ntoa(ho->hisaddr))); - ipcp_close(f->unit, "Unauthorized remote IP address"); - return; - } - - /* set tcp compression */ - sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex); - - /* - * Set IP addresses and (if specified) netmask. - */ - mask = GetMask(go->ouraddr); - - if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) { - IPCPDEBUG((LOG_WARNING, "sifaddr failed\n")); - ipcp_close(f->unit, "Interface configuration failed"); - return; - } - - /* bring the interface up for IP */ - if (!sifup(f->unit)) { - IPCPDEBUG((LOG_WARNING, "sifup failed\n")); - ipcp_close(f->unit, "Interface configuration failed"); - return; - } - - sifnpmode(f->unit, PPP_IP, NPMODE_PASS); - - /* assign a default route through the interface if required */ - if (ipcp_wantoptions[f->unit].default_route) { - if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) { - default_route_set[f->unit] = 1; - } - } - - IPCPDEBUG((LOG_NOTICE, "local IP address %s\n", inet_ntoa(go->ouraddr))); - IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr))); - if (go->dnsaddr[0]) { - IPCPDEBUG((LOG_NOTICE, "primary DNS address %s\n", inet_ntoa(go->dnsaddr[0]))); - } - if (go->dnsaddr[1]) { - IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1]))); - } -} - - -/* - * ipcp_down - IPCP has gone DOWN. - * - * Take the IP network interface down, clear its addresses - * and delete routes through it. - */ -static void -ipcp_down(fsm *f) -{ - IPCPDEBUG((LOG_INFO, "ipcp: down\n")); - np_down(f->unit, PPP_IP); - sifvjcomp(f->unit, 0, 0, 0); - - sifdown(f->unit); - ipcp_clear_addrs(f->unit); -} - - -/* - * ipcp_clear_addrs() - clear the interface addresses, routes, etc. - */ -static void -ipcp_clear_addrs(int unit) -{ - u32_t ouraddr, hisaddr; - - ouraddr = ipcp_gotoptions[unit].ouraddr; - hisaddr = ipcp_hisoptions[unit].hisaddr; - if (default_route_set[unit]) { - cifdefaultroute(unit, ouraddr, hisaddr); - default_route_set[unit] = 0; - } - cifaddr(unit, ouraddr, hisaddr); -} - - -/* - * ipcp_finished - possibly shut down the lower layers. - */ -static void -ipcp_finished(fsm *f) -{ - np_finished(f->unit, PPP_IP); -} - -#if 0 -static int -ipcp_printpkt(u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg) -{ - LWIP_UNUSED_ARG(p); - LWIP_UNUSED_ARG(plen); - LWIP_UNUSED_ARG(printer); - LWIP_UNUSED_ARG(arg); - return 0; -} - -/* - * ip_active_pkt - see if this IP packet is worth bringing the link up for. - * We don't bring the link up for IP fragments or for TCP FIN packets - * with no data. - */ -#define IP_HDRLEN 20 /* bytes */ -#define IP_OFFMASK 0x1fff -#define IPPROTO_TCP 6 -#define TCP_HDRLEN 20 -#define TH_FIN 0x01 - -/* - * We use these macros because the IP header may be at an odd address, - * and some compilers might use word loads to get th_off or ip_hl. - */ - -#define net_short(x) (((x)[0] << 8) + (x)[1]) -#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) -#define get_ipoff(x) net_short((unsigned char *)(x) + 6) -#define get_ipproto(x) (((unsigned char *)(x))[9]) -#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) -#define get_tcpflags(x) (((unsigned char *)(x))[13]) - -static int -ip_active_pkt(u_char *pkt, int len) -{ - u_char *tcp; - int hlen; - - len -= PPP_HDRLEN; - pkt += PPP_HDRLEN; - if (len < IP_HDRLEN) { - return 0; - } - if ((get_ipoff(pkt) & IP_OFFMASK) != 0) { - return 0; - } - if (get_ipproto(pkt) != IPPROTO_TCP) { - return 1; - } - hlen = get_iphl(pkt) * 4; - if (len < hlen + TCP_HDRLEN) { - return 0; - } - tcp = pkt + hlen; - if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) { - return 0; - } - return 1; -} -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/ipcp.h b/components/net/lwip-1.3.2/src/netif/ppp/ipcp.h deleted file mode 100644 index dfcf4fba61..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/ipcp.h +++ /dev/null @@ -1,124 +0,0 @@ -/***************************************************************************** -* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * ipcp.h - IP Control Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id: ipcp.h,v 1.3 2007/12/19 20:47:23 fbernon Exp $ - */ - -#ifndef IPCP_H -#define IPCP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Options. - */ -#define CI_ADDRS 1 /* IP Addresses */ -#define CI_COMPRESSTYPE 2 /* Compression Type */ -#define CI_ADDR 3 - -#define CI_MS_WINS1 128 /* Primary WINS value */ -#define CI_MS_DNS1 129 /* Primary DNS value */ -#define CI_MS_WINS2 130 /* Secondary WINS value */ -#define CI_MS_DNS2 131 /* Secondary DNS value */ - -#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ -#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ -#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ - /* maxslot and slot number compression) */ - -#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option */ -#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ - /* compression option */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -typedef struct ipcp_options { - u_int neg_addr : 1; /* Negotiate IP Address? */ - u_int old_addrs : 1; /* Use old (IP-Addresses) option? */ - u_int req_addr : 1; /* Ask peer to send IP address? */ - u_int default_route : 1; /* Assign default route through interface? */ - u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */ - u_int neg_vj : 1; /* Van Jacobson Compression? */ - u_int old_vj : 1; /* use old (short) form of VJ option? */ - u_int accept_local : 1; /* accept peer's value for ouraddr */ - u_int accept_remote : 1; /* accept peer's value for hisaddr */ - u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */ - u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */ - u_short vj_protocol; /* protocol value to use in VJ option */ - u_char maxslotindex; /* VJ slots - 1. */ - u_char cflag; /* VJ slot compression flag. */ - u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ - u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ - u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ -} ipcp_options; - - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -extern fsm ipcp_fsm[]; -extern ipcp_options ipcp_wantoptions[]; -extern ipcp_options ipcp_gotoptions[]; -extern ipcp_options ipcp_allowoptions[]; -extern ipcp_options ipcp_hisoptions[]; - -extern struct protent ipcp_protent; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -#endif /* IPCP_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/lcp.c b/components/net/lwip-1.3.2/src/netif/ppp/lcp.c deleted file mode 100644 index 85a0add95b..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/lcp.c +++ /dev/null @@ -1,2035 +0,0 @@ -/***************************************************************************** -* lcp.c - Network Link Control Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-01 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ - -/* - * lcp.c - PPP Link Control Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "fsm.h" -#include "chap.h" -#include "magic.h" -#include "auth.h" -#include "lcp.h" - -#include - -#if PPPOE_SUPPORT -#include "netif/ppp_oe.h" -#else -#define PPPOE_MAXMTU PPP_MAXMRU -#endif - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ -/* - * Length of each type of configuration option (in octets) - */ -#define CILEN_VOID 2 -#define CILEN_CHAR 3 -#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */ -#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */ -#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */ -#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */ -#define CILEN_CBCP 3 - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Callbacks for fsm code. (CI = Configuration Information) - */ -static void lcp_resetci (fsm*); /* Reset our CI */ -static int lcp_cilen (fsm*); /* Return length of our CI */ -static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */ -static int lcp_ackci (fsm*, u_char*, int); /* Peer ack'd our CI */ -static int lcp_nakci (fsm*, u_char*, int); /* Peer nak'd our CI */ -static int lcp_rejci (fsm*, u_char*, int); /* Peer rej'd our CI */ -static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */ -static void lcp_up (fsm*); /* We're UP */ -static void lcp_down (fsm*); /* We're DOWN */ -static void lcp_starting (fsm*); /* We need lower layer up */ -static void lcp_finished (fsm*); /* We need lower layer down */ -static int lcp_extcode (fsm*, int, u_char, u_char*, int); - -static void lcp_rprotrej (fsm*, u_char*, int); - -/* - * routines to send LCP echos to peer - */ -static void lcp_echo_lowerup (int); -static void lcp_echo_lowerdown (int); -static void LcpEchoTimeout (void*); -static void lcp_received_echo_reply (fsm*, int, u_char*, int); -static void LcpSendEchoRequest (fsm*); -static void LcpLinkFailure (fsm*); -static void LcpEchoCheck (fsm*); - -/* - * Protocol entry points. - * Some of these are called directly. - */ -static void lcp_input (int, u_char *, int); -static void lcp_protrej (int); - -#define CODENAME(x) ((x) == CONFACK ? "ACK" : (x) == CONFNAK ? "NAK" : "REJ") - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -/* global vars */ -LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ -lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */ -lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ -lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ -lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ -ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */ - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/ -static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ -static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ -static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */ -static u32_t lcp_echo_number = 0; /* ID number of next echo frame */ -static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */ - -static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ - -static fsm_callbacks lcp_callbacks = { /* LCP callback routines */ - lcp_resetci, /* Reset our Configuration Information */ - lcp_cilen, /* Length of our Configuration Information */ - lcp_addci, /* Add our Configuration Information */ - lcp_ackci, /* ACK our Configuration Information */ - lcp_nakci, /* NAK our Configuration Information */ - lcp_rejci, /* Reject our Configuration Information */ - lcp_reqci, /* Request peer's Configuration Information */ - lcp_up, /* Called when fsm reaches LS_OPENED state */ - lcp_down, /* Called when fsm leaves LS_OPENED state */ - lcp_starting, /* Called when we want the lower layer up */ - lcp_finished, /* Called when we want the lower layer down */ - NULL, /* Called when Protocol-Reject received */ - NULL, /* Retransmission is necessary */ - lcp_extcode, /* Called to handle LCP-specific codes */ - "LCP" /* String name of protocol */ -}; - -struct protent lcp_protent = { - PPP_LCP, - lcp_init, - lcp_input, - lcp_protrej, - lcp_lowerup, - lcp_lowerdown, - lcp_open, - lcp_close, -#if 0 - lcp_printpkt, - NULL, -#endif - 1, - "LCP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - -int lcp_loopbackfail = DEFLOOPBACKFAIL; - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * lcp_init - Initialize LCP. - */ -void -lcp_init(int unit) -{ - fsm *f = &lcp_fsm[unit]; - lcp_options *wo = &lcp_wantoptions[unit]; - lcp_options *ao = &lcp_allowoptions[unit]; - - f->unit = unit; - f->protocol = PPP_LCP; - f->callbacks = &lcp_callbacks; - - fsm_init(f); - - wo->passive = 0; - wo->silent = 0; - wo->restart = 0; /* Set to 1 in kernels or multi-line implementations */ - wo->neg_mru = 1; - wo->mru = PPP_DEFMRU; - wo->neg_asyncmap = 1; - wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ - wo->neg_chap = 0; /* Set to 1 on server */ - wo->neg_upap = 0; /* Set to 1 on server */ - wo->chap_mdtype = CHAP_DIGEST_MD5; - wo->neg_magicnumber = 1; - wo->neg_pcompression = 1; - wo->neg_accompression = 1; - wo->neg_lqr = 0; /* no LQR implementation yet */ - wo->neg_cbcp = 0; - - ao->neg_mru = 1; - ao->mru = PPP_MAXMRU; - ao->neg_asyncmap = 1; - ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ - ao->neg_chap = (CHAP_SUPPORT != 0); - ao->chap_mdtype = CHAP_DIGEST_MD5; - ao->neg_upap = (PAP_SUPPORT != 0); - ao->neg_magicnumber = 1; - ao->neg_pcompression = 1; - ao->neg_accompression = 1; - ao->neg_lqr = 0; /* no LQR implementation yet */ - ao->neg_cbcp = (CBCP_SUPPORT != 0); - - /* - * Set transmit escape for the flag and escape characters plus anything - * set for the allowable options. - */ - memset(xmit_accm[unit], 0, sizeof(xmit_accm[0])); - xmit_accm[unit][15] = 0x60; - xmit_accm[unit][0] = (u_char)((ao->asyncmap & 0xFF)); - xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF); - xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF); - xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF); - LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n", - xmit_accm[unit][0], - xmit_accm[unit][1], - xmit_accm[unit][2], - xmit_accm[unit][3])); - - lcp_phase[unit] = PHASE_INITIALIZE; -} - - -/* - * lcp_open - LCP is allowed to come up. - */ -void -lcp_open(int unit) -{ - fsm *f = &lcp_fsm[unit]; - lcp_options *wo = &lcp_wantoptions[unit]; - - f->flags = 0; - if (wo->passive) { - f->flags |= OPT_PASSIVE; - } - if (wo->silent) { - f->flags |= OPT_SILENT; - } - fsm_open(f); - - lcp_phase[unit] = PHASE_ESTABLISH; -} - - -/* - * lcp_close - Take LCP down. - */ -void -lcp_close(int unit, char *reason) -{ - fsm *f = &lcp_fsm[unit]; - - if (lcp_phase[unit] != PHASE_DEAD) { - lcp_phase[unit] = PHASE_TERMINATE; - } - if (f->state == LS_STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) { - /* - * This action is not strictly according to the FSM in RFC1548, - * but it does mean that the program terminates if you do an - * lcp_close() in passive/silent mode when a connection hasn't - * been established. - */ - f->state = LS_CLOSED; - lcp_finished(f); - } else { - fsm_close(&lcp_fsm[unit], reason); - } -} - - -/* - * lcp_lowerup - The lower layer is up. - */ -void -lcp_lowerup(int unit) -{ - lcp_options *wo = &lcp_wantoptions[unit]; - - /* - * Don't use A/C or protocol compression on transmission, - * but accept A/C and protocol compressed packets - * if we are going to ask for A/C and protocol compression. - */ - ppp_set_xaccm(unit, &xmit_accm[unit]); - ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0); - ppp_recv_config(unit, PPP_MRU, 0x00000000l, - wo->neg_pcompression, wo->neg_accompression); - peer_mru[unit] = PPP_MRU; - lcp_allowoptions[unit].asyncmap = (u_long)xmit_accm[unit][0] - | ((u_long)xmit_accm[unit][1] << 8) - | ((u_long)xmit_accm[unit][2] << 16) - | ((u_long)xmit_accm[unit][3] << 24); - LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n", - xmit_accm[unit][3], - xmit_accm[unit][2], - xmit_accm[unit][1], - xmit_accm[unit][0])); - - fsm_lowerup(&lcp_fsm[unit]); -} - - -/* - * lcp_lowerdown - The lower layer is down. - */ -void -lcp_lowerdown(int unit) -{ - fsm_lowerdown(&lcp_fsm[unit]); -} - -/* - * lcp_sprotrej - Send a Protocol-Reject for some protocol. - */ -void -lcp_sprotrej(int unit, u_char *p, int len) -{ - /* - * Send back the protocol and the information field of the - * rejected packet. We only get here if LCP is in the LS_OPENED state. - */ - - fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, p, len); -} - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * lcp_input - Input LCP packet. - */ -static void -lcp_input(int unit, u_char *p, int len) -{ - fsm *f = &lcp_fsm[unit]; - - fsm_input(f, p, len); -} - - -/* - * lcp_extcode - Handle a LCP-specific code. - */ -static int -lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len) -{ - u_char *magp; - - switch( code ){ - case PROTREJ: - lcp_rprotrej(f, inp, len); - break; - - case ECHOREQ: - if (f->state != LS_OPENED) { - break; - } - LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id)); - magp = inp; - PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp); - fsm_sdata(f, ECHOREP, id, inp, len); - break; - - case ECHOREP: - lcp_received_echo_reply(f, id, inp, len); - break; - - case DISCREQ: - break; - - default: - return 0; - } - return 1; -} - - -/* - * lcp_rprotrej - Receive an Protocol-Reject. - * - * Figure out which protocol is rejected and inform it. - */ -static void -lcp_rprotrej(fsm *f, u_char *inp, int len) -{ - int i; - struct protent *protp; - u_short prot; - - if (len < sizeof (u_short)) { - LCPDEBUG((LOG_INFO, "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n")); - return; - } - - GETSHORT(prot, inp); - - LCPDEBUG((LOG_INFO, "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", prot)); - - /* - * Protocol-Reject packets received in any state other than the LCP - * LS_OPENED state SHOULD be silently discarded. - */ - if( f->state != LS_OPENED ) { - LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", f->state)); - return; - } - - /* - * Upcall the proper Protocol-Reject routine. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (protp->protocol == prot && protp->enabled_flag) { - (*protp->protrej)(f->unit); - return; - } - } - - LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", prot)); -} - - -/* - * lcp_protrej - A Protocol-Reject was received. - */ -static void -lcp_protrej(int unit) -{ - LWIP_UNUSED_ARG(unit); - /* - * Can't reject LCP! - */ - LCPDEBUG((LOG_WARNING, "lcp_protrej: Received Protocol-Reject for LCP!\n")); - fsm_protreject(&lcp_fsm[unit]); -} - - -/* - * lcp_resetci - Reset our CI. - */ -static void -lcp_resetci(fsm *f) -{ - lcp_wantoptions[f->unit].magicnumber = magic(); - lcp_wantoptions[f->unit].numloops = 0; - lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit]; - peer_mru[f->unit] = PPP_MRU; - auth_reset(f->unit); -} - - -/* - * lcp_cilen - Return length of our CI. - */ -static int lcp_cilen(fsm *f) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - -#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) -#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) -#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) -#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) -#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) -#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) - /* - * NB: we only ask for one of CHAP and UPAP, even if we will - * accept either. - */ - return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + - LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + - LENCICHAP(go->neg_chap) + - LENCISHORT(!go->neg_chap && go->neg_upap) + - LENCILQR(go->neg_lqr) + - LENCICBCP(go->neg_cbcp) + - LENCILONG(go->neg_magicnumber) + - LENCIVOID(go->neg_pcompression) + - LENCIVOID(go->neg_accompression)); -} - - -/* - * lcp_addci - Add our desired CIs to a packet. - */ -static void -lcp_addci(fsm *f, u_char *ucp, int *lenp) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char *start_ucp = ucp; - -#define ADDCIVOID(opt, neg) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_VOID, ucp); \ - } -#define ADDCISHORT(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_SHORT, ucp); \ - PUTSHORT(val, ucp); \ - } -#define ADDCICHAP(opt, neg, val, digest) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_CHAP, ucp); \ - PUTSHORT(val, ucp); \ - PUTCHAR(digest, ucp); \ - } -#define ADDCILONG(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_LONG, ucp); \ - PUTLONG(val, ucp); \ - } -#define ADDCILQR(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_LQR, ucp); \ - PUTSHORT(PPP_LQR, ucp); \ - PUTLONG(val, ucp); \ - } -#define ADDCICHAR(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_CHAR, ucp); \ - PUTCHAR(val, ucp); \ - } - - ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); - ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap); - ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); - ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); - ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); - ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); - ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); - ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); - ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); - - if (ucp - start_ucp != *lenp) { - /* this should never happen, because peer_mtu should be 1500 */ - LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n")); - } -} - - -/* - * lcp_ackci - Ack our CIs. - * This should not modify any state if the Ack is bad. - * - * Returns: - * 0 - Ack was bad. - * 1 - Ack was good. - */ -static int -lcp_ackci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char cilen, citype, cichar; - u_short cishort; - u32_t cilong; - - /* - * CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define ACKCIVOID(opt, neg) \ - if (neg) { \ - if ((len -= CILEN_VOID) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_VOID || citype != opt) \ - goto bad; \ - } -#define ACKCISHORT(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_SHORT) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_SHORT || citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - } -#define ACKCICHAR(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_CHAR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_CHAR || citype != opt) \ - goto bad; \ - GETCHAR(cichar, p); \ - if (cichar != val) \ - goto bad; \ - } -#define ACKCICHAP(opt, neg, val, digest) \ - if (neg) { \ - if ((len -= CILEN_CHAP) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_CHAP || citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - GETCHAR(cichar, p); \ - if (cichar != digest) \ - goto bad; \ - } -#define ACKCILONG(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_LONG) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_LONG || citype != opt) \ - goto bad; \ - GETLONG(cilong, p); \ - if (cilong != val) \ - goto bad; \ - } -#define ACKCILQR(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_LQR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_LQR || citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != PPP_LQR) \ - goto bad; \ - GETLONG(cilong, p); \ - if (cilong != val) \ - goto bad; \ - } - - ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); - ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap); - ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); - ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); - ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); - ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); - ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); - ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); - ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) { - goto bad; - } - LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n")); - return (1); -bad: - LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n")); - return (0); -} - - -/* - * lcp_nakci - Peer has sent a NAK for some of our CIs. - * This should not modify any state if the Nak is bad - * or if LCP is in the LS_OPENED state. - * - * Returns: - * 0 - Nak was bad. - * 1 - Nak was good. - */ -static int -lcp_nakci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *wo = &lcp_wantoptions[f->unit]; - u_char citype, cichar, *next; - u_short cishort; - u32_t cilong; - lcp_options no; /* options we've seen Naks for */ - lcp_options try; /* options to request next time */ - int looped_back = 0; - int cilen; - - BZERO(&no, sizeof(no)); - try = *go; - - /* - * Any Nak'd CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define NAKCIVOID(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_VOID && \ - p[1] == CILEN_VOID && \ - p[0] == opt) { \ - len -= CILEN_VOID; \ - INCPTR(CILEN_VOID, p); \ - no.neg = 1; \ - code \ - } -#define NAKCICHAP(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_CHAP && \ - p[1] == CILEN_CHAP && \ - p[0] == opt) { \ - len -= CILEN_CHAP; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETCHAR(cichar, p); \ - no.neg = 1; \ - code \ - } -#define NAKCICHAR(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_CHAR && \ - p[1] == CILEN_CHAR && \ - p[0] == opt) { \ - len -= CILEN_CHAR; \ - INCPTR(2, p); \ - GETCHAR(cichar, p); \ - no.neg = 1; \ - code \ - } -#define NAKCISHORT(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_SHORT && \ - p[1] == CILEN_SHORT && \ - p[0] == opt) { \ - len -= CILEN_SHORT; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - no.neg = 1; \ - code \ - } -#define NAKCILONG(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_LONG && \ - p[1] == CILEN_LONG && \ - p[0] == opt) { \ - len -= CILEN_LONG; \ - INCPTR(2, p); \ - GETLONG(cilong, p); \ - no.neg = 1; \ - code \ - } -#define NAKCILQR(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_LQR && \ - p[1] == CILEN_LQR && \ - p[0] == opt) { \ - len -= CILEN_LQR; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETLONG(cilong, p); \ - no.neg = 1; \ - code \ - } - - /* - * We don't care if they want to send us smaller packets than - * we want. Therefore, accept any MRU less than what we asked for, - * but then ignore the new value when setting the MRU in the kernel. - * If they send us a bigger MRU than what we asked, accept it, up to - * the limit of the default MRU we'd get if we didn't negotiate. - */ - if (go->neg_mru && go->mru != PPP_DEFMRU) { - NAKCISHORT(CI_MRU, neg_mru, - if (cishort <= wo->mru || cishort < PPP_DEFMRU) { - try.mru = cishort; - } - ); - } - - /* - * Add any characters they want to our (receive-side) asyncmap. - */ - if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) { - NAKCILONG(CI_ASYNCMAP, neg_asyncmap, - try.asyncmap = go->asyncmap | cilong; - ); - } - - /* - * If they've nak'd our authentication-protocol, check whether - * they are proposing a different protocol, or a different - * hash algorithm for CHAP. - */ - if ((go->neg_chap || go->neg_upap) - && len >= CILEN_SHORT - && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { - cilen = p[1]; - len -= cilen; - no.neg_chap = go->neg_chap; - no.neg_upap = go->neg_upap; - INCPTR(2, p); - GETSHORT(cishort, p); - if (cishort == PPP_PAP && cilen == CILEN_SHORT) { - /* - * If we were asking for CHAP, they obviously don't want to do it. - * If we weren't asking for CHAP, then we were asking for PAP, - * in which case this Nak is bad. - */ - if (!go->neg_chap) { - goto bad; - } - try.neg_chap = 0; - - } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { - GETCHAR(cichar, p); - if (go->neg_chap) { - /* - * We were asking for CHAP/MD5; they must want a different - * algorithm. If they can't do MD5, we'll have to stop - * asking for CHAP. - */ - if (cichar != go->chap_mdtype) { - try.neg_chap = 0; - } - } else { - /* - * Stop asking for PAP if we were asking for it. - */ - try.neg_upap = 0; - } - - } else { - /* - * We don't recognize what they're suggesting. - * Stop asking for what we were asking for. - */ - if (go->neg_chap) { - try.neg_chap = 0; - } else { - try.neg_upap = 0; - } - p += cilen - CILEN_SHORT; - } - } - - /* - * If they can't cope with our link quality protocol, we'll have - * to stop asking for LQR. We haven't got any other protocol. - * If they Nak the reporting period, take their value XXX ? - */ - NAKCILQR(CI_QUALITY, neg_lqr, - if (cishort != PPP_LQR) { - try.neg_lqr = 0; - } else { - try.lqr_period = cilong; - } - ); - - /* - * Only implementing CBCP...not the rest of the callback options - */ - NAKCICHAR(CI_CALLBACK, neg_cbcp, - try.neg_cbcp = 0; - ); - - /* - * Check for a looped-back line. - */ - NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, - try.magicnumber = magic(); - looped_back = 1; - ); - - /* - * Peer shouldn't send Nak for protocol compression or - * address/control compression requests; they should send - * a Reject instead. If they send a Nak, treat it as a Reject. - */ - NAKCIVOID(CI_PCOMPRESSION, neg_pcompression, - try.neg_pcompression = 0; - ); - NAKCIVOID(CI_ACCOMPRESSION, neg_accompression, - try.neg_accompression = 0; - ); - - /* - * There may be remaining CIs, if the peer is requesting negotiation - * on an option that we didn't include in our request packet. - * If we see an option that we requested, or one we've already seen - * in this packet, then this packet is bad. - * If we wanted to respond by starting to negotiate on the requested - * option(s), we could, but we don't, because except for the - * authentication type and quality protocol, if we are not negotiating - * an option, it is because we were told not to. - * For the authentication type, the Nak from the peer means - * `let me authenticate myself with you' which is a bit pointless. - * For the quality protocol, the Nak means `ask me to send you quality - * reports', but if we didn't ask for them, we don't want them. - * An option we don't recognize represents the peer asking to - * negotiate some option we don't support, so ignore it. - */ - while (len > CILEN_VOID) { - GETCHAR(citype, p); - GETCHAR(cilen, p); - if (cilen < CILEN_VOID || (len -= cilen) < 0) { - goto bad; - } - next = p + cilen - 2; - - switch (citype) { - case CI_MRU: - if ((go->neg_mru && go->mru != PPP_DEFMRU) - || no.neg_mru || cilen != CILEN_SHORT) { - goto bad; - } - GETSHORT(cishort, p); - if (cishort < PPP_DEFMRU) { - try.mru = cishort; - } - break; - case CI_ASYNCMAP: - if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) - || no.neg_asyncmap || cilen != CILEN_LONG) { - goto bad; - } - break; - case CI_AUTHTYPE: - if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) { - goto bad; - } - break; - case CI_MAGICNUMBER: - if (go->neg_magicnumber || no.neg_magicnumber || - cilen != CILEN_LONG) { - goto bad; - } - break; - case CI_PCOMPRESSION: - if (go->neg_pcompression || no.neg_pcompression - || cilen != CILEN_VOID) { - goto bad; - } - break; - case CI_ACCOMPRESSION: - if (go->neg_accompression || no.neg_accompression - || cilen != CILEN_VOID) { - goto bad; - } - break; - case CI_QUALITY: - if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) { - goto bad; - } - break; - } - p = next; - } - - /* If there is still anything left, this packet is bad. */ - if (len != 0) { - goto bad; - } - - /* - * OK, the Nak is good. Now we can update state. - */ - if (f->state != LS_OPENED) { - if (looped_back) { - if (++try.numloops >= lcp_loopbackfail) { - LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n")); - lcp_close(f->unit, "Loopback detected"); - } - } else { - try.numloops = 0; - } - *go = try; - } - - return 1; - -bad: - LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n")); - return 0; -} - - -/* - * lcp_rejci - Peer has Rejected some of our CIs. - * This should not modify any state if the Reject is bad - * or if LCP is in the LS_OPENED state. - * - * Returns: - * 0 - Reject was bad. - * 1 - Reject was good. - */ -static int -lcp_rejci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char cichar; - u_short cishort; - u32_t cilong; - lcp_options try; /* options to request next time */ - - try = *go; - - /* - * Any Rejected CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define REJCIVOID(opt, neg) \ - if (go->neg && \ - len >= CILEN_VOID && \ - p[1] == CILEN_VOID && \ - p[0] == opt) { \ - len -= CILEN_VOID; \ - INCPTR(CILEN_VOID, p); \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \ - } -#define REJCISHORT(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_SHORT && \ - p[1] == CILEN_SHORT && \ - p[0] == opt) { \ - len -= CILEN_SHORT; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - /* Check rejected value. */ \ - if (cishort != val) { \ - goto bad; \ - } \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \ - } -#define REJCICHAP(opt, neg, val, digest) \ - if (go->neg && \ - len >= CILEN_CHAP && \ - p[1] == CILEN_CHAP && \ - p[0] == opt) { \ - len -= CILEN_CHAP; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETCHAR(cichar, p); \ - /* Check rejected value. */ \ - if (cishort != val || cichar != digest) { \ - goto bad; \ - } \ - try.neg = 0; \ - try.neg_upap = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \ - } -#define REJCILONG(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_LONG && \ - p[1] == CILEN_LONG && \ - p[0] == opt) { \ - len -= CILEN_LONG; \ - INCPTR(2, p); \ - GETLONG(cilong, p); \ - /* Check rejected value. */ \ - if (cilong != val) { \ - goto bad; \ - } \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \ - } -#define REJCILQR(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_LQR && \ - p[1] == CILEN_LQR && \ - p[0] == opt) { \ - len -= CILEN_LQR; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETLONG(cilong, p); \ - /* Check rejected value. */ \ - if (cishort != PPP_LQR || cilong != val) { \ - goto bad; \ - } \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \ - } -#define REJCICBCP(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_CBCP && \ - p[1] == CILEN_CBCP && \ - p[0] == opt) { \ - len -= CILEN_CBCP; \ - INCPTR(2, p); \ - GETCHAR(cichar, p); \ - /* Check rejected value. */ \ - if (cichar != val) { \ - goto bad; \ - } \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \ - } - - REJCISHORT(CI_MRU, neg_mru, go->mru); - REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); - REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype); - if (!go->neg_chap) { - REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); - } - REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); - REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); - REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); - REJCIVOID(CI_PCOMPRESSION, neg_pcompression); - REJCIVOID(CI_ACCOMPRESSION, neg_accompression); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) { - goto bad; - } - /* - * Now we can update state. - */ - if (f->state != LS_OPENED) { - *go = try; - } - return 1; - -bad: - LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n")); - return 0; -} - - -/* - * lcp_reqci - Check the peer's requested CIs and send appropriate response. - * - * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified - * appropriately. If reject_if_disagree is non-zero, doesn't return - * CONFNAK; returns CONFREJ if it can't return CONFACK. - */ -static int -lcp_reqci(fsm *f, - u_char *inp, /* Requested CIs */ - int *lenp, /* Length of requested CIs */ - int reject_if_disagree) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *ho = &lcp_hisoptions[f->unit]; - lcp_options *ao = &lcp_allowoptions[f->unit]; - u_char *cip, *next; /* Pointer to current and next CIs */ - int cilen, citype, cichar; /* Parsed len, type, char value */ - u_short cishort; /* Parsed short value */ - u32_t cilong; /* Parse long value */ - int rc = CONFACK; /* Final packet return code */ - int orc; /* Individual option return code */ - u_char *p; /* Pointer to next char to parse */ - u_char *rejp; /* Pointer to next char in reject frame */ - u_char *nakp; /* Pointer to next char in Nak frame */ - int l = *lenp; /* Length left */ -#if TRACELCP > 0 - char traceBuf[80]; - int traceNdx = 0; -#endif - - /* - * Reset all his options. - */ - BZERO(ho, sizeof(*ho)); - - /* - * Process all his options. - */ - next = inp; - nakp = nak_buffer; - rejp = inp; - while (l) { - orc = CONFACK; /* Assume success */ - cip = p = next; /* Remember begining of CI */ - if (l < 2 || /* Not enough data for CI header or */ - p[1] < 2 || /* CI length too small or */ - p[1] > l) { /* CI length too big? */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n")); - orc = CONFREJ; /* Reject bad CI */ - cilen = l; /* Reject till end of packet */ - l = 0; /* Don't loop again */ - citype = 0; - goto endswitch; - } - GETCHAR(citype, p); /* Parse CI type */ - GETCHAR(cilen, p); /* Parse CI length */ - l -= cilen; /* Adjust remaining length */ - next += cilen; /* Step to next CI */ - - switch (citype) { /* Check CI type */ - case CI_MRU: - if (!ao->neg_mru) { /* Allow option? */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n")); - orc = CONFREJ; /* Reject CI */ - break; - } else if (cilen != CILEN_SHORT) { /* Check CI length */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n")); - orc = CONFREJ; /* Reject CI */ - break; - } - GETSHORT(cishort, p); /* Parse MRU */ - - /* - * He must be able to receive at least our minimum. - * No need to check a maximum. If he sends a large number, - * we'll just ignore it. - */ - if (cishort < PPP_MINMRU) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n")); - orc = CONFNAK; /* Nak CI */ - PUTCHAR(CI_MRU, nakp); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */ - break; - } - ho->neg_mru = 1; /* Remember he sent MRU */ - ho->mru = cishort; /* And remember value */ -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort); - traceNdx = strlen(traceBuf); -#endif - break; - - case CI_ASYNCMAP: - if (!ao->neg_asyncmap) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_LONG) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n")); - orc = CONFREJ; - break; - } - GETLONG(cilong, p); - - /* - * Asyncmap must have set at least the bits - * which are set in lcp_allowoptions[unit].asyncmap. - */ - if ((ao->asyncmap & ~cilong) != 0) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", - cilong, ao->asyncmap)); - orc = CONFNAK; - PUTCHAR(CI_ASYNCMAP, nakp); - PUTCHAR(CILEN_LONG, nakp); - PUTLONG(ao->asyncmap | cilong, nakp); - break; - } - ho->neg_asyncmap = 1; - ho->asyncmap = cilong; -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong); - traceNdx = strlen(traceBuf); -#endif - break; - - case CI_AUTHTYPE: - if (cilen < CILEN_SHORT) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n")); - orc = CONFREJ; - break; - } else if (!(ao->neg_upap || ao->neg_chap)) { - /* - * Reject the option if we're not willing to authenticate. - */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n")); - orc = CONFREJ; - break; - } - GETSHORT(cishort, p); - - /* - * Authtype must be UPAP or CHAP. - * - * Note: if both ao->neg_upap and ao->neg_chap are set, - * and the peer sends a Configure-Request with two - * authenticate-protocol requests, one for CHAP and one - * for UPAP, then we will reject the second request. - * Whether we end up doing CHAP or UPAP depends then on - * the ordering of the CIs in the peer's Configure-Request. - */ - - if (cishort == PPP_PAP) { - if (ho->neg_chap) { /* we've already accepted CHAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_SHORT) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n")); - orc = CONFREJ; - break; - } - if (!ao->neg_upap) { /* we don't want to do PAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n")); - orc = CONFNAK; /* NAK it and suggest CHAP */ - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - break; - } - ho->neg_upap = 1; -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort); - traceNdx = strlen(traceBuf); -#endif - break; - } - if (cishort == PPP_CHAP) { - if (ho->neg_upap) { /* we've already accepted PAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_CHAP) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n")); - orc = CONFREJ; - break; - } - if (!ao->neg_chap) { /* we don't want to do CHAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n")); - orc = CONFNAK; /* NAK it and suggest PAP */ - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_PAP, nakp); - break; - } - GETCHAR(cichar, p); /* get digest type*/ - if (cichar != CHAP_DIGEST_MD5 -#ifdef CHAPMS - && cichar != CHAP_MICROSOFT -#endif - ) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar)); - orc = CONFNAK; - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - break; - } -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar); - traceNdx = strlen(traceBuf); -#endif - ho->chap_mdtype = cichar; /* save md type */ - ho->neg_chap = 1; - break; - } - - /* - * We don't recognize the protocol they're asking for. - * Nak it with something we're willing to do. - * (At this point we know ao->neg_upap || ao->neg_chap.) - */ - orc = CONFNAK; - PUTCHAR(CI_AUTHTYPE, nakp); - if (ao->neg_chap) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort)); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - } else { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort)); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_PAP, nakp); - } - break; - - case CI_QUALITY: - GETSHORT(cishort, p); - GETLONG(cilong, p); -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong); - traceNdx = strlen(traceBuf); -#endif - - if (!ao->neg_lqr || - cilen != CILEN_LQR) { - orc = CONFREJ; - break; - } - - /* - * Check the protocol and the reporting period. - * XXX When should we Nak this, and what with? - */ - if (cishort != PPP_LQR) { - orc = CONFNAK; - PUTCHAR(CI_QUALITY, nakp); - PUTCHAR(CILEN_LQR, nakp); - PUTSHORT(PPP_LQR, nakp); - PUTLONG(ao->lqr_period, nakp); - break; - } - break; - - case CI_MAGICNUMBER: - if (!(ao->neg_magicnumber || go->neg_magicnumber) || - cilen != CILEN_LONG) { - orc = CONFREJ; - break; - } - GETLONG(cilong, p); -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong); - traceNdx = strlen(traceBuf); -#endif - - /* - * He must have a different magic number. - */ - if (go->neg_magicnumber && - cilong == go->magicnumber) { - cilong = magic(); /* Don't put magic() inside macro! */ - orc = CONFNAK; - PUTCHAR(CI_MAGICNUMBER, nakp); - PUTCHAR(CILEN_LONG, nakp); - PUTLONG(cilong, nakp); - break; - } - ho->neg_magicnumber = 1; - ho->magicnumber = cilong; - break; - - - case CI_PCOMPRESSION: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION"); - traceNdx = strlen(traceBuf); -#endif - if (!ao->neg_pcompression || - cilen != CILEN_VOID) { - orc = CONFREJ; - break; - } - ho->neg_pcompression = 1; - break; - - case CI_ACCOMPRESSION: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION"); - traceNdx = strlen(traceBuf); -#endif - if (!ao->neg_accompression || - cilen != CILEN_VOID) { - orc = CONFREJ; - break; - } - ho->neg_accompression = 1; - break; - - case CI_MRRU: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - case CI_SSNHF: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - case CI_EPDISC: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - default: -#if TRACELCP - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - } - - endswitch: -#if TRACELCP - if (traceNdx >= 80 - 32) { - LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf)); - traceNdx = 0; - } -#endif - if (orc == CONFACK && /* Good CI */ - rc != CONFACK) { /* but prior CI wasnt? */ - continue; /* Don't send this one */ - } - - if (orc == CONFNAK) { /* Nak this CI? */ - if (reject_if_disagree /* Getting fed up with sending NAKs? */ - && citype != CI_MAGICNUMBER) { - orc = CONFREJ; /* Get tough if so */ - } else { - if (rc == CONFREJ) { /* Rejecting prior CI? */ - continue; /* Don't send this one */ - } - rc = CONFNAK; - } - } - if (orc == CONFREJ) { /* Reject this CI */ - rc = CONFREJ; - if (cip != rejp) { /* Need to move rejected CI? */ - BCOPY(cip, rejp, cilen); /* Move it */ - } - INCPTR(cilen, rejp); /* Update output pointer */ - } - } - - /* - * If we wanted to send additional NAKs (for unsent CIs), the - * code would go here. The extra NAKs would go at *nakp. - * At present there are no cases where we want to ask the - * peer to negotiate an option. - */ - - switch (rc) { - case CONFACK: - *lenp = (int)(next - inp); - break; - case CONFNAK: - /* - * Copy the Nak'd options from the nak_buffer to the caller's buffer. - */ - *lenp = (int)(nakp - nak_buffer); - BCOPY(nak_buffer, inp, *lenp); - break; - case CONFREJ: - *lenp = (int)(rejp - inp); - break; - } - -#if TRACELCP > 0 - if (traceNdx > 0) { - LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf)); - } -#endif - LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc))); - return (rc); /* Return final code */ -} - - -/* - * lcp_up - LCP has come UP. - */ -static void -lcp_up(fsm *f) -{ - lcp_options *wo = &lcp_wantoptions[f->unit]; - lcp_options *ho = &lcp_hisoptions[f->unit]; - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *ao = &lcp_allowoptions[f->unit]; - - if (!go->neg_magicnumber) { - go->magicnumber = 0; - } - if (!ho->neg_magicnumber) { - ho->magicnumber = 0; - } - - /* - * Set our MTU to the smaller of the MTU we wanted and - * the MRU our peer wanted. If we negotiated an MRU, - * set our MRU to the larger of value we wanted and - * the value we got in the negotiation. - */ - ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)), - (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl), - ho->neg_pcompression, ho->neg_accompression); - /* - * If the asyncmap hasn't been negotiated, we really should - * set the receive asyncmap to ffffffff, but we set it to 0 - * for backwards contemptibility. - */ - ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU), - (go->neg_asyncmap? go->asyncmap: 0x00000000), - go->neg_pcompression, go->neg_accompression); - - if (ho->neg_mru) { - peer_mru[f->unit] = ho->mru; - } - - lcp_echo_lowerup(f->unit); /* Enable echo messages */ - - link_established(f->unit); -} - - -/* - * lcp_down - LCP has gone DOWN. - * - * Alert other protocols. - */ -static void -lcp_down(fsm *f) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - - lcp_echo_lowerdown(f->unit); - - link_down(f->unit); - - ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0); - ppp_recv_config(f->unit, PPP_MRU, - (go->neg_asyncmap? go->asyncmap: 0x00000000), - go->neg_pcompression, go->neg_accompression); - peer_mru[f->unit] = PPP_MRU; -} - - -/* - * lcp_starting - LCP needs the lower layer up. - */ -static void -lcp_starting(fsm *f) -{ - link_required(f->unit); -} - - -/* - * lcp_finished - LCP has finished with the lower layer. - */ -static void -lcp_finished(fsm *f) -{ - link_terminated(f->unit); -} - - -#if 0 -/* - * print_string - print a readable representation of a string using - * printer. - */ -static void -print_string( char *p, int len, void (*printer) (void *, char *, ...), void *arg) -{ - int c; - - printer(arg, "\""); - for (; len > 0; --len) { - c = *p++; - if (' ' <= c && c <= '~') { - if (c == '\\' || c == '"') { - printer(arg, "\\"); - } - printer(arg, "%c", c); - } else { - switch (c) { - case '\n': - printer(arg, "\\n"); - break; - case '\r': - printer(arg, "\\r"); - break; - case '\t': - printer(arg, "\\t"); - break; - default: - printer(arg, "\\%.3o", c); - } - } - } - printer(arg, "\""); -} - - -/* - * lcp_printpkt - print the contents of an LCP packet. - */ -static char *lcp_codenames[] = { - "ConfReq", "ConfAck", "ConfNak", "ConfRej", - "TermReq", "TermAck", "CodeRej", "ProtRej", - "EchoReq", "EchoRep", "DiscReq" -}; - -static int -lcp_printpkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg) -{ - int code, id, len, olen; - u_char *pstart, *optend; - u_short cishort; - u32_t cilong; - - if (plen < HEADERLEN) { - return 0; - } - pstart = p; - GETCHAR(code, p); - GETCHAR(id, p); - GETSHORT(len, p); - if (len < HEADERLEN || len > plen) { - return 0; - } - - if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) { - printer(arg, " %s", lcp_codenames[code-1]); - } else { - printer(arg, " code=0x%x", code); - } - printer(arg, " id=0x%x", id); - len -= HEADERLEN; - switch (code) { - case CONFREQ: - case CONFACK: - case CONFNAK: - case CONFREJ: - /* print option list */ - while (len >= 2) { - GETCHAR(code, p); - GETCHAR(olen, p); - p -= 2; - if (olen < 2 || olen > len) { - break; - } - printer(arg, " <"); - len -= olen; - optend = p + olen; - switch (code) { - case CI_MRU: - if (olen == CILEN_SHORT) { - p += 2; - GETSHORT(cishort, p); - printer(arg, "mru %d", cishort); - } - break; - case CI_ASYNCMAP: - if (olen == CILEN_LONG) { - p += 2; - GETLONG(cilong, p); - printer(arg, "asyncmap 0x%lx", cilong); - } - break; - case CI_AUTHTYPE: - if (olen >= CILEN_SHORT) { - p += 2; - printer(arg, "auth "); - GETSHORT(cishort, p); - switch (cishort) { - case PPP_PAP: - printer(arg, "pap"); - break; - case PPP_CHAP: - printer(arg, "chap"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_QUALITY: - if (olen >= CILEN_SHORT) { - p += 2; - printer(arg, "quality "); - GETSHORT(cishort, p); - switch (cishort) { - case PPP_LQR: - printer(arg, "lqr"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_CALLBACK: - if (olen >= CILEN_CHAR) { - p += 2; - printer(arg, "callback "); - GETSHORT(cishort, p); - switch (cishort) { - case CBCP_OPT: - printer(arg, "CBCP"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_MAGICNUMBER: - if (olen == CILEN_LONG) { - p += 2; - GETLONG(cilong, p); - printer(arg, "magic 0x%x", cilong); - } - break; - case CI_PCOMPRESSION: - if (olen == CILEN_VOID) { - p += 2; - printer(arg, "pcomp"); - } - break; - case CI_ACCOMPRESSION: - if (olen == CILEN_VOID) { - p += 2; - printer(arg, "accomp"); - } - break; - } - while (p < optend) { - GETCHAR(code, p); - printer(arg, " %.2x", code); - } - printer(arg, ">"); - } - break; - - case TERMACK: - case TERMREQ: - if (len > 0 && *p >= ' ' && *p < 0x7f) { - printer(arg, " "); - print_string((char*)p, len, printer, arg); - p += len; - len = 0; - } - break; - - case ECHOREQ: - case ECHOREP: - case DISCREQ: - if (len >= 4) { - GETLONG(cilong, p); - printer(arg, " magic=0x%x", cilong); - p += 4; - len -= 4; - } - break; - } - - /* print the rest of the bytes in the packet */ - for (; len > 0; --len) { - GETCHAR(code, p); - printer(arg, " %.2x", code); - } - - return (int)(p - pstart); -} -#endif - -/* - * Time to shut down the link because there is nothing out there. - */ -static void -LcpLinkFailure (fsm *f) -{ - if (f->state == LS_OPENED) { - LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending)); - LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n")); - lcp_close(f->unit, "Peer not responding"); - } -} - -/* - * Timer expired for the LCP echo requests from this process. - */ -static void -LcpEchoCheck (fsm *f) -{ - LcpSendEchoRequest (f); - - /* - * Start the timer for the next interval. - */ - LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0); - - TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval); - lcp_echo_timer_running = 1; -} - -/* - * LcpEchoTimeout - Timer expired on the LCP echo - */ -static void -LcpEchoTimeout (void *arg) -{ - if (lcp_echo_timer_running != 0) { - lcp_echo_timer_running = 0; - LcpEchoCheck ((fsm *) arg); - } -} - -/* - * LcpEchoReply - LCP has received a reply to the echo - */ -static void -lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len) -{ - u32_t magic; - - LWIP_UNUSED_ARG(id); - - /* Check the magic number - don't count replies from ourselves. */ - if (len < 4) { - LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len)); - return; - } - GETLONG(magic, inp); - if (lcp_gotoptions[f->unit].neg_magicnumber && magic == lcp_gotoptions[f->unit].magicnumber) { - LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n")); - return; - } - - /* Reset the number of outstanding echo frames */ - lcp_echos_pending = 0; -} - -/* - * LcpSendEchoRequest - Send an echo request frame to the peer - */ -static void -LcpSendEchoRequest (fsm *f) -{ - u32_t lcp_magic; - u_char pkt[4], *pktp; - - /* - * Detect the failure of the peer at this point. - */ - if (lcp_echo_fails != 0) { - if (lcp_echos_pending++ >= lcp_echo_fails) { - LcpLinkFailure(f); - lcp_echos_pending = 0; - } - } - - /* - * Make and send the echo request frame. - */ - if (f->state == LS_OPENED) { - lcp_magic = lcp_gotoptions[f->unit].magicnumber; - pktp = pkt; - PUTLONG(lcp_magic, pktp); - fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt)); - } -} - -/* - * lcp_echo_lowerup - Start the timer for the LCP frame - */ - -static void -lcp_echo_lowerup (int unit) -{ - fsm *f = &lcp_fsm[unit]; - - /* Clear the parameters for generating echo frames */ - lcp_echos_pending = 0; - lcp_echo_number = 0; - lcp_echo_timer_running = 0; - - /* If a timeout interval is specified then start the timer */ - if (lcp_echo_interval != 0) { - LcpEchoCheck (f); - } -} - -/* - * lcp_echo_lowerdown - Stop the timer for the LCP frame - */ - -static void -lcp_echo_lowerdown (int unit) -{ - fsm *f = &lcp_fsm[unit]; - - if (lcp_echo_timer_running != 0) { - UNTIMEOUT (LcpEchoTimeout, f); - lcp_echo_timer_running = 0; - } -} - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/lcp.h b/components/net/lwip-1.3.2/src/netif/ppp/lcp.h deleted file mode 100644 index 1a5e5a4c08..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/lcp.h +++ /dev/null @@ -1,167 +0,0 @@ -/***************************************************************************** -* lcp.h - Network Link Control Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * lcp.h - Link Control Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id: lcp.h,v 1.3 2007/12/19 20:47:23 fbernon Exp $ - */ - -#ifndef LCP_H -#define LCP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Options. - */ -#define CI_MRU 1 /* Maximum Receive Unit */ -#define CI_ASYNCMAP 2 /* Async Control Character Map */ -#define CI_AUTHTYPE 3 /* Authentication Type */ -#define CI_QUALITY 4 /* Quality Protocol */ -#define CI_MAGICNUMBER 5 /* Magic Number */ -#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ -#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ -#define CI_CALLBACK 13 /* callback */ -#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ -#define CI_SSNHF 18 /* short sequence numbers for multilink */ -#define CI_EPDISC 19 /* endpoint discriminator */ - -/* - * LCP-specific packet types. - */ -#define PROTREJ 8 /* Protocol Reject */ -#define ECHOREQ 9 /* Echo Request */ -#define ECHOREP 10 /* Echo Reply */ -#define DISCREQ 11 /* Discard Request */ -#define CBCP_OPT 6 /* Use callback control protocol */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * The state of options is described by an lcp_options structure. - */ -typedef struct lcp_options { - u_int passive : 1; /* Don't die if we don't get a response */ - u_int silent : 1; /* Wait for the other end to start first */ - u_int restart : 1; /* Restart vs. exit after close */ - u_int neg_mru : 1; /* Negotiate the MRU? */ - u_int neg_asyncmap : 1; /* Negotiate the async map? */ - u_int neg_upap : 1; /* Ask for UPAP authentication? */ - u_int neg_chap : 1; /* Ask for CHAP authentication? */ - u_int neg_magicnumber : 1; /* Ask for magic number? */ - u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */ - u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */ - u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */ - u_int neg_cbcp : 1; /* Negotiate use of CBCP */ -#ifdef PPP_MULTILINK - u_int neg_mrru : 1; /* Negotiate multilink MRRU */ - u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */ - u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */ -#endif - u_short mru; /* Value of MRU */ -#ifdef PPP_MULTILINK - u_short mrru; /* Value of MRRU, and multilink enable */ -#endif - u_char chap_mdtype; /* which MD type (hashing algorithm) */ - u32_t asyncmap; /* Value of async map */ - u32_t magicnumber; - int numloops; /* Number of loops during magic number neg. */ - u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ -#ifdef PPP_MULTILINK - struct epdisc endpoint; /* endpoint discriminator */ -#endif -} lcp_options; - -/* - * Values for phase from BSD pppd.h based on RFC 1661. - */ -typedef enum { - PHASE_DEAD = 0, - PHASE_INITIALIZE, - PHASE_ESTABLISH, - PHASE_AUTHENTICATE, - PHASE_CALLBACK, - PHASE_NETWORK, - PHASE_TERMINATE -} LinkPhase; - - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ -extern lcp_options lcp_wantoptions[]; -extern lcp_options lcp_gotoptions[]; -extern lcp_options lcp_allowoptions[]; -extern lcp_options lcp_hisoptions[]; -extern ext_accm xmit_accm[]; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -void lcp_init (int); -void lcp_open (int); -void lcp_close (int, char *); -void lcp_lowerup (int); -void lcp_lowerdown(int); -void lcp_sprotrej (int, u_char *, int); /* send protocol reject */ - -extern struct protent lcp_protent; - -/* Default number of times we receive our magic number from the peer - before deciding the link is looped-back. */ -#define DEFLOOPBACKFAIL 10 - -#endif /* LCP_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/magic.c b/components/net/lwip-1.3.2/src/netif/ppp/magic.c deleted file mode 100644 index d3922bb569..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/magic.c +++ /dev/null @@ -1,82 +0,0 @@ -/***************************************************************************** -* magic.c - Network Random Number Generator program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD magic.c. -*****************************************************************************/ -/* - * magic.c - PPP Magic Number routines. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT - -#include "ppp.h" -#include "randm.h" -#include "magic.h" - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * magicInit - Initialize the magic number generator. - * - * Since we use another random number generator that has its own - * initialization, we do nothing here. - */ -void magicInit() -{ - return; -} - -/* - * magic - Returns the next magic number. - */ -u32_t magic() -{ - return avRandom(); -} - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/magic.h b/components/net/lwip-1.3.2/src/netif/ppp/magic.h deleted file mode 100644 index bc51749933..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/magic.h +++ /dev/null @@ -1,67 +0,0 @@ -/***************************************************************************** -* magic.h - Network Random Number Generator header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * magic.h - PPP Magic Number definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id: magic.h,v 1.2 2007/12/02 22:35:55 fbernon Exp $ - */ - -#ifndef MAGIC_H -#define MAGIC_H - -/***************************************************************************** -************************** PUBLIC FUNCTIONS ********************************** -*****************************************************************************/ - -/* Initialize the magic number generator */ -void magicInit(void); - -/* Returns the next magic number */ -u32_t magic(void); - -#endif /* MAGIC_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/md5.c b/components/net/lwip-1.3.2/src/netif/ppp/md5.c deleted file mode 100644 index 7a60d78325..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/md5.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - *********************************************************************** - ** md5.c -- the source code for MD5 routines ** - ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** - ** Created: 2/17/90 RLR ** - ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. ** - *********************************************************************** - */ - -/* - *********************************************************************** - ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** - ** ** - ** License to copy and use this software is granted provided that ** - ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** - ** Digest Algorithm" in all material mentioning or referencing this ** - ** software or this function. ** - ** ** - ** License is also granted to make and use derivative works ** - ** provided that such works are identified as "derived from the RSA ** - ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** - ** material mentioning or referencing the derived work. ** - ** ** - ** RSA Data Security, Inc. makes no representations concerning ** - ** either the merchantability of this software or the suitability ** - ** of this software for any particular purpose. It is provided "as ** - ** is" without express or implied warranty of any kind. ** - ** ** - ** These notices must be retained in any copies of any part of this ** - ** documentation and/or software. ** - *********************************************************************** - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#if CHAP_SUPPORT || MD5_SUPPORT - -#include "ppp.h" -#include "pppdebug.h" - -#include "md5.h" - -#include - -/* - *********************************************************************** - ** Message-digest routines: ** - ** To form the message digest for a message M ** - ** (1) Initialize a context buffer mdContext using MD5Init ** - ** (2) Call MD5Update on mdContext and M ** - ** (3) Call MD5Final on mdContext ** - ** The message digest is now in mdContext->digest[0...15] ** - *********************************************************************** - */ - -/* forward declaration */ -static void Transform (u32_t *buf, u32_t *in); - -static unsigned char PADDING[64] = { - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -/* F, G, H and I are basic MD5 functions */ -#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) -#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) -#define H(x, y, z) ((x) ^ (y) ^ (z)) -#define I(x, y, z) ((y) ^ ((x) | (~z))) - -/* ROTATE_LEFT rotates x left n bits */ -#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) - -/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */ -/* Rotation is separate from addition to prevent recomputation */ -#define FF(a, b, c, d, x, s, ac) \ - {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define GG(a, b, c, d, x, s, ac) \ - {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define HH(a, b, c, d, x, s, ac) \ - {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define II(a, b, c, d, x, s, ac) \ - {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } - -#ifdef __STDC__ -#define UL(x) x##UL -#else -#ifdef WIN32 -#define UL(x) x##UL -#else -#define UL(x) x -#endif -#endif - -/* The routine MD5Init initializes the message-digest context - mdContext. All fields are set to zero. - */ -void -MD5Init (MD5_CTX *mdContext) -{ - mdContext->i[0] = mdContext->i[1] = (u32_t)0; - - /* Load magic initialization constants. */ - mdContext->buf[0] = (u32_t)0x67452301UL; - mdContext->buf[1] = (u32_t)0xefcdab89UL; - mdContext->buf[2] = (u32_t)0x98badcfeUL; - mdContext->buf[3] = (u32_t)0x10325476UL; -} - -/* The routine MD5Update updates the message-digest context to - account for the presence of each of the characters inBuf[0..inLen-1] - in the message whose digest is being computed. - */ -void -MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen) -{ - u32_t in[16]; - int mdi; - unsigned int i, ii; - -#if 0 - ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf); - ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf); -#endif - - /* compute number of bytes mod 64 */ - mdi = (int)((mdContext->i[0] >> 3) & 0x3F); - - /* update number of bits */ - if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) { - mdContext->i[1]++; - } - mdContext->i[0] += ((u32_t)inLen << 3); - mdContext->i[1] += ((u32_t)inLen >> 29); - - while (inLen--) { - /* add new character to buffer, increment mdi */ - mdContext->in[mdi++] = *inBuf++; - - /* transform if necessary */ - if (mdi == 0x40) { - for (i = 0, ii = 0; i < 16; i++, ii += 4) { - in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | - (((u32_t)mdContext->in[ii+2]) << 16) | - (((u32_t)mdContext->in[ii+1]) << 8) | - ((u32_t)mdContext->in[ii]); - } - Transform (mdContext->buf, in); - mdi = 0; - } - } -} - -/* The routine MD5Final terminates the message-digest computation and - ends with the desired message digest in mdContext->digest[0...15]. - */ -void -MD5Final (unsigned char hash[], MD5_CTX *mdContext) -{ - u32_t in[16]; - int mdi; - unsigned int i, ii; - unsigned int padLen; - - /* save number of bits */ - in[14] = mdContext->i[0]; - in[15] = mdContext->i[1]; - - /* compute number of bytes mod 64 */ - mdi = (int)((mdContext->i[0] >> 3) & 0x3F); - - /* pad out to 56 mod 64 */ - padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi); - MD5Update (mdContext, PADDING, padLen); - - /* append length in bits and transform */ - for (i = 0, ii = 0; i < 14; i++, ii += 4) { - in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | - (((u32_t)mdContext->in[ii+2]) << 16) | - (((u32_t)mdContext->in[ii+1]) << 8) | - ((u32_t)mdContext->in[ii]); - } - Transform (mdContext->buf, in); - - /* store buffer in digest */ - for (i = 0, ii = 0; i < 4; i++, ii += 4) { - mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF); - mdContext->digest[ii+1] = - (unsigned char)((mdContext->buf[i] >> 8) & 0xFF); - mdContext->digest[ii+2] = - (unsigned char)((mdContext->buf[i] >> 16) & 0xFF); - mdContext->digest[ii+3] = - (unsigned char)((mdContext->buf[i] >> 24) & 0xFF); - } - SMEMCPY(hash, mdContext->digest, 16); -} - -/* Basic MD5 step. Transforms buf based on in. - */ -static void -Transform (u32_t *buf, u32_t *in) -{ - u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3]; - - /* Round 1 */ -#define S11 7 -#define S12 12 -#define S13 17 -#define S14 22 - FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */ - FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */ - FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */ - FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */ - FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */ - FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */ - FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */ - FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */ - FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */ - FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */ - FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */ - FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */ - FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */ - FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */ - FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */ - FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */ - - /* Round 2 */ -#define S21 5 -#define S22 9 -#define S23 14 -#define S24 20 - GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */ - GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */ - GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */ - GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */ - GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */ - GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */ - GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */ - GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */ - GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */ - GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */ - GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */ - GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */ - GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */ - GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */ - GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */ - GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */ - - /* Round 3 */ -#define S31 4 -#define S32 11 -#define S33 16 -#define S34 23 - HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */ - HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */ - HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */ - HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */ - HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */ - HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */ - HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */ - HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */ - HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */ - HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */ - HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */ - HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */ - HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */ - HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */ - HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */ - HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */ - - /* Round 4 */ -#define S41 6 -#define S42 10 -#define S43 15 -#define S44 21 - II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */ - II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */ - II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */ - II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */ - II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */ - II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */ - II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */ - II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */ - II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */ - II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */ - II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */ - II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */ - II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */ - II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */ - II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */ - II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */ - - buf[0] += a; - buf[1] += b; - buf[2] += c; - buf[3] += d; -} - -#endif /* CHAP_SUPPORT || MD5_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/md5.h b/components/net/lwip-1.3.2/src/netif/ppp/md5.h deleted file mode 100644 index e129533f38..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/md5.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - *********************************************************************** - ** md5.h -- header file for implementation of MD5 ** - ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** - ** Created: 2/17/90 RLR ** - ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version ** - ** Revised (for MD5): RLR 4/27/91 ** - ** -- G modified to have y&~z instead of y&z ** - ** -- FF, GG, HH modified to add in last register done ** - ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 ** - ** -- distinct additive constant for each step ** - ** -- round 4 added, working mod 7 ** - *********************************************************************** - */ - -/* - *********************************************************************** - ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** - ** ** - ** License to copy and use this software is granted provided that ** - ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** - ** Digest Algorithm" in all material mentioning or referencing this ** - ** software or this function. ** - ** ** - ** License is also granted to make and use derivative works ** - ** provided that such works are identified as "derived from the RSA ** - ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** - ** material mentioning or referencing the derived work. ** - ** ** - ** RSA Data Security, Inc. makes no representations concerning ** - ** either the merchantability of this software or the suitability ** - ** of this software for any particular purpose. It is provided "as ** - ** is" without express or implied warranty of any kind. ** - ** ** - ** These notices must be retained in any copies of any part of this ** - ** documentation and/or software. ** - *********************************************************************** - */ - -#ifndef MD5_H -#define MD5_H - -/* Data structure for MD5 (Message-Digest) computation */ -typedef struct { - u32_t i[2]; /* number of _bits_ handled mod 2^64 */ - u32_t buf[4]; /* scratch buffer */ - unsigned char in[64]; /* input buffer */ - unsigned char digest[16]; /* actual digest after MD5Final call */ -} MD5_CTX; - -void MD5Init ( MD5_CTX *mdContext); -void MD5Update( MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen); -void MD5Final ( unsigned char hash[], MD5_CTX *mdContext); - -#endif /* MD5_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/pap.c b/components/net/lwip-1.3.2/src/netif/ppp/pap.c deleted file mode 100644 index e8c45dff9c..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/pap.c +++ /dev/null @@ -1,622 +0,0 @@ -/***************************************************************************** -* pap.c - Network Password Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-12 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ -/* - * upap.c - User/Password Authentication Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "auth.h" -#include "pap.h" - -#include - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Protocol entry points. - */ -static void upap_init (int); -static void upap_lowerup (int); -static void upap_lowerdown (int); -static void upap_input (int, u_char *, int); -static void upap_protrej (int); - -static void upap_timeout (void *); -static void upap_reqtimeout(void *); -static void upap_rauthreq (upap_state *, u_char *, int, int); -static void upap_rauthack (upap_state *, u_char *, int, int); -static void upap_rauthnak (upap_state *, u_char *, int, int); -static void upap_sauthreq (upap_state *); -static void upap_sresp (upap_state *, u_char, u_char, char *, int); - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -struct protent pap_protent = { - PPP_PAP, - upap_init, - upap_input, - upap_protrej, - upap_lowerup, - upap_lowerdown, - NULL, - NULL, -#if 0 - upap_printpkt, - NULL, -#endif - 1, - "PAP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - -upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */ - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Set the default login name and password for the pap sessions - */ -void -upap_setloginpasswd(int unit, const char *luser, const char *lpassword) -{ - upap_state *u = &upap[unit]; - - /* Save the username and password we're given */ - u->us_user = luser; - u->us_userlen = strlen(luser); - u->us_passwd = lpassword; - u->us_passwdlen = strlen(lpassword); -} - - -/* - * upap_authwithpeer - Authenticate us with our peer (start client). - * - * Set new state and send authenticate's. - */ -void -upap_authwithpeer(int unit, char *user, char *password) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n", - unit, user, password, u->us_clientstate)); - - upap_setloginpasswd(unit, user, password); - - u->us_transmits = 0; - - /* Lower layer up yet? */ - if (u->us_clientstate == UPAPCS_INITIAL || - u->us_clientstate == UPAPCS_PENDING) { - u->us_clientstate = UPAPCS_PENDING; - return; - } - - upap_sauthreq(u); /* Start protocol */ -} - - -/* - * upap_authpeer - Authenticate our peer (start server). - * - * Set new state. - */ -void -upap_authpeer(int unit) -{ - upap_state *u = &upap[unit]; - - /* Lower layer up yet? */ - if (u->us_serverstate == UPAPSS_INITIAL || - u->us_serverstate == UPAPSS_PENDING) { - u->us_serverstate = UPAPSS_PENDING; - return; - } - - u->us_serverstate = UPAPSS_LISTEN; - if (u->us_reqtimeout > 0) { - TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); - } -} - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * upap_init - Initialize a UPAP unit. - */ -static void -upap_init(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit)); - u->us_unit = unit; - u->us_user = NULL; - u->us_userlen = 0; - u->us_passwd = NULL; - u->us_passwdlen = 0; - u->us_clientstate = UPAPCS_INITIAL; - u->us_serverstate = UPAPSS_INITIAL; - u->us_id = 0; - u->us_timeouttime = UPAP_DEFTIMEOUT; - u->us_maxtransmits = 10; - u->us_reqtimeout = UPAP_DEFREQTIME; -} - -/* - * upap_timeout - Retransmission timer for sending auth-reqs expired. - */ -static void -upap_timeout(void *arg) -{ - upap_state *u = (upap_state *) arg; - - UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", - u->us_unit, u->us_timeouttime, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) { - return; - } - - if (u->us_transmits >= u->us_maxtransmits) { - /* give up in disgust */ - UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n")); - u->us_clientstate = UPAPCS_BADAUTH; - auth_withpeer_fail(u->us_unit, PPP_PAP); - return; - } - - upap_sauthreq(u); /* Send Authenticate-Request */ -} - - -/* - * upap_reqtimeout - Give up waiting for the peer to send an auth-req. - */ -static void -upap_reqtimeout(void *arg) -{ - upap_state *u = (upap_state *) arg; - - if (u->us_serverstate != UPAPSS_LISTEN) { - return; /* huh?? */ - } - - auth_peer_fail(u->us_unit, PPP_PAP); - u->us_serverstate = UPAPSS_BADAUTH; -} - - -/* - * upap_lowerup - The lower layer is up. - * - * Start authenticating if pending. - */ -static void -upap_lowerup(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate)); - - if (u->us_clientstate == UPAPCS_INITIAL) { - u->us_clientstate = UPAPCS_CLOSED; - } else if (u->us_clientstate == UPAPCS_PENDING) { - upap_sauthreq(u); /* send an auth-request */ - } - - if (u->us_serverstate == UPAPSS_INITIAL) { - u->us_serverstate = UPAPSS_CLOSED; - } else if (u->us_serverstate == UPAPSS_PENDING) { - u->us_serverstate = UPAPSS_LISTEN; - if (u->us_reqtimeout > 0) { - TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); - } - } -} - - -/* - * upap_lowerdown - The lower layer is down. - * - * Cancel all timeouts. - */ -static void -upap_lowerdown(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate)); - - if (u->us_clientstate == UPAPCS_AUTHREQ) { /* Timeout pending? */ - UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ - } - if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) { - UNTIMEOUT(upap_reqtimeout, u); - } - - u->us_clientstate = UPAPCS_INITIAL; - u->us_serverstate = UPAPSS_INITIAL; -} - - -/* - * upap_protrej - Peer doesn't speak this protocol. - * - * This shouldn't happen. In any case, pretend lower layer went down. - */ -static void -upap_protrej(int unit) -{ - upap_state *u = &upap[unit]; - - if (u->us_clientstate == UPAPCS_AUTHREQ) { - UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n")); - auth_withpeer_fail(unit, PPP_PAP); - } - if (u->us_serverstate == UPAPSS_LISTEN) { - UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n")); - auth_peer_fail(unit, PPP_PAP); - } - upap_lowerdown(unit); -} - - -/* - * upap_input - Input UPAP packet. - */ -static void -upap_input(int unit, u_char *inpacket, int l) -{ - upap_state *u = &upap[unit]; - u_char *inp; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - inp = inpacket; - if (l < UPAP_HEADERLEN) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < UPAP_HEADERLEN) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n")); - return; - } - if (len > l) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n")); - return; - } - len -= UPAP_HEADERLEN; - - /* - * Action depends on code. - */ - switch (code) { - case UPAP_AUTHREQ: - upap_rauthreq(u, inp, id, len); - break; - - case UPAP_AUTHACK: - upap_rauthack(u, inp, id, len); - break; - - case UPAP_AUTHNAK: - upap_rauthnak(u, inp, id, len); - break; - - default: /* XXX Need code reject */ - break; - } -} - - -/* - * upap_rauth - Receive Authenticate. - */ -static void -upap_rauthreq(upap_state *u, u_char *inp, int id, int len) -{ - u_char ruserlen, rpasswdlen; - char *ruser, *rpasswd; - int retcode; - char *msg; - int msglen; - - UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id)); - - if (u->us_serverstate < UPAPSS_LISTEN) { - return; - } - - /* - * If we receive a duplicate authenticate-request, we are - * supposed to return the same status as for the first request. - */ - if (u->us_serverstate == UPAPSS_OPEN) { - upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ - return; - } - if (u->us_serverstate == UPAPSS_BADAUTH) { - upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ - return; - } - - /* - * Parse user/passwd. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - GETCHAR(ruserlen, inp); - len -= sizeof (u_char) + ruserlen + sizeof (u_char); - if (len < 0) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - ruser = (char *) inp; - INCPTR(ruserlen, inp); - GETCHAR(rpasswdlen, inp); - if (len < rpasswdlen) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - rpasswd = (char *) inp; - - /* - * Check the username and password given. - */ - retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen); - BZERO(rpasswd, rpasswdlen); - - upap_sresp(u, retcode, id, msg, msglen); - - if (retcode == UPAP_AUTHACK) { - u->us_serverstate = UPAPSS_OPEN; - auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen); - } else { - u->us_serverstate = UPAPSS_BADAUTH; - auth_peer_fail(u->us_unit, PPP_PAP); - } - - if (u->us_reqtimeout > 0) { - UNTIMEOUT(upap_reqtimeout, u); - } -} - - -/* - * upap_rauthack - Receive Authenticate-Ack. - */ -static void -upap_rauthack(upap_state *u, u_char *inp, int id, int len) -{ - u_char msglen; - char *msg; - - LWIP_UNUSED_ARG(id); - - UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */ - return; - } - - /* - * Parse message. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); - return; - } - GETCHAR(msglen, inp); - len -= sizeof (u_char); - if (len < msglen) { - UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); - return; - } - msg = (char *) inp; - PRINTMSG(msg, msglen); - - UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ - u->us_clientstate = UPAPCS_OPEN; - - auth_withpeer_success(u->us_unit, PPP_PAP); -} - - -/* - * upap_rauthnak - Receive Authenticate-Nakk. - */ -static void -upap_rauthnak(upap_state *u, u_char *inp, int id, int len) -{ - u_char msglen; - char *msg; - - LWIP_UNUSED_ARG(id); - - UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */ - return; - } - - /* - * Parse message. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); - } else { - GETCHAR(msglen, inp); - if(msglen > 0) { - len -= sizeof (u_char); - if (len < msglen) { - UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); - return; - } - msg = (char *) inp; - PRINTMSG(msg, msglen); - } - } - - u->us_clientstate = UPAPCS_BADAUTH; - - UPAPDEBUG((LOG_ERR, "PAP authentication failed\n")); - auth_withpeer_fail(u->us_unit, PPP_PAP); -} - - -/* - * upap_sauthreq - Send an Authenticate-Request. - */ -static void -upap_sauthreq(upap_state *u) -{ - u_char *outp; - int outlen; - - outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) - + u->us_userlen + u->us_passwdlen; - outp = outpacket_buf[u->us_unit]; - - MAKEHEADER(outp, PPP_PAP); - - PUTCHAR(UPAP_AUTHREQ, outp); - PUTCHAR(++u->us_id, outp); - PUTSHORT(outlen, outp); - PUTCHAR(u->us_userlen, outp); - BCOPY(u->us_user, outp, u->us_userlen); - INCPTR(u->us_userlen, outp); - PUTCHAR(u->us_passwdlen, outp); - BCOPY(u->us_passwd, outp, u->us_passwdlen); - - pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); - - UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id)); - - TIMEOUT(upap_timeout, u, u->us_timeouttime); - ++u->us_transmits; - u->us_clientstate = UPAPCS_AUTHREQ; -} - - -/* - * upap_sresp - Send a response (ack or nak). - */ -static void -upap_sresp(upap_state *u, u_char code, u_char id, char *msg, int msglen) -{ - u_char *outp; - int outlen; - - outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; - outp = outpacket_buf[u->us_unit]; - MAKEHEADER(outp, PPP_PAP); - - PUTCHAR(code, outp); - PUTCHAR(id, outp); - PUTSHORT(outlen, outp); - PUTCHAR(msglen, outp); - BCOPY(msg, outp, msglen); - pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); - - UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", code, id, u->us_clientstate)); -} - -#if 0 -/* - * upap_printpkt - print the contents of a PAP packet. - */ -static int upap_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - LWIP_UNUSED_ARG(p); - LWIP_UNUSED_ARG(plen); - LWIP_UNUSED_ARG(printer); - LWIP_UNUSED_ARG(arg); - return 0; -} -#endif /* 0 */ - -#endif /* PAP_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/pap.h b/components/net/lwip-1.3.2/src/netif/ppp/pap.h deleted file mode 100644 index 0a09fc841b..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/pap.h +++ /dev/null @@ -1,131 +0,0 @@ -/***************************************************************************** -* pap.h - PPP Password Authentication Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * upap.h - User/Password Authentication Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef PAP_H -#define PAP_H - -#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Packet header = Code, id, length. - */ -#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) - - -/* - * UPAP codes. - */ -#define UPAP_AUTHREQ 1 /* Authenticate-Request */ -#define UPAP_AUTHACK 2 /* Authenticate-Ack */ -#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ - -/* - * Client states. - */ -#define UPAPCS_INITIAL 0 /* Connection down */ -#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ -#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ -#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ -#define UPAPCS_OPEN 4 /* We've received an Ack */ -#define UPAPCS_BADAUTH 5 /* We've received a Nak */ - -/* - * Server states. - */ -#define UPAPSS_INITIAL 0 /* Connection down */ -#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ -#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ -#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ -#define UPAPSS_OPEN 4 /* We've sent an Ack */ -#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * Each interface is described by upap structure. - */ -typedef struct upap_state { - int us_unit; /* Interface unit number */ - const char *us_user; /* User */ - int us_userlen; /* User length */ - const char *us_passwd; /* Password */ - int us_passwdlen; /* Password length */ - int us_clientstate; /* Client state */ - int us_serverstate; /* Server state */ - u_char us_id; /* Current id */ - int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */ - int us_transmits; /* Number of auth-reqs sent */ - int us_maxtransmits; /* Maximum number of auth-reqs to send */ - int us_reqtimeout; /* Time to wait for auth-req from peer */ -} upap_state; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -extern upap_state upap[]; - -void upap_setloginpasswd(int unit, const char *luser, const char *lpassword); -void upap_authwithpeer (int, char *, char *); -void upap_authpeer (int); - -extern struct protent pap_protent; - -#endif /* PAP_SUPPORT */ - -#endif /* PAP_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/ppp.c b/components/net/lwip-1.3.2/src/netif/ppp/ppp.c deleted file mode 100644 index 13fa5ed090..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/ppp.c +++ /dev/null @@ -1,1989 +0,0 @@ -/***************************************************************************** -* ppp.c - Network Point to Point Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ - -/* - * ppp_defs.h - PPP definitions. - * - * if_pppvar.h - private structures and declarations for PPP. - * - * Copyright (c) 1994 The Australian National University. - * All rights reserved. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, provided that the above copyright - * notice appears in all copies. This software is provided without any - * warranty, express or implied. The Australian National University - * makes no representations about the suitability of this software for - * any purpose. - * - * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY - * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES - * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, - * OR MODIFICATIONS. - */ - -/* - * if_ppp.h - Point-to-Point Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/ip.h" /* for ip_input() */ - -#include "ppp.h" -#include "pppdebug.h" - -#include "randm.h" -#include "fsm.h" -#if PAP_SUPPORT -#include "pap.h" -#endif /* PAP_SUPPORT */ -#if CHAP_SUPPORT -#include "chap.h" -#endif /* CHAP_SUPPORT */ -#include "ipcp.h" -#include "lcp.h" -#include "magic.h" -#include "auth.h" -#if VJ_SUPPORT -#include "vj.h" -#endif /* VJ_SUPPORT */ -#if PPPOE_SUPPORT -#include "netif/ppp_oe.h" -#endif /* PPPOE_SUPPORT */ - -#include - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -/* - * The basic PPP frame. - */ -#define PPP_ADDRESS(p) (((u_char *)(p))[0]) -#define PPP_CONTROL(p) (((u_char *)(p))[1]) -#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) - -/* PPP packet parser states. Current state indicates operation yet to be - * completed. */ -typedef enum { - PDIDLE = 0, /* Idle state - waiting. */ - PDSTART, /* Process start flag. */ - PDADDRESS, /* Process address field. */ - PDCONTROL, /* Process control field. */ - PDPROTOCOL1, /* Process protocol field 1. */ - PDPROTOCOL2, /* Process protocol field 2. */ - PDDATA /* Process data byte. */ -} PPPDevStates; - -#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07]) - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -/* - * PPP interface control block. - */ -typedef struct PPPControl_s { - char openFlag; /* True when in use. */ -#if PPPOE_SUPPORT - struct netif *ethif; - struct pppoe_softc *pppoe_sc; -#endif /* PPPOE_SUPPORT */ - int if_up; /* True when the interface is up. */ - int errCode; /* Code indicating why interface is down. */ -#if PPPOS_SUPPORT - sio_fd_t fd; /* File device ID of port. */ - int kill_link; /* Shut the link down. */ - int sig_hup; /* Carrier lost. */ - struct pbuf *inHead, *inTail; /* The input packet. */ - PPPDevStates inState; /* The input process state. */ - char inEscaped; /* Escape next character. */ - u16_t inProtocol; /* The input protocol code. */ - u16_t inFCS; /* Input Frame Check Sequence value. */ -#endif /* PPPOS_SUPPORT */ - int mtu; /* Peer's mru */ - int pcomp; /* Does peer accept protocol compression? */ - int accomp; /* Does peer accept addr/ctl compression? */ - u_long lastXMit; /* Time of last transmission. */ - ext_accm inACCM; /* Async-Ctl-Char-Map for input. */ - ext_accm outACCM; /* Async-Ctl-Char-Map for output. */ -#if PPPOS_SUPPORT && VJ_SUPPORT - int vjEnabled; /* Flag indicating VJ compression enabled. */ - struct vjcompress vjComp; /* Van Jacobson compression header. */ -#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ - - struct netif netif; - - struct ppp_addrs addrs; - - void (*linkStatusCB)(void *ctx, int errCode, void *arg); - void *linkStatusCtx; - -} PPPControl; - - -/* - * Ioctl definitions. - */ - -struct npioctl { - int protocol; /* PPP procotol, e.g. PPP_IP */ - enum NPmode mode; -}; - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -#if PPPOS_SUPPORT -static void pppMain(void *pd); -static void pppDrop(PPPControl *pc); -static void pppInProc(int pd, u_char *s, int l); -#endif /* PPPOS_SUPPORT */ - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -u_long subnetMask; - -static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */ - -/* - * PPP Data Link Layer "protocol" table. - * One entry per supported protocol. - * The last entry must be NULL. - */ -struct protent *ppp_protocols[] = { - &lcp_protent, -#if PAP_SUPPORT - &pap_protent, -#endif /* PAP_SUPPORT */ -#if CHAP_SUPPORT - &chap_protent, -#endif /* CHAP_SUPPORT */ -#if CBCP_SUPPORT - &cbcp_protent, -#endif /* CBCP_SUPPORT */ - &ipcp_protent, -#if CCP_SUPPORT - &ccp_protent, -#endif /* CCP_SUPPORT */ - NULL -}; - - -/* - * Buffers for outgoing packets. This must be accessed only from the appropriate - * PPP task so that it doesn't need to be protected to avoid collisions. - */ -u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ - -#if PPPOS_SUPPORT -/* - * FCS lookup table as calculated by genfcstab. - */ -static const u_short fcstab[256] = { - 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, - 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, - 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, - 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, - 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, - 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, - 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, - 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, - 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, - 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, - 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, - 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, - 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, - 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, - 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, - 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, - 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, - 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, - 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, - 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, - 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, - 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, - 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, - 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, - 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, - 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, - 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, - 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, - 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, - 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, - 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, - 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 -}; - -/* PPP's Asynchronous-Control-Character-Map. The mask array is used - * to select the specific bit for a character. */ -static u_char pppACCMMask[] = { - 0x01, - 0x02, - 0x04, - 0x08, - 0x10, - 0x20, - 0x40, - 0x80 -}; - - -void -pppMainWakeup(int pd) -{ - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd)); - sio_read_abort(pppControl[pd].fd); -} -#endif /* PPPOS_SUPPORT */ - -void -pppLinkTerminated(int pd) -{ - PPPDEBUG((LOG_DEBUG, "pppLinkTerminated: unit %d\n", pd)); - -#if PPPOE_SUPPORT - if(pppControl[pd].ethif) { - pppoe_disconnect(pppControl[pd].pppoe_sc); - } else -#endif /* PPPOE_SUPPORT */ - { -#if PPPOS_SUPPORT - pppMainWakeup(pd); -#endif /* PPPOS_SUPPORT */ - } -} - -void -pppLinkDown(int pd) -{ - PPPDEBUG((LOG_DEBUG, "pppLinkDown: unit %d\n", pd)); - -#if PPPOE_SUPPORT - if(pppControl[pd].ethif) { - pppoe_disconnect(pppControl[pd].pppoe_sc); - } else -#endif /* PPPOE_SUPPORT */ - { -#if PPPOS_SUPPORT - pppMainWakeup(pd); -#endif /* PPPOS_SUPPORT */ - } -} - -/* these callbacks are necessary because lcp_* functions - must be called in the same context as pppInput(), - namely the tcpip_thread(), essentially because - they manipulate timeouts which are thread-private -*/ - -static void -pppStartCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd)); - lcp_lowerup(pd); - lcp_open(pd); /* Start protocol */ -} - -static void -pppStopCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd)); - lcp_close(pd, "User request"); -} - -static void -pppHupCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd)); - lcp_lowerdown(pd); - link_terminated(pd); -} - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* Initialize the PPP subsystem. */ - -struct ppp_settings ppp_settings; - -void -pppInit(void) -{ - struct protent *protp; - int i, j; - - memset(&ppp_settings, 0, sizeof(ppp_settings)); - ppp_settings.usepeerdns = 1; - pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL); - - magicInit(); - - subnetMask = htonl(0xffffff00); - - for (i = 0; i < NUM_PPP; i++) { - pppControl[i].openFlag = 0; - - /* - * Initialize to the standard option set. - */ - for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) { - (*protp->init)(i); - } - } - -#if PPPOE_SUPPORT - pppoe_init(); -#endif /* PPPOE_SUPPORT */ -} - -void -pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd) -{ - switch(authType) { - case PPPAUTHTYPE_NONE: - default: -#ifdef LWIP_PPP_STRICT_PAP_REJECT - ppp_settings.refuse_pap = 1; -#else /* LWIP_PPP_STRICT_PAP_REJECT */ - /* some providers request pap and accept an empty login/pw */ - ppp_settings.refuse_pap = 0; -#endif /* LWIP_PPP_STRICT_PAP_REJECT */ - ppp_settings.refuse_chap = 1; - break; - - case PPPAUTHTYPE_ANY: - /* Warning: Using PPPAUTHTYPE_ANY might have security consequences. - * RFC 1994 says: - * - * In practice, within or associated with each PPP server, there is a - * database which associates "user" names with authentication - * information ("secrets"). It is not anticipated that a particular - * named user would be authenticated by multiple methods. This would - * make the user vulnerable to attacks which negotiate the least secure - * method from among a set (such as PAP rather than CHAP). If the same - * secret was used, PAP would reveal the secret to be used later with - * CHAP. - * - * Instead, for each user name there should be an indication of exactly - * one method used to authenticate that user name. If a user needs to - * make use of different authentication methods under different - * circumstances, then distinct user names SHOULD be employed, each of - * which identifies exactly one authentication method. - * - */ - ppp_settings.refuse_pap = 0; - ppp_settings.refuse_chap = 0; - break; - - case PPPAUTHTYPE_PAP: - ppp_settings.refuse_pap = 0; - ppp_settings.refuse_chap = 1; - break; - - case PPPAUTHTYPE_CHAP: - ppp_settings.refuse_pap = 1; - ppp_settings.refuse_chap = 0; - break; - } - - if(user) { - strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1); - ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0'; - } else { - ppp_settings.user[0] = '\0'; - } - - if(passwd) { - strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1); - ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0'; - } else { - ppp_settings.passwd[0] = '\0'; - } -} - -#if PPPOS_SUPPORT -/* Open a new PPP connection using the given I/O device. - * This initializes the PPP control block but does not - * attempt to negotiate the LCP session. If this port - * connects to a modem, the modem connection must be - * established before calling this. - * Return a new PPP connection descriptor on success or - * an error code (negative) on failure. */ -int -pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) -{ - PPPControl *pc; - int pd; - - /* Find a free PPP session descriptor. Critical region? */ - for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); - - if (pd >= NUM_PPP) { - pd = PPPERR_OPEN; - } else { - pppControl[pd].openFlag = !0; - } - - /* Launch a deamon thread. */ - if (pd >= 0) { - pppControl[pd].openFlag = 1; - - lcp_init(pd); - pc = &pppControl[pd]; - pc->fd = fd; -#if PPPOE_SUPPORT - pc->ethif= NULL; -#endif /* PPPOE_SUPPORT */ - pc->kill_link = 0; - pc->sig_hup = 0; - pc->if_up = 0; - pc->errCode = 0; - pc->inState = PDIDLE; - pc->inHead = NULL; - pc->inTail = NULL; - pc->inEscaped = 0; - pc->lastXMit = 0; - -#if VJ_SUPPORT - pc->vjEnabled = 0; - vj_compress_init(&pc->vjComp); -#endif /* VJ_SUPPORT */ - - /* - * Default the in and out accm so that escape and flag characters - * are always escaped. - */ - memset(pc->inACCM, 0, sizeof(ext_accm)); - pc->inACCM[15] = 0x60; - memset(pc->outACCM, 0, sizeof(ext_accm)); - pc->outACCM[15] = 0x60; - - pc->linkStatusCB = linkStatusCB; - pc->linkStatusCtx = linkStatusCtx; - - sys_thread_new(PPP_THREAD_NAME, pppMain, (void*)pd, PPP_THREAD_STACKSIZE, PPP_THREAD_PRIO); - if(!linkStatusCB) { - while(pd >= 0 && !pc->if_up) { - sys_msleep(500); - if (lcp_phase[pd] == PHASE_DEAD) { - pppClose(pd); - if (pc->errCode) { - pd = pc->errCode; - } else { - pd = PPPERR_CONNECT; - } - } - } - } - } - - return pd; -} -#endif /* PPPOS_SUPPORT */ - -#if PPPOE_SUPPORT -static void pppOverEthernetLinkStatusCB(int pd, int up); - -void -pppOverEthernetClose(int pd) -{ - PPPControl* pc = &pppControl[pd]; - - /* *TJL* There's no lcp_deinit */ - lcp_close(pd, NULL); - - pppoe_destroy(&pc->netif); -} - -int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) -{ - PPPControl *pc; - int pd; - - LWIP_UNUSED_ARG(service_name); - LWIP_UNUSED_ARG(concentrator_name); - - /* Find a free PPP session descriptor. Critical region? */ - for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); - if (pd >= NUM_PPP) { - pd = PPPERR_OPEN; - } else { - pppControl[pd].openFlag = !0; - } - - /* PPP session descriptor found, start PPPoE */ - if (pd >= 0) { - - pppControl[pd].openFlag = 1; - - lcp_init(pd); - - lcp_wantoptions[pd].mru = PPPOE_MAXMTU; - lcp_wantoptions[pd].neg_asyncmap = 0; - lcp_wantoptions[pd].neg_pcompression = 0; - lcp_wantoptions[pd].neg_accompression = 0; - - lcp_allowoptions[pd].mru = PPPOE_MAXMTU; - lcp_allowoptions[pd].neg_asyncmap = 0; - lcp_allowoptions[pd].neg_pcompression = 0; - lcp_allowoptions[pd].neg_accompression = 0; - - pc = &pppControl[pd]; - pc->if_up = 0; - pc->errCode = 0; - pc->lastXMit = 0; -#if PPPOS_SUPPORT - pc->kill_link = 0; - pc->sig_hup = 0; - pc->inState = PDIDLE; - pc->inHead = NULL; - pc->inTail = NULL; - pc->inEscaped = 0; -#if VJ_SUPPORT - pc->vjEnabled = 0; -#endif /* VJ_SUPPORT */ -#endif /* PPPOS_SUPPORT */ - pc->ethif= ethif; - - memset(pc->inACCM, 0, sizeof(ext_accm)); - memset(pc->outACCM, 0, sizeof(ext_accm)); - - pc->linkStatusCB = linkStatusCB; - pc->linkStatusCtx = linkStatusCtx; - - if(pppoe_create(ethif, pd, pppOverEthernetLinkStatusCB, &pc->pppoe_sc) != ERR_OK) { - pc->openFlag = 0; - return PPPERR_OPEN; - } - - pppoe_connect(pc->pppoe_sc); - - if(!linkStatusCB) { - while(pd >= 0 && !pc->if_up) { - sys_msleep(500); - if (lcp_phase[pd] == PHASE_DEAD) { - pppClose(pd); - if (pc->errCode) { - pd = pc->errCode; - } else { - pd = PPPERR_CONNECT; - } - } - } - } - } - - return pd; -} -#endif /* PPPOE_SUPPORT */ - - -/* Close a PPP connection and release the descriptor. - * Any outstanding packets in the queues are dropped. - * Return 0 on success, an error code on failure. */ -int -pppClose(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 0; - - /* Disconnect */ -#if PPPOE_SUPPORT - if(pc->ethif) { - PPPDEBUG((LOG_DEBUG, "pppClose: unit %d kill_link -> pppStopCB\n", pd)); - pc->errCode = PPPERR_USER; - /* This will leave us at PHASE_DEAD. */ - tcpip_callback(pppStopCB, (void*)pd); - } else -#endif /* PPPOE_SUPPORT */ - { -#if PPPOS_SUPPORT - pc->kill_link = !0; - pppMainWakeup(pd); -#endif /* PPPOS_SUPPORT */ - } - - if(!pc->linkStatusCB) { - while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) { - sys_msleep(500); - break; - } - } - - return st; -} - -/* This function is called when carrier is lost on the PPP channel. */ -void -pppSigHUP(int pd) -{ - PPPControl *pc = &pppControl[pd]; - -#if PPPOE_SUPPORT - if(pc->ethif) { - PPPDEBUG((LOG_DEBUG, "pppSigHUP: unit %d sig_hup -> pppHupCB\n", pd)); - tcpip_callback(pppHupCB, (void*)pd); - } else -#endif /* PPPOE_SUPPORT */ - { -#if PPPOS_SUPPORT - pc->sig_hup = 1; - pppMainWakeup(pd); -#endif /* PPPOS_SUPPORT */ - } -} - -#if PPPOS_SUPPORT -static void -nPut(PPPControl *pc, struct pbuf *nb) -{ - struct pbuf *b; - int c; - - for(b = nb; b != NULL; b = b->next) { - if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) { - PPPDEBUG((LOG_WARNING, - "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c)); - LINK_STATS_INC(link.err); - pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */ - break; - } - } - - pbuf_free(nb); - LINK_STATS_INC(link.xmit); -} - -/* - * pppAppend - append given character to end of given pbuf. If outACCM - * is not NULL and the character needs to be escaped, do so. - * If pbuf is full, append another. - * Return the current pbuf. - */ -static struct pbuf * -pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM) -{ - struct pbuf *tb = nb; - - /* Make sure there is room for the character and an escape code. - * Sure we don't quite fill the buffer if the character doesn't - * get escaped but is one character worth complicating this? */ - /* Note: We assume no packet header. */ - if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) { - tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (tb) { - nb->next = tb; - } else { - LINK_STATS_INC(link.memerr); - } - nb = tb; - } - - if (nb) { - if (outACCM && ESCAPE_P(*outACCM, c)) { - *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE; - *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS; - } else { - *((u_char*)nb->payload + nb->len++) = c; - } - } - - return tb; -} -#endif /* PPPOS_SUPPORT */ - -#if PPPOE_SUPPORT -static err_t -pppifOutputOverEthernet(int pd, struct pbuf *p) -{ - PPPControl *pc = &pppControl[pd]; - struct pbuf *pb; - u_short protocol = PPP_IP; - int i=0; - - pb = pbuf_alloc(PBUF_LINK, pppoe_hdrlen + sizeof(protocol), PBUF_RAM); - if(!pb) { - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.proterr); - return ERR_MEM; - } - - pbuf_header(pb, -pppoe_hdrlen); - - pc->lastXMit = sys_jiffies(); - - if (!pc->pcomp || protocol > 0xFF) { - *((u_char*)pb->payload + i++) = (protocol >> 8) & 0xFF; - } - *((u_char*)pb->payload + i) = protocol & 0xFF; - - pbuf_chain(pb, p); - - if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) { - LINK_STATS_INC(link.err); - return PPPERR_DEVICE; - } - - LINK_STATS_INC(link.xmit); - return ERR_OK; -} -#endif /* PPPOE_SUPPORT */ - -/* Send a packet on the given connection. */ -static err_t -pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr) -{ - int pd = (int)netif->state; - PPPControl *pc = &pppControl[pd]; -#if PPPOS_SUPPORT - u_short protocol = PPP_IP; - u_int fcsOut = PPP_INITFCS; - struct pbuf *headMB = NULL, *tailMB = NULL, *p; - u_char c; -#endif /* PPPOS_SUPPORT */ - - LWIP_UNUSED_ARG(ipaddr); - - /* Validate parameters. */ - /* We let any protocol value go through - it can't hurt us - * and the peer will just drop it if it's not accepting it. */ - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) { - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n", - pd, PPP_IP, pb)); - LINK_STATS_INC(link.opterr); - LINK_STATS_INC(link.drop); - return ERR_ARG; - } - - /* Check that the link is up. */ - if (lcp_phase[pd] == PHASE_DEAD) { - PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd)); - LINK_STATS_INC(link.rterr); - LINK_STATS_INC(link.drop); - return ERR_RTE; - } - -#if PPPOE_SUPPORT - if(pc->ethif) { - return pppifOutputOverEthernet(pd, pb); - } -#endif /* PPPOE_SUPPORT */ - -#if PPPOS_SUPPORT - /* Grab an output buffer. */ - headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (headMB == NULL) { - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd)); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - return ERR_MEM; - } - -#if VJ_SUPPORT - /* - * Attempt Van Jacobson header compression if VJ is configured and - * this is an IP packet. - */ - if (protocol == PPP_IP && pc->vjEnabled) { - switch (vj_compress_tcp(&pc->vjComp, pb)) { - case TYPE_IP: - /* No change... - protocol = PPP_IP_PROTOCOL; */ - break; - case TYPE_COMPRESSED_TCP: - protocol = PPP_VJC_COMP; - break; - case TYPE_UNCOMPRESSED_TCP: - protocol = PPP_VJC_UNCOMP; - break; - default: - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd)); - LINK_STATS_INC(link.proterr); - LINK_STATS_INC(link.drop); - pbuf_free(headMB); - return ERR_VAL; - } - } -#endif /* VJ_SUPPORT */ - - tailMB = headMB; - - /* Build the PPP header. */ - if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) { - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - } - - pc->lastXMit = sys_jiffies(); - if (!pc->accomp) { - fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS); - tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM); - fcsOut = PPP_FCS(fcsOut, PPP_UI); - tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM); - } - if (!pc->pcomp || protocol > 0xFF) { - c = (protocol >> 8) & 0xFF; - fcsOut = PPP_FCS(fcsOut, c); - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - c = protocol & 0xFF; - fcsOut = PPP_FCS(fcsOut, c); - tailMB = pppAppend(c, tailMB, &pc->outACCM); - - /* Load packet. */ - for(p = pb; p; p = p->next) { - int n; - u_char *sPtr; - - sPtr = (u_char*)p->payload; - n = p->len; - while (n-- > 0) { - c = *sPtr++; - - /* Update FCS before checking for special characters. */ - fcsOut = PPP_FCS(fcsOut, c); - - /* Copy to output buffer escaping special characters. */ - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - } - - /* Add FCS and trailing flag. */ - c = ~fcsOut & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - c = (~fcsOut >> 8) & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - - /* If we failed to complete the packet, throw it away. */ - if (!tailMB) { - PPPDEBUG((LOG_WARNING, - "pppifOutput[%d]: Alloc err - dropping proto=%d\n", - pd, protocol)); - pbuf_free(headMB); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - return ERR_MEM; - } - - /* Send it. */ - PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol)); - - nPut(pc, headMB); -#endif /* PPPOS_SUPPORT */ - - return ERR_OK; -} - -/* Get and set parameters for the given connection. - * Return 0 on success, an error code on failure. */ -int -pppIOCtl(int pd, int cmd, void *arg) -{ - PPPControl *pc = &pppControl[pd]; - int st = 0; - - if (pd < 0 || pd >= NUM_PPP) { - st = PPPERR_PARAM; - } else { - switch(cmd) { - case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ - if (arg) { - *(int *)arg = (int)(pc->if_up); - } else { - st = PPPERR_PARAM; - } - break; - case PPPCTLS_ERRCODE: /* Set the PPP error code. */ - if (arg) { - pc->errCode = *(int *)arg; - } else { - st = PPPERR_PARAM; - } - break; - case PPPCTLG_ERRCODE: /* Get the PPP error code. */ - if (arg) { - *(int *)arg = (int)(pc->errCode); - } else { - st = PPPERR_PARAM; - } - break; -#if PPPOS_SUPPORT - case PPPCTLG_FD: - if (arg) { - *(sio_fd_t *)arg = pc->fd; - } else { - st = PPPERR_PARAM; - } - break; -#endif /* PPPOS_SUPPORT */ - default: - st = PPPERR_PARAM; - break; - } - } - - return st; -} - -/* - * Return the Maximum Transmission Unit for the given PPP connection. - */ -u_int -pppMTU(int pd) -{ - PPPControl *pc = &pppControl[pd]; - u_int st; - - /* Validate parameters. */ - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - } else { - st = pc->mtu; - } - - return st; -} - -#if PPPOE_SUPPORT -int -pppWriteOverEthernet(int pd, const u_char *s, int n) -{ - PPPControl *pc = &pppControl[pd]; - struct pbuf *pb; - - /* skip address & flags */ - s += 2; - n -= 2; - - pb = pbuf_alloc(PBUF_LINK, pppoe_hdrlen + n, PBUF_RAM); - if(!pb) { - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.proterr); - return PPPERR_ALLOC; - } - - pbuf_header(pb, -pppoe_hdrlen); - - pc->lastXMit = sys_jiffies(); - - MEMCPY(pb->payload, s, n); - - if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) { - LINK_STATS_INC(link.err); - return PPPERR_DEVICE; - } - - LINK_STATS_INC(link.xmit); - return PPPERR_NONE; -} -#endif /* PPPOE_SUPPORT */ - -/* - * Write n characters to a ppp link. - * RETURN: >= 0 Number of characters written - * -1 Failed to write to device - */ -int -pppWrite(int pd, const u_char *s, int n) -{ - PPPControl *pc = &pppControl[pd]; -#if PPPOS_SUPPORT - u_char c; - u_int fcsOut; - struct pbuf *headMB, *tailMB; -#endif /* PPPOS_SUPPORT */ - -#if PPPOE_SUPPORT - if(pc->ethif) { - return pppWriteOverEthernet(pd, s, n); - } -#endif /* PPPOE_SUPPORT */ - -#if PPPOS_SUPPORT - headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (headMB == NULL) { - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.proterr); - return PPPERR_ALLOC; - } - - tailMB = headMB; - - /* If the link has been idle, we'll send a fresh flag character to - * flush any noise. */ - if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) { - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - } - pc->lastXMit = sys_jiffies(); - - fcsOut = PPP_INITFCS; - /* Load output buffer. */ - while (n-- > 0) { - c = *s++; - - /* Update FCS before checking for special characters. */ - fcsOut = PPP_FCS(fcsOut, c); - - /* Copy to output buffer escaping special characters. */ - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - - /* Add FCS and trailing flag. */ - c = ~fcsOut & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - c = (~fcsOut >> 8) & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - - /* If we failed to complete the packet, throw it away. - * Otherwise send it. */ - if (!tailMB) { - PPPDEBUG((LOG_WARNING, - "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len)); - /*"pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ - pbuf_free(headMB); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.proterr); - return PPPERR_ALLOC; - } - - PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len)); - /* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ - nPut(pc, headMB); -#endif /* PPPOS_SUPPORT */ - - return PPPERR_NONE; -} - -/* - * ppp_send_config - configure the transmit characteristics of - * the ppp interface. - */ -void -ppp_send_config( int unit, int mtu, u32_t asyncmap, int pcomp, int accomp) -{ - PPPControl *pc = &pppControl[unit]; - int i; - - pc->mtu = mtu; - pc->pcomp = pcomp; - pc->accomp = accomp; - - /* Load the ACCM bits for the 32 control codes. */ - for (i = 0; i < 32/8; i++) { - pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF); - } - PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n", - unit, - pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3])); -} - - -/* - * ppp_set_xaccm - set the extended transmit ACCM for the interface. - */ -void -ppp_set_xaccm(int unit, ext_accm *accm) -{ - SMEMCPY(pppControl[unit].outACCM, accm, sizeof(ext_accm)); - PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n", - unit, - pppControl[unit].outACCM[0], - pppControl[unit].outACCM[1], - pppControl[unit].outACCM[2], - pppControl[unit].outACCM[3])); -} - - -/* - * ppp_recv_config - configure the receive-side characteristics of - * the ppp interface. - */ -void -ppp_recv_config( int unit, int mru, u32_t asyncmap, int pcomp, int accomp) -{ - PPPControl *pc = &pppControl[unit]; - int i; - - LWIP_UNUSED_ARG(accomp); - LWIP_UNUSED_ARG(pcomp); - LWIP_UNUSED_ARG(mru); - - /* Load the ACCM bits for the 32 control codes. */ - for (i = 0; i < 32 / 8; i++) { - pc->inACCM[i] = (u_char)(asyncmap >> (i * 8)); - } - PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n", - unit, - pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3])); -} - -#if 0 -/* - * ccp_test - ask kernel whether a given compression method - * is acceptable for use. Returns 1 if the method and parameters - * are OK, 0 if the method is known but the parameters are not OK - * (e.g. code size should be reduced), or -1 if the method is unknown. - */ -int -ccp_test( int unit, int opt_len, int for_transmit, u_char *opt_ptr) -{ - return 0; /* XXX Currently no compression. */ -} - -/* - * ccp_flags_set - inform kernel about the current state of CCP. - */ -void -ccp_flags_set(int unit, int isopen, int isup) -{ - /* XXX */ -} - -/* - * ccp_fatal_error - returns 1 if decompression was disabled as a - * result of an error detected after decompression of a packet, - * 0 otherwise. This is necessary because of patent nonsense. - */ -int -ccp_fatal_error(int unit) -{ - /* XXX */ - return 0; -} -#endif - -/* - * get_idle_time - return how long the link has been idle. - */ -int -get_idle_time(int u, struct ppp_idle *ip) -{ - /* XXX */ - LWIP_UNUSED_ARG(u); - LWIP_UNUSED_ARG(ip); - - return 0; -} - - -/* - * Return user specified netmask, modified by any mask we might determine - * for address `addr' (in network byte order). - * Here we scan through the system's list of interfaces, looking for - * any non-point-to-point interfaces which might appear to be on the same - * network as `addr'. If we find any, we OR in their netmask to the - * user-specified netmask. - */ -u32_t -GetMask(u32_t addr) -{ - u32_t mask, nmask; - - htonl(addr); - if (IN_CLASSA(addr)) { /* determine network mask for address class */ - nmask = IN_CLASSA_NET; - } else if (IN_CLASSB(addr)) { - nmask = IN_CLASSB_NET; - } else { - nmask = IN_CLASSC_NET; - } - - /* class D nets are disallowed by bad_ip_adrs */ - mask = subnetMask | htonl(nmask); - - /* XXX - * Scan through the system's network interfaces. - * Get each netmask and OR them into our mask. - */ - - return mask; -} - -/* - * sifvjcomp - config tcp header compression - */ -int -sifvjcomp(int pd, int vjcomp, int cidcomp, int maxcid) -{ -#if PPPOS_SUPPORT && VJ_SUPPORT - PPPControl *pc = &pppControl[pd]; - - pc->vjEnabled = vjcomp; - pc->vjComp.compressSlot = cidcomp; - pc->vjComp.maxSlotIndex = maxcid; - PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n", - vjcomp, cidcomp, maxcid)); -#else /* PPPOS_SUPPORT && VJ_SUPPORT */ - LWIP_UNUSED_ARG(pd); - LWIP_UNUSED_ARG(vjcomp); - LWIP_UNUSED_ARG(cidcomp); - LWIP_UNUSED_ARG(maxcid); -#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ - - return 0; -} - -/* - * pppifNetifInit - netif init callback - */ -static err_t -pppifNetifInit(struct netif *netif) -{ - netif->name[0] = 'p'; - netif->name[1] = 'p'; - netif->output = pppifOutput; - netif->mtu = pppMTU((int)netif->state); - return ERR_OK; -} - - -/* - * sifup - Config the interface up and enable IP packets to pass. - */ -int -sifup(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_remove(&pc->netif); - if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) { - netif_set_up(&pc->netif); - pc->if_up = 1; - pc->errCode = PPPERR_NONE; - - PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) { - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs); - } - } else { - st = 0; - PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd)); - } - } - - return st; -} - -/* - * sifnpmode - Set the mode for handling packets for a given NP. - */ -int -sifnpmode(int u, int proto, enum NPmode mode) -{ - LWIP_UNUSED_ARG(u); - LWIP_UNUSED_ARG(proto); - LWIP_UNUSED_ARG(mode); - return 0; -} - -/* - * sifdown - Config the interface down and disable IP. - */ -int -sifdown(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd)); - } else { - pc->if_up = 0; - /* make sure the netif status callback is called */ - netif_set_down(&pc->netif); - netif_remove(&pc->netif); - PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) { - pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL); - } - } - return st; -} - -/** - * sifaddr - Config the interface IP addresses and netmask. - * @param pd Interface unit ??? - * @param o Our IP address ??? - * @param h His IP address ??? - * @param m IP subnet mask ??? - * @param ns1 Primary DNS - * @param ns2 Secondary DNS - */ -int -sifaddr( int pd, u32_t o, u32_t h, u32_t m, u32_t ns1, u32_t ns2) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - SMEMCPY(&pc->addrs.our_ipaddr, &o, sizeof(o)); - SMEMCPY(&pc->addrs.his_ipaddr, &h, sizeof(h)); - SMEMCPY(&pc->addrs.netmask, &m, sizeof(m)); - SMEMCPY(&pc->addrs.dns1, &ns1, sizeof(ns1)); - SMEMCPY(&pc->addrs.dns2, &ns2, sizeof(ns2)); - } - return st; -} - -/** - * cifaddr - Clear the interface IP addresses, and delete routes - * through the interface if possible. - * @param pd Interface unit ??? - * @param o Our IP address ??? - * @param h IP broadcast address ??? - */ -int -cifaddr( int pd, u32_t o, u32_t h) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - LWIP_UNUSED_ARG(o); - LWIP_UNUSED_ARG(h); - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0); - IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0); - IP4_ADDR(&pc->addrs.netmask, 255,255,255,0); - IP4_ADDR(&pc->addrs.dns1, 0,0,0,0); - IP4_ADDR(&pc->addrs.dns2, 0,0,0,0); - } - return st; -} - -/* - * sifdefaultroute - assign a default route through the address given. - */ -int -sifdefaultroute(int pd, u32_t l, u32_t g) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - LWIP_UNUSED_ARG(l); - LWIP_UNUSED_ARG(g); - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_set_default(&pc->netif); - } - - /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */ - - return st; -} - -/* - * cifdefaultroute - delete a default route through the address given. - */ -int -cifdefaultroute(int pd, u32_t l, u32_t g) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - LWIP_UNUSED_ARG(l); - LWIP_UNUSED_ARG(g); - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_set_default(NULL); - } - - return st; -} - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -#if PPPOS_SUPPORT -/* The main PPP process function. This implements the state machine according - * to section 4 of RFC 1661: The Point-To-Point Protocol. */ -static void -pppMain(void *arg) -{ - int pd = (int)arg; - struct pbuf *p; - PPPControl* pc; - int c; - - pc = &pppControl[pd]; - - p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM); - if (!p) { - LWIP_ASSERT("p != NULL", p); - pc->errCode = PPPERR_ALLOC; - goto out; - } - - /* - * Start the connection and handle incoming events (packet or timeout). - */ - PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd)); - tcpip_callback(pppStartCB, arg); - while (lcp_phase[pd] != PHASE_DEAD) { - if (pc->kill_link) { - PPPDEBUG((LOG_DEBUG, "pppMain: unit %d kill_link -> pppStopCB\n", pd)); - pc->errCode = PPPERR_USER; - /* This will leave us at PHASE_DEAD. */ - tcpip_callback(pppStopCB, arg); - pc->kill_link = 0; - } else if (pc->sig_hup) { - PPPDEBUG((LOG_DEBUG, "pppMain: unit %d sig_hup -> pppHupCB\n", pd)); - pc->sig_hup = 0; - tcpip_callback(pppHupCB, arg); - } else { - c = sio_read(pc->fd, p->payload, p->len); - if(c > 0) { - pppInProc(pd, p->payload, c); - } else { - /* nothing received, give other tasks a chance to run */ - sys_msleep(1); - } - } - } - PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd)); - pppDrop(pc); /* bug fix #17726 */ - pbuf_free(p); - -out: - PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) { - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); - } - - pc->openFlag = 0; -} -#endif /* PPPOS_SUPPORT */ - -#if PPPOE_SUPPORT - -void -pppOverEthernetInitFailed(void* arg) -{ - PPPControl* pc; - int pd = (int)arg; - - pppHupCB(arg); - pppStopCB(arg); - - pc = &pppControl[pd]; - pppoe_destroy(&pc->netif); - pc->openFlag = 0; - - if(pc->linkStatusCB) { - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); - } -} - -static void -pppOverEthernetLinkStatusCB(int pd, int up) -{ - if(up) { - PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd)); - tcpip_callback(pppStartCB, (void*)pd); - } else { - PPPControl* pc; - pc = &pppControl[pd]; - tcpip_callback(pppOverEthernetInitFailed, (void*)pd); - } -} -#endif /* PPPOE_SUPPORT */ - -struct pbuf * -pppSingleBuf(struct pbuf *p) -{ - struct pbuf *q, *b; - u_char *pl; - - if(p->tot_len == p->len) { - return p; - } - - q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if(!q) { - PPPDEBUG((LOG_ERR, - "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len)); - return p; /* live dangerously */ - } - - for(b = p, pl = q->payload; b != NULL; b = b->next) { - MEMCPY(pl, b->payload, b->len); - pl += b->len; - } - - pbuf_free(p); - - return q; -} - -struct pppInputHeader { - int unit; - u16_t proto; -}; - -/* - * Pass the processed input packet to the appropriate handler. - * This function and all handlers run in the context of the tcpip_thread - */ -static void -pppInput(void *arg) -{ - struct pbuf *nb = (struct pbuf *)arg; - u16_t protocol; - int pd; - - pd = ((struct pppInputHeader *)nb->payload)->unit; - protocol = ((struct pppInputHeader *)nb->payload)->proto; - - if(pbuf_header(nb, -(int)sizeof(struct pppInputHeader))) { - LWIP_ASSERT("pbuf_header failed\n", 0); - goto drop; - } - - LINK_STATS_INC(link.recv); - - /* - * Toss all non-LCP packets unless LCP is OPEN. - * Until we get past the authentication phase, toss all packets - * except LCP, LQR and authentication packets. - */ - if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) { - if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) || - (lcp_phase[pd] != PHASE_AUTHENTICATE)) { - PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd])); - goto drop; - } - } - - switch(protocol) { - case PPP_VJC_COMP: /* VJ compressed TCP */ -#if PPPOS_SUPPORT && VJ_SUPPORT - PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len)); - /* - * Clip off the VJ header and prepend the rebuilt TCP/IP header and - * pass the result to IP. - */ - if ((vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) && (pppControl[pd].netif.input)) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - /* Something's wrong so drop it. */ - PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd)); -#else /* PPPOS_SUPPORT && VJ_SUPPORT */ - /* No handler for this protocol so drop the packet. */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload)); -#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ - break; - - case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ -#if PPPOS_SUPPORT && VJ_SUPPORT - PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len)); - /* - * Process the TCP/IP header for VJ header compression and then pass - * the packet to IP. - */ - if ((vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) && pppControl[pd].netif.input) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - /* Something's wrong so drop it. */ - PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd)); -#else /* PPPOS_SUPPORT && VJ_SUPPORT */ - /* No handler for this protocol so drop the packet. */ - PPPDEBUG((LOG_INFO, - "pppInput[%d]: drop VJ UnComp in %d:.*H\n", - pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload)); -#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ - break; - - case PPP_IP: /* Internet Protocol */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len)); - if (pppControl[pd].netif.input) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - break; - - default: { - struct protent *protp; - int i; - - /* - * Upcall the proper protocol input routine. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (protp->protocol == protocol && protp->enabled_flag) { - PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len)); - nb = pppSingleBuf(nb); - (*protp->input)(pd, nb->payload, nb->len); - goto out; - } - } - - /* No handler for this protocol so reject the packet. */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len)); - if (pbuf_header(nb, sizeof(protocol))) { - LWIP_ASSERT("pbuf_header failed\n", 0); - goto drop; - } -#if BYTE_ORDER == LITTLE_ENDIAN - protocol = htons(protocol); - SMEMCPY(nb->payload, &protocol, sizeof(protocol)); -#endif /* BYTE_ORDER == LITTLE_ENDIAN */ - lcp_sprotrej(pd, nb->payload, nb->len); - } - break; - } - -drop: - LINK_STATS_INC(link.drop); - -out: - pbuf_free(nb); - return; -} - -#if PPPOS_SUPPORT -/* - * Drop the input packet. - */ -static void -pppDrop(PPPControl *pc) -{ - if (pc->inHead != NULL) { -#if 0 - PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload)); -#endif - PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len)); - if (pc->inTail && (pc->inTail != pc->inHead)) { - pbuf_free(pc->inTail); - } - pbuf_free(pc->inHead); - pc->inHead = NULL; - pc->inTail = NULL; - } -#if VJ_SUPPORT - vj_uncompress_err(&pc->vjComp); -#endif /* VJ_SUPPORT */ - - LINK_STATS_INC(link.drop); -} - -/** - * Process a received octet string. - */ -static void -pppInProc(int pd, u_char *s, int l) -{ - PPPControl *pc = &pppControl[pd]; - struct pbuf *nextNBuf; - u_char curChar; - - PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l)); - while (l-- > 0) { - curChar = *s++; - - /* Handle special characters. */ - if (ESCAPE_P(pc->inACCM, curChar)) { - /* Check for escape sequences. */ - /* XXX Note that this does not handle an escaped 0x5d character which - * would appear as an escape character. Since this is an ASCII ']' - * and there is no reason that I know of to escape it, I won't complicate - * the code to handle this case. GLL */ - if (curChar == PPP_ESCAPE) { - pc->inEscaped = 1; - /* Check for the flag character. */ - } else if (curChar == PPP_FLAG) { - /* If this is just an extra flag character, ignore it. */ - if (pc->inState <= PDADDRESS) { - /* ignore it */; - /* If we haven't received the packet header, drop what has come in. */ - } else if (pc->inState < PDDATA) { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Dropping incomplete packet %d\n", - pd, pc->inState)); - LINK_STATS_INC(link.lenerr); - pppDrop(pc); - /* If the fcs is invalid, drop the packet. */ - } else if (pc->inFCS != PPP_GOODFCS) { - PPPDEBUG((LOG_INFO, - "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", - pd, pc->inFCS, pc->inProtocol)); - LINK_STATS_INC(link.chkerr); - pppDrop(pc); - /* Otherwise it's a good packet so pass it on. */ - } else { - /* Trim off the checksum. */ - if(pc->inTail->len >= 2) { - pc->inTail->len -= 2; - - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - } else { - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - - pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2); - } - - /* Dispatch the packet thereby consuming it. */ - if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) { - PPPDEBUG((LOG_ERR, "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd)); - pbuf_free(pc->inHead); - LINK_STATS_INC(link.drop); - } - pc->inHead = NULL; - pc->inTail = NULL; - } - - /* Prepare for a new packet. */ - pc->inFCS = PPP_INITFCS; - pc->inState = PDADDRESS; - pc->inEscaped = 0; - /* Other characters are usually control characters that may have - * been inserted by the physical layer so here we just drop them. */ - } else { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar)); - } - /* Process other characters. */ - } else { - /* Unencode escaped characters. */ - if (pc->inEscaped) { - pc->inEscaped = 0; - curChar ^= PPP_TRANS; - } - - /* Process character relative to current state. */ - switch(pc->inState) { - case PDIDLE: /* Idle state - waiting. */ - /* Drop the character if it's not 0xff - * we would have processed a flag character above. */ - if (curChar != PPP_ALLSTATIONS) { - break; - } - - /* Fall through */ - case PDSTART: /* Process start flag. */ - /* Prepare for a new packet. */ - pc->inFCS = PPP_INITFCS; - - /* Fall through */ - case PDADDRESS: /* Process address field. */ - if (curChar == PPP_ALLSTATIONS) { - pc->inState = PDCONTROL; - break; - } - /* Else assume compressed address and control fields so - * fall through to get the protocol... */ - case PDCONTROL: /* Process control field. */ - /* If we don't get a valid control code, restart. */ - if (curChar == PPP_UI) { - pc->inState = PDPROTOCOL1; - break; - } -#if 0 - else { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Invalid control <%d>\n", pd, curChar)); - pc->inState = PDSTART; - } -#endif - case PDPROTOCOL1: /* Process protocol field 1. */ - /* If the lower bit is set, this is the end of the protocol - * field. */ - if (curChar & 1) { - pc->inProtocol = curChar; - pc->inState = PDDATA; - } else { - pc->inProtocol = (u_int)curChar << 8; - pc->inState = PDPROTOCOL2; - } - break; - case PDPROTOCOL2: /* Process protocol field 2. */ - pc->inProtocol |= curChar; - pc->inState = PDDATA; - break; - case PDDATA: /* Process data byte. */ - /* Make space to receive processed data. */ - if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) { - if(pc->inTail) { - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - } - /* If we haven't started a packet, we need a packet header. */ - nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (nextNBuf == NULL) { - /* No free buffers. Drop the input packet and let the - * higher layers deal with it. Continue processing - * the received pbuf chain in case a new packet starts. */ - PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd)); - LINK_STATS_INC(link.memerr); - pppDrop(pc); - pc->inState = PDSTART; /* Wait for flag sequence. */ - break; - } - if (pc->inHead == NULL) { - struct pppInputHeader *pih = nextNBuf->payload; - - pih->unit = pd; - pih->proto = pc->inProtocol; - - nextNBuf->len += sizeof(*pih); - - pc->inHead = nextNBuf; - } - pc->inTail = nextNBuf; - } - /* Load character into buffer. */ - ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar; - break; - } - - /* update the frame check sequence number. */ - pc->inFCS = PPP_FCS(pc->inFCS, curChar); - } - } - - avRandomize(); -} -#endif /* PPPOS_SUPPORT */ - -#if PPPOE_SUPPORT -void -pppInProcOverEthernet(int pd, struct pbuf *pb) -{ - struct pppInputHeader *pih; - u16_t inProtocol; - - if(pb->len < sizeof(inProtocol)) { - PPPDEBUG((LOG_ERR, "pppInProcOverEthernet: too small for protocol field\n")); - goto drop; - } - - inProtocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1]; - - /* make room for pppInputHeader - should not fail */ - if (pbuf_header(pb, sizeof(*pih) - sizeof(inProtocol)) != 0) { - PPPDEBUG((LOG_ERR, "pppInProcOverEthernet: could not allocate room for header\n")); - goto drop; - } - - pih = pb->payload; - - pih->unit = pd; - pih->proto = inProtocol; - - /* Dispatch the packet thereby consuming it. */ - if(tcpip_callback(pppInput, pb) != ERR_OK) { - PPPDEBUG((LOG_ERR, "pppInProcOverEthernet[%d]: tcpip_callback() failed, dropping packet\n", pd)); - goto drop; - } - - return; - -drop: - LINK_STATS_INC(link.drop); - pbuf_free(pb); - return; -} -#endif /* PPPOE_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/ppp.h b/components/net/lwip-1.3.2/src/netif/ppp/ppp.h deleted file mode 100644 index ebc733be65..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/ppp.h +++ /dev/null @@ -1,465 +0,0 @@ -/***************************************************************************** -* ppp.h - Network Point to Point Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ - -#ifndef PPP_H -#define PPP_H - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "lwip/def.h" -#include "lwip/sio.h" -#include "lwip/api.h" -#include "lwip/sockets.h" -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/tcpip.h" -#include "lwip/netif.h" - -/* - * pppd.h - PPP daemon global declarations. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - */ -/* - * ppp_defs.h - PPP definitions. - * - * Copyright (c) 1994 The Australian National University. - * All rights reserved. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, provided that the above copyright - * notice appears in all copies. This software is provided without any - * warranty, express or implied. The Australian National University - * makes no representations about the suitability of this software for - * any purpose. - * - * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY - * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES - * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, - * OR MODIFICATIONS. - */ - -#define TIMEOUT(f, a, t) sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a)) -#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) - - -#ifndef __u_char_defined - -/* Type definitions for BSD code. */ -typedef unsigned long u_long; -typedef unsigned int u_int; -typedef unsigned short u_short; -typedef unsigned char u_char; - -#endif - -/* - * Constants and structures defined by the internet system, - * Per RFC 790, September 1981, and numerous additions. - */ - -/* - * The basic PPP frame. - */ -#define PPP_HDRLEN 4 /* octets for standard ppp header */ -#define PPP_FCSLEN 2 /* octets for FCS */ - - -/* - * Significant octet values. - */ -#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ -#define PPP_UI 0x03 /* Unnumbered Information */ -#define PPP_FLAG 0x7e /* Flag Sequence */ -#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ -#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ - -/* - * Protocol field values. - */ -#define PPP_IP 0x21 /* Internet Protocol */ -#define PPP_AT 0x29 /* AppleTalk Protocol */ -#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ -#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ -#define PPP_COMP 0xfd /* compressed packet */ -#define PPP_IPCP 0x8021 /* IP Control Protocol */ -#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ -#define PPP_CCP 0x80fd /* Compression Control Protocol */ -#define PPP_LCP 0xc021 /* Link Control Protocol */ -#define PPP_PAP 0xc023 /* Password Authentication Protocol */ -#define PPP_LQR 0xc025 /* Link Quality Report protocol */ -#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ -#define PPP_CBCP 0xc029 /* Callback Control Protocol */ - -/* - * Values for FCS calculations. - */ -#define PPP_INITFCS 0xffff /* Initial FCS value */ -#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ -#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) - -/* - * Extended asyncmap - allows any character to be escaped. - */ -typedef u_char ext_accm[32]; - -/* - * What to do with network protocol (NP) packets. - */ -enum NPmode { - NPMODE_PASS, /* pass the packet through */ - NPMODE_DROP, /* silently drop the packet */ - NPMODE_ERROR, /* return an error */ - NPMODE_QUEUE /* save it up for later. */ -}; - -/* - * Inline versions of get/put char/short/long. - * Pointer is advanced; we assume that both arguments - * are lvalues and will already be in registers. - * cp MUST be u_char *. - */ -#define GETCHAR(c, cp) { \ - (c) = *(cp)++; \ -} -#define PUTCHAR(c, cp) { \ - *(cp)++ = (u_char) (c); \ -} - - -#define GETSHORT(s, cp) { \ - (s) = *(cp); (cp)++; (s) <<= 8; \ - (s) |= *(cp); (cp)++; \ -} -#define PUTSHORT(s, cp) { \ - *(cp)++ = (u_char) ((s) >> 8); \ - *(cp)++ = (u_char) (s & 0xff); \ -} - -#define GETLONG(l, cp) { \ - (l) = *(cp); (cp)++; (l) <<= 8; \ - (l) |= *(cp); (cp)++; (l) <<= 8; \ - (l) |= *(cp); (cp)++; (l) <<= 8; \ - (l) |= *(cp); (cp)++; \ -} -#define PUTLONG(l, cp) { \ - *(cp)++ = (u_char) ((l) >> 24); \ - *(cp)++ = (u_char) ((l) >> 16); \ - *(cp)++ = (u_char) ((l) >> 8); \ - *(cp)++ = (u_char) (l); \ -} - - -#define INCPTR(n, cp) ((cp) += (n)) -#define DECPTR(n, cp) ((cp) -= (n)) - -#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l)) -#define BCOPY(s, d, l) MEMCPY((d), (s), (l)) -#define BZERO(s, n) memset(s, 0, n) - -#if PPP_DEBUG -#define PRINTMSG(m, l) { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); } -#else /* PPP_DEBUG */ -#define PRINTMSG(m, l) -#endif /* PPP_DEBUG */ - -/* - * MAKEHEADER - Add PPP Header fields to a packet. - */ -#define MAKEHEADER(p, t) { \ - PUTCHAR(PPP_ALLSTATIONS, p); \ - PUTCHAR(PPP_UI, p); \ - PUTSHORT(t, p); } - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ - -/* Error codes. */ -#define PPPERR_NONE 0 /* No error. */ -#define PPPERR_PARAM -1 /* Invalid parameter. */ -#define PPPERR_OPEN -2 /* Unable to open PPP session. */ -#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */ -#define PPPERR_ALLOC -4 /* Unable to allocate resources. */ -#define PPPERR_USER -5 /* User interrupt. */ -#define PPPERR_CONNECT -6 /* Connection lost. */ -#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */ -#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */ - -/* - * PPP IOCTL commands. - */ -/* - * Get the up status - 0 for down, non-zero for up. The argument must - * point to an int. - */ -#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */ -#define PPPCTLS_ERRCODE 101 /* Set the error code */ -#define PPPCTLG_ERRCODE 102 /* Get the error code */ -#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */ - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * The following struct gives the addresses of procedures to call - * for a particular protocol. - */ -struct protent { - u_short protocol; /* PPP protocol number */ - /* Initialization procedure */ - void (*init) (int unit); - /* Process a received packet */ - void (*input) (int unit, u_char *pkt, int len); - /* Process a received protocol-reject */ - void (*protrej) (int unit); - /* Lower layer has come up */ - void (*lowerup) (int unit); - /* Lower layer has gone down */ - void (*lowerdown) (int unit); - /* Open the protocol */ - void (*open) (int unit); - /* Close the protocol */ - void (*close) (int unit, char *reason); -#if 0 - /* Print a packet in readable form */ - int (*printpkt) (u_char *pkt, int len, - void (*printer) (void *, char *, ...), - void *arg); - /* Process a received data packet */ - void (*datainput) (int unit, u_char *pkt, int len); -#endif - int enabled_flag; /* 0 iff protocol is disabled */ - char *name; /* Text name of protocol */ -#if 0 - /* Check requested options, assign defaults */ - void (*check_options) (u_long); - /* Configure interface for demand-dial */ - int (*demand_conf) (int unit); - /* Say whether to bring up link for this pkt */ - int (*active_pkt) (u_char *pkt, int len); -#endif -}; - -/* - * The following structure records the time in seconds since - * the last NP packet was sent or received. - */ -struct ppp_idle { - u_short xmit_idle; /* seconds since last NP packet sent */ - u_short recv_idle; /* seconds since last NP packet received */ -}; - -struct ppp_settings { - - u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */ - u_int auth_required : 1; /* Peer is required to authenticate */ - u_int explicit_remote : 1; /* remote_name specified with remotename opt */ - u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */ - u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */ - u_int usehostname : 1; /* Use hostname for our_name */ - u_int usepeerdns : 1; /* Ask peer for DNS adds */ - - u_short idle_time_limit; /* Shut down link if idle for this long */ - int maxconnect; /* Maximum connect time (seconds) */ - - char user [MAXNAMELEN + 1]; /* Username for PAP */ - char passwd [MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */ - char our_name [MAXNAMELEN + 1]; /* Our name for authentication purposes */ - char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ -}; - -struct ppp_addrs { - struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2; -}; - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -/* Buffers for outgoing packets. */ -extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; - -extern struct ppp_settings ppp_settings; - -extern struct protent *ppp_protocols[]; /* Table of pointers to supported protocols */ - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -/* Initialize the PPP subsystem. */ -void pppInit(void); - -/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. - * RFC 1994 says: - * - * In practice, within or associated with each PPP server, there is a - * database which associates "user" names with authentication - * information ("secrets"). It is not anticipated that a particular - * named user would be authenticated by multiple methods. This would - * make the user vulnerable to attacks which negotiate the least secure - * method from among a set (such as PAP rather than CHAP). If the same - * secret was used, PAP would reveal the secret to be used later with - * CHAP. - * - * Instead, for each user name there should be an indication of exactly - * one method used to authenticate that user name. If a user needs to - * make use of different authentication methods under different - * circumstances, then distinct user names SHOULD be employed, each of - * which identifies exactly one authentication method. - * - */ -enum pppAuthType { - PPPAUTHTYPE_NONE, - PPPAUTHTYPE_ANY, - PPPAUTHTYPE_PAP, - PPPAUTHTYPE_CHAP -}; - -void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd); - -/* - * Open a new PPP connection using the given serial I/O device. - * This initializes the PPP control block but does not - * attempt to negotiate the LCP session. - * Return a new PPP connection descriptor on success or - * an error code (negative) on failure. - */ -int pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); - -/* - * Open a new PPP Over Ethernet (PPPOE) connection. - */ -int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); - -/* for source code compatibility */ -#define pppOpen(fd,cb,ls) pppOverSerialOpen(fd,cb,ls) - -/* - * Close a PPP connection and release the descriptor. - * Any outstanding packets in the queues are dropped. - * Return 0 on success, an error code on failure. - */ -int pppClose(int pd); - -/* - * Indicate to the PPP process that the line has disconnected. - */ -void pppSigHUP(int pd); - -/* - * Get and set parameters for the given connection. - * Return 0 on success, an error code on failure. - */ -int pppIOCtl(int pd, int cmd, void *arg); - -/* - * Return the Maximum Transmission Unit for the given PPP connection. - */ -u_int pppMTU(int pd); - -/* - * Write n characters to a ppp link. - * RETURN: >= 0 Number of characters written, -1 Failed to write to device. - */ -int pppWrite(int pd, const u_char *s, int n); - -void pppInProcOverEthernet(int pd, struct pbuf *pb); - -struct pbuf *pppSingleBuf(struct pbuf *p); - -void pppLinkTerminated(int pd); - -void pppLinkDown(int pd); - -void pppMainWakeup(int pd); - -/* Configure i/f transmit parameters */ -void ppp_send_config (int, int, u32_t, int, int); -/* Set extended transmit ACCM */ -void ppp_set_xaccm (int, ext_accm *); -/* Configure i/f receive parameters */ -void ppp_recv_config (int, int, u32_t, int, int); -/* Find out how long link has been idle */ -int get_idle_time (int, struct ppp_idle *); - -/* Configure VJ TCP header compression */ -int sifvjcomp (int, int, int, int); -/* Configure i/f down (for IP) */ -int sifup (int); -/* Set mode for handling packets for proto */ -int sifnpmode (int u, int proto, enum NPmode mode); -/* Configure i/f down (for IP) */ -int sifdown (int); -/* Configure IP addresses for i/f */ -int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t); -/* Reset i/f IP addresses */ -int cifaddr (int, u32_t, u32_t); -/* Create default route through i/f */ -int sifdefaultroute (int, u32_t, u32_t); -/* Delete default route through i/f */ -int cifdefaultroute (int, u32_t, u32_t); - -/* Get appropriate netmask for address */ -u32_t GetMask (u32_t); - -#endif /* PPP_SUPPORT */ - -#endif /* PPP_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/randm.c b/components/net/lwip-1.3.2/src/netif/ppp/randm.c deleted file mode 100644 index 83c4174171..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/randm.c +++ /dev/null @@ -1,249 +0,0 @@ -/***************************************************************************** -* randm.c - Random number generator program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1998 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-06-03 Guy Lancaster , Global Election Systems Inc. -* Extracted from avos. -*****************************************************************************/ - -#include "lwip/opt.h" - -#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ - -#include "md5.h" -#include "randm.h" - -#include "ppp.h" -#include "pppdebug.h" - -#include - -#if MD5_SUPPORT /* this module depends on MD5 */ -#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */ - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static char randPool[RANDPOOLSZ]; /* Pool of randomness. */ -static long randCount = 0; /* Pseudo-random incrementer */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Initialize the random number generator. - * - * Since this is to be called on power up, we don't have much - * system randomess to work with. Here all we use is the - * real-time clock. We'll accumulate more randomness as soon - * as things start happening. - */ -void -avRandomInit() -{ - avChurnRand(NULL, 0); -} - -/* - * Churn the randomness pool on a random event. Call this early and often - * on random and semi-random system events to build randomness in time for - * usage. For randomly timed events, pass a null pointer and a zero length - * and this will use the system timer and other sources to add randomness. - * If new random data is available, pass a pointer to that and it will be - * included. - * - * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 - */ -void -avChurnRand(char *randData, u32_t randLen) -{ - MD5_CTX md5; - - /* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */ - MD5Init(&md5); - MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); - if (randData) { - MD5Update(&md5, (u_char *)randData, randLen); - } else { - struct { - /* INCLUDE fields for any system sources of randomness */ - char foobar; - } sysData; - - /* Load sysData fields here. */ - MD5Update(&md5, (u_char *)&sysData, sizeof(sysData)); - } - MD5Final((u_char *)randPool, &md5); -/* ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */ -} - -/* - * Use the random pool to generate random data. This degrades to pseudo - * random when used faster than randomness is supplied using churnRand(). - * Note: It's important that there be sufficient randomness in randPool - * before this is called for otherwise the range of the result may be - * narrow enough to make a search feasible. - * - * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 - * - * XXX Why does he not just call churnRand() for each block? Probably - * so that you don't ever publish the seed which could possibly help - * predict future values. - * XXX Why don't we preserve md5 between blocks and just update it with - * randCount each time? Probably there is a weakness but I wish that - * it was documented. - */ -void -avGenRand(char *buf, u32_t bufLen) -{ - MD5_CTX md5; - u_char tmp[16]; - u32_t n; - - while (bufLen > 0) { - n = LWIP_MIN(bufLen, RANDPOOLSZ); - MD5Init(&md5); - MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); - MD5Update(&md5, (u_char *)&randCount, sizeof(randCount)); - MD5Final(tmp, &md5); - randCount++; - MEMCPY(buf, tmp, n); - buf += n; - bufLen -= n; - } -} - -/* - * Return a new random number. - */ -u32_t -avRandom() -{ - u32_t newRand; - - avGenRand((char *)&newRand, sizeof(newRand)); - - return newRand; -} - -#else /* MD5_SUPPORT */ - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static int avRandomized = 0; /* Set when truely randomized. */ -static u32_t avRandomSeed = 0; /* Seed used for random number generation. */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Initialize the random number generator. - * - * Here we attempt to compute a random number seed but even if - * it isn't random, we'll randomize it later. - * - * The current method uses the fields from the real time clock, - * the idle process counter, the millisecond counter, and the - * hardware timer tick counter. When this is invoked - * in startup(), then the idle counter and timer values may - * repeat after each boot and the real time clock may not be - * operational. Thus we call it again on the first random - * event. - */ -void -avRandomInit() -{ -#if 0 - /* Get a pointer into the last 4 bytes of clockBuf. */ - u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]); - - /* - * Initialize our seed using the real-time clock, the idle - * counter, the millisecond timer, and the hardware timer - * tick counter. The real-time clock and the hardware - * tick counter are the best sources of randomness but - * since the tick counter is only 16 bit (and truncated - * at that), the idle counter and millisecond timer - * (which may be small values) are added to help - * randomize the lower 16 bits of the seed. - */ - readClk(); - avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr - + ppp_mtime() + ((u32_t)TM1 << 16) + TM1; -#else - avRandomSeed += sys_jiffies(); /* XXX */ -#endif - - /* Initialize the Borland random number generator. */ - srand((unsigned)avRandomSeed); -} - -/* - * Randomize our random seed value. Here we use the fact that - * this function is called at *truely random* times by the polling - * and network functions. Here we only get 16 bits of new random - * value but we use the previous value to randomize the other 16 - * bits. - */ -void -avRandomize(void) -{ - static u32_t last_jiffies; - - if (!avRandomized) { - avRandomized = !0; - avRandomInit(); - /* The initialization function also updates the seed. */ - } else { - /* avRandomSeed += (avRandomSeed << 16) + TM1; */ - avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */ - } - last_jiffies = sys_jiffies(); -} - -/* - * Return a new random number. - * Here we use the Borland rand() function to supply a pseudo random - * number which we make truely random by combining it with our own - * seed which is randomized by truely random events. - * Thus the numbers will be truely random unless there have been no - * operator or network events in which case it will be pseudo random - * seeded by the real time clock. - */ -u32_t -avRandom() -{ - return ((((u32_t)rand() << 16) + rand()) + avRandomSeed); -} - -#endif /* MD5_SUPPORT */ - -#endif /* PPP_SUPPORT */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/randm.h b/components/net/lwip-1.3.2/src/netif/ppp/randm.h deleted file mode 100644 index a0984b0202..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/randm.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************** -* randm.h - Random number generator header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-05-29 Guy Lancaster , Global Election Systems Inc. -* Extracted from avos. -*****************************************************************************/ - -#ifndef RANDM_H -#define RANDM_H - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -/* - * Initialize the random number generator. - */ -void avRandomInit(void); - -/* - * Churn the randomness pool on a random event. Call this early and often - * on random and semi-random system events to build randomness in time for - * usage. For randomly timed events, pass a null pointer and a zero length - * and this will use the system timer and other sources to add randomness. - * If new random data is available, pass a pointer to that and it will be - * included. - */ -void avChurnRand(char *randData, u32_t randLen); - -/* - * Randomize our random seed value. To be called for truely random events - * such as user operations and network traffic. - */ -#if MD5_SUPPORT -#define avRandomize() avChurnRand(NULL, 0) -#else /* MD5_SUPPORT */ -void avRandomize(void); -#endif /* MD5_SUPPORT */ - -/* - * Use the random pool to generate random data. This degrades to pseudo - * random when used faster than randomness is supplied using churnRand(). - * Thus it's important to make sure that the results of this are not - * published directly because one could predict the next result to at - * least some degree. Also, it's important to get a good seed before - * the first use. - */ -void avGenRand(char *buf, u32_t bufLen); - -/* - * Return a new random number. - */ -u32_t avRandom(void); - - -#endif /* RANDM_H */ diff --git a/components/net/lwip-1.3.2/src/netif/ppp/vjbsdhdr.h b/components/net/lwip-1.3.2/src/netif/ppp/vjbsdhdr.h deleted file mode 100644 index f46267614a..0000000000 --- a/components/net/lwip-1.3.2/src/netif/ppp/vjbsdhdr.h +++ /dev/null @@ -1,75 +0,0 @@ -#ifndef VJBSDHDR_H -#define VJBSDHDR_H - -#include "lwip/tcp.h" - -/* - * Structure of an internet header, naked of options. - * - * We declare ip_len and ip_off to be short, rather than u_short - * pragmatically since otherwise unsigned comparisons can result - * against negative integers quite easily, and fail in subtle ways. - */ -PACK_STRUCT_BEGIN -struct ip -{ -#if defined(NO_CHAR_BITFIELDS) - u_char ip_hl_v; /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */ -#else -#if BYTE_ORDER == LITTLE_ENDIAN - unsigned ip_hl:4, /* header length */ - ip_v :4; /* version */ -#elif BYTE_ORDER == BIG_ENDIAN - unsigned ip_v :4, /* version */ - ip_hl:4; /* header length */ -#else - COMPLAIN - NO BYTE ORDER SELECTED! -#endif -#endif - u_char ip_tos; /* type of service */ - u_short ip_len; /* total length */ - u_short ip_id; /* identification */ - u_short ip_off; /* fragment offset field */ -#define IP_DF 0x4000 /* dont fragment flag */ -#define IP_MF 0x2000 /* more fragments flag */ -#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ - u_char ip_ttl; /* time to live */ - u_char ip_p; /* protocol */ - u_short ip_sum; /* checksum */ - struct in_addr ip_src,ip_dst; /* source and dest address */ -}; -PACK_STRUCT_END - -typedef u32_t tcp_seq; - -/* - * TCP header. - * Per RFC 793, September, 1981. - */ -PACK_STRUCT_BEGIN -struct tcphdr -{ - u_short th_sport; /* source port */ - u_short th_dport; /* destination port */ - tcp_seq th_seq; /* sequence number */ - tcp_seq th_ack; /* acknowledgement number */ -#if defined(NO_CHAR_BITFIELDS) - u_char th_x2_off; -#else -#if BYTE_ORDER == LITTLE_ENDIAN - unsigned th_x2 :4, /* (unused) */ - th_off:4; /* data offset */ -#endif -#if BYTE_ORDER == BIG_ENDIAN - unsigned th_off:4, /* data offset */ - th_x2 :4; /* (unused) */ -#endif -#endif - u_char th_flags; - u_short th_win; /* window */ - u_short th_sum; /* checksum */ - u_short th_urp; /* urgent pointer */ -}; -PACK_STRUCT_END - -#endif /* VJBSDHDR_H */ diff --git a/components/net/lwip-1.3.2/src/netif/skeleton.c b/components/net/lwip-1.3.2/src/netif/skeleton.c deleted file mode 100644 index 52a2ba5a31..0000000000 --- a/components/net/lwip-1.3.2/src/netif/skeleton.c +++ /dev/null @@ -1,211 +0,0 @@ -#include -#include "skeleton.h" -#include - -#define MAX_ADDR_LEN 6 -struct rt_skeleton_eth -{ - /* inherit from ethernet device */ - struct eth_device parent; - - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ -}; -static struct rt_skeleton_eth _skeleton_device; - -void rt_skeleton_isr(int irqno) -{ - rt_uint32_t status; - - /* read status */ - - /* Received the coming packet */ - if (status) - { - /* disable receive interrupt */ - - /* a frame has been received */ - eth_device_ready(&(_skeleton_device.parent)); - } - - /* Transmit Interrupt check */ - if (status) - { - } -} - -static rt_err_t rt_skeleton_init(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_err_t rt_skeleton_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_skeleton_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_skeleton_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_size_t rt_skeleton_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_err_t rt_skeleton_control(rt_device_t dev, int cmd, void *args) -{ - struct rt_skeleton_eth *eth; - - eth = (struct rt_skeleton_eth*)dev; - RT_ASSERT(eth != RT_NULL); - - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, _skeleton_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -rt_err_t rt_skeleton_tx( rt_device_t dev, struct pbuf* p) -{ - { - /* q traverses through linked list of pbuf's - * This list MUST consist of a single packet ONLY */ - struct pbuf *q; - rt_uint16_t pbuf_index = 0; - rt_uint8_t word[2], word_index = 0; - - q = p; - /* Write data into hardware, two bytes at a time - * Handling pbuf's with odd number of bytes correctly - * No attempt to optimize for speed has been made */ - while (q) - { - if (pbuf_index < q->len) - { - word[word_index++] = ((u8_t*)q->payload)[pbuf_index++]; - if (word_index == 2) - { - /* write data to hardware */ - - word_index = 0; - } - } - else - { - q = q->next; - pbuf_index = 0; - } - } - /* One byte could still be unsent */ - if (word_index == 1) - { - /* write data to hardware */ - - } - } - - return RT_EOK; -} - -struct pbuf *rt_skeleton_rx(rt_device_t dev) -{ - struct pbuf* p; - rt_uint32_t rxbyte; - - /* init p pointer */ - p = RT_NULL; - rxbyte = 0; /* get eth status */ - if (rxbyte) /* there is data received */ - { - rt_uint16_t rx_len; - rt_uint16_t* data; - - /* get recieved packet length */ - rx_len = 0; - - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf* q; - rt_int32_t len; - - for (q = p; q != RT_NULL; q= q->next) - { - data = (rt_uint16_t*)q->payload; - len = q->len; - - while (len > 0) - { - *data = 0; /* read data from hardware */ - data ++; - len -= 2; - } - } - } - else - { - rt_uint16_t dummy; - rt_int32_t len; - - /* no pbuf, discard data from EMAC */ - data = &dummy; - len = rx_len; - while (len > 0) - { - *data = 0; /* read from hardware */ - len -= 2; - } - } - } - else - { - /* restore receive interrupt */ - } - - return p; -} - -void rt_hw_skeleton_init() -{ - /* set default MAC address */ - _skeleton_device.dev_addr[0] = 0x00; - _skeleton_device.dev_addr[1] = 0x60; - _skeleton_device.dev_addr[2] = 0x6E; - _skeleton_device.dev_addr[3] = 0x11; - _skeleton_device.dev_addr[4] = 0x22; - _skeleton_device.dev_addr[5] = 0x33; - - /* set RT-Thread device interface */ - _skeleton_device.parent.parent.init = rt_skeleton_init; - _skeleton_device.parent.parent.open = rt_skeleton_open; - _skeleton_device.parent.parent.close = rt_skeleton_close; - _skeleton_device.parent.parent.read = rt_skeleton_read; - _skeleton_device.parent.parent.write = rt_skeleton_write; - _skeleton_device.parent.parent.control = rt_skeleton_control; - _skeleton_device.parent.parent.user_data = RT_NULL; - - /* set ethernet interface */ - _skeleton_device.parent.eth_rx = rt_skeleton_rx; - _skeleton_device.parent.eth_tx = rt_skeleton_tx; - - eth_device_init(&(_skeleton_device.parent), "e0"); -} diff --git a/components/net/lwip-1.3.2/src/netif/skeleton.h b/components/net/lwip-1.3.2/src/netif/skeleton.h deleted file mode 100644 index f8185d0da5..0000000000 --- a/components/net/lwip-1.3.2/src/netif/skeleton.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __SKELETON_H__ -#define __SKELETON_H__ - -void rt_hw_skeleton_init(void); - -#endif diff --git a/components/net/lwip-1.3.2/src/netif/slipif.c b/components/net/lwip-1.3.2/src/netif/slipif.c deleted file mode 100644 index 089d2d3eb8..0000000000 --- a/components/net/lwip-1.3.2/src/netif/slipif.c +++ /dev/null @@ -1,367 +0,0 @@ -/** - * @file - * SLIP Interface - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is built upon the file: src/arch/rtxc/netif/sioslip.c - * - * Author: Magnus Ivarsson - */ - -/* - * This is an arch independent SLIP netif. The specific serial hooks must be - * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send - */ - -#include "netif/slipif.h" -#include "lwip/opt.h" - -#if LWIP_HAVE_SLIPIF - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "lwip/sio.h" - -#define SLIP_BLOCK 1 -#define SLIP_DONTBLOCK 0 - -#define SLIP_END 0300 /* 0xC0 */ -#define SLIP_ESC 0333 /* 0xDB */ -#define SLIP_ESC_END 0334 /* 0xDC */ -#define SLIP_ESC_ESC 0335 /* 0xDD */ - -#define SLIP_MAX_SIZE 1500 - -enum slipif_recv_state { - SLIP_RECV_NORMAL, - SLIP_RECV_ESCAPE, -}; - -struct slipif_priv { - sio_fd_t sd; - /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */ - struct pbuf *p, *q; - enum slipif_recv_state state; - u16_t i, recved; -}; - -/** - * Send a pbuf doing the necessary SLIP encapsulation - * - * Uses the serial layer's sio_send() - * - * @param netif the lwip network interface structure for this slipif - * @param p the pbuf chaing packet to send - * @param ipaddr the ip address to send the packet to (not used for slipif) - * @return always returns ERR_OK since the serial layer does not provide return values - */ -err_t -slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) -{ - struct slipif_priv *priv; - struct pbuf *q; - u16_t i; - u8_t c; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - LWIP_ASSERT("p != NULL", (p != NULL)); - - LWIP_UNUSED_ARG(ipaddr); - - priv = netif->state; - - /* Send pbuf out on the serial I/O device. */ - sio_send(SLIP_END, priv->sd); - - for (q = p; q != NULL; q = q->next) { - for (i = 0; i < q->len; i++) { - c = ((u8_t *)q->payload)[i]; - switch (c) { - case SLIP_END: - sio_send(SLIP_ESC, priv->sd); - sio_send(SLIP_ESC_END, priv->sd); - break; - case SLIP_ESC: - sio_send(SLIP_ESC, priv->sd); - sio_send(SLIP_ESC_ESC, priv->sd); - break; - default: - sio_send(c, priv->sd); - break; - } - } - } - sio_send(SLIP_END, priv->sd); - return ERR_OK; -} - -/** - * Static function for easy use of blockig or non-blocking - * sio_read - * - * @param fd serial device handle - * @param data pointer to data buffer for receiving - * @param len maximum length (in bytes) of data to receive - * @param block if 1, call sio_read; if 0, call sio_tryread - * @return return value of sio_read of sio_tryread - */ -static u32_t -slip_sio_read(sio_fd_t fd, u8_t* data, u32_t len, u8_t block) -{ - if (block) { - return sio_read(fd, data, len); - } else { - return sio_tryread(fd, data, len); - } -} - -/** - * Handle the incoming SLIP stream character by character - * - * Poll the serial layer by calling sio_read() or sio_tryread(). - * - * @param netif the lwip network interface structure for this slipif - * @param block if 1, block until data is received; if 0, return when all data - * from the buffer is received (multiple calls to this function will - * return a complete packet, NULL is returned before - used for polling) - * @return The IP packet when SLIP_END is received - */ -static struct pbuf * -slipif_input(struct netif *netif, u8_t block) -{ - struct slipif_priv *priv; - u8_t c; - struct pbuf *t; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - - priv = netif->state; - - while (slip_sio_read(priv->sd, &c, 1, block) > 0) { - switch (priv->state) { - case SLIP_RECV_NORMAL: - switch (c) { - case SLIP_END: - if (priv->recved > 0) { - /* Received whole packet. */ - /* Trim the pbuf to the size of the received packet. */ - pbuf_realloc(priv->q, priv->recved); - - LINK_STATS_INC(link.recv); - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n")); - t = priv->q; - priv->p = priv->q = NULL; - priv->i = priv->recved = 0; - return t; - } - continue; - case SLIP_ESC: - priv->state = SLIP_RECV_ESCAPE; - continue; - } - break; - case SLIP_RECV_ESCAPE: - switch (c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - priv->state = SLIP_RECV_NORMAL; - /* FALLTHROUGH */ - } - - /* byte received, packet not yet completely received */ - if (priv->p == NULL) { - /* allocate a new pbuf */ - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); - priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN), PBUF_POOL); - - if (priv->p == NULL) { - LINK_STATS_INC(link.drop); - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); - /* don't process any further since we got no pbuf to receive to */ - break; - } - - if (priv->q != NULL) { - /* 'chain' the pbuf to the existing chain */ - pbuf_cat(priv->q, priv->p); - } else { - /* p is the first pbuf in the chain */ - priv->q = priv->p; - } - } - - /* this automatically drops bytes if > SLIP_MAX_SIZE */ - if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) { - ((u8_t *)priv->p->payload)[priv->i] = c; - priv->recved++; - priv->i++; - if (priv->i >= priv->p->len) { - /* on to the next pbuf */ - priv->i = 0; - if (priv->p->next != NULL && priv->p->next->len > 0) { - /* p is a chain, on to the next in the chain */ - priv->p = priv->p->next; - } else { - /* p is a single pbuf, set it to NULL so next time a new - * pbuf is allocated */ - priv->p = NULL; - } - } - } - } - - return NULL; -} - -#if !NO_SYS -/** - * The SLIP input thread. - * - * Feed the IP layer with incoming packets - * - * @param nf the lwip network interface structure for this slipif - */ -static void -slipif_loop_thread(void *nf) -{ - struct pbuf *p; - struct netif *netif = (struct netif *)nf; - - while (1) { - p = slipif_input(netif, SLIP_BLOCK); - if (p != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - p = NULL; - } - } - } -} -#endif /* !NO_SYS */ - -/** - * SLIP netif initialization - * - * Call the arch specific sio_open and remember - * the opened device in the state field of the netif. - * - * @param netif the lwip network interface structure for this slipif - * @return ERR_OK if serial line could be opened, - * ERR_MEM if no memory could be allocated, - * ERR_IF is serial line couldn't be opened - * - * @note netif->num must contain the number of the serial port to open - * (0 by default) - */ -err_t -slipif_init(struct netif *netif) -{ - struct slipif_priv *priv; - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); - - /* Allocate private data */ - priv = mem_malloc(sizeof(struct slipif_priv)); - if (!priv) { - return ERR_MEM; - } - - netif->name[0] = 's'; - netif->name[1] = 'l'; - netif->output = slipif_output; - netif->mtu = SLIP_MAX_SIZE; - netif->flags |= NETIF_FLAG_POINTTOPOINT; - - /* Try to open the serial port (netif->num contains the port number). */ - priv->sd = sio_open(netif->num); - if (!priv->sd) { - /* Opening the serial port failed. */ - mem_free(priv); - return ERR_IF; - } - - /* Initialize private data */ - priv->p = NULL; - priv->q = NULL; - priv->state = SLIP_RECV_NORMAL; - priv->i = 0; - priv->recved = 0; - - netif->state = priv; - - /* initialize the snmp variables and counters inside the struct netif - * ifSpeed: no assumption can be made without knowing more about the - * serial line! - */ - NETIF_INIT_SNMP(netif, snmp_ifType_slip, 0); - - /* Create a thread to poll the serial line. */ - sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif, - SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO); - return ERR_OK; -} - -/** - * Polls the serial device and feeds the IP layer with incoming packets. - * - * @param netif The lwip network interface structure for this slipif - */ -void -slipif_poll(struct netif *netif) -{ - struct pbuf *p; - struct slipif_priv *priv; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); - - priv = netif->state; - - while ((p = slipif_input(netif, SLIP_DONTBLOCK)) != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - } -} - -#endif /* LWIP_HAVE_SLIPIF */ diff --git a/components/net/lwip-1.3.2/test/unit/lwip_check.h b/components/net/lwip-1.3.2/test/unit/lwip_check.h deleted file mode 100644 index d8984a127c..0000000000 --- a/components/net/lwip-1.3.2/test/unit/lwip_check.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __LWIP_CHECK_H__ -#define __LWIP_CHECK_H__ - -/* Common header file for lwIP unit tests using the check framework */ - -#include -#include -#include - -#define FAIL_RET() do { fail(); return; } while(0) -#define EXPECT(x) fail_unless(x) -#define EXPECT_RET(x) do { fail_unless(x); if(!(x)) { return; }} while(0) -#define EXPECT_RETX(x, y) do { fail_unless(x); if(!(x)) { return y; }} while(0) -#define EXPECT_RETNULL(x) EXPECT_RETX(x, NULL) - -/** typedef for a function returning a test suite */ -typedef Suite* (suite_getter_fn)(void); - -/** Create a test suite */ -static Suite* create_suite(const char* name, TFun *tests, size_t num_tests, SFun setup, SFun teardown) -{ - size_t i; - Suite *s = suite_create(name); - - for(i = 0; i < num_tests; i++) { - // Core test case - TCase *tc_core = tcase_create("Core"); - if ((setup != NULL) || (teardown != NULL)) { - tcase_add_checked_fixture(tc_core, setup, teardown); - } - tcase_add_test(tc_core, tests[i]); - suite_add_tcase(s, tc_core); - } - return s; -} - -#endif /* __LWIP_CHECK_H__ */ diff --git a/components/net/lwip-1.3.2/test/unit/lwip_unittests.c b/components/net/lwip-1.3.2/test/unit/lwip_unittests.c deleted file mode 100644 index 2dbeb6d45a..0000000000 --- a/components/net/lwip-1.3.2/test/unit/lwip_unittests.c +++ /dev/null @@ -1,42 +0,0 @@ -#include "lwip_check.h" - -#include "udp/test_udp.h" -#include "tcp/test_tcp.h" -#include "tcp/test_tcp_oos.h" - -#include "lwip/init.h" - - -int main() -{ - int number_failed; - SRunner *sr; - size_t i; - suite_getter_fn* suites[] = { - udp_suite, - tcp_suite, - tcp_oos_suite, - }; - size_t num = sizeof(suites)/sizeof(void*); - LWIP_ASSERT("No suites defined", num > 0); - - lwip_init(); - - sr = srunner_create((suites[0])()); - for(i = 1; i < num; i++) { - srunner_add_suite(sr, ((suite_getter_fn*)suites[i])()); - } - -#ifdef LWIP_UNITTESTS_NOFORK - srunner_set_fork_status(sr, CK_NOFORK); -#endif -#ifdef LWIP_UNITTESTS_FORK - srunner_set_fork_status(sr, CK_FORK); -#endif - - srunner_run_all(sr, CK_NORMAL); - number_failed = srunner_ntests_failed(sr); - srunner_free(sr); - return (number_failed == 0) ? EXIT_SUCCESS : EXIT_FAILURE; -} - diff --git a/components/net/lwip-1.3.2/test/unit/tcp/tcp_helper.c b/components/net/lwip-1.3.2/test/unit/tcp/tcp_helper.c deleted file mode 100644 index 0957cbe42e..0000000000 --- a/components/net/lwip-1.3.2/test/unit/tcp/tcp_helper.c +++ /dev/null @@ -1,196 +0,0 @@ -#include "tcp_helper.h" - -#include "lwip/tcp.h" -#include "lwip/stats.h" -#include "lwip/pbuf.h" -#include "lwip/inet_chksum.h" - -#if !LWIP_STATS || !TCP_STATS || !MEMP_STATS -#error "This tests needs TCP- and MEMP-statistics enabled" -#endif - -/** Remove all pcbs on the given list. */ -static void -tcp_remove(struct tcp_pcb* pcb_list) -{ - struct tcp_pcb *pcb = pcb_list; - struct tcp_pcb *pcb2; - - while(pcb != NULL) { - pcb2 = pcb; - pcb = pcb->next; - tcp_abort(pcb2); - } -} - -/** Remove all pcbs on listen-, active- and time-wait-list (bound- isn't exported). */ -void -tcp_remove_all(void) -{ - //tcp_remove(tcp_bound_pcbs); - tcp_remove(tcp_listen_pcbs.pcbs); - tcp_remove(tcp_active_pcbs); - tcp_remove(tcp_tw_pcbs); - fail_unless(lwip_stats.memp[MEMP_TCP_PCB].used == 0); - fail_unless(lwip_stats.memp[MEMP_TCP_PCB_LISTEN].used == 0); - fail_unless(lwip_stats.memp[MEMP_TCP_SEG].used == 0); - fail_unless(lwip_stats.memp[MEMP_PBUF_POOL].used == 0); -} - -/** Create a TCP segment usable for passing to tcp_input - * - IP-addresses, ports, seqno and ackno are taken from pcb - * - seqno and ackno can be altered with an offset - */ -struct pbuf* -tcp_create_rx_segment(struct tcp_pcb* pcb, void* data, size_t data_len, u32_t seqno_offset, - u32_t ackno_offset, u8_t headerflags) -{ - return tcp_create_segment(&pcb->remote_ip, &pcb->local_ip, pcb->remote_port, pcb->local_port, - data, data_len, pcb->rcv_nxt + seqno_offset, pcb->snd_nxt + ackno_offset, headerflags); -} - -/** Create a TCP segment usable for passing to tcp_input */ -struct pbuf* -tcp_create_segment(struct ip_addr* src_ip, struct ip_addr* dst_ip, - u16_t src_port, u16_t dst_port, void* data, size_t data_len, - u32_t seqno, u32_t ackno, u8_t headerflags) -{ - struct pbuf* p; - struct ip_hdr* iphdr; - struct tcp_hdr* tcphdr; - u16_t pbuf_len = sizeof(struct ip_hdr) + sizeof(struct tcp_hdr) + data_len; - - p = pbuf_alloc(PBUF_RAW, pbuf_len, PBUF_POOL); - EXPECT_RETNULL(p != NULL); - EXPECT_RETNULL(p->next == NULL); - - memset(p->payload, 0, p->len); - - iphdr = p->payload; - /* fill IP header */ - iphdr->dest.addr = dst_ip->addr; - iphdr->src.addr = src_ip->addr; - IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, 0); - IPH_LEN_SET(iphdr, htons(p->tot_len)); - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - - pbuf_header(p, -(s16_t)sizeof(struct ip_hdr)); - - tcphdr = p->payload; - tcphdr->src = htons(src_port); - tcphdr->dest = htons(dst_port); - tcphdr->seqno = htonl(seqno); - tcphdr->ackno = htonl(ackno); - TCPH_HDRLEN_SET(tcphdr, sizeof(struct tcp_hdr)/4); - TCPH_FLAGS_SET(tcphdr, headerflags); - tcphdr->wnd = htonl(TCP_WND); - - /* copy data */ - memcpy((char*)tcphdr + sizeof(struct tcp_hdr), data, data_len); - - /* calculate checksum */ - tcphdr->chksum = inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), - IP_PROTO_TCP, p->tot_len); - - pbuf_header(p, sizeof(struct ip_hdr)); - - return p; -} - -/** Safely bring a tcp_pcb into the requested state */ -void -tcp_set_state(struct tcp_pcb* pcb, enum tcp_state state, struct ip_addr* local_ip, - struct ip_addr* remote_ip, u16_t local_port, u16_t remote_port) -{ - /* @todo: are these all states? */ - /* @todo: remove from previous list */ - pcb->state = state; - if (state == ESTABLISHED) { - TCP_REG(&tcp_active_pcbs, pcb); - pcb->local_ip.addr = local_ip->addr; - pcb->local_port = local_port; - pcb->remote_ip.addr = remote_ip->addr; - pcb->remote_port = remote_port; - } else if(state == LISTEN) { - TCP_REG(&tcp_listen_pcbs.pcbs, pcb); - pcb->local_ip.addr = local_ip->addr; - pcb->local_port = local_port; - } else if(state == TIME_WAIT) { - TCP_REG(&tcp_tw_pcbs, pcb); - pcb->local_ip.addr = local_ip->addr; - pcb->local_port = local_port; - pcb->remote_ip.addr = remote_ip->addr; - pcb->remote_port = remote_port; - } else { - fail(); - } -} - -void -test_tcp_counters_err(void* arg, err_t err) -{ - struct test_tcp_counters* counters = arg; - EXPECT_RET(arg != NULL); - counters->err_calls++; - counters->last_err = err; -} - -static void -test_tcp_counters_check_rxdata(struct test_tcp_counters* counters, struct pbuf* p) -{ - struct pbuf* q; - u32_t i, received; - if(counters->expected_data == NULL) { - /* no data to compare */ - return; - } - EXPECT_RET(counters->recved_bytes + p->tot_len <= counters->expected_data_len); - received = counters->recved_bytes; - for(q = p; q != NULL; q = q->next) { - char *data = q->payload; - for(i = 0; i < q->len; i++) { - EXPECT_RET(data[i] == counters->expected_data[received]); - received++; - } - } - EXPECT(received == counters->recved_bytes + p->tot_len); -} - -err_t -test_tcp_counters_recv(void* arg, struct tcp_pcb* pcb, struct pbuf* p, err_t err) -{ - struct test_tcp_counters* counters = arg; - EXPECT_RETX(arg != NULL, ERR_OK); - EXPECT_RETX(pcb != NULL, ERR_OK); - EXPECT_RETX(err == ERR_OK, ERR_OK); - - if (p != NULL) { - if (counters->close_calls == 0) { - counters->recv_calls++; - test_tcp_counters_check_rxdata(counters, p); - counters->recved_bytes += p->tot_len; - } else { - counters->recv_calls_after_close++; - counters->recved_bytes_after_close += p->tot_len; - } - pbuf_free(p); - } else { - counters->close_calls++; - } - EXPECT(counters->recv_calls_after_close == 0 && counters->recved_bytes_after_close == 0); - return ERR_OK; -} - -/** Allocate a pcb and set up the test_tcp_counters_* callbacks */ -struct tcp_pcb* -test_tcp_new_counters_pcb(struct test_tcp_counters* counters) -{ - struct tcp_pcb* pcb = tcp_new(); - if (pcb != NULL) { - /* set up args and callbacks */ - tcp_arg(pcb, counters); - tcp_recv(pcb, test_tcp_counters_recv); - tcp_err(pcb, test_tcp_counters_err); - } - return pcb; -} diff --git a/components/net/lwip-1.3.2/test/unit/tcp/tcp_helper.h b/components/net/lwip-1.3.2/test/unit/tcp/tcp_helper.h deleted file mode 100644 index b61e0f0af3..0000000000 --- a/components/net/lwip-1.3.2/test/unit/tcp/tcp_helper.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __TCP_HELPER_H__ -#define __TCP_HELPER_H__ - -#include "../lwip_check.h" -#include "lwip/arch.h" -#include "lwip/tcp.h" - -/* counters used for test_tcp_counters_* callback functions */ -struct test_tcp_counters { - u32_t recv_calls; - u32_t recved_bytes; - u32_t recv_calls_after_close; - u32_t recved_bytes_after_close; - u32_t close_calls; - u32_t err_calls; - err_t last_err; - char* expected_data; - u32_t expected_data_len; -}; - -/* Helper functions */ -void tcp_remove_all(void); - -struct pbuf* tcp_create_segment(struct ip_addr* src_ip, struct ip_addr* dst_ip, - u16_t src_port, u16_t dst_port, void* data, size_t data_len, - u32_t seqno, u32_t ackno, u8_t headerflags); -struct pbuf* tcp_create_rx_segment(struct tcp_pcb* pcb, void* data, size_t data_len, - u32_t seqno_offset, u32_t ackno_offset, u8_t headerflags); -void tcp_set_state(struct tcp_pcb* pcb, enum tcp_state state, struct ip_addr* local_ip, - struct ip_addr* remote_ip, u16_t local_port, u16_t remote_port); -void test_tcp_counters_err(void* arg, err_t err); -err_t test_tcp_counters_recv(void* arg, struct tcp_pcb* pcb, struct pbuf* p, err_t err); - -struct tcp_pcb* test_tcp_new_counters_pcb(struct test_tcp_counters* counters); - -#endif diff --git a/components/net/lwip-1.3.2/test/unit/tcp/test_tcp.c b/components/net/lwip-1.3.2/test/unit/tcp/test_tcp.c deleted file mode 100644 index 350cb0cb93..0000000000 --- a/components/net/lwip-1.3.2/test/unit/tcp/test_tcp.c +++ /dev/null @@ -1,104 +0,0 @@ -#include "test_tcp.h" - -#include "lwip/tcp.h" -#include "lwip/stats.h" -#include "tcp_helper.h" - -#if !LWIP_STATS || !TCP_STATS || !MEMP_STATS -#error "This tests needs TCP- and MEMP-statistics enabled" -#endif - -/* Setups/teardown functions */ - -static void -tcp_setup(void) -{ - tcp_remove_all(); -} - -static void -tcp_teardown(void) -{ - tcp_remove_all(); -} - - -/* Test functions */ - -/** Call tcp_new() and tcp_abort() and test memp stats */ -START_TEST(test_tcp_new_abort) -{ - struct tcp_pcb* pcb; - LWIP_UNUSED_ARG(_i); - - fail_unless(lwip_stats.memp[MEMP_TCP_PCB].used == 0); - - pcb = tcp_new(); - fail_unless(pcb != NULL); - if (pcb != NULL) { - fail_unless(lwip_stats.memp[MEMP_TCP_PCB].used == 1); - tcp_abort(pcb); - fail_unless(lwip_stats.memp[MEMP_TCP_PCB].used == 0); - } -} -END_TEST - -/** Create an ESTABLISHED pcb and check if receive callback is called */ -START_TEST(test_tcp_recv_inseq) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf* p; - char data[] = {1, 2, 3, 4}; - struct ip_addr remote_ip, local_ip; - u16_t data_len; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP4_ADDR(&local_ip, 192, 168, 1, 1); - IP4_ADDR(&remote_ip, 192, 168, 1, 2); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create a segment */ - p = tcp_create_rx_segment(pcb, counters.expected_data, data_len, 0, 0, 0); - EXPECT(p != NULL); - if (p != NULL) { - /* pass the segment to tcp_input */ - tcp_input(p, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == data_len); - EXPECT(counters.err_calls == 0); - } - - /* make sure the pcb is freed */ - EXPECT(lwip_stats.memp[MEMP_TCP_PCB].used == 1); - tcp_abort(pcb); - EXPECT(lwip_stats.memp[MEMP_TCP_PCB].used == 0); -} -END_TEST - - -/** Create the suite including all tests for this module */ -Suite * -tcp_suite(void) -{ - TFun tests[] = { - test_tcp_new_abort, - test_tcp_recv_inseq, - }; - return create_suite("TCP", tests, sizeof(tests)/sizeof(TFun), tcp_setup, tcp_teardown); -} diff --git a/components/net/lwip-1.3.2/test/unit/tcp/test_tcp_oos.c b/components/net/lwip-1.3.2/test/unit/tcp/test_tcp_oos.c deleted file mode 100644 index 8e4c7f4d0e..0000000000 --- a/components/net/lwip-1.3.2/test/unit/tcp/test_tcp_oos.c +++ /dev/null @@ -1,433 +0,0 @@ -#include "test_tcp_oos.h" - -#include "lwip/tcp.h" -#include "lwip/stats.h" -#include "tcp_helper.h" - -#if !LWIP_STATS || !TCP_STATS || !MEMP_STATS -#error "This tests needs TCP- and MEMP-statistics enabled" -#endif -#if !TCP_QUEUE_OOSEQ -#error "This tests needs TCP_QUEUE_OOSEQ enabled" -#endif - -/** CHECK_SEGMENTS_ON_OOSEQ: - * 1: check count, seqno and len of segments on pcb->ooseq (strict) - * 0: only check that bytes are received in correct order (less strict) */ -#define CHECK_SEGMENTS_ON_OOSEQ 1 - -#if CHECK_SEGMENTS_ON_OOSEQ -#define EXPECT_OOSEQ(x) EXPECT(x) -#else -#define EXPECT_OOSEQ(x) -#endif - -/* helper functions */ - -/** Get the numbers of segments on the ooseq list */ -static int tcp_oos_count(struct tcp_pcb* pcb) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - while(seg != NULL) { - num++; - seg = seg->next; - } - return num; -} - -/** Get the seqno of a segment (by index) on the ooseq list - * - * @param pcb the pcb to check for ooseq segments - * @param seg_index index of the segment on the ooseq list - * @return seqno of the segment - */ -static u32_t -tcp_oos_seg_seqno(struct tcp_pcb* pcb, int seg_index) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - - /* then check the actual segment */ - while(seg != NULL) { - if(num == seg_index) { - return seg->tcphdr->seqno; - } - num++; - seg = seg->next; - } - fail(); - return 0; -} - -/** Get the tcplen of a segment (by index) on the ooseq list - * - * @param pcb the pcb to check for ooseq segments - * @param seg_index index of the segment on the ooseq list - * @return tcplen of the segment - */ -static int -tcp_oos_seg_tcplen(struct tcp_pcb* pcb, int seg_index) -{ - int num = 0; - struct tcp_seg* seg = pcb->ooseq; - - /* then check the actual segment */ - while(seg != NULL) { - if(num == seg_index) { - return TCP_TCPLEN(seg); - } - num++; - seg = seg->next; - } - fail(); - return -1; -} - -/* Setup/teardown functions */ - -static void -tcp_oos_setup(void) -{ - tcp_remove_all(); -} - -static void -tcp_oos_teardown(void) -{ - tcp_remove_all(); -} - - - -/* Test functions */ - -/** create multiple segments and pass them to tcp_input in a wrong - * order to see if ooseq-caching works correctly - * FIN is received in out-of-sequence segments only */ -START_TEST(test_tcp_recv_ooseq_FIN_OOSEQ) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_8_9, *p_4_8, *p_4_10, *p_2_14, *p_fin, *pinseq; - char data[] = { - 1, 2, 3, 4, - 5, 6, 7, 8, - 9, 10, 11, 12, - 13, 14, 15, 16}; - struct ip_addr remote_ip, local_ip; - u16_t data_len; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP4_ADDR(&local_ip, 192, 168, 1, 1); - IP4_ADDR(&remote_ip, 192, 168, 1, 2); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create segments */ - /* pinseq is sent as last segment! */ - pinseq = tcp_create_rx_segment(pcb, &data[0], 4, 0, 0, TCP_ACK); - /* p1: 8 bytes before FIN */ - /* seqno: 8..16 */ - p_8_9 = tcp_create_rx_segment(pcb, &data[8], 8, 8, 0, TCP_ACK|TCP_FIN); - /* p2: 4 bytes before p1, including the first 4 bytes of p1 (partly duplicate) */ - /* seqno: 4..11 */ - p_4_8 = tcp_create_rx_segment(pcb, &data[4], 8, 4, 0, TCP_ACK); - /* p3: same as p2 but 2 bytes longer */ - /* seqno: 4..13 */ - p_4_10 = tcp_create_rx_segment(pcb, &data[4], 10, 4, 0, TCP_ACK); - /* p4: 14 bytes before FIN, includes data from p1 and p2, plus partly from pinseq */ - /* seqno: 2..15 */ - p_2_14 = tcp_create_rx_segment(pcb, &data[2], 14, 2, 0, TCP_ACK); - /* FIN, seqno 16 */ - p_fin = tcp_create_rx_segment(pcb, NULL, 0,16, 0, TCP_ACK|TCP_FIN); - EXPECT(pinseq != NULL); - EXPECT(p_8_9 != NULL); - EXPECT(p_4_8 != NULL); - EXPECT(p_4_10 != NULL); - EXPECT(p_2_14 != NULL); - EXPECT(p_fin != NULL); - if ((pinseq != NULL) && (p_8_9 != NULL) && (p_4_8 != NULL) && (p_4_10 != NULL) && (p_2_14 != NULL) && (p_fin != NULL)) { - /* pass the segment to tcp_input */ - tcp_input(p_8_9, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - tcp_input(p_4_8, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - tcp_input(p_4_10, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* ooseq queue: unchanged */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 4); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - tcp_input(p_2_14, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 2); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 6); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - tcp_input(p_fin, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* ooseq queue: unchanged */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 2); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 6); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 8); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 9); /* includes FIN */ - - /* pass the segment to tcp_input */ - tcp_input(pinseq, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 1); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == data_len); - EXPECT(counters.err_calls == 0); - EXPECT(pcb->ooseq == NULL); - } - - /* make sure the pcb is freed */ - EXPECT(lwip_stats.memp[MEMP_TCP_PCB].used == 1); - tcp_abort(pcb); - EXPECT(lwip_stats.memp[MEMP_TCP_PCB].used == 0); -} -END_TEST - - -/** create multiple segments and pass them to tcp_input in a wrong - * order to see if ooseq-caching works correctly - * FIN is received IN-SEQUENCE at the end */ -START_TEST(test_tcp_recv_ooseq_FIN_INSEQ) -{ - struct test_tcp_counters counters; - struct tcp_pcb* pcb; - struct pbuf *p_1_2, *p_4_8, *p_3_11, *p_2_12, *p_15_1, *p_15_1a, *pinseq, *pinseqFIN; - char data[] = { - 1, 2, 3, 4, - 5, 6, 7, 8, - 9, 10, 11, 12, - 13, 14, 15, 16}; - struct ip_addr remote_ip, local_ip; - u16_t data_len; - u16_t remote_port = 0x100, local_port = 0x101; - struct netif netif; - LWIP_UNUSED_ARG(_i); - - /* initialize local vars */ - memset(&netif, 0, sizeof(netif)); - IP4_ADDR(&local_ip, 192, 168, 1, 1); - IP4_ADDR(&remote_ip, 192, 168, 1, 2); - data_len = sizeof(data); - /* initialize counter struct */ - memset(&counters, 0, sizeof(counters)); - counters.expected_data_len = data_len; - counters.expected_data = data; - - /* create and initialize the pcb */ - pcb = test_tcp_new_counters_pcb(&counters); - EXPECT_RET(pcb != NULL); - tcp_set_state(pcb, ESTABLISHED, &local_ip, &remote_ip, local_port, remote_port); - - /* create segments */ - /* p1: 7 bytes - 2 before FIN */ - /* seqno: 1..2 */ - p_1_2 = tcp_create_rx_segment(pcb, &data[1], 2, 1, 0, TCP_ACK); - /* p2: 4 bytes before p1, including the first 4 bytes of p1 (partly duplicate) */ - /* seqno: 4..11 */ - p_4_8 = tcp_create_rx_segment(pcb, &data[4], 8, 4, 0, TCP_ACK); - /* p3: same as p2 but 2 bytes longer and one byte more at the front */ - /* seqno: 3..13 */ - p_3_11 = tcp_create_rx_segment(pcb, &data[3], 11, 3, 0, TCP_ACK); - /* p4: 13 bytes - 2 before FIN - should be ignored as contained in p1 and p3 */ - /* seqno: 2..13 */ - p_2_12 = tcp_create_rx_segment(pcb, &data[2], 12, 2, 0, TCP_ACK); - /* pinseq is the first segment that is held back to create ooseq! */ - /* seqno: 0..3 */ - pinseq = tcp_create_rx_segment(pcb, &data[0], 4, 0, 0, TCP_ACK); - /* p5: last byte before FIN */ - /* seqno: 15 */ - p_15_1 = tcp_create_rx_segment(pcb, &data[15], 1, 15, 0, TCP_ACK); - /* p6: same as p5, should be ignored */ - p_15_1a= tcp_create_rx_segment(pcb, &data[15], 1, 15, 0, TCP_ACK); - /* pinseqFIN: last 2 bytes plus FIN */ - /* only segment containing seqno 14 and FIN */ - pinseqFIN = tcp_create_rx_segment(pcb, &data[14], 2, 14, 0, TCP_ACK|TCP_FIN); - EXPECT(pinseq != NULL); - EXPECT(p_1_2 != NULL); - EXPECT(p_4_8 != NULL); - EXPECT(p_3_11 != NULL); - EXPECT(p_2_12 != NULL); - EXPECT(p_15_1 != NULL); - EXPECT(p_15_1a != NULL); - EXPECT(pinseqFIN != NULL); - if ((pinseq != NULL) && (p_1_2 != NULL) && (p_4_8 != NULL) && (p_3_11 != NULL) && (p_2_12 != NULL) - && (p_15_1 != NULL) && (p_15_1a != NULL) && (pinseqFIN != NULL)) { - /* pass the segment to tcp_input */ - tcp_input(p_1_2, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 2); - - /* pass the segment to tcp_input */ - tcp_input(p_4_8, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 4); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 8); - - /* pass the segment to tcp_input */ - tcp_input(p_3_11, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 2); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 2); - /* p_3_11 has removed p_4_8 from ooseq */ - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 3); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 11); - - /* pass the segment to tcp_input */ - tcp_input(p_2_12, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 0); - EXPECT(counters.recved_bytes == 0); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 3); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 1) == 2); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 1) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 2) == 3); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 2) == 11); - - /* pass the segment to tcp_input */ - tcp_input(pinseq, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == 14); - EXPECT(counters.err_calls == 0); - EXPECT(pcb->ooseq == NULL); - - /* pass the segment to tcp_input */ - tcp_input(p_15_1, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == 14); - EXPECT(counters.err_calls == 0); - /* check ooseq queue */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 15); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 1); - - /* pass the segment to tcp_input */ - tcp_input(p_15_1a, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 0); - EXPECT(counters.recv_calls == 1); - EXPECT(counters.recved_bytes == 14); - EXPECT(counters.err_calls == 0); - /* check ooseq queue: unchanged */ - EXPECT_OOSEQ(tcp_oos_count(pcb) == 1); - EXPECT_OOSEQ(tcp_oos_seg_seqno(pcb, 0) == 15); - EXPECT_OOSEQ(tcp_oos_seg_tcplen(pcb, 0) == 1); - - /* pass the segment to tcp_input */ - tcp_input(pinseqFIN, &netif); - /* check if counters are as expected */ - EXPECT(counters.close_calls == 1); - EXPECT(counters.recv_calls == 2); - EXPECT(counters.recved_bytes == data_len); - EXPECT(counters.err_calls == 0); - EXPECT(pcb->ooseq == NULL); - } - - /* make sure the pcb is freed */ - EXPECT(lwip_stats.memp[MEMP_TCP_PCB].used == 1); - tcp_abort(pcb); - EXPECT(lwip_stats.memp[MEMP_TCP_PCB].used == 0); -} -END_TEST - -/** Create the suite including all tests for this module */ -Suite * -tcp_oos_suite(void) -{ - TFun tests[] = { - test_tcp_recv_ooseq_FIN_OOSEQ, - test_tcp_recv_ooseq_FIN_INSEQ, - }; - return create_suite("TCP_OOS", tests, sizeof(tests)/sizeof(TFun), tcp_oos_setup, tcp_oos_teardown); -} diff --git a/components/net/lwip-1.3.2/test/unit/udp/test_udp.c b/components/net/lwip-1.3.2/test/unit/udp/test_udp.c deleted file mode 100644 index d9b407e03b..0000000000 --- a/components/net/lwip-1.3.2/test/unit/udp/test_udp.c +++ /dev/null @@ -1,80 +0,0 @@ -#include "test_udp.h" - -#include "lwip/udp.h" -#include "lwip/stats.h" - -#if !LWIP_STATS || !UDP_STATS || !MEMP_STATS -#error "This tests needs UDP- and MEMP-statistics enabled" -#endif - -/* Helper functions */ -static void -udp_remove_all(void) -{ - struct udp_pcb *pcb = udp_pcbs; - struct udp_pcb *pcb2; - - while(pcb != NULL) { - pcb2 = pcb; - pcb = pcb->next; - udp_remove(pcb2); - } - fail_unless(lwip_stats.memp[MEMP_UDP_PCB].used == 0); -} - -/* Setups/teardown functions */ - -static void -udp_setup(void) -{ - udp_remove_all(); -} - -static void -udp_teardown(void) -{ - udp_remove_all(); -} - - -/* Test functions */ - -START_TEST(test_udp_new_remove) -{ - struct udp_pcb* pcb; - LWIP_UNUSED_ARG(_i); - - fail_unless(lwip_stats.memp[MEMP_UDP_PCB].used == 0); - - pcb = udp_new(); - fail_unless(pcb != NULL); - if (pcb != NULL) { - fail_unless(lwip_stats.memp[MEMP_UDP_PCB].used == 1); - udp_remove(pcb); - fail_unless(lwip_stats.memp[MEMP_UDP_PCB].used == 0); - } -} -END_TEST - -START_TEST(test_udp_remove) -{ - struct udp_pcb* pcb; - LWIP_UNUSED_ARG(_i); - - pcb = NULL; - //pcb = udp_new(); - //fail_unless(pcb != NULL); -} -END_TEST - - -/** Create the suite including all tests for this module */ -Suite * -udp_suite(void) -{ - TFun tests[] = { - test_udp_new_remove, - test_udp_remove - }; - return create_suite("UDP", tests, sizeof(tests)/sizeof(TFun), udp_setup, udp_teardown); -} diff --git a/components/net/lwip-1.4.1/src/arch/sys_arch.c b/components/net/lwip-1.4.1/src/arch/sys_arch.c index d480242cd0..45c09e6137 100644 --- a/components/net/lwip-1.4.1/src/arch/sys_arch.c +++ b/components/net/lwip-1.4.1/src/arch/sys_arch.c @@ -1,11 +1,28 @@ /* - * File : sys_arch.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * All rights reserved. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. * * Change Logs: * Date Author Notes diff --git a/components/net/lwip-1.4.1/src/netif/ethernetif.c b/components/net/lwip-1.4.1/src/netif/ethernetif.c index ddebaf347e..943d95f9ed 100644 --- a/components/net/lwip-1.4.1/src/netif/ethernetif.c +++ b/components/net/lwip-1.4.1/src/netif/ethernetif.c @@ -1,24 +1,6 @@ -/* - * File : ethernetif.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-07 Bernard fix send mail to mailbox issue. - * 2011-07-30 mbbill port lwIP 1.4.0 to RT-Thread - * 2012-04-10 Bernard add more compatible with RT-Thread. - * 2012-11-12 Bernard The network interface can be initialized - * after lwIP initialization. - * 2013-02-28 aozima fixed list_tcps bug: ipaddr_ntoa isn't reentrant. - */ - /* * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * COPYRIGHT (C) 2006-2010, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -47,6 +29,14 @@ * * Author: Adam Dunkels * + * Change Logs: + * Date Author Notes + * 2010-07-07 Bernard fix send mail to mailbox issue. + * 2011-07-30 mbbill port lwIP 1.4.0 to RT-Thread + * 2012-04-10 Bernard add more compatible with RT-Thread. + * 2012-11-12 Bernard The network interface can be initialized + * after lwIP initialization. + * 2013-02-28 aozima fixed list_tcps bug: ipaddr_ntoa isn't reentrant. */ #include diff --git a/components/net/lwip-2.0.2/SConscript b/components/net/lwip-2.0.2/SConscript index 0fc63f4b26..d99556af90 100644 --- a/components/net/lwip-2.0.2/SConscript +++ b/components/net/lwip-2.0.2/SConscript @@ -67,7 +67,7 @@ path = [GetCurrentDir() + '/src', GetCurrentDir() + '/src/arch/include', GetCurrentDir() + '/src/include/netif'] -if not GetDepend('RT_USING_POSIX') or not GetDepend('SAL_USING_POSIX'): +if not GetDepend('RT_USING_SAL'): path += [GetCurrentDir() + '/src/include/posix'] if GetDepend(['RT_LWIP_SNMP']): diff --git a/components/net/lwip-2.0.2/src/api/sockets.c b/components/net/lwip-2.0.2/src/api/sockets.c index 1d0fb0dd19..dc2477b611 100644 --- a/components/net/lwip-2.0.2/src/api/sockets.c +++ b/components/net/lwip-2.0.2/src/api/sockets.c @@ -410,8 +410,6 @@ lwip_tryget_socket(int s) return tryget_socket(s); } - - /** * Allocate a new socket for a given netconn. * @@ -443,6 +441,9 @@ alloc_socket(struct netconn *newconn, int accepted) sockets[i].sendevent = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1); sockets[i].errevent = 0; sockets[i].err = 0; +#ifdef SAL_USING_POSIX + rt_wqueue_init(&sockets[i].wait_head); +#endif return i + LWIP_SOCKET_OFFSET; } SYS_ARCH_UNPROTECT(lev); diff --git a/components/net/lwip-2.0.2/src/arch/include/arch/cc.h b/components/net/lwip-2.0.2/src/arch/include/arch/cc.h index 1875d9ab00..77a589276a 100644 --- a/components/net/lwip-2.0.2/src/arch/include/arch/cc.h +++ b/components/net/lwip-2.0.2/src/arch/include/arch/cc.h @@ -46,7 +46,7 @@ #define X32_F "lx" #ifdef RT_USING_LIBC -#if defined(__CC_ARM) || defined(__IAR_SYSTEMS_ICC__) +#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined(__IAR_SYSTEMS_ICC__) #include #else #include diff --git a/components/net/lwip-2.0.2/src/arch/sys_arch.c b/components/net/lwip-2.0.2/src/arch/sys_arch.c index 97d962e63e..7a92170886 100644 --- a/components/net/lwip-2.0.2/src/arch/sys_arch.c +++ b/components/net/lwip-2.0.2/src/arch/sys_arch.c @@ -1,11 +1,28 @@ /* - * File : sys_arch.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * COPYRIGHT (C) 2006-2018, RT-Thread Development Team + * All rights reserved. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. * * Change Logs: * Date Author Notes diff --git a/components/net/lwip-2.0.2/src/netif/ethernetif.c b/components/net/lwip-2.0.2/src/netif/ethernetif.c index 8ab1727bd3..8b05e592d4 100644 --- a/components/net/lwip-2.0.2/src/netif/ethernetif.c +++ b/components/net/lwip-2.0.2/src/netif/ethernetif.c @@ -1,25 +1,6 @@ -/* - * File : ethernetif.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-07 Bernard fix send mail to mailbox issue. - * 2011-07-30 mbbill port lwIP 1.4.0 to RT-Thread - * 2012-04-10 Bernard add more compatible with RT-Thread. - * 2012-11-12 Bernard The network interface can be initialized - * after lwIP initialization. - * 2013-02-28 aozima fixed list_tcps bug: ipaddr_ntoa isn't reentrant. - * 2016-08-18 Bernard port to lwIP 2.0.0 - */ - /* * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * COPYRIGHT (C) 2006-2018, RT-Thread Development Team * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -48,13 +29,15 @@ * * Author: Adam Dunkels * - */ - -/* - * This file is a skeleton for developing Ethernet network interface - * drivers for lwIP. Add code to the low_level functions and do a - * search-and-replace for the word "ethernetif" to replace it with - * something that better describes your network interface. + * Change Logs: + * Date Author Notes + * 2010-07-07 Bernard fix send mail to mailbox issue. + * 2011-07-30 mbbill port lwIP 1.4.0 to RT-Thread + * 2012-04-10 Bernard add more compatible with RT-Thread. + * 2012-11-12 Bernard The network interface can be initialized + * after lwIP initialization. + * 2013-02-28 aozima fixed list_tcps bug: ipaddr_ntoa isn't reentrant. + * 2016-08-18 Bernard port to lwIP 2.0.0 */ #include "lwip/opt.h" diff --git a/components/net/lwip-1.3.2/CHANGELOG b/components/net/lwip-2.1.0/CHANGELOG similarity index 53% rename from components/net/lwip-1.3.2/CHANGELOG rename to components/net/lwip-2.1.0/CHANGELOG index 860d1c470e..032cfa3ee1 100644 --- a/components/net/lwip-1.3.2/CHANGELOG +++ b/components/net/lwip-2.1.0/CHANGELOG @@ -1,27 +1,2101 @@ -FUTURE - - * TODO: The lwIP source code makes some invalid assumptions on processor - word-length, storage sizes and alignment. See the mailing lists for - problems with exoteric (/DSP) architectures showing these problems. - We still have to fix some of these issues neatly. - - * TODO: the PPP code is broken in a few ways. There are namespace - collisions on BSD systems and many assumptions on word-length - (sizeof(int)). In ppp.c an assumption is made on the availability of - a thread subsystem. Either PPP needs to be moved to contrib/ports/??? - or rearranged to be more generic. - HISTORY + * These are only the most important changes. For a full list, use git log: + http://git.savannah.nongnu.org/cgit/lwip.git -(CVS HEAD) +(git master) * [Enter new changes just after this line - do not remove this line] +(STABLE-2.1.0): + ++ New features: + 2018-06-17: Simon Goldschmidt + * lwiperf: implemented iPerf client mode + + 2018-04-23: Dirk Ziegelmeier + * added cmake build files + + 2018-03-04: Ray Abram + * netbios responder: respond to '*' queries + + 2018-02-23: Benjamin Aigner + * 6lowpan: add 6lowpan-over-BLE netif (based on existing 6lowpan netif) + + 2018-02-22: Simon Goldschmidt + * ipv6: add support for stateless DHCPv6 (to get DNS servers in SLAAC nets) + + 2018-02-16: Simon Goldschmidt + * add raw API http(s) client (with proxy support) + + 2018-02-01: Simon Goldschmidt + * tcp: add hooks to implement additional socket options + + 2018-02-01: Simon Goldschmidt + * tcp: add hooks to implement tcp md5 signatures or similar (see contrib/addons for an example) + + 2018-01-05: Simon Goldschmidt + * Added sys_mbox_trypost_fromisr() and tcpip_callbackmsg_trycallback_fromisr() + These can be used to post preallocated messages from an ISR to the tcpip thread + (e.g. when using FreeRTOS) + + 2018-01-02: Dirk Ziegelmeier + * task #14780: Add debug helper asserts to ensure threading/locking requirements are met + + 2017-11-21: Simon Goldschmidt + * task #14600: tcp_alloc(): kill TF_CLOSEPEND connections before other ESTABLISHED + + 2017-11-21: Simon Goldschmidt + * makefsdata: added option "-ssi:" to control SSI tag checking/insertion + through a list of filenames, not by checking the file extension at runtime + + 2017-11-20: Joel Cunningham + * netconn: add LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE to use external DNS resolver (patch #9427) + + 2017-11-14: Joel Cunningham + * netifapi: Add thread safe ARP cache APIs (task #14724) + + 2017-11-06: Axel Lin + * TCP: kill existing connections with a LOWER priority than the one currently being opened. + Previous implementations also kill existing connections of the SAME priority. + + 2017-09-21: Kalle Olavi Niemitalo + * sockets: add poll() implementation (patch #9450) + + 2017-09-10: Joel Cunningham + * sockets: add readv() implementation (task #14610) + + 2017-08-04: Simon Goldschmidt + * Clean up DHCP a bit: no need keep msg_out and msg_in as members in struct + dhcp - they are used in a call stack only (p_out and options_out_len as well) + + 2017-08-04: Simon Goldschmidt + * pbuf: split pbuf_header(s16_t) into pbuf_add_header(size_t) and + pbuf_remove_header(size_t) + + 2017-07-20: Douglas + * sys: deprecate sys_arch_sem_wait and sys_arch_mbox_fetch returning the + time waited rather they are now defined to return != SYS_ARCH_TIMEOUT + on success. + + 2017-07-03: Jakub Schmidtke + * tcp: added support for sending TCP SACKs + + 2017-06-20: Joel Cunningham + * netconn/netdb: added core locking support to netconn_gethostbyname (task #14523) + + 2017-04-25: Simon Goldschmidt + * dhcp: added two hooks for adding and parsing user defined DHCP options + + 2017-04-25: Joel Cunningham + * sockets: added recvmsg for UDP (together with CMSG and IP_PKTINFO) (task #14247) + + 2017-04-20: Joel Cunningham + * tcp: added Appropriate Byte Counting support (task #14128) + + 2017-04-11: Simon Goldschmidt + * netconn/sockets: remove fatal error handling, fix asynchronous error handling, + ensure data before RST can be received + + 2017-03-30: Simon Goldschmidt + * added "application layered TCP" connection API (altcp) for seamless integration + of TLS or proxy connections + + 2017-03-09: Simon Goldschmidt + * sockets: add recvmsg for TCP + + 2017-03-02: Joel Cunningham + * netconn/sockets: vectorize netconn_write for TCP, treating a vectored I/O write + atomically in regards to TCP segmentation (patch #8882) + + 2017-03-02: Simon Goldschmidt + * netconn: added nonblocking accept/recv to netconn API (task #14396) + + 2017-02-28: Simon Goldschmidt + * Added LWIP_SINGLE_NETIF for small targets with only one netif + + 2017-02-10: David van Moolenbroek + * Implement UDP and RAW multicast support for IPv6 (core API, not netconn/sockets) + + 2017-02-04: David van Moolenbroek + * IPv6 scopes support + + 2017-01-20: Joel Cunningham + * sockets: add interface name/index APIs (task #14314) + + 2017-01-08: David van Moolenbroek + * Extensions to RAW API (patch #9208) + - Connected RAW PCBs + - Add raw_sendto_if_src() + - Support IP_HDRINCL socket option + + ++ Bugfixes: + + 2018-06-19: Simon Goldschmidt + * tcp: fix RTO timer not working if link is down + + 2018-06-15: Sylvain Rochet + * ppp: multiple smaller bugfixes + + 2018-05-17: Simon Goldschmidt + * etharp: arp table can now be bigger than 127 entries + + 2018-04-25: Jens Nielsen + * tftp server: correctly handle retransmissions + + 2018-04-18: Simon Goldschmidt + sockets: fix race conditions when closing full-duplex sockets + + 2018-03-09: Simon Goldschmidt + * 6lowpan: fix to work against contiki; added ZigBee encapsulation netif for tests + + 2018-02-04: Simon Goldschmidt + * sockets: fix inconsistencies on close (inconsistent error codes, double FIN) + + 2018-01-05: Dirk Ziegelmeier + * Fix bug #52748: the bug in timeouts.c by reimplementing timer logic to use + absolute instead of relative timeout values + + 2017-12-31: Dirk Ziegelmeier + * Fix bug #52704: DHCP and bad OFFER: Stop timeout only if offer is accepted + + 2017-11-08: Joel Cunningham + * netif: ensure link and admin states are up in issue reports (bug #52353) + + 2017-09-12: David Lockyer + * select: allocate select_cb from memp for LWIP_MPU_COMPATIBLE = 1 (bug #51990) + + 2017-09-11: Simon Goldschmidt + * tcp_in.c: fix bug #51937 (leaking tcp_pcbs on passive close with unacked data) + + 2017-08-11: Joel Cunningham + * lwip_itoa: fix converting the number 0 (previously converted to '\0') (bug #51729) + + 2017-08-08: Dirk Ziegelmeier + * ip4_route_src: parameter order is reversed: ip4_route_src(dest, src) -> ip4_route_src(src, dest) + to make parameter order consistent with other ip*_route*() functions + Same also applies to LWIP_HOOK_IP4_ROUTE_SRC() parameter order. + + 2017-08-04: Joel Cunningham + * tcp: re-work persist timer to fully close window (details in bug #50837) + + 2017-07-26: Simon Goldschmidt + * snmp_msg.c: fix bug #51578 (SNMP failed to decode some values on non 32bit platforms) + + 2017-07-20: Simon Goldschmidt + * compatibility headers: moved from 'src/include/posix' to 'src/include/compat/posix', + 'src/include/compat/stdc' etc. + + 2017-05-09: Joel Cunningham + * tcp: add zero-window probe timeout (bug #50837) + + 2017-04-11: Simon Goldschmidt + * sockets.c: task #14420 (Remove sys_sem_signal from inside SYS_ARCH_PROTECT + crit section) done for LWIP_TCPIP_CORE_LOCKING==1 + + 2017-02-24: Simon Goldschmidt + * sockets.c: fixed close race conditions in lwip_select (for LWIP_NETCONN_FULLDUPLEX) + + 2017-02-24: Simon Goldschmidt + * sockets.c: fixed that select ignored invalid/not open sockets in the fd_sets (bug #50392) + + 2017-01-11: David van Moolenbroek + * Lots of IPv6 related fixes and improvements + +(STABLE-2.0.3) + + ++ Bugfixes: + + 2017-09-11: Simon Goldschmidt + * tcp_in.c: fix bug #51937 (leaking tcp_pcbs on passive close with unacked data) + + 2017-08-02: Abroz Bizjak/Simon Goldschmidt + * multiple fixes in IPv4 reassembly (leading to corrupted datagrams received) + + 2017-03-30: Simon Goldschmidt + * dhcp.c: return ERR_VAL instead of asserting on offset-out-of-pbuf + + 2017-03-23: Dirk Ziegelmeier + * dhcp.h: fix bug #50618 (dhcp_remove_struct() macro does not work) + +(STABLE-2.0.2) + + ++ New features: + + 2017-02-10: Dirk Ziegelmeier + * Implement task #14367: Hooks need a better place to be defined: + We now have a #define for a header file name that is #included in every .c + file that provides hooks. + + 2017-02-10: Simon Goldschmidt + * tcp_close does not fail on memory error (instead, FIN is sent from tcp_tmr) + + ++ Bugfixes: + + 2017-03-08 + * tcp: do not keep sending SYNs when getting ACKs + + 2017-03-08: Joel Cunningham + * tcp: Initialize ssthresh to TCP_SND_BUF (bug #50476) + + 2017-03-01: Simon Goldschmidt + * httpd: LWIP_HTTPD_POST_MANUAL_WND: fixed double-free when httpd_post_data_recved + is called nested from httpd_post_receive_data() (bug #50424) + + 2017-02-28: David van Moolenbroek/Simon Goldschmidt + * tcp: fixed bug #50418: LWIP_EVENT_API: fix invalid calbacks for SYN_RCVD pcb + + 2017-02-17: Simon Goldschmidt + * dns: Improved DNS_LOCAL_HOSTLIST interface (bug #50325) + + 2017-02-16: Simon Goldschmidt + * LWIP_NETCONN_FULLDUPLEX: fixed shutdown during write (bug #50274) + + 2017-02-13: Simon Goldschmidt/Dirk Ziegelmeier + * For tiny targtes, LWIP_RAND is optional (fix compile time checks) + + 2017-02-10: Simon Goldschmidt + * tcp: Fixed bug #47485 (tcp_close() should not fail on memory error) by retrying + to send FIN from tcp_fasttmr + + 2017-02-09: Simon Goldschmidt + * sockets: Fixed bug #44032 (LWIP_NETCONN_FULLDUPLEX: select might work on + invalid/reused socket) by not allowing to reallocate a socket that has + "select_waiting != 0" + + 2017-02-09: Simon Goldschmidt + * httpd: Fixed bug #50059 (httpd LWIP_HTTPD_SUPPORT_11_KEEPALIVE vs. + LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED) + + 2017-02-08: Dirk Ziegelmeier + * Rename "IPv6 mapped IPv4 addresses" to their correct name from RFC4191: + "IPv4-mapped IPv6 address" + + 2017-02-08: Luc Revardel + * mld6.c: Fix bug #50220 (mld6_leavegroup does not send ICMP6_TYPE_MLD, even + if last reporter) + + 2017-02-08: David van Moolenbroek + * ip6.c: Patch #9250: fix source substitution in ip6_output_if() + + 2017-02-08: Simon Goldschmidt + * tcp_out.c: Fixed bug #50090 (last_unsent->oversize_left can become wrong value + in tcp_write error path) + + 2017-02-02: Dirk Ziegelmeier + * Fix bug #50206: UDP Netconn bind to IP6_ADDR_ANY fails + + 2017-01-18: Dirk Ziegelmeier + * Fix zero-copy RX, see bug bug #50064. PBUF_REFs were not supported as ARP requests. + + 2017-01-15: Axel Lin, Dirk Ziegelmeier + * minor bug fixes in mqtt + + 2017-01-11: Knut Andre Tidemann + * sockets/netconn: fix broken default ICMPv6 handling of checksums + +(STABLE-2.0.1) + + ++ New features: + + 2016-12-31: Simon Goldschmidt + * tcp.h/.c: added function tcp_listen_with_backlog_and_err() to get the error + reason when listening fails (bug #49861) + + 2016-12-20: Erik Andersen + * Add MQTT client + + 2016-12-14: Jan Breuer: + * opt.h, ndc.h/.c: add support for RDNSS option (as per RFC 6106) + + 2016-12-14: David van Moolenbroek + * opt.h, nd6.c: Added LWIP_HOOK_ND6_GET_GW() + + 2016-12-09: Dirk Ziegelmeier + * ip6_frag.c: Implemented support for LWIP_NETIF_TX_SINGLE_PBUF + + 2016-12-09: Simon Goldschmidt + * dns.c: added one-shot multicast DNS queries + + 2016-11-24: Ambroz Bizjak, David van Moolenbroek + * tcp_out.c: Optimize passing contiguous nocopy buffers to tcp_write (bug #46290) + + 2016-11-16: Dirk Ziegelmeier + * sockets.c: added support for IPv6 mapped IPv4 addresses + + ++ Bugfixes: + + 2016-12-16: Thomas Mueller + * api_lib.c: fixed race condition in return value of netconn_gethostbyname() + (and thus also lwip_gethostbyname/_r() and lwip_getaddrinfo()) + + 2016-12-15: David van Moolenbroek + * opt.h, tcp: added LWIP_HOOK_TCP_ISN() to implement less predictable initial + sequence numbers (see contrib/addons/tcp_isn for an example implementation) + + 2016-12-05: Dirk Ziegelmeier + * fixed compiling with IPv4 disabled (IPv6 only case) + + 2016-11-28: Simon Goldschmidt + * api_lib.c: fixed bug #49725 (send-timeout: netconn_write() can return + ERR_OK without all bytes being written) + + 2016-11-28: Ambroz Bizjak + * tcpi_in.c: fixed bug #49717 (window size in received SYN and SYN-ACK + assumed scaled) + + 2016-11-25: Simon Goldschmidt + * dhcp.c: fixed bug #49676 (Possible endless loop when parsing dhcp options) + + 2016-11-23: Dirk Ziegelmeier + * udp.c: fixed bug #49662: multicast traffic is now only received on a UDP PCB + (and therefore on a UDP socket/netconn) when the PCB is bound to IP_ADDR_ANY + + 2016-11-16: Dirk Ziegelmeier + * *: Fixed dual-stack behaviour, IPv6 mapped IPv4 support in socket API + + 2016-11-14: Joel Cunningham + * tcp_out.c: fixed bug #49533 (start persist timer when unsent seg can't fit + in window) + + 2016-11-16: Roberto Barbieri Carrera + * autoip.c: fixed bug #49610 (sometimes AutoIP fails to reuse the same address) + + 2016-11-11: Dirk Ziegelmeier + * sockets.c: fixed bug #49578 (dropping multicast membership does not work + with LWIP_SOCKET_OFFSET) + +(STABLE-2.0.0) + + ++ New features: + + 2016-07-27: Simon Goldschmidt + * opt.h, timeouts.h/.c: added LWIP_TIMERS_CUSTOM to override the default + implementation of timeouts + + 2016-07-xx: Dirk Ziegelmeier + * Large overhaul of doxygen documentation + + 2016-04-05: Simon Goldschmidt + * timers.h/.c: prepare for overriding current timeout implementation: all + stack-internal caclic timers are avaliable in the lwip_cyclic_timers array + + 2016-03-23: Simon Goldschmidt + * tcp: call accept-callback with ERR_MEM when allocating a pcb fails on + passive open to inform the application about this error + ATTENTION: applications have to handle NULL pcb in accept callback! + + 2016-02-22: Ivan Delamer + * Initial 6LoWPAN support + + 2016-02-XX to 2016-03-XX: Dirk Ziegelmeier + * Cleanup TCPIP thread sync methods in a way that it is possibe to use them + in arbitrary code that needs things to be done in TCPIP thread. Used to + decouple netconn, netif, ppp and 6LoWPAN from LWIP core. + + 2016-02-XX: Dirk Ziegelmeier + * Implement dual-stack support in RAW, UDP and TCP. Add new IP address + type IPADDR_ANY_TYPE for this. Netconn/Socket API: Dual-stack is + automatically supported when an IPv6 netconn/socket is created. + + 2015-12-26: Martin Hentschel and Dirk Ziegelmeier + * Rewrite SNMP agent. SNMPv2c + MIB compiler. + + 2015-11-12: Dirk Ziegelmeier + * Decouple SNMP stack from lwIP core and move stack to apps/ directory. + Breaking change: Users have to call snmp_init() now! + + 2015-11-12: Dirk Ziegelmeier + * Implement possibility to declare private memory pools. This is useful to + decouple some apps from the core (SNMP stack) or make contrib app usage + simpler (httpserver_raw) + + 2015-10-09: Simon Goldschmidt + * started to move "private" header files containing implementation details to + "lwip/priv/" include directory to seperate the API from the implementation. + + 2015-10-07: Simon Goldschmidt + * added sntp client as first "supported" application layer protocol implementation + added 'apps' folder + + 2015-09-30: Dirk Ziegelmeier + * snmp_structs.h, mib_structs.c, mib2.c: snmp: fixed ugly inheritance + implementation by aggregating the "base class" (struct mib_node) in all + derived node classes to get more type-safe code + + 2015-09-23: Simon Goldschmidt + * netif.h/.c, nd6.c: task #13729: Convert netif addresses (IPv4 & IPv6) to + ip_addr_t (so they can be used without conversion/temporary storage) + + 2015-09-08: Dirk Ziegelmeier + * snmp: Separate mib2 counter/table callbacks from snmp agent. This both cleans + up the code and should allow integration of a 3rd party agent/mib2. Simple + counters are kept in MIB2_STATS, tree/table change function prototypes moved to + snmp_mib2.h. + + 2015-09-03: Simon Goldschmidt + * opt.h, dns.h/.c: DNS/IPv6: added support for AAAA records + + 2015-09-01: Simon Goldschmidt + * task #12178: hardware checksum capabilities can be configured per netif + (use NETIF_SET_CHECKSUM_CTRL() in your netif's init function) + + 2015-08-30: Simon Goldschmidt + * PBUF_REF with "custom" pbufs is now supported for RX pbufs (see pcapif in + contrib for an example, LWIP_SUPPORT_CUSTOM_PBUF is required) + + 2015-08-30: Simon Goldschmidt + * support IPv4 source based routing: define LWIP_HOOK_IP4_ROUTE_SRC to point + to a routing function + + 2015-08-05: Simon Goldschmidt + * many files: allow multicast socket options IP_MULTICAST_TTL, IP_MULTICAST_IF + and IP_MULTICAST_LOOP to be used without IGMP + + 2015-04-24: Simon Goldschmidt + * dhcp.h/c, autoip.h/.c: added functions dhcp/autoip_supplied_address() to + check for the source of address assignment (replacement for NETIF_FLAG_DHCP) + + 2015-04-10: Simon Goldschmidt + * many files: task #13480: added LWIP_IPV4 define - IPv4 can be disabled, + leaving an IPv6-only stack + + 2015-04-09: Simon Goldschmidt + * nearly all files: task #12722 (improve IPv4/v6 address handling): renamed + ip_addr_t to ip4_addr_t, renamed ipX_addr_t to ip_addr_t and added IP + version; ip_addr_t is used for all generic IP addresses for the API, + ip(4/6)_addr_t are only used internally or when initializing netifs or when + calling version-related functions + + 2015-03-24: Simon Goldschmidt + * opt.h, ip4_addr.h, ip4.c, ip6.c: loopif is not required for loopback traffic + any more but passed through any netif (ENABLE_LOOPBACK has to be enabled) + + 2015-03-23: Simon Goldschmidt + * opt.h, etharp.c: with ETHARP_TABLE_MATCH_NETIF== 1, duplicate (Auto)-IP + addresses on multiple netifs should now be working correctly (if correctly + addressed by routing, that is) + + 2015-03-23: Simon Goldschmidt + * etharp.c: Stable etharp entries that are about to expire are now refreshed + using unicast to prevent unnecessary broadcast. Only if no answer is received + after 15 seconds, broadcast is used. + + 2015-03-06: Philip Gladstone + * netif.h/.c: patch #8359 (Provide utility function to add an IPv6 address to + an interface) + + 2015-03-05: Simon Goldschmidt + * netif.c, ip4.c, dhcp.c, autoip.c: fixed bug #37068 (netif up/down handling + is unclear): correclty separated administrative status of a netif (up/down) + from 'valid address' status + ATTENTION: netif_set_up() now always has to be called, even when dhcp/autoip + is used! + + 2015-02-26: patch by TabascoEye + * netif.c, udp.h/.c: fixed bug #40753 (re-bind UDP pcbs on change of IP address) + + 2015-02-22: chrysn, Simon Goldschmidt + * *.*: Changed nearly all functions taking 'ip(X)_addr_t' pointer to take + const pointers (changed user callbacks: raw_recv_fn, udp_recv_fn; changed + port callbacks: netif_output_fn, netif_igmp_mac_filter_fn) + + 2015-02-19: Ivan Delamer + * netif.h, dhcp.c: Removed unused netif flag for DHCP. The preferred way to evaluate + if DHCP is active is through netif->dhcp field. + + 2015-02-19: Ivan Delamer + * netif.h, slipif.c, ppp.c: Removed unused netif flag for point to point connections + + 2015-02-18: Simon Goldschmidt + * api_lib.c: fixed bug #37958 "netconn API doesn't handle correctly + connections half-closed by peer" + + 2015-02-18: Simon Goldschmidt + * tcp.c: tcp_alloc() prefers killing CLOSING/LAST_ACK over active connections + (see bug #39565) + + 2015-02-16: Claudius Zingerli, Sergio Caprile + * opt.h, dhcp.h/.c: patch #8361 "Add support for NTP option in DHCP" + + 2015-02-14: Simon Goldschmidt + * opt.h, snmp*: added support for write-access community and dedicated + community for sending traps + + 2015-02-13: Simon Goldschmidt + * opt.h, memp.c: added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when + a memp pool was empty and an item is now available + + 2015-02-13: Simon Goldschmidt + * opt.h, pbuf.h/.c, etharp.c: Added the option PBUF_LINK_ENCAPSULATION_HLEN to + allocate additional header space for TX on netifs requiring additional headers + + 2015-02-12: chrysn + * timers.h/.c: introduce sys_timeouts_sleeptime (returns the time left before + the next timeout is due, for NO_SYS==1) + + 2015-02-11: Nick van Ijzendoorn + * opt.h, sockets.h/c: patch #7702 "Include ability to increase the socket number + with defined offset" + + 2015-02-11: Frederick Baksik + * opt.h, def.h, others: patch #8423 "arch/perf.h" should be made an optional item + + 2015-02-11: Simon Goldschmidt + * api_msg.c, opt.h: started to implement fullduplex sockets/netconns + (note that this is highly unstable yet!) + + 2015-01-17: Simon Goldschmidt + * api: allow enabling socket API without (public) netconn API - netconn API is + still used by sockets, but keeping it private (static) should allow better + compiler optimizations + + 2015-01-16: Simon Goldschmidt + * tcp_in.c: fixed bug #20506 "Initial congestion window is very small" again + by implementing the calculation formula from RFC3390 + + 2014-12-10: Simon Goldschmidt + * api: added option LWIP_NETCONN_SEM_PER_THREAD to use a semaphore per thread + instead of using one per netconn and per select call + + 2014-12-08: Simon Goldschmidt + * ip6.h: fixed bug #43778: IPv6 header version not set on 16-bit platform + (macro IP6H_VTCFL_SET()) + + 2014-12-08: Simon Goldschmidt + * icmp.c, ip4.c, pbuf.c, udp.c, pbuf.h: task #11472 Support PBUF_REF for RX + (IPv6 and IPv4/v6 reassembly might not work yet) + + 2014-11-06: Simon Goldschmidt + * sockets.c/.h, init.c: lwip_socket_init() is not needed any more + -> compatibility define + + 2014-09-16: Simon Goldschmidt + * dns.c, opt.h: reduced ram usage by parsing DNS responses in place + + 2014-09-16: Simon Goldschmidt + * pbuf.h/.c: added pbuf_take_at() and pbuf_put_at() + + 2014-09-15: Simon Goldschmidt + * dns.c: added source port randomization to make the DNS client more robust + (see bug #43144) + + 2013-09-02: Simon Goldschmidt + * arch.h and many other files: added optional macros PACK_STRUCT_FLD_8() and + PACK_STRUCT_FLD_S() to prevent gcc 4 from warning about struct members that + do not need packing + + 2013-08-19: Simon Goldschmidt + * netif.h: bug #42998: made NETIF_MAX_HWADDR_LEN overridable for some special + networks + + 2013-03-17: Simon Goldschmidt (patch by Ghobad Emadi) + * opt.h, etharp.c: Added LWIP_HOOK_ETHARP_GET_GW to implement IPv4 routing with + multiple gateways + + 2013-04-20: Fatih Asici + * opt.h, etharp.h/.c: patch #7993: Added support for transmitting packets + with VLAN headers via hook function LWIP_HOOK_VLAN_SET and to check them + via hook function LWIP_HOOK_VLAN_CHECK + + 2014-02-20: Simon Goldschmidt (based on patch by Artem Pisarenko) + * patch #7885: modification of api modules to support FreeRTOS-MPU + (don't pass stack-pointers to other threads) + + 2014-02-05: Simon Goldschmidt (patch by "xtian" and "alex_ab") + * patch #6537/#7858: TCP window scaling support + + 2014-01-17: Jiri Engelthaler + * icmp, icmp6, opt.h: patch #8027: Completed HW checksuming for IPv4 and + IPv6 ICMP's + + 2012-08-22: Sylvain Rochet + * New PPP stack for lwIP, developed in ppp-new branch. + Based from pppd 2.4.5, released 2009-11-17, with huge changes to match + code size and memory requirements for embedded devices, including: + - Gluing together the previous low-level PPP code in lwIP to pppd 2.4.5, which + is more or less what pppd sys-* files are, so that we get something working + using the unix port. + - Merged some patchs from lwIP Git repository which add interesting features + or fix bugs. + - Merged some patchs from Debian pppd package which add interesting features + or fix bugs. + - Ported PPP timeout handling to the lwIP timers system + - Disabled all the PPP code using filesystem access, replaced in necessary cases + to configuration variables. + - Disabled all the PPP code forking processes. + - Removed IPX support, lwIP does not support IPX. + - Ported and improved random module from the previous PPP port. + - Removed samba TDB (file-driven database) usage, because it needs a filesystem. + - MS-CHAP required a DES implementation, we added the latest PolarSSL DES + implementation which is under a BSD-ish license. + - Also switched to PolarSSL MD4,MD5,SHA1 implementations, which are meant to be + used in embedded devices with reduced memory footprint. + - Removed PPP configuration file parsing support. + - Added macro definition EAP_SUPPORT to make EAP support optional. + - Added macro definition CHAP_SUPPORT to make CHAP support optional. + - Added macro definition MSCHAP_SUPPORT to make MSCHAP support optional. + - Added macro definition PAP_SUPPORT to make PAP support optional. + - Cleared all Linux syscall calls. + - Disabled demand support using a macro, so that it can be ported later. + - Disabled ECP support using a macro, so that it can be ported later. + - Disabled CCP support using a macro, so that it can be ported later. + - Disabled CBCP support using a macro, so that it can be ported later. + - Disabled LQR support using a macro, so that it can be ported later. + - Print packet debug feature optional, through PRINTPKT_SUPPORT + - Removed POSIX signal usage. + - Fully ported PPPoS code from the previous port. + - Fully ported PPPoE code from the previous port. + - Fully ported VJ compression protocol code from the previous port. + - Removed all malloc()/free() use from PPP, replaced by stack usage or PBUF. + - Disabled PPP server support using a macro, so that it can be ported later. + - Switched all PPP debug to lwIP debug system. + - Created PPP Control Block (PPP PCB), removed PPP unit integer everywhere, + removed all global variables everywhere, did everything necessary for + the PPP stack to support more than one PPP session (pppd only support + one session per process). + - Removed the statically allocated output buffer, now using PBUF. + - Improved structure size of all PPP modules, deep analyze of code to reduce + variables size to the bare minimum. Switched all boolean type (char type in + most architecture) to compiler generated bitfields. + - Added PPP IPv6 support, glued lwIP IPv6 support to PPP. + - Now using a persistent netif interface which can then be used in lwIP + functions requiring a netif. + - Now initializing PPP in lwip_init() function. + - Reworked completely the PPP state machine, so that we don't end up in + anymore in inconsistent state, especially with PPPoE. + - Improved the way we handle PPP reconnection after disconnect, cleaning + everything required so that we start the PPP connection again from a + clean state. + - Added PPP holdoff support, allow the lwIP user to wait a little bit before + reconnecting, prevents connection flood, especially when using PPPoL2TP. + - Added PPPoL2TP LAC support (a.k.a. UDP tunnels), adding a VPN client + feature to lwIP, L2TP being a widely used tunnel protocol. + - Switched all used PPP types to lwIP types (u8t, u16t, u32t, ...) + - Added PPP API "sequential" thread-safe API, based from NETIFAPI. + + 2011-07-21: Simon Goldschmidt + * sockets.c, opt.h: (bug #30185): added LWIP_FIONREAD_LINUXMODE that makes + ioctl/FIONREAD return the size of the next pending datagram. + + 2011-05-25: Simon Goldschmidt + * again nearly the whole stack, renamed ip.c to ip4.c, ip_addr.c to ip4_addr.c, + combined ipv4/ipv6 inet_chksum.c, added ip.h, ip_addr.h: Combined IPv4 + and IPv6 code where possible, added defines to access IPv4/IPv6 in non-IP + code so that the code is more readable. + + 2011-05-17: Patch by Ivan Delamer (only checked in by Simon Goldschmidt) + * nearly the whole stack: Finally, we got decent IPv6 support, big thanks to + Ivan! (this is work in progress: we're just post release anyway :-) + ++ Bugfixes: + 2016-08-23: Simon Goldschmidt + * etharp: removed ETHARP_TRUST_IP_MAC since it is insecure and we don't need + it any more after implementing unicast ARP renewal towards arp entry timeout + + 2016-07-20: Simon Goldschmidt + * memp.h/.c: fixed bug #48442 (memp stats don't work for MEMP_MEM_MALLOC) + + 2016-07-21: Simon Goldschmidt (patch by Ambroz Bizjak) + * tcp_in.c, tcp_out.c: fixed bug #48543 (TCP sent callback may prematurely + report sent data when only part of a segment is acked) and don't include + SYN/FIN in snd_buf counter + + 2016-07-19: Simon Goldschmidt + * etharp.c: fixed bug #48477 (ARP input packet might update static entry) + + 2016-07-11: Simon Goldschmidt + * tcp_in.c: fixed bug #48476 (TCP sent callback called wrongly due to picking + up old pcb->acked + + 2016-06-30: Simon Goldschmidt (original patch by Fabian Koch) + * tcp_in.c: fixed bug #48170 (Vulnerable to TCP RST spoofing) + + 2016-05-20: Dirk Ziegelmeier + * sntp.h/.c: Fix return value of sntp_getserver() call to return a pointer + + 2016-04-05: Simon Goldschmidt (patch by Philip Gladstone) + * udp.c: patch #8358: allow more combinations of listening PCB for IPv6 + + 2016-04-05: Simon Goldschmidt + * netconn/socket API: fixed bug# 43739 (Accept not reporting errors about + aborted connections): netconn_accept() returns ERR_ABRT (sockets: ECONNABORTED) + for aborted connections, ERR_CLSD (sockets: EINVAL) if the listening netconn + is closed, which better seems to follow the standard. + + 2016-03-23: Florent Matignon + * dhcp.c: fixed bug #38203: DHCP options are not recorded in all DHCP ack messages + + 2016-03-22: Simon Goldschmidt + * tcp: changed accept handling to be done internally: the application does not + have to call tcp_accepted() any more. Instead, when delaying accept (e.g. sockets + do), call tcp_backlog_delayed()/tcp_backlog_accepted() (fixes bug #46696) + + 2016-03-22: Simon Goldschmidt + * dns.c: ignore dns response parsing errors, only abort resolving for correct + responses or error responses from correct server (bug #47459) + + 2016-03-17: Simon Goldschmidt + * api_msg.c: fixed bug #47448 (netconn/socket leak if RST is received during close) + + 2016-03-17: Joel Cunningham + * api_msg.c: don't fail closing a socket/netconn when failing to allocate the + FIN segment; blocking the calling thread for a while is better than risking + leaking a netconn/socket (see bug #46701) + + 2016-03-16: Joel Cunningham + * tcp_out.c: reset rto timer on fast retransmission + + 2016-03-16: Deomid Ryabkov + * tcp_out.c: fixed bug #46384 Segment size calculation bug with MSS != TCP_MSS + + 2016-03-05: Simon Goldschmidt + * err.h/.c, sockets.c: ERR_IF is not necessarily a fatal error + + 2015-11-19: fix by Kerem Hadimli + * sockets.c: fixed bug #46471: lwip_accept() leaks socket descriptors if new + netconn was already closed because of peer behavior + + 2015-11-12: fix by Valery Ushakov + * tcp_in.c: fixed bug #46365 tcp_accept_null() should call tcp_abort() + + 2015-10-02: Dirk Ziegelmeier/Simon Goldschmidt + * snmp: cleaned up snmp structs API (fixed race conditions from bug #46089, + reduce ram/rom usage of tables): incompatible change for private MIBs + + 2015-09-30: Simon Goldschmidt + * ip4_addr.c: fixed bug #46072: ip4addr_aton() does not check the number range + of all address parts + + 2015-08-28: Simon Goldschmidt + * tcp.c, tcp_in.c: fixed bug #44023: TCP ssthresh value is unclear: ssthresh + is set to the full send window for active open, too, and is updated once + after SYN to ensure the correct send window is used + + 2015-08-28: Simon Goldschmidt + * tcp: fixed bug #45559: Window scaling casts u32_t to u16_t without checks + + 2015-08-26: Simon Goldschmidt + * ip6_frag.h/.c: fixed bug bug #41009: IPv6 reassembly broken on 64-bit platforms: + define IPV6_FRAG_COPYHEADER==1 on these platforms to copy the IPv6 header + instead of referencing it, which gives more room for struct ip6_reass_helper + + 2015-08-25: Simon Goldschmidt + * sockets.c: fixed bug #45827: recvfrom: TCP window is updated with MSG_PEEK + + 2015-08-20: Manoj Kumar + * snmp_msg.h, msg_in.c: fixed bug #43790: Sending octet string of Length >255 + from SNMP agent + + 2015-08-19: Jens Nielsen + * icmp.c, ip4.c, tcp_in.c, udp.c, raw.c: fixed bug #45120: Broadcast & multiple + interfaces handling + + 2015-08-19: Simon Goldschmidt (patch by "Sandra") + * dns.c: fixed bug #45004: dns response without answer might be discarded + + 2015-08-18: Chrysn + * timers.c: patch #8704 fix sys_timeouts_sleeptime function + + 2015-07-01: Erik Ekman + * puf.c: fixed bug #45454 (pbuf_take_at() skips write and returns OK if offset + is at start of pbuf in chain) + + 2015-05-19: Simon Goldschmidt + * dhcp.h/.c: fixed bugs #45140 and #45141 (dhcp was not stopped correctly after + fixing bug #38204) + + 2015-03-21: Simon Goldschmidt (patch by Homyak) + * tcp_in.c: fixed bug #44766 (LWIP_WND_SCALE: tcphdr->wnd was not scaled in + two places) + + 2015-03-21: Simon Goldschmidt + * tcp_impl.h, tcp.c, tcp_in.c: fixed bug #41318 (Bad memory ref in tcp_input() + after tcp_close()) + + 2015-03-21: Simon Goldschmidt + * tcp_in.c: fixed bug #38468 (tcp_sent() not called on half-open connection for + data ACKed with the same ack as FIN) + + 2015-03-21: Simon Goldschmidt (patch by Christoffer Lind) + * dhcp.h/.c: fixed bug #38204 (DHCP lease time not handled correctly) + + 2015-03-20: Simon Goldschmidt + * dhcp.c: fixed bug #38714 (Missing option and client address in DHCPRELEASE message) + + 2015-03-19: Simon Goldschmidt + * api.h, tcpip.h, api_lib.c, api_msg.c: fixed race conditions in assigning + netconn->last_err (fixed bugs #38121 and #37676) + + 2015-03-09: Simon Goldschmidt + * ip4.c: fixed the IPv4 part of bug #43904 (ip_route() must detect linkup status) + + 2015-03-04: Simon Goldschmidt + * nd6.c: fixed bug #43784 (a host should send at least one Router Solicitation) + + 2015-03-04: Valery Ushakov + * ip6.c: fixed bug #41094 (Byte-order bug in IPv6 fragmentation header test) + + 2015-03-04: Zach Smith + * nd6.c: fixed bug #38153 (nd6_input() byte order issues) + + 2015-02-26: Simon Goldschmidt + * netif.c, tcp.h/.c: fixed bug #44378 (TCP connections are not aborted on netif + remove) + + 2015-02-25: Simon Goldschmidt + * ip4.c, etharp.c: fixed bug #40177 (System hangs when dealing with corrupted + packets), implemented task #12357 (Ensure that malicious packets don't + assert-fail): improved some pbuf_header calls to not assert-fail. + + 2015-02-25: patch by Joel Cunningham + * udp.h/.c, sockets.c: fixed bug #43028 (IP_MULTICAST_TTL affects unicast + datagrams) + + 2015-02-25: patch by Greg Renda + * ip4_frag.c: fixed bug #38210 (ip reassembly while remove oldest datagram) + + 2015-02-25: Simon Goldschmidt + * sockets.c: fixed bug #38165 (socket with mulicast): ensure igmp membership + are dropped when socket (not netconn!) is closed. + + 2015-02-25: Simon Goldschmidt + * ip4.h/.c, udp.c: fixed bug #38061 (wrong multicast routing in IPv4) by + adding an optional default netif for multicast routing + + 2015-02-25: Simon Goldschmidt + * netconn API: fixed that netconn_connect still used message passing for + LWIP_TCPIP_CORE_LOCKING==1 + + 2015-02-22: patch by Jens Nielsen + * icmp.c: fixed bug #38803 (Source address in broadcast ping reply) + + 2015-02-22: Simon Goldschmidt + * udp.h, sockets.c: added proper accessor functions for pcb->multicast_ip + (previously used by get/setsockopt only) + + 2015-02-18: Simon Goldschmidt + * sockets.c: Fixed select not reporting received FIN as 'readable' in certain + rare cases (bug #43779: select(), close(), and TCP retransmission error) + + 2015-02-17: Simon Goldschmidt + * err.h, sockets.c, api_msg.c: fixed bug #38853 "connect() use a wrong errno": + return ERR_ALREADY/EALRADY during connect, ERR_ISCONN/EISCONN when already + connected + + 2015-02-17: Simon Goldschmidt + * tcp_impl.h, tcp_out.c, tcp.c, api_msg.c: fixed bug #37614 "Errors from + ipX_output are not processed". Now tcp_output(_segment) checks for the return + value of ipX_output and does not try to send more on error. A netif driver + can call tcp_txnow() (from tcpip_thread!) to try to send again if TX buffers + are available again. + + 2015-02-14: patches by Freddie Chopin + * snmp*: made community writable, fixed some const pointers + + 2015-02-13: Simon Goldschmidt + * msg_in.c: fixed bug #22070 "MIB_OBJECT_WRITE_ONLY not implemented in SNMP" + + 2015-02-12: Simon Goldschmidt + * ip.h, ip4.c, ip6.c: fixed bug #36403 "ip4_input() and ip6_input() always pass + inp to higher layers": now the accepting netif is passed up, but the input + netif is available through ip_current_input_netif() if required. + + 2015-02-11: patch by hichard + * tcpip.c: fixed bug #43094 "The function tcpip_input() forget to handle IPv6" + + 2015-02-10: Simon Goldschmidt + * netconn API: fixed that netconn_close/netconn_delete still used message passing + for LWIP_TCPIP_CORE_LOCKING==1 + + 2015-02-10: Simon Goldschmidt + * netconn/socket api: fixed bug #44225 "closing TCP socket should time out + eventually", implemented task #6930 "Implement SO_LINGER": closing TCP sockets + times out after 20 seconds or after the configured SND_TIMEOUT or depending + on the linger settings. + + 2015-01-27: Simon Goldschmidt + * api_msg.c: fixed that SHUT_RD followed by SHUT_WR was different to SHUT_RDWR, + fixed return value of lwip_netconn_do_close on unconnected netconns + + 2015-01-17: Simon Goldschmidt + * sockets.c: fixed bug #43361 select() crashes with stale FDs + + 2015-01-17: Simon Goldschmidt + * sockets.c/.h, memp_std.h: fixed bug #40788 "lwip_setsockopt_internal() crashes" + by rewriting set/getsockopt functions to combine checks with the actual code + and add more NULL checks; this also fixes that CORE_LOCKING used message + passing for set/getsockopt. + + 2014-12-19: Simon Goldschmidt + * opt.h, dhcp.h/.c: prevent dhcp from starting when netif link is down (only + when LWIP_DHCP_CHECK_LINK_UP==1, which is disabled by default for + compatibility reasons) + + 2014-12-17: Simon Goldschmidt + * tcp_out.c: fixed bug #43840 Checksum error for TCP_CHECKSUM_ON_COPY==1 for + no-copy data with odd length + + 2014-12-10: Simon Goldschmidt + * sockets.c, tcp.c, others: fixed bug #43797 set/getsockopt: SO_SNDTIMEO/SO_RCVTIMEO + take int as option but should take timeval (LWIP_SO_SNDRCVTIMEO_STANDARD==0 can + be used to revert to the old 'winsock' style behaviour) + Fixed implementation of SO_ACCEPTCONN to just look at the pcb state + + 2014-12-09: Simon Goldschmidt + * ip4.c: fixed bug #43596 IGMP queries from 0.0.0.0 are discarded + + 2014-10-21: Simon Goldschmidt (patch by Joel Cunningham and Albert Huitsing) + * sockts.c: fixed bugs #41495 Possible threading issue in select() and #43278 + event_callback() handle context switch when calling sys_sem_signal() + + 2014-10-21: Simon Goldschmidt + * api_msg.c: fixed bug #38219 Assert on TCP netconn_write with sndtimeout set + + 2014-09-16: Kevin Cernekee + * dns.c: patch #8480 Fix handling of dns_seqno wraparound + + 2014-09-16: Simon Goldschmidt + * tcp_out.c: fixed bug #43192 tcp_enqueue_flags() should not check TCP_SND_QUEUELEN + when sending FIN + + 2014-09-03: Simon Goldschmidt + * msg_in.c: fixed bug #39355 SNMP Memory Leak in case of error + + 2014-09-02: Simon Goldschmidt + * err.h/.c, sockets.c, api_msg.c: fixed bug #43110 call getpeername() before + listen() will cause a error + + 2014-09-02: Simon Goldschmidt + * sockets.c: fixed bug #42117 lwip_fcntl does not set errno + + 2014-09-02: Simon Goldschmidt + * tcp.c: fixed bug #42299 tcp_abort() leaves freed pcb on tcp_bound_pcbs list + + 2014-08-20: Simon Goldschmidt + * dns.c: fixed bug #42987 lwIP is vulnerable to DNS cache poisoning due to + non-randomized TXIDs + + 2014-06-03: Simon Goldschmidt + * tcp_impl.h, tcp_in.c: fixed bug #37969 SYN packet dropped as short packet in + tcp_input function + + 2014-05-20: Simon Goldschmidt + * tcp_out.c: fixed bug #37184 tcp_write problem for pcbs in the SYN_SENT state + + 2014-05-19: Simon Goldschmidt + * *.h: Fixed bug #35874 reserved identifier violation (removed leading underscores + from header include guards) + + 2014-04-08: Simon Goldschmidt + * tcp.c: Fixed bug #36167 tcp server crash when client closes (maximum window) + + 2014-04-06: Simon Goldschmidt + * tcp_in.c: Fixed bug #36210 lwIP does not elicit an empty ACK when received + unacceptable ACK + + 2014-04-06: Simon Goldschmidt + * dhcp.c, ip4.c/.h, ip6.c/.h, udp.c/.h, ip.h: Fixed bug #41787 DHCP Discovery + is invalid when an IP is set to thet netif. + + 2014-03-14: Simon Goldschmidt + * tcp_out.c: Fixed bug #36153 TCP Cheksum error if LWIP_CHECKSUM_ON_COPY=1 + + 2014-03-11: Simon Goldschmidt (patch by Mason) + * opt.h, sockets.c: fixed bug #35928 BSD sockets functions must set errno for + POSIX-compliance + + 2014-02-27: Simon Goldschmidt + * dhcp.c: fixed bug #40303 DHCP xid renewed when sending a DHCPREQUEST + + 2014-02-27: Simon Goldschmidt + * raw.c: fixed bug #41680 raw socket can not receive IPv6 packet when + IP_SOF_BROADCAST_RECV==1 + + 2014-02-27: Simon Goldschmidt + * api_msg.c, sockets.c: fixed bug #38404 getpeeraddr returns success on + unconnected/listening TCP sockets + + 2014-02-27: Simon Goldschmidt + * sockets.c: fixed bug #41729 Some socket functions return Exyz instead of -1 + + 2014-02-25: Simon Goldschmidt + * ip4.c: fixed bug #39514 ip_route() may return an IPv6-only interface + + 2014-02-25: Simon Goldschmidt, patch by Fatih Asici + * pbuf.c: fixed bug #39356 Wrong increment in pbuf_memfind() + + 2014-02-25: Simon Goldschmidt + * netif.c/.h, udp.c: fixed bug #39225 udp.c uses netif_matches_ip6_addr() incorrectly; + renamed function netif_matches_ip6_addr() to netif_get_ip6_addr_match() + + 2014-02-25: Simon Goldschmidt + * igmp.c: fixed bug #39145 IGMP membership report for 224.0.0.1 + + 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) + * etharp.c, opt.h: fixed bug #34681 Limit ARP queue length by ARP_QUEUE_LEN (=3) + + 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) + * etharp.h/.c: fixed bug #34682 Limit ARP request flood for unresolved entry + + 2014-02-20: Simon Goldschmidt + * tcp_out.c: fixed bug #39683 Assertion "seg->tcphdr not aligned" failed with + MEM_ALIGNMENT = 8 + + 2014-02-20: Simon Goldschmidt + * sockets.c: fixed bug #39882 No function shall set errno to 0 + + 2014-02-20: Simon Goldschmidt + * mib_structs.c: fixed bug #40050 SNMP problem with MIB arrays > 255 + + 2014-02-20: Simon Goldschmidt + * api.h, sockets.c: fixed bug #41499 netconn::recv_avail can overflow + + 2014-01-08: Stathis Voukelatos + * memp_std.h: patch #7928 Fixed size calculation in MALLOC memory pool + creation macro + + 2014-01-18: Brian Fahs + * tcp_out.c: patch #8237: tcp_rexmit_rto fails to update pcb->unsent_oversize + when necessary + + 2014-01-17: Grant Erickson, Jay Logue, Simon Goldschmidt + * ipv6.c, netif.c: patch #7913 Enable Support for IPv6 Loopback + + 2014-01-16: Stathis Voukelatos + * netif.c: patch #7902 Fixed netif_poll() operation when LWIP_LOOPBACK_MAX_PBUFS > 0 + + 2014-01-14: "Freddie Chopin" + * snmp.h, mib2.c: fixed constness and spelling of sysdescr + + 2014-01-14: Simon Goldschmidt (patch by Thomas Faber) + * tcpip.c: patch #8241: Fix implicit declaration of ip_input with + LWIP_TCPIP_CORE_LOCKING_INPUT disabled + + 2014-01-14: chrysn + * timers.c: patch #8244 make timeouts usable reliably from outside of the + timeout routine + + 2014-01-10: Simon Goldschmidt + * ip_frag.c, ip6_frag.c: fixed bug #41041 Potential use-after-free in IPv6 reassembly + + 2014-01-10: Simon Goldschmidt + * memp.c: fixed bug #41188 Alignment error in memp_init() when MEMP_SEPARATE_POOLS==1 + + 2014-01-10: Simon Goldschmidt + * tcp.c: fixed bug #39898 tcp_fasttmr() possible lock due to infinte queue process loop + + 2013-06-29: Simon Goldschmidt + * inet.h, sockets.h: partially fixed bug #37585: IPv6 compatibility (in socket structs) + + 2013-06-29: Simon Goldschmidt + * inet6.h: bug #37585/task #12600: fixed struct in6_addr.s6_addr to conform to spec + + 2013-04-24: patch by Liam + * api_msg.c: patch #8008 Fix a potential null pointer dereference in assert + + 2013-04-24: Simon Goldschmidt + * igmp.c: fixed possible division by zero + + 2013-04-24: Simon Goldschmidt + * ip6.h, some ipv6 C files: fixed bug #38526 Coverity: Recursive Header Inclusion in ip6.h + + 2013-04-24: Simon Goldschmidt (patch by Emil Ljungdahl): + * netif.c: fixed bug #38586 netif_loop_output() "deadlocks" + + 2013-01-15: Simon Goldschmidt + * ip4.c: fixed bug #37665 ip_canforward operates on address in wrong byte order + + 2013-01-15: Simon Goldschmidt + * pbuf.h: fixed bug #38097 pbuf_free_ooseq() warning + + 2013-01-14: Simon Goldschmidt + * dns.c: fixed bug #37705 Possible memory corruption in DNS query + + 2013-01-11: Simon Goldschmidt + * raw.c: fixed bug #38066 Raw pcbs can alter packet without eating it + + 2012-08-22: Simon Goldschmidt + * memp.c: fixed bug #37166: memp_sanity check loops itself + + 2012-08-13: Simon Goldschmidt + * dhcp.c: fixed bug #36645: Calling dhcp_release before dhcp_start + dereferences NULL + + 2012-08-13: Simon Goldschmidt + * msg_out.c: fixed bug #36840 snmp_send_trap() NULL de-reference if traps + configured but no interfaces available + + 2012-08-13: Simon Goldschmidt + * dns.c: fixed bug #36899 DNS TTL 0 is cached for a long time + + 2012-05-11: Simon Goldschmidt (patch by Marty) + * memp.c: fixed bug #36412: memp.c does not compile when + MEMP_OVERFLOW_CHECK > zero and MEMP_SEPARATE_POOLS == 1 + + 2012-05-03: Simon Goldschmidt (patch by Sylvain Rochet) + * ppp.c: fixed bug #36283 (PPP struct used on header size computation and + not packed) + + 2012-05-03: Simon Goldschmidt (patch by David Empson) + * ppp.c: fixed bug #36388 (PPP: checksum-only in last pbuf leads to pbuf with + zero length) + + 2012-03-25: Simon Goldschmidt + * api_msg.c: Fixed bug #35817: do_connect() invalidly signals op_completed + for UDP/RAW with LWIP_TCPIP_CORE_LOCKING==1 + + 2012-03-25: Simon Goldschmidt + * api_msg.h, api_lib.c, api_msg.c, netifapi.c: fixed bug #35931: Name space + pollution in api_msg.c and netifapi.c + + 2011-08-24: Simon Goldschmidt + * inet6.h: fixed bug #34124 struct in6_addr does not conform to the standard + + + +(STABLE-1.4.1) + + ++ New features: + + 2012-03-25: Simon Goldschmidt (idea by Mason) + * posix/*: added posix-compatibility include files posix/netdb.h and posix/sys/socket.h + which are a simple wrapper to the correct lwIP include files. + + 2012-01-16: Simon Goldschmidt + * opt.h, icmp.c: Added option CHECKSUM_GEN_ICMP + + 2011-12-17: Simon Goldschmidt + * ip.h: implemented API functions to access so_options of IP pcbs (UDP, TCP, RAW) + (fixes bug #35061) + + 2011-09-27: Simon Goldschmidt + * opt.h, tcp.c, tcp_in.c: Implemented limiting data on ooseq queue (task #9989) + (define TCP_OOSEQ_MAX_BYTES / TCP_OOSEQ_MAX_PBUFS in lwipopts.h) + + 2011-09-21: Simon Goldschmidt + * opt.h, api.h, api_lib.c, api_msg.h/.c, sockets.c: Implemented timeout on + send (TCP only, bug #33820) + + 2011-09-21: Simon Goldschmidt + * init.c: Converted runtime-sanity-checks into compile-time checks that can + be disabled (since runtime checks can often not be seen on embedded targets) + + 2011-09-11: Simon Goldschmidt + * ppp.h, ppp_impl.h: splitted ppp.h to an internal and external header file + to get a clear separation of which functions an application or port may use + (task #11281) + + 2011-09-11: Simon Goldschmidt + * opt.h, tcp_impl.h, tcp.c, udp.h/.c: Added a config option to randomize + initial local TCP/UDP ports (so that different port ranges are used after + a reboot; bug #33818; this one added tcp_init/udp_init functions again) + + 2011-09-03: Simon Goldschmidt + * dhcp.c: DHCP uses LWIP_RAND() for xid's (bug #30302) + + 2011-08-24: Simon Goldschmidt + * opt.h, netif.h/.c: added netif remove callback (bug #32397) + + 2011-07-26: Simon Goldschmidt + * etharp.c: ETHARP_SUPPORT_VLAN: add support for an external VLAN filter + function instead of only checking for one VLAN (define ETHARP_VLAN_CHECK_FN) + + 2011-07-21: Simon Goldschmidt (patch by hanhui) + * ip4.c, etharp.c, pbuf.h: bug #33634 ip_forward() have a faulty behaviour: + Added pbuf flags to mark incoming packets as link-layer broadcast/multicast. + Also added code to allow ip_forward() to forward non-broadcast packets to + the input netif (set IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1). + + 2011-06-26: Simon Goldschmidt (patch by Cameron Gutman) + * tcp.c, tcp_out.c: bug #33604: added some more asserts to check that + pcb->state != LISTEN + + 2011-05-14: Simon Goldschmidt (patch by Stéphane Lesage) + * tcpip.c/.h: patch #7449 allow tcpip callback from interrupt with static + memory message + + + ++ Bugfixes: + + 2012-09-26: Simon Goldschmidt + * api_msg.c: fixed bug #37405 'err_tcp()' uses already freed 'netconn' object + + 2012-09-26: patch by Henrik Persson + * dhcp.c: patch #7843 Fix corner case with dhcp timeouts + + 2012-09-26: patch by Henrik Persson + * dhcp.c: patch #7840 Segfault in dhcp_parse_reply if no end marker in dhcp packet + + 2012-08-22: Simon Goldschmidt + * memp.c: fixed bug #37166: memp_sanity check loops itself + + 2012-05-08: Simon Goldschmidt + * tcp_out.c: fixed bug: #36380 unsent_oversize mismatch in 1.4.1RC1 (this was + a debug-check issue only) + + 2012-03-27: Simon Goldschmidt + * vj.c: fixed bug #35756 header length calculation problem in ppp/vj.c + + 2012-03-27: Simon Goldschmidt (patch by Mason) + * tcp_out.c: fixed bug #35945: SYN packet should provide the recv MSS not the + send MSS + + 2012-03-22: Simon Goldschmidt + * ip4.c: fixed bug #35927: missing refragmentaion in ip_forward + + 2012-03-20: Simon Goldschmidt (patch by Mason) + * netdb.c: fixed bug #35907: lwip_gethostbyname_r returns an invalid h_addr_list + + 2012-03-12: Simon Goldschmidt (patch by Bostjan Meglic) + * ppp.c: fixed bug #35809: PPP GetMask(): Compiler warning on big endian, + possible bug on little endian system + + 2012-02-23: Simon Goldschmidt + * etharp.c: fixed bug #35595: Impossible to send broadcast without a gateway + (introduced when fixing bug# 33551) + + 2012-02-16: Simon Goldschmidt + * ppp.c: fixed pbuf leak when PPP session is aborted through pppSigHUP() + (bug #35541: PPP Memory Leak) + + 2012-02-16: Simon Goldschmidt + * etharp.c: fixed bug #35531: Impossible to send multicast without a gateway + (introduced when fixing bug# 33551) + + 2012-02-16: Simon Goldschmidt (patch by Stéphane Lesage) + * msg_in.c, msg_out.c: fixed bug #35536 SNMP: error too big response is malformed + + 2012-02-15: Simon Goldschmidt + * init.c: fixed bug #35537: MEMP_NUM_* sanity checks should be disabled with + MEMP_MEM_MALLOC==1 + + 2012-02-12: Simon Goldschmidt + * tcp.h, tcp_in.c, tcp_out.c: partly fixed bug #25882: TCP hangs on + MSS > pcb->snd_wnd (by not creating segments bigger than half the window) + + 2012-02-11: Simon Goldschmidt + * tcp.c: fixed bug #35435: No pcb state check before adding it to time-wait + queue while closing + + 2012-01-22: Simon Goldschmidt + * tcp.c, tcp_in.c: fixed bug #35305: pcb may be freed too early on shutdown(WR) + + 2012-01-21: Simon Goldschmidt + * tcp.c: fixed bug #34636: FIN_WAIT_2 - Incorrect shutdown of TCP pcb + + 2012-01-20: Simon Goldschmidt + * dhcp.c: fixed bug #35151: DHCP asserts on incoming option lengths + + 2012-01-20: Simon Goldschmidt + * pbuf.c: fixed bug #35291: NULL pointer in pbuf_copy + + 2011-11-25: Simon Goldschmidt + * tcp.h/.c, tcp_impl.h, tcp_in.c: fixed bug #31177: tcp timers can corrupt + tcp_active_pcbs in some cases + + 2011-11-23: Simon Goldschmidt + * sys.c: fixed bug #34884: sys_msleep() body needs to be surrounded with + '#ifndef sys_msleep' + + 2011-11-22: Simon Goldschmidt + * netif.c, etharp.h/.c: fixed bug #34684: Clear the arp table cache when + netif is brought down + + 2011-10-28: Simon Goldschmidt + * tcp_in.c: fixed bug #34638: Dead code in tcp_receive - pcb->dupacks + + 2011-10-23: Simon Goldschmidt + * mem.c: fixed bug #34429: possible memory corruption with + LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT set to 1 + + 2011-10-18: Simon Goldschmidt + * arch.h, netdb.c: fixed bug #34592: lwip_gethostbyname_r uses nonstandard + error value + + 2011-10-18: Simon Goldschmidt + * opt.h: fixed default values of TCP_SNDLOWAT and TCP_SNDQUEUELOWAT for small + windows (bug #34176 select after non-blocking send times out) + + 2011-10-18: Simon Goldschmidt + * tcp_impl.h, tcp_out.c: fixed bug #34587: TCP_BUILD_MSS_OPTION doesn't + consider netif->mtu, causes slow network + + 2011-10-18: Simon Goldschmidt + * sockets.c: fixed bug #34581 missing parentheses in udplite sockets code + + 2011-10-18: Simon Goldschmidt + * sockets.h: fixed bug #34580 fcntl() is missing in LWIP_COMPAT_SOCKETS + + 2011-10-17: Simon Goldschmidt + * api_msg.c: fixed bug #34569: shutdown(SHUT_WR) crashes netconn/socket api + + 2011-10-13: Simon Goldschmidt + * tcp_in.c, tcp_out.c: fixed bug #34517 (persist timer is started although no + zero window is received) by starting the persist timer when a zero window is + received, not when we have more data queued for sending than fits into the + window + + 2011-10-13: Simon Goldschmidt + * def.h, timers.c: fixed bug #34541: LWIP_U32_DIFF is unnecessarily complex + + 2011-10-13: Simon Goldschmidt + * sockets.c, api_lib.c: fixed bug #34540: compiler error when CORE_LOCKING is + used and not all protocols are enabled + + 2011-10-12: Simon Goldschmidt + * pbuf.c: fixed bug #34534: Error in sending fragmented IP if MEM_ALIGNMENT > 4 + + 2011-10-09: Simon Goldschmidt + * tcp_out.c: fixed bug #34426: tcp_zero_window_probe() transmits incorrect + byte value when pcb->unacked != NULL + + 2011-10-09: Simon Goldschmidt + * ip4.c: fixed bug #34447 LWIP_IP_ACCEPT_UDP_PORT(dst_port) wrong + + 2011-09-27: Simon Goldschmidt + * tcp_in.c, tcp_out.c: Reset pcb->unsent_oversize in 2 more places... + + 2011-09-27: Simon Goldschmidt + * tcp_in.c: fixed bug #28288: Data after FIN in oos queue + + 2011-09-27: Simon Goldschmidt + * dhcp.c: fixed bug #34406 dhcp_option_hostname() can overflow the pbuf + + 2011-09-24: Simon Goldschmidt + * mem.h: fixed bug #34377 MEM_SIZE_F is not defined if MEM_LIBC_MALLOC==1 + + 2011-09-23: Simon Goldschmidt + * pbuf.h, tcp.c, tcp_in.c: fixed bug #33871: rejecting TCP_EVENT_RECV() for + the last packet including FIN can lose data + + 2011-09-22: Simon Goldschmidt + * tcp_impl.h: fixed bug #34355: nagle does not take snd_buf/snd_queuelen into + account + + 2011-09-21: Simon Goldschmidt + * opt.h: fixed default value of TCP_SND_BUF to not violate the sanity checks + in init.c + + 2011-09-20: Simon Goldschmidt + * timers.c: fixed bug #34337 (possible NULL pointer in sys_check_timeouts) + + 2011-09-11: Simon Goldschmidt + * tcp_out.c: use pcb->mss instead of TCP_MSS for preallocate mss-sized pbufs + (bug #34019) + + 2011-09-09: Simon Goldschmidt + * udp.c: fixed bug #34072: UDP broadcast is received from wrong UDP pcb if + udp port matches + + 2011-09-03: Simon Goldschmidt + * tcp_in.c: fixed bug #33952 PUSH flag in incoming packet is lost when packet + is aggregated and sent to application + + 2011-09-01: Simon Goldschmidt + * opt.h: fixed bug #31809 LWIP_EVENT_API in opts.h is inconsistent compared + to other options + + 2011-09-01: Simon Goldschmidt + * tcp_in.c: fixed bug #34111 RST for ACK to listening pcb has wrong seqno + + 2011-08-24: Simon Goldschmidt + * api_msg.c, sockets.c: fixed bug #33956 Wrong error returned when calling + accept() on UDP connections + + 2011-08-24: Simon Goldschmidt + * sockets.h: fixed bug #34057 socklen_t should be a typedef + + 2011-08-24: Simon Goldschmidt + * pbuf.c: fixed bug #34112 Odd check in pbuf_alloced_custom (typo) + + 2011-08-24: Simon Goldschmidt + * dhcp.c: fixed bug #34122 dhcp: hostname can overflow + + 2011-08-24: Simon Goldschmidt + * netif.c: fixed bug #34121 netif_add/netif_set_ipaddr fail on NULL ipaddr + + 2011-08-22: Simon Goldschmidt + * tcp_out.c: fixed bug #33962 TF_FIN not always set after FIN is sent. (This + merely prevents nagle from not transmitting fast after closing.) + + 2011-07-22: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, api.h: fixed bug #31084 (socket API returns + always EMSGSIZE on non-blocking sockets if data size > send buffers) -> now + lwip_send() sends as much as possible for non-blocking sockets + + 2011-07-22: Simon Goldschmidt + * pbuf.c/.h, timers.c: freeing ooseq pbufs when the pbuf pool is empty implemented + for NO_SYS==1: when not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() + at regular intervals from main level. + + 2011-07-21: Simon Goldschmidt + * etharp.c: fixed bug #33551 (ARP entries may time out although in use) by + sending an ARP request when an ARP entry is used in the last minute before + it would time out. + + 2011-07-04: Simon Goldschmidt + * sys_arch.txt: Fixed documentation after changing sys arch prototypes for 1.4.0. + + 2011-06-26: Simon Goldschmidt + * tcp.c: fixed bug #31723 (tcp_kill_prio() kills pcbs with the same prio) by + updating its documentation only. + + 2011-06-26: Simon Goldschmidt + * mem.c: fixed bug #33545: With MEM_USE_POOLS==1, mem_malloc can return an + unaligned pointer. + + 2011-06-26: Simon Goldschmidt + * mem.c: fixed bug #33544 "warning in mem.c in lwip 1.4.0 with NO_SYS=1" + + 2011-05-25: Simon Goldschmidt + * tcp.c: fixed bug #33398 (pointless conversion when checking TCP port range) + + + +(STABLE-1.4.0) + + ++ New features: + + 2011-03-27: Simon Goldschmidt + * tcp_impl.h, tcp_in.c, tcp_out.c: Removed 'dataptr' from 'struct tcp_seg' and + calculate it in tcp_zero_window_probe (the only place where it was used). + + 2010-11-21: Simon Goldschmidt + * dhcp.c/.h: Added a function to deallocate the struct dhcp from a netif + (fixes bug #31525). + + 2010-07-12: Simon Goldschmidt (patch by Stephane Lesage) + * ip.c, udp.c/.h, pbuf.h, sockets.c: task #10495: Added support for + IP_MULTICAST_LOOP at socket- and raw-API level. + + 2010-06-16: Simon Goldschmidt + * ip.c: Added an optional define (LWIP_IP_ACCEPT_UDP_PORT) that can allow + link-layer-addressed UDP traffic to be received while a netif is down (just + like DHCP during configuration) + + 2010-05-22: Simon Goldschmidt + * many many files: bug #27352: removed packing from ip_addr_t, the packed + version is now only used in protocol headers. Added global storage for + current src/dest IP address while in input functions. + + 2010-05-16: Simon Goldschmidt + * def.h: task #10391: Add preprocessor-macros for compile-time htonl + calculation (and use them throughout the stack where applicable) + + 2010-05-16: Simon Goldschmidt + * opt.h, memp_std.h, memp.c, ppp_oe.h/.c: PPPoE now uses its own MEMP pool + instead of the heap (moved struct pppoe_softc from ppp_oe.c to ppp_oe.h) + + 2010-05-16: Simon Goldschmidt + * opt.h, memp_std.h, dns.h/.c: DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses its own + MEMP pool instead of the heap + + 2010-05-13: Simon Goldschmidt + * tcp.c, udp.c: task #6995: Implement SO_REUSEADDR (correctly), added + new option SO_REUSE_RXTOALL to pass received UDP broadcast/multicast + packets to more than one pcb. + + 2010-05-02: Simon Goldschmidt + * netbuf.h/.c, sockets.c, api_msg.c: use checksum-on-copy for sending + UDP data for LWIP_NETIF_TX_SINGLE_PBUF==1 + + 2010-04-30: Simon Goldschmidt + * udp.h/.c, pbuf.h/.c: task #6849: added udp_send(_to/_if) functions that + take a precalculated checksum, added pbuf_fill_chksum() to copy data + into a pbuf and at the same time calculating the checksum for that data + + 2010-04-29: Simon Goldschmidt + * ip_addr.h, etharp.h/.c, autoip.c: Create overridable macros for copying + 2-byte-aligned IP addresses and MAC addresses + + 2010-04-28: Patch by Bill Auerbach + * ip.c: Inline generating IP checksum to save a function call + + 2010-04-14: Simon Goldschmidt + * tcpip.h/.c, timers.c: Added an overridable define to get informed when the + tcpip_thread processes messages or timeouts to implement a watchdog. + + 2010-03-28: Simon Goldschmidt + * ip_frag.c: create a new (contiguous) PBUF_RAM for every outgoing + fragment if LWIP_NETIF_TX_SINGLE_PBUF==1 + + 2010-03-27: Simon Goldschmidt + * etharp.c: Speedup TX by moving code from find_entry to etharp_output/ + etharp_query to prevent unnecessary function calls (inspired by + patch #7135). + + 2010-03-20: Simon Goldschmidt + * opt.h, tcpip.c/.h: Added an option to disable tcpip_(un)timeout code + since the linker cannot do this automatically to save space. + + 2010-03-20: Simon Goldschmidt + * opt.h, etharp.c/.h: Added support for static ARP table entries + + 2010-03-14: Simon Goldschmidt + * tcp_impl.h, tcp_out.c, inet_chksum.h/.c: task #6849: Calculate checksum + when creating TCP segments, not when (re-)transmitting them. + + 2010-03-07: Simon Goldschmidt + * sockets.c: bug #28775 (select/event_callback: only check select_cb_list + on change) plus use SYS_LIGHTWEIGHT_PROT to protect the select code. + This should speed up receiving data on sockets as the select code in + event_callback is only executed when select is waiting. + + 2010-03-06: Simon Goldschmidt + * tcp_out.c: task #7013 (Create option to have all packets delivered to + netif->output in one piece): Always copy to try to create single pbufs + in tcp_write. + + 2010-03-06: Simon Goldschmidt + * api.h, api_lib.c, sockets.c: task #10167 (sockets: speed up TCP recv + by not allocating a netbuf): added function netconn_recv_tcp_pbuf() + for tcp netconns to receive pbufs, not netbufs; use that function + for tcp sockets. + + 2010-03-05: Jakob Ole Stoklundsen / Simon Goldschmidt + * opt.h, tcp.h, tcp_impl.h, tcp.c, tcp_in.c, tcp_out.c: task #7040: + Work on tcp_enqueue: Don't waste memory when chaining segments, + added option TCP_OVERSIZE to prevent creating many small pbufs when + calling tcp_write with many small blocks of data. Instead, pbufs are + allocated larger than needed and the space is used for later calls to + tcp_write. + + 2010-02-21: Simon Goldschmidt + * stats.c/.h: Added const char* name to mem- and memp-stats for easier + debugging. + + 2010-02-21: Simon Goldschmidt + * tcp.h (and usages), added tcp_impl.h: Splitted API and internal + implementation of tcp to make API usage cleare to application programmers + + 2010-02-14: Simon Goldschmidt/Stephane Lesage + * ip_addr.h: Improved some defines working on ip addresses, added faster + macro to copy addresses that cannot be NULL + + 2010-02-13: Simon Goldschmidt + * api.h, api_lib.c, api_msg.c, sockets.c: task #7865 (implement non- + blocking send operation) + + 2010-02-12: Simon Goldschmidt + * sockets.c/.h: Added a minimal version of posix fctl() to have a + standardised way to set O_NONBLOCK for nonblocking sockets. + + 2010-02-12: Simon Goldschmidt + * dhcp.c/.h, autoip.c/.h: task #10139 (Prefer statically allocated + memory): added autoip_set_struct() and dhcp_set_struct() to let autoip + and dhcp work with user-allocated structs instead of callin mem_malloc + + 2010-02-12: Simon Goldschmidt/Jeff Barber + * tcp.c/h: patch #6865 (SO_REUSEADDR for TCP): if pcb.so_options has + SOF_REUSEADDR set, allow binding to endpoint in TIME_WAIT + + 2010-02-12: Simon Goldschmidt + * sys layer: task #10139 (Prefer statically allocated memory): converted + mbox and semaphore functions to take pointers to sys_mbox_t/sys_sem_t; + converted sys_mbox_new/sys_sem_new to take pointers and return err_t; + task #7212: Add Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX + to let sys.h use binary semaphores instead of mutexes - as before) + + 2010-02-09: Simon Goldschmidt (Simon Kallweit) + * timers.c/.h: Added function sys_restart_timeouts() from patch #7085 + (Restart system timeout handling) + + 2010-02-09: Simon Goldschmidt + * netif.c/.h, removed loopif.c/.h: task #10153 (Integrate loopif into + netif.c) - loopif does not have to be created by the port any more, + just define LWIP_HAVE_LOOPIF to 1. + + 2010-02-08: Simon Goldschmidt + * inet.h, ip_addr.c/.h: Added reentrant versions of inet_ntoa/ipaddr_ntoa + inet_ntoa_r/ipaddr_ntoa_r + + 2010-02-08: Simon Goldschmidt + * netif.h: Added netif_s/get_igmp_mac_filter() macros + + 2010-02-05: Simon Goldschmidt + * netif.h: Added function-like macros to get/set the hostname on a netif + + 2010-02-04: Simon Goldschmidt + * nearly every file: Replaced struct ip_addr by typedef ip_addr_t to + make changing the actual implementation behind the typedef easier. + + 2010-02-01: Simon Goldschmidt + * opt.h, memp_std.h, dns.h, netdb.c, memp.c: Let netdb use a memp pool + for allocating memory when getaddrinfo() is called. + + 2010-01-31: Simon Goldschmidt + * dhcp.h, dhcp.c: Reworked the code that parses DHCP options: parse + them once instead of parsing for every option. This also removes + the need for mem_malloc from dhcp_recv and makes it possible to + correctly retrieve the BOOTP file. + + 2010-01-30: simon Goldschmidt + * sockets.c: Use SYS_LIGHTWEIGHT_PROT instead of a semaphore to protect + the sockets array. + + 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) + * api.h, api_msg.c, sockets.c: Added except set support in select + (patch #6860) + + 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) + * api.h, sockets.h, err.h, api_lib.c, api_msg.c, sockets.c, err.c: + Add non-blocking support for connect (partly from patch #6860), + plus many cleanups in socket & netconn API. + + 2010-01-27: Simon Goldschmidt + * opt.h, tcp.h, init.c, api_msg.c: Added TCP_SNDQUEUELOWAT corresponding + to TCP_SNDLOWAT and added tcp_sndqueuelen() - this fixes bug #28605 + + 2010-01-26: Simon Goldschmidt + * snmp: Use memp pools for snmp instead of the heap; added 4 new pools. + + 2010-01-14: Simon Goldschmidt + * ppp.c/.h: Fixed bug #27856: PPP: Set netif link- and status-callback + by adding ppp_set_netif_statuscallback()/ppp_set_netif_linkcallback() + + 2010-01-13: Simon Goldschmidt + * mem.c: The heap now may be moved to user-defined memory by defining + LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address + (patch #6966 and bug #26133) + + 2010-01-10: Simon Goldschmidt (Bill Auerbach) + * opt.h, memp.c: patch #6822 (Add option to place memory pools in + separate arrays) + + 2010-01-10: Simon Goldschmidt + * init.c, igmp.c: patch #6463 (IGMP - Adding Random Delay): added define + LWIP_RAND() for lwip-wide randomization (to be defined in cc.h) + + 2009-12-31: Simon Goldschmidt + * tcpip.c, init.c, memp.c, sys.c, memp_std.h, sys.h, tcpip.h + added timers.c/.h: Separated timer implementation from semaphore/mbox + implementation, moved timer implementation to timers.c/.h, timers are + now only called from tcpip_thread or by explicitly checking them. + (TASK#7235) + + 2009-12-27: Simon Goldschmidt + * opt.h, etharp.h/.c, init.c, tcpip.c: Added an additional option + LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE) + + + ++ Bugfixes: + + 2011-04-20: Simon Goldschmidt + * sys_arch.txt: sys_arch_timeouts() is not needed any more. + + 2011-04-13: Simon Goldschmidt + * tcp.c, udp.c: Fixed bug #33048 (Bad range for IP source port numbers) by + using ports in the IANA private/dynamic range (49152 through 65535). + + 2011-03-29: Simon Goldschmidt, patch by Emil Lhungdahl: + * etharp.h/.c: Fixed broken VLAN support. + + 2011-03-27: Simon Goldschmidt + * tcp.c: Fixed bug #32926 (TCP_RMV(&tcp_bound_pcbs) is called on unbound tcp + pcbs) by checking if the pcb was bound (local_port != 0). + + 2011-03-27: Simon Goldschmidt + * ppp.c: Fixed bug #32280 (ppp: a pbuf is freed twice) + + 2011-03-27: Simon Goldschmidt + * sockets.c: Fixed bug #32906: lwip_connect+lwip_send did not work for udp and + raw pcbs with LWIP_TCPIP_CORE_LOCKING==1. + + 2011-03-27: Simon Goldschmidt + * tcp_out.c: Fixed bug #32820 (Outgoing TCP connections created before route + is present never times out) by starting retransmission timer before checking + route. + + 2011-03-22: Simon Goldschmidt + * ppp.c: Fixed bug #32648 (PPP code crashes when terminating a link) by only + calling sio_read_abort() if the file descriptor is valid. + + 2011-03-14: Simon Goldschmidt + * err.h/.c, sockets.c, api_msg.c: fixed bug #31748 (Calling non-blocking connect + more than once can render a socket useless) since it mainly involves changing + "FATAL" classification of error codes: ERR_USE and ERR_ISCONN just aren't fatal. + + 2011-03-13: Simon Goldschmidt + * sockets.c: fixed bug #32769 (ESHUTDOWN is linux-specific) by fixing + err_to_errno_table (ERR_CLSD: ENOTCONN instead of ESHUTDOWN), ERR_ISCONN: + use EALRADY instead of -1 + + 2011-03-13: Simon Goldschmidt + * api_lib.c: netconn_accept: return ERR_ABRT instead of ERR_CLSD if the + connection has been aborted by err_tcp (since this is not a normal closing + procedure). + + 2011-03-13: Simon Goldschmidt + * tcp.c: tcp_bind: return ERR_VAL instead of ERR_ISCONN when trying to bind + with pcb->state != CLOSED + + 2011-02-17: Simon Goldschmidt + * rawapi.txt: Fixed bug #32561 tcp_poll argument definition out-of-order in + documentation + + 2011-02-17: Simon Goldschmidt + * many files: Added missing U/UL modifiers to fix 16-bit-arch portability. + + 2011-01-24: Simon Goldschmidt + * sockets.c: Fixed bug #31741: lwip_select seems to have threading problems + + 2010-12-02: Simon Goldschmidt + * err.h: Fixed ERR_IS_FATAL so that ERR_WOULDBLOCK is not fatal. + + 2010-11-23: Simon Goldschmidt + * api.h, api_lib.c, api_msg.c, sockets.c: netconn.recv_avail is only used for + LWIP_SO_RCVBUF and ioctl/FIONREAD. + + 2010-11-23: Simon Goldschmidt + * etharp.c: Fixed bug #31720: ARP-queueing: RFC 1122 recommends to queue at + least 1 packet -> ARP_QUEUEING==0 now queues the most recent packet. + + 2010-11-23: Simon Goldschmidt + * tcp_in.c: Fixed bug #30577: tcp_input: don't discard ACK-only packets after + refusing 'refused_data' again. + + 2010-11-22: Simon Goldschmidt + * sockets.c: Fixed bug #31590: getsockopt(... SO_ERROR ...) gives EINPROGRESS + after a successful nonblocking connection. + + 2010-11-22: Simon Goldschmidt + * etharp.c: Fixed bug #31722: IP packets sent with an AutoIP source addr + must be sent link-local + + 2010-11-22: Simon Goldschmidt + * timers.c: patch #7329: tcp_timer_needed prototype was ifdef'ed out for + LWIP_TIMERS==0 + + 2010-11-20: Simon Goldschmidt + * sockets.c: Fixed bug #31170: lwip_setsockopt() does not set socket number + + 2010-11-20: Simon Goldschmidt + * sockets.h: Fixed bug #31304: Changed SHUT_RD, SHUT_WR and SHUT_RDWR to + resemble other stacks. + + 2010-11-20: Simon Goldschmidt + * dns.c: Fixed bug #31535: TCP_SND_QUEUELEN must be at least 2 or else + no-copy TCP writes will never succeed. + + 2010-11-20: Simon Goldschmidt + * dns.c: Fixed bug #31701: Error return value from dns_gethostbyname() does + not match documentation: return ERR_ARG instead of ERR_VAL if not + initialized or wrong argument. + + 2010-10-20: Simon Goldschmidt + * sockets.h: Fixed bug #31385: sizeof(struct sockaddr) is 30 but should be 16 + + 2010-10-05: Simon Goldschmidt + * dhcp.c: Once again fixed #30038: DHCP/AutoIP cooperation failed when + replugging the network cable after an AutoIP address was assigned. + + 2010-08-10: Simon Goldschmidt + * tcp.c: Fixed bug #30728: tcp_new_port() did not check listen pcbs + + 2010-08-03: Simon Goldschmidt + * udp.c, raw.c: Don't chain empty pbufs when sending them (fixes bug #30625) + + 2010-08-01: Simon Goldschmidt (patch by Greg Renda) + * ppp.c: Applied patch #7264 (PPP protocols are rejected incorrectly on big + endian architectures) + + 2010-07-28: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, mib2.c: Fixed compilation with TCP or UDP + disabled. + + 2010-07-27: Simon Goldschmidt + * tcp.c: Fixed bug #30565 (tcp_connect() check bound list): that check did no + harm but never did anything + + 2010-07-21: Simon Goldschmidt + * ip.c: Fixed invalid fix for bug #30402 (CHECKSUM_GEN_IP_INLINE does not + add IP options) + + 2010-07-16: Kieran Mansley + * msg_in.c: Fixed SNMP ASN constant defines to not use ! operator + + 2010-07-10: Simon Goldschmidt + * ip.c: Fixed bug #30402: CHECKSUM_GEN_IP_INLINE does not add IP options + + 2010-06-30: Simon Goldschmidt + * api_msg.c: fixed bug #30300 (shutdown parameter was not initialized in + netconn_delete) + + 2010-06-28: Kieran Mansley + * timers.c remove unportable printing of C function pointers + + 2010-06-24: Simon Goldschmidt + * init.c, timers.c/.h, opt.h, memp_std.h: From patch #7221: added flag + NO_SYS_NO_TIMERS to drop timer support for NO_SYS==1 for easier upgrading + + 2010-06-24: Simon Goldschmidt + * api(_lib).c/.h, api_msg.c/.h, sockets.c/.h: Fixed bug #10088: Correctly + implemented shutdown at socket level. + + 2010-06-21: Simon Goldschmidt + * pbuf.c/.h, ip_frag.c/.h, opt.h, memp_std.h: Fixed bug #29361 (ip_frag has + problems with zero-copy DMA MACs) by adding custom pbufs and implementing + custom pbufs that reference other (original) pbufs. Additionally set + IP_FRAG_USES_STATIC_BUF=0 as default to be on the safe side. + + 2010-06-15: Simon Goldschmidt + * dhcp.c: Fixed bug #29970: DHCP endian issue parsing option responses + + 2010-06-14: Simon Goldschmidt + * autoip.c: Fixed bug #30039: AutoIP does not reuse previous addresses + + 2010-06-12: Simon Goldschmidt + * dhcp.c: Fixed bug #30038: dhcp_network_changed doesn't reset AUTOIP coop + state + + 2010-05-17: Simon Goldschmidt + * netdb.c: Correctly NULL-terminate h_addr_list + + 2010-05-16: Simon Goldschmidt + * def.h/.c: changed the semantics of LWIP_PREFIX_BYTEORDER_FUNCS to prevent + "symbol already defined" i.e. when linking to winsock + + 2010-05-05: Simon Goldschmidt + * def.h, timers.c: Fixed bug #29769 (sys_check_timeouts: sys_now() may + overflow) + + 2010-04-21: Simon Goldschmidt + * api_msg.c: Fixed bug #29617 (sometime cause stall on delete listening + connection) + + 2010-03-28: Luca Ceresoli + * ip_addr.c/.h: patch #7143: Add a few missing const qualifiers + + 2010-03-27: Luca Ceresoli + * mib2.c: patch #7130: remove meaningless const qualifiers + + 2010-03-26: Simon Goldschmidt + * tcp_out.c: Make LWIP_NETIF_TX_SINGLE_PBUF work for TCP, too + + 2010-03-26: Simon Goldschmidt + * various files: Fixed compiling with different options disabled (TCP/UDP), + triggered by bug #29345; don't allocate acceptmbox if LWIP_TCP is disabled + + 2010-03-25: Simon Goldschmidt + * sockets.c: Fixed bug #29332: lwip_select() processes readset incorrectly + + 2010-03-25: Simon Goldschmidt + * tcp_in.c, test_tcp_oos.c: Fixed bug #29080: Correctly handle remote side + overrunning our rcv_wnd in ooseq case. + + 2010-03-22: Simon Goldschmidt + * tcp.c: tcp_listen() did not copy the pcb's prio. + + 2010-03-19: Simon Goldschmidt + * snmp_msg.c: Fixed bug #29256: SNMP Trap address was not correctly set + + 2010-03-14: Simon Goldschmidt + * opt.h, etharp.h: Fixed bug #29148 (Incorrect PBUF_POOL_BUFSIZE for ports + where ETH_PAD_SIZE > 0) by moving definition of ETH_PAD_SIZE to opt.h + and basing PBUF_LINK_HLEN on it. + + 2010-03-08: Simon Goldschmidt + * netif.c, ipv4/ip.c: task #10241 (AutoIP: don't break existing connections + when assiging routable address): when checking incoming packets and + aborting existing connection on address change, filter out link-local + addresses. + + 2010-03-06: Simon Goldschmidt + * sockets.c: Fixed LWIP_NETIF_TX_SINGLE_PBUF for LWIP_TCPIP_CORE_LOCKING + + 2010-03-06: Simon Goldschmidt + * ipv4/ip.c: Don't try to forward link-local addresses + + 2010-03-06: Simon Goldschmidt + * etharp.c: Fixed bug #29087: etharp: don't send packets for LinkLocal- + addresses to gw + + 2010-03-05: Simon Goldschmidt + * dhcp.c: Fixed bug #29072: Correctly set ciaddr based on message-type + and state. + + 2010-03-05: Simon Goldschmidt + * api_msg.c: Correctly set TCP_WRITE_FLAG_MORE when netconn_write is split + into multiple calls to tcp_write. + + 2010-02-21: Simon Goldschmidt + * opt.h, mem.h, dns.c: task #10140: Remove DNS_USES_STATIC_BUF (keep + the implementation of DNS_USES_STATIC_BUF==1) + + 2010-02-20: Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Task #10088: Correctly implement + close() vs. shutdown(). Now the application does not get any more + recv callbacks after calling tcp_close(). Added tcp_shutdown(). + + 2010-02-19: Simon Goldschmidt + * mem.c/.h, pbuf.c: Renamed mem_realloc() to mem_trim() to prevent + confusion with realloc() + + 2010-02-15: Simon Goldschmidt/Stephane Lesage + * netif.c/.h: Link status does not depend on LWIP_NETIF_LINK_CALLBACK + (fixes bug #28899) + + 2010-02-14: Simon Goldschmidt + * netif.c: Fixed bug #28877 (Duplicate ARP gratuitous packet with + LWIP_NETIF_LINK_CALLBACK set on) by only sending if both link- and + admin-status of a netif are up + + 2010-02-14: Simon Goldschmidt + * opt.h: Disable ETHARP_TRUST_IP_MAC by default since it slows down packet + reception and is not really necessary + + 2010-02-14: Simon Goldschmidt + * etharp.c/.h: Fixed ARP input processing: only add a new entry if a + request was directed as us (RFC 826, Packet Reception), otherwise + only update existing entries; internalized some functions + + 2010-02-14: Simon Goldschmidt + * netif.h, etharp.c, tcpip.c: Fixed bug #28183 (ARP and TCP/IP cannot be + disabled on netif used for PPPoE) by adding a new netif flag + (NETIF_FLAG_ETHERNET) that tells the stack the device is an ethernet + device but prevents usage of ARP (so that ethernet_input can be used + for PPPoE). + + 2010-02-12: Simon Goldschmidt + * netif.c: netif_set_link_up/down: only do something if the link state + actually changes + + 2010-02-12: Simon Goldschmidt/Stephane Lesage + * api_msg.c: Fixed bug #28865 (Cannot close socket/netconn in non-blocking + connect) + + 2010-02-12: Simon Goldschmidt + * mem.h: Fixed bug #28866 (mem_realloc function defined in mem.h) + + 2010-02-09: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, api.h, api_msg.h: Fixed bug #22110 + (recv() makes receive window update for data that wasn't received by + application) + + 2010-02-09: Simon Goldschmidt/Stephane Lesage + * sockets.c: Fixed bug #28853 (lwip_recvfrom() returns 0 on receive time-out + or any netconn_recv() error) + + 2010-02-09: Simon Goldschmidt + * ppp.c: task #10154 (PPP: Update snmp in/out counters for tx/rx packets) + + 2010-02-09: Simon Goldschmidt + * netif.c: For loopback packets, adjust the stats- and snmp-counters + for the loopback netif. + + 2010-02-08: Simon Goldschmidt + * igmp.c/.h, ip.h: Moved most defines from igmp.h to igmp.c for clarity + since they are not used anywhere else. + + 2010-02-08: Simon Goldschmidt (Stéphane Lesage) + * igmp.c, igmp.h, stats.c, stats.h: Improved IGMP stats + (patch from bug #28798) + + 2010-02-08: Simon Goldschmidt (Stéphane Lesage) + * igmp.c: Fixed bug #28798 (Error in "Max Response Time" processing) and + another bug when LWIP_RAND() returns zero. + + 2010-02-04: Simon Goldschmidt + * nearly every file: Use macros defined in ip_addr.h (some of them new) + to work with IP addresses (preparation for bug #27352 - Change ip_addr + from struct to typedef (u32_t) - and better code). + + 2010-01-31: Simon Goldschmidt + * netif.c: Don't call the link-callback from netif_set_up/down() since + this invalidly retriggers DHCP. + + 2010-01-29: Simon Goldschmidt + * ip_addr.h, inet.h, def.h, inet.c, def.c, more: Cleanly separate the + portability file inet.h and its contents from the stack: moved htonX- + functions to def.h (and the new def.c - they are not ipv4 dependent), + let inet.h depend on ip_addr.h and not the other way round. + This fixes bug #28732. + + 2010-01-28: Kieran Mansley + * tcp.c: Ensure ssthresh >= 2*MSS + + 2010-01-27: Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c: Fixed bug #27871: Calling tcp_abort() in recv + callback can lead to accessing unallocated memory. As a consequence, + ERR_ABRT means the application has called tcp_abort()! + + 2010-01-25: Simon Goldschmidt + * snmp_structs.h, msg_in.c: Partly fixed bug #22070 (MIB_OBJECT_WRITE_ONLY + not implemented in SNMP): write-only or not-accessible are still + returned by getnext (though not by get) + + 2010-01-24: Simon Goldschmidt + * snmp: Renamed the private mib node from 'private' to 'mib_private' to + not use reserved C/C++ keywords + + 2010-01-23: Simon Goldschmidt + * sockets.c: Fixed bug #28716: select() returns 0 after waiting for less + than 1 ms + + 2010-01-21: Simon Goldschmidt + * tcp.c, api_msg.c: Fixed bug #28651 (tcp_connect: no callbacks called + if tcp_enqueue fails) both in raw- and netconn-API + + 2010-01-19: Simon Goldschmidt + * api_msg.c: Fixed bug #27316: netconn: Possible deadlock in err_tcp + + 2010-01-18: Iordan Neshev/Simon Goldschmidt + * src/netif/ppp: reorganised PPP sourcecode to 2.3.11 including some + bugfix backports from 2.4.x. + + 2010-01-18: Simon Goldschmidt + * mem.c: Fixed bug #28679: mem_realloc calculates mem_stats wrong + + 2010-01-17: Simon Goldschmidt + * api_lib.c, api_msg.c, (api_msg.h, api.h, sockets.c, tcpip.c): + task #10102: "netconn: clean up conn->err threading issues" by adding + error return value to struct api_msg_msg + + 2010-01-17: Simon Goldschmidt + * api.h, api_lib.c, sockets.c: Changed netconn_recv() and netconn_accept() + to return err_t (bugs #27709 and #28087) + + 2010-01-14: Simon Goldschmidt + * ...: Use typedef for function prototypes throughout the stack. + + 2010-01-13: Simon Goldschmidt + * api_msg.h/.c, api_lib.c: Fixed bug #26672 (close connection when receive + window = 0) by correctly draining recvmbox/acceptmbox + + 2010-01-11: Simon Goldschmidt + * pap.c: Fixed bug #13315 (PPP PAP authentication can result in + erroneous callbacks) by copying the code from recent pppd + + 2010-01-10: Simon Goldschmidt + * raw.c: Fixed bug #28506 (raw_bind should filter received packets) + + 2010-01-10: Simon Goldschmidt + * tcp.h/.c: bug #28127 (remove call to tcp_output() from tcp_ack(_now)()) + + 2010-01-08: Simon Goldschmidt + * sockets.c: Fixed bug #28519 (lwip_recvfrom bug with len > 65535) + + 2010-01-08: Simon Goldschmidt + * dns.c: Copy hostname for DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1 since string + passed to dns_local_addhost() might be volatile + + 2010-01-07: Simon Goldschmidt + * timers.c, tcp.h: Call tcp_timer_needed() with NO_SYS==1, too + + 2010-01-06: Simon Goldschmidt + * netdb.h: Fixed bug #28496: missing include guards in netdb.h + + 2009-12-31: Simon Goldschmidt + * many ppp files: Reorganised PPP source code from ucip structure to pppd + structure to easily compare our code against the pppd code (around v2.3.1) + + 2009-12-27: Simon Goldschmidt + * tcp_in.c: Another fix for bug #28241 (ooseq processing) and adapted + unit test + (STABLE-1.3.2) @@ -157,7 +2231,7 @@ HISTORY LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead of network byte order - 2009-10-11 Simon Goldschmidt (Jrg Kesten) + 2009-10-11 Simon Goldschmidt (Jörg Kesten) * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments which are not consecutive when retransmitting unacked segments @@ -335,7 +2409,7 @@ HISTORY 2009-05-04 Simon Goldschmidt * init.c: snmp was not initialized in lwip_init() - 2009-05-04 Frdric Bernon + 2009-05-04 Frédéric Bernon * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled. 2009-05-03 Simon Goldschmidt @@ -355,7 +2429,7 @@ HISTORY 2009-05-01 Simon Goldschmidt * ppp.c: bug #24228: Memory corruption with PPP and DHCP - 2009-04-29 Frdric Bernon + 2009-04-29 Frédéric Bernon * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception of broadcast packets even when this option wasn't set. Port maintainers @@ -377,7 +2451,7 @@ HISTORY when debugging": memp_sizes contained the wrong sizes (including sanity regions); memp pools for MEM_USE_POOLS were too small - 2009-04-24 Simon Goldschmidt, Frdric Bernon + 2009-04-24 Simon Goldschmidt, Frédéric Bernon * inet.c: patch #6765: Fix a small problem with the last changes (incorrect behavior, with with ip address string not ended by a '\0', a space or a end of line) @@ -487,7 +2561,7 @@ HISTORY 2008-12-19 Simon Goldschmidt * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 - 2008-12-10 Tamas Somogyi, Frdric Bernon + 2008-12-10 Tamas Somogyi, Frédéric Bernon * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and port uses deleted netbuf. @@ -521,7 +2595,7 @@ HISTORY * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when tcp_close returns != ERR_OK) - 2008-07-08 Frdric Bernon + 2008-07-08 Frédéric Bernon * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters in macros, mainly if MEM_STATS=0 and MEMP_STATS=0). @@ -569,39 +2643,39 @@ HISTORY * inet_chksum.c: Allow choice of one of the sample algorithms to be made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM. - 2008-01-22 Frdric Bernon + 2008-01-22 Frédéric Bernon * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names. - 2008-01-14 Frdric Bernon + 2008-01-14 Frédéric Bernon * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the tcp_recv callback (see rawapi.txt). - 2008-01-14 Frdric Bernon, Marc Chaland + 2008-01-14 Frédéric Bernon, Marc Chaland * ip.c: Integrate patch #6369" ip_input : checking before realloc". - 2008-01-12 Frdric Bernon + 2008-01-12 Frédéric Bernon * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field netconn::sem per netconn::op_completed like suggested for the task #7490 "Add return value to sys_mbox_post". - 2008-01-12 Frdric Bernon + 2008-01-12 Frédéric Bernon * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE, DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues sizes), like suggested for the task #7490 "Add return value to sys_mbox_post". - 2008-01-10 Frdric Bernon + 2008-01-10 Frédéric Bernon * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490 "Add return value to sys_mbox_post". tcpip_callback is always defined as "blocking" ("block" parameter = 1). - 2008-01-10 Frdric Bernon + 2008-01-10 Frédéric Bernon * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490 "Add return value to sys_mbox_post". - 2008-01-05 Frdric Bernon + 2008-01-05 Frédéric Bernon * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h: Introduce changes for task #7490 "Add return value to sys_mbox_post" with some modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which @@ -614,7 +2688,7 @@ HISTORY This new function is used in tcpip_input (so, can be called in an interrupt context since the function is not blocking), and in recv_udp and recv_raw. - 2008-01-04 Frdric Bernon, Simon Goldschmidt, Jonathan Larmour + 2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c, tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add @@ -623,31 +2697,31 @@ HISTORY 2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm) * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer - 2007-12-31 Frdric Bernon, Luca Ceresoli + 2007-12-31 Frédéric Bernon, Luca Ceresoli * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets in autoip". The change in etharp_raw could be removed, since all calls to etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be wrong in the future. - 2007-12-30 Frdric Bernon, Tom Evans + 2007-12-30 Frédéric Bernon, Tom Evans * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address Filtering" reported by Tom Evans. - 2007-12-21 Frdric Bernon, Simon Goldschmidt, Jonathan Larmour + 2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c, sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API applications have to call 'tcp_accepted(pcb)' in their accept callback to keep accepting new connections. - 2007-12-13 Frdric Bernon + 2007-12-13 Frédéric Bernon * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result" by err_t type. Add a new err_t code "ERR_INPROGRESS". - 2007-12-12 Frdric Bernon + 2007-12-12 Frédéric Bernon * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles are the one which have ram usage. - 2007-12-05 Frdric Bernon + 2007-12-05 Frédéric Bernon * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static set of variables (=0) or a local one (=1). In this last case, your port should provide a function "struct hostent* sys_thread_hostent( struct hostent* h)" @@ -679,7 +2753,7 @@ HISTORY based on the MTU of the netif used to send. Enabled by default. Disable by setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492. - 2007-11-19 Frdric Bernon + 2007-11-19 Frédéric Bernon * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name received match the name query), implement DNS_USES_STATIC_BUF (the place where copy dns payload to parse the response), return an error if there is no place @@ -696,7 +2770,7 @@ HISTORY dns resolver function for netconn api (netconn_gethostbyname) and socket api (gethostbyname/gethostbyname_r). - 2007-11-15 Jim Pettinato, Frdric Bernon + 2007-11-15 Jim Pettinato, Frédéric Bernon * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name requests with RAW api interface. Initialization is done in lwip_init() with build time options. DNS timer is added in tcpip_thread context. DHCP can set @@ -715,7 +2789,7 @@ HISTORY core header files in api.h (ip/tcp/udp/raw.h) to hide the internal implementation from netconn api applications. - 2007-11-03 Frdric Bernon + 2007-11-03 Frédéric Bernon * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP & RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled by default). Netconn API users can use the netconn_recv_bufsize macro to access @@ -723,14 +2797,14 @@ HISTORY netconn::recv_avail which need to be more "thread-safe" (note there is already the problem for FIONREAD with lwip_ioctl/ioctlsocket). - 2007-11-01 Frdric Bernon, Marc Chaland + 2007-11-01 Frédéric Bernon, Marc Chaland * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c: Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api layer. This option enable to delayed TCP PUSH flag on multiple "write" calls. Note that previous "copy" parameter for "write" APIs is now called "apiflags". - 2007-10-24 Frdric Bernon + 2007-10-24 Frédéric Bernon * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than TCP_EVENT_xxx macros to get a code more readable. It could also help to remove some code (like we have talk in "patch #5919 : Create compile switch to remove @@ -750,23 +2824,23 @@ HISTORY * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so all netifs (or ports) can use it. - 2007-10-05 Frdric Bernon + 2007-10-05 Frédéric Bernon * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the common function to reduce a little bit the footprint (for all functions using only the "netif" parameter). - 2007-10-03 Frdric Bernon + 2007-10-03 Frédéric Bernon * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down, netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce a little bit the footprint (for all functions using only the "netif" parameter). - 2007-09-15 Frdric Bernon + 2007-09-15 Frédéric Bernon * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for IP_MULTICAST_TTL and IP_MULTICAST_IF. - 2007-09-10 Frdric Bernon + 2007-09-10 Frédéric Bernon * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime() each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can @@ -778,7 +2852,7 @@ HISTORY when it's queried (any direct call to "sysuptime" is changed by a call to snmp_get_sysuptime). - 2007-09-09 Frdric Bernon, Bill Florac + 2007-09-09 Frédéric Bernon, Bill Florac * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP, and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags if you want IGMP on an interface. igmp_stop() is now called inside netif_remove(). @@ -786,20 +2860,20 @@ HISTORY LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait the next query message to receive the matching multicast streams). - 2007-09-08 Frdric Bernon + 2007-09-08 Frédéric Bernon * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change). Use this new field to access to common pcb fields (ttl, tos, so_options, etc...). Enable to access to these fields with LWIP_TCP=0. - 2007-09-05 Frdric Bernon + 2007-09-05 Frédéric Bernon * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h, ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default). Be careful, disabling ICMP make your product non-compliant to RFC1122, but help to reduce footprint, and to reduce "visibility" on the Internet. - 2007-09-05 Frdric Bernon, Bill Florac + 2007-09-05 Frédéric Bernon, Bill Florac * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new parameters have to be provided: a task name, and a task stack size. For this @@ -808,11 +2882,11 @@ HISTORY in your sys_arch.c file, and but it's not mandatory, use them in your OS specific functions. - 2007-09-05 Frdric Bernon + 2007-09-05 Frédéric Bernon * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings inside init.c for task #7142 "Sanity check user-configurable values". - 2007-09-04 Frdric Bernon, Bill Florac + 2007-09-04 Frédéric Bernon, Bill Florac * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the value). It will avoid potential fragmentation problems, use a counter to know @@ -820,7 +2894,7 @@ HISTORY leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity check if LWIP_IGMP!=0). - 2007-09-03 Frdric Bernon + 2007-09-03 Frédéric Bernon * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement". Initialize igmp_mac_filter to NULL in netif_add (this field should be set in the netif's "init" function). Use the "imr_interface" field (for socket layer) @@ -828,22 +2902,22 @@ HISTORY The igmp_join/leavegroup first parameter change from a netif to an ipaddr. This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany). - 2007-08-30 Frdric Bernon + 2007-08-30 Frédéric Bernon * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions from api/api_lib". Now netbuf API is independant of netconn, and can be used with other API (application based on raw API, or future "socket2" API). Ports maintainers just have to add src/api/netbuf.c in their makefile/projects. - 2007-08-30 Frdric Bernon, Jonathan Larmour + 2007-08-30 Frédéric Bernon, Jonathan Larmour * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check user-configurable values". - 2007-08-29 Frdric Bernon + 2007-08-29 Frédéric Bernon * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start. igmp_start is call inside netif_add. Now, igmp initialization is in the same spirit than the others modules. Modify some IGMP debug traces. - 2007-08-29 Frdric Bernon + 2007-08-29 Frédéric Bernon * Add init.h, init.c, Change opt.h, tcpip.c: Task #7213 "Add a lwip_init function" Add lwip_init function to regroup all modules initializations, and to provide a place to add code for task #7142 "Sanity check user-configurable values". @@ -858,15 +2932,15 @@ HISTORY since they can under certain circumstances be called with an invalid conn pointer after the connection has been closed (and conn has been freed). - 2007-08-25 Frdric Bernon (Artem Migaev's Patch) + 2007-08-25 Frédéric Bernon (Artem Migaev's Patch) * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up". Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set. - 2007-08-22 Frdric Bernon + 2007-08-22 Frédéric Bernon * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release. - 2007-08-22 Frdric Bernon + 2007-08-22 Frédéric Bernon * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT & ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the name is tcpip_input (we keep the name of 1.2.0 function). @@ -918,13 +2992,13 @@ HISTORY 2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and other stacks. - 2007-07-13 Jared Grubb (integrated by Frdric Bernon) + 2007-07-13 Jared Grubb (integrated by Frédéric Bernon) * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add a link callback in the netif struct, and functions to handle it. Be carefull for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c) if you want to be sure to be compatible with future changes... - 2007-06-30 Frdric Bernon + 2007-06-30 Frédéric Bernon * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions. 2007-06-21 Simon Goldschmidt @@ -961,7 +3035,7 @@ HISTORY * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets to disable UDP checksum generation on transmit. - 2007-06-13 Frdric Bernon, Simon Goldschmidt + 2007-06-13 Frédéric Bernon, Simon Goldschmidt * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid pointers or parameters, and let the possibility to redefined it in cc.h. Use this macro to check "conn" parameter in api_msg.c functions. @@ -974,7 +3048,7 @@ HISTORY by default) to switch off UDP-Lite support if not needed (reduces udp.c code size) - 2007-06-09 Dominik Spies (integrated by Frdric Bernon) + 2007-06-09 Dominik Spies (integrated by Frédéric Bernon) * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h: AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt @@ -995,11 +3069,11 @@ HISTORY (defaulting to off for now) that can be set to 0 to send fragmented packets by passing PBUF_REFs down the stack. - 2007-05-23 Frdric Bernon + 2007-05-23 Frédéric Bernon * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP connections, such present in patch #5959. - 2007-05-23 Frdric Bernon + 2007-05-23 Frédéric Bernon * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx code in only one part... @@ -1016,7 +3090,7 @@ HISTORY PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce code size. - 2007-05-11 Frdric Bernon + 2007-05-11 Frédéric Bernon * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c: Include a function pointer instead of a table index in the message to reduce footprint. Disable some part of lwip_send and lwip_sendto if some options are @@ -1044,7 +3118,7 @@ HISTORY * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending multiple packets to the same host. - 2007-05-04 Frdric Bernon, Jonathan Larmour + 2007-05-04 Frédéric Bernon, Jonathan Larmour * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible to corrupt remote addr/port connection state". Reduce problems "not enought memory" with netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between @@ -1058,12 +3132,12 @@ HISTORY with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro by the port in sys_arch.h if desired. - 2007-04-06 Frdric Bernon, Simon Goldschmidt + 2007-04-06 Frédéric Bernon, Simon Goldschmidt * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp clients, using new functions from netifapi.h. Disable as default (no port change to do). - 2007-04-05 Frdric Bernon + 2007-04-05 Frédéric Bernon * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant. 2007-04-04 Simon Goldschmidt @@ -1071,26 +3145,26 @@ HISTORY use this for and architecture-independent form to tell the compiler you intentionally are not using this variable. Can be overriden in cc.h. - 2007-03-28 Frdric Bernon + 2007-03-28 Frédéric Bernon * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded string, point on one of your's ethernetif field, or alloc a string you will free yourself). It will be used by DHCP to register a client hostname, but can also be use when you call snmp_set_sysname. - 2007-03-28 Frdric Bernon + 2007-03-28 Frédéric Bernon * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to initialize a network interface's flag with. It tell this interface is an ethernet device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility Support for IPv4" section 4.6) when interface is "up" with netif_set_up(). - 2007-03-26 Frdric Bernon, Jonathan Larmour + 2007-03-26 Frédéric Bernon, Jonathan Larmour * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build time if you only use PPP or SLIP. The default is enable. Note we don't have to call etharp_init in your port's initilization sequence if you use tcpip.c, because this call is done in tcpip_init function. - 2007-03-22 Frdric Bernon + 2007-03-22 Frédéric Bernon * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in your lwipopts.h. More, unused counters are not defined in the stats structs, and not @@ -1101,24 +3175,24 @@ HISTORY * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). Provides callback on netif up/down state change. - 2007-03-11 Frdric Bernon, Mace Gael, Steve Reynolds + 2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c, ip.c, netif.h, tcpip.c, opt.h: New configuration option LWIP_IGMP to enable IGMP processing. Based on only one filter per all network interfaces. Declare a new function in netif to enable to control the MAC filter (to reduce lwIP traffic processing). - 2007-03-11 Frdric Bernon + 2007-03-11 Frédéric Bernon * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this unless you know what you're doing (default are RFC1122 compliant). Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds. - 2007-03-08 Frdric Bernon + 2007-03-08 Frédéric Bernon * tcp.h: Keepalive values can be configured at compile time, but don't change this unless you know what you're doing (default are RFC1122 compliant). - 2007-03-08 Frdric Bernon + 2007-03-08 Frédéric Bernon * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h: Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO on UDP sockets/netconn. @@ -1126,7 +3200,7 @@ HISTORY 2007-03-08 Simon Goldschmidt * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time. - 2007-03-06 Frdric Bernon + 2007-03-06 Frédéric Bernon * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: Implement SO_RCVTIMEO on UDP sockets/netconn. @@ -1146,19 +3220,19 @@ HISTORY ++ Bug fixes: - 2008-03-17 Frdric Bernon, Ed Kerekes + 2008-03-17 Frédéric Bernon, Ed Kerekes * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have some problems to fill the IP header on some targets, use now the ip.h macros to do it). - 2008-03-13 Frdric Bernon + 2008-03-13 Frédéric Bernon * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a TCP connection caused a crash. Note that using (lwip_)recvfrom like this is a bit slow and that using (lwip)getpeername is the good lwip way to do it (so, using recv is faster on tcp sockets). - 2008-03-12 Frdric Bernon, Jonathan Larmour + 2008-03-12 Frédéric Bernon, Jonathan Larmour * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's recv_raw() does not consume data", and the ping sample (with LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom @@ -1173,7 +3247,7 @@ HISTORY * Numerous small compiler error/warning fixes from contributions to mailing list after 1.3.0 release candidate made. - 2008-01-25 Cui hengbin (integrated by Frdric Bernon) + 2008-01-25 Cui hengbin (integrated by Frédéric Bernon) * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures. 2008-01-15 Kieran Mansley @@ -1247,7 +3321,7 @@ HISTORY Fixed the nagle algorithm; nagle now also works for all raw API applications and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY' - 2007-11-12 Frdric Bernon + 2007-11-12 Frédéric Bernon * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most of the netconn_peer and netconn_addr processing is done inside tcpip_thread context in do_getaddr. @@ -1279,7 +3353,7 @@ HISTORY 2007-10-08 Simon Goldschmidt * mem.c: lfree was not updated in mem_realloc! - 2007-10-07 Frdric Bernon + 2007-10-07 Frédéric Bernon * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT: this change cause an API breakage for netconn_addr, since a parameter @@ -1299,23 +3373,23 @@ HISTORY 2007-09-15 Mike Kleshov * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used) - 2007-09-06 Frdric Bernon + 2007-09-06 Frédéric Bernon * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h" if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h. - 2007-08-30 Frdric Bernon + 2007-08-30 Frédéric Bernon * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, and fix some coding style. - 2007-08-28 Frdric Bernon + 2007-08-28 Frédéric Bernon * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any kind of packets. These packets are considered like Ethernet packets (payload pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets are considered like IP packets (payload pointing to iphdr). - 2007-08-27 Frdric Bernon + 2007-08-27 Frédéric Bernon * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT). @@ -1324,19 +3398,19 @@ HISTORY * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy compiler (Paradigm C++) - 2007-08-09 Frdric Bernon, Bill Florac + 2007-08-09 Frédéric Bernon, Bill Florac * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement. Introduce IGMP_STATS to centralize statistics management. - 2007-08-09 Frdric Bernon, Bill Florac + 2007-08-09 Frédéric Bernon, Bill Florac * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast packet on a udp pcb binded on an netif's IP address, and not on "any". - 2007-08-09 Frdric Bernon, Bill Florac + 2007-08-09 Frédéric Bernon, Bill Florac * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement. This is mainly on using lookup/lookfor, and some coding styles... - 2007-07-26 Frdric Bernon (and "thedoctor") + 2007-07-26 Frédéric Bernon (and "thedoctor") * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages. 2007-07-25 Simon Goldschmidt @@ -1360,11 +3434,11 @@ HISTORY * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed allocation. It now returns NULL. - 2007-07-13 Frdric Bernon + 2007-07-13 Frédéric Bernon * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in all error cases. - 2007-07-13 Frdric Bernon + 2007-07-13 Frédéric Bernon * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed, because current code doesn't follow rawapi.txt documentation. @@ -1401,13 +3475,13 @@ HISTORY * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if a segment contained chained pbufs) - 2007-06-28 Frdric Bernon + 2007-06-28 Frédéric Bernon * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute a "pseudo-random" value based on netif's MAC and some autoip fields. It's always possible to define this macro in your own lwipopts.h to always use C library's rand(). Note that autoip_create_rand_addr doesn't use this macro. - 2007-06-28 Frdric Bernon + 2007-06-28 Frédéric Bernon * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications in api_lib/api_msg (use pointers and not type with table, etc...) @@ -1432,11 +3506,11 @@ HISTORY -> netconn_new_..() does not allocate a new connection for unsupported protocols. - 2007-06-13 Frdric Bernon, Simon Goldschmidt + 2007-06-13 Frédéric Bernon, Simon Goldschmidt * api_lib.c: change return expression in netconn_addr and netconn_peer, because conn->err was reset to ERR_OK without any reasons (and error was lost)... - 2007-06-13 Frdric Bernon, Matthias Weisser + 2007-06-13 Frédéric Bernon, Matthias Weisser * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid some macro names collision with some OS macros. @@ -1465,13 +3539,13 @@ HISTORY 2007-06-01 Simon Goldschmidt * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread. - 2007-05-23 Frdric Bernon + 2007-05-23 Frédéric Bernon * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only allocated by do_listen if success) and netconn_accept errors handling. In most of api_lib functions, we replace some errors checkings like "if (conn==NULL)" by ASSERT, except for netconn_delete. - 2007-05-23 Frdric Bernon + 2007-05-23 Frédéric Bernon * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return an error code if it's impossible to fetch a pbuf on a TCP connection (and not directly close the recvmbox). @@ -1480,13 +3554,13 @@ HISTORY * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of bound but unconnected (and non-listening) tcp_pcbs. - 2007-05-22 Frdric Bernon + 2007-05-22 Frédéric Bernon * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features like "sys_timeout" in their application threads. - 2007-05-22 Frdric Bernon + 2007-05-22 Frédéric Bernon * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see which parameters are used by which do_xxx function, and to avoid "misusing" parameters (patch #5938). @@ -1510,7 +3584,7 @@ HISTORY as the one of the netif used for sending to prevent sending from old addresses after a netif address gets changed (partly fixes bug #3168). - 2007-05-16 Frdric Bernon + 2007-05-16 Frédéric Bernon * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in tcpip_init) because we have to be sure that network interfaces are already @@ -1574,24 +3648,24 @@ HISTORY "Constant is long" warnings with 16bit compilers. Contributed by avatar@mmlab.cse.yzu.edu.tw - 2007-04-05 Frdric Bernon, Jonathan Larmour + 2007-04-05 Frédéric Bernon, Jonathan Larmour * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on the mailbox is active". Now, the post is only done during a connect, and do_send, do_write and do_join_leave_group don't do anything if a previous error was signaled. - 2007-04-03 Frdric Bernon + 2007-04-03 Frédéric Bernon * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output packets. See patch #5834. - 2007-03-30 Frdric Bernon + 2007-03-30 Frédéric Bernon * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add missing pcb allocations checking (in do_bind, and for each raw_new). Fix style. - 2007-03-30 Frdric Bernon + 2007-03-30 Frédéric Bernon * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with others environment defines (these were too "generic"). - 2007-03-28 Frdric Bernon + 2007-03-28 Frédéric Bernon * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call result and can cause a crash. lwip_send now check netbuf_ref result. @@ -1605,19 +3679,19 @@ HISTORY * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS + IP and TCP headers *and* physical link headers - 2007-03-26 Frdric Bernon (based on patch from Dmitry Potapov) + 2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov) * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause to send some garbage. It is not a definitive solution, but the patch does solve the problem for most cases. - 2007-03-22 Frdric Bernon + 2007-03-22 Frédéric Bernon * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used). - 2007-03-22 Frdric Bernon + 2007-03-22 Frédéric Bernon * api_lib.c: somes resources couldn't be freed if there was errors during netconn_new_with_proto_and_callback. - 2007-03-22 Frdric Bernon + 2007-03-22 Frédéric Bernon * ethernetif.c: update netif->input calls to check return value. In older ports, it's a good idea to upgrade them, even if before, there could be another problem (access to an uninitialized mailbox). @@ -1626,17 +3700,17 @@ HISTORY * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed by casting to unsigned). - 2007-03-21 Frdric Bernon + 2007-03-21 Frédéric Bernon * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call. Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a faster and more reliable communication between api_lib and tcpip. - 2007-03-21 Frdric Bernon + 2007-03-21 Frédéric Bernon * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0. - 2007-03-21 Frdric Bernon + 2007-03-21 Frédéric Bernon * api_msg.c, igmp.c, igmp.h: Fix C++ style comments 2007-03-21 Kieran Mansley @@ -1653,11 +3727,11 @@ HISTORY * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and comment out missing header include in icmp.c - 2007-03-20 Frdric Bernon + 2007-03-20 Frédéric Bernon * memp.h, stats.c: Fix stats_display function where memp_names table wasn't synchronized with memp.h. - 2007-03-20 Frdric Bernon + 2007-03-20 Frédéric Bernon * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input, tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with network interfaces. Also fix a compiler warning. @@ -1666,11 +3740,11 @@ HISTORY * udp.c: Only try and use pbuf_header() to make space for headers if not a ROM or REF pbuf. - 2007-03-19 Frdric Bernon + 2007-03-19 Frédéric Bernon * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg() and api_msg_post(). - 2007-03-19 Frdric Bernon + 2007-03-19 Frédéric Bernon * Remove unimplemented "memp_realloc" function from memp.h. 2007-03-11 Simon Goldschmidt @@ -1682,7 +3756,7 @@ HISTORY (missing `const' qualifier in socket functions), to get more compatible to standard POSIX sockets. - 2007-03-11 Frdric Bernon (based on patch from Dmitry Potapov) + 2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov) * sockets.c: Add asserts inside bind, connect and sendto to check input parameters. Remove excessive set_errno() calls after get_socket(), because errno is set inside of get_socket(). Move last sock_set_errno() inside @@ -1696,7 +3770,7 @@ HISTORY * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect the stack from concurrent access. - 2007-03-06 Frdric Bernon, Dmitry Potapov + 2007-03-06 Frédéric Bernon, Dmitry Potapov * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input(). @@ -1704,7 +3778,7 @@ HISTORY * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files if IP_FRAG == 0 and IP_REASSEMBLY == 0 - 2007-03-06 Frdric Bernon, Simon Goldschmidt + 2007-03-06 Frédéric Bernon, Simon Goldschmidt * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput. Allow to do ARP processing for incoming packets inside tcpip_thread @@ -1716,15 +3790,15 @@ HISTORY * err.h, err.c: fixed compiler warning "initialization dircards qualifiers from pointer target type" - 2007-03-05 Frdric Bernon + 2007-03-05 Frédéric Bernon * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES, ETHARP_TRUST_IP_MAC, review SO_REUSE) - 2007-03-04 Frdric Bernon + 2007-03-04 Frédéric Bernon * api_msg.c: Remove some compiler warnings : parameter "pcb" was never referenced. - 2007-03-04 Frdric Bernon + 2007-03-04 Frédéric Bernon * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from Dmitry Potapov). The api_msg struct stay on the stack (not moved to netconn struct). @@ -1738,7 +3812,7 @@ HISTORY * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt existing pbuf chain when enqueuing multiple pbufs to a pending ARP request - 2007-03-03 Frdric Bernon + 2007-03-03 Frédéric Bernon * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;" It is static, and never used in udp.c except udp_init(). @@ -1747,7 +3821,7 @@ HISTORY tcpip_thread() to tcpip_init(). This way, raw API connections can be initialized before tcpip_thread is running (e.g. before OS is started) - 2007-03-02 Frdric Bernon + 2007-03-02 Frédéric Bernon * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call interval. diff --git a/components/net/lwip-2.1.0/CMakeLists.txt b/components/net/lwip-2.1.0/CMakeLists.txt new file mode 100644 index 0000000000..f05c0f6160 --- /dev/null +++ b/components/net/lwip-2.1.0/CMakeLists.txt @@ -0,0 +1,20 @@ +cmake_minimum_required(VERSION 3.7) + +project(lwIP) + +set(LWIP_DIR ${CMAKE_CURRENT_SOURCE_DIR}) +include(src/Filelists.cmake) + +# Package generation +set(CPACK_SOURCE_GENERATOR "ZIP") +set(CPACK_SOURCE_PACKAGE_DESCRIPTION_SUMMARY "lwIP lightweight IP stack") +set(CPACK_PACKAGE_VERSION_MAJOR "${LWIP_VERSION_MAJOR}") +set(CPACK_PACKAGE_VERSION_MINOR "${LWIP_VERSION_MINOR}") +set(CPACK_PACKAGE_VERSION_PATCH "${LWIP_VERSION_REVISION}") +set(CPACK_SOURCE_IGNORE_FILES "/build/;${CPACK_SOURCE_IGNORE_FILES};.git") +set(CPACK_SOURCE_PACKAGE_FILE_NAME "lwip-${LWIP_VERSION_MAJOR}.${LWIP_VERSION_MINOR}.${LWIP_VERSION_REVISION}") +include(CPack) + +# Target for package generation +add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) +add_dependencies(dist lwipdocs) diff --git a/components/net/lwip-1.3.2/COPYING b/components/net/lwip-2.1.0/COPYING similarity index 100% rename from components/net/lwip-1.3.2/COPYING rename to components/net/lwip-2.1.0/COPYING diff --git a/components/net/lwip-2.1.0/FEATURES b/components/net/lwip-2.1.0/FEATURES new file mode 100644 index 0000000000..a50c5a5e3b --- /dev/null +++ b/components/net/lwip-2.1.0/FEATURES @@ -0,0 +1,11 @@ +lwIP is a small independent implementation of the TCP/IP protocol suite targeted at embedded systems. + +The focus of the lwIP TCP/IP implementation is to reduce resource usage while still having a full scale TCP. This makes lwIP suitable for use in embedded systems with tens of kilobytes of free RAM and room for around 40 kilobytes of code ROM. + +Main features include: +- Protocols: IP, IPv6, ICMP, ND, MLD, UDP, TCP, IGMP, ARP, PPPoS, PPPoE, 6LowPAN (via IEEE 802.15.4, BLE or ZEP; since v2.1.0) +- DHCP client, stateless DHCPv6 (since v2.1.0), DNS client (incl. mDNS hostname resolver), AutoIP/APIPA (Zeroconf), SNMP agent (v1, v2c, v3 (since v2.1.0), private MIB support & MIB compiler) +- APIs: specialized APIs for enhanced performance & zero copy, optional Berkeley-alike socket API +- Extended features: IP forwarding over multiple network interfaces +- Extended TCP features: congestion control, RTT estimation and fast recovery/fast retransmit, sending SACKs (since v2.1.0), "altcp": nearly transparent TLS for any tcp pcb (since v2.1.0) +- Addon applications: HTTP server (HTTPS via altcp), HTTP(S) client (since v2.1.0), SNTP client, SMTP client (SMTPS via altcp), ping, NetBIOS nameserver, mDNS responder, MQTT client (TLS support since v2.1.0), TFTP server, iPerf2 counterpart diff --git a/components/net/lwip-1.3.2/FILES b/components/net/lwip-2.1.0/FILES similarity index 66% rename from components/net/lwip-1.3.2/FILES rename to components/net/lwip-2.1.0/FILES index 66253196f9..e6e09989d9 100644 --- a/components/net/lwip-1.3.2/FILES +++ b/components/net/lwip-2.1.0/FILES @@ -1,4 +1,5 @@ src/ - The source code for the lwIP TCP/IP stack. doc/ - The documentation for lwIP. +test/ - Some code to test whether the sources do what they should. See also the FILES file in each subdirectory. diff --git a/components/net/lwip-2.1.0/README b/components/net/lwip-2.1.0/README new file mode 100644 index 0000000000..b95f1552e6 --- /dev/null +++ b/components/net/lwip-2.1.0/README @@ -0,0 +1,106 @@ +INTRODUCTION + +lwIP is a small independent implementation of the TCP/IP protocol suite. + +The focus of the lwIP TCP/IP implementation is to reduce the RAM usage +while still having a full scale TCP. This making lwIP suitable for use +in embedded systems with tens of kilobytes of free RAM and room for +around 40 kilobytes of code ROM. + +lwIP was originally developed by Adam Dunkels at the Computer and Networks +Architectures (CNA) lab at the Swedish Institute of Computer Science (SICS) +and is now developed and maintained by a worldwide network of developers. + +FEATURES + + * IP (Internet Protocol, IPv4 and IPv6) including packet forwarding over + multiple network interfaces + * ICMP (Internet Control Message Protocol) for network maintenance and debugging + * IGMP (Internet Group Management Protocol) for multicast traffic management + * MLD (Multicast listener discovery for IPv6). Aims to be compliant with + RFC 2710. No support for MLDv2 + * ND (Neighbor discovery and stateless address autoconfiguration for IPv6). + Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 + (Address autoconfiguration) + * DHCP, AutoIP/APIPA (Zeroconf) and (stateless) DHCPv6 + * UDP (User Datagram Protocol) including experimental UDP-lite extensions + * TCP (Transmission Control Protocol) with congestion control, RTT estimation + fast recovery/fast retransmit and sending SACKs + * raw/native API for enhanced performance + * Optional Berkeley-like socket API + * TLS: optional layered TCP ("altcp") for nearly transparent TLS for any + TCP-based protocol (ported to mbedTLS) (see changelog for more info) + * PPPoS and PPPoE (Point-to-point protocol over Serial/Ethernet) + * DNS (Domain name resolver incl. mDNS) + * 6LoWPAN (via IEEE 802.15.4, BLE or ZEP) + + +APPLICATIONS + + * HTTP server with SSI and CGI (HTTPS via altcp) + * SNMPv2c agent with MIB compiler (Simple Network Management Protocol), v3 via altcp + * SNTP (Simple network time protocol) + * NetBIOS name service responder + * MDNS (Multicast DNS) responder + * iPerf server implementation + * MQTT client (TLS support via altcp) + + +LICENSE + +lwIP is freely available under a BSD license. + + +DEVELOPMENT + +lwIP has grown into an excellent TCP/IP stack for embedded devices, +and developers using the stack often submit bug fixes, improvements, +and additions to the stack to further increase its usefulness. + +Development of lwIP is hosted on Savannah, a central point for +software development, maintenance and distribution. Everyone can +help improve lwIP by use of Savannah's interface, Git and the +mailing list. A core team of developers will commit changes to the +Git source tree. + +The lwIP TCP/IP stack is maintained in the 'lwip' Git module and +contributions (such as platform ports) are in the 'contrib' Git module. + +See doc/savannah.txt for details on Git server access for users and +developers. + +The current Git trees are web-browsable: + http://git.savannah.gnu.org/cgit/lwip.git + http://git.savannah.gnu.org/cgit/lwip/lwip-contrib.git + +Submit patches and bugs via the lwIP project page: + http://savannah.nongnu.org/projects/lwip/ + +Continuous integration builds (GCC, clang): + https://travis-ci.org/yarrick/lwip-merged + + +DOCUMENTATION + +Self documentation of the source code is regularly extracted from the current +Git sources and is available from this web page: + http://www.nongnu.org/lwip/ + +There is now a constantly growing wiki about lwIP at + http://lwip.wikia.com/wiki/LwIP_Wiki + +Also, there are mailing lists you can subscribe at + http://savannah.nongnu.org/mail/?group=lwip +plus searchable archives: + http://lists.nongnu.org/archive/html/lwip-users/ + http://lists.nongnu.org/archive/html/lwip-devel/ + +lwIP was originally written by Adam Dunkels: + http://dunkels.com/adam/ + +Reading Adam's papers, the files in docs/, browsing the source code +documentation and browsing the mailing list archives is a good way to +become familiar with the design of lwIP. + +Adam Dunkels +Leon Woestenberg diff --git a/components/net/lwip-2.1.0/SConscript b/components/net/lwip-2.1.0/SConscript new file mode 100644 index 0000000000..22c56be1b9 --- /dev/null +++ b/components/net/lwip-2.1.0/SConscript @@ -0,0 +1,268 @@ +from building import * + +# get current directory +cwd = GetCurrentDir() + +# 1. The minimum set of files needed for lwIP. +lwipcore_SRCS = Split(""" +src/core/init.c +src/core/def.c +src/core/dns.c +src/core/inet_chksum.c +src/core/ip.c +src/core/memp.c +src/core/netif.c +src/core/pbuf.c +src/core/raw.c +src/core/stats.c +src/core/sys.c +src/core/tcp.c +src/core/tcp_in.c +src/core/tcp_out.c +src/core/timeouts.c +src/core/udp.c +""") + +# 1.1 +lwipcore_altcp_SRCS = Split(""" +src/core/altcp.c +src/core/altcp_alloc.c +src/core/altcp_tcp.c +""") + +# 1.2 +lwipcore4_SRCS = Split(""" +src/core/ipv4/autoip.c +src/core/ipv4/dhcp.c +src/core/ipv4/etharp.c +src/core/ipv4/icmp.c +src/core/ipv4/igmp.c +src/core/ipv4/ip4_frag.c +src/core/ipv4/ip4.c +src/core/ipv4/ip4_addr.c +""") + +# 1.3 +lwipcore6_SRCS = Split(""" +src/core/ipv6/dhcp6.c +src/core/ipv6/ethip6.c +src/core/ipv6/icmp6.c +src/core/ipv6/inet6.c +src/core/ipv6/ip6.c +src/core/ipv6/ip6_addr.c +src/core/ipv6/ip6_frag.c +src/core/ipv6/mld6.c +src/core/ipv6/nd6.c +""") + +# 2. APIFILES: The files which implement the sequential and socket APIs. +lwipapi_SRCS = Split(""" +src/api/api_lib.c +src/api/api_msg.c +src/api/err.c +src/api/if_api.c +src/api/netbuf.c +src/api/netdb.c +src/api/netifapi.c +src/api/sockets.c +src/api/tcpip.c +""") + +# 3. Files implementing various generic network interface functions +lwipnetif_SRCS = Split(""" +src/netif/ethernet.c +src/netif/ethernetif.c +""") + +# 3.1 Files implementing an IEEE 802.1D bridge by using a multilayer netif approach +lwipnetif_bridgeif_SRCS = Split(""" +src/netif/bridgeif.c +src/netif/bridgeif_fdb.c +""") + +# 3.2 A generic implementation of the SLIP (Serial Line IP) protocol. +lwipnetif_slipif_SRCS = Split(""" +src/netif/slipif.c +""") + +# 4. 6LoWPAN +lwipsixlowpan_SRCS = Split(""" +src/netif/lowpan6.c +""") + +# 4.1 A 6LoWPAN over Bluetooth Low Energy (BLE) implementation as netif, +# according to RFC-7668. +lwipsixlowpan_ble_SRCS = Split(""" +src/netif/lowpan6_ble.c +""") + +# 4.2 Common 6LowPAN routines for IPv6. +lwipsixlowpan_ipv6_SRCS = Split(""" +src/netif/lowpan6_common.c +""") + +# 4.3 A netif implementing the ZigBee Encapsulation Protocol (ZEP). +lwipsixlowpan_zep_SRCS = Split(""" +src/netif/zepif.c +""") + +# 5. PPP +lwipppp_SRCS = Split(""" +src/netif/ppp/auth.c +src/netif/ppp/ccp.c +src/netif/ppp/chap-md5.c +src/netif/ppp/chap_ms.c +src/netif/ppp/chap-new.c +src/netif/ppp/demand.c +src/netif/ppp/eap.c +src/netif/ppp/ecp.c +src/netif/ppp/eui64.c +src/netif/ppp/fsm.c +src/netif/ppp/ipcp.c +src/netif/ppp/ipv6cp.c +src/netif/ppp/lcp.c +src/netif/ppp/magic.c +src/netif/ppp/mppe.c +src/netif/ppp/multilink.c +src/netif/ppp/ppp.c +src/netif/ppp/pppapi.c +src/netif/ppp/pppcrypt.c +src/netif/ppp/pppoe.c +src/netif/ppp/pppol2tp.c +src/netif/ppp/pppos.c +src/netif/ppp/upap.c +src/netif/ppp/utils.c +src/netif/ppp/vj.c +src/netif/ppp/polarssl/arc4.c +src/netif/ppp/polarssl/des.c +src/netif/ppp/polarssl/md4.c +src/netif/ppp/polarssl/md5.c +src/netif/ppp/polarssl/sha1.c +""") + +# 6. SNMPv3 agent +lwipsnmp_SRCS = Split(""" +src/apps/snmp/snmp_asn1.c +src/apps/snmp/snmp_core.c +src/apps/snmp/snmp_mib2.c +src/apps/snmp/snmp_mib2_icmp.c +src/apps/snmp/snmp_mib2_interfaces.c +src/apps/snmp/snmp_mib2_ip.c +src/apps/snmp/snmp_mib2_snmp.c +src/apps/snmp/snmp_mib2_system.c +src/apps/snmp/snmp_mib2_tcp.c +src/apps/snmp/snmp_mib2_udp.c +src/apps/snmp/snmp_snmpv2_framework.c +src/apps/snmp/snmp_snmpv2_usm.c +src/apps/snmp/snmp_msg.c +src/apps/snmp/snmpv3.c +src/apps/snmp/snmp_netconn.c +src/apps/snmp/snmp_pbuf_stream.c +src/apps/snmp/snmp_raw.c +src/apps/snmp/snmp_scalar.c +src/apps/snmp/snmp_table.c +src/apps/snmp/snmp_threadsync.c +src/apps/snmp/snmp_traps.c +""") + +# 7. HTTP server + client +lwiphttp_SRCS = Split(""" +src/apps/http/altcp_proxyconnect.c +src/apps/http/fs.c +src/apps/http/http_client.c +src/apps/http/httpd.c +""") + +# 8. MAKEFSDATA HTTP server host utility +lwipmakefsdata_SRCS = Split(""" +src/apps/http/makefsdata/makefsdata.c +""") + +# 9. IPERF server +lwipiperf_SRCS = Split(""" +src/apps/lwiperf/lwiperf.c +""") + +# 10. SMTP client +lwipsmtp_SRCS = Split(""" +src/apps/smtp/smtp.c +""") + +# 11. SNTP client +lwipsntp_SRCS = Split(""" +src/apps/sntp/sntp.c +""") + +# 12. MDNS responder +lwipmdns_SRCS = Split(""" +src/apps/mdns/mdns.c +""") + +# 13. NetBIOS name server +lwipnetbios_SRCS = Split(""" +src/apps/netbiosns/netbiosns.c +""") + +# 14. TFTP server files +lwiptftp_SRCS = Split(""" +src/apps/tftp/tftp_server.c +src/apps/tftp/tftp_port.c +""") + +# 15. MQTT client files +lwipmqtt_SRCS = Split(""" +src/apps/mqtt/mqtt.c +""") + +# 16. ARM MBEDTLS related files of lwIP rep +lwipmbedtls_SRCS = Split(""" +src/apps/altcp_tls/altcp_tls_mbedtls.c +src/apps/altcp_tls/altcp_tls_mbedtls_mem.c +src/apps/snmp/snmpv3_mbedtls.c +""") + +# 17. ping +lwipping_SRCS = Split(""" +src/apps/ping/ping.c +""") + +src = Split(""" +src/arch/sys_arch.c +""") + +src += lwipcore_SRCS # rm mem.c +src += lwipcore_altcp_SRCS +src += lwipapi_SRCS +src += lwipnetif_SRCS +src += lwipsixlowpan_SRCS + +src += lwipcore4_SRCS + +path = [cwd + '/src', + cwd + '/src/include', + cwd + '/src/arch/include', + cwd + '/src/include/netif'] + +if not GetDepend('RT_USING_SAL'): + path += [cwd + '/src/include/compat/posix'] + +if GetDepend(['RT_LWIP_SNMP']): + src += lwipsnmp_SRCS + path += [cwd + '/src/apps/snmp'] + +if GetDepend(['RT_LWIP_PPP']): + src += lwipppp_SRCS + path += [cwd + '/src/netif/ppp'] + +if GetDepend(['RT_USING_LWIP_IPV6']): + src += lwipcore6_SRCS + +if GetDepend(['RT_USING_NETUTILS']): + if GetDepend(['RT_NETUTILS_USING_TFTP']): + src += lwiptftp_SRCS + if GetDepend(['RT_NETUTILS_USING_PING']): + src += lwipping_SRCS + +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP210'], CPPPATH = path) + +Return('group') diff --git a/components/net/lwip-2.1.0/UPGRADING b/components/net/lwip-2.1.0/UPGRADING new file mode 100644 index 0000000000..21ad8cc3d2 --- /dev/null +++ b/components/net/lwip-2.1.0/UPGRADING @@ -0,0 +1,278 @@ +This file lists major changes between release versions that require +ports or applications to be changed. Use it to update a port or an +application written for an older version of lwIP to correctly work +with newer versions. + + +(git master) + + * [Enter new changes just after this line - do not remove this line] + +(2.1.0) + + ++ Application changes: + + * Use the new altcp API for seamless TLS integration into existing TCP applications (see changelog) + * TCP only kills existing connections with a LOWER priority than the one currently being opened. + Previous implementations also kill existing connections of the SAME priority. + * ip4_route_src: parameter order is reversed: ip4_route_src(dest, src) -> ip4_route_src(src, dest) + to make parameter order consistent with other ip*_route*() functions. + Same also applies to LWIP_HOOK_IP4_ROUTE_SRC() parameter order. + * pbuf API: pbuf->type (an u8_t holding the enum 'pbuf_type') has changed to only hold a + description of the pbuf (e.g. data following pbuf struct, data volatile, allocation + source heap/pool/etc.). As a consequence, applications can't test pbuf->type any more. + Use pbuf_match_type(pbuf, type) instead. + * socket API: according to the standard, SO_ERROR now only returns asynchronous errors. + All other/normal/synchronous errors are (and always were) available via 'errno'. + LWIP_SOCKET_SET_ERRNO has been removed - 'errno' is always set - and required! + * httpd LWIP_HTTPD_CGI_SSI: httpd_cgi_handler() has an additional parameter "struct fs_file *" + + ++ Port changes: + + * tcpip_trycallback() was renamed to tcpip_callbackmsg_trycallback() to avoid confusion + with tcpip_try_callback() + * compatibility headers: moved from 'src/include/posix' to 'src/include/compat/posix', + 'src/include/compat/stdc' etc. + * The IPv6 implementation now supports address scopes. (See LWIP_IPV6_SCOPES documentation + and ip6_zone.h for more documentation) + * LWIP_HOOK_DHCP_APPEND_OPTIONS() has changed, see description in opt.h (options_out_len is not + available in struct dhcp any more) + * Added debug helper asserts to ensure threading/locking requirements are met (define + LWIP_MARK_TCPIP_THREAD() and LWIP_ASSERT_CORE_LOCKED()). + * Added sys_mbox_trypost_fromisr() and tcpip_callbackmsg_trycallback_fromisr() + These can be used to post preallocated messages from an ISR to the tcpip thread + (e.g. when using FreeRTOS) + +(2.0.2) + + ++ Application changes: + + * slipif: The way to pass serial port number has changed. netif->num is not + supported any more, netif->state is interpreted as an u8_t port number now + (it's not a POINTER to an u8_t any more!) + +(2.0.1) + + ++ Application changes: + + * UDP does NOT receive multicast traffic from ALL netifs on an UDP PCB bound to a specific + netif any more. Users need to bind to IP_ADDR_ANY to receive multicast traffic and compare + ip_current_netif() to the desired netif for every packet. + See bug #49662 for an explanation. + +(2.0.0) + + ++ Application changes: + + * Changed netif "up" flag handling to be an administrative flag (as opposed to the previous meaning of + "ip4-address-valid", a netif will now not be used for transmission if not up) -> even a DHCP netif + has to be set "up" before starting the DHCP client + * Added IPv6 support (dual-stack or IPv4/IPv6 only) + * Changed ip_addr_t to be a union in dual-stack mode (use ip4_addr_t where referring to IPv4 only). + * Major rewrite of SNMP (added MIB parser that creates code stubs for custom MIBs); + supports SNMPv2c (experimental v3 support) + * Moved some core applications from contrib repository to src/apps (and include/lwip/apps) + + +++ Raw API: + * Changed TCP listen backlog: removed tcp_accepted(), added the function pair tcp_backlog_delayed()/ + tcp_backlog_accepted() to explicitly delay backlog handling on a connection pcb + + +++ Socket API: + * Added an implementation for posix sendmsg() + * Added LWIP_FIONREAD_LINUXMODE that makes ioctl/FIONREAD return the size of the next pending datagram + + ++ Port changes + + +++ new files: + * MANY new and moved files! + * Added src/Filelists.mk for use in Makefile projects + * Continued moving stack-internal parts from abc.h to abc_priv.h in sub-folder "priv" + to let abc.h only contain the actual application programmer's API + + +++ sys layer: + * Made LWIP_TCPIP_CORE_LOCKING==1 the default as it usually performs better than + the traditional message passing (although with LWIP_COMPAT_MUTEX you are still + open to priority inversion, so this is not recommended any more) + * Added LWIP_NETCONN_SEM_PER_THREAD to use one "op_completed" semaphore per thread + instead of using one per netconn (these semaphores are used even with core locking + enabled as some longer lasting functions like big writes still need to delay) + * Added generalized abstraction for itoa(), strnicmp(), stricmp() and strnstr() + in def.h (to be overridden in cc.h) instead of config + options for netbiosns, httpd, dns, etc. ... + * New abstraction for hton* and ntoh* functions in def.h. + To override them, use the following in cc.h: + #define lwip_htons(x) + #define lwip_htonl(x) + + +++ new options: + * TODO + + +++ new pools: + * Added LWIP_MEMPOOL_* (declare/init/alloc/free) to declare private memp pools + that share memp.c code but do not have to be made global via lwippools.h + * Added pools for IPv6, MPU_COMPATIBLE, dns-api, netif-api, etc. + * added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when a memp pool was empty and an item + is now available + + * Signature of LWIP_HOOK_VLAN_SET macro was changed + + * LWIP_DECLARE_MEMORY_ALIGNED() may be used to declare aligned memory buffers (mem/memp) + or to move buffers to dedicated memory using compiler attributes + + * Standard C headers are used to define sized types and printf formatters + (disable by setting LWIP_NO_STDINT_H=1 or LWIP_NO_INTTYPES_H=1 if your compiler + does not support these) + + + ++ Major bugfixes/improvements + + * Added IPv6 support (dual-stack or IPv4/IPv6 only) + * Major rewrite of PPP (incl. keep-up with apache pppd) + see doc/ppp.txt for an upgrading how-to + * Major rewrite of SNMP (incl. MIB parser) + * Fixed timing issues that might have lead to losing a DHCP lease + * Made rx processing path more robust against crafted errors + * TCP window scaling support + * modification of api modules to support FreeRTOS-MPU (don't pass stack-pointers to other threads) + * made DNS client more robust + * support PBUF_REF for RX packets + * LWIP_NETCONN_FULLDUPLEX allows netconn/sockets to be used for reading/writing from separate + threads each (needs LWIP_NETCONN_SEM_PER_THREAD) + * Moved and reordered stats (mainly memp/mib2) + +(1.4.0) + + ++ Application changes: + + * Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for + compatibility to old applications, but will be removed in the future). + + * Renamed mem_realloc() to mem_trim() to prevent confusion with realloc() + + +++ Raw API: + * Changed the semantics of tcp_close() (since it was rather a + shutdown before): Now the application does *NOT* get any calls to the recv + callback (aside from NULL/closed) after calling tcp_close() + + * When calling tcp_abort() from a raw API TCP callback function, + make sure you return ERR_ABRT to prevent accessing unallocated memory. + (ERR_ABRT now means the applicaiton has called tcp_abort!) + + +++ Netconn API: + * Changed netconn_receive() and netconn_accept() to return + err_t, not a pointer to new data/netconn. + + +++ Socket API: + * LWIP_SO_RCVTIMEO: when accept() or recv() time out, they + now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT. + + * Added a minimal version of posix fctl() to have a + standardised way to set O_NONBLOCK for nonblocking sockets. + + +++ all APIs: + * correctly implemented SO(F)_REUSEADDR + + ++ Port changes + + +++ new files: + + * Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h: + + * Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains + the actual application programmer's API + + * Separated timer implementation from sys.h/.c, moved to timers.h/.c; + Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you + still want to use your own timer implementation for NO_SYS==0 (as before). + + +++ sys layer: + + * Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/ + sys_sem_t; + + * Converted sys_mbox_new/sys_sem_new to take pointers and return err_t; + + * Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use + binary semaphores instead of mutexes - as before) + + +++ new options: + + * Don't waste memory when chaining segments, added option TCP_OVERSIZE to + prevent creating many small pbufs when calling tcp_write with many small + blocks of data. Instead, pbufs are allocated larger than needed and the + space is used for later calls to tcp_write. + + * Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs + in tcp_write/udp_send. + + * Added an additional option LWIP_ETHERNET to support ethernet without ARP + (necessary for pure PPPoE) + + * Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may + be used to place these pools into user-defined memory by using external + declaration. + + * Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT + + +++ new pools: + + * Netdb uses a memp pool for allocating memory when getaddrinfo() is called, + so MEMP_NUM_NETDB has to be set accordingly. + + * DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so + MEMP_NUM_LOCALHOSTLIST has to be set accordingly. + + * Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have + to be set accordingly. + + * PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES + has to be set accordingly + + * Integrated loopif into netif.c - loopif does not have to be created by the + port any more, just define LWIP_HAVE_LOOPIF to 1. + + * Added define LWIP_RAND() for lwip-wide randomization (needs to be defined + in cc.h, e.g. used by igmp) + + * Added printf-formatter X8_F to printf u8_t as hex + + * The heap now may be moved to user-defined memory by defining + LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address + + * added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work + with user-allocated structs instead of calling mem_malloc + + * Added const char* name to mem- and memp-stats for easier debugging. + + * Calculate the TCP/UDP checksum while copying to only fetch data once: + Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum + + * Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to + more than one pcb. + + * Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned + off any more, if this is set to 0, only one packet (the most recent one) is + queued (like demanded by RFC 1122). + + + ++ Major bugfixes/improvements + + * Implemented tcp_shutdown() to only shut down one end of a connection + * Implemented shutdown() at socket- and netconn-level + * Added errorset support to select() + improved select speed overhead + * Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x) + * Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1 + * Use macros defined in ip_addr.h to work with IP addresses + * Implemented many nonblocking socket/netconn functions + * Fixed ARP input processing: only add a new entry if a request was directed as us + * mem_realloc() to mem_trim() to prevent confusion with realloc() + * Some improvements for AutoIP (don't route/forward link-local addresses, don't break + existing connections when assigning a routable address) + * Correctly handle remote side overrunning our rcv_wnd in ooseq case + * Removed packing from ip_addr_t, the packed version is now only used in protocol headers + * Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0 + * Added support for static ARP table entries + +(STABLE-1.3.2) + + * initial version of this file diff --git a/components/net/lwip-1.3.2/doc/FILES b/components/net/lwip-2.1.0/doc/FILES similarity index 61% rename from components/net/lwip-1.3.2/doc/FILES rename to components/net/lwip-2.1.0/doc/FILES index 05d356f4f9..e588575085 100644 --- a/components/net/lwip-1.3.2/doc/FILES +++ b/components/net/lwip-2.1.0/doc/FILES @@ -1,6 +1,9 @@ +doxygen/ - Configuration files and scripts to create the lwIP doxygen source + documentation (found at http://www.nongnu.org/lwip/) + savannah.txt - How to obtain the current development source code. contrib.txt - How to contribute to lwIP as a developer. rawapi.txt - The documentation for the core API of lwIP. Also provides an overview about the other APIs and multithreading. -snmp_agent.txt - The documentation for the lwIP SNMP agent. sys_arch.txt - The documentation for a system abstraction layer of lwIP. +ppp.txt - Documentation of the PPP interface for lwIP. diff --git a/components/net/lwip-2.1.0/doc/NO_SYS_SampleCode.c b/components/net/lwip-2.1.0/doc/NO_SYS_SampleCode.c new file mode 100644 index 0000000000..71f1c9f7f2 --- /dev/null +++ b/components/net/lwip-2.1.0/doc/NO_SYS_SampleCode.c @@ -0,0 +1,122 @@ +void +eth_mac_irq() +{ + /* Service MAC IRQ here */ + + /* Allocate pbuf from pool (avoid using heap in interrupts) */ + struct pbuf* p = pbuf_alloc(PBUF_RAW, eth_data_count, PBUF_POOL); + + if(p != NULL) { + /* Copy ethernet frame into pbuf */ + pbuf_take(p, eth_data, eth_data_count); + + /* Put in a queue which is processed in main loop */ + if(!queue_try_put(&queue, p)) { + /* queue is full -> packet loss */ + pbuf_free(p); + } + } +} + +static err_t +netif_output(struct netif *netif, struct pbuf *p) +{ + LINK_STATS_INC(link.xmit); + + /* Update SNMP stats (only if you use SNMP) */ + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); + int unicast = ((p->payload[0] & 0x01) == 0); + if (unicast) { + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + } else { + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + } + + lock_interrupts(); + pbuf_copy_partial(p, mac_send_buffer, p->tot_len, 0); + /* Start MAC transmit here */ + unlock_interrupts(); + + return ERR_OK; +} + +static void +netif_status_callback(struct netif *netif) +{ + printf("netif status changed %s\n", ip4addr_ntoa(netif_ip4_addr(netif))); +} + +static err_t +netif_init(struct netif *netif) +{ + netif->linkoutput = netif_output; + netif->output = etharp_output; + netif->output_ip6 = ethip6_output; + netif->mtu = ETHERNET_MTU; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP | NETIF_FLAG_MLD6; + MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 100000000); + + SMEMCPY(netif->hwaddr, your_mac_address_goes_here, ETH_HWADDR_LEN); + netif->hwaddr_len = ETH_HWADDR_LEN; + + return ERR_OK; +} + +void +main(void) +{ + struct netif netif; + + lwip_init(); + + netif_add(&netif, IP4_ADDR_ANY, IP4_ADDR_ANY, IP4_ADDR_ANY, NULL, netif_init, netif_input); + netif.name[0] = 'e'; + netif.name[1] = '0'; + netif_create_ip6_linklocal_address(&netif, 1); + netif.ip6_autoconfig_enabled = 1; + netif_set_status_callback(&netif, netif_status_callback); + netif_set_default(&netif); + netif_set_up(&netif); + + /* Start DHCP and HTTPD */ + dhcp_start(&netif ); + httpd_init(); + + while(1) { + /* Check link state, e.g. via MDIO communication with PHY */ + if(link_state_changed()) { + if(link_is_up()) { + netif_set_link_up(&netif); + } else { + netif_set_link_down(&netif); + } + } + + /* Check for received frames, feed them to lwIP */ + lock_interrupts(); + struct pbuf* p = queue_try_get(&queue); + unlock_interrupts(); + + if(p != NULL) { + LINK_STATS_INC(link.recv); + + /* Update SNMP stats (only if you use SNMP) */ + MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); + int unicast = ((p->payload[0] & 0x01) == 0); + if (unicast) { + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + } else { + MIB2_STATS_NETIF_INC(netif, ifinnucastpkts); + } + + if(netif.input(p, &netif) != ERR_OK) { + pbuf_free(p); + } + } + + /* Cyclic lwIP timers check */ + sys_check_timeouts(); + + /* your application goes here */ + } +} diff --git a/components/net/lwip-2.1.0/doc/ZeroCopyRx.c b/components/net/lwip-2.1.0/doc/ZeroCopyRx.c new file mode 100644 index 0000000000..0e8219bd28 --- /dev/null +++ b/components/net/lwip-2.1.0/doc/ZeroCopyRx.c @@ -0,0 +1,45 @@ +typedef struct my_custom_pbuf +{ + struct pbuf_custom p; + void* dma_descriptor; +} my_custom_pbuf_t; + +LWIP_MEMPOOL_DECLARE(RX_POOL, 10, sizeof(my_custom_pbuf_t), "Zero-copy RX PBUF pool"); + +void my_pbuf_free_custom(void* p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + + my_custom_pbuf_t* my_puf = (my_custom_pbuf_t*)p; + + // invalidate data cache here - lwIP and/or application may have written into buffer! + // (invalidate is faster than flushing, and noone needs the correct data in the buffer) + invalidate_cpu_cache(p->payload, p->tot_len); + + SYS_ARCH_PROTECT(old_level); + free_rx_dma_descriptor(my_pbuf->dma_descriptor); + LWIP_MEMPOOL_FREE(RX_POOL, my_pbuf); + SYS_ARCH_UNPROTECT(old_level); +} + +void eth_rx_irq() +{ + dma_descriptor* dma_desc = get_RX_DMA_descriptor_from_ethernet(); + my_custom_pbuf_t* my_pbuf = (my_custom_pbuf_t*)LWIP_MEMPOOL_ALLOC(RX_POOL); + + my_pbuf->p.custom_free_function = my_pbuf_free_custom; + my_pbuf->dma_descriptor = dma_desc; + + invalidate_cpu_cache(dma_desc->rx_data, dma_desc->rx_length); + + struct pbuf* p = pbuf_alloced_custom(PBUF_RAW, + dma_desc->rx_length, + PBUF_REF, + &my_pbuf->p, + dma_desc->rx_data, + dma_desc->max_buffer_size); + + if(netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + } +} diff --git a/components/net/lwip-1.3.2/doc/contrib.txt b/components/net/lwip-2.1.0/doc/contrib.txt similarity index 73% rename from components/net/lwip-1.3.2/doc/contrib.txt rename to components/net/lwip-2.1.0/doc/contrib.txt index 39596fca33..6f0d7bc516 100644 --- a/components/net/lwip-1.3.2/doc/contrib.txt +++ b/components/net/lwip-2.1.0/doc/contrib.txt @@ -34,30 +34,25 @@ features of Savannah help us not lose users' input. 2.3 Bug reports and patches: 1. Make sure you are reporting bugs or send patches against the latest - sources. (From the latest release and/or the current CVS sources.) + sources. (From the latest release and/or the current Git sources.) 2. If you think you found a bug make sure it's not already filed in the bugtracker at Savannah. 3. If you have a fix put the patch on Savannah. If it is a patch that affects both core and arch specific stuff please separate them so that the core can - be applied separately while leaving the other patch 'open'. The prefered way + be applied separately while leaving the other patch 'open'. The preferred way is to NOT touch archs you can't test and let maintainers take care of them. This is a good way to see if they are used at all - the same goes for unix netifs except tapif. 4. Do not file a bug and post a fix to it to the patch area. Either a bug report or a patch will be enough. If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area. -5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two) - can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded - as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead - for reporting a compiler warning fix. -6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other - trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you - change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than +5. Patches should be specific to a single change or to related changes. Do not mix bugfixes with spelling and other + trivial fixes unless the bugfix is trivial too. Do not reorganize code and rename identifiers in the same patch you + change behaviour if not necessary. A patch is easier to read and understand if it's to the point and short than if it's not to the point and long :) so the chances for it to be applied are greater. 2.4 Platform porters: 1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and you think it could benefit others[1] you might want discuss this on the mailing list. You - can also ask for CVS access to submit and maintain your port in the contrib CVS module. - \ No newline at end of file + can also ask for Git access to submit and maintain your port in the contrib Git module. diff --git a/components/net/lwip-2.1.0/doc/doxygen/generate.bat b/components/net/lwip-2.1.0/doc/doxygen/generate.bat new file mode 100644 index 0000000000..4eab18c7f4 --- /dev/null +++ b/components/net/lwip-2.1.0/doc/doxygen/generate.bat @@ -0,0 +1 @@ +doxygen lwip.Doxyfile diff --git a/components/net/lwip-2.1.0/doc/doxygen/generate.sh b/components/net/lwip-2.1.0/doc/doxygen/generate.sh new file mode 100644 index 0000000000..89344b0e81 --- /dev/null +++ b/components/net/lwip-2.1.0/doc/doxygen/generate.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +doxygen lwip.Doxyfile diff --git a/components/net/lwip-2.1.0/doc/doxygen/lwip.Doxyfile b/components/net/lwip-2.1.0/doc/doxygen/lwip.Doxyfile new file mode 100644 index 0000000000..78cc0f28f7 --- /dev/null +++ b/components/net/lwip-2.1.0/doc/doxygen/lwip.Doxyfile @@ -0,0 +1,2531 @@ +# Doxyfile 1.8.13 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all text +# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv +# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv +# for the list of possible encodings. +# The default value is: UTF-8. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by +# double-quotes, unless you are using Doxywizard) that should identify the +# project for which the documentation is generated. This name is used in the +# title of most generated pages and in a few other places. +# The default value is: My Project. + +PROJECT_NAME = "lwIP" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. This +# could be handy for archiving the generated documentation or if some version +# control system is used. + +PROJECT_NUMBER = "2.1.0" + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer a +# quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = "Lightweight IP stack" + +# With the PROJECT_LOGO tag one can specify a logo or an icon that is included +# in the documentation. The maximum height of the logo should not exceed 55 +# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy +# the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path +# into which the generated documentation will be written. If a relative path is +# entered, it will be relative to the location where doxygen was started. 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Set to NO to disable this. +# The default value is: YES. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief +# description of a member or function before the detailed description +# +# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. +# The default value is: YES. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator that is +# used to form the text in various listings. Each string in this list, if found +# as the leading text of the brief description, will be stripped from the text +# and the result, after processing the whole list, is used as the annotated +# text. Otherwise, the brief description is used as-is. If left blank, the +# following values are used ($name is automatically replaced with the name of +# the entity):The $name class, The $name widget, The $name file, is, provides, +# specifies, contains, represents, a, an and the. + +ABBREVIATE_BRIEF = "The $name class " \ + "The $name widget " \ + "The $name file " \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# doxygen will generate a detailed section even if there is only a brief +# description. +# The default value is: NO. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. 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Set this +# tag to YES if you prefer the old behavior instead. +# +# Note that setting this tag to YES also means that rational rose comments are +# not recognized any more. +# The default value is: NO. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the +# documentation from any documented member that it re-implements. +# The default value is: YES. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new +# page for each member. If set to NO, the documentation of a member will be part +# of the file/class/namespace that contains it. +# The default value is: NO. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. 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Doxygen will then generate output that is more tailored for C. For +# instance, some of the names that are used will be different. The list of all +# members will be omitted, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or +# Python sources only. Doxygen will then generate output that is more tailored +# for that language. For instance, namespaces will be presented as packages, +# qualified scopes will look different, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources. Doxygen will then generate output that is tailored for Fortran. +# The default value is: NO. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. 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For +# instance to make doxygen treat .inc files as Fortran files (default is PHP), +# and .f files as C (default is Fortran), use: inc=Fortran f=C. +# +# Note: For files without extension you can use no_extension as a placeholder. +# +# Note that for custom extensions you also need to set FILE_PATTERNS otherwise +# the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments +# according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you can +# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in +# case of backward compatibilities issues. +# The default value is: YES. + +MARKDOWN_SUPPORT = YES + +# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up +# to that level are automatically included in the table of contents, even if +# they do not have an id attribute. +# Note: This feature currently applies only to Markdown headings. +# Minimum value: 0, maximum value: 99, default value: 0. +# This tag requires that the tag MARKDOWN_SUPPORT is set to YES. + +TOC_INCLUDE_HEADINGS = 0 + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. 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This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. +# The default value is: NO. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. +# The default value is: NO. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: +# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen +# will parse them like normal C++ but will assume all classes use public instead +# of private inheritance when no explicit protection keyword is present. +# The default value is: NO. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. 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Alternatively, this can be done per class using the +# \nosubgrouping command. +# The default value is: YES. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions +# are shown inside the group in which they are included (e.g. using \ingroup) +# instead of on a separate page (for HTML and Man pages) or section (for LaTeX +# and RTF). +# +# Note that this feature does not work in combination with +# SEPARATE_MEMBER_PAGES. +# The default value is: NO. + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions +# with only public data fields or simple typedef fields will be shown inline in +# the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO, structs, classes, and unions are shown on a separate page (for HTML and +# Man pages) or section (for LaTeX and RTF). +# The default value is: NO. + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or +# enum is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically be +# useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. +# The default value is: NO. + +TYPEDEF_HIDES_STRUCT = NO + +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can be +# an expensive process and often the same symbol appears multiple times in the +# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small +# doxygen will become slower. If the cache is too large, memory is wasted. The +# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range +# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 +# symbols. At the end of a run doxygen will report the cache usage and suggest +# the optimal cache size from a speed point of view. +# Minimum value: 0, maximum value: 9, default value: 0. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in +# documentation are documented, even if no documentation was available. Private +# class members and static file members will be hidden unless the +# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. +# Note: This will also disable the warnings about undocumented members that are +# normally produced when WARNINGS is set to YES. +# The default value is: NO. + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will +# be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal +# scope will be included in the documentation. +# The default value is: NO. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be +# included in the documentation. +# The default value is: NO. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined +# locally in source files will be included in the documentation. If set to NO, +# only classes defined in header files are included. Does not have any effect +# for Java sources. +# The default value is: YES. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. If set to YES, local methods, +# which are defined in the implementation section but not in the interface are +# included in the documentation. If set to NO, only methods in the interface are +# included. +# The default value is: NO. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base name of +# the file that contains the anonymous namespace. By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = YES + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO, these classes will be included in the various overviews. This option +# has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = YES + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO, these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO, these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES, upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES, the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will +# append additional text to a page's title, such as Class Reference. If set to +# YES the compound reference will be hidden. +# The default value is: NO. + +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo +# list. This list is created by putting \todo commands in the documentation. +# The default value is: YES. + +GENERATE_TODOLIST = NO + +# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test +# list. This list is created by putting \test commands in the documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES, the +# list will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. See also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO, doxygen will only warn about wrong or incomplete +# parameter documentation, but not about the absence of documentation. +# The default value is: NO. + +WARN_NO_PARAMDOC = NO + +# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when +# a warning is encountered. +# The default value is: NO. + +WARN_AS_ERROR = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text " + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING +# Note: If this tag is empty the current directory is searched. + +INPUT = main_page.h \ + ../../src + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: http://www.gnu.org/software/libiconv) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# read by doxygen. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, +# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, +# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, +# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, +# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf. + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.inc \ + *.m \ + *.mm \ + *.dox + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = ../../src/include/netif/ppp/polarssl + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = ../ \ + ../../ + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = main_page.h + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# function all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see http://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = NO + +# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the +# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the +# cost of reduced performance. This can be particularly helpful with template +# rich C++ code for which doxygen's built-in parser lacks the necessary type +# information. +# Note: The availability of this option depends on whether or not doxygen was +# generated with the -Duse-libclang=ON option for CMake. +# The default value is: NO. + +CLANG_ASSISTED_PARSING = NO + +# If clang assisted parsing is enabled you can provide the compiler with command +# line options that you would normally use when invoking the compiler. Note that +# the include paths will already be set by doxygen for the files and directories +# specified with INPUT and INCLUDE_PATH. +# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. + +CLANG_OPTIONS = + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = NO + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined +# cascading style sheets that are included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefore more robust against future updates. +# Doxygen will copy the style sheet files to the output directory. +# Note: The order of the extra style sheet files is of importance (e.g. the last +# style sheet in the list overrules the setting of the previous ones in the +# list). For an example see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the style sheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# http://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to YES can help to show when doxygen was last run and thus if the +# documentation is up to date. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = NO + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: http://developer.apple.com/tools/xcode/), introduced with +# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = lwip.chm + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler (hhc.exe). If non-empty, +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated +# (YES) or that it should be included in the master .chm file (NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated +# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it +# enables the Previous and Next buttons. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = YES + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 4 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# http://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from http://www.mathjax.org before deployment. +# The default value is: http://cdn.mathjax.org/mathjax/latest. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /